1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) {} 106 }; 107 108 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 109 const llvm::Triple &Triple, 110 StringRef &PlatformName, 111 VersionTuple &PlatformMinVersion) { 112 Builder.defineMacro("__APPLE_CC__", "6000"); 113 Builder.defineMacro("__APPLE__"); 114 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 115 // AddressSanitizer doesn't play well with source fortification, which is on 116 // by default on Darwin. 117 if (Opts.Sanitize.has(SanitizerKind::Address)) 118 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 119 120 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 121 if (!Opts.ObjC1) { 122 // __weak is always defined, for use in blocks and with objc pointers. 123 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 124 Builder.defineMacro("__strong", ""); 125 Builder.defineMacro("__unsafe_unretained", ""); 126 } 127 128 if (Opts.Static) 129 Builder.defineMacro("__STATIC__"); 130 else 131 Builder.defineMacro("__DYNAMIC__"); 132 133 if (Opts.POSIXThreads) 134 Builder.defineMacro("_REENTRANT"); 135 136 // Get the platform type and version number from the triple. 137 unsigned Maj, Min, Rev; 138 if (Triple.isMacOSX()) { 139 Triple.getMacOSXVersion(Maj, Min, Rev); 140 PlatformName = "macosx"; 141 } else { 142 Triple.getOSVersion(Maj, Min, Rev); 143 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 144 } 145 146 // If -target arch-pc-win32-macho option specified, we're 147 // generating code for Win32 ABI. No need to emit 148 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 149 if (PlatformName == "win32") { 150 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 151 return; 152 } 153 154 // Set the appropriate OS version define. 155 if (Triple.isiOS()) { 156 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 157 char Str[6]; 158 Str[0] = '0' + Maj; 159 Str[1] = '0' + (Min / 10); 160 Str[2] = '0' + (Min % 10); 161 Str[3] = '0' + (Rev / 10); 162 Str[4] = '0' + (Rev % 10); 163 Str[5] = '\0'; 164 if (Triple.isTvOS()) 165 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 166 else 167 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 168 Str); 169 170 } else if (Triple.isWatchOS()) { 171 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 172 char Str[6]; 173 Str[0] = '0' + Maj; 174 Str[1] = '0' + (Min / 10); 175 Str[2] = '0' + (Min % 10); 176 Str[3] = '0' + (Rev / 10); 177 Str[4] = '0' + (Rev % 10); 178 Str[5] = '\0'; 179 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 180 } else if (Triple.isMacOSX()) { 181 // Note that the Driver allows versions which aren't representable in the 182 // define (because we only get a single digit for the minor and micro 183 // revision numbers). So, we limit them to the maximum representable 184 // version. 185 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 186 char Str[7]; 187 if (Maj < 10 || (Maj == 10 && Min < 10)) { 188 Str[0] = '0' + (Maj / 10); 189 Str[1] = '0' + (Maj % 10); 190 Str[2] = '0' + std::min(Min, 9U); 191 Str[3] = '0' + std::min(Rev, 9U); 192 Str[4] = '\0'; 193 } else { 194 // Handle versions > 10.9. 195 Str[0] = '0' + (Maj / 10); 196 Str[1] = '0' + (Maj % 10); 197 Str[2] = '0' + (Min / 10); 198 Str[3] = '0' + (Min % 10); 199 Str[4] = '0' + (Rev / 10); 200 Str[5] = '0' + (Rev % 10); 201 Str[6] = '\0'; 202 } 203 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 204 } 205 206 // Tell users about the kernel if there is one. 207 if (Triple.isOSDarwin()) 208 Builder.defineMacro("__MACH__"); 209 210 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 211 } 212 213 template<typename Target> 214 class DarwinTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const override { 218 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 219 this->PlatformMinVersion); 220 } 221 222 public: 223 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 224 // By default, no TLS, and we whitelist permitted architecture/OS 225 // combinations. 226 this->TLSSupported = false; 227 228 if (Triple.isMacOSX()) 229 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 230 else if (Triple.isiOS()) { 231 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 232 if (Triple.getArch() == llvm::Triple::x86_64 || 233 Triple.getArch() == llvm::Triple::aarch64) 234 this->TLSSupported = !Triple.isOSVersionLT(8); 235 else if (Triple.getArch() == llvm::Triple::x86 || 236 Triple.getArch() == llvm::Triple::arm || 237 Triple.getArch() == llvm::Triple::thumb) 238 this->TLSSupported = !Triple.isOSVersionLT(9); 239 } else if (Triple.isWatchOS()) 240 this->TLSSupported = !Triple.isOSVersionLT(2); 241 242 this->MCountName = "\01mcount"; 243 } 244 245 std::string isValidSectionSpecifier(StringRef SR) const override { 246 // Let MCSectionMachO validate this. 247 StringRef Segment, Section; 248 unsigned TAA, StubSize; 249 bool HasTAA; 250 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 251 TAA, HasTAA, StubSize); 252 } 253 254 const char *getStaticInitSectionSpecifier() const override { 255 // FIXME: We should return 0 when building kexts. 256 return "__TEXT,__StaticInit,regular,pure_instructions"; 257 } 258 259 /// Darwin does not support protected visibility. Darwin's "default" 260 /// is very similar to ELF's "protected"; Darwin requires a "weak" 261 /// attribute on declarations that can be dynamically replaced. 262 bool hasProtectedVisibility() const override { 263 return false; 264 } 265 }; 266 267 268 // DragonFlyBSD Target 269 template<typename Target> 270 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 271 protected: 272 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 273 MacroBuilder &Builder) const override { 274 // DragonFly defines; list based off of gcc output 275 Builder.defineMacro("__DragonFly__"); 276 Builder.defineMacro("__DragonFly_cc_version", "100001"); 277 Builder.defineMacro("__ELF__"); 278 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 279 Builder.defineMacro("__tune_i386__"); 280 DefineStd(Builder, "unix", Opts); 281 } 282 public: 283 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 284 : OSTargetInfo<Target>(Triple) { 285 switch (Triple.getArch()) { 286 default: 287 case llvm::Triple::x86: 288 case llvm::Triple::x86_64: 289 this->MCountName = ".mcount"; 290 break; 291 } 292 } 293 }; 294 295 // FreeBSD Target 296 template<typename Target> 297 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 298 protected: 299 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 300 MacroBuilder &Builder) const override { 301 // FreeBSD defines; list based off of gcc output 302 303 unsigned Release = Triple.getOSMajorVersion(); 304 if (Release == 0U) 305 Release = 8; 306 307 Builder.defineMacro("__FreeBSD__", Twine(Release)); 308 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 309 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 310 DefineStd(Builder, "unix", Opts); 311 Builder.defineMacro("__ELF__"); 312 313 // On FreeBSD, wchar_t contains the number of the code point as 314 // used by the character set of the locale. These character sets are 315 // not necessarily a superset of ASCII. 316 // 317 // FIXME: This is wrong; the macro refers to the numerical values 318 // of wchar_t *literals*, which are not locale-dependent. However, 319 // FreeBSD systems apparently depend on us getting this wrong, and 320 // setting this to 1 is conforming even if all the basic source 321 // character literals have the same encoding as char and wchar_t. 322 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 323 } 324 public: 325 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 326 switch (Triple.getArch()) { 327 default: 328 case llvm::Triple::x86: 329 case llvm::Triple::x86_64: 330 this->MCountName = ".mcount"; 331 break; 332 case llvm::Triple::mips: 333 case llvm::Triple::mipsel: 334 case llvm::Triple::ppc: 335 case llvm::Triple::ppc64: 336 case llvm::Triple::ppc64le: 337 this->MCountName = "_mcount"; 338 break; 339 case llvm::Triple::arm: 340 this->MCountName = "__mcount"; 341 break; 342 } 343 } 344 }; 345 346 // GNU/kFreeBSD Target 347 template<typename Target> 348 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 349 protected: 350 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 351 MacroBuilder &Builder) const override { 352 // GNU/kFreeBSD defines; list based off of gcc output 353 354 DefineStd(Builder, "unix", Opts); 355 Builder.defineMacro("__FreeBSD_kernel__"); 356 Builder.defineMacro("__GLIBC__"); 357 Builder.defineMacro("__ELF__"); 358 if (Opts.POSIXThreads) 359 Builder.defineMacro("_REENTRANT"); 360 if (Opts.CPlusPlus) 361 Builder.defineMacro("_GNU_SOURCE"); 362 } 363 public: 364 KFreeBSDTargetInfo(const llvm::Triple &Triple) 365 : OSTargetInfo<Target>(Triple) {} 366 }; 367 368 // Minix Target 369 template<typename Target> 370 class MinixTargetInfo : public OSTargetInfo<Target> { 371 protected: 372 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 373 MacroBuilder &Builder) const override { 374 // Minix defines 375 376 Builder.defineMacro("__minix", "3"); 377 Builder.defineMacro("_EM_WSIZE", "4"); 378 Builder.defineMacro("_EM_PSIZE", "4"); 379 Builder.defineMacro("_EM_SSIZE", "2"); 380 Builder.defineMacro("_EM_LSIZE", "4"); 381 Builder.defineMacro("_EM_FSIZE", "4"); 382 Builder.defineMacro("_EM_DSIZE", "8"); 383 Builder.defineMacro("__ELF__"); 384 DefineStd(Builder, "unix", Opts); 385 } 386 public: 387 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 388 }; 389 390 // Linux target 391 template<typename Target> 392 class LinuxTargetInfo : public OSTargetInfo<Target> { 393 protected: 394 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 395 MacroBuilder &Builder) const override { 396 // Linux defines; list based off of gcc output 397 DefineStd(Builder, "unix", Opts); 398 DefineStd(Builder, "linux", Opts); 399 Builder.defineMacro("__gnu_linux__"); 400 Builder.defineMacro("__ELF__"); 401 if (Triple.isAndroid()) { 402 Builder.defineMacro("__ANDROID__", "1"); 403 unsigned Maj, Min, Rev; 404 Triple.getEnvironmentVersion(Maj, Min, Rev); 405 this->PlatformName = "android"; 406 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 407 } 408 if (Opts.POSIXThreads) 409 Builder.defineMacro("_REENTRANT"); 410 if (Opts.CPlusPlus) 411 Builder.defineMacro("_GNU_SOURCE"); 412 } 413 public: 414 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 415 this->WIntType = TargetInfo::UnsignedInt; 416 417 switch (Triple.getArch()) { 418 default: 419 break; 420 case llvm::Triple::ppc: 421 case llvm::Triple::ppc64: 422 case llvm::Triple::ppc64le: 423 this->MCountName = "_mcount"; 424 break; 425 } 426 } 427 428 const char *getStaticInitSectionSpecifier() const override { 429 return ".text.startup"; 430 } 431 }; 432 433 // NetBSD Target 434 template<typename Target> 435 class NetBSDTargetInfo : public OSTargetInfo<Target> { 436 protected: 437 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 438 MacroBuilder &Builder) const override { 439 // NetBSD defines; list based off of gcc output 440 Builder.defineMacro("__NetBSD__"); 441 Builder.defineMacro("__unix__"); 442 Builder.defineMacro("__ELF__"); 443 if (Opts.POSIXThreads) 444 Builder.defineMacro("_POSIX_THREADS"); 445 446 switch (Triple.getArch()) { 447 default: 448 break; 449 case llvm::Triple::arm: 450 case llvm::Triple::armeb: 451 case llvm::Triple::thumb: 452 case llvm::Triple::thumbeb: 453 Builder.defineMacro("__ARM_DWARF_EH__"); 454 break; 455 } 456 } 457 public: 458 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 459 this->MCountName = "_mcount"; 460 } 461 }; 462 463 // OpenBSD Target 464 template<typename Target> 465 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const override { 469 // OpenBSD defines; list based off of gcc output 470 471 Builder.defineMacro("__OpenBSD__"); 472 DefineStd(Builder, "unix", Opts); 473 Builder.defineMacro("__ELF__"); 474 if (Opts.POSIXThreads) 475 Builder.defineMacro("_REENTRANT"); 476 } 477 public: 478 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 479 this->TLSSupported = false; 480 481 switch (Triple.getArch()) { 482 default: 483 case llvm::Triple::x86: 484 case llvm::Triple::x86_64: 485 case llvm::Triple::arm: 486 case llvm::Triple::sparc: 487 this->MCountName = "__mcount"; 488 break; 489 case llvm::Triple::mips64: 490 case llvm::Triple::mips64el: 491 case llvm::Triple::ppc: 492 case llvm::Triple::sparcv9: 493 this->MCountName = "_mcount"; 494 break; 495 } 496 } 497 }; 498 499 // Bitrig Target 500 template<typename Target> 501 class BitrigTargetInfo : public OSTargetInfo<Target> { 502 protected: 503 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 504 MacroBuilder &Builder) const override { 505 // Bitrig defines; list based off of gcc output 506 507 Builder.defineMacro("__Bitrig__"); 508 DefineStd(Builder, "unix", Opts); 509 Builder.defineMacro("__ELF__"); 510 if (Opts.POSIXThreads) 511 Builder.defineMacro("_REENTRANT"); 512 513 switch (Triple.getArch()) { 514 default: 515 break; 516 case llvm::Triple::arm: 517 case llvm::Triple::armeb: 518 case llvm::Triple::thumb: 519 case llvm::Triple::thumbeb: 520 Builder.defineMacro("__ARM_DWARF_EH__"); 521 break; 522 } 523 } 524 public: 525 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 526 this->MCountName = "__mcount"; 527 } 528 }; 529 530 // PSP Target 531 template<typename Target> 532 class PSPTargetInfo : public OSTargetInfo<Target> { 533 protected: 534 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 535 MacroBuilder &Builder) const override { 536 // PSP defines; list based on the output of the pspdev gcc toolchain. 537 Builder.defineMacro("PSP"); 538 Builder.defineMacro("_PSP"); 539 Builder.defineMacro("__psp__"); 540 Builder.defineMacro("__ELF__"); 541 } 542 public: 543 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 544 }; 545 546 // PS3 PPU Target 547 template<typename Target> 548 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const override { 552 // PS3 PPU defines. 553 Builder.defineMacro("__PPC__"); 554 Builder.defineMacro("__PPU__"); 555 Builder.defineMacro("__CELLOS_LV2__"); 556 Builder.defineMacro("__ELF__"); 557 Builder.defineMacro("__LP32__"); 558 Builder.defineMacro("_ARCH_PPC64"); 559 Builder.defineMacro("__powerpc64__"); 560 } 561 public: 562 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 591 // On PS4, do not honor explicit bit field alignment, 592 // as in "__attribute__((aligned(2))) int b : 1;". 593 this->UseExplicitBitFieldAlignment = false; 594 595 switch (Triple.getArch()) { 596 default: 597 case llvm::Triple::x86_64: 598 this->MCountName = ".mcount"; 599 break; 600 } 601 } 602 }; 603 604 // Solaris target 605 template<typename Target> 606 class SolarisTargetInfo : public OSTargetInfo<Target> { 607 protected: 608 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 609 MacroBuilder &Builder) const override { 610 DefineStd(Builder, "sun", Opts); 611 DefineStd(Builder, "unix", Opts); 612 Builder.defineMacro("__ELF__"); 613 Builder.defineMacro("__svr4__"); 614 Builder.defineMacro("__SVR4"); 615 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 616 // newer, but to 500 for everything else. feature_test.h has a check to 617 // ensure that you are not using C99 with an old version of X/Open or C89 618 // with a new version. 619 if (Opts.C99) 620 Builder.defineMacro("_XOPEN_SOURCE", "600"); 621 else 622 Builder.defineMacro("_XOPEN_SOURCE", "500"); 623 if (Opts.CPlusPlus) 624 Builder.defineMacro("__C99FEATURES__"); 625 Builder.defineMacro("_LARGEFILE_SOURCE"); 626 Builder.defineMacro("_LARGEFILE64_SOURCE"); 627 Builder.defineMacro("__EXTENSIONS__"); 628 Builder.defineMacro("_REENTRANT"); 629 } 630 public: 631 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 632 this->WCharType = this->SignedInt; 633 // FIXME: WIntType should be SignedLong 634 } 635 }; 636 637 // Windows target 638 template<typename Target> 639 class WindowsTargetInfo : public OSTargetInfo<Target> { 640 protected: 641 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 642 MacroBuilder &Builder) const override { 643 Builder.defineMacro("_WIN32"); 644 } 645 void getVisualStudioDefines(const LangOptions &Opts, 646 MacroBuilder &Builder) const { 647 if (Opts.CPlusPlus) { 648 if (Opts.RTTIData) 649 Builder.defineMacro("_CPPRTTI"); 650 651 if (Opts.CXXExceptions) 652 Builder.defineMacro("_CPPUNWIND"); 653 } 654 655 if (Opts.Bool) 656 Builder.defineMacro("__BOOL_DEFINED"); 657 658 if (!Opts.CharIsSigned) 659 Builder.defineMacro("_CHAR_UNSIGNED"); 660 661 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 662 // but it works for now. 663 if (Opts.POSIXThreads) 664 Builder.defineMacro("_MT"); 665 666 if (Opts.MSCompatibilityVersion) { 667 Builder.defineMacro("_MSC_VER", 668 Twine(Opts.MSCompatibilityVersion / 100000)); 669 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 670 // FIXME We cannot encode the revision information into 32-bits 671 Builder.defineMacro("_MSC_BUILD", Twine(1)); 672 673 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 674 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 675 } 676 677 if (Opts.MicrosoftExt) { 678 Builder.defineMacro("_MSC_EXTENSIONS"); 679 680 if (Opts.CPlusPlus11) { 681 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 682 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 683 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 684 } 685 } 686 687 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 688 } 689 690 public: 691 WindowsTargetInfo(const llvm::Triple &Triple) 692 : OSTargetInfo<Target>(Triple) {} 693 }; 694 695 template <typename Target> 696 class NaClTargetInfo : public OSTargetInfo<Target> { 697 protected: 698 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 699 MacroBuilder &Builder) const override { 700 if (Opts.POSIXThreads) 701 Builder.defineMacro("_REENTRANT"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("_GNU_SOURCE"); 704 705 DefineStd(Builder, "unix", Opts); 706 Builder.defineMacro("__ELF__"); 707 Builder.defineMacro("__native_client__"); 708 } 709 710 public: 711 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 712 this->LongAlign = 32; 713 this->LongWidth = 32; 714 this->PointerAlign = 32; 715 this->PointerWidth = 32; 716 this->IntMaxType = TargetInfo::SignedLongLong; 717 this->Int64Type = TargetInfo::SignedLongLong; 718 this->DoubleAlign = 64; 719 this->LongDoubleWidth = 64; 720 this->LongDoubleAlign = 64; 721 this->LongLongWidth = 64; 722 this->LongLongAlign = 64; 723 this->SizeType = TargetInfo::UnsignedInt; 724 this->PtrDiffType = TargetInfo::SignedInt; 725 this->IntPtrType = TargetInfo::SignedInt; 726 // RegParmMax is inherited from the underlying architecture 727 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 728 if (Triple.getArch() == llvm::Triple::arm) { 729 // Handled in ARM's setABI(). 730 } else if (Triple.getArch() == llvm::Triple::x86) { 731 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 732 } else if (Triple.getArch() == llvm::Triple::x86_64) { 733 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 734 } else if (Triple.getArch() == llvm::Triple::mipsel) { 735 // Handled on mips' setDataLayout. 736 } else { 737 assert(Triple.getArch() == llvm::Triple::le32); 738 this->resetDataLayout("e-p:32:32-i64:64"); 739 } 740 } 741 }; 742 743 // WebAssembly target 744 template <typename Target> 745 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 746 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 747 MacroBuilder &Builder) const final { 748 // A common platform macro. 749 if (Opts.POSIXThreads) 750 Builder.defineMacro("_REENTRANT"); 751 // Follow g++ convention and predefine _GNU_SOURCE for C++. 752 if (Opts.CPlusPlus) 753 Builder.defineMacro("_GNU_SOURCE"); 754 } 755 756 // As an optimization, group static init code together in a section. 757 const char *getStaticInitSectionSpecifier() const final { 758 return ".text.__startup"; 759 } 760 761 public: 762 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 763 : OSTargetInfo<Target>(Triple) { 764 this->MCountName = "__mcount"; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 resetDataLayout("e-m:e-i64:64-n32:64"); 1517 ABI = "elfv2"; 1518 } else { 1519 resetDataLayout("E-m:e-i64:64-n32:64"); 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 resetDataLayout("E-m:o-i64:64-n32:64"); 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringR600DoubleOps = 1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1753 1754 static const char *const DataLayoutStringSI = 1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 class AMDGPUTargetInfo : public TargetInfo { 1760 static const Builtin::Info BuiltinInfo[]; 1761 static const char * const GCCRegNames[]; 1762 1763 /// \brief The GPU profiles supported by the AMDGPU target. 1764 enum GPUKind { 1765 GK_NONE, 1766 GK_R600, 1767 GK_R600_DOUBLE_OPS, 1768 GK_R700, 1769 GK_R700_DOUBLE_OPS, 1770 GK_EVERGREEN, 1771 GK_EVERGREEN_DOUBLE_OPS, 1772 GK_NORTHERN_ISLANDS, 1773 GK_CAYMAN, 1774 GK_SOUTHERN_ISLANDS, 1775 GK_SEA_ISLANDS, 1776 GK_VOLCANIC_ISLANDS 1777 } GPU; 1778 1779 bool hasFP64:1; 1780 bool hasFMAF:1; 1781 bool hasLDEXPF:1; 1782 1783 public: 1784 AMDGPUTargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple) { 1786 1787 if (Triple.getArch() == llvm::Triple::amdgcn) { 1788 resetDataLayout(DataLayoutStringSI); 1789 GPU = GK_SOUTHERN_ISLANDS; 1790 hasFP64 = true; 1791 hasFMAF = true; 1792 hasLDEXPF = true; 1793 } else { 1794 resetDataLayout(DataLayoutStringR600); 1795 GPU = GK_R600; 1796 hasFP64 = false; 1797 hasFMAF = false; 1798 hasLDEXPF = false; 1799 } 1800 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1801 UseAddrSpaceMapMangling = true; 1802 } 1803 1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1805 if (GPU <= GK_CAYMAN) 1806 return 32; 1807 1808 switch(AddrSpace) { 1809 default: 1810 return 64; 1811 case 0: 1812 case 3: 1813 case 5: 1814 return 32; 1815 } 1816 } 1817 1818 const char * getClobbers() const override { 1819 return ""; 1820 } 1821 1822 ArrayRef<const char *> getGCCRegNames() const override; 1823 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 return None; 1826 } 1827 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: break; 1832 case 'v': // vgpr 1833 case 's': // sgpr 1834 Info.setAllowsRegister(); 1835 return true; 1836 } 1837 return false; 1838 } 1839 1840 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1841 return llvm::makeArrayRef(BuiltinInfo, 1842 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1843 } 1844 1845 void getTargetDefines(const LangOptions &Opts, 1846 MacroBuilder &Builder) const override { 1847 if (getTriple().getArch() == llvm::Triple::amdgcn) 1848 Builder.defineMacro("__AMDGCN__"); 1849 else 1850 Builder.defineMacro("__R600__"); 1851 1852 if (hasFMAF) 1853 Builder.defineMacro("__HAS_FMAF__"); 1854 if (hasLDEXPF) 1855 Builder.defineMacro("__HAS_LDEXPF__"); 1856 if (hasFP64 && Opts.OpenCL) 1857 Builder.defineMacro("cl_khr_fp64"); 1858 if (Opts.OpenCL) { 1859 if (GPU >= GK_NORTHERN_ISLANDS) { 1860 Builder.defineMacro("cl_khr_byte_addressable_store"); 1861 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1862 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1863 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1864 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1865 } 1866 } 1867 } 1868 1869 BuiltinVaListKind getBuiltinVaListKind() const override { 1870 return TargetInfo::CharPtrBuiltinVaList; 1871 } 1872 1873 bool setCPU(const std::string &Name) override { 1874 GPU = llvm::StringSwitch<GPUKind>(Name) 1875 .Case("r600" , GK_R600) 1876 .Case("rv610", GK_R600) 1877 .Case("rv620", GK_R600) 1878 .Case("rv630", GK_R600) 1879 .Case("rv635", GK_R600) 1880 .Case("rs780", GK_R600) 1881 .Case("rs880", GK_R600) 1882 .Case("rv670", GK_R600_DOUBLE_OPS) 1883 .Case("rv710", GK_R700) 1884 .Case("rv730", GK_R700) 1885 .Case("rv740", GK_R700_DOUBLE_OPS) 1886 .Case("rv770", GK_R700_DOUBLE_OPS) 1887 .Case("palm", GK_EVERGREEN) 1888 .Case("cedar", GK_EVERGREEN) 1889 .Case("sumo", GK_EVERGREEN) 1890 .Case("sumo2", GK_EVERGREEN) 1891 .Case("redwood", GK_EVERGREEN) 1892 .Case("juniper", GK_EVERGREEN) 1893 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1894 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1895 .Case("barts", GK_NORTHERN_ISLANDS) 1896 .Case("turks", GK_NORTHERN_ISLANDS) 1897 .Case("caicos", GK_NORTHERN_ISLANDS) 1898 .Case("cayman", GK_CAYMAN) 1899 .Case("aruba", GK_CAYMAN) 1900 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1901 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1902 .Case("verde", GK_SOUTHERN_ISLANDS) 1903 .Case("oland", GK_SOUTHERN_ISLANDS) 1904 .Case("hainan", GK_SOUTHERN_ISLANDS) 1905 .Case("bonaire", GK_SEA_ISLANDS) 1906 .Case("kabini", GK_SEA_ISLANDS) 1907 .Case("kaveri", GK_SEA_ISLANDS) 1908 .Case("hawaii", GK_SEA_ISLANDS) 1909 .Case("mullins", GK_SEA_ISLANDS) 1910 .Case("tonga", GK_VOLCANIC_ISLANDS) 1911 .Case("iceland", GK_VOLCANIC_ISLANDS) 1912 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1913 .Case("fiji", GK_VOLCANIC_ISLANDS) 1914 .Case("stoney", GK_VOLCANIC_ISLANDS) 1915 .Default(GK_NONE); 1916 1917 if (GPU == GK_NONE) { 1918 return false; 1919 } 1920 1921 // Set the correct data layout 1922 switch (GPU) { 1923 case GK_NONE: 1924 case GK_R600: 1925 case GK_R700: 1926 case GK_EVERGREEN: 1927 case GK_NORTHERN_ISLANDS: 1928 resetDataLayout(DataLayoutStringR600); 1929 hasFP64 = false; 1930 hasFMAF = false; 1931 hasLDEXPF = false; 1932 break; 1933 case GK_R600_DOUBLE_OPS: 1934 case GK_R700_DOUBLE_OPS: 1935 case GK_EVERGREEN_DOUBLE_OPS: 1936 case GK_CAYMAN: 1937 resetDataLayout(DataLayoutStringR600DoubleOps); 1938 hasFP64 = true; 1939 hasFMAF = true; 1940 hasLDEXPF = false; 1941 break; 1942 case GK_SOUTHERN_ISLANDS: 1943 case GK_SEA_ISLANDS: 1944 case GK_VOLCANIC_ISLANDS: 1945 resetDataLayout(DataLayoutStringSI); 1946 hasFP64 = true; 1947 hasFMAF = true; 1948 hasLDEXPF = true; 1949 break; 1950 } 1951 1952 return true; 1953 } 1954 }; 1955 1956 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1957 #define BUILTIN(ID, TYPE, ATTRS) \ 1958 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1959 #include "clang/Basic/BuiltinsAMDGPU.def" 1960 }; 1961 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1962 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1963 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1964 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1965 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1966 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1967 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1968 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1969 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1970 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1971 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1972 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1973 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1974 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1975 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1976 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1977 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1978 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1979 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1980 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1981 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1982 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1983 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1984 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1985 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1986 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1987 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1988 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1989 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1990 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1991 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1992 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1993 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1994 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1995 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1996 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1997 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1998 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1999 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2000 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2001 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2002 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2003 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2004 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2005 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2006 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2007 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2008 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2009 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2010 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2011 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2012 }; 2013 2014 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2015 return llvm::makeArrayRef(GCCRegNames); 2016 } 2017 2018 // Namespace for x86 abstract base class 2019 const Builtin::Info BuiltinInfo[] = { 2020 #define BUILTIN(ID, TYPE, ATTRS) \ 2021 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2022 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2023 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2024 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2025 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2026 #include "clang/Basic/BuiltinsX86.def" 2027 }; 2028 2029 static const char* const GCCRegNames[] = { 2030 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2031 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2032 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2033 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2034 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2035 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2036 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2037 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2038 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2039 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2040 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2041 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2042 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2043 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2044 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2045 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2046 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2047 }; 2048 2049 const TargetInfo::AddlRegName AddlRegNames[] = { 2050 { { "al", "ah", "eax", "rax" }, 0 }, 2051 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2052 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2053 { { "dl", "dh", "edx", "rdx" }, 1 }, 2054 { { "esi", "rsi" }, 4 }, 2055 { { "edi", "rdi" }, 5 }, 2056 { { "esp", "rsp" }, 7 }, 2057 { { "ebp", "rbp" }, 6 }, 2058 { { "r8d", "r8w", "r8b" }, 38 }, 2059 { { "r9d", "r9w", "r9b" }, 39 }, 2060 { { "r10d", "r10w", "r10b" }, 40 }, 2061 { { "r11d", "r11w", "r11b" }, 41 }, 2062 { { "r12d", "r12w", "r12b" }, 42 }, 2063 { { "r13d", "r13w", "r13b" }, 43 }, 2064 { { "r14d", "r14w", "r14b" }, 44 }, 2065 { { "r15d", "r15w", "r15b" }, 45 }, 2066 }; 2067 2068 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2069 // most of the implementation can be shared. 2070 class X86TargetInfo : public TargetInfo { 2071 enum X86SSEEnum { 2072 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2073 } SSELevel = NoSSE; 2074 enum MMX3DNowEnum { 2075 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2076 } MMX3DNowLevel = NoMMX3DNow; 2077 enum XOPEnum { 2078 NoXOP, 2079 SSE4A, 2080 FMA4, 2081 XOP 2082 } XOPLevel = NoXOP; 2083 2084 bool HasAES = false; 2085 bool HasPCLMUL = false; 2086 bool HasLZCNT = false; 2087 bool HasRDRND = false; 2088 bool HasFSGSBASE = false; 2089 bool HasBMI = false; 2090 bool HasBMI2 = false; 2091 bool HasPOPCNT = false; 2092 bool HasRTM = false; 2093 bool HasPRFCHW = false; 2094 bool HasRDSEED = false; 2095 bool HasADX = false; 2096 bool HasTBM = false; 2097 bool HasFMA = false; 2098 bool HasF16C = false; 2099 bool HasAVX512CD = false; 2100 bool HasAVX512ER = false; 2101 bool HasAVX512PF = false; 2102 bool HasAVX512DQ = false; 2103 bool HasAVX512BW = false; 2104 bool HasAVX512VL = false; 2105 bool HasAVX512VBMI = false; 2106 bool HasAVX512IFMA = false; 2107 bool HasSHA = false; 2108 bool HasMPX = false; 2109 bool HasSGX = false; 2110 bool HasCX16 = false; 2111 bool HasFXSR = false; 2112 bool HasXSAVE = false; 2113 bool HasXSAVEOPT = false; 2114 bool HasXSAVEC = false; 2115 bool HasXSAVES = false; 2116 bool HasPKU = false; 2117 bool HasCLFLUSHOPT = false; 2118 bool HasPCOMMIT = false; 2119 bool HasCLWB = false; 2120 bool HasUMIP = false; 2121 bool HasMOVBE = false; 2122 bool HasPREFETCHWT1 = false; 2123 2124 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2125 /// 2126 /// Each enumeration represents a particular CPU supported by Clang. These 2127 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2128 enum CPUKind { 2129 CK_Generic, 2130 2131 /// \name i386 2132 /// i386-generation processors. 2133 //@{ 2134 CK_i386, 2135 //@} 2136 2137 /// \name i486 2138 /// i486-generation processors. 2139 //@{ 2140 CK_i486, 2141 CK_WinChipC6, 2142 CK_WinChip2, 2143 CK_C3, 2144 //@} 2145 2146 /// \name i586 2147 /// i586-generation processors, P5 microarchitecture based. 2148 //@{ 2149 CK_i586, 2150 CK_Pentium, 2151 CK_PentiumMMX, 2152 //@} 2153 2154 /// \name i686 2155 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2156 //@{ 2157 CK_i686, 2158 CK_PentiumPro, 2159 CK_Pentium2, 2160 CK_Pentium3, 2161 CK_Pentium3M, 2162 CK_PentiumM, 2163 CK_C3_2, 2164 2165 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2166 /// Clang however has some logic to suport this. 2167 // FIXME: Warn, deprecate, and potentially remove this. 2168 CK_Yonah, 2169 //@} 2170 2171 /// \name Netburst 2172 /// Netburst microarchitecture based processors. 2173 //@{ 2174 CK_Pentium4, 2175 CK_Pentium4M, 2176 CK_Prescott, 2177 CK_Nocona, 2178 //@} 2179 2180 /// \name Core 2181 /// Core microarchitecture based processors. 2182 //@{ 2183 CK_Core2, 2184 2185 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2186 /// codename which GCC no longer accepts as an option to -march, but Clang 2187 /// has some logic for recognizing it. 2188 // FIXME: Warn, deprecate, and potentially remove this. 2189 CK_Penryn, 2190 //@} 2191 2192 /// \name Atom 2193 /// Atom processors 2194 //@{ 2195 CK_Bonnell, 2196 CK_Silvermont, 2197 //@} 2198 2199 /// \name Nehalem 2200 /// Nehalem microarchitecture based processors. 2201 CK_Nehalem, 2202 2203 /// \name Westmere 2204 /// Westmere microarchitecture based processors. 2205 CK_Westmere, 2206 2207 /// \name Sandy Bridge 2208 /// Sandy Bridge microarchitecture based processors. 2209 CK_SandyBridge, 2210 2211 /// \name Ivy Bridge 2212 /// Ivy Bridge microarchitecture based processors. 2213 CK_IvyBridge, 2214 2215 /// \name Haswell 2216 /// Haswell microarchitecture based processors. 2217 CK_Haswell, 2218 2219 /// \name Broadwell 2220 /// Broadwell microarchitecture based processors. 2221 CK_Broadwell, 2222 2223 /// \name Skylake Client 2224 /// Skylake client microarchitecture based processors. 2225 CK_SkylakeClient, 2226 2227 /// \name Skylake Server 2228 /// Skylake server microarchitecture based processors. 2229 CK_SkylakeServer, 2230 2231 /// \name Cannonlake Client 2232 /// Cannonlake client microarchitecture based processors. 2233 CK_Cannonlake, 2234 2235 /// \name Knights Landing 2236 /// Knights Landing processor. 2237 CK_KNL, 2238 2239 /// \name K6 2240 /// K6 architecture processors. 2241 //@{ 2242 CK_K6, 2243 CK_K6_2, 2244 CK_K6_3, 2245 //@} 2246 2247 /// \name K7 2248 /// K7 architecture processors. 2249 //@{ 2250 CK_Athlon, 2251 CK_AthlonThunderbird, 2252 CK_Athlon4, 2253 CK_AthlonXP, 2254 CK_AthlonMP, 2255 //@} 2256 2257 /// \name K8 2258 /// K8 architecture processors. 2259 //@{ 2260 CK_Athlon64, 2261 CK_Athlon64SSE3, 2262 CK_AthlonFX, 2263 CK_K8, 2264 CK_K8SSE3, 2265 CK_Opteron, 2266 CK_OpteronSSE3, 2267 CK_AMDFAM10, 2268 //@} 2269 2270 /// \name Bobcat 2271 /// Bobcat architecture processors. 2272 //@{ 2273 CK_BTVER1, 2274 CK_BTVER2, 2275 //@} 2276 2277 /// \name Bulldozer 2278 /// Bulldozer architecture processors. 2279 //@{ 2280 CK_BDVER1, 2281 CK_BDVER2, 2282 CK_BDVER3, 2283 CK_BDVER4, 2284 //@} 2285 2286 /// This specification is deprecated and will be removed in the future. 2287 /// Users should prefer \see CK_K8. 2288 // FIXME: Warn on this when the CPU is set to it. 2289 //@{ 2290 CK_x86_64, 2291 //@} 2292 2293 /// \name Geode 2294 /// Geode processors. 2295 //@{ 2296 CK_Geode 2297 //@} 2298 } CPU = CK_Generic; 2299 2300 CPUKind getCPUKind(StringRef CPU) const { 2301 return llvm::StringSwitch<CPUKind>(CPU) 2302 .Case("i386", CK_i386) 2303 .Case("i486", CK_i486) 2304 .Case("winchip-c6", CK_WinChipC6) 2305 .Case("winchip2", CK_WinChip2) 2306 .Case("c3", CK_C3) 2307 .Case("i586", CK_i586) 2308 .Case("pentium", CK_Pentium) 2309 .Case("pentium-mmx", CK_PentiumMMX) 2310 .Case("i686", CK_i686) 2311 .Case("pentiumpro", CK_PentiumPro) 2312 .Case("pentium2", CK_Pentium2) 2313 .Case("pentium3", CK_Pentium3) 2314 .Case("pentium3m", CK_Pentium3M) 2315 .Case("pentium-m", CK_PentiumM) 2316 .Case("c3-2", CK_C3_2) 2317 .Case("yonah", CK_Yonah) 2318 .Case("pentium4", CK_Pentium4) 2319 .Case("pentium4m", CK_Pentium4M) 2320 .Case("prescott", CK_Prescott) 2321 .Case("nocona", CK_Nocona) 2322 .Case("core2", CK_Core2) 2323 .Case("penryn", CK_Penryn) 2324 .Case("bonnell", CK_Bonnell) 2325 .Case("atom", CK_Bonnell) // Legacy name. 2326 .Case("silvermont", CK_Silvermont) 2327 .Case("slm", CK_Silvermont) // Legacy name. 2328 .Case("nehalem", CK_Nehalem) 2329 .Case("corei7", CK_Nehalem) // Legacy name. 2330 .Case("westmere", CK_Westmere) 2331 .Case("sandybridge", CK_SandyBridge) 2332 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2333 .Case("ivybridge", CK_IvyBridge) 2334 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2335 .Case("haswell", CK_Haswell) 2336 .Case("core-avx2", CK_Haswell) // Legacy name. 2337 .Case("broadwell", CK_Broadwell) 2338 .Case("skylake", CK_SkylakeClient) 2339 .Case("skylake-avx512", CK_SkylakeServer) 2340 .Case("skx", CK_SkylakeServer) // Legacy name. 2341 .Case("cannonlake", CK_Cannonlake) 2342 .Case("knl", CK_KNL) 2343 .Case("k6", CK_K6) 2344 .Case("k6-2", CK_K6_2) 2345 .Case("k6-3", CK_K6_3) 2346 .Case("athlon", CK_Athlon) 2347 .Case("athlon-tbird", CK_AthlonThunderbird) 2348 .Case("athlon-4", CK_Athlon4) 2349 .Case("athlon-xp", CK_AthlonXP) 2350 .Case("athlon-mp", CK_AthlonMP) 2351 .Case("athlon64", CK_Athlon64) 2352 .Case("athlon64-sse3", CK_Athlon64SSE3) 2353 .Case("athlon-fx", CK_AthlonFX) 2354 .Case("k8", CK_K8) 2355 .Case("k8-sse3", CK_K8SSE3) 2356 .Case("opteron", CK_Opteron) 2357 .Case("opteron-sse3", CK_OpteronSSE3) 2358 .Case("barcelona", CK_AMDFAM10) 2359 .Case("amdfam10", CK_AMDFAM10) 2360 .Case("btver1", CK_BTVER1) 2361 .Case("btver2", CK_BTVER2) 2362 .Case("bdver1", CK_BDVER1) 2363 .Case("bdver2", CK_BDVER2) 2364 .Case("bdver3", CK_BDVER3) 2365 .Case("bdver4", CK_BDVER4) 2366 .Case("x86-64", CK_x86_64) 2367 .Case("geode", CK_Geode) 2368 .Default(CK_Generic); 2369 } 2370 2371 enum FPMathKind { 2372 FP_Default, 2373 FP_SSE, 2374 FP_387 2375 } FPMath = FP_Default; 2376 2377 public: 2378 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2379 BigEndian = false; 2380 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2381 } 2382 unsigned getFloatEvalMethod() const override { 2383 // X87 evaluates with 80 bits "long double" precision. 2384 return SSELevel == NoSSE ? 2 : 0; 2385 } 2386 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2387 return llvm::makeArrayRef(BuiltinInfo, 2388 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2389 } 2390 ArrayRef<const char *> getGCCRegNames() const override { 2391 return llvm::makeArrayRef(GCCRegNames); 2392 } 2393 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2394 return None; 2395 } 2396 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2397 return llvm::makeArrayRef(AddlRegNames); 2398 } 2399 bool validateCpuSupports(StringRef Name) const override; 2400 bool validateAsmConstraint(const char *&Name, 2401 TargetInfo::ConstraintInfo &info) const override; 2402 2403 bool validateGlobalRegisterVariable(StringRef RegName, 2404 unsigned RegSize, 2405 bool &HasSizeMismatch) const override { 2406 // esp and ebp are the only 32-bit registers the x86 backend can currently 2407 // handle. 2408 if (RegName.equals("esp") || RegName.equals("ebp")) { 2409 // Check that the register size is 32-bit. 2410 HasSizeMismatch = RegSize != 32; 2411 return true; 2412 } 2413 2414 return false; 2415 } 2416 2417 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2418 2419 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2420 2421 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2422 2423 std::string convertConstraint(const char *&Constraint) const override; 2424 const char *getClobbers() const override { 2425 return "~{dirflag},~{fpsr},~{flags}"; 2426 } 2427 void getTargetDefines(const LangOptions &Opts, 2428 MacroBuilder &Builder) const override; 2429 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2430 bool Enabled); 2431 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2432 bool Enabled); 2433 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2434 bool Enabled); 2435 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2436 StringRef Name, bool Enabled) const override { 2437 setFeatureEnabledImpl(Features, Name, Enabled); 2438 } 2439 // This exists purely to cut down on the number of virtual calls in 2440 // initFeatureMap which calls this repeatedly. 2441 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2442 StringRef Name, bool Enabled); 2443 bool 2444 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2445 StringRef CPU, 2446 const std::vector<std::string> &FeaturesVec) const override; 2447 bool hasFeature(StringRef Feature) const override; 2448 bool handleTargetFeatures(std::vector<std::string> &Features, 2449 DiagnosticsEngine &Diags) override; 2450 StringRef getABI() const override { 2451 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2452 return "avx512"; 2453 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2454 return "avx"; 2455 if (getTriple().getArch() == llvm::Triple::x86 && 2456 MMX3DNowLevel == NoMMX3DNow) 2457 return "no-mmx"; 2458 return ""; 2459 } 2460 bool setCPU(const std::string &Name) override { 2461 CPU = getCPUKind(Name); 2462 2463 // Perform any per-CPU checks necessary to determine if this CPU is 2464 // acceptable. 2465 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2466 // invalid without explaining *why*. 2467 switch (CPU) { 2468 case CK_Generic: 2469 // No processor selected! 2470 return false; 2471 2472 case CK_i386: 2473 case CK_i486: 2474 case CK_WinChipC6: 2475 case CK_WinChip2: 2476 case CK_C3: 2477 case CK_i586: 2478 case CK_Pentium: 2479 case CK_PentiumMMX: 2480 case CK_i686: 2481 case CK_PentiumPro: 2482 case CK_Pentium2: 2483 case CK_Pentium3: 2484 case CK_Pentium3M: 2485 case CK_PentiumM: 2486 case CK_Yonah: 2487 case CK_C3_2: 2488 case CK_Pentium4: 2489 case CK_Pentium4M: 2490 case CK_Prescott: 2491 case CK_K6: 2492 case CK_K6_2: 2493 case CK_K6_3: 2494 case CK_Athlon: 2495 case CK_AthlonThunderbird: 2496 case CK_Athlon4: 2497 case CK_AthlonXP: 2498 case CK_AthlonMP: 2499 case CK_Geode: 2500 // Only accept certain architectures when compiling in 32-bit mode. 2501 if (getTriple().getArch() != llvm::Triple::x86) 2502 return false; 2503 2504 // Fallthrough 2505 case CK_Nocona: 2506 case CK_Core2: 2507 case CK_Penryn: 2508 case CK_Bonnell: 2509 case CK_Silvermont: 2510 case CK_Nehalem: 2511 case CK_Westmere: 2512 case CK_SandyBridge: 2513 case CK_IvyBridge: 2514 case CK_Haswell: 2515 case CK_Broadwell: 2516 case CK_SkylakeClient: 2517 case CK_SkylakeServer: 2518 case CK_Cannonlake: 2519 case CK_KNL: 2520 case CK_Athlon64: 2521 case CK_Athlon64SSE3: 2522 case CK_AthlonFX: 2523 case CK_K8: 2524 case CK_K8SSE3: 2525 case CK_Opteron: 2526 case CK_OpteronSSE3: 2527 case CK_AMDFAM10: 2528 case CK_BTVER1: 2529 case CK_BTVER2: 2530 case CK_BDVER1: 2531 case CK_BDVER2: 2532 case CK_BDVER3: 2533 case CK_BDVER4: 2534 case CK_x86_64: 2535 return true; 2536 } 2537 llvm_unreachable("Unhandled CPU kind"); 2538 } 2539 2540 bool setFPMath(StringRef Name) override; 2541 2542 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2543 // Most of the non-ARM calling conventions are i386 conventions. 2544 switch (CC) { 2545 case CC_X86ThisCall: 2546 case CC_X86FastCall: 2547 case CC_X86StdCall: 2548 case CC_X86VectorCall: 2549 case CC_C: 2550 case CC_Swift: 2551 case CC_X86Pascal: 2552 case CC_IntelOclBicc: 2553 return CCCR_OK; 2554 default: 2555 return CCCR_Warning; 2556 } 2557 } 2558 2559 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2560 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2561 } 2562 2563 bool hasSjLjLowering() const override { 2564 return true; 2565 } 2566 }; 2567 2568 bool X86TargetInfo::setFPMath(StringRef Name) { 2569 if (Name == "387") { 2570 FPMath = FP_387; 2571 return true; 2572 } 2573 if (Name == "sse") { 2574 FPMath = FP_SSE; 2575 return true; 2576 } 2577 return false; 2578 } 2579 2580 bool X86TargetInfo::initFeatureMap( 2581 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2582 const std::vector<std::string> &FeaturesVec) const { 2583 // FIXME: This *really* should not be here. 2584 // X86_64 always has SSE2. 2585 if (getTriple().getArch() == llvm::Triple::x86_64) 2586 setFeatureEnabledImpl(Features, "sse2", true); 2587 2588 // Enable X87 for all X86 processors. 2589 setFeatureEnabledImpl(Features, "x87", true); 2590 2591 switch (getCPUKind(CPU)) { 2592 case CK_Generic: 2593 case CK_i386: 2594 case CK_i486: 2595 case CK_i586: 2596 case CK_Pentium: 2597 case CK_i686: 2598 case CK_PentiumPro: 2599 break; 2600 case CK_PentiumMMX: 2601 case CK_Pentium2: 2602 case CK_K6: 2603 case CK_WinChipC6: 2604 setFeatureEnabledImpl(Features, "mmx", true); 2605 break; 2606 case CK_Pentium3: 2607 case CK_Pentium3M: 2608 case CK_C3_2: 2609 setFeatureEnabledImpl(Features, "sse", true); 2610 setFeatureEnabledImpl(Features, "fxsr", true); 2611 break; 2612 case CK_PentiumM: 2613 case CK_Pentium4: 2614 case CK_Pentium4M: 2615 case CK_x86_64: 2616 setFeatureEnabledImpl(Features, "sse2", true); 2617 setFeatureEnabledImpl(Features, "fxsr", true); 2618 break; 2619 case CK_Yonah: 2620 case CK_Prescott: 2621 case CK_Nocona: 2622 setFeatureEnabledImpl(Features, "sse3", true); 2623 setFeatureEnabledImpl(Features, "fxsr", true); 2624 setFeatureEnabledImpl(Features, "cx16", true); 2625 break; 2626 case CK_Core2: 2627 case CK_Bonnell: 2628 setFeatureEnabledImpl(Features, "ssse3", true); 2629 setFeatureEnabledImpl(Features, "fxsr", true); 2630 setFeatureEnabledImpl(Features, "cx16", true); 2631 break; 2632 case CK_Penryn: 2633 setFeatureEnabledImpl(Features, "sse4.1", true); 2634 setFeatureEnabledImpl(Features, "fxsr", true); 2635 setFeatureEnabledImpl(Features, "cx16", true); 2636 break; 2637 case CK_Cannonlake: 2638 setFeatureEnabledImpl(Features, "avx512ifma", true); 2639 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2640 setFeatureEnabledImpl(Features, "sha", true); 2641 setFeatureEnabledImpl(Features, "umip", true); 2642 // FALLTHROUGH 2643 case CK_SkylakeServer: 2644 setFeatureEnabledImpl(Features, "avx512f", true); 2645 setFeatureEnabledImpl(Features, "avx512cd", true); 2646 setFeatureEnabledImpl(Features, "avx512dq", true); 2647 setFeatureEnabledImpl(Features, "avx512bw", true); 2648 setFeatureEnabledImpl(Features, "avx512vl", true); 2649 setFeatureEnabledImpl(Features, "pku", true); 2650 setFeatureEnabledImpl(Features, "pcommit", true); 2651 setFeatureEnabledImpl(Features, "clwb", true); 2652 // FALLTHROUGH 2653 case CK_SkylakeClient: 2654 setFeatureEnabledImpl(Features, "xsavec", true); 2655 setFeatureEnabledImpl(Features, "xsaves", true); 2656 setFeatureEnabledImpl(Features, "mpx", true); 2657 setFeatureEnabledImpl(Features, "sgx", true); 2658 setFeatureEnabledImpl(Features, "clflushopt", true); 2659 // FALLTHROUGH 2660 case CK_Broadwell: 2661 setFeatureEnabledImpl(Features, "rdseed", true); 2662 setFeatureEnabledImpl(Features, "adx", true); 2663 // FALLTHROUGH 2664 case CK_Haswell: 2665 setFeatureEnabledImpl(Features, "avx2", true); 2666 setFeatureEnabledImpl(Features, "lzcnt", true); 2667 setFeatureEnabledImpl(Features, "bmi", true); 2668 setFeatureEnabledImpl(Features, "bmi2", true); 2669 setFeatureEnabledImpl(Features, "rtm", true); 2670 setFeatureEnabledImpl(Features, "fma", true); 2671 setFeatureEnabledImpl(Features, "movbe", true); 2672 // FALLTHROUGH 2673 case CK_IvyBridge: 2674 setFeatureEnabledImpl(Features, "rdrnd", true); 2675 setFeatureEnabledImpl(Features, "f16c", true); 2676 setFeatureEnabledImpl(Features, "fsgsbase", true); 2677 // FALLTHROUGH 2678 case CK_SandyBridge: 2679 setFeatureEnabledImpl(Features, "avx", true); 2680 setFeatureEnabledImpl(Features, "xsave", true); 2681 setFeatureEnabledImpl(Features, "xsaveopt", true); 2682 // FALLTHROUGH 2683 case CK_Westmere: 2684 case CK_Silvermont: 2685 setFeatureEnabledImpl(Features, "aes", true); 2686 setFeatureEnabledImpl(Features, "pclmul", true); 2687 // FALLTHROUGH 2688 case CK_Nehalem: 2689 setFeatureEnabledImpl(Features, "sse4.2", true); 2690 setFeatureEnabledImpl(Features, "fxsr", true); 2691 setFeatureEnabledImpl(Features, "cx16", true); 2692 break; 2693 case CK_KNL: 2694 setFeatureEnabledImpl(Features, "avx512f", true); 2695 setFeatureEnabledImpl(Features, "avx512cd", true); 2696 setFeatureEnabledImpl(Features, "avx512er", true); 2697 setFeatureEnabledImpl(Features, "avx512pf", true); 2698 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2699 setFeatureEnabledImpl(Features, "fxsr", true); 2700 setFeatureEnabledImpl(Features, "rdseed", true); 2701 setFeatureEnabledImpl(Features, "adx", true); 2702 setFeatureEnabledImpl(Features, "lzcnt", true); 2703 setFeatureEnabledImpl(Features, "bmi", true); 2704 setFeatureEnabledImpl(Features, "bmi2", true); 2705 setFeatureEnabledImpl(Features, "rtm", true); 2706 setFeatureEnabledImpl(Features, "fma", true); 2707 setFeatureEnabledImpl(Features, "rdrnd", true); 2708 setFeatureEnabledImpl(Features, "f16c", true); 2709 setFeatureEnabledImpl(Features, "fsgsbase", true); 2710 setFeatureEnabledImpl(Features, "aes", true); 2711 setFeatureEnabledImpl(Features, "pclmul", true); 2712 setFeatureEnabledImpl(Features, "cx16", true); 2713 setFeatureEnabledImpl(Features, "xsaveopt", true); 2714 setFeatureEnabledImpl(Features, "xsave", true); 2715 setFeatureEnabledImpl(Features, "movbe", true); 2716 break; 2717 case CK_K6_2: 2718 case CK_K6_3: 2719 case CK_WinChip2: 2720 case CK_C3: 2721 setFeatureEnabledImpl(Features, "3dnow", true); 2722 break; 2723 case CK_Athlon: 2724 case CK_AthlonThunderbird: 2725 case CK_Geode: 2726 setFeatureEnabledImpl(Features, "3dnowa", true); 2727 break; 2728 case CK_Athlon4: 2729 case CK_AthlonXP: 2730 case CK_AthlonMP: 2731 setFeatureEnabledImpl(Features, "sse", true); 2732 setFeatureEnabledImpl(Features, "3dnowa", true); 2733 setFeatureEnabledImpl(Features, "fxsr", true); 2734 break; 2735 case CK_K8: 2736 case CK_Opteron: 2737 case CK_Athlon64: 2738 case CK_AthlonFX: 2739 setFeatureEnabledImpl(Features, "sse2", true); 2740 setFeatureEnabledImpl(Features, "3dnowa", true); 2741 setFeatureEnabledImpl(Features, "fxsr", true); 2742 break; 2743 case CK_AMDFAM10: 2744 setFeatureEnabledImpl(Features, "sse4a", true); 2745 setFeatureEnabledImpl(Features, "lzcnt", true); 2746 setFeatureEnabledImpl(Features, "popcnt", true); 2747 // FALLTHROUGH 2748 case CK_K8SSE3: 2749 case CK_OpteronSSE3: 2750 case CK_Athlon64SSE3: 2751 setFeatureEnabledImpl(Features, "sse3", true); 2752 setFeatureEnabledImpl(Features, "3dnowa", true); 2753 setFeatureEnabledImpl(Features, "fxsr", true); 2754 break; 2755 case CK_BTVER2: 2756 setFeatureEnabledImpl(Features, "avx", true); 2757 setFeatureEnabledImpl(Features, "aes", true); 2758 setFeatureEnabledImpl(Features, "pclmul", true); 2759 setFeatureEnabledImpl(Features, "bmi", true); 2760 setFeatureEnabledImpl(Features, "f16c", true); 2761 setFeatureEnabledImpl(Features, "xsaveopt", true); 2762 // FALLTHROUGH 2763 case CK_BTVER1: 2764 setFeatureEnabledImpl(Features, "ssse3", true); 2765 setFeatureEnabledImpl(Features, "sse4a", true); 2766 setFeatureEnabledImpl(Features, "lzcnt", true); 2767 setFeatureEnabledImpl(Features, "popcnt", true); 2768 setFeatureEnabledImpl(Features, "prfchw", true); 2769 setFeatureEnabledImpl(Features, "cx16", true); 2770 setFeatureEnabledImpl(Features, "fxsr", true); 2771 break; 2772 case CK_BDVER4: 2773 setFeatureEnabledImpl(Features, "avx2", true); 2774 setFeatureEnabledImpl(Features, "bmi2", true); 2775 // FALLTHROUGH 2776 case CK_BDVER3: 2777 setFeatureEnabledImpl(Features, "fsgsbase", true); 2778 setFeatureEnabledImpl(Features, "xsaveopt", true); 2779 // FALLTHROUGH 2780 case CK_BDVER2: 2781 setFeatureEnabledImpl(Features, "bmi", true); 2782 setFeatureEnabledImpl(Features, "fma", true); 2783 setFeatureEnabledImpl(Features, "f16c", true); 2784 setFeatureEnabledImpl(Features, "tbm", true); 2785 // FALLTHROUGH 2786 case CK_BDVER1: 2787 // xop implies avx, sse4a and fma4. 2788 setFeatureEnabledImpl(Features, "xop", true); 2789 setFeatureEnabledImpl(Features, "lzcnt", true); 2790 setFeatureEnabledImpl(Features, "aes", true); 2791 setFeatureEnabledImpl(Features, "pclmul", true); 2792 setFeatureEnabledImpl(Features, "prfchw", true); 2793 setFeatureEnabledImpl(Features, "cx16", true); 2794 setFeatureEnabledImpl(Features, "fxsr", true); 2795 setFeatureEnabledImpl(Features, "xsave", true); 2796 break; 2797 } 2798 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2799 return false; 2800 2801 // Can't do this earlier because we need to be able to explicitly enable 2802 // or disable these features and the things that they depend upon. 2803 2804 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2805 auto I = Features.find("sse4.2"); 2806 if (I != Features.end() && I->getValue() && 2807 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2808 FeaturesVec.end()) 2809 Features["popcnt"] = true; 2810 2811 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2812 I = Features.find("3dnow"); 2813 if (I != Features.end() && I->getValue() && 2814 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2815 FeaturesVec.end()) 2816 Features["prfchw"] = true; 2817 2818 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2819 // then enable MMX. 2820 I = Features.find("sse"); 2821 if (I != Features.end() && I->getValue() && 2822 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2823 FeaturesVec.end()) 2824 Features["mmx"] = true; 2825 2826 return true; 2827 } 2828 2829 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2830 X86SSEEnum Level, bool Enabled) { 2831 if (Enabled) { 2832 switch (Level) { 2833 case AVX512F: 2834 Features["avx512f"] = true; 2835 case AVX2: 2836 Features["avx2"] = true; 2837 case AVX: 2838 Features["avx"] = true; 2839 Features["xsave"] = true; 2840 case SSE42: 2841 Features["sse4.2"] = true; 2842 case SSE41: 2843 Features["sse4.1"] = true; 2844 case SSSE3: 2845 Features["ssse3"] = true; 2846 case SSE3: 2847 Features["sse3"] = true; 2848 case SSE2: 2849 Features["sse2"] = true; 2850 case SSE1: 2851 Features["sse"] = true; 2852 case NoSSE: 2853 break; 2854 } 2855 return; 2856 } 2857 2858 switch (Level) { 2859 case NoSSE: 2860 case SSE1: 2861 Features["sse"] = false; 2862 case SSE2: 2863 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2864 Features["sha"] = false; 2865 case SSE3: 2866 Features["sse3"] = false; 2867 setXOPLevel(Features, NoXOP, false); 2868 case SSSE3: 2869 Features["ssse3"] = false; 2870 case SSE41: 2871 Features["sse4.1"] = false; 2872 case SSE42: 2873 Features["sse4.2"] = false; 2874 case AVX: 2875 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2876 Features["xsaveopt"] = false; 2877 setXOPLevel(Features, FMA4, false); 2878 case AVX2: 2879 Features["avx2"] = false; 2880 case AVX512F: 2881 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2882 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2883 Features["avx512vl"] = Features["avx512vbmi"] = 2884 Features["avx512ifma"] = false; 2885 } 2886 } 2887 2888 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2889 MMX3DNowEnum Level, bool Enabled) { 2890 if (Enabled) { 2891 switch (Level) { 2892 case AMD3DNowAthlon: 2893 Features["3dnowa"] = true; 2894 case AMD3DNow: 2895 Features["3dnow"] = true; 2896 case MMX: 2897 Features["mmx"] = true; 2898 case NoMMX3DNow: 2899 break; 2900 } 2901 return; 2902 } 2903 2904 switch (Level) { 2905 case NoMMX3DNow: 2906 case MMX: 2907 Features["mmx"] = false; 2908 case AMD3DNow: 2909 Features["3dnow"] = false; 2910 case AMD3DNowAthlon: 2911 Features["3dnowa"] = false; 2912 } 2913 } 2914 2915 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2916 bool Enabled) { 2917 if (Enabled) { 2918 switch (Level) { 2919 case XOP: 2920 Features["xop"] = true; 2921 case FMA4: 2922 Features["fma4"] = true; 2923 setSSELevel(Features, AVX, true); 2924 case SSE4A: 2925 Features["sse4a"] = true; 2926 setSSELevel(Features, SSE3, true); 2927 case NoXOP: 2928 break; 2929 } 2930 return; 2931 } 2932 2933 switch (Level) { 2934 case NoXOP: 2935 case SSE4A: 2936 Features["sse4a"] = false; 2937 case FMA4: 2938 Features["fma4"] = false; 2939 case XOP: 2940 Features["xop"] = false; 2941 } 2942 } 2943 2944 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2945 StringRef Name, bool Enabled) { 2946 // This is a bit of a hack to deal with the sse4 target feature when used 2947 // as part of the target attribute. We handle sse4 correctly everywhere 2948 // else. See below for more information on how we handle the sse4 options. 2949 if (Name != "sse4") 2950 Features[Name] = Enabled; 2951 2952 if (Name == "mmx") { 2953 setMMXLevel(Features, MMX, Enabled); 2954 } else if (Name == "sse") { 2955 setSSELevel(Features, SSE1, Enabled); 2956 } else if (Name == "sse2") { 2957 setSSELevel(Features, SSE2, Enabled); 2958 } else if (Name == "sse3") { 2959 setSSELevel(Features, SSE3, Enabled); 2960 } else if (Name == "ssse3") { 2961 setSSELevel(Features, SSSE3, Enabled); 2962 } else if (Name == "sse4.2") { 2963 setSSELevel(Features, SSE42, Enabled); 2964 } else if (Name == "sse4.1") { 2965 setSSELevel(Features, SSE41, Enabled); 2966 } else if (Name == "3dnow") { 2967 setMMXLevel(Features, AMD3DNow, Enabled); 2968 } else if (Name == "3dnowa") { 2969 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2970 } else if (Name == "aes") { 2971 if (Enabled) 2972 setSSELevel(Features, SSE2, Enabled); 2973 } else if (Name == "pclmul") { 2974 if (Enabled) 2975 setSSELevel(Features, SSE2, Enabled); 2976 } else if (Name == "avx") { 2977 setSSELevel(Features, AVX, Enabled); 2978 } else if (Name == "avx2") { 2979 setSSELevel(Features, AVX2, Enabled); 2980 } else if (Name == "avx512f") { 2981 setSSELevel(Features, AVX512F, Enabled); 2982 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 2983 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 2984 Name == "avx512vbmi" || Name == "avx512ifma") { 2985 if (Enabled) 2986 setSSELevel(Features, AVX512F, Enabled); 2987 } else if (Name == "fma") { 2988 if (Enabled) 2989 setSSELevel(Features, AVX, Enabled); 2990 } else if (Name == "fma4") { 2991 setXOPLevel(Features, FMA4, Enabled); 2992 } else if (Name == "xop") { 2993 setXOPLevel(Features, XOP, Enabled); 2994 } else if (Name == "sse4a") { 2995 setXOPLevel(Features, SSE4A, Enabled); 2996 } else if (Name == "f16c") { 2997 if (Enabled) 2998 setSSELevel(Features, AVX, Enabled); 2999 } else if (Name == "sha") { 3000 if (Enabled) 3001 setSSELevel(Features, SSE2, Enabled); 3002 } else if (Name == "sse4") { 3003 // We can get here via the __target__ attribute since that's not controlled 3004 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3005 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3006 // disabled. 3007 if (Enabled) 3008 setSSELevel(Features, SSE42, Enabled); 3009 else 3010 setSSELevel(Features, SSE41, Enabled); 3011 } else if (Name == "xsave") { 3012 if (!Enabled) 3013 Features["xsaveopt"] = false; 3014 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3015 if (Enabled) 3016 Features["xsave"] = true; 3017 } 3018 } 3019 3020 /// handleTargetFeatures - Perform initialization based on the user 3021 /// configured set of features. 3022 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3023 DiagnosticsEngine &Diags) { 3024 for (const auto &Feature : Features) { 3025 if (Feature[0] != '+') 3026 continue; 3027 3028 if (Feature == "+aes") { 3029 HasAES = true; 3030 } else if (Feature == "+pclmul") { 3031 HasPCLMUL = true; 3032 } else if (Feature == "+lzcnt") { 3033 HasLZCNT = true; 3034 } else if (Feature == "+rdrnd") { 3035 HasRDRND = true; 3036 } else if (Feature == "+fsgsbase") { 3037 HasFSGSBASE = true; 3038 } else if (Feature == "+bmi") { 3039 HasBMI = true; 3040 } else if (Feature == "+bmi2") { 3041 HasBMI2 = true; 3042 } else if (Feature == "+popcnt") { 3043 HasPOPCNT = true; 3044 } else if (Feature == "+rtm") { 3045 HasRTM = true; 3046 } else if (Feature == "+prfchw") { 3047 HasPRFCHW = true; 3048 } else if (Feature == "+rdseed") { 3049 HasRDSEED = true; 3050 } else if (Feature == "+adx") { 3051 HasADX = true; 3052 } else if (Feature == "+tbm") { 3053 HasTBM = true; 3054 } else if (Feature == "+fma") { 3055 HasFMA = true; 3056 } else if (Feature == "+f16c") { 3057 HasF16C = true; 3058 } else if (Feature == "+avx512cd") { 3059 HasAVX512CD = true; 3060 } else if (Feature == "+avx512er") { 3061 HasAVX512ER = true; 3062 } else if (Feature == "+avx512pf") { 3063 HasAVX512PF = true; 3064 } else if (Feature == "+avx512dq") { 3065 HasAVX512DQ = true; 3066 } else if (Feature == "+avx512bw") { 3067 HasAVX512BW = true; 3068 } else if (Feature == "+avx512vl") { 3069 HasAVX512VL = true; 3070 } else if (Feature == "+avx512vbmi") { 3071 HasAVX512VBMI = true; 3072 } else if (Feature == "+avx512ifma") { 3073 HasAVX512IFMA = true; 3074 } else if (Feature == "+sha") { 3075 HasSHA = true; 3076 } else if (Feature == "+mpx") { 3077 HasMPX = true; 3078 } else if (Feature == "+movbe") { 3079 HasMOVBE = true; 3080 } else if (Feature == "+sgx") { 3081 HasSGX = true; 3082 } else if (Feature == "+cx16") { 3083 HasCX16 = true; 3084 } else if (Feature == "+fxsr") { 3085 HasFXSR = true; 3086 } else if (Feature == "+xsave") { 3087 HasXSAVE = true; 3088 } else if (Feature == "+xsaveopt") { 3089 HasXSAVEOPT = true; 3090 } else if (Feature == "+xsavec") { 3091 HasXSAVEC = true; 3092 } else if (Feature == "+xsaves") { 3093 HasXSAVES = true; 3094 } else if (Feature == "+pku") { 3095 HasPKU = true; 3096 } else if (Feature == "+clflushopt") { 3097 HasCLFLUSHOPT = true; 3098 } else if (Feature == "+pcommit") { 3099 HasPCOMMIT = true; 3100 } else if (Feature == "+clwb") { 3101 HasCLWB = true; 3102 } else if (Feature == "+umip") { 3103 HasUMIP = true; 3104 } else if (Feature == "+prefetchwt1") { 3105 HasPREFETCHWT1 = true; 3106 } 3107 3108 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3109 .Case("+avx512f", AVX512F) 3110 .Case("+avx2", AVX2) 3111 .Case("+avx", AVX) 3112 .Case("+sse4.2", SSE42) 3113 .Case("+sse4.1", SSE41) 3114 .Case("+ssse3", SSSE3) 3115 .Case("+sse3", SSE3) 3116 .Case("+sse2", SSE2) 3117 .Case("+sse", SSE1) 3118 .Default(NoSSE); 3119 SSELevel = std::max(SSELevel, Level); 3120 3121 MMX3DNowEnum ThreeDNowLevel = 3122 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3123 .Case("+3dnowa", AMD3DNowAthlon) 3124 .Case("+3dnow", AMD3DNow) 3125 .Case("+mmx", MMX) 3126 .Default(NoMMX3DNow); 3127 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3128 3129 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3130 .Case("+xop", XOP) 3131 .Case("+fma4", FMA4) 3132 .Case("+sse4a", SSE4A) 3133 .Default(NoXOP); 3134 XOPLevel = std::max(XOPLevel, XLevel); 3135 } 3136 3137 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3138 // matches the selected sse level. 3139 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3140 (FPMath == FP_387 && SSELevel >= SSE1)) { 3141 Diags.Report(diag::err_target_unsupported_fpmath) << 3142 (FPMath == FP_SSE ? "sse" : "387"); 3143 return false; 3144 } 3145 3146 SimdDefaultAlign = 3147 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3148 return true; 3149 } 3150 3151 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3152 /// definitions for this particular subtarget. 3153 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3154 MacroBuilder &Builder) const { 3155 // Target identification. 3156 if (getTriple().getArch() == llvm::Triple::x86_64) { 3157 Builder.defineMacro("__amd64__"); 3158 Builder.defineMacro("__amd64"); 3159 Builder.defineMacro("__x86_64"); 3160 Builder.defineMacro("__x86_64__"); 3161 if (getTriple().getArchName() == "x86_64h") { 3162 Builder.defineMacro("__x86_64h"); 3163 Builder.defineMacro("__x86_64h__"); 3164 } 3165 } else { 3166 DefineStd(Builder, "i386", Opts); 3167 } 3168 3169 // Subtarget options. 3170 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3171 // truly should be based on -mtune options. 3172 switch (CPU) { 3173 case CK_Generic: 3174 break; 3175 case CK_i386: 3176 // The rest are coming from the i386 define above. 3177 Builder.defineMacro("__tune_i386__"); 3178 break; 3179 case CK_i486: 3180 case CK_WinChipC6: 3181 case CK_WinChip2: 3182 case CK_C3: 3183 defineCPUMacros(Builder, "i486"); 3184 break; 3185 case CK_PentiumMMX: 3186 Builder.defineMacro("__pentium_mmx__"); 3187 Builder.defineMacro("__tune_pentium_mmx__"); 3188 // Fallthrough 3189 case CK_i586: 3190 case CK_Pentium: 3191 defineCPUMacros(Builder, "i586"); 3192 defineCPUMacros(Builder, "pentium"); 3193 break; 3194 case CK_Pentium3: 3195 case CK_Pentium3M: 3196 case CK_PentiumM: 3197 Builder.defineMacro("__tune_pentium3__"); 3198 // Fallthrough 3199 case CK_Pentium2: 3200 case CK_C3_2: 3201 Builder.defineMacro("__tune_pentium2__"); 3202 // Fallthrough 3203 case CK_PentiumPro: 3204 Builder.defineMacro("__tune_i686__"); 3205 Builder.defineMacro("__tune_pentiumpro__"); 3206 // Fallthrough 3207 case CK_i686: 3208 Builder.defineMacro("__i686"); 3209 Builder.defineMacro("__i686__"); 3210 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3211 Builder.defineMacro("__pentiumpro"); 3212 Builder.defineMacro("__pentiumpro__"); 3213 break; 3214 case CK_Pentium4: 3215 case CK_Pentium4M: 3216 defineCPUMacros(Builder, "pentium4"); 3217 break; 3218 case CK_Yonah: 3219 case CK_Prescott: 3220 case CK_Nocona: 3221 defineCPUMacros(Builder, "nocona"); 3222 break; 3223 case CK_Core2: 3224 case CK_Penryn: 3225 defineCPUMacros(Builder, "core2"); 3226 break; 3227 case CK_Bonnell: 3228 defineCPUMacros(Builder, "atom"); 3229 break; 3230 case CK_Silvermont: 3231 defineCPUMacros(Builder, "slm"); 3232 break; 3233 case CK_Nehalem: 3234 case CK_Westmere: 3235 case CK_SandyBridge: 3236 case CK_IvyBridge: 3237 case CK_Haswell: 3238 case CK_Broadwell: 3239 case CK_SkylakeClient: 3240 // FIXME: Historically, we defined this legacy name, it would be nice to 3241 // remove it at some point. We've never exposed fine-grained names for 3242 // recent primary x86 CPUs, and we should keep it that way. 3243 defineCPUMacros(Builder, "corei7"); 3244 break; 3245 case CK_SkylakeServer: 3246 defineCPUMacros(Builder, "skx"); 3247 break; 3248 case CK_Cannonlake: 3249 break; 3250 case CK_KNL: 3251 defineCPUMacros(Builder, "knl"); 3252 break; 3253 case CK_K6_2: 3254 Builder.defineMacro("__k6_2__"); 3255 Builder.defineMacro("__tune_k6_2__"); 3256 // Fallthrough 3257 case CK_K6_3: 3258 if (CPU != CK_K6_2) { // In case of fallthrough 3259 // FIXME: GCC may be enabling these in cases where some other k6 3260 // architecture is specified but -m3dnow is explicitly provided. The 3261 // exact semantics need to be determined and emulated here. 3262 Builder.defineMacro("__k6_3__"); 3263 Builder.defineMacro("__tune_k6_3__"); 3264 } 3265 // Fallthrough 3266 case CK_K6: 3267 defineCPUMacros(Builder, "k6"); 3268 break; 3269 case CK_Athlon: 3270 case CK_AthlonThunderbird: 3271 case CK_Athlon4: 3272 case CK_AthlonXP: 3273 case CK_AthlonMP: 3274 defineCPUMacros(Builder, "athlon"); 3275 if (SSELevel != NoSSE) { 3276 Builder.defineMacro("__athlon_sse__"); 3277 Builder.defineMacro("__tune_athlon_sse__"); 3278 } 3279 break; 3280 case CK_K8: 3281 case CK_K8SSE3: 3282 case CK_x86_64: 3283 case CK_Opteron: 3284 case CK_OpteronSSE3: 3285 case CK_Athlon64: 3286 case CK_Athlon64SSE3: 3287 case CK_AthlonFX: 3288 defineCPUMacros(Builder, "k8"); 3289 break; 3290 case CK_AMDFAM10: 3291 defineCPUMacros(Builder, "amdfam10"); 3292 break; 3293 case CK_BTVER1: 3294 defineCPUMacros(Builder, "btver1"); 3295 break; 3296 case CK_BTVER2: 3297 defineCPUMacros(Builder, "btver2"); 3298 break; 3299 case CK_BDVER1: 3300 defineCPUMacros(Builder, "bdver1"); 3301 break; 3302 case CK_BDVER2: 3303 defineCPUMacros(Builder, "bdver2"); 3304 break; 3305 case CK_BDVER3: 3306 defineCPUMacros(Builder, "bdver3"); 3307 break; 3308 case CK_BDVER4: 3309 defineCPUMacros(Builder, "bdver4"); 3310 break; 3311 case CK_Geode: 3312 defineCPUMacros(Builder, "geode"); 3313 break; 3314 } 3315 3316 // Target properties. 3317 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3318 3319 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3320 // functions in glibc header files that use FP Stack inline asm which the 3321 // backend can't deal with (PR879). 3322 Builder.defineMacro("__NO_MATH_INLINES"); 3323 3324 if (HasAES) 3325 Builder.defineMacro("__AES__"); 3326 3327 if (HasPCLMUL) 3328 Builder.defineMacro("__PCLMUL__"); 3329 3330 if (HasLZCNT) 3331 Builder.defineMacro("__LZCNT__"); 3332 3333 if (HasRDRND) 3334 Builder.defineMacro("__RDRND__"); 3335 3336 if (HasFSGSBASE) 3337 Builder.defineMacro("__FSGSBASE__"); 3338 3339 if (HasBMI) 3340 Builder.defineMacro("__BMI__"); 3341 3342 if (HasBMI2) 3343 Builder.defineMacro("__BMI2__"); 3344 3345 if (HasPOPCNT) 3346 Builder.defineMacro("__POPCNT__"); 3347 3348 if (HasRTM) 3349 Builder.defineMacro("__RTM__"); 3350 3351 if (HasPRFCHW) 3352 Builder.defineMacro("__PRFCHW__"); 3353 3354 if (HasRDSEED) 3355 Builder.defineMacro("__RDSEED__"); 3356 3357 if (HasADX) 3358 Builder.defineMacro("__ADX__"); 3359 3360 if (HasTBM) 3361 Builder.defineMacro("__TBM__"); 3362 3363 switch (XOPLevel) { 3364 case XOP: 3365 Builder.defineMacro("__XOP__"); 3366 case FMA4: 3367 Builder.defineMacro("__FMA4__"); 3368 case SSE4A: 3369 Builder.defineMacro("__SSE4A__"); 3370 case NoXOP: 3371 break; 3372 } 3373 3374 if (HasFMA) 3375 Builder.defineMacro("__FMA__"); 3376 3377 if (HasF16C) 3378 Builder.defineMacro("__F16C__"); 3379 3380 if (HasAVX512CD) 3381 Builder.defineMacro("__AVX512CD__"); 3382 if (HasAVX512ER) 3383 Builder.defineMacro("__AVX512ER__"); 3384 if (HasAVX512PF) 3385 Builder.defineMacro("__AVX512PF__"); 3386 if (HasAVX512DQ) 3387 Builder.defineMacro("__AVX512DQ__"); 3388 if (HasAVX512BW) 3389 Builder.defineMacro("__AVX512BW__"); 3390 if (HasAVX512VL) 3391 Builder.defineMacro("__AVX512VL__"); 3392 if (HasAVX512VBMI) 3393 Builder.defineMacro("__AVX512VBMI__"); 3394 if (HasAVX512IFMA) 3395 Builder.defineMacro("__AVX512IFMA__"); 3396 3397 if (HasSHA) 3398 Builder.defineMacro("__SHA__"); 3399 3400 if (HasFXSR) 3401 Builder.defineMacro("__FXSR__"); 3402 if (HasXSAVE) 3403 Builder.defineMacro("__XSAVE__"); 3404 if (HasXSAVEOPT) 3405 Builder.defineMacro("__XSAVEOPT__"); 3406 if (HasXSAVEC) 3407 Builder.defineMacro("__XSAVEC__"); 3408 if (HasXSAVES) 3409 Builder.defineMacro("__XSAVES__"); 3410 if (HasPKU) 3411 Builder.defineMacro("__PKU__"); 3412 if (HasCX16) 3413 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3414 3415 // Each case falls through to the previous one here. 3416 switch (SSELevel) { 3417 case AVX512F: 3418 Builder.defineMacro("__AVX512F__"); 3419 case AVX2: 3420 Builder.defineMacro("__AVX2__"); 3421 case AVX: 3422 Builder.defineMacro("__AVX__"); 3423 case SSE42: 3424 Builder.defineMacro("__SSE4_2__"); 3425 case SSE41: 3426 Builder.defineMacro("__SSE4_1__"); 3427 case SSSE3: 3428 Builder.defineMacro("__SSSE3__"); 3429 case SSE3: 3430 Builder.defineMacro("__SSE3__"); 3431 case SSE2: 3432 Builder.defineMacro("__SSE2__"); 3433 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3434 case SSE1: 3435 Builder.defineMacro("__SSE__"); 3436 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3437 case NoSSE: 3438 break; 3439 } 3440 3441 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3442 switch (SSELevel) { 3443 case AVX512F: 3444 case AVX2: 3445 case AVX: 3446 case SSE42: 3447 case SSE41: 3448 case SSSE3: 3449 case SSE3: 3450 case SSE2: 3451 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3452 break; 3453 case SSE1: 3454 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3455 break; 3456 default: 3457 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3458 } 3459 } 3460 3461 // Each case falls through to the previous one here. 3462 switch (MMX3DNowLevel) { 3463 case AMD3DNowAthlon: 3464 Builder.defineMacro("__3dNOW_A__"); 3465 case AMD3DNow: 3466 Builder.defineMacro("__3dNOW__"); 3467 case MMX: 3468 Builder.defineMacro("__MMX__"); 3469 case NoMMX3DNow: 3470 break; 3471 } 3472 3473 if (CPU >= CK_i486) { 3474 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3475 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3476 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3477 } 3478 if (CPU >= CK_i586) 3479 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3480 } 3481 3482 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3483 return llvm::StringSwitch<bool>(Feature) 3484 .Case("aes", HasAES) 3485 .Case("avx", SSELevel >= AVX) 3486 .Case("avx2", SSELevel >= AVX2) 3487 .Case("avx512f", SSELevel >= AVX512F) 3488 .Case("avx512cd", HasAVX512CD) 3489 .Case("avx512er", HasAVX512ER) 3490 .Case("avx512pf", HasAVX512PF) 3491 .Case("avx512dq", HasAVX512DQ) 3492 .Case("avx512bw", HasAVX512BW) 3493 .Case("avx512vl", HasAVX512VL) 3494 .Case("avx512vbmi", HasAVX512VBMI) 3495 .Case("avx512ifma", HasAVX512IFMA) 3496 .Case("bmi", HasBMI) 3497 .Case("bmi2", HasBMI2) 3498 .Case("clflushopt", HasCLFLUSHOPT) 3499 .Case("clwb", HasCLWB) 3500 .Case("cx16", HasCX16) 3501 .Case("f16c", HasF16C) 3502 .Case("fma", HasFMA) 3503 .Case("fma4", XOPLevel >= FMA4) 3504 .Case("fsgsbase", HasFSGSBASE) 3505 .Case("fxsr", HasFXSR) 3506 .Case("lzcnt", HasLZCNT) 3507 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3508 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3509 .Case("mmx", MMX3DNowLevel >= MMX) 3510 .Case("movbe", HasMOVBE) 3511 .Case("mpx", HasMPX) 3512 .Case("pclmul", HasPCLMUL) 3513 .Case("pcommit", HasPCOMMIT) 3514 .Case("pku", HasPKU) 3515 .Case("popcnt", HasPOPCNT) 3516 .Case("prefetchwt1", HasPREFETCHWT1) 3517 .Case("prfchw", HasPRFCHW) 3518 .Case("rdrnd", HasRDRND) 3519 .Case("rdseed", HasRDSEED) 3520 .Case("rtm", HasRTM) 3521 .Case("sgx", HasSGX) 3522 .Case("sha", HasSHA) 3523 .Case("sse", SSELevel >= SSE1) 3524 .Case("sse2", SSELevel >= SSE2) 3525 .Case("sse3", SSELevel >= SSE3) 3526 .Case("ssse3", SSELevel >= SSSE3) 3527 .Case("sse4.1", SSELevel >= SSE41) 3528 .Case("sse4.2", SSELevel >= SSE42) 3529 .Case("sse4a", XOPLevel >= SSE4A) 3530 .Case("tbm", HasTBM) 3531 .Case("umip", HasUMIP) 3532 .Case("x86", true) 3533 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3534 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3535 .Case("xop", XOPLevel >= XOP) 3536 .Case("xsave", HasXSAVE) 3537 .Case("xsavec", HasXSAVEC) 3538 .Case("xsaves", HasXSAVES) 3539 .Case("xsaveopt", HasXSAVEOPT) 3540 .Default(false); 3541 } 3542 3543 // We can't use a generic validation scheme for the features accepted here 3544 // versus subtarget features accepted in the target attribute because the 3545 // bitfield structure that's initialized in the runtime only supports the 3546 // below currently rather than the full range of subtarget features. (See 3547 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3548 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3549 return llvm::StringSwitch<bool>(FeatureStr) 3550 .Case("cmov", true) 3551 .Case("mmx", true) 3552 .Case("popcnt", true) 3553 .Case("sse", true) 3554 .Case("sse2", true) 3555 .Case("sse3", true) 3556 .Case("sse4.1", true) 3557 .Case("sse4.2", true) 3558 .Case("avx", true) 3559 .Case("avx2", true) 3560 .Case("sse4a", true) 3561 .Case("fma4", true) 3562 .Case("xop", true) 3563 .Case("fma", true) 3564 .Case("avx512f", true) 3565 .Case("bmi", true) 3566 .Case("bmi2", true) 3567 .Default(false); 3568 } 3569 3570 bool 3571 X86TargetInfo::validateAsmConstraint(const char *&Name, 3572 TargetInfo::ConstraintInfo &Info) const { 3573 switch (*Name) { 3574 default: return false; 3575 // Constant constraints. 3576 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3577 // instructions. 3578 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3579 // x86_64 instructions. 3580 case 's': 3581 Info.setRequiresImmediate(); 3582 return true; 3583 case 'I': 3584 Info.setRequiresImmediate(0, 31); 3585 return true; 3586 case 'J': 3587 Info.setRequiresImmediate(0, 63); 3588 return true; 3589 case 'K': 3590 Info.setRequiresImmediate(-128, 127); 3591 return true; 3592 case 'L': 3593 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3594 return true; 3595 case 'M': 3596 Info.setRequiresImmediate(0, 3); 3597 return true; 3598 case 'N': 3599 Info.setRequiresImmediate(0, 255); 3600 return true; 3601 case 'O': 3602 Info.setRequiresImmediate(0, 127); 3603 return true; 3604 // Register constraints. 3605 case 'Y': // 'Y' is the first character for several 2-character constraints. 3606 // Shift the pointer to the second character of the constraint. 3607 Name++; 3608 switch (*Name) { 3609 default: 3610 return false; 3611 case '0': // First SSE register. 3612 case 't': // Any SSE register, when SSE2 is enabled. 3613 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3614 case 'm': // Any MMX register, when inter-unit moves enabled. 3615 Info.setAllowsRegister(); 3616 return true; 3617 } 3618 case 'f': // Any x87 floating point stack register. 3619 // Constraint 'f' cannot be used for output operands. 3620 if (Info.ConstraintStr[0] == '=') 3621 return false; 3622 Info.setAllowsRegister(); 3623 return true; 3624 case 'a': // eax. 3625 case 'b': // ebx. 3626 case 'c': // ecx. 3627 case 'd': // edx. 3628 case 'S': // esi. 3629 case 'D': // edi. 3630 case 'A': // edx:eax. 3631 case 't': // Top of floating point stack. 3632 case 'u': // Second from top of floating point stack. 3633 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3634 case 'y': // Any MMX register. 3635 case 'x': // Any SSE register. 3636 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3637 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3638 case 'l': // "Index" registers: any general register that can be used as an 3639 // index in a base+index memory access. 3640 Info.setAllowsRegister(); 3641 return true; 3642 // Floating point constant constraints. 3643 case 'C': // SSE floating point constant. 3644 case 'G': // x87 floating point constant. 3645 return true; 3646 } 3647 } 3648 3649 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3650 unsigned Size) const { 3651 // Strip off constraint modifiers. 3652 while (Constraint[0] == '=' || 3653 Constraint[0] == '+' || 3654 Constraint[0] == '&') 3655 Constraint = Constraint.substr(1); 3656 3657 return validateOperandSize(Constraint, Size); 3658 } 3659 3660 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3661 unsigned Size) const { 3662 return validateOperandSize(Constraint, Size); 3663 } 3664 3665 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3666 unsigned Size) const { 3667 switch (Constraint[0]) { 3668 default: break; 3669 case 'y': 3670 return Size <= 64; 3671 case 'f': 3672 case 't': 3673 case 'u': 3674 return Size <= 128; 3675 case 'x': 3676 if (SSELevel >= AVX512F) 3677 // 512-bit zmm registers can be used if target supports AVX512F. 3678 return Size <= 512U; 3679 else if (SSELevel >= AVX) 3680 // 256-bit ymm registers can be used if target supports AVX. 3681 return Size <= 256U; 3682 return Size <= 128U; 3683 case 'Y': 3684 // 'Y' is the first character for several 2-character constraints. 3685 switch (Constraint[1]) { 3686 default: break; 3687 case 'm': 3688 // 'Ym' is synonymous with 'y'. 3689 return Size <= 64; 3690 case 'i': 3691 case 't': 3692 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3693 if (SSELevel >= AVX512F) 3694 return Size <= 512U; 3695 else if (SSELevel >= AVX) 3696 return Size <= 256U; 3697 return SSELevel >= SSE2 && Size <= 128U; 3698 } 3699 3700 } 3701 3702 return true; 3703 } 3704 3705 std::string 3706 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3707 switch (*Constraint) { 3708 case 'a': return std::string("{ax}"); 3709 case 'b': return std::string("{bx}"); 3710 case 'c': return std::string("{cx}"); 3711 case 'd': return std::string("{dx}"); 3712 case 'S': return std::string("{si}"); 3713 case 'D': return std::string("{di}"); 3714 case 'p': // address 3715 return std::string("im"); 3716 case 't': // top of floating point stack. 3717 return std::string("{st}"); 3718 case 'u': // second from top of floating point stack. 3719 return std::string("{st(1)}"); // second from top of floating point stack. 3720 default: 3721 return std::string(1, *Constraint); 3722 } 3723 } 3724 3725 // X86-32 generic target 3726 class X86_32TargetInfo : public X86TargetInfo { 3727 public: 3728 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3729 DoubleAlign = LongLongAlign = 32; 3730 LongDoubleWidth = 96; 3731 LongDoubleAlign = 32; 3732 SuitableAlign = 128; 3733 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3734 SizeType = UnsignedInt; 3735 PtrDiffType = SignedInt; 3736 IntPtrType = SignedInt; 3737 RegParmMax = 3; 3738 3739 // Use fpret for all types. 3740 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3741 (1 << TargetInfo::Double) | 3742 (1 << TargetInfo::LongDouble)); 3743 3744 // x86-32 has atomics up to 8 bytes 3745 // FIXME: Check that we actually have cmpxchg8b before setting 3746 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3747 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3748 } 3749 BuiltinVaListKind getBuiltinVaListKind() const override { 3750 return TargetInfo::CharPtrBuiltinVaList; 3751 } 3752 3753 int getEHDataRegisterNumber(unsigned RegNo) const override { 3754 if (RegNo == 0) return 0; 3755 if (RegNo == 1) return 2; 3756 return -1; 3757 } 3758 bool validateOperandSize(StringRef Constraint, 3759 unsigned Size) const override { 3760 switch (Constraint[0]) { 3761 default: break; 3762 case 'R': 3763 case 'q': 3764 case 'Q': 3765 case 'a': 3766 case 'b': 3767 case 'c': 3768 case 'd': 3769 case 'S': 3770 case 'D': 3771 return Size <= 32; 3772 case 'A': 3773 return Size <= 64; 3774 } 3775 3776 return X86TargetInfo::validateOperandSize(Constraint, Size); 3777 } 3778 }; 3779 3780 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3781 public: 3782 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3783 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3784 3785 unsigned getFloatEvalMethod() const override { 3786 unsigned Major, Minor, Micro; 3787 getTriple().getOSVersion(Major, Minor, Micro); 3788 // New NetBSD uses the default rounding mode. 3789 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3790 return X86_32TargetInfo::getFloatEvalMethod(); 3791 // NetBSD before 6.99.26 defaults to "double" rounding. 3792 return 1; 3793 } 3794 }; 3795 3796 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3797 public: 3798 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3799 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3800 SizeType = UnsignedLong; 3801 IntPtrType = SignedLong; 3802 PtrDiffType = SignedLong; 3803 } 3804 }; 3805 3806 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3807 public: 3808 BitrigI386TargetInfo(const llvm::Triple &Triple) 3809 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3810 SizeType = UnsignedLong; 3811 IntPtrType = SignedLong; 3812 PtrDiffType = SignedLong; 3813 } 3814 }; 3815 3816 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3817 public: 3818 DarwinI386TargetInfo(const llvm::Triple &Triple) 3819 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3820 LongDoubleWidth = 128; 3821 LongDoubleAlign = 128; 3822 SuitableAlign = 128; 3823 MaxVectorAlign = 256; 3824 // The watchOS simulator uses the builtin bool type for Objective-C. 3825 llvm::Triple T = llvm::Triple(Triple); 3826 if (T.isWatchOS()) 3827 UseSignedCharForObjCBool = false; 3828 SizeType = UnsignedLong; 3829 IntPtrType = SignedLong; 3830 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 3831 HasAlignMac68kSupport = true; 3832 } 3833 3834 bool handleTargetFeatures(std::vector<std::string> &Features, 3835 DiagnosticsEngine &Diags) override { 3836 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3837 Diags)) 3838 return false; 3839 // We now know the features we have: we can decide how to align vectors. 3840 MaxVectorAlign = 3841 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3842 return true; 3843 } 3844 }; 3845 3846 // x86-32 Windows target 3847 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3848 public: 3849 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3850 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3851 WCharType = UnsignedShort; 3852 DoubleAlign = LongLongAlign = 64; 3853 bool IsWinCOFF = 3854 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3855 resetDataLayout(IsWinCOFF 3856 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3857 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3858 } 3859 void getTargetDefines(const LangOptions &Opts, 3860 MacroBuilder &Builder) const override { 3861 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3862 } 3863 }; 3864 3865 // x86-32 Windows Visual Studio target 3866 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3867 public: 3868 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3869 : WindowsX86_32TargetInfo(Triple) { 3870 LongDoubleWidth = LongDoubleAlign = 64; 3871 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3872 } 3873 void getTargetDefines(const LangOptions &Opts, 3874 MacroBuilder &Builder) const override { 3875 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3876 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3877 // The value of the following reflects processor type. 3878 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3879 // We lost the original triple, so we use the default. 3880 Builder.defineMacro("_M_IX86", "600"); 3881 } 3882 }; 3883 3884 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3885 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3886 // supports __declspec natively under -fms-extensions, but we define a no-op 3887 // __declspec macro anyway for pre-processor compatibility. 3888 if (Opts.MicrosoftExt) 3889 Builder.defineMacro("__declspec", "__declspec"); 3890 else 3891 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3892 3893 if (!Opts.MicrosoftExt) { 3894 // Provide macros for all the calling convention keywords. Provide both 3895 // single and double underscore prefixed variants. These are available on 3896 // x64 as well as x86, even though they have no effect. 3897 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3898 for (const char *CC : CCs) { 3899 std::string GCCSpelling = "__attribute__((__"; 3900 GCCSpelling += CC; 3901 GCCSpelling += "__))"; 3902 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3903 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3904 } 3905 } 3906 } 3907 3908 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3909 Builder.defineMacro("__MSVCRT__"); 3910 Builder.defineMacro("__MINGW32__"); 3911 addCygMingDefines(Opts, Builder); 3912 } 3913 3914 // x86-32 MinGW target 3915 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3916 public: 3917 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3918 : WindowsX86_32TargetInfo(Triple) {} 3919 void getTargetDefines(const LangOptions &Opts, 3920 MacroBuilder &Builder) const override { 3921 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3922 DefineStd(Builder, "WIN32", Opts); 3923 DefineStd(Builder, "WINNT", Opts); 3924 Builder.defineMacro("_X86_"); 3925 addMinGWDefines(Opts, Builder); 3926 } 3927 }; 3928 3929 // x86-32 Cygwin target 3930 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3931 public: 3932 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3933 : X86_32TargetInfo(Triple) { 3934 WCharType = UnsignedShort; 3935 DoubleAlign = LongLongAlign = 64; 3936 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 3937 } 3938 void getTargetDefines(const LangOptions &Opts, 3939 MacroBuilder &Builder) const override { 3940 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3941 Builder.defineMacro("_X86_"); 3942 Builder.defineMacro("__CYGWIN__"); 3943 Builder.defineMacro("__CYGWIN32__"); 3944 addCygMingDefines(Opts, Builder); 3945 DefineStd(Builder, "unix", Opts); 3946 if (Opts.CPlusPlus) 3947 Builder.defineMacro("_GNU_SOURCE"); 3948 } 3949 }; 3950 3951 // x86-32 Haiku target 3952 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3953 public: 3954 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3955 SizeType = UnsignedLong; 3956 IntPtrType = SignedLong; 3957 PtrDiffType = SignedLong; 3958 ProcessIDType = SignedLong; 3959 this->TLSSupported = false; 3960 } 3961 void getTargetDefines(const LangOptions &Opts, 3962 MacroBuilder &Builder) const override { 3963 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3964 Builder.defineMacro("__INTEL__"); 3965 Builder.defineMacro("__HAIKU__"); 3966 } 3967 }; 3968 3969 // X86-32 MCU target 3970 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3971 public: 3972 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3973 LongDoubleWidth = 64; 3974 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3975 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 3976 WIntType = UnsignedInt; 3977 } 3978 3979 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3980 // On MCU we support only C calling convention. 3981 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3982 } 3983 3984 void getTargetDefines(const LangOptions &Opts, 3985 MacroBuilder &Builder) const override { 3986 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3987 Builder.defineMacro("__iamcu"); 3988 Builder.defineMacro("__iamcu__"); 3989 } 3990 3991 bool allowsLargerPreferedTypeAlignment() const override { 3992 return false; 3993 } 3994 }; 3995 3996 // RTEMS Target 3997 template<typename Target> 3998 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3999 protected: 4000 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4001 MacroBuilder &Builder) const override { 4002 // RTEMS defines; list based off of gcc output 4003 4004 Builder.defineMacro("__rtems__"); 4005 Builder.defineMacro("__ELF__"); 4006 } 4007 4008 public: 4009 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4010 switch (Triple.getArch()) { 4011 default: 4012 case llvm::Triple::x86: 4013 // this->MCountName = ".mcount"; 4014 break; 4015 case llvm::Triple::mips: 4016 case llvm::Triple::mipsel: 4017 case llvm::Triple::ppc: 4018 case llvm::Triple::ppc64: 4019 case llvm::Triple::ppc64le: 4020 // this->MCountName = "_mcount"; 4021 break; 4022 case llvm::Triple::arm: 4023 // this->MCountName = "__mcount"; 4024 break; 4025 } 4026 } 4027 }; 4028 4029 // x86-32 RTEMS target 4030 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4031 public: 4032 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4033 SizeType = UnsignedLong; 4034 IntPtrType = SignedLong; 4035 PtrDiffType = SignedLong; 4036 } 4037 void getTargetDefines(const LangOptions &Opts, 4038 MacroBuilder &Builder) const override { 4039 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4040 Builder.defineMacro("__INTEL__"); 4041 Builder.defineMacro("__rtems__"); 4042 } 4043 }; 4044 4045 // x86-64 generic target 4046 class X86_64TargetInfo : public X86TargetInfo { 4047 public: 4048 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4049 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4050 bool IsWinCOFF = 4051 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4052 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4053 LongDoubleWidth = 128; 4054 LongDoubleAlign = 128; 4055 LargeArrayMinWidth = 128; 4056 LargeArrayAlign = 128; 4057 SuitableAlign = 128; 4058 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4059 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4060 IntPtrType = IsX32 ? SignedInt : SignedLong; 4061 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4062 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4063 RegParmMax = 6; 4064 4065 // Pointers are 32-bit in x32. 4066 resetDataLayout(IsX32 4067 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4068 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4069 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4070 4071 // Use fpret only for long double. 4072 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4073 4074 // Use fp2ret for _Complex long double. 4075 ComplexLongDoubleUsesFP2Ret = true; 4076 4077 // Make __builtin_ms_va_list available. 4078 HasBuiltinMSVaList = true; 4079 4080 // x86-64 has atomics up to 16 bytes. 4081 MaxAtomicPromoteWidth = 128; 4082 MaxAtomicInlineWidth = 128; 4083 } 4084 BuiltinVaListKind getBuiltinVaListKind() const override { 4085 return TargetInfo::X86_64ABIBuiltinVaList; 4086 } 4087 4088 int getEHDataRegisterNumber(unsigned RegNo) const override { 4089 if (RegNo == 0) return 0; 4090 if (RegNo == 1) return 1; 4091 return -1; 4092 } 4093 4094 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4095 switch (CC) { 4096 case CC_C: 4097 case CC_Swift: 4098 case CC_X86VectorCall: 4099 case CC_IntelOclBicc: 4100 case CC_X86_64Win64: 4101 case CC_PreserveMost: 4102 case CC_PreserveAll: 4103 return CCCR_OK; 4104 default: 4105 return CCCR_Warning; 4106 } 4107 } 4108 4109 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4110 return CC_C; 4111 } 4112 4113 // for x32 we need it here explicitly 4114 bool hasInt128Type() const override { return true; } 4115 unsigned getUnwindWordWidth() const override { return 64; } 4116 unsigned getRegisterWidth() const override { return 64; } 4117 4118 bool validateGlobalRegisterVariable(StringRef RegName, 4119 unsigned RegSize, 4120 bool &HasSizeMismatch) const override { 4121 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4122 // handle. 4123 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4124 // Check that the register size is 64-bit. 4125 HasSizeMismatch = RegSize != 64; 4126 return true; 4127 } 4128 4129 // Check if the register is a 32-bit register the backend can handle. 4130 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4131 HasSizeMismatch); 4132 } 4133 }; 4134 4135 // x86-64 Windows target 4136 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4137 public: 4138 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4139 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4140 WCharType = UnsignedShort; 4141 LongWidth = LongAlign = 32; 4142 DoubleAlign = LongLongAlign = 64; 4143 IntMaxType = SignedLongLong; 4144 Int64Type = SignedLongLong; 4145 SizeType = UnsignedLongLong; 4146 PtrDiffType = SignedLongLong; 4147 IntPtrType = SignedLongLong; 4148 } 4149 4150 void getTargetDefines(const LangOptions &Opts, 4151 MacroBuilder &Builder) const override { 4152 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4153 Builder.defineMacro("_WIN64"); 4154 } 4155 4156 BuiltinVaListKind getBuiltinVaListKind() const override { 4157 return TargetInfo::CharPtrBuiltinVaList; 4158 } 4159 4160 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4161 switch (CC) { 4162 case CC_X86StdCall: 4163 case CC_X86ThisCall: 4164 case CC_X86FastCall: 4165 return CCCR_Ignore; 4166 case CC_C: 4167 case CC_X86VectorCall: 4168 case CC_IntelOclBicc: 4169 case CC_X86_64SysV: 4170 return CCCR_OK; 4171 default: 4172 return CCCR_Warning; 4173 } 4174 } 4175 }; 4176 4177 // x86-64 Windows Visual Studio target 4178 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4179 public: 4180 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4181 : WindowsX86_64TargetInfo(Triple) { 4182 LongDoubleWidth = LongDoubleAlign = 64; 4183 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4184 } 4185 void getTargetDefines(const LangOptions &Opts, 4186 MacroBuilder &Builder) const override { 4187 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4188 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4189 Builder.defineMacro("_M_X64", "100"); 4190 Builder.defineMacro("_M_AMD64", "100"); 4191 } 4192 }; 4193 4194 // x86-64 MinGW target 4195 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4196 public: 4197 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4198 : WindowsX86_64TargetInfo(Triple) { 4199 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4200 // with x86 FP ops. Weird. 4201 LongDoubleWidth = LongDoubleAlign = 128; 4202 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4203 } 4204 4205 void getTargetDefines(const LangOptions &Opts, 4206 MacroBuilder &Builder) const override { 4207 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4208 DefineStd(Builder, "WIN64", Opts); 4209 Builder.defineMacro("__MINGW64__"); 4210 addMinGWDefines(Opts, Builder); 4211 4212 // GCC defines this macro when it is using __gxx_personality_seh0. 4213 if (!Opts.SjLjExceptions) 4214 Builder.defineMacro("__SEH__"); 4215 } 4216 }; 4217 4218 // x86-64 Cygwin target 4219 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4220 public: 4221 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4222 : X86_64TargetInfo(Triple) { 4223 TLSSupported = false; 4224 WCharType = UnsignedShort; 4225 } 4226 void getTargetDefines(const LangOptions &Opts, 4227 MacroBuilder &Builder) const override { 4228 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4229 Builder.defineMacro("__x86_64__"); 4230 Builder.defineMacro("__CYGWIN__"); 4231 Builder.defineMacro("__CYGWIN64__"); 4232 addCygMingDefines(Opts, Builder); 4233 DefineStd(Builder, "unix", Opts); 4234 if (Opts.CPlusPlus) 4235 Builder.defineMacro("_GNU_SOURCE"); 4236 4237 // GCC defines this macro when it is using __gxx_personality_seh0. 4238 if (!Opts.SjLjExceptions) 4239 Builder.defineMacro("__SEH__"); 4240 } 4241 }; 4242 4243 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4244 public: 4245 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4246 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4247 Int64Type = SignedLongLong; 4248 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4249 llvm::Triple T = llvm::Triple(Triple); 4250 if (T.isiOS()) 4251 UseSignedCharForObjCBool = false; 4252 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4253 } 4254 4255 bool handleTargetFeatures(std::vector<std::string> &Features, 4256 DiagnosticsEngine &Diags) override { 4257 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4258 Diags)) 4259 return false; 4260 // We now know the features we have: we can decide how to align vectors. 4261 MaxVectorAlign = 4262 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4263 return true; 4264 } 4265 }; 4266 4267 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4268 public: 4269 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4270 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4271 IntMaxType = SignedLongLong; 4272 Int64Type = SignedLongLong; 4273 } 4274 }; 4275 4276 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4277 public: 4278 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4279 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4280 IntMaxType = SignedLongLong; 4281 Int64Type = SignedLongLong; 4282 } 4283 }; 4284 4285 class ARMTargetInfo : public TargetInfo { 4286 // Possible FPU choices. 4287 enum FPUMode { 4288 VFP2FPU = (1 << 0), 4289 VFP3FPU = (1 << 1), 4290 VFP4FPU = (1 << 2), 4291 NeonFPU = (1 << 3), 4292 FPARMV8 = (1 << 4) 4293 }; 4294 4295 // Possible HWDiv features. 4296 enum HWDivMode { 4297 HWDivThumb = (1 << 0), 4298 HWDivARM = (1 << 1) 4299 }; 4300 4301 static bool FPUModeIsVFP(FPUMode Mode) { 4302 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4303 } 4304 4305 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4306 static const char * const GCCRegNames[]; 4307 4308 std::string ABI, CPU; 4309 4310 StringRef CPUProfile; 4311 StringRef CPUAttr; 4312 4313 enum { 4314 FP_Default, 4315 FP_VFP, 4316 FP_Neon 4317 } FPMath; 4318 4319 unsigned ArchISA; 4320 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4321 unsigned ArchProfile; 4322 unsigned ArchVersion; 4323 4324 unsigned FPU : 5; 4325 4326 unsigned IsAAPCS : 1; 4327 unsigned HWDiv : 2; 4328 4329 // Initialized via features. 4330 unsigned SoftFloat : 1; 4331 unsigned SoftFloatABI : 1; 4332 4333 unsigned CRC : 1; 4334 unsigned Crypto : 1; 4335 unsigned DSP : 1; 4336 unsigned Unaligned : 1; 4337 4338 enum { 4339 LDREX_B = (1 << 0), /// byte (8-bit) 4340 LDREX_H = (1 << 1), /// half (16-bit) 4341 LDREX_W = (1 << 2), /// word (32-bit) 4342 LDREX_D = (1 << 3), /// double (64-bit) 4343 }; 4344 4345 uint32_t LDREX; 4346 4347 // ACLE 6.5.1 Hardware floating point 4348 enum { 4349 HW_FP_HP = (1 << 1), /// half (16-bit) 4350 HW_FP_SP = (1 << 2), /// single (32-bit) 4351 HW_FP_DP = (1 << 3), /// double (64-bit) 4352 }; 4353 uint32_t HW_FP; 4354 4355 static const Builtin::Info BuiltinInfo[]; 4356 4357 void setABIAAPCS() { 4358 IsAAPCS = true; 4359 4360 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4361 const llvm::Triple &T = getTriple(); 4362 4363 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4364 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4365 T.getOS() == llvm::Triple::Bitrig) 4366 SizeType = UnsignedLong; 4367 else 4368 SizeType = UnsignedInt; 4369 4370 switch (T.getOS()) { 4371 case llvm::Triple::NetBSD: 4372 WCharType = SignedInt; 4373 break; 4374 case llvm::Triple::Win32: 4375 WCharType = UnsignedShort; 4376 break; 4377 case llvm::Triple::Linux: 4378 default: 4379 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4380 WCharType = UnsignedInt; 4381 break; 4382 } 4383 4384 UseBitFieldTypeAlignment = true; 4385 4386 ZeroLengthBitfieldBoundary = 0; 4387 4388 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4389 // so set preferred for small types to 32. 4390 if (T.isOSBinFormatMachO()) { 4391 resetDataLayout(BigEndian 4392 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4393 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4394 } else if (T.isOSWindows()) { 4395 assert(!BigEndian && "Windows on ARM does not support big endian"); 4396 resetDataLayout("e" 4397 "-m:w" 4398 "-p:32:32" 4399 "-i64:64" 4400 "-v128:64:128" 4401 "-a:0:32" 4402 "-n32" 4403 "-S64"); 4404 } else if (T.isOSNaCl()) { 4405 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4406 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4407 } else { 4408 resetDataLayout(BigEndian 4409 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4410 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4411 } 4412 4413 // FIXME: Enumerated types are variable width in straight AAPCS. 4414 } 4415 4416 void setABIAPCS(bool IsAAPCS16) { 4417 const llvm::Triple &T = getTriple(); 4418 4419 IsAAPCS = false; 4420 4421 if (IsAAPCS16) 4422 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4423 else 4424 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4425 4426 // size_t is unsigned int on FreeBSD. 4427 if (T.getOS() == llvm::Triple::FreeBSD) 4428 SizeType = UnsignedInt; 4429 else 4430 SizeType = UnsignedLong; 4431 4432 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4433 WCharType = SignedInt; 4434 4435 // Do not respect the alignment of bit-field types when laying out 4436 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4437 UseBitFieldTypeAlignment = false; 4438 4439 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4440 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4441 /// gcc. 4442 ZeroLengthBitfieldBoundary = 32; 4443 4444 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4445 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4446 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4447 } else if (T.isOSBinFormatMachO()) 4448 resetDataLayout( 4449 BigEndian 4450 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4451 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4452 else 4453 resetDataLayout( 4454 BigEndian 4455 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4456 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4457 4458 // FIXME: Override "preferred align" for double and long long. 4459 } 4460 4461 void setArchInfo() { 4462 StringRef ArchName = getTriple().getArchName(); 4463 4464 ArchISA = llvm::ARM::parseArchISA(ArchName); 4465 CPU = llvm::ARM::getDefaultCPU(ArchName); 4466 unsigned AK = llvm::ARM::parseArch(ArchName); 4467 if (AK != llvm::ARM::AK_INVALID) 4468 ArchKind = AK; 4469 setArchInfo(ArchKind); 4470 } 4471 4472 void setArchInfo(unsigned Kind) { 4473 StringRef SubArch; 4474 4475 // cache TargetParser info 4476 ArchKind = Kind; 4477 SubArch = llvm::ARM::getSubArch(ArchKind); 4478 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4479 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4480 4481 // cache CPU related strings 4482 CPUAttr = getCPUAttr(); 4483 CPUProfile = getCPUProfile(); 4484 } 4485 4486 void setAtomic() { 4487 // when triple does not specify a sub arch, 4488 // then we are not using inline atomics 4489 bool ShouldUseInlineAtomic = 4490 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4491 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4492 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4493 if (ArchProfile == llvm::ARM::PK_M) { 4494 MaxAtomicPromoteWidth = 32; 4495 if (ShouldUseInlineAtomic) 4496 MaxAtomicInlineWidth = 32; 4497 } 4498 else { 4499 MaxAtomicPromoteWidth = 64; 4500 if (ShouldUseInlineAtomic) 4501 MaxAtomicInlineWidth = 64; 4502 } 4503 } 4504 4505 bool isThumb() const { 4506 return (ArchISA == llvm::ARM::IK_THUMB); 4507 } 4508 4509 bool supportsThumb() const { 4510 return CPUAttr.count('T') || ArchVersion >= 6; 4511 } 4512 4513 bool supportsThumb2() const { 4514 return CPUAttr.equals("6T2") || 4515 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4516 } 4517 4518 StringRef getCPUAttr() const { 4519 // For most sub-arches, the build attribute CPU name is enough. 4520 // For Cortex variants, it's slightly different. 4521 switch(ArchKind) { 4522 default: 4523 return llvm::ARM::getCPUAttr(ArchKind); 4524 case llvm::ARM::AK_ARMV6M: 4525 return "6M"; 4526 case llvm::ARM::AK_ARMV7S: 4527 return "7S"; 4528 case llvm::ARM::AK_ARMV7A: 4529 return "7A"; 4530 case llvm::ARM::AK_ARMV7R: 4531 return "7R"; 4532 case llvm::ARM::AK_ARMV7M: 4533 return "7M"; 4534 case llvm::ARM::AK_ARMV7EM: 4535 return "7EM"; 4536 case llvm::ARM::AK_ARMV8A: 4537 return "8A"; 4538 case llvm::ARM::AK_ARMV8_1A: 4539 return "8_1A"; 4540 case llvm::ARM::AK_ARMV8_2A: 4541 return "8_2A"; 4542 case llvm::ARM::AK_ARMV8MBaseline: 4543 return "8M_BASE"; 4544 case llvm::ARM::AK_ARMV8MMainline: 4545 return "8M_MAIN"; 4546 } 4547 } 4548 4549 StringRef getCPUProfile() const { 4550 switch(ArchProfile) { 4551 case llvm::ARM::PK_A: 4552 return "A"; 4553 case llvm::ARM::PK_R: 4554 return "R"; 4555 case llvm::ARM::PK_M: 4556 return "M"; 4557 default: 4558 return ""; 4559 } 4560 } 4561 4562 public: 4563 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4564 : TargetInfo(Triple), FPMath(FP_Default), 4565 IsAAPCS(true), LDREX(0), HW_FP(0) { 4566 BigEndian = IsBigEndian; 4567 4568 switch (getTriple().getOS()) { 4569 case llvm::Triple::NetBSD: 4570 PtrDiffType = SignedLong; 4571 break; 4572 default: 4573 PtrDiffType = SignedInt; 4574 break; 4575 } 4576 4577 // Cache arch related info. 4578 setArchInfo(); 4579 4580 // {} in inline assembly are neon specifiers, not assembly variant 4581 // specifiers. 4582 NoAsmVariants = true; 4583 4584 // FIXME: This duplicates code from the driver that sets the -target-abi 4585 // option - this code is used if -target-abi isn't passed and should 4586 // be unified in some way. 4587 if (Triple.isOSBinFormatMachO()) { 4588 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4589 // the frontend matches that. 4590 if (Triple.getEnvironment() == llvm::Triple::EABI || 4591 Triple.getOS() == llvm::Triple::UnknownOS || 4592 StringRef(CPU).startswith("cortex-m")) { 4593 setABI("aapcs"); 4594 } else if (Triple.isWatchABI()) { 4595 setABI("aapcs16"); 4596 } else { 4597 setABI("apcs-gnu"); 4598 } 4599 } else if (Triple.isOSWindows()) { 4600 // FIXME: this is invalid for WindowsCE 4601 setABI("aapcs"); 4602 } else { 4603 // Select the default based on the platform. 4604 switch (Triple.getEnvironment()) { 4605 case llvm::Triple::Android: 4606 case llvm::Triple::GNUEABI: 4607 case llvm::Triple::GNUEABIHF: 4608 setABI("aapcs-linux"); 4609 break; 4610 case llvm::Triple::EABIHF: 4611 case llvm::Triple::EABI: 4612 setABI("aapcs"); 4613 break; 4614 case llvm::Triple::GNU: 4615 setABI("apcs-gnu"); 4616 break; 4617 default: 4618 if (Triple.getOS() == llvm::Triple::NetBSD) 4619 setABI("apcs-gnu"); 4620 else 4621 setABI("aapcs"); 4622 break; 4623 } 4624 } 4625 4626 // ARM targets default to using the ARM C++ ABI. 4627 TheCXXABI.set(TargetCXXABI::GenericARM); 4628 4629 // ARM has atomics up to 8 bytes 4630 setAtomic(); 4631 4632 // Do force alignment of members that follow zero length bitfields. If 4633 // the alignment of the zero-length bitfield is greater than the member 4634 // that follows it, `bar', `bar' will be aligned as the type of the 4635 // zero length bitfield. 4636 UseZeroLengthBitfieldAlignment = true; 4637 } 4638 4639 StringRef getABI() const override { return ABI; } 4640 4641 bool setABI(const std::string &Name) override { 4642 ABI = Name; 4643 4644 // The defaults (above) are for AAPCS, check if we need to change them. 4645 // 4646 // FIXME: We need support for -meabi... we could just mangle it into the 4647 // name. 4648 if (Name == "apcs-gnu" || Name == "aapcs16") { 4649 setABIAPCS(Name == "aapcs16"); 4650 return true; 4651 } 4652 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4653 setABIAAPCS(); 4654 return true; 4655 } 4656 return false; 4657 } 4658 4659 // FIXME: This should be based on Arch attributes, not CPU names. 4660 bool 4661 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4662 StringRef CPU, 4663 const std::vector<std::string> &FeaturesVec) const override { 4664 4665 std::vector<const char*> TargetFeatures; 4666 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4667 4668 // get default FPU features 4669 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4670 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4671 4672 // get default Extension features 4673 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4674 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4675 4676 for (const char *Feature : TargetFeatures) 4677 if (Feature[0] == '+') 4678 Features[Feature+1] = true; 4679 4680 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4681 } 4682 4683 bool handleTargetFeatures(std::vector<std::string> &Features, 4684 DiagnosticsEngine &Diags) override { 4685 FPU = 0; 4686 CRC = 0; 4687 Crypto = 0; 4688 DSP = 0; 4689 Unaligned = 1; 4690 SoftFloat = SoftFloatABI = false; 4691 HWDiv = 0; 4692 4693 // This does not diagnose illegal cases like having both 4694 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4695 uint32_t HW_FP_remove = 0; 4696 for (const auto &Feature : Features) { 4697 if (Feature == "+soft-float") { 4698 SoftFloat = true; 4699 } else if (Feature == "+soft-float-abi") { 4700 SoftFloatABI = true; 4701 } else if (Feature == "+vfp2") { 4702 FPU |= VFP2FPU; 4703 HW_FP |= HW_FP_SP | HW_FP_DP; 4704 } else if (Feature == "+vfp3") { 4705 FPU |= VFP3FPU; 4706 HW_FP |= HW_FP_SP | HW_FP_DP; 4707 } else if (Feature == "+vfp4") { 4708 FPU |= VFP4FPU; 4709 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4710 } else if (Feature == "+fp-armv8") { 4711 FPU |= FPARMV8; 4712 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4713 } else if (Feature == "+neon") { 4714 FPU |= NeonFPU; 4715 HW_FP |= HW_FP_SP | HW_FP_DP; 4716 } else if (Feature == "+hwdiv") { 4717 HWDiv |= HWDivThumb; 4718 } else if (Feature == "+hwdiv-arm") { 4719 HWDiv |= HWDivARM; 4720 } else if (Feature == "+crc") { 4721 CRC = 1; 4722 } else if (Feature == "+crypto") { 4723 Crypto = 1; 4724 } else if (Feature == "+dsp") { 4725 DSP = 1; 4726 } else if (Feature == "+fp-only-sp") { 4727 HW_FP_remove |= HW_FP_DP; 4728 } else if (Feature == "+strict-align") { 4729 Unaligned = 0; 4730 } else if (Feature == "+fp16") { 4731 HW_FP |= HW_FP_HP; 4732 } 4733 } 4734 HW_FP &= ~HW_FP_remove; 4735 4736 switch (ArchVersion) { 4737 case 6: 4738 if (ArchProfile == llvm::ARM::PK_M) 4739 LDREX = 0; 4740 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4741 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4742 else 4743 LDREX = LDREX_W; 4744 break; 4745 case 7: 4746 if (ArchProfile == llvm::ARM::PK_M) 4747 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4748 else 4749 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4750 break; 4751 case 8: 4752 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4753 } 4754 4755 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4756 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4757 return false; 4758 } 4759 4760 if (FPMath == FP_Neon) 4761 Features.push_back("+neonfp"); 4762 else if (FPMath == FP_VFP) 4763 Features.push_back("-neonfp"); 4764 4765 // Remove front-end specific options which the backend handles differently. 4766 auto Feature = 4767 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4768 if (Feature != Features.end()) 4769 Features.erase(Feature); 4770 4771 return true; 4772 } 4773 4774 bool hasFeature(StringRef Feature) const override { 4775 return llvm::StringSwitch<bool>(Feature) 4776 .Case("arm", true) 4777 .Case("aarch32", true) 4778 .Case("softfloat", SoftFloat) 4779 .Case("thumb", isThumb()) 4780 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4781 .Case("hwdiv", HWDiv & HWDivThumb) 4782 .Case("hwdiv-arm", HWDiv & HWDivARM) 4783 .Default(false); 4784 } 4785 4786 bool setCPU(const std::string &Name) override { 4787 if (Name != "generic") 4788 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4789 4790 if (ArchKind == llvm::ARM::AK_INVALID) 4791 return false; 4792 setAtomic(); 4793 CPU = Name; 4794 return true; 4795 } 4796 4797 bool setFPMath(StringRef Name) override; 4798 4799 void getTargetDefines(const LangOptions &Opts, 4800 MacroBuilder &Builder) const override { 4801 // Target identification. 4802 Builder.defineMacro("__arm"); 4803 Builder.defineMacro("__arm__"); 4804 4805 // Target properties. 4806 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4807 4808 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4809 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4810 if (getTriple().isWatchABI()) 4811 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4812 4813 if (!CPUAttr.empty()) 4814 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4815 4816 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4817 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4818 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4819 4820 if (ArchVersion >= 8) { 4821 // ACLE 6.5.7 Crypto Extension 4822 if (Crypto) 4823 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4824 // ACLE 6.5.8 CRC32 Extension 4825 if (CRC) 4826 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4827 // ACLE 6.5.10 Numeric Maximum and Minimum 4828 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4829 // ACLE 6.5.9 Directed Rounding 4830 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4831 } 4832 4833 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4834 // is not defined for the M-profile. 4835 // NOTE that the default profile is assumed to be 'A' 4836 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 4837 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4838 4839 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 4840 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 4841 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 4842 // v7 and v8 architectures excluding v8-M Baseline. 4843 if (supportsThumb2()) 4844 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4845 else if (supportsThumb()) 4846 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4847 4848 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4849 // instruction set such as ARM or Thumb. 4850 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4851 4852 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4853 4854 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4855 if (!CPUProfile.empty()) 4856 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4857 4858 // ACLE 6.4.3 Unaligned access supported in hardware 4859 if (Unaligned) 4860 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4861 4862 // ACLE 6.4.4 LDREX/STREX 4863 if (LDREX) 4864 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4865 4866 // ACLE 6.4.5 CLZ 4867 if (ArchVersion == 5 || 4868 (ArchVersion == 6 && CPUProfile != "M") || 4869 ArchVersion > 6) 4870 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4871 4872 // ACLE 6.5.1 Hardware Floating Point 4873 if (HW_FP) 4874 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4875 4876 // ACLE predefines. 4877 Builder.defineMacro("__ARM_ACLE", "200"); 4878 4879 // FP16 support (we currently only support IEEE format). 4880 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4881 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4882 4883 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4884 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4885 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4886 4887 // Subtarget options. 4888 4889 // FIXME: It's more complicated than this and we don't really support 4890 // interworking. 4891 // Windows on ARM does not "support" interworking 4892 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4893 Builder.defineMacro("__THUMB_INTERWORK__"); 4894 4895 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4896 // Embedded targets on Darwin follow AAPCS, but not EABI. 4897 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4898 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4899 Builder.defineMacro("__ARM_EABI__"); 4900 Builder.defineMacro("__ARM_PCS", "1"); 4901 4902 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4903 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4904 } 4905 4906 if (SoftFloat) 4907 Builder.defineMacro("__SOFTFP__"); 4908 4909 if (CPU == "xscale") 4910 Builder.defineMacro("__XSCALE__"); 4911 4912 if (isThumb()) { 4913 Builder.defineMacro("__THUMBEL__"); 4914 Builder.defineMacro("__thumb__"); 4915 if (supportsThumb2()) 4916 Builder.defineMacro("__thumb2__"); 4917 } 4918 4919 // ACLE 6.4.9 32-bit SIMD instructions 4920 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4921 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4922 4923 // ACLE 6.4.10 Hardware Integer Divide 4924 if (((HWDiv & HWDivThumb) && isThumb()) || 4925 ((HWDiv & HWDivARM) && !isThumb())) { 4926 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4927 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4928 } 4929 4930 // Note, this is always on in gcc, even though it doesn't make sense. 4931 Builder.defineMacro("__APCS_32__"); 4932 4933 if (FPUModeIsVFP((FPUMode) FPU)) { 4934 Builder.defineMacro("__VFP_FP__"); 4935 if (FPU & VFP2FPU) 4936 Builder.defineMacro("__ARM_VFPV2__"); 4937 if (FPU & VFP3FPU) 4938 Builder.defineMacro("__ARM_VFPV3__"); 4939 if (FPU & VFP4FPU) 4940 Builder.defineMacro("__ARM_VFPV4__"); 4941 } 4942 4943 // This only gets set when Neon instructions are actually available, unlike 4944 // the VFP define, hence the soft float and arch check. This is subtly 4945 // different from gcc, we follow the intent which was that it should be set 4946 // when Neon instructions are actually available. 4947 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4948 Builder.defineMacro("__ARM_NEON", "1"); 4949 Builder.defineMacro("__ARM_NEON__"); 4950 // current AArch32 NEON implementations do not support double-precision 4951 // floating-point even when it is present in VFP. 4952 Builder.defineMacro("__ARM_NEON_FP", 4953 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4954 } 4955 4956 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4957 Opts.ShortWChar ? "2" : "4"); 4958 4959 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4960 Opts.ShortEnums ? "1" : "4"); 4961 4962 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 4963 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4964 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4965 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4966 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4967 } 4968 4969 // ACLE 6.4.7 DSP instructions 4970 if (DSP) { 4971 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4972 } 4973 4974 // ACLE 6.4.8 Saturation instructions 4975 bool SAT = false; 4976 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4977 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4978 SAT = true; 4979 } 4980 4981 // ACLE 6.4.6 Q (saturation) flag 4982 if (DSP || SAT) 4983 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4984 4985 if (Opts.UnsafeFPMath) 4986 Builder.defineMacro("__ARM_FP_FAST", "1"); 4987 4988 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4989 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4990 } 4991 4992 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4993 return llvm::makeArrayRef(BuiltinInfo, 4994 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4995 } 4996 bool isCLZForZeroUndef() const override { return false; } 4997 BuiltinVaListKind getBuiltinVaListKind() const override { 4998 return IsAAPCS 4999 ? AAPCSABIBuiltinVaList 5000 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5001 : TargetInfo::VoidPtrBuiltinVaList); 5002 } 5003 ArrayRef<const char *> getGCCRegNames() const override; 5004 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5005 bool validateAsmConstraint(const char *&Name, 5006 TargetInfo::ConstraintInfo &Info) const override { 5007 switch (*Name) { 5008 default: break; 5009 case 'l': // r0-r7 5010 case 'h': // r8-r15 5011 case 't': // VFP Floating point register single precision 5012 case 'w': // VFP Floating point register double precision 5013 Info.setAllowsRegister(); 5014 return true; 5015 case 'I': 5016 case 'J': 5017 case 'K': 5018 case 'L': 5019 case 'M': 5020 // FIXME 5021 return true; 5022 case 'Q': // A memory address that is a single base register. 5023 Info.setAllowsMemory(); 5024 return true; 5025 case 'U': // a memory reference... 5026 switch (Name[1]) { 5027 case 'q': // ...ARMV4 ldrsb 5028 case 'v': // ...VFP load/store (reg+constant offset) 5029 case 'y': // ...iWMMXt load/store 5030 case 't': // address valid for load/store opaque types wider 5031 // than 128-bits 5032 case 'n': // valid address for Neon doubleword vector load/store 5033 case 'm': // valid address for Neon element and structure load/store 5034 case 's': // valid address for non-offset loads/stores of quad-word 5035 // values in four ARM registers 5036 Info.setAllowsMemory(); 5037 Name++; 5038 return true; 5039 } 5040 } 5041 return false; 5042 } 5043 std::string convertConstraint(const char *&Constraint) const override { 5044 std::string R; 5045 switch (*Constraint) { 5046 case 'U': // Two-character constraint; add "^" hint for later parsing. 5047 R = std::string("^") + std::string(Constraint, 2); 5048 Constraint++; 5049 break; 5050 case 'p': // 'p' should be translated to 'r' by default. 5051 R = std::string("r"); 5052 break; 5053 default: 5054 return std::string(1, *Constraint); 5055 } 5056 return R; 5057 } 5058 bool 5059 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5060 std::string &SuggestedModifier) const override { 5061 bool isOutput = (Constraint[0] == '='); 5062 bool isInOut = (Constraint[0] == '+'); 5063 5064 // Strip off constraint modifiers. 5065 while (Constraint[0] == '=' || 5066 Constraint[0] == '+' || 5067 Constraint[0] == '&') 5068 Constraint = Constraint.substr(1); 5069 5070 switch (Constraint[0]) { 5071 default: break; 5072 case 'r': { 5073 switch (Modifier) { 5074 default: 5075 return (isInOut || isOutput || Size <= 64); 5076 case 'q': 5077 // A register of size 32 cannot fit a vector type. 5078 return false; 5079 } 5080 } 5081 } 5082 5083 return true; 5084 } 5085 const char *getClobbers() const override { 5086 // FIXME: Is this really right? 5087 return ""; 5088 } 5089 5090 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5091 switch (CC) { 5092 case CC_AAPCS: 5093 case CC_AAPCS_VFP: 5094 case CC_Swift: 5095 return CCCR_OK; 5096 default: 5097 return CCCR_Warning; 5098 } 5099 } 5100 5101 int getEHDataRegisterNumber(unsigned RegNo) const override { 5102 if (RegNo == 0) return 0; 5103 if (RegNo == 1) return 1; 5104 return -1; 5105 } 5106 5107 bool hasSjLjLowering() const override { 5108 return true; 5109 } 5110 }; 5111 5112 bool ARMTargetInfo::setFPMath(StringRef Name) { 5113 if (Name == "neon") { 5114 FPMath = FP_Neon; 5115 return true; 5116 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5117 Name == "vfp4") { 5118 FPMath = FP_VFP; 5119 return true; 5120 } 5121 return false; 5122 } 5123 5124 const char * const ARMTargetInfo::GCCRegNames[] = { 5125 // Integer registers 5126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5127 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5128 5129 // Float registers 5130 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5131 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5132 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5133 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5134 5135 // Double registers 5136 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5137 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5138 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5139 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5140 5141 // Quad registers 5142 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5143 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5144 }; 5145 5146 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5147 return llvm::makeArrayRef(GCCRegNames); 5148 } 5149 5150 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5151 { { "a1" }, "r0" }, 5152 { { "a2" }, "r1" }, 5153 { { "a3" }, "r2" }, 5154 { { "a4" }, "r3" }, 5155 { { "v1" }, "r4" }, 5156 { { "v2" }, "r5" }, 5157 { { "v3" }, "r6" }, 5158 { { "v4" }, "r7" }, 5159 { { "v5" }, "r8" }, 5160 { { "v6", "rfp" }, "r9" }, 5161 { { "sl" }, "r10" }, 5162 { { "fp" }, "r11" }, 5163 { { "ip" }, "r12" }, 5164 { { "r13" }, "sp" }, 5165 { { "r14" }, "lr" }, 5166 { { "r15" }, "pc" }, 5167 // The S, D and Q registers overlap, but aren't really aliases; we 5168 // don't want to substitute one of these for a different-sized one. 5169 }; 5170 5171 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5172 return llvm::makeArrayRef(GCCRegAliases); 5173 } 5174 5175 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5176 #define BUILTIN(ID, TYPE, ATTRS) \ 5177 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5178 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5179 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5180 #include "clang/Basic/BuiltinsNEON.def" 5181 5182 #define BUILTIN(ID, TYPE, ATTRS) \ 5183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5184 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5185 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5186 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5187 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5188 #include "clang/Basic/BuiltinsARM.def" 5189 }; 5190 5191 class ARMleTargetInfo : public ARMTargetInfo { 5192 public: 5193 ARMleTargetInfo(const llvm::Triple &Triple) 5194 : ARMTargetInfo(Triple, false) { } 5195 void getTargetDefines(const LangOptions &Opts, 5196 MacroBuilder &Builder) const override { 5197 Builder.defineMacro("__ARMEL__"); 5198 ARMTargetInfo::getTargetDefines(Opts, Builder); 5199 } 5200 }; 5201 5202 class ARMbeTargetInfo : public ARMTargetInfo { 5203 public: 5204 ARMbeTargetInfo(const llvm::Triple &Triple) 5205 : ARMTargetInfo(Triple, true) { } 5206 void getTargetDefines(const LangOptions &Opts, 5207 MacroBuilder &Builder) const override { 5208 Builder.defineMacro("__ARMEB__"); 5209 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5210 ARMTargetInfo::getTargetDefines(Opts, Builder); 5211 } 5212 }; 5213 5214 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5215 const llvm::Triple Triple; 5216 public: 5217 WindowsARMTargetInfo(const llvm::Triple &Triple) 5218 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5219 WCharType = UnsignedShort; 5220 SizeType = UnsignedInt; 5221 } 5222 void getVisualStudioDefines(const LangOptions &Opts, 5223 MacroBuilder &Builder) const { 5224 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5225 5226 // FIXME: this is invalid for WindowsCE 5227 Builder.defineMacro("_M_ARM_NT", "1"); 5228 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5229 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5230 5231 assert((Triple.getArch() == llvm::Triple::arm || 5232 Triple.getArch() == llvm::Triple::thumb) && 5233 "invalid architecture for Windows ARM target info"); 5234 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5235 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5236 5237 // TODO map the complete set of values 5238 // 31: VFPv3 40: VFPv4 5239 Builder.defineMacro("_M_ARM_FP", "31"); 5240 } 5241 BuiltinVaListKind getBuiltinVaListKind() const override { 5242 return TargetInfo::CharPtrBuiltinVaList; 5243 } 5244 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5245 switch (CC) { 5246 case CC_X86StdCall: 5247 case CC_X86ThisCall: 5248 case CC_X86FastCall: 5249 case CC_X86VectorCall: 5250 return CCCR_Ignore; 5251 case CC_C: 5252 return CCCR_OK; 5253 default: 5254 return CCCR_Warning; 5255 } 5256 } 5257 }; 5258 5259 // Windows ARM + Itanium C++ ABI Target 5260 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5261 public: 5262 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5263 : WindowsARMTargetInfo(Triple) { 5264 TheCXXABI.set(TargetCXXABI::GenericARM); 5265 } 5266 5267 void getTargetDefines(const LangOptions &Opts, 5268 MacroBuilder &Builder) const override { 5269 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5270 5271 if (Opts.MSVCCompat) 5272 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5273 } 5274 }; 5275 5276 // Windows ARM, MS (C++) ABI 5277 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5278 public: 5279 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5280 : WindowsARMTargetInfo(Triple) { 5281 TheCXXABI.set(TargetCXXABI::Microsoft); 5282 } 5283 5284 void getTargetDefines(const LangOptions &Opts, 5285 MacroBuilder &Builder) const override { 5286 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5287 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5288 } 5289 }; 5290 5291 // ARM MinGW target 5292 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5293 public: 5294 MinGWARMTargetInfo(const llvm::Triple &Triple) 5295 : WindowsARMTargetInfo(Triple) { 5296 TheCXXABI.set(TargetCXXABI::GenericARM); 5297 } 5298 5299 void getTargetDefines(const LangOptions &Opts, 5300 MacroBuilder &Builder) const override { 5301 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5302 DefineStd(Builder, "WIN32", Opts); 5303 DefineStd(Builder, "WINNT", Opts); 5304 Builder.defineMacro("_ARM_"); 5305 addMinGWDefines(Opts, Builder); 5306 } 5307 }; 5308 5309 // ARM Cygwin target 5310 class CygwinARMTargetInfo : public ARMleTargetInfo { 5311 public: 5312 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5313 TLSSupported = false; 5314 WCharType = UnsignedShort; 5315 DoubleAlign = LongLongAlign = 64; 5316 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5317 } 5318 void getTargetDefines(const LangOptions &Opts, 5319 MacroBuilder &Builder) const override { 5320 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5321 Builder.defineMacro("_ARM_"); 5322 Builder.defineMacro("__CYGWIN__"); 5323 Builder.defineMacro("__CYGWIN32__"); 5324 DefineStd(Builder, "unix", Opts); 5325 if (Opts.CPlusPlus) 5326 Builder.defineMacro("_GNU_SOURCE"); 5327 } 5328 }; 5329 5330 class DarwinARMTargetInfo : 5331 public DarwinTargetInfo<ARMleTargetInfo> { 5332 protected: 5333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5334 MacroBuilder &Builder) const override { 5335 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5336 } 5337 5338 public: 5339 DarwinARMTargetInfo(const llvm::Triple &Triple) 5340 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5341 HasAlignMac68kSupport = true; 5342 // iOS always has 64-bit atomic instructions. 5343 // FIXME: This should be based off of the target features in 5344 // ARMleTargetInfo. 5345 MaxAtomicInlineWidth = 64; 5346 5347 if (Triple.isWatchABI()) { 5348 // Darwin on iOS uses a variant of the ARM C++ ABI. 5349 TheCXXABI.set(TargetCXXABI::WatchOS); 5350 5351 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5352 // size_t is long, it's a bit weird for it to be int. 5353 PtrDiffType = SignedLong; 5354 5355 // BOOL should be a real boolean on the new ABI 5356 UseSignedCharForObjCBool = false; 5357 } else 5358 TheCXXABI.set(TargetCXXABI::iOS); 5359 } 5360 }; 5361 5362 class AArch64TargetInfo : public TargetInfo { 5363 virtual void setDataLayout() = 0; 5364 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5365 static const char *const GCCRegNames[]; 5366 5367 enum FPUModeEnum { 5368 FPUMode, 5369 NeonMode 5370 }; 5371 5372 unsigned FPU; 5373 unsigned CRC; 5374 unsigned Crypto; 5375 unsigned Unaligned; 5376 unsigned V8_1A; 5377 5378 static const Builtin::Info BuiltinInfo[]; 5379 5380 std::string ABI; 5381 5382 public: 5383 AArch64TargetInfo(const llvm::Triple &Triple) 5384 : TargetInfo(Triple), ABI("aapcs") { 5385 5386 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5387 WCharType = SignedInt; 5388 5389 // NetBSD apparently prefers consistency across ARM targets to consistency 5390 // across 64-bit targets. 5391 Int64Type = SignedLongLong; 5392 IntMaxType = SignedLongLong; 5393 } else { 5394 WCharType = UnsignedInt; 5395 Int64Type = SignedLong; 5396 IntMaxType = SignedLong; 5397 } 5398 5399 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5400 MaxVectorAlign = 128; 5401 MaxAtomicInlineWidth = 128; 5402 MaxAtomicPromoteWidth = 128; 5403 5404 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5405 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5406 5407 // {} in inline assembly are neon specifiers, not assembly variant 5408 // specifiers. 5409 NoAsmVariants = true; 5410 5411 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5412 // contributes to the alignment of the containing aggregate in the same way 5413 // a plain (non bit-field) member of that type would, without exception for 5414 // zero-sized or anonymous bit-fields." 5415 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5416 UseZeroLengthBitfieldAlignment = true; 5417 5418 // AArch64 targets default to using the ARM C++ ABI. 5419 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5420 } 5421 5422 StringRef getABI() const override { return ABI; } 5423 bool setABI(const std::string &Name) override { 5424 if (Name != "aapcs" && Name != "darwinpcs") 5425 return false; 5426 5427 ABI = Name; 5428 return true; 5429 } 5430 5431 bool setCPU(const std::string &Name) override { 5432 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5433 .Case("generic", true) 5434 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5435 "cortex-a35", "exynos-m1", true) 5436 .Case("cyclone", true) 5437 .Case("kryo", true) 5438 .Default(false); 5439 return CPUKnown; 5440 } 5441 5442 void getTargetDefines(const LangOptions &Opts, 5443 MacroBuilder &Builder) const override { 5444 // Target identification. 5445 Builder.defineMacro("__aarch64__"); 5446 5447 // Target properties. 5448 Builder.defineMacro("_LP64"); 5449 Builder.defineMacro("__LP64__"); 5450 5451 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5452 Builder.defineMacro("__ARM_ACLE", "200"); 5453 Builder.defineMacro("__ARM_ARCH", "8"); 5454 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5455 5456 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5457 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5458 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5459 5460 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5461 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5462 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5463 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5464 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5465 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5466 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5467 5468 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5469 5470 // 0xe implies support for half, single and double precision operations. 5471 Builder.defineMacro("__ARM_FP", "0xE"); 5472 5473 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5474 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5475 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5476 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5477 5478 if (Opts.UnsafeFPMath) 5479 Builder.defineMacro("__ARM_FP_FAST", "1"); 5480 5481 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5482 5483 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5484 Opts.ShortEnums ? "1" : "4"); 5485 5486 if (FPU == NeonMode) { 5487 Builder.defineMacro("__ARM_NEON", "1"); 5488 // 64-bit NEON supports half, single and double precision operations. 5489 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5490 } 5491 5492 if (CRC) 5493 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5494 5495 if (Crypto) 5496 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5497 5498 if (Unaligned) 5499 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5500 5501 if (V8_1A) 5502 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5503 5504 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5505 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5506 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5507 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5508 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5509 } 5510 5511 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5512 return llvm::makeArrayRef(BuiltinInfo, 5513 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5514 } 5515 5516 bool hasFeature(StringRef Feature) const override { 5517 return Feature == "aarch64" || 5518 Feature == "arm64" || 5519 Feature == "arm" || 5520 (Feature == "neon" && FPU == NeonMode); 5521 } 5522 5523 bool handleTargetFeatures(std::vector<std::string> &Features, 5524 DiagnosticsEngine &Diags) override { 5525 FPU = FPUMode; 5526 CRC = 0; 5527 Crypto = 0; 5528 Unaligned = 1; 5529 V8_1A = 0; 5530 5531 for (const auto &Feature : Features) { 5532 if (Feature == "+neon") 5533 FPU = NeonMode; 5534 if (Feature == "+crc") 5535 CRC = 1; 5536 if (Feature == "+crypto") 5537 Crypto = 1; 5538 if (Feature == "+strict-align") 5539 Unaligned = 0; 5540 if (Feature == "+v8.1a") 5541 V8_1A = 1; 5542 } 5543 5544 setDataLayout(); 5545 5546 return true; 5547 } 5548 5549 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5550 switch (CC) { 5551 case CC_C: 5552 case CC_Swift: 5553 case CC_PreserveMost: 5554 case CC_PreserveAll: 5555 return CCCR_OK; 5556 default: 5557 return CCCR_Warning; 5558 } 5559 } 5560 5561 bool isCLZForZeroUndef() const override { return false; } 5562 5563 BuiltinVaListKind getBuiltinVaListKind() const override { 5564 return TargetInfo::AArch64ABIBuiltinVaList; 5565 } 5566 5567 ArrayRef<const char *> getGCCRegNames() const override; 5568 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5569 5570 bool validateAsmConstraint(const char *&Name, 5571 TargetInfo::ConstraintInfo &Info) const override { 5572 switch (*Name) { 5573 default: 5574 return false; 5575 case 'w': // Floating point and SIMD registers (V0-V31) 5576 Info.setAllowsRegister(); 5577 return true; 5578 case 'I': // Constant that can be used with an ADD instruction 5579 case 'J': // Constant that can be used with a SUB instruction 5580 case 'K': // Constant that can be used with a 32-bit logical instruction 5581 case 'L': // Constant that can be used with a 64-bit logical instruction 5582 case 'M': // Constant that can be used as a 32-bit MOV immediate 5583 case 'N': // Constant that can be used as a 64-bit MOV immediate 5584 case 'Y': // Floating point constant zero 5585 case 'Z': // Integer constant zero 5586 return true; 5587 case 'Q': // A memory reference with base register and no offset 5588 Info.setAllowsMemory(); 5589 return true; 5590 case 'S': // A symbolic address 5591 Info.setAllowsRegister(); 5592 return true; 5593 case 'U': 5594 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5595 // Utf: A memory address suitable for ldp/stp in TF mode. 5596 // Usa: An absolute symbolic address. 5597 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5598 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5599 case 'z': // Zero register, wzr or xzr 5600 Info.setAllowsRegister(); 5601 return true; 5602 case 'x': // Floating point and SIMD registers (V0-V15) 5603 Info.setAllowsRegister(); 5604 return true; 5605 } 5606 return false; 5607 } 5608 5609 bool 5610 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5611 std::string &SuggestedModifier) const override { 5612 // Strip off constraint modifiers. 5613 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5614 Constraint = Constraint.substr(1); 5615 5616 switch (Constraint[0]) { 5617 default: 5618 return true; 5619 case 'z': 5620 case 'r': { 5621 switch (Modifier) { 5622 case 'x': 5623 case 'w': 5624 // For now assume that the person knows what they're 5625 // doing with the modifier. 5626 return true; 5627 default: 5628 // By default an 'r' constraint will be in the 'x' 5629 // registers. 5630 if (Size == 64) 5631 return true; 5632 5633 SuggestedModifier = "w"; 5634 return false; 5635 } 5636 } 5637 } 5638 } 5639 5640 const char *getClobbers() const override { return ""; } 5641 5642 int getEHDataRegisterNumber(unsigned RegNo) const override { 5643 if (RegNo == 0) 5644 return 0; 5645 if (RegNo == 1) 5646 return 1; 5647 return -1; 5648 } 5649 }; 5650 5651 const char *const AArch64TargetInfo::GCCRegNames[] = { 5652 // 32-bit Integer registers 5653 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5654 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5655 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5656 5657 // 64-bit Integer registers 5658 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5659 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5660 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5661 5662 // 32-bit floating point regsisters 5663 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5664 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5665 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5666 5667 // 64-bit floating point regsisters 5668 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5669 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5670 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5671 5672 // Vector registers 5673 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5674 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5675 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5676 }; 5677 5678 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5679 return llvm::makeArrayRef(GCCRegNames); 5680 } 5681 5682 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5683 { { "w31" }, "wsp" }, 5684 { { "x29" }, "fp" }, 5685 { { "x30" }, "lr" }, 5686 { { "x31" }, "sp" }, 5687 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5688 // don't want to substitute one of these for a different-sized one. 5689 }; 5690 5691 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5692 return llvm::makeArrayRef(GCCRegAliases); 5693 } 5694 5695 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5696 #define BUILTIN(ID, TYPE, ATTRS) \ 5697 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5698 #include "clang/Basic/BuiltinsNEON.def" 5699 5700 #define BUILTIN(ID, TYPE, ATTRS) \ 5701 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5702 #include "clang/Basic/BuiltinsAArch64.def" 5703 }; 5704 5705 class AArch64leTargetInfo : public AArch64TargetInfo { 5706 void setDataLayout() override { 5707 if (getTriple().isOSBinFormatMachO()) 5708 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5709 else 5710 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5711 } 5712 5713 public: 5714 AArch64leTargetInfo(const llvm::Triple &Triple) 5715 : AArch64TargetInfo(Triple) { 5716 BigEndian = false; 5717 } 5718 void getTargetDefines(const LangOptions &Opts, 5719 MacroBuilder &Builder) const override { 5720 Builder.defineMacro("__AARCH64EL__"); 5721 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5722 } 5723 }; 5724 5725 class AArch64beTargetInfo : public AArch64TargetInfo { 5726 void setDataLayout() override { 5727 assert(!getTriple().isOSBinFormatMachO()); 5728 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5729 } 5730 5731 public: 5732 AArch64beTargetInfo(const llvm::Triple &Triple) 5733 : AArch64TargetInfo(Triple) { } 5734 void getTargetDefines(const LangOptions &Opts, 5735 MacroBuilder &Builder) const override { 5736 Builder.defineMacro("__AARCH64EB__"); 5737 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5738 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5739 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5740 } 5741 }; 5742 5743 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5744 protected: 5745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5746 MacroBuilder &Builder) const override { 5747 Builder.defineMacro("__AARCH64_SIMD__"); 5748 Builder.defineMacro("__ARM64_ARCH_8__"); 5749 Builder.defineMacro("__ARM_NEON__"); 5750 Builder.defineMacro("__LITTLE_ENDIAN__"); 5751 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5752 Builder.defineMacro("__arm64", "1"); 5753 Builder.defineMacro("__arm64__", "1"); 5754 5755 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5756 } 5757 5758 public: 5759 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5760 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5761 Int64Type = SignedLongLong; 5762 WCharType = SignedInt; 5763 UseSignedCharForObjCBool = false; 5764 5765 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5766 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5767 5768 TheCXXABI.set(TargetCXXABI::iOS64); 5769 } 5770 5771 BuiltinVaListKind getBuiltinVaListKind() const override { 5772 return TargetInfo::CharPtrBuiltinVaList; 5773 } 5774 }; 5775 5776 // Hexagon abstract base class 5777 class HexagonTargetInfo : public TargetInfo { 5778 static const Builtin::Info BuiltinInfo[]; 5779 static const char * const GCCRegNames[]; 5780 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5781 std::string CPU; 5782 bool HasHVX, HasHVXDouble; 5783 5784 public: 5785 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5786 BigEndian = false; 5787 // Specify the vector alignment explicitly. For v512x1, the calculated 5788 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5789 // the required minimum of 64 bytes. 5790 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 5791 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5792 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 5793 SizeType = UnsignedInt; 5794 PtrDiffType = SignedInt; 5795 IntPtrType = SignedInt; 5796 5797 // {} in inline assembly are packet specifiers, not assembly variant 5798 // specifiers. 5799 NoAsmVariants = true; 5800 5801 LargeArrayMinWidth = 64; 5802 LargeArrayAlign = 64; 5803 UseBitFieldTypeAlignment = true; 5804 ZeroLengthBitfieldBoundary = 32; 5805 HasHVX = HasHVXDouble = false; 5806 } 5807 5808 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5809 return llvm::makeArrayRef(BuiltinInfo, 5810 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5811 } 5812 5813 bool validateAsmConstraint(const char *&Name, 5814 TargetInfo::ConstraintInfo &Info) const override { 5815 return true; 5816 } 5817 5818 void getTargetDefines(const LangOptions &Opts, 5819 MacroBuilder &Builder) const override; 5820 5821 bool isCLZForZeroUndef() const override { return false; } 5822 5823 bool hasFeature(StringRef Feature) const override { 5824 return llvm::StringSwitch<bool>(Feature) 5825 .Case("hexagon", true) 5826 .Case("hvx", HasHVX) 5827 .Case("hvx-double", HasHVXDouble) 5828 .Default(false); 5829 } 5830 5831 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5832 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5833 const override; 5834 5835 bool handleTargetFeatures(std::vector<std::string> &Features, 5836 DiagnosticsEngine &Diags) override; 5837 5838 BuiltinVaListKind getBuiltinVaListKind() const override { 5839 return TargetInfo::CharPtrBuiltinVaList; 5840 } 5841 ArrayRef<const char *> getGCCRegNames() const override; 5842 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5843 const char *getClobbers() const override { 5844 return ""; 5845 } 5846 5847 static const char *getHexagonCPUSuffix(StringRef Name) { 5848 return llvm::StringSwitch<const char*>(Name) 5849 .Case("hexagonv4", "4") 5850 .Case("hexagonv5", "5") 5851 .Case("hexagonv55", "55") 5852 .Case("hexagonv60", "60") 5853 .Default(nullptr); 5854 } 5855 5856 bool setCPU(const std::string &Name) override { 5857 if (!getHexagonCPUSuffix(Name)) 5858 return false; 5859 CPU = Name; 5860 return true; 5861 } 5862 5863 int getEHDataRegisterNumber(unsigned RegNo) const override { 5864 return RegNo < 2 ? RegNo : -1; 5865 } 5866 }; 5867 5868 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5869 MacroBuilder &Builder) const { 5870 Builder.defineMacro("__qdsp6__", "1"); 5871 Builder.defineMacro("__hexagon__", "1"); 5872 5873 if (CPU == "hexagonv4") { 5874 Builder.defineMacro("__HEXAGON_V4__"); 5875 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5876 if (Opts.HexagonQdsp6Compat) { 5877 Builder.defineMacro("__QDSP6_V4__"); 5878 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5879 } 5880 } else if (CPU == "hexagonv5") { 5881 Builder.defineMacro("__HEXAGON_V5__"); 5882 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5883 if(Opts.HexagonQdsp6Compat) { 5884 Builder.defineMacro("__QDSP6_V5__"); 5885 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5886 } 5887 } else if (CPU == "hexagonv60") { 5888 Builder.defineMacro("__HEXAGON_V60__"); 5889 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5890 Builder.defineMacro("__QDSP6_V60__"); 5891 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5892 } 5893 } 5894 5895 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5896 DiagnosticsEngine &Diags) { 5897 for (auto &F : Features) { 5898 if (F == "+hvx") 5899 HasHVX = true; 5900 else if (F == "-hvx") 5901 HasHVX = HasHVXDouble = false; 5902 else if (F == "+hvx-double") 5903 HasHVX = HasHVXDouble = true; 5904 else if (F == "-hvx-double") 5905 HasHVXDouble = false; 5906 } 5907 return true; 5908 } 5909 5910 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5911 DiagnosticsEngine &Diags, StringRef CPU, 5912 const std::vector<std::string> &FeaturesVec) const { 5913 // Default for v60: -hvx, -hvx-double. 5914 Features["hvx"] = false; 5915 Features["hvx-double"] = false; 5916 5917 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5918 } 5919 5920 5921 const char *const HexagonTargetInfo::GCCRegNames[] = { 5922 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5923 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5924 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5925 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5926 "p0", "p1", "p2", "p3", 5927 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5928 }; 5929 5930 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5931 return llvm::makeArrayRef(GCCRegNames); 5932 } 5933 5934 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5935 { { "sp" }, "r29" }, 5936 { { "fp" }, "r30" }, 5937 { { "lr" }, "r31" }, 5938 }; 5939 5940 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5941 return llvm::makeArrayRef(GCCRegAliases); 5942 } 5943 5944 5945 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5946 #define BUILTIN(ID, TYPE, ATTRS) \ 5947 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5948 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5949 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5950 #include "clang/Basic/BuiltinsHexagon.def" 5951 }; 5952 5953 class LanaiTargetInfo : public TargetInfo { 5954 // Class for Lanai (32-bit). 5955 // The CPU profiles supported by the Lanai backend 5956 enum CPUKind { 5957 CK_NONE, 5958 CK_V11, 5959 } CPU; 5960 5961 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5962 static const char *const GCCRegNames[]; 5963 5964 public: 5965 LanaiTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5966 // Description string has to be kept in sync with backend. 5967 resetDataLayout("E" // Big endian 5968 "-m:e" // ELF name manging 5969 "-p:32:32" // 32 bit pointers, 32 bit aligned 5970 "-i64:64" // 64 bit integers, 64 bit aligned 5971 "-a:0:32" // 32 bit alignment of objects of aggregate type 5972 "-n32" // 32 bit native integer width 5973 "-S64" // 64 bit natural stack alignment 5974 ); 5975 5976 // Setting RegParmMax equal to what mregparm was set to in the old 5977 // toolchain 5978 RegParmMax = 4; 5979 5980 // Set the default CPU to V11 5981 CPU = CK_V11; 5982 5983 // Temporary approach to make everything at least word-aligned and allow for 5984 // safely casting between pointers with different alignment requirements. 5985 // TODO: Remove this when there are no more cast align warnings on the 5986 // firmware. 5987 MinGlobalAlign = 32; 5988 } 5989 5990 void getTargetDefines(const LangOptions &Opts, 5991 MacroBuilder &Builder) const override { 5992 // Define __lanai__ when building for target lanai. 5993 Builder.defineMacro("__lanai__"); 5994 5995 // Set define for the CPU specified. 5996 switch (CPU) { 5997 case CK_V11: 5998 Builder.defineMacro("__LANAI_V11__"); 5999 break; 6000 case CK_NONE: 6001 llvm_unreachable("Unhandled target CPU"); 6002 } 6003 } 6004 6005 bool setCPU(const std::string &Name) override { 6006 CPU = llvm::StringSwitch<CPUKind>(Name) 6007 .Case("v11", CK_V11) 6008 .Default(CK_NONE); 6009 6010 return CPU != CK_NONE; 6011 } 6012 6013 bool hasFeature(StringRef Feature) const override { 6014 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6015 } 6016 6017 ArrayRef<const char *> getGCCRegNames() const override; 6018 6019 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6020 6021 BuiltinVaListKind getBuiltinVaListKind() const override { 6022 return TargetInfo::VoidPtrBuiltinVaList; 6023 } 6024 6025 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6026 6027 bool validateAsmConstraint(const char *&Name, 6028 TargetInfo::ConstraintInfo &info) const override { 6029 return false; 6030 } 6031 6032 const char *getClobbers() const override { return ""; } 6033 }; 6034 6035 const char *const LanaiTargetInfo::GCCRegNames[] = { 6036 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6037 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6038 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6039 6040 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6041 return llvm::makeArrayRef(GCCRegNames); 6042 } 6043 6044 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6045 {{"pc"}, "r2"}, 6046 {{"sp"}, "r4"}, 6047 {{"fp"}, "r5"}, 6048 {{"rv"}, "r8"}, 6049 {{"rr1"}, "r10"}, 6050 {{"rr2"}, "r11"}, 6051 {{"rca"}, "r15"}, 6052 }; 6053 6054 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6055 return llvm::makeArrayRef(GCCRegAliases); 6056 } 6057 6058 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6059 class SparcTargetInfo : public TargetInfo { 6060 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6061 static const char * const GCCRegNames[]; 6062 bool SoftFloat; 6063 public: 6064 SparcTargetInfo(const llvm::Triple &Triple) 6065 : TargetInfo(Triple), SoftFloat(false) {} 6066 6067 int getEHDataRegisterNumber(unsigned RegNo) const override { 6068 if (RegNo == 0) return 24; 6069 if (RegNo == 1) return 25; 6070 return -1; 6071 } 6072 6073 bool handleTargetFeatures(std::vector<std::string> &Features, 6074 DiagnosticsEngine &Diags) override { 6075 // The backend doesn't actually handle soft float yet, but in case someone 6076 // is using the support for the front end continue to support it. 6077 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6078 if (Feature != Features.end()) { 6079 SoftFloat = true; 6080 Features.erase(Feature); 6081 } 6082 return true; 6083 } 6084 void getTargetDefines(const LangOptions &Opts, 6085 MacroBuilder &Builder) const override { 6086 DefineStd(Builder, "sparc", Opts); 6087 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6088 6089 if (SoftFloat) 6090 Builder.defineMacro("SOFT_FLOAT", "1"); 6091 } 6092 6093 bool hasFeature(StringRef Feature) const override { 6094 return llvm::StringSwitch<bool>(Feature) 6095 .Case("softfloat", SoftFloat) 6096 .Case("sparc", true) 6097 .Default(false); 6098 } 6099 6100 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6101 // FIXME: Implement! 6102 return None; 6103 } 6104 BuiltinVaListKind getBuiltinVaListKind() const override { 6105 return TargetInfo::VoidPtrBuiltinVaList; 6106 } 6107 ArrayRef<const char *> getGCCRegNames() const override; 6108 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6109 bool validateAsmConstraint(const char *&Name, 6110 TargetInfo::ConstraintInfo &info) const override { 6111 // FIXME: Implement! 6112 switch (*Name) { 6113 case 'I': // Signed 13-bit constant 6114 case 'J': // Zero 6115 case 'K': // 32-bit constant with the low 12 bits clear 6116 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6117 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6118 case 'N': // Same as 'K' but zext (required for SIMode) 6119 case 'O': // The constant 4096 6120 return true; 6121 } 6122 return false; 6123 } 6124 const char *getClobbers() const override { 6125 // FIXME: Implement! 6126 return ""; 6127 } 6128 6129 // No Sparc V7 for now, the backend doesn't support it anyway. 6130 enum CPUKind { 6131 CK_GENERIC, 6132 CK_V8, 6133 CK_SUPERSPARC, 6134 CK_SPARCLITE, 6135 CK_F934, 6136 CK_HYPERSPARC, 6137 CK_SPARCLITE86X, 6138 CK_SPARCLET, 6139 CK_TSC701, 6140 CK_V9, 6141 CK_ULTRASPARC, 6142 CK_ULTRASPARC3, 6143 CK_NIAGARA, 6144 CK_NIAGARA2, 6145 CK_NIAGARA3, 6146 CK_NIAGARA4, 6147 CK_MYRIAD2_1, 6148 CK_MYRIAD2_2 6149 } CPU = CK_GENERIC; 6150 6151 enum CPUGeneration { 6152 CG_V8, 6153 CG_V9, 6154 }; 6155 6156 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6157 switch (Kind) { 6158 case CK_GENERIC: 6159 case CK_V8: 6160 case CK_SUPERSPARC: 6161 case CK_SPARCLITE: 6162 case CK_F934: 6163 case CK_HYPERSPARC: 6164 case CK_SPARCLITE86X: 6165 case CK_SPARCLET: 6166 case CK_TSC701: 6167 case CK_MYRIAD2_1: 6168 case CK_MYRIAD2_2: 6169 return CG_V8; 6170 case CK_V9: 6171 case CK_ULTRASPARC: 6172 case CK_ULTRASPARC3: 6173 case CK_NIAGARA: 6174 case CK_NIAGARA2: 6175 case CK_NIAGARA3: 6176 case CK_NIAGARA4: 6177 return CG_V9; 6178 } 6179 llvm_unreachable("Unexpected CPU kind"); 6180 } 6181 6182 CPUKind getCPUKind(StringRef Name) const { 6183 return llvm::StringSwitch<CPUKind>(Name) 6184 .Case("v8", CK_V8) 6185 .Case("supersparc", CK_SUPERSPARC) 6186 .Case("sparclite", CK_SPARCLITE) 6187 .Case("f934", CK_F934) 6188 .Case("hypersparc", CK_HYPERSPARC) 6189 .Case("sparclite86x", CK_SPARCLITE86X) 6190 .Case("sparclet", CK_SPARCLET) 6191 .Case("tsc701", CK_TSC701) 6192 .Case("v9", CK_V9) 6193 .Case("ultrasparc", CK_ULTRASPARC) 6194 .Case("ultrasparc3", CK_ULTRASPARC3) 6195 .Case("niagara", CK_NIAGARA) 6196 .Case("niagara2", CK_NIAGARA2) 6197 .Case("niagara3", CK_NIAGARA3) 6198 .Case("niagara4", CK_NIAGARA4) 6199 .Case("myriad2", CK_MYRIAD2_1) 6200 .Case("myriad2.1", CK_MYRIAD2_1) 6201 .Case("myriad2.2", CK_MYRIAD2_2) 6202 .Default(CK_GENERIC); 6203 } 6204 6205 bool setCPU(const std::string &Name) override { 6206 CPU = getCPUKind(Name); 6207 return CPU != CK_GENERIC; 6208 } 6209 }; 6210 6211 const char * const SparcTargetInfo::GCCRegNames[] = { 6212 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6213 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6214 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6215 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6216 }; 6217 6218 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6219 return llvm::makeArrayRef(GCCRegNames); 6220 } 6221 6222 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6223 { { "g0" }, "r0" }, 6224 { { "g1" }, "r1" }, 6225 { { "g2" }, "r2" }, 6226 { { "g3" }, "r3" }, 6227 { { "g4" }, "r4" }, 6228 { { "g5" }, "r5" }, 6229 { { "g6" }, "r6" }, 6230 { { "g7" }, "r7" }, 6231 { { "o0" }, "r8" }, 6232 { { "o1" }, "r9" }, 6233 { { "o2" }, "r10" }, 6234 { { "o3" }, "r11" }, 6235 { { "o4" }, "r12" }, 6236 { { "o5" }, "r13" }, 6237 { { "o6", "sp" }, "r14" }, 6238 { { "o7" }, "r15" }, 6239 { { "l0" }, "r16" }, 6240 { { "l1" }, "r17" }, 6241 { { "l2" }, "r18" }, 6242 { { "l3" }, "r19" }, 6243 { { "l4" }, "r20" }, 6244 { { "l5" }, "r21" }, 6245 { { "l6" }, "r22" }, 6246 { { "l7" }, "r23" }, 6247 { { "i0" }, "r24" }, 6248 { { "i1" }, "r25" }, 6249 { { "i2" }, "r26" }, 6250 { { "i3" }, "r27" }, 6251 { { "i4" }, "r28" }, 6252 { { "i5" }, "r29" }, 6253 { { "i6", "fp" }, "r30" }, 6254 { { "i7" }, "r31" }, 6255 }; 6256 6257 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6258 return llvm::makeArrayRef(GCCRegAliases); 6259 } 6260 6261 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6262 class SparcV8TargetInfo : public SparcTargetInfo { 6263 public: 6264 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6265 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6266 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6267 switch (getTriple().getOS()) { 6268 default: 6269 SizeType = UnsignedInt; 6270 IntPtrType = SignedInt; 6271 PtrDiffType = SignedInt; 6272 break; 6273 case llvm::Triple::NetBSD: 6274 case llvm::Triple::OpenBSD: 6275 SizeType = UnsignedLong; 6276 IntPtrType = SignedLong; 6277 PtrDiffType = SignedLong; 6278 break; 6279 } 6280 } 6281 6282 void getTargetDefines(const LangOptions &Opts, 6283 MacroBuilder &Builder) const override { 6284 SparcTargetInfo::getTargetDefines(Opts, Builder); 6285 switch (getCPUGeneration(CPU)) { 6286 case CG_V8: 6287 Builder.defineMacro("__sparcv8"); 6288 if (getTriple().getOS() != llvm::Triple::Solaris) 6289 Builder.defineMacro("__sparcv8__"); 6290 break; 6291 case CG_V9: 6292 Builder.defineMacro("__sparcv9"); 6293 if (getTriple().getOS() != llvm::Triple::Solaris) { 6294 Builder.defineMacro("__sparcv9__"); 6295 Builder.defineMacro("__sparc_v9__"); 6296 } 6297 break; 6298 } 6299 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6300 switch (CPU) { 6301 case CK_MYRIAD2_1: 6302 Builder.defineMacro("__myriad2", "1"); 6303 Builder.defineMacro("__myriad2__", "1"); 6304 break; 6305 case CK_MYRIAD2_2: 6306 Builder.defineMacro("__myriad2", "2"); 6307 Builder.defineMacro("__myriad2__", "2"); 6308 break; 6309 default: 6310 break; 6311 } 6312 } 6313 } 6314 }; 6315 6316 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6317 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6318 public: 6319 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6320 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6321 BigEndian = false; 6322 } 6323 }; 6324 6325 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6326 class SparcV9TargetInfo : public SparcTargetInfo { 6327 public: 6328 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6329 // FIXME: Support Sparc quad-precision long double? 6330 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6331 // This is an LP64 platform. 6332 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6333 6334 // OpenBSD uses long long for int64_t and intmax_t. 6335 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6336 IntMaxType = SignedLongLong; 6337 else 6338 IntMaxType = SignedLong; 6339 Int64Type = IntMaxType; 6340 6341 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6342 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6343 LongDoubleWidth = 128; 6344 LongDoubleAlign = 128; 6345 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6346 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6347 } 6348 6349 void getTargetDefines(const LangOptions &Opts, 6350 MacroBuilder &Builder) const override { 6351 SparcTargetInfo::getTargetDefines(Opts, Builder); 6352 Builder.defineMacro("__sparcv9"); 6353 Builder.defineMacro("__arch64__"); 6354 // Solaris doesn't need these variants, but the BSDs do. 6355 if (getTriple().getOS() != llvm::Triple::Solaris) { 6356 Builder.defineMacro("__sparc64__"); 6357 Builder.defineMacro("__sparc_v9__"); 6358 Builder.defineMacro("__sparcv9__"); 6359 } 6360 } 6361 6362 bool setCPU(const std::string &Name) override { 6363 if (!SparcTargetInfo::setCPU(Name)) 6364 return false; 6365 return getCPUGeneration(CPU) == CG_V9; 6366 } 6367 }; 6368 6369 class SystemZTargetInfo : public TargetInfo { 6370 static const Builtin::Info BuiltinInfo[]; 6371 static const char *const GCCRegNames[]; 6372 std::string CPU; 6373 bool HasTransactionalExecution; 6374 bool HasVector; 6375 6376 public: 6377 SystemZTargetInfo(const llvm::Triple &Triple) 6378 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6379 HasVector(false) { 6380 IntMaxType = SignedLong; 6381 Int64Type = SignedLong; 6382 TLSSupported = true; 6383 IntWidth = IntAlign = 32; 6384 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6385 PointerWidth = PointerAlign = 64; 6386 LongDoubleWidth = 128; 6387 LongDoubleAlign = 64; 6388 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6389 DefaultAlignForAttributeAligned = 64; 6390 MinGlobalAlign = 16; 6391 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6392 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6393 } 6394 void getTargetDefines(const LangOptions &Opts, 6395 MacroBuilder &Builder) const override { 6396 Builder.defineMacro("__s390__"); 6397 Builder.defineMacro("__s390x__"); 6398 Builder.defineMacro("__zarch__"); 6399 Builder.defineMacro("__LONG_DOUBLE_128__"); 6400 6401 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6402 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6403 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6404 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6405 6406 if (HasTransactionalExecution) 6407 Builder.defineMacro("__HTM__"); 6408 if (Opts.ZVector) 6409 Builder.defineMacro("__VEC__", "10301"); 6410 } 6411 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6412 return llvm::makeArrayRef(BuiltinInfo, 6413 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6414 } 6415 6416 ArrayRef<const char *> getGCCRegNames() const override; 6417 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6418 // No aliases. 6419 return None; 6420 } 6421 bool validateAsmConstraint(const char *&Name, 6422 TargetInfo::ConstraintInfo &info) const override; 6423 const char *getClobbers() const override { 6424 // FIXME: Is this really right? 6425 return ""; 6426 } 6427 BuiltinVaListKind getBuiltinVaListKind() const override { 6428 return TargetInfo::SystemZBuiltinVaList; 6429 } 6430 bool setCPU(const std::string &Name) override { 6431 CPU = Name; 6432 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6433 .Case("z10", true) 6434 .Case("z196", true) 6435 .Case("zEC12", true) 6436 .Case("z13", true) 6437 .Default(false); 6438 6439 return CPUKnown; 6440 } 6441 bool 6442 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6443 StringRef CPU, 6444 const std::vector<std::string> &FeaturesVec) const override { 6445 if (CPU == "zEC12") 6446 Features["transactional-execution"] = true; 6447 if (CPU == "z13") { 6448 Features["transactional-execution"] = true; 6449 Features["vector"] = true; 6450 } 6451 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6452 } 6453 6454 bool handleTargetFeatures(std::vector<std::string> &Features, 6455 DiagnosticsEngine &Diags) override { 6456 HasTransactionalExecution = false; 6457 for (const auto &Feature : Features) { 6458 if (Feature == "+transactional-execution") 6459 HasTransactionalExecution = true; 6460 else if (Feature == "+vector") 6461 HasVector = true; 6462 } 6463 // If we use the vector ABI, vector types are 64-bit aligned. 6464 if (HasVector) { 6465 MaxVectorAlign = 64; 6466 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6467 "-v128:64-a:8:16-n32:64"); 6468 } 6469 return true; 6470 } 6471 6472 bool hasFeature(StringRef Feature) const override { 6473 return llvm::StringSwitch<bool>(Feature) 6474 .Case("systemz", true) 6475 .Case("htm", HasTransactionalExecution) 6476 .Case("vx", HasVector) 6477 .Default(false); 6478 } 6479 6480 StringRef getABI() const override { 6481 if (HasVector) 6482 return "vector"; 6483 return ""; 6484 } 6485 6486 bool useFloat128ManglingForLongDouble() const override { 6487 return true; 6488 } 6489 }; 6490 6491 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6492 #define BUILTIN(ID, TYPE, ATTRS) \ 6493 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6494 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6495 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6496 #include "clang/Basic/BuiltinsSystemZ.def" 6497 }; 6498 6499 const char *const SystemZTargetInfo::GCCRegNames[] = { 6500 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6501 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6502 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6503 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6504 }; 6505 6506 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6507 return llvm::makeArrayRef(GCCRegNames); 6508 } 6509 6510 bool SystemZTargetInfo:: 6511 validateAsmConstraint(const char *&Name, 6512 TargetInfo::ConstraintInfo &Info) const { 6513 switch (*Name) { 6514 default: 6515 return false; 6516 6517 case 'a': // Address register 6518 case 'd': // Data register (equivalent to 'r') 6519 case 'f': // Floating-point register 6520 Info.setAllowsRegister(); 6521 return true; 6522 6523 case 'I': // Unsigned 8-bit constant 6524 case 'J': // Unsigned 12-bit constant 6525 case 'K': // Signed 16-bit constant 6526 case 'L': // Signed 20-bit displacement (on all targets we support) 6527 case 'M': // 0x7fffffff 6528 return true; 6529 6530 case 'Q': // Memory with base and unsigned 12-bit displacement 6531 case 'R': // Likewise, plus an index 6532 case 'S': // Memory with base and signed 20-bit displacement 6533 case 'T': // Likewise, plus an index 6534 Info.setAllowsMemory(); 6535 return true; 6536 } 6537 } 6538 6539 class MSP430TargetInfo : public TargetInfo { 6540 static const char *const GCCRegNames[]; 6541 6542 public: 6543 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6544 BigEndian = false; 6545 TLSSupported = false; 6546 IntWidth = 16; 6547 IntAlign = 16; 6548 LongWidth = 32; 6549 LongLongWidth = 64; 6550 LongAlign = LongLongAlign = 16; 6551 PointerWidth = 16; 6552 PointerAlign = 16; 6553 SuitableAlign = 16; 6554 SizeType = UnsignedInt; 6555 IntMaxType = SignedLongLong; 6556 IntPtrType = SignedInt; 6557 PtrDiffType = SignedInt; 6558 SigAtomicType = SignedLong; 6559 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6560 } 6561 void getTargetDefines(const LangOptions &Opts, 6562 MacroBuilder &Builder) const override { 6563 Builder.defineMacro("MSP430"); 6564 Builder.defineMacro("__MSP430__"); 6565 // FIXME: defines for different 'flavours' of MCU 6566 } 6567 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6568 // FIXME: Implement. 6569 return None; 6570 } 6571 bool hasFeature(StringRef Feature) const override { 6572 return Feature == "msp430"; 6573 } 6574 ArrayRef<const char *> getGCCRegNames() const override; 6575 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6576 // No aliases. 6577 return None; 6578 } 6579 bool validateAsmConstraint(const char *&Name, 6580 TargetInfo::ConstraintInfo &info) const override { 6581 // FIXME: implement 6582 switch (*Name) { 6583 case 'K': // the constant 1 6584 case 'L': // constant -1^20 .. 1^19 6585 case 'M': // constant 1-4: 6586 return true; 6587 } 6588 // No target constraints for now. 6589 return false; 6590 } 6591 const char *getClobbers() const override { 6592 // FIXME: Is this really right? 6593 return ""; 6594 } 6595 BuiltinVaListKind getBuiltinVaListKind() const override { 6596 // FIXME: implement 6597 return TargetInfo::CharPtrBuiltinVaList; 6598 } 6599 }; 6600 6601 const char *const MSP430TargetInfo::GCCRegNames[] = { 6602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6604 6605 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6606 return llvm::makeArrayRef(GCCRegNames); 6607 } 6608 6609 // LLVM and Clang cannot be used directly to output native binaries for 6610 // target, but is used to compile C code to llvm bitcode with correct 6611 // type and alignment information. 6612 // 6613 // TCE uses the llvm bitcode as input and uses it for generating customized 6614 // target processor and program binary. TCE co-design environment is 6615 // publicly available in http://tce.cs.tut.fi 6616 6617 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6618 3, // opencl_global 6619 4, // opencl_local 6620 5, // opencl_constant 6621 // FIXME: generic has to be added to the target 6622 0, // opencl_generic 6623 0, // cuda_device 6624 0, // cuda_constant 6625 0 // cuda_shared 6626 }; 6627 6628 class TCETargetInfo : public TargetInfo { 6629 public: 6630 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6631 TLSSupported = false; 6632 IntWidth = 32; 6633 LongWidth = LongLongWidth = 32; 6634 PointerWidth = 32; 6635 IntAlign = 32; 6636 LongAlign = LongLongAlign = 32; 6637 PointerAlign = 32; 6638 SuitableAlign = 32; 6639 SizeType = UnsignedInt; 6640 IntMaxType = SignedLong; 6641 IntPtrType = SignedInt; 6642 PtrDiffType = SignedInt; 6643 FloatWidth = 32; 6644 FloatAlign = 32; 6645 DoubleWidth = 32; 6646 DoubleAlign = 32; 6647 LongDoubleWidth = 32; 6648 LongDoubleAlign = 32; 6649 FloatFormat = &llvm::APFloat::IEEEsingle; 6650 DoubleFormat = &llvm::APFloat::IEEEsingle; 6651 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6652 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6653 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6654 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6655 UseAddrSpaceMapMangling = true; 6656 } 6657 6658 void getTargetDefines(const LangOptions &Opts, 6659 MacroBuilder &Builder) const override { 6660 DefineStd(Builder, "tce", Opts); 6661 Builder.defineMacro("__TCE__"); 6662 Builder.defineMacro("__TCE_V1__"); 6663 } 6664 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6665 6666 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6667 const char *getClobbers() const override { return ""; } 6668 BuiltinVaListKind getBuiltinVaListKind() const override { 6669 return TargetInfo::VoidPtrBuiltinVaList; 6670 } 6671 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6672 bool validateAsmConstraint(const char *&Name, 6673 TargetInfo::ConstraintInfo &info) const override { 6674 return true; 6675 } 6676 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6677 return None; 6678 } 6679 }; 6680 6681 class BPFTargetInfo : public TargetInfo { 6682 public: 6683 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6684 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6685 SizeType = UnsignedLong; 6686 PtrDiffType = SignedLong; 6687 IntPtrType = SignedLong; 6688 IntMaxType = SignedLong; 6689 Int64Type = SignedLong; 6690 RegParmMax = 5; 6691 if (Triple.getArch() == llvm::Triple::bpfeb) { 6692 BigEndian = true; 6693 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6694 } else { 6695 BigEndian = false; 6696 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6697 } 6698 MaxAtomicPromoteWidth = 64; 6699 MaxAtomicInlineWidth = 64; 6700 TLSSupported = false; 6701 } 6702 void getTargetDefines(const LangOptions &Opts, 6703 MacroBuilder &Builder) const override { 6704 DefineStd(Builder, "bpf", Opts); 6705 Builder.defineMacro("__BPF__"); 6706 } 6707 bool hasFeature(StringRef Feature) const override { 6708 return Feature == "bpf"; 6709 } 6710 6711 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6712 const char *getClobbers() const override { 6713 return ""; 6714 } 6715 BuiltinVaListKind getBuiltinVaListKind() const override { 6716 return TargetInfo::VoidPtrBuiltinVaList; 6717 } 6718 ArrayRef<const char *> getGCCRegNames() const override { 6719 return None; 6720 } 6721 bool validateAsmConstraint(const char *&Name, 6722 TargetInfo::ConstraintInfo &info) const override { 6723 return true; 6724 } 6725 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6726 return None; 6727 } 6728 }; 6729 6730 class MipsTargetInfoBase : public TargetInfo { 6731 virtual void setDataLayout() = 0; 6732 6733 static const Builtin::Info BuiltinInfo[]; 6734 std::string CPU; 6735 bool IsMips16; 6736 bool IsMicromips; 6737 bool IsNan2008; 6738 bool IsSingleFloat; 6739 enum MipsFloatABI { 6740 HardFloat, SoftFloat 6741 } FloatABI; 6742 enum DspRevEnum { 6743 NoDSP, DSP1, DSP2 6744 } DspRev; 6745 bool HasMSA; 6746 6747 protected: 6748 bool HasFP64; 6749 std::string ABI; 6750 6751 public: 6752 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6753 const std::string &CPUStr) 6754 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6755 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6756 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6757 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6758 } 6759 6760 bool isNaN2008Default() const { 6761 return CPU == "mips32r6" || CPU == "mips64r6"; 6762 } 6763 6764 bool isFP64Default() const { 6765 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6766 } 6767 6768 bool isNan2008() const override { 6769 return IsNan2008; 6770 } 6771 6772 StringRef getABI() const override { return ABI; } 6773 bool setCPU(const std::string &Name) override { 6774 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6775 getTriple().getArch() == llvm::Triple::mipsel; 6776 CPU = Name; 6777 return llvm::StringSwitch<bool>(Name) 6778 .Case("mips1", IsMips32) 6779 .Case("mips2", IsMips32) 6780 .Case("mips3", true) 6781 .Case("mips4", true) 6782 .Case("mips5", true) 6783 .Case("mips32", IsMips32) 6784 .Case("mips32r2", IsMips32) 6785 .Case("mips32r3", IsMips32) 6786 .Case("mips32r5", IsMips32) 6787 .Case("mips32r6", IsMips32) 6788 .Case("mips64", true) 6789 .Case("mips64r2", true) 6790 .Case("mips64r3", true) 6791 .Case("mips64r5", true) 6792 .Case("mips64r6", true) 6793 .Case("octeon", true) 6794 .Case("p5600", true) 6795 .Default(false); 6796 } 6797 const std::string& getCPU() const { return CPU; } 6798 bool 6799 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6800 StringRef CPU, 6801 const std::vector<std::string> &FeaturesVec) const override { 6802 if (CPU.empty()) 6803 CPU = getCPU(); 6804 if (CPU == "octeon") 6805 Features["mips64r2"] = Features["cnmips"] = true; 6806 else 6807 Features[CPU] = true; 6808 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6809 } 6810 6811 void getTargetDefines(const LangOptions &Opts, 6812 MacroBuilder &Builder) const override { 6813 Builder.defineMacro("__mips__"); 6814 Builder.defineMacro("_mips"); 6815 if (Opts.GNUMode) 6816 Builder.defineMacro("mips"); 6817 6818 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6819 6820 switch (FloatABI) { 6821 case HardFloat: 6822 Builder.defineMacro("__mips_hard_float", Twine(1)); 6823 break; 6824 case SoftFloat: 6825 Builder.defineMacro("__mips_soft_float", Twine(1)); 6826 break; 6827 } 6828 6829 if (IsSingleFloat) 6830 Builder.defineMacro("__mips_single_float", Twine(1)); 6831 6832 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6833 Builder.defineMacro("_MIPS_FPSET", 6834 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6835 6836 if (IsMips16) 6837 Builder.defineMacro("__mips16", Twine(1)); 6838 6839 if (IsMicromips) 6840 Builder.defineMacro("__mips_micromips", Twine(1)); 6841 6842 if (IsNan2008) 6843 Builder.defineMacro("__mips_nan2008", Twine(1)); 6844 6845 switch (DspRev) { 6846 default: 6847 break; 6848 case DSP1: 6849 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6850 Builder.defineMacro("__mips_dsp", Twine(1)); 6851 break; 6852 case DSP2: 6853 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6854 Builder.defineMacro("__mips_dspr2", Twine(1)); 6855 Builder.defineMacro("__mips_dsp", Twine(1)); 6856 break; 6857 } 6858 6859 if (HasMSA) 6860 Builder.defineMacro("__mips_msa", Twine(1)); 6861 6862 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6863 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6864 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6865 6866 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6867 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6868 6869 // These shouldn't be defined for MIPS-I but there's no need to check 6870 // for that since MIPS-I isn't supported. 6871 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6872 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6873 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6874 } 6875 6876 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6877 return llvm::makeArrayRef(BuiltinInfo, 6878 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6879 } 6880 bool hasFeature(StringRef Feature) const override { 6881 return llvm::StringSwitch<bool>(Feature) 6882 .Case("mips", true) 6883 .Case("fp64", HasFP64) 6884 .Default(false); 6885 } 6886 BuiltinVaListKind getBuiltinVaListKind() const override { 6887 return TargetInfo::VoidPtrBuiltinVaList; 6888 } 6889 ArrayRef<const char *> getGCCRegNames() const override { 6890 static const char *const GCCRegNames[] = { 6891 // CPU register names 6892 // Must match second column of GCCRegAliases 6893 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6894 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6895 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6896 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6897 // Floating point register names 6898 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6899 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6900 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6901 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6902 // Hi/lo and condition register names 6903 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6904 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 6905 "$ac3hi","$ac3lo", 6906 // MSA register names 6907 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6908 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6909 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6910 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6911 // MSA control register names 6912 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6913 "$msarequest", "$msamap", "$msaunmap" 6914 }; 6915 return llvm::makeArrayRef(GCCRegNames); 6916 } 6917 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6918 bool validateAsmConstraint(const char *&Name, 6919 TargetInfo::ConstraintInfo &Info) const override { 6920 switch (*Name) { 6921 default: 6922 return false; 6923 case 'r': // CPU registers. 6924 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6925 case 'y': // Equivalent to "r", backward compatibility only. 6926 case 'f': // floating-point registers. 6927 case 'c': // $25 for indirect jumps 6928 case 'l': // lo register 6929 case 'x': // hilo register pair 6930 Info.setAllowsRegister(); 6931 return true; 6932 case 'I': // Signed 16-bit constant 6933 case 'J': // Integer 0 6934 case 'K': // Unsigned 16-bit constant 6935 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6936 case 'M': // Constants not loadable via lui, addiu, or ori 6937 case 'N': // Constant -1 to -65535 6938 case 'O': // A signed 15-bit constant 6939 case 'P': // A constant between 1 go 65535 6940 return true; 6941 case 'R': // An address that can be used in a non-macro load or store 6942 Info.setAllowsMemory(); 6943 return true; 6944 case 'Z': 6945 if (Name[1] == 'C') { // An address usable by ll, and sc. 6946 Info.setAllowsMemory(); 6947 Name++; // Skip over 'Z'. 6948 return true; 6949 } 6950 return false; 6951 } 6952 } 6953 6954 std::string convertConstraint(const char *&Constraint) const override { 6955 std::string R; 6956 switch (*Constraint) { 6957 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6958 if (Constraint[1] == 'C') { 6959 R = std::string("^") + std::string(Constraint, 2); 6960 Constraint++; 6961 return R; 6962 } 6963 break; 6964 } 6965 return TargetInfo::convertConstraint(Constraint); 6966 } 6967 6968 const char *getClobbers() const override { 6969 // In GCC, $1 is not widely used in generated code (it's used only in a few 6970 // specific situations), so there is no real need for users to add it to 6971 // the clobbers list if they want to use it in their inline assembly code. 6972 // 6973 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6974 // code generation, so using it in inline assembly without adding it to the 6975 // clobbers list can cause conflicts between the inline assembly code and 6976 // the surrounding generated code. 6977 // 6978 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6979 // operands, which will conflict with the ".set at" assembler option (which 6980 // we use only for inline assembly, in order to maintain compatibility with 6981 // GCC) and will also conflict with the user's usage of $1. 6982 // 6983 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6984 // register for generated code is to automatically clobber $1 for all inline 6985 // assembly code. 6986 // 6987 // FIXME: We should automatically clobber $1 only for inline assembly code 6988 // which actually uses it. This would allow LLVM to use $1 for inline 6989 // assembly operands if the user's assembly code doesn't use it. 6990 return "~{$1}"; 6991 } 6992 6993 bool handleTargetFeatures(std::vector<std::string> &Features, 6994 DiagnosticsEngine &Diags) override { 6995 IsMips16 = false; 6996 IsMicromips = false; 6997 IsNan2008 = isNaN2008Default(); 6998 IsSingleFloat = false; 6999 FloatABI = HardFloat; 7000 DspRev = NoDSP; 7001 HasFP64 = isFP64Default(); 7002 7003 for (const auto &Feature : Features) { 7004 if (Feature == "+single-float") 7005 IsSingleFloat = true; 7006 else if (Feature == "+soft-float") 7007 FloatABI = SoftFloat; 7008 else if (Feature == "+mips16") 7009 IsMips16 = true; 7010 else if (Feature == "+micromips") 7011 IsMicromips = true; 7012 else if (Feature == "+dsp") 7013 DspRev = std::max(DspRev, DSP1); 7014 else if (Feature == "+dspr2") 7015 DspRev = std::max(DspRev, DSP2); 7016 else if (Feature == "+msa") 7017 HasMSA = true; 7018 else if (Feature == "+fp64") 7019 HasFP64 = true; 7020 else if (Feature == "-fp64") 7021 HasFP64 = false; 7022 else if (Feature == "+nan2008") 7023 IsNan2008 = true; 7024 else if (Feature == "-nan2008") 7025 IsNan2008 = false; 7026 } 7027 7028 setDataLayout(); 7029 7030 return true; 7031 } 7032 7033 int getEHDataRegisterNumber(unsigned RegNo) const override { 7034 if (RegNo == 0) return 4; 7035 if (RegNo == 1) return 5; 7036 return -1; 7037 } 7038 7039 bool isCLZForZeroUndef() const override { return false; } 7040 }; 7041 7042 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7043 #define BUILTIN(ID, TYPE, ATTRS) \ 7044 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7045 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7046 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7047 #include "clang/Basic/BuiltinsMips.def" 7048 }; 7049 7050 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7051 public: 7052 Mips32TargetInfoBase(const llvm::Triple &Triple) 7053 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 7054 SizeType = UnsignedInt; 7055 PtrDiffType = SignedInt; 7056 Int64Type = SignedLongLong; 7057 IntMaxType = Int64Type; 7058 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7059 } 7060 bool setABI(const std::string &Name) override { 7061 if (Name == "o32" || Name == "eabi") { 7062 ABI = Name; 7063 return true; 7064 } 7065 return false; 7066 } 7067 void getTargetDefines(const LangOptions &Opts, 7068 MacroBuilder &Builder) const override { 7069 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7070 7071 Builder.defineMacro("__mips", "32"); 7072 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7073 7074 const std::string& CPUStr = getCPU(); 7075 if (CPUStr == "mips32") 7076 Builder.defineMacro("__mips_isa_rev", "1"); 7077 else if (CPUStr == "mips32r2") 7078 Builder.defineMacro("__mips_isa_rev", "2"); 7079 else if (CPUStr == "mips32r3") 7080 Builder.defineMacro("__mips_isa_rev", "3"); 7081 else if (CPUStr == "mips32r5") 7082 Builder.defineMacro("__mips_isa_rev", "5"); 7083 else if (CPUStr == "mips32r6") 7084 Builder.defineMacro("__mips_isa_rev", "6"); 7085 7086 if (ABI == "o32") { 7087 Builder.defineMacro("__mips_o32"); 7088 Builder.defineMacro("_ABIO32", "1"); 7089 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7090 } 7091 else if (ABI == "eabi") 7092 Builder.defineMacro("__mips_eabi"); 7093 else 7094 llvm_unreachable("Invalid ABI for Mips32."); 7095 } 7096 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7097 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7098 { { "at" }, "$1" }, 7099 { { "v0" }, "$2" }, 7100 { { "v1" }, "$3" }, 7101 { { "a0" }, "$4" }, 7102 { { "a1" }, "$5" }, 7103 { { "a2" }, "$6" }, 7104 { { "a3" }, "$7" }, 7105 { { "t0" }, "$8" }, 7106 { { "t1" }, "$9" }, 7107 { { "t2" }, "$10" }, 7108 { { "t3" }, "$11" }, 7109 { { "t4" }, "$12" }, 7110 { { "t5" }, "$13" }, 7111 { { "t6" }, "$14" }, 7112 { { "t7" }, "$15" }, 7113 { { "s0" }, "$16" }, 7114 { { "s1" }, "$17" }, 7115 { { "s2" }, "$18" }, 7116 { { "s3" }, "$19" }, 7117 { { "s4" }, "$20" }, 7118 { { "s5" }, "$21" }, 7119 { { "s6" }, "$22" }, 7120 { { "s7" }, "$23" }, 7121 { { "t8" }, "$24" }, 7122 { { "t9" }, "$25" }, 7123 { { "k0" }, "$26" }, 7124 { { "k1" }, "$27" }, 7125 { { "gp" }, "$28" }, 7126 { { "sp","$sp" }, "$29" }, 7127 { { "fp","$fp" }, "$30" }, 7128 { { "ra" }, "$31" } 7129 }; 7130 return llvm::makeArrayRef(GCCRegAliases); 7131 } 7132 }; 7133 7134 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7135 void setDataLayout() override { 7136 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7137 } 7138 7139 public: 7140 Mips32EBTargetInfo(const llvm::Triple &Triple) 7141 : Mips32TargetInfoBase(Triple) { 7142 } 7143 void getTargetDefines(const LangOptions &Opts, 7144 MacroBuilder &Builder) const override { 7145 DefineStd(Builder, "MIPSEB", Opts); 7146 Builder.defineMacro("_MIPSEB"); 7147 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7148 } 7149 }; 7150 7151 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7152 void setDataLayout() override { 7153 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7154 } 7155 7156 public: 7157 Mips32ELTargetInfo(const llvm::Triple &Triple) 7158 : Mips32TargetInfoBase(Triple) { 7159 BigEndian = false; 7160 } 7161 void getTargetDefines(const LangOptions &Opts, 7162 MacroBuilder &Builder) const override { 7163 DefineStd(Builder, "MIPSEL", Opts); 7164 Builder.defineMacro("_MIPSEL"); 7165 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7166 } 7167 }; 7168 7169 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7170 public: 7171 Mips64TargetInfoBase(const llvm::Triple &Triple) 7172 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7173 LongDoubleWidth = LongDoubleAlign = 128; 7174 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7175 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7176 LongDoubleWidth = LongDoubleAlign = 64; 7177 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7178 } 7179 setN64ABITypes(); 7180 SuitableAlign = 128; 7181 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7182 } 7183 7184 void setN64ABITypes() { 7185 LongWidth = LongAlign = 64; 7186 PointerWidth = PointerAlign = 64; 7187 SizeType = UnsignedLong; 7188 PtrDiffType = SignedLong; 7189 Int64Type = SignedLong; 7190 IntMaxType = Int64Type; 7191 } 7192 7193 void setN32ABITypes() { 7194 LongWidth = LongAlign = 32; 7195 PointerWidth = PointerAlign = 32; 7196 SizeType = UnsignedInt; 7197 PtrDiffType = SignedInt; 7198 Int64Type = SignedLongLong; 7199 IntMaxType = Int64Type; 7200 } 7201 7202 bool setABI(const std::string &Name) override { 7203 if (Name == "n32") { 7204 setN32ABITypes(); 7205 ABI = Name; 7206 return true; 7207 } 7208 if (Name == "n64") { 7209 setN64ABITypes(); 7210 ABI = Name; 7211 return true; 7212 } 7213 return false; 7214 } 7215 7216 void getTargetDefines(const LangOptions &Opts, 7217 MacroBuilder &Builder) const override { 7218 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7219 7220 Builder.defineMacro("__mips", "64"); 7221 Builder.defineMacro("__mips64"); 7222 Builder.defineMacro("__mips64__"); 7223 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7224 7225 const std::string& CPUStr = getCPU(); 7226 if (CPUStr == "mips64") 7227 Builder.defineMacro("__mips_isa_rev", "1"); 7228 else if (CPUStr == "mips64r2") 7229 Builder.defineMacro("__mips_isa_rev", "2"); 7230 else if (CPUStr == "mips64r3") 7231 Builder.defineMacro("__mips_isa_rev", "3"); 7232 else if (CPUStr == "mips64r5") 7233 Builder.defineMacro("__mips_isa_rev", "5"); 7234 else if (CPUStr == "mips64r6") 7235 Builder.defineMacro("__mips_isa_rev", "6"); 7236 7237 if (ABI == "n32") { 7238 Builder.defineMacro("__mips_n32"); 7239 Builder.defineMacro("_ABIN32", "2"); 7240 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7241 } 7242 else if (ABI == "n64") { 7243 Builder.defineMacro("__mips_n64"); 7244 Builder.defineMacro("_ABI64", "3"); 7245 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7246 } 7247 else 7248 llvm_unreachable("Invalid ABI for Mips64."); 7249 7250 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7251 } 7252 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7253 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7254 { { "at" }, "$1" }, 7255 { { "v0" }, "$2" }, 7256 { { "v1" }, "$3" }, 7257 { { "a0" }, "$4" }, 7258 { { "a1" }, "$5" }, 7259 { { "a2" }, "$6" }, 7260 { { "a3" }, "$7" }, 7261 { { "a4" }, "$8" }, 7262 { { "a5" }, "$9" }, 7263 { { "a6" }, "$10" }, 7264 { { "a7" }, "$11" }, 7265 { { "t0" }, "$12" }, 7266 { { "t1" }, "$13" }, 7267 { { "t2" }, "$14" }, 7268 { { "t3" }, "$15" }, 7269 { { "s0" }, "$16" }, 7270 { { "s1" }, "$17" }, 7271 { { "s2" }, "$18" }, 7272 { { "s3" }, "$19" }, 7273 { { "s4" }, "$20" }, 7274 { { "s5" }, "$21" }, 7275 { { "s6" }, "$22" }, 7276 { { "s7" }, "$23" }, 7277 { { "t8" }, "$24" }, 7278 { { "t9" }, "$25" }, 7279 { { "k0" }, "$26" }, 7280 { { "k1" }, "$27" }, 7281 { { "gp" }, "$28" }, 7282 { { "sp","$sp" }, "$29" }, 7283 { { "fp","$fp" }, "$30" }, 7284 { { "ra" }, "$31" } 7285 }; 7286 return llvm::makeArrayRef(GCCRegAliases); 7287 } 7288 7289 bool hasInt128Type() const override { return true; } 7290 }; 7291 7292 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7293 void setDataLayout() override { 7294 if (ABI == "n32") 7295 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7296 else 7297 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7298 } 7299 7300 public: 7301 Mips64EBTargetInfo(const llvm::Triple &Triple) 7302 : Mips64TargetInfoBase(Triple) {} 7303 void getTargetDefines(const LangOptions &Opts, 7304 MacroBuilder &Builder) const override { 7305 DefineStd(Builder, "MIPSEB", Opts); 7306 Builder.defineMacro("_MIPSEB"); 7307 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7308 } 7309 }; 7310 7311 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7312 void setDataLayout() override { 7313 if (ABI == "n32") 7314 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7315 else 7316 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7317 } 7318 public: 7319 Mips64ELTargetInfo(const llvm::Triple &Triple) 7320 : Mips64TargetInfoBase(Triple) { 7321 // Default ABI is n64. 7322 BigEndian = false; 7323 } 7324 void getTargetDefines(const LangOptions &Opts, 7325 MacroBuilder &Builder) const override { 7326 DefineStd(Builder, "MIPSEL", Opts); 7327 Builder.defineMacro("_MIPSEL"); 7328 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7329 } 7330 }; 7331 7332 class PNaClTargetInfo : public TargetInfo { 7333 public: 7334 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7335 BigEndian = false; 7336 this->LongAlign = 32; 7337 this->LongWidth = 32; 7338 this->PointerAlign = 32; 7339 this->PointerWidth = 32; 7340 this->IntMaxType = TargetInfo::SignedLongLong; 7341 this->Int64Type = TargetInfo::SignedLongLong; 7342 this->DoubleAlign = 64; 7343 this->LongDoubleWidth = 64; 7344 this->LongDoubleAlign = 64; 7345 this->SizeType = TargetInfo::UnsignedInt; 7346 this->PtrDiffType = TargetInfo::SignedInt; 7347 this->IntPtrType = TargetInfo::SignedInt; 7348 this->RegParmMax = 0; // Disallow regparm 7349 } 7350 7351 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7352 Builder.defineMacro("__le32__"); 7353 Builder.defineMacro("__pnacl__"); 7354 } 7355 void getTargetDefines(const LangOptions &Opts, 7356 MacroBuilder &Builder) const override { 7357 getArchDefines(Opts, Builder); 7358 } 7359 bool hasFeature(StringRef Feature) const override { 7360 return Feature == "pnacl"; 7361 } 7362 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7363 BuiltinVaListKind getBuiltinVaListKind() const override { 7364 return TargetInfo::PNaClABIBuiltinVaList; 7365 } 7366 ArrayRef<const char *> getGCCRegNames() const override; 7367 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7368 bool validateAsmConstraint(const char *&Name, 7369 TargetInfo::ConstraintInfo &Info) const override { 7370 return false; 7371 } 7372 7373 const char *getClobbers() const override { 7374 return ""; 7375 } 7376 }; 7377 7378 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7379 return None; 7380 } 7381 7382 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7383 return None; 7384 } 7385 7386 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7387 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7388 public: 7389 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7390 Mips32ELTargetInfo(Triple) { 7391 } 7392 7393 BuiltinVaListKind getBuiltinVaListKind() const override { 7394 return TargetInfo::PNaClABIBuiltinVaList; 7395 } 7396 }; 7397 7398 class Le64TargetInfo : public TargetInfo { 7399 static const Builtin::Info BuiltinInfo[]; 7400 7401 public: 7402 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7403 BigEndian = false; 7404 NoAsmVariants = true; 7405 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7406 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7407 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7408 } 7409 7410 void getTargetDefines(const LangOptions &Opts, 7411 MacroBuilder &Builder) const override { 7412 DefineStd(Builder, "unix", Opts); 7413 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7414 Builder.defineMacro("__ELF__"); 7415 } 7416 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7417 return llvm::makeArrayRef(BuiltinInfo, 7418 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7419 } 7420 BuiltinVaListKind getBuiltinVaListKind() const override { 7421 return TargetInfo::PNaClABIBuiltinVaList; 7422 } 7423 const char *getClobbers() const override { return ""; } 7424 ArrayRef<const char *> getGCCRegNames() const override { 7425 return None; 7426 } 7427 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7428 return None; 7429 } 7430 bool validateAsmConstraint(const char *&Name, 7431 TargetInfo::ConstraintInfo &Info) const override { 7432 return false; 7433 } 7434 7435 bool hasProtectedVisibility() const override { return false; } 7436 }; 7437 7438 class WebAssemblyTargetInfo : public TargetInfo { 7439 static const Builtin::Info BuiltinInfo[]; 7440 7441 enum SIMDEnum { 7442 NoSIMD, 7443 SIMD128, 7444 } SIMDLevel; 7445 7446 public: 7447 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7448 : TargetInfo(T), SIMDLevel(NoSIMD) { 7449 BigEndian = false; 7450 NoAsmVariants = true; 7451 SuitableAlign = 128; 7452 LargeArrayMinWidth = 128; 7453 LargeArrayAlign = 128; 7454 SimdDefaultAlign = 128; 7455 SigAtomicType = SignedLong; 7456 LongDoubleWidth = LongDoubleAlign = 128; 7457 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7458 } 7459 7460 protected: 7461 void getTargetDefines(const LangOptions &Opts, 7462 MacroBuilder &Builder) const override { 7463 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7464 if (SIMDLevel >= SIMD128) 7465 Builder.defineMacro("__wasm_simd128__"); 7466 } 7467 7468 private: 7469 bool 7470 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7471 StringRef CPU, 7472 const std::vector<std::string> &FeaturesVec) const override { 7473 if (CPU == "bleeding-edge") 7474 Features["simd128"] = true; 7475 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7476 } 7477 bool hasFeature(StringRef Feature) const final { 7478 return llvm::StringSwitch<bool>(Feature) 7479 .Case("simd128", SIMDLevel >= SIMD128) 7480 .Default(false); 7481 } 7482 bool handleTargetFeatures(std::vector<std::string> &Features, 7483 DiagnosticsEngine &Diags) final { 7484 for (const auto &Feature : Features) { 7485 if (Feature == "+simd128") { 7486 SIMDLevel = std::max(SIMDLevel, SIMD128); 7487 continue; 7488 } 7489 if (Feature == "-simd128") { 7490 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7491 continue; 7492 } 7493 7494 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7495 << "-target-feature"; 7496 return false; 7497 } 7498 return true; 7499 } 7500 bool setCPU(const std::string &Name) final { 7501 return llvm::StringSwitch<bool>(Name) 7502 .Case("mvp", true) 7503 .Case("bleeding-edge", true) 7504 .Case("generic", true) 7505 .Default(false); 7506 } 7507 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7508 return llvm::makeArrayRef(BuiltinInfo, 7509 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7510 } 7511 BuiltinVaListKind getBuiltinVaListKind() const final { 7512 return VoidPtrBuiltinVaList; 7513 } 7514 ArrayRef<const char *> getGCCRegNames() const final { 7515 return None; 7516 } 7517 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7518 return None; 7519 } 7520 bool 7521 validateAsmConstraint(const char *&Name, 7522 TargetInfo::ConstraintInfo &Info) const final { 7523 return false; 7524 } 7525 const char *getClobbers() const final { return ""; } 7526 bool isCLZForZeroUndef() const final { return false; } 7527 bool hasInt128Type() const final { return true; } 7528 IntType getIntTypeByWidth(unsigned BitWidth, 7529 bool IsSigned) const final { 7530 // WebAssembly prefers long long for explicitly 64-bit integers. 7531 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7532 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7533 } 7534 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7535 bool IsSigned) const final { 7536 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7537 return BitWidth == 64 7538 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7539 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7540 } 7541 }; 7542 7543 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7544 #define BUILTIN(ID, TYPE, ATTRS) \ 7545 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7546 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7547 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7548 #include "clang/Basic/BuiltinsWebAssembly.def" 7549 }; 7550 7551 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7552 public: 7553 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7554 : WebAssemblyTargetInfo(T) { 7555 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7556 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7557 } 7558 7559 protected: 7560 void getTargetDefines(const LangOptions &Opts, 7561 MacroBuilder &Builder) const override { 7562 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7563 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7564 } 7565 }; 7566 7567 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7568 public: 7569 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7570 : WebAssemblyTargetInfo(T) { 7571 LongAlign = LongWidth = 64; 7572 PointerAlign = PointerWidth = 64; 7573 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7574 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7575 } 7576 7577 protected: 7578 void getTargetDefines(const LangOptions &Opts, 7579 MacroBuilder &Builder) const override { 7580 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7581 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7582 } 7583 }; 7584 7585 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7586 #define BUILTIN(ID, TYPE, ATTRS) \ 7587 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7588 #include "clang/Basic/BuiltinsLe64.def" 7589 }; 7590 7591 static const unsigned SPIRAddrSpaceMap[] = { 7592 1, // opencl_global 7593 3, // opencl_local 7594 2, // opencl_constant 7595 4, // opencl_generic 7596 0, // cuda_device 7597 0, // cuda_constant 7598 0 // cuda_shared 7599 }; 7600 class SPIRTargetInfo : public TargetInfo { 7601 public: 7602 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7603 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7604 "SPIR target must use unknown OS"); 7605 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7606 "SPIR target must use unknown environment type"); 7607 BigEndian = false; 7608 TLSSupported = false; 7609 LongWidth = LongAlign = 64; 7610 AddrSpaceMap = &SPIRAddrSpaceMap; 7611 UseAddrSpaceMapMangling = true; 7612 // Define available target features 7613 // These must be defined in sorted order! 7614 NoAsmVariants = true; 7615 } 7616 void getTargetDefines(const LangOptions &Opts, 7617 MacroBuilder &Builder) const override { 7618 DefineStd(Builder, "SPIR", Opts); 7619 } 7620 bool hasFeature(StringRef Feature) const override { 7621 return Feature == "spir"; 7622 } 7623 7624 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7625 const char *getClobbers() const override { return ""; } 7626 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7627 bool validateAsmConstraint(const char *&Name, 7628 TargetInfo::ConstraintInfo &info) const override { 7629 return true; 7630 } 7631 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7632 return None; 7633 } 7634 BuiltinVaListKind getBuiltinVaListKind() const override { 7635 return TargetInfo::VoidPtrBuiltinVaList; 7636 } 7637 7638 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7639 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7640 : CCCR_Warning; 7641 } 7642 7643 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7644 return CC_SpirFunction; 7645 } 7646 }; 7647 7648 class SPIR32TargetInfo : public SPIRTargetInfo { 7649 public: 7650 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7651 PointerWidth = PointerAlign = 32; 7652 SizeType = TargetInfo::UnsignedInt; 7653 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7654 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7655 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7656 } 7657 void getTargetDefines(const LangOptions &Opts, 7658 MacroBuilder &Builder) const override { 7659 DefineStd(Builder, "SPIR32", Opts); 7660 } 7661 }; 7662 7663 class SPIR64TargetInfo : public SPIRTargetInfo { 7664 public: 7665 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7666 PointerWidth = PointerAlign = 64; 7667 SizeType = TargetInfo::UnsignedLong; 7668 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7669 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7670 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7671 } 7672 void getTargetDefines(const LangOptions &Opts, 7673 MacroBuilder &Builder) const override { 7674 DefineStd(Builder, "SPIR64", Opts); 7675 } 7676 }; 7677 7678 class XCoreTargetInfo : public TargetInfo { 7679 static const Builtin::Info BuiltinInfo[]; 7680 public: 7681 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7682 BigEndian = false; 7683 NoAsmVariants = true; 7684 LongLongAlign = 32; 7685 SuitableAlign = 32; 7686 DoubleAlign = LongDoubleAlign = 32; 7687 SizeType = UnsignedInt; 7688 PtrDiffType = SignedInt; 7689 IntPtrType = SignedInt; 7690 WCharType = UnsignedChar; 7691 WIntType = UnsignedInt; 7692 UseZeroLengthBitfieldAlignment = true; 7693 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7694 "-f64:32-a:0:32-n32"); 7695 } 7696 void getTargetDefines(const LangOptions &Opts, 7697 MacroBuilder &Builder) const override { 7698 Builder.defineMacro("__XS1B__"); 7699 } 7700 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7701 return llvm::makeArrayRef(BuiltinInfo, 7702 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7703 } 7704 BuiltinVaListKind getBuiltinVaListKind() const override { 7705 return TargetInfo::VoidPtrBuiltinVaList; 7706 } 7707 const char *getClobbers() const override { 7708 return ""; 7709 } 7710 ArrayRef<const char *> getGCCRegNames() const override { 7711 static const char * const GCCRegNames[] = { 7712 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7713 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7714 }; 7715 return llvm::makeArrayRef(GCCRegNames); 7716 } 7717 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7718 return None; 7719 } 7720 bool validateAsmConstraint(const char *&Name, 7721 TargetInfo::ConstraintInfo &Info) const override { 7722 return false; 7723 } 7724 int getEHDataRegisterNumber(unsigned RegNo) const override { 7725 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7726 return (RegNo < 2)? RegNo : -1; 7727 } 7728 bool allowsLargerPreferedTypeAlignment() const override { 7729 return false; 7730 } 7731 }; 7732 7733 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7734 #define BUILTIN(ID, TYPE, ATTRS) \ 7735 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7736 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7737 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7738 #include "clang/Basic/BuiltinsXCore.def" 7739 }; 7740 7741 // x86_32 Android target 7742 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7743 public: 7744 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7745 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7746 SuitableAlign = 32; 7747 LongDoubleWidth = 64; 7748 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7749 } 7750 }; 7751 7752 // x86_64 Android target 7753 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7754 public: 7755 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7756 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7757 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7758 } 7759 7760 bool useFloat128ManglingForLongDouble() const override { 7761 return true; 7762 } 7763 }; 7764 } // end anonymous namespace 7765 7766 //===----------------------------------------------------------------------===// 7767 // Driver code 7768 //===----------------------------------------------------------------------===// 7769 7770 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7771 llvm::Triple::OSType os = Triple.getOS(); 7772 7773 switch (Triple.getArch()) { 7774 default: 7775 return nullptr; 7776 7777 case llvm::Triple::xcore: 7778 return new XCoreTargetInfo(Triple); 7779 7780 case llvm::Triple::hexagon: 7781 return new HexagonTargetInfo(Triple); 7782 7783 case llvm::Triple::lanai: 7784 return new LanaiTargetInfo(Triple); 7785 7786 case llvm::Triple::aarch64: 7787 if (Triple.isOSDarwin()) 7788 return new DarwinAArch64TargetInfo(Triple); 7789 7790 switch (os) { 7791 case llvm::Triple::CloudABI: 7792 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7793 case llvm::Triple::FreeBSD: 7794 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7795 case llvm::Triple::Linux: 7796 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7797 case llvm::Triple::NetBSD: 7798 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7799 default: 7800 return new AArch64leTargetInfo(Triple); 7801 } 7802 7803 case llvm::Triple::aarch64_be: 7804 switch (os) { 7805 case llvm::Triple::FreeBSD: 7806 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7807 case llvm::Triple::Linux: 7808 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7809 case llvm::Triple::NetBSD: 7810 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7811 default: 7812 return new AArch64beTargetInfo(Triple); 7813 } 7814 7815 case llvm::Triple::arm: 7816 case llvm::Triple::thumb: 7817 if (Triple.isOSBinFormatMachO()) 7818 return new DarwinARMTargetInfo(Triple); 7819 7820 switch (os) { 7821 case llvm::Triple::Linux: 7822 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7823 case llvm::Triple::FreeBSD: 7824 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7825 case llvm::Triple::NetBSD: 7826 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7827 case llvm::Triple::OpenBSD: 7828 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7829 case llvm::Triple::Bitrig: 7830 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7831 case llvm::Triple::RTEMS: 7832 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7833 case llvm::Triple::NaCl: 7834 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7835 case llvm::Triple::Win32: 7836 switch (Triple.getEnvironment()) { 7837 case llvm::Triple::Cygnus: 7838 return new CygwinARMTargetInfo(Triple); 7839 case llvm::Triple::GNU: 7840 return new MinGWARMTargetInfo(Triple); 7841 case llvm::Triple::Itanium: 7842 return new ItaniumWindowsARMleTargetInfo(Triple); 7843 case llvm::Triple::MSVC: 7844 default: // Assume MSVC for unknown environments 7845 return new MicrosoftARMleTargetInfo(Triple); 7846 } 7847 default: 7848 return new ARMleTargetInfo(Triple); 7849 } 7850 7851 case llvm::Triple::armeb: 7852 case llvm::Triple::thumbeb: 7853 if (Triple.isOSDarwin()) 7854 return new DarwinARMTargetInfo(Triple); 7855 7856 switch (os) { 7857 case llvm::Triple::Linux: 7858 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7859 case llvm::Triple::FreeBSD: 7860 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7861 case llvm::Triple::NetBSD: 7862 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7863 case llvm::Triple::OpenBSD: 7864 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7865 case llvm::Triple::Bitrig: 7866 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7867 case llvm::Triple::RTEMS: 7868 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7869 case llvm::Triple::NaCl: 7870 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7871 default: 7872 return new ARMbeTargetInfo(Triple); 7873 } 7874 7875 case llvm::Triple::bpfeb: 7876 case llvm::Triple::bpfel: 7877 return new BPFTargetInfo(Triple); 7878 7879 case llvm::Triple::msp430: 7880 return new MSP430TargetInfo(Triple); 7881 7882 case llvm::Triple::mips: 7883 switch (os) { 7884 case llvm::Triple::Linux: 7885 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7886 case llvm::Triple::RTEMS: 7887 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7888 case llvm::Triple::FreeBSD: 7889 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7890 case llvm::Triple::NetBSD: 7891 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7892 default: 7893 return new Mips32EBTargetInfo(Triple); 7894 } 7895 7896 case llvm::Triple::mipsel: 7897 switch (os) { 7898 case llvm::Triple::Linux: 7899 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7900 case llvm::Triple::RTEMS: 7901 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7902 case llvm::Triple::FreeBSD: 7903 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7904 case llvm::Triple::NetBSD: 7905 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7906 case llvm::Triple::NaCl: 7907 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7908 default: 7909 return new Mips32ELTargetInfo(Triple); 7910 } 7911 7912 case llvm::Triple::mips64: 7913 switch (os) { 7914 case llvm::Triple::Linux: 7915 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7916 case llvm::Triple::RTEMS: 7917 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7918 case llvm::Triple::FreeBSD: 7919 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7920 case llvm::Triple::NetBSD: 7921 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7922 case llvm::Triple::OpenBSD: 7923 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7924 default: 7925 return new Mips64EBTargetInfo(Triple); 7926 } 7927 7928 case llvm::Triple::mips64el: 7929 switch (os) { 7930 case llvm::Triple::Linux: 7931 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7932 case llvm::Triple::RTEMS: 7933 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7934 case llvm::Triple::FreeBSD: 7935 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7936 case llvm::Triple::NetBSD: 7937 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7938 case llvm::Triple::OpenBSD: 7939 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7940 default: 7941 return new Mips64ELTargetInfo(Triple); 7942 } 7943 7944 case llvm::Triple::le32: 7945 switch (os) { 7946 case llvm::Triple::NaCl: 7947 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7948 default: 7949 return nullptr; 7950 } 7951 7952 case llvm::Triple::le64: 7953 return new Le64TargetInfo(Triple); 7954 7955 case llvm::Triple::ppc: 7956 if (Triple.isOSDarwin()) 7957 return new DarwinPPC32TargetInfo(Triple); 7958 switch (os) { 7959 case llvm::Triple::Linux: 7960 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7961 case llvm::Triple::FreeBSD: 7962 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7963 case llvm::Triple::NetBSD: 7964 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7965 case llvm::Triple::OpenBSD: 7966 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7967 case llvm::Triple::RTEMS: 7968 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7969 default: 7970 return new PPC32TargetInfo(Triple); 7971 } 7972 7973 case llvm::Triple::ppc64: 7974 if (Triple.isOSDarwin()) 7975 return new DarwinPPC64TargetInfo(Triple); 7976 switch (os) { 7977 case llvm::Triple::Linux: 7978 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7979 case llvm::Triple::Lv2: 7980 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7981 case llvm::Triple::FreeBSD: 7982 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7983 case llvm::Triple::NetBSD: 7984 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7985 default: 7986 return new PPC64TargetInfo(Triple); 7987 } 7988 7989 case llvm::Triple::ppc64le: 7990 switch (os) { 7991 case llvm::Triple::Linux: 7992 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7993 case llvm::Triple::NetBSD: 7994 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7995 default: 7996 return new PPC64TargetInfo(Triple); 7997 } 7998 7999 case llvm::Triple::nvptx: 8000 return new NVPTX32TargetInfo(Triple); 8001 case llvm::Triple::nvptx64: 8002 return new NVPTX64TargetInfo(Triple); 8003 8004 case llvm::Triple::amdgcn: 8005 case llvm::Triple::r600: 8006 return new AMDGPUTargetInfo(Triple); 8007 8008 case llvm::Triple::sparc: 8009 switch (os) { 8010 case llvm::Triple::Linux: 8011 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 8012 case llvm::Triple::Solaris: 8013 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 8014 case llvm::Triple::NetBSD: 8015 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 8016 case llvm::Triple::OpenBSD: 8017 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 8018 case llvm::Triple::RTEMS: 8019 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 8020 default: 8021 return new SparcV8TargetInfo(Triple); 8022 } 8023 8024 // The 'sparcel' architecture copies all the above cases except for Solaris. 8025 case llvm::Triple::sparcel: 8026 switch (os) { 8027 case llvm::Triple::Linux: 8028 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 8029 case llvm::Triple::NetBSD: 8030 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8031 case llvm::Triple::OpenBSD: 8032 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 8033 case llvm::Triple::RTEMS: 8034 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 8035 default: 8036 return new SparcV8elTargetInfo(Triple); 8037 } 8038 8039 case llvm::Triple::sparcv9: 8040 switch (os) { 8041 case llvm::Triple::Linux: 8042 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 8043 case llvm::Triple::Solaris: 8044 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 8045 case llvm::Triple::NetBSD: 8046 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 8047 case llvm::Triple::OpenBSD: 8048 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 8049 case llvm::Triple::FreeBSD: 8050 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 8051 default: 8052 return new SparcV9TargetInfo(Triple); 8053 } 8054 8055 case llvm::Triple::systemz: 8056 switch (os) { 8057 case llvm::Triple::Linux: 8058 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 8059 default: 8060 return new SystemZTargetInfo(Triple); 8061 } 8062 8063 case llvm::Triple::tce: 8064 return new TCETargetInfo(Triple); 8065 8066 case llvm::Triple::x86: 8067 if (Triple.isOSDarwin()) 8068 return new DarwinI386TargetInfo(Triple); 8069 8070 switch (os) { 8071 case llvm::Triple::CloudABI: 8072 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 8073 case llvm::Triple::Linux: { 8074 switch (Triple.getEnvironment()) { 8075 default: 8076 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 8077 case llvm::Triple::Android: 8078 return new AndroidX86_32TargetInfo(Triple); 8079 } 8080 } 8081 case llvm::Triple::DragonFly: 8082 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 8083 case llvm::Triple::NetBSD: 8084 return new NetBSDI386TargetInfo(Triple); 8085 case llvm::Triple::OpenBSD: 8086 return new OpenBSDI386TargetInfo(Triple); 8087 case llvm::Triple::Bitrig: 8088 return new BitrigI386TargetInfo(Triple); 8089 case llvm::Triple::FreeBSD: 8090 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8091 case llvm::Triple::KFreeBSD: 8092 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 8093 case llvm::Triple::Minix: 8094 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 8095 case llvm::Triple::Solaris: 8096 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 8097 case llvm::Triple::Win32: { 8098 switch (Triple.getEnvironment()) { 8099 case llvm::Triple::Cygnus: 8100 return new CygwinX86_32TargetInfo(Triple); 8101 case llvm::Triple::GNU: 8102 return new MinGWX86_32TargetInfo(Triple); 8103 case llvm::Triple::Itanium: 8104 case llvm::Triple::MSVC: 8105 default: // Assume MSVC for unknown environments 8106 return new MicrosoftX86_32TargetInfo(Triple); 8107 } 8108 } 8109 case llvm::Triple::Haiku: 8110 return new HaikuX86_32TargetInfo(Triple); 8111 case llvm::Triple::RTEMS: 8112 return new RTEMSX86_32TargetInfo(Triple); 8113 case llvm::Triple::NaCl: 8114 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 8115 case llvm::Triple::ELFIAMCU: 8116 return new MCUX86_32TargetInfo(Triple); 8117 default: 8118 return new X86_32TargetInfo(Triple); 8119 } 8120 8121 case llvm::Triple::x86_64: 8122 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8123 return new DarwinX86_64TargetInfo(Triple); 8124 8125 switch (os) { 8126 case llvm::Triple::CloudABI: 8127 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 8128 case llvm::Triple::Linux: { 8129 switch (Triple.getEnvironment()) { 8130 default: 8131 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 8132 case llvm::Triple::Android: 8133 return new AndroidX86_64TargetInfo(Triple); 8134 } 8135 } 8136 case llvm::Triple::DragonFly: 8137 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 8138 case llvm::Triple::NetBSD: 8139 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 8140 case llvm::Triple::OpenBSD: 8141 return new OpenBSDX86_64TargetInfo(Triple); 8142 case llvm::Triple::Bitrig: 8143 return new BitrigX86_64TargetInfo(Triple); 8144 case llvm::Triple::FreeBSD: 8145 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8146 case llvm::Triple::KFreeBSD: 8147 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 8148 case llvm::Triple::Solaris: 8149 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 8150 case llvm::Triple::Win32: { 8151 switch (Triple.getEnvironment()) { 8152 case llvm::Triple::Cygnus: 8153 return new CygwinX86_64TargetInfo(Triple); 8154 case llvm::Triple::GNU: 8155 return new MinGWX86_64TargetInfo(Triple); 8156 case llvm::Triple::MSVC: 8157 default: // Assume MSVC for unknown environments 8158 return new MicrosoftX86_64TargetInfo(Triple); 8159 } 8160 } 8161 case llvm::Triple::NaCl: 8162 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8163 case llvm::Triple::PS4: 8164 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8165 default: 8166 return new X86_64TargetInfo(Triple); 8167 } 8168 8169 case llvm::Triple::spir: { 8170 if (Triple.getOS() != llvm::Triple::UnknownOS || 8171 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8172 return nullptr; 8173 return new SPIR32TargetInfo(Triple); 8174 } 8175 case llvm::Triple::spir64: { 8176 if (Triple.getOS() != llvm::Triple::UnknownOS || 8177 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8178 return nullptr; 8179 return new SPIR64TargetInfo(Triple); 8180 } 8181 case llvm::Triple::wasm32: 8182 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8183 return nullptr; 8184 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8185 case llvm::Triple::wasm64: 8186 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8187 return nullptr; 8188 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8189 } 8190 } 8191 8192 /// CreateTargetInfo - Return the target info object for the specified target 8193 /// options. 8194 TargetInfo * 8195 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8196 const std::shared_ptr<TargetOptions> &Opts) { 8197 llvm::Triple Triple(Opts->Triple); 8198 8199 // Construct the target 8200 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8201 if (!Target) { 8202 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8203 return nullptr; 8204 } 8205 Target->TargetOpts = Opts; 8206 8207 // Set the target CPU if specified. 8208 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8209 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8210 return nullptr; 8211 } 8212 8213 // Set the target ABI if specified. 8214 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8215 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8216 return nullptr; 8217 } 8218 8219 // Set the fp math unit. 8220 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8221 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8222 return nullptr; 8223 } 8224 8225 // Compute the default target features, we need the target to handle this 8226 // because features may have dependencies on one another. 8227 llvm::StringMap<bool> Features; 8228 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8229 Opts->FeaturesAsWritten)) 8230 return nullptr; 8231 8232 // Add the features to the compile options. 8233 Opts->Features.clear(); 8234 for (const auto &F : Features) 8235 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8236 8237 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8238 return nullptr; 8239 8240 return Target.release(); 8241 } 8242