1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 const char *getStaticInitSectionSpecifier() const override { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const override { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const override { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const override { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 486 } 487 }; 488 489 // AuroraUX target 490 template<typename Target> 491 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 DefineStd(Builder, "sun", Opts); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 Builder.defineMacro("__svr4__"); 499 Builder.defineMacro("__SVR4"); 500 } 501 public: 502 AuroraUXTargetInfo(const llvm::Triple &Triple) 503 : OSTargetInfo<Target>(Triple) { 504 this->UserLabelPrefix = ""; 505 this->WCharType = this->SignedLong; 506 // FIXME: WIntType should be SignedLong 507 } 508 }; 509 510 // Solaris target 511 template<typename Target> 512 class SolarisTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const override { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 522 // newer, but to 500 for everything else. feature_test.h has a check to 523 // ensure that you are not using C99 with an old version of X/Open or C89 524 // with a new version. 525 if (Opts.C99 || Opts.C11) 526 Builder.defineMacro("_XOPEN_SOURCE", "600"); 527 else 528 Builder.defineMacro("_XOPEN_SOURCE", "500"); 529 if (Opts.CPlusPlus) 530 Builder.defineMacro("__C99FEATURES__"); 531 Builder.defineMacro("_LARGEFILE_SOURCE"); 532 Builder.defineMacro("_LARGEFILE64_SOURCE"); 533 Builder.defineMacro("__EXTENSIONS__"); 534 Builder.defineMacro("_REENTRANT"); 535 } 536 public: 537 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 538 this->UserLabelPrefix = ""; 539 this->WCharType = this->SignedInt; 540 // FIXME: WIntType should be SignedLong 541 } 542 }; 543 544 // Windows target 545 template<typename Target> 546 class WindowsTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 Builder.defineMacro("_WIN32"); 551 } 552 void getVisualStudioDefines(const LangOptions &Opts, 553 MacroBuilder &Builder) const { 554 if (Opts.CPlusPlus) { 555 if (Opts.RTTI) 556 Builder.defineMacro("_CPPRTTI"); 557 558 if (Opts.Exceptions) 559 Builder.defineMacro("_CPPUNWIND"); 560 } 561 562 if (!Opts.CharIsSigned) 563 Builder.defineMacro("_CHAR_UNSIGNED"); 564 565 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 566 // but it works for now. 567 if (Opts.POSIXThreads) 568 Builder.defineMacro("_MT"); 569 570 if (Opts.MSCVersion != 0) 571 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 572 573 if (Opts.MicrosoftExt) { 574 Builder.defineMacro("_MSC_EXTENSIONS"); 575 576 if (Opts.CPlusPlus11) { 577 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 578 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 579 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 580 } 581 } 582 583 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 584 } 585 586 public: 587 WindowsTargetInfo(const llvm::Triple &Triple) 588 : OSTargetInfo<Target>(Triple) {} 589 }; 590 591 template <typename Target> 592 class NaClTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 if (Opts.POSIXThreads) 597 Builder.defineMacro("_REENTRANT"); 598 if (Opts.CPlusPlus) 599 Builder.defineMacro("_GNU_SOURCE"); 600 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__native_client__"); 604 } 605 606 public: 607 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 608 this->UserLabelPrefix = ""; 609 this->LongAlign = 32; 610 this->LongWidth = 32; 611 this->PointerAlign = 32; 612 this->PointerWidth = 32; 613 this->IntMaxType = TargetInfo::SignedLongLong; 614 this->UIntMaxType = TargetInfo::UnsignedLongLong; 615 this->Int64Type = TargetInfo::SignedLongLong; 616 this->DoubleAlign = 64; 617 this->LongDoubleWidth = 64; 618 this->LongDoubleAlign = 64; 619 this->LongLongWidth = 64; 620 this->LongLongAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 if (Triple.getArch() == llvm::Triple::arm) { 627 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 628 } else if (Triple.getArch() == llvm::Triple::x86) { 629 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 630 } else if (Triple.getArch() == llvm::Triple::x86_64) { 631 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 632 } else if (Triple.getArch() == llvm::Triple::mipsel) { 633 // Handled on mips' setDescriptionString. 634 } else { 635 assert(Triple.getArch() == llvm::Triple::le32); 636 this->DescriptionString = "e-p:32:32-i64:64"; 637 } 638 } 639 typename Target::CallingConvCheckResult checkCallingConvention( 640 CallingConv CC) const override { 641 return CC == CC_PnaclCall ? Target::CCCR_OK : 642 Target::checkCallingConvention(CC); 643 } 644 }; 645 } // end anonymous namespace. 646 647 //===----------------------------------------------------------------------===// 648 // Specific target implementations. 649 //===----------------------------------------------------------------------===// 650 651 namespace { 652 // PPC abstract base class 653 class PPCTargetInfo : public TargetInfo { 654 static const Builtin::Info BuiltinInfo[]; 655 static const char * const GCCRegNames[]; 656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 657 std::string CPU; 658 659 // Target cpu features. 660 bool HasVSX; 661 662 public: 663 PPCTargetInfo(const llvm::Triple &Triple) 664 : TargetInfo(Triple), HasVSX(false) { 665 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 666 LongDoubleWidth = LongDoubleAlign = 128; 667 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 668 } 669 670 /// \brief Flags for architecture specific defines. 671 typedef enum { 672 ArchDefineNone = 0, 673 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 674 ArchDefinePpcgr = 1 << 1, 675 ArchDefinePpcsq = 1 << 2, 676 ArchDefine440 = 1 << 3, 677 ArchDefine603 = 1 << 4, 678 ArchDefine604 = 1 << 5, 679 ArchDefinePwr4 = 1 << 6, 680 ArchDefinePwr5 = 1 << 7, 681 ArchDefinePwr5x = 1 << 8, 682 ArchDefinePwr6 = 1 << 9, 683 ArchDefinePwr6x = 1 << 10, 684 ArchDefinePwr7 = 1 << 11, 685 ArchDefineA2 = 1 << 12, 686 ArchDefineA2q = 1 << 13 687 } ArchDefineTypes; 688 689 // Note: GCC recognizes the following additional cpus: 690 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 691 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 692 // titan, rs64. 693 bool setCPU(const std::string &Name) override { 694 bool CPUKnown = llvm::StringSwitch<bool>(Name) 695 .Case("generic", true) 696 .Case("440", true) 697 .Case("450", true) 698 .Case("601", true) 699 .Case("602", true) 700 .Case("603", true) 701 .Case("603e", true) 702 .Case("603ev", true) 703 .Case("604", true) 704 .Case("604e", true) 705 .Case("620", true) 706 .Case("630", true) 707 .Case("g3", true) 708 .Case("7400", true) 709 .Case("g4", true) 710 .Case("7450", true) 711 .Case("g4+", true) 712 .Case("750", true) 713 .Case("970", true) 714 .Case("g5", true) 715 .Case("a2", true) 716 .Case("a2q", true) 717 .Case("e500mc", true) 718 .Case("e5500", true) 719 .Case("power3", true) 720 .Case("pwr3", true) 721 .Case("power4", true) 722 .Case("pwr4", true) 723 .Case("power5", true) 724 .Case("pwr5", true) 725 .Case("power5x", true) 726 .Case("pwr5x", true) 727 .Case("power6", true) 728 .Case("pwr6", true) 729 .Case("power6x", true) 730 .Case("pwr6x", true) 731 .Case("power7", true) 732 .Case("pwr7", true) 733 .Case("powerpc", true) 734 .Case("ppc", true) 735 .Case("powerpc64", true) 736 .Case("ppc64", true) 737 .Case("powerpc64le", true) 738 .Case("ppc64le", true) 739 .Default(false); 740 741 if (CPUKnown) 742 CPU = Name; 743 744 return CPUKnown; 745 } 746 747 void getTargetBuiltins(const Builtin::Info *&Records, 748 unsigned &NumRecords) const override { 749 Records = BuiltinInfo; 750 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 751 } 752 753 bool isCLZForZeroUndef() const override { return false; } 754 755 void getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const override; 757 758 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 759 760 bool handleTargetFeatures(std::vector<std::string> &Features, 761 DiagnosticsEngine &Diags) override; 762 bool hasFeature(StringRef Feature) const override; 763 764 void getGCCRegNames(const char * const *&Names, 765 unsigned &NumNames) const override; 766 void getGCCRegAliases(const GCCRegAlias *&Aliases, 767 unsigned &NumAliases) const override; 768 bool validateAsmConstraint(const char *&Name, 769 TargetInfo::ConstraintInfo &Info) const override { 770 switch (*Name) { 771 default: return false; 772 case 'O': // Zero 773 break; 774 case 'b': // Base register 775 case 'f': // Floating point register 776 Info.setAllowsRegister(); 777 break; 778 // FIXME: The following are added to allow parsing. 779 // I just took a guess at what the actions should be. 780 // Also, is more specific checking needed? I.e. specific registers? 781 case 'd': // Floating point register (containing 64-bit value) 782 case 'v': // Altivec vector register 783 Info.setAllowsRegister(); 784 break; 785 case 'w': 786 switch (Name[1]) { 787 case 'd':// VSX vector register to hold vector double data 788 case 'f':// VSX vector register to hold vector float data 789 case 's':// VSX vector register to hold scalar float data 790 case 'a':// Any VSX register 791 case 'c':// An individual CR bit 792 break; 793 default: 794 return false; 795 } 796 Info.setAllowsRegister(); 797 Name++; // Skip over 'w'. 798 break; 799 case 'h': // `MQ', `CTR', or `LINK' register 800 case 'q': // `MQ' register 801 case 'c': // `CTR' register 802 case 'l': // `LINK' register 803 case 'x': // `CR' register (condition register) number 0 804 case 'y': // `CR' register (condition register) 805 case 'z': // `XER[CA]' carry bit (part of the XER register) 806 Info.setAllowsRegister(); 807 break; 808 case 'I': // Signed 16-bit constant 809 case 'J': // Unsigned 16-bit constant shifted left 16 bits 810 // (use `L' instead for SImode constants) 811 case 'K': // Unsigned 16-bit constant 812 case 'L': // Signed 16-bit constant shifted left 16 bits 813 case 'M': // Constant larger than 31 814 case 'N': // Exact power of 2 815 case 'P': // Constant whose negation is a signed 16-bit constant 816 case 'G': // Floating point constant that can be loaded into a 817 // register with one instruction per word 818 case 'H': // Integer/Floating point constant that can be loaded 819 // into a register using three instructions 820 break; 821 case 'm': // Memory operand. Note that on PowerPC targets, m can 822 // include addresses that update the base register. It 823 // is therefore only safe to use `m' in an asm statement 824 // if that asm statement accesses the operand exactly once. 825 // The asm statement must also use `%U<opno>' as a 826 // placeholder for the "update" flag in the corresponding 827 // load or store instruction. For example: 828 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 829 // is correct but: 830 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 831 // is not. Use es rather than m if you don't want the base 832 // register to be updated. 833 case 'e': 834 if (Name[1] != 's') 835 return false; 836 // es: A "stable" memory operand; that is, one which does not 837 // include any automodification of the base register. Unlike 838 // `m', this constraint can be used in asm statements that 839 // might access the operand several times, or that might not 840 // access it at all. 841 Info.setAllowsMemory(); 842 Name++; // Skip over 'e'. 843 break; 844 case 'Q': // Memory operand that is an offset from a register (it is 845 // usually better to use `m' or `es' in asm statements) 846 case 'Z': // Memory operand that is an indexed or indirect from a 847 // register (it is usually better to use `m' or `es' in 848 // asm statements) 849 Info.setAllowsMemory(); 850 Info.setAllowsRegister(); 851 break; 852 case 'R': // AIX TOC entry 853 case 'a': // Address operand that is an indexed or indirect from a 854 // register (`p' is preferable for asm statements) 855 case 'S': // Constant suitable as a 64-bit mask operand 856 case 'T': // Constant suitable as a 32-bit mask operand 857 case 'U': // System V Release 4 small data area reference 858 case 't': // AND masks that can be performed by two rldic{l, r} 859 // instructions 860 case 'W': // Vector constant that does not require memory 861 case 'j': // Vector constant that is all zeros. 862 break; 863 // End FIXME. 864 } 865 return true; 866 } 867 std::string convertConstraint(const char *&Constraint) const override { 868 std::string R; 869 switch (*Constraint) { 870 case 'e': 871 case 'w': 872 // Two-character constraint; add "^" hint for later parsing. 873 R = std::string("^") + std::string(Constraint, 2); 874 Constraint++; 875 break; 876 default: 877 return TargetInfo::convertConstraint(Constraint); 878 } 879 return R; 880 } 881 const char *getClobbers() const override { 882 return ""; 883 } 884 int getEHDataRegisterNumber(unsigned RegNo) const override { 885 if (RegNo == 0) return 3; 886 if (RegNo == 1) return 4; 887 return -1; 888 } 889 }; 890 891 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 892 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 894 ALL_LANGUAGES }, 895 #include "clang/Basic/BuiltinsPPC.def" 896 }; 897 898 /// handleTargetFeatures - Perform initialization based on the user 899 /// configured set of features. 900 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 901 DiagnosticsEngine &Diags) { 902 // Remember the maximum enabled sselevel. 903 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 904 // Ignore disabled features. 905 if (Features[i][0] == '-') 906 continue; 907 908 StringRef Feature = StringRef(Features[i]).substr(1); 909 910 if (Feature == "vsx") { 911 HasVSX = true; 912 continue; 913 } 914 915 // TODO: Finish this list and add an assert that we've handled them 916 // all. 917 } 918 919 return true; 920 } 921 922 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 923 /// #defines that are not tied to a specific subtarget. 924 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 925 MacroBuilder &Builder) const { 926 // Target identification. 927 Builder.defineMacro("__ppc__"); 928 Builder.defineMacro("__PPC__"); 929 Builder.defineMacro("_ARCH_PPC"); 930 Builder.defineMacro("__powerpc__"); 931 Builder.defineMacro("__POWERPC__"); 932 if (PointerWidth == 64) { 933 Builder.defineMacro("_ARCH_PPC64"); 934 Builder.defineMacro("__powerpc64__"); 935 Builder.defineMacro("__ppc64__"); 936 Builder.defineMacro("__PPC64__"); 937 } 938 939 // Target properties. 940 if (getTriple().getArch() == llvm::Triple::ppc64le) { 941 Builder.defineMacro("_LITTLE_ENDIAN"); 942 Builder.defineMacro("_CALL_ELF","2"); 943 } else { 944 if (getTriple().getOS() != llvm::Triple::NetBSD && 945 getTriple().getOS() != llvm::Triple::OpenBSD) 946 Builder.defineMacro("_BIG_ENDIAN"); 947 } 948 949 // Subtarget options. 950 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 951 Builder.defineMacro("__REGISTER_PREFIX__", ""); 952 953 // FIXME: Should be controlled by command line option. 954 if (LongDoubleWidth == 128) 955 Builder.defineMacro("__LONG_DOUBLE_128__"); 956 957 if (Opts.AltiVec) { 958 Builder.defineMacro("__VEC__", "10206"); 959 Builder.defineMacro("__ALTIVEC__"); 960 } 961 962 // CPU identification. 963 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 964 .Case("440", ArchDefineName) 965 .Case("450", ArchDefineName | ArchDefine440) 966 .Case("601", ArchDefineName) 967 .Case("602", ArchDefineName | ArchDefinePpcgr) 968 .Case("603", ArchDefineName | ArchDefinePpcgr) 969 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 970 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 971 .Case("604", ArchDefineName | ArchDefinePpcgr) 972 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 973 .Case("620", ArchDefineName | ArchDefinePpcgr) 974 .Case("630", ArchDefineName | ArchDefinePpcgr) 975 .Case("7400", ArchDefineName | ArchDefinePpcgr) 976 .Case("7450", ArchDefineName | ArchDefinePpcgr) 977 .Case("750", ArchDefineName | ArchDefinePpcgr) 978 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 979 | ArchDefinePpcsq) 980 .Case("a2", ArchDefineA2) 981 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 982 .Case("pwr3", ArchDefinePpcgr) 983 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 984 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 985 | ArchDefinePpcsq) 986 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 987 | ArchDefinePpcgr | ArchDefinePpcsq) 988 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 989 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 990 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 991 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 992 | ArchDefinePpcsq) 993 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 994 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 995 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 996 .Case("power3", ArchDefinePpcgr) 997 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 998 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 999 | ArchDefinePpcsq) 1000 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1001 | ArchDefinePpcgr | ArchDefinePpcsq) 1002 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1003 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1004 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1005 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1006 | ArchDefinePpcsq) 1007 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1008 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1009 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1010 .Default(ArchDefineNone); 1011 1012 if (defs & ArchDefineName) 1013 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1014 if (defs & ArchDefinePpcgr) 1015 Builder.defineMacro("_ARCH_PPCGR"); 1016 if (defs & ArchDefinePpcsq) 1017 Builder.defineMacro("_ARCH_PPCSQ"); 1018 if (defs & ArchDefine440) 1019 Builder.defineMacro("_ARCH_440"); 1020 if (defs & ArchDefine603) 1021 Builder.defineMacro("_ARCH_603"); 1022 if (defs & ArchDefine604) 1023 Builder.defineMacro("_ARCH_604"); 1024 if (defs & ArchDefinePwr4) 1025 Builder.defineMacro("_ARCH_PWR4"); 1026 if (defs & ArchDefinePwr5) 1027 Builder.defineMacro("_ARCH_PWR5"); 1028 if (defs & ArchDefinePwr5x) 1029 Builder.defineMacro("_ARCH_PWR5X"); 1030 if (defs & ArchDefinePwr6) 1031 Builder.defineMacro("_ARCH_PWR6"); 1032 if (defs & ArchDefinePwr6x) 1033 Builder.defineMacro("_ARCH_PWR6X"); 1034 if (defs & ArchDefinePwr7) 1035 Builder.defineMacro("_ARCH_PWR7"); 1036 if (defs & ArchDefineA2) 1037 Builder.defineMacro("_ARCH_A2"); 1038 if (defs & ArchDefineA2q) { 1039 Builder.defineMacro("_ARCH_A2Q"); 1040 Builder.defineMacro("_ARCH_QP"); 1041 } 1042 1043 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1044 Builder.defineMacro("__bg__"); 1045 Builder.defineMacro("__THW_BLUEGENE__"); 1046 Builder.defineMacro("__bgq__"); 1047 Builder.defineMacro("__TOS_BGQ__"); 1048 } 1049 1050 if (HasVSX) 1051 Builder.defineMacro("__VSX__"); 1052 1053 // FIXME: The following are not yet generated here by Clang, but are 1054 // generated by GCC: 1055 // 1056 // _SOFT_FLOAT_ 1057 // __RECIP_PRECISION__ 1058 // __APPLE_ALTIVEC__ 1059 // __RECIP__ 1060 // __RECIPF__ 1061 // __RSQRTE__ 1062 // __RSQRTEF__ 1063 // _SOFT_DOUBLE_ 1064 // __NO_LWSYNC__ 1065 // __HAVE_BSWAP__ 1066 // __LONGDOUBLE128 1067 // __CMODEL_MEDIUM__ 1068 // __CMODEL_LARGE__ 1069 // _CALL_SYSV 1070 // _CALL_DARWIN 1071 // __NO_FPRS__ 1072 } 1073 1074 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1075 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1076 .Case("7400", true) 1077 .Case("g4", true) 1078 .Case("7450", true) 1079 .Case("g4+", true) 1080 .Case("970", true) 1081 .Case("g5", true) 1082 .Case("pwr6", true) 1083 .Case("pwr7", true) 1084 .Case("ppc64", true) 1085 .Case("ppc64le", true) 1086 .Default(false); 1087 1088 Features["qpx"] = (CPU == "a2q"); 1089 } 1090 1091 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1092 return Feature == "powerpc"; 1093 } 1094 1095 1096 const char * const PPCTargetInfo::GCCRegNames[] = { 1097 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1098 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1099 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1100 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1105 "mq", "lr", "ctr", "ap", 1106 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1107 "xer", 1108 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1109 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1110 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1111 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1112 "vrsave", "vscr", 1113 "spe_acc", "spefscr", 1114 "sfp" 1115 }; 1116 1117 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1118 unsigned &NumNames) const { 1119 Names = GCCRegNames; 1120 NumNames = llvm::array_lengthof(GCCRegNames); 1121 } 1122 1123 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1124 // While some of these aliases do map to different registers 1125 // they still share the same register name. 1126 { { "0" }, "r0" }, 1127 { { "1"}, "r1" }, 1128 { { "2" }, "r2" }, 1129 { { "3" }, "r3" }, 1130 { { "4" }, "r4" }, 1131 { { "5" }, "r5" }, 1132 { { "6" }, "r6" }, 1133 { { "7" }, "r7" }, 1134 { { "8" }, "r8" }, 1135 { { "9" }, "r9" }, 1136 { { "10" }, "r10" }, 1137 { { "11" }, "r11" }, 1138 { { "12" }, "r12" }, 1139 { { "13" }, "r13" }, 1140 { { "14" }, "r14" }, 1141 { { "15" }, "r15" }, 1142 { { "16" }, "r16" }, 1143 { { "17" }, "r17" }, 1144 { { "18" }, "r18" }, 1145 { { "19" }, "r19" }, 1146 { { "20" }, "r20" }, 1147 { { "21" }, "r21" }, 1148 { { "22" }, "r22" }, 1149 { { "23" }, "r23" }, 1150 { { "24" }, "r24" }, 1151 { { "25" }, "r25" }, 1152 { { "26" }, "r26" }, 1153 { { "27" }, "r27" }, 1154 { { "28" }, "r28" }, 1155 { { "29" }, "r29" }, 1156 { { "30" }, "r30" }, 1157 { { "31" }, "r31" }, 1158 { { "fr0" }, "f0" }, 1159 { { "fr1" }, "f1" }, 1160 { { "fr2" }, "f2" }, 1161 { { "fr3" }, "f3" }, 1162 { { "fr4" }, "f4" }, 1163 { { "fr5" }, "f5" }, 1164 { { "fr6" }, "f6" }, 1165 { { "fr7" }, "f7" }, 1166 { { "fr8" }, "f8" }, 1167 { { "fr9" }, "f9" }, 1168 { { "fr10" }, "f10" }, 1169 { { "fr11" }, "f11" }, 1170 { { "fr12" }, "f12" }, 1171 { { "fr13" }, "f13" }, 1172 { { "fr14" }, "f14" }, 1173 { { "fr15" }, "f15" }, 1174 { { "fr16" }, "f16" }, 1175 { { "fr17" }, "f17" }, 1176 { { "fr18" }, "f18" }, 1177 { { "fr19" }, "f19" }, 1178 { { "fr20" }, "f20" }, 1179 { { "fr21" }, "f21" }, 1180 { { "fr22" }, "f22" }, 1181 { { "fr23" }, "f23" }, 1182 { { "fr24" }, "f24" }, 1183 { { "fr25" }, "f25" }, 1184 { { "fr26" }, "f26" }, 1185 { { "fr27" }, "f27" }, 1186 { { "fr28" }, "f28" }, 1187 { { "fr29" }, "f29" }, 1188 { { "fr30" }, "f30" }, 1189 { { "fr31" }, "f31" }, 1190 { { "cc" }, "cr0" }, 1191 }; 1192 1193 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1194 unsigned &NumAliases) const { 1195 Aliases = GCCRegAliases; 1196 NumAliases = llvm::array_lengthof(GCCRegAliases); 1197 } 1198 } // end anonymous namespace. 1199 1200 namespace { 1201 class PPC32TargetInfo : public PPCTargetInfo { 1202 public: 1203 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1204 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1205 1206 switch (getTriple().getOS()) { 1207 case llvm::Triple::Linux: 1208 case llvm::Triple::FreeBSD: 1209 case llvm::Triple::NetBSD: 1210 SizeType = UnsignedInt; 1211 PtrDiffType = SignedInt; 1212 IntPtrType = SignedInt; 1213 break; 1214 default: 1215 break; 1216 } 1217 1218 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1219 LongDoubleWidth = LongDoubleAlign = 64; 1220 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1221 } 1222 1223 // PPC32 supports atomics up to 4 bytes. 1224 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1225 } 1226 1227 BuiltinVaListKind getBuiltinVaListKind() const override { 1228 // This is the ELF definition, and is overridden by the Darwin sub-target 1229 return TargetInfo::PowerABIBuiltinVaList; 1230 } 1231 }; 1232 } // end anonymous namespace. 1233 1234 // Note: ABI differences may eventually require us to have a separate 1235 // TargetInfo for little endian. 1236 namespace { 1237 class PPC64TargetInfo : public PPCTargetInfo { 1238 public: 1239 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1240 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1241 IntMaxType = SignedLong; 1242 UIntMaxType = UnsignedLong; 1243 Int64Type = SignedLong; 1244 1245 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1246 LongDoubleWidth = LongDoubleAlign = 64; 1247 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1248 DescriptionString = "E-m:e-i64:64-n32:64"; 1249 } else { 1250 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1251 DescriptionString = "e-m:e-i64:64-n32:64"; 1252 } else { 1253 DescriptionString = "E-m:e-i64:64-n32:64"; 1254 } 1255 } 1256 1257 // PPC64 supports atomics up to 8 bytes. 1258 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1259 } 1260 BuiltinVaListKind getBuiltinVaListKind() const override { 1261 return TargetInfo::CharPtrBuiltinVaList; 1262 } 1263 }; 1264 } // end anonymous namespace. 1265 1266 1267 namespace { 1268 class DarwinPPC32TargetInfo : 1269 public DarwinTargetInfo<PPC32TargetInfo> { 1270 public: 1271 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1272 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1273 HasAlignMac68kSupport = true; 1274 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1275 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1276 LongLongAlign = 32; 1277 SuitableAlign = 128; 1278 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1279 } 1280 BuiltinVaListKind getBuiltinVaListKind() const override { 1281 return TargetInfo::CharPtrBuiltinVaList; 1282 } 1283 }; 1284 1285 class DarwinPPC64TargetInfo : 1286 public DarwinTargetInfo<PPC64TargetInfo> { 1287 public: 1288 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1289 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1290 HasAlignMac68kSupport = true; 1291 SuitableAlign = 128; 1292 DescriptionString = "E-m:o-i64:64-n32:64"; 1293 } 1294 }; 1295 } // end anonymous namespace. 1296 1297 namespace { 1298 static const unsigned NVPTXAddrSpaceMap[] = { 1299 1, // opencl_global 1300 3, // opencl_local 1301 4, // opencl_constant 1302 1, // cuda_device 1303 4, // cuda_constant 1304 3, // cuda_shared 1305 }; 1306 class NVPTXTargetInfo : public TargetInfo { 1307 static const char * const GCCRegNames[]; 1308 static const Builtin::Info BuiltinInfo[]; 1309 public: 1310 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1311 BigEndian = false; 1312 TLSSupported = false; 1313 LongWidth = LongAlign = 64; 1314 AddrSpaceMap = &NVPTXAddrSpaceMap; 1315 UseAddrSpaceMapMangling = true; 1316 // Define available target features 1317 // These must be defined in sorted order! 1318 NoAsmVariants = true; 1319 } 1320 void getTargetDefines(const LangOptions &Opts, 1321 MacroBuilder &Builder) const override { 1322 Builder.defineMacro("__PTX__"); 1323 Builder.defineMacro("__NVPTX__"); 1324 } 1325 void getTargetBuiltins(const Builtin::Info *&Records, 1326 unsigned &NumRecords) const override { 1327 Records = BuiltinInfo; 1328 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1329 } 1330 bool hasFeature(StringRef Feature) const override { 1331 return Feature == "ptx" || Feature == "nvptx"; 1332 } 1333 1334 void getGCCRegNames(const char * const *&Names, 1335 unsigned &NumNames) const override; 1336 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1337 unsigned &NumAliases) const override { 1338 // No aliases. 1339 Aliases = 0; 1340 NumAliases = 0; 1341 } 1342 bool validateAsmConstraint(const char *&Name, 1343 TargetInfo::ConstraintInfo &Info) const override { 1344 switch (*Name) { 1345 default: return false; 1346 case 'c': 1347 case 'h': 1348 case 'r': 1349 case 'l': 1350 case 'f': 1351 case 'd': 1352 Info.setAllowsRegister(); 1353 return true; 1354 } 1355 } 1356 const char *getClobbers() const override { 1357 // FIXME: Is this really right? 1358 return ""; 1359 } 1360 BuiltinVaListKind getBuiltinVaListKind() const override { 1361 // FIXME: implement 1362 return TargetInfo::CharPtrBuiltinVaList; 1363 } 1364 bool setCPU(const std::string &Name) override { 1365 bool Valid = llvm::StringSwitch<bool>(Name) 1366 .Case("sm_20", true) 1367 .Case("sm_21", true) 1368 .Case("sm_30", true) 1369 .Case("sm_35", true) 1370 .Default(false); 1371 1372 return Valid; 1373 } 1374 }; 1375 1376 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1377 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1378 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1379 ALL_LANGUAGES }, 1380 #include "clang/Basic/BuiltinsNVPTX.def" 1381 }; 1382 1383 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1384 "r0" 1385 }; 1386 1387 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1388 unsigned &NumNames) const { 1389 Names = GCCRegNames; 1390 NumNames = llvm::array_lengthof(GCCRegNames); 1391 } 1392 1393 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1394 public: 1395 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1396 PointerWidth = PointerAlign = 32; 1397 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1398 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1399 } 1400 }; 1401 1402 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1403 public: 1404 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1405 PointerWidth = PointerAlign = 64; 1406 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1407 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1408 } 1409 }; 1410 } 1411 1412 namespace { 1413 1414 static const unsigned R600AddrSpaceMap[] = { 1415 1, // opencl_global 1416 3, // opencl_local 1417 2, // opencl_constant 1418 1, // cuda_device 1419 2, // cuda_constant 1420 3 // cuda_shared 1421 }; 1422 1423 static const char *DescriptionStringR600 = 1424 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1425 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1426 1427 static const char *DescriptionStringR600DoubleOps = 1428 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1429 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1430 1431 static const char *DescriptionStringSI = 1432 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1433 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1434 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1435 1436 class R600TargetInfo : public TargetInfo { 1437 /// \brief The GPU profiles supported by the R600 target. 1438 enum GPUKind { 1439 GK_NONE, 1440 GK_R600, 1441 GK_R600_DOUBLE_OPS, 1442 GK_R700, 1443 GK_R700_DOUBLE_OPS, 1444 GK_EVERGREEN, 1445 GK_EVERGREEN_DOUBLE_OPS, 1446 GK_NORTHERN_ISLANDS, 1447 GK_CAYMAN, 1448 GK_SOUTHERN_ISLANDS, 1449 GK_SEA_ISLANDS 1450 } GPU; 1451 1452 public: 1453 R600TargetInfo(const llvm::Triple &Triple) 1454 : TargetInfo(Triple), GPU(GK_R600) { 1455 DescriptionString = DescriptionStringR600; 1456 AddrSpaceMap = &R600AddrSpaceMap; 1457 UseAddrSpaceMapMangling = true; 1458 } 1459 1460 const char * getClobbers() const override { 1461 return ""; 1462 } 1463 1464 void getGCCRegNames(const char * const *&Names, 1465 unsigned &numNames) const override { 1466 Names = NULL; 1467 numNames = 0; 1468 } 1469 1470 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1471 unsigned &NumAliases) const override { 1472 Aliases = NULL; 1473 NumAliases = 0; 1474 } 1475 1476 bool validateAsmConstraint(const char *&Name, 1477 TargetInfo::ConstraintInfo &info) const override { 1478 return true; 1479 } 1480 1481 void getTargetBuiltins(const Builtin::Info *&Records, 1482 unsigned &NumRecords) const override { 1483 Records = NULL; 1484 NumRecords = 0; 1485 } 1486 1487 1488 void getTargetDefines(const LangOptions &Opts, 1489 MacroBuilder &Builder) const override { 1490 Builder.defineMacro("__R600__"); 1491 } 1492 1493 BuiltinVaListKind getBuiltinVaListKind() const override { 1494 return TargetInfo::CharPtrBuiltinVaList; 1495 } 1496 1497 bool setCPU(const std::string &Name) override { 1498 GPU = llvm::StringSwitch<GPUKind>(Name) 1499 .Case("r600" , GK_R600) 1500 .Case("rv610", GK_R600) 1501 .Case("rv620", GK_R600) 1502 .Case("rv630", GK_R600) 1503 .Case("rv635", GK_R600) 1504 .Case("rs780", GK_R600) 1505 .Case("rs880", GK_R600) 1506 .Case("rv670", GK_R600_DOUBLE_OPS) 1507 .Case("rv710", GK_R700) 1508 .Case("rv730", GK_R700) 1509 .Case("rv740", GK_R700_DOUBLE_OPS) 1510 .Case("rv770", GK_R700_DOUBLE_OPS) 1511 .Case("palm", GK_EVERGREEN) 1512 .Case("cedar", GK_EVERGREEN) 1513 .Case("sumo", GK_EVERGREEN) 1514 .Case("sumo2", GK_EVERGREEN) 1515 .Case("redwood", GK_EVERGREEN) 1516 .Case("juniper", GK_EVERGREEN) 1517 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1518 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1519 .Case("barts", GK_NORTHERN_ISLANDS) 1520 .Case("turks", GK_NORTHERN_ISLANDS) 1521 .Case("caicos", GK_NORTHERN_ISLANDS) 1522 .Case("cayman", GK_CAYMAN) 1523 .Case("aruba", GK_CAYMAN) 1524 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1525 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1526 .Case("verde", GK_SOUTHERN_ISLANDS) 1527 .Case("oland", GK_SOUTHERN_ISLANDS) 1528 .Case("bonaire", GK_SEA_ISLANDS) 1529 .Case("kabini", GK_SEA_ISLANDS) 1530 .Case("kaveri", GK_SEA_ISLANDS) 1531 .Case("hawaii", GK_SEA_ISLANDS) 1532 .Default(GK_NONE); 1533 1534 if (GPU == GK_NONE) { 1535 return false; 1536 } 1537 1538 // Set the correct data layout 1539 switch (GPU) { 1540 case GK_NONE: 1541 case GK_R600: 1542 case GK_R700: 1543 case GK_EVERGREEN: 1544 case GK_NORTHERN_ISLANDS: 1545 DescriptionString = DescriptionStringR600; 1546 break; 1547 case GK_R600_DOUBLE_OPS: 1548 case GK_R700_DOUBLE_OPS: 1549 case GK_EVERGREEN_DOUBLE_OPS: 1550 case GK_CAYMAN: 1551 DescriptionString = DescriptionStringR600DoubleOps; 1552 break; 1553 case GK_SOUTHERN_ISLANDS: 1554 case GK_SEA_ISLANDS: 1555 DescriptionString = DescriptionStringSI; 1556 break; 1557 } 1558 1559 return true; 1560 } 1561 }; 1562 1563 } // end anonymous namespace 1564 1565 namespace { 1566 // Namespace for x86 abstract base class 1567 const Builtin::Info BuiltinInfo[] = { 1568 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1569 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1570 ALL_LANGUAGES }, 1571 #include "clang/Basic/BuiltinsX86.def" 1572 }; 1573 1574 static const char* const GCCRegNames[] = { 1575 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1576 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1577 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1578 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1579 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1580 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1581 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1582 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1583 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1584 }; 1585 1586 const TargetInfo::AddlRegName AddlRegNames[] = { 1587 { { "al", "ah", "eax", "rax" }, 0 }, 1588 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1589 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1590 { { "dl", "dh", "edx", "rdx" }, 1 }, 1591 { { "esi", "rsi" }, 4 }, 1592 { { "edi", "rdi" }, 5 }, 1593 { { "esp", "rsp" }, 7 }, 1594 { { "ebp", "rbp" }, 6 }, 1595 }; 1596 1597 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1598 // most of the implementation can be shared. 1599 class X86TargetInfo : public TargetInfo { 1600 enum X86SSEEnum { 1601 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1602 } SSELevel; 1603 enum MMX3DNowEnum { 1604 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1605 } MMX3DNowLevel; 1606 enum XOPEnum { 1607 NoXOP, 1608 SSE4A, 1609 FMA4, 1610 XOP 1611 } XOPLevel; 1612 1613 bool HasAES; 1614 bool HasPCLMUL; 1615 bool HasLZCNT; 1616 bool HasRDRND; 1617 bool HasBMI; 1618 bool HasBMI2; 1619 bool HasPOPCNT; 1620 bool HasRTM; 1621 bool HasPRFCHW; 1622 bool HasRDSEED; 1623 bool HasTBM; 1624 bool HasFMA; 1625 bool HasF16C; 1626 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1627 bool HasSHA; 1628 bool HasCX16; 1629 1630 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1631 /// 1632 /// Each enumeration represents a particular CPU supported by Clang. These 1633 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1634 enum CPUKind { 1635 CK_Generic, 1636 1637 /// \name i386 1638 /// i386-generation processors. 1639 //@{ 1640 CK_i386, 1641 //@} 1642 1643 /// \name i486 1644 /// i486-generation processors. 1645 //@{ 1646 CK_i486, 1647 CK_WinChipC6, 1648 CK_WinChip2, 1649 CK_C3, 1650 //@} 1651 1652 /// \name i586 1653 /// i586-generation processors, P5 microarchitecture based. 1654 //@{ 1655 CK_i586, 1656 CK_Pentium, 1657 CK_PentiumMMX, 1658 //@} 1659 1660 /// \name i686 1661 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1662 //@{ 1663 CK_i686, 1664 CK_PentiumPro, 1665 CK_Pentium2, 1666 CK_Pentium3, 1667 CK_Pentium3M, 1668 CK_PentiumM, 1669 CK_C3_2, 1670 1671 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1672 /// Clang however has some logic to suport this. 1673 // FIXME: Warn, deprecate, and potentially remove this. 1674 CK_Yonah, 1675 //@} 1676 1677 /// \name Netburst 1678 /// Netburst microarchitecture based processors. 1679 //@{ 1680 CK_Pentium4, 1681 CK_Pentium4M, 1682 CK_Prescott, 1683 CK_Nocona, 1684 //@} 1685 1686 /// \name Core 1687 /// Core microarchitecture based processors. 1688 //@{ 1689 CK_Core2, 1690 1691 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1692 /// codename which GCC no longer accepts as an option to -march, but Clang 1693 /// has some logic for recognizing it. 1694 // FIXME: Warn, deprecate, and potentially remove this. 1695 CK_Penryn, 1696 //@} 1697 1698 /// \name Atom 1699 /// Atom processors 1700 //@{ 1701 CK_Atom, 1702 CK_Silvermont, 1703 //@} 1704 1705 /// \name Nehalem 1706 /// Nehalem microarchitecture based processors. 1707 //@{ 1708 CK_Corei7, 1709 CK_Corei7AVX, 1710 CK_CoreAVXi, 1711 CK_CoreAVX2, 1712 //@} 1713 1714 /// \name Knights Landing 1715 /// Knights Landing processor. 1716 CK_KNL, 1717 1718 /// \name K6 1719 /// K6 architecture processors. 1720 //@{ 1721 CK_K6, 1722 CK_K6_2, 1723 CK_K6_3, 1724 //@} 1725 1726 /// \name K7 1727 /// K7 architecture processors. 1728 //@{ 1729 CK_Athlon, 1730 CK_AthlonThunderbird, 1731 CK_Athlon4, 1732 CK_AthlonXP, 1733 CK_AthlonMP, 1734 //@} 1735 1736 /// \name K8 1737 /// K8 architecture processors. 1738 //@{ 1739 CK_Athlon64, 1740 CK_Athlon64SSE3, 1741 CK_AthlonFX, 1742 CK_K8, 1743 CK_K8SSE3, 1744 CK_Opteron, 1745 CK_OpteronSSE3, 1746 CK_AMDFAM10, 1747 //@} 1748 1749 /// \name Bobcat 1750 /// Bobcat architecture processors. 1751 //@{ 1752 CK_BTVER1, 1753 CK_BTVER2, 1754 //@} 1755 1756 /// \name Bulldozer 1757 /// Bulldozer architecture processors. 1758 //@{ 1759 CK_BDVER1, 1760 CK_BDVER2, 1761 CK_BDVER3, 1762 //@} 1763 1764 /// This specification is deprecated and will be removed in the future. 1765 /// Users should prefer \see CK_K8. 1766 // FIXME: Warn on this when the CPU is set to it. 1767 CK_x86_64, 1768 //@} 1769 1770 /// \name Geode 1771 /// Geode processors. 1772 //@{ 1773 CK_Geode 1774 //@} 1775 } CPU; 1776 1777 enum FPMathKind { 1778 FP_Default, 1779 FP_SSE, 1780 FP_387 1781 } FPMath; 1782 1783 public: 1784 X86TargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1786 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1787 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1788 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1789 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1790 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1791 FPMath(FP_Default) { 1792 BigEndian = false; 1793 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1794 } 1795 unsigned getFloatEvalMethod() const override { 1796 // X87 evaluates with 80 bits "long double" precision. 1797 return SSELevel == NoSSE ? 2 : 0; 1798 } 1799 void getTargetBuiltins(const Builtin::Info *&Records, 1800 unsigned &NumRecords) const override { 1801 Records = BuiltinInfo; 1802 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1803 } 1804 void getGCCRegNames(const char * const *&Names, 1805 unsigned &NumNames) const override { 1806 Names = GCCRegNames; 1807 NumNames = llvm::array_lengthof(GCCRegNames); 1808 } 1809 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1810 unsigned &NumAliases) const override { 1811 Aliases = 0; 1812 NumAliases = 0; 1813 } 1814 void getGCCAddlRegNames(const AddlRegName *&Names, 1815 unsigned &NumNames) const override { 1816 Names = AddlRegNames; 1817 NumNames = llvm::array_lengthof(AddlRegNames); 1818 } 1819 bool validateAsmConstraint(const char *&Name, 1820 TargetInfo::ConstraintInfo &info) const override; 1821 std::string convertConstraint(const char *&Constraint) const override; 1822 const char *getClobbers() const override { 1823 return "~{dirflag},~{fpsr},~{flags}"; 1824 } 1825 void getTargetDefines(const LangOptions &Opts, 1826 MacroBuilder &Builder) const override; 1827 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1828 bool Enabled); 1829 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1830 bool Enabled); 1831 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1832 bool Enabled); 1833 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1834 StringRef Name, bool Enabled) const override { 1835 setFeatureEnabledImpl(Features, Name, Enabled); 1836 } 1837 // This exists purely to cut down on the number of virtual calls in 1838 // getDefaultFeatures which calls this repeatedly. 1839 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1840 StringRef Name, bool Enabled); 1841 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1842 bool hasFeature(StringRef Feature) const override; 1843 bool handleTargetFeatures(std::vector<std::string> &Features, 1844 DiagnosticsEngine &Diags) override; 1845 const char* getABI() const override { 1846 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1847 return "avx"; 1848 else if (getTriple().getArch() == llvm::Triple::x86 && 1849 MMX3DNowLevel == NoMMX3DNow) 1850 return "no-mmx"; 1851 return ""; 1852 } 1853 bool setCPU(const std::string &Name) override { 1854 CPU = llvm::StringSwitch<CPUKind>(Name) 1855 .Case("i386", CK_i386) 1856 .Case("i486", CK_i486) 1857 .Case("winchip-c6", CK_WinChipC6) 1858 .Case("winchip2", CK_WinChip2) 1859 .Case("c3", CK_C3) 1860 .Case("i586", CK_i586) 1861 .Case("pentium", CK_Pentium) 1862 .Case("pentium-mmx", CK_PentiumMMX) 1863 .Case("i686", CK_i686) 1864 .Case("pentiumpro", CK_PentiumPro) 1865 .Case("pentium2", CK_Pentium2) 1866 .Case("pentium3", CK_Pentium3) 1867 .Case("pentium3m", CK_Pentium3M) 1868 .Case("pentium-m", CK_PentiumM) 1869 .Case("c3-2", CK_C3_2) 1870 .Case("yonah", CK_Yonah) 1871 .Case("pentium4", CK_Pentium4) 1872 .Case("pentium4m", CK_Pentium4M) 1873 .Case("prescott", CK_Prescott) 1874 .Case("nocona", CK_Nocona) 1875 .Case("core2", CK_Core2) 1876 .Case("penryn", CK_Penryn) 1877 .Case("atom", CK_Atom) 1878 .Case("slm", CK_Silvermont) 1879 .Case("corei7", CK_Corei7) 1880 .Case("corei7-avx", CK_Corei7AVX) 1881 .Case("core-avx-i", CK_CoreAVXi) 1882 .Case("core-avx2", CK_CoreAVX2) 1883 .Case("knl", CK_KNL) 1884 .Case("k6", CK_K6) 1885 .Case("k6-2", CK_K6_2) 1886 .Case("k6-3", CK_K6_3) 1887 .Case("athlon", CK_Athlon) 1888 .Case("athlon-tbird", CK_AthlonThunderbird) 1889 .Case("athlon-4", CK_Athlon4) 1890 .Case("athlon-xp", CK_AthlonXP) 1891 .Case("athlon-mp", CK_AthlonMP) 1892 .Case("athlon64", CK_Athlon64) 1893 .Case("athlon64-sse3", CK_Athlon64SSE3) 1894 .Case("athlon-fx", CK_AthlonFX) 1895 .Case("k8", CK_K8) 1896 .Case("k8-sse3", CK_K8SSE3) 1897 .Case("opteron", CK_Opteron) 1898 .Case("opteron-sse3", CK_OpteronSSE3) 1899 .Case("amdfam10", CK_AMDFAM10) 1900 .Case("btver1", CK_BTVER1) 1901 .Case("btver2", CK_BTVER2) 1902 .Case("bdver1", CK_BDVER1) 1903 .Case("bdver2", CK_BDVER2) 1904 .Case("bdver3", CK_BDVER3) 1905 .Case("x86-64", CK_x86_64) 1906 .Case("geode", CK_Geode) 1907 .Default(CK_Generic); 1908 1909 // Perform any per-CPU checks necessary to determine if this CPU is 1910 // acceptable. 1911 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1912 // invalid without explaining *why*. 1913 switch (CPU) { 1914 case CK_Generic: 1915 // No processor selected! 1916 return false; 1917 1918 case CK_i386: 1919 case CK_i486: 1920 case CK_WinChipC6: 1921 case CK_WinChip2: 1922 case CK_C3: 1923 case CK_i586: 1924 case CK_Pentium: 1925 case CK_PentiumMMX: 1926 case CK_i686: 1927 case CK_PentiumPro: 1928 case CK_Pentium2: 1929 case CK_Pentium3: 1930 case CK_Pentium3M: 1931 case CK_PentiumM: 1932 case CK_Yonah: 1933 case CK_C3_2: 1934 case CK_Pentium4: 1935 case CK_Pentium4M: 1936 case CK_Prescott: 1937 case CK_K6: 1938 case CK_K6_2: 1939 case CK_K6_3: 1940 case CK_Athlon: 1941 case CK_AthlonThunderbird: 1942 case CK_Athlon4: 1943 case CK_AthlonXP: 1944 case CK_AthlonMP: 1945 case CK_Geode: 1946 // Only accept certain architectures when compiling in 32-bit mode. 1947 if (getTriple().getArch() != llvm::Triple::x86) 1948 return false; 1949 1950 // Fallthrough 1951 case CK_Nocona: 1952 case CK_Core2: 1953 case CK_Penryn: 1954 case CK_Atom: 1955 case CK_Silvermont: 1956 case CK_Corei7: 1957 case CK_Corei7AVX: 1958 case CK_CoreAVXi: 1959 case CK_CoreAVX2: 1960 case CK_KNL: 1961 case CK_Athlon64: 1962 case CK_Athlon64SSE3: 1963 case CK_AthlonFX: 1964 case CK_K8: 1965 case CK_K8SSE3: 1966 case CK_Opteron: 1967 case CK_OpteronSSE3: 1968 case CK_AMDFAM10: 1969 case CK_BTVER1: 1970 case CK_BTVER2: 1971 case CK_BDVER1: 1972 case CK_BDVER2: 1973 case CK_BDVER3: 1974 case CK_x86_64: 1975 return true; 1976 } 1977 llvm_unreachable("Unhandled CPU kind"); 1978 } 1979 1980 bool setFPMath(StringRef Name) override; 1981 1982 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1983 // We accept all non-ARM calling conventions 1984 return (CC == CC_X86ThisCall || 1985 CC == CC_X86FastCall || 1986 CC == CC_X86StdCall || 1987 CC == CC_C || 1988 CC == CC_X86Pascal || 1989 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1990 } 1991 1992 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 1993 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1994 } 1995 }; 1996 1997 bool X86TargetInfo::setFPMath(StringRef Name) { 1998 if (Name == "387") { 1999 FPMath = FP_387; 2000 return true; 2001 } 2002 if (Name == "sse") { 2003 FPMath = FP_SSE; 2004 return true; 2005 } 2006 return false; 2007 } 2008 2009 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2010 // FIXME: This *really* should not be here. 2011 2012 // X86_64 always has SSE2. 2013 if (getTriple().getArch() == llvm::Triple::x86_64) 2014 setFeatureEnabledImpl(Features, "sse2", true); 2015 2016 switch (CPU) { 2017 case CK_Generic: 2018 case CK_i386: 2019 case CK_i486: 2020 case CK_i586: 2021 case CK_Pentium: 2022 case CK_i686: 2023 case CK_PentiumPro: 2024 break; 2025 case CK_PentiumMMX: 2026 case CK_Pentium2: 2027 setFeatureEnabledImpl(Features, "mmx", true); 2028 break; 2029 case CK_Pentium3: 2030 case CK_Pentium3M: 2031 setFeatureEnabledImpl(Features, "sse", true); 2032 break; 2033 case CK_PentiumM: 2034 case CK_Pentium4: 2035 case CK_Pentium4M: 2036 case CK_x86_64: 2037 setFeatureEnabledImpl(Features, "sse2", true); 2038 break; 2039 case CK_Yonah: 2040 case CK_Prescott: 2041 case CK_Nocona: 2042 setFeatureEnabledImpl(Features, "sse3", true); 2043 setFeatureEnabledImpl(Features, "cx16", true); 2044 break; 2045 case CK_Core2: 2046 setFeatureEnabledImpl(Features, "ssse3", true); 2047 setFeatureEnabledImpl(Features, "cx16", true); 2048 break; 2049 case CK_Penryn: 2050 setFeatureEnabledImpl(Features, "sse4.1", true); 2051 setFeatureEnabledImpl(Features, "cx16", true); 2052 break; 2053 case CK_Atom: 2054 setFeatureEnabledImpl(Features, "ssse3", true); 2055 setFeatureEnabledImpl(Features, "cx16", true); 2056 break; 2057 case CK_Silvermont: 2058 setFeatureEnabledImpl(Features, "sse4.2", true); 2059 setFeatureEnabledImpl(Features, "aes", true); 2060 setFeatureEnabledImpl(Features, "cx16", true); 2061 setFeatureEnabledImpl(Features, "pclmul", true); 2062 break; 2063 case CK_Corei7: 2064 setFeatureEnabledImpl(Features, "sse4.2", true); 2065 setFeatureEnabledImpl(Features, "cx16", true); 2066 break; 2067 case CK_Corei7AVX: 2068 setFeatureEnabledImpl(Features, "avx", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 setFeatureEnabledImpl(Features, "pclmul", true); 2072 break; 2073 case CK_CoreAVXi: 2074 setFeatureEnabledImpl(Features, "avx", true); 2075 setFeatureEnabledImpl(Features, "aes", true); 2076 setFeatureEnabledImpl(Features, "pclmul", true); 2077 setFeatureEnabledImpl(Features, "rdrnd", true); 2078 setFeatureEnabledImpl(Features, "f16c", true); 2079 break; 2080 case CK_CoreAVX2: 2081 setFeatureEnabledImpl(Features, "avx2", true); 2082 setFeatureEnabledImpl(Features, "aes", true); 2083 setFeatureEnabledImpl(Features, "pclmul", true); 2084 setFeatureEnabledImpl(Features, "lzcnt", true); 2085 setFeatureEnabledImpl(Features, "rdrnd", true); 2086 setFeatureEnabledImpl(Features, "f16c", true); 2087 setFeatureEnabledImpl(Features, "bmi", true); 2088 setFeatureEnabledImpl(Features, "bmi2", true); 2089 setFeatureEnabledImpl(Features, "rtm", true); 2090 setFeatureEnabledImpl(Features, "fma", true); 2091 setFeatureEnabledImpl(Features, "cx16", true); 2092 break; 2093 case CK_KNL: 2094 setFeatureEnabledImpl(Features, "avx512f", true); 2095 setFeatureEnabledImpl(Features, "avx512cd", true); 2096 setFeatureEnabledImpl(Features, "avx512er", true); 2097 setFeatureEnabledImpl(Features, "avx512pf", true); 2098 setFeatureEnabledImpl(Features, "aes", true); 2099 setFeatureEnabledImpl(Features, "pclmul", true); 2100 setFeatureEnabledImpl(Features, "lzcnt", true); 2101 setFeatureEnabledImpl(Features, "rdrnd", true); 2102 setFeatureEnabledImpl(Features, "f16c", true); 2103 setFeatureEnabledImpl(Features, "bmi", true); 2104 setFeatureEnabledImpl(Features, "bmi2", true); 2105 setFeatureEnabledImpl(Features, "rtm", true); 2106 setFeatureEnabledImpl(Features, "fma", true); 2107 break; 2108 case CK_K6: 2109 case CK_WinChipC6: 2110 setFeatureEnabledImpl(Features, "mmx", true); 2111 break; 2112 case CK_K6_2: 2113 case CK_K6_3: 2114 case CK_WinChip2: 2115 case CK_C3: 2116 setFeatureEnabledImpl(Features, "3dnow", true); 2117 break; 2118 case CK_Athlon: 2119 case CK_AthlonThunderbird: 2120 case CK_Geode: 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_Athlon4: 2124 case CK_AthlonXP: 2125 case CK_AthlonMP: 2126 setFeatureEnabledImpl(Features, "sse", true); 2127 setFeatureEnabledImpl(Features, "3dnowa", true); 2128 break; 2129 case CK_K8: 2130 case CK_Opteron: 2131 case CK_Athlon64: 2132 case CK_AthlonFX: 2133 setFeatureEnabledImpl(Features, "sse2", true); 2134 setFeatureEnabledImpl(Features, "3dnowa", true); 2135 break; 2136 case CK_K8SSE3: 2137 case CK_OpteronSSE3: 2138 case CK_Athlon64SSE3: 2139 setFeatureEnabledImpl(Features, "sse3", true); 2140 setFeatureEnabledImpl(Features, "3dnowa", true); 2141 break; 2142 case CK_AMDFAM10: 2143 setFeatureEnabledImpl(Features, "sse3", true); 2144 setFeatureEnabledImpl(Features, "sse4a", true); 2145 setFeatureEnabledImpl(Features, "3dnowa", true); 2146 setFeatureEnabledImpl(Features, "lzcnt", true); 2147 setFeatureEnabledImpl(Features, "popcnt", true); 2148 break; 2149 case CK_BTVER1: 2150 setFeatureEnabledImpl(Features, "ssse3", true); 2151 setFeatureEnabledImpl(Features, "sse4a", true); 2152 setFeatureEnabledImpl(Features, "cx16", true); 2153 setFeatureEnabledImpl(Features, "lzcnt", true); 2154 setFeatureEnabledImpl(Features, "popcnt", true); 2155 setFeatureEnabledImpl(Features, "prfchw", true); 2156 break; 2157 case CK_BTVER2: 2158 setFeatureEnabledImpl(Features, "avx", true); 2159 setFeatureEnabledImpl(Features, "sse4a", true); 2160 setFeatureEnabledImpl(Features, "lzcnt", true); 2161 setFeatureEnabledImpl(Features, "aes", true); 2162 setFeatureEnabledImpl(Features, "pclmul", true); 2163 setFeatureEnabledImpl(Features, "prfchw", true); 2164 setFeatureEnabledImpl(Features, "bmi", true); 2165 setFeatureEnabledImpl(Features, "f16c", true); 2166 setFeatureEnabledImpl(Features, "cx16", true); 2167 break; 2168 case CK_BDVER1: 2169 setFeatureEnabledImpl(Features, "xop", true); 2170 setFeatureEnabledImpl(Features, "lzcnt", true); 2171 setFeatureEnabledImpl(Features, "aes", true); 2172 setFeatureEnabledImpl(Features, "pclmul", true); 2173 setFeatureEnabledImpl(Features, "prfchw", true); 2174 setFeatureEnabledImpl(Features, "cx16", true); 2175 break; 2176 case CK_BDVER2: 2177 case CK_BDVER3: 2178 setFeatureEnabledImpl(Features, "xop", true); 2179 setFeatureEnabledImpl(Features, "lzcnt", true); 2180 setFeatureEnabledImpl(Features, "aes", true); 2181 setFeatureEnabledImpl(Features, "pclmul", true); 2182 setFeatureEnabledImpl(Features, "prfchw", true); 2183 setFeatureEnabledImpl(Features, "bmi", true); 2184 setFeatureEnabledImpl(Features, "fma", true); 2185 setFeatureEnabledImpl(Features, "f16c", true); 2186 setFeatureEnabledImpl(Features, "tbm", true); 2187 setFeatureEnabledImpl(Features, "cx16", true); 2188 break; 2189 case CK_C3_2: 2190 setFeatureEnabledImpl(Features, "sse", true); 2191 break; 2192 } 2193 } 2194 2195 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2196 X86SSEEnum Level, bool Enabled) { 2197 if (Enabled) { 2198 switch (Level) { 2199 case AVX512F: 2200 Features["avx512f"] = true; 2201 case AVX2: 2202 Features["avx2"] = true; 2203 case AVX: 2204 Features["avx"] = true; 2205 case SSE42: 2206 Features["sse4.2"] = true; 2207 case SSE41: 2208 Features["sse4.1"] = true; 2209 case SSSE3: 2210 Features["ssse3"] = true; 2211 case SSE3: 2212 Features["sse3"] = true; 2213 case SSE2: 2214 Features["sse2"] = true; 2215 case SSE1: 2216 Features["sse"] = true; 2217 case NoSSE: 2218 break; 2219 } 2220 return; 2221 } 2222 2223 switch (Level) { 2224 case NoSSE: 2225 case SSE1: 2226 Features["sse"] = false; 2227 case SSE2: 2228 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2229 Features["sha"] = false; 2230 case SSE3: 2231 Features["sse3"] = false; 2232 setXOPLevel(Features, NoXOP, false); 2233 case SSSE3: 2234 Features["ssse3"] = false; 2235 case SSE41: 2236 Features["sse4.1"] = false; 2237 case SSE42: 2238 Features["sse4.2"] = false; 2239 case AVX: 2240 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2241 setXOPLevel(Features, FMA4, false); 2242 case AVX2: 2243 Features["avx2"] = false; 2244 case AVX512F: 2245 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2246 Features["avx512pf"] = false; 2247 } 2248 } 2249 2250 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2251 MMX3DNowEnum Level, bool Enabled) { 2252 if (Enabled) { 2253 switch (Level) { 2254 case AMD3DNowAthlon: 2255 Features["3dnowa"] = true; 2256 case AMD3DNow: 2257 Features["3dnow"] = true; 2258 case MMX: 2259 Features["mmx"] = true; 2260 case NoMMX3DNow: 2261 break; 2262 } 2263 return; 2264 } 2265 2266 switch (Level) { 2267 case NoMMX3DNow: 2268 case MMX: 2269 Features["mmx"] = false; 2270 case AMD3DNow: 2271 Features["3dnow"] = false; 2272 case AMD3DNowAthlon: 2273 Features["3dnowa"] = false; 2274 } 2275 } 2276 2277 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2278 bool Enabled) { 2279 if (Enabled) { 2280 switch (Level) { 2281 case XOP: 2282 Features["xop"] = true; 2283 case FMA4: 2284 Features["fma4"] = true; 2285 setSSELevel(Features, AVX, true); 2286 case SSE4A: 2287 Features["sse4a"] = true; 2288 setSSELevel(Features, SSE3, true); 2289 case NoXOP: 2290 break; 2291 } 2292 return; 2293 } 2294 2295 switch (Level) { 2296 case NoXOP: 2297 case SSE4A: 2298 Features["sse4a"] = false; 2299 case FMA4: 2300 Features["fma4"] = false; 2301 case XOP: 2302 Features["xop"] = false; 2303 } 2304 } 2305 2306 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2307 StringRef Name, bool Enabled) { 2308 // FIXME: This *really* should not be here. We need some way of translating 2309 // options into llvm subtarget features. 2310 if (Name == "sse4") 2311 Name = "sse4.2"; 2312 2313 Features[Name] = Enabled; 2314 2315 if (Name == "mmx") { 2316 setMMXLevel(Features, MMX, Enabled); 2317 } else if (Name == "sse") { 2318 setSSELevel(Features, SSE1, Enabled); 2319 } else if (Name == "sse2") { 2320 setSSELevel(Features, SSE2, Enabled); 2321 } else if (Name == "sse3") { 2322 setSSELevel(Features, SSE3, Enabled); 2323 } else if (Name == "ssse3") { 2324 setSSELevel(Features, SSSE3, Enabled); 2325 } else if (Name == "sse4.2") { 2326 setSSELevel(Features, SSE42, Enabled); 2327 } else if (Name == "sse4.1") { 2328 setSSELevel(Features, SSE41, Enabled); 2329 } else if (Name == "3dnow") { 2330 setMMXLevel(Features, AMD3DNow, Enabled); 2331 } else if (Name == "3dnowa") { 2332 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2333 } else if (Name == "aes") { 2334 if (Enabled) 2335 setSSELevel(Features, SSE2, Enabled); 2336 } else if (Name == "pclmul") { 2337 if (Enabled) 2338 setSSELevel(Features, SSE2, Enabled); 2339 } else if (Name == "avx") { 2340 setSSELevel(Features, AVX, Enabled); 2341 } else if (Name == "avx2") { 2342 setSSELevel(Features, AVX2, Enabled); 2343 } else if (Name == "avx512f") { 2344 setSSELevel(Features, AVX512F, Enabled); 2345 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2346 if (Enabled) 2347 setSSELevel(Features, AVX512F, Enabled); 2348 } else if (Name == "fma") { 2349 if (Enabled) 2350 setSSELevel(Features, AVX, Enabled); 2351 } else if (Name == "fma4") { 2352 setXOPLevel(Features, FMA4, Enabled); 2353 } else if (Name == "xop") { 2354 setXOPLevel(Features, XOP, Enabled); 2355 } else if (Name == "sse4a") { 2356 setXOPLevel(Features, SSE4A, Enabled); 2357 } else if (Name == "f16c") { 2358 if (Enabled) 2359 setSSELevel(Features, AVX, Enabled); 2360 } else if (Name == "sha") { 2361 if (Enabled) 2362 setSSELevel(Features, SSE2, Enabled); 2363 } 2364 } 2365 2366 /// handleTargetFeatures - Perform initialization based on the user 2367 /// configured set of features. 2368 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2369 DiagnosticsEngine &Diags) { 2370 // Remember the maximum enabled sselevel. 2371 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2372 // Ignore disabled features. 2373 if (Features[i][0] == '-') 2374 continue; 2375 2376 StringRef Feature = StringRef(Features[i]).substr(1); 2377 2378 if (Feature == "aes") { 2379 HasAES = true; 2380 continue; 2381 } 2382 2383 if (Feature == "pclmul") { 2384 HasPCLMUL = true; 2385 continue; 2386 } 2387 2388 if (Feature == "lzcnt") { 2389 HasLZCNT = true; 2390 continue; 2391 } 2392 2393 if (Feature == "rdrnd") { 2394 HasRDRND = true; 2395 continue; 2396 } 2397 2398 if (Feature == "bmi") { 2399 HasBMI = true; 2400 continue; 2401 } 2402 2403 if (Feature == "bmi2") { 2404 HasBMI2 = true; 2405 continue; 2406 } 2407 2408 if (Feature == "popcnt") { 2409 HasPOPCNT = true; 2410 continue; 2411 } 2412 2413 if (Feature == "rtm") { 2414 HasRTM = true; 2415 continue; 2416 } 2417 2418 if (Feature == "prfchw") { 2419 HasPRFCHW = true; 2420 continue; 2421 } 2422 2423 if (Feature == "rdseed") { 2424 HasRDSEED = true; 2425 continue; 2426 } 2427 2428 if (Feature == "tbm") { 2429 HasTBM = true; 2430 continue; 2431 } 2432 2433 if (Feature == "fma") { 2434 HasFMA = true; 2435 continue; 2436 } 2437 2438 if (Feature == "f16c") { 2439 HasF16C = true; 2440 continue; 2441 } 2442 2443 if (Feature == "avx512cd") { 2444 HasAVX512CD = true; 2445 continue; 2446 } 2447 2448 if (Feature == "avx512er") { 2449 HasAVX512ER = true; 2450 continue; 2451 } 2452 2453 if (Feature == "avx512pf") { 2454 HasAVX512PF = true; 2455 continue; 2456 } 2457 2458 if (Feature == "sha") { 2459 HasSHA = true; 2460 continue; 2461 } 2462 2463 if (Feature == "cx16") { 2464 HasCX16 = true; 2465 continue; 2466 } 2467 2468 assert(Features[i][0] == '+' && "Invalid target feature!"); 2469 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2470 .Case("avx512f", AVX512F) 2471 .Case("avx2", AVX2) 2472 .Case("avx", AVX) 2473 .Case("sse4.2", SSE42) 2474 .Case("sse4.1", SSE41) 2475 .Case("ssse3", SSSE3) 2476 .Case("sse3", SSE3) 2477 .Case("sse2", SSE2) 2478 .Case("sse", SSE1) 2479 .Default(NoSSE); 2480 SSELevel = std::max(SSELevel, Level); 2481 2482 MMX3DNowEnum ThreeDNowLevel = 2483 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2484 .Case("3dnowa", AMD3DNowAthlon) 2485 .Case("3dnow", AMD3DNow) 2486 .Case("mmx", MMX) 2487 .Default(NoMMX3DNow); 2488 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2489 2490 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2491 .Case("xop", XOP) 2492 .Case("fma4", FMA4) 2493 .Case("sse4a", SSE4A) 2494 .Default(NoXOP); 2495 XOPLevel = std::max(XOPLevel, XLevel); 2496 } 2497 2498 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2499 // Can't do this earlier because we need to be able to explicitly enable 2500 // popcnt and still disable sse4.2. 2501 if (!HasPOPCNT && SSELevel >= SSE42 && 2502 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2503 HasPOPCNT = true; 2504 Features.push_back("+popcnt"); 2505 } 2506 2507 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2508 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2509 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2510 HasPRFCHW = true; 2511 Features.push_back("+prfchw"); 2512 } 2513 2514 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2515 // matches the selected sse level. 2516 if (FPMath == FP_SSE && SSELevel < SSE1) { 2517 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2518 return false; 2519 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2520 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2521 return false; 2522 } 2523 2524 // Don't tell the backend if we're turning off mmx; it will end up disabling 2525 // SSE, which we don't want. 2526 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2527 // then enable MMX. 2528 std::vector<std::string>::iterator it; 2529 it = std::find(Features.begin(), Features.end(), "-mmx"); 2530 if (it != Features.end()) 2531 Features.erase(it); 2532 else if (SSELevel > NoSSE) 2533 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2534 return true; 2535 } 2536 2537 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2538 /// definitions for this particular subtarget. 2539 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2540 MacroBuilder &Builder) const { 2541 // Target identification. 2542 if (getTriple().getArch() == llvm::Triple::x86_64) { 2543 Builder.defineMacro("__amd64__"); 2544 Builder.defineMacro("__amd64"); 2545 Builder.defineMacro("__x86_64"); 2546 Builder.defineMacro("__x86_64__"); 2547 } else { 2548 DefineStd(Builder, "i386", Opts); 2549 } 2550 2551 // Subtarget options. 2552 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2553 // truly should be based on -mtune options. 2554 switch (CPU) { 2555 case CK_Generic: 2556 break; 2557 case CK_i386: 2558 // The rest are coming from the i386 define above. 2559 Builder.defineMacro("__tune_i386__"); 2560 break; 2561 case CK_i486: 2562 case CK_WinChipC6: 2563 case CK_WinChip2: 2564 case CK_C3: 2565 defineCPUMacros(Builder, "i486"); 2566 break; 2567 case CK_PentiumMMX: 2568 Builder.defineMacro("__pentium_mmx__"); 2569 Builder.defineMacro("__tune_pentium_mmx__"); 2570 // Fallthrough 2571 case CK_i586: 2572 case CK_Pentium: 2573 defineCPUMacros(Builder, "i586"); 2574 defineCPUMacros(Builder, "pentium"); 2575 break; 2576 case CK_Pentium3: 2577 case CK_Pentium3M: 2578 case CK_PentiumM: 2579 Builder.defineMacro("__tune_pentium3__"); 2580 // Fallthrough 2581 case CK_Pentium2: 2582 case CK_C3_2: 2583 Builder.defineMacro("__tune_pentium2__"); 2584 // Fallthrough 2585 case CK_PentiumPro: 2586 Builder.defineMacro("__tune_i686__"); 2587 Builder.defineMacro("__tune_pentiumpro__"); 2588 // Fallthrough 2589 case CK_i686: 2590 Builder.defineMacro("__i686"); 2591 Builder.defineMacro("__i686__"); 2592 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2593 Builder.defineMacro("__pentiumpro"); 2594 Builder.defineMacro("__pentiumpro__"); 2595 break; 2596 case CK_Pentium4: 2597 case CK_Pentium4M: 2598 defineCPUMacros(Builder, "pentium4"); 2599 break; 2600 case CK_Yonah: 2601 case CK_Prescott: 2602 case CK_Nocona: 2603 defineCPUMacros(Builder, "nocona"); 2604 break; 2605 case CK_Core2: 2606 case CK_Penryn: 2607 defineCPUMacros(Builder, "core2"); 2608 break; 2609 case CK_Atom: 2610 defineCPUMacros(Builder, "atom"); 2611 break; 2612 case CK_Silvermont: 2613 defineCPUMacros(Builder, "slm"); 2614 break; 2615 case CK_Corei7: 2616 case CK_Corei7AVX: 2617 case CK_CoreAVXi: 2618 case CK_CoreAVX2: 2619 defineCPUMacros(Builder, "corei7"); 2620 break; 2621 case CK_KNL: 2622 defineCPUMacros(Builder, "knl"); 2623 break; 2624 case CK_K6_2: 2625 Builder.defineMacro("__k6_2__"); 2626 Builder.defineMacro("__tune_k6_2__"); 2627 // Fallthrough 2628 case CK_K6_3: 2629 if (CPU != CK_K6_2) { // In case of fallthrough 2630 // FIXME: GCC may be enabling these in cases where some other k6 2631 // architecture is specified but -m3dnow is explicitly provided. The 2632 // exact semantics need to be determined and emulated here. 2633 Builder.defineMacro("__k6_3__"); 2634 Builder.defineMacro("__tune_k6_3__"); 2635 } 2636 // Fallthrough 2637 case CK_K6: 2638 defineCPUMacros(Builder, "k6"); 2639 break; 2640 case CK_Athlon: 2641 case CK_AthlonThunderbird: 2642 case CK_Athlon4: 2643 case CK_AthlonXP: 2644 case CK_AthlonMP: 2645 defineCPUMacros(Builder, "athlon"); 2646 if (SSELevel != NoSSE) { 2647 Builder.defineMacro("__athlon_sse__"); 2648 Builder.defineMacro("__tune_athlon_sse__"); 2649 } 2650 break; 2651 case CK_K8: 2652 case CK_K8SSE3: 2653 case CK_x86_64: 2654 case CK_Opteron: 2655 case CK_OpteronSSE3: 2656 case CK_Athlon64: 2657 case CK_Athlon64SSE3: 2658 case CK_AthlonFX: 2659 defineCPUMacros(Builder, "k8"); 2660 break; 2661 case CK_AMDFAM10: 2662 defineCPUMacros(Builder, "amdfam10"); 2663 break; 2664 case CK_BTVER1: 2665 defineCPUMacros(Builder, "btver1"); 2666 break; 2667 case CK_BTVER2: 2668 defineCPUMacros(Builder, "btver2"); 2669 break; 2670 case CK_BDVER1: 2671 defineCPUMacros(Builder, "bdver1"); 2672 break; 2673 case CK_BDVER2: 2674 defineCPUMacros(Builder, "bdver2"); 2675 break; 2676 case CK_BDVER3: 2677 defineCPUMacros(Builder, "bdver3"); 2678 break; 2679 case CK_Geode: 2680 defineCPUMacros(Builder, "geode"); 2681 break; 2682 } 2683 2684 // Target properties. 2685 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2686 2687 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2688 // functions in glibc header files that use FP Stack inline asm which the 2689 // backend can't deal with (PR879). 2690 Builder.defineMacro("__NO_MATH_INLINES"); 2691 2692 if (HasAES) 2693 Builder.defineMacro("__AES__"); 2694 2695 if (HasPCLMUL) 2696 Builder.defineMacro("__PCLMUL__"); 2697 2698 if (HasLZCNT) 2699 Builder.defineMacro("__LZCNT__"); 2700 2701 if (HasRDRND) 2702 Builder.defineMacro("__RDRND__"); 2703 2704 if (HasBMI) 2705 Builder.defineMacro("__BMI__"); 2706 2707 if (HasBMI2) 2708 Builder.defineMacro("__BMI2__"); 2709 2710 if (HasPOPCNT) 2711 Builder.defineMacro("__POPCNT__"); 2712 2713 if (HasRTM) 2714 Builder.defineMacro("__RTM__"); 2715 2716 if (HasPRFCHW) 2717 Builder.defineMacro("__PRFCHW__"); 2718 2719 if (HasRDSEED) 2720 Builder.defineMacro("__RDSEED__"); 2721 2722 if (HasTBM) 2723 Builder.defineMacro("__TBM__"); 2724 2725 switch (XOPLevel) { 2726 case XOP: 2727 Builder.defineMacro("__XOP__"); 2728 case FMA4: 2729 Builder.defineMacro("__FMA4__"); 2730 case SSE4A: 2731 Builder.defineMacro("__SSE4A__"); 2732 case NoXOP: 2733 break; 2734 } 2735 2736 if (HasFMA) 2737 Builder.defineMacro("__FMA__"); 2738 2739 if (HasF16C) 2740 Builder.defineMacro("__F16C__"); 2741 2742 if (HasAVX512CD) 2743 Builder.defineMacro("__AVX512CD__"); 2744 if (HasAVX512ER) 2745 Builder.defineMacro("__AVX512ER__"); 2746 if (HasAVX512PF) 2747 Builder.defineMacro("__AVX512PF__"); 2748 2749 if (HasSHA) 2750 Builder.defineMacro("__SHA__"); 2751 2752 if (HasCX16) 2753 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2754 2755 // Each case falls through to the previous one here. 2756 switch (SSELevel) { 2757 case AVX512F: 2758 Builder.defineMacro("__AVX512F__"); 2759 case AVX2: 2760 Builder.defineMacro("__AVX2__"); 2761 case AVX: 2762 Builder.defineMacro("__AVX__"); 2763 case SSE42: 2764 Builder.defineMacro("__SSE4_2__"); 2765 case SSE41: 2766 Builder.defineMacro("__SSE4_1__"); 2767 case SSSE3: 2768 Builder.defineMacro("__SSSE3__"); 2769 case SSE3: 2770 Builder.defineMacro("__SSE3__"); 2771 case SSE2: 2772 Builder.defineMacro("__SSE2__"); 2773 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2774 case SSE1: 2775 Builder.defineMacro("__SSE__"); 2776 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2777 case NoSSE: 2778 break; 2779 } 2780 2781 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2782 switch (SSELevel) { 2783 case AVX512F: 2784 case AVX2: 2785 case AVX: 2786 case SSE42: 2787 case SSE41: 2788 case SSSE3: 2789 case SSE3: 2790 case SSE2: 2791 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2792 break; 2793 case SSE1: 2794 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2795 break; 2796 default: 2797 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2798 } 2799 } 2800 2801 // Each case falls through to the previous one here. 2802 switch (MMX3DNowLevel) { 2803 case AMD3DNowAthlon: 2804 Builder.defineMacro("__3dNOW_A__"); 2805 case AMD3DNow: 2806 Builder.defineMacro("__3dNOW__"); 2807 case MMX: 2808 Builder.defineMacro("__MMX__"); 2809 case NoMMX3DNow: 2810 break; 2811 } 2812 2813 if (CPU >= CK_i486) { 2814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2815 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2817 } 2818 if (CPU >= CK_i586) 2819 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2820 } 2821 2822 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2823 return llvm::StringSwitch<bool>(Feature) 2824 .Case("aes", HasAES) 2825 .Case("avx", SSELevel >= AVX) 2826 .Case("avx2", SSELevel >= AVX2) 2827 .Case("avx512f", SSELevel >= AVX512F) 2828 .Case("avx512cd", HasAVX512CD) 2829 .Case("avx512er", HasAVX512ER) 2830 .Case("avx512pf", HasAVX512PF) 2831 .Case("bmi", HasBMI) 2832 .Case("bmi2", HasBMI2) 2833 .Case("cx16", HasCX16) 2834 .Case("f16c", HasF16C) 2835 .Case("fma", HasFMA) 2836 .Case("fma4", XOPLevel >= FMA4) 2837 .Case("tbm", HasTBM) 2838 .Case("lzcnt", HasLZCNT) 2839 .Case("rdrnd", HasRDRND) 2840 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2841 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2842 .Case("mmx", MMX3DNowLevel >= MMX) 2843 .Case("pclmul", HasPCLMUL) 2844 .Case("popcnt", HasPOPCNT) 2845 .Case("rtm", HasRTM) 2846 .Case("prfchw", HasPRFCHW) 2847 .Case("rdseed", HasRDSEED) 2848 .Case("sha", HasSHA) 2849 .Case("sse", SSELevel >= SSE1) 2850 .Case("sse2", SSELevel >= SSE2) 2851 .Case("sse3", SSELevel >= SSE3) 2852 .Case("ssse3", SSELevel >= SSSE3) 2853 .Case("sse4.1", SSELevel >= SSE41) 2854 .Case("sse4.2", SSELevel >= SSE42) 2855 .Case("sse4a", XOPLevel >= SSE4A) 2856 .Case("x86", true) 2857 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2858 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2859 .Case("xop", XOPLevel >= XOP) 2860 .Default(false); 2861 } 2862 2863 bool 2864 X86TargetInfo::validateAsmConstraint(const char *&Name, 2865 TargetInfo::ConstraintInfo &Info) const { 2866 switch (*Name) { 2867 default: return false; 2868 case 'Y': // first letter of a pair: 2869 switch (*(Name+1)) { 2870 default: return false; 2871 case '0': // First SSE register. 2872 case 't': // Any SSE register, when SSE2 is enabled. 2873 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2874 case 'm': // any MMX register, when inter-unit moves enabled. 2875 break; // falls through to setAllowsRegister. 2876 } 2877 case 'a': // eax. 2878 case 'b': // ebx. 2879 case 'c': // ecx. 2880 case 'd': // edx. 2881 case 'S': // esi. 2882 case 'D': // edi. 2883 case 'A': // edx:eax. 2884 case 'f': // any x87 floating point stack register. 2885 case 't': // top of floating point stack. 2886 case 'u': // second from top of floating point stack. 2887 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2888 case 'y': // Any MMX register. 2889 case 'x': // Any SSE register. 2890 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2891 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2892 case 'l': // "Index" registers: any general register that can be used as an 2893 // index in a base+index memory access. 2894 Info.setAllowsRegister(); 2895 return true; 2896 case 'C': // SSE floating point constant. 2897 case 'G': // x87 floating point constant. 2898 case 'e': // 32-bit signed integer constant for use with zero-extending 2899 // x86_64 instructions. 2900 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2901 // x86_64 instructions. 2902 return true; 2903 } 2904 } 2905 2906 2907 std::string 2908 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2909 switch (*Constraint) { 2910 case 'a': return std::string("{ax}"); 2911 case 'b': return std::string("{bx}"); 2912 case 'c': return std::string("{cx}"); 2913 case 'd': return std::string("{dx}"); 2914 case 'S': return std::string("{si}"); 2915 case 'D': return std::string("{di}"); 2916 case 'p': // address 2917 return std::string("im"); 2918 case 't': // top of floating point stack. 2919 return std::string("{st}"); 2920 case 'u': // second from top of floating point stack. 2921 return std::string("{st(1)}"); // second from top of floating point stack. 2922 default: 2923 return std::string(1, *Constraint); 2924 } 2925 } 2926 } // end anonymous namespace 2927 2928 namespace { 2929 // X86-32 generic target 2930 class X86_32TargetInfo : public X86TargetInfo { 2931 public: 2932 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2933 DoubleAlign = LongLongAlign = 32; 2934 LongDoubleWidth = 96; 2935 LongDoubleAlign = 32; 2936 SuitableAlign = 128; 2937 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2938 SizeType = UnsignedInt; 2939 PtrDiffType = SignedInt; 2940 IntPtrType = SignedInt; 2941 RegParmMax = 3; 2942 2943 // Use fpret for all types. 2944 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2945 (1 << TargetInfo::Double) | 2946 (1 << TargetInfo::LongDouble)); 2947 2948 // x86-32 has atomics up to 8 bytes 2949 // FIXME: Check that we actually have cmpxchg8b before setting 2950 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2951 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2952 } 2953 BuiltinVaListKind getBuiltinVaListKind() const override { 2954 return TargetInfo::CharPtrBuiltinVaList; 2955 } 2956 2957 int getEHDataRegisterNumber(unsigned RegNo) const override { 2958 if (RegNo == 0) return 0; 2959 if (RegNo == 1) return 2; 2960 return -1; 2961 } 2962 bool validateInputSize(StringRef Constraint, 2963 unsigned Size) const override { 2964 switch (Constraint[0]) { 2965 default: break; 2966 case 'a': 2967 case 'b': 2968 case 'c': 2969 case 'd': 2970 return Size <= 32; 2971 } 2972 2973 return true; 2974 } 2975 }; 2976 } // end anonymous namespace 2977 2978 namespace { 2979 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2980 public: 2981 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2982 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2983 2984 unsigned getFloatEvalMethod() const override { 2985 unsigned Major, Minor, Micro; 2986 getTriple().getOSVersion(Major, Minor, Micro); 2987 // New NetBSD uses the default rounding mode. 2988 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2989 return X86_32TargetInfo::getFloatEvalMethod(); 2990 // NetBSD before 6.99.26 defaults to "double" rounding. 2991 return 1; 2992 } 2993 }; 2994 } // end anonymous namespace 2995 2996 namespace { 2997 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2998 public: 2999 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3000 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3001 SizeType = UnsignedLong; 3002 IntPtrType = SignedLong; 3003 PtrDiffType = SignedLong; 3004 } 3005 }; 3006 } // end anonymous namespace 3007 3008 namespace { 3009 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3010 public: 3011 BitrigI386TargetInfo(const llvm::Triple &Triple) 3012 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3013 SizeType = UnsignedLong; 3014 IntPtrType = SignedLong; 3015 PtrDiffType = SignedLong; 3016 } 3017 }; 3018 } // end anonymous namespace 3019 3020 namespace { 3021 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3022 public: 3023 DarwinI386TargetInfo(const llvm::Triple &Triple) 3024 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3025 LongDoubleWidth = 128; 3026 LongDoubleAlign = 128; 3027 SuitableAlign = 128; 3028 MaxVectorAlign = 256; 3029 SizeType = UnsignedLong; 3030 IntPtrType = SignedLong; 3031 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3032 HasAlignMac68kSupport = true; 3033 } 3034 3035 }; 3036 } // end anonymous namespace 3037 3038 namespace { 3039 // x86-32 Windows target 3040 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3041 public: 3042 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3043 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3044 TLSSupported = false; 3045 WCharType = UnsignedShort; 3046 DoubleAlign = LongLongAlign = 64; 3047 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3048 } 3049 void getTargetDefines(const LangOptions &Opts, 3050 MacroBuilder &Builder) const override { 3051 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3052 } 3053 }; 3054 } // end anonymous namespace 3055 3056 namespace { 3057 3058 // x86-32 Windows Visual Studio target 3059 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3060 public: 3061 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3062 : WindowsX86_32TargetInfo(Triple) { 3063 LongDoubleWidth = LongDoubleAlign = 64; 3064 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3065 } 3066 void getTargetDefines(const LangOptions &Opts, 3067 MacroBuilder &Builder) const override { 3068 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3069 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3070 // The value of the following reflects processor type. 3071 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3072 // We lost the original triple, so we use the default. 3073 Builder.defineMacro("_M_IX86", "600"); 3074 } 3075 }; 3076 } // end anonymous namespace 3077 3078 namespace { 3079 // x86-32 MinGW target 3080 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3081 public: 3082 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3083 : WindowsX86_32TargetInfo(Triple) {} 3084 void getTargetDefines(const LangOptions &Opts, 3085 MacroBuilder &Builder) const override { 3086 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3087 DefineStd(Builder, "WIN32", Opts); 3088 DefineStd(Builder, "WINNT", Opts); 3089 Builder.defineMacro("_X86_"); 3090 Builder.defineMacro("__MSVCRT__"); 3091 Builder.defineMacro("__MINGW32__"); 3092 3093 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3094 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3095 if (Opts.MicrosoftExt) 3096 // Provide "as-is" __declspec. 3097 Builder.defineMacro("__declspec", "__declspec"); 3098 else 3099 // Provide alias of __attribute__ like mingw32-gcc. 3100 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3101 } 3102 }; 3103 } // end anonymous namespace 3104 3105 namespace { 3106 // x86-32 Cygwin target 3107 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3108 public: 3109 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3110 : X86_32TargetInfo(Triple) { 3111 TLSSupported = false; 3112 WCharType = UnsignedShort; 3113 DoubleAlign = LongLongAlign = 64; 3114 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3115 } 3116 void getTargetDefines(const LangOptions &Opts, 3117 MacroBuilder &Builder) const override { 3118 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3119 Builder.defineMacro("_X86_"); 3120 Builder.defineMacro("__CYGWIN__"); 3121 Builder.defineMacro("__CYGWIN32__"); 3122 DefineStd(Builder, "unix", Opts); 3123 if (Opts.CPlusPlus) 3124 Builder.defineMacro("_GNU_SOURCE"); 3125 } 3126 }; 3127 } // end anonymous namespace 3128 3129 namespace { 3130 // x86-32 Haiku target 3131 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3132 public: 3133 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3134 SizeType = UnsignedLong; 3135 IntPtrType = SignedLong; 3136 PtrDiffType = SignedLong; 3137 ProcessIDType = SignedLong; 3138 this->UserLabelPrefix = ""; 3139 this->TLSSupported = false; 3140 } 3141 void getTargetDefines(const LangOptions &Opts, 3142 MacroBuilder &Builder) const override { 3143 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3144 Builder.defineMacro("__INTEL__"); 3145 Builder.defineMacro("__HAIKU__"); 3146 } 3147 }; 3148 } // end anonymous namespace 3149 3150 // RTEMS Target 3151 template<typename Target> 3152 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3153 protected: 3154 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3155 MacroBuilder &Builder) const override { 3156 // RTEMS defines; list based off of gcc output 3157 3158 Builder.defineMacro("__rtems__"); 3159 Builder.defineMacro("__ELF__"); 3160 } 3161 3162 public: 3163 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3164 this->UserLabelPrefix = ""; 3165 3166 switch (Triple.getArch()) { 3167 default: 3168 case llvm::Triple::x86: 3169 // this->MCountName = ".mcount"; 3170 break; 3171 case llvm::Triple::mips: 3172 case llvm::Triple::mipsel: 3173 case llvm::Triple::ppc: 3174 case llvm::Triple::ppc64: 3175 case llvm::Triple::ppc64le: 3176 // this->MCountName = "_mcount"; 3177 break; 3178 case llvm::Triple::arm: 3179 // this->MCountName = "__mcount"; 3180 break; 3181 } 3182 } 3183 }; 3184 3185 namespace { 3186 // x86-32 RTEMS target 3187 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3188 public: 3189 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3190 SizeType = UnsignedLong; 3191 IntPtrType = SignedLong; 3192 PtrDiffType = SignedLong; 3193 this->UserLabelPrefix = ""; 3194 } 3195 void getTargetDefines(const LangOptions &Opts, 3196 MacroBuilder &Builder) const override { 3197 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3198 Builder.defineMacro("__INTEL__"); 3199 Builder.defineMacro("__rtems__"); 3200 } 3201 }; 3202 } // end anonymous namespace 3203 3204 namespace { 3205 // x86-64 generic target 3206 class X86_64TargetInfo : public X86TargetInfo { 3207 public: 3208 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3209 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3210 LongDoubleWidth = 128; 3211 LongDoubleAlign = 128; 3212 LargeArrayMinWidth = 128; 3213 LargeArrayAlign = 128; 3214 SuitableAlign = 128; 3215 IntMaxType = SignedLong; 3216 UIntMaxType = UnsignedLong; 3217 Int64Type = SignedLong; 3218 RegParmMax = 6; 3219 3220 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3221 3222 // Use fpret only for long double. 3223 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3224 3225 // Use fp2ret for _Complex long double. 3226 ComplexLongDoubleUsesFP2Ret = true; 3227 3228 // x86-64 has atomics up to 16 bytes. 3229 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3230 // on CPUs with cmpxchg16b 3231 MaxAtomicPromoteWidth = 128; 3232 MaxAtomicInlineWidth = 64; 3233 } 3234 BuiltinVaListKind getBuiltinVaListKind() const override { 3235 return TargetInfo::X86_64ABIBuiltinVaList; 3236 } 3237 3238 int getEHDataRegisterNumber(unsigned RegNo) const override { 3239 if (RegNo == 0) return 0; 3240 if (RegNo == 1) return 1; 3241 return -1; 3242 } 3243 3244 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3245 return (CC == CC_C || 3246 CC == CC_IntelOclBicc || 3247 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3248 } 3249 3250 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3251 return CC_C; 3252 } 3253 3254 }; 3255 } // end anonymous namespace 3256 3257 namespace { 3258 // x86-64 Windows target 3259 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3260 public: 3261 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3262 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3263 TLSSupported = false; 3264 WCharType = UnsignedShort; 3265 LongWidth = LongAlign = 32; 3266 DoubleAlign = LongLongAlign = 64; 3267 IntMaxType = SignedLongLong; 3268 UIntMaxType = UnsignedLongLong; 3269 Int64Type = SignedLongLong; 3270 SizeType = UnsignedLongLong; 3271 PtrDiffType = SignedLongLong; 3272 IntPtrType = SignedLongLong; 3273 this->UserLabelPrefix = ""; 3274 } 3275 void getTargetDefines(const LangOptions &Opts, 3276 MacroBuilder &Builder) const override { 3277 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3278 Builder.defineMacro("_WIN64"); 3279 } 3280 BuiltinVaListKind getBuiltinVaListKind() const override { 3281 return TargetInfo::CharPtrBuiltinVaList; 3282 } 3283 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3284 return (CC == CC_C || 3285 CC == CC_IntelOclBicc || 3286 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3287 } 3288 }; 3289 } // end anonymous namespace 3290 3291 namespace { 3292 // x86-64 Windows Visual Studio target 3293 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3294 public: 3295 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3296 : WindowsX86_64TargetInfo(Triple) { 3297 LongDoubleWidth = LongDoubleAlign = 64; 3298 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3299 } 3300 void getTargetDefines(const LangOptions &Opts, 3301 MacroBuilder &Builder) const override { 3302 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3303 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3304 Builder.defineMacro("_M_X64"); 3305 Builder.defineMacro("_M_AMD64"); 3306 } 3307 }; 3308 } // end anonymous namespace 3309 3310 namespace { 3311 // x86-64 MinGW target 3312 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3313 public: 3314 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3315 : WindowsX86_64TargetInfo(Triple) {} 3316 void getTargetDefines(const LangOptions &Opts, 3317 MacroBuilder &Builder) const override { 3318 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3319 DefineStd(Builder, "WIN64", Opts); 3320 Builder.defineMacro("__MSVCRT__"); 3321 Builder.defineMacro("__MINGW32__"); 3322 Builder.defineMacro("__MINGW64__"); 3323 3324 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3325 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3326 if (Opts.MicrosoftExt) 3327 // Provide "as-is" __declspec. 3328 Builder.defineMacro("__declspec", "__declspec"); 3329 else 3330 // Provide alias of __attribute__ like mingw32-gcc. 3331 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3338 public: 3339 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3340 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3341 Int64Type = SignedLongLong; 3342 MaxVectorAlign = 256; 3343 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3344 } 3345 }; 3346 } // end anonymous namespace 3347 3348 namespace { 3349 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3350 public: 3351 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3352 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3353 IntMaxType = SignedLongLong; 3354 UIntMaxType = UnsignedLongLong; 3355 Int64Type = SignedLongLong; 3356 } 3357 }; 3358 } // end anonymous namespace 3359 3360 namespace { 3361 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3362 public: 3363 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3364 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3365 IntMaxType = SignedLongLong; 3366 UIntMaxType = UnsignedLongLong; 3367 Int64Type = SignedLongLong; 3368 } 3369 }; 3370 } 3371 3372 namespace { 3373 class AArch64TargetInfo : public TargetInfo { 3374 virtual void setDescriptionString() = 0; 3375 static const char * const GCCRegNames[]; 3376 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3377 3378 enum FPUModeEnum { 3379 FPUMode, 3380 NeonMode 3381 }; 3382 3383 unsigned FPU; 3384 unsigned Crypto; 3385 static const Builtin::Info BuiltinInfo[]; 3386 3387 public: 3388 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3389 LongWidth = LongAlign = 64; 3390 LongDoubleWidth = LongDoubleAlign = 128; 3391 PointerWidth = PointerAlign = 64; 3392 SuitableAlign = 128; 3393 3394 WCharType = UnsignedInt; 3395 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3396 WCharType = SignedInt; 3397 Int64Type = SignedLongLong; 3398 IntMaxType = SignedLongLong; 3399 UIntMaxType = UnsignedLongLong; 3400 } else { 3401 WCharType = UnsignedInt; 3402 Int64Type = SignedLong; 3403 IntMaxType = SignedLong; 3404 UIntMaxType = UnsignedLong; 3405 } 3406 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3407 3408 // AArch64 backend supports 64-bit operations at the moment. In principle 3409 // 128-bit is possible if register-pairs are used. 3410 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3411 3412 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3413 } 3414 void getTargetDefines(const LangOptions &Opts, 3415 MacroBuilder &Builder) const override { 3416 // GCC defines theses currently 3417 Builder.defineMacro("__aarch64__"); 3418 3419 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3420 Builder.defineMacro("__ARM_ACLE", "200"); 3421 Builder.defineMacro("__ARM_ARCH", "8"); 3422 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3423 3424 Builder.defineMacro("__ARM_64BIT_STATE"); 3425 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3426 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3427 3428 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3429 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3430 Builder.defineMacro("__ARM_FEATURE_FMA"); 3431 Builder.defineMacro("__ARM_FEATURE_DIV"); 3432 3433 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3434 3435 // 0xe implies support for half, single and double precision operations. 3436 Builder.defineMacro("__ARM_FP", "0xe"); 3437 3438 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3439 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3440 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3441 3442 if (Opts.FastMath || Opts.FiniteMathOnly) 3443 Builder.defineMacro("__ARM_FP_FAST"); 3444 3445 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3446 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3447 3448 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3449 Opts.ShortWChar ? "2" : "4"); 3450 3451 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3452 Opts.ShortEnums ? "1" : "4"); 3453 3454 if (FPU == NeonMode) { 3455 Builder.defineMacro("__ARM_NEON"); 3456 // 64-bit NEON supports half, single and double precision operations. 3457 Builder.defineMacro("__ARM_NEON_FP", "7"); 3458 } 3459 3460 if (Crypto) { 3461 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3462 } 3463 } 3464 void getTargetBuiltins(const Builtin::Info *&Records, 3465 unsigned &NumRecords) const override { 3466 Records = BuiltinInfo; 3467 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3468 } 3469 bool hasFeature(StringRef Feature) const override { 3470 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3471 } 3472 3473 bool setCPU(const std::string &Name) override { 3474 return llvm::StringSwitch<bool>(Name) 3475 .Case("generic", true) 3476 .Cases("cortex-a53", "cortex-a57", true) 3477 .Default(false); 3478 } 3479 3480 bool handleTargetFeatures(std::vector<std::string> &Features, 3481 DiagnosticsEngine &Diags) override { 3482 FPU = FPUMode; 3483 Crypto = 0; 3484 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3485 if (Features[i] == "+neon") 3486 FPU = NeonMode; 3487 if (Features[i] == "+crypto") 3488 Crypto = 1; 3489 } 3490 3491 setDescriptionString(); 3492 3493 return true; 3494 } 3495 3496 void getGCCRegNames(const char *const *&Names, 3497 unsigned &NumNames) const override; 3498 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3499 unsigned &NumAliases) const override; 3500 3501 bool isCLZForZeroUndef() const override { return false; } 3502 3503 bool validateAsmConstraint(const char *&Name, 3504 TargetInfo::ConstraintInfo &Info) const override { 3505 switch (*Name) { 3506 default: return false; 3507 case 'w': // An FP/SIMD vector register 3508 Info.setAllowsRegister(); 3509 return true; 3510 case 'I': // Constant that can be used with an ADD instruction 3511 case 'J': // Constant that can be used with a SUB instruction 3512 case 'K': // Constant that can be used with a 32-bit logical instruction 3513 case 'L': // Constant that can be used with a 64-bit logical instruction 3514 case 'M': // Constant that can be used as a 32-bit MOV immediate 3515 case 'N': // Constant that can be used as a 64-bit MOV immediate 3516 case 'Y': // Floating point constant zero 3517 case 'Z': // Integer constant zero 3518 return true; 3519 case 'Q': // A memory reference with base register and no offset 3520 Info.setAllowsMemory(); 3521 return true; 3522 case 'S': // A symbolic address 3523 Info.setAllowsRegister(); 3524 return true; 3525 case 'U': 3526 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3527 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3528 // Usa: An absolute symbolic address 3529 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3530 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3531 } 3532 } 3533 3534 const char *getClobbers() const override { 3535 // There are no AArch64 clobbers shared by all asm statements. 3536 return ""; 3537 } 3538 3539 BuiltinVaListKind getBuiltinVaListKind() const override { 3540 return TargetInfo::AArch64ABIBuiltinVaList; 3541 } 3542 }; 3543 3544 const char * const AArch64TargetInfo::GCCRegNames[] = { 3545 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3546 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3547 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3548 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3549 3550 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3551 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3552 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3553 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3554 3555 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3556 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3557 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3558 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3559 3560 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3561 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3562 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3563 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3564 3565 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3566 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3567 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3568 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3569 3570 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3571 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3572 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3573 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3574 3575 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3576 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3577 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3578 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3579 }; 3580 3581 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3582 unsigned &NumNames) const { 3583 Names = GCCRegNames; 3584 NumNames = llvm::array_lengthof(GCCRegNames); 3585 } 3586 3587 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3588 { { "x16" }, "ip0"}, 3589 { { "x17" }, "ip1"}, 3590 { { "x29" }, "fp" }, 3591 { { "x30" }, "lr" } 3592 }; 3593 3594 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3595 unsigned &NumAliases) const { 3596 Aliases = GCCRegAliases; 3597 NumAliases = llvm::array_lengthof(GCCRegAliases); 3598 3599 } 3600 3601 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3602 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3603 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3604 ALL_LANGUAGES }, 3605 #define GET_NEON_BUILTINS 3606 #include "clang/Basic/arm_neon.inc" 3607 #undef GET_NEON_BUILTINS 3608 3609 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3610 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3611 ALL_LANGUAGES }, 3612 #include "clang/Basic/BuiltinsAArch64.def" 3613 }; 3614 3615 class AArch64leTargetInfo : public AArch64TargetInfo { 3616 void setDescriptionString() override { 3617 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3618 } 3619 3620 public: 3621 AArch64leTargetInfo(const llvm::Triple &Triple) 3622 : AArch64TargetInfo(Triple) { 3623 BigEndian = false; 3624 } 3625 void getTargetDefines(const LangOptions &Opts, 3626 MacroBuilder &Builder) const override { 3627 Builder.defineMacro("__AARCH64EL__"); 3628 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3629 } 3630 }; 3631 3632 class AArch64beTargetInfo : public AArch64TargetInfo { 3633 void setDescriptionString() override { 3634 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3635 } 3636 3637 public: 3638 AArch64beTargetInfo(const llvm::Triple &Triple) 3639 : AArch64TargetInfo(Triple) { } 3640 void getTargetDefines(const LangOptions &Opts, 3641 MacroBuilder &Builder) const override { 3642 Builder.defineMacro("__AARCH64EB__"); 3643 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3644 Builder.defineMacro("__ARM_BIG_ENDIAN"); 3645 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3646 } 3647 }; 3648 3649 } // end anonymous namespace 3650 3651 namespace { 3652 class ARMTargetInfo : public TargetInfo { 3653 // Possible FPU choices. 3654 enum FPUMode { 3655 VFP2FPU = (1 << 0), 3656 VFP3FPU = (1 << 1), 3657 VFP4FPU = (1 << 2), 3658 NeonFPU = (1 << 3), 3659 FPARMV8 = (1 << 4) 3660 }; 3661 3662 // Possible HWDiv features. 3663 enum HWDivMode { 3664 HWDivThumb = (1 << 0), 3665 HWDivARM = (1 << 1) 3666 }; 3667 3668 static bool FPUModeIsVFP(FPUMode Mode) { 3669 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3670 } 3671 3672 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3673 static const char * const GCCRegNames[]; 3674 3675 std::string ABI, CPU; 3676 3677 enum { 3678 FP_Default, 3679 FP_VFP, 3680 FP_Neon 3681 } FPMath; 3682 3683 unsigned FPU : 5; 3684 3685 unsigned IsAAPCS : 1; 3686 unsigned IsThumb : 1; 3687 unsigned HWDiv : 2; 3688 3689 // Initialized via features. 3690 unsigned SoftFloat : 1; 3691 unsigned SoftFloatABI : 1; 3692 3693 unsigned CRC : 1; 3694 unsigned Crypto : 1; 3695 3696 static const Builtin::Info BuiltinInfo[]; 3697 3698 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3699 // On linux, binaries targeting old cpus call functions in libgcc to 3700 // perform atomic operations. The implementation in libgcc then calls into 3701 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3702 // is that if we assume the kernel is at least as recent as the hardware, 3703 // it is safe to use atomic instructions on armv6 and newer. 3704 if (!T.isOSLinux() && 3705 T.getOS() != llvm::Triple::FreeBSD && 3706 T.getOS() != llvm::Triple::NetBSD && 3707 T.getOS() != llvm::Triple::Bitrig) 3708 return false; 3709 StringRef ArchName = T.getArchName(); 3710 if (T.getArch() == llvm::Triple::arm) { 3711 if (!ArchName.startswith("armv")) 3712 return false; 3713 StringRef VersionStr = ArchName.substr(4); 3714 unsigned Version; 3715 if (VersionStr.getAsInteger(10, Version)) 3716 return false; 3717 return Version >= 6; 3718 } 3719 assert(T.getArch() == llvm::Triple::thumb); 3720 if (!ArchName.startswith("thumbv")) 3721 return false; 3722 StringRef VersionStr = ArchName.substr(6); 3723 unsigned Version; 3724 if (VersionStr.getAsInteger(10, Version)) 3725 return false; 3726 return Version >= 7; 3727 } 3728 3729 void setABIAAPCS() { 3730 IsAAPCS = true; 3731 3732 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3733 const llvm::Triple &T = getTriple(); 3734 3735 // size_t is unsigned long on Darwin and NetBSD. 3736 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3737 SizeType = UnsignedLong; 3738 else 3739 SizeType = UnsignedInt; 3740 3741 if (T.getOS() == llvm::Triple::NetBSD) { 3742 WCharType = SignedInt; 3743 } else { 3744 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3745 WCharType = UnsignedInt; 3746 } 3747 3748 UseBitFieldTypeAlignment = true; 3749 3750 ZeroLengthBitfieldBoundary = 0; 3751 3752 if (IsThumb) { 3753 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3754 // so set preferred for small types to 32. 3755 if (T.isOSBinFormatMachO()) 3756 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3757 "v128:64:128-a:0:32-n32-S64"; 3758 else 3759 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3760 "v128:64:128-a:0:32-n32-S64"; 3761 3762 } else { 3763 if (T.isOSBinFormatMachO()) 3764 DescriptionString = "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3765 else 3766 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3767 } 3768 3769 // FIXME: Enumerated types are variable width in straight AAPCS. 3770 } 3771 3772 void setABIAPCS() { 3773 const llvm::Triple &T = getTriple(); 3774 3775 IsAAPCS = false; 3776 3777 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3778 3779 // size_t is unsigned int on FreeBSD. 3780 if (T.getOS() == llvm::Triple::FreeBSD) 3781 SizeType = UnsignedInt; 3782 else 3783 SizeType = UnsignedLong; 3784 3785 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3786 WCharType = SignedInt; 3787 3788 // Do not respect the alignment of bit-field types when laying out 3789 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3790 UseBitFieldTypeAlignment = false; 3791 3792 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3793 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3794 /// gcc. 3795 ZeroLengthBitfieldBoundary = 32; 3796 3797 if (IsThumb) { 3798 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3799 // so set preferred for small types to 32. 3800 if (T.isOSBinFormatMachO()) 3801 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3802 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3803 else 3804 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3805 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3806 } else { 3807 if (T.isOSBinFormatMachO()) 3808 DescriptionString = 3809 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3810 else 3811 DescriptionString = 3812 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3813 } 3814 3815 // FIXME: Override "preferred align" for double and long long. 3816 } 3817 3818 public: 3819 ARMTargetInfo(const llvm::Triple &Triple) 3820 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3821 IsAAPCS(true) { 3822 BigEndian = false; 3823 switch (getTriple().getOS()) { 3824 case llvm::Triple::NetBSD: 3825 PtrDiffType = SignedLong; 3826 break; 3827 default: 3828 PtrDiffType = SignedInt; 3829 break; 3830 } 3831 3832 // {} in inline assembly are neon specifiers, not assembly variant 3833 // specifiers. 3834 NoAsmVariants = true; 3835 3836 // FIXME: Should we just treat this as a feature? 3837 IsThumb = getTriple().getArchName().startswith("thumb"); 3838 3839 setABI("aapcs-linux"); 3840 3841 // ARM targets default to using the ARM C++ ABI. 3842 TheCXXABI.set(TargetCXXABI::GenericARM); 3843 3844 // ARM has atomics up to 8 bytes 3845 MaxAtomicPromoteWidth = 64; 3846 if (shouldUseInlineAtomic(getTriple())) 3847 MaxAtomicInlineWidth = 64; 3848 3849 // Do force alignment of members that follow zero length bitfields. If 3850 // the alignment of the zero-length bitfield is greater than the member 3851 // that follows it, `bar', `bar' will be aligned as the type of the 3852 // zero length bitfield. 3853 UseZeroLengthBitfieldAlignment = true; 3854 } 3855 const char *getABI() const override { return ABI.c_str(); } 3856 bool setABI(const std::string &Name) override { 3857 ABI = Name; 3858 3859 // The defaults (above) are for AAPCS, check if we need to change them. 3860 // 3861 // FIXME: We need support for -meabi... we could just mangle it into the 3862 // name. 3863 if (Name == "apcs-gnu") { 3864 setABIAPCS(); 3865 return true; 3866 } 3867 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3868 setABIAAPCS(); 3869 return true; 3870 } 3871 return false; 3872 } 3873 3874 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3875 if (IsAAPCS) 3876 Features["aapcs"] = true; 3877 else 3878 Features["apcs"] = true; 3879 3880 StringRef ArchName = getTriple().getArchName(); 3881 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3882 Features["vfp2"] = true; 3883 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3884 CPU == "cortex-a9-mp") { 3885 Features["vfp3"] = true; 3886 Features["neon"] = true; 3887 } 3888 else if (CPU == "cortex-a5") { 3889 Features["vfp4"] = true; 3890 Features["neon"] = true; 3891 } else if (CPU == "swift" || CPU == "cortex-a7" || 3892 CPU == "cortex-a12" || CPU == "cortex-a15" || 3893 CPU == "krait") { 3894 Features["vfp4"] = true; 3895 Features["neon"] = true; 3896 Features["hwdiv"] = true; 3897 Features["hwdiv-arm"] = true; 3898 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3899 Features["fp-armv8"] = true; 3900 Features["neon"] = true; 3901 Features["hwdiv"] = true; 3902 Features["hwdiv-arm"] = true; 3903 Features["crc"] = true; 3904 Features["crypto"] = true; 3905 } else if (CPU == "cortex-r5" || 3906 // Enable the hwdiv extension for all v8a AArch32 cores by 3907 // default. 3908 ArchName == "armv8a" || ArchName == "armv8" || 3909 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3910 Features["hwdiv"] = true; 3911 Features["hwdiv-arm"] = true; 3912 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3913 Features["hwdiv"] = true; 3914 } 3915 } 3916 3917 bool handleTargetFeatures(std::vector<std::string> &Features, 3918 DiagnosticsEngine &Diags) override { 3919 FPU = 0; 3920 CRC = 0; 3921 Crypto = 0; 3922 SoftFloat = SoftFloatABI = false; 3923 HWDiv = 0; 3924 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3925 if (Features[i] == "+soft-float") 3926 SoftFloat = true; 3927 else if (Features[i] == "+soft-float-abi") 3928 SoftFloatABI = true; 3929 else if (Features[i] == "+vfp2") 3930 FPU |= VFP2FPU; 3931 else if (Features[i] == "+vfp3") 3932 FPU |= VFP3FPU; 3933 else if (Features[i] == "+vfp4") 3934 FPU |= VFP4FPU; 3935 else if (Features[i] == "+fp-armv8") 3936 FPU |= FPARMV8; 3937 else if (Features[i] == "+neon") 3938 FPU |= NeonFPU; 3939 else if (Features[i] == "+hwdiv") 3940 HWDiv |= HWDivThumb; 3941 else if (Features[i] == "+hwdiv-arm") 3942 HWDiv |= HWDivARM; 3943 else if (Features[i] == "+crc") 3944 CRC = 1; 3945 else if (Features[i] == "+crypto") 3946 Crypto = 1; 3947 } 3948 3949 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3950 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3951 return false; 3952 } 3953 3954 if (FPMath == FP_Neon) 3955 Features.push_back("+neonfp"); 3956 else if (FPMath == FP_VFP) 3957 Features.push_back("-neonfp"); 3958 3959 // Remove front-end specific options which the backend handles differently. 3960 std::vector<std::string>::iterator it; 3961 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3962 if (it != Features.end()) 3963 Features.erase(it); 3964 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3965 if (it != Features.end()) 3966 Features.erase(it); 3967 return true; 3968 } 3969 3970 bool hasFeature(StringRef Feature) const override { 3971 return llvm::StringSwitch<bool>(Feature) 3972 .Case("arm", true) 3973 .Case("softfloat", SoftFloat) 3974 .Case("thumb", IsThumb) 3975 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3976 .Case("hwdiv", HWDiv & HWDivThumb) 3977 .Case("hwdiv-arm", HWDiv & HWDivARM) 3978 .Default(false); 3979 } 3980 // FIXME: Should we actually have some table instead of these switches? 3981 static const char *getCPUDefineSuffix(StringRef Name) { 3982 return llvm::StringSwitch<const char*>(Name) 3983 .Cases("arm8", "arm810", "4") 3984 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3985 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3986 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3987 .Case("ep9312", "4T") 3988 .Cases("arm10tdmi", "arm1020t", "5T") 3989 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3990 .Case("arm926ej-s", "5TEJ") 3991 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3992 .Cases("xscale", "iwmmxt", "5TE") 3993 .Case("arm1136j-s", "6J") 3994 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3995 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3996 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3997 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3998 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3999 .Cases("cortex-r4", "cortex-r5", "7R") 4000 .Case("swift", "7S") 4001 .Cases("cortex-m3", "cortex-m4", "7M") 4002 .Case("cortex-m0", "6M") 4003 .Cases("cortex-a53", "cortex-a57", "8A") 4004 .Default(0); 4005 } 4006 static const char *getCPUProfile(StringRef Name) { 4007 return llvm::StringSwitch<const char*>(Name) 4008 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4009 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4010 .Cases("cortex-a53", "cortex-a57", "A") 4011 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4012 .Cases("cortex-r4", "cortex-r5", "R") 4013 .Default(""); 4014 } 4015 bool setCPU(const std::string &Name) override { 4016 if (!getCPUDefineSuffix(Name)) 4017 return false; 4018 4019 CPU = Name; 4020 return true; 4021 } 4022 bool setFPMath(StringRef Name) override; 4023 void getTargetDefines(const LangOptions &Opts, 4024 MacroBuilder &Builder) const override { 4025 // Target identification. 4026 Builder.defineMacro("__arm"); 4027 Builder.defineMacro("__arm__"); 4028 4029 // Target properties. 4030 Builder.defineMacro("__ARMEL__"); 4031 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4032 4033 StringRef CPUArch = getCPUDefineSuffix(CPU); 4034 unsigned int CPUArchVer; 4035 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4036 llvm_unreachable("Invalid char for architecture version number"); 4037 } 4038 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4039 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4040 StringRef CPUProfile = getCPUProfile(CPU); 4041 if (!CPUProfile.empty()) 4042 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4043 4044 // Subtarget options. 4045 4046 // FIXME: It's more complicated than this and we don't really support 4047 // interworking. 4048 if (5 <= CPUArchVer && CPUArchVer <= 8) 4049 Builder.defineMacro("__THUMB_INTERWORK__"); 4050 4051 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4052 // Embedded targets on Darwin follow AAPCS, but not EABI. 4053 if (!getTriple().isOSDarwin()) 4054 Builder.defineMacro("__ARM_EABI__"); 4055 Builder.defineMacro("__ARM_PCS", "1"); 4056 4057 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4058 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4059 } 4060 4061 if (SoftFloat) 4062 Builder.defineMacro("__SOFTFP__"); 4063 4064 if (CPU == "xscale") 4065 Builder.defineMacro("__XSCALE__"); 4066 4067 if (IsThumb) { 4068 Builder.defineMacro("__THUMBEL__"); 4069 Builder.defineMacro("__thumb__"); 4070 // We check both CPUArchVer and ArchName because when only triple is 4071 // specified, the default CPU is arm1136j-s. 4072 StringRef ArchName = getTriple().getArchName(); 4073 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4074 ArchName.endswith("v7") || ArchName.endswith("v8")) 4075 Builder.defineMacro("__thumb2__"); 4076 } 4077 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4078 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4079 4080 // Note, this is always on in gcc, even though it doesn't make sense. 4081 Builder.defineMacro("__APCS_32__"); 4082 4083 if (FPUModeIsVFP((FPUMode) FPU)) { 4084 Builder.defineMacro("__VFP_FP__"); 4085 if (FPU & VFP2FPU) 4086 Builder.defineMacro("__ARM_VFPV2__"); 4087 if (FPU & VFP3FPU) 4088 Builder.defineMacro("__ARM_VFPV3__"); 4089 if (FPU & VFP4FPU) 4090 Builder.defineMacro("__ARM_VFPV4__"); 4091 } 4092 4093 // This only gets set when Neon instructions are actually available, unlike 4094 // the VFP define, hence the soft float and arch check. This is subtly 4095 // different from gcc, we follow the intent which was that it should be set 4096 // when Neon instructions are actually available. 4097 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4098 Builder.defineMacro("__ARM_NEON"); 4099 Builder.defineMacro("__ARM_NEON__"); 4100 } 4101 4102 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4103 Opts.ShortWChar ? "2" : "4"); 4104 4105 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4106 Opts.ShortEnums ? "1" : "4"); 4107 4108 if (CRC) 4109 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4110 4111 if (Crypto) 4112 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4113 4114 if (CPUArchVer >= 6 && CPUArch != "6M") { 4115 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4116 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4117 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4118 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4119 } 4120 } 4121 void getTargetBuiltins(const Builtin::Info *&Records, 4122 unsigned &NumRecords) const override { 4123 Records = BuiltinInfo; 4124 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4125 } 4126 bool isCLZForZeroUndef() const override { return false; } 4127 BuiltinVaListKind getBuiltinVaListKind() const override { 4128 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4129 } 4130 void getGCCRegNames(const char * const *&Names, 4131 unsigned &NumNames) const override; 4132 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4133 unsigned &NumAliases) const override; 4134 bool validateAsmConstraint(const char *&Name, 4135 TargetInfo::ConstraintInfo &Info) const override { 4136 switch (*Name) { 4137 default: break; 4138 case 'l': // r0-r7 4139 case 'h': // r8-r15 4140 case 'w': // VFP Floating point register single precision 4141 case 'P': // VFP Floating point register double precision 4142 Info.setAllowsRegister(); 4143 return true; 4144 case 'Q': // A memory address that is a single base register. 4145 Info.setAllowsMemory(); 4146 return true; 4147 case 'U': // a memory reference... 4148 switch (Name[1]) { 4149 case 'q': // ...ARMV4 ldrsb 4150 case 'v': // ...VFP load/store (reg+constant offset) 4151 case 'y': // ...iWMMXt load/store 4152 case 't': // address valid for load/store opaque types wider 4153 // than 128-bits 4154 case 'n': // valid address for Neon doubleword vector load/store 4155 case 'm': // valid address for Neon element and structure load/store 4156 case 's': // valid address for non-offset loads/stores of quad-word 4157 // values in four ARM registers 4158 Info.setAllowsMemory(); 4159 Name++; 4160 return true; 4161 } 4162 } 4163 return false; 4164 } 4165 std::string convertConstraint(const char *&Constraint) const override { 4166 std::string R; 4167 switch (*Constraint) { 4168 case 'U': // Two-character constraint; add "^" hint for later parsing. 4169 R = std::string("^") + std::string(Constraint, 2); 4170 Constraint++; 4171 break; 4172 case 'p': // 'p' should be translated to 'r' by default. 4173 R = std::string("r"); 4174 break; 4175 default: 4176 return std::string(1, *Constraint); 4177 } 4178 return R; 4179 } 4180 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4181 unsigned Size) const override { 4182 bool isOutput = (Constraint[0] == '='); 4183 bool isInOut = (Constraint[0] == '+'); 4184 4185 // Strip off constraint modifiers. 4186 while (Constraint[0] == '=' || 4187 Constraint[0] == '+' || 4188 Constraint[0] == '&') 4189 Constraint = Constraint.substr(1); 4190 4191 switch (Constraint[0]) { 4192 default: break; 4193 case 'r': { 4194 switch (Modifier) { 4195 default: 4196 return (isInOut || isOutput || Size <= 64); 4197 case 'q': 4198 // A register of size 32 cannot fit a vector type. 4199 return false; 4200 } 4201 } 4202 } 4203 4204 return true; 4205 } 4206 const char *getClobbers() const override { 4207 // FIXME: Is this really right? 4208 return ""; 4209 } 4210 4211 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4212 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4213 } 4214 4215 int getEHDataRegisterNumber(unsigned RegNo) const override { 4216 if (RegNo == 0) return 0; 4217 if (RegNo == 1) return 1; 4218 return -1; 4219 } 4220 }; 4221 4222 bool ARMTargetInfo::setFPMath(StringRef Name) { 4223 if (Name == "neon") { 4224 FPMath = FP_Neon; 4225 return true; 4226 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4227 Name == "vfp4") { 4228 FPMath = FP_VFP; 4229 return true; 4230 } 4231 return false; 4232 } 4233 4234 const char * const ARMTargetInfo::GCCRegNames[] = { 4235 // Integer registers 4236 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4237 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4238 4239 // Float registers 4240 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4241 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4242 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4243 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4244 4245 // Double registers 4246 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4247 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4248 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4249 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4250 4251 // Quad registers 4252 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4253 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4254 }; 4255 4256 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4257 unsigned &NumNames) const { 4258 Names = GCCRegNames; 4259 NumNames = llvm::array_lengthof(GCCRegNames); 4260 } 4261 4262 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4263 { { "a1" }, "r0" }, 4264 { { "a2" }, "r1" }, 4265 { { "a3" }, "r2" }, 4266 { { "a4" }, "r3" }, 4267 { { "v1" }, "r4" }, 4268 { { "v2" }, "r5" }, 4269 { { "v3" }, "r6" }, 4270 { { "v4" }, "r7" }, 4271 { { "v5" }, "r8" }, 4272 { { "v6", "rfp" }, "r9" }, 4273 { { "sl" }, "r10" }, 4274 { { "fp" }, "r11" }, 4275 { { "ip" }, "r12" }, 4276 { { "r13" }, "sp" }, 4277 { { "r14" }, "lr" }, 4278 { { "r15" }, "pc" }, 4279 // The S, D and Q registers overlap, but aren't really aliases; we 4280 // don't want to substitute one of these for a different-sized one. 4281 }; 4282 4283 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4284 unsigned &NumAliases) const { 4285 Aliases = GCCRegAliases; 4286 NumAliases = llvm::array_lengthof(GCCRegAliases); 4287 } 4288 4289 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4290 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4291 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4292 ALL_LANGUAGES }, 4293 #define GET_NEON_BUILTINS 4294 #include "clang/Basic/arm_neon.inc" 4295 #undef GET_NEON_BUILTINS 4296 4297 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4298 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4299 ALL_LANGUAGES }, 4300 #include "clang/Basic/BuiltinsARM.def" 4301 }; 4302 } // end anonymous namespace. 4303 4304 namespace { 4305 class DarwinARMTargetInfo : 4306 public DarwinTargetInfo<ARMTargetInfo> { 4307 protected: 4308 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4309 MacroBuilder &Builder) const override { 4310 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4311 } 4312 4313 public: 4314 DarwinARMTargetInfo(const llvm::Triple &Triple) 4315 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4316 HasAlignMac68kSupport = true; 4317 // iOS always has 64-bit atomic instructions. 4318 // FIXME: This should be based off of the target features in ARMTargetInfo. 4319 MaxAtomicInlineWidth = 64; 4320 4321 // Darwin on iOS uses a variant of the ARM C++ ABI. 4322 TheCXXABI.set(TargetCXXABI::iOS); 4323 } 4324 }; 4325 } // end anonymous namespace. 4326 4327 4328 namespace { 4329 // Hexagon abstract base class 4330 class HexagonTargetInfo : public TargetInfo { 4331 static const Builtin::Info BuiltinInfo[]; 4332 static const char * const GCCRegNames[]; 4333 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4334 std::string CPU; 4335 public: 4336 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4337 BigEndian = false; 4338 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4339 4340 // {} in inline assembly are packet specifiers, not assembly variant 4341 // specifiers. 4342 NoAsmVariants = true; 4343 } 4344 4345 void getTargetBuiltins(const Builtin::Info *&Records, 4346 unsigned &NumRecords) const override { 4347 Records = BuiltinInfo; 4348 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4349 } 4350 4351 bool validateAsmConstraint(const char *&Name, 4352 TargetInfo::ConstraintInfo &Info) const override { 4353 return true; 4354 } 4355 4356 void getTargetDefines(const LangOptions &Opts, 4357 MacroBuilder &Builder) const override; 4358 4359 bool hasFeature(StringRef Feature) const override { 4360 return Feature == "hexagon"; 4361 } 4362 4363 BuiltinVaListKind getBuiltinVaListKind() const override { 4364 return TargetInfo::CharPtrBuiltinVaList; 4365 } 4366 void getGCCRegNames(const char * const *&Names, 4367 unsigned &NumNames) const override; 4368 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4369 unsigned &NumAliases) const override; 4370 const char *getClobbers() const override { 4371 return ""; 4372 } 4373 4374 static const char *getHexagonCPUSuffix(StringRef Name) { 4375 return llvm::StringSwitch<const char*>(Name) 4376 .Case("hexagonv4", "4") 4377 .Case("hexagonv5", "5") 4378 .Default(0); 4379 } 4380 4381 bool setCPU(const std::string &Name) override { 4382 if (!getHexagonCPUSuffix(Name)) 4383 return false; 4384 4385 CPU = Name; 4386 return true; 4387 } 4388 }; 4389 4390 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4391 MacroBuilder &Builder) const { 4392 Builder.defineMacro("qdsp6"); 4393 Builder.defineMacro("__qdsp6", "1"); 4394 Builder.defineMacro("__qdsp6__", "1"); 4395 4396 Builder.defineMacro("hexagon"); 4397 Builder.defineMacro("__hexagon", "1"); 4398 Builder.defineMacro("__hexagon__", "1"); 4399 4400 if(CPU == "hexagonv1") { 4401 Builder.defineMacro("__HEXAGON_V1__"); 4402 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4403 if(Opts.HexagonQdsp6Compat) { 4404 Builder.defineMacro("__QDSP6_V1__"); 4405 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4406 } 4407 } 4408 else if(CPU == "hexagonv2") { 4409 Builder.defineMacro("__HEXAGON_V2__"); 4410 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4411 if(Opts.HexagonQdsp6Compat) { 4412 Builder.defineMacro("__QDSP6_V2__"); 4413 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4414 } 4415 } 4416 else if(CPU == "hexagonv3") { 4417 Builder.defineMacro("__HEXAGON_V3__"); 4418 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4419 if(Opts.HexagonQdsp6Compat) { 4420 Builder.defineMacro("__QDSP6_V3__"); 4421 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4422 } 4423 } 4424 else if(CPU == "hexagonv4") { 4425 Builder.defineMacro("__HEXAGON_V4__"); 4426 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4427 if(Opts.HexagonQdsp6Compat) { 4428 Builder.defineMacro("__QDSP6_V4__"); 4429 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4430 } 4431 } 4432 else if(CPU == "hexagonv5") { 4433 Builder.defineMacro("__HEXAGON_V5__"); 4434 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4435 if(Opts.HexagonQdsp6Compat) { 4436 Builder.defineMacro("__QDSP6_V5__"); 4437 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4438 } 4439 } 4440 } 4441 4442 const char * const HexagonTargetInfo::GCCRegNames[] = { 4443 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4444 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4445 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4446 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4447 "p0", "p1", "p2", "p3", 4448 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4449 }; 4450 4451 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4452 unsigned &NumNames) const { 4453 Names = GCCRegNames; 4454 NumNames = llvm::array_lengthof(GCCRegNames); 4455 } 4456 4457 4458 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4459 { { "sp" }, "r29" }, 4460 { { "fp" }, "r30" }, 4461 { { "lr" }, "r31" }, 4462 }; 4463 4464 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4465 unsigned &NumAliases) const { 4466 Aliases = GCCRegAliases; 4467 NumAliases = llvm::array_lengthof(GCCRegAliases); 4468 } 4469 4470 4471 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4472 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4473 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4474 ALL_LANGUAGES }, 4475 #include "clang/Basic/BuiltinsHexagon.def" 4476 }; 4477 } 4478 4479 4480 namespace { 4481 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4482 class SparcTargetInfo : public TargetInfo { 4483 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4484 static const char * const GCCRegNames[]; 4485 bool SoftFloat; 4486 public: 4487 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4488 4489 bool handleTargetFeatures(std::vector<std::string> &Features, 4490 DiagnosticsEngine &Diags) override { 4491 SoftFloat = false; 4492 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4493 if (Features[i] == "+soft-float") 4494 SoftFloat = true; 4495 return true; 4496 } 4497 void getTargetDefines(const LangOptions &Opts, 4498 MacroBuilder &Builder) const override { 4499 DefineStd(Builder, "sparc", Opts); 4500 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4501 4502 if (SoftFloat) 4503 Builder.defineMacro("SOFT_FLOAT", "1"); 4504 } 4505 4506 bool hasFeature(StringRef Feature) const override { 4507 return llvm::StringSwitch<bool>(Feature) 4508 .Case("softfloat", SoftFloat) 4509 .Case("sparc", true) 4510 .Default(false); 4511 } 4512 4513 void getTargetBuiltins(const Builtin::Info *&Records, 4514 unsigned &NumRecords) const override { 4515 // FIXME: Implement! 4516 } 4517 BuiltinVaListKind getBuiltinVaListKind() const override { 4518 return TargetInfo::VoidPtrBuiltinVaList; 4519 } 4520 void getGCCRegNames(const char * const *&Names, 4521 unsigned &NumNames) const override; 4522 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4523 unsigned &NumAliases) const override; 4524 bool validateAsmConstraint(const char *&Name, 4525 TargetInfo::ConstraintInfo &info) const override { 4526 // FIXME: Implement! 4527 return false; 4528 } 4529 const char *getClobbers() const override { 4530 // FIXME: Implement! 4531 return ""; 4532 } 4533 }; 4534 4535 const char * const SparcTargetInfo::GCCRegNames[] = { 4536 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4537 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4538 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4539 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4540 }; 4541 4542 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4543 unsigned &NumNames) const { 4544 Names = GCCRegNames; 4545 NumNames = llvm::array_lengthof(GCCRegNames); 4546 } 4547 4548 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4549 { { "g0" }, "r0" }, 4550 { { "g1" }, "r1" }, 4551 { { "g2" }, "r2" }, 4552 { { "g3" }, "r3" }, 4553 { { "g4" }, "r4" }, 4554 { { "g5" }, "r5" }, 4555 { { "g6" }, "r6" }, 4556 { { "g7" }, "r7" }, 4557 { { "o0" }, "r8" }, 4558 { { "o1" }, "r9" }, 4559 { { "o2" }, "r10" }, 4560 { { "o3" }, "r11" }, 4561 { { "o4" }, "r12" }, 4562 { { "o5" }, "r13" }, 4563 { { "o6", "sp" }, "r14" }, 4564 { { "o7" }, "r15" }, 4565 { { "l0" }, "r16" }, 4566 { { "l1" }, "r17" }, 4567 { { "l2" }, "r18" }, 4568 { { "l3" }, "r19" }, 4569 { { "l4" }, "r20" }, 4570 { { "l5" }, "r21" }, 4571 { { "l6" }, "r22" }, 4572 { { "l7" }, "r23" }, 4573 { { "i0" }, "r24" }, 4574 { { "i1" }, "r25" }, 4575 { { "i2" }, "r26" }, 4576 { { "i3" }, "r27" }, 4577 { { "i4" }, "r28" }, 4578 { { "i5" }, "r29" }, 4579 { { "i6", "fp" }, "r30" }, 4580 { { "i7" }, "r31" }, 4581 }; 4582 4583 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4584 unsigned &NumAliases) const { 4585 Aliases = GCCRegAliases; 4586 NumAliases = llvm::array_lengthof(GCCRegAliases); 4587 } 4588 4589 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4590 class SparcV8TargetInfo : public SparcTargetInfo { 4591 public: 4592 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4593 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4594 } 4595 4596 void getTargetDefines(const LangOptions &Opts, 4597 MacroBuilder &Builder) const override { 4598 SparcTargetInfo::getTargetDefines(Opts, Builder); 4599 Builder.defineMacro("__sparcv8"); 4600 } 4601 }; 4602 4603 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4604 class SparcV9TargetInfo : public SparcTargetInfo { 4605 public: 4606 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4607 // FIXME: Support Sparc quad-precision long double? 4608 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4609 // This is an LP64 platform. 4610 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4611 4612 // OpenBSD uses long long for int64_t and intmax_t. 4613 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4614 IntMaxType = SignedLongLong; 4615 UIntMaxType = UnsignedLongLong; 4616 } else { 4617 IntMaxType = SignedLong; 4618 UIntMaxType = UnsignedLong; 4619 } 4620 Int64Type = IntMaxType; 4621 4622 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4623 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4624 LongDoubleWidth = 128; 4625 LongDoubleAlign = 128; 4626 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4627 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4628 } 4629 4630 void getTargetDefines(const LangOptions &Opts, 4631 MacroBuilder &Builder) const override { 4632 SparcTargetInfo::getTargetDefines(Opts, Builder); 4633 Builder.defineMacro("__sparcv9"); 4634 Builder.defineMacro("__arch64__"); 4635 // Solaris and its derivative AuroraUX don't need these variants, but the 4636 // BSDs do. 4637 if (getTriple().getOS() != llvm::Triple::Solaris && 4638 getTriple().getOS() != llvm::Triple::AuroraUX) { 4639 Builder.defineMacro("__sparc64__"); 4640 Builder.defineMacro("__sparc_v9__"); 4641 Builder.defineMacro("__sparcv9__"); 4642 } 4643 } 4644 4645 bool setCPU(const std::string &Name) override { 4646 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4647 .Case("v9", true) 4648 .Case("ultrasparc", true) 4649 .Case("ultrasparc3", true) 4650 .Case("niagara", true) 4651 .Case("niagara2", true) 4652 .Case("niagara3", true) 4653 .Case("niagara4", true) 4654 .Default(false); 4655 4656 // No need to store the CPU yet. There aren't any CPU-specific 4657 // macros to define. 4658 return CPUKnown; 4659 } 4660 }; 4661 4662 } // end anonymous namespace. 4663 4664 namespace { 4665 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4666 public: 4667 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4668 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4669 SizeType = UnsignedInt; 4670 PtrDiffType = SignedInt; 4671 } 4672 }; 4673 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4674 public: 4675 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4676 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4677 SizeType = UnsignedInt; 4678 PtrDiffType = SignedInt; 4679 } 4680 }; 4681 } // end anonymous namespace. 4682 4683 namespace { 4684 class SystemZTargetInfo : public TargetInfo { 4685 static const char *const GCCRegNames[]; 4686 4687 public: 4688 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4689 TLSSupported = true; 4690 IntWidth = IntAlign = 32; 4691 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4692 PointerWidth = PointerAlign = 64; 4693 LongDoubleWidth = 128; 4694 LongDoubleAlign = 64; 4695 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4696 MinGlobalAlign = 16; 4697 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4698 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4699 } 4700 void getTargetDefines(const LangOptions &Opts, 4701 MacroBuilder &Builder) const override { 4702 Builder.defineMacro("__s390__"); 4703 Builder.defineMacro("__s390x__"); 4704 Builder.defineMacro("__zarch__"); 4705 Builder.defineMacro("__LONG_DOUBLE_128__"); 4706 } 4707 void getTargetBuiltins(const Builtin::Info *&Records, 4708 unsigned &NumRecords) const override { 4709 // FIXME: Implement. 4710 Records = 0; 4711 NumRecords = 0; 4712 } 4713 4714 void getGCCRegNames(const char *const *&Names, 4715 unsigned &NumNames) const override; 4716 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4717 unsigned &NumAliases) const override { 4718 // No aliases. 4719 Aliases = 0; 4720 NumAliases = 0; 4721 } 4722 bool validateAsmConstraint(const char *&Name, 4723 TargetInfo::ConstraintInfo &info) const override; 4724 const char *getClobbers() const override { 4725 // FIXME: Is this really right? 4726 return ""; 4727 } 4728 BuiltinVaListKind getBuiltinVaListKind() const override { 4729 return TargetInfo::SystemZBuiltinVaList; 4730 } 4731 bool setCPU(const std::string &Name) override { 4732 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4733 .Case("z10", true) 4734 .Case("z196", true) 4735 .Case("zEC12", true) 4736 .Default(false); 4737 4738 // No need to store the CPU yet. There aren't any CPU-specific 4739 // macros to define. 4740 return CPUKnown; 4741 } 4742 }; 4743 4744 const char *const SystemZTargetInfo::GCCRegNames[] = { 4745 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4746 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4747 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4748 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4749 }; 4750 4751 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4752 unsigned &NumNames) const { 4753 Names = GCCRegNames; 4754 NumNames = llvm::array_lengthof(GCCRegNames); 4755 } 4756 4757 bool SystemZTargetInfo:: 4758 validateAsmConstraint(const char *&Name, 4759 TargetInfo::ConstraintInfo &Info) const { 4760 switch (*Name) { 4761 default: 4762 return false; 4763 4764 case 'a': // Address register 4765 case 'd': // Data register (equivalent to 'r') 4766 case 'f': // Floating-point register 4767 Info.setAllowsRegister(); 4768 return true; 4769 4770 case 'I': // Unsigned 8-bit constant 4771 case 'J': // Unsigned 12-bit constant 4772 case 'K': // Signed 16-bit constant 4773 case 'L': // Signed 20-bit displacement (on all targets we support) 4774 case 'M': // 0x7fffffff 4775 return true; 4776 4777 case 'Q': // Memory with base and unsigned 12-bit displacement 4778 case 'R': // Likewise, plus an index 4779 case 'S': // Memory with base and signed 20-bit displacement 4780 case 'T': // Likewise, plus an index 4781 Info.setAllowsMemory(); 4782 return true; 4783 } 4784 } 4785 } 4786 4787 namespace { 4788 class MSP430TargetInfo : public TargetInfo { 4789 static const char * const GCCRegNames[]; 4790 public: 4791 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4792 BigEndian = false; 4793 TLSSupported = false; 4794 IntWidth = 16; IntAlign = 16; 4795 LongWidth = 32; LongLongWidth = 64; 4796 LongAlign = LongLongAlign = 16; 4797 PointerWidth = 16; PointerAlign = 16; 4798 SuitableAlign = 16; 4799 SizeType = UnsignedInt; 4800 IntMaxType = SignedLongLong; 4801 UIntMaxType = UnsignedLongLong; 4802 IntPtrType = SignedInt; 4803 PtrDiffType = SignedInt; 4804 SigAtomicType = SignedLong; 4805 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4806 } 4807 void getTargetDefines(const LangOptions &Opts, 4808 MacroBuilder &Builder) const override { 4809 Builder.defineMacro("MSP430"); 4810 Builder.defineMacro("__MSP430__"); 4811 // FIXME: defines for different 'flavours' of MCU 4812 } 4813 void getTargetBuiltins(const Builtin::Info *&Records, 4814 unsigned &NumRecords) const override { 4815 // FIXME: Implement. 4816 Records = 0; 4817 NumRecords = 0; 4818 } 4819 bool hasFeature(StringRef Feature) const override { 4820 return Feature == "msp430"; 4821 } 4822 void getGCCRegNames(const char * const *&Names, 4823 unsigned &NumNames) const override; 4824 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4825 unsigned &NumAliases) const override { 4826 // No aliases. 4827 Aliases = 0; 4828 NumAliases = 0; 4829 } 4830 bool validateAsmConstraint(const char *&Name, 4831 TargetInfo::ConstraintInfo &info) const override { 4832 // No target constraints for now. 4833 return false; 4834 } 4835 const char *getClobbers() const override { 4836 // FIXME: Is this really right? 4837 return ""; 4838 } 4839 BuiltinVaListKind getBuiltinVaListKind() const override { 4840 // FIXME: implement 4841 return TargetInfo::CharPtrBuiltinVaList; 4842 } 4843 }; 4844 4845 const char * const MSP430TargetInfo::GCCRegNames[] = { 4846 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4847 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4848 }; 4849 4850 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4851 unsigned &NumNames) const { 4852 Names = GCCRegNames; 4853 NumNames = llvm::array_lengthof(GCCRegNames); 4854 } 4855 } 4856 4857 namespace { 4858 4859 // LLVM and Clang cannot be used directly to output native binaries for 4860 // target, but is used to compile C code to llvm bitcode with correct 4861 // type and alignment information. 4862 // 4863 // TCE uses the llvm bitcode as input and uses it for generating customized 4864 // target processor and program binary. TCE co-design environment is 4865 // publicly available in http://tce.cs.tut.fi 4866 4867 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4868 3, // opencl_global 4869 4, // opencl_local 4870 5, // opencl_constant 4871 0, // cuda_device 4872 0, // cuda_constant 4873 0 // cuda_shared 4874 }; 4875 4876 class TCETargetInfo : public TargetInfo{ 4877 public: 4878 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4879 TLSSupported = false; 4880 IntWidth = 32; 4881 LongWidth = LongLongWidth = 32; 4882 PointerWidth = 32; 4883 IntAlign = 32; 4884 LongAlign = LongLongAlign = 32; 4885 PointerAlign = 32; 4886 SuitableAlign = 32; 4887 SizeType = UnsignedInt; 4888 IntMaxType = SignedLong; 4889 UIntMaxType = UnsignedLong; 4890 IntPtrType = SignedInt; 4891 PtrDiffType = SignedInt; 4892 FloatWidth = 32; 4893 FloatAlign = 32; 4894 DoubleWidth = 32; 4895 DoubleAlign = 32; 4896 LongDoubleWidth = 32; 4897 LongDoubleAlign = 32; 4898 FloatFormat = &llvm::APFloat::IEEEsingle; 4899 DoubleFormat = &llvm::APFloat::IEEEsingle; 4900 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4901 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4902 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4903 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4904 UseAddrSpaceMapMangling = true; 4905 } 4906 4907 void getTargetDefines(const LangOptions &Opts, 4908 MacroBuilder &Builder) const override { 4909 DefineStd(Builder, "tce", Opts); 4910 Builder.defineMacro("__TCE__"); 4911 Builder.defineMacro("__TCE_V1__"); 4912 } 4913 bool hasFeature(StringRef Feature) const override { 4914 return Feature == "tce"; 4915 } 4916 4917 void getTargetBuiltins(const Builtin::Info *&Records, 4918 unsigned &NumRecords) const override {} 4919 const char *getClobbers() const override { 4920 return ""; 4921 } 4922 BuiltinVaListKind getBuiltinVaListKind() const override { 4923 return TargetInfo::VoidPtrBuiltinVaList; 4924 } 4925 void getGCCRegNames(const char * const *&Names, 4926 unsigned &NumNames) const override {} 4927 bool validateAsmConstraint(const char *&Name, 4928 TargetInfo::ConstraintInfo &info) const override{ 4929 return true; 4930 } 4931 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4932 unsigned &NumAliases) const override {} 4933 }; 4934 } 4935 4936 namespace { 4937 class MipsTargetInfoBase : public TargetInfo { 4938 virtual void setDescriptionString() = 0; 4939 4940 static const Builtin::Info BuiltinInfo[]; 4941 std::string CPU; 4942 bool IsMips16; 4943 bool IsMicromips; 4944 bool IsNan2008; 4945 bool IsSingleFloat; 4946 enum MipsFloatABI { 4947 HardFloat, SoftFloat 4948 } FloatABI; 4949 enum DspRevEnum { 4950 NoDSP, DSP1, DSP2 4951 } DspRev; 4952 bool HasMSA; 4953 4954 protected: 4955 bool HasFP64; 4956 std::string ABI; 4957 4958 public: 4959 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4960 const std::string &CPUStr) 4961 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4962 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4963 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4964 4965 const char *getABI() const override { return ABI.c_str(); } 4966 bool setABI(const std::string &Name) override = 0; 4967 bool setCPU(const std::string &Name) override { 4968 CPU = Name; 4969 return true; 4970 } 4971 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4972 // The backend enables certain ABI's by default according to the 4973 // architecture. 4974 // Disable both possible defaults so that we don't end up with multiple 4975 // ABI's selected and trigger an assertion. 4976 Features["o32"] = false; 4977 Features["n64"] = false; 4978 4979 Features[ABI] = true; 4980 Features[CPU] = true; 4981 } 4982 4983 void getTargetDefines(const LangOptions &Opts, 4984 MacroBuilder &Builder) const override { 4985 Builder.defineMacro("__mips__"); 4986 Builder.defineMacro("_mips"); 4987 if (Opts.GNUMode) 4988 Builder.defineMacro("mips"); 4989 4990 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4991 4992 switch (FloatABI) { 4993 case HardFloat: 4994 Builder.defineMacro("__mips_hard_float", Twine(1)); 4995 break; 4996 case SoftFloat: 4997 Builder.defineMacro("__mips_soft_float", Twine(1)); 4998 break; 4999 } 5000 5001 if (IsSingleFloat) 5002 Builder.defineMacro("__mips_single_float", Twine(1)); 5003 5004 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5005 Builder.defineMacro("_MIPS_FPSET", 5006 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5007 5008 if (IsMips16) 5009 Builder.defineMacro("__mips16", Twine(1)); 5010 5011 if (IsMicromips) 5012 Builder.defineMacro("__mips_micromips", Twine(1)); 5013 5014 if (IsNan2008) 5015 Builder.defineMacro("__mips_nan2008", Twine(1)); 5016 5017 switch (DspRev) { 5018 default: 5019 break; 5020 case DSP1: 5021 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5022 Builder.defineMacro("__mips_dsp", Twine(1)); 5023 break; 5024 case DSP2: 5025 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5026 Builder.defineMacro("__mips_dspr2", Twine(1)); 5027 Builder.defineMacro("__mips_dsp", Twine(1)); 5028 break; 5029 } 5030 5031 if (HasMSA) 5032 Builder.defineMacro("__mips_msa", Twine(1)); 5033 5034 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5035 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5036 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5037 5038 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5039 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5040 } 5041 5042 void getTargetBuiltins(const Builtin::Info *&Records, 5043 unsigned &NumRecords) const override { 5044 Records = BuiltinInfo; 5045 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5046 } 5047 bool hasFeature(StringRef Feature) const override { 5048 return llvm::StringSwitch<bool>(Feature) 5049 .Case("mips", true) 5050 .Case("fp64", HasFP64) 5051 .Default(false); 5052 } 5053 BuiltinVaListKind getBuiltinVaListKind() const override { 5054 return TargetInfo::VoidPtrBuiltinVaList; 5055 } 5056 void getGCCRegNames(const char * const *&Names, 5057 unsigned &NumNames) const override { 5058 static const char *const GCCRegNames[] = { 5059 // CPU register names 5060 // Must match second column of GCCRegAliases 5061 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5062 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5063 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5064 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5065 // Floating point register names 5066 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5067 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5068 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5069 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5070 // Hi/lo and condition register names 5071 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5072 "$fcc5","$fcc6","$fcc7", 5073 // MSA register names 5074 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5075 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5076 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5077 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5078 // MSA control register names 5079 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5080 "$msarequest", "$msamap", "$msaunmap" 5081 }; 5082 Names = GCCRegNames; 5083 NumNames = llvm::array_lengthof(GCCRegNames); 5084 } 5085 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5086 unsigned &NumAliases) const override = 0; 5087 bool validateAsmConstraint(const char *&Name, 5088 TargetInfo::ConstraintInfo &Info) const override { 5089 switch (*Name) { 5090 default: 5091 return false; 5092 5093 case 'r': // CPU registers. 5094 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5095 case 'y': // Equivalent to "r", backwards compatibility only. 5096 case 'f': // floating-point registers. 5097 case 'c': // $25 for indirect jumps 5098 case 'l': // lo register 5099 case 'x': // hilo register pair 5100 Info.setAllowsRegister(); 5101 return true; 5102 case 'R': // An address that can be used in a non-macro load or store 5103 Info.setAllowsMemory(); 5104 return true; 5105 } 5106 } 5107 5108 const char *getClobbers() const override { 5109 // FIXME: Implement! 5110 return ""; 5111 } 5112 5113 bool handleTargetFeatures(std::vector<std::string> &Features, 5114 DiagnosticsEngine &Diags) override { 5115 IsMips16 = false; 5116 IsMicromips = false; 5117 IsNan2008 = false; 5118 IsSingleFloat = false; 5119 FloatABI = HardFloat; 5120 DspRev = NoDSP; 5121 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5122 5123 for (std::vector<std::string>::iterator it = Features.begin(), 5124 ie = Features.end(); it != ie; ++it) { 5125 if (*it == "+single-float") 5126 IsSingleFloat = true; 5127 else if (*it == "+soft-float") 5128 FloatABI = SoftFloat; 5129 else if (*it == "+mips16") 5130 IsMips16 = true; 5131 else if (*it == "+micromips") 5132 IsMicromips = true; 5133 else if (*it == "+dsp") 5134 DspRev = std::max(DspRev, DSP1); 5135 else if (*it == "+dspr2") 5136 DspRev = std::max(DspRev, DSP2); 5137 else if (*it == "+msa") 5138 HasMSA = true; 5139 else if (*it == "+fp64") 5140 HasFP64 = true; 5141 else if (*it == "-fp64") 5142 HasFP64 = false; 5143 else if (*it == "+nan2008") 5144 IsNan2008 = true; 5145 } 5146 5147 // Remove front-end specific options. 5148 std::vector<std::string>::iterator it = 5149 std::find(Features.begin(), Features.end(), "+soft-float"); 5150 if (it != Features.end()) 5151 Features.erase(it); 5152 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5153 if (it != Features.end()) 5154 Features.erase(it); 5155 5156 setDescriptionString(); 5157 5158 return true; 5159 } 5160 5161 int getEHDataRegisterNumber(unsigned RegNo) const override { 5162 if (RegNo == 0) return 4; 5163 if (RegNo == 1) return 5; 5164 return -1; 5165 } 5166 }; 5167 5168 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5169 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5170 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5171 ALL_LANGUAGES }, 5172 #include "clang/Basic/BuiltinsMips.def" 5173 }; 5174 5175 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5176 public: 5177 Mips32TargetInfoBase(const llvm::Triple &Triple) 5178 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5179 SizeType = UnsignedInt; 5180 PtrDiffType = SignedInt; 5181 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5182 } 5183 bool setABI(const std::string &Name) override { 5184 if ((Name == "o32") || (Name == "eabi")) { 5185 ABI = Name; 5186 return true; 5187 } else if (Name == "32") { 5188 ABI = "o32"; 5189 return true; 5190 } else 5191 return false; 5192 } 5193 void getTargetDefines(const LangOptions &Opts, 5194 MacroBuilder &Builder) const override { 5195 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5196 5197 Builder.defineMacro("__mips", "32"); 5198 5199 if (ABI == "o32") { 5200 Builder.defineMacro("__mips_o32"); 5201 Builder.defineMacro("_ABIO32", "1"); 5202 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5203 } 5204 else if (ABI == "eabi") 5205 Builder.defineMacro("__mips_eabi"); 5206 else 5207 llvm_unreachable("Invalid ABI for Mips32."); 5208 } 5209 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5210 unsigned &NumAliases) const override { 5211 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5212 { { "at" }, "$1" }, 5213 { { "v0" }, "$2" }, 5214 { { "v1" }, "$3" }, 5215 { { "a0" }, "$4" }, 5216 { { "a1" }, "$5" }, 5217 { { "a2" }, "$6" }, 5218 { { "a3" }, "$7" }, 5219 { { "t0" }, "$8" }, 5220 { { "t1" }, "$9" }, 5221 { { "t2" }, "$10" }, 5222 { { "t3" }, "$11" }, 5223 { { "t4" }, "$12" }, 5224 { { "t5" }, "$13" }, 5225 { { "t6" }, "$14" }, 5226 { { "t7" }, "$15" }, 5227 { { "s0" }, "$16" }, 5228 { { "s1" }, "$17" }, 5229 { { "s2" }, "$18" }, 5230 { { "s3" }, "$19" }, 5231 { { "s4" }, "$20" }, 5232 { { "s5" }, "$21" }, 5233 { { "s6" }, "$22" }, 5234 { { "s7" }, "$23" }, 5235 { { "t8" }, "$24" }, 5236 { { "t9" }, "$25" }, 5237 { { "k0" }, "$26" }, 5238 { { "k1" }, "$27" }, 5239 { { "gp" }, "$28" }, 5240 { { "sp","$sp" }, "$29" }, 5241 { { "fp","$fp" }, "$30" }, 5242 { { "ra" }, "$31" } 5243 }; 5244 Aliases = GCCRegAliases; 5245 NumAliases = llvm::array_lengthof(GCCRegAliases); 5246 } 5247 }; 5248 5249 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5250 void setDescriptionString() override { 5251 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5252 } 5253 5254 public: 5255 Mips32EBTargetInfo(const llvm::Triple &Triple) 5256 : Mips32TargetInfoBase(Triple) { 5257 } 5258 void getTargetDefines(const LangOptions &Opts, 5259 MacroBuilder &Builder) const override { 5260 DefineStd(Builder, "MIPSEB", Opts); 5261 Builder.defineMacro("_MIPSEB"); 5262 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5263 } 5264 }; 5265 5266 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5267 void setDescriptionString() override { 5268 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5269 } 5270 5271 public: 5272 Mips32ELTargetInfo(const llvm::Triple &Triple) 5273 : Mips32TargetInfoBase(Triple) { 5274 BigEndian = false; 5275 } 5276 void getTargetDefines(const LangOptions &Opts, 5277 MacroBuilder &Builder) const override { 5278 DefineStd(Builder, "MIPSEL", Opts); 5279 Builder.defineMacro("_MIPSEL"); 5280 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5281 } 5282 }; 5283 5284 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5285 public: 5286 Mips64TargetInfoBase(const llvm::Triple &Triple) 5287 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5288 LongWidth = LongAlign = 64; 5289 PointerWidth = PointerAlign = 64; 5290 LongDoubleWidth = LongDoubleAlign = 128; 5291 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5292 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5293 LongDoubleWidth = LongDoubleAlign = 64; 5294 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5295 } 5296 SuitableAlign = 128; 5297 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5298 } 5299 bool setABI(const std::string &Name) override { 5300 if (Name == "n32") { 5301 LongWidth = LongAlign = 32; 5302 PointerWidth = PointerAlign = 32; 5303 ABI = Name; 5304 return true; 5305 } else if (Name == "n64") { 5306 ABI = Name; 5307 return true; 5308 } else if (Name == "64") { 5309 ABI = "n64"; 5310 return true; 5311 } else 5312 return false; 5313 } 5314 void getTargetDefines(const LangOptions &Opts, 5315 MacroBuilder &Builder) const override { 5316 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5317 5318 Builder.defineMacro("__mips", "64"); 5319 Builder.defineMacro("__mips64"); 5320 Builder.defineMacro("__mips64__"); 5321 5322 if (ABI == "n32") { 5323 Builder.defineMacro("__mips_n32"); 5324 Builder.defineMacro("_ABIN32", "2"); 5325 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5326 } 5327 else if (ABI == "n64") { 5328 Builder.defineMacro("__mips_n64"); 5329 Builder.defineMacro("_ABI64", "3"); 5330 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5331 } 5332 else 5333 llvm_unreachable("Invalid ABI for Mips64."); 5334 } 5335 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5336 unsigned &NumAliases) const override { 5337 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5338 { { "at" }, "$1" }, 5339 { { "v0" }, "$2" }, 5340 { { "v1" }, "$3" }, 5341 { { "a0" }, "$4" }, 5342 { { "a1" }, "$5" }, 5343 { { "a2" }, "$6" }, 5344 { { "a3" }, "$7" }, 5345 { { "a4" }, "$8" }, 5346 { { "a5" }, "$9" }, 5347 { { "a6" }, "$10" }, 5348 { { "a7" }, "$11" }, 5349 { { "t0" }, "$12" }, 5350 { { "t1" }, "$13" }, 5351 { { "t2" }, "$14" }, 5352 { { "t3" }, "$15" }, 5353 { { "s0" }, "$16" }, 5354 { { "s1" }, "$17" }, 5355 { { "s2" }, "$18" }, 5356 { { "s3" }, "$19" }, 5357 { { "s4" }, "$20" }, 5358 { { "s5" }, "$21" }, 5359 { { "s6" }, "$22" }, 5360 { { "s7" }, "$23" }, 5361 { { "t8" }, "$24" }, 5362 { { "t9" }, "$25" }, 5363 { { "k0" }, "$26" }, 5364 { { "k1" }, "$27" }, 5365 { { "gp" }, "$28" }, 5366 { { "sp","$sp" }, "$29" }, 5367 { { "fp","$fp" }, "$30" }, 5368 { { "ra" }, "$31" } 5369 }; 5370 Aliases = GCCRegAliases; 5371 NumAliases = llvm::array_lengthof(GCCRegAliases); 5372 } 5373 }; 5374 5375 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5376 void setDescriptionString() override { 5377 if (ABI == "n32") 5378 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5379 else 5380 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5381 5382 } 5383 5384 public: 5385 Mips64EBTargetInfo(const llvm::Triple &Triple) 5386 : Mips64TargetInfoBase(Triple) {} 5387 void getTargetDefines(const LangOptions &Opts, 5388 MacroBuilder &Builder) const override { 5389 DefineStd(Builder, "MIPSEB", Opts); 5390 Builder.defineMacro("_MIPSEB"); 5391 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5392 } 5393 }; 5394 5395 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5396 void setDescriptionString() override { 5397 if (ABI == "n32") 5398 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5399 else 5400 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5401 } 5402 public: 5403 Mips64ELTargetInfo(const llvm::Triple &Triple) 5404 : Mips64TargetInfoBase(Triple) { 5405 // Default ABI is n64. 5406 BigEndian = false; 5407 } 5408 void getTargetDefines(const LangOptions &Opts, 5409 MacroBuilder &Builder) const override { 5410 DefineStd(Builder, "MIPSEL", Opts); 5411 Builder.defineMacro("_MIPSEL"); 5412 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5413 } 5414 }; 5415 } // end anonymous namespace. 5416 5417 namespace { 5418 class PNaClTargetInfo : public TargetInfo { 5419 public: 5420 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5421 BigEndian = false; 5422 this->UserLabelPrefix = ""; 5423 this->LongAlign = 32; 5424 this->LongWidth = 32; 5425 this->PointerAlign = 32; 5426 this->PointerWidth = 32; 5427 this->IntMaxType = TargetInfo::SignedLongLong; 5428 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5429 this->Int64Type = TargetInfo::SignedLongLong; 5430 this->DoubleAlign = 64; 5431 this->LongDoubleWidth = 64; 5432 this->LongDoubleAlign = 64; 5433 this->SizeType = TargetInfo::UnsignedInt; 5434 this->PtrDiffType = TargetInfo::SignedInt; 5435 this->IntPtrType = TargetInfo::SignedInt; 5436 this->RegParmMax = 0; // Disallow regparm 5437 } 5438 5439 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5440 } 5441 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5442 Builder.defineMacro("__le32__"); 5443 Builder.defineMacro("__pnacl__"); 5444 } 5445 void getTargetDefines(const LangOptions &Opts, 5446 MacroBuilder &Builder) const override { 5447 getArchDefines(Opts, Builder); 5448 } 5449 bool hasFeature(StringRef Feature) const override { 5450 return Feature == "pnacl"; 5451 } 5452 void getTargetBuiltins(const Builtin::Info *&Records, 5453 unsigned &NumRecords) const override { 5454 } 5455 BuiltinVaListKind getBuiltinVaListKind() const override { 5456 return TargetInfo::PNaClABIBuiltinVaList; 5457 } 5458 void getGCCRegNames(const char * const *&Names, 5459 unsigned &NumNames) const override; 5460 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5461 unsigned &NumAliases) const override; 5462 bool validateAsmConstraint(const char *&Name, 5463 TargetInfo::ConstraintInfo &Info) const override { 5464 return false; 5465 } 5466 5467 const char *getClobbers() const override { 5468 return ""; 5469 } 5470 }; 5471 5472 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5473 unsigned &NumNames) const { 5474 Names = NULL; 5475 NumNames = 0; 5476 } 5477 5478 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5479 unsigned &NumAliases) const { 5480 Aliases = NULL; 5481 NumAliases = 0; 5482 } 5483 } // end anonymous namespace. 5484 5485 namespace { 5486 static const unsigned SPIRAddrSpaceMap[] = { 5487 1, // opencl_global 5488 3, // opencl_local 5489 2, // opencl_constant 5490 0, // cuda_device 5491 0, // cuda_constant 5492 0 // cuda_shared 5493 }; 5494 class SPIRTargetInfo : public TargetInfo { 5495 public: 5496 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5497 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5498 "SPIR target must use unknown OS"); 5499 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5500 "SPIR target must use unknown environment type"); 5501 BigEndian = false; 5502 TLSSupported = false; 5503 LongWidth = LongAlign = 64; 5504 AddrSpaceMap = &SPIRAddrSpaceMap; 5505 UseAddrSpaceMapMangling = true; 5506 // Define available target features 5507 // These must be defined in sorted order! 5508 NoAsmVariants = true; 5509 } 5510 void getTargetDefines(const LangOptions &Opts, 5511 MacroBuilder &Builder) const override { 5512 DefineStd(Builder, "SPIR", Opts); 5513 } 5514 bool hasFeature(StringRef Feature) const override { 5515 return Feature == "spir"; 5516 } 5517 5518 void getTargetBuiltins(const Builtin::Info *&Records, 5519 unsigned &NumRecords) const override {} 5520 const char *getClobbers() const override { 5521 return ""; 5522 } 5523 void getGCCRegNames(const char * const *&Names, 5524 unsigned &NumNames) const override {} 5525 bool validateAsmConstraint(const char *&Name, 5526 TargetInfo::ConstraintInfo &info) const override { 5527 return true; 5528 } 5529 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5530 unsigned &NumAliases) const override {} 5531 BuiltinVaListKind getBuiltinVaListKind() const override { 5532 return TargetInfo::VoidPtrBuiltinVaList; 5533 } 5534 }; 5535 5536 5537 class SPIR32TargetInfo : public SPIRTargetInfo { 5538 public: 5539 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5540 PointerWidth = PointerAlign = 32; 5541 SizeType = TargetInfo::UnsignedInt; 5542 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5543 DescriptionString 5544 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5545 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5546 } 5547 void getTargetDefines(const LangOptions &Opts, 5548 MacroBuilder &Builder) const override { 5549 DefineStd(Builder, "SPIR32", Opts); 5550 } 5551 }; 5552 5553 class SPIR64TargetInfo : public SPIRTargetInfo { 5554 public: 5555 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5556 PointerWidth = PointerAlign = 64; 5557 SizeType = TargetInfo::UnsignedLong; 5558 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5559 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5560 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5561 } 5562 void getTargetDefines(const LangOptions &Opts, 5563 MacroBuilder &Builder) const override { 5564 DefineStd(Builder, "SPIR64", Opts); 5565 } 5566 }; 5567 } 5568 5569 namespace { 5570 class XCoreTargetInfo : public TargetInfo { 5571 static const Builtin::Info BuiltinInfo[]; 5572 public: 5573 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5574 BigEndian = false; 5575 NoAsmVariants = true; 5576 LongLongAlign = 32; 5577 SuitableAlign = 32; 5578 DoubleAlign = LongDoubleAlign = 32; 5579 SizeType = UnsignedInt; 5580 PtrDiffType = SignedInt; 5581 IntPtrType = SignedInt; 5582 WCharType = UnsignedChar; 5583 WIntType = UnsignedInt; 5584 UseZeroLengthBitfieldAlignment = true; 5585 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5586 "-f64:32-a:0:32-n32"; 5587 } 5588 void getTargetDefines(const LangOptions &Opts, 5589 MacroBuilder &Builder) const override { 5590 Builder.defineMacro("__XS1B__"); 5591 } 5592 void getTargetBuiltins(const Builtin::Info *&Records, 5593 unsigned &NumRecords) const override { 5594 Records = BuiltinInfo; 5595 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5596 } 5597 BuiltinVaListKind getBuiltinVaListKind() const override { 5598 return TargetInfo::VoidPtrBuiltinVaList; 5599 } 5600 const char *getClobbers() const override { 5601 return ""; 5602 } 5603 void getGCCRegNames(const char * const *&Names, 5604 unsigned &NumNames) const override { 5605 static const char * const GCCRegNames[] = { 5606 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5607 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5608 }; 5609 Names = GCCRegNames; 5610 NumNames = llvm::array_lengthof(GCCRegNames); 5611 } 5612 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5613 unsigned &NumAliases) const override { 5614 Aliases = NULL; 5615 NumAliases = 0; 5616 } 5617 bool validateAsmConstraint(const char *&Name, 5618 TargetInfo::ConstraintInfo &Info) const override { 5619 return false; 5620 } 5621 int getEHDataRegisterNumber(unsigned RegNo) const override { 5622 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5623 return (RegNo < 2)? RegNo : -1; 5624 } 5625 }; 5626 5627 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5628 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5629 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5630 ALL_LANGUAGES }, 5631 #include "clang/Basic/BuiltinsXCore.def" 5632 }; 5633 } // end anonymous namespace. 5634 5635 5636 //===----------------------------------------------------------------------===// 5637 // Driver code 5638 //===----------------------------------------------------------------------===// 5639 5640 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5641 llvm::Triple::OSType os = Triple.getOS(); 5642 5643 switch (Triple.getArch()) { 5644 default: 5645 return NULL; 5646 5647 case llvm::Triple::xcore: 5648 return new XCoreTargetInfo(Triple); 5649 5650 case llvm::Triple::hexagon: 5651 return new HexagonTargetInfo(Triple); 5652 5653 case llvm::Triple::aarch64: 5654 switch (os) { 5655 case llvm::Triple::Linux: 5656 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 5657 case llvm::Triple::NetBSD: 5658 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 5659 default: 5660 return new AArch64leTargetInfo(Triple); 5661 } 5662 5663 case llvm::Triple::aarch64_be: 5664 switch (os) { 5665 case llvm::Triple::Linux: 5666 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 5667 case llvm::Triple::NetBSD: 5668 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 5669 default: 5670 return new AArch64beTargetInfo(Triple); 5671 } 5672 5673 case llvm::Triple::arm: 5674 case llvm::Triple::thumb: 5675 if (Triple.isOSBinFormatMachO()) 5676 return new DarwinARMTargetInfo(Triple); 5677 5678 switch (os) { 5679 case llvm::Triple::Linux: 5680 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5681 case llvm::Triple::FreeBSD: 5682 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5683 case llvm::Triple::NetBSD: 5684 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5685 case llvm::Triple::OpenBSD: 5686 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5687 case llvm::Triple::Bitrig: 5688 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5689 case llvm::Triple::RTEMS: 5690 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5691 case llvm::Triple::NaCl: 5692 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5693 default: 5694 return new ARMTargetInfo(Triple); 5695 } 5696 5697 case llvm::Triple::msp430: 5698 return new MSP430TargetInfo(Triple); 5699 5700 case llvm::Triple::mips: 5701 switch (os) { 5702 case llvm::Triple::Linux: 5703 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5704 case llvm::Triple::RTEMS: 5705 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5706 case llvm::Triple::FreeBSD: 5707 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5708 case llvm::Triple::NetBSD: 5709 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5710 default: 5711 return new Mips32EBTargetInfo(Triple); 5712 } 5713 5714 case llvm::Triple::mipsel: 5715 switch (os) { 5716 case llvm::Triple::Linux: 5717 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5718 case llvm::Triple::RTEMS: 5719 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5720 case llvm::Triple::FreeBSD: 5721 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5722 case llvm::Triple::NetBSD: 5723 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5724 case llvm::Triple::NaCl: 5725 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5726 default: 5727 return new Mips32ELTargetInfo(Triple); 5728 } 5729 5730 case llvm::Triple::mips64: 5731 switch (os) { 5732 case llvm::Triple::Linux: 5733 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5734 case llvm::Triple::RTEMS: 5735 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5736 case llvm::Triple::FreeBSD: 5737 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5738 case llvm::Triple::NetBSD: 5739 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5740 case llvm::Triple::OpenBSD: 5741 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5742 default: 5743 return new Mips64EBTargetInfo(Triple); 5744 } 5745 5746 case llvm::Triple::mips64el: 5747 switch (os) { 5748 case llvm::Triple::Linux: 5749 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5750 case llvm::Triple::RTEMS: 5751 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5752 case llvm::Triple::FreeBSD: 5753 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5754 case llvm::Triple::NetBSD: 5755 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5756 case llvm::Triple::OpenBSD: 5757 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5758 default: 5759 return new Mips64ELTargetInfo(Triple); 5760 } 5761 5762 case llvm::Triple::le32: 5763 switch (os) { 5764 case llvm::Triple::NaCl: 5765 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5766 default: 5767 return NULL; 5768 } 5769 5770 case llvm::Triple::ppc: 5771 if (Triple.isOSDarwin()) 5772 return new DarwinPPC32TargetInfo(Triple); 5773 switch (os) { 5774 case llvm::Triple::Linux: 5775 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5776 case llvm::Triple::FreeBSD: 5777 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5778 case llvm::Triple::NetBSD: 5779 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5780 case llvm::Triple::OpenBSD: 5781 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5782 case llvm::Triple::RTEMS: 5783 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5784 default: 5785 return new PPC32TargetInfo(Triple); 5786 } 5787 5788 case llvm::Triple::ppc64: 5789 if (Triple.isOSDarwin()) 5790 return new DarwinPPC64TargetInfo(Triple); 5791 switch (os) { 5792 case llvm::Triple::Linux: 5793 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5794 case llvm::Triple::Lv2: 5795 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5796 case llvm::Triple::FreeBSD: 5797 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5798 case llvm::Triple::NetBSD: 5799 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5800 default: 5801 return new PPC64TargetInfo(Triple); 5802 } 5803 5804 case llvm::Triple::ppc64le: 5805 switch (os) { 5806 case llvm::Triple::Linux: 5807 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5808 default: 5809 return new PPC64TargetInfo(Triple); 5810 } 5811 5812 case llvm::Triple::nvptx: 5813 return new NVPTX32TargetInfo(Triple); 5814 case llvm::Triple::nvptx64: 5815 return new NVPTX64TargetInfo(Triple); 5816 5817 case llvm::Triple::r600: 5818 return new R600TargetInfo(Triple); 5819 5820 case llvm::Triple::sparc: 5821 switch (os) { 5822 case llvm::Triple::Linux: 5823 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5824 case llvm::Triple::AuroraUX: 5825 return new AuroraUXSparcV8TargetInfo(Triple); 5826 case llvm::Triple::Solaris: 5827 return new SolarisSparcV8TargetInfo(Triple); 5828 case llvm::Triple::NetBSD: 5829 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5830 case llvm::Triple::OpenBSD: 5831 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5832 case llvm::Triple::RTEMS: 5833 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5834 default: 5835 return new SparcV8TargetInfo(Triple); 5836 } 5837 5838 case llvm::Triple::sparcv9: 5839 switch (os) { 5840 case llvm::Triple::Linux: 5841 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5842 case llvm::Triple::AuroraUX: 5843 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5844 case llvm::Triple::Solaris: 5845 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5846 case llvm::Triple::NetBSD: 5847 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5848 case llvm::Triple::OpenBSD: 5849 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5850 case llvm::Triple::FreeBSD: 5851 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5852 default: 5853 return new SparcV9TargetInfo(Triple); 5854 } 5855 5856 case llvm::Triple::systemz: 5857 switch (os) { 5858 case llvm::Triple::Linux: 5859 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5860 default: 5861 return new SystemZTargetInfo(Triple); 5862 } 5863 5864 case llvm::Triple::tce: 5865 return new TCETargetInfo(Triple); 5866 5867 case llvm::Triple::x86: 5868 if (Triple.isOSDarwin()) 5869 return new DarwinI386TargetInfo(Triple); 5870 5871 switch (os) { 5872 case llvm::Triple::AuroraUX: 5873 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5874 case llvm::Triple::Linux: 5875 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5876 case llvm::Triple::DragonFly: 5877 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5878 case llvm::Triple::NetBSD: 5879 return new NetBSDI386TargetInfo(Triple); 5880 case llvm::Triple::OpenBSD: 5881 return new OpenBSDI386TargetInfo(Triple); 5882 case llvm::Triple::Bitrig: 5883 return new BitrigI386TargetInfo(Triple); 5884 case llvm::Triple::FreeBSD: 5885 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5886 case llvm::Triple::KFreeBSD: 5887 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5888 case llvm::Triple::Minix: 5889 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5890 case llvm::Triple::Solaris: 5891 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5892 case llvm::Triple::Cygwin: 5893 return new CygwinX86_32TargetInfo(Triple); 5894 case llvm::Triple::MinGW32: 5895 return new MinGWX86_32TargetInfo(Triple); 5896 case llvm::Triple::Win32: 5897 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5898 case llvm::Triple::Haiku: 5899 return new HaikuX86_32TargetInfo(Triple); 5900 case llvm::Triple::RTEMS: 5901 return new RTEMSX86_32TargetInfo(Triple); 5902 case llvm::Triple::NaCl: 5903 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5904 default: 5905 return new X86_32TargetInfo(Triple); 5906 } 5907 5908 case llvm::Triple::x86_64: 5909 if (Triple.isOSDarwin() || Triple.getObjectFormat() == llvm::Triple::MachO) 5910 return new DarwinX86_64TargetInfo(Triple); 5911 5912 switch (os) { 5913 case llvm::Triple::AuroraUX: 5914 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5915 case llvm::Triple::Linux: 5916 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5917 case llvm::Triple::DragonFly: 5918 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5919 case llvm::Triple::NetBSD: 5920 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5921 case llvm::Triple::OpenBSD: 5922 return new OpenBSDX86_64TargetInfo(Triple); 5923 case llvm::Triple::Bitrig: 5924 return new BitrigX86_64TargetInfo(Triple); 5925 case llvm::Triple::FreeBSD: 5926 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5927 case llvm::Triple::KFreeBSD: 5928 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5929 case llvm::Triple::Solaris: 5930 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5931 case llvm::Triple::MinGW32: 5932 return new MinGWX86_64TargetInfo(Triple); 5933 case llvm::Triple::Win32: // This is what Triple.h supports now. 5934 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5935 case llvm::Triple::NaCl: 5936 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5937 default: 5938 return new X86_64TargetInfo(Triple); 5939 } 5940 5941 case llvm::Triple::spir: { 5942 if (Triple.getOS() != llvm::Triple::UnknownOS || 5943 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5944 return NULL; 5945 return new SPIR32TargetInfo(Triple); 5946 } 5947 case llvm::Triple::spir64: { 5948 if (Triple.getOS() != llvm::Triple::UnknownOS || 5949 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5950 return NULL; 5951 return new SPIR64TargetInfo(Triple); 5952 } 5953 } 5954 } 5955 5956 /// CreateTargetInfo - Return the target info object for the specified target 5957 /// triple. 5958 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5959 TargetOptions *Opts) { 5960 llvm::Triple Triple(Opts->Triple); 5961 5962 // Construct the target 5963 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 5964 if (!Target) { 5965 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5966 return 0; 5967 } 5968 Target->setTargetOpts(Opts); 5969 5970 // Set the target CPU if specified. 5971 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5972 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5973 return 0; 5974 } 5975 5976 // Set the target ABI if specified. 5977 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5978 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5979 return 0; 5980 } 5981 5982 // Set the fp math unit. 5983 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5984 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5985 return 0; 5986 } 5987 5988 // Compute the default target features, we need the target to handle this 5989 // because features may have dependencies on one another. 5990 llvm::StringMap<bool> Features; 5991 Target->getDefaultFeatures(Features); 5992 5993 // Apply the user specified deltas. 5994 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5995 I < N; ++I) { 5996 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5997 // Apply the feature via the target. 5998 bool Enabled = Name[0] == '+'; 5999 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6000 } 6001 6002 // Add the features to the compile options. 6003 // 6004 // FIXME: If we are completely confident that we have the right set, we only 6005 // need to pass the minuses. 6006 Opts->Features.clear(); 6007 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6008 ie = Features.end(); it != ie; ++it) 6009 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6010 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6011 return 0; 6012 6013 return Target.release(); 6014 } 6015