1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 template<typename Target> 188 class DarwinTargetInfo : public OSTargetInfo<Target> { 189 protected: 190 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 191 MacroBuilder &Builder) const override { 192 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 193 this->PlatformMinVersion); 194 } 195 196 public: 197 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 198 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 199 this->MCountName = "\01mcount"; 200 } 201 202 std::string isValidSectionSpecifier(StringRef SR) const override { 203 // Let MCSectionMachO validate this. 204 StringRef Segment, Section; 205 unsigned TAA, StubSize; 206 bool HasTAA; 207 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 208 TAA, HasTAA, StubSize); 209 } 210 211 const char *getStaticInitSectionSpecifier() const override { 212 // FIXME: We should return 0 when building kexts. 213 return "__TEXT,__StaticInit,regular,pure_instructions"; 214 } 215 216 /// Darwin does not support protected visibility. Darwin's "default" 217 /// is very similar to ELF's "protected"; Darwin requires a "weak" 218 /// attribute on declarations that can be dynamically replaced. 219 bool hasProtectedVisibility() const override { 220 return false; 221 } 222 }; 223 224 225 // DragonFlyBSD Target 226 template<typename Target> 227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 228 protected: 229 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 230 MacroBuilder &Builder) const override { 231 // DragonFly defines; list based off of gcc output 232 Builder.defineMacro("__DragonFly__"); 233 Builder.defineMacro("__DragonFly_cc_version", "100001"); 234 Builder.defineMacro("__ELF__"); 235 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 236 Builder.defineMacro("__tune_i386__"); 237 DefineStd(Builder, "unix", Opts); 238 } 239 public: 240 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 241 : OSTargetInfo<Target>(Triple) { 242 this->UserLabelPrefix = ""; 243 244 switch (Triple.getArch()) { 245 default: 246 case llvm::Triple::x86: 247 case llvm::Triple::x86_64: 248 this->MCountName = ".mcount"; 249 break; 250 } 251 } 252 }; 253 254 // FreeBSD Target 255 template<typename Target> 256 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 257 protected: 258 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 259 MacroBuilder &Builder) const override { 260 // FreeBSD defines; list based off of gcc output 261 262 unsigned Release = Triple.getOSMajorVersion(); 263 if (Release == 0U) 264 Release = 8; 265 266 Builder.defineMacro("__FreeBSD__", Twine(Release)); 267 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 268 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 269 DefineStd(Builder, "unix", Opts); 270 Builder.defineMacro("__ELF__"); 271 272 // On FreeBSD, wchar_t contains the number of the code point as 273 // used by the character set of the locale. These character sets are 274 // not necessarily a superset of ASCII. 275 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 276 } 277 public: 278 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 279 this->UserLabelPrefix = ""; 280 281 switch (Triple.getArch()) { 282 default: 283 case llvm::Triple::x86: 284 case llvm::Triple::x86_64: 285 this->MCountName = ".mcount"; 286 break; 287 case llvm::Triple::mips: 288 case llvm::Triple::mipsel: 289 case llvm::Triple::ppc: 290 case llvm::Triple::ppc64: 291 case llvm::Triple::ppc64le: 292 this->MCountName = "_mcount"; 293 break; 294 case llvm::Triple::arm: 295 this->MCountName = "__mcount"; 296 break; 297 } 298 } 299 }; 300 301 // GNU/kFreeBSD Target 302 template<typename Target> 303 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 304 protected: 305 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 306 MacroBuilder &Builder) const override { 307 // GNU/kFreeBSD defines; list based off of gcc output 308 309 DefineStd(Builder, "unix", Opts); 310 Builder.defineMacro("__FreeBSD_kernel__"); 311 Builder.defineMacro("__GLIBC__"); 312 Builder.defineMacro("__ELF__"); 313 if (Opts.POSIXThreads) 314 Builder.defineMacro("_REENTRANT"); 315 if (Opts.CPlusPlus) 316 Builder.defineMacro("_GNU_SOURCE"); 317 } 318 public: 319 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 320 this->UserLabelPrefix = ""; 321 } 322 }; 323 324 // Minix Target 325 template<typename Target> 326 class MinixTargetInfo : public OSTargetInfo<Target> { 327 protected: 328 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 329 MacroBuilder &Builder) const override { 330 // Minix defines 331 332 Builder.defineMacro("__minix", "3"); 333 Builder.defineMacro("_EM_WSIZE", "4"); 334 Builder.defineMacro("_EM_PSIZE", "4"); 335 Builder.defineMacro("_EM_SSIZE", "2"); 336 Builder.defineMacro("_EM_LSIZE", "4"); 337 Builder.defineMacro("_EM_FSIZE", "4"); 338 Builder.defineMacro("_EM_DSIZE", "8"); 339 Builder.defineMacro("__ELF__"); 340 DefineStd(Builder, "unix", Opts); 341 } 342 public: 343 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 344 this->UserLabelPrefix = ""; 345 } 346 }; 347 348 // Linux target 349 template<typename Target> 350 class LinuxTargetInfo : public OSTargetInfo<Target> { 351 protected: 352 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 353 MacroBuilder &Builder) const override { 354 // Linux defines; list based off of gcc output 355 DefineStd(Builder, "unix", Opts); 356 DefineStd(Builder, "linux", Opts); 357 Builder.defineMacro("__gnu_linux__"); 358 Builder.defineMacro("__ELF__"); 359 if (Triple.getEnvironment() == llvm::Triple::Android) 360 Builder.defineMacro("__ANDROID__", "1"); 361 if (Opts.POSIXThreads) 362 Builder.defineMacro("_REENTRANT"); 363 if (Opts.CPlusPlus) 364 Builder.defineMacro("_GNU_SOURCE"); 365 } 366 public: 367 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 368 this->UserLabelPrefix = ""; 369 this->WIntType = TargetInfo::UnsignedInt; 370 371 switch (Triple.getArch()) { 372 default: 373 break; 374 case llvm::Triple::ppc: 375 case llvm::Triple::ppc64: 376 case llvm::Triple::ppc64le: 377 this->MCountName = "_mcount"; 378 break; 379 } 380 } 381 382 const char *getStaticInitSectionSpecifier() const override { 383 return ".text.startup"; 384 } 385 }; 386 387 // NetBSD Target 388 template<typename Target> 389 class NetBSDTargetInfo : public OSTargetInfo<Target> { 390 protected: 391 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 392 MacroBuilder &Builder) const override { 393 // NetBSD defines; list based off of gcc output 394 Builder.defineMacro("__NetBSD__"); 395 Builder.defineMacro("__unix__"); 396 Builder.defineMacro("__ELF__"); 397 if (Opts.POSIXThreads) 398 Builder.defineMacro("_POSIX_THREADS"); 399 400 switch (Triple.getArch()) { 401 default: 402 break; 403 case llvm::Triple::arm: 404 case llvm::Triple::armeb: 405 case llvm::Triple::thumb: 406 case llvm::Triple::thumbeb: 407 Builder.defineMacro("__ARM_DWARF_EH__"); 408 break; 409 } 410 } 411 public: 412 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 413 this->UserLabelPrefix = ""; 414 } 415 }; 416 417 // OpenBSD Target 418 template<typename Target> 419 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 420 protected: 421 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 422 MacroBuilder &Builder) const override { 423 // OpenBSD defines; list based off of gcc output 424 425 Builder.defineMacro("__OpenBSD__"); 426 DefineStd(Builder, "unix", Opts); 427 Builder.defineMacro("__ELF__"); 428 if (Opts.POSIXThreads) 429 Builder.defineMacro("_REENTRANT"); 430 } 431 public: 432 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 433 this->UserLabelPrefix = ""; 434 this->TLSSupported = false; 435 436 switch (Triple.getArch()) { 437 default: 438 case llvm::Triple::x86: 439 case llvm::Triple::x86_64: 440 case llvm::Triple::arm: 441 case llvm::Triple::sparc: 442 this->MCountName = "__mcount"; 443 break; 444 case llvm::Triple::mips64: 445 case llvm::Triple::mips64el: 446 case llvm::Triple::ppc: 447 case llvm::Triple::sparcv9: 448 this->MCountName = "_mcount"; 449 break; 450 } 451 } 452 }; 453 454 // Bitrig Target 455 template<typename Target> 456 class BitrigTargetInfo : public OSTargetInfo<Target> { 457 protected: 458 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 459 MacroBuilder &Builder) const override { 460 // Bitrig defines; list based off of gcc output 461 462 Builder.defineMacro("__Bitrig__"); 463 DefineStd(Builder, "unix", Opts); 464 Builder.defineMacro("__ELF__"); 465 if (Opts.POSIXThreads) 466 Builder.defineMacro("_REENTRANT"); 467 } 468 public: 469 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->MCountName = "__mcount"; 472 } 473 }; 474 475 // PSP Target 476 template<typename Target> 477 class PSPTargetInfo : public OSTargetInfo<Target> { 478 protected: 479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 480 MacroBuilder &Builder) const override { 481 // PSP defines; list based on the output of the pspdev gcc toolchain. 482 Builder.defineMacro("PSP"); 483 Builder.defineMacro("_PSP"); 484 Builder.defineMacro("__psp__"); 485 Builder.defineMacro("__ELF__"); 486 } 487 public: 488 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 489 this->UserLabelPrefix = ""; 490 } 491 }; 492 493 // PS3 PPU Target 494 template<typename Target> 495 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 496 protected: 497 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 498 MacroBuilder &Builder) const override { 499 // PS3 PPU defines. 500 Builder.defineMacro("__PPC__"); 501 Builder.defineMacro("__PPU__"); 502 Builder.defineMacro("__CELLOS_LV2__"); 503 Builder.defineMacro("__ELF__"); 504 Builder.defineMacro("__LP32__"); 505 Builder.defineMacro("_ARCH_PPC64"); 506 Builder.defineMacro("__powerpc64__"); 507 } 508 public: 509 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 510 this->UserLabelPrefix = ""; 511 this->LongWidth = this->LongAlign = 32; 512 this->PointerWidth = this->PointerAlign = 32; 513 this->IntMaxType = TargetInfo::SignedLongLong; 514 this->Int64Type = TargetInfo::SignedLongLong; 515 this->SizeType = TargetInfo::UnsignedInt; 516 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 517 } 518 }; 519 520 // Solaris target 521 template<typename Target> 522 class SolarisTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 DefineStd(Builder, "sun", Opts); 527 DefineStd(Builder, "unix", Opts); 528 Builder.defineMacro("__ELF__"); 529 Builder.defineMacro("__svr4__"); 530 Builder.defineMacro("__SVR4"); 531 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 532 // newer, but to 500 for everything else. feature_test.h has a check to 533 // ensure that you are not using C99 with an old version of X/Open or C89 534 // with a new version. 535 if (Opts.C99) 536 Builder.defineMacro("_XOPEN_SOURCE", "600"); 537 else 538 Builder.defineMacro("_XOPEN_SOURCE", "500"); 539 if (Opts.CPlusPlus) 540 Builder.defineMacro("__C99FEATURES__"); 541 Builder.defineMacro("_LARGEFILE_SOURCE"); 542 Builder.defineMacro("_LARGEFILE64_SOURCE"); 543 Builder.defineMacro("__EXTENSIONS__"); 544 Builder.defineMacro("_REENTRANT"); 545 } 546 public: 547 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 548 this->UserLabelPrefix = ""; 549 this->WCharType = this->SignedInt; 550 // FIXME: WIntType should be SignedLong 551 } 552 }; 553 554 // Windows target 555 template<typename Target> 556 class WindowsTargetInfo : public OSTargetInfo<Target> { 557 protected: 558 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 559 MacroBuilder &Builder) const override { 560 Builder.defineMacro("_WIN32"); 561 } 562 void getVisualStudioDefines(const LangOptions &Opts, 563 MacroBuilder &Builder) const { 564 if (Opts.CPlusPlus) { 565 if (Opts.RTTIData) 566 Builder.defineMacro("_CPPRTTI"); 567 568 if (Opts.Exceptions) 569 Builder.defineMacro("_CPPUNWIND"); 570 } 571 572 if (!Opts.CharIsSigned) 573 Builder.defineMacro("_CHAR_UNSIGNED"); 574 575 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 576 // but it works for now. 577 if (Opts.POSIXThreads) 578 Builder.defineMacro("_MT"); 579 580 if (Opts.MSCompatibilityVersion) { 581 Builder.defineMacro("_MSC_VER", 582 Twine(Opts.MSCompatibilityVersion / 100000)); 583 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 584 // FIXME We cannot encode the revision information into 32-bits 585 Builder.defineMacro("_MSC_BUILD", Twine(1)); 586 } 587 588 if (Opts.MicrosoftExt) { 589 Builder.defineMacro("_MSC_EXTENSIONS"); 590 591 if (Opts.CPlusPlus11) { 592 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 593 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 594 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 595 } 596 } 597 598 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 599 } 600 601 public: 602 WindowsTargetInfo(const llvm::Triple &Triple) 603 : OSTargetInfo<Target>(Triple) {} 604 }; 605 606 template <typename Target> 607 class NaClTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 if (Opts.POSIXThreads) 612 Builder.defineMacro("_REENTRANT"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("_GNU_SOURCE"); 615 616 DefineStd(Builder, "unix", Opts); 617 Builder.defineMacro("__ELF__"); 618 Builder.defineMacro("__native_client__"); 619 } 620 621 public: 622 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 623 this->UserLabelPrefix = ""; 624 this->LongAlign = 32; 625 this->LongWidth = 32; 626 this->PointerAlign = 32; 627 this->PointerWidth = 32; 628 this->IntMaxType = TargetInfo::SignedLongLong; 629 this->Int64Type = TargetInfo::SignedLongLong; 630 this->DoubleAlign = 64; 631 this->LongDoubleWidth = 64; 632 this->LongDoubleAlign = 64; 633 this->LongLongWidth = 64; 634 this->LongLongAlign = 64; 635 this->SizeType = TargetInfo::UnsignedInt; 636 this->PtrDiffType = TargetInfo::SignedInt; 637 this->IntPtrType = TargetInfo::SignedInt; 638 // RegParmMax is inherited from the underlying architecture 639 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 640 if (Triple.getArch() == llvm::Triple::arm) { 641 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 642 } else if (Triple.getArch() == llvm::Triple::x86) { 643 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 644 } else if (Triple.getArch() == llvm::Triple::x86_64) { 645 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 646 } else if (Triple.getArch() == llvm::Triple::mipsel) { 647 // Handled on mips' setDescriptionString. 648 } else { 649 assert(Triple.getArch() == llvm::Triple::le32); 650 this->DescriptionString = "e-p:32:32-i64:64"; 651 } 652 } 653 typename Target::CallingConvCheckResult checkCallingConvention( 654 CallingConv CC) const override { 655 return CC == CC_PnaclCall ? Target::CCCR_OK : 656 Target::checkCallingConvention(CC); 657 } 658 }; 659 } // end anonymous namespace. 660 661 //===----------------------------------------------------------------------===// 662 // Specific target implementations. 663 //===----------------------------------------------------------------------===// 664 665 namespace { 666 // PPC abstract base class 667 class PPCTargetInfo : public TargetInfo { 668 static const Builtin::Info BuiltinInfo[]; 669 static const char * const GCCRegNames[]; 670 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 671 std::string CPU; 672 673 // Target cpu features. 674 bool HasVSX; 675 bool HasP8Vector; 676 677 protected: 678 std::string ABI; 679 680 public: 681 PPCTargetInfo(const llvm::Triple &Triple) 682 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) { 683 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 684 LongDoubleWidth = LongDoubleAlign = 128; 685 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 686 } 687 688 /// \brief Flags for architecture specific defines. 689 typedef enum { 690 ArchDefineNone = 0, 691 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 692 ArchDefinePpcgr = 1 << 1, 693 ArchDefinePpcsq = 1 << 2, 694 ArchDefine440 = 1 << 3, 695 ArchDefine603 = 1 << 4, 696 ArchDefine604 = 1 << 5, 697 ArchDefinePwr4 = 1 << 6, 698 ArchDefinePwr5 = 1 << 7, 699 ArchDefinePwr5x = 1 << 8, 700 ArchDefinePwr6 = 1 << 9, 701 ArchDefinePwr6x = 1 << 10, 702 ArchDefinePwr7 = 1 << 11, 703 ArchDefinePwr8 = 1 << 12, 704 ArchDefineA2 = 1 << 13, 705 ArchDefineA2q = 1 << 14 706 } ArchDefineTypes; 707 708 // Note: GCC recognizes the following additional cpus: 709 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 710 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 711 // titan, rs64. 712 bool setCPU(const std::string &Name) override { 713 bool CPUKnown = llvm::StringSwitch<bool>(Name) 714 .Case("generic", true) 715 .Case("440", true) 716 .Case("450", true) 717 .Case("601", true) 718 .Case("602", true) 719 .Case("603", true) 720 .Case("603e", true) 721 .Case("603ev", true) 722 .Case("604", true) 723 .Case("604e", true) 724 .Case("620", true) 725 .Case("630", true) 726 .Case("g3", true) 727 .Case("7400", true) 728 .Case("g4", true) 729 .Case("7450", true) 730 .Case("g4+", true) 731 .Case("750", true) 732 .Case("970", true) 733 .Case("g5", true) 734 .Case("a2", true) 735 .Case("a2q", true) 736 .Case("e500mc", true) 737 .Case("e5500", true) 738 .Case("power3", true) 739 .Case("pwr3", true) 740 .Case("power4", true) 741 .Case("pwr4", true) 742 .Case("power5", true) 743 .Case("pwr5", true) 744 .Case("power5x", true) 745 .Case("pwr5x", true) 746 .Case("power6", true) 747 .Case("pwr6", true) 748 .Case("power6x", true) 749 .Case("pwr6x", true) 750 .Case("power7", true) 751 .Case("pwr7", true) 752 .Case("power8", true) 753 .Case("pwr8", true) 754 .Case("powerpc", true) 755 .Case("ppc", true) 756 .Case("powerpc64", true) 757 .Case("ppc64", true) 758 .Case("powerpc64le", true) 759 .Case("ppc64le", true) 760 .Default(false); 761 762 if (CPUKnown) 763 CPU = Name; 764 765 return CPUKnown; 766 } 767 768 769 StringRef getABI() const override { return ABI; } 770 771 void getTargetBuiltins(const Builtin::Info *&Records, 772 unsigned &NumRecords) const override { 773 Records = BuiltinInfo; 774 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 775 } 776 777 bool isCLZForZeroUndef() const override { return false; } 778 779 void getTargetDefines(const LangOptions &Opts, 780 MacroBuilder &Builder) const override; 781 782 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 783 784 bool handleTargetFeatures(std::vector<std::string> &Features, 785 DiagnosticsEngine &Diags) override; 786 bool hasFeature(StringRef Feature) const override; 787 788 void getGCCRegNames(const char * const *&Names, 789 unsigned &NumNames) const override; 790 void getGCCRegAliases(const GCCRegAlias *&Aliases, 791 unsigned &NumAliases) const override; 792 bool validateAsmConstraint(const char *&Name, 793 TargetInfo::ConstraintInfo &Info) const override { 794 switch (*Name) { 795 default: return false; 796 case 'O': // Zero 797 break; 798 case 'b': // Base register 799 case 'f': // Floating point register 800 Info.setAllowsRegister(); 801 break; 802 // FIXME: The following are added to allow parsing. 803 // I just took a guess at what the actions should be. 804 // Also, is more specific checking needed? I.e. specific registers? 805 case 'd': // Floating point register (containing 64-bit value) 806 case 'v': // Altivec vector register 807 Info.setAllowsRegister(); 808 break; 809 case 'w': 810 switch (Name[1]) { 811 case 'd':// VSX vector register to hold vector double data 812 case 'f':// VSX vector register to hold vector float data 813 case 's':// VSX vector register to hold scalar float data 814 case 'a':// Any VSX register 815 case 'c':// An individual CR bit 816 break; 817 default: 818 return false; 819 } 820 Info.setAllowsRegister(); 821 Name++; // Skip over 'w'. 822 break; 823 case 'h': // `MQ', `CTR', or `LINK' register 824 case 'q': // `MQ' register 825 case 'c': // `CTR' register 826 case 'l': // `LINK' register 827 case 'x': // `CR' register (condition register) number 0 828 case 'y': // `CR' register (condition register) 829 case 'z': // `XER[CA]' carry bit (part of the XER register) 830 Info.setAllowsRegister(); 831 break; 832 case 'I': // Signed 16-bit constant 833 case 'J': // Unsigned 16-bit constant shifted left 16 bits 834 // (use `L' instead for SImode constants) 835 case 'K': // Unsigned 16-bit constant 836 case 'L': // Signed 16-bit constant shifted left 16 bits 837 case 'M': // Constant larger than 31 838 case 'N': // Exact power of 2 839 case 'P': // Constant whose negation is a signed 16-bit constant 840 case 'G': // Floating point constant that can be loaded into a 841 // register with one instruction per word 842 case 'H': // Integer/Floating point constant that can be loaded 843 // into a register using three instructions 844 break; 845 case 'm': // Memory operand. Note that on PowerPC targets, m can 846 // include addresses that update the base register. It 847 // is therefore only safe to use `m' in an asm statement 848 // if that asm statement accesses the operand exactly once. 849 // The asm statement must also use `%U<opno>' as a 850 // placeholder for the "update" flag in the corresponding 851 // load or store instruction. For example: 852 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 853 // is correct but: 854 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 855 // is not. Use es rather than m if you don't want the base 856 // register to be updated. 857 case 'e': 858 if (Name[1] != 's') 859 return false; 860 // es: A "stable" memory operand; that is, one which does not 861 // include any automodification of the base register. Unlike 862 // `m', this constraint can be used in asm statements that 863 // might access the operand several times, or that might not 864 // access it at all. 865 Info.setAllowsMemory(); 866 Name++; // Skip over 'e'. 867 break; 868 case 'Q': // Memory operand that is an offset from a register (it is 869 // usually better to use `m' or `es' in asm statements) 870 case 'Z': // Memory operand that is an indexed or indirect from a 871 // register (it is usually better to use `m' or `es' in 872 // asm statements) 873 Info.setAllowsMemory(); 874 Info.setAllowsRegister(); 875 break; 876 case 'R': // AIX TOC entry 877 case 'a': // Address operand that is an indexed or indirect from a 878 // register (`p' is preferable for asm statements) 879 case 'S': // Constant suitable as a 64-bit mask operand 880 case 'T': // Constant suitable as a 32-bit mask operand 881 case 'U': // System V Release 4 small data area reference 882 case 't': // AND masks that can be performed by two rldic{l, r} 883 // instructions 884 case 'W': // Vector constant that does not require memory 885 case 'j': // Vector constant that is all zeros. 886 break; 887 // End FIXME. 888 } 889 return true; 890 } 891 std::string convertConstraint(const char *&Constraint) const override { 892 std::string R; 893 switch (*Constraint) { 894 case 'e': 895 case 'w': 896 // Two-character constraint; add "^" hint for later parsing. 897 R = std::string("^") + std::string(Constraint, 2); 898 Constraint++; 899 break; 900 default: 901 return TargetInfo::convertConstraint(Constraint); 902 } 903 return R; 904 } 905 const char *getClobbers() const override { 906 return ""; 907 } 908 int getEHDataRegisterNumber(unsigned RegNo) const override { 909 if (RegNo == 0) return 3; 910 if (RegNo == 1) return 4; 911 return -1; 912 } 913 }; 914 915 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 916 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 917 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 918 ALL_LANGUAGES }, 919 #include "clang/Basic/BuiltinsPPC.def" 920 }; 921 922 /// handleTargetFeatures - Perform initialization based on the user 923 /// configured set of features. 924 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 925 DiagnosticsEngine &Diags) { 926 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 927 // Ignore disabled features. 928 if (Features[i][0] == '-') 929 continue; 930 931 StringRef Feature = StringRef(Features[i]).substr(1); 932 933 if (Feature == "vsx") { 934 HasVSX = true; 935 continue; 936 } 937 938 if (Feature == "power8-vector") { 939 HasP8Vector = true; 940 continue; 941 } 942 943 // TODO: Finish this list and add an assert that we've handled them 944 // all. 945 } 946 947 return true; 948 } 949 950 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 951 /// #defines that are not tied to a specific subtarget. 952 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 953 MacroBuilder &Builder) const { 954 // Target identification. 955 Builder.defineMacro("__ppc__"); 956 Builder.defineMacro("__PPC__"); 957 Builder.defineMacro("_ARCH_PPC"); 958 Builder.defineMacro("__powerpc__"); 959 Builder.defineMacro("__POWERPC__"); 960 if (PointerWidth == 64) { 961 Builder.defineMacro("_ARCH_PPC64"); 962 Builder.defineMacro("__powerpc64__"); 963 Builder.defineMacro("__ppc64__"); 964 Builder.defineMacro("__PPC64__"); 965 } 966 967 // Target properties. 968 if (getTriple().getArch() == llvm::Triple::ppc64le) { 969 Builder.defineMacro("_LITTLE_ENDIAN"); 970 } else { 971 if (getTriple().getOS() != llvm::Triple::NetBSD && 972 getTriple().getOS() != llvm::Triple::OpenBSD) 973 Builder.defineMacro("_BIG_ENDIAN"); 974 } 975 976 // ABI options. 977 if (ABI == "elfv1") 978 Builder.defineMacro("_CALL_ELF", "1"); 979 if (ABI == "elfv2") 980 Builder.defineMacro("_CALL_ELF", "2"); 981 982 // Subtarget options. 983 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 984 Builder.defineMacro("__REGISTER_PREFIX__", ""); 985 986 // FIXME: Should be controlled by command line option. 987 if (LongDoubleWidth == 128) 988 Builder.defineMacro("__LONG_DOUBLE_128__"); 989 990 if (Opts.AltiVec) { 991 Builder.defineMacro("__VEC__", "10206"); 992 Builder.defineMacro("__ALTIVEC__"); 993 } 994 995 // CPU identification. 996 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 997 .Case("440", ArchDefineName) 998 .Case("450", ArchDefineName | ArchDefine440) 999 .Case("601", ArchDefineName) 1000 .Case("602", ArchDefineName | ArchDefinePpcgr) 1001 .Case("603", ArchDefineName | ArchDefinePpcgr) 1002 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1003 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1004 .Case("604", ArchDefineName | ArchDefinePpcgr) 1005 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1006 .Case("620", ArchDefineName | ArchDefinePpcgr) 1007 .Case("630", ArchDefineName | ArchDefinePpcgr) 1008 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1009 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1010 .Case("750", ArchDefineName | ArchDefinePpcgr) 1011 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1012 | ArchDefinePpcsq) 1013 .Case("a2", ArchDefineA2) 1014 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1015 .Case("pwr3", ArchDefinePpcgr) 1016 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1017 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1018 | ArchDefinePpcsq) 1019 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1020 | ArchDefinePpcgr | ArchDefinePpcsq) 1021 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1022 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1023 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1024 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1025 | ArchDefinePpcsq) 1026 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1027 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1028 | ArchDefinePpcgr | ArchDefinePpcsq) 1029 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1030 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1031 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1032 .Case("power3", ArchDefinePpcgr) 1033 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1034 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1035 | ArchDefinePpcsq) 1036 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1037 | ArchDefinePpcgr | ArchDefinePpcsq) 1038 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1039 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1040 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1041 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1042 | ArchDefinePpcsq) 1043 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1044 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1045 | ArchDefinePpcgr | ArchDefinePpcsq) 1046 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1047 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1048 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1049 .Default(ArchDefineNone); 1050 1051 if (defs & ArchDefineName) 1052 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1053 if (defs & ArchDefinePpcgr) 1054 Builder.defineMacro("_ARCH_PPCGR"); 1055 if (defs & ArchDefinePpcsq) 1056 Builder.defineMacro("_ARCH_PPCSQ"); 1057 if (defs & ArchDefine440) 1058 Builder.defineMacro("_ARCH_440"); 1059 if (defs & ArchDefine603) 1060 Builder.defineMacro("_ARCH_603"); 1061 if (defs & ArchDefine604) 1062 Builder.defineMacro("_ARCH_604"); 1063 if (defs & ArchDefinePwr4) 1064 Builder.defineMacro("_ARCH_PWR4"); 1065 if (defs & ArchDefinePwr5) 1066 Builder.defineMacro("_ARCH_PWR5"); 1067 if (defs & ArchDefinePwr5x) 1068 Builder.defineMacro("_ARCH_PWR5X"); 1069 if (defs & ArchDefinePwr6) 1070 Builder.defineMacro("_ARCH_PWR6"); 1071 if (defs & ArchDefinePwr6x) 1072 Builder.defineMacro("_ARCH_PWR6X"); 1073 if (defs & ArchDefinePwr7) 1074 Builder.defineMacro("_ARCH_PWR7"); 1075 if (defs & ArchDefinePwr8) 1076 Builder.defineMacro("_ARCH_PWR8"); 1077 if (defs & ArchDefineA2) 1078 Builder.defineMacro("_ARCH_A2"); 1079 if (defs & ArchDefineA2q) { 1080 Builder.defineMacro("_ARCH_A2Q"); 1081 Builder.defineMacro("_ARCH_QP"); 1082 } 1083 1084 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1085 Builder.defineMacro("__bg__"); 1086 Builder.defineMacro("__THW_BLUEGENE__"); 1087 Builder.defineMacro("__bgq__"); 1088 Builder.defineMacro("__TOS_BGQ__"); 1089 } 1090 1091 if (HasVSX) 1092 Builder.defineMacro("__VSX__"); 1093 if (HasP8Vector) 1094 Builder.defineMacro("__POWER8_VECTOR__"); 1095 1096 // FIXME: The following are not yet generated here by Clang, but are 1097 // generated by GCC: 1098 // 1099 // _SOFT_FLOAT_ 1100 // __RECIP_PRECISION__ 1101 // __APPLE_ALTIVEC__ 1102 // __RECIP__ 1103 // __RECIPF__ 1104 // __RSQRTE__ 1105 // __RSQRTEF__ 1106 // _SOFT_DOUBLE_ 1107 // __NO_LWSYNC__ 1108 // __HAVE_BSWAP__ 1109 // __LONGDOUBLE128 1110 // __CMODEL_MEDIUM__ 1111 // __CMODEL_LARGE__ 1112 // _CALL_SYSV 1113 // _CALL_DARWIN 1114 // __NO_FPRS__ 1115 } 1116 1117 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1118 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1119 .Case("7400", true) 1120 .Case("g4", true) 1121 .Case("7450", true) 1122 .Case("g4+", true) 1123 .Case("970", true) 1124 .Case("g5", true) 1125 .Case("pwr6", true) 1126 .Case("pwr7", true) 1127 .Case("pwr8", true) 1128 .Case("ppc64", true) 1129 .Case("ppc64le", true) 1130 .Default(false); 1131 1132 Features["qpx"] = (CPU == "a2q"); 1133 1134 if (!ABI.empty()) 1135 Features[ABI] = true; 1136 } 1137 1138 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1139 return Feature == "powerpc"; 1140 } 1141 1142 1143 const char * const PPCTargetInfo::GCCRegNames[] = { 1144 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1145 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1146 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1147 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1148 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1149 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1150 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1151 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1152 "mq", "lr", "ctr", "ap", 1153 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1154 "xer", 1155 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1156 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1157 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1158 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1159 "vrsave", "vscr", 1160 "spe_acc", "spefscr", 1161 "sfp" 1162 }; 1163 1164 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1165 unsigned &NumNames) const { 1166 Names = GCCRegNames; 1167 NumNames = llvm::array_lengthof(GCCRegNames); 1168 } 1169 1170 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1171 // While some of these aliases do map to different registers 1172 // they still share the same register name. 1173 { { "0" }, "r0" }, 1174 { { "1"}, "r1" }, 1175 { { "2" }, "r2" }, 1176 { { "3" }, "r3" }, 1177 { { "4" }, "r4" }, 1178 { { "5" }, "r5" }, 1179 { { "6" }, "r6" }, 1180 { { "7" }, "r7" }, 1181 { { "8" }, "r8" }, 1182 { { "9" }, "r9" }, 1183 { { "10" }, "r10" }, 1184 { { "11" }, "r11" }, 1185 { { "12" }, "r12" }, 1186 { { "13" }, "r13" }, 1187 { { "14" }, "r14" }, 1188 { { "15" }, "r15" }, 1189 { { "16" }, "r16" }, 1190 { { "17" }, "r17" }, 1191 { { "18" }, "r18" }, 1192 { { "19" }, "r19" }, 1193 { { "20" }, "r20" }, 1194 { { "21" }, "r21" }, 1195 { { "22" }, "r22" }, 1196 { { "23" }, "r23" }, 1197 { { "24" }, "r24" }, 1198 { { "25" }, "r25" }, 1199 { { "26" }, "r26" }, 1200 { { "27" }, "r27" }, 1201 { { "28" }, "r28" }, 1202 { { "29" }, "r29" }, 1203 { { "30" }, "r30" }, 1204 { { "31" }, "r31" }, 1205 { { "fr0" }, "f0" }, 1206 { { "fr1" }, "f1" }, 1207 { { "fr2" }, "f2" }, 1208 { { "fr3" }, "f3" }, 1209 { { "fr4" }, "f4" }, 1210 { { "fr5" }, "f5" }, 1211 { { "fr6" }, "f6" }, 1212 { { "fr7" }, "f7" }, 1213 { { "fr8" }, "f8" }, 1214 { { "fr9" }, "f9" }, 1215 { { "fr10" }, "f10" }, 1216 { { "fr11" }, "f11" }, 1217 { { "fr12" }, "f12" }, 1218 { { "fr13" }, "f13" }, 1219 { { "fr14" }, "f14" }, 1220 { { "fr15" }, "f15" }, 1221 { { "fr16" }, "f16" }, 1222 { { "fr17" }, "f17" }, 1223 { { "fr18" }, "f18" }, 1224 { { "fr19" }, "f19" }, 1225 { { "fr20" }, "f20" }, 1226 { { "fr21" }, "f21" }, 1227 { { "fr22" }, "f22" }, 1228 { { "fr23" }, "f23" }, 1229 { { "fr24" }, "f24" }, 1230 { { "fr25" }, "f25" }, 1231 { { "fr26" }, "f26" }, 1232 { { "fr27" }, "f27" }, 1233 { { "fr28" }, "f28" }, 1234 { { "fr29" }, "f29" }, 1235 { { "fr30" }, "f30" }, 1236 { { "fr31" }, "f31" }, 1237 { { "cc" }, "cr0" }, 1238 }; 1239 1240 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1241 unsigned &NumAliases) const { 1242 Aliases = GCCRegAliases; 1243 NumAliases = llvm::array_lengthof(GCCRegAliases); 1244 } 1245 } // end anonymous namespace. 1246 1247 namespace { 1248 class PPC32TargetInfo : public PPCTargetInfo { 1249 public: 1250 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1251 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1252 1253 switch (getTriple().getOS()) { 1254 case llvm::Triple::Linux: 1255 case llvm::Triple::FreeBSD: 1256 case llvm::Triple::NetBSD: 1257 SizeType = UnsignedInt; 1258 PtrDiffType = SignedInt; 1259 IntPtrType = SignedInt; 1260 break; 1261 default: 1262 break; 1263 } 1264 1265 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1266 LongDoubleWidth = LongDoubleAlign = 64; 1267 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1268 } 1269 1270 // PPC32 supports atomics up to 4 bytes. 1271 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1272 } 1273 1274 BuiltinVaListKind getBuiltinVaListKind() const override { 1275 // This is the ELF definition, and is overridden by the Darwin sub-target 1276 return TargetInfo::PowerABIBuiltinVaList; 1277 } 1278 }; 1279 } // end anonymous namespace. 1280 1281 // Note: ABI differences may eventually require us to have a separate 1282 // TargetInfo for little endian. 1283 namespace { 1284 class PPC64TargetInfo : public PPCTargetInfo { 1285 public: 1286 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1287 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1288 IntMaxType = SignedLong; 1289 Int64Type = SignedLong; 1290 1291 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1292 DescriptionString = "e-m:e-i64:64-n32:64"; 1293 ABI = "elfv2"; 1294 } else { 1295 DescriptionString = "E-m:e-i64:64-n32:64"; 1296 ABI = "elfv1"; 1297 } 1298 1299 switch (getTriple().getOS()) { 1300 case llvm::Triple::FreeBSD: 1301 LongDoubleWidth = LongDoubleAlign = 64; 1302 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1303 break; 1304 case llvm::Triple::NetBSD: 1305 IntMaxType = SignedLongLong; 1306 Int64Type = SignedLongLong; 1307 break; 1308 default: 1309 break; 1310 } 1311 1312 // PPC64 supports atomics up to 8 bytes. 1313 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1314 } 1315 BuiltinVaListKind getBuiltinVaListKind() const override { 1316 return TargetInfo::CharPtrBuiltinVaList; 1317 } 1318 // PPC64 Linux-specifc ABI options. 1319 bool setABI(const std::string &Name) override { 1320 if (Name == "elfv1" || Name == "elfv2") { 1321 ABI = Name; 1322 return true; 1323 } 1324 return false; 1325 } 1326 }; 1327 } // end anonymous namespace. 1328 1329 1330 namespace { 1331 class DarwinPPC32TargetInfo : 1332 public DarwinTargetInfo<PPC32TargetInfo> { 1333 public: 1334 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1335 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1336 HasAlignMac68kSupport = true; 1337 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1338 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1339 LongLongAlign = 32; 1340 SuitableAlign = 128; 1341 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1342 } 1343 BuiltinVaListKind getBuiltinVaListKind() const override { 1344 return TargetInfo::CharPtrBuiltinVaList; 1345 } 1346 }; 1347 1348 class DarwinPPC64TargetInfo : 1349 public DarwinTargetInfo<PPC64TargetInfo> { 1350 public: 1351 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1352 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1353 HasAlignMac68kSupport = true; 1354 SuitableAlign = 128; 1355 DescriptionString = "E-m:o-i64:64-n32:64"; 1356 } 1357 }; 1358 } // end anonymous namespace. 1359 1360 namespace { 1361 static const unsigned NVPTXAddrSpaceMap[] = { 1362 1, // opencl_global 1363 3, // opencl_local 1364 4, // opencl_constant 1365 1, // cuda_device 1366 4, // cuda_constant 1367 3, // cuda_shared 1368 }; 1369 class NVPTXTargetInfo : public TargetInfo { 1370 static const char * const GCCRegNames[]; 1371 static const Builtin::Info BuiltinInfo[]; 1372 public: 1373 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1374 BigEndian = false; 1375 TLSSupported = false; 1376 LongWidth = LongAlign = 64; 1377 AddrSpaceMap = &NVPTXAddrSpaceMap; 1378 UseAddrSpaceMapMangling = true; 1379 // Define available target features 1380 // These must be defined in sorted order! 1381 NoAsmVariants = true; 1382 } 1383 void getTargetDefines(const LangOptions &Opts, 1384 MacroBuilder &Builder) const override { 1385 Builder.defineMacro("__PTX__"); 1386 Builder.defineMacro("__NVPTX__"); 1387 } 1388 void getTargetBuiltins(const Builtin::Info *&Records, 1389 unsigned &NumRecords) const override { 1390 Records = BuiltinInfo; 1391 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1392 } 1393 bool hasFeature(StringRef Feature) const override { 1394 return Feature == "ptx" || Feature == "nvptx"; 1395 } 1396 1397 void getGCCRegNames(const char * const *&Names, 1398 unsigned &NumNames) const override; 1399 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1400 unsigned &NumAliases) const override { 1401 // No aliases. 1402 Aliases = nullptr; 1403 NumAliases = 0; 1404 } 1405 bool validateAsmConstraint(const char *&Name, 1406 TargetInfo::ConstraintInfo &Info) const override { 1407 switch (*Name) { 1408 default: return false; 1409 case 'c': 1410 case 'h': 1411 case 'r': 1412 case 'l': 1413 case 'f': 1414 case 'd': 1415 Info.setAllowsRegister(); 1416 return true; 1417 } 1418 } 1419 const char *getClobbers() const override { 1420 // FIXME: Is this really right? 1421 return ""; 1422 } 1423 BuiltinVaListKind getBuiltinVaListKind() const override { 1424 // FIXME: implement 1425 return TargetInfo::CharPtrBuiltinVaList; 1426 } 1427 bool setCPU(const std::string &Name) override { 1428 bool Valid = llvm::StringSwitch<bool>(Name) 1429 .Case("sm_20", true) 1430 .Case("sm_21", true) 1431 .Case("sm_30", true) 1432 .Case("sm_35", true) 1433 .Default(false); 1434 1435 return Valid; 1436 } 1437 }; 1438 1439 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1440 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1441 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1442 ALL_LANGUAGES }, 1443 #include "clang/Basic/BuiltinsNVPTX.def" 1444 }; 1445 1446 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1447 "r0" 1448 }; 1449 1450 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1451 unsigned &NumNames) const { 1452 Names = GCCRegNames; 1453 NumNames = llvm::array_lengthof(GCCRegNames); 1454 } 1455 1456 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1457 public: 1458 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1459 PointerWidth = PointerAlign = 32; 1460 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1461 IntPtrType = TargetInfo::SignedInt; 1462 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1463 } 1464 }; 1465 1466 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1467 public: 1468 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1469 PointerWidth = PointerAlign = 64; 1470 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1471 IntPtrType = TargetInfo::SignedLongLong; 1472 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1473 } 1474 }; 1475 } 1476 1477 namespace { 1478 1479 static const unsigned R600AddrSpaceMap[] = { 1480 1, // opencl_global 1481 3, // opencl_local 1482 2, // opencl_constant 1483 1, // cuda_device 1484 2, // cuda_constant 1485 3 // cuda_shared 1486 }; 1487 1488 // If you edit the description strings, make sure you update 1489 // getPointerWidthV(). 1490 1491 static const char *DescriptionStringR600 = 1492 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1493 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1494 1495 static const char *DescriptionStringR600DoubleOps = 1496 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1497 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1498 1499 static const char *DescriptionStringSI = 1500 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1501 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1502 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1503 1504 class R600TargetInfo : public TargetInfo { 1505 static const Builtin::Info BuiltinInfo[]; 1506 1507 /// \brief The GPU profiles supported by the R600 target. 1508 enum GPUKind { 1509 GK_NONE, 1510 GK_R600, 1511 GK_R600_DOUBLE_OPS, 1512 GK_R700, 1513 GK_R700_DOUBLE_OPS, 1514 GK_EVERGREEN, 1515 GK_EVERGREEN_DOUBLE_OPS, 1516 GK_NORTHERN_ISLANDS, 1517 GK_CAYMAN, 1518 GK_SOUTHERN_ISLANDS, 1519 GK_SEA_ISLANDS 1520 } GPU; 1521 1522 public: 1523 R600TargetInfo(const llvm::Triple &Triple) 1524 : TargetInfo(Triple), GPU(GK_R600) { 1525 DescriptionString = DescriptionStringR600; 1526 AddrSpaceMap = &R600AddrSpaceMap; 1527 UseAddrSpaceMapMangling = true; 1528 } 1529 1530 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1531 if (GPU <= GK_CAYMAN) 1532 return 32; 1533 1534 switch(AddrSpace) { 1535 default: 1536 return 64; 1537 case 0: 1538 case 3: 1539 case 5: 1540 return 32; 1541 } 1542 } 1543 1544 const char * getClobbers() const override { 1545 return ""; 1546 } 1547 1548 void getGCCRegNames(const char * const *&Names, 1549 unsigned &numNames) const override { 1550 Names = nullptr; 1551 numNames = 0; 1552 } 1553 1554 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1555 unsigned &NumAliases) const override { 1556 Aliases = nullptr; 1557 NumAliases = 0; 1558 } 1559 1560 bool validateAsmConstraint(const char *&Name, 1561 TargetInfo::ConstraintInfo &info) const override { 1562 return true; 1563 } 1564 1565 void getTargetBuiltins(const Builtin::Info *&Records, 1566 unsigned &NumRecords) const override { 1567 Records = BuiltinInfo; 1568 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1569 } 1570 1571 void getTargetDefines(const LangOptions &Opts, 1572 MacroBuilder &Builder) const override { 1573 Builder.defineMacro("__R600__"); 1574 } 1575 1576 BuiltinVaListKind getBuiltinVaListKind() const override { 1577 return TargetInfo::CharPtrBuiltinVaList; 1578 } 1579 1580 bool setCPU(const std::string &Name) override { 1581 GPU = llvm::StringSwitch<GPUKind>(Name) 1582 .Case("r600" , GK_R600) 1583 .Case("rv610", GK_R600) 1584 .Case("rv620", GK_R600) 1585 .Case("rv630", GK_R600) 1586 .Case("rv635", GK_R600) 1587 .Case("rs780", GK_R600) 1588 .Case("rs880", GK_R600) 1589 .Case("rv670", GK_R600_DOUBLE_OPS) 1590 .Case("rv710", GK_R700) 1591 .Case("rv730", GK_R700) 1592 .Case("rv740", GK_R700_DOUBLE_OPS) 1593 .Case("rv770", GK_R700_DOUBLE_OPS) 1594 .Case("palm", GK_EVERGREEN) 1595 .Case("cedar", GK_EVERGREEN) 1596 .Case("sumo", GK_EVERGREEN) 1597 .Case("sumo2", GK_EVERGREEN) 1598 .Case("redwood", GK_EVERGREEN) 1599 .Case("juniper", GK_EVERGREEN) 1600 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1601 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1602 .Case("barts", GK_NORTHERN_ISLANDS) 1603 .Case("turks", GK_NORTHERN_ISLANDS) 1604 .Case("caicos", GK_NORTHERN_ISLANDS) 1605 .Case("cayman", GK_CAYMAN) 1606 .Case("aruba", GK_CAYMAN) 1607 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1608 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1609 .Case("verde", GK_SOUTHERN_ISLANDS) 1610 .Case("oland", GK_SOUTHERN_ISLANDS) 1611 .Case("hainan", GK_SOUTHERN_ISLANDS) 1612 .Case("bonaire", GK_SEA_ISLANDS) 1613 .Case("kabini", GK_SEA_ISLANDS) 1614 .Case("kaveri", GK_SEA_ISLANDS) 1615 .Case("hawaii", GK_SEA_ISLANDS) 1616 .Case("mullins", GK_SEA_ISLANDS) 1617 .Default(GK_NONE); 1618 1619 if (GPU == GK_NONE) { 1620 return false; 1621 } 1622 1623 // Set the correct data layout 1624 switch (GPU) { 1625 case GK_NONE: 1626 case GK_R600: 1627 case GK_R700: 1628 case GK_EVERGREEN: 1629 case GK_NORTHERN_ISLANDS: 1630 DescriptionString = DescriptionStringR600; 1631 break; 1632 case GK_R600_DOUBLE_OPS: 1633 case GK_R700_DOUBLE_OPS: 1634 case GK_EVERGREEN_DOUBLE_OPS: 1635 case GK_CAYMAN: 1636 DescriptionString = DescriptionStringR600DoubleOps; 1637 break; 1638 case GK_SOUTHERN_ISLANDS: 1639 case GK_SEA_ISLANDS: 1640 DescriptionString = DescriptionStringSI; 1641 break; 1642 } 1643 1644 return true; 1645 } 1646 }; 1647 1648 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1649 #define BUILTIN(ID, TYPE, ATTRS) \ 1650 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1651 #include "clang/Basic/BuiltinsR600.def" 1652 }; 1653 1654 } // end anonymous namespace 1655 1656 namespace { 1657 // Namespace for x86 abstract base class 1658 const Builtin::Info BuiltinInfo[] = { 1659 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1660 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1661 ALL_LANGUAGES }, 1662 #include "clang/Basic/BuiltinsX86.def" 1663 }; 1664 1665 static const char* const GCCRegNames[] = { 1666 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1667 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1668 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1669 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1670 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1671 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1672 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1673 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1674 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1675 }; 1676 1677 const TargetInfo::AddlRegName AddlRegNames[] = { 1678 { { "al", "ah", "eax", "rax" }, 0 }, 1679 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1680 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1681 { { "dl", "dh", "edx", "rdx" }, 1 }, 1682 { { "esi", "rsi" }, 4 }, 1683 { { "edi", "rdi" }, 5 }, 1684 { { "esp", "rsp" }, 7 }, 1685 { { "ebp", "rbp" }, 6 }, 1686 }; 1687 1688 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1689 // most of the implementation can be shared. 1690 class X86TargetInfo : public TargetInfo { 1691 enum X86SSEEnum { 1692 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1693 } SSELevel; 1694 enum MMX3DNowEnum { 1695 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1696 } MMX3DNowLevel; 1697 enum XOPEnum { 1698 NoXOP, 1699 SSE4A, 1700 FMA4, 1701 XOP 1702 } XOPLevel; 1703 1704 bool HasAES; 1705 bool HasPCLMUL; 1706 bool HasLZCNT; 1707 bool HasRDRND; 1708 bool HasBMI; 1709 bool HasBMI2; 1710 bool HasPOPCNT; 1711 bool HasRTM; 1712 bool HasPRFCHW; 1713 bool HasRDSEED; 1714 bool HasADX; 1715 bool HasTBM; 1716 bool HasFMA; 1717 bool HasF16C; 1718 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL; 1719 bool HasSHA; 1720 bool HasCX16; 1721 1722 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1723 /// 1724 /// Each enumeration represents a particular CPU supported by Clang. These 1725 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1726 enum CPUKind { 1727 CK_Generic, 1728 1729 /// \name i386 1730 /// i386-generation processors. 1731 //@{ 1732 CK_i386, 1733 //@} 1734 1735 /// \name i486 1736 /// i486-generation processors. 1737 //@{ 1738 CK_i486, 1739 CK_WinChipC6, 1740 CK_WinChip2, 1741 CK_C3, 1742 //@} 1743 1744 /// \name i586 1745 /// i586-generation processors, P5 microarchitecture based. 1746 //@{ 1747 CK_i586, 1748 CK_Pentium, 1749 CK_PentiumMMX, 1750 //@} 1751 1752 /// \name i686 1753 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1754 //@{ 1755 CK_i686, 1756 CK_PentiumPro, 1757 CK_Pentium2, 1758 CK_Pentium3, 1759 CK_Pentium3M, 1760 CK_PentiumM, 1761 CK_C3_2, 1762 1763 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1764 /// Clang however has some logic to suport this. 1765 // FIXME: Warn, deprecate, and potentially remove this. 1766 CK_Yonah, 1767 //@} 1768 1769 /// \name Netburst 1770 /// Netburst microarchitecture based processors. 1771 //@{ 1772 CK_Pentium4, 1773 CK_Pentium4M, 1774 CK_Prescott, 1775 CK_Nocona, 1776 //@} 1777 1778 /// \name Core 1779 /// Core microarchitecture based processors. 1780 //@{ 1781 CK_Core2, 1782 1783 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1784 /// codename which GCC no longer accepts as an option to -march, but Clang 1785 /// has some logic for recognizing it. 1786 // FIXME: Warn, deprecate, and potentially remove this. 1787 CK_Penryn, 1788 //@} 1789 1790 /// \name Atom 1791 /// Atom processors 1792 //@{ 1793 CK_Atom, 1794 CK_Silvermont, 1795 //@} 1796 1797 /// \name Nehalem 1798 /// Nehalem microarchitecture based processors. 1799 //@{ 1800 CK_Corei7, 1801 CK_Corei7AVX, 1802 CK_CoreAVXi, 1803 CK_CoreAVX2, 1804 CK_Broadwell, 1805 //@} 1806 1807 /// \name Knights Landing 1808 /// Knights Landing processor. 1809 CK_KNL, 1810 1811 /// \name Skylake Server 1812 /// Skylake server processor. 1813 CK_SKX, 1814 1815 /// \name K6 1816 /// K6 architecture processors. 1817 //@{ 1818 CK_K6, 1819 CK_K6_2, 1820 CK_K6_3, 1821 //@} 1822 1823 /// \name K7 1824 /// K7 architecture processors. 1825 //@{ 1826 CK_Athlon, 1827 CK_AthlonThunderbird, 1828 CK_Athlon4, 1829 CK_AthlonXP, 1830 CK_AthlonMP, 1831 //@} 1832 1833 /// \name K8 1834 /// K8 architecture processors. 1835 //@{ 1836 CK_Athlon64, 1837 CK_Athlon64SSE3, 1838 CK_AthlonFX, 1839 CK_K8, 1840 CK_K8SSE3, 1841 CK_Opteron, 1842 CK_OpteronSSE3, 1843 CK_AMDFAM10, 1844 //@} 1845 1846 /// \name Bobcat 1847 /// Bobcat architecture processors. 1848 //@{ 1849 CK_BTVER1, 1850 CK_BTVER2, 1851 //@} 1852 1853 /// \name Bulldozer 1854 /// Bulldozer architecture processors. 1855 //@{ 1856 CK_BDVER1, 1857 CK_BDVER2, 1858 CK_BDVER3, 1859 CK_BDVER4, 1860 //@} 1861 1862 /// This specification is deprecated and will be removed in the future. 1863 /// Users should prefer \see CK_K8. 1864 // FIXME: Warn on this when the CPU is set to it. 1865 CK_x86_64, 1866 //@} 1867 1868 /// \name Geode 1869 /// Geode processors. 1870 //@{ 1871 CK_Geode 1872 //@} 1873 } CPU; 1874 1875 enum FPMathKind { 1876 FP_Default, 1877 FP_SSE, 1878 FP_387 1879 } FPMath; 1880 1881 public: 1882 X86TargetInfo(const llvm::Triple &Triple) 1883 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1884 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1885 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1886 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasADX(false), 1887 HasTBM(false), HasFMA(false), HasF16C(false), HasAVX512CD(false), 1888 HasAVX512ER(false), HasAVX512PF(false), HasAVX512DQ(false), 1889 HasAVX512BW(false), HasAVX512VL(false), HasSHA(false), HasCX16(false), 1890 CPU(CK_Generic), FPMath(FP_Default) { 1891 BigEndian = false; 1892 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1893 } 1894 unsigned getFloatEvalMethod() const override { 1895 // X87 evaluates with 80 bits "long double" precision. 1896 return SSELevel == NoSSE ? 2 : 0; 1897 } 1898 void getTargetBuiltins(const Builtin::Info *&Records, 1899 unsigned &NumRecords) const override { 1900 Records = BuiltinInfo; 1901 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1902 } 1903 void getGCCRegNames(const char * const *&Names, 1904 unsigned &NumNames) const override { 1905 Names = GCCRegNames; 1906 NumNames = llvm::array_lengthof(GCCRegNames); 1907 } 1908 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1909 unsigned &NumAliases) const override { 1910 Aliases = nullptr; 1911 NumAliases = 0; 1912 } 1913 void getGCCAddlRegNames(const AddlRegName *&Names, 1914 unsigned &NumNames) const override { 1915 Names = AddlRegNames; 1916 NumNames = llvm::array_lengthof(AddlRegNames); 1917 } 1918 bool validateAsmConstraint(const char *&Name, 1919 TargetInfo::ConstraintInfo &info) const override; 1920 1921 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 1922 1923 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 1924 1925 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 1926 1927 std::string convertConstraint(const char *&Constraint) const override; 1928 const char *getClobbers() const override { 1929 return "~{dirflag},~{fpsr},~{flags}"; 1930 } 1931 void getTargetDefines(const LangOptions &Opts, 1932 MacroBuilder &Builder) const override; 1933 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1934 bool Enabled); 1935 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1936 bool Enabled); 1937 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1938 bool Enabled); 1939 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1940 StringRef Name, bool Enabled) const override { 1941 setFeatureEnabledImpl(Features, Name, Enabled); 1942 } 1943 // This exists purely to cut down on the number of virtual calls in 1944 // getDefaultFeatures which calls this repeatedly. 1945 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1946 StringRef Name, bool Enabled); 1947 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1948 bool hasFeature(StringRef Feature) const override; 1949 bool handleTargetFeatures(std::vector<std::string> &Features, 1950 DiagnosticsEngine &Diags) override; 1951 StringRef getABI() const override { 1952 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1953 return "avx"; 1954 else if (getTriple().getArch() == llvm::Triple::x86 && 1955 MMX3DNowLevel == NoMMX3DNow) 1956 return "no-mmx"; 1957 return ""; 1958 } 1959 bool setCPU(const std::string &Name) override { 1960 CPU = llvm::StringSwitch<CPUKind>(Name) 1961 .Case("i386", CK_i386) 1962 .Case("i486", CK_i486) 1963 .Case("winchip-c6", CK_WinChipC6) 1964 .Case("winchip2", CK_WinChip2) 1965 .Case("c3", CK_C3) 1966 .Case("i586", CK_i586) 1967 .Case("pentium", CK_Pentium) 1968 .Case("pentium-mmx", CK_PentiumMMX) 1969 .Case("i686", CK_i686) 1970 .Case("pentiumpro", CK_PentiumPro) 1971 .Case("pentium2", CK_Pentium2) 1972 .Case("pentium3", CK_Pentium3) 1973 .Case("pentium3m", CK_Pentium3M) 1974 .Case("pentium-m", CK_PentiumM) 1975 .Case("c3-2", CK_C3_2) 1976 .Case("yonah", CK_Yonah) 1977 .Case("pentium4", CK_Pentium4) 1978 .Case("pentium4m", CK_Pentium4M) 1979 .Case("prescott", CK_Prescott) 1980 .Case("nocona", CK_Nocona) 1981 .Case("core2", CK_Core2) 1982 .Case("penryn", CK_Penryn) 1983 .Case("atom", CK_Atom) 1984 .Case("slm", CK_Silvermont) 1985 .Case("corei7", CK_Corei7) 1986 .Case("corei7-avx", CK_Corei7AVX) 1987 .Case("core-avx-i", CK_CoreAVXi) 1988 .Case("core-avx2", CK_CoreAVX2) 1989 .Case("broadwell", CK_Broadwell) 1990 .Case("knl", CK_KNL) 1991 .Case("skx", CK_SKX) 1992 .Case("k6", CK_K6) 1993 .Case("k6-2", CK_K6_2) 1994 .Case("k6-3", CK_K6_3) 1995 .Case("athlon", CK_Athlon) 1996 .Case("athlon-tbird", CK_AthlonThunderbird) 1997 .Case("athlon-4", CK_Athlon4) 1998 .Case("athlon-xp", CK_AthlonXP) 1999 .Case("athlon-mp", CK_AthlonMP) 2000 .Case("athlon64", CK_Athlon64) 2001 .Case("athlon64-sse3", CK_Athlon64SSE3) 2002 .Case("athlon-fx", CK_AthlonFX) 2003 .Case("k8", CK_K8) 2004 .Case("k8-sse3", CK_K8SSE3) 2005 .Case("opteron", CK_Opteron) 2006 .Case("opteron-sse3", CK_OpteronSSE3) 2007 .Case("amdfam10", CK_AMDFAM10) 2008 .Case("btver1", CK_BTVER1) 2009 .Case("btver2", CK_BTVER2) 2010 .Case("bdver1", CK_BDVER1) 2011 .Case("bdver2", CK_BDVER2) 2012 .Case("bdver3", CK_BDVER3) 2013 .Case("bdver4", CK_BDVER4) 2014 .Case("x86-64", CK_x86_64) 2015 .Case("geode", CK_Geode) 2016 .Default(CK_Generic); 2017 2018 // Perform any per-CPU checks necessary to determine if this CPU is 2019 // acceptable. 2020 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2021 // invalid without explaining *why*. 2022 switch (CPU) { 2023 case CK_Generic: 2024 // No processor selected! 2025 return false; 2026 2027 case CK_i386: 2028 case CK_i486: 2029 case CK_WinChipC6: 2030 case CK_WinChip2: 2031 case CK_C3: 2032 case CK_i586: 2033 case CK_Pentium: 2034 case CK_PentiumMMX: 2035 case CK_i686: 2036 case CK_PentiumPro: 2037 case CK_Pentium2: 2038 case CK_Pentium3: 2039 case CK_Pentium3M: 2040 case CK_PentiumM: 2041 case CK_Yonah: 2042 case CK_C3_2: 2043 case CK_Pentium4: 2044 case CK_Pentium4M: 2045 case CK_Prescott: 2046 case CK_K6: 2047 case CK_K6_2: 2048 case CK_K6_3: 2049 case CK_Athlon: 2050 case CK_AthlonThunderbird: 2051 case CK_Athlon4: 2052 case CK_AthlonXP: 2053 case CK_AthlonMP: 2054 case CK_Geode: 2055 // Only accept certain architectures when compiling in 32-bit mode. 2056 if (getTriple().getArch() != llvm::Triple::x86) 2057 return false; 2058 2059 // Fallthrough 2060 case CK_Nocona: 2061 case CK_Core2: 2062 case CK_Penryn: 2063 case CK_Atom: 2064 case CK_Silvermont: 2065 case CK_Corei7: 2066 case CK_Corei7AVX: 2067 case CK_CoreAVXi: 2068 case CK_CoreAVX2: 2069 case CK_Broadwell: 2070 case CK_KNL: 2071 case CK_SKX: 2072 case CK_Athlon64: 2073 case CK_Athlon64SSE3: 2074 case CK_AthlonFX: 2075 case CK_K8: 2076 case CK_K8SSE3: 2077 case CK_Opteron: 2078 case CK_OpteronSSE3: 2079 case CK_AMDFAM10: 2080 case CK_BTVER1: 2081 case CK_BTVER2: 2082 case CK_BDVER1: 2083 case CK_BDVER2: 2084 case CK_BDVER3: 2085 case CK_BDVER4: 2086 case CK_x86_64: 2087 return true; 2088 } 2089 llvm_unreachable("Unhandled CPU kind"); 2090 } 2091 2092 bool setFPMath(StringRef Name) override; 2093 2094 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2095 // We accept all non-ARM calling conventions 2096 return (CC == CC_X86ThisCall || 2097 CC == CC_X86FastCall || 2098 CC == CC_X86StdCall || 2099 CC == CC_X86VectorCall || 2100 CC == CC_C || 2101 CC == CC_X86Pascal || 2102 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2103 } 2104 2105 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2106 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2107 } 2108 }; 2109 2110 bool X86TargetInfo::setFPMath(StringRef Name) { 2111 if (Name == "387") { 2112 FPMath = FP_387; 2113 return true; 2114 } 2115 if (Name == "sse") { 2116 FPMath = FP_SSE; 2117 return true; 2118 } 2119 return false; 2120 } 2121 2122 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2123 // FIXME: This *really* should not be here. 2124 2125 // X86_64 always has SSE2. 2126 if (getTriple().getArch() == llvm::Triple::x86_64) 2127 setFeatureEnabledImpl(Features, "sse2", true); 2128 2129 switch (CPU) { 2130 case CK_Generic: 2131 case CK_i386: 2132 case CK_i486: 2133 case CK_i586: 2134 case CK_Pentium: 2135 case CK_i686: 2136 case CK_PentiumPro: 2137 break; 2138 case CK_PentiumMMX: 2139 case CK_Pentium2: 2140 setFeatureEnabledImpl(Features, "mmx", true); 2141 break; 2142 case CK_Pentium3: 2143 case CK_Pentium3M: 2144 setFeatureEnabledImpl(Features, "sse", true); 2145 break; 2146 case CK_PentiumM: 2147 case CK_Pentium4: 2148 case CK_Pentium4M: 2149 case CK_x86_64: 2150 setFeatureEnabledImpl(Features, "sse2", true); 2151 break; 2152 case CK_Yonah: 2153 case CK_Prescott: 2154 case CK_Nocona: 2155 setFeatureEnabledImpl(Features, "sse3", true); 2156 setFeatureEnabledImpl(Features, "cx16", true); 2157 break; 2158 case CK_Core2: 2159 setFeatureEnabledImpl(Features, "ssse3", true); 2160 setFeatureEnabledImpl(Features, "cx16", true); 2161 break; 2162 case CK_Penryn: 2163 setFeatureEnabledImpl(Features, "sse4.1", true); 2164 setFeatureEnabledImpl(Features, "cx16", true); 2165 break; 2166 case CK_Atom: 2167 setFeatureEnabledImpl(Features, "ssse3", true); 2168 setFeatureEnabledImpl(Features, "cx16", true); 2169 break; 2170 case CK_Silvermont: 2171 setFeatureEnabledImpl(Features, "sse4.2", true); 2172 setFeatureEnabledImpl(Features, "aes", true); 2173 setFeatureEnabledImpl(Features, "cx16", true); 2174 setFeatureEnabledImpl(Features, "pclmul", true); 2175 break; 2176 case CK_Corei7: 2177 setFeatureEnabledImpl(Features, "sse4.2", true); 2178 setFeatureEnabledImpl(Features, "cx16", true); 2179 break; 2180 case CK_Corei7AVX: 2181 setFeatureEnabledImpl(Features, "avx", true); 2182 setFeatureEnabledImpl(Features, "aes", true); 2183 setFeatureEnabledImpl(Features, "cx16", true); 2184 setFeatureEnabledImpl(Features, "pclmul", true); 2185 break; 2186 case CK_CoreAVXi: 2187 setFeatureEnabledImpl(Features, "avx", true); 2188 setFeatureEnabledImpl(Features, "aes", true); 2189 setFeatureEnabledImpl(Features, "pclmul", true); 2190 setFeatureEnabledImpl(Features, "rdrnd", true); 2191 setFeatureEnabledImpl(Features, "f16c", true); 2192 break; 2193 case CK_CoreAVX2: 2194 setFeatureEnabledImpl(Features, "avx2", true); 2195 setFeatureEnabledImpl(Features, "aes", true); 2196 setFeatureEnabledImpl(Features, "pclmul", true); 2197 setFeatureEnabledImpl(Features, "lzcnt", true); 2198 setFeatureEnabledImpl(Features, "rdrnd", true); 2199 setFeatureEnabledImpl(Features, "f16c", true); 2200 setFeatureEnabledImpl(Features, "bmi", true); 2201 setFeatureEnabledImpl(Features, "bmi2", true); 2202 setFeatureEnabledImpl(Features, "rtm", true); 2203 setFeatureEnabledImpl(Features, "fma", true); 2204 setFeatureEnabledImpl(Features, "cx16", true); 2205 break; 2206 case CK_Broadwell: 2207 setFeatureEnabledImpl(Features, "avx2", true); 2208 setFeatureEnabledImpl(Features, "aes", true); 2209 setFeatureEnabledImpl(Features, "pclmul", true); 2210 setFeatureEnabledImpl(Features, "lzcnt", true); 2211 setFeatureEnabledImpl(Features, "rdrnd", true); 2212 setFeatureEnabledImpl(Features, "f16c", true); 2213 setFeatureEnabledImpl(Features, "bmi", true); 2214 setFeatureEnabledImpl(Features, "bmi2", true); 2215 setFeatureEnabledImpl(Features, "rtm", true); 2216 setFeatureEnabledImpl(Features, "fma", true); 2217 setFeatureEnabledImpl(Features, "cx16", true); 2218 setFeatureEnabledImpl(Features, "rdseed", true); 2219 setFeatureEnabledImpl(Features, "adx", true); 2220 break; 2221 case CK_KNL: 2222 setFeatureEnabledImpl(Features, "avx512f", true); 2223 setFeatureEnabledImpl(Features, "avx512cd", true); 2224 setFeatureEnabledImpl(Features, "avx512er", true); 2225 setFeatureEnabledImpl(Features, "avx512pf", true); 2226 setFeatureEnabledImpl(Features, "aes", true); 2227 setFeatureEnabledImpl(Features, "pclmul", true); 2228 setFeatureEnabledImpl(Features, "lzcnt", true); 2229 setFeatureEnabledImpl(Features, "rdrnd", true); 2230 setFeatureEnabledImpl(Features, "f16c", true); 2231 setFeatureEnabledImpl(Features, "bmi", true); 2232 setFeatureEnabledImpl(Features, "bmi2", true); 2233 setFeatureEnabledImpl(Features, "rtm", true); 2234 setFeatureEnabledImpl(Features, "fma", true); 2235 setFeatureEnabledImpl(Features, "rdseed", true); 2236 setFeatureEnabledImpl(Features, "adx", true); 2237 break; 2238 case CK_SKX: 2239 setFeatureEnabledImpl(Features, "avx512f", true); 2240 setFeatureEnabledImpl(Features, "avx512cd", true); 2241 setFeatureEnabledImpl(Features, "avx512dq", true); 2242 setFeatureEnabledImpl(Features, "avx512bw", true); 2243 setFeatureEnabledImpl(Features, "avx512vl", true); 2244 setFeatureEnabledImpl(Features, "aes", true); 2245 setFeatureEnabledImpl(Features, "pclmul", true); 2246 setFeatureEnabledImpl(Features, "lzcnt", true); 2247 setFeatureEnabledImpl(Features, "rdrnd", true); 2248 setFeatureEnabledImpl(Features, "f16c", true); 2249 setFeatureEnabledImpl(Features, "bmi", true); 2250 setFeatureEnabledImpl(Features, "bmi2", true); 2251 setFeatureEnabledImpl(Features, "rtm", true); 2252 setFeatureEnabledImpl(Features, "fma", true); 2253 setFeatureEnabledImpl(Features, "rdseed", true); 2254 setFeatureEnabledImpl(Features, "adx", true); 2255 break; 2256 case CK_K6: 2257 case CK_WinChipC6: 2258 setFeatureEnabledImpl(Features, "mmx", true); 2259 break; 2260 case CK_K6_2: 2261 case CK_K6_3: 2262 case CK_WinChip2: 2263 case CK_C3: 2264 setFeatureEnabledImpl(Features, "3dnow", true); 2265 break; 2266 case CK_Athlon: 2267 case CK_AthlonThunderbird: 2268 case CK_Geode: 2269 setFeatureEnabledImpl(Features, "3dnowa", true); 2270 break; 2271 case CK_Athlon4: 2272 case CK_AthlonXP: 2273 case CK_AthlonMP: 2274 setFeatureEnabledImpl(Features, "sse", true); 2275 setFeatureEnabledImpl(Features, "3dnowa", true); 2276 break; 2277 case CK_K8: 2278 case CK_Opteron: 2279 case CK_Athlon64: 2280 case CK_AthlonFX: 2281 setFeatureEnabledImpl(Features, "sse2", true); 2282 setFeatureEnabledImpl(Features, "3dnowa", true); 2283 break; 2284 case CK_K8SSE3: 2285 case CK_OpteronSSE3: 2286 case CK_Athlon64SSE3: 2287 setFeatureEnabledImpl(Features, "sse3", true); 2288 setFeatureEnabledImpl(Features, "3dnowa", true); 2289 break; 2290 case CK_AMDFAM10: 2291 setFeatureEnabledImpl(Features, "sse3", true); 2292 setFeatureEnabledImpl(Features, "sse4a", true); 2293 setFeatureEnabledImpl(Features, "3dnowa", true); 2294 setFeatureEnabledImpl(Features, "lzcnt", true); 2295 setFeatureEnabledImpl(Features, "popcnt", true); 2296 break; 2297 case CK_BTVER1: 2298 setFeatureEnabledImpl(Features, "ssse3", true); 2299 setFeatureEnabledImpl(Features, "sse4a", true); 2300 setFeatureEnabledImpl(Features, "cx16", true); 2301 setFeatureEnabledImpl(Features, "lzcnt", true); 2302 setFeatureEnabledImpl(Features, "popcnt", true); 2303 setFeatureEnabledImpl(Features, "prfchw", true); 2304 break; 2305 case CK_BTVER2: 2306 setFeatureEnabledImpl(Features, "avx", true); 2307 setFeatureEnabledImpl(Features, "sse4a", true); 2308 setFeatureEnabledImpl(Features, "lzcnt", true); 2309 setFeatureEnabledImpl(Features, "aes", true); 2310 setFeatureEnabledImpl(Features, "pclmul", true); 2311 setFeatureEnabledImpl(Features, "prfchw", true); 2312 setFeatureEnabledImpl(Features, "bmi", true); 2313 setFeatureEnabledImpl(Features, "f16c", true); 2314 setFeatureEnabledImpl(Features, "cx16", true); 2315 break; 2316 case CK_BDVER1: 2317 setFeatureEnabledImpl(Features, "xop", true); 2318 setFeatureEnabledImpl(Features, "lzcnt", true); 2319 setFeatureEnabledImpl(Features, "aes", true); 2320 setFeatureEnabledImpl(Features, "pclmul", true); 2321 setFeatureEnabledImpl(Features, "prfchw", true); 2322 setFeatureEnabledImpl(Features, "cx16", true); 2323 break; 2324 case CK_BDVER4: 2325 setFeatureEnabledImpl(Features, "avx2", true); 2326 setFeatureEnabledImpl(Features, "bmi2", true); 2327 // FALLTHROUGH 2328 case CK_BDVER2: 2329 case CK_BDVER3: 2330 setFeatureEnabledImpl(Features, "xop", true); 2331 setFeatureEnabledImpl(Features, "lzcnt", true); 2332 setFeatureEnabledImpl(Features, "aes", true); 2333 setFeatureEnabledImpl(Features, "pclmul", true); 2334 setFeatureEnabledImpl(Features, "prfchw", true); 2335 setFeatureEnabledImpl(Features, "bmi", true); 2336 setFeatureEnabledImpl(Features, "fma", true); 2337 setFeatureEnabledImpl(Features, "f16c", true); 2338 setFeatureEnabledImpl(Features, "tbm", true); 2339 setFeatureEnabledImpl(Features, "cx16", true); 2340 break; 2341 case CK_C3_2: 2342 setFeatureEnabledImpl(Features, "sse", true); 2343 break; 2344 } 2345 } 2346 2347 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2348 X86SSEEnum Level, bool Enabled) { 2349 if (Enabled) { 2350 switch (Level) { 2351 case AVX512F: 2352 Features["avx512f"] = true; 2353 case AVX2: 2354 Features["avx2"] = true; 2355 case AVX: 2356 Features["avx"] = true; 2357 case SSE42: 2358 Features["sse4.2"] = true; 2359 case SSE41: 2360 Features["sse4.1"] = true; 2361 case SSSE3: 2362 Features["ssse3"] = true; 2363 case SSE3: 2364 Features["sse3"] = true; 2365 case SSE2: 2366 Features["sse2"] = true; 2367 case SSE1: 2368 Features["sse"] = true; 2369 case NoSSE: 2370 break; 2371 } 2372 return; 2373 } 2374 2375 switch (Level) { 2376 case NoSSE: 2377 case SSE1: 2378 Features["sse"] = false; 2379 case SSE2: 2380 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2381 Features["sha"] = false; 2382 case SSE3: 2383 Features["sse3"] = false; 2384 setXOPLevel(Features, NoXOP, false); 2385 case SSSE3: 2386 Features["ssse3"] = false; 2387 case SSE41: 2388 Features["sse4.1"] = false; 2389 case SSE42: 2390 Features["sse4.2"] = false; 2391 case AVX: 2392 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2393 setXOPLevel(Features, FMA4, false); 2394 case AVX2: 2395 Features["avx2"] = false; 2396 case AVX512F: 2397 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] = 2398 Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false; 2399 } 2400 } 2401 2402 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2403 MMX3DNowEnum Level, bool Enabled) { 2404 if (Enabled) { 2405 switch (Level) { 2406 case AMD3DNowAthlon: 2407 Features["3dnowa"] = true; 2408 case AMD3DNow: 2409 Features["3dnow"] = true; 2410 case MMX: 2411 Features["mmx"] = true; 2412 case NoMMX3DNow: 2413 break; 2414 } 2415 return; 2416 } 2417 2418 switch (Level) { 2419 case NoMMX3DNow: 2420 case MMX: 2421 Features["mmx"] = false; 2422 case AMD3DNow: 2423 Features["3dnow"] = false; 2424 case AMD3DNowAthlon: 2425 Features["3dnowa"] = false; 2426 } 2427 } 2428 2429 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2430 bool Enabled) { 2431 if (Enabled) { 2432 switch (Level) { 2433 case XOP: 2434 Features["xop"] = true; 2435 case FMA4: 2436 Features["fma4"] = true; 2437 setSSELevel(Features, AVX, true); 2438 case SSE4A: 2439 Features["sse4a"] = true; 2440 setSSELevel(Features, SSE3, true); 2441 case NoXOP: 2442 break; 2443 } 2444 return; 2445 } 2446 2447 switch (Level) { 2448 case NoXOP: 2449 case SSE4A: 2450 Features["sse4a"] = false; 2451 case FMA4: 2452 Features["fma4"] = false; 2453 case XOP: 2454 Features["xop"] = false; 2455 } 2456 } 2457 2458 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2459 StringRef Name, bool Enabled) { 2460 // FIXME: This *really* should not be here. We need some way of translating 2461 // options into llvm subtarget features. 2462 if (Name == "sse4") 2463 Name = "sse4.2"; 2464 2465 Features[Name] = Enabled; 2466 2467 if (Name == "mmx") { 2468 setMMXLevel(Features, MMX, Enabled); 2469 } else if (Name == "sse") { 2470 setSSELevel(Features, SSE1, Enabled); 2471 } else if (Name == "sse2") { 2472 setSSELevel(Features, SSE2, Enabled); 2473 } else if (Name == "sse3") { 2474 setSSELevel(Features, SSE3, Enabled); 2475 } else if (Name == "ssse3") { 2476 setSSELevel(Features, SSSE3, Enabled); 2477 } else if (Name == "sse4.2") { 2478 setSSELevel(Features, SSE42, Enabled); 2479 } else if (Name == "sse4.1") { 2480 setSSELevel(Features, SSE41, Enabled); 2481 } else if (Name == "3dnow") { 2482 setMMXLevel(Features, AMD3DNow, Enabled); 2483 } else if (Name == "3dnowa") { 2484 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2485 } else if (Name == "aes") { 2486 if (Enabled) 2487 setSSELevel(Features, SSE2, Enabled); 2488 } else if (Name == "pclmul") { 2489 if (Enabled) 2490 setSSELevel(Features, SSE2, Enabled); 2491 } else if (Name == "avx") { 2492 setSSELevel(Features, AVX, Enabled); 2493 } else if (Name == "avx2") { 2494 setSSELevel(Features, AVX2, Enabled); 2495 } else if (Name == "avx512f") { 2496 setSSELevel(Features, AVX512F, Enabled); 2497 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2498 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2499 if (Enabled) 2500 setSSELevel(Features, AVX512F, Enabled); 2501 } else if (Name == "fma") { 2502 if (Enabled) 2503 setSSELevel(Features, AVX, Enabled); 2504 } else if (Name == "fma4") { 2505 setXOPLevel(Features, FMA4, Enabled); 2506 } else if (Name == "xop") { 2507 setXOPLevel(Features, XOP, Enabled); 2508 } else if (Name == "sse4a") { 2509 setXOPLevel(Features, SSE4A, Enabled); 2510 } else if (Name == "f16c") { 2511 if (Enabled) 2512 setSSELevel(Features, AVX, Enabled); 2513 } else if (Name == "sha") { 2514 if (Enabled) 2515 setSSELevel(Features, SSE2, Enabled); 2516 } 2517 } 2518 2519 /// handleTargetFeatures - Perform initialization based on the user 2520 /// configured set of features. 2521 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2522 DiagnosticsEngine &Diags) { 2523 // Remember the maximum enabled sselevel. 2524 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2525 // Ignore disabled features. 2526 if (Features[i][0] == '-') 2527 continue; 2528 2529 StringRef Feature = StringRef(Features[i]).substr(1); 2530 2531 if (Feature == "aes") { 2532 HasAES = true; 2533 continue; 2534 } 2535 2536 if (Feature == "pclmul") { 2537 HasPCLMUL = true; 2538 continue; 2539 } 2540 2541 if (Feature == "lzcnt") { 2542 HasLZCNT = true; 2543 continue; 2544 } 2545 2546 if (Feature == "rdrnd") { 2547 HasRDRND = true; 2548 continue; 2549 } 2550 2551 if (Feature == "bmi") { 2552 HasBMI = true; 2553 continue; 2554 } 2555 2556 if (Feature == "bmi2") { 2557 HasBMI2 = true; 2558 continue; 2559 } 2560 2561 if (Feature == "popcnt") { 2562 HasPOPCNT = true; 2563 continue; 2564 } 2565 2566 if (Feature == "rtm") { 2567 HasRTM = true; 2568 continue; 2569 } 2570 2571 if (Feature == "prfchw") { 2572 HasPRFCHW = true; 2573 continue; 2574 } 2575 2576 if (Feature == "rdseed") { 2577 HasRDSEED = true; 2578 continue; 2579 } 2580 2581 if (Feature == "adx") { 2582 HasADX = true; 2583 continue; 2584 } 2585 2586 if (Feature == "tbm") { 2587 HasTBM = true; 2588 continue; 2589 } 2590 2591 if (Feature == "fma") { 2592 HasFMA = true; 2593 continue; 2594 } 2595 2596 if (Feature == "f16c") { 2597 HasF16C = true; 2598 continue; 2599 } 2600 2601 if (Feature == "avx512cd") { 2602 HasAVX512CD = true; 2603 continue; 2604 } 2605 2606 if (Feature == "avx512er") { 2607 HasAVX512ER = true; 2608 continue; 2609 } 2610 2611 if (Feature == "avx512pf") { 2612 HasAVX512PF = true; 2613 continue; 2614 } 2615 2616 if (Feature == "avx512dq") { 2617 HasAVX512DQ = true; 2618 continue; 2619 } 2620 2621 if (Feature == "avx512bw") { 2622 HasAVX512BW = true; 2623 continue; 2624 } 2625 2626 if (Feature == "avx512vl") { 2627 HasAVX512VL = true; 2628 continue; 2629 } 2630 2631 if (Feature == "sha") { 2632 HasSHA = true; 2633 continue; 2634 } 2635 2636 if (Feature == "cx16") { 2637 HasCX16 = true; 2638 continue; 2639 } 2640 2641 assert(Features[i][0] == '+' && "Invalid target feature!"); 2642 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2643 .Case("avx512f", AVX512F) 2644 .Case("avx2", AVX2) 2645 .Case("avx", AVX) 2646 .Case("sse4.2", SSE42) 2647 .Case("sse4.1", SSE41) 2648 .Case("ssse3", SSSE3) 2649 .Case("sse3", SSE3) 2650 .Case("sse2", SSE2) 2651 .Case("sse", SSE1) 2652 .Default(NoSSE); 2653 SSELevel = std::max(SSELevel, Level); 2654 2655 MMX3DNowEnum ThreeDNowLevel = 2656 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2657 .Case("3dnowa", AMD3DNowAthlon) 2658 .Case("3dnow", AMD3DNow) 2659 .Case("mmx", MMX) 2660 .Default(NoMMX3DNow); 2661 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2662 2663 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2664 .Case("xop", XOP) 2665 .Case("fma4", FMA4) 2666 .Case("sse4a", SSE4A) 2667 .Default(NoXOP); 2668 XOPLevel = std::max(XOPLevel, XLevel); 2669 } 2670 2671 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2672 // Can't do this earlier because we need to be able to explicitly enable 2673 // popcnt and still disable sse4.2. 2674 if (!HasPOPCNT && SSELevel >= SSE42 && 2675 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2676 HasPOPCNT = true; 2677 Features.push_back("+popcnt"); 2678 } 2679 2680 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2681 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2682 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2683 HasPRFCHW = true; 2684 Features.push_back("+prfchw"); 2685 } 2686 2687 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2688 // matches the selected sse level. 2689 if (FPMath == FP_SSE && SSELevel < SSE1) { 2690 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2691 return false; 2692 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2693 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2694 return false; 2695 } 2696 2697 // Don't tell the backend if we're turning off mmx; it will end up disabling 2698 // SSE, which we don't want. 2699 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2700 // then enable MMX. 2701 std::vector<std::string>::iterator it; 2702 it = std::find(Features.begin(), Features.end(), "-mmx"); 2703 if (it != Features.end()) 2704 Features.erase(it); 2705 else if (SSELevel > NoSSE) 2706 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2707 return true; 2708 } 2709 2710 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2711 /// definitions for this particular subtarget. 2712 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2713 MacroBuilder &Builder) const { 2714 // Target identification. 2715 if (getTriple().getArch() == llvm::Triple::x86_64) { 2716 Builder.defineMacro("__amd64__"); 2717 Builder.defineMacro("__amd64"); 2718 Builder.defineMacro("__x86_64"); 2719 Builder.defineMacro("__x86_64__"); 2720 if (getTriple().getArchName() == "x86_64h") { 2721 Builder.defineMacro("__x86_64h"); 2722 Builder.defineMacro("__x86_64h__"); 2723 } 2724 } else { 2725 DefineStd(Builder, "i386", Opts); 2726 } 2727 2728 // Subtarget options. 2729 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2730 // truly should be based on -mtune options. 2731 switch (CPU) { 2732 case CK_Generic: 2733 break; 2734 case CK_i386: 2735 // The rest are coming from the i386 define above. 2736 Builder.defineMacro("__tune_i386__"); 2737 break; 2738 case CK_i486: 2739 case CK_WinChipC6: 2740 case CK_WinChip2: 2741 case CK_C3: 2742 defineCPUMacros(Builder, "i486"); 2743 break; 2744 case CK_PentiumMMX: 2745 Builder.defineMacro("__pentium_mmx__"); 2746 Builder.defineMacro("__tune_pentium_mmx__"); 2747 // Fallthrough 2748 case CK_i586: 2749 case CK_Pentium: 2750 defineCPUMacros(Builder, "i586"); 2751 defineCPUMacros(Builder, "pentium"); 2752 break; 2753 case CK_Pentium3: 2754 case CK_Pentium3M: 2755 case CK_PentiumM: 2756 Builder.defineMacro("__tune_pentium3__"); 2757 // Fallthrough 2758 case CK_Pentium2: 2759 case CK_C3_2: 2760 Builder.defineMacro("__tune_pentium2__"); 2761 // Fallthrough 2762 case CK_PentiumPro: 2763 Builder.defineMacro("__tune_i686__"); 2764 Builder.defineMacro("__tune_pentiumpro__"); 2765 // Fallthrough 2766 case CK_i686: 2767 Builder.defineMacro("__i686"); 2768 Builder.defineMacro("__i686__"); 2769 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2770 Builder.defineMacro("__pentiumpro"); 2771 Builder.defineMacro("__pentiumpro__"); 2772 break; 2773 case CK_Pentium4: 2774 case CK_Pentium4M: 2775 defineCPUMacros(Builder, "pentium4"); 2776 break; 2777 case CK_Yonah: 2778 case CK_Prescott: 2779 case CK_Nocona: 2780 defineCPUMacros(Builder, "nocona"); 2781 break; 2782 case CK_Core2: 2783 case CK_Penryn: 2784 defineCPUMacros(Builder, "core2"); 2785 break; 2786 case CK_Atom: 2787 defineCPUMacros(Builder, "atom"); 2788 break; 2789 case CK_Silvermont: 2790 defineCPUMacros(Builder, "slm"); 2791 break; 2792 case CK_Corei7: 2793 case CK_Corei7AVX: 2794 case CK_CoreAVXi: 2795 case CK_CoreAVX2: 2796 case CK_Broadwell: 2797 defineCPUMacros(Builder, "corei7"); 2798 break; 2799 case CK_KNL: 2800 defineCPUMacros(Builder, "knl"); 2801 break; 2802 case CK_SKX: 2803 defineCPUMacros(Builder, "skx"); 2804 break; 2805 case CK_K6_2: 2806 Builder.defineMacro("__k6_2__"); 2807 Builder.defineMacro("__tune_k6_2__"); 2808 // Fallthrough 2809 case CK_K6_3: 2810 if (CPU != CK_K6_2) { // In case of fallthrough 2811 // FIXME: GCC may be enabling these in cases where some other k6 2812 // architecture is specified but -m3dnow is explicitly provided. The 2813 // exact semantics need to be determined and emulated here. 2814 Builder.defineMacro("__k6_3__"); 2815 Builder.defineMacro("__tune_k6_3__"); 2816 } 2817 // Fallthrough 2818 case CK_K6: 2819 defineCPUMacros(Builder, "k6"); 2820 break; 2821 case CK_Athlon: 2822 case CK_AthlonThunderbird: 2823 case CK_Athlon4: 2824 case CK_AthlonXP: 2825 case CK_AthlonMP: 2826 defineCPUMacros(Builder, "athlon"); 2827 if (SSELevel != NoSSE) { 2828 Builder.defineMacro("__athlon_sse__"); 2829 Builder.defineMacro("__tune_athlon_sse__"); 2830 } 2831 break; 2832 case CK_K8: 2833 case CK_K8SSE3: 2834 case CK_x86_64: 2835 case CK_Opteron: 2836 case CK_OpteronSSE3: 2837 case CK_Athlon64: 2838 case CK_Athlon64SSE3: 2839 case CK_AthlonFX: 2840 defineCPUMacros(Builder, "k8"); 2841 break; 2842 case CK_AMDFAM10: 2843 defineCPUMacros(Builder, "amdfam10"); 2844 break; 2845 case CK_BTVER1: 2846 defineCPUMacros(Builder, "btver1"); 2847 break; 2848 case CK_BTVER2: 2849 defineCPUMacros(Builder, "btver2"); 2850 break; 2851 case CK_BDVER1: 2852 defineCPUMacros(Builder, "bdver1"); 2853 break; 2854 case CK_BDVER2: 2855 defineCPUMacros(Builder, "bdver2"); 2856 break; 2857 case CK_BDVER3: 2858 defineCPUMacros(Builder, "bdver3"); 2859 break; 2860 case CK_BDVER4: 2861 defineCPUMacros(Builder, "bdver4"); 2862 break; 2863 case CK_Geode: 2864 defineCPUMacros(Builder, "geode"); 2865 break; 2866 } 2867 2868 // Target properties. 2869 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2870 2871 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2872 // functions in glibc header files that use FP Stack inline asm which the 2873 // backend can't deal with (PR879). 2874 Builder.defineMacro("__NO_MATH_INLINES"); 2875 2876 if (HasAES) 2877 Builder.defineMacro("__AES__"); 2878 2879 if (HasPCLMUL) 2880 Builder.defineMacro("__PCLMUL__"); 2881 2882 if (HasLZCNT) 2883 Builder.defineMacro("__LZCNT__"); 2884 2885 if (HasRDRND) 2886 Builder.defineMacro("__RDRND__"); 2887 2888 if (HasBMI) 2889 Builder.defineMacro("__BMI__"); 2890 2891 if (HasBMI2) 2892 Builder.defineMacro("__BMI2__"); 2893 2894 if (HasPOPCNT) 2895 Builder.defineMacro("__POPCNT__"); 2896 2897 if (HasRTM) 2898 Builder.defineMacro("__RTM__"); 2899 2900 if (HasPRFCHW) 2901 Builder.defineMacro("__PRFCHW__"); 2902 2903 if (HasRDSEED) 2904 Builder.defineMacro("__RDSEED__"); 2905 2906 if (HasADX) 2907 Builder.defineMacro("__ADX__"); 2908 2909 if (HasTBM) 2910 Builder.defineMacro("__TBM__"); 2911 2912 switch (XOPLevel) { 2913 case XOP: 2914 Builder.defineMacro("__XOP__"); 2915 case FMA4: 2916 Builder.defineMacro("__FMA4__"); 2917 case SSE4A: 2918 Builder.defineMacro("__SSE4A__"); 2919 case NoXOP: 2920 break; 2921 } 2922 2923 if (HasFMA) 2924 Builder.defineMacro("__FMA__"); 2925 2926 if (HasF16C) 2927 Builder.defineMacro("__F16C__"); 2928 2929 if (HasAVX512CD) 2930 Builder.defineMacro("__AVX512CD__"); 2931 if (HasAVX512ER) 2932 Builder.defineMacro("__AVX512ER__"); 2933 if (HasAVX512PF) 2934 Builder.defineMacro("__AVX512PF__"); 2935 if (HasAVX512DQ) 2936 Builder.defineMacro("__AVX512DQ__"); 2937 if (HasAVX512BW) 2938 Builder.defineMacro("__AVX512BW__"); 2939 if (HasAVX512VL) 2940 Builder.defineMacro("__AVX512VL__"); 2941 2942 if (HasSHA) 2943 Builder.defineMacro("__SHA__"); 2944 2945 if (HasCX16) 2946 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2947 2948 // Each case falls through to the previous one here. 2949 switch (SSELevel) { 2950 case AVX512F: 2951 Builder.defineMacro("__AVX512F__"); 2952 case AVX2: 2953 Builder.defineMacro("__AVX2__"); 2954 case AVX: 2955 Builder.defineMacro("__AVX__"); 2956 case SSE42: 2957 Builder.defineMacro("__SSE4_2__"); 2958 case SSE41: 2959 Builder.defineMacro("__SSE4_1__"); 2960 case SSSE3: 2961 Builder.defineMacro("__SSSE3__"); 2962 case SSE3: 2963 Builder.defineMacro("__SSE3__"); 2964 case SSE2: 2965 Builder.defineMacro("__SSE2__"); 2966 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2967 case SSE1: 2968 Builder.defineMacro("__SSE__"); 2969 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2970 case NoSSE: 2971 break; 2972 } 2973 2974 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2975 switch (SSELevel) { 2976 case AVX512F: 2977 case AVX2: 2978 case AVX: 2979 case SSE42: 2980 case SSE41: 2981 case SSSE3: 2982 case SSE3: 2983 case SSE2: 2984 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2985 break; 2986 case SSE1: 2987 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2988 break; 2989 default: 2990 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2991 } 2992 } 2993 2994 // Each case falls through to the previous one here. 2995 switch (MMX3DNowLevel) { 2996 case AMD3DNowAthlon: 2997 Builder.defineMacro("__3dNOW_A__"); 2998 case AMD3DNow: 2999 Builder.defineMacro("__3dNOW__"); 3000 case MMX: 3001 Builder.defineMacro("__MMX__"); 3002 case NoMMX3DNow: 3003 break; 3004 } 3005 3006 if (CPU >= CK_i486) { 3007 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3008 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3009 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3010 } 3011 if (CPU >= CK_i586) 3012 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3013 } 3014 3015 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3016 return llvm::StringSwitch<bool>(Feature) 3017 .Case("aes", HasAES) 3018 .Case("avx", SSELevel >= AVX) 3019 .Case("avx2", SSELevel >= AVX2) 3020 .Case("avx512f", SSELevel >= AVX512F) 3021 .Case("avx512cd", HasAVX512CD) 3022 .Case("avx512er", HasAVX512ER) 3023 .Case("avx512pf", HasAVX512PF) 3024 .Case("avx512dq", HasAVX512DQ) 3025 .Case("avx512bw", HasAVX512BW) 3026 .Case("avx512vl", HasAVX512VL) 3027 .Case("bmi", HasBMI) 3028 .Case("bmi2", HasBMI2) 3029 .Case("cx16", HasCX16) 3030 .Case("f16c", HasF16C) 3031 .Case("fma", HasFMA) 3032 .Case("fma4", XOPLevel >= FMA4) 3033 .Case("tbm", HasTBM) 3034 .Case("lzcnt", HasLZCNT) 3035 .Case("rdrnd", HasRDRND) 3036 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3037 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3038 .Case("mmx", MMX3DNowLevel >= MMX) 3039 .Case("pclmul", HasPCLMUL) 3040 .Case("popcnt", HasPOPCNT) 3041 .Case("rtm", HasRTM) 3042 .Case("prfchw", HasPRFCHW) 3043 .Case("rdseed", HasRDSEED) 3044 .Case("sha", HasSHA) 3045 .Case("sse", SSELevel >= SSE1) 3046 .Case("sse2", SSELevel >= SSE2) 3047 .Case("sse3", SSELevel >= SSE3) 3048 .Case("ssse3", SSELevel >= SSSE3) 3049 .Case("sse4.1", SSELevel >= SSE41) 3050 .Case("sse4.2", SSELevel >= SSE42) 3051 .Case("sse4a", XOPLevel >= SSE4A) 3052 .Case("x86", true) 3053 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3054 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3055 .Case("xop", XOPLevel >= XOP) 3056 .Default(false); 3057 } 3058 3059 bool 3060 X86TargetInfo::validateAsmConstraint(const char *&Name, 3061 TargetInfo::ConstraintInfo &Info) const { 3062 switch (*Name) { 3063 default: return false; 3064 case 'Y': // first letter of a pair: 3065 switch (*(Name+1)) { 3066 default: return false; 3067 case '0': // First SSE register. 3068 case 't': // Any SSE register, when SSE2 is enabled. 3069 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3070 case 'm': // any MMX register, when inter-unit moves enabled. 3071 break; // falls through to setAllowsRegister. 3072 } 3073 case 'f': // any x87 floating point stack register. 3074 // Constraint 'f' cannot be used for output operands. 3075 if (Info.ConstraintStr[0] == '=') 3076 return false; 3077 3078 Info.setAllowsRegister(); 3079 return true; 3080 case 'a': // eax. 3081 case 'b': // ebx. 3082 case 'c': // ecx. 3083 case 'd': // edx. 3084 case 'S': // esi. 3085 case 'D': // edi. 3086 case 'A': // edx:eax. 3087 case 't': // top of floating point stack. 3088 case 'u': // second from top of floating point stack. 3089 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3090 case 'y': // Any MMX register. 3091 case 'x': // Any SSE register. 3092 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3093 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3094 case 'l': // "Index" registers: any general register that can be used as an 3095 // index in a base+index memory access. 3096 Info.setAllowsRegister(); 3097 return true; 3098 case 'C': // SSE floating point constant. 3099 case 'G': // x87 floating point constant. 3100 case 'e': // 32-bit signed integer constant for use with zero-extending 3101 // x86_64 instructions. 3102 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3103 // x86_64 instructions. 3104 return true; 3105 } 3106 } 3107 3108 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3109 unsigned Size) const { 3110 // Strip off constraint modifiers. 3111 while (Constraint[0] == '=' || 3112 Constraint[0] == '+' || 3113 Constraint[0] == '&') 3114 Constraint = Constraint.substr(1); 3115 3116 return validateOperandSize(Constraint, Size); 3117 } 3118 3119 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3120 unsigned Size) const { 3121 return validateOperandSize(Constraint, Size); 3122 } 3123 3124 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3125 unsigned Size) const { 3126 switch (Constraint[0]) { 3127 default: break; 3128 case 'y': 3129 return Size <= 64; 3130 case 'f': 3131 case 't': 3132 case 'u': 3133 return Size <= 128; 3134 case 'x': 3135 // 256-bit ymm registers can be used if target supports AVX. 3136 return Size <= (SSELevel >= AVX ? 256U : 128U); 3137 } 3138 3139 return true; 3140 } 3141 3142 std::string 3143 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3144 switch (*Constraint) { 3145 case 'a': return std::string("{ax}"); 3146 case 'b': return std::string("{bx}"); 3147 case 'c': return std::string("{cx}"); 3148 case 'd': return std::string("{dx}"); 3149 case 'S': return std::string("{si}"); 3150 case 'D': return std::string("{di}"); 3151 case 'p': // address 3152 return std::string("im"); 3153 case 't': // top of floating point stack. 3154 return std::string("{st}"); 3155 case 'u': // second from top of floating point stack. 3156 return std::string("{st(1)}"); // second from top of floating point stack. 3157 default: 3158 return std::string(1, *Constraint); 3159 } 3160 } 3161 } // end anonymous namespace 3162 3163 namespace { 3164 // X86-32 generic target 3165 class X86_32TargetInfo : public X86TargetInfo { 3166 public: 3167 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3168 DoubleAlign = LongLongAlign = 32; 3169 LongDoubleWidth = 96; 3170 LongDoubleAlign = 32; 3171 SuitableAlign = 128; 3172 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3173 SizeType = UnsignedInt; 3174 PtrDiffType = SignedInt; 3175 IntPtrType = SignedInt; 3176 RegParmMax = 3; 3177 3178 // Use fpret for all types. 3179 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3180 (1 << TargetInfo::Double) | 3181 (1 << TargetInfo::LongDouble)); 3182 3183 // x86-32 has atomics up to 8 bytes 3184 // FIXME: Check that we actually have cmpxchg8b before setting 3185 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3186 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3187 } 3188 BuiltinVaListKind getBuiltinVaListKind() const override { 3189 return TargetInfo::CharPtrBuiltinVaList; 3190 } 3191 3192 int getEHDataRegisterNumber(unsigned RegNo) const override { 3193 if (RegNo == 0) return 0; 3194 if (RegNo == 1) return 2; 3195 return -1; 3196 } 3197 bool validateOperandSize(StringRef Constraint, 3198 unsigned Size) const override { 3199 switch (Constraint[0]) { 3200 default: break; 3201 case 'R': 3202 case 'q': 3203 case 'Q': 3204 case 'a': 3205 case 'b': 3206 case 'c': 3207 case 'd': 3208 case 'S': 3209 case 'D': 3210 return Size <= 32; 3211 case 'A': 3212 return Size <= 64; 3213 } 3214 3215 return X86TargetInfo::validateOperandSize(Constraint, Size); 3216 } 3217 }; 3218 } // end anonymous namespace 3219 3220 namespace { 3221 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3222 public: 3223 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3224 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3225 3226 unsigned getFloatEvalMethod() const override { 3227 unsigned Major, Minor, Micro; 3228 getTriple().getOSVersion(Major, Minor, Micro); 3229 // New NetBSD uses the default rounding mode. 3230 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3231 return X86_32TargetInfo::getFloatEvalMethod(); 3232 // NetBSD before 6.99.26 defaults to "double" rounding. 3233 return 1; 3234 } 3235 }; 3236 } // end anonymous namespace 3237 3238 namespace { 3239 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3240 public: 3241 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3242 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3243 SizeType = UnsignedLong; 3244 IntPtrType = SignedLong; 3245 PtrDiffType = SignedLong; 3246 } 3247 }; 3248 } // end anonymous namespace 3249 3250 namespace { 3251 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3252 public: 3253 BitrigI386TargetInfo(const llvm::Triple &Triple) 3254 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3255 SizeType = UnsignedLong; 3256 IntPtrType = SignedLong; 3257 PtrDiffType = SignedLong; 3258 } 3259 }; 3260 } // end anonymous namespace 3261 3262 namespace { 3263 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3264 public: 3265 DarwinI386TargetInfo(const llvm::Triple &Triple) 3266 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3267 LongDoubleWidth = 128; 3268 LongDoubleAlign = 128; 3269 SuitableAlign = 128; 3270 MaxVectorAlign = 256; 3271 SizeType = UnsignedLong; 3272 IntPtrType = SignedLong; 3273 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3274 HasAlignMac68kSupport = true; 3275 } 3276 3277 }; 3278 } // end anonymous namespace 3279 3280 namespace { 3281 // x86-32 Windows target 3282 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3283 public: 3284 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3285 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3286 WCharType = UnsignedShort; 3287 DoubleAlign = LongLongAlign = 64; 3288 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3289 } 3290 void getTargetDefines(const LangOptions &Opts, 3291 MacroBuilder &Builder) const override { 3292 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3293 } 3294 }; 3295 3296 // x86-32 Windows Visual Studio target 3297 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3298 public: 3299 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3300 : WindowsX86_32TargetInfo(Triple) { 3301 LongDoubleWidth = LongDoubleAlign = 64; 3302 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3303 } 3304 void getTargetDefines(const LangOptions &Opts, 3305 MacroBuilder &Builder) const override { 3306 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3307 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3308 // The value of the following reflects processor type. 3309 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3310 // We lost the original triple, so we use the default. 3311 Builder.defineMacro("_M_IX86", "600"); 3312 } 3313 }; 3314 } // end anonymous namespace 3315 3316 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3317 Builder.defineMacro("__MSVCRT__"); 3318 Builder.defineMacro("__MINGW32__"); 3319 3320 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3321 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3322 // macro anyway for pre-processor compatibility. 3323 if (Opts.MicrosoftExt) 3324 Builder.defineMacro("__declspec", "__declspec"); 3325 else 3326 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3327 3328 if (!Opts.MicrosoftExt) { 3329 // Provide macros for all the calling convention keywords. Provide both 3330 // single and double underscore prefixed variants. These are available on 3331 // x64 as well as x86, even though they have no effect. 3332 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3333 for (const char *CC : CCs) { 3334 std::string GCCSpelling = "__attribute__((__"; 3335 GCCSpelling += CC; 3336 GCCSpelling += "__))"; 3337 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3338 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3339 } 3340 } 3341 } 3342 3343 namespace { 3344 // x86-32 MinGW target 3345 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3346 public: 3347 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3348 : WindowsX86_32TargetInfo(Triple) {} 3349 void getTargetDefines(const LangOptions &Opts, 3350 MacroBuilder &Builder) const override { 3351 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3352 DefineStd(Builder, "WIN32", Opts); 3353 DefineStd(Builder, "WINNT", Opts); 3354 Builder.defineMacro("_X86_"); 3355 addMinGWDefines(Opts, Builder); 3356 } 3357 }; 3358 } // end anonymous namespace 3359 3360 namespace { 3361 // x86-32 Cygwin target 3362 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3363 public: 3364 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3365 : X86_32TargetInfo(Triple) { 3366 TLSSupported = false; 3367 WCharType = UnsignedShort; 3368 DoubleAlign = LongLongAlign = 64; 3369 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3370 } 3371 void getTargetDefines(const LangOptions &Opts, 3372 MacroBuilder &Builder) const override { 3373 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3374 Builder.defineMacro("_X86_"); 3375 Builder.defineMacro("__CYGWIN__"); 3376 Builder.defineMacro("__CYGWIN32__"); 3377 DefineStd(Builder, "unix", Opts); 3378 if (Opts.CPlusPlus) 3379 Builder.defineMacro("_GNU_SOURCE"); 3380 } 3381 }; 3382 } // end anonymous namespace 3383 3384 namespace { 3385 // x86-32 Haiku target 3386 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3387 public: 3388 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3389 SizeType = UnsignedLong; 3390 IntPtrType = SignedLong; 3391 PtrDiffType = SignedLong; 3392 ProcessIDType = SignedLong; 3393 this->UserLabelPrefix = ""; 3394 this->TLSSupported = false; 3395 } 3396 void getTargetDefines(const LangOptions &Opts, 3397 MacroBuilder &Builder) const override { 3398 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3399 Builder.defineMacro("__INTEL__"); 3400 Builder.defineMacro("__HAIKU__"); 3401 } 3402 }; 3403 } // end anonymous namespace 3404 3405 // RTEMS Target 3406 template<typename Target> 3407 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3408 protected: 3409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3410 MacroBuilder &Builder) const override { 3411 // RTEMS defines; list based off of gcc output 3412 3413 Builder.defineMacro("__rtems__"); 3414 Builder.defineMacro("__ELF__"); 3415 } 3416 3417 public: 3418 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3419 this->UserLabelPrefix = ""; 3420 3421 switch (Triple.getArch()) { 3422 default: 3423 case llvm::Triple::x86: 3424 // this->MCountName = ".mcount"; 3425 break; 3426 case llvm::Triple::mips: 3427 case llvm::Triple::mipsel: 3428 case llvm::Triple::ppc: 3429 case llvm::Triple::ppc64: 3430 case llvm::Triple::ppc64le: 3431 // this->MCountName = "_mcount"; 3432 break; 3433 case llvm::Triple::arm: 3434 // this->MCountName = "__mcount"; 3435 break; 3436 } 3437 } 3438 }; 3439 3440 namespace { 3441 // x86-32 RTEMS target 3442 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3443 public: 3444 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3445 SizeType = UnsignedLong; 3446 IntPtrType = SignedLong; 3447 PtrDiffType = SignedLong; 3448 this->UserLabelPrefix = ""; 3449 } 3450 void getTargetDefines(const LangOptions &Opts, 3451 MacroBuilder &Builder) const override { 3452 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3453 Builder.defineMacro("__INTEL__"); 3454 Builder.defineMacro("__rtems__"); 3455 } 3456 }; 3457 } // end anonymous namespace 3458 3459 namespace { 3460 // x86-64 generic target 3461 class X86_64TargetInfo : public X86TargetInfo { 3462 public: 3463 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3464 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3465 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3466 LongDoubleWidth = 128; 3467 LongDoubleAlign = 128; 3468 LargeArrayMinWidth = 128; 3469 LargeArrayAlign = 128; 3470 SuitableAlign = 128; 3471 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3472 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3473 IntPtrType = IsX32 ? SignedInt : SignedLong; 3474 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3475 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3476 RegParmMax = 6; 3477 3478 DescriptionString = (IsX32) 3479 ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128" 3480 : "e-m:e-" "i64:64-f80:128-n8:16:32:64-S128"; 3481 3482 // Use fpret only for long double. 3483 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3484 3485 // Use fp2ret for _Complex long double. 3486 ComplexLongDoubleUsesFP2Ret = true; 3487 3488 // x86-64 has atomics up to 16 bytes. 3489 MaxAtomicPromoteWidth = 128; 3490 MaxAtomicInlineWidth = 128; 3491 } 3492 BuiltinVaListKind getBuiltinVaListKind() const override { 3493 return TargetInfo::X86_64ABIBuiltinVaList; 3494 } 3495 3496 int getEHDataRegisterNumber(unsigned RegNo) const override { 3497 if (RegNo == 0) return 0; 3498 if (RegNo == 1) return 1; 3499 return -1; 3500 } 3501 3502 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3503 return (CC == CC_C || 3504 CC == CC_IntelOclBicc || 3505 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3506 } 3507 3508 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3509 return CC_C; 3510 } 3511 3512 // for x32 we need it here explicitly 3513 bool hasInt128Type() const override { return true; } 3514 }; 3515 } // end anonymous namespace 3516 3517 namespace { 3518 // x86-64 Windows target 3519 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3520 public: 3521 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3522 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3523 WCharType = UnsignedShort; 3524 LongWidth = LongAlign = 32; 3525 DoubleAlign = LongLongAlign = 64; 3526 IntMaxType = SignedLongLong; 3527 Int64Type = SignedLongLong; 3528 SizeType = UnsignedLongLong; 3529 PtrDiffType = SignedLongLong; 3530 IntPtrType = SignedLongLong; 3531 this->UserLabelPrefix = ""; 3532 } 3533 void getTargetDefines(const LangOptions &Opts, 3534 MacroBuilder &Builder) const override { 3535 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3536 Builder.defineMacro("_WIN64"); 3537 } 3538 BuiltinVaListKind getBuiltinVaListKind() const override { 3539 return TargetInfo::CharPtrBuiltinVaList; 3540 } 3541 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3542 return (CC == CC_C || 3543 CC == CC_IntelOclBicc || 3544 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3545 } 3546 }; 3547 } // end anonymous namespace 3548 3549 namespace { 3550 // x86-64 Windows Visual Studio target 3551 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3552 public: 3553 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3554 : WindowsX86_64TargetInfo(Triple) { 3555 LongDoubleWidth = LongDoubleAlign = 64; 3556 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3557 } 3558 void getTargetDefines(const LangOptions &Opts, 3559 MacroBuilder &Builder) const override { 3560 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3561 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3562 Builder.defineMacro("_M_X64"); 3563 Builder.defineMacro("_M_AMD64"); 3564 } 3565 }; 3566 } // end anonymous namespace 3567 3568 namespace { 3569 // x86-64 MinGW target 3570 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3571 public: 3572 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3573 : WindowsX86_64TargetInfo(Triple) {} 3574 void getTargetDefines(const LangOptions &Opts, 3575 MacroBuilder &Builder) const override { 3576 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3577 DefineStd(Builder, "WIN64", Opts); 3578 Builder.defineMacro("__MINGW64__"); 3579 addMinGWDefines(Opts, Builder); 3580 } 3581 }; 3582 } // end anonymous namespace 3583 3584 namespace { 3585 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3586 public: 3587 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3588 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3589 Int64Type = SignedLongLong; 3590 MaxVectorAlign = 256; 3591 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3592 llvm::Triple T = llvm::Triple(Triple); 3593 if (T.isiOS()) 3594 UseSignedCharForObjCBool = false; 3595 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3596 } 3597 }; 3598 } // end anonymous namespace 3599 3600 namespace { 3601 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3602 public: 3603 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3604 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3605 IntMaxType = SignedLongLong; 3606 Int64Type = SignedLongLong; 3607 } 3608 }; 3609 } // end anonymous namespace 3610 3611 namespace { 3612 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3613 public: 3614 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3615 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3616 IntMaxType = SignedLongLong; 3617 Int64Type = SignedLongLong; 3618 } 3619 }; 3620 } 3621 3622 3623 namespace { 3624 class ARMTargetInfo : public TargetInfo { 3625 // Possible FPU choices. 3626 enum FPUMode { 3627 VFP2FPU = (1 << 0), 3628 VFP3FPU = (1 << 1), 3629 VFP4FPU = (1 << 2), 3630 NeonFPU = (1 << 3), 3631 FPARMV8 = (1 << 4) 3632 }; 3633 3634 // Possible HWDiv features. 3635 enum HWDivMode { 3636 HWDivThumb = (1 << 0), 3637 HWDivARM = (1 << 1) 3638 }; 3639 3640 static bool FPUModeIsVFP(FPUMode Mode) { 3641 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3642 } 3643 3644 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3645 static const char * const GCCRegNames[]; 3646 3647 std::string ABI, CPU; 3648 3649 enum { 3650 FP_Default, 3651 FP_VFP, 3652 FP_Neon 3653 } FPMath; 3654 3655 unsigned FPU : 5; 3656 3657 unsigned IsAAPCS : 1; 3658 unsigned IsThumb : 1; 3659 unsigned HWDiv : 2; 3660 3661 // Initialized via features. 3662 unsigned SoftFloat : 1; 3663 unsigned SoftFloatABI : 1; 3664 3665 unsigned CRC : 1; 3666 unsigned Crypto : 1; 3667 3668 // ACLE 6.5.1 Hardware floating point 3669 enum { 3670 HW_FP_HP = (1 << 1), /// half (16-bit) 3671 HW_FP_SP = (1 << 2), /// single (32-bit) 3672 HW_FP_DP = (1 << 3), /// double (64-bit) 3673 }; 3674 uint32_t HW_FP; 3675 3676 static const Builtin::Info BuiltinInfo[]; 3677 3678 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3679 StringRef ArchName = T.getArchName(); 3680 if (T.getArch() == llvm::Triple::arm || 3681 T.getArch() == llvm::Triple::armeb) { 3682 StringRef VersionStr; 3683 if (ArchName.startswith("armv")) 3684 VersionStr = ArchName.substr(4, 1); 3685 else if (ArchName.startswith("armebv")) 3686 VersionStr = ArchName.substr(6, 1); 3687 else 3688 return false; 3689 unsigned Version; 3690 if (VersionStr.getAsInteger(10, Version)) 3691 return false; 3692 return Version >= 6; 3693 } 3694 assert(T.getArch() == llvm::Triple::thumb || 3695 T.getArch() == llvm::Triple::thumbeb); 3696 StringRef VersionStr; 3697 if (ArchName.startswith("thumbv")) 3698 VersionStr = ArchName.substr(6, 1); 3699 else if (ArchName.startswith("thumbebv")) 3700 VersionStr = ArchName.substr(8, 1); 3701 else 3702 return false; 3703 unsigned Version; 3704 if (VersionStr.getAsInteger(10, Version)) 3705 return false; 3706 return Version >= 7; 3707 } 3708 3709 void setABIAAPCS() { 3710 IsAAPCS = true; 3711 3712 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3713 const llvm::Triple &T = getTriple(); 3714 3715 // size_t is unsigned long on MachO-derived environments and NetBSD. 3716 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD) 3717 SizeType = UnsignedLong; 3718 else 3719 SizeType = UnsignedInt; 3720 3721 switch (T.getOS()) { 3722 case llvm::Triple::NetBSD: 3723 WCharType = SignedInt; 3724 break; 3725 case llvm::Triple::Win32: 3726 WCharType = UnsignedShort; 3727 break; 3728 case llvm::Triple::Linux: 3729 default: 3730 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3731 WCharType = UnsignedInt; 3732 break; 3733 } 3734 3735 UseBitFieldTypeAlignment = true; 3736 3737 ZeroLengthBitfieldBoundary = 0; 3738 3739 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3740 // so set preferred for small types to 32. 3741 if (T.isOSBinFormatMachO()) { 3742 DescriptionString = 3743 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3744 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3745 } else if (T.isOSWindows()) { 3746 // FIXME: this is invalid for WindowsCE 3747 assert(!BigEndian && "Windows on ARM does not support big endian"); 3748 DescriptionString = "e" 3749 "-m:e" 3750 "-p:32:32" 3751 "-i64:64" 3752 "-v128:64:128" 3753 "-a:0:32" 3754 "-n32" 3755 "-S64"; 3756 } else { 3757 DescriptionString = 3758 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3759 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3760 } 3761 3762 // FIXME: Enumerated types are variable width in straight AAPCS. 3763 } 3764 3765 void setABIAPCS() { 3766 const llvm::Triple &T = getTriple(); 3767 3768 IsAAPCS = false; 3769 3770 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3771 3772 // size_t is unsigned int on FreeBSD. 3773 if (T.getOS() == llvm::Triple::FreeBSD) 3774 SizeType = UnsignedInt; 3775 else 3776 SizeType = UnsignedLong; 3777 3778 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3779 WCharType = SignedInt; 3780 3781 // Do not respect the alignment of bit-field types when laying out 3782 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3783 UseBitFieldTypeAlignment = false; 3784 3785 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3786 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3787 /// gcc. 3788 ZeroLengthBitfieldBoundary = 32; 3789 3790 if (T.isOSBinFormatMachO()) 3791 DescriptionString = 3792 BigEndian 3793 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3794 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3795 else 3796 DescriptionString = 3797 BigEndian 3798 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3799 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3800 3801 // FIXME: Override "preferred align" for double and long long. 3802 } 3803 3804 public: 3805 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3806 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3807 IsAAPCS(true), HW_FP(0) { 3808 BigEndian = IsBigEndian; 3809 3810 switch (getTriple().getOS()) { 3811 case llvm::Triple::NetBSD: 3812 PtrDiffType = SignedLong; 3813 break; 3814 default: 3815 PtrDiffType = SignedInt; 3816 break; 3817 } 3818 3819 // {} in inline assembly are neon specifiers, not assembly variant 3820 // specifiers. 3821 NoAsmVariants = true; 3822 3823 // FIXME: Should we just treat this as a feature? 3824 IsThumb = getTriple().getArchName().startswith("thumb"); 3825 3826 setABI("aapcs-linux"); 3827 3828 // ARM targets default to using the ARM C++ ABI. 3829 TheCXXABI.set(TargetCXXABI::GenericARM); 3830 3831 // ARM has atomics up to 8 bytes 3832 MaxAtomicPromoteWidth = 64; 3833 if (shouldUseInlineAtomic(getTriple())) 3834 MaxAtomicInlineWidth = 64; 3835 3836 // Do force alignment of members that follow zero length bitfields. If 3837 // the alignment of the zero-length bitfield is greater than the member 3838 // that follows it, `bar', `bar' will be aligned as the type of the 3839 // zero length bitfield. 3840 UseZeroLengthBitfieldAlignment = true; 3841 } 3842 StringRef getABI() const override { return ABI; } 3843 bool setABI(const std::string &Name) override { 3844 ABI = Name; 3845 3846 // The defaults (above) are for AAPCS, check if we need to change them. 3847 // 3848 // FIXME: We need support for -meabi... we could just mangle it into the 3849 // name. 3850 if (Name == "apcs-gnu") { 3851 setABIAPCS(); 3852 return true; 3853 } 3854 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3855 setABIAAPCS(); 3856 return true; 3857 } 3858 return false; 3859 } 3860 3861 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3862 if (IsAAPCS) 3863 Features["aapcs"] = true; 3864 else 3865 Features["apcs"] = true; 3866 3867 StringRef ArchName = getTriple().getArchName(); 3868 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3869 Features["vfp2"] = true; 3870 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3871 CPU == "cortex-a9-mp") { 3872 Features["vfp3"] = true; 3873 Features["neon"] = true; 3874 } 3875 else if (CPU == "cortex-a5") { 3876 Features["vfp4"] = true; 3877 Features["neon"] = true; 3878 } else if (CPU == "swift" || CPU == "cortex-a7" || 3879 CPU == "cortex-a12" || CPU == "cortex-a15" || 3880 CPU == "cortex-a17" || CPU == "krait") { 3881 Features["vfp4"] = true; 3882 Features["neon"] = true; 3883 Features["hwdiv"] = true; 3884 Features["hwdiv-arm"] = true; 3885 } else if (CPU == "cyclone") { 3886 Features["v8fp"] = true; 3887 Features["neon"] = true; 3888 Features["hwdiv"] = true; 3889 Features["hwdiv-arm"] = true; 3890 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3891 Features["fp-armv8"] = true; 3892 Features["neon"] = true; 3893 Features["hwdiv"] = true; 3894 Features["hwdiv-arm"] = true; 3895 Features["crc"] = true; 3896 Features["crypto"] = true; 3897 } else if (CPU == "cortex-r5" || 3898 // Enable the hwdiv extension for all v8a AArch32 cores by 3899 // default. 3900 ArchName == "armv8a" || ArchName == "armv8" || 3901 ArchName == "armebv8a" || ArchName == "armebv8" || 3902 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3903 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3904 Features["hwdiv"] = true; 3905 Features["hwdiv-arm"] = true; 3906 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") { 3907 Features["hwdiv"] = true; 3908 } 3909 } 3910 3911 bool handleTargetFeatures(std::vector<std::string> &Features, 3912 DiagnosticsEngine &Diags) override { 3913 FPU = 0; 3914 CRC = 0; 3915 Crypto = 0; 3916 SoftFloat = SoftFloatABI = false; 3917 HWDiv = 0; 3918 3919 for (const auto &Feature : Features) { 3920 if (Feature == "+soft-float") { 3921 SoftFloat = true; 3922 } else if (Feature == "+soft-float-abi") { 3923 SoftFloatABI = true; 3924 } else if (Feature == "+vfp2") { 3925 FPU |= VFP2FPU; 3926 HW_FP = HW_FP_SP | HW_FP_DP; 3927 } else if (Feature == "+vfp3") { 3928 FPU |= VFP3FPU; 3929 HW_FP = HW_FP_SP | HW_FP_DP; 3930 } else if (Feature == "+vfp4") { 3931 FPU |= VFP4FPU; 3932 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 3933 } else if (Feature == "+fp-armv8") { 3934 FPU |= FPARMV8; 3935 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 3936 } else if (Feature == "+neon") { 3937 FPU |= NeonFPU; 3938 HW_FP = HW_FP_SP | HW_FP_DP; 3939 } else if (Feature == "+hwdiv") { 3940 HWDiv |= HWDivThumb; 3941 } else if (Feature == "+hwdiv-arm") { 3942 HWDiv |= HWDivARM; 3943 } else if (Feature == "+crc") { 3944 CRC = 1; 3945 } else if (Feature == "+crypto") { 3946 Crypto = 1; 3947 } else if (Feature == "+fp-only-sp") { 3948 HW_FP &= ~HW_FP_DP; 3949 } 3950 } 3951 3952 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3953 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3954 return false; 3955 } 3956 3957 if (FPMath == FP_Neon) 3958 Features.push_back("+neonfp"); 3959 else if (FPMath == FP_VFP) 3960 Features.push_back("-neonfp"); 3961 3962 // Remove front-end specific options which the backend handles differently. 3963 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 3964 for (const auto &FEFeature : FrontEndFeatures) { 3965 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 3966 if (Feature != Features.end()) 3967 Features.erase(Feature); 3968 } 3969 3970 return true; 3971 } 3972 3973 bool hasFeature(StringRef Feature) const override { 3974 return llvm::StringSwitch<bool>(Feature) 3975 .Case("arm", true) 3976 .Case("softfloat", SoftFloat) 3977 .Case("thumb", IsThumb) 3978 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3979 .Case("hwdiv", HWDiv & HWDivThumb) 3980 .Case("hwdiv-arm", HWDiv & HWDivARM) 3981 .Default(false); 3982 } 3983 // FIXME: Should we actually have some table instead of these switches? 3984 static const char *getCPUDefineSuffix(StringRef Name) { 3985 return llvm::StringSwitch<const char*>(Name) 3986 .Cases("arm8", "arm810", "4") 3987 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3988 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3989 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3990 .Case("ep9312", "4T") 3991 .Cases("arm10tdmi", "arm1020t", "5T") 3992 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3993 .Case("arm926ej-s", "5TEJ") 3994 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3995 .Cases("xscale", "iwmmxt", "5TE") 3996 .Case("arm1136j-s", "6J") 3997 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3998 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3999 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4000 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 4001 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "7A") 4002 .Cases("cortex-r4", "cortex-r5", "7R") 4003 .Case("swift", "7S") 4004 .Case("cyclone", "8A") 4005 .Case("cortex-m3", "7M") 4006 .Cases("cortex-m4", "cortex-m7", "7EM") 4007 .Case("cortex-m0", "6M") 4008 .Cases("cortex-a53", "cortex-a57", "8A") 4009 .Default(nullptr); 4010 } 4011 static const char *getCPUProfile(StringRef Name) { 4012 return llvm::StringSwitch<const char*>(Name) 4013 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4014 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "A") 4015 .Cases("cortex-a53", "cortex-a57", "A") 4016 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M") 4017 .Cases("cortex-r4", "cortex-r5", "R") 4018 .Default(""); 4019 } 4020 bool setCPU(const std::string &Name) override { 4021 if (!getCPUDefineSuffix(Name)) 4022 return false; 4023 4024 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4025 StringRef Profile = getCPUProfile(Name); 4026 if (Profile == "M" && MaxAtomicInlineWidth) { 4027 MaxAtomicPromoteWidth = 32; 4028 MaxAtomicInlineWidth = 32; 4029 } 4030 4031 CPU = Name; 4032 return true; 4033 } 4034 bool setFPMath(StringRef Name) override; 4035 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4036 unsigned CPUArchVer) const { 4037 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4038 (CPUArch.find('M') != StringRef::npos); 4039 } 4040 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4041 unsigned CPUArchVer) const { 4042 // We check both CPUArchVer and ArchName because when only triple is 4043 // specified, the default CPU is arm1136j-s. 4044 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4045 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4046 } 4047 void getTargetDefines(const LangOptions &Opts, 4048 MacroBuilder &Builder) const override { 4049 // Target identification. 4050 Builder.defineMacro("__arm"); 4051 Builder.defineMacro("__arm__"); 4052 4053 // Target properties. 4054 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4055 4056 StringRef CPUArch = getCPUDefineSuffix(CPU); 4057 unsigned int CPUArchVer; 4058 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4059 llvm_unreachable("Invalid char for architecture version number"); 4060 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4061 4062 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4063 StringRef CPUProfile = getCPUProfile(CPU); 4064 StringRef ArchName = getTriple().getArchName(); 4065 4066 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4067 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4068 if (CPUArch[0] >= '8') { 4069 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4070 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4071 } 4072 4073 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4074 // is not defined for the M-profile. 4075 // NOTE that the deffault profile is assumed to be 'A' 4076 if (CPUProfile.empty() || CPUProfile != "M") 4077 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4078 4079 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4080 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4081 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4082 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4083 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4084 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4085 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4086 4087 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4088 // instruction set such as ARM or Thumb. 4089 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4090 4091 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4092 4093 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4094 if (!CPUProfile.empty()) 4095 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4096 4097 // ACLE 6.5.1 Hardware Floating Point 4098 if (HW_FP) 4099 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4100 4101 // ACLE predefines. 4102 Builder.defineMacro("__ARM_ACLE", "200"); 4103 4104 // Subtarget options. 4105 4106 // FIXME: It's more complicated than this and we don't really support 4107 // interworking. 4108 // Windows on ARM does not "support" interworking 4109 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4110 Builder.defineMacro("__THUMB_INTERWORK__"); 4111 4112 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4113 // Embedded targets on Darwin follow AAPCS, but not EABI. 4114 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4115 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4116 Builder.defineMacro("__ARM_EABI__"); 4117 Builder.defineMacro("__ARM_PCS", "1"); 4118 4119 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4120 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4121 } 4122 4123 if (SoftFloat) 4124 Builder.defineMacro("__SOFTFP__"); 4125 4126 if (CPU == "xscale") 4127 Builder.defineMacro("__XSCALE__"); 4128 4129 if (IsThumb) { 4130 Builder.defineMacro("__THUMBEL__"); 4131 Builder.defineMacro("__thumb__"); 4132 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4133 Builder.defineMacro("__thumb2__"); 4134 } 4135 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4136 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4137 4138 // Note, this is always on in gcc, even though it doesn't make sense. 4139 Builder.defineMacro("__APCS_32__"); 4140 4141 if (FPUModeIsVFP((FPUMode) FPU)) { 4142 Builder.defineMacro("__VFP_FP__"); 4143 if (FPU & VFP2FPU) 4144 Builder.defineMacro("__ARM_VFPV2__"); 4145 if (FPU & VFP3FPU) 4146 Builder.defineMacro("__ARM_VFPV3__"); 4147 if (FPU & VFP4FPU) 4148 Builder.defineMacro("__ARM_VFPV4__"); 4149 } 4150 4151 // This only gets set when Neon instructions are actually available, unlike 4152 // the VFP define, hence the soft float and arch check. This is subtly 4153 // different from gcc, we follow the intent which was that it should be set 4154 // when Neon instructions are actually available. 4155 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4156 Builder.defineMacro("__ARM_NEON"); 4157 Builder.defineMacro("__ARM_NEON__"); 4158 } 4159 4160 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4161 Opts.ShortWChar ? "2" : "4"); 4162 4163 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4164 Opts.ShortEnums ? "1" : "4"); 4165 4166 if (CRC) 4167 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4168 4169 if (Crypto) 4170 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4171 4172 if (CPUArchVer >= 6 && CPUArch != "6M") { 4173 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4174 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4175 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4176 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4177 } 4178 } 4179 void getTargetBuiltins(const Builtin::Info *&Records, 4180 unsigned &NumRecords) const override { 4181 Records = BuiltinInfo; 4182 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4183 } 4184 bool isCLZForZeroUndef() const override { return false; } 4185 BuiltinVaListKind getBuiltinVaListKind() const override { 4186 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4187 } 4188 void getGCCRegNames(const char * const *&Names, 4189 unsigned &NumNames) const override; 4190 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4191 unsigned &NumAliases) const override; 4192 bool validateAsmConstraint(const char *&Name, 4193 TargetInfo::ConstraintInfo &Info) const override { 4194 switch (*Name) { 4195 default: break; 4196 case 'l': // r0-r7 4197 case 'h': // r8-r15 4198 case 'w': // VFP Floating point register single precision 4199 case 'P': // VFP Floating point register double precision 4200 Info.setAllowsRegister(); 4201 return true; 4202 case 'Q': // A memory address that is a single base register. 4203 Info.setAllowsMemory(); 4204 return true; 4205 case 'U': // a memory reference... 4206 switch (Name[1]) { 4207 case 'q': // ...ARMV4 ldrsb 4208 case 'v': // ...VFP load/store (reg+constant offset) 4209 case 'y': // ...iWMMXt load/store 4210 case 't': // address valid for load/store opaque types wider 4211 // than 128-bits 4212 case 'n': // valid address for Neon doubleword vector load/store 4213 case 'm': // valid address for Neon element and structure load/store 4214 case 's': // valid address for non-offset loads/stores of quad-word 4215 // values in four ARM registers 4216 Info.setAllowsMemory(); 4217 Name++; 4218 return true; 4219 } 4220 } 4221 return false; 4222 } 4223 std::string convertConstraint(const char *&Constraint) const override { 4224 std::string R; 4225 switch (*Constraint) { 4226 case 'U': // Two-character constraint; add "^" hint for later parsing. 4227 R = std::string("^") + std::string(Constraint, 2); 4228 Constraint++; 4229 break; 4230 case 'p': // 'p' should be translated to 'r' by default. 4231 R = std::string("r"); 4232 break; 4233 default: 4234 return std::string(1, *Constraint); 4235 } 4236 return R; 4237 } 4238 bool 4239 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4240 std::string &SuggestedModifier) const override { 4241 bool isOutput = (Constraint[0] == '='); 4242 bool isInOut = (Constraint[0] == '+'); 4243 4244 // Strip off constraint modifiers. 4245 while (Constraint[0] == '=' || 4246 Constraint[0] == '+' || 4247 Constraint[0] == '&') 4248 Constraint = Constraint.substr(1); 4249 4250 switch (Constraint[0]) { 4251 default: break; 4252 case 'r': { 4253 switch (Modifier) { 4254 default: 4255 return (isInOut || isOutput || Size <= 64); 4256 case 'q': 4257 // A register of size 32 cannot fit a vector type. 4258 return false; 4259 } 4260 } 4261 } 4262 4263 return true; 4264 } 4265 const char *getClobbers() const override { 4266 // FIXME: Is this really right? 4267 return ""; 4268 } 4269 4270 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4271 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4272 } 4273 4274 int getEHDataRegisterNumber(unsigned RegNo) const override { 4275 if (RegNo == 0) return 0; 4276 if (RegNo == 1) return 1; 4277 return -1; 4278 } 4279 }; 4280 4281 bool ARMTargetInfo::setFPMath(StringRef Name) { 4282 if (Name == "neon") { 4283 FPMath = FP_Neon; 4284 return true; 4285 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4286 Name == "vfp4") { 4287 FPMath = FP_VFP; 4288 return true; 4289 } 4290 return false; 4291 } 4292 4293 const char * const ARMTargetInfo::GCCRegNames[] = { 4294 // Integer registers 4295 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4296 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4297 4298 // Float registers 4299 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4300 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4301 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4302 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4303 4304 // Double registers 4305 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4306 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4307 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4308 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4309 4310 // Quad registers 4311 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4312 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4313 }; 4314 4315 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4316 unsigned &NumNames) const { 4317 Names = GCCRegNames; 4318 NumNames = llvm::array_lengthof(GCCRegNames); 4319 } 4320 4321 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4322 { { "a1" }, "r0" }, 4323 { { "a2" }, "r1" }, 4324 { { "a3" }, "r2" }, 4325 { { "a4" }, "r3" }, 4326 { { "v1" }, "r4" }, 4327 { { "v2" }, "r5" }, 4328 { { "v3" }, "r6" }, 4329 { { "v4" }, "r7" }, 4330 { { "v5" }, "r8" }, 4331 { { "v6", "rfp" }, "r9" }, 4332 { { "sl" }, "r10" }, 4333 { { "fp" }, "r11" }, 4334 { { "ip" }, "r12" }, 4335 { { "r13" }, "sp" }, 4336 { { "r14" }, "lr" }, 4337 { { "r15" }, "pc" }, 4338 // The S, D and Q registers overlap, but aren't really aliases; we 4339 // don't want to substitute one of these for a different-sized one. 4340 }; 4341 4342 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4343 unsigned &NumAliases) const { 4344 Aliases = GCCRegAliases; 4345 NumAliases = llvm::array_lengthof(GCCRegAliases); 4346 } 4347 4348 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4349 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4350 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4351 ALL_LANGUAGES }, 4352 #include "clang/Basic/BuiltinsNEON.def" 4353 4354 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4355 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4356 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4357 ALL_LANGUAGES }, 4358 #include "clang/Basic/BuiltinsARM.def" 4359 }; 4360 4361 class ARMleTargetInfo : public ARMTargetInfo { 4362 public: 4363 ARMleTargetInfo(const llvm::Triple &Triple) 4364 : ARMTargetInfo(Triple, false) { } 4365 virtual void getTargetDefines(const LangOptions &Opts, 4366 MacroBuilder &Builder) const { 4367 Builder.defineMacro("__ARMEL__"); 4368 ARMTargetInfo::getTargetDefines(Opts, Builder); 4369 } 4370 }; 4371 4372 class ARMbeTargetInfo : public ARMTargetInfo { 4373 public: 4374 ARMbeTargetInfo(const llvm::Triple &Triple) 4375 : ARMTargetInfo(Triple, true) { } 4376 virtual void getTargetDefines(const LangOptions &Opts, 4377 MacroBuilder &Builder) const { 4378 Builder.defineMacro("__ARMEB__"); 4379 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4380 ARMTargetInfo::getTargetDefines(Opts, Builder); 4381 } 4382 }; 4383 } // end anonymous namespace. 4384 4385 namespace { 4386 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4387 const llvm::Triple Triple; 4388 public: 4389 WindowsARMTargetInfo(const llvm::Triple &Triple) 4390 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4391 TLSSupported = false; 4392 WCharType = UnsignedShort; 4393 SizeType = UnsignedInt; 4394 UserLabelPrefix = ""; 4395 } 4396 void getVisualStudioDefines(const LangOptions &Opts, 4397 MacroBuilder &Builder) const { 4398 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4399 4400 // FIXME: this is invalid for WindowsCE 4401 Builder.defineMacro("_M_ARM_NT", "1"); 4402 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4403 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4404 4405 assert((Triple.getArch() == llvm::Triple::arm || 4406 Triple.getArch() == llvm::Triple::thumb) && 4407 "invalid architecture for Windows ARM target info"); 4408 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4409 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4410 4411 // TODO map the complete set of values 4412 // 31: VFPv3 40: VFPv4 4413 Builder.defineMacro("_M_ARM_FP", "31"); 4414 } 4415 BuiltinVaListKind getBuiltinVaListKind() const override { 4416 return TargetInfo::CharPtrBuiltinVaList; 4417 } 4418 }; 4419 4420 // Windows ARM + Itanium C++ ABI Target 4421 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4422 public: 4423 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4424 : WindowsARMTargetInfo(Triple) { 4425 TheCXXABI.set(TargetCXXABI::GenericARM); 4426 } 4427 4428 void getTargetDefines(const LangOptions &Opts, 4429 MacroBuilder &Builder) const override { 4430 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4431 4432 if (Opts.MSVCCompat) 4433 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4434 } 4435 }; 4436 4437 // Windows ARM, MS (C++) ABI 4438 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4439 public: 4440 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4441 : WindowsARMTargetInfo(Triple) { 4442 TheCXXABI.set(TargetCXXABI::Microsoft); 4443 } 4444 4445 void getTargetDefines(const LangOptions &Opts, 4446 MacroBuilder &Builder) const override { 4447 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4448 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4449 } 4450 }; 4451 } 4452 4453 4454 namespace { 4455 class DarwinARMTargetInfo : 4456 public DarwinTargetInfo<ARMleTargetInfo> { 4457 protected: 4458 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4459 MacroBuilder &Builder) const override { 4460 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4461 } 4462 4463 public: 4464 DarwinARMTargetInfo(const llvm::Triple &Triple) 4465 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4466 HasAlignMac68kSupport = true; 4467 // iOS always has 64-bit atomic instructions. 4468 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4469 MaxAtomicInlineWidth = 64; 4470 4471 // Darwin on iOS uses a variant of the ARM C++ ABI. 4472 TheCXXABI.set(TargetCXXABI::iOS); 4473 } 4474 }; 4475 } // end anonymous namespace. 4476 4477 4478 namespace { 4479 class AArch64TargetInfo : public TargetInfo { 4480 virtual void setDescriptionString() = 0; 4481 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4482 static const char *const GCCRegNames[]; 4483 4484 enum FPUModeEnum { 4485 FPUMode, 4486 NeonMode 4487 }; 4488 4489 unsigned FPU; 4490 unsigned CRC; 4491 unsigned Crypto; 4492 4493 static const Builtin::Info BuiltinInfo[]; 4494 4495 std::string ABI; 4496 4497 public: 4498 AArch64TargetInfo(const llvm::Triple &Triple) 4499 : TargetInfo(Triple), ABI("aapcs") { 4500 4501 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4502 WCharType = SignedInt; 4503 4504 // NetBSD apparently prefers consistency across ARM targets to consistency 4505 // across 64-bit targets. 4506 Int64Type = SignedLongLong; 4507 IntMaxType = SignedLongLong; 4508 } else { 4509 WCharType = UnsignedInt; 4510 Int64Type = SignedLong; 4511 IntMaxType = SignedLong; 4512 } 4513 4514 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4515 MaxVectorAlign = 128; 4516 RegParmMax = 8; 4517 MaxAtomicInlineWidth = 128; 4518 MaxAtomicPromoteWidth = 128; 4519 4520 LongDoubleWidth = LongDoubleAlign = 128; 4521 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4522 4523 // {} in inline assembly are neon specifiers, not assembly variant 4524 // specifiers. 4525 NoAsmVariants = true; 4526 4527 // AArch64 targets default to using the ARM C++ ABI. 4528 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4529 } 4530 4531 StringRef getABI() const override { return ABI; } 4532 virtual bool setABI(const std::string &Name) override { 4533 if (Name != "aapcs" && Name != "darwinpcs") 4534 return false; 4535 4536 ABI = Name; 4537 return true; 4538 } 4539 4540 virtual bool setCPU(const std::string &Name) override { 4541 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4542 .Case("generic", true) 4543 .Cases("cortex-a53", "cortex-a57", true) 4544 .Case("cyclone", true) 4545 .Default(false); 4546 return CPUKnown; 4547 } 4548 4549 virtual void getTargetDefines(const LangOptions &Opts, 4550 MacroBuilder &Builder) const override { 4551 // Target identification. 4552 Builder.defineMacro("__aarch64__"); 4553 4554 // Target properties. 4555 Builder.defineMacro("_LP64"); 4556 Builder.defineMacro("__LP64__"); 4557 4558 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4559 Builder.defineMacro("__ARM_ACLE", "200"); 4560 Builder.defineMacro("__ARM_ARCH", "8"); 4561 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4562 4563 Builder.defineMacro("__ARM_64BIT_STATE"); 4564 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4565 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4566 4567 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4568 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4569 Builder.defineMacro("__ARM_FEATURE_FMA"); 4570 Builder.defineMacro("__ARM_FEATURE_DIV"); 4571 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4572 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4573 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4574 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4575 4576 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4577 4578 // 0xe implies support for half, single and double precision operations. 4579 Builder.defineMacro("__ARM_FP", "0xe"); 4580 4581 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4582 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4583 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4584 4585 if (Opts.FastMath || Opts.FiniteMathOnly) 4586 Builder.defineMacro("__ARM_FP_FAST"); 4587 4588 if (Opts.C99 && !Opts.Freestanding) 4589 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4590 4591 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4592 4593 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4594 Opts.ShortEnums ? "1" : "4"); 4595 4596 if (FPU == NeonMode) { 4597 Builder.defineMacro("__ARM_NEON"); 4598 // 64-bit NEON supports half, single and double precision operations. 4599 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4600 } 4601 4602 if (CRC) 4603 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4604 4605 if (Crypto) 4606 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4607 } 4608 4609 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4610 unsigned &NumRecords) const override { 4611 Records = BuiltinInfo; 4612 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4613 } 4614 4615 virtual bool hasFeature(StringRef Feature) const override { 4616 return Feature == "aarch64" || 4617 Feature == "arm64" || 4618 (Feature == "neon" && FPU == NeonMode); 4619 } 4620 4621 bool handleTargetFeatures(std::vector<std::string> &Features, 4622 DiagnosticsEngine &Diags) override { 4623 FPU = FPUMode; 4624 CRC = 0; 4625 Crypto = 0; 4626 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4627 if (Features[i] == "+neon") 4628 FPU = NeonMode; 4629 if (Features[i] == "+crc") 4630 CRC = 1; 4631 if (Features[i] == "+crypto") 4632 Crypto = 1; 4633 } 4634 4635 setDescriptionString(); 4636 4637 return true; 4638 } 4639 4640 virtual bool isCLZForZeroUndef() const override { return false; } 4641 4642 virtual BuiltinVaListKind getBuiltinVaListKind() const override { 4643 return TargetInfo::AArch64ABIBuiltinVaList; 4644 } 4645 4646 virtual void getGCCRegNames(const char *const *&Names, 4647 unsigned &NumNames) const override; 4648 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4649 unsigned &NumAliases) const override; 4650 4651 virtual bool validateAsmConstraint(const char *&Name, 4652 TargetInfo::ConstraintInfo &Info) const override { 4653 switch (*Name) { 4654 default: 4655 return false; 4656 case 'w': // Floating point and SIMD registers (V0-V31) 4657 Info.setAllowsRegister(); 4658 return true; 4659 case 'I': // Constant that can be used with an ADD instruction 4660 case 'J': // Constant that can be used with a SUB instruction 4661 case 'K': // Constant that can be used with a 32-bit logical instruction 4662 case 'L': // Constant that can be used with a 64-bit logical instruction 4663 case 'M': // Constant that can be used as a 32-bit MOV immediate 4664 case 'N': // Constant that can be used as a 64-bit MOV immediate 4665 case 'Y': // Floating point constant zero 4666 case 'Z': // Integer constant zero 4667 return true; 4668 case 'Q': // A memory reference with base register and no offset 4669 Info.setAllowsMemory(); 4670 return true; 4671 case 'S': // A symbolic address 4672 Info.setAllowsRegister(); 4673 return true; 4674 case 'U': 4675 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4676 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4677 // Usa: An absolute symbolic address 4678 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4679 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4680 case 'z': // Zero register, wzr or xzr 4681 Info.setAllowsRegister(); 4682 return true; 4683 case 'x': // Floating point and SIMD registers (V0-V15) 4684 Info.setAllowsRegister(); 4685 return true; 4686 } 4687 return false; 4688 } 4689 4690 bool 4691 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4692 std::string &SuggestedModifier) const override { 4693 // Strip off constraint modifiers. 4694 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4695 Constraint = Constraint.substr(1); 4696 4697 switch (Constraint[0]) { 4698 default: 4699 return true; 4700 case 'z': 4701 case 'r': { 4702 switch (Modifier) { 4703 case 'x': 4704 case 'w': 4705 // For now assume that the person knows what they're 4706 // doing with the modifier. 4707 return true; 4708 default: 4709 // By default an 'r' constraint will be in the 'x' 4710 // registers. 4711 if (Size == 64) 4712 return true; 4713 4714 SuggestedModifier = "w"; 4715 return false; 4716 } 4717 } 4718 } 4719 } 4720 4721 virtual const char *getClobbers() const override { return ""; } 4722 4723 int getEHDataRegisterNumber(unsigned RegNo) const override { 4724 if (RegNo == 0) 4725 return 0; 4726 if (RegNo == 1) 4727 return 1; 4728 return -1; 4729 } 4730 }; 4731 4732 const char *const AArch64TargetInfo::GCCRegNames[] = { 4733 // 32-bit Integer registers 4734 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4735 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4736 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4737 4738 // 64-bit Integer registers 4739 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4740 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4741 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4742 4743 // 32-bit floating point regsisters 4744 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4745 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4746 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4747 4748 // 64-bit floating point regsisters 4749 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4750 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4751 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4752 4753 // Vector registers 4754 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4755 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4756 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4757 }; 4758 4759 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4760 unsigned &NumNames) const { 4761 Names = GCCRegNames; 4762 NumNames = llvm::array_lengthof(GCCRegNames); 4763 } 4764 4765 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4766 { { "w31" }, "wsp" }, 4767 { { "x29" }, "fp" }, 4768 { { "x30" }, "lr" }, 4769 { { "x31" }, "sp" }, 4770 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4771 // don't want to substitute one of these for a different-sized one. 4772 }; 4773 4774 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4775 unsigned &NumAliases) const { 4776 Aliases = GCCRegAliases; 4777 NumAliases = llvm::array_lengthof(GCCRegAliases); 4778 } 4779 4780 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4781 #define BUILTIN(ID, TYPE, ATTRS) \ 4782 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4783 #include "clang/Basic/BuiltinsNEON.def" 4784 4785 #define BUILTIN(ID, TYPE, ATTRS) \ 4786 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4787 #include "clang/Basic/BuiltinsAArch64.def" 4788 }; 4789 4790 class AArch64leTargetInfo : public AArch64TargetInfo { 4791 void setDescriptionString() override { 4792 if (getTriple().isOSBinFormatMachO()) 4793 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4794 else 4795 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4796 } 4797 4798 public: 4799 AArch64leTargetInfo(const llvm::Triple &Triple) 4800 : AArch64TargetInfo(Triple) { 4801 BigEndian = false; 4802 } 4803 void getTargetDefines(const LangOptions &Opts, 4804 MacroBuilder &Builder) const override { 4805 Builder.defineMacro("__AARCH64EL__"); 4806 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4807 } 4808 }; 4809 4810 class AArch64beTargetInfo : public AArch64TargetInfo { 4811 void setDescriptionString() override { 4812 assert(!getTriple().isOSBinFormatMachO()); 4813 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4814 } 4815 4816 public: 4817 AArch64beTargetInfo(const llvm::Triple &Triple) 4818 : AArch64TargetInfo(Triple) { } 4819 void getTargetDefines(const LangOptions &Opts, 4820 MacroBuilder &Builder) const override { 4821 Builder.defineMacro("__AARCH64EB__"); 4822 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4823 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4824 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4825 } 4826 }; 4827 } // end anonymous namespace. 4828 4829 namespace { 4830 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 4831 protected: 4832 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4833 MacroBuilder &Builder) const override { 4834 Builder.defineMacro("__AARCH64_SIMD__"); 4835 Builder.defineMacro("__ARM64_ARCH_8__"); 4836 Builder.defineMacro("__ARM_NEON__"); 4837 Builder.defineMacro("__LITTLE_ENDIAN__"); 4838 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4839 Builder.defineMacro("__arm64", "1"); 4840 Builder.defineMacro("__arm64__", "1"); 4841 4842 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4843 } 4844 4845 public: 4846 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 4847 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 4848 Int64Type = SignedLongLong; 4849 WCharType = SignedInt; 4850 UseSignedCharForObjCBool = false; 4851 4852 LongDoubleWidth = LongDoubleAlign = 64; 4853 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4854 4855 TheCXXABI.set(TargetCXXABI::iOS64); 4856 } 4857 4858 virtual BuiltinVaListKind getBuiltinVaListKind() const override { 4859 return TargetInfo::CharPtrBuiltinVaList; 4860 } 4861 }; 4862 } // end anonymous namespace 4863 4864 namespace { 4865 // Hexagon abstract base class 4866 class HexagonTargetInfo : public TargetInfo { 4867 static const Builtin::Info BuiltinInfo[]; 4868 static const char * const GCCRegNames[]; 4869 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4870 std::string CPU; 4871 public: 4872 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4873 BigEndian = false; 4874 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4875 4876 // {} in inline assembly are packet specifiers, not assembly variant 4877 // specifiers. 4878 NoAsmVariants = true; 4879 } 4880 4881 void getTargetBuiltins(const Builtin::Info *&Records, 4882 unsigned &NumRecords) const override { 4883 Records = BuiltinInfo; 4884 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4885 } 4886 4887 bool validateAsmConstraint(const char *&Name, 4888 TargetInfo::ConstraintInfo &Info) const override { 4889 return true; 4890 } 4891 4892 void getTargetDefines(const LangOptions &Opts, 4893 MacroBuilder &Builder) const override; 4894 4895 bool hasFeature(StringRef Feature) const override { 4896 return Feature == "hexagon"; 4897 } 4898 4899 BuiltinVaListKind getBuiltinVaListKind() const override { 4900 return TargetInfo::CharPtrBuiltinVaList; 4901 } 4902 void getGCCRegNames(const char * const *&Names, 4903 unsigned &NumNames) const override; 4904 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4905 unsigned &NumAliases) const override; 4906 const char *getClobbers() const override { 4907 return ""; 4908 } 4909 4910 static const char *getHexagonCPUSuffix(StringRef Name) { 4911 return llvm::StringSwitch<const char*>(Name) 4912 .Case("hexagonv4", "4") 4913 .Case("hexagonv5", "5") 4914 .Default(nullptr); 4915 } 4916 4917 bool setCPU(const std::string &Name) override { 4918 if (!getHexagonCPUSuffix(Name)) 4919 return false; 4920 4921 CPU = Name; 4922 return true; 4923 } 4924 }; 4925 4926 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4927 MacroBuilder &Builder) const { 4928 Builder.defineMacro("qdsp6"); 4929 Builder.defineMacro("__qdsp6", "1"); 4930 Builder.defineMacro("__qdsp6__", "1"); 4931 4932 Builder.defineMacro("hexagon"); 4933 Builder.defineMacro("__hexagon", "1"); 4934 Builder.defineMacro("__hexagon__", "1"); 4935 4936 if(CPU == "hexagonv1") { 4937 Builder.defineMacro("__HEXAGON_V1__"); 4938 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4939 if(Opts.HexagonQdsp6Compat) { 4940 Builder.defineMacro("__QDSP6_V1__"); 4941 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4942 } 4943 } 4944 else if(CPU == "hexagonv2") { 4945 Builder.defineMacro("__HEXAGON_V2__"); 4946 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4947 if(Opts.HexagonQdsp6Compat) { 4948 Builder.defineMacro("__QDSP6_V2__"); 4949 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4950 } 4951 } 4952 else if(CPU == "hexagonv3") { 4953 Builder.defineMacro("__HEXAGON_V3__"); 4954 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4955 if(Opts.HexagonQdsp6Compat) { 4956 Builder.defineMacro("__QDSP6_V3__"); 4957 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4958 } 4959 } 4960 else if(CPU == "hexagonv4") { 4961 Builder.defineMacro("__HEXAGON_V4__"); 4962 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4963 if(Opts.HexagonQdsp6Compat) { 4964 Builder.defineMacro("__QDSP6_V4__"); 4965 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4966 } 4967 } 4968 else if(CPU == "hexagonv5") { 4969 Builder.defineMacro("__HEXAGON_V5__"); 4970 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4971 if(Opts.HexagonQdsp6Compat) { 4972 Builder.defineMacro("__QDSP6_V5__"); 4973 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4974 } 4975 } 4976 } 4977 4978 const char * const HexagonTargetInfo::GCCRegNames[] = { 4979 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4980 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4981 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4982 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4983 "p0", "p1", "p2", "p3", 4984 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4985 }; 4986 4987 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4988 unsigned &NumNames) const { 4989 Names = GCCRegNames; 4990 NumNames = llvm::array_lengthof(GCCRegNames); 4991 } 4992 4993 4994 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4995 { { "sp" }, "r29" }, 4996 { { "fp" }, "r30" }, 4997 { { "lr" }, "r31" }, 4998 }; 4999 5000 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5001 unsigned &NumAliases) const { 5002 Aliases = GCCRegAliases; 5003 NumAliases = llvm::array_lengthof(GCCRegAliases); 5004 } 5005 5006 5007 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5008 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5010 ALL_LANGUAGES }, 5011 #include "clang/Basic/BuiltinsHexagon.def" 5012 }; 5013 } 5014 5015 5016 namespace { 5017 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5018 class SparcTargetInfo : public TargetInfo { 5019 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5020 static const char * const GCCRegNames[]; 5021 bool SoftFloat; 5022 public: 5023 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5024 5025 bool handleTargetFeatures(std::vector<std::string> &Features, 5026 DiagnosticsEngine &Diags) override { 5027 SoftFloat = false; 5028 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5029 if (Features[i] == "+soft-float") 5030 SoftFloat = true; 5031 return true; 5032 } 5033 void getTargetDefines(const LangOptions &Opts, 5034 MacroBuilder &Builder) const override { 5035 DefineStd(Builder, "sparc", Opts); 5036 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5037 5038 if (SoftFloat) 5039 Builder.defineMacro("SOFT_FLOAT", "1"); 5040 } 5041 5042 bool hasFeature(StringRef Feature) const override { 5043 return llvm::StringSwitch<bool>(Feature) 5044 .Case("softfloat", SoftFloat) 5045 .Case("sparc", true) 5046 .Default(false); 5047 } 5048 5049 void getTargetBuiltins(const Builtin::Info *&Records, 5050 unsigned &NumRecords) const override { 5051 // FIXME: Implement! 5052 } 5053 BuiltinVaListKind getBuiltinVaListKind() const override { 5054 return TargetInfo::VoidPtrBuiltinVaList; 5055 } 5056 void getGCCRegNames(const char * const *&Names, 5057 unsigned &NumNames) const override; 5058 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5059 unsigned &NumAliases) const override; 5060 bool validateAsmConstraint(const char *&Name, 5061 TargetInfo::ConstraintInfo &info) const override { 5062 // FIXME: Implement! 5063 return false; 5064 } 5065 const char *getClobbers() const override { 5066 // FIXME: Implement! 5067 return ""; 5068 } 5069 }; 5070 5071 const char * const SparcTargetInfo::GCCRegNames[] = { 5072 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5073 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5074 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5075 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5076 }; 5077 5078 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5079 unsigned &NumNames) const { 5080 Names = GCCRegNames; 5081 NumNames = llvm::array_lengthof(GCCRegNames); 5082 } 5083 5084 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5085 { { "g0" }, "r0" }, 5086 { { "g1" }, "r1" }, 5087 { { "g2" }, "r2" }, 5088 { { "g3" }, "r3" }, 5089 { { "g4" }, "r4" }, 5090 { { "g5" }, "r5" }, 5091 { { "g6" }, "r6" }, 5092 { { "g7" }, "r7" }, 5093 { { "o0" }, "r8" }, 5094 { { "o1" }, "r9" }, 5095 { { "o2" }, "r10" }, 5096 { { "o3" }, "r11" }, 5097 { { "o4" }, "r12" }, 5098 { { "o5" }, "r13" }, 5099 { { "o6", "sp" }, "r14" }, 5100 { { "o7" }, "r15" }, 5101 { { "l0" }, "r16" }, 5102 { { "l1" }, "r17" }, 5103 { { "l2" }, "r18" }, 5104 { { "l3" }, "r19" }, 5105 { { "l4" }, "r20" }, 5106 { { "l5" }, "r21" }, 5107 { { "l6" }, "r22" }, 5108 { { "l7" }, "r23" }, 5109 { { "i0" }, "r24" }, 5110 { { "i1" }, "r25" }, 5111 { { "i2" }, "r26" }, 5112 { { "i3" }, "r27" }, 5113 { { "i4" }, "r28" }, 5114 { { "i5" }, "r29" }, 5115 { { "i6", "fp" }, "r30" }, 5116 { { "i7" }, "r31" }, 5117 }; 5118 5119 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5120 unsigned &NumAliases) const { 5121 Aliases = GCCRegAliases; 5122 NumAliases = llvm::array_lengthof(GCCRegAliases); 5123 } 5124 5125 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5126 class SparcV8TargetInfo : public SparcTargetInfo { 5127 public: 5128 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5129 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5130 } 5131 5132 void getTargetDefines(const LangOptions &Opts, 5133 MacroBuilder &Builder) const override { 5134 SparcTargetInfo::getTargetDefines(Opts, Builder); 5135 Builder.defineMacro("__sparcv8"); 5136 } 5137 }; 5138 5139 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5140 class SparcV9TargetInfo : public SparcTargetInfo { 5141 public: 5142 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5143 // FIXME: Support Sparc quad-precision long double? 5144 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5145 // This is an LP64 platform. 5146 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5147 5148 // OpenBSD uses long long for int64_t and intmax_t. 5149 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5150 IntMaxType = SignedLongLong; 5151 else 5152 IntMaxType = SignedLong; 5153 Int64Type = IntMaxType; 5154 5155 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5156 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5157 LongDoubleWidth = 128; 5158 LongDoubleAlign = 128; 5159 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5160 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5161 } 5162 5163 void getTargetDefines(const LangOptions &Opts, 5164 MacroBuilder &Builder) const override { 5165 SparcTargetInfo::getTargetDefines(Opts, Builder); 5166 Builder.defineMacro("__sparcv9"); 5167 Builder.defineMacro("__arch64__"); 5168 // Solaris doesn't need these variants, but the BSDs do. 5169 if (getTriple().getOS() != llvm::Triple::Solaris) { 5170 Builder.defineMacro("__sparc64__"); 5171 Builder.defineMacro("__sparc_v9__"); 5172 Builder.defineMacro("__sparcv9__"); 5173 } 5174 } 5175 5176 bool setCPU(const std::string &Name) override { 5177 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5178 .Case("v9", true) 5179 .Case("ultrasparc", true) 5180 .Case("ultrasparc3", true) 5181 .Case("niagara", true) 5182 .Case("niagara2", true) 5183 .Case("niagara3", true) 5184 .Case("niagara4", true) 5185 .Default(false); 5186 5187 // No need to store the CPU yet. There aren't any CPU-specific 5188 // macros to define. 5189 return CPUKnown; 5190 } 5191 }; 5192 5193 } // end anonymous namespace. 5194 5195 namespace { 5196 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5197 public: 5198 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5199 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5200 SizeType = UnsignedInt; 5201 PtrDiffType = SignedInt; 5202 } 5203 }; 5204 } // end anonymous namespace. 5205 5206 namespace { 5207 class SystemZTargetInfo : public TargetInfo { 5208 static const char *const GCCRegNames[]; 5209 5210 public: 5211 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5212 TLSSupported = true; 5213 IntWidth = IntAlign = 32; 5214 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5215 PointerWidth = PointerAlign = 64; 5216 LongDoubleWidth = 128; 5217 LongDoubleAlign = 64; 5218 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5219 MinGlobalAlign = 16; 5220 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5221 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5222 } 5223 void getTargetDefines(const LangOptions &Opts, 5224 MacroBuilder &Builder) const override { 5225 Builder.defineMacro("__s390__"); 5226 Builder.defineMacro("__s390x__"); 5227 Builder.defineMacro("__zarch__"); 5228 Builder.defineMacro("__LONG_DOUBLE_128__"); 5229 } 5230 void getTargetBuiltins(const Builtin::Info *&Records, 5231 unsigned &NumRecords) const override { 5232 // FIXME: Implement. 5233 Records = nullptr; 5234 NumRecords = 0; 5235 } 5236 5237 void getGCCRegNames(const char *const *&Names, 5238 unsigned &NumNames) const override; 5239 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5240 unsigned &NumAliases) const override { 5241 // No aliases. 5242 Aliases = nullptr; 5243 NumAliases = 0; 5244 } 5245 bool validateAsmConstraint(const char *&Name, 5246 TargetInfo::ConstraintInfo &info) const override; 5247 const char *getClobbers() const override { 5248 // FIXME: Is this really right? 5249 return ""; 5250 } 5251 BuiltinVaListKind getBuiltinVaListKind() const override { 5252 return TargetInfo::SystemZBuiltinVaList; 5253 } 5254 bool setCPU(const std::string &Name) override { 5255 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5256 .Case("z10", true) 5257 .Case("z196", true) 5258 .Case("zEC12", true) 5259 .Default(false); 5260 5261 // No need to store the CPU yet. There aren't any CPU-specific 5262 // macros to define. 5263 return CPUKnown; 5264 } 5265 }; 5266 5267 const char *const SystemZTargetInfo::GCCRegNames[] = { 5268 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5269 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5270 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5271 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5272 }; 5273 5274 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5275 unsigned &NumNames) const { 5276 Names = GCCRegNames; 5277 NumNames = llvm::array_lengthof(GCCRegNames); 5278 } 5279 5280 bool SystemZTargetInfo:: 5281 validateAsmConstraint(const char *&Name, 5282 TargetInfo::ConstraintInfo &Info) const { 5283 switch (*Name) { 5284 default: 5285 return false; 5286 5287 case 'a': // Address register 5288 case 'd': // Data register (equivalent to 'r') 5289 case 'f': // Floating-point register 5290 Info.setAllowsRegister(); 5291 return true; 5292 5293 case 'I': // Unsigned 8-bit constant 5294 case 'J': // Unsigned 12-bit constant 5295 case 'K': // Signed 16-bit constant 5296 case 'L': // Signed 20-bit displacement (on all targets we support) 5297 case 'M': // 0x7fffffff 5298 return true; 5299 5300 case 'Q': // Memory with base and unsigned 12-bit displacement 5301 case 'R': // Likewise, plus an index 5302 case 'S': // Memory with base and signed 20-bit displacement 5303 case 'T': // Likewise, plus an index 5304 Info.setAllowsMemory(); 5305 return true; 5306 } 5307 } 5308 } 5309 5310 namespace { 5311 class MSP430TargetInfo : public TargetInfo { 5312 static const char * const GCCRegNames[]; 5313 public: 5314 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5315 BigEndian = false; 5316 TLSSupported = false; 5317 IntWidth = 16; IntAlign = 16; 5318 LongWidth = 32; LongLongWidth = 64; 5319 LongAlign = LongLongAlign = 16; 5320 PointerWidth = 16; PointerAlign = 16; 5321 SuitableAlign = 16; 5322 SizeType = UnsignedInt; 5323 IntMaxType = SignedLongLong; 5324 IntPtrType = SignedInt; 5325 PtrDiffType = SignedInt; 5326 SigAtomicType = SignedLong; 5327 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5328 } 5329 void getTargetDefines(const LangOptions &Opts, 5330 MacroBuilder &Builder) const override { 5331 Builder.defineMacro("MSP430"); 5332 Builder.defineMacro("__MSP430__"); 5333 // FIXME: defines for different 'flavours' of MCU 5334 } 5335 void getTargetBuiltins(const Builtin::Info *&Records, 5336 unsigned &NumRecords) const override { 5337 // FIXME: Implement. 5338 Records = nullptr; 5339 NumRecords = 0; 5340 } 5341 bool hasFeature(StringRef Feature) const override { 5342 return Feature == "msp430"; 5343 } 5344 void getGCCRegNames(const char * const *&Names, 5345 unsigned &NumNames) const override; 5346 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5347 unsigned &NumAliases) const override { 5348 // No aliases. 5349 Aliases = nullptr; 5350 NumAliases = 0; 5351 } 5352 bool validateAsmConstraint(const char *&Name, 5353 TargetInfo::ConstraintInfo &info) const override { 5354 // No target constraints for now. 5355 return false; 5356 } 5357 const char *getClobbers() const override { 5358 // FIXME: Is this really right? 5359 return ""; 5360 } 5361 BuiltinVaListKind getBuiltinVaListKind() const override { 5362 // FIXME: implement 5363 return TargetInfo::CharPtrBuiltinVaList; 5364 } 5365 }; 5366 5367 const char * const MSP430TargetInfo::GCCRegNames[] = { 5368 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5369 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5370 }; 5371 5372 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5373 unsigned &NumNames) const { 5374 Names = GCCRegNames; 5375 NumNames = llvm::array_lengthof(GCCRegNames); 5376 } 5377 } 5378 5379 namespace { 5380 5381 // LLVM and Clang cannot be used directly to output native binaries for 5382 // target, but is used to compile C code to llvm bitcode with correct 5383 // type and alignment information. 5384 // 5385 // TCE uses the llvm bitcode as input and uses it for generating customized 5386 // target processor and program binary. TCE co-design environment is 5387 // publicly available in http://tce.cs.tut.fi 5388 5389 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5390 3, // opencl_global 5391 4, // opencl_local 5392 5, // opencl_constant 5393 0, // cuda_device 5394 0, // cuda_constant 5395 0 // cuda_shared 5396 }; 5397 5398 class TCETargetInfo : public TargetInfo{ 5399 public: 5400 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5401 TLSSupported = false; 5402 IntWidth = 32; 5403 LongWidth = LongLongWidth = 32; 5404 PointerWidth = 32; 5405 IntAlign = 32; 5406 LongAlign = LongLongAlign = 32; 5407 PointerAlign = 32; 5408 SuitableAlign = 32; 5409 SizeType = UnsignedInt; 5410 IntMaxType = SignedLong; 5411 IntPtrType = SignedInt; 5412 PtrDiffType = SignedInt; 5413 FloatWidth = 32; 5414 FloatAlign = 32; 5415 DoubleWidth = 32; 5416 DoubleAlign = 32; 5417 LongDoubleWidth = 32; 5418 LongDoubleAlign = 32; 5419 FloatFormat = &llvm::APFloat::IEEEsingle; 5420 DoubleFormat = &llvm::APFloat::IEEEsingle; 5421 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5422 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5423 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5424 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5425 UseAddrSpaceMapMangling = true; 5426 } 5427 5428 void getTargetDefines(const LangOptions &Opts, 5429 MacroBuilder &Builder) const override { 5430 DefineStd(Builder, "tce", Opts); 5431 Builder.defineMacro("__TCE__"); 5432 Builder.defineMacro("__TCE_V1__"); 5433 } 5434 bool hasFeature(StringRef Feature) const override { 5435 return Feature == "tce"; 5436 } 5437 5438 void getTargetBuiltins(const Builtin::Info *&Records, 5439 unsigned &NumRecords) const override {} 5440 const char *getClobbers() const override { 5441 return ""; 5442 } 5443 BuiltinVaListKind getBuiltinVaListKind() const override { 5444 return TargetInfo::VoidPtrBuiltinVaList; 5445 } 5446 void getGCCRegNames(const char * const *&Names, 5447 unsigned &NumNames) const override {} 5448 bool validateAsmConstraint(const char *&Name, 5449 TargetInfo::ConstraintInfo &info) const override{ 5450 return true; 5451 } 5452 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5453 unsigned &NumAliases) const override {} 5454 }; 5455 } 5456 5457 namespace { 5458 class MipsTargetInfoBase : public TargetInfo { 5459 virtual void setDescriptionString() = 0; 5460 5461 static const Builtin::Info BuiltinInfo[]; 5462 std::string CPU; 5463 bool IsMips16; 5464 bool IsMicromips; 5465 bool IsNan2008; 5466 bool IsSingleFloat; 5467 enum MipsFloatABI { 5468 HardFloat, SoftFloat 5469 } FloatABI; 5470 enum DspRevEnum { 5471 NoDSP, DSP1, DSP2 5472 } DspRev; 5473 bool HasMSA; 5474 5475 protected: 5476 bool HasFP64; 5477 std::string ABI; 5478 5479 public: 5480 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5481 const std::string &CPUStr) 5482 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5483 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5484 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5485 5486 bool isNaN2008Default() const { 5487 return CPU == "mips32r6" || CPU == "mips64r6"; 5488 } 5489 5490 bool isFP64Default() const { 5491 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5492 } 5493 5494 StringRef getABI() const override { return ABI; } 5495 bool setCPU(const std::string &Name) override { 5496 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5497 getTriple().getArch() == llvm::Triple::mipsel; 5498 CPU = Name; 5499 return llvm::StringSwitch<bool>(Name) 5500 .Case("mips1", IsMips32) 5501 .Case("mips2", IsMips32) 5502 .Case("mips3", true) 5503 .Case("mips4", true) 5504 .Case("mips5", true) 5505 .Case("mips32", IsMips32) 5506 .Case("mips32r2", IsMips32) 5507 .Case("mips32r6", IsMips32) 5508 .Case("mips64", true) 5509 .Case("mips64r2", true) 5510 .Case("mips64r6", true) 5511 .Case("octeon", true) 5512 .Default(false); 5513 } 5514 const std::string& getCPU() const { return CPU; } 5515 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5516 // The backend enables certain ABI's by default according to the 5517 // architecture. 5518 // Disable both possible defaults so that we don't end up with multiple 5519 // ABI's selected and trigger an assertion. 5520 Features["o32"] = false; 5521 Features["n64"] = false; 5522 5523 Features[ABI] = true; 5524 if (CPU == "octeon") 5525 Features["mips64r2"] = Features["cnmips"] = true; 5526 else 5527 Features[CPU] = true; 5528 } 5529 5530 void getTargetDefines(const LangOptions &Opts, 5531 MacroBuilder &Builder) const override { 5532 Builder.defineMacro("__mips__"); 5533 Builder.defineMacro("_mips"); 5534 if (Opts.GNUMode) 5535 Builder.defineMacro("mips"); 5536 5537 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5538 5539 switch (FloatABI) { 5540 case HardFloat: 5541 Builder.defineMacro("__mips_hard_float", Twine(1)); 5542 break; 5543 case SoftFloat: 5544 Builder.defineMacro("__mips_soft_float", Twine(1)); 5545 break; 5546 } 5547 5548 if (IsSingleFloat) 5549 Builder.defineMacro("__mips_single_float", Twine(1)); 5550 5551 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5552 Builder.defineMacro("_MIPS_FPSET", 5553 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5554 5555 if (IsMips16) 5556 Builder.defineMacro("__mips16", Twine(1)); 5557 5558 if (IsMicromips) 5559 Builder.defineMacro("__mips_micromips", Twine(1)); 5560 5561 if (IsNan2008) 5562 Builder.defineMacro("__mips_nan2008", Twine(1)); 5563 5564 switch (DspRev) { 5565 default: 5566 break; 5567 case DSP1: 5568 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5569 Builder.defineMacro("__mips_dsp", Twine(1)); 5570 break; 5571 case DSP2: 5572 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5573 Builder.defineMacro("__mips_dspr2", Twine(1)); 5574 Builder.defineMacro("__mips_dsp", Twine(1)); 5575 break; 5576 } 5577 5578 if (HasMSA) 5579 Builder.defineMacro("__mips_msa", Twine(1)); 5580 5581 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5582 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5583 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5584 5585 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5586 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5587 } 5588 5589 void getTargetBuiltins(const Builtin::Info *&Records, 5590 unsigned &NumRecords) const override { 5591 Records = BuiltinInfo; 5592 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5593 } 5594 bool hasFeature(StringRef Feature) const override { 5595 return llvm::StringSwitch<bool>(Feature) 5596 .Case("mips", true) 5597 .Case("fp64", HasFP64) 5598 .Default(false); 5599 } 5600 BuiltinVaListKind getBuiltinVaListKind() const override { 5601 return TargetInfo::VoidPtrBuiltinVaList; 5602 } 5603 void getGCCRegNames(const char * const *&Names, 5604 unsigned &NumNames) const override { 5605 static const char *const GCCRegNames[] = { 5606 // CPU register names 5607 // Must match second column of GCCRegAliases 5608 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5609 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5610 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5611 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5612 // Floating point register names 5613 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5614 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5615 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5616 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5617 // Hi/lo and condition register names 5618 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5619 "$fcc5","$fcc6","$fcc7", 5620 // MSA register names 5621 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5622 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5623 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5624 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5625 // MSA control register names 5626 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5627 "$msarequest", "$msamap", "$msaunmap" 5628 }; 5629 Names = GCCRegNames; 5630 NumNames = llvm::array_lengthof(GCCRegNames); 5631 } 5632 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5633 unsigned &NumAliases) const override = 0; 5634 bool validateAsmConstraint(const char *&Name, 5635 TargetInfo::ConstraintInfo &Info) const override { 5636 switch (*Name) { 5637 default: 5638 return false; 5639 5640 case 'r': // CPU registers. 5641 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5642 case 'y': // Equivalent to "r", backward compatibility only. 5643 case 'f': // floating-point registers. 5644 case 'c': // $25 for indirect jumps 5645 case 'l': // lo register 5646 case 'x': // hilo register pair 5647 Info.setAllowsRegister(); 5648 return true; 5649 case 'R': // An address that can be used in a non-macro load or store 5650 Info.setAllowsMemory(); 5651 return true; 5652 } 5653 } 5654 5655 const char *getClobbers() const override { 5656 // FIXME: Implement! 5657 return ""; 5658 } 5659 5660 bool handleTargetFeatures(std::vector<std::string> &Features, 5661 DiagnosticsEngine &Diags) override { 5662 IsMips16 = false; 5663 IsMicromips = false; 5664 IsNan2008 = isNaN2008Default(); 5665 IsSingleFloat = false; 5666 FloatABI = HardFloat; 5667 DspRev = NoDSP; 5668 HasFP64 = isFP64Default(); 5669 5670 for (std::vector<std::string>::iterator it = Features.begin(), 5671 ie = Features.end(); it != ie; ++it) { 5672 if (*it == "+single-float") 5673 IsSingleFloat = true; 5674 else if (*it == "+soft-float") 5675 FloatABI = SoftFloat; 5676 else if (*it == "+mips16") 5677 IsMips16 = true; 5678 else if (*it == "+micromips") 5679 IsMicromips = true; 5680 else if (*it == "+dsp") 5681 DspRev = std::max(DspRev, DSP1); 5682 else if (*it == "+dspr2") 5683 DspRev = std::max(DspRev, DSP2); 5684 else if (*it == "+msa") 5685 HasMSA = true; 5686 else if (*it == "+fp64") 5687 HasFP64 = true; 5688 else if (*it == "-fp64") 5689 HasFP64 = false; 5690 else if (*it == "+nan2008") 5691 IsNan2008 = true; 5692 else if (*it == "-nan2008") 5693 IsNan2008 = false; 5694 } 5695 5696 // Remove front-end specific options. 5697 std::vector<std::string>::iterator it = 5698 std::find(Features.begin(), Features.end(), "+soft-float"); 5699 if (it != Features.end()) 5700 Features.erase(it); 5701 5702 setDescriptionString(); 5703 5704 return true; 5705 } 5706 5707 int getEHDataRegisterNumber(unsigned RegNo) const override { 5708 if (RegNo == 0) return 4; 5709 if (RegNo == 1) return 5; 5710 return -1; 5711 } 5712 5713 bool isCLZForZeroUndef() const override { return false; } 5714 }; 5715 5716 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5717 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5718 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5719 ALL_LANGUAGES }, 5720 #include "clang/Basic/BuiltinsMips.def" 5721 }; 5722 5723 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5724 public: 5725 Mips32TargetInfoBase(const llvm::Triple &Triple) 5726 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5727 SizeType = UnsignedInt; 5728 PtrDiffType = SignedInt; 5729 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5730 } 5731 bool setABI(const std::string &Name) override { 5732 if (Name == "o32" || Name == "eabi") { 5733 ABI = Name; 5734 return true; 5735 } 5736 return false; 5737 } 5738 void getTargetDefines(const LangOptions &Opts, 5739 MacroBuilder &Builder) const override { 5740 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5741 5742 Builder.defineMacro("__mips", "32"); 5743 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5744 5745 const std::string& CPUStr = getCPU(); 5746 if (CPUStr == "mips32") 5747 Builder.defineMacro("__mips_isa_rev", "1"); 5748 else if (CPUStr == "mips32r2") 5749 Builder.defineMacro("__mips_isa_rev", "2"); 5750 5751 if (ABI == "o32") { 5752 Builder.defineMacro("__mips_o32"); 5753 Builder.defineMacro("_ABIO32", "1"); 5754 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5755 } 5756 else if (ABI == "eabi") 5757 Builder.defineMacro("__mips_eabi"); 5758 else 5759 llvm_unreachable("Invalid ABI for Mips32."); 5760 } 5761 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5762 unsigned &NumAliases) const override { 5763 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5764 { { "at" }, "$1" }, 5765 { { "v0" }, "$2" }, 5766 { { "v1" }, "$3" }, 5767 { { "a0" }, "$4" }, 5768 { { "a1" }, "$5" }, 5769 { { "a2" }, "$6" }, 5770 { { "a3" }, "$7" }, 5771 { { "t0" }, "$8" }, 5772 { { "t1" }, "$9" }, 5773 { { "t2" }, "$10" }, 5774 { { "t3" }, "$11" }, 5775 { { "t4" }, "$12" }, 5776 { { "t5" }, "$13" }, 5777 { { "t6" }, "$14" }, 5778 { { "t7" }, "$15" }, 5779 { { "s0" }, "$16" }, 5780 { { "s1" }, "$17" }, 5781 { { "s2" }, "$18" }, 5782 { { "s3" }, "$19" }, 5783 { { "s4" }, "$20" }, 5784 { { "s5" }, "$21" }, 5785 { { "s6" }, "$22" }, 5786 { { "s7" }, "$23" }, 5787 { { "t8" }, "$24" }, 5788 { { "t9" }, "$25" }, 5789 { { "k0" }, "$26" }, 5790 { { "k1" }, "$27" }, 5791 { { "gp" }, "$28" }, 5792 { { "sp","$sp" }, "$29" }, 5793 { { "fp","$fp" }, "$30" }, 5794 { { "ra" }, "$31" } 5795 }; 5796 Aliases = GCCRegAliases; 5797 NumAliases = llvm::array_lengthof(GCCRegAliases); 5798 } 5799 }; 5800 5801 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5802 void setDescriptionString() override { 5803 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5804 } 5805 5806 public: 5807 Mips32EBTargetInfo(const llvm::Triple &Triple) 5808 : Mips32TargetInfoBase(Triple) { 5809 } 5810 void getTargetDefines(const LangOptions &Opts, 5811 MacroBuilder &Builder) const override { 5812 DefineStd(Builder, "MIPSEB", Opts); 5813 Builder.defineMacro("_MIPSEB"); 5814 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5815 } 5816 }; 5817 5818 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5819 void setDescriptionString() override { 5820 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5821 } 5822 5823 public: 5824 Mips32ELTargetInfo(const llvm::Triple &Triple) 5825 : Mips32TargetInfoBase(Triple) { 5826 BigEndian = false; 5827 } 5828 void getTargetDefines(const LangOptions &Opts, 5829 MacroBuilder &Builder) const override { 5830 DefineStd(Builder, "MIPSEL", Opts); 5831 Builder.defineMacro("_MIPSEL"); 5832 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5833 } 5834 }; 5835 5836 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5837 public: 5838 Mips64TargetInfoBase(const llvm::Triple &Triple) 5839 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5840 LongDoubleWidth = LongDoubleAlign = 128; 5841 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5842 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5843 LongDoubleWidth = LongDoubleAlign = 64; 5844 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5845 } 5846 setN64ABITypes(); 5847 SuitableAlign = 128; 5848 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5849 } 5850 5851 void setN64ABITypes() { 5852 LongWidth = LongAlign = 64; 5853 PointerWidth = PointerAlign = 64; 5854 SizeType = UnsignedLong; 5855 PtrDiffType = SignedLong; 5856 } 5857 5858 void setN32ABITypes() { 5859 LongWidth = LongAlign = 32; 5860 PointerWidth = PointerAlign = 32; 5861 SizeType = UnsignedInt; 5862 PtrDiffType = SignedInt; 5863 } 5864 5865 bool setABI(const std::string &Name) override { 5866 if (Name == "n32") { 5867 setN32ABITypes(); 5868 ABI = Name; 5869 return true; 5870 } 5871 if (Name == "n64") { 5872 setN64ABITypes(); 5873 ABI = Name; 5874 return true; 5875 } 5876 return false; 5877 } 5878 5879 void getTargetDefines(const LangOptions &Opts, 5880 MacroBuilder &Builder) const override { 5881 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5882 5883 Builder.defineMacro("__mips", "64"); 5884 Builder.defineMacro("__mips64"); 5885 Builder.defineMacro("__mips64__"); 5886 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 5887 5888 const std::string& CPUStr = getCPU(); 5889 if (CPUStr == "mips64") 5890 Builder.defineMacro("__mips_isa_rev", "1"); 5891 else if (CPUStr == "mips64r2") 5892 Builder.defineMacro("__mips_isa_rev", "2"); 5893 5894 if (ABI == "n32") { 5895 Builder.defineMacro("__mips_n32"); 5896 Builder.defineMacro("_ABIN32", "2"); 5897 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5898 } 5899 else if (ABI == "n64") { 5900 Builder.defineMacro("__mips_n64"); 5901 Builder.defineMacro("_ABI64", "3"); 5902 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5903 } 5904 else 5905 llvm_unreachable("Invalid ABI for Mips64."); 5906 } 5907 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5908 unsigned &NumAliases) const override { 5909 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5910 { { "at" }, "$1" }, 5911 { { "v0" }, "$2" }, 5912 { { "v1" }, "$3" }, 5913 { { "a0" }, "$4" }, 5914 { { "a1" }, "$5" }, 5915 { { "a2" }, "$6" }, 5916 { { "a3" }, "$7" }, 5917 { { "a4" }, "$8" }, 5918 { { "a5" }, "$9" }, 5919 { { "a6" }, "$10" }, 5920 { { "a7" }, "$11" }, 5921 { { "t0" }, "$12" }, 5922 { { "t1" }, "$13" }, 5923 { { "t2" }, "$14" }, 5924 { { "t3" }, "$15" }, 5925 { { "s0" }, "$16" }, 5926 { { "s1" }, "$17" }, 5927 { { "s2" }, "$18" }, 5928 { { "s3" }, "$19" }, 5929 { { "s4" }, "$20" }, 5930 { { "s5" }, "$21" }, 5931 { { "s6" }, "$22" }, 5932 { { "s7" }, "$23" }, 5933 { { "t8" }, "$24" }, 5934 { { "t9" }, "$25" }, 5935 { { "k0" }, "$26" }, 5936 { { "k1" }, "$27" }, 5937 { { "gp" }, "$28" }, 5938 { { "sp","$sp" }, "$29" }, 5939 { { "fp","$fp" }, "$30" }, 5940 { { "ra" }, "$31" } 5941 }; 5942 Aliases = GCCRegAliases; 5943 NumAliases = llvm::array_lengthof(GCCRegAliases); 5944 } 5945 5946 bool hasInt128Type() const override { return true; } 5947 }; 5948 5949 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5950 void setDescriptionString() override { 5951 if (ABI == "n32") 5952 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5953 else 5954 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5955 5956 } 5957 5958 public: 5959 Mips64EBTargetInfo(const llvm::Triple &Triple) 5960 : Mips64TargetInfoBase(Triple) {} 5961 void getTargetDefines(const LangOptions &Opts, 5962 MacroBuilder &Builder) const override { 5963 DefineStd(Builder, "MIPSEB", Opts); 5964 Builder.defineMacro("_MIPSEB"); 5965 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5966 } 5967 }; 5968 5969 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5970 void setDescriptionString() override { 5971 if (ABI == "n32") 5972 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5973 else 5974 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5975 } 5976 public: 5977 Mips64ELTargetInfo(const llvm::Triple &Triple) 5978 : Mips64TargetInfoBase(Triple) { 5979 // Default ABI is n64. 5980 BigEndian = false; 5981 } 5982 void getTargetDefines(const LangOptions &Opts, 5983 MacroBuilder &Builder) const override { 5984 DefineStd(Builder, "MIPSEL", Opts); 5985 Builder.defineMacro("_MIPSEL"); 5986 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5987 } 5988 }; 5989 } // end anonymous namespace. 5990 5991 namespace { 5992 class PNaClTargetInfo : public TargetInfo { 5993 public: 5994 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5995 BigEndian = false; 5996 this->UserLabelPrefix = ""; 5997 this->LongAlign = 32; 5998 this->LongWidth = 32; 5999 this->PointerAlign = 32; 6000 this->PointerWidth = 32; 6001 this->IntMaxType = TargetInfo::SignedLongLong; 6002 this->Int64Type = TargetInfo::SignedLongLong; 6003 this->DoubleAlign = 64; 6004 this->LongDoubleWidth = 64; 6005 this->LongDoubleAlign = 64; 6006 this->SizeType = TargetInfo::UnsignedInt; 6007 this->PtrDiffType = TargetInfo::SignedInt; 6008 this->IntPtrType = TargetInfo::SignedInt; 6009 this->RegParmMax = 0; // Disallow regparm 6010 } 6011 6012 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6013 } 6014 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6015 Builder.defineMacro("__le32__"); 6016 Builder.defineMacro("__pnacl__"); 6017 } 6018 void getTargetDefines(const LangOptions &Opts, 6019 MacroBuilder &Builder) const override { 6020 getArchDefines(Opts, Builder); 6021 } 6022 bool hasFeature(StringRef Feature) const override { 6023 return Feature == "pnacl"; 6024 } 6025 void getTargetBuiltins(const Builtin::Info *&Records, 6026 unsigned &NumRecords) const override { 6027 } 6028 BuiltinVaListKind getBuiltinVaListKind() const override { 6029 return TargetInfo::PNaClABIBuiltinVaList; 6030 } 6031 void getGCCRegNames(const char * const *&Names, 6032 unsigned &NumNames) const override; 6033 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6034 unsigned &NumAliases) const override; 6035 bool validateAsmConstraint(const char *&Name, 6036 TargetInfo::ConstraintInfo &Info) const override { 6037 return false; 6038 } 6039 6040 const char *getClobbers() const override { 6041 return ""; 6042 } 6043 }; 6044 6045 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6046 unsigned &NumNames) const { 6047 Names = nullptr; 6048 NumNames = 0; 6049 } 6050 6051 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6052 unsigned &NumAliases) const { 6053 Aliases = nullptr; 6054 NumAliases = 0; 6055 } 6056 } // end anonymous namespace. 6057 6058 namespace { 6059 class Le64TargetInfo : public TargetInfo { 6060 static const Builtin::Info BuiltinInfo[]; 6061 6062 public: 6063 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6064 BigEndian = false; 6065 NoAsmVariants = true; 6066 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6067 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6068 DescriptionString = 6069 "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64"; 6070 } 6071 6072 void getTargetDefines(const LangOptions &Opts, 6073 MacroBuilder &Builder) const override { 6074 DefineStd(Builder, "unix", Opts); 6075 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6076 Builder.defineMacro("__ELF__"); 6077 } 6078 void getTargetBuiltins(const Builtin::Info *&Records, 6079 unsigned &NumRecords) const override { 6080 Records = BuiltinInfo; 6081 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6082 } 6083 BuiltinVaListKind getBuiltinVaListKind() const override { 6084 return TargetInfo::PNaClABIBuiltinVaList; 6085 } 6086 const char *getClobbers() const override { return ""; } 6087 void getGCCRegNames(const char *const *&Names, 6088 unsigned &NumNames) const override { 6089 Names = nullptr; 6090 NumNames = 0; 6091 } 6092 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6093 unsigned &NumAliases) const override { 6094 Aliases = nullptr; 6095 NumAliases = 0; 6096 } 6097 bool validateAsmConstraint(const char *&Name, 6098 TargetInfo::ConstraintInfo &Info) const override { 6099 return false; 6100 } 6101 6102 bool hasProtectedVisibility() const override { return false; } 6103 }; 6104 } // end anonymous namespace. 6105 6106 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6107 #define BUILTIN(ID, TYPE, ATTRS) \ 6108 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6109 #include "clang/Basic/BuiltinsLe64.def" 6110 }; 6111 6112 namespace { 6113 static const unsigned SPIRAddrSpaceMap[] = { 6114 1, // opencl_global 6115 3, // opencl_local 6116 2, // opencl_constant 6117 0, // cuda_device 6118 0, // cuda_constant 6119 0 // cuda_shared 6120 }; 6121 class SPIRTargetInfo : public TargetInfo { 6122 public: 6123 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6124 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6125 "SPIR target must use unknown OS"); 6126 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6127 "SPIR target must use unknown environment type"); 6128 BigEndian = false; 6129 TLSSupported = false; 6130 LongWidth = LongAlign = 64; 6131 AddrSpaceMap = &SPIRAddrSpaceMap; 6132 UseAddrSpaceMapMangling = true; 6133 // Define available target features 6134 // These must be defined in sorted order! 6135 NoAsmVariants = true; 6136 } 6137 void getTargetDefines(const LangOptions &Opts, 6138 MacroBuilder &Builder) const override { 6139 DefineStd(Builder, "SPIR", Opts); 6140 } 6141 bool hasFeature(StringRef Feature) const override { 6142 return Feature == "spir"; 6143 } 6144 6145 void getTargetBuiltins(const Builtin::Info *&Records, 6146 unsigned &NumRecords) const override {} 6147 const char *getClobbers() const override { 6148 return ""; 6149 } 6150 void getGCCRegNames(const char * const *&Names, 6151 unsigned &NumNames) const override {} 6152 bool validateAsmConstraint(const char *&Name, 6153 TargetInfo::ConstraintInfo &info) const override { 6154 return true; 6155 } 6156 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6157 unsigned &NumAliases) const override {} 6158 BuiltinVaListKind getBuiltinVaListKind() const override { 6159 return TargetInfo::VoidPtrBuiltinVaList; 6160 } 6161 }; 6162 6163 6164 class SPIR32TargetInfo : public SPIRTargetInfo { 6165 public: 6166 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6167 PointerWidth = PointerAlign = 32; 6168 SizeType = TargetInfo::UnsignedInt; 6169 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6170 DescriptionString 6171 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6172 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6173 } 6174 void getTargetDefines(const LangOptions &Opts, 6175 MacroBuilder &Builder) const override { 6176 DefineStd(Builder, "SPIR32", Opts); 6177 } 6178 }; 6179 6180 class SPIR64TargetInfo : public SPIRTargetInfo { 6181 public: 6182 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6183 PointerWidth = PointerAlign = 64; 6184 SizeType = TargetInfo::UnsignedLong; 6185 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6186 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6187 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6188 } 6189 void getTargetDefines(const LangOptions &Opts, 6190 MacroBuilder &Builder) const override { 6191 DefineStd(Builder, "SPIR64", Opts); 6192 } 6193 }; 6194 } 6195 6196 namespace { 6197 class XCoreTargetInfo : public TargetInfo { 6198 static const Builtin::Info BuiltinInfo[]; 6199 public: 6200 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6201 BigEndian = false; 6202 NoAsmVariants = true; 6203 LongLongAlign = 32; 6204 SuitableAlign = 32; 6205 DoubleAlign = LongDoubleAlign = 32; 6206 SizeType = UnsignedInt; 6207 PtrDiffType = SignedInt; 6208 IntPtrType = SignedInt; 6209 WCharType = UnsignedChar; 6210 WIntType = UnsignedInt; 6211 UseZeroLengthBitfieldAlignment = true; 6212 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6213 "-f64:32-a:0:32-n32"; 6214 } 6215 void getTargetDefines(const LangOptions &Opts, 6216 MacroBuilder &Builder) const override { 6217 Builder.defineMacro("__XS1B__"); 6218 } 6219 void getTargetBuiltins(const Builtin::Info *&Records, 6220 unsigned &NumRecords) const override { 6221 Records = BuiltinInfo; 6222 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6223 } 6224 BuiltinVaListKind getBuiltinVaListKind() const override { 6225 return TargetInfo::VoidPtrBuiltinVaList; 6226 } 6227 const char *getClobbers() const override { 6228 return ""; 6229 } 6230 void getGCCRegNames(const char * const *&Names, 6231 unsigned &NumNames) const override { 6232 static const char * const GCCRegNames[] = { 6233 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6234 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6235 }; 6236 Names = GCCRegNames; 6237 NumNames = llvm::array_lengthof(GCCRegNames); 6238 } 6239 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6240 unsigned &NumAliases) const override { 6241 Aliases = nullptr; 6242 NumAliases = 0; 6243 } 6244 bool validateAsmConstraint(const char *&Name, 6245 TargetInfo::ConstraintInfo &Info) const override { 6246 return false; 6247 } 6248 int getEHDataRegisterNumber(unsigned RegNo) const override { 6249 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6250 return (RegNo < 2)? RegNo : -1; 6251 } 6252 }; 6253 6254 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6255 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6256 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6257 ALL_LANGUAGES }, 6258 #include "clang/Basic/BuiltinsXCore.def" 6259 }; 6260 } // end anonymous namespace. 6261 6262 6263 //===----------------------------------------------------------------------===// 6264 // Driver code 6265 //===----------------------------------------------------------------------===// 6266 6267 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6268 llvm::Triple::OSType os = Triple.getOS(); 6269 6270 switch (Triple.getArch()) { 6271 default: 6272 return nullptr; 6273 6274 case llvm::Triple::xcore: 6275 return new XCoreTargetInfo(Triple); 6276 6277 case llvm::Triple::hexagon: 6278 return new HexagonTargetInfo(Triple); 6279 6280 case llvm::Triple::aarch64: 6281 if (Triple.isOSDarwin()) 6282 return new DarwinAArch64TargetInfo(Triple); 6283 6284 switch (os) { 6285 case llvm::Triple::Linux: 6286 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6287 case llvm::Triple::NetBSD: 6288 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6289 default: 6290 return new AArch64leTargetInfo(Triple); 6291 } 6292 6293 case llvm::Triple::aarch64_be: 6294 switch (os) { 6295 case llvm::Triple::Linux: 6296 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6297 case llvm::Triple::NetBSD: 6298 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6299 default: 6300 return new AArch64beTargetInfo(Triple); 6301 } 6302 6303 case llvm::Triple::arm: 6304 case llvm::Triple::thumb: 6305 if (Triple.isOSBinFormatMachO()) 6306 return new DarwinARMTargetInfo(Triple); 6307 6308 switch (os) { 6309 case llvm::Triple::Linux: 6310 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6311 case llvm::Triple::FreeBSD: 6312 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6313 case llvm::Triple::NetBSD: 6314 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6315 case llvm::Triple::OpenBSD: 6316 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6317 case llvm::Triple::Bitrig: 6318 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6319 case llvm::Triple::RTEMS: 6320 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6321 case llvm::Triple::NaCl: 6322 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6323 case llvm::Triple::Win32: 6324 switch (Triple.getEnvironment()) { 6325 default: 6326 return new ARMleTargetInfo(Triple); 6327 case llvm::Triple::Itanium: 6328 return new ItaniumWindowsARMleTargetInfo(Triple); 6329 case llvm::Triple::MSVC: 6330 return new MicrosoftARMleTargetInfo(Triple); 6331 } 6332 default: 6333 return new ARMleTargetInfo(Triple); 6334 } 6335 6336 case llvm::Triple::armeb: 6337 case llvm::Triple::thumbeb: 6338 if (Triple.isOSDarwin()) 6339 return new DarwinARMTargetInfo(Triple); 6340 6341 switch (os) { 6342 case llvm::Triple::Linux: 6343 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6344 case llvm::Triple::FreeBSD: 6345 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6346 case llvm::Triple::NetBSD: 6347 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6348 case llvm::Triple::OpenBSD: 6349 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6350 case llvm::Triple::Bitrig: 6351 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6352 case llvm::Triple::RTEMS: 6353 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6354 case llvm::Triple::NaCl: 6355 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6356 default: 6357 return new ARMbeTargetInfo(Triple); 6358 } 6359 6360 case llvm::Triple::msp430: 6361 return new MSP430TargetInfo(Triple); 6362 6363 case llvm::Triple::mips: 6364 switch (os) { 6365 case llvm::Triple::Linux: 6366 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6367 case llvm::Triple::RTEMS: 6368 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6369 case llvm::Triple::FreeBSD: 6370 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6371 case llvm::Triple::NetBSD: 6372 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6373 default: 6374 return new Mips32EBTargetInfo(Triple); 6375 } 6376 6377 case llvm::Triple::mipsel: 6378 switch (os) { 6379 case llvm::Triple::Linux: 6380 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6381 case llvm::Triple::RTEMS: 6382 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6383 case llvm::Triple::FreeBSD: 6384 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6385 case llvm::Triple::NetBSD: 6386 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6387 case llvm::Triple::NaCl: 6388 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6389 default: 6390 return new Mips32ELTargetInfo(Triple); 6391 } 6392 6393 case llvm::Triple::mips64: 6394 switch (os) { 6395 case llvm::Triple::Linux: 6396 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6397 case llvm::Triple::RTEMS: 6398 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6399 case llvm::Triple::FreeBSD: 6400 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6401 case llvm::Triple::NetBSD: 6402 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6403 case llvm::Triple::OpenBSD: 6404 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6405 default: 6406 return new Mips64EBTargetInfo(Triple); 6407 } 6408 6409 case llvm::Triple::mips64el: 6410 switch (os) { 6411 case llvm::Triple::Linux: 6412 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6413 case llvm::Triple::RTEMS: 6414 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6415 case llvm::Triple::FreeBSD: 6416 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6417 case llvm::Triple::NetBSD: 6418 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6419 case llvm::Triple::OpenBSD: 6420 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6421 default: 6422 return new Mips64ELTargetInfo(Triple); 6423 } 6424 6425 case llvm::Triple::le32: 6426 switch (os) { 6427 case llvm::Triple::NaCl: 6428 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6429 default: 6430 return nullptr; 6431 } 6432 6433 case llvm::Triple::le64: 6434 return new Le64TargetInfo(Triple); 6435 6436 case llvm::Triple::ppc: 6437 if (Triple.isOSDarwin()) 6438 return new DarwinPPC32TargetInfo(Triple); 6439 switch (os) { 6440 case llvm::Triple::Linux: 6441 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6442 case llvm::Triple::FreeBSD: 6443 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6444 case llvm::Triple::NetBSD: 6445 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6446 case llvm::Triple::OpenBSD: 6447 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6448 case llvm::Triple::RTEMS: 6449 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6450 default: 6451 return new PPC32TargetInfo(Triple); 6452 } 6453 6454 case llvm::Triple::ppc64: 6455 if (Triple.isOSDarwin()) 6456 return new DarwinPPC64TargetInfo(Triple); 6457 switch (os) { 6458 case llvm::Triple::Linux: 6459 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6460 case llvm::Triple::Lv2: 6461 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6462 case llvm::Triple::FreeBSD: 6463 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6464 case llvm::Triple::NetBSD: 6465 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6466 default: 6467 return new PPC64TargetInfo(Triple); 6468 } 6469 6470 case llvm::Triple::ppc64le: 6471 switch (os) { 6472 case llvm::Triple::Linux: 6473 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6474 default: 6475 return new PPC64TargetInfo(Triple); 6476 } 6477 6478 case llvm::Triple::nvptx: 6479 return new NVPTX32TargetInfo(Triple); 6480 case llvm::Triple::nvptx64: 6481 return new NVPTX64TargetInfo(Triple); 6482 6483 case llvm::Triple::r600: 6484 return new R600TargetInfo(Triple); 6485 6486 case llvm::Triple::sparc: 6487 switch (os) { 6488 case llvm::Triple::Linux: 6489 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6490 case llvm::Triple::Solaris: 6491 return new SolarisSparcV8TargetInfo(Triple); 6492 case llvm::Triple::NetBSD: 6493 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6494 case llvm::Triple::OpenBSD: 6495 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6496 case llvm::Triple::RTEMS: 6497 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6498 default: 6499 return new SparcV8TargetInfo(Triple); 6500 } 6501 6502 case llvm::Triple::sparcv9: 6503 switch (os) { 6504 case llvm::Triple::Linux: 6505 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6506 case llvm::Triple::Solaris: 6507 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6508 case llvm::Triple::NetBSD: 6509 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6510 case llvm::Triple::OpenBSD: 6511 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6512 case llvm::Triple::FreeBSD: 6513 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6514 default: 6515 return new SparcV9TargetInfo(Triple); 6516 } 6517 6518 case llvm::Triple::systemz: 6519 switch (os) { 6520 case llvm::Triple::Linux: 6521 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6522 default: 6523 return new SystemZTargetInfo(Triple); 6524 } 6525 6526 case llvm::Triple::tce: 6527 return new TCETargetInfo(Triple); 6528 6529 case llvm::Triple::x86: 6530 if (Triple.isOSDarwin()) 6531 return new DarwinI386TargetInfo(Triple); 6532 6533 switch (os) { 6534 case llvm::Triple::Linux: 6535 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6536 case llvm::Triple::DragonFly: 6537 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6538 case llvm::Triple::NetBSD: 6539 return new NetBSDI386TargetInfo(Triple); 6540 case llvm::Triple::OpenBSD: 6541 return new OpenBSDI386TargetInfo(Triple); 6542 case llvm::Triple::Bitrig: 6543 return new BitrigI386TargetInfo(Triple); 6544 case llvm::Triple::FreeBSD: 6545 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6546 case llvm::Triple::KFreeBSD: 6547 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6548 case llvm::Triple::Minix: 6549 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6550 case llvm::Triple::Solaris: 6551 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6552 case llvm::Triple::Win32: { 6553 switch (Triple.getEnvironment()) { 6554 default: 6555 return new X86_32TargetInfo(Triple); 6556 case llvm::Triple::Cygnus: 6557 return new CygwinX86_32TargetInfo(Triple); 6558 case llvm::Triple::GNU: 6559 return new MinGWX86_32TargetInfo(Triple); 6560 case llvm::Triple::Itanium: 6561 case llvm::Triple::MSVC: 6562 return new MicrosoftX86_32TargetInfo(Triple); 6563 } 6564 } 6565 case llvm::Triple::Haiku: 6566 return new HaikuX86_32TargetInfo(Triple); 6567 case llvm::Triple::RTEMS: 6568 return new RTEMSX86_32TargetInfo(Triple); 6569 case llvm::Triple::NaCl: 6570 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6571 default: 6572 return new X86_32TargetInfo(Triple); 6573 } 6574 6575 case llvm::Triple::x86_64: 6576 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6577 return new DarwinX86_64TargetInfo(Triple); 6578 6579 switch (os) { 6580 case llvm::Triple::Linux: 6581 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6582 case llvm::Triple::DragonFly: 6583 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6584 case llvm::Triple::NetBSD: 6585 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6586 case llvm::Triple::OpenBSD: 6587 return new OpenBSDX86_64TargetInfo(Triple); 6588 case llvm::Triple::Bitrig: 6589 return new BitrigX86_64TargetInfo(Triple); 6590 case llvm::Triple::FreeBSD: 6591 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6592 case llvm::Triple::KFreeBSD: 6593 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6594 case llvm::Triple::Solaris: 6595 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6596 case llvm::Triple::Win32: { 6597 switch (Triple.getEnvironment()) { 6598 default: 6599 return new X86_64TargetInfo(Triple); 6600 case llvm::Triple::GNU: 6601 return new MinGWX86_64TargetInfo(Triple); 6602 case llvm::Triple::MSVC: 6603 return new MicrosoftX86_64TargetInfo(Triple); 6604 } 6605 } 6606 case llvm::Triple::NaCl: 6607 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6608 default: 6609 return new X86_64TargetInfo(Triple); 6610 } 6611 6612 case llvm::Triple::spir: { 6613 if (Triple.getOS() != llvm::Triple::UnknownOS || 6614 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6615 return nullptr; 6616 return new SPIR32TargetInfo(Triple); 6617 } 6618 case llvm::Triple::spir64: { 6619 if (Triple.getOS() != llvm::Triple::UnknownOS || 6620 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6621 return nullptr; 6622 return new SPIR64TargetInfo(Triple); 6623 } 6624 } 6625 } 6626 6627 /// CreateTargetInfo - Return the target info object for the specified target 6628 /// triple. 6629 TargetInfo * 6630 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6631 const std::shared_ptr<TargetOptions> &Opts) { 6632 llvm::Triple Triple(Opts->Triple); 6633 6634 // Construct the target 6635 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6636 if (!Target) { 6637 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6638 return nullptr; 6639 } 6640 Target->TargetOpts = Opts; 6641 6642 // Set the target CPU if specified. 6643 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6644 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6645 return nullptr; 6646 } 6647 6648 // Set the target ABI if specified. 6649 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6650 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6651 return nullptr; 6652 } 6653 6654 // Set the fp math unit. 6655 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6656 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6657 return nullptr; 6658 } 6659 6660 // Compute the default target features, we need the target to handle this 6661 // because features may have dependencies on one another. 6662 llvm::StringMap<bool> Features; 6663 Target->getDefaultFeatures(Features); 6664 6665 // Apply the user specified deltas. 6666 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6667 I < N; ++I) { 6668 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6669 // Apply the feature via the target. 6670 bool Enabled = Name[0] == '+'; 6671 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6672 } 6673 6674 // Add the features to the compile options. 6675 // 6676 // FIXME: If we are completely confident that we have the right set, we only 6677 // need to pass the minuses. 6678 Opts->Features.clear(); 6679 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6680 ie = Features.end(); it != ie; ++it) 6681 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6682 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6683 return nullptr; 6684 6685 return Target.release(); 6686 } 6687