1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.has(SanitizerKind::Address))
98     Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 
100   if (!Opts.ObjCAutoRefCount) {
101     // __weak is always defined, for use in blocks and with objc pointers.
102     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 
104     // Darwin defines __strong even in C mode (just to nothing).
105     if (Opts.getGC() != LangOptions::NonGC)
106       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107     else
108       Builder.defineMacro("__strong", "");
109 
110     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111     // allow this in C, since one might have block pointers in structs that
112     // are used in pure C code and in Objective-C ARC.
113     Builder.defineMacro("__unsafe_unretained", "");
114   }
115 
116   if (Opts.Static)
117     Builder.defineMacro("__STATIC__");
118   else
119     Builder.defineMacro("__DYNAMIC__");
120 
121   if (Opts.POSIXThreads)
122     Builder.defineMacro("_REENTRANT");
123 
124   // Get the platform type and version number from the triple.
125   unsigned Maj, Min, Rev;
126   if (Triple.isMacOSX()) {
127     Triple.getMacOSXVersion(Maj, Min, Rev);
128     PlatformName = "macosx";
129   } else {
130     Triple.getOSVersion(Maj, Min, Rev);
131     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132   }
133 
134   // If -target arch-pc-win32-macho option specified, we're
135   // generating code for Win32 ABI. No need to emit
136   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137   if (PlatformName == "win32") {
138     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139     return;
140   }
141 
142   // Set the appropriate OS version define.
143   if (Triple.isiOS()) {
144     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145     char Str[6];
146     Str[0] = '0' + Maj;
147     Str[1] = '0' + (Min / 10);
148     Str[2] = '0' + (Min % 10);
149     Str[3] = '0' + (Rev / 10);
150     Str[4] = '0' + (Rev % 10);
151     Str[5] = '\0';
152     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153                         Str);
154   } else if (Triple.isMacOSX()) {
155     // Note that the Driver allows versions which aren't representable in the
156     // define (because we only get a single digit for the minor and micro
157     // revision numbers). So, we limit them to the maximum representable
158     // version.
159     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160     char Str[7];
161     if (Maj < 10 || (Maj == 10 && Min < 10)) {
162       Str[0] = '0' + (Maj / 10);
163       Str[1] = '0' + (Maj % 10);
164       Str[2] = '0' + std::min(Min, 9U);
165       Str[3] = '0' + std::min(Rev, 9U);
166       Str[4] = '\0';
167     } else {
168       // Handle versions > 10.9.
169       Str[0] = '0' + (Maj / 10);
170       Str[1] = '0' + (Maj % 10);
171       Str[2] = '0' + (Min / 10);
172       Str[3] = '0' + (Min % 10);
173       Str[4] = '0' + (Rev / 10);
174       Str[5] = '0' + (Rev % 10);
175       Str[6] = '\0';
176     }
177     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178   }
179 
180   // Tell users about the kernel if there is one.
181   if (Triple.isOSDarwin())
182     Builder.defineMacro("__MACH__");
183 
184   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186 
187 namespace {
188 template<typename Target>
189 class DarwinTargetInfo : public OSTargetInfo<Target> {
190 protected:
191   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192                     MacroBuilder &Builder) const override {
193     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194                      this->PlatformMinVersion);
195   }
196 
197 public:
198   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200     this->MCountName = "\01mcount";
201   }
202 
203   std::string isValidSectionSpecifier(StringRef SR) const override {
204     // Let MCSectionMachO validate this.
205     StringRef Segment, Section;
206     unsigned TAA, StubSize;
207     bool HasTAA;
208     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209                                                        TAA, HasTAA, StubSize);
210   }
211 
212   const char *getStaticInitSectionSpecifier() const override {
213     // FIXME: We should return 0 when building kexts.
214     return "__TEXT,__StaticInit,regular,pure_instructions";
215   }
216 
217   /// Darwin does not support protected visibility.  Darwin's "default"
218   /// is very similar to ELF's "protected";  Darwin requires a "weak"
219   /// attribute on declarations that can be dynamically replaced.
220   bool hasProtectedVisibility() const override {
221     return false;
222   }
223 };
224 
225 
226 // DragonFlyBSD Target
227 template<typename Target>
228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229 protected:
230   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231                     MacroBuilder &Builder) const override {
232     // DragonFly defines; list based off of gcc output
233     Builder.defineMacro("__DragonFly__");
234     Builder.defineMacro("__DragonFly_cc_version", "100001");
235     Builder.defineMacro("__ELF__");
236     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237     Builder.defineMacro("__tune_i386__");
238     DefineStd(Builder, "unix", Opts);
239   }
240 public:
241   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242       : OSTargetInfo<Target>(Triple) {
243     this->UserLabelPrefix = "";
244 
245     switch (Triple.getArch()) {
246     default:
247     case llvm::Triple::x86:
248     case llvm::Triple::x86_64:
249       this->MCountName = ".mcount";
250       break;
251     }
252   }
253 };
254 
255 // FreeBSD Target
256 template<typename Target>
257 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258 protected:
259   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260                     MacroBuilder &Builder) const override {
261     // FreeBSD defines; list based off of gcc output
262 
263     unsigned Release = Triple.getOSMajorVersion();
264     if (Release == 0U)
265       Release = 8;
266 
267     Builder.defineMacro("__FreeBSD__", Twine(Release));
268     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270     DefineStd(Builder, "unix", Opts);
271     Builder.defineMacro("__ELF__");
272 
273     // On FreeBSD, wchar_t contains the number of the code point as
274     // used by the character set of the locale. These character sets are
275     // not necessarily a superset of ASCII.
276     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
277   }
278 public:
279   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
280     this->UserLabelPrefix = "";
281 
282     switch (Triple.getArch()) {
283     default:
284     case llvm::Triple::x86:
285     case llvm::Triple::x86_64:
286       this->MCountName = ".mcount";
287       break;
288     case llvm::Triple::mips:
289     case llvm::Triple::mipsel:
290     case llvm::Triple::ppc:
291     case llvm::Triple::ppc64:
292     case llvm::Triple::ppc64le:
293       this->MCountName = "_mcount";
294       break;
295     case llvm::Triple::arm:
296       this->MCountName = "__mcount";
297       break;
298     }
299   }
300 };
301 
302 // GNU/kFreeBSD Target
303 template<typename Target>
304 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
305 protected:
306   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
307                     MacroBuilder &Builder) const override {
308     // GNU/kFreeBSD defines; list based off of gcc output
309 
310     DefineStd(Builder, "unix", Opts);
311     Builder.defineMacro("__FreeBSD_kernel__");
312     Builder.defineMacro("__GLIBC__");
313     Builder.defineMacro("__ELF__");
314     if (Opts.POSIXThreads)
315       Builder.defineMacro("_REENTRANT");
316     if (Opts.CPlusPlus)
317       Builder.defineMacro("_GNU_SOURCE");
318   }
319 public:
320   KFreeBSDTargetInfo(const llvm::Triple &Triple)
321       : OSTargetInfo<Target>(Triple) {
322     this->UserLabelPrefix = "";
323   }
324 };
325 
326 // Minix Target
327 template<typename Target>
328 class MinixTargetInfo : public OSTargetInfo<Target> {
329 protected:
330   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
331                     MacroBuilder &Builder) const override {
332     // Minix defines
333 
334     Builder.defineMacro("__minix", "3");
335     Builder.defineMacro("_EM_WSIZE", "4");
336     Builder.defineMacro("_EM_PSIZE", "4");
337     Builder.defineMacro("_EM_SSIZE", "2");
338     Builder.defineMacro("_EM_LSIZE", "4");
339     Builder.defineMacro("_EM_FSIZE", "4");
340     Builder.defineMacro("_EM_DSIZE", "8");
341     Builder.defineMacro("__ELF__");
342     DefineStd(Builder, "unix", Opts);
343   }
344 public:
345   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
346     this->UserLabelPrefix = "";
347   }
348 };
349 
350 // Linux target
351 template<typename Target>
352 class LinuxTargetInfo : public OSTargetInfo<Target> {
353 protected:
354   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
355                     MacroBuilder &Builder) const override {
356     // Linux defines; list based off of gcc output
357     DefineStd(Builder, "unix", Opts);
358     DefineStd(Builder, "linux", Opts);
359     Builder.defineMacro("__gnu_linux__");
360     Builder.defineMacro("__ELF__");
361     if (Triple.getEnvironment() == llvm::Triple::Android)
362       Builder.defineMacro("__ANDROID__", "1");
363     if (Opts.POSIXThreads)
364       Builder.defineMacro("_REENTRANT");
365     if (Opts.CPlusPlus)
366       Builder.defineMacro("_GNU_SOURCE");
367   }
368 public:
369   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
370     this->UserLabelPrefix = "";
371     this->WIntType = TargetInfo::UnsignedInt;
372 
373     switch (Triple.getArch()) {
374     default:
375       break;
376     case llvm::Triple::ppc:
377     case llvm::Triple::ppc64:
378     case llvm::Triple::ppc64le:
379       this->MCountName = "_mcount";
380       break;
381     }
382   }
383 
384   const char *getStaticInitSectionSpecifier() const override {
385     return ".text.startup";
386   }
387 };
388 
389 // NetBSD Target
390 template<typename Target>
391 class NetBSDTargetInfo : public OSTargetInfo<Target> {
392 protected:
393   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
394                     MacroBuilder &Builder) const override {
395     // NetBSD defines; list based off of gcc output
396     Builder.defineMacro("__NetBSD__");
397     Builder.defineMacro("__unix__");
398     Builder.defineMacro("__ELF__");
399     if (Opts.POSIXThreads)
400       Builder.defineMacro("_POSIX_THREADS");
401 
402     switch (Triple.getArch()) {
403     default:
404       break;
405     case llvm::Triple::arm:
406     case llvm::Triple::armeb:
407     case llvm::Triple::thumb:
408     case llvm::Triple::thumbeb:
409       Builder.defineMacro("__ARM_DWARF_EH__");
410       break;
411     }
412   }
413 public:
414   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
415     this->UserLabelPrefix = "";
416   }
417 };
418 
419 // OpenBSD Target
420 template<typename Target>
421 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
422 protected:
423   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
424                     MacroBuilder &Builder) const override {
425     // OpenBSD defines; list based off of gcc output
426 
427     Builder.defineMacro("__OpenBSD__");
428     DefineStd(Builder, "unix", Opts);
429     Builder.defineMacro("__ELF__");
430     if (Opts.POSIXThreads)
431       Builder.defineMacro("_REENTRANT");
432   }
433 public:
434   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
435     this->UserLabelPrefix = "";
436     this->TLSSupported = false;
437 
438       switch (Triple.getArch()) {
439         default:
440         case llvm::Triple::x86:
441         case llvm::Triple::x86_64:
442         case llvm::Triple::arm:
443         case llvm::Triple::sparc:
444           this->MCountName = "__mcount";
445           break;
446         case llvm::Triple::mips64:
447         case llvm::Triple::mips64el:
448         case llvm::Triple::ppc:
449         case llvm::Triple::sparcv9:
450           this->MCountName = "_mcount";
451           break;
452       }
453   }
454 };
455 
456 // Bitrig Target
457 template<typename Target>
458 class BitrigTargetInfo : public OSTargetInfo<Target> {
459 protected:
460   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
461                     MacroBuilder &Builder) const override {
462     // Bitrig defines; list based off of gcc output
463 
464     Builder.defineMacro("__Bitrig__");
465     DefineStd(Builder, "unix", Opts);
466     Builder.defineMacro("__ELF__");
467     if (Opts.POSIXThreads)
468       Builder.defineMacro("_REENTRANT");
469   }
470 public:
471   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
472     this->UserLabelPrefix = "";
473     this->MCountName = "__mcount";
474   }
475 };
476 
477 // PSP Target
478 template<typename Target>
479 class PSPTargetInfo : public OSTargetInfo<Target> {
480 protected:
481   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
482                     MacroBuilder &Builder) const override {
483     // PSP defines; list based on the output of the pspdev gcc toolchain.
484     Builder.defineMacro("PSP");
485     Builder.defineMacro("_PSP");
486     Builder.defineMacro("__psp__");
487     Builder.defineMacro("__ELF__");
488   }
489 public:
490   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
491     this->UserLabelPrefix = "";
492   }
493 };
494 
495 // PS3 PPU Target
496 template<typename Target>
497 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
498 protected:
499   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
500                     MacroBuilder &Builder) const override {
501     // PS3 PPU defines.
502     Builder.defineMacro("__PPC__");
503     Builder.defineMacro("__PPU__");
504     Builder.defineMacro("__CELLOS_LV2__");
505     Builder.defineMacro("__ELF__");
506     Builder.defineMacro("__LP32__");
507     Builder.defineMacro("_ARCH_PPC64");
508     Builder.defineMacro("__powerpc64__");
509   }
510 public:
511   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
512     this->UserLabelPrefix = "";
513     this->LongWidth = this->LongAlign = 32;
514     this->PointerWidth = this->PointerAlign = 32;
515     this->IntMaxType = TargetInfo::SignedLongLong;
516     this->Int64Type = TargetInfo::SignedLongLong;
517     this->SizeType = TargetInfo::UnsignedInt;
518     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
519   }
520 };
521 
522 // Solaris target
523 template<typename Target>
524 class SolarisTargetInfo : public OSTargetInfo<Target> {
525 protected:
526   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527                     MacroBuilder &Builder) const override {
528     DefineStd(Builder, "sun", Opts);
529     DefineStd(Builder, "unix", Opts);
530     Builder.defineMacro("__ELF__");
531     Builder.defineMacro("__svr4__");
532     Builder.defineMacro("__SVR4");
533     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
534     // newer, but to 500 for everything else.  feature_test.h has a check to
535     // ensure that you are not using C99 with an old version of X/Open or C89
536     // with a new version.
537     if (Opts.C99)
538       Builder.defineMacro("_XOPEN_SOURCE", "600");
539     else
540       Builder.defineMacro("_XOPEN_SOURCE", "500");
541     if (Opts.CPlusPlus)
542       Builder.defineMacro("__C99FEATURES__");
543     Builder.defineMacro("_LARGEFILE_SOURCE");
544     Builder.defineMacro("_LARGEFILE64_SOURCE");
545     Builder.defineMacro("__EXTENSIONS__");
546     Builder.defineMacro("_REENTRANT");
547   }
548 public:
549   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
550     this->UserLabelPrefix = "";
551     this->WCharType = this->SignedInt;
552     // FIXME: WIntType should be SignedLong
553   }
554 };
555 
556 // Windows target
557 template<typename Target>
558 class WindowsTargetInfo : public OSTargetInfo<Target> {
559 protected:
560   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
561                     MacroBuilder &Builder) const override {
562     Builder.defineMacro("_WIN32");
563   }
564   void getVisualStudioDefines(const LangOptions &Opts,
565                               MacroBuilder &Builder) const {
566     if (Opts.CPlusPlus) {
567       if (Opts.RTTIData)
568         Builder.defineMacro("_CPPRTTI");
569 
570       if (Opts.Exceptions)
571         Builder.defineMacro("_CPPUNWIND");
572     }
573 
574     if (!Opts.CharIsSigned)
575       Builder.defineMacro("_CHAR_UNSIGNED");
576 
577     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
578     //        but it works for now.
579     if (Opts.POSIXThreads)
580       Builder.defineMacro("_MT");
581 
582     if (Opts.MSCompatibilityVersion) {
583       Builder.defineMacro("_MSC_VER",
584                           Twine(Opts.MSCompatibilityVersion / 100000));
585       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
586       // FIXME We cannot encode the revision information into 32-bits
587       Builder.defineMacro("_MSC_BUILD", Twine(1));
588     }
589 
590     if (Opts.MicrosoftExt) {
591       Builder.defineMacro("_MSC_EXTENSIONS");
592 
593       if (Opts.CPlusPlus11) {
594         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
595         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
596         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
597       }
598     }
599 
600     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
601   }
602 
603 public:
604   WindowsTargetInfo(const llvm::Triple &Triple)
605       : OSTargetInfo<Target>(Triple) {}
606 };
607 
608 template <typename Target>
609 class NaClTargetInfo : public OSTargetInfo<Target> {
610 protected:
611   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
612                     MacroBuilder &Builder) const override {
613     if (Opts.POSIXThreads)
614       Builder.defineMacro("_REENTRANT");
615     if (Opts.CPlusPlus)
616       Builder.defineMacro("_GNU_SOURCE");
617 
618     DefineStd(Builder, "unix", Opts);
619     Builder.defineMacro("__ELF__");
620     Builder.defineMacro("__native_client__");
621   }
622 
623 public:
624   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
625     this->UserLabelPrefix = "";
626     this->LongAlign = 32;
627     this->LongWidth = 32;
628     this->PointerAlign = 32;
629     this->PointerWidth = 32;
630     this->IntMaxType = TargetInfo::SignedLongLong;
631     this->Int64Type = TargetInfo::SignedLongLong;
632     this->DoubleAlign = 64;
633     this->LongDoubleWidth = 64;
634     this->LongDoubleAlign = 64;
635     this->LongLongWidth = 64;
636     this->LongLongAlign = 64;
637     this->SizeType = TargetInfo::UnsignedInt;
638     this->PtrDiffType = TargetInfo::SignedInt;
639     this->IntPtrType = TargetInfo::SignedInt;
640     // RegParmMax is inherited from the underlying architecture
641     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
642     if (Triple.getArch() == llvm::Triple::arm) {
643       this->DescriptionString =
644           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
645     } else if (Triple.getArch() == llvm::Triple::x86) {
646       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
647     } else if (Triple.getArch() == llvm::Triple::x86_64) {
648       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
649     } else if (Triple.getArch() == llvm::Triple::mipsel) {
650       // Handled on mips' setDescriptionString.
651     } else {
652       assert(Triple.getArch() == llvm::Triple::le32);
653       this->DescriptionString = "e-p:32:32-i64:64";
654     }
655   }
656   typename Target::CallingConvCheckResult checkCallingConvention(
657       CallingConv CC) const override {
658     return CC == CC_PnaclCall ? Target::CCCR_OK :
659         Target::checkCallingConvention(CC);
660   }
661 };
662 } // end anonymous namespace.
663 
664 //===----------------------------------------------------------------------===//
665 // Specific target implementations.
666 //===----------------------------------------------------------------------===//
667 
668 namespace {
669 // PPC abstract base class
670 class PPCTargetInfo : public TargetInfo {
671   static const Builtin::Info BuiltinInfo[];
672   static const char * const GCCRegNames[];
673   static const TargetInfo::GCCRegAlias GCCRegAliases[];
674   std::string CPU;
675 
676   // Target cpu features.
677   bool HasVSX;
678   bool HasP8Vector;
679 
680 protected:
681   std::string ABI;
682 
683 public:
684   PPCTargetInfo(const llvm::Triple &Triple)
685     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
686     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
687     LongDoubleWidth = LongDoubleAlign = 128;
688     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
689   }
690 
691   /// \brief Flags for architecture specific defines.
692   typedef enum {
693     ArchDefineNone  = 0,
694     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
695     ArchDefinePpcgr = 1 << 1,
696     ArchDefinePpcsq = 1 << 2,
697     ArchDefine440   = 1 << 3,
698     ArchDefine603   = 1 << 4,
699     ArchDefine604   = 1 << 5,
700     ArchDefinePwr4  = 1 << 6,
701     ArchDefinePwr5  = 1 << 7,
702     ArchDefinePwr5x = 1 << 8,
703     ArchDefinePwr6  = 1 << 9,
704     ArchDefinePwr6x = 1 << 10,
705     ArchDefinePwr7  = 1 << 11,
706     ArchDefinePwr8  = 1 << 12,
707     ArchDefineA2    = 1 << 13,
708     ArchDefineA2q   = 1 << 14
709   } ArchDefineTypes;
710 
711   // Note: GCC recognizes the following additional cpus:
712   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
713   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
714   //  titan, rs64.
715   bool setCPU(const std::string &Name) override {
716     bool CPUKnown = llvm::StringSwitch<bool>(Name)
717       .Case("generic", true)
718       .Case("440", true)
719       .Case("450", true)
720       .Case("601", true)
721       .Case("602", true)
722       .Case("603", true)
723       .Case("603e", true)
724       .Case("603ev", true)
725       .Case("604", true)
726       .Case("604e", true)
727       .Case("620", true)
728       .Case("630", true)
729       .Case("g3", true)
730       .Case("7400", true)
731       .Case("g4", true)
732       .Case("7450", true)
733       .Case("g4+", true)
734       .Case("750", true)
735       .Case("970", true)
736       .Case("g5", true)
737       .Case("a2", true)
738       .Case("a2q", true)
739       .Case("e500mc", true)
740       .Case("e5500", true)
741       .Case("power3", true)
742       .Case("pwr3", true)
743       .Case("power4", true)
744       .Case("pwr4", true)
745       .Case("power5", true)
746       .Case("pwr5", true)
747       .Case("power5x", true)
748       .Case("pwr5x", true)
749       .Case("power6", true)
750       .Case("pwr6", true)
751       .Case("power6x", true)
752       .Case("pwr6x", true)
753       .Case("power7", true)
754       .Case("pwr7", true)
755       .Case("power8", true)
756       .Case("pwr8", true)
757       .Case("powerpc", true)
758       .Case("ppc", true)
759       .Case("powerpc64", true)
760       .Case("ppc64", true)
761       .Case("powerpc64le", true)
762       .Case("ppc64le", true)
763       .Default(false);
764 
765     if (CPUKnown)
766       CPU = Name;
767 
768     return CPUKnown;
769   }
770 
771 
772   StringRef getABI() const override { return ABI; }
773 
774   void getTargetBuiltins(const Builtin::Info *&Records,
775                          unsigned &NumRecords) const override {
776     Records = BuiltinInfo;
777     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
778   }
779 
780   bool isCLZForZeroUndef() const override { return false; }
781 
782   void getTargetDefines(const LangOptions &Opts,
783                         MacroBuilder &Builder) const override;
784 
785   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
786 
787   bool handleTargetFeatures(std::vector<std::string> &Features,
788                             DiagnosticsEngine &Diags) override;
789   bool hasFeature(StringRef Feature) const override;
790 
791   void getGCCRegNames(const char * const *&Names,
792                       unsigned &NumNames) const override;
793   void getGCCRegAliases(const GCCRegAlias *&Aliases,
794                         unsigned &NumAliases) const override;
795   bool validateAsmConstraint(const char *&Name,
796                              TargetInfo::ConstraintInfo &Info) const override {
797     switch (*Name) {
798     default: return false;
799     case 'O': // Zero
800       break;
801     case 'b': // Base register
802     case 'f': // Floating point register
803       Info.setAllowsRegister();
804       break;
805     // FIXME: The following are added to allow parsing.
806     // I just took a guess at what the actions should be.
807     // Also, is more specific checking needed?  I.e. specific registers?
808     case 'd': // Floating point register (containing 64-bit value)
809     case 'v': // Altivec vector register
810       Info.setAllowsRegister();
811       break;
812     case 'w':
813       switch (Name[1]) {
814         case 'd':// VSX vector register to hold vector double data
815         case 'f':// VSX vector register to hold vector float data
816         case 's':// VSX vector register to hold scalar float data
817         case 'a':// Any VSX register
818         case 'c':// An individual CR bit
819           break;
820         default:
821           return false;
822       }
823       Info.setAllowsRegister();
824       Name++; // Skip over 'w'.
825       break;
826     case 'h': // `MQ', `CTR', or `LINK' register
827     case 'q': // `MQ' register
828     case 'c': // `CTR' register
829     case 'l': // `LINK' register
830     case 'x': // `CR' register (condition register) number 0
831     case 'y': // `CR' register (condition register)
832     case 'z': // `XER[CA]' carry bit (part of the XER register)
833       Info.setAllowsRegister();
834       break;
835     case 'I': // Signed 16-bit constant
836     case 'J': // Unsigned 16-bit constant shifted left 16 bits
837               //  (use `L' instead for SImode constants)
838     case 'K': // Unsigned 16-bit constant
839     case 'L': // Signed 16-bit constant shifted left 16 bits
840     case 'M': // Constant larger than 31
841     case 'N': // Exact power of 2
842     case 'P': // Constant whose negation is a signed 16-bit constant
843     case 'G': // Floating point constant that can be loaded into a
844               // register with one instruction per word
845     case 'H': // Integer/Floating point constant that can be loaded
846               // into a register using three instructions
847       break;
848     case 'm': // Memory operand. Note that on PowerPC targets, m can
849               // include addresses that update the base register. It
850               // is therefore only safe to use `m' in an asm statement
851               // if that asm statement accesses the operand exactly once.
852               // The asm statement must also use `%U<opno>' as a
853               // placeholder for the "update" flag in the corresponding
854               // load or store instruction. For example:
855               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
856               // is correct but:
857               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
858               // is not. Use es rather than m if you don't want the base
859               // register to be updated.
860     case 'e':
861       if (Name[1] != 's')
862           return false;
863               // es: A "stable" memory operand; that is, one which does not
864               // include any automodification of the base register. Unlike
865               // `m', this constraint can be used in asm statements that
866               // might access the operand several times, or that might not
867               // access it at all.
868       Info.setAllowsMemory();
869       Name++; // Skip over 'e'.
870       break;
871     case 'Q': // Memory operand that is an offset from a register (it is
872               // usually better to use `m' or `es' in asm statements)
873     case 'Z': // Memory operand that is an indexed or indirect from a
874               // register (it is usually better to use `m' or `es' in
875               // asm statements)
876       Info.setAllowsMemory();
877       Info.setAllowsRegister();
878       break;
879     case 'R': // AIX TOC entry
880     case 'a': // Address operand that is an indexed or indirect from a
881               // register (`p' is preferable for asm statements)
882     case 'S': // Constant suitable as a 64-bit mask operand
883     case 'T': // Constant suitable as a 32-bit mask operand
884     case 'U': // System V Release 4 small data area reference
885     case 't': // AND masks that can be performed by two rldic{l, r}
886               // instructions
887     case 'W': // Vector constant that does not require memory
888     case 'j': // Vector constant that is all zeros.
889       break;
890     // End FIXME.
891     }
892     return true;
893   }
894   std::string convertConstraint(const char *&Constraint) const override {
895     std::string R;
896     switch (*Constraint) {
897     case 'e':
898     case 'w':
899       // Two-character constraint; add "^" hint for later parsing.
900       R = std::string("^") + std::string(Constraint, 2);
901       Constraint++;
902       break;
903     default:
904       return TargetInfo::convertConstraint(Constraint);
905     }
906     return R;
907   }
908   const char *getClobbers() const override {
909     return "";
910   }
911   int getEHDataRegisterNumber(unsigned RegNo) const override {
912     if (RegNo == 0) return 3;
913     if (RegNo == 1) return 4;
914     return -1;
915   }
916 };
917 
918 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
919 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
920 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
921                                               ALL_LANGUAGES },
922 #include "clang/Basic/BuiltinsPPC.def"
923 };
924 
925 /// handleTargetFeatures - Perform initialization based on the user
926 /// configured set of features.
927 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
928                                          DiagnosticsEngine &Diags) {
929   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
930     // Ignore disabled features.
931     if (Features[i][0] == '-')
932       continue;
933 
934     StringRef Feature = StringRef(Features[i]).substr(1);
935 
936     if (Feature == "vsx") {
937       HasVSX = true;
938       continue;
939     }
940 
941     if (Feature == "power8-vector") {
942       HasP8Vector = true;
943       continue;
944     }
945 
946     // TODO: Finish this list and add an assert that we've handled them
947     // all.
948   }
949 
950   return true;
951 }
952 
953 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
954 /// #defines that are not tied to a specific subtarget.
955 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
956                                      MacroBuilder &Builder) const {
957   // Target identification.
958   Builder.defineMacro("__ppc__");
959   Builder.defineMacro("__PPC__");
960   Builder.defineMacro("_ARCH_PPC");
961   Builder.defineMacro("__powerpc__");
962   Builder.defineMacro("__POWERPC__");
963   if (PointerWidth == 64) {
964     Builder.defineMacro("_ARCH_PPC64");
965     Builder.defineMacro("__powerpc64__");
966     Builder.defineMacro("__ppc64__");
967     Builder.defineMacro("__PPC64__");
968   }
969 
970   // Target properties.
971   if (getTriple().getArch() == llvm::Triple::ppc64le) {
972     Builder.defineMacro("_LITTLE_ENDIAN");
973   } else {
974     if (getTriple().getOS() != llvm::Triple::NetBSD &&
975         getTriple().getOS() != llvm::Triple::OpenBSD)
976       Builder.defineMacro("_BIG_ENDIAN");
977   }
978 
979   // ABI options.
980   if (ABI == "elfv1")
981     Builder.defineMacro("_CALL_ELF", "1");
982   if (ABI == "elfv2")
983     Builder.defineMacro("_CALL_ELF", "2");
984 
985   // Subtarget options.
986   Builder.defineMacro("__NATURAL_ALIGNMENT__");
987   Builder.defineMacro("__REGISTER_PREFIX__", "");
988 
989   // FIXME: Should be controlled by command line option.
990   if (LongDoubleWidth == 128)
991     Builder.defineMacro("__LONG_DOUBLE_128__");
992 
993   if (Opts.AltiVec) {
994     Builder.defineMacro("__VEC__", "10206");
995     Builder.defineMacro("__ALTIVEC__");
996   }
997 
998   // CPU identification.
999   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1000     .Case("440",   ArchDefineName)
1001     .Case("450",   ArchDefineName | ArchDefine440)
1002     .Case("601",   ArchDefineName)
1003     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1004     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1005     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1006     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1007     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1008     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1009     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1010     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1011     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1012     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1013     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1014     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1015                      | ArchDefinePpcsq)
1016     .Case("a2",    ArchDefineA2)
1017     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1018     .Case("pwr3",  ArchDefinePpcgr)
1019     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1020     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1021                      | ArchDefinePpcsq)
1022     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1023                      | ArchDefinePpcgr | ArchDefinePpcsq)
1024     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1025                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1026     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1027                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1028                      | ArchDefinePpcsq)
1029     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1030                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1031                      | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1033                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1034                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1035     .Case("power3",  ArchDefinePpcgr)
1036     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1037     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1038                        | ArchDefinePpcsq)
1039     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1040                        | ArchDefinePpcgr | ArchDefinePpcsq)
1041     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1042                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1043     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1044                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1045                        | ArchDefinePpcsq)
1046     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1047                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1048                        | ArchDefinePpcgr | ArchDefinePpcsq)
1049     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1050                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1051                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1052     .Default(ArchDefineNone);
1053 
1054   if (defs & ArchDefineName)
1055     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1056   if (defs & ArchDefinePpcgr)
1057     Builder.defineMacro("_ARCH_PPCGR");
1058   if (defs & ArchDefinePpcsq)
1059     Builder.defineMacro("_ARCH_PPCSQ");
1060   if (defs & ArchDefine440)
1061     Builder.defineMacro("_ARCH_440");
1062   if (defs & ArchDefine603)
1063     Builder.defineMacro("_ARCH_603");
1064   if (defs & ArchDefine604)
1065     Builder.defineMacro("_ARCH_604");
1066   if (defs & ArchDefinePwr4)
1067     Builder.defineMacro("_ARCH_PWR4");
1068   if (defs & ArchDefinePwr5)
1069     Builder.defineMacro("_ARCH_PWR5");
1070   if (defs & ArchDefinePwr5x)
1071     Builder.defineMacro("_ARCH_PWR5X");
1072   if (defs & ArchDefinePwr6)
1073     Builder.defineMacro("_ARCH_PWR6");
1074   if (defs & ArchDefinePwr6x)
1075     Builder.defineMacro("_ARCH_PWR6X");
1076   if (defs & ArchDefinePwr7)
1077     Builder.defineMacro("_ARCH_PWR7");
1078   if (defs & ArchDefinePwr8)
1079     Builder.defineMacro("_ARCH_PWR8");
1080   if (defs & ArchDefineA2)
1081     Builder.defineMacro("_ARCH_A2");
1082   if (defs & ArchDefineA2q) {
1083     Builder.defineMacro("_ARCH_A2Q");
1084     Builder.defineMacro("_ARCH_QP");
1085   }
1086 
1087   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1088     Builder.defineMacro("__bg__");
1089     Builder.defineMacro("__THW_BLUEGENE__");
1090     Builder.defineMacro("__bgq__");
1091     Builder.defineMacro("__TOS_BGQ__");
1092   }
1093 
1094   if (HasVSX)
1095     Builder.defineMacro("__VSX__");
1096   if (HasP8Vector)
1097     Builder.defineMacro("__POWER8_VECTOR__");
1098 
1099   // FIXME: The following are not yet generated here by Clang, but are
1100   //        generated by GCC:
1101   //
1102   //   _SOFT_FLOAT_
1103   //   __RECIP_PRECISION__
1104   //   __APPLE_ALTIVEC__
1105   //   __RECIP__
1106   //   __RECIPF__
1107   //   __RSQRTE__
1108   //   __RSQRTEF__
1109   //   _SOFT_DOUBLE_
1110   //   __NO_LWSYNC__
1111   //   __HAVE_BSWAP__
1112   //   __LONGDOUBLE128
1113   //   __CMODEL_MEDIUM__
1114   //   __CMODEL_LARGE__
1115   //   _CALL_SYSV
1116   //   _CALL_DARWIN
1117   //   __NO_FPRS__
1118 }
1119 
1120 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1121   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1122     .Case("7400", true)
1123     .Case("g4", true)
1124     .Case("7450", true)
1125     .Case("g4+", true)
1126     .Case("970", true)
1127     .Case("g5", true)
1128     .Case("pwr6", true)
1129     .Case("pwr7", true)
1130     .Case("pwr8", true)
1131     .Case("ppc64", true)
1132     .Case("ppc64le", true)
1133     .Default(false);
1134 
1135   Features["qpx"] = (CPU == "a2q");
1136 
1137   if (!ABI.empty())
1138     Features[ABI] = true;
1139 }
1140 
1141 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1142   return llvm::StringSwitch<bool>(Feature)
1143     .Case("powerpc", true)
1144     .Case("vsx", HasVSX)
1145     .Case("power8-vector", HasP8Vector)
1146     .Default(false);
1147 }
1148 
1149 const char * const PPCTargetInfo::GCCRegNames[] = {
1150   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1151   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1152   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1153   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1154   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1155   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1156   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1157   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1158   "mq", "lr", "ctr", "ap",
1159   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1160   "xer",
1161   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1162   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1163   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1164   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1165   "vrsave", "vscr",
1166   "spe_acc", "spefscr",
1167   "sfp"
1168 };
1169 
1170 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1171                                    unsigned &NumNames) const {
1172   Names = GCCRegNames;
1173   NumNames = llvm::array_lengthof(GCCRegNames);
1174 }
1175 
1176 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1177   // While some of these aliases do map to different registers
1178   // they still share the same register name.
1179   { { "0" }, "r0" },
1180   { { "1"}, "r1" },
1181   { { "2" }, "r2" },
1182   { { "3" }, "r3" },
1183   { { "4" }, "r4" },
1184   { { "5" }, "r5" },
1185   { { "6" }, "r6" },
1186   { { "7" }, "r7" },
1187   { { "8" }, "r8" },
1188   { { "9" }, "r9" },
1189   { { "10" }, "r10" },
1190   { { "11" }, "r11" },
1191   { { "12" }, "r12" },
1192   { { "13" }, "r13" },
1193   { { "14" }, "r14" },
1194   { { "15" }, "r15" },
1195   { { "16" }, "r16" },
1196   { { "17" }, "r17" },
1197   { { "18" }, "r18" },
1198   { { "19" }, "r19" },
1199   { { "20" }, "r20" },
1200   { { "21" }, "r21" },
1201   { { "22" }, "r22" },
1202   { { "23" }, "r23" },
1203   { { "24" }, "r24" },
1204   { { "25" }, "r25" },
1205   { { "26" }, "r26" },
1206   { { "27" }, "r27" },
1207   { { "28" }, "r28" },
1208   { { "29" }, "r29" },
1209   { { "30" }, "r30" },
1210   { { "31" }, "r31" },
1211   { { "fr0" }, "f0" },
1212   { { "fr1" }, "f1" },
1213   { { "fr2" }, "f2" },
1214   { { "fr3" }, "f3" },
1215   { { "fr4" }, "f4" },
1216   { { "fr5" }, "f5" },
1217   { { "fr6" }, "f6" },
1218   { { "fr7" }, "f7" },
1219   { { "fr8" }, "f8" },
1220   { { "fr9" }, "f9" },
1221   { { "fr10" }, "f10" },
1222   { { "fr11" }, "f11" },
1223   { { "fr12" }, "f12" },
1224   { { "fr13" }, "f13" },
1225   { { "fr14" }, "f14" },
1226   { { "fr15" }, "f15" },
1227   { { "fr16" }, "f16" },
1228   { { "fr17" }, "f17" },
1229   { { "fr18" }, "f18" },
1230   { { "fr19" }, "f19" },
1231   { { "fr20" }, "f20" },
1232   { { "fr21" }, "f21" },
1233   { { "fr22" }, "f22" },
1234   { { "fr23" }, "f23" },
1235   { { "fr24" }, "f24" },
1236   { { "fr25" }, "f25" },
1237   { { "fr26" }, "f26" },
1238   { { "fr27" }, "f27" },
1239   { { "fr28" }, "f28" },
1240   { { "fr29" }, "f29" },
1241   { { "fr30" }, "f30" },
1242   { { "fr31" }, "f31" },
1243   { { "cc" }, "cr0" },
1244 };
1245 
1246 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1247                                      unsigned &NumAliases) const {
1248   Aliases = GCCRegAliases;
1249   NumAliases = llvm::array_lengthof(GCCRegAliases);
1250 }
1251 } // end anonymous namespace.
1252 
1253 namespace {
1254 class PPC32TargetInfo : public PPCTargetInfo {
1255 public:
1256   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1257     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1258 
1259     switch (getTriple().getOS()) {
1260     case llvm::Triple::Linux:
1261     case llvm::Triple::FreeBSD:
1262     case llvm::Triple::NetBSD:
1263       SizeType = UnsignedInt;
1264       PtrDiffType = SignedInt;
1265       IntPtrType = SignedInt;
1266       break;
1267     default:
1268       break;
1269     }
1270 
1271     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1272       LongDoubleWidth = LongDoubleAlign = 64;
1273       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1274     }
1275 
1276     // PPC32 supports atomics up to 4 bytes.
1277     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1278   }
1279 
1280   BuiltinVaListKind getBuiltinVaListKind() const override {
1281     // This is the ELF definition, and is overridden by the Darwin sub-target
1282     return TargetInfo::PowerABIBuiltinVaList;
1283   }
1284 };
1285 } // end anonymous namespace.
1286 
1287 // Note: ABI differences may eventually require us to have a separate
1288 // TargetInfo for little endian.
1289 namespace {
1290 class PPC64TargetInfo : public PPCTargetInfo {
1291 public:
1292   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1293     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1294     IntMaxType = SignedLong;
1295     Int64Type = SignedLong;
1296 
1297     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1298       DescriptionString = "e-m:e-i64:64-n32:64";
1299       ABI = "elfv2";
1300     } else {
1301       DescriptionString = "E-m:e-i64:64-n32:64";
1302       ABI = "elfv1";
1303     }
1304 
1305     switch (getTriple().getOS()) {
1306     case llvm::Triple::FreeBSD:
1307       LongDoubleWidth = LongDoubleAlign = 64;
1308       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1309       break;
1310     case llvm::Triple::NetBSD:
1311       IntMaxType = SignedLongLong;
1312       Int64Type = SignedLongLong;
1313       break;
1314     default:
1315       break;
1316     }
1317 
1318     // PPC64 supports atomics up to 8 bytes.
1319     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1320   }
1321   BuiltinVaListKind getBuiltinVaListKind() const override {
1322     return TargetInfo::CharPtrBuiltinVaList;
1323   }
1324   // PPC64 Linux-specifc ABI options.
1325   bool setABI(const std::string &Name) override {
1326     if (Name == "elfv1" || Name == "elfv2") {
1327       ABI = Name;
1328       return true;
1329     }
1330     return false;
1331   }
1332 };
1333 } // end anonymous namespace.
1334 
1335 
1336 namespace {
1337 class DarwinPPC32TargetInfo :
1338   public DarwinTargetInfo<PPC32TargetInfo> {
1339 public:
1340   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1341       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1342     HasAlignMac68kSupport = true;
1343     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1344     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1345     LongLongAlign = 32;
1346     SuitableAlign = 128;
1347     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1348   }
1349   BuiltinVaListKind getBuiltinVaListKind() const override {
1350     return TargetInfo::CharPtrBuiltinVaList;
1351   }
1352 };
1353 
1354 class DarwinPPC64TargetInfo :
1355   public DarwinTargetInfo<PPC64TargetInfo> {
1356 public:
1357   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1358       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1359     HasAlignMac68kSupport = true;
1360     SuitableAlign = 128;
1361     DescriptionString = "E-m:o-i64:64-n32:64";
1362   }
1363 };
1364 } // end anonymous namespace.
1365 
1366 namespace {
1367   static const unsigned NVPTXAddrSpaceMap[] = {
1368     1,    // opencl_global
1369     3,    // opencl_local
1370     4,    // opencl_constant
1371     // FIXME: generic has to be added to the target
1372     0,    // opencl_generic
1373     1,    // cuda_device
1374     4,    // cuda_constant
1375     3,    // cuda_shared
1376   };
1377   class NVPTXTargetInfo : public TargetInfo {
1378     static const char * const GCCRegNames[];
1379     static const Builtin::Info BuiltinInfo[];
1380 
1381   // The GPU profiles supported by the NVPTX backend
1382   enum GPUKind {
1383     GK_NONE,
1384     GK_SM20,
1385     GK_SM21,
1386     GK_SM30,
1387     GK_SM35,
1388   } GPU;
1389 
1390   public:
1391     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1392       BigEndian = false;
1393       TLSSupported = false;
1394       LongWidth = LongAlign = 64;
1395       AddrSpaceMap = &NVPTXAddrSpaceMap;
1396       UseAddrSpaceMapMangling = true;
1397       // Define available target features
1398       // These must be defined in sorted order!
1399       NoAsmVariants = true;
1400       // Set the default GPU to sm20
1401       GPU = GK_SM20;
1402     }
1403     void getTargetDefines(const LangOptions &Opts,
1404                           MacroBuilder &Builder) const override {
1405       Builder.defineMacro("__PTX__");
1406       Builder.defineMacro("__NVPTX__");
1407       if (Opts.CUDAIsDevice) {
1408         // Set __CUDA_ARCH__ for the GPU specified.
1409         std::string CUDAArchCode;
1410         switch (GPU) {
1411         case GK_SM20:
1412           CUDAArchCode = "200";
1413           break;
1414         case GK_SM21:
1415           CUDAArchCode = "210";
1416           break;
1417         case GK_SM30:
1418           CUDAArchCode = "300";
1419           break;
1420         case GK_SM35:
1421           CUDAArchCode = "350";
1422           break;
1423         default:
1424           llvm_unreachable("Unhandled target CPU");
1425         }
1426         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1427       }
1428     }
1429     void getTargetBuiltins(const Builtin::Info *&Records,
1430                            unsigned &NumRecords) const override {
1431       Records = BuiltinInfo;
1432       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1433     }
1434     bool hasFeature(StringRef Feature) const override {
1435       return Feature == "ptx" || Feature == "nvptx";
1436     }
1437 
1438     void getGCCRegNames(const char * const *&Names,
1439                         unsigned &NumNames) const override;
1440     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1441                                   unsigned &NumAliases) const override {
1442       // No aliases.
1443       Aliases = nullptr;
1444       NumAliases = 0;
1445     }
1446     bool
1447     validateAsmConstraint(const char *&Name,
1448                           TargetInfo::ConstraintInfo &Info) const override {
1449       switch (*Name) {
1450       default: return false;
1451       case 'c':
1452       case 'h':
1453       case 'r':
1454       case 'l':
1455       case 'f':
1456       case 'd':
1457         Info.setAllowsRegister();
1458         return true;
1459       }
1460     }
1461     const char *getClobbers() const override {
1462       // FIXME: Is this really right?
1463       return "";
1464     }
1465     BuiltinVaListKind getBuiltinVaListKind() const override {
1466       // FIXME: implement
1467       return TargetInfo::CharPtrBuiltinVaList;
1468     }
1469     bool setCPU(const std::string &Name) override {
1470       GPU = llvm::StringSwitch<GPUKind>(Name)
1471                 .Case("sm_20", GK_SM20)
1472                 .Case("sm_21", GK_SM21)
1473                 .Case("sm_30", GK_SM30)
1474                 .Case("sm_35", GK_SM35)
1475                 .Default(GK_NONE);
1476 
1477       return GPU != GK_NONE;
1478     }
1479   };
1480 
1481   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1482 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1483 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1484                                               ALL_LANGUAGES },
1485 #include "clang/Basic/BuiltinsNVPTX.def"
1486   };
1487 
1488   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1489     "r0"
1490   };
1491 
1492   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1493                                      unsigned &NumNames) const {
1494     Names = GCCRegNames;
1495     NumNames = llvm::array_lengthof(GCCRegNames);
1496   }
1497 
1498   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1499   public:
1500     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1501       PointerWidth = PointerAlign = 32;
1502       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1503       IntPtrType = TargetInfo::SignedInt;
1504       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1505   }
1506   };
1507 
1508   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1509   public:
1510     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1511       PointerWidth = PointerAlign = 64;
1512       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1513       IntPtrType = TargetInfo::SignedLongLong;
1514       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1515   }
1516   };
1517 }
1518 
1519 namespace {
1520 
1521 static const unsigned R600AddrSpaceMap[] = {
1522   1,    // opencl_global
1523   3,    // opencl_local
1524   2,    // opencl_constant
1525   4,    // opencl_generic
1526   1,    // cuda_device
1527   2,    // cuda_constant
1528   3     // cuda_shared
1529 };
1530 
1531 // If you edit the description strings, make sure you update
1532 // getPointerWidthV().
1533 
1534 static const char *DescriptionStringR600 =
1535   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1536   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1537 
1538 static const char *DescriptionStringR600DoubleOps =
1539   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1540   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1541 
1542 static const char *DescriptionStringSI =
1543   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1544   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1545   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1546 
1547 class R600TargetInfo : public TargetInfo {
1548   static const Builtin::Info BuiltinInfo[];
1549 
1550   /// \brief The GPU profiles supported by the R600 target.
1551   enum GPUKind {
1552     GK_NONE,
1553     GK_R600,
1554     GK_R600_DOUBLE_OPS,
1555     GK_R700,
1556     GK_R700_DOUBLE_OPS,
1557     GK_EVERGREEN,
1558     GK_EVERGREEN_DOUBLE_OPS,
1559     GK_NORTHERN_ISLANDS,
1560     GK_CAYMAN,
1561     GK_SOUTHERN_ISLANDS,
1562     GK_SEA_ISLANDS
1563   } GPU;
1564 
1565 public:
1566   R600TargetInfo(const llvm::Triple &Triple)
1567       : TargetInfo(Triple), GPU(GK_R600) {
1568     DescriptionString = DescriptionStringR600;
1569     AddrSpaceMap = &R600AddrSpaceMap;
1570     UseAddrSpaceMapMangling = true;
1571   }
1572 
1573   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1574     if (GPU <= GK_CAYMAN)
1575       return 32;
1576 
1577     switch(AddrSpace) {
1578       default:
1579         return 64;
1580       case 0:
1581       case 3:
1582       case 5:
1583         return 32;
1584     }
1585   }
1586 
1587   const char * getClobbers() const override {
1588     return "";
1589   }
1590 
1591   void getGCCRegNames(const char * const *&Names,
1592                       unsigned &numNames) const override {
1593     Names = nullptr;
1594     numNames = 0;
1595   }
1596 
1597   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1598                         unsigned &NumAliases) const override {
1599     Aliases = nullptr;
1600     NumAliases = 0;
1601   }
1602 
1603   bool validateAsmConstraint(const char *&Name,
1604                              TargetInfo::ConstraintInfo &info) const override {
1605     return true;
1606   }
1607 
1608   void getTargetBuiltins(const Builtin::Info *&Records,
1609                          unsigned &NumRecords) const override {
1610     Records = BuiltinInfo;
1611     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1612   }
1613 
1614   void getTargetDefines(const LangOptions &Opts,
1615                         MacroBuilder &Builder) const override {
1616     Builder.defineMacro("__R600__");
1617   }
1618 
1619   BuiltinVaListKind getBuiltinVaListKind() const override {
1620     return TargetInfo::CharPtrBuiltinVaList;
1621   }
1622 
1623   bool setCPU(const std::string &Name) override {
1624     GPU = llvm::StringSwitch<GPUKind>(Name)
1625       .Case("r600" ,    GK_R600)
1626       .Case("rv610",    GK_R600)
1627       .Case("rv620",    GK_R600)
1628       .Case("rv630",    GK_R600)
1629       .Case("rv635",    GK_R600)
1630       .Case("rs780",    GK_R600)
1631       .Case("rs880",    GK_R600)
1632       .Case("rv670",    GK_R600_DOUBLE_OPS)
1633       .Case("rv710",    GK_R700)
1634       .Case("rv730",    GK_R700)
1635       .Case("rv740",    GK_R700_DOUBLE_OPS)
1636       .Case("rv770",    GK_R700_DOUBLE_OPS)
1637       .Case("palm",     GK_EVERGREEN)
1638       .Case("cedar",    GK_EVERGREEN)
1639       .Case("sumo",     GK_EVERGREEN)
1640       .Case("sumo2",    GK_EVERGREEN)
1641       .Case("redwood",  GK_EVERGREEN)
1642       .Case("juniper",  GK_EVERGREEN)
1643       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1644       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1645       .Case("barts",    GK_NORTHERN_ISLANDS)
1646       .Case("turks",    GK_NORTHERN_ISLANDS)
1647       .Case("caicos",   GK_NORTHERN_ISLANDS)
1648       .Case("cayman",   GK_CAYMAN)
1649       .Case("aruba",    GK_CAYMAN)
1650       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1651       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1652       .Case("verde",    GK_SOUTHERN_ISLANDS)
1653       .Case("oland",    GK_SOUTHERN_ISLANDS)
1654       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1655       .Case("bonaire",  GK_SEA_ISLANDS)
1656       .Case("kabini",   GK_SEA_ISLANDS)
1657       .Case("kaveri",   GK_SEA_ISLANDS)
1658       .Case("hawaii",   GK_SEA_ISLANDS)
1659       .Case("mullins",  GK_SEA_ISLANDS)
1660       .Default(GK_NONE);
1661 
1662     if (GPU == GK_NONE) {
1663       return false;
1664     }
1665 
1666     // Set the correct data layout
1667     switch (GPU) {
1668     case GK_NONE:
1669     case GK_R600:
1670     case GK_R700:
1671     case GK_EVERGREEN:
1672     case GK_NORTHERN_ISLANDS:
1673       DescriptionString = DescriptionStringR600;
1674       break;
1675     case GK_R600_DOUBLE_OPS:
1676     case GK_R700_DOUBLE_OPS:
1677     case GK_EVERGREEN_DOUBLE_OPS:
1678     case GK_CAYMAN:
1679       DescriptionString = DescriptionStringR600DoubleOps;
1680       break;
1681     case GK_SOUTHERN_ISLANDS:
1682     case GK_SEA_ISLANDS:
1683       DescriptionString = DescriptionStringSI;
1684       break;
1685     }
1686 
1687     return true;
1688   }
1689 };
1690 
1691 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1692 #define BUILTIN(ID, TYPE, ATTRS)                \
1693   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1694 #include "clang/Basic/BuiltinsR600.def"
1695 };
1696 
1697 } // end anonymous namespace
1698 
1699 namespace {
1700 // Namespace for x86 abstract base class
1701 const Builtin::Info BuiltinInfo[] = {
1702 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1703 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1704                                               ALL_LANGUAGES },
1705 #include "clang/Basic/BuiltinsX86.def"
1706 };
1707 
1708 static const char* const GCCRegNames[] = {
1709   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1710   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1711   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1712   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1713   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1714   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1715   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1716   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1717   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1718 };
1719 
1720 const TargetInfo::AddlRegName AddlRegNames[] = {
1721   { { "al", "ah", "eax", "rax" }, 0 },
1722   { { "bl", "bh", "ebx", "rbx" }, 3 },
1723   { { "cl", "ch", "ecx", "rcx" }, 2 },
1724   { { "dl", "dh", "edx", "rdx" }, 1 },
1725   { { "esi", "rsi" }, 4 },
1726   { { "edi", "rdi" }, 5 },
1727   { { "esp", "rsp" }, 7 },
1728   { { "ebp", "rbp" }, 6 },
1729 };
1730 
1731 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1732 // most of the implementation can be shared.
1733 class X86TargetInfo : public TargetInfo {
1734   enum X86SSEEnum {
1735     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1736   } SSELevel;
1737   enum MMX3DNowEnum {
1738     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1739   } MMX3DNowLevel;
1740   enum XOPEnum {
1741     NoXOP,
1742     SSE4A,
1743     FMA4,
1744     XOP
1745   } XOPLevel;
1746 
1747   bool HasAES;
1748   bool HasPCLMUL;
1749   bool HasLZCNT;
1750   bool HasRDRND;
1751   bool HasFSGSBASE;
1752   bool HasBMI;
1753   bool HasBMI2;
1754   bool HasPOPCNT;
1755   bool HasRTM;
1756   bool HasPRFCHW;
1757   bool HasRDSEED;
1758   bool HasADX;
1759   bool HasTBM;
1760   bool HasFMA;
1761   bool HasF16C;
1762   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1763       HasAVX512VL;
1764   bool HasSHA;
1765   bool HasCX16;
1766 
1767   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1768   ///
1769   /// Each enumeration represents a particular CPU supported by Clang. These
1770   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1771   enum CPUKind {
1772     CK_Generic,
1773 
1774     /// \name i386
1775     /// i386-generation processors.
1776     //@{
1777     CK_i386,
1778     //@}
1779 
1780     /// \name i486
1781     /// i486-generation processors.
1782     //@{
1783     CK_i486,
1784     CK_WinChipC6,
1785     CK_WinChip2,
1786     CK_C3,
1787     //@}
1788 
1789     /// \name i586
1790     /// i586-generation processors, P5 microarchitecture based.
1791     //@{
1792     CK_i586,
1793     CK_Pentium,
1794     CK_PentiumMMX,
1795     //@}
1796 
1797     /// \name i686
1798     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1799     //@{
1800     CK_i686,
1801     CK_PentiumPro,
1802     CK_Pentium2,
1803     CK_Pentium3,
1804     CK_Pentium3M,
1805     CK_PentiumM,
1806     CK_C3_2,
1807 
1808     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1809     /// Clang however has some logic to suport this.
1810     // FIXME: Warn, deprecate, and potentially remove this.
1811     CK_Yonah,
1812     //@}
1813 
1814     /// \name Netburst
1815     /// Netburst microarchitecture based processors.
1816     //@{
1817     CK_Pentium4,
1818     CK_Pentium4M,
1819     CK_Prescott,
1820     CK_Nocona,
1821     //@}
1822 
1823     /// \name Core
1824     /// Core microarchitecture based processors.
1825     //@{
1826     CK_Core2,
1827 
1828     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1829     /// codename which GCC no longer accepts as an option to -march, but Clang
1830     /// has some logic for recognizing it.
1831     // FIXME: Warn, deprecate, and potentially remove this.
1832     CK_Penryn,
1833     //@}
1834 
1835     /// \name Atom
1836     /// Atom processors
1837     //@{
1838     CK_Bonnell,
1839     CK_Silvermont,
1840     //@}
1841 
1842     /// \name Nehalem
1843     /// Nehalem microarchitecture based processors.
1844     CK_Nehalem,
1845 
1846     /// \name Westmere
1847     /// Westmere microarchitecture based processors.
1848     CK_Westmere,
1849 
1850     /// \name Sandy Bridge
1851     /// Sandy Bridge microarchitecture based processors.
1852     CK_SandyBridge,
1853 
1854     /// \name Ivy Bridge
1855     /// Ivy Bridge microarchitecture based processors.
1856     CK_IvyBridge,
1857 
1858     /// \name Haswell
1859     /// Haswell microarchitecture based processors.
1860     CK_Haswell,
1861 
1862     /// \name Broadwell
1863     /// Broadwell microarchitecture based processors.
1864     CK_Broadwell,
1865 
1866     /// \name Skylake
1867     /// Skylake microarchitecture based processors.
1868     CK_Skylake,
1869 
1870     /// \name Knights Landing
1871     /// Knights Landing processor.
1872     CK_KNL,
1873 
1874     /// \name K6
1875     /// K6 architecture processors.
1876     //@{
1877     CK_K6,
1878     CK_K6_2,
1879     CK_K6_3,
1880     //@}
1881 
1882     /// \name K7
1883     /// K7 architecture processors.
1884     //@{
1885     CK_Athlon,
1886     CK_AthlonThunderbird,
1887     CK_Athlon4,
1888     CK_AthlonXP,
1889     CK_AthlonMP,
1890     //@}
1891 
1892     /// \name K8
1893     /// K8 architecture processors.
1894     //@{
1895     CK_Athlon64,
1896     CK_Athlon64SSE3,
1897     CK_AthlonFX,
1898     CK_K8,
1899     CK_K8SSE3,
1900     CK_Opteron,
1901     CK_OpteronSSE3,
1902     CK_AMDFAM10,
1903     //@}
1904 
1905     /// \name Bobcat
1906     /// Bobcat architecture processors.
1907     //@{
1908     CK_BTVER1,
1909     CK_BTVER2,
1910     //@}
1911 
1912     /// \name Bulldozer
1913     /// Bulldozer architecture processors.
1914     //@{
1915     CK_BDVER1,
1916     CK_BDVER2,
1917     CK_BDVER3,
1918     CK_BDVER4,
1919     //@}
1920 
1921     /// This specification is deprecated and will be removed in the future.
1922     /// Users should prefer \see CK_K8.
1923     // FIXME: Warn on this when the CPU is set to it.
1924     //@{
1925     CK_x86_64,
1926     //@}
1927 
1928     /// \name Geode
1929     /// Geode processors.
1930     //@{
1931     CK_Geode
1932     //@}
1933   } CPU;
1934 
1935   enum FPMathKind {
1936     FP_Default,
1937     FP_SSE,
1938     FP_387
1939   } FPMath;
1940 
1941 public:
1942   X86TargetInfo(const llvm::Triple &Triple)
1943       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1944         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1945         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1946         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1947         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1948         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1949         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1950         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1951     BigEndian = false;
1952     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1953   }
1954   unsigned getFloatEvalMethod() const override {
1955     // X87 evaluates with 80 bits "long double" precision.
1956     return SSELevel == NoSSE ? 2 : 0;
1957   }
1958   void getTargetBuiltins(const Builtin::Info *&Records,
1959                                  unsigned &NumRecords) const override {
1960     Records = BuiltinInfo;
1961     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1962   }
1963   void getGCCRegNames(const char * const *&Names,
1964                       unsigned &NumNames) const override {
1965     Names = GCCRegNames;
1966     NumNames = llvm::array_lengthof(GCCRegNames);
1967   }
1968   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1969                         unsigned &NumAliases) const override {
1970     Aliases = nullptr;
1971     NumAliases = 0;
1972   }
1973   void getGCCAddlRegNames(const AddlRegName *&Names,
1974                           unsigned &NumNames) const override {
1975     Names = AddlRegNames;
1976     NumNames = llvm::array_lengthof(AddlRegNames);
1977   }
1978   bool validateAsmConstraint(const char *&Name,
1979                              TargetInfo::ConstraintInfo &info) const override;
1980 
1981   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1982 
1983   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1984 
1985   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1986 
1987   std::string convertConstraint(const char *&Constraint) const override;
1988   const char *getClobbers() const override {
1989     return "~{dirflag},~{fpsr},~{flags}";
1990   }
1991   void getTargetDefines(const LangOptions &Opts,
1992                         MacroBuilder &Builder) const override;
1993   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1994                           bool Enabled);
1995   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1996                           bool Enabled);
1997   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1998                           bool Enabled);
1999   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2000                          StringRef Name, bool Enabled) const override {
2001     setFeatureEnabledImpl(Features, Name, Enabled);
2002   }
2003   // This exists purely to cut down on the number of virtual calls in
2004   // getDefaultFeatures which calls this repeatedly.
2005   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2006                                     StringRef Name, bool Enabled);
2007   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2008   bool hasFeature(StringRef Feature) const override;
2009   bool handleTargetFeatures(std::vector<std::string> &Features,
2010                             DiagnosticsEngine &Diags) override;
2011   StringRef getABI() const override {
2012     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2013       return "avx";
2014     else if (getTriple().getArch() == llvm::Triple::x86 &&
2015              MMX3DNowLevel == NoMMX3DNow)
2016       return "no-mmx";
2017     return "";
2018   }
2019   bool setCPU(const std::string &Name) override {
2020     CPU = llvm::StringSwitch<CPUKind>(Name)
2021       .Case("i386", CK_i386)
2022       .Case("i486", CK_i486)
2023       .Case("winchip-c6", CK_WinChipC6)
2024       .Case("winchip2", CK_WinChip2)
2025       .Case("c3", CK_C3)
2026       .Case("i586", CK_i586)
2027       .Case("pentium", CK_Pentium)
2028       .Case("pentium-mmx", CK_PentiumMMX)
2029       .Case("i686", CK_i686)
2030       .Case("pentiumpro", CK_PentiumPro)
2031       .Case("pentium2", CK_Pentium2)
2032       .Case("pentium3", CK_Pentium3)
2033       .Case("pentium3m", CK_Pentium3M)
2034       .Case("pentium-m", CK_PentiumM)
2035       .Case("c3-2", CK_C3_2)
2036       .Case("yonah", CK_Yonah)
2037       .Case("pentium4", CK_Pentium4)
2038       .Case("pentium4m", CK_Pentium4M)
2039       .Case("prescott", CK_Prescott)
2040       .Case("nocona", CK_Nocona)
2041       .Case("core2", CK_Core2)
2042       .Case("penryn", CK_Penryn)
2043       .Case("bonnell", CK_Bonnell)
2044       .Case("atom", CK_Bonnell) // Legacy name.
2045       .Case("silvermont", CK_Silvermont)
2046       .Case("slm", CK_Silvermont) // Legacy name.
2047       .Case("nehalem", CK_Nehalem)
2048       .Case("corei7", CK_Nehalem) // Legacy name.
2049       .Case("westmere", CK_Westmere)
2050       .Case("sandybridge", CK_SandyBridge)
2051       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2052       .Case("ivybridge", CK_IvyBridge)
2053       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2054       .Case("haswell", CK_Haswell)
2055       .Case("core-avx2", CK_Haswell) // Legacy name.
2056       .Case("broadwell", CK_Broadwell)
2057       .Case("skylake", CK_Skylake)
2058       .Case("skx", CK_Skylake) // Legacy name.
2059       .Case("knl", CK_KNL)
2060       .Case("k6", CK_K6)
2061       .Case("k6-2", CK_K6_2)
2062       .Case("k6-3", CK_K6_3)
2063       .Case("athlon", CK_Athlon)
2064       .Case("athlon-tbird", CK_AthlonThunderbird)
2065       .Case("athlon-4", CK_Athlon4)
2066       .Case("athlon-xp", CK_AthlonXP)
2067       .Case("athlon-mp", CK_AthlonMP)
2068       .Case("athlon64", CK_Athlon64)
2069       .Case("athlon64-sse3", CK_Athlon64SSE3)
2070       .Case("athlon-fx", CK_AthlonFX)
2071       .Case("k8", CK_K8)
2072       .Case("k8-sse3", CK_K8SSE3)
2073       .Case("opteron", CK_Opteron)
2074       .Case("opteron-sse3", CK_OpteronSSE3)
2075       .Case("barcelona", CK_AMDFAM10)
2076       .Case("amdfam10", CK_AMDFAM10)
2077       .Case("btver1", CK_BTVER1)
2078       .Case("btver2", CK_BTVER2)
2079       .Case("bdver1", CK_BDVER1)
2080       .Case("bdver2", CK_BDVER2)
2081       .Case("bdver3", CK_BDVER3)
2082       .Case("bdver4", CK_BDVER4)
2083       .Case("x86-64", CK_x86_64)
2084       .Case("geode", CK_Geode)
2085       .Default(CK_Generic);
2086 
2087     // Perform any per-CPU checks necessary to determine if this CPU is
2088     // acceptable.
2089     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2090     // invalid without explaining *why*.
2091     switch (CPU) {
2092     case CK_Generic:
2093       // No processor selected!
2094       return false;
2095 
2096     case CK_i386:
2097     case CK_i486:
2098     case CK_WinChipC6:
2099     case CK_WinChip2:
2100     case CK_C3:
2101     case CK_i586:
2102     case CK_Pentium:
2103     case CK_PentiumMMX:
2104     case CK_i686:
2105     case CK_PentiumPro:
2106     case CK_Pentium2:
2107     case CK_Pentium3:
2108     case CK_Pentium3M:
2109     case CK_PentiumM:
2110     case CK_Yonah:
2111     case CK_C3_2:
2112     case CK_Pentium4:
2113     case CK_Pentium4M:
2114     case CK_Prescott:
2115     case CK_K6:
2116     case CK_K6_2:
2117     case CK_K6_3:
2118     case CK_Athlon:
2119     case CK_AthlonThunderbird:
2120     case CK_Athlon4:
2121     case CK_AthlonXP:
2122     case CK_AthlonMP:
2123     case CK_Geode:
2124       // Only accept certain architectures when compiling in 32-bit mode.
2125       if (getTriple().getArch() != llvm::Triple::x86)
2126         return false;
2127 
2128       // Fallthrough
2129     case CK_Nocona:
2130     case CK_Core2:
2131     case CK_Penryn:
2132     case CK_Bonnell:
2133     case CK_Silvermont:
2134     case CK_Nehalem:
2135     case CK_Westmere:
2136     case CK_SandyBridge:
2137     case CK_IvyBridge:
2138     case CK_Haswell:
2139     case CK_Broadwell:
2140     case CK_Skylake:
2141     case CK_KNL:
2142     case CK_Athlon64:
2143     case CK_Athlon64SSE3:
2144     case CK_AthlonFX:
2145     case CK_K8:
2146     case CK_K8SSE3:
2147     case CK_Opteron:
2148     case CK_OpteronSSE3:
2149     case CK_AMDFAM10:
2150     case CK_BTVER1:
2151     case CK_BTVER2:
2152     case CK_BDVER1:
2153     case CK_BDVER2:
2154     case CK_BDVER3:
2155     case CK_BDVER4:
2156     case CK_x86_64:
2157       return true;
2158     }
2159     llvm_unreachable("Unhandled CPU kind");
2160   }
2161 
2162   bool setFPMath(StringRef Name) override;
2163 
2164   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2165     // We accept all non-ARM calling conventions
2166     return (CC == CC_X86ThisCall ||
2167             CC == CC_X86FastCall ||
2168             CC == CC_X86StdCall ||
2169             CC == CC_X86VectorCall ||
2170             CC == CC_C ||
2171             CC == CC_X86Pascal ||
2172             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2173   }
2174 
2175   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2176     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2177   }
2178 };
2179 
2180 bool X86TargetInfo::setFPMath(StringRef Name) {
2181   if (Name == "387") {
2182     FPMath = FP_387;
2183     return true;
2184   }
2185   if (Name == "sse") {
2186     FPMath = FP_SSE;
2187     return true;
2188   }
2189   return false;
2190 }
2191 
2192 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2193   // FIXME: This *really* should not be here.
2194 
2195   // X86_64 always has SSE2.
2196   if (getTriple().getArch() == llvm::Triple::x86_64)
2197     setFeatureEnabledImpl(Features, "sse2", true);
2198 
2199   switch (CPU) {
2200   case CK_Generic:
2201   case CK_i386:
2202   case CK_i486:
2203   case CK_i586:
2204   case CK_Pentium:
2205   case CK_i686:
2206   case CK_PentiumPro:
2207     break;
2208   case CK_PentiumMMX:
2209   case CK_Pentium2:
2210   case CK_K6:
2211   case CK_WinChipC6:
2212     setFeatureEnabledImpl(Features, "mmx", true);
2213     break;
2214   case CK_Pentium3:
2215   case CK_Pentium3M:
2216   case CK_C3_2:
2217     setFeatureEnabledImpl(Features, "sse", true);
2218     break;
2219   case CK_PentiumM:
2220   case CK_Pentium4:
2221   case CK_Pentium4M:
2222   case CK_x86_64:
2223     setFeatureEnabledImpl(Features, "sse2", true);
2224     break;
2225   case CK_Yonah:
2226   case CK_Prescott:
2227   case CK_Nocona:
2228     setFeatureEnabledImpl(Features, "sse3", true);
2229     setFeatureEnabledImpl(Features, "cx16", true);
2230     break;
2231   case CK_Core2:
2232   case CK_Bonnell:
2233     setFeatureEnabledImpl(Features, "ssse3", true);
2234     setFeatureEnabledImpl(Features, "cx16", true);
2235     break;
2236   case CK_Penryn:
2237     setFeatureEnabledImpl(Features, "sse4.1", true);
2238     setFeatureEnabledImpl(Features, "cx16", true);
2239     break;
2240   case CK_Skylake:
2241     setFeatureEnabledImpl(Features, "avx512f", true);
2242     setFeatureEnabledImpl(Features, "avx512cd", true);
2243     setFeatureEnabledImpl(Features, "avx512dq", true);
2244     setFeatureEnabledImpl(Features, "avx512bw", true);
2245     setFeatureEnabledImpl(Features, "avx512vl", true);
2246     // FALLTHROUGH
2247   case CK_Broadwell:
2248     setFeatureEnabledImpl(Features, "rdseed", true);
2249     setFeatureEnabledImpl(Features, "adx", true);
2250     // FALLTHROUGH
2251   case CK_Haswell:
2252     setFeatureEnabledImpl(Features, "avx2", true);
2253     setFeatureEnabledImpl(Features, "lzcnt", true);
2254     setFeatureEnabledImpl(Features, "bmi", true);
2255     setFeatureEnabledImpl(Features, "bmi2", true);
2256     setFeatureEnabledImpl(Features, "rtm", true);
2257     setFeatureEnabledImpl(Features, "fma", true);
2258     // FALLTHROUGH
2259   case CK_IvyBridge:
2260     setFeatureEnabledImpl(Features, "rdrnd", true);
2261     setFeatureEnabledImpl(Features, "f16c", true);
2262     setFeatureEnabledImpl(Features, "fsgsbase", true);
2263     // FALLTHROUGH
2264   case CK_SandyBridge:
2265     setFeatureEnabledImpl(Features, "avx", true);
2266     // FALLTHROUGH
2267   case CK_Westmere:
2268   case CK_Silvermont:
2269     setFeatureEnabledImpl(Features, "aes", true);
2270     setFeatureEnabledImpl(Features, "pclmul", true);
2271     // FALLTHROUGH
2272   case CK_Nehalem:
2273     setFeatureEnabledImpl(Features, "sse4.2", true);
2274     setFeatureEnabledImpl(Features, "cx16", true);
2275     break;
2276   case CK_KNL:
2277     setFeatureEnabledImpl(Features, "avx512f", true);
2278     setFeatureEnabledImpl(Features, "avx512cd", true);
2279     setFeatureEnabledImpl(Features, "avx512er", true);
2280     setFeatureEnabledImpl(Features, "avx512pf", true);
2281     setFeatureEnabledImpl(Features, "rdseed", true);
2282     setFeatureEnabledImpl(Features, "adx", true);
2283     setFeatureEnabledImpl(Features, "lzcnt", true);
2284     setFeatureEnabledImpl(Features, "bmi", true);
2285     setFeatureEnabledImpl(Features, "bmi2", true);
2286     setFeatureEnabledImpl(Features, "rtm", true);
2287     setFeatureEnabledImpl(Features, "fma", true);
2288     setFeatureEnabledImpl(Features, "rdrnd", true);
2289     setFeatureEnabledImpl(Features, "f16c", true);
2290     setFeatureEnabledImpl(Features, "fsgsbase", true);
2291     setFeatureEnabledImpl(Features, "aes", true);
2292     setFeatureEnabledImpl(Features, "pclmul", true);
2293     setFeatureEnabledImpl(Features, "cx16", true);
2294     break;
2295   case CK_K6_2:
2296   case CK_K6_3:
2297   case CK_WinChip2:
2298   case CK_C3:
2299     setFeatureEnabledImpl(Features, "3dnow", true);
2300     break;
2301   case CK_Athlon:
2302   case CK_AthlonThunderbird:
2303   case CK_Geode:
2304     setFeatureEnabledImpl(Features, "3dnowa", true);
2305     break;
2306   case CK_Athlon4:
2307   case CK_AthlonXP:
2308   case CK_AthlonMP:
2309     setFeatureEnabledImpl(Features, "sse", true);
2310     setFeatureEnabledImpl(Features, "3dnowa", true);
2311     break;
2312   case CK_K8:
2313   case CK_Opteron:
2314   case CK_Athlon64:
2315   case CK_AthlonFX:
2316     setFeatureEnabledImpl(Features, "sse2", true);
2317     setFeatureEnabledImpl(Features, "3dnowa", true);
2318     break;
2319   case CK_AMDFAM10:
2320     setFeatureEnabledImpl(Features, "sse4a", true);
2321     setFeatureEnabledImpl(Features, "lzcnt", true);
2322     setFeatureEnabledImpl(Features, "popcnt", true);
2323     // FALLTHROUGH
2324   case CK_K8SSE3:
2325   case CK_OpteronSSE3:
2326   case CK_Athlon64SSE3:
2327     setFeatureEnabledImpl(Features, "sse3", true);
2328     setFeatureEnabledImpl(Features, "3dnowa", true);
2329     break;
2330   case CK_BTVER2:
2331     setFeatureEnabledImpl(Features, "avx", true);
2332     setFeatureEnabledImpl(Features, "aes", true);
2333     setFeatureEnabledImpl(Features, "pclmul", true);
2334     setFeatureEnabledImpl(Features, "bmi", true);
2335     setFeatureEnabledImpl(Features, "f16c", true);
2336     // FALLTHROUGH
2337   case CK_BTVER1:
2338     setFeatureEnabledImpl(Features, "ssse3", true);
2339     setFeatureEnabledImpl(Features, "sse4a", true);
2340     setFeatureEnabledImpl(Features, "lzcnt", true);
2341     setFeatureEnabledImpl(Features, "popcnt", true);
2342     setFeatureEnabledImpl(Features, "prfchw", true);
2343     setFeatureEnabledImpl(Features, "cx16", true);
2344     break;
2345   case CK_BDVER4:
2346     setFeatureEnabledImpl(Features, "avx2", true);
2347     setFeatureEnabledImpl(Features, "bmi2", true);
2348     // FALLTHROUGH
2349   case CK_BDVER3:
2350     setFeatureEnabledImpl(Features, "fsgsbase", true);
2351     // FALLTHROUGH
2352   case CK_BDVER2:
2353     setFeatureEnabledImpl(Features, "bmi", true);
2354     setFeatureEnabledImpl(Features, "fma", true);
2355     setFeatureEnabledImpl(Features, "f16c", true);
2356     setFeatureEnabledImpl(Features, "tbm", true);
2357     // FALLTHROUGH
2358   case CK_BDVER1:
2359     // xop implies avx, sse4a and fma4.
2360     setFeatureEnabledImpl(Features, "xop", true);
2361     setFeatureEnabledImpl(Features, "lzcnt", true);
2362     setFeatureEnabledImpl(Features, "aes", true);
2363     setFeatureEnabledImpl(Features, "pclmul", true);
2364     setFeatureEnabledImpl(Features, "prfchw", true);
2365     setFeatureEnabledImpl(Features, "cx16", true);
2366     break;
2367   }
2368 }
2369 
2370 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2371                                 X86SSEEnum Level, bool Enabled) {
2372   if (Enabled) {
2373     switch (Level) {
2374     case AVX512F:
2375       Features["avx512f"] = true;
2376     case AVX2:
2377       Features["avx2"] = true;
2378     case AVX:
2379       Features["avx"] = true;
2380     case SSE42:
2381       Features["sse4.2"] = true;
2382     case SSE41:
2383       Features["sse4.1"] = true;
2384     case SSSE3:
2385       Features["ssse3"] = true;
2386     case SSE3:
2387       Features["sse3"] = true;
2388     case SSE2:
2389       Features["sse2"] = true;
2390     case SSE1:
2391       Features["sse"] = true;
2392     case NoSSE:
2393       break;
2394     }
2395     return;
2396   }
2397 
2398   switch (Level) {
2399   case NoSSE:
2400   case SSE1:
2401     Features["sse"] = false;
2402   case SSE2:
2403     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2404       Features["sha"] = false;
2405   case SSE3:
2406     Features["sse3"] = false;
2407     setXOPLevel(Features, NoXOP, false);
2408   case SSSE3:
2409     Features["ssse3"] = false;
2410   case SSE41:
2411     Features["sse4.1"] = false;
2412   case SSE42:
2413     Features["sse4.2"] = false;
2414   case AVX:
2415     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2416     setXOPLevel(Features, FMA4, false);
2417   case AVX2:
2418     Features["avx2"] = false;
2419   case AVX512F:
2420     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2421         Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2422             Features["avx512vl"] = false;
2423   }
2424 }
2425 
2426 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2427                                 MMX3DNowEnum Level, bool Enabled) {
2428   if (Enabled) {
2429     switch (Level) {
2430     case AMD3DNowAthlon:
2431       Features["3dnowa"] = true;
2432     case AMD3DNow:
2433       Features["3dnow"] = true;
2434     case MMX:
2435       Features["mmx"] = true;
2436     case NoMMX3DNow:
2437       break;
2438     }
2439     return;
2440   }
2441 
2442   switch (Level) {
2443   case NoMMX3DNow:
2444   case MMX:
2445     Features["mmx"] = false;
2446   case AMD3DNow:
2447     Features["3dnow"] = false;
2448   case AMD3DNowAthlon:
2449     Features["3dnowa"] = false;
2450   }
2451 }
2452 
2453 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2454                                 bool Enabled) {
2455   if (Enabled) {
2456     switch (Level) {
2457     case XOP:
2458       Features["xop"] = true;
2459     case FMA4:
2460       Features["fma4"] = true;
2461       setSSELevel(Features, AVX, true);
2462     case SSE4A:
2463       Features["sse4a"] = true;
2464       setSSELevel(Features, SSE3, true);
2465     case NoXOP:
2466       break;
2467     }
2468     return;
2469   }
2470 
2471   switch (Level) {
2472   case NoXOP:
2473   case SSE4A:
2474     Features["sse4a"] = false;
2475   case FMA4:
2476     Features["fma4"] = false;
2477   case XOP:
2478     Features["xop"] = false;
2479   }
2480 }
2481 
2482 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2483                                           StringRef Name, bool Enabled) {
2484   // FIXME: This *really* should not be here.  We need some way of translating
2485   // options into llvm subtarget features.
2486   if (Name == "sse4")
2487     Name = "sse4.2";
2488 
2489   Features[Name] = Enabled;
2490 
2491   if (Name == "mmx") {
2492     setMMXLevel(Features, MMX, Enabled);
2493   } else if (Name == "sse") {
2494     setSSELevel(Features, SSE1, Enabled);
2495   } else if (Name == "sse2") {
2496     setSSELevel(Features, SSE2, Enabled);
2497   } else if (Name == "sse3") {
2498     setSSELevel(Features, SSE3, Enabled);
2499   } else if (Name == "ssse3") {
2500     setSSELevel(Features, SSSE3, Enabled);
2501   } else if (Name == "sse4.2") {
2502     setSSELevel(Features, SSE42, Enabled);
2503   } else if (Name == "sse4.1") {
2504     setSSELevel(Features, SSE41, Enabled);
2505   } else if (Name == "3dnow") {
2506     setMMXLevel(Features, AMD3DNow, Enabled);
2507   } else if (Name == "3dnowa") {
2508     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2509   } else if (Name == "aes") {
2510     if (Enabled)
2511       setSSELevel(Features, SSE2, Enabled);
2512   } else if (Name == "pclmul") {
2513     if (Enabled)
2514       setSSELevel(Features, SSE2, Enabled);
2515   } else if (Name == "avx") {
2516     setSSELevel(Features, AVX, Enabled);
2517   } else if (Name == "avx2") {
2518     setSSELevel(Features, AVX2, Enabled);
2519   } else if (Name == "avx512f") {
2520     setSSELevel(Features, AVX512F, Enabled);
2521   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2522           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2523     if (Enabled)
2524       setSSELevel(Features, AVX512F, Enabled);
2525   } else if (Name == "fma") {
2526     if (Enabled)
2527       setSSELevel(Features, AVX, Enabled);
2528   } else if (Name == "fma4") {
2529     setXOPLevel(Features, FMA4, Enabled);
2530   } else if (Name == "xop") {
2531     setXOPLevel(Features, XOP, Enabled);
2532   } else if (Name == "sse4a") {
2533     setXOPLevel(Features, SSE4A, Enabled);
2534   } else if (Name == "f16c") {
2535     if (Enabled)
2536       setSSELevel(Features, AVX, Enabled);
2537   } else if (Name == "sha") {
2538     if (Enabled)
2539       setSSELevel(Features, SSE2, Enabled);
2540   }
2541 }
2542 
2543 /// handleTargetFeatures - Perform initialization based on the user
2544 /// configured set of features.
2545 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2546                                          DiagnosticsEngine &Diags) {
2547   // Remember the maximum enabled sselevel.
2548   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2549     // Ignore disabled features.
2550     if (Features[i][0] == '-')
2551       continue;
2552 
2553     StringRef Feature = StringRef(Features[i]).substr(1);
2554 
2555     if (Feature == "aes") {
2556       HasAES = true;
2557       continue;
2558     }
2559 
2560     if (Feature == "pclmul") {
2561       HasPCLMUL = true;
2562       continue;
2563     }
2564 
2565     if (Feature == "lzcnt") {
2566       HasLZCNT = true;
2567       continue;
2568     }
2569 
2570     if (Feature == "rdrnd") {
2571       HasRDRND = true;
2572       continue;
2573     }
2574 
2575     if (Feature == "fsgsbase") {
2576       HasFSGSBASE = true;
2577       continue;
2578     }
2579 
2580     if (Feature == "bmi") {
2581       HasBMI = true;
2582       continue;
2583     }
2584 
2585     if (Feature == "bmi2") {
2586       HasBMI2 = true;
2587       continue;
2588     }
2589 
2590     if (Feature == "popcnt") {
2591       HasPOPCNT = true;
2592       continue;
2593     }
2594 
2595     if (Feature == "rtm") {
2596       HasRTM = true;
2597       continue;
2598     }
2599 
2600     if (Feature == "prfchw") {
2601       HasPRFCHW = true;
2602       continue;
2603     }
2604 
2605     if (Feature == "rdseed") {
2606       HasRDSEED = true;
2607       continue;
2608     }
2609 
2610     if (Feature == "adx") {
2611       HasADX = true;
2612       continue;
2613     }
2614 
2615     if (Feature == "tbm") {
2616       HasTBM = true;
2617       continue;
2618     }
2619 
2620     if (Feature == "fma") {
2621       HasFMA = true;
2622       continue;
2623     }
2624 
2625     if (Feature == "f16c") {
2626       HasF16C = true;
2627       continue;
2628     }
2629 
2630     if (Feature == "avx512cd") {
2631       HasAVX512CD = true;
2632       continue;
2633     }
2634 
2635     if (Feature == "avx512er") {
2636       HasAVX512ER = true;
2637       continue;
2638     }
2639 
2640     if (Feature == "avx512pf") {
2641       HasAVX512PF = true;
2642       continue;
2643     }
2644 
2645     if (Feature == "avx512dq") {
2646       HasAVX512DQ = true;
2647       continue;
2648     }
2649 
2650     if (Feature == "avx512bw") {
2651       HasAVX512BW = true;
2652       continue;
2653     }
2654 
2655     if (Feature == "avx512vl") {
2656       HasAVX512VL = true;
2657       continue;
2658     }
2659 
2660     if (Feature == "sha") {
2661       HasSHA = true;
2662       continue;
2663     }
2664 
2665     if (Feature == "cx16") {
2666       HasCX16 = true;
2667       continue;
2668     }
2669 
2670     assert(Features[i][0] == '+' && "Invalid target feature!");
2671     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2672       .Case("avx512f", AVX512F)
2673       .Case("avx2", AVX2)
2674       .Case("avx", AVX)
2675       .Case("sse4.2", SSE42)
2676       .Case("sse4.1", SSE41)
2677       .Case("ssse3", SSSE3)
2678       .Case("sse3", SSE3)
2679       .Case("sse2", SSE2)
2680       .Case("sse", SSE1)
2681       .Default(NoSSE);
2682     SSELevel = std::max(SSELevel, Level);
2683 
2684     MMX3DNowEnum ThreeDNowLevel =
2685       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2686         .Case("3dnowa", AMD3DNowAthlon)
2687         .Case("3dnow", AMD3DNow)
2688         .Case("mmx", MMX)
2689         .Default(NoMMX3DNow);
2690     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2691 
2692     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2693         .Case("xop", XOP)
2694         .Case("fma4", FMA4)
2695         .Case("sse4a", SSE4A)
2696         .Default(NoXOP);
2697     XOPLevel = std::max(XOPLevel, XLevel);
2698   }
2699 
2700   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2701   // Can't do this earlier because we need to be able to explicitly enable
2702   // popcnt and still disable sse4.2.
2703   if (!HasPOPCNT && SSELevel >= SSE42 &&
2704       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2705     HasPOPCNT = true;
2706     Features.push_back("+popcnt");
2707   }
2708 
2709   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2710   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2711       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2712     HasPRFCHW = true;
2713     Features.push_back("+prfchw");
2714   }
2715 
2716   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2717   // matches the selected sse level.
2718   if (FPMath == FP_SSE && SSELevel < SSE1) {
2719     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2720     return false;
2721   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2722     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2723     return false;
2724   }
2725 
2726   // Don't tell the backend if we're turning off mmx; it will end up disabling
2727   // SSE, which we don't want.
2728   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2729   // then enable MMX.
2730   std::vector<std::string>::iterator it;
2731   it = std::find(Features.begin(), Features.end(), "-mmx");
2732   if (it != Features.end())
2733     Features.erase(it);
2734   else if (SSELevel > NoSSE)
2735     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2736   return true;
2737 }
2738 
2739 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2740 /// definitions for this particular subtarget.
2741 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2742                                      MacroBuilder &Builder) const {
2743   // Target identification.
2744   if (getTriple().getArch() == llvm::Triple::x86_64) {
2745     Builder.defineMacro("__amd64__");
2746     Builder.defineMacro("__amd64");
2747     Builder.defineMacro("__x86_64");
2748     Builder.defineMacro("__x86_64__");
2749     if (getTriple().getArchName() == "x86_64h") {
2750       Builder.defineMacro("__x86_64h");
2751       Builder.defineMacro("__x86_64h__");
2752     }
2753   } else {
2754     DefineStd(Builder, "i386", Opts);
2755   }
2756 
2757   // Subtarget options.
2758   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2759   // truly should be based on -mtune options.
2760   switch (CPU) {
2761   case CK_Generic:
2762     break;
2763   case CK_i386:
2764     // The rest are coming from the i386 define above.
2765     Builder.defineMacro("__tune_i386__");
2766     break;
2767   case CK_i486:
2768   case CK_WinChipC6:
2769   case CK_WinChip2:
2770   case CK_C3:
2771     defineCPUMacros(Builder, "i486");
2772     break;
2773   case CK_PentiumMMX:
2774     Builder.defineMacro("__pentium_mmx__");
2775     Builder.defineMacro("__tune_pentium_mmx__");
2776     // Fallthrough
2777   case CK_i586:
2778   case CK_Pentium:
2779     defineCPUMacros(Builder, "i586");
2780     defineCPUMacros(Builder, "pentium");
2781     break;
2782   case CK_Pentium3:
2783   case CK_Pentium3M:
2784   case CK_PentiumM:
2785     Builder.defineMacro("__tune_pentium3__");
2786     // Fallthrough
2787   case CK_Pentium2:
2788   case CK_C3_2:
2789     Builder.defineMacro("__tune_pentium2__");
2790     // Fallthrough
2791   case CK_PentiumPro:
2792     Builder.defineMacro("__tune_i686__");
2793     Builder.defineMacro("__tune_pentiumpro__");
2794     // Fallthrough
2795   case CK_i686:
2796     Builder.defineMacro("__i686");
2797     Builder.defineMacro("__i686__");
2798     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2799     Builder.defineMacro("__pentiumpro");
2800     Builder.defineMacro("__pentiumpro__");
2801     break;
2802   case CK_Pentium4:
2803   case CK_Pentium4M:
2804     defineCPUMacros(Builder, "pentium4");
2805     break;
2806   case CK_Yonah:
2807   case CK_Prescott:
2808   case CK_Nocona:
2809     defineCPUMacros(Builder, "nocona");
2810     break;
2811   case CK_Core2:
2812   case CK_Penryn:
2813     defineCPUMacros(Builder, "core2");
2814     break;
2815   case CK_Bonnell:
2816     defineCPUMacros(Builder, "atom");
2817     break;
2818   case CK_Silvermont:
2819     defineCPUMacros(Builder, "slm");
2820     break;
2821   case CK_Nehalem:
2822   case CK_Westmere:
2823   case CK_SandyBridge:
2824   case CK_IvyBridge:
2825   case CK_Haswell:
2826   case CK_Broadwell:
2827     // FIXME: Historically, we defined this legacy name, it would be nice to
2828     // remove it at some point. We've never exposed fine-grained names for
2829     // recent primary x86 CPUs, and we should keep it that way.
2830     defineCPUMacros(Builder, "corei7");
2831     break;
2832   case CK_Skylake:
2833     // FIXME: Historically, we defined this legacy name, it would be nice to
2834     // remove it at some point. This is the only fine-grained CPU macro in the
2835     // main intel CPU line, and it would be better to not have these and force
2836     // people to use ISA macros.
2837     defineCPUMacros(Builder, "skx");
2838     break;
2839   case CK_KNL:
2840     defineCPUMacros(Builder, "knl");
2841     break;
2842   case CK_K6_2:
2843     Builder.defineMacro("__k6_2__");
2844     Builder.defineMacro("__tune_k6_2__");
2845     // Fallthrough
2846   case CK_K6_3:
2847     if (CPU != CK_K6_2) {  // In case of fallthrough
2848       // FIXME: GCC may be enabling these in cases where some other k6
2849       // architecture is specified but -m3dnow is explicitly provided. The
2850       // exact semantics need to be determined and emulated here.
2851       Builder.defineMacro("__k6_3__");
2852       Builder.defineMacro("__tune_k6_3__");
2853     }
2854     // Fallthrough
2855   case CK_K6:
2856     defineCPUMacros(Builder, "k6");
2857     break;
2858   case CK_Athlon:
2859   case CK_AthlonThunderbird:
2860   case CK_Athlon4:
2861   case CK_AthlonXP:
2862   case CK_AthlonMP:
2863     defineCPUMacros(Builder, "athlon");
2864     if (SSELevel != NoSSE) {
2865       Builder.defineMacro("__athlon_sse__");
2866       Builder.defineMacro("__tune_athlon_sse__");
2867     }
2868     break;
2869   case CK_K8:
2870   case CK_K8SSE3:
2871   case CK_x86_64:
2872   case CK_Opteron:
2873   case CK_OpteronSSE3:
2874   case CK_Athlon64:
2875   case CK_Athlon64SSE3:
2876   case CK_AthlonFX:
2877     defineCPUMacros(Builder, "k8");
2878     break;
2879   case CK_AMDFAM10:
2880     defineCPUMacros(Builder, "amdfam10");
2881     break;
2882   case CK_BTVER1:
2883     defineCPUMacros(Builder, "btver1");
2884     break;
2885   case CK_BTVER2:
2886     defineCPUMacros(Builder, "btver2");
2887     break;
2888   case CK_BDVER1:
2889     defineCPUMacros(Builder, "bdver1");
2890     break;
2891   case CK_BDVER2:
2892     defineCPUMacros(Builder, "bdver2");
2893     break;
2894   case CK_BDVER3:
2895     defineCPUMacros(Builder, "bdver3");
2896     break;
2897   case CK_BDVER4:
2898     defineCPUMacros(Builder, "bdver4");
2899     break;
2900   case CK_Geode:
2901     defineCPUMacros(Builder, "geode");
2902     break;
2903   }
2904 
2905   // Target properties.
2906   Builder.defineMacro("__REGISTER_PREFIX__", "");
2907 
2908   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2909   // functions in glibc header files that use FP Stack inline asm which the
2910   // backend can't deal with (PR879).
2911   Builder.defineMacro("__NO_MATH_INLINES");
2912 
2913   if (HasAES)
2914     Builder.defineMacro("__AES__");
2915 
2916   if (HasPCLMUL)
2917     Builder.defineMacro("__PCLMUL__");
2918 
2919   if (HasLZCNT)
2920     Builder.defineMacro("__LZCNT__");
2921 
2922   if (HasRDRND)
2923     Builder.defineMacro("__RDRND__");
2924 
2925   if (HasFSGSBASE)
2926     Builder.defineMacro("__FSGSBASE__");
2927 
2928   if (HasBMI)
2929     Builder.defineMacro("__BMI__");
2930 
2931   if (HasBMI2)
2932     Builder.defineMacro("__BMI2__");
2933 
2934   if (HasPOPCNT)
2935     Builder.defineMacro("__POPCNT__");
2936 
2937   if (HasRTM)
2938     Builder.defineMacro("__RTM__");
2939 
2940   if (HasPRFCHW)
2941     Builder.defineMacro("__PRFCHW__");
2942 
2943   if (HasRDSEED)
2944     Builder.defineMacro("__RDSEED__");
2945 
2946   if (HasADX)
2947     Builder.defineMacro("__ADX__");
2948 
2949   if (HasTBM)
2950     Builder.defineMacro("__TBM__");
2951 
2952   switch (XOPLevel) {
2953   case XOP:
2954     Builder.defineMacro("__XOP__");
2955   case FMA4:
2956     Builder.defineMacro("__FMA4__");
2957   case SSE4A:
2958     Builder.defineMacro("__SSE4A__");
2959   case NoXOP:
2960     break;
2961   }
2962 
2963   if (HasFMA)
2964     Builder.defineMacro("__FMA__");
2965 
2966   if (HasF16C)
2967     Builder.defineMacro("__F16C__");
2968 
2969   if (HasAVX512CD)
2970     Builder.defineMacro("__AVX512CD__");
2971   if (HasAVX512ER)
2972     Builder.defineMacro("__AVX512ER__");
2973   if (HasAVX512PF)
2974     Builder.defineMacro("__AVX512PF__");
2975   if (HasAVX512DQ)
2976     Builder.defineMacro("__AVX512DQ__");
2977   if (HasAVX512BW)
2978     Builder.defineMacro("__AVX512BW__");
2979   if (HasAVX512VL)
2980     Builder.defineMacro("__AVX512VL__");
2981 
2982   if (HasSHA)
2983     Builder.defineMacro("__SHA__");
2984 
2985   if (HasCX16)
2986     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2987 
2988   // Each case falls through to the previous one here.
2989   switch (SSELevel) {
2990   case AVX512F:
2991     Builder.defineMacro("__AVX512F__");
2992   case AVX2:
2993     Builder.defineMacro("__AVX2__");
2994   case AVX:
2995     Builder.defineMacro("__AVX__");
2996   case SSE42:
2997     Builder.defineMacro("__SSE4_2__");
2998   case SSE41:
2999     Builder.defineMacro("__SSE4_1__");
3000   case SSSE3:
3001     Builder.defineMacro("__SSSE3__");
3002   case SSE3:
3003     Builder.defineMacro("__SSE3__");
3004   case SSE2:
3005     Builder.defineMacro("__SSE2__");
3006     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3007   case SSE1:
3008     Builder.defineMacro("__SSE__");
3009     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3010   case NoSSE:
3011     break;
3012   }
3013 
3014   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3015     switch (SSELevel) {
3016     case AVX512F:
3017     case AVX2:
3018     case AVX:
3019     case SSE42:
3020     case SSE41:
3021     case SSSE3:
3022     case SSE3:
3023     case SSE2:
3024       Builder.defineMacro("_M_IX86_FP", Twine(2));
3025       break;
3026     case SSE1:
3027       Builder.defineMacro("_M_IX86_FP", Twine(1));
3028       break;
3029     default:
3030       Builder.defineMacro("_M_IX86_FP", Twine(0));
3031     }
3032   }
3033 
3034   // Each case falls through to the previous one here.
3035   switch (MMX3DNowLevel) {
3036   case AMD3DNowAthlon:
3037     Builder.defineMacro("__3dNOW_A__");
3038   case AMD3DNow:
3039     Builder.defineMacro("__3dNOW__");
3040   case MMX:
3041     Builder.defineMacro("__MMX__");
3042   case NoMMX3DNow:
3043     break;
3044   }
3045 
3046   if (CPU >= CK_i486) {
3047     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3048     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3049     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3050   }
3051   if (CPU >= CK_i586)
3052     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3053 }
3054 
3055 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3056   return llvm::StringSwitch<bool>(Feature)
3057       .Case("aes", HasAES)
3058       .Case("avx", SSELevel >= AVX)
3059       .Case("avx2", SSELevel >= AVX2)
3060       .Case("avx512f", SSELevel >= AVX512F)
3061       .Case("avx512cd", HasAVX512CD)
3062       .Case("avx512er", HasAVX512ER)
3063       .Case("avx512pf", HasAVX512PF)
3064       .Case("avx512dq", HasAVX512DQ)
3065       .Case("avx512bw", HasAVX512BW)
3066       .Case("avx512vl", HasAVX512VL)
3067       .Case("bmi", HasBMI)
3068       .Case("bmi2", HasBMI2)
3069       .Case("cx16", HasCX16)
3070       .Case("f16c", HasF16C)
3071       .Case("fma", HasFMA)
3072       .Case("fma4", XOPLevel >= FMA4)
3073       .Case("fsgsbase", HasFSGSBASE)
3074       .Case("lzcnt", HasLZCNT)
3075       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3076       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3077       .Case("mmx", MMX3DNowLevel >= MMX)
3078       .Case("pclmul", HasPCLMUL)
3079       .Case("popcnt", HasPOPCNT)
3080       .Case("prfchw", HasPRFCHW)
3081       .Case("rdrnd", HasRDRND)
3082       .Case("rdseed", HasRDSEED)
3083       .Case("rtm", HasRTM)
3084       .Case("sha", HasSHA)
3085       .Case("sse", SSELevel >= SSE1)
3086       .Case("sse2", SSELevel >= SSE2)
3087       .Case("sse3", SSELevel >= SSE3)
3088       .Case("ssse3", SSELevel >= SSSE3)
3089       .Case("sse4.1", SSELevel >= SSE41)
3090       .Case("sse4.2", SSELevel >= SSE42)
3091       .Case("sse4a", XOPLevel >= SSE4A)
3092       .Case("tbm", HasTBM)
3093       .Case("x86", true)
3094       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3095       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3096       .Case("xop", XOPLevel >= XOP)
3097       .Default(false);
3098 }
3099 
3100 bool
3101 X86TargetInfo::validateAsmConstraint(const char *&Name,
3102                                      TargetInfo::ConstraintInfo &Info) const {
3103   switch (*Name) {
3104   default: return false;
3105   case 'Y': // first letter of a pair:
3106     switch (*(Name+1)) {
3107     default: return false;
3108     case '0':  // First SSE register.
3109     case 't':  // Any SSE register, when SSE2 is enabled.
3110     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3111     case 'm':  // any MMX register, when inter-unit moves enabled.
3112       break;   // falls through to setAllowsRegister.
3113   }
3114   case 'f': // any x87 floating point stack register.
3115     // Constraint 'f' cannot be used for output operands.
3116     if (Info.ConstraintStr[0] == '=')
3117       return false;
3118 
3119     Info.setAllowsRegister();
3120     return true;
3121   case 'a': // eax.
3122   case 'b': // ebx.
3123   case 'c': // ecx.
3124   case 'd': // edx.
3125   case 'S': // esi.
3126   case 'D': // edi.
3127   case 'A': // edx:eax.
3128   case 't': // top of floating point stack.
3129   case 'u': // second from top of floating point stack.
3130   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3131   case 'y': // Any MMX register.
3132   case 'x': // Any SSE register.
3133   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3134   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3135   case 'l': // "Index" registers: any general register that can be used as an
3136             // index in a base+index memory access.
3137     Info.setAllowsRegister();
3138     return true;
3139   case 'C': // SSE floating point constant.
3140   case 'G': // x87 floating point constant.
3141   case 'e': // 32-bit signed integer constant for use with zero-extending
3142             // x86_64 instructions.
3143   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3144             // x86_64 instructions.
3145     return true;
3146   }
3147 }
3148 
3149 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3150                                        unsigned Size) const {
3151   // Strip off constraint modifiers.
3152   while (Constraint[0] == '=' ||
3153          Constraint[0] == '+' ||
3154          Constraint[0] == '&')
3155     Constraint = Constraint.substr(1);
3156 
3157   return validateOperandSize(Constraint, Size);
3158 }
3159 
3160 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3161                                       unsigned Size) const {
3162   return validateOperandSize(Constraint, Size);
3163 }
3164 
3165 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3166                                         unsigned Size) const {
3167   switch (Constraint[0]) {
3168   default: break;
3169   case 'y':
3170     return Size <= 64;
3171   case 'f':
3172   case 't':
3173   case 'u':
3174     return Size <= 128;
3175   case 'x':
3176     // 256-bit ymm registers can be used if target supports AVX.
3177     return Size <= (SSELevel >= AVX ? 256U : 128U);
3178   }
3179 
3180   return true;
3181 }
3182 
3183 std::string
3184 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3185   switch (*Constraint) {
3186   case 'a': return std::string("{ax}");
3187   case 'b': return std::string("{bx}");
3188   case 'c': return std::string("{cx}");
3189   case 'd': return std::string("{dx}");
3190   case 'S': return std::string("{si}");
3191   case 'D': return std::string("{di}");
3192   case 'p': // address
3193     return std::string("im");
3194   case 't': // top of floating point stack.
3195     return std::string("{st}");
3196   case 'u': // second from top of floating point stack.
3197     return std::string("{st(1)}"); // second from top of floating point stack.
3198   default:
3199     return std::string(1, *Constraint);
3200   }
3201 }
3202 } // end anonymous namespace
3203 
3204 namespace {
3205 // X86-32 generic target
3206 class X86_32TargetInfo : public X86TargetInfo {
3207 public:
3208   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3209     DoubleAlign = LongLongAlign = 32;
3210     LongDoubleWidth = 96;
3211     LongDoubleAlign = 32;
3212     SuitableAlign = 128;
3213     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3214     SizeType = UnsignedInt;
3215     PtrDiffType = SignedInt;
3216     IntPtrType = SignedInt;
3217     RegParmMax = 3;
3218 
3219     // Use fpret for all types.
3220     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3221                              (1 << TargetInfo::Double) |
3222                              (1 << TargetInfo::LongDouble));
3223 
3224     // x86-32 has atomics up to 8 bytes
3225     // FIXME: Check that we actually have cmpxchg8b before setting
3226     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3227     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3228   }
3229   BuiltinVaListKind getBuiltinVaListKind() const override {
3230     return TargetInfo::CharPtrBuiltinVaList;
3231   }
3232 
3233   int getEHDataRegisterNumber(unsigned RegNo) const override {
3234     if (RegNo == 0) return 0;
3235     if (RegNo == 1) return 2;
3236     return -1;
3237   }
3238   bool validateOperandSize(StringRef Constraint,
3239                            unsigned Size) const override {
3240     switch (Constraint[0]) {
3241     default: break;
3242     case 'R':
3243     case 'q':
3244     case 'Q':
3245     case 'a':
3246     case 'b':
3247     case 'c':
3248     case 'd':
3249     case 'S':
3250     case 'D':
3251       return Size <= 32;
3252     case 'A':
3253       return Size <= 64;
3254     }
3255 
3256     return X86TargetInfo::validateOperandSize(Constraint, Size);
3257   }
3258 };
3259 } // end anonymous namespace
3260 
3261 namespace {
3262 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3263 public:
3264   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3265       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3266 
3267   unsigned getFloatEvalMethod() const override {
3268     unsigned Major, Minor, Micro;
3269     getTriple().getOSVersion(Major, Minor, Micro);
3270     // New NetBSD uses the default rounding mode.
3271     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3272       return X86_32TargetInfo::getFloatEvalMethod();
3273     // NetBSD before 6.99.26 defaults to "double" rounding.
3274     return 1;
3275   }
3276 };
3277 } // end anonymous namespace
3278 
3279 namespace {
3280 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3281 public:
3282   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3283       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3284     SizeType = UnsignedLong;
3285     IntPtrType = SignedLong;
3286     PtrDiffType = SignedLong;
3287   }
3288 };
3289 } // end anonymous namespace
3290 
3291 namespace {
3292 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3293 public:
3294   BitrigI386TargetInfo(const llvm::Triple &Triple)
3295       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3296     SizeType = UnsignedLong;
3297     IntPtrType = SignedLong;
3298     PtrDiffType = SignedLong;
3299   }
3300 };
3301 } // end anonymous namespace
3302 
3303 namespace {
3304 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3305 public:
3306   DarwinI386TargetInfo(const llvm::Triple &Triple)
3307       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3308     LongDoubleWidth = 128;
3309     LongDoubleAlign = 128;
3310     SuitableAlign = 128;
3311     MaxVectorAlign = 256;
3312     SizeType = UnsignedLong;
3313     IntPtrType = SignedLong;
3314     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3315     HasAlignMac68kSupport = true;
3316   }
3317 
3318 };
3319 } // end anonymous namespace
3320 
3321 namespace {
3322 // x86-32 Windows target
3323 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3324 public:
3325   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3326       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3327     WCharType = UnsignedShort;
3328     DoubleAlign = LongLongAlign = 64;
3329     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3330   }
3331   void getTargetDefines(const LangOptions &Opts,
3332                         MacroBuilder &Builder) const override {
3333     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3334   }
3335 };
3336 
3337 // x86-32 Windows Visual Studio target
3338 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3339 public:
3340   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3341       : WindowsX86_32TargetInfo(Triple) {
3342     LongDoubleWidth = LongDoubleAlign = 64;
3343     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3344   }
3345   void getTargetDefines(const LangOptions &Opts,
3346                         MacroBuilder &Builder) const override {
3347     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3348     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3349     // The value of the following reflects processor type.
3350     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3351     // We lost the original triple, so we use the default.
3352     Builder.defineMacro("_M_IX86", "600");
3353   }
3354 };
3355 } // end anonymous namespace
3356 
3357 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3358   Builder.defineMacro("__MSVCRT__");
3359   Builder.defineMacro("__MINGW32__");
3360 
3361   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3362   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3363   // macro anyway for pre-processor compatibility.
3364   if (Opts.MicrosoftExt)
3365     Builder.defineMacro("__declspec", "__declspec");
3366   else
3367     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3368 
3369   if (!Opts.MicrosoftExt) {
3370     // Provide macros for all the calling convention keywords.  Provide both
3371     // single and double underscore prefixed variants.  These are available on
3372     // x64 as well as x86, even though they have no effect.
3373     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3374     for (const char *CC : CCs) {
3375       std::string GCCSpelling = "__attribute__((__";
3376       GCCSpelling += CC;
3377       GCCSpelling += "__))";
3378       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3379       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3380     }
3381   }
3382 }
3383 
3384 namespace {
3385 // x86-32 MinGW target
3386 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3387 public:
3388   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3389       : WindowsX86_32TargetInfo(Triple) {}
3390   void getTargetDefines(const LangOptions &Opts,
3391                         MacroBuilder &Builder) const override {
3392     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3393     DefineStd(Builder, "WIN32", Opts);
3394     DefineStd(Builder, "WINNT", Opts);
3395     Builder.defineMacro("_X86_");
3396     addMinGWDefines(Opts, Builder);
3397   }
3398 };
3399 } // end anonymous namespace
3400 
3401 namespace {
3402 // x86-32 Cygwin target
3403 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3404 public:
3405   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3406       : X86_32TargetInfo(Triple) {
3407     TLSSupported = false;
3408     WCharType = UnsignedShort;
3409     DoubleAlign = LongLongAlign = 64;
3410     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3411   }
3412   void getTargetDefines(const LangOptions &Opts,
3413                         MacroBuilder &Builder) const override {
3414     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3415     Builder.defineMacro("_X86_");
3416     Builder.defineMacro("__CYGWIN__");
3417     Builder.defineMacro("__CYGWIN32__");
3418     DefineStd(Builder, "unix", Opts);
3419     if (Opts.CPlusPlus)
3420       Builder.defineMacro("_GNU_SOURCE");
3421   }
3422 };
3423 } // end anonymous namespace
3424 
3425 namespace {
3426 // x86-32 Haiku target
3427 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3428 public:
3429   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3430     SizeType = UnsignedLong;
3431     IntPtrType = SignedLong;
3432     PtrDiffType = SignedLong;
3433     ProcessIDType = SignedLong;
3434     this->UserLabelPrefix = "";
3435     this->TLSSupported = false;
3436   }
3437   void getTargetDefines(const LangOptions &Opts,
3438                         MacroBuilder &Builder) const override {
3439     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3440     Builder.defineMacro("__INTEL__");
3441     Builder.defineMacro("__HAIKU__");
3442   }
3443 };
3444 } // end anonymous namespace
3445 
3446 // RTEMS Target
3447 template<typename Target>
3448 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3449 protected:
3450   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3451                     MacroBuilder &Builder) const override {
3452     // RTEMS defines; list based off of gcc output
3453 
3454     Builder.defineMacro("__rtems__");
3455     Builder.defineMacro("__ELF__");
3456   }
3457 
3458 public:
3459   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3460     this->UserLabelPrefix = "";
3461 
3462     switch (Triple.getArch()) {
3463     default:
3464     case llvm::Triple::x86:
3465       // this->MCountName = ".mcount";
3466       break;
3467     case llvm::Triple::mips:
3468     case llvm::Triple::mipsel:
3469     case llvm::Triple::ppc:
3470     case llvm::Triple::ppc64:
3471     case llvm::Triple::ppc64le:
3472       // this->MCountName = "_mcount";
3473       break;
3474     case llvm::Triple::arm:
3475       // this->MCountName = "__mcount";
3476       break;
3477     }
3478   }
3479 };
3480 
3481 namespace {
3482 // x86-32 RTEMS target
3483 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3484 public:
3485   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3486     SizeType = UnsignedLong;
3487     IntPtrType = SignedLong;
3488     PtrDiffType = SignedLong;
3489     this->UserLabelPrefix = "";
3490   }
3491   void getTargetDefines(const LangOptions &Opts,
3492                         MacroBuilder &Builder) const override {
3493     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3494     Builder.defineMacro("__INTEL__");
3495     Builder.defineMacro("__rtems__");
3496   }
3497 };
3498 } // end anonymous namespace
3499 
3500 namespace {
3501 // x86-64 generic target
3502 class X86_64TargetInfo : public X86TargetInfo {
3503 public:
3504   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3505     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3506     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3507     LongDoubleWidth = 128;
3508     LongDoubleAlign = 128;
3509     LargeArrayMinWidth = 128;
3510     LargeArrayAlign = 128;
3511     SuitableAlign = 128;
3512     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3513     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3514     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3515     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3516     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3517     RegParmMax = 6;
3518 
3519     // Pointers are 32-bit in x32.
3520     DescriptionString = (IsX32)
3521                             ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3522                             : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3523 
3524     // Use fpret only for long double.
3525     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3526 
3527     // Use fp2ret for _Complex long double.
3528     ComplexLongDoubleUsesFP2Ret = true;
3529 
3530     // x86-64 has atomics up to 16 bytes.
3531     MaxAtomicPromoteWidth = 128;
3532     MaxAtomicInlineWidth = 128;
3533   }
3534   BuiltinVaListKind getBuiltinVaListKind() const override {
3535     return TargetInfo::X86_64ABIBuiltinVaList;
3536   }
3537 
3538   int getEHDataRegisterNumber(unsigned RegNo) const override {
3539     if (RegNo == 0) return 0;
3540     if (RegNo == 1) return 1;
3541     return -1;
3542   }
3543 
3544   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3545     return (CC == CC_C ||
3546             CC == CC_X86VectorCall ||
3547             CC == CC_IntelOclBicc ||
3548             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3549   }
3550 
3551   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3552     return CC_C;
3553   }
3554 
3555   // for x32 we need it here explicitly
3556   bool hasInt128Type() const override { return true; }
3557 };
3558 } // end anonymous namespace
3559 
3560 namespace {
3561 // x86-64 Windows target
3562 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3563 public:
3564   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3565       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3566     WCharType = UnsignedShort;
3567     LongWidth = LongAlign = 32;
3568     DoubleAlign = LongLongAlign = 64;
3569     IntMaxType = SignedLongLong;
3570     Int64Type = SignedLongLong;
3571     SizeType = UnsignedLongLong;
3572     PtrDiffType = SignedLongLong;
3573     IntPtrType = SignedLongLong;
3574     this->UserLabelPrefix = "";
3575   }
3576   void getTargetDefines(const LangOptions &Opts,
3577                                 MacroBuilder &Builder) const override {
3578     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3579     Builder.defineMacro("_WIN64");
3580   }
3581   BuiltinVaListKind getBuiltinVaListKind() const override {
3582     return TargetInfo::CharPtrBuiltinVaList;
3583   }
3584   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3585     return (CC == CC_C ||
3586             CC == CC_X86VectorCall ||
3587             CC == CC_IntelOclBicc ||
3588             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3589   }
3590 };
3591 } // end anonymous namespace
3592 
3593 namespace {
3594 // x86-64 Windows Visual Studio target
3595 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3596 public:
3597   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3598       : WindowsX86_64TargetInfo(Triple) {
3599     LongDoubleWidth = LongDoubleAlign = 64;
3600     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3601   }
3602   void getTargetDefines(const LangOptions &Opts,
3603                         MacroBuilder &Builder) const override {
3604     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3605     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3606     Builder.defineMacro("_M_X64");
3607     Builder.defineMacro("_M_AMD64");
3608   }
3609 };
3610 } // end anonymous namespace
3611 
3612 namespace {
3613 // x86-64 MinGW target
3614 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3615 public:
3616   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3617       : WindowsX86_64TargetInfo(Triple) {}
3618   void getTargetDefines(const LangOptions &Opts,
3619                         MacroBuilder &Builder) const override {
3620     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3621     DefineStd(Builder, "WIN64", Opts);
3622     Builder.defineMacro("__MINGW64__");
3623     addMinGWDefines(Opts, Builder);
3624 
3625     // GCC defines this macro when it is using __gxx_personality_seh0.
3626     if (!Opts.SjLjExceptions)
3627       Builder.defineMacro("__SEH__");
3628   }
3629 };
3630 } // end anonymous namespace
3631 
3632 namespace {
3633 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3634 public:
3635   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3636       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3637     Int64Type = SignedLongLong;
3638     MaxVectorAlign = 256;
3639     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3640     llvm::Triple T = llvm::Triple(Triple);
3641     if (T.isiOS())
3642       UseSignedCharForObjCBool = false;
3643     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3644   }
3645 };
3646 } // end anonymous namespace
3647 
3648 namespace {
3649 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3650 public:
3651   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3652       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3653     IntMaxType = SignedLongLong;
3654     Int64Type = SignedLongLong;
3655   }
3656 };
3657 } // end anonymous namespace
3658 
3659 namespace {
3660 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3661 public:
3662   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3663       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3664     IntMaxType = SignedLongLong;
3665     Int64Type = SignedLongLong;
3666   }
3667 };
3668 }
3669 
3670 
3671 namespace {
3672 class ARMTargetInfo : public TargetInfo {
3673   // Possible FPU choices.
3674   enum FPUMode {
3675     VFP2FPU = (1 << 0),
3676     VFP3FPU = (1 << 1),
3677     VFP4FPU = (1 << 2),
3678     NeonFPU = (1 << 3),
3679     FPARMV8 = (1 << 4)
3680   };
3681 
3682   // Possible HWDiv features.
3683   enum HWDivMode {
3684     HWDivThumb = (1 << 0),
3685     HWDivARM = (1 << 1)
3686   };
3687 
3688   static bool FPUModeIsVFP(FPUMode Mode) {
3689     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3690   }
3691 
3692   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3693   static const char * const GCCRegNames[];
3694 
3695   std::string ABI, CPU;
3696 
3697   enum {
3698     FP_Default,
3699     FP_VFP,
3700     FP_Neon
3701   } FPMath;
3702 
3703   unsigned FPU : 5;
3704 
3705   unsigned IsAAPCS : 1;
3706   unsigned IsThumb : 1;
3707   unsigned HWDiv : 2;
3708 
3709   // Initialized via features.
3710   unsigned SoftFloat : 1;
3711   unsigned SoftFloatABI : 1;
3712 
3713   unsigned CRC : 1;
3714   unsigned Crypto : 1;
3715 
3716   // ACLE 6.5.1 Hardware floating point
3717   enum {
3718     HW_FP_HP = (1 << 1), /// half (16-bit)
3719     HW_FP_SP = (1 << 2), /// single (32-bit)
3720     HW_FP_DP = (1 << 3), /// double (64-bit)
3721   };
3722   uint32_t HW_FP;
3723 
3724   static const Builtin::Info BuiltinInfo[];
3725 
3726   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3727     StringRef ArchName = T.getArchName();
3728     if (T.getArch() == llvm::Triple::arm ||
3729         T.getArch() == llvm::Triple::armeb) {
3730       StringRef VersionStr;
3731       if (ArchName.startswith("armv"))
3732         VersionStr = ArchName.substr(4, 1);
3733       else if (ArchName.startswith("armebv"))
3734         VersionStr = ArchName.substr(6, 1);
3735       else
3736         return false;
3737       unsigned Version;
3738       if (VersionStr.getAsInteger(10, Version))
3739         return false;
3740       return Version >= 6;
3741     }
3742     assert(T.getArch() == llvm::Triple::thumb ||
3743            T.getArch() == llvm::Triple::thumbeb);
3744     StringRef VersionStr;
3745     if (ArchName.startswith("thumbv"))
3746       VersionStr = ArchName.substr(6, 1);
3747     else if (ArchName.startswith("thumbebv"))
3748       VersionStr = ArchName.substr(8, 1);
3749     else
3750       return false;
3751     unsigned Version;
3752     if (VersionStr.getAsInteger(10, Version))
3753       return false;
3754     return Version >= 7;
3755   }
3756 
3757   void setABIAAPCS() {
3758     IsAAPCS = true;
3759 
3760     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3761     const llvm::Triple &T = getTriple();
3762 
3763     // size_t is unsigned long on MachO-derived environments and NetBSD.
3764     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3765       SizeType = UnsignedLong;
3766     else
3767       SizeType = UnsignedInt;
3768 
3769     switch (T.getOS()) {
3770     case llvm::Triple::NetBSD:
3771       WCharType = SignedInt;
3772       break;
3773     case llvm::Triple::Win32:
3774       WCharType = UnsignedShort;
3775       break;
3776     case llvm::Triple::Linux:
3777     default:
3778       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3779       WCharType = UnsignedInt;
3780       break;
3781     }
3782 
3783     UseBitFieldTypeAlignment = true;
3784 
3785     ZeroLengthBitfieldBoundary = 0;
3786 
3787     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3788     // so set preferred for small types to 32.
3789     if (T.isOSBinFormatMachO()) {
3790       DescriptionString =
3791           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3792                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3793     } else if (T.isOSWindows()) {
3794       // FIXME: this is invalid for WindowsCE
3795       assert(!BigEndian && "Windows on ARM does not support big endian");
3796       DescriptionString = "e"
3797                           "-m:e"
3798                           "-p:32:32"
3799                           "-i64:64"
3800                           "-v128:64:128"
3801                           "-a:0:32"
3802                           "-n32"
3803                           "-S64";
3804     } else {
3805       DescriptionString =
3806           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3807                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3808     }
3809 
3810     // FIXME: Enumerated types are variable width in straight AAPCS.
3811   }
3812 
3813   void setABIAPCS() {
3814     const llvm::Triple &T = getTriple();
3815 
3816     IsAAPCS = false;
3817 
3818     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3819 
3820     // size_t is unsigned int on FreeBSD.
3821     if (T.getOS() == llvm::Triple::FreeBSD)
3822       SizeType = UnsignedInt;
3823     else
3824       SizeType = UnsignedLong;
3825 
3826     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3827     WCharType = SignedInt;
3828 
3829     // Do not respect the alignment of bit-field types when laying out
3830     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3831     UseBitFieldTypeAlignment = false;
3832 
3833     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3834     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3835     /// gcc.
3836     ZeroLengthBitfieldBoundary = 32;
3837 
3838     if (T.isOSBinFormatMachO())
3839       DescriptionString =
3840           BigEndian
3841               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3842               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3843     else
3844       DescriptionString =
3845           BigEndian
3846               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3847               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3848 
3849     // FIXME: Override "preferred align" for double and long long.
3850   }
3851 
3852 public:
3853   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3854       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3855         IsAAPCS(true), HW_FP(0) {
3856     BigEndian = IsBigEndian;
3857 
3858     switch (getTriple().getOS()) {
3859     case llvm::Triple::NetBSD:
3860       PtrDiffType = SignedLong;
3861       break;
3862     default:
3863       PtrDiffType = SignedInt;
3864       break;
3865     }
3866 
3867     // {} in inline assembly are neon specifiers, not assembly variant
3868     // specifiers.
3869     NoAsmVariants = true;
3870 
3871     // FIXME: Should we just treat this as a feature?
3872     IsThumb = getTriple().getArchName().startswith("thumb");
3873 
3874     // FIXME: This duplicates code from the driver that sets the -target-abi
3875     // option - this code is used if -target-abi isn't passed and should
3876     // be unified in some way.
3877     if (Triple.isOSBinFormatMachO()) {
3878       // The backend is hardwired to assume AAPCS for M-class processors, ensure
3879       // the frontend matches that.
3880       if (Triple.getEnvironment() == llvm::Triple::EABI ||
3881           Triple.getOS() == llvm::Triple::UnknownOS ||
3882           StringRef(CPU).startswith("cortex-m")) {
3883         setABI("aapcs");
3884       } else {
3885         setABI("apcs-gnu");
3886       }
3887     } else if (Triple.isOSWindows()) {
3888       // FIXME: this is invalid for WindowsCE
3889       setABI("aapcs");
3890     } else {
3891       // Select the default based on the platform.
3892       switch (Triple.getEnvironment()) {
3893       case llvm::Triple::Android:
3894       case llvm::Triple::GNUEABI:
3895       case llvm::Triple::GNUEABIHF:
3896         setABI("aapcs-linux");
3897         break;
3898       case llvm::Triple::EABIHF:
3899       case llvm::Triple::EABI:
3900         setABI("aapcs");
3901         break;
3902       default:
3903         if (Triple.getOS() == llvm::Triple::NetBSD)
3904           setABI("apcs-gnu");
3905         else
3906           setABI("aapcs");
3907         break;
3908       }
3909     }
3910 
3911     // ARM targets default to using the ARM C++ ABI.
3912     TheCXXABI.set(TargetCXXABI::GenericARM);
3913 
3914     // ARM has atomics up to 8 bytes
3915     MaxAtomicPromoteWidth = 64;
3916     if (shouldUseInlineAtomic(getTriple()))
3917       MaxAtomicInlineWidth = 64;
3918 
3919     // Do force alignment of members that follow zero length bitfields.  If
3920     // the alignment of the zero-length bitfield is greater than the member
3921     // that follows it, `bar', `bar' will be aligned as the  type of the
3922     // zero length bitfield.
3923     UseZeroLengthBitfieldAlignment = true;
3924   }
3925   StringRef getABI() const override { return ABI; }
3926   bool setABI(const std::string &Name) override {
3927     ABI = Name;
3928 
3929     // The defaults (above) are for AAPCS, check if we need to change them.
3930     //
3931     // FIXME: We need support for -meabi... we could just mangle it into the
3932     // name.
3933     if (Name == "apcs-gnu") {
3934       setABIAPCS();
3935       return true;
3936     }
3937     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3938       setABIAAPCS();
3939       return true;
3940     }
3941     return false;
3942   }
3943 
3944   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3945     if (IsAAPCS)
3946       Features["aapcs"] = true;
3947     else
3948       Features["apcs"] = true;
3949 
3950     StringRef ArchName = getTriple().getArchName();
3951     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3952       Features["vfp2"] = true;
3953     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3954       Features["vfp3"] = true;
3955       Features["neon"] = true;
3956     }
3957     else if (CPU == "cortex-a5") {
3958       Features["vfp4"] = true;
3959       Features["neon"] = true;
3960     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3961                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3962                CPU == "cortex-a17" || CPU == "krait") {
3963       Features["vfp4"] = true;
3964       Features["neon"] = true;
3965       Features["hwdiv"] = true;
3966       Features["hwdiv-arm"] = true;
3967     } else if (CPU == "cyclone") {
3968       Features["v8fp"] = true;
3969       Features["neon"] = true;
3970       Features["hwdiv"] = true;
3971       Features["hwdiv-arm"] = true;
3972     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3973       Features["fp-armv8"] = true;
3974       Features["neon"] = true;
3975       Features["hwdiv"] = true;
3976       Features["hwdiv-arm"] = true;
3977       Features["crc"] = true;
3978       Features["crypto"] = true;
3979     } else if (CPU == "cortex-r5" ||
3980                // Enable the hwdiv extension for all v8a AArch32 cores by
3981                // default.
3982                ArchName == "armv8a" || ArchName == "armv8" ||
3983                ArchName == "armebv8a" || ArchName == "armebv8" ||
3984                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3985                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3986       Features["hwdiv"] = true;
3987       Features["hwdiv-arm"] = true;
3988     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
3989       Features["hwdiv"] = true;
3990     }
3991   }
3992 
3993   bool handleTargetFeatures(std::vector<std::string> &Features,
3994                             DiagnosticsEngine &Diags) override {
3995     FPU = 0;
3996     CRC = 0;
3997     Crypto = 0;
3998     SoftFloat = SoftFloatABI = false;
3999     HWDiv = 0;
4000 
4001     for (const auto &Feature : Features) {
4002       if (Feature == "+soft-float") {
4003         SoftFloat = true;
4004       } else if (Feature == "+soft-float-abi") {
4005         SoftFloatABI = true;
4006       } else if (Feature == "+vfp2") {
4007         FPU |= VFP2FPU;
4008         HW_FP = HW_FP_SP | HW_FP_DP;
4009       } else if (Feature == "+vfp3") {
4010         FPU |= VFP3FPU;
4011         HW_FP = HW_FP_SP | HW_FP_DP;
4012       } else if (Feature == "+vfp4") {
4013         FPU |= VFP4FPU;
4014         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4015       } else if (Feature == "+fp-armv8") {
4016         FPU |= FPARMV8;
4017         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4018       } else if (Feature == "+neon") {
4019         FPU |= NeonFPU;
4020         HW_FP = HW_FP_SP | HW_FP_DP;
4021       } else if (Feature == "+hwdiv") {
4022         HWDiv |= HWDivThumb;
4023       } else if (Feature == "+hwdiv-arm") {
4024         HWDiv |= HWDivARM;
4025       } else if (Feature == "+crc") {
4026         CRC = 1;
4027       } else if (Feature == "+crypto") {
4028         Crypto = 1;
4029       } else if (Feature == "+fp-only-sp") {
4030         HW_FP &= ~HW_FP_DP;
4031       }
4032     }
4033 
4034     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4035       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4036       return false;
4037     }
4038 
4039     if (FPMath == FP_Neon)
4040       Features.push_back("+neonfp");
4041     else if (FPMath == FP_VFP)
4042       Features.push_back("-neonfp");
4043 
4044     // Remove front-end specific options which the backend handles differently.
4045     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4046     for (const auto &FEFeature : FrontEndFeatures) {
4047       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4048       if (Feature != Features.end())
4049         Features.erase(Feature);
4050     }
4051 
4052     return true;
4053   }
4054 
4055   bool hasFeature(StringRef Feature) const override {
4056     return llvm::StringSwitch<bool>(Feature)
4057         .Case("arm", true)
4058         .Case("softfloat", SoftFloat)
4059         .Case("thumb", IsThumb)
4060         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4061         .Case("hwdiv", HWDiv & HWDivThumb)
4062         .Case("hwdiv-arm", HWDiv & HWDivARM)
4063         .Default(false);
4064   }
4065   // FIXME: Should we actually have some table instead of these switches?
4066   static const char *getCPUDefineSuffix(StringRef Name) {
4067     return llvm::StringSwitch<const char *>(Name)
4068         .Cases("arm8", "arm810", "4")
4069         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4070                "4")
4071         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4072         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4073         .Case("ep9312", "4T")
4074         .Cases("arm10tdmi", "arm1020t", "5T")
4075         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4076         .Case("arm926ej-s", "5TEJ")
4077         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4078         .Cases("xscale", "iwmmxt", "5TE")
4079         .Case("arm1136j-s", "6J")
4080         .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4081         .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4082         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4083         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4084         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4085                "7A")
4086         .Cases("cortex-r4", "cortex-r5", "7R")
4087         .Case("swift", "7S")
4088         .Case("cyclone", "8A")
4089         .Case("cortex-m3", "7M")
4090         .Cases("cortex-m4", "cortex-m7", "7EM")
4091         .Case("cortex-m0", "6M")
4092         .Cases("cortex-a53", "cortex-a57", "8A")
4093         .Default(nullptr);
4094   }
4095   static const char *getCPUProfile(StringRef Name) {
4096     return llvm::StringSwitch<const char *>(Name)
4097         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4098         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4099                "A")
4100         .Cases("cortex-a53", "cortex-a57", "A")
4101         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4102         .Cases("cortex-r4", "cortex-r5", "R")
4103         .Default("");
4104   }
4105   bool setCPU(const std::string &Name) override {
4106     if (!getCPUDefineSuffix(Name))
4107       return false;
4108 
4109     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4110     StringRef Profile = getCPUProfile(Name);
4111     if (Profile == "M" && MaxAtomicInlineWidth) {
4112       MaxAtomicPromoteWidth = 32;
4113       MaxAtomicInlineWidth = 32;
4114     }
4115 
4116     CPU = Name;
4117     return true;
4118   }
4119   bool setFPMath(StringRef Name) override;
4120   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4121                      unsigned CPUArchVer) const {
4122     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4123            (CPUArch.find('M') != StringRef::npos);
4124   }
4125   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4126                       unsigned CPUArchVer) const {
4127     // We check both CPUArchVer and ArchName because when only triple is
4128     // specified, the default CPU is arm1136j-s.
4129     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4130            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4131   }
4132   void getTargetDefines(const LangOptions &Opts,
4133                         MacroBuilder &Builder) const override {
4134     // Target identification.
4135     Builder.defineMacro("__arm");
4136     Builder.defineMacro("__arm__");
4137 
4138     // Target properties.
4139     Builder.defineMacro("__REGISTER_PREFIX__", "");
4140 
4141     StringRef CPUArch = getCPUDefineSuffix(CPU);
4142     unsigned int CPUArchVer;
4143     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4144       llvm_unreachable("Invalid char for architecture version number");
4145     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4146 
4147     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4148     StringRef CPUProfile = getCPUProfile(CPU);
4149     StringRef ArchName = getTriple().getArchName();
4150 
4151     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4152     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4153     if (CPUArch[0] >= '8') {
4154       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4155       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4156     }
4157 
4158     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4159     // is not defined for the M-profile.
4160     // NOTE that the deffault profile is assumed to be 'A'
4161     if (CPUProfile.empty() || CPUProfile != "M")
4162       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4163 
4164     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4165     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4166     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4167     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4168       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4169     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4170       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4171 
4172     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4173     // instruction set such as ARM or Thumb.
4174     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4175 
4176     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4177 
4178     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4179     if (!CPUProfile.empty())
4180       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4181 
4182     // ACLE 6.5.1 Hardware Floating Point
4183     if (HW_FP)
4184       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4185 
4186     // ACLE predefines.
4187     Builder.defineMacro("__ARM_ACLE", "200");
4188 
4189     // Subtarget options.
4190 
4191     // FIXME: It's more complicated than this and we don't really support
4192     // interworking.
4193     // Windows on ARM does not "support" interworking
4194     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4195       Builder.defineMacro("__THUMB_INTERWORK__");
4196 
4197     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4198       // Embedded targets on Darwin follow AAPCS, but not EABI.
4199       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4200       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4201         Builder.defineMacro("__ARM_EABI__");
4202       Builder.defineMacro("__ARM_PCS", "1");
4203 
4204       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4205         Builder.defineMacro("__ARM_PCS_VFP", "1");
4206     }
4207 
4208     if (SoftFloat)
4209       Builder.defineMacro("__SOFTFP__");
4210 
4211     if (CPU == "xscale")
4212       Builder.defineMacro("__XSCALE__");
4213 
4214     if (IsThumb) {
4215       Builder.defineMacro("__THUMBEL__");
4216       Builder.defineMacro("__thumb__");
4217       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4218         Builder.defineMacro("__thumb2__");
4219     }
4220     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4221       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4222 
4223     // Note, this is always on in gcc, even though it doesn't make sense.
4224     Builder.defineMacro("__APCS_32__");
4225 
4226     if (FPUModeIsVFP((FPUMode) FPU)) {
4227       Builder.defineMacro("__VFP_FP__");
4228       if (FPU & VFP2FPU)
4229         Builder.defineMacro("__ARM_VFPV2__");
4230       if (FPU & VFP3FPU)
4231         Builder.defineMacro("__ARM_VFPV3__");
4232       if (FPU & VFP4FPU)
4233         Builder.defineMacro("__ARM_VFPV4__");
4234     }
4235 
4236     // This only gets set when Neon instructions are actually available, unlike
4237     // the VFP define, hence the soft float and arch check. This is subtly
4238     // different from gcc, we follow the intent which was that it should be set
4239     // when Neon instructions are actually available.
4240     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4241       Builder.defineMacro("__ARM_NEON");
4242       Builder.defineMacro("__ARM_NEON__");
4243     }
4244 
4245     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4246                         Opts.ShortWChar ? "2" : "4");
4247 
4248     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4249                         Opts.ShortEnums ? "1" : "4");
4250 
4251     if (CRC)
4252       Builder.defineMacro("__ARM_FEATURE_CRC32");
4253 
4254     if (Crypto)
4255       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4256 
4257     if (CPUArchVer >= 6 && CPUArch != "6M") {
4258       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4259       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4260       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4261       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4262     }
4263 
4264     bool is5EOrAbove = (CPUArchVer >= 6 ||
4265                         (CPUArchVer == 5 &&
4266                          CPUArch.find('E') != StringRef::npos));
4267     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4268     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4269       Builder.defineMacro("__ARM_FEATURE_DSP");
4270   }
4271   void getTargetBuiltins(const Builtin::Info *&Records,
4272                          unsigned &NumRecords) const override {
4273     Records = BuiltinInfo;
4274     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4275   }
4276   bool isCLZForZeroUndef() const override { return false; }
4277   BuiltinVaListKind getBuiltinVaListKind() const override {
4278     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4279   }
4280   void getGCCRegNames(const char * const *&Names,
4281                       unsigned &NumNames) const override;
4282   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4283                         unsigned &NumAliases) const override;
4284   bool validateAsmConstraint(const char *&Name,
4285                              TargetInfo::ConstraintInfo &Info) const override {
4286     switch (*Name) {
4287     default: break;
4288     case 'l': // r0-r7
4289     case 'h': // r8-r15
4290     case 'w': // VFP Floating point register single precision
4291     case 'P': // VFP Floating point register double precision
4292       Info.setAllowsRegister();
4293       return true;
4294     case 'Q': // A memory address that is a single base register.
4295       Info.setAllowsMemory();
4296       return true;
4297     case 'U': // a memory reference...
4298       switch (Name[1]) {
4299       case 'q': // ...ARMV4 ldrsb
4300       case 'v': // ...VFP load/store (reg+constant offset)
4301       case 'y': // ...iWMMXt load/store
4302       case 't': // address valid for load/store opaque types wider
4303                 // than 128-bits
4304       case 'n': // valid address for Neon doubleword vector load/store
4305       case 'm': // valid address for Neon element and structure load/store
4306       case 's': // valid address for non-offset loads/stores of quad-word
4307                 // values in four ARM registers
4308         Info.setAllowsMemory();
4309         Name++;
4310         return true;
4311       }
4312     }
4313     return false;
4314   }
4315   std::string convertConstraint(const char *&Constraint) const override {
4316     std::string R;
4317     switch (*Constraint) {
4318     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4319       R = std::string("^") + std::string(Constraint, 2);
4320       Constraint++;
4321       break;
4322     case 'p': // 'p' should be translated to 'r' by default.
4323       R = std::string("r");
4324       break;
4325     default:
4326       return std::string(1, *Constraint);
4327     }
4328     return R;
4329   }
4330   bool
4331   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4332                              std::string &SuggestedModifier) const override {
4333     bool isOutput = (Constraint[0] == '=');
4334     bool isInOut = (Constraint[0] == '+');
4335 
4336     // Strip off constraint modifiers.
4337     while (Constraint[0] == '=' ||
4338            Constraint[0] == '+' ||
4339            Constraint[0] == '&')
4340       Constraint = Constraint.substr(1);
4341 
4342     switch (Constraint[0]) {
4343     default: break;
4344     case 'r': {
4345       switch (Modifier) {
4346       default:
4347         return (isInOut || isOutput || Size <= 64);
4348       case 'q':
4349         // A register of size 32 cannot fit a vector type.
4350         return false;
4351       }
4352     }
4353     }
4354 
4355     return true;
4356   }
4357   const char *getClobbers() const override {
4358     // FIXME: Is this really right?
4359     return "";
4360   }
4361 
4362   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4363     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4364   }
4365 
4366   int getEHDataRegisterNumber(unsigned RegNo) const override {
4367     if (RegNo == 0) return 0;
4368     if (RegNo == 1) return 1;
4369     return -1;
4370   }
4371 };
4372 
4373 bool ARMTargetInfo::setFPMath(StringRef Name) {
4374   if (Name == "neon") {
4375     FPMath = FP_Neon;
4376     return true;
4377   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4378              Name == "vfp4") {
4379     FPMath = FP_VFP;
4380     return true;
4381   }
4382   return false;
4383 }
4384 
4385 const char * const ARMTargetInfo::GCCRegNames[] = {
4386   // Integer registers
4387   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4388   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4389 
4390   // Float registers
4391   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4392   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4393   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4394   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4395 
4396   // Double registers
4397   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4398   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4399   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4400   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4401 
4402   // Quad registers
4403   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4404   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4405 };
4406 
4407 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4408                                    unsigned &NumNames) const {
4409   Names = GCCRegNames;
4410   NumNames = llvm::array_lengthof(GCCRegNames);
4411 }
4412 
4413 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4414   { { "a1" }, "r0" },
4415   { { "a2" }, "r1" },
4416   { { "a3" }, "r2" },
4417   { { "a4" }, "r3" },
4418   { { "v1" }, "r4" },
4419   { { "v2" }, "r5" },
4420   { { "v3" }, "r6" },
4421   { { "v4" }, "r7" },
4422   { { "v5" }, "r8" },
4423   { { "v6", "rfp" }, "r9" },
4424   { { "sl" }, "r10" },
4425   { { "fp" }, "r11" },
4426   { { "ip" }, "r12" },
4427   { { "r13" }, "sp" },
4428   { { "r14" }, "lr" },
4429   { { "r15" }, "pc" },
4430   // The S, D and Q registers overlap, but aren't really aliases; we
4431   // don't want to substitute one of these for a different-sized one.
4432 };
4433 
4434 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4435                                        unsigned &NumAliases) const {
4436   Aliases = GCCRegAliases;
4437   NumAliases = llvm::array_lengthof(GCCRegAliases);
4438 }
4439 
4440 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4441 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4442 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4443                                               ALL_LANGUAGES },
4444 #include "clang/Basic/BuiltinsNEON.def"
4445 
4446 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4447 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4448 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4449                                               ALL_LANGUAGES },
4450 #include "clang/Basic/BuiltinsARM.def"
4451 };
4452 
4453 class ARMleTargetInfo : public ARMTargetInfo {
4454 public:
4455   ARMleTargetInfo(const llvm::Triple &Triple)
4456     : ARMTargetInfo(Triple, false) { }
4457   virtual void getTargetDefines(const LangOptions &Opts,
4458                                 MacroBuilder &Builder) const {
4459     Builder.defineMacro("__ARMEL__");
4460     ARMTargetInfo::getTargetDefines(Opts, Builder);
4461   }
4462 };
4463 
4464 class ARMbeTargetInfo : public ARMTargetInfo {
4465 public:
4466   ARMbeTargetInfo(const llvm::Triple &Triple)
4467     : ARMTargetInfo(Triple, true) { }
4468   virtual void getTargetDefines(const LangOptions &Opts,
4469                                 MacroBuilder &Builder) const {
4470     Builder.defineMacro("__ARMEB__");
4471     Builder.defineMacro("__ARM_BIG_ENDIAN");
4472     ARMTargetInfo::getTargetDefines(Opts, Builder);
4473   }
4474 };
4475 } // end anonymous namespace.
4476 
4477 namespace {
4478 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4479   const llvm::Triple Triple;
4480 public:
4481   WindowsARMTargetInfo(const llvm::Triple &Triple)
4482     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4483     TLSSupported = false;
4484     WCharType = UnsignedShort;
4485     SizeType = UnsignedInt;
4486     UserLabelPrefix = "";
4487   }
4488   void getVisualStudioDefines(const LangOptions &Opts,
4489                               MacroBuilder &Builder) const {
4490     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4491 
4492     // FIXME: this is invalid for WindowsCE
4493     Builder.defineMacro("_M_ARM_NT", "1");
4494     Builder.defineMacro("_M_ARMT", "_M_ARM");
4495     Builder.defineMacro("_M_THUMB", "_M_ARM");
4496 
4497     assert((Triple.getArch() == llvm::Triple::arm ||
4498             Triple.getArch() == llvm::Triple::thumb) &&
4499            "invalid architecture for Windows ARM target info");
4500     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4501     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4502 
4503     // TODO map the complete set of values
4504     // 31: VFPv3 40: VFPv4
4505     Builder.defineMacro("_M_ARM_FP", "31");
4506   }
4507   BuiltinVaListKind getBuiltinVaListKind() const override {
4508     return TargetInfo::CharPtrBuiltinVaList;
4509   }
4510 };
4511 
4512 // Windows ARM + Itanium C++ ABI Target
4513 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4514 public:
4515   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4516     : WindowsARMTargetInfo(Triple) {
4517     TheCXXABI.set(TargetCXXABI::GenericARM);
4518   }
4519 
4520   void getTargetDefines(const LangOptions &Opts,
4521                         MacroBuilder &Builder) const override {
4522     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4523 
4524     if (Opts.MSVCCompat)
4525       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4526   }
4527 };
4528 
4529 // Windows ARM, MS (C++) ABI
4530 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4531 public:
4532   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4533     : WindowsARMTargetInfo(Triple) {
4534     TheCXXABI.set(TargetCXXABI::Microsoft);
4535   }
4536 
4537   void getTargetDefines(const LangOptions &Opts,
4538                         MacroBuilder &Builder) const override {
4539     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4540     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4541   }
4542 };
4543 }
4544 
4545 
4546 namespace {
4547 class DarwinARMTargetInfo :
4548   public DarwinTargetInfo<ARMleTargetInfo> {
4549 protected:
4550   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4551                     MacroBuilder &Builder) const override {
4552     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4553   }
4554 
4555 public:
4556   DarwinARMTargetInfo(const llvm::Triple &Triple)
4557       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4558     HasAlignMac68kSupport = true;
4559     // iOS always has 64-bit atomic instructions.
4560     // FIXME: This should be based off of the target features in
4561     // ARMleTargetInfo.
4562     MaxAtomicInlineWidth = 64;
4563 
4564     // Darwin on iOS uses a variant of the ARM C++ ABI.
4565     TheCXXABI.set(TargetCXXABI::iOS);
4566   }
4567 };
4568 } // end anonymous namespace.
4569 
4570 
4571 namespace {
4572 class AArch64TargetInfo : public TargetInfo {
4573   virtual void setDescriptionString() = 0;
4574   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4575   static const char *const GCCRegNames[];
4576 
4577   enum FPUModeEnum {
4578     FPUMode,
4579     NeonMode
4580   };
4581 
4582   unsigned FPU;
4583   unsigned CRC;
4584   unsigned Crypto;
4585 
4586   static const Builtin::Info BuiltinInfo[];
4587 
4588   std::string ABI;
4589 
4590 public:
4591   AArch64TargetInfo(const llvm::Triple &Triple)
4592       : TargetInfo(Triple), ABI("aapcs") {
4593 
4594     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4595       WCharType = SignedInt;
4596 
4597       // NetBSD apparently prefers consistency across ARM targets to consistency
4598       // across 64-bit targets.
4599       Int64Type = SignedLongLong;
4600       IntMaxType = SignedLongLong;
4601     } else {
4602       WCharType = UnsignedInt;
4603       Int64Type = SignedLong;
4604       IntMaxType = SignedLong;
4605     }
4606 
4607     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4608     MaxVectorAlign = 128;
4609     RegParmMax = 8;
4610     MaxAtomicInlineWidth = 128;
4611     MaxAtomicPromoteWidth = 128;
4612 
4613     LongDoubleWidth = LongDoubleAlign = 128;
4614     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4615 
4616     // {} in inline assembly are neon specifiers, not assembly variant
4617     // specifiers.
4618     NoAsmVariants = true;
4619 
4620     // AArch64 targets default to using the ARM C++ ABI.
4621     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4622   }
4623 
4624   StringRef getABI() const override { return ABI; }
4625   bool setABI(const std::string &Name) override {
4626     if (Name != "aapcs" && Name != "darwinpcs")
4627       return false;
4628 
4629     ABI = Name;
4630     return true;
4631   }
4632 
4633   bool setCPU(const std::string &Name) override {
4634     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4635                         .Case("generic", true)
4636                         .Cases("cortex-a53", "cortex-a57", true)
4637                         .Case("cyclone", true)
4638                         .Default(false);
4639     return CPUKnown;
4640   }
4641 
4642   virtual void getTargetDefines(const LangOptions &Opts,
4643                                 MacroBuilder &Builder) const  override {
4644     // Target identification.
4645     Builder.defineMacro("__aarch64__");
4646 
4647     // Target properties.
4648     Builder.defineMacro("_LP64");
4649     Builder.defineMacro("__LP64__");
4650 
4651     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4652     Builder.defineMacro("__ARM_ACLE", "200");
4653     Builder.defineMacro("__ARM_ARCH", "8");
4654     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4655 
4656     Builder.defineMacro("__ARM_64BIT_STATE");
4657     Builder.defineMacro("__ARM_PCS_AAPCS64");
4658     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4659 
4660     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4661     Builder.defineMacro("__ARM_FEATURE_CLZ");
4662     Builder.defineMacro("__ARM_FEATURE_FMA");
4663     Builder.defineMacro("__ARM_FEATURE_DIV");
4664     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4665     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4666     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4667     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4668 
4669     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4670 
4671     // 0xe implies support for half, single and double precision operations.
4672     Builder.defineMacro("__ARM_FP", "0xe");
4673 
4674     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4675     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4676     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4677 
4678     if (Opts.FastMath || Opts.FiniteMathOnly)
4679       Builder.defineMacro("__ARM_FP_FAST");
4680 
4681     if (Opts.C99 && !Opts.Freestanding)
4682       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4683 
4684     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4685 
4686     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4687                         Opts.ShortEnums ? "1" : "4");
4688 
4689     if (FPU == NeonMode) {
4690       Builder.defineMacro("__ARM_NEON");
4691       // 64-bit NEON supports half, single and double precision operations.
4692       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4693     }
4694 
4695     if (CRC)
4696       Builder.defineMacro("__ARM_FEATURE_CRC32");
4697 
4698     if (Crypto)
4699       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4700   }
4701 
4702   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4703                                  unsigned &NumRecords) const override {
4704     Records = BuiltinInfo;
4705     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4706   }
4707 
4708   bool hasFeature(StringRef Feature) const override {
4709     return Feature == "aarch64" ||
4710       Feature == "arm64" ||
4711       (Feature == "neon" && FPU == NeonMode);
4712   }
4713 
4714   bool handleTargetFeatures(std::vector<std::string> &Features,
4715                             DiagnosticsEngine &Diags) override {
4716     FPU = FPUMode;
4717     CRC = 0;
4718     Crypto = 0;
4719     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4720       if (Features[i] == "+neon")
4721         FPU = NeonMode;
4722       if (Features[i] == "+crc")
4723         CRC = 1;
4724       if (Features[i] == "+crypto")
4725         Crypto = 1;
4726     }
4727 
4728     setDescriptionString();
4729 
4730     return true;
4731   }
4732 
4733   bool isCLZForZeroUndef() const override { return false; }
4734 
4735   BuiltinVaListKind getBuiltinVaListKind() const override {
4736     return TargetInfo::AArch64ABIBuiltinVaList;
4737   }
4738 
4739   virtual void getGCCRegNames(const char *const *&Names,
4740                               unsigned &NumNames) const override;
4741   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4742                                 unsigned &NumAliases) const override;
4743 
4744   virtual bool
4745   validateAsmConstraint(const char *&Name,
4746                         TargetInfo::ConstraintInfo &Info) const override {
4747     switch (*Name) {
4748     default:
4749       return false;
4750     case 'w': // Floating point and SIMD registers (V0-V31)
4751       Info.setAllowsRegister();
4752       return true;
4753     case 'I': // Constant that can be used with an ADD instruction
4754     case 'J': // Constant that can be used with a SUB instruction
4755     case 'K': // Constant that can be used with a 32-bit logical instruction
4756     case 'L': // Constant that can be used with a 64-bit logical instruction
4757     case 'M': // Constant that can be used as a 32-bit MOV immediate
4758     case 'N': // Constant that can be used as a 64-bit MOV immediate
4759     case 'Y': // Floating point constant zero
4760     case 'Z': // Integer constant zero
4761       return true;
4762     case 'Q': // A memory reference with base register and no offset
4763       Info.setAllowsMemory();
4764       return true;
4765     case 'S': // A symbolic address
4766       Info.setAllowsRegister();
4767       return true;
4768     case 'U':
4769       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4770       // Utf: A memory address suitable for ldp/stp in TF mode.
4771       // Usa: An absolute symbolic address.
4772       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4773       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4774     case 'z': // Zero register, wzr or xzr
4775       Info.setAllowsRegister();
4776       return true;
4777     case 'x': // Floating point and SIMD registers (V0-V15)
4778       Info.setAllowsRegister();
4779       return true;
4780     }
4781     return false;
4782   }
4783 
4784   bool
4785   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4786                              std::string &SuggestedModifier) const override {
4787     // Strip off constraint modifiers.
4788     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4789       Constraint = Constraint.substr(1);
4790 
4791     switch (Constraint[0]) {
4792     default:
4793       return true;
4794     case 'z':
4795     case 'r': {
4796       switch (Modifier) {
4797       case 'x':
4798       case 'w':
4799         // For now assume that the person knows what they're
4800         // doing with the modifier.
4801         return true;
4802       default:
4803         // By default an 'r' constraint will be in the 'x'
4804         // registers.
4805         if (Size == 64)
4806           return true;
4807 
4808         SuggestedModifier = "w";
4809         return false;
4810       }
4811     }
4812     }
4813   }
4814 
4815   const char *getClobbers() const override { return ""; }
4816 
4817   int getEHDataRegisterNumber(unsigned RegNo) const override {
4818     if (RegNo == 0)
4819       return 0;
4820     if (RegNo == 1)
4821       return 1;
4822     return -1;
4823   }
4824 };
4825 
4826 const char *const AArch64TargetInfo::GCCRegNames[] = {
4827   // 32-bit Integer registers
4828   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4829   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4830   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4831 
4832   // 64-bit Integer registers
4833   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4834   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4835   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4836 
4837   // 32-bit floating point regsisters
4838   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4839   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4840   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4841 
4842   // 64-bit floating point regsisters
4843   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4844   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4845   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4846 
4847   // Vector registers
4848   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4849   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4850   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4851 };
4852 
4853 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4854                                      unsigned &NumNames) const {
4855   Names = GCCRegNames;
4856   NumNames = llvm::array_lengthof(GCCRegNames);
4857 }
4858 
4859 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4860   { { "w31" }, "wsp" },
4861   { { "x29" }, "fp" },
4862   { { "x30" }, "lr" },
4863   { { "x31" }, "sp" },
4864   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4865   // don't want to substitute one of these for a different-sized one.
4866 };
4867 
4868 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4869                                        unsigned &NumAliases) const {
4870   Aliases = GCCRegAliases;
4871   NumAliases = llvm::array_lengthof(GCCRegAliases);
4872 }
4873 
4874 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4875 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4876   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4877 #include "clang/Basic/BuiltinsNEON.def"
4878 
4879 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4880   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4881 #include "clang/Basic/BuiltinsAArch64.def"
4882 };
4883 
4884 class AArch64leTargetInfo : public AArch64TargetInfo {
4885   void setDescriptionString() override {
4886     if (getTriple().isOSBinFormatMachO())
4887       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4888     else
4889       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4890   }
4891 
4892 public:
4893   AArch64leTargetInfo(const llvm::Triple &Triple)
4894     : AArch64TargetInfo(Triple) {
4895     BigEndian = false;
4896     }
4897   void getTargetDefines(const LangOptions &Opts,
4898                         MacroBuilder &Builder) const override {
4899     Builder.defineMacro("__AARCH64EL__");
4900     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4901   }
4902 };
4903 
4904 class AArch64beTargetInfo : public AArch64TargetInfo {
4905   void setDescriptionString() override {
4906     assert(!getTriple().isOSBinFormatMachO());
4907     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4908   }
4909 
4910 public:
4911   AArch64beTargetInfo(const llvm::Triple &Triple)
4912     : AArch64TargetInfo(Triple) { }
4913   void getTargetDefines(const LangOptions &Opts,
4914                         MacroBuilder &Builder) const override {
4915     Builder.defineMacro("__AARCH64EB__");
4916     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4917     Builder.defineMacro("__ARM_BIG_ENDIAN");
4918     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4919   }
4920 };
4921 } // end anonymous namespace.
4922 
4923 namespace {
4924 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4925 protected:
4926   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4927                     MacroBuilder &Builder) const override {
4928     Builder.defineMacro("__AARCH64_SIMD__");
4929     Builder.defineMacro("__ARM64_ARCH_8__");
4930     Builder.defineMacro("__ARM_NEON__");
4931     Builder.defineMacro("__LITTLE_ENDIAN__");
4932     Builder.defineMacro("__REGISTER_PREFIX__", "");
4933     Builder.defineMacro("__arm64", "1");
4934     Builder.defineMacro("__arm64__", "1");
4935 
4936     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4937   }
4938 
4939 public:
4940   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4941       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4942     Int64Type = SignedLongLong;
4943     WCharType = SignedInt;
4944     UseSignedCharForObjCBool = false;
4945 
4946     LongDoubleWidth = LongDoubleAlign = 64;
4947     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4948 
4949     TheCXXABI.set(TargetCXXABI::iOS64);
4950   }
4951 
4952   BuiltinVaListKind getBuiltinVaListKind() const override {
4953     return TargetInfo::CharPtrBuiltinVaList;
4954   }
4955 };
4956 } // end anonymous namespace
4957 
4958 namespace {
4959 // Hexagon abstract base class
4960 class HexagonTargetInfo : public TargetInfo {
4961   static const Builtin::Info BuiltinInfo[];
4962   static const char * const GCCRegNames[];
4963   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4964   std::string CPU;
4965 public:
4966   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4967     BigEndian = false;
4968     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4969 
4970     // {} in inline assembly are packet specifiers, not assembly variant
4971     // specifiers.
4972     NoAsmVariants = true;
4973   }
4974 
4975   void getTargetBuiltins(const Builtin::Info *&Records,
4976                          unsigned &NumRecords) const override {
4977     Records = BuiltinInfo;
4978     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4979   }
4980 
4981   bool validateAsmConstraint(const char *&Name,
4982                              TargetInfo::ConstraintInfo &Info) const override {
4983     return true;
4984   }
4985 
4986   void getTargetDefines(const LangOptions &Opts,
4987                         MacroBuilder &Builder) const override;
4988 
4989   bool hasFeature(StringRef Feature) const override {
4990     return Feature == "hexagon";
4991   }
4992 
4993   BuiltinVaListKind getBuiltinVaListKind() const override {
4994     return TargetInfo::CharPtrBuiltinVaList;
4995   }
4996   void getGCCRegNames(const char * const *&Names,
4997                       unsigned &NumNames) const override;
4998   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4999                         unsigned &NumAliases) const override;
5000   const char *getClobbers() const override {
5001     return "";
5002   }
5003 
5004   static const char *getHexagonCPUSuffix(StringRef Name) {
5005     return llvm::StringSwitch<const char*>(Name)
5006       .Case("hexagonv4", "4")
5007       .Case("hexagonv5", "5")
5008       .Default(nullptr);
5009   }
5010 
5011   bool setCPU(const std::string &Name) override {
5012     if (!getHexagonCPUSuffix(Name))
5013       return false;
5014 
5015     CPU = Name;
5016     return true;
5017   }
5018 };
5019 
5020 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5021                                 MacroBuilder &Builder) const {
5022   Builder.defineMacro("qdsp6");
5023   Builder.defineMacro("__qdsp6", "1");
5024   Builder.defineMacro("__qdsp6__", "1");
5025 
5026   Builder.defineMacro("hexagon");
5027   Builder.defineMacro("__hexagon", "1");
5028   Builder.defineMacro("__hexagon__", "1");
5029 
5030   if(CPU == "hexagonv1") {
5031     Builder.defineMacro("__HEXAGON_V1__");
5032     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5033     if(Opts.HexagonQdsp6Compat) {
5034       Builder.defineMacro("__QDSP6_V1__");
5035       Builder.defineMacro("__QDSP6_ARCH__", "1");
5036     }
5037   }
5038   else if(CPU == "hexagonv2") {
5039     Builder.defineMacro("__HEXAGON_V2__");
5040     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5041     if(Opts.HexagonQdsp6Compat) {
5042       Builder.defineMacro("__QDSP6_V2__");
5043       Builder.defineMacro("__QDSP6_ARCH__", "2");
5044     }
5045   }
5046   else if(CPU == "hexagonv3") {
5047     Builder.defineMacro("__HEXAGON_V3__");
5048     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5049     if(Opts.HexagonQdsp6Compat) {
5050       Builder.defineMacro("__QDSP6_V3__");
5051       Builder.defineMacro("__QDSP6_ARCH__", "3");
5052     }
5053   }
5054   else if(CPU == "hexagonv4") {
5055     Builder.defineMacro("__HEXAGON_V4__");
5056     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5057     if(Opts.HexagonQdsp6Compat) {
5058       Builder.defineMacro("__QDSP6_V4__");
5059       Builder.defineMacro("__QDSP6_ARCH__", "4");
5060     }
5061   }
5062   else if(CPU == "hexagonv5") {
5063     Builder.defineMacro("__HEXAGON_V5__");
5064     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5065     if(Opts.HexagonQdsp6Compat) {
5066       Builder.defineMacro("__QDSP6_V5__");
5067       Builder.defineMacro("__QDSP6_ARCH__", "5");
5068     }
5069   }
5070 }
5071 
5072 const char * const HexagonTargetInfo::GCCRegNames[] = {
5073   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5074   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5075   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5076   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5077   "p0", "p1", "p2", "p3",
5078   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5079 };
5080 
5081 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5082                                    unsigned &NumNames) const {
5083   Names = GCCRegNames;
5084   NumNames = llvm::array_lengthof(GCCRegNames);
5085 }
5086 
5087 
5088 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5089   { { "sp" }, "r29" },
5090   { { "fp" }, "r30" },
5091   { { "lr" }, "r31" },
5092  };
5093 
5094 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5095                                      unsigned &NumAliases) const {
5096   Aliases = GCCRegAliases;
5097   NumAliases = llvm::array_lengthof(GCCRegAliases);
5098 }
5099 
5100 
5101 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5102 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5103 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5104                                               ALL_LANGUAGES },
5105 #include "clang/Basic/BuiltinsHexagon.def"
5106 };
5107 }
5108 
5109 
5110 namespace {
5111 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5112 class SparcTargetInfo : public TargetInfo {
5113   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5114   static const char * const GCCRegNames[];
5115   bool SoftFloat;
5116 public:
5117   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5118 
5119   bool handleTargetFeatures(std::vector<std::string> &Features,
5120                             DiagnosticsEngine &Diags) override {
5121     SoftFloat = false;
5122     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5123       if (Features[i] == "+soft-float")
5124         SoftFloat = true;
5125     return true;
5126   }
5127   void getTargetDefines(const LangOptions &Opts,
5128                         MacroBuilder &Builder) const override {
5129     DefineStd(Builder, "sparc", Opts);
5130     Builder.defineMacro("__REGISTER_PREFIX__", "");
5131 
5132     if (SoftFloat)
5133       Builder.defineMacro("SOFT_FLOAT", "1");
5134   }
5135 
5136   bool hasFeature(StringRef Feature) const override {
5137     return llvm::StringSwitch<bool>(Feature)
5138              .Case("softfloat", SoftFloat)
5139              .Case("sparc", true)
5140              .Default(false);
5141   }
5142 
5143   void getTargetBuiltins(const Builtin::Info *&Records,
5144                          unsigned &NumRecords) const override {
5145     // FIXME: Implement!
5146   }
5147   BuiltinVaListKind getBuiltinVaListKind() const override {
5148     return TargetInfo::VoidPtrBuiltinVaList;
5149   }
5150   void getGCCRegNames(const char * const *&Names,
5151                       unsigned &NumNames) const override;
5152   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5153                         unsigned &NumAliases) const override;
5154   bool validateAsmConstraint(const char *&Name,
5155                              TargetInfo::ConstraintInfo &info) const override {
5156     // FIXME: Implement!
5157     return false;
5158   }
5159   const char *getClobbers() const override {
5160     // FIXME: Implement!
5161     return "";
5162   }
5163 };
5164 
5165 const char * const SparcTargetInfo::GCCRegNames[] = {
5166   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5167   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5168   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5169   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5170 };
5171 
5172 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5173                                      unsigned &NumNames) const {
5174   Names = GCCRegNames;
5175   NumNames = llvm::array_lengthof(GCCRegNames);
5176 }
5177 
5178 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5179   { { "g0" }, "r0" },
5180   { { "g1" }, "r1" },
5181   { { "g2" }, "r2" },
5182   { { "g3" }, "r3" },
5183   { { "g4" }, "r4" },
5184   { { "g5" }, "r5" },
5185   { { "g6" }, "r6" },
5186   { { "g7" }, "r7" },
5187   { { "o0" }, "r8" },
5188   { { "o1" }, "r9" },
5189   { { "o2" }, "r10" },
5190   { { "o3" }, "r11" },
5191   { { "o4" }, "r12" },
5192   { { "o5" }, "r13" },
5193   { { "o6", "sp" }, "r14" },
5194   { { "o7" }, "r15" },
5195   { { "l0" }, "r16" },
5196   { { "l1" }, "r17" },
5197   { { "l2" }, "r18" },
5198   { { "l3" }, "r19" },
5199   { { "l4" }, "r20" },
5200   { { "l5" }, "r21" },
5201   { { "l6" }, "r22" },
5202   { { "l7" }, "r23" },
5203   { { "i0" }, "r24" },
5204   { { "i1" }, "r25" },
5205   { { "i2" }, "r26" },
5206   { { "i3" }, "r27" },
5207   { { "i4" }, "r28" },
5208   { { "i5" }, "r29" },
5209   { { "i6", "fp" }, "r30" },
5210   { { "i7" }, "r31" },
5211 };
5212 
5213 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5214                                        unsigned &NumAliases) const {
5215   Aliases = GCCRegAliases;
5216   NumAliases = llvm::array_lengthof(GCCRegAliases);
5217 }
5218 
5219 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5220 class SparcV8TargetInfo : public SparcTargetInfo {
5221 public:
5222   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5223     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5224   }
5225 
5226   void getTargetDefines(const LangOptions &Opts,
5227                         MacroBuilder &Builder) const override {
5228     SparcTargetInfo::getTargetDefines(Opts, Builder);
5229     Builder.defineMacro("__sparcv8");
5230   }
5231 };
5232 
5233 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5234 class SparcV9TargetInfo : public SparcTargetInfo {
5235 public:
5236   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5237     // FIXME: Support Sparc quad-precision long double?
5238     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5239     // This is an LP64 platform.
5240     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5241 
5242     // OpenBSD uses long long for int64_t and intmax_t.
5243     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5244       IntMaxType = SignedLongLong;
5245     else
5246       IntMaxType = SignedLong;
5247     Int64Type = IntMaxType;
5248 
5249     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5250     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5251     LongDoubleWidth = 128;
5252     LongDoubleAlign = 128;
5253     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5254     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5255   }
5256 
5257   void getTargetDefines(const LangOptions &Opts,
5258                         MacroBuilder &Builder) const override {
5259     SparcTargetInfo::getTargetDefines(Opts, Builder);
5260     Builder.defineMacro("__sparcv9");
5261     Builder.defineMacro("__arch64__");
5262     // Solaris doesn't need these variants, but the BSDs do.
5263     if (getTriple().getOS() != llvm::Triple::Solaris) {
5264       Builder.defineMacro("__sparc64__");
5265       Builder.defineMacro("__sparc_v9__");
5266       Builder.defineMacro("__sparcv9__");
5267     }
5268   }
5269 
5270   bool setCPU(const std::string &Name) override {
5271     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5272       .Case("v9", true)
5273       .Case("ultrasparc", true)
5274       .Case("ultrasparc3", true)
5275       .Case("niagara", true)
5276       .Case("niagara2", true)
5277       .Case("niagara3", true)
5278       .Case("niagara4", true)
5279       .Default(false);
5280 
5281     // No need to store the CPU yet.  There aren't any CPU-specific
5282     // macros to define.
5283     return CPUKnown;
5284   }
5285 };
5286 
5287 } // end anonymous namespace.
5288 
5289 namespace {
5290 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5291 public:
5292   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5293       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5294     SizeType = UnsignedInt;
5295     PtrDiffType = SignedInt;
5296   }
5297 };
5298 } // end anonymous namespace.
5299 
5300 namespace {
5301 class SystemZTargetInfo : public TargetInfo {
5302   static const char *const GCCRegNames[];
5303 
5304 public:
5305   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5306     TLSSupported = true;
5307     IntWidth = IntAlign = 32;
5308     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5309     PointerWidth = PointerAlign = 64;
5310     LongDoubleWidth = 128;
5311     LongDoubleAlign = 64;
5312     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5313     MinGlobalAlign = 16;
5314     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5315     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5316   }
5317   void getTargetDefines(const LangOptions &Opts,
5318                         MacroBuilder &Builder) const override {
5319     Builder.defineMacro("__s390__");
5320     Builder.defineMacro("__s390x__");
5321     Builder.defineMacro("__zarch__");
5322     Builder.defineMacro("__LONG_DOUBLE_128__");
5323   }
5324   void getTargetBuiltins(const Builtin::Info *&Records,
5325                          unsigned &NumRecords) const override {
5326     // FIXME: Implement.
5327     Records = nullptr;
5328     NumRecords = 0;
5329   }
5330 
5331   void getGCCRegNames(const char *const *&Names,
5332                       unsigned &NumNames) const override;
5333   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5334                         unsigned &NumAliases) const override {
5335     // No aliases.
5336     Aliases = nullptr;
5337     NumAliases = 0;
5338   }
5339   bool validateAsmConstraint(const char *&Name,
5340                              TargetInfo::ConstraintInfo &info) const override;
5341   const char *getClobbers() const override {
5342     // FIXME: Is this really right?
5343     return "";
5344   }
5345   BuiltinVaListKind getBuiltinVaListKind() const override {
5346     return TargetInfo::SystemZBuiltinVaList;
5347   }
5348   bool setCPU(const std::string &Name) override {
5349     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5350       .Case("z10", true)
5351       .Case("z196", true)
5352       .Case("zEC12", true)
5353       .Default(false);
5354 
5355     // No need to store the CPU yet.  There aren't any CPU-specific
5356     // macros to define.
5357     return CPUKnown;
5358   }
5359 };
5360 
5361 const char *const SystemZTargetInfo::GCCRegNames[] = {
5362   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5363   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5364   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5365   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5366 };
5367 
5368 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5369                                        unsigned &NumNames) const {
5370   Names = GCCRegNames;
5371   NumNames = llvm::array_lengthof(GCCRegNames);
5372 }
5373 
5374 bool SystemZTargetInfo::
5375 validateAsmConstraint(const char *&Name,
5376                       TargetInfo::ConstraintInfo &Info) const {
5377   switch (*Name) {
5378   default:
5379     return false;
5380 
5381   case 'a': // Address register
5382   case 'd': // Data register (equivalent to 'r')
5383   case 'f': // Floating-point register
5384     Info.setAllowsRegister();
5385     return true;
5386 
5387   case 'I': // Unsigned 8-bit constant
5388   case 'J': // Unsigned 12-bit constant
5389   case 'K': // Signed 16-bit constant
5390   case 'L': // Signed 20-bit displacement (on all targets we support)
5391   case 'M': // 0x7fffffff
5392     return true;
5393 
5394   case 'Q': // Memory with base and unsigned 12-bit displacement
5395   case 'R': // Likewise, plus an index
5396   case 'S': // Memory with base and signed 20-bit displacement
5397   case 'T': // Likewise, plus an index
5398     Info.setAllowsMemory();
5399     return true;
5400   }
5401 }
5402 }
5403 
5404 namespace {
5405   class MSP430TargetInfo : public TargetInfo {
5406     static const char * const GCCRegNames[];
5407   public:
5408     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5409       BigEndian = false;
5410       TLSSupported = false;
5411       IntWidth = 16; IntAlign = 16;
5412       LongWidth = 32; LongLongWidth = 64;
5413       LongAlign = LongLongAlign = 16;
5414       PointerWidth = 16; PointerAlign = 16;
5415       SuitableAlign = 16;
5416       SizeType = UnsignedInt;
5417       IntMaxType = SignedLongLong;
5418       IntPtrType = SignedInt;
5419       PtrDiffType = SignedInt;
5420       SigAtomicType = SignedLong;
5421       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5422     }
5423     void getTargetDefines(const LangOptions &Opts,
5424                           MacroBuilder &Builder) const override {
5425       Builder.defineMacro("MSP430");
5426       Builder.defineMacro("__MSP430__");
5427       // FIXME: defines for different 'flavours' of MCU
5428     }
5429     void getTargetBuiltins(const Builtin::Info *&Records,
5430                            unsigned &NumRecords) const override {
5431       // FIXME: Implement.
5432       Records = nullptr;
5433       NumRecords = 0;
5434     }
5435     bool hasFeature(StringRef Feature) const override {
5436       return Feature == "msp430";
5437     }
5438     void getGCCRegNames(const char * const *&Names,
5439                         unsigned &NumNames) const override;
5440     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5441                           unsigned &NumAliases) const override {
5442       // No aliases.
5443       Aliases = nullptr;
5444       NumAliases = 0;
5445     }
5446     bool
5447     validateAsmConstraint(const char *&Name,
5448                           TargetInfo::ConstraintInfo &info) const override {
5449       // No target constraints for now.
5450       return false;
5451     }
5452     const char *getClobbers() const override {
5453       // FIXME: Is this really right?
5454       return "";
5455     }
5456     BuiltinVaListKind getBuiltinVaListKind() const override {
5457       // FIXME: implement
5458       return TargetInfo::CharPtrBuiltinVaList;
5459    }
5460   };
5461 
5462   const char * const MSP430TargetInfo::GCCRegNames[] = {
5463     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5464     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5465   };
5466 
5467   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5468                                         unsigned &NumNames) const {
5469     Names = GCCRegNames;
5470     NumNames = llvm::array_lengthof(GCCRegNames);
5471   }
5472 }
5473 
5474 namespace {
5475 
5476   // LLVM and Clang cannot be used directly to output native binaries for
5477   // target, but is used to compile C code to llvm bitcode with correct
5478   // type and alignment information.
5479   //
5480   // TCE uses the llvm bitcode as input and uses it for generating customized
5481   // target processor and program binary. TCE co-design environment is
5482   // publicly available in http://tce.cs.tut.fi
5483 
5484   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5485       3, // opencl_global
5486       4, // opencl_local
5487       5, // opencl_constant
5488       // FIXME: generic has to be added to the target
5489       0, // opencl_generic
5490       0, // cuda_device
5491       0, // cuda_constant
5492       0  // cuda_shared
5493   };
5494 
5495   class TCETargetInfo : public TargetInfo{
5496   public:
5497     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5498       TLSSupported = false;
5499       IntWidth = 32;
5500       LongWidth = LongLongWidth = 32;
5501       PointerWidth = 32;
5502       IntAlign = 32;
5503       LongAlign = LongLongAlign = 32;
5504       PointerAlign = 32;
5505       SuitableAlign = 32;
5506       SizeType = UnsignedInt;
5507       IntMaxType = SignedLong;
5508       IntPtrType = SignedInt;
5509       PtrDiffType = SignedInt;
5510       FloatWidth = 32;
5511       FloatAlign = 32;
5512       DoubleWidth = 32;
5513       DoubleAlign = 32;
5514       LongDoubleWidth = 32;
5515       LongDoubleAlign = 32;
5516       FloatFormat = &llvm::APFloat::IEEEsingle;
5517       DoubleFormat = &llvm::APFloat::IEEEsingle;
5518       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5519       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5520                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5521       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5522       UseAddrSpaceMapMangling = true;
5523     }
5524 
5525     void getTargetDefines(const LangOptions &Opts,
5526                           MacroBuilder &Builder) const override {
5527       DefineStd(Builder, "tce", Opts);
5528       Builder.defineMacro("__TCE__");
5529       Builder.defineMacro("__TCE_V1__");
5530     }
5531     bool hasFeature(StringRef Feature) const override {
5532       return Feature == "tce";
5533     }
5534 
5535     void getTargetBuiltins(const Builtin::Info *&Records,
5536                            unsigned &NumRecords) const override {}
5537     const char *getClobbers() const override {
5538       return "";
5539     }
5540     BuiltinVaListKind getBuiltinVaListKind() const override {
5541       return TargetInfo::VoidPtrBuiltinVaList;
5542     }
5543     void getGCCRegNames(const char * const *&Names,
5544                         unsigned &NumNames) const override {}
5545     bool validateAsmConstraint(const char *&Name,
5546                                TargetInfo::ConstraintInfo &info) const override{
5547       return true;
5548     }
5549     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5550                           unsigned &NumAliases) const override {}
5551   };
5552 }
5553 
5554 namespace {
5555 class MipsTargetInfoBase : public TargetInfo {
5556   virtual void setDescriptionString() = 0;
5557 
5558   static const Builtin::Info BuiltinInfo[];
5559   std::string CPU;
5560   bool IsMips16;
5561   bool IsMicromips;
5562   bool IsNan2008;
5563   bool IsSingleFloat;
5564   enum MipsFloatABI {
5565     HardFloat, SoftFloat
5566   } FloatABI;
5567   enum DspRevEnum {
5568     NoDSP, DSP1, DSP2
5569   } DspRev;
5570   bool HasMSA;
5571 
5572 protected:
5573   bool HasFP64;
5574   std::string ABI;
5575 
5576 public:
5577   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5578                      const std::string &CPUStr)
5579       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5580         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5581         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5582 
5583   bool isNaN2008Default() const {
5584     return CPU == "mips32r6" || CPU == "mips64r6";
5585   }
5586 
5587   bool isFP64Default() const {
5588     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5589   }
5590 
5591   StringRef getABI() const override { return ABI; }
5592   bool setCPU(const std::string &Name) override {
5593     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5594                     getTriple().getArch() == llvm::Triple::mipsel;
5595     CPU = Name;
5596     return llvm::StringSwitch<bool>(Name)
5597         .Case("mips1", IsMips32)
5598         .Case("mips2", IsMips32)
5599         .Case("mips3", true)
5600         .Case("mips4", true)
5601         .Case("mips5", true)
5602         .Case("mips32", IsMips32)
5603         .Case("mips32r2", IsMips32)
5604         .Case("mips32r6", IsMips32)
5605         .Case("mips64", true)
5606         .Case("mips64r2", true)
5607         .Case("mips64r6", true)
5608         .Case("octeon", true)
5609         .Default(false);
5610   }
5611   const std::string& getCPU() const { return CPU; }
5612   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5613     // The backend enables certain ABI's by default according to the
5614     // architecture.
5615     // Disable both possible defaults so that we don't end up with multiple
5616     // ABI's selected and trigger an assertion.
5617     Features["o32"] = false;
5618     Features["n64"] = false;
5619 
5620     Features[ABI] = true;
5621     if (CPU == "octeon")
5622       Features["mips64r2"] = Features["cnmips"] = true;
5623     else
5624       Features[CPU] = true;
5625   }
5626 
5627   void getTargetDefines(const LangOptions &Opts,
5628                         MacroBuilder &Builder) const override {
5629     Builder.defineMacro("__mips__");
5630     Builder.defineMacro("_mips");
5631     if (Opts.GNUMode)
5632       Builder.defineMacro("mips");
5633 
5634     Builder.defineMacro("__REGISTER_PREFIX__", "");
5635 
5636     switch (FloatABI) {
5637     case HardFloat:
5638       Builder.defineMacro("__mips_hard_float", Twine(1));
5639       break;
5640     case SoftFloat:
5641       Builder.defineMacro("__mips_soft_float", Twine(1));
5642       break;
5643     }
5644 
5645     if (IsSingleFloat)
5646       Builder.defineMacro("__mips_single_float", Twine(1));
5647 
5648     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5649     Builder.defineMacro("_MIPS_FPSET",
5650                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5651 
5652     if (IsMips16)
5653       Builder.defineMacro("__mips16", Twine(1));
5654 
5655     if (IsMicromips)
5656       Builder.defineMacro("__mips_micromips", Twine(1));
5657 
5658     if (IsNan2008)
5659       Builder.defineMacro("__mips_nan2008", Twine(1));
5660 
5661     switch (DspRev) {
5662     default:
5663       break;
5664     case DSP1:
5665       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5666       Builder.defineMacro("__mips_dsp", Twine(1));
5667       break;
5668     case DSP2:
5669       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5670       Builder.defineMacro("__mips_dspr2", Twine(1));
5671       Builder.defineMacro("__mips_dsp", Twine(1));
5672       break;
5673     }
5674 
5675     if (HasMSA)
5676       Builder.defineMacro("__mips_msa", Twine(1));
5677 
5678     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5679     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5680     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5681 
5682     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5683     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5684   }
5685 
5686   void getTargetBuiltins(const Builtin::Info *&Records,
5687                          unsigned &NumRecords) const override {
5688     Records = BuiltinInfo;
5689     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5690   }
5691   bool hasFeature(StringRef Feature) const override {
5692     return llvm::StringSwitch<bool>(Feature)
5693       .Case("mips", true)
5694       .Case("fp64", HasFP64)
5695       .Default(false);
5696   }
5697   BuiltinVaListKind getBuiltinVaListKind() const override {
5698     return TargetInfo::VoidPtrBuiltinVaList;
5699   }
5700   void getGCCRegNames(const char * const *&Names,
5701                       unsigned &NumNames) const override {
5702     static const char *const GCCRegNames[] = {
5703       // CPU register names
5704       // Must match second column of GCCRegAliases
5705       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5706       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5707       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5708       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5709       // Floating point register names
5710       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5711       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5712       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5713       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5714       // Hi/lo and condition register names
5715       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5716       "$fcc5","$fcc6","$fcc7",
5717       // MSA register names
5718       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5719       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5720       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5721       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5722       // MSA control register names
5723       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5724       "$msarequest", "$msamap", "$msaunmap"
5725     };
5726     Names = GCCRegNames;
5727     NumNames = llvm::array_lengthof(GCCRegNames);
5728   }
5729   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5730                         unsigned &NumAliases) const override = 0;
5731   bool validateAsmConstraint(const char *&Name,
5732                              TargetInfo::ConstraintInfo &Info) const override {
5733     switch (*Name) {
5734     default:
5735       return false;
5736     case 'r': // CPU registers.
5737     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5738     case 'y': // Equivalent to "r", backward compatibility only.
5739     case 'f': // floating-point registers.
5740     case 'c': // $25 for indirect jumps
5741     case 'l': // lo register
5742     case 'x': // hilo register pair
5743       Info.setAllowsRegister();
5744       return true;
5745     case 'R': // An address that can be used in a non-macro load or store
5746       Info.setAllowsMemory();
5747       return true;
5748     }
5749   }
5750 
5751   const char *getClobbers() const override {
5752     // FIXME: Implement!
5753     return "";
5754   }
5755 
5756   bool handleTargetFeatures(std::vector<std::string> &Features,
5757                             DiagnosticsEngine &Diags) override {
5758     IsMips16 = false;
5759     IsMicromips = false;
5760     IsNan2008 = isNaN2008Default();
5761     IsSingleFloat = false;
5762     FloatABI = HardFloat;
5763     DspRev = NoDSP;
5764     HasFP64 = isFP64Default();
5765 
5766     for (std::vector<std::string>::iterator it = Features.begin(),
5767          ie = Features.end(); it != ie; ++it) {
5768       if (*it == "+single-float")
5769         IsSingleFloat = true;
5770       else if (*it == "+soft-float")
5771         FloatABI = SoftFloat;
5772       else if (*it == "+mips16")
5773         IsMips16 = true;
5774       else if (*it == "+micromips")
5775         IsMicromips = true;
5776       else if (*it == "+dsp")
5777         DspRev = std::max(DspRev, DSP1);
5778       else if (*it == "+dspr2")
5779         DspRev = std::max(DspRev, DSP2);
5780       else if (*it == "+msa")
5781         HasMSA = true;
5782       else if (*it == "+fp64")
5783         HasFP64 = true;
5784       else if (*it == "-fp64")
5785         HasFP64 = false;
5786       else if (*it == "+nan2008")
5787         IsNan2008 = true;
5788       else if (*it == "-nan2008")
5789         IsNan2008 = false;
5790     }
5791 
5792     // Remove front-end specific options.
5793     std::vector<std::string>::iterator it =
5794       std::find(Features.begin(), Features.end(), "+soft-float");
5795     if (it != Features.end())
5796       Features.erase(it);
5797 
5798     setDescriptionString();
5799 
5800     return true;
5801   }
5802 
5803   int getEHDataRegisterNumber(unsigned RegNo) const override {
5804     if (RegNo == 0) return 4;
5805     if (RegNo == 1) return 5;
5806     return -1;
5807   }
5808 
5809   bool isCLZForZeroUndef() const override { return false; }
5810 };
5811 
5812 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5813 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5814 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5815                                               ALL_LANGUAGES },
5816 #include "clang/Basic/BuiltinsMips.def"
5817 };
5818 
5819 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5820 public:
5821   Mips32TargetInfoBase(const llvm::Triple &Triple)
5822       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5823     SizeType = UnsignedInt;
5824     PtrDiffType = SignedInt;
5825     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5826   }
5827   bool setABI(const std::string &Name) override {
5828     if (Name == "o32" || Name == "eabi") {
5829       ABI = Name;
5830       return true;
5831     }
5832     return false;
5833   }
5834   void getTargetDefines(const LangOptions &Opts,
5835                         MacroBuilder &Builder) const override {
5836     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5837 
5838     Builder.defineMacro("__mips", "32");
5839     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5840 
5841     const std::string& CPUStr = getCPU();
5842     if (CPUStr == "mips32")
5843       Builder.defineMacro("__mips_isa_rev", "1");
5844     else if (CPUStr == "mips32r2")
5845       Builder.defineMacro("__mips_isa_rev", "2");
5846 
5847     if (ABI == "o32") {
5848       Builder.defineMacro("__mips_o32");
5849       Builder.defineMacro("_ABIO32", "1");
5850       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5851     }
5852     else if (ABI == "eabi")
5853       Builder.defineMacro("__mips_eabi");
5854     else
5855       llvm_unreachable("Invalid ABI for Mips32.");
5856   }
5857   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5858                         unsigned &NumAliases) const override {
5859     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5860       { { "at" },  "$1" },
5861       { { "v0" },  "$2" },
5862       { { "v1" },  "$3" },
5863       { { "a0" },  "$4" },
5864       { { "a1" },  "$5" },
5865       { { "a2" },  "$6" },
5866       { { "a3" },  "$7" },
5867       { { "t0" },  "$8" },
5868       { { "t1" },  "$9" },
5869       { { "t2" }, "$10" },
5870       { { "t3" }, "$11" },
5871       { { "t4" }, "$12" },
5872       { { "t5" }, "$13" },
5873       { { "t6" }, "$14" },
5874       { { "t7" }, "$15" },
5875       { { "s0" }, "$16" },
5876       { { "s1" }, "$17" },
5877       { { "s2" }, "$18" },
5878       { { "s3" }, "$19" },
5879       { { "s4" }, "$20" },
5880       { { "s5" }, "$21" },
5881       { { "s6" }, "$22" },
5882       { { "s7" }, "$23" },
5883       { { "t8" }, "$24" },
5884       { { "t9" }, "$25" },
5885       { { "k0" }, "$26" },
5886       { { "k1" }, "$27" },
5887       { { "gp" }, "$28" },
5888       { { "sp","$sp" }, "$29" },
5889       { { "fp","$fp" }, "$30" },
5890       { { "ra" }, "$31" }
5891     };
5892     Aliases = GCCRegAliases;
5893     NumAliases = llvm::array_lengthof(GCCRegAliases);
5894   }
5895 };
5896 
5897 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5898   void setDescriptionString() override {
5899     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5900   }
5901 
5902 public:
5903   Mips32EBTargetInfo(const llvm::Triple &Triple)
5904       : Mips32TargetInfoBase(Triple) {
5905   }
5906   void getTargetDefines(const LangOptions &Opts,
5907                         MacroBuilder &Builder) const override {
5908     DefineStd(Builder, "MIPSEB", Opts);
5909     Builder.defineMacro("_MIPSEB");
5910     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5911   }
5912 };
5913 
5914 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5915   void setDescriptionString() override {
5916     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5917   }
5918 
5919 public:
5920   Mips32ELTargetInfo(const llvm::Triple &Triple)
5921       : Mips32TargetInfoBase(Triple) {
5922     BigEndian = false;
5923   }
5924   void getTargetDefines(const LangOptions &Opts,
5925                         MacroBuilder &Builder) const override {
5926     DefineStd(Builder, "MIPSEL", Opts);
5927     Builder.defineMacro("_MIPSEL");
5928     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5929   }
5930 };
5931 
5932 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5933 public:
5934   Mips64TargetInfoBase(const llvm::Triple &Triple)
5935       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5936     LongDoubleWidth = LongDoubleAlign = 128;
5937     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5938     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5939       LongDoubleWidth = LongDoubleAlign = 64;
5940       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5941     }
5942     setN64ABITypes();
5943     SuitableAlign = 128;
5944     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5945   }
5946 
5947   void setN64ABITypes() {
5948     LongWidth = LongAlign = 64;
5949     PointerWidth = PointerAlign = 64;
5950     SizeType = UnsignedLong;
5951     PtrDiffType = SignedLong;
5952   }
5953 
5954   void setN32ABITypes() {
5955     LongWidth = LongAlign = 32;
5956     PointerWidth = PointerAlign = 32;
5957     SizeType = UnsignedInt;
5958     PtrDiffType = SignedInt;
5959   }
5960 
5961   bool setABI(const std::string &Name) override {
5962     if (Name == "n32") {
5963       setN32ABITypes();
5964       ABI = Name;
5965       return true;
5966     }
5967     if (Name == "n64") {
5968       setN64ABITypes();
5969       ABI = Name;
5970       return true;
5971     }
5972     return false;
5973   }
5974 
5975   void getTargetDefines(const LangOptions &Opts,
5976                         MacroBuilder &Builder) const override {
5977     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5978 
5979     Builder.defineMacro("__mips", "64");
5980     Builder.defineMacro("__mips64");
5981     Builder.defineMacro("__mips64__");
5982     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5983 
5984     const std::string& CPUStr = getCPU();
5985     if (CPUStr == "mips64")
5986       Builder.defineMacro("__mips_isa_rev", "1");
5987     else if (CPUStr == "mips64r2")
5988       Builder.defineMacro("__mips_isa_rev", "2");
5989 
5990     if (ABI == "n32") {
5991       Builder.defineMacro("__mips_n32");
5992       Builder.defineMacro("_ABIN32", "2");
5993       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5994     }
5995     else if (ABI == "n64") {
5996       Builder.defineMacro("__mips_n64");
5997       Builder.defineMacro("_ABI64", "3");
5998       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5999     }
6000     else
6001       llvm_unreachable("Invalid ABI for Mips64.");
6002   }
6003   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6004                         unsigned &NumAliases) const override {
6005     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6006       { { "at" },  "$1" },
6007       { { "v0" },  "$2" },
6008       { { "v1" },  "$3" },
6009       { { "a0" },  "$4" },
6010       { { "a1" },  "$5" },
6011       { { "a2" },  "$6" },
6012       { { "a3" },  "$7" },
6013       { { "a4" },  "$8" },
6014       { { "a5" },  "$9" },
6015       { { "a6" }, "$10" },
6016       { { "a7" }, "$11" },
6017       { { "t0" }, "$12" },
6018       { { "t1" }, "$13" },
6019       { { "t2" }, "$14" },
6020       { { "t3" }, "$15" },
6021       { { "s0" }, "$16" },
6022       { { "s1" }, "$17" },
6023       { { "s2" }, "$18" },
6024       { { "s3" }, "$19" },
6025       { { "s4" }, "$20" },
6026       { { "s5" }, "$21" },
6027       { { "s6" }, "$22" },
6028       { { "s7" }, "$23" },
6029       { { "t8" }, "$24" },
6030       { { "t9" }, "$25" },
6031       { { "k0" }, "$26" },
6032       { { "k1" }, "$27" },
6033       { { "gp" }, "$28" },
6034       { { "sp","$sp" }, "$29" },
6035       { { "fp","$fp" }, "$30" },
6036       { { "ra" }, "$31" }
6037     };
6038     Aliases = GCCRegAliases;
6039     NumAliases = llvm::array_lengthof(GCCRegAliases);
6040   }
6041 
6042   bool hasInt128Type() const override { return true; }
6043 };
6044 
6045 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6046   void setDescriptionString() override {
6047     if (ABI == "n32")
6048       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6049     else
6050       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6051 
6052   }
6053 
6054 public:
6055   Mips64EBTargetInfo(const llvm::Triple &Triple)
6056       : Mips64TargetInfoBase(Triple) {}
6057   void getTargetDefines(const LangOptions &Opts,
6058                         MacroBuilder &Builder) const override {
6059     DefineStd(Builder, "MIPSEB", Opts);
6060     Builder.defineMacro("_MIPSEB");
6061     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6062   }
6063 };
6064 
6065 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6066   void setDescriptionString() override {
6067     if (ABI == "n32")
6068       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6069     else
6070       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6071   }
6072 public:
6073   Mips64ELTargetInfo(const llvm::Triple &Triple)
6074       : Mips64TargetInfoBase(Triple) {
6075     // Default ABI is n64.
6076     BigEndian = false;
6077   }
6078   void getTargetDefines(const LangOptions &Opts,
6079                         MacroBuilder &Builder) const override {
6080     DefineStd(Builder, "MIPSEL", Opts);
6081     Builder.defineMacro("_MIPSEL");
6082     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6083   }
6084 };
6085 } // end anonymous namespace.
6086 
6087 namespace {
6088 class PNaClTargetInfo : public TargetInfo {
6089 public:
6090   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6091     BigEndian = false;
6092     this->UserLabelPrefix = "";
6093     this->LongAlign = 32;
6094     this->LongWidth = 32;
6095     this->PointerAlign = 32;
6096     this->PointerWidth = 32;
6097     this->IntMaxType = TargetInfo::SignedLongLong;
6098     this->Int64Type = TargetInfo::SignedLongLong;
6099     this->DoubleAlign = 64;
6100     this->LongDoubleWidth = 64;
6101     this->LongDoubleAlign = 64;
6102     this->SizeType = TargetInfo::UnsignedInt;
6103     this->PtrDiffType = TargetInfo::SignedInt;
6104     this->IntPtrType = TargetInfo::SignedInt;
6105     this->RegParmMax = 0; // Disallow regparm
6106   }
6107 
6108   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6109   }
6110   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6111     Builder.defineMacro("__le32__");
6112     Builder.defineMacro("__pnacl__");
6113   }
6114   void getTargetDefines(const LangOptions &Opts,
6115                         MacroBuilder &Builder) const override {
6116     getArchDefines(Opts, Builder);
6117   }
6118   bool hasFeature(StringRef Feature) const override {
6119     return Feature == "pnacl";
6120   }
6121   void getTargetBuiltins(const Builtin::Info *&Records,
6122                          unsigned &NumRecords) const override {
6123   }
6124   BuiltinVaListKind getBuiltinVaListKind() const override {
6125     return TargetInfo::PNaClABIBuiltinVaList;
6126   }
6127   void getGCCRegNames(const char * const *&Names,
6128                       unsigned &NumNames) const override;
6129   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6130                         unsigned &NumAliases) const override;
6131   bool validateAsmConstraint(const char *&Name,
6132                              TargetInfo::ConstraintInfo &Info) const override {
6133     return false;
6134   }
6135 
6136   const char *getClobbers() const override {
6137     return "";
6138   }
6139 };
6140 
6141 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6142                                      unsigned &NumNames) const {
6143   Names = nullptr;
6144   NumNames = 0;
6145 }
6146 
6147 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6148                                        unsigned &NumAliases) const {
6149   Aliases = nullptr;
6150   NumAliases = 0;
6151 }
6152 } // end anonymous namespace.
6153 
6154 namespace {
6155 class Le64TargetInfo : public TargetInfo {
6156   static const Builtin::Info BuiltinInfo[];
6157 
6158 public:
6159   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6160     BigEndian = false;
6161     NoAsmVariants = true;
6162     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6163     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6164     DescriptionString =
6165         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6166   }
6167 
6168   void getTargetDefines(const LangOptions &Opts,
6169                         MacroBuilder &Builder) const override {
6170     DefineStd(Builder, "unix", Opts);
6171     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6172     Builder.defineMacro("__ELF__");
6173   }
6174   void getTargetBuiltins(const Builtin::Info *&Records,
6175                          unsigned &NumRecords) const override {
6176     Records = BuiltinInfo;
6177     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6178   }
6179   BuiltinVaListKind getBuiltinVaListKind() const override {
6180     return TargetInfo::PNaClABIBuiltinVaList;
6181   }
6182   const char *getClobbers() const override { return ""; }
6183   void getGCCRegNames(const char *const *&Names,
6184                       unsigned &NumNames) const override {
6185     Names = nullptr;
6186     NumNames = 0;
6187   }
6188   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6189                         unsigned &NumAliases) const override {
6190     Aliases = nullptr;
6191     NumAliases = 0;
6192   }
6193   bool validateAsmConstraint(const char *&Name,
6194                              TargetInfo::ConstraintInfo &Info) const override {
6195     return false;
6196   }
6197 
6198   bool hasProtectedVisibility() const override { return false; }
6199 };
6200 } // end anonymous namespace.
6201 
6202 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6203 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6204   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6205 #include "clang/Basic/BuiltinsLe64.def"
6206 };
6207 
6208 namespace {
6209   static const unsigned SPIRAddrSpaceMap[] = {
6210     1,    // opencl_global
6211     3,    // opencl_local
6212     2,    // opencl_constant
6213     4,    // opencl_generic
6214     0,    // cuda_device
6215     0,    // cuda_constant
6216     0     // cuda_shared
6217   };
6218   class SPIRTargetInfo : public TargetInfo {
6219   public:
6220     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6221       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6222         "SPIR target must use unknown OS");
6223       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6224         "SPIR target must use unknown environment type");
6225       BigEndian = false;
6226       TLSSupported = false;
6227       LongWidth = LongAlign = 64;
6228       AddrSpaceMap = &SPIRAddrSpaceMap;
6229       UseAddrSpaceMapMangling = true;
6230       // Define available target features
6231       // These must be defined in sorted order!
6232       NoAsmVariants = true;
6233     }
6234     void getTargetDefines(const LangOptions &Opts,
6235                           MacroBuilder &Builder) const override {
6236       DefineStd(Builder, "SPIR", Opts);
6237     }
6238     bool hasFeature(StringRef Feature) const override {
6239       return Feature == "spir";
6240     }
6241 
6242     void getTargetBuiltins(const Builtin::Info *&Records,
6243                            unsigned &NumRecords) const override {}
6244     const char *getClobbers() const override {
6245       return "";
6246     }
6247     void getGCCRegNames(const char * const *&Names,
6248                         unsigned &NumNames) const override {}
6249     bool
6250     validateAsmConstraint(const char *&Name,
6251                           TargetInfo::ConstraintInfo &info) const override {
6252       return true;
6253     }
6254     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6255                           unsigned &NumAliases) const override {}
6256     BuiltinVaListKind getBuiltinVaListKind() const override {
6257       return TargetInfo::VoidPtrBuiltinVaList;
6258     }
6259   };
6260 
6261 
6262   class SPIR32TargetInfo : public SPIRTargetInfo {
6263   public:
6264     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6265       PointerWidth = PointerAlign = 32;
6266       SizeType     = TargetInfo::UnsignedInt;
6267       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6268       DescriptionString
6269         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6270           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6271     }
6272     void getTargetDefines(const LangOptions &Opts,
6273                           MacroBuilder &Builder) const override {
6274       DefineStd(Builder, "SPIR32", Opts);
6275     }
6276   };
6277 
6278   class SPIR64TargetInfo : public SPIRTargetInfo {
6279   public:
6280     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6281       PointerWidth = PointerAlign = 64;
6282       SizeType     = TargetInfo::UnsignedLong;
6283       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6284       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6285                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6286     }
6287     void getTargetDefines(const LangOptions &Opts,
6288                           MacroBuilder &Builder) const override {
6289       DefineStd(Builder, "SPIR64", Opts);
6290     }
6291   };
6292 }
6293 
6294 namespace {
6295 class XCoreTargetInfo : public TargetInfo {
6296   static const Builtin::Info BuiltinInfo[];
6297 public:
6298   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6299     BigEndian = false;
6300     NoAsmVariants = true;
6301     LongLongAlign = 32;
6302     SuitableAlign = 32;
6303     DoubleAlign = LongDoubleAlign = 32;
6304     SizeType = UnsignedInt;
6305     PtrDiffType = SignedInt;
6306     IntPtrType = SignedInt;
6307     WCharType = UnsignedChar;
6308     WIntType = UnsignedInt;
6309     UseZeroLengthBitfieldAlignment = true;
6310     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6311                         "-f64:32-a:0:32-n32";
6312   }
6313   void getTargetDefines(const LangOptions &Opts,
6314                         MacroBuilder &Builder) const override {
6315     Builder.defineMacro("__XS1B__");
6316   }
6317   void getTargetBuiltins(const Builtin::Info *&Records,
6318                          unsigned &NumRecords) const override {
6319     Records = BuiltinInfo;
6320     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6321   }
6322   BuiltinVaListKind getBuiltinVaListKind() const override {
6323     return TargetInfo::VoidPtrBuiltinVaList;
6324   }
6325   const char *getClobbers() const override {
6326     return "";
6327   }
6328   void getGCCRegNames(const char * const *&Names,
6329                       unsigned &NumNames) const override {
6330     static const char * const GCCRegNames[] = {
6331       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6332       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6333     };
6334     Names = GCCRegNames;
6335     NumNames = llvm::array_lengthof(GCCRegNames);
6336   }
6337   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6338                         unsigned &NumAliases) const override {
6339     Aliases = nullptr;
6340     NumAliases = 0;
6341   }
6342   bool validateAsmConstraint(const char *&Name,
6343                              TargetInfo::ConstraintInfo &Info) const override {
6344     return false;
6345   }
6346   int getEHDataRegisterNumber(unsigned RegNo) const override {
6347     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6348     return (RegNo < 2)? RegNo : -1;
6349   }
6350 };
6351 
6352 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6353 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6354 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6355                                               ALL_LANGUAGES },
6356 #include "clang/Basic/BuiltinsXCore.def"
6357 };
6358 } // end anonymous namespace.
6359 
6360 
6361 //===----------------------------------------------------------------------===//
6362 // Driver code
6363 //===----------------------------------------------------------------------===//
6364 
6365 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6366   llvm::Triple::OSType os = Triple.getOS();
6367 
6368   switch (Triple.getArch()) {
6369   default:
6370     return nullptr;
6371 
6372   case llvm::Triple::xcore:
6373     return new XCoreTargetInfo(Triple);
6374 
6375   case llvm::Triple::hexagon:
6376     return new HexagonTargetInfo(Triple);
6377 
6378   case llvm::Triple::aarch64:
6379     if (Triple.isOSDarwin())
6380       return new DarwinAArch64TargetInfo(Triple);
6381 
6382     switch (os) {
6383     case llvm::Triple::FreeBSD:
6384       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6385     case llvm::Triple::Linux:
6386       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6387     case llvm::Triple::NetBSD:
6388       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6389     default:
6390       return new AArch64leTargetInfo(Triple);
6391     }
6392 
6393   case llvm::Triple::aarch64_be:
6394     switch (os) {
6395     case llvm::Triple::FreeBSD:
6396       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6397     case llvm::Triple::Linux:
6398       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6399     case llvm::Triple::NetBSD:
6400       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6401     default:
6402       return new AArch64beTargetInfo(Triple);
6403     }
6404 
6405   case llvm::Triple::arm:
6406   case llvm::Triple::thumb:
6407     if (Triple.isOSBinFormatMachO())
6408       return new DarwinARMTargetInfo(Triple);
6409 
6410     switch (os) {
6411     case llvm::Triple::Linux:
6412       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6413     case llvm::Triple::FreeBSD:
6414       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6415     case llvm::Triple::NetBSD:
6416       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6417     case llvm::Triple::OpenBSD:
6418       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6419     case llvm::Triple::Bitrig:
6420       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6421     case llvm::Triple::RTEMS:
6422       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6423     case llvm::Triple::NaCl:
6424       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6425     case llvm::Triple::Win32:
6426       switch (Triple.getEnvironment()) {
6427       default:
6428         return new ARMleTargetInfo(Triple);
6429       case llvm::Triple::Itanium:
6430         return new ItaniumWindowsARMleTargetInfo(Triple);
6431       case llvm::Triple::MSVC:
6432         return new MicrosoftARMleTargetInfo(Triple);
6433       }
6434     default:
6435       return new ARMleTargetInfo(Triple);
6436     }
6437 
6438   case llvm::Triple::armeb:
6439   case llvm::Triple::thumbeb:
6440     if (Triple.isOSDarwin())
6441       return new DarwinARMTargetInfo(Triple);
6442 
6443     switch (os) {
6444     case llvm::Triple::Linux:
6445       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6446     case llvm::Triple::FreeBSD:
6447       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6448     case llvm::Triple::NetBSD:
6449       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6450     case llvm::Triple::OpenBSD:
6451       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6452     case llvm::Triple::Bitrig:
6453       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6454     case llvm::Triple::RTEMS:
6455       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6456     case llvm::Triple::NaCl:
6457       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6458     default:
6459       return new ARMbeTargetInfo(Triple);
6460     }
6461 
6462   case llvm::Triple::msp430:
6463     return new MSP430TargetInfo(Triple);
6464 
6465   case llvm::Triple::mips:
6466     switch (os) {
6467     case llvm::Triple::Linux:
6468       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6469     case llvm::Triple::RTEMS:
6470       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6471     case llvm::Triple::FreeBSD:
6472       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6473     case llvm::Triple::NetBSD:
6474       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6475     default:
6476       return new Mips32EBTargetInfo(Triple);
6477     }
6478 
6479   case llvm::Triple::mipsel:
6480     switch (os) {
6481     case llvm::Triple::Linux:
6482       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6483     case llvm::Triple::RTEMS:
6484       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6485     case llvm::Triple::FreeBSD:
6486       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6487     case llvm::Triple::NetBSD:
6488       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6489     case llvm::Triple::NaCl:
6490       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6491     default:
6492       return new Mips32ELTargetInfo(Triple);
6493     }
6494 
6495   case llvm::Triple::mips64:
6496     switch (os) {
6497     case llvm::Triple::Linux:
6498       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6499     case llvm::Triple::RTEMS:
6500       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6501     case llvm::Triple::FreeBSD:
6502       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6503     case llvm::Triple::NetBSD:
6504       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6505     case llvm::Triple::OpenBSD:
6506       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6507     default:
6508       return new Mips64EBTargetInfo(Triple);
6509     }
6510 
6511   case llvm::Triple::mips64el:
6512     switch (os) {
6513     case llvm::Triple::Linux:
6514       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6515     case llvm::Triple::RTEMS:
6516       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6517     case llvm::Triple::FreeBSD:
6518       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6519     case llvm::Triple::NetBSD:
6520       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6521     case llvm::Triple::OpenBSD:
6522       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6523     default:
6524       return new Mips64ELTargetInfo(Triple);
6525     }
6526 
6527   case llvm::Triple::le32:
6528     switch (os) {
6529       case llvm::Triple::NaCl:
6530         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6531       default:
6532         return nullptr;
6533     }
6534 
6535   case llvm::Triple::le64:
6536     return new Le64TargetInfo(Triple);
6537 
6538   case llvm::Triple::ppc:
6539     if (Triple.isOSDarwin())
6540       return new DarwinPPC32TargetInfo(Triple);
6541     switch (os) {
6542     case llvm::Triple::Linux:
6543       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6544     case llvm::Triple::FreeBSD:
6545       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6546     case llvm::Triple::NetBSD:
6547       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6548     case llvm::Triple::OpenBSD:
6549       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6550     case llvm::Triple::RTEMS:
6551       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6552     default:
6553       return new PPC32TargetInfo(Triple);
6554     }
6555 
6556   case llvm::Triple::ppc64:
6557     if (Triple.isOSDarwin())
6558       return new DarwinPPC64TargetInfo(Triple);
6559     switch (os) {
6560     case llvm::Triple::Linux:
6561       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6562     case llvm::Triple::Lv2:
6563       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6564     case llvm::Triple::FreeBSD:
6565       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6566     case llvm::Triple::NetBSD:
6567       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6568     default:
6569       return new PPC64TargetInfo(Triple);
6570     }
6571 
6572   case llvm::Triple::ppc64le:
6573     switch (os) {
6574     case llvm::Triple::Linux:
6575       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6576     default:
6577       return new PPC64TargetInfo(Triple);
6578     }
6579 
6580   case llvm::Triple::nvptx:
6581     return new NVPTX32TargetInfo(Triple);
6582   case llvm::Triple::nvptx64:
6583     return new NVPTX64TargetInfo(Triple);
6584 
6585   case llvm::Triple::r600:
6586     return new R600TargetInfo(Triple);
6587 
6588   case llvm::Triple::sparc:
6589     switch (os) {
6590     case llvm::Triple::Linux:
6591       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6592     case llvm::Triple::Solaris:
6593       return new SolarisSparcV8TargetInfo(Triple);
6594     case llvm::Triple::NetBSD:
6595       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6596     case llvm::Triple::OpenBSD:
6597       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6598     case llvm::Triple::RTEMS:
6599       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6600     default:
6601       return new SparcV8TargetInfo(Triple);
6602     }
6603 
6604   case llvm::Triple::sparcv9:
6605     switch (os) {
6606     case llvm::Triple::Linux:
6607       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6608     case llvm::Triple::Solaris:
6609       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6610     case llvm::Triple::NetBSD:
6611       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6612     case llvm::Triple::OpenBSD:
6613       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6614     case llvm::Triple::FreeBSD:
6615       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6616     default:
6617       return new SparcV9TargetInfo(Triple);
6618     }
6619 
6620   case llvm::Triple::systemz:
6621     switch (os) {
6622     case llvm::Triple::Linux:
6623       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6624     default:
6625       return new SystemZTargetInfo(Triple);
6626     }
6627 
6628   case llvm::Triple::tce:
6629     return new TCETargetInfo(Triple);
6630 
6631   case llvm::Triple::x86:
6632     if (Triple.isOSDarwin())
6633       return new DarwinI386TargetInfo(Triple);
6634 
6635     switch (os) {
6636     case llvm::Triple::Linux:
6637       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6638     case llvm::Triple::DragonFly:
6639       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6640     case llvm::Triple::NetBSD:
6641       return new NetBSDI386TargetInfo(Triple);
6642     case llvm::Triple::OpenBSD:
6643       return new OpenBSDI386TargetInfo(Triple);
6644     case llvm::Triple::Bitrig:
6645       return new BitrigI386TargetInfo(Triple);
6646     case llvm::Triple::FreeBSD:
6647       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6648     case llvm::Triple::KFreeBSD:
6649       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6650     case llvm::Triple::Minix:
6651       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6652     case llvm::Triple::Solaris:
6653       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6654     case llvm::Triple::Win32: {
6655       switch (Triple.getEnvironment()) {
6656       default:
6657         return new X86_32TargetInfo(Triple);
6658       case llvm::Triple::Cygnus:
6659         return new CygwinX86_32TargetInfo(Triple);
6660       case llvm::Triple::GNU:
6661         return new MinGWX86_32TargetInfo(Triple);
6662       case llvm::Triple::Itanium:
6663       case llvm::Triple::MSVC:
6664         return new MicrosoftX86_32TargetInfo(Triple);
6665       }
6666     }
6667     case llvm::Triple::Haiku:
6668       return new HaikuX86_32TargetInfo(Triple);
6669     case llvm::Triple::RTEMS:
6670       return new RTEMSX86_32TargetInfo(Triple);
6671     case llvm::Triple::NaCl:
6672       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6673     default:
6674       return new X86_32TargetInfo(Triple);
6675     }
6676 
6677   case llvm::Triple::x86_64:
6678     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6679       return new DarwinX86_64TargetInfo(Triple);
6680 
6681     switch (os) {
6682     case llvm::Triple::Linux:
6683       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6684     case llvm::Triple::DragonFly:
6685       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6686     case llvm::Triple::NetBSD:
6687       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6688     case llvm::Triple::OpenBSD:
6689       return new OpenBSDX86_64TargetInfo(Triple);
6690     case llvm::Triple::Bitrig:
6691       return new BitrigX86_64TargetInfo(Triple);
6692     case llvm::Triple::FreeBSD:
6693       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6694     case llvm::Triple::KFreeBSD:
6695       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6696     case llvm::Triple::Solaris:
6697       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6698     case llvm::Triple::Win32: {
6699       switch (Triple.getEnvironment()) {
6700       default:
6701         return new X86_64TargetInfo(Triple);
6702       case llvm::Triple::GNU:
6703         return new MinGWX86_64TargetInfo(Triple);
6704       case llvm::Triple::MSVC:
6705         return new MicrosoftX86_64TargetInfo(Triple);
6706       }
6707     }
6708     case llvm::Triple::NaCl:
6709       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6710     default:
6711       return new X86_64TargetInfo(Triple);
6712     }
6713 
6714     case llvm::Triple::spir: {
6715       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6716           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6717         return nullptr;
6718       return new SPIR32TargetInfo(Triple);
6719     }
6720     case llvm::Triple::spir64: {
6721       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6722           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6723         return nullptr;
6724       return new SPIR64TargetInfo(Triple);
6725     }
6726   }
6727 }
6728 
6729 /// CreateTargetInfo - Return the target info object for the specified target
6730 /// triple.
6731 TargetInfo *
6732 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6733                              const std::shared_ptr<TargetOptions> &Opts) {
6734   llvm::Triple Triple(Opts->Triple);
6735 
6736   // Construct the target
6737   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6738   if (!Target) {
6739     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6740     return nullptr;
6741   }
6742   Target->TargetOpts = Opts;
6743 
6744   // Set the target CPU if specified.
6745   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6746     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6747     return nullptr;
6748   }
6749 
6750   // Set the target ABI if specified.
6751   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6752     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6753     return nullptr;
6754   }
6755 
6756   // Set the fp math unit.
6757   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6758     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6759     return nullptr;
6760   }
6761 
6762   // Compute the default target features, we need the target to handle this
6763   // because features may have dependencies on one another.
6764   llvm::StringMap<bool> Features;
6765   Target->getDefaultFeatures(Features);
6766 
6767   // Apply the user specified deltas.
6768   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6769        I < N; ++I) {
6770     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6771     // Apply the feature via the target.
6772     bool Enabled = Name[0] == '+';
6773     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6774   }
6775 
6776   // Add the features to the compile options.
6777   //
6778   // FIXME: If we are completely confident that we have the right set, we only
6779   // need to pass the minuses.
6780   Opts->Features.clear();
6781   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6782          ie = Features.end(); it != ie; ++it)
6783     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6784   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6785     return nullptr;
6786 
6787   return Target.release();
6788 }
6789