1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.has(SanitizerKind::Address))
98     Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 
100   if (!Opts.ObjCAutoRefCount) {
101     // __weak is always defined, for use in blocks and with objc pointers.
102     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 
104     // Darwin defines __strong even in C mode (just to nothing).
105     if (Opts.getGC() != LangOptions::NonGC)
106       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107     else
108       Builder.defineMacro("__strong", "");
109 
110     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111     // allow this in C, since one might have block pointers in structs that
112     // are used in pure C code and in Objective-C ARC.
113     Builder.defineMacro("__unsafe_unretained", "");
114   }
115 
116   if (Opts.Static)
117     Builder.defineMacro("__STATIC__");
118   else
119     Builder.defineMacro("__DYNAMIC__");
120 
121   if (Opts.POSIXThreads)
122     Builder.defineMacro("_REENTRANT");
123 
124   // Get the platform type and version number from the triple.
125   unsigned Maj, Min, Rev;
126   if (Triple.isMacOSX()) {
127     Triple.getMacOSXVersion(Maj, Min, Rev);
128     PlatformName = "macosx";
129   } else {
130     Triple.getOSVersion(Maj, Min, Rev);
131     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132   }
133 
134   // If -target arch-pc-win32-macho option specified, we're
135   // generating code for Win32 ABI. No need to emit
136   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137   if (PlatformName == "win32") {
138     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139     return;
140   }
141 
142   // Set the appropriate OS version define.
143   if (Triple.isiOS()) {
144     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145     char Str[6];
146     Str[0] = '0' + Maj;
147     Str[1] = '0' + (Min / 10);
148     Str[2] = '0' + (Min % 10);
149     Str[3] = '0' + (Rev / 10);
150     Str[4] = '0' + (Rev % 10);
151     Str[5] = '\0';
152     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153                         Str);
154   } else if (Triple.isMacOSX()) {
155     // Note that the Driver allows versions which aren't representable in the
156     // define (because we only get a single digit for the minor and micro
157     // revision numbers). So, we limit them to the maximum representable
158     // version.
159     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160     char Str[7];
161     if (Maj < 10 || (Maj == 10 && Min < 10)) {
162       Str[0] = '0' + (Maj / 10);
163       Str[1] = '0' + (Maj % 10);
164       Str[2] = '0' + std::min(Min, 9U);
165       Str[3] = '0' + std::min(Rev, 9U);
166       Str[4] = '\0';
167     } else {
168       // Handle versions > 10.9.
169       Str[0] = '0' + (Maj / 10);
170       Str[1] = '0' + (Maj % 10);
171       Str[2] = '0' + (Min / 10);
172       Str[3] = '0' + (Min % 10);
173       Str[4] = '0' + (Rev / 10);
174       Str[5] = '0' + (Rev % 10);
175       Str[6] = '\0';
176     }
177     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178   }
179 
180   // Tell users about the kernel if there is one.
181   if (Triple.isOSDarwin())
182     Builder.defineMacro("__MACH__");
183 
184   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186 
187 namespace {
188 template<typename Target>
189 class DarwinTargetInfo : public OSTargetInfo<Target> {
190 protected:
191   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
192                     MacroBuilder &Builder) const override {
193     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
194                      this->PlatformMinVersion);
195   }
196 
197 public:
198   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
199     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
200     this->MCountName = "\01mcount";
201   }
202 
203   std::string isValidSectionSpecifier(StringRef SR) const override {
204     // Let MCSectionMachO validate this.
205     StringRef Segment, Section;
206     unsigned TAA, StubSize;
207     bool HasTAA;
208     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
209                                                        TAA, HasTAA, StubSize);
210   }
211 
212   const char *getStaticInitSectionSpecifier() const override {
213     // FIXME: We should return 0 when building kexts.
214     return "__TEXT,__StaticInit,regular,pure_instructions";
215   }
216 
217   /// Darwin does not support protected visibility.  Darwin's "default"
218   /// is very similar to ELF's "protected";  Darwin requires a "weak"
219   /// attribute on declarations that can be dynamically replaced.
220   bool hasProtectedVisibility() const override {
221     return false;
222   }
223 };
224 
225 
226 // DragonFlyBSD Target
227 template<typename Target>
228 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
229 protected:
230   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
231                     MacroBuilder &Builder) const override {
232     // DragonFly defines; list based off of gcc output
233     Builder.defineMacro("__DragonFly__");
234     Builder.defineMacro("__DragonFly_cc_version", "100001");
235     Builder.defineMacro("__ELF__");
236     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
237     Builder.defineMacro("__tune_i386__");
238     DefineStd(Builder, "unix", Opts);
239   }
240 public:
241   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
242       : OSTargetInfo<Target>(Triple) {
243     this->UserLabelPrefix = "";
244 
245     switch (Triple.getArch()) {
246     default:
247     case llvm::Triple::x86:
248     case llvm::Triple::x86_64:
249       this->MCountName = ".mcount";
250       break;
251     }
252   }
253 };
254 
255 // FreeBSD Target
256 template<typename Target>
257 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
258 protected:
259   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
260                     MacroBuilder &Builder) const override {
261     // FreeBSD defines; list based off of gcc output
262 
263     unsigned Release = Triple.getOSMajorVersion();
264     if (Release == 0U)
265       Release = 8;
266 
267     Builder.defineMacro("__FreeBSD__", Twine(Release));
268     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
269     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
270     DefineStd(Builder, "unix", Opts);
271     Builder.defineMacro("__ELF__");
272 
273     // On FreeBSD, wchar_t contains the number of the code point as
274     // used by the character set of the locale. These character sets are
275     // not necessarily a superset of ASCII.
276     //
277     // FIXME: This is wrong; the macro refers to the numerical values
278     // of wchar_t *literals*, which are not locale-dependent. However,
279     // FreeBSD systems apparently depend on us getting this wrong, and
280     // setting this to 1 is conforming even if all the basic source
281     // character literals have the same encoding as char and wchar_t.
282     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
283   }
284 public:
285   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
286     this->UserLabelPrefix = "";
287 
288     switch (Triple.getArch()) {
289     default:
290     case llvm::Triple::x86:
291     case llvm::Triple::x86_64:
292       this->MCountName = ".mcount";
293       break;
294     case llvm::Triple::mips:
295     case llvm::Triple::mipsel:
296     case llvm::Triple::ppc:
297     case llvm::Triple::ppc64:
298     case llvm::Triple::ppc64le:
299       this->MCountName = "_mcount";
300       break;
301     case llvm::Triple::arm:
302       this->MCountName = "__mcount";
303       break;
304     }
305   }
306 };
307 
308 // GNU/kFreeBSD Target
309 template<typename Target>
310 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
311 protected:
312   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
313                     MacroBuilder &Builder) const override {
314     // GNU/kFreeBSD defines; list based off of gcc output
315 
316     DefineStd(Builder, "unix", Opts);
317     Builder.defineMacro("__FreeBSD_kernel__");
318     Builder.defineMacro("__GLIBC__");
319     Builder.defineMacro("__ELF__");
320     if (Opts.POSIXThreads)
321       Builder.defineMacro("_REENTRANT");
322     if (Opts.CPlusPlus)
323       Builder.defineMacro("_GNU_SOURCE");
324   }
325 public:
326   KFreeBSDTargetInfo(const llvm::Triple &Triple)
327       : OSTargetInfo<Target>(Triple) {
328     this->UserLabelPrefix = "";
329   }
330 };
331 
332 // Minix Target
333 template<typename Target>
334 class MinixTargetInfo : public OSTargetInfo<Target> {
335 protected:
336   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
337                     MacroBuilder &Builder) const override {
338     // Minix defines
339 
340     Builder.defineMacro("__minix", "3");
341     Builder.defineMacro("_EM_WSIZE", "4");
342     Builder.defineMacro("_EM_PSIZE", "4");
343     Builder.defineMacro("_EM_SSIZE", "2");
344     Builder.defineMacro("_EM_LSIZE", "4");
345     Builder.defineMacro("_EM_FSIZE", "4");
346     Builder.defineMacro("_EM_DSIZE", "8");
347     Builder.defineMacro("__ELF__");
348     DefineStd(Builder, "unix", Opts);
349   }
350 public:
351   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
352     this->UserLabelPrefix = "";
353   }
354 };
355 
356 // Linux target
357 template<typename Target>
358 class LinuxTargetInfo : public OSTargetInfo<Target> {
359 protected:
360   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
361                     MacroBuilder &Builder) const override {
362     // Linux defines; list based off of gcc output
363     DefineStd(Builder, "unix", Opts);
364     DefineStd(Builder, "linux", Opts);
365     Builder.defineMacro("__gnu_linux__");
366     Builder.defineMacro("__ELF__");
367     if (Triple.getEnvironment() == llvm::Triple::Android)
368       Builder.defineMacro("__ANDROID__", "1");
369     if (Opts.POSIXThreads)
370       Builder.defineMacro("_REENTRANT");
371     if (Opts.CPlusPlus)
372       Builder.defineMacro("_GNU_SOURCE");
373   }
374 public:
375   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
376     this->UserLabelPrefix = "";
377     this->WIntType = TargetInfo::UnsignedInt;
378 
379     switch (Triple.getArch()) {
380     default:
381       break;
382     case llvm::Triple::ppc:
383     case llvm::Triple::ppc64:
384     case llvm::Triple::ppc64le:
385       this->MCountName = "_mcount";
386       break;
387     }
388   }
389 
390   const char *getStaticInitSectionSpecifier() const override {
391     return ".text.startup";
392   }
393 };
394 
395 // NetBSD Target
396 template<typename Target>
397 class NetBSDTargetInfo : public OSTargetInfo<Target> {
398 protected:
399   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
400                     MacroBuilder &Builder) const override {
401     // NetBSD defines; list based off of gcc output
402     Builder.defineMacro("__NetBSD__");
403     Builder.defineMacro("__unix__");
404     Builder.defineMacro("__ELF__");
405     if (Opts.POSIXThreads)
406       Builder.defineMacro("_POSIX_THREADS");
407 
408     switch (Triple.getArch()) {
409     default:
410       break;
411     case llvm::Triple::arm:
412     case llvm::Triple::armeb:
413     case llvm::Triple::thumb:
414     case llvm::Triple::thumbeb:
415       Builder.defineMacro("__ARM_DWARF_EH__");
416       break;
417     }
418   }
419 public:
420   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
421     this->UserLabelPrefix = "";
422   }
423 };
424 
425 // OpenBSD Target
426 template<typename Target>
427 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
428 protected:
429   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
430                     MacroBuilder &Builder) const override {
431     // OpenBSD defines; list based off of gcc output
432 
433     Builder.defineMacro("__OpenBSD__");
434     DefineStd(Builder, "unix", Opts);
435     Builder.defineMacro("__ELF__");
436     if (Opts.POSIXThreads)
437       Builder.defineMacro("_REENTRANT");
438   }
439 public:
440   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
441     this->UserLabelPrefix = "";
442     this->TLSSupported = false;
443 
444       switch (Triple.getArch()) {
445         default:
446         case llvm::Triple::x86:
447         case llvm::Triple::x86_64:
448         case llvm::Triple::arm:
449         case llvm::Triple::sparc:
450           this->MCountName = "__mcount";
451           break;
452         case llvm::Triple::mips64:
453         case llvm::Triple::mips64el:
454         case llvm::Triple::ppc:
455         case llvm::Triple::sparcv9:
456           this->MCountName = "_mcount";
457           break;
458       }
459   }
460 };
461 
462 // Bitrig Target
463 template<typename Target>
464 class BitrigTargetInfo : public OSTargetInfo<Target> {
465 protected:
466   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
467                     MacroBuilder &Builder) const override {
468     // Bitrig defines; list based off of gcc output
469 
470     Builder.defineMacro("__Bitrig__");
471     DefineStd(Builder, "unix", Opts);
472     Builder.defineMacro("__ELF__");
473     if (Opts.POSIXThreads)
474       Builder.defineMacro("_REENTRANT");
475   }
476 public:
477   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
478     this->UserLabelPrefix = "";
479     this->MCountName = "__mcount";
480   }
481 };
482 
483 // PSP Target
484 template<typename Target>
485 class PSPTargetInfo : public OSTargetInfo<Target> {
486 protected:
487   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
488                     MacroBuilder &Builder) const override {
489     // PSP defines; list based on the output of the pspdev gcc toolchain.
490     Builder.defineMacro("PSP");
491     Builder.defineMacro("_PSP");
492     Builder.defineMacro("__psp__");
493     Builder.defineMacro("__ELF__");
494   }
495 public:
496   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
497     this->UserLabelPrefix = "";
498   }
499 };
500 
501 // PS3 PPU Target
502 template<typename Target>
503 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
504 protected:
505   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
506                     MacroBuilder &Builder) const override {
507     // PS3 PPU defines.
508     Builder.defineMacro("__PPC__");
509     Builder.defineMacro("__PPU__");
510     Builder.defineMacro("__CELLOS_LV2__");
511     Builder.defineMacro("__ELF__");
512     Builder.defineMacro("__LP32__");
513     Builder.defineMacro("_ARCH_PPC64");
514     Builder.defineMacro("__powerpc64__");
515   }
516 public:
517   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
518     this->UserLabelPrefix = "";
519     this->LongWidth = this->LongAlign = 32;
520     this->PointerWidth = this->PointerAlign = 32;
521     this->IntMaxType = TargetInfo::SignedLongLong;
522     this->Int64Type = TargetInfo::SignedLongLong;
523     this->SizeType = TargetInfo::UnsignedInt;
524     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
525   }
526 };
527 
528 // Solaris target
529 template<typename Target>
530 class SolarisTargetInfo : public OSTargetInfo<Target> {
531 protected:
532   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
533                     MacroBuilder &Builder) const override {
534     DefineStd(Builder, "sun", Opts);
535     DefineStd(Builder, "unix", Opts);
536     Builder.defineMacro("__ELF__");
537     Builder.defineMacro("__svr4__");
538     Builder.defineMacro("__SVR4");
539     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
540     // newer, but to 500 for everything else.  feature_test.h has a check to
541     // ensure that you are not using C99 with an old version of X/Open or C89
542     // with a new version.
543     if (Opts.C99)
544       Builder.defineMacro("_XOPEN_SOURCE", "600");
545     else
546       Builder.defineMacro("_XOPEN_SOURCE", "500");
547     if (Opts.CPlusPlus)
548       Builder.defineMacro("__C99FEATURES__");
549     Builder.defineMacro("_LARGEFILE_SOURCE");
550     Builder.defineMacro("_LARGEFILE64_SOURCE");
551     Builder.defineMacro("__EXTENSIONS__");
552     Builder.defineMacro("_REENTRANT");
553   }
554 public:
555   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
556     this->UserLabelPrefix = "";
557     this->WCharType = this->SignedInt;
558     // FIXME: WIntType should be SignedLong
559   }
560 };
561 
562 // Windows target
563 template<typename Target>
564 class WindowsTargetInfo : public OSTargetInfo<Target> {
565 protected:
566   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
567                     MacroBuilder &Builder) const override {
568     Builder.defineMacro("_WIN32");
569   }
570   void getVisualStudioDefines(const LangOptions &Opts,
571                               MacroBuilder &Builder) const {
572     if (Opts.CPlusPlus) {
573       if (Opts.RTTIData)
574         Builder.defineMacro("_CPPRTTI");
575 
576       if (Opts.Exceptions)
577         Builder.defineMacro("_CPPUNWIND");
578     }
579 
580     if (!Opts.CharIsSigned)
581       Builder.defineMacro("_CHAR_UNSIGNED");
582 
583     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
584     //        but it works for now.
585     if (Opts.POSIXThreads)
586       Builder.defineMacro("_MT");
587 
588     if (Opts.MSCompatibilityVersion) {
589       Builder.defineMacro("_MSC_VER",
590                           Twine(Opts.MSCompatibilityVersion / 100000));
591       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
592       // FIXME We cannot encode the revision information into 32-bits
593       Builder.defineMacro("_MSC_BUILD", Twine(1));
594     }
595 
596     if (Opts.MicrosoftExt) {
597       Builder.defineMacro("_MSC_EXTENSIONS");
598 
599       if (Opts.CPlusPlus11) {
600         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
601         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
602         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
603       }
604     }
605 
606     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
607   }
608 
609 public:
610   WindowsTargetInfo(const llvm::Triple &Triple)
611       : OSTargetInfo<Target>(Triple) {}
612 };
613 
614 template <typename Target>
615 class NaClTargetInfo : public OSTargetInfo<Target> {
616 protected:
617   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
618                     MacroBuilder &Builder) const override {
619     if (Opts.POSIXThreads)
620       Builder.defineMacro("_REENTRANT");
621     if (Opts.CPlusPlus)
622       Builder.defineMacro("_GNU_SOURCE");
623 
624     DefineStd(Builder, "unix", Opts);
625     Builder.defineMacro("__ELF__");
626     Builder.defineMacro("__native_client__");
627   }
628 
629 public:
630   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
631     this->UserLabelPrefix = "";
632     this->LongAlign = 32;
633     this->LongWidth = 32;
634     this->PointerAlign = 32;
635     this->PointerWidth = 32;
636     this->IntMaxType = TargetInfo::SignedLongLong;
637     this->Int64Type = TargetInfo::SignedLongLong;
638     this->DoubleAlign = 64;
639     this->LongDoubleWidth = 64;
640     this->LongDoubleAlign = 64;
641     this->LongLongWidth = 64;
642     this->LongLongAlign = 64;
643     this->SizeType = TargetInfo::UnsignedInt;
644     this->PtrDiffType = TargetInfo::SignedInt;
645     this->IntPtrType = TargetInfo::SignedInt;
646     // RegParmMax is inherited from the underlying architecture
647     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
648     if (Triple.getArch() == llvm::Triple::arm) {
649       this->DescriptionString =
650           "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
651     } else if (Triple.getArch() == llvm::Triple::x86) {
652       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
653     } else if (Triple.getArch() == llvm::Triple::x86_64) {
654       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
655     } else if (Triple.getArch() == llvm::Triple::mipsel) {
656       // Handled on mips' setDescriptionString.
657     } else {
658       assert(Triple.getArch() == llvm::Triple::le32);
659       this->DescriptionString = "e-p:32:32-i64:64";
660     }
661   }
662   typename Target::CallingConvCheckResult checkCallingConvention(
663       CallingConv CC) const override {
664     return CC == CC_PnaclCall ? Target::CCCR_OK :
665         Target::checkCallingConvention(CC);
666   }
667 };
668 } // end anonymous namespace.
669 
670 //===----------------------------------------------------------------------===//
671 // Specific target implementations.
672 //===----------------------------------------------------------------------===//
673 
674 namespace {
675 // PPC abstract base class
676 class PPCTargetInfo : public TargetInfo {
677   static const Builtin::Info BuiltinInfo[];
678   static const char * const GCCRegNames[];
679   static const TargetInfo::GCCRegAlias GCCRegAliases[];
680   std::string CPU;
681 
682   // Target cpu features.
683   bool HasVSX;
684   bool HasP8Vector;
685 
686 protected:
687   std::string ABI;
688 
689 public:
690   PPCTargetInfo(const llvm::Triple &Triple)
691     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
692     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
693     LongDoubleWidth = LongDoubleAlign = 128;
694     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
695   }
696 
697   /// \brief Flags for architecture specific defines.
698   typedef enum {
699     ArchDefineNone  = 0,
700     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
701     ArchDefinePpcgr = 1 << 1,
702     ArchDefinePpcsq = 1 << 2,
703     ArchDefine440   = 1 << 3,
704     ArchDefine603   = 1 << 4,
705     ArchDefine604   = 1 << 5,
706     ArchDefinePwr4  = 1 << 6,
707     ArchDefinePwr5  = 1 << 7,
708     ArchDefinePwr5x = 1 << 8,
709     ArchDefinePwr6  = 1 << 9,
710     ArchDefinePwr6x = 1 << 10,
711     ArchDefinePwr7  = 1 << 11,
712     ArchDefinePwr8  = 1 << 12,
713     ArchDefineA2    = 1 << 13,
714     ArchDefineA2q   = 1 << 14
715   } ArchDefineTypes;
716 
717   // Note: GCC recognizes the following additional cpus:
718   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
719   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
720   //  titan, rs64.
721   bool setCPU(const std::string &Name) override {
722     bool CPUKnown = llvm::StringSwitch<bool>(Name)
723       .Case("generic", true)
724       .Case("440", true)
725       .Case("450", true)
726       .Case("601", true)
727       .Case("602", true)
728       .Case("603", true)
729       .Case("603e", true)
730       .Case("603ev", true)
731       .Case("604", true)
732       .Case("604e", true)
733       .Case("620", true)
734       .Case("630", true)
735       .Case("g3", true)
736       .Case("7400", true)
737       .Case("g4", true)
738       .Case("7450", true)
739       .Case("g4+", true)
740       .Case("750", true)
741       .Case("970", true)
742       .Case("g5", true)
743       .Case("a2", true)
744       .Case("a2q", true)
745       .Case("e500mc", true)
746       .Case("e5500", true)
747       .Case("power3", true)
748       .Case("pwr3", true)
749       .Case("power4", true)
750       .Case("pwr4", true)
751       .Case("power5", true)
752       .Case("pwr5", true)
753       .Case("power5x", true)
754       .Case("pwr5x", true)
755       .Case("power6", true)
756       .Case("pwr6", true)
757       .Case("power6x", true)
758       .Case("pwr6x", true)
759       .Case("power7", true)
760       .Case("pwr7", true)
761       .Case("power8", true)
762       .Case("pwr8", true)
763       .Case("powerpc", true)
764       .Case("ppc", true)
765       .Case("powerpc64", true)
766       .Case("ppc64", true)
767       .Case("powerpc64le", true)
768       .Case("ppc64le", true)
769       .Default(false);
770 
771     if (CPUKnown)
772       CPU = Name;
773 
774     return CPUKnown;
775   }
776 
777 
778   StringRef getABI() const override { return ABI; }
779 
780   void getTargetBuiltins(const Builtin::Info *&Records,
781                          unsigned &NumRecords) const override {
782     Records = BuiltinInfo;
783     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
784   }
785 
786   bool isCLZForZeroUndef() const override { return false; }
787 
788   void getTargetDefines(const LangOptions &Opts,
789                         MacroBuilder &Builder) const override;
790 
791   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
792 
793   bool handleTargetFeatures(std::vector<std::string> &Features,
794                             DiagnosticsEngine &Diags) override;
795   bool hasFeature(StringRef Feature) const override;
796 
797   void getGCCRegNames(const char * const *&Names,
798                       unsigned &NumNames) const override;
799   void getGCCRegAliases(const GCCRegAlias *&Aliases,
800                         unsigned &NumAliases) const override;
801   bool validateAsmConstraint(const char *&Name,
802                              TargetInfo::ConstraintInfo &Info) const override {
803     switch (*Name) {
804     default: return false;
805     case 'O': // Zero
806       break;
807     case 'b': // Base register
808     case 'f': // Floating point register
809       Info.setAllowsRegister();
810       break;
811     // FIXME: The following are added to allow parsing.
812     // I just took a guess at what the actions should be.
813     // Also, is more specific checking needed?  I.e. specific registers?
814     case 'd': // Floating point register (containing 64-bit value)
815     case 'v': // Altivec vector register
816       Info.setAllowsRegister();
817       break;
818     case 'w':
819       switch (Name[1]) {
820         case 'd':// VSX vector register to hold vector double data
821         case 'f':// VSX vector register to hold vector float data
822         case 's':// VSX vector register to hold scalar float data
823         case 'a':// Any VSX register
824         case 'c':// An individual CR bit
825           break;
826         default:
827           return false;
828       }
829       Info.setAllowsRegister();
830       Name++; // Skip over 'w'.
831       break;
832     case 'h': // `MQ', `CTR', or `LINK' register
833     case 'q': // `MQ' register
834     case 'c': // `CTR' register
835     case 'l': // `LINK' register
836     case 'x': // `CR' register (condition register) number 0
837     case 'y': // `CR' register (condition register)
838     case 'z': // `XER[CA]' carry bit (part of the XER register)
839       Info.setAllowsRegister();
840       break;
841     case 'I': // Signed 16-bit constant
842     case 'J': // Unsigned 16-bit constant shifted left 16 bits
843               //  (use `L' instead for SImode constants)
844     case 'K': // Unsigned 16-bit constant
845     case 'L': // Signed 16-bit constant shifted left 16 bits
846     case 'M': // Constant larger than 31
847     case 'N': // Exact power of 2
848     case 'P': // Constant whose negation is a signed 16-bit constant
849     case 'G': // Floating point constant that can be loaded into a
850               // register with one instruction per word
851     case 'H': // Integer/Floating point constant that can be loaded
852               // into a register using three instructions
853       break;
854     case 'm': // Memory operand. Note that on PowerPC targets, m can
855               // include addresses that update the base register. It
856               // is therefore only safe to use `m' in an asm statement
857               // if that asm statement accesses the operand exactly once.
858               // The asm statement must also use `%U<opno>' as a
859               // placeholder for the "update" flag in the corresponding
860               // load or store instruction. For example:
861               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
862               // is correct but:
863               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
864               // is not. Use es rather than m if you don't want the base
865               // register to be updated.
866     case 'e':
867       if (Name[1] != 's')
868           return false;
869               // es: A "stable" memory operand; that is, one which does not
870               // include any automodification of the base register. Unlike
871               // `m', this constraint can be used in asm statements that
872               // might access the operand several times, or that might not
873               // access it at all.
874       Info.setAllowsMemory();
875       Name++; // Skip over 'e'.
876       break;
877     case 'Q': // Memory operand that is an offset from a register (it is
878               // usually better to use `m' or `es' in asm statements)
879     case 'Z': // Memory operand that is an indexed or indirect from a
880               // register (it is usually better to use `m' or `es' in
881               // asm statements)
882       Info.setAllowsMemory();
883       Info.setAllowsRegister();
884       break;
885     case 'R': // AIX TOC entry
886     case 'a': // Address operand that is an indexed or indirect from a
887               // register (`p' is preferable for asm statements)
888     case 'S': // Constant suitable as a 64-bit mask operand
889     case 'T': // Constant suitable as a 32-bit mask operand
890     case 'U': // System V Release 4 small data area reference
891     case 't': // AND masks that can be performed by two rldic{l, r}
892               // instructions
893     case 'W': // Vector constant that does not require memory
894     case 'j': // Vector constant that is all zeros.
895       break;
896     // End FIXME.
897     }
898     return true;
899   }
900   std::string convertConstraint(const char *&Constraint) const override {
901     std::string R;
902     switch (*Constraint) {
903     case 'e':
904     case 'w':
905       // Two-character constraint; add "^" hint for later parsing.
906       R = std::string("^") + std::string(Constraint, 2);
907       Constraint++;
908       break;
909     default:
910       return TargetInfo::convertConstraint(Constraint);
911     }
912     return R;
913   }
914   const char *getClobbers() const override {
915     return "";
916   }
917   int getEHDataRegisterNumber(unsigned RegNo) const override {
918     if (RegNo == 0) return 3;
919     if (RegNo == 1) return 4;
920     return -1;
921   }
922 };
923 
924 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
925 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
926 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
927                                               ALL_LANGUAGES },
928 #include "clang/Basic/BuiltinsPPC.def"
929 };
930 
931 /// handleTargetFeatures - Perform initialization based on the user
932 /// configured set of features.
933 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
934                                          DiagnosticsEngine &Diags) {
935   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
936     // Ignore disabled features.
937     if (Features[i][0] == '-')
938       continue;
939 
940     StringRef Feature = StringRef(Features[i]).substr(1);
941 
942     if (Feature == "vsx") {
943       HasVSX = true;
944       continue;
945     }
946 
947     if (Feature == "power8-vector") {
948       HasP8Vector = true;
949       continue;
950     }
951 
952     // TODO: Finish this list and add an assert that we've handled them
953     // all.
954   }
955 
956   return true;
957 }
958 
959 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
960 /// #defines that are not tied to a specific subtarget.
961 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
962                                      MacroBuilder &Builder) const {
963   // Target identification.
964   Builder.defineMacro("__ppc__");
965   Builder.defineMacro("__PPC__");
966   Builder.defineMacro("_ARCH_PPC");
967   Builder.defineMacro("__powerpc__");
968   Builder.defineMacro("__POWERPC__");
969   if (PointerWidth == 64) {
970     Builder.defineMacro("_ARCH_PPC64");
971     Builder.defineMacro("__powerpc64__");
972     Builder.defineMacro("__ppc64__");
973     Builder.defineMacro("__PPC64__");
974   }
975 
976   // Target properties.
977   if (getTriple().getArch() == llvm::Triple::ppc64le) {
978     Builder.defineMacro("_LITTLE_ENDIAN");
979   } else {
980     if (getTriple().getOS() != llvm::Triple::NetBSD &&
981         getTriple().getOS() != llvm::Triple::OpenBSD)
982       Builder.defineMacro("_BIG_ENDIAN");
983   }
984 
985   // ABI options.
986   if (ABI == "elfv1")
987     Builder.defineMacro("_CALL_ELF", "1");
988   if (ABI == "elfv2")
989     Builder.defineMacro("_CALL_ELF", "2");
990 
991   // Subtarget options.
992   Builder.defineMacro("__NATURAL_ALIGNMENT__");
993   Builder.defineMacro("__REGISTER_PREFIX__", "");
994 
995   // FIXME: Should be controlled by command line option.
996   if (LongDoubleWidth == 128)
997     Builder.defineMacro("__LONG_DOUBLE_128__");
998 
999   if (Opts.AltiVec) {
1000     Builder.defineMacro("__VEC__", "10206");
1001     Builder.defineMacro("__ALTIVEC__");
1002   }
1003 
1004   // CPU identification.
1005   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1006     .Case("440",   ArchDefineName)
1007     .Case("450",   ArchDefineName | ArchDefine440)
1008     .Case("601",   ArchDefineName)
1009     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1010     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1011     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1012     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1013     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1014     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1015     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1016     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1017     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1018     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1019     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1020     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1021                      | ArchDefinePpcsq)
1022     .Case("a2",    ArchDefineA2)
1023     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1024     .Case("pwr3",  ArchDefinePpcgr)
1025     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1026     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1027                      | ArchDefinePpcsq)
1028     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1029                      | ArchDefinePpcgr | ArchDefinePpcsq)
1030     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1031                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1033                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1034                      | ArchDefinePpcsq)
1035     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1036                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1037                      | ArchDefinePpcgr | ArchDefinePpcsq)
1038     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1039                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1040                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1041     .Case("power3",  ArchDefinePpcgr)
1042     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1043     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1044                        | ArchDefinePpcsq)
1045     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1046                        | ArchDefinePpcgr | ArchDefinePpcsq)
1047     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1048                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1049     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1050                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1051                        | ArchDefinePpcsq)
1052     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1053                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1054                        | ArchDefinePpcgr | ArchDefinePpcsq)
1055     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1056                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1057                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1058     .Default(ArchDefineNone);
1059 
1060   if (defs & ArchDefineName)
1061     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1062   if (defs & ArchDefinePpcgr)
1063     Builder.defineMacro("_ARCH_PPCGR");
1064   if (defs & ArchDefinePpcsq)
1065     Builder.defineMacro("_ARCH_PPCSQ");
1066   if (defs & ArchDefine440)
1067     Builder.defineMacro("_ARCH_440");
1068   if (defs & ArchDefine603)
1069     Builder.defineMacro("_ARCH_603");
1070   if (defs & ArchDefine604)
1071     Builder.defineMacro("_ARCH_604");
1072   if (defs & ArchDefinePwr4)
1073     Builder.defineMacro("_ARCH_PWR4");
1074   if (defs & ArchDefinePwr5)
1075     Builder.defineMacro("_ARCH_PWR5");
1076   if (defs & ArchDefinePwr5x)
1077     Builder.defineMacro("_ARCH_PWR5X");
1078   if (defs & ArchDefinePwr6)
1079     Builder.defineMacro("_ARCH_PWR6");
1080   if (defs & ArchDefinePwr6x)
1081     Builder.defineMacro("_ARCH_PWR6X");
1082   if (defs & ArchDefinePwr7)
1083     Builder.defineMacro("_ARCH_PWR7");
1084   if (defs & ArchDefinePwr8)
1085     Builder.defineMacro("_ARCH_PWR8");
1086   if (defs & ArchDefineA2)
1087     Builder.defineMacro("_ARCH_A2");
1088   if (defs & ArchDefineA2q) {
1089     Builder.defineMacro("_ARCH_A2Q");
1090     Builder.defineMacro("_ARCH_QP");
1091   }
1092 
1093   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1094     Builder.defineMacro("__bg__");
1095     Builder.defineMacro("__THW_BLUEGENE__");
1096     Builder.defineMacro("__bgq__");
1097     Builder.defineMacro("__TOS_BGQ__");
1098   }
1099 
1100   if (HasVSX)
1101     Builder.defineMacro("__VSX__");
1102   if (HasP8Vector)
1103     Builder.defineMacro("__POWER8_VECTOR__");
1104 
1105   // FIXME: The following are not yet generated here by Clang, but are
1106   //        generated by GCC:
1107   //
1108   //   _SOFT_FLOAT_
1109   //   __RECIP_PRECISION__
1110   //   __APPLE_ALTIVEC__
1111   //   __RECIP__
1112   //   __RECIPF__
1113   //   __RSQRTE__
1114   //   __RSQRTEF__
1115   //   _SOFT_DOUBLE_
1116   //   __NO_LWSYNC__
1117   //   __HAVE_BSWAP__
1118   //   __LONGDOUBLE128
1119   //   __CMODEL_MEDIUM__
1120   //   __CMODEL_LARGE__
1121   //   _CALL_SYSV
1122   //   _CALL_DARWIN
1123   //   __NO_FPRS__
1124 }
1125 
1126 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1127   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1128     .Case("7400", true)
1129     .Case("g4", true)
1130     .Case("7450", true)
1131     .Case("g4+", true)
1132     .Case("970", true)
1133     .Case("g5", true)
1134     .Case("pwr6", true)
1135     .Case("pwr7", true)
1136     .Case("pwr8", true)
1137     .Case("ppc64", true)
1138     .Case("ppc64le", true)
1139     .Default(false);
1140 
1141   Features["qpx"] = (CPU == "a2q");
1142 
1143   if (!ABI.empty())
1144     Features[ABI] = true;
1145 }
1146 
1147 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1148   return llvm::StringSwitch<bool>(Feature)
1149     .Case("powerpc", true)
1150     .Case("vsx", HasVSX)
1151     .Case("power8-vector", HasP8Vector)
1152     .Default(false);
1153 }
1154 
1155 const char * const PPCTargetInfo::GCCRegNames[] = {
1156   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1157   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1158   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1159   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1160   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1161   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1162   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1163   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1164   "mq", "lr", "ctr", "ap",
1165   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1166   "xer",
1167   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1168   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1169   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1170   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1171   "vrsave", "vscr",
1172   "spe_acc", "spefscr",
1173   "sfp"
1174 };
1175 
1176 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1177                                    unsigned &NumNames) const {
1178   Names = GCCRegNames;
1179   NumNames = llvm::array_lengthof(GCCRegNames);
1180 }
1181 
1182 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1183   // While some of these aliases do map to different registers
1184   // they still share the same register name.
1185   { { "0" }, "r0" },
1186   { { "1"}, "r1" },
1187   { { "2" }, "r2" },
1188   { { "3" }, "r3" },
1189   { { "4" }, "r4" },
1190   { { "5" }, "r5" },
1191   { { "6" }, "r6" },
1192   { { "7" }, "r7" },
1193   { { "8" }, "r8" },
1194   { { "9" }, "r9" },
1195   { { "10" }, "r10" },
1196   { { "11" }, "r11" },
1197   { { "12" }, "r12" },
1198   { { "13" }, "r13" },
1199   { { "14" }, "r14" },
1200   { { "15" }, "r15" },
1201   { { "16" }, "r16" },
1202   { { "17" }, "r17" },
1203   { { "18" }, "r18" },
1204   { { "19" }, "r19" },
1205   { { "20" }, "r20" },
1206   { { "21" }, "r21" },
1207   { { "22" }, "r22" },
1208   { { "23" }, "r23" },
1209   { { "24" }, "r24" },
1210   { { "25" }, "r25" },
1211   { { "26" }, "r26" },
1212   { { "27" }, "r27" },
1213   { { "28" }, "r28" },
1214   { { "29" }, "r29" },
1215   { { "30" }, "r30" },
1216   { { "31" }, "r31" },
1217   { { "fr0" }, "f0" },
1218   { { "fr1" }, "f1" },
1219   { { "fr2" }, "f2" },
1220   { { "fr3" }, "f3" },
1221   { { "fr4" }, "f4" },
1222   { { "fr5" }, "f5" },
1223   { { "fr6" }, "f6" },
1224   { { "fr7" }, "f7" },
1225   { { "fr8" }, "f8" },
1226   { { "fr9" }, "f9" },
1227   { { "fr10" }, "f10" },
1228   { { "fr11" }, "f11" },
1229   { { "fr12" }, "f12" },
1230   { { "fr13" }, "f13" },
1231   { { "fr14" }, "f14" },
1232   { { "fr15" }, "f15" },
1233   { { "fr16" }, "f16" },
1234   { { "fr17" }, "f17" },
1235   { { "fr18" }, "f18" },
1236   { { "fr19" }, "f19" },
1237   { { "fr20" }, "f20" },
1238   { { "fr21" }, "f21" },
1239   { { "fr22" }, "f22" },
1240   { { "fr23" }, "f23" },
1241   { { "fr24" }, "f24" },
1242   { { "fr25" }, "f25" },
1243   { { "fr26" }, "f26" },
1244   { { "fr27" }, "f27" },
1245   { { "fr28" }, "f28" },
1246   { { "fr29" }, "f29" },
1247   { { "fr30" }, "f30" },
1248   { { "fr31" }, "f31" },
1249   { { "cc" }, "cr0" },
1250 };
1251 
1252 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1253                                      unsigned &NumAliases) const {
1254   Aliases = GCCRegAliases;
1255   NumAliases = llvm::array_lengthof(GCCRegAliases);
1256 }
1257 } // end anonymous namespace.
1258 
1259 namespace {
1260 class PPC32TargetInfo : public PPCTargetInfo {
1261 public:
1262   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1263     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1264 
1265     switch (getTriple().getOS()) {
1266     case llvm::Triple::Linux:
1267     case llvm::Triple::FreeBSD:
1268     case llvm::Triple::NetBSD:
1269       SizeType = UnsignedInt;
1270       PtrDiffType = SignedInt;
1271       IntPtrType = SignedInt;
1272       break;
1273     default:
1274       break;
1275     }
1276 
1277     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1278       LongDoubleWidth = LongDoubleAlign = 64;
1279       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1280     }
1281 
1282     // PPC32 supports atomics up to 4 bytes.
1283     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1284   }
1285 
1286   BuiltinVaListKind getBuiltinVaListKind() const override {
1287     // This is the ELF definition, and is overridden by the Darwin sub-target
1288     return TargetInfo::PowerABIBuiltinVaList;
1289   }
1290 };
1291 } // end anonymous namespace.
1292 
1293 // Note: ABI differences may eventually require us to have a separate
1294 // TargetInfo for little endian.
1295 namespace {
1296 class PPC64TargetInfo : public PPCTargetInfo {
1297 public:
1298   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1299     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1300     IntMaxType = SignedLong;
1301     Int64Type = SignedLong;
1302 
1303     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1304       DescriptionString = "e-m:e-i64:64-n32:64";
1305       ABI = "elfv2";
1306     } else {
1307       DescriptionString = "E-m:e-i64:64-n32:64";
1308       ABI = "elfv1";
1309     }
1310 
1311     switch (getTriple().getOS()) {
1312     case llvm::Triple::FreeBSD:
1313       LongDoubleWidth = LongDoubleAlign = 64;
1314       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1315       break;
1316     case llvm::Triple::NetBSD:
1317       IntMaxType = SignedLongLong;
1318       Int64Type = SignedLongLong;
1319       break;
1320     default:
1321       break;
1322     }
1323 
1324     // PPC64 supports atomics up to 8 bytes.
1325     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1326   }
1327   BuiltinVaListKind getBuiltinVaListKind() const override {
1328     return TargetInfo::CharPtrBuiltinVaList;
1329   }
1330   // PPC64 Linux-specifc ABI options.
1331   bool setABI(const std::string &Name) override {
1332     if (Name == "elfv1" || Name == "elfv2") {
1333       ABI = Name;
1334       return true;
1335     }
1336     return false;
1337   }
1338 };
1339 } // end anonymous namespace.
1340 
1341 
1342 namespace {
1343 class DarwinPPC32TargetInfo :
1344   public DarwinTargetInfo<PPC32TargetInfo> {
1345 public:
1346   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1347       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1348     HasAlignMac68kSupport = true;
1349     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1350     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1351     LongLongAlign = 32;
1352     SuitableAlign = 128;
1353     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1354   }
1355   BuiltinVaListKind getBuiltinVaListKind() const override {
1356     return TargetInfo::CharPtrBuiltinVaList;
1357   }
1358 };
1359 
1360 class DarwinPPC64TargetInfo :
1361   public DarwinTargetInfo<PPC64TargetInfo> {
1362 public:
1363   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1364       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1365     HasAlignMac68kSupport = true;
1366     SuitableAlign = 128;
1367     DescriptionString = "E-m:o-i64:64-n32:64";
1368   }
1369 };
1370 } // end anonymous namespace.
1371 
1372 namespace {
1373   static const unsigned NVPTXAddrSpaceMap[] = {
1374     1,    // opencl_global
1375     3,    // opencl_local
1376     4,    // opencl_constant
1377     // FIXME: generic has to be added to the target
1378     0,    // opencl_generic
1379     1,    // cuda_device
1380     4,    // cuda_constant
1381     3,    // cuda_shared
1382   };
1383   class NVPTXTargetInfo : public TargetInfo {
1384     static const char * const GCCRegNames[];
1385     static const Builtin::Info BuiltinInfo[];
1386 
1387   // The GPU profiles supported by the NVPTX backend
1388   enum GPUKind {
1389     GK_NONE,
1390     GK_SM20,
1391     GK_SM21,
1392     GK_SM30,
1393     GK_SM35,
1394   } GPU;
1395 
1396   public:
1397     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1398       BigEndian = false;
1399       TLSSupported = false;
1400       LongWidth = LongAlign = 64;
1401       AddrSpaceMap = &NVPTXAddrSpaceMap;
1402       UseAddrSpaceMapMangling = true;
1403       // Define available target features
1404       // These must be defined in sorted order!
1405       NoAsmVariants = true;
1406       // Set the default GPU to sm20
1407       GPU = GK_SM20;
1408     }
1409     void getTargetDefines(const LangOptions &Opts,
1410                           MacroBuilder &Builder) const override {
1411       Builder.defineMacro("__PTX__");
1412       Builder.defineMacro("__NVPTX__");
1413       if (Opts.CUDAIsDevice) {
1414         // Set __CUDA_ARCH__ for the GPU specified.
1415         std::string CUDAArchCode;
1416         switch (GPU) {
1417         case GK_SM20:
1418           CUDAArchCode = "200";
1419           break;
1420         case GK_SM21:
1421           CUDAArchCode = "210";
1422           break;
1423         case GK_SM30:
1424           CUDAArchCode = "300";
1425           break;
1426         case GK_SM35:
1427           CUDAArchCode = "350";
1428           break;
1429         default:
1430           llvm_unreachable("Unhandled target CPU");
1431         }
1432         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1433       }
1434     }
1435     void getTargetBuiltins(const Builtin::Info *&Records,
1436                            unsigned &NumRecords) const override {
1437       Records = BuiltinInfo;
1438       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1439     }
1440     bool hasFeature(StringRef Feature) const override {
1441       return Feature == "ptx" || Feature == "nvptx";
1442     }
1443 
1444     void getGCCRegNames(const char * const *&Names,
1445                         unsigned &NumNames) const override;
1446     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1447                                   unsigned &NumAliases) const override {
1448       // No aliases.
1449       Aliases = nullptr;
1450       NumAliases = 0;
1451     }
1452     bool
1453     validateAsmConstraint(const char *&Name,
1454                           TargetInfo::ConstraintInfo &Info) const override {
1455       switch (*Name) {
1456       default: return false;
1457       case 'c':
1458       case 'h':
1459       case 'r':
1460       case 'l':
1461       case 'f':
1462       case 'd':
1463         Info.setAllowsRegister();
1464         return true;
1465       }
1466     }
1467     const char *getClobbers() const override {
1468       // FIXME: Is this really right?
1469       return "";
1470     }
1471     BuiltinVaListKind getBuiltinVaListKind() const override {
1472       // FIXME: implement
1473       return TargetInfo::CharPtrBuiltinVaList;
1474     }
1475     bool setCPU(const std::string &Name) override {
1476       GPU = llvm::StringSwitch<GPUKind>(Name)
1477                 .Case("sm_20", GK_SM20)
1478                 .Case("sm_21", GK_SM21)
1479                 .Case("sm_30", GK_SM30)
1480                 .Case("sm_35", GK_SM35)
1481                 .Default(GK_NONE);
1482 
1483       return GPU != GK_NONE;
1484     }
1485   };
1486 
1487   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1488 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1489 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1490                                               ALL_LANGUAGES },
1491 #include "clang/Basic/BuiltinsNVPTX.def"
1492   };
1493 
1494   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1495     "r0"
1496   };
1497 
1498   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1499                                      unsigned &NumNames) const {
1500     Names = GCCRegNames;
1501     NumNames = llvm::array_lengthof(GCCRegNames);
1502   }
1503 
1504   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1505   public:
1506     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1507       PointerWidth = PointerAlign = 32;
1508       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1509       IntPtrType = TargetInfo::SignedInt;
1510       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1511   }
1512   };
1513 
1514   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1515   public:
1516     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1517       PointerWidth = PointerAlign = 64;
1518       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1519       IntPtrType = TargetInfo::SignedLongLong;
1520       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1521   }
1522   };
1523 }
1524 
1525 namespace {
1526 
1527 static const unsigned R600AddrSpaceMap[] = {
1528   1,    // opencl_global
1529   3,    // opencl_local
1530   2,    // opencl_constant
1531   4,    // opencl_generic
1532   1,    // cuda_device
1533   2,    // cuda_constant
1534   3     // cuda_shared
1535 };
1536 
1537 // If you edit the description strings, make sure you update
1538 // getPointerWidthV().
1539 
1540 static const char *DescriptionStringR600 =
1541   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1542   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1543 
1544 static const char *DescriptionStringR600DoubleOps =
1545   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1546   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1547 
1548 static const char *DescriptionStringSI =
1549   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1550   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1551   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1552 
1553 class R600TargetInfo : public TargetInfo {
1554   static const Builtin::Info BuiltinInfo[];
1555 
1556   /// \brief The GPU profiles supported by the R600 target.
1557   enum GPUKind {
1558     GK_NONE,
1559     GK_R600,
1560     GK_R600_DOUBLE_OPS,
1561     GK_R700,
1562     GK_R700_DOUBLE_OPS,
1563     GK_EVERGREEN,
1564     GK_EVERGREEN_DOUBLE_OPS,
1565     GK_NORTHERN_ISLANDS,
1566     GK_CAYMAN,
1567     GK_SOUTHERN_ISLANDS,
1568     GK_SEA_ISLANDS
1569   } GPU;
1570 
1571 public:
1572   R600TargetInfo(const llvm::Triple &Triple)
1573       : TargetInfo(Triple), GPU(GK_R600) {
1574     DescriptionString = DescriptionStringR600;
1575     AddrSpaceMap = &R600AddrSpaceMap;
1576     UseAddrSpaceMapMangling = true;
1577   }
1578 
1579   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1580     if (GPU <= GK_CAYMAN)
1581       return 32;
1582 
1583     switch(AddrSpace) {
1584       default:
1585         return 64;
1586       case 0:
1587       case 3:
1588       case 5:
1589         return 32;
1590     }
1591   }
1592 
1593   const char * getClobbers() const override {
1594     return "";
1595   }
1596 
1597   void getGCCRegNames(const char * const *&Names,
1598                       unsigned &numNames) const override {
1599     Names = nullptr;
1600     numNames = 0;
1601   }
1602 
1603   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1604                         unsigned &NumAliases) const override {
1605     Aliases = nullptr;
1606     NumAliases = 0;
1607   }
1608 
1609   bool validateAsmConstraint(const char *&Name,
1610                              TargetInfo::ConstraintInfo &info) const override {
1611     return true;
1612   }
1613 
1614   void getTargetBuiltins(const Builtin::Info *&Records,
1615                          unsigned &NumRecords) const override {
1616     Records = BuiltinInfo;
1617     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1618   }
1619 
1620   void getTargetDefines(const LangOptions &Opts,
1621                         MacroBuilder &Builder) const override {
1622     Builder.defineMacro("__R600__");
1623   }
1624 
1625   BuiltinVaListKind getBuiltinVaListKind() const override {
1626     return TargetInfo::CharPtrBuiltinVaList;
1627   }
1628 
1629   bool setCPU(const std::string &Name) override {
1630     GPU = llvm::StringSwitch<GPUKind>(Name)
1631       .Case("r600" ,    GK_R600)
1632       .Case("rv610",    GK_R600)
1633       .Case("rv620",    GK_R600)
1634       .Case("rv630",    GK_R600)
1635       .Case("rv635",    GK_R600)
1636       .Case("rs780",    GK_R600)
1637       .Case("rs880",    GK_R600)
1638       .Case("rv670",    GK_R600_DOUBLE_OPS)
1639       .Case("rv710",    GK_R700)
1640       .Case("rv730",    GK_R700)
1641       .Case("rv740",    GK_R700_DOUBLE_OPS)
1642       .Case("rv770",    GK_R700_DOUBLE_OPS)
1643       .Case("palm",     GK_EVERGREEN)
1644       .Case("cedar",    GK_EVERGREEN)
1645       .Case("sumo",     GK_EVERGREEN)
1646       .Case("sumo2",    GK_EVERGREEN)
1647       .Case("redwood",  GK_EVERGREEN)
1648       .Case("juniper",  GK_EVERGREEN)
1649       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1650       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1651       .Case("barts",    GK_NORTHERN_ISLANDS)
1652       .Case("turks",    GK_NORTHERN_ISLANDS)
1653       .Case("caicos",   GK_NORTHERN_ISLANDS)
1654       .Case("cayman",   GK_CAYMAN)
1655       .Case("aruba",    GK_CAYMAN)
1656       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1657       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1658       .Case("verde",    GK_SOUTHERN_ISLANDS)
1659       .Case("oland",    GK_SOUTHERN_ISLANDS)
1660       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1661       .Case("bonaire",  GK_SEA_ISLANDS)
1662       .Case("kabini",   GK_SEA_ISLANDS)
1663       .Case("kaveri",   GK_SEA_ISLANDS)
1664       .Case("hawaii",   GK_SEA_ISLANDS)
1665       .Case("mullins",  GK_SEA_ISLANDS)
1666       .Default(GK_NONE);
1667 
1668     if (GPU == GK_NONE) {
1669       return false;
1670     }
1671 
1672     // Set the correct data layout
1673     switch (GPU) {
1674     case GK_NONE:
1675     case GK_R600:
1676     case GK_R700:
1677     case GK_EVERGREEN:
1678     case GK_NORTHERN_ISLANDS:
1679       DescriptionString = DescriptionStringR600;
1680       break;
1681     case GK_R600_DOUBLE_OPS:
1682     case GK_R700_DOUBLE_OPS:
1683     case GK_EVERGREEN_DOUBLE_OPS:
1684     case GK_CAYMAN:
1685       DescriptionString = DescriptionStringR600DoubleOps;
1686       break;
1687     case GK_SOUTHERN_ISLANDS:
1688     case GK_SEA_ISLANDS:
1689       DescriptionString = DescriptionStringSI;
1690       break;
1691     }
1692 
1693     return true;
1694   }
1695 };
1696 
1697 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1698 #define BUILTIN(ID, TYPE, ATTRS)                \
1699   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1700 #include "clang/Basic/BuiltinsR600.def"
1701 };
1702 
1703 } // end anonymous namespace
1704 
1705 namespace {
1706 // Namespace for x86 abstract base class
1707 const Builtin::Info BuiltinInfo[] = {
1708 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1709 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1710                                               ALL_LANGUAGES },
1711 #include "clang/Basic/BuiltinsX86.def"
1712 };
1713 
1714 static const char* const GCCRegNames[] = {
1715   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1716   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1717   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1718   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1719   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1720   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1721   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1722   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1723   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1724 };
1725 
1726 const TargetInfo::AddlRegName AddlRegNames[] = {
1727   { { "al", "ah", "eax", "rax" }, 0 },
1728   { { "bl", "bh", "ebx", "rbx" }, 3 },
1729   { { "cl", "ch", "ecx", "rcx" }, 2 },
1730   { { "dl", "dh", "edx", "rdx" }, 1 },
1731   { { "esi", "rsi" }, 4 },
1732   { { "edi", "rdi" }, 5 },
1733   { { "esp", "rsp" }, 7 },
1734   { { "ebp", "rbp" }, 6 },
1735 };
1736 
1737 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1738 // most of the implementation can be shared.
1739 class X86TargetInfo : public TargetInfo {
1740   enum X86SSEEnum {
1741     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1742   } SSELevel;
1743   enum MMX3DNowEnum {
1744     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1745   } MMX3DNowLevel;
1746   enum XOPEnum {
1747     NoXOP,
1748     SSE4A,
1749     FMA4,
1750     XOP
1751   } XOPLevel;
1752 
1753   bool HasAES;
1754   bool HasPCLMUL;
1755   bool HasLZCNT;
1756   bool HasRDRND;
1757   bool HasFSGSBASE;
1758   bool HasBMI;
1759   bool HasBMI2;
1760   bool HasPOPCNT;
1761   bool HasRTM;
1762   bool HasPRFCHW;
1763   bool HasRDSEED;
1764   bool HasADX;
1765   bool HasTBM;
1766   bool HasFMA;
1767   bool HasF16C;
1768   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1769       HasAVX512VL;
1770   bool HasSHA;
1771   bool HasCX16;
1772 
1773   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1774   ///
1775   /// Each enumeration represents a particular CPU supported by Clang. These
1776   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1777   enum CPUKind {
1778     CK_Generic,
1779 
1780     /// \name i386
1781     /// i386-generation processors.
1782     //@{
1783     CK_i386,
1784     //@}
1785 
1786     /// \name i486
1787     /// i486-generation processors.
1788     //@{
1789     CK_i486,
1790     CK_WinChipC6,
1791     CK_WinChip2,
1792     CK_C3,
1793     //@}
1794 
1795     /// \name i586
1796     /// i586-generation processors, P5 microarchitecture based.
1797     //@{
1798     CK_i586,
1799     CK_Pentium,
1800     CK_PentiumMMX,
1801     //@}
1802 
1803     /// \name i686
1804     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1805     //@{
1806     CK_i686,
1807     CK_PentiumPro,
1808     CK_Pentium2,
1809     CK_Pentium3,
1810     CK_Pentium3M,
1811     CK_PentiumM,
1812     CK_C3_2,
1813 
1814     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1815     /// Clang however has some logic to suport this.
1816     // FIXME: Warn, deprecate, and potentially remove this.
1817     CK_Yonah,
1818     //@}
1819 
1820     /// \name Netburst
1821     /// Netburst microarchitecture based processors.
1822     //@{
1823     CK_Pentium4,
1824     CK_Pentium4M,
1825     CK_Prescott,
1826     CK_Nocona,
1827     //@}
1828 
1829     /// \name Core
1830     /// Core microarchitecture based processors.
1831     //@{
1832     CK_Core2,
1833 
1834     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1835     /// codename which GCC no longer accepts as an option to -march, but Clang
1836     /// has some logic for recognizing it.
1837     // FIXME: Warn, deprecate, and potentially remove this.
1838     CK_Penryn,
1839     //@}
1840 
1841     /// \name Atom
1842     /// Atom processors
1843     //@{
1844     CK_Bonnell,
1845     CK_Silvermont,
1846     //@}
1847 
1848     /// \name Nehalem
1849     /// Nehalem microarchitecture based processors.
1850     CK_Nehalem,
1851 
1852     /// \name Westmere
1853     /// Westmere microarchitecture based processors.
1854     CK_Westmere,
1855 
1856     /// \name Sandy Bridge
1857     /// Sandy Bridge microarchitecture based processors.
1858     CK_SandyBridge,
1859 
1860     /// \name Ivy Bridge
1861     /// Ivy Bridge microarchitecture based processors.
1862     CK_IvyBridge,
1863 
1864     /// \name Haswell
1865     /// Haswell microarchitecture based processors.
1866     CK_Haswell,
1867 
1868     /// \name Broadwell
1869     /// Broadwell microarchitecture based processors.
1870     CK_Broadwell,
1871 
1872     /// \name Skylake
1873     /// Skylake microarchitecture based processors.
1874     CK_Skylake,
1875 
1876     /// \name Knights Landing
1877     /// Knights Landing processor.
1878     CK_KNL,
1879 
1880     /// \name K6
1881     /// K6 architecture processors.
1882     //@{
1883     CK_K6,
1884     CK_K6_2,
1885     CK_K6_3,
1886     //@}
1887 
1888     /// \name K7
1889     /// K7 architecture processors.
1890     //@{
1891     CK_Athlon,
1892     CK_AthlonThunderbird,
1893     CK_Athlon4,
1894     CK_AthlonXP,
1895     CK_AthlonMP,
1896     //@}
1897 
1898     /// \name K8
1899     /// K8 architecture processors.
1900     //@{
1901     CK_Athlon64,
1902     CK_Athlon64SSE3,
1903     CK_AthlonFX,
1904     CK_K8,
1905     CK_K8SSE3,
1906     CK_Opteron,
1907     CK_OpteronSSE3,
1908     CK_AMDFAM10,
1909     //@}
1910 
1911     /// \name Bobcat
1912     /// Bobcat architecture processors.
1913     //@{
1914     CK_BTVER1,
1915     CK_BTVER2,
1916     //@}
1917 
1918     /// \name Bulldozer
1919     /// Bulldozer architecture processors.
1920     //@{
1921     CK_BDVER1,
1922     CK_BDVER2,
1923     CK_BDVER3,
1924     CK_BDVER4,
1925     //@}
1926 
1927     /// This specification is deprecated and will be removed in the future.
1928     /// Users should prefer \see CK_K8.
1929     // FIXME: Warn on this when the CPU is set to it.
1930     //@{
1931     CK_x86_64,
1932     //@}
1933 
1934     /// \name Geode
1935     /// Geode processors.
1936     //@{
1937     CK_Geode
1938     //@}
1939   } CPU;
1940 
1941   enum FPMathKind {
1942     FP_Default,
1943     FP_SSE,
1944     FP_387
1945   } FPMath;
1946 
1947 public:
1948   X86TargetInfo(const llvm::Triple &Triple)
1949       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1950         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1951         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1952         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1953         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1954         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1955         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1956         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1957     BigEndian = false;
1958     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1959   }
1960   unsigned getFloatEvalMethod() const override {
1961     // X87 evaluates with 80 bits "long double" precision.
1962     return SSELevel == NoSSE ? 2 : 0;
1963   }
1964   void getTargetBuiltins(const Builtin::Info *&Records,
1965                                  unsigned &NumRecords) const override {
1966     Records = BuiltinInfo;
1967     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1968   }
1969   void getGCCRegNames(const char * const *&Names,
1970                       unsigned &NumNames) const override {
1971     Names = GCCRegNames;
1972     NumNames = llvm::array_lengthof(GCCRegNames);
1973   }
1974   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1975                         unsigned &NumAliases) const override {
1976     Aliases = nullptr;
1977     NumAliases = 0;
1978   }
1979   void getGCCAddlRegNames(const AddlRegName *&Names,
1980                           unsigned &NumNames) const override {
1981     Names = AddlRegNames;
1982     NumNames = llvm::array_lengthof(AddlRegNames);
1983   }
1984   bool validateAsmConstraint(const char *&Name,
1985                              TargetInfo::ConstraintInfo &info) const override;
1986 
1987   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1988 
1989   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1990 
1991   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1992 
1993   std::string convertConstraint(const char *&Constraint) const override;
1994   const char *getClobbers() const override {
1995     return "~{dirflag},~{fpsr},~{flags}";
1996   }
1997   void getTargetDefines(const LangOptions &Opts,
1998                         MacroBuilder &Builder) const override;
1999   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2000                           bool Enabled);
2001   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2002                           bool Enabled);
2003   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2004                           bool Enabled);
2005   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2006                          StringRef Name, bool Enabled) const override {
2007     setFeatureEnabledImpl(Features, Name, Enabled);
2008   }
2009   // This exists purely to cut down on the number of virtual calls in
2010   // getDefaultFeatures which calls this repeatedly.
2011   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2012                                     StringRef Name, bool Enabled);
2013   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2014   bool hasFeature(StringRef Feature) const override;
2015   bool handleTargetFeatures(std::vector<std::string> &Features,
2016                             DiagnosticsEngine &Diags) override;
2017   StringRef getABI() const override {
2018     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2019       return "avx";
2020     else if (getTriple().getArch() == llvm::Triple::x86 &&
2021              MMX3DNowLevel == NoMMX3DNow)
2022       return "no-mmx";
2023     return "";
2024   }
2025   bool setCPU(const std::string &Name) override {
2026     CPU = llvm::StringSwitch<CPUKind>(Name)
2027       .Case("i386", CK_i386)
2028       .Case("i486", CK_i486)
2029       .Case("winchip-c6", CK_WinChipC6)
2030       .Case("winchip2", CK_WinChip2)
2031       .Case("c3", CK_C3)
2032       .Case("i586", CK_i586)
2033       .Case("pentium", CK_Pentium)
2034       .Case("pentium-mmx", CK_PentiumMMX)
2035       .Case("i686", CK_i686)
2036       .Case("pentiumpro", CK_PentiumPro)
2037       .Case("pentium2", CK_Pentium2)
2038       .Case("pentium3", CK_Pentium3)
2039       .Case("pentium3m", CK_Pentium3M)
2040       .Case("pentium-m", CK_PentiumM)
2041       .Case("c3-2", CK_C3_2)
2042       .Case("yonah", CK_Yonah)
2043       .Case("pentium4", CK_Pentium4)
2044       .Case("pentium4m", CK_Pentium4M)
2045       .Case("prescott", CK_Prescott)
2046       .Case("nocona", CK_Nocona)
2047       .Case("core2", CK_Core2)
2048       .Case("penryn", CK_Penryn)
2049       .Case("bonnell", CK_Bonnell)
2050       .Case("atom", CK_Bonnell) // Legacy name.
2051       .Case("silvermont", CK_Silvermont)
2052       .Case("slm", CK_Silvermont) // Legacy name.
2053       .Case("nehalem", CK_Nehalem)
2054       .Case("corei7", CK_Nehalem) // Legacy name.
2055       .Case("westmere", CK_Westmere)
2056       .Case("sandybridge", CK_SandyBridge)
2057       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2058       .Case("ivybridge", CK_IvyBridge)
2059       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2060       .Case("haswell", CK_Haswell)
2061       .Case("core-avx2", CK_Haswell) // Legacy name.
2062       .Case("broadwell", CK_Broadwell)
2063       .Case("skylake", CK_Skylake)
2064       .Case("skx", CK_Skylake) // Legacy name.
2065       .Case("knl", CK_KNL)
2066       .Case("k6", CK_K6)
2067       .Case("k6-2", CK_K6_2)
2068       .Case("k6-3", CK_K6_3)
2069       .Case("athlon", CK_Athlon)
2070       .Case("athlon-tbird", CK_AthlonThunderbird)
2071       .Case("athlon-4", CK_Athlon4)
2072       .Case("athlon-xp", CK_AthlonXP)
2073       .Case("athlon-mp", CK_AthlonMP)
2074       .Case("athlon64", CK_Athlon64)
2075       .Case("athlon64-sse3", CK_Athlon64SSE3)
2076       .Case("athlon-fx", CK_AthlonFX)
2077       .Case("k8", CK_K8)
2078       .Case("k8-sse3", CK_K8SSE3)
2079       .Case("opteron", CK_Opteron)
2080       .Case("opteron-sse3", CK_OpteronSSE3)
2081       .Case("barcelona", CK_AMDFAM10)
2082       .Case("amdfam10", CK_AMDFAM10)
2083       .Case("btver1", CK_BTVER1)
2084       .Case("btver2", CK_BTVER2)
2085       .Case("bdver1", CK_BDVER1)
2086       .Case("bdver2", CK_BDVER2)
2087       .Case("bdver3", CK_BDVER3)
2088       .Case("bdver4", CK_BDVER4)
2089       .Case("x86-64", CK_x86_64)
2090       .Case("geode", CK_Geode)
2091       .Default(CK_Generic);
2092 
2093     // Perform any per-CPU checks necessary to determine if this CPU is
2094     // acceptable.
2095     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2096     // invalid without explaining *why*.
2097     switch (CPU) {
2098     case CK_Generic:
2099       // No processor selected!
2100       return false;
2101 
2102     case CK_i386:
2103     case CK_i486:
2104     case CK_WinChipC6:
2105     case CK_WinChip2:
2106     case CK_C3:
2107     case CK_i586:
2108     case CK_Pentium:
2109     case CK_PentiumMMX:
2110     case CK_i686:
2111     case CK_PentiumPro:
2112     case CK_Pentium2:
2113     case CK_Pentium3:
2114     case CK_Pentium3M:
2115     case CK_PentiumM:
2116     case CK_Yonah:
2117     case CK_C3_2:
2118     case CK_Pentium4:
2119     case CK_Pentium4M:
2120     case CK_Prescott:
2121     case CK_K6:
2122     case CK_K6_2:
2123     case CK_K6_3:
2124     case CK_Athlon:
2125     case CK_AthlonThunderbird:
2126     case CK_Athlon4:
2127     case CK_AthlonXP:
2128     case CK_AthlonMP:
2129     case CK_Geode:
2130       // Only accept certain architectures when compiling in 32-bit mode.
2131       if (getTriple().getArch() != llvm::Triple::x86)
2132         return false;
2133 
2134       // Fallthrough
2135     case CK_Nocona:
2136     case CK_Core2:
2137     case CK_Penryn:
2138     case CK_Bonnell:
2139     case CK_Silvermont:
2140     case CK_Nehalem:
2141     case CK_Westmere:
2142     case CK_SandyBridge:
2143     case CK_IvyBridge:
2144     case CK_Haswell:
2145     case CK_Broadwell:
2146     case CK_Skylake:
2147     case CK_KNL:
2148     case CK_Athlon64:
2149     case CK_Athlon64SSE3:
2150     case CK_AthlonFX:
2151     case CK_K8:
2152     case CK_K8SSE3:
2153     case CK_Opteron:
2154     case CK_OpteronSSE3:
2155     case CK_AMDFAM10:
2156     case CK_BTVER1:
2157     case CK_BTVER2:
2158     case CK_BDVER1:
2159     case CK_BDVER2:
2160     case CK_BDVER3:
2161     case CK_BDVER4:
2162     case CK_x86_64:
2163       return true;
2164     }
2165     llvm_unreachable("Unhandled CPU kind");
2166   }
2167 
2168   bool setFPMath(StringRef Name) override;
2169 
2170   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2171     // We accept all non-ARM calling conventions
2172     return (CC == CC_X86ThisCall ||
2173             CC == CC_X86FastCall ||
2174             CC == CC_X86StdCall ||
2175             CC == CC_X86VectorCall ||
2176             CC == CC_C ||
2177             CC == CC_X86Pascal ||
2178             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2179   }
2180 
2181   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2182     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2183   }
2184 };
2185 
2186 bool X86TargetInfo::setFPMath(StringRef Name) {
2187   if (Name == "387") {
2188     FPMath = FP_387;
2189     return true;
2190   }
2191   if (Name == "sse") {
2192     FPMath = FP_SSE;
2193     return true;
2194   }
2195   return false;
2196 }
2197 
2198 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2199   // FIXME: This *really* should not be here.
2200 
2201   // X86_64 always has SSE2.
2202   if (getTriple().getArch() == llvm::Triple::x86_64)
2203     setFeatureEnabledImpl(Features, "sse2", true);
2204 
2205   switch (CPU) {
2206   case CK_Generic:
2207   case CK_i386:
2208   case CK_i486:
2209   case CK_i586:
2210   case CK_Pentium:
2211   case CK_i686:
2212   case CK_PentiumPro:
2213     break;
2214   case CK_PentiumMMX:
2215   case CK_Pentium2:
2216   case CK_K6:
2217   case CK_WinChipC6:
2218     setFeatureEnabledImpl(Features, "mmx", true);
2219     break;
2220   case CK_Pentium3:
2221   case CK_Pentium3M:
2222   case CK_C3_2:
2223     setFeatureEnabledImpl(Features, "sse", true);
2224     break;
2225   case CK_PentiumM:
2226   case CK_Pentium4:
2227   case CK_Pentium4M:
2228   case CK_x86_64:
2229     setFeatureEnabledImpl(Features, "sse2", true);
2230     break;
2231   case CK_Yonah:
2232   case CK_Prescott:
2233   case CK_Nocona:
2234     setFeatureEnabledImpl(Features, "sse3", true);
2235     setFeatureEnabledImpl(Features, "cx16", true);
2236     break;
2237   case CK_Core2:
2238   case CK_Bonnell:
2239     setFeatureEnabledImpl(Features, "ssse3", true);
2240     setFeatureEnabledImpl(Features, "cx16", true);
2241     break;
2242   case CK_Penryn:
2243     setFeatureEnabledImpl(Features, "sse4.1", true);
2244     setFeatureEnabledImpl(Features, "cx16", true);
2245     break;
2246   case CK_Skylake:
2247     setFeatureEnabledImpl(Features, "avx512f", true);
2248     setFeatureEnabledImpl(Features, "avx512cd", true);
2249     setFeatureEnabledImpl(Features, "avx512dq", true);
2250     setFeatureEnabledImpl(Features, "avx512bw", true);
2251     setFeatureEnabledImpl(Features, "avx512vl", true);
2252     // FALLTHROUGH
2253   case CK_Broadwell:
2254     setFeatureEnabledImpl(Features, "rdseed", true);
2255     setFeatureEnabledImpl(Features, "adx", true);
2256     // FALLTHROUGH
2257   case CK_Haswell:
2258     setFeatureEnabledImpl(Features, "avx2", true);
2259     setFeatureEnabledImpl(Features, "lzcnt", true);
2260     setFeatureEnabledImpl(Features, "bmi", true);
2261     setFeatureEnabledImpl(Features, "bmi2", true);
2262     setFeatureEnabledImpl(Features, "rtm", true);
2263     setFeatureEnabledImpl(Features, "fma", true);
2264     // FALLTHROUGH
2265   case CK_IvyBridge:
2266     setFeatureEnabledImpl(Features, "rdrnd", true);
2267     setFeatureEnabledImpl(Features, "f16c", true);
2268     setFeatureEnabledImpl(Features, "fsgsbase", true);
2269     // FALLTHROUGH
2270   case CK_SandyBridge:
2271     setFeatureEnabledImpl(Features, "avx", true);
2272     // FALLTHROUGH
2273   case CK_Westmere:
2274   case CK_Silvermont:
2275     setFeatureEnabledImpl(Features, "aes", true);
2276     setFeatureEnabledImpl(Features, "pclmul", true);
2277     // FALLTHROUGH
2278   case CK_Nehalem:
2279     setFeatureEnabledImpl(Features, "sse4.2", true);
2280     setFeatureEnabledImpl(Features, "cx16", true);
2281     break;
2282   case CK_KNL:
2283     setFeatureEnabledImpl(Features, "avx512f", true);
2284     setFeatureEnabledImpl(Features, "avx512cd", true);
2285     setFeatureEnabledImpl(Features, "avx512er", true);
2286     setFeatureEnabledImpl(Features, "avx512pf", true);
2287     setFeatureEnabledImpl(Features, "rdseed", true);
2288     setFeatureEnabledImpl(Features, "adx", true);
2289     setFeatureEnabledImpl(Features, "lzcnt", true);
2290     setFeatureEnabledImpl(Features, "bmi", true);
2291     setFeatureEnabledImpl(Features, "bmi2", true);
2292     setFeatureEnabledImpl(Features, "rtm", true);
2293     setFeatureEnabledImpl(Features, "fma", true);
2294     setFeatureEnabledImpl(Features, "rdrnd", true);
2295     setFeatureEnabledImpl(Features, "f16c", true);
2296     setFeatureEnabledImpl(Features, "fsgsbase", true);
2297     setFeatureEnabledImpl(Features, "aes", true);
2298     setFeatureEnabledImpl(Features, "pclmul", true);
2299     setFeatureEnabledImpl(Features, "cx16", true);
2300     break;
2301   case CK_K6_2:
2302   case CK_K6_3:
2303   case CK_WinChip2:
2304   case CK_C3:
2305     setFeatureEnabledImpl(Features, "3dnow", true);
2306     break;
2307   case CK_Athlon:
2308   case CK_AthlonThunderbird:
2309   case CK_Geode:
2310     setFeatureEnabledImpl(Features, "3dnowa", true);
2311     break;
2312   case CK_Athlon4:
2313   case CK_AthlonXP:
2314   case CK_AthlonMP:
2315     setFeatureEnabledImpl(Features, "sse", true);
2316     setFeatureEnabledImpl(Features, "3dnowa", true);
2317     break;
2318   case CK_K8:
2319   case CK_Opteron:
2320   case CK_Athlon64:
2321   case CK_AthlonFX:
2322     setFeatureEnabledImpl(Features, "sse2", true);
2323     setFeatureEnabledImpl(Features, "3dnowa", true);
2324     break;
2325   case CK_AMDFAM10:
2326     setFeatureEnabledImpl(Features, "sse4a", true);
2327     setFeatureEnabledImpl(Features, "lzcnt", true);
2328     setFeatureEnabledImpl(Features, "popcnt", true);
2329     // FALLTHROUGH
2330   case CK_K8SSE3:
2331   case CK_OpteronSSE3:
2332   case CK_Athlon64SSE3:
2333     setFeatureEnabledImpl(Features, "sse3", true);
2334     setFeatureEnabledImpl(Features, "3dnowa", true);
2335     break;
2336   case CK_BTVER2:
2337     setFeatureEnabledImpl(Features, "avx", true);
2338     setFeatureEnabledImpl(Features, "aes", true);
2339     setFeatureEnabledImpl(Features, "pclmul", true);
2340     setFeatureEnabledImpl(Features, "bmi", true);
2341     setFeatureEnabledImpl(Features, "f16c", true);
2342     // FALLTHROUGH
2343   case CK_BTVER1:
2344     setFeatureEnabledImpl(Features, "ssse3", true);
2345     setFeatureEnabledImpl(Features, "sse4a", true);
2346     setFeatureEnabledImpl(Features, "lzcnt", true);
2347     setFeatureEnabledImpl(Features, "popcnt", true);
2348     setFeatureEnabledImpl(Features, "prfchw", true);
2349     setFeatureEnabledImpl(Features, "cx16", true);
2350     break;
2351   case CK_BDVER4:
2352     setFeatureEnabledImpl(Features, "avx2", true);
2353     setFeatureEnabledImpl(Features, "bmi2", true);
2354     // FALLTHROUGH
2355   case CK_BDVER3:
2356     setFeatureEnabledImpl(Features, "fsgsbase", true);
2357     // FALLTHROUGH
2358   case CK_BDVER2:
2359     setFeatureEnabledImpl(Features, "bmi", true);
2360     setFeatureEnabledImpl(Features, "fma", true);
2361     setFeatureEnabledImpl(Features, "f16c", true);
2362     setFeatureEnabledImpl(Features, "tbm", true);
2363     // FALLTHROUGH
2364   case CK_BDVER1:
2365     // xop implies avx, sse4a and fma4.
2366     setFeatureEnabledImpl(Features, "xop", true);
2367     setFeatureEnabledImpl(Features, "lzcnt", true);
2368     setFeatureEnabledImpl(Features, "aes", true);
2369     setFeatureEnabledImpl(Features, "pclmul", true);
2370     setFeatureEnabledImpl(Features, "prfchw", true);
2371     setFeatureEnabledImpl(Features, "cx16", true);
2372     break;
2373   }
2374 }
2375 
2376 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2377                                 X86SSEEnum Level, bool Enabled) {
2378   if (Enabled) {
2379     switch (Level) {
2380     case AVX512F:
2381       Features["avx512f"] = true;
2382     case AVX2:
2383       Features["avx2"] = true;
2384     case AVX:
2385       Features["avx"] = true;
2386     case SSE42:
2387       Features["sse4.2"] = true;
2388     case SSE41:
2389       Features["sse4.1"] = true;
2390     case SSSE3:
2391       Features["ssse3"] = true;
2392     case SSE3:
2393       Features["sse3"] = true;
2394     case SSE2:
2395       Features["sse2"] = true;
2396     case SSE1:
2397       Features["sse"] = true;
2398     case NoSSE:
2399       break;
2400     }
2401     return;
2402   }
2403 
2404   switch (Level) {
2405   case NoSSE:
2406   case SSE1:
2407     Features["sse"] = false;
2408   case SSE2:
2409     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2410       Features["sha"] = false;
2411   case SSE3:
2412     Features["sse3"] = false;
2413     setXOPLevel(Features, NoXOP, false);
2414   case SSSE3:
2415     Features["ssse3"] = false;
2416   case SSE41:
2417     Features["sse4.1"] = false;
2418   case SSE42:
2419     Features["sse4.2"] = false;
2420   case AVX:
2421     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2422     setXOPLevel(Features, FMA4, false);
2423   case AVX2:
2424     Features["avx2"] = false;
2425   case AVX512F:
2426     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2427       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2428       Features["avx512vl"] = false;
2429   }
2430 }
2431 
2432 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2433                                 MMX3DNowEnum Level, bool Enabled) {
2434   if (Enabled) {
2435     switch (Level) {
2436     case AMD3DNowAthlon:
2437       Features["3dnowa"] = true;
2438     case AMD3DNow:
2439       Features["3dnow"] = true;
2440     case MMX:
2441       Features["mmx"] = true;
2442     case NoMMX3DNow:
2443       break;
2444     }
2445     return;
2446   }
2447 
2448   switch (Level) {
2449   case NoMMX3DNow:
2450   case MMX:
2451     Features["mmx"] = false;
2452   case AMD3DNow:
2453     Features["3dnow"] = false;
2454   case AMD3DNowAthlon:
2455     Features["3dnowa"] = false;
2456   }
2457 }
2458 
2459 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2460                                 bool Enabled) {
2461   if (Enabled) {
2462     switch (Level) {
2463     case XOP:
2464       Features["xop"] = true;
2465     case FMA4:
2466       Features["fma4"] = true;
2467       setSSELevel(Features, AVX, true);
2468     case SSE4A:
2469       Features["sse4a"] = true;
2470       setSSELevel(Features, SSE3, true);
2471     case NoXOP:
2472       break;
2473     }
2474     return;
2475   }
2476 
2477   switch (Level) {
2478   case NoXOP:
2479   case SSE4A:
2480     Features["sse4a"] = false;
2481   case FMA4:
2482     Features["fma4"] = false;
2483   case XOP:
2484     Features["xop"] = false;
2485   }
2486 }
2487 
2488 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2489                                           StringRef Name, bool Enabled) {
2490   // FIXME: This *really* should not be here.  We need some way of translating
2491   // options into llvm subtarget features.
2492   if (Name == "sse4")
2493     Name = "sse4.2";
2494 
2495   Features[Name] = Enabled;
2496 
2497   if (Name == "mmx") {
2498     setMMXLevel(Features, MMX, Enabled);
2499   } else if (Name == "sse") {
2500     setSSELevel(Features, SSE1, Enabled);
2501   } else if (Name == "sse2") {
2502     setSSELevel(Features, SSE2, Enabled);
2503   } else if (Name == "sse3") {
2504     setSSELevel(Features, SSE3, Enabled);
2505   } else if (Name == "ssse3") {
2506     setSSELevel(Features, SSSE3, Enabled);
2507   } else if (Name == "sse4.2") {
2508     setSSELevel(Features, SSE42, Enabled);
2509   } else if (Name == "sse4.1") {
2510     setSSELevel(Features, SSE41, Enabled);
2511   } else if (Name == "3dnow") {
2512     setMMXLevel(Features, AMD3DNow, Enabled);
2513   } else if (Name == "3dnowa") {
2514     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2515   } else if (Name == "aes") {
2516     if (Enabled)
2517       setSSELevel(Features, SSE2, Enabled);
2518   } else if (Name == "pclmul") {
2519     if (Enabled)
2520       setSSELevel(Features, SSE2, Enabled);
2521   } else if (Name == "avx") {
2522     setSSELevel(Features, AVX, Enabled);
2523   } else if (Name == "avx2") {
2524     setSSELevel(Features, AVX2, Enabled);
2525   } else if (Name == "avx512f") {
2526     setSSELevel(Features, AVX512F, Enabled);
2527   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2528           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2529     if (Enabled)
2530       setSSELevel(Features, AVX512F, Enabled);
2531   } else if (Name == "fma") {
2532     if (Enabled)
2533       setSSELevel(Features, AVX, Enabled);
2534   } else if (Name == "fma4") {
2535     setXOPLevel(Features, FMA4, Enabled);
2536   } else if (Name == "xop") {
2537     setXOPLevel(Features, XOP, Enabled);
2538   } else if (Name == "sse4a") {
2539     setXOPLevel(Features, SSE4A, Enabled);
2540   } else if (Name == "f16c") {
2541     if (Enabled)
2542       setSSELevel(Features, AVX, Enabled);
2543   } else if (Name == "sha") {
2544     if (Enabled)
2545       setSSELevel(Features, SSE2, Enabled);
2546   }
2547 }
2548 
2549 /// handleTargetFeatures - Perform initialization based on the user
2550 /// configured set of features.
2551 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2552                                          DiagnosticsEngine &Diags) {
2553   // Remember the maximum enabled sselevel.
2554   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2555     // Ignore disabled features.
2556     if (Features[i][0] == '-')
2557       continue;
2558 
2559     StringRef Feature = StringRef(Features[i]).substr(1);
2560 
2561     if (Feature == "aes") {
2562       HasAES = true;
2563       continue;
2564     }
2565 
2566     if (Feature == "pclmul") {
2567       HasPCLMUL = true;
2568       continue;
2569     }
2570 
2571     if (Feature == "lzcnt") {
2572       HasLZCNT = true;
2573       continue;
2574     }
2575 
2576     if (Feature == "rdrnd") {
2577       HasRDRND = true;
2578       continue;
2579     }
2580 
2581     if (Feature == "fsgsbase") {
2582       HasFSGSBASE = true;
2583       continue;
2584     }
2585 
2586     if (Feature == "bmi") {
2587       HasBMI = true;
2588       continue;
2589     }
2590 
2591     if (Feature == "bmi2") {
2592       HasBMI2 = true;
2593       continue;
2594     }
2595 
2596     if (Feature == "popcnt") {
2597       HasPOPCNT = true;
2598       continue;
2599     }
2600 
2601     if (Feature == "rtm") {
2602       HasRTM = true;
2603       continue;
2604     }
2605 
2606     if (Feature == "prfchw") {
2607       HasPRFCHW = true;
2608       continue;
2609     }
2610 
2611     if (Feature == "rdseed") {
2612       HasRDSEED = true;
2613       continue;
2614     }
2615 
2616     if (Feature == "adx") {
2617       HasADX = true;
2618       continue;
2619     }
2620 
2621     if (Feature == "tbm") {
2622       HasTBM = true;
2623       continue;
2624     }
2625 
2626     if (Feature == "fma") {
2627       HasFMA = true;
2628       continue;
2629     }
2630 
2631     if (Feature == "f16c") {
2632       HasF16C = true;
2633       continue;
2634     }
2635 
2636     if (Feature == "avx512cd") {
2637       HasAVX512CD = true;
2638       continue;
2639     }
2640 
2641     if (Feature == "avx512er") {
2642       HasAVX512ER = true;
2643       continue;
2644     }
2645 
2646     if (Feature == "avx512pf") {
2647       HasAVX512PF = true;
2648       continue;
2649     }
2650 
2651     if (Feature == "avx512dq") {
2652       HasAVX512DQ = true;
2653       continue;
2654     }
2655 
2656     if (Feature == "avx512bw") {
2657       HasAVX512BW = true;
2658       continue;
2659     }
2660 
2661     if (Feature == "avx512vl") {
2662       HasAVX512VL = true;
2663       continue;
2664     }
2665 
2666     if (Feature == "sha") {
2667       HasSHA = true;
2668       continue;
2669     }
2670 
2671     if (Feature == "cx16") {
2672       HasCX16 = true;
2673       continue;
2674     }
2675 
2676     assert(Features[i][0] == '+' && "Invalid target feature!");
2677     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2678       .Case("avx512f", AVX512F)
2679       .Case("avx2", AVX2)
2680       .Case("avx", AVX)
2681       .Case("sse4.2", SSE42)
2682       .Case("sse4.1", SSE41)
2683       .Case("ssse3", SSSE3)
2684       .Case("sse3", SSE3)
2685       .Case("sse2", SSE2)
2686       .Case("sse", SSE1)
2687       .Default(NoSSE);
2688     SSELevel = std::max(SSELevel, Level);
2689 
2690     MMX3DNowEnum ThreeDNowLevel =
2691       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2692         .Case("3dnowa", AMD3DNowAthlon)
2693         .Case("3dnow", AMD3DNow)
2694         .Case("mmx", MMX)
2695         .Default(NoMMX3DNow);
2696     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2697 
2698     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2699         .Case("xop", XOP)
2700         .Case("fma4", FMA4)
2701         .Case("sse4a", SSE4A)
2702         .Default(NoXOP);
2703     XOPLevel = std::max(XOPLevel, XLevel);
2704   }
2705 
2706   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2707   // Can't do this earlier because we need to be able to explicitly enable
2708   // popcnt and still disable sse4.2.
2709   if (!HasPOPCNT && SSELevel >= SSE42 &&
2710       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2711     HasPOPCNT = true;
2712     Features.push_back("+popcnt");
2713   }
2714 
2715   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2716   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2717       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2718     HasPRFCHW = true;
2719     Features.push_back("+prfchw");
2720   }
2721 
2722   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2723   // matches the selected sse level.
2724   if (FPMath == FP_SSE && SSELevel < SSE1) {
2725     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2726     return false;
2727   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2728     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2729     return false;
2730   }
2731 
2732   // Don't tell the backend if we're turning off mmx; it will end up disabling
2733   // SSE, which we don't want.
2734   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2735   // then enable MMX.
2736   std::vector<std::string>::iterator it;
2737   it = std::find(Features.begin(), Features.end(), "-mmx");
2738   if (it != Features.end())
2739     Features.erase(it);
2740   else if (SSELevel > NoSSE)
2741     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2742   return true;
2743 }
2744 
2745 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2746 /// definitions for this particular subtarget.
2747 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2748                                      MacroBuilder &Builder) const {
2749   // Target identification.
2750   if (getTriple().getArch() == llvm::Triple::x86_64) {
2751     Builder.defineMacro("__amd64__");
2752     Builder.defineMacro("__amd64");
2753     Builder.defineMacro("__x86_64");
2754     Builder.defineMacro("__x86_64__");
2755     if (getTriple().getArchName() == "x86_64h") {
2756       Builder.defineMacro("__x86_64h");
2757       Builder.defineMacro("__x86_64h__");
2758     }
2759   } else {
2760     DefineStd(Builder, "i386", Opts);
2761   }
2762 
2763   // Subtarget options.
2764   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2765   // truly should be based on -mtune options.
2766   switch (CPU) {
2767   case CK_Generic:
2768     break;
2769   case CK_i386:
2770     // The rest are coming from the i386 define above.
2771     Builder.defineMacro("__tune_i386__");
2772     break;
2773   case CK_i486:
2774   case CK_WinChipC6:
2775   case CK_WinChip2:
2776   case CK_C3:
2777     defineCPUMacros(Builder, "i486");
2778     break;
2779   case CK_PentiumMMX:
2780     Builder.defineMacro("__pentium_mmx__");
2781     Builder.defineMacro("__tune_pentium_mmx__");
2782     // Fallthrough
2783   case CK_i586:
2784   case CK_Pentium:
2785     defineCPUMacros(Builder, "i586");
2786     defineCPUMacros(Builder, "pentium");
2787     break;
2788   case CK_Pentium3:
2789   case CK_Pentium3M:
2790   case CK_PentiumM:
2791     Builder.defineMacro("__tune_pentium3__");
2792     // Fallthrough
2793   case CK_Pentium2:
2794   case CK_C3_2:
2795     Builder.defineMacro("__tune_pentium2__");
2796     // Fallthrough
2797   case CK_PentiumPro:
2798     Builder.defineMacro("__tune_i686__");
2799     Builder.defineMacro("__tune_pentiumpro__");
2800     // Fallthrough
2801   case CK_i686:
2802     Builder.defineMacro("__i686");
2803     Builder.defineMacro("__i686__");
2804     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2805     Builder.defineMacro("__pentiumpro");
2806     Builder.defineMacro("__pentiumpro__");
2807     break;
2808   case CK_Pentium4:
2809   case CK_Pentium4M:
2810     defineCPUMacros(Builder, "pentium4");
2811     break;
2812   case CK_Yonah:
2813   case CK_Prescott:
2814   case CK_Nocona:
2815     defineCPUMacros(Builder, "nocona");
2816     break;
2817   case CK_Core2:
2818   case CK_Penryn:
2819     defineCPUMacros(Builder, "core2");
2820     break;
2821   case CK_Bonnell:
2822     defineCPUMacros(Builder, "atom");
2823     break;
2824   case CK_Silvermont:
2825     defineCPUMacros(Builder, "slm");
2826     break;
2827   case CK_Nehalem:
2828   case CK_Westmere:
2829   case CK_SandyBridge:
2830   case CK_IvyBridge:
2831   case CK_Haswell:
2832   case CK_Broadwell:
2833     // FIXME: Historically, we defined this legacy name, it would be nice to
2834     // remove it at some point. We've never exposed fine-grained names for
2835     // recent primary x86 CPUs, and we should keep it that way.
2836     defineCPUMacros(Builder, "corei7");
2837     break;
2838   case CK_Skylake:
2839     // FIXME: Historically, we defined this legacy name, it would be nice to
2840     // remove it at some point. This is the only fine-grained CPU macro in the
2841     // main intel CPU line, and it would be better to not have these and force
2842     // people to use ISA macros.
2843     defineCPUMacros(Builder, "skx");
2844     break;
2845   case CK_KNL:
2846     defineCPUMacros(Builder, "knl");
2847     break;
2848   case CK_K6_2:
2849     Builder.defineMacro("__k6_2__");
2850     Builder.defineMacro("__tune_k6_2__");
2851     // Fallthrough
2852   case CK_K6_3:
2853     if (CPU != CK_K6_2) {  // In case of fallthrough
2854       // FIXME: GCC may be enabling these in cases where some other k6
2855       // architecture is specified but -m3dnow is explicitly provided. The
2856       // exact semantics need to be determined and emulated here.
2857       Builder.defineMacro("__k6_3__");
2858       Builder.defineMacro("__tune_k6_3__");
2859     }
2860     // Fallthrough
2861   case CK_K6:
2862     defineCPUMacros(Builder, "k6");
2863     break;
2864   case CK_Athlon:
2865   case CK_AthlonThunderbird:
2866   case CK_Athlon4:
2867   case CK_AthlonXP:
2868   case CK_AthlonMP:
2869     defineCPUMacros(Builder, "athlon");
2870     if (SSELevel != NoSSE) {
2871       Builder.defineMacro("__athlon_sse__");
2872       Builder.defineMacro("__tune_athlon_sse__");
2873     }
2874     break;
2875   case CK_K8:
2876   case CK_K8SSE3:
2877   case CK_x86_64:
2878   case CK_Opteron:
2879   case CK_OpteronSSE3:
2880   case CK_Athlon64:
2881   case CK_Athlon64SSE3:
2882   case CK_AthlonFX:
2883     defineCPUMacros(Builder, "k8");
2884     break;
2885   case CK_AMDFAM10:
2886     defineCPUMacros(Builder, "amdfam10");
2887     break;
2888   case CK_BTVER1:
2889     defineCPUMacros(Builder, "btver1");
2890     break;
2891   case CK_BTVER2:
2892     defineCPUMacros(Builder, "btver2");
2893     break;
2894   case CK_BDVER1:
2895     defineCPUMacros(Builder, "bdver1");
2896     break;
2897   case CK_BDVER2:
2898     defineCPUMacros(Builder, "bdver2");
2899     break;
2900   case CK_BDVER3:
2901     defineCPUMacros(Builder, "bdver3");
2902     break;
2903   case CK_BDVER4:
2904     defineCPUMacros(Builder, "bdver4");
2905     break;
2906   case CK_Geode:
2907     defineCPUMacros(Builder, "geode");
2908     break;
2909   }
2910 
2911   // Target properties.
2912   Builder.defineMacro("__REGISTER_PREFIX__", "");
2913 
2914   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2915   // functions in glibc header files that use FP Stack inline asm which the
2916   // backend can't deal with (PR879).
2917   Builder.defineMacro("__NO_MATH_INLINES");
2918 
2919   if (HasAES)
2920     Builder.defineMacro("__AES__");
2921 
2922   if (HasPCLMUL)
2923     Builder.defineMacro("__PCLMUL__");
2924 
2925   if (HasLZCNT)
2926     Builder.defineMacro("__LZCNT__");
2927 
2928   if (HasRDRND)
2929     Builder.defineMacro("__RDRND__");
2930 
2931   if (HasFSGSBASE)
2932     Builder.defineMacro("__FSGSBASE__");
2933 
2934   if (HasBMI)
2935     Builder.defineMacro("__BMI__");
2936 
2937   if (HasBMI2)
2938     Builder.defineMacro("__BMI2__");
2939 
2940   if (HasPOPCNT)
2941     Builder.defineMacro("__POPCNT__");
2942 
2943   if (HasRTM)
2944     Builder.defineMacro("__RTM__");
2945 
2946   if (HasPRFCHW)
2947     Builder.defineMacro("__PRFCHW__");
2948 
2949   if (HasRDSEED)
2950     Builder.defineMacro("__RDSEED__");
2951 
2952   if (HasADX)
2953     Builder.defineMacro("__ADX__");
2954 
2955   if (HasTBM)
2956     Builder.defineMacro("__TBM__");
2957 
2958   switch (XOPLevel) {
2959   case XOP:
2960     Builder.defineMacro("__XOP__");
2961   case FMA4:
2962     Builder.defineMacro("__FMA4__");
2963   case SSE4A:
2964     Builder.defineMacro("__SSE4A__");
2965   case NoXOP:
2966     break;
2967   }
2968 
2969   if (HasFMA)
2970     Builder.defineMacro("__FMA__");
2971 
2972   if (HasF16C)
2973     Builder.defineMacro("__F16C__");
2974 
2975   if (HasAVX512CD)
2976     Builder.defineMacro("__AVX512CD__");
2977   if (HasAVX512ER)
2978     Builder.defineMacro("__AVX512ER__");
2979   if (HasAVX512PF)
2980     Builder.defineMacro("__AVX512PF__");
2981   if (HasAVX512DQ)
2982     Builder.defineMacro("__AVX512DQ__");
2983   if (HasAVX512BW)
2984     Builder.defineMacro("__AVX512BW__");
2985   if (HasAVX512VL)
2986     Builder.defineMacro("__AVX512VL__");
2987 
2988   if (HasSHA)
2989     Builder.defineMacro("__SHA__");
2990 
2991   if (HasCX16)
2992     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2993 
2994   // Each case falls through to the previous one here.
2995   switch (SSELevel) {
2996   case AVX512F:
2997     Builder.defineMacro("__AVX512F__");
2998   case AVX2:
2999     Builder.defineMacro("__AVX2__");
3000   case AVX:
3001     Builder.defineMacro("__AVX__");
3002   case SSE42:
3003     Builder.defineMacro("__SSE4_2__");
3004   case SSE41:
3005     Builder.defineMacro("__SSE4_1__");
3006   case SSSE3:
3007     Builder.defineMacro("__SSSE3__");
3008   case SSE3:
3009     Builder.defineMacro("__SSE3__");
3010   case SSE2:
3011     Builder.defineMacro("__SSE2__");
3012     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3013   case SSE1:
3014     Builder.defineMacro("__SSE__");
3015     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3016   case NoSSE:
3017     break;
3018   }
3019 
3020   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3021     switch (SSELevel) {
3022     case AVX512F:
3023     case AVX2:
3024     case AVX:
3025     case SSE42:
3026     case SSE41:
3027     case SSSE3:
3028     case SSE3:
3029     case SSE2:
3030       Builder.defineMacro("_M_IX86_FP", Twine(2));
3031       break;
3032     case SSE1:
3033       Builder.defineMacro("_M_IX86_FP", Twine(1));
3034       break;
3035     default:
3036       Builder.defineMacro("_M_IX86_FP", Twine(0));
3037     }
3038   }
3039 
3040   // Each case falls through to the previous one here.
3041   switch (MMX3DNowLevel) {
3042   case AMD3DNowAthlon:
3043     Builder.defineMacro("__3dNOW_A__");
3044   case AMD3DNow:
3045     Builder.defineMacro("__3dNOW__");
3046   case MMX:
3047     Builder.defineMacro("__MMX__");
3048   case NoMMX3DNow:
3049     break;
3050   }
3051 
3052   if (CPU >= CK_i486) {
3053     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3054     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3055     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3056   }
3057   if (CPU >= CK_i586)
3058     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3059 }
3060 
3061 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3062   return llvm::StringSwitch<bool>(Feature)
3063       .Case("aes", HasAES)
3064       .Case("avx", SSELevel >= AVX)
3065       .Case("avx2", SSELevel >= AVX2)
3066       .Case("avx512f", SSELevel >= AVX512F)
3067       .Case("avx512cd", HasAVX512CD)
3068       .Case("avx512er", HasAVX512ER)
3069       .Case("avx512pf", HasAVX512PF)
3070       .Case("avx512dq", HasAVX512DQ)
3071       .Case("avx512bw", HasAVX512BW)
3072       .Case("avx512vl", HasAVX512VL)
3073       .Case("bmi", HasBMI)
3074       .Case("bmi2", HasBMI2)
3075       .Case("cx16", HasCX16)
3076       .Case("f16c", HasF16C)
3077       .Case("fma", HasFMA)
3078       .Case("fma4", XOPLevel >= FMA4)
3079       .Case("fsgsbase", HasFSGSBASE)
3080       .Case("lzcnt", HasLZCNT)
3081       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3082       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3083       .Case("mmx", MMX3DNowLevel >= MMX)
3084       .Case("pclmul", HasPCLMUL)
3085       .Case("popcnt", HasPOPCNT)
3086       .Case("prfchw", HasPRFCHW)
3087       .Case("rdrnd", HasRDRND)
3088       .Case("rdseed", HasRDSEED)
3089       .Case("rtm", HasRTM)
3090       .Case("sha", HasSHA)
3091       .Case("sse", SSELevel >= SSE1)
3092       .Case("sse2", SSELevel >= SSE2)
3093       .Case("sse3", SSELevel >= SSE3)
3094       .Case("ssse3", SSELevel >= SSSE3)
3095       .Case("sse4.1", SSELevel >= SSE41)
3096       .Case("sse4.2", SSELevel >= SSE42)
3097       .Case("sse4a", XOPLevel >= SSE4A)
3098       .Case("tbm", HasTBM)
3099       .Case("x86", true)
3100       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3101       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3102       .Case("xop", XOPLevel >= XOP)
3103       .Default(false);
3104 }
3105 
3106 bool
3107 X86TargetInfo::validateAsmConstraint(const char *&Name,
3108                                      TargetInfo::ConstraintInfo &Info) const {
3109   switch (*Name) {
3110   default: return false;
3111   case 'I':
3112     Info.setRequiresImmediate(0, 31);
3113     return true;
3114   case 'J':
3115     Info.setRequiresImmediate(0, 63);
3116     return true;
3117   case 'K':
3118     Info.setRequiresImmediate(-128, 127);
3119     return true;
3120   case 'L':
3121     // FIXME: properly analyze this constraint:
3122     //  must be one of 0xff, 0xffff, or 0xffffffff
3123     return true;
3124   case 'M':
3125     Info.setRequiresImmediate(0, 3);
3126     return true;
3127   case 'N':
3128     Info.setRequiresImmediate(0, 255);
3129     return true;
3130   case 'O':
3131     Info.setRequiresImmediate(0, 127);
3132     return true;
3133   case 'Y': // first letter of a pair:
3134     switch (*(Name+1)) {
3135     default: return false;
3136     case '0':  // First SSE register.
3137     case 't':  // Any SSE register, when SSE2 is enabled.
3138     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3139     case 'm':  // any MMX register, when inter-unit moves enabled.
3140       break;   // falls through to setAllowsRegister.
3141   }
3142   case 'f': // any x87 floating point stack register.
3143     // Constraint 'f' cannot be used for output operands.
3144     if (Info.ConstraintStr[0] == '=')
3145       return false;
3146 
3147     Info.setAllowsRegister();
3148     return true;
3149   case 'a': // eax.
3150   case 'b': // ebx.
3151   case 'c': // ecx.
3152   case 'd': // edx.
3153   case 'S': // esi.
3154   case 'D': // edi.
3155   case 'A': // edx:eax.
3156   case 't': // top of floating point stack.
3157   case 'u': // second from top of floating point stack.
3158   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3159   case 'y': // Any MMX register.
3160   case 'x': // Any SSE register.
3161   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3162   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3163   case 'l': // "Index" registers: any general register that can be used as an
3164             // index in a base+index memory access.
3165     Info.setAllowsRegister();
3166     return true;
3167   case 'C': // SSE floating point constant.
3168   case 'G': // x87 floating point constant.
3169   case 'e': // 32-bit signed integer constant for use with zero-extending
3170             // x86_64 instructions.
3171   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3172             // x86_64 instructions.
3173     return true;
3174   }
3175 }
3176 
3177 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3178                                        unsigned Size) const {
3179   // Strip off constraint modifiers.
3180   while (Constraint[0] == '=' ||
3181          Constraint[0] == '+' ||
3182          Constraint[0] == '&')
3183     Constraint = Constraint.substr(1);
3184 
3185   return validateOperandSize(Constraint, Size);
3186 }
3187 
3188 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3189                                       unsigned Size) const {
3190   return validateOperandSize(Constraint, Size);
3191 }
3192 
3193 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3194                                         unsigned Size) const {
3195   switch (Constraint[0]) {
3196   default: break;
3197   case 'y':
3198     return Size <= 64;
3199   case 'f':
3200   case 't':
3201   case 'u':
3202     return Size <= 128;
3203   case 'x':
3204     // 256-bit ymm registers can be used if target supports AVX.
3205     return Size <= (SSELevel >= AVX ? 256U : 128U);
3206   }
3207 
3208   return true;
3209 }
3210 
3211 std::string
3212 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3213   switch (*Constraint) {
3214   case 'a': return std::string("{ax}");
3215   case 'b': return std::string("{bx}");
3216   case 'c': return std::string("{cx}");
3217   case 'd': return std::string("{dx}");
3218   case 'S': return std::string("{si}");
3219   case 'D': return std::string("{di}");
3220   case 'p': // address
3221     return std::string("im");
3222   case 't': // top of floating point stack.
3223     return std::string("{st}");
3224   case 'u': // second from top of floating point stack.
3225     return std::string("{st(1)}"); // second from top of floating point stack.
3226   default:
3227     return std::string(1, *Constraint);
3228   }
3229 }
3230 } // end anonymous namespace
3231 
3232 namespace {
3233 // X86-32 generic target
3234 class X86_32TargetInfo : public X86TargetInfo {
3235 public:
3236   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3237     DoubleAlign = LongLongAlign = 32;
3238     LongDoubleWidth = 96;
3239     LongDoubleAlign = 32;
3240     SuitableAlign = 128;
3241     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3242     SizeType = UnsignedInt;
3243     PtrDiffType = SignedInt;
3244     IntPtrType = SignedInt;
3245     RegParmMax = 3;
3246 
3247     // Use fpret for all types.
3248     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3249                              (1 << TargetInfo::Double) |
3250                              (1 << TargetInfo::LongDouble));
3251 
3252     // x86-32 has atomics up to 8 bytes
3253     // FIXME: Check that we actually have cmpxchg8b before setting
3254     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3255     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3256   }
3257   BuiltinVaListKind getBuiltinVaListKind() const override {
3258     return TargetInfo::CharPtrBuiltinVaList;
3259   }
3260 
3261   int getEHDataRegisterNumber(unsigned RegNo) const override {
3262     if (RegNo == 0) return 0;
3263     if (RegNo == 1) return 2;
3264     return -1;
3265   }
3266   bool validateOperandSize(StringRef Constraint,
3267                            unsigned Size) const override {
3268     switch (Constraint[0]) {
3269     default: break;
3270     case 'R':
3271     case 'q':
3272     case 'Q':
3273     case 'a':
3274     case 'b':
3275     case 'c':
3276     case 'd':
3277     case 'S':
3278     case 'D':
3279       return Size <= 32;
3280     case 'A':
3281       return Size <= 64;
3282     }
3283 
3284     return X86TargetInfo::validateOperandSize(Constraint, Size);
3285   }
3286 };
3287 } // end anonymous namespace
3288 
3289 namespace {
3290 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3291 public:
3292   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3293       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3294 
3295   unsigned getFloatEvalMethod() const override {
3296     unsigned Major, Minor, Micro;
3297     getTriple().getOSVersion(Major, Minor, Micro);
3298     // New NetBSD uses the default rounding mode.
3299     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3300       return X86_32TargetInfo::getFloatEvalMethod();
3301     // NetBSD before 6.99.26 defaults to "double" rounding.
3302     return 1;
3303   }
3304 };
3305 } // end anonymous namespace
3306 
3307 namespace {
3308 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3309 public:
3310   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3311       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3312     SizeType = UnsignedLong;
3313     IntPtrType = SignedLong;
3314     PtrDiffType = SignedLong;
3315   }
3316 };
3317 } // end anonymous namespace
3318 
3319 namespace {
3320 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3321 public:
3322   BitrigI386TargetInfo(const llvm::Triple &Triple)
3323       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3324     SizeType = UnsignedLong;
3325     IntPtrType = SignedLong;
3326     PtrDiffType = SignedLong;
3327   }
3328 };
3329 } // end anonymous namespace
3330 
3331 namespace {
3332 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3333 public:
3334   DarwinI386TargetInfo(const llvm::Triple &Triple)
3335       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3336     LongDoubleWidth = 128;
3337     LongDoubleAlign = 128;
3338     SuitableAlign = 128;
3339     MaxVectorAlign = 256;
3340     SizeType = UnsignedLong;
3341     IntPtrType = SignedLong;
3342     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3343     HasAlignMac68kSupport = true;
3344   }
3345 
3346 };
3347 } // end anonymous namespace
3348 
3349 namespace {
3350 // x86-32 Windows target
3351 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3352 public:
3353   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3354       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3355     WCharType = UnsignedShort;
3356     DoubleAlign = LongLongAlign = 64;
3357     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3358   }
3359   void getTargetDefines(const LangOptions &Opts,
3360                         MacroBuilder &Builder) const override {
3361     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3362   }
3363 };
3364 
3365 // x86-32 Windows Visual Studio target
3366 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3367 public:
3368   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3369       : WindowsX86_32TargetInfo(Triple) {
3370     LongDoubleWidth = LongDoubleAlign = 64;
3371     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3372   }
3373   void getTargetDefines(const LangOptions &Opts,
3374                         MacroBuilder &Builder) const override {
3375     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3376     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3377     // The value of the following reflects processor type.
3378     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3379     // We lost the original triple, so we use the default.
3380     Builder.defineMacro("_M_IX86", "600");
3381   }
3382 };
3383 } // end anonymous namespace
3384 
3385 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3386   Builder.defineMacro("__MSVCRT__");
3387   Builder.defineMacro("__MINGW32__");
3388 
3389   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3390   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3391   // macro anyway for pre-processor compatibility.
3392   if (Opts.MicrosoftExt)
3393     Builder.defineMacro("__declspec", "__declspec");
3394   else
3395     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3396 
3397   if (!Opts.MicrosoftExt) {
3398     // Provide macros for all the calling convention keywords.  Provide both
3399     // single and double underscore prefixed variants.  These are available on
3400     // x64 as well as x86, even though they have no effect.
3401     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3402     for (const char *CC : CCs) {
3403       std::string GCCSpelling = "__attribute__((__";
3404       GCCSpelling += CC;
3405       GCCSpelling += "__))";
3406       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3407       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3408     }
3409   }
3410 }
3411 
3412 namespace {
3413 // x86-32 MinGW target
3414 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3415 public:
3416   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3417       : WindowsX86_32TargetInfo(Triple) {}
3418   void getTargetDefines(const LangOptions &Opts,
3419                         MacroBuilder &Builder) const override {
3420     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3421     DefineStd(Builder, "WIN32", Opts);
3422     DefineStd(Builder, "WINNT", Opts);
3423     Builder.defineMacro("_X86_");
3424     addMinGWDefines(Opts, Builder);
3425   }
3426 };
3427 } // end anonymous namespace
3428 
3429 namespace {
3430 // x86-32 Cygwin target
3431 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3432 public:
3433   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3434       : X86_32TargetInfo(Triple) {
3435     TLSSupported = false;
3436     WCharType = UnsignedShort;
3437     DoubleAlign = LongLongAlign = 64;
3438     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3439   }
3440   void getTargetDefines(const LangOptions &Opts,
3441                         MacroBuilder &Builder) const override {
3442     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3443     Builder.defineMacro("_X86_");
3444     Builder.defineMacro("__CYGWIN__");
3445     Builder.defineMacro("__CYGWIN32__");
3446     DefineStd(Builder, "unix", Opts);
3447     if (Opts.CPlusPlus)
3448       Builder.defineMacro("_GNU_SOURCE");
3449   }
3450 };
3451 } // end anonymous namespace
3452 
3453 namespace {
3454 // x86-32 Haiku target
3455 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3456 public:
3457   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3458     SizeType = UnsignedLong;
3459     IntPtrType = SignedLong;
3460     PtrDiffType = SignedLong;
3461     ProcessIDType = SignedLong;
3462     this->UserLabelPrefix = "";
3463     this->TLSSupported = false;
3464   }
3465   void getTargetDefines(const LangOptions &Opts,
3466                         MacroBuilder &Builder) const override {
3467     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3468     Builder.defineMacro("__INTEL__");
3469     Builder.defineMacro("__HAIKU__");
3470   }
3471 };
3472 } // end anonymous namespace
3473 
3474 // RTEMS Target
3475 template<typename Target>
3476 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3477 protected:
3478   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3479                     MacroBuilder &Builder) const override {
3480     // RTEMS defines; list based off of gcc output
3481 
3482     Builder.defineMacro("__rtems__");
3483     Builder.defineMacro("__ELF__");
3484   }
3485 
3486 public:
3487   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3488     this->UserLabelPrefix = "";
3489 
3490     switch (Triple.getArch()) {
3491     default:
3492     case llvm::Triple::x86:
3493       // this->MCountName = ".mcount";
3494       break;
3495     case llvm::Triple::mips:
3496     case llvm::Triple::mipsel:
3497     case llvm::Triple::ppc:
3498     case llvm::Triple::ppc64:
3499     case llvm::Triple::ppc64le:
3500       // this->MCountName = "_mcount";
3501       break;
3502     case llvm::Triple::arm:
3503       // this->MCountName = "__mcount";
3504       break;
3505     }
3506   }
3507 };
3508 
3509 namespace {
3510 // x86-32 RTEMS target
3511 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3512 public:
3513   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3514     SizeType = UnsignedLong;
3515     IntPtrType = SignedLong;
3516     PtrDiffType = SignedLong;
3517     this->UserLabelPrefix = "";
3518   }
3519   void getTargetDefines(const LangOptions &Opts,
3520                         MacroBuilder &Builder) const override {
3521     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3522     Builder.defineMacro("__INTEL__");
3523     Builder.defineMacro("__rtems__");
3524   }
3525 };
3526 } // end anonymous namespace
3527 
3528 namespace {
3529 // x86-64 generic target
3530 class X86_64TargetInfo : public X86TargetInfo {
3531 public:
3532   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3533     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3534     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3535     LongDoubleWidth = 128;
3536     LongDoubleAlign = 128;
3537     LargeArrayMinWidth = 128;
3538     LargeArrayAlign = 128;
3539     SuitableAlign = 128;
3540     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3541     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3542     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3543     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3544     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3545     RegParmMax = 6;
3546 
3547     // Pointers are 32-bit in x32.
3548     DescriptionString = (IsX32)
3549                             ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3550                             : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3551 
3552     // Use fpret only for long double.
3553     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3554 
3555     // Use fp2ret for _Complex long double.
3556     ComplexLongDoubleUsesFP2Ret = true;
3557 
3558     // x86-64 has atomics up to 16 bytes.
3559     MaxAtomicPromoteWidth = 128;
3560     MaxAtomicInlineWidth = 128;
3561   }
3562   BuiltinVaListKind getBuiltinVaListKind() const override {
3563     return TargetInfo::X86_64ABIBuiltinVaList;
3564   }
3565 
3566   int getEHDataRegisterNumber(unsigned RegNo) const override {
3567     if (RegNo == 0) return 0;
3568     if (RegNo == 1) return 1;
3569     return -1;
3570   }
3571 
3572   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3573     return (CC == CC_C ||
3574             CC == CC_X86VectorCall ||
3575             CC == CC_IntelOclBicc ||
3576             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3577   }
3578 
3579   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3580     return CC_C;
3581   }
3582 
3583   // for x32 we need it here explicitly
3584   bool hasInt128Type() const override { return true; }
3585 };
3586 } // end anonymous namespace
3587 
3588 namespace {
3589 // x86-64 Windows target
3590 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3591 public:
3592   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3593       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3594     WCharType = UnsignedShort;
3595     LongWidth = LongAlign = 32;
3596     DoubleAlign = LongLongAlign = 64;
3597     IntMaxType = SignedLongLong;
3598     Int64Type = SignedLongLong;
3599     SizeType = UnsignedLongLong;
3600     PtrDiffType = SignedLongLong;
3601     IntPtrType = SignedLongLong;
3602     this->UserLabelPrefix = "";
3603   }
3604   void getTargetDefines(const LangOptions &Opts,
3605                                 MacroBuilder &Builder) const override {
3606     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3607     Builder.defineMacro("_WIN64");
3608   }
3609   BuiltinVaListKind getBuiltinVaListKind() const override {
3610     return TargetInfo::CharPtrBuiltinVaList;
3611   }
3612   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3613     return (CC == CC_C ||
3614             CC == CC_X86VectorCall ||
3615             CC == CC_IntelOclBicc ||
3616             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3617   }
3618 };
3619 } // end anonymous namespace
3620 
3621 namespace {
3622 // x86-64 Windows Visual Studio target
3623 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3624 public:
3625   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3626       : WindowsX86_64TargetInfo(Triple) {
3627     LongDoubleWidth = LongDoubleAlign = 64;
3628     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3629   }
3630   void getTargetDefines(const LangOptions &Opts,
3631                         MacroBuilder &Builder) const override {
3632     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3633     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3634     Builder.defineMacro("_M_X64");
3635     Builder.defineMacro("_M_AMD64");
3636   }
3637 };
3638 } // end anonymous namespace
3639 
3640 namespace {
3641 // x86-64 MinGW target
3642 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3643 public:
3644   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3645       : WindowsX86_64TargetInfo(Triple) {}
3646   void getTargetDefines(const LangOptions &Opts,
3647                         MacroBuilder &Builder) const override {
3648     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3649     DefineStd(Builder, "WIN64", Opts);
3650     Builder.defineMacro("__MINGW64__");
3651     addMinGWDefines(Opts, Builder);
3652 
3653     // GCC defines this macro when it is using __gxx_personality_seh0.
3654     if (!Opts.SjLjExceptions)
3655       Builder.defineMacro("__SEH__");
3656   }
3657 };
3658 } // end anonymous namespace
3659 
3660 namespace {
3661 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3662 public:
3663   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3664       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3665     Int64Type = SignedLongLong;
3666     MaxVectorAlign = 256;
3667     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3668     llvm::Triple T = llvm::Triple(Triple);
3669     if (T.isiOS())
3670       UseSignedCharForObjCBool = false;
3671     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3672   }
3673 };
3674 } // end anonymous namespace
3675 
3676 namespace {
3677 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3678 public:
3679   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3680       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3681     IntMaxType = SignedLongLong;
3682     Int64Type = SignedLongLong;
3683   }
3684 };
3685 } // end anonymous namespace
3686 
3687 namespace {
3688 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3689 public:
3690   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3691       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3692     IntMaxType = SignedLongLong;
3693     Int64Type = SignedLongLong;
3694   }
3695 };
3696 }
3697 
3698 
3699 namespace {
3700 class ARMTargetInfo : public TargetInfo {
3701   // Possible FPU choices.
3702   enum FPUMode {
3703     VFP2FPU = (1 << 0),
3704     VFP3FPU = (1 << 1),
3705     VFP4FPU = (1 << 2),
3706     NeonFPU = (1 << 3),
3707     FPARMV8 = (1 << 4)
3708   };
3709 
3710   // Possible HWDiv features.
3711   enum HWDivMode {
3712     HWDivThumb = (1 << 0),
3713     HWDivARM = (1 << 1)
3714   };
3715 
3716   static bool FPUModeIsVFP(FPUMode Mode) {
3717     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3718   }
3719 
3720   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3721   static const char * const GCCRegNames[];
3722 
3723   std::string ABI, CPU;
3724 
3725   enum {
3726     FP_Default,
3727     FP_VFP,
3728     FP_Neon
3729   } FPMath;
3730 
3731   unsigned FPU : 5;
3732 
3733   unsigned IsAAPCS : 1;
3734   unsigned IsThumb : 1;
3735   unsigned HWDiv : 2;
3736 
3737   // Initialized via features.
3738   unsigned SoftFloat : 1;
3739   unsigned SoftFloatABI : 1;
3740 
3741   unsigned CRC : 1;
3742   unsigned Crypto : 1;
3743 
3744   // ACLE 6.5.1 Hardware floating point
3745   enum {
3746     HW_FP_HP = (1 << 1), /// half (16-bit)
3747     HW_FP_SP = (1 << 2), /// single (32-bit)
3748     HW_FP_DP = (1 << 3), /// double (64-bit)
3749   };
3750   uint32_t HW_FP;
3751 
3752   static const Builtin::Info BuiltinInfo[];
3753 
3754   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3755     StringRef ArchName = T.getArchName();
3756     if (T.getArch() == llvm::Triple::arm ||
3757         T.getArch() == llvm::Triple::armeb) {
3758       StringRef VersionStr;
3759       if (ArchName.startswith("armv"))
3760         VersionStr = ArchName.substr(4, 1);
3761       else if (ArchName.startswith("armebv"))
3762         VersionStr = ArchName.substr(6, 1);
3763       else
3764         return false;
3765       unsigned Version;
3766       if (VersionStr.getAsInteger(10, Version))
3767         return false;
3768       return Version >= 6;
3769     }
3770     assert(T.getArch() == llvm::Triple::thumb ||
3771            T.getArch() == llvm::Triple::thumbeb);
3772     StringRef VersionStr;
3773     if (ArchName.startswith("thumbv"))
3774       VersionStr = ArchName.substr(6, 1);
3775     else if (ArchName.startswith("thumbebv"))
3776       VersionStr = ArchName.substr(8, 1);
3777     else
3778       return false;
3779     unsigned Version;
3780     if (VersionStr.getAsInteger(10, Version))
3781       return false;
3782     return Version >= 7;
3783   }
3784 
3785   void setABIAAPCS() {
3786     IsAAPCS = true;
3787 
3788     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3789     const llvm::Triple &T = getTriple();
3790 
3791     // size_t is unsigned long on MachO-derived environments and NetBSD.
3792     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3793       SizeType = UnsignedLong;
3794     else
3795       SizeType = UnsignedInt;
3796 
3797     switch (T.getOS()) {
3798     case llvm::Triple::NetBSD:
3799       WCharType = SignedInt;
3800       break;
3801     case llvm::Triple::Win32:
3802       WCharType = UnsignedShort;
3803       break;
3804     case llvm::Triple::Linux:
3805     default:
3806       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3807       WCharType = UnsignedInt;
3808       break;
3809     }
3810 
3811     UseBitFieldTypeAlignment = true;
3812 
3813     ZeroLengthBitfieldBoundary = 0;
3814 
3815     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3816     // so set preferred for small types to 32.
3817     if (T.isOSBinFormatMachO()) {
3818       DescriptionString =
3819           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3820                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3821     } else if (T.isOSWindows()) {
3822       // FIXME: this is invalid for WindowsCE
3823       assert(!BigEndian && "Windows on ARM does not support big endian");
3824       DescriptionString = "e"
3825                           "-m:e"
3826                           "-p:32:32"
3827                           "-i64:64"
3828                           "-v128:64:128"
3829                           "-a:0:32"
3830                           "-n32"
3831                           "-S64";
3832     } else {
3833       DescriptionString =
3834           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3835                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3836     }
3837 
3838     // FIXME: Enumerated types are variable width in straight AAPCS.
3839   }
3840 
3841   void setABIAPCS() {
3842     const llvm::Triple &T = getTriple();
3843 
3844     IsAAPCS = false;
3845 
3846     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3847 
3848     // size_t is unsigned int on FreeBSD.
3849     if (T.getOS() == llvm::Triple::FreeBSD)
3850       SizeType = UnsignedInt;
3851     else
3852       SizeType = UnsignedLong;
3853 
3854     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3855     WCharType = SignedInt;
3856 
3857     // Do not respect the alignment of bit-field types when laying out
3858     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3859     UseBitFieldTypeAlignment = false;
3860 
3861     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3862     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3863     /// gcc.
3864     ZeroLengthBitfieldBoundary = 32;
3865 
3866     if (T.isOSBinFormatMachO())
3867       DescriptionString =
3868           BigEndian
3869               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3870               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3871     else
3872       DescriptionString =
3873           BigEndian
3874               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3875               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3876 
3877     // FIXME: Override "preferred align" for double and long long.
3878   }
3879 
3880 public:
3881   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3882       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3883         IsAAPCS(true), HW_FP(0) {
3884     BigEndian = IsBigEndian;
3885 
3886     switch (getTriple().getOS()) {
3887     case llvm::Triple::NetBSD:
3888       PtrDiffType = SignedLong;
3889       break;
3890     default:
3891       PtrDiffType = SignedInt;
3892       break;
3893     }
3894 
3895     // {} in inline assembly are neon specifiers, not assembly variant
3896     // specifiers.
3897     NoAsmVariants = true;
3898 
3899     // FIXME: Should we just treat this as a feature?
3900     IsThumb = getTriple().getArchName().startswith("thumb");
3901 
3902     // FIXME: This duplicates code from the driver that sets the -target-abi
3903     // option - this code is used if -target-abi isn't passed and should
3904     // be unified in some way.
3905     if (Triple.isOSBinFormatMachO()) {
3906       // The backend is hardwired to assume AAPCS for M-class processors, ensure
3907       // the frontend matches that.
3908       if (Triple.getEnvironment() == llvm::Triple::EABI ||
3909           Triple.getOS() == llvm::Triple::UnknownOS ||
3910           StringRef(CPU).startswith("cortex-m")) {
3911         setABI("aapcs");
3912       } else {
3913         setABI("apcs-gnu");
3914       }
3915     } else if (Triple.isOSWindows()) {
3916       // FIXME: this is invalid for WindowsCE
3917       setABI("aapcs");
3918     } else {
3919       // Select the default based on the platform.
3920       switch (Triple.getEnvironment()) {
3921       case llvm::Triple::Android:
3922       case llvm::Triple::GNUEABI:
3923       case llvm::Triple::GNUEABIHF:
3924         setABI("aapcs-linux");
3925         break;
3926       case llvm::Triple::EABIHF:
3927       case llvm::Triple::EABI:
3928         setABI("aapcs");
3929         break;
3930       case llvm::Triple::GNU:
3931 	setABI("apcs-gnu");
3932 	break;
3933       default:
3934         if (Triple.getOS() == llvm::Triple::NetBSD)
3935           setABI("apcs-gnu");
3936         else
3937           setABI("aapcs");
3938         break;
3939       }
3940     }
3941 
3942     // ARM targets default to using the ARM C++ ABI.
3943     TheCXXABI.set(TargetCXXABI::GenericARM);
3944 
3945     // ARM has atomics up to 8 bytes
3946     MaxAtomicPromoteWidth = 64;
3947     if (shouldUseInlineAtomic(getTriple()))
3948       MaxAtomicInlineWidth = 64;
3949 
3950     // Do force alignment of members that follow zero length bitfields.  If
3951     // the alignment of the zero-length bitfield is greater than the member
3952     // that follows it, `bar', `bar' will be aligned as the  type of the
3953     // zero length bitfield.
3954     UseZeroLengthBitfieldAlignment = true;
3955   }
3956   StringRef getABI() const override { return ABI; }
3957   bool setABI(const std::string &Name) override {
3958     ABI = Name;
3959 
3960     // The defaults (above) are for AAPCS, check if we need to change them.
3961     //
3962     // FIXME: We need support for -meabi... we could just mangle it into the
3963     // name.
3964     if (Name == "apcs-gnu") {
3965       setABIAPCS();
3966       return true;
3967     }
3968     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3969       setABIAAPCS();
3970       return true;
3971     }
3972     return false;
3973   }
3974 
3975   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3976     StringRef ArchName = getTriple().getArchName();
3977     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3978       Features["vfp2"] = true;
3979     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
3980       Features["vfp3"] = true;
3981       Features["neon"] = true;
3982     }
3983     else if (CPU == "cortex-a5") {
3984       Features["vfp4"] = true;
3985       Features["neon"] = true;
3986     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3987                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3988                CPU == "cortex-a17" || CPU == "krait") {
3989       Features["vfp4"] = true;
3990       Features["neon"] = true;
3991       Features["hwdiv"] = true;
3992       Features["hwdiv-arm"] = true;
3993     } else if (CPU == "cyclone") {
3994       Features["v8fp"] = true;
3995       Features["neon"] = true;
3996       Features["hwdiv"] = true;
3997       Features["hwdiv-arm"] = true;
3998     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3999       Features["fp-armv8"] = true;
4000       Features["neon"] = true;
4001       Features["hwdiv"] = true;
4002       Features["hwdiv-arm"] = true;
4003       Features["crc"] = true;
4004       Features["crypto"] = true;
4005     } else if (CPU == "cortex-r5" ||
4006                // Enable the hwdiv extension for all v8a AArch32 cores by
4007                // default.
4008                ArchName == "armv8a" || ArchName == "armv8" ||
4009                ArchName == "armebv8a" || ArchName == "armebv8" ||
4010                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
4011                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
4012       Features["hwdiv"] = true;
4013       Features["hwdiv-arm"] = true;
4014     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
4015       Features["hwdiv"] = true;
4016     }
4017   }
4018 
4019   bool handleTargetFeatures(std::vector<std::string> &Features,
4020                             DiagnosticsEngine &Diags) override {
4021     FPU = 0;
4022     CRC = 0;
4023     Crypto = 0;
4024     SoftFloat = SoftFloatABI = false;
4025     HWDiv = 0;
4026 
4027     for (const auto &Feature : Features) {
4028       if (Feature == "+soft-float") {
4029         SoftFloat = true;
4030       } else if (Feature == "+soft-float-abi") {
4031         SoftFloatABI = true;
4032       } else if (Feature == "+vfp2") {
4033         FPU |= VFP2FPU;
4034         HW_FP = HW_FP_SP | HW_FP_DP;
4035       } else if (Feature == "+vfp3") {
4036         FPU |= VFP3FPU;
4037         HW_FP = HW_FP_SP | HW_FP_DP;
4038       } else if (Feature == "+vfp4") {
4039         FPU |= VFP4FPU;
4040         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4041       } else if (Feature == "+fp-armv8") {
4042         FPU |= FPARMV8;
4043         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4044       } else if (Feature == "+neon") {
4045         FPU |= NeonFPU;
4046         HW_FP = HW_FP_SP | HW_FP_DP;
4047       } else if (Feature == "+hwdiv") {
4048         HWDiv |= HWDivThumb;
4049       } else if (Feature == "+hwdiv-arm") {
4050         HWDiv |= HWDivARM;
4051       } else if (Feature == "+crc") {
4052         CRC = 1;
4053       } else if (Feature == "+crypto") {
4054         Crypto = 1;
4055       } else if (Feature == "+fp-only-sp") {
4056         HW_FP &= ~HW_FP_DP;
4057       }
4058     }
4059 
4060     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4061       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4062       return false;
4063     }
4064 
4065     if (FPMath == FP_Neon)
4066       Features.push_back("+neonfp");
4067     else if (FPMath == FP_VFP)
4068       Features.push_back("-neonfp");
4069 
4070     // Remove front-end specific options which the backend handles differently.
4071     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
4072     for (const auto &FEFeature : FrontEndFeatures) {
4073       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
4074       if (Feature != Features.end())
4075         Features.erase(Feature);
4076     }
4077 
4078     return true;
4079   }
4080 
4081   bool hasFeature(StringRef Feature) const override {
4082     return llvm::StringSwitch<bool>(Feature)
4083         .Case("arm", true)
4084         .Case("softfloat", SoftFloat)
4085         .Case("thumb", IsThumb)
4086         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4087         .Case("hwdiv", HWDiv & HWDivThumb)
4088         .Case("hwdiv-arm", HWDiv & HWDivARM)
4089         .Default(false);
4090   }
4091   // FIXME: Should we actually have some table instead of these switches?
4092   static const char *getCPUDefineSuffix(StringRef Name) {
4093     return llvm::StringSwitch<const char *>(Name)
4094         .Cases("arm8", "arm810", "4")
4095         .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110",
4096                "4")
4097         .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4098         .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4099         .Case("ep9312", "4T")
4100         .Cases("arm10tdmi", "arm1020t", "5T")
4101         .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4102         .Case("arm926ej-s", "5TEJ")
4103         .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4104         .Cases("xscale", "iwmmxt", "5TE")
4105         .Case("arm1136j-s", "6J")
4106         .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4107         .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4108         .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4109         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A")
4110         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4111                "7A")
4112         .Cases("cortex-r4", "cortex-r5", "7R")
4113         .Case("swift", "7S")
4114         .Case("cyclone", "8A")
4115         .Case("cortex-m3", "7M")
4116         .Cases("cortex-m4", "cortex-m7", "7EM")
4117         .Case("cortex-m0", "6M")
4118         .Cases("cortex-a53", "cortex-a57", "8A")
4119         .Default(nullptr);
4120   }
4121   static const char *getCPUProfile(StringRef Name) {
4122     return llvm::StringSwitch<const char *>(Name)
4123         .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4124         .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait",
4125                "A")
4126         .Cases("cortex-a53", "cortex-a57", "A")
4127         .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4128         .Cases("cortex-r4", "cortex-r5", "R")
4129         .Default("");
4130   }
4131   bool setCPU(const std::string &Name) override {
4132     if (!getCPUDefineSuffix(Name))
4133       return false;
4134 
4135     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4136     StringRef Profile = getCPUProfile(Name);
4137     if (Profile == "M" && MaxAtomicInlineWidth) {
4138       MaxAtomicPromoteWidth = 32;
4139       MaxAtomicInlineWidth = 32;
4140     }
4141 
4142     CPU = Name;
4143     return true;
4144   }
4145   bool setFPMath(StringRef Name) override;
4146   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4147                      unsigned CPUArchVer) const {
4148     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4149            (CPUArch.find('M') != StringRef::npos);
4150   }
4151   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4152                       unsigned CPUArchVer) const {
4153     // We check both CPUArchVer and ArchName because when only triple is
4154     // specified, the default CPU is arm1136j-s.
4155     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4156            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4157   }
4158   void getTargetDefines(const LangOptions &Opts,
4159                         MacroBuilder &Builder) const override {
4160     // Target identification.
4161     Builder.defineMacro("__arm");
4162     Builder.defineMacro("__arm__");
4163 
4164     // Target properties.
4165     Builder.defineMacro("__REGISTER_PREFIX__", "");
4166 
4167     StringRef CPUArch = getCPUDefineSuffix(CPU);
4168     unsigned int CPUArchVer;
4169     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4170       llvm_unreachable("Invalid char for architecture version number");
4171     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4172 
4173     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4174     StringRef CPUProfile = getCPUProfile(CPU);
4175     StringRef ArchName = getTriple().getArchName();
4176 
4177     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4178     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4179     if (CPUArch[0] >= '8') {
4180       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4181       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4182     }
4183 
4184     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4185     // is not defined for the M-profile.
4186     // NOTE that the deffault profile is assumed to be 'A'
4187     if (CPUProfile.empty() || CPUProfile != "M")
4188       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4189 
4190     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4191     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4192     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4193     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4194       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4195     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4196       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4197 
4198     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4199     // instruction set such as ARM or Thumb.
4200     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4201 
4202     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4203 
4204     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4205     if (!CPUProfile.empty())
4206       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4207 
4208     // ACLE 6.5.1 Hardware Floating Point
4209     if (HW_FP)
4210       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4211 
4212     // ACLE predefines.
4213     Builder.defineMacro("__ARM_ACLE", "200");
4214 
4215     // Subtarget options.
4216 
4217     // FIXME: It's more complicated than this and we don't really support
4218     // interworking.
4219     // Windows on ARM does not "support" interworking
4220     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4221       Builder.defineMacro("__THUMB_INTERWORK__");
4222 
4223     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4224       // Embedded targets on Darwin follow AAPCS, but not EABI.
4225       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4226       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4227         Builder.defineMacro("__ARM_EABI__");
4228       Builder.defineMacro("__ARM_PCS", "1");
4229 
4230       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4231         Builder.defineMacro("__ARM_PCS_VFP", "1");
4232     }
4233 
4234     if (SoftFloat)
4235       Builder.defineMacro("__SOFTFP__");
4236 
4237     if (CPU == "xscale")
4238       Builder.defineMacro("__XSCALE__");
4239 
4240     if (IsThumb) {
4241       Builder.defineMacro("__THUMBEL__");
4242       Builder.defineMacro("__thumb__");
4243       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4244         Builder.defineMacro("__thumb2__");
4245     }
4246     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4247       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4248 
4249     // Note, this is always on in gcc, even though it doesn't make sense.
4250     Builder.defineMacro("__APCS_32__");
4251 
4252     if (FPUModeIsVFP((FPUMode) FPU)) {
4253       Builder.defineMacro("__VFP_FP__");
4254       if (FPU & VFP2FPU)
4255         Builder.defineMacro("__ARM_VFPV2__");
4256       if (FPU & VFP3FPU)
4257         Builder.defineMacro("__ARM_VFPV3__");
4258       if (FPU & VFP4FPU)
4259         Builder.defineMacro("__ARM_VFPV4__");
4260     }
4261 
4262     // This only gets set when Neon instructions are actually available, unlike
4263     // the VFP define, hence the soft float and arch check. This is subtly
4264     // different from gcc, we follow the intent which was that it should be set
4265     // when Neon instructions are actually available.
4266     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4267       Builder.defineMacro("__ARM_NEON");
4268       Builder.defineMacro("__ARM_NEON__");
4269     }
4270 
4271     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4272                         Opts.ShortWChar ? "2" : "4");
4273 
4274     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4275                         Opts.ShortEnums ? "1" : "4");
4276 
4277     if (CRC)
4278       Builder.defineMacro("__ARM_FEATURE_CRC32");
4279 
4280     if (Crypto)
4281       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4282 
4283     if (CPUArchVer >= 6 && CPUArch != "6M") {
4284       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4285       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4286       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4287       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4288     }
4289 
4290     bool is5EOrAbove = (CPUArchVer >= 6 ||
4291                         (CPUArchVer == 5 &&
4292                          CPUArch.find('E') != StringRef::npos));
4293     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4294     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4295       Builder.defineMacro("__ARM_FEATURE_DSP");
4296   }
4297   void getTargetBuiltins(const Builtin::Info *&Records,
4298                          unsigned &NumRecords) const override {
4299     Records = BuiltinInfo;
4300     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4301   }
4302   bool isCLZForZeroUndef() const override { return false; }
4303   BuiltinVaListKind getBuiltinVaListKind() const override {
4304     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4305   }
4306   void getGCCRegNames(const char * const *&Names,
4307                       unsigned &NumNames) const override;
4308   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4309                         unsigned &NumAliases) const override;
4310   bool validateAsmConstraint(const char *&Name,
4311                              TargetInfo::ConstraintInfo &Info) const override {
4312     switch (*Name) {
4313     default: break;
4314     case 'l': // r0-r7
4315     case 'h': // r8-r15
4316     case 'w': // VFP Floating point register single precision
4317     case 'P': // VFP Floating point register double precision
4318       Info.setAllowsRegister();
4319       return true;
4320     case 'I':
4321     case 'J':
4322     case 'K':
4323     case 'L':
4324     case 'M':
4325       // FIXME
4326       return true;
4327     case 'Q': // A memory address that is a single base register.
4328       Info.setAllowsMemory();
4329       return true;
4330     case 'U': // a memory reference...
4331       switch (Name[1]) {
4332       case 'q': // ...ARMV4 ldrsb
4333       case 'v': // ...VFP load/store (reg+constant offset)
4334       case 'y': // ...iWMMXt load/store
4335       case 't': // address valid for load/store opaque types wider
4336                 // than 128-bits
4337       case 'n': // valid address for Neon doubleword vector load/store
4338       case 'm': // valid address for Neon element and structure load/store
4339       case 's': // valid address for non-offset loads/stores of quad-word
4340                 // values in four ARM registers
4341         Info.setAllowsMemory();
4342         Name++;
4343         return true;
4344       }
4345     }
4346     return false;
4347   }
4348   std::string convertConstraint(const char *&Constraint) const override {
4349     std::string R;
4350     switch (*Constraint) {
4351     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4352       R = std::string("^") + std::string(Constraint, 2);
4353       Constraint++;
4354       break;
4355     case 'p': // 'p' should be translated to 'r' by default.
4356       R = std::string("r");
4357       break;
4358     default:
4359       return std::string(1, *Constraint);
4360     }
4361     return R;
4362   }
4363   bool
4364   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4365                              std::string &SuggestedModifier) const override {
4366     bool isOutput = (Constraint[0] == '=');
4367     bool isInOut = (Constraint[0] == '+');
4368 
4369     // Strip off constraint modifiers.
4370     while (Constraint[0] == '=' ||
4371            Constraint[0] == '+' ||
4372            Constraint[0] == '&')
4373       Constraint = Constraint.substr(1);
4374 
4375     switch (Constraint[0]) {
4376     default: break;
4377     case 'r': {
4378       switch (Modifier) {
4379       default:
4380         return (isInOut || isOutput || Size <= 64);
4381       case 'q':
4382         // A register of size 32 cannot fit a vector type.
4383         return false;
4384       }
4385     }
4386     }
4387 
4388     return true;
4389   }
4390   const char *getClobbers() const override {
4391     // FIXME: Is this really right?
4392     return "";
4393   }
4394 
4395   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4396     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4397   }
4398 
4399   int getEHDataRegisterNumber(unsigned RegNo) const override {
4400     if (RegNo == 0) return 0;
4401     if (RegNo == 1) return 1;
4402     return -1;
4403   }
4404 };
4405 
4406 bool ARMTargetInfo::setFPMath(StringRef Name) {
4407   if (Name == "neon") {
4408     FPMath = FP_Neon;
4409     return true;
4410   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4411              Name == "vfp4") {
4412     FPMath = FP_VFP;
4413     return true;
4414   }
4415   return false;
4416 }
4417 
4418 const char * const ARMTargetInfo::GCCRegNames[] = {
4419   // Integer registers
4420   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4421   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4422 
4423   // Float registers
4424   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4425   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4426   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4427   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4428 
4429   // Double registers
4430   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4431   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4432   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4433   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4434 
4435   // Quad registers
4436   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4437   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4438 };
4439 
4440 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4441                                    unsigned &NumNames) const {
4442   Names = GCCRegNames;
4443   NumNames = llvm::array_lengthof(GCCRegNames);
4444 }
4445 
4446 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4447   { { "a1" }, "r0" },
4448   { { "a2" }, "r1" },
4449   { { "a3" }, "r2" },
4450   { { "a4" }, "r3" },
4451   { { "v1" }, "r4" },
4452   { { "v2" }, "r5" },
4453   { { "v3" }, "r6" },
4454   { { "v4" }, "r7" },
4455   { { "v5" }, "r8" },
4456   { { "v6", "rfp" }, "r9" },
4457   { { "sl" }, "r10" },
4458   { { "fp" }, "r11" },
4459   { { "ip" }, "r12" },
4460   { { "r13" }, "sp" },
4461   { { "r14" }, "lr" },
4462   { { "r15" }, "pc" },
4463   // The S, D and Q registers overlap, but aren't really aliases; we
4464   // don't want to substitute one of these for a different-sized one.
4465 };
4466 
4467 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4468                                        unsigned &NumAliases) const {
4469   Aliases = GCCRegAliases;
4470   NumAliases = llvm::array_lengthof(GCCRegAliases);
4471 }
4472 
4473 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4474 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4475 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4476                                               ALL_LANGUAGES },
4477 #include "clang/Basic/BuiltinsNEON.def"
4478 
4479 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4480 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4481 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4482                                               ALL_LANGUAGES },
4483 #include "clang/Basic/BuiltinsARM.def"
4484 };
4485 
4486 class ARMleTargetInfo : public ARMTargetInfo {
4487 public:
4488   ARMleTargetInfo(const llvm::Triple &Triple)
4489     : ARMTargetInfo(Triple, false) { }
4490   virtual void getTargetDefines(const LangOptions &Opts,
4491                                 MacroBuilder &Builder) const {
4492     Builder.defineMacro("__ARMEL__");
4493     ARMTargetInfo::getTargetDefines(Opts, Builder);
4494   }
4495 };
4496 
4497 class ARMbeTargetInfo : public ARMTargetInfo {
4498 public:
4499   ARMbeTargetInfo(const llvm::Triple &Triple)
4500     : ARMTargetInfo(Triple, true) { }
4501   virtual void getTargetDefines(const LangOptions &Opts,
4502                                 MacroBuilder &Builder) const {
4503     Builder.defineMacro("__ARMEB__");
4504     Builder.defineMacro("__ARM_BIG_ENDIAN");
4505     ARMTargetInfo::getTargetDefines(Opts, Builder);
4506   }
4507 };
4508 } // end anonymous namespace.
4509 
4510 namespace {
4511 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4512   const llvm::Triple Triple;
4513 public:
4514   WindowsARMTargetInfo(const llvm::Triple &Triple)
4515     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4516     TLSSupported = false;
4517     WCharType = UnsignedShort;
4518     SizeType = UnsignedInt;
4519     UserLabelPrefix = "";
4520   }
4521   void getVisualStudioDefines(const LangOptions &Opts,
4522                               MacroBuilder &Builder) const {
4523     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4524 
4525     // FIXME: this is invalid for WindowsCE
4526     Builder.defineMacro("_M_ARM_NT", "1");
4527     Builder.defineMacro("_M_ARMT", "_M_ARM");
4528     Builder.defineMacro("_M_THUMB", "_M_ARM");
4529 
4530     assert((Triple.getArch() == llvm::Triple::arm ||
4531             Triple.getArch() == llvm::Triple::thumb) &&
4532            "invalid architecture for Windows ARM target info");
4533     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4534     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4535 
4536     // TODO map the complete set of values
4537     // 31: VFPv3 40: VFPv4
4538     Builder.defineMacro("_M_ARM_FP", "31");
4539   }
4540   BuiltinVaListKind getBuiltinVaListKind() const override {
4541     return TargetInfo::CharPtrBuiltinVaList;
4542   }
4543 };
4544 
4545 // Windows ARM + Itanium C++ ABI Target
4546 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4547 public:
4548   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4549     : WindowsARMTargetInfo(Triple) {
4550     TheCXXABI.set(TargetCXXABI::GenericARM);
4551   }
4552 
4553   void getTargetDefines(const LangOptions &Opts,
4554                         MacroBuilder &Builder) const override {
4555     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4556 
4557     if (Opts.MSVCCompat)
4558       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4559   }
4560 };
4561 
4562 // Windows ARM, MS (C++) ABI
4563 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4564 public:
4565   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4566     : WindowsARMTargetInfo(Triple) {
4567     TheCXXABI.set(TargetCXXABI::Microsoft);
4568   }
4569 
4570   void getTargetDefines(const LangOptions &Opts,
4571                         MacroBuilder &Builder) const override {
4572     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4573     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4574   }
4575 };
4576 }
4577 
4578 
4579 namespace {
4580 class DarwinARMTargetInfo :
4581   public DarwinTargetInfo<ARMleTargetInfo> {
4582 protected:
4583   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4584                     MacroBuilder &Builder) const override {
4585     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4586   }
4587 
4588 public:
4589   DarwinARMTargetInfo(const llvm::Triple &Triple)
4590       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4591     HasAlignMac68kSupport = true;
4592     // iOS always has 64-bit atomic instructions.
4593     // FIXME: This should be based off of the target features in
4594     // ARMleTargetInfo.
4595     MaxAtomicInlineWidth = 64;
4596 
4597     // Darwin on iOS uses a variant of the ARM C++ ABI.
4598     TheCXXABI.set(TargetCXXABI::iOS);
4599   }
4600 };
4601 } // end anonymous namespace.
4602 
4603 
4604 namespace {
4605 class AArch64TargetInfo : public TargetInfo {
4606   virtual void setDescriptionString() = 0;
4607   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4608   static const char *const GCCRegNames[];
4609 
4610   enum FPUModeEnum {
4611     FPUMode,
4612     NeonMode
4613   };
4614 
4615   unsigned FPU;
4616   unsigned CRC;
4617   unsigned Crypto;
4618 
4619   static const Builtin::Info BuiltinInfo[];
4620 
4621   std::string ABI;
4622 
4623 public:
4624   AArch64TargetInfo(const llvm::Triple &Triple)
4625       : TargetInfo(Triple), ABI("aapcs") {
4626 
4627     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4628       WCharType = SignedInt;
4629 
4630       // NetBSD apparently prefers consistency across ARM targets to consistency
4631       // across 64-bit targets.
4632       Int64Type = SignedLongLong;
4633       IntMaxType = SignedLongLong;
4634     } else {
4635       WCharType = UnsignedInt;
4636       Int64Type = SignedLong;
4637       IntMaxType = SignedLong;
4638     }
4639 
4640     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4641     MaxVectorAlign = 128;
4642     RegParmMax = 8;
4643     MaxAtomicInlineWidth = 128;
4644     MaxAtomicPromoteWidth = 128;
4645 
4646     LongDoubleWidth = LongDoubleAlign = 128;
4647     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4648 
4649     // {} in inline assembly are neon specifiers, not assembly variant
4650     // specifiers.
4651     NoAsmVariants = true;
4652 
4653     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4654     // contributes to the alignment of the containing aggregate in the same way
4655     // a plain (non bit-field) member of that type would, without exception for
4656     // zero-sized or anonymous bit-fields."
4657     UseBitFieldTypeAlignment = true;
4658     UseZeroLengthBitfieldAlignment = true;
4659 
4660     // AArch64 targets default to using the ARM C++ ABI.
4661     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4662   }
4663 
4664   StringRef getABI() const override { return ABI; }
4665   bool setABI(const std::string &Name) override {
4666     if (Name != "aapcs" && Name != "darwinpcs")
4667       return false;
4668 
4669     ABI = Name;
4670     return true;
4671   }
4672 
4673   bool setCPU(const std::string &Name) override {
4674     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4675                         .Case("generic", true)
4676                         .Cases("cortex-a53", "cortex-a57", true)
4677                         .Case("cyclone", true)
4678                         .Default(false);
4679     return CPUKnown;
4680   }
4681 
4682   virtual void getTargetDefines(const LangOptions &Opts,
4683                                 MacroBuilder &Builder) const  override {
4684     // Target identification.
4685     Builder.defineMacro("__aarch64__");
4686 
4687     // Target properties.
4688     Builder.defineMacro("_LP64");
4689     Builder.defineMacro("__LP64__");
4690 
4691     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4692     Builder.defineMacro("__ARM_ACLE", "200");
4693     Builder.defineMacro("__ARM_ARCH", "8");
4694     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4695 
4696     Builder.defineMacro("__ARM_64BIT_STATE");
4697     Builder.defineMacro("__ARM_PCS_AAPCS64");
4698     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4699 
4700     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4701     Builder.defineMacro("__ARM_FEATURE_CLZ");
4702     Builder.defineMacro("__ARM_FEATURE_FMA");
4703     Builder.defineMacro("__ARM_FEATURE_DIV");
4704     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4705     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4706     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4707     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4708 
4709     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4710 
4711     // 0xe implies support for half, single and double precision operations.
4712     Builder.defineMacro("__ARM_FP", "0xe");
4713 
4714     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4715     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4716     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4717 
4718     if (Opts.FastMath || Opts.FiniteMathOnly)
4719       Builder.defineMacro("__ARM_FP_FAST");
4720 
4721     if (Opts.C99 && !Opts.Freestanding)
4722       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4723 
4724     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4725 
4726     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4727                         Opts.ShortEnums ? "1" : "4");
4728 
4729     if (FPU == NeonMode) {
4730       Builder.defineMacro("__ARM_NEON");
4731       // 64-bit NEON supports half, single and double precision operations.
4732       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4733     }
4734 
4735     if (CRC)
4736       Builder.defineMacro("__ARM_FEATURE_CRC32");
4737 
4738     if (Crypto)
4739       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4740   }
4741 
4742   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4743                                  unsigned &NumRecords) const override {
4744     Records = BuiltinInfo;
4745     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4746   }
4747 
4748   bool hasFeature(StringRef Feature) const override {
4749     return Feature == "aarch64" ||
4750       Feature == "arm64" ||
4751       (Feature == "neon" && FPU == NeonMode);
4752   }
4753 
4754   bool handleTargetFeatures(std::vector<std::string> &Features,
4755                             DiagnosticsEngine &Diags) override {
4756     FPU = FPUMode;
4757     CRC = 0;
4758     Crypto = 0;
4759     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4760       if (Features[i] == "+neon")
4761         FPU = NeonMode;
4762       if (Features[i] == "+crc")
4763         CRC = 1;
4764       if (Features[i] == "+crypto")
4765         Crypto = 1;
4766     }
4767 
4768     setDescriptionString();
4769 
4770     return true;
4771   }
4772 
4773   bool isCLZForZeroUndef() const override { return false; }
4774 
4775   BuiltinVaListKind getBuiltinVaListKind() const override {
4776     return TargetInfo::AArch64ABIBuiltinVaList;
4777   }
4778 
4779   virtual void getGCCRegNames(const char *const *&Names,
4780                               unsigned &NumNames) const override;
4781   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4782                                 unsigned &NumAliases) const override;
4783 
4784   virtual bool
4785   validateAsmConstraint(const char *&Name,
4786                         TargetInfo::ConstraintInfo &Info) const override {
4787     switch (*Name) {
4788     default:
4789       return false;
4790     case 'w': // Floating point and SIMD registers (V0-V31)
4791       Info.setAllowsRegister();
4792       return true;
4793     case 'I': // Constant that can be used with an ADD instruction
4794     case 'J': // Constant that can be used with a SUB instruction
4795     case 'K': // Constant that can be used with a 32-bit logical instruction
4796     case 'L': // Constant that can be used with a 64-bit logical instruction
4797     case 'M': // Constant that can be used as a 32-bit MOV immediate
4798     case 'N': // Constant that can be used as a 64-bit MOV immediate
4799     case 'Y': // Floating point constant zero
4800     case 'Z': // Integer constant zero
4801       return true;
4802     case 'Q': // A memory reference with base register and no offset
4803       Info.setAllowsMemory();
4804       return true;
4805     case 'S': // A symbolic address
4806       Info.setAllowsRegister();
4807       return true;
4808     case 'U':
4809       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
4810       // Utf: A memory address suitable for ldp/stp in TF mode.
4811       // Usa: An absolute symbolic address.
4812       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
4813       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
4814     case 'z': // Zero register, wzr or xzr
4815       Info.setAllowsRegister();
4816       return true;
4817     case 'x': // Floating point and SIMD registers (V0-V15)
4818       Info.setAllowsRegister();
4819       return true;
4820     }
4821     return false;
4822   }
4823 
4824   bool
4825   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4826                              std::string &SuggestedModifier) const override {
4827     // Strip off constraint modifiers.
4828     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4829       Constraint = Constraint.substr(1);
4830 
4831     switch (Constraint[0]) {
4832     default:
4833       return true;
4834     case 'z':
4835     case 'r': {
4836       switch (Modifier) {
4837       case 'x':
4838       case 'w':
4839         // For now assume that the person knows what they're
4840         // doing with the modifier.
4841         return true;
4842       default:
4843         // By default an 'r' constraint will be in the 'x'
4844         // registers.
4845         if (Size == 64)
4846           return true;
4847 
4848         SuggestedModifier = "w";
4849         return false;
4850       }
4851     }
4852     }
4853   }
4854 
4855   const char *getClobbers() const override { return ""; }
4856 
4857   int getEHDataRegisterNumber(unsigned RegNo) const override {
4858     if (RegNo == 0)
4859       return 0;
4860     if (RegNo == 1)
4861       return 1;
4862     return -1;
4863   }
4864 };
4865 
4866 const char *const AArch64TargetInfo::GCCRegNames[] = {
4867   // 32-bit Integer registers
4868   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4869   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4870   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4871 
4872   // 64-bit Integer registers
4873   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4874   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4875   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4876 
4877   // 32-bit floating point regsisters
4878   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4879   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4880   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4881 
4882   // 64-bit floating point regsisters
4883   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4884   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4885   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4886 
4887   // Vector registers
4888   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4889   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4890   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4891 };
4892 
4893 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4894                                      unsigned &NumNames) const {
4895   Names = GCCRegNames;
4896   NumNames = llvm::array_lengthof(GCCRegNames);
4897 }
4898 
4899 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4900   { { "w31" }, "wsp" },
4901   { { "x29" }, "fp" },
4902   { { "x30" }, "lr" },
4903   { { "x31" }, "sp" },
4904   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4905   // don't want to substitute one of these for a different-sized one.
4906 };
4907 
4908 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4909                                        unsigned &NumAliases) const {
4910   Aliases = GCCRegAliases;
4911   NumAliases = llvm::array_lengthof(GCCRegAliases);
4912 }
4913 
4914 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4915 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4916   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4917 #include "clang/Basic/BuiltinsNEON.def"
4918 
4919 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4920   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4921 #include "clang/Basic/BuiltinsAArch64.def"
4922 };
4923 
4924 class AArch64leTargetInfo : public AArch64TargetInfo {
4925   void setDescriptionString() override {
4926     if (getTriple().isOSBinFormatMachO())
4927       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4928     else
4929       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4930   }
4931 
4932 public:
4933   AArch64leTargetInfo(const llvm::Triple &Triple)
4934     : AArch64TargetInfo(Triple) {
4935     BigEndian = false;
4936     }
4937   void getTargetDefines(const LangOptions &Opts,
4938                         MacroBuilder &Builder) const override {
4939     Builder.defineMacro("__AARCH64EL__");
4940     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4941   }
4942 };
4943 
4944 class AArch64beTargetInfo : public AArch64TargetInfo {
4945   void setDescriptionString() override {
4946     assert(!getTriple().isOSBinFormatMachO());
4947     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4948   }
4949 
4950 public:
4951   AArch64beTargetInfo(const llvm::Triple &Triple)
4952     : AArch64TargetInfo(Triple) { }
4953   void getTargetDefines(const LangOptions &Opts,
4954                         MacroBuilder &Builder) const override {
4955     Builder.defineMacro("__AARCH64EB__");
4956     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4957     Builder.defineMacro("__ARM_BIG_ENDIAN");
4958     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4959   }
4960 };
4961 } // end anonymous namespace.
4962 
4963 namespace {
4964 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4965 protected:
4966   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4967                     MacroBuilder &Builder) const override {
4968     Builder.defineMacro("__AARCH64_SIMD__");
4969     Builder.defineMacro("__ARM64_ARCH_8__");
4970     Builder.defineMacro("__ARM_NEON__");
4971     Builder.defineMacro("__LITTLE_ENDIAN__");
4972     Builder.defineMacro("__REGISTER_PREFIX__", "");
4973     Builder.defineMacro("__arm64", "1");
4974     Builder.defineMacro("__arm64__", "1");
4975 
4976     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4977   }
4978 
4979 public:
4980   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4981       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4982     Int64Type = SignedLongLong;
4983     WCharType = SignedInt;
4984     UseSignedCharForObjCBool = false;
4985 
4986     LongDoubleWidth = LongDoubleAlign = 64;
4987     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4988 
4989     TheCXXABI.set(TargetCXXABI::iOS64);
4990   }
4991 
4992   BuiltinVaListKind getBuiltinVaListKind() const override {
4993     return TargetInfo::CharPtrBuiltinVaList;
4994   }
4995 };
4996 } // end anonymous namespace
4997 
4998 namespace {
4999 // Hexagon abstract base class
5000 class HexagonTargetInfo : public TargetInfo {
5001   static const Builtin::Info BuiltinInfo[];
5002   static const char * const GCCRegNames[];
5003   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5004   std::string CPU;
5005 public:
5006   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5007     BigEndian = false;
5008     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5009 
5010     // {} in inline assembly are packet specifiers, not assembly variant
5011     // specifiers.
5012     NoAsmVariants = true;
5013   }
5014 
5015   void getTargetBuiltins(const Builtin::Info *&Records,
5016                          unsigned &NumRecords) const override {
5017     Records = BuiltinInfo;
5018     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5019   }
5020 
5021   bool validateAsmConstraint(const char *&Name,
5022                              TargetInfo::ConstraintInfo &Info) const override {
5023     return true;
5024   }
5025 
5026   void getTargetDefines(const LangOptions &Opts,
5027                         MacroBuilder &Builder) const override;
5028 
5029   bool hasFeature(StringRef Feature) const override {
5030     return Feature == "hexagon";
5031   }
5032 
5033   BuiltinVaListKind getBuiltinVaListKind() const override {
5034     return TargetInfo::CharPtrBuiltinVaList;
5035   }
5036   void getGCCRegNames(const char * const *&Names,
5037                       unsigned &NumNames) const override;
5038   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5039                         unsigned &NumAliases) const override;
5040   const char *getClobbers() const override {
5041     return "";
5042   }
5043 
5044   static const char *getHexagonCPUSuffix(StringRef Name) {
5045     return llvm::StringSwitch<const char*>(Name)
5046       .Case("hexagonv4", "4")
5047       .Case("hexagonv5", "5")
5048       .Default(nullptr);
5049   }
5050 
5051   bool setCPU(const std::string &Name) override {
5052     if (!getHexagonCPUSuffix(Name))
5053       return false;
5054 
5055     CPU = Name;
5056     return true;
5057   }
5058 };
5059 
5060 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5061                                 MacroBuilder &Builder) const {
5062   Builder.defineMacro("qdsp6");
5063   Builder.defineMacro("__qdsp6", "1");
5064   Builder.defineMacro("__qdsp6__", "1");
5065 
5066   Builder.defineMacro("hexagon");
5067   Builder.defineMacro("__hexagon", "1");
5068   Builder.defineMacro("__hexagon__", "1");
5069 
5070   if(CPU == "hexagonv1") {
5071     Builder.defineMacro("__HEXAGON_V1__");
5072     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5073     if(Opts.HexagonQdsp6Compat) {
5074       Builder.defineMacro("__QDSP6_V1__");
5075       Builder.defineMacro("__QDSP6_ARCH__", "1");
5076     }
5077   }
5078   else if(CPU == "hexagonv2") {
5079     Builder.defineMacro("__HEXAGON_V2__");
5080     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5081     if(Opts.HexagonQdsp6Compat) {
5082       Builder.defineMacro("__QDSP6_V2__");
5083       Builder.defineMacro("__QDSP6_ARCH__", "2");
5084     }
5085   }
5086   else if(CPU == "hexagonv3") {
5087     Builder.defineMacro("__HEXAGON_V3__");
5088     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5089     if(Opts.HexagonQdsp6Compat) {
5090       Builder.defineMacro("__QDSP6_V3__");
5091       Builder.defineMacro("__QDSP6_ARCH__", "3");
5092     }
5093   }
5094   else if(CPU == "hexagonv4") {
5095     Builder.defineMacro("__HEXAGON_V4__");
5096     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5097     if(Opts.HexagonQdsp6Compat) {
5098       Builder.defineMacro("__QDSP6_V4__");
5099       Builder.defineMacro("__QDSP6_ARCH__", "4");
5100     }
5101   }
5102   else if(CPU == "hexagonv5") {
5103     Builder.defineMacro("__HEXAGON_V5__");
5104     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5105     if(Opts.HexagonQdsp6Compat) {
5106       Builder.defineMacro("__QDSP6_V5__");
5107       Builder.defineMacro("__QDSP6_ARCH__", "5");
5108     }
5109   }
5110 }
5111 
5112 const char * const HexagonTargetInfo::GCCRegNames[] = {
5113   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5114   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5115   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5116   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5117   "p0", "p1", "p2", "p3",
5118   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5119 };
5120 
5121 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5122                                    unsigned &NumNames) const {
5123   Names = GCCRegNames;
5124   NumNames = llvm::array_lengthof(GCCRegNames);
5125 }
5126 
5127 
5128 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5129   { { "sp" }, "r29" },
5130   { { "fp" }, "r30" },
5131   { { "lr" }, "r31" },
5132  };
5133 
5134 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5135                                      unsigned &NumAliases) const {
5136   Aliases = GCCRegAliases;
5137   NumAliases = llvm::array_lengthof(GCCRegAliases);
5138 }
5139 
5140 
5141 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5142 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5143 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5144                                               ALL_LANGUAGES },
5145 #include "clang/Basic/BuiltinsHexagon.def"
5146 };
5147 }
5148 
5149 
5150 namespace {
5151 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5152 class SparcTargetInfo : public TargetInfo {
5153   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5154   static const char * const GCCRegNames[];
5155   bool SoftFloat;
5156 public:
5157   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5158 
5159   bool handleTargetFeatures(std::vector<std::string> &Features,
5160                             DiagnosticsEngine &Diags) override {
5161     SoftFloat = false;
5162     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5163       if (Features[i] == "+soft-float")
5164         SoftFloat = true;
5165     return true;
5166   }
5167   void getTargetDefines(const LangOptions &Opts,
5168                         MacroBuilder &Builder) const override {
5169     DefineStd(Builder, "sparc", Opts);
5170     Builder.defineMacro("__REGISTER_PREFIX__", "");
5171 
5172     if (SoftFloat)
5173       Builder.defineMacro("SOFT_FLOAT", "1");
5174   }
5175 
5176   bool hasFeature(StringRef Feature) const override {
5177     return llvm::StringSwitch<bool>(Feature)
5178              .Case("softfloat", SoftFloat)
5179              .Case("sparc", true)
5180              .Default(false);
5181   }
5182 
5183   void getTargetBuiltins(const Builtin::Info *&Records,
5184                          unsigned &NumRecords) const override {
5185     // FIXME: Implement!
5186   }
5187   BuiltinVaListKind getBuiltinVaListKind() const override {
5188     return TargetInfo::VoidPtrBuiltinVaList;
5189   }
5190   void getGCCRegNames(const char * const *&Names,
5191                       unsigned &NumNames) const override;
5192   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5193                         unsigned &NumAliases) const override;
5194   bool validateAsmConstraint(const char *&Name,
5195                              TargetInfo::ConstraintInfo &info) const override {
5196     // FIXME: Implement!
5197     switch (*Name) {
5198     case 'I': // Signed 13-bit constant
5199     case 'J': // Zero
5200     case 'K': // 32-bit constant with the low 12 bits clear
5201     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5202     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5203     case 'N': // Same as 'K' but zext (required for SIMode)
5204     case 'O': // The constant 4096
5205       return true;
5206     }
5207     return false;
5208   }
5209   const char *getClobbers() const override {
5210     // FIXME: Implement!
5211     return "";
5212   }
5213 };
5214 
5215 const char * const SparcTargetInfo::GCCRegNames[] = {
5216   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5217   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5218   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5219   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5220 };
5221 
5222 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5223                                      unsigned &NumNames) const {
5224   Names = GCCRegNames;
5225   NumNames = llvm::array_lengthof(GCCRegNames);
5226 }
5227 
5228 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5229   { { "g0" }, "r0" },
5230   { { "g1" }, "r1" },
5231   { { "g2" }, "r2" },
5232   { { "g3" }, "r3" },
5233   { { "g4" }, "r4" },
5234   { { "g5" }, "r5" },
5235   { { "g6" }, "r6" },
5236   { { "g7" }, "r7" },
5237   { { "o0" }, "r8" },
5238   { { "o1" }, "r9" },
5239   { { "o2" }, "r10" },
5240   { { "o3" }, "r11" },
5241   { { "o4" }, "r12" },
5242   { { "o5" }, "r13" },
5243   { { "o6", "sp" }, "r14" },
5244   { { "o7" }, "r15" },
5245   { { "l0" }, "r16" },
5246   { { "l1" }, "r17" },
5247   { { "l2" }, "r18" },
5248   { { "l3" }, "r19" },
5249   { { "l4" }, "r20" },
5250   { { "l5" }, "r21" },
5251   { { "l6" }, "r22" },
5252   { { "l7" }, "r23" },
5253   { { "i0" }, "r24" },
5254   { { "i1" }, "r25" },
5255   { { "i2" }, "r26" },
5256   { { "i3" }, "r27" },
5257   { { "i4" }, "r28" },
5258   { { "i5" }, "r29" },
5259   { { "i6", "fp" }, "r30" },
5260   { { "i7" }, "r31" },
5261 };
5262 
5263 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5264                                        unsigned &NumAliases) const {
5265   Aliases = GCCRegAliases;
5266   NumAliases = llvm::array_lengthof(GCCRegAliases);
5267 }
5268 
5269 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5270 class SparcV8TargetInfo : public SparcTargetInfo {
5271 public:
5272   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5273     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5274   }
5275 
5276   void getTargetDefines(const LangOptions &Opts,
5277                         MacroBuilder &Builder) const override {
5278     SparcTargetInfo::getTargetDefines(Opts, Builder);
5279     Builder.defineMacro("__sparcv8");
5280   }
5281 };
5282 
5283 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5284 class SparcV9TargetInfo : public SparcTargetInfo {
5285 public:
5286   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5287     // FIXME: Support Sparc quad-precision long double?
5288     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5289     // This is an LP64 platform.
5290     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5291 
5292     // OpenBSD uses long long for int64_t and intmax_t.
5293     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5294       IntMaxType = SignedLongLong;
5295     else
5296       IntMaxType = SignedLong;
5297     Int64Type = IntMaxType;
5298 
5299     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5300     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5301     LongDoubleWidth = 128;
5302     LongDoubleAlign = 128;
5303     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5304     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5305   }
5306 
5307   void getTargetDefines(const LangOptions &Opts,
5308                         MacroBuilder &Builder) const override {
5309     SparcTargetInfo::getTargetDefines(Opts, Builder);
5310     Builder.defineMacro("__sparcv9");
5311     Builder.defineMacro("__arch64__");
5312     // Solaris doesn't need these variants, but the BSDs do.
5313     if (getTriple().getOS() != llvm::Triple::Solaris) {
5314       Builder.defineMacro("__sparc64__");
5315       Builder.defineMacro("__sparc_v9__");
5316       Builder.defineMacro("__sparcv9__");
5317     }
5318   }
5319 
5320   bool setCPU(const std::string &Name) override {
5321     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5322       .Case("v9", true)
5323       .Case("ultrasparc", true)
5324       .Case("ultrasparc3", true)
5325       .Case("niagara", true)
5326       .Case("niagara2", true)
5327       .Case("niagara3", true)
5328       .Case("niagara4", true)
5329       .Default(false);
5330 
5331     // No need to store the CPU yet.  There aren't any CPU-specific
5332     // macros to define.
5333     return CPUKnown;
5334   }
5335 };
5336 
5337 } // end anonymous namespace.
5338 
5339 namespace {
5340 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5341 public:
5342   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5343       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5344     SizeType = UnsignedInt;
5345     PtrDiffType = SignedInt;
5346   }
5347 };
5348 } // end anonymous namespace.
5349 
5350 namespace {
5351 class SystemZTargetInfo : public TargetInfo {
5352   static const char *const GCCRegNames[];
5353 
5354 public:
5355   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5356     TLSSupported = true;
5357     IntWidth = IntAlign = 32;
5358     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5359     PointerWidth = PointerAlign = 64;
5360     LongDoubleWidth = 128;
5361     LongDoubleAlign = 64;
5362     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5363     MinGlobalAlign = 16;
5364     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5365     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5366   }
5367   void getTargetDefines(const LangOptions &Opts,
5368                         MacroBuilder &Builder) const override {
5369     Builder.defineMacro("__s390__");
5370     Builder.defineMacro("__s390x__");
5371     Builder.defineMacro("__zarch__");
5372     Builder.defineMacro("__LONG_DOUBLE_128__");
5373   }
5374   void getTargetBuiltins(const Builtin::Info *&Records,
5375                          unsigned &NumRecords) const override {
5376     // FIXME: Implement.
5377     Records = nullptr;
5378     NumRecords = 0;
5379   }
5380 
5381   void getGCCRegNames(const char *const *&Names,
5382                       unsigned &NumNames) const override;
5383   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5384                         unsigned &NumAliases) const override {
5385     // No aliases.
5386     Aliases = nullptr;
5387     NumAliases = 0;
5388   }
5389   bool validateAsmConstraint(const char *&Name,
5390                              TargetInfo::ConstraintInfo &info) const override;
5391   const char *getClobbers() const override {
5392     // FIXME: Is this really right?
5393     return "";
5394   }
5395   BuiltinVaListKind getBuiltinVaListKind() const override {
5396     return TargetInfo::SystemZBuiltinVaList;
5397   }
5398   bool setCPU(const std::string &Name) override {
5399     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5400       .Case("z10", true)
5401       .Case("z196", true)
5402       .Case("zEC12", true)
5403       .Default(false);
5404 
5405     // No need to store the CPU yet.  There aren't any CPU-specific
5406     // macros to define.
5407     return CPUKnown;
5408   }
5409 };
5410 
5411 const char *const SystemZTargetInfo::GCCRegNames[] = {
5412   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5413   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5414   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5415   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5416 };
5417 
5418 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5419                                        unsigned &NumNames) const {
5420   Names = GCCRegNames;
5421   NumNames = llvm::array_lengthof(GCCRegNames);
5422 }
5423 
5424 bool SystemZTargetInfo::
5425 validateAsmConstraint(const char *&Name,
5426                       TargetInfo::ConstraintInfo &Info) const {
5427   switch (*Name) {
5428   default:
5429     return false;
5430 
5431   case 'a': // Address register
5432   case 'd': // Data register (equivalent to 'r')
5433   case 'f': // Floating-point register
5434     Info.setAllowsRegister();
5435     return true;
5436 
5437   case 'I': // Unsigned 8-bit constant
5438   case 'J': // Unsigned 12-bit constant
5439   case 'K': // Signed 16-bit constant
5440   case 'L': // Signed 20-bit displacement (on all targets we support)
5441   case 'M': // 0x7fffffff
5442     return true;
5443 
5444   case 'Q': // Memory with base and unsigned 12-bit displacement
5445   case 'R': // Likewise, plus an index
5446   case 'S': // Memory with base and signed 20-bit displacement
5447   case 'T': // Likewise, plus an index
5448     Info.setAllowsMemory();
5449     return true;
5450   }
5451 }
5452 }
5453 
5454 namespace {
5455   class MSP430TargetInfo : public TargetInfo {
5456     static const char * const GCCRegNames[];
5457   public:
5458     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5459       BigEndian = false;
5460       TLSSupported = false;
5461       IntWidth = 16; IntAlign = 16;
5462       LongWidth = 32; LongLongWidth = 64;
5463       LongAlign = LongLongAlign = 16;
5464       PointerWidth = 16; PointerAlign = 16;
5465       SuitableAlign = 16;
5466       SizeType = UnsignedInt;
5467       IntMaxType = SignedLongLong;
5468       IntPtrType = SignedInt;
5469       PtrDiffType = SignedInt;
5470       SigAtomicType = SignedLong;
5471       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5472     }
5473     void getTargetDefines(const LangOptions &Opts,
5474                           MacroBuilder &Builder) const override {
5475       Builder.defineMacro("MSP430");
5476       Builder.defineMacro("__MSP430__");
5477       // FIXME: defines for different 'flavours' of MCU
5478     }
5479     void getTargetBuiltins(const Builtin::Info *&Records,
5480                            unsigned &NumRecords) const override {
5481       // FIXME: Implement.
5482       Records = nullptr;
5483       NumRecords = 0;
5484     }
5485     bool hasFeature(StringRef Feature) const override {
5486       return Feature == "msp430";
5487     }
5488     void getGCCRegNames(const char * const *&Names,
5489                         unsigned &NumNames) const override;
5490     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5491                           unsigned &NumAliases) const override {
5492       // No aliases.
5493       Aliases = nullptr;
5494       NumAliases = 0;
5495     }
5496     bool
5497     validateAsmConstraint(const char *&Name,
5498                           TargetInfo::ConstraintInfo &info) const override {
5499       // FIXME: implement
5500       switch (*Name) {
5501       case 'K': // the constant 1
5502       case 'L': // constant -1^20 .. 1^19
5503       case 'M': // constant 1-4:
5504         return true;
5505       }
5506       // No target constraints for now.
5507       return false;
5508     }
5509     const char *getClobbers() const override {
5510       // FIXME: Is this really right?
5511       return "";
5512     }
5513     BuiltinVaListKind getBuiltinVaListKind() const override {
5514       // FIXME: implement
5515       return TargetInfo::CharPtrBuiltinVaList;
5516    }
5517   };
5518 
5519   const char * const MSP430TargetInfo::GCCRegNames[] = {
5520     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5521     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5522   };
5523 
5524   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5525                                         unsigned &NumNames) const {
5526     Names = GCCRegNames;
5527     NumNames = llvm::array_lengthof(GCCRegNames);
5528   }
5529 }
5530 
5531 namespace {
5532 
5533   // LLVM and Clang cannot be used directly to output native binaries for
5534   // target, but is used to compile C code to llvm bitcode with correct
5535   // type and alignment information.
5536   //
5537   // TCE uses the llvm bitcode as input and uses it for generating customized
5538   // target processor and program binary. TCE co-design environment is
5539   // publicly available in http://tce.cs.tut.fi
5540 
5541   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5542       3, // opencl_global
5543       4, // opencl_local
5544       5, // opencl_constant
5545       // FIXME: generic has to be added to the target
5546       0, // opencl_generic
5547       0, // cuda_device
5548       0, // cuda_constant
5549       0  // cuda_shared
5550   };
5551 
5552   class TCETargetInfo : public TargetInfo{
5553   public:
5554     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5555       TLSSupported = false;
5556       IntWidth = 32;
5557       LongWidth = LongLongWidth = 32;
5558       PointerWidth = 32;
5559       IntAlign = 32;
5560       LongAlign = LongLongAlign = 32;
5561       PointerAlign = 32;
5562       SuitableAlign = 32;
5563       SizeType = UnsignedInt;
5564       IntMaxType = SignedLong;
5565       IntPtrType = SignedInt;
5566       PtrDiffType = SignedInt;
5567       FloatWidth = 32;
5568       FloatAlign = 32;
5569       DoubleWidth = 32;
5570       DoubleAlign = 32;
5571       LongDoubleWidth = 32;
5572       LongDoubleAlign = 32;
5573       FloatFormat = &llvm::APFloat::IEEEsingle;
5574       DoubleFormat = &llvm::APFloat::IEEEsingle;
5575       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5576       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5577                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5578       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5579       UseAddrSpaceMapMangling = true;
5580     }
5581 
5582     void getTargetDefines(const LangOptions &Opts,
5583                           MacroBuilder &Builder) const override {
5584       DefineStd(Builder, "tce", Opts);
5585       Builder.defineMacro("__TCE__");
5586       Builder.defineMacro("__TCE_V1__");
5587     }
5588     bool hasFeature(StringRef Feature) const override {
5589       return Feature == "tce";
5590     }
5591 
5592     void getTargetBuiltins(const Builtin::Info *&Records,
5593                            unsigned &NumRecords) const override {}
5594     const char *getClobbers() const override {
5595       return "";
5596     }
5597     BuiltinVaListKind getBuiltinVaListKind() const override {
5598       return TargetInfo::VoidPtrBuiltinVaList;
5599     }
5600     void getGCCRegNames(const char * const *&Names,
5601                         unsigned &NumNames) const override {}
5602     bool validateAsmConstraint(const char *&Name,
5603                                TargetInfo::ConstraintInfo &info) const override{
5604       return true;
5605     }
5606     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5607                           unsigned &NumAliases) const override {}
5608   };
5609 }
5610 
5611 namespace {
5612 class MipsTargetInfoBase : public TargetInfo {
5613   virtual void setDescriptionString() = 0;
5614 
5615   static const Builtin::Info BuiltinInfo[];
5616   std::string CPU;
5617   bool IsMips16;
5618   bool IsMicromips;
5619   bool IsNan2008;
5620   bool IsSingleFloat;
5621   enum MipsFloatABI {
5622     HardFloat, SoftFloat
5623   } FloatABI;
5624   enum DspRevEnum {
5625     NoDSP, DSP1, DSP2
5626   } DspRev;
5627   bool HasMSA;
5628 
5629 protected:
5630   bool HasFP64;
5631   std::string ABI;
5632 
5633 public:
5634   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5635                      const std::string &CPUStr)
5636       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5637         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5638         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5639 
5640   bool isNaN2008Default() const {
5641     return CPU == "mips32r6" || CPU == "mips64r6";
5642   }
5643 
5644   bool isFP64Default() const {
5645     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5646   }
5647 
5648   StringRef getABI() const override { return ABI; }
5649   bool setCPU(const std::string &Name) override {
5650     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5651                     getTriple().getArch() == llvm::Triple::mipsel;
5652     CPU = Name;
5653     return llvm::StringSwitch<bool>(Name)
5654         .Case("mips1", IsMips32)
5655         .Case("mips2", IsMips32)
5656         .Case("mips3", true)
5657         .Case("mips4", true)
5658         .Case("mips5", true)
5659         .Case("mips32", IsMips32)
5660         .Case("mips32r2", IsMips32)
5661         .Case("mips32r6", IsMips32)
5662         .Case("mips64", true)
5663         .Case("mips64r2", true)
5664         .Case("mips64r6", true)
5665         .Case("octeon", true)
5666         .Default(false);
5667   }
5668   const std::string& getCPU() const { return CPU; }
5669   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5670     // The backend enables certain ABI's by default according to the
5671     // architecture.
5672     // Disable both possible defaults so that we don't end up with multiple
5673     // ABI's selected and trigger an assertion.
5674     Features["o32"] = false;
5675     Features["n64"] = false;
5676 
5677     Features[ABI] = true;
5678     if (CPU == "octeon")
5679       Features["mips64r2"] = Features["cnmips"] = true;
5680     else
5681       Features[CPU] = true;
5682   }
5683 
5684   void getTargetDefines(const LangOptions &Opts,
5685                         MacroBuilder &Builder) const override {
5686     Builder.defineMacro("__mips__");
5687     Builder.defineMacro("_mips");
5688     if (Opts.GNUMode)
5689       Builder.defineMacro("mips");
5690 
5691     Builder.defineMacro("__REGISTER_PREFIX__", "");
5692 
5693     switch (FloatABI) {
5694     case HardFloat:
5695       Builder.defineMacro("__mips_hard_float", Twine(1));
5696       break;
5697     case SoftFloat:
5698       Builder.defineMacro("__mips_soft_float", Twine(1));
5699       break;
5700     }
5701 
5702     if (IsSingleFloat)
5703       Builder.defineMacro("__mips_single_float", Twine(1));
5704 
5705     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5706     Builder.defineMacro("_MIPS_FPSET",
5707                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5708 
5709     if (IsMips16)
5710       Builder.defineMacro("__mips16", Twine(1));
5711 
5712     if (IsMicromips)
5713       Builder.defineMacro("__mips_micromips", Twine(1));
5714 
5715     if (IsNan2008)
5716       Builder.defineMacro("__mips_nan2008", Twine(1));
5717 
5718     switch (DspRev) {
5719     default:
5720       break;
5721     case DSP1:
5722       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5723       Builder.defineMacro("__mips_dsp", Twine(1));
5724       break;
5725     case DSP2:
5726       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5727       Builder.defineMacro("__mips_dspr2", Twine(1));
5728       Builder.defineMacro("__mips_dsp", Twine(1));
5729       break;
5730     }
5731 
5732     if (HasMSA)
5733       Builder.defineMacro("__mips_msa", Twine(1));
5734 
5735     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5736     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5737     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5738 
5739     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5740     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5741   }
5742 
5743   void getTargetBuiltins(const Builtin::Info *&Records,
5744                          unsigned &NumRecords) const override {
5745     Records = BuiltinInfo;
5746     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5747   }
5748   bool hasFeature(StringRef Feature) const override {
5749     return llvm::StringSwitch<bool>(Feature)
5750       .Case("mips", true)
5751       .Case("fp64", HasFP64)
5752       .Default(false);
5753   }
5754   BuiltinVaListKind getBuiltinVaListKind() const override {
5755     return TargetInfo::VoidPtrBuiltinVaList;
5756   }
5757   void getGCCRegNames(const char * const *&Names,
5758                       unsigned &NumNames) const override {
5759     static const char *const GCCRegNames[] = {
5760       // CPU register names
5761       // Must match second column of GCCRegAliases
5762       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5763       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5764       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5765       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5766       // Floating point register names
5767       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5768       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5769       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5770       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5771       // Hi/lo and condition register names
5772       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5773       "$fcc5","$fcc6","$fcc7",
5774       // MSA register names
5775       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5776       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5777       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5778       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5779       // MSA control register names
5780       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5781       "$msarequest", "$msamap", "$msaunmap"
5782     };
5783     Names = GCCRegNames;
5784     NumNames = llvm::array_lengthof(GCCRegNames);
5785   }
5786   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5787                         unsigned &NumAliases) const override = 0;
5788   bool validateAsmConstraint(const char *&Name,
5789                              TargetInfo::ConstraintInfo &Info) const override {
5790     switch (*Name) {
5791     default:
5792       return false;
5793     case 'r': // CPU registers.
5794     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5795     case 'y': // Equivalent to "r", backward compatibility only.
5796     case 'f': // floating-point registers.
5797     case 'c': // $25 for indirect jumps
5798     case 'l': // lo register
5799     case 'x': // hilo register pair
5800       Info.setAllowsRegister();
5801       return true;
5802     case 'I': // Signed 16-bit constant
5803     case 'J': // Integer 0
5804     case 'K': // Unsigned 16-bit constant
5805     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
5806     case 'M': // Constants not loadable via lui, addiu, or ori
5807     case 'N': // Constant -1 to -65535
5808     case 'O': // A signed 15-bit constant
5809     case 'P': // A constant between 1 go 65535
5810       return true;
5811     case 'R': // An address that can be used in a non-macro load or store
5812       Info.setAllowsMemory();
5813       return true;
5814     }
5815   }
5816 
5817   const char *getClobbers() const override {
5818     // In GCC, $1 is not widely used in generated code (it's used only in a few
5819     // specific situations), so there is no real need for users to add it to
5820     // the clobbers list if they want to use it in their inline assembly code.
5821     //
5822     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
5823     // code generation, so using it in inline assembly without adding it to the
5824     // clobbers list can cause conflicts between the inline assembly code and
5825     // the surrounding generated code.
5826     //
5827     // Another problem is that LLVM is allowed to choose $1 for inline assembly
5828     // operands, which will conflict with the ".set at" assembler option (which
5829     // we use only for inline assembly, in order to maintain compatibility with
5830     // GCC) and will also conflict with the user's usage of $1.
5831     //
5832     // The easiest way to avoid these conflicts and keep $1 as an allocatable
5833     // register for generated code is to automatically clobber $1 for all inline
5834     // assembly code.
5835     //
5836     // FIXME: We should automatically clobber $1 only for inline assembly code
5837     // which actually uses it. This would allow LLVM to use $1 for inline
5838     // assembly operands if the user's assembly code doesn't use it.
5839     return "~{$1}";
5840   }
5841 
5842   bool handleTargetFeatures(std::vector<std::string> &Features,
5843                             DiagnosticsEngine &Diags) override {
5844     IsMips16 = false;
5845     IsMicromips = false;
5846     IsNan2008 = isNaN2008Default();
5847     IsSingleFloat = false;
5848     FloatABI = HardFloat;
5849     DspRev = NoDSP;
5850     HasFP64 = isFP64Default();
5851 
5852     for (std::vector<std::string>::iterator it = Features.begin(),
5853          ie = Features.end(); it != ie; ++it) {
5854       if (*it == "+single-float")
5855         IsSingleFloat = true;
5856       else if (*it == "+soft-float")
5857         FloatABI = SoftFloat;
5858       else if (*it == "+mips16")
5859         IsMips16 = true;
5860       else if (*it == "+micromips")
5861         IsMicromips = true;
5862       else if (*it == "+dsp")
5863         DspRev = std::max(DspRev, DSP1);
5864       else if (*it == "+dspr2")
5865         DspRev = std::max(DspRev, DSP2);
5866       else if (*it == "+msa")
5867         HasMSA = true;
5868       else if (*it == "+fp64")
5869         HasFP64 = true;
5870       else if (*it == "-fp64")
5871         HasFP64 = false;
5872       else if (*it == "+nan2008")
5873         IsNan2008 = true;
5874       else if (*it == "-nan2008")
5875         IsNan2008 = false;
5876     }
5877 
5878     // Remove front-end specific options.
5879     std::vector<std::string>::iterator it =
5880       std::find(Features.begin(), Features.end(), "+soft-float");
5881     if (it != Features.end())
5882       Features.erase(it);
5883 
5884     setDescriptionString();
5885 
5886     return true;
5887   }
5888 
5889   int getEHDataRegisterNumber(unsigned RegNo) const override {
5890     if (RegNo == 0) return 4;
5891     if (RegNo == 1) return 5;
5892     return -1;
5893   }
5894 
5895   bool isCLZForZeroUndef() const override { return false; }
5896 };
5897 
5898 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5899 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5900 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5901                                               ALL_LANGUAGES },
5902 #include "clang/Basic/BuiltinsMips.def"
5903 };
5904 
5905 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5906 public:
5907   Mips32TargetInfoBase(const llvm::Triple &Triple)
5908       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5909     SizeType = UnsignedInt;
5910     PtrDiffType = SignedInt;
5911     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5912   }
5913   bool setABI(const std::string &Name) override {
5914     if (Name == "o32" || Name == "eabi") {
5915       ABI = Name;
5916       return true;
5917     }
5918     return false;
5919   }
5920   void getTargetDefines(const LangOptions &Opts,
5921                         MacroBuilder &Builder) const override {
5922     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5923 
5924     Builder.defineMacro("__mips", "32");
5925     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5926 
5927     const std::string& CPUStr = getCPU();
5928     if (CPUStr == "mips32")
5929       Builder.defineMacro("__mips_isa_rev", "1");
5930     else if (CPUStr == "mips32r2")
5931       Builder.defineMacro("__mips_isa_rev", "2");
5932     else if (CPUStr == "mips32r6")
5933       Builder.defineMacro("__mips_isa_rev", "6");
5934 
5935     if (ABI == "o32") {
5936       Builder.defineMacro("__mips_o32");
5937       Builder.defineMacro("_ABIO32", "1");
5938       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5939     }
5940     else if (ABI == "eabi")
5941       Builder.defineMacro("__mips_eabi");
5942     else
5943       llvm_unreachable("Invalid ABI for Mips32.");
5944   }
5945   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5946                         unsigned &NumAliases) const override {
5947     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5948       { { "at" },  "$1" },
5949       { { "v0" },  "$2" },
5950       { { "v1" },  "$3" },
5951       { { "a0" },  "$4" },
5952       { { "a1" },  "$5" },
5953       { { "a2" },  "$6" },
5954       { { "a3" },  "$7" },
5955       { { "t0" },  "$8" },
5956       { { "t1" },  "$9" },
5957       { { "t2" }, "$10" },
5958       { { "t3" }, "$11" },
5959       { { "t4" }, "$12" },
5960       { { "t5" }, "$13" },
5961       { { "t6" }, "$14" },
5962       { { "t7" }, "$15" },
5963       { { "s0" }, "$16" },
5964       { { "s1" }, "$17" },
5965       { { "s2" }, "$18" },
5966       { { "s3" }, "$19" },
5967       { { "s4" }, "$20" },
5968       { { "s5" }, "$21" },
5969       { { "s6" }, "$22" },
5970       { { "s7" }, "$23" },
5971       { { "t8" }, "$24" },
5972       { { "t9" }, "$25" },
5973       { { "k0" }, "$26" },
5974       { { "k1" }, "$27" },
5975       { { "gp" }, "$28" },
5976       { { "sp","$sp" }, "$29" },
5977       { { "fp","$fp" }, "$30" },
5978       { { "ra" }, "$31" }
5979     };
5980     Aliases = GCCRegAliases;
5981     NumAliases = llvm::array_lengthof(GCCRegAliases);
5982   }
5983 };
5984 
5985 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5986   void setDescriptionString() override {
5987     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5988   }
5989 
5990 public:
5991   Mips32EBTargetInfo(const llvm::Triple &Triple)
5992       : Mips32TargetInfoBase(Triple) {
5993   }
5994   void getTargetDefines(const LangOptions &Opts,
5995                         MacroBuilder &Builder) const override {
5996     DefineStd(Builder, "MIPSEB", Opts);
5997     Builder.defineMacro("_MIPSEB");
5998     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5999   }
6000 };
6001 
6002 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6003   void setDescriptionString() override {
6004     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6005   }
6006 
6007 public:
6008   Mips32ELTargetInfo(const llvm::Triple &Triple)
6009       : Mips32TargetInfoBase(Triple) {
6010     BigEndian = false;
6011   }
6012   void getTargetDefines(const LangOptions &Opts,
6013                         MacroBuilder &Builder) const override {
6014     DefineStd(Builder, "MIPSEL", Opts);
6015     Builder.defineMacro("_MIPSEL");
6016     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6017   }
6018 };
6019 
6020 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6021 public:
6022   Mips64TargetInfoBase(const llvm::Triple &Triple)
6023       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6024     LongDoubleWidth = LongDoubleAlign = 128;
6025     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6026     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6027       LongDoubleWidth = LongDoubleAlign = 64;
6028       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6029     }
6030     setN64ABITypes();
6031     SuitableAlign = 128;
6032     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6033   }
6034 
6035   void setN64ABITypes() {
6036     LongWidth = LongAlign = 64;
6037     PointerWidth = PointerAlign = 64;
6038     SizeType = UnsignedLong;
6039     PtrDiffType = SignedLong;
6040   }
6041 
6042   void setN32ABITypes() {
6043     LongWidth = LongAlign = 32;
6044     PointerWidth = PointerAlign = 32;
6045     SizeType = UnsignedInt;
6046     PtrDiffType = SignedInt;
6047   }
6048 
6049   bool setABI(const std::string &Name) override {
6050     if (Name == "n32") {
6051       setN32ABITypes();
6052       ABI = Name;
6053       return true;
6054     }
6055     if (Name == "n64") {
6056       setN64ABITypes();
6057       ABI = Name;
6058       return true;
6059     }
6060     return false;
6061   }
6062 
6063   void getTargetDefines(const LangOptions &Opts,
6064                         MacroBuilder &Builder) const override {
6065     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6066 
6067     Builder.defineMacro("__mips", "64");
6068     Builder.defineMacro("__mips64");
6069     Builder.defineMacro("__mips64__");
6070     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6071 
6072     const std::string& CPUStr = getCPU();
6073     if (CPUStr == "mips64")
6074       Builder.defineMacro("__mips_isa_rev", "1");
6075     else if (CPUStr == "mips64r2")
6076       Builder.defineMacro("__mips_isa_rev", "2");
6077     else if (CPUStr == "mips64r6")
6078       Builder.defineMacro("__mips_isa_rev", "6");
6079 
6080     if (ABI == "n32") {
6081       Builder.defineMacro("__mips_n32");
6082       Builder.defineMacro("_ABIN32", "2");
6083       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6084     }
6085     else if (ABI == "n64") {
6086       Builder.defineMacro("__mips_n64");
6087       Builder.defineMacro("_ABI64", "3");
6088       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6089     }
6090     else
6091       llvm_unreachable("Invalid ABI for Mips64.");
6092   }
6093   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6094                         unsigned &NumAliases) const override {
6095     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6096       { { "at" },  "$1" },
6097       { { "v0" },  "$2" },
6098       { { "v1" },  "$3" },
6099       { { "a0" },  "$4" },
6100       { { "a1" },  "$5" },
6101       { { "a2" },  "$6" },
6102       { { "a3" },  "$7" },
6103       { { "a4" },  "$8" },
6104       { { "a5" },  "$9" },
6105       { { "a6" }, "$10" },
6106       { { "a7" }, "$11" },
6107       { { "t0" }, "$12" },
6108       { { "t1" }, "$13" },
6109       { { "t2" }, "$14" },
6110       { { "t3" }, "$15" },
6111       { { "s0" }, "$16" },
6112       { { "s1" }, "$17" },
6113       { { "s2" }, "$18" },
6114       { { "s3" }, "$19" },
6115       { { "s4" }, "$20" },
6116       { { "s5" }, "$21" },
6117       { { "s6" }, "$22" },
6118       { { "s7" }, "$23" },
6119       { { "t8" }, "$24" },
6120       { { "t9" }, "$25" },
6121       { { "k0" }, "$26" },
6122       { { "k1" }, "$27" },
6123       { { "gp" }, "$28" },
6124       { { "sp","$sp" }, "$29" },
6125       { { "fp","$fp" }, "$30" },
6126       { { "ra" }, "$31" }
6127     };
6128     Aliases = GCCRegAliases;
6129     NumAliases = llvm::array_lengthof(GCCRegAliases);
6130   }
6131 
6132   bool hasInt128Type() const override { return true; }
6133 };
6134 
6135 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6136   void setDescriptionString() override {
6137     if (ABI == "n32")
6138       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6139     else
6140       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6141 
6142   }
6143 
6144 public:
6145   Mips64EBTargetInfo(const llvm::Triple &Triple)
6146       : Mips64TargetInfoBase(Triple) {}
6147   void getTargetDefines(const LangOptions &Opts,
6148                         MacroBuilder &Builder) const override {
6149     DefineStd(Builder, "MIPSEB", Opts);
6150     Builder.defineMacro("_MIPSEB");
6151     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6152   }
6153 };
6154 
6155 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6156   void setDescriptionString() override {
6157     if (ABI == "n32")
6158       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6159     else
6160       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6161   }
6162 public:
6163   Mips64ELTargetInfo(const llvm::Triple &Triple)
6164       : Mips64TargetInfoBase(Triple) {
6165     // Default ABI is n64.
6166     BigEndian = false;
6167   }
6168   void getTargetDefines(const LangOptions &Opts,
6169                         MacroBuilder &Builder) const override {
6170     DefineStd(Builder, "MIPSEL", Opts);
6171     Builder.defineMacro("_MIPSEL");
6172     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6173   }
6174 };
6175 } // end anonymous namespace.
6176 
6177 namespace {
6178 class PNaClTargetInfo : public TargetInfo {
6179 public:
6180   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6181     BigEndian = false;
6182     this->UserLabelPrefix = "";
6183     this->LongAlign = 32;
6184     this->LongWidth = 32;
6185     this->PointerAlign = 32;
6186     this->PointerWidth = 32;
6187     this->IntMaxType = TargetInfo::SignedLongLong;
6188     this->Int64Type = TargetInfo::SignedLongLong;
6189     this->DoubleAlign = 64;
6190     this->LongDoubleWidth = 64;
6191     this->LongDoubleAlign = 64;
6192     this->SizeType = TargetInfo::UnsignedInt;
6193     this->PtrDiffType = TargetInfo::SignedInt;
6194     this->IntPtrType = TargetInfo::SignedInt;
6195     this->RegParmMax = 0; // Disallow regparm
6196   }
6197 
6198   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6199   }
6200   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6201     Builder.defineMacro("__le32__");
6202     Builder.defineMacro("__pnacl__");
6203   }
6204   void getTargetDefines(const LangOptions &Opts,
6205                         MacroBuilder &Builder) const override {
6206     getArchDefines(Opts, Builder);
6207   }
6208   bool hasFeature(StringRef Feature) const override {
6209     return Feature == "pnacl";
6210   }
6211   void getTargetBuiltins(const Builtin::Info *&Records,
6212                          unsigned &NumRecords) const override {
6213   }
6214   BuiltinVaListKind getBuiltinVaListKind() const override {
6215     return TargetInfo::PNaClABIBuiltinVaList;
6216   }
6217   void getGCCRegNames(const char * const *&Names,
6218                       unsigned &NumNames) const override;
6219   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6220                         unsigned &NumAliases) const override;
6221   bool validateAsmConstraint(const char *&Name,
6222                              TargetInfo::ConstraintInfo &Info) const override {
6223     return false;
6224   }
6225 
6226   const char *getClobbers() const override {
6227     return "";
6228   }
6229 };
6230 
6231 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6232                                      unsigned &NumNames) const {
6233   Names = nullptr;
6234   NumNames = 0;
6235 }
6236 
6237 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6238                                        unsigned &NumAliases) const {
6239   Aliases = nullptr;
6240   NumAliases = 0;
6241 }
6242 } // end anonymous namespace.
6243 
6244 namespace {
6245 class Le64TargetInfo : public TargetInfo {
6246   static const Builtin::Info BuiltinInfo[];
6247 
6248 public:
6249   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6250     BigEndian = false;
6251     NoAsmVariants = true;
6252     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6253     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6254     DescriptionString =
6255         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6256   }
6257 
6258   void getTargetDefines(const LangOptions &Opts,
6259                         MacroBuilder &Builder) const override {
6260     DefineStd(Builder, "unix", Opts);
6261     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6262     Builder.defineMacro("__ELF__");
6263   }
6264   void getTargetBuiltins(const Builtin::Info *&Records,
6265                          unsigned &NumRecords) const override {
6266     Records = BuiltinInfo;
6267     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6268   }
6269   BuiltinVaListKind getBuiltinVaListKind() const override {
6270     return TargetInfo::PNaClABIBuiltinVaList;
6271   }
6272   const char *getClobbers() const override { return ""; }
6273   void getGCCRegNames(const char *const *&Names,
6274                       unsigned &NumNames) const override {
6275     Names = nullptr;
6276     NumNames = 0;
6277   }
6278   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6279                         unsigned &NumAliases) const override {
6280     Aliases = nullptr;
6281     NumAliases = 0;
6282   }
6283   bool validateAsmConstraint(const char *&Name,
6284                              TargetInfo::ConstraintInfo &Info) const override {
6285     return false;
6286   }
6287 
6288   bool hasProtectedVisibility() const override { return false; }
6289 };
6290 } // end anonymous namespace.
6291 
6292 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6293 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6294   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6295 #include "clang/Basic/BuiltinsLe64.def"
6296 };
6297 
6298 namespace {
6299   static const unsigned SPIRAddrSpaceMap[] = {
6300     1,    // opencl_global
6301     3,    // opencl_local
6302     2,    // opencl_constant
6303     4,    // opencl_generic
6304     0,    // cuda_device
6305     0,    // cuda_constant
6306     0     // cuda_shared
6307   };
6308   class SPIRTargetInfo : public TargetInfo {
6309   public:
6310     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6311       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6312         "SPIR target must use unknown OS");
6313       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6314         "SPIR target must use unknown environment type");
6315       BigEndian = false;
6316       TLSSupported = false;
6317       LongWidth = LongAlign = 64;
6318       AddrSpaceMap = &SPIRAddrSpaceMap;
6319       UseAddrSpaceMapMangling = true;
6320       // Define available target features
6321       // These must be defined in sorted order!
6322       NoAsmVariants = true;
6323     }
6324     void getTargetDefines(const LangOptions &Opts,
6325                           MacroBuilder &Builder) const override {
6326       DefineStd(Builder, "SPIR", Opts);
6327     }
6328     bool hasFeature(StringRef Feature) const override {
6329       return Feature == "spir";
6330     }
6331 
6332     void getTargetBuiltins(const Builtin::Info *&Records,
6333                            unsigned &NumRecords) const override {}
6334     const char *getClobbers() const override {
6335       return "";
6336     }
6337     void getGCCRegNames(const char * const *&Names,
6338                         unsigned &NumNames) const override {}
6339     bool
6340     validateAsmConstraint(const char *&Name,
6341                           TargetInfo::ConstraintInfo &info) const override {
6342       return true;
6343     }
6344     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6345                           unsigned &NumAliases) const override {}
6346     BuiltinVaListKind getBuiltinVaListKind() const override {
6347       return TargetInfo::VoidPtrBuiltinVaList;
6348     }
6349 
6350     CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6351       return (CC == CC_SpirFunction ||
6352               CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6353     }
6354 
6355     CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6356       return CC_SpirFunction;
6357     }
6358   };
6359 
6360 
6361   class SPIR32TargetInfo : public SPIRTargetInfo {
6362   public:
6363     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6364       PointerWidth = PointerAlign = 32;
6365       SizeType     = TargetInfo::UnsignedInt;
6366       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6367       DescriptionString
6368         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6369           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6370     }
6371     void getTargetDefines(const LangOptions &Opts,
6372                           MacroBuilder &Builder) const override {
6373       DefineStd(Builder, "SPIR32", Opts);
6374     }
6375   };
6376 
6377   class SPIR64TargetInfo : public SPIRTargetInfo {
6378   public:
6379     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6380       PointerWidth = PointerAlign = 64;
6381       SizeType     = TargetInfo::UnsignedLong;
6382       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6383       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6384                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6385     }
6386     void getTargetDefines(const LangOptions &Opts,
6387                           MacroBuilder &Builder) const override {
6388       DefineStd(Builder, "SPIR64", Opts);
6389     }
6390   };
6391 }
6392 
6393 namespace {
6394 class XCoreTargetInfo : public TargetInfo {
6395   static const Builtin::Info BuiltinInfo[];
6396 public:
6397   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6398     BigEndian = false;
6399     NoAsmVariants = true;
6400     LongLongAlign = 32;
6401     SuitableAlign = 32;
6402     DoubleAlign = LongDoubleAlign = 32;
6403     SizeType = UnsignedInt;
6404     PtrDiffType = SignedInt;
6405     IntPtrType = SignedInt;
6406     WCharType = UnsignedChar;
6407     WIntType = UnsignedInt;
6408     UseZeroLengthBitfieldAlignment = true;
6409     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6410                         "-f64:32-a:0:32-n32";
6411   }
6412   void getTargetDefines(const LangOptions &Opts,
6413                         MacroBuilder &Builder) const override {
6414     Builder.defineMacro("__XS1B__");
6415   }
6416   void getTargetBuiltins(const Builtin::Info *&Records,
6417                          unsigned &NumRecords) const override {
6418     Records = BuiltinInfo;
6419     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6420   }
6421   BuiltinVaListKind getBuiltinVaListKind() const override {
6422     return TargetInfo::VoidPtrBuiltinVaList;
6423   }
6424   const char *getClobbers() const override {
6425     return "";
6426   }
6427   void getGCCRegNames(const char * const *&Names,
6428                       unsigned &NumNames) const override {
6429     static const char * const GCCRegNames[] = {
6430       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6431       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6432     };
6433     Names = GCCRegNames;
6434     NumNames = llvm::array_lengthof(GCCRegNames);
6435   }
6436   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6437                         unsigned &NumAliases) const override {
6438     Aliases = nullptr;
6439     NumAliases = 0;
6440   }
6441   bool validateAsmConstraint(const char *&Name,
6442                              TargetInfo::ConstraintInfo &Info) const override {
6443     return false;
6444   }
6445   int getEHDataRegisterNumber(unsigned RegNo) const override {
6446     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6447     return (RegNo < 2)? RegNo : -1;
6448   }
6449 };
6450 
6451 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6452 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6453 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6454                                               ALL_LANGUAGES },
6455 #include "clang/Basic/BuiltinsXCore.def"
6456 };
6457 } // end anonymous namespace.
6458 
6459 
6460 //===----------------------------------------------------------------------===//
6461 // Driver code
6462 //===----------------------------------------------------------------------===//
6463 
6464 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6465   llvm::Triple::OSType os = Triple.getOS();
6466 
6467   switch (Triple.getArch()) {
6468   default:
6469     return nullptr;
6470 
6471   case llvm::Triple::xcore:
6472     return new XCoreTargetInfo(Triple);
6473 
6474   case llvm::Triple::hexagon:
6475     return new HexagonTargetInfo(Triple);
6476 
6477   case llvm::Triple::aarch64:
6478     if (Triple.isOSDarwin())
6479       return new DarwinAArch64TargetInfo(Triple);
6480 
6481     switch (os) {
6482     case llvm::Triple::FreeBSD:
6483       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6484     case llvm::Triple::Linux:
6485       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6486     case llvm::Triple::NetBSD:
6487       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6488     default:
6489       return new AArch64leTargetInfo(Triple);
6490     }
6491 
6492   case llvm::Triple::aarch64_be:
6493     switch (os) {
6494     case llvm::Triple::FreeBSD:
6495       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6496     case llvm::Triple::Linux:
6497       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6498     case llvm::Triple::NetBSD:
6499       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6500     default:
6501       return new AArch64beTargetInfo(Triple);
6502     }
6503 
6504   case llvm::Triple::arm:
6505   case llvm::Triple::thumb:
6506     if (Triple.isOSBinFormatMachO())
6507       return new DarwinARMTargetInfo(Triple);
6508 
6509     switch (os) {
6510     case llvm::Triple::Linux:
6511       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6512     case llvm::Triple::FreeBSD:
6513       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6514     case llvm::Triple::NetBSD:
6515       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6516     case llvm::Triple::OpenBSD:
6517       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6518     case llvm::Triple::Bitrig:
6519       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6520     case llvm::Triple::RTEMS:
6521       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6522     case llvm::Triple::NaCl:
6523       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6524     case llvm::Triple::Win32:
6525       switch (Triple.getEnvironment()) {
6526       default:
6527         return new ARMleTargetInfo(Triple);
6528       case llvm::Triple::Itanium:
6529         return new ItaniumWindowsARMleTargetInfo(Triple);
6530       case llvm::Triple::MSVC:
6531         return new MicrosoftARMleTargetInfo(Triple);
6532       }
6533     default:
6534       return new ARMleTargetInfo(Triple);
6535     }
6536 
6537   case llvm::Triple::armeb:
6538   case llvm::Triple::thumbeb:
6539     if (Triple.isOSDarwin())
6540       return new DarwinARMTargetInfo(Triple);
6541 
6542     switch (os) {
6543     case llvm::Triple::Linux:
6544       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6545     case llvm::Triple::FreeBSD:
6546       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6547     case llvm::Triple::NetBSD:
6548       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6549     case llvm::Triple::OpenBSD:
6550       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6551     case llvm::Triple::Bitrig:
6552       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6553     case llvm::Triple::RTEMS:
6554       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6555     case llvm::Triple::NaCl:
6556       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6557     default:
6558       return new ARMbeTargetInfo(Triple);
6559     }
6560 
6561   case llvm::Triple::msp430:
6562     return new MSP430TargetInfo(Triple);
6563 
6564   case llvm::Triple::mips:
6565     switch (os) {
6566     case llvm::Triple::Linux:
6567       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6568     case llvm::Triple::RTEMS:
6569       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6570     case llvm::Triple::FreeBSD:
6571       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6572     case llvm::Triple::NetBSD:
6573       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6574     default:
6575       return new Mips32EBTargetInfo(Triple);
6576     }
6577 
6578   case llvm::Triple::mipsel:
6579     switch (os) {
6580     case llvm::Triple::Linux:
6581       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6582     case llvm::Triple::RTEMS:
6583       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6584     case llvm::Triple::FreeBSD:
6585       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6586     case llvm::Triple::NetBSD:
6587       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6588     case llvm::Triple::NaCl:
6589       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6590     default:
6591       return new Mips32ELTargetInfo(Triple);
6592     }
6593 
6594   case llvm::Triple::mips64:
6595     switch (os) {
6596     case llvm::Triple::Linux:
6597       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6598     case llvm::Triple::RTEMS:
6599       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6600     case llvm::Triple::FreeBSD:
6601       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6602     case llvm::Triple::NetBSD:
6603       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6604     case llvm::Triple::OpenBSD:
6605       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6606     default:
6607       return new Mips64EBTargetInfo(Triple);
6608     }
6609 
6610   case llvm::Triple::mips64el:
6611     switch (os) {
6612     case llvm::Triple::Linux:
6613       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6614     case llvm::Triple::RTEMS:
6615       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6616     case llvm::Triple::FreeBSD:
6617       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6618     case llvm::Triple::NetBSD:
6619       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6620     case llvm::Triple::OpenBSD:
6621       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6622     default:
6623       return new Mips64ELTargetInfo(Triple);
6624     }
6625 
6626   case llvm::Triple::le32:
6627     switch (os) {
6628       case llvm::Triple::NaCl:
6629         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6630       default:
6631         return nullptr;
6632     }
6633 
6634   case llvm::Triple::le64:
6635     return new Le64TargetInfo(Triple);
6636 
6637   case llvm::Triple::ppc:
6638     if (Triple.isOSDarwin())
6639       return new DarwinPPC32TargetInfo(Triple);
6640     switch (os) {
6641     case llvm::Triple::Linux:
6642       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6643     case llvm::Triple::FreeBSD:
6644       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6645     case llvm::Triple::NetBSD:
6646       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6647     case llvm::Triple::OpenBSD:
6648       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6649     case llvm::Triple::RTEMS:
6650       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6651     default:
6652       return new PPC32TargetInfo(Triple);
6653     }
6654 
6655   case llvm::Triple::ppc64:
6656     if (Triple.isOSDarwin())
6657       return new DarwinPPC64TargetInfo(Triple);
6658     switch (os) {
6659     case llvm::Triple::Linux:
6660       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6661     case llvm::Triple::Lv2:
6662       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6663     case llvm::Triple::FreeBSD:
6664       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6665     case llvm::Triple::NetBSD:
6666       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6667     default:
6668       return new PPC64TargetInfo(Triple);
6669     }
6670 
6671   case llvm::Triple::ppc64le:
6672     switch (os) {
6673     case llvm::Triple::Linux:
6674       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6675     default:
6676       return new PPC64TargetInfo(Triple);
6677     }
6678 
6679   case llvm::Triple::nvptx:
6680     return new NVPTX32TargetInfo(Triple);
6681   case llvm::Triple::nvptx64:
6682     return new NVPTX64TargetInfo(Triple);
6683 
6684   case llvm::Triple::amdgcn:
6685   case llvm::Triple::r600:
6686     return new R600TargetInfo(Triple);
6687 
6688   case llvm::Triple::sparc:
6689     switch (os) {
6690     case llvm::Triple::Linux:
6691       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6692     case llvm::Triple::Solaris:
6693       return new SolarisSparcV8TargetInfo(Triple);
6694     case llvm::Triple::NetBSD:
6695       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6696     case llvm::Triple::OpenBSD:
6697       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6698     case llvm::Triple::RTEMS:
6699       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6700     default:
6701       return new SparcV8TargetInfo(Triple);
6702     }
6703 
6704   case llvm::Triple::sparcv9:
6705     switch (os) {
6706     case llvm::Triple::Linux:
6707       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6708     case llvm::Triple::Solaris:
6709       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6710     case llvm::Triple::NetBSD:
6711       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6712     case llvm::Triple::OpenBSD:
6713       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6714     case llvm::Triple::FreeBSD:
6715       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6716     default:
6717       return new SparcV9TargetInfo(Triple);
6718     }
6719 
6720   case llvm::Triple::systemz:
6721     switch (os) {
6722     case llvm::Triple::Linux:
6723       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6724     default:
6725       return new SystemZTargetInfo(Triple);
6726     }
6727 
6728   case llvm::Triple::tce:
6729     return new TCETargetInfo(Triple);
6730 
6731   case llvm::Triple::x86:
6732     if (Triple.isOSDarwin())
6733       return new DarwinI386TargetInfo(Triple);
6734 
6735     switch (os) {
6736     case llvm::Triple::Linux:
6737       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6738     case llvm::Triple::DragonFly:
6739       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6740     case llvm::Triple::NetBSD:
6741       return new NetBSDI386TargetInfo(Triple);
6742     case llvm::Triple::OpenBSD:
6743       return new OpenBSDI386TargetInfo(Triple);
6744     case llvm::Triple::Bitrig:
6745       return new BitrigI386TargetInfo(Triple);
6746     case llvm::Triple::FreeBSD:
6747       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6748     case llvm::Triple::KFreeBSD:
6749       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6750     case llvm::Triple::Minix:
6751       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6752     case llvm::Triple::Solaris:
6753       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6754     case llvm::Triple::Win32: {
6755       switch (Triple.getEnvironment()) {
6756       default:
6757         return new X86_32TargetInfo(Triple);
6758       case llvm::Triple::Cygnus:
6759         return new CygwinX86_32TargetInfo(Triple);
6760       case llvm::Triple::GNU:
6761         return new MinGWX86_32TargetInfo(Triple);
6762       case llvm::Triple::Itanium:
6763       case llvm::Triple::MSVC:
6764         return new MicrosoftX86_32TargetInfo(Triple);
6765       }
6766     }
6767     case llvm::Triple::Haiku:
6768       return new HaikuX86_32TargetInfo(Triple);
6769     case llvm::Triple::RTEMS:
6770       return new RTEMSX86_32TargetInfo(Triple);
6771     case llvm::Triple::NaCl:
6772       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6773     default:
6774       return new X86_32TargetInfo(Triple);
6775     }
6776 
6777   case llvm::Triple::x86_64:
6778     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6779       return new DarwinX86_64TargetInfo(Triple);
6780 
6781     switch (os) {
6782     case llvm::Triple::Linux:
6783       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6784     case llvm::Triple::DragonFly:
6785       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6786     case llvm::Triple::NetBSD:
6787       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6788     case llvm::Triple::OpenBSD:
6789       return new OpenBSDX86_64TargetInfo(Triple);
6790     case llvm::Triple::Bitrig:
6791       return new BitrigX86_64TargetInfo(Triple);
6792     case llvm::Triple::FreeBSD:
6793       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6794     case llvm::Triple::KFreeBSD:
6795       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6796     case llvm::Triple::Solaris:
6797       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6798     case llvm::Triple::Win32: {
6799       switch (Triple.getEnvironment()) {
6800       default:
6801         return new X86_64TargetInfo(Triple);
6802       case llvm::Triple::GNU:
6803         return new MinGWX86_64TargetInfo(Triple);
6804       case llvm::Triple::MSVC:
6805         return new MicrosoftX86_64TargetInfo(Triple);
6806       }
6807     }
6808     case llvm::Triple::NaCl:
6809       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6810     default:
6811       return new X86_64TargetInfo(Triple);
6812     }
6813 
6814     case llvm::Triple::spir: {
6815       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6816           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6817         return nullptr;
6818       return new SPIR32TargetInfo(Triple);
6819     }
6820     case llvm::Triple::spir64: {
6821       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6822           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6823         return nullptr;
6824       return new SPIR64TargetInfo(Triple);
6825     }
6826   }
6827 }
6828 
6829 /// CreateTargetInfo - Return the target info object for the specified target
6830 /// triple.
6831 TargetInfo *
6832 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6833                              const std::shared_ptr<TargetOptions> &Opts) {
6834   llvm::Triple Triple(Opts->Triple);
6835 
6836   // Construct the target
6837   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6838   if (!Target) {
6839     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6840     return nullptr;
6841   }
6842   Target->TargetOpts = Opts;
6843 
6844   // Set the target CPU if specified.
6845   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6846     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6847     return nullptr;
6848   }
6849 
6850   // Set the target ABI if specified.
6851   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6852     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6853     return nullptr;
6854   }
6855 
6856   // Set the fp math unit.
6857   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6858     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6859     return nullptr;
6860   }
6861 
6862   // Compute the default target features, we need the target to handle this
6863   // because features may have dependencies on one another.
6864   llvm::StringMap<bool> Features;
6865   Target->getDefaultFeatures(Features);
6866 
6867   // Apply the user specified deltas.
6868   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6869        I < N; ++I) {
6870     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6871     // Apply the feature via the target.
6872     bool Enabled = Name[0] == '+';
6873     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6874   }
6875 
6876   // Add the features to the compile options.
6877   //
6878   // FIXME: If we are completely confident that we have the right set, we only
6879   // need to pass the minuses.
6880   Opts->Features.clear();
6881   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6882          ie = Features.end(); it != ie; ++it)
6883     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6884   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6885     return nullptr;
6886 
6887   return Target.release();
6888 }
6889