1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 virtual std::string isValidSectionSpecifier(StringRef SR) const { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 virtual const char *getStaticInitSectionSpecifier() const { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 virtual bool hasProtectedVisibility() const { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 virtual const char *getStaticInitSectionSpecifier() const { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 486 } 487 }; 488 489 // AuroraUX target 490 template<typename Target> 491 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const { 495 DefineStd(Builder, "sun", Opts); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 Builder.defineMacro("__svr4__"); 499 Builder.defineMacro("__SVR4"); 500 } 501 public: 502 AuroraUXTargetInfo(const llvm::Triple &Triple) 503 : OSTargetInfo<Target>(Triple) { 504 this->UserLabelPrefix = ""; 505 this->WCharType = this->SignedLong; 506 // FIXME: WIntType should be SignedLong 507 } 508 }; 509 510 // Solaris target 511 template<typename Target> 512 class SolarisTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 522 // newer, but to 500 for everything else. feature_test.h has a check to 523 // ensure that you are not using C99 with an old version of X/Open or C89 524 // with a new version. 525 if (Opts.C99 || Opts.C11) 526 Builder.defineMacro("_XOPEN_SOURCE", "600"); 527 else 528 Builder.defineMacro("_XOPEN_SOURCE", "500"); 529 if (Opts.CPlusPlus) 530 Builder.defineMacro("__C99FEATURES__"); 531 Builder.defineMacro("_LARGEFILE_SOURCE"); 532 Builder.defineMacro("_LARGEFILE64_SOURCE"); 533 Builder.defineMacro("__EXTENSIONS__"); 534 Builder.defineMacro("_REENTRANT"); 535 } 536 public: 537 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 538 this->UserLabelPrefix = ""; 539 this->WCharType = this->SignedInt; 540 // FIXME: WIntType should be SignedLong 541 } 542 }; 543 544 // Windows target 545 template<typename Target> 546 class WindowsTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const { 550 Builder.defineMacro("_WIN32"); 551 } 552 void getVisualStudioDefines(const LangOptions &Opts, 553 MacroBuilder &Builder) const { 554 if (Opts.CPlusPlus) { 555 if (Opts.RTTI) 556 Builder.defineMacro("_CPPRTTI"); 557 558 if (Opts.Exceptions) 559 Builder.defineMacro("_CPPUNWIND"); 560 } 561 562 if (!Opts.CharIsSigned) 563 Builder.defineMacro("_CHAR_UNSIGNED"); 564 565 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 566 // but it works for now. 567 if (Opts.POSIXThreads) 568 Builder.defineMacro("_MT"); 569 570 if (Opts.MSCVersion != 0) 571 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 572 573 if (Opts.MicrosoftExt) { 574 Builder.defineMacro("_MSC_EXTENSIONS"); 575 576 if (Opts.CPlusPlus11) { 577 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 578 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 579 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 580 } 581 } 582 583 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 584 } 585 586 public: 587 WindowsTargetInfo(const llvm::Triple &Triple) 588 : OSTargetInfo<Target>(Triple) {} 589 }; 590 591 template <typename Target> 592 class NaClTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const { 596 if (Opts.POSIXThreads) 597 Builder.defineMacro("_REENTRANT"); 598 if (Opts.CPlusPlus) 599 Builder.defineMacro("_GNU_SOURCE"); 600 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__native_client__"); 604 } 605 606 public: 607 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 608 this->UserLabelPrefix = ""; 609 this->LongAlign = 32; 610 this->LongWidth = 32; 611 this->PointerAlign = 32; 612 this->PointerWidth = 32; 613 this->IntMaxType = TargetInfo::SignedLongLong; 614 this->UIntMaxType = TargetInfo::UnsignedLongLong; 615 this->Int64Type = TargetInfo::SignedLongLong; 616 this->DoubleAlign = 64; 617 this->LongDoubleWidth = 64; 618 this->LongDoubleAlign = 64; 619 this->LongLongWidth = 64; 620 this->LongLongAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 if (Triple.getArch() == llvm::Triple::arm) { 627 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 628 } else if (Triple.getArch() == llvm::Triple::x86) { 629 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 630 } else if (Triple.getArch() == llvm::Triple::x86_64) { 631 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 632 } else if (Triple.getArch() == llvm::Triple::mipsel) { 633 // Handled on mips' setDescriptionString. 634 } else { 635 assert(Triple.getArch() == llvm::Triple::le32); 636 this->DescriptionString = "e-p:32:32-i64:64"; 637 } 638 } 639 virtual typename Target::CallingConvCheckResult checkCallingConvention( 640 CallingConv CC) const { 641 return CC == CC_PnaclCall ? Target::CCCR_OK : 642 Target::checkCallingConvention(CC); 643 } 644 }; 645 } // end anonymous namespace. 646 647 //===----------------------------------------------------------------------===// 648 // Specific target implementations. 649 //===----------------------------------------------------------------------===// 650 651 namespace { 652 // PPC abstract base class 653 class PPCTargetInfo : public TargetInfo { 654 static const Builtin::Info BuiltinInfo[]; 655 static const char * const GCCRegNames[]; 656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 657 std::string CPU; 658 659 // Target cpu features. 660 bool HasVSX; 661 662 public: 663 PPCTargetInfo(const llvm::Triple &Triple) 664 : TargetInfo(Triple), HasVSX(false) { 665 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 666 LongDoubleWidth = LongDoubleAlign = 128; 667 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 668 } 669 670 /// \brief Flags for architecture specific defines. 671 typedef enum { 672 ArchDefineNone = 0, 673 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 674 ArchDefinePpcgr = 1 << 1, 675 ArchDefinePpcsq = 1 << 2, 676 ArchDefine440 = 1 << 3, 677 ArchDefine603 = 1 << 4, 678 ArchDefine604 = 1 << 5, 679 ArchDefinePwr4 = 1 << 6, 680 ArchDefinePwr5 = 1 << 7, 681 ArchDefinePwr5x = 1 << 8, 682 ArchDefinePwr6 = 1 << 9, 683 ArchDefinePwr6x = 1 << 10, 684 ArchDefinePwr7 = 1 << 11, 685 ArchDefineA2 = 1 << 12, 686 ArchDefineA2q = 1 << 13 687 } ArchDefineTypes; 688 689 // Note: GCC recognizes the following additional cpus: 690 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 691 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 692 // titan, rs64. 693 virtual bool setCPU(const std::string &Name) { 694 bool CPUKnown = llvm::StringSwitch<bool>(Name) 695 .Case("generic", true) 696 .Case("440", true) 697 .Case("450", true) 698 .Case("601", true) 699 .Case("602", true) 700 .Case("603", true) 701 .Case("603e", true) 702 .Case("603ev", true) 703 .Case("604", true) 704 .Case("604e", true) 705 .Case("620", true) 706 .Case("630", true) 707 .Case("g3", true) 708 .Case("7400", true) 709 .Case("g4", true) 710 .Case("7450", true) 711 .Case("g4+", true) 712 .Case("750", true) 713 .Case("970", true) 714 .Case("g5", true) 715 .Case("a2", true) 716 .Case("a2q", true) 717 .Case("e500mc", true) 718 .Case("e5500", true) 719 .Case("power3", true) 720 .Case("pwr3", true) 721 .Case("power4", true) 722 .Case("pwr4", true) 723 .Case("power5", true) 724 .Case("pwr5", true) 725 .Case("power5x", true) 726 .Case("pwr5x", true) 727 .Case("power6", true) 728 .Case("pwr6", true) 729 .Case("power6x", true) 730 .Case("pwr6x", true) 731 .Case("power7", true) 732 .Case("pwr7", true) 733 .Case("powerpc", true) 734 .Case("ppc", true) 735 .Case("powerpc64", true) 736 .Case("ppc64", true) 737 .Case("powerpc64le", true) 738 .Case("ppc64le", true) 739 .Default(false); 740 741 if (CPUKnown) 742 CPU = Name; 743 744 return CPUKnown; 745 } 746 747 virtual void getTargetBuiltins(const Builtin::Info *&Records, 748 unsigned &NumRecords) const { 749 Records = BuiltinInfo; 750 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 751 } 752 753 virtual bool isCLZForZeroUndef() const { return false; } 754 755 virtual void getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const; 757 758 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 759 760 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 761 DiagnosticsEngine &Diags); 762 virtual bool hasFeature(StringRef Feature) const; 763 764 virtual void getGCCRegNames(const char * const *&Names, 765 unsigned &NumNames) const; 766 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 767 unsigned &NumAliases) const; 768 virtual bool validateAsmConstraint(const char *&Name, 769 TargetInfo::ConstraintInfo &Info) const { 770 switch (*Name) { 771 default: return false; 772 case 'O': // Zero 773 break; 774 case 'b': // Base register 775 case 'f': // Floating point register 776 Info.setAllowsRegister(); 777 break; 778 // FIXME: The following are added to allow parsing. 779 // I just took a guess at what the actions should be. 780 // Also, is more specific checking needed? I.e. specific registers? 781 case 'd': // Floating point register (containing 64-bit value) 782 case 'v': // Altivec vector register 783 Info.setAllowsRegister(); 784 break; 785 case 'w': 786 switch (Name[1]) { 787 case 'd':// VSX vector register to hold vector double data 788 case 'f':// VSX vector register to hold vector float data 789 case 's':// VSX vector register to hold scalar float data 790 case 'a':// Any VSX register 791 break; 792 default: 793 return false; 794 } 795 Info.setAllowsRegister(); 796 Name++; // Skip over 'w'. 797 break; 798 case 'h': // `MQ', `CTR', or `LINK' register 799 case 'q': // `MQ' register 800 case 'c': // `CTR' register 801 case 'l': // `LINK' register 802 case 'x': // `CR' register (condition register) number 0 803 case 'y': // `CR' register (condition register) 804 case 'z': // `XER[CA]' carry bit (part of the XER register) 805 Info.setAllowsRegister(); 806 break; 807 case 'I': // Signed 16-bit constant 808 case 'J': // Unsigned 16-bit constant shifted left 16 bits 809 // (use `L' instead for SImode constants) 810 case 'K': // Unsigned 16-bit constant 811 case 'L': // Signed 16-bit constant shifted left 16 bits 812 case 'M': // Constant larger than 31 813 case 'N': // Exact power of 2 814 case 'P': // Constant whose negation is a signed 16-bit constant 815 case 'G': // Floating point constant that can be loaded into a 816 // register with one instruction per word 817 case 'H': // Integer/Floating point constant that can be loaded 818 // into a register using three instructions 819 break; 820 case 'm': // Memory operand. Note that on PowerPC targets, m can 821 // include addresses that update the base register. It 822 // is therefore only safe to use `m' in an asm statement 823 // if that asm statement accesses the operand exactly once. 824 // The asm statement must also use `%U<opno>' as a 825 // placeholder for the "update" flag in the corresponding 826 // load or store instruction. For example: 827 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 828 // is correct but: 829 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 830 // is not. Use es rather than m if you don't want the base 831 // register to be updated. 832 case 'e': 833 if (Name[1] != 's') 834 return false; 835 // es: A "stable" memory operand; that is, one which does not 836 // include any automodification of the base register. Unlike 837 // `m', this constraint can be used in asm statements that 838 // might access the operand several times, or that might not 839 // access it at all. 840 Info.setAllowsMemory(); 841 Name++; // Skip over 'e'. 842 break; 843 case 'Q': // Memory operand that is an offset from a register (it is 844 // usually better to use `m' or `es' in asm statements) 845 case 'Z': // Memory operand that is an indexed or indirect from a 846 // register (it is usually better to use `m' or `es' in 847 // asm statements) 848 Info.setAllowsMemory(); 849 Info.setAllowsRegister(); 850 break; 851 case 'R': // AIX TOC entry 852 case 'a': // Address operand that is an indexed or indirect from a 853 // register (`p' is preferable for asm statements) 854 case 'S': // Constant suitable as a 64-bit mask operand 855 case 'T': // Constant suitable as a 32-bit mask operand 856 case 'U': // System V Release 4 small data area reference 857 case 't': // AND masks that can be performed by two rldic{l, r} 858 // instructions 859 case 'W': // Vector constant that does not require memory 860 case 'j': // Vector constant that is all zeros. 861 break; 862 // End FIXME. 863 } 864 return true; 865 } 866 virtual const char *getClobbers() const { 867 return ""; 868 } 869 int getEHDataRegisterNumber(unsigned RegNo) const { 870 if (RegNo == 0) return 3; 871 if (RegNo == 1) return 4; 872 return -1; 873 } 874 }; 875 876 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 877 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 878 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 879 ALL_LANGUAGES }, 880 #include "clang/Basic/BuiltinsPPC.def" 881 }; 882 883 /// handleTargetFeatures - Perform initialization based on the user 884 /// configured set of features. 885 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 886 DiagnosticsEngine &Diags) { 887 // Remember the maximum enabled sselevel. 888 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 889 // Ignore disabled features. 890 if (Features[i][0] == '-') 891 continue; 892 893 StringRef Feature = StringRef(Features[i]).substr(1); 894 895 if (Feature == "vsx") { 896 HasVSX = true; 897 continue; 898 } 899 900 // TODO: Finish this list and add an assert that we've handled them 901 // all. 902 } 903 904 return true; 905 } 906 907 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 908 /// #defines that are not tied to a specific subtarget. 909 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 910 MacroBuilder &Builder) const { 911 // Target identification. 912 Builder.defineMacro("__ppc__"); 913 Builder.defineMacro("__PPC__"); 914 Builder.defineMacro("_ARCH_PPC"); 915 Builder.defineMacro("__powerpc__"); 916 Builder.defineMacro("__POWERPC__"); 917 if (PointerWidth == 64) { 918 Builder.defineMacro("_ARCH_PPC64"); 919 Builder.defineMacro("__powerpc64__"); 920 Builder.defineMacro("__ppc64__"); 921 Builder.defineMacro("__PPC64__"); 922 } 923 924 // Target properties. 925 if (getTriple().getArch() == llvm::Triple::ppc64le) { 926 Builder.defineMacro("_LITTLE_ENDIAN"); 927 Builder.defineMacro("__LITTLE_ENDIAN__"); 928 } else { 929 if (getTriple().getOS() != llvm::Triple::NetBSD && 930 getTriple().getOS() != llvm::Triple::OpenBSD) 931 Builder.defineMacro("_BIG_ENDIAN"); 932 Builder.defineMacro("__BIG_ENDIAN__"); 933 } 934 935 // Subtarget options. 936 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 937 Builder.defineMacro("__REGISTER_PREFIX__", ""); 938 939 // FIXME: Should be controlled by command line option. 940 if (LongDoubleWidth == 128) 941 Builder.defineMacro("__LONG_DOUBLE_128__"); 942 943 if (Opts.AltiVec) { 944 Builder.defineMacro("__VEC__", "10206"); 945 Builder.defineMacro("__ALTIVEC__"); 946 } 947 948 // CPU identification. 949 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 950 .Case("440", ArchDefineName) 951 .Case("450", ArchDefineName | ArchDefine440) 952 .Case("601", ArchDefineName) 953 .Case("602", ArchDefineName | ArchDefinePpcgr) 954 .Case("603", ArchDefineName | ArchDefinePpcgr) 955 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 956 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 957 .Case("604", ArchDefineName | ArchDefinePpcgr) 958 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 959 .Case("620", ArchDefineName | ArchDefinePpcgr) 960 .Case("630", ArchDefineName | ArchDefinePpcgr) 961 .Case("7400", ArchDefineName | ArchDefinePpcgr) 962 .Case("7450", ArchDefineName | ArchDefinePpcgr) 963 .Case("750", ArchDefineName | ArchDefinePpcgr) 964 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 965 | ArchDefinePpcsq) 966 .Case("a2", ArchDefineA2) 967 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 968 .Case("pwr3", ArchDefinePpcgr) 969 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 970 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 971 | ArchDefinePpcsq) 972 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 973 | ArchDefinePpcgr | ArchDefinePpcsq) 974 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 975 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 976 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 977 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 978 | ArchDefinePpcsq) 979 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 980 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 981 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 982 .Case("power3", ArchDefinePpcgr) 983 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 984 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 985 | ArchDefinePpcsq) 986 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 987 | ArchDefinePpcgr | ArchDefinePpcsq) 988 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 989 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 990 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 991 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 992 | ArchDefinePpcsq) 993 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 994 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 995 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 996 .Default(ArchDefineNone); 997 998 if (defs & ArchDefineName) 999 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1000 if (defs & ArchDefinePpcgr) 1001 Builder.defineMacro("_ARCH_PPCGR"); 1002 if (defs & ArchDefinePpcsq) 1003 Builder.defineMacro("_ARCH_PPCSQ"); 1004 if (defs & ArchDefine440) 1005 Builder.defineMacro("_ARCH_440"); 1006 if (defs & ArchDefine603) 1007 Builder.defineMacro("_ARCH_603"); 1008 if (defs & ArchDefine604) 1009 Builder.defineMacro("_ARCH_604"); 1010 if (defs & ArchDefinePwr4) 1011 Builder.defineMacro("_ARCH_PWR4"); 1012 if (defs & ArchDefinePwr5) 1013 Builder.defineMacro("_ARCH_PWR5"); 1014 if (defs & ArchDefinePwr5x) 1015 Builder.defineMacro("_ARCH_PWR5X"); 1016 if (defs & ArchDefinePwr6) 1017 Builder.defineMacro("_ARCH_PWR6"); 1018 if (defs & ArchDefinePwr6x) 1019 Builder.defineMacro("_ARCH_PWR6X"); 1020 if (defs & ArchDefinePwr7) 1021 Builder.defineMacro("_ARCH_PWR7"); 1022 if (defs & ArchDefineA2) 1023 Builder.defineMacro("_ARCH_A2"); 1024 if (defs & ArchDefineA2q) { 1025 Builder.defineMacro("_ARCH_A2Q"); 1026 Builder.defineMacro("_ARCH_QP"); 1027 } 1028 1029 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1030 Builder.defineMacro("__bg__"); 1031 Builder.defineMacro("__THW_BLUEGENE__"); 1032 Builder.defineMacro("__bgq__"); 1033 Builder.defineMacro("__TOS_BGQ__"); 1034 } 1035 1036 if (HasVSX) 1037 Builder.defineMacro("__VSX__"); 1038 1039 // FIXME: The following are not yet generated here by Clang, but are 1040 // generated by GCC: 1041 // 1042 // _SOFT_FLOAT_ 1043 // __RECIP_PRECISION__ 1044 // __APPLE_ALTIVEC__ 1045 // __RECIP__ 1046 // __RECIPF__ 1047 // __RSQRTE__ 1048 // __RSQRTEF__ 1049 // _SOFT_DOUBLE_ 1050 // __NO_LWSYNC__ 1051 // __HAVE_BSWAP__ 1052 // __LONGDOUBLE128 1053 // __CMODEL_MEDIUM__ 1054 // __CMODEL_LARGE__ 1055 // _CALL_SYSV 1056 // _CALL_DARWIN 1057 // __NO_FPRS__ 1058 } 1059 1060 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1061 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1062 .Case("7400", true) 1063 .Case("g4", true) 1064 .Case("7450", true) 1065 .Case("g4+", true) 1066 .Case("970", true) 1067 .Case("g5", true) 1068 .Case("pwr6", true) 1069 .Case("pwr7", true) 1070 .Case("ppc64", true) 1071 .Case("ppc64le", true) 1072 .Default(false); 1073 1074 Features["qpx"] = (CPU == "a2q"); 1075 } 1076 1077 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1078 return Feature == "powerpc"; 1079 } 1080 1081 1082 const char * const PPCTargetInfo::GCCRegNames[] = { 1083 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1084 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1085 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1086 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1087 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1088 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1089 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1090 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1091 "mq", "lr", "ctr", "ap", 1092 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1093 "xer", 1094 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1095 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1096 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1097 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1098 "vrsave", "vscr", 1099 "spe_acc", "spefscr", 1100 "sfp" 1101 }; 1102 1103 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1104 unsigned &NumNames) const { 1105 Names = GCCRegNames; 1106 NumNames = llvm::array_lengthof(GCCRegNames); 1107 } 1108 1109 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1110 // While some of these aliases do map to different registers 1111 // they still share the same register name. 1112 { { "0" }, "r0" }, 1113 { { "1"}, "r1" }, 1114 { { "2" }, "r2" }, 1115 { { "3" }, "r3" }, 1116 { { "4" }, "r4" }, 1117 { { "5" }, "r5" }, 1118 { { "6" }, "r6" }, 1119 { { "7" }, "r7" }, 1120 { { "8" }, "r8" }, 1121 { { "9" }, "r9" }, 1122 { { "10" }, "r10" }, 1123 { { "11" }, "r11" }, 1124 { { "12" }, "r12" }, 1125 { { "13" }, "r13" }, 1126 { { "14" }, "r14" }, 1127 { { "15" }, "r15" }, 1128 { { "16" }, "r16" }, 1129 { { "17" }, "r17" }, 1130 { { "18" }, "r18" }, 1131 { { "19" }, "r19" }, 1132 { { "20" }, "r20" }, 1133 { { "21" }, "r21" }, 1134 { { "22" }, "r22" }, 1135 { { "23" }, "r23" }, 1136 { { "24" }, "r24" }, 1137 { { "25" }, "r25" }, 1138 { { "26" }, "r26" }, 1139 { { "27" }, "r27" }, 1140 { { "28" }, "r28" }, 1141 { { "29" }, "r29" }, 1142 { { "30" }, "r30" }, 1143 { { "31" }, "r31" }, 1144 { { "fr0" }, "f0" }, 1145 { { "fr1" }, "f1" }, 1146 { { "fr2" }, "f2" }, 1147 { { "fr3" }, "f3" }, 1148 { { "fr4" }, "f4" }, 1149 { { "fr5" }, "f5" }, 1150 { { "fr6" }, "f6" }, 1151 { { "fr7" }, "f7" }, 1152 { { "fr8" }, "f8" }, 1153 { { "fr9" }, "f9" }, 1154 { { "fr10" }, "f10" }, 1155 { { "fr11" }, "f11" }, 1156 { { "fr12" }, "f12" }, 1157 { { "fr13" }, "f13" }, 1158 { { "fr14" }, "f14" }, 1159 { { "fr15" }, "f15" }, 1160 { { "fr16" }, "f16" }, 1161 { { "fr17" }, "f17" }, 1162 { { "fr18" }, "f18" }, 1163 { { "fr19" }, "f19" }, 1164 { { "fr20" }, "f20" }, 1165 { { "fr21" }, "f21" }, 1166 { { "fr22" }, "f22" }, 1167 { { "fr23" }, "f23" }, 1168 { { "fr24" }, "f24" }, 1169 { { "fr25" }, "f25" }, 1170 { { "fr26" }, "f26" }, 1171 { { "fr27" }, "f27" }, 1172 { { "fr28" }, "f28" }, 1173 { { "fr29" }, "f29" }, 1174 { { "fr30" }, "f30" }, 1175 { { "fr31" }, "f31" }, 1176 { { "cc" }, "cr0" }, 1177 }; 1178 1179 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1180 unsigned &NumAliases) const { 1181 Aliases = GCCRegAliases; 1182 NumAliases = llvm::array_lengthof(GCCRegAliases); 1183 } 1184 } // end anonymous namespace. 1185 1186 namespace { 1187 class PPC32TargetInfo : public PPCTargetInfo { 1188 public: 1189 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1190 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1191 1192 switch (getTriple().getOS()) { 1193 case llvm::Triple::Linux: 1194 case llvm::Triple::FreeBSD: 1195 case llvm::Triple::NetBSD: 1196 SizeType = UnsignedInt; 1197 PtrDiffType = SignedInt; 1198 IntPtrType = SignedInt; 1199 break; 1200 default: 1201 break; 1202 } 1203 1204 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1205 LongDoubleWidth = LongDoubleAlign = 64; 1206 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1207 } 1208 1209 // PPC32 supports atomics up to 4 bytes. 1210 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1211 } 1212 1213 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1214 // This is the ELF definition, and is overridden by the Darwin sub-target 1215 return TargetInfo::PowerABIBuiltinVaList; 1216 } 1217 }; 1218 } // end anonymous namespace. 1219 1220 // Note: ABI differences may eventually require us to have a separate 1221 // TargetInfo for little endian. 1222 namespace { 1223 class PPC64TargetInfo : public PPCTargetInfo { 1224 public: 1225 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1226 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1227 IntMaxType = SignedLong; 1228 UIntMaxType = UnsignedLong; 1229 Int64Type = SignedLong; 1230 1231 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1232 LongDoubleWidth = LongDoubleAlign = 64; 1233 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1234 DescriptionString = "E-m:e-i64:64-n32:64"; 1235 } else 1236 DescriptionString = "E-m:e-i64:64-n32:64"; 1237 1238 // PPC64 supports atomics up to 8 bytes. 1239 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1240 } 1241 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1242 return TargetInfo::CharPtrBuiltinVaList; 1243 } 1244 }; 1245 } // end anonymous namespace. 1246 1247 1248 namespace { 1249 class DarwinPPC32TargetInfo : 1250 public DarwinTargetInfo<PPC32TargetInfo> { 1251 public: 1252 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1253 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1254 HasAlignMac68kSupport = true; 1255 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1256 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1257 LongLongAlign = 32; 1258 SuitableAlign = 128; 1259 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1260 } 1261 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1262 return TargetInfo::CharPtrBuiltinVaList; 1263 } 1264 }; 1265 1266 class DarwinPPC64TargetInfo : 1267 public DarwinTargetInfo<PPC64TargetInfo> { 1268 public: 1269 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1270 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1271 HasAlignMac68kSupport = true; 1272 SuitableAlign = 128; 1273 DescriptionString = "E-m:o-i64:64-n32:64"; 1274 } 1275 }; 1276 } // end anonymous namespace. 1277 1278 namespace { 1279 static const unsigned NVPTXAddrSpaceMap[] = { 1280 1, // opencl_global 1281 3, // opencl_local 1282 4, // opencl_constant 1283 1, // cuda_device 1284 4, // cuda_constant 1285 3, // cuda_shared 1286 }; 1287 class NVPTXTargetInfo : public TargetInfo { 1288 static const char * const GCCRegNames[]; 1289 static const Builtin::Info BuiltinInfo[]; 1290 public: 1291 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1292 BigEndian = false; 1293 TLSSupported = false; 1294 LongWidth = LongAlign = 64; 1295 AddrSpaceMap = &NVPTXAddrSpaceMap; 1296 UseAddrSpaceMapMangling = true; 1297 // Define available target features 1298 // These must be defined in sorted order! 1299 NoAsmVariants = true; 1300 } 1301 virtual void getTargetDefines(const LangOptions &Opts, 1302 MacroBuilder &Builder) const { 1303 Builder.defineMacro("__PTX__"); 1304 Builder.defineMacro("__NVPTX__"); 1305 } 1306 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1307 unsigned &NumRecords) const { 1308 Records = BuiltinInfo; 1309 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1310 } 1311 virtual bool hasFeature(StringRef Feature) const { 1312 return Feature == "ptx" || Feature == "nvptx"; 1313 } 1314 1315 virtual void getGCCRegNames(const char * const *&Names, 1316 unsigned &NumNames) const; 1317 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1318 unsigned &NumAliases) const { 1319 // No aliases. 1320 Aliases = 0; 1321 NumAliases = 0; 1322 } 1323 virtual bool validateAsmConstraint(const char *&Name, 1324 TargetInfo::ConstraintInfo &Info) const { 1325 switch (*Name) { 1326 default: return false; 1327 case 'c': 1328 case 'h': 1329 case 'r': 1330 case 'l': 1331 case 'f': 1332 case 'd': 1333 Info.setAllowsRegister(); 1334 return true; 1335 } 1336 } 1337 virtual const char *getClobbers() const { 1338 // FIXME: Is this really right? 1339 return ""; 1340 } 1341 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1342 // FIXME: implement 1343 return TargetInfo::CharPtrBuiltinVaList; 1344 } 1345 virtual bool setCPU(const std::string &Name) { 1346 bool Valid = llvm::StringSwitch<bool>(Name) 1347 .Case("sm_20", true) 1348 .Case("sm_21", true) 1349 .Case("sm_30", true) 1350 .Case("sm_35", true) 1351 .Default(false); 1352 1353 return Valid; 1354 } 1355 }; 1356 1357 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1358 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1359 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1360 ALL_LANGUAGES }, 1361 #include "clang/Basic/BuiltinsNVPTX.def" 1362 }; 1363 1364 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1365 "r0" 1366 }; 1367 1368 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1369 unsigned &NumNames) const { 1370 Names = GCCRegNames; 1371 NumNames = llvm::array_lengthof(GCCRegNames); 1372 } 1373 1374 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1375 public: 1376 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1377 PointerWidth = PointerAlign = 32; 1378 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1379 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1380 } 1381 }; 1382 1383 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1384 public: 1385 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1386 PointerWidth = PointerAlign = 64; 1387 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1388 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1389 } 1390 }; 1391 } 1392 1393 namespace { 1394 1395 static const unsigned R600AddrSpaceMap[] = { 1396 1, // opencl_global 1397 3, // opencl_local 1398 2, // opencl_constant 1399 1, // cuda_device 1400 2, // cuda_constant 1401 3 // cuda_shared 1402 }; 1403 1404 static const char *DescriptionStringR600 = 1405 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1406 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1407 1408 static const char *DescriptionStringR600DoubleOps = 1409 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1410 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1411 1412 static const char *DescriptionStringSI = 1413 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1414 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1415 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1416 1417 class R600TargetInfo : public TargetInfo { 1418 /// \brief The GPU profiles supported by the R600 target. 1419 enum GPUKind { 1420 GK_NONE, 1421 GK_R600, 1422 GK_R600_DOUBLE_OPS, 1423 GK_R700, 1424 GK_R700_DOUBLE_OPS, 1425 GK_EVERGREEN, 1426 GK_EVERGREEN_DOUBLE_OPS, 1427 GK_NORTHERN_ISLANDS, 1428 GK_CAYMAN, 1429 GK_SOUTHERN_ISLANDS, 1430 GK_SEA_ISLANDS 1431 } GPU; 1432 1433 public: 1434 R600TargetInfo(const llvm::Triple &Triple) 1435 : TargetInfo(Triple), GPU(GK_R600) { 1436 DescriptionString = DescriptionStringR600; 1437 AddrSpaceMap = &R600AddrSpaceMap; 1438 UseAddrSpaceMapMangling = true; 1439 } 1440 1441 virtual const char * getClobbers() const { 1442 return ""; 1443 } 1444 1445 virtual void getGCCRegNames(const char * const *&Names, 1446 unsigned &numNames) const { 1447 Names = NULL; 1448 numNames = 0; 1449 } 1450 1451 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1452 unsigned &NumAliases) const { 1453 Aliases = NULL; 1454 NumAliases = 0; 1455 } 1456 1457 virtual bool validateAsmConstraint(const char *&Name, 1458 TargetInfo::ConstraintInfo &info) const { 1459 return true; 1460 } 1461 1462 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1463 unsigned &NumRecords) const { 1464 Records = NULL; 1465 NumRecords = 0; 1466 } 1467 1468 1469 virtual void getTargetDefines(const LangOptions &Opts, 1470 MacroBuilder &Builder) const { 1471 Builder.defineMacro("__R600__"); 1472 } 1473 1474 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1475 return TargetInfo::CharPtrBuiltinVaList; 1476 } 1477 1478 virtual bool setCPU(const std::string &Name) { 1479 GPU = llvm::StringSwitch<GPUKind>(Name) 1480 .Case("r600" , GK_R600) 1481 .Case("rv610", GK_R600) 1482 .Case("rv620", GK_R600) 1483 .Case("rv630", GK_R600) 1484 .Case("rv635", GK_R600) 1485 .Case("rs780", GK_R600) 1486 .Case("rs880", GK_R600) 1487 .Case("rv670", GK_R600_DOUBLE_OPS) 1488 .Case("rv710", GK_R700) 1489 .Case("rv730", GK_R700) 1490 .Case("rv740", GK_R700_DOUBLE_OPS) 1491 .Case("rv770", GK_R700_DOUBLE_OPS) 1492 .Case("palm", GK_EVERGREEN) 1493 .Case("cedar", GK_EVERGREEN) 1494 .Case("sumo", GK_EVERGREEN) 1495 .Case("sumo2", GK_EVERGREEN) 1496 .Case("redwood", GK_EVERGREEN) 1497 .Case("juniper", GK_EVERGREEN) 1498 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1499 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1500 .Case("barts", GK_NORTHERN_ISLANDS) 1501 .Case("turks", GK_NORTHERN_ISLANDS) 1502 .Case("caicos", GK_NORTHERN_ISLANDS) 1503 .Case("cayman", GK_CAYMAN) 1504 .Case("aruba", GK_CAYMAN) 1505 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1506 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1507 .Case("verde", GK_SOUTHERN_ISLANDS) 1508 .Case("oland", GK_SOUTHERN_ISLANDS) 1509 .Case("bonaire", GK_SEA_ISLANDS) 1510 .Case("kabini", GK_SEA_ISLANDS) 1511 .Case("kaveri", GK_SEA_ISLANDS) 1512 .Case("hawaii", GK_SEA_ISLANDS) 1513 .Default(GK_NONE); 1514 1515 if (GPU == GK_NONE) { 1516 return false; 1517 } 1518 1519 // Set the correct data layout 1520 switch (GPU) { 1521 case GK_NONE: 1522 case GK_R600: 1523 case GK_R700: 1524 case GK_EVERGREEN: 1525 case GK_NORTHERN_ISLANDS: 1526 DescriptionString = DescriptionStringR600; 1527 break; 1528 case GK_R600_DOUBLE_OPS: 1529 case GK_R700_DOUBLE_OPS: 1530 case GK_EVERGREEN_DOUBLE_OPS: 1531 case GK_CAYMAN: 1532 DescriptionString = DescriptionStringR600DoubleOps; 1533 break; 1534 case GK_SOUTHERN_ISLANDS: 1535 case GK_SEA_ISLANDS: 1536 DescriptionString = DescriptionStringSI; 1537 break; 1538 } 1539 1540 return true; 1541 } 1542 }; 1543 1544 } // end anonymous namespace 1545 1546 namespace { 1547 // Namespace for x86 abstract base class 1548 const Builtin::Info BuiltinInfo[] = { 1549 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1550 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1551 ALL_LANGUAGES }, 1552 #include "clang/Basic/BuiltinsX86.def" 1553 }; 1554 1555 static const char* const GCCRegNames[] = { 1556 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1557 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1558 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1559 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1560 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1561 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1562 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1563 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1564 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1565 }; 1566 1567 const TargetInfo::AddlRegName AddlRegNames[] = { 1568 { { "al", "ah", "eax", "rax" }, 0 }, 1569 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1570 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1571 { { "dl", "dh", "edx", "rdx" }, 1 }, 1572 { { "esi", "rsi" }, 4 }, 1573 { { "edi", "rdi" }, 5 }, 1574 { { "esp", "rsp" }, 7 }, 1575 { { "ebp", "rbp" }, 6 }, 1576 }; 1577 1578 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1579 // most of the implementation can be shared. 1580 class X86TargetInfo : public TargetInfo { 1581 enum X86SSEEnum { 1582 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1583 } SSELevel; 1584 enum MMX3DNowEnum { 1585 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1586 } MMX3DNowLevel; 1587 enum XOPEnum { 1588 NoXOP, 1589 SSE4A, 1590 FMA4, 1591 XOP 1592 } XOPLevel; 1593 1594 bool HasAES; 1595 bool HasPCLMUL; 1596 bool HasLZCNT; 1597 bool HasRDRND; 1598 bool HasBMI; 1599 bool HasBMI2; 1600 bool HasPOPCNT; 1601 bool HasRTM; 1602 bool HasPRFCHW; 1603 bool HasRDSEED; 1604 bool HasTBM; 1605 bool HasFMA; 1606 bool HasF16C; 1607 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1608 bool HasSHA; 1609 bool HasCX16; 1610 1611 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1612 /// 1613 /// Each enumeration represents a particular CPU supported by Clang. These 1614 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1615 enum CPUKind { 1616 CK_Generic, 1617 1618 /// \name i386 1619 /// i386-generation processors. 1620 //@{ 1621 CK_i386, 1622 //@} 1623 1624 /// \name i486 1625 /// i486-generation processors. 1626 //@{ 1627 CK_i486, 1628 CK_WinChipC6, 1629 CK_WinChip2, 1630 CK_C3, 1631 //@} 1632 1633 /// \name i586 1634 /// i586-generation processors, P5 microarchitecture based. 1635 //@{ 1636 CK_i586, 1637 CK_Pentium, 1638 CK_PentiumMMX, 1639 //@} 1640 1641 /// \name i686 1642 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1643 //@{ 1644 CK_i686, 1645 CK_PentiumPro, 1646 CK_Pentium2, 1647 CK_Pentium3, 1648 CK_Pentium3M, 1649 CK_PentiumM, 1650 CK_C3_2, 1651 1652 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1653 /// Clang however has some logic to suport this. 1654 // FIXME: Warn, deprecate, and potentially remove this. 1655 CK_Yonah, 1656 //@} 1657 1658 /// \name Netburst 1659 /// Netburst microarchitecture based processors. 1660 //@{ 1661 CK_Pentium4, 1662 CK_Pentium4M, 1663 CK_Prescott, 1664 CK_Nocona, 1665 //@} 1666 1667 /// \name Core 1668 /// Core microarchitecture based processors. 1669 //@{ 1670 CK_Core2, 1671 1672 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1673 /// codename which GCC no longer accepts as an option to -march, but Clang 1674 /// has some logic for recognizing it. 1675 // FIXME: Warn, deprecate, and potentially remove this. 1676 CK_Penryn, 1677 //@} 1678 1679 /// \name Atom 1680 /// Atom processors 1681 //@{ 1682 CK_Atom, 1683 CK_Silvermont, 1684 //@} 1685 1686 /// \name Nehalem 1687 /// Nehalem microarchitecture based processors. 1688 //@{ 1689 CK_Corei7, 1690 CK_Corei7AVX, 1691 CK_CoreAVXi, 1692 CK_CoreAVX2, 1693 //@} 1694 1695 /// \name Knights Landing 1696 /// Knights Landing processor. 1697 CK_KNL, 1698 1699 /// \name K6 1700 /// K6 architecture processors. 1701 //@{ 1702 CK_K6, 1703 CK_K6_2, 1704 CK_K6_3, 1705 //@} 1706 1707 /// \name K7 1708 /// K7 architecture processors. 1709 //@{ 1710 CK_Athlon, 1711 CK_AthlonThunderbird, 1712 CK_Athlon4, 1713 CK_AthlonXP, 1714 CK_AthlonMP, 1715 //@} 1716 1717 /// \name K8 1718 /// K8 architecture processors. 1719 //@{ 1720 CK_Athlon64, 1721 CK_Athlon64SSE3, 1722 CK_AthlonFX, 1723 CK_K8, 1724 CK_K8SSE3, 1725 CK_Opteron, 1726 CK_OpteronSSE3, 1727 CK_AMDFAM10, 1728 //@} 1729 1730 /// \name Bobcat 1731 /// Bobcat architecture processors. 1732 //@{ 1733 CK_BTVER1, 1734 CK_BTVER2, 1735 //@} 1736 1737 /// \name Bulldozer 1738 /// Bulldozer architecture processors. 1739 //@{ 1740 CK_BDVER1, 1741 CK_BDVER2, 1742 CK_BDVER3, 1743 //@} 1744 1745 /// This specification is deprecated and will be removed in the future. 1746 /// Users should prefer \see CK_K8. 1747 // FIXME: Warn on this when the CPU is set to it. 1748 CK_x86_64, 1749 //@} 1750 1751 /// \name Geode 1752 /// Geode processors. 1753 //@{ 1754 CK_Geode 1755 //@} 1756 } CPU; 1757 1758 enum FPMathKind { 1759 FP_Default, 1760 FP_SSE, 1761 FP_387 1762 } FPMath; 1763 1764 public: 1765 X86TargetInfo(const llvm::Triple &Triple) 1766 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1767 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1768 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1769 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1770 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1771 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1772 FPMath(FP_Default) { 1773 BigEndian = false; 1774 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1775 } 1776 virtual unsigned getFloatEvalMethod() const { 1777 // X87 evaluates with 80 bits "long double" precision. 1778 return SSELevel == NoSSE ? 2 : 0; 1779 } 1780 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1781 unsigned &NumRecords) const { 1782 Records = BuiltinInfo; 1783 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1784 } 1785 virtual void getGCCRegNames(const char * const *&Names, 1786 unsigned &NumNames) const { 1787 Names = GCCRegNames; 1788 NumNames = llvm::array_lengthof(GCCRegNames); 1789 } 1790 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1791 unsigned &NumAliases) const { 1792 Aliases = 0; 1793 NumAliases = 0; 1794 } 1795 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1796 unsigned &NumNames) const { 1797 Names = AddlRegNames; 1798 NumNames = llvm::array_lengthof(AddlRegNames); 1799 } 1800 virtual bool validateAsmConstraint(const char *&Name, 1801 TargetInfo::ConstraintInfo &info) const; 1802 virtual std::string convertConstraint(const char *&Constraint) const; 1803 virtual const char *getClobbers() const { 1804 return "~{dirflag},~{fpsr},~{flags}"; 1805 } 1806 virtual void getTargetDefines(const LangOptions &Opts, 1807 MacroBuilder &Builder) const; 1808 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1809 bool Enabled); 1810 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1811 bool Enabled); 1812 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1813 bool Enabled); 1814 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1815 StringRef Name, bool Enabled) const { 1816 setFeatureEnabledImpl(Features, Name, Enabled); 1817 } 1818 // This exists purely to cut down on the number of virtual calls in 1819 // getDefaultFeatures which calls this repeatedly. 1820 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1821 StringRef Name, bool Enabled); 1822 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1823 virtual bool hasFeature(StringRef Feature) const; 1824 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1825 DiagnosticsEngine &Diags); 1826 virtual const char* getABI() const { 1827 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1828 return "avx"; 1829 else if (getTriple().getArch() == llvm::Triple::x86 && 1830 MMX3DNowLevel == NoMMX3DNow) 1831 return "no-mmx"; 1832 return ""; 1833 } 1834 virtual bool setCPU(const std::string &Name) { 1835 CPU = llvm::StringSwitch<CPUKind>(Name) 1836 .Case("i386", CK_i386) 1837 .Case("i486", CK_i486) 1838 .Case("winchip-c6", CK_WinChipC6) 1839 .Case("winchip2", CK_WinChip2) 1840 .Case("c3", CK_C3) 1841 .Case("i586", CK_i586) 1842 .Case("pentium", CK_Pentium) 1843 .Case("pentium-mmx", CK_PentiumMMX) 1844 .Case("i686", CK_i686) 1845 .Case("pentiumpro", CK_PentiumPro) 1846 .Case("pentium2", CK_Pentium2) 1847 .Case("pentium3", CK_Pentium3) 1848 .Case("pentium3m", CK_Pentium3M) 1849 .Case("pentium-m", CK_PentiumM) 1850 .Case("c3-2", CK_C3_2) 1851 .Case("yonah", CK_Yonah) 1852 .Case("pentium4", CK_Pentium4) 1853 .Case("pentium4m", CK_Pentium4M) 1854 .Case("prescott", CK_Prescott) 1855 .Case("nocona", CK_Nocona) 1856 .Case("core2", CK_Core2) 1857 .Case("penryn", CK_Penryn) 1858 .Case("atom", CK_Atom) 1859 .Case("slm", CK_Silvermont) 1860 .Case("corei7", CK_Corei7) 1861 .Case("corei7-avx", CK_Corei7AVX) 1862 .Case("core-avx-i", CK_CoreAVXi) 1863 .Case("core-avx2", CK_CoreAVX2) 1864 .Case("knl", CK_KNL) 1865 .Case("k6", CK_K6) 1866 .Case("k6-2", CK_K6_2) 1867 .Case("k6-3", CK_K6_3) 1868 .Case("athlon", CK_Athlon) 1869 .Case("athlon-tbird", CK_AthlonThunderbird) 1870 .Case("athlon-4", CK_Athlon4) 1871 .Case("athlon-xp", CK_AthlonXP) 1872 .Case("athlon-mp", CK_AthlonMP) 1873 .Case("athlon64", CK_Athlon64) 1874 .Case("athlon64-sse3", CK_Athlon64SSE3) 1875 .Case("athlon-fx", CK_AthlonFX) 1876 .Case("k8", CK_K8) 1877 .Case("k8-sse3", CK_K8SSE3) 1878 .Case("opteron", CK_Opteron) 1879 .Case("opteron-sse3", CK_OpteronSSE3) 1880 .Case("amdfam10", CK_AMDFAM10) 1881 .Case("btver1", CK_BTVER1) 1882 .Case("btver2", CK_BTVER2) 1883 .Case("bdver1", CK_BDVER1) 1884 .Case("bdver2", CK_BDVER2) 1885 .Case("bdver3", CK_BDVER3) 1886 .Case("x86-64", CK_x86_64) 1887 .Case("geode", CK_Geode) 1888 .Default(CK_Generic); 1889 1890 // Perform any per-CPU checks necessary to determine if this CPU is 1891 // acceptable. 1892 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1893 // invalid without explaining *why*. 1894 switch (CPU) { 1895 case CK_Generic: 1896 // No processor selected! 1897 return false; 1898 1899 case CK_i386: 1900 case CK_i486: 1901 case CK_WinChipC6: 1902 case CK_WinChip2: 1903 case CK_C3: 1904 case CK_i586: 1905 case CK_Pentium: 1906 case CK_PentiumMMX: 1907 case CK_i686: 1908 case CK_PentiumPro: 1909 case CK_Pentium2: 1910 case CK_Pentium3: 1911 case CK_Pentium3M: 1912 case CK_PentiumM: 1913 case CK_Yonah: 1914 case CK_C3_2: 1915 case CK_Pentium4: 1916 case CK_Pentium4M: 1917 case CK_Prescott: 1918 case CK_K6: 1919 case CK_K6_2: 1920 case CK_K6_3: 1921 case CK_Athlon: 1922 case CK_AthlonThunderbird: 1923 case CK_Athlon4: 1924 case CK_AthlonXP: 1925 case CK_AthlonMP: 1926 case CK_Geode: 1927 // Only accept certain architectures when compiling in 32-bit mode. 1928 if (getTriple().getArch() != llvm::Triple::x86) 1929 return false; 1930 1931 // Fallthrough 1932 case CK_Nocona: 1933 case CK_Core2: 1934 case CK_Penryn: 1935 case CK_Atom: 1936 case CK_Silvermont: 1937 case CK_Corei7: 1938 case CK_Corei7AVX: 1939 case CK_CoreAVXi: 1940 case CK_CoreAVX2: 1941 case CK_KNL: 1942 case CK_Athlon64: 1943 case CK_Athlon64SSE3: 1944 case CK_AthlonFX: 1945 case CK_K8: 1946 case CK_K8SSE3: 1947 case CK_Opteron: 1948 case CK_OpteronSSE3: 1949 case CK_AMDFAM10: 1950 case CK_BTVER1: 1951 case CK_BTVER2: 1952 case CK_BDVER1: 1953 case CK_BDVER2: 1954 case CK_BDVER3: 1955 case CK_x86_64: 1956 return true; 1957 } 1958 llvm_unreachable("Unhandled CPU kind"); 1959 } 1960 1961 virtual bool setFPMath(StringRef Name); 1962 1963 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1964 // We accept all non-ARM calling conventions 1965 return (CC == CC_X86ThisCall || 1966 CC == CC_X86FastCall || 1967 CC == CC_X86StdCall || 1968 CC == CC_C || 1969 CC == CC_X86Pascal || 1970 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1971 } 1972 1973 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1974 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1975 } 1976 }; 1977 1978 bool X86TargetInfo::setFPMath(StringRef Name) { 1979 if (Name == "387") { 1980 FPMath = FP_387; 1981 return true; 1982 } 1983 if (Name == "sse") { 1984 FPMath = FP_SSE; 1985 return true; 1986 } 1987 return false; 1988 } 1989 1990 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1991 // FIXME: This *really* should not be here. 1992 1993 // X86_64 always has SSE2. 1994 if (getTriple().getArch() == llvm::Triple::x86_64) 1995 setFeatureEnabledImpl(Features, "sse2", true); 1996 1997 switch (CPU) { 1998 case CK_Generic: 1999 case CK_i386: 2000 case CK_i486: 2001 case CK_i586: 2002 case CK_Pentium: 2003 case CK_i686: 2004 case CK_PentiumPro: 2005 break; 2006 case CK_PentiumMMX: 2007 case CK_Pentium2: 2008 setFeatureEnabledImpl(Features, "mmx", true); 2009 break; 2010 case CK_Pentium3: 2011 case CK_Pentium3M: 2012 setFeatureEnabledImpl(Features, "sse", true); 2013 break; 2014 case CK_PentiumM: 2015 case CK_Pentium4: 2016 case CK_Pentium4M: 2017 case CK_x86_64: 2018 setFeatureEnabledImpl(Features, "sse2", true); 2019 break; 2020 case CK_Yonah: 2021 case CK_Prescott: 2022 case CK_Nocona: 2023 setFeatureEnabledImpl(Features, "sse3", true); 2024 setFeatureEnabledImpl(Features, "cx16", true); 2025 break; 2026 case CK_Core2: 2027 setFeatureEnabledImpl(Features, "ssse3", true); 2028 setFeatureEnabledImpl(Features, "cx16", true); 2029 break; 2030 case CK_Penryn: 2031 setFeatureEnabledImpl(Features, "sse4.1", true); 2032 setFeatureEnabledImpl(Features, "cx16", true); 2033 break; 2034 case CK_Atom: 2035 setFeatureEnabledImpl(Features, "ssse3", true); 2036 setFeatureEnabledImpl(Features, "cx16", true); 2037 break; 2038 case CK_Silvermont: 2039 setFeatureEnabledImpl(Features, "sse4.2", true); 2040 setFeatureEnabledImpl(Features, "aes", true); 2041 setFeatureEnabledImpl(Features, "cx16", true); 2042 setFeatureEnabledImpl(Features, "pclmul", true); 2043 break; 2044 case CK_Corei7: 2045 setFeatureEnabledImpl(Features, "sse4.2", true); 2046 setFeatureEnabledImpl(Features, "cx16", true); 2047 break; 2048 case CK_Corei7AVX: 2049 setFeatureEnabledImpl(Features, "avx", true); 2050 setFeatureEnabledImpl(Features, "aes", true); 2051 setFeatureEnabledImpl(Features, "cx16", true); 2052 setFeatureEnabledImpl(Features, "pclmul", true); 2053 break; 2054 case CK_CoreAVXi: 2055 setFeatureEnabledImpl(Features, "avx", true); 2056 setFeatureEnabledImpl(Features, "aes", true); 2057 setFeatureEnabledImpl(Features, "pclmul", true); 2058 setFeatureEnabledImpl(Features, "rdrnd", true); 2059 setFeatureEnabledImpl(Features, "f16c", true); 2060 break; 2061 case CK_CoreAVX2: 2062 setFeatureEnabledImpl(Features, "avx2", true); 2063 setFeatureEnabledImpl(Features, "aes", true); 2064 setFeatureEnabledImpl(Features, "pclmul", true); 2065 setFeatureEnabledImpl(Features, "lzcnt", true); 2066 setFeatureEnabledImpl(Features, "rdrnd", true); 2067 setFeatureEnabledImpl(Features, "f16c", true); 2068 setFeatureEnabledImpl(Features, "bmi", true); 2069 setFeatureEnabledImpl(Features, "bmi2", true); 2070 setFeatureEnabledImpl(Features, "rtm", true); 2071 setFeatureEnabledImpl(Features, "fma", true); 2072 setFeatureEnabledImpl(Features, "cx16", true); 2073 break; 2074 case CK_KNL: 2075 setFeatureEnabledImpl(Features, "avx512f", true); 2076 setFeatureEnabledImpl(Features, "avx512cd", true); 2077 setFeatureEnabledImpl(Features, "avx512er", true); 2078 setFeatureEnabledImpl(Features, "avx512pf", true); 2079 setFeatureEnabledImpl(Features, "aes", true); 2080 setFeatureEnabledImpl(Features, "pclmul", true); 2081 setFeatureEnabledImpl(Features, "lzcnt", true); 2082 setFeatureEnabledImpl(Features, "rdrnd", true); 2083 setFeatureEnabledImpl(Features, "f16c", true); 2084 setFeatureEnabledImpl(Features, "bmi", true); 2085 setFeatureEnabledImpl(Features, "bmi2", true); 2086 setFeatureEnabledImpl(Features, "rtm", true); 2087 setFeatureEnabledImpl(Features, "fma", true); 2088 break; 2089 case CK_K6: 2090 case CK_WinChipC6: 2091 setFeatureEnabledImpl(Features, "mmx", true); 2092 break; 2093 case CK_K6_2: 2094 case CK_K6_3: 2095 case CK_WinChip2: 2096 case CK_C3: 2097 setFeatureEnabledImpl(Features, "3dnow", true); 2098 break; 2099 case CK_Athlon: 2100 case CK_AthlonThunderbird: 2101 case CK_Geode: 2102 setFeatureEnabledImpl(Features, "3dnowa", true); 2103 break; 2104 case CK_Athlon4: 2105 case CK_AthlonXP: 2106 case CK_AthlonMP: 2107 setFeatureEnabledImpl(Features, "sse", true); 2108 setFeatureEnabledImpl(Features, "3dnowa", true); 2109 break; 2110 case CK_K8: 2111 case CK_Opteron: 2112 case CK_Athlon64: 2113 case CK_AthlonFX: 2114 setFeatureEnabledImpl(Features, "sse2", true); 2115 setFeatureEnabledImpl(Features, "3dnowa", true); 2116 break; 2117 case CK_K8SSE3: 2118 case CK_OpteronSSE3: 2119 case CK_Athlon64SSE3: 2120 setFeatureEnabledImpl(Features, "sse3", true); 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_AMDFAM10: 2124 setFeatureEnabledImpl(Features, "sse3", true); 2125 setFeatureEnabledImpl(Features, "sse4a", true); 2126 setFeatureEnabledImpl(Features, "3dnowa", true); 2127 setFeatureEnabledImpl(Features, "lzcnt", true); 2128 setFeatureEnabledImpl(Features, "popcnt", true); 2129 break; 2130 case CK_BTVER1: 2131 setFeatureEnabledImpl(Features, "ssse3", true); 2132 setFeatureEnabledImpl(Features, "sse4a", true); 2133 setFeatureEnabledImpl(Features, "cx16", true); 2134 setFeatureEnabledImpl(Features, "lzcnt", true); 2135 setFeatureEnabledImpl(Features, "popcnt", true); 2136 setFeatureEnabledImpl(Features, "prfchw", true); 2137 break; 2138 case CK_BTVER2: 2139 setFeatureEnabledImpl(Features, "avx", true); 2140 setFeatureEnabledImpl(Features, "sse4a", true); 2141 setFeatureEnabledImpl(Features, "lzcnt", true); 2142 setFeatureEnabledImpl(Features, "aes", true); 2143 setFeatureEnabledImpl(Features, "pclmul", true); 2144 setFeatureEnabledImpl(Features, "prfchw", true); 2145 setFeatureEnabledImpl(Features, "bmi", true); 2146 setFeatureEnabledImpl(Features, "f16c", true); 2147 setFeatureEnabledImpl(Features, "cx16", true); 2148 break; 2149 case CK_BDVER1: 2150 setFeatureEnabledImpl(Features, "xop", true); 2151 setFeatureEnabledImpl(Features, "lzcnt", true); 2152 setFeatureEnabledImpl(Features, "aes", true); 2153 setFeatureEnabledImpl(Features, "pclmul", true); 2154 setFeatureEnabledImpl(Features, "prfchw", true); 2155 setFeatureEnabledImpl(Features, "cx16", true); 2156 break; 2157 case CK_BDVER2: 2158 case CK_BDVER3: 2159 setFeatureEnabledImpl(Features, "xop", true); 2160 setFeatureEnabledImpl(Features, "lzcnt", true); 2161 setFeatureEnabledImpl(Features, "aes", true); 2162 setFeatureEnabledImpl(Features, "pclmul", true); 2163 setFeatureEnabledImpl(Features, "prfchw", true); 2164 setFeatureEnabledImpl(Features, "bmi", true); 2165 setFeatureEnabledImpl(Features, "fma", true); 2166 setFeatureEnabledImpl(Features, "f16c", true); 2167 setFeatureEnabledImpl(Features, "tbm", true); 2168 setFeatureEnabledImpl(Features, "cx16", true); 2169 break; 2170 case CK_C3_2: 2171 setFeatureEnabledImpl(Features, "sse", true); 2172 break; 2173 } 2174 } 2175 2176 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2177 X86SSEEnum Level, bool Enabled) { 2178 if (Enabled) { 2179 switch (Level) { 2180 case AVX512F: 2181 Features["avx512f"] = true; 2182 case AVX2: 2183 Features["avx2"] = true; 2184 case AVX: 2185 Features["avx"] = true; 2186 case SSE42: 2187 Features["sse4.2"] = true; 2188 case SSE41: 2189 Features["sse4.1"] = true; 2190 case SSSE3: 2191 Features["ssse3"] = true; 2192 case SSE3: 2193 Features["sse3"] = true; 2194 case SSE2: 2195 Features["sse2"] = true; 2196 case SSE1: 2197 Features["sse"] = true; 2198 case NoSSE: 2199 break; 2200 } 2201 return; 2202 } 2203 2204 switch (Level) { 2205 case NoSSE: 2206 case SSE1: 2207 Features["sse"] = false; 2208 case SSE2: 2209 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2210 Features["sha"] = false; 2211 case SSE3: 2212 Features["sse3"] = false; 2213 setXOPLevel(Features, NoXOP, false); 2214 case SSSE3: 2215 Features["ssse3"] = false; 2216 case SSE41: 2217 Features["sse4.1"] = false; 2218 case SSE42: 2219 Features["sse4.2"] = false; 2220 case AVX: 2221 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2222 setXOPLevel(Features, FMA4, false); 2223 case AVX2: 2224 Features["avx2"] = false; 2225 case AVX512F: 2226 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2227 Features["avx512pf"] = false; 2228 } 2229 } 2230 2231 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2232 MMX3DNowEnum Level, bool Enabled) { 2233 if (Enabled) { 2234 switch (Level) { 2235 case AMD3DNowAthlon: 2236 Features["3dnowa"] = true; 2237 case AMD3DNow: 2238 Features["3dnow"] = true; 2239 case MMX: 2240 Features["mmx"] = true; 2241 case NoMMX3DNow: 2242 break; 2243 } 2244 return; 2245 } 2246 2247 switch (Level) { 2248 case NoMMX3DNow: 2249 case MMX: 2250 Features["mmx"] = false; 2251 case AMD3DNow: 2252 Features["3dnow"] = false; 2253 case AMD3DNowAthlon: 2254 Features["3dnowa"] = false; 2255 } 2256 } 2257 2258 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2259 bool Enabled) { 2260 if (Enabled) { 2261 switch (Level) { 2262 case XOP: 2263 Features["xop"] = true; 2264 case FMA4: 2265 Features["fma4"] = true; 2266 setSSELevel(Features, AVX, true); 2267 case SSE4A: 2268 Features["sse4a"] = true; 2269 setSSELevel(Features, SSE3, true); 2270 case NoXOP: 2271 break; 2272 } 2273 return; 2274 } 2275 2276 switch (Level) { 2277 case NoXOP: 2278 case SSE4A: 2279 Features["sse4a"] = false; 2280 case FMA4: 2281 Features["fma4"] = false; 2282 case XOP: 2283 Features["xop"] = false; 2284 } 2285 } 2286 2287 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2288 StringRef Name, bool Enabled) { 2289 // FIXME: This *really* should not be here. We need some way of translating 2290 // options into llvm subtarget features. 2291 if (Name == "sse4") 2292 Name = "sse4.2"; 2293 2294 Features[Name] = Enabled; 2295 2296 if (Name == "mmx") { 2297 setMMXLevel(Features, MMX, Enabled); 2298 } else if (Name == "sse") { 2299 setSSELevel(Features, SSE1, Enabled); 2300 } else if (Name == "sse2") { 2301 setSSELevel(Features, SSE2, Enabled); 2302 } else if (Name == "sse3") { 2303 setSSELevel(Features, SSE3, Enabled); 2304 } else if (Name == "ssse3") { 2305 setSSELevel(Features, SSSE3, Enabled); 2306 } else if (Name == "sse4.2") { 2307 setSSELevel(Features, SSE42, Enabled); 2308 } else if (Name == "sse4.1") { 2309 setSSELevel(Features, SSE41, Enabled); 2310 } else if (Name == "3dnow") { 2311 setMMXLevel(Features, AMD3DNow, Enabled); 2312 } else if (Name == "3dnowa") { 2313 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2314 } else if (Name == "aes") { 2315 if (Enabled) 2316 setSSELevel(Features, SSE2, Enabled); 2317 } else if (Name == "pclmul") { 2318 if (Enabled) 2319 setSSELevel(Features, SSE2, Enabled); 2320 } else if (Name == "avx") { 2321 setSSELevel(Features, AVX, Enabled); 2322 } else if (Name == "avx2") { 2323 setSSELevel(Features, AVX2, Enabled); 2324 } else if (Name == "avx512f") { 2325 setSSELevel(Features, AVX512F, Enabled); 2326 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2327 if (Enabled) 2328 setSSELevel(Features, AVX512F, Enabled); 2329 } else if (Name == "fma") { 2330 if (Enabled) 2331 setSSELevel(Features, AVX, Enabled); 2332 } else if (Name == "fma4") { 2333 setXOPLevel(Features, FMA4, Enabled); 2334 } else if (Name == "xop") { 2335 setXOPLevel(Features, XOP, Enabled); 2336 } else if (Name == "sse4a") { 2337 setXOPLevel(Features, SSE4A, Enabled); 2338 } else if (Name == "f16c") { 2339 if (Enabled) 2340 setSSELevel(Features, AVX, Enabled); 2341 } else if (Name == "sha") { 2342 if (Enabled) 2343 setSSELevel(Features, SSE2, Enabled); 2344 } 2345 } 2346 2347 /// handleTargetFeatures - Perform initialization based on the user 2348 /// configured set of features. 2349 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2350 DiagnosticsEngine &Diags) { 2351 // Remember the maximum enabled sselevel. 2352 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2353 // Ignore disabled features. 2354 if (Features[i][0] == '-') 2355 continue; 2356 2357 StringRef Feature = StringRef(Features[i]).substr(1); 2358 2359 if (Feature == "aes") { 2360 HasAES = true; 2361 continue; 2362 } 2363 2364 if (Feature == "pclmul") { 2365 HasPCLMUL = true; 2366 continue; 2367 } 2368 2369 if (Feature == "lzcnt") { 2370 HasLZCNT = true; 2371 continue; 2372 } 2373 2374 if (Feature == "rdrnd") { 2375 HasRDRND = true; 2376 continue; 2377 } 2378 2379 if (Feature == "bmi") { 2380 HasBMI = true; 2381 continue; 2382 } 2383 2384 if (Feature == "bmi2") { 2385 HasBMI2 = true; 2386 continue; 2387 } 2388 2389 if (Feature == "popcnt") { 2390 HasPOPCNT = true; 2391 continue; 2392 } 2393 2394 if (Feature == "rtm") { 2395 HasRTM = true; 2396 continue; 2397 } 2398 2399 if (Feature == "prfchw") { 2400 HasPRFCHW = true; 2401 continue; 2402 } 2403 2404 if (Feature == "rdseed") { 2405 HasRDSEED = true; 2406 continue; 2407 } 2408 2409 if (Feature == "tbm") { 2410 HasTBM = true; 2411 continue; 2412 } 2413 2414 if (Feature == "fma") { 2415 HasFMA = true; 2416 continue; 2417 } 2418 2419 if (Feature == "f16c") { 2420 HasF16C = true; 2421 continue; 2422 } 2423 2424 if (Feature == "avx512cd") { 2425 HasAVX512CD = true; 2426 continue; 2427 } 2428 2429 if (Feature == "avx512er") { 2430 HasAVX512ER = true; 2431 continue; 2432 } 2433 2434 if (Feature == "avx512pf") { 2435 HasAVX512PF = true; 2436 continue; 2437 } 2438 2439 if (Feature == "sha") { 2440 HasSHA = true; 2441 continue; 2442 } 2443 2444 if (Feature == "cx16") { 2445 HasCX16 = true; 2446 continue; 2447 } 2448 2449 assert(Features[i][0] == '+' && "Invalid target feature!"); 2450 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2451 .Case("avx512f", AVX512F) 2452 .Case("avx2", AVX2) 2453 .Case("avx", AVX) 2454 .Case("sse4.2", SSE42) 2455 .Case("sse4.1", SSE41) 2456 .Case("ssse3", SSSE3) 2457 .Case("sse3", SSE3) 2458 .Case("sse2", SSE2) 2459 .Case("sse", SSE1) 2460 .Default(NoSSE); 2461 SSELevel = std::max(SSELevel, Level); 2462 2463 MMX3DNowEnum ThreeDNowLevel = 2464 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2465 .Case("3dnowa", AMD3DNowAthlon) 2466 .Case("3dnow", AMD3DNow) 2467 .Case("mmx", MMX) 2468 .Default(NoMMX3DNow); 2469 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2470 2471 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2472 .Case("xop", XOP) 2473 .Case("fma4", FMA4) 2474 .Case("sse4a", SSE4A) 2475 .Default(NoXOP); 2476 XOPLevel = std::max(XOPLevel, XLevel); 2477 } 2478 2479 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2480 // Can't do this earlier because we need to be able to explicitly enable 2481 // popcnt and still disable sse4.2. 2482 if (!HasPOPCNT && SSELevel >= SSE42 && 2483 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2484 HasPOPCNT = true; 2485 Features.push_back("+popcnt"); 2486 } 2487 2488 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2489 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2490 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2491 HasPRFCHW = true; 2492 Features.push_back("+prfchw"); 2493 } 2494 2495 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2496 // matches the selected sse level. 2497 if (FPMath == FP_SSE && SSELevel < SSE1) { 2498 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2499 return false; 2500 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2501 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2502 return false; 2503 } 2504 2505 // Don't tell the backend if we're turning off mmx; it will end up disabling 2506 // SSE, which we don't want. 2507 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2508 // then enable MMX. 2509 std::vector<std::string>::iterator it; 2510 it = std::find(Features.begin(), Features.end(), "-mmx"); 2511 if (it != Features.end()) 2512 Features.erase(it); 2513 else if (SSELevel > NoSSE) 2514 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2515 return true; 2516 } 2517 2518 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2519 /// definitions for this particular subtarget. 2520 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2521 MacroBuilder &Builder) const { 2522 // Target identification. 2523 if (getTriple().getArch() == llvm::Triple::x86_64) { 2524 Builder.defineMacro("__amd64__"); 2525 Builder.defineMacro("__amd64"); 2526 Builder.defineMacro("__x86_64"); 2527 Builder.defineMacro("__x86_64__"); 2528 } else { 2529 DefineStd(Builder, "i386", Opts); 2530 } 2531 2532 // Subtarget options. 2533 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2534 // truly should be based on -mtune options. 2535 switch (CPU) { 2536 case CK_Generic: 2537 break; 2538 case CK_i386: 2539 // The rest are coming from the i386 define above. 2540 Builder.defineMacro("__tune_i386__"); 2541 break; 2542 case CK_i486: 2543 case CK_WinChipC6: 2544 case CK_WinChip2: 2545 case CK_C3: 2546 defineCPUMacros(Builder, "i486"); 2547 break; 2548 case CK_PentiumMMX: 2549 Builder.defineMacro("__pentium_mmx__"); 2550 Builder.defineMacro("__tune_pentium_mmx__"); 2551 // Fallthrough 2552 case CK_i586: 2553 case CK_Pentium: 2554 defineCPUMacros(Builder, "i586"); 2555 defineCPUMacros(Builder, "pentium"); 2556 break; 2557 case CK_Pentium3: 2558 case CK_Pentium3M: 2559 case CK_PentiumM: 2560 Builder.defineMacro("__tune_pentium3__"); 2561 // Fallthrough 2562 case CK_Pentium2: 2563 case CK_C3_2: 2564 Builder.defineMacro("__tune_pentium2__"); 2565 // Fallthrough 2566 case CK_PentiumPro: 2567 Builder.defineMacro("__tune_i686__"); 2568 Builder.defineMacro("__tune_pentiumpro__"); 2569 // Fallthrough 2570 case CK_i686: 2571 Builder.defineMacro("__i686"); 2572 Builder.defineMacro("__i686__"); 2573 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2574 Builder.defineMacro("__pentiumpro"); 2575 Builder.defineMacro("__pentiumpro__"); 2576 break; 2577 case CK_Pentium4: 2578 case CK_Pentium4M: 2579 defineCPUMacros(Builder, "pentium4"); 2580 break; 2581 case CK_Yonah: 2582 case CK_Prescott: 2583 case CK_Nocona: 2584 defineCPUMacros(Builder, "nocona"); 2585 break; 2586 case CK_Core2: 2587 case CK_Penryn: 2588 defineCPUMacros(Builder, "core2"); 2589 break; 2590 case CK_Atom: 2591 defineCPUMacros(Builder, "atom"); 2592 break; 2593 case CK_Silvermont: 2594 defineCPUMacros(Builder, "slm"); 2595 break; 2596 case CK_Corei7: 2597 case CK_Corei7AVX: 2598 case CK_CoreAVXi: 2599 case CK_CoreAVX2: 2600 defineCPUMacros(Builder, "corei7"); 2601 break; 2602 case CK_KNL: 2603 defineCPUMacros(Builder, "knl"); 2604 break; 2605 case CK_K6_2: 2606 Builder.defineMacro("__k6_2__"); 2607 Builder.defineMacro("__tune_k6_2__"); 2608 // Fallthrough 2609 case CK_K6_3: 2610 if (CPU != CK_K6_2) { // In case of fallthrough 2611 // FIXME: GCC may be enabling these in cases where some other k6 2612 // architecture is specified but -m3dnow is explicitly provided. The 2613 // exact semantics need to be determined and emulated here. 2614 Builder.defineMacro("__k6_3__"); 2615 Builder.defineMacro("__tune_k6_3__"); 2616 } 2617 // Fallthrough 2618 case CK_K6: 2619 defineCPUMacros(Builder, "k6"); 2620 break; 2621 case CK_Athlon: 2622 case CK_AthlonThunderbird: 2623 case CK_Athlon4: 2624 case CK_AthlonXP: 2625 case CK_AthlonMP: 2626 defineCPUMacros(Builder, "athlon"); 2627 if (SSELevel != NoSSE) { 2628 Builder.defineMacro("__athlon_sse__"); 2629 Builder.defineMacro("__tune_athlon_sse__"); 2630 } 2631 break; 2632 case CK_K8: 2633 case CK_K8SSE3: 2634 case CK_x86_64: 2635 case CK_Opteron: 2636 case CK_OpteronSSE3: 2637 case CK_Athlon64: 2638 case CK_Athlon64SSE3: 2639 case CK_AthlonFX: 2640 defineCPUMacros(Builder, "k8"); 2641 break; 2642 case CK_AMDFAM10: 2643 defineCPUMacros(Builder, "amdfam10"); 2644 break; 2645 case CK_BTVER1: 2646 defineCPUMacros(Builder, "btver1"); 2647 break; 2648 case CK_BTVER2: 2649 defineCPUMacros(Builder, "btver2"); 2650 break; 2651 case CK_BDVER1: 2652 defineCPUMacros(Builder, "bdver1"); 2653 break; 2654 case CK_BDVER2: 2655 defineCPUMacros(Builder, "bdver2"); 2656 break; 2657 case CK_BDVER3: 2658 defineCPUMacros(Builder, "bdver3"); 2659 break; 2660 case CK_Geode: 2661 defineCPUMacros(Builder, "geode"); 2662 break; 2663 } 2664 2665 // Target properties. 2666 Builder.defineMacro("__LITTLE_ENDIAN__"); 2667 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2668 2669 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2670 // functions in glibc header files that use FP Stack inline asm which the 2671 // backend can't deal with (PR879). 2672 Builder.defineMacro("__NO_MATH_INLINES"); 2673 2674 if (HasAES) 2675 Builder.defineMacro("__AES__"); 2676 2677 if (HasPCLMUL) 2678 Builder.defineMacro("__PCLMUL__"); 2679 2680 if (HasLZCNT) 2681 Builder.defineMacro("__LZCNT__"); 2682 2683 if (HasRDRND) 2684 Builder.defineMacro("__RDRND__"); 2685 2686 if (HasBMI) 2687 Builder.defineMacro("__BMI__"); 2688 2689 if (HasBMI2) 2690 Builder.defineMacro("__BMI2__"); 2691 2692 if (HasPOPCNT) 2693 Builder.defineMacro("__POPCNT__"); 2694 2695 if (HasRTM) 2696 Builder.defineMacro("__RTM__"); 2697 2698 if (HasPRFCHW) 2699 Builder.defineMacro("__PRFCHW__"); 2700 2701 if (HasRDSEED) 2702 Builder.defineMacro("__RDSEED__"); 2703 2704 if (HasTBM) 2705 Builder.defineMacro("__TBM__"); 2706 2707 switch (XOPLevel) { 2708 case XOP: 2709 Builder.defineMacro("__XOP__"); 2710 case FMA4: 2711 Builder.defineMacro("__FMA4__"); 2712 case SSE4A: 2713 Builder.defineMacro("__SSE4A__"); 2714 case NoXOP: 2715 break; 2716 } 2717 2718 if (HasFMA) 2719 Builder.defineMacro("__FMA__"); 2720 2721 if (HasF16C) 2722 Builder.defineMacro("__F16C__"); 2723 2724 if (HasAVX512CD) 2725 Builder.defineMacro("__AVX512CD__"); 2726 if (HasAVX512ER) 2727 Builder.defineMacro("__AVX512ER__"); 2728 if (HasAVX512PF) 2729 Builder.defineMacro("__AVX512PF__"); 2730 2731 if (HasSHA) 2732 Builder.defineMacro("__SHA__"); 2733 2734 if (HasCX16) 2735 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2736 2737 // Each case falls through to the previous one here. 2738 switch (SSELevel) { 2739 case AVX512F: 2740 Builder.defineMacro("__AVX512F__"); 2741 case AVX2: 2742 Builder.defineMacro("__AVX2__"); 2743 case AVX: 2744 Builder.defineMacro("__AVX__"); 2745 case SSE42: 2746 Builder.defineMacro("__SSE4_2__"); 2747 case SSE41: 2748 Builder.defineMacro("__SSE4_1__"); 2749 case SSSE3: 2750 Builder.defineMacro("__SSSE3__"); 2751 case SSE3: 2752 Builder.defineMacro("__SSE3__"); 2753 case SSE2: 2754 Builder.defineMacro("__SSE2__"); 2755 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2756 case SSE1: 2757 Builder.defineMacro("__SSE__"); 2758 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2759 case NoSSE: 2760 break; 2761 } 2762 2763 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2764 switch (SSELevel) { 2765 case AVX512F: 2766 case AVX2: 2767 case AVX: 2768 case SSE42: 2769 case SSE41: 2770 case SSSE3: 2771 case SSE3: 2772 case SSE2: 2773 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2774 break; 2775 case SSE1: 2776 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2777 break; 2778 default: 2779 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2780 } 2781 } 2782 2783 // Each case falls through to the previous one here. 2784 switch (MMX3DNowLevel) { 2785 case AMD3DNowAthlon: 2786 Builder.defineMacro("__3dNOW_A__"); 2787 case AMD3DNow: 2788 Builder.defineMacro("__3dNOW__"); 2789 case MMX: 2790 Builder.defineMacro("__MMX__"); 2791 case NoMMX3DNow: 2792 break; 2793 } 2794 2795 if (CPU >= CK_i486) { 2796 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2797 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2798 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2799 } 2800 if (CPU >= CK_i586) 2801 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2802 } 2803 2804 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2805 return llvm::StringSwitch<bool>(Feature) 2806 .Case("aes", HasAES) 2807 .Case("avx", SSELevel >= AVX) 2808 .Case("avx2", SSELevel >= AVX2) 2809 .Case("avx512f", SSELevel >= AVX512F) 2810 .Case("avx512cd", HasAVX512CD) 2811 .Case("avx512er", HasAVX512ER) 2812 .Case("avx512pf", HasAVX512PF) 2813 .Case("bmi", HasBMI) 2814 .Case("bmi2", HasBMI2) 2815 .Case("cx16", HasCX16) 2816 .Case("f16c", HasF16C) 2817 .Case("fma", HasFMA) 2818 .Case("fma4", XOPLevel >= FMA4) 2819 .Case("tbm", HasTBM) 2820 .Case("lzcnt", HasLZCNT) 2821 .Case("rdrnd", HasRDRND) 2822 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2823 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2824 .Case("mmx", MMX3DNowLevel >= MMX) 2825 .Case("pclmul", HasPCLMUL) 2826 .Case("popcnt", HasPOPCNT) 2827 .Case("rtm", HasRTM) 2828 .Case("prfchw", HasPRFCHW) 2829 .Case("rdseed", HasRDSEED) 2830 .Case("sha", HasSHA) 2831 .Case("sse", SSELevel >= SSE1) 2832 .Case("sse2", SSELevel >= SSE2) 2833 .Case("sse3", SSELevel >= SSE3) 2834 .Case("ssse3", SSELevel >= SSSE3) 2835 .Case("sse4.1", SSELevel >= SSE41) 2836 .Case("sse4.2", SSELevel >= SSE42) 2837 .Case("sse4a", XOPLevel >= SSE4A) 2838 .Case("x86", true) 2839 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2840 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2841 .Case("xop", XOPLevel >= XOP) 2842 .Default(false); 2843 } 2844 2845 bool 2846 X86TargetInfo::validateAsmConstraint(const char *&Name, 2847 TargetInfo::ConstraintInfo &Info) const { 2848 switch (*Name) { 2849 default: return false; 2850 case 'Y': // first letter of a pair: 2851 switch (*(Name+1)) { 2852 default: return false; 2853 case '0': // First SSE register. 2854 case 't': // Any SSE register, when SSE2 is enabled. 2855 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2856 case 'm': // any MMX register, when inter-unit moves enabled. 2857 break; // falls through to setAllowsRegister. 2858 } 2859 case 'a': // eax. 2860 case 'b': // ebx. 2861 case 'c': // ecx. 2862 case 'd': // edx. 2863 case 'S': // esi. 2864 case 'D': // edi. 2865 case 'A': // edx:eax. 2866 case 'f': // any x87 floating point stack register. 2867 case 't': // top of floating point stack. 2868 case 'u': // second from top of floating point stack. 2869 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2870 case 'y': // Any MMX register. 2871 case 'x': // Any SSE register. 2872 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2873 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2874 case 'l': // "Index" registers: any general register that can be used as an 2875 // index in a base+index memory access. 2876 Info.setAllowsRegister(); 2877 return true; 2878 case 'C': // SSE floating point constant. 2879 case 'G': // x87 floating point constant. 2880 case 'e': // 32-bit signed integer constant for use with zero-extending 2881 // x86_64 instructions. 2882 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2883 // x86_64 instructions. 2884 return true; 2885 } 2886 } 2887 2888 2889 std::string 2890 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2891 switch (*Constraint) { 2892 case 'a': return std::string("{ax}"); 2893 case 'b': return std::string("{bx}"); 2894 case 'c': return std::string("{cx}"); 2895 case 'd': return std::string("{dx}"); 2896 case 'S': return std::string("{si}"); 2897 case 'D': return std::string("{di}"); 2898 case 'p': // address 2899 return std::string("im"); 2900 case 't': // top of floating point stack. 2901 return std::string("{st}"); 2902 case 'u': // second from top of floating point stack. 2903 return std::string("{st(1)}"); // second from top of floating point stack. 2904 default: 2905 return std::string(1, *Constraint); 2906 } 2907 } 2908 } // end anonymous namespace 2909 2910 namespace { 2911 // X86-32 generic target 2912 class X86_32TargetInfo : public X86TargetInfo { 2913 public: 2914 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2915 DoubleAlign = LongLongAlign = 32; 2916 LongDoubleWidth = 96; 2917 LongDoubleAlign = 32; 2918 SuitableAlign = 128; 2919 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2920 SizeType = UnsignedInt; 2921 PtrDiffType = SignedInt; 2922 IntPtrType = SignedInt; 2923 RegParmMax = 3; 2924 2925 // Use fpret for all types. 2926 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2927 (1 << TargetInfo::Double) | 2928 (1 << TargetInfo::LongDouble)); 2929 2930 // x86-32 has atomics up to 8 bytes 2931 // FIXME: Check that we actually have cmpxchg8b before setting 2932 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2933 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2934 } 2935 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2936 return TargetInfo::CharPtrBuiltinVaList; 2937 } 2938 2939 int getEHDataRegisterNumber(unsigned RegNo) const { 2940 if (RegNo == 0) return 0; 2941 if (RegNo == 1) return 2; 2942 return -1; 2943 } 2944 virtual bool validateInputSize(StringRef Constraint, 2945 unsigned Size) const { 2946 switch (Constraint[0]) { 2947 default: break; 2948 case 'a': 2949 case 'b': 2950 case 'c': 2951 case 'd': 2952 return Size <= 32; 2953 } 2954 2955 return true; 2956 } 2957 }; 2958 } // end anonymous namespace 2959 2960 namespace { 2961 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2962 public: 2963 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2964 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2965 2966 virtual unsigned getFloatEvalMethod() const { 2967 unsigned Major, Minor, Micro; 2968 getTriple().getOSVersion(Major, Minor, Micro); 2969 // New NetBSD uses the default rounding mode. 2970 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2971 return X86_32TargetInfo::getFloatEvalMethod(); 2972 // NetBSD before 6.99.26 defaults to "double" rounding. 2973 return 1; 2974 } 2975 }; 2976 } // end anonymous namespace 2977 2978 namespace { 2979 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2980 public: 2981 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2982 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2983 SizeType = UnsignedLong; 2984 IntPtrType = SignedLong; 2985 PtrDiffType = SignedLong; 2986 } 2987 }; 2988 } // end anonymous namespace 2989 2990 namespace { 2991 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2992 public: 2993 BitrigI386TargetInfo(const llvm::Triple &Triple) 2994 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 2995 SizeType = UnsignedLong; 2996 IntPtrType = SignedLong; 2997 PtrDiffType = SignedLong; 2998 } 2999 }; 3000 } // end anonymous namespace 3001 3002 namespace { 3003 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3004 public: 3005 DarwinI386TargetInfo(const llvm::Triple &Triple) 3006 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3007 LongDoubleWidth = 128; 3008 LongDoubleAlign = 128; 3009 SuitableAlign = 128; 3010 MaxVectorAlign = 256; 3011 SizeType = UnsignedLong; 3012 IntPtrType = SignedLong; 3013 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3014 HasAlignMac68kSupport = true; 3015 } 3016 3017 }; 3018 } // end anonymous namespace 3019 3020 namespace { 3021 // x86-32 Windows target 3022 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3023 public: 3024 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3025 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3026 TLSSupported = false; 3027 WCharType = UnsignedShort; 3028 DoubleAlign = LongLongAlign = 64; 3029 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3030 } 3031 virtual void getTargetDefines(const LangOptions &Opts, 3032 MacroBuilder &Builder) const { 3033 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3034 } 3035 }; 3036 } // end anonymous namespace 3037 3038 namespace { 3039 3040 // x86-32 Windows Visual Studio target 3041 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3042 public: 3043 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3044 : WindowsX86_32TargetInfo(Triple) { 3045 LongDoubleWidth = LongDoubleAlign = 64; 3046 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3047 } 3048 virtual void getTargetDefines(const LangOptions &Opts, 3049 MacroBuilder &Builder) const { 3050 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3051 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3052 // The value of the following reflects processor type. 3053 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3054 // We lost the original triple, so we use the default. 3055 Builder.defineMacro("_M_IX86", "600"); 3056 } 3057 }; 3058 } // end anonymous namespace 3059 3060 namespace { 3061 // x86-32 MinGW target 3062 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3063 public: 3064 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3065 : WindowsX86_32TargetInfo(Triple) {} 3066 virtual void getTargetDefines(const LangOptions &Opts, 3067 MacroBuilder &Builder) const { 3068 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3069 DefineStd(Builder, "WIN32", Opts); 3070 DefineStd(Builder, "WINNT", Opts); 3071 Builder.defineMacro("_X86_"); 3072 Builder.defineMacro("__MSVCRT__"); 3073 Builder.defineMacro("__MINGW32__"); 3074 3075 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3076 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3077 if (Opts.MicrosoftExt) 3078 // Provide "as-is" __declspec. 3079 Builder.defineMacro("__declspec", "__declspec"); 3080 else 3081 // Provide alias of __attribute__ like mingw32-gcc. 3082 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3083 } 3084 }; 3085 } // end anonymous namespace 3086 3087 namespace { 3088 // x86-32 Cygwin target 3089 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3090 public: 3091 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3092 : X86_32TargetInfo(Triple) { 3093 TLSSupported = false; 3094 WCharType = UnsignedShort; 3095 DoubleAlign = LongLongAlign = 64; 3096 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3097 } 3098 virtual void getTargetDefines(const LangOptions &Opts, 3099 MacroBuilder &Builder) const { 3100 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3101 Builder.defineMacro("_X86_"); 3102 Builder.defineMacro("__CYGWIN__"); 3103 Builder.defineMacro("__CYGWIN32__"); 3104 DefineStd(Builder, "unix", Opts); 3105 if (Opts.CPlusPlus) 3106 Builder.defineMacro("_GNU_SOURCE"); 3107 } 3108 }; 3109 } // end anonymous namespace 3110 3111 namespace { 3112 // x86-32 Haiku target 3113 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3114 public: 3115 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3116 SizeType = UnsignedLong; 3117 IntPtrType = SignedLong; 3118 PtrDiffType = SignedLong; 3119 ProcessIDType = SignedLong; 3120 this->UserLabelPrefix = ""; 3121 this->TLSSupported = false; 3122 } 3123 virtual void getTargetDefines(const LangOptions &Opts, 3124 MacroBuilder &Builder) const { 3125 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3126 Builder.defineMacro("__INTEL__"); 3127 Builder.defineMacro("__HAIKU__"); 3128 } 3129 }; 3130 } // end anonymous namespace 3131 3132 // RTEMS Target 3133 template<typename Target> 3134 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3135 protected: 3136 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3137 MacroBuilder &Builder) const { 3138 // RTEMS defines; list based off of gcc output 3139 3140 Builder.defineMacro("__rtems__"); 3141 Builder.defineMacro("__ELF__"); 3142 } 3143 3144 public: 3145 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3146 this->UserLabelPrefix = ""; 3147 3148 switch (Triple.getArch()) { 3149 default: 3150 case llvm::Triple::x86: 3151 // this->MCountName = ".mcount"; 3152 break; 3153 case llvm::Triple::mips: 3154 case llvm::Triple::mipsel: 3155 case llvm::Triple::ppc: 3156 case llvm::Triple::ppc64: 3157 case llvm::Triple::ppc64le: 3158 // this->MCountName = "_mcount"; 3159 break; 3160 case llvm::Triple::arm: 3161 // this->MCountName = "__mcount"; 3162 break; 3163 } 3164 } 3165 }; 3166 3167 namespace { 3168 // x86-32 RTEMS target 3169 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3170 public: 3171 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3172 SizeType = UnsignedLong; 3173 IntPtrType = SignedLong; 3174 PtrDiffType = SignedLong; 3175 this->UserLabelPrefix = ""; 3176 } 3177 virtual void getTargetDefines(const LangOptions &Opts, 3178 MacroBuilder &Builder) const { 3179 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3180 Builder.defineMacro("__INTEL__"); 3181 Builder.defineMacro("__rtems__"); 3182 } 3183 }; 3184 } // end anonymous namespace 3185 3186 namespace { 3187 // x86-64 generic target 3188 class X86_64TargetInfo : public X86TargetInfo { 3189 public: 3190 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3191 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3192 LongDoubleWidth = 128; 3193 LongDoubleAlign = 128; 3194 LargeArrayMinWidth = 128; 3195 LargeArrayAlign = 128; 3196 SuitableAlign = 128; 3197 IntMaxType = SignedLong; 3198 UIntMaxType = UnsignedLong; 3199 Int64Type = SignedLong; 3200 RegParmMax = 6; 3201 3202 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3203 3204 // Use fpret only for long double. 3205 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3206 3207 // Use fp2ret for _Complex long double. 3208 ComplexLongDoubleUsesFP2Ret = true; 3209 3210 // x86-64 has atomics up to 16 bytes. 3211 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3212 // on CPUs with cmpxchg16b 3213 MaxAtomicPromoteWidth = 128; 3214 MaxAtomicInlineWidth = 64; 3215 } 3216 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3217 return TargetInfo::X86_64ABIBuiltinVaList; 3218 } 3219 3220 int getEHDataRegisterNumber(unsigned RegNo) const { 3221 if (RegNo == 0) return 0; 3222 if (RegNo == 1) return 1; 3223 return -1; 3224 } 3225 3226 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3227 return (CC == CC_C || 3228 CC == CC_IntelOclBicc || 3229 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3230 } 3231 3232 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3233 return CC_C; 3234 } 3235 3236 }; 3237 } // end anonymous namespace 3238 3239 namespace { 3240 // x86-64 Windows target 3241 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3242 public: 3243 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3244 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3245 TLSSupported = false; 3246 WCharType = UnsignedShort; 3247 LongWidth = LongAlign = 32; 3248 DoubleAlign = LongLongAlign = 64; 3249 IntMaxType = SignedLongLong; 3250 UIntMaxType = UnsignedLongLong; 3251 Int64Type = SignedLongLong; 3252 SizeType = UnsignedLongLong; 3253 PtrDiffType = SignedLongLong; 3254 IntPtrType = SignedLongLong; 3255 this->UserLabelPrefix = ""; 3256 } 3257 virtual void getTargetDefines(const LangOptions &Opts, 3258 MacroBuilder &Builder) const { 3259 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3260 Builder.defineMacro("_WIN64"); 3261 } 3262 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3263 return TargetInfo::CharPtrBuiltinVaList; 3264 } 3265 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3266 return (CC == CC_C || 3267 CC == CC_IntelOclBicc || 3268 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3269 } 3270 }; 3271 } // end anonymous namespace 3272 3273 namespace { 3274 // x86-64 Windows Visual Studio target 3275 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3276 public: 3277 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3278 : WindowsX86_64TargetInfo(Triple) { 3279 LongDoubleWidth = LongDoubleAlign = 64; 3280 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3281 } 3282 virtual void getTargetDefines(const LangOptions &Opts, 3283 MacroBuilder &Builder) const { 3284 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3285 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3286 Builder.defineMacro("_M_X64"); 3287 Builder.defineMacro("_M_AMD64"); 3288 } 3289 }; 3290 } // end anonymous namespace 3291 3292 namespace { 3293 // x86-64 MinGW target 3294 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3295 public: 3296 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3297 : WindowsX86_64TargetInfo(Triple) {} 3298 virtual void getTargetDefines(const LangOptions &Opts, 3299 MacroBuilder &Builder) const { 3300 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3301 DefineStd(Builder, "WIN64", Opts); 3302 Builder.defineMacro("__MSVCRT__"); 3303 Builder.defineMacro("__MINGW32__"); 3304 Builder.defineMacro("__MINGW64__"); 3305 3306 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3307 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3308 if (Opts.MicrosoftExt) 3309 // Provide "as-is" __declspec. 3310 Builder.defineMacro("__declspec", "__declspec"); 3311 else 3312 // Provide alias of __attribute__ like mingw32-gcc. 3313 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3314 } 3315 }; 3316 } // end anonymous namespace 3317 3318 namespace { 3319 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3320 public: 3321 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3322 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3323 Int64Type = SignedLongLong; 3324 MaxVectorAlign = 256; 3325 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3326 } 3327 }; 3328 } // end anonymous namespace 3329 3330 namespace { 3331 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3332 public: 3333 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3334 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3335 IntMaxType = SignedLongLong; 3336 UIntMaxType = UnsignedLongLong; 3337 Int64Type = SignedLongLong; 3338 } 3339 }; 3340 } // end anonymous namespace 3341 3342 namespace { 3343 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3344 public: 3345 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3346 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3347 IntMaxType = SignedLongLong; 3348 UIntMaxType = UnsignedLongLong; 3349 Int64Type = SignedLongLong; 3350 } 3351 }; 3352 } 3353 3354 namespace { 3355 class AArch64TargetInfo : public TargetInfo { 3356 static const char * const GCCRegNames[]; 3357 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3358 3359 enum FPUModeEnum { 3360 FPUMode, 3361 NeonMode 3362 }; 3363 3364 unsigned FPU; 3365 unsigned Crypto; 3366 static const Builtin::Info BuiltinInfo[]; 3367 3368 public: 3369 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3370 IntMaxType = SignedLong; 3371 UIntMaxType = UnsignedLong; 3372 Int64Type = SignedLong; 3373 BigEndian = false; 3374 LongWidth = LongAlign = 64; 3375 LongDoubleWidth = LongDoubleAlign = 128; 3376 PointerWidth = PointerAlign = 64; 3377 SuitableAlign = 128; 3378 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3379 3380 WCharType = UnsignedInt; 3381 if (getTriple().getOS() == llvm::Triple::NetBSD) 3382 WCharType = SignedInt; 3383 else 3384 WCharType = UnsignedInt; 3385 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3386 3387 // AArch64 backend supports 64-bit operations at the moment. In principle 3388 // 128-bit is possible if register-pairs are used. 3389 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3390 3391 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3392 } 3393 virtual void getTargetDefines(const LangOptions &Opts, 3394 MacroBuilder &Builder) const { 3395 // GCC defines theses currently 3396 Builder.defineMacro("__aarch64__"); 3397 Builder.defineMacro("__AARCH64EL__"); 3398 3399 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3400 Builder.defineMacro("__ARM_ACLE", "200"); 3401 Builder.defineMacro("__ARM_ARCH", "8"); 3402 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3403 3404 Builder.defineMacro("__ARM_64BIT_STATE"); 3405 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3406 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3407 3408 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3409 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3410 Builder.defineMacro("__ARM_FEATURE_FMA"); 3411 Builder.defineMacro("__ARM_FEATURE_DIV"); 3412 3413 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3414 3415 // 0xe implies support for half, single and double precision operations. 3416 Builder.defineMacro("__ARM_FP", "0xe"); 3417 3418 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3419 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3420 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3421 3422 if (Opts.FastMath || Opts.FiniteMathOnly) 3423 Builder.defineMacro("__ARM_FP_FAST"); 3424 3425 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3426 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3427 3428 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3429 Opts.ShortWChar ? "2" : "4"); 3430 3431 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3432 Opts.ShortEnums ? "1" : "4"); 3433 3434 if (BigEndian) 3435 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3436 3437 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3438 if (BigEndian) 3439 Builder.defineMacro("__BIG_ENDIAN__"); 3440 else 3441 Builder.defineMacro("__LITTLE_ENDIAN__"); 3442 } 3443 3444 if (FPU == NeonMode) { 3445 Builder.defineMacro("__ARM_NEON"); 3446 // 64-bit NEON supports half, single and double precision operations. 3447 Builder.defineMacro("__ARM_NEON_FP", "7"); 3448 } 3449 3450 if (Crypto) { 3451 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3452 } 3453 } 3454 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3455 unsigned &NumRecords) const { 3456 Records = BuiltinInfo; 3457 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3458 } 3459 virtual bool hasFeature(StringRef Feature) const { 3460 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3461 } 3462 3463 virtual bool setCPU(const std::string &Name) { 3464 return llvm::StringSwitch<bool>(Name) 3465 .Case("generic", true) 3466 .Cases("cortex-a53", "cortex-a57", true) 3467 .Default(false); 3468 } 3469 3470 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3471 DiagnosticsEngine &Diags) { 3472 FPU = FPUMode; 3473 Crypto = 0; 3474 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3475 if (Features[i] == "+neon") 3476 FPU = NeonMode; 3477 if (Features[i] == "+crypto") 3478 Crypto = 1; 3479 } 3480 return true; 3481 } 3482 3483 virtual void getGCCRegNames(const char *const *&Names, 3484 unsigned &NumNames) const; 3485 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3486 unsigned &NumAliases) const; 3487 3488 virtual bool isCLZForZeroUndef() const { return false; } 3489 3490 virtual bool validateAsmConstraint(const char *&Name, 3491 TargetInfo::ConstraintInfo &Info) const { 3492 switch (*Name) { 3493 default: return false; 3494 case 'w': // An FP/SIMD vector register 3495 Info.setAllowsRegister(); 3496 return true; 3497 case 'I': // Constant that can be used with an ADD instruction 3498 case 'J': // Constant that can be used with a SUB instruction 3499 case 'K': // Constant that can be used with a 32-bit logical instruction 3500 case 'L': // Constant that can be used with a 64-bit logical instruction 3501 case 'M': // Constant that can be used as a 32-bit MOV immediate 3502 case 'N': // Constant that can be used as a 64-bit MOV immediate 3503 case 'Y': // Floating point constant zero 3504 case 'Z': // Integer constant zero 3505 return true; 3506 case 'Q': // A memory reference with base register and no offset 3507 Info.setAllowsMemory(); 3508 return true; 3509 case 'S': // A symbolic address 3510 Info.setAllowsRegister(); 3511 return true; 3512 case 'U': 3513 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3514 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3515 // Usa: An absolute symbolic address 3516 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3517 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3518 } 3519 } 3520 3521 virtual const char *getClobbers() const { 3522 // There are no AArch64 clobbers shared by all asm statements. 3523 return ""; 3524 } 3525 3526 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3527 return TargetInfo::AArch64ABIBuiltinVaList; 3528 } 3529 }; 3530 3531 const char * const AArch64TargetInfo::GCCRegNames[] = { 3532 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3533 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3534 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3535 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3536 3537 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3538 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3539 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3540 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3541 3542 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3543 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3544 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3545 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3546 3547 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3548 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3549 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3550 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3551 3552 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3553 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3554 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3555 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3556 3557 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3558 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3559 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3560 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3561 3562 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3563 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3564 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3565 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3566 }; 3567 3568 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3569 unsigned &NumNames) const { 3570 Names = GCCRegNames; 3571 NumNames = llvm::array_lengthof(GCCRegNames); 3572 } 3573 3574 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3575 { { "x16" }, "ip0"}, 3576 { { "x17" }, "ip1"}, 3577 { { "x29" }, "fp" }, 3578 { { "x30" }, "lr" } 3579 }; 3580 3581 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3582 unsigned &NumAliases) const { 3583 Aliases = GCCRegAliases; 3584 NumAliases = llvm::array_lengthof(GCCRegAliases); 3585 3586 } 3587 3588 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3589 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3590 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3591 ALL_LANGUAGES }, 3592 #define GET_NEON_BUILTINS 3593 #include "clang/Basic/arm_neon.inc" 3594 #undef GET_NEON_BUILTINS 3595 3596 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3597 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3598 ALL_LANGUAGES }, 3599 #include "clang/Basic/BuiltinsAArch64.def" 3600 }; 3601 3602 } // end anonymous namespace 3603 3604 namespace { 3605 class ARMTargetInfo : public TargetInfo { 3606 // Possible FPU choices. 3607 enum FPUMode { 3608 VFP2FPU = (1 << 0), 3609 VFP3FPU = (1 << 1), 3610 VFP4FPU = (1 << 2), 3611 NeonFPU = (1 << 3), 3612 FPARMV8 = (1 << 4) 3613 }; 3614 3615 // Possible HWDiv features. 3616 enum HWDivMode { 3617 HWDivThumb = (1 << 0), 3618 HWDivARM = (1 << 1) 3619 }; 3620 3621 static bool FPUModeIsVFP(FPUMode Mode) { 3622 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3623 } 3624 3625 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3626 static const char * const GCCRegNames[]; 3627 3628 std::string ABI, CPU; 3629 3630 enum { 3631 FP_Default, 3632 FP_VFP, 3633 FP_Neon 3634 } FPMath; 3635 3636 unsigned FPU : 5; 3637 3638 unsigned IsAAPCS : 1; 3639 unsigned IsThumb : 1; 3640 unsigned HWDiv : 2; 3641 3642 // Initialized via features. 3643 unsigned SoftFloat : 1; 3644 unsigned SoftFloatABI : 1; 3645 3646 unsigned CRC : 1; 3647 unsigned Crypto : 1; 3648 3649 static const Builtin::Info BuiltinInfo[]; 3650 3651 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3652 // On linux, binaries targeting old cpus call functions in libgcc to 3653 // perform atomic operations. The implementation in libgcc then calls into 3654 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3655 // is that if we assume the kernel is at least as recent as the hardware, 3656 // it is safe to use atomic instructions on armv6 and newer. 3657 if (!T.isOSLinux() && 3658 T.getOS() != llvm::Triple::FreeBSD && 3659 T.getOS() != llvm::Triple::NetBSD && 3660 T.getOS() != llvm::Triple::Bitrig) 3661 return false; 3662 StringRef ArchName = T.getArchName(); 3663 if (T.getArch() == llvm::Triple::arm) { 3664 if (!ArchName.startswith("armv")) 3665 return false; 3666 StringRef VersionStr = ArchName.substr(4); 3667 unsigned Version; 3668 if (VersionStr.getAsInteger(10, Version)) 3669 return false; 3670 return Version >= 6; 3671 } 3672 assert(T.getArch() == llvm::Triple::thumb); 3673 if (!ArchName.startswith("thumbv")) 3674 return false; 3675 StringRef VersionStr = ArchName.substr(6); 3676 unsigned Version; 3677 if (VersionStr.getAsInteger(10, Version)) 3678 return false; 3679 return Version >= 7; 3680 } 3681 3682 void setABIAAPCS() { 3683 IsAAPCS = true; 3684 3685 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3686 const llvm::Triple &T = getTriple(); 3687 3688 // size_t is unsigned long on Darwin and NetBSD. 3689 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3690 SizeType = UnsignedLong; 3691 else 3692 SizeType = UnsignedInt; 3693 3694 if (T.getOS() == llvm::Triple::NetBSD) { 3695 WCharType = SignedInt; 3696 } else { 3697 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3698 WCharType = UnsignedInt; 3699 } 3700 3701 UseBitFieldTypeAlignment = true; 3702 3703 ZeroLengthBitfieldBoundary = 0; 3704 3705 if (IsThumb) { 3706 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3707 // so set preferred for small types to 32. 3708 if (T.isOSBinFormatMachO()) 3709 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3710 "v128:64:128-a:0:32-n32-S64"; 3711 else 3712 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3713 "v128:64:128-a:0:32-n32-S64"; 3714 3715 } else { 3716 if (T.isOSBinFormatMachO()) 3717 DescriptionString = "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3718 else 3719 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3720 } 3721 3722 // FIXME: Enumerated types are variable width in straight AAPCS. 3723 } 3724 3725 void setABIAPCS() { 3726 const llvm::Triple &T = getTriple(); 3727 3728 IsAAPCS = false; 3729 3730 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3731 3732 // size_t is unsigned int on FreeBSD. 3733 if (T.getOS() == llvm::Triple::FreeBSD) 3734 SizeType = UnsignedInt; 3735 else 3736 SizeType = UnsignedLong; 3737 3738 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3739 WCharType = SignedInt; 3740 3741 // Do not respect the alignment of bit-field types when laying out 3742 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3743 UseBitFieldTypeAlignment = false; 3744 3745 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3746 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3747 /// gcc. 3748 ZeroLengthBitfieldBoundary = 32; 3749 3750 if (IsThumb) { 3751 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3752 // so set preferred for small types to 32. 3753 if (T.isOSBinFormatMachO()) 3754 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3755 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3756 else 3757 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3758 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3759 } else { 3760 if (T.isOSBinFormatMachO()) 3761 DescriptionString = 3762 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3763 else 3764 DescriptionString = 3765 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3766 } 3767 3768 // FIXME: Override "preferred align" for double and long long. 3769 } 3770 3771 public: 3772 ARMTargetInfo(const llvm::Triple &Triple) 3773 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3774 IsAAPCS(true) { 3775 BigEndian = false; 3776 switch (getTriple().getOS()) { 3777 case llvm::Triple::NetBSD: 3778 PtrDiffType = SignedLong; 3779 break; 3780 default: 3781 PtrDiffType = SignedInt; 3782 break; 3783 } 3784 3785 // {} in inline assembly are neon specifiers, not assembly variant 3786 // specifiers. 3787 NoAsmVariants = true; 3788 3789 // FIXME: Should we just treat this as a feature? 3790 IsThumb = getTriple().getArchName().startswith("thumb"); 3791 3792 setABI("aapcs-linux"); 3793 3794 // ARM targets default to using the ARM C++ ABI. 3795 TheCXXABI.set(TargetCXXABI::GenericARM); 3796 3797 // ARM has atomics up to 8 bytes 3798 MaxAtomicPromoteWidth = 64; 3799 if (shouldUseInlineAtomic(getTriple())) 3800 MaxAtomicInlineWidth = 64; 3801 3802 // Do force alignment of members that follow zero length bitfields. If 3803 // the alignment of the zero-length bitfield is greater than the member 3804 // that follows it, `bar', `bar' will be aligned as the type of the 3805 // zero length bitfield. 3806 UseZeroLengthBitfieldAlignment = true; 3807 } 3808 virtual const char *getABI() const { return ABI.c_str(); } 3809 virtual bool setABI(const std::string &Name) { 3810 ABI = Name; 3811 3812 // The defaults (above) are for AAPCS, check if we need to change them. 3813 // 3814 // FIXME: We need support for -meabi... we could just mangle it into the 3815 // name. 3816 if (Name == "apcs-gnu") { 3817 setABIAPCS(); 3818 return true; 3819 } 3820 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3821 setABIAAPCS(); 3822 return true; 3823 } 3824 return false; 3825 } 3826 3827 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3828 if (IsAAPCS) 3829 Features["aapcs"] = true; 3830 else 3831 Features["apcs"] = true; 3832 3833 StringRef ArchName = getTriple().getArchName(); 3834 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3835 Features["vfp2"] = true; 3836 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3837 CPU == "cortex-a9-mp") { 3838 Features["vfp3"] = true; 3839 Features["neon"] = true; 3840 } 3841 else if (CPU == "cortex-a5") { 3842 Features["vfp4"] = true; 3843 Features["neon"] = true; 3844 } else if (CPU == "swift" || CPU == "cortex-a7" || 3845 CPU == "cortex-a12" || CPU == "cortex-a15" || 3846 CPU == "krait") { 3847 Features["vfp4"] = true; 3848 Features["neon"] = true; 3849 Features["hwdiv"] = true; 3850 Features["hwdiv-arm"] = true; 3851 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3852 Features["fp-armv8"] = true; 3853 Features["neon"] = true; 3854 Features["hwdiv"] = true; 3855 Features["hwdiv-arm"] = true; 3856 Features["crc"] = true; 3857 Features["crypto"] = true; 3858 } else if (CPU == "cortex-r5" || 3859 // Enable the hwdiv extension for all v8a AArch32 cores by 3860 // default. 3861 ArchName == "armv8a" || ArchName == "armv8" || 3862 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3863 Features["hwdiv"] = true; 3864 Features["hwdiv-arm"] = true; 3865 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3866 Features["hwdiv"] = true; 3867 } 3868 } 3869 3870 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3871 DiagnosticsEngine &Diags) { 3872 FPU = 0; 3873 CRC = 0; 3874 Crypto = 0; 3875 SoftFloat = SoftFloatABI = false; 3876 HWDiv = 0; 3877 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3878 if (Features[i] == "+soft-float") 3879 SoftFloat = true; 3880 else if (Features[i] == "+soft-float-abi") 3881 SoftFloatABI = true; 3882 else if (Features[i] == "+vfp2") 3883 FPU |= VFP2FPU; 3884 else if (Features[i] == "+vfp3") 3885 FPU |= VFP3FPU; 3886 else if (Features[i] == "+vfp4") 3887 FPU |= VFP4FPU; 3888 else if (Features[i] == "+fp-armv8") 3889 FPU |= FPARMV8; 3890 else if (Features[i] == "+neon") 3891 FPU |= NeonFPU; 3892 else if (Features[i] == "+hwdiv") 3893 HWDiv |= HWDivThumb; 3894 else if (Features[i] == "+hwdiv-arm") 3895 HWDiv |= HWDivARM; 3896 else if (Features[i] == "+crc") 3897 CRC = 1; 3898 else if (Features[i] == "+crypto") 3899 Crypto = 1; 3900 } 3901 3902 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3903 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3904 return false; 3905 } 3906 3907 if (FPMath == FP_Neon) 3908 Features.push_back("+neonfp"); 3909 else if (FPMath == FP_VFP) 3910 Features.push_back("-neonfp"); 3911 3912 // Remove front-end specific options which the backend handles differently. 3913 std::vector<std::string>::iterator it; 3914 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3915 if (it != Features.end()) 3916 Features.erase(it); 3917 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3918 if (it != Features.end()) 3919 Features.erase(it); 3920 return true; 3921 } 3922 3923 virtual bool hasFeature(StringRef Feature) const { 3924 return llvm::StringSwitch<bool>(Feature) 3925 .Case("arm", true) 3926 .Case("softfloat", SoftFloat) 3927 .Case("thumb", IsThumb) 3928 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3929 .Case("hwdiv", HWDiv & HWDivThumb) 3930 .Case("hwdiv-arm", HWDiv & HWDivARM) 3931 .Default(false); 3932 } 3933 // FIXME: Should we actually have some table instead of these switches? 3934 static const char *getCPUDefineSuffix(StringRef Name) { 3935 return llvm::StringSwitch<const char*>(Name) 3936 .Cases("arm8", "arm810", "4") 3937 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3938 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3939 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3940 .Case("ep9312", "4T") 3941 .Cases("arm10tdmi", "arm1020t", "5T") 3942 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3943 .Case("arm926ej-s", "5TEJ") 3944 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3945 .Cases("xscale", "iwmmxt", "5TE") 3946 .Case("arm1136j-s", "6J") 3947 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3948 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3949 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3950 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3951 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3952 .Cases("cortex-r4", "cortex-r5", "7R") 3953 .Case("swift", "7S") 3954 .Cases("cortex-m3", "cortex-m4", "7M") 3955 .Case("cortex-m0", "6M") 3956 .Cases("cortex-a53", "cortex-a57", "8A") 3957 .Default(0); 3958 } 3959 static const char *getCPUProfile(StringRef Name) { 3960 return llvm::StringSwitch<const char*>(Name) 3961 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3962 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 3963 .Cases("cortex-a53", "cortex-a57", "A") 3964 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3965 .Cases("cortex-r4", "cortex-r5", "R") 3966 .Default(""); 3967 } 3968 virtual bool setCPU(const std::string &Name) { 3969 if (!getCPUDefineSuffix(Name)) 3970 return false; 3971 3972 CPU = Name; 3973 return true; 3974 } 3975 virtual bool setFPMath(StringRef Name); 3976 virtual void getTargetDefines(const LangOptions &Opts, 3977 MacroBuilder &Builder) const { 3978 // Target identification. 3979 Builder.defineMacro("__arm"); 3980 Builder.defineMacro("__arm__"); 3981 3982 // Target properties. 3983 Builder.defineMacro("__ARMEL__"); 3984 Builder.defineMacro("__LITTLE_ENDIAN__"); 3985 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3986 3987 StringRef CPUArch = getCPUDefineSuffix(CPU); 3988 unsigned int CPUArchVer; 3989 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3990 llvm_unreachable("Invalid char for architecture version number"); 3991 } 3992 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3993 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3994 StringRef CPUProfile = getCPUProfile(CPU); 3995 if (!CPUProfile.empty()) 3996 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3997 3998 // Subtarget options. 3999 4000 // FIXME: It's more complicated than this and we don't really support 4001 // interworking. 4002 if (5 <= CPUArchVer && CPUArchVer <= 8) 4003 Builder.defineMacro("__THUMB_INTERWORK__"); 4004 4005 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4006 // Embedded targets on Darwin follow AAPCS, but not EABI. 4007 if (!getTriple().isOSDarwin()) 4008 Builder.defineMacro("__ARM_EABI__"); 4009 Builder.defineMacro("__ARM_PCS", "1"); 4010 4011 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4012 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4013 } 4014 4015 if (SoftFloat) 4016 Builder.defineMacro("__SOFTFP__"); 4017 4018 if (CPU == "xscale") 4019 Builder.defineMacro("__XSCALE__"); 4020 4021 if (IsThumb) { 4022 Builder.defineMacro("__THUMBEL__"); 4023 Builder.defineMacro("__thumb__"); 4024 // We check both CPUArchVer and ArchName because when only triple is 4025 // specified, the default CPU is arm1136j-s. 4026 StringRef ArchName = getTriple().getArchName(); 4027 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4028 ArchName.endswith("v7") || ArchName.endswith("v8")) 4029 Builder.defineMacro("__thumb2__"); 4030 } 4031 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4032 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4033 4034 // Note, this is always on in gcc, even though it doesn't make sense. 4035 Builder.defineMacro("__APCS_32__"); 4036 4037 if (FPUModeIsVFP((FPUMode) FPU)) { 4038 Builder.defineMacro("__VFP_FP__"); 4039 if (FPU & VFP2FPU) 4040 Builder.defineMacro("__ARM_VFPV2__"); 4041 if (FPU & VFP3FPU) 4042 Builder.defineMacro("__ARM_VFPV3__"); 4043 if (FPU & VFP4FPU) 4044 Builder.defineMacro("__ARM_VFPV4__"); 4045 } 4046 4047 // This only gets set when Neon instructions are actually available, unlike 4048 // the VFP define, hence the soft float and arch check. This is subtly 4049 // different from gcc, we follow the intent which was that it should be set 4050 // when Neon instructions are actually available. 4051 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4052 Builder.defineMacro("__ARM_NEON"); 4053 Builder.defineMacro("__ARM_NEON__"); 4054 } 4055 4056 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4057 Opts.ShortWChar ? "2" : "4"); 4058 4059 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4060 Opts.ShortEnums ? "1" : "4"); 4061 4062 if (CRC) 4063 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4064 4065 if (Crypto) 4066 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4067 4068 if (CPUArchVer >= 6 && CPUArch != "6M") { 4069 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4070 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4071 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4072 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4073 } 4074 } 4075 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4076 unsigned &NumRecords) const { 4077 Records = BuiltinInfo; 4078 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4079 } 4080 virtual bool isCLZForZeroUndef() const { return false; } 4081 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4082 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4083 } 4084 virtual void getGCCRegNames(const char * const *&Names, 4085 unsigned &NumNames) const; 4086 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4087 unsigned &NumAliases) const; 4088 virtual bool validateAsmConstraint(const char *&Name, 4089 TargetInfo::ConstraintInfo &Info) const { 4090 switch (*Name) { 4091 default: break; 4092 case 'l': // r0-r7 4093 case 'h': // r8-r15 4094 case 'w': // VFP Floating point register single precision 4095 case 'P': // VFP Floating point register double precision 4096 Info.setAllowsRegister(); 4097 return true; 4098 case 'Q': // A memory address that is a single base register. 4099 Info.setAllowsMemory(); 4100 return true; 4101 case 'U': // a memory reference... 4102 switch (Name[1]) { 4103 case 'q': // ...ARMV4 ldrsb 4104 case 'v': // ...VFP load/store (reg+constant offset) 4105 case 'y': // ...iWMMXt load/store 4106 case 't': // address valid for load/store opaque types wider 4107 // than 128-bits 4108 case 'n': // valid address for Neon doubleword vector load/store 4109 case 'm': // valid address for Neon element and structure load/store 4110 case 's': // valid address for non-offset loads/stores of quad-word 4111 // values in four ARM registers 4112 Info.setAllowsMemory(); 4113 Name++; 4114 return true; 4115 } 4116 } 4117 return false; 4118 } 4119 virtual std::string convertConstraint(const char *&Constraint) const { 4120 std::string R; 4121 switch (*Constraint) { 4122 case 'U': // Two-character constraint; add "^" hint for later parsing. 4123 R = std::string("^") + std::string(Constraint, 2); 4124 Constraint++; 4125 break; 4126 case 'p': // 'p' should be translated to 'r' by default. 4127 R = std::string("r"); 4128 break; 4129 default: 4130 return std::string(1, *Constraint); 4131 } 4132 return R; 4133 } 4134 virtual bool validateConstraintModifier(StringRef Constraint, 4135 const char Modifier, 4136 unsigned Size) const { 4137 bool isOutput = (Constraint[0] == '='); 4138 bool isInOut = (Constraint[0] == '+'); 4139 4140 // Strip off constraint modifiers. 4141 while (Constraint[0] == '=' || 4142 Constraint[0] == '+' || 4143 Constraint[0] == '&') 4144 Constraint = Constraint.substr(1); 4145 4146 switch (Constraint[0]) { 4147 default: break; 4148 case 'r': { 4149 switch (Modifier) { 4150 default: 4151 return (isInOut || isOutput || Size <= 64); 4152 case 'q': 4153 // A register of size 32 cannot fit a vector type. 4154 return false; 4155 } 4156 } 4157 } 4158 4159 return true; 4160 } 4161 virtual const char *getClobbers() const { 4162 // FIXME: Is this really right? 4163 return ""; 4164 } 4165 4166 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4167 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4168 } 4169 4170 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4171 if (RegNo == 0) return 0; 4172 if (RegNo == 1) return 1; 4173 return -1; 4174 } 4175 }; 4176 4177 bool ARMTargetInfo::setFPMath(StringRef Name) { 4178 if (Name == "neon") { 4179 FPMath = FP_Neon; 4180 return true; 4181 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4182 Name == "vfp4") { 4183 FPMath = FP_VFP; 4184 return true; 4185 } 4186 return false; 4187 } 4188 4189 const char * const ARMTargetInfo::GCCRegNames[] = { 4190 // Integer registers 4191 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4192 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4193 4194 // Float registers 4195 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4196 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4197 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4198 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4199 4200 // Double registers 4201 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4202 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4203 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4204 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4205 4206 // Quad registers 4207 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4208 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4209 }; 4210 4211 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4212 unsigned &NumNames) const { 4213 Names = GCCRegNames; 4214 NumNames = llvm::array_lengthof(GCCRegNames); 4215 } 4216 4217 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4218 { { "a1" }, "r0" }, 4219 { { "a2" }, "r1" }, 4220 { { "a3" }, "r2" }, 4221 { { "a4" }, "r3" }, 4222 { { "v1" }, "r4" }, 4223 { { "v2" }, "r5" }, 4224 { { "v3" }, "r6" }, 4225 { { "v4" }, "r7" }, 4226 { { "v5" }, "r8" }, 4227 { { "v6", "rfp" }, "r9" }, 4228 { { "sl" }, "r10" }, 4229 { { "fp" }, "r11" }, 4230 { { "ip" }, "r12" }, 4231 { { "r13" }, "sp" }, 4232 { { "r14" }, "lr" }, 4233 { { "r15" }, "pc" }, 4234 // The S, D and Q registers overlap, but aren't really aliases; we 4235 // don't want to substitute one of these for a different-sized one. 4236 }; 4237 4238 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4239 unsigned &NumAliases) const { 4240 Aliases = GCCRegAliases; 4241 NumAliases = llvm::array_lengthof(GCCRegAliases); 4242 } 4243 4244 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4245 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4246 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4247 ALL_LANGUAGES }, 4248 #define GET_NEON_BUILTINS 4249 #include "clang/Basic/arm_neon.inc" 4250 #undef GET_NEON_BUILTINS 4251 4252 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4253 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4254 ALL_LANGUAGES }, 4255 #include "clang/Basic/BuiltinsARM.def" 4256 }; 4257 } // end anonymous namespace. 4258 4259 namespace { 4260 class DarwinARMTargetInfo : 4261 public DarwinTargetInfo<ARMTargetInfo> { 4262 protected: 4263 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4264 MacroBuilder &Builder) const { 4265 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4266 } 4267 4268 public: 4269 DarwinARMTargetInfo(const llvm::Triple &Triple) 4270 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4271 HasAlignMac68kSupport = true; 4272 // iOS always has 64-bit atomic instructions. 4273 // FIXME: This should be based off of the target features in ARMTargetInfo. 4274 MaxAtomicInlineWidth = 64; 4275 4276 // Darwin on iOS uses a variant of the ARM C++ ABI. 4277 TheCXXABI.set(TargetCXXABI::iOS); 4278 } 4279 }; 4280 } // end anonymous namespace. 4281 4282 4283 namespace { 4284 // Hexagon abstract base class 4285 class HexagonTargetInfo : public TargetInfo { 4286 static const Builtin::Info BuiltinInfo[]; 4287 static const char * const GCCRegNames[]; 4288 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4289 std::string CPU; 4290 public: 4291 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4292 BigEndian = false; 4293 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4294 4295 // {} in inline assembly are packet specifiers, not assembly variant 4296 // specifiers. 4297 NoAsmVariants = true; 4298 } 4299 4300 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4301 unsigned &NumRecords) const { 4302 Records = BuiltinInfo; 4303 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4304 } 4305 4306 virtual bool validateAsmConstraint(const char *&Name, 4307 TargetInfo::ConstraintInfo &Info) const { 4308 return true; 4309 } 4310 4311 virtual void getTargetDefines(const LangOptions &Opts, 4312 MacroBuilder &Builder) const; 4313 4314 virtual bool hasFeature(StringRef Feature) const { 4315 return Feature == "hexagon"; 4316 } 4317 4318 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4319 return TargetInfo::CharPtrBuiltinVaList; 4320 } 4321 virtual void getGCCRegNames(const char * const *&Names, 4322 unsigned &NumNames) const; 4323 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4324 unsigned &NumAliases) const; 4325 virtual const char *getClobbers() const { 4326 return ""; 4327 } 4328 4329 static const char *getHexagonCPUSuffix(StringRef Name) { 4330 return llvm::StringSwitch<const char*>(Name) 4331 .Case("hexagonv4", "4") 4332 .Case("hexagonv5", "5") 4333 .Default(0); 4334 } 4335 4336 virtual bool setCPU(const std::string &Name) { 4337 if (!getHexagonCPUSuffix(Name)) 4338 return false; 4339 4340 CPU = Name; 4341 return true; 4342 } 4343 }; 4344 4345 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4346 MacroBuilder &Builder) const { 4347 Builder.defineMacro("qdsp6"); 4348 Builder.defineMacro("__qdsp6", "1"); 4349 Builder.defineMacro("__qdsp6__", "1"); 4350 4351 Builder.defineMacro("hexagon"); 4352 Builder.defineMacro("__hexagon", "1"); 4353 Builder.defineMacro("__hexagon__", "1"); 4354 4355 if(CPU == "hexagonv1") { 4356 Builder.defineMacro("__HEXAGON_V1__"); 4357 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4358 if(Opts.HexagonQdsp6Compat) { 4359 Builder.defineMacro("__QDSP6_V1__"); 4360 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4361 } 4362 } 4363 else if(CPU == "hexagonv2") { 4364 Builder.defineMacro("__HEXAGON_V2__"); 4365 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4366 if(Opts.HexagonQdsp6Compat) { 4367 Builder.defineMacro("__QDSP6_V2__"); 4368 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4369 } 4370 } 4371 else if(CPU == "hexagonv3") { 4372 Builder.defineMacro("__HEXAGON_V3__"); 4373 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4374 if(Opts.HexagonQdsp6Compat) { 4375 Builder.defineMacro("__QDSP6_V3__"); 4376 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4377 } 4378 } 4379 else if(CPU == "hexagonv4") { 4380 Builder.defineMacro("__HEXAGON_V4__"); 4381 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4382 if(Opts.HexagonQdsp6Compat) { 4383 Builder.defineMacro("__QDSP6_V4__"); 4384 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4385 } 4386 } 4387 else if(CPU == "hexagonv5") { 4388 Builder.defineMacro("__HEXAGON_V5__"); 4389 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4390 if(Opts.HexagonQdsp6Compat) { 4391 Builder.defineMacro("__QDSP6_V5__"); 4392 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4393 } 4394 } 4395 } 4396 4397 const char * const HexagonTargetInfo::GCCRegNames[] = { 4398 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4399 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4400 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4401 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4402 "p0", "p1", "p2", "p3", 4403 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4404 }; 4405 4406 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4407 unsigned &NumNames) const { 4408 Names = GCCRegNames; 4409 NumNames = llvm::array_lengthof(GCCRegNames); 4410 } 4411 4412 4413 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4414 { { "sp" }, "r29" }, 4415 { { "fp" }, "r30" }, 4416 { { "lr" }, "r31" }, 4417 }; 4418 4419 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4420 unsigned &NumAliases) const { 4421 Aliases = GCCRegAliases; 4422 NumAliases = llvm::array_lengthof(GCCRegAliases); 4423 } 4424 4425 4426 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4427 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4428 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4429 ALL_LANGUAGES }, 4430 #include "clang/Basic/BuiltinsHexagon.def" 4431 }; 4432 } 4433 4434 4435 namespace { 4436 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4437 class SparcTargetInfo : public TargetInfo { 4438 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4439 static const char * const GCCRegNames[]; 4440 bool SoftFloat; 4441 public: 4442 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4443 4444 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4445 DiagnosticsEngine &Diags) { 4446 SoftFloat = false; 4447 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4448 if (Features[i] == "+soft-float") 4449 SoftFloat = true; 4450 return true; 4451 } 4452 virtual void getTargetDefines(const LangOptions &Opts, 4453 MacroBuilder &Builder) const { 4454 DefineStd(Builder, "sparc", Opts); 4455 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4456 4457 if (SoftFloat) 4458 Builder.defineMacro("SOFT_FLOAT", "1"); 4459 } 4460 4461 virtual bool hasFeature(StringRef Feature) const { 4462 return llvm::StringSwitch<bool>(Feature) 4463 .Case("softfloat", SoftFloat) 4464 .Case("sparc", true) 4465 .Default(false); 4466 } 4467 4468 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4469 unsigned &NumRecords) const { 4470 // FIXME: Implement! 4471 } 4472 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4473 return TargetInfo::VoidPtrBuiltinVaList; 4474 } 4475 virtual void getGCCRegNames(const char * const *&Names, 4476 unsigned &NumNames) const; 4477 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4478 unsigned &NumAliases) const; 4479 virtual bool validateAsmConstraint(const char *&Name, 4480 TargetInfo::ConstraintInfo &info) const { 4481 // FIXME: Implement! 4482 return false; 4483 } 4484 virtual const char *getClobbers() const { 4485 // FIXME: Implement! 4486 return ""; 4487 } 4488 }; 4489 4490 const char * const SparcTargetInfo::GCCRegNames[] = { 4491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4495 }; 4496 4497 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4498 unsigned &NumNames) const { 4499 Names = GCCRegNames; 4500 NumNames = llvm::array_lengthof(GCCRegNames); 4501 } 4502 4503 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4504 { { "g0" }, "r0" }, 4505 { { "g1" }, "r1" }, 4506 { { "g2" }, "r2" }, 4507 { { "g3" }, "r3" }, 4508 { { "g4" }, "r4" }, 4509 { { "g5" }, "r5" }, 4510 { { "g6" }, "r6" }, 4511 { { "g7" }, "r7" }, 4512 { { "o0" }, "r8" }, 4513 { { "o1" }, "r9" }, 4514 { { "o2" }, "r10" }, 4515 { { "o3" }, "r11" }, 4516 { { "o4" }, "r12" }, 4517 { { "o5" }, "r13" }, 4518 { { "o6", "sp" }, "r14" }, 4519 { { "o7" }, "r15" }, 4520 { { "l0" }, "r16" }, 4521 { { "l1" }, "r17" }, 4522 { { "l2" }, "r18" }, 4523 { { "l3" }, "r19" }, 4524 { { "l4" }, "r20" }, 4525 { { "l5" }, "r21" }, 4526 { { "l6" }, "r22" }, 4527 { { "l7" }, "r23" }, 4528 { { "i0" }, "r24" }, 4529 { { "i1" }, "r25" }, 4530 { { "i2" }, "r26" }, 4531 { { "i3" }, "r27" }, 4532 { { "i4" }, "r28" }, 4533 { { "i5" }, "r29" }, 4534 { { "i6", "fp" }, "r30" }, 4535 { { "i7" }, "r31" }, 4536 }; 4537 4538 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4539 unsigned &NumAliases) const { 4540 Aliases = GCCRegAliases; 4541 NumAliases = llvm::array_lengthof(GCCRegAliases); 4542 } 4543 4544 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4545 class SparcV8TargetInfo : public SparcTargetInfo { 4546 public: 4547 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4548 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4549 } 4550 4551 virtual void getTargetDefines(const LangOptions &Opts, 4552 MacroBuilder &Builder) const { 4553 SparcTargetInfo::getTargetDefines(Opts, Builder); 4554 Builder.defineMacro("__sparcv8"); 4555 } 4556 }; 4557 4558 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4559 class SparcV9TargetInfo : public SparcTargetInfo { 4560 public: 4561 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4562 // FIXME: Support Sparc quad-precision long double? 4563 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4564 // This is an LP64 platform. 4565 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4566 4567 // OpenBSD uses long long for int64_t and intmax_t. 4568 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4569 IntMaxType = SignedLongLong; 4570 UIntMaxType = UnsignedLongLong; 4571 } else { 4572 IntMaxType = SignedLong; 4573 UIntMaxType = UnsignedLong; 4574 } 4575 Int64Type = IntMaxType; 4576 4577 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4578 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4579 LongDoubleWidth = 128; 4580 LongDoubleAlign = 128; 4581 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4582 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4583 } 4584 4585 virtual void getTargetDefines(const LangOptions &Opts, 4586 MacroBuilder &Builder) const { 4587 SparcTargetInfo::getTargetDefines(Opts, Builder); 4588 Builder.defineMacro("__sparcv9"); 4589 Builder.defineMacro("__arch64__"); 4590 // Solaris and its derivative AuroraUX don't need these variants, but the 4591 // BSDs do. 4592 if (getTriple().getOS() != llvm::Triple::Solaris && 4593 getTriple().getOS() != llvm::Triple::AuroraUX) { 4594 Builder.defineMacro("__sparc64__"); 4595 Builder.defineMacro("__sparc_v9__"); 4596 Builder.defineMacro("__sparcv9__"); 4597 } 4598 } 4599 }; 4600 4601 } // end anonymous namespace. 4602 4603 namespace { 4604 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4605 public: 4606 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4607 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4608 SizeType = UnsignedInt; 4609 PtrDiffType = SignedInt; 4610 } 4611 }; 4612 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4613 public: 4614 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4615 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4616 SizeType = UnsignedInt; 4617 PtrDiffType = SignedInt; 4618 } 4619 }; 4620 } // end anonymous namespace. 4621 4622 namespace { 4623 class SystemZTargetInfo : public TargetInfo { 4624 static const char *const GCCRegNames[]; 4625 4626 public: 4627 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4628 TLSSupported = true; 4629 IntWidth = IntAlign = 32; 4630 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4631 PointerWidth = PointerAlign = 64; 4632 LongDoubleWidth = 128; 4633 LongDoubleAlign = 64; 4634 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4635 MinGlobalAlign = 16; 4636 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4637 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4638 } 4639 virtual void getTargetDefines(const LangOptions &Opts, 4640 MacroBuilder &Builder) const { 4641 Builder.defineMacro("__s390__"); 4642 Builder.defineMacro("__s390x__"); 4643 Builder.defineMacro("__zarch__"); 4644 Builder.defineMacro("__LONG_DOUBLE_128__"); 4645 } 4646 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4647 unsigned &NumRecords) const { 4648 // FIXME: Implement. 4649 Records = 0; 4650 NumRecords = 0; 4651 } 4652 4653 virtual void getGCCRegNames(const char *const *&Names, 4654 unsigned &NumNames) const; 4655 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4656 unsigned &NumAliases) const { 4657 // No aliases. 4658 Aliases = 0; 4659 NumAliases = 0; 4660 } 4661 virtual bool validateAsmConstraint(const char *&Name, 4662 TargetInfo::ConstraintInfo &info) const; 4663 virtual const char *getClobbers() const { 4664 // FIXME: Is this really right? 4665 return ""; 4666 } 4667 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4668 return TargetInfo::SystemZBuiltinVaList; 4669 } 4670 virtual bool setCPU(const std::string &Name) { 4671 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4672 .Case("z10", true) 4673 .Case("z196", true) 4674 .Case("zEC12", true) 4675 .Default(false); 4676 4677 // No need to store the CPU yet. There aren't any CPU-specific 4678 // macros to define. 4679 return CPUKnown; 4680 } 4681 }; 4682 4683 const char *const SystemZTargetInfo::GCCRegNames[] = { 4684 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4685 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4686 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4687 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4688 }; 4689 4690 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4691 unsigned &NumNames) const { 4692 Names = GCCRegNames; 4693 NumNames = llvm::array_lengthof(GCCRegNames); 4694 } 4695 4696 bool SystemZTargetInfo:: 4697 validateAsmConstraint(const char *&Name, 4698 TargetInfo::ConstraintInfo &Info) const { 4699 switch (*Name) { 4700 default: 4701 return false; 4702 4703 case 'a': // Address register 4704 case 'd': // Data register (equivalent to 'r') 4705 case 'f': // Floating-point register 4706 Info.setAllowsRegister(); 4707 return true; 4708 4709 case 'I': // Unsigned 8-bit constant 4710 case 'J': // Unsigned 12-bit constant 4711 case 'K': // Signed 16-bit constant 4712 case 'L': // Signed 20-bit displacement (on all targets we support) 4713 case 'M': // 0x7fffffff 4714 return true; 4715 4716 case 'Q': // Memory with base and unsigned 12-bit displacement 4717 case 'R': // Likewise, plus an index 4718 case 'S': // Memory with base and signed 20-bit displacement 4719 case 'T': // Likewise, plus an index 4720 Info.setAllowsMemory(); 4721 return true; 4722 } 4723 } 4724 } 4725 4726 namespace { 4727 class MSP430TargetInfo : public TargetInfo { 4728 static const char * const GCCRegNames[]; 4729 public: 4730 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4731 BigEndian = false; 4732 TLSSupported = false; 4733 IntWidth = 16; IntAlign = 16; 4734 LongWidth = 32; LongLongWidth = 64; 4735 LongAlign = LongLongAlign = 16; 4736 PointerWidth = 16; PointerAlign = 16; 4737 SuitableAlign = 16; 4738 SizeType = UnsignedInt; 4739 IntMaxType = SignedLongLong; 4740 UIntMaxType = UnsignedLongLong; 4741 IntPtrType = SignedInt; 4742 PtrDiffType = SignedInt; 4743 SigAtomicType = SignedLong; 4744 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4745 } 4746 virtual void getTargetDefines(const LangOptions &Opts, 4747 MacroBuilder &Builder) const { 4748 Builder.defineMacro("MSP430"); 4749 Builder.defineMacro("__MSP430__"); 4750 // FIXME: defines for different 'flavours' of MCU 4751 } 4752 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4753 unsigned &NumRecords) const { 4754 // FIXME: Implement. 4755 Records = 0; 4756 NumRecords = 0; 4757 } 4758 virtual bool hasFeature(StringRef Feature) const { 4759 return Feature == "msp430"; 4760 } 4761 virtual void getGCCRegNames(const char * const *&Names, 4762 unsigned &NumNames) const; 4763 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4764 unsigned &NumAliases) const { 4765 // No aliases. 4766 Aliases = 0; 4767 NumAliases = 0; 4768 } 4769 virtual bool validateAsmConstraint(const char *&Name, 4770 TargetInfo::ConstraintInfo &info) const { 4771 // No target constraints for now. 4772 return false; 4773 } 4774 virtual const char *getClobbers() const { 4775 // FIXME: Is this really right? 4776 return ""; 4777 } 4778 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4779 // FIXME: implement 4780 return TargetInfo::CharPtrBuiltinVaList; 4781 } 4782 }; 4783 4784 const char * const MSP430TargetInfo::GCCRegNames[] = { 4785 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4786 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4787 }; 4788 4789 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4790 unsigned &NumNames) const { 4791 Names = GCCRegNames; 4792 NumNames = llvm::array_lengthof(GCCRegNames); 4793 } 4794 } 4795 4796 namespace { 4797 4798 // LLVM and Clang cannot be used directly to output native binaries for 4799 // target, but is used to compile C code to llvm bitcode with correct 4800 // type and alignment information. 4801 // 4802 // TCE uses the llvm bitcode as input and uses it for generating customized 4803 // target processor and program binary. TCE co-design environment is 4804 // publicly available in http://tce.cs.tut.fi 4805 4806 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4807 3, // opencl_global 4808 4, // opencl_local 4809 5, // opencl_constant 4810 0, // cuda_device 4811 0, // cuda_constant 4812 0 // cuda_shared 4813 }; 4814 4815 class TCETargetInfo : public TargetInfo{ 4816 public: 4817 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4818 TLSSupported = false; 4819 IntWidth = 32; 4820 LongWidth = LongLongWidth = 32; 4821 PointerWidth = 32; 4822 IntAlign = 32; 4823 LongAlign = LongLongAlign = 32; 4824 PointerAlign = 32; 4825 SuitableAlign = 32; 4826 SizeType = UnsignedInt; 4827 IntMaxType = SignedLong; 4828 UIntMaxType = UnsignedLong; 4829 IntPtrType = SignedInt; 4830 PtrDiffType = SignedInt; 4831 FloatWidth = 32; 4832 FloatAlign = 32; 4833 DoubleWidth = 32; 4834 DoubleAlign = 32; 4835 LongDoubleWidth = 32; 4836 LongDoubleAlign = 32; 4837 FloatFormat = &llvm::APFloat::IEEEsingle; 4838 DoubleFormat = &llvm::APFloat::IEEEsingle; 4839 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4840 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4841 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4842 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4843 UseAddrSpaceMapMangling = true; 4844 } 4845 4846 virtual void getTargetDefines(const LangOptions &Opts, 4847 MacroBuilder &Builder) const { 4848 DefineStd(Builder, "tce", Opts); 4849 Builder.defineMacro("__TCE__"); 4850 Builder.defineMacro("__TCE_V1__"); 4851 } 4852 virtual bool hasFeature(StringRef Feature) const { 4853 return Feature == "tce"; 4854 } 4855 4856 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4857 unsigned &NumRecords) const {} 4858 virtual const char *getClobbers() const { 4859 return ""; 4860 } 4861 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4862 return TargetInfo::VoidPtrBuiltinVaList; 4863 } 4864 virtual void getGCCRegNames(const char * const *&Names, 4865 unsigned &NumNames) const {} 4866 virtual bool validateAsmConstraint(const char *&Name, 4867 TargetInfo::ConstraintInfo &info) const { 4868 return true; 4869 } 4870 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4871 unsigned &NumAliases) const {} 4872 }; 4873 } 4874 4875 namespace { 4876 class MipsTargetInfoBase : public TargetInfo { 4877 virtual void setDescriptionString() = 0; 4878 4879 static const Builtin::Info BuiltinInfo[]; 4880 std::string CPU; 4881 bool IsMips16; 4882 bool IsMicromips; 4883 bool IsNan2008; 4884 bool IsSingleFloat; 4885 enum MipsFloatABI { 4886 HardFloat, SoftFloat 4887 } FloatABI; 4888 enum DspRevEnum { 4889 NoDSP, DSP1, DSP2 4890 } DspRev; 4891 bool HasMSA; 4892 4893 protected: 4894 bool HasFP64; 4895 std::string ABI; 4896 4897 public: 4898 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4899 const std::string &CPUStr) 4900 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4901 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4902 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4903 4904 virtual const char *getABI() const { return ABI.c_str(); } 4905 virtual bool setABI(const std::string &Name) = 0; 4906 virtual bool setCPU(const std::string &Name) { 4907 CPU = Name; 4908 return true; 4909 } 4910 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4911 // The backend enables certain ABI's by default according to the 4912 // architecture. 4913 // Disable both possible defaults so that we don't end up with multiple 4914 // ABI's selected and trigger an assertion. 4915 Features["o32"] = false; 4916 Features["n64"] = false; 4917 4918 Features[ABI] = true; 4919 Features[CPU] = true; 4920 } 4921 4922 virtual void getTargetDefines(const LangOptions &Opts, 4923 MacroBuilder &Builder) const { 4924 Builder.defineMacro("__mips__"); 4925 Builder.defineMacro("_mips"); 4926 if (Opts.GNUMode) 4927 Builder.defineMacro("mips"); 4928 4929 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4930 4931 switch (FloatABI) { 4932 case HardFloat: 4933 Builder.defineMacro("__mips_hard_float", Twine(1)); 4934 break; 4935 case SoftFloat: 4936 Builder.defineMacro("__mips_soft_float", Twine(1)); 4937 break; 4938 } 4939 4940 if (IsSingleFloat) 4941 Builder.defineMacro("__mips_single_float", Twine(1)); 4942 4943 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4944 Builder.defineMacro("_MIPS_FPSET", 4945 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4946 4947 if (IsMips16) 4948 Builder.defineMacro("__mips16", Twine(1)); 4949 4950 if (IsMicromips) 4951 Builder.defineMacro("__mips_micromips", Twine(1)); 4952 4953 if (IsNan2008) 4954 Builder.defineMacro("__mips_nan2008", Twine(1)); 4955 4956 switch (DspRev) { 4957 default: 4958 break; 4959 case DSP1: 4960 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4961 Builder.defineMacro("__mips_dsp", Twine(1)); 4962 break; 4963 case DSP2: 4964 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4965 Builder.defineMacro("__mips_dspr2", Twine(1)); 4966 Builder.defineMacro("__mips_dsp", Twine(1)); 4967 break; 4968 } 4969 4970 if (HasMSA) 4971 Builder.defineMacro("__mips_msa", Twine(1)); 4972 4973 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4974 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4975 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4976 4977 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4978 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4979 } 4980 4981 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4982 unsigned &NumRecords) const { 4983 Records = BuiltinInfo; 4984 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4985 } 4986 virtual bool hasFeature(StringRef Feature) const { 4987 return llvm::StringSwitch<bool>(Feature) 4988 .Case("mips", true) 4989 .Case("fp64", HasFP64) 4990 .Default(false); 4991 } 4992 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4993 return TargetInfo::VoidPtrBuiltinVaList; 4994 } 4995 virtual void getGCCRegNames(const char * const *&Names, 4996 unsigned &NumNames) const { 4997 static const char *const GCCRegNames[] = { 4998 // CPU register names 4999 // Must match second column of GCCRegAliases 5000 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5001 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5002 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5003 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5004 // Floating point register names 5005 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5006 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5007 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5008 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5009 // Hi/lo and condition register names 5010 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5011 "$fcc5","$fcc6","$fcc7", 5012 // MSA register names 5013 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5014 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5015 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5016 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5017 // MSA control register names 5018 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5019 "$msarequest", "$msamap", "$msaunmap" 5020 }; 5021 Names = GCCRegNames; 5022 NumNames = llvm::array_lengthof(GCCRegNames); 5023 } 5024 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5025 unsigned &NumAliases) const = 0; 5026 virtual bool validateAsmConstraint(const char *&Name, 5027 TargetInfo::ConstraintInfo &Info) const { 5028 switch (*Name) { 5029 default: 5030 return false; 5031 5032 case 'r': // CPU registers. 5033 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5034 case 'y': // Equivalent to "r", backwards compatibility only. 5035 case 'f': // floating-point registers. 5036 case 'c': // $25 for indirect jumps 5037 case 'l': // lo register 5038 case 'x': // hilo register pair 5039 Info.setAllowsRegister(); 5040 return true; 5041 case 'R': // An address that can be used in a non-macro load or store 5042 Info.setAllowsMemory(); 5043 return true; 5044 } 5045 } 5046 5047 virtual const char *getClobbers() const { 5048 // FIXME: Implement! 5049 return ""; 5050 } 5051 5052 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 5053 DiagnosticsEngine &Diags) { 5054 IsMips16 = false; 5055 IsMicromips = false; 5056 IsNan2008 = false; 5057 IsSingleFloat = false; 5058 FloatABI = HardFloat; 5059 DspRev = NoDSP; 5060 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5061 5062 for (std::vector<std::string>::iterator it = Features.begin(), 5063 ie = Features.end(); it != ie; ++it) { 5064 if (*it == "+single-float") 5065 IsSingleFloat = true; 5066 else if (*it == "+soft-float") 5067 FloatABI = SoftFloat; 5068 else if (*it == "+mips16") 5069 IsMips16 = true; 5070 else if (*it == "+micromips") 5071 IsMicromips = true; 5072 else if (*it == "+dsp") 5073 DspRev = std::max(DspRev, DSP1); 5074 else if (*it == "+dspr2") 5075 DspRev = std::max(DspRev, DSP2); 5076 else if (*it == "+msa") 5077 HasMSA = true; 5078 else if (*it == "+fp64") 5079 HasFP64 = true; 5080 else if (*it == "-fp64") 5081 HasFP64 = false; 5082 else if (*it == "+nan2008") 5083 IsNan2008 = true; 5084 } 5085 5086 // Remove front-end specific options. 5087 std::vector<std::string>::iterator it = 5088 std::find(Features.begin(), Features.end(), "+soft-float"); 5089 if (it != Features.end()) 5090 Features.erase(it); 5091 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5092 if (it != Features.end()) 5093 Features.erase(it); 5094 5095 setDescriptionString(); 5096 5097 return true; 5098 } 5099 5100 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5101 if (RegNo == 0) return 4; 5102 if (RegNo == 1) return 5; 5103 return -1; 5104 } 5105 }; 5106 5107 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5108 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5109 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5110 ALL_LANGUAGES }, 5111 #include "clang/Basic/BuiltinsMips.def" 5112 }; 5113 5114 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5115 public: 5116 Mips32TargetInfoBase(const llvm::Triple &Triple) 5117 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5118 SizeType = UnsignedInt; 5119 PtrDiffType = SignedInt; 5120 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5121 } 5122 virtual bool setABI(const std::string &Name) { 5123 if ((Name == "o32") || (Name == "eabi")) { 5124 ABI = Name; 5125 return true; 5126 } else if (Name == "32") { 5127 ABI = "o32"; 5128 return true; 5129 } else 5130 return false; 5131 } 5132 virtual void getTargetDefines(const LangOptions &Opts, 5133 MacroBuilder &Builder) const { 5134 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5135 5136 Builder.defineMacro("__mips", "32"); 5137 5138 if (ABI == "o32") { 5139 Builder.defineMacro("__mips_o32"); 5140 Builder.defineMacro("_ABIO32", "1"); 5141 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5142 } 5143 else if (ABI == "eabi") 5144 Builder.defineMacro("__mips_eabi"); 5145 else 5146 llvm_unreachable("Invalid ABI for Mips32."); 5147 } 5148 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5149 unsigned &NumAliases) const { 5150 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5151 { { "at" }, "$1" }, 5152 { { "v0" }, "$2" }, 5153 { { "v1" }, "$3" }, 5154 { { "a0" }, "$4" }, 5155 { { "a1" }, "$5" }, 5156 { { "a2" }, "$6" }, 5157 { { "a3" }, "$7" }, 5158 { { "t0" }, "$8" }, 5159 { { "t1" }, "$9" }, 5160 { { "t2" }, "$10" }, 5161 { { "t3" }, "$11" }, 5162 { { "t4" }, "$12" }, 5163 { { "t5" }, "$13" }, 5164 { { "t6" }, "$14" }, 5165 { { "t7" }, "$15" }, 5166 { { "s0" }, "$16" }, 5167 { { "s1" }, "$17" }, 5168 { { "s2" }, "$18" }, 5169 { { "s3" }, "$19" }, 5170 { { "s4" }, "$20" }, 5171 { { "s5" }, "$21" }, 5172 { { "s6" }, "$22" }, 5173 { { "s7" }, "$23" }, 5174 { { "t8" }, "$24" }, 5175 { { "t9" }, "$25" }, 5176 { { "k0" }, "$26" }, 5177 { { "k1" }, "$27" }, 5178 { { "gp" }, "$28" }, 5179 { { "sp","$sp" }, "$29" }, 5180 { { "fp","$fp" }, "$30" }, 5181 { { "ra" }, "$31" } 5182 }; 5183 Aliases = GCCRegAliases; 5184 NumAliases = llvm::array_lengthof(GCCRegAliases); 5185 } 5186 }; 5187 5188 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5189 virtual void setDescriptionString() { 5190 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5191 } 5192 5193 public: 5194 Mips32EBTargetInfo(const llvm::Triple &Triple) 5195 : Mips32TargetInfoBase(Triple) { 5196 } 5197 virtual void getTargetDefines(const LangOptions &Opts, 5198 MacroBuilder &Builder) const { 5199 DefineStd(Builder, "MIPSEB", Opts); 5200 Builder.defineMacro("_MIPSEB"); 5201 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5202 } 5203 }; 5204 5205 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5206 virtual void setDescriptionString() { 5207 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5208 } 5209 5210 public: 5211 Mips32ELTargetInfo(const llvm::Triple &Triple) 5212 : Mips32TargetInfoBase(Triple) { 5213 BigEndian = false; 5214 } 5215 virtual void getTargetDefines(const LangOptions &Opts, 5216 MacroBuilder &Builder) const { 5217 DefineStd(Builder, "MIPSEL", Opts); 5218 Builder.defineMacro("_MIPSEL"); 5219 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5220 } 5221 }; 5222 5223 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5224 public: 5225 Mips64TargetInfoBase(const llvm::Triple &Triple) 5226 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5227 LongWidth = LongAlign = 64; 5228 PointerWidth = PointerAlign = 64; 5229 LongDoubleWidth = LongDoubleAlign = 128; 5230 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5231 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5232 LongDoubleWidth = LongDoubleAlign = 64; 5233 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5234 } 5235 SuitableAlign = 128; 5236 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5237 } 5238 virtual bool setABI(const std::string &Name) { 5239 if (Name == "n32") { 5240 LongWidth = LongAlign = 32; 5241 PointerWidth = PointerAlign = 32; 5242 ABI = Name; 5243 return true; 5244 } else if (Name == "n64") { 5245 ABI = Name; 5246 return true; 5247 } else if (Name == "64") { 5248 ABI = "n64"; 5249 return true; 5250 } else 5251 return false; 5252 } 5253 virtual void getTargetDefines(const LangOptions &Opts, 5254 MacroBuilder &Builder) const { 5255 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5256 5257 Builder.defineMacro("__mips", "64"); 5258 Builder.defineMacro("__mips64"); 5259 Builder.defineMacro("__mips64__"); 5260 5261 if (ABI == "n32") { 5262 Builder.defineMacro("__mips_n32"); 5263 Builder.defineMacro("_ABIN32", "2"); 5264 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5265 } 5266 else if (ABI == "n64") { 5267 Builder.defineMacro("__mips_n64"); 5268 Builder.defineMacro("_ABI64", "3"); 5269 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5270 } 5271 else 5272 llvm_unreachable("Invalid ABI for Mips64."); 5273 } 5274 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5275 unsigned &NumAliases) const { 5276 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5277 { { "at" }, "$1" }, 5278 { { "v0" }, "$2" }, 5279 { { "v1" }, "$3" }, 5280 { { "a0" }, "$4" }, 5281 { { "a1" }, "$5" }, 5282 { { "a2" }, "$6" }, 5283 { { "a3" }, "$7" }, 5284 { { "a4" }, "$8" }, 5285 { { "a5" }, "$9" }, 5286 { { "a6" }, "$10" }, 5287 { { "a7" }, "$11" }, 5288 { { "t0" }, "$12" }, 5289 { { "t1" }, "$13" }, 5290 { { "t2" }, "$14" }, 5291 { { "t3" }, "$15" }, 5292 { { "s0" }, "$16" }, 5293 { { "s1" }, "$17" }, 5294 { { "s2" }, "$18" }, 5295 { { "s3" }, "$19" }, 5296 { { "s4" }, "$20" }, 5297 { { "s5" }, "$21" }, 5298 { { "s6" }, "$22" }, 5299 { { "s7" }, "$23" }, 5300 { { "t8" }, "$24" }, 5301 { { "t9" }, "$25" }, 5302 { { "k0" }, "$26" }, 5303 { { "k1" }, "$27" }, 5304 { { "gp" }, "$28" }, 5305 { { "sp","$sp" }, "$29" }, 5306 { { "fp","$fp" }, "$30" }, 5307 { { "ra" }, "$31" } 5308 }; 5309 Aliases = GCCRegAliases; 5310 NumAliases = llvm::array_lengthof(GCCRegAliases); 5311 } 5312 }; 5313 5314 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5315 virtual void setDescriptionString() { 5316 if (ABI == "n32") 5317 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5318 else 5319 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5320 5321 } 5322 5323 public: 5324 Mips64EBTargetInfo(const llvm::Triple &Triple) 5325 : Mips64TargetInfoBase(Triple) {} 5326 virtual void getTargetDefines(const LangOptions &Opts, 5327 MacroBuilder &Builder) const { 5328 DefineStd(Builder, "MIPSEB", Opts); 5329 Builder.defineMacro("_MIPSEB"); 5330 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5331 } 5332 }; 5333 5334 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5335 virtual void setDescriptionString() { 5336 if (ABI == "n32") 5337 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5338 else 5339 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5340 } 5341 public: 5342 Mips64ELTargetInfo(const llvm::Triple &Triple) 5343 : Mips64TargetInfoBase(Triple) { 5344 // Default ABI is n64. 5345 BigEndian = false; 5346 } 5347 virtual void getTargetDefines(const LangOptions &Opts, 5348 MacroBuilder &Builder) const { 5349 DefineStd(Builder, "MIPSEL", Opts); 5350 Builder.defineMacro("_MIPSEL"); 5351 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5352 } 5353 }; 5354 } // end anonymous namespace. 5355 5356 namespace { 5357 class PNaClTargetInfo : public TargetInfo { 5358 public: 5359 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5360 BigEndian = false; 5361 this->UserLabelPrefix = ""; 5362 this->LongAlign = 32; 5363 this->LongWidth = 32; 5364 this->PointerAlign = 32; 5365 this->PointerWidth = 32; 5366 this->IntMaxType = TargetInfo::SignedLongLong; 5367 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5368 this->Int64Type = TargetInfo::SignedLongLong; 5369 this->DoubleAlign = 64; 5370 this->LongDoubleWidth = 64; 5371 this->LongDoubleAlign = 64; 5372 this->SizeType = TargetInfo::UnsignedInt; 5373 this->PtrDiffType = TargetInfo::SignedInt; 5374 this->IntPtrType = TargetInfo::SignedInt; 5375 this->RegParmMax = 0; // Disallow regparm 5376 } 5377 5378 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5379 } 5380 virtual void getArchDefines(const LangOptions &Opts, 5381 MacroBuilder &Builder) const { 5382 Builder.defineMacro("__le32__"); 5383 Builder.defineMacro("__pnacl__"); 5384 } 5385 virtual void getTargetDefines(const LangOptions &Opts, 5386 MacroBuilder &Builder) const { 5387 Builder.defineMacro("__LITTLE_ENDIAN__"); 5388 getArchDefines(Opts, Builder); 5389 } 5390 virtual bool hasFeature(StringRef Feature) const { 5391 return Feature == "pnacl"; 5392 } 5393 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5394 unsigned &NumRecords) const { 5395 } 5396 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5397 return TargetInfo::PNaClABIBuiltinVaList; 5398 } 5399 virtual void getGCCRegNames(const char * const *&Names, 5400 unsigned &NumNames) const; 5401 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5402 unsigned &NumAliases) const; 5403 virtual bool validateAsmConstraint(const char *&Name, 5404 TargetInfo::ConstraintInfo &Info) const { 5405 return false; 5406 } 5407 5408 virtual const char *getClobbers() const { 5409 return ""; 5410 } 5411 }; 5412 5413 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5414 unsigned &NumNames) const { 5415 Names = NULL; 5416 NumNames = 0; 5417 } 5418 5419 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5420 unsigned &NumAliases) const { 5421 Aliases = NULL; 5422 NumAliases = 0; 5423 } 5424 } // end anonymous namespace. 5425 5426 namespace { 5427 static const unsigned SPIRAddrSpaceMap[] = { 5428 1, // opencl_global 5429 3, // opencl_local 5430 2, // opencl_constant 5431 0, // cuda_device 5432 0, // cuda_constant 5433 0 // cuda_shared 5434 }; 5435 class SPIRTargetInfo : public TargetInfo { 5436 public: 5437 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5438 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5439 "SPIR target must use unknown OS"); 5440 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5441 "SPIR target must use unknown environment type"); 5442 BigEndian = false; 5443 TLSSupported = false; 5444 LongWidth = LongAlign = 64; 5445 AddrSpaceMap = &SPIRAddrSpaceMap; 5446 UseAddrSpaceMapMangling = true; 5447 // Define available target features 5448 // These must be defined in sorted order! 5449 NoAsmVariants = true; 5450 } 5451 virtual void getTargetDefines(const LangOptions &Opts, 5452 MacroBuilder &Builder) const { 5453 DefineStd(Builder, "SPIR", Opts); 5454 } 5455 virtual bool hasFeature(StringRef Feature) const { 5456 return Feature == "spir"; 5457 } 5458 5459 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5460 unsigned &NumRecords) const {} 5461 virtual const char *getClobbers() const { 5462 return ""; 5463 } 5464 virtual void getGCCRegNames(const char * const *&Names, 5465 unsigned &NumNames) const {} 5466 virtual bool validateAsmConstraint(const char *&Name, 5467 TargetInfo::ConstraintInfo &info) const { 5468 return true; 5469 } 5470 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5471 unsigned &NumAliases) const {} 5472 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5473 return TargetInfo::VoidPtrBuiltinVaList; 5474 } 5475 }; 5476 5477 5478 class SPIR32TargetInfo : public SPIRTargetInfo { 5479 public: 5480 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5481 PointerWidth = PointerAlign = 32; 5482 SizeType = TargetInfo::UnsignedInt; 5483 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5484 DescriptionString 5485 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5486 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5487 } 5488 virtual void getTargetDefines(const LangOptions &Opts, 5489 MacroBuilder &Builder) const { 5490 DefineStd(Builder, "SPIR32", Opts); 5491 } 5492 }; 5493 5494 class SPIR64TargetInfo : public SPIRTargetInfo { 5495 public: 5496 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5497 PointerWidth = PointerAlign = 64; 5498 SizeType = TargetInfo::UnsignedLong; 5499 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5500 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5501 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5502 } 5503 virtual void getTargetDefines(const LangOptions &Opts, 5504 MacroBuilder &Builder) const { 5505 DefineStd(Builder, "SPIR64", Opts); 5506 } 5507 }; 5508 } 5509 5510 namespace { 5511 class XCoreTargetInfo : public TargetInfo { 5512 static const Builtin::Info BuiltinInfo[]; 5513 public: 5514 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5515 BigEndian = false; 5516 NoAsmVariants = true; 5517 LongLongAlign = 32; 5518 SuitableAlign = 32; 5519 DoubleAlign = LongDoubleAlign = 32; 5520 SizeType = UnsignedInt; 5521 PtrDiffType = SignedInt; 5522 IntPtrType = SignedInt; 5523 WCharType = UnsignedChar; 5524 WIntType = UnsignedInt; 5525 UseZeroLengthBitfieldAlignment = true; 5526 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5527 "-f64:32-a:0:32-n32"; 5528 } 5529 virtual void getTargetDefines(const LangOptions &Opts, 5530 MacroBuilder &Builder) const { 5531 Builder.defineMacro("__XS1B__"); 5532 } 5533 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5534 unsigned &NumRecords) const { 5535 Records = BuiltinInfo; 5536 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5537 } 5538 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5539 return TargetInfo::VoidPtrBuiltinVaList; 5540 } 5541 virtual const char *getClobbers() const { 5542 return ""; 5543 } 5544 virtual void getGCCRegNames(const char * const *&Names, 5545 unsigned &NumNames) const { 5546 static const char * const GCCRegNames[] = { 5547 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5548 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5549 }; 5550 Names = GCCRegNames; 5551 NumNames = llvm::array_lengthof(GCCRegNames); 5552 } 5553 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5554 unsigned &NumAliases) const { 5555 Aliases = NULL; 5556 NumAliases = 0; 5557 } 5558 virtual bool validateAsmConstraint(const char *&Name, 5559 TargetInfo::ConstraintInfo &Info) const { 5560 return false; 5561 } 5562 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5563 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5564 return (RegNo < 2)? RegNo : -1; 5565 } 5566 }; 5567 5568 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5569 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5570 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5571 ALL_LANGUAGES }, 5572 #include "clang/Basic/BuiltinsXCore.def" 5573 }; 5574 } // end anonymous namespace. 5575 5576 5577 //===----------------------------------------------------------------------===// 5578 // Driver code 5579 //===----------------------------------------------------------------------===// 5580 5581 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5582 llvm::Triple::OSType os = Triple.getOS(); 5583 5584 switch (Triple.getArch()) { 5585 default: 5586 return NULL; 5587 5588 case llvm::Triple::xcore: 5589 return new XCoreTargetInfo(Triple); 5590 5591 case llvm::Triple::hexagon: 5592 return new HexagonTargetInfo(Triple); 5593 5594 case llvm::Triple::aarch64: 5595 switch (os) { 5596 case llvm::Triple::Linux: 5597 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5598 case llvm::Triple::NetBSD: 5599 return new NetBSDTargetInfo<AArch64TargetInfo>(Triple); 5600 default: 5601 return new AArch64TargetInfo(Triple); 5602 } 5603 5604 case llvm::Triple::arm: 5605 case llvm::Triple::thumb: 5606 if (Triple.isOSBinFormatMachO()) 5607 return new DarwinARMTargetInfo(Triple); 5608 5609 switch (os) { 5610 case llvm::Triple::Linux: 5611 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5612 case llvm::Triple::FreeBSD: 5613 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5614 case llvm::Triple::NetBSD: 5615 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5616 case llvm::Triple::OpenBSD: 5617 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5618 case llvm::Triple::Bitrig: 5619 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5620 case llvm::Triple::RTEMS: 5621 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5622 case llvm::Triple::NaCl: 5623 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5624 default: 5625 return new ARMTargetInfo(Triple); 5626 } 5627 5628 case llvm::Triple::msp430: 5629 return new MSP430TargetInfo(Triple); 5630 5631 case llvm::Triple::mips: 5632 switch (os) { 5633 case llvm::Triple::Linux: 5634 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5635 case llvm::Triple::RTEMS: 5636 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5637 case llvm::Triple::FreeBSD: 5638 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5639 case llvm::Triple::NetBSD: 5640 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5641 default: 5642 return new Mips32EBTargetInfo(Triple); 5643 } 5644 5645 case llvm::Triple::mipsel: 5646 switch (os) { 5647 case llvm::Triple::Linux: 5648 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5649 case llvm::Triple::RTEMS: 5650 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5651 case llvm::Triple::FreeBSD: 5652 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5653 case llvm::Triple::NetBSD: 5654 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5655 case llvm::Triple::NaCl: 5656 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5657 default: 5658 return new Mips32ELTargetInfo(Triple); 5659 } 5660 5661 case llvm::Triple::mips64: 5662 switch (os) { 5663 case llvm::Triple::Linux: 5664 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5665 case llvm::Triple::RTEMS: 5666 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5667 case llvm::Triple::FreeBSD: 5668 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5669 case llvm::Triple::NetBSD: 5670 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5671 case llvm::Triple::OpenBSD: 5672 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5673 default: 5674 return new Mips64EBTargetInfo(Triple); 5675 } 5676 5677 case llvm::Triple::mips64el: 5678 switch (os) { 5679 case llvm::Triple::Linux: 5680 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5681 case llvm::Triple::RTEMS: 5682 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5683 case llvm::Triple::FreeBSD: 5684 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5685 case llvm::Triple::NetBSD: 5686 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5687 case llvm::Triple::OpenBSD: 5688 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5689 default: 5690 return new Mips64ELTargetInfo(Triple); 5691 } 5692 5693 case llvm::Triple::le32: 5694 switch (os) { 5695 case llvm::Triple::NaCl: 5696 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5697 default: 5698 return NULL; 5699 } 5700 5701 case llvm::Triple::ppc: 5702 if (Triple.isOSDarwin()) 5703 return new DarwinPPC32TargetInfo(Triple); 5704 switch (os) { 5705 case llvm::Triple::Linux: 5706 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5707 case llvm::Triple::FreeBSD: 5708 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5709 case llvm::Triple::NetBSD: 5710 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5711 case llvm::Triple::OpenBSD: 5712 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5713 case llvm::Triple::RTEMS: 5714 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5715 default: 5716 return new PPC32TargetInfo(Triple); 5717 } 5718 5719 case llvm::Triple::ppc64: 5720 if (Triple.isOSDarwin()) 5721 return new DarwinPPC64TargetInfo(Triple); 5722 switch (os) { 5723 case llvm::Triple::Linux: 5724 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5725 case llvm::Triple::Lv2: 5726 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5727 case llvm::Triple::FreeBSD: 5728 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5729 case llvm::Triple::NetBSD: 5730 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5731 default: 5732 return new PPC64TargetInfo(Triple); 5733 } 5734 5735 case llvm::Triple::ppc64le: 5736 switch (os) { 5737 case llvm::Triple::Linux: 5738 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5739 default: 5740 return new PPC64TargetInfo(Triple); 5741 } 5742 5743 case llvm::Triple::nvptx: 5744 return new NVPTX32TargetInfo(Triple); 5745 case llvm::Triple::nvptx64: 5746 return new NVPTX64TargetInfo(Triple); 5747 5748 case llvm::Triple::r600: 5749 return new R600TargetInfo(Triple); 5750 5751 case llvm::Triple::sparc: 5752 switch (os) { 5753 case llvm::Triple::Linux: 5754 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5755 case llvm::Triple::AuroraUX: 5756 return new AuroraUXSparcV8TargetInfo(Triple); 5757 case llvm::Triple::Solaris: 5758 return new SolarisSparcV8TargetInfo(Triple); 5759 case llvm::Triple::NetBSD: 5760 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5761 case llvm::Triple::OpenBSD: 5762 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5763 case llvm::Triple::RTEMS: 5764 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5765 default: 5766 return new SparcV8TargetInfo(Triple); 5767 } 5768 5769 case llvm::Triple::sparcv9: 5770 switch (os) { 5771 case llvm::Triple::Linux: 5772 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5773 case llvm::Triple::AuroraUX: 5774 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5775 case llvm::Triple::Solaris: 5776 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5777 case llvm::Triple::NetBSD: 5778 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5779 case llvm::Triple::OpenBSD: 5780 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5781 case llvm::Triple::FreeBSD: 5782 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5783 default: 5784 return new SparcV9TargetInfo(Triple); 5785 } 5786 5787 case llvm::Triple::systemz: 5788 switch (os) { 5789 case llvm::Triple::Linux: 5790 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5791 default: 5792 return new SystemZTargetInfo(Triple); 5793 } 5794 5795 case llvm::Triple::tce: 5796 return new TCETargetInfo(Triple); 5797 5798 case llvm::Triple::x86: 5799 if (Triple.isOSDarwin()) 5800 return new DarwinI386TargetInfo(Triple); 5801 5802 switch (os) { 5803 case llvm::Triple::AuroraUX: 5804 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5805 case llvm::Triple::Linux: 5806 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5807 case llvm::Triple::DragonFly: 5808 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5809 case llvm::Triple::NetBSD: 5810 return new NetBSDI386TargetInfo(Triple); 5811 case llvm::Triple::OpenBSD: 5812 return new OpenBSDI386TargetInfo(Triple); 5813 case llvm::Triple::Bitrig: 5814 return new BitrigI386TargetInfo(Triple); 5815 case llvm::Triple::FreeBSD: 5816 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5817 case llvm::Triple::KFreeBSD: 5818 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5819 case llvm::Triple::Minix: 5820 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5821 case llvm::Triple::Solaris: 5822 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5823 case llvm::Triple::Cygwin: 5824 return new CygwinX86_32TargetInfo(Triple); 5825 case llvm::Triple::MinGW32: 5826 return new MinGWX86_32TargetInfo(Triple); 5827 case llvm::Triple::Win32: 5828 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5829 case llvm::Triple::Haiku: 5830 return new HaikuX86_32TargetInfo(Triple); 5831 case llvm::Triple::RTEMS: 5832 return new RTEMSX86_32TargetInfo(Triple); 5833 case llvm::Triple::NaCl: 5834 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5835 default: 5836 return new X86_32TargetInfo(Triple); 5837 } 5838 5839 case llvm::Triple::x86_64: 5840 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5841 return new DarwinX86_64TargetInfo(Triple); 5842 5843 switch (os) { 5844 case llvm::Triple::AuroraUX: 5845 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5846 case llvm::Triple::Linux: 5847 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5848 case llvm::Triple::DragonFly: 5849 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5850 case llvm::Triple::NetBSD: 5851 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5852 case llvm::Triple::OpenBSD: 5853 return new OpenBSDX86_64TargetInfo(Triple); 5854 case llvm::Triple::Bitrig: 5855 return new BitrigX86_64TargetInfo(Triple); 5856 case llvm::Triple::FreeBSD: 5857 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5858 case llvm::Triple::KFreeBSD: 5859 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5860 case llvm::Triple::Solaris: 5861 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5862 case llvm::Triple::MinGW32: 5863 return new MinGWX86_64TargetInfo(Triple); 5864 case llvm::Triple::Win32: // This is what Triple.h supports now. 5865 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5866 case llvm::Triple::NaCl: 5867 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5868 default: 5869 return new X86_64TargetInfo(Triple); 5870 } 5871 5872 case llvm::Triple::spir: { 5873 if (Triple.getOS() != llvm::Triple::UnknownOS || 5874 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5875 return NULL; 5876 return new SPIR32TargetInfo(Triple); 5877 } 5878 case llvm::Triple::spir64: { 5879 if (Triple.getOS() != llvm::Triple::UnknownOS || 5880 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5881 return NULL; 5882 return new SPIR64TargetInfo(Triple); 5883 } 5884 } 5885 } 5886 5887 /// CreateTargetInfo - Return the target info object for the specified target 5888 /// triple. 5889 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5890 TargetOptions *Opts) { 5891 llvm::Triple Triple(Opts->Triple); 5892 5893 // Construct the target 5894 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5895 if (!Target) { 5896 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5897 return 0; 5898 } 5899 Target->setTargetOpts(Opts); 5900 5901 // Set the target CPU if specified. 5902 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5903 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5904 return 0; 5905 } 5906 5907 // Set the target ABI if specified. 5908 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5909 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5910 return 0; 5911 } 5912 5913 // Set the fp math unit. 5914 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5915 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5916 return 0; 5917 } 5918 5919 // Compute the default target features, we need the target to handle this 5920 // because features may have dependencies on one another. 5921 llvm::StringMap<bool> Features; 5922 Target->getDefaultFeatures(Features); 5923 5924 // Apply the user specified deltas. 5925 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5926 I < N; ++I) { 5927 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5928 // Apply the feature via the target. 5929 bool Enabled = Name[0] == '+'; 5930 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5931 } 5932 5933 // Add the features to the compile options. 5934 // 5935 // FIXME: If we are completely confident that we have the right set, we only 5936 // need to pass the minuses. 5937 Opts->Features.clear(); 5938 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5939 ie = Features.end(); it != ie; ++it) 5940 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5941 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5942 return 0; 5943 5944 return Target.take(); 5945 } 5946