1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 183 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 184 this->MCountName = "\01mcount"; 185 } 186 187 virtual std::string isValidSectionSpecifier(StringRef SR) const { 188 // Let MCSectionMachO validate this. 189 StringRef Segment, Section; 190 unsigned TAA, StubSize; 191 bool HasTAA; 192 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 193 TAA, HasTAA, StubSize); 194 } 195 196 virtual const char *getStaticInitSectionSpecifier() const { 197 // FIXME: We should return 0 when building kexts. 198 return "__TEXT,__StaticInit,regular,pure_instructions"; 199 } 200 201 /// Darwin does not support protected visibility. Darwin's "default" 202 /// is very similar to ELF's "protected"; Darwin requires a "weak" 203 /// attribute on declarations that can be dynamically replaced. 204 virtual bool hasProtectedVisibility() const { 205 return false; 206 } 207 }; 208 209 210 // DragonFlyBSD Target 211 template<typename Target> 212 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 213 protected: 214 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 215 MacroBuilder &Builder) const { 216 // DragonFly defines; list based off of gcc output 217 Builder.defineMacro("__DragonFly__"); 218 Builder.defineMacro("__DragonFly_cc_version", "100001"); 219 Builder.defineMacro("__ELF__"); 220 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 221 Builder.defineMacro("__tune_i386__"); 222 DefineStd(Builder, "unix", Opts); 223 } 224 public: 225 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 226 : OSTargetInfo<Target>(Triple) { 227 this->UserLabelPrefix = ""; 228 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 257 // On FreeBSD, wchar_t contains the number of the code point as 258 // used by the character set of the locale. These character sets are 259 // not necessarily a superset of ASCII. 260 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 261 } 262 public: 263 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 case llvm::Triple::ppc64le: 277 this->MCountName = "_mcount"; 278 break; 279 case llvm::Triple::arm: 280 this->MCountName = "__mcount"; 281 break; 282 } 283 } 284 }; 285 286 // GNU/kFreeBSD Target 287 template<typename Target> 288 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 289 protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // GNU/kFreeBSD defines; list based off of gcc output 293 294 DefineStd(Builder, "unix", Opts); 295 Builder.defineMacro("__FreeBSD_kernel__"); 296 Builder.defineMacro("__GLIBC__"); 297 Builder.defineMacro("__ELF__"); 298 if (Opts.POSIXThreads) 299 Builder.defineMacro("_REENTRANT"); 300 if (Opts.CPlusPlus) 301 Builder.defineMacro("_GNU_SOURCE"); 302 } 303 public: 304 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 305 this->UserLabelPrefix = ""; 306 } 307 }; 308 309 // Minix Target 310 template<typename Target> 311 class MinixTargetInfo : public OSTargetInfo<Target> { 312 protected: 313 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 314 MacroBuilder &Builder) const { 315 // Minix defines 316 317 Builder.defineMacro("__minix", "3"); 318 Builder.defineMacro("_EM_WSIZE", "4"); 319 Builder.defineMacro("_EM_PSIZE", "4"); 320 Builder.defineMacro("_EM_SSIZE", "2"); 321 Builder.defineMacro("_EM_LSIZE", "4"); 322 Builder.defineMacro("_EM_FSIZE", "4"); 323 Builder.defineMacro("_EM_DSIZE", "8"); 324 Builder.defineMacro("__ELF__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 329 this->UserLabelPrefix = ""; 330 } 331 }; 332 333 // Linux target 334 template<typename Target> 335 class LinuxTargetInfo : public OSTargetInfo<Target> { 336 protected: 337 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 338 MacroBuilder &Builder) const { 339 // Linux defines; list based off of gcc output 340 DefineStd(Builder, "unix", Opts); 341 DefineStd(Builder, "linux", Opts); 342 Builder.defineMacro("__gnu_linux__"); 343 Builder.defineMacro("__ELF__"); 344 if (Triple.getEnvironment() == llvm::Triple::Android) 345 Builder.defineMacro("__ANDROID__", "1"); 346 if (Opts.POSIXThreads) 347 Builder.defineMacro("_REENTRANT"); 348 if (Opts.CPlusPlus) 349 Builder.defineMacro("_GNU_SOURCE"); 350 } 351 public: 352 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 353 this->UserLabelPrefix = ""; 354 this->WIntType = TargetInfo::UnsignedInt; 355 } 356 357 virtual const char *getStaticInitSectionSpecifier() const { 358 return ".text.startup"; 359 } 360 }; 361 362 // NetBSD Target 363 template<typename Target> 364 class NetBSDTargetInfo : public OSTargetInfo<Target> { 365 protected: 366 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 367 MacroBuilder &Builder) const { 368 // NetBSD defines; list based off of gcc output 369 Builder.defineMacro("__NetBSD__"); 370 Builder.defineMacro("__unix__"); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_POSIX_THREADS"); 374 } 375 public: 376 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 377 this->UserLabelPrefix = ""; 378 } 379 }; 380 381 // OpenBSD Target 382 template<typename Target> 383 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 384 protected: 385 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 386 MacroBuilder &Builder) const { 387 // OpenBSD defines; list based off of gcc output 388 389 Builder.defineMacro("__OpenBSD__"); 390 DefineStd(Builder, "unix", Opts); 391 Builder.defineMacro("__ELF__"); 392 if (Opts.POSIXThreads) 393 Builder.defineMacro("_REENTRANT"); 394 } 395 public: 396 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 397 this->UserLabelPrefix = ""; 398 this->TLSSupported = false; 399 400 switch (Triple.getArch()) { 401 default: 402 case llvm::Triple::x86: 403 case llvm::Triple::x86_64: 404 case llvm::Triple::arm: 405 case llvm::Triple::sparc: 406 this->MCountName = "__mcount"; 407 break; 408 case llvm::Triple::mips64: 409 case llvm::Triple::mips64el: 410 case llvm::Triple::ppc: 411 case llvm::Triple::sparcv9: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 }; 417 418 // Bitrig Target 419 template<typename Target> 420 class BitrigTargetInfo : public OSTargetInfo<Target> { 421 protected: 422 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 423 MacroBuilder &Builder) const { 424 // Bitrig defines; list based off of gcc output 425 426 Builder.defineMacro("__Bitrig__"); 427 DefineStd(Builder, "unix", Opts); 428 Builder.defineMacro("__ELF__"); 429 if (Opts.POSIXThreads) 430 Builder.defineMacro("_REENTRANT"); 431 } 432 public: 433 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 434 this->UserLabelPrefix = ""; 435 this->TLSSupported = false; 436 this->MCountName = "__mcount"; 437 } 438 }; 439 440 // PSP Target 441 template<typename Target> 442 class PSPTargetInfo : public OSTargetInfo<Target> { 443 protected: 444 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 445 MacroBuilder &Builder) const { 446 // PSP defines; list based on the output of the pspdev gcc toolchain. 447 Builder.defineMacro("PSP"); 448 Builder.defineMacro("_PSP"); 449 Builder.defineMacro("__psp__"); 450 Builder.defineMacro("__ELF__"); 451 } 452 public: 453 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 454 this->UserLabelPrefix = ""; 455 } 456 }; 457 458 // PS3 PPU Target 459 template<typename Target> 460 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 461 protected: 462 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 463 MacroBuilder &Builder) const { 464 // PS3 PPU defines. 465 Builder.defineMacro("__PPC__"); 466 Builder.defineMacro("__PPU__"); 467 Builder.defineMacro("__CELLOS_LV2__"); 468 Builder.defineMacro("__ELF__"); 469 Builder.defineMacro("__LP32__"); 470 Builder.defineMacro("_ARCH_PPC64"); 471 Builder.defineMacro("__powerpc64__"); 472 } 473 public: 474 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 475 this->UserLabelPrefix = ""; 476 this->LongWidth = this->LongAlign = 32; 477 this->PointerWidth = this->PointerAlign = 32; 478 this->IntMaxType = TargetInfo::SignedLongLong; 479 this->UIntMaxType = TargetInfo::UnsignedLongLong; 480 this->Int64Type = TargetInfo::SignedLongLong; 481 this->SizeType = TargetInfo::UnsignedInt; 482 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 483 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 484 } 485 }; 486 487 // FIXME: Need a real SPU target. 488 // PS3 SPU Target 489 template<typename Target> 490 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 491 protected: 492 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 493 MacroBuilder &Builder) const { 494 // PS3 PPU defines. 495 Builder.defineMacro("__SPU__"); 496 Builder.defineMacro("__ELF__"); 497 } 498 public: 499 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 500 this->UserLabelPrefix = ""; 501 } 502 }; 503 504 // AuroraUX target 505 template<typename Target> 506 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const { 510 DefineStd(Builder, "sun", Opts); 511 DefineStd(Builder, "unix", Opts); 512 Builder.defineMacro("__ELF__"); 513 Builder.defineMacro("__svr4__"); 514 Builder.defineMacro("__SVR4"); 515 } 516 public: 517 AuroraUXTargetInfo(const llvm::Triple &Triple) 518 : OSTargetInfo<Target>(Triple) { 519 this->UserLabelPrefix = ""; 520 this->WCharType = this->SignedLong; 521 // FIXME: WIntType should be SignedLong 522 } 523 }; 524 525 // Solaris target 526 template<typename Target> 527 class SolarisTargetInfo : public OSTargetInfo<Target> { 528 protected: 529 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 530 MacroBuilder &Builder) const { 531 DefineStd(Builder, "sun", Opts); 532 DefineStd(Builder, "unix", Opts); 533 Builder.defineMacro("__ELF__"); 534 Builder.defineMacro("__svr4__"); 535 Builder.defineMacro("__SVR4"); 536 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 537 // newer, but to 500 for everything else. feature_test.h has a check to 538 // ensure that you are not using C99 with an old version of X/Open or C89 539 // with a new version. 540 if (Opts.C99 || Opts.C11) 541 Builder.defineMacro("_XOPEN_SOURCE", "600"); 542 else 543 Builder.defineMacro("_XOPEN_SOURCE", "500"); 544 if (Opts.CPlusPlus) 545 Builder.defineMacro("__C99FEATURES__"); 546 Builder.defineMacro("_LARGEFILE_SOURCE"); 547 Builder.defineMacro("_LARGEFILE64_SOURCE"); 548 Builder.defineMacro("__EXTENSIONS__"); 549 Builder.defineMacro("_REENTRANT"); 550 } 551 public: 552 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 553 this->UserLabelPrefix = ""; 554 this->WCharType = this->SignedInt; 555 // FIXME: WIntType should be SignedLong 556 } 557 }; 558 559 // Windows target 560 template<typename Target> 561 class WindowsTargetInfo : public OSTargetInfo<Target> { 562 protected: 563 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 564 MacroBuilder &Builder) const { 565 Builder.defineMacro("_WIN32"); 566 } 567 void getVisualStudioDefines(const LangOptions &Opts, 568 MacroBuilder &Builder) const { 569 if (Opts.CPlusPlus) { 570 if (Opts.RTTI) 571 Builder.defineMacro("_CPPRTTI"); 572 573 if (Opts.Exceptions) 574 Builder.defineMacro("_CPPUNWIND"); 575 } 576 577 if (!Opts.CharIsSigned) 578 Builder.defineMacro("_CHAR_UNSIGNED"); 579 580 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 581 // but it works for now. 582 if (Opts.POSIXThreads) 583 Builder.defineMacro("_MT"); 584 585 if (Opts.MSCVersion != 0) 586 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 587 588 if (Opts.MicrosoftExt) { 589 Builder.defineMacro("_MSC_EXTENSIONS"); 590 591 if (Opts.CPlusPlus11) { 592 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 593 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 594 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 595 } 596 } 597 598 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 599 } 600 601 public: 602 WindowsTargetInfo(const llvm::Triple &Triple) 603 : OSTargetInfo<Target>(Triple) {} 604 }; 605 606 template <typename Target> 607 class NaClTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const { 611 if (Opts.POSIXThreads) 612 Builder.defineMacro("_REENTRANT"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("_GNU_SOURCE"); 615 616 DefineStd(Builder, "unix", Opts); 617 Builder.defineMacro("__ELF__"); 618 Builder.defineMacro("__native_client__"); 619 } 620 621 public: 622 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 623 this->UserLabelPrefix = ""; 624 this->LongAlign = 32; 625 this->LongWidth = 32; 626 this->PointerAlign = 32; 627 this->PointerWidth = 32; 628 this->IntMaxType = TargetInfo::SignedLongLong; 629 this->UIntMaxType = TargetInfo::UnsignedLongLong; 630 this->Int64Type = TargetInfo::SignedLongLong; 631 this->DoubleAlign = 64; 632 this->LongDoubleWidth = 64; 633 this->LongDoubleAlign = 64; 634 this->SizeType = TargetInfo::UnsignedInt; 635 this->PtrDiffType = TargetInfo::SignedInt; 636 this->IntPtrType = TargetInfo::SignedInt; 637 // RegParmMax is inherited from the underlying architecture 638 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 639 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 640 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 641 } 642 virtual typename Target::CallingConvCheckResult checkCallingConvention( 643 CallingConv CC) const { 644 return CC == CC_PnaclCall ? Target::CCCR_OK : 645 Target::checkCallingConvention(CC); 646 } 647 }; 648 } // end anonymous namespace. 649 650 //===----------------------------------------------------------------------===// 651 // Specific target implementations. 652 //===----------------------------------------------------------------------===// 653 654 namespace { 655 // PPC abstract base class 656 class PPCTargetInfo : public TargetInfo { 657 static const Builtin::Info BuiltinInfo[]; 658 static const char * const GCCRegNames[]; 659 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 660 std::string CPU; 661 662 // Target cpu features. 663 bool HasVSX; 664 665 public: 666 PPCTargetInfo(const llvm::Triple &Triple) 667 : TargetInfo(Triple), HasVSX(false) { 668 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 669 LongDoubleWidth = LongDoubleAlign = 128; 670 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 671 } 672 673 /// \brief Flags for architecture specific defines. 674 typedef enum { 675 ArchDefineNone = 0, 676 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 677 ArchDefinePpcgr = 1 << 1, 678 ArchDefinePpcsq = 1 << 2, 679 ArchDefine440 = 1 << 3, 680 ArchDefine603 = 1 << 4, 681 ArchDefine604 = 1 << 5, 682 ArchDefinePwr4 = 1 << 6, 683 ArchDefinePwr5 = 1 << 7, 684 ArchDefinePwr5x = 1 << 8, 685 ArchDefinePwr6 = 1 << 9, 686 ArchDefinePwr6x = 1 << 10, 687 ArchDefinePwr7 = 1 << 11, 688 ArchDefineA2 = 1 << 12, 689 ArchDefineA2q = 1 << 13 690 } ArchDefineTypes; 691 692 // Note: GCC recognizes the following additional cpus: 693 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 694 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 695 // titan, rs64. 696 virtual bool setCPU(const std::string &Name) { 697 bool CPUKnown = llvm::StringSwitch<bool>(Name) 698 .Case("generic", true) 699 .Case("440", true) 700 .Case("450", true) 701 .Case("601", true) 702 .Case("602", true) 703 .Case("603", true) 704 .Case("603e", true) 705 .Case("603ev", true) 706 .Case("604", true) 707 .Case("604e", true) 708 .Case("620", true) 709 .Case("630", true) 710 .Case("g3", true) 711 .Case("7400", true) 712 .Case("g4", true) 713 .Case("7450", true) 714 .Case("g4+", true) 715 .Case("750", true) 716 .Case("970", true) 717 .Case("g5", true) 718 .Case("a2", true) 719 .Case("a2q", true) 720 .Case("e500mc", true) 721 .Case("e5500", true) 722 .Case("power3", true) 723 .Case("pwr3", true) 724 .Case("power4", true) 725 .Case("pwr4", true) 726 .Case("power5", true) 727 .Case("pwr5", true) 728 .Case("power5x", true) 729 .Case("pwr5x", true) 730 .Case("power6", true) 731 .Case("pwr6", true) 732 .Case("power6x", true) 733 .Case("pwr6x", true) 734 .Case("power7", true) 735 .Case("pwr7", true) 736 .Case("powerpc", true) 737 .Case("ppc", true) 738 .Case("powerpc64", true) 739 .Case("ppc64", true) 740 .Case("powerpc64le", true) 741 .Case("ppc64le", true) 742 .Default(false); 743 744 if (CPUKnown) 745 CPU = Name; 746 747 return CPUKnown; 748 } 749 750 virtual void getTargetBuiltins(const Builtin::Info *&Records, 751 unsigned &NumRecords) const { 752 Records = BuiltinInfo; 753 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 754 } 755 756 virtual bool isCLZForZeroUndef() const { return false; } 757 758 virtual void getTargetDefines(const LangOptions &Opts, 759 MacroBuilder &Builder) const; 760 761 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 762 763 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 764 DiagnosticsEngine &Diags); 765 virtual bool hasFeature(StringRef Feature) const; 766 767 virtual void getGCCRegNames(const char * const *&Names, 768 unsigned &NumNames) const; 769 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 770 unsigned &NumAliases) const; 771 virtual bool validateAsmConstraint(const char *&Name, 772 TargetInfo::ConstraintInfo &Info) const { 773 switch (*Name) { 774 default: return false; 775 case 'O': // Zero 776 break; 777 case 'b': // Base register 778 case 'f': // Floating point register 779 Info.setAllowsRegister(); 780 break; 781 // FIXME: The following are added to allow parsing. 782 // I just took a guess at what the actions should be. 783 // Also, is more specific checking needed? I.e. specific registers? 784 case 'd': // Floating point register (containing 64-bit value) 785 case 'v': // Altivec vector register 786 Info.setAllowsRegister(); 787 break; 788 case 'w': 789 switch (Name[1]) { 790 case 'd':// VSX vector register to hold vector double data 791 case 'f':// VSX vector register to hold vector float data 792 case 's':// VSX vector register to hold scalar float data 793 case 'a':// Any VSX register 794 break; 795 default: 796 return false; 797 } 798 Info.setAllowsRegister(); 799 Name++; // Skip over 'w'. 800 break; 801 case 'h': // `MQ', `CTR', or `LINK' register 802 case 'q': // `MQ' register 803 case 'c': // `CTR' register 804 case 'l': // `LINK' register 805 case 'x': // `CR' register (condition register) number 0 806 case 'y': // `CR' register (condition register) 807 case 'z': // `XER[CA]' carry bit (part of the XER register) 808 Info.setAllowsRegister(); 809 break; 810 case 'I': // Signed 16-bit constant 811 case 'J': // Unsigned 16-bit constant shifted left 16 bits 812 // (use `L' instead for SImode constants) 813 case 'K': // Unsigned 16-bit constant 814 case 'L': // Signed 16-bit constant shifted left 16 bits 815 case 'M': // Constant larger than 31 816 case 'N': // Exact power of 2 817 case 'P': // Constant whose negation is a signed 16-bit constant 818 case 'G': // Floating point constant that can be loaded into a 819 // register with one instruction per word 820 case 'H': // Integer/Floating point constant that can be loaded 821 // into a register using three instructions 822 break; 823 case 'm': // Memory operand. Note that on PowerPC targets, m can 824 // include addresses that update the base register. It 825 // is therefore only safe to use `m' in an asm statement 826 // if that asm statement accesses the operand exactly once. 827 // The asm statement must also use `%U<opno>' as a 828 // placeholder for the "update" flag in the corresponding 829 // load or store instruction. For example: 830 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 831 // is correct but: 832 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 833 // is not. Use es rather than m if you don't want the base 834 // register to be updated. 835 case 'e': 836 if (Name[1] != 's') 837 return false; 838 // es: A "stable" memory operand; that is, one which does not 839 // include any automodification of the base register. Unlike 840 // `m', this constraint can be used in asm statements that 841 // might access the operand several times, or that might not 842 // access it at all. 843 Info.setAllowsMemory(); 844 Name++; // Skip over 'e'. 845 break; 846 case 'Q': // Memory operand that is an offset from a register (it is 847 // usually better to use `m' or `es' in asm statements) 848 case 'Z': // Memory operand that is an indexed or indirect from a 849 // register (it is usually better to use `m' or `es' in 850 // asm statements) 851 Info.setAllowsMemory(); 852 Info.setAllowsRegister(); 853 break; 854 case 'R': // AIX TOC entry 855 case 'a': // Address operand that is an indexed or indirect from a 856 // register (`p' is preferable for asm statements) 857 case 'S': // Constant suitable as a 64-bit mask operand 858 case 'T': // Constant suitable as a 32-bit mask operand 859 case 'U': // System V Release 4 small data area reference 860 case 't': // AND masks that can be performed by two rldic{l, r} 861 // instructions 862 case 'W': // Vector constant that does not require memory 863 case 'j': // Vector constant that is all zeros. 864 break; 865 // End FIXME. 866 } 867 return true; 868 } 869 virtual const char *getClobbers() const { 870 return ""; 871 } 872 int getEHDataRegisterNumber(unsigned RegNo) const { 873 if (RegNo == 0) return 3; 874 if (RegNo == 1) return 4; 875 return -1; 876 } 877 }; 878 879 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 880 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 881 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 882 ALL_LANGUAGES }, 883 #include "clang/Basic/BuiltinsPPC.def" 884 }; 885 886 /// handleTargetFeatures - Perform initialization based on the user 887 /// configured set of features. 888 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 889 DiagnosticsEngine &Diags) { 890 // Remember the maximum enabled sselevel. 891 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 892 // Ignore disabled features. 893 if (Features[i][0] == '-') 894 continue; 895 896 StringRef Feature = StringRef(Features[i]).substr(1); 897 898 if (Feature == "vsx") { 899 HasVSX = true; 900 continue; 901 } 902 903 // TODO: Finish this list and add an assert that we've handled them 904 // all. 905 } 906 907 return true; 908 } 909 910 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 911 /// #defines that are not tied to a specific subtarget. 912 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 913 MacroBuilder &Builder) const { 914 // Target identification. 915 Builder.defineMacro("__ppc__"); 916 Builder.defineMacro("__PPC__"); 917 Builder.defineMacro("_ARCH_PPC"); 918 Builder.defineMacro("__powerpc__"); 919 Builder.defineMacro("__POWERPC__"); 920 if (PointerWidth == 64) { 921 Builder.defineMacro("_ARCH_PPC64"); 922 Builder.defineMacro("__powerpc64__"); 923 Builder.defineMacro("__ppc64__"); 924 Builder.defineMacro("__PPC64__"); 925 } 926 927 // Target properties. 928 if (getTriple().getArch() == llvm::Triple::ppc64le) { 929 Builder.defineMacro("_LITTLE_ENDIAN"); 930 Builder.defineMacro("__LITTLE_ENDIAN__"); 931 } else { 932 if (getTriple().getOS() != llvm::Triple::NetBSD && 933 getTriple().getOS() != llvm::Triple::OpenBSD) 934 Builder.defineMacro("_BIG_ENDIAN"); 935 Builder.defineMacro("__BIG_ENDIAN__"); 936 } 937 938 // Subtarget options. 939 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 940 Builder.defineMacro("__REGISTER_PREFIX__", ""); 941 942 // FIXME: Should be controlled by command line option. 943 if (LongDoubleWidth == 128) 944 Builder.defineMacro("__LONG_DOUBLE_128__"); 945 946 if (Opts.AltiVec) { 947 Builder.defineMacro("__VEC__", "10206"); 948 Builder.defineMacro("__ALTIVEC__"); 949 } 950 951 // CPU identification. 952 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 953 .Case("440", ArchDefineName) 954 .Case("450", ArchDefineName | ArchDefine440) 955 .Case("601", ArchDefineName) 956 .Case("602", ArchDefineName | ArchDefinePpcgr) 957 .Case("603", ArchDefineName | ArchDefinePpcgr) 958 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 959 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 960 .Case("604", ArchDefineName | ArchDefinePpcgr) 961 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 962 .Case("620", ArchDefineName | ArchDefinePpcgr) 963 .Case("630", ArchDefineName | ArchDefinePpcgr) 964 .Case("7400", ArchDefineName | ArchDefinePpcgr) 965 .Case("7450", ArchDefineName | ArchDefinePpcgr) 966 .Case("750", ArchDefineName | ArchDefinePpcgr) 967 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 968 | ArchDefinePpcsq) 969 .Case("a2", ArchDefineA2) 970 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 971 .Case("pwr3", ArchDefinePpcgr) 972 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 973 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 974 | ArchDefinePpcsq) 975 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 976 | ArchDefinePpcgr | ArchDefinePpcsq) 977 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 978 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 979 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 980 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 981 | ArchDefinePpcsq) 982 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 983 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 984 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 985 .Case("power3", ArchDefinePpcgr) 986 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 987 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 988 | ArchDefinePpcsq) 989 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 990 | ArchDefinePpcgr | ArchDefinePpcsq) 991 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 992 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 993 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 994 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 995 | ArchDefinePpcsq) 996 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 997 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 998 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 999 .Default(ArchDefineNone); 1000 1001 if (defs & ArchDefineName) 1002 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1003 if (defs & ArchDefinePpcgr) 1004 Builder.defineMacro("_ARCH_PPCGR"); 1005 if (defs & ArchDefinePpcsq) 1006 Builder.defineMacro("_ARCH_PPCSQ"); 1007 if (defs & ArchDefine440) 1008 Builder.defineMacro("_ARCH_440"); 1009 if (defs & ArchDefine603) 1010 Builder.defineMacro("_ARCH_603"); 1011 if (defs & ArchDefine604) 1012 Builder.defineMacro("_ARCH_604"); 1013 if (defs & ArchDefinePwr4) 1014 Builder.defineMacro("_ARCH_PWR4"); 1015 if (defs & ArchDefinePwr5) 1016 Builder.defineMacro("_ARCH_PWR5"); 1017 if (defs & ArchDefinePwr5x) 1018 Builder.defineMacro("_ARCH_PWR5X"); 1019 if (defs & ArchDefinePwr6) 1020 Builder.defineMacro("_ARCH_PWR6"); 1021 if (defs & ArchDefinePwr6x) 1022 Builder.defineMacro("_ARCH_PWR6X"); 1023 if (defs & ArchDefinePwr7) 1024 Builder.defineMacro("_ARCH_PWR7"); 1025 if (defs & ArchDefineA2) 1026 Builder.defineMacro("_ARCH_A2"); 1027 if (defs & ArchDefineA2q) { 1028 Builder.defineMacro("_ARCH_A2Q"); 1029 Builder.defineMacro("_ARCH_QP"); 1030 } 1031 1032 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1033 Builder.defineMacro("__bg__"); 1034 Builder.defineMacro("__THW_BLUEGENE__"); 1035 Builder.defineMacro("__bgq__"); 1036 Builder.defineMacro("__TOS_BGQ__"); 1037 } 1038 1039 if (HasVSX) 1040 Builder.defineMacro("__VSX__"); 1041 1042 // FIXME: The following are not yet generated here by Clang, but are 1043 // generated by GCC: 1044 // 1045 // _SOFT_FLOAT_ 1046 // __RECIP_PRECISION__ 1047 // __APPLE_ALTIVEC__ 1048 // __RECIP__ 1049 // __RECIPF__ 1050 // __RSQRTE__ 1051 // __RSQRTEF__ 1052 // _SOFT_DOUBLE_ 1053 // __NO_LWSYNC__ 1054 // __HAVE_BSWAP__ 1055 // __LONGDOUBLE128 1056 // __CMODEL_MEDIUM__ 1057 // __CMODEL_LARGE__ 1058 // _CALL_SYSV 1059 // _CALL_DARWIN 1060 // __NO_FPRS__ 1061 } 1062 1063 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1064 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1065 .Case("7400", true) 1066 .Case("g4", true) 1067 .Case("7450", true) 1068 .Case("g4+", true) 1069 .Case("970", true) 1070 .Case("g5", true) 1071 .Case("pwr6", true) 1072 .Case("pwr7", true) 1073 .Case("ppc64", true) 1074 .Case("ppc64le", true) 1075 .Default(false); 1076 1077 Features["qpx"] = (CPU == "a2q"); 1078 } 1079 1080 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1081 return Feature == "powerpc"; 1082 } 1083 1084 1085 const char * const PPCTargetInfo::GCCRegNames[] = { 1086 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1087 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1088 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1089 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1090 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1091 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1092 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1093 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1094 "mq", "lr", "ctr", "ap", 1095 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1096 "xer", 1097 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1098 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1099 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1100 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1101 "vrsave", "vscr", 1102 "spe_acc", "spefscr", 1103 "sfp" 1104 }; 1105 1106 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1107 unsigned &NumNames) const { 1108 Names = GCCRegNames; 1109 NumNames = llvm::array_lengthof(GCCRegNames); 1110 } 1111 1112 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1113 // While some of these aliases do map to different registers 1114 // they still share the same register name. 1115 { { "0" }, "r0" }, 1116 { { "1"}, "r1" }, 1117 { { "2" }, "r2" }, 1118 { { "3" }, "r3" }, 1119 { { "4" }, "r4" }, 1120 { { "5" }, "r5" }, 1121 { { "6" }, "r6" }, 1122 { { "7" }, "r7" }, 1123 { { "8" }, "r8" }, 1124 { { "9" }, "r9" }, 1125 { { "10" }, "r10" }, 1126 { { "11" }, "r11" }, 1127 { { "12" }, "r12" }, 1128 { { "13" }, "r13" }, 1129 { { "14" }, "r14" }, 1130 { { "15" }, "r15" }, 1131 { { "16" }, "r16" }, 1132 { { "17" }, "r17" }, 1133 { { "18" }, "r18" }, 1134 { { "19" }, "r19" }, 1135 { { "20" }, "r20" }, 1136 { { "21" }, "r21" }, 1137 { { "22" }, "r22" }, 1138 { { "23" }, "r23" }, 1139 { { "24" }, "r24" }, 1140 { { "25" }, "r25" }, 1141 { { "26" }, "r26" }, 1142 { { "27" }, "r27" }, 1143 { { "28" }, "r28" }, 1144 { { "29" }, "r29" }, 1145 { { "30" }, "r30" }, 1146 { { "31" }, "r31" }, 1147 { { "fr0" }, "f0" }, 1148 { { "fr1" }, "f1" }, 1149 { { "fr2" }, "f2" }, 1150 { { "fr3" }, "f3" }, 1151 { { "fr4" }, "f4" }, 1152 { { "fr5" }, "f5" }, 1153 { { "fr6" }, "f6" }, 1154 { { "fr7" }, "f7" }, 1155 { { "fr8" }, "f8" }, 1156 { { "fr9" }, "f9" }, 1157 { { "fr10" }, "f10" }, 1158 { { "fr11" }, "f11" }, 1159 { { "fr12" }, "f12" }, 1160 { { "fr13" }, "f13" }, 1161 { { "fr14" }, "f14" }, 1162 { { "fr15" }, "f15" }, 1163 { { "fr16" }, "f16" }, 1164 { { "fr17" }, "f17" }, 1165 { { "fr18" }, "f18" }, 1166 { { "fr19" }, "f19" }, 1167 { { "fr20" }, "f20" }, 1168 { { "fr21" }, "f21" }, 1169 { { "fr22" }, "f22" }, 1170 { { "fr23" }, "f23" }, 1171 { { "fr24" }, "f24" }, 1172 { { "fr25" }, "f25" }, 1173 { { "fr26" }, "f26" }, 1174 { { "fr27" }, "f27" }, 1175 { { "fr28" }, "f28" }, 1176 { { "fr29" }, "f29" }, 1177 { { "fr30" }, "f30" }, 1178 { { "fr31" }, "f31" }, 1179 { { "cc" }, "cr0" }, 1180 }; 1181 1182 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1183 unsigned &NumAliases) const { 1184 Aliases = GCCRegAliases; 1185 NumAliases = llvm::array_lengthof(GCCRegAliases); 1186 } 1187 } // end anonymous namespace. 1188 1189 namespace { 1190 class PPC32TargetInfo : public PPCTargetInfo { 1191 public: 1192 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1193 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1194 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1195 1196 switch (getTriple().getOS()) { 1197 case llvm::Triple::Linux: 1198 case llvm::Triple::FreeBSD: 1199 case llvm::Triple::NetBSD: 1200 SizeType = UnsignedInt; 1201 PtrDiffType = SignedInt; 1202 IntPtrType = SignedInt; 1203 break; 1204 default: 1205 break; 1206 } 1207 1208 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1209 LongDoubleWidth = LongDoubleAlign = 64; 1210 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1211 } 1212 1213 // PPC32 supports atomics up to 4 bytes. 1214 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1215 } 1216 1217 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1218 // This is the ELF definition, and is overridden by the Darwin sub-target 1219 return TargetInfo::PowerABIBuiltinVaList; 1220 } 1221 }; 1222 } // end anonymous namespace. 1223 1224 // Note: ABI differences may eventually require us to have a separate 1225 // TargetInfo for little endian. 1226 namespace { 1227 class PPC64TargetInfo : public PPCTargetInfo { 1228 public: 1229 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1230 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1231 IntMaxType = SignedLong; 1232 UIntMaxType = UnsignedLong; 1233 Int64Type = SignedLong; 1234 1235 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1236 LongDoubleWidth = LongDoubleAlign = 64; 1237 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1238 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1239 "i64:64:64-f32:32:32-f64:64:64-" 1240 "v128:128:128-n32:64"; 1241 } else 1242 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1243 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1244 "v128:128:128-n32:64"; 1245 1246 // PPC64 supports atomics up to 8 bytes. 1247 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1248 } 1249 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1250 return TargetInfo::CharPtrBuiltinVaList; 1251 } 1252 }; 1253 } // end anonymous namespace. 1254 1255 1256 namespace { 1257 class DarwinPPC32TargetInfo : 1258 public DarwinTargetInfo<PPC32TargetInfo> { 1259 public: 1260 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1261 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1262 HasAlignMac68kSupport = true; 1263 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1264 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1265 LongLongAlign = 32; 1266 SuitableAlign = 128; 1267 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1268 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1269 } 1270 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1271 return TargetInfo::CharPtrBuiltinVaList; 1272 } 1273 }; 1274 1275 class DarwinPPC64TargetInfo : 1276 public DarwinTargetInfo<PPC64TargetInfo> { 1277 public: 1278 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1279 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1280 HasAlignMac68kSupport = true; 1281 SuitableAlign = 128; 1282 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1283 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1284 } 1285 }; 1286 } // end anonymous namespace. 1287 1288 namespace { 1289 static const unsigned NVPTXAddrSpaceMap[] = { 1290 1, // opencl_global 1291 3, // opencl_local 1292 4, // opencl_constant 1293 1, // cuda_device 1294 4, // cuda_constant 1295 3, // cuda_shared 1296 }; 1297 class NVPTXTargetInfo : public TargetInfo { 1298 static const char * const GCCRegNames[]; 1299 static const Builtin::Info BuiltinInfo[]; 1300 public: 1301 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1302 BigEndian = false; 1303 TLSSupported = false; 1304 LongWidth = LongAlign = 64; 1305 AddrSpaceMap = &NVPTXAddrSpaceMap; 1306 UseAddrSpaceMapMangling = true; 1307 // Define available target features 1308 // These must be defined in sorted order! 1309 NoAsmVariants = true; 1310 } 1311 virtual void getTargetDefines(const LangOptions &Opts, 1312 MacroBuilder &Builder) const { 1313 Builder.defineMacro("__PTX__"); 1314 Builder.defineMacro("__NVPTX__"); 1315 } 1316 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1317 unsigned &NumRecords) const { 1318 Records = BuiltinInfo; 1319 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1320 } 1321 virtual bool hasFeature(StringRef Feature) const { 1322 return Feature == "ptx" || Feature == "nvptx"; 1323 } 1324 1325 virtual void getGCCRegNames(const char * const *&Names, 1326 unsigned &NumNames) const; 1327 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1328 unsigned &NumAliases) const { 1329 // No aliases. 1330 Aliases = 0; 1331 NumAliases = 0; 1332 } 1333 virtual bool validateAsmConstraint(const char *&Name, 1334 TargetInfo::ConstraintInfo &Info) const { 1335 switch (*Name) { 1336 default: return false; 1337 case 'c': 1338 case 'h': 1339 case 'r': 1340 case 'l': 1341 case 'f': 1342 case 'd': 1343 Info.setAllowsRegister(); 1344 return true; 1345 } 1346 } 1347 virtual const char *getClobbers() const { 1348 // FIXME: Is this really right? 1349 return ""; 1350 } 1351 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1352 // FIXME: implement 1353 return TargetInfo::CharPtrBuiltinVaList; 1354 } 1355 virtual bool setCPU(const std::string &Name) { 1356 bool Valid = llvm::StringSwitch<bool>(Name) 1357 .Case("sm_20", true) 1358 .Case("sm_21", true) 1359 .Case("sm_30", true) 1360 .Case("sm_35", true) 1361 .Default(false); 1362 1363 return Valid; 1364 } 1365 }; 1366 1367 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1368 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1369 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1370 ALL_LANGUAGES }, 1371 #include "clang/Basic/BuiltinsNVPTX.def" 1372 }; 1373 1374 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1375 "r0" 1376 }; 1377 1378 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1379 unsigned &NumNames) const { 1380 Names = GCCRegNames; 1381 NumNames = llvm::array_lengthof(GCCRegNames); 1382 } 1383 1384 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1385 public: 1386 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1387 PointerWidth = PointerAlign = 32; 1388 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1389 DescriptionString 1390 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1391 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1392 "n16:32:64"; 1393 } 1394 }; 1395 1396 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1397 public: 1398 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1399 PointerWidth = PointerAlign = 64; 1400 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1401 DescriptionString 1402 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1403 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1404 "n16:32:64"; 1405 } 1406 }; 1407 } 1408 1409 namespace { 1410 1411 static const unsigned R600AddrSpaceMap[] = { 1412 1, // opencl_global 1413 3, // opencl_local 1414 2, // opencl_constant 1415 1, // cuda_device 1416 2, // cuda_constant 1417 3 // cuda_shared 1418 }; 1419 1420 static const char *DescriptionStringR600 = 1421 "e" 1422 "-p:32:32:32" 1423 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1424 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1425 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1426 "-n32:64"; 1427 1428 static const char *DescriptionStringR600DoubleOps = 1429 "e" 1430 "-p:32:32:32" 1431 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1432 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1433 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1434 "-n32:64"; 1435 1436 static const char *DescriptionStringSI = 1437 "e" 1438 "-p:64:64:64" 1439 "-p3:32:32:32" 1440 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1441 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1442 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1443 "-n32:64"; 1444 1445 class R600TargetInfo : public TargetInfo { 1446 /// \brief The GPU profiles supported by the R600 target. 1447 enum GPUKind { 1448 GK_NONE, 1449 GK_R600, 1450 GK_R600_DOUBLE_OPS, 1451 GK_R700, 1452 GK_R700_DOUBLE_OPS, 1453 GK_EVERGREEN, 1454 GK_EVERGREEN_DOUBLE_OPS, 1455 GK_NORTHERN_ISLANDS, 1456 GK_CAYMAN, 1457 GK_SOUTHERN_ISLANDS 1458 } GPU; 1459 1460 public: 1461 R600TargetInfo(const llvm::Triple &Triple) 1462 : TargetInfo(Triple), GPU(GK_R600) { 1463 DescriptionString = DescriptionStringR600; 1464 AddrSpaceMap = &R600AddrSpaceMap; 1465 UseAddrSpaceMapMangling = true; 1466 } 1467 1468 virtual const char * getClobbers() const { 1469 return ""; 1470 } 1471 1472 virtual void getGCCRegNames(const char * const *&Names, 1473 unsigned &numNames) const { 1474 Names = NULL; 1475 numNames = 0; 1476 } 1477 1478 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1479 unsigned &NumAliases) const { 1480 Aliases = NULL; 1481 NumAliases = 0; 1482 } 1483 1484 virtual bool validateAsmConstraint(const char *&Name, 1485 TargetInfo::ConstraintInfo &info) const { 1486 return true; 1487 } 1488 1489 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1490 unsigned &NumRecords) const { 1491 Records = NULL; 1492 NumRecords = 0; 1493 } 1494 1495 1496 virtual void getTargetDefines(const LangOptions &Opts, 1497 MacroBuilder &Builder) const { 1498 Builder.defineMacro("__R600__"); 1499 } 1500 1501 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1502 return TargetInfo::CharPtrBuiltinVaList; 1503 } 1504 1505 virtual bool setCPU(const std::string &Name) { 1506 GPU = llvm::StringSwitch<GPUKind>(Name) 1507 .Case("r600" , GK_R600) 1508 .Case("rv610", GK_R600) 1509 .Case("rv620", GK_R600) 1510 .Case("rv630", GK_R600) 1511 .Case("rv635", GK_R600) 1512 .Case("rs780", GK_R600) 1513 .Case("rs880", GK_R600) 1514 .Case("rv670", GK_R600_DOUBLE_OPS) 1515 .Case("rv710", GK_R700) 1516 .Case("rv730", GK_R700) 1517 .Case("rv740", GK_R700_DOUBLE_OPS) 1518 .Case("rv770", GK_R700_DOUBLE_OPS) 1519 .Case("palm", GK_EVERGREEN) 1520 .Case("cedar", GK_EVERGREEN) 1521 .Case("sumo", GK_EVERGREEN) 1522 .Case("sumo2", GK_EVERGREEN) 1523 .Case("redwood", GK_EVERGREEN) 1524 .Case("juniper", GK_EVERGREEN) 1525 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1526 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1527 .Case("barts", GK_NORTHERN_ISLANDS) 1528 .Case("turks", GK_NORTHERN_ISLANDS) 1529 .Case("caicos", GK_NORTHERN_ISLANDS) 1530 .Case("cayman", GK_CAYMAN) 1531 .Case("aruba", GK_CAYMAN) 1532 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1533 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1534 .Case("verde", GK_SOUTHERN_ISLANDS) 1535 .Case("oland", GK_SOUTHERN_ISLANDS) 1536 .Default(GK_NONE); 1537 1538 if (GPU == GK_NONE) { 1539 return false; 1540 } 1541 1542 // Set the correct data layout 1543 switch (GPU) { 1544 case GK_NONE: 1545 case GK_R600: 1546 case GK_R700: 1547 case GK_EVERGREEN: 1548 case GK_NORTHERN_ISLANDS: 1549 DescriptionString = DescriptionStringR600; 1550 break; 1551 case GK_R600_DOUBLE_OPS: 1552 case GK_R700_DOUBLE_OPS: 1553 case GK_EVERGREEN_DOUBLE_OPS: 1554 case GK_CAYMAN: 1555 DescriptionString = DescriptionStringR600DoubleOps; 1556 break; 1557 case GK_SOUTHERN_ISLANDS: 1558 DescriptionString = DescriptionStringSI; 1559 break; 1560 } 1561 1562 return true; 1563 } 1564 }; 1565 1566 } // end anonymous namespace 1567 1568 namespace { 1569 // Namespace for x86 abstract base class 1570 const Builtin::Info BuiltinInfo[] = { 1571 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1572 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1573 ALL_LANGUAGES }, 1574 #include "clang/Basic/BuiltinsX86.def" 1575 }; 1576 1577 static const char* const GCCRegNames[] = { 1578 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1579 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1580 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1581 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1582 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1583 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1584 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1585 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1586 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1587 }; 1588 1589 const TargetInfo::AddlRegName AddlRegNames[] = { 1590 { { "al", "ah", "eax", "rax" }, 0 }, 1591 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1592 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1593 { { "dl", "dh", "edx", "rdx" }, 1 }, 1594 { { "esi", "rsi" }, 4 }, 1595 { { "edi", "rdi" }, 5 }, 1596 { { "esp", "rsp" }, 7 }, 1597 { { "ebp", "rbp" }, 6 }, 1598 }; 1599 1600 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1601 // most of the implementation can be shared. 1602 class X86TargetInfo : public TargetInfo { 1603 enum X86SSEEnum { 1604 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1605 } SSELevel; 1606 enum MMX3DNowEnum { 1607 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1608 } MMX3DNowLevel; 1609 enum XOPEnum { 1610 NoXOP, 1611 SSE4A, 1612 FMA4, 1613 XOP 1614 } XOPLevel; 1615 1616 bool HasAES; 1617 bool HasPCLMUL; 1618 bool HasLZCNT; 1619 bool HasRDRND; 1620 bool HasBMI; 1621 bool HasBMI2; 1622 bool HasPOPCNT; 1623 bool HasRTM; 1624 bool HasPRFCHW; 1625 bool HasRDSEED; 1626 bool HasTBM; 1627 bool HasFMA; 1628 bool HasF16C; 1629 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1630 bool HasSHA; 1631 bool HasCX16; 1632 1633 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1634 /// 1635 /// Each enumeration represents a particular CPU supported by Clang. These 1636 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1637 enum CPUKind { 1638 CK_Generic, 1639 1640 /// \name i386 1641 /// i386-generation processors. 1642 //@{ 1643 CK_i386, 1644 //@} 1645 1646 /// \name i486 1647 /// i486-generation processors. 1648 //@{ 1649 CK_i486, 1650 CK_WinChipC6, 1651 CK_WinChip2, 1652 CK_C3, 1653 //@} 1654 1655 /// \name i586 1656 /// i586-generation processors, P5 microarchitecture based. 1657 //@{ 1658 CK_i586, 1659 CK_Pentium, 1660 CK_PentiumMMX, 1661 //@} 1662 1663 /// \name i686 1664 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1665 //@{ 1666 CK_i686, 1667 CK_PentiumPro, 1668 CK_Pentium2, 1669 CK_Pentium3, 1670 CK_Pentium3M, 1671 CK_PentiumM, 1672 CK_C3_2, 1673 1674 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1675 /// Clang however has some logic to suport this. 1676 // FIXME: Warn, deprecate, and potentially remove this. 1677 CK_Yonah, 1678 //@} 1679 1680 /// \name Netburst 1681 /// Netburst microarchitecture based processors. 1682 //@{ 1683 CK_Pentium4, 1684 CK_Pentium4M, 1685 CK_Prescott, 1686 CK_Nocona, 1687 //@} 1688 1689 /// \name Core 1690 /// Core microarchitecture based processors. 1691 //@{ 1692 CK_Core2, 1693 1694 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1695 /// codename which GCC no longer accepts as an option to -march, but Clang 1696 /// has some logic for recognizing it. 1697 // FIXME: Warn, deprecate, and potentially remove this. 1698 CK_Penryn, 1699 //@} 1700 1701 /// \name Atom 1702 /// Atom processors 1703 //@{ 1704 CK_Atom, 1705 CK_Silvermont, 1706 //@} 1707 1708 /// \name Nehalem 1709 /// Nehalem microarchitecture based processors. 1710 //@{ 1711 CK_Corei7, 1712 CK_Corei7AVX, 1713 CK_CoreAVXi, 1714 CK_CoreAVX2, 1715 //@} 1716 1717 /// \name Knights Landing 1718 /// Knights Landing processor. 1719 CK_KNL, 1720 1721 /// \name K6 1722 /// K6 architecture processors. 1723 //@{ 1724 CK_K6, 1725 CK_K6_2, 1726 CK_K6_3, 1727 //@} 1728 1729 /// \name K7 1730 /// K7 architecture processors. 1731 //@{ 1732 CK_Athlon, 1733 CK_AthlonThunderbird, 1734 CK_Athlon4, 1735 CK_AthlonXP, 1736 CK_AthlonMP, 1737 //@} 1738 1739 /// \name K8 1740 /// K8 architecture processors. 1741 //@{ 1742 CK_Athlon64, 1743 CK_Athlon64SSE3, 1744 CK_AthlonFX, 1745 CK_K8, 1746 CK_K8SSE3, 1747 CK_Opteron, 1748 CK_OpteronSSE3, 1749 CK_AMDFAM10, 1750 //@} 1751 1752 /// \name Bobcat 1753 /// Bobcat architecture processors. 1754 //@{ 1755 CK_BTVER1, 1756 CK_BTVER2, 1757 //@} 1758 1759 /// \name Bulldozer 1760 /// Bulldozer architecture processors. 1761 //@{ 1762 CK_BDVER1, 1763 CK_BDVER2, 1764 //@} 1765 1766 /// This specification is deprecated and will be removed in the future. 1767 /// Users should prefer \see CK_K8. 1768 // FIXME: Warn on this when the CPU is set to it. 1769 CK_x86_64, 1770 //@} 1771 1772 /// \name Geode 1773 /// Geode processors. 1774 //@{ 1775 CK_Geode 1776 //@} 1777 } CPU; 1778 1779 enum FPMathKind { 1780 FP_Default, 1781 FP_SSE, 1782 FP_387 1783 } FPMath; 1784 1785 public: 1786 X86TargetInfo(const llvm::Triple &Triple) 1787 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1788 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1789 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1790 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1791 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1792 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1793 FPMath(FP_Default) { 1794 BigEndian = false; 1795 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1796 } 1797 virtual unsigned getFloatEvalMethod() const { 1798 // X87 evaluates with 80 bits "long double" precision. 1799 return SSELevel == NoSSE ? 2 : 0; 1800 } 1801 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1802 unsigned &NumRecords) const { 1803 Records = BuiltinInfo; 1804 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1805 } 1806 virtual void getGCCRegNames(const char * const *&Names, 1807 unsigned &NumNames) const { 1808 Names = GCCRegNames; 1809 NumNames = llvm::array_lengthof(GCCRegNames); 1810 } 1811 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1812 unsigned &NumAliases) const { 1813 Aliases = 0; 1814 NumAliases = 0; 1815 } 1816 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1817 unsigned &NumNames) const { 1818 Names = AddlRegNames; 1819 NumNames = llvm::array_lengthof(AddlRegNames); 1820 } 1821 virtual bool validateAsmConstraint(const char *&Name, 1822 TargetInfo::ConstraintInfo &info) const; 1823 virtual std::string convertConstraint(const char *&Constraint) const; 1824 virtual const char *getClobbers() const { 1825 return "~{dirflag},~{fpsr},~{flags}"; 1826 } 1827 virtual void getTargetDefines(const LangOptions &Opts, 1828 MacroBuilder &Builder) const; 1829 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1830 bool Enabled); 1831 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1832 bool Enabled); 1833 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1834 bool Enabled); 1835 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1836 StringRef Name, bool Enabled) const { 1837 setFeatureEnabledImpl(Features, Name, Enabled); 1838 } 1839 // This exists purely to cut down on the number of virtual calls in 1840 // getDefaultFeatures which calls this repeatedly. 1841 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1842 StringRef Name, bool Enabled); 1843 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1844 virtual bool hasFeature(StringRef Feature) const; 1845 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1846 DiagnosticsEngine &Diags); 1847 virtual const char* getABI() const { 1848 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1849 return "avx"; 1850 else if (getTriple().getArch() == llvm::Triple::x86 && 1851 MMX3DNowLevel == NoMMX3DNow) 1852 return "no-mmx"; 1853 return ""; 1854 } 1855 virtual bool setCPU(const std::string &Name) { 1856 CPU = llvm::StringSwitch<CPUKind>(Name) 1857 .Case("i386", CK_i386) 1858 .Case("i486", CK_i486) 1859 .Case("winchip-c6", CK_WinChipC6) 1860 .Case("winchip2", CK_WinChip2) 1861 .Case("c3", CK_C3) 1862 .Case("i586", CK_i586) 1863 .Case("pentium", CK_Pentium) 1864 .Case("pentium-mmx", CK_PentiumMMX) 1865 .Case("i686", CK_i686) 1866 .Case("pentiumpro", CK_PentiumPro) 1867 .Case("pentium2", CK_Pentium2) 1868 .Case("pentium3", CK_Pentium3) 1869 .Case("pentium3m", CK_Pentium3M) 1870 .Case("pentium-m", CK_PentiumM) 1871 .Case("c3-2", CK_C3_2) 1872 .Case("yonah", CK_Yonah) 1873 .Case("pentium4", CK_Pentium4) 1874 .Case("pentium4m", CK_Pentium4M) 1875 .Case("prescott", CK_Prescott) 1876 .Case("nocona", CK_Nocona) 1877 .Case("core2", CK_Core2) 1878 .Case("penryn", CK_Penryn) 1879 .Case("atom", CK_Atom) 1880 .Case("slm", CK_Silvermont) 1881 .Case("corei7", CK_Corei7) 1882 .Case("corei7-avx", CK_Corei7AVX) 1883 .Case("core-avx-i", CK_CoreAVXi) 1884 .Case("core-avx2", CK_CoreAVX2) 1885 .Case("knl", CK_KNL) 1886 .Case("k6", CK_K6) 1887 .Case("k6-2", CK_K6_2) 1888 .Case("k6-3", CK_K6_3) 1889 .Case("athlon", CK_Athlon) 1890 .Case("athlon-tbird", CK_AthlonThunderbird) 1891 .Case("athlon-4", CK_Athlon4) 1892 .Case("athlon-xp", CK_AthlonXP) 1893 .Case("athlon-mp", CK_AthlonMP) 1894 .Case("athlon64", CK_Athlon64) 1895 .Case("athlon64-sse3", CK_Athlon64SSE3) 1896 .Case("athlon-fx", CK_AthlonFX) 1897 .Case("k8", CK_K8) 1898 .Case("k8-sse3", CK_K8SSE3) 1899 .Case("opteron", CK_Opteron) 1900 .Case("opteron-sse3", CK_OpteronSSE3) 1901 .Case("amdfam10", CK_AMDFAM10) 1902 .Case("btver1", CK_BTVER1) 1903 .Case("btver2", CK_BTVER2) 1904 .Case("bdver1", CK_BDVER1) 1905 .Case("bdver2", CK_BDVER2) 1906 .Case("x86-64", CK_x86_64) 1907 .Case("geode", CK_Geode) 1908 .Default(CK_Generic); 1909 1910 // Perform any per-CPU checks necessary to determine if this CPU is 1911 // acceptable. 1912 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1913 // invalid without explaining *why*. 1914 switch (CPU) { 1915 case CK_Generic: 1916 // No processor selected! 1917 return false; 1918 1919 case CK_i386: 1920 case CK_i486: 1921 case CK_WinChipC6: 1922 case CK_WinChip2: 1923 case CK_C3: 1924 case CK_i586: 1925 case CK_Pentium: 1926 case CK_PentiumMMX: 1927 case CK_i686: 1928 case CK_PentiumPro: 1929 case CK_Pentium2: 1930 case CK_Pentium3: 1931 case CK_Pentium3M: 1932 case CK_PentiumM: 1933 case CK_Yonah: 1934 case CK_C3_2: 1935 case CK_Pentium4: 1936 case CK_Pentium4M: 1937 case CK_Prescott: 1938 case CK_K6: 1939 case CK_K6_2: 1940 case CK_K6_3: 1941 case CK_Athlon: 1942 case CK_AthlonThunderbird: 1943 case CK_Athlon4: 1944 case CK_AthlonXP: 1945 case CK_AthlonMP: 1946 case CK_Geode: 1947 // Only accept certain architectures when compiling in 32-bit mode. 1948 if (getTriple().getArch() != llvm::Triple::x86) 1949 return false; 1950 1951 // Fallthrough 1952 case CK_Nocona: 1953 case CK_Core2: 1954 case CK_Penryn: 1955 case CK_Atom: 1956 case CK_Silvermont: 1957 case CK_Corei7: 1958 case CK_Corei7AVX: 1959 case CK_CoreAVXi: 1960 case CK_CoreAVX2: 1961 case CK_KNL: 1962 case CK_Athlon64: 1963 case CK_Athlon64SSE3: 1964 case CK_AthlonFX: 1965 case CK_K8: 1966 case CK_K8SSE3: 1967 case CK_Opteron: 1968 case CK_OpteronSSE3: 1969 case CK_AMDFAM10: 1970 case CK_BTVER1: 1971 case CK_BTVER2: 1972 case CK_BDVER1: 1973 case CK_BDVER2: 1974 case CK_x86_64: 1975 return true; 1976 } 1977 llvm_unreachable("Unhandled CPU kind"); 1978 } 1979 1980 virtual bool setFPMath(StringRef Name); 1981 1982 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1983 // We accept all non-ARM calling conventions 1984 return (CC == CC_X86ThisCall || 1985 CC == CC_X86FastCall || 1986 CC == CC_X86StdCall || 1987 CC == CC_C || 1988 CC == CC_X86Pascal || 1989 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1990 } 1991 1992 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1993 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1994 } 1995 }; 1996 1997 bool X86TargetInfo::setFPMath(StringRef Name) { 1998 if (Name == "387") { 1999 FPMath = FP_387; 2000 return true; 2001 } 2002 if (Name == "sse") { 2003 FPMath = FP_SSE; 2004 return true; 2005 } 2006 return false; 2007 } 2008 2009 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2010 // FIXME: This *really* should not be here. 2011 2012 // X86_64 always has SSE2. 2013 if (getTriple().getArch() == llvm::Triple::x86_64) 2014 setFeatureEnabledImpl(Features, "sse2", true); 2015 2016 switch (CPU) { 2017 case CK_Generic: 2018 case CK_i386: 2019 case CK_i486: 2020 case CK_i586: 2021 case CK_Pentium: 2022 case CK_i686: 2023 case CK_PentiumPro: 2024 break; 2025 case CK_PentiumMMX: 2026 case CK_Pentium2: 2027 setFeatureEnabledImpl(Features, "mmx", true); 2028 break; 2029 case CK_Pentium3: 2030 case CK_Pentium3M: 2031 setFeatureEnabledImpl(Features, "sse", true); 2032 break; 2033 case CK_PentiumM: 2034 case CK_Pentium4: 2035 case CK_Pentium4M: 2036 case CK_x86_64: 2037 setFeatureEnabledImpl(Features, "sse2", true); 2038 break; 2039 case CK_Yonah: 2040 case CK_Prescott: 2041 case CK_Nocona: 2042 setFeatureEnabledImpl(Features, "sse3", true); 2043 setFeatureEnabledImpl(Features, "cx16", true); 2044 break; 2045 case CK_Core2: 2046 setFeatureEnabledImpl(Features, "ssse3", true); 2047 setFeatureEnabledImpl(Features, "cx16", true); 2048 break; 2049 case CK_Penryn: 2050 setFeatureEnabledImpl(Features, "sse4.1", true); 2051 setFeatureEnabledImpl(Features, "cx16", true); 2052 break; 2053 case CK_Atom: 2054 setFeatureEnabledImpl(Features, "ssse3", true); 2055 setFeatureEnabledImpl(Features, "cx16", true); 2056 break; 2057 case CK_Silvermont: 2058 setFeatureEnabledImpl(Features, "sse4.2", true); 2059 setFeatureEnabledImpl(Features, "aes", true); 2060 setFeatureEnabledImpl(Features, "cx16", true); 2061 setFeatureEnabledImpl(Features, "pclmul", true); 2062 break; 2063 case CK_Corei7: 2064 setFeatureEnabledImpl(Features, "sse4.2", true); 2065 setFeatureEnabledImpl(Features, "cx16", true); 2066 break; 2067 case CK_Corei7AVX: 2068 setFeatureEnabledImpl(Features, "avx", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 setFeatureEnabledImpl(Features, "pclmul", true); 2072 break; 2073 case CK_CoreAVXi: 2074 setFeatureEnabledImpl(Features, "avx", true); 2075 setFeatureEnabledImpl(Features, "aes", true); 2076 setFeatureEnabledImpl(Features, "pclmul", true); 2077 setFeatureEnabledImpl(Features, "rdrnd", true); 2078 setFeatureEnabledImpl(Features, "f16c", true); 2079 break; 2080 case CK_CoreAVX2: 2081 setFeatureEnabledImpl(Features, "avx2", true); 2082 setFeatureEnabledImpl(Features, "aes", true); 2083 setFeatureEnabledImpl(Features, "pclmul", true); 2084 setFeatureEnabledImpl(Features, "lzcnt", true); 2085 setFeatureEnabledImpl(Features, "rdrnd", true); 2086 setFeatureEnabledImpl(Features, "f16c", true); 2087 setFeatureEnabledImpl(Features, "bmi", true); 2088 setFeatureEnabledImpl(Features, "bmi2", true); 2089 setFeatureEnabledImpl(Features, "rtm", true); 2090 setFeatureEnabledImpl(Features, "fma", true); 2091 setFeatureEnabledImpl(Features, "cx16", true); 2092 break; 2093 case CK_KNL: 2094 setFeatureEnabledImpl(Features, "avx512f", true); 2095 setFeatureEnabledImpl(Features, "avx512cd", true); 2096 setFeatureEnabledImpl(Features, "avx512er", true); 2097 setFeatureEnabledImpl(Features, "avx512pf", true); 2098 setFeatureEnabledImpl(Features, "aes", true); 2099 setFeatureEnabledImpl(Features, "pclmul", true); 2100 setFeatureEnabledImpl(Features, "lzcnt", true); 2101 setFeatureEnabledImpl(Features, "rdrnd", true); 2102 setFeatureEnabledImpl(Features, "f16c", true); 2103 setFeatureEnabledImpl(Features, "bmi", true); 2104 setFeatureEnabledImpl(Features, "bmi2", true); 2105 setFeatureEnabledImpl(Features, "rtm", true); 2106 setFeatureEnabledImpl(Features, "fma", true); 2107 break; 2108 case CK_K6: 2109 case CK_WinChipC6: 2110 setFeatureEnabledImpl(Features, "mmx", true); 2111 break; 2112 case CK_K6_2: 2113 case CK_K6_3: 2114 case CK_WinChip2: 2115 case CK_C3: 2116 setFeatureEnabledImpl(Features, "3dnow", true); 2117 break; 2118 case CK_Athlon: 2119 case CK_AthlonThunderbird: 2120 case CK_Geode: 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_Athlon4: 2124 case CK_AthlonXP: 2125 case CK_AthlonMP: 2126 setFeatureEnabledImpl(Features, "sse", true); 2127 setFeatureEnabledImpl(Features, "3dnowa", true); 2128 break; 2129 case CK_K8: 2130 case CK_Opteron: 2131 case CK_Athlon64: 2132 case CK_AthlonFX: 2133 setFeatureEnabledImpl(Features, "sse2", true); 2134 setFeatureEnabledImpl(Features, "3dnowa", true); 2135 break; 2136 case CK_K8SSE3: 2137 case CK_OpteronSSE3: 2138 case CK_Athlon64SSE3: 2139 setFeatureEnabledImpl(Features, "sse3", true); 2140 setFeatureEnabledImpl(Features, "3dnowa", true); 2141 break; 2142 case CK_AMDFAM10: 2143 setFeatureEnabledImpl(Features, "sse3", true); 2144 setFeatureEnabledImpl(Features, "sse4a", true); 2145 setFeatureEnabledImpl(Features, "3dnowa", true); 2146 setFeatureEnabledImpl(Features, "lzcnt", true); 2147 setFeatureEnabledImpl(Features, "popcnt", true); 2148 break; 2149 case CK_BTVER1: 2150 setFeatureEnabledImpl(Features, "ssse3", true); 2151 setFeatureEnabledImpl(Features, "sse4a", true); 2152 setFeatureEnabledImpl(Features, "cx16", true); 2153 setFeatureEnabledImpl(Features, "lzcnt", true); 2154 setFeatureEnabledImpl(Features, "popcnt", true); 2155 setFeatureEnabledImpl(Features, "prfchw", true); 2156 break; 2157 case CK_BTVER2: 2158 setFeatureEnabledImpl(Features, "avx", true); 2159 setFeatureEnabledImpl(Features, "sse4a", true); 2160 setFeatureEnabledImpl(Features, "lzcnt", true); 2161 setFeatureEnabledImpl(Features, "aes", true); 2162 setFeatureEnabledImpl(Features, "pclmul", true); 2163 setFeatureEnabledImpl(Features, "prfchw", true); 2164 setFeatureEnabledImpl(Features, "bmi", true); 2165 setFeatureEnabledImpl(Features, "f16c", true); 2166 setFeatureEnabledImpl(Features, "cx16", true); 2167 break; 2168 case CK_BDVER1: 2169 setFeatureEnabledImpl(Features, "xop", true); 2170 setFeatureEnabledImpl(Features, "lzcnt", true); 2171 setFeatureEnabledImpl(Features, "aes", true); 2172 setFeatureEnabledImpl(Features, "pclmul", true); 2173 setFeatureEnabledImpl(Features, "prfchw", true); 2174 setFeatureEnabledImpl(Features, "cx16", true); 2175 break; 2176 case CK_BDVER2: 2177 setFeatureEnabledImpl(Features, "xop", true); 2178 setFeatureEnabledImpl(Features, "lzcnt", true); 2179 setFeatureEnabledImpl(Features, "aes", true); 2180 setFeatureEnabledImpl(Features, "pclmul", true); 2181 setFeatureEnabledImpl(Features, "prfchw", true); 2182 setFeatureEnabledImpl(Features, "bmi", true); 2183 setFeatureEnabledImpl(Features, "fma", true); 2184 setFeatureEnabledImpl(Features, "f16c", true); 2185 setFeatureEnabledImpl(Features, "tbm", true); 2186 setFeatureEnabledImpl(Features, "cx16", true); 2187 break; 2188 case CK_C3_2: 2189 setFeatureEnabledImpl(Features, "sse", true); 2190 break; 2191 } 2192 } 2193 2194 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2195 X86SSEEnum Level, bool Enabled) { 2196 if (Enabled) { 2197 switch (Level) { 2198 case AVX512F: 2199 Features["avx512f"] = true; 2200 case AVX2: 2201 Features["avx2"] = true; 2202 case AVX: 2203 Features["avx"] = true; 2204 case SSE42: 2205 Features["sse4.2"] = true; 2206 case SSE41: 2207 Features["sse4.1"] = true; 2208 case SSSE3: 2209 Features["ssse3"] = true; 2210 case SSE3: 2211 Features["sse3"] = true; 2212 case SSE2: 2213 Features["sse2"] = true; 2214 case SSE1: 2215 Features["sse"] = true; 2216 case NoSSE: 2217 break; 2218 } 2219 return; 2220 } 2221 2222 switch (Level) { 2223 case NoSSE: 2224 case SSE1: 2225 Features["sse"] = false; 2226 case SSE2: 2227 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2228 Features["sha"] = false; 2229 case SSE3: 2230 Features["sse3"] = false; 2231 setXOPLevel(Features, NoXOP, false); 2232 case SSSE3: 2233 Features["ssse3"] = false; 2234 case SSE41: 2235 Features["sse4.1"] = false; 2236 case SSE42: 2237 Features["sse4.2"] = false; 2238 case AVX: 2239 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2240 setXOPLevel(Features, FMA4, false); 2241 case AVX2: 2242 Features["avx2"] = false; 2243 case AVX512F: 2244 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2245 Features["avx512pf"] = false; 2246 } 2247 } 2248 2249 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2250 MMX3DNowEnum Level, bool Enabled) { 2251 if (Enabled) { 2252 switch (Level) { 2253 case AMD3DNowAthlon: 2254 Features["3dnowa"] = true; 2255 case AMD3DNow: 2256 Features["3dnow"] = true; 2257 case MMX: 2258 Features["mmx"] = true; 2259 case NoMMX3DNow: 2260 break; 2261 } 2262 return; 2263 } 2264 2265 switch (Level) { 2266 case NoMMX3DNow: 2267 case MMX: 2268 Features["mmx"] = false; 2269 case AMD3DNow: 2270 Features["3dnow"] = false; 2271 case AMD3DNowAthlon: 2272 Features["3dnowa"] = false; 2273 } 2274 } 2275 2276 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2277 bool Enabled) { 2278 if (Enabled) { 2279 switch (Level) { 2280 case XOP: 2281 Features["xop"] = true; 2282 case FMA4: 2283 Features["fma4"] = true; 2284 setSSELevel(Features, AVX, true); 2285 case SSE4A: 2286 Features["sse4a"] = true; 2287 setSSELevel(Features, SSE3, true); 2288 case NoXOP: 2289 break; 2290 } 2291 return; 2292 } 2293 2294 switch (Level) { 2295 case NoXOP: 2296 case SSE4A: 2297 Features["sse4a"] = false; 2298 case FMA4: 2299 Features["fma4"] = false; 2300 case XOP: 2301 Features["xop"] = false; 2302 } 2303 } 2304 2305 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2306 StringRef Name, bool Enabled) { 2307 // FIXME: This *really* should not be here. We need some way of translating 2308 // options into llvm subtarget features. 2309 if (Name == "sse4") 2310 Name = "sse4.2"; 2311 2312 Features[Name] = Enabled; 2313 2314 if (Name == "mmx") { 2315 setMMXLevel(Features, MMX, Enabled); 2316 } else if (Name == "sse") { 2317 setSSELevel(Features, SSE1, Enabled); 2318 } else if (Name == "sse2") { 2319 setSSELevel(Features, SSE2, Enabled); 2320 } else if (Name == "sse3") { 2321 setSSELevel(Features, SSE3, Enabled); 2322 } else if (Name == "ssse3") { 2323 setSSELevel(Features, SSSE3, Enabled); 2324 } else if (Name == "sse4.2") { 2325 setSSELevel(Features, SSE42, Enabled); 2326 } else if (Name == "sse4.1") { 2327 setSSELevel(Features, SSE41, Enabled); 2328 } else if (Name == "3dnow") { 2329 setMMXLevel(Features, AMD3DNow, Enabled); 2330 } else if (Name == "3dnowa") { 2331 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2332 } else if (Name == "aes") { 2333 if (Enabled) 2334 setSSELevel(Features, SSE2, Enabled); 2335 } else if (Name == "pclmul") { 2336 if (Enabled) 2337 setSSELevel(Features, SSE2, Enabled); 2338 } else if (Name == "avx") { 2339 setSSELevel(Features, AVX, Enabled); 2340 } else if (Name == "avx2") { 2341 setSSELevel(Features, AVX2, Enabled); 2342 } else if (Name == "avx512f") { 2343 setSSELevel(Features, AVX512F, Enabled); 2344 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2345 if (Enabled) 2346 setSSELevel(Features, AVX512F, Enabled); 2347 } else if (Name == "fma") { 2348 if (Enabled) 2349 setSSELevel(Features, AVX, Enabled); 2350 } else if (Name == "fma4") { 2351 setXOPLevel(Features, FMA4, Enabled); 2352 } else if (Name == "xop") { 2353 setXOPLevel(Features, XOP, Enabled); 2354 } else if (Name == "sse4a") { 2355 setXOPLevel(Features, SSE4A, Enabled); 2356 } else if (Name == "f16c") { 2357 if (Enabled) 2358 setSSELevel(Features, AVX, Enabled); 2359 } else if (Name == "sha") { 2360 if (Enabled) 2361 setSSELevel(Features, SSE2, Enabled); 2362 } 2363 } 2364 2365 /// handleTargetFeatures - Perform initialization based on the user 2366 /// configured set of features. 2367 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2368 DiagnosticsEngine &Diags) { 2369 // Remember the maximum enabled sselevel. 2370 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2371 // Ignore disabled features. 2372 if (Features[i][0] == '-') 2373 continue; 2374 2375 StringRef Feature = StringRef(Features[i]).substr(1); 2376 2377 if (Feature == "aes") { 2378 HasAES = true; 2379 continue; 2380 } 2381 2382 if (Feature == "pclmul") { 2383 HasPCLMUL = true; 2384 continue; 2385 } 2386 2387 if (Feature == "lzcnt") { 2388 HasLZCNT = true; 2389 continue; 2390 } 2391 2392 if (Feature == "rdrnd") { 2393 HasRDRND = true; 2394 continue; 2395 } 2396 2397 if (Feature == "bmi") { 2398 HasBMI = true; 2399 continue; 2400 } 2401 2402 if (Feature == "bmi2") { 2403 HasBMI2 = true; 2404 continue; 2405 } 2406 2407 if (Feature == "popcnt") { 2408 HasPOPCNT = true; 2409 continue; 2410 } 2411 2412 if (Feature == "rtm") { 2413 HasRTM = true; 2414 continue; 2415 } 2416 2417 if (Feature == "prfchw") { 2418 HasPRFCHW = true; 2419 continue; 2420 } 2421 2422 if (Feature == "rdseed") { 2423 HasRDSEED = true; 2424 continue; 2425 } 2426 2427 if (Feature == "tbm") { 2428 HasTBM = true; 2429 continue; 2430 } 2431 2432 if (Feature == "fma") { 2433 HasFMA = true; 2434 continue; 2435 } 2436 2437 if (Feature == "f16c") { 2438 HasF16C = true; 2439 continue; 2440 } 2441 2442 if (Feature == "avx512cd") { 2443 HasAVX512CD = true; 2444 continue; 2445 } 2446 2447 if (Feature == "avx512er") { 2448 HasAVX512ER = true; 2449 continue; 2450 } 2451 2452 if (Feature == "avx512pf") { 2453 HasAVX512PF = true; 2454 continue; 2455 } 2456 2457 if (Feature == "sha") { 2458 HasSHA = true; 2459 continue; 2460 } 2461 2462 if (Feature == "cx16") { 2463 HasCX16 = true; 2464 continue; 2465 } 2466 2467 assert(Features[i][0] == '+' && "Invalid target feature!"); 2468 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2469 .Case("avx512f", AVX512F) 2470 .Case("avx2", AVX2) 2471 .Case("avx", AVX) 2472 .Case("sse4.2", SSE42) 2473 .Case("sse4.1", SSE41) 2474 .Case("ssse3", SSSE3) 2475 .Case("sse3", SSE3) 2476 .Case("sse2", SSE2) 2477 .Case("sse", SSE1) 2478 .Default(NoSSE); 2479 SSELevel = std::max(SSELevel, Level); 2480 2481 MMX3DNowEnum ThreeDNowLevel = 2482 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2483 .Case("3dnowa", AMD3DNowAthlon) 2484 .Case("3dnow", AMD3DNow) 2485 .Case("mmx", MMX) 2486 .Default(NoMMX3DNow); 2487 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2488 2489 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2490 .Case("xop", XOP) 2491 .Case("fma4", FMA4) 2492 .Case("sse4a", SSE4A) 2493 .Default(NoXOP); 2494 XOPLevel = std::max(XOPLevel, XLevel); 2495 } 2496 2497 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2498 // Can't do this earlier because we need to be able to explicitly enable 2499 // popcnt and still disable sse4.2. 2500 if (!HasPOPCNT && SSELevel >= SSE42 && 2501 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2502 HasPOPCNT = true; 2503 Features.push_back("+popcnt"); 2504 } 2505 2506 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2507 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2508 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2509 HasPRFCHW = true; 2510 Features.push_back("+prfchw"); 2511 } 2512 2513 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2514 // matches the selected sse level. 2515 if (FPMath == FP_SSE && SSELevel < SSE1) { 2516 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2517 return false; 2518 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2519 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2520 return false; 2521 } 2522 2523 // Don't tell the backend if we're turning off mmx; it will end up disabling 2524 // SSE, which we don't want. 2525 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2526 // then enable MMX. 2527 std::vector<std::string>::iterator it; 2528 it = std::find(Features.begin(), Features.end(), "-mmx"); 2529 if (it != Features.end()) 2530 Features.erase(it); 2531 else if (SSELevel > NoSSE) 2532 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2533 return true; 2534 } 2535 2536 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2537 /// definitions for this particular subtarget. 2538 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2539 MacroBuilder &Builder) const { 2540 // Target identification. 2541 if (getTriple().getArch() == llvm::Triple::x86_64) { 2542 Builder.defineMacro("__amd64__"); 2543 Builder.defineMacro("__amd64"); 2544 Builder.defineMacro("__x86_64"); 2545 Builder.defineMacro("__x86_64__"); 2546 } else { 2547 DefineStd(Builder, "i386", Opts); 2548 } 2549 2550 // Subtarget options. 2551 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2552 // truly should be based on -mtune options. 2553 switch (CPU) { 2554 case CK_Generic: 2555 break; 2556 case CK_i386: 2557 // The rest are coming from the i386 define above. 2558 Builder.defineMacro("__tune_i386__"); 2559 break; 2560 case CK_i486: 2561 case CK_WinChipC6: 2562 case CK_WinChip2: 2563 case CK_C3: 2564 defineCPUMacros(Builder, "i486"); 2565 break; 2566 case CK_PentiumMMX: 2567 Builder.defineMacro("__pentium_mmx__"); 2568 Builder.defineMacro("__tune_pentium_mmx__"); 2569 // Fallthrough 2570 case CK_i586: 2571 case CK_Pentium: 2572 defineCPUMacros(Builder, "i586"); 2573 defineCPUMacros(Builder, "pentium"); 2574 break; 2575 case CK_Pentium3: 2576 case CK_Pentium3M: 2577 case CK_PentiumM: 2578 Builder.defineMacro("__tune_pentium3__"); 2579 // Fallthrough 2580 case CK_Pentium2: 2581 case CK_C3_2: 2582 Builder.defineMacro("__tune_pentium2__"); 2583 // Fallthrough 2584 case CK_PentiumPro: 2585 Builder.defineMacro("__tune_i686__"); 2586 Builder.defineMacro("__tune_pentiumpro__"); 2587 // Fallthrough 2588 case CK_i686: 2589 Builder.defineMacro("__i686"); 2590 Builder.defineMacro("__i686__"); 2591 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2592 Builder.defineMacro("__pentiumpro"); 2593 Builder.defineMacro("__pentiumpro__"); 2594 break; 2595 case CK_Pentium4: 2596 case CK_Pentium4M: 2597 defineCPUMacros(Builder, "pentium4"); 2598 break; 2599 case CK_Yonah: 2600 case CK_Prescott: 2601 case CK_Nocona: 2602 defineCPUMacros(Builder, "nocona"); 2603 break; 2604 case CK_Core2: 2605 case CK_Penryn: 2606 defineCPUMacros(Builder, "core2"); 2607 break; 2608 case CK_Atom: 2609 defineCPUMacros(Builder, "atom"); 2610 break; 2611 case CK_Silvermont: 2612 defineCPUMacros(Builder, "slm"); 2613 break; 2614 case CK_Corei7: 2615 case CK_Corei7AVX: 2616 case CK_CoreAVXi: 2617 case CK_CoreAVX2: 2618 defineCPUMacros(Builder, "corei7"); 2619 break; 2620 case CK_KNL: 2621 defineCPUMacros(Builder, "knl"); 2622 break; 2623 case CK_K6_2: 2624 Builder.defineMacro("__k6_2__"); 2625 Builder.defineMacro("__tune_k6_2__"); 2626 // Fallthrough 2627 case CK_K6_3: 2628 if (CPU != CK_K6_2) { // In case of fallthrough 2629 // FIXME: GCC may be enabling these in cases where some other k6 2630 // architecture is specified but -m3dnow is explicitly provided. The 2631 // exact semantics need to be determined and emulated here. 2632 Builder.defineMacro("__k6_3__"); 2633 Builder.defineMacro("__tune_k6_3__"); 2634 } 2635 // Fallthrough 2636 case CK_K6: 2637 defineCPUMacros(Builder, "k6"); 2638 break; 2639 case CK_Athlon: 2640 case CK_AthlonThunderbird: 2641 case CK_Athlon4: 2642 case CK_AthlonXP: 2643 case CK_AthlonMP: 2644 defineCPUMacros(Builder, "athlon"); 2645 if (SSELevel != NoSSE) { 2646 Builder.defineMacro("__athlon_sse__"); 2647 Builder.defineMacro("__tune_athlon_sse__"); 2648 } 2649 break; 2650 case CK_K8: 2651 case CK_K8SSE3: 2652 case CK_x86_64: 2653 case CK_Opteron: 2654 case CK_OpteronSSE3: 2655 case CK_Athlon64: 2656 case CK_Athlon64SSE3: 2657 case CK_AthlonFX: 2658 defineCPUMacros(Builder, "k8"); 2659 break; 2660 case CK_AMDFAM10: 2661 defineCPUMacros(Builder, "amdfam10"); 2662 break; 2663 case CK_BTVER1: 2664 defineCPUMacros(Builder, "btver1"); 2665 break; 2666 case CK_BTVER2: 2667 defineCPUMacros(Builder, "btver2"); 2668 break; 2669 case CK_BDVER1: 2670 defineCPUMacros(Builder, "bdver1"); 2671 break; 2672 case CK_BDVER2: 2673 defineCPUMacros(Builder, "bdver2"); 2674 break; 2675 case CK_Geode: 2676 defineCPUMacros(Builder, "geode"); 2677 break; 2678 } 2679 2680 // Target properties. 2681 Builder.defineMacro("__LITTLE_ENDIAN__"); 2682 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2683 2684 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2685 // functions in glibc header files that use FP Stack inline asm which the 2686 // backend can't deal with (PR879). 2687 Builder.defineMacro("__NO_MATH_INLINES"); 2688 2689 if (HasAES) 2690 Builder.defineMacro("__AES__"); 2691 2692 if (HasPCLMUL) 2693 Builder.defineMacro("__PCLMUL__"); 2694 2695 if (HasLZCNT) 2696 Builder.defineMacro("__LZCNT__"); 2697 2698 if (HasRDRND) 2699 Builder.defineMacro("__RDRND__"); 2700 2701 if (HasBMI) 2702 Builder.defineMacro("__BMI__"); 2703 2704 if (HasBMI2) 2705 Builder.defineMacro("__BMI2__"); 2706 2707 if (HasPOPCNT) 2708 Builder.defineMacro("__POPCNT__"); 2709 2710 if (HasRTM) 2711 Builder.defineMacro("__RTM__"); 2712 2713 if (HasPRFCHW) 2714 Builder.defineMacro("__PRFCHW__"); 2715 2716 if (HasRDSEED) 2717 Builder.defineMacro("__RDSEED__"); 2718 2719 if (HasTBM) 2720 Builder.defineMacro("__TBM__"); 2721 2722 switch (XOPLevel) { 2723 case XOP: 2724 Builder.defineMacro("__XOP__"); 2725 case FMA4: 2726 Builder.defineMacro("__FMA4__"); 2727 case SSE4A: 2728 Builder.defineMacro("__SSE4A__"); 2729 case NoXOP: 2730 break; 2731 } 2732 2733 if (HasFMA) 2734 Builder.defineMacro("__FMA__"); 2735 2736 if (HasF16C) 2737 Builder.defineMacro("__F16C__"); 2738 2739 if (HasAVX512CD) 2740 Builder.defineMacro("__AVX512CD__"); 2741 if (HasAVX512ER) 2742 Builder.defineMacro("__AVX512ER__"); 2743 if (HasAVX512PF) 2744 Builder.defineMacro("__AVX512PF__"); 2745 2746 if (HasSHA) 2747 Builder.defineMacro("__SHA__"); 2748 2749 if (HasCX16) 2750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2751 2752 // Each case falls through to the previous one here. 2753 switch (SSELevel) { 2754 case AVX512F: 2755 Builder.defineMacro("__AVX512F__"); 2756 case AVX2: 2757 Builder.defineMacro("__AVX2__"); 2758 case AVX: 2759 Builder.defineMacro("__AVX__"); 2760 case SSE42: 2761 Builder.defineMacro("__SSE4_2__"); 2762 case SSE41: 2763 Builder.defineMacro("__SSE4_1__"); 2764 case SSSE3: 2765 Builder.defineMacro("__SSSE3__"); 2766 case SSE3: 2767 Builder.defineMacro("__SSE3__"); 2768 case SSE2: 2769 Builder.defineMacro("__SSE2__"); 2770 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2771 case SSE1: 2772 Builder.defineMacro("__SSE__"); 2773 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2774 case NoSSE: 2775 break; 2776 } 2777 2778 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2779 switch (SSELevel) { 2780 case AVX512F: 2781 case AVX2: 2782 case AVX: 2783 case SSE42: 2784 case SSE41: 2785 case SSSE3: 2786 case SSE3: 2787 case SSE2: 2788 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2789 break; 2790 case SSE1: 2791 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2792 break; 2793 default: 2794 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2795 } 2796 } 2797 2798 // Each case falls through to the previous one here. 2799 switch (MMX3DNowLevel) { 2800 case AMD3DNowAthlon: 2801 Builder.defineMacro("__3dNOW_A__"); 2802 case AMD3DNow: 2803 Builder.defineMacro("__3dNOW__"); 2804 case MMX: 2805 Builder.defineMacro("__MMX__"); 2806 case NoMMX3DNow: 2807 break; 2808 } 2809 2810 if (CPU >= CK_i486) { 2811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2814 } 2815 if (CPU >= CK_i586) 2816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2817 } 2818 2819 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2820 return llvm::StringSwitch<bool>(Feature) 2821 .Case("aes", HasAES) 2822 .Case("avx", SSELevel >= AVX) 2823 .Case("avx2", SSELevel >= AVX2) 2824 .Case("avx512f", SSELevel >= AVX512F) 2825 .Case("avx512cd", HasAVX512CD) 2826 .Case("avx512er", HasAVX512ER) 2827 .Case("avx512pf", HasAVX512PF) 2828 .Case("bmi", HasBMI) 2829 .Case("bmi2", HasBMI2) 2830 .Case("cx16", HasCX16) 2831 .Case("f16c", HasF16C) 2832 .Case("fma", HasFMA) 2833 .Case("fma4", XOPLevel >= FMA4) 2834 .Case("tbm", HasTBM) 2835 .Case("lzcnt", HasLZCNT) 2836 .Case("rdrnd", HasRDRND) 2837 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2838 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2839 .Case("mmx", MMX3DNowLevel >= MMX) 2840 .Case("pclmul", HasPCLMUL) 2841 .Case("popcnt", HasPOPCNT) 2842 .Case("rtm", HasRTM) 2843 .Case("prfchw", HasPRFCHW) 2844 .Case("rdseed", HasRDSEED) 2845 .Case("sha", HasSHA) 2846 .Case("sse", SSELevel >= SSE1) 2847 .Case("sse2", SSELevel >= SSE2) 2848 .Case("sse3", SSELevel >= SSE3) 2849 .Case("ssse3", SSELevel >= SSSE3) 2850 .Case("sse4.1", SSELevel >= SSE41) 2851 .Case("sse4.2", SSELevel >= SSE42) 2852 .Case("sse4a", XOPLevel >= SSE4A) 2853 .Case("x86", true) 2854 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2855 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2856 .Case("xop", XOPLevel >= XOP) 2857 .Default(false); 2858 } 2859 2860 bool 2861 X86TargetInfo::validateAsmConstraint(const char *&Name, 2862 TargetInfo::ConstraintInfo &Info) const { 2863 switch (*Name) { 2864 default: return false; 2865 case 'Y': // first letter of a pair: 2866 switch (*(Name+1)) { 2867 default: return false; 2868 case '0': // First SSE register. 2869 case 't': // Any SSE register, when SSE2 is enabled. 2870 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2871 case 'm': // any MMX register, when inter-unit moves enabled. 2872 break; // falls through to setAllowsRegister. 2873 } 2874 case 'a': // eax. 2875 case 'b': // ebx. 2876 case 'c': // ecx. 2877 case 'd': // edx. 2878 case 'S': // esi. 2879 case 'D': // edi. 2880 case 'A': // edx:eax. 2881 case 'f': // any x87 floating point stack register. 2882 case 't': // top of floating point stack. 2883 case 'u': // second from top of floating point stack. 2884 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2885 case 'y': // Any MMX register. 2886 case 'x': // Any SSE register. 2887 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2888 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2889 case 'l': // "Index" registers: any general register that can be used as an 2890 // index in a base+index memory access. 2891 Info.setAllowsRegister(); 2892 return true; 2893 case 'C': // SSE floating point constant. 2894 case 'G': // x87 floating point constant. 2895 case 'e': // 32-bit signed integer constant for use with zero-extending 2896 // x86_64 instructions. 2897 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2898 // x86_64 instructions. 2899 return true; 2900 } 2901 } 2902 2903 2904 std::string 2905 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2906 switch (*Constraint) { 2907 case 'a': return std::string("{ax}"); 2908 case 'b': return std::string("{bx}"); 2909 case 'c': return std::string("{cx}"); 2910 case 'd': return std::string("{dx}"); 2911 case 'S': return std::string("{si}"); 2912 case 'D': return std::string("{di}"); 2913 case 'p': // address 2914 return std::string("im"); 2915 case 't': // top of floating point stack. 2916 return std::string("{st}"); 2917 case 'u': // second from top of floating point stack. 2918 return std::string("{st(1)}"); // second from top of floating point stack. 2919 default: 2920 return std::string(1, *Constraint); 2921 } 2922 } 2923 } // end anonymous namespace 2924 2925 namespace { 2926 // X86-32 generic target 2927 class X86_32TargetInfo : public X86TargetInfo { 2928 public: 2929 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2930 DoubleAlign = LongLongAlign = 32; 2931 LongDoubleWidth = 96; 2932 LongDoubleAlign = 32; 2933 SuitableAlign = 128; 2934 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2935 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2936 "a0:0:64-f80:32:32-n8:16:32-S128"; 2937 SizeType = UnsignedInt; 2938 PtrDiffType = SignedInt; 2939 IntPtrType = SignedInt; 2940 RegParmMax = 3; 2941 2942 // Use fpret for all types. 2943 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2944 (1 << TargetInfo::Double) | 2945 (1 << TargetInfo::LongDouble)); 2946 2947 // x86-32 has atomics up to 8 bytes 2948 // FIXME: Check that we actually have cmpxchg8b before setting 2949 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2950 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2951 } 2952 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2953 return TargetInfo::CharPtrBuiltinVaList; 2954 } 2955 2956 int getEHDataRegisterNumber(unsigned RegNo) const { 2957 if (RegNo == 0) return 0; 2958 if (RegNo == 1) return 2; 2959 return -1; 2960 } 2961 virtual bool validateInputSize(StringRef Constraint, 2962 unsigned Size) const { 2963 switch (Constraint[0]) { 2964 default: break; 2965 case 'a': 2966 case 'b': 2967 case 'c': 2968 case 'd': 2969 return Size <= 32; 2970 } 2971 2972 return true; 2973 } 2974 }; 2975 } // end anonymous namespace 2976 2977 namespace { 2978 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2979 public: 2980 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2981 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2982 2983 virtual unsigned getFloatEvalMethod() const { 2984 // NetBSD defaults to "double" rounding 2985 return 1; 2986 } 2987 }; 2988 } // end anonymous namespace 2989 2990 namespace { 2991 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2992 public: 2993 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2994 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2995 SizeType = UnsignedLong; 2996 IntPtrType = SignedLong; 2997 PtrDiffType = SignedLong; 2998 } 2999 }; 3000 } // end anonymous namespace 3001 3002 namespace { 3003 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3004 public: 3005 BitrigI386TargetInfo(const llvm::Triple &Triple) 3006 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3007 SizeType = UnsignedLong; 3008 IntPtrType = SignedLong; 3009 PtrDiffType = SignedLong; 3010 } 3011 }; 3012 } // end anonymous namespace 3013 3014 namespace { 3015 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3016 public: 3017 DarwinI386TargetInfo(const llvm::Triple &Triple) 3018 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3019 LongDoubleWidth = 128; 3020 LongDoubleAlign = 128; 3021 SuitableAlign = 128; 3022 MaxVectorAlign = 256; 3023 SizeType = UnsignedLong; 3024 IntPtrType = SignedLong; 3025 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3026 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 3027 "a0:0:64-f80:128:128-n8:16:32-S128"; 3028 HasAlignMac68kSupport = true; 3029 } 3030 3031 }; 3032 } // end anonymous namespace 3033 3034 namespace { 3035 // x86-32 Windows target 3036 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3037 public: 3038 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3039 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3040 TLSSupported = false; 3041 WCharType = UnsignedShort; 3042 DoubleAlign = LongLongAlign = 64; 3043 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3044 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 3045 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 3046 } 3047 virtual void getTargetDefines(const LangOptions &Opts, 3048 MacroBuilder &Builder) const { 3049 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3050 } 3051 }; 3052 } // end anonymous namespace 3053 3054 namespace { 3055 3056 // x86-32 Windows Visual Studio target 3057 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3058 public: 3059 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3060 : WindowsX86_32TargetInfo(Triple) { 3061 LongDoubleWidth = LongDoubleAlign = 64; 3062 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3063 } 3064 virtual void getTargetDefines(const LangOptions &Opts, 3065 MacroBuilder &Builder) const { 3066 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3067 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3068 // The value of the following reflects processor type. 3069 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3070 // We lost the original triple, so we use the default. 3071 Builder.defineMacro("_M_IX86", "600"); 3072 } 3073 }; 3074 } // end anonymous namespace 3075 3076 namespace { 3077 // x86-32 MinGW target 3078 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3079 public: 3080 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3081 : WindowsX86_32TargetInfo(Triple) {} 3082 virtual void getTargetDefines(const LangOptions &Opts, 3083 MacroBuilder &Builder) const { 3084 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3085 DefineStd(Builder, "WIN32", Opts); 3086 DefineStd(Builder, "WINNT", Opts); 3087 Builder.defineMacro("_X86_"); 3088 Builder.defineMacro("__MSVCRT__"); 3089 Builder.defineMacro("__MINGW32__"); 3090 3091 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3092 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3093 if (Opts.MicrosoftExt) 3094 // Provide "as-is" __declspec. 3095 Builder.defineMacro("__declspec", "__declspec"); 3096 else 3097 // Provide alias of __attribute__ like mingw32-gcc. 3098 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3099 } 3100 }; 3101 } // end anonymous namespace 3102 3103 namespace { 3104 // x86-32 Cygwin target 3105 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3106 public: 3107 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3108 : X86_32TargetInfo(Triple) { 3109 TLSSupported = false; 3110 WCharType = UnsignedShort; 3111 DoubleAlign = LongLongAlign = 64; 3112 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3113 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3114 "a0:0:64-f80:32:32-n8:16:32-S32"; 3115 } 3116 virtual void getTargetDefines(const LangOptions &Opts, 3117 MacroBuilder &Builder) const { 3118 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3119 Builder.defineMacro("_X86_"); 3120 Builder.defineMacro("__CYGWIN__"); 3121 Builder.defineMacro("__CYGWIN32__"); 3122 DefineStd(Builder, "unix", Opts); 3123 if (Opts.CPlusPlus) 3124 Builder.defineMacro("_GNU_SOURCE"); 3125 } 3126 }; 3127 } // end anonymous namespace 3128 3129 namespace { 3130 // x86-32 Haiku target 3131 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3132 public: 3133 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3134 SizeType = UnsignedLong; 3135 IntPtrType = SignedLong; 3136 PtrDiffType = SignedLong; 3137 ProcessIDType = SignedLong; 3138 this->UserLabelPrefix = ""; 3139 this->TLSSupported = false; 3140 } 3141 virtual void getTargetDefines(const LangOptions &Opts, 3142 MacroBuilder &Builder) const { 3143 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3144 Builder.defineMacro("__INTEL__"); 3145 Builder.defineMacro("__HAIKU__"); 3146 } 3147 }; 3148 } // end anonymous namespace 3149 3150 // RTEMS Target 3151 template<typename Target> 3152 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3153 protected: 3154 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3155 MacroBuilder &Builder) const { 3156 // RTEMS defines; list based off of gcc output 3157 3158 Builder.defineMacro("__rtems__"); 3159 Builder.defineMacro("__ELF__"); 3160 } 3161 3162 public: 3163 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3164 this->UserLabelPrefix = ""; 3165 3166 switch (Triple.getArch()) { 3167 default: 3168 case llvm::Triple::x86: 3169 // this->MCountName = ".mcount"; 3170 break; 3171 case llvm::Triple::mips: 3172 case llvm::Triple::mipsel: 3173 case llvm::Triple::ppc: 3174 case llvm::Triple::ppc64: 3175 case llvm::Triple::ppc64le: 3176 // this->MCountName = "_mcount"; 3177 break; 3178 case llvm::Triple::arm: 3179 // this->MCountName = "__mcount"; 3180 break; 3181 } 3182 } 3183 }; 3184 3185 namespace { 3186 // x86-32 RTEMS target 3187 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3188 public: 3189 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3190 SizeType = UnsignedLong; 3191 IntPtrType = SignedLong; 3192 PtrDiffType = SignedLong; 3193 this->UserLabelPrefix = ""; 3194 } 3195 virtual void getTargetDefines(const LangOptions &Opts, 3196 MacroBuilder &Builder) const { 3197 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3198 Builder.defineMacro("__INTEL__"); 3199 Builder.defineMacro("__rtems__"); 3200 } 3201 }; 3202 } // end anonymous namespace 3203 3204 namespace { 3205 // x86-64 generic target 3206 class X86_64TargetInfo : public X86TargetInfo { 3207 public: 3208 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3209 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3210 LongDoubleWidth = 128; 3211 LongDoubleAlign = 128; 3212 LargeArrayMinWidth = 128; 3213 LargeArrayAlign = 128; 3214 SuitableAlign = 128; 3215 IntMaxType = SignedLong; 3216 UIntMaxType = UnsignedLong; 3217 Int64Type = SignedLong; 3218 RegParmMax = 6; 3219 3220 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3221 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3222 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3223 3224 // Use fpret only for long double. 3225 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3226 3227 // Use fp2ret for _Complex long double. 3228 ComplexLongDoubleUsesFP2Ret = true; 3229 3230 // x86-64 has atomics up to 16 bytes. 3231 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3232 // on CPUs with cmpxchg16b 3233 MaxAtomicPromoteWidth = 128; 3234 MaxAtomicInlineWidth = 64; 3235 } 3236 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3237 return TargetInfo::X86_64ABIBuiltinVaList; 3238 } 3239 3240 int getEHDataRegisterNumber(unsigned RegNo) const { 3241 if (RegNo == 0) return 0; 3242 if (RegNo == 1) return 1; 3243 return -1; 3244 } 3245 3246 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3247 return (CC == CC_C || 3248 CC == CC_IntelOclBicc || 3249 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3250 } 3251 3252 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3253 return CC_C; 3254 } 3255 3256 }; 3257 } // end anonymous namespace 3258 3259 namespace { 3260 // x86-64 Windows target 3261 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3262 public: 3263 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3264 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3265 TLSSupported = false; 3266 WCharType = UnsignedShort; 3267 LongWidth = LongAlign = 32; 3268 DoubleAlign = LongLongAlign = 64; 3269 IntMaxType = SignedLongLong; 3270 UIntMaxType = UnsignedLongLong; 3271 Int64Type = SignedLongLong; 3272 SizeType = UnsignedLongLong; 3273 PtrDiffType = SignedLongLong; 3274 IntPtrType = SignedLongLong; 3275 this->UserLabelPrefix = ""; 3276 } 3277 virtual void getTargetDefines(const LangOptions &Opts, 3278 MacroBuilder &Builder) const { 3279 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3280 Builder.defineMacro("_WIN64"); 3281 } 3282 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3283 return TargetInfo::CharPtrBuiltinVaList; 3284 } 3285 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3286 return (CC == CC_C || 3287 CC == CC_IntelOclBicc || 3288 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3289 } 3290 }; 3291 } // end anonymous namespace 3292 3293 namespace { 3294 // x86-64 Windows Visual Studio target 3295 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3296 public: 3297 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3298 : WindowsX86_64TargetInfo(Triple) { 3299 LongDoubleWidth = LongDoubleAlign = 64; 3300 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3301 } 3302 virtual void getTargetDefines(const LangOptions &Opts, 3303 MacroBuilder &Builder) const { 3304 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3305 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3306 Builder.defineMacro("_M_X64"); 3307 Builder.defineMacro("_M_AMD64"); 3308 } 3309 }; 3310 } // end anonymous namespace 3311 3312 namespace { 3313 // x86-64 MinGW target 3314 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3315 public: 3316 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3317 : WindowsX86_64TargetInfo(Triple) {} 3318 virtual void getTargetDefines(const LangOptions &Opts, 3319 MacroBuilder &Builder) const { 3320 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3321 DefineStd(Builder, "WIN64", Opts); 3322 Builder.defineMacro("__MSVCRT__"); 3323 Builder.defineMacro("__MINGW32__"); 3324 Builder.defineMacro("__MINGW64__"); 3325 3326 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3327 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3328 if (Opts.MicrosoftExt) 3329 // Provide "as-is" __declspec. 3330 Builder.defineMacro("__declspec", "__declspec"); 3331 else 3332 // Provide alias of __attribute__ like mingw32-gcc. 3333 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3334 } 3335 }; 3336 } // end anonymous namespace 3337 3338 namespace { 3339 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3340 public: 3341 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3342 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3343 Int64Type = SignedLongLong; 3344 MaxVectorAlign = 256; 3345 } 3346 }; 3347 } // end anonymous namespace 3348 3349 namespace { 3350 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3351 public: 3352 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3353 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3354 IntMaxType = SignedLongLong; 3355 UIntMaxType = UnsignedLongLong; 3356 Int64Type = SignedLongLong; 3357 } 3358 }; 3359 } // end anonymous namespace 3360 3361 namespace { 3362 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3363 public: 3364 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3365 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3366 IntMaxType = SignedLongLong; 3367 UIntMaxType = UnsignedLongLong; 3368 Int64Type = SignedLongLong; 3369 } 3370 }; 3371 } 3372 3373 namespace { 3374 class AArch64TargetInfo : public TargetInfo { 3375 static const char * const GCCRegNames[]; 3376 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3377 3378 enum FPUModeEnum { 3379 FPUMode, 3380 NeonMode 3381 }; 3382 3383 unsigned FPU; 3384 static const Builtin::Info BuiltinInfo[]; 3385 3386 public: 3387 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3388 BigEndian = false; 3389 LongWidth = LongAlign = 64; 3390 LongDoubleWidth = LongDoubleAlign = 128; 3391 PointerWidth = PointerAlign = 64; 3392 SuitableAlign = 128; 3393 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3394 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3395 "f128:128:128-n32:64-S128"; 3396 3397 WCharType = UnsignedInt; 3398 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3399 3400 // AArch64 backend supports 64-bit operations at the moment. In principle 3401 // 128-bit is possible if register-pairs are used. 3402 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3403 3404 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3405 } 3406 virtual void getTargetDefines(const LangOptions &Opts, 3407 MacroBuilder &Builder) const { 3408 // GCC defines theses currently 3409 Builder.defineMacro("__aarch64__"); 3410 Builder.defineMacro("__AARCH64EL__"); 3411 3412 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3413 3414 // FIXME: these were written based on an unreleased version of a 32-bit ACLE 3415 // which was intended to be compatible with a 64-bit implementation. They 3416 // will need updating when a real 64-bit ACLE exists. Particularly pressing 3417 // instances are: __ARM_ARCH_ISA_ARM, __ARM_ARCH_ISA_THUMB, __ARM_PCS. 3418 Builder.defineMacro("__ARM_ACLE", "101"); 3419 Builder.defineMacro("__ARM_ARCH", "8"); 3420 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3421 3422 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3423 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3424 Builder.defineMacro("__ARM_FEATURE_FMA"); 3425 3426 // FIXME: ACLE 1.1 reserves bit 4. Will almost certainly come to mean 3427 // 128-bit LDXP present, at which point this becomes 0x1f. 3428 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xf"); 3429 3430 // 0xe implies support for half, single and double precision operations. 3431 Builder.defineMacro("__ARM_FP", "0xe"); 3432 3433 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3434 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3435 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3436 3437 if (Opts.FastMath || Opts.FiniteMathOnly) 3438 Builder.defineMacro("__ARM_FP_FAST"); 3439 3440 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3441 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3442 3443 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3444 Opts.ShortWChar ? "2" : "4"); 3445 3446 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3447 Opts.ShortEnums ? "1" : "4"); 3448 3449 if (BigEndian) 3450 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3451 3452 if (FPU == NeonMode) { 3453 Builder.defineMacro("__AARCH_FEATURE_ADVSIMD"); 3454 3455 // 64-bit NEON supports half, single and double precision operations. 3456 Builder.defineMacro("__AARCH_ADVSIMD_FP", "0xe"); 3457 } 3458 } 3459 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3460 unsigned &NumRecords) const { 3461 Records = BuiltinInfo; 3462 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3463 } 3464 virtual bool hasFeature(StringRef Feature) const { 3465 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3466 } 3467 3468 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3469 DiagnosticsEngine &Diags) { 3470 FPU = FPUMode; 3471 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3472 if (Features[i] == "+neon") 3473 FPU = NeonMode; 3474 } 3475 return true; 3476 } 3477 3478 virtual void getGCCRegNames(const char *const *&Names, 3479 unsigned &NumNames) const; 3480 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3481 unsigned &NumAliases) const; 3482 3483 virtual bool isCLZForZeroUndef() const { return false; } 3484 3485 virtual bool validateAsmConstraint(const char *&Name, 3486 TargetInfo::ConstraintInfo &Info) const { 3487 switch (*Name) { 3488 default: return false; 3489 case 'w': // An FP/SIMD vector register 3490 Info.setAllowsRegister(); 3491 return true; 3492 case 'I': // Constant that can be used with an ADD instruction 3493 case 'J': // Constant that can be used with a SUB instruction 3494 case 'K': // Constant that can be used with a 32-bit logical instruction 3495 case 'L': // Constant that can be used with a 64-bit logical instruction 3496 case 'M': // Constant that can be used as a 32-bit MOV immediate 3497 case 'N': // Constant that can be used as a 64-bit MOV immediate 3498 case 'Y': // Floating point constant zero 3499 case 'Z': // Integer constant zero 3500 return true; 3501 case 'Q': // A memory reference with base register and no offset 3502 Info.setAllowsMemory(); 3503 return true; 3504 case 'S': // A symbolic address 3505 Info.setAllowsRegister(); 3506 return true; 3507 case 'U': 3508 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3509 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3510 // Usa: An absolute symbolic address 3511 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3512 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3513 } 3514 } 3515 3516 virtual const char *getClobbers() const { 3517 // There are no AArch64 clobbers shared by all asm statements. 3518 return ""; 3519 } 3520 3521 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3522 return TargetInfo::AArch64ABIBuiltinVaList; 3523 } 3524 }; 3525 3526 const char * const AArch64TargetInfo::GCCRegNames[] = { 3527 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3528 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3529 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3530 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3531 3532 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3533 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3534 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3535 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3536 3537 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3538 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3539 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3540 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3541 3542 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3543 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3544 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3545 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3546 3547 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3548 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3549 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3550 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3551 3552 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3553 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3554 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3555 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3556 3557 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3558 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3559 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3560 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3561 }; 3562 3563 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3564 unsigned &NumNames) const { 3565 Names = GCCRegNames; 3566 NumNames = llvm::array_lengthof(GCCRegNames); 3567 } 3568 3569 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3570 { { "x16" }, "ip0"}, 3571 { { "x17" }, "ip1"}, 3572 { { "x29" }, "fp" }, 3573 { { "x30" }, "lr" } 3574 }; 3575 3576 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3577 unsigned &NumAliases) const { 3578 Aliases = GCCRegAliases; 3579 NumAliases = llvm::array_lengthof(GCCRegAliases); 3580 3581 } 3582 3583 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3584 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3585 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3586 ALL_LANGUAGES }, 3587 #include "clang/Basic/BuiltinsAArch64.def" 3588 }; 3589 3590 } // end anonymous namespace 3591 3592 namespace { 3593 class ARMTargetInfo : public TargetInfo { 3594 // Possible FPU choices. 3595 enum FPUMode { 3596 VFP2FPU = (1 << 0), 3597 VFP3FPU = (1 << 1), 3598 VFP4FPU = (1 << 2), 3599 NeonFPU = (1 << 3) 3600 }; 3601 3602 // Possible HWDiv features. 3603 enum HWDivMode { 3604 HWDivThumb = (1 << 0), 3605 HWDivARM = (1 << 1) 3606 }; 3607 3608 static bool FPUModeIsVFP(FPUMode Mode) { 3609 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3610 } 3611 3612 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3613 static const char * const GCCRegNames[]; 3614 3615 std::string ABI, CPU; 3616 3617 enum { 3618 FP_Default, 3619 FP_VFP, 3620 FP_Neon 3621 } FPMath; 3622 3623 unsigned FPU : 4; 3624 3625 unsigned IsAAPCS : 1; 3626 unsigned IsThumb : 1; 3627 unsigned HWDiv : 2; 3628 3629 // Initialized via features. 3630 unsigned SoftFloat : 1; 3631 unsigned SoftFloatABI : 1; 3632 3633 static const Builtin::Info BuiltinInfo[]; 3634 3635 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3636 // On linux, binaries targeting old cpus call functions in libgcc to 3637 // perform atomic operations. The implementation in libgcc then calls into 3638 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3639 // is that if we assume the kernel is at least as recent as the hardware, 3640 // it is safe to use atomic instructions on armv6 and newer. 3641 if (!T.isOSLinux() && 3642 T.getOS() != llvm::Triple::FreeBSD && 3643 T.getOS() != llvm::Triple::Bitrig) 3644 return false; 3645 StringRef ArchName = T.getArchName(); 3646 if (T.getArch() == llvm::Triple::arm) { 3647 if (!ArchName.startswith("armv")) 3648 return false; 3649 StringRef VersionStr = ArchName.substr(4); 3650 unsigned Version; 3651 if (VersionStr.getAsInteger(10, Version)) 3652 return false; 3653 return Version >= 6; 3654 } 3655 assert(T.getArch() == llvm::Triple::thumb); 3656 if (!ArchName.startswith("thumbv")) 3657 return false; 3658 StringRef VersionStr = ArchName.substr(6); 3659 unsigned Version; 3660 if (VersionStr.getAsInteger(10, Version)) 3661 return false; 3662 return Version >= 7; 3663 } 3664 3665 public: 3666 ARMTargetInfo(const llvm::Triple &Triple) 3667 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3668 FPMath(FP_Default), IsAAPCS(true) { 3669 BigEndian = false; 3670 SizeType = UnsignedInt; 3671 PtrDiffType = SignedInt; 3672 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3673 WCharType = UnsignedInt; 3674 3675 // {} in inline assembly are neon specifiers, not assembly variant 3676 // specifiers. 3677 NoAsmVariants = true; 3678 3679 // FIXME: Should we just treat this as a feature? 3680 IsThumb = getTriple().getArchName().startswith("thumb"); 3681 if (IsThumb) { 3682 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3683 // so set preferred for small types to 32. 3684 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3685 "i64:64:64-f32:32:32-f64:64:64-" 3686 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3687 } else { 3688 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3689 "i64:64:64-f32:32:32-f64:64:64-" 3690 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3691 } 3692 3693 // ARM targets default to using the ARM C++ ABI. 3694 TheCXXABI.set(TargetCXXABI::GenericARM); 3695 3696 // ARM has atomics up to 8 bytes 3697 MaxAtomicPromoteWidth = 64; 3698 if (shouldUseInlineAtomic(getTriple())) 3699 MaxAtomicInlineWidth = 64; 3700 3701 // Do force alignment of members that follow zero length bitfields. If 3702 // the alignment of the zero-length bitfield is greater than the member 3703 // that follows it, `bar', `bar' will be aligned as the type of the 3704 // zero length bitfield. 3705 UseZeroLengthBitfieldAlignment = true; 3706 } 3707 virtual const char *getABI() const { return ABI.c_str(); } 3708 virtual bool setABI(const std::string &Name) { 3709 ABI = Name; 3710 3711 // The defaults (above) are for AAPCS, check if we need to change them. 3712 // 3713 // FIXME: We need support for -meabi... we could just mangle it into the 3714 // name. 3715 if (Name == "apcs-gnu") { 3716 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3717 // size_t is unsigned int on FreeBSD. 3718 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3719 SizeType = UnsignedLong; 3720 3721 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3722 WCharType = SignedInt; 3723 3724 // Do not respect the alignment of bit-field types when laying out 3725 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3726 UseBitFieldTypeAlignment = false; 3727 3728 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3729 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3730 /// gcc. 3731 ZeroLengthBitfieldBoundary = 32; 3732 3733 IsAAPCS = false; 3734 3735 if (IsThumb) { 3736 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3737 // so set preferred for small types to 32. 3738 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3739 "i64:32:64-f32:32:32-f64:32:64-" 3740 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3741 } else { 3742 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3743 "i64:32:64-f32:32:32-f64:32:64-" 3744 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3745 } 3746 3747 // FIXME: Override "preferred align" for double and long long. 3748 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3749 // size_t is unsigned long on Darwin. 3750 if (getTriple().isOSDarwin()) 3751 SizeType = UnsignedLong; 3752 IsAAPCS = true; 3753 // FIXME: Enumerated types are variable width in straight AAPCS. 3754 } else if (Name == "aapcs-linux") { 3755 IsAAPCS = true; 3756 } else 3757 return false; 3758 3759 return true; 3760 } 3761 3762 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3763 StringRef ArchName = getTriple().getArchName(); 3764 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3765 Features["vfp2"] = true; 3766 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3767 CPU == "cortex-a9-mp") { 3768 Features["vfp3"] = true; 3769 Features["neon"] = true; 3770 } 3771 else if (CPU == "cortex-a5") { 3772 Features["vfp4"] = true; 3773 Features["neon"] = true; 3774 } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") { 3775 Features["vfp4"] = true; 3776 Features["neon"] = true; 3777 Features["hwdiv"] = true; 3778 Features["hwdiv-arm"] = true; 3779 } else if (CPU == "cortex-r5" || CPU == "cortex-a53"|| 3780 CPU == "cortex-a57" || CPU == "cortex-m3" || 3781 CPU == "cortex-m4" || 3782 // Enable the hwdiv extension for all v8a AArch32 cores by 3783 // default. 3784 ArchName == "armv8a" || ArchName == "armv8" || 3785 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3786 Features["hwdiv"] = true; 3787 Features["hwdiv-arm"] = true; 3788 } 3789 } 3790 3791 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3792 DiagnosticsEngine &Diags) { 3793 FPU = 0; 3794 SoftFloat = SoftFloatABI = false; 3795 HWDiv = 0; 3796 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3797 if (Features[i] == "+soft-float") 3798 SoftFloat = true; 3799 else if (Features[i] == "+soft-float-abi") 3800 SoftFloatABI = true; 3801 else if (Features[i] == "+vfp2") 3802 FPU |= VFP2FPU; 3803 else if (Features[i] == "+vfp3") 3804 FPU |= VFP3FPU; 3805 else if (Features[i] == "+vfp4") 3806 FPU |= VFP4FPU; 3807 else if (Features[i] == "+neon") 3808 FPU |= NeonFPU; 3809 else if (Features[i] == "+hwdiv") 3810 HWDiv |= HWDivThumb; 3811 else if (Features[i] == "+hwdiv-arm") 3812 HWDiv |= HWDivARM; 3813 } 3814 3815 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3816 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3817 return false; 3818 } 3819 3820 if (FPMath == FP_Neon) 3821 Features.push_back("+neonfp"); 3822 else if (FPMath == FP_VFP) 3823 Features.push_back("-neonfp"); 3824 3825 // Remove front-end specific options which the backend handles differently. 3826 std::vector<std::string>::iterator it; 3827 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3828 if (it != Features.end()) 3829 Features.erase(it); 3830 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3831 if (it != Features.end()) 3832 Features.erase(it); 3833 return true; 3834 } 3835 3836 virtual bool hasFeature(StringRef Feature) const { 3837 return llvm::StringSwitch<bool>(Feature) 3838 .Case("arm", true) 3839 .Case("softfloat", SoftFloat) 3840 .Case("thumb", IsThumb) 3841 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3842 .Case("hwdiv", HWDiv & HWDivThumb) 3843 .Case("hwdiv-arm", HWDiv & HWDivARM) 3844 .Default(false); 3845 } 3846 // FIXME: Should we actually have some table instead of these switches? 3847 static const char *getCPUDefineSuffix(StringRef Name) { 3848 return llvm::StringSwitch<const char*>(Name) 3849 .Cases("arm8", "arm810", "4") 3850 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3851 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3852 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3853 .Case("ep9312", "4T") 3854 .Cases("arm10tdmi", "arm1020t", "5T") 3855 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3856 .Case("arm926ej-s", "5TEJ") 3857 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3858 .Cases("xscale", "iwmmxt", "5TE") 3859 .Case("arm1136j-s", "6J") 3860 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3861 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3862 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3863 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3864 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A") 3865 .Cases("cortex-r4", "cortex-r5", "7R") 3866 .Case("cortex-a9-mp", "7F") 3867 .Case("swift", "7S") 3868 .Cases("cortex-m3", "cortex-m4", "7M") 3869 .Case("cortex-m0", "6M") 3870 .Case("cortex-a53", "8A") 3871 .Default(0); 3872 } 3873 static const char *getCPUProfile(StringRef Name) { 3874 return llvm::StringSwitch<const char*>(Name) 3875 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3876 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A") 3877 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3878 .Cases("cortex-r4", "cortex-r5", "R") 3879 .Default(""); 3880 } 3881 virtual bool setCPU(const std::string &Name) { 3882 if (!getCPUDefineSuffix(Name)) 3883 return false; 3884 3885 CPU = Name; 3886 return true; 3887 } 3888 virtual bool setFPMath(StringRef Name); 3889 virtual void getTargetDefines(const LangOptions &Opts, 3890 MacroBuilder &Builder) const { 3891 // Target identification. 3892 Builder.defineMacro("__arm"); 3893 Builder.defineMacro("__arm__"); 3894 3895 // Target properties. 3896 Builder.defineMacro("__ARMEL__"); 3897 Builder.defineMacro("__LITTLE_ENDIAN__"); 3898 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3899 3900 StringRef CPUArch = getCPUDefineSuffix(CPU); 3901 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3902 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3903 StringRef CPUProfile = getCPUProfile(CPU); 3904 if (!CPUProfile.empty()) 3905 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3906 3907 // Subtarget options. 3908 3909 // FIXME: It's more complicated than this and we don't really support 3910 // interworking. 3911 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3912 Builder.defineMacro("__THUMB_INTERWORK__"); 3913 3914 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3915 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3916 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3917 Builder.defineMacro("__ARM_EABI__"); 3918 Builder.defineMacro("__ARM_PCS", "1"); 3919 3920 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3921 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3922 } 3923 3924 if (SoftFloat) 3925 Builder.defineMacro("__SOFTFP__"); 3926 3927 if (CPU == "xscale") 3928 Builder.defineMacro("__XSCALE__"); 3929 3930 bool IsARMv7 = CPUArch.startswith("7"); 3931 if (IsThumb) { 3932 Builder.defineMacro("__THUMBEL__"); 3933 Builder.defineMacro("__thumb__"); 3934 if (CPUArch == "6T2" || IsARMv7) 3935 Builder.defineMacro("__thumb2__"); 3936 } 3937 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 3938 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 3939 3940 // Note, this is always on in gcc, even though it doesn't make sense. 3941 Builder.defineMacro("__APCS_32__"); 3942 3943 if (FPUModeIsVFP((FPUMode) FPU)) { 3944 Builder.defineMacro("__VFP_FP__"); 3945 if (FPU & VFP2FPU) 3946 Builder.defineMacro("__ARM_VFPV2__"); 3947 if (FPU & VFP3FPU) 3948 Builder.defineMacro("__ARM_VFPV3__"); 3949 if (FPU & VFP4FPU) 3950 Builder.defineMacro("__ARM_VFPV4__"); 3951 } 3952 3953 // This only gets set when Neon instructions are actually available, unlike 3954 // the VFP define, hence the soft float and arch check. This is subtly 3955 // different from gcc, we follow the intent which was that it should be set 3956 // when Neon instructions are actually available. 3957 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3958 Builder.defineMacro("__ARM_NEON__"); 3959 3960 if (CPUArch.startswith("8")) 3961 Builder.defineMacro("__ARM_FEATURE_CRC32"); 3962 3963 if (CPUArch[0] >= '6' && CPUArch != "6M") { 3964 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3965 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3966 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3967 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3968 } 3969 } 3970 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3971 unsigned &NumRecords) const { 3972 Records = BuiltinInfo; 3973 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3974 } 3975 virtual bool isCLZForZeroUndef() const { return false; } 3976 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3977 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3978 } 3979 virtual void getGCCRegNames(const char * const *&Names, 3980 unsigned &NumNames) const; 3981 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3982 unsigned &NumAliases) const; 3983 virtual bool validateAsmConstraint(const char *&Name, 3984 TargetInfo::ConstraintInfo &Info) const { 3985 switch (*Name) { 3986 default: break; 3987 case 'l': // r0-r7 3988 case 'h': // r8-r15 3989 case 'w': // VFP Floating point register single precision 3990 case 'P': // VFP Floating point register double precision 3991 Info.setAllowsRegister(); 3992 return true; 3993 case 'Q': // A memory address that is a single base register. 3994 Info.setAllowsMemory(); 3995 return true; 3996 case 'U': // a memory reference... 3997 switch (Name[1]) { 3998 case 'q': // ...ARMV4 ldrsb 3999 case 'v': // ...VFP load/store (reg+constant offset) 4000 case 'y': // ...iWMMXt load/store 4001 case 't': // address valid for load/store opaque types wider 4002 // than 128-bits 4003 case 'n': // valid address for Neon doubleword vector load/store 4004 case 'm': // valid address for Neon element and structure load/store 4005 case 's': // valid address for non-offset loads/stores of quad-word 4006 // values in four ARM registers 4007 Info.setAllowsMemory(); 4008 Name++; 4009 return true; 4010 } 4011 } 4012 return false; 4013 } 4014 virtual std::string convertConstraint(const char *&Constraint) const { 4015 std::string R; 4016 switch (*Constraint) { 4017 case 'U': // Two-character constraint; add "^" hint for later parsing. 4018 R = std::string("^") + std::string(Constraint, 2); 4019 Constraint++; 4020 break; 4021 case 'p': // 'p' should be translated to 'r' by default. 4022 R = std::string("r"); 4023 break; 4024 default: 4025 return std::string(1, *Constraint); 4026 } 4027 return R; 4028 } 4029 virtual bool validateConstraintModifier(StringRef Constraint, 4030 const char Modifier, 4031 unsigned Size) const { 4032 bool isOutput = (Constraint[0] == '='); 4033 bool isInOut = (Constraint[0] == '+'); 4034 4035 // Strip off constraint modifiers. 4036 while (Constraint[0] == '=' || 4037 Constraint[0] == '+' || 4038 Constraint[0] == '&') 4039 Constraint = Constraint.substr(1); 4040 4041 switch (Constraint[0]) { 4042 default: break; 4043 case 'r': { 4044 switch (Modifier) { 4045 default: 4046 return (isInOut || isOutput || Size <= 32); 4047 case 'q': 4048 // A register of size 32 cannot fit a vector type. 4049 return false; 4050 } 4051 } 4052 } 4053 4054 return true; 4055 } 4056 virtual const char *getClobbers() const { 4057 // FIXME: Is this really right? 4058 return ""; 4059 } 4060 4061 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4062 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4063 } 4064 4065 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4066 if (RegNo == 0) return 0; 4067 if (RegNo == 1) return 1; 4068 return -1; 4069 } 4070 }; 4071 4072 bool ARMTargetInfo::setFPMath(StringRef Name) { 4073 if (Name == "neon") { 4074 FPMath = FP_Neon; 4075 return true; 4076 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4077 Name == "vfp4") { 4078 FPMath = FP_VFP; 4079 return true; 4080 } 4081 return false; 4082 } 4083 4084 const char * const ARMTargetInfo::GCCRegNames[] = { 4085 // Integer registers 4086 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4087 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4088 4089 // Float registers 4090 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4091 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4092 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4093 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4094 4095 // Double registers 4096 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4097 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4098 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4099 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4100 4101 // Quad registers 4102 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4103 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4104 }; 4105 4106 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4107 unsigned &NumNames) const { 4108 Names = GCCRegNames; 4109 NumNames = llvm::array_lengthof(GCCRegNames); 4110 } 4111 4112 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4113 { { "a1" }, "r0" }, 4114 { { "a2" }, "r1" }, 4115 { { "a3" }, "r2" }, 4116 { { "a4" }, "r3" }, 4117 { { "v1" }, "r4" }, 4118 { { "v2" }, "r5" }, 4119 { { "v3" }, "r6" }, 4120 { { "v4" }, "r7" }, 4121 { { "v5" }, "r8" }, 4122 { { "v6", "rfp" }, "r9" }, 4123 { { "sl" }, "r10" }, 4124 { { "fp" }, "r11" }, 4125 { { "ip" }, "r12" }, 4126 { { "r13" }, "sp" }, 4127 { { "r14" }, "lr" }, 4128 { { "r15" }, "pc" }, 4129 // The S, D and Q registers overlap, but aren't really aliases; we 4130 // don't want to substitute one of these for a different-sized one. 4131 }; 4132 4133 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4134 unsigned &NumAliases) const { 4135 Aliases = GCCRegAliases; 4136 NumAliases = llvm::array_lengthof(GCCRegAliases); 4137 } 4138 4139 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4140 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4141 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4142 ALL_LANGUAGES }, 4143 #include "clang/Basic/BuiltinsARM.def" 4144 }; 4145 } // end anonymous namespace. 4146 4147 namespace { 4148 class DarwinARMTargetInfo : 4149 public DarwinTargetInfo<ARMTargetInfo> { 4150 protected: 4151 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4152 MacroBuilder &Builder) const { 4153 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4154 } 4155 4156 public: 4157 DarwinARMTargetInfo(const llvm::Triple &Triple) 4158 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4159 HasAlignMac68kSupport = true; 4160 // iOS always has 64-bit atomic instructions. 4161 // FIXME: This should be based off of the target features in ARMTargetInfo. 4162 MaxAtomicInlineWidth = 64; 4163 4164 // Darwin on iOS uses a variant of the ARM C++ ABI. 4165 TheCXXABI.set(TargetCXXABI::iOS); 4166 } 4167 }; 4168 } // end anonymous namespace. 4169 4170 4171 namespace { 4172 // Hexagon abstract base class 4173 class HexagonTargetInfo : public TargetInfo { 4174 static const Builtin::Info BuiltinInfo[]; 4175 static const char * const GCCRegNames[]; 4176 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4177 std::string CPU; 4178 public: 4179 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4180 BigEndian = false; 4181 DescriptionString = ("e-p:32:32:32-" 4182 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4183 "f64:64:64-f32:32:32-a0:0-n32"); 4184 4185 // {} in inline assembly are packet specifiers, not assembly variant 4186 // specifiers. 4187 NoAsmVariants = true; 4188 } 4189 4190 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4191 unsigned &NumRecords) const { 4192 Records = BuiltinInfo; 4193 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4194 } 4195 4196 virtual bool validateAsmConstraint(const char *&Name, 4197 TargetInfo::ConstraintInfo &Info) const { 4198 return true; 4199 } 4200 4201 virtual void getTargetDefines(const LangOptions &Opts, 4202 MacroBuilder &Builder) const; 4203 4204 virtual bool hasFeature(StringRef Feature) const { 4205 return Feature == "hexagon"; 4206 } 4207 4208 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4209 return TargetInfo::CharPtrBuiltinVaList; 4210 } 4211 virtual void getGCCRegNames(const char * const *&Names, 4212 unsigned &NumNames) const; 4213 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4214 unsigned &NumAliases) const; 4215 virtual const char *getClobbers() const { 4216 return ""; 4217 } 4218 4219 static const char *getHexagonCPUSuffix(StringRef Name) { 4220 return llvm::StringSwitch<const char*>(Name) 4221 .Case("hexagonv4", "4") 4222 .Case("hexagonv5", "5") 4223 .Default(0); 4224 } 4225 4226 virtual bool setCPU(const std::string &Name) { 4227 if (!getHexagonCPUSuffix(Name)) 4228 return false; 4229 4230 CPU = Name; 4231 return true; 4232 } 4233 }; 4234 4235 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4236 MacroBuilder &Builder) const { 4237 Builder.defineMacro("qdsp6"); 4238 Builder.defineMacro("__qdsp6", "1"); 4239 Builder.defineMacro("__qdsp6__", "1"); 4240 4241 Builder.defineMacro("hexagon"); 4242 Builder.defineMacro("__hexagon", "1"); 4243 Builder.defineMacro("__hexagon__", "1"); 4244 4245 if(CPU == "hexagonv1") { 4246 Builder.defineMacro("__HEXAGON_V1__"); 4247 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4248 if(Opts.HexagonQdsp6Compat) { 4249 Builder.defineMacro("__QDSP6_V1__"); 4250 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4251 } 4252 } 4253 else if(CPU == "hexagonv2") { 4254 Builder.defineMacro("__HEXAGON_V2__"); 4255 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4256 if(Opts.HexagonQdsp6Compat) { 4257 Builder.defineMacro("__QDSP6_V2__"); 4258 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4259 } 4260 } 4261 else if(CPU == "hexagonv3") { 4262 Builder.defineMacro("__HEXAGON_V3__"); 4263 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4264 if(Opts.HexagonQdsp6Compat) { 4265 Builder.defineMacro("__QDSP6_V3__"); 4266 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4267 } 4268 } 4269 else if(CPU == "hexagonv4") { 4270 Builder.defineMacro("__HEXAGON_V4__"); 4271 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4272 if(Opts.HexagonQdsp6Compat) { 4273 Builder.defineMacro("__QDSP6_V4__"); 4274 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4275 } 4276 } 4277 else if(CPU == "hexagonv5") { 4278 Builder.defineMacro("__HEXAGON_V5__"); 4279 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4280 if(Opts.HexagonQdsp6Compat) { 4281 Builder.defineMacro("__QDSP6_V5__"); 4282 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4283 } 4284 } 4285 } 4286 4287 const char * const HexagonTargetInfo::GCCRegNames[] = { 4288 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4289 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4290 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4291 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4292 "p0", "p1", "p2", "p3", 4293 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4294 }; 4295 4296 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4297 unsigned &NumNames) const { 4298 Names = GCCRegNames; 4299 NumNames = llvm::array_lengthof(GCCRegNames); 4300 } 4301 4302 4303 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4304 { { "sp" }, "r29" }, 4305 { { "fp" }, "r30" }, 4306 { { "lr" }, "r31" }, 4307 }; 4308 4309 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4310 unsigned &NumAliases) const { 4311 Aliases = GCCRegAliases; 4312 NumAliases = llvm::array_lengthof(GCCRegAliases); 4313 } 4314 4315 4316 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4317 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4318 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4319 ALL_LANGUAGES }, 4320 #include "clang/Basic/BuiltinsHexagon.def" 4321 }; 4322 } 4323 4324 4325 namespace { 4326 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4327 class SparcTargetInfo : public TargetInfo { 4328 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4329 static const char * const GCCRegNames[]; 4330 bool SoftFloat; 4331 public: 4332 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4333 4334 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4335 DiagnosticsEngine &Diags) { 4336 SoftFloat = false; 4337 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4338 if (Features[i] == "+soft-float") 4339 SoftFloat = true; 4340 return true; 4341 } 4342 virtual void getTargetDefines(const LangOptions &Opts, 4343 MacroBuilder &Builder) const { 4344 DefineStd(Builder, "sparc", Opts); 4345 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4346 4347 if (SoftFloat) 4348 Builder.defineMacro("SOFT_FLOAT", "1"); 4349 } 4350 4351 virtual bool hasFeature(StringRef Feature) const { 4352 return llvm::StringSwitch<bool>(Feature) 4353 .Case("softfloat", SoftFloat) 4354 .Case("sparc", true) 4355 .Default(false); 4356 } 4357 4358 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4359 unsigned &NumRecords) const { 4360 // FIXME: Implement! 4361 } 4362 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4363 return TargetInfo::VoidPtrBuiltinVaList; 4364 } 4365 virtual void getGCCRegNames(const char * const *&Names, 4366 unsigned &NumNames) const; 4367 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4368 unsigned &NumAliases) const; 4369 virtual bool validateAsmConstraint(const char *&Name, 4370 TargetInfo::ConstraintInfo &info) const { 4371 // FIXME: Implement! 4372 return false; 4373 } 4374 virtual const char *getClobbers() const { 4375 // FIXME: Implement! 4376 return ""; 4377 } 4378 }; 4379 4380 const char * const SparcTargetInfo::GCCRegNames[] = { 4381 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4382 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4383 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4384 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4385 }; 4386 4387 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4388 unsigned &NumNames) const { 4389 Names = GCCRegNames; 4390 NumNames = llvm::array_lengthof(GCCRegNames); 4391 } 4392 4393 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4394 { { "g0" }, "r0" }, 4395 { { "g1" }, "r1" }, 4396 { { "g2" }, "r2" }, 4397 { { "g3" }, "r3" }, 4398 { { "g4" }, "r4" }, 4399 { { "g5" }, "r5" }, 4400 { { "g6" }, "r6" }, 4401 { { "g7" }, "r7" }, 4402 { { "o0" }, "r8" }, 4403 { { "o1" }, "r9" }, 4404 { { "o2" }, "r10" }, 4405 { { "o3" }, "r11" }, 4406 { { "o4" }, "r12" }, 4407 { { "o5" }, "r13" }, 4408 { { "o6", "sp" }, "r14" }, 4409 { { "o7" }, "r15" }, 4410 { { "l0" }, "r16" }, 4411 { { "l1" }, "r17" }, 4412 { { "l2" }, "r18" }, 4413 { { "l3" }, "r19" }, 4414 { { "l4" }, "r20" }, 4415 { { "l5" }, "r21" }, 4416 { { "l6" }, "r22" }, 4417 { { "l7" }, "r23" }, 4418 { { "i0" }, "r24" }, 4419 { { "i1" }, "r25" }, 4420 { { "i2" }, "r26" }, 4421 { { "i3" }, "r27" }, 4422 { { "i4" }, "r28" }, 4423 { { "i5" }, "r29" }, 4424 { { "i6", "fp" }, "r30" }, 4425 { { "i7" }, "r31" }, 4426 }; 4427 4428 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4429 unsigned &NumAliases) const { 4430 Aliases = GCCRegAliases; 4431 NumAliases = llvm::array_lengthof(GCCRegAliases); 4432 } 4433 4434 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4435 class SparcV8TargetInfo : public SparcTargetInfo { 4436 public: 4437 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4438 // FIXME: Support Sparc quad-precision long double? 4439 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4440 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4441 } 4442 4443 virtual void getTargetDefines(const LangOptions &Opts, 4444 MacroBuilder &Builder) const { 4445 SparcTargetInfo::getTargetDefines(Opts, Builder); 4446 Builder.defineMacro("__sparcv8"); 4447 } 4448 }; 4449 4450 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4451 class SparcV9TargetInfo : public SparcTargetInfo { 4452 public: 4453 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4454 // FIXME: Support Sparc quad-precision long double? 4455 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4456 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4457 // This is an LP64 platform. 4458 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4459 4460 // OpenBSD uses long long for int64_t and intmax_t. 4461 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4462 IntMaxType = SignedLongLong; 4463 UIntMaxType = UnsignedLongLong; 4464 } else { 4465 IntMaxType = SignedLong; 4466 UIntMaxType = UnsignedLong; 4467 } 4468 Int64Type = IntMaxType; 4469 } 4470 4471 virtual void getTargetDefines(const LangOptions &Opts, 4472 MacroBuilder &Builder) const { 4473 SparcTargetInfo::getTargetDefines(Opts, Builder); 4474 Builder.defineMacro("__sparcv9"); 4475 Builder.defineMacro("__arch64__"); 4476 // Solaris and its derivative AuroraUX don't need these variants, but the 4477 // BSDs do. 4478 if (getTriple().getOS() != llvm::Triple::Solaris && 4479 getTriple().getOS() != llvm::Triple::AuroraUX) { 4480 Builder.defineMacro("__sparc64__"); 4481 Builder.defineMacro("__sparc_v9__"); 4482 Builder.defineMacro("__sparcv9__"); 4483 } 4484 } 4485 }; 4486 4487 } // end anonymous namespace. 4488 4489 namespace { 4490 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4491 public: 4492 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4493 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4494 SizeType = UnsignedInt; 4495 PtrDiffType = SignedInt; 4496 } 4497 }; 4498 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4499 public: 4500 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4501 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4502 SizeType = UnsignedInt; 4503 PtrDiffType = SignedInt; 4504 } 4505 }; 4506 } // end anonymous namespace. 4507 4508 namespace { 4509 class SystemZTargetInfo : public TargetInfo { 4510 static const char *const GCCRegNames[]; 4511 4512 public: 4513 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4514 TLSSupported = true; 4515 IntWidth = IntAlign = 32; 4516 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4517 PointerWidth = PointerAlign = 64; 4518 LongDoubleWidth = 128; 4519 LongDoubleAlign = 64; 4520 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4521 MinGlobalAlign = 16; 4522 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4523 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4524 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4525 } 4526 virtual void getTargetDefines(const LangOptions &Opts, 4527 MacroBuilder &Builder) const { 4528 Builder.defineMacro("__s390__"); 4529 Builder.defineMacro("__s390x__"); 4530 Builder.defineMacro("__zarch__"); 4531 Builder.defineMacro("__LONG_DOUBLE_128__"); 4532 } 4533 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4534 unsigned &NumRecords) const { 4535 // FIXME: Implement. 4536 Records = 0; 4537 NumRecords = 0; 4538 } 4539 4540 virtual void getGCCRegNames(const char *const *&Names, 4541 unsigned &NumNames) const; 4542 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4543 unsigned &NumAliases) const { 4544 // No aliases. 4545 Aliases = 0; 4546 NumAliases = 0; 4547 } 4548 virtual bool validateAsmConstraint(const char *&Name, 4549 TargetInfo::ConstraintInfo &info) const; 4550 virtual const char *getClobbers() const { 4551 // FIXME: Is this really right? 4552 return ""; 4553 } 4554 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4555 return TargetInfo::SystemZBuiltinVaList; 4556 } 4557 virtual bool setCPU(const std::string &Name) { 4558 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4559 .Case("z10", true) 4560 .Case("z196", true) 4561 .Case("zEC12", true) 4562 .Default(false); 4563 4564 // No need to store the CPU yet. There aren't any CPU-specific 4565 // macros to define. 4566 return CPUKnown; 4567 } 4568 }; 4569 4570 const char *const SystemZTargetInfo::GCCRegNames[] = { 4571 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4572 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4573 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4574 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4575 }; 4576 4577 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4578 unsigned &NumNames) const { 4579 Names = GCCRegNames; 4580 NumNames = llvm::array_lengthof(GCCRegNames); 4581 } 4582 4583 bool SystemZTargetInfo:: 4584 validateAsmConstraint(const char *&Name, 4585 TargetInfo::ConstraintInfo &Info) const { 4586 switch (*Name) { 4587 default: 4588 return false; 4589 4590 case 'a': // Address register 4591 case 'd': // Data register (equivalent to 'r') 4592 case 'f': // Floating-point register 4593 Info.setAllowsRegister(); 4594 return true; 4595 4596 case 'I': // Unsigned 8-bit constant 4597 case 'J': // Unsigned 12-bit constant 4598 case 'K': // Signed 16-bit constant 4599 case 'L': // Signed 20-bit displacement (on all targets we support) 4600 case 'M': // 0x7fffffff 4601 return true; 4602 4603 case 'Q': // Memory with base and unsigned 12-bit displacement 4604 case 'R': // Likewise, plus an index 4605 case 'S': // Memory with base and signed 20-bit displacement 4606 case 'T': // Likewise, plus an index 4607 Info.setAllowsMemory(); 4608 return true; 4609 } 4610 } 4611 } 4612 4613 namespace { 4614 class MSP430TargetInfo : public TargetInfo { 4615 static const char * const GCCRegNames[]; 4616 public: 4617 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4618 BigEndian = false; 4619 TLSSupported = false; 4620 IntWidth = 16; IntAlign = 16; 4621 LongWidth = 32; LongLongWidth = 64; 4622 LongAlign = LongLongAlign = 16; 4623 PointerWidth = 16; PointerAlign = 16; 4624 SuitableAlign = 16; 4625 SizeType = UnsignedInt; 4626 IntMaxType = SignedLongLong; 4627 UIntMaxType = UnsignedLongLong; 4628 IntPtrType = SignedInt; 4629 PtrDiffType = SignedInt; 4630 SigAtomicType = SignedLong; 4631 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4632 } 4633 virtual void getTargetDefines(const LangOptions &Opts, 4634 MacroBuilder &Builder) const { 4635 Builder.defineMacro("MSP430"); 4636 Builder.defineMacro("__MSP430__"); 4637 // FIXME: defines for different 'flavours' of MCU 4638 } 4639 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4640 unsigned &NumRecords) const { 4641 // FIXME: Implement. 4642 Records = 0; 4643 NumRecords = 0; 4644 } 4645 virtual bool hasFeature(StringRef Feature) const { 4646 return Feature == "msp430"; 4647 } 4648 virtual void getGCCRegNames(const char * const *&Names, 4649 unsigned &NumNames) const; 4650 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4651 unsigned &NumAliases) const { 4652 // No aliases. 4653 Aliases = 0; 4654 NumAliases = 0; 4655 } 4656 virtual bool validateAsmConstraint(const char *&Name, 4657 TargetInfo::ConstraintInfo &info) const { 4658 // No target constraints for now. 4659 return false; 4660 } 4661 virtual const char *getClobbers() const { 4662 // FIXME: Is this really right? 4663 return ""; 4664 } 4665 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4666 // FIXME: implement 4667 return TargetInfo::CharPtrBuiltinVaList; 4668 } 4669 }; 4670 4671 const char * const MSP430TargetInfo::GCCRegNames[] = { 4672 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4673 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4674 }; 4675 4676 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4677 unsigned &NumNames) const { 4678 Names = GCCRegNames; 4679 NumNames = llvm::array_lengthof(GCCRegNames); 4680 } 4681 } 4682 4683 namespace { 4684 4685 // LLVM and Clang cannot be used directly to output native binaries for 4686 // target, but is used to compile C code to llvm bitcode with correct 4687 // type and alignment information. 4688 // 4689 // TCE uses the llvm bitcode as input and uses it for generating customized 4690 // target processor and program binary. TCE co-design environment is 4691 // publicly available in http://tce.cs.tut.fi 4692 4693 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4694 3, // opencl_global 4695 4, // opencl_local 4696 5, // opencl_constant 4697 0, // cuda_device 4698 0, // cuda_constant 4699 0 // cuda_shared 4700 }; 4701 4702 class TCETargetInfo : public TargetInfo{ 4703 public: 4704 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4705 TLSSupported = false; 4706 IntWidth = 32; 4707 LongWidth = LongLongWidth = 32; 4708 PointerWidth = 32; 4709 IntAlign = 32; 4710 LongAlign = LongLongAlign = 32; 4711 PointerAlign = 32; 4712 SuitableAlign = 32; 4713 SizeType = UnsignedInt; 4714 IntMaxType = SignedLong; 4715 UIntMaxType = UnsignedLong; 4716 IntPtrType = SignedInt; 4717 PtrDiffType = SignedInt; 4718 FloatWidth = 32; 4719 FloatAlign = 32; 4720 DoubleWidth = 32; 4721 DoubleAlign = 32; 4722 LongDoubleWidth = 32; 4723 LongDoubleAlign = 32; 4724 FloatFormat = &llvm::APFloat::IEEEsingle; 4725 DoubleFormat = &llvm::APFloat::IEEEsingle; 4726 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4727 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4728 "i16:16:32-i32:32:32-i64:32:32-" 4729 "f32:32:32-f64:32:32-v64:32:32-" 4730 "v128:32:32-a0:0:32-n32"; 4731 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4732 UseAddrSpaceMapMangling = true; 4733 } 4734 4735 virtual void getTargetDefines(const LangOptions &Opts, 4736 MacroBuilder &Builder) const { 4737 DefineStd(Builder, "tce", Opts); 4738 Builder.defineMacro("__TCE__"); 4739 Builder.defineMacro("__TCE_V1__"); 4740 } 4741 virtual bool hasFeature(StringRef Feature) const { 4742 return Feature == "tce"; 4743 } 4744 4745 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4746 unsigned &NumRecords) const {} 4747 virtual const char *getClobbers() const { 4748 return ""; 4749 } 4750 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4751 return TargetInfo::VoidPtrBuiltinVaList; 4752 } 4753 virtual void getGCCRegNames(const char * const *&Names, 4754 unsigned &NumNames) const {} 4755 virtual bool validateAsmConstraint(const char *&Name, 4756 TargetInfo::ConstraintInfo &info) const { 4757 return true; 4758 } 4759 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4760 unsigned &NumAliases) const {} 4761 }; 4762 } 4763 4764 namespace { 4765 class MipsTargetInfoBase : public TargetInfo { 4766 static const Builtin::Info BuiltinInfo[]; 4767 std::string CPU; 4768 bool IsMips16; 4769 bool IsMicromips; 4770 bool IsNan2008; 4771 bool IsSingleFloat; 4772 enum MipsFloatABI { 4773 HardFloat, SoftFloat 4774 } FloatABI; 4775 enum DspRevEnum { 4776 NoDSP, DSP1, DSP2 4777 } DspRev; 4778 bool HasMSA; 4779 bool HasFP64; 4780 4781 protected: 4782 std::string ABI; 4783 4784 public: 4785 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4786 const std::string &CPUStr) 4787 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4788 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4789 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4790 4791 virtual const char *getABI() const { return ABI.c_str(); } 4792 virtual bool setABI(const std::string &Name) = 0; 4793 virtual bool setCPU(const std::string &Name) { 4794 CPU = Name; 4795 return true; 4796 } 4797 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4798 Features[ABI] = true; 4799 Features[CPU] = true; 4800 } 4801 4802 virtual void getTargetDefines(const LangOptions &Opts, 4803 MacroBuilder &Builder) const { 4804 DefineStd(Builder, "mips", Opts); 4805 Builder.defineMacro("_mips"); 4806 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4807 4808 switch (FloatABI) { 4809 case HardFloat: 4810 Builder.defineMacro("__mips_hard_float", Twine(1)); 4811 break; 4812 case SoftFloat: 4813 Builder.defineMacro("__mips_soft_float", Twine(1)); 4814 break; 4815 } 4816 4817 if (IsSingleFloat) 4818 Builder.defineMacro("__mips_single_float", Twine(1)); 4819 4820 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4821 Builder.defineMacro("_MIPS_FPSET", 4822 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4823 4824 if (IsMips16) 4825 Builder.defineMacro("__mips16", Twine(1)); 4826 4827 if (IsMicromips) 4828 Builder.defineMacro("__mips_micromips", Twine(1)); 4829 4830 if (IsNan2008) 4831 Builder.defineMacro("__mips_nan2008", Twine(1)); 4832 4833 switch (DspRev) { 4834 default: 4835 break; 4836 case DSP1: 4837 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4838 Builder.defineMacro("__mips_dsp", Twine(1)); 4839 break; 4840 case DSP2: 4841 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4842 Builder.defineMacro("__mips_dspr2", Twine(1)); 4843 Builder.defineMacro("__mips_dsp", Twine(1)); 4844 break; 4845 } 4846 4847 if (HasMSA) 4848 Builder.defineMacro("__mips_msa", Twine(1)); 4849 4850 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4851 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4852 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4853 4854 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4855 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4856 } 4857 4858 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4859 unsigned &NumRecords) const { 4860 Records = BuiltinInfo; 4861 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4862 } 4863 virtual bool hasFeature(StringRef Feature) const { 4864 return Feature == "mips"; 4865 } 4866 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4867 return TargetInfo::VoidPtrBuiltinVaList; 4868 } 4869 virtual void getGCCRegNames(const char * const *&Names, 4870 unsigned &NumNames) const { 4871 static const char * const GCCRegNames[] = { 4872 // CPU register names 4873 // Must match second column of GCCRegAliases 4874 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4875 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4876 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4877 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4878 // Floating point register names 4879 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4880 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4881 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4882 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4883 // Hi/lo and condition register names 4884 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4885 "$fcc5","$fcc6","$fcc7" 4886 }; 4887 Names = GCCRegNames; 4888 NumNames = llvm::array_lengthof(GCCRegNames); 4889 } 4890 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4891 unsigned &NumAliases) const = 0; 4892 virtual bool validateAsmConstraint(const char *&Name, 4893 TargetInfo::ConstraintInfo &Info) const { 4894 switch (*Name) { 4895 default: 4896 return false; 4897 4898 case 'r': // CPU registers. 4899 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4900 case 'y': // Equivalent to "r", backwards compatibility only. 4901 case 'f': // floating-point registers. 4902 case 'c': // $25 for indirect jumps 4903 case 'l': // lo register 4904 case 'x': // hilo register pair 4905 Info.setAllowsRegister(); 4906 return true; 4907 case 'R': // An address that can be used in a non-macro load or store 4908 Info.setAllowsMemory(); 4909 return true; 4910 } 4911 } 4912 4913 virtual const char *getClobbers() const { 4914 // FIXME: Implement! 4915 return ""; 4916 } 4917 4918 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4919 DiagnosticsEngine &Diags) { 4920 IsMips16 = false; 4921 IsMicromips = false; 4922 IsNan2008 = false; 4923 IsSingleFloat = false; 4924 FloatABI = HardFloat; 4925 DspRev = NoDSP; 4926 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 4927 4928 for (std::vector<std::string>::iterator it = Features.begin(), 4929 ie = Features.end(); it != ie; ++it) { 4930 if (*it == "+single-float") 4931 IsSingleFloat = true; 4932 else if (*it == "+soft-float") 4933 FloatABI = SoftFloat; 4934 else if (*it == "+mips16") 4935 IsMips16 = true; 4936 else if (*it == "+micromips") 4937 IsMicromips = true; 4938 else if (*it == "+dsp") 4939 DspRev = std::max(DspRev, DSP1); 4940 else if (*it == "+dspr2") 4941 DspRev = std::max(DspRev, DSP2); 4942 else if (*it == "+msa") 4943 HasMSA = true; 4944 else if (*it == "+fp64") 4945 HasFP64 = true; 4946 else if (*it == "-fp64") 4947 HasFP64 = false; 4948 else if (*it == "+nan2008") 4949 IsNan2008 = true; 4950 } 4951 4952 // Remove front-end specific options. 4953 std::vector<std::string>::iterator it = 4954 std::find(Features.begin(), Features.end(), "+soft-float"); 4955 if (it != Features.end()) 4956 Features.erase(it); 4957 it = std::find(Features.begin(), Features.end(), "+nan2008"); 4958 if (it != Features.end()) 4959 Features.erase(it); 4960 4961 return true; 4962 } 4963 4964 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4965 if (RegNo == 0) return 4; 4966 if (RegNo == 1) return 5; 4967 return -1; 4968 } 4969 }; 4970 4971 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4972 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4973 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4974 ALL_LANGUAGES }, 4975 #include "clang/Basic/BuiltinsMips.def" 4976 }; 4977 4978 class Mips32TargetInfoBase : public MipsTargetInfoBase { 4979 public: 4980 Mips32TargetInfoBase(const llvm::Triple &Triple) 4981 : MipsTargetInfoBase(Triple, "o32", "mips32") { 4982 SizeType = UnsignedInt; 4983 PtrDiffType = SignedInt; 4984 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 4985 } 4986 virtual bool setABI(const std::string &Name) { 4987 if ((Name == "o32") || (Name == "eabi")) { 4988 ABI = Name; 4989 return true; 4990 } else if (Name == "32") { 4991 ABI = "o32"; 4992 return true; 4993 } else 4994 return false; 4995 } 4996 virtual void getTargetDefines(const LangOptions &Opts, 4997 MacroBuilder &Builder) const { 4998 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4999 5000 if (ABI == "o32") { 5001 Builder.defineMacro("__mips_o32"); 5002 Builder.defineMacro("_ABIO32", "1"); 5003 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5004 } 5005 else if (ABI == "eabi") 5006 Builder.defineMacro("__mips_eabi"); 5007 else 5008 llvm_unreachable("Invalid ABI for Mips32."); 5009 } 5010 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5011 unsigned &NumAliases) const { 5012 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5013 { { "at" }, "$1" }, 5014 { { "v0" }, "$2" }, 5015 { { "v1" }, "$3" }, 5016 { { "a0" }, "$4" }, 5017 { { "a1" }, "$5" }, 5018 { { "a2" }, "$6" }, 5019 { { "a3" }, "$7" }, 5020 { { "t0" }, "$8" }, 5021 { { "t1" }, "$9" }, 5022 { { "t2" }, "$10" }, 5023 { { "t3" }, "$11" }, 5024 { { "t4" }, "$12" }, 5025 { { "t5" }, "$13" }, 5026 { { "t6" }, "$14" }, 5027 { { "t7" }, "$15" }, 5028 { { "s0" }, "$16" }, 5029 { { "s1" }, "$17" }, 5030 { { "s2" }, "$18" }, 5031 { { "s3" }, "$19" }, 5032 { { "s4" }, "$20" }, 5033 { { "s5" }, "$21" }, 5034 { { "s6" }, "$22" }, 5035 { { "s7" }, "$23" }, 5036 { { "t8" }, "$24" }, 5037 { { "t9" }, "$25" }, 5038 { { "k0" }, "$26" }, 5039 { { "k1" }, "$27" }, 5040 { { "gp" }, "$28" }, 5041 { { "sp","$sp" }, "$29" }, 5042 { { "fp","$fp" }, "$30" }, 5043 { { "ra" }, "$31" } 5044 }; 5045 Aliases = GCCRegAliases; 5046 NumAliases = llvm::array_lengthof(GCCRegAliases); 5047 } 5048 }; 5049 5050 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5051 public: 5052 Mips32EBTargetInfo(const llvm::Triple &Triple) 5053 : Mips32TargetInfoBase(Triple) { 5054 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5055 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5056 } 5057 virtual void getTargetDefines(const LangOptions &Opts, 5058 MacroBuilder &Builder) const { 5059 DefineStd(Builder, "MIPSEB", Opts); 5060 Builder.defineMacro("_MIPSEB"); 5061 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5062 } 5063 }; 5064 5065 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5066 public: 5067 Mips32ELTargetInfo(const llvm::Triple &Triple) 5068 : Mips32TargetInfoBase(Triple) { 5069 BigEndian = false; 5070 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5071 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5072 } 5073 virtual void getTargetDefines(const LangOptions &Opts, 5074 MacroBuilder &Builder) const { 5075 DefineStd(Builder, "MIPSEL", Opts); 5076 Builder.defineMacro("_MIPSEL"); 5077 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5078 } 5079 }; 5080 5081 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5082 virtual void SetDescriptionString(const std::string &Name) = 0; 5083 public: 5084 Mips64TargetInfoBase(const llvm::Triple &Triple) 5085 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5086 LongWidth = LongAlign = 64; 5087 PointerWidth = PointerAlign = 64; 5088 LongDoubleWidth = LongDoubleAlign = 128; 5089 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5090 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5091 LongDoubleWidth = LongDoubleAlign = 64; 5092 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5093 } 5094 SuitableAlign = 128; 5095 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5096 } 5097 virtual bool setABI(const std::string &Name) { 5098 SetDescriptionString(Name); 5099 if (Name == "n32") { 5100 LongWidth = LongAlign = 32; 5101 PointerWidth = PointerAlign = 32; 5102 ABI = Name; 5103 return true; 5104 } else if (Name == "n64") { 5105 ABI = Name; 5106 return true; 5107 } else if (Name == "64") { 5108 ABI = "n64"; 5109 return true; 5110 } else 5111 return false; 5112 } 5113 virtual void getTargetDefines(const LangOptions &Opts, 5114 MacroBuilder &Builder) const { 5115 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5116 5117 Builder.defineMacro("__mips64"); 5118 Builder.defineMacro("__mips64__"); 5119 5120 if (ABI == "n32") { 5121 Builder.defineMacro("__mips_n32"); 5122 Builder.defineMacro("_ABIN32", "2"); 5123 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5124 } 5125 else if (ABI == "n64") { 5126 Builder.defineMacro("__mips_n64"); 5127 Builder.defineMacro("_ABI64", "3"); 5128 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5129 } 5130 else 5131 llvm_unreachable("Invalid ABI for Mips64."); 5132 } 5133 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5134 unsigned &NumAliases) const { 5135 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5136 { { "at" }, "$1" }, 5137 { { "v0" }, "$2" }, 5138 { { "v1" }, "$3" }, 5139 { { "a0" }, "$4" }, 5140 { { "a1" }, "$5" }, 5141 { { "a2" }, "$6" }, 5142 { { "a3" }, "$7" }, 5143 { { "a4" }, "$8" }, 5144 { { "a5" }, "$9" }, 5145 { { "a6" }, "$10" }, 5146 { { "a7" }, "$11" }, 5147 { { "t0" }, "$12" }, 5148 { { "t1" }, "$13" }, 5149 { { "t2" }, "$14" }, 5150 { { "t3" }, "$15" }, 5151 { { "s0" }, "$16" }, 5152 { { "s1" }, "$17" }, 5153 { { "s2" }, "$18" }, 5154 { { "s3" }, "$19" }, 5155 { { "s4" }, "$20" }, 5156 { { "s5" }, "$21" }, 5157 { { "s6" }, "$22" }, 5158 { { "s7" }, "$23" }, 5159 { { "t8" }, "$24" }, 5160 { { "t9" }, "$25" }, 5161 { { "k0" }, "$26" }, 5162 { { "k1" }, "$27" }, 5163 { { "gp" }, "$28" }, 5164 { { "sp","$sp" }, "$29" }, 5165 { { "fp","$fp" }, "$30" }, 5166 { { "ra" }, "$31" } 5167 }; 5168 Aliases = GCCRegAliases; 5169 NumAliases = llvm::array_lengthof(GCCRegAliases); 5170 } 5171 }; 5172 5173 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5174 virtual void SetDescriptionString(const std::string &Name) { 5175 // Change DescriptionString only if ABI is n32. 5176 if (Name == "n32") 5177 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5178 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5179 "v64:64:64-n32:64-S128"; 5180 } 5181 public: 5182 Mips64EBTargetInfo(const llvm::Triple &Triple) 5183 : Mips64TargetInfoBase(Triple) { 5184 // Default ABI is n64. 5185 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5186 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5187 "v64:64:64-n32:64-S128"; 5188 } 5189 virtual void getTargetDefines(const LangOptions &Opts, 5190 MacroBuilder &Builder) const { 5191 DefineStd(Builder, "MIPSEB", Opts); 5192 Builder.defineMacro("_MIPSEB"); 5193 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5194 } 5195 }; 5196 5197 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5198 virtual void SetDescriptionString(const std::string &Name) { 5199 // Change DescriptionString only if ABI is n32. 5200 if (Name == "n32") 5201 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5202 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5203 "-v64:64:64-n32:64-S128"; 5204 } 5205 public: 5206 Mips64ELTargetInfo(const llvm::Triple &Triple) 5207 : Mips64TargetInfoBase(Triple) { 5208 // Default ABI is n64. 5209 BigEndian = false; 5210 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5211 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5212 "v64:64:64-n32:64-S128"; 5213 } 5214 virtual void getTargetDefines(const LangOptions &Opts, 5215 MacroBuilder &Builder) const { 5216 DefineStd(Builder, "MIPSEL", Opts); 5217 Builder.defineMacro("_MIPSEL"); 5218 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5219 } 5220 }; 5221 } // end anonymous namespace. 5222 5223 namespace { 5224 class PNaClTargetInfo : public TargetInfo { 5225 public: 5226 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5227 BigEndian = false; 5228 this->UserLabelPrefix = ""; 5229 this->LongAlign = 32; 5230 this->LongWidth = 32; 5231 this->PointerAlign = 32; 5232 this->PointerWidth = 32; 5233 this->IntMaxType = TargetInfo::SignedLongLong; 5234 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5235 this->Int64Type = TargetInfo::SignedLongLong; 5236 this->DoubleAlign = 64; 5237 this->LongDoubleWidth = 64; 5238 this->LongDoubleAlign = 64; 5239 this->SizeType = TargetInfo::UnsignedInt; 5240 this->PtrDiffType = TargetInfo::SignedInt; 5241 this->IntPtrType = TargetInfo::SignedInt; 5242 this->RegParmMax = 0; // Disallow regparm 5243 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5244 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5245 } 5246 5247 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5248 } 5249 virtual void getArchDefines(const LangOptions &Opts, 5250 MacroBuilder &Builder) const { 5251 Builder.defineMacro("__le32__"); 5252 Builder.defineMacro("__pnacl__"); 5253 } 5254 virtual void getTargetDefines(const LangOptions &Opts, 5255 MacroBuilder &Builder) const { 5256 Builder.defineMacro("__LITTLE_ENDIAN__"); 5257 getArchDefines(Opts, Builder); 5258 } 5259 virtual bool hasFeature(StringRef Feature) const { 5260 return Feature == "pnacl"; 5261 } 5262 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5263 unsigned &NumRecords) const { 5264 } 5265 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5266 return TargetInfo::PNaClABIBuiltinVaList; 5267 } 5268 virtual void getGCCRegNames(const char * const *&Names, 5269 unsigned &NumNames) const; 5270 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5271 unsigned &NumAliases) const; 5272 virtual bool validateAsmConstraint(const char *&Name, 5273 TargetInfo::ConstraintInfo &Info) const { 5274 return false; 5275 } 5276 5277 virtual const char *getClobbers() const { 5278 return ""; 5279 } 5280 }; 5281 5282 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5283 unsigned &NumNames) const { 5284 Names = NULL; 5285 NumNames = 0; 5286 } 5287 5288 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5289 unsigned &NumAliases) const { 5290 Aliases = NULL; 5291 NumAliases = 0; 5292 } 5293 } // end anonymous namespace. 5294 5295 namespace { 5296 static const unsigned SPIRAddrSpaceMap[] = { 5297 1, // opencl_global 5298 3, // opencl_local 5299 2, // opencl_constant 5300 0, // cuda_device 5301 0, // cuda_constant 5302 0 // cuda_shared 5303 }; 5304 class SPIRTargetInfo : public TargetInfo { 5305 public: 5306 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5307 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5308 "SPIR target must use unknown OS"); 5309 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5310 "SPIR target must use unknown environment type"); 5311 BigEndian = false; 5312 TLSSupported = false; 5313 LongWidth = LongAlign = 64; 5314 AddrSpaceMap = &SPIRAddrSpaceMap; 5315 UseAddrSpaceMapMangling = true; 5316 // Define available target features 5317 // These must be defined in sorted order! 5318 NoAsmVariants = true; 5319 } 5320 virtual void getTargetDefines(const LangOptions &Opts, 5321 MacroBuilder &Builder) const { 5322 DefineStd(Builder, "SPIR", Opts); 5323 } 5324 virtual bool hasFeature(StringRef Feature) const { 5325 return Feature == "spir"; 5326 } 5327 5328 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5329 unsigned &NumRecords) const {} 5330 virtual const char *getClobbers() const { 5331 return ""; 5332 } 5333 virtual void getGCCRegNames(const char * const *&Names, 5334 unsigned &NumNames) const {} 5335 virtual bool validateAsmConstraint(const char *&Name, 5336 TargetInfo::ConstraintInfo &info) const { 5337 return true; 5338 } 5339 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5340 unsigned &NumAliases) const {} 5341 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5342 return TargetInfo::VoidPtrBuiltinVaList; 5343 } 5344 }; 5345 5346 5347 class SPIR32TargetInfo : public SPIRTargetInfo { 5348 public: 5349 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5350 PointerWidth = PointerAlign = 32; 5351 SizeType = TargetInfo::UnsignedInt; 5352 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5353 DescriptionString 5354 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5355 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5356 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5357 "v512:512:512-v1024:1024:1024"; 5358 } 5359 virtual void getTargetDefines(const LangOptions &Opts, 5360 MacroBuilder &Builder) const { 5361 DefineStd(Builder, "SPIR32", Opts); 5362 } 5363 }; 5364 5365 class SPIR64TargetInfo : public SPIRTargetInfo { 5366 public: 5367 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5368 PointerWidth = PointerAlign = 64; 5369 SizeType = TargetInfo::UnsignedLong; 5370 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5371 DescriptionString 5372 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5373 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5374 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5375 "v512:512:512-v1024:1024:1024"; 5376 } 5377 virtual void getTargetDefines(const LangOptions &Opts, 5378 MacroBuilder &Builder) const { 5379 DefineStd(Builder, "SPIR64", Opts); 5380 } 5381 }; 5382 } 5383 5384 namespace { 5385 class XCoreTargetInfo : public TargetInfo { 5386 static const Builtin::Info BuiltinInfo[]; 5387 public: 5388 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5389 BigEndian = false; 5390 NoAsmVariants = true; 5391 LongLongAlign = 32; 5392 SuitableAlign = 32; 5393 DoubleAlign = LongDoubleAlign = 32; 5394 UseZeroLengthBitfieldAlignment = true; 5395 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5396 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5397 "-f16:16:32-f32:32:32-f64:32:32"; 5398 } 5399 virtual void getTargetDefines(const LangOptions &Opts, 5400 MacroBuilder &Builder) const { 5401 Builder.defineMacro("__XS1B__"); 5402 } 5403 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5404 unsigned &NumRecords) const { 5405 Records = BuiltinInfo; 5406 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5407 } 5408 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5409 return TargetInfo::VoidPtrBuiltinVaList; 5410 } 5411 virtual const char *getClobbers() const { 5412 return ""; 5413 } 5414 virtual void getGCCRegNames(const char * const *&Names, 5415 unsigned &NumNames) const { 5416 static const char * const GCCRegNames[] = { 5417 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5418 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5419 }; 5420 Names = GCCRegNames; 5421 NumNames = llvm::array_lengthof(GCCRegNames); 5422 } 5423 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5424 unsigned &NumAliases) const { 5425 Aliases = NULL; 5426 NumAliases = 0; 5427 } 5428 virtual bool validateAsmConstraint(const char *&Name, 5429 TargetInfo::ConstraintInfo &Info) const { 5430 return false; 5431 } 5432 }; 5433 5434 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5435 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5436 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5437 ALL_LANGUAGES }, 5438 #include "clang/Basic/BuiltinsXCore.def" 5439 }; 5440 } // end anonymous namespace. 5441 5442 5443 //===----------------------------------------------------------------------===// 5444 // Driver code 5445 //===----------------------------------------------------------------------===// 5446 5447 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5448 llvm::Triple::OSType os = Triple.getOS(); 5449 5450 switch (Triple.getArch()) { 5451 default: 5452 return NULL; 5453 5454 case llvm::Triple::xcore: 5455 return new XCoreTargetInfo(Triple); 5456 5457 case llvm::Triple::hexagon: 5458 return new HexagonTargetInfo(Triple); 5459 5460 case llvm::Triple::aarch64: 5461 switch (os) { 5462 case llvm::Triple::Linux: 5463 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5464 default: 5465 return new AArch64TargetInfo(Triple); 5466 } 5467 5468 case llvm::Triple::arm: 5469 case llvm::Triple::thumb: 5470 if (Triple.isOSDarwin()) 5471 return new DarwinARMTargetInfo(Triple); 5472 5473 switch (os) { 5474 case llvm::Triple::Linux: 5475 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5476 case llvm::Triple::FreeBSD: 5477 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5478 case llvm::Triple::NetBSD: 5479 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5480 case llvm::Triple::OpenBSD: 5481 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5482 case llvm::Triple::Bitrig: 5483 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5484 case llvm::Triple::RTEMS: 5485 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5486 case llvm::Triple::NaCl: 5487 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5488 default: 5489 return new ARMTargetInfo(Triple); 5490 } 5491 5492 case llvm::Triple::msp430: 5493 return new MSP430TargetInfo(Triple); 5494 5495 case llvm::Triple::mips: 5496 switch (os) { 5497 case llvm::Triple::Linux: 5498 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5499 case llvm::Triple::RTEMS: 5500 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5501 case llvm::Triple::FreeBSD: 5502 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5503 case llvm::Triple::NetBSD: 5504 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5505 default: 5506 return new Mips32EBTargetInfo(Triple); 5507 } 5508 5509 case llvm::Triple::mipsel: 5510 switch (os) { 5511 case llvm::Triple::Linux: 5512 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5513 case llvm::Triple::RTEMS: 5514 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5515 case llvm::Triple::FreeBSD: 5516 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5517 case llvm::Triple::NetBSD: 5518 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5519 case llvm::Triple::NaCl: 5520 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5521 default: 5522 return new Mips32ELTargetInfo(Triple); 5523 } 5524 5525 case llvm::Triple::mips64: 5526 switch (os) { 5527 case llvm::Triple::Linux: 5528 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5529 case llvm::Triple::RTEMS: 5530 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5531 case llvm::Triple::FreeBSD: 5532 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5533 case llvm::Triple::NetBSD: 5534 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5535 case llvm::Triple::OpenBSD: 5536 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5537 default: 5538 return new Mips64EBTargetInfo(Triple); 5539 } 5540 5541 case llvm::Triple::mips64el: 5542 switch (os) { 5543 case llvm::Triple::Linux: 5544 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5545 case llvm::Triple::RTEMS: 5546 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5547 case llvm::Triple::FreeBSD: 5548 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5549 case llvm::Triple::NetBSD: 5550 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5551 case llvm::Triple::OpenBSD: 5552 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5553 default: 5554 return new Mips64ELTargetInfo(Triple); 5555 } 5556 5557 case llvm::Triple::le32: 5558 switch (os) { 5559 case llvm::Triple::NaCl: 5560 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5561 default: 5562 return NULL; 5563 } 5564 5565 case llvm::Triple::ppc: 5566 if (Triple.isOSDarwin()) 5567 return new DarwinPPC32TargetInfo(Triple); 5568 switch (os) { 5569 case llvm::Triple::Linux: 5570 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5571 case llvm::Triple::FreeBSD: 5572 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5573 case llvm::Triple::NetBSD: 5574 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5575 case llvm::Triple::OpenBSD: 5576 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5577 case llvm::Triple::RTEMS: 5578 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5579 default: 5580 return new PPC32TargetInfo(Triple); 5581 } 5582 5583 case llvm::Triple::ppc64: 5584 if (Triple.isOSDarwin()) 5585 return new DarwinPPC64TargetInfo(Triple); 5586 switch (os) { 5587 case llvm::Triple::Linux: 5588 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5589 case llvm::Triple::Lv2: 5590 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5591 case llvm::Triple::FreeBSD: 5592 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5593 case llvm::Triple::NetBSD: 5594 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5595 default: 5596 return new PPC64TargetInfo(Triple); 5597 } 5598 5599 case llvm::Triple::ppc64le: 5600 switch (os) { 5601 case llvm::Triple::Linux: 5602 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5603 default: 5604 return new PPC64TargetInfo(Triple); 5605 } 5606 5607 case llvm::Triple::nvptx: 5608 return new NVPTX32TargetInfo(Triple); 5609 case llvm::Triple::nvptx64: 5610 return new NVPTX64TargetInfo(Triple); 5611 5612 case llvm::Triple::r600: 5613 return new R600TargetInfo(Triple); 5614 5615 case llvm::Triple::sparc: 5616 switch (os) { 5617 case llvm::Triple::Linux: 5618 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5619 case llvm::Triple::AuroraUX: 5620 return new AuroraUXSparcV8TargetInfo(Triple); 5621 case llvm::Triple::Solaris: 5622 return new SolarisSparcV8TargetInfo(Triple); 5623 case llvm::Triple::NetBSD: 5624 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5625 case llvm::Triple::OpenBSD: 5626 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5627 case llvm::Triple::RTEMS: 5628 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5629 default: 5630 return new SparcV8TargetInfo(Triple); 5631 } 5632 5633 case llvm::Triple::sparcv9: 5634 switch (os) { 5635 case llvm::Triple::Linux: 5636 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5637 case llvm::Triple::AuroraUX: 5638 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5639 case llvm::Triple::Solaris: 5640 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5641 case llvm::Triple::NetBSD: 5642 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5643 case llvm::Triple::OpenBSD: 5644 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5645 case llvm::Triple::FreeBSD: 5646 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5647 default: 5648 return new SparcV9TargetInfo(Triple); 5649 } 5650 5651 case llvm::Triple::systemz: 5652 switch (os) { 5653 case llvm::Triple::Linux: 5654 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5655 default: 5656 return new SystemZTargetInfo(Triple); 5657 } 5658 5659 case llvm::Triple::tce: 5660 return new TCETargetInfo(Triple); 5661 5662 case llvm::Triple::x86: 5663 if (Triple.isOSDarwin()) 5664 return new DarwinI386TargetInfo(Triple); 5665 5666 switch (os) { 5667 case llvm::Triple::AuroraUX: 5668 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5669 case llvm::Triple::Linux: 5670 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5671 case llvm::Triple::DragonFly: 5672 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5673 case llvm::Triple::NetBSD: 5674 return new NetBSDI386TargetInfo(Triple); 5675 case llvm::Triple::OpenBSD: 5676 return new OpenBSDI386TargetInfo(Triple); 5677 case llvm::Triple::Bitrig: 5678 return new BitrigI386TargetInfo(Triple); 5679 case llvm::Triple::FreeBSD: 5680 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5681 case llvm::Triple::KFreeBSD: 5682 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5683 case llvm::Triple::Minix: 5684 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5685 case llvm::Triple::Solaris: 5686 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5687 case llvm::Triple::Cygwin: 5688 return new CygwinX86_32TargetInfo(Triple); 5689 case llvm::Triple::MinGW32: 5690 return new MinGWX86_32TargetInfo(Triple); 5691 case llvm::Triple::Win32: 5692 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5693 case llvm::Triple::Haiku: 5694 return new HaikuX86_32TargetInfo(Triple); 5695 case llvm::Triple::RTEMS: 5696 return new RTEMSX86_32TargetInfo(Triple); 5697 case llvm::Triple::NaCl: 5698 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5699 default: 5700 return new X86_32TargetInfo(Triple); 5701 } 5702 5703 case llvm::Triple::x86_64: 5704 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5705 return new DarwinX86_64TargetInfo(Triple); 5706 5707 switch (os) { 5708 case llvm::Triple::AuroraUX: 5709 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5710 case llvm::Triple::Linux: 5711 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5712 case llvm::Triple::DragonFly: 5713 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5714 case llvm::Triple::NetBSD: 5715 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5716 case llvm::Triple::OpenBSD: 5717 return new OpenBSDX86_64TargetInfo(Triple); 5718 case llvm::Triple::Bitrig: 5719 return new BitrigX86_64TargetInfo(Triple); 5720 case llvm::Triple::FreeBSD: 5721 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5722 case llvm::Triple::KFreeBSD: 5723 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5724 case llvm::Triple::Solaris: 5725 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5726 case llvm::Triple::MinGW32: 5727 return new MinGWX86_64TargetInfo(Triple); 5728 case llvm::Triple::Win32: // This is what Triple.h supports now. 5729 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5730 case llvm::Triple::NaCl: 5731 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5732 default: 5733 return new X86_64TargetInfo(Triple); 5734 } 5735 5736 case llvm::Triple::spir: { 5737 if (Triple.getOS() != llvm::Triple::UnknownOS || 5738 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5739 return NULL; 5740 return new SPIR32TargetInfo(Triple); 5741 } 5742 case llvm::Triple::spir64: { 5743 if (Triple.getOS() != llvm::Triple::UnknownOS || 5744 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5745 return NULL; 5746 return new SPIR64TargetInfo(Triple); 5747 } 5748 } 5749 } 5750 5751 /// CreateTargetInfo - Return the target info object for the specified target 5752 /// triple. 5753 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5754 TargetOptions *Opts) { 5755 llvm::Triple Triple(Opts->Triple); 5756 5757 // Construct the target 5758 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5759 if (!Target) { 5760 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5761 return 0; 5762 } 5763 Target->setTargetOpts(Opts); 5764 5765 // Set the target CPU if specified. 5766 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5767 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5768 return 0; 5769 } 5770 5771 // Set the target ABI if specified. 5772 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5773 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5774 return 0; 5775 } 5776 5777 // Set the target C++ ABI. 5778 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5779 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5780 return 0; 5781 } 5782 5783 // Set the fp math unit. 5784 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5785 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5786 return 0; 5787 } 5788 5789 // Compute the default target features, we need the target to handle this 5790 // because features may have dependencies on one another. 5791 llvm::StringMap<bool> Features; 5792 Target->getDefaultFeatures(Features); 5793 5794 // Apply the user specified deltas. 5795 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5796 I < N; ++I) { 5797 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5798 // Apply the feature via the target. 5799 bool Enabled = Name[0] == '+'; 5800 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5801 } 5802 5803 // Add the features to the compile options. 5804 // 5805 // FIXME: If we are completely confident that we have the right set, we only 5806 // need to pass the minuses. 5807 Opts->Features.clear(); 5808 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5809 ie = Features.end(); it != ie; ++it) 5810 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5811 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5812 return 0; 5813 5814 return Target.take(); 5815 } 5816