1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/TargetParser.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.has(SanitizerKind::Address))
98     Builder.defineMacro("_FORTIFY_SOURCE", "0");
99 
100   if (!Opts.ObjCAutoRefCount) {
101     // __weak is always defined, for use in blocks and with objc pointers.
102     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
103 
104     // Darwin defines __strong even in C mode (just to nothing).
105     if (Opts.getGC() != LangOptions::NonGC)
106       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
107     else
108       Builder.defineMacro("__strong", "");
109 
110     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
111     // allow this in C, since one might have block pointers in structs that
112     // are used in pure C code and in Objective-C ARC.
113     Builder.defineMacro("__unsafe_unretained", "");
114   }
115 
116   if (Opts.Static)
117     Builder.defineMacro("__STATIC__");
118   else
119     Builder.defineMacro("__DYNAMIC__");
120 
121   if (Opts.POSIXThreads)
122     Builder.defineMacro("_REENTRANT");
123 
124   // Get the platform type and version number from the triple.
125   unsigned Maj, Min, Rev;
126   if (Triple.isMacOSX()) {
127     Triple.getMacOSXVersion(Maj, Min, Rev);
128     PlatformName = "macosx";
129   } else {
130     Triple.getOSVersion(Maj, Min, Rev);
131     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
132   }
133 
134   // If -target arch-pc-win32-macho option specified, we're
135   // generating code for Win32 ABI. No need to emit
136   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
137   if (PlatformName == "win32") {
138     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
139     return;
140   }
141 
142   // Set the appropriate OS version define.
143   if (Triple.isiOS()) {
144     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
145     char Str[6];
146     Str[0] = '0' + Maj;
147     Str[1] = '0' + (Min / 10);
148     Str[2] = '0' + (Min % 10);
149     Str[3] = '0' + (Rev / 10);
150     Str[4] = '0' + (Rev % 10);
151     Str[5] = '\0';
152     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
153                         Str);
154   } else if (Triple.isMacOSX()) {
155     // Note that the Driver allows versions which aren't representable in the
156     // define (because we only get a single digit for the minor and micro
157     // revision numbers). So, we limit them to the maximum representable
158     // version.
159     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
160     char Str[7];
161     if (Maj < 10 || (Maj == 10 && Min < 10)) {
162       Str[0] = '0' + (Maj / 10);
163       Str[1] = '0' + (Maj % 10);
164       Str[2] = '0' + std::min(Min, 9U);
165       Str[3] = '0' + std::min(Rev, 9U);
166       Str[4] = '\0';
167     } else {
168       // Handle versions > 10.9.
169       Str[0] = '0' + (Maj / 10);
170       Str[1] = '0' + (Maj % 10);
171       Str[2] = '0' + (Min / 10);
172       Str[3] = '0' + (Min % 10);
173       Str[4] = '0' + (Rev / 10);
174       Str[5] = '0' + (Rev % 10);
175       Str[6] = '\0';
176     }
177     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
178   }
179 
180   // Tell users about the kernel if there is one.
181   if (Triple.isOSDarwin())
182     Builder.defineMacro("__MACH__");
183 
184   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
185 }
186 
187 namespace {
188 // CloudABI Target
189 template <typename Target>
190 class CloudABITargetInfo : public OSTargetInfo<Target> {
191 protected:
192   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
193                     MacroBuilder &Builder) const override {
194     Builder.defineMacro("__CloudABI__");
195     Builder.defineMacro("__ELF__");
196 
197     // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t.
198     Builder.defineMacro("__STDC_ISO_10646__", "201206L");
199     Builder.defineMacro("__STDC_UTF_16__");
200     Builder.defineMacro("__STDC_UTF_32__");
201   }
202 
203 public:
204   CloudABITargetInfo(const llvm::Triple &Triple)
205       : OSTargetInfo<Target>(Triple) {
206     this->UserLabelPrefix = "";
207   }
208 };
209 
210 template<typename Target>
211 class DarwinTargetInfo : public OSTargetInfo<Target> {
212 protected:
213   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
214                     MacroBuilder &Builder) const override {
215     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
216                      this->PlatformMinVersion);
217   }
218 
219 public:
220   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
221     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
222     this->MCountName = "\01mcount";
223   }
224 
225   std::string isValidSectionSpecifier(StringRef SR) const override {
226     // Let MCSectionMachO validate this.
227     StringRef Segment, Section;
228     unsigned TAA, StubSize;
229     bool HasTAA;
230     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
231                                                        TAA, HasTAA, StubSize);
232   }
233 
234   const char *getStaticInitSectionSpecifier() const override {
235     // FIXME: We should return 0 when building kexts.
236     return "__TEXT,__StaticInit,regular,pure_instructions";
237   }
238 
239   /// Darwin does not support protected visibility.  Darwin's "default"
240   /// is very similar to ELF's "protected";  Darwin requires a "weak"
241   /// attribute on declarations that can be dynamically replaced.
242   bool hasProtectedVisibility() const override {
243     return false;
244   }
245 };
246 
247 
248 // DragonFlyBSD Target
249 template<typename Target>
250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
251 protected:
252   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
253                     MacroBuilder &Builder) const override {
254     // DragonFly defines; list based off of gcc output
255     Builder.defineMacro("__DragonFly__");
256     Builder.defineMacro("__DragonFly_cc_version", "100001");
257     Builder.defineMacro("__ELF__");
258     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
259     Builder.defineMacro("__tune_i386__");
260     DefineStd(Builder, "unix", Opts);
261   }
262 public:
263   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
264       : OSTargetInfo<Target>(Triple) {
265     this->UserLabelPrefix = "";
266 
267     switch (Triple.getArch()) {
268     default:
269     case llvm::Triple::x86:
270     case llvm::Triple::x86_64:
271       this->MCountName = ".mcount";
272       break;
273     }
274   }
275 };
276 
277 // FreeBSD Target
278 template<typename Target>
279 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
280 protected:
281   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
282                     MacroBuilder &Builder) const override {
283     // FreeBSD defines; list based off of gcc output
284 
285     unsigned Release = Triple.getOSMajorVersion();
286     if (Release == 0U)
287       Release = 8;
288 
289     Builder.defineMacro("__FreeBSD__", Twine(Release));
290     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
291     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
292     DefineStd(Builder, "unix", Opts);
293     Builder.defineMacro("__ELF__");
294 
295     // On FreeBSD, wchar_t contains the number of the code point as
296     // used by the character set of the locale. These character sets are
297     // not necessarily a superset of ASCII.
298     //
299     // FIXME: This is wrong; the macro refers to the numerical values
300     // of wchar_t *literals*, which are not locale-dependent. However,
301     // FreeBSD systems apparently depend on us getting this wrong, and
302     // setting this to 1 is conforming even if all the basic source
303     // character literals have the same encoding as char and wchar_t.
304     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
305   }
306 public:
307   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308     this->UserLabelPrefix = "";
309 
310     switch (Triple.getArch()) {
311     default:
312     case llvm::Triple::x86:
313     case llvm::Triple::x86_64:
314       this->MCountName = ".mcount";
315       break;
316     case llvm::Triple::mips:
317     case llvm::Triple::mipsel:
318     case llvm::Triple::ppc:
319     case llvm::Triple::ppc64:
320     case llvm::Triple::ppc64le:
321       this->MCountName = "_mcount";
322       break;
323     case llvm::Triple::arm:
324       this->MCountName = "__mcount";
325       break;
326     }
327   }
328 };
329 
330 // GNU/kFreeBSD Target
331 template<typename Target>
332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
333 protected:
334   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
335                     MacroBuilder &Builder) const override {
336     // GNU/kFreeBSD defines; list based off of gcc output
337 
338     DefineStd(Builder, "unix", Opts);
339     Builder.defineMacro("__FreeBSD_kernel__");
340     Builder.defineMacro("__GLIBC__");
341     Builder.defineMacro("__ELF__");
342     if (Opts.POSIXThreads)
343       Builder.defineMacro("_REENTRANT");
344     if (Opts.CPlusPlus)
345       Builder.defineMacro("_GNU_SOURCE");
346   }
347 public:
348   KFreeBSDTargetInfo(const llvm::Triple &Triple)
349       : OSTargetInfo<Target>(Triple) {
350     this->UserLabelPrefix = "";
351   }
352 };
353 
354 // Minix Target
355 template<typename Target>
356 class MinixTargetInfo : public OSTargetInfo<Target> {
357 protected:
358   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
359                     MacroBuilder &Builder) const override {
360     // Minix defines
361 
362     Builder.defineMacro("__minix", "3");
363     Builder.defineMacro("_EM_WSIZE", "4");
364     Builder.defineMacro("_EM_PSIZE", "4");
365     Builder.defineMacro("_EM_SSIZE", "2");
366     Builder.defineMacro("_EM_LSIZE", "4");
367     Builder.defineMacro("_EM_FSIZE", "4");
368     Builder.defineMacro("_EM_DSIZE", "8");
369     Builder.defineMacro("__ELF__");
370     DefineStd(Builder, "unix", Opts);
371   }
372 public:
373   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
374     this->UserLabelPrefix = "";
375   }
376 };
377 
378 // Linux target
379 template<typename Target>
380 class LinuxTargetInfo : public OSTargetInfo<Target> {
381 protected:
382   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
383                     MacroBuilder &Builder) const override {
384     // Linux defines; list based off of gcc output
385     DefineStd(Builder, "unix", Opts);
386     DefineStd(Builder, "linux", Opts);
387     Builder.defineMacro("__gnu_linux__");
388     Builder.defineMacro("__ELF__");
389     if (Triple.getEnvironment() == llvm::Triple::Android) {
390       Builder.defineMacro("__ANDROID__", "1");
391       unsigned Maj, Min, Rev;
392       Triple.getEnvironmentVersion(Maj, Min, Rev);
393       this->PlatformName = "android";
394       this->PlatformMinVersion = VersionTuple(Maj, Min, Rev);
395     }
396     if (Opts.POSIXThreads)
397       Builder.defineMacro("_REENTRANT");
398     if (Opts.CPlusPlus)
399       Builder.defineMacro("_GNU_SOURCE");
400   }
401 public:
402   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
403     this->UserLabelPrefix = "";
404     this->WIntType = TargetInfo::UnsignedInt;
405 
406     switch (Triple.getArch()) {
407     default:
408       break;
409     case llvm::Triple::ppc:
410     case llvm::Triple::ppc64:
411     case llvm::Triple::ppc64le:
412       this->MCountName = "_mcount";
413       break;
414     }
415   }
416 
417   const char *getStaticInitSectionSpecifier() const override {
418     return ".text.startup";
419   }
420 };
421 
422 // NetBSD Target
423 template<typename Target>
424 class NetBSDTargetInfo : public OSTargetInfo<Target> {
425 protected:
426   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
427                     MacroBuilder &Builder) const override {
428     // NetBSD defines; list based off of gcc output
429     Builder.defineMacro("__NetBSD__");
430     Builder.defineMacro("__unix__");
431     Builder.defineMacro("__ELF__");
432     if (Opts.POSIXThreads)
433       Builder.defineMacro("_POSIX_THREADS");
434 
435     switch (Triple.getArch()) {
436     default:
437       break;
438     case llvm::Triple::arm:
439     case llvm::Triple::armeb:
440     case llvm::Triple::thumb:
441     case llvm::Triple::thumbeb:
442       Builder.defineMacro("__ARM_DWARF_EH__");
443       break;
444     }
445   }
446 public:
447   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
448     this->UserLabelPrefix = "";
449     this->MCountName = "_mcount";
450   }
451 };
452 
453 // OpenBSD Target
454 template<typename Target>
455 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
456 protected:
457   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
458                     MacroBuilder &Builder) const override {
459     // OpenBSD defines; list based off of gcc output
460 
461     Builder.defineMacro("__OpenBSD__");
462     DefineStd(Builder, "unix", Opts);
463     Builder.defineMacro("__ELF__");
464     if (Opts.POSIXThreads)
465       Builder.defineMacro("_REENTRANT");
466   }
467 public:
468   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
469     this->UserLabelPrefix = "";
470     this->TLSSupported = false;
471 
472       switch (Triple.getArch()) {
473         default:
474         case llvm::Triple::x86:
475         case llvm::Triple::x86_64:
476         case llvm::Triple::arm:
477         case llvm::Triple::sparc:
478           this->MCountName = "__mcount";
479           break;
480         case llvm::Triple::mips64:
481         case llvm::Triple::mips64el:
482         case llvm::Triple::ppc:
483         case llvm::Triple::sparcv9:
484           this->MCountName = "_mcount";
485           break;
486       }
487   }
488 };
489 
490 // Bitrig Target
491 template<typename Target>
492 class BitrigTargetInfo : public OSTargetInfo<Target> {
493 protected:
494   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
495                     MacroBuilder &Builder) const override {
496     // Bitrig defines; list based off of gcc output
497 
498     Builder.defineMacro("__Bitrig__");
499     DefineStd(Builder, "unix", Opts);
500     Builder.defineMacro("__ELF__");
501     if (Opts.POSIXThreads)
502       Builder.defineMacro("_REENTRANT");
503 
504     switch (Triple.getArch()) {
505     default:
506       break;
507     case llvm::Triple::arm:
508     case llvm::Triple::armeb:
509     case llvm::Triple::thumb:
510     case llvm::Triple::thumbeb:
511       Builder.defineMacro("__ARM_DWARF_EH__");
512       break;
513     }
514   }
515 public:
516   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
517     this->UserLabelPrefix = "";
518     this->MCountName = "__mcount";
519   }
520 };
521 
522 // PSP Target
523 template<typename Target>
524 class PSPTargetInfo : public OSTargetInfo<Target> {
525 protected:
526   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
527                     MacroBuilder &Builder) const override {
528     // PSP defines; list based on the output of the pspdev gcc toolchain.
529     Builder.defineMacro("PSP");
530     Builder.defineMacro("_PSP");
531     Builder.defineMacro("__psp__");
532     Builder.defineMacro("__ELF__");
533   }
534 public:
535   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
536     this->UserLabelPrefix = "";
537   }
538 };
539 
540 // PS3 PPU Target
541 template<typename Target>
542 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
543 protected:
544   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
545                     MacroBuilder &Builder) const override {
546     // PS3 PPU defines.
547     Builder.defineMacro("__PPC__");
548     Builder.defineMacro("__PPU__");
549     Builder.defineMacro("__CELLOS_LV2__");
550     Builder.defineMacro("__ELF__");
551     Builder.defineMacro("__LP32__");
552     Builder.defineMacro("_ARCH_PPC64");
553     Builder.defineMacro("__powerpc64__");
554   }
555 public:
556   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557     this->UserLabelPrefix = "";
558     this->LongWidth = this->LongAlign = 32;
559     this->PointerWidth = this->PointerAlign = 32;
560     this->IntMaxType = TargetInfo::SignedLongLong;
561     this->Int64Type = TargetInfo::SignedLongLong;
562     this->SizeType = TargetInfo::UnsignedInt;
563     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
564   }
565 };
566 
567 template <typename Target>
568 class PS4OSTargetInfo : public OSTargetInfo<Target> {
569 protected:
570   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
571                     MacroBuilder &Builder) const override {
572     Builder.defineMacro("__FreeBSD__", "9");
573     Builder.defineMacro("__FreeBSD_cc_version", "900001");
574     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
575     DefineStd(Builder, "unix", Opts);
576     Builder.defineMacro("__ELF__");
577     Builder.defineMacro("__PS4__");
578   }
579 public:
580   PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
581     this->WCharType = this->UnsignedShort;
582 
583     this->UserLabelPrefix = "";
584 
585     switch (Triple.getArch()) {
586     default:
587     case llvm::Triple::x86_64:
588       this->MCountName = ".mcount";
589       break;
590     }
591   }
592 };
593 
594 // Solaris target
595 template<typename Target>
596 class SolarisTargetInfo : public OSTargetInfo<Target> {
597 protected:
598   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
599                     MacroBuilder &Builder) const override {
600     DefineStd(Builder, "sun", Opts);
601     DefineStd(Builder, "unix", Opts);
602     Builder.defineMacro("__ELF__");
603     Builder.defineMacro("__svr4__");
604     Builder.defineMacro("__SVR4");
605     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
606     // newer, but to 500 for everything else.  feature_test.h has a check to
607     // ensure that you are not using C99 with an old version of X/Open or C89
608     // with a new version.
609     if (Opts.C99)
610       Builder.defineMacro("_XOPEN_SOURCE", "600");
611     else
612       Builder.defineMacro("_XOPEN_SOURCE", "500");
613     if (Opts.CPlusPlus)
614       Builder.defineMacro("__C99FEATURES__");
615     Builder.defineMacro("_LARGEFILE_SOURCE");
616     Builder.defineMacro("_LARGEFILE64_SOURCE");
617     Builder.defineMacro("__EXTENSIONS__");
618     Builder.defineMacro("_REENTRANT");
619   }
620 public:
621   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
622     this->UserLabelPrefix = "";
623     this->WCharType = this->SignedInt;
624     // FIXME: WIntType should be SignedLong
625   }
626 };
627 
628 // Windows target
629 template<typename Target>
630 class WindowsTargetInfo : public OSTargetInfo<Target> {
631 protected:
632   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
633                     MacroBuilder &Builder) const override {
634     Builder.defineMacro("_WIN32");
635   }
636   void getVisualStudioDefines(const LangOptions &Opts,
637                               MacroBuilder &Builder) const {
638     if (Opts.CPlusPlus) {
639       if (Opts.RTTIData)
640         Builder.defineMacro("_CPPRTTI");
641 
642       if (Opts.CXXExceptions)
643         Builder.defineMacro("_CPPUNWIND");
644     }
645 
646     if (!Opts.CharIsSigned)
647       Builder.defineMacro("_CHAR_UNSIGNED");
648 
649     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
650     //        but it works for now.
651     if (Opts.POSIXThreads)
652       Builder.defineMacro("_MT");
653 
654     if (Opts.MSCompatibilityVersion) {
655       Builder.defineMacro("_MSC_VER",
656                           Twine(Opts.MSCompatibilityVersion / 100000));
657       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
658       // FIXME We cannot encode the revision information into 32-bits
659       Builder.defineMacro("_MSC_BUILD", Twine(1));
660 
661       if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015))
662         Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1));
663     }
664 
665     if (Opts.MicrosoftExt) {
666       Builder.defineMacro("_MSC_EXTENSIONS");
667 
668       if (Opts.CPlusPlus11) {
669         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
670         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
671         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
672       }
673     }
674 
675     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
676   }
677 
678 public:
679   WindowsTargetInfo(const llvm::Triple &Triple)
680       : OSTargetInfo<Target>(Triple) {}
681 };
682 
683 template <typename Target>
684 class NaClTargetInfo : public OSTargetInfo<Target> {
685 protected:
686   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
687                     MacroBuilder &Builder) const override {
688     if (Opts.POSIXThreads)
689       Builder.defineMacro("_REENTRANT");
690     if (Opts.CPlusPlus)
691       Builder.defineMacro("_GNU_SOURCE");
692 
693     DefineStd(Builder, "unix", Opts);
694     Builder.defineMacro("__ELF__");
695     Builder.defineMacro("__native_client__");
696   }
697 
698 public:
699   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
700     this->UserLabelPrefix = "";
701     this->LongAlign = 32;
702     this->LongWidth = 32;
703     this->PointerAlign = 32;
704     this->PointerWidth = 32;
705     this->IntMaxType = TargetInfo::SignedLongLong;
706     this->Int64Type = TargetInfo::SignedLongLong;
707     this->DoubleAlign = 64;
708     this->LongDoubleWidth = 64;
709     this->LongDoubleAlign = 64;
710     this->LongLongWidth = 64;
711     this->LongLongAlign = 64;
712     this->SizeType = TargetInfo::UnsignedInt;
713     this->PtrDiffType = TargetInfo::SignedInt;
714     this->IntPtrType = TargetInfo::SignedInt;
715     // RegParmMax is inherited from the underlying architecture
716     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
717     if (Triple.getArch() == llvm::Triple::arm) {
718       // Handled in ARM's setABI().
719     } else if (Triple.getArch() == llvm::Triple::x86) {
720       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
721     } else if (Triple.getArch() == llvm::Triple::x86_64) {
722       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
723     } else if (Triple.getArch() == llvm::Triple::mipsel) {
724       // Handled on mips' setDescriptionString.
725     } else {
726       assert(Triple.getArch() == llvm::Triple::le32);
727       this->DescriptionString = "e-p:32:32-i64:64";
728     }
729   }
730 };
731 
732 //===----------------------------------------------------------------------===//
733 // Specific target implementations.
734 //===----------------------------------------------------------------------===//
735 
736 // PPC abstract base class
737 class PPCTargetInfo : public TargetInfo {
738   static const Builtin::Info BuiltinInfo[];
739   static const char * const GCCRegNames[];
740   static const TargetInfo::GCCRegAlias GCCRegAliases[];
741   std::string CPU;
742 
743   // Target cpu features.
744   bool HasVSX;
745   bool HasP8Vector;
746   bool HasP8Crypto;
747   bool HasDirectMove;
748   bool HasQPX;
749   bool HasHTM;
750   bool HasBPERMD;
751   bool HasExtDiv;
752 
753 protected:
754   std::string ABI;
755 
756 public:
757   PPCTargetInfo(const llvm::Triple &Triple)
758     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false),
759       HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false),
760       HasBPERMD(false), HasExtDiv(false) {
761     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
762     LongDoubleWidth = LongDoubleAlign = 128;
763     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
764   }
765 
766   /// \brief Flags for architecture specific defines.
767   typedef enum {
768     ArchDefineNone  = 0,
769     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
770     ArchDefinePpcgr = 1 << 1,
771     ArchDefinePpcsq = 1 << 2,
772     ArchDefine440   = 1 << 3,
773     ArchDefine603   = 1 << 4,
774     ArchDefine604   = 1 << 5,
775     ArchDefinePwr4  = 1 << 6,
776     ArchDefinePwr5  = 1 << 7,
777     ArchDefinePwr5x = 1 << 8,
778     ArchDefinePwr6  = 1 << 9,
779     ArchDefinePwr6x = 1 << 10,
780     ArchDefinePwr7  = 1 << 11,
781     ArchDefinePwr8  = 1 << 12,
782     ArchDefineA2    = 1 << 13,
783     ArchDefineA2q   = 1 << 14
784   } ArchDefineTypes;
785 
786   // Note: GCC recognizes the following additional cpus:
787   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
788   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
789   //  titan, rs64.
790   bool setCPU(const std::string &Name) override {
791     bool CPUKnown = llvm::StringSwitch<bool>(Name)
792       .Case("generic", true)
793       .Case("440", true)
794       .Case("450", true)
795       .Case("601", true)
796       .Case("602", true)
797       .Case("603", true)
798       .Case("603e", true)
799       .Case("603ev", true)
800       .Case("604", true)
801       .Case("604e", true)
802       .Case("620", true)
803       .Case("630", true)
804       .Case("g3", true)
805       .Case("7400", true)
806       .Case("g4", true)
807       .Case("7450", true)
808       .Case("g4+", true)
809       .Case("750", true)
810       .Case("970", true)
811       .Case("g5", true)
812       .Case("a2", true)
813       .Case("a2q", true)
814       .Case("e500mc", true)
815       .Case("e5500", true)
816       .Case("power3", true)
817       .Case("pwr3", true)
818       .Case("power4", true)
819       .Case("pwr4", true)
820       .Case("power5", true)
821       .Case("pwr5", true)
822       .Case("power5x", true)
823       .Case("pwr5x", true)
824       .Case("power6", true)
825       .Case("pwr6", true)
826       .Case("power6x", true)
827       .Case("pwr6x", true)
828       .Case("power7", true)
829       .Case("pwr7", true)
830       .Case("power8", true)
831       .Case("pwr8", true)
832       .Case("powerpc", true)
833       .Case("ppc", true)
834       .Case("powerpc64", true)
835       .Case("ppc64", true)
836       .Case("powerpc64le", true)
837       .Case("ppc64le", true)
838       .Default(false);
839 
840     if (CPUKnown)
841       CPU = Name;
842 
843     return CPUKnown;
844   }
845 
846 
847   StringRef getABI() const override { return ABI; }
848 
849   void getTargetBuiltins(const Builtin::Info *&Records,
850                          unsigned &NumRecords) const override {
851     Records = BuiltinInfo;
852     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
853   }
854 
855   bool isCLZForZeroUndef() const override { return false; }
856 
857   void getTargetDefines(const LangOptions &Opts,
858                         MacroBuilder &Builder) const override;
859 
860   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
861 
862   bool handleTargetFeatures(std::vector<std::string> &Features,
863                             DiagnosticsEngine &Diags) override;
864   bool hasFeature(StringRef Feature) const override;
865 
866   void getGCCRegNames(const char * const *&Names,
867                       unsigned &NumNames) const override;
868   void getGCCRegAliases(const GCCRegAlias *&Aliases,
869                         unsigned &NumAliases) const override;
870   bool validateAsmConstraint(const char *&Name,
871                              TargetInfo::ConstraintInfo &Info) const override {
872     switch (*Name) {
873     default: return false;
874     case 'O': // Zero
875       break;
876     case 'b': // Base register
877     case 'f': // Floating point register
878       Info.setAllowsRegister();
879       break;
880     // FIXME: The following are added to allow parsing.
881     // I just took a guess at what the actions should be.
882     // Also, is more specific checking needed?  I.e. specific registers?
883     case 'd': // Floating point register (containing 64-bit value)
884     case 'v': // Altivec vector register
885       Info.setAllowsRegister();
886       break;
887     case 'w':
888       switch (Name[1]) {
889         case 'd':// VSX vector register to hold vector double data
890         case 'f':// VSX vector register to hold vector float data
891         case 's':// VSX vector register to hold scalar float data
892         case 'a':// Any VSX register
893         case 'c':// An individual CR bit
894           break;
895         default:
896           return false;
897       }
898       Info.setAllowsRegister();
899       Name++; // Skip over 'w'.
900       break;
901     case 'h': // `MQ', `CTR', or `LINK' register
902     case 'q': // `MQ' register
903     case 'c': // `CTR' register
904     case 'l': // `LINK' register
905     case 'x': // `CR' register (condition register) number 0
906     case 'y': // `CR' register (condition register)
907     case 'z': // `XER[CA]' carry bit (part of the XER register)
908       Info.setAllowsRegister();
909       break;
910     case 'I': // Signed 16-bit constant
911     case 'J': // Unsigned 16-bit constant shifted left 16 bits
912               //  (use `L' instead for SImode constants)
913     case 'K': // Unsigned 16-bit constant
914     case 'L': // Signed 16-bit constant shifted left 16 bits
915     case 'M': // Constant larger than 31
916     case 'N': // Exact power of 2
917     case 'P': // Constant whose negation is a signed 16-bit constant
918     case 'G': // Floating point constant that can be loaded into a
919               // register with one instruction per word
920     case 'H': // Integer/Floating point constant that can be loaded
921               // into a register using three instructions
922       break;
923     case 'm': // Memory operand. Note that on PowerPC targets, m can
924               // include addresses that update the base register. It
925               // is therefore only safe to use `m' in an asm statement
926               // if that asm statement accesses the operand exactly once.
927               // The asm statement must also use `%U<opno>' as a
928               // placeholder for the "update" flag in the corresponding
929               // load or store instruction. For example:
930               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
931               // is correct but:
932               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
933               // is not. Use es rather than m if you don't want the base
934               // register to be updated.
935     case 'e':
936       if (Name[1] != 's')
937           return false;
938               // es: A "stable" memory operand; that is, one which does not
939               // include any automodification of the base register. Unlike
940               // `m', this constraint can be used in asm statements that
941               // might access the operand several times, or that might not
942               // access it at all.
943       Info.setAllowsMemory();
944       Name++; // Skip over 'e'.
945       break;
946     case 'Q': // Memory operand that is an offset from a register (it is
947               // usually better to use `m' or `es' in asm statements)
948     case 'Z': // Memory operand that is an indexed or indirect from a
949               // register (it is usually better to use `m' or `es' in
950               // asm statements)
951       Info.setAllowsMemory();
952       Info.setAllowsRegister();
953       break;
954     case 'R': // AIX TOC entry
955     case 'a': // Address operand that is an indexed or indirect from a
956               // register (`p' is preferable for asm statements)
957     case 'S': // Constant suitable as a 64-bit mask operand
958     case 'T': // Constant suitable as a 32-bit mask operand
959     case 'U': // System V Release 4 small data area reference
960     case 't': // AND masks that can be performed by two rldic{l, r}
961               // instructions
962     case 'W': // Vector constant that does not require memory
963     case 'j': // Vector constant that is all zeros.
964       break;
965     // End FIXME.
966     }
967     return true;
968   }
969   std::string convertConstraint(const char *&Constraint) const override {
970     std::string R;
971     switch (*Constraint) {
972     case 'e':
973     case 'w':
974       // Two-character constraint; add "^" hint for later parsing.
975       R = std::string("^") + std::string(Constraint, 2);
976       Constraint++;
977       break;
978     default:
979       return TargetInfo::convertConstraint(Constraint);
980     }
981     return R;
982   }
983   const char *getClobbers() const override {
984     return "";
985   }
986   int getEHDataRegisterNumber(unsigned RegNo) const override {
987     if (RegNo == 0) return 3;
988     if (RegNo == 1) return 4;
989     return -1;
990   }
991 
992   bool hasSjLjLowering() const override {
993     return true;
994   }
995 
996   bool useFloat128ManglingForLongDouble() const override {
997     return LongDoubleWidth == 128 &&
998            LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble &&
999            getTriple().isOSBinFormatELF();
1000   }
1001 };
1002 
1003 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
1004 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1005 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1006                                               ALL_LANGUAGES },
1007 #include "clang/Basic/BuiltinsPPC.def"
1008 };
1009 
1010 /// handleTargetFeatures - Perform initialization based on the user
1011 /// configured set of features.
1012 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
1013                                          DiagnosticsEngine &Diags) {
1014   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
1015     // Ignore disabled features.
1016     if (Features[i][0] == '-')
1017       continue;
1018 
1019     StringRef Feature = StringRef(Features[i]).substr(1);
1020 
1021     if (Feature == "vsx") {
1022       HasVSX = true;
1023       continue;
1024     }
1025 
1026     if (Feature == "bpermd") {
1027       HasBPERMD = true;
1028       continue;
1029     }
1030 
1031     if (Feature == "extdiv") {
1032       HasExtDiv = true;
1033       continue;
1034     }
1035 
1036     if (Feature == "power8-vector") {
1037       HasP8Vector = true;
1038       HasVSX = true;
1039       continue;
1040     }
1041 
1042     if (Feature == "crypto") {
1043       HasP8Crypto = true;
1044       continue;
1045     }
1046 
1047     if (Feature == "direct-move") {
1048       HasDirectMove = true;
1049       HasVSX = true;
1050       continue;
1051     }
1052 
1053     if (Feature == "qpx") {
1054       HasQPX = true;
1055       continue;
1056     }
1057 
1058     if (Feature == "htm") {
1059       HasHTM = true;
1060       continue;
1061     }
1062 
1063     // TODO: Finish this list and add an assert that we've handled them
1064     // all.
1065   }
1066 
1067   return true;
1068 }
1069 
1070 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
1071 /// #defines that are not tied to a specific subtarget.
1072 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
1073                                      MacroBuilder &Builder) const {
1074   // Target identification.
1075   Builder.defineMacro("__ppc__");
1076   Builder.defineMacro("__PPC__");
1077   Builder.defineMacro("_ARCH_PPC");
1078   Builder.defineMacro("__powerpc__");
1079   Builder.defineMacro("__POWERPC__");
1080   if (PointerWidth == 64) {
1081     Builder.defineMacro("_ARCH_PPC64");
1082     Builder.defineMacro("__powerpc64__");
1083     Builder.defineMacro("__ppc64__");
1084     Builder.defineMacro("__PPC64__");
1085   }
1086 
1087   // Target properties.
1088   if (getTriple().getArch() == llvm::Triple::ppc64le) {
1089     Builder.defineMacro("_LITTLE_ENDIAN");
1090   } else {
1091     if (getTriple().getOS() != llvm::Triple::NetBSD &&
1092         getTriple().getOS() != llvm::Triple::OpenBSD)
1093       Builder.defineMacro("_BIG_ENDIAN");
1094   }
1095 
1096   // ABI options.
1097   if (ABI == "elfv1" || ABI == "elfv1-qpx")
1098     Builder.defineMacro("_CALL_ELF", "1");
1099   if (ABI == "elfv2")
1100     Builder.defineMacro("_CALL_ELF", "2");
1101 
1102   // Subtarget options.
1103   Builder.defineMacro("__NATURAL_ALIGNMENT__");
1104   Builder.defineMacro("__REGISTER_PREFIX__", "");
1105 
1106   // FIXME: Should be controlled by command line option.
1107   if (LongDoubleWidth == 128)
1108     Builder.defineMacro("__LONG_DOUBLE_128__");
1109 
1110   if (Opts.AltiVec) {
1111     Builder.defineMacro("__VEC__", "10206");
1112     Builder.defineMacro("__ALTIVEC__");
1113   }
1114 
1115   // CPU identification.
1116   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
1117     .Case("440",   ArchDefineName)
1118     .Case("450",   ArchDefineName | ArchDefine440)
1119     .Case("601",   ArchDefineName)
1120     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1121     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1122     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1123     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1124     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1125     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1126     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1127     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1128     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1129     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1130     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1131     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1132                      | ArchDefinePpcsq)
1133     .Case("a2",    ArchDefineA2)
1134     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1135     .Case("pwr3",  ArchDefinePpcgr)
1136     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1137     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1138                      | ArchDefinePpcsq)
1139     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1140                      | ArchDefinePpcgr | ArchDefinePpcsq)
1141     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1142                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1143     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1144                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1145                      | ArchDefinePpcsq)
1146     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1147                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1148                      | ArchDefinePpcgr | ArchDefinePpcsq)
1149     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1150                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1151                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1152     .Case("power3",  ArchDefinePpcgr)
1153     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1154     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1155                        | ArchDefinePpcsq)
1156     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1157                        | ArchDefinePpcgr | ArchDefinePpcsq)
1158     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1159                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1160     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1161                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1162                        | ArchDefinePpcsq)
1163     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1164                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1165                        | ArchDefinePpcgr | ArchDefinePpcsq)
1166     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1167                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1168                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1169     .Default(ArchDefineNone);
1170 
1171   if (defs & ArchDefineName)
1172     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1173   if (defs & ArchDefinePpcgr)
1174     Builder.defineMacro("_ARCH_PPCGR");
1175   if (defs & ArchDefinePpcsq)
1176     Builder.defineMacro("_ARCH_PPCSQ");
1177   if (defs & ArchDefine440)
1178     Builder.defineMacro("_ARCH_440");
1179   if (defs & ArchDefine603)
1180     Builder.defineMacro("_ARCH_603");
1181   if (defs & ArchDefine604)
1182     Builder.defineMacro("_ARCH_604");
1183   if (defs & ArchDefinePwr4)
1184     Builder.defineMacro("_ARCH_PWR4");
1185   if (defs & ArchDefinePwr5)
1186     Builder.defineMacro("_ARCH_PWR5");
1187   if (defs & ArchDefinePwr5x)
1188     Builder.defineMacro("_ARCH_PWR5X");
1189   if (defs & ArchDefinePwr6)
1190     Builder.defineMacro("_ARCH_PWR6");
1191   if (defs & ArchDefinePwr6x)
1192     Builder.defineMacro("_ARCH_PWR6X");
1193   if (defs & ArchDefinePwr7)
1194     Builder.defineMacro("_ARCH_PWR7");
1195   if (defs & ArchDefinePwr8)
1196     Builder.defineMacro("_ARCH_PWR8");
1197   if (defs & ArchDefineA2)
1198     Builder.defineMacro("_ARCH_A2");
1199   if (defs & ArchDefineA2q) {
1200     Builder.defineMacro("_ARCH_A2Q");
1201     Builder.defineMacro("_ARCH_QP");
1202   }
1203 
1204   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1205     Builder.defineMacro("__bg__");
1206     Builder.defineMacro("__THW_BLUEGENE__");
1207     Builder.defineMacro("__bgq__");
1208     Builder.defineMacro("__TOS_BGQ__");
1209   }
1210 
1211   if (HasVSX)
1212     Builder.defineMacro("__VSX__");
1213   if (HasP8Vector)
1214     Builder.defineMacro("__POWER8_VECTOR__");
1215   if (HasP8Crypto)
1216     Builder.defineMacro("__CRYPTO__");
1217   if (HasHTM)
1218     Builder.defineMacro("__HTM__");
1219   if (getTriple().getArch() == llvm::Triple::ppc64le ||
1220       (defs & ArchDefinePwr8) || (CPU == "pwr8")) {
1221     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
1222     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
1223     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
1224     if (PointerWidth == 64)
1225       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
1226   }
1227 
1228   // FIXME: The following are not yet generated here by Clang, but are
1229   //        generated by GCC:
1230   //
1231   //   _SOFT_FLOAT_
1232   //   __RECIP_PRECISION__
1233   //   __APPLE_ALTIVEC__
1234   //   __RECIP__
1235   //   __RECIPF__
1236   //   __RSQRTE__
1237   //   __RSQRTEF__
1238   //   _SOFT_DOUBLE_
1239   //   __NO_LWSYNC__
1240   //   __HAVE_BSWAP__
1241   //   __LONGDOUBLE128
1242   //   __CMODEL_MEDIUM__
1243   //   __CMODEL_LARGE__
1244   //   _CALL_SYSV
1245   //   _CALL_DARWIN
1246   //   __NO_FPRS__
1247 }
1248 
1249 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1250   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1251     .Case("7400", true)
1252     .Case("g4", true)
1253     .Case("7450", true)
1254     .Case("g4+", true)
1255     .Case("970", true)
1256     .Case("g5", true)
1257     .Case("pwr6", true)
1258     .Case("pwr7", true)
1259     .Case("pwr8", true)
1260     .Case("ppc64", true)
1261     .Case("ppc64le", true)
1262     .Default(false);
1263 
1264   Features["qpx"] = (CPU == "a2q");
1265   Features["crypto"] = llvm::StringSwitch<bool>(CPU)
1266     .Case("ppc64le", true)
1267     .Case("pwr8", true)
1268     .Default(false);
1269   Features["power8-vector"] = llvm::StringSwitch<bool>(CPU)
1270     .Case("ppc64le", true)
1271     .Case("pwr8", true)
1272     .Default(false);
1273   Features["bpermd"] = llvm::StringSwitch<bool>(CPU)
1274     .Case("ppc64le", true)
1275     .Case("pwr8", true)
1276     .Case("pwr7", true)
1277     .Default(false);
1278   Features["extdiv"] = llvm::StringSwitch<bool>(CPU)
1279     .Case("ppc64le", true)
1280     .Case("pwr8", true)
1281     .Case("pwr7", true)
1282     .Default(false);
1283   Features["direct-move"] = llvm::StringSwitch<bool>(CPU)
1284     .Case("ppc64le", true)
1285     .Case("pwr8", true)
1286     .Default(false);
1287 }
1288 
1289 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1290   return llvm::StringSwitch<bool>(Feature)
1291     .Case("powerpc", true)
1292     .Case("vsx", HasVSX)
1293     .Case("power8-vector", HasP8Vector)
1294     .Case("crypto", HasP8Crypto)
1295     .Case("direct-move", HasDirectMove)
1296     .Case("qpx", HasQPX)
1297     .Case("htm", HasHTM)
1298     .Case("bpermd", HasBPERMD)
1299     .Case("extdiv", HasExtDiv)
1300     .Default(false);
1301 }
1302 
1303 const char * const PPCTargetInfo::GCCRegNames[] = {
1304   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1305   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1306   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1307   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1308   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1309   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1310   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1311   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1312   "mq", "lr", "ctr", "ap",
1313   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1314   "xer",
1315   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1316   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1317   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1318   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1319   "vrsave", "vscr",
1320   "spe_acc", "spefscr",
1321   "sfp"
1322 };
1323 
1324 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1325                                    unsigned &NumNames) const {
1326   Names = GCCRegNames;
1327   NumNames = llvm::array_lengthof(GCCRegNames);
1328 }
1329 
1330 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1331   // While some of these aliases do map to different registers
1332   // they still share the same register name.
1333   { { "0" }, "r0" },
1334   { { "1"}, "r1" },
1335   { { "2" }, "r2" },
1336   { { "3" }, "r3" },
1337   { { "4" }, "r4" },
1338   { { "5" }, "r5" },
1339   { { "6" }, "r6" },
1340   { { "7" }, "r7" },
1341   { { "8" }, "r8" },
1342   { { "9" }, "r9" },
1343   { { "10" }, "r10" },
1344   { { "11" }, "r11" },
1345   { { "12" }, "r12" },
1346   { { "13" }, "r13" },
1347   { { "14" }, "r14" },
1348   { { "15" }, "r15" },
1349   { { "16" }, "r16" },
1350   { { "17" }, "r17" },
1351   { { "18" }, "r18" },
1352   { { "19" }, "r19" },
1353   { { "20" }, "r20" },
1354   { { "21" }, "r21" },
1355   { { "22" }, "r22" },
1356   { { "23" }, "r23" },
1357   { { "24" }, "r24" },
1358   { { "25" }, "r25" },
1359   { { "26" }, "r26" },
1360   { { "27" }, "r27" },
1361   { { "28" }, "r28" },
1362   { { "29" }, "r29" },
1363   { { "30" }, "r30" },
1364   { { "31" }, "r31" },
1365   { { "fr0" }, "f0" },
1366   { { "fr1" }, "f1" },
1367   { { "fr2" }, "f2" },
1368   { { "fr3" }, "f3" },
1369   { { "fr4" }, "f4" },
1370   { { "fr5" }, "f5" },
1371   { { "fr6" }, "f6" },
1372   { { "fr7" }, "f7" },
1373   { { "fr8" }, "f8" },
1374   { { "fr9" }, "f9" },
1375   { { "fr10" }, "f10" },
1376   { { "fr11" }, "f11" },
1377   { { "fr12" }, "f12" },
1378   { { "fr13" }, "f13" },
1379   { { "fr14" }, "f14" },
1380   { { "fr15" }, "f15" },
1381   { { "fr16" }, "f16" },
1382   { { "fr17" }, "f17" },
1383   { { "fr18" }, "f18" },
1384   { { "fr19" }, "f19" },
1385   { { "fr20" }, "f20" },
1386   { { "fr21" }, "f21" },
1387   { { "fr22" }, "f22" },
1388   { { "fr23" }, "f23" },
1389   { { "fr24" }, "f24" },
1390   { { "fr25" }, "f25" },
1391   { { "fr26" }, "f26" },
1392   { { "fr27" }, "f27" },
1393   { { "fr28" }, "f28" },
1394   { { "fr29" }, "f29" },
1395   { { "fr30" }, "f30" },
1396   { { "fr31" }, "f31" },
1397   { { "cc" }, "cr0" },
1398 };
1399 
1400 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1401                                      unsigned &NumAliases) const {
1402   Aliases = GCCRegAliases;
1403   NumAliases = llvm::array_lengthof(GCCRegAliases);
1404 }
1405 
1406 class PPC32TargetInfo : public PPCTargetInfo {
1407 public:
1408   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1409     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1410 
1411     switch (getTriple().getOS()) {
1412     case llvm::Triple::Linux:
1413     case llvm::Triple::FreeBSD:
1414     case llvm::Triple::NetBSD:
1415       SizeType = UnsignedInt;
1416       PtrDiffType = SignedInt;
1417       IntPtrType = SignedInt;
1418       break;
1419     default:
1420       break;
1421     }
1422 
1423     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1424       LongDoubleWidth = LongDoubleAlign = 64;
1425       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1426     }
1427 
1428     // PPC32 supports atomics up to 4 bytes.
1429     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1430   }
1431 
1432   BuiltinVaListKind getBuiltinVaListKind() const override {
1433     // This is the ELF definition, and is overridden by the Darwin sub-target
1434     return TargetInfo::PowerABIBuiltinVaList;
1435   }
1436 };
1437 
1438 // Note: ABI differences may eventually require us to have a separate
1439 // TargetInfo for little endian.
1440 class PPC64TargetInfo : public PPCTargetInfo {
1441 public:
1442   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1443     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1444     IntMaxType = SignedLong;
1445     Int64Type = SignedLong;
1446 
1447     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1448       DescriptionString = "e-m:e-i64:64-n32:64";
1449       ABI = "elfv2";
1450     } else {
1451       DescriptionString = "E-m:e-i64:64-n32:64";
1452       ABI = "elfv1";
1453     }
1454 
1455     switch (getTriple().getOS()) {
1456     case llvm::Triple::FreeBSD:
1457       LongDoubleWidth = LongDoubleAlign = 64;
1458       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1459       break;
1460     case llvm::Triple::NetBSD:
1461       IntMaxType = SignedLongLong;
1462       Int64Type = SignedLongLong;
1463       break;
1464     default:
1465       break;
1466     }
1467 
1468     // PPC64 supports atomics up to 8 bytes.
1469     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1470   }
1471   BuiltinVaListKind getBuiltinVaListKind() const override {
1472     return TargetInfo::CharPtrBuiltinVaList;
1473   }
1474   // PPC64 Linux-specifc ABI options.
1475   bool setABI(const std::string &Name) override {
1476     if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") {
1477       ABI = Name;
1478       return true;
1479     }
1480     return false;
1481   }
1482 };
1483 
1484 class DarwinPPC32TargetInfo :
1485   public DarwinTargetInfo<PPC32TargetInfo> {
1486 public:
1487   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1488       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1489     HasAlignMac68kSupport = true;
1490     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1491     PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726
1492     LongLongAlign = 32;
1493     SuitableAlign = 128;
1494     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1495   }
1496   BuiltinVaListKind getBuiltinVaListKind() const override {
1497     return TargetInfo::CharPtrBuiltinVaList;
1498   }
1499 };
1500 
1501 class DarwinPPC64TargetInfo :
1502   public DarwinTargetInfo<PPC64TargetInfo> {
1503 public:
1504   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1505       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1506     HasAlignMac68kSupport = true;
1507     SuitableAlign = 128;
1508     DescriptionString = "E-m:o-i64:64-n32:64";
1509   }
1510 };
1511 
1512   static const unsigned NVPTXAddrSpaceMap[] = {
1513     1,    // opencl_global
1514     3,    // opencl_local
1515     4,    // opencl_constant
1516     // FIXME: generic has to be added to the target
1517     0,    // opencl_generic
1518     1,    // cuda_device
1519     4,    // cuda_constant
1520     3,    // cuda_shared
1521   };
1522   class NVPTXTargetInfo : public TargetInfo {
1523     static const char * const GCCRegNames[];
1524     static const Builtin::Info BuiltinInfo[];
1525 
1526   // The GPU profiles supported by the NVPTX backend
1527   enum GPUKind {
1528     GK_NONE,
1529     GK_SM20,
1530     GK_SM21,
1531     GK_SM30,
1532     GK_SM35,
1533     GK_SM37,
1534   } GPU;
1535 
1536   public:
1537     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1538       BigEndian = false;
1539       TLSSupported = false;
1540       LongWidth = LongAlign = 64;
1541       AddrSpaceMap = &NVPTXAddrSpaceMap;
1542       UseAddrSpaceMapMangling = true;
1543       // Define available target features
1544       // These must be defined in sorted order!
1545       NoAsmVariants = true;
1546       // Set the default GPU to sm20
1547       GPU = GK_SM20;
1548     }
1549     void getTargetDefines(const LangOptions &Opts,
1550                           MacroBuilder &Builder) const override {
1551       Builder.defineMacro("__PTX__");
1552       Builder.defineMacro("__NVPTX__");
1553       if (Opts.CUDAIsDevice) {
1554         // Set __CUDA_ARCH__ for the GPU specified.
1555         std::string CUDAArchCode;
1556         switch (GPU) {
1557         case GK_SM20:
1558           CUDAArchCode = "200";
1559           break;
1560         case GK_SM21:
1561           CUDAArchCode = "210";
1562           break;
1563         case GK_SM30:
1564           CUDAArchCode = "300";
1565           break;
1566         case GK_SM35:
1567           CUDAArchCode = "350";
1568           break;
1569         case GK_SM37:
1570           CUDAArchCode = "370";
1571           break;
1572         default:
1573           llvm_unreachable("Unhandled target CPU");
1574         }
1575         Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode);
1576       }
1577     }
1578     void getTargetBuiltins(const Builtin::Info *&Records,
1579                            unsigned &NumRecords) const override {
1580       Records = BuiltinInfo;
1581       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1582     }
1583     bool hasFeature(StringRef Feature) const override {
1584       return Feature == "ptx" || Feature == "nvptx";
1585     }
1586 
1587     void getGCCRegNames(const char * const *&Names,
1588                         unsigned &NumNames) const override;
1589     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1590                                   unsigned &NumAliases) const override {
1591       // No aliases.
1592       Aliases = nullptr;
1593       NumAliases = 0;
1594     }
1595     bool
1596     validateAsmConstraint(const char *&Name,
1597                           TargetInfo::ConstraintInfo &Info) const override {
1598       switch (*Name) {
1599       default: return false;
1600       case 'c':
1601       case 'h':
1602       case 'r':
1603       case 'l':
1604       case 'f':
1605       case 'd':
1606         Info.setAllowsRegister();
1607         return true;
1608       }
1609     }
1610     const char *getClobbers() const override {
1611       // FIXME: Is this really right?
1612       return "";
1613     }
1614     BuiltinVaListKind getBuiltinVaListKind() const override {
1615       // FIXME: implement
1616       return TargetInfo::CharPtrBuiltinVaList;
1617     }
1618     bool setCPU(const std::string &Name) override {
1619       GPU = llvm::StringSwitch<GPUKind>(Name)
1620                 .Case("sm_20", GK_SM20)
1621                 .Case("sm_21", GK_SM21)
1622                 .Case("sm_30", GK_SM30)
1623                 .Case("sm_35", GK_SM35)
1624                 .Case("sm_37", GK_SM37)
1625                 .Default(GK_NONE);
1626 
1627       return GPU != GK_NONE;
1628     }
1629   };
1630 
1631   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1632 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1633 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1634                                               ALL_LANGUAGES },
1635 #include "clang/Basic/BuiltinsNVPTX.def"
1636   };
1637 
1638   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1639     "r0"
1640   };
1641 
1642   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1643                                      unsigned &NumNames) const {
1644     Names = GCCRegNames;
1645     NumNames = llvm::array_lengthof(GCCRegNames);
1646   }
1647 
1648   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1649   public:
1650     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1651       PointerWidth = PointerAlign = 32;
1652       SizeType = TargetInfo::UnsignedInt;
1653       PtrDiffType = TargetInfo::SignedInt;
1654       IntPtrType = TargetInfo::SignedInt;
1655       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1656     }
1657   };
1658 
1659   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1660   public:
1661     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1662       PointerWidth = PointerAlign = 64;
1663       SizeType = TargetInfo::UnsignedLong;
1664       PtrDiffType = TargetInfo::SignedLong;
1665       IntPtrType = TargetInfo::SignedLong;
1666       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1667     }
1668   };
1669 
1670 static const unsigned R600AddrSpaceMap[] = {
1671   1,    // opencl_global
1672   3,    // opencl_local
1673   2,    // opencl_constant
1674   4,    // opencl_generic
1675   1,    // cuda_device
1676   2,    // cuda_constant
1677   3     // cuda_shared
1678 };
1679 
1680 // If you edit the description strings, make sure you update
1681 // getPointerWidthV().
1682 
1683 static const char *DescriptionStringR600 =
1684   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1685   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1686 
1687 static const char *DescriptionStringR600DoubleOps =
1688   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1689   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1690 
1691 static const char *DescriptionStringSI =
1692   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1693   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1694   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1695 
1696 class R600TargetInfo : public TargetInfo {
1697   static const Builtin::Info BuiltinInfo[];
1698   static const char * const GCCRegNames[];
1699 
1700   /// \brief The GPU profiles supported by the R600 target.
1701   enum GPUKind {
1702     GK_NONE,
1703     GK_R600,
1704     GK_R600_DOUBLE_OPS,
1705     GK_R700,
1706     GK_R700_DOUBLE_OPS,
1707     GK_EVERGREEN,
1708     GK_EVERGREEN_DOUBLE_OPS,
1709     GK_NORTHERN_ISLANDS,
1710     GK_CAYMAN,
1711     GK_SOUTHERN_ISLANDS,
1712     GK_SEA_ISLANDS
1713   } GPU;
1714 
1715   bool hasFP64:1;
1716   bool hasFMAF:1;
1717   bool hasLDEXPF:1;
1718 
1719 public:
1720   R600TargetInfo(const llvm::Triple &Triple)
1721       : TargetInfo(Triple) {
1722 
1723     if (Triple.getArch() == llvm::Triple::amdgcn) {
1724       DescriptionString = DescriptionStringSI;
1725       GPU = GK_SOUTHERN_ISLANDS;
1726       hasFP64 = true;
1727       hasFMAF = true;
1728       hasLDEXPF = true;
1729     } else {
1730       DescriptionString = DescriptionStringR600;
1731       GPU = GK_R600;
1732       hasFP64 = false;
1733       hasFMAF = false;
1734       hasLDEXPF = false;
1735     }
1736     AddrSpaceMap = &R600AddrSpaceMap;
1737     UseAddrSpaceMapMangling = true;
1738   }
1739 
1740   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1741     if (GPU <= GK_CAYMAN)
1742       return 32;
1743 
1744     switch(AddrSpace) {
1745       default:
1746         return 64;
1747       case 0:
1748       case 3:
1749       case 5:
1750         return 32;
1751     }
1752   }
1753 
1754   const char * getClobbers() const override {
1755     return "";
1756   }
1757 
1758   void getGCCRegNames(const char * const *&Names,
1759                       unsigned &NumNames) const override;
1760 
1761   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1762                         unsigned &NumAliases) const override {
1763     Aliases = nullptr;
1764     NumAliases = 0;
1765   }
1766 
1767   bool validateAsmConstraint(const char *&Name,
1768                              TargetInfo::ConstraintInfo &info) const override {
1769     return true;
1770   }
1771 
1772   void getTargetBuiltins(const Builtin::Info *&Records,
1773                          unsigned &NumRecords) const override {
1774     Records = BuiltinInfo;
1775     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1776   }
1777 
1778   void getTargetDefines(const LangOptions &Opts,
1779                         MacroBuilder &Builder) const override {
1780     Builder.defineMacro("__R600__");
1781     if (hasFMAF)
1782       Builder.defineMacro("__HAS_FMAF__");
1783     if (hasLDEXPF)
1784       Builder.defineMacro("__HAS_LDEXPF__");
1785     if (hasFP64 && Opts.OpenCL) {
1786       Builder.defineMacro("cl_khr_fp64");
1787     }
1788   }
1789 
1790   BuiltinVaListKind getBuiltinVaListKind() const override {
1791     return TargetInfo::CharPtrBuiltinVaList;
1792   }
1793 
1794   bool setCPU(const std::string &Name) override {
1795     GPU = llvm::StringSwitch<GPUKind>(Name)
1796       .Case("r600" ,    GK_R600)
1797       .Case("rv610",    GK_R600)
1798       .Case("rv620",    GK_R600)
1799       .Case("rv630",    GK_R600)
1800       .Case("rv635",    GK_R600)
1801       .Case("rs780",    GK_R600)
1802       .Case("rs880",    GK_R600)
1803       .Case("rv670",    GK_R600_DOUBLE_OPS)
1804       .Case("rv710",    GK_R700)
1805       .Case("rv730",    GK_R700)
1806       .Case("rv740",    GK_R700_DOUBLE_OPS)
1807       .Case("rv770",    GK_R700_DOUBLE_OPS)
1808       .Case("palm",     GK_EVERGREEN)
1809       .Case("cedar",    GK_EVERGREEN)
1810       .Case("sumo",     GK_EVERGREEN)
1811       .Case("sumo2",    GK_EVERGREEN)
1812       .Case("redwood",  GK_EVERGREEN)
1813       .Case("juniper",  GK_EVERGREEN)
1814       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1815       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1816       .Case("barts",    GK_NORTHERN_ISLANDS)
1817       .Case("turks",    GK_NORTHERN_ISLANDS)
1818       .Case("caicos",   GK_NORTHERN_ISLANDS)
1819       .Case("cayman",   GK_CAYMAN)
1820       .Case("aruba",    GK_CAYMAN)
1821       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1822       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1823       .Case("verde",    GK_SOUTHERN_ISLANDS)
1824       .Case("oland",    GK_SOUTHERN_ISLANDS)
1825       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1826       .Case("bonaire",  GK_SEA_ISLANDS)
1827       .Case("kabini",   GK_SEA_ISLANDS)
1828       .Case("kaveri",   GK_SEA_ISLANDS)
1829       .Case("hawaii",   GK_SEA_ISLANDS)
1830       .Case("mullins",  GK_SEA_ISLANDS)
1831       .Default(GK_NONE);
1832 
1833     if (GPU == GK_NONE) {
1834       return false;
1835     }
1836 
1837     // Set the correct data layout
1838     switch (GPU) {
1839     case GK_NONE:
1840     case GK_R600:
1841     case GK_R700:
1842     case GK_EVERGREEN:
1843     case GK_NORTHERN_ISLANDS:
1844       DescriptionString = DescriptionStringR600;
1845       hasFP64 = false;
1846       hasFMAF = false;
1847       hasLDEXPF = false;
1848       break;
1849     case GK_R600_DOUBLE_OPS:
1850     case GK_R700_DOUBLE_OPS:
1851     case GK_EVERGREEN_DOUBLE_OPS:
1852     case GK_CAYMAN:
1853       DescriptionString = DescriptionStringR600DoubleOps;
1854       hasFP64 = true;
1855       hasFMAF = true;
1856       hasLDEXPF = false;
1857       break;
1858     case GK_SOUTHERN_ISLANDS:
1859     case GK_SEA_ISLANDS:
1860       DescriptionString = DescriptionStringSI;
1861       hasFP64 = true;
1862       hasFMAF = true;
1863       hasLDEXPF = true;
1864       break;
1865     }
1866 
1867     return true;
1868   }
1869 };
1870 
1871 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1872 #define BUILTIN(ID, TYPE, ATTRS)                \
1873   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1874 #include "clang/Basic/BuiltinsR600.def"
1875 };
1876 const char * const R600TargetInfo::GCCRegNames[] = {
1877   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1878   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1879   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1880   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1881   "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39",
1882   "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47",
1883   "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55",
1884   "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63",
1885   "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71",
1886   "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79",
1887   "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87",
1888   "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95",
1889   "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103",
1890   "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111",
1891   "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119",
1892   "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127",
1893   "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135",
1894   "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143",
1895   "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151",
1896   "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159",
1897   "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167",
1898   "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175",
1899   "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183",
1900   "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191",
1901   "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199",
1902   "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207",
1903   "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215",
1904   "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223",
1905   "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231",
1906   "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239",
1907   "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247",
1908   "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255",
1909   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
1910   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
1911   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
1912   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
1913   "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
1914   "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
1915   "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
1916   "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
1917   "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
1918   "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
1919   "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
1920   "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
1921   "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
1922   "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
1923   "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
1924   "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127"
1925   "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi",
1926   "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi"
1927 };
1928 
1929 void R600TargetInfo::getGCCRegNames(const char * const *&Names,
1930                                     unsigned &NumNames) const {
1931   Names = GCCRegNames;
1932   NumNames = llvm::array_lengthof(GCCRegNames);
1933 }
1934 
1935 // Namespace for x86 abstract base class
1936 const Builtin::Info BuiltinInfo[] = {
1937 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1938 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1939                                               ALL_LANGUAGES },
1940 #include "clang/Basic/BuiltinsX86.def"
1941 };
1942 
1943 static const char* const GCCRegNames[] = {
1944   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1945   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1946   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1947   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1948   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1949   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1950   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1951   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1952   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1953 };
1954 
1955 const TargetInfo::AddlRegName AddlRegNames[] = {
1956   { { "al", "ah", "eax", "rax" }, 0 },
1957   { { "bl", "bh", "ebx", "rbx" }, 3 },
1958   { { "cl", "ch", "ecx", "rcx" }, 2 },
1959   { { "dl", "dh", "edx", "rdx" }, 1 },
1960   { { "esi", "rsi" }, 4 },
1961   { { "edi", "rdi" }, 5 },
1962   { { "esp", "rsp" }, 7 },
1963   { { "ebp", "rbp" }, 6 },
1964 };
1965 
1966 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1967 // most of the implementation can be shared.
1968 class X86TargetInfo : public TargetInfo {
1969   enum X86SSEEnum {
1970     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1971   } SSELevel;
1972   enum MMX3DNowEnum {
1973     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1974   } MMX3DNowLevel;
1975   enum XOPEnum {
1976     NoXOP,
1977     SSE4A,
1978     FMA4,
1979     XOP
1980   } XOPLevel;
1981 
1982   bool HasAES;
1983   bool HasPCLMUL;
1984   bool HasLZCNT;
1985   bool HasRDRND;
1986   bool HasFSGSBASE;
1987   bool HasBMI;
1988   bool HasBMI2;
1989   bool HasPOPCNT;
1990   bool HasRTM;
1991   bool HasPRFCHW;
1992   bool HasRDSEED;
1993   bool HasADX;
1994   bool HasTBM;
1995   bool HasFMA;
1996   bool HasF16C;
1997   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW,
1998       HasAVX512VL;
1999   bool HasSHA;
2000   bool HasCX16;
2001 
2002   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
2003   ///
2004   /// Each enumeration represents a particular CPU supported by Clang. These
2005   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
2006   enum CPUKind {
2007     CK_Generic,
2008 
2009     /// \name i386
2010     /// i386-generation processors.
2011     //@{
2012     CK_i386,
2013     //@}
2014 
2015     /// \name i486
2016     /// i486-generation processors.
2017     //@{
2018     CK_i486,
2019     CK_WinChipC6,
2020     CK_WinChip2,
2021     CK_C3,
2022     //@}
2023 
2024     /// \name i586
2025     /// i586-generation processors, P5 microarchitecture based.
2026     //@{
2027     CK_i586,
2028     CK_Pentium,
2029     CK_PentiumMMX,
2030     //@}
2031 
2032     /// \name i686
2033     /// i686-generation processors, P6 / Pentium M microarchitecture based.
2034     //@{
2035     CK_i686,
2036     CK_PentiumPro,
2037     CK_Pentium2,
2038     CK_Pentium3,
2039     CK_Pentium3M,
2040     CK_PentiumM,
2041     CK_C3_2,
2042 
2043     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
2044     /// Clang however has some logic to suport this.
2045     // FIXME: Warn, deprecate, and potentially remove this.
2046     CK_Yonah,
2047     //@}
2048 
2049     /// \name Netburst
2050     /// Netburst microarchitecture based processors.
2051     //@{
2052     CK_Pentium4,
2053     CK_Pentium4M,
2054     CK_Prescott,
2055     CK_Nocona,
2056     //@}
2057 
2058     /// \name Core
2059     /// Core microarchitecture based processors.
2060     //@{
2061     CK_Core2,
2062 
2063     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
2064     /// codename which GCC no longer accepts as an option to -march, but Clang
2065     /// has some logic for recognizing it.
2066     // FIXME: Warn, deprecate, and potentially remove this.
2067     CK_Penryn,
2068     //@}
2069 
2070     /// \name Atom
2071     /// Atom processors
2072     //@{
2073     CK_Bonnell,
2074     CK_Silvermont,
2075     //@}
2076 
2077     /// \name Nehalem
2078     /// Nehalem microarchitecture based processors.
2079     CK_Nehalem,
2080 
2081     /// \name Westmere
2082     /// Westmere microarchitecture based processors.
2083     CK_Westmere,
2084 
2085     /// \name Sandy Bridge
2086     /// Sandy Bridge microarchitecture based processors.
2087     CK_SandyBridge,
2088 
2089     /// \name Ivy Bridge
2090     /// Ivy Bridge microarchitecture based processors.
2091     CK_IvyBridge,
2092 
2093     /// \name Haswell
2094     /// Haswell microarchitecture based processors.
2095     CK_Haswell,
2096 
2097     /// \name Broadwell
2098     /// Broadwell microarchitecture based processors.
2099     CK_Broadwell,
2100 
2101     /// \name Skylake
2102     /// Skylake microarchitecture based processors.
2103     CK_Skylake,
2104 
2105     /// \name Knights Landing
2106     /// Knights Landing processor.
2107     CK_KNL,
2108 
2109     /// \name K6
2110     /// K6 architecture processors.
2111     //@{
2112     CK_K6,
2113     CK_K6_2,
2114     CK_K6_3,
2115     //@}
2116 
2117     /// \name K7
2118     /// K7 architecture processors.
2119     //@{
2120     CK_Athlon,
2121     CK_AthlonThunderbird,
2122     CK_Athlon4,
2123     CK_AthlonXP,
2124     CK_AthlonMP,
2125     //@}
2126 
2127     /// \name K8
2128     /// K8 architecture processors.
2129     //@{
2130     CK_Athlon64,
2131     CK_Athlon64SSE3,
2132     CK_AthlonFX,
2133     CK_K8,
2134     CK_K8SSE3,
2135     CK_Opteron,
2136     CK_OpteronSSE3,
2137     CK_AMDFAM10,
2138     //@}
2139 
2140     /// \name Bobcat
2141     /// Bobcat architecture processors.
2142     //@{
2143     CK_BTVER1,
2144     CK_BTVER2,
2145     //@}
2146 
2147     /// \name Bulldozer
2148     /// Bulldozer architecture processors.
2149     //@{
2150     CK_BDVER1,
2151     CK_BDVER2,
2152     CK_BDVER3,
2153     CK_BDVER4,
2154     //@}
2155 
2156     /// This specification is deprecated and will be removed in the future.
2157     /// Users should prefer \see CK_K8.
2158     // FIXME: Warn on this when the CPU is set to it.
2159     //@{
2160     CK_x86_64,
2161     //@}
2162 
2163     /// \name Geode
2164     /// Geode processors.
2165     //@{
2166     CK_Geode
2167     //@}
2168   } CPU;
2169 
2170   enum FPMathKind {
2171     FP_Default,
2172     FP_SSE,
2173     FP_387
2174   } FPMath;
2175 
2176 public:
2177   X86TargetInfo(const llvm::Triple &Triple)
2178       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
2179         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
2180         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
2181         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
2182         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
2183         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
2184         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
2185         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
2186     BigEndian = false;
2187     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
2188   }
2189   unsigned getFloatEvalMethod() const override {
2190     // X87 evaluates with 80 bits "long double" precision.
2191     return SSELevel == NoSSE ? 2 : 0;
2192   }
2193   void getTargetBuiltins(const Builtin::Info *&Records,
2194                                  unsigned &NumRecords) const override {
2195     Records = BuiltinInfo;
2196     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
2197   }
2198   void getGCCRegNames(const char * const *&Names,
2199                       unsigned &NumNames) const override {
2200     Names = GCCRegNames;
2201     NumNames = llvm::array_lengthof(GCCRegNames);
2202   }
2203   void getGCCRegAliases(const GCCRegAlias *&Aliases,
2204                         unsigned &NumAliases) const override {
2205     Aliases = nullptr;
2206     NumAliases = 0;
2207   }
2208   void getGCCAddlRegNames(const AddlRegName *&Names,
2209                           unsigned &NumNames) const override {
2210     Names = AddlRegNames;
2211     NumNames = llvm::array_lengthof(AddlRegNames);
2212   }
2213   bool validateAsmConstraint(const char *&Name,
2214                              TargetInfo::ConstraintInfo &info) const override;
2215 
2216   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
2217 
2218   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
2219 
2220   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
2221 
2222   std::string convertConstraint(const char *&Constraint) const override;
2223   const char *getClobbers() const override {
2224     return "~{dirflag},~{fpsr},~{flags}";
2225   }
2226   void getTargetDefines(const LangOptions &Opts,
2227                         MacroBuilder &Builder) const override;
2228   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
2229                           bool Enabled);
2230   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
2231                           bool Enabled);
2232   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2233                           bool Enabled);
2234   void setFeatureEnabled(llvm::StringMap<bool> &Features,
2235                          StringRef Name, bool Enabled) const override {
2236     setFeatureEnabledImpl(Features, Name, Enabled);
2237   }
2238   // This exists purely to cut down on the number of virtual calls in
2239   // getDefaultFeatures which calls this repeatedly.
2240   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2241                                     StringRef Name, bool Enabled);
2242   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
2243   bool hasFeature(StringRef Feature) const override;
2244   bool handleTargetFeatures(std::vector<std::string> &Features,
2245                             DiagnosticsEngine &Diags) override;
2246   StringRef getABI() const override {
2247     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
2248       return "avx";
2249     else if (getTriple().getArch() == llvm::Triple::x86 &&
2250              MMX3DNowLevel == NoMMX3DNow)
2251       return "no-mmx";
2252     return "";
2253   }
2254   bool setCPU(const std::string &Name) override {
2255     CPU = llvm::StringSwitch<CPUKind>(Name)
2256       .Case("i386", CK_i386)
2257       .Case("i486", CK_i486)
2258       .Case("winchip-c6", CK_WinChipC6)
2259       .Case("winchip2", CK_WinChip2)
2260       .Case("c3", CK_C3)
2261       .Case("i586", CK_i586)
2262       .Case("pentium", CK_Pentium)
2263       .Case("pentium-mmx", CK_PentiumMMX)
2264       .Case("i686", CK_i686)
2265       .Case("pentiumpro", CK_PentiumPro)
2266       .Case("pentium2", CK_Pentium2)
2267       .Case("pentium3", CK_Pentium3)
2268       .Case("pentium3m", CK_Pentium3M)
2269       .Case("pentium-m", CK_PentiumM)
2270       .Case("c3-2", CK_C3_2)
2271       .Case("yonah", CK_Yonah)
2272       .Case("pentium4", CK_Pentium4)
2273       .Case("pentium4m", CK_Pentium4M)
2274       .Case("prescott", CK_Prescott)
2275       .Case("nocona", CK_Nocona)
2276       .Case("core2", CK_Core2)
2277       .Case("penryn", CK_Penryn)
2278       .Case("bonnell", CK_Bonnell)
2279       .Case("atom", CK_Bonnell) // Legacy name.
2280       .Case("silvermont", CK_Silvermont)
2281       .Case("slm", CK_Silvermont) // Legacy name.
2282       .Case("nehalem", CK_Nehalem)
2283       .Case("corei7", CK_Nehalem) // Legacy name.
2284       .Case("westmere", CK_Westmere)
2285       .Case("sandybridge", CK_SandyBridge)
2286       .Case("corei7-avx", CK_SandyBridge) // Legacy name.
2287       .Case("ivybridge", CK_IvyBridge)
2288       .Case("core-avx-i", CK_IvyBridge) // Legacy name.
2289       .Case("haswell", CK_Haswell)
2290       .Case("core-avx2", CK_Haswell) // Legacy name.
2291       .Case("broadwell", CK_Broadwell)
2292       .Case("skylake", CK_Skylake)
2293       .Case("skx", CK_Skylake) // Legacy name.
2294       .Case("knl", CK_KNL)
2295       .Case("k6", CK_K6)
2296       .Case("k6-2", CK_K6_2)
2297       .Case("k6-3", CK_K6_3)
2298       .Case("athlon", CK_Athlon)
2299       .Case("athlon-tbird", CK_AthlonThunderbird)
2300       .Case("athlon-4", CK_Athlon4)
2301       .Case("athlon-xp", CK_AthlonXP)
2302       .Case("athlon-mp", CK_AthlonMP)
2303       .Case("athlon64", CK_Athlon64)
2304       .Case("athlon64-sse3", CK_Athlon64SSE3)
2305       .Case("athlon-fx", CK_AthlonFX)
2306       .Case("k8", CK_K8)
2307       .Case("k8-sse3", CK_K8SSE3)
2308       .Case("opteron", CK_Opteron)
2309       .Case("opteron-sse3", CK_OpteronSSE3)
2310       .Case("barcelona", CK_AMDFAM10)
2311       .Case("amdfam10", CK_AMDFAM10)
2312       .Case("btver1", CK_BTVER1)
2313       .Case("btver2", CK_BTVER2)
2314       .Case("bdver1", CK_BDVER1)
2315       .Case("bdver2", CK_BDVER2)
2316       .Case("bdver3", CK_BDVER3)
2317       .Case("bdver4", CK_BDVER4)
2318       .Case("x86-64", CK_x86_64)
2319       .Case("geode", CK_Geode)
2320       .Default(CK_Generic);
2321 
2322     // Perform any per-CPU checks necessary to determine if this CPU is
2323     // acceptable.
2324     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2325     // invalid without explaining *why*.
2326     switch (CPU) {
2327     case CK_Generic:
2328       // No processor selected!
2329       return false;
2330 
2331     case CK_i386:
2332     case CK_i486:
2333     case CK_WinChipC6:
2334     case CK_WinChip2:
2335     case CK_C3:
2336     case CK_i586:
2337     case CK_Pentium:
2338     case CK_PentiumMMX:
2339     case CK_i686:
2340     case CK_PentiumPro:
2341     case CK_Pentium2:
2342     case CK_Pentium3:
2343     case CK_Pentium3M:
2344     case CK_PentiumM:
2345     case CK_Yonah:
2346     case CK_C3_2:
2347     case CK_Pentium4:
2348     case CK_Pentium4M:
2349     case CK_Prescott:
2350     case CK_K6:
2351     case CK_K6_2:
2352     case CK_K6_3:
2353     case CK_Athlon:
2354     case CK_AthlonThunderbird:
2355     case CK_Athlon4:
2356     case CK_AthlonXP:
2357     case CK_AthlonMP:
2358     case CK_Geode:
2359       // Only accept certain architectures when compiling in 32-bit mode.
2360       if (getTriple().getArch() != llvm::Triple::x86)
2361         return false;
2362 
2363       // Fallthrough
2364     case CK_Nocona:
2365     case CK_Core2:
2366     case CK_Penryn:
2367     case CK_Bonnell:
2368     case CK_Silvermont:
2369     case CK_Nehalem:
2370     case CK_Westmere:
2371     case CK_SandyBridge:
2372     case CK_IvyBridge:
2373     case CK_Haswell:
2374     case CK_Broadwell:
2375     case CK_Skylake:
2376     case CK_KNL:
2377     case CK_Athlon64:
2378     case CK_Athlon64SSE3:
2379     case CK_AthlonFX:
2380     case CK_K8:
2381     case CK_K8SSE3:
2382     case CK_Opteron:
2383     case CK_OpteronSSE3:
2384     case CK_AMDFAM10:
2385     case CK_BTVER1:
2386     case CK_BTVER2:
2387     case CK_BDVER1:
2388     case CK_BDVER2:
2389     case CK_BDVER3:
2390     case CK_BDVER4:
2391     case CK_x86_64:
2392       return true;
2393     }
2394     llvm_unreachable("Unhandled CPU kind");
2395   }
2396 
2397   bool setFPMath(StringRef Name) override;
2398 
2399   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2400     // We accept all non-ARM calling conventions
2401     return (CC == CC_X86ThisCall ||
2402             CC == CC_X86FastCall ||
2403             CC == CC_X86StdCall ||
2404             CC == CC_X86VectorCall ||
2405             CC == CC_C ||
2406             CC == CC_X86Pascal ||
2407             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2408   }
2409 
2410   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2411     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2412   }
2413 
2414   bool hasSjLjLowering() const override {
2415     return true;
2416   }
2417 };
2418 
2419 bool X86TargetInfo::setFPMath(StringRef Name) {
2420   if (Name == "387") {
2421     FPMath = FP_387;
2422     return true;
2423   }
2424   if (Name == "sse") {
2425     FPMath = FP_SSE;
2426     return true;
2427   }
2428   return false;
2429 }
2430 
2431 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2432   // FIXME: This *really* should not be here.
2433 
2434   // X86_64 always has SSE2.
2435   if (getTriple().getArch() == llvm::Triple::x86_64)
2436     setFeatureEnabledImpl(Features, "sse2", true);
2437 
2438   switch (CPU) {
2439   case CK_Generic:
2440   case CK_i386:
2441   case CK_i486:
2442   case CK_i586:
2443   case CK_Pentium:
2444   case CK_i686:
2445   case CK_PentiumPro:
2446     break;
2447   case CK_PentiumMMX:
2448   case CK_Pentium2:
2449   case CK_K6:
2450   case CK_WinChipC6:
2451     setFeatureEnabledImpl(Features, "mmx", true);
2452     break;
2453   case CK_Pentium3:
2454   case CK_Pentium3M:
2455   case CK_C3_2:
2456     setFeatureEnabledImpl(Features, "sse", true);
2457     break;
2458   case CK_PentiumM:
2459   case CK_Pentium4:
2460   case CK_Pentium4M:
2461   case CK_x86_64:
2462     setFeatureEnabledImpl(Features, "sse2", true);
2463     break;
2464   case CK_Yonah:
2465   case CK_Prescott:
2466   case CK_Nocona:
2467     setFeatureEnabledImpl(Features, "sse3", true);
2468     setFeatureEnabledImpl(Features, "cx16", true);
2469     break;
2470   case CK_Core2:
2471   case CK_Bonnell:
2472     setFeatureEnabledImpl(Features, "ssse3", true);
2473     setFeatureEnabledImpl(Features, "cx16", true);
2474     break;
2475   case CK_Penryn:
2476     setFeatureEnabledImpl(Features, "sse4.1", true);
2477     setFeatureEnabledImpl(Features, "cx16", true);
2478     break;
2479   case CK_Skylake:
2480     setFeatureEnabledImpl(Features, "avx512f", true);
2481     setFeatureEnabledImpl(Features, "avx512cd", true);
2482     setFeatureEnabledImpl(Features, "avx512dq", true);
2483     setFeatureEnabledImpl(Features, "avx512bw", true);
2484     setFeatureEnabledImpl(Features, "avx512vl", true);
2485     // FALLTHROUGH
2486   case CK_Broadwell:
2487     setFeatureEnabledImpl(Features, "rdseed", true);
2488     setFeatureEnabledImpl(Features, "adx", true);
2489     // FALLTHROUGH
2490   case CK_Haswell:
2491     setFeatureEnabledImpl(Features, "avx2", true);
2492     setFeatureEnabledImpl(Features, "lzcnt", true);
2493     setFeatureEnabledImpl(Features, "bmi", true);
2494     setFeatureEnabledImpl(Features, "bmi2", true);
2495     setFeatureEnabledImpl(Features, "rtm", true);
2496     setFeatureEnabledImpl(Features, "fma", true);
2497     // FALLTHROUGH
2498   case CK_IvyBridge:
2499     setFeatureEnabledImpl(Features, "rdrnd", true);
2500     setFeatureEnabledImpl(Features, "f16c", true);
2501     setFeatureEnabledImpl(Features, "fsgsbase", true);
2502     // FALLTHROUGH
2503   case CK_SandyBridge:
2504     setFeatureEnabledImpl(Features, "avx", true);
2505     // FALLTHROUGH
2506   case CK_Westmere:
2507   case CK_Silvermont:
2508     setFeatureEnabledImpl(Features, "aes", true);
2509     setFeatureEnabledImpl(Features, "pclmul", true);
2510     // FALLTHROUGH
2511   case CK_Nehalem:
2512     setFeatureEnabledImpl(Features, "sse4.2", true);
2513     setFeatureEnabledImpl(Features, "cx16", true);
2514     break;
2515   case CK_KNL:
2516     setFeatureEnabledImpl(Features, "avx512f", true);
2517     setFeatureEnabledImpl(Features, "avx512cd", true);
2518     setFeatureEnabledImpl(Features, "avx512er", true);
2519     setFeatureEnabledImpl(Features, "avx512pf", true);
2520     setFeatureEnabledImpl(Features, "rdseed", true);
2521     setFeatureEnabledImpl(Features, "adx", true);
2522     setFeatureEnabledImpl(Features, "lzcnt", true);
2523     setFeatureEnabledImpl(Features, "bmi", true);
2524     setFeatureEnabledImpl(Features, "bmi2", true);
2525     setFeatureEnabledImpl(Features, "rtm", true);
2526     setFeatureEnabledImpl(Features, "fma", true);
2527     setFeatureEnabledImpl(Features, "rdrnd", true);
2528     setFeatureEnabledImpl(Features, "f16c", true);
2529     setFeatureEnabledImpl(Features, "fsgsbase", true);
2530     setFeatureEnabledImpl(Features, "aes", true);
2531     setFeatureEnabledImpl(Features, "pclmul", true);
2532     setFeatureEnabledImpl(Features, "cx16", true);
2533     break;
2534   case CK_K6_2:
2535   case CK_K6_3:
2536   case CK_WinChip2:
2537   case CK_C3:
2538     setFeatureEnabledImpl(Features, "3dnow", true);
2539     break;
2540   case CK_Athlon:
2541   case CK_AthlonThunderbird:
2542   case CK_Geode:
2543     setFeatureEnabledImpl(Features, "3dnowa", true);
2544     break;
2545   case CK_Athlon4:
2546   case CK_AthlonXP:
2547   case CK_AthlonMP:
2548     setFeatureEnabledImpl(Features, "sse", true);
2549     setFeatureEnabledImpl(Features, "3dnowa", true);
2550     break;
2551   case CK_K8:
2552   case CK_Opteron:
2553   case CK_Athlon64:
2554   case CK_AthlonFX:
2555     setFeatureEnabledImpl(Features, "sse2", true);
2556     setFeatureEnabledImpl(Features, "3dnowa", true);
2557     break;
2558   case CK_AMDFAM10:
2559     setFeatureEnabledImpl(Features, "sse4a", true);
2560     setFeatureEnabledImpl(Features, "lzcnt", true);
2561     setFeatureEnabledImpl(Features, "popcnt", true);
2562     // FALLTHROUGH
2563   case CK_K8SSE3:
2564   case CK_OpteronSSE3:
2565   case CK_Athlon64SSE3:
2566     setFeatureEnabledImpl(Features, "sse3", true);
2567     setFeatureEnabledImpl(Features, "3dnowa", true);
2568     break;
2569   case CK_BTVER2:
2570     setFeatureEnabledImpl(Features, "avx", true);
2571     setFeatureEnabledImpl(Features, "aes", true);
2572     setFeatureEnabledImpl(Features, "pclmul", true);
2573     setFeatureEnabledImpl(Features, "bmi", true);
2574     setFeatureEnabledImpl(Features, "f16c", true);
2575     // FALLTHROUGH
2576   case CK_BTVER1:
2577     setFeatureEnabledImpl(Features, "ssse3", true);
2578     setFeatureEnabledImpl(Features, "sse4a", true);
2579     setFeatureEnabledImpl(Features, "lzcnt", true);
2580     setFeatureEnabledImpl(Features, "popcnt", true);
2581     setFeatureEnabledImpl(Features, "prfchw", true);
2582     setFeatureEnabledImpl(Features, "cx16", true);
2583     break;
2584   case CK_BDVER4:
2585     setFeatureEnabledImpl(Features, "avx2", true);
2586     setFeatureEnabledImpl(Features, "bmi2", true);
2587     // FALLTHROUGH
2588   case CK_BDVER3:
2589     setFeatureEnabledImpl(Features, "fsgsbase", true);
2590     // FALLTHROUGH
2591   case CK_BDVER2:
2592     setFeatureEnabledImpl(Features, "bmi", true);
2593     setFeatureEnabledImpl(Features, "fma", true);
2594     setFeatureEnabledImpl(Features, "f16c", true);
2595     setFeatureEnabledImpl(Features, "tbm", true);
2596     // FALLTHROUGH
2597   case CK_BDVER1:
2598     // xop implies avx, sse4a and fma4.
2599     setFeatureEnabledImpl(Features, "xop", true);
2600     setFeatureEnabledImpl(Features, "lzcnt", true);
2601     setFeatureEnabledImpl(Features, "aes", true);
2602     setFeatureEnabledImpl(Features, "pclmul", true);
2603     setFeatureEnabledImpl(Features, "prfchw", true);
2604     setFeatureEnabledImpl(Features, "cx16", true);
2605     break;
2606   }
2607 }
2608 
2609 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2610                                 X86SSEEnum Level, bool Enabled) {
2611   if (Enabled) {
2612     switch (Level) {
2613     case AVX512F:
2614       Features["avx512f"] = true;
2615     case AVX2:
2616       Features["avx2"] = true;
2617     case AVX:
2618       Features["avx"] = true;
2619     case SSE42:
2620       Features["sse4.2"] = true;
2621     case SSE41:
2622       Features["sse4.1"] = true;
2623     case SSSE3:
2624       Features["ssse3"] = true;
2625     case SSE3:
2626       Features["sse3"] = true;
2627     case SSE2:
2628       Features["sse2"] = true;
2629     case SSE1:
2630       Features["sse"] = true;
2631     case NoSSE:
2632       break;
2633     }
2634     return;
2635   }
2636 
2637   switch (Level) {
2638   case NoSSE:
2639   case SSE1:
2640     Features["sse"] = false;
2641   case SSE2:
2642     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2643       Features["sha"] = false;
2644   case SSE3:
2645     Features["sse3"] = false;
2646     setXOPLevel(Features, NoXOP, false);
2647   case SSSE3:
2648     Features["ssse3"] = false;
2649   case SSE41:
2650     Features["sse4.1"] = false;
2651   case SSE42:
2652     Features["sse4.2"] = false;
2653   case AVX:
2654     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2655     setXOPLevel(Features, FMA4, false);
2656   case AVX2:
2657     Features["avx2"] = false;
2658   case AVX512F:
2659     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2660       Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] =
2661       Features["avx512vl"] = false;
2662   }
2663 }
2664 
2665 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2666                                 MMX3DNowEnum Level, bool Enabled) {
2667   if (Enabled) {
2668     switch (Level) {
2669     case AMD3DNowAthlon:
2670       Features["3dnowa"] = true;
2671     case AMD3DNow:
2672       Features["3dnow"] = true;
2673     case MMX:
2674       Features["mmx"] = true;
2675     case NoMMX3DNow:
2676       break;
2677     }
2678     return;
2679   }
2680 
2681   switch (Level) {
2682   case NoMMX3DNow:
2683   case MMX:
2684     Features["mmx"] = false;
2685   case AMD3DNow:
2686     Features["3dnow"] = false;
2687   case AMD3DNowAthlon:
2688     Features["3dnowa"] = false;
2689   }
2690 }
2691 
2692 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2693                                 bool Enabled) {
2694   if (Enabled) {
2695     switch (Level) {
2696     case XOP:
2697       Features["xop"] = true;
2698     case FMA4:
2699       Features["fma4"] = true;
2700       setSSELevel(Features, AVX, true);
2701     case SSE4A:
2702       Features["sse4a"] = true;
2703       setSSELevel(Features, SSE3, true);
2704     case NoXOP:
2705       break;
2706     }
2707     return;
2708   }
2709 
2710   switch (Level) {
2711   case NoXOP:
2712   case SSE4A:
2713     Features["sse4a"] = false;
2714   case FMA4:
2715     Features["fma4"] = false;
2716   case XOP:
2717     Features["xop"] = false;
2718   }
2719 }
2720 
2721 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2722                                           StringRef Name, bool Enabled) {
2723   Features[Name] = Enabled;
2724 
2725   if (Name == "mmx") {
2726     setMMXLevel(Features, MMX, Enabled);
2727   } else if (Name == "sse") {
2728     setSSELevel(Features, SSE1, Enabled);
2729   } else if (Name == "sse2") {
2730     setSSELevel(Features, SSE2, Enabled);
2731   } else if (Name == "sse3") {
2732     setSSELevel(Features, SSE3, Enabled);
2733   } else if (Name == "ssse3") {
2734     setSSELevel(Features, SSSE3, Enabled);
2735   } else if (Name == "sse4.2") {
2736     setSSELevel(Features, SSE42, Enabled);
2737   } else if (Name == "sse4.1") {
2738     setSSELevel(Features, SSE41, Enabled);
2739   } else if (Name == "3dnow") {
2740     setMMXLevel(Features, AMD3DNow, Enabled);
2741   } else if (Name == "3dnowa") {
2742     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2743   } else if (Name == "aes") {
2744     if (Enabled)
2745       setSSELevel(Features, SSE2, Enabled);
2746   } else if (Name == "pclmul") {
2747     if (Enabled)
2748       setSSELevel(Features, SSE2, Enabled);
2749   } else if (Name == "avx") {
2750     setSSELevel(Features, AVX, Enabled);
2751   } else if (Name == "avx2") {
2752     setSSELevel(Features, AVX2, Enabled);
2753   } else if (Name == "avx512f") {
2754     setSSELevel(Features, AVX512F, Enabled);
2755   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2756           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2757     if (Enabled)
2758       setSSELevel(Features, AVX512F, Enabled);
2759   } else if (Name == "fma") {
2760     if (Enabled)
2761       setSSELevel(Features, AVX, Enabled);
2762   } else if (Name == "fma4") {
2763     setXOPLevel(Features, FMA4, Enabled);
2764   } else if (Name == "xop") {
2765     setXOPLevel(Features, XOP, Enabled);
2766   } else if (Name == "sse4a") {
2767     setXOPLevel(Features, SSE4A, Enabled);
2768   } else if (Name == "f16c") {
2769     if (Enabled)
2770       setSSELevel(Features, AVX, Enabled);
2771   } else if (Name == "sha") {
2772     if (Enabled)
2773       setSSELevel(Features, SSE2, Enabled);
2774   }
2775 }
2776 
2777 /// handleTargetFeatures - Perform initialization based on the user
2778 /// configured set of features.
2779 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2780                                          DiagnosticsEngine &Diags) {
2781   // Remember the maximum enabled sselevel.
2782   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2783     // Ignore disabled features.
2784     if (Features[i][0] == '-')
2785       continue;
2786 
2787     StringRef Feature = StringRef(Features[i]).substr(1);
2788 
2789     if (Feature == "aes") {
2790       HasAES = true;
2791       continue;
2792     }
2793 
2794     if (Feature == "pclmul") {
2795       HasPCLMUL = true;
2796       continue;
2797     }
2798 
2799     if (Feature == "lzcnt") {
2800       HasLZCNT = true;
2801       continue;
2802     }
2803 
2804     if (Feature == "rdrnd") {
2805       HasRDRND = true;
2806       continue;
2807     }
2808 
2809     if (Feature == "fsgsbase") {
2810       HasFSGSBASE = true;
2811       continue;
2812     }
2813 
2814     if (Feature == "bmi") {
2815       HasBMI = true;
2816       continue;
2817     }
2818 
2819     if (Feature == "bmi2") {
2820       HasBMI2 = true;
2821       continue;
2822     }
2823 
2824     if (Feature == "popcnt") {
2825       HasPOPCNT = true;
2826       continue;
2827     }
2828 
2829     if (Feature == "rtm") {
2830       HasRTM = true;
2831       continue;
2832     }
2833 
2834     if (Feature == "prfchw") {
2835       HasPRFCHW = true;
2836       continue;
2837     }
2838 
2839     if (Feature == "rdseed") {
2840       HasRDSEED = true;
2841       continue;
2842     }
2843 
2844     if (Feature == "adx") {
2845       HasADX = true;
2846       continue;
2847     }
2848 
2849     if (Feature == "tbm") {
2850       HasTBM = true;
2851       continue;
2852     }
2853 
2854     if (Feature == "fma") {
2855       HasFMA = true;
2856       continue;
2857     }
2858 
2859     if (Feature == "f16c") {
2860       HasF16C = true;
2861       continue;
2862     }
2863 
2864     if (Feature == "avx512cd") {
2865       HasAVX512CD = true;
2866       continue;
2867     }
2868 
2869     if (Feature == "avx512er") {
2870       HasAVX512ER = true;
2871       continue;
2872     }
2873 
2874     if (Feature == "avx512pf") {
2875       HasAVX512PF = true;
2876       continue;
2877     }
2878 
2879     if (Feature == "avx512dq") {
2880       HasAVX512DQ = true;
2881       continue;
2882     }
2883 
2884     if (Feature == "avx512bw") {
2885       HasAVX512BW = true;
2886       continue;
2887     }
2888 
2889     if (Feature == "avx512vl") {
2890       HasAVX512VL = true;
2891       continue;
2892     }
2893 
2894     if (Feature == "sha") {
2895       HasSHA = true;
2896       continue;
2897     }
2898 
2899     if (Feature == "cx16") {
2900       HasCX16 = true;
2901       continue;
2902     }
2903 
2904     assert(Features[i][0] == '+' && "Invalid target feature!");
2905     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2906       .Case("avx512f", AVX512F)
2907       .Case("avx2", AVX2)
2908       .Case("avx", AVX)
2909       .Case("sse4.2", SSE42)
2910       .Case("sse4.1", SSE41)
2911       .Case("ssse3", SSSE3)
2912       .Case("sse3", SSE3)
2913       .Case("sse2", SSE2)
2914       .Case("sse", SSE1)
2915       .Default(NoSSE);
2916     SSELevel = std::max(SSELevel, Level);
2917 
2918     MMX3DNowEnum ThreeDNowLevel =
2919       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2920         .Case("3dnowa", AMD3DNowAthlon)
2921         .Case("3dnow", AMD3DNow)
2922         .Case("mmx", MMX)
2923         .Default(NoMMX3DNow);
2924     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2925 
2926     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2927         .Case("xop", XOP)
2928         .Case("fma4", FMA4)
2929         .Case("sse4a", SSE4A)
2930         .Default(NoXOP);
2931     XOPLevel = std::max(XOPLevel, XLevel);
2932   }
2933 
2934   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2935   // Can't do this earlier because we need to be able to explicitly enable
2936   // popcnt and still disable sse4.2.
2937   if (!HasPOPCNT && SSELevel >= SSE42 &&
2938       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2939     HasPOPCNT = true;
2940     Features.push_back("+popcnt");
2941   }
2942 
2943   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2944   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2945       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2946     HasPRFCHW = true;
2947     Features.push_back("+prfchw");
2948   }
2949 
2950   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2951   // matches the selected sse level.
2952   if (FPMath == FP_SSE && SSELevel < SSE1) {
2953     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2954     return false;
2955   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2956     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2957     return false;
2958   }
2959 
2960   // Don't tell the backend if we're turning off mmx; it will end up disabling
2961   // SSE, which we don't want.
2962   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2963   // then enable MMX.
2964   std::vector<std::string>::iterator it;
2965   it = std::find(Features.begin(), Features.end(), "-mmx");
2966   if (it != Features.end())
2967     Features.erase(it);
2968   else if (SSELevel > NoSSE)
2969     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2970   return true;
2971 }
2972 
2973 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2974 /// definitions for this particular subtarget.
2975 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2976                                      MacroBuilder &Builder) const {
2977   // Target identification.
2978   if (getTriple().getArch() == llvm::Triple::x86_64) {
2979     Builder.defineMacro("__amd64__");
2980     Builder.defineMacro("__amd64");
2981     Builder.defineMacro("__x86_64");
2982     Builder.defineMacro("__x86_64__");
2983     if (getTriple().getArchName() == "x86_64h") {
2984       Builder.defineMacro("__x86_64h");
2985       Builder.defineMacro("__x86_64h__");
2986     }
2987   } else {
2988     DefineStd(Builder, "i386", Opts);
2989   }
2990 
2991   // Subtarget options.
2992   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2993   // truly should be based on -mtune options.
2994   switch (CPU) {
2995   case CK_Generic:
2996     break;
2997   case CK_i386:
2998     // The rest are coming from the i386 define above.
2999     Builder.defineMacro("__tune_i386__");
3000     break;
3001   case CK_i486:
3002   case CK_WinChipC6:
3003   case CK_WinChip2:
3004   case CK_C3:
3005     defineCPUMacros(Builder, "i486");
3006     break;
3007   case CK_PentiumMMX:
3008     Builder.defineMacro("__pentium_mmx__");
3009     Builder.defineMacro("__tune_pentium_mmx__");
3010     // Fallthrough
3011   case CK_i586:
3012   case CK_Pentium:
3013     defineCPUMacros(Builder, "i586");
3014     defineCPUMacros(Builder, "pentium");
3015     break;
3016   case CK_Pentium3:
3017   case CK_Pentium3M:
3018   case CK_PentiumM:
3019     Builder.defineMacro("__tune_pentium3__");
3020     // Fallthrough
3021   case CK_Pentium2:
3022   case CK_C3_2:
3023     Builder.defineMacro("__tune_pentium2__");
3024     // Fallthrough
3025   case CK_PentiumPro:
3026     Builder.defineMacro("__tune_i686__");
3027     Builder.defineMacro("__tune_pentiumpro__");
3028     // Fallthrough
3029   case CK_i686:
3030     Builder.defineMacro("__i686");
3031     Builder.defineMacro("__i686__");
3032     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
3033     Builder.defineMacro("__pentiumpro");
3034     Builder.defineMacro("__pentiumpro__");
3035     break;
3036   case CK_Pentium4:
3037   case CK_Pentium4M:
3038     defineCPUMacros(Builder, "pentium4");
3039     break;
3040   case CK_Yonah:
3041   case CK_Prescott:
3042   case CK_Nocona:
3043     defineCPUMacros(Builder, "nocona");
3044     break;
3045   case CK_Core2:
3046   case CK_Penryn:
3047     defineCPUMacros(Builder, "core2");
3048     break;
3049   case CK_Bonnell:
3050     defineCPUMacros(Builder, "atom");
3051     break;
3052   case CK_Silvermont:
3053     defineCPUMacros(Builder, "slm");
3054     break;
3055   case CK_Nehalem:
3056   case CK_Westmere:
3057   case CK_SandyBridge:
3058   case CK_IvyBridge:
3059   case CK_Haswell:
3060   case CK_Broadwell:
3061     // FIXME: Historically, we defined this legacy name, it would be nice to
3062     // remove it at some point. We've never exposed fine-grained names for
3063     // recent primary x86 CPUs, and we should keep it that way.
3064     defineCPUMacros(Builder, "corei7");
3065     break;
3066   case CK_Skylake:
3067     // FIXME: Historically, we defined this legacy name, it would be nice to
3068     // remove it at some point. This is the only fine-grained CPU macro in the
3069     // main intel CPU line, and it would be better to not have these and force
3070     // people to use ISA macros.
3071     defineCPUMacros(Builder, "skx");
3072     break;
3073   case CK_KNL:
3074     defineCPUMacros(Builder, "knl");
3075     break;
3076   case CK_K6_2:
3077     Builder.defineMacro("__k6_2__");
3078     Builder.defineMacro("__tune_k6_2__");
3079     // Fallthrough
3080   case CK_K6_3:
3081     if (CPU != CK_K6_2) {  // In case of fallthrough
3082       // FIXME: GCC may be enabling these in cases where some other k6
3083       // architecture is specified but -m3dnow is explicitly provided. The
3084       // exact semantics need to be determined and emulated here.
3085       Builder.defineMacro("__k6_3__");
3086       Builder.defineMacro("__tune_k6_3__");
3087     }
3088     // Fallthrough
3089   case CK_K6:
3090     defineCPUMacros(Builder, "k6");
3091     break;
3092   case CK_Athlon:
3093   case CK_AthlonThunderbird:
3094   case CK_Athlon4:
3095   case CK_AthlonXP:
3096   case CK_AthlonMP:
3097     defineCPUMacros(Builder, "athlon");
3098     if (SSELevel != NoSSE) {
3099       Builder.defineMacro("__athlon_sse__");
3100       Builder.defineMacro("__tune_athlon_sse__");
3101     }
3102     break;
3103   case CK_K8:
3104   case CK_K8SSE3:
3105   case CK_x86_64:
3106   case CK_Opteron:
3107   case CK_OpteronSSE3:
3108   case CK_Athlon64:
3109   case CK_Athlon64SSE3:
3110   case CK_AthlonFX:
3111     defineCPUMacros(Builder, "k8");
3112     break;
3113   case CK_AMDFAM10:
3114     defineCPUMacros(Builder, "amdfam10");
3115     break;
3116   case CK_BTVER1:
3117     defineCPUMacros(Builder, "btver1");
3118     break;
3119   case CK_BTVER2:
3120     defineCPUMacros(Builder, "btver2");
3121     break;
3122   case CK_BDVER1:
3123     defineCPUMacros(Builder, "bdver1");
3124     break;
3125   case CK_BDVER2:
3126     defineCPUMacros(Builder, "bdver2");
3127     break;
3128   case CK_BDVER3:
3129     defineCPUMacros(Builder, "bdver3");
3130     break;
3131   case CK_BDVER4:
3132     defineCPUMacros(Builder, "bdver4");
3133     break;
3134   case CK_Geode:
3135     defineCPUMacros(Builder, "geode");
3136     break;
3137   }
3138 
3139   // Target properties.
3140   Builder.defineMacro("__REGISTER_PREFIX__", "");
3141 
3142   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
3143   // functions in glibc header files that use FP Stack inline asm which the
3144   // backend can't deal with (PR879).
3145   Builder.defineMacro("__NO_MATH_INLINES");
3146 
3147   if (HasAES)
3148     Builder.defineMacro("__AES__");
3149 
3150   if (HasPCLMUL)
3151     Builder.defineMacro("__PCLMUL__");
3152 
3153   if (HasLZCNT)
3154     Builder.defineMacro("__LZCNT__");
3155 
3156   if (HasRDRND)
3157     Builder.defineMacro("__RDRND__");
3158 
3159   if (HasFSGSBASE)
3160     Builder.defineMacro("__FSGSBASE__");
3161 
3162   if (HasBMI)
3163     Builder.defineMacro("__BMI__");
3164 
3165   if (HasBMI2)
3166     Builder.defineMacro("__BMI2__");
3167 
3168   if (HasPOPCNT)
3169     Builder.defineMacro("__POPCNT__");
3170 
3171   if (HasRTM)
3172     Builder.defineMacro("__RTM__");
3173 
3174   if (HasPRFCHW)
3175     Builder.defineMacro("__PRFCHW__");
3176 
3177   if (HasRDSEED)
3178     Builder.defineMacro("__RDSEED__");
3179 
3180   if (HasADX)
3181     Builder.defineMacro("__ADX__");
3182 
3183   if (HasTBM)
3184     Builder.defineMacro("__TBM__");
3185 
3186   switch (XOPLevel) {
3187   case XOP:
3188     Builder.defineMacro("__XOP__");
3189   case FMA4:
3190     Builder.defineMacro("__FMA4__");
3191   case SSE4A:
3192     Builder.defineMacro("__SSE4A__");
3193   case NoXOP:
3194     break;
3195   }
3196 
3197   if (HasFMA)
3198     Builder.defineMacro("__FMA__");
3199 
3200   if (HasF16C)
3201     Builder.defineMacro("__F16C__");
3202 
3203   if (HasAVX512CD)
3204     Builder.defineMacro("__AVX512CD__");
3205   if (HasAVX512ER)
3206     Builder.defineMacro("__AVX512ER__");
3207   if (HasAVX512PF)
3208     Builder.defineMacro("__AVX512PF__");
3209   if (HasAVX512DQ)
3210     Builder.defineMacro("__AVX512DQ__");
3211   if (HasAVX512BW)
3212     Builder.defineMacro("__AVX512BW__");
3213   if (HasAVX512VL)
3214     Builder.defineMacro("__AVX512VL__");
3215 
3216   if (HasSHA)
3217     Builder.defineMacro("__SHA__");
3218 
3219   if (HasCX16)
3220     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
3221 
3222   // Each case falls through to the previous one here.
3223   switch (SSELevel) {
3224   case AVX512F:
3225     Builder.defineMacro("__AVX512F__");
3226   case AVX2:
3227     Builder.defineMacro("__AVX2__");
3228   case AVX:
3229     Builder.defineMacro("__AVX__");
3230   case SSE42:
3231     Builder.defineMacro("__SSE4_2__");
3232   case SSE41:
3233     Builder.defineMacro("__SSE4_1__");
3234   case SSSE3:
3235     Builder.defineMacro("__SSSE3__");
3236   case SSE3:
3237     Builder.defineMacro("__SSE3__");
3238   case SSE2:
3239     Builder.defineMacro("__SSE2__");
3240     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
3241   case SSE1:
3242     Builder.defineMacro("__SSE__");
3243     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
3244   case NoSSE:
3245     break;
3246   }
3247 
3248   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
3249     switch (SSELevel) {
3250     case AVX512F:
3251     case AVX2:
3252     case AVX:
3253     case SSE42:
3254     case SSE41:
3255     case SSSE3:
3256     case SSE3:
3257     case SSE2:
3258       Builder.defineMacro("_M_IX86_FP", Twine(2));
3259       break;
3260     case SSE1:
3261       Builder.defineMacro("_M_IX86_FP", Twine(1));
3262       break;
3263     default:
3264       Builder.defineMacro("_M_IX86_FP", Twine(0));
3265     }
3266   }
3267 
3268   // Each case falls through to the previous one here.
3269   switch (MMX3DNowLevel) {
3270   case AMD3DNowAthlon:
3271     Builder.defineMacro("__3dNOW_A__");
3272   case AMD3DNow:
3273     Builder.defineMacro("__3dNOW__");
3274   case MMX:
3275     Builder.defineMacro("__MMX__");
3276   case NoMMX3DNow:
3277     break;
3278   }
3279 
3280   if (CPU >= CK_i486) {
3281     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3282     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3283     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3284   }
3285   if (CPU >= CK_i586)
3286     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3287 }
3288 
3289 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3290   return llvm::StringSwitch<bool>(Feature)
3291       .Case("aes", HasAES)
3292       .Case("avx", SSELevel >= AVX)
3293       .Case("avx2", SSELevel >= AVX2)
3294       .Case("avx512f", SSELevel >= AVX512F)
3295       .Case("avx512cd", HasAVX512CD)
3296       .Case("avx512er", HasAVX512ER)
3297       .Case("avx512pf", HasAVX512PF)
3298       .Case("avx512dq", HasAVX512DQ)
3299       .Case("avx512bw", HasAVX512BW)
3300       .Case("avx512vl", HasAVX512VL)
3301       .Case("bmi", HasBMI)
3302       .Case("bmi2", HasBMI2)
3303       .Case("cx16", HasCX16)
3304       .Case("f16c", HasF16C)
3305       .Case("fma", HasFMA)
3306       .Case("fma4", XOPLevel >= FMA4)
3307       .Case("fsgsbase", HasFSGSBASE)
3308       .Case("lzcnt", HasLZCNT)
3309       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3310       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3311       .Case("mmx", MMX3DNowLevel >= MMX)
3312       .Case("pclmul", HasPCLMUL)
3313       .Case("popcnt", HasPOPCNT)
3314       .Case("prfchw", HasPRFCHW)
3315       .Case("rdrnd", HasRDRND)
3316       .Case("rdseed", HasRDSEED)
3317       .Case("rtm", HasRTM)
3318       .Case("sha", HasSHA)
3319       .Case("sse", SSELevel >= SSE1)
3320       .Case("sse2", SSELevel >= SSE2)
3321       .Case("sse3", SSELevel >= SSE3)
3322       .Case("ssse3", SSELevel >= SSSE3)
3323       .Case("sse4.1", SSELevel >= SSE41)
3324       .Case("sse4.2", SSELevel >= SSE42)
3325       .Case("sse4a", XOPLevel >= SSE4A)
3326       .Case("tbm", HasTBM)
3327       .Case("x86", true)
3328       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3329       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3330       .Case("xop", XOPLevel >= XOP)
3331       .Default(false);
3332 }
3333 
3334 bool
3335 X86TargetInfo::validateAsmConstraint(const char *&Name,
3336                                      TargetInfo::ConstraintInfo &Info) const {
3337   switch (*Name) {
3338   default: return false;
3339   case 'I':
3340     Info.setRequiresImmediate(0, 31);
3341     return true;
3342   case 'J':
3343     Info.setRequiresImmediate(0, 63);
3344     return true;
3345   case 'K':
3346     Info.setRequiresImmediate(-128, 127);
3347     return true;
3348   case 'L':
3349     // FIXME: properly analyze this constraint:
3350     //  must be one of 0xff, 0xffff, or 0xffffffff
3351     return true;
3352   case 'M':
3353     Info.setRequiresImmediate(0, 3);
3354     return true;
3355   case 'N':
3356     Info.setRequiresImmediate(0, 255);
3357     return true;
3358   case 'O':
3359     Info.setRequiresImmediate(0, 127);
3360     return true;
3361   case 'Y': // first letter of a pair:
3362     switch (*(Name+1)) {
3363     default: return false;
3364     case '0':  // First SSE register.
3365     case 't':  // Any SSE register, when SSE2 is enabled.
3366     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3367     case 'm':  // any MMX register, when inter-unit moves enabled.
3368       break;   // falls through to setAllowsRegister.
3369   }
3370   case 'f': // any x87 floating point stack register.
3371     // Constraint 'f' cannot be used for output operands.
3372     if (Info.ConstraintStr[0] == '=')
3373       return false;
3374 
3375     Info.setAllowsRegister();
3376     return true;
3377   case 'a': // eax.
3378   case 'b': // ebx.
3379   case 'c': // ecx.
3380   case 'd': // edx.
3381   case 'S': // esi.
3382   case 'D': // edi.
3383   case 'A': // edx:eax.
3384   case 't': // top of floating point stack.
3385   case 'u': // second from top of floating point stack.
3386   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3387   case 'y': // Any MMX register.
3388   case 'x': // Any SSE register.
3389   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3390   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3391   case 'l': // "Index" registers: any general register that can be used as an
3392             // index in a base+index memory access.
3393     Info.setAllowsRegister();
3394     return true;
3395   case 'C': // SSE floating point constant.
3396   case 'G': // x87 floating point constant.
3397   case 'e': // 32-bit signed integer constant for use with zero-extending
3398             // x86_64 instructions.
3399   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3400             // x86_64 instructions.
3401     return true;
3402   }
3403 }
3404 
3405 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3406                                        unsigned Size) const {
3407   // Strip off constraint modifiers.
3408   while (Constraint[0] == '=' ||
3409          Constraint[0] == '+' ||
3410          Constraint[0] == '&')
3411     Constraint = Constraint.substr(1);
3412 
3413   return validateOperandSize(Constraint, Size);
3414 }
3415 
3416 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3417                                       unsigned Size) const {
3418   return validateOperandSize(Constraint, Size);
3419 }
3420 
3421 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3422                                         unsigned Size) const {
3423   switch (Constraint[0]) {
3424   default: break;
3425   case 'y':
3426     return Size <= 64;
3427   case 'f':
3428   case 't':
3429   case 'u':
3430     return Size <= 128;
3431   case 'x':
3432     // 256-bit ymm registers can be used if target supports AVX.
3433     return Size <= (SSELevel >= AVX ? 256U : 128U);
3434   }
3435 
3436   return true;
3437 }
3438 
3439 std::string
3440 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3441   switch (*Constraint) {
3442   case 'a': return std::string("{ax}");
3443   case 'b': return std::string("{bx}");
3444   case 'c': return std::string("{cx}");
3445   case 'd': return std::string("{dx}");
3446   case 'S': return std::string("{si}");
3447   case 'D': return std::string("{di}");
3448   case 'p': // address
3449     return std::string("im");
3450   case 't': // top of floating point stack.
3451     return std::string("{st}");
3452   case 'u': // second from top of floating point stack.
3453     return std::string("{st(1)}"); // second from top of floating point stack.
3454   default:
3455     return std::string(1, *Constraint);
3456   }
3457 }
3458 
3459 // X86-32 generic target
3460 class X86_32TargetInfo : public X86TargetInfo {
3461 public:
3462   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3463     DoubleAlign = LongLongAlign = 32;
3464     LongDoubleWidth = 96;
3465     LongDoubleAlign = 32;
3466     SuitableAlign = 128;
3467     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3468     SizeType = UnsignedInt;
3469     PtrDiffType = SignedInt;
3470     IntPtrType = SignedInt;
3471     RegParmMax = 3;
3472 
3473     // Use fpret for all types.
3474     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3475                              (1 << TargetInfo::Double) |
3476                              (1 << TargetInfo::LongDouble));
3477 
3478     // x86-32 has atomics up to 8 bytes
3479     // FIXME: Check that we actually have cmpxchg8b before setting
3480     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3481     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3482   }
3483   BuiltinVaListKind getBuiltinVaListKind() const override {
3484     return TargetInfo::CharPtrBuiltinVaList;
3485   }
3486 
3487   int getEHDataRegisterNumber(unsigned RegNo) const override {
3488     if (RegNo == 0) return 0;
3489     if (RegNo == 1) return 2;
3490     return -1;
3491   }
3492   bool validateOperandSize(StringRef Constraint,
3493                            unsigned Size) const override {
3494     switch (Constraint[0]) {
3495     default: break;
3496     case 'R':
3497     case 'q':
3498     case 'Q':
3499     case 'a':
3500     case 'b':
3501     case 'c':
3502     case 'd':
3503     case 'S':
3504     case 'D':
3505       return Size <= 32;
3506     case 'A':
3507       return Size <= 64;
3508     }
3509 
3510     return X86TargetInfo::validateOperandSize(Constraint, Size);
3511   }
3512 };
3513 
3514 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3515 public:
3516   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3517       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3518 
3519   unsigned getFloatEvalMethod() const override {
3520     unsigned Major, Minor, Micro;
3521     getTriple().getOSVersion(Major, Minor, Micro);
3522     // New NetBSD uses the default rounding mode.
3523     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3524       return X86_32TargetInfo::getFloatEvalMethod();
3525     // NetBSD before 6.99.26 defaults to "double" rounding.
3526     return 1;
3527   }
3528 };
3529 
3530 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3531 public:
3532   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3533       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3534     SizeType = UnsignedLong;
3535     IntPtrType = SignedLong;
3536     PtrDiffType = SignedLong;
3537   }
3538 };
3539 
3540 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3541 public:
3542   BitrigI386TargetInfo(const llvm::Triple &Triple)
3543       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3544     SizeType = UnsignedLong;
3545     IntPtrType = SignedLong;
3546     PtrDiffType = SignedLong;
3547   }
3548 };
3549 
3550 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3551 public:
3552   DarwinI386TargetInfo(const llvm::Triple &Triple)
3553       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3554     LongDoubleWidth = 128;
3555     LongDoubleAlign = 128;
3556     SuitableAlign = 128;
3557     MaxVectorAlign = 256;
3558     SizeType = UnsignedLong;
3559     IntPtrType = SignedLong;
3560     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3561     HasAlignMac68kSupport = true;
3562   }
3563 
3564 };
3565 
3566 // x86-32 Windows target
3567 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3568 public:
3569   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3570       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3571     WCharType = UnsignedShort;
3572     DoubleAlign = LongLongAlign = 64;
3573     bool IsWinCOFF =
3574         getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3575     DescriptionString = IsWinCOFF
3576                             ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
3577                             : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3578   }
3579   void getTargetDefines(const LangOptions &Opts,
3580                         MacroBuilder &Builder) const override {
3581     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3582   }
3583 };
3584 
3585 // x86-32 Windows Visual Studio target
3586 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3587 public:
3588   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3589       : WindowsX86_32TargetInfo(Triple) {
3590     LongDoubleWidth = LongDoubleAlign = 64;
3591     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3592   }
3593   void getTargetDefines(const LangOptions &Opts,
3594                         MacroBuilder &Builder) const override {
3595     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3596     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3597     // The value of the following reflects processor type.
3598     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3599     // We lost the original triple, so we use the default.
3600     Builder.defineMacro("_M_IX86", "600");
3601   }
3602 };
3603 } // end anonymous namespace
3604 
3605 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3606   // Mingw and cygwin define __declspec(a) to __attribute__((a)).  Clang supports
3607   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3608   // macro anyway for pre-processor compatibility.
3609   if (Opts.MicrosoftExt)
3610     Builder.defineMacro("__declspec", "__declspec");
3611   else
3612     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3613 
3614   if (!Opts.MicrosoftExt) {
3615     // Provide macros for all the calling convention keywords.  Provide both
3616     // single and double underscore prefixed variants.  These are available on
3617     // x64 as well as x86, even though they have no effect.
3618     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3619     for (const char *CC : CCs) {
3620       std::string GCCSpelling = "__attribute__((__";
3621       GCCSpelling += CC;
3622       GCCSpelling += "__))";
3623       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3624       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3625     }
3626   }
3627 }
3628 
3629 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3630   Builder.defineMacro("__MSVCRT__");
3631   Builder.defineMacro("__MINGW32__");
3632   addCygMingDefines(Opts, Builder);
3633 }
3634 
3635 namespace {
3636 // x86-32 MinGW target
3637 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3638 public:
3639   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3640       : WindowsX86_32TargetInfo(Triple) {}
3641   void getTargetDefines(const LangOptions &Opts,
3642                         MacroBuilder &Builder) const override {
3643     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3644     DefineStd(Builder, "WIN32", Opts);
3645     DefineStd(Builder, "WINNT", Opts);
3646     Builder.defineMacro("_X86_");
3647     addMinGWDefines(Opts, Builder);
3648   }
3649 };
3650 
3651 // x86-32 Cygwin target
3652 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3653 public:
3654   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3655       : X86_32TargetInfo(Triple) {
3656     TLSSupported = false;
3657     WCharType = UnsignedShort;
3658     DoubleAlign = LongLongAlign = 64;
3659     DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32";
3660   }
3661   void getTargetDefines(const LangOptions &Opts,
3662                         MacroBuilder &Builder) const override {
3663     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3664     Builder.defineMacro("_X86_");
3665     Builder.defineMacro("__CYGWIN__");
3666     Builder.defineMacro("__CYGWIN32__");
3667     addCygMingDefines(Opts, Builder);
3668     DefineStd(Builder, "unix", Opts);
3669     if (Opts.CPlusPlus)
3670       Builder.defineMacro("_GNU_SOURCE");
3671   }
3672 };
3673 
3674 // x86-32 Haiku target
3675 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3676 public:
3677   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3678     SizeType = UnsignedLong;
3679     IntPtrType = SignedLong;
3680     PtrDiffType = SignedLong;
3681     ProcessIDType = SignedLong;
3682     this->UserLabelPrefix = "";
3683     this->TLSSupported = false;
3684   }
3685   void getTargetDefines(const LangOptions &Opts,
3686                         MacroBuilder &Builder) const override {
3687     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3688     Builder.defineMacro("__INTEL__");
3689     Builder.defineMacro("__HAIKU__");
3690   }
3691 };
3692 
3693 // RTEMS Target
3694 template<typename Target>
3695 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3696 protected:
3697   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3698                     MacroBuilder &Builder) const override {
3699     // RTEMS defines; list based off of gcc output
3700 
3701     Builder.defineMacro("__rtems__");
3702     Builder.defineMacro("__ELF__");
3703   }
3704 
3705 public:
3706   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3707     this->UserLabelPrefix = "";
3708 
3709     switch (Triple.getArch()) {
3710     default:
3711     case llvm::Triple::x86:
3712       // this->MCountName = ".mcount";
3713       break;
3714     case llvm::Triple::mips:
3715     case llvm::Triple::mipsel:
3716     case llvm::Triple::ppc:
3717     case llvm::Triple::ppc64:
3718     case llvm::Triple::ppc64le:
3719       // this->MCountName = "_mcount";
3720       break;
3721     case llvm::Triple::arm:
3722       // this->MCountName = "__mcount";
3723       break;
3724     }
3725   }
3726 };
3727 
3728 // x86-32 RTEMS target
3729 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3730 public:
3731   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3732     SizeType = UnsignedLong;
3733     IntPtrType = SignedLong;
3734     PtrDiffType = SignedLong;
3735     this->UserLabelPrefix = "";
3736   }
3737   void getTargetDefines(const LangOptions &Opts,
3738                         MacroBuilder &Builder) const override {
3739     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3740     Builder.defineMacro("__INTEL__");
3741     Builder.defineMacro("__rtems__");
3742   }
3743 };
3744 
3745 // x86-64 generic target
3746 class X86_64TargetInfo : public X86TargetInfo {
3747 public:
3748   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3749     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3750     bool IsWinCOFF =
3751         getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF();
3752     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3753     LongDoubleWidth = 128;
3754     LongDoubleAlign = 128;
3755     LargeArrayMinWidth = 128;
3756     LargeArrayAlign = 128;
3757     SuitableAlign = 128;
3758     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3759     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3760     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3761     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3762     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3763     RegParmMax = 6;
3764 
3765     // Pointers are 32-bit in x32.
3766     DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128"
3767                               : IsWinCOFF
3768                                     ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128"
3769                                     : "e-m:e-i64:64-f80:128-n8:16:32:64-S128";
3770 
3771     // Use fpret only for long double.
3772     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3773 
3774     // Use fp2ret for _Complex long double.
3775     ComplexLongDoubleUsesFP2Ret = true;
3776 
3777     // x86-64 has atomics up to 16 bytes.
3778     MaxAtomicPromoteWidth = 128;
3779     MaxAtomicInlineWidth = 128;
3780   }
3781   BuiltinVaListKind getBuiltinVaListKind() const override {
3782     return TargetInfo::X86_64ABIBuiltinVaList;
3783   }
3784 
3785   int getEHDataRegisterNumber(unsigned RegNo) const override {
3786     if (RegNo == 0) return 0;
3787     if (RegNo == 1) return 1;
3788     return -1;
3789   }
3790 
3791   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3792     return (CC == CC_C ||
3793             CC == CC_X86VectorCall ||
3794             CC == CC_IntelOclBicc ||
3795             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3796   }
3797 
3798   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3799     return CC_C;
3800   }
3801 
3802   // for x32 we need it here explicitly
3803   bool hasInt128Type() const override { return true; }
3804 };
3805 
3806 // x86-64 Windows target
3807 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3808 public:
3809   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3810       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3811     WCharType = UnsignedShort;
3812     LongWidth = LongAlign = 32;
3813     DoubleAlign = LongLongAlign = 64;
3814     IntMaxType = SignedLongLong;
3815     Int64Type = SignedLongLong;
3816     SizeType = UnsignedLongLong;
3817     PtrDiffType = SignedLongLong;
3818     IntPtrType = SignedLongLong;
3819     this->UserLabelPrefix = "";
3820   }
3821 
3822   void getTargetDefines(const LangOptions &Opts,
3823                                 MacroBuilder &Builder) const override {
3824     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3825     Builder.defineMacro("_WIN64");
3826   }
3827 
3828   BuiltinVaListKind getBuiltinVaListKind() const override {
3829     return TargetInfo::CharPtrBuiltinVaList;
3830   }
3831 
3832   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3833     switch (CC) {
3834     case CC_X86StdCall:
3835     case CC_X86ThisCall:
3836     case CC_X86FastCall:
3837       return CCCR_Ignore;
3838     case CC_C:
3839     case CC_X86VectorCall:
3840     case CC_IntelOclBicc:
3841     case CC_X86_64SysV:
3842       return CCCR_OK;
3843     default:
3844       return CCCR_Warning;
3845     }
3846   }
3847 };
3848 
3849 // x86-64 Windows Visual Studio target
3850 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3851 public:
3852   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3853       : WindowsX86_64TargetInfo(Triple) {
3854     LongDoubleWidth = LongDoubleAlign = 64;
3855     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3856   }
3857   void getTargetDefines(const LangOptions &Opts,
3858                         MacroBuilder &Builder) const override {
3859     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3860     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3861     Builder.defineMacro("_M_X64");
3862     Builder.defineMacro("_M_AMD64");
3863   }
3864 };
3865 
3866 // x86-64 MinGW target
3867 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3868 public:
3869   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3870       : WindowsX86_64TargetInfo(Triple) {}
3871   void getTargetDefines(const LangOptions &Opts,
3872                         MacroBuilder &Builder) const override {
3873     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3874     DefineStd(Builder, "WIN64", Opts);
3875     Builder.defineMacro("__MINGW64__");
3876     addMinGWDefines(Opts, Builder);
3877 
3878     // GCC defines this macro when it is using __gxx_personality_seh0.
3879     if (!Opts.SjLjExceptions)
3880       Builder.defineMacro("__SEH__");
3881   }
3882 };
3883 
3884 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3885 public:
3886   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3887       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3888     Int64Type = SignedLongLong;
3889     MaxVectorAlign = 256;
3890     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3891     llvm::Triple T = llvm::Triple(Triple);
3892     if (T.isiOS())
3893       UseSignedCharForObjCBool = false;
3894     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3895   }
3896 };
3897 
3898 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3899 public:
3900   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3901       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3902     IntMaxType = SignedLongLong;
3903     Int64Type = SignedLongLong;
3904   }
3905 };
3906 
3907 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3908 public:
3909   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3910       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3911     IntMaxType = SignedLongLong;
3912     Int64Type = SignedLongLong;
3913   }
3914 };
3915 
3916 class ARMTargetInfo : public TargetInfo {
3917   // Possible FPU choices.
3918   enum FPUMode {
3919     VFP2FPU = (1 << 0),
3920     VFP3FPU = (1 << 1),
3921     VFP4FPU = (1 << 2),
3922     NeonFPU = (1 << 3),
3923     FPARMV8 = (1 << 4)
3924   };
3925 
3926   // Possible HWDiv features.
3927   enum HWDivMode {
3928     HWDivThumb = (1 << 0),
3929     HWDivARM = (1 << 1)
3930   };
3931 
3932   static bool FPUModeIsVFP(FPUMode Mode) {
3933     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3934   }
3935 
3936   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3937   static const char * const GCCRegNames[];
3938 
3939   std::string ABI, CPU;
3940 
3941   enum {
3942     FP_Default,
3943     FP_VFP,
3944     FP_Neon
3945   } FPMath;
3946 
3947   unsigned FPU : 5;
3948 
3949   unsigned IsAAPCS : 1;
3950   unsigned IsThumb : 1;
3951   unsigned HWDiv : 2;
3952 
3953   // Initialized via features.
3954   unsigned SoftFloat : 1;
3955   unsigned SoftFloatABI : 1;
3956 
3957   unsigned CRC : 1;
3958   unsigned Crypto : 1;
3959 
3960   // ACLE 6.5.1 Hardware floating point
3961   enum {
3962     HW_FP_HP = (1 << 1), /// half (16-bit)
3963     HW_FP_SP = (1 << 2), /// single (32-bit)
3964     HW_FP_DP = (1 << 3), /// double (64-bit)
3965   };
3966   uint32_t HW_FP;
3967 
3968   static const Builtin::Info BuiltinInfo[];
3969 
3970   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3971     StringRef ArchName = T.getArchName();
3972     if (T.getArch() == llvm::Triple::arm ||
3973         T.getArch() == llvm::Triple::armeb) {
3974       StringRef VersionStr;
3975       if (ArchName.startswith("armv"))
3976         VersionStr = ArchName.substr(4, 1);
3977       else if (ArchName.startswith("armebv"))
3978         VersionStr = ArchName.substr(6, 1);
3979       else
3980         return false;
3981       unsigned Version;
3982       if (VersionStr.getAsInteger(10, Version))
3983         return false;
3984       return Version >= 6;
3985     }
3986     assert(T.getArch() == llvm::Triple::thumb ||
3987            T.getArch() == llvm::Triple::thumbeb);
3988     StringRef VersionStr;
3989     if (ArchName.startswith("thumbv"))
3990       VersionStr = ArchName.substr(6, 1);
3991     else if (ArchName.startswith("thumbebv"))
3992       VersionStr = ArchName.substr(8, 1);
3993     else
3994       return false;
3995     unsigned Version;
3996     if (VersionStr.getAsInteger(10, Version))
3997       return false;
3998     return Version >= 7;
3999   }
4000 
4001   void setABIAAPCS() {
4002     IsAAPCS = true;
4003 
4004     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
4005     const llvm::Triple &T = getTriple();
4006 
4007     // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig.
4008     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD ||
4009         T.getOS() == llvm::Triple::Bitrig)
4010       SizeType = UnsignedLong;
4011     else
4012       SizeType = UnsignedInt;
4013 
4014     switch (T.getOS()) {
4015     case llvm::Triple::NetBSD:
4016       WCharType = SignedInt;
4017       break;
4018     case llvm::Triple::Win32:
4019       WCharType = UnsignedShort;
4020       break;
4021     case llvm::Triple::Linux:
4022     default:
4023       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
4024       WCharType = UnsignedInt;
4025       break;
4026     }
4027 
4028     UseBitFieldTypeAlignment = true;
4029 
4030     ZeroLengthBitfieldBoundary = 0;
4031 
4032     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
4033     // so set preferred for small types to 32.
4034     if (T.isOSBinFormatMachO()) {
4035       DescriptionString =
4036           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4037                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4038     } else if (T.isOSWindows()) {
4039       assert(!BigEndian && "Windows on ARM does not support big endian");
4040       DescriptionString = "e"
4041                           "-m:w"
4042                           "-p:32:32"
4043                           "-i64:64"
4044                           "-v128:64:128"
4045                           "-a:0:32"
4046                           "-n32"
4047                           "-S64";
4048     } else if (T.isOSNaCl()) {
4049       assert(!BigEndian && "NaCl on ARM does not support big endian");
4050       DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
4051     } else {
4052       DescriptionString =
4053           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
4054                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
4055     }
4056 
4057     // FIXME: Enumerated types are variable width in straight AAPCS.
4058   }
4059 
4060   void setABIAPCS() {
4061     const llvm::Triple &T = getTriple();
4062 
4063     IsAAPCS = false;
4064 
4065     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
4066 
4067     // size_t is unsigned int on FreeBSD.
4068     if (T.getOS() == llvm::Triple::FreeBSD)
4069       SizeType = UnsignedInt;
4070     else
4071       SizeType = UnsignedLong;
4072 
4073     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
4074     WCharType = SignedInt;
4075 
4076     // Do not respect the alignment of bit-field types when laying out
4077     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
4078     UseBitFieldTypeAlignment = false;
4079 
4080     /// gcc forces the alignment to 4 bytes, regardless of the type of the
4081     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
4082     /// gcc.
4083     ZeroLengthBitfieldBoundary = 32;
4084 
4085     if (T.isOSBinFormatMachO())
4086       DescriptionString =
4087           BigEndian
4088               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4089               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4090     else
4091       DescriptionString =
4092           BigEndian
4093               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
4094               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
4095 
4096     // FIXME: Override "preferred align" for double and long long.
4097   }
4098 
4099 public:
4100   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
4101       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
4102         IsAAPCS(true), HW_FP(0) {
4103     BigEndian = IsBigEndian;
4104 
4105     switch (getTriple().getOS()) {
4106     case llvm::Triple::NetBSD:
4107       PtrDiffType = SignedLong;
4108       break;
4109     default:
4110       PtrDiffType = SignedInt;
4111       break;
4112     }
4113 
4114     // {} in inline assembly are neon specifiers, not assembly variant
4115     // specifiers.
4116     NoAsmVariants = true;
4117 
4118     // FIXME: Should we just treat this as a feature?
4119     IsThumb = getTriple().getArchName().startswith("thumb");
4120 
4121     // FIXME: This duplicates code from the driver that sets the -target-abi
4122     // option - this code is used if -target-abi isn't passed and should
4123     // be unified in some way.
4124     if (Triple.isOSBinFormatMachO()) {
4125       // The backend is hardwired to assume AAPCS for M-class processors, ensure
4126       // the frontend matches that.
4127       if (Triple.getEnvironment() == llvm::Triple::EABI ||
4128           Triple.getOS() == llvm::Triple::UnknownOS ||
4129           StringRef(CPU).startswith("cortex-m")) {
4130         setABI("aapcs");
4131       } else {
4132         setABI("apcs-gnu");
4133       }
4134     } else if (Triple.isOSWindows()) {
4135       // FIXME: this is invalid for WindowsCE
4136       setABI("aapcs");
4137     } else {
4138       // Select the default based on the platform.
4139       switch (Triple.getEnvironment()) {
4140       case llvm::Triple::Android:
4141       case llvm::Triple::GNUEABI:
4142       case llvm::Triple::GNUEABIHF:
4143         setABI("aapcs-linux");
4144         break;
4145       case llvm::Triple::EABIHF:
4146       case llvm::Triple::EABI:
4147         setABI("aapcs");
4148         break;
4149       case llvm::Triple::GNU:
4150 	setABI("apcs-gnu");
4151 	break;
4152       default:
4153         if (Triple.getOS() == llvm::Triple::NetBSD)
4154           setABI("apcs-gnu");
4155         else
4156           setABI("aapcs");
4157         break;
4158       }
4159     }
4160 
4161     // ARM targets default to using the ARM C++ ABI.
4162     TheCXXABI.set(TargetCXXABI::GenericARM);
4163 
4164     // ARM has atomics up to 8 bytes
4165     MaxAtomicPromoteWidth = 64;
4166     if (shouldUseInlineAtomic(getTriple()))
4167       MaxAtomicInlineWidth = 64;
4168 
4169     // Do force alignment of members that follow zero length bitfields.  If
4170     // the alignment of the zero-length bitfield is greater than the member
4171     // that follows it, `bar', `bar' will be aligned as the  type of the
4172     // zero length bitfield.
4173     UseZeroLengthBitfieldAlignment = true;
4174   }
4175   StringRef getABI() const override { return ABI; }
4176   bool setABI(const std::string &Name) override {
4177     ABI = Name;
4178 
4179     // The defaults (above) are for AAPCS, check if we need to change them.
4180     //
4181     // FIXME: We need support for -meabi... we could just mangle it into the
4182     // name.
4183     if (Name == "apcs-gnu") {
4184       setABIAPCS();
4185       return true;
4186     }
4187     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
4188       setABIAAPCS();
4189       return true;
4190     }
4191     return false;
4192   }
4193 
4194   // FIXME: This should be based on Arch attributes, not CPU names.
4195   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
4196     StringRef ArchName = getTriple().getArchName();
4197     unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName);
4198     bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A ||
4199                  ArchKind == llvm::ARM::AK_ARMV8_1A);
4200 
4201     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
4202       Features["vfp2"] = true;
4203     else if (CPU == "cortex-a8" || CPU == "cortex-a9") {
4204       Features["vfp3"] = true;
4205       Features["neon"] = true;
4206     }
4207     else if (CPU == "cortex-a5") {
4208       Features["vfp4"] = true;
4209       Features["neon"] = true;
4210     } else if (CPU == "swift" || CPU == "cortex-a7" ||
4211                CPU == "cortex-a12" || CPU == "cortex-a15" ||
4212                CPU == "cortex-a17" || CPU == "krait") {
4213       Features["vfp4"] = true;
4214       Features["neon"] = true;
4215       Features["hwdiv"] = true;
4216       Features["hwdiv-arm"] = true;
4217     } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" ||
4218                CPU == "cortex-a72") {
4219       Features["fp-armv8"] = true;
4220       Features["neon"] = true;
4221       Features["hwdiv"] = true;
4222       Features["hwdiv-arm"] = true;
4223       Features["crc"] = true;
4224       Features["crypto"] = true;
4225     } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) {
4226       Features["hwdiv"] = true;
4227       Features["hwdiv-arm"] = true;
4228     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" ||
4229                CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") {
4230       Features["hwdiv"] = true;
4231     }
4232   }
4233 
4234   bool handleTargetFeatures(std::vector<std::string> &Features,
4235                             DiagnosticsEngine &Diags) override {
4236     FPU = 0;
4237     CRC = 0;
4238     Crypto = 0;
4239     SoftFloat = SoftFloatABI = false;
4240     HWDiv = 0;
4241 
4242     for (const auto &Feature : Features) {
4243       if (Feature == "+soft-float") {
4244         SoftFloat = true;
4245       } else if (Feature == "+soft-float-abi") {
4246         SoftFloatABI = true;
4247       } else if (Feature == "+vfp2") {
4248         FPU |= VFP2FPU;
4249         HW_FP = HW_FP_SP | HW_FP_DP;
4250       } else if (Feature == "+vfp3") {
4251         FPU |= VFP3FPU;
4252         HW_FP = HW_FP_SP | HW_FP_DP;
4253       } else if (Feature == "+vfp4") {
4254         FPU |= VFP4FPU;
4255         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4256       } else if (Feature == "+fp-armv8") {
4257         FPU |= FPARMV8;
4258         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
4259       } else if (Feature == "+neon") {
4260         FPU |= NeonFPU;
4261         HW_FP = HW_FP_SP | HW_FP_DP;
4262       } else if (Feature == "+hwdiv") {
4263         HWDiv |= HWDivThumb;
4264       } else if (Feature == "+hwdiv-arm") {
4265         HWDiv |= HWDivARM;
4266       } else if (Feature == "+crc") {
4267         CRC = 1;
4268       } else if (Feature == "+crypto") {
4269         Crypto = 1;
4270       } else if (Feature == "+fp-only-sp") {
4271         HW_FP &= ~HW_FP_DP;
4272       }
4273     }
4274 
4275     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
4276       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
4277       return false;
4278     }
4279 
4280     if (FPMath == FP_Neon)
4281       Features.push_back("+neonfp");
4282     else if (FPMath == FP_VFP)
4283       Features.push_back("-neonfp");
4284 
4285     // Remove front-end specific options which the backend handles differently.
4286     auto Feature =
4287         std::find(Features.begin(), Features.end(), "+soft-float-abi");
4288     if (Feature != Features.end())
4289       Features.erase(Feature);
4290 
4291     return true;
4292   }
4293 
4294   bool hasFeature(StringRef Feature) const override {
4295     return llvm::StringSwitch<bool>(Feature)
4296         .Case("arm", true)
4297         .Case("softfloat", SoftFloat)
4298         .Case("thumb", IsThumb)
4299         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4300         .Case("hwdiv", HWDiv & HWDivThumb)
4301         .Case("hwdiv-arm", HWDiv & HWDivARM)
4302         .Default(false);
4303   }
4304   const char *getCPUDefineSuffix(StringRef Name) const {
4305     if(Name == "generic") {
4306       auto subarch = getTriple().getSubArch();
4307       switch (subarch) {
4308         case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4309           return "8_1A";
4310         default:
4311           break;
4312       }
4313     }
4314 
4315     unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name);
4316     if (ArchKind == llvm::ARM::AK_INVALID)
4317       return "";
4318 
4319     // For most sub-arches, the build attribute CPU name is enough.
4320     // For Cortex variants, it's slightly different.
4321     switch(ArchKind) {
4322     default:
4323       return llvm::ARMTargetParser::getCPUAttr(ArchKind);
4324     case llvm::ARM::AK_ARMV6M:
4325     case llvm::ARM::AK_ARMV6SM:
4326       return "6M";
4327     case llvm::ARM::AK_ARMV7:
4328     case llvm::ARM::AK_ARMV7A:
4329     case llvm::ARM::AK_ARMV7S:
4330       return "7A";
4331     case llvm::ARM::AK_ARMV7R:
4332       return "7R";
4333     case llvm::ARM::AK_ARMV7M:
4334       return "7M";
4335     case llvm::ARM::AK_ARMV7EM:
4336       return "7EM";
4337     case llvm::ARM::AK_ARMV8A:
4338       return "8A";
4339     case llvm::ARM::AK_ARMV8_1A:
4340       return "8_1A";
4341     }
4342   }
4343   const char *getCPUProfile(StringRef Name) const {
4344     if(Name == "generic") {
4345       auto subarch = getTriple().getSubArch();
4346       switch (subarch) {
4347         case llvm::Triple::SubArchType::ARMSubArch_v8_1a:
4348           return "A";
4349         default:
4350           break;
4351       }
4352     }
4353 
4354     unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name);
4355     if (CPUArch == llvm::ARM::AK_INVALID)
4356       return "";
4357 
4358     StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch);
4359     switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) {
4360       case llvm::ARM::PK_A:
4361         return "A";
4362       case llvm::ARM::PK_R:
4363         return "R";
4364       case llvm::ARM::PK_M:
4365         return "M";
4366       default:
4367         return "";
4368     }
4369   }
4370   bool setCPU(const std::string &Name) override {
4371     if (!getCPUDefineSuffix(Name))
4372       return false;
4373 
4374     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4375     StringRef Profile = getCPUProfile(Name);
4376     if (Profile == "M" && MaxAtomicInlineWidth) {
4377       MaxAtomicPromoteWidth = 32;
4378       MaxAtomicInlineWidth = 32;
4379     }
4380 
4381     CPU = Name;
4382     return true;
4383   }
4384   bool setFPMath(StringRef Name) override;
4385   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4386                      unsigned CPUArchVer) const {
4387     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4388            (CPUArch.find('M') != StringRef::npos);
4389   }
4390   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4391                       unsigned CPUArchVer) const {
4392     // We check both CPUArchVer and ArchName because when only triple is
4393     // specified, the default CPU is arm1136j-s.
4394     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4395            ArchName.endswith("v8.1a") ||
4396            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4397   }
4398   void getTargetDefines(const LangOptions &Opts,
4399                         MacroBuilder &Builder) const override {
4400     // Target identification.
4401     Builder.defineMacro("__arm");
4402     Builder.defineMacro("__arm__");
4403 
4404     // Target properties.
4405     Builder.defineMacro("__REGISTER_PREFIX__", "");
4406 
4407     StringRef CPUArch = getCPUDefineSuffix(CPU);
4408     unsigned int CPUArchVer;
4409     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4410       llvm_unreachable("Invalid char for architecture version number");
4411     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4412 
4413     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4414     StringRef CPUProfile = getCPUProfile(CPU);
4415     StringRef ArchName = getTriple().getArchName();
4416 
4417     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4418     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4419     if (CPUArch[0] >= '8') {
4420       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4421       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4422     }
4423 
4424     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4425     // is not defined for the M-profile.
4426     // NOTE that the deffault profile is assumed to be 'A'
4427     if (CPUProfile.empty() || CPUProfile != "M")
4428       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4429 
4430     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4431     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4432     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4433     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4434       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4435     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4436       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4437 
4438     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4439     // instruction set such as ARM or Thumb.
4440     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4441 
4442     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4443 
4444     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4445     if (!CPUProfile.empty())
4446       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4447 
4448     // ACLE 6.5.1 Hardware Floating Point
4449     if (HW_FP)
4450       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4451 
4452     // ACLE predefines.
4453     Builder.defineMacro("__ARM_ACLE", "200");
4454 
4455     // Subtarget options.
4456 
4457     // FIXME: It's more complicated than this and we don't really support
4458     // interworking.
4459     // Windows on ARM does not "support" interworking
4460     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4461       Builder.defineMacro("__THUMB_INTERWORK__");
4462 
4463     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4464       // Embedded targets on Darwin follow AAPCS, but not EABI.
4465       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4466       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4467         Builder.defineMacro("__ARM_EABI__");
4468       Builder.defineMacro("__ARM_PCS", "1");
4469 
4470       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4471         Builder.defineMacro("__ARM_PCS_VFP", "1");
4472     }
4473 
4474     if (SoftFloat)
4475       Builder.defineMacro("__SOFTFP__");
4476 
4477     if (CPU == "xscale")
4478       Builder.defineMacro("__XSCALE__");
4479 
4480     if (IsThumb) {
4481       Builder.defineMacro("__THUMBEL__");
4482       Builder.defineMacro("__thumb__");
4483       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4484         Builder.defineMacro("__thumb2__");
4485     }
4486     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4487       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4488 
4489     // Note, this is always on in gcc, even though it doesn't make sense.
4490     Builder.defineMacro("__APCS_32__");
4491 
4492     if (FPUModeIsVFP((FPUMode) FPU)) {
4493       Builder.defineMacro("__VFP_FP__");
4494       if (FPU & VFP2FPU)
4495         Builder.defineMacro("__ARM_VFPV2__");
4496       if (FPU & VFP3FPU)
4497         Builder.defineMacro("__ARM_VFPV3__");
4498       if (FPU & VFP4FPU)
4499         Builder.defineMacro("__ARM_VFPV4__");
4500     }
4501 
4502     // This only gets set when Neon instructions are actually available, unlike
4503     // the VFP define, hence the soft float and arch check. This is subtly
4504     // different from gcc, we follow the intent which was that it should be set
4505     // when Neon instructions are actually available.
4506     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4507       Builder.defineMacro("__ARM_NEON");
4508       Builder.defineMacro("__ARM_NEON__");
4509     }
4510 
4511     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4512                         Opts.ShortWChar ? "2" : "4");
4513 
4514     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4515                         Opts.ShortEnums ? "1" : "4");
4516 
4517     if (CRC)
4518       Builder.defineMacro("__ARM_FEATURE_CRC32");
4519 
4520     if (Crypto)
4521       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4522 
4523     if (CPUArchVer >= 6 && CPUArch != "6M") {
4524       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4525       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4526       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4527       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4528     }
4529 
4530     bool is5EOrAbove = (CPUArchVer >= 6 ||
4531                         (CPUArchVer == 5 &&
4532                          CPUArch.find('E') != StringRef::npos));
4533     bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer));
4534     if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch  == "7EM"))
4535       Builder.defineMacro("__ARM_FEATURE_DSP");
4536   }
4537   void getTargetBuiltins(const Builtin::Info *&Records,
4538                          unsigned &NumRecords) const override {
4539     Records = BuiltinInfo;
4540     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4541   }
4542   bool isCLZForZeroUndef() const override { return false; }
4543   BuiltinVaListKind getBuiltinVaListKind() const override {
4544     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4545   }
4546   void getGCCRegNames(const char * const *&Names,
4547                       unsigned &NumNames) const override;
4548   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4549                         unsigned &NumAliases) const override;
4550   bool validateAsmConstraint(const char *&Name,
4551                              TargetInfo::ConstraintInfo &Info) const override {
4552     switch (*Name) {
4553     default: break;
4554     case 'l': // r0-r7
4555     case 'h': // r8-r15
4556     case 'w': // VFP Floating point register single precision
4557     case 'P': // VFP Floating point register double precision
4558       Info.setAllowsRegister();
4559       return true;
4560     case 'I':
4561     case 'J':
4562     case 'K':
4563     case 'L':
4564     case 'M':
4565       // FIXME
4566       return true;
4567     case 'Q': // A memory address that is a single base register.
4568       Info.setAllowsMemory();
4569       return true;
4570     case 'U': // a memory reference...
4571       switch (Name[1]) {
4572       case 'q': // ...ARMV4 ldrsb
4573       case 'v': // ...VFP load/store (reg+constant offset)
4574       case 'y': // ...iWMMXt load/store
4575       case 't': // address valid for load/store opaque types wider
4576                 // than 128-bits
4577       case 'n': // valid address for Neon doubleword vector load/store
4578       case 'm': // valid address for Neon element and structure load/store
4579       case 's': // valid address for non-offset loads/stores of quad-word
4580                 // values in four ARM registers
4581         Info.setAllowsMemory();
4582         Name++;
4583         return true;
4584       }
4585     }
4586     return false;
4587   }
4588   std::string convertConstraint(const char *&Constraint) const override {
4589     std::string R;
4590     switch (*Constraint) {
4591     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4592       R = std::string("^") + std::string(Constraint, 2);
4593       Constraint++;
4594       break;
4595     case 'p': // 'p' should be translated to 'r' by default.
4596       R = std::string("r");
4597       break;
4598     default:
4599       return std::string(1, *Constraint);
4600     }
4601     return R;
4602   }
4603   bool
4604   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4605                              std::string &SuggestedModifier) const override {
4606     bool isOutput = (Constraint[0] == '=');
4607     bool isInOut = (Constraint[0] == '+');
4608 
4609     // Strip off constraint modifiers.
4610     while (Constraint[0] == '=' ||
4611            Constraint[0] == '+' ||
4612            Constraint[0] == '&')
4613       Constraint = Constraint.substr(1);
4614 
4615     switch (Constraint[0]) {
4616     default: break;
4617     case 'r': {
4618       switch (Modifier) {
4619       default:
4620         return (isInOut || isOutput || Size <= 64);
4621       case 'q':
4622         // A register of size 32 cannot fit a vector type.
4623         return false;
4624       }
4625     }
4626     }
4627 
4628     return true;
4629   }
4630   const char *getClobbers() const override {
4631     // FIXME: Is this really right?
4632     return "";
4633   }
4634 
4635   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4636     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4637   }
4638 
4639   int getEHDataRegisterNumber(unsigned RegNo) const override {
4640     if (RegNo == 0) return 0;
4641     if (RegNo == 1) return 1;
4642     return -1;
4643   }
4644 };
4645 
4646 bool ARMTargetInfo::setFPMath(StringRef Name) {
4647   if (Name == "neon") {
4648     FPMath = FP_Neon;
4649     return true;
4650   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4651              Name == "vfp4") {
4652     FPMath = FP_VFP;
4653     return true;
4654   }
4655   return false;
4656 }
4657 
4658 const char * const ARMTargetInfo::GCCRegNames[] = {
4659   // Integer registers
4660   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4661   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4662 
4663   // Float registers
4664   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4665   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4666   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4667   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4668 
4669   // Double registers
4670   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4671   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4672   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4673   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4674 
4675   // Quad registers
4676   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4677   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4678 };
4679 
4680 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4681                                    unsigned &NumNames) const {
4682   Names = GCCRegNames;
4683   NumNames = llvm::array_lengthof(GCCRegNames);
4684 }
4685 
4686 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4687   { { "a1" }, "r0" },
4688   { { "a2" }, "r1" },
4689   { { "a3" }, "r2" },
4690   { { "a4" }, "r3" },
4691   { { "v1" }, "r4" },
4692   { { "v2" }, "r5" },
4693   { { "v3" }, "r6" },
4694   { { "v4" }, "r7" },
4695   { { "v5" }, "r8" },
4696   { { "v6", "rfp" }, "r9" },
4697   { { "sl" }, "r10" },
4698   { { "fp" }, "r11" },
4699   { { "ip" }, "r12" },
4700   { { "r13" }, "sp" },
4701   { { "r14" }, "lr" },
4702   { { "r15" }, "pc" },
4703   // The S, D and Q registers overlap, but aren't really aliases; we
4704   // don't want to substitute one of these for a different-sized one.
4705 };
4706 
4707 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4708                                        unsigned &NumAliases) const {
4709   Aliases = GCCRegAliases;
4710   NumAliases = llvm::array_lengthof(GCCRegAliases);
4711 }
4712 
4713 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4714 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4715 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4716                                               ALL_LANGUAGES },
4717 #include "clang/Basic/BuiltinsNEON.def"
4718 
4719 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4720 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4721 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4722                                               ALL_LANGUAGES },
4723 #include "clang/Basic/BuiltinsARM.def"
4724 };
4725 
4726 class ARMleTargetInfo : public ARMTargetInfo {
4727 public:
4728   ARMleTargetInfo(const llvm::Triple &Triple)
4729     : ARMTargetInfo(Triple, false) { }
4730   void getTargetDefines(const LangOptions &Opts,
4731                         MacroBuilder &Builder) const override {
4732     Builder.defineMacro("__ARMEL__");
4733     ARMTargetInfo::getTargetDefines(Opts, Builder);
4734   }
4735 };
4736 
4737 class ARMbeTargetInfo : public ARMTargetInfo {
4738 public:
4739   ARMbeTargetInfo(const llvm::Triple &Triple)
4740     : ARMTargetInfo(Triple, true) { }
4741   void getTargetDefines(const LangOptions &Opts,
4742                         MacroBuilder &Builder) const override {
4743     Builder.defineMacro("__ARMEB__");
4744     Builder.defineMacro("__ARM_BIG_ENDIAN");
4745     ARMTargetInfo::getTargetDefines(Opts, Builder);
4746   }
4747 };
4748 
4749 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4750   const llvm::Triple Triple;
4751 public:
4752   WindowsARMTargetInfo(const llvm::Triple &Triple)
4753     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4754     TLSSupported = false;
4755     WCharType = UnsignedShort;
4756     SizeType = UnsignedInt;
4757     UserLabelPrefix = "";
4758   }
4759   void getVisualStudioDefines(const LangOptions &Opts,
4760                               MacroBuilder &Builder) const {
4761     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4762 
4763     // FIXME: this is invalid for WindowsCE
4764     Builder.defineMacro("_M_ARM_NT", "1");
4765     Builder.defineMacro("_M_ARMT", "_M_ARM");
4766     Builder.defineMacro("_M_THUMB", "_M_ARM");
4767 
4768     assert((Triple.getArch() == llvm::Triple::arm ||
4769             Triple.getArch() == llvm::Triple::thumb) &&
4770            "invalid architecture for Windows ARM target info");
4771     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4772     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4773 
4774     // TODO map the complete set of values
4775     // 31: VFPv3 40: VFPv4
4776     Builder.defineMacro("_M_ARM_FP", "31");
4777   }
4778   BuiltinVaListKind getBuiltinVaListKind() const override {
4779     return TargetInfo::CharPtrBuiltinVaList;
4780   }
4781 };
4782 
4783 // Windows ARM + Itanium C++ ABI Target
4784 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4785 public:
4786   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4787     : WindowsARMTargetInfo(Triple) {
4788     TheCXXABI.set(TargetCXXABI::GenericARM);
4789   }
4790 
4791   void getTargetDefines(const LangOptions &Opts,
4792                         MacroBuilder &Builder) const override {
4793     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4794 
4795     if (Opts.MSVCCompat)
4796       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4797   }
4798 };
4799 
4800 // Windows ARM, MS (C++) ABI
4801 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4802 public:
4803   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4804     : WindowsARMTargetInfo(Triple) {
4805     TheCXXABI.set(TargetCXXABI::Microsoft);
4806   }
4807 
4808   void getTargetDefines(const LangOptions &Opts,
4809                         MacroBuilder &Builder) const override {
4810     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4811     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4812   }
4813 };
4814 
4815 class DarwinARMTargetInfo :
4816   public DarwinTargetInfo<ARMleTargetInfo> {
4817 protected:
4818   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4819                     MacroBuilder &Builder) const override {
4820     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4821   }
4822 
4823 public:
4824   DarwinARMTargetInfo(const llvm::Triple &Triple)
4825       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4826     HasAlignMac68kSupport = true;
4827     // iOS always has 64-bit atomic instructions.
4828     // FIXME: This should be based off of the target features in
4829     // ARMleTargetInfo.
4830     MaxAtomicInlineWidth = 64;
4831 
4832     // Darwin on iOS uses a variant of the ARM C++ ABI.
4833     TheCXXABI.set(TargetCXXABI::iOS);
4834   }
4835 };
4836 
4837 class AArch64TargetInfo : public TargetInfo {
4838   virtual void setDescriptionString() = 0;
4839   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4840   static const char *const GCCRegNames[];
4841 
4842   enum FPUModeEnum {
4843     FPUMode,
4844     NeonMode
4845   };
4846 
4847   unsigned FPU;
4848   unsigned CRC;
4849   unsigned Crypto;
4850 
4851   static const Builtin::Info BuiltinInfo[];
4852 
4853   std::string ABI;
4854 
4855 public:
4856   AArch64TargetInfo(const llvm::Triple &Triple)
4857       : TargetInfo(Triple), ABI("aapcs") {
4858 
4859     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4860       WCharType = SignedInt;
4861 
4862       // NetBSD apparently prefers consistency across ARM targets to consistency
4863       // across 64-bit targets.
4864       Int64Type = SignedLongLong;
4865       IntMaxType = SignedLongLong;
4866     } else {
4867       WCharType = UnsignedInt;
4868       Int64Type = SignedLong;
4869       IntMaxType = SignedLong;
4870     }
4871 
4872     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4873     MaxVectorAlign = 128;
4874     RegParmMax = 8;
4875     MaxAtomicInlineWidth = 128;
4876     MaxAtomicPromoteWidth = 128;
4877 
4878     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128;
4879     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4880 
4881     // {} in inline assembly are neon specifiers, not assembly variant
4882     // specifiers.
4883     NoAsmVariants = true;
4884 
4885     // AAPCS gives rules for bitfields. 7.1.7 says: "The container type
4886     // contributes to the alignment of the containing aggregate in the same way
4887     // a plain (non bit-field) member of that type would, without exception for
4888     // zero-sized or anonymous bit-fields."
4889     UseBitFieldTypeAlignment = true;
4890     UseZeroLengthBitfieldAlignment = true;
4891 
4892     // AArch64 targets default to using the ARM C++ ABI.
4893     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4894   }
4895 
4896   StringRef getABI() const override { return ABI; }
4897   bool setABI(const std::string &Name) override {
4898     if (Name != "aapcs" && Name != "darwinpcs")
4899       return false;
4900 
4901     ABI = Name;
4902     return true;
4903   }
4904 
4905   bool setCPU(const std::string &Name) override {
4906     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4907                         .Case("generic", true)
4908                         .Cases("cortex-a53", "cortex-a57", "cortex-a72", true)
4909                         .Case("cyclone", true)
4910                         .Default(false);
4911     return CPUKnown;
4912   }
4913 
4914   void getTargetDefines(const LangOptions &Opts,
4915                         MacroBuilder &Builder) const override {
4916     // Target identification.
4917     Builder.defineMacro("__aarch64__");
4918 
4919     // Target properties.
4920     Builder.defineMacro("_LP64");
4921     Builder.defineMacro("__LP64__");
4922 
4923     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4924     Builder.defineMacro("__ARM_ACLE", "200");
4925     Builder.defineMacro("__ARM_ARCH", "8");
4926     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4927 
4928     Builder.defineMacro("__ARM_64BIT_STATE");
4929     Builder.defineMacro("__ARM_PCS_AAPCS64");
4930     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4931 
4932     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4933     Builder.defineMacro("__ARM_FEATURE_CLZ");
4934     Builder.defineMacro("__ARM_FEATURE_FMA");
4935     Builder.defineMacro("__ARM_FEATURE_DIV");
4936     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4937     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4938     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4939     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4940 
4941     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4942 
4943     // 0xe implies support for half, single and double precision operations.
4944     Builder.defineMacro("__ARM_FP", "0xe");
4945 
4946     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4947     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4948     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4949 
4950     if (Opts.FastMath || Opts.FiniteMathOnly)
4951       Builder.defineMacro("__ARM_FP_FAST");
4952 
4953     if (Opts.C99 && !Opts.Freestanding)
4954       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4955 
4956     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4957 
4958     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4959                         Opts.ShortEnums ? "1" : "4");
4960 
4961     if (FPU == NeonMode) {
4962       Builder.defineMacro("__ARM_NEON");
4963       // 64-bit NEON supports half, single and double precision operations.
4964       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4965     }
4966 
4967     if (CRC)
4968       Builder.defineMacro("__ARM_FEATURE_CRC32");
4969 
4970     if (Crypto)
4971       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4972 
4973     // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
4974     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4975     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4976     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4977     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4978   }
4979 
4980   void getTargetBuiltins(const Builtin::Info *&Records,
4981                          unsigned &NumRecords) const override {
4982     Records = BuiltinInfo;
4983     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4984   }
4985 
4986   bool hasFeature(StringRef Feature) const override {
4987     return Feature == "aarch64" ||
4988       Feature == "arm64" ||
4989       (Feature == "neon" && FPU == NeonMode);
4990   }
4991 
4992   bool handleTargetFeatures(std::vector<std::string> &Features,
4993                             DiagnosticsEngine &Diags) override {
4994     FPU = FPUMode;
4995     CRC = 0;
4996     Crypto = 0;
4997     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4998       if (Features[i] == "+neon")
4999         FPU = NeonMode;
5000       if (Features[i] == "+crc")
5001         CRC = 1;
5002       if (Features[i] == "+crypto")
5003         Crypto = 1;
5004     }
5005 
5006     setDescriptionString();
5007 
5008     return true;
5009   }
5010 
5011   bool isCLZForZeroUndef() const override { return false; }
5012 
5013   BuiltinVaListKind getBuiltinVaListKind() const override {
5014     return TargetInfo::AArch64ABIBuiltinVaList;
5015   }
5016 
5017   void getGCCRegNames(const char *const *&Names,
5018                       unsigned &NumNames) const override;
5019   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5020                         unsigned &NumAliases) const override;
5021 
5022   bool validateAsmConstraint(const char *&Name,
5023                              TargetInfo::ConstraintInfo &Info) const override {
5024     switch (*Name) {
5025     default:
5026       return false;
5027     case 'w': // Floating point and SIMD registers (V0-V31)
5028       Info.setAllowsRegister();
5029       return true;
5030     case 'I': // Constant that can be used with an ADD instruction
5031     case 'J': // Constant that can be used with a SUB instruction
5032     case 'K': // Constant that can be used with a 32-bit logical instruction
5033     case 'L': // Constant that can be used with a 64-bit logical instruction
5034     case 'M': // Constant that can be used as a 32-bit MOV immediate
5035     case 'N': // Constant that can be used as a 64-bit MOV immediate
5036     case 'Y': // Floating point constant zero
5037     case 'Z': // Integer constant zero
5038       return true;
5039     case 'Q': // A memory reference with base register and no offset
5040       Info.setAllowsMemory();
5041       return true;
5042     case 'S': // A symbolic address
5043       Info.setAllowsRegister();
5044       return true;
5045     case 'U':
5046       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes.
5047       // Utf: A memory address suitable for ldp/stp in TF mode.
5048       // Usa: An absolute symbolic address.
5049       // Ush: The high part (bits 32:12) of a pc-relative symbolic address.
5050       llvm_unreachable("FIXME: Unimplemented support for U* constraints.");
5051     case 'z': // Zero register, wzr or xzr
5052       Info.setAllowsRegister();
5053       return true;
5054     case 'x': // Floating point and SIMD registers (V0-V15)
5055       Info.setAllowsRegister();
5056       return true;
5057     }
5058     return false;
5059   }
5060 
5061   bool
5062   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
5063                              std::string &SuggestedModifier) const override {
5064     // Strip off constraint modifiers.
5065     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
5066       Constraint = Constraint.substr(1);
5067 
5068     switch (Constraint[0]) {
5069     default:
5070       return true;
5071     case 'z':
5072     case 'r': {
5073       switch (Modifier) {
5074       case 'x':
5075       case 'w':
5076         // For now assume that the person knows what they're
5077         // doing with the modifier.
5078         return true;
5079       default:
5080         // By default an 'r' constraint will be in the 'x'
5081         // registers.
5082         if (Size == 64)
5083           return true;
5084 
5085         SuggestedModifier = "w";
5086         return false;
5087       }
5088     }
5089     }
5090   }
5091 
5092   const char *getClobbers() const override { return ""; }
5093 
5094   int getEHDataRegisterNumber(unsigned RegNo) const override {
5095     if (RegNo == 0)
5096       return 0;
5097     if (RegNo == 1)
5098       return 1;
5099     return -1;
5100   }
5101 };
5102 
5103 const char *const AArch64TargetInfo::GCCRegNames[] = {
5104   // 32-bit Integer registers
5105   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
5106   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
5107   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
5108 
5109   // 64-bit Integer registers
5110   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
5111   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
5112   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
5113 
5114   // 32-bit floating point regsisters
5115   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
5116   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
5117   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
5118 
5119   // 64-bit floating point regsisters
5120   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
5121   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
5122   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
5123 
5124   // Vector registers
5125   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
5126   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
5127   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
5128 };
5129 
5130 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
5131                                      unsigned &NumNames) const {
5132   Names = GCCRegNames;
5133   NumNames = llvm::array_lengthof(GCCRegNames);
5134 }
5135 
5136 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
5137   { { "w31" }, "wsp" },
5138   { { "x29" }, "fp" },
5139   { { "x30" }, "lr" },
5140   { { "x31" }, "sp" },
5141   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
5142   // don't want to substitute one of these for a different-sized one.
5143 };
5144 
5145 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5146                                        unsigned &NumAliases) const {
5147   Aliases = GCCRegAliases;
5148   NumAliases = llvm::array_lengthof(GCCRegAliases);
5149 }
5150 
5151 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
5152 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5153   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5154 #include "clang/Basic/BuiltinsNEON.def"
5155 
5156 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5157   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5158 #include "clang/Basic/BuiltinsAArch64.def"
5159 };
5160 
5161 class AArch64leTargetInfo : public AArch64TargetInfo {
5162   void setDescriptionString() override {
5163     if (getTriple().isOSBinFormatMachO())
5164       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
5165     else
5166       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
5167   }
5168 
5169 public:
5170   AArch64leTargetInfo(const llvm::Triple &Triple)
5171     : AArch64TargetInfo(Triple) {
5172     BigEndian = false;
5173     }
5174   void getTargetDefines(const LangOptions &Opts,
5175                         MacroBuilder &Builder) const override {
5176     Builder.defineMacro("__AARCH64EL__");
5177     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5178   }
5179 };
5180 
5181 class AArch64beTargetInfo : public AArch64TargetInfo {
5182   void setDescriptionString() override {
5183     assert(!getTriple().isOSBinFormatMachO());
5184     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
5185   }
5186 
5187 public:
5188   AArch64beTargetInfo(const llvm::Triple &Triple)
5189     : AArch64TargetInfo(Triple) { }
5190   void getTargetDefines(const LangOptions &Opts,
5191                         MacroBuilder &Builder) const override {
5192     Builder.defineMacro("__AARCH64EB__");
5193     Builder.defineMacro("__AARCH_BIG_ENDIAN");
5194     Builder.defineMacro("__ARM_BIG_ENDIAN");
5195     AArch64TargetInfo::getTargetDefines(Opts, Builder);
5196   }
5197 };
5198 
5199 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
5200 protected:
5201   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
5202                     MacroBuilder &Builder) const override {
5203     Builder.defineMacro("__AARCH64_SIMD__");
5204     Builder.defineMacro("__ARM64_ARCH_8__");
5205     Builder.defineMacro("__ARM_NEON__");
5206     Builder.defineMacro("__LITTLE_ENDIAN__");
5207     Builder.defineMacro("__REGISTER_PREFIX__", "");
5208     Builder.defineMacro("__arm64", "1");
5209     Builder.defineMacro("__arm64__", "1");
5210 
5211     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
5212   }
5213 
5214 public:
5215   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
5216       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
5217     Int64Type = SignedLongLong;
5218     WCharType = SignedInt;
5219     UseSignedCharForObjCBool = false;
5220 
5221     LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64;
5222     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5223 
5224     TheCXXABI.set(TargetCXXABI::iOS64);
5225   }
5226 
5227   BuiltinVaListKind getBuiltinVaListKind() const override {
5228     return TargetInfo::CharPtrBuiltinVaList;
5229   }
5230 };
5231 
5232 // Hexagon abstract base class
5233 class HexagonTargetInfo : public TargetInfo {
5234   static const Builtin::Info BuiltinInfo[];
5235   static const char * const GCCRegNames[];
5236   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5237   std::string CPU;
5238 public:
5239   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5240     BigEndian = false;
5241     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
5242 
5243     // {} in inline assembly are packet specifiers, not assembly variant
5244     // specifiers.
5245     NoAsmVariants = true;
5246   }
5247 
5248   void getTargetBuiltins(const Builtin::Info *&Records,
5249                          unsigned &NumRecords) const override {
5250     Records = BuiltinInfo;
5251     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
5252   }
5253 
5254   bool validateAsmConstraint(const char *&Name,
5255                              TargetInfo::ConstraintInfo &Info) const override {
5256     return true;
5257   }
5258 
5259   void getTargetDefines(const LangOptions &Opts,
5260                         MacroBuilder &Builder) const override;
5261 
5262   bool hasFeature(StringRef Feature) const override {
5263     return Feature == "hexagon";
5264   }
5265 
5266   BuiltinVaListKind getBuiltinVaListKind() const override {
5267     return TargetInfo::CharPtrBuiltinVaList;
5268   }
5269   void getGCCRegNames(const char * const *&Names,
5270                       unsigned &NumNames) const override;
5271   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5272                         unsigned &NumAliases) const override;
5273   const char *getClobbers() const override {
5274     return "";
5275   }
5276 
5277   static const char *getHexagonCPUSuffix(StringRef Name) {
5278     return llvm::StringSwitch<const char*>(Name)
5279       .Case("hexagonv4", "4")
5280       .Case("hexagonv5", "5")
5281       .Default(nullptr);
5282   }
5283 
5284   bool setCPU(const std::string &Name) override {
5285     if (!getHexagonCPUSuffix(Name))
5286       return false;
5287 
5288     CPU = Name;
5289     return true;
5290   }
5291 };
5292 
5293 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
5294                                 MacroBuilder &Builder) const {
5295   Builder.defineMacro("qdsp6");
5296   Builder.defineMacro("__qdsp6", "1");
5297   Builder.defineMacro("__qdsp6__", "1");
5298 
5299   Builder.defineMacro("hexagon");
5300   Builder.defineMacro("__hexagon", "1");
5301   Builder.defineMacro("__hexagon__", "1");
5302 
5303   if(CPU == "hexagonv1") {
5304     Builder.defineMacro("__HEXAGON_V1__");
5305     Builder.defineMacro("__HEXAGON_ARCH__", "1");
5306     if(Opts.HexagonQdsp6Compat) {
5307       Builder.defineMacro("__QDSP6_V1__");
5308       Builder.defineMacro("__QDSP6_ARCH__", "1");
5309     }
5310   }
5311   else if(CPU == "hexagonv2") {
5312     Builder.defineMacro("__HEXAGON_V2__");
5313     Builder.defineMacro("__HEXAGON_ARCH__", "2");
5314     if(Opts.HexagonQdsp6Compat) {
5315       Builder.defineMacro("__QDSP6_V2__");
5316       Builder.defineMacro("__QDSP6_ARCH__", "2");
5317     }
5318   }
5319   else if(CPU == "hexagonv3") {
5320     Builder.defineMacro("__HEXAGON_V3__");
5321     Builder.defineMacro("__HEXAGON_ARCH__", "3");
5322     if(Opts.HexagonQdsp6Compat) {
5323       Builder.defineMacro("__QDSP6_V3__");
5324       Builder.defineMacro("__QDSP6_ARCH__", "3");
5325     }
5326   }
5327   else if(CPU == "hexagonv4") {
5328     Builder.defineMacro("__HEXAGON_V4__");
5329     Builder.defineMacro("__HEXAGON_ARCH__", "4");
5330     if(Opts.HexagonQdsp6Compat) {
5331       Builder.defineMacro("__QDSP6_V4__");
5332       Builder.defineMacro("__QDSP6_ARCH__", "4");
5333     }
5334   }
5335   else if(CPU == "hexagonv5") {
5336     Builder.defineMacro("__HEXAGON_V5__");
5337     Builder.defineMacro("__HEXAGON_ARCH__", "5");
5338     if(Opts.HexagonQdsp6Compat) {
5339       Builder.defineMacro("__QDSP6_V5__");
5340       Builder.defineMacro("__QDSP6_ARCH__", "5");
5341     }
5342   }
5343 }
5344 
5345 const char * const HexagonTargetInfo::GCCRegNames[] = {
5346   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5347   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5348   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5349   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5350   "p0", "p1", "p2", "p3",
5351   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5352 };
5353 
5354 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5355                                    unsigned &NumNames) const {
5356   Names = GCCRegNames;
5357   NumNames = llvm::array_lengthof(GCCRegNames);
5358 }
5359 
5360 
5361 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5362   { { "sp" }, "r29" },
5363   { { "fp" }, "r30" },
5364   { { "lr" }, "r31" },
5365  };
5366 
5367 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5368                                      unsigned &NumAliases) const {
5369   Aliases = GCCRegAliases;
5370   NumAliases = llvm::array_lengthof(GCCRegAliases);
5371 }
5372 
5373 
5374 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5375 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5376 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5377                                               ALL_LANGUAGES },
5378 #include "clang/Basic/BuiltinsHexagon.def"
5379 };
5380 
5381 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5382 class SparcTargetInfo : public TargetInfo {
5383   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5384   static const char * const GCCRegNames[];
5385   bool SoftFloat;
5386 public:
5387   SparcTargetInfo(const llvm::Triple &Triple)
5388       : TargetInfo(Triple), SoftFloat(false) {}
5389 
5390   bool handleTargetFeatures(std::vector<std::string> &Features,
5391                             DiagnosticsEngine &Diags) override {
5392     // The backend doesn't actually handle soft float yet, but in case someone
5393     // is using the support for the front end continue to support it.
5394     auto Feature = std::find(Features.begin(), Features.end(), "+soft-float");
5395     if (Feature != Features.end()) {
5396       SoftFloat = true;
5397       Features.erase(Feature);
5398     }
5399     return true;
5400   }
5401   void getTargetDefines(const LangOptions &Opts,
5402                         MacroBuilder &Builder) const override {
5403     DefineStd(Builder, "sparc", Opts);
5404     Builder.defineMacro("__REGISTER_PREFIX__", "");
5405 
5406     if (SoftFloat)
5407       Builder.defineMacro("SOFT_FLOAT", "1");
5408   }
5409 
5410   bool hasFeature(StringRef Feature) const override {
5411     return llvm::StringSwitch<bool>(Feature)
5412              .Case("softfloat", SoftFloat)
5413              .Case("sparc", true)
5414              .Default(false);
5415   }
5416 
5417   void getTargetBuiltins(const Builtin::Info *&Records,
5418                          unsigned &NumRecords) const override {
5419     // FIXME: Implement!
5420   }
5421   BuiltinVaListKind getBuiltinVaListKind() const override {
5422     return TargetInfo::VoidPtrBuiltinVaList;
5423   }
5424   void getGCCRegNames(const char * const *&Names,
5425                       unsigned &NumNames) const override;
5426   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5427                         unsigned &NumAliases) const override;
5428   bool validateAsmConstraint(const char *&Name,
5429                              TargetInfo::ConstraintInfo &info) const override {
5430     // FIXME: Implement!
5431     switch (*Name) {
5432     case 'I': // Signed 13-bit constant
5433     case 'J': // Zero
5434     case 'K': // 32-bit constant with the low 12 bits clear
5435     case 'L': // A constant in the range supported by movcc (11-bit signed imm)
5436     case 'M': // A constant in the range supported by movrcc (19-bit signed imm)
5437     case 'N': // Same as 'K' but zext (required for SIMode)
5438     case 'O': // The constant 4096
5439       return true;
5440     }
5441     return false;
5442   }
5443   const char *getClobbers() const override {
5444     // FIXME: Implement!
5445     return "";
5446   }
5447 };
5448 
5449 const char * const SparcTargetInfo::GCCRegNames[] = {
5450   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5451   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5452   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5453   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5454 };
5455 
5456 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5457                                      unsigned &NumNames) const {
5458   Names = GCCRegNames;
5459   NumNames = llvm::array_lengthof(GCCRegNames);
5460 }
5461 
5462 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5463   { { "g0" }, "r0" },
5464   { { "g1" }, "r1" },
5465   { { "g2" }, "r2" },
5466   { { "g3" }, "r3" },
5467   { { "g4" }, "r4" },
5468   { { "g5" }, "r5" },
5469   { { "g6" }, "r6" },
5470   { { "g7" }, "r7" },
5471   { { "o0" }, "r8" },
5472   { { "o1" }, "r9" },
5473   { { "o2" }, "r10" },
5474   { { "o3" }, "r11" },
5475   { { "o4" }, "r12" },
5476   { { "o5" }, "r13" },
5477   { { "o6", "sp" }, "r14" },
5478   { { "o7" }, "r15" },
5479   { { "l0" }, "r16" },
5480   { { "l1" }, "r17" },
5481   { { "l2" }, "r18" },
5482   { { "l3" }, "r19" },
5483   { { "l4" }, "r20" },
5484   { { "l5" }, "r21" },
5485   { { "l6" }, "r22" },
5486   { { "l7" }, "r23" },
5487   { { "i0" }, "r24" },
5488   { { "i1" }, "r25" },
5489   { { "i2" }, "r26" },
5490   { { "i3" }, "r27" },
5491   { { "i4" }, "r28" },
5492   { { "i5" }, "r29" },
5493   { { "i6", "fp" }, "r30" },
5494   { { "i7" }, "r31" },
5495 };
5496 
5497 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5498                                        unsigned &NumAliases) const {
5499   Aliases = GCCRegAliases;
5500   NumAliases = llvm::array_lengthof(GCCRegAliases);
5501 }
5502 
5503 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5504 class SparcV8TargetInfo : public SparcTargetInfo {
5505 public:
5506   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5507     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5508     // NetBSD uses long (same as llvm default); everyone else uses int.
5509     if (getTriple().getOS() == llvm::Triple::NetBSD) {
5510       SizeType = UnsignedLong;
5511       IntPtrType = SignedLong;
5512       PtrDiffType = SignedLong;
5513     } else {
5514       SizeType = UnsignedInt;
5515       IntPtrType = SignedInt;
5516       PtrDiffType = SignedInt;
5517     }
5518   }
5519 
5520   void getTargetDefines(const LangOptions &Opts,
5521                         MacroBuilder &Builder) const override {
5522     SparcTargetInfo::getTargetDefines(Opts, Builder);
5523     Builder.defineMacro("__sparcv8");
5524   }
5525 };
5526 
5527 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel.
5528 class SparcV8elTargetInfo : public SparcV8TargetInfo {
5529  public:
5530   SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) {
5531     DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64";
5532     BigEndian = false;
5533   }
5534 };
5535 
5536 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5537 class SparcV9TargetInfo : public SparcTargetInfo {
5538 public:
5539   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5540     // FIXME: Support Sparc quad-precision long double?
5541     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5542     // This is an LP64 platform.
5543     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5544 
5545     // OpenBSD uses long long for int64_t and intmax_t.
5546     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5547       IntMaxType = SignedLongLong;
5548     else
5549       IntMaxType = SignedLong;
5550     Int64Type = IntMaxType;
5551 
5552     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5553     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5554     LongDoubleWidth = 128;
5555     LongDoubleAlign = 128;
5556     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5557     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5558   }
5559 
5560   void getTargetDefines(const LangOptions &Opts,
5561                         MacroBuilder &Builder) const override {
5562     SparcTargetInfo::getTargetDefines(Opts, Builder);
5563     Builder.defineMacro("__sparcv9");
5564     Builder.defineMacro("__arch64__");
5565     // Solaris doesn't need these variants, but the BSDs do.
5566     if (getTriple().getOS() != llvm::Triple::Solaris) {
5567       Builder.defineMacro("__sparc64__");
5568       Builder.defineMacro("__sparc_v9__");
5569       Builder.defineMacro("__sparcv9__");
5570     }
5571   }
5572 
5573   bool setCPU(const std::string &Name) override {
5574     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5575       .Case("v9", true)
5576       .Case("ultrasparc", true)
5577       .Case("ultrasparc3", true)
5578       .Case("niagara", true)
5579       .Case("niagara2", true)
5580       .Case("niagara3", true)
5581       .Case("niagara4", true)
5582       .Default(false);
5583 
5584     // No need to store the CPU yet.  There aren't any CPU-specific
5585     // macros to define.
5586     return CPUKnown;
5587   }
5588 };
5589 
5590 class SystemZTargetInfo : public TargetInfo {
5591   static const Builtin::Info BuiltinInfo[];
5592   static const char *const GCCRegNames[];
5593   std::string CPU;
5594   bool HasTransactionalExecution;
5595   bool HasVector;
5596 
5597 public:
5598   SystemZTargetInfo(const llvm::Triple &Triple)
5599     : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) {
5600     IntMaxType = SignedLong;
5601     Int64Type = SignedLong;
5602     TLSSupported = true;
5603     IntWidth = IntAlign = 32;
5604     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5605     PointerWidth = PointerAlign = 64;
5606     LongDoubleWidth = 128;
5607     LongDoubleAlign = 64;
5608     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5609     DefaultAlignForAttributeAligned = 64;
5610     MinGlobalAlign = 16;
5611     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5612     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5613   }
5614   void getTargetDefines(const LangOptions &Opts,
5615                         MacroBuilder &Builder) const override {
5616     Builder.defineMacro("__s390__");
5617     Builder.defineMacro("__s390x__");
5618     Builder.defineMacro("__zarch__");
5619     Builder.defineMacro("__LONG_DOUBLE_128__");
5620     if (HasTransactionalExecution)
5621       Builder.defineMacro("__HTM__");
5622   }
5623   void getTargetBuiltins(const Builtin::Info *&Records,
5624                          unsigned &NumRecords) const override {
5625     Records = BuiltinInfo;
5626     NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin;
5627   }
5628 
5629   void getGCCRegNames(const char *const *&Names,
5630                       unsigned &NumNames) const override;
5631   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5632                         unsigned &NumAliases) const override {
5633     // No aliases.
5634     Aliases = nullptr;
5635     NumAliases = 0;
5636   }
5637   bool validateAsmConstraint(const char *&Name,
5638                              TargetInfo::ConstraintInfo &info) const override;
5639   const char *getClobbers() const override {
5640     // FIXME: Is this really right?
5641     return "";
5642   }
5643   BuiltinVaListKind getBuiltinVaListKind() const override {
5644     return TargetInfo::SystemZBuiltinVaList;
5645   }
5646   bool setCPU(const std::string &Name) override {
5647     CPU = Name;
5648     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5649       .Case("z10", true)
5650       .Case("z196", true)
5651       .Case("zEC12", true)
5652       .Case("z13", true)
5653       .Default(false);
5654 
5655     return CPUKnown;
5656   }
5657   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5658     if (CPU == "zEC12")
5659       Features["transactional-execution"] = true;
5660     if (CPU == "z13") {
5661       Features["transactional-execution"] = true;
5662       Features["vector"] = true;
5663     }
5664   }
5665 
5666   bool handleTargetFeatures(std::vector<std::string> &Features,
5667                             DiagnosticsEngine &Diags) override {
5668     HasTransactionalExecution = false;
5669     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
5670       if (Features[i] == "+transactional-execution")
5671         HasTransactionalExecution = true;
5672       if (Features[i] == "+vector")
5673         HasVector = true;
5674     }
5675     // If we use the vector ABI, vector types are 64-bit aligned.
5676     if (HasVector) {
5677       MaxVectorAlign = 64;
5678       DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64"
5679                           "-v128:64-a:8:16-n32:64";
5680     }
5681     return true;
5682   }
5683 
5684   bool hasFeature(StringRef Feature) const override {
5685     return llvm::StringSwitch<bool>(Feature)
5686         .Case("systemz", true)
5687         .Case("htm", HasTransactionalExecution)
5688         .Case("vx", HasVector)
5689         .Default(false);
5690   }
5691 
5692   StringRef getABI() const override {
5693     if (HasVector)
5694       return "vector";
5695     return "";
5696   }
5697 };
5698 
5699 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = {
5700 #define BUILTIN(ID, TYPE, ATTRS)                                               \
5701   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5702 #include "clang/Basic/BuiltinsSystemZ.def"
5703 };
5704 
5705 const char *const SystemZTargetInfo::GCCRegNames[] = {
5706   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5707   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5708   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5709   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5710 };
5711 
5712 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5713                                        unsigned &NumNames) const {
5714   Names = GCCRegNames;
5715   NumNames = llvm::array_lengthof(GCCRegNames);
5716 }
5717 
5718 bool SystemZTargetInfo::
5719 validateAsmConstraint(const char *&Name,
5720                       TargetInfo::ConstraintInfo &Info) const {
5721   switch (*Name) {
5722   default:
5723     return false;
5724 
5725   case 'a': // Address register
5726   case 'd': // Data register (equivalent to 'r')
5727   case 'f': // Floating-point register
5728     Info.setAllowsRegister();
5729     return true;
5730 
5731   case 'I': // Unsigned 8-bit constant
5732   case 'J': // Unsigned 12-bit constant
5733   case 'K': // Signed 16-bit constant
5734   case 'L': // Signed 20-bit displacement (on all targets we support)
5735   case 'M': // 0x7fffffff
5736     return true;
5737 
5738   case 'Q': // Memory with base and unsigned 12-bit displacement
5739   case 'R': // Likewise, plus an index
5740   case 'S': // Memory with base and signed 20-bit displacement
5741   case 'T': // Likewise, plus an index
5742     Info.setAllowsMemory();
5743     return true;
5744   }
5745 }
5746 
5747   class MSP430TargetInfo : public TargetInfo {
5748     static const char * const GCCRegNames[];
5749   public:
5750     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5751       BigEndian = false;
5752       TLSSupported = false;
5753       IntWidth = 16; IntAlign = 16;
5754       LongWidth = 32; LongLongWidth = 64;
5755       LongAlign = LongLongAlign = 16;
5756       PointerWidth = 16; PointerAlign = 16;
5757       SuitableAlign = 16;
5758       SizeType = UnsignedInt;
5759       IntMaxType = SignedLongLong;
5760       IntPtrType = SignedInt;
5761       PtrDiffType = SignedInt;
5762       SigAtomicType = SignedLong;
5763       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5764     }
5765     void getTargetDefines(const LangOptions &Opts,
5766                           MacroBuilder &Builder) const override {
5767       Builder.defineMacro("MSP430");
5768       Builder.defineMacro("__MSP430__");
5769       // FIXME: defines for different 'flavours' of MCU
5770     }
5771     void getTargetBuiltins(const Builtin::Info *&Records,
5772                            unsigned &NumRecords) const override {
5773       // FIXME: Implement.
5774       Records = nullptr;
5775       NumRecords = 0;
5776     }
5777     bool hasFeature(StringRef Feature) const override {
5778       return Feature == "msp430";
5779     }
5780     void getGCCRegNames(const char * const *&Names,
5781                         unsigned &NumNames) const override;
5782     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5783                           unsigned &NumAliases) const override {
5784       // No aliases.
5785       Aliases = nullptr;
5786       NumAliases = 0;
5787     }
5788     bool
5789     validateAsmConstraint(const char *&Name,
5790                           TargetInfo::ConstraintInfo &info) const override {
5791       // FIXME: implement
5792       switch (*Name) {
5793       case 'K': // the constant 1
5794       case 'L': // constant -1^20 .. 1^19
5795       case 'M': // constant 1-4:
5796         return true;
5797       }
5798       // No target constraints for now.
5799       return false;
5800     }
5801     const char *getClobbers() const override {
5802       // FIXME: Is this really right?
5803       return "";
5804     }
5805     BuiltinVaListKind getBuiltinVaListKind() const override {
5806       // FIXME: implement
5807       return TargetInfo::CharPtrBuiltinVaList;
5808    }
5809   };
5810 
5811   const char * const MSP430TargetInfo::GCCRegNames[] = {
5812     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5813     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5814   };
5815 
5816   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5817                                         unsigned &NumNames) const {
5818     Names = GCCRegNames;
5819     NumNames = llvm::array_lengthof(GCCRegNames);
5820   }
5821 
5822   // LLVM and Clang cannot be used directly to output native binaries for
5823   // target, but is used to compile C code to llvm bitcode with correct
5824   // type and alignment information.
5825   //
5826   // TCE uses the llvm bitcode as input and uses it for generating customized
5827   // target processor and program binary. TCE co-design environment is
5828   // publicly available in http://tce.cs.tut.fi
5829 
5830   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5831       3, // opencl_global
5832       4, // opencl_local
5833       5, // opencl_constant
5834       // FIXME: generic has to be added to the target
5835       0, // opencl_generic
5836       0, // cuda_device
5837       0, // cuda_constant
5838       0  // cuda_shared
5839   };
5840 
5841   class TCETargetInfo : public TargetInfo{
5842   public:
5843     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5844       TLSSupported = false;
5845       IntWidth = 32;
5846       LongWidth = LongLongWidth = 32;
5847       PointerWidth = 32;
5848       IntAlign = 32;
5849       LongAlign = LongLongAlign = 32;
5850       PointerAlign = 32;
5851       SuitableAlign = 32;
5852       SizeType = UnsignedInt;
5853       IntMaxType = SignedLong;
5854       IntPtrType = SignedInt;
5855       PtrDiffType = SignedInt;
5856       FloatWidth = 32;
5857       FloatAlign = 32;
5858       DoubleWidth = 32;
5859       DoubleAlign = 32;
5860       LongDoubleWidth = 32;
5861       LongDoubleAlign = 32;
5862       FloatFormat = &llvm::APFloat::IEEEsingle;
5863       DoubleFormat = &llvm::APFloat::IEEEsingle;
5864       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5865       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5866                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5867       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5868       UseAddrSpaceMapMangling = true;
5869     }
5870 
5871     void getTargetDefines(const LangOptions &Opts,
5872                           MacroBuilder &Builder) const override {
5873       DefineStd(Builder, "tce", Opts);
5874       Builder.defineMacro("__TCE__");
5875       Builder.defineMacro("__TCE_V1__");
5876     }
5877     bool hasFeature(StringRef Feature) const override {
5878       return Feature == "tce";
5879     }
5880 
5881     void getTargetBuiltins(const Builtin::Info *&Records,
5882                            unsigned &NumRecords) const override {}
5883     const char *getClobbers() const override {
5884       return "";
5885     }
5886     BuiltinVaListKind getBuiltinVaListKind() const override {
5887       return TargetInfo::VoidPtrBuiltinVaList;
5888     }
5889     void getGCCRegNames(const char * const *&Names,
5890                         unsigned &NumNames) const override {}
5891     bool validateAsmConstraint(const char *&Name,
5892                                TargetInfo::ConstraintInfo &info) const override{
5893       return true;
5894     }
5895     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5896                           unsigned &NumAliases) const override {}
5897   };
5898 
5899 class BPFTargetInfo : public TargetInfo {
5900 public:
5901   BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5902     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5903     SizeType    = UnsignedLong;
5904     PtrDiffType = SignedLong;
5905     IntPtrType  = SignedLong;
5906     IntMaxType  = SignedLong;
5907     Int64Type   = SignedLong;
5908     RegParmMax = 5;
5909     if (Triple.getArch() == llvm::Triple::bpfeb) {
5910       BigEndian = true;
5911       DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128";
5912     } else {
5913       BigEndian = false;
5914       DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128";
5915     }
5916     MaxAtomicPromoteWidth = 64;
5917     MaxAtomicInlineWidth = 64;
5918     TLSSupported = false;
5919   }
5920   void getTargetDefines(const LangOptions &Opts,
5921                         MacroBuilder &Builder) const override {
5922     DefineStd(Builder, "bpf", Opts);
5923     Builder.defineMacro("__BPF__");
5924   }
5925   bool hasFeature(StringRef Feature) const override {
5926     return Feature == "bpf";
5927   }
5928 
5929   void getTargetBuiltins(const Builtin::Info *&Records,
5930                          unsigned &NumRecords) const override {}
5931   const char *getClobbers() const override {
5932     return "";
5933   }
5934   BuiltinVaListKind getBuiltinVaListKind() const override {
5935     return TargetInfo::VoidPtrBuiltinVaList;
5936   }
5937   void getGCCRegNames(const char * const *&Names,
5938                       unsigned &NumNames) const override {
5939     Names = nullptr;
5940     NumNames = 0;
5941   }
5942   bool validateAsmConstraint(const char *&Name,
5943                              TargetInfo::ConstraintInfo &info) const override {
5944     return true;
5945   }
5946   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5947                         unsigned &NumAliases) const override {
5948     Aliases = nullptr;
5949     NumAliases = 0;
5950   }
5951 };
5952 
5953 class MipsTargetInfoBase : public TargetInfo {
5954   virtual void setDescriptionString() = 0;
5955 
5956   static const Builtin::Info BuiltinInfo[];
5957   std::string CPU;
5958   bool IsMips16;
5959   bool IsMicromips;
5960   bool IsNan2008;
5961   bool IsSingleFloat;
5962   enum MipsFloatABI {
5963     HardFloat, SoftFloat
5964   } FloatABI;
5965   enum DspRevEnum {
5966     NoDSP, DSP1, DSP2
5967   } DspRev;
5968   bool HasMSA;
5969 
5970 protected:
5971   bool HasFP64;
5972   std::string ABI;
5973 
5974 public:
5975   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5976                      const std::string &CPUStr)
5977       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5978         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5979         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {
5980     TheCXXABI.set(TargetCXXABI::GenericMIPS);
5981   }
5982 
5983   bool isNaN2008Default() const {
5984     return CPU == "mips32r6" || CPU == "mips64r6";
5985   }
5986 
5987   bool isFP64Default() const {
5988     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5989   }
5990 
5991   bool isNan2008() const override {
5992     return IsNan2008;
5993   }
5994 
5995   StringRef getABI() const override { return ABI; }
5996   bool setCPU(const std::string &Name) override {
5997     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5998                     getTriple().getArch() == llvm::Triple::mipsel;
5999     CPU = Name;
6000     return llvm::StringSwitch<bool>(Name)
6001         .Case("mips1", IsMips32)
6002         .Case("mips2", IsMips32)
6003         .Case("mips3", true)
6004         .Case("mips4", true)
6005         .Case("mips5", true)
6006         .Case("mips32", IsMips32)
6007         .Case("mips32r2", IsMips32)
6008         .Case("mips32r3", IsMips32)
6009         .Case("mips32r5", IsMips32)
6010         .Case("mips32r6", IsMips32)
6011         .Case("mips64", true)
6012         .Case("mips64r2", true)
6013         .Case("mips64r3", true)
6014         .Case("mips64r5", true)
6015         .Case("mips64r6", true)
6016         .Case("octeon", true)
6017         .Default(false);
6018   }
6019   const std::string& getCPU() const { return CPU; }
6020   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6021     if (CPU == "octeon")
6022       Features["mips64r2"] = Features["cnmips"] = true;
6023     else
6024       Features[CPU] = true;
6025   }
6026 
6027   void getTargetDefines(const LangOptions &Opts,
6028                         MacroBuilder &Builder) const override {
6029     Builder.defineMacro("__mips__");
6030     Builder.defineMacro("_mips");
6031     if (Opts.GNUMode)
6032       Builder.defineMacro("mips");
6033 
6034     Builder.defineMacro("__REGISTER_PREFIX__", "");
6035 
6036     switch (FloatABI) {
6037     case HardFloat:
6038       Builder.defineMacro("__mips_hard_float", Twine(1));
6039       break;
6040     case SoftFloat:
6041       Builder.defineMacro("__mips_soft_float", Twine(1));
6042       break;
6043     }
6044 
6045     if (IsSingleFloat)
6046       Builder.defineMacro("__mips_single_float", Twine(1));
6047 
6048     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
6049     Builder.defineMacro("_MIPS_FPSET",
6050                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
6051 
6052     if (IsMips16)
6053       Builder.defineMacro("__mips16", Twine(1));
6054 
6055     if (IsMicromips)
6056       Builder.defineMacro("__mips_micromips", Twine(1));
6057 
6058     if (IsNan2008)
6059       Builder.defineMacro("__mips_nan2008", Twine(1));
6060 
6061     switch (DspRev) {
6062     default:
6063       break;
6064     case DSP1:
6065       Builder.defineMacro("__mips_dsp_rev", Twine(1));
6066       Builder.defineMacro("__mips_dsp", Twine(1));
6067       break;
6068     case DSP2:
6069       Builder.defineMacro("__mips_dsp_rev", Twine(2));
6070       Builder.defineMacro("__mips_dspr2", Twine(1));
6071       Builder.defineMacro("__mips_dsp", Twine(1));
6072       break;
6073     }
6074 
6075     if (HasMSA)
6076       Builder.defineMacro("__mips_msa", Twine(1));
6077 
6078     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
6079     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
6080     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
6081 
6082     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
6083     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
6084   }
6085 
6086   void getTargetBuiltins(const Builtin::Info *&Records,
6087                          unsigned &NumRecords) const override {
6088     Records = BuiltinInfo;
6089     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
6090   }
6091   bool hasFeature(StringRef Feature) const override {
6092     return llvm::StringSwitch<bool>(Feature)
6093       .Case("mips", true)
6094       .Case("fp64", HasFP64)
6095       .Default(false);
6096   }
6097   BuiltinVaListKind getBuiltinVaListKind() const override {
6098     return TargetInfo::VoidPtrBuiltinVaList;
6099   }
6100   void getGCCRegNames(const char * const *&Names,
6101                       unsigned &NumNames) const override {
6102     static const char *const GCCRegNames[] = {
6103       // CPU register names
6104       // Must match second column of GCCRegAliases
6105       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
6106       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
6107       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
6108       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
6109       // Floating point register names
6110       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
6111       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
6112       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
6113       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
6114       // Hi/lo and condition register names
6115       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
6116       "$fcc5","$fcc6","$fcc7",
6117       // MSA register names
6118       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
6119       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
6120       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
6121       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
6122       // MSA control register names
6123       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
6124       "$msarequest", "$msamap", "$msaunmap"
6125     };
6126     Names = GCCRegNames;
6127     NumNames = llvm::array_lengthof(GCCRegNames);
6128   }
6129   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6130                         unsigned &NumAliases) const override = 0;
6131   bool validateAsmConstraint(const char *&Name,
6132                              TargetInfo::ConstraintInfo &Info) const override {
6133     switch (*Name) {
6134     default:
6135       return false;
6136     case 'r': // CPU registers.
6137     case 'd': // Equivalent to "r" unless generating MIPS16 code.
6138     case 'y': // Equivalent to "r", backward compatibility only.
6139     case 'f': // floating-point registers.
6140     case 'c': // $25 for indirect jumps
6141     case 'l': // lo register
6142     case 'x': // hilo register pair
6143       Info.setAllowsRegister();
6144       return true;
6145     case 'I': // Signed 16-bit constant
6146     case 'J': // Integer 0
6147     case 'K': // Unsigned 16-bit constant
6148     case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui)
6149     case 'M': // Constants not loadable via lui, addiu, or ori
6150     case 'N': // Constant -1 to -65535
6151     case 'O': // A signed 15-bit constant
6152     case 'P': // A constant between 1 go 65535
6153       return true;
6154     case 'R': // An address that can be used in a non-macro load or store
6155       Info.setAllowsMemory();
6156       return true;
6157     case 'Z':
6158       if (Name[1] == 'C') { // An address usable by ll, and sc.
6159         Info.setAllowsMemory();
6160         Name++; // Skip over 'Z'.
6161         return true;
6162       }
6163       return false;
6164     }
6165   }
6166 
6167   std::string convertConstraint(const char *&Constraint) const override {
6168     std::string R;
6169     switch (*Constraint) {
6170     case 'Z': // Two-character constraint; add "^" hint for later parsing.
6171       if (Constraint[1] == 'C') {
6172         R = std::string("^") + std::string(Constraint, 2);
6173         Constraint++;
6174         return R;
6175       }
6176       break;
6177     }
6178     return TargetInfo::convertConstraint(Constraint);
6179   }
6180 
6181   const char *getClobbers() const override {
6182     // In GCC, $1 is not widely used in generated code (it's used only in a few
6183     // specific situations), so there is no real need for users to add it to
6184     // the clobbers list if they want to use it in their inline assembly code.
6185     //
6186     // In LLVM, $1 is treated as a normal GPR and is always allocatable during
6187     // code generation, so using it in inline assembly without adding it to the
6188     // clobbers list can cause conflicts between the inline assembly code and
6189     // the surrounding generated code.
6190     //
6191     // Another problem is that LLVM is allowed to choose $1 for inline assembly
6192     // operands, which will conflict with the ".set at" assembler option (which
6193     // we use only for inline assembly, in order to maintain compatibility with
6194     // GCC) and will also conflict with the user's usage of $1.
6195     //
6196     // The easiest way to avoid these conflicts and keep $1 as an allocatable
6197     // register for generated code is to automatically clobber $1 for all inline
6198     // assembly code.
6199     //
6200     // FIXME: We should automatically clobber $1 only for inline assembly code
6201     // which actually uses it. This would allow LLVM to use $1 for inline
6202     // assembly operands if the user's assembly code doesn't use it.
6203     return "~{$1}";
6204   }
6205 
6206   bool handleTargetFeatures(std::vector<std::string> &Features,
6207                             DiagnosticsEngine &Diags) override {
6208     IsMips16 = false;
6209     IsMicromips = false;
6210     IsNan2008 = isNaN2008Default();
6211     IsSingleFloat = false;
6212     FloatABI = HardFloat;
6213     DspRev = NoDSP;
6214     HasFP64 = isFP64Default();
6215 
6216     for (std::vector<std::string>::iterator it = Features.begin(),
6217          ie = Features.end(); it != ie; ++it) {
6218       if (*it == "+single-float")
6219         IsSingleFloat = true;
6220       else if (*it == "+soft-float")
6221         FloatABI = SoftFloat;
6222       else if (*it == "+mips16")
6223         IsMips16 = true;
6224       else if (*it == "+micromips")
6225         IsMicromips = true;
6226       else if (*it == "+dsp")
6227         DspRev = std::max(DspRev, DSP1);
6228       else if (*it == "+dspr2")
6229         DspRev = std::max(DspRev, DSP2);
6230       else if (*it == "+msa")
6231         HasMSA = true;
6232       else if (*it == "+fp64")
6233         HasFP64 = true;
6234       else if (*it == "-fp64")
6235         HasFP64 = false;
6236       else if (*it == "+nan2008")
6237         IsNan2008 = true;
6238       else if (*it == "-nan2008")
6239         IsNan2008 = false;
6240     }
6241 
6242     setDescriptionString();
6243 
6244     return true;
6245   }
6246 
6247   int getEHDataRegisterNumber(unsigned RegNo) const override {
6248     if (RegNo == 0) return 4;
6249     if (RegNo == 1) return 5;
6250     return -1;
6251   }
6252 
6253   bool isCLZForZeroUndef() const override { return false; }
6254 };
6255 
6256 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
6257 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6258 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6259                                               ALL_LANGUAGES },
6260 #include "clang/Basic/BuiltinsMips.def"
6261 };
6262 
6263 class Mips32TargetInfoBase : public MipsTargetInfoBase {
6264 public:
6265   Mips32TargetInfoBase(const llvm::Triple &Triple)
6266       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
6267     SizeType = UnsignedInt;
6268     PtrDiffType = SignedInt;
6269     Int64Type = SignedLongLong;
6270     IntMaxType = Int64Type;
6271     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
6272   }
6273   bool setABI(const std::string &Name) override {
6274     if (Name == "o32" || Name == "eabi") {
6275       ABI = Name;
6276       return true;
6277     }
6278     return false;
6279   }
6280   void getTargetDefines(const LangOptions &Opts,
6281                         MacroBuilder &Builder) const override {
6282     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6283 
6284     Builder.defineMacro("__mips", "32");
6285     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
6286 
6287     const std::string& CPUStr = getCPU();
6288     if (CPUStr == "mips32")
6289       Builder.defineMacro("__mips_isa_rev", "1");
6290     else if (CPUStr == "mips32r2")
6291       Builder.defineMacro("__mips_isa_rev", "2");
6292     else if (CPUStr == "mips32r3")
6293       Builder.defineMacro("__mips_isa_rev", "3");
6294     else if (CPUStr == "mips32r5")
6295       Builder.defineMacro("__mips_isa_rev", "5");
6296     else if (CPUStr == "mips32r6")
6297       Builder.defineMacro("__mips_isa_rev", "6");
6298 
6299     if (ABI == "o32") {
6300       Builder.defineMacro("__mips_o32");
6301       Builder.defineMacro("_ABIO32", "1");
6302       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
6303     }
6304     else if (ABI == "eabi")
6305       Builder.defineMacro("__mips_eabi");
6306     else
6307       llvm_unreachable("Invalid ABI for Mips32.");
6308   }
6309   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6310                         unsigned &NumAliases) const override {
6311     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6312       { { "at" },  "$1" },
6313       { { "v0" },  "$2" },
6314       { { "v1" },  "$3" },
6315       { { "a0" },  "$4" },
6316       { { "a1" },  "$5" },
6317       { { "a2" },  "$6" },
6318       { { "a3" },  "$7" },
6319       { { "t0" },  "$8" },
6320       { { "t1" },  "$9" },
6321       { { "t2" }, "$10" },
6322       { { "t3" }, "$11" },
6323       { { "t4" }, "$12" },
6324       { { "t5" }, "$13" },
6325       { { "t6" }, "$14" },
6326       { { "t7" }, "$15" },
6327       { { "s0" }, "$16" },
6328       { { "s1" }, "$17" },
6329       { { "s2" }, "$18" },
6330       { { "s3" }, "$19" },
6331       { { "s4" }, "$20" },
6332       { { "s5" }, "$21" },
6333       { { "s6" }, "$22" },
6334       { { "s7" }, "$23" },
6335       { { "t8" }, "$24" },
6336       { { "t9" }, "$25" },
6337       { { "k0" }, "$26" },
6338       { { "k1" }, "$27" },
6339       { { "gp" }, "$28" },
6340       { { "sp","$sp" }, "$29" },
6341       { { "fp","$fp" }, "$30" },
6342       { { "ra" }, "$31" }
6343     };
6344     Aliases = GCCRegAliases;
6345     NumAliases = llvm::array_lengthof(GCCRegAliases);
6346   }
6347 };
6348 
6349 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
6350   void setDescriptionString() override {
6351     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6352   }
6353 
6354 public:
6355   Mips32EBTargetInfo(const llvm::Triple &Triple)
6356       : Mips32TargetInfoBase(Triple) {
6357   }
6358   void getTargetDefines(const LangOptions &Opts,
6359                         MacroBuilder &Builder) const override {
6360     DefineStd(Builder, "MIPSEB", Opts);
6361     Builder.defineMacro("_MIPSEB");
6362     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6363   }
6364 };
6365 
6366 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
6367   void setDescriptionString() override {
6368     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
6369   }
6370 
6371 public:
6372   Mips32ELTargetInfo(const llvm::Triple &Triple)
6373       : Mips32TargetInfoBase(Triple) {
6374     BigEndian = false;
6375   }
6376   void getTargetDefines(const LangOptions &Opts,
6377                         MacroBuilder &Builder) const override {
6378     DefineStd(Builder, "MIPSEL", Opts);
6379     Builder.defineMacro("_MIPSEL");
6380     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
6381   }
6382 };
6383 
6384 class Mips64TargetInfoBase : public MipsTargetInfoBase {
6385 public:
6386   Mips64TargetInfoBase(const llvm::Triple &Triple)
6387       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
6388     LongDoubleWidth = LongDoubleAlign = 128;
6389     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6390     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
6391       LongDoubleWidth = LongDoubleAlign = 64;
6392       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6393     }
6394     setN64ABITypes();
6395     SuitableAlign = 128;
6396     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6397   }
6398 
6399   void setN64ABITypes() {
6400     LongWidth = LongAlign = 64;
6401     PointerWidth = PointerAlign = 64;
6402     SizeType = UnsignedLong;
6403     PtrDiffType = SignedLong;
6404     Int64Type = SignedLong;
6405     IntMaxType = Int64Type;
6406   }
6407 
6408   void setN32ABITypes() {
6409     LongWidth = LongAlign = 32;
6410     PointerWidth = PointerAlign = 32;
6411     SizeType = UnsignedInt;
6412     PtrDiffType = SignedInt;
6413     Int64Type = SignedLongLong;
6414     IntMaxType = Int64Type;
6415   }
6416 
6417   bool setABI(const std::string &Name) override {
6418     if (Name == "n32") {
6419       setN32ABITypes();
6420       ABI = Name;
6421       return true;
6422     }
6423     if (Name == "n64") {
6424       setN64ABITypes();
6425       ABI = Name;
6426       return true;
6427     }
6428     return false;
6429   }
6430 
6431   void getTargetDefines(const LangOptions &Opts,
6432                         MacroBuilder &Builder) const override {
6433     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
6434 
6435     Builder.defineMacro("__mips", "64");
6436     Builder.defineMacro("__mips64");
6437     Builder.defineMacro("__mips64__");
6438     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
6439 
6440     const std::string& CPUStr = getCPU();
6441     if (CPUStr == "mips64")
6442       Builder.defineMacro("__mips_isa_rev", "1");
6443     else if (CPUStr == "mips64r2")
6444       Builder.defineMacro("__mips_isa_rev", "2");
6445     else if (CPUStr == "mips64r3")
6446       Builder.defineMacro("__mips_isa_rev", "3");
6447     else if (CPUStr == "mips64r5")
6448       Builder.defineMacro("__mips_isa_rev", "5");
6449     else if (CPUStr == "mips64r6")
6450       Builder.defineMacro("__mips_isa_rev", "6");
6451 
6452     if (ABI == "n32") {
6453       Builder.defineMacro("__mips_n32");
6454       Builder.defineMacro("_ABIN32", "2");
6455       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
6456     }
6457     else if (ABI == "n64") {
6458       Builder.defineMacro("__mips_n64");
6459       Builder.defineMacro("_ABI64", "3");
6460       Builder.defineMacro("_MIPS_SIM", "_ABI64");
6461     }
6462     else
6463       llvm_unreachable("Invalid ABI for Mips64.");
6464   }
6465   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6466                         unsigned &NumAliases) const override {
6467     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
6468       { { "at" },  "$1" },
6469       { { "v0" },  "$2" },
6470       { { "v1" },  "$3" },
6471       { { "a0" },  "$4" },
6472       { { "a1" },  "$5" },
6473       { { "a2" },  "$6" },
6474       { { "a3" },  "$7" },
6475       { { "a4" },  "$8" },
6476       { { "a5" },  "$9" },
6477       { { "a6" }, "$10" },
6478       { { "a7" }, "$11" },
6479       { { "t0" }, "$12" },
6480       { { "t1" }, "$13" },
6481       { { "t2" }, "$14" },
6482       { { "t3" }, "$15" },
6483       { { "s0" }, "$16" },
6484       { { "s1" }, "$17" },
6485       { { "s2" }, "$18" },
6486       { { "s3" }, "$19" },
6487       { { "s4" }, "$20" },
6488       { { "s5" }, "$21" },
6489       { { "s6" }, "$22" },
6490       { { "s7" }, "$23" },
6491       { { "t8" }, "$24" },
6492       { { "t9" }, "$25" },
6493       { { "k0" }, "$26" },
6494       { { "k1" }, "$27" },
6495       { { "gp" }, "$28" },
6496       { { "sp","$sp" }, "$29" },
6497       { { "fp","$fp" }, "$30" },
6498       { { "ra" }, "$31" }
6499     };
6500     Aliases = GCCRegAliases;
6501     NumAliases = llvm::array_lengthof(GCCRegAliases);
6502   }
6503 
6504   bool hasInt128Type() const override { return true; }
6505 };
6506 
6507 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
6508   void setDescriptionString() override {
6509     if (ABI == "n32")
6510       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6511     else
6512       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6513 
6514   }
6515 
6516 public:
6517   Mips64EBTargetInfo(const llvm::Triple &Triple)
6518       : Mips64TargetInfoBase(Triple) {}
6519   void getTargetDefines(const LangOptions &Opts,
6520                         MacroBuilder &Builder) const override {
6521     DefineStd(Builder, "MIPSEB", Opts);
6522     Builder.defineMacro("_MIPSEB");
6523     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6524   }
6525 };
6526 
6527 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
6528   void setDescriptionString() override {
6529     if (ABI == "n32")
6530       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6531     else
6532       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6533   }
6534 public:
6535   Mips64ELTargetInfo(const llvm::Triple &Triple)
6536       : Mips64TargetInfoBase(Triple) {
6537     // Default ABI is n64.
6538     BigEndian = false;
6539   }
6540   void getTargetDefines(const LangOptions &Opts,
6541                         MacroBuilder &Builder) const override {
6542     DefineStd(Builder, "MIPSEL", Opts);
6543     Builder.defineMacro("_MIPSEL");
6544     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6545   }
6546 };
6547 
6548 class PNaClTargetInfo : public TargetInfo {
6549 public:
6550   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6551     BigEndian = false;
6552     this->UserLabelPrefix = "";
6553     this->LongAlign = 32;
6554     this->LongWidth = 32;
6555     this->PointerAlign = 32;
6556     this->PointerWidth = 32;
6557     this->IntMaxType = TargetInfo::SignedLongLong;
6558     this->Int64Type = TargetInfo::SignedLongLong;
6559     this->DoubleAlign = 64;
6560     this->LongDoubleWidth = 64;
6561     this->LongDoubleAlign = 64;
6562     this->SizeType = TargetInfo::UnsignedInt;
6563     this->PtrDiffType = TargetInfo::SignedInt;
6564     this->IntPtrType = TargetInfo::SignedInt;
6565     this->RegParmMax = 0; // Disallow regparm
6566   }
6567 
6568   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6569   }
6570   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6571     Builder.defineMacro("__le32__");
6572     Builder.defineMacro("__pnacl__");
6573   }
6574   void getTargetDefines(const LangOptions &Opts,
6575                         MacroBuilder &Builder) const override {
6576     getArchDefines(Opts, Builder);
6577   }
6578   bool hasFeature(StringRef Feature) const override {
6579     return Feature == "pnacl";
6580   }
6581   void getTargetBuiltins(const Builtin::Info *&Records,
6582                          unsigned &NumRecords) const override {
6583   }
6584   BuiltinVaListKind getBuiltinVaListKind() const override {
6585     return TargetInfo::PNaClABIBuiltinVaList;
6586   }
6587   void getGCCRegNames(const char * const *&Names,
6588                       unsigned &NumNames) const override;
6589   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6590                         unsigned &NumAliases) const override;
6591   bool validateAsmConstraint(const char *&Name,
6592                              TargetInfo::ConstraintInfo &Info) const override {
6593     return false;
6594   }
6595 
6596   const char *getClobbers() const override {
6597     return "";
6598   }
6599 };
6600 
6601 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6602                                      unsigned &NumNames) const {
6603   Names = nullptr;
6604   NumNames = 0;
6605 }
6606 
6607 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6608                                        unsigned &NumAliases) const {
6609   Aliases = nullptr;
6610   NumAliases = 0;
6611 }
6612 
6613 class Le64TargetInfo : public TargetInfo {
6614   static const Builtin::Info BuiltinInfo[];
6615 
6616 public:
6617   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6618     BigEndian = false;
6619     NoAsmVariants = true;
6620     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6621     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6622     DescriptionString =
6623         "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128";
6624   }
6625 
6626   void getTargetDefines(const LangOptions &Opts,
6627                         MacroBuilder &Builder) const override {
6628     DefineStd(Builder, "unix", Opts);
6629     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6630     Builder.defineMacro("__ELF__");
6631   }
6632   void getTargetBuiltins(const Builtin::Info *&Records,
6633                          unsigned &NumRecords) const override {
6634     Records = BuiltinInfo;
6635     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6636   }
6637   BuiltinVaListKind getBuiltinVaListKind() const override {
6638     return TargetInfo::PNaClABIBuiltinVaList;
6639   }
6640   const char *getClobbers() const override { return ""; }
6641   void getGCCRegNames(const char *const *&Names,
6642                       unsigned &NumNames) const override {
6643     Names = nullptr;
6644     NumNames = 0;
6645   }
6646   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6647                         unsigned &NumAliases) const override {
6648     Aliases = nullptr;
6649     NumAliases = 0;
6650   }
6651   bool validateAsmConstraint(const char *&Name,
6652                              TargetInfo::ConstraintInfo &Info) const override {
6653     return false;
6654   }
6655 
6656   bool hasProtectedVisibility() const override { return false; }
6657 };
6658 } // end anonymous namespace.
6659 
6660 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6661 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6662   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6663 #include "clang/Basic/BuiltinsLe64.def"
6664 };
6665 
6666 namespace {
6667   static const unsigned SPIRAddrSpaceMap[] = {
6668     1,    // opencl_global
6669     3,    // opencl_local
6670     2,    // opencl_constant
6671     4,    // opencl_generic
6672     0,    // cuda_device
6673     0,    // cuda_constant
6674     0     // cuda_shared
6675   };
6676   class SPIRTargetInfo : public TargetInfo {
6677   public:
6678     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6679       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6680         "SPIR target must use unknown OS");
6681       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6682         "SPIR target must use unknown environment type");
6683       BigEndian = false;
6684       TLSSupported = false;
6685       LongWidth = LongAlign = 64;
6686       AddrSpaceMap = &SPIRAddrSpaceMap;
6687       UseAddrSpaceMapMangling = true;
6688       // Define available target features
6689       // These must be defined in sorted order!
6690       NoAsmVariants = true;
6691     }
6692     void getTargetDefines(const LangOptions &Opts,
6693                           MacroBuilder &Builder) const override {
6694       DefineStd(Builder, "SPIR", Opts);
6695     }
6696     bool hasFeature(StringRef Feature) const override {
6697       return Feature == "spir";
6698     }
6699 
6700     void getTargetBuiltins(const Builtin::Info *&Records,
6701                            unsigned &NumRecords) const override {}
6702     const char *getClobbers() const override {
6703       return "";
6704     }
6705     void getGCCRegNames(const char * const *&Names,
6706                         unsigned &NumNames) const override {}
6707     bool
6708     validateAsmConstraint(const char *&Name,
6709                           TargetInfo::ConstraintInfo &info) const override {
6710       return true;
6711     }
6712     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6713                           unsigned &NumAliases) const override {}
6714     BuiltinVaListKind getBuiltinVaListKind() const override {
6715       return TargetInfo::VoidPtrBuiltinVaList;
6716     }
6717 
6718     CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
6719       return (CC == CC_SpirFunction ||
6720               CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning;
6721     }
6722 
6723     CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
6724       return CC_SpirFunction;
6725     }
6726   };
6727 
6728 
6729   class SPIR32TargetInfo : public SPIRTargetInfo {
6730   public:
6731     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6732       PointerWidth = PointerAlign = 32;
6733       SizeType     = TargetInfo::UnsignedInt;
6734       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6735       DescriptionString
6736         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6737           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6738     }
6739     void getTargetDefines(const LangOptions &Opts,
6740                           MacroBuilder &Builder) const override {
6741       DefineStd(Builder, "SPIR32", Opts);
6742     }
6743   };
6744 
6745   class SPIR64TargetInfo : public SPIRTargetInfo {
6746   public:
6747     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6748       PointerWidth = PointerAlign = 64;
6749       SizeType     = TargetInfo::UnsignedLong;
6750       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6751       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6752                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6753     }
6754     void getTargetDefines(const LangOptions &Opts,
6755                           MacroBuilder &Builder) const override {
6756       DefineStd(Builder, "SPIR64", Opts);
6757     }
6758   };
6759 
6760 class XCoreTargetInfo : public TargetInfo {
6761   static const Builtin::Info BuiltinInfo[];
6762 public:
6763   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6764     BigEndian = false;
6765     NoAsmVariants = true;
6766     LongLongAlign = 32;
6767     SuitableAlign = 32;
6768     DoubleAlign = LongDoubleAlign = 32;
6769     SizeType = UnsignedInt;
6770     PtrDiffType = SignedInt;
6771     IntPtrType = SignedInt;
6772     WCharType = UnsignedChar;
6773     WIntType = UnsignedInt;
6774     UseZeroLengthBitfieldAlignment = true;
6775     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6776                         "-f64:32-a:0:32-n32";
6777   }
6778   void getTargetDefines(const LangOptions &Opts,
6779                         MacroBuilder &Builder) const override {
6780     Builder.defineMacro("__XS1B__");
6781   }
6782   void getTargetBuiltins(const Builtin::Info *&Records,
6783                          unsigned &NumRecords) const override {
6784     Records = BuiltinInfo;
6785     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6786   }
6787   BuiltinVaListKind getBuiltinVaListKind() const override {
6788     return TargetInfo::VoidPtrBuiltinVaList;
6789   }
6790   const char *getClobbers() const override {
6791     return "";
6792   }
6793   void getGCCRegNames(const char * const *&Names,
6794                       unsigned &NumNames) const override {
6795     static const char * const GCCRegNames[] = {
6796       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6797       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6798     };
6799     Names = GCCRegNames;
6800     NumNames = llvm::array_lengthof(GCCRegNames);
6801   }
6802   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6803                         unsigned &NumAliases) const override {
6804     Aliases = nullptr;
6805     NumAliases = 0;
6806   }
6807   bool validateAsmConstraint(const char *&Name,
6808                              TargetInfo::ConstraintInfo &Info) const override {
6809     return false;
6810   }
6811   int getEHDataRegisterNumber(unsigned RegNo) const override {
6812     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6813     return (RegNo < 2)? RegNo : -1;
6814   }
6815 };
6816 
6817 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6818 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6819 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6820                                               ALL_LANGUAGES },
6821 #include "clang/Basic/BuiltinsXCore.def"
6822 };
6823 } // end anonymous namespace.
6824 
6825 namespace {
6826 // x86_32 Android target
6827 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> {
6828 public:
6829   AndroidX86_32TargetInfo(const llvm::Triple &Triple)
6830       : LinuxTargetInfo<X86_32TargetInfo>(Triple) {
6831     SuitableAlign = 32;
6832     LongDoubleWidth = 64;
6833     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
6834   }
6835 };
6836 } // end anonymous namespace
6837 
6838 namespace {
6839 // x86_64 Android target
6840 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> {
6841 public:
6842   AndroidX86_64TargetInfo(const llvm::Triple &Triple)
6843       : LinuxTargetInfo<X86_64TargetInfo>(Triple) {
6844     LongDoubleFormat = &llvm::APFloat::IEEEquad;
6845   }
6846 };
6847 } // end anonymous namespace
6848 
6849 
6850 //===----------------------------------------------------------------------===//
6851 // Driver code
6852 //===----------------------------------------------------------------------===//
6853 
6854 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6855   llvm::Triple::OSType os = Triple.getOS();
6856 
6857   switch (Triple.getArch()) {
6858   default:
6859     return nullptr;
6860 
6861   case llvm::Triple::xcore:
6862     return new XCoreTargetInfo(Triple);
6863 
6864   case llvm::Triple::hexagon:
6865     return new HexagonTargetInfo(Triple);
6866 
6867   case llvm::Triple::aarch64:
6868     if (Triple.isOSDarwin())
6869       return new DarwinAArch64TargetInfo(Triple);
6870 
6871     switch (os) {
6872     case llvm::Triple::FreeBSD:
6873       return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple);
6874     case llvm::Triple::Linux:
6875       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6876     case llvm::Triple::NetBSD:
6877       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6878     default:
6879       return new AArch64leTargetInfo(Triple);
6880     }
6881 
6882   case llvm::Triple::aarch64_be:
6883     switch (os) {
6884     case llvm::Triple::FreeBSD:
6885       return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple);
6886     case llvm::Triple::Linux:
6887       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6888     case llvm::Triple::NetBSD:
6889       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6890     default:
6891       return new AArch64beTargetInfo(Triple);
6892     }
6893 
6894   case llvm::Triple::arm:
6895   case llvm::Triple::thumb:
6896     if (Triple.isOSBinFormatMachO())
6897       return new DarwinARMTargetInfo(Triple);
6898 
6899     switch (os) {
6900     case llvm::Triple::Linux:
6901       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6902     case llvm::Triple::FreeBSD:
6903       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6904     case llvm::Triple::NetBSD:
6905       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6906     case llvm::Triple::OpenBSD:
6907       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6908     case llvm::Triple::Bitrig:
6909       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6910     case llvm::Triple::RTEMS:
6911       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6912     case llvm::Triple::NaCl:
6913       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6914     case llvm::Triple::Win32:
6915       switch (Triple.getEnvironment()) {
6916       default:
6917         return new ARMleTargetInfo(Triple);
6918       case llvm::Triple::Itanium:
6919         return new ItaniumWindowsARMleTargetInfo(Triple);
6920       case llvm::Triple::MSVC:
6921         return new MicrosoftARMleTargetInfo(Triple);
6922       }
6923     default:
6924       return new ARMleTargetInfo(Triple);
6925     }
6926 
6927   case llvm::Triple::armeb:
6928   case llvm::Triple::thumbeb:
6929     if (Triple.isOSDarwin())
6930       return new DarwinARMTargetInfo(Triple);
6931 
6932     switch (os) {
6933     case llvm::Triple::Linux:
6934       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6935     case llvm::Triple::FreeBSD:
6936       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6937     case llvm::Triple::NetBSD:
6938       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6939     case llvm::Triple::OpenBSD:
6940       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6941     case llvm::Triple::Bitrig:
6942       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6943     case llvm::Triple::RTEMS:
6944       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6945     case llvm::Triple::NaCl:
6946       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6947     default:
6948       return new ARMbeTargetInfo(Triple);
6949     }
6950 
6951   case llvm::Triple::bpfeb:
6952   case llvm::Triple::bpfel:
6953     return new BPFTargetInfo(Triple);
6954 
6955   case llvm::Triple::msp430:
6956     return new MSP430TargetInfo(Triple);
6957 
6958   case llvm::Triple::mips:
6959     switch (os) {
6960     case llvm::Triple::Linux:
6961       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6962     case llvm::Triple::RTEMS:
6963       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6964     case llvm::Triple::FreeBSD:
6965       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6966     case llvm::Triple::NetBSD:
6967       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6968     default:
6969       return new Mips32EBTargetInfo(Triple);
6970     }
6971 
6972   case llvm::Triple::mipsel:
6973     switch (os) {
6974     case llvm::Triple::Linux:
6975       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6976     case llvm::Triple::RTEMS:
6977       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6978     case llvm::Triple::FreeBSD:
6979       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6980     case llvm::Triple::NetBSD:
6981       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6982     case llvm::Triple::NaCl:
6983       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6984     default:
6985       return new Mips32ELTargetInfo(Triple);
6986     }
6987 
6988   case llvm::Triple::mips64:
6989     switch (os) {
6990     case llvm::Triple::Linux:
6991       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6992     case llvm::Triple::RTEMS:
6993       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6994     case llvm::Triple::FreeBSD:
6995       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6996     case llvm::Triple::NetBSD:
6997       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6998     case llvm::Triple::OpenBSD:
6999       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
7000     default:
7001       return new Mips64EBTargetInfo(Triple);
7002     }
7003 
7004   case llvm::Triple::mips64el:
7005     switch (os) {
7006     case llvm::Triple::Linux:
7007       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
7008     case llvm::Triple::RTEMS:
7009       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
7010     case llvm::Triple::FreeBSD:
7011       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7012     case llvm::Triple::NetBSD:
7013       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7014     case llvm::Triple::OpenBSD:
7015       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
7016     default:
7017       return new Mips64ELTargetInfo(Triple);
7018     }
7019 
7020   case llvm::Triple::le32:
7021     switch (os) {
7022     case llvm::Triple::NaCl:
7023       return new NaClTargetInfo<PNaClTargetInfo>(Triple);
7024     default:
7025       return nullptr;
7026     }
7027 
7028   case llvm::Triple::le64:
7029     return new Le64TargetInfo(Triple);
7030 
7031   case llvm::Triple::ppc:
7032     if (Triple.isOSDarwin())
7033       return new DarwinPPC32TargetInfo(Triple);
7034     switch (os) {
7035     case llvm::Triple::Linux:
7036       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
7037     case llvm::Triple::FreeBSD:
7038       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
7039     case llvm::Triple::NetBSD:
7040       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
7041     case llvm::Triple::OpenBSD:
7042       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
7043     case llvm::Triple::RTEMS:
7044       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
7045     default:
7046       return new PPC32TargetInfo(Triple);
7047     }
7048 
7049   case llvm::Triple::ppc64:
7050     if (Triple.isOSDarwin())
7051       return new DarwinPPC64TargetInfo(Triple);
7052     switch (os) {
7053     case llvm::Triple::Linux:
7054       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7055     case llvm::Triple::Lv2:
7056       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
7057     case llvm::Triple::FreeBSD:
7058       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
7059     case llvm::Triple::NetBSD:
7060       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7061     default:
7062       return new PPC64TargetInfo(Triple);
7063     }
7064 
7065   case llvm::Triple::ppc64le:
7066     switch (os) {
7067     case llvm::Triple::Linux:
7068       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
7069     case llvm::Triple::NetBSD:
7070       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
7071     default:
7072       return new PPC64TargetInfo(Triple);
7073     }
7074 
7075   case llvm::Triple::nvptx:
7076     return new NVPTX32TargetInfo(Triple);
7077   case llvm::Triple::nvptx64:
7078     return new NVPTX64TargetInfo(Triple);
7079 
7080   case llvm::Triple::amdgcn:
7081   case llvm::Triple::r600:
7082     return new R600TargetInfo(Triple);
7083 
7084   case llvm::Triple::sparc:
7085     switch (os) {
7086     case llvm::Triple::Linux:
7087       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
7088     case llvm::Triple::Solaris:
7089       return new SolarisTargetInfo<SparcV8TargetInfo>(Triple);
7090     case llvm::Triple::NetBSD:
7091       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
7092     case llvm::Triple::OpenBSD:
7093       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
7094     case llvm::Triple::RTEMS:
7095       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
7096     default:
7097       return new SparcV8TargetInfo(Triple);
7098     }
7099 
7100   // The 'sparcel' architecture copies all the above cases except for Solaris.
7101   case llvm::Triple::sparcel:
7102     switch (os) {
7103     case llvm::Triple::Linux:
7104       return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple);
7105     case llvm::Triple::NetBSD:
7106       return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7107     case llvm::Triple::OpenBSD:
7108       return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple);
7109     case llvm::Triple::RTEMS:
7110       return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple);
7111     default:
7112       return new SparcV8elTargetInfo(Triple);
7113     }
7114 
7115   case llvm::Triple::sparcv9:
7116     switch (os) {
7117     case llvm::Triple::Linux:
7118       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
7119     case llvm::Triple::Solaris:
7120       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
7121     case llvm::Triple::NetBSD:
7122       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
7123     case llvm::Triple::OpenBSD:
7124       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
7125     case llvm::Triple::FreeBSD:
7126       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
7127     default:
7128       return new SparcV9TargetInfo(Triple);
7129     }
7130 
7131   case llvm::Triple::systemz:
7132     switch (os) {
7133     case llvm::Triple::Linux:
7134       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
7135     default:
7136       return new SystemZTargetInfo(Triple);
7137     }
7138 
7139   case llvm::Triple::tce:
7140     return new TCETargetInfo(Triple);
7141 
7142   case llvm::Triple::x86:
7143     if (Triple.isOSDarwin())
7144       return new DarwinI386TargetInfo(Triple);
7145 
7146     switch (os) {
7147     case llvm::Triple::Linux: {
7148       switch (Triple.getEnvironment()) {
7149       default:
7150         return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
7151       case llvm::Triple::Android:
7152         return new AndroidX86_32TargetInfo(Triple);
7153       }
7154     }
7155     case llvm::Triple::DragonFly:
7156       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
7157     case llvm::Triple::NetBSD:
7158       return new NetBSDI386TargetInfo(Triple);
7159     case llvm::Triple::OpenBSD:
7160       return new OpenBSDI386TargetInfo(Triple);
7161     case llvm::Triple::Bitrig:
7162       return new BitrigI386TargetInfo(Triple);
7163     case llvm::Triple::FreeBSD:
7164       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7165     case llvm::Triple::KFreeBSD:
7166       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
7167     case llvm::Triple::Minix:
7168       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
7169     case llvm::Triple::Solaris:
7170       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
7171     case llvm::Triple::Win32: {
7172       switch (Triple.getEnvironment()) {
7173       default:
7174         return new X86_32TargetInfo(Triple);
7175       case llvm::Triple::Cygnus:
7176         return new CygwinX86_32TargetInfo(Triple);
7177       case llvm::Triple::GNU:
7178         return new MinGWX86_32TargetInfo(Triple);
7179       case llvm::Triple::Itanium:
7180       case llvm::Triple::MSVC:
7181         return new MicrosoftX86_32TargetInfo(Triple);
7182       }
7183     }
7184     case llvm::Triple::Haiku:
7185       return new HaikuX86_32TargetInfo(Triple);
7186     case llvm::Triple::RTEMS:
7187       return new RTEMSX86_32TargetInfo(Triple);
7188     case llvm::Triple::NaCl:
7189       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
7190     default:
7191       return new X86_32TargetInfo(Triple);
7192     }
7193 
7194   case llvm::Triple::x86_64:
7195     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
7196       return new DarwinX86_64TargetInfo(Triple);
7197 
7198     switch (os) {
7199     case llvm::Triple::CloudABI:
7200       return new CloudABITargetInfo<X86_64TargetInfo>(Triple);
7201     case llvm::Triple::Linux: {
7202       switch (Triple.getEnvironment()) {
7203       default:
7204         return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
7205       case llvm::Triple::Android:
7206         return new AndroidX86_64TargetInfo(Triple);
7207       }
7208     }
7209     case llvm::Triple::DragonFly:
7210       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
7211     case llvm::Triple::NetBSD:
7212       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
7213     case llvm::Triple::OpenBSD:
7214       return new OpenBSDX86_64TargetInfo(Triple);
7215     case llvm::Triple::Bitrig:
7216       return new BitrigX86_64TargetInfo(Triple);
7217     case llvm::Triple::FreeBSD:
7218       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7219     case llvm::Triple::KFreeBSD:
7220       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
7221     case llvm::Triple::Solaris:
7222       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
7223     case llvm::Triple::Win32: {
7224       switch (Triple.getEnvironment()) {
7225       default:
7226         return new X86_64TargetInfo(Triple);
7227       case llvm::Triple::GNU:
7228         return new MinGWX86_64TargetInfo(Triple);
7229       case llvm::Triple::MSVC:
7230         return new MicrosoftX86_64TargetInfo(Triple);
7231       }
7232     }
7233     case llvm::Triple::NaCl:
7234       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
7235     case llvm::Triple::PS4:
7236       return new PS4OSTargetInfo<X86_64TargetInfo>(Triple);
7237     default:
7238       return new X86_64TargetInfo(Triple);
7239     }
7240 
7241   case llvm::Triple::spir: {
7242     if (Triple.getOS() != llvm::Triple::UnknownOS ||
7243         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7244       return nullptr;
7245     return new SPIR32TargetInfo(Triple);
7246   }
7247   case llvm::Triple::spir64: {
7248     if (Triple.getOS() != llvm::Triple::UnknownOS ||
7249         Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
7250       return nullptr;
7251     return new SPIR64TargetInfo(Triple);
7252   }
7253   }
7254 }
7255 
7256 /// CreateTargetInfo - Return the target info object for the specified target
7257 /// triple.
7258 TargetInfo *
7259 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
7260                              const std::shared_ptr<TargetOptions> &Opts) {
7261   llvm::Triple Triple(Opts->Triple);
7262 
7263   // Construct the target
7264   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
7265   if (!Target) {
7266     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
7267     return nullptr;
7268   }
7269   Target->TargetOpts = Opts;
7270 
7271   // Set the target CPU if specified.
7272   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
7273     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
7274     return nullptr;
7275   }
7276 
7277   // Set the target ABI if specified.
7278   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
7279     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
7280     return nullptr;
7281   }
7282 
7283   // Set the fp math unit.
7284   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
7285     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
7286     return nullptr;
7287   }
7288 
7289   // Compute the default target features, we need the target to handle this
7290   // because features may have dependencies on one another.
7291   llvm::StringMap<bool> Features;
7292   Target->getDefaultFeatures(Features);
7293 
7294   // Apply the user specified deltas.
7295   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
7296        I < N; ++I) {
7297     const char *Name = Opts->FeaturesAsWritten[I].c_str();
7298     // Apply the feature via the target.
7299     bool Enabled = Name[0] == '+';
7300     Target->setFeatureEnabled(Features, Name + 1, Enabled);
7301   }
7302 
7303   // Add the features to the compile options.
7304   //
7305   // FIXME: If we are completely confident that we have the right set, we only
7306   // need to pass the minuses.
7307   Opts->Features.clear();
7308   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
7309          ie = Features.end(); it != ie; ++it)
7310     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
7311   if (!Target->handleTargetFeatures(Opts->Features, Diags))
7312     return nullptr;
7313 
7314   return Target.release();
7315 }
7316