1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 // Ananas target 115 template<typename Target> 116 class AnanasTargetInfo : public OSTargetInfo<Target> { 117 protected: 118 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 119 MacroBuilder &Builder) const override { 120 // Ananas defines 121 Builder.defineMacro("__Ananas__"); 122 Builder.defineMacro("__ELF__"); 123 } 124 public: 125 AnanasTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 126 : OSTargetInfo<Target>(Triple, Opts) {} 127 }; 128 129 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 130 const llvm::Triple &Triple, 131 StringRef &PlatformName, 132 VersionTuple &PlatformMinVersion) { 133 Builder.defineMacro("__APPLE_CC__", "6000"); 134 Builder.defineMacro("__APPLE__"); 135 Builder.defineMacro("__STDC_NO_THREADS__"); 136 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 137 // AddressSanitizer doesn't play well with source fortification, which is on 138 // by default on Darwin. 139 if (Opts.Sanitize.has(SanitizerKind::Address)) 140 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 141 142 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 143 if (!Opts.ObjC1) { 144 // __weak is always defined, for use in blocks and with objc pointers. 145 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 146 Builder.defineMacro("__strong", ""); 147 Builder.defineMacro("__unsafe_unretained", ""); 148 } 149 150 if (Opts.Static) 151 Builder.defineMacro("__STATIC__"); 152 else 153 Builder.defineMacro("__DYNAMIC__"); 154 155 if (Opts.POSIXThreads) 156 Builder.defineMacro("_REENTRANT"); 157 158 // Get the platform type and version number from the triple. 159 unsigned Maj, Min, Rev; 160 if (Triple.isMacOSX()) { 161 Triple.getMacOSXVersion(Maj, Min, Rev); 162 PlatformName = "macos"; 163 } else { 164 Triple.getOSVersion(Maj, Min, Rev); 165 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 166 } 167 168 // If -target arch-pc-win32-macho option specified, we're 169 // generating code for Win32 ABI. No need to emit 170 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 171 if (PlatformName == "win32") { 172 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 173 return; 174 } 175 176 // Set the appropriate OS version define. 177 if (Triple.isiOS()) { 178 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 179 char Str[7]; 180 if (Maj < 10) { 181 Str[0] = '0' + Maj; 182 Str[1] = '0' + (Min / 10); 183 Str[2] = '0' + (Min % 10); 184 Str[3] = '0' + (Rev / 10); 185 Str[4] = '0' + (Rev % 10); 186 Str[5] = '\0'; 187 } else { 188 // Handle versions >= 10. 189 Str[0] = '0' + (Maj / 10); 190 Str[1] = '0' + (Maj % 10); 191 Str[2] = '0' + (Min / 10); 192 Str[3] = '0' + (Min % 10); 193 Str[4] = '0' + (Rev / 10); 194 Str[5] = '0' + (Rev % 10); 195 Str[6] = '\0'; 196 } 197 if (Triple.isTvOS()) 198 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 199 else 200 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 201 Str); 202 203 } else if (Triple.isWatchOS()) { 204 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 205 char Str[6]; 206 Str[0] = '0' + Maj; 207 Str[1] = '0' + (Min / 10); 208 Str[2] = '0' + (Min % 10); 209 Str[3] = '0' + (Rev / 10); 210 Str[4] = '0' + (Rev % 10); 211 Str[5] = '\0'; 212 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 213 } else if (Triple.isMacOSX()) { 214 // Note that the Driver allows versions which aren't representable in the 215 // define (because we only get a single digit for the minor and micro 216 // revision numbers). So, we limit them to the maximum representable 217 // version. 218 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 219 char Str[7]; 220 if (Maj < 10 || (Maj == 10 && Min < 10)) { 221 Str[0] = '0' + (Maj / 10); 222 Str[1] = '0' + (Maj % 10); 223 Str[2] = '0' + std::min(Min, 9U); 224 Str[3] = '0' + std::min(Rev, 9U); 225 Str[4] = '\0'; 226 } else { 227 // Handle versions > 10.9. 228 Str[0] = '0' + (Maj / 10); 229 Str[1] = '0' + (Maj % 10); 230 Str[2] = '0' + (Min / 10); 231 Str[3] = '0' + (Min % 10); 232 Str[4] = '0' + (Rev / 10); 233 Str[5] = '0' + (Rev % 10); 234 Str[6] = '\0'; 235 } 236 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 237 } 238 239 // Tell users about the kernel if there is one. 240 if (Triple.isOSDarwin()) 241 Builder.defineMacro("__MACH__"); 242 243 // The Watch ABI uses Dwarf EH. 244 if(Triple.isWatchABI()) 245 Builder.defineMacro("__ARM_DWARF_EH__"); 246 247 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 248 } 249 250 template<typename Target> 251 class DarwinTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 256 this->PlatformMinVersion); 257 } 258 259 public: 260 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 261 : OSTargetInfo<Target>(Triple, Opts) { 262 // By default, no TLS, and we whitelist permitted architecture/OS 263 // combinations. 264 this->TLSSupported = false; 265 266 if (Triple.isMacOSX()) 267 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 268 else if (Triple.isiOS()) { 269 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 270 if (Triple.getArch() == llvm::Triple::x86_64 || 271 Triple.getArch() == llvm::Triple::aarch64) 272 this->TLSSupported = !Triple.isOSVersionLT(8); 273 else if (Triple.getArch() == llvm::Triple::x86 || 274 Triple.getArch() == llvm::Triple::arm || 275 Triple.getArch() == llvm::Triple::thumb) 276 this->TLSSupported = !Triple.isOSVersionLT(9); 277 } else if (Triple.isWatchOS()) 278 this->TLSSupported = !Triple.isOSVersionLT(2); 279 280 this->MCountName = "\01mcount"; 281 } 282 283 std::string isValidSectionSpecifier(StringRef SR) const override { 284 // Let MCSectionMachO validate this. 285 StringRef Segment, Section; 286 unsigned TAA, StubSize; 287 bool HasTAA; 288 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 289 TAA, HasTAA, StubSize); 290 } 291 292 const char *getStaticInitSectionSpecifier() const override { 293 // FIXME: We should return 0 when building kexts. 294 return "__TEXT,__StaticInit,regular,pure_instructions"; 295 } 296 297 /// Darwin does not support protected visibility. Darwin's "default" 298 /// is very similar to ELF's "protected"; Darwin requires a "weak" 299 /// attribute on declarations that can be dynamically replaced. 300 bool hasProtectedVisibility() const override { 301 return false; 302 } 303 304 unsigned getExnObjectAlignment() const override { 305 // The alignment of an exception object is 8-bytes for darwin since 306 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 307 // and therefore doesn't guarantee 16-byte alignment. 308 return 64; 309 } 310 }; 311 312 313 // DragonFlyBSD Target 314 template<typename Target> 315 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 316 protected: 317 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 318 MacroBuilder &Builder) const override { 319 // DragonFly defines; list based off of gcc output 320 Builder.defineMacro("__DragonFly__"); 321 Builder.defineMacro("__DragonFly_cc_version", "100001"); 322 Builder.defineMacro("__ELF__"); 323 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 324 Builder.defineMacro("__tune_i386__"); 325 DefineStd(Builder, "unix", Opts); 326 } 327 public: 328 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 329 : OSTargetInfo<Target>(Triple, Opts) { 330 switch (Triple.getArch()) { 331 default: 332 case llvm::Triple::x86: 333 case llvm::Triple::x86_64: 334 this->MCountName = ".mcount"; 335 break; 336 } 337 } 338 }; 339 340 #ifndef FREEBSD_CC_VERSION 341 #define FREEBSD_CC_VERSION 0U 342 #endif 343 344 // FreeBSD Target 345 template<typename Target> 346 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 347 protected: 348 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 349 MacroBuilder &Builder) const override { 350 // FreeBSD defines; list based off of gcc output 351 352 unsigned Release = Triple.getOSMajorVersion(); 353 if (Release == 0U) 354 Release = 8U; 355 unsigned CCVersion = FREEBSD_CC_VERSION; 356 if (CCVersion == 0U) 357 CCVersion = Release * 100000U + 1U; 358 359 Builder.defineMacro("__FreeBSD__", Twine(Release)); 360 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 361 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 362 DefineStd(Builder, "unix", Opts); 363 Builder.defineMacro("__ELF__"); 364 365 // On FreeBSD, wchar_t contains the number of the code point as 366 // used by the character set of the locale. These character sets are 367 // not necessarily a superset of ASCII. 368 // 369 // FIXME: This is wrong; the macro refers to the numerical values 370 // of wchar_t *literals*, which are not locale-dependent. However, 371 // FreeBSD systems apparently depend on us getting this wrong, and 372 // setting this to 1 is conforming even if all the basic source 373 // character literals have the same encoding as char and wchar_t. 374 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 375 } 376 public: 377 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 378 : OSTargetInfo<Target>(Triple, Opts) { 379 switch (Triple.getArch()) { 380 default: 381 case llvm::Triple::x86: 382 case llvm::Triple::x86_64: 383 this->MCountName = ".mcount"; 384 break; 385 case llvm::Triple::mips: 386 case llvm::Triple::mipsel: 387 case llvm::Triple::ppc: 388 case llvm::Triple::ppc64: 389 case llvm::Triple::ppc64le: 390 this->MCountName = "_mcount"; 391 break; 392 case llvm::Triple::arm: 393 this->MCountName = "__mcount"; 394 break; 395 } 396 } 397 }; 398 399 // GNU/kFreeBSD Target 400 template<typename Target> 401 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 402 protected: 403 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 404 MacroBuilder &Builder) const override { 405 // GNU/kFreeBSD defines; list based off of gcc output 406 407 DefineStd(Builder, "unix", Opts); 408 Builder.defineMacro("__FreeBSD_kernel__"); 409 Builder.defineMacro("__GLIBC__"); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 if (Opts.CPlusPlus) 414 Builder.defineMacro("_GNU_SOURCE"); 415 } 416 public: 417 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) {} 419 }; 420 421 // Haiku Target 422 template<typename Target> 423 class HaikuTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Haiku defines; list based off of gcc output 428 Builder.defineMacro("__HAIKU__"); 429 Builder.defineMacro("__ELF__"); 430 DefineStd(Builder, "unix", Opts); 431 } 432 public: 433 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 434 : OSTargetInfo<Target>(Triple, Opts) { 435 this->SizeType = TargetInfo::UnsignedLong; 436 this->IntPtrType = TargetInfo::SignedLong; 437 this->PtrDiffType = TargetInfo::SignedLong; 438 this->ProcessIDType = TargetInfo::SignedLong; 439 this->TLSSupported = false; 440 441 } 442 }; 443 444 // Minix Target 445 template<typename Target> 446 class MinixTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // Minix defines 451 452 Builder.defineMacro("__minix", "3"); 453 Builder.defineMacro("_EM_WSIZE", "4"); 454 Builder.defineMacro("_EM_PSIZE", "4"); 455 Builder.defineMacro("_EM_SSIZE", "2"); 456 Builder.defineMacro("_EM_LSIZE", "4"); 457 Builder.defineMacro("_EM_FSIZE", "4"); 458 Builder.defineMacro("_EM_DSIZE", "8"); 459 Builder.defineMacro("__ELF__"); 460 DefineStd(Builder, "unix", Opts); 461 } 462 public: 463 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 464 : OSTargetInfo<Target>(Triple, Opts) {} 465 }; 466 467 // Linux target 468 template<typename Target> 469 class LinuxTargetInfo : public OSTargetInfo<Target> { 470 protected: 471 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 472 MacroBuilder &Builder) const override { 473 // Linux defines; list based off of gcc output 474 DefineStd(Builder, "unix", Opts); 475 DefineStd(Builder, "linux", Opts); 476 Builder.defineMacro("__gnu_linux__"); 477 Builder.defineMacro("__ELF__"); 478 if (Triple.isAndroid()) { 479 Builder.defineMacro("__ANDROID__", "1"); 480 unsigned Maj, Min, Rev; 481 Triple.getEnvironmentVersion(Maj, Min, Rev); 482 this->PlatformName = "android"; 483 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 484 if (Maj) 485 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 486 } 487 if (Opts.POSIXThreads) 488 Builder.defineMacro("_REENTRANT"); 489 if (Opts.CPlusPlus) 490 Builder.defineMacro("_GNU_SOURCE"); 491 if (this->HasFloat128) 492 Builder.defineMacro("__FLOAT128__"); 493 } 494 public: 495 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 496 : OSTargetInfo<Target>(Triple, Opts) { 497 this->WIntType = TargetInfo::UnsignedInt; 498 499 switch (Triple.getArch()) { 500 default: 501 break; 502 case llvm::Triple::mips: 503 case llvm::Triple::mipsel: 504 case llvm::Triple::mips64: 505 case llvm::Triple::mips64el: 506 case llvm::Triple::ppc: 507 case llvm::Triple::ppc64: 508 case llvm::Triple::ppc64le: 509 this->MCountName = "_mcount"; 510 break; 511 case llvm::Triple::x86: 512 case llvm::Triple::x86_64: 513 case llvm::Triple::systemz: 514 this->HasFloat128 = true; 515 break; 516 } 517 } 518 519 const char *getStaticInitSectionSpecifier() const override { 520 return ".text.startup"; 521 } 522 }; 523 524 // NetBSD Target 525 template<typename Target> 526 class NetBSDTargetInfo : public OSTargetInfo<Target> { 527 protected: 528 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 529 MacroBuilder &Builder) const override { 530 // NetBSD defines; list based off of gcc output 531 Builder.defineMacro("__NetBSD__"); 532 Builder.defineMacro("__unix__"); 533 Builder.defineMacro("__ELF__"); 534 if (Opts.POSIXThreads) 535 Builder.defineMacro("_REENTRANT"); 536 537 switch (Triple.getArch()) { 538 default: 539 break; 540 case llvm::Triple::arm: 541 case llvm::Triple::armeb: 542 case llvm::Triple::thumb: 543 case llvm::Triple::thumbeb: 544 Builder.defineMacro("__ARM_DWARF_EH__"); 545 break; 546 } 547 } 548 public: 549 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 550 : OSTargetInfo<Target>(Triple, Opts) { 551 this->MCountName = "_mcount"; 552 } 553 }; 554 555 // OpenBSD Target 556 template<typename Target> 557 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 558 protected: 559 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 560 MacroBuilder &Builder) const override { 561 // OpenBSD defines; list based off of gcc output 562 563 Builder.defineMacro("__OpenBSD__"); 564 DefineStd(Builder, "unix", Opts); 565 Builder.defineMacro("__ELF__"); 566 if (Opts.POSIXThreads) 567 Builder.defineMacro("_REENTRANT"); 568 if (this->HasFloat128) 569 Builder.defineMacro("__FLOAT128__"); 570 } 571 public: 572 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 573 : OSTargetInfo<Target>(Triple, Opts) { 574 switch (Triple.getArch()) { 575 case llvm::Triple::x86: 576 case llvm::Triple::x86_64: 577 this->HasFloat128 = true; 578 // FALLTHROUGH 579 default: 580 this->MCountName = "__mcount"; 581 break; 582 case llvm::Triple::mips64: 583 case llvm::Triple::mips64el: 584 case llvm::Triple::ppc: 585 case llvm::Triple::sparcv9: 586 this->MCountName = "_mcount"; 587 break; 588 } 589 } 590 }; 591 592 // Bitrig Target 593 template<typename Target> 594 class BitrigTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const override { 598 // Bitrig defines; list based off of gcc output 599 600 Builder.defineMacro("__Bitrig__"); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 if (Opts.POSIXThreads) 604 Builder.defineMacro("_REENTRANT"); 605 606 switch (Triple.getArch()) { 607 default: 608 break; 609 case llvm::Triple::arm: 610 case llvm::Triple::armeb: 611 case llvm::Triple::thumb: 612 case llvm::Triple::thumbeb: 613 Builder.defineMacro("__ARM_DWARF_EH__"); 614 break; 615 } 616 } 617 public: 618 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 619 : OSTargetInfo<Target>(Triple, Opts) { 620 this->MCountName = "__mcount"; 621 } 622 }; 623 624 // PSP Target 625 template<typename Target> 626 class PSPTargetInfo : public OSTargetInfo<Target> { 627 protected: 628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 629 MacroBuilder &Builder) const override { 630 // PSP defines; list based on the output of the pspdev gcc toolchain. 631 Builder.defineMacro("PSP"); 632 Builder.defineMacro("_PSP"); 633 Builder.defineMacro("__psp__"); 634 Builder.defineMacro("__ELF__"); 635 } 636 public: 637 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 638 }; 639 640 // PS3 PPU Target 641 template<typename Target> 642 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 643 protected: 644 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 645 MacroBuilder &Builder) const override { 646 // PS3 PPU defines. 647 Builder.defineMacro("__PPC__"); 648 Builder.defineMacro("__PPU__"); 649 Builder.defineMacro("__CELLOS_LV2__"); 650 Builder.defineMacro("__ELF__"); 651 Builder.defineMacro("__LP32__"); 652 Builder.defineMacro("_ARCH_PPC64"); 653 Builder.defineMacro("__powerpc64__"); 654 } 655 public: 656 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 657 : OSTargetInfo<Target>(Triple, Opts) { 658 this->LongWidth = this->LongAlign = 32; 659 this->PointerWidth = this->PointerAlign = 32; 660 this->IntMaxType = TargetInfo::SignedLongLong; 661 this->Int64Type = TargetInfo::SignedLongLong; 662 this->SizeType = TargetInfo::UnsignedInt; 663 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 664 } 665 }; 666 667 template <typename Target> 668 class PS4OSTargetInfo : public OSTargetInfo<Target> { 669 protected: 670 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 671 MacroBuilder &Builder) const override { 672 Builder.defineMacro("__FreeBSD__", "9"); 673 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 674 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 675 DefineStd(Builder, "unix", Opts); 676 Builder.defineMacro("__ELF__"); 677 Builder.defineMacro("__ORBIS__"); 678 } 679 public: 680 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 681 : OSTargetInfo<Target>(Triple, Opts) { 682 this->WCharType = this->UnsignedShort; 683 684 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 685 this->MaxTLSAlign = 256; 686 687 // On PS4, do not honor explicit bit field alignment, 688 // as in "__attribute__((aligned(2))) int b : 1;". 689 this->UseExplicitBitFieldAlignment = false; 690 691 switch (Triple.getArch()) { 692 default: 693 case llvm::Triple::x86_64: 694 this->MCountName = ".mcount"; 695 break; 696 } 697 } 698 }; 699 700 // Solaris target 701 template<typename Target> 702 class SolarisTargetInfo : public OSTargetInfo<Target> { 703 protected: 704 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 705 MacroBuilder &Builder) const override { 706 DefineStd(Builder, "sun", Opts); 707 DefineStd(Builder, "unix", Opts); 708 Builder.defineMacro("__ELF__"); 709 Builder.defineMacro("__svr4__"); 710 Builder.defineMacro("__SVR4"); 711 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 712 // newer, but to 500 for everything else. feature_test.h has a check to 713 // ensure that you are not using C99 with an old version of X/Open or C89 714 // with a new version. 715 if (Opts.C99) 716 Builder.defineMacro("_XOPEN_SOURCE", "600"); 717 else 718 Builder.defineMacro("_XOPEN_SOURCE", "500"); 719 if (Opts.CPlusPlus) 720 Builder.defineMacro("__C99FEATURES__"); 721 Builder.defineMacro("_LARGEFILE_SOURCE"); 722 Builder.defineMacro("_LARGEFILE64_SOURCE"); 723 Builder.defineMacro("__EXTENSIONS__"); 724 Builder.defineMacro("_REENTRANT"); 725 } 726 public: 727 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 728 : OSTargetInfo<Target>(Triple, Opts) { 729 this->WCharType = this->SignedInt; 730 // FIXME: WIntType should be SignedLong 731 } 732 }; 733 734 // Windows target 735 template<typename Target> 736 class WindowsTargetInfo : public OSTargetInfo<Target> { 737 protected: 738 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 739 MacroBuilder &Builder) const override { 740 Builder.defineMacro("_WIN32"); 741 } 742 void getVisualStudioDefines(const LangOptions &Opts, 743 MacroBuilder &Builder) const { 744 if (Opts.CPlusPlus) { 745 if (Opts.RTTIData) 746 Builder.defineMacro("_CPPRTTI"); 747 748 if (Opts.CXXExceptions) 749 Builder.defineMacro("_CPPUNWIND"); 750 } 751 752 if (Opts.Bool) 753 Builder.defineMacro("__BOOL_DEFINED"); 754 755 if (!Opts.CharIsSigned) 756 Builder.defineMacro("_CHAR_UNSIGNED"); 757 758 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 759 // but it works for now. 760 if (Opts.POSIXThreads) 761 Builder.defineMacro("_MT"); 762 763 if (Opts.MSCompatibilityVersion) { 764 Builder.defineMacro("_MSC_VER", 765 Twine(Opts.MSCompatibilityVersion / 100000)); 766 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 767 // FIXME We cannot encode the revision information into 32-bits 768 Builder.defineMacro("_MSC_BUILD", Twine(1)); 769 770 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 771 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 772 773 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 774 if (Opts.CPlusPlus1z) 775 Builder.defineMacro("_MSVC_LANG", "201403L"); 776 else if (Opts.CPlusPlus14) 777 Builder.defineMacro("_MSVC_LANG", "201402L"); 778 } 779 } 780 781 if (Opts.MicrosoftExt) { 782 Builder.defineMacro("_MSC_EXTENSIONS"); 783 784 if (Opts.CPlusPlus11) { 785 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 786 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 787 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 788 } 789 } 790 791 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 792 } 793 794 public: 795 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 796 : OSTargetInfo<Target>(Triple, Opts) {} 797 }; 798 799 template <typename Target> 800 class NaClTargetInfo : public OSTargetInfo<Target> { 801 protected: 802 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 803 MacroBuilder &Builder) const override { 804 if (Opts.POSIXThreads) 805 Builder.defineMacro("_REENTRANT"); 806 if (Opts.CPlusPlus) 807 Builder.defineMacro("_GNU_SOURCE"); 808 809 DefineStd(Builder, "unix", Opts); 810 Builder.defineMacro("__ELF__"); 811 Builder.defineMacro("__native_client__"); 812 } 813 814 public: 815 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 816 : OSTargetInfo<Target>(Triple, Opts) { 817 this->LongAlign = 32; 818 this->LongWidth = 32; 819 this->PointerAlign = 32; 820 this->PointerWidth = 32; 821 this->IntMaxType = TargetInfo::SignedLongLong; 822 this->Int64Type = TargetInfo::SignedLongLong; 823 this->DoubleAlign = 64; 824 this->LongDoubleWidth = 64; 825 this->LongDoubleAlign = 64; 826 this->LongLongWidth = 64; 827 this->LongLongAlign = 64; 828 this->SizeType = TargetInfo::UnsignedInt; 829 this->PtrDiffType = TargetInfo::SignedInt; 830 this->IntPtrType = TargetInfo::SignedInt; 831 // RegParmMax is inherited from the underlying architecture. 832 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 833 if (Triple.getArch() == llvm::Triple::arm) { 834 // Handled in ARM's setABI(). 835 } else if (Triple.getArch() == llvm::Triple::x86) { 836 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 837 } else if (Triple.getArch() == llvm::Triple::x86_64) { 838 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 839 } else if (Triple.getArch() == llvm::Triple::mipsel) { 840 // Handled on mips' setDataLayout. 841 } else { 842 assert(Triple.getArch() == llvm::Triple::le32); 843 this->resetDataLayout("e-p:32:32-i64:64"); 844 } 845 } 846 }; 847 848 // Fuchsia Target 849 template<typename Target> 850 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 851 protected: 852 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 853 MacroBuilder &Builder) const override { 854 Builder.defineMacro("__Fuchsia__"); 855 Builder.defineMacro("__ELF__"); 856 if (Opts.POSIXThreads) 857 Builder.defineMacro("_REENTRANT"); 858 // Required by the libc++ locale support. 859 if (Opts.CPlusPlus) 860 Builder.defineMacro("_GNU_SOURCE"); 861 } 862 public: 863 FuchsiaTargetInfo(const llvm::Triple &Triple, 864 const TargetOptions &Opts) 865 : OSTargetInfo<Target>(Triple, Opts) { 866 this->MCountName = "__mcount"; 867 } 868 }; 869 870 // WebAssembly target 871 template <typename Target> 872 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 873 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 874 MacroBuilder &Builder) const final { 875 // A common platform macro. 876 if (Opts.POSIXThreads) 877 Builder.defineMacro("_REENTRANT"); 878 // Follow g++ convention and predefine _GNU_SOURCE for C++. 879 if (Opts.CPlusPlus) 880 Builder.defineMacro("_GNU_SOURCE"); 881 } 882 883 // As an optimization, group static init code together in a section. 884 const char *getStaticInitSectionSpecifier() const final { 885 return ".text.__startup"; 886 } 887 888 public: 889 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 890 const TargetOptions &Opts) 891 : OSTargetInfo<Target>(Triple, Opts) { 892 this->MCountName = "__mcount"; 893 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 894 } 895 }; 896 897 //===----------------------------------------------------------------------===// 898 // Specific target implementations. 899 //===----------------------------------------------------------------------===// 900 901 // PPC abstract base class 902 class PPCTargetInfo : public TargetInfo { 903 static const Builtin::Info BuiltinInfo[]; 904 static const char * const GCCRegNames[]; 905 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 906 std::string CPU; 907 908 // Target cpu features. 909 bool HasAltivec; 910 bool HasVSX; 911 bool HasP8Vector; 912 bool HasP8Crypto; 913 bool HasDirectMove; 914 bool HasQPX; 915 bool HasHTM; 916 bool HasBPERMD; 917 bool HasExtDiv; 918 bool HasP9Vector; 919 920 protected: 921 std::string ABI; 922 923 public: 924 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 925 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 926 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 927 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 928 SuitableAlign = 128; 929 SimdDefaultAlign = 128; 930 LongDoubleWidth = LongDoubleAlign = 128; 931 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 932 } 933 934 /// \brief Flags for architecture specific defines. 935 typedef enum { 936 ArchDefineNone = 0, 937 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 938 ArchDefinePpcgr = 1 << 1, 939 ArchDefinePpcsq = 1 << 2, 940 ArchDefine440 = 1 << 3, 941 ArchDefine603 = 1 << 4, 942 ArchDefine604 = 1 << 5, 943 ArchDefinePwr4 = 1 << 6, 944 ArchDefinePwr5 = 1 << 7, 945 ArchDefinePwr5x = 1 << 8, 946 ArchDefinePwr6 = 1 << 9, 947 ArchDefinePwr6x = 1 << 10, 948 ArchDefinePwr7 = 1 << 11, 949 ArchDefinePwr8 = 1 << 12, 950 ArchDefinePwr9 = 1 << 13, 951 ArchDefineA2 = 1 << 14, 952 ArchDefineA2q = 1 << 15 953 } ArchDefineTypes; 954 955 // Set the language option for altivec based on our value. 956 void adjust(LangOptions &Opts) override { 957 if (HasAltivec) 958 Opts.AltiVec = 1; 959 TargetInfo::adjust(Opts); 960 } 961 962 // Note: GCC recognizes the following additional cpus: 963 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 964 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 965 // titan, rs64. 966 bool isValidCPUName(StringRef Name) const override { 967 return llvm::StringSwitch<bool>(Name) 968 .Case("generic", true) 969 .Case("440", true) 970 .Case("450", true) 971 .Case("601", true) 972 .Case("602", true) 973 .Case("603", true) 974 .Case("603e", true) 975 .Case("603ev", true) 976 .Case("604", true) 977 .Case("604e", true) 978 .Case("620", true) 979 .Case("630", true) 980 .Case("g3", true) 981 .Case("7400", true) 982 .Case("g4", true) 983 .Case("7450", true) 984 .Case("g4+", true) 985 .Case("750", true) 986 .Case("970", true) 987 .Case("g5", true) 988 .Case("a2", true) 989 .Case("a2q", true) 990 .Case("e500mc", true) 991 .Case("e5500", true) 992 .Case("power3", true) 993 .Case("pwr3", true) 994 .Case("power4", true) 995 .Case("pwr4", true) 996 .Case("power5", true) 997 .Case("pwr5", true) 998 .Case("power5x", true) 999 .Case("pwr5x", true) 1000 .Case("power6", true) 1001 .Case("pwr6", true) 1002 .Case("power6x", true) 1003 .Case("pwr6x", true) 1004 .Case("power7", true) 1005 .Case("pwr7", true) 1006 .Case("power8", true) 1007 .Case("pwr8", true) 1008 .Case("power9", true) 1009 .Case("pwr9", true) 1010 .Case("powerpc", true) 1011 .Case("ppc", true) 1012 .Case("powerpc64", true) 1013 .Case("ppc64", true) 1014 .Case("powerpc64le", true) 1015 .Case("ppc64le", true) 1016 .Default(false); 1017 } 1018 1019 bool setCPU(const std::string &Name) override { 1020 bool CPUKnown = isValidCPUName(Name); 1021 if (CPUKnown) 1022 CPU = Name; 1023 return CPUKnown; 1024 } 1025 1026 1027 StringRef getABI() const override { return ABI; } 1028 1029 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1030 return llvm::makeArrayRef(BuiltinInfo, 1031 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1032 } 1033 1034 bool isCLZForZeroUndef() const override { return false; } 1035 1036 void getTargetDefines(const LangOptions &Opts, 1037 MacroBuilder &Builder) const override; 1038 1039 bool 1040 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1041 StringRef CPU, 1042 const std::vector<std::string> &FeaturesVec) const override; 1043 1044 bool handleTargetFeatures(std::vector<std::string> &Features, 1045 DiagnosticsEngine &Diags) override; 1046 bool hasFeature(StringRef Feature) const override; 1047 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1048 bool Enabled) const override; 1049 1050 ArrayRef<const char *> getGCCRegNames() const override; 1051 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1052 bool validateAsmConstraint(const char *&Name, 1053 TargetInfo::ConstraintInfo &Info) const override { 1054 switch (*Name) { 1055 default: return false; 1056 case 'O': // Zero 1057 break; 1058 case 'b': // Base register 1059 case 'f': // Floating point register 1060 Info.setAllowsRegister(); 1061 break; 1062 // FIXME: The following are added to allow parsing. 1063 // I just took a guess at what the actions should be. 1064 // Also, is more specific checking needed? I.e. specific registers? 1065 case 'd': // Floating point register (containing 64-bit value) 1066 case 'v': // Altivec vector register 1067 Info.setAllowsRegister(); 1068 break; 1069 case 'w': 1070 switch (Name[1]) { 1071 case 'd':// VSX vector register to hold vector double data 1072 case 'f':// VSX vector register to hold vector float data 1073 case 's':// VSX vector register to hold scalar float data 1074 case 'a':// Any VSX register 1075 case 'c':// An individual CR bit 1076 break; 1077 default: 1078 return false; 1079 } 1080 Info.setAllowsRegister(); 1081 Name++; // Skip over 'w'. 1082 break; 1083 case 'h': // `MQ', `CTR', or `LINK' register 1084 case 'q': // `MQ' register 1085 case 'c': // `CTR' register 1086 case 'l': // `LINK' register 1087 case 'x': // `CR' register (condition register) number 0 1088 case 'y': // `CR' register (condition register) 1089 case 'z': // `XER[CA]' carry bit (part of the XER register) 1090 Info.setAllowsRegister(); 1091 break; 1092 case 'I': // Signed 16-bit constant 1093 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1094 // (use `L' instead for SImode constants) 1095 case 'K': // Unsigned 16-bit constant 1096 case 'L': // Signed 16-bit constant shifted left 16 bits 1097 case 'M': // Constant larger than 31 1098 case 'N': // Exact power of 2 1099 case 'P': // Constant whose negation is a signed 16-bit constant 1100 case 'G': // Floating point constant that can be loaded into a 1101 // register with one instruction per word 1102 case 'H': // Integer/Floating point constant that can be loaded 1103 // into a register using three instructions 1104 break; 1105 case 'm': // Memory operand. Note that on PowerPC targets, m can 1106 // include addresses that update the base register. It 1107 // is therefore only safe to use `m' in an asm statement 1108 // if that asm statement accesses the operand exactly once. 1109 // The asm statement must also use `%U<opno>' as a 1110 // placeholder for the "update" flag in the corresponding 1111 // load or store instruction. For example: 1112 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1113 // is correct but: 1114 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1115 // is not. Use es rather than m if you don't want the base 1116 // register to be updated. 1117 case 'e': 1118 if (Name[1] != 's') 1119 return false; 1120 // es: A "stable" memory operand; that is, one which does not 1121 // include any automodification of the base register. Unlike 1122 // `m', this constraint can be used in asm statements that 1123 // might access the operand several times, or that might not 1124 // access it at all. 1125 Info.setAllowsMemory(); 1126 Name++; // Skip over 'e'. 1127 break; 1128 case 'Q': // Memory operand that is an offset from a register (it is 1129 // usually better to use `m' or `es' in asm statements) 1130 case 'Z': // Memory operand that is an indexed or indirect from a 1131 // register (it is usually better to use `m' or `es' in 1132 // asm statements) 1133 Info.setAllowsMemory(); 1134 Info.setAllowsRegister(); 1135 break; 1136 case 'R': // AIX TOC entry 1137 case 'a': // Address operand that is an indexed or indirect from a 1138 // register (`p' is preferable for asm statements) 1139 case 'S': // Constant suitable as a 64-bit mask operand 1140 case 'T': // Constant suitable as a 32-bit mask operand 1141 case 'U': // System V Release 4 small data area reference 1142 case 't': // AND masks that can be performed by two rldic{l, r} 1143 // instructions 1144 case 'W': // Vector constant that does not require memory 1145 case 'j': // Vector constant that is all zeros. 1146 break; 1147 // End FIXME. 1148 } 1149 return true; 1150 } 1151 std::string convertConstraint(const char *&Constraint) const override { 1152 std::string R; 1153 switch (*Constraint) { 1154 case 'e': 1155 case 'w': 1156 // Two-character constraint; add "^" hint for later parsing. 1157 R = std::string("^") + std::string(Constraint, 2); 1158 Constraint++; 1159 break; 1160 default: 1161 return TargetInfo::convertConstraint(Constraint); 1162 } 1163 return R; 1164 } 1165 const char *getClobbers() const override { 1166 return ""; 1167 } 1168 int getEHDataRegisterNumber(unsigned RegNo) const override { 1169 if (RegNo == 0) return 3; 1170 if (RegNo == 1) return 4; 1171 return -1; 1172 } 1173 1174 bool hasSjLjLowering() const override { 1175 return true; 1176 } 1177 1178 bool useFloat128ManglingForLongDouble() const override { 1179 return LongDoubleWidth == 128 && 1180 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1181 getTriple().isOSBinFormatELF(); 1182 } 1183 }; 1184 1185 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1186 #define BUILTIN(ID, TYPE, ATTRS) \ 1187 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1188 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1189 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1190 #include "clang/Basic/BuiltinsPPC.def" 1191 }; 1192 1193 /// handleTargetFeatures - Perform initialization based on the user 1194 /// configured set of features. 1195 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1196 DiagnosticsEngine &Diags) { 1197 for (const auto &Feature : Features) { 1198 if (Feature == "+altivec") { 1199 HasAltivec = true; 1200 } else if (Feature == "+vsx") { 1201 HasVSX = true; 1202 } else if (Feature == "+bpermd") { 1203 HasBPERMD = true; 1204 } else if (Feature == "+extdiv") { 1205 HasExtDiv = true; 1206 } else if (Feature == "+power8-vector") { 1207 HasP8Vector = true; 1208 } else if (Feature == "+crypto") { 1209 HasP8Crypto = true; 1210 } else if (Feature == "+direct-move") { 1211 HasDirectMove = true; 1212 } else if (Feature == "+qpx") { 1213 HasQPX = true; 1214 } else if (Feature == "+htm") { 1215 HasHTM = true; 1216 } else if (Feature == "+float128") { 1217 HasFloat128 = true; 1218 } else if (Feature == "+power9-vector") { 1219 HasP9Vector = true; 1220 } 1221 // TODO: Finish this list and add an assert that we've handled them 1222 // all. 1223 } 1224 1225 return true; 1226 } 1227 1228 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1229 /// #defines that are not tied to a specific subtarget. 1230 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1231 MacroBuilder &Builder) const { 1232 // Target identification. 1233 Builder.defineMacro("__ppc__"); 1234 Builder.defineMacro("__PPC__"); 1235 Builder.defineMacro("_ARCH_PPC"); 1236 Builder.defineMacro("__powerpc__"); 1237 Builder.defineMacro("__POWERPC__"); 1238 if (PointerWidth == 64) { 1239 Builder.defineMacro("_ARCH_PPC64"); 1240 Builder.defineMacro("__powerpc64__"); 1241 Builder.defineMacro("__ppc64__"); 1242 Builder.defineMacro("__PPC64__"); 1243 } 1244 1245 // Target properties. 1246 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1247 Builder.defineMacro("_LITTLE_ENDIAN"); 1248 } else { 1249 if (getTriple().getOS() != llvm::Triple::NetBSD && 1250 getTriple().getOS() != llvm::Triple::OpenBSD) 1251 Builder.defineMacro("_BIG_ENDIAN"); 1252 } 1253 1254 // ABI options. 1255 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1256 Builder.defineMacro("_CALL_ELF", "1"); 1257 if (ABI == "elfv2") 1258 Builder.defineMacro("_CALL_ELF", "2"); 1259 1260 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1261 // our suppport post-dates this and it should work on all 64-bit ppc linux 1262 // platforms. It is guaranteed to work on all elfv2 platforms. 1263 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1264 Builder.defineMacro("_CALL_LINUX", "1"); 1265 1266 // Subtarget options. 1267 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1268 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1269 1270 // FIXME: Should be controlled by command line option. 1271 if (LongDoubleWidth == 128) { 1272 Builder.defineMacro("__LONG_DOUBLE_128__"); 1273 Builder.defineMacro("__LONGDOUBLE128"); 1274 } 1275 1276 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1277 if (ABI == "elfv2" || 1278 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1279 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1280 1281 // CPU identification. 1282 ArchDefineTypes defs = 1283 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1284 .Case("440", ArchDefineName) 1285 .Case("450", ArchDefineName | ArchDefine440) 1286 .Case("601", ArchDefineName) 1287 .Case("602", ArchDefineName | ArchDefinePpcgr) 1288 .Case("603", ArchDefineName | ArchDefinePpcgr) 1289 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1290 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1291 .Case("604", ArchDefineName | ArchDefinePpcgr) 1292 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1293 .Case("620", ArchDefineName | ArchDefinePpcgr) 1294 .Case("630", ArchDefineName | ArchDefinePpcgr) 1295 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1296 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1297 .Case("750", ArchDefineName | ArchDefinePpcgr) 1298 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1299 ArchDefinePpcsq) 1300 .Case("a2", ArchDefineA2) 1301 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1302 .Case("pwr3", ArchDefinePpcgr) 1303 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1304 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1305 ArchDefinePpcsq) 1306 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1307 ArchDefinePpcgr | ArchDefinePpcsq) 1308 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1309 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1311 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1314 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1317 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1319 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1320 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1321 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1322 ArchDefinePpcsq) 1323 .Case("power3", ArchDefinePpcgr) 1324 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1325 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1326 ArchDefinePpcsq) 1327 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1328 ArchDefinePpcgr | ArchDefinePpcsq) 1329 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1330 ArchDefinePwr4 | ArchDefinePpcgr | 1331 ArchDefinePpcsq) 1332 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1333 ArchDefinePwr5 | ArchDefinePwr4 | 1334 ArchDefinePpcgr | ArchDefinePpcsq) 1335 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1336 ArchDefinePwr5x | ArchDefinePwr5 | 1337 ArchDefinePwr4 | ArchDefinePpcgr | 1338 ArchDefinePpcsq) 1339 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1340 ArchDefinePwr6 | ArchDefinePwr5x | 1341 ArchDefinePwr5 | ArchDefinePwr4 | 1342 ArchDefinePpcgr | ArchDefinePpcsq) 1343 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1344 ArchDefinePwr6x | ArchDefinePwr6 | 1345 ArchDefinePwr5x | ArchDefinePwr5 | 1346 ArchDefinePwr4 | ArchDefinePpcgr | 1347 ArchDefinePpcsq) 1348 // powerpc64le automatically defaults to at least power8. 1349 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1350 ArchDefinePwr6 | ArchDefinePwr5x | 1351 ArchDefinePwr5 | ArchDefinePwr4 | 1352 ArchDefinePpcgr | ArchDefinePpcsq) 1353 .Default(ArchDefineNone); 1354 1355 if (defs & ArchDefineName) 1356 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1357 if (defs & ArchDefinePpcgr) 1358 Builder.defineMacro("_ARCH_PPCGR"); 1359 if (defs & ArchDefinePpcsq) 1360 Builder.defineMacro("_ARCH_PPCSQ"); 1361 if (defs & ArchDefine440) 1362 Builder.defineMacro("_ARCH_440"); 1363 if (defs & ArchDefine603) 1364 Builder.defineMacro("_ARCH_603"); 1365 if (defs & ArchDefine604) 1366 Builder.defineMacro("_ARCH_604"); 1367 if (defs & ArchDefinePwr4) 1368 Builder.defineMacro("_ARCH_PWR4"); 1369 if (defs & ArchDefinePwr5) 1370 Builder.defineMacro("_ARCH_PWR5"); 1371 if (defs & ArchDefinePwr5x) 1372 Builder.defineMacro("_ARCH_PWR5X"); 1373 if (defs & ArchDefinePwr6) 1374 Builder.defineMacro("_ARCH_PWR6"); 1375 if (defs & ArchDefinePwr6x) 1376 Builder.defineMacro("_ARCH_PWR6X"); 1377 if (defs & ArchDefinePwr7) 1378 Builder.defineMacro("_ARCH_PWR7"); 1379 if (defs & ArchDefinePwr8) 1380 Builder.defineMacro("_ARCH_PWR8"); 1381 if (defs & ArchDefinePwr9) 1382 Builder.defineMacro("_ARCH_PWR9"); 1383 if (defs & ArchDefineA2) 1384 Builder.defineMacro("_ARCH_A2"); 1385 if (defs & ArchDefineA2q) { 1386 Builder.defineMacro("_ARCH_A2Q"); 1387 Builder.defineMacro("_ARCH_QP"); 1388 } 1389 1390 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1391 Builder.defineMacro("__bg__"); 1392 Builder.defineMacro("__THW_BLUEGENE__"); 1393 Builder.defineMacro("__bgq__"); 1394 Builder.defineMacro("__TOS_BGQ__"); 1395 } 1396 1397 if (HasAltivec) { 1398 Builder.defineMacro("__VEC__", "10206"); 1399 Builder.defineMacro("__ALTIVEC__"); 1400 } 1401 if (HasVSX) 1402 Builder.defineMacro("__VSX__"); 1403 if (HasP8Vector) 1404 Builder.defineMacro("__POWER8_VECTOR__"); 1405 if (HasP8Crypto) 1406 Builder.defineMacro("__CRYPTO__"); 1407 if (HasHTM) 1408 Builder.defineMacro("__HTM__"); 1409 if (HasFloat128) 1410 Builder.defineMacro("__FLOAT128__"); 1411 if (HasP9Vector) 1412 Builder.defineMacro("__POWER9_VECTOR__"); 1413 1414 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1415 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1416 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1417 if (PointerWidth == 64) 1418 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1419 1420 // We have support for the bswap intrinsics so we can define this. 1421 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1422 1423 // FIXME: The following are not yet generated here by Clang, but are 1424 // generated by GCC: 1425 // 1426 // _SOFT_FLOAT_ 1427 // __RECIP_PRECISION__ 1428 // __APPLE_ALTIVEC__ 1429 // __RECIP__ 1430 // __RECIPF__ 1431 // __RSQRTE__ 1432 // __RSQRTEF__ 1433 // _SOFT_DOUBLE_ 1434 // __NO_LWSYNC__ 1435 // __CMODEL_MEDIUM__ 1436 // __CMODEL_LARGE__ 1437 // _CALL_SYSV 1438 // _CALL_DARWIN 1439 // __NO_FPRS__ 1440 } 1441 1442 // Handle explicit options being passed to the compiler here: if we've 1443 // explicitly turned off vsx and turned on any of: 1444 // - power8-vector 1445 // - direct-move 1446 // - float128 1447 // - power9-vector 1448 // then go ahead and error since the customer has expressed an incompatible 1449 // set of options. 1450 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1451 const std::vector<std::string> &FeaturesVec) { 1452 1453 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1454 FeaturesVec.end()) { 1455 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1456 FeaturesVec.end()) { 1457 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1458 << "-mno-vsx"; 1459 return false; 1460 } 1461 1462 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1463 FeaturesVec.end()) { 1464 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1465 << "-mno-vsx"; 1466 return false; 1467 } 1468 1469 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1470 FeaturesVec.end()) { 1471 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1472 << "-mno-vsx"; 1473 return false; 1474 } 1475 1476 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1477 FeaturesVec.end()) { 1478 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1479 << "-mno-vsx"; 1480 return false; 1481 } 1482 } 1483 1484 return true; 1485 } 1486 1487 bool PPCTargetInfo::initFeatureMap( 1488 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1489 const std::vector<std::string> &FeaturesVec) const { 1490 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1491 .Case("7400", true) 1492 .Case("g4", true) 1493 .Case("7450", true) 1494 .Case("g4+", true) 1495 .Case("970", true) 1496 .Case("g5", true) 1497 .Case("pwr6", true) 1498 .Case("pwr7", true) 1499 .Case("pwr8", true) 1500 .Case("pwr9", true) 1501 .Case("ppc64", true) 1502 .Case("ppc64le", true) 1503 .Default(false); 1504 1505 Features["qpx"] = (CPU == "a2q"); 1506 Features["power9-vector"] = (CPU == "pwr9"); 1507 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1508 .Case("ppc64le", true) 1509 .Case("pwr9", true) 1510 .Case("pwr8", true) 1511 .Default(false); 1512 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1513 .Case("ppc64le", true) 1514 .Case("pwr9", true) 1515 .Case("pwr8", true) 1516 .Default(false); 1517 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1518 .Case("ppc64le", true) 1519 .Case("pwr9", true) 1520 .Case("pwr8", true) 1521 .Case("pwr7", true) 1522 .Default(false); 1523 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1524 .Case("ppc64le", true) 1525 .Case("pwr9", true) 1526 .Case("pwr8", true) 1527 .Case("pwr7", true) 1528 .Default(false); 1529 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1530 .Case("ppc64le", true) 1531 .Case("pwr9", true) 1532 .Case("pwr8", true) 1533 .Default(false); 1534 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1535 .Case("ppc64le", true) 1536 .Case("pwr9", true) 1537 .Case("pwr8", true) 1538 .Case("pwr7", true) 1539 .Default(false); 1540 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1541 .Case("ppc64le", true) 1542 .Case("pwr9", true) 1543 .Case("pwr8", true) 1544 .Default(false); 1545 1546 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1547 return false; 1548 1549 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1550 } 1551 1552 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1553 return llvm::StringSwitch<bool>(Feature) 1554 .Case("powerpc", true) 1555 .Case("altivec", HasAltivec) 1556 .Case("vsx", HasVSX) 1557 .Case("power8-vector", HasP8Vector) 1558 .Case("crypto", HasP8Crypto) 1559 .Case("direct-move", HasDirectMove) 1560 .Case("qpx", HasQPX) 1561 .Case("htm", HasHTM) 1562 .Case("bpermd", HasBPERMD) 1563 .Case("extdiv", HasExtDiv) 1564 .Case("float128", HasFloat128) 1565 .Case("power9-vector", HasP9Vector) 1566 .Default(false); 1567 } 1568 1569 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1570 StringRef Name, bool Enabled) const { 1571 if (Enabled) { 1572 // If we're enabling any of the vsx based features then enable vsx and 1573 // altivec. We'll diagnose any problems later. 1574 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1575 .Case("vsx", true) 1576 .Case("direct-move", true) 1577 .Case("power8-vector", true) 1578 .Case("power9-vector", true) 1579 .Case("float128", true) 1580 .Default(false); 1581 if (FeatureHasVSX) 1582 Features["vsx"] = Features["altivec"] = true; 1583 if (Name == "power9-vector") 1584 Features["power8-vector"] = true; 1585 Features[Name] = true; 1586 } else { 1587 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1588 // features. 1589 if ((Name == "altivec") || (Name == "vsx")) 1590 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1591 Features["float128"] = Features["power9-vector"] = false; 1592 if (Name == "power8-vector") 1593 Features["power9-vector"] = false; 1594 Features[Name] = false; 1595 } 1596 } 1597 1598 const char * const PPCTargetInfo::GCCRegNames[] = { 1599 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1600 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1601 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1602 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1603 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1604 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1605 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1606 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1607 "mq", "lr", "ctr", "ap", 1608 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1609 "xer", 1610 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1611 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1612 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1613 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1614 "vrsave", "vscr", 1615 "spe_acc", "spefscr", 1616 "sfp" 1617 }; 1618 1619 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1620 return llvm::makeArrayRef(GCCRegNames); 1621 } 1622 1623 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1624 // While some of these aliases do map to different registers 1625 // they still share the same register name. 1626 { { "0" }, "r0" }, 1627 { { "1"}, "r1" }, 1628 { { "2" }, "r2" }, 1629 { { "3" }, "r3" }, 1630 { { "4" }, "r4" }, 1631 { { "5" }, "r5" }, 1632 { { "6" }, "r6" }, 1633 { { "7" }, "r7" }, 1634 { { "8" }, "r8" }, 1635 { { "9" }, "r9" }, 1636 { { "10" }, "r10" }, 1637 { { "11" }, "r11" }, 1638 { { "12" }, "r12" }, 1639 { { "13" }, "r13" }, 1640 { { "14" }, "r14" }, 1641 { { "15" }, "r15" }, 1642 { { "16" }, "r16" }, 1643 { { "17" }, "r17" }, 1644 { { "18" }, "r18" }, 1645 { { "19" }, "r19" }, 1646 { { "20" }, "r20" }, 1647 { { "21" }, "r21" }, 1648 { { "22" }, "r22" }, 1649 { { "23" }, "r23" }, 1650 { { "24" }, "r24" }, 1651 { { "25" }, "r25" }, 1652 { { "26" }, "r26" }, 1653 { { "27" }, "r27" }, 1654 { { "28" }, "r28" }, 1655 { { "29" }, "r29" }, 1656 { { "30" }, "r30" }, 1657 { { "31" }, "r31" }, 1658 { { "fr0" }, "f0" }, 1659 { { "fr1" }, "f1" }, 1660 { { "fr2" }, "f2" }, 1661 { { "fr3" }, "f3" }, 1662 { { "fr4" }, "f4" }, 1663 { { "fr5" }, "f5" }, 1664 { { "fr6" }, "f6" }, 1665 { { "fr7" }, "f7" }, 1666 { { "fr8" }, "f8" }, 1667 { { "fr9" }, "f9" }, 1668 { { "fr10" }, "f10" }, 1669 { { "fr11" }, "f11" }, 1670 { { "fr12" }, "f12" }, 1671 { { "fr13" }, "f13" }, 1672 { { "fr14" }, "f14" }, 1673 { { "fr15" }, "f15" }, 1674 { { "fr16" }, "f16" }, 1675 { { "fr17" }, "f17" }, 1676 { { "fr18" }, "f18" }, 1677 { { "fr19" }, "f19" }, 1678 { { "fr20" }, "f20" }, 1679 { { "fr21" }, "f21" }, 1680 { { "fr22" }, "f22" }, 1681 { { "fr23" }, "f23" }, 1682 { { "fr24" }, "f24" }, 1683 { { "fr25" }, "f25" }, 1684 { { "fr26" }, "f26" }, 1685 { { "fr27" }, "f27" }, 1686 { { "fr28" }, "f28" }, 1687 { { "fr29" }, "f29" }, 1688 { { "fr30" }, "f30" }, 1689 { { "fr31" }, "f31" }, 1690 { { "cc" }, "cr0" }, 1691 }; 1692 1693 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1694 return llvm::makeArrayRef(GCCRegAliases); 1695 } 1696 1697 class PPC32TargetInfo : public PPCTargetInfo { 1698 public: 1699 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1700 : PPCTargetInfo(Triple, Opts) { 1701 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1702 1703 switch (getTriple().getOS()) { 1704 case llvm::Triple::Linux: 1705 case llvm::Triple::FreeBSD: 1706 case llvm::Triple::NetBSD: 1707 SizeType = UnsignedInt; 1708 PtrDiffType = SignedInt; 1709 IntPtrType = SignedInt; 1710 break; 1711 default: 1712 break; 1713 } 1714 1715 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1716 LongDoubleWidth = LongDoubleAlign = 64; 1717 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1718 } 1719 1720 // PPC32 supports atomics up to 4 bytes. 1721 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1722 } 1723 1724 BuiltinVaListKind getBuiltinVaListKind() const override { 1725 // This is the ELF definition, and is overridden by the Darwin sub-target 1726 return TargetInfo::PowerABIBuiltinVaList; 1727 } 1728 }; 1729 1730 // Note: ABI differences may eventually require us to have a separate 1731 // TargetInfo for little endian. 1732 class PPC64TargetInfo : public PPCTargetInfo { 1733 public: 1734 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1735 : PPCTargetInfo(Triple, Opts) { 1736 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1737 IntMaxType = SignedLong; 1738 Int64Type = SignedLong; 1739 1740 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1741 resetDataLayout("e-m:e-i64:64-n32:64"); 1742 ABI = "elfv2"; 1743 } else { 1744 resetDataLayout("E-m:e-i64:64-n32:64"); 1745 ABI = "elfv1"; 1746 } 1747 1748 switch (getTriple().getOS()) { 1749 case llvm::Triple::FreeBSD: 1750 LongDoubleWidth = LongDoubleAlign = 64; 1751 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1752 break; 1753 case llvm::Triple::NetBSD: 1754 IntMaxType = SignedLongLong; 1755 Int64Type = SignedLongLong; 1756 break; 1757 default: 1758 break; 1759 } 1760 1761 // PPC64 supports atomics up to 8 bytes. 1762 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1763 } 1764 BuiltinVaListKind getBuiltinVaListKind() const override { 1765 return TargetInfo::CharPtrBuiltinVaList; 1766 } 1767 // PPC64 Linux-specific ABI options. 1768 bool setABI(const std::string &Name) override { 1769 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1770 ABI = Name; 1771 return true; 1772 } 1773 return false; 1774 } 1775 }; 1776 1777 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1778 public: 1779 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1780 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1781 HasAlignMac68kSupport = true; 1782 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1783 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1784 LongLongAlign = 32; 1785 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1786 } 1787 BuiltinVaListKind getBuiltinVaListKind() const override { 1788 return TargetInfo::CharPtrBuiltinVaList; 1789 } 1790 }; 1791 1792 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1793 public: 1794 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1795 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1796 HasAlignMac68kSupport = true; 1797 resetDataLayout("E-m:o-i64:64-n32:64"); 1798 } 1799 }; 1800 1801 static const unsigned NVPTXAddrSpaceMap[] = { 1802 0, // Default 1803 1, // opencl_global 1804 3, // opencl_local 1805 4, // opencl_constant 1806 // FIXME: generic has to be added to the target 1807 0, // opencl_generic 1808 1, // cuda_device 1809 4, // cuda_constant 1810 3, // cuda_shared 1811 }; 1812 1813 class NVPTXTargetInfo : public TargetInfo { 1814 static const char *const GCCRegNames[]; 1815 static const Builtin::Info BuiltinInfo[]; 1816 CudaArch GPU; 1817 std::unique_ptr<TargetInfo> HostTarget; 1818 1819 public: 1820 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1821 unsigned TargetPointerWidth) 1822 : TargetInfo(Triple) { 1823 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1824 "NVPTX only supports 32- and 64-bit modes."); 1825 1826 TLSSupported = false; 1827 AddrSpaceMap = &NVPTXAddrSpaceMap; 1828 UseAddrSpaceMapMangling = true; 1829 1830 // Define available target features 1831 // These must be defined in sorted order! 1832 NoAsmVariants = true; 1833 GPU = CudaArch::SM_20; 1834 1835 if (TargetPointerWidth == 32) 1836 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1837 else 1838 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1839 1840 // If possible, get a TargetInfo for our host triple, so we can match its 1841 // types. 1842 llvm::Triple HostTriple(Opts.HostTriple); 1843 if (!HostTriple.isNVPTX()) 1844 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1845 1846 // If no host target, make some guesses about the data layout and return. 1847 if (!HostTarget) { 1848 LongWidth = LongAlign = TargetPointerWidth; 1849 PointerWidth = PointerAlign = TargetPointerWidth; 1850 switch (TargetPointerWidth) { 1851 case 32: 1852 SizeType = TargetInfo::UnsignedInt; 1853 PtrDiffType = TargetInfo::SignedInt; 1854 IntPtrType = TargetInfo::SignedInt; 1855 break; 1856 case 64: 1857 SizeType = TargetInfo::UnsignedLong; 1858 PtrDiffType = TargetInfo::SignedLong; 1859 IntPtrType = TargetInfo::SignedLong; 1860 break; 1861 default: 1862 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1863 } 1864 return; 1865 } 1866 1867 // Copy properties from host target. 1868 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1869 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1870 BoolWidth = HostTarget->getBoolWidth(); 1871 BoolAlign = HostTarget->getBoolAlign(); 1872 IntWidth = HostTarget->getIntWidth(); 1873 IntAlign = HostTarget->getIntAlign(); 1874 HalfWidth = HostTarget->getHalfWidth(); 1875 HalfAlign = HostTarget->getHalfAlign(); 1876 FloatWidth = HostTarget->getFloatWidth(); 1877 FloatAlign = HostTarget->getFloatAlign(); 1878 DoubleWidth = HostTarget->getDoubleWidth(); 1879 DoubleAlign = HostTarget->getDoubleAlign(); 1880 LongWidth = HostTarget->getLongWidth(); 1881 LongAlign = HostTarget->getLongAlign(); 1882 LongLongWidth = HostTarget->getLongLongWidth(); 1883 LongLongAlign = HostTarget->getLongLongAlign(); 1884 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1885 NewAlign = HostTarget->getNewAlign(); 1886 DefaultAlignForAttributeAligned = 1887 HostTarget->getDefaultAlignForAttributeAligned(); 1888 SizeType = HostTarget->getSizeType(); 1889 IntMaxType = HostTarget->getIntMaxType(); 1890 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1891 IntPtrType = HostTarget->getIntPtrType(); 1892 WCharType = HostTarget->getWCharType(); 1893 WIntType = HostTarget->getWIntType(); 1894 Char16Type = HostTarget->getChar16Type(); 1895 Char32Type = HostTarget->getChar32Type(); 1896 Int64Type = HostTarget->getInt64Type(); 1897 SigAtomicType = HostTarget->getSigAtomicType(); 1898 ProcessIDType = HostTarget->getProcessIDType(); 1899 1900 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1901 UseZeroLengthBitfieldAlignment = 1902 HostTarget->useZeroLengthBitfieldAlignment(); 1903 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1904 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1905 1906 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1907 // we need those macros to be identical on host and device, because (among 1908 // other things) they affect which standard library classes are defined, and 1909 // we need all classes to be defined on both the host and device. 1910 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1911 1912 // Properties intentionally not copied from host: 1913 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1914 // host/device boundary. 1915 // - SuitableAlign: Not visible across the host/device boundary, and may 1916 // correctly be different on host/device, e.g. if host has wider vector 1917 // types than device. 1918 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1919 // as its double type, but that's not necessarily true on the host. 1920 // TODO: nvcc emits a warning when using long double on device; we should 1921 // do the same. 1922 } 1923 void getTargetDefines(const LangOptions &Opts, 1924 MacroBuilder &Builder) const override { 1925 Builder.defineMacro("__PTX__"); 1926 Builder.defineMacro("__NVPTX__"); 1927 if (Opts.CUDAIsDevice) { 1928 // Set __CUDA_ARCH__ for the GPU specified. 1929 std::string CUDAArchCode = [this] { 1930 switch (GPU) { 1931 case CudaArch::UNKNOWN: 1932 assert(false && "No GPU arch when compiling CUDA device code."); 1933 return ""; 1934 case CudaArch::SM_20: 1935 return "200"; 1936 case CudaArch::SM_21: 1937 return "210"; 1938 case CudaArch::SM_30: 1939 return "300"; 1940 case CudaArch::SM_32: 1941 return "320"; 1942 case CudaArch::SM_35: 1943 return "350"; 1944 case CudaArch::SM_37: 1945 return "370"; 1946 case CudaArch::SM_50: 1947 return "500"; 1948 case CudaArch::SM_52: 1949 return "520"; 1950 case CudaArch::SM_53: 1951 return "530"; 1952 case CudaArch::SM_60: 1953 return "600"; 1954 case CudaArch::SM_61: 1955 return "610"; 1956 case CudaArch::SM_62: 1957 return "620"; 1958 } 1959 llvm_unreachable("unhandled CudaArch"); 1960 }(); 1961 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1962 } 1963 } 1964 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1965 return llvm::makeArrayRef(BuiltinInfo, 1966 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1967 } 1968 bool 1969 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1970 StringRef CPU, 1971 const std::vector<std::string> &FeaturesVec) const override { 1972 Features["satom"] = GPU >= CudaArch::SM_60; 1973 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1974 } 1975 1976 bool hasFeature(StringRef Feature) const override { 1977 return llvm::StringSwitch<bool>(Feature) 1978 .Cases("ptx", "nvptx", true) 1979 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1980 .Default(false); 1981 } 1982 1983 ArrayRef<const char *> getGCCRegNames() const override; 1984 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1985 // No aliases. 1986 return None; 1987 } 1988 bool validateAsmConstraint(const char *&Name, 1989 TargetInfo::ConstraintInfo &Info) const override { 1990 switch (*Name) { 1991 default: 1992 return false; 1993 case 'c': 1994 case 'h': 1995 case 'r': 1996 case 'l': 1997 case 'f': 1998 case 'd': 1999 Info.setAllowsRegister(); 2000 return true; 2001 } 2002 } 2003 const char *getClobbers() const override { 2004 // FIXME: Is this really right? 2005 return ""; 2006 } 2007 BuiltinVaListKind getBuiltinVaListKind() const override { 2008 // FIXME: implement 2009 return TargetInfo::CharPtrBuiltinVaList; 2010 } 2011 bool isValidCPUName(StringRef Name) const override { 2012 return StringToCudaArch(Name) != CudaArch::UNKNOWN; 2013 } 2014 bool setCPU(const std::string &Name) override { 2015 GPU = StringToCudaArch(Name); 2016 return GPU != CudaArch::UNKNOWN; 2017 } 2018 void setSupportedOpenCLOpts() override { 2019 auto &Opts = getSupportedOpenCLOpts(); 2020 Opts.support("cl_clang_storage_class_specifiers"); 2021 Opts.support("cl_khr_gl_sharing"); 2022 Opts.support("cl_khr_icd"); 2023 2024 Opts.support("cl_khr_fp64"); 2025 Opts.support("cl_khr_byte_addressable_store"); 2026 Opts.support("cl_khr_global_int32_base_atomics"); 2027 Opts.support("cl_khr_global_int32_extended_atomics"); 2028 Opts.support("cl_khr_local_int32_base_atomics"); 2029 Opts.support("cl_khr_local_int32_extended_atomics"); 2030 } 2031 2032 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2033 // CUDA compilations support all of the host's calling conventions. 2034 // 2035 // TODO: We should warn if you apply a non-default CC to anything other than 2036 // a host function. 2037 if (HostTarget) 2038 return HostTarget->checkCallingConvention(CC); 2039 return CCCR_Warning; 2040 } 2041 }; 2042 2043 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2044 #define BUILTIN(ID, TYPE, ATTRS) \ 2045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2048 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2049 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2050 #include "clang/Basic/BuiltinsNVPTX.def" 2051 }; 2052 2053 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2054 2055 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2056 return llvm::makeArrayRef(GCCRegNames); 2057 } 2058 2059 static const LangAS::Map AMDGPUPrivIsZeroDefIsGenMap = { 2060 4, // Default 2061 1, // opencl_global 2062 3, // opencl_local 2063 2, // opencl_constant 2064 4, // opencl_generic 2065 1, // cuda_device 2066 2, // cuda_constant 2067 3 // cuda_shared 2068 }; 2069 static const LangAS::Map AMDGPUGenIsZeroDefIsGenMap = { 2070 0, // Default 2071 1, // opencl_global 2072 3, // opencl_local 2073 2, // opencl_constant 2074 0, // opencl_generic 2075 1, // cuda_device 2076 2, // cuda_constant 2077 3 // cuda_shared 2078 }; 2079 static const LangAS::Map AMDGPUPrivIsZeroDefIsPrivMap = { 2080 0, // Default 2081 1, // opencl_global 2082 3, // opencl_local 2083 2, // opencl_constant 2084 4, // opencl_generic 2085 1, // cuda_device 2086 2, // cuda_constant 2087 3 // cuda_shared 2088 }; 2089 static const LangAS::Map AMDGPUGenIsZeroDefIsPrivMap = { 2090 5, // Default 2091 1, // opencl_global 2092 3, // opencl_local 2093 2, // opencl_constant 2094 0, // opencl_generic 2095 1, // cuda_device 2096 2, // cuda_constant 2097 3 // cuda_shared 2098 }; 2099 2100 // If you edit the description strings, make sure you update 2101 // getPointerWidthV(). 2102 2103 static const char *const DataLayoutStringR600 = 2104 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2105 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2106 2107 static const char *const DataLayoutStringSIPrivateIsZero = 2108 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2109 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2110 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2111 2112 static const char *const DataLayoutStringSIGenericIsZero = 2113 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2114 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2115 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2116 2117 class AMDGPUTargetInfo final : public TargetInfo { 2118 static const Builtin::Info BuiltinInfo[]; 2119 static const char * const GCCRegNames[]; 2120 2121 struct AddrSpace { 2122 unsigned Generic, Global, Local, Constant, Private; 2123 AddrSpace(bool IsGenericZero_ = false){ 2124 if (IsGenericZero_) { 2125 Generic = 0; 2126 Global = 1; 2127 Local = 3; 2128 Constant = 2; 2129 Private = 5; 2130 } else { 2131 Generic = 4; 2132 Global = 1; 2133 Local = 3; 2134 Constant = 2; 2135 Private = 0; 2136 } 2137 } 2138 }; 2139 2140 /// \brief The GPU profiles supported by the AMDGPU target. 2141 enum GPUKind { 2142 GK_NONE, 2143 GK_R600, 2144 GK_R600_DOUBLE_OPS, 2145 GK_R700, 2146 GK_R700_DOUBLE_OPS, 2147 GK_EVERGREEN, 2148 GK_EVERGREEN_DOUBLE_OPS, 2149 GK_NORTHERN_ISLANDS, 2150 GK_CAYMAN, 2151 GK_GFX6, 2152 GK_GFX7, 2153 GK_GFX8, 2154 GK_GFX9 2155 } GPU; 2156 2157 bool hasFP64:1; 2158 bool hasFMAF:1; 2159 bool hasLDEXPF:1; 2160 const AddrSpace AS; 2161 2162 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2163 return parseAMDGCNName(GPUName) >= GK_GFX9; 2164 } 2165 2166 static bool isAMDGCN(const llvm::Triple &TT) { 2167 return TT.getArch() == llvm::Triple::amdgcn; 2168 } 2169 2170 static bool isGenericZero(const llvm::Triple &TT) { 2171 return TT.getEnvironmentName() == "amdgiz" || 2172 TT.getEnvironmentName() == "amdgizcl"; 2173 } 2174 public: 2175 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2176 : TargetInfo(Triple) , 2177 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2178 hasFP64(false), 2179 hasFMAF(false), 2180 hasLDEXPF(false), 2181 AS(isGenericZero(Triple)){ 2182 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2183 hasFP64 = true; 2184 hasFMAF = true; 2185 hasLDEXPF = true; 2186 } 2187 auto IsGenericZero = isGenericZero(Triple); 2188 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2189 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2190 DataLayoutStringSIPrivateIsZero) 2191 : DataLayoutStringR600); 2192 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2193 2194 setAddressSpaceMap(Triple.getOS() == llvm::Triple::Mesa3D || 2195 Triple.getEnvironment() == llvm::Triple::OpenCL || 2196 Triple.getEnvironmentName() == "amdgizcl" || 2197 !isAMDGCN(Triple)); 2198 UseAddrSpaceMapMangling = true; 2199 2200 // Set pointer width and alignment for target address space 0. 2201 PointerWidth = PointerAlign = DataLayout->getPointerSizeInBits(); 2202 if (getMaxPointerWidth() == 64) { 2203 LongWidth = LongAlign = 64; 2204 SizeType = UnsignedLong; 2205 PtrDiffType = SignedLong; 2206 IntPtrType = SignedLong; 2207 } 2208 } 2209 2210 void setAddressSpaceMap(bool DefaultIsPrivate) { 2211 if (isGenericZero(getTriple())) { 2212 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUGenIsZeroDefIsPrivMap 2213 : &AMDGPUGenIsZeroDefIsGenMap; 2214 } else { 2215 AddrSpaceMap = DefaultIsPrivate ? &AMDGPUPrivIsZeroDefIsPrivMap 2216 : &AMDGPUPrivIsZeroDefIsGenMap; 2217 } 2218 } 2219 2220 void adjust(LangOptions &Opts) override { 2221 TargetInfo::adjust(Opts); 2222 setAddressSpaceMap(Opts.OpenCL || !isAMDGCN(getTriple())); 2223 } 2224 2225 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2226 if (GPU <= GK_CAYMAN) 2227 return 32; 2228 2229 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2230 return 32; 2231 } 2232 return 64; 2233 } 2234 2235 uint64_t getPointerAlignV(unsigned AddrSpace) const override { 2236 return getPointerWidthV(AddrSpace); 2237 } 2238 2239 uint64_t getMaxPointerWidth() const override { 2240 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2241 } 2242 2243 const char * getClobbers() const override { 2244 return ""; 2245 } 2246 2247 ArrayRef<const char *> getGCCRegNames() const override; 2248 2249 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2250 return None; 2251 } 2252 2253 bool validateAsmConstraint(const char *&Name, 2254 TargetInfo::ConstraintInfo &Info) const override { 2255 switch (*Name) { 2256 default: break; 2257 case 'v': // vgpr 2258 case 's': // sgpr 2259 Info.setAllowsRegister(); 2260 return true; 2261 } 2262 return false; 2263 } 2264 2265 bool initFeatureMap(llvm::StringMap<bool> &Features, 2266 DiagnosticsEngine &Diags, StringRef CPU, 2267 const std::vector<std::string> &FeatureVec) const override; 2268 2269 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2270 TargetOptions &TargetOpts) const override { 2271 bool hasFP32Denormals = false; 2272 bool hasFP64Denormals = false; 2273 for (auto &I : TargetOpts.FeaturesAsWritten) { 2274 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2275 hasFP32Denormals = true; 2276 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2277 hasFP64Denormals = true; 2278 } 2279 if (!hasFP32Denormals) 2280 TargetOpts.Features.push_back( 2281 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2282 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2283 // Always do not flush fp64 or fp16 denorms. 2284 if (!hasFP64Denormals && hasFP64) 2285 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2286 } 2287 2288 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2289 return llvm::makeArrayRef(BuiltinInfo, 2290 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2291 } 2292 2293 void getTargetDefines(const LangOptions &Opts, 2294 MacroBuilder &Builder) const override { 2295 if (getTriple().getArch() == llvm::Triple::amdgcn) 2296 Builder.defineMacro("__AMDGCN__"); 2297 else 2298 Builder.defineMacro("__R600__"); 2299 2300 if (hasFMAF) 2301 Builder.defineMacro("__HAS_FMAF__"); 2302 if (hasLDEXPF) 2303 Builder.defineMacro("__HAS_LDEXPF__"); 2304 if (hasFP64) 2305 Builder.defineMacro("__HAS_FP64__"); 2306 } 2307 2308 BuiltinVaListKind getBuiltinVaListKind() const override { 2309 return TargetInfo::CharPtrBuiltinVaList; 2310 } 2311 2312 static GPUKind parseR600Name(StringRef Name) { 2313 return llvm::StringSwitch<GPUKind>(Name) 2314 .Case("r600" , GK_R600) 2315 .Case("rv610", GK_R600) 2316 .Case("rv620", GK_R600) 2317 .Case("rv630", GK_R600) 2318 .Case("rv635", GK_R600) 2319 .Case("rs780", GK_R600) 2320 .Case("rs880", GK_R600) 2321 .Case("rv670", GK_R600_DOUBLE_OPS) 2322 .Case("rv710", GK_R700) 2323 .Case("rv730", GK_R700) 2324 .Case("rv740", GK_R700_DOUBLE_OPS) 2325 .Case("rv770", GK_R700_DOUBLE_OPS) 2326 .Case("palm", GK_EVERGREEN) 2327 .Case("cedar", GK_EVERGREEN) 2328 .Case("sumo", GK_EVERGREEN) 2329 .Case("sumo2", GK_EVERGREEN) 2330 .Case("redwood", GK_EVERGREEN) 2331 .Case("juniper", GK_EVERGREEN) 2332 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2333 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2334 .Case("barts", GK_NORTHERN_ISLANDS) 2335 .Case("turks", GK_NORTHERN_ISLANDS) 2336 .Case("caicos", GK_NORTHERN_ISLANDS) 2337 .Case("cayman", GK_CAYMAN) 2338 .Case("aruba", GK_CAYMAN) 2339 .Default(GK_NONE); 2340 } 2341 2342 static GPUKind parseAMDGCNName(StringRef Name) { 2343 return llvm::StringSwitch<GPUKind>(Name) 2344 .Case("tahiti", GK_GFX6) 2345 .Case("pitcairn", GK_GFX6) 2346 .Case("verde", GK_GFX6) 2347 .Case("oland", GK_GFX6) 2348 .Case("hainan", GK_GFX6) 2349 .Case("bonaire", GK_GFX7) 2350 .Case("kabini", GK_GFX7) 2351 .Case("kaveri", GK_GFX7) 2352 .Case("hawaii", GK_GFX7) 2353 .Case("mullins", GK_GFX7) 2354 .Case("gfx700", GK_GFX7) 2355 .Case("gfx701", GK_GFX7) 2356 .Case("gfx702", GK_GFX7) 2357 .Case("tonga", GK_GFX8) 2358 .Case("iceland", GK_GFX8) 2359 .Case("carrizo", GK_GFX8) 2360 .Case("fiji", GK_GFX8) 2361 .Case("stoney", GK_GFX8) 2362 .Case("polaris10", GK_GFX8) 2363 .Case("polaris11", GK_GFX8) 2364 .Case("gfx800", GK_GFX8) 2365 .Case("gfx801", GK_GFX8) 2366 .Case("gfx802", GK_GFX8) 2367 .Case("gfx803", GK_GFX8) 2368 .Case("gfx804", GK_GFX8) 2369 .Case("gfx810", GK_GFX8) 2370 .Case("gfx900", GK_GFX9) 2371 .Case("gfx901", GK_GFX9) 2372 .Default(GK_NONE); 2373 } 2374 2375 bool isValidCPUName(StringRef Name) const override { 2376 if (getTriple().getArch() == llvm::Triple::amdgcn) 2377 return GK_NONE != parseAMDGCNName(Name); 2378 else 2379 return GK_NONE != parseR600Name(Name); 2380 } 2381 2382 bool setCPU(const std::string &Name) override { 2383 if (getTriple().getArch() == llvm::Triple::amdgcn) 2384 GPU = parseAMDGCNName(Name); 2385 else 2386 GPU = parseR600Name(Name); 2387 2388 return GPU != GK_NONE; 2389 } 2390 2391 void setSupportedOpenCLOpts() override { 2392 auto &Opts = getSupportedOpenCLOpts(); 2393 Opts.support("cl_clang_storage_class_specifiers"); 2394 Opts.support("cl_khr_icd"); 2395 2396 if (hasFP64) 2397 Opts.support("cl_khr_fp64"); 2398 if (GPU >= GK_EVERGREEN) { 2399 Opts.support("cl_khr_byte_addressable_store"); 2400 Opts.support("cl_khr_global_int32_base_atomics"); 2401 Opts.support("cl_khr_global_int32_extended_atomics"); 2402 Opts.support("cl_khr_local_int32_base_atomics"); 2403 Opts.support("cl_khr_local_int32_extended_atomics"); 2404 } 2405 if (GPU >= GK_GFX6) { 2406 Opts.support("cl_khr_fp16"); 2407 Opts.support("cl_khr_int64_base_atomics"); 2408 Opts.support("cl_khr_int64_extended_atomics"); 2409 Opts.support("cl_khr_mipmap_image"); 2410 Opts.support("cl_khr_subgroups"); 2411 Opts.support("cl_khr_3d_image_writes"); 2412 Opts.support("cl_amd_media_ops"); 2413 Opts.support("cl_amd_media_ops2"); 2414 } 2415 } 2416 2417 LangAS::ID getOpenCLImageAddrSpace() const override { 2418 return LangAS::opencl_constant; 2419 } 2420 2421 llvm::Optional<unsigned> getConstantAddressSpace() const override { 2422 return LangAS::FirstTargetAddressSpace + AS.Constant; 2423 } 2424 2425 /// \returns Target specific vtbl ptr address space. 2426 unsigned getVtblPtrAddressSpace() const override { return AS.Constant; } 2427 2428 /// \returns If a target requires an address within a target specific address 2429 /// space \p AddressSpace to be converted in order to be used, then return the 2430 /// corresponding target specific DWARF address space. 2431 /// 2432 /// \returns Otherwise return None and no conversion will be emitted in the 2433 /// DWARF. 2434 Optional<unsigned> getDWARFAddressSpace( 2435 unsigned AddressSpace) const override { 2436 const unsigned DWARF_Private = 1; 2437 const unsigned DWARF_Local = 2; 2438 if (AddressSpace == AS.Private) { 2439 return DWARF_Private; 2440 } else if (AddressSpace == AS.Local) { 2441 return DWARF_Local; 2442 } else { 2443 return None; 2444 } 2445 } 2446 2447 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2448 switch (CC) { 2449 default: 2450 return CCCR_Warning; 2451 case CC_C: 2452 case CC_OpenCLKernel: 2453 return CCCR_OK; 2454 } 2455 } 2456 2457 // In amdgcn target the null pointer in global, constant, and generic 2458 // address space has value 0 but in private and local address space has 2459 // value ~0. 2460 uint64_t getNullPointerValue(unsigned AS) const override { 2461 return AS == LangAS::opencl_local ? ~0 : 0; 2462 } 2463 }; 2464 2465 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2466 #define BUILTIN(ID, TYPE, ATTRS) \ 2467 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2468 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2469 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2470 #include "clang/Basic/BuiltinsAMDGPU.def" 2471 }; 2472 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2473 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2474 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2475 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2476 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2477 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2478 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2479 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2480 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2481 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2482 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2483 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2484 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2485 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2486 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2487 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2488 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2489 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2490 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2491 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2492 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2493 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2494 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2495 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2496 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2497 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2498 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2499 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2500 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2501 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2502 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2503 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2504 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2505 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2506 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2507 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2508 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2509 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2510 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2511 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2512 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2513 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2514 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2515 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2516 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2517 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2518 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2519 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2520 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2521 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2522 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2523 }; 2524 2525 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2526 return llvm::makeArrayRef(GCCRegNames); 2527 } 2528 2529 bool AMDGPUTargetInfo::initFeatureMap( 2530 llvm::StringMap<bool> &Features, 2531 DiagnosticsEngine &Diags, StringRef CPU, 2532 const std::vector<std::string> &FeatureVec) const { 2533 2534 // XXX - What does the member GPU mean if device name string passed here? 2535 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2536 if (CPU.empty()) 2537 CPU = "tahiti"; 2538 2539 switch (parseAMDGCNName(CPU)) { 2540 case GK_GFX6: 2541 case GK_GFX7: 2542 break; 2543 2544 case GK_GFX9: 2545 Features["gfx9-insts"] = true; 2546 LLVM_FALLTHROUGH; 2547 case GK_GFX8: 2548 Features["s-memrealtime"] = true; 2549 Features["16-bit-insts"] = true; 2550 Features["dpp"] = true; 2551 break; 2552 2553 case GK_NONE: 2554 return false; 2555 default: 2556 llvm_unreachable("unhandled subtarget"); 2557 } 2558 } else { 2559 if (CPU.empty()) 2560 CPU = "r600"; 2561 2562 switch (parseR600Name(CPU)) { 2563 case GK_R600: 2564 case GK_R700: 2565 case GK_EVERGREEN: 2566 case GK_NORTHERN_ISLANDS: 2567 break; 2568 case GK_R600_DOUBLE_OPS: 2569 case GK_R700_DOUBLE_OPS: 2570 case GK_EVERGREEN_DOUBLE_OPS: 2571 case GK_CAYMAN: 2572 Features["fp64"] = true; 2573 break; 2574 case GK_NONE: 2575 return false; 2576 default: 2577 llvm_unreachable("unhandled subtarget"); 2578 } 2579 } 2580 2581 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2582 } 2583 2584 const Builtin::Info BuiltinInfoX86[] = { 2585 #define BUILTIN(ID, TYPE, ATTRS) \ 2586 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2587 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2588 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2589 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2590 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2591 #include "clang/Basic/BuiltinsX86.def" 2592 2593 #define BUILTIN(ID, TYPE, ATTRS) \ 2594 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2595 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2596 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2597 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2598 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2599 #include "clang/Basic/BuiltinsX86_64.def" 2600 }; 2601 2602 2603 static const char* const GCCRegNames[] = { 2604 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2605 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2606 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2607 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2608 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2609 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2610 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2611 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2612 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2613 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2614 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2615 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2616 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2617 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2618 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2619 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2620 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2621 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2622 }; 2623 2624 const TargetInfo::AddlRegName AddlRegNames[] = { 2625 { { "al", "ah", "eax", "rax" }, 0 }, 2626 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2627 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2628 { { "dl", "dh", "edx", "rdx" }, 1 }, 2629 { { "esi", "rsi" }, 4 }, 2630 { { "edi", "rdi" }, 5 }, 2631 { { "esp", "rsp" }, 7 }, 2632 { { "ebp", "rbp" }, 6 }, 2633 { { "r8d", "r8w", "r8b" }, 38 }, 2634 { { "r9d", "r9w", "r9b" }, 39 }, 2635 { { "r10d", "r10w", "r10b" }, 40 }, 2636 { { "r11d", "r11w", "r11b" }, 41 }, 2637 { { "r12d", "r12w", "r12b" }, 42 }, 2638 { { "r13d", "r13w", "r13b" }, 43 }, 2639 { { "r14d", "r14w", "r14b" }, 44 }, 2640 { { "r15d", "r15w", "r15b" }, 45 }, 2641 }; 2642 2643 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2644 // most of the implementation can be shared. 2645 class X86TargetInfo : public TargetInfo { 2646 enum X86SSEEnum { 2647 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2648 } SSELevel = NoSSE; 2649 enum MMX3DNowEnum { 2650 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2651 } MMX3DNowLevel = NoMMX3DNow; 2652 enum XOPEnum { 2653 NoXOP, 2654 SSE4A, 2655 FMA4, 2656 XOP 2657 } XOPLevel = NoXOP; 2658 2659 bool HasAES = false; 2660 bool HasPCLMUL = false; 2661 bool HasLZCNT = false; 2662 bool HasRDRND = false; 2663 bool HasFSGSBASE = false; 2664 bool HasBMI = false; 2665 bool HasBMI2 = false; 2666 bool HasPOPCNT = false; 2667 bool HasRTM = false; 2668 bool HasPRFCHW = false; 2669 bool HasRDSEED = false; 2670 bool HasADX = false; 2671 bool HasTBM = false; 2672 bool HasLWP = false; 2673 bool HasFMA = false; 2674 bool HasF16C = false; 2675 bool HasAVX512CD = false; 2676 bool HasAVX512VPOPCNTDQ = false; 2677 bool HasAVX512ER = false; 2678 bool HasAVX512PF = false; 2679 bool HasAVX512DQ = false; 2680 bool HasAVX512BW = false; 2681 bool HasAVX512VL = false; 2682 bool HasAVX512VBMI = false; 2683 bool HasAVX512IFMA = false; 2684 bool HasSHA = false; 2685 bool HasMPX = false; 2686 bool HasSGX = false; 2687 bool HasCX16 = false; 2688 bool HasFXSR = false; 2689 bool HasXSAVE = false; 2690 bool HasXSAVEOPT = false; 2691 bool HasXSAVEC = false; 2692 bool HasXSAVES = false; 2693 bool HasMWAITX = false; 2694 bool HasCLZERO = false; 2695 bool HasPKU = false; 2696 bool HasCLFLUSHOPT = false; 2697 bool HasCLWB = false; 2698 bool HasMOVBE = false; 2699 bool HasPREFETCHWT1 = false; 2700 2701 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2702 /// 2703 /// Each enumeration represents a particular CPU supported by Clang. These 2704 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2705 enum CPUKind { 2706 CK_Generic, 2707 2708 /// \name i386 2709 /// i386-generation processors. 2710 //@{ 2711 CK_i386, 2712 //@} 2713 2714 /// \name i486 2715 /// i486-generation processors. 2716 //@{ 2717 CK_i486, 2718 CK_WinChipC6, 2719 CK_WinChip2, 2720 CK_C3, 2721 //@} 2722 2723 /// \name i586 2724 /// i586-generation processors, P5 microarchitecture based. 2725 //@{ 2726 CK_i586, 2727 CK_Pentium, 2728 CK_PentiumMMX, 2729 //@} 2730 2731 /// \name i686 2732 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2733 //@{ 2734 CK_i686, 2735 CK_PentiumPro, 2736 CK_Pentium2, 2737 CK_Pentium3, 2738 CK_Pentium3M, 2739 CK_PentiumM, 2740 CK_C3_2, 2741 2742 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2743 /// Clang however has some logic to support this. 2744 // FIXME: Warn, deprecate, and potentially remove this. 2745 CK_Yonah, 2746 //@} 2747 2748 /// \name Netburst 2749 /// Netburst microarchitecture based processors. 2750 //@{ 2751 CK_Pentium4, 2752 CK_Pentium4M, 2753 CK_Prescott, 2754 CK_Nocona, 2755 //@} 2756 2757 /// \name Core 2758 /// Core microarchitecture based processors. 2759 //@{ 2760 CK_Core2, 2761 2762 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2763 /// codename which GCC no longer accepts as an option to -march, but Clang 2764 /// has some logic for recognizing it. 2765 // FIXME: Warn, deprecate, and potentially remove this. 2766 CK_Penryn, 2767 //@} 2768 2769 /// \name Atom 2770 /// Atom processors 2771 //@{ 2772 CK_Bonnell, 2773 CK_Silvermont, 2774 CK_Goldmont, 2775 //@} 2776 2777 /// \name Nehalem 2778 /// Nehalem microarchitecture based processors. 2779 CK_Nehalem, 2780 2781 /// \name Westmere 2782 /// Westmere microarchitecture based processors. 2783 CK_Westmere, 2784 2785 /// \name Sandy Bridge 2786 /// Sandy Bridge microarchitecture based processors. 2787 CK_SandyBridge, 2788 2789 /// \name Ivy Bridge 2790 /// Ivy Bridge microarchitecture based processors. 2791 CK_IvyBridge, 2792 2793 /// \name Haswell 2794 /// Haswell microarchitecture based processors. 2795 CK_Haswell, 2796 2797 /// \name Broadwell 2798 /// Broadwell microarchitecture based processors. 2799 CK_Broadwell, 2800 2801 /// \name Skylake Client 2802 /// Skylake client microarchitecture based processors. 2803 CK_SkylakeClient, 2804 2805 /// \name Skylake Server 2806 /// Skylake server microarchitecture based processors. 2807 CK_SkylakeServer, 2808 2809 /// \name Cannonlake Client 2810 /// Cannonlake client microarchitecture based processors. 2811 CK_Cannonlake, 2812 2813 /// \name Knights Landing 2814 /// Knights Landing processor. 2815 CK_KNL, 2816 2817 /// \name Lakemont 2818 /// Lakemont microarchitecture based processors. 2819 CK_Lakemont, 2820 2821 /// \name K6 2822 /// K6 architecture processors. 2823 //@{ 2824 CK_K6, 2825 CK_K6_2, 2826 CK_K6_3, 2827 //@} 2828 2829 /// \name K7 2830 /// K7 architecture processors. 2831 //@{ 2832 CK_Athlon, 2833 CK_AthlonThunderbird, 2834 CK_Athlon4, 2835 CK_AthlonXP, 2836 CK_AthlonMP, 2837 //@} 2838 2839 /// \name K8 2840 /// K8 architecture processors. 2841 //@{ 2842 CK_Athlon64, 2843 CK_Athlon64SSE3, 2844 CK_AthlonFX, 2845 CK_K8, 2846 CK_K8SSE3, 2847 CK_Opteron, 2848 CK_OpteronSSE3, 2849 CK_AMDFAM10, 2850 //@} 2851 2852 /// \name Bobcat 2853 /// Bobcat architecture processors. 2854 //@{ 2855 CK_BTVER1, 2856 CK_BTVER2, 2857 //@} 2858 2859 /// \name Bulldozer 2860 /// Bulldozer architecture processors. 2861 //@{ 2862 CK_BDVER1, 2863 CK_BDVER2, 2864 CK_BDVER3, 2865 CK_BDVER4, 2866 //@} 2867 2868 /// \name zen 2869 /// Zen architecture processors. 2870 //@{ 2871 CK_ZNVER1, 2872 //@} 2873 2874 /// This specification is deprecated and will be removed in the future. 2875 /// Users should prefer \see CK_K8. 2876 // FIXME: Warn on this when the CPU is set to it. 2877 //@{ 2878 CK_x86_64, 2879 //@} 2880 2881 /// \name Geode 2882 /// Geode processors. 2883 //@{ 2884 CK_Geode 2885 //@} 2886 } CPU = CK_Generic; 2887 2888 bool checkCPUKind(CPUKind Kind) const { 2889 // Perform any per-CPU checks necessary to determine if this CPU is 2890 // acceptable. 2891 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2892 // invalid without explaining *why*. 2893 switch (Kind) { 2894 case CK_Generic: 2895 // No processor selected! 2896 return false; 2897 2898 case CK_i386: 2899 case CK_i486: 2900 case CK_WinChipC6: 2901 case CK_WinChip2: 2902 case CK_C3: 2903 case CK_i586: 2904 case CK_Pentium: 2905 case CK_PentiumMMX: 2906 case CK_i686: 2907 case CK_PentiumPro: 2908 case CK_Pentium2: 2909 case CK_Pentium3: 2910 case CK_Pentium3M: 2911 case CK_PentiumM: 2912 case CK_Yonah: 2913 case CK_C3_2: 2914 case CK_Pentium4: 2915 case CK_Pentium4M: 2916 case CK_Lakemont: 2917 case CK_Prescott: 2918 case CK_K6: 2919 case CK_K6_2: 2920 case CK_K6_3: 2921 case CK_Athlon: 2922 case CK_AthlonThunderbird: 2923 case CK_Athlon4: 2924 case CK_AthlonXP: 2925 case CK_AthlonMP: 2926 case CK_Geode: 2927 // Only accept certain architectures when compiling in 32-bit mode. 2928 if (getTriple().getArch() != llvm::Triple::x86) 2929 return false; 2930 2931 LLVM_FALLTHROUGH; 2932 case CK_Nocona: 2933 case CK_Core2: 2934 case CK_Penryn: 2935 case CK_Bonnell: 2936 case CK_Silvermont: 2937 case CK_Goldmont: 2938 case CK_Nehalem: 2939 case CK_Westmere: 2940 case CK_SandyBridge: 2941 case CK_IvyBridge: 2942 case CK_Haswell: 2943 case CK_Broadwell: 2944 case CK_SkylakeClient: 2945 case CK_SkylakeServer: 2946 case CK_Cannonlake: 2947 case CK_KNL: 2948 case CK_Athlon64: 2949 case CK_Athlon64SSE3: 2950 case CK_AthlonFX: 2951 case CK_K8: 2952 case CK_K8SSE3: 2953 case CK_Opteron: 2954 case CK_OpteronSSE3: 2955 case CK_AMDFAM10: 2956 case CK_BTVER1: 2957 case CK_BTVER2: 2958 case CK_BDVER1: 2959 case CK_BDVER2: 2960 case CK_BDVER3: 2961 case CK_BDVER4: 2962 case CK_ZNVER1: 2963 case CK_x86_64: 2964 return true; 2965 } 2966 llvm_unreachable("Unhandled CPU kind"); 2967 } 2968 2969 CPUKind getCPUKind(StringRef CPU) const { 2970 return llvm::StringSwitch<CPUKind>(CPU) 2971 .Case("i386", CK_i386) 2972 .Case("i486", CK_i486) 2973 .Case("winchip-c6", CK_WinChipC6) 2974 .Case("winchip2", CK_WinChip2) 2975 .Case("c3", CK_C3) 2976 .Case("i586", CK_i586) 2977 .Case("pentium", CK_Pentium) 2978 .Case("pentium-mmx", CK_PentiumMMX) 2979 .Case("i686", CK_i686) 2980 .Case("pentiumpro", CK_PentiumPro) 2981 .Case("pentium2", CK_Pentium2) 2982 .Case("pentium3", CK_Pentium3) 2983 .Case("pentium3m", CK_Pentium3M) 2984 .Case("pentium-m", CK_PentiumM) 2985 .Case("c3-2", CK_C3_2) 2986 .Case("yonah", CK_Yonah) 2987 .Case("pentium4", CK_Pentium4) 2988 .Case("pentium4m", CK_Pentium4M) 2989 .Case("prescott", CK_Prescott) 2990 .Case("nocona", CK_Nocona) 2991 .Case("core2", CK_Core2) 2992 .Case("penryn", CK_Penryn) 2993 .Case("bonnell", CK_Bonnell) 2994 .Case("atom", CK_Bonnell) // Legacy name. 2995 .Case("silvermont", CK_Silvermont) 2996 .Case("slm", CK_Silvermont) // Legacy name. 2997 .Case("goldmont", CK_Goldmont) 2998 .Case("nehalem", CK_Nehalem) 2999 .Case("corei7", CK_Nehalem) // Legacy name. 3000 .Case("westmere", CK_Westmere) 3001 .Case("sandybridge", CK_SandyBridge) 3002 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 3003 .Case("ivybridge", CK_IvyBridge) 3004 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 3005 .Case("haswell", CK_Haswell) 3006 .Case("core-avx2", CK_Haswell) // Legacy name. 3007 .Case("broadwell", CK_Broadwell) 3008 .Case("skylake", CK_SkylakeClient) 3009 .Case("skylake-avx512", CK_SkylakeServer) 3010 .Case("skx", CK_SkylakeServer) // Legacy name. 3011 .Case("cannonlake", CK_Cannonlake) 3012 .Case("knl", CK_KNL) 3013 .Case("lakemont", CK_Lakemont) 3014 .Case("k6", CK_K6) 3015 .Case("k6-2", CK_K6_2) 3016 .Case("k6-3", CK_K6_3) 3017 .Case("athlon", CK_Athlon) 3018 .Case("athlon-tbird", CK_AthlonThunderbird) 3019 .Case("athlon-4", CK_Athlon4) 3020 .Case("athlon-xp", CK_AthlonXP) 3021 .Case("athlon-mp", CK_AthlonMP) 3022 .Case("athlon64", CK_Athlon64) 3023 .Case("athlon64-sse3", CK_Athlon64SSE3) 3024 .Case("athlon-fx", CK_AthlonFX) 3025 .Case("k8", CK_K8) 3026 .Case("k8-sse3", CK_K8SSE3) 3027 .Case("opteron", CK_Opteron) 3028 .Case("opteron-sse3", CK_OpteronSSE3) 3029 .Case("barcelona", CK_AMDFAM10) 3030 .Case("amdfam10", CK_AMDFAM10) 3031 .Case("btver1", CK_BTVER1) 3032 .Case("btver2", CK_BTVER2) 3033 .Case("bdver1", CK_BDVER1) 3034 .Case("bdver2", CK_BDVER2) 3035 .Case("bdver3", CK_BDVER3) 3036 .Case("bdver4", CK_BDVER4) 3037 .Case("znver1", CK_ZNVER1) 3038 .Case("x86-64", CK_x86_64) 3039 .Case("geode", CK_Geode) 3040 .Default(CK_Generic); 3041 } 3042 3043 enum FPMathKind { 3044 FP_Default, 3045 FP_SSE, 3046 FP_387 3047 } FPMath = FP_Default; 3048 3049 public: 3050 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 3051 : TargetInfo(Triple) { 3052 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 3053 } 3054 unsigned getFloatEvalMethod() const override { 3055 // X87 evaluates with 80 bits "long double" precision. 3056 return SSELevel == NoSSE ? 2 : 0; 3057 } 3058 ArrayRef<const char *> getGCCRegNames() const override { 3059 return llvm::makeArrayRef(GCCRegNames); 3060 } 3061 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 3062 return None; 3063 } 3064 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 3065 return llvm::makeArrayRef(AddlRegNames); 3066 } 3067 bool validateCpuSupports(StringRef Name) const override; 3068 bool validateAsmConstraint(const char *&Name, 3069 TargetInfo::ConstraintInfo &info) const override; 3070 3071 bool validateGlobalRegisterVariable(StringRef RegName, 3072 unsigned RegSize, 3073 bool &HasSizeMismatch) const override { 3074 // esp and ebp are the only 32-bit registers the x86 backend can currently 3075 // handle. 3076 if (RegName.equals("esp") || RegName.equals("ebp")) { 3077 // Check that the register size is 32-bit. 3078 HasSizeMismatch = RegSize != 32; 3079 return true; 3080 } 3081 3082 return false; 3083 } 3084 3085 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 3086 3087 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 3088 3089 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 3090 3091 std::string convertConstraint(const char *&Constraint) const override; 3092 const char *getClobbers() const override { 3093 return "~{dirflag},~{fpsr},~{flags}"; 3094 } 3095 3096 StringRef getConstraintRegister(const StringRef &Constraint, 3097 const StringRef &Expression) const override { 3098 StringRef::iterator I, E; 3099 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 3100 if (isalpha(*I)) 3101 break; 3102 } 3103 if (I == E) 3104 return ""; 3105 switch (*I) { 3106 // For the register constraints, return the matching register name 3107 case 'a': 3108 return "ax"; 3109 case 'b': 3110 return "bx"; 3111 case 'c': 3112 return "cx"; 3113 case 'd': 3114 return "dx"; 3115 case 'S': 3116 return "si"; 3117 case 'D': 3118 return "di"; 3119 // In case the constraint is 'r' we need to return Expression 3120 case 'r': 3121 return Expression; 3122 default: 3123 // Default value if there is no constraint for the register 3124 return ""; 3125 } 3126 return ""; 3127 } 3128 3129 void getTargetDefines(const LangOptions &Opts, 3130 MacroBuilder &Builder) const override; 3131 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3132 bool Enabled); 3133 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3134 bool Enabled); 3135 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3136 bool Enabled); 3137 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3138 StringRef Name, bool Enabled) const override { 3139 setFeatureEnabledImpl(Features, Name, Enabled); 3140 } 3141 // This exists purely to cut down on the number of virtual calls in 3142 // initFeatureMap which calls this repeatedly. 3143 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3144 StringRef Name, bool Enabled); 3145 bool 3146 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3147 StringRef CPU, 3148 const std::vector<std::string> &FeaturesVec) const override; 3149 bool isValidFeatureName(StringRef Name) const override; 3150 bool hasFeature(StringRef Feature) const override; 3151 bool handleTargetFeatures(std::vector<std::string> &Features, 3152 DiagnosticsEngine &Diags) override; 3153 StringRef getABI() const override { 3154 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3155 return "avx512"; 3156 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3157 return "avx"; 3158 if (getTriple().getArch() == llvm::Triple::x86 && 3159 MMX3DNowLevel == NoMMX3DNow) 3160 return "no-mmx"; 3161 return ""; 3162 } 3163 3164 bool isValidCPUName(StringRef Name) const override { 3165 return checkCPUKind(getCPUKind(Name)); 3166 } 3167 3168 bool setCPU(const std::string &Name) override { 3169 return checkCPUKind(CPU = getCPUKind(Name)); 3170 } 3171 3172 bool setFPMath(StringRef Name) override; 3173 3174 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3175 // Most of the non-ARM calling conventions are i386 conventions. 3176 switch (CC) { 3177 case CC_X86ThisCall: 3178 case CC_X86FastCall: 3179 case CC_X86StdCall: 3180 case CC_X86VectorCall: 3181 case CC_X86RegCall: 3182 case CC_C: 3183 case CC_Swift: 3184 case CC_X86Pascal: 3185 case CC_IntelOclBicc: 3186 case CC_OpenCLKernel: 3187 return CCCR_OK; 3188 default: 3189 return CCCR_Warning; 3190 } 3191 } 3192 3193 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3194 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3195 } 3196 3197 bool hasSjLjLowering() const override { 3198 return true; 3199 } 3200 3201 void setSupportedOpenCLOpts() override { 3202 getSupportedOpenCLOpts().supportAll(); 3203 } 3204 }; 3205 3206 bool X86TargetInfo::setFPMath(StringRef Name) { 3207 if (Name == "387") { 3208 FPMath = FP_387; 3209 return true; 3210 } 3211 if (Name == "sse") { 3212 FPMath = FP_SSE; 3213 return true; 3214 } 3215 return false; 3216 } 3217 3218 bool X86TargetInfo::initFeatureMap( 3219 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3220 const std::vector<std::string> &FeaturesVec) const { 3221 // FIXME: This *really* should not be here. 3222 // X86_64 always has SSE2. 3223 if (getTriple().getArch() == llvm::Triple::x86_64) 3224 setFeatureEnabledImpl(Features, "sse2", true); 3225 3226 const CPUKind Kind = getCPUKind(CPU); 3227 3228 // Enable X87 for all X86 processors but Lakemont. 3229 if (Kind != CK_Lakemont) 3230 setFeatureEnabledImpl(Features, "x87", true); 3231 3232 switch (Kind) { 3233 case CK_Generic: 3234 case CK_i386: 3235 case CK_i486: 3236 case CK_i586: 3237 case CK_Pentium: 3238 case CK_i686: 3239 case CK_PentiumPro: 3240 case CK_Lakemont: 3241 break; 3242 case CK_PentiumMMX: 3243 case CK_Pentium2: 3244 case CK_K6: 3245 case CK_WinChipC6: 3246 setFeatureEnabledImpl(Features, "mmx", true); 3247 break; 3248 case CK_Pentium3: 3249 case CK_Pentium3M: 3250 case CK_C3_2: 3251 setFeatureEnabledImpl(Features, "sse", true); 3252 setFeatureEnabledImpl(Features, "fxsr", true); 3253 break; 3254 case CK_PentiumM: 3255 case CK_Pentium4: 3256 case CK_Pentium4M: 3257 case CK_x86_64: 3258 setFeatureEnabledImpl(Features, "sse2", true); 3259 setFeatureEnabledImpl(Features, "fxsr", true); 3260 break; 3261 case CK_Yonah: 3262 case CK_Prescott: 3263 case CK_Nocona: 3264 setFeatureEnabledImpl(Features, "sse3", true); 3265 setFeatureEnabledImpl(Features, "fxsr", true); 3266 setFeatureEnabledImpl(Features, "cx16", true); 3267 break; 3268 case CK_Core2: 3269 setFeatureEnabledImpl(Features, "ssse3", true); 3270 setFeatureEnabledImpl(Features, "fxsr", true); 3271 setFeatureEnabledImpl(Features, "cx16", true); 3272 break; 3273 case CK_Penryn: 3274 setFeatureEnabledImpl(Features, "sse4.1", true); 3275 setFeatureEnabledImpl(Features, "fxsr", true); 3276 setFeatureEnabledImpl(Features, "cx16", true); 3277 break; 3278 case CK_Cannonlake: 3279 setFeatureEnabledImpl(Features, "avx512ifma", true); 3280 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3281 setFeatureEnabledImpl(Features, "sha", true); 3282 LLVM_FALLTHROUGH; 3283 case CK_SkylakeServer: 3284 setFeatureEnabledImpl(Features, "avx512f", true); 3285 setFeatureEnabledImpl(Features, "avx512cd", true); 3286 setFeatureEnabledImpl(Features, "avx512dq", true); 3287 setFeatureEnabledImpl(Features, "avx512bw", true); 3288 setFeatureEnabledImpl(Features, "avx512vl", true); 3289 setFeatureEnabledImpl(Features, "pku", true); 3290 setFeatureEnabledImpl(Features, "clwb", true); 3291 LLVM_FALLTHROUGH; 3292 case CK_SkylakeClient: 3293 setFeatureEnabledImpl(Features, "xsavec", true); 3294 setFeatureEnabledImpl(Features, "xsaves", true); 3295 setFeatureEnabledImpl(Features, "mpx", true); 3296 setFeatureEnabledImpl(Features, "sgx", true); 3297 setFeatureEnabledImpl(Features, "clflushopt", true); 3298 setFeatureEnabledImpl(Features, "rtm", true); 3299 LLVM_FALLTHROUGH; 3300 case CK_Broadwell: 3301 setFeatureEnabledImpl(Features, "rdseed", true); 3302 setFeatureEnabledImpl(Features, "adx", true); 3303 LLVM_FALLTHROUGH; 3304 case CK_Haswell: 3305 setFeatureEnabledImpl(Features, "avx2", true); 3306 setFeatureEnabledImpl(Features, "lzcnt", true); 3307 setFeatureEnabledImpl(Features, "bmi", true); 3308 setFeatureEnabledImpl(Features, "bmi2", true); 3309 setFeatureEnabledImpl(Features, "fma", true); 3310 setFeatureEnabledImpl(Features, "movbe", true); 3311 LLVM_FALLTHROUGH; 3312 case CK_IvyBridge: 3313 setFeatureEnabledImpl(Features, "rdrnd", true); 3314 setFeatureEnabledImpl(Features, "f16c", true); 3315 setFeatureEnabledImpl(Features, "fsgsbase", true); 3316 LLVM_FALLTHROUGH; 3317 case CK_SandyBridge: 3318 setFeatureEnabledImpl(Features, "avx", true); 3319 setFeatureEnabledImpl(Features, "xsave", true); 3320 setFeatureEnabledImpl(Features, "xsaveopt", true); 3321 LLVM_FALLTHROUGH; 3322 case CK_Westmere: 3323 setFeatureEnabledImpl(Features, "aes", true); 3324 setFeatureEnabledImpl(Features, "pclmul", true); 3325 LLVM_FALLTHROUGH; 3326 case CK_Nehalem: 3327 setFeatureEnabledImpl(Features, "sse4.2", true); 3328 setFeatureEnabledImpl(Features, "fxsr", true); 3329 setFeatureEnabledImpl(Features, "cx16", true); 3330 break; 3331 case CK_Goldmont: 3332 setFeatureEnabledImpl(Features, "sha", true); 3333 setFeatureEnabledImpl(Features, "rdrnd", true); 3334 setFeatureEnabledImpl(Features, "rdseed", true); 3335 setFeatureEnabledImpl(Features, "xsave", true); 3336 setFeatureEnabledImpl(Features, "xsaveopt", true); 3337 setFeatureEnabledImpl(Features, "xsavec", true); 3338 setFeatureEnabledImpl(Features, "xsaves", true); 3339 setFeatureEnabledImpl(Features, "clflushopt", true); 3340 setFeatureEnabledImpl(Features, "mpx", true); 3341 LLVM_FALLTHROUGH; 3342 case CK_Silvermont: 3343 setFeatureEnabledImpl(Features, "aes", true); 3344 setFeatureEnabledImpl(Features, "pclmul", true); 3345 setFeatureEnabledImpl(Features, "sse4.2", true); 3346 LLVM_FALLTHROUGH; 3347 case CK_Bonnell: 3348 setFeatureEnabledImpl(Features, "movbe", true); 3349 setFeatureEnabledImpl(Features, "ssse3", true); 3350 setFeatureEnabledImpl(Features, "fxsr", true); 3351 setFeatureEnabledImpl(Features, "cx16", true); 3352 break; 3353 case CK_KNL: 3354 setFeatureEnabledImpl(Features, "avx512f", true); 3355 setFeatureEnabledImpl(Features, "avx512cd", true); 3356 setFeatureEnabledImpl(Features, "avx512er", true); 3357 setFeatureEnabledImpl(Features, "avx512pf", true); 3358 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3359 setFeatureEnabledImpl(Features, "fxsr", true); 3360 setFeatureEnabledImpl(Features, "rdseed", true); 3361 setFeatureEnabledImpl(Features, "adx", true); 3362 setFeatureEnabledImpl(Features, "lzcnt", true); 3363 setFeatureEnabledImpl(Features, "bmi", true); 3364 setFeatureEnabledImpl(Features, "bmi2", true); 3365 setFeatureEnabledImpl(Features, "rtm", true); 3366 setFeatureEnabledImpl(Features, "fma", true); 3367 setFeatureEnabledImpl(Features, "rdrnd", true); 3368 setFeatureEnabledImpl(Features, "f16c", true); 3369 setFeatureEnabledImpl(Features, "fsgsbase", true); 3370 setFeatureEnabledImpl(Features, "aes", true); 3371 setFeatureEnabledImpl(Features, "pclmul", true); 3372 setFeatureEnabledImpl(Features, "cx16", true); 3373 setFeatureEnabledImpl(Features, "xsaveopt", true); 3374 setFeatureEnabledImpl(Features, "xsave", true); 3375 setFeatureEnabledImpl(Features, "movbe", true); 3376 break; 3377 case CK_K6_2: 3378 case CK_K6_3: 3379 case CK_WinChip2: 3380 case CK_C3: 3381 setFeatureEnabledImpl(Features, "3dnow", true); 3382 break; 3383 case CK_Athlon: 3384 case CK_AthlonThunderbird: 3385 case CK_Geode: 3386 setFeatureEnabledImpl(Features, "3dnowa", true); 3387 break; 3388 case CK_Athlon4: 3389 case CK_AthlonXP: 3390 case CK_AthlonMP: 3391 setFeatureEnabledImpl(Features, "sse", true); 3392 setFeatureEnabledImpl(Features, "3dnowa", true); 3393 setFeatureEnabledImpl(Features, "fxsr", true); 3394 break; 3395 case CK_K8: 3396 case CK_Opteron: 3397 case CK_Athlon64: 3398 case CK_AthlonFX: 3399 setFeatureEnabledImpl(Features, "sse2", true); 3400 setFeatureEnabledImpl(Features, "3dnowa", true); 3401 setFeatureEnabledImpl(Features, "fxsr", true); 3402 break; 3403 case CK_AMDFAM10: 3404 setFeatureEnabledImpl(Features, "sse4a", true); 3405 setFeatureEnabledImpl(Features, "lzcnt", true); 3406 setFeatureEnabledImpl(Features, "popcnt", true); 3407 LLVM_FALLTHROUGH; 3408 case CK_K8SSE3: 3409 case CK_OpteronSSE3: 3410 case CK_Athlon64SSE3: 3411 setFeatureEnabledImpl(Features, "sse3", true); 3412 setFeatureEnabledImpl(Features, "3dnowa", true); 3413 setFeatureEnabledImpl(Features, "fxsr", true); 3414 break; 3415 case CK_BTVER2: 3416 setFeatureEnabledImpl(Features, "avx", true); 3417 setFeatureEnabledImpl(Features, "aes", true); 3418 setFeatureEnabledImpl(Features, "pclmul", true); 3419 setFeatureEnabledImpl(Features, "bmi", true); 3420 setFeatureEnabledImpl(Features, "f16c", true); 3421 setFeatureEnabledImpl(Features, "xsaveopt", true); 3422 setFeatureEnabledImpl(Features, "movbe", true); 3423 LLVM_FALLTHROUGH; 3424 case CK_BTVER1: 3425 setFeatureEnabledImpl(Features, "ssse3", true); 3426 setFeatureEnabledImpl(Features, "sse4a", true); 3427 setFeatureEnabledImpl(Features, "lzcnt", true); 3428 setFeatureEnabledImpl(Features, "popcnt", true); 3429 setFeatureEnabledImpl(Features, "prfchw", true); 3430 setFeatureEnabledImpl(Features, "cx16", true); 3431 setFeatureEnabledImpl(Features, "fxsr", true); 3432 break; 3433 case CK_ZNVER1: 3434 setFeatureEnabledImpl(Features, "adx", true); 3435 setFeatureEnabledImpl(Features, "aes", true); 3436 setFeatureEnabledImpl(Features, "avx2", true); 3437 setFeatureEnabledImpl(Features, "bmi", true); 3438 setFeatureEnabledImpl(Features, "bmi2", true); 3439 setFeatureEnabledImpl(Features, "clflushopt", true); 3440 setFeatureEnabledImpl(Features, "clzero", true); 3441 setFeatureEnabledImpl(Features, "cx16", true); 3442 setFeatureEnabledImpl(Features, "f16c", true); 3443 setFeatureEnabledImpl(Features, "fma", true); 3444 setFeatureEnabledImpl(Features, "fsgsbase", true); 3445 setFeatureEnabledImpl(Features, "fxsr", true); 3446 setFeatureEnabledImpl(Features, "lzcnt", true); 3447 setFeatureEnabledImpl(Features, "mwaitx", true); 3448 setFeatureEnabledImpl(Features, "movbe", true); 3449 setFeatureEnabledImpl(Features, "pclmul", true); 3450 setFeatureEnabledImpl(Features, "popcnt", true); 3451 setFeatureEnabledImpl(Features, "prfchw", true); 3452 setFeatureEnabledImpl(Features, "rdrnd", true); 3453 setFeatureEnabledImpl(Features, "rdseed", true); 3454 setFeatureEnabledImpl(Features, "sha", true); 3455 setFeatureEnabledImpl(Features, "sse4a", true); 3456 setFeatureEnabledImpl(Features, "xsave", true); 3457 setFeatureEnabledImpl(Features, "xsavec", true); 3458 setFeatureEnabledImpl(Features, "xsaveopt", true); 3459 setFeatureEnabledImpl(Features, "xsaves", true); 3460 break; 3461 case CK_BDVER4: 3462 setFeatureEnabledImpl(Features, "avx2", true); 3463 setFeatureEnabledImpl(Features, "bmi2", true); 3464 setFeatureEnabledImpl(Features, "mwaitx", true); 3465 LLVM_FALLTHROUGH; 3466 case CK_BDVER3: 3467 setFeatureEnabledImpl(Features, "fsgsbase", true); 3468 setFeatureEnabledImpl(Features, "xsaveopt", true); 3469 LLVM_FALLTHROUGH; 3470 case CK_BDVER2: 3471 setFeatureEnabledImpl(Features, "bmi", true); 3472 setFeatureEnabledImpl(Features, "fma", true); 3473 setFeatureEnabledImpl(Features, "f16c", true); 3474 setFeatureEnabledImpl(Features, "tbm", true); 3475 LLVM_FALLTHROUGH; 3476 case CK_BDVER1: 3477 // xop implies avx, sse4a and fma4. 3478 setFeatureEnabledImpl(Features, "xop", true); 3479 setFeatureEnabledImpl(Features, "lwp", true); 3480 setFeatureEnabledImpl(Features, "lzcnt", true); 3481 setFeatureEnabledImpl(Features, "aes", true); 3482 setFeatureEnabledImpl(Features, "pclmul", true); 3483 setFeatureEnabledImpl(Features, "prfchw", true); 3484 setFeatureEnabledImpl(Features, "cx16", true); 3485 setFeatureEnabledImpl(Features, "fxsr", true); 3486 setFeatureEnabledImpl(Features, "xsave", true); 3487 break; 3488 } 3489 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3490 return false; 3491 3492 // Can't do this earlier because we need to be able to explicitly enable 3493 // or disable these features and the things that they depend upon. 3494 3495 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3496 auto I = Features.find("sse4.2"); 3497 if (I != Features.end() && I->getValue() && 3498 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3499 FeaturesVec.end()) 3500 Features["popcnt"] = true; 3501 3502 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3503 I = Features.find("3dnow"); 3504 if (I != Features.end() && I->getValue() && 3505 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3506 FeaturesVec.end()) 3507 Features["prfchw"] = true; 3508 3509 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3510 // then enable MMX. 3511 I = Features.find("sse"); 3512 if (I != Features.end() && I->getValue() && 3513 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3514 FeaturesVec.end()) 3515 Features["mmx"] = true; 3516 3517 return true; 3518 } 3519 3520 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3521 X86SSEEnum Level, bool Enabled) { 3522 if (Enabled) { 3523 switch (Level) { 3524 case AVX512F: 3525 Features["avx512f"] = true; 3526 LLVM_FALLTHROUGH; 3527 case AVX2: 3528 Features["avx2"] = true; 3529 LLVM_FALLTHROUGH; 3530 case AVX: 3531 Features["avx"] = true; 3532 Features["xsave"] = true; 3533 LLVM_FALLTHROUGH; 3534 case SSE42: 3535 Features["sse4.2"] = true; 3536 LLVM_FALLTHROUGH; 3537 case SSE41: 3538 Features["sse4.1"] = true; 3539 LLVM_FALLTHROUGH; 3540 case SSSE3: 3541 Features["ssse3"] = true; 3542 LLVM_FALLTHROUGH; 3543 case SSE3: 3544 Features["sse3"] = true; 3545 LLVM_FALLTHROUGH; 3546 case SSE2: 3547 Features["sse2"] = true; 3548 LLVM_FALLTHROUGH; 3549 case SSE1: 3550 Features["sse"] = true; 3551 LLVM_FALLTHROUGH; 3552 case NoSSE: 3553 break; 3554 } 3555 return; 3556 } 3557 3558 switch (Level) { 3559 case NoSSE: 3560 case SSE1: 3561 Features["sse"] = false; 3562 LLVM_FALLTHROUGH; 3563 case SSE2: 3564 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3565 Features["sha"] = false; 3566 LLVM_FALLTHROUGH; 3567 case SSE3: 3568 Features["sse3"] = false; 3569 setXOPLevel(Features, NoXOP, false); 3570 LLVM_FALLTHROUGH; 3571 case SSSE3: 3572 Features["ssse3"] = false; 3573 LLVM_FALLTHROUGH; 3574 case SSE41: 3575 Features["sse4.1"] = false; 3576 LLVM_FALLTHROUGH; 3577 case SSE42: 3578 Features["sse4.2"] = false; 3579 LLVM_FALLTHROUGH; 3580 case AVX: 3581 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3582 Features["xsaveopt"] = false; 3583 setXOPLevel(Features, FMA4, false); 3584 LLVM_FALLTHROUGH; 3585 case AVX2: 3586 Features["avx2"] = false; 3587 LLVM_FALLTHROUGH; 3588 case AVX512F: 3589 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3590 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3591 Features["avx512vl"] = Features["avx512vbmi"] = 3592 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3593 break; 3594 } 3595 } 3596 3597 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3598 MMX3DNowEnum Level, bool Enabled) { 3599 if (Enabled) { 3600 switch (Level) { 3601 case AMD3DNowAthlon: 3602 Features["3dnowa"] = true; 3603 LLVM_FALLTHROUGH; 3604 case AMD3DNow: 3605 Features["3dnow"] = true; 3606 LLVM_FALLTHROUGH; 3607 case MMX: 3608 Features["mmx"] = true; 3609 LLVM_FALLTHROUGH; 3610 case NoMMX3DNow: 3611 break; 3612 } 3613 return; 3614 } 3615 3616 switch (Level) { 3617 case NoMMX3DNow: 3618 case MMX: 3619 Features["mmx"] = false; 3620 LLVM_FALLTHROUGH; 3621 case AMD3DNow: 3622 Features["3dnow"] = false; 3623 LLVM_FALLTHROUGH; 3624 case AMD3DNowAthlon: 3625 Features["3dnowa"] = false; 3626 break; 3627 } 3628 } 3629 3630 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3631 bool Enabled) { 3632 if (Enabled) { 3633 switch (Level) { 3634 case XOP: 3635 Features["xop"] = true; 3636 LLVM_FALLTHROUGH; 3637 case FMA4: 3638 Features["fma4"] = true; 3639 setSSELevel(Features, AVX, true); 3640 LLVM_FALLTHROUGH; 3641 case SSE4A: 3642 Features["sse4a"] = true; 3643 setSSELevel(Features, SSE3, true); 3644 LLVM_FALLTHROUGH; 3645 case NoXOP: 3646 break; 3647 } 3648 return; 3649 } 3650 3651 switch (Level) { 3652 case NoXOP: 3653 case SSE4A: 3654 Features["sse4a"] = false; 3655 LLVM_FALLTHROUGH; 3656 case FMA4: 3657 Features["fma4"] = false; 3658 LLVM_FALLTHROUGH; 3659 case XOP: 3660 Features["xop"] = false; 3661 break; 3662 } 3663 } 3664 3665 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3666 StringRef Name, bool Enabled) { 3667 // This is a bit of a hack to deal with the sse4 target feature when used 3668 // as part of the target attribute. We handle sse4 correctly everywhere 3669 // else. See below for more information on how we handle the sse4 options. 3670 if (Name != "sse4") 3671 Features[Name] = Enabled; 3672 3673 if (Name == "mmx") { 3674 setMMXLevel(Features, MMX, Enabled); 3675 } else if (Name == "sse") { 3676 setSSELevel(Features, SSE1, Enabled); 3677 } else if (Name == "sse2") { 3678 setSSELevel(Features, SSE2, Enabled); 3679 } else if (Name == "sse3") { 3680 setSSELevel(Features, SSE3, Enabled); 3681 } else if (Name == "ssse3") { 3682 setSSELevel(Features, SSSE3, Enabled); 3683 } else if (Name == "sse4.2") { 3684 setSSELevel(Features, SSE42, Enabled); 3685 } else if (Name == "sse4.1") { 3686 setSSELevel(Features, SSE41, Enabled); 3687 } else if (Name == "3dnow") { 3688 setMMXLevel(Features, AMD3DNow, Enabled); 3689 } else if (Name == "3dnowa") { 3690 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3691 } else if (Name == "aes") { 3692 if (Enabled) 3693 setSSELevel(Features, SSE2, Enabled); 3694 } else if (Name == "pclmul") { 3695 if (Enabled) 3696 setSSELevel(Features, SSE2, Enabled); 3697 } else if (Name == "avx") { 3698 setSSELevel(Features, AVX, Enabled); 3699 } else if (Name == "avx2") { 3700 setSSELevel(Features, AVX2, Enabled); 3701 } else if (Name == "avx512f") { 3702 setSSELevel(Features, AVX512F, Enabled); 3703 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3704 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3705 Name == "avx512vbmi" || Name == "avx512ifma" || 3706 Name == "avx512vpopcntdq") { 3707 if (Enabled) 3708 setSSELevel(Features, AVX512F, Enabled); 3709 // Enable BWI instruction if VBMI is being enabled. 3710 if (Name == "avx512vbmi" && Enabled) 3711 Features["avx512bw"] = true; 3712 // Also disable VBMI if BWI is being disabled. 3713 if (Name == "avx512bw" && !Enabled) 3714 Features["avx512vbmi"] = false; 3715 } else if (Name == "fma") { 3716 if (Enabled) 3717 setSSELevel(Features, AVX, Enabled); 3718 } else if (Name == "fma4") { 3719 setXOPLevel(Features, FMA4, Enabled); 3720 } else if (Name == "xop") { 3721 setXOPLevel(Features, XOP, Enabled); 3722 } else if (Name == "sse4a") { 3723 setXOPLevel(Features, SSE4A, Enabled); 3724 } else if (Name == "f16c") { 3725 if (Enabled) 3726 setSSELevel(Features, AVX, Enabled); 3727 } else if (Name == "sha") { 3728 if (Enabled) 3729 setSSELevel(Features, SSE2, Enabled); 3730 } else if (Name == "sse4") { 3731 // We can get here via the __target__ attribute since that's not controlled 3732 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3733 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3734 // disabled. 3735 if (Enabled) 3736 setSSELevel(Features, SSE42, Enabled); 3737 else 3738 setSSELevel(Features, SSE41, Enabled); 3739 } else if (Name == "xsave") { 3740 if (!Enabled) 3741 Features["xsaveopt"] = false; 3742 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3743 if (Enabled) 3744 Features["xsave"] = true; 3745 } 3746 } 3747 3748 /// handleTargetFeatures - Perform initialization based on the user 3749 /// configured set of features. 3750 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3751 DiagnosticsEngine &Diags) { 3752 for (const auto &Feature : Features) { 3753 if (Feature[0] != '+') 3754 continue; 3755 3756 if (Feature == "+aes") { 3757 HasAES = true; 3758 } else if (Feature == "+pclmul") { 3759 HasPCLMUL = true; 3760 } else if (Feature == "+lzcnt") { 3761 HasLZCNT = true; 3762 } else if (Feature == "+rdrnd") { 3763 HasRDRND = true; 3764 } else if (Feature == "+fsgsbase") { 3765 HasFSGSBASE = true; 3766 } else if (Feature == "+bmi") { 3767 HasBMI = true; 3768 } else if (Feature == "+bmi2") { 3769 HasBMI2 = true; 3770 } else if (Feature == "+popcnt") { 3771 HasPOPCNT = true; 3772 } else if (Feature == "+rtm") { 3773 HasRTM = true; 3774 } else if (Feature == "+prfchw") { 3775 HasPRFCHW = true; 3776 } else if (Feature == "+rdseed") { 3777 HasRDSEED = true; 3778 } else if (Feature == "+adx") { 3779 HasADX = true; 3780 } else if (Feature == "+tbm") { 3781 HasTBM = true; 3782 } else if (Feature == "+lwp") { 3783 HasLWP = true; 3784 } else if (Feature == "+fma") { 3785 HasFMA = true; 3786 } else if (Feature == "+f16c") { 3787 HasF16C = true; 3788 } else if (Feature == "+avx512cd") { 3789 HasAVX512CD = true; 3790 } else if (Feature == "+avx512vpopcntdq") { 3791 HasAVX512VPOPCNTDQ = true; 3792 } else if (Feature == "+avx512er") { 3793 HasAVX512ER = true; 3794 } else if (Feature == "+avx512pf") { 3795 HasAVX512PF = true; 3796 } else if (Feature == "+avx512dq") { 3797 HasAVX512DQ = true; 3798 } else if (Feature == "+avx512bw") { 3799 HasAVX512BW = true; 3800 } else if (Feature == "+avx512vl") { 3801 HasAVX512VL = true; 3802 } else if (Feature == "+avx512vbmi") { 3803 HasAVX512VBMI = true; 3804 } else if (Feature == "+avx512ifma") { 3805 HasAVX512IFMA = true; 3806 } else if (Feature == "+sha") { 3807 HasSHA = true; 3808 } else if (Feature == "+mpx") { 3809 HasMPX = true; 3810 } else if (Feature == "+movbe") { 3811 HasMOVBE = true; 3812 } else if (Feature == "+sgx") { 3813 HasSGX = true; 3814 } else if (Feature == "+cx16") { 3815 HasCX16 = true; 3816 } else if (Feature == "+fxsr") { 3817 HasFXSR = true; 3818 } else if (Feature == "+xsave") { 3819 HasXSAVE = true; 3820 } else if (Feature == "+xsaveopt") { 3821 HasXSAVEOPT = true; 3822 } else if (Feature == "+xsavec") { 3823 HasXSAVEC = true; 3824 } else if (Feature == "+xsaves") { 3825 HasXSAVES = true; 3826 } else if (Feature == "+mwaitx") { 3827 HasMWAITX = true; 3828 } else if (Feature == "+pku") { 3829 HasPKU = true; 3830 } else if (Feature == "+clflushopt") { 3831 HasCLFLUSHOPT = true; 3832 } else if (Feature == "+clwb") { 3833 HasCLWB = true; 3834 } else if (Feature == "+prefetchwt1") { 3835 HasPREFETCHWT1 = true; 3836 } else if (Feature == "+clzero") { 3837 HasCLZERO = true; 3838 } 3839 3840 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3841 .Case("+avx512f", AVX512F) 3842 .Case("+avx2", AVX2) 3843 .Case("+avx", AVX) 3844 .Case("+sse4.2", SSE42) 3845 .Case("+sse4.1", SSE41) 3846 .Case("+ssse3", SSSE3) 3847 .Case("+sse3", SSE3) 3848 .Case("+sse2", SSE2) 3849 .Case("+sse", SSE1) 3850 .Default(NoSSE); 3851 SSELevel = std::max(SSELevel, Level); 3852 3853 MMX3DNowEnum ThreeDNowLevel = 3854 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3855 .Case("+3dnowa", AMD3DNowAthlon) 3856 .Case("+3dnow", AMD3DNow) 3857 .Case("+mmx", MMX) 3858 .Default(NoMMX3DNow); 3859 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3860 3861 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3862 .Case("+xop", XOP) 3863 .Case("+fma4", FMA4) 3864 .Case("+sse4a", SSE4A) 3865 .Default(NoXOP); 3866 XOPLevel = std::max(XOPLevel, XLevel); 3867 } 3868 3869 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3870 // matches the selected sse level. 3871 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3872 (FPMath == FP_387 && SSELevel >= SSE1)) { 3873 Diags.Report(diag::err_target_unsupported_fpmath) << 3874 (FPMath == FP_SSE ? "sse" : "387"); 3875 return false; 3876 } 3877 3878 SimdDefaultAlign = 3879 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3880 return true; 3881 } 3882 3883 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3884 /// definitions for this particular subtarget. 3885 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3886 MacroBuilder &Builder) const { 3887 // Target identification. 3888 if (getTriple().getArch() == llvm::Triple::x86_64) { 3889 Builder.defineMacro("__amd64__"); 3890 Builder.defineMacro("__amd64"); 3891 Builder.defineMacro("__x86_64"); 3892 Builder.defineMacro("__x86_64__"); 3893 if (getTriple().getArchName() == "x86_64h") { 3894 Builder.defineMacro("__x86_64h"); 3895 Builder.defineMacro("__x86_64h__"); 3896 } 3897 } else { 3898 DefineStd(Builder, "i386", Opts); 3899 } 3900 3901 // Subtarget options. 3902 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3903 // truly should be based on -mtune options. 3904 switch (CPU) { 3905 case CK_Generic: 3906 break; 3907 case CK_i386: 3908 // The rest are coming from the i386 define above. 3909 Builder.defineMacro("__tune_i386__"); 3910 break; 3911 case CK_i486: 3912 case CK_WinChipC6: 3913 case CK_WinChip2: 3914 case CK_C3: 3915 defineCPUMacros(Builder, "i486"); 3916 break; 3917 case CK_PentiumMMX: 3918 Builder.defineMacro("__pentium_mmx__"); 3919 Builder.defineMacro("__tune_pentium_mmx__"); 3920 LLVM_FALLTHROUGH; 3921 case CK_i586: 3922 case CK_Pentium: 3923 defineCPUMacros(Builder, "i586"); 3924 defineCPUMacros(Builder, "pentium"); 3925 break; 3926 case CK_Pentium3: 3927 case CK_Pentium3M: 3928 case CK_PentiumM: 3929 Builder.defineMacro("__tune_pentium3__"); 3930 LLVM_FALLTHROUGH; 3931 case CK_Pentium2: 3932 case CK_C3_2: 3933 Builder.defineMacro("__tune_pentium2__"); 3934 LLVM_FALLTHROUGH; 3935 case CK_PentiumPro: 3936 Builder.defineMacro("__tune_i686__"); 3937 Builder.defineMacro("__tune_pentiumpro__"); 3938 LLVM_FALLTHROUGH; 3939 case CK_i686: 3940 Builder.defineMacro("__i686"); 3941 Builder.defineMacro("__i686__"); 3942 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3943 Builder.defineMacro("__pentiumpro"); 3944 Builder.defineMacro("__pentiumpro__"); 3945 break; 3946 case CK_Pentium4: 3947 case CK_Pentium4M: 3948 defineCPUMacros(Builder, "pentium4"); 3949 break; 3950 case CK_Yonah: 3951 case CK_Prescott: 3952 case CK_Nocona: 3953 defineCPUMacros(Builder, "nocona"); 3954 break; 3955 case CK_Core2: 3956 case CK_Penryn: 3957 defineCPUMacros(Builder, "core2"); 3958 break; 3959 case CK_Bonnell: 3960 defineCPUMacros(Builder, "atom"); 3961 break; 3962 case CK_Silvermont: 3963 defineCPUMacros(Builder, "slm"); 3964 break; 3965 case CK_Goldmont: 3966 defineCPUMacros(Builder, "goldmont"); 3967 break; 3968 case CK_Nehalem: 3969 case CK_Westmere: 3970 case CK_SandyBridge: 3971 case CK_IvyBridge: 3972 case CK_Haswell: 3973 case CK_Broadwell: 3974 case CK_SkylakeClient: 3975 // FIXME: Historically, we defined this legacy name, it would be nice to 3976 // remove it at some point. We've never exposed fine-grained names for 3977 // recent primary x86 CPUs, and we should keep it that way. 3978 defineCPUMacros(Builder, "corei7"); 3979 break; 3980 case CK_SkylakeServer: 3981 defineCPUMacros(Builder, "skx"); 3982 break; 3983 case CK_Cannonlake: 3984 break; 3985 case CK_KNL: 3986 defineCPUMacros(Builder, "knl"); 3987 break; 3988 case CK_Lakemont: 3989 Builder.defineMacro("__tune_lakemont__"); 3990 break; 3991 case CK_K6_2: 3992 Builder.defineMacro("__k6_2__"); 3993 Builder.defineMacro("__tune_k6_2__"); 3994 LLVM_FALLTHROUGH; 3995 case CK_K6_3: 3996 if (CPU != CK_K6_2) { // In case of fallthrough 3997 // FIXME: GCC may be enabling these in cases where some other k6 3998 // architecture is specified but -m3dnow is explicitly provided. The 3999 // exact semantics need to be determined and emulated here. 4000 Builder.defineMacro("__k6_3__"); 4001 Builder.defineMacro("__tune_k6_3__"); 4002 } 4003 LLVM_FALLTHROUGH; 4004 case CK_K6: 4005 defineCPUMacros(Builder, "k6"); 4006 break; 4007 case CK_Athlon: 4008 case CK_AthlonThunderbird: 4009 case CK_Athlon4: 4010 case CK_AthlonXP: 4011 case CK_AthlonMP: 4012 defineCPUMacros(Builder, "athlon"); 4013 if (SSELevel != NoSSE) { 4014 Builder.defineMacro("__athlon_sse__"); 4015 Builder.defineMacro("__tune_athlon_sse__"); 4016 } 4017 break; 4018 case CK_K8: 4019 case CK_K8SSE3: 4020 case CK_x86_64: 4021 case CK_Opteron: 4022 case CK_OpteronSSE3: 4023 case CK_Athlon64: 4024 case CK_Athlon64SSE3: 4025 case CK_AthlonFX: 4026 defineCPUMacros(Builder, "k8"); 4027 break; 4028 case CK_AMDFAM10: 4029 defineCPUMacros(Builder, "amdfam10"); 4030 break; 4031 case CK_BTVER1: 4032 defineCPUMacros(Builder, "btver1"); 4033 break; 4034 case CK_BTVER2: 4035 defineCPUMacros(Builder, "btver2"); 4036 break; 4037 case CK_BDVER1: 4038 defineCPUMacros(Builder, "bdver1"); 4039 break; 4040 case CK_BDVER2: 4041 defineCPUMacros(Builder, "bdver2"); 4042 break; 4043 case CK_BDVER3: 4044 defineCPUMacros(Builder, "bdver3"); 4045 break; 4046 case CK_BDVER4: 4047 defineCPUMacros(Builder, "bdver4"); 4048 break; 4049 case CK_ZNVER1: 4050 defineCPUMacros(Builder, "znver1"); 4051 break; 4052 case CK_Geode: 4053 defineCPUMacros(Builder, "geode"); 4054 break; 4055 } 4056 4057 // Target properties. 4058 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4059 4060 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 4061 // functions in glibc header files that use FP Stack inline asm which the 4062 // backend can't deal with (PR879). 4063 Builder.defineMacro("__NO_MATH_INLINES"); 4064 4065 if (HasAES) 4066 Builder.defineMacro("__AES__"); 4067 4068 if (HasPCLMUL) 4069 Builder.defineMacro("__PCLMUL__"); 4070 4071 if (HasLZCNT) 4072 Builder.defineMacro("__LZCNT__"); 4073 4074 if (HasRDRND) 4075 Builder.defineMacro("__RDRND__"); 4076 4077 if (HasFSGSBASE) 4078 Builder.defineMacro("__FSGSBASE__"); 4079 4080 if (HasBMI) 4081 Builder.defineMacro("__BMI__"); 4082 4083 if (HasBMI2) 4084 Builder.defineMacro("__BMI2__"); 4085 4086 if (HasPOPCNT) 4087 Builder.defineMacro("__POPCNT__"); 4088 4089 if (HasRTM) 4090 Builder.defineMacro("__RTM__"); 4091 4092 if (HasPRFCHW) 4093 Builder.defineMacro("__PRFCHW__"); 4094 4095 if (HasRDSEED) 4096 Builder.defineMacro("__RDSEED__"); 4097 4098 if (HasADX) 4099 Builder.defineMacro("__ADX__"); 4100 4101 if (HasTBM) 4102 Builder.defineMacro("__TBM__"); 4103 4104 if (HasLWP) 4105 Builder.defineMacro("__LWP__"); 4106 4107 if (HasMWAITX) 4108 Builder.defineMacro("__MWAITX__"); 4109 4110 switch (XOPLevel) { 4111 case XOP: 4112 Builder.defineMacro("__XOP__"); 4113 LLVM_FALLTHROUGH; 4114 case FMA4: 4115 Builder.defineMacro("__FMA4__"); 4116 LLVM_FALLTHROUGH; 4117 case SSE4A: 4118 Builder.defineMacro("__SSE4A__"); 4119 LLVM_FALLTHROUGH; 4120 case NoXOP: 4121 break; 4122 } 4123 4124 if (HasFMA) 4125 Builder.defineMacro("__FMA__"); 4126 4127 if (HasF16C) 4128 Builder.defineMacro("__F16C__"); 4129 4130 if (HasAVX512CD) 4131 Builder.defineMacro("__AVX512CD__"); 4132 if (HasAVX512VPOPCNTDQ) 4133 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4134 if (HasAVX512ER) 4135 Builder.defineMacro("__AVX512ER__"); 4136 if (HasAVX512PF) 4137 Builder.defineMacro("__AVX512PF__"); 4138 if (HasAVX512DQ) 4139 Builder.defineMacro("__AVX512DQ__"); 4140 if (HasAVX512BW) 4141 Builder.defineMacro("__AVX512BW__"); 4142 if (HasAVX512VL) 4143 Builder.defineMacro("__AVX512VL__"); 4144 if (HasAVX512VBMI) 4145 Builder.defineMacro("__AVX512VBMI__"); 4146 if (HasAVX512IFMA) 4147 Builder.defineMacro("__AVX512IFMA__"); 4148 4149 if (HasSHA) 4150 Builder.defineMacro("__SHA__"); 4151 4152 if (HasFXSR) 4153 Builder.defineMacro("__FXSR__"); 4154 if (HasXSAVE) 4155 Builder.defineMacro("__XSAVE__"); 4156 if (HasXSAVEOPT) 4157 Builder.defineMacro("__XSAVEOPT__"); 4158 if (HasXSAVEC) 4159 Builder.defineMacro("__XSAVEC__"); 4160 if (HasXSAVES) 4161 Builder.defineMacro("__XSAVES__"); 4162 if (HasPKU) 4163 Builder.defineMacro("__PKU__"); 4164 if (HasCX16) 4165 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4166 if (HasCLFLUSHOPT) 4167 Builder.defineMacro("__CLFLUSHOPT__"); 4168 if (HasCLWB) 4169 Builder.defineMacro("__CLWB__"); 4170 if (HasMPX) 4171 Builder.defineMacro("__MPX__"); 4172 if (HasSGX) 4173 Builder.defineMacro("__SGX__"); 4174 if (HasPREFETCHWT1) 4175 Builder.defineMacro("__PREFETCHWT1__"); 4176 if (HasCLZERO) 4177 Builder.defineMacro("__CLZERO__"); 4178 4179 // Each case falls through to the previous one here. 4180 switch (SSELevel) { 4181 case AVX512F: 4182 Builder.defineMacro("__AVX512F__"); 4183 LLVM_FALLTHROUGH; 4184 case AVX2: 4185 Builder.defineMacro("__AVX2__"); 4186 LLVM_FALLTHROUGH; 4187 case AVX: 4188 Builder.defineMacro("__AVX__"); 4189 LLVM_FALLTHROUGH; 4190 case SSE42: 4191 Builder.defineMacro("__SSE4_2__"); 4192 LLVM_FALLTHROUGH; 4193 case SSE41: 4194 Builder.defineMacro("__SSE4_1__"); 4195 LLVM_FALLTHROUGH; 4196 case SSSE3: 4197 Builder.defineMacro("__SSSE3__"); 4198 LLVM_FALLTHROUGH; 4199 case SSE3: 4200 Builder.defineMacro("__SSE3__"); 4201 LLVM_FALLTHROUGH; 4202 case SSE2: 4203 Builder.defineMacro("__SSE2__"); 4204 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4205 LLVM_FALLTHROUGH; 4206 case SSE1: 4207 Builder.defineMacro("__SSE__"); 4208 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4209 LLVM_FALLTHROUGH; 4210 case NoSSE: 4211 break; 4212 } 4213 4214 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4215 switch (SSELevel) { 4216 case AVX512F: 4217 case AVX2: 4218 case AVX: 4219 case SSE42: 4220 case SSE41: 4221 case SSSE3: 4222 case SSE3: 4223 case SSE2: 4224 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4225 break; 4226 case SSE1: 4227 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4228 break; 4229 default: 4230 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4231 break; 4232 } 4233 } 4234 4235 // Each case falls through to the previous one here. 4236 switch (MMX3DNowLevel) { 4237 case AMD3DNowAthlon: 4238 Builder.defineMacro("__3dNOW_A__"); 4239 LLVM_FALLTHROUGH; 4240 case AMD3DNow: 4241 Builder.defineMacro("__3dNOW__"); 4242 LLVM_FALLTHROUGH; 4243 case MMX: 4244 Builder.defineMacro("__MMX__"); 4245 LLVM_FALLTHROUGH; 4246 case NoMMX3DNow: 4247 break; 4248 } 4249 4250 if (CPU >= CK_i486) { 4251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4254 } 4255 if (CPU >= CK_i586) 4256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4257 4258 if (HasFloat128) 4259 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4260 } 4261 4262 bool X86TargetInfo::isValidFeatureName(StringRef Name) const { 4263 return llvm::StringSwitch<bool>(Name) 4264 .Case("aes", true) 4265 .Case("avx", true) 4266 .Case("avx2", true) 4267 .Case("avx512f", true) 4268 .Case("avx512cd", true) 4269 .Case("avx512vpopcntdq", true) 4270 .Case("avx512er", true) 4271 .Case("avx512pf", true) 4272 .Case("avx512dq", true) 4273 .Case("avx512bw", true) 4274 .Case("avx512vl", true) 4275 .Case("avx512vbmi", true) 4276 .Case("avx512ifma", true) 4277 .Case("bmi", true) 4278 .Case("bmi2", true) 4279 .Case("clflushopt", true) 4280 .Case("clwb", true) 4281 .Case("clzero", true) 4282 .Case("cx16", true) 4283 .Case("f16c", true) 4284 .Case("fma", true) 4285 .Case("fma4", true) 4286 .Case("fsgsbase", true) 4287 .Case("fxsr", true) 4288 .Case("lwp", true) 4289 .Case("lzcnt", true) 4290 .Case("mm3dnow", true) 4291 .Case("mm3dnowa", true) 4292 .Case("mmx", true) 4293 .Case("movbe", true) 4294 .Case("mpx", true) 4295 .Case("pclmul", true) 4296 .Case("pku", true) 4297 .Case("popcnt", true) 4298 .Case("prefetchwt1", true) 4299 .Case("prfchw", true) 4300 .Case("rdrnd", true) 4301 .Case("rdseed", true) 4302 .Case("rtm", true) 4303 .Case("sgx", true) 4304 .Case("sha", true) 4305 .Case("sse", true) 4306 .Case("sse2", true) 4307 .Case("sse3", true) 4308 .Case("ssse3", true) 4309 .Case("sse4.1", true) 4310 .Case("sse4.2", true) 4311 .Case("sse4a", true) 4312 .Case("tbm", true) 4313 .Case("x86", true) 4314 .Case("x86_32", true) 4315 .Case("x86_64", true) 4316 .Case("xop", true) 4317 .Case("xsave", true) 4318 .Case("xsavec", true) 4319 .Case("xsaves", true) 4320 .Case("xsaveopt", true) 4321 .Default(false); 4322 } 4323 4324 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4325 return llvm::StringSwitch<bool>(Feature) 4326 .Case("aes", HasAES) 4327 .Case("avx", SSELevel >= AVX) 4328 .Case("avx2", SSELevel >= AVX2) 4329 .Case("avx512f", SSELevel >= AVX512F) 4330 .Case("avx512cd", HasAVX512CD) 4331 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4332 .Case("avx512er", HasAVX512ER) 4333 .Case("avx512pf", HasAVX512PF) 4334 .Case("avx512dq", HasAVX512DQ) 4335 .Case("avx512bw", HasAVX512BW) 4336 .Case("avx512vl", HasAVX512VL) 4337 .Case("avx512vbmi", HasAVX512VBMI) 4338 .Case("avx512ifma", HasAVX512IFMA) 4339 .Case("bmi", HasBMI) 4340 .Case("bmi2", HasBMI2) 4341 .Case("clflushopt", HasCLFLUSHOPT) 4342 .Case("clwb", HasCLWB) 4343 .Case("clzero", HasCLZERO) 4344 .Case("cx16", HasCX16) 4345 .Case("f16c", HasF16C) 4346 .Case("fma", HasFMA) 4347 .Case("fma4", XOPLevel >= FMA4) 4348 .Case("fsgsbase", HasFSGSBASE) 4349 .Case("fxsr", HasFXSR) 4350 .Case("lwp", HasLWP) 4351 .Case("lzcnt", HasLZCNT) 4352 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4353 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4354 .Case("mmx", MMX3DNowLevel >= MMX) 4355 .Case("movbe", HasMOVBE) 4356 .Case("mpx", HasMPX) 4357 .Case("pclmul", HasPCLMUL) 4358 .Case("pku", HasPKU) 4359 .Case("popcnt", HasPOPCNT) 4360 .Case("prefetchwt1", HasPREFETCHWT1) 4361 .Case("prfchw", HasPRFCHW) 4362 .Case("rdrnd", HasRDRND) 4363 .Case("rdseed", HasRDSEED) 4364 .Case("rtm", HasRTM) 4365 .Case("sgx", HasSGX) 4366 .Case("sha", HasSHA) 4367 .Case("sse", SSELevel >= SSE1) 4368 .Case("sse2", SSELevel >= SSE2) 4369 .Case("sse3", SSELevel >= SSE3) 4370 .Case("ssse3", SSELevel >= SSSE3) 4371 .Case("sse4.1", SSELevel >= SSE41) 4372 .Case("sse4.2", SSELevel >= SSE42) 4373 .Case("sse4a", XOPLevel >= SSE4A) 4374 .Case("tbm", HasTBM) 4375 .Case("x86", true) 4376 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4377 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4378 .Case("xop", XOPLevel >= XOP) 4379 .Case("xsave", HasXSAVE) 4380 .Case("xsavec", HasXSAVEC) 4381 .Case("xsaves", HasXSAVES) 4382 .Case("xsaveopt", HasXSAVEOPT) 4383 .Default(false); 4384 } 4385 4386 // We can't use a generic validation scheme for the features accepted here 4387 // versus subtarget features accepted in the target attribute because the 4388 // bitfield structure that's initialized in the runtime only supports the 4389 // below currently rather than the full range of subtarget features. (See 4390 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4391 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4392 return llvm::StringSwitch<bool>(FeatureStr) 4393 .Case("cmov", true) 4394 .Case("mmx", true) 4395 .Case("popcnt", true) 4396 .Case("sse", true) 4397 .Case("sse2", true) 4398 .Case("sse3", true) 4399 .Case("ssse3", true) 4400 .Case("sse4.1", true) 4401 .Case("sse4.2", true) 4402 .Case("avx", true) 4403 .Case("avx2", true) 4404 .Case("sse4a", true) 4405 .Case("fma4", true) 4406 .Case("xop", true) 4407 .Case("fma", true) 4408 .Case("avx512f", true) 4409 .Case("bmi", true) 4410 .Case("bmi2", true) 4411 .Case("aes", true) 4412 .Case("pclmul", true) 4413 .Case("avx512vl", true) 4414 .Case("avx512bw", true) 4415 .Case("avx512dq", true) 4416 .Case("avx512cd", true) 4417 .Case("avx512er", true) 4418 .Case("avx512pf", true) 4419 .Case("avx512vbmi", true) 4420 .Case("avx512ifma", true) 4421 .Case("avx512vpopcntdq", true) 4422 .Default(false); 4423 } 4424 4425 bool 4426 X86TargetInfo::validateAsmConstraint(const char *&Name, 4427 TargetInfo::ConstraintInfo &Info) const { 4428 switch (*Name) { 4429 default: return false; 4430 // Constant constraints. 4431 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4432 // instructions. 4433 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4434 // x86_64 instructions. 4435 case 's': 4436 Info.setRequiresImmediate(); 4437 return true; 4438 case 'I': 4439 Info.setRequiresImmediate(0, 31); 4440 return true; 4441 case 'J': 4442 Info.setRequiresImmediate(0, 63); 4443 return true; 4444 case 'K': 4445 Info.setRequiresImmediate(-128, 127); 4446 return true; 4447 case 'L': 4448 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4449 return true; 4450 case 'M': 4451 Info.setRequiresImmediate(0, 3); 4452 return true; 4453 case 'N': 4454 Info.setRequiresImmediate(0, 255); 4455 return true; 4456 case 'O': 4457 Info.setRequiresImmediate(0, 127); 4458 return true; 4459 // Register constraints. 4460 case 'Y': // 'Y' is the first character for several 2-character constraints. 4461 // Shift the pointer to the second character of the constraint. 4462 Name++; 4463 switch (*Name) { 4464 default: 4465 return false; 4466 case '0': // First SSE register. 4467 case 't': // Any SSE register, when SSE2 is enabled. 4468 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4469 case 'm': // Any MMX register, when inter-unit moves enabled. 4470 case 'k': // AVX512 arch mask registers: k1-k7. 4471 Info.setAllowsRegister(); 4472 return true; 4473 } 4474 case 'f': // Any x87 floating point stack register. 4475 // Constraint 'f' cannot be used for output operands. 4476 if (Info.ConstraintStr[0] == '=') 4477 return false; 4478 Info.setAllowsRegister(); 4479 return true; 4480 case 'a': // eax. 4481 case 'b': // ebx. 4482 case 'c': // ecx. 4483 case 'd': // edx. 4484 case 'S': // esi. 4485 case 'D': // edi. 4486 case 'A': // edx:eax. 4487 case 't': // Top of floating point stack. 4488 case 'u': // Second from top of floating point stack. 4489 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4490 case 'y': // Any MMX register. 4491 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4492 case 'x': // Any SSE register. 4493 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4494 // for intermideate k reg operations). 4495 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4496 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4497 case 'l': // "Index" registers: any general register that can be used as an 4498 // index in a base+index memory access. 4499 Info.setAllowsRegister(); 4500 return true; 4501 // Floating point constant constraints. 4502 case 'C': // SSE floating point constant. 4503 case 'G': // x87 floating point constant. 4504 return true; 4505 } 4506 } 4507 4508 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4509 unsigned Size) const { 4510 // Strip off constraint modifiers. 4511 while (Constraint[0] == '=' || 4512 Constraint[0] == '+' || 4513 Constraint[0] == '&') 4514 Constraint = Constraint.substr(1); 4515 4516 return validateOperandSize(Constraint, Size); 4517 } 4518 4519 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4520 unsigned Size) const { 4521 return validateOperandSize(Constraint, Size); 4522 } 4523 4524 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4525 unsigned Size) const { 4526 switch (Constraint[0]) { 4527 default: break; 4528 case 'k': 4529 // Registers k0-k7 (AVX512) size limit is 64 bit. 4530 case 'y': 4531 return Size <= 64; 4532 case 'f': 4533 case 't': 4534 case 'u': 4535 return Size <= 128; 4536 case 'v': 4537 case 'x': 4538 if (SSELevel >= AVX512F) 4539 // 512-bit zmm registers can be used if target supports AVX512F. 4540 return Size <= 512U; 4541 else if (SSELevel >= AVX) 4542 // 256-bit ymm registers can be used if target supports AVX. 4543 return Size <= 256U; 4544 return Size <= 128U; 4545 case 'Y': 4546 // 'Y' is the first character for several 2-character constraints. 4547 switch (Constraint[1]) { 4548 default: break; 4549 case 'm': 4550 // 'Ym' is synonymous with 'y'. 4551 case 'k': 4552 return Size <= 64; 4553 case 'i': 4554 case 't': 4555 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4556 if (SSELevel >= AVX512F) 4557 return Size <= 512U; 4558 else if (SSELevel >= AVX) 4559 return Size <= 256U; 4560 return SSELevel >= SSE2 && Size <= 128U; 4561 } 4562 4563 } 4564 4565 return true; 4566 } 4567 4568 std::string 4569 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4570 switch (*Constraint) { 4571 case 'a': return std::string("{ax}"); 4572 case 'b': return std::string("{bx}"); 4573 case 'c': return std::string("{cx}"); 4574 case 'd': return std::string("{dx}"); 4575 case 'S': return std::string("{si}"); 4576 case 'D': return std::string("{di}"); 4577 case 'p': // address 4578 return std::string("im"); 4579 case 't': // top of floating point stack. 4580 return std::string("{st}"); 4581 case 'u': // second from top of floating point stack. 4582 return std::string("{st(1)}"); // second from top of floating point stack. 4583 case 'Y': 4584 switch (Constraint[1]) { 4585 default: 4586 // Break from inner switch and fall through (copy single char), 4587 // continue parsing after copying the current constraint into 4588 // the return string. 4589 break; 4590 case 'k': 4591 // "^" hints llvm that this is a 2 letter constraint. 4592 // "Constraint++" is used to promote the string iterator 4593 // to the next constraint. 4594 return std::string("^") + std::string(Constraint++, 2); 4595 } 4596 LLVM_FALLTHROUGH; 4597 default: 4598 return std::string(1, *Constraint); 4599 } 4600 } 4601 4602 // X86-32 generic target 4603 class X86_32TargetInfo : public X86TargetInfo { 4604 public: 4605 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4606 : X86TargetInfo(Triple, Opts) { 4607 DoubleAlign = LongLongAlign = 32; 4608 LongDoubleWidth = 96; 4609 LongDoubleAlign = 32; 4610 SuitableAlign = 128; 4611 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4612 SizeType = UnsignedInt; 4613 PtrDiffType = SignedInt; 4614 IntPtrType = SignedInt; 4615 RegParmMax = 3; 4616 4617 // Use fpret for all types. 4618 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4619 (1 << TargetInfo::Double) | 4620 (1 << TargetInfo::LongDouble)); 4621 4622 // x86-32 has atomics up to 8 bytes 4623 // FIXME: Check that we actually have cmpxchg8b before setting 4624 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4625 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4626 } 4627 BuiltinVaListKind getBuiltinVaListKind() const override { 4628 return TargetInfo::CharPtrBuiltinVaList; 4629 } 4630 4631 int getEHDataRegisterNumber(unsigned RegNo) const override { 4632 if (RegNo == 0) return 0; 4633 if (RegNo == 1) return 2; 4634 return -1; 4635 } 4636 bool validateOperandSize(StringRef Constraint, 4637 unsigned Size) const override { 4638 switch (Constraint[0]) { 4639 default: break; 4640 case 'R': 4641 case 'q': 4642 case 'Q': 4643 case 'a': 4644 case 'b': 4645 case 'c': 4646 case 'd': 4647 case 'S': 4648 case 'D': 4649 return Size <= 32; 4650 case 'A': 4651 return Size <= 64; 4652 } 4653 4654 return X86TargetInfo::validateOperandSize(Constraint, Size); 4655 } 4656 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4657 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4658 Builtin::FirstTSBuiltin + 1); 4659 } 4660 }; 4661 4662 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4663 public: 4664 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4665 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4666 4667 unsigned getFloatEvalMethod() const override { 4668 unsigned Major, Minor, Micro; 4669 getTriple().getOSVersion(Major, Minor, Micro); 4670 // New NetBSD uses the default rounding mode. 4671 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4672 return X86_32TargetInfo::getFloatEvalMethod(); 4673 // NetBSD before 6.99.26 defaults to "double" rounding. 4674 return 1; 4675 } 4676 }; 4677 4678 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4679 public: 4680 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4681 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4682 SizeType = UnsignedLong; 4683 IntPtrType = SignedLong; 4684 PtrDiffType = SignedLong; 4685 } 4686 }; 4687 4688 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4689 public: 4690 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4691 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4692 SizeType = UnsignedLong; 4693 IntPtrType = SignedLong; 4694 PtrDiffType = SignedLong; 4695 } 4696 }; 4697 4698 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4699 public: 4700 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4701 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4702 LongDoubleWidth = 128; 4703 LongDoubleAlign = 128; 4704 SuitableAlign = 128; 4705 MaxVectorAlign = 256; 4706 // The watchOS simulator uses the builtin bool type for Objective-C. 4707 llvm::Triple T = llvm::Triple(Triple); 4708 if (T.isWatchOS()) 4709 UseSignedCharForObjCBool = false; 4710 SizeType = UnsignedLong; 4711 IntPtrType = SignedLong; 4712 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4713 HasAlignMac68kSupport = true; 4714 } 4715 4716 bool handleTargetFeatures(std::vector<std::string> &Features, 4717 DiagnosticsEngine &Diags) override { 4718 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4719 Diags)) 4720 return false; 4721 // We now know the features we have: we can decide how to align vectors. 4722 MaxVectorAlign = 4723 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4724 return true; 4725 } 4726 }; 4727 4728 // x86-32 Windows target 4729 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4730 public: 4731 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4732 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4733 WCharType = UnsignedShort; 4734 DoubleAlign = LongLongAlign = 64; 4735 bool IsWinCOFF = 4736 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4737 resetDataLayout(IsWinCOFF 4738 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4739 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4740 } 4741 void getTargetDefines(const LangOptions &Opts, 4742 MacroBuilder &Builder) const override { 4743 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4744 } 4745 }; 4746 4747 // x86-32 Windows Visual Studio target 4748 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4749 public: 4750 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4751 const TargetOptions &Opts) 4752 : WindowsX86_32TargetInfo(Triple, Opts) { 4753 LongDoubleWidth = LongDoubleAlign = 64; 4754 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4755 } 4756 void getTargetDefines(const LangOptions &Opts, 4757 MacroBuilder &Builder) const override { 4758 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4759 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4760 // The value of the following reflects processor type. 4761 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4762 // We lost the original triple, so we use the default. 4763 Builder.defineMacro("_M_IX86", "600"); 4764 } 4765 }; 4766 4767 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4768 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4769 // supports __declspec natively under -fms-extensions, but we define a no-op 4770 // __declspec macro anyway for pre-processor compatibility. 4771 if (Opts.MicrosoftExt) 4772 Builder.defineMacro("__declspec", "__declspec"); 4773 else 4774 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4775 4776 if (!Opts.MicrosoftExt) { 4777 // Provide macros for all the calling convention keywords. Provide both 4778 // single and double underscore prefixed variants. These are available on 4779 // x64 as well as x86, even though they have no effect. 4780 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4781 for (const char *CC : CCs) { 4782 std::string GCCSpelling = "__attribute__((__"; 4783 GCCSpelling += CC; 4784 GCCSpelling += "__))"; 4785 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4786 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4787 } 4788 } 4789 } 4790 4791 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4792 Builder.defineMacro("__MSVCRT__"); 4793 Builder.defineMacro("__MINGW32__"); 4794 addCygMingDefines(Opts, Builder); 4795 } 4796 4797 // x86-32 MinGW target 4798 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4799 public: 4800 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4801 : WindowsX86_32TargetInfo(Triple, Opts) { 4802 HasFloat128 = true; 4803 } 4804 void getTargetDefines(const LangOptions &Opts, 4805 MacroBuilder &Builder) const override { 4806 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4807 DefineStd(Builder, "WIN32", Opts); 4808 DefineStd(Builder, "WINNT", Opts); 4809 Builder.defineMacro("_X86_"); 4810 addMinGWDefines(Opts, Builder); 4811 } 4812 }; 4813 4814 // x86-32 Cygwin target 4815 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4816 public: 4817 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4818 : X86_32TargetInfo(Triple, Opts) { 4819 WCharType = UnsignedShort; 4820 DoubleAlign = LongLongAlign = 64; 4821 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4822 } 4823 void getTargetDefines(const LangOptions &Opts, 4824 MacroBuilder &Builder) const override { 4825 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4826 Builder.defineMacro("_X86_"); 4827 Builder.defineMacro("__CYGWIN__"); 4828 Builder.defineMacro("__CYGWIN32__"); 4829 addCygMingDefines(Opts, Builder); 4830 DefineStd(Builder, "unix", Opts); 4831 if (Opts.CPlusPlus) 4832 Builder.defineMacro("_GNU_SOURCE"); 4833 } 4834 }; 4835 4836 // x86-32 Haiku target 4837 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4838 public: 4839 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4840 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4841 } 4842 void getTargetDefines(const LangOptions &Opts, 4843 MacroBuilder &Builder) const override { 4844 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4845 Builder.defineMacro("__INTEL__"); 4846 } 4847 }; 4848 4849 // X86-32 MCU target 4850 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4851 public: 4852 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4853 : X86_32TargetInfo(Triple, Opts) { 4854 LongDoubleWidth = 64; 4855 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4856 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4857 WIntType = UnsignedInt; 4858 } 4859 4860 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4861 // On MCU we support only C calling convention. 4862 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4863 } 4864 4865 void getTargetDefines(const LangOptions &Opts, 4866 MacroBuilder &Builder) const override { 4867 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4868 Builder.defineMacro("__iamcu"); 4869 Builder.defineMacro("__iamcu__"); 4870 } 4871 4872 bool allowsLargerPreferedTypeAlignment() const override { 4873 return false; 4874 } 4875 }; 4876 4877 // RTEMS Target 4878 template<typename Target> 4879 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4880 protected: 4881 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4882 MacroBuilder &Builder) const override { 4883 // RTEMS defines; list based off of gcc output 4884 4885 Builder.defineMacro("__rtems__"); 4886 Builder.defineMacro("__ELF__"); 4887 } 4888 4889 public: 4890 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4891 : OSTargetInfo<Target>(Triple, Opts) { 4892 switch (Triple.getArch()) { 4893 default: 4894 case llvm::Triple::x86: 4895 // this->MCountName = ".mcount"; 4896 break; 4897 case llvm::Triple::mips: 4898 case llvm::Triple::mipsel: 4899 case llvm::Triple::ppc: 4900 case llvm::Triple::ppc64: 4901 case llvm::Triple::ppc64le: 4902 // this->MCountName = "_mcount"; 4903 break; 4904 case llvm::Triple::arm: 4905 // this->MCountName = "__mcount"; 4906 break; 4907 } 4908 } 4909 }; 4910 4911 // x86-32 RTEMS target 4912 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4913 public: 4914 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4915 : X86_32TargetInfo(Triple, Opts) { 4916 SizeType = UnsignedLong; 4917 IntPtrType = SignedLong; 4918 PtrDiffType = SignedLong; 4919 } 4920 void getTargetDefines(const LangOptions &Opts, 4921 MacroBuilder &Builder) const override { 4922 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4923 Builder.defineMacro("__INTEL__"); 4924 Builder.defineMacro("__rtems__"); 4925 } 4926 }; 4927 4928 // x86-64 generic target 4929 class X86_64TargetInfo : public X86TargetInfo { 4930 public: 4931 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4932 : X86TargetInfo(Triple, Opts) { 4933 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4934 bool IsWinCOFF = 4935 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4936 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4937 LongDoubleWidth = 128; 4938 LongDoubleAlign = 128; 4939 LargeArrayMinWidth = 128; 4940 LargeArrayAlign = 128; 4941 SuitableAlign = 128; 4942 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4943 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4944 IntPtrType = IsX32 ? SignedInt : SignedLong; 4945 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4946 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4947 RegParmMax = 6; 4948 4949 // Pointers are 32-bit in x32. 4950 resetDataLayout(IsX32 4951 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4952 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4953 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4954 4955 // Use fpret only for long double. 4956 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4957 4958 // Use fp2ret for _Complex long double. 4959 ComplexLongDoubleUsesFP2Ret = true; 4960 4961 // Make __builtin_ms_va_list available. 4962 HasBuiltinMSVaList = true; 4963 4964 // x86-64 has atomics up to 16 bytes. 4965 MaxAtomicPromoteWidth = 128; 4966 MaxAtomicInlineWidth = 128; 4967 } 4968 BuiltinVaListKind getBuiltinVaListKind() const override { 4969 return TargetInfo::X86_64ABIBuiltinVaList; 4970 } 4971 4972 int getEHDataRegisterNumber(unsigned RegNo) const override { 4973 if (RegNo == 0) return 0; 4974 if (RegNo == 1) return 1; 4975 return -1; 4976 } 4977 4978 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4979 switch (CC) { 4980 case CC_C: 4981 case CC_Swift: 4982 case CC_X86VectorCall: 4983 case CC_IntelOclBicc: 4984 case CC_Win64: 4985 case CC_PreserveMost: 4986 case CC_PreserveAll: 4987 case CC_X86RegCall: 4988 case CC_OpenCLKernel: 4989 return CCCR_OK; 4990 default: 4991 return CCCR_Warning; 4992 } 4993 } 4994 4995 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4996 return CC_C; 4997 } 4998 4999 // for x32 we need it here explicitly 5000 bool hasInt128Type() const override { return true; } 5001 unsigned getUnwindWordWidth() const override { return 64; } 5002 unsigned getRegisterWidth() const override { return 64; } 5003 5004 bool validateGlobalRegisterVariable(StringRef RegName, 5005 unsigned RegSize, 5006 bool &HasSizeMismatch) const override { 5007 // rsp and rbp are the only 64-bit registers the x86 backend can currently 5008 // handle. 5009 if (RegName.equals("rsp") || RegName.equals("rbp")) { 5010 // Check that the register size is 64-bit. 5011 HasSizeMismatch = RegSize != 64; 5012 return true; 5013 } 5014 5015 // Check if the register is a 32-bit register the backend can handle. 5016 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 5017 HasSizeMismatch); 5018 } 5019 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5020 return llvm::makeArrayRef(BuiltinInfoX86, 5021 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 5022 } 5023 }; 5024 5025 // x86-64 Windows target 5026 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 5027 public: 5028 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5029 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5030 WCharType = UnsignedShort; 5031 LongWidth = LongAlign = 32; 5032 DoubleAlign = LongLongAlign = 64; 5033 IntMaxType = SignedLongLong; 5034 Int64Type = SignedLongLong; 5035 SizeType = UnsignedLongLong; 5036 PtrDiffType = SignedLongLong; 5037 IntPtrType = SignedLongLong; 5038 } 5039 5040 void getTargetDefines(const LangOptions &Opts, 5041 MacroBuilder &Builder) const override { 5042 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 5043 Builder.defineMacro("_WIN64"); 5044 } 5045 5046 BuiltinVaListKind getBuiltinVaListKind() const override { 5047 return TargetInfo::CharPtrBuiltinVaList; 5048 } 5049 5050 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5051 switch (CC) { 5052 case CC_X86StdCall: 5053 case CC_X86ThisCall: 5054 case CC_X86FastCall: 5055 return CCCR_Ignore; 5056 case CC_C: 5057 case CC_X86VectorCall: 5058 case CC_IntelOclBicc: 5059 case CC_X86_64SysV: 5060 case CC_Swift: 5061 case CC_X86RegCall: 5062 case CC_OpenCLKernel: 5063 return CCCR_OK; 5064 default: 5065 return CCCR_Warning; 5066 } 5067 } 5068 }; 5069 5070 // x86-64 Windows Visual Studio target 5071 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 5072 public: 5073 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 5074 const TargetOptions &Opts) 5075 : WindowsX86_64TargetInfo(Triple, Opts) { 5076 LongDoubleWidth = LongDoubleAlign = 64; 5077 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 5078 } 5079 void getTargetDefines(const LangOptions &Opts, 5080 MacroBuilder &Builder) const override { 5081 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5082 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 5083 Builder.defineMacro("_M_X64", "100"); 5084 Builder.defineMacro("_M_AMD64", "100"); 5085 } 5086 }; 5087 5088 // x86-64 MinGW target 5089 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 5090 public: 5091 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5092 : WindowsX86_64TargetInfo(Triple, Opts) { 5093 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 5094 // with x86 FP ops. Weird. 5095 LongDoubleWidth = LongDoubleAlign = 128; 5096 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 5097 HasFloat128 = true; 5098 } 5099 5100 void getTargetDefines(const LangOptions &Opts, 5101 MacroBuilder &Builder) const override { 5102 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 5103 DefineStd(Builder, "WIN64", Opts); 5104 Builder.defineMacro("__MINGW64__"); 5105 addMinGWDefines(Opts, Builder); 5106 5107 // GCC defines this macro when it is using __gxx_personality_seh0. 5108 if (!Opts.SjLjExceptions) 5109 Builder.defineMacro("__SEH__"); 5110 } 5111 }; 5112 5113 // x86-64 Cygwin target 5114 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 5115 public: 5116 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5117 : X86_64TargetInfo(Triple, Opts) { 5118 TLSSupported = false; 5119 WCharType = UnsignedShort; 5120 } 5121 void getTargetDefines(const LangOptions &Opts, 5122 MacroBuilder &Builder) const override { 5123 X86_64TargetInfo::getTargetDefines(Opts, Builder); 5124 Builder.defineMacro("__x86_64__"); 5125 Builder.defineMacro("__CYGWIN__"); 5126 Builder.defineMacro("__CYGWIN64__"); 5127 addCygMingDefines(Opts, Builder); 5128 DefineStd(Builder, "unix", Opts); 5129 if (Opts.CPlusPlus) 5130 Builder.defineMacro("_GNU_SOURCE"); 5131 5132 // GCC defines this macro when it is using __gxx_personality_seh0. 5133 if (!Opts.SjLjExceptions) 5134 Builder.defineMacro("__SEH__"); 5135 } 5136 }; 5137 5138 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 5139 public: 5140 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5141 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5142 Int64Type = SignedLongLong; 5143 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 5144 llvm::Triple T = llvm::Triple(Triple); 5145 if (T.isiOS()) 5146 UseSignedCharForObjCBool = false; 5147 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 5148 } 5149 5150 bool handleTargetFeatures(std::vector<std::string> &Features, 5151 DiagnosticsEngine &Diags) override { 5152 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5153 Diags)) 5154 return false; 5155 // We now know the features we have: we can decide how to align vectors. 5156 MaxVectorAlign = 5157 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5158 return true; 5159 } 5160 }; 5161 5162 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5163 public: 5164 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5165 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5166 IntMaxType = SignedLongLong; 5167 Int64Type = SignedLongLong; 5168 } 5169 }; 5170 5171 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5172 public: 5173 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5174 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5175 IntMaxType = SignedLongLong; 5176 Int64Type = SignedLongLong; 5177 } 5178 }; 5179 5180 class ARMTargetInfo : public TargetInfo { 5181 // Possible FPU choices. 5182 enum FPUMode { 5183 VFP2FPU = (1 << 0), 5184 VFP3FPU = (1 << 1), 5185 VFP4FPU = (1 << 2), 5186 NeonFPU = (1 << 3), 5187 FPARMV8 = (1 << 4) 5188 }; 5189 5190 // Possible HWDiv features. 5191 enum HWDivMode { 5192 HWDivThumb = (1 << 0), 5193 HWDivARM = (1 << 1) 5194 }; 5195 5196 static bool FPUModeIsVFP(FPUMode Mode) { 5197 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5198 } 5199 5200 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5201 static const char * const GCCRegNames[]; 5202 5203 std::string ABI, CPU; 5204 5205 StringRef CPUProfile; 5206 StringRef CPUAttr; 5207 5208 enum { 5209 FP_Default, 5210 FP_VFP, 5211 FP_Neon 5212 } FPMath; 5213 5214 unsigned ArchISA; 5215 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5216 unsigned ArchProfile; 5217 unsigned ArchVersion; 5218 5219 unsigned FPU : 5; 5220 5221 unsigned IsAAPCS : 1; 5222 unsigned HWDiv : 2; 5223 5224 // Initialized via features. 5225 unsigned SoftFloat : 1; 5226 unsigned SoftFloatABI : 1; 5227 5228 unsigned CRC : 1; 5229 unsigned Crypto : 1; 5230 unsigned DSP : 1; 5231 unsigned Unaligned : 1; 5232 5233 enum { 5234 LDREX_B = (1 << 0), /// byte (8-bit) 5235 LDREX_H = (1 << 1), /// half (16-bit) 5236 LDREX_W = (1 << 2), /// word (32-bit) 5237 LDREX_D = (1 << 3), /// double (64-bit) 5238 }; 5239 5240 uint32_t LDREX; 5241 5242 // ACLE 6.5.1 Hardware floating point 5243 enum { 5244 HW_FP_HP = (1 << 1), /// half (16-bit) 5245 HW_FP_SP = (1 << 2), /// single (32-bit) 5246 HW_FP_DP = (1 << 3), /// double (64-bit) 5247 }; 5248 uint32_t HW_FP; 5249 5250 static const Builtin::Info BuiltinInfo[]; 5251 5252 void setABIAAPCS() { 5253 IsAAPCS = true; 5254 5255 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5256 const llvm::Triple &T = getTriple(); 5257 5258 // size_t is unsigned long on MachO-derived environments, NetBSD, 5259 // OpenBSD and Bitrig. 5260 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5261 T.getOS() == llvm::Triple::OpenBSD || 5262 T.getOS() == llvm::Triple::Bitrig) 5263 SizeType = UnsignedLong; 5264 else 5265 SizeType = UnsignedInt; 5266 5267 switch (T.getOS()) { 5268 case llvm::Triple::NetBSD: 5269 case llvm::Triple::OpenBSD: 5270 WCharType = SignedInt; 5271 break; 5272 case llvm::Triple::Win32: 5273 WCharType = UnsignedShort; 5274 break; 5275 case llvm::Triple::Linux: 5276 default: 5277 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5278 WCharType = UnsignedInt; 5279 break; 5280 } 5281 5282 UseBitFieldTypeAlignment = true; 5283 5284 ZeroLengthBitfieldBoundary = 0; 5285 5286 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5287 // so set preferred for small types to 32. 5288 if (T.isOSBinFormatMachO()) { 5289 resetDataLayout(BigEndian 5290 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5291 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5292 } else if (T.isOSWindows()) { 5293 assert(!BigEndian && "Windows on ARM does not support big endian"); 5294 resetDataLayout("e" 5295 "-m:w" 5296 "-p:32:32" 5297 "-i64:64" 5298 "-v128:64:128" 5299 "-a:0:32" 5300 "-n32" 5301 "-S64"); 5302 } else if (T.isOSNaCl()) { 5303 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5304 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5305 } else { 5306 resetDataLayout(BigEndian 5307 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5308 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5309 } 5310 5311 // FIXME: Enumerated types are variable width in straight AAPCS. 5312 } 5313 5314 void setABIAPCS(bool IsAAPCS16) { 5315 const llvm::Triple &T = getTriple(); 5316 5317 IsAAPCS = false; 5318 5319 if (IsAAPCS16) 5320 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5321 else 5322 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5323 5324 // size_t is unsigned int on FreeBSD. 5325 if (T.getOS() == llvm::Triple::FreeBSD) 5326 SizeType = UnsignedInt; 5327 else 5328 SizeType = UnsignedLong; 5329 5330 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5331 WCharType = SignedInt; 5332 5333 // Do not respect the alignment of bit-field types when laying out 5334 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5335 UseBitFieldTypeAlignment = false; 5336 5337 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5338 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5339 /// gcc. 5340 ZeroLengthBitfieldBoundary = 32; 5341 5342 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5343 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5344 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5345 } else if (T.isOSBinFormatMachO()) 5346 resetDataLayout( 5347 BigEndian 5348 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5349 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5350 else 5351 resetDataLayout( 5352 BigEndian 5353 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5354 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5355 5356 // FIXME: Override "preferred align" for double and long long. 5357 } 5358 5359 void setArchInfo() { 5360 StringRef ArchName = getTriple().getArchName(); 5361 5362 ArchISA = llvm::ARM::parseArchISA(ArchName); 5363 CPU = llvm::ARM::getDefaultCPU(ArchName); 5364 unsigned AK = llvm::ARM::parseArch(ArchName); 5365 if (AK != llvm::ARM::AK_INVALID) 5366 ArchKind = AK; 5367 setArchInfo(ArchKind); 5368 } 5369 5370 void setArchInfo(unsigned Kind) { 5371 StringRef SubArch; 5372 5373 // cache TargetParser info 5374 ArchKind = Kind; 5375 SubArch = llvm::ARM::getSubArch(ArchKind); 5376 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5377 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5378 5379 // cache CPU related strings 5380 CPUAttr = getCPUAttr(); 5381 CPUProfile = getCPUProfile(); 5382 } 5383 5384 void setAtomic() { 5385 // when triple does not specify a sub arch, 5386 // then we are not using inline atomics 5387 bool ShouldUseInlineAtomic = 5388 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5389 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5390 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5391 if (ArchProfile == llvm::ARM::PK_M) { 5392 MaxAtomicPromoteWidth = 32; 5393 if (ShouldUseInlineAtomic) 5394 MaxAtomicInlineWidth = 32; 5395 } 5396 else { 5397 MaxAtomicPromoteWidth = 64; 5398 if (ShouldUseInlineAtomic) 5399 MaxAtomicInlineWidth = 64; 5400 } 5401 } 5402 5403 bool isThumb() const { 5404 return (ArchISA == llvm::ARM::IK_THUMB); 5405 } 5406 5407 bool supportsThumb() const { 5408 return CPUAttr.count('T') || ArchVersion >= 6; 5409 } 5410 5411 bool supportsThumb2() const { 5412 return CPUAttr.equals("6T2") || 5413 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5414 } 5415 5416 StringRef getCPUAttr() const { 5417 // For most sub-arches, the build attribute CPU name is enough. 5418 // For Cortex variants, it's slightly different. 5419 switch(ArchKind) { 5420 default: 5421 return llvm::ARM::getCPUAttr(ArchKind); 5422 case llvm::ARM::AK_ARMV6M: 5423 return "6M"; 5424 case llvm::ARM::AK_ARMV7S: 5425 return "7S"; 5426 case llvm::ARM::AK_ARMV7A: 5427 return "7A"; 5428 case llvm::ARM::AK_ARMV7R: 5429 return "7R"; 5430 case llvm::ARM::AK_ARMV7M: 5431 return "7M"; 5432 case llvm::ARM::AK_ARMV7EM: 5433 return "7EM"; 5434 case llvm::ARM::AK_ARMV7VE: 5435 return "7VE"; 5436 case llvm::ARM::AK_ARMV8A: 5437 return "8A"; 5438 case llvm::ARM::AK_ARMV8_1A: 5439 return "8_1A"; 5440 case llvm::ARM::AK_ARMV8_2A: 5441 return "8_2A"; 5442 case llvm::ARM::AK_ARMV8MBaseline: 5443 return "8M_BASE"; 5444 case llvm::ARM::AK_ARMV8MMainline: 5445 return "8M_MAIN"; 5446 case llvm::ARM::AK_ARMV8R: 5447 return "8R"; 5448 } 5449 } 5450 5451 StringRef getCPUProfile() const { 5452 switch(ArchProfile) { 5453 case llvm::ARM::PK_A: 5454 return "A"; 5455 case llvm::ARM::PK_R: 5456 return "R"; 5457 case llvm::ARM::PK_M: 5458 return "M"; 5459 default: 5460 return ""; 5461 } 5462 } 5463 5464 public: 5465 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5466 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5467 HW_FP(0) { 5468 5469 switch (getTriple().getOS()) { 5470 case llvm::Triple::NetBSD: 5471 case llvm::Triple::OpenBSD: 5472 PtrDiffType = SignedLong; 5473 break; 5474 default: 5475 PtrDiffType = SignedInt; 5476 break; 5477 } 5478 5479 // Cache arch related info. 5480 setArchInfo(); 5481 5482 // {} in inline assembly are neon specifiers, not assembly variant 5483 // specifiers. 5484 NoAsmVariants = true; 5485 5486 // FIXME: This duplicates code from the driver that sets the -target-abi 5487 // option - this code is used if -target-abi isn't passed and should 5488 // be unified in some way. 5489 if (Triple.isOSBinFormatMachO()) { 5490 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5491 // the frontend matches that. 5492 if (Triple.getEnvironment() == llvm::Triple::EABI || 5493 Triple.getOS() == llvm::Triple::UnknownOS || 5494 ArchProfile == llvm::ARM::PK_M) { 5495 setABI("aapcs"); 5496 } else if (Triple.isWatchABI()) { 5497 setABI("aapcs16"); 5498 } else { 5499 setABI("apcs-gnu"); 5500 } 5501 } else if (Triple.isOSWindows()) { 5502 // FIXME: this is invalid for WindowsCE 5503 setABI("aapcs"); 5504 } else { 5505 // Select the default based on the platform. 5506 switch (Triple.getEnvironment()) { 5507 case llvm::Triple::Android: 5508 case llvm::Triple::GNUEABI: 5509 case llvm::Triple::GNUEABIHF: 5510 case llvm::Triple::MuslEABI: 5511 case llvm::Triple::MuslEABIHF: 5512 setABI("aapcs-linux"); 5513 break; 5514 case llvm::Triple::EABIHF: 5515 case llvm::Triple::EABI: 5516 setABI("aapcs"); 5517 break; 5518 case llvm::Triple::GNU: 5519 setABI("apcs-gnu"); 5520 break; 5521 default: 5522 if (Triple.getOS() == llvm::Triple::NetBSD) 5523 setABI("apcs-gnu"); 5524 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5525 setABI("aapcs-linux"); 5526 else 5527 setABI("aapcs"); 5528 break; 5529 } 5530 } 5531 5532 // ARM targets default to using the ARM C++ ABI. 5533 TheCXXABI.set(TargetCXXABI::GenericARM); 5534 5535 // ARM has atomics up to 8 bytes 5536 setAtomic(); 5537 5538 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5539 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5540 MaxVectorAlign = 64; 5541 5542 // Do force alignment of members that follow zero length bitfields. If 5543 // the alignment of the zero-length bitfield is greater than the member 5544 // that follows it, `bar', `bar' will be aligned as the type of the 5545 // zero length bitfield. 5546 UseZeroLengthBitfieldAlignment = true; 5547 5548 if (Triple.getOS() == llvm::Triple::Linux || 5549 Triple.getOS() == llvm::Triple::UnknownOS) 5550 this->MCountName = 5551 Opts.EABIVersion == llvm::EABI::GNU ? "\01__gnu_mcount_nc" : "\01mcount"; 5552 } 5553 5554 StringRef getABI() const override { return ABI; } 5555 5556 bool setABI(const std::string &Name) override { 5557 ABI = Name; 5558 5559 // The defaults (above) are for AAPCS, check if we need to change them. 5560 // 5561 // FIXME: We need support for -meabi... we could just mangle it into the 5562 // name. 5563 if (Name == "apcs-gnu" || Name == "aapcs16") { 5564 setABIAPCS(Name == "aapcs16"); 5565 return true; 5566 } 5567 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5568 setABIAAPCS(); 5569 return true; 5570 } 5571 return false; 5572 } 5573 5574 // FIXME: This should be based on Arch attributes, not CPU names. 5575 bool 5576 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5577 StringRef CPU, 5578 const std::vector<std::string> &FeaturesVec) const override { 5579 5580 std::vector<StringRef> TargetFeatures; 5581 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5582 5583 // get default FPU features 5584 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5585 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5586 5587 // get default Extension features 5588 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5589 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5590 5591 for (auto Feature : TargetFeatures) 5592 if (Feature[0] == '+') 5593 Features[Feature.drop_front(1)] = true; 5594 5595 // Enable or disable thumb-mode explicitly per function to enable mixed 5596 // ARM and Thumb code generation. 5597 if (isThumb()) 5598 Features["thumb-mode"] = true; 5599 else 5600 Features["thumb-mode"] = false; 5601 5602 // Convert user-provided arm and thumb GNU target attributes to 5603 // [-|+]thumb-mode target features respectively. 5604 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5605 for (auto &Feature : UpdatedFeaturesVec) { 5606 if (Feature.compare("+arm") == 0) 5607 Feature = "-thumb-mode"; 5608 else if (Feature.compare("+thumb") == 0) 5609 Feature = "+thumb-mode"; 5610 } 5611 5612 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5613 } 5614 5615 bool handleTargetFeatures(std::vector<std::string> &Features, 5616 DiagnosticsEngine &Diags) override { 5617 FPU = 0; 5618 CRC = 0; 5619 Crypto = 0; 5620 DSP = 0; 5621 Unaligned = 1; 5622 SoftFloat = SoftFloatABI = false; 5623 HWDiv = 0; 5624 5625 // This does not diagnose illegal cases like having both 5626 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5627 uint32_t HW_FP_remove = 0; 5628 for (const auto &Feature : Features) { 5629 if (Feature == "+soft-float") { 5630 SoftFloat = true; 5631 } else if (Feature == "+soft-float-abi") { 5632 SoftFloatABI = true; 5633 } else if (Feature == "+vfp2") { 5634 FPU |= VFP2FPU; 5635 HW_FP |= HW_FP_SP | HW_FP_DP; 5636 } else if (Feature == "+vfp3") { 5637 FPU |= VFP3FPU; 5638 HW_FP |= HW_FP_SP | HW_FP_DP; 5639 } else if (Feature == "+vfp4") { 5640 FPU |= VFP4FPU; 5641 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5642 } else if (Feature == "+fp-armv8") { 5643 FPU |= FPARMV8; 5644 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5645 } else if (Feature == "+neon") { 5646 FPU |= NeonFPU; 5647 HW_FP |= HW_FP_SP | HW_FP_DP; 5648 } else if (Feature == "+hwdiv") { 5649 HWDiv |= HWDivThumb; 5650 } else if (Feature == "+hwdiv-arm") { 5651 HWDiv |= HWDivARM; 5652 } else if (Feature == "+crc") { 5653 CRC = 1; 5654 } else if (Feature == "+crypto") { 5655 Crypto = 1; 5656 } else if (Feature == "+dsp") { 5657 DSP = 1; 5658 } else if (Feature == "+fp-only-sp") { 5659 HW_FP_remove |= HW_FP_DP; 5660 } else if (Feature == "+strict-align") { 5661 Unaligned = 0; 5662 } else if (Feature == "+fp16") { 5663 HW_FP |= HW_FP_HP; 5664 } 5665 } 5666 HW_FP &= ~HW_FP_remove; 5667 5668 switch (ArchVersion) { 5669 case 6: 5670 if (ArchProfile == llvm::ARM::PK_M) 5671 LDREX = 0; 5672 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5673 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5674 else 5675 LDREX = LDREX_W; 5676 break; 5677 case 7: 5678 if (ArchProfile == llvm::ARM::PK_M) 5679 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5680 else 5681 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5682 break; 5683 case 8: 5684 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5685 } 5686 5687 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5688 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5689 return false; 5690 } 5691 5692 if (FPMath == FP_Neon) 5693 Features.push_back("+neonfp"); 5694 else if (FPMath == FP_VFP) 5695 Features.push_back("-neonfp"); 5696 5697 // Remove front-end specific options which the backend handles differently. 5698 auto Feature = 5699 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5700 if (Feature != Features.end()) 5701 Features.erase(Feature); 5702 5703 return true; 5704 } 5705 5706 bool hasFeature(StringRef Feature) const override { 5707 return llvm::StringSwitch<bool>(Feature) 5708 .Case("arm", true) 5709 .Case("aarch32", true) 5710 .Case("softfloat", SoftFloat) 5711 .Case("thumb", isThumb()) 5712 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5713 .Case("vfp", FPU && !SoftFloat) 5714 .Case("hwdiv", HWDiv & HWDivThumb) 5715 .Case("hwdiv-arm", HWDiv & HWDivARM) 5716 .Default(false); 5717 } 5718 5719 bool isValidCPUName(StringRef Name) const override { 5720 return Name == "generic" || 5721 llvm::ARM::parseCPUArch(Name) != llvm::ARM::AK_INVALID; 5722 } 5723 5724 bool setCPU(const std::string &Name) override { 5725 if (Name != "generic") 5726 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5727 5728 if (ArchKind == llvm::ARM::AK_INVALID) 5729 return false; 5730 setAtomic(); 5731 CPU = Name; 5732 return true; 5733 } 5734 5735 bool setFPMath(StringRef Name) override; 5736 5737 void getTargetDefinesARMV81A(const LangOptions &Opts, 5738 MacroBuilder &Builder) const { 5739 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5740 } 5741 5742 void getTargetDefinesARMV82A(const LangOptions &Opts, 5743 MacroBuilder &Builder) const { 5744 // Also include the ARMv8.1-A defines 5745 getTargetDefinesARMV81A(Opts, Builder); 5746 } 5747 5748 void getTargetDefines(const LangOptions &Opts, 5749 MacroBuilder &Builder) const override { 5750 // Target identification. 5751 Builder.defineMacro("__arm"); 5752 Builder.defineMacro("__arm__"); 5753 // For bare-metal none-eabi. 5754 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5755 (getTriple().getEnvironment() == llvm::Triple::EABI || 5756 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5757 Builder.defineMacro("__ELF__"); 5758 5759 5760 // Target properties. 5761 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5762 5763 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5764 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5765 if (getTriple().isWatchABI()) 5766 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5767 5768 if (!CPUAttr.empty()) 5769 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5770 5771 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5772 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5773 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5774 5775 if (ArchVersion >= 8) { 5776 // ACLE 6.5.7 Crypto Extension 5777 if (Crypto) 5778 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5779 // ACLE 6.5.8 CRC32 Extension 5780 if (CRC) 5781 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5782 // ACLE 6.5.10 Numeric Maximum and Minimum 5783 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5784 // ACLE 6.5.9 Directed Rounding 5785 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5786 } 5787 5788 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5789 // is not defined for the M-profile. 5790 // NOTE that the default profile is assumed to be 'A' 5791 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5792 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5793 5794 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5795 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5796 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5797 // v7 and v8 architectures excluding v8-M Baseline. 5798 if (supportsThumb2()) 5799 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5800 else if (supportsThumb()) 5801 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5802 5803 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5804 // instruction set such as ARM or Thumb. 5805 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5806 5807 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5808 5809 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5810 if (!CPUProfile.empty()) 5811 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5812 5813 // ACLE 6.4.3 Unaligned access supported in hardware 5814 if (Unaligned) 5815 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5816 5817 // ACLE 6.4.4 LDREX/STREX 5818 if (LDREX) 5819 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5820 5821 // ACLE 6.4.5 CLZ 5822 if (ArchVersion == 5 || 5823 (ArchVersion == 6 && CPUProfile != "M") || 5824 ArchVersion > 6) 5825 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5826 5827 // ACLE 6.5.1 Hardware Floating Point 5828 if (HW_FP) 5829 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5830 5831 // ACLE predefines. 5832 Builder.defineMacro("__ARM_ACLE", "200"); 5833 5834 // FP16 support (we currently only support IEEE format). 5835 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5836 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5837 5838 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5839 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5840 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5841 5842 // Subtarget options. 5843 5844 // FIXME: It's more complicated than this and we don't really support 5845 // interworking. 5846 // Windows on ARM does not "support" interworking 5847 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5848 Builder.defineMacro("__THUMB_INTERWORK__"); 5849 5850 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5851 // Embedded targets on Darwin follow AAPCS, but not EABI. 5852 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5853 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5854 Builder.defineMacro("__ARM_EABI__"); 5855 Builder.defineMacro("__ARM_PCS", "1"); 5856 } 5857 5858 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5859 ABI == "aapcs16") 5860 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5861 5862 if (SoftFloat) 5863 Builder.defineMacro("__SOFTFP__"); 5864 5865 if (ArchKind == llvm::ARM::AK_XSCALE) 5866 Builder.defineMacro("__XSCALE__"); 5867 5868 if (isThumb()) { 5869 Builder.defineMacro("__THUMBEL__"); 5870 Builder.defineMacro("__thumb__"); 5871 if (supportsThumb2()) 5872 Builder.defineMacro("__thumb2__"); 5873 } 5874 5875 // ACLE 6.4.9 32-bit SIMD instructions 5876 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5877 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5878 5879 // ACLE 6.4.10 Hardware Integer Divide 5880 if (((HWDiv & HWDivThumb) && isThumb()) || 5881 ((HWDiv & HWDivARM) && !isThumb())) { 5882 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5883 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5884 } 5885 5886 // Note, this is always on in gcc, even though it doesn't make sense. 5887 Builder.defineMacro("__APCS_32__"); 5888 5889 if (FPUModeIsVFP((FPUMode) FPU)) { 5890 Builder.defineMacro("__VFP_FP__"); 5891 if (FPU & VFP2FPU) 5892 Builder.defineMacro("__ARM_VFPV2__"); 5893 if (FPU & VFP3FPU) 5894 Builder.defineMacro("__ARM_VFPV3__"); 5895 if (FPU & VFP4FPU) 5896 Builder.defineMacro("__ARM_VFPV4__"); 5897 if (FPU & FPARMV8) 5898 Builder.defineMacro("__ARM_FPV5__"); 5899 } 5900 5901 // This only gets set when Neon instructions are actually available, unlike 5902 // the VFP define, hence the soft float and arch check. This is subtly 5903 // different from gcc, we follow the intent which was that it should be set 5904 // when Neon instructions are actually available. 5905 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5906 Builder.defineMacro("__ARM_NEON", "1"); 5907 Builder.defineMacro("__ARM_NEON__"); 5908 // current AArch32 NEON implementations do not support double-precision 5909 // floating-point even when it is present in VFP. 5910 Builder.defineMacro("__ARM_NEON_FP", 5911 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5912 } 5913 5914 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5915 Opts.ShortWChar ? "2" : "4"); 5916 5917 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5918 Opts.ShortEnums ? "1" : "4"); 5919 5920 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5921 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5922 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5923 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5924 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5925 } 5926 5927 // ACLE 6.4.7 DSP instructions 5928 if (DSP) { 5929 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5930 } 5931 5932 // ACLE 6.4.8 Saturation instructions 5933 bool SAT = false; 5934 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5935 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5936 SAT = true; 5937 } 5938 5939 // ACLE 6.4.6 Q (saturation) flag 5940 if (DSP || SAT) 5941 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5942 5943 if (Opts.UnsafeFPMath) 5944 Builder.defineMacro("__ARM_FP_FAST", "1"); 5945 5946 switch(ArchKind) { 5947 default: break; 5948 case llvm::ARM::AK_ARMV8_1A: 5949 getTargetDefinesARMV81A(Opts, Builder); 5950 break; 5951 case llvm::ARM::AK_ARMV8_2A: 5952 getTargetDefinesARMV82A(Opts, Builder); 5953 break; 5954 } 5955 } 5956 5957 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5958 return llvm::makeArrayRef(BuiltinInfo, 5959 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5960 } 5961 bool isCLZForZeroUndef() const override { return false; } 5962 BuiltinVaListKind getBuiltinVaListKind() const override { 5963 return IsAAPCS 5964 ? AAPCSABIBuiltinVaList 5965 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5966 : TargetInfo::VoidPtrBuiltinVaList); 5967 } 5968 ArrayRef<const char *> getGCCRegNames() const override; 5969 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5970 bool validateAsmConstraint(const char *&Name, 5971 TargetInfo::ConstraintInfo &Info) const override { 5972 switch (*Name) { 5973 default: break; 5974 case 'l': // r0-r7 5975 case 'h': // r8-r15 5976 case 't': // VFP Floating point register single precision 5977 case 'w': // VFP Floating point register double precision 5978 Info.setAllowsRegister(); 5979 return true; 5980 case 'I': 5981 case 'J': 5982 case 'K': 5983 case 'L': 5984 case 'M': 5985 // FIXME 5986 return true; 5987 case 'Q': // A memory address that is a single base register. 5988 Info.setAllowsMemory(); 5989 return true; 5990 case 'U': // a memory reference... 5991 switch (Name[1]) { 5992 case 'q': // ...ARMV4 ldrsb 5993 case 'v': // ...VFP load/store (reg+constant offset) 5994 case 'y': // ...iWMMXt load/store 5995 case 't': // address valid for load/store opaque types wider 5996 // than 128-bits 5997 case 'n': // valid address for Neon doubleword vector load/store 5998 case 'm': // valid address for Neon element and structure load/store 5999 case 's': // valid address for non-offset loads/stores of quad-word 6000 // values in four ARM registers 6001 Info.setAllowsMemory(); 6002 Name++; 6003 return true; 6004 } 6005 } 6006 return false; 6007 } 6008 std::string convertConstraint(const char *&Constraint) const override { 6009 std::string R; 6010 switch (*Constraint) { 6011 case 'U': // Two-character constraint; add "^" hint for later parsing. 6012 R = std::string("^") + std::string(Constraint, 2); 6013 Constraint++; 6014 break; 6015 case 'p': // 'p' should be translated to 'r' by default. 6016 R = std::string("r"); 6017 break; 6018 default: 6019 return std::string(1, *Constraint); 6020 } 6021 return R; 6022 } 6023 bool 6024 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6025 std::string &SuggestedModifier) const override { 6026 bool isOutput = (Constraint[0] == '='); 6027 bool isInOut = (Constraint[0] == '+'); 6028 6029 // Strip off constraint modifiers. 6030 while (Constraint[0] == '=' || 6031 Constraint[0] == '+' || 6032 Constraint[0] == '&') 6033 Constraint = Constraint.substr(1); 6034 6035 switch (Constraint[0]) { 6036 default: break; 6037 case 'r': { 6038 switch (Modifier) { 6039 default: 6040 return (isInOut || isOutput || Size <= 64); 6041 case 'q': 6042 // A register of size 32 cannot fit a vector type. 6043 return false; 6044 } 6045 } 6046 } 6047 6048 return true; 6049 } 6050 const char *getClobbers() const override { 6051 // FIXME: Is this really right? 6052 return ""; 6053 } 6054 6055 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6056 switch (CC) { 6057 case CC_AAPCS: 6058 case CC_AAPCS_VFP: 6059 case CC_Swift: 6060 case CC_OpenCLKernel: 6061 return CCCR_OK; 6062 default: 6063 return CCCR_Warning; 6064 } 6065 } 6066 6067 int getEHDataRegisterNumber(unsigned RegNo) const override { 6068 if (RegNo == 0) return 0; 6069 if (RegNo == 1) return 1; 6070 return -1; 6071 } 6072 6073 bool hasSjLjLowering() const override { 6074 return true; 6075 } 6076 }; 6077 6078 bool ARMTargetInfo::setFPMath(StringRef Name) { 6079 if (Name == "neon") { 6080 FPMath = FP_Neon; 6081 return true; 6082 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 6083 Name == "vfp4") { 6084 FPMath = FP_VFP; 6085 return true; 6086 } 6087 return false; 6088 } 6089 6090 const char * const ARMTargetInfo::GCCRegNames[] = { 6091 // Integer registers 6092 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6093 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 6094 6095 // Float registers 6096 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 6097 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 6098 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 6099 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6100 6101 // Double registers 6102 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 6103 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 6104 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 6105 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6106 6107 // Quad registers 6108 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 6109 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 6110 }; 6111 6112 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 6113 return llvm::makeArrayRef(GCCRegNames); 6114 } 6115 6116 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 6117 { { "a1" }, "r0" }, 6118 { { "a2" }, "r1" }, 6119 { { "a3" }, "r2" }, 6120 { { "a4" }, "r3" }, 6121 { { "v1" }, "r4" }, 6122 { { "v2" }, "r5" }, 6123 { { "v3" }, "r6" }, 6124 { { "v4" }, "r7" }, 6125 { { "v5" }, "r8" }, 6126 { { "v6", "rfp" }, "r9" }, 6127 { { "sl" }, "r10" }, 6128 { { "fp" }, "r11" }, 6129 { { "ip" }, "r12" }, 6130 { { "r13" }, "sp" }, 6131 { { "r14" }, "lr" }, 6132 { { "r15" }, "pc" }, 6133 // The S, D and Q registers overlap, but aren't really aliases; we 6134 // don't want to substitute one of these for a different-sized one. 6135 }; 6136 6137 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 6138 return llvm::makeArrayRef(GCCRegAliases); 6139 } 6140 6141 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 6142 #define BUILTIN(ID, TYPE, ATTRS) \ 6143 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6144 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6145 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6146 #include "clang/Basic/BuiltinsNEON.def" 6147 6148 #define BUILTIN(ID, TYPE, ATTRS) \ 6149 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6150 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 6151 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 6152 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6153 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6154 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 6155 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 6156 #include "clang/Basic/BuiltinsARM.def" 6157 }; 6158 6159 class ARMleTargetInfo : public ARMTargetInfo { 6160 public: 6161 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6162 : ARMTargetInfo(Triple, Opts) {} 6163 void getTargetDefines(const LangOptions &Opts, 6164 MacroBuilder &Builder) const override { 6165 Builder.defineMacro("__ARMEL__"); 6166 ARMTargetInfo::getTargetDefines(Opts, Builder); 6167 } 6168 }; 6169 6170 class ARMbeTargetInfo : public ARMTargetInfo { 6171 public: 6172 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6173 : ARMTargetInfo(Triple, Opts) {} 6174 void getTargetDefines(const LangOptions &Opts, 6175 MacroBuilder &Builder) const override { 6176 Builder.defineMacro("__ARMEB__"); 6177 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6178 ARMTargetInfo::getTargetDefines(Opts, Builder); 6179 } 6180 }; 6181 6182 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6183 const llvm::Triple Triple; 6184 public: 6185 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6186 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6187 WCharType = UnsignedShort; 6188 SizeType = UnsignedInt; 6189 } 6190 void getVisualStudioDefines(const LangOptions &Opts, 6191 MacroBuilder &Builder) const { 6192 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6193 6194 // FIXME: this is invalid for WindowsCE 6195 Builder.defineMacro("_M_ARM_NT", "1"); 6196 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6197 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6198 6199 assert((Triple.getArch() == llvm::Triple::arm || 6200 Triple.getArch() == llvm::Triple::thumb) && 6201 "invalid architecture for Windows ARM target info"); 6202 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6203 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6204 6205 // TODO map the complete set of values 6206 // 31: VFPv3 40: VFPv4 6207 Builder.defineMacro("_M_ARM_FP", "31"); 6208 } 6209 BuiltinVaListKind getBuiltinVaListKind() const override { 6210 return TargetInfo::CharPtrBuiltinVaList; 6211 } 6212 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6213 switch (CC) { 6214 case CC_X86StdCall: 6215 case CC_X86ThisCall: 6216 case CC_X86FastCall: 6217 case CC_X86VectorCall: 6218 return CCCR_Ignore; 6219 case CC_C: 6220 case CC_OpenCLKernel: 6221 return CCCR_OK; 6222 default: 6223 return CCCR_Warning; 6224 } 6225 } 6226 }; 6227 6228 // Windows ARM + Itanium C++ ABI Target 6229 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6230 public: 6231 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6232 const TargetOptions &Opts) 6233 : WindowsARMTargetInfo(Triple, Opts) { 6234 TheCXXABI.set(TargetCXXABI::GenericARM); 6235 } 6236 6237 void getTargetDefines(const LangOptions &Opts, 6238 MacroBuilder &Builder) const override { 6239 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6240 6241 if (Opts.MSVCCompat) 6242 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6243 } 6244 }; 6245 6246 // Windows ARM, MS (C++) ABI 6247 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6248 public: 6249 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6250 const TargetOptions &Opts) 6251 : WindowsARMTargetInfo(Triple, Opts) { 6252 TheCXXABI.set(TargetCXXABI::Microsoft); 6253 } 6254 6255 void getTargetDefines(const LangOptions &Opts, 6256 MacroBuilder &Builder) const override { 6257 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6258 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6259 } 6260 }; 6261 6262 // ARM MinGW target 6263 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6264 public: 6265 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6266 : WindowsARMTargetInfo(Triple, Opts) { 6267 TheCXXABI.set(TargetCXXABI::GenericARM); 6268 } 6269 6270 void getTargetDefines(const LangOptions &Opts, 6271 MacroBuilder &Builder) const override { 6272 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6273 DefineStd(Builder, "WIN32", Opts); 6274 DefineStd(Builder, "WINNT", Opts); 6275 Builder.defineMacro("_ARM_"); 6276 addMinGWDefines(Opts, Builder); 6277 } 6278 }; 6279 6280 // ARM Cygwin target 6281 class CygwinARMTargetInfo : public ARMleTargetInfo { 6282 public: 6283 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6284 : ARMleTargetInfo(Triple, Opts) { 6285 TLSSupported = false; 6286 WCharType = UnsignedShort; 6287 DoubleAlign = LongLongAlign = 64; 6288 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6289 } 6290 void getTargetDefines(const LangOptions &Opts, 6291 MacroBuilder &Builder) const override { 6292 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6293 Builder.defineMacro("_ARM_"); 6294 Builder.defineMacro("__CYGWIN__"); 6295 Builder.defineMacro("__CYGWIN32__"); 6296 DefineStd(Builder, "unix", Opts); 6297 if (Opts.CPlusPlus) 6298 Builder.defineMacro("_GNU_SOURCE"); 6299 } 6300 }; 6301 6302 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6303 protected: 6304 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6305 MacroBuilder &Builder) const override { 6306 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6307 } 6308 6309 public: 6310 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6311 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6312 HasAlignMac68kSupport = true; 6313 // iOS always has 64-bit atomic instructions. 6314 // FIXME: This should be based off of the target features in 6315 // ARMleTargetInfo. 6316 MaxAtomicInlineWidth = 64; 6317 6318 if (Triple.isWatchABI()) { 6319 // Darwin on iOS uses a variant of the ARM C++ ABI. 6320 TheCXXABI.set(TargetCXXABI::WatchOS); 6321 6322 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6323 // size_t is long, it's a bit weird for it to be int. 6324 PtrDiffType = SignedLong; 6325 6326 // BOOL should be a real boolean on the new ABI 6327 UseSignedCharForObjCBool = false; 6328 } else 6329 TheCXXABI.set(TargetCXXABI::iOS); 6330 } 6331 }; 6332 6333 class AArch64TargetInfo : public TargetInfo { 6334 virtual void setDataLayout() = 0; 6335 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6336 static const char *const GCCRegNames[]; 6337 6338 enum FPUModeEnum { 6339 FPUMode, 6340 NeonMode = (1 << 0), 6341 SveMode = (1 << 1) 6342 }; 6343 6344 unsigned FPU; 6345 unsigned CRC; 6346 unsigned Crypto; 6347 unsigned Unaligned; 6348 unsigned HasFullFP16; 6349 llvm::AArch64::ArchKind ArchKind; 6350 6351 static const Builtin::Info BuiltinInfo[]; 6352 6353 std::string ABI; 6354 6355 public: 6356 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6357 : TargetInfo(Triple), ABI("aapcs") { 6358 if (getTriple().getOS() == llvm::Triple::NetBSD || 6359 getTriple().getOS() == llvm::Triple::OpenBSD) { 6360 WCharType = SignedInt; 6361 6362 // NetBSD apparently prefers consistency across ARM targets to consistency 6363 // across 64-bit targets. 6364 Int64Type = SignedLongLong; 6365 IntMaxType = SignedLongLong; 6366 } else { 6367 WCharType = UnsignedInt; 6368 Int64Type = SignedLong; 6369 IntMaxType = SignedLong; 6370 } 6371 6372 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6373 MaxVectorAlign = 128; 6374 MaxAtomicInlineWidth = 128; 6375 MaxAtomicPromoteWidth = 128; 6376 6377 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6378 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6379 6380 // Make __builtin_ms_va_list available. 6381 HasBuiltinMSVaList = true; 6382 6383 // {} in inline assembly are neon specifiers, not assembly variant 6384 // specifiers. 6385 NoAsmVariants = true; 6386 6387 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6388 // contributes to the alignment of the containing aggregate in the same way 6389 // a plain (non bit-field) member of that type would, without exception for 6390 // zero-sized or anonymous bit-fields." 6391 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6392 UseZeroLengthBitfieldAlignment = true; 6393 6394 // AArch64 targets default to using the ARM C++ ABI. 6395 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6396 6397 if (Triple.getOS() == llvm::Triple::Linux) 6398 this->MCountName = "\01_mcount"; 6399 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6400 this->MCountName = Opts.EABIVersion == llvm::EABI::GNU ? "\01_mcount" : "mcount"; 6401 } 6402 6403 StringRef getABI() const override { return ABI; } 6404 bool setABI(const std::string &Name) override { 6405 if (Name != "aapcs" && Name != "darwinpcs") 6406 return false; 6407 6408 ABI = Name; 6409 return true; 6410 } 6411 6412 bool isValidCPUName(StringRef Name) const override { 6413 return Name == "generic" || 6414 llvm::AArch64::parseCPUArch(Name) != 6415 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6416 } 6417 6418 bool setCPU(const std::string &Name) override { 6419 return isValidCPUName(Name); 6420 } 6421 6422 void getTargetDefinesARMV81A(const LangOptions &Opts, 6423 MacroBuilder &Builder) const { 6424 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6425 } 6426 6427 void getTargetDefinesARMV82A(const LangOptions &Opts, 6428 MacroBuilder &Builder) const { 6429 // Also include the ARMv8.1 defines 6430 getTargetDefinesARMV81A(Opts, Builder); 6431 } 6432 6433 void getTargetDefines(const LangOptions &Opts, 6434 MacroBuilder &Builder) const override { 6435 // Target identification. 6436 Builder.defineMacro("__aarch64__"); 6437 // For bare-metal none-eabi. 6438 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6439 (getTriple().getEnvironment() == llvm::Triple::EABI || 6440 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6441 Builder.defineMacro("__ELF__"); 6442 6443 // Target properties. 6444 Builder.defineMacro("_LP64"); 6445 Builder.defineMacro("__LP64__"); 6446 6447 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6448 Builder.defineMacro("__ARM_ACLE", "200"); 6449 Builder.defineMacro("__ARM_ARCH", "8"); 6450 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6451 6452 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6453 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6454 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6455 6456 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6457 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6458 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6459 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6460 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6461 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6462 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6463 6464 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6465 6466 // 0xe implies support for half, single and double precision operations. 6467 Builder.defineMacro("__ARM_FP", "0xE"); 6468 6469 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6470 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6471 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6472 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6473 6474 if (Opts.UnsafeFPMath) 6475 Builder.defineMacro("__ARM_FP_FAST", "1"); 6476 6477 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6478 6479 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6480 Opts.ShortEnums ? "1" : "4"); 6481 6482 if (FPU & NeonMode) { 6483 Builder.defineMacro("__ARM_NEON", "1"); 6484 // 64-bit NEON supports half, single and double precision operations. 6485 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6486 } 6487 6488 if (FPU & SveMode) 6489 Builder.defineMacro("__ARM_FEATURE_SVE", "1"); 6490 6491 if (CRC) 6492 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6493 6494 if (Crypto) 6495 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6496 6497 if (Unaligned) 6498 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6499 6500 switch(ArchKind) { 6501 default: break; 6502 case llvm::AArch64::ArchKind::AK_ARMV8_1A: 6503 getTargetDefinesARMV81A(Opts, Builder); 6504 break; 6505 case llvm::AArch64::ArchKind::AK_ARMV8_2A: 6506 getTargetDefinesARMV82A(Opts, Builder); 6507 break; 6508 } 6509 6510 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6511 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6512 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6513 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6514 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6515 } 6516 6517 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6518 return llvm::makeArrayRef(BuiltinInfo, 6519 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6520 } 6521 6522 bool hasFeature(StringRef Feature) const override { 6523 return Feature == "aarch64" || 6524 Feature == "arm64" || 6525 Feature == "arm" || 6526 (Feature == "neon" && (FPU & NeonMode)) || 6527 (Feature == "sve" && (FPU & SveMode)); 6528 } 6529 6530 bool handleTargetFeatures(std::vector<std::string> &Features, 6531 DiagnosticsEngine &Diags) override { 6532 FPU = FPUMode; 6533 CRC = 0; 6534 Crypto = 0; 6535 Unaligned = 1; 6536 HasFullFP16 = 0; 6537 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8A; 6538 6539 for (const auto &Feature : Features) { 6540 if (Feature == "+neon") 6541 FPU |= NeonMode; 6542 if (Feature == "+sve") 6543 FPU |= SveMode; 6544 if (Feature == "+crc") 6545 CRC = 1; 6546 if (Feature == "+crypto") 6547 Crypto = 1; 6548 if (Feature == "+strict-align") 6549 Unaligned = 0; 6550 if (Feature == "+v8.1a") 6551 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_1A; 6552 if (Feature == "+v8.2a") 6553 ArchKind = llvm::AArch64::ArchKind::AK_ARMV8_2A; 6554 if (Feature == "+fullfp16") 6555 HasFullFP16 = 1; 6556 } 6557 6558 setDataLayout(); 6559 6560 return true; 6561 } 6562 6563 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6564 switch (CC) { 6565 case CC_C: 6566 case CC_Swift: 6567 case CC_PreserveMost: 6568 case CC_PreserveAll: 6569 case CC_OpenCLKernel: 6570 case CC_Win64: 6571 return CCCR_OK; 6572 default: 6573 return CCCR_Warning; 6574 } 6575 } 6576 6577 bool isCLZForZeroUndef() const override { return false; } 6578 6579 BuiltinVaListKind getBuiltinVaListKind() const override { 6580 return TargetInfo::AArch64ABIBuiltinVaList; 6581 } 6582 6583 ArrayRef<const char *> getGCCRegNames() const override; 6584 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6585 6586 bool validateAsmConstraint(const char *&Name, 6587 TargetInfo::ConstraintInfo &Info) const override { 6588 switch (*Name) { 6589 default: 6590 return false; 6591 case 'w': // Floating point and SIMD registers (V0-V31) 6592 Info.setAllowsRegister(); 6593 return true; 6594 case 'I': // Constant that can be used with an ADD instruction 6595 case 'J': // Constant that can be used with a SUB instruction 6596 case 'K': // Constant that can be used with a 32-bit logical instruction 6597 case 'L': // Constant that can be used with a 64-bit logical instruction 6598 case 'M': // Constant that can be used as a 32-bit MOV immediate 6599 case 'N': // Constant that can be used as a 64-bit MOV immediate 6600 case 'Y': // Floating point constant zero 6601 case 'Z': // Integer constant zero 6602 return true; 6603 case 'Q': // A memory reference with base register and no offset 6604 Info.setAllowsMemory(); 6605 return true; 6606 case 'S': // A symbolic address 6607 Info.setAllowsRegister(); 6608 return true; 6609 case 'U': 6610 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6611 // Utf: A memory address suitable for ldp/stp in TF mode. 6612 // Usa: An absolute symbolic address. 6613 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6614 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6615 case 'z': // Zero register, wzr or xzr 6616 Info.setAllowsRegister(); 6617 return true; 6618 case 'x': // Floating point and SIMD registers (V0-V15) 6619 Info.setAllowsRegister(); 6620 return true; 6621 } 6622 return false; 6623 } 6624 6625 bool 6626 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6627 std::string &SuggestedModifier) const override { 6628 // Strip off constraint modifiers. 6629 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6630 Constraint = Constraint.substr(1); 6631 6632 switch (Constraint[0]) { 6633 default: 6634 return true; 6635 case 'z': 6636 case 'r': { 6637 switch (Modifier) { 6638 case 'x': 6639 case 'w': 6640 // For now assume that the person knows what they're 6641 // doing with the modifier. 6642 return true; 6643 default: 6644 // By default an 'r' constraint will be in the 'x' 6645 // registers. 6646 if (Size == 64) 6647 return true; 6648 6649 SuggestedModifier = "w"; 6650 return false; 6651 } 6652 } 6653 } 6654 } 6655 6656 const char *getClobbers() const override { return ""; } 6657 6658 int getEHDataRegisterNumber(unsigned RegNo) const override { 6659 if (RegNo == 0) 6660 return 0; 6661 if (RegNo == 1) 6662 return 1; 6663 return -1; 6664 } 6665 }; 6666 6667 const char *const AArch64TargetInfo::GCCRegNames[] = { 6668 // 32-bit Integer registers 6669 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6670 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6671 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6672 6673 // 64-bit Integer registers 6674 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6675 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6676 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6677 6678 // 32-bit floating point regsisters 6679 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6680 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6681 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6682 6683 // 64-bit floating point regsisters 6684 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6685 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6686 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6687 6688 // Vector registers 6689 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6690 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6691 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6692 }; 6693 6694 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6695 return llvm::makeArrayRef(GCCRegNames); 6696 } 6697 6698 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6699 { { "w31" }, "wsp" }, 6700 { { "x29" }, "fp" }, 6701 { { "x30" }, "lr" }, 6702 { { "x31" }, "sp" }, 6703 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6704 // don't want to substitute one of these for a different-sized one. 6705 }; 6706 6707 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6708 return llvm::makeArrayRef(GCCRegAliases); 6709 } 6710 6711 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6712 #define BUILTIN(ID, TYPE, ATTRS) \ 6713 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6714 #include "clang/Basic/BuiltinsNEON.def" 6715 6716 #define BUILTIN(ID, TYPE, ATTRS) \ 6717 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6718 #include "clang/Basic/BuiltinsAArch64.def" 6719 }; 6720 6721 class AArch64leTargetInfo : public AArch64TargetInfo { 6722 void setDataLayout() override { 6723 if (getTriple().isOSBinFormatMachO()) 6724 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6725 else 6726 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6727 } 6728 6729 public: 6730 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6731 : AArch64TargetInfo(Triple, Opts) { 6732 } 6733 void getTargetDefines(const LangOptions &Opts, 6734 MacroBuilder &Builder) const override { 6735 Builder.defineMacro("__AARCH64EL__"); 6736 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6737 } 6738 }; 6739 6740 class MicrosoftARM64TargetInfo 6741 : public WindowsTargetInfo<AArch64leTargetInfo> { 6742 const llvm::Triple Triple; 6743 6744 public: 6745 MicrosoftARM64TargetInfo(const llvm::Triple &Triple, 6746 const TargetOptions &Opts) 6747 : WindowsTargetInfo<AArch64leTargetInfo>(Triple, Opts), Triple(Triple) { 6748 6749 // This is an LLP64 platform. 6750 // int:4, long:4, long long:8, long double:8. 6751 WCharType = UnsignedShort; 6752 IntWidth = IntAlign = 32; 6753 LongWidth = LongAlign = 32; 6754 DoubleAlign = LongLongAlign = 64; 6755 LongDoubleWidth = LongDoubleAlign = 64; 6756 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6757 IntMaxType = SignedLongLong; 6758 Int64Type = SignedLongLong; 6759 SizeType = UnsignedLongLong; 6760 PtrDiffType = SignedLongLong; 6761 IntPtrType = SignedLongLong; 6762 6763 TheCXXABI.set(TargetCXXABI::Microsoft); 6764 } 6765 6766 void setDataLayout() override { 6767 resetDataLayout("e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"); 6768 } 6769 6770 void getVisualStudioDefines(const LangOptions &Opts, 6771 MacroBuilder &Builder) const { 6772 WindowsTargetInfo<AArch64leTargetInfo>::getVisualStudioDefines(Opts, 6773 Builder); 6774 Builder.defineMacro("_WIN32", "1"); 6775 Builder.defineMacro("_WIN64", "1"); 6776 Builder.defineMacro("_M_ARM64", "1"); 6777 } 6778 6779 void getTargetDefines(const LangOptions &Opts, 6780 MacroBuilder &Builder) const override { 6781 WindowsTargetInfo::getTargetDefines(Opts, Builder); 6782 getVisualStudioDefines(Opts, Builder); 6783 } 6784 6785 BuiltinVaListKind getBuiltinVaListKind() const override { 6786 return TargetInfo::CharPtrBuiltinVaList; 6787 } 6788 }; 6789 6790 class AArch64beTargetInfo : public AArch64TargetInfo { 6791 void setDataLayout() override { 6792 assert(!getTriple().isOSBinFormatMachO()); 6793 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6794 } 6795 6796 public: 6797 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6798 : AArch64TargetInfo(Triple, Opts) {} 6799 void getTargetDefines(const LangOptions &Opts, 6800 MacroBuilder &Builder) const override { 6801 Builder.defineMacro("__AARCH64EB__"); 6802 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6803 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6804 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6805 } 6806 }; 6807 6808 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6809 protected: 6810 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6811 MacroBuilder &Builder) const override { 6812 Builder.defineMacro("__AARCH64_SIMD__"); 6813 Builder.defineMacro("__ARM64_ARCH_8__"); 6814 Builder.defineMacro("__ARM_NEON__"); 6815 Builder.defineMacro("__LITTLE_ENDIAN__"); 6816 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6817 Builder.defineMacro("__arm64", "1"); 6818 Builder.defineMacro("__arm64__", "1"); 6819 6820 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6821 } 6822 6823 public: 6824 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6825 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6826 Int64Type = SignedLongLong; 6827 WCharType = SignedInt; 6828 UseSignedCharForObjCBool = false; 6829 6830 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6831 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6832 6833 TheCXXABI.set(TargetCXXABI::iOS64); 6834 } 6835 6836 BuiltinVaListKind getBuiltinVaListKind() const override { 6837 return TargetInfo::CharPtrBuiltinVaList; 6838 } 6839 }; 6840 6841 // Hexagon abstract base class 6842 class HexagonTargetInfo : public TargetInfo { 6843 static const Builtin::Info BuiltinInfo[]; 6844 static const char * const GCCRegNames[]; 6845 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6846 std::string CPU; 6847 bool HasHVX, HasHVXDouble; 6848 bool UseLongCalls; 6849 6850 public: 6851 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6852 : TargetInfo(Triple) { 6853 // Specify the vector alignment explicitly. For v512x1, the calculated 6854 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6855 // the required minimum of 64 bytes. 6856 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6857 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6858 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6859 SizeType = UnsignedInt; 6860 PtrDiffType = SignedInt; 6861 IntPtrType = SignedInt; 6862 6863 // {} in inline assembly are packet specifiers, not assembly variant 6864 // specifiers. 6865 NoAsmVariants = true; 6866 6867 LargeArrayMinWidth = 64; 6868 LargeArrayAlign = 64; 6869 UseBitFieldTypeAlignment = true; 6870 ZeroLengthBitfieldBoundary = 32; 6871 HasHVX = HasHVXDouble = false; 6872 UseLongCalls = false; 6873 } 6874 6875 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6876 return llvm::makeArrayRef(BuiltinInfo, 6877 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6878 } 6879 6880 bool validateAsmConstraint(const char *&Name, 6881 TargetInfo::ConstraintInfo &Info) const override { 6882 switch (*Name) { 6883 case 'v': 6884 case 'q': 6885 if (HasHVX) { 6886 Info.setAllowsRegister(); 6887 return true; 6888 } 6889 break; 6890 case 's': 6891 // Relocatable constant. 6892 return true; 6893 } 6894 return false; 6895 } 6896 6897 void getTargetDefines(const LangOptions &Opts, 6898 MacroBuilder &Builder) const override; 6899 6900 bool isCLZForZeroUndef() const override { return false; } 6901 6902 bool hasFeature(StringRef Feature) const override { 6903 return llvm::StringSwitch<bool>(Feature) 6904 .Case("hexagon", true) 6905 .Case("hvx", HasHVX) 6906 .Case("hvx-double", HasHVXDouble) 6907 .Case("long-calls", UseLongCalls) 6908 .Default(false); 6909 } 6910 6911 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6912 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6913 const override; 6914 6915 bool handleTargetFeatures(std::vector<std::string> &Features, 6916 DiagnosticsEngine &Diags) override; 6917 6918 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6919 bool Enabled) const override; 6920 6921 BuiltinVaListKind getBuiltinVaListKind() const override { 6922 return TargetInfo::CharPtrBuiltinVaList; 6923 } 6924 ArrayRef<const char *> getGCCRegNames() const override; 6925 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6926 const char *getClobbers() const override { 6927 return ""; 6928 } 6929 6930 static const char *getHexagonCPUSuffix(StringRef Name) { 6931 return llvm::StringSwitch<const char*>(Name) 6932 .Case("hexagonv4", "4") 6933 .Case("hexagonv5", "5") 6934 .Case("hexagonv55", "55") 6935 .Case("hexagonv60", "60") 6936 .Case("hexagonv62", "62") 6937 .Default(nullptr); 6938 } 6939 6940 bool isValidCPUName(StringRef Name) const override { 6941 return getHexagonCPUSuffix(Name); 6942 } 6943 6944 bool setCPU(const std::string &Name) override { 6945 if (!isValidCPUName(Name)) 6946 return false; 6947 CPU = Name; 6948 return true; 6949 } 6950 6951 int getEHDataRegisterNumber(unsigned RegNo) const override { 6952 return RegNo < 2 ? RegNo : -1; 6953 } 6954 }; 6955 6956 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6957 MacroBuilder &Builder) const { 6958 Builder.defineMacro("__qdsp6__", "1"); 6959 Builder.defineMacro("__hexagon__", "1"); 6960 6961 if (CPU == "hexagonv4") { 6962 Builder.defineMacro("__HEXAGON_V4__"); 6963 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6964 if (Opts.HexagonQdsp6Compat) { 6965 Builder.defineMacro("__QDSP6_V4__"); 6966 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6967 } 6968 } else if (CPU == "hexagonv5") { 6969 Builder.defineMacro("__HEXAGON_V5__"); 6970 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6971 if(Opts.HexagonQdsp6Compat) { 6972 Builder.defineMacro("__QDSP6_V5__"); 6973 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6974 } 6975 } else if (CPU == "hexagonv55") { 6976 Builder.defineMacro("__HEXAGON_V55__"); 6977 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6978 Builder.defineMacro("__QDSP6_V55__"); 6979 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6980 } else if (CPU == "hexagonv60") { 6981 Builder.defineMacro("__HEXAGON_V60__"); 6982 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6983 Builder.defineMacro("__QDSP6_V60__"); 6984 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6985 } else if (CPU == "hexagonv62") { 6986 Builder.defineMacro("__HEXAGON_V62__"); 6987 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6988 } 6989 6990 if (hasFeature("hvx")) { 6991 Builder.defineMacro("__HVX__"); 6992 if (hasFeature("hvx-double")) 6993 Builder.defineMacro("__HVXDBL__"); 6994 } 6995 } 6996 6997 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6998 DiagnosticsEngine &Diags, StringRef CPU, 6999 const std::vector<std::string> &FeaturesVec) const { 7000 // Default for v60: -hvx, -hvx-double. 7001 Features["hvx"] = false; 7002 Features["hvx-double"] = false; 7003 Features["long-calls"] = false; 7004 7005 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7006 } 7007 7008 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 7009 DiagnosticsEngine &Diags) { 7010 for (auto &F : Features) { 7011 if (F == "+hvx") 7012 HasHVX = true; 7013 else if (F == "-hvx") 7014 HasHVX = HasHVXDouble = false; 7015 else if (F == "+hvx-double") 7016 HasHVX = HasHVXDouble = true; 7017 else if (F == "-hvx-double") 7018 HasHVXDouble = false; 7019 7020 if (F == "+long-calls") 7021 UseLongCalls = true; 7022 else if (F == "-long-calls") 7023 UseLongCalls = false; 7024 } 7025 return true; 7026 } 7027 7028 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 7029 StringRef Name, bool Enabled) const { 7030 if (Enabled) { 7031 if (Name == "hvx-double") 7032 Features["hvx"] = true; 7033 } else { 7034 if (Name == "hvx") 7035 Features["hvx-double"] = false; 7036 } 7037 Features[Name] = Enabled; 7038 } 7039 7040 const char *const HexagonTargetInfo::GCCRegNames[] = { 7041 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7042 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7043 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7044 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 7045 "p0", "p1", "p2", "p3", 7046 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 7047 }; 7048 7049 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 7050 return llvm::makeArrayRef(GCCRegNames); 7051 } 7052 7053 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 7054 { { "sp" }, "r29" }, 7055 { { "fp" }, "r30" }, 7056 { { "lr" }, "r31" }, 7057 }; 7058 7059 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 7060 return llvm::makeArrayRef(GCCRegAliases); 7061 } 7062 7063 7064 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 7065 #define BUILTIN(ID, TYPE, ATTRS) \ 7066 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7068 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7069 #include "clang/Basic/BuiltinsHexagon.def" 7070 }; 7071 7072 class LanaiTargetInfo : public TargetInfo { 7073 // Class for Lanai (32-bit). 7074 // The CPU profiles supported by the Lanai backend 7075 enum CPUKind { 7076 CK_NONE, 7077 CK_V11, 7078 } CPU; 7079 7080 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7081 static const char *const GCCRegNames[]; 7082 7083 public: 7084 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7085 : TargetInfo(Triple) { 7086 // Description string has to be kept in sync with backend. 7087 resetDataLayout("E" // Big endian 7088 "-m:e" // ELF name manging 7089 "-p:32:32" // 32 bit pointers, 32 bit aligned 7090 "-i64:64" // 64 bit integers, 64 bit aligned 7091 "-a:0:32" // 32 bit alignment of objects of aggregate type 7092 "-n32" // 32 bit native integer width 7093 "-S64" // 64 bit natural stack alignment 7094 ); 7095 7096 // Setting RegParmMax equal to what mregparm was set to in the old 7097 // toolchain 7098 RegParmMax = 4; 7099 7100 // Set the default CPU to V11 7101 CPU = CK_V11; 7102 7103 // Temporary approach to make everything at least word-aligned and allow for 7104 // safely casting between pointers with different alignment requirements. 7105 // TODO: Remove this when there are no more cast align warnings on the 7106 // firmware. 7107 MinGlobalAlign = 32; 7108 } 7109 7110 void getTargetDefines(const LangOptions &Opts, 7111 MacroBuilder &Builder) const override { 7112 // Define __lanai__ when building for target lanai. 7113 Builder.defineMacro("__lanai__"); 7114 7115 // Set define for the CPU specified. 7116 switch (CPU) { 7117 case CK_V11: 7118 Builder.defineMacro("__LANAI_V11__"); 7119 break; 7120 case CK_NONE: 7121 llvm_unreachable("Unhandled target CPU"); 7122 } 7123 } 7124 7125 bool isValidCPUName(StringRef Name) const override { 7126 return llvm::StringSwitch<bool>(Name) 7127 .Case("v11", true) 7128 .Default(false); 7129 } 7130 7131 bool setCPU(const std::string &Name) override { 7132 CPU = llvm::StringSwitch<CPUKind>(Name) 7133 .Case("v11", CK_V11) 7134 .Default(CK_NONE); 7135 7136 return CPU != CK_NONE; 7137 } 7138 7139 bool hasFeature(StringRef Feature) const override { 7140 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 7141 } 7142 7143 ArrayRef<const char *> getGCCRegNames() const override; 7144 7145 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7146 7147 BuiltinVaListKind getBuiltinVaListKind() const override { 7148 return TargetInfo::VoidPtrBuiltinVaList; 7149 } 7150 7151 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7152 7153 bool validateAsmConstraint(const char *&Name, 7154 TargetInfo::ConstraintInfo &info) const override { 7155 return false; 7156 } 7157 7158 const char *getClobbers() const override { return ""; } 7159 }; 7160 7161 const char *const LanaiTargetInfo::GCCRegNames[] = { 7162 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 7163 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 7164 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 7165 7166 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 7167 return llvm::makeArrayRef(GCCRegNames); 7168 } 7169 7170 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 7171 {{"pc"}, "r2"}, 7172 {{"sp"}, "r4"}, 7173 {{"fp"}, "r5"}, 7174 {{"rv"}, "r8"}, 7175 {{"rr1"}, "r10"}, 7176 {{"rr2"}, "r11"}, 7177 {{"rca"}, "r15"}, 7178 }; 7179 7180 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 7181 return llvm::makeArrayRef(GCCRegAliases); 7182 } 7183 7184 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 7185 class SparcTargetInfo : public TargetInfo { 7186 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 7187 static const char * const GCCRegNames[]; 7188 bool SoftFloat; 7189 public: 7190 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7191 : TargetInfo(Triple), SoftFloat(false) {} 7192 7193 int getEHDataRegisterNumber(unsigned RegNo) const override { 7194 if (RegNo == 0) return 24; 7195 if (RegNo == 1) return 25; 7196 return -1; 7197 } 7198 7199 bool handleTargetFeatures(std::vector<std::string> &Features, 7200 DiagnosticsEngine &Diags) override { 7201 // Check if software floating point is enabled 7202 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 7203 if (Feature != Features.end()) { 7204 SoftFloat = true; 7205 } 7206 return true; 7207 } 7208 void getTargetDefines(const LangOptions &Opts, 7209 MacroBuilder &Builder) const override { 7210 DefineStd(Builder, "sparc", Opts); 7211 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7212 7213 if (SoftFloat) 7214 Builder.defineMacro("SOFT_FLOAT", "1"); 7215 } 7216 7217 bool hasFeature(StringRef Feature) const override { 7218 return llvm::StringSwitch<bool>(Feature) 7219 .Case("softfloat", SoftFloat) 7220 .Case("sparc", true) 7221 .Default(false); 7222 } 7223 7224 bool hasSjLjLowering() const override { 7225 return true; 7226 } 7227 7228 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7229 // FIXME: Implement! 7230 return None; 7231 } 7232 BuiltinVaListKind getBuiltinVaListKind() const override { 7233 return TargetInfo::VoidPtrBuiltinVaList; 7234 } 7235 ArrayRef<const char *> getGCCRegNames() const override; 7236 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7237 bool validateAsmConstraint(const char *&Name, 7238 TargetInfo::ConstraintInfo &info) const override { 7239 // FIXME: Implement! 7240 switch (*Name) { 7241 case 'I': // Signed 13-bit constant 7242 case 'J': // Zero 7243 case 'K': // 32-bit constant with the low 12 bits clear 7244 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 7245 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 7246 case 'N': // Same as 'K' but zext (required for SIMode) 7247 case 'O': // The constant 4096 7248 return true; 7249 7250 case 'f': 7251 case 'e': 7252 info.setAllowsRegister(); 7253 return true; 7254 } 7255 return false; 7256 } 7257 const char *getClobbers() const override { 7258 // FIXME: Implement! 7259 return ""; 7260 } 7261 7262 // No Sparc V7 for now, the backend doesn't support it anyway. 7263 enum CPUKind { 7264 CK_GENERIC, 7265 CK_V8, 7266 CK_SUPERSPARC, 7267 CK_SPARCLITE, 7268 CK_F934, 7269 CK_HYPERSPARC, 7270 CK_SPARCLITE86X, 7271 CK_SPARCLET, 7272 CK_TSC701, 7273 CK_V9, 7274 CK_ULTRASPARC, 7275 CK_ULTRASPARC3, 7276 CK_NIAGARA, 7277 CK_NIAGARA2, 7278 CK_NIAGARA3, 7279 CK_NIAGARA4, 7280 CK_MYRIAD2100, 7281 CK_MYRIAD2150, 7282 CK_MYRIAD2450, 7283 CK_LEON2, 7284 CK_LEON2_AT697E, 7285 CK_LEON2_AT697F, 7286 CK_LEON3, 7287 CK_LEON3_UT699, 7288 CK_LEON3_GR712RC, 7289 CK_LEON4, 7290 CK_LEON4_GR740 7291 } CPU = CK_GENERIC; 7292 7293 enum CPUGeneration { 7294 CG_V8, 7295 CG_V9, 7296 }; 7297 7298 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7299 switch (Kind) { 7300 case CK_GENERIC: 7301 case CK_V8: 7302 case CK_SUPERSPARC: 7303 case CK_SPARCLITE: 7304 case CK_F934: 7305 case CK_HYPERSPARC: 7306 case CK_SPARCLITE86X: 7307 case CK_SPARCLET: 7308 case CK_TSC701: 7309 case CK_MYRIAD2100: 7310 case CK_MYRIAD2150: 7311 case CK_MYRIAD2450: 7312 case CK_LEON2: 7313 case CK_LEON2_AT697E: 7314 case CK_LEON2_AT697F: 7315 case CK_LEON3: 7316 case CK_LEON3_UT699: 7317 case CK_LEON3_GR712RC: 7318 case CK_LEON4: 7319 case CK_LEON4_GR740: 7320 return CG_V8; 7321 case CK_V9: 7322 case CK_ULTRASPARC: 7323 case CK_ULTRASPARC3: 7324 case CK_NIAGARA: 7325 case CK_NIAGARA2: 7326 case CK_NIAGARA3: 7327 case CK_NIAGARA4: 7328 return CG_V9; 7329 } 7330 llvm_unreachable("Unexpected CPU kind"); 7331 } 7332 7333 CPUKind getCPUKind(StringRef Name) const { 7334 return llvm::StringSwitch<CPUKind>(Name) 7335 .Case("v8", CK_V8) 7336 .Case("supersparc", CK_SUPERSPARC) 7337 .Case("sparclite", CK_SPARCLITE) 7338 .Case("f934", CK_F934) 7339 .Case("hypersparc", CK_HYPERSPARC) 7340 .Case("sparclite86x", CK_SPARCLITE86X) 7341 .Case("sparclet", CK_SPARCLET) 7342 .Case("tsc701", CK_TSC701) 7343 .Case("v9", CK_V9) 7344 .Case("ultrasparc", CK_ULTRASPARC) 7345 .Case("ultrasparc3", CK_ULTRASPARC3) 7346 .Case("niagara", CK_NIAGARA) 7347 .Case("niagara2", CK_NIAGARA2) 7348 .Case("niagara3", CK_NIAGARA3) 7349 .Case("niagara4", CK_NIAGARA4) 7350 .Case("ma2100", CK_MYRIAD2100) 7351 .Case("ma2150", CK_MYRIAD2150) 7352 .Case("ma2450", CK_MYRIAD2450) 7353 // FIXME: the myriad2[.n] spellings are obsolete, 7354 // but a grace period is needed to allow updating dependent builds. 7355 .Case("myriad2", CK_MYRIAD2100) 7356 .Case("myriad2.1", CK_MYRIAD2100) 7357 .Case("myriad2.2", CK_MYRIAD2150) 7358 .Case("leon2", CK_LEON2) 7359 .Case("at697e", CK_LEON2_AT697E) 7360 .Case("at697f", CK_LEON2_AT697F) 7361 .Case("leon3", CK_LEON3) 7362 .Case("ut699", CK_LEON3_UT699) 7363 .Case("gr712rc", CK_LEON3_GR712RC) 7364 .Case("leon4", CK_LEON4) 7365 .Case("gr740", CK_LEON4_GR740) 7366 .Default(CK_GENERIC); 7367 } 7368 7369 bool isValidCPUName(StringRef Name) const override { 7370 return getCPUKind(Name) != CK_GENERIC; 7371 } 7372 7373 bool setCPU(const std::string &Name) override { 7374 CPU = getCPUKind(Name); 7375 return CPU != CK_GENERIC; 7376 } 7377 }; 7378 7379 const char * const SparcTargetInfo::GCCRegNames[] = { 7380 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7381 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7382 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7383 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7384 }; 7385 7386 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7387 return llvm::makeArrayRef(GCCRegNames); 7388 } 7389 7390 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7391 { { "g0" }, "r0" }, 7392 { { "g1" }, "r1" }, 7393 { { "g2" }, "r2" }, 7394 { { "g3" }, "r3" }, 7395 { { "g4" }, "r4" }, 7396 { { "g5" }, "r5" }, 7397 { { "g6" }, "r6" }, 7398 { { "g7" }, "r7" }, 7399 { { "o0" }, "r8" }, 7400 { { "o1" }, "r9" }, 7401 { { "o2" }, "r10" }, 7402 { { "o3" }, "r11" }, 7403 { { "o4" }, "r12" }, 7404 { { "o5" }, "r13" }, 7405 { { "o6", "sp" }, "r14" }, 7406 { { "o7" }, "r15" }, 7407 { { "l0" }, "r16" }, 7408 { { "l1" }, "r17" }, 7409 { { "l2" }, "r18" }, 7410 { { "l3" }, "r19" }, 7411 { { "l4" }, "r20" }, 7412 { { "l5" }, "r21" }, 7413 { { "l6" }, "r22" }, 7414 { { "l7" }, "r23" }, 7415 { { "i0" }, "r24" }, 7416 { { "i1" }, "r25" }, 7417 { { "i2" }, "r26" }, 7418 { { "i3" }, "r27" }, 7419 { { "i4" }, "r28" }, 7420 { { "i5" }, "r29" }, 7421 { { "i6", "fp" }, "r30" }, 7422 { { "i7" }, "r31" }, 7423 }; 7424 7425 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7426 return llvm::makeArrayRef(GCCRegAliases); 7427 } 7428 7429 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7430 class SparcV8TargetInfo : public SparcTargetInfo { 7431 public: 7432 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7433 : SparcTargetInfo(Triple, Opts) { 7434 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7435 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7436 switch (getTriple().getOS()) { 7437 default: 7438 SizeType = UnsignedInt; 7439 IntPtrType = SignedInt; 7440 PtrDiffType = SignedInt; 7441 break; 7442 case llvm::Triple::NetBSD: 7443 case llvm::Triple::OpenBSD: 7444 SizeType = UnsignedLong; 7445 IntPtrType = SignedLong; 7446 PtrDiffType = SignedLong; 7447 break; 7448 } 7449 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7450 // on up to 64 bits. 7451 MaxAtomicPromoteWidth = 64; 7452 MaxAtomicInlineWidth = 32; 7453 } 7454 7455 void getTargetDefines(const LangOptions &Opts, 7456 MacroBuilder &Builder) const override { 7457 SparcTargetInfo::getTargetDefines(Opts, Builder); 7458 switch (getCPUGeneration(CPU)) { 7459 case CG_V8: 7460 Builder.defineMacro("__sparcv8"); 7461 if (getTriple().getOS() != llvm::Triple::Solaris) 7462 Builder.defineMacro("__sparcv8__"); 7463 break; 7464 case CG_V9: 7465 Builder.defineMacro("__sparcv9"); 7466 if (getTriple().getOS() != llvm::Triple::Solaris) { 7467 Builder.defineMacro("__sparcv9__"); 7468 Builder.defineMacro("__sparc_v9__"); 7469 } 7470 break; 7471 } 7472 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7473 std::string MyriadArchValue, Myriad2Value; 7474 Builder.defineMacro("__sparc_v8__"); 7475 Builder.defineMacro("__leon__"); 7476 switch (CPU) { 7477 case CK_MYRIAD2150: 7478 MyriadArchValue = "__ma2150"; 7479 Myriad2Value = "2"; 7480 break; 7481 case CK_MYRIAD2450: 7482 MyriadArchValue = "__ma2450"; 7483 Myriad2Value = "2"; 7484 break; 7485 default: 7486 MyriadArchValue = "__ma2100"; 7487 Myriad2Value = "1"; 7488 break; 7489 } 7490 Builder.defineMacro(MyriadArchValue, "1"); 7491 Builder.defineMacro(MyriadArchValue+"__", "1"); 7492 Builder.defineMacro("__myriad2__", Myriad2Value); 7493 Builder.defineMacro("__myriad2", Myriad2Value); 7494 } 7495 } 7496 7497 bool hasSjLjLowering() const override { 7498 return true; 7499 } 7500 }; 7501 7502 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7503 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7504 public: 7505 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7506 : SparcV8TargetInfo(Triple, Opts) { 7507 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7508 } 7509 }; 7510 7511 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7512 class SparcV9TargetInfo : public SparcTargetInfo { 7513 public: 7514 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7515 : SparcTargetInfo(Triple, Opts) { 7516 // FIXME: Support Sparc quad-precision long double? 7517 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7518 // This is an LP64 platform. 7519 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7520 7521 // OpenBSD uses long long for int64_t and intmax_t. 7522 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7523 IntMaxType = SignedLongLong; 7524 else 7525 IntMaxType = SignedLong; 7526 Int64Type = IntMaxType; 7527 7528 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7529 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7530 LongDoubleWidth = 128; 7531 LongDoubleAlign = 128; 7532 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7533 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7534 } 7535 7536 void getTargetDefines(const LangOptions &Opts, 7537 MacroBuilder &Builder) const override { 7538 SparcTargetInfo::getTargetDefines(Opts, Builder); 7539 Builder.defineMacro("__sparcv9"); 7540 Builder.defineMacro("__arch64__"); 7541 // Solaris doesn't need these variants, but the BSDs do. 7542 if (getTriple().getOS() != llvm::Triple::Solaris) { 7543 Builder.defineMacro("__sparc64__"); 7544 Builder.defineMacro("__sparc_v9__"); 7545 Builder.defineMacro("__sparcv9__"); 7546 } 7547 } 7548 7549 bool isValidCPUName(StringRef Name) const override { 7550 return getCPUGeneration(SparcTargetInfo::getCPUKind(Name)) == CG_V9; 7551 } 7552 7553 bool setCPU(const std::string &Name) override { 7554 if (!SparcTargetInfo::setCPU(Name)) 7555 return false; 7556 return getCPUGeneration(CPU) == CG_V9; 7557 } 7558 }; 7559 7560 class SystemZTargetInfo : public TargetInfo { 7561 static const Builtin::Info BuiltinInfo[]; 7562 static const char *const GCCRegNames[]; 7563 std::string CPU; 7564 int ISARevision; 7565 bool HasTransactionalExecution; 7566 bool HasVector; 7567 7568 public: 7569 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7570 : TargetInfo(Triple), CPU("z10"), ISARevision(8), 7571 HasTransactionalExecution(false), HasVector(false) { 7572 IntMaxType = SignedLong; 7573 Int64Type = SignedLong; 7574 TLSSupported = true; 7575 IntWidth = IntAlign = 32; 7576 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7577 PointerWidth = PointerAlign = 64; 7578 LongDoubleWidth = 128; 7579 LongDoubleAlign = 64; 7580 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7581 DefaultAlignForAttributeAligned = 64; 7582 MinGlobalAlign = 16; 7583 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7584 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7585 } 7586 void getTargetDefines(const LangOptions &Opts, 7587 MacroBuilder &Builder) const override { 7588 Builder.defineMacro("__s390__"); 7589 Builder.defineMacro("__s390x__"); 7590 Builder.defineMacro("__zarch__"); 7591 Builder.defineMacro("__LONG_DOUBLE_128__"); 7592 7593 Builder.defineMacro("__ARCH__", Twine(ISARevision)); 7594 7595 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7596 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7597 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7598 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7599 7600 if (HasTransactionalExecution) 7601 Builder.defineMacro("__HTM__"); 7602 if (HasVector) 7603 Builder.defineMacro("__VX__"); 7604 if (Opts.ZVector) 7605 Builder.defineMacro("__VEC__", "10302"); 7606 } 7607 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7608 return llvm::makeArrayRef(BuiltinInfo, 7609 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7610 } 7611 7612 ArrayRef<const char *> getGCCRegNames() const override; 7613 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7614 // No aliases. 7615 return None; 7616 } 7617 bool validateAsmConstraint(const char *&Name, 7618 TargetInfo::ConstraintInfo &info) const override; 7619 const char *getClobbers() const override { 7620 // FIXME: Is this really right? 7621 return ""; 7622 } 7623 BuiltinVaListKind getBuiltinVaListKind() const override { 7624 return TargetInfo::SystemZBuiltinVaList; 7625 } 7626 int getISARevision(const StringRef &Name) const { 7627 return llvm::StringSwitch<int>(Name) 7628 .Cases("arch8", "z10", 8) 7629 .Cases("arch9", "z196", 9) 7630 .Cases("arch10", "zEC12", 10) 7631 .Cases("arch11", "z13", 11) 7632 .Cases("arch12", "z14", 12) 7633 .Default(-1); 7634 } 7635 7636 bool isValidCPUName(StringRef Name) const override { 7637 return getISARevision(Name) != -1; 7638 } 7639 7640 bool setCPU(const std::string &Name) override { 7641 CPU = Name; 7642 ISARevision = getISARevision(CPU); 7643 return ISARevision != -1; 7644 } 7645 bool 7646 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7647 StringRef CPU, 7648 const std::vector<std::string> &FeaturesVec) const override { 7649 int ISARevision = getISARevision(CPU); 7650 if (ISARevision >= 10) 7651 Features["transactional-execution"] = true; 7652 if (ISARevision >= 11) 7653 Features["vector"] = true; 7654 if (ISARevision >= 12) 7655 Features["vector-enhancements-1"] = true; 7656 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7657 } 7658 7659 bool handleTargetFeatures(std::vector<std::string> &Features, 7660 DiagnosticsEngine &Diags) override { 7661 HasTransactionalExecution = false; 7662 HasVector = false; 7663 for (const auto &Feature : Features) { 7664 if (Feature == "+transactional-execution") 7665 HasTransactionalExecution = true; 7666 else if (Feature == "+vector") 7667 HasVector = true; 7668 } 7669 // If we use the vector ABI, vector types are 64-bit aligned. 7670 if (HasVector) { 7671 MaxVectorAlign = 64; 7672 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7673 "-v128:64-a:8:16-n32:64"); 7674 } 7675 return true; 7676 } 7677 7678 bool hasFeature(StringRef Feature) const override { 7679 return llvm::StringSwitch<bool>(Feature) 7680 .Case("systemz", true) 7681 .Case("arch8", ISARevision >= 8) 7682 .Case("arch9", ISARevision >= 9) 7683 .Case("arch10", ISARevision >= 10) 7684 .Case("arch11", ISARevision >= 11) 7685 .Case("arch12", ISARevision >= 12) 7686 .Case("htm", HasTransactionalExecution) 7687 .Case("vx", HasVector) 7688 .Default(false); 7689 } 7690 7691 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7692 switch (CC) { 7693 case CC_C: 7694 case CC_Swift: 7695 case CC_OpenCLKernel: 7696 return CCCR_OK; 7697 default: 7698 return CCCR_Warning; 7699 } 7700 } 7701 7702 StringRef getABI() const override { 7703 if (HasVector) 7704 return "vector"; 7705 return ""; 7706 } 7707 7708 bool useFloat128ManglingForLongDouble() const override { 7709 return true; 7710 } 7711 }; 7712 7713 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7714 #define BUILTIN(ID, TYPE, ATTRS) \ 7715 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7716 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7717 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7718 #include "clang/Basic/BuiltinsSystemZ.def" 7719 }; 7720 7721 const char *const SystemZTargetInfo::GCCRegNames[] = { 7722 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7723 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7724 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7725 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7726 }; 7727 7728 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7729 return llvm::makeArrayRef(GCCRegNames); 7730 } 7731 7732 bool SystemZTargetInfo:: 7733 validateAsmConstraint(const char *&Name, 7734 TargetInfo::ConstraintInfo &Info) const { 7735 switch (*Name) { 7736 default: 7737 return false; 7738 7739 case 'a': // Address register 7740 case 'd': // Data register (equivalent to 'r') 7741 case 'f': // Floating-point register 7742 Info.setAllowsRegister(); 7743 return true; 7744 7745 case 'I': // Unsigned 8-bit constant 7746 case 'J': // Unsigned 12-bit constant 7747 case 'K': // Signed 16-bit constant 7748 case 'L': // Signed 20-bit displacement (on all targets we support) 7749 case 'M': // 0x7fffffff 7750 return true; 7751 7752 case 'Q': // Memory with base and unsigned 12-bit displacement 7753 case 'R': // Likewise, plus an index 7754 case 'S': // Memory with base and signed 20-bit displacement 7755 case 'T': // Likewise, plus an index 7756 Info.setAllowsMemory(); 7757 return true; 7758 } 7759 } 7760 7761 class MSP430TargetInfo : public TargetInfo { 7762 static const char *const GCCRegNames[]; 7763 7764 public: 7765 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7766 : TargetInfo(Triple) { 7767 TLSSupported = false; 7768 IntWidth = 16; 7769 IntAlign = 16; 7770 LongWidth = 32; 7771 LongLongWidth = 64; 7772 LongAlign = LongLongAlign = 16; 7773 PointerWidth = 16; 7774 PointerAlign = 16; 7775 SuitableAlign = 16; 7776 SizeType = UnsignedInt; 7777 IntMaxType = SignedLongLong; 7778 IntPtrType = SignedInt; 7779 PtrDiffType = SignedInt; 7780 SigAtomicType = SignedLong; 7781 resetDataLayout("e-m:e-p:16:16-i32:16-i64:16-f32:16-f64:16-a:8-n8:16-S16"); 7782 } 7783 void getTargetDefines(const LangOptions &Opts, 7784 MacroBuilder &Builder) const override { 7785 Builder.defineMacro("MSP430"); 7786 Builder.defineMacro("__MSP430__"); 7787 // FIXME: defines for different 'flavours' of MCU 7788 } 7789 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7790 // FIXME: Implement. 7791 return None; 7792 } 7793 bool hasFeature(StringRef Feature) const override { 7794 return Feature == "msp430"; 7795 } 7796 ArrayRef<const char *> getGCCRegNames() const override; 7797 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7798 // No aliases. 7799 return None; 7800 } 7801 bool validateAsmConstraint(const char *&Name, 7802 TargetInfo::ConstraintInfo &info) const override { 7803 // FIXME: implement 7804 switch (*Name) { 7805 case 'K': // the constant 1 7806 case 'L': // constant -1^20 .. 1^19 7807 case 'M': // constant 1-4: 7808 return true; 7809 } 7810 // No target constraints for now. 7811 return false; 7812 } 7813 const char *getClobbers() const override { 7814 // FIXME: Is this really right? 7815 return ""; 7816 } 7817 BuiltinVaListKind getBuiltinVaListKind() const override { 7818 // FIXME: implement 7819 return TargetInfo::CharPtrBuiltinVaList; 7820 } 7821 }; 7822 7823 const char *const MSP430TargetInfo::GCCRegNames[] = { 7824 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7825 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7826 7827 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7828 return llvm::makeArrayRef(GCCRegNames); 7829 } 7830 7831 // LLVM and Clang cannot be used directly to output native binaries for 7832 // target, but is used to compile C code to llvm bitcode with correct 7833 // type and alignment information. 7834 // 7835 // TCE uses the llvm bitcode as input and uses it for generating customized 7836 // target processor and program binary. TCE co-design environment is 7837 // publicly available in http://tce.cs.tut.fi 7838 7839 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7840 0, // Default 7841 3, // opencl_global 7842 4, // opencl_local 7843 5, // opencl_constant 7844 // FIXME: generic has to be added to the target 7845 0, // opencl_generic 7846 0, // cuda_device 7847 0, // cuda_constant 7848 0 // cuda_shared 7849 }; 7850 7851 class TCETargetInfo : public TargetInfo { 7852 public: 7853 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7854 : TargetInfo(Triple) { 7855 TLSSupported = false; 7856 IntWidth = 32; 7857 LongWidth = LongLongWidth = 32; 7858 PointerWidth = 32; 7859 IntAlign = 32; 7860 LongAlign = LongLongAlign = 32; 7861 PointerAlign = 32; 7862 SuitableAlign = 32; 7863 SizeType = UnsignedInt; 7864 IntMaxType = SignedLong; 7865 IntPtrType = SignedInt; 7866 PtrDiffType = SignedInt; 7867 FloatWidth = 32; 7868 FloatAlign = 32; 7869 DoubleWidth = 32; 7870 DoubleAlign = 32; 7871 LongDoubleWidth = 32; 7872 LongDoubleAlign = 32; 7873 FloatFormat = &llvm::APFloat::IEEEsingle(); 7874 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7875 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7876 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7877 "i16:16:32-i32:32:32-i64:32:32-" 7878 "f32:32:32-f64:32:32-v64:32:32-" 7879 "v128:32:32-v256:32:32-v512:32:32-" 7880 "v1024:32:32-a0:0:32-n32"); 7881 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7882 UseAddrSpaceMapMangling = true; 7883 } 7884 7885 void getTargetDefines(const LangOptions &Opts, 7886 MacroBuilder &Builder) const override { 7887 DefineStd(Builder, "tce", Opts); 7888 Builder.defineMacro("__TCE__"); 7889 Builder.defineMacro("__TCE_V1__"); 7890 } 7891 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7892 7893 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7894 const char *getClobbers() const override { return ""; } 7895 BuiltinVaListKind getBuiltinVaListKind() const override { 7896 return TargetInfo::VoidPtrBuiltinVaList; 7897 } 7898 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7899 bool validateAsmConstraint(const char *&Name, 7900 TargetInfo::ConstraintInfo &info) const override { 7901 return true; 7902 } 7903 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7904 return None; 7905 } 7906 }; 7907 7908 class TCELETargetInfo : public TCETargetInfo { 7909 public: 7910 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7911 : TCETargetInfo(Triple, Opts) { 7912 BigEndian = false; 7913 7914 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7915 "i16:16:32-i32:32:32-i64:32:32-" 7916 "f32:32:32-f64:32:32-v64:32:32-" 7917 "v128:32:32-v256:32:32-v512:32:32-" 7918 "v1024:32:32-a0:0:32-n32"); 7919 7920 } 7921 7922 virtual void getTargetDefines(const LangOptions &Opts, 7923 MacroBuilder &Builder) const { 7924 DefineStd(Builder, "tcele", Opts); 7925 Builder.defineMacro("__TCE__"); 7926 Builder.defineMacro("__TCE_V1__"); 7927 Builder.defineMacro("__TCELE__"); 7928 Builder.defineMacro("__TCELE_V1__"); 7929 } 7930 7931 }; 7932 7933 class BPFTargetInfo : public TargetInfo { 7934 public: 7935 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7936 : TargetInfo(Triple) { 7937 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7938 SizeType = UnsignedLong; 7939 PtrDiffType = SignedLong; 7940 IntPtrType = SignedLong; 7941 IntMaxType = SignedLong; 7942 Int64Type = SignedLong; 7943 RegParmMax = 5; 7944 if (Triple.getArch() == llvm::Triple::bpfeb) { 7945 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7946 } else { 7947 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7948 } 7949 MaxAtomicPromoteWidth = 64; 7950 MaxAtomicInlineWidth = 64; 7951 TLSSupported = false; 7952 } 7953 void getTargetDefines(const LangOptions &Opts, 7954 MacroBuilder &Builder) const override { 7955 DefineStd(Builder, "bpf", Opts); 7956 Builder.defineMacro("__BPF__"); 7957 } 7958 bool hasFeature(StringRef Feature) const override { 7959 return Feature == "bpf"; 7960 } 7961 7962 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7963 const char *getClobbers() const override { 7964 return ""; 7965 } 7966 BuiltinVaListKind getBuiltinVaListKind() const override { 7967 return TargetInfo::VoidPtrBuiltinVaList; 7968 } 7969 ArrayRef<const char *> getGCCRegNames() const override { 7970 return None; 7971 } 7972 bool validateAsmConstraint(const char *&Name, 7973 TargetInfo::ConstraintInfo &info) const override { 7974 return true; 7975 } 7976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7977 return None; 7978 } 7979 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7980 switch (CC) { 7981 default: 7982 return CCCR_Warning; 7983 case CC_C: 7984 case CC_OpenCLKernel: 7985 return CCCR_OK; 7986 } 7987 } 7988 }; 7989 7990 class Nios2TargetInfo : public TargetInfo { 7991 void setDataLayout() { 7992 if (BigEndian) 7993 resetDataLayout("E-p:32:32:32-i8:8:32-i16:16:32-n32"); 7994 else 7995 resetDataLayout("e-p:32:32:32-i8:8:32-i16:16:32-n32"); 7996 } 7997 7998 static const Builtin::Info BuiltinInfo[]; 7999 std::string CPU; 8000 std::string ABI; 8001 8002 public: 8003 Nios2TargetInfo(const llvm::Triple &triple, const TargetOptions &opts) 8004 : TargetInfo(triple), CPU(opts.CPU), ABI(opts.ABI) { 8005 SizeType = UnsignedInt; 8006 PtrDiffType = SignedInt; 8007 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8008 setDataLayout(); 8009 } 8010 8011 StringRef getABI() const override { return ABI; } 8012 bool setABI(const std::string &Name) override { 8013 if (Name == "o32" || Name == "eabi") { 8014 ABI = Name; 8015 return true; 8016 } 8017 return false; 8018 } 8019 8020 bool isValidCPUName(StringRef Name) const override { 8021 return Name == "nios2r1" || Name == "nios2r2"; 8022 } 8023 8024 bool setCPU(const std::string &Name) override { 8025 if (isValidCPUName(Name)) { 8026 CPU = Name; 8027 return true; 8028 } 8029 return false; 8030 } 8031 8032 void getTargetDefines(const LangOptions &Opts, 8033 MacroBuilder &Builder) const override { 8034 DefineStd(Builder, "nios2", Opts); 8035 DefineStd(Builder, "NIOS2", Opts); 8036 8037 Builder.defineMacro("__nios2"); 8038 Builder.defineMacro("__NIOS2"); 8039 Builder.defineMacro("__nios2__"); 8040 Builder.defineMacro("__NIOS2__"); 8041 } 8042 8043 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8044 return llvm::makeArrayRef(BuiltinInfo, clang::Nios2::LastTSBuiltin - 8045 Builtin::FirstTSBuiltin); 8046 } 8047 8048 bool isFeatureSupportedByCPU(StringRef Feature, StringRef CPU) const { 8049 const bool isR2 = CPU == "nios2r2"; 8050 return llvm::StringSwitch<bool>(Feature) 8051 .Case("nios2r2mandatory", isR2) 8052 .Case("nios2r2bmx", isR2) 8053 .Case("nios2r2mpx", isR2) 8054 .Case("nios2r2cdx", isR2) 8055 .Default(false); 8056 } 8057 8058 bool initFeatureMap(llvm::StringMap<bool> &Features, 8059 DiagnosticsEngine &Diags, StringRef CPU, 8060 const std::vector<std::string> &FeatureVec) const override { 8061 static const char *allFeatures[] = { 8062 "nios2r2mandatory", "nios2r2bmx", "nios2r2mpx", "nios2r2cdx" 8063 }; 8064 for (const char *feature : allFeatures) { 8065 Features[feature] = isFeatureSupportedByCPU(feature, CPU); 8066 } 8067 return true; 8068 } 8069 8070 bool hasFeature(StringRef Feature) const override { 8071 return isFeatureSupportedByCPU(Feature, CPU); 8072 } 8073 8074 BuiltinVaListKind getBuiltinVaListKind() const override { 8075 return TargetInfo::VoidPtrBuiltinVaList; 8076 } 8077 8078 ArrayRef<const char *> getGCCRegNames() const override { 8079 static const char *const GCCRegNames[] = { 8080 // CPU register names 8081 // Must match second column of GCCRegAliases 8082 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 8083 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", 8084 "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", 8085 "r31", 8086 // Floating point register names 8087 "ctl0", "ctl1", "ctl2", "ctl3", "ctl4", "ctl5", "ctl6", "ctl7", "ctl8", 8088 "ctl9", "ctl10", "ctl11", "ctl12", "ctl13", "ctl14", "ctl15" 8089 }; 8090 return llvm::makeArrayRef(GCCRegNames); 8091 } 8092 8093 bool validateAsmConstraint(const char *&Name, 8094 TargetInfo::ConstraintInfo &Info) const override { 8095 switch (*Name) { 8096 default: 8097 return false; 8098 8099 case 'r': // CPU registers. 8100 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8101 case 'y': // Equivalent to "r", backwards compatibility only. 8102 case 'f': // floating-point registers. 8103 case 'c': // $25 for indirect jumps 8104 case 'l': // lo register 8105 case 'x': // hilo register pair 8106 Info.setAllowsRegister(); 8107 return true; 8108 } 8109 } 8110 8111 const char *getClobbers() const override { return ""; } 8112 8113 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8114 static const TargetInfo::GCCRegAlias aliases[] = { 8115 {{"zero"}, "r0"}, {{"at"}, "r1"}, {{"et"}, "r24"}, 8116 {{"bt"}, "r25"}, {{"gp"}, "r26"}, {{"sp"}, "r27"}, 8117 {{"fp"}, "r28"}, {{"ea"}, "r29"}, {{"ba"}, "r30"}, 8118 {{"ra"}, "r31"}, {{"status"}, "ctl0"}, {{"estatus"}, "ctl1"}, 8119 {{"bstatus"}, "ctl2"}, {{"ienable"}, "ctl3"}, {{"ipending"}, "ctl4"}, 8120 {{"cpuid"}, "ctl5"}, {{"exception"}, "ctl7"}, {{"pteaddr"}, "ctl8"}, 8121 {{"tlbacc"}, "ctl9"}, {{"tlbmisc"}, "ctl10"}, {{"badaddr"}, "ctl12"}, 8122 {{"config"}, "ctl13"}, {{"mpubase"}, "ctl14"}, {{"mpuacc"}, "ctl15"}, 8123 }; 8124 return llvm::makeArrayRef(aliases); 8125 } 8126 }; 8127 8128 const Builtin::Info Nios2TargetInfo::BuiltinInfo[] = { 8129 #define BUILTIN(ID, TYPE, ATTRS) \ 8130 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 8131 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 8132 {#ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE}, 8133 #include "clang/Basic/BuiltinsNios2.def" 8134 }; 8135 8136 class MipsTargetInfo : public TargetInfo { 8137 void setDataLayout() { 8138 StringRef Layout; 8139 8140 if (ABI == "o32") 8141 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 8142 else if (ABI == "n32") 8143 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 8144 else if (ABI == "n64") 8145 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 8146 else 8147 llvm_unreachable("Invalid ABI"); 8148 8149 if (BigEndian) 8150 resetDataLayout(("E-" + Layout).str()); 8151 else 8152 resetDataLayout(("e-" + Layout).str()); 8153 } 8154 8155 8156 static const Builtin::Info BuiltinInfo[]; 8157 std::string CPU; 8158 bool IsMips16; 8159 bool IsMicromips; 8160 bool IsNan2008; 8161 bool IsSingleFloat; 8162 bool IsNoABICalls; 8163 bool CanUseBSDABICalls; 8164 enum MipsFloatABI { 8165 HardFloat, SoftFloat 8166 } FloatABI; 8167 enum DspRevEnum { 8168 NoDSP, DSP1, DSP2 8169 } DspRev; 8170 bool HasMSA; 8171 bool DisableMadd4; 8172 8173 protected: 8174 bool HasFP64; 8175 std::string ABI; 8176 8177 public: 8178 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8179 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 8180 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 8181 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 8182 HasMSA(false), DisableMadd4(false), HasFP64(false) { 8183 TheCXXABI.set(TargetCXXABI::GenericMIPS); 8184 8185 setABI((getTriple().getArch() == llvm::Triple::mips || 8186 getTriple().getArch() == llvm::Triple::mipsel) 8187 ? "o32" 8188 : "n64"); 8189 8190 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 8191 8192 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 8193 Triple.getOS() == llvm::Triple::OpenBSD; 8194 } 8195 8196 bool isNaN2008Default() const { 8197 return CPU == "mips32r6" || CPU == "mips64r6"; 8198 } 8199 8200 bool isFP64Default() const { 8201 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 8202 } 8203 8204 bool isNan2008() const override { 8205 return IsNan2008; 8206 } 8207 8208 bool processorSupportsGPR64() const { 8209 return llvm::StringSwitch<bool>(CPU) 8210 .Case("mips3", true) 8211 .Case("mips4", true) 8212 .Case("mips5", true) 8213 .Case("mips64", true) 8214 .Case("mips64r2", true) 8215 .Case("mips64r3", true) 8216 .Case("mips64r5", true) 8217 .Case("mips64r6", true) 8218 .Case("octeon", true) 8219 .Default(false); 8220 return false; 8221 } 8222 8223 StringRef getABI() const override { return ABI; } 8224 bool setABI(const std::string &Name) override { 8225 if (Name == "o32") { 8226 setO32ABITypes(); 8227 ABI = Name; 8228 return true; 8229 } 8230 8231 if (Name == "n32") { 8232 setN32ABITypes(); 8233 ABI = Name; 8234 return true; 8235 } 8236 if (Name == "n64") { 8237 setN64ABITypes(); 8238 ABI = Name; 8239 return true; 8240 } 8241 return false; 8242 } 8243 8244 void setO32ABITypes() { 8245 Int64Type = SignedLongLong; 8246 IntMaxType = Int64Type; 8247 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8248 LongDoubleWidth = LongDoubleAlign = 64; 8249 LongWidth = LongAlign = 32; 8250 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8251 PointerWidth = PointerAlign = 32; 8252 PtrDiffType = SignedInt; 8253 SizeType = UnsignedInt; 8254 SuitableAlign = 64; 8255 } 8256 8257 void setN32N64ABITypes() { 8258 LongDoubleWidth = LongDoubleAlign = 128; 8259 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8260 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 8261 LongDoubleWidth = LongDoubleAlign = 64; 8262 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8263 } 8264 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8265 SuitableAlign = 128; 8266 } 8267 8268 void setN64ABITypes() { 8269 setN32N64ABITypes(); 8270 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 8271 Int64Type = SignedLongLong; 8272 } else { 8273 Int64Type = SignedLong; 8274 } 8275 IntMaxType = Int64Type; 8276 LongWidth = LongAlign = 64; 8277 PointerWidth = PointerAlign = 64; 8278 PtrDiffType = SignedLong; 8279 SizeType = UnsignedLong; 8280 } 8281 8282 void setN32ABITypes() { 8283 setN32N64ABITypes(); 8284 Int64Type = SignedLongLong; 8285 IntMaxType = Int64Type; 8286 LongWidth = LongAlign = 32; 8287 PointerWidth = PointerAlign = 32; 8288 PtrDiffType = SignedInt; 8289 SizeType = UnsignedInt; 8290 } 8291 8292 bool isValidCPUName(StringRef Name) const override { 8293 return llvm::StringSwitch<bool>(Name) 8294 .Case("mips1", true) 8295 .Case("mips2", true) 8296 .Case("mips3", true) 8297 .Case("mips4", true) 8298 .Case("mips5", true) 8299 .Case("mips32", true) 8300 .Case("mips32r2", true) 8301 .Case("mips32r3", true) 8302 .Case("mips32r5", true) 8303 .Case("mips32r6", true) 8304 .Case("mips64", true) 8305 .Case("mips64r2", true) 8306 .Case("mips64r3", true) 8307 .Case("mips64r5", true) 8308 .Case("mips64r6", true) 8309 .Case("octeon", true) 8310 .Case("p5600", true) 8311 .Default(false); 8312 } 8313 8314 bool setCPU(const std::string &Name) override { 8315 CPU = Name; 8316 return isValidCPUName(Name); 8317 } 8318 8319 const std::string& getCPU() const { return CPU; } 8320 bool 8321 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8322 StringRef CPU, 8323 const std::vector<std::string> &FeaturesVec) const override { 8324 if (CPU.empty()) 8325 CPU = getCPU(); 8326 if (CPU == "octeon") 8327 Features["mips64r2"] = Features["cnmips"] = true; 8328 else 8329 Features[CPU] = true; 8330 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8331 } 8332 8333 void getTargetDefines(const LangOptions &Opts, 8334 MacroBuilder &Builder) const override { 8335 if (BigEndian) { 8336 DefineStd(Builder, "MIPSEB", Opts); 8337 Builder.defineMacro("_MIPSEB"); 8338 } else { 8339 DefineStd(Builder, "MIPSEL", Opts); 8340 Builder.defineMacro("_MIPSEL"); 8341 } 8342 8343 Builder.defineMacro("__mips__"); 8344 Builder.defineMacro("_mips"); 8345 if (Opts.GNUMode) 8346 Builder.defineMacro("mips"); 8347 8348 if (ABI == "o32") { 8349 Builder.defineMacro("__mips", "32"); 8350 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 8351 } else { 8352 Builder.defineMacro("__mips", "64"); 8353 Builder.defineMacro("__mips64"); 8354 Builder.defineMacro("__mips64__"); 8355 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 8356 } 8357 8358 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 8359 .Cases("mips32", "mips64", "1") 8360 .Cases("mips32r2", "mips64r2", "2") 8361 .Cases("mips32r3", "mips64r3", "3") 8362 .Cases("mips32r5", "mips64r5", "5") 8363 .Cases("mips32r6", "mips64r6", "6") 8364 .Default(""); 8365 if (!ISARev.empty()) 8366 Builder.defineMacro("__mips_isa_rev", ISARev); 8367 8368 if (ABI == "o32") { 8369 Builder.defineMacro("__mips_o32"); 8370 Builder.defineMacro("_ABIO32", "1"); 8371 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 8372 } else if (ABI == "n32") { 8373 Builder.defineMacro("__mips_n32"); 8374 Builder.defineMacro("_ABIN32", "2"); 8375 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 8376 } else if (ABI == "n64") { 8377 Builder.defineMacro("__mips_n64"); 8378 Builder.defineMacro("_ABI64", "3"); 8379 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 8380 } else 8381 llvm_unreachable("Invalid ABI."); 8382 8383 if (!IsNoABICalls) { 8384 Builder.defineMacro("__mips_abicalls"); 8385 if (CanUseBSDABICalls) 8386 Builder.defineMacro("__ABICALLS__"); 8387 } 8388 8389 Builder.defineMacro("__REGISTER_PREFIX__", ""); 8390 8391 switch (FloatABI) { 8392 case HardFloat: 8393 Builder.defineMacro("__mips_hard_float", Twine(1)); 8394 break; 8395 case SoftFloat: 8396 Builder.defineMacro("__mips_soft_float", Twine(1)); 8397 break; 8398 } 8399 8400 if (IsSingleFloat) 8401 Builder.defineMacro("__mips_single_float", Twine(1)); 8402 8403 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 8404 Builder.defineMacro("_MIPS_FPSET", 8405 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 8406 8407 if (IsMips16) 8408 Builder.defineMacro("__mips16", Twine(1)); 8409 8410 if (IsMicromips) 8411 Builder.defineMacro("__mips_micromips", Twine(1)); 8412 8413 if (IsNan2008) 8414 Builder.defineMacro("__mips_nan2008", Twine(1)); 8415 8416 switch (DspRev) { 8417 default: 8418 break; 8419 case DSP1: 8420 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 8421 Builder.defineMacro("__mips_dsp", Twine(1)); 8422 break; 8423 case DSP2: 8424 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 8425 Builder.defineMacro("__mips_dspr2", Twine(1)); 8426 Builder.defineMacro("__mips_dsp", Twine(1)); 8427 break; 8428 } 8429 8430 if (HasMSA) 8431 Builder.defineMacro("__mips_msa", Twine(1)); 8432 8433 if (DisableMadd4) 8434 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8435 8436 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8437 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8438 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8439 8440 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8441 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8442 8443 // These shouldn't be defined for MIPS-I but there's no need to check 8444 // for that since MIPS-I isn't supported. 8445 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8446 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8447 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8448 8449 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8450 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8451 // the instructions exist but using them violates the ABI since they 8452 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8453 if (ABI == "n32" || ABI == "n64") 8454 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8455 } 8456 8457 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8458 return llvm::makeArrayRef(BuiltinInfo, 8459 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8460 } 8461 bool hasFeature(StringRef Feature) const override { 8462 return llvm::StringSwitch<bool>(Feature) 8463 .Case("mips", true) 8464 .Case("fp64", HasFP64) 8465 .Default(false); 8466 } 8467 BuiltinVaListKind getBuiltinVaListKind() const override { 8468 return TargetInfo::VoidPtrBuiltinVaList; 8469 } 8470 ArrayRef<const char *> getGCCRegNames() const override { 8471 static const char *const GCCRegNames[] = { 8472 // CPU register names 8473 // Must match second column of GCCRegAliases 8474 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8475 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8476 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8477 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8478 // Floating point register names 8479 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8480 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8481 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8482 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8483 // Hi/lo and condition register names 8484 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8485 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8486 "$ac3hi","$ac3lo", 8487 // MSA register names 8488 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8489 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8490 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8491 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8492 // MSA control register names 8493 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8494 "$msarequest", "$msamap", "$msaunmap" 8495 }; 8496 return llvm::makeArrayRef(GCCRegNames); 8497 } 8498 bool validateAsmConstraint(const char *&Name, 8499 TargetInfo::ConstraintInfo &Info) const override { 8500 switch (*Name) { 8501 default: 8502 return false; 8503 case 'r': // CPU registers. 8504 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8505 case 'y': // Equivalent to "r", backward compatibility only. 8506 case 'f': // floating-point registers. 8507 case 'c': // $25 for indirect jumps 8508 case 'l': // lo register 8509 case 'x': // hilo register pair 8510 Info.setAllowsRegister(); 8511 return true; 8512 case 'I': // Signed 16-bit constant 8513 case 'J': // Integer 0 8514 case 'K': // Unsigned 16-bit constant 8515 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8516 case 'M': // Constants not loadable via lui, addiu, or ori 8517 case 'N': // Constant -1 to -65535 8518 case 'O': // A signed 15-bit constant 8519 case 'P': // A constant between 1 go 65535 8520 return true; 8521 case 'R': // An address that can be used in a non-macro load or store 8522 Info.setAllowsMemory(); 8523 return true; 8524 case 'Z': 8525 if (Name[1] == 'C') { // An address usable by ll, and sc. 8526 Info.setAllowsMemory(); 8527 Name++; // Skip over 'Z'. 8528 return true; 8529 } 8530 return false; 8531 } 8532 } 8533 8534 std::string convertConstraint(const char *&Constraint) const override { 8535 std::string R; 8536 switch (*Constraint) { 8537 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8538 if (Constraint[1] == 'C') { 8539 R = std::string("^") + std::string(Constraint, 2); 8540 Constraint++; 8541 return R; 8542 } 8543 break; 8544 } 8545 return TargetInfo::convertConstraint(Constraint); 8546 } 8547 8548 const char *getClobbers() const override { 8549 // In GCC, $1 is not widely used in generated code (it's used only in a few 8550 // specific situations), so there is no real need for users to add it to 8551 // the clobbers list if they want to use it in their inline assembly code. 8552 // 8553 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8554 // code generation, so using it in inline assembly without adding it to the 8555 // clobbers list can cause conflicts between the inline assembly code and 8556 // the surrounding generated code. 8557 // 8558 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8559 // operands, which will conflict with the ".set at" assembler option (which 8560 // we use only for inline assembly, in order to maintain compatibility with 8561 // GCC) and will also conflict with the user's usage of $1. 8562 // 8563 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8564 // register for generated code is to automatically clobber $1 for all inline 8565 // assembly code. 8566 // 8567 // FIXME: We should automatically clobber $1 only for inline assembly code 8568 // which actually uses it. This would allow LLVM to use $1 for inline 8569 // assembly operands if the user's assembly code doesn't use it. 8570 return "~{$1}"; 8571 } 8572 8573 bool handleTargetFeatures(std::vector<std::string> &Features, 8574 DiagnosticsEngine &Diags) override { 8575 IsMips16 = false; 8576 IsMicromips = false; 8577 IsNan2008 = isNaN2008Default(); 8578 IsSingleFloat = false; 8579 FloatABI = HardFloat; 8580 DspRev = NoDSP; 8581 HasFP64 = isFP64Default(); 8582 8583 for (const auto &Feature : Features) { 8584 if (Feature == "+single-float") 8585 IsSingleFloat = true; 8586 else if (Feature == "+soft-float") 8587 FloatABI = SoftFloat; 8588 else if (Feature == "+mips16") 8589 IsMips16 = true; 8590 else if (Feature == "+micromips") 8591 IsMicromips = true; 8592 else if (Feature == "+dsp") 8593 DspRev = std::max(DspRev, DSP1); 8594 else if (Feature == "+dspr2") 8595 DspRev = std::max(DspRev, DSP2); 8596 else if (Feature == "+msa") 8597 HasMSA = true; 8598 else if (Feature == "+nomadd4") 8599 DisableMadd4 = true; 8600 else if (Feature == "+fp64") 8601 HasFP64 = true; 8602 else if (Feature == "-fp64") 8603 HasFP64 = false; 8604 else if (Feature == "+nan2008") 8605 IsNan2008 = true; 8606 else if (Feature == "-nan2008") 8607 IsNan2008 = false; 8608 else if (Feature == "+noabicalls") 8609 IsNoABICalls = true; 8610 } 8611 8612 setDataLayout(); 8613 8614 return true; 8615 } 8616 8617 int getEHDataRegisterNumber(unsigned RegNo) const override { 8618 if (RegNo == 0) return 4; 8619 if (RegNo == 1) return 5; 8620 return -1; 8621 } 8622 8623 bool isCLZForZeroUndef() const override { return false; } 8624 8625 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8626 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8627 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8628 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8629 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8630 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8631 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8632 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8633 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8634 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8635 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8636 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8637 {{"ra"}, "$31"}}; 8638 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8639 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8640 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8641 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8642 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8643 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8644 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8645 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8646 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8647 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8648 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8649 {{"ra"}, "$31"}}; 8650 if (ABI == "o32") 8651 return llvm::makeArrayRef(O32RegAliases); 8652 return llvm::makeArrayRef(NewABIRegAliases); 8653 } 8654 8655 bool hasInt128Type() const override { 8656 return ABI == "n32" || ABI == "n64"; 8657 } 8658 8659 bool validateTarget(DiagnosticsEngine &Diags) const override { 8660 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8661 // this yet. It's better to fail here than on the backend assertion. 8662 if (processorSupportsGPR64() && ABI == "o32") { 8663 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8664 return false; 8665 } 8666 8667 // 64-bit ABI's require 64-bit CPU's. 8668 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8669 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8670 return false; 8671 } 8672 8673 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8674 // can't handle this yet. It's better to fail here than on the 8675 // backend assertion. 8676 if ((getTriple().getArch() == llvm::Triple::mips64 || 8677 getTriple().getArch() == llvm::Triple::mips64el) && 8678 ABI == "o32") { 8679 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8680 << ABI << getTriple().str(); 8681 return false; 8682 } 8683 8684 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8685 // can't handle this yet. It's better to fail here than on the 8686 // backend assertion. 8687 if ((getTriple().getArch() == llvm::Triple::mips || 8688 getTriple().getArch() == llvm::Triple::mipsel) && 8689 (ABI == "n32" || ABI == "n64")) { 8690 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8691 << ABI << getTriple().str(); 8692 return false; 8693 } 8694 8695 return true; 8696 } 8697 }; 8698 8699 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8700 #define BUILTIN(ID, TYPE, ATTRS) \ 8701 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8702 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8703 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8704 #include "clang/Basic/BuiltinsMips.def" 8705 }; 8706 8707 class PNaClTargetInfo : public TargetInfo { 8708 public: 8709 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8710 : TargetInfo(Triple) { 8711 this->LongAlign = 32; 8712 this->LongWidth = 32; 8713 this->PointerAlign = 32; 8714 this->PointerWidth = 32; 8715 this->IntMaxType = TargetInfo::SignedLongLong; 8716 this->Int64Type = TargetInfo::SignedLongLong; 8717 this->DoubleAlign = 64; 8718 this->LongDoubleWidth = 64; 8719 this->LongDoubleAlign = 64; 8720 this->SizeType = TargetInfo::UnsignedInt; 8721 this->PtrDiffType = TargetInfo::SignedInt; 8722 this->IntPtrType = TargetInfo::SignedInt; 8723 this->RegParmMax = 0; // Disallow regparm 8724 } 8725 8726 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8727 Builder.defineMacro("__le32__"); 8728 Builder.defineMacro("__pnacl__"); 8729 } 8730 void getTargetDefines(const LangOptions &Opts, 8731 MacroBuilder &Builder) const override { 8732 getArchDefines(Opts, Builder); 8733 } 8734 bool hasFeature(StringRef Feature) const override { 8735 return Feature == "pnacl"; 8736 } 8737 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8738 BuiltinVaListKind getBuiltinVaListKind() const override { 8739 return TargetInfo::PNaClABIBuiltinVaList; 8740 } 8741 ArrayRef<const char *> getGCCRegNames() const override; 8742 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8743 bool validateAsmConstraint(const char *&Name, 8744 TargetInfo::ConstraintInfo &Info) const override { 8745 return false; 8746 } 8747 8748 const char *getClobbers() const override { 8749 return ""; 8750 } 8751 }; 8752 8753 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8754 return None; 8755 } 8756 8757 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8758 return None; 8759 } 8760 8761 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8762 class NaClMips32TargetInfo : public MipsTargetInfo { 8763 public: 8764 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8765 : MipsTargetInfo(Triple, Opts) {} 8766 8767 BuiltinVaListKind getBuiltinVaListKind() const override { 8768 return TargetInfo::PNaClABIBuiltinVaList; 8769 } 8770 }; 8771 8772 class Le64TargetInfo : public TargetInfo { 8773 static const Builtin::Info BuiltinInfo[]; 8774 8775 public: 8776 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8777 : TargetInfo(Triple) { 8778 NoAsmVariants = true; 8779 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8780 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8781 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8782 } 8783 8784 void getTargetDefines(const LangOptions &Opts, 8785 MacroBuilder &Builder) const override { 8786 DefineStd(Builder, "unix", Opts); 8787 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8788 Builder.defineMacro("__ELF__"); 8789 } 8790 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8791 return llvm::makeArrayRef(BuiltinInfo, 8792 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8793 } 8794 BuiltinVaListKind getBuiltinVaListKind() const override { 8795 return TargetInfo::PNaClABIBuiltinVaList; 8796 } 8797 const char *getClobbers() const override { return ""; } 8798 ArrayRef<const char *> getGCCRegNames() const override { 8799 return None; 8800 } 8801 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8802 return None; 8803 } 8804 bool validateAsmConstraint(const char *&Name, 8805 TargetInfo::ConstraintInfo &Info) const override { 8806 return false; 8807 } 8808 8809 bool hasProtectedVisibility() const override { return false; } 8810 }; 8811 8812 class WebAssemblyTargetInfo : public TargetInfo { 8813 static const Builtin::Info BuiltinInfo[]; 8814 8815 enum SIMDEnum { 8816 NoSIMD, 8817 SIMD128, 8818 } SIMDLevel; 8819 8820 public: 8821 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8822 : TargetInfo(T), SIMDLevel(NoSIMD) { 8823 NoAsmVariants = true; 8824 SuitableAlign = 128; 8825 LargeArrayMinWidth = 128; 8826 LargeArrayAlign = 128; 8827 SimdDefaultAlign = 128; 8828 SigAtomicType = SignedLong; 8829 LongDoubleWidth = LongDoubleAlign = 128; 8830 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8831 SizeType = UnsignedInt; 8832 PtrDiffType = SignedInt; 8833 IntPtrType = SignedInt; 8834 } 8835 8836 protected: 8837 void getTargetDefines(const LangOptions &Opts, 8838 MacroBuilder &Builder) const override { 8839 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8840 if (SIMDLevel >= SIMD128) 8841 Builder.defineMacro("__wasm_simd128__"); 8842 } 8843 8844 private: 8845 bool 8846 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8847 StringRef CPU, 8848 const std::vector<std::string> &FeaturesVec) const override { 8849 if (CPU == "bleeding-edge") 8850 Features["simd128"] = true; 8851 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8852 } 8853 bool hasFeature(StringRef Feature) const final { 8854 return llvm::StringSwitch<bool>(Feature) 8855 .Case("simd128", SIMDLevel >= SIMD128) 8856 .Default(false); 8857 } 8858 bool handleTargetFeatures(std::vector<std::string> &Features, 8859 DiagnosticsEngine &Diags) final { 8860 for (const auto &Feature : Features) { 8861 if (Feature == "+simd128") { 8862 SIMDLevel = std::max(SIMDLevel, SIMD128); 8863 continue; 8864 } 8865 if (Feature == "-simd128") { 8866 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8867 continue; 8868 } 8869 8870 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8871 << "-target-feature"; 8872 return false; 8873 } 8874 return true; 8875 } 8876 bool isValidCPUName(StringRef Name) const final { 8877 return llvm::StringSwitch<bool>(Name) 8878 .Case("mvp", true) 8879 .Case("bleeding-edge", true) 8880 .Case("generic", true) 8881 .Default(false); 8882 } 8883 bool setCPU(const std::string &Name) final { 8884 return isValidCPUName(Name); 8885 } 8886 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8887 return llvm::makeArrayRef(BuiltinInfo, 8888 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8889 } 8890 BuiltinVaListKind getBuiltinVaListKind() const final { 8891 return VoidPtrBuiltinVaList; 8892 } 8893 ArrayRef<const char *> getGCCRegNames() const final { 8894 return None; 8895 } 8896 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8897 return None; 8898 } 8899 bool 8900 validateAsmConstraint(const char *&Name, 8901 TargetInfo::ConstraintInfo &Info) const final { 8902 return false; 8903 } 8904 const char *getClobbers() const final { return ""; } 8905 bool isCLZForZeroUndef() const final { return false; } 8906 bool hasInt128Type() const final { return true; } 8907 IntType getIntTypeByWidth(unsigned BitWidth, 8908 bool IsSigned) const final { 8909 // WebAssembly prefers long long for explicitly 64-bit integers. 8910 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8911 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8912 } 8913 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8914 bool IsSigned) const final { 8915 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8916 return BitWidth == 64 8917 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8918 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8919 } 8920 }; 8921 8922 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8923 #define BUILTIN(ID, TYPE, ATTRS) \ 8924 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8925 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8926 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8927 #include "clang/Basic/BuiltinsWebAssembly.def" 8928 }; 8929 8930 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8931 public: 8932 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8933 const TargetOptions &Opts) 8934 : WebAssemblyTargetInfo(T, Opts) { 8935 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8936 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8937 } 8938 8939 protected: 8940 void getTargetDefines(const LangOptions &Opts, 8941 MacroBuilder &Builder) const override { 8942 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8943 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8944 } 8945 }; 8946 8947 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8948 public: 8949 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8950 const TargetOptions &Opts) 8951 : WebAssemblyTargetInfo(T, Opts) { 8952 LongAlign = LongWidth = 64; 8953 PointerAlign = PointerWidth = 64; 8954 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8955 SizeType = UnsignedLong; 8956 PtrDiffType = SignedLong; 8957 IntPtrType = SignedLong; 8958 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8959 } 8960 8961 protected: 8962 void getTargetDefines(const LangOptions &Opts, 8963 MacroBuilder &Builder) const override { 8964 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8965 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8966 } 8967 }; 8968 8969 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8970 #define BUILTIN(ID, TYPE, ATTRS) \ 8971 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8972 #include "clang/Basic/BuiltinsLe64.def" 8973 }; 8974 8975 static const unsigned SPIRAddrSpaceMap[] = { 8976 0, // Default 8977 1, // opencl_global 8978 3, // opencl_local 8979 2, // opencl_constant 8980 4, // opencl_generic 8981 0, // cuda_device 8982 0, // cuda_constant 8983 0 // cuda_shared 8984 }; 8985 class SPIRTargetInfo : public TargetInfo { 8986 public: 8987 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8988 : TargetInfo(Triple) { 8989 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8990 "SPIR target must use unknown OS"); 8991 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8992 "SPIR target must use unknown environment type"); 8993 TLSSupported = false; 8994 LongWidth = LongAlign = 64; 8995 AddrSpaceMap = &SPIRAddrSpaceMap; 8996 UseAddrSpaceMapMangling = true; 8997 // Define available target features 8998 // These must be defined in sorted order! 8999 NoAsmVariants = true; 9000 } 9001 void getTargetDefines(const LangOptions &Opts, 9002 MacroBuilder &Builder) const override { 9003 DefineStd(Builder, "SPIR", Opts); 9004 } 9005 bool hasFeature(StringRef Feature) const override { 9006 return Feature == "spir"; 9007 } 9008 9009 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 9010 const char *getClobbers() const override { return ""; } 9011 ArrayRef<const char *> getGCCRegNames() const override { return None; } 9012 bool validateAsmConstraint(const char *&Name, 9013 TargetInfo::ConstraintInfo &info) const override { 9014 return true; 9015 } 9016 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9017 return None; 9018 } 9019 BuiltinVaListKind getBuiltinVaListKind() const override { 9020 return TargetInfo::VoidPtrBuiltinVaList; 9021 } 9022 9023 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 9024 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 9025 : CCCR_Warning; 9026 } 9027 9028 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 9029 return CC_SpirFunction; 9030 } 9031 9032 void setSupportedOpenCLOpts() override { 9033 // Assume all OpenCL extensions and optional core features are supported 9034 // for SPIR since it is a generic target. 9035 getSupportedOpenCLOpts().supportAll(); 9036 } 9037 }; 9038 9039 class SPIR32TargetInfo : public SPIRTargetInfo { 9040 public: 9041 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9042 : SPIRTargetInfo(Triple, Opts) { 9043 PointerWidth = PointerAlign = 32; 9044 SizeType = TargetInfo::UnsignedInt; 9045 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 9046 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 9047 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 9048 } 9049 void getTargetDefines(const LangOptions &Opts, 9050 MacroBuilder &Builder) const override { 9051 DefineStd(Builder, "SPIR32", Opts); 9052 } 9053 }; 9054 9055 class SPIR64TargetInfo : public SPIRTargetInfo { 9056 public: 9057 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9058 : SPIRTargetInfo(Triple, Opts) { 9059 PointerWidth = PointerAlign = 64; 9060 SizeType = TargetInfo::UnsignedLong; 9061 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 9062 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 9063 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 9064 } 9065 void getTargetDefines(const LangOptions &Opts, 9066 MacroBuilder &Builder) const override { 9067 DefineStd(Builder, "SPIR64", Opts); 9068 } 9069 }; 9070 9071 class XCoreTargetInfo : public TargetInfo { 9072 static const Builtin::Info BuiltinInfo[]; 9073 public: 9074 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9075 : TargetInfo(Triple) { 9076 NoAsmVariants = true; 9077 LongLongAlign = 32; 9078 SuitableAlign = 32; 9079 DoubleAlign = LongDoubleAlign = 32; 9080 SizeType = UnsignedInt; 9081 PtrDiffType = SignedInt; 9082 IntPtrType = SignedInt; 9083 WCharType = UnsignedChar; 9084 WIntType = UnsignedInt; 9085 UseZeroLengthBitfieldAlignment = true; 9086 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 9087 "-f64:32-a:0:32-n32"); 9088 } 9089 void getTargetDefines(const LangOptions &Opts, 9090 MacroBuilder &Builder) const override { 9091 Builder.defineMacro("__XS1B__"); 9092 } 9093 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9094 return llvm::makeArrayRef(BuiltinInfo, 9095 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 9096 } 9097 BuiltinVaListKind getBuiltinVaListKind() const override { 9098 return TargetInfo::VoidPtrBuiltinVaList; 9099 } 9100 const char *getClobbers() const override { 9101 return ""; 9102 } 9103 ArrayRef<const char *> getGCCRegNames() const override { 9104 static const char * const GCCRegNames[] = { 9105 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9106 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 9107 }; 9108 return llvm::makeArrayRef(GCCRegNames); 9109 } 9110 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9111 return None; 9112 } 9113 bool validateAsmConstraint(const char *&Name, 9114 TargetInfo::ConstraintInfo &Info) const override { 9115 return false; 9116 } 9117 int getEHDataRegisterNumber(unsigned RegNo) const override { 9118 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 9119 return (RegNo < 2)? RegNo : -1; 9120 } 9121 bool allowsLargerPreferedTypeAlignment() const override { 9122 return false; 9123 } 9124 }; 9125 9126 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 9127 #define BUILTIN(ID, TYPE, ATTRS) \ 9128 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 9129 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 9130 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 9131 #include "clang/Basic/BuiltinsXCore.def" 9132 }; 9133 9134 // x86_32 Android target 9135 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 9136 public: 9137 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9138 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 9139 SuitableAlign = 32; 9140 LongDoubleWidth = 64; 9141 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 9142 } 9143 }; 9144 9145 // x86_64 Android target 9146 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 9147 public: 9148 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 9149 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 9150 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 9151 } 9152 9153 bool useFloat128ManglingForLongDouble() const override { 9154 return true; 9155 } 9156 }; 9157 9158 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 9159 class RenderScript32TargetInfo : public ARMleTargetInfo { 9160 public: 9161 RenderScript32TargetInfo(const llvm::Triple &Triple, 9162 const TargetOptions &Opts) 9163 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 9164 Triple.getOSName(), 9165 Triple.getEnvironmentName()), 9166 Opts) { 9167 IsRenderScriptTarget = true; 9168 LongWidth = LongAlign = 64; 9169 } 9170 void getTargetDefines(const LangOptions &Opts, 9171 MacroBuilder &Builder) const override { 9172 Builder.defineMacro("__RENDERSCRIPT__"); 9173 ARMleTargetInfo::getTargetDefines(Opts, Builder); 9174 } 9175 }; 9176 9177 // 64-bit RenderScript is aarch64 9178 class RenderScript64TargetInfo : public AArch64leTargetInfo { 9179 public: 9180 RenderScript64TargetInfo(const llvm::Triple &Triple, 9181 const TargetOptions &Opts) 9182 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 9183 Triple.getOSName(), 9184 Triple.getEnvironmentName()), 9185 Opts) { 9186 IsRenderScriptTarget = true; 9187 } 9188 9189 void getTargetDefines(const LangOptions &Opts, 9190 MacroBuilder &Builder) const override { 9191 Builder.defineMacro("__RENDERSCRIPT__"); 9192 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 9193 } 9194 }; 9195 9196 /// Information about a specific microcontroller. 9197 struct MCUInfo { 9198 const char *Name; 9199 const char *DefineName; 9200 }; 9201 9202 // This list should be kept up-to-date with AVRDevices.td in LLVM. 9203 static ArrayRef<MCUInfo> AVRMcus = { 9204 { "at90s1200", "__AVR_AT90S1200__" }, 9205 { "attiny11", "__AVR_ATtiny11__" }, 9206 { "attiny12", "__AVR_ATtiny12__" }, 9207 { "attiny15", "__AVR_ATtiny15__" }, 9208 { "attiny28", "__AVR_ATtiny28__" }, 9209 { "at90s2313", "__AVR_AT90S2313__" }, 9210 { "at90s2323", "__AVR_AT90S2323__" }, 9211 { "at90s2333", "__AVR_AT90S2333__" }, 9212 { "at90s2343", "__AVR_AT90S2343__" }, 9213 { "attiny22", "__AVR_ATtiny22__" }, 9214 { "attiny26", "__AVR_ATtiny26__" }, 9215 { "at86rf401", "__AVR_AT86RF401__" }, 9216 { "at90s4414", "__AVR_AT90S4414__" }, 9217 { "at90s4433", "__AVR_AT90S4433__" }, 9218 { "at90s4434", "__AVR_AT90S4434__" }, 9219 { "at90s8515", "__AVR_AT90S8515__" }, 9220 { "at90c8534", "__AVR_AT90c8534__" }, 9221 { "at90s8535", "__AVR_AT90S8535__" }, 9222 { "ata5272", "__AVR_ATA5272__" }, 9223 { "attiny13", "__AVR_ATtiny13__" }, 9224 { "attiny13a", "__AVR_ATtiny13A__" }, 9225 { "attiny2313", "__AVR_ATtiny2313__" }, 9226 { "attiny2313a", "__AVR_ATtiny2313A__" }, 9227 { "attiny24", "__AVR_ATtiny24__" }, 9228 { "attiny24a", "__AVR_ATtiny24A__" }, 9229 { "attiny4313", "__AVR_ATtiny4313__" }, 9230 { "attiny44", "__AVR_ATtiny44__" }, 9231 { "attiny44a", "__AVR_ATtiny44A__" }, 9232 { "attiny84", "__AVR_ATtiny84__" }, 9233 { "attiny84a", "__AVR_ATtiny84A__" }, 9234 { "attiny25", "__AVR_ATtiny25__" }, 9235 { "attiny45", "__AVR_ATtiny45__" }, 9236 { "attiny85", "__AVR_ATtiny85__" }, 9237 { "attiny261", "__AVR_ATtiny261__" }, 9238 { "attiny261a", "__AVR_ATtiny261A__" }, 9239 { "attiny461", "__AVR_ATtiny461__" }, 9240 { "attiny461a", "__AVR_ATtiny461A__" }, 9241 { "attiny861", "__AVR_ATtiny861__" }, 9242 { "attiny861a", "__AVR_ATtiny861A__" }, 9243 { "attiny87", "__AVR_ATtiny87__" }, 9244 { "attiny43u", "__AVR_ATtiny43U__" }, 9245 { "attiny48", "__AVR_ATtiny48__" }, 9246 { "attiny88", "__AVR_ATtiny88__" }, 9247 { "attiny828", "__AVR_ATtiny828__" }, 9248 { "at43usb355", "__AVR_AT43USB355__" }, 9249 { "at76c711", "__AVR_AT76C711__" }, 9250 { "atmega103", "__AVR_ATmega103__" }, 9251 { "at43usb320", "__AVR_AT43USB320__" }, 9252 { "attiny167", "__AVR_ATtiny167__" }, 9253 { "at90usb82", "__AVR_AT90USB82__" }, 9254 { "at90usb162", "__AVR_AT90USB162__" }, 9255 { "ata5505", "__AVR_ATA5505__" }, 9256 { "atmega8u2", "__AVR_ATmega8U2__" }, 9257 { "atmega16u2", "__AVR_ATmega16U2__" }, 9258 { "atmega32u2", "__AVR_ATmega32U2__" }, 9259 { "attiny1634", "__AVR_ATtiny1634__" }, 9260 { "atmega8", "__AVR_ATmega8__" }, 9261 { "ata6289", "__AVR_ATA6289__" }, 9262 { "atmega8a", "__AVR_ATmega8A__" }, 9263 { "ata6285", "__AVR_ATA6285__" }, 9264 { "ata6286", "__AVR_ATA6286__" }, 9265 { "atmega48", "__AVR_ATmega48__" }, 9266 { "atmega48a", "__AVR_ATmega48A__" }, 9267 { "atmega48pa", "__AVR_ATmega48PA__" }, 9268 { "atmega48p", "__AVR_ATmega48P__" }, 9269 { "atmega88", "__AVR_ATmega88__" }, 9270 { "atmega88a", "__AVR_ATmega88A__" }, 9271 { "atmega88p", "__AVR_ATmega88P__" }, 9272 { "atmega88pa", "__AVR_ATmega88PA__" }, 9273 { "atmega8515", "__AVR_ATmega8515__" }, 9274 { "atmega8535", "__AVR_ATmega8535__" }, 9275 { "atmega8hva", "__AVR_ATmega8HVA__" }, 9276 { "at90pwm1", "__AVR_AT90PWM1__" }, 9277 { "at90pwm2", "__AVR_AT90PWM2__" }, 9278 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 9279 { "at90pwm3", "__AVR_AT90PWM3__" }, 9280 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 9281 { "at90pwm81", "__AVR_AT90PWM81__" }, 9282 { "ata5790", "__AVR_ATA5790__" }, 9283 { "ata5795", "__AVR_ATA5795__" }, 9284 { "atmega16", "__AVR_ATmega16__" }, 9285 { "atmega16a", "__AVR_ATmega16A__" }, 9286 { "atmega161", "__AVR_ATmega161__" }, 9287 { "atmega162", "__AVR_ATmega162__" }, 9288 { "atmega163", "__AVR_ATmega163__" }, 9289 { "atmega164a", "__AVR_ATmega164A__" }, 9290 { "atmega164p", "__AVR_ATmega164P__" }, 9291 { "atmega164pa", "__AVR_ATmega164PA__" }, 9292 { "atmega165", "__AVR_ATmega165__" }, 9293 { "atmega165a", "__AVR_ATmega165A__" }, 9294 { "atmega165p", "__AVR_ATmega165P__" }, 9295 { "atmega165pa", "__AVR_ATmega165PA__" }, 9296 { "atmega168", "__AVR_ATmega168__" }, 9297 { "atmega168a", "__AVR_ATmega168A__" }, 9298 { "atmega168p", "__AVR_ATmega168P__" }, 9299 { "atmega168pa", "__AVR_ATmega168PA__" }, 9300 { "atmega169", "__AVR_ATmega169__" }, 9301 { "atmega169a", "__AVR_ATmega169A__" }, 9302 { "atmega169p", "__AVR_ATmega169P__" }, 9303 { "atmega169pa", "__AVR_ATmega169PA__" }, 9304 { "atmega32", "__AVR_ATmega32__" }, 9305 { "atmega32a", "__AVR_ATmega32A__" }, 9306 { "atmega323", "__AVR_ATmega323__" }, 9307 { "atmega324a", "__AVR_ATmega324A__" }, 9308 { "atmega324p", "__AVR_ATmega324P__" }, 9309 { "atmega324pa", "__AVR_ATmega324PA__" }, 9310 { "atmega325", "__AVR_ATmega325__" }, 9311 { "atmega325a", "__AVR_ATmega325A__" }, 9312 { "atmega325p", "__AVR_ATmega325P__" }, 9313 { "atmega325pa", "__AVR_ATmega325PA__" }, 9314 { "atmega3250", "__AVR_ATmega3250__" }, 9315 { "atmega3250a", "__AVR_ATmega3250A__" }, 9316 { "atmega3250p", "__AVR_ATmega3250P__" }, 9317 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 9318 { "atmega328", "__AVR_ATmega328__" }, 9319 { "atmega328p", "__AVR_ATmega328P__" }, 9320 { "atmega329", "__AVR_ATmega329__" }, 9321 { "atmega329a", "__AVR_ATmega329A__" }, 9322 { "atmega329p", "__AVR_ATmega329P__" }, 9323 { "atmega329pa", "__AVR_ATmega329PA__" }, 9324 { "atmega3290", "__AVR_ATmega3290__" }, 9325 { "atmega3290a", "__AVR_ATmega3290A__" }, 9326 { "atmega3290p", "__AVR_ATmega3290P__" }, 9327 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 9328 { "atmega406", "__AVR_ATmega406__" }, 9329 { "atmega64", "__AVR_ATmega64__" }, 9330 { "atmega64a", "__AVR_ATmega64A__" }, 9331 { "atmega640", "__AVR_ATmega640__" }, 9332 { "atmega644", "__AVR_ATmega644__" }, 9333 { "atmega644a", "__AVR_ATmega644A__" }, 9334 { "atmega644p", "__AVR_ATmega644P__" }, 9335 { "atmega644pa", "__AVR_ATmega644PA__" }, 9336 { "atmega645", "__AVR_ATmega645__" }, 9337 { "atmega645a", "__AVR_ATmega645A__" }, 9338 { "atmega645p", "__AVR_ATmega645P__" }, 9339 { "atmega649", "__AVR_ATmega649__" }, 9340 { "atmega649a", "__AVR_ATmega649A__" }, 9341 { "atmega649p", "__AVR_ATmega649P__" }, 9342 { "atmega6450", "__AVR_ATmega6450__" }, 9343 { "atmega6450a", "__AVR_ATmega6450A__" }, 9344 { "atmega6450p", "__AVR_ATmega6450P__" }, 9345 { "atmega6490", "__AVR_ATmega6490__" }, 9346 { "atmega6490a", "__AVR_ATmega6490A__" }, 9347 { "atmega6490p", "__AVR_ATmega6490P__" }, 9348 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 9349 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 9350 { "atmega16hva", "__AVR_ATmega16HVA__" }, 9351 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 9352 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 9353 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 9354 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 9355 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 9356 { "atmega64hve", "__AVR_ATmega64HVE__" }, 9357 { "at90can32", "__AVR_AT90CAN32__" }, 9358 { "at90can64", "__AVR_AT90CAN64__" }, 9359 { "at90pwm161", "__AVR_AT90PWM161__" }, 9360 { "at90pwm216", "__AVR_AT90PWM216__" }, 9361 { "at90pwm316", "__AVR_AT90PWM316__" }, 9362 { "atmega32c1", "__AVR_ATmega32C1__" }, 9363 { "atmega64c1", "__AVR_ATmega64C1__" }, 9364 { "atmega16m1", "__AVR_ATmega16M1__" }, 9365 { "atmega32m1", "__AVR_ATmega32M1__" }, 9366 { "atmega64m1", "__AVR_ATmega64M1__" }, 9367 { "atmega16u4", "__AVR_ATmega16U4__" }, 9368 { "atmega32u4", "__AVR_ATmega32U4__" }, 9369 { "atmega32u6", "__AVR_ATmega32U6__" }, 9370 { "at90usb646", "__AVR_AT90USB646__" }, 9371 { "at90usb647", "__AVR_AT90USB647__" }, 9372 { "at90scr100", "__AVR_AT90SCR100__" }, 9373 { "at94k", "__AVR_AT94K__" }, 9374 { "m3000", "__AVR_AT000__" }, 9375 { "atmega128", "__AVR_ATmega128__" }, 9376 { "atmega128a", "__AVR_ATmega128A__" }, 9377 { "atmega1280", "__AVR_ATmega1280__" }, 9378 { "atmega1281", "__AVR_ATmega1281__" }, 9379 { "atmega1284", "__AVR_ATmega1284__" }, 9380 { "atmega1284p", "__AVR_ATmega1284P__" }, 9381 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 9382 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 9383 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 9384 { "at90can128", "__AVR_AT90CAN128__" }, 9385 { "at90usb1286", "__AVR_AT90USB1286__" }, 9386 { "at90usb1287", "__AVR_AT90USB1287__" }, 9387 { "atmega2560", "__AVR_ATmega2560__" }, 9388 { "atmega2561", "__AVR_ATmega2561__" }, 9389 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 9390 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 9391 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 9392 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 9393 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 9394 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 9395 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 9396 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 9397 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 9398 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 9399 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 9400 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 9401 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 9402 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 9403 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 9404 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 9405 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 9406 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 9407 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 9408 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 9409 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 9410 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 9411 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 9412 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 9413 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 9414 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 9415 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 9416 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 9417 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 9418 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 9419 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 9420 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 9421 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 9422 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 9423 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 9424 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 9425 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 9426 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 9427 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 9428 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9429 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9430 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9431 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9432 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9433 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9434 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9435 { "attiny4", "__AVR_ATtiny4__" }, 9436 { "attiny5", "__AVR_ATtiny5__" }, 9437 { "attiny9", "__AVR_ATtiny9__" }, 9438 { "attiny10", "__AVR_ATtiny10__" }, 9439 { "attiny20", "__AVR_ATtiny20__" }, 9440 { "attiny40", "__AVR_ATtiny40__" }, 9441 { "attiny102", "__AVR_ATtiny102__" }, 9442 { "attiny104", "__AVR_ATtiny104__" }, 9443 }; 9444 9445 // AVR Target 9446 class AVRTargetInfo : public TargetInfo { 9447 public: 9448 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9449 : TargetInfo(Triple) { 9450 TLSSupported = false; 9451 PointerWidth = 16; 9452 PointerAlign = 8; 9453 IntWidth = 16; 9454 IntAlign = 8; 9455 LongWidth = 32; 9456 LongAlign = 8; 9457 LongLongWidth = 64; 9458 LongLongAlign = 8; 9459 SuitableAlign = 8; 9460 DefaultAlignForAttributeAligned = 8; 9461 HalfWidth = 16; 9462 HalfAlign = 8; 9463 FloatWidth = 32; 9464 FloatAlign = 8; 9465 DoubleWidth = 32; 9466 DoubleAlign = 8; 9467 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9468 LongDoubleWidth = 32; 9469 LongDoubleAlign = 8; 9470 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9471 SizeType = UnsignedInt; 9472 PtrDiffType = SignedInt; 9473 IntPtrType = SignedInt; 9474 Char16Type = UnsignedInt; 9475 WCharType = SignedInt; 9476 WIntType = SignedInt; 9477 Char32Type = UnsignedLong; 9478 SigAtomicType = SignedChar; 9479 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9480 "-f32:32:32-f64:64:64-n8"); 9481 } 9482 9483 void getTargetDefines(const LangOptions &Opts, 9484 MacroBuilder &Builder) const override { 9485 Builder.defineMacro("AVR"); 9486 Builder.defineMacro("__AVR"); 9487 Builder.defineMacro("__AVR__"); 9488 9489 if (!this->CPU.empty()) { 9490 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9491 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9492 9493 if (It != AVRMcus.end()) 9494 Builder.defineMacro(It->DefineName); 9495 } 9496 } 9497 9498 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9499 return None; 9500 } 9501 9502 BuiltinVaListKind getBuiltinVaListKind() const override { 9503 return TargetInfo::VoidPtrBuiltinVaList; 9504 } 9505 9506 const char *getClobbers() const override { 9507 return ""; 9508 } 9509 9510 ArrayRef<const char *> getGCCRegNames() const override { 9511 static const char * const GCCRegNames[] = { 9512 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9513 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9514 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9515 "r24", "r25", "X", "Y", "Z", "SP" 9516 }; 9517 return llvm::makeArrayRef(GCCRegNames); 9518 } 9519 9520 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9521 return None; 9522 } 9523 9524 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9525 static const TargetInfo::AddlRegName AddlRegNames[] = { 9526 { { "r26", "r27"}, 26 }, 9527 { { "r28", "r29"}, 27 }, 9528 { { "r30", "r31"}, 28 }, 9529 { { "SPL", "SPH"}, 29 }, 9530 }; 9531 return llvm::makeArrayRef(AddlRegNames); 9532 } 9533 9534 bool validateAsmConstraint(const char *&Name, 9535 TargetInfo::ConstraintInfo &Info) const override { 9536 // There aren't any multi-character AVR specific constraints. 9537 if (StringRef(Name).size() > 1) return false; 9538 9539 switch (*Name) { 9540 default: return false; 9541 case 'a': // Simple upper registers 9542 case 'b': // Base pointer registers pairs 9543 case 'd': // Upper register 9544 case 'l': // Lower registers 9545 case 'e': // Pointer register pairs 9546 case 'q': // Stack pointer register 9547 case 'r': // Any register 9548 case 'w': // Special upper register pairs 9549 case 't': // Temporary register 9550 case 'x': case 'X': // Pointer register pair X 9551 case 'y': case 'Y': // Pointer register pair Y 9552 case 'z': case 'Z': // Pointer register pair Z 9553 Info.setAllowsRegister(); 9554 return true; 9555 case 'I': // 6-bit positive integer constant 9556 Info.setRequiresImmediate(0, 63); 9557 return true; 9558 case 'J': // 6-bit negative integer constant 9559 Info.setRequiresImmediate(-63, 0); 9560 return true; 9561 case 'K': // Integer constant (Range: 2) 9562 Info.setRequiresImmediate(2); 9563 return true; 9564 case 'L': // Integer constant (Range: 0) 9565 Info.setRequiresImmediate(0); 9566 return true; 9567 case 'M': // 8-bit integer constant 9568 Info.setRequiresImmediate(0, 0xff); 9569 return true; 9570 case 'N': // Integer constant (Range: -1) 9571 Info.setRequiresImmediate(-1); 9572 return true; 9573 case 'O': // Integer constant (Range: 8, 16, 24) 9574 Info.setRequiresImmediate({8, 16, 24}); 9575 return true; 9576 case 'P': // Integer constant (Range: 1) 9577 Info.setRequiresImmediate(1); 9578 return true; 9579 case 'R': // Integer constant (Range: -6 to 5) 9580 Info.setRequiresImmediate(-6, 5); 9581 return true; 9582 case 'G': // Floating point constant 9583 case 'Q': // A memory address based on Y or Z pointer with displacement. 9584 return true; 9585 } 9586 9587 return false; 9588 } 9589 9590 IntType getIntTypeByWidth(unsigned BitWidth, 9591 bool IsSigned) const final { 9592 // AVR prefers int for 16-bit integers. 9593 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9594 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9595 } 9596 9597 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9598 bool IsSigned) const final { 9599 // AVR uses int for int_least16_t and int_fast16_t. 9600 return BitWidth == 16 9601 ? (IsSigned ? SignedInt : UnsignedInt) 9602 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9603 } 9604 9605 bool isValidCPUName(StringRef Name) const override { 9606 bool IsFamily = llvm::StringSwitch<bool>(Name) 9607 .Case("avr1", true) 9608 .Case("avr2", true) 9609 .Case("avr25", true) 9610 .Case("avr3", true) 9611 .Case("avr31", true) 9612 .Case("avr35", true) 9613 .Case("avr4", true) 9614 .Case("avr5", true) 9615 .Case("avr51", true) 9616 .Case("avr6", true) 9617 .Case("avrxmega1", true) 9618 .Case("avrxmega2", true) 9619 .Case("avrxmega3", true) 9620 .Case("avrxmega4", true) 9621 .Case("avrxmega5", true) 9622 .Case("avrxmega6", true) 9623 .Case("avrxmega7", true) 9624 .Case("avrtiny", true) 9625 .Default(false); 9626 9627 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9628 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9629 return IsFamily || IsMCU; 9630 } 9631 9632 bool setCPU(const std::string &Name) override { 9633 bool isValid = isValidCPUName(Name); 9634 if (isValid) 9635 CPU = Name; 9636 return isValid; 9637 } 9638 9639 protected: 9640 std::string CPU; 9641 }; 9642 9643 } // end anonymous namespace 9644 9645 //===----------------------------------------------------------------------===// 9646 // Driver code 9647 //===----------------------------------------------------------------------===// 9648 9649 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9650 const TargetOptions &Opts) { 9651 llvm::Triple::OSType os = Triple.getOS(); 9652 9653 switch (Triple.getArch()) { 9654 default: 9655 return nullptr; 9656 9657 case llvm::Triple::xcore: 9658 return new XCoreTargetInfo(Triple, Opts); 9659 9660 case llvm::Triple::hexagon: 9661 return new HexagonTargetInfo(Triple, Opts); 9662 9663 case llvm::Triple::lanai: 9664 return new LanaiTargetInfo(Triple, Opts); 9665 9666 case llvm::Triple::aarch64: 9667 if (Triple.isOSDarwin()) 9668 return new DarwinAArch64TargetInfo(Triple, Opts); 9669 9670 switch (os) { 9671 case llvm::Triple::CloudABI: 9672 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9673 case llvm::Triple::FreeBSD: 9674 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9675 case llvm::Triple::Fuchsia: 9676 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9677 case llvm::Triple::Linux: 9678 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9679 case llvm::Triple::NetBSD: 9680 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9681 case llvm::Triple::OpenBSD: 9682 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9683 case llvm::Triple::Win32: 9684 return new MicrosoftARM64TargetInfo(Triple, Opts); 9685 default: 9686 return new AArch64leTargetInfo(Triple, Opts); 9687 } 9688 9689 case llvm::Triple::aarch64_be: 9690 switch (os) { 9691 case llvm::Triple::FreeBSD: 9692 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9693 case llvm::Triple::Fuchsia: 9694 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9695 case llvm::Triple::Linux: 9696 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9697 case llvm::Triple::NetBSD: 9698 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9699 default: 9700 return new AArch64beTargetInfo(Triple, Opts); 9701 } 9702 9703 case llvm::Triple::arm: 9704 case llvm::Triple::thumb: 9705 if (Triple.isOSBinFormatMachO()) 9706 return new DarwinARMTargetInfo(Triple, Opts); 9707 9708 switch (os) { 9709 case llvm::Triple::CloudABI: 9710 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9711 case llvm::Triple::Linux: 9712 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9713 case llvm::Triple::FreeBSD: 9714 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9715 case llvm::Triple::NetBSD: 9716 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9717 case llvm::Triple::OpenBSD: 9718 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9719 case llvm::Triple::Bitrig: 9720 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9721 case llvm::Triple::RTEMS: 9722 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9723 case llvm::Triple::NaCl: 9724 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9725 case llvm::Triple::Win32: 9726 switch (Triple.getEnvironment()) { 9727 case llvm::Triple::Cygnus: 9728 return new CygwinARMTargetInfo(Triple, Opts); 9729 case llvm::Triple::GNU: 9730 return new MinGWARMTargetInfo(Triple, Opts); 9731 case llvm::Triple::Itanium: 9732 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9733 case llvm::Triple::MSVC: 9734 default: // Assume MSVC for unknown environments 9735 return new MicrosoftARMleTargetInfo(Triple, Opts); 9736 } 9737 default: 9738 return new ARMleTargetInfo(Triple, Opts); 9739 } 9740 9741 case llvm::Triple::armeb: 9742 case llvm::Triple::thumbeb: 9743 if (Triple.isOSDarwin()) 9744 return new DarwinARMTargetInfo(Triple, Opts); 9745 9746 switch (os) { 9747 case llvm::Triple::Linux: 9748 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9749 case llvm::Triple::FreeBSD: 9750 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9751 case llvm::Triple::NetBSD: 9752 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9753 case llvm::Triple::OpenBSD: 9754 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9755 case llvm::Triple::Bitrig: 9756 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9757 case llvm::Triple::RTEMS: 9758 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9759 case llvm::Triple::NaCl: 9760 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9761 default: 9762 return new ARMbeTargetInfo(Triple, Opts); 9763 } 9764 9765 case llvm::Triple::avr: 9766 return new AVRTargetInfo(Triple, Opts); 9767 case llvm::Triple::bpfeb: 9768 case llvm::Triple::bpfel: 9769 return new BPFTargetInfo(Triple, Opts); 9770 9771 case llvm::Triple::msp430: 9772 return new MSP430TargetInfo(Triple, Opts); 9773 9774 case llvm::Triple::nios2: 9775 return new LinuxTargetInfo<Nios2TargetInfo>(Triple, Opts); 9776 9777 case llvm::Triple::mips: 9778 switch (os) { 9779 case llvm::Triple::Linux: 9780 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9781 case llvm::Triple::RTEMS: 9782 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9783 case llvm::Triple::FreeBSD: 9784 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9785 case llvm::Triple::NetBSD: 9786 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9787 default: 9788 return new MipsTargetInfo(Triple, Opts); 9789 } 9790 9791 case llvm::Triple::mipsel: 9792 switch (os) { 9793 case llvm::Triple::Linux: 9794 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9795 case llvm::Triple::RTEMS: 9796 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9797 case llvm::Triple::FreeBSD: 9798 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9799 case llvm::Triple::NetBSD: 9800 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9801 case llvm::Triple::NaCl: 9802 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9803 default: 9804 return new MipsTargetInfo(Triple, Opts); 9805 } 9806 9807 case llvm::Triple::mips64: 9808 switch (os) { 9809 case llvm::Triple::Linux: 9810 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9811 case llvm::Triple::RTEMS: 9812 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9813 case llvm::Triple::FreeBSD: 9814 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9815 case llvm::Triple::NetBSD: 9816 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9817 case llvm::Triple::OpenBSD: 9818 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9819 default: 9820 return new MipsTargetInfo(Triple, Opts); 9821 } 9822 9823 case llvm::Triple::mips64el: 9824 switch (os) { 9825 case llvm::Triple::Linux: 9826 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9827 case llvm::Triple::RTEMS: 9828 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9829 case llvm::Triple::FreeBSD: 9830 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9831 case llvm::Triple::NetBSD: 9832 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9833 case llvm::Triple::OpenBSD: 9834 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9835 default: 9836 return new MipsTargetInfo(Triple, Opts); 9837 } 9838 9839 case llvm::Triple::le32: 9840 switch (os) { 9841 case llvm::Triple::NaCl: 9842 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9843 default: 9844 return nullptr; 9845 } 9846 9847 case llvm::Triple::le64: 9848 return new Le64TargetInfo(Triple, Opts); 9849 9850 case llvm::Triple::ppc: 9851 if (Triple.isOSDarwin()) 9852 return new DarwinPPC32TargetInfo(Triple, Opts); 9853 switch (os) { 9854 case llvm::Triple::Linux: 9855 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9856 case llvm::Triple::FreeBSD: 9857 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9858 case llvm::Triple::NetBSD: 9859 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9860 case llvm::Triple::OpenBSD: 9861 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9862 case llvm::Triple::RTEMS: 9863 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9864 default: 9865 return new PPC32TargetInfo(Triple, Opts); 9866 } 9867 9868 case llvm::Triple::ppc64: 9869 if (Triple.isOSDarwin()) 9870 return new DarwinPPC64TargetInfo(Triple, Opts); 9871 switch (os) { 9872 case llvm::Triple::Linux: 9873 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9874 case llvm::Triple::Lv2: 9875 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9876 case llvm::Triple::FreeBSD: 9877 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9878 case llvm::Triple::NetBSD: 9879 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9880 default: 9881 return new PPC64TargetInfo(Triple, Opts); 9882 } 9883 9884 case llvm::Triple::ppc64le: 9885 switch (os) { 9886 case llvm::Triple::Linux: 9887 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9888 case llvm::Triple::NetBSD: 9889 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9890 default: 9891 return new PPC64TargetInfo(Triple, Opts); 9892 } 9893 9894 case llvm::Triple::nvptx: 9895 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9896 case llvm::Triple::nvptx64: 9897 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9898 9899 case llvm::Triple::amdgcn: 9900 case llvm::Triple::r600: 9901 return new AMDGPUTargetInfo(Triple, Opts); 9902 9903 case llvm::Triple::sparc: 9904 switch (os) { 9905 case llvm::Triple::Linux: 9906 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9907 case llvm::Triple::Solaris: 9908 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9909 case llvm::Triple::NetBSD: 9910 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9911 case llvm::Triple::OpenBSD: 9912 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9913 case llvm::Triple::RTEMS: 9914 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9915 default: 9916 return new SparcV8TargetInfo(Triple, Opts); 9917 } 9918 9919 // The 'sparcel' architecture copies all the above cases except for Solaris. 9920 case llvm::Triple::sparcel: 9921 switch (os) { 9922 case llvm::Triple::Linux: 9923 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9924 case llvm::Triple::NetBSD: 9925 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9926 case llvm::Triple::OpenBSD: 9927 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9928 case llvm::Triple::RTEMS: 9929 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9930 default: 9931 return new SparcV8elTargetInfo(Triple, Opts); 9932 } 9933 9934 case llvm::Triple::sparcv9: 9935 switch (os) { 9936 case llvm::Triple::Linux: 9937 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9938 case llvm::Triple::Solaris: 9939 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9940 case llvm::Triple::NetBSD: 9941 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9942 case llvm::Triple::OpenBSD: 9943 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9944 case llvm::Triple::FreeBSD: 9945 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9946 default: 9947 return new SparcV9TargetInfo(Triple, Opts); 9948 } 9949 9950 case llvm::Triple::systemz: 9951 switch (os) { 9952 case llvm::Triple::Linux: 9953 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9954 default: 9955 return new SystemZTargetInfo(Triple, Opts); 9956 } 9957 9958 case llvm::Triple::tce: 9959 return new TCETargetInfo(Triple, Opts); 9960 9961 case llvm::Triple::tcele: 9962 return new TCELETargetInfo(Triple, Opts); 9963 9964 case llvm::Triple::x86: 9965 if (Triple.isOSDarwin()) 9966 return new DarwinI386TargetInfo(Triple, Opts); 9967 9968 switch (os) { 9969 case llvm::Triple::Ananas: 9970 return new AnanasTargetInfo<X86_32TargetInfo>(Triple, Opts); 9971 case llvm::Triple::CloudABI: 9972 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9973 case llvm::Triple::Linux: { 9974 switch (Triple.getEnvironment()) { 9975 default: 9976 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9977 case llvm::Triple::Android: 9978 return new AndroidX86_32TargetInfo(Triple, Opts); 9979 } 9980 } 9981 case llvm::Triple::DragonFly: 9982 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9983 case llvm::Triple::NetBSD: 9984 return new NetBSDI386TargetInfo(Triple, Opts); 9985 case llvm::Triple::OpenBSD: 9986 return new OpenBSDI386TargetInfo(Triple, Opts); 9987 case llvm::Triple::Bitrig: 9988 return new BitrigI386TargetInfo(Triple, Opts); 9989 case llvm::Triple::FreeBSD: 9990 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9991 case llvm::Triple::KFreeBSD: 9992 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9993 case llvm::Triple::Minix: 9994 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9995 case llvm::Triple::Solaris: 9996 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9997 case llvm::Triple::Win32: { 9998 switch (Triple.getEnvironment()) { 9999 case llvm::Triple::Cygnus: 10000 return new CygwinX86_32TargetInfo(Triple, Opts); 10001 case llvm::Triple::GNU: 10002 return new MinGWX86_32TargetInfo(Triple, Opts); 10003 case llvm::Triple::Itanium: 10004 case llvm::Triple::MSVC: 10005 default: // Assume MSVC for unknown environments 10006 return new MicrosoftX86_32TargetInfo(Triple, Opts); 10007 } 10008 } 10009 case llvm::Triple::Haiku: 10010 return new HaikuX86_32TargetInfo(Triple, Opts); 10011 case llvm::Triple::RTEMS: 10012 return new RTEMSX86_32TargetInfo(Triple, Opts); 10013 case llvm::Triple::NaCl: 10014 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 10015 case llvm::Triple::ELFIAMCU: 10016 return new MCUX86_32TargetInfo(Triple, Opts); 10017 default: 10018 return new X86_32TargetInfo(Triple, Opts); 10019 } 10020 10021 case llvm::Triple::x86_64: 10022 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 10023 return new DarwinX86_64TargetInfo(Triple, Opts); 10024 10025 switch (os) { 10026 case llvm::Triple::Ananas: 10027 return new AnanasTargetInfo<X86_64TargetInfo>(Triple, Opts); 10028 case llvm::Triple::CloudABI: 10029 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 10030 case llvm::Triple::Linux: { 10031 switch (Triple.getEnvironment()) { 10032 default: 10033 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 10034 case llvm::Triple::Android: 10035 return new AndroidX86_64TargetInfo(Triple, Opts); 10036 } 10037 } 10038 case llvm::Triple::DragonFly: 10039 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 10040 case llvm::Triple::NetBSD: 10041 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 10042 case llvm::Triple::OpenBSD: 10043 return new OpenBSDX86_64TargetInfo(Triple, Opts); 10044 case llvm::Triple::Bitrig: 10045 return new BitrigX86_64TargetInfo(Triple, Opts); 10046 case llvm::Triple::FreeBSD: 10047 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 10048 case llvm::Triple::Fuchsia: 10049 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 10050 case llvm::Triple::KFreeBSD: 10051 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 10052 case llvm::Triple::Solaris: 10053 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 10054 case llvm::Triple::Win32: { 10055 switch (Triple.getEnvironment()) { 10056 case llvm::Triple::Cygnus: 10057 return new CygwinX86_64TargetInfo(Triple, Opts); 10058 case llvm::Triple::GNU: 10059 return new MinGWX86_64TargetInfo(Triple, Opts); 10060 case llvm::Triple::MSVC: 10061 default: // Assume MSVC for unknown environments 10062 return new MicrosoftX86_64TargetInfo(Triple, Opts); 10063 } 10064 } 10065 case llvm::Triple::Haiku: 10066 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 10067 case llvm::Triple::NaCl: 10068 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 10069 case llvm::Triple::PS4: 10070 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 10071 default: 10072 return new X86_64TargetInfo(Triple, Opts); 10073 } 10074 10075 case llvm::Triple::spir: { 10076 if (Triple.getOS() != llvm::Triple::UnknownOS || 10077 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 10078 return nullptr; 10079 return new SPIR32TargetInfo(Triple, Opts); 10080 } 10081 case llvm::Triple::spir64: { 10082 if (Triple.getOS() != llvm::Triple::UnknownOS || 10083 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 10084 return nullptr; 10085 return new SPIR64TargetInfo(Triple, Opts); 10086 } 10087 case llvm::Triple::wasm32: 10088 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 10089 Triple.getVendor() != llvm::Triple::UnknownVendor || 10090 Triple.getOS() != llvm::Triple::UnknownOS || 10091 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 10092 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 10093 return nullptr; 10094 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 10095 case llvm::Triple::wasm64: 10096 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 10097 Triple.getVendor() != llvm::Triple::UnknownVendor || 10098 Triple.getOS() != llvm::Triple::UnknownOS || 10099 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 10100 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 10101 return nullptr; 10102 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 10103 10104 case llvm::Triple::renderscript32: 10105 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 10106 case llvm::Triple::renderscript64: 10107 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 10108 } 10109 } 10110 10111 /// CreateTargetInfo - Return the target info object for the specified target 10112 /// options. 10113 TargetInfo * 10114 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 10115 const std::shared_ptr<TargetOptions> &Opts) { 10116 llvm::Triple Triple(Opts->Triple); 10117 10118 // Construct the target 10119 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 10120 if (!Target) { 10121 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 10122 return nullptr; 10123 } 10124 Target->TargetOpts = Opts; 10125 10126 // Set the target CPU if specified. 10127 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 10128 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 10129 return nullptr; 10130 } 10131 10132 // Set the target ABI if specified. 10133 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 10134 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 10135 return nullptr; 10136 } 10137 10138 // Set the fp math unit. 10139 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 10140 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 10141 return nullptr; 10142 } 10143 10144 // Compute the default target features, we need the target to handle this 10145 // because features may have dependencies on one another. 10146 llvm::StringMap<bool> Features; 10147 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 10148 Opts->FeaturesAsWritten)) 10149 return nullptr; 10150 10151 // Add the features to the compile options. 10152 Opts->Features.clear(); 10153 for (const auto &F : Features) 10154 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 10155 10156 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 10157 return nullptr; 10158 10159 Target->setSupportedOpenCLOpts(); 10160 Target->setOpenCLExtensionOpts(); 10161 10162 if (!Target->validateTarget(Diags)) 10163 return nullptr; 10164 10165 return Target.release(); 10166 } 10167