1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 584 this->MaxTLSAlign = 256; 585 this->UserLabelPrefix = ""; 586 587 switch (Triple.getArch()) { 588 default: 589 case llvm::Triple::x86_64: 590 this->MCountName = ".mcount"; 591 break; 592 } 593 } 594 }; 595 596 // Solaris target 597 template<typename Target> 598 class SolarisTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const override { 602 DefineStd(Builder, "sun", Opts); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__svr4__"); 606 Builder.defineMacro("__SVR4"); 607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 608 // newer, but to 500 for everything else. feature_test.h has a check to 609 // ensure that you are not using C99 with an old version of X/Open or C89 610 // with a new version. 611 if (Opts.C99) 612 Builder.defineMacro("_XOPEN_SOURCE", "600"); 613 else 614 Builder.defineMacro("_XOPEN_SOURCE", "500"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("__C99FEATURES__"); 617 Builder.defineMacro("_LARGEFILE_SOURCE"); 618 Builder.defineMacro("_LARGEFILE64_SOURCE"); 619 Builder.defineMacro("__EXTENSIONS__"); 620 Builder.defineMacro("_REENTRANT"); 621 } 622 public: 623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 624 this->UserLabelPrefix = ""; 625 this->WCharType = this->SignedInt; 626 // FIXME: WIntType should be SignedLong 627 } 628 }; 629 630 // Windows target 631 template<typename Target> 632 class WindowsTargetInfo : public OSTargetInfo<Target> { 633 protected: 634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 635 MacroBuilder &Builder) const override { 636 Builder.defineMacro("_WIN32"); 637 } 638 void getVisualStudioDefines(const LangOptions &Opts, 639 MacroBuilder &Builder) const { 640 if (Opts.CPlusPlus) { 641 if (Opts.RTTIData) 642 Builder.defineMacro("_CPPRTTI"); 643 644 if (Opts.CXXExceptions) 645 Builder.defineMacro("_CPPUNWIND"); 646 } 647 648 if (Opts.Bool) 649 Builder.defineMacro("__BOOL_DEFINED"); 650 651 if (!Opts.CharIsSigned) 652 Builder.defineMacro("_CHAR_UNSIGNED"); 653 654 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 655 // but it works for now. 656 if (Opts.POSIXThreads) 657 Builder.defineMacro("_MT"); 658 659 if (Opts.MSCompatibilityVersion) { 660 Builder.defineMacro("_MSC_VER", 661 Twine(Opts.MSCompatibilityVersion / 100000)); 662 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 663 // FIXME We cannot encode the revision information into 32-bits 664 Builder.defineMacro("_MSC_BUILD", Twine(1)); 665 666 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 667 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 668 } 669 670 if (Opts.MicrosoftExt) { 671 Builder.defineMacro("_MSC_EXTENSIONS"); 672 673 if (Opts.CPlusPlus11) { 674 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 675 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 676 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 677 } 678 } 679 680 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 681 } 682 683 public: 684 WindowsTargetInfo(const llvm::Triple &Triple) 685 : OSTargetInfo<Target>(Triple) {} 686 }; 687 688 template <typename Target> 689 class NaClTargetInfo : public OSTargetInfo<Target> { 690 protected: 691 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 692 MacroBuilder &Builder) const override { 693 if (Opts.POSIXThreads) 694 Builder.defineMacro("_REENTRANT"); 695 if (Opts.CPlusPlus) 696 Builder.defineMacro("_GNU_SOURCE"); 697 698 DefineStd(Builder, "unix", Opts); 699 Builder.defineMacro("__ELF__"); 700 Builder.defineMacro("__native_client__"); 701 } 702 703 public: 704 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 705 this->UserLabelPrefix = ""; 706 this->LongAlign = 32; 707 this->LongWidth = 32; 708 this->PointerAlign = 32; 709 this->PointerWidth = 32; 710 this->IntMaxType = TargetInfo::SignedLongLong; 711 this->Int64Type = TargetInfo::SignedLongLong; 712 this->DoubleAlign = 64; 713 this->LongDoubleWidth = 64; 714 this->LongDoubleAlign = 64; 715 this->LongLongWidth = 64; 716 this->LongLongAlign = 64; 717 this->SizeType = TargetInfo::UnsignedInt; 718 this->PtrDiffType = TargetInfo::SignedInt; 719 this->IntPtrType = TargetInfo::SignedInt; 720 // RegParmMax is inherited from the underlying architecture 721 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 722 if (Triple.getArch() == llvm::Triple::arm) { 723 // Handled in ARM's setABI(). 724 } else if (Triple.getArch() == llvm::Triple::x86) { 725 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 726 } else if (Triple.getArch() == llvm::Triple::x86_64) { 727 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 728 } else if (Triple.getArch() == llvm::Triple::mipsel) { 729 // Handled on mips' setDataLayoutString. 730 } else { 731 assert(Triple.getArch() == llvm::Triple::le32); 732 this->DataLayoutString = "e-p:32:32-i64:64"; 733 } 734 } 735 }; 736 737 //===----------------------------------------------------------------------===// 738 // Specific target implementations. 739 //===----------------------------------------------------------------------===// 740 741 // PPC abstract base class 742 class PPCTargetInfo : public TargetInfo { 743 static const Builtin::Info BuiltinInfo[]; 744 static const char * const GCCRegNames[]; 745 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 746 std::string CPU; 747 748 // Target cpu features. 749 bool HasVSX; 750 bool HasP8Vector; 751 bool HasP8Crypto; 752 bool HasDirectMove; 753 bool HasQPX; 754 bool HasHTM; 755 bool HasBPERMD; 756 bool HasExtDiv; 757 758 protected: 759 std::string ABI; 760 761 public: 762 PPCTargetInfo(const llvm::Triple &Triple) 763 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 764 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 765 HasBPERMD(false), HasExtDiv(false) { 766 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 767 SimdDefaultAlign = 128; 768 LongDoubleWidth = LongDoubleAlign = 128; 769 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 770 } 771 772 /// \brief Flags for architecture specific defines. 773 typedef enum { 774 ArchDefineNone = 0, 775 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 776 ArchDefinePpcgr = 1 << 1, 777 ArchDefinePpcsq = 1 << 2, 778 ArchDefine440 = 1 << 3, 779 ArchDefine603 = 1 << 4, 780 ArchDefine604 = 1 << 5, 781 ArchDefinePwr4 = 1 << 6, 782 ArchDefinePwr5 = 1 << 7, 783 ArchDefinePwr5x = 1 << 8, 784 ArchDefinePwr6 = 1 << 9, 785 ArchDefinePwr6x = 1 << 10, 786 ArchDefinePwr7 = 1 << 11, 787 ArchDefinePwr8 = 1 << 12, 788 ArchDefineA2 = 1 << 13, 789 ArchDefineA2q = 1 << 14 790 } ArchDefineTypes; 791 792 // Note: GCC recognizes the following additional cpus: 793 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 794 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 795 // titan, rs64. 796 bool setCPU(const std::string &Name) override { 797 bool CPUKnown = llvm::StringSwitch<bool>(Name) 798 .Case("generic", true) 799 .Case("440", true) 800 .Case("450", true) 801 .Case("601", true) 802 .Case("602", true) 803 .Case("603", true) 804 .Case("603e", true) 805 .Case("603ev", true) 806 .Case("604", true) 807 .Case("604e", true) 808 .Case("620", true) 809 .Case("630", true) 810 .Case("g3", true) 811 .Case("7400", true) 812 .Case("g4", true) 813 .Case("7450", true) 814 .Case("g4+", true) 815 .Case("750", true) 816 .Case("970", true) 817 .Case("g5", true) 818 .Case("a2", true) 819 .Case("a2q", true) 820 .Case("e500mc", true) 821 .Case("e5500", true) 822 .Case("power3", true) 823 .Case("pwr3", true) 824 .Case("power4", true) 825 .Case("pwr4", true) 826 .Case("power5", true) 827 .Case("pwr5", true) 828 .Case("power5x", true) 829 .Case("pwr5x", true) 830 .Case("power6", true) 831 .Case("pwr6", true) 832 .Case("power6x", true) 833 .Case("pwr6x", true) 834 .Case("power7", true) 835 .Case("pwr7", true) 836 .Case("power8", true) 837 .Case("pwr8", true) 838 .Case("powerpc", true) 839 .Case("ppc", true) 840 .Case("powerpc64", true) 841 .Case("ppc64", true) 842 .Case("powerpc64le", true) 843 .Case("ppc64le", true) 844 .Default(false); 845 846 if (CPUKnown) 847 CPU = Name; 848 849 return CPUKnown; 850 } 851 852 853 StringRef getABI() const override { return ABI; } 854 855 void getTargetBuiltins(const Builtin::Info *&Records, 856 unsigned &NumRecords) const override { 857 Records = BuiltinInfo; 858 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 859 } 860 861 bool isCLZForZeroUndef() const override { return false; } 862 863 void getTargetDefines(const LangOptions &Opts, 864 MacroBuilder &Builder) const override; 865 866 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 867 StringRef CPU, 868 std::vector<std::string> &FeaturesVec) const override; 869 870 bool handleTargetFeatures(std::vector<std::string> &Features, 871 DiagnosticsEngine &Diags) override; 872 bool hasFeature(StringRef Feature) const override; 873 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 874 bool Enabled) const override; 875 876 void getGCCRegNames(const char * const *&Names, 877 unsigned &NumNames) const override; 878 void getGCCRegAliases(const GCCRegAlias *&Aliases, 879 unsigned &NumAliases) const override; 880 bool validateAsmConstraint(const char *&Name, 881 TargetInfo::ConstraintInfo &Info) const override { 882 switch (*Name) { 883 default: return false; 884 case 'O': // Zero 885 break; 886 case 'b': // Base register 887 case 'f': // Floating point register 888 Info.setAllowsRegister(); 889 break; 890 // FIXME: The following are added to allow parsing. 891 // I just took a guess at what the actions should be. 892 // Also, is more specific checking needed? I.e. specific registers? 893 case 'd': // Floating point register (containing 64-bit value) 894 case 'v': // Altivec vector register 895 Info.setAllowsRegister(); 896 break; 897 case 'w': 898 switch (Name[1]) { 899 case 'd':// VSX vector register to hold vector double data 900 case 'f':// VSX vector register to hold vector float data 901 case 's':// VSX vector register to hold scalar float data 902 case 'a':// Any VSX register 903 case 'c':// An individual CR bit 904 break; 905 default: 906 return false; 907 } 908 Info.setAllowsRegister(); 909 Name++; // Skip over 'w'. 910 break; 911 case 'h': // `MQ', `CTR', or `LINK' register 912 case 'q': // `MQ' register 913 case 'c': // `CTR' register 914 case 'l': // `LINK' register 915 case 'x': // `CR' register (condition register) number 0 916 case 'y': // `CR' register (condition register) 917 case 'z': // `XER[CA]' carry bit (part of the XER register) 918 Info.setAllowsRegister(); 919 break; 920 case 'I': // Signed 16-bit constant 921 case 'J': // Unsigned 16-bit constant shifted left 16 bits 922 // (use `L' instead for SImode constants) 923 case 'K': // Unsigned 16-bit constant 924 case 'L': // Signed 16-bit constant shifted left 16 bits 925 case 'M': // Constant larger than 31 926 case 'N': // Exact power of 2 927 case 'P': // Constant whose negation is a signed 16-bit constant 928 case 'G': // Floating point constant that can be loaded into a 929 // register with one instruction per word 930 case 'H': // Integer/Floating point constant that can be loaded 931 // into a register using three instructions 932 break; 933 case 'm': // Memory operand. Note that on PowerPC targets, m can 934 // include addresses that update the base register. It 935 // is therefore only safe to use `m' in an asm statement 936 // if that asm statement accesses the operand exactly once. 937 // The asm statement must also use `%U<opno>' as a 938 // placeholder for the "update" flag in the corresponding 939 // load or store instruction. For example: 940 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 941 // is correct but: 942 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 943 // is not. Use es rather than m if you don't want the base 944 // register to be updated. 945 case 'e': 946 if (Name[1] != 's') 947 return false; 948 // es: A "stable" memory operand; that is, one which does not 949 // include any automodification of the base register. Unlike 950 // `m', this constraint can be used in asm statements that 951 // might access the operand several times, or that might not 952 // access it at all. 953 Info.setAllowsMemory(); 954 Name++; // Skip over 'e'. 955 break; 956 case 'Q': // Memory operand that is an offset from a register (it is 957 // usually better to use `m' or `es' in asm statements) 958 case 'Z': // Memory operand that is an indexed or indirect from a 959 // register (it is usually better to use `m' or `es' in 960 // asm statements) 961 Info.setAllowsMemory(); 962 Info.setAllowsRegister(); 963 break; 964 case 'R': // AIX TOC entry 965 case 'a': // Address operand that is an indexed or indirect from a 966 // register (`p' is preferable for asm statements) 967 case 'S': // Constant suitable as a 64-bit mask operand 968 case 'T': // Constant suitable as a 32-bit mask operand 969 case 'U': // System V Release 4 small data area reference 970 case 't': // AND masks that can be performed by two rldic{l, r} 971 // instructions 972 case 'W': // Vector constant that does not require memory 973 case 'j': // Vector constant that is all zeros. 974 break; 975 // End FIXME. 976 } 977 return true; 978 } 979 std::string convertConstraint(const char *&Constraint) const override { 980 std::string R; 981 switch (*Constraint) { 982 case 'e': 983 case 'w': 984 // Two-character constraint; add "^" hint for later parsing. 985 R = std::string("^") + std::string(Constraint, 2); 986 Constraint++; 987 break; 988 default: 989 return TargetInfo::convertConstraint(Constraint); 990 } 991 return R; 992 } 993 const char *getClobbers() const override { 994 return ""; 995 } 996 int getEHDataRegisterNumber(unsigned RegNo) const override { 997 if (RegNo == 0) return 3; 998 if (RegNo == 1) return 4; 999 return -1; 1000 } 1001 1002 bool hasSjLjLowering() const override { 1003 return true; 1004 } 1005 1006 bool useFloat128ManglingForLongDouble() const override { 1007 return LongDoubleWidth == 128 && 1008 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1009 getTriple().isOSBinFormatELF(); 1010 } 1011 }; 1012 1013 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1014 #define BUILTIN(ID, TYPE, ATTRS) \ 1015 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1016 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1017 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1018 #include "clang/Basic/BuiltinsPPC.def" 1019 }; 1020 1021 /// handleTargetFeatures - Perform initialization based on the user 1022 /// configured set of features. 1023 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1024 DiagnosticsEngine &Diags) { 1025 for (const auto &Feature : Features) { 1026 if (Feature == "+vsx") { 1027 HasVSX = true; 1028 } else if (Feature == "+bpermd") { 1029 HasBPERMD = true; 1030 } else if (Feature == "+extdiv") { 1031 HasExtDiv = true; 1032 } else if (Feature == "+power8-vector") { 1033 HasP8Vector = true; 1034 } else if (Feature == "+crypto") { 1035 HasP8Crypto = true; 1036 } else if (Feature == "+direct-move") { 1037 HasDirectMove = true; 1038 } else if (Feature == "+qpx") { 1039 HasQPX = true; 1040 } else if (Feature == "+htm") { 1041 HasHTM = true; 1042 } 1043 // TODO: Finish this list and add an assert that we've handled them 1044 // all. 1045 } 1046 1047 return true; 1048 } 1049 1050 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1051 /// #defines that are not tied to a specific subtarget. 1052 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1053 MacroBuilder &Builder) const { 1054 // Target identification. 1055 Builder.defineMacro("__ppc__"); 1056 Builder.defineMacro("__PPC__"); 1057 Builder.defineMacro("_ARCH_PPC"); 1058 Builder.defineMacro("__powerpc__"); 1059 Builder.defineMacro("__POWERPC__"); 1060 if (PointerWidth == 64) { 1061 Builder.defineMacro("_ARCH_PPC64"); 1062 Builder.defineMacro("__powerpc64__"); 1063 Builder.defineMacro("__ppc64__"); 1064 Builder.defineMacro("__PPC64__"); 1065 } 1066 1067 // Target properties. 1068 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1069 Builder.defineMacro("_LITTLE_ENDIAN"); 1070 } else { 1071 if (getTriple().getOS() != llvm::Triple::NetBSD && 1072 getTriple().getOS() != llvm::Triple::OpenBSD) 1073 Builder.defineMacro("_BIG_ENDIAN"); 1074 } 1075 1076 // ABI options. 1077 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1078 Builder.defineMacro("_CALL_ELF", "1"); 1079 if (ABI == "elfv2") 1080 Builder.defineMacro("_CALL_ELF", "2"); 1081 1082 // Subtarget options. 1083 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1084 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1085 1086 // FIXME: Should be controlled by command line option. 1087 if (LongDoubleWidth == 128) 1088 Builder.defineMacro("__LONG_DOUBLE_128__"); 1089 1090 if (Opts.AltiVec) { 1091 Builder.defineMacro("__VEC__", "10206"); 1092 Builder.defineMacro("__ALTIVEC__"); 1093 } 1094 1095 // CPU identification. 1096 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1097 .Case("440", ArchDefineName) 1098 .Case("450", ArchDefineName | ArchDefine440) 1099 .Case("601", ArchDefineName) 1100 .Case("602", ArchDefineName | ArchDefinePpcgr) 1101 .Case("603", ArchDefineName | ArchDefinePpcgr) 1102 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1103 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1104 .Case("604", ArchDefineName | ArchDefinePpcgr) 1105 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1106 .Case("620", ArchDefineName | ArchDefinePpcgr) 1107 .Case("630", ArchDefineName | ArchDefinePpcgr) 1108 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1109 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1110 .Case("750", ArchDefineName | ArchDefinePpcgr) 1111 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1112 | ArchDefinePpcsq) 1113 .Case("a2", ArchDefineA2) 1114 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1115 .Case("pwr3", ArchDefinePpcgr) 1116 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1117 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1118 | ArchDefinePpcsq) 1119 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1120 | ArchDefinePpcgr | ArchDefinePpcsq) 1121 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1122 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1123 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1124 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1125 | ArchDefinePpcsq) 1126 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1127 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1128 | ArchDefinePpcgr | ArchDefinePpcsq) 1129 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1130 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1131 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1132 .Case("power3", ArchDefinePpcgr) 1133 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1134 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1135 | ArchDefinePpcsq) 1136 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1137 | ArchDefinePpcgr | ArchDefinePpcsq) 1138 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1139 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1140 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1141 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1144 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1145 | ArchDefinePpcgr | ArchDefinePpcsq) 1146 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1147 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1148 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1149 .Default(ArchDefineNone); 1150 1151 if (defs & ArchDefineName) 1152 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1153 if (defs & ArchDefinePpcgr) 1154 Builder.defineMacro("_ARCH_PPCGR"); 1155 if (defs & ArchDefinePpcsq) 1156 Builder.defineMacro("_ARCH_PPCSQ"); 1157 if (defs & ArchDefine440) 1158 Builder.defineMacro("_ARCH_440"); 1159 if (defs & ArchDefine603) 1160 Builder.defineMacro("_ARCH_603"); 1161 if (defs & ArchDefine604) 1162 Builder.defineMacro("_ARCH_604"); 1163 if (defs & ArchDefinePwr4) 1164 Builder.defineMacro("_ARCH_PWR4"); 1165 if (defs & ArchDefinePwr5) 1166 Builder.defineMacro("_ARCH_PWR5"); 1167 if (defs & ArchDefinePwr5x) 1168 Builder.defineMacro("_ARCH_PWR5X"); 1169 if (defs & ArchDefinePwr6) 1170 Builder.defineMacro("_ARCH_PWR6"); 1171 if (defs & ArchDefinePwr6x) 1172 Builder.defineMacro("_ARCH_PWR6X"); 1173 if (defs & ArchDefinePwr7) 1174 Builder.defineMacro("_ARCH_PWR7"); 1175 if (defs & ArchDefinePwr8) 1176 Builder.defineMacro("_ARCH_PWR8"); 1177 if (defs & ArchDefineA2) 1178 Builder.defineMacro("_ARCH_A2"); 1179 if (defs & ArchDefineA2q) { 1180 Builder.defineMacro("_ARCH_A2Q"); 1181 Builder.defineMacro("_ARCH_QP"); 1182 } 1183 1184 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1185 Builder.defineMacro("__bg__"); 1186 Builder.defineMacro("__THW_BLUEGENE__"); 1187 Builder.defineMacro("__bgq__"); 1188 Builder.defineMacro("__TOS_BGQ__"); 1189 } 1190 1191 if (HasVSX) 1192 Builder.defineMacro("__VSX__"); 1193 if (HasP8Vector) 1194 Builder.defineMacro("__POWER8_VECTOR__"); 1195 if (HasP8Crypto) 1196 Builder.defineMacro("__CRYPTO__"); 1197 if (HasHTM) 1198 Builder.defineMacro("__HTM__"); 1199 if (getTriple().getArch() == llvm::Triple::ppc64le || 1200 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1201 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1202 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1203 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1204 if (PointerWidth == 64) 1205 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1206 } 1207 1208 // FIXME: The following are not yet generated here by Clang, but are 1209 // generated by GCC: 1210 // 1211 // _SOFT_FLOAT_ 1212 // __RECIP_PRECISION__ 1213 // __APPLE_ALTIVEC__ 1214 // __RECIP__ 1215 // __RECIPF__ 1216 // __RSQRTE__ 1217 // __RSQRTEF__ 1218 // _SOFT_DOUBLE_ 1219 // __NO_LWSYNC__ 1220 // __HAVE_BSWAP__ 1221 // __LONGDOUBLE128 1222 // __CMODEL_MEDIUM__ 1223 // __CMODEL_LARGE__ 1224 // _CALL_SYSV 1225 // _CALL_DARWIN 1226 // __NO_FPRS__ 1227 } 1228 1229 bool PPCTargetInfo::initFeatureMap( 1230 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1231 std::vector<std::string> &FeaturesVec) const { 1232 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1233 .Case("7400", true) 1234 .Case("g4", true) 1235 .Case("7450", true) 1236 .Case("g4+", true) 1237 .Case("970", true) 1238 .Case("g5", true) 1239 .Case("pwr6", true) 1240 .Case("pwr7", true) 1241 .Case("pwr8", true) 1242 .Case("ppc64", true) 1243 .Case("ppc64le", true) 1244 .Default(false); 1245 1246 Features["qpx"] = (CPU == "a2q"); 1247 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1248 .Case("ppc64le", true) 1249 .Case("pwr8", true) 1250 .Default(false); 1251 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1252 .Case("ppc64le", true) 1253 .Case("pwr8", true) 1254 .Default(false); 1255 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1256 .Case("ppc64le", true) 1257 .Case("pwr8", true) 1258 .Case("pwr7", true) 1259 .Default(false); 1260 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1261 .Case("ppc64le", true) 1262 .Case("pwr8", true) 1263 .Case("pwr7", true) 1264 .Default(false); 1265 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1266 .Case("ppc64le", true) 1267 .Case("pwr8", true) 1268 .Default(false); 1269 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1270 .Case("ppc64le", true) 1271 .Case("pwr8", true) 1272 .Case("pwr7", true) 1273 .Default(false); 1274 1275 // Handle explicit options being passed to the compiler here: if we've 1276 // explicitly turned off vsx and turned on power8-vector or direct-move then 1277 // go ahead and error since the customer has expressed a somewhat incompatible 1278 // set of options. 1279 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1280 FeaturesVec.end()) { 1281 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1282 FeaturesVec.end()) { 1283 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1284 << "-mno-vsx"; 1285 return false; 1286 } 1287 1288 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1289 FeaturesVec.end()) { 1290 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1291 << "-mno-vsx"; 1292 return false; 1293 } 1294 } 1295 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1296 } 1297 1298 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1299 return llvm::StringSwitch<bool>(Feature) 1300 .Case("powerpc", true) 1301 .Case("vsx", HasVSX) 1302 .Case("power8-vector", HasP8Vector) 1303 .Case("crypto", HasP8Crypto) 1304 .Case("direct-move", HasDirectMove) 1305 .Case("qpx", HasQPX) 1306 .Case("htm", HasHTM) 1307 .Case("bpermd", HasBPERMD) 1308 .Case("extdiv", HasExtDiv) 1309 .Default(false); 1310 } 1311 1312 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1313 StringRef Name, bool Enabled) const { 1314 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1315 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1316 // incompatible options. 1317 if (Enabled) { 1318 if (Name == "vsx") { 1319 Features[Name] = true; 1320 } else if (Name == "direct-move") { 1321 Features[Name] = Features["vsx"] = true; 1322 } else if (Name == "power8-vector") { 1323 Features[Name] = Features["vsx"] = true; 1324 } else { 1325 Features[Name] = true; 1326 } 1327 } else { 1328 if (Name == "vsx") { 1329 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1330 false; 1331 } else { 1332 Features[Name] = false; 1333 } 1334 } 1335 } 1336 1337 const char * const PPCTargetInfo::GCCRegNames[] = { 1338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1340 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1341 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1342 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1343 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1344 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1345 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1346 "mq", "lr", "ctr", "ap", 1347 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1348 "xer", 1349 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1350 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1351 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1352 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1353 "vrsave", "vscr", 1354 "spe_acc", "spefscr", 1355 "sfp" 1356 }; 1357 1358 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1359 unsigned &NumNames) const { 1360 Names = GCCRegNames; 1361 NumNames = llvm::array_lengthof(GCCRegNames); 1362 } 1363 1364 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1365 // While some of these aliases do map to different registers 1366 // they still share the same register name. 1367 { { "0" }, "r0" }, 1368 { { "1"}, "r1" }, 1369 { { "2" }, "r2" }, 1370 { { "3" }, "r3" }, 1371 { { "4" }, "r4" }, 1372 { { "5" }, "r5" }, 1373 { { "6" }, "r6" }, 1374 { { "7" }, "r7" }, 1375 { { "8" }, "r8" }, 1376 { { "9" }, "r9" }, 1377 { { "10" }, "r10" }, 1378 { { "11" }, "r11" }, 1379 { { "12" }, "r12" }, 1380 { { "13" }, "r13" }, 1381 { { "14" }, "r14" }, 1382 { { "15" }, "r15" }, 1383 { { "16" }, "r16" }, 1384 { { "17" }, "r17" }, 1385 { { "18" }, "r18" }, 1386 { { "19" }, "r19" }, 1387 { { "20" }, "r20" }, 1388 { { "21" }, "r21" }, 1389 { { "22" }, "r22" }, 1390 { { "23" }, "r23" }, 1391 { { "24" }, "r24" }, 1392 { { "25" }, "r25" }, 1393 { { "26" }, "r26" }, 1394 { { "27" }, "r27" }, 1395 { { "28" }, "r28" }, 1396 { { "29" }, "r29" }, 1397 { { "30" }, "r30" }, 1398 { { "31" }, "r31" }, 1399 { { "fr0" }, "f0" }, 1400 { { "fr1" }, "f1" }, 1401 { { "fr2" }, "f2" }, 1402 { { "fr3" }, "f3" }, 1403 { { "fr4" }, "f4" }, 1404 { { "fr5" }, "f5" }, 1405 { { "fr6" }, "f6" }, 1406 { { "fr7" }, "f7" }, 1407 { { "fr8" }, "f8" }, 1408 { { "fr9" }, "f9" }, 1409 { { "fr10" }, "f10" }, 1410 { { "fr11" }, "f11" }, 1411 { { "fr12" }, "f12" }, 1412 { { "fr13" }, "f13" }, 1413 { { "fr14" }, "f14" }, 1414 { { "fr15" }, "f15" }, 1415 { { "fr16" }, "f16" }, 1416 { { "fr17" }, "f17" }, 1417 { { "fr18" }, "f18" }, 1418 { { "fr19" }, "f19" }, 1419 { { "fr20" }, "f20" }, 1420 { { "fr21" }, "f21" }, 1421 { { "fr22" }, "f22" }, 1422 { { "fr23" }, "f23" }, 1423 { { "fr24" }, "f24" }, 1424 { { "fr25" }, "f25" }, 1425 { { "fr26" }, "f26" }, 1426 { { "fr27" }, "f27" }, 1427 { { "fr28" }, "f28" }, 1428 { { "fr29" }, "f29" }, 1429 { { "fr30" }, "f30" }, 1430 { { "fr31" }, "f31" }, 1431 { { "cc" }, "cr0" }, 1432 }; 1433 1434 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1435 unsigned &NumAliases) const { 1436 Aliases = GCCRegAliases; 1437 NumAliases = llvm::array_lengthof(GCCRegAliases); 1438 } 1439 1440 class PPC32TargetInfo : public PPCTargetInfo { 1441 public: 1442 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1443 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1444 1445 switch (getTriple().getOS()) { 1446 case llvm::Triple::Linux: 1447 case llvm::Triple::FreeBSD: 1448 case llvm::Triple::NetBSD: 1449 SizeType = UnsignedInt; 1450 PtrDiffType = SignedInt; 1451 IntPtrType = SignedInt; 1452 break; 1453 default: 1454 break; 1455 } 1456 1457 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1458 LongDoubleWidth = LongDoubleAlign = 64; 1459 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1460 } 1461 1462 // PPC32 supports atomics up to 4 bytes. 1463 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1464 } 1465 1466 BuiltinVaListKind getBuiltinVaListKind() const override { 1467 // This is the ELF definition, and is overridden by the Darwin sub-target 1468 return TargetInfo::PowerABIBuiltinVaList; 1469 } 1470 }; 1471 1472 // Note: ABI differences may eventually require us to have a separate 1473 // TargetInfo for little endian. 1474 class PPC64TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1478 IntMaxType = SignedLong; 1479 Int64Type = SignedLong; 1480 1481 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1482 DataLayoutString = "e-m:e-i64:64-n32:64"; 1483 ABI = "elfv2"; 1484 } else { 1485 DataLayoutString = "E-m:e-i64:64-n32:64"; 1486 ABI = "elfv1"; 1487 } 1488 1489 switch (getTriple().getOS()) { 1490 case llvm::Triple::FreeBSD: 1491 LongDoubleWidth = LongDoubleAlign = 64; 1492 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1493 break; 1494 case llvm::Triple::NetBSD: 1495 IntMaxType = SignedLongLong; 1496 Int64Type = SignedLongLong; 1497 break; 1498 default: 1499 break; 1500 } 1501 1502 // PPC64 supports atomics up to 8 bytes. 1503 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1504 } 1505 BuiltinVaListKind getBuiltinVaListKind() const override { 1506 return TargetInfo::CharPtrBuiltinVaList; 1507 } 1508 // PPC64 Linux-specific ABI options. 1509 bool setABI(const std::string &Name) override { 1510 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1511 ABI = Name; 1512 return true; 1513 } 1514 return false; 1515 } 1516 }; 1517 1518 class DarwinPPC32TargetInfo : 1519 public DarwinTargetInfo<PPC32TargetInfo> { 1520 public: 1521 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1522 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1523 HasAlignMac68kSupport = true; 1524 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1525 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1526 LongLongAlign = 32; 1527 SuitableAlign = 128; 1528 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1529 } 1530 BuiltinVaListKind getBuiltinVaListKind() const override { 1531 return TargetInfo::CharPtrBuiltinVaList; 1532 } 1533 }; 1534 1535 class DarwinPPC64TargetInfo : 1536 public DarwinTargetInfo<PPC64TargetInfo> { 1537 public: 1538 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1539 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1540 HasAlignMac68kSupport = true; 1541 SuitableAlign = 128; 1542 DataLayoutString = "E-m:o-i64:64-n32:64"; 1543 } 1544 }; 1545 1546 static const unsigned NVPTXAddrSpaceMap[] = { 1547 1, // opencl_global 1548 3, // opencl_local 1549 4, // opencl_constant 1550 // FIXME: generic has to be added to the target 1551 0, // opencl_generic 1552 1, // cuda_device 1553 4, // cuda_constant 1554 3, // cuda_shared 1555 }; 1556 class NVPTXTargetInfo : public TargetInfo { 1557 static const char * const GCCRegNames[]; 1558 static const Builtin::Info BuiltinInfo[]; 1559 1560 // The GPU profiles supported by the NVPTX backend 1561 enum GPUKind { 1562 GK_NONE, 1563 GK_SM20, 1564 GK_SM21, 1565 GK_SM30, 1566 GK_SM35, 1567 GK_SM37, 1568 } GPU; 1569 1570 public: 1571 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1572 BigEndian = false; 1573 TLSSupported = false; 1574 LongWidth = LongAlign = 64; 1575 AddrSpaceMap = &NVPTXAddrSpaceMap; 1576 UseAddrSpaceMapMangling = true; 1577 // Define available target features 1578 // These must be defined in sorted order! 1579 NoAsmVariants = true; 1580 // Set the default GPU to sm20 1581 GPU = GK_SM20; 1582 } 1583 void getTargetDefines(const LangOptions &Opts, 1584 MacroBuilder &Builder) const override { 1585 Builder.defineMacro("__PTX__"); 1586 Builder.defineMacro("__NVPTX__"); 1587 if (Opts.CUDAIsDevice) { 1588 // Set __CUDA_ARCH__ for the GPU specified. 1589 std::string CUDAArchCode; 1590 switch (GPU) { 1591 case GK_SM20: 1592 CUDAArchCode = "200"; 1593 break; 1594 case GK_SM21: 1595 CUDAArchCode = "210"; 1596 break; 1597 case GK_SM30: 1598 CUDAArchCode = "300"; 1599 break; 1600 case GK_SM35: 1601 CUDAArchCode = "350"; 1602 break; 1603 case GK_SM37: 1604 CUDAArchCode = "370"; 1605 break; 1606 default: 1607 llvm_unreachable("Unhandled target CPU"); 1608 } 1609 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1610 } 1611 } 1612 void getTargetBuiltins(const Builtin::Info *&Records, 1613 unsigned &NumRecords) const override { 1614 Records = BuiltinInfo; 1615 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1616 } 1617 bool hasFeature(StringRef Feature) const override { 1618 return Feature == "ptx" || Feature == "nvptx"; 1619 } 1620 1621 void getGCCRegNames(const char * const *&Names, 1622 unsigned &NumNames) const override; 1623 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1624 unsigned &NumAliases) const override { 1625 // No aliases. 1626 Aliases = nullptr; 1627 NumAliases = 0; 1628 } 1629 bool 1630 validateAsmConstraint(const char *&Name, 1631 TargetInfo::ConstraintInfo &Info) const override { 1632 switch (*Name) { 1633 default: return false; 1634 case 'c': 1635 case 'h': 1636 case 'r': 1637 case 'l': 1638 case 'f': 1639 case 'd': 1640 Info.setAllowsRegister(); 1641 return true; 1642 } 1643 } 1644 const char *getClobbers() const override { 1645 // FIXME: Is this really right? 1646 return ""; 1647 } 1648 BuiltinVaListKind getBuiltinVaListKind() const override { 1649 // FIXME: implement 1650 return TargetInfo::CharPtrBuiltinVaList; 1651 } 1652 bool setCPU(const std::string &Name) override { 1653 GPU = llvm::StringSwitch<GPUKind>(Name) 1654 .Case("sm_20", GK_SM20) 1655 .Case("sm_21", GK_SM21) 1656 .Case("sm_30", GK_SM30) 1657 .Case("sm_35", GK_SM35) 1658 .Case("sm_37", GK_SM37) 1659 .Default(GK_NONE); 1660 1661 return GPU != GK_NONE; 1662 } 1663 }; 1664 1665 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1666 #define BUILTIN(ID, TYPE, ATTRS) \ 1667 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1668 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1669 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1670 #include "clang/Basic/BuiltinsNVPTX.def" 1671 }; 1672 1673 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1674 "r0" 1675 }; 1676 1677 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1678 unsigned &NumNames) const { 1679 Names = GCCRegNames; 1680 NumNames = llvm::array_lengthof(GCCRegNames); 1681 } 1682 1683 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1684 public: 1685 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1686 PointerWidth = PointerAlign = 32; 1687 SizeType = TargetInfo::UnsignedInt; 1688 PtrDiffType = TargetInfo::SignedInt; 1689 IntPtrType = TargetInfo::SignedInt; 1690 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1691 } 1692 }; 1693 1694 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1695 public: 1696 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1697 PointerWidth = PointerAlign = 64; 1698 SizeType = TargetInfo::UnsignedLong; 1699 PtrDiffType = TargetInfo::SignedLong; 1700 IntPtrType = TargetInfo::SignedLong; 1701 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1702 } 1703 }; 1704 1705 static const unsigned AMDGPUAddrSpaceMap[] = { 1706 1, // opencl_global 1707 3, // opencl_local 1708 2, // opencl_constant 1709 4, // opencl_generic 1710 1, // cuda_device 1711 2, // cuda_constant 1712 3 // cuda_shared 1713 }; 1714 1715 // If you edit the description strings, make sure you update 1716 // getPointerWidthV(). 1717 1718 static const char *DataLayoutStringR600 = 1719 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1720 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1721 1722 static const char *DataLayoutStringR600DoubleOps = 1723 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1724 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1725 1726 static const char *DataLayoutStringSI = 1727 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1728 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1729 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1730 1731 class AMDGPUTargetInfo : public TargetInfo { 1732 static const Builtin::Info BuiltinInfo[]; 1733 static const char * const GCCRegNames[]; 1734 1735 /// \brief The GPU profiles supported by the AMDGPU target. 1736 enum GPUKind { 1737 GK_NONE, 1738 GK_R600, 1739 GK_R600_DOUBLE_OPS, 1740 GK_R700, 1741 GK_R700_DOUBLE_OPS, 1742 GK_EVERGREEN, 1743 GK_EVERGREEN_DOUBLE_OPS, 1744 GK_NORTHERN_ISLANDS, 1745 GK_CAYMAN, 1746 GK_SOUTHERN_ISLANDS, 1747 GK_SEA_ISLANDS, 1748 GK_VOLCANIC_ISLANDS 1749 } GPU; 1750 1751 bool hasFP64:1; 1752 bool hasFMAF:1; 1753 bool hasLDEXPF:1; 1754 1755 public: 1756 AMDGPUTargetInfo(const llvm::Triple &Triple) 1757 : TargetInfo(Triple) { 1758 1759 if (Triple.getArch() == llvm::Triple::amdgcn) { 1760 DataLayoutString = DataLayoutStringSI; 1761 GPU = GK_SOUTHERN_ISLANDS; 1762 hasFP64 = true; 1763 hasFMAF = true; 1764 hasLDEXPF = true; 1765 } else { 1766 DataLayoutString = DataLayoutStringR600; 1767 GPU = GK_R600; 1768 hasFP64 = false; 1769 hasFMAF = false; 1770 hasLDEXPF = false; 1771 } 1772 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1773 UseAddrSpaceMapMangling = true; 1774 } 1775 1776 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1777 if (GPU <= GK_CAYMAN) 1778 return 32; 1779 1780 switch(AddrSpace) { 1781 default: 1782 return 64; 1783 case 0: 1784 case 3: 1785 case 5: 1786 return 32; 1787 } 1788 } 1789 1790 const char * getClobbers() const override { 1791 return ""; 1792 } 1793 1794 void getGCCRegNames(const char * const *&Names, 1795 unsigned &NumNames) const override; 1796 1797 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1798 unsigned &NumAliases) const override { 1799 Aliases = nullptr; 1800 NumAliases = 0; 1801 } 1802 1803 bool validateAsmConstraint(const char *&Name, 1804 TargetInfo::ConstraintInfo &info) const override { 1805 return true; 1806 } 1807 1808 void getTargetBuiltins(const Builtin::Info *&Records, 1809 unsigned &NumRecords) const override { 1810 Records = BuiltinInfo; 1811 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1812 } 1813 1814 void getTargetDefines(const LangOptions &Opts, 1815 MacroBuilder &Builder) const override { 1816 Builder.defineMacro("__R600__"); 1817 if (hasFMAF) 1818 Builder.defineMacro("__HAS_FMAF__"); 1819 if (hasLDEXPF) 1820 Builder.defineMacro("__HAS_LDEXPF__"); 1821 if (hasFP64 && Opts.OpenCL) 1822 Builder.defineMacro("cl_khr_fp64"); 1823 if (Opts.OpenCL) { 1824 if (GPU >= GK_NORTHERN_ISLANDS) { 1825 Builder.defineMacro("cl_khr_byte_addressable_store"); 1826 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1827 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1828 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1829 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1830 } 1831 } 1832 } 1833 1834 BuiltinVaListKind getBuiltinVaListKind() const override { 1835 return TargetInfo::CharPtrBuiltinVaList; 1836 } 1837 1838 bool setCPU(const std::string &Name) override { 1839 GPU = llvm::StringSwitch<GPUKind>(Name) 1840 .Case("r600" , GK_R600) 1841 .Case("rv610", GK_R600) 1842 .Case("rv620", GK_R600) 1843 .Case("rv630", GK_R600) 1844 .Case("rv635", GK_R600) 1845 .Case("rs780", GK_R600) 1846 .Case("rs880", GK_R600) 1847 .Case("rv670", GK_R600_DOUBLE_OPS) 1848 .Case("rv710", GK_R700) 1849 .Case("rv730", GK_R700) 1850 .Case("rv740", GK_R700_DOUBLE_OPS) 1851 .Case("rv770", GK_R700_DOUBLE_OPS) 1852 .Case("palm", GK_EVERGREEN) 1853 .Case("cedar", GK_EVERGREEN) 1854 .Case("sumo", GK_EVERGREEN) 1855 .Case("sumo2", GK_EVERGREEN) 1856 .Case("redwood", GK_EVERGREEN) 1857 .Case("juniper", GK_EVERGREEN) 1858 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1859 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1860 .Case("barts", GK_NORTHERN_ISLANDS) 1861 .Case("turks", GK_NORTHERN_ISLANDS) 1862 .Case("caicos", GK_NORTHERN_ISLANDS) 1863 .Case("cayman", GK_CAYMAN) 1864 .Case("aruba", GK_CAYMAN) 1865 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1866 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1867 .Case("verde", GK_SOUTHERN_ISLANDS) 1868 .Case("oland", GK_SOUTHERN_ISLANDS) 1869 .Case("hainan", GK_SOUTHERN_ISLANDS) 1870 .Case("bonaire", GK_SEA_ISLANDS) 1871 .Case("kabini", GK_SEA_ISLANDS) 1872 .Case("kaveri", GK_SEA_ISLANDS) 1873 .Case("hawaii", GK_SEA_ISLANDS) 1874 .Case("mullins", GK_SEA_ISLANDS) 1875 .Case("tonga", GK_VOLCANIC_ISLANDS) 1876 .Case("iceland", GK_VOLCANIC_ISLANDS) 1877 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1878 .Default(GK_NONE); 1879 1880 if (GPU == GK_NONE) { 1881 return false; 1882 } 1883 1884 // Set the correct data layout 1885 switch (GPU) { 1886 case GK_NONE: 1887 case GK_R600: 1888 case GK_R700: 1889 case GK_EVERGREEN: 1890 case GK_NORTHERN_ISLANDS: 1891 DataLayoutString = DataLayoutStringR600; 1892 hasFP64 = false; 1893 hasFMAF = false; 1894 hasLDEXPF = false; 1895 break; 1896 case GK_R600_DOUBLE_OPS: 1897 case GK_R700_DOUBLE_OPS: 1898 case GK_EVERGREEN_DOUBLE_OPS: 1899 case GK_CAYMAN: 1900 DataLayoutString = DataLayoutStringR600DoubleOps; 1901 hasFP64 = true; 1902 hasFMAF = true; 1903 hasLDEXPF = false; 1904 break; 1905 case GK_SOUTHERN_ISLANDS: 1906 case GK_SEA_ISLANDS: 1907 case GK_VOLCANIC_ISLANDS: 1908 DataLayoutString = DataLayoutStringSI; 1909 hasFP64 = true; 1910 hasFMAF = true; 1911 hasLDEXPF = true; 1912 break; 1913 } 1914 1915 return true; 1916 } 1917 }; 1918 1919 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1920 #define BUILTIN(ID, TYPE, ATTRS) \ 1921 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1922 #include "clang/Basic/BuiltinsAMDGPU.def" 1923 }; 1924 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1925 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1926 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1927 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1928 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1929 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1930 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1931 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1932 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1933 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1934 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1935 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1936 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1937 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1938 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1939 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1940 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1941 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1942 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1943 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1944 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1945 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1946 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1947 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1948 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1949 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1950 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1951 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1952 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1953 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1954 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1955 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1956 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1957 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1958 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1959 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1960 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1961 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1962 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1963 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1964 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1965 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1966 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1967 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1968 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1969 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1970 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1971 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1972 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1973 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1974 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1975 }; 1976 1977 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1978 unsigned &NumNames) const { 1979 Names = GCCRegNames; 1980 NumNames = llvm::array_lengthof(GCCRegNames); 1981 } 1982 1983 // Namespace for x86 abstract base class 1984 const Builtin::Info BuiltinInfo[] = { 1985 #define BUILTIN(ID, TYPE, ATTRS) \ 1986 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1987 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1988 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1989 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1990 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1991 #include "clang/Basic/BuiltinsX86.def" 1992 }; 1993 1994 static const char* const GCCRegNames[] = { 1995 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1996 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1997 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1998 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1999 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2000 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2001 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2002 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2003 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2004 }; 2005 2006 const TargetInfo::AddlRegName AddlRegNames[] = { 2007 { { "al", "ah", "eax", "rax" }, 0 }, 2008 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2009 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2010 { { "dl", "dh", "edx", "rdx" }, 1 }, 2011 { { "esi", "rsi" }, 4 }, 2012 { { "edi", "rdi" }, 5 }, 2013 { { "esp", "rsp" }, 7 }, 2014 { { "ebp", "rbp" }, 6 }, 2015 }; 2016 2017 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2018 // most of the implementation can be shared. 2019 class X86TargetInfo : public TargetInfo { 2020 enum X86SSEEnum { 2021 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2022 } SSELevel; 2023 enum MMX3DNowEnum { 2024 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2025 } MMX3DNowLevel; 2026 enum XOPEnum { 2027 NoXOP, 2028 SSE4A, 2029 FMA4, 2030 XOP 2031 } XOPLevel; 2032 2033 bool HasAES; 2034 bool HasPCLMUL; 2035 bool HasLZCNT; 2036 bool HasRDRND; 2037 bool HasFSGSBASE; 2038 bool HasBMI; 2039 bool HasBMI2; 2040 bool HasPOPCNT; 2041 bool HasRTM; 2042 bool HasPRFCHW; 2043 bool HasRDSEED; 2044 bool HasADX; 2045 bool HasTBM; 2046 bool HasFMA; 2047 bool HasF16C; 2048 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2049 HasAVX512VL; 2050 bool HasSHA; 2051 bool HasCX16; 2052 2053 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2054 /// 2055 /// Each enumeration represents a particular CPU supported by Clang. These 2056 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2057 enum CPUKind { 2058 CK_Generic, 2059 2060 /// \name i386 2061 /// i386-generation processors. 2062 //@{ 2063 CK_i386, 2064 //@} 2065 2066 /// \name i486 2067 /// i486-generation processors. 2068 //@{ 2069 CK_i486, 2070 CK_WinChipC6, 2071 CK_WinChip2, 2072 CK_C3, 2073 //@} 2074 2075 /// \name i586 2076 /// i586-generation processors, P5 microarchitecture based. 2077 //@{ 2078 CK_i586, 2079 CK_Pentium, 2080 CK_PentiumMMX, 2081 //@} 2082 2083 /// \name i686 2084 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2085 //@{ 2086 CK_i686, 2087 CK_PentiumPro, 2088 CK_Pentium2, 2089 CK_Pentium3, 2090 CK_Pentium3M, 2091 CK_PentiumM, 2092 CK_C3_2, 2093 2094 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2095 /// Clang however has some logic to suport this. 2096 // FIXME: Warn, deprecate, and potentially remove this. 2097 CK_Yonah, 2098 //@} 2099 2100 /// \name Netburst 2101 /// Netburst microarchitecture based processors. 2102 //@{ 2103 CK_Pentium4, 2104 CK_Pentium4M, 2105 CK_Prescott, 2106 CK_Nocona, 2107 //@} 2108 2109 /// \name Core 2110 /// Core microarchitecture based processors. 2111 //@{ 2112 CK_Core2, 2113 2114 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2115 /// codename which GCC no longer accepts as an option to -march, but Clang 2116 /// has some logic for recognizing it. 2117 // FIXME: Warn, deprecate, and potentially remove this. 2118 CK_Penryn, 2119 //@} 2120 2121 /// \name Atom 2122 /// Atom processors 2123 //@{ 2124 CK_Bonnell, 2125 CK_Silvermont, 2126 //@} 2127 2128 /// \name Nehalem 2129 /// Nehalem microarchitecture based processors. 2130 CK_Nehalem, 2131 2132 /// \name Westmere 2133 /// Westmere microarchitecture based processors. 2134 CK_Westmere, 2135 2136 /// \name Sandy Bridge 2137 /// Sandy Bridge microarchitecture based processors. 2138 CK_SandyBridge, 2139 2140 /// \name Ivy Bridge 2141 /// Ivy Bridge microarchitecture based processors. 2142 CK_IvyBridge, 2143 2144 /// \name Haswell 2145 /// Haswell microarchitecture based processors. 2146 CK_Haswell, 2147 2148 /// \name Broadwell 2149 /// Broadwell microarchitecture based processors. 2150 CK_Broadwell, 2151 2152 /// \name Skylake 2153 /// Skylake microarchitecture based processors. 2154 CK_Skylake, 2155 2156 /// \name Knights Landing 2157 /// Knights Landing processor. 2158 CK_KNL, 2159 2160 /// \name K6 2161 /// K6 architecture processors. 2162 //@{ 2163 CK_K6, 2164 CK_K6_2, 2165 CK_K6_3, 2166 //@} 2167 2168 /// \name K7 2169 /// K7 architecture processors. 2170 //@{ 2171 CK_Athlon, 2172 CK_AthlonThunderbird, 2173 CK_Athlon4, 2174 CK_AthlonXP, 2175 CK_AthlonMP, 2176 //@} 2177 2178 /// \name K8 2179 /// K8 architecture processors. 2180 //@{ 2181 CK_Athlon64, 2182 CK_Athlon64SSE3, 2183 CK_AthlonFX, 2184 CK_K8, 2185 CK_K8SSE3, 2186 CK_Opteron, 2187 CK_OpteronSSE3, 2188 CK_AMDFAM10, 2189 //@} 2190 2191 /// \name Bobcat 2192 /// Bobcat architecture processors. 2193 //@{ 2194 CK_BTVER1, 2195 CK_BTVER2, 2196 //@} 2197 2198 /// \name Bulldozer 2199 /// Bulldozer architecture processors. 2200 //@{ 2201 CK_BDVER1, 2202 CK_BDVER2, 2203 CK_BDVER3, 2204 CK_BDVER4, 2205 //@} 2206 2207 /// This specification is deprecated and will be removed in the future. 2208 /// Users should prefer \see CK_K8. 2209 // FIXME: Warn on this when the CPU is set to it. 2210 //@{ 2211 CK_x86_64, 2212 //@} 2213 2214 /// \name Geode 2215 /// Geode processors. 2216 //@{ 2217 CK_Geode 2218 //@} 2219 } CPU; 2220 2221 CPUKind getCPUKind(StringRef CPU) const { 2222 return llvm::StringSwitch<CPUKind>(CPU) 2223 .Case("i386", CK_i386) 2224 .Case("i486", CK_i486) 2225 .Case("winchip-c6", CK_WinChipC6) 2226 .Case("winchip2", CK_WinChip2) 2227 .Case("c3", CK_C3) 2228 .Case("i586", CK_i586) 2229 .Case("pentium", CK_Pentium) 2230 .Case("pentium-mmx", CK_PentiumMMX) 2231 .Case("i686", CK_i686) 2232 .Case("pentiumpro", CK_PentiumPro) 2233 .Case("pentium2", CK_Pentium2) 2234 .Case("pentium3", CK_Pentium3) 2235 .Case("pentium3m", CK_Pentium3M) 2236 .Case("pentium-m", CK_PentiumM) 2237 .Case("c3-2", CK_C3_2) 2238 .Case("yonah", CK_Yonah) 2239 .Case("pentium4", CK_Pentium4) 2240 .Case("pentium4m", CK_Pentium4M) 2241 .Case("prescott", CK_Prescott) 2242 .Case("nocona", CK_Nocona) 2243 .Case("core2", CK_Core2) 2244 .Case("penryn", CK_Penryn) 2245 .Case("bonnell", CK_Bonnell) 2246 .Case("atom", CK_Bonnell) // Legacy name. 2247 .Case("silvermont", CK_Silvermont) 2248 .Case("slm", CK_Silvermont) // Legacy name. 2249 .Case("nehalem", CK_Nehalem) 2250 .Case("corei7", CK_Nehalem) // Legacy name. 2251 .Case("westmere", CK_Westmere) 2252 .Case("sandybridge", CK_SandyBridge) 2253 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2254 .Case("ivybridge", CK_IvyBridge) 2255 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2256 .Case("haswell", CK_Haswell) 2257 .Case("core-avx2", CK_Haswell) // Legacy name. 2258 .Case("broadwell", CK_Broadwell) 2259 .Case("skylake", CK_Skylake) 2260 .Case("skx", CK_Skylake) // Legacy name. 2261 .Case("knl", CK_KNL) 2262 .Case("k6", CK_K6) 2263 .Case("k6-2", CK_K6_2) 2264 .Case("k6-3", CK_K6_3) 2265 .Case("athlon", CK_Athlon) 2266 .Case("athlon-tbird", CK_AthlonThunderbird) 2267 .Case("athlon-4", CK_Athlon4) 2268 .Case("athlon-xp", CK_AthlonXP) 2269 .Case("athlon-mp", CK_AthlonMP) 2270 .Case("athlon64", CK_Athlon64) 2271 .Case("athlon64-sse3", CK_Athlon64SSE3) 2272 .Case("athlon-fx", CK_AthlonFX) 2273 .Case("k8", CK_K8) 2274 .Case("k8-sse3", CK_K8SSE3) 2275 .Case("opteron", CK_Opteron) 2276 .Case("opteron-sse3", CK_OpteronSSE3) 2277 .Case("barcelona", CK_AMDFAM10) 2278 .Case("amdfam10", CK_AMDFAM10) 2279 .Case("btver1", CK_BTVER1) 2280 .Case("btver2", CK_BTVER2) 2281 .Case("bdver1", CK_BDVER1) 2282 .Case("bdver2", CK_BDVER2) 2283 .Case("bdver3", CK_BDVER3) 2284 .Case("bdver4", CK_BDVER4) 2285 .Case("x86-64", CK_x86_64) 2286 .Case("geode", CK_Geode) 2287 .Default(CK_Generic); 2288 } 2289 2290 enum FPMathKind { 2291 FP_Default, 2292 FP_SSE, 2293 FP_387 2294 } FPMath; 2295 2296 public: 2297 X86TargetInfo(const llvm::Triple &Triple) 2298 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2299 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2300 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2301 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2302 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2303 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2304 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2305 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2306 BigEndian = false; 2307 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2308 } 2309 unsigned getFloatEvalMethod() const override { 2310 // X87 evaluates with 80 bits "long double" precision. 2311 return SSELevel == NoSSE ? 2 : 0; 2312 } 2313 void getTargetBuiltins(const Builtin::Info *&Records, 2314 unsigned &NumRecords) const override { 2315 Records = BuiltinInfo; 2316 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2317 } 2318 void getGCCRegNames(const char * const *&Names, 2319 unsigned &NumNames) const override { 2320 Names = GCCRegNames; 2321 NumNames = llvm::array_lengthof(GCCRegNames); 2322 } 2323 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2324 unsigned &NumAliases) const override { 2325 Aliases = nullptr; 2326 NumAliases = 0; 2327 } 2328 void getGCCAddlRegNames(const AddlRegName *&Names, 2329 unsigned &NumNames) const override { 2330 Names = AddlRegNames; 2331 NumNames = llvm::array_lengthof(AddlRegNames); 2332 } 2333 bool validateCpuSupports(StringRef Name) const override; 2334 bool validateAsmConstraint(const char *&Name, 2335 TargetInfo::ConstraintInfo &info) const override; 2336 2337 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2338 2339 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2340 2341 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2342 2343 std::string convertConstraint(const char *&Constraint) const override; 2344 const char *getClobbers() const override { 2345 return "~{dirflag},~{fpsr},~{flags}"; 2346 } 2347 void getTargetDefines(const LangOptions &Opts, 2348 MacroBuilder &Builder) const override; 2349 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2350 bool Enabled); 2351 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2352 bool Enabled); 2353 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2354 bool Enabled); 2355 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2356 StringRef Name, bool Enabled) const override { 2357 setFeatureEnabledImpl(Features, Name, Enabled); 2358 } 2359 // This exists purely to cut down on the number of virtual calls in 2360 // initFeatureMap which calls this repeatedly. 2361 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2362 StringRef Name, bool Enabled); 2363 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2364 StringRef CPU, 2365 std::vector<std::string> &FeaturesVec) const override; 2366 bool hasFeature(StringRef Feature) const override; 2367 bool handleTargetFeatures(std::vector<std::string> &Features, 2368 DiagnosticsEngine &Diags) override; 2369 StringRef getABI() const override { 2370 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2371 return "avx512"; 2372 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2373 return "avx"; 2374 else if (getTriple().getArch() == llvm::Triple::x86 && 2375 MMX3DNowLevel == NoMMX3DNow) 2376 return "no-mmx"; 2377 return ""; 2378 } 2379 bool setCPU(const std::string &Name) override { 2380 CPU = getCPUKind(Name); 2381 2382 // Perform any per-CPU checks necessary to determine if this CPU is 2383 // acceptable. 2384 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2385 // invalid without explaining *why*. 2386 switch (CPU) { 2387 case CK_Generic: 2388 // No processor selected! 2389 return false; 2390 2391 case CK_i386: 2392 case CK_i486: 2393 case CK_WinChipC6: 2394 case CK_WinChip2: 2395 case CK_C3: 2396 case CK_i586: 2397 case CK_Pentium: 2398 case CK_PentiumMMX: 2399 case CK_i686: 2400 case CK_PentiumPro: 2401 case CK_Pentium2: 2402 case CK_Pentium3: 2403 case CK_Pentium3M: 2404 case CK_PentiumM: 2405 case CK_Yonah: 2406 case CK_C3_2: 2407 case CK_Pentium4: 2408 case CK_Pentium4M: 2409 case CK_Prescott: 2410 case CK_K6: 2411 case CK_K6_2: 2412 case CK_K6_3: 2413 case CK_Athlon: 2414 case CK_AthlonThunderbird: 2415 case CK_Athlon4: 2416 case CK_AthlonXP: 2417 case CK_AthlonMP: 2418 case CK_Geode: 2419 // Only accept certain architectures when compiling in 32-bit mode. 2420 if (getTriple().getArch() != llvm::Triple::x86) 2421 return false; 2422 2423 // Fallthrough 2424 case CK_Nocona: 2425 case CK_Core2: 2426 case CK_Penryn: 2427 case CK_Bonnell: 2428 case CK_Silvermont: 2429 case CK_Nehalem: 2430 case CK_Westmere: 2431 case CK_SandyBridge: 2432 case CK_IvyBridge: 2433 case CK_Haswell: 2434 case CK_Broadwell: 2435 case CK_Skylake: 2436 case CK_KNL: 2437 case CK_Athlon64: 2438 case CK_Athlon64SSE3: 2439 case CK_AthlonFX: 2440 case CK_K8: 2441 case CK_K8SSE3: 2442 case CK_Opteron: 2443 case CK_OpteronSSE3: 2444 case CK_AMDFAM10: 2445 case CK_BTVER1: 2446 case CK_BTVER2: 2447 case CK_BDVER1: 2448 case CK_BDVER2: 2449 case CK_BDVER3: 2450 case CK_BDVER4: 2451 case CK_x86_64: 2452 return true; 2453 } 2454 llvm_unreachable("Unhandled CPU kind"); 2455 } 2456 2457 bool setFPMath(StringRef Name) override; 2458 2459 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2460 // We accept all non-ARM calling conventions 2461 return (CC == CC_X86ThisCall || 2462 CC == CC_X86FastCall || 2463 CC == CC_X86StdCall || 2464 CC == CC_X86VectorCall || 2465 CC == CC_C || 2466 CC == CC_X86Pascal || 2467 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2468 } 2469 2470 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2471 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2472 } 2473 2474 bool hasSjLjLowering() const override { 2475 return true; 2476 } 2477 }; 2478 2479 bool X86TargetInfo::setFPMath(StringRef Name) { 2480 if (Name == "387") { 2481 FPMath = FP_387; 2482 return true; 2483 } 2484 if (Name == "sse") { 2485 FPMath = FP_SSE; 2486 return true; 2487 } 2488 return false; 2489 } 2490 2491 bool X86TargetInfo::initFeatureMap( 2492 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2493 std::vector<std::string> &FeaturesVec) const { 2494 // FIXME: This *really* should not be here. 2495 2496 // X86_64 always has SSE2. 2497 if (getTriple().getArch() == llvm::Triple::x86_64) 2498 setFeatureEnabledImpl(Features, "sse2", true); 2499 2500 switch (getCPUKind(CPU)) { 2501 case CK_Generic: 2502 case CK_i386: 2503 case CK_i486: 2504 case CK_i586: 2505 case CK_Pentium: 2506 case CK_i686: 2507 case CK_PentiumPro: 2508 break; 2509 case CK_PentiumMMX: 2510 case CK_Pentium2: 2511 case CK_K6: 2512 case CK_WinChipC6: 2513 setFeatureEnabledImpl(Features, "mmx", true); 2514 break; 2515 case CK_Pentium3: 2516 case CK_Pentium3M: 2517 case CK_C3_2: 2518 setFeatureEnabledImpl(Features, "sse", true); 2519 break; 2520 case CK_PentiumM: 2521 case CK_Pentium4: 2522 case CK_Pentium4M: 2523 case CK_x86_64: 2524 setFeatureEnabledImpl(Features, "sse2", true); 2525 break; 2526 case CK_Yonah: 2527 case CK_Prescott: 2528 case CK_Nocona: 2529 setFeatureEnabledImpl(Features, "sse3", true); 2530 setFeatureEnabledImpl(Features, "cx16", true); 2531 break; 2532 case CK_Core2: 2533 case CK_Bonnell: 2534 setFeatureEnabledImpl(Features, "ssse3", true); 2535 setFeatureEnabledImpl(Features, "cx16", true); 2536 break; 2537 case CK_Penryn: 2538 setFeatureEnabledImpl(Features, "sse4.1", true); 2539 setFeatureEnabledImpl(Features, "cx16", true); 2540 break; 2541 case CK_Skylake: 2542 setFeatureEnabledImpl(Features, "avx512f", true); 2543 setFeatureEnabledImpl(Features, "avx512cd", true); 2544 setFeatureEnabledImpl(Features, "avx512dq", true); 2545 setFeatureEnabledImpl(Features, "avx512bw", true); 2546 setFeatureEnabledImpl(Features, "avx512vl", true); 2547 // FALLTHROUGH 2548 case CK_Broadwell: 2549 setFeatureEnabledImpl(Features, "rdseed", true); 2550 setFeatureEnabledImpl(Features, "adx", true); 2551 // FALLTHROUGH 2552 case CK_Haswell: 2553 setFeatureEnabledImpl(Features, "avx2", true); 2554 setFeatureEnabledImpl(Features, "lzcnt", true); 2555 setFeatureEnabledImpl(Features, "bmi", true); 2556 setFeatureEnabledImpl(Features, "bmi2", true); 2557 setFeatureEnabledImpl(Features, "rtm", true); 2558 setFeatureEnabledImpl(Features, "fma", true); 2559 // FALLTHROUGH 2560 case CK_IvyBridge: 2561 setFeatureEnabledImpl(Features, "rdrnd", true); 2562 setFeatureEnabledImpl(Features, "f16c", true); 2563 setFeatureEnabledImpl(Features, "fsgsbase", true); 2564 // FALLTHROUGH 2565 case CK_SandyBridge: 2566 setFeatureEnabledImpl(Features, "avx", true); 2567 // FALLTHROUGH 2568 case CK_Westmere: 2569 case CK_Silvermont: 2570 setFeatureEnabledImpl(Features, "aes", true); 2571 setFeatureEnabledImpl(Features, "pclmul", true); 2572 // FALLTHROUGH 2573 case CK_Nehalem: 2574 setFeatureEnabledImpl(Features, "sse4.2", true); 2575 setFeatureEnabledImpl(Features, "cx16", true); 2576 break; 2577 case CK_KNL: 2578 setFeatureEnabledImpl(Features, "avx512f", true); 2579 setFeatureEnabledImpl(Features, "avx512cd", true); 2580 setFeatureEnabledImpl(Features, "avx512er", true); 2581 setFeatureEnabledImpl(Features, "avx512pf", true); 2582 setFeatureEnabledImpl(Features, "rdseed", true); 2583 setFeatureEnabledImpl(Features, "adx", true); 2584 setFeatureEnabledImpl(Features, "lzcnt", true); 2585 setFeatureEnabledImpl(Features, "bmi", true); 2586 setFeatureEnabledImpl(Features, "bmi2", true); 2587 setFeatureEnabledImpl(Features, "rtm", true); 2588 setFeatureEnabledImpl(Features, "fma", true); 2589 setFeatureEnabledImpl(Features, "rdrnd", true); 2590 setFeatureEnabledImpl(Features, "f16c", true); 2591 setFeatureEnabledImpl(Features, "fsgsbase", true); 2592 setFeatureEnabledImpl(Features, "aes", true); 2593 setFeatureEnabledImpl(Features, "pclmul", true); 2594 setFeatureEnabledImpl(Features, "cx16", true); 2595 break; 2596 case CK_K6_2: 2597 case CK_K6_3: 2598 case CK_WinChip2: 2599 case CK_C3: 2600 setFeatureEnabledImpl(Features, "3dnow", true); 2601 break; 2602 case CK_Athlon: 2603 case CK_AthlonThunderbird: 2604 case CK_Geode: 2605 setFeatureEnabledImpl(Features, "3dnowa", true); 2606 break; 2607 case CK_Athlon4: 2608 case CK_AthlonXP: 2609 case CK_AthlonMP: 2610 setFeatureEnabledImpl(Features, "sse", true); 2611 setFeatureEnabledImpl(Features, "3dnowa", true); 2612 break; 2613 case CK_K8: 2614 case CK_Opteron: 2615 case CK_Athlon64: 2616 case CK_AthlonFX: 2617 setFeatureEnabledImpl(Features, "sse2", true); 2618 setFeatureEnabledImpl(Features, "3dnowa", true); 2619 break; 2620 case CK_AMDFAM10: 2621 setFeatureEnabledImpl(Features, "sse4a", true); 2622 setFeatureEnabledImpl(Features, "lzcnt", true); 2623 setFeatureEnabledImpl(Features, "popcnt", true); 2624 // FALLTHROUGH 2625 case CK_K8SSE3: 2626 case CK_OpteronSSE3: 2627 case CK_Athlon64SSE3: 2628 setFeatureEnabledImpl(Features, "sse3", true); 2629 setFeatureEnabledImpl(Features, "3dnowa", true); 2630 break; 2631 case CK_BTVER2: 2632 setFeatureEnabledImpl(Features, "avx", true); 2633 setFeatureEnabledImpl(Features, "aes", true); 2634 setFeatureEnabledImpl(Features, "pclmul", true); 2635 setFeatureEnabledImpl(Features, "bmi", true); 2636 setFeatureEnabledImpl(Features, "f16c", true); 2637 // FALLTHROUGH 2638 case CK_BTVER1: 2639 setFeatureEnabledImpl(Features, "ssse3", true); 2640 setFeatureEnabledImpl(Features, "sse4a", true); 2641 setFeatureEnabledImpl(Features, "lzcnt", true); 2642 setFeatureEnabledImpl(Features, "popcnt", true); 2643 setFeatureEnabledImpl(Features, "prfchw", true); 2644 setFeatureEnabledImpl(Features, "cx16", true); 2645 break; 2646 case CK_BDVER4: 2647 setFeatureEnabledImpl(Features, "avx2", true); 2648 setFeatureEnabledImpl(Features, "bmi2", true); 2649 // FALLTHROUGH 2650 case CK_BDVER3: 2651 setFeatureEnabledImpl(Features, "fsgsbase", true); 2652 // FALLTHROUGH 2653 case CK_BDVER2: 2654 setFeatureEnabledImpl(Features, "bmi", true); 2655 setFeatureEnabledImpl(Features, "fma", true); 2656 setFeatureEnabledImpl(Features, "f16c", true); 2657 setFeatureEnabledImpl(Features, "tbm", true); 2658 // FALLTHROUGH 2659 case CK_BDVER1: 2660 // xop implies avx, sse4a and fma4. 2661 setFeatureEnabledImpl(Features, "xop", true); 2662 setFeatureEnabledImpl(Features, "lzcnt", true); 2663 setFeatureEnabledImpl(Features, "aes", true); 2664 setFeatureEnabledImpl(Features, "pclmul", true); 2665 setFeatureEnabledImpl(Features, "prfchw", true); 2666 setFeatureEnabledImpl(Features, "cx16", true); 2667 break; 2668 } 2669 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 2670 } 2671 2672 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2673 X86SSEEnum Level, bool Enabled) { 2674 if (Enabled) { 2675 switch (Level) { 2676 case AVX512F: 2677 Features["avx512f"] = true; 2678 case AVX2: 2679 Features["avx2"] = true; 2680 case AVX: 2681 Features["avx"] = true; 2682 case SSE42: 2683 Features["sse4.2"] = true; 2684 case SSE41: 2685 Features["sse4.1"] = true; 2686 case SSSE3: 2687 Features["ssse3"] = true; 2688 case SSE3: 2689 Features["sse3"] = true; 2690 case SSE2: 2691 Features["sse2"] = true; 2692 case SSE1: 2693 Features["sse"] = true; 2694 case NoSSE: 2695 break; 2696 } 2697 return; 2698 } 2699 2700 switch (Level) { 2701 case NoSSE: 2702 case SSE1: 2703 Features["sse"] = false; 2704 case SSE2: 2705 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2706 Features["sha"] = false; 2707 case SSE3: 2708 Features["sse3"] = false; 2709 setXOPLevel(Features, NoXOP, false); 2710 case SSSE3: 2711 Features["ssse3"] = false; 2712 case SSE41: 2713 Features["sse4.1"] = false; 2714 case SSE42: 2715 Features["sse4.2"] = false; 2716 case AVX: 2717 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2718 setXOPLevel(Features, FMA4, false); 2719 case AVX2: 2720 Features["avx2"] = false; 2721 case AVX512F: 2722 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2723 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2724 Features["avx512vl"] = false; 2725 } 2726 } 2727 2728 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2729 MMX3DNowEnum Level, bool Enabled) { 2730 if (Enabled) { 2731 switch (Level) { 2732 case AMD3DNowAthlon: 2733 Features["3dnowa"] = true; 2734 case AMD3DNow: 2735 Features["3dnow"] = true; 2736 case MMX: 2737 Features["mmx"] = true; 2738 case NoMMX3DNow: 2739 break; 2740 } 2741 return; 2742 } 2743 2744 switch (Level) { 2745 case NoMMX3DNow: 2746 case MMX: 2747 Features["mmx"] = false; 2748 case AMD3DNow: 2749 Features["3dnow"] = false; 2750 case AMD3DNowAthlon: 2751 Features["3dnowa"] = false; 2752 } 2753 } 2754 2755 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2756 bool Enabled) { 2757 if (Enabled) { 2758 switch (Level) { 2759 case XOP: 2760 Features["xop"] = true; 2761 case FMA4: 2762 Features["fma4"] = true; 2763 setSSELevel(Features, AVX, true); 2764 case SSE4A: 2765 Features["sse4a"] = true; 2766 setSSELevel(Features, SSE3, true); 2767 case NoXOP: 2768 break; 2769 } 2770 return; 2771 } 2772 2773 switch (Level) { 2774 case NoXOP: 2775 case SSE4A: 2776 Features["sse4a"] = false; 2777 case FMA4: 2778 Features["fma4"] = false; 2779 case XOP: 2780 Features["xop"] = false; 2781 } 2782 } 2783 2784 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2785 StringRef Name, bool Enabled) { 2786 // This is a bit of a hack to deal with the sse4 target feature when used 2787 // as part of the target attribute. We handle sse4 correctly everywhere 2788 // else. See below for more information on how we handle the sse4 options. 2789 if (Name != "sse4") 2790 Features[Name] = Enabled; 2791 2792 if (Name == "mmx") { 2793 setMMXLevel(Features, MMX, Enabled); 2794 } else if (Name == "sse") { 2795 setSSELevel(Features, SSE1, Enabled); 2796 } else if (Name == "sse2") { 2797 setSSELevel(Features, SSE2, Enabled); 2798 } else if (Name == "sse3") { 2799 setSSELevel(Features, SSE3, Enabled); 2800 } else if (Name == "ssse3") { 2801 setSSELevel(Features, SSSE3, Enabled); 2802 } else if (Name == "sse4.2") { 2803 setSSELevel(Features, SSE42, Enabled); 2804 } else if (Name == "sse4.1") { 2805 setSSELevel(Features, SSE41, Enabled); 2806 } else if (Name == "3dnow") { 2807 setMMXLevel(Features, AMD3DNow, Enabled); 2808 } else if (Name == "3dnowa") { 2809 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2810 } else if (Name == "aes") { 2811 if (Enabled) 2812 setSSELevel(Features, SSE2, Enabled); 2813 } else if (Name == "pclmul") { 2814 if (Enabled) 2815 setSSELevel(Features, SSE2, Enabled); 2816 } else if (Name == "avx") { 2817 setSSELevel(Features, AVX, Enabled); 2818 } else if (Name == "avx2") { 2819 setSSELevel(Features, AVX2, Enabled); 2820 } else if (Name == "avx512f") { 2821 setSSELevel(Features, AVX512F, Enabled); 2822 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2823 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2824 if (Enabled) 2825 setSSELevel(Features, AVX512F, Enabled); 2826 } else if (Name == "fma") { 2827 if (Enabled) 2828 setSSELevel(Features, AVX, Enabled); 2829 } else if (Name == "fma4") { 2830 setXOPLevel(Features, FMA4, Enabled); 2831 } else if (Name == "xop") { 2832 setXOPLevel(Features, XOP, Enabled); 2833 } else if (Name == "sse4a") { 2834 setXOPLevel(Features, SSE4A, Enabled); 2835 } else if (Name == "f16c") { 2836 if (Enabled) 2837 setSSELevel(Features, AVX, Enabled); 2838 } else if (Name == "sha") { 2839 if (Enabled) 2840 setSSELevel(Features, SSE2, Enabled); 2841 } else if (Name == "sse4") { 2842 // We can get here via the __target__ attribute since that's not controlled 2843 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2844 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2845 // disabled. 2846 if (Enabled) 2847 setSSELevel(Features, SSE42, Enabled); 2848 else 2849 setSSELevel(Features, SSE41, Enabled); 2850 } 2851 } 2852 2853 /// handleTargetFeatures - Perform initialization based on the user 2854 /// configured set of features. 2855 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2856 DiagnosticsEngine &Diags) { 2857 for (const auto &Feature : Features) { 2858 if (Feature[0] != '+') 2859 continue; 2860 2861 if (Feature == "+aes") { 2862 HasAES = true; 2863 } else if (Feature == "+pclmul") { 2864 HasPCLMUL = true; 2865 } else if (Feature == "+lzcnt") { 2866 HasLZCNT = true; 2867 } else if (Feature == "+rdrnd") { 2868 HasRDRND = true; 2869 } else if (Feature == "+fsgsbase") { 2870 HasFSGSBASE = true; 2871 } else if (Feature == "+bmi") { 2872 HasBMI = true; 2873 } else if (Feature == "+bmi2") { 2874 HasBMI2 = true; 2875 } else if (Feature == "+popcnt") { 2876 HasPOPCNT = true; 2877 } else if (Feature == "+rtm") { 2878 HasRTM = true; 2879 } else if (Feature == "+prfchw") { 2880 HasPRFCHW = true; 2881 } else if (Feature == "+rdseed") { 2882 HasRDSEED = true; 2883 } else if (Feature == "+adx") { 2884 HasADX = true; 2885 } else if (Feature == "+tbm") { 2886 HasTBM = true; 2887 } else if (Feature == "+fma") { 2888 HasFMA = true; 2889 } else if (Feature == "+f16c") { 2890 HasF16C = true; 2891 } else if (Feature == "+avx512cd") { 2892 HasAVX512CD = true; 2893 } else if (Feature == "+avx512er") { 2894 HasAVX512ER = true; 2895 } else if (Feature == "+avx512pf") { 2896 HasAVX512PF = true; 2897 } else if (Feature == "+avx512dq") { 2898 HasAVX512DQ = true; 2899 } else if (Feature == "+avx512bw") { 2900 HasAVX512BW = true; 2901 } else if (Feature == "+avx512vl") { 2902 HasAVX512VL = true; 2903 } else if (Feature == "+sha") { 2904 HasSHA = true; 2905 } else if (Feature == "+cx16") { 2906 HasCX16 = true; 2907 } 2908 2909 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2910 .Case("+avx512f", AVX512F) 2911 .Case("+avx2", AVX2) 2912 .Case("+avx", AVX) 2913 .Case("+sse4.2", SSE42) 2914 .Case("+sse4.1", SSE41) 2915 .Case("+ssse3", SSSE3) 2916 .Case("+sse3", SSE3) 2917 .Case("+sse2", SSE2) 2918 .Case("+sse", SSE1) 2919 .Default(NoSSE); 2920 SSELevel = std::max(SSELevel, Level); 2921 2922 MMX3DNowEnum ThreeDNowLevel = 2923 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2924 .Case("+3dnowa", AMD3DNowAthlon) 2925 .Case("+3dnow", AMD3DNow) 2926 .Case("+mmx", MMX) 2927 .Default(NoMMX3DNow); 2928 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2929 2930 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2931 .Case("+xop", XOP) 2932 .Case("+fma4", FMA4) 2933 .Case("+sse4a", SSE4A) 2934 .Default(NoXOP); 2935 XOPLevel = std::max(XOPLevel, XLevel); 2936 } 2937 2938 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2939 // Can't do this earlier because we need to be able to explicitly enable 2940 // popcnt and still disable sse4.2. 2941 if (!HasPOPCNT && SSELevel >= SSE42 && 2942 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2943 HasPOPCNT = true; 2944 Features.push_back("+popcnt"); 2945 } 2946 2947 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2948 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2949 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2950 HasPRFCHW = true; 2951 Features.push_back("+prfchw"); 2952 } 2953 2954 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2955 // matches the selected sse level. 2956 if (FPMath == FP_SSE && SSELevel < SSE1) { 2957 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2958 return false; 2959 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2960 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2961 return false; 2962 } 2963 2964 // Don't tell the backend if we're turning off mmx; it will end up disabling 2965 // SSE, which we don't want. 2966 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2967 // then enable MMX. 2968 std::vector<std::string>::iterator it; 2969 it = std::find(Features.begin(), Features.end(), "-mmx"); 2970 if (it != Features.end()) 2971 Features.erase(it); 2972 else if (SSELevel > NoSSE) 2973 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2974 2975 SimdDefaultAlign = 2976 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 2977 return true; 2978 } 2979 2980 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2981 /// definitions for this particular subtarget. 2982 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2983 MacroBuilder &Builder) const { 2984 // Target identification. 2985 if (getTriple().getArch() == llvm::Triple::x86_64) { 2986 Builder.defineMacro("__amd64__"); 2987 Builder.defineMacro("__amd64"); 2988 Builder.defineMacro("__x86_64"); 2989 Builder.defineMacro("__x86_64__"); 2990 if (getTriple().getArchName() == "x86_64h") { 2991 Builder.defineMacro("__x86_64h"); 2992 Builder.defineMacro("__x86_64h__"); 2993 } 2994 } else { 2995 DefineStd(Builder, "i386", Opts); 2996 } 2997 2998 // Subtarget options. 2999 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3000 // truly should be based on -mtune options. 3001 switch (CPU) { 3002 case CK_Generic: 3003 break; 3004 case CK_i386: 3005 // The rest are coming from the i386 define above. 3006 Builder.defineMacro("__tune_i386__"); 3007 break; 3008 case CK_i486: 3009 case CK_WinChipC6: 3010 case CK_WinChip2: 3011 case CK_C3: 3012 defineCPUMacros(Builder, "i486"); 3013 break; 3014 case CK_PentiumMMX: 3015 Builder.defineMacro("__pentium_mmx__"); 3016 Builder.defineMacro("__tune_pentium_mmx__"); 3017 // Fallthrough 3018 case CK_i586: 3019 case CK_Pentium: 3020 defineCPUMacros(Builder, "i586"); 3021 defineCPUMacros(Builder, "pentium"); 3022 break; 3023 case CK_Pentium3: 3024 case CK_Pentium3M: 3025 case CK_PentiumM: 3026 Builder.defineMacro("__tune_pentium3__"); 3027 // Fallthrough 3028 case CK_Pentium2: 3029 case CK_C3_2: 3030 Builder.defineMacro("__tune_pentium2__"); 3031 // Fallthrough 3032 case CK_PentiumPro: 3033 Builder.defineMacro("__tune_i686__"); 3034 Builder.defineMacro("__tune_pentiumpro__"); 3035 // Fallthrough 3036 case CK_i686: 3037 Builder.defineMacro("__i686"); 3038 Builder.defineMacro("__i686__"); 3039 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3040 Builder.defineMacro("__pentiumpro"); 3041 Builder.defineMacro("__pentiumpro__"); 3042 break; 3043 case CK_Pentium4: 3044 case CK_Pentium4M: 3045 defineCPUMacros(Builder, "pentium4"); 3046 break; 3047 case CK_Yonah: 3048 case CK_Prescott: 3049 case CK_Nocona: 3050 defineCPUMacros(Builder, "nocona"); 3051 break; 3052 case CK_Core2: 3053 case CK_Penryn: 3054 defineCPUMacros(Builder, "core2"); 3055 break; 3056 case CK_Bonnell: 3057 defineCPUMacros(Builder, "atom"); 3058 break; 3059 case CK_Silvermont: 3060 defineCPUMacros(Builder, "slm"); 3061 break; 3062 case CK_Nehalem: 3063 case CK_Westmere: 3064 case CK_SandyBridge: 3065 case CK_IvyBridge: 3066 case CK_Haswell: 3067 case CK_Broadwell: 3068 // FIXME: Historically, we defined this legacy name, it would be nice to 3069 // remove it at some point. We've never exposed fine-grained names for 3070 // recent primary x86 CPUs, and we should keep it that way. 3071 defineCPUMacros(Builder, "corei7"); 3072 break; 3073 case CK_Skylake: 3074 // FIXME: Historically, we defined this legacy name, it would be nice to 3075 // remove it at some point. This is the only fine-grained CPU macro in the 3076 // main intel CPU line, and it would be better to not have these and force 3077 // people to use ISA macros. 3078 defineCPUMacros(Builder, "skx"); 3079 break; 3080 case CK_KNL: 3081 defineCPUMacros(Builder, "knl"); 3082 break; 3083 case CK_K6_2: 3084 Builder.defineMacro("__k6_2__"); 3085 Builder.defineMacro("__tune_k6_2__"); 3086 // Fallthrough 3087 case CK_K6_3: 3088 if (CPU != CK_K6_2) { // In case of fallthrough 3089 // FIXME: GCC may be enabling these in cases where some other k6 3090 // architecture is specified but -m3dnow is explicitly provided. The 3091 // exact semantics need to be determined and emulated here. 3092 Builder.defineMacro("__k6_3__"); 3093 Builder.defineMacro("__tune_k6_3__"); 3094 } 3095 // Fallthrough 3096 case CK_K6: 3097 defineCPUMacros(Builder, "k6"); 3098 break; 3099 case CK_Athlon: 3100 case CK_AthlonThunderbird: 3101 case CK_Athlon4: 3102 case CK_AthlonXP: 3103 case CK_AthlonMP: 3104 defineCPUMacros(Builder, "athlon"); 3105 if (SSELevel != NoSSE) { 3106 Builder.defineMacro("__athlon_sse__"); 3107 Builder.defineMacro("__tune_athlon_sse__"); 3108 } 3109 break; 3110 case CK_K8: 3111 case CK_K8SSE3: 3112 case CK_x86_64: 3113 case CK_Opteron: 3114 case CK_OpteronSSE3: 3115 case CK_Athlon64: 3116 case CK_Athlon64SSE3: 3117 case CK_AthlonFX: 3118 defineCPUMacros(Builder, "k8"); 3119 break; 3120 case CK_AMDFAM10: 3121 defineCPUMacros(Builder, "amdfam10"); 3122 break; 3123 case CK_BTVER1: 3124 defineCPUMacros(Builder, "btver1"); 3125 break; 3126 case CK_BTVER2: 3127 defineCPUMacros(Builder, "btver2"); 3128 break; 3129 case CK_BDVER1: 3130 defineCPUMacros(Builder, "bdver1"); 3131 break; 3132 case CK_BDVER2: 3133 defineCPUMacros(Builder, "bdver2"); 3134 break; 3135 case CK_BDVER3: 3136 defineCPUMacros(Builder, "bdver3"); 3137 break; 3138 case CK_BDVER4: 3139 defineCPUMacros(Builder, "bdver4"); 3140 break; 3141 case CK_Geode: 3142 defineCPUMacros(Builder, "geode"); 3143 break; 3144 } 3145 3146 // Target properties. 3147 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3148 3149 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3150 // functions in glibc header files that use FP Stack inline asm which the 3151 // backend can't deal with (PR879). 3152 Builder.defineMacro("__NO_MATH_INLINES"); 3153 3154 if (HasAES) 3155 Builder.defineMacro("__AES__"); 3156 3157 if (HasPCLMUL) 3158 Builder.defineMacro("__PCLMUL__"); 3159 3160 if (HasLZCNT) 3161 Builder.defineMacro("__LZCNT__"); 3162 3163 if (HasRDRND) 3164 Builder.defineMacro("__RDRND__"); 3165 3166 if (HasFSGSBASE) 3167 Builder.defineMacro("__FSGSBASE__"); 3168 3169 if (HasBMI) 3170 Builder.defineMacro("__BMI__"); 3171 3172 if (HasBMI2) 3173 Builder.defineMacro("__BMI2__"); 3174 3175 if (HasPOPCNT) 3176 Builder.defineMacro("__POPCNT__"); 3177 3178 if (HasRTM) 3179 Builder.defineMacro("__RTM__"); 3180 3181 if (HasPRFCHW) 3182 Builder.defineMacro("__PRFCHW__"); 3183 3184 if (HasRDSEED) 3185 Builder.defineMacro("__RDSEED__"); 3186 3187 if (HasADX) 3188 Builder.defineMacro("__ADX__"); 3189 3190 if (HasTBM) 3191 Builder.defineMacro("__TBM__"); 3192 3193 switch (XOPLevel) { 3194 case XOP: 3195 Builder.defineMacro("__XOP__"); 3196 case FMA4: 3197 Builder.defineMacro("__FMA4__"); 3198 case SSE4A: 3199 Builder.defineMacro("__SSE4A__"); 3200 case NoXOP: 3201 break; 3202 } 3203 3204 if (HasFMA) 3205 Builder.defineMacro("__FMA__"); 3206 3207 if (HasF16C) 3208 Builder.defineMacro("__F16C__"); 3209 3210 if (HasAVX512CD) 3211 Builder.defineMacro("__AVX512CD__"); 3212 if (HasAVX512ER) 3213 Builder.defineMacro("__AVX512ER__"); 3214 if (HasAVX512PF) 3215 Builder.defineMacro("__AVX512PF__"); 3216 if (HasAVX512DQ) 3217 Builder.defineMacro("__AVX512DQ__"); 3218 if (HasAVX512BW) 3219 Builder.defineMacro("__AVX512BW__"); 3220 if (HasAVX512VL) 3221 Builder.defineMacro("__AVX512VL__"); 3222 3223 if (HasSHA) 3224 Builder.defineMacro("__SHA__"); 3225 3226 if (HasCX16) 3227 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3228 3229 // Each case falls through to the previous one here. 3230 switch (SSELevel) { 3231 case AVX512F: 3232 Builder.defineMacro("__AVX512F__"); 3233 case AVX2: 3234 Builder.defineMacro("__AVX2__"); 3235 case AVX: 3236 Builder.defineMacro("__AVX__"); 3237 case SSE42: 3238 Builder.defineMacro("__SSE4_2__"); 3239 case SSE41: 3240 Builder.defineMacro("__SSE4_1__"); 3241 case SSSE3: 3242 Builder.defineMacro("__SSSE3__"); 3243 case SSE3: 3244 Builder.defineMacro("__SSE3__"); 3245 case SSE2: 3246 Builder.defineMacro("__SSE2__"); 3247 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3248 case SSE1: 3249 Builder.defineMacro("__SSE__"); 3250 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3251 case NoSSE: 3252 break; 3253 } 3254 3255 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3256 switch (SSELevel) { 3257 case AVX512F: 3258 case AVX2: 3259 case AVX: 3260 case SSE42: 3261 case SSE41: 3262 case SSSE3: 3263 case SSE3: 3264 case SSE2: 3265 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3266 break; 3267 case SSE1: 3268 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3269 break; 3270 default: 3271 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3272 } 3273 } 3274 3275 // Each case falls through to the previous one here. 3276 switch (MMX3DNowLevel) { 3277 case AMD3DNowAthlon: 3278 Builder.defineMacro("__3dNOW_A__"); 3279 case AMD3DNow: 3280 Builder.defineMacro("__3dNOW__"); 3281 case MMX: 3282 Builder.defineMacro("__MMX__"); 3283 case NoMMX3DNow: 3284 break; 3285 } 3286 3287 if (CPU >= CK_i486) { 3288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3291 } 3292 if (CPU >= CK_i586) 3293 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3294 } 3295 3296 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3297 return llvm::StringSwitch<bool>(Feature) 3298 .Case("aes", HasAES) 3299 .Case("avx", SSELevel >= AVX) 3300 .Case("avx2", SSELevel >= AVX2) 3301 .Case("avx512f", SSELevel >= AVX512F) 3302 .Case("avx512cd", HasAVX512CD) 3303 .Case("avx512er", HasAVX512ER) 3304 .Case("avx512pf", HasAVX512PF) 3305 .Case("avx512dq", HasAVX512DQ) 3306 .Case("avx512bw", HasAVX512BW) 3307 .Case("avx512vl", HasAVX512VL) 3308 .Case("bmi", HasBMI) 3309 .Case("bmi2", HasBMI2) 3310 .Case("cx16", HasCX16) 3311 .Case("f16c", HasF16C) 3312 .Case("fma", HasFMA) 3313 .Case("fma4", XOPLevel >= FMA4) 3314 .Case("fsgsbase", HasFSGSBASE) 3315 .Case("lzcnt", HasLZCNT) 3316 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3317 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3318 .Case("mmx", MMX3DNowLevel >= MMX) 3319 .Case("pclmul", HasPCLMUL) 3320 .Case("popcnt", HasPOPCNT) 3321 .Case("prfchw", HasPRFCHW) 3322 .Case("rdrnd", HasRDRND) 3323 .Case("rdseed", HasRDSEED) 3324 .Case("rtm", HasRTM) 3325 .Case("sha", HasSHA) 3326 .Case("sse", SSELevel >= SSE1) 3327 .Case("sse2", SSELevel >= SSE2) 3328 .Case("sse3", SSELevel >= SSE3) 3329 .Case("ssse3", SSELevel >= SSSE3) 3330 .Case("sse4.1", SSELevel >= SSE41) 3331 .Case("sse4.2", SSELevel >= SSE42) 3332 .Case("sse4a", XOPLevel >= SSE4A) 3333 .Case("tbm", HasTBM) 3334 .Case("x86", true) 3335 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3336 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3337 .Case("xop", XOPLevel >= XOP) 3338 .Default(false); 3339 } 3340 3341 // We can't use a generic validation scheme for the features accepted here 3342 // versus subtarget features accepted in the target attribute because the 3343 // bitfield structure that's initialized in the runtime only supports the 3344 // below currently rather than the full range of subtarget features. (See 3345 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3346 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3347 return llvm::StringSwitch<bool>(FeatureStr) 3348 .Case("cmov", true) 3349 .Case("mmx", true) 3350 .Case("popcnt", true) 3351 .Case("sse", true) 3352 .Case("sse2", true) 3353 .Case("sse3", true) 3354 .Case("sse4.1", true) 3355 .Case("sse4.2", true) 3356 .Case("avx", true) 3357 .Case("avx2", true) 3358 .Case("sse4a", true) 3359 .Case("fma4", true) 3360 .Case("xop", true) 3361 .Case("fma", true) 3362 .Case("avx512f", true) 3363 .Case("bmi", true) 3364 .Case("bmi2", true) 3365 .Default(false); 3366 } 3367 3368 bool 3369 X86TargetInfo::validateAsmConstraint(const char *&Name, 3370 TargetInfo::ConstraintInfo &Info) const { 3371 switch (*Name) { 3372 default: return false; 3373 // Constant constraints. 3374 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3375 // instructions. 3376 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3377 // x86_64 instructions. 3378 case 's': 3379 Info.setRequiresImmediate(); 3380 return true; 3381 case 'I': 3382 Info.setRequiresImmediate(0, 31); 3383 return true; 3384 case 'J': 3385 Info.setRequiresImmediate(0, 63); 3386 return true; 3387 case 'K': 3388 Info.setRequiresImmediate(-128, 127); 3389 return true; 3390 case 'L': 3391 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3392 return true; 3393 case 'M': 3394 Info.setRequiresImmediate(0, 3); 3395 return true; 3396 case 'N': 3397 Info.setRequiresImmediate(0, 255); 3398 return true; 3399 case 'O': 3400 Info.setRequiresImmediate(0, 127); 3401 return true; 3402 // Register constraints. 3403 case 'Y': // 'Y' is the first character for several 2-character constraints. 3404 // Shift the pointer to the second character of the constraint. 3405 Name++; 3406 switch (*Name) { 3407 default: 3408 return false; 3409 case '0': // First SSE register. 3410 case 't': // Any SSE register, when SSE2 is enabled. 3411 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3412 case 'm': // Any MMX register, when inter-unit moves enabled. 3413 Info.setAllowsRegister(); 3414 return true; 3415 } 3416 case 'f': // Any x87 floating point stack register. 3417 // Constraint 'f' cannot be used for output operands. 3418 if (Info.ConstraintStr[0] == '=') 3419 return false; 3420 Info.setAllowsRegister(); 3421 return true; 3422 case 'a': // eax. 3423 case 'b': // ebx. 3424 case 'c': // ecx. 3425 case 'd': // edx. 3426 case 'S': // esi. 3427 case 'D': // edi. 3428 case 'A': // edx:eax. 3429 case 't': // Top of floating point stack. 3430 case 'u': // Second from top of floating point stack. 3431 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3432 case 'y': // Any MMX register. 3433 case 'x': // Any SSE register. 3434 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3435 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3436 case 'l': // "Index" registers: any general register that can be used as an 3437 // index in a base+index memory access. 3438 Info.setAllowsRegister(); 3439 return true; 3440 // Floating point constant constraints. 3441 case 'C': // SSE floating point constant. 3442 case 'G': // x87 floating point constant. 3443 return true; 3444 } 3445 } 3446 3447 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3448 unsigned Size) const { 3449 // Strip off constraint modifiers. 3450 while (Constraint[0] == '=' || 3451 Constraint[0] == '+' || 3452 Constraint[0] == '&') 3453 Constraint = Constraint.substr(1); 3454 3455 return validateOperandSize(Constraint, Size); 3456 } 3457 3458 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3459 unsigned Size) const { 3460 return validateOperandSize(Constraint, Size); 3461 } 3462 3463 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3464 unsigned Size) const { 3465 switch (Constraint[0]) { 3466 default: break; 3467 case 'y': 3468 return Size <= 64; 3469 case 'f': 3470 case 't': 3471 case 'u': 3472 return Size <= 128; 3473 case 'x': 3474 if (SSELevel >= AVX512F) 3475 // 512-bit zmm registers can be used if target supports AVX512F. 3476 return Size <= 512U; 3477 else if (SSELevel >= AVX) 3478 // 256-bit ymm registers can be used if target supports AVX. 3479 return Size <= 256U; 3480 return Size <= 128U; 3481 case 'Y': 3482 // 'Y' is the first character for several 2-character constraints. 3483 switch (Constraint[1]) { 3484 default: break; 3485 case 'm': 3486 // 'Ym' is synonymous with 'y'. 3487 return Size <= 64; 3488 case 'i': 3489 case 't': 3490 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3491 if (SSELevel >= AVX512F) 3492 return Size <= 512U; 3493 else if (SSELevel >= AVX) 3494 return Size <= 256U; 3495 return SSELevel >= SSE2 && Size <= 128U; 3496 } 3497 3498 } 3499 3500 return true; 3501 } 3502 3503 std::string 3504 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3505 switch (*Constraint) { 3506 case 'a': return std::string("{ax}"); 3507 case 'b': return std::string("{bx}"); 3508 case 'c': return std::string("{cx}"); 3509 case 'd': return std::string("{dx}"); 3510 case 'S': return std::string("{si}"); 3511 case 'D': return std::string("{di}"); 3512 case 'p': // address 3513 return std::string("im"); 3514 case 't': // top of floating point stack. 3515 return std::string("{st}"); 3516 case 'u': // second from top of floating point stack. 3517 return std::string("{st(1)}"); // second from top of floating point stack. 3518 default: 3519 return std::string(1, *Constraint); 3520 } 3521 } 3522 3523 // X86-32 generic target 3524 class X86_32TargetInfo : public X86TargetInfo { 3525 public: 3526 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3527 DoubleAlign = LongLongAlign = 32; 3528 LongDoubleWidth = 96; 3529 LongDoubleAlign = 32; 3530 SuitableAlign = 128; 3531 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3532 SizeType = UnsignedInt; 3533 PtrDiffType = SignedInt; 3534 IntPtrType = SignedInt; 3535 RegParmMax = 3; 3536 3537 // Use fpret for all types. 3538 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3539 (1 << TargetInfo::Double) | 3540 (1 << TargetInfo::LongDouble)); 3541 3542 // x86-32 has atomics up to 8 bytes 3543 // FIXME: Check that we actually have cmpxchg8b before setting 3544 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3545 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3546 } 3547 BuiltinVaListKind getBuiltinVaListKind() const override { 3548 return TargetInfo::CharPtrBuiltinVaList; 3549 } 3550 3551 int getEHDataRegisterNumber(unsigned RegNo) const override { 3552 if (RegNo == 0) return 0; 3553 if (RegNo == 1) return 2; 3554 return -1; 3555 } 3556 bool validateOperandSize(StringRef Constraint, 3557 unsigned Size) const override { 3558 switch (Constraint[0]) { 3559 default: break; 3560 case 'R': 3561 case 'q': 3562 case 'Q': 3563 case 'a': 3564 case 'b': 3565 case 'c': 3566 case 'd': 3567 case 'S': 3568 case 'D': 3569 return Size <= 32; 3570 case 'A': 3571 return Size <= 64; 3572 } 3573 3574 return X86TargetInfo::validateOperandSize(Constraint, Size); 3575 } 3576 }; 3577 3578 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3579 public: 3580 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3581 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3582 3583 unsigned getFloatEvalMethod() const override { 3584 unsigned Major, Minor, Micro; 3585 getTriple().getOSVersion(Major, Minor, Micro); 3586 // New NetBSD uses the default rounding mode. 3587 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3588 return X86_32TargetInfo::getFloatEvalMethod(); 3589 // NetBSD before 6.99.26 defaults to "double" rounding. 3590 return 1; 3591 } 3592 }; 3593 3594 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3595 public: 3596 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3597 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3598 SizeType = UnsignedLong; 3599 IntPtrType = SignedLong; 3600 PtrDiffType = SignedLong; 3601 } 3602 }; 3603 3604 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3605 public: 3606 BitrigI386TargetInfo(const llvm::Triple &Triple) 3607 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3608 SizeType = UnsignedLong; 3609 IntPtrType = SignedLong; 3610 PtrDiffType = SignedLong; 3611 } 3612 }; 3613 3614 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3615 public: 3616 DarwinI386TargetInfo(const llvm::Triple &Triple) 3617 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3618 LongDoubleWidth = 128; 3619 LongDoubleAlign = 128; 3620 SuitableAlign = 128; 3621 SizeType = UnsignedLong; 3622 IntPtrType = SignedLong; 3623 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3624 HasAlignMac68kSupport = true; 3625 } 3626 3627 bool handleTargetFeatures(std::vector<std::string> &Features, 3628 DiagnosticsEngine &Diags) override { 3629 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3630 Diags)) 3631 return false; 3632 // We now know the features we have: we can decide how to align vectors. 3633 MaxVectorAlign = 3634 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3635 return true; 3636 } 3637 }; 3638 3639 // x86-32 Windows target 3640 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3641 public: 3642 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3643 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3644 WCharType = UnsignedShort; 3645 DoubleAlign = LongLongAlign = 64; 3646 bool IsWinCOFF = 3647 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3648 DataLayoutString = IsWinCOFF 3649 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3650 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3651 } 3652 void getTargetDefines(const LangOptions &Opts, 3653 MacroBuilder &Builder) const override { 3654 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3655 } 3656 }; 3657 3658 // x86-32 Windows Visual Studio target 3659 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3660 public: 3661 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3662 : WindowsX86_32TargetInfo(Triple) { 3663 LongDoubleWidth = LongDoubleAlign = 64; 3664 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3665 } 3666 void getTargetDefines(const LangOptions &Opts, 3667 MacroBuilder &Builder) const override { 3668 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3669 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3670 // The value of the following reflects processor type. 3671 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3672 // We lost the original triple, so we use the default. 3673 Builder.defineMacro("_M_IX86", "600"); 3674 } 3675 }; 3676 } // end anonymous namespace 3677 3678 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3679 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3680 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3681 // macro anyway for pre-processor compatibility. 3682 if (Opts.MicrosoftExt) 3683 Builder.defineMacro("__declspec", "__declspec"); 3684 else 3685 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3686 3687 if (!Opts.MicrosoftExt) { 3688 // Provide macros for all the calling convention keywords. Provide both 3689 // single and double underscore prefixed variants. These are available on 3690 // x64 as well as x86, even though they have no effect. 3691 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3692 for (const char *CC : CCs) { 3693 std::string GCCSpelling = "__attribute__((__"; 3694 GCCSpelling += CC; 3695 GCCSpelling += "__))"; 3696 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3697 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3698 } 3699 } 3700 } 3701 3702 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3703 Builder.defineMacro("__MSVCRT__"); 3704 Builder.defineMacro("__MINGW32__"); 3705 addCygMingDefines(Opts, Builder); 3706 } 3707 3708 namespace { 3709 // x86-32 MinGW target 3710 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3711 public: 3712 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3713 : WindowsX86_32TargetInfo(Triple) {} 3714 void getTargetDefines(const LangOptions &Opts, 3715 MacroBuilder &Builder) const override { 3716 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3717 DefineStd(Builder, "WIN32", Opts); 3718 DefineStd(Builder, "WINNT", Opts); 3719 Builder.defineMacro("_X86_"); 3720 addMinGWDefines(Opts, Builder); 3721 } 3722 }; 3723 3724 // x86-32 Cygwin target 3725 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3726 public: 3727 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3728 : X86_32TargetInfo(Triple) { 3729 TLSSupported = false; 3730 WCharType = UnsignedShort; 3731 DoubleAlign = LongLongAlign = 64; 3732 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3733 } 3734 void getTargetDefines(const LangOptions &Opts, 3735 MacroBuilder &Builder) const override { 3736 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3737 Builder.defineMacro("_X86_"); 3738 Builder.defineMacro("__CYGWIN__"); 3739 Builder.defineMacro("__CYGWIN32__"); 3740 addCygMingDefines(Opts, Builder); 3741 DefineStd(Builder, "unix", Opts); 3742 if (Opts.CPlusPlus) 3743 Builder.defineMacro("_GNU_SOURCE"); 3744 } 3745 }; 3746 3747 // x86-32 Haiku target 3748 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3749 public: 3750 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3751 SizeType = UnsignedLong; 3752 IntPtrType = SignedLong; 3753 PtrDiffType = SignedLong; 3754 ProcessIDType = SignedLong; 3755 this->UserLabelPrefix = ""; 3756 this->TLSSupported = false; 3757 } 3758 void getTargetDefines(const LangOptions &Opts, 3759 MacroBuilder &Builder) const override { 3760 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3761 Builder.defineMacro("__INTEL__"); 3762 Builder.defineMacro("__HAIKU__"); 3763 } 3764 }; 3765 3766 // RTEMS Target 3767 template<typename Target> 3768 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3769 protected: 3770 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3771 MacroBuilder &Builder) const override { 3772 // RTEMS defines; list based off of gcc output 3773 3774 Builder.defineMacro("__rtems__"); 3775 Builder.defineMacro("__ELF__"); 3776 } 3777 3778 public: 3779 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3780 this->UserLabelPrefix = ""; 3781 3782 switch (Triple.getArch()) { 3783 default: 3784 case llvm::Triple::x86: 3785 // this->MCountName = ".mcount"; 3786 break; 3787 case llvm::Triple::mips: 3788 case llvm::Triple::mipsel: 3789 case llvm::Triple::ppc: 3790 case llvm::Triple::ppc64: 3791 case llvm::Triple::ppc64le: 3792 // this->MCountName = "_mcount"; 3793 break; 3794 case llvm::Triple::arm: 3795 // this->MCountName = "__mcount"; 3796 break; 3797 } 3798 } 3799 }; 3800 3801 // x86-32 RTEMS target 3802 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3803 public: 3804 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3805 SizeType = UnsignedLong; 3806 IntPtrType = SignedLong; 3807 PtrDiffType = SignedLong; 3808 this->UserLabelPrefix = ""; 3809 } 3810 void getTargetDefines(const LangOptions &Opts, 3811 MacroBuilder &Builder) const override { 3812 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3813 Builder.defineMacro("__INTEL__"); 3814 Builder.defineMacro("__rtems__"); 3815 } 3816 }; 3817 3818 // x86-64 generic target 3819 class X86_64TargetInfo : public X86TargetInfo { 3820 public: 3821 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3822 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3823 bool IsWinCOFF = 3824 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3825 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3826 LongDoubleWidth = 128; 3827 LongDoubleAlign = 128; 3828 LargeArrayMinWidth = 128; 3829 LargeArrayAlign = 128; 3830 SuitableAlign = 128; 3831 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3832 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3833 IntPtrType = IsX32 ? SignedInt : SignedLong; 3834 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3835 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3836 RegParmMax = 6; 3837 3838 // Pointers are 32-bit in x32. 3839 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3840 : IsWinCOFF 3841 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3842 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3843 3844 // Use fpret only for long double. 3845 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3846 3847 // Use fp2ret for _Complex long double. 3848 ComplexLongDoubleUsesFP2Ret = true; 3849 3850 // x86-64 has atomics up to 16 bytes. 3851 MaxAtomicPromoteWidth = 128; 3852 MaxAtomicInlineWidth = 128; 3853 } 3854 BuiltinVaListKind getBuiltinVaListKind() const override { 3855 return TargetInfo::X86_64ABIBuiltinVaList; 3856 } 3857 3858 int getEHDataRegisterNumber(unsigned RegNo) const override { 3859 if (RegNo == 0) return 0; 3860 if (RegNo == 1) return 1; 3861 return -1; 3862 } 3863 3864 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3865 return (CC == CC_C || 3866 CC == CC_X86VectorCall || 3867 CC == CC_IntelOclBicc || 3868 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3869 } 3870 3871 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3872 return CC_C; 3873 } 3874 3875 // for x32 we need it here explicitly 3876 bool hasInt128Type() const override { return true; } 3877 }; 3878 3879 // x86-64 Windows target 3880 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3881 public: 3882 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3883 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3884 WCharType = UnsignedShort; 3885 LongWidth = LongAlign = 32; 3886 DoubleAlign = LongLongAlign = 64; 3887 IntMaxType = SignedLongLong; 3888 Int64Type = SignedLongLong; 3889 SizeType = UnsignedLongLong; 3890 PtrDiffType = SignedLongLong; 3891 IntPtrType = SignedLongLong; 3892 this->UserLabelPrefix = ""; 3893 } 3894 3895 void getTargetDefines(const LangOptions &Opts, 3896 MacroBuilder &Builder) const override { 3897 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3898 Builder.defineMacro("_WIN64"); 3899 } 3900 3901 BuiltinVaListKind getBuiltinVaListKind() const override { 3902 return TargetInfo::CharPtrBuiltinVaList; 3903 } 3904 3905 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3906 switch (CC) { 3907 case CC_X86StdCall: 3908 case CC_X86ThisCall: 3909 case CC_X86FastCall: 3910 return CCCR_Ignore; 3911 case CC_C: 3912 case CC_X86VectorCall: 3913 case CC_IntelOclBicc: 3914 case CC_X86_64SysV: 3915 return CCCR_OK; 3916 default: 3917 return CCCR_Warning; 3918 } 3919 } 3920 }; 3921 3922 // x86-64 Windows Visual Studio target 3923 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3924 public: 3925 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3926 : WindowsX86_64TargetInfo(Triple) { 3927 LongDoubleWidth = LongDoubleAlign = 64; 3928 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3929 } 3930 void getTargetDefines(const LangOptions &Opts, 3931 MacroBuilder &Builder) const override { 3932 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3933 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3934 Builder.defineMacro("_M_X64", "100"); 3935 Builder.defineMacro("_M_AMD64", "100"); 3936 } 3937 }; 3938 3939 // x86-64 MinGW target 3940 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3941 public: 3942 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3943 : WindowsX86_64TargetInfo(Triple) {} 3944 void getTargetDefines(const LangOptions &Opts, 3945 MacroBuilder &Builder) const override { 3946 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3947 DefineStd(Builder, "WIN64", Opts); 3948 Builder.defineMacro("__MINGW64__"); 3949 addMinGWDefines(Opts, Builder); 3950 3951 // GCC defines this macro when it is using __gxx_personality_seh0. 3952 if (!Opts.SjLjExceptions) 3953 Builder.defineMacro("__SEH__"); 3954 } 3955 }; 3956 3957 // x86-64 Cygwin target 3958 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 3959 public: 3960 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 3961 : X86_64TargetInfo(Triple) { 3962 TLSSupported = false; 3963 WCharType = UnsignedShort; 3964 } 3965 void getTargetDefines(const LangOptions &Opts, 3966 MacroBuilder &Builder) const override { 3967 X86_64TargetInfo::getTargetDefines(Opts, Builder); 3968 Builder.defineMacro("__x86_64__"); 3969 Builder.defineMacro("__CYGWIN__"); 3970 Builder.defineMacro("__CYGWIN64__"); 3971 addCygMingDefines(Opts, Builder); 3972 DefineStd(Builder, "unix", Opts); 3973 if (Opts.CPlusPlus) 3974 Builder.defineMacro("_GNU_SOURCE"); 3975 3976 // GCC defines this macro when it is using __gxx_personality_seh0. 3977 if (!Opts.SjLjExceptions) 3978 Builder.defineMacro("__SEH__"); 3979 } 3980 }; 3981 3982 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3983 public: 3984 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3985 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3986 Int64Type = SignedLongLong; 3987 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3988 llvm::Triple T = llvm::Triple(Triple); 3989 if (T.isiOS()) 3990 UseSignedCharForObjCBool = false; 3991 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3992 } 3993 3994 bool handleTargetFeatures(std::vector<std::string> &Features, 3995 DiagnosticsEngine &Diags) override { 3996 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 3997 Diags)) 3998 return false; 3999 // We now know the features we have: we can decide how to align vectors. 4000 MaxVectorAlign = 4001 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4002 return true; 4003 } 4004 }; 4005 4006 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4007 public: 4008 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4009 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4010 IntMaxType = SignedLongLong; 4011 Int64Type = SignedLongLong; 4012 } 4013 }; 4014 4015 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4016 public: 4017 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4018 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4019 IntMaxType = SignedLongLong; 4020 Int64Type = SignedLongLong; 4021 } 4022 }; 4023 4024 class ARMTargetInfo : public TargetInfo { 4025 // Possible FPU choices. 4026 enum FPUMode { 4027 VFP2FPU = (1 << 0), 4028 VFP3FPU = (1 << 1), 4029 VFP4FPU = (1 << 2), 4030 NeonFPU = (1 << 3), 4031 FPARMV8 = (1 << 4) 4032 }; 4033 4034 // Possible HWDiv features. 4035 enum HWDivMode { 4036 HWDivThumb = (1 << 0), 4037 HWDivARM = (1 << 1) 4038 }; 4039 4040 static bool FPUModeIsVFP(FPUMode Mode) { 4041 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4042 } 4043 4044 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4045 static const char * const GCCRegNames[]; 4046 4047 std::string ABI, CPU; 4048 4049 StringRef DefaultCPU; 4050 StringRef CPUProfile; 4051 StringRef CPUAttr; 4052 4053 enum { 4054 FP_Default, 4055 FP_VFP, 4056 FP_Neon 4057 } FPMath; 4058 4059 unsigned ArchISA; 4060 unsigned ArchKind; 4061 unsigned ArchProfile; 4062 unsigned ArchVersion; 4063 4064 unsigned FPU : 5; 4065 4066 unsigned IsAAPCS : 1; 4067 unsigned HWDiv : 2; 4068 4069 // Initialized via features. 4070 unsigned SoftFloat : 1; 4071 unsigned SoftFloatABI : 1; 4072 4073 unsigned CRC : 1; 4074 unsigned Crypto : 1; 4075 4076 // ACLE 6.5.1 Hardware floating point 4077 enum { 4078 HW_FP_HP = (1 << 1), /// half (16-bit) 4079 HW_FP_SP = (1 << 2), /// single (32-bit) 4080 HW_FP_DP = (1 << 3), /// double (64-bit) 4081 }; 4082 uint32_t HW_FP; 4083 4084 static const Builtin::Info BuiltinInfo[]; 4085 4086 void setABIAAPCS() { 4087 IsAAPCS = true; 4088 4089 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4090 const llvm::Triple &T = getTriple(); 4091 4092 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4093 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4094 T.getOS() == llvm::Triple::Bitrig) 4095 SizeType = UnsignedLong; 4096 else 4097 SizeType = UnsignedInt; 4098 4099 switch (T.getOS()) { 4100 case llvm::Triple::NetBSD: 4101 WCharType = SignedInt; 4102 break; 4103 case llvm::Triple::Win32: 4104 WCharType = UnsignedShort; 4105 break; 4106 case llvm::Triple::Linux: 4107 default: 4108 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4109 WCharType = UnsignedInt; 4110 break; 4111 } 4112 4113 UseBitFieldTypeAlignment = true; 4114 4115 ZeroLengthBitfieldBoundary = 0; 4116 4117 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4118 // so set preferred for small types to 32. 4119 if (T.isOSBinFormatMachO()) { 4120 DataLayoutString = 4121 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4122 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4123 } else if (T.isOSWindows()) { 4124 assert(!BigEndian && "Windows on ARM does not support big endian"); 4125 DataLayoutString = "e" 4126 "-m:w" 4127 "-p:32:32" 4128 "-i64:64" 4129 "-v128:64:128" 4130 "-a:0:32" 4131 "-n32" 4132 "-S64"; 4133 } else if (T.isOSNaCl()) { 4134 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4135 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4136 } else { 4137 DataLayoutString = 4138 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4139 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4140 } 4141 4142 // FIXME: Enumerated types are variable width in straight AAPCS. 4143 } 4144 4145 void setABIAPCS() { 4146 const llvm::Triple &T = getTriple(); 4147 4148 IsAAPCS = false; 4149 4150 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4151 4152 // size_t is unsigned int on FreeBSD. 4153 if (T.getOS() == llvm::Triple::FreeBSD) 4154 SizeType = UnsignedInt; 4155 else 4156 SizeType = UnsignedLong; 4157 4158 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4159 WCharType = SignedInt; 4160 4161 // Do not respect the alignment of bit-field types when laying out 4162 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4163 UseBitFieldTypeAlignment = false; 4164 4165 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4166 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4167 /// gcc. 4168 ZeroLengthBitfieldBoundary = 32; 4169 4170 if (T.isOSBinFormatMachO()) 4171 DataLayoutString = 4172 BigEndian 4173 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4174 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4175 else 4176 DataLayoutString = 4177 BigEndian 4178 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4179 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4180 4181 // FIXME: Override "preferred align" for double and long long. 4182 } 4183 4184 void setArchInfo() { 4185 StringRef ArchName = getTriple().getArchName(); 4186 4187 ArchISA = llvm::ARM::parseArchISA(ArchName); 4188 DefaultCPU = getDefaultCPU(ArchName); 4189 4190 unsigned ArchKind = llvm::ARM::parseArch(ArchName); 4191 if (ArchKind == llvm::ARM::AK_INVALID) 4192 // set arch of the CPU, either provided explicitly or hardcoded default 4193 ArchKind = llvm::ARM::parseCPUArch(CPU); 4194 setArchInfo(ArchKind); 4195 } 4196 4197 void setArchInfo(unsigned Kind) { 4198 StringRef SubArch; 4199 4200 // cache TargetParser info 4201 ArchKind = Kind; 4202 SubArch = llvm::ARM::getSubArch(ArchKind); 4203 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4204 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4205 4206 // cache CPU related strings 4207 CPUAttr = getCPUAttr(); 4208 CPUProfile = getCPUProfile(); 4209 } 4210 4211 void setAtomic() { 4212 // when triple does not specify a sub arch, 4213 // then we are not using inline atomics 4214 bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 4215 false : 4216 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4217 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4218 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4219 if (ArchProfile == llvm::ARM::PK_M) { 4220 MaxAtomicPromoteWidth = 32; 4221 if (ShouldUseInlineAtomic) 4222 MaxAtomicInlineWidth = 32; 4223 } 4224 else { 4225 MaxAtomicPromoteWidth = 64; 4226 if (ShouldUseInlineAtomic) 4227 MaxAtomicInlineWidth = 64; 4228 } 4229 } 4230 4231 bool isThumb() const { 4232 return (ArchISA == llvm::ARM::IK_THUMB); 4233 } 4234 4235 bool supportsThumb() const { 4236 return CPUAttr.count('T') || ArchVersion >= 6; 4237 } 4238 4239 bool supportsThumb2() const { 4240 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4241 } 4242 4243 StringRef getDefaultCPU(StringRef ArchName) const { 4244 return llvm::ARM::getDefaultCPU(ArchName); 4245 } 4246 4247 StringRef getCPUAttr() const { 4248 // For most sub-arches, the build attribute CPU name is enough. 4249 // For Cortex variants, it's slightly different. 4250 switch(ArchKind) { 4251 default: 4252 return llvm::ARM::getCPUAttr(ArchKind); 4253 case llvm::ARM::AK_ARMV6M: 4254 case llvm::ARM::AK_ARMV6SM: 4255 case llvm::ARM::AK_ARMV6HL: 4256 return "6M"; 4257 case llvm::ARM::AK_ARMV7S: 4258 return "7S"; 4259 case llvm::ARM::AK_ARMV7: 4260 case llvm::ARM::AK_ARMV7A: 4261 case llvm::ARM::AK_ARMV7L: 4262 case llvm::ARM::AK_ARMV7HL: 4263 return "7A"; 4264 case llvm::ARM::AK_ARMV7R: 4265 return "7R"; 4266 case llvm::ARM::AK_ARMV7M: 4267 return "7M"; 4268 case llvm::ARM::AK_ARMV7EM: 4269 return "7EM"; 4270 case llvm::ARM::AK_ARMV8A: 4271 return "8A"; 4272 case llvm::ARM::AK_ARMV8_1A: 4273 return "8_1A"; 4274 } 4275 } 4276 4277 StringRef getCPUProfile() const { 4278 switch(ArchProfile) { 4279 case llvm::ARM::PK_A: 4280 return "A"; 4281 case llvm::ARM::PK_R: 4282 return "R"; 4283 case llvm::ARM::PK_M: 4284 return "M"; 4285 default: 4286 return ""; 4287 } 4288 } 4289 4290 public: 4291 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4292 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4293 IsAAPCS(true), HW_FP(0) { 4294 BigEndian = IsBigEndian; 4295 4296 switch (getTriple().getOS()) { 4297 case llvm::Triple::NetBSD: 4298 PtrDiffType = SignedLong; 4299 break; 4300 default: 4301 PtrDiffType = SignedInt; 4302 break; 4303 } 4304 4305 // cache arch related info 4306 setArchInfo(); 4307 4308 // {} in inline assembly are neon specifiers, not assembly variant 4309 // specifiers. 4310 NoAsmVariants = true; 4311 4312 // FIXME: This duplicates code from the driver that sets the -target-abi 4313 // option - this code is used if -target-abi isn't passed and should 4314 // be unified in some way. 4315 if (Triple.isOSBinFormatMachO()) { 4316 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4317 // the frontend matches that. 4318 if (Triple.getEnvironment() == llvm::Triple::EABI || 4319 Triple.getOS() == llvm::Triple::UnknownOS || 4320 StringRef(CPU).startswith("cortex-m")) { 4321 setABI("aapcs"); 4322 } else { 4323 setABI("apcs-gnu"); 4324 } 4325 } else if (Triple.isOSWindows()) { 4326 // FIXME: this is invalid for WindowsCE 4327 setABI("aapcs"); 4328 } else { 4329 // Select the default based on the platform. 4330 switch (Triple.getEnvironment()) { 4331 case llvm::Triple::Android: 4332 case llvm::Triple::GNUEABI: 4333 case llvm::Triple::GNUEABIHF: 4334 setABI("aapcs-linux"); 4335 break; 4336 case llvm::Triple::EABIHF: 4337 case llvm::Triple::EABI: 4338 setABI("aapcs"); 4339 break; 4340 case llvm::Triple::GNU: 4341 setABI("apcs-gnu"); 4342 break; 4343 default: 4344 if (Triple.getOS() == llvm::Triple::NetBSD) 4345 setABI("apcs-gnu"); 4346 else 4347 setABI("aapcs"); 4348 break; 4349 } 4350 } 4351 4352 // ARM targets default to using the ARM C++ ABI. 4353 TheCXXABI.set(TargetCXXABI::GenericARM); 4354 4355 // ARM has atomics up to 8 bytes 4356 setAtomic(); 4357 4358 // Do force alignment of members that follow zero length bitfields. If 4359 // the alignment of the zero-length bitfield is greater than the member 4360 // that follows it, `bar', `bar' will be aligned as the type of the 4361 // zero length bitfield. 4362 UseZeroLengthBitfieldAlignment = true; 4363 } 4364 4365 StringRef getABI() const override { return ABI; } 4366 4367 bool setABI(const std::string &Name) override { 4368 ABI = Name; 4369 4370 // The defaults (above) are for AAPCS, check if we need to change them. 4371 // 4372 // FIXME: We need support for -meabi... we could just mangle it into the 4373 // name. 4374 if (Name == "apcs-gnu") { 4375 setABIAPCS(); 4376 return true; 4377 } 4378 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4379 setABIAAPCS(); 4380 return true; 4381 } 4382 return false; 4383 } 4384 4385 // FIXME: This should be based on Arch attributes, not CPU names. 4386 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4387 StringRef CPU, 4388 std::vector<std::string> &FeaturesVec) const override { 4389 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4390 Features["vfp2"] = true; 4391 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4392 Features["vfp3"] = true; 4393 Features["neon"] = true; 4394 } 4395 else if (CPU == "cortex-a5") { 4396 Features["vfp4"] = true; 4397 Features["neon"] = true; 4398 } else if (CPU == "swift" || CPU == "cortex-a7" || 4399 CPU == "cortex-a12" || CPU == "cortex-a15" || 4400 CPU == "cortex-a17" || CPU == "krait") { 4401 Features["vfp4"] = true; 4402 Features["neon"] = true; 4403 Features["hwdiv"] = true; 4404 Features["hwdiv-arm"] = true; 4405 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4406 CPU == "cortex-a72") { 4407 Features["fp-armv8"] = true; 4408 Features["neon"] = true; 4409 Features["hwdiv"] = true; 4410 Features["hwdiv-arm"] = true; 4411 Features["crc"] = true; 4412 Features["crypto"] = true; 4413 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) { 4414 Features["hwdiv"] = true; 4415 Features["hwdiv-arm"] = true; 4416 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4417 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4418 Features["hwdiv"] = true; 4419 } 4420 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4421 } 4422 4423 bool handleTargetFeatures(std::vector<std::string> &Features, 4424 DiagnosticsEngine &Diags) override { 4425 FPU = 0; 4426 CRC = 0; 4427 Crypto = 0; 4428 SoftFloat = SoftFloatABI = false; 4429 HWDiv = 0; 4430 4431 // This does not diagnose illegal cases like having both 4432 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4433 uint32_t HW_FP_remove = 0; 4434 for (const auto &Feature : Features) { 4435 if (Feature == "+soft-float") { 4436 SoftFloat = true; 4437 } else if (Feature == "+soft-float-abi") { 4438 SoftFloatABI = true; 4439 } else if (Feature == "+vfp2") { 4440 FPU |= VFP2FPU; 4441 HW_FP |= HW_FP_SP | HW_FP_DP; 4442 } else if (Feature == "+vfp3") { 4443 FPU |= VFP3FPU; 4444 HW_FP |= HW_FP_SP | HW_FP_DP; 4445 } else if (Feature == "+vfp4") { 4446 FPU |= VFP4FPU; 4447 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4448 } else if (Feature == "+fp-armv8") { 4449 FPU |= FPARMV8; 4450 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4451 } else if (Feature == "+neon") { 4452 FPU |= NeonFPU; 4453 HW_FP |= HW_FP_SP | HW_FP_DP; 4454 } else if (Feature == "+hwdiv") { 4455 HWDiv |= HWDivThumb; 4456 } else if (Feature == "+hwdiv-arm") { 4457 HWDiv |= HWDivARM; 4458 } else if (Feature == "+crc") { 4459 CRC = 1; 4460 } else if (Feature == "+crypto") { 4461 Crypto = 1; 4462 } else if (Feature == "+fp-only-sp") { 4463 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4464 } 4465 } 4466 HW_FP &= ~HW_FP_remove; 4467 4468 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4469 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4470 return false; 4471 } 4472 4473 if (FPMath == FP_Neon) 4474 Features.push_back("+neonfp"); 4475 else if (FPMath == FP_VFP) 4476 Features.push_back("-neonfp"); 4477 4478 // Remove front-end specific options which the backend handles differently. 4479 auto Feature = 4480 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4481 if (Feature != Features.end()) 4482 Features.erase(Feature); 4483 4484 return true; 4485 } 4486 4487 bool hasFeature(StringRef Feature) const override { 4488 return llvm::StringSwitch<bool>(Feature) 4489 .Case("arm", true) 4490 .Case("aarch32", true) 4491 .Case("softfloat", SoftFloat) 4492 .Case("thumb", isThumb()) 4493 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4494 .Case("hwdiv", HWDiv & HWDivThumb) 4495 .Case("hwdiv-arm", HWDiv & HWDivARM) 4496 .Default(false); 4497 } 4498 4499 bool setCPU(const std::string &Name) override { 4500 if (Name != "generic") 4501 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4502 4503 if (ArchKind == llvm::ARM::AK_INVALID) 4504 return false; 4505 setAtomic(); 4506 CPU = Name; 4507 return true; 4508 } 4509 4510 bool setFPMath(StringRef Name) override; 4511 4512 void getTargetDefines(const LangOptions &Opts, 4513 MacroBuilder &Builder) const override { 4514 // Target identification. 4515 Builder.defineMacro("__arm"); 4516 Builder.defineMacro("__arm__"); 4517 4518 // Target properties. 4519 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4520 if (!CPUAttr.empty()) 4521 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4522 4523 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4524 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4525 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4526 if (ArchVersion >= 8) { 4527 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4528 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4529 } 4530 4531 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4532 // is not defined for the M-profile. 4533 // NOTE that the deffault profile is assumed to be 'A' 4534 if (CPUProfile.empty() || CPUProfile != "M") 4535 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4536 4537 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4538 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4539 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4540 if (supportsThumb2()) 4541 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4542 else if (supportsThumb()) 4543 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4544 4545 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4546 // instruction set such as ARM or Thumb. 4547 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4548 4549 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4550 4551 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4552 if (!CPUProfile.empty()) 4553 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4554 4555 // ACLE 6.5.1 Hardware Floating Point 4556 if (HW_FP) 4557 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4558 4559 // ACLE predefines. 4560 Builder.defineMacro("__ARM_ACLE", "200"); 4561 4562 // Subtarget options. 4563 4564 // FIXME: It's more complicated than this and we don't really support 4565 // interworking. 4566 // Windows on ARM does not "support" interworking 4567 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4568 Builder.defineMacro("__THUMB_INTERWORK__"); 4569 4570 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4571 // Embedded targets on Darwin follow AAPCS, but not EABI. 4572 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4573 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4574 Builder.defineMacro("__ARM_EABI__"); 4575 Builder.defineMacro("__ARM_PCS", "1"); 4576 4577 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4578 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4579 } 4580 4581 if (SoftFloat) 4582 Builder.defineMacro("__SOFTFP__"); 4583 4584 if (CPU == "xscale") 4585 Builder.defineMacro("__XSCALE__"); 4586 4587 if (isThumb()) { 4588 Builder.defineMacro("__THUMBEL__"); 4589 Builder.defineMacro("__thumb__"); 4590 if (supportsThumb2()) 4591 Builder.defineMacro("__thumb2__"); 4592 } 4593 if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) 4594 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4595 4596 // Note, this is always on in gcc, even though it doesn't make sense. 4597 Builder.defineMacro("__APCS_32__"); 4598 4599 if (FPUModeIsVFP((FPUMode) FPU)) { 4600 Builder.defineMacro("__VFP_FP__"); 4601 if (FPU & VFP2FPU) 4602 Builder.defineMacro("__ARM_VFPV2__"); 4603 if (FPU & VFP3FPU) 4604 Builder.defineMacro("__ARM_VFPV3__"); 4605 if (FPU & VFP4FPU) 4606 Builder.defineMacro("__ARM_VFPV4__"); 4607 } 4608 4609 // This only gets set when Neon instructions are actually available, unlike 4610 // the VFP define, hence the soft float and arch check. This is subtly 4611 // different from gcc, we follow the intent which was that it should be set 4612 // when Neon instructions are actually available. 4613 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4614 Builder.defineMacro("__ARM_NEON"); 4615 Builder.defineMacro("__ARM_NEON__"); 4616 } 4617 4618 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4619 Opts.ShortWChar ? "2" : "4"); 4620 4621 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4622 Opts.ShortEnums ? "1" : "4"); 4623 4624 if (CRC) 4625 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4626 4627 if (Crypto) 4628 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4629 4630 if (ArchVersion >= 6 && CPUAttr != "6M") { 4631 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4632 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4633 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4634 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4635 } 4636 4637 bool is5EOrAbove = (ArchVersion >= 6 || 4638 (ArchVersion == 5 && CPUAttr.count('E'))); 4639 // FIXME: We are not getting all 32-bit ARM architectures 4640 bool is32Bit = (!isThumb() || supportsThumb2()); 4641 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM")) 4642 Builder.defineMacro("__ARM_FEATURE_DSP"); 4643 } 4644 4645 void getTargetBuiltins(const Builtin::Info *&Records, 4646 unsigned &NumRecords) const override { 4647 Records = BuiltinInfo; 4648 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4649 } 4650 bool isCLZForZeroUndef() const override { return false; } 4651 BuiltinVaListKind getBuiltinVaListKind() const override { 4652 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4653 } 4654 void getGCCRegNames(const char * const *&Names, 4655 unsigned &NumNames) const override; 4656 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4657 unsigned &NumAliases) const override; 4658 bool validateAsmConstraint(const char *&Name, 4659 TargetInfo::ConstraintInfo &Info) const override { 4660 switch (*Name) { 4661 default: break; 4662 case 'l': // r0-r7 4663 case 'h': // r8-r15 4664 case 'w': // VFP Floating point register single precision 4665 case 'P': // VFP Floating point register double precision 4666 Info.setAllowsRegister(); 4667 return true; 4668 case 'I': 4669 case 'J': 4670 case 'K': 4671 case 'L': 4672 case 'M': 4673 // FIXME 4674 return true; 4675 case 'Q': // A memory address that is a single base register. 4676 Info.setAllowsMemory(); 4677 return true; 4678 case 'U': // a memory reference... 4679 switch (Name[1]) { 4680 case 'q': // ...ARMV4 ldrsb 4681 case 'v': // ...VFP load/store (reg+constant offset) 4682 case 'y': // ...iWMMXt load/store 4683 case 't': // address valid for load/store opaque types wider 4684 // than 128-bits 4685 case 'n': // valid address for Neon doubleword vector load/store 4686 case 'm': // valid address for Neon element and structure load/store 4687 case 's': // valid address for non-offset loads/stores of quad-word 4688 // values in four ARM registers 4689 Info.setAllowsMemory(); 4690 Name++; 4691 return true; 4692 } 4693 } 4694 return false; 4695 } 4696 std::string convertConstraint(const char *&Constraint) const override { 4697 std::string R; 4698 switch (*Constraint) { 4699 case 'U': // Two-character constraint; add "^" hint for later parsing. 4700 R = std::string("^") + std::string(Constraint, 2); 4701 Constraint++; 4702 break; 4703 case 'p': // 'p' should be translated to 'r' by default. 4704 R = std::string("r"); 4705 break; 4706 default: 4707 return std::string(1, *Constraint); 4708 } 4709 return R; 4710 } 4711 bool 4712 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4713 std::string &SuggestedModifier) const override { 4714 bool isOutput = (Constraint[0] == '='); 4715 bool isInOut = (Constraint[0] == '+'); 4716 4717 // Strip off constraint modifiers. 4718 while (Constraint[0] == '=' || 4719 Constraint[0] == '+' || 4720 Constraint[0] == '&') 4721 Constraint = Constraint.substr(1); 4722 4723 switch (Constraint[0]) { 4724 default: break; 4725 case 'r': { 4726 switch (Modifier) { 4727 default: 4728 return (isInOut || isOutput || Size <= 64); 4729 case 'q': 4730 // A register of size 32 cannot fit a vector type. 4731 return false; 4732 } 4733 } 4734 } 4735 4736 return true; 4737 } 4738 const char *getClobbers() const override { 4739 // FIXME: Is this really right? 4740 return ""; 4741 } 4742 4743 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4744 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4745 } 4746 4747 int getEHDataRegisterNumber(unsigned RegNo) const override { 4748 if (RegNo == 0) return 0; 4749 if (RegNo == 1) return 1; 4750 return -1; 4751 } 4752 4753 bool hasSjLjLowering() const override { 4754 return true; 4755 } 4756 }; 4757 4758 bool ARMTargetInfo::setFPMath(StringRef Name) { 4759 if (Name == "neon") { 4760 FPMath = FP_Neon; 4761 return true; 4762 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4763 Name == "vfp4") { 4764 FPMath = FP_VFP; 4765 return true; 4766 } 4767 return false; 4768 } 4769 4770 const char * const ARMTargetInfo::GCCRegNames[] = { 4771 // Integer registers 4772 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4773 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4774 4775 // Float registers 4776 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4777 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4778 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4779 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4780 4781 // Double registers 4782 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4783 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4784 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4785 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4786 4787 // Quad registers 4788 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4789 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4790 }; 4791 4792 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4793 unsigned &NumNames) const { 4794 Names = GCCRegNames; 4795 NumNames = llvm::array_lengthof(GCCRegNames); 4796 } 4797 4798 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4799 { { "a1" }, "r0" }, 4800 { { "a2" }, "r1" }, 4801 { { "a3" }, "r2" }, 4802 { { "a4" }, "r3" }, 4803 { { "v1" }, "r4" }, 4804 { { "v2" }, "r5" }, 4805 { { "v3" }, "r6" }, 4806 { { "v4" }, "r7" }, 4807 { { "v5" }, "r8" }, 4808 { { "v6", "rfp" }, "r9" }, 4809 { { "sl" }, "r10" }, 4810 { { "fp" }, "r11" }, 4811 { { "ip" }, "r12" }, 4812 { { "r13" }, "sp" }, 4813 { { "r14" }, "lr" }, 4814 { { "r15" }, "pc" }, 4815 // The S, D and Q registers overlap, but aren't really aliases; we 4816 // don't want to substitute one of these for a different-sized one. 4817 }; 4818 4819 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4820 unsigned &NumAliases) const { 4821 Aliases = GCCRegAliases; 4822 NumAliases = llvm::array_lengthof(GCCRegAliases); 4823 } 4824 4825 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4826 #define BUILTIN(ID, TYPE, ATTRS) \ 4827 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4829 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4830 #include "clang/Basic/BuiltinsNEON.def" 4831 4832 #define BUILTIN(ID, TYPE, ATTRS) \ 4833 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4834 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4835 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr}, 4836 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4837 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4838 #include "clang/Basic/BuiltinsARM.def" 4839 }; 4840 4841 class ARMleTargetInfo : public ARMTargetInfo { 4842 public: 4843 ARMleTargetInfo(const llvm::Triple &Triple) 4844 : ARMTargetInfo(Triple, false) { } 4845 void getTargetDefines(const LangOptions &Opts, 4846 MacroBuilder &Builder) const override { 4847 Builder.defineMacro("__ARMEL__"); 4848 ARMTargetInfo::getTargetDefines(Opts, Builder); 4849 } 4850 }; 4851 4852 class ARMbeTargetInfo : public ARMTargetInfo { 4853 public: 4854 ARMbeTargetInfo(const llvm::Triple &Triple) 4855 : ARMTargetInfo(Triple, true) { } 4856 void getTargetDefines(const LangOptions &Opts, 4857 MacroBuilder &Builder) const override { 4858 Builder.defineMacro("__ARMEB__"); 4859 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4860 ARMTargetInfo::getTargetDefines(Opts, Builder); 4861 } 4862 }; 4863 4864 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4865 const llvm::Triple Triple; 4866 public: 4867 WindowsARMTargetInfo(const llvm::Triple &Triple) 4868 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4869 TLSSupported = false; 4870 WCharType = UnsignedShort; 4871 SizeType = UnsignedInt; 4872 UserLabelPrefix = ""; 4873 } 4874 void getVisualStudioDefines(const LangOptions &Opts, 4875 MacroBuilder &Builder) const { 4876 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4877 4878 // FIXME: this is invalid for WindowsCE 4879 Builder.defineMacro("_M_ARM_NT", "1"); 4880 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4881 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4882 4883 assert((Triple.getArch() == llvm::Triple::arm || 4884 Triple.getArch() == llvm::Triple::thumb) && 4885 "invalid architecture for Windows ARM target info"); 4886 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4887 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4888 4889 // TODO map the complete set of values 4890 // 31: VFPv3 40: VFPv4 4891 Builder.defineMacro("_M_ARM_FP", "31"); 4892 } 4893 BuiltinVaListKind getBuiltinVaListKind() const override { 4894 return TargetInfo::CharPtrBuiltinVaList; 4895 } 4896 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4897 switch (CC) { 4898 case CC_X86StdCall: 4899 case CC_X86ThisCall: 4900 case CC_X86FastCall: 4901 case CC_X86VectorCall: 4902 return CCCR_Ignore; 4903 case CC_C: 4904 return CCCR_OK; 4905 default: 4906 return CCCR_Warning; 4907 } 4908 } 4909 }; 4910 4911 // Windows ARM + Itanium C++ ABI Target 4912 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4913 public: 4914 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4915 : WindowsARMTargetInfo(Triple) { 4916 TheCXXABI.set(TargetCXXABI::GenericARM); 4917 } 4918 4919 void getTargetDefines(const LangOptions &Opts, 4920 MacroBuilder &Builder) const override { 4921 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4922 4923 if (Opts.MSVCCompat) 4924 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4925 } 4926 }; 4927 4928 // Windows ARM, MS (C++) ABI 4929 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4930 public: 4931 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4932 : WindowsARMTargetInfo(Triple) { 4933 TheCXXABI.set(TargetCXXABI::Microsoft); 4934 } 4935 4936 void getTargetDefines(const LangOptions &Opts, 4937 MacroBuilder &Builder) const override { 4938 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4939 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4940 } 4941 }; 4942 4943 // ARM MinGW target 4944 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 4945 public: 4946 MinGWARMTargetInfo(const llvm::Triple &Triple) 4947 : WindowsARMTargetInfo(Triple) { 4948 TheCXXABI.set(TargetCXXABI::GenericARM); 4949 } 4950 4951 void getTargetDefines(const LangOptions &Opts, 4952 MacroBuilder &Builder) const override { 4953 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4954 DefineStd(Builder, "WIN32", Opts); 4955 DefineStd(Builder, "WINNT", Opts); 4956 Builder.defineMacro("_ARM_"); 4957 addMinGWDefines(Opts, Builder); 4958 } 4959 }; 4960 4961 // ARM Cygwin target 4962 class CygwinARMTargetInfo : public ARMleTargetInfo { 4963 public: 4964 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 4965 TLSSupported = false; 4966 WCharType = UnsignedShort; 4967 DoubleAlign = LongLongAlign = 64; 4968 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4969 } 4970 void getTargetDefines(const LangOptions &Opts, 4971 MacroBuilder &Builder) const override { 4972 ARMleTargetInfo::getTargetDefines(Opts, Builder); 4973 Builder.defineMacro("_ARM_"); 4974 Builder.defineMacro("__CYGWIN__"); 4975 Builder.defineMacro("__CYGWIN32__"); 4976 DefineStd(Builder, "unix", Opts); 4977 if (Opts.CPlusPlus) 4978 Builder.defineMacro("_GNU_SOURCE"); 4979 } 4980 }; 4981 4982 class DarwinARMTargetInfo : 4983 public DarwinTargetInfo<ARMleTargetInfo> { 4984 protected: 4985 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4986 MacroBuilder &Builder) const override { 4987 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4988 } 4989 4990 public: 4991 DarwinARMTargetInfo(const llvm::Triple &Triple) 4992 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4993 HasAlignMac68kSupport = true; 4994 // iOS always has 64-bit atomic instructions. 4995 // FIXME: This should be based off of the target features in 4996 // ARMleTargetInfo. 4997 MaxAtomicInlineWidth = 64; 4998 4999 // Darwin on iOS uses a variant of the ARM C++ ABI. 5000 TheCXXABI.set(TargetCXXABI::iOS); 5001 } 5002 }; 5003 5004 class AArch64TargetInfo : public TargetInfo { 5005 virtual void setDataLayoutString() = 0; 5006 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5007 static const char *const GCCRegNames[]; 5008 5009 enum FPUModeEnum { 5010 FPUMode, 5011 NeonMode 5012 }; 5013 5014 unsigned FPU; 5015 unsigned CRC; 5016 unsigned Crypto; 5017 5018 static const Builtin::Info BuiltinInfo[]; 5019 5020 std::string ABI; 5021 5022 public: 5023 AArch64TargetInfo(const llvm::Triple &Triple) 5024 : TargetInfo(Triple), ABI("aapcs") { 5025 5026 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5027 WCharType = SignedInt; 5028 5029 // NetBSD apparently prefers consistency across ARM targets to consistency 5030 // across 64-bit targets. 5031 Int64Type = SignedLongLong; 5032 IntMaxType = SignedLongLong; 5033 } else { 5034 WCharType = UnsignedInt; 5035 Int64Type = SignedLong; 5036 IntMaxType = SignedLong; 5037 } 5038 5039 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5040 MaxVectorAlign = 128; 5041 MaxAtomicInlineWidth = 128; 5042 MaxAtomicPromoteWidth = 128; 5043 5044 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5045 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5046 5047 // {} in inline assembly are neon specifiers, not assembly variant 5048 // specifiers. 5049 NoAsmVariants = true; 5050 5051 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5052 // contributes to the alignment of the containing aggregate in the same way 5053 // a plain (non bit-field) member of that type would, without exception for 5054 // zero-sized or anonymous bit-fields." 5055 UseBitFieldTypeAlignment = true; 5056 UseZeroLengthBitfieldAlignment = true; 5057 5058 // AArch64 targets default to using the ARM C++ ABI. 5059 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5060 } 5061 5062 StringRef getABI() const override { return ABI; } 5063 bool setABI(const std::string &Name) override { 5064 if (Name != "aapcs" && Name != "darwinpcs") 5065 return false; 5066 5067 ABI = Name; 5068 return true; 5069 } 5070 5071 bool setCPU(const std::string &Name) override { 5072 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5073 .Case("generic", true) 5074 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5075 .Case("cyclone", true) 5076 .Default(false); 5077 return CPUKnown; 5078 } 5079 5080 void getTargetDefines(const LangOptions &Opts, 5081 MacroBuilder &Builder) const override { 5082 // Target identification. 5083 Builder.defineMacro("__aarch64__"); 5084 5085 // Target properties. 5086 Builder.defineMacro("_LP64"); 5087 Builder.defineMacro("__LP64__"); 5088 5089 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5090 Builder.defineMacro("__ARM_ACLE", "200"); 5091 Builder.defineMacro("__ARM_ARCH", "8"); 5092 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5093 5094 Builder.defineMacro("__ARM_64BIT_STATE"); 5095 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5096 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5097 5098 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5099 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5100 Builder.defineMacro("__ARM_FEATURE_FMA"); 5101 Builder.defineMacro("__ARM_FEATURE_DIV"); 5102 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5103 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5104 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5105 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5106 5107 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5108 5109 // 0xe implies support for half, single and double precision operations. 5110 Builder.defineMacro("__ARM_FP", "0xe"); 5111 5112 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5113 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5114 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5115 Builder.defineMacro("__ARM_FP16_ARGS"); 5116 5117 if (Opts.FastMath || Opts.FiniteMathOnly) 5118 Builder.defineMacro("__ARM_FP_FAST"); 5119 5120 if (Opts.C99 && !Opts.Freestanding) 5121 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5122 5123 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5124 5125 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5126 Opts.ShortEnums ? "1" : "4"); 5127 5128 if (FPU == NeonMode) { 5129 Builder.defineMacro("__ARM_NEON"); 5130 // 64-bit NEON supports half, single and double precision operations. 5131 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5132 } 5133 5134 if (CRC) 5135 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5136 5137 if (Crypto) 5138 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5139 5140 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5141 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5142 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5143 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5144 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5145 } 5146 5147 void getTargetBuiltins(const Builtin::Info *&Records, 5148 unsigned &NumRecords) const override { 5149 Records = BuiltinInfo; 5150 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5151 } 5152 5153 bool hasFeature(StringRef Feature) const override { 5154 return Feature == "aarch64" || 5155 Feature == "arm64" || 5156 Feature == "arm" || 5157 (Feature == "neon" && FPU == NeonMode); 5158 } 5159 5160 bool handleTargetFeatures(std::vector<std::string> &Features, 5161 DiagnosticsEngine &Diags) override { 5162 FPU = FPUMode; 5163 CRC = 0; 5164 Crypto = 0; 5165 for (const auto &Feature : Features) { 5166 if (Feature == "+neon") 5167 FPU = NeonMode; 5168 if (Feature == "+crc") 5169 CRC = 1; 5170 if (Feature == "+crypto") 5171 Crypto = 1; 5172 } 5173 5174 setDataLayoutString(); 5175 5176 return true; 5177 } 5178 5179 bool isCLZForZeroUndef() const override { return false; } 5180 5181 BuiltinVaListKind getBuiltinVaListKind() const override { 5182 return TargetInfo::AArch64ABIBuiltinVaList; 5183 } 5184 5185 void getGCCRegNames(const char *const *&Names, 5186 unsigned &NumNames) const override; 5187 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5188 unsigned &NumAliases) const override; 5189 5190 bool validateAsmConstraint(const char *&Name, 5191 TargetInfo::ConstraintInfo &Info) const override { 5192 switch (*Name) { 5193 default: 5194 return false; 5195 case 'w': // Floating point and SIMD registers (V0-V31) 5196 Info.setAllowsRegister(); 5197 return true; 5198 case 'I': // Constant that can be used with an ADD instruction 5199 case 'J': // Constant that can be used with a SUB instruction 5200 case 'K': // Constant that can be used with a 32-bit logical instruction 5201 case 'L': // Constant that can be used with a 64-bit logical instruction 5202 case 'M': // Constant that can be used as a 32-bit MOV immediate 5203 case 'N': // Constant that can be used as a 64-bit MOV immediate 5204 case 'Y': // Floating point constant zero 5205 case 'Z': // Integer constant zero 5206 return true; 5207 case 'Q': // A memory reference with base register and no offset 5208 Info.setAllowsMemory(); 5209 return true; 5210 case 'S': // A symbolic address 5211 Info.setAllowsRegister(); 5212 return true; 5213 case 'U': 5214 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5215 // Utf: A memory address suitable for ldp/stp in TF mode. 5216 // Usa: An absolute symbolic address. 5217 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5218 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5219 case 'z': // Zero register, wzr or xzr 5220 Info.setAllowsRegister(); 5221 return true; 5222 case 'x': // Floating point and SIMD registers (V0-V15) 5223 Info.setAllowsRegister(); 5224 return true; 5225 } 5226 return false; 5227 } 5228 5229 bool 5230 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5231 std::string &SuggestedModifier) const override { 5232 // Strip off constraint modifiers. 5233 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5234 Constraint = Constraint.substr(1); 5235 5236 switch (Constraint[0]) { 5237 default: 5238 return true; 5239 case 'z': 5240 case 'r': { 5241 switch (Modifier) { 5242 case 'x': 5243 case 'w': 5244 // For now assume that the person knows what they're 5245 // doing with the modifier. 5246 return true; 5247 default: 5248 // By default an 'r' constraint will be in the 'x' 5249 // registers. 5250 if (Size == 64) 5251 return true; 5252 5253 SuggestedModifier = "w"; 5254 return false; 5255 } 5256 } 5257 } 5258 } 5259 5260 const char *getClobbers() const override { return ""; } 5261 5262 int getEHDataRegisterNumber(unsigned RegNo) const override { 5263 if (RegNo == 0) 5264 return 0; 5265 if (RegNo == 1) 5266 return 1; 5267 return -1; 5268 } 5269 }; 5270 5271 const char *const AArch64TargetInfo::GCCRegNames[] = { 5272 // 32-bit Integer registers 5273 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5274 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5275 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5276 5277 // 64-bit Integer registers 5278 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5279 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5280 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5281 5282 // 32-bit floating point regsisters 5283 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5284 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5285 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5286 5287 // 64-bit floating point regsisters 5288 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5289 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5290 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5291 5292 // Vector registers 5293 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5294 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5295 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5296 }; 5297 5298 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5299 unsigned &NumNames) const { 5300 Names = GCCRegNames; 5301 NumNames = llvm::array_lengthof(GCCRegNames); 5302 } 5303 5304 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5305 { { "w31" }, "wsp" }, 5306 { { "x29" }, "fp" }, 5307 { { "x30" }, "lr" }, 5308 { { "x31" }, "sp" }, 5309 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5310 // don't want to substitute one of these for a different-sized one. 5311 }; 5312 5313 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5314 unsigned &NumAliases) const { 5315 Aliases = GCCRegAliases; 5316 NumAliases = llvm::array_lengthof(GCCRegAliases); 5317 } 5318 5319 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5320 #define BUILTIN(ID, TYPE, ATTRS) \ 5321 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5322 #include "clang/Basic/BuiltinsNEON.def" 5323 5324 #define BUILTIN(ID, TYPE, ATTRS) \ 5325 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5326 #include "clang/Basic/BuiltinsAArch64.def" 5327 }; 5328 5329 class AArch64leTargetInfo : public AArch64TargetInfo { 5330 void setDataLayoutString() override { 5331 if (getTriple().isOSBinFormatMachO()) 5332 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5333 else 5334 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5335 } 5336 5337 public: 5338 AArch64leTargetInfo(const llvm::Triple &Triple) 5339 : AArch64TargetInfo(Triple) { 5340 BigEndian = false; 5341 } 5342 void getTargetDefines(const LangOptions &Opts, 5343 MacroBuilder &Builder) const override { 5344 Builder.defineMacro("__AARCH64EL__"); 5345 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5346 } 5347 }; 5348 5349 class AArch64beTargetInfo : public AArch64TargetInfo { 5350 void setDataLayoutString() override { 5351 assert(!getTriple().isOSBinFormatMachO()); 5352 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5353 } 5354 5355 public: 5356 AArch64beTargetInfo(const llvm::Triple &Triple) 5357 : AArch64TargetInfo(Triple) { } 5358 void getTargetDefines(const LangOptions &Opts, 5359 MacroBuilder &Builder) const override { 5360 Builder.defineMacro("__AARCH64EB__"); 5361 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5362 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5363 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5364 } 5365 }; 5366 5367 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5368 protected: 5369 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5370 MacroBuilder &Builder) const override { 5371 Builder.defineMacro("__AARCH64_SIMD__"); 5372 Builder.defineMacro("__ARM64_ARCH_8__"); 5373 Builder.defineMacro("__ARM_NEON__"); 5374 Builder.defineMacro("__LITTLE_ENDIAN__"); 5375 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5376 Builder.defineMacro("__arm64", "1"); 5377 Builder.defineMacro("__arm64__", "1"); 5378 5379 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5380 } 5381 5382 public: 5383 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5384 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5385 Int64Type = SignedLongLong; 5386 WCharType = SignedInt; 5387 UseSignedCharForObjCBool = false; 5388 5389 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5390 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5391 5392 TheCXXABI.set(TargetCXXABI::iOS64); 5393 } 5394 5395 BuiltinVaListKind getBuiltinVaListKind() const override { 5396 return TargetInfo::CharPtrBuiltinVaList; 5397 } 5398 }; 5399 5400 // Hexagon abstract base class 5401 class HexagonTargetInfo : public TargetInfo { 5402 static const Builtin::Info BuiltinInfo[]; 5403 static const char * const GCCRegNames[]; 5404 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5405 std::string CPU; 5406 public: 5407 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5408 BigEndian = false; 5409 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5410 5411 // {} in inline assembly are packet specifiers, not assembly variant 5412 // specifiers. 5413 NoAsmVariants = true; 5414 } 5415 5416 void getTargetBuiltins(const Builtin::Info *&Records, 5417 unsigned &NumRecords) const override { 5418 Records = BuiltinInfo; 5419 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5420 } 5421 5422 bool validateAsmConstraint(const char *&Name, 5423 TargetInfo::ConstraintInfo &Info) const override { 5424 return true; 5425 } 5426 5427 void getTargetDefines(const LangOptions &Opts, 5428 MacroBuilder &Builder) const override; 5429 5430 bool hasFeature(StringRef Feature) const override { 5431 return Feature == "hexagon"; 5432 } 5433 5434 BuiltinVaListKind getBuiltinVaListKind() const override { 5435 return TargetInfo::CharPtrBuiltinVaList; 5436 } 5437 void getGCCRegNames(const char * const *&Names, 5438 unsigned &NumNames) const override; 5439 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5440 unsigned &NumAliases) const override; 5441 const char *getClobbers() const override { 5442 return ""; 5443 } 5444 5445 static const char *getHexagonCPUSuffix(StringRef Name) { 5446 return llvm::StringSwitch<const char*>(Name) 5447 .Case("hexagonv4", "4") 5448 .Case("hexagonv5", "5") 5449 .Default(nullptr); 5450 } 5451 5452 bool setCPU(const std::string &Name) override { 5453 if (!getHexagonCPUSuffix(Name)) 5454 return false; 5455 5456 CPU = Name; 5457 return true; 5458 } 5459 }; 5460 5461 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5462 MacroBuilder &Builder) const { 5463 Builder.defineMacro("qdsp6"); 5464 Builder.defineMacro("__qdsp6", "1"); 5465 Builder.defineMacro("__qdsp6__", "1"); 5466 5467 Builder.defineMacro("hexagon"); 5468 Builder.defineMacro("__hexagon", "1"); 5469 Builder.defineMacro("__hexagon__", "1"); 5470 5471 if(CPU == "hexagonv1") { 5472 Builder.defineMacro("__HEXAGON_V1__"); 5473 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5474 if(Opts.HexagonQdsp6Compat) { 5475 Builder.defineMacro("__QDSP6_V1__"); 5476 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5477 } 5478 } 5479 else if(CPU == "hexagonv2") { 5480 Builder.defineMacro("__HEXAGON_V2__"); 5481 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5482 if(Opts.HexagonQdsp6Compat) { 5483 Builder.defineMacro("__QDSP6_V2__"); 5484 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5485 } 5486 } 5487 else if(CPU == "hexagonv3") { 5488 Builder.defineMacro("__HEXAGON_V3__"); 5489 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5490 if(Opts.HexagonQdsp6Compat) { 5491 Builder.defineMacro("__QDSP6_V3__"); 5492 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5493 } 5494 } 5495 else if(CPU == "hexagonv4") { 5496 Builder.defineMacro("__HEXAGON_V4__"); 5497 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5498 if(Opts.HexagonQdsp6Compat) { 5499 Builder.defineMacro("__QDSP6_V4__"); 5500 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5501 } 5502 } 5503 else if(CPU == "hexagonv5") { 5504 Builder.defineMacro("__HEXAGON_V5__"); 5505 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5506 if(Opts.HexagonQdsp6Compat) { 5507 Builder.defineMacro("__QDSP6_V5__"); 5508 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5509 } 5510 } 5511 } 5512 5513 const char * const HexagonTargetInfo::GCCRegNames[] = { 5514 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5515 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5516 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5517 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5518 "p0", "p1", "p2", "p3", 5519 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5520 }; 5521 5522 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5523 unsigned &NumNames) const { 5524 Names = GCCRegNames; 5525 NumNames = llvm::array_lengthof(GCCRegNames); 5526 } 5527 5528 5529 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5530 { { "sp" }, "r29" }, 5531 { { "fp" }, "r30" }, 5532 { { "lr" }, "r31" }, 5533 }; 5534 5535 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5536 unsigned &NumAliases) const { 5537 Aliases = GCCRegAliases; 5538 NumAliases = llvm::array_lengthof(GCCRegAliases); 5539 } 5540 5541 5542 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5543 #define BUILTIN(ID, TYPE, ATTRS) \ 5544 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5545 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5546 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5547 #include "clang/Basic/BuiltinsHexagon.def" 5548 }; 5549 5550 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5551 class SparcTargetInfo : public TargetInfo { 5552 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5553 static const char * const GCCRegNames[]; 5554 bool SoftFloat; 5555 public: 5556 SparcTargetInfo(const llvm::Triple &Triple) 5557 : TargetInfo(Triple), SoftFloat(false) {} 5558 5559 bool handleTargetFeatures(std::vector<std::string> &Features, 5560 DiagnosticsEngine &Diags) override { 5561 // The backend doesn't actually handle soft float yet, but in case someone 5562 // is using the support for the front end continue to support it. 5563 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5564 if (Feature != Features.end()) { 5565 SoftFloat = true; 5566 Features.erase(Feature); 5567 } 5568 return true; 5569 } 5570 void getTargetDefines(const LangOptions &Opts, 5571 MacroBuilder &Builder) const override { 5572 DefineStd(Builder, "sparc", Opts); 5573 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5574 5575 if (SoftFloat) 5576 Builder.defineMacro("SOFT_FLOAT", "1"); 5577 } 5578 5579 bool hasFeature(StringRef Feature) const override { 5580 return llvm::StringSwitch<bool>(Feature) 5581 .Case("softfloat", SoftFloat) 5582 .Case("sparc", true) 5583 .Default(false); 5584 } 5585 5586 void getTargetBuiltins(const Builtin::Info *&Records, 5587 unsigned &NumRecords) const override { 5588 // FIXME: Implement! 5589 } 5590 BuiltinVaListKind getBuiltinVaListKind() const override { 5591 return TargetInfo::VoidPtrBuiltinVaList; 5592 } 5593 void getGCCRegNames(const char * const *&Names, 5594 unsigned &NumNames) const override; 5595 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5596 unsigned &NumAliases) const override; 5597 bool validateAsmConstraint(const char *&Name, 5598 TargetInfo::ConstraintInfo &info) const override { 5599 // FIXME: Implement! 5600 switch (*Name) { 5601 case 'I': // Signed 13-bit constant 5602 case 'J': // Zero 5603 case 'K': // 32-bit constant with the low 12 bits clear 5604 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5605 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5606 case 'N': // Same as 'K' but zext (required for SIMode) 5607 case 'O': // The constant 4096 5608 return true; 5609 } 5610 return false; 5611 } 5612 const char *getClobbers() const override { 5613 // FIXME: Implement! 5614 return ""; 5615 } 5616 }; 5617 5618 const char * const SparcTargetInfo::GCCRegNames[] = { 5619 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5620 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5621 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5622 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5623 }; 5624 5625 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5626 unsigned &NumNames) const { 5627 Names = GCCRegNames; 5628 NumNames = llvm::array_lengthof(GCCRegNames); 5629 } 5630 5631 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5632 { { "g0" }, "r0" }, 5633 { { "g1" }, "r1" }, 5634 { { "g2" }, "r2" }, 5635 { { "g3" }, "r3" }, 5636 { { "g4" }, "r4" }, 5637 { { "g5" }, "r5" }, 5638 { { "g6" }, "r6" }, 5639 { { "g7" }, "r7" }, 5640 { { "o0" }, "r8" }, 5641 { { "o1" }, "r9" }, 5642 { { "o2" }, "r10" }, 5643 { { "o3" }, "r11" }, 5644 { { "o4" }, "r12" }, 5645 { { "o5" }, "r13" }, 5646 { { "o6", "sp" }, "r14" }, 5647 { { "o7" }, "r15" }, 5648 { { "l0" }, "r16" }, 5649 { { "l1" }, "r17" }, 5650 { { "l2" }, "r18" }, 5651 { { "l3" }, "r19" }, 5652 { { "l4" }, "r20" }, 5653 { { "l5" }, "r21" }, 5654 { { "l6" }, "r22" }, 5655 { { "l7" }, "r23" }, 5656 { { "i0" }, "r24" }, 5657 { { "i1" }, "r25" }, 5658 { { "i2" }, "r26" }, 5659 { { "i3" }, "r27" }, 5660 { { "i4" }, "r28" }, 5661 { { "i5" }, "r29" }, 5662 { { "i6", "fp" }, "r30" }, 5663 { { "i7" }, "r31" }, 5664 }; 5665 5666 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5667 unsigned &NumAliases) const { 5668 Aliases = GCCRegAliases; 5669 NumAliases = llvm::array_lengthof(GCCRegAliases); 5670 } 5671 5672 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5673 class SparcV8TargetInfo : public SparcTargetInfo { 5674 public: 5675 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5676 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5677 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5678 switch (getTriple().getOS()) { 5679 default: 5680 SizeType = UnsignedInt; 5681 IntPtrType = SignedInt; 5682 PtrDiffType = SignedInt; 5683 break; 5684 case llvm::Triple::NetBSD: 5685 case llvm::Triple::OpenBSD: 5686 SizeType = UnsignedLong; 5687 IntPtrType = SignedLong; 5688 PtrDiffType = SignedLong; 5689 break; 5690 } 5691 } 5692 5693 void getTargetDefines(const LangOptions &Opts, 5694 MacroBuilder &Builder) const override { 5695 SparcTargetInfo::getTargetDefines(Opts, Builder); 5696 Builder.defineMacro("__sparcv8"); 5697 } 5698 }; 5699 5700 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5701 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5702 public: 5703 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5704 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5705 BigEndian = false; 5706 } 5707 }; 5708 5709 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5710 class SparcV9TargetInfo : public SparcTargetInfo { 5711 public: 5712 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5713 // FIXME: Support Sparc quad-precision long double? 5714 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5715 // This is an LP64 platform. 5716 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5717 5718 // OpenBSD uses long long for int64_t and intmax_t. 5719 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5720 IntMaxType = SignedLongLong; 5721 else 5722 IntMaxType = SignedLong; 5723 Int64Type = IntMaxType; 5724 5725 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5726 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5727 LongDoubleWidth = 128; 5728 LongDoubleAlign = 128; 5729 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5730 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5731 } 5732 5733 void getTargetDefines(const LangOptions &Opts, 5734 MacroBuilder &Builder) const override { 5735 SparcTargetInfo::getTargetDefines(Opts, Builder); 5736 Builder.defineMacro("__sparcv9"); 5737 Builder.defineMacro("__arch64__"); 5738 // Solaris doesn't need these variants, but the BSDs do. 5739 if (getTriple().getOS() != llvm::Triple::Solaris) { 5740 Builder.defineMacro("__sparc64__"); 5741 Builder.defineMacro("__sparc_v9__"); 5742 Builder.defineMacro("__sparcv9__"); 5743 } 5744 } 5745 5746 bool setCPU(const std::string &Name) override { 5747 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5748 .Case("v9", true) 5749 .Case("ultrasparc", true) 5750 .Case("ultrasparc3", true) 5751 .Case("niagara", true) 5752 .Case("niagara2", true) 5753 .Case("niagara3", true) 5754 .Case("niagara4", true) 5755 .Default(false); 5756 5757 // No need to store the CPU yet. There aren't any CPU-specific 5758 // macros to define. 5759 return CPUKnown; 5760 } 5761 }; 5762 5763 class SystemZTargetInfo : public TargetInfo { 5764 static const Builtin::Info BuiltinInfo[]; 5765 static const char *const GCCRegNames[]; 5766 std::string CPU; 5767 bool HasTransactionalExecution; 5768 bool HasVector; 5769 5770 public: 5771 SystemZTargetInfo(const llvm::Triple &Triple) 5772 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5773 IntMaxType = SignedLong; 5774 Int64Type = SignedLong; 5775 TLSSupported = true; 5776 IntWidth = IntAlign = 32; 5777 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5778 PointerWidth = PointerAlign = 64; 5779 LongDoubleWidth = 128; 5780 LongDoubleAlign = 64; 5781 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5782 DefaultAlignForAttributeAligned = 64; 5783 MinGlobalAlign = 16; 5784 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5785 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5786 } 5787 void getTargetDefines(const LangOptions &Opts, 5788 MacroBuilder &Builder) const override { 5789 Builder.defineMacro("__s390__"); 5790 Builder.defineMacro("__s390x__"); 5791 Builder.defineMacro("__zarch__"); 5792 Builder.defineMacro("__LONG_DOUBLE_128__"); 5793 if (HasTransactionalExecution) 5794 Builder.defineMacro("__HTM__"); 5795 if (Opts.ZVector) 5796 Builder.defineMacro("__VEC__", "10301"); 5797 } 5798 void getTargetBuiltins(const Builtin::Info *&Records, 5799 unsigned &NumRecords) const override { 5800 Records = BuiltinInfo; 5801 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5802 } 5803 5804 void getGCCRegNames(const char *const *&Names, 5805 unsigned &NumNames) const override; 5806 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5807 unsigned &NumAliases) const override { 5808 // No aliases. 5809 Aliases = nullptr; 5810 NumAliases = 0; 5811 } 5812 bool validateAsmConstraint(const char *&Name, 5813 TargetInfo::ConstraintInfo &info) const override; 5814 const char *getClobbers() const override { 5815 // FIXME: Is this really right? 5816 return ""; 5817 } 5818 BuiltinVaListKind getBuiltinVaListKind() const override { 5819 return TargetInfo::SystemZBuiltinVaList; 5820 } 5821 bool setCPU(const std::string &Name) override { 5822 CPU = Name; 5823 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5824 .Case("z10", true) 5825 .Case("z196", true) 5826 .Case("zEC12", true) 5827 .Case("z13", true) 5828 .Default(false); 5829 5830 return CPUKnown; 5831 } 5832 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5833 StringRef CPU, 5834 std::vector<std::string> &FeaturesVec) const override { 5835 if (CPU == "zEC12") 5836 Features["transactional-execution"] = true; 5837 if (CPU == "z13") { 5838 Features["transactional-execution"] = true; 5839 Features["vector"] = true; 5840 } 5841 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5842 } 5843 5844 bool handleTargetFeatures(std::vector<std::string> &Features, 5845 DiagnosticsEngine &Diags) override { 5846 HasTransactionalExecution = false; 5847 for (const auto &Feature : Features) { 5848 if (Feature == "+transactional-execution") 5849 HasTransactionalExecution = true; 5850 else if (Feature == "+vector") 5851 HasVector = true; 5852 } 5853 // If we use the vector ABI, vector types are 64-bit aligned. 5854 if (HasVector) { 5855 MaxVectorAlign = 64; 5856 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5857 "-v128:64-a:8:16-n32:64"; 5858 } 5859 return true; 5860 } 5861 5862 bool hasFeature(StringRef Feature) const override { 5863 return llvm::StringSwitch<bool>(Feature) 5864 .Case("systemz", true) 5865 .Case("htm", HasTransactionalExecution) 5866 .Case("vx", HasVector) 5867 .Default(false); 5868 } 5869 5870 StringRef getABI() const override { 5871 if (HasVector) 5872 return "vector"; 5873 return ""; 5874 } 5875 5876 bool useFloat128ManglingForLongDouble() const override { 5877 return true; 5878 } 5879 }; 5880 5881 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5882 #define BUILTIN(ID, TYPE, ATTRS) \ 5883 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5884 #include "clang/Basic/BuiltinsSystemZ.def" 5885 }; 5886 5887 const char *const SystemZTargetInfo::GCCRegNames[] = { 5888 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5889 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5890 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5891 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5892 }; 5893 5894 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5895 unsigned &NumNames) const { 5896 Names = GCCRegNames; 5897 NumNames = llvm::array_lengthof(GCCRegNames); 5898 } 5899 5900 bool SystemZTargetInfo:: 5901 validateAsmConstraint(const char *&Name, 5902 TargetInfo::ConstraintInfo &Info) const { 5903 switch (*Name) { 5904 default: 5905 return false; 5906 5907 case 'a': // Address register 5908 case 'd': // Data register (equivalent to 'r') 5909 case 'f': // Floating-point register 5910 Info.setAllowsRegister(); 5911 return true; 5912 5913 case 'I': // Unsigned 8-bit constant 5914 case 'J': // Unsigned 12-bit constant 5915 case 'K': // Signed 16-bit constant 5916 case 'L': // Signed 20-bit displacement (on all targets we support) 5917 case 'M': // 0x7fffffff 5918 return true; 5919 5920 case 'Q': // Memory with base and unsigned 12-bit displacement 5921 case 'R': // Likewise, plus an index 5922 case 'S': // Memory with base and signed 20-bit displacement 5923 case 'T': // Likewise, plus an index 5924 Info.setAllowsMemory(); 5925 return true; 5926 } 5927 } 5928 5929 class MSP430TargetInfo : public TargetInfo { 5930 static const char * const GCCRegNames[]; 5931 public: 5932 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5933 BigEndian = false; 5934 TLSSupported = false; 5935 IntWidth = 16; IntAlign = 16; 5936 LongWidth = 32; LongLongWidth = 64; 5937 LongAlign = LongLongAlign = 16; 5938 PointerWidth = 16; PointerAlign = 16; 5939 SuitableAlign = 16; 5940 SizeType = UnsignedInt; 5941 IntMaxType = SignedLongLong; 5942 IntPtrType = SignedInt; 5943 PtrDiffType = SignedInt; 5944 SigAtomicType = SignedLong; 5945 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5946 } 5947 void getTargetDefines(const LangOptions &Opts, 5948 MacroBuilder &Builder) const override { 5949 Builder.defineMacro("MSP430"); 5950 Builder.defineMacro("__MSP430__"); 5951 // FIXME: defines for different 'flavours' of MCU 5952 } 5953 void getTargetBuiltins(const Builtin::Info *&Records, 5954 unsigned &NumRecords) const override { 5955 // FIXME: Implement. 5956 Records = nullptr; 5957 NumRecords = 0; 5958 } 5959 bool hasFeature(StringRef Feature) const override { 5960 return Feature == "msp430"; 5961 } 5962 void getGCCRegNames(const char * const *&Names, 5963 unsigned &NumNames) const override; 5964 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5965 unsigned &NumAliases) const override { 5966 // No aliases. 5967 Aliases = nullptr; 5968 NumAliases = 0; 5969 } 5970 bool 5971 validateAsmConstraint(const char *&Name, 5972 TargetInfo::ConstraintInfo &info) const override { 5973 // FIXME: implement 5974 switch (*Name) { 5975 case 'K': // the constant 1 5976 case 'L': // constant -1^20 .. 1^19 5977 case 'M': // constant 1-4: 5978 return true; 5979 } 5980 // No target constraints for now. 5981 return false; 5982 } 5983 const char *getClobbers() const override { 5984 // FIXME: Is this really right? 5985 return ""; 5986 } 5987 BuiltinVaListKind getBuiltinVaListKind() const override { 5988 // FIXME: implement 5989 return TargetInfo::CharPtrBuiltinVaList; 5990 } 5991 }; 5992 5993 const char * const MSP430TargetInfo::GCCRegNames[] = { 5994 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5995 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5996 }; 5997 5998 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5999 unsigned &NumNames) const { 6000 Names = GCCRegNames; 6001 NumNames = llvm::array_lengthof(GCCRegNames); 6002 } 6003 6004 // LLVM and Clang cannot be used directly to output native binaries for 6005 // target, but is used to compile C code to llvm bitcode with correct 6006 // type and alignment information. 6007 // 6008 // TCE uses the llvm bitcode as input and uses it for generating customized 6009 // target processor and program binary. TCE co-design environment is 6010 // publicly available in http://tce.cs.tut.fi 6011 6012 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6013 3, // opencl_global 6014 4, // opencl_local 6015 5, // opencl_constant 6016 // FIXME: generic has to be added to the target 6017 0, // opencl_generic 6018 0, // cuda_device 6019 0, // cuda_constant 6020 0 // cuda_shared 6021 }; 6022 6023 class TCETargetInfo : public TargetInfo{ 6024 public: 6025 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6026 TLSSupported = false; 6027 IntWidth = 32; 6028 LongWidth = LongLongWidth = 32; 6029 PointerWidth = 32; 6030 IntAlign = 32; 6031 LongAlign = LongLongAlign = 32; 6032 PointerAlign = 32; 6033 SuitableAlign = 32; 6034 SizeType = UnsignedInt; 6035 IntMaxType = SignedLong; 6036 IntPtrType = SignedInt; 6037 PtrDiffType = SignedInt; 6038 FloatWidth = 32; 6039 FloatAlign = 32; 6040 DoubleWidth = 32; 6041 DoubleAlign = 32; 6042 LongDoubleWidth = 32; 6043 LongDoubleAlign = 32; 6044 FloatFormat = &llvm::APFloat::IEEEsingle; 6045 DoubleFormat = &llvm::APFloat::IEEEsingle; 6046 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6047 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6048 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6049 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6050 UseAddrSpaceMapMangling = true; 6051 } 6052 6053 void getTargetDefines(const LangOptions &Opts, 6054 MacroBuilder &Builder) const override { 6055 DefineStd(Builder, "tce", Opts); 6056 Builder.defineMacro("__TCE__"); 6057 Builder.defineMacro("__TCE_V1__"); 6058 } 6059 bool hasFeature(StringRef Feature) const override { 6060 return Feature == "tce"; 6061 } 6062 6063 void getTargetBuiltins(const Builtin::Info *&Records, 6064 unsigned &NumRecords) const override {} 6065 const char *getClobbers() const override { 6066 return ""; 6067 } 6068 BuiltinVaListKind getBuiltinVaListKind() const override { 6069 return TargetInfo::VoidPtrBuiltinVaList; 6070 } 6071 void getGCCRegNames(const char * const *&Names, 6072 unsigned &NumNames) const override {} 6073 bool validateAsmConstraint(const char *&Name, 6074 TargetInfo::ConstraintInfo &info) const override{ 6075 return true; 6076 } 6077 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6078 unsigned &NumAliases) const override {} 6079 }; 6080 6081 class BPFTargetInfo : public TargetInfo { 6082 public: 6083 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6084 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6085 SizeType = UnsignedLong; 6086 PtrDiffType = SignedLong; 6087 IntPtrType = SignedLong; 6088 IntMaxType = SignedLong; 6089 Int64Type = SignedLong; 6090 RegParmMax = 5; 6091 if (Triple.getArch() == llvm::Triple::bpfeb) { 6092 BigEndian = true; 6093 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6094 } else { 6095 BigEndian = false; 6096 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6097 } 6098 MaxAtomicPromoteWidth = 64; 6099 MaxAtomicInlineWidth = 64; 6100 TLSSupported = false; 6101 } 6102 void getTargetDefines(const LangOptions &Opts, 6103 MacroBuilder &Builder) const override { 6104 DefineStd(Builder, "bpf", Opts); 6105 Builder.defineMacro("__BPF__"); 6106 } 6107 bool hasFeature(StringRef Feature) const override { 6108 return Feature == "bpf"; 6109 } 6110 6111 void getTargetBuiltins(const Builtin::Info *&Records, 6112 unsigned &NumRecords) const override {} 6113 const char *getClobbers() const override { 6114 return ""; 6115 } 6116 BuiltinVaListKind getBuiltinVaListKind() const override { 6117 return TargetInfo::VoidPtrBuiltinVaList; 6118 } 6119 void getGCCRegNames(const char * const *&Names, 6120 unsigned &NumNames) const override { 6121 Names = nullptr; 6122 NumNames = 0; 6123 } 6124 bool validateAsmConstraint(const char *&Name, 6125 TargetInfo::ConstraintInfo &info) const override { 6126 return true; 6127 } 6128 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6129 unsigned &NumAliases) const override { 6130 Aliases = nullptr; 6131 NumAliases = 0; 6132 } 6133 }; 6134 6135 class MipsTargetInfoBase : public TargetInfo { 6136 virtual void setDataLayoutString() = 0; 6137 6138 static const Builtin::Info BuiltinInfo[]; 6139 std::string CPU; 6140 bool IsMips16; 6141 bool IsMicromips; 6142 bool IsNan2008; 6143 bool IsSingleFloat; 6144 enum MipsFloatABI { 6145 HardFloat, SoftFloat 6146 } FloatABI; 6147 enum DspRevEnum { 6148 NoDSP, DSP1, DSP2 6149 } DspRev; 6150 bool HasMSA; 6151 6152 protected: 6153 bool HasFP64; 6154 std::string ABI; 6155 6156 public: 6157 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6158 const std::string &CPUStr) 6159 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6160 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6161 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6162 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6163 } 6164 6165 bool isNaN2008Default() const { 6166 return CPU == "mips32r6" || CPU == "mips64r6"; 6167 } 6168 6169 bool isFP64Default() const { 6170 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6171 } 6172 6173 bool isNan2008() const override { 6174 return IsNan2008; 6175 } 6176 6177 StringRef getABI() const override { return ABI; } 6178 bool setCPU(const std::string &Name) override { 6179 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6180 getTriple().getArch() == llvm::Triple::mipsel; 6181 CPU = Name; 6182 return llvm::StringSwitch<bool>(Name) 6183 .Case("mips1", IsMips32) 6184 .Case("mips2", IsMips32) 6185 .Case("mips3", true) 6186 .Case("mips4", true) 6187 .Case("mips5", true) 6188 .Case("mips32", IsMips32) 6189 .Case("mips32r2", IsMips32) 6190 .Case("mips32r3", IsMips32) 6191 .Case("mips32r5", IsMips32) 6192 .Case("mips32r6", IsMips32) 6193 .Case("mips64", true) 6194 .Case("mips64r2", true) 6195 .Case("mips64r3", true) 6196 .Case("mips64r5", true) 6197 .Case("mips64r6", true) 6198 .Case("octeon", true) 6199 .Default(false); 6200 } 6201 const std::string& getCPU() const { return CPU; } 6202 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6203 StringRef CPU, 6204 std::vector<std::string> &FeaturesVec) const override { 6205 if (CPU == "octeon") 6206 Features["mips64r2"] = Features["cnmips"] = true; 6207 else 6208 Features[CPU] = true; 6209 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6210 } 6211 6212 void getTargetDefines(const LangOptions &Opts, 6213 MacroBuilder &Builder) const override { 6214 Builder.defineMacro("__mips__"); 6215 Builder.defineMacro("_mips"); 6216 if (Opts.GNUMode) 6217 Builder.defineMacro("mips"); 6218 6219 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6220 6221 switch (FloatABI) { 6222 case HardFloat: 6223 Builder.defineMacro("__mips_hard_float", Twine(1)); 6224 break; 6225 case SoftFloat: 6226 Builder.defineMacro("__mips_soft_float", Twine(1)); 6227 break; 6228 } 6229 6230 if (IsSingleFloat) 6231 Builder.defineMacro("__mips_single_float", Twine(1)); 6232 6233 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6234 Builder.defineMacro("_MIPS_FPSET", 6235 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6236 6237 if (IsMips16) 6238 Builder.defineMacro("__mips16", Twine(1)); 6239 6240 if (IsMicromips) 6241 Builder.defineMacro("__mips_micromips", Twine(1)); 6242 6243 if (IsNan2008) 6244 Builder.defineMacro("__mips_nan2008", Twine(1)); 6245 6246 switch (DspRev) { 6247 default: 6248 break; 6249 case DSP1: 6250 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6251 Builder.defineMacro("__mips_dsp", Twine(1)); 6252 break; 6253 case DSP2: 6254 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6255 Builder.defineMacro("__mips_dspr2", Twine(1)); 6256 Builder.defineMacro("__mips_dsp", Twine(1)); 6257 break; 6258 } 6259 6260 if (HasMSA) 6261 Builder.defineMacro("__mips_msa", Twine(1)); 6262 6263 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6264 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6265 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6266 6267 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6268 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6269 } 6270 6271 void getTargetBuiltins(const Builtin::Info *&Records, 6272 unsigned &NumRecords) const override { 6273 Records = BuiltinInfo; 6274 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6275 } 6276 bool hasFeature(StringRef Feature) const override { 6277 return llvm::StringSwitch<bool>(Feature) 6278 .Case("mips", true) 6279 .Case("fp64", HasFP64) 6280 .Default(false); 6281 } 6282 BuiltinVaListKind getBuiltinVaListKind() const override { 6283 return TargetInfo::VoidPtrBuiltinVaList; 6284 } 6285 void getGCCRegNames(const char * const *&Names, 6286 unsigned &NumNames) const override { 6287 static const char *const GCCRegNames[] = { 6288 // CPU register names 6289 // Must match second column of GCCRegAliases 6290 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6291 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6292 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6293 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6294 // Floating point register names 6295 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6296 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6297 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6298 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6299 // Hi/lo and condition register names 6300 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6301 "$fcc5","$fcc6","$fcc7", 6302 // MSA register names 6303 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6304 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6305 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6306 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6307 // MSA control register names 6308 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6309 "$msarequest", "$msamap", "$msaunmap" 6310 }; 6311 Names = GCCRegNames; 6312 NumNames = llvm::array_lengthof(GCCRegNames); 6313 } 6314 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6315 unsigned &NumAliases) const override = 0; 6316 bool validateAsmConstraint(const char *&Name, 6317 TargetInfo::ConstraintInfo &Info) const override { 6318 switch (*Name) { 6319 default: 6320 return false; 6321 case 'r': // CPU registers. 6322 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6323 case 'y': // Equivalent to "r", backward compatibility only. 6324 case 'f': // floating-point registers. 6325 case 'c': // $25 for indirect jumps 6326 case 'l': // lo register 6327 case 'x': // hilo register pair 6328 Info.setAllowsRegister(); 6329 return true; 6330 case 'I': // Signed 16-bit constant 6331 case 'J': // Integer 0 6332 case 'K': // Unsigned 16-bit constant 6333 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6334 case 'M': // Constants not loadable via lui, addiu, or ori 6335 case 'N': // Constant -1 to -65535 6336 case 'O': // A signed 15-bit constant 6337 case 'P': // A constant between 1 go 65535 6338 return true; 6339 case 'R': // An address that can be used in a non-macro load or store 6340 Info.setAllowsMemory(); 6341 return true; 6342 case 'Z': 6343 if (Name[1] == 'C') { // An address usable by ll, and sc. 6344 Info.setAllowsMemory(); 6345 Name++; // Skip over 'Z'. 6346 return true; 6347 } 6348 return false; 6349 } 6350 } 6351 6352 std::string convertConstraint(const char *&Constraint) const override { 6353 std::string R; 6354 switch (*Constraint) { 6355 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6356 if (Constraint[1] == 'C') { 6357 R = std::string("^") + std::string(Constraint, 2); 6358 Constraint++; 6359 return R; 6360 } 6361 break; 6362 } 6363 return TargetInfo::convertConstraint(Constraint); 6364 } 6365 6366 const char *getClobbers() const override { 6367 // In GCC, $1 is not widely used in generated code (it's used only in a few 6368 // specific situations), so there is no real need for users to add it to 6369 // the clobbers list if they want to use it in their inline assembly code. 6370 // 6371 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6372 // code generation, so using it in inline assembly without adding it to the 6373 // clobbers list can cause conflicts between the inline assembly code and 6374 // the surrounding generated code. 6375 // 6376 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6377 // operands, which will conflict with the ".set at" assembler option (which 6378 // we use only for inline assembly, in order to maintain compatibility with 6379 // GCC) and will also conflict with the user's usage of $1. 6380 // 6381 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6382 // register for generated code is to automatically clobber $1 for all inline 6383 // assembly code. 6384 // 6385 // FIXME: We should automatically clobber $1 only for inline assembly code 6386 // which actually uses it. This would allow LLVM to use $1 for inline 6387 // assembly operands if the user's assembly code doesn't use it. 6388 return "~{$1}"; 6389 } 6390 6391 bool handleTargetFeatures(std::vector<std::string> &Features, 6392 DiagnosticsEngine &Diags) override { 6393 IsMips16 = false; 6394 IsMicromips = false; 6395 IsNan2008 = isNaN2008Default(); 6396 IsSingleFloat = false; 6397 FloatABI = HardFloat; 6398 DspRev = NoDSP; 6399 HasFP64 = isFP64Default(); 6400 6401 for (const auto &Feature : Features) { 6402 if (Feature == "+single-float") 6403 IsSingleFloat = true; 6404 else if (Feature == "+soft-float") 6405 FloatABI = SoftFloat; 6406 else if (Feature == "+mips16") 6407 IsMips16 = true; 6408 else if (Feature == "+micromips") 6409 IsMicromips = true; 6410 else if (Feature == "+dsp") 6411 DspRev = std::max(DspRev, DSP1); 6412 else if (Feature == "+dspr2") 6413 DspRev = std::max(DspRev, DSP2); 6414 else if (Feature == "+msa") 6415 HasMSA = true; 6416 else if (Feature == "+fp64") 6417 HasFP64 = true; 6418 else if (Feature == "-fp64") 6419 HasFP64 = false; 6420 else if (Feature == "+nan2008") 6421 IsNan2008 = true; 6422 else if (Feature == "-nan2008") 6423 IsNan2008 = false; 6424 } 6425 6426 setDataLayoutString(); 6427 6428 return true; 6429 } 6430 6431 int getEHDataRegisterNumber(unsigned RegNo) const override { 6432 if (RegNo == 0) return 4; 6433 if (RegNo == 1) return 5; 6434 return -1; 6435 } 6436 6437 bool isCLZForZeroUndef() const override { return false; } 6438 }; 6439 6440 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6441 #define BUILTIN(ID, TYPE, ATTRS) \ 6442 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6443 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6444 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6445 #include "clang/Basic/BuiltinsMips.def" 6446 }; 6447 6448 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6449 public: 6450 Mips32TargetInfoBase(const llvm::Triple &Triple) 6451 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6452 SizeType = UnsignedInt; 6453 PtrDiffType = SignedInt; 6454 Int64Type = SignedLongLong; 6455 IntMaxType = Int64Type; 6456 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6457 } 6458 bool setABI(const std::string &Name) override { 6459 if (Name == "o32" || Name == "eabi") { 6460 ABI = Name; 6461 return true; 6462 } 6463 return false; 6464 } 6465 void getTargetDefines(const LangOptions &Opts, 6466 MacroBuilder &Builder) const override { 6467 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6468 6469 Builder.defineMacro("__mips", "32"); 6470 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6471 6472 const std::string& CPUStr = getCPU(); 6473 if (CPUStr == "mips32") 6474 Builder.defineMacro("__mips_isa_rev", "1"); 6475 else if (CPUStr == "mips32r2") 6476 Builder.defineMacro("__mips_isa_rev", "2"); 6477 else if (CPUStr == "mips32r3") 6478 Builder.defineMacro("__mips_isa_rev", "3"); 6479 else if (CPUStr == "mips32r5") 6480 Builder.defineMacro("__mips_isa_rev", "5"); 6481 else if (CPUStr == "mips32r6") 6482 Builder.defineMacro("__mips_isa_rev", "6"); 6483 6484 if (ABI == "o32") { 6485 Builder.defineMacro("__mips_o32"); 6486 Builder.defineMacro("_ABIO32", "1"); 6487 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6488 } 6489 else if (ABI == "eabi") 6490 Builder.defineMacro("__mips_eabi"); 6491 else 6492 llvm_unreachable("Invalid ABI for Mips32."); 6493 } 6494 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6495 unsigned &NumAliases) const override { 6496 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6497 { { "at" }, "$1" }, 6498 { { "v0" }, "$2" }, 6499 { { "v1" }, "$3" }, 6500 { { "a0" }, "$4" }, 6501 { { "a1" }, "$5" }, 6502 { { "a2" }, "$6" }, 6503 { { "a3" }, "$7" }, 6504 { { "t0" }, "$8" }, 6505 { { "t1" }, "$9" }, 6506 { { "t2" }, "$10" }, 6507 { { "t3" }, "$11" }, 6508 { { "t4" }, "$12" }, 6509 { { "t5" }, "$13" }, 6510 { { "t6" }, "$14" }, 6511 { { "t7" }, "$15" }, 6512 { { "s0" }, "$16" }, 6513 { { "s1" }, "$17" }, 6514 { { "s2" }, "$18" }, 6515 { { "s3" }, "$19" }, 6516 { { "s4" }, "$20" }, 6517 { { "s5" }, "$21" }, 6518 { { "s6" }, "$22" }, 6519 { { "s7" }, "$23" }, 6520 { { "t8" }, "$24" }, 6521 { { "t9" }, "$25" }, 6522 { { "k0" }, "$26" }, 6523 { { "k1" }, "$27" }, 6524 { { "gp" }, "$28" }, 6525 { { "sp","$sp" }, "$29" }, 6526 { { "fp","$fp" }, "$30" }, 6527 { { "ra" }, "$31" } 6528 }; 6529 Aliases = GCCRegAliases; 6530 NumAliases = llvm::array_lengthof(GCCRegAliases); 6531 } 6532 }; 6533 6534 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6535 void setDataLayoutString() override { 6536 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6537 } 6538 6539 public: 6540 Mips32EBTargetInfo(const llvm::Triple &Triple) 6541 : Mips32TargetInfoBase(Triple) { 6542 } 6543 void getTargetDefines(const LangOptions &Opts, 6544 MacroBuilder &Builder) const override { 6545 DefineStd(Builder, "MIPSEB", Opts); 6546 Builder.defineMacro("_MIPSEB"); 6547 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6548 } 6549 }; 6550 6551 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6552 void setDataLayoutString() override { 6553 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6554 } 6555 6556 public: 6557 Mips32ELTargetInfo(const llvm::Triple &Triple) 6558 : Mips32TargetInfoBase(Triple) { 6559 BigEndian = false; 6560 } 6561 void getTargetDefines(const LangOptions &Opts, 6562 MacroBuilder &Builder) const override { 6563 DefineStd(Builder, "MIPSEL", Opts); 6564 Builder.defineMacro("_MIPSEL"); 6565 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6566 } 6567 }; 6568 6569 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6570 public: 6571 Mips64TargetInfoBase(const llvm::Triple &Triple) 6572 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6573 LongDoubleWidth = LongDoubleAlign = 128; 6574 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6575 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6576 LongDoubleWidth = LongDoubleAlign = 64; 6577 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6578 } 6579 setN64ABITypes(); 6580 SuitableAlign = 128; 6581 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6582 } 6583 6584 void setN64ABITypes() { 6585 LongWidth = LongAlign = 64; 6586 PointerWidth = PointerAlign = 64; 6587 SizeType = UnsignedLong; 6588 PtrDiffType = SignedLong; 6589 Int64Type = SignedLong; 6590 IntMaxType = Int64Type; 6591 } 6592 6593 void setN32ABITypes() { 6594 LongWidth = LongAlign = 32; 6595 PointerWidth = PointerAlign = 32; 6596 SizeType = UnsignedInt; 6597 PtrDiffType = SignedInt; 6598 Int64Type = SignedLongLong; 6599 IntMaxType = Int64Type; 6600 } 6601 6602 bool setABI(const std::string &Name) override { 6603 if (Name == "n32") { 6604 setN32ABITypes(); 6605 ABI = Name; 6606 return true; 6607 } 6608 if (Name == "n64") { 6609 setN64ABITypes(); 6610 ABI = Name; 6611 return true; 6612 } 6613 return false; 6614 } 6615 6616 void getTargetDefines(const LangOptions &Opts, 6617 MacroBuilder &Builder) const override { 6618 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6619 6620 Builder.defineMacro("__mips", "64"); 6621 Builder.defineMacro("__mips64"); 6622 Builder.defineMacro("__mips64__"); 6623 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6624 6625 const std::string& CPUStr = getCPU(); 6626 if (CPUStr == "mips64") 6627 Builder.defineMacro("__mips_isa_rev", "1"); 6628 else if (CPUStr == "mips64r2") 6629 Builder.defineMacro("__mips_isa_rev", "2"); 6630 else if (CPUStr == "mips64r3") 6631 Builder.defineMacro("__mips_isa_rev", "3"); 6632 else if (CPUStr == "mips64r5") 6633 Builder.defineMacro("__mips_isa_rev", "5"); 6634 else if (CPUStr == "mips64r6") 6635 Builder.defineMacro("__mips_isa_rev", "6"); 6636 6637 if (ABI == "n32") { 6638 Builder.defineMacro("__mips_n32"); 6639 Builder.defineMacro("_ABIN32", "2"); 6640 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6641 } 6642 else if (ABI == "n64") { 6643 Builder.defineMacro("__mips_n64"); 6644 Builder.defineMacro("_ABI64", "3"); 6645 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6646 } 6647 else 6648 llvm_unreachable("Invalid ABI for Mips64."); 6649 } 6650 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6651 unsigned &NumAliases) const override { 6652 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6653 { { "at" }, "$1" }, 6654 { { "v0" }, "$2" }, 6655 { { "v1" }, "$3" }, 6656 { { "a0" }, "$4" }, 6657 { { "a1" }, "$5" }, 6658 { { "a2" }, "$6" }, 6659 { { "a3" }, "$7" }, 6660 { { "a4" }, "$8" }, 6661 { { "a5" }, "$9" }, 6662 { { "a6" }, "$10" }, 6663 { { "a7" }, "$11" }, 6664 { { "t0" }, "$12" }, 6665 { { "t1" }, "$13" }, 6666 { { "t2" }, "$14" }, 6667 { { "t3" }, "$15" }, 6668 { { "s0" }, "$16" }, 6669 { { "s1" }, "$17" }, 6670 { { "s2" }, "$18" }, 6671 { { "s3" }, "$19" }, 6672 { { "s4" }, "$20" }, 6673 { { "s5" }, "$21" }, 6674 { { "s6" }, "$22" }, 6675 { { "s7" }, "$23" }, 6676 { { "t8" }, "$24" }, 6677 { { "t9" }, "$25" }, 6678 { { "k0" }, "$26" }, 6679 { { "k1" }, "$27" }, 6680 { { "gp" }, "$28" }, 6681 { { "sp","$sp" }, "$29" }, 6682 { { "fp","$fp" }, "$30" }, 6683 { { "ra" }, "$31" } 6684 }; 6685 Aliases = GCCRegAliases; 6686 NumAliases = llvm::array_lengthof(GCCRegAliases); 6687 } 6688 6689 bool hasInt128Type() const override { return true; } 6690 }; 6691 6692 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6693 void setDataLayoutString() override { 6694 if (ABI == "n32") 6695 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6696 else 6697 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6698 6699 } 6700 6701 public: 6702 Mips64EBTargetInfo(const llvm::Triple &Triple) 6703 : Mips64TargetInfoBase(Triple) {} 6704 void getTargetDefines(const LangOptions &Opts, 6705 MacroBuilder &Builder) const override { 6706 DefineStd(Builder, "MIPSEB", Opts); 6707 Builder.defineMacro("_MIPSEB"); 6708 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6709 } 6710 }; 6711 6712 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6713 void setDataLayoutString() override { 6714 if (ABI == "n32") 6715 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6716 else 6717 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6718 } 6719 public: 6720 Mips64ELTargetInfo(const llvm::Triple &Triple) 6721 : Mips64TargetInfoBase(Triple) { 6722 // Default ABI is n64. 6723 BigEndian = false; 6724 } 6725 void getTargetDefines(const LangOptions &Opts, 6726 MacroBuilder &Builder) const override { 6727 DefineStd(Builder, "MIPSEL", Opts); 6728 Builder.defineMacro("_MIPSEL"); 6729 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6730 } 6731 }; 6732 6733 class PNaClTargetInfo : public TargetInfo { 6734 public: 6735 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6736 BigEndian = false; 6737 this->UserLabelPrefix = ""; 6738 this->LongAlign = 32; 6739 this->LongWidth = 32; 6740 this->PointerAlign = 32; 6741 this->PointerWidth = 32; 6742 this->IntMaxType = TargetInfo::SignedLongLong; 6743 this->Int64Type = TargetInfo::SignedLongLong; 6744 this->DoubleAlign = 64; 6745 this->LongDoubleWidth = 64; 6746 this->LongDoubleAlign = 64; 6747 this->SizeType = TargetInfo::UnsignedInt; 6748 this->PtrDiffType = TargetInfo::SignedInt; 6749 this->IntPtrType = TargetInfo::SignedInt; 6750 this->RegParmMax = 0; // Disallow regparm 6751 } 6752 6753 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6754 Builder.defineMacro("__le32__"); 6755 Builder.defineMacro("__pnacl__"); 6756 } 6757 void getTargetDefines(const LangOptions &Opts, 6758 MacroBuilder &Builder) const override { 6759 getArchDefines(Opts, Builder); 6760 } 6761 bool hasFeature(StringRef Feature) const override { 6762 return Feature == "pnacl"; 6763 } 6764 void getTargetBuiltins(const Builtin::Info *&Records, 6765 unsigned &NumRecords) const override { 6766 } 6767 BuiltinVaListKind getBuiltinVaListKind() const override { 6768 return TargetInfo::PNaClABIBuiltinVaList; 6769 } 6770 void getGCCRegNames(const char * const *&Names, 6771 unsigned &NumNames) const override; 6772 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6773 unsigned &NumAliases) const override; 6774 bool validateAsmConstraint(const char *&Name, 6775 TargetInfo::ConstraintInfo &Info) const override { 6776 return false; 6777 } 6778 6779 const char *getClobbers() const override { 6780 return ""; 6781 } 6782 }; 6783 6784 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6785 unsigned &NumNames) const { 6786 Names = nullptr; 6787 NumNames = 0; 6788 } 6789 6790 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6791 unsigned &NumAliases) const { 6792 Aliases = nullptr; 6793 NumAliases = 0; 6794 } 6795 6796 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6797 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6798 public: 6799 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6800 Mips32ELTargetInfo(Triple) { 6801 } 6802 6803 BuiltinVaListKind getBuiltinVaListKind() const override { 6804 return TargetInfo::PNaClABIBuiltinVaList; 6805 } 6806 }; 6807 6808 class Le64TargetInfo : public TargetInfo { 6809 static const Builtin::Info BuiltinInfo[]; 6810 6811 public: 6812 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6813 BigEndian = false; 6814 NoAsmVariants = true; 6815 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6816 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6817 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6818 } 6819 6820 void getTargetDefines(const LangOptions &Opts, 6821 MacroBuilder &Builder) const override { 6822 DefineStd(Builder, "unix", Opts); 6823 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6824 Builder.defineMacro("__ELF__"); 6825 } 6826 void getTargetBuiltins(const Builtin::Info *&Records, 6827 unsigned &NumRecords) const override { 6828 Records = BuiltinInfo; 6829 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6830 } 6831 BuiltinVaListKind getBuiltinVaListKind() const override { 6832 return TargetInfo::PNaClABIBuiltinVaList; 6833 } 6834 const char *getClobbers() const override { return ""; } 6835 void getGCCRegNames(const char *const *&Names, 6836 unsigned &NumNames) const override { 6837 Names = nullptr; 6838 NumNames = 0; 6839 } 6840 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6841 unsigned &NumAliases) const override { 6842 Aliases = nullptr; 6843 NumAliases = 0; 6844 } 6845 bool validateAsmConstraint(const char *&Name, 6846 TargetInfo::ConstraintInfo &Info) const override { 6847 return false; 6848 } 6849 6850 bool hasProtectedVisibility() const override { return false; } 6851 }; 6852 } // end anonymous namespace. 6853 6854 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6855 #define BUILTIN(ID, TYPE, ATTRS) \ 6856 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6857 #include "clang/Basic/BuiltinsLe64.def" 6858 }; 6859 6860 namespace { 6861 static const unsigned SPIRAddrSpaceMap[] = { 6862 1, // opencl_global 6863 3, // opencl_local 6864 2, // opencl_constant 6865 4, // opencl_generic 6866 0, // cuda_device 6867 0, // cuda_constant 6868 0 // cuda_shared 6869 }; 6870 class SPIRTargetInfo : public TargetInfo { 6871 public: 6872 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6873 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6874 "SPIR target must use unknown OS"); 6875 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6876 "SPIR target must use unknown environment type"); 6877 BigEndian = false; 6878 TLSSupported = false; 6879 LongWidth = LongAlign = 64; 6880 AddrSpaceMap = &SPIRAddrSpaceMap; 6881 UseAddrSpaceMapMangling = true; 6882 // Define available target features 6883 // These must be defined in sorted order! 6884 NoAsmVariants = true; 6885 } 6886 void getTargetDefines(const LangOptions &Opts, 6887 MacroBuilder &Builder) const override { 6888 DefineStd(Builder, "SPIR", Opts); 6889 } 6890 bool hasFeature(StringRef Feature) const override { 6891 return Feature == "spir"; 6892 } 6893 6894 void getTargetBuiltins(const Builtin::Info *&Records, 6895 unsigned &NumRecords) const override {} 6896 const char *getClobbers() const override { 6897 return ""; 6898 } 6899 void getGCCRegNames(const char * const *&Names, 6900 unsigned &NumNames) const override {} 6901 bool 6902 validateAsmConstraint(const char *&Name, 6903 TargetInfo::ConstraintInfo &info) const override { 6904 return true; 6905 } 6906 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6907 unsigned &NumAliases) const override {} 6908 BuiltinVaListKind getBuiltinVaListKind() const override { 6909 return TargetInfo::VoidPtrBuiltinVaList; 6910 } 6911 6912 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6913 return (CC == CC_SpirFunction || 6914 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6915 } 6916 6917 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6918 return CC_SpirFunction; 6919 } 6920 }; 6921 6922 6923 class SPIR32TargetInfo : public SPIRTargetInfo { 6924 public: 6925 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6926 PointerWidth = PointerAlign = 32; 6927 SizeType = TargetInfo::UnsignedInt; 6928 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6929 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6930 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6931 } 6932 void getTargetDefines(const LangOptions &Opts, 6933 MacroBuilder &Builder) const override { 6934 DefineStd(Builder, "SPIR32", Opts); 6935 } 6936 }; 6937 6938 class SPIR64TargetInfo : public SPIRTargetInfo { 6939 public: 6940 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6941 PointerWidth = PointerAlign = 64; 6942 SizeType = TargetInfo::UnsignedLong; 6943 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6944 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6945 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6946 } 6947 void getTargetDefines(const LangOptions &Opts, 6948 MacroBuilder &Builder) const override { 6949 DefineStd(Builder, "SPIR64", Opts); 6950 } 6951 }; 6952 6953 class XCoreTargetInfo : public TargetInfo { 6954 static const Builtin::Info BuiltinInfo[]; 6955 public: 6956 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6957 BigEndian = false; 6958 NoAsmVariants = true; 6959 LongLongAlign = 32; 6960 SuitableAlign = 32; 6961 DoubleAlign = LongDoubleAlign = 32; 6962 SizeType = UnsignedInt; 6963 PtrDiffType = SignedInt; 6964 IntPtrType = SignedInt; 6965 WCharType = UnsignedChar; 6966 WIntType = UnsignedInt; 6967 UseZeroLengthBitfieldAlignment = true; 6968 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6969 "-f64:32-a:0:32-n32"; 6970 } 6971 void getTargetDefines(const LangOptions &Opts, 6972 MacroBuilder &Builder) const override { 6973 Builder.defineMacro("__XS1B__"); 6974 } 6975 void getTargetBuiltins(const Builtin::Info *&Records, 6976 unsigned &NumRecords) const override { 6977 Records = BuiltinInfo; 6978 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6979 } 6980 BuiltinVaListKind getBuiltinVaListKind() const override { 6981 return TargetInfo::VoidPtrBuiltinVaList; 6982 } 6983 const char *getClobbers() const override { 6984 return ""; 6985 } 6986 void getGCCRegNames(const char * const *&Names, 6987 unsigned &NumNames) const override { 6988 static const char * const GCCRegNames[] = { 6989 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6990 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6991 }; 6992 Names = GCCRegNames; 6993 NumNames = llvm::array_lengthof(GCCRegNames); 6994 } 6995 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6996 unsigned &NumAliases) const override { 6997 Aliases = nullptr; 6998 NumAliases = 0; 6999 } 7000 bool validateAsmConstraint(const char *&Name, 7001 TargetInfo::ConstraintInfo &Info) const override { 7002 return false; 7003 } 7004 int getEHDataRegisterNumber(unsigned RegNo) const override { 7005 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7006 return (RegNo < 2)? RegNo : -1; 7007 } 7008 }; 7009 7010 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7011 #define BUILTIN(ID, TYPE, ATTRS) \ 7012 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7013 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7014 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7015 #include "clang/Basic/BuiltinsXCore.def" 7016 }; 7017 } // end anonymous namespace. 7018 7019 namespace { 7020 // x86_32 Android target 7021 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7022 public: 7023 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7024 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7025 SuitableAlign = 32; 7026 LongDoubleWidth = 64; 7027 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7028 } 7029 }; 7030 } // end anonymous namespace 7031 7032 namespace { 7033 // x86_64 Android target 7034 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7035 public: 7036 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7037 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7038 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7039 } 7040 7041 bool useFloat128ManglingForLongDouble() const override { 7042 return true; 7043 } 7044 }; 7045 } // end anonymous namespace 7046 7047 7048 //===----------------------------------------------------------------------===// 7049 // Driver code 7050 //===----------------------------------------------------------------------===// 7051 7052 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7053 llvm::Triple::OSType os = Triple.getOS(); 7054 7055 switch (Triple.getArch()) { 7056 default: 7057 return nullptr; 7058 7059 case llvm::Triple::xcore: 7060 return new XCoreTargetInfo(Triple); 7061 7062 case llvm::Triple::hexagon: 7063 return new HexagonTargetInfo(Triple); 7064 7065 case llvm::Triple::aarch64: 7066 if (Triple.isOSDarwin()) 7067 return new DarwinAArch64TargetInfo(Triple); 7068 7069 switch (os) { 7070 case llvm::Triple::FreeBSD: 7071 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7072 case llvm::Triple::Linux: 7073 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7074 case llvm::Triple::NetBSD: 7075 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7076 default: 7077 return new AArch64leTargetInfo(Triple); 7078 } 7079 7080 case llvm::Triple::aarch64_be: 7081 switch (os) { 7082 case llvm::Triple::FreeBSD: 7083 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7084 case llvm::Triple::Linux: 7085 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7086 case llvm::Triple::NetBSD: 7087 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7088 default: 7089 return new AArch64beTargetInfo(Triple); 7090 } 7091 7092 case llvm::Triple::arm: 7093 case llvm::Triple::thumb: 7094 if (Triple.isOSBinFormatMachO()) 7095 return new DarwinARMTargetInfo(Triple); 7096 7097 switch (os) { 7098 case llvm::Triple::Linux: 7099 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7100 case llvm::Triple::FreeBSD: 7101 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7102 case llvm::Triple::NetBSD: 7103 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7104 case llvm::Triple::OpenBSD: 7105 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7106 case llvm::Triple::Bitrig: 7107 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7108 case llvm::Triple::RTEMS: 7109 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7110 case llvm::Triple::NaCl: 7111 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7112 case llvm::Triple::Win32: 7113 switch (Triple.getEnvironment()) { 7114 case llvm::Triple::Cygnus: 7115 return new CygwinARMTargetInfo(Triple); 7116 case llvm::Triple::GNU: 7117 return new MinGWARMTargetInfo(Triple); 7118 case llvm::Triple::Itanium: 7119 return new ItaniumWindowsARMleTargetInfo(Triple); 7120 case llvm::Triple::MSVC: 7121 default: // Assume MSVC for unknown environments 7122 return new MicrosoftARMleTargetInfo(Triple); 7123 } 7124 default: 7125 return new ARMleTargetInfo(Triple); 7126 } 7127 7128 case llvm::Triple::armeb: 7129 case llvm::Triple::thumbeb: 7130 if (Triple.isOSDarwin()) 7131 return new DarwinARMTargetInfo(Triple); 7132 7133 switch (os) { 7134 case llvm::Triple::Linux: 7135 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7136 case llvm::Triple::FreeBSD: 7137 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7138 case llvm::Triple::NetBSD: 7139 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7140 case llvm::Triple::OpenBSD: 7141 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7142 case llvm::Triple::Bitrig: 7143 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7144 case llvm::Triple::RTEMS: 7145 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7146 case llvm::Triple::NaCl: 7147 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7148 default: 7149 return new ARMbeTargetInfo(Triple); 7150 } 7151 7152 case llvm::Triple::bpfeb: 7153 case llvm::Triple::bpfel: 7154 return new BPFTargetInfo(Triple); 7155 7156 case llvm::Triple::msp430: 7157 return new MSP430TargetInfo(Triple); 7158 7159 case llvm::Triple::mips: 7160 switch (os) { 7161 case llvm::Triple::Linux: 7162 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7163 case llvm::Triple::RTEMS: 7164 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7165 case llvm::Triple::FreeBSD: 7166 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7167 case llvm::Triple::NetBSD: 7168 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7169 default: 7170 return new Mips32EBTargetInfo(Triple); 7171 } 7172 7173 case llvm::Triple::mipsel: 7174 switch (os) { 7175 case llvm::Triple::Linux: 7176 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7177 case llvm::Triple::RTEMS: 7178 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7179 case llvm::Triple::FreeBSD: 7180 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7181 case llvm::Triple::NetBSD: 7182 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7183 case llvm::Triple::NaCl: 7184 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7185 default: 7186 return new Mips32ELTargetInfo(Triple); 7187 } 7188 7189 case llvm::Triple::mips64: 7190 switch (os) { 7191 case llvm::Triple::Linux: 7192 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7193 case llvm::Triple::RTEMS: 7194 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7195 case llvm::Triple::FreeBSD: 7196 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7197 case llvm::Triple::NetBSD: 7198 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7199 case llvm::Triple::OpenBSD: 7200 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7201 default: 7202 return new Mips64EBTargetInfo(Triple); 7203 } 7204 7205 case llvm::Triple::mips64el: 7206 switch (os) { 7207 case llvm::Triple::Linux: 7208 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7209 case llvm::Triple::RTEMS: 7210 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7211 case llvm::Triple::FreeBSD: 7212 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7213 case llvm::Triple::NetBSD: 7214 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7215 case llvm::Triple::OpenBSD: 7216 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7217 default: 7218 return new Mips64ELTargetInfo(Triple); 7219 } 7220 7221 case llvm::Triple::le32: 7222 switch (os) { 7223 case llvm::Triple::NaCl: 7224 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7225 default: 7226 return nullptr; 7227 } 7228 7229 case llvm::Triple::le64: 7230 return new Le64TargetInfo(Triple); 7231 7232 case llvm::Triple::ppc: 7233 if (Triple.isOSDarwin()) 7234 return new DarwinPPC32TargetInfo(Triple); 7235 switch (os) { 7236 case llvm::Triple::Linux: 7237 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7238 case llvm::Triple::FreeBSD: 7239 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7240 case llvm::Triple::NetBSD: 7241 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7242 case llvm::Triple::OpenBSD: 7243 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7244 case llvm::Triple::RTEMS: 7245 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7246 default: 7247 return new PPC32TargetInfo(Triple); 7248 } 7249 7250 case llvm::Triple::ppc64: 7251 if (Triple.isOSDarwin()) 7252 return new DarwinPPC64TargetInfo(Triple); 7253 switch (os) { 7254 case llvm::Triple::Linux: 7255 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7256 case llvm::Triple::Lv2: 7257 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7258 case llvm::Triple::FreeBSD: 7259 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7260 case llvm::Triple::NetBSD: 7261 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7262 default: 7263 return new PPC64TargetInfo(Triple); 7264 } 7265 7266 case llvm::Triple::ppc64le: 7267 switch (os) { 7268 case llvm::Triple::Linux: 7269 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7270 case llvm::Triple::NetBSD: 7271 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7272 default: 7273 return new PPC64TargetInfo(Triple); 7274 } 7275 7276 case llvm::Triple::nvptx: 7277 return new NVPTX32TargetInfo(Triple); 7278 case llvm::Triple::nvptx64: 7279 return new NVPTX64TargetInfo(Triple); 7280 7281 case llvm::Triple::amdgcn: 7282 case llvm::Triple::r600: 7283 return new AMDGPUTargetInfo(Triple); 7284 7285 case llvm::Triple::sparc: 7286 switch (os) { 7287 case llvm::Triple::Linux: 7288 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7289 case llvm::Triple::Solaris: 7290 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7291 case llvm::Triple::NetBSD: 7292 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7293 case llvm::Triple::OpenBSD: 7294 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7295 case llvm::Triple::RTEMS: 7296 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7297 default: 7298 return new SparcV8TargetInfo(Triple); 7299 } 7300 7301 // The 'sparcel' architecture copies all the above cases except for Solaris. 7302 case llvm::Triple::sparcel: 7303 switch (os) { 7304 case llvm::Triple::Linux: 7305 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7306 case llvm::Triple::NetBSD: 7307 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7308 case llvm::Triple::OpenBSD: 7309 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7310 case llvm::Triple::RTEMS: 7311 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7312 default: 7313 return new SparcV8elTargetInfo(Triple); 7314 } 7315 7316 case llvm::Triple::sparcv9: 7317 switch (os) { 7318 case llvm::Triple::Linux: 7319 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7320 case llvm::Triple::Solaris: 7321 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7322 case llvm::Triple::NetBSD: 7323 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7324 case llvm::Triple::OpenBSD: 7325 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7326 case llvm::Triple::FreeBSD: 7327 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7328 default: 7329 return new SparcV9TargetInfo(Triple); 7330 } 7331 7332 case llvm::Triple::systemz: 7333 switch (os) { 7334 case llvm::Triple::Linux: 7335 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7336 default: 7337 return new SystemZTargetInfo(Triple); 7338 } 7339 7340 case llvm::Triple::tce: 7341 return new TCETargetInfo(Triple); 7342 7343 case llvm::Triple::x86: 7344 if (Triple.isOSDarwin()) 7345 return new DarwinI386TargetInfo(Triple); 7346 7347 switch (os) { 7348 case llvm::Triple::CloudABI: 7349 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7350 case llvm::Triple::Linux: { 7351 switch (Triple.getEnvironment()) { 7352 default: 7353 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7354 case llvm::Triple::Android: 7355 return new AndroidX86_32TargetInfo(Triple); 7356 } 7357 } 7358 case llvm::Triple::DragonFly: 7359 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7360 case llvm::Triple::NetBSD: 7361 return new NetBSDI386TargetInfo(Triple); 7362 case llvm::Triple::OpenBSD: 7363 return new OpenBSDI386TargetInfo(Triple); 7364 case llvm::Triple::Bitrig: 7365 return new BitrigI386TargetInfo(Triple); 7366 case llvm::Triple::FreeBSD: 7367 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7368 case llvm::Triple::KFreeBSD: 7369 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7370 case llvm::Triple::Minix: 7371 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7372 case llvm::Triple::Solaris: 7373 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7374 case llvm::Triple::Win32: { 7375 switch (Triple.getEnvironment()) { 7376 case llvm::Triple::Cygnus: 7377 return new CygwinX86_32TargetInfo(Triple); 7378 case llvm::Triple::GNU: 7379 return new MinGWX86_32TargetInfo(Triple); 7380 case llvm::Triple::Itanium: 7381 case llvm::Triple::MSVC: 7382 default: // Assume MSVC for unknown environments 7383 return new MicrosoftX86_32TargetInfo(Triple); 7384 } 7385 } 7386 case llvm::Triple::Haiku: 7387 return new HaikuX86_32TargetInfo(Triple); 7388 case llvm::Triple::RTEMS: 7389 return new RTEMSX86_32TargetInfo(Triple); 7390 case llvm::Triple::NaCl: 7391 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7392 default: 7393 return new X86_32TargetInfo(Triple); 7394 } 7395 7396 case llvm::Triple::x86_64: 7397 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7398 return new DarwinX86_64TargetInfo(Triple); 7399 7400 switch (os) { 7401 case llvm::Triple::CloudABI: 7402 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7403 case llvm::Triple::Linux: { 7404 switch (Triple.getEnvironment()) { 7405 default: 7406 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7407 case llvm::Triple::Android: 7408 return new AndroidX86_64TargetInfo(Triple); 7409 } 7410 } 7411 case llvm::Triple::DragonFly: 7412 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7413 case llvm::Triple::NetBSD: 7414 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7415 case llvm::Triple::OpenBSD: 7416 return new OpenBSDX86_64TargetInfo(Triple); 7417 case llvm::Triple::Bitrig: 7418 return new BitrigX86_64TargetInfo(Triple); 7419 case llvm::Triple::FreeBSD: 7420 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7421 case llvm::Triple::KFreeBSD: 7422 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7423 case llvm::Triple::Solaris: 7424 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7425 case llvm::Triple::Win32: { 7426 switch (Triple.getEnvironment()) { 7427 case llvm::Triple::Cygnus: 7428 return new CygwinX86_64TargetInfo(Triple); 7429 case llvm::Triple::GNU: 7430 return new MinGWX86_64TargetInfo(Triple); 7431 case llvm::Triple::MSVC: 7432 default: // Assume MSVC for unknown environments 7433 return new MicrosoftX86_64TargetInfo(Triple); 7434 } 7435 } 7436 case llvm::Triple::NaCl: 7437 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7438 case llvm::Triple::PS4: 7439 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7440 default: 7441 return new X86_64TargetInfo(Triple); 7442 } 7443 7444 case llvm::Triple::spir: { 7445 if (Triple.getOS() != llvm::Triple::UnknownOS || 7446 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7447 return nullptr; 7448 return new SPIR32TargetInfo(Triple); 7449 } 7450 case llvm::Triple::spir64: { 7451 if (Triple.getOS() != llvm::Triple::UnknownOS || 7452 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7453 return nullptr; 7454 return new SPIR64TargetInfo(Triple); 7455 } 7456 } 7457 } 7458 7459 /// CreateTargetInfo - Return the target info object for the specified target 7460 /// options. 7461 TargetInfo * 7462 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7463 const std::shared_ptr<TargetOptions> &Opts) { 7464 llvm::Triple Triple(Opts->Triple); 7465 7466 // Construct the target 7467 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7468 if (!Target) { 7469 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7470 return nullptr; 7471 } 7472 Target->TargetOpts = Opts; 7473 7474 // Set the target CPU if specified. 7475 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7476 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7477 return nullptr; 7478 } 7479 7480 // Set the target ABI if specified. 7481 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7482 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7483 return nullptr; 7484 } 7485 7486 // Set the fp math unit. 7487 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7488 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7489 return nullptr; 7490 } 7491 7492 // Compute the default target features, we need the target to handle this 7493 // because features may have dependencies on one another. 7494 llvm::StringMap<bool> Features; 7495 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7496 Opts->FeaturesAsWritten)) 7497 return nullptr; 7498 7499 // Add the features to the compile options. 7500 Opts->Features.clear(); 7501 for (const auto &F : Features) 7502 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7503 7504 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7505 return nullptr; 7506 7507 return Target.release(); 7508 } 7509