1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 584 this->MaxTLSAlign = 256; 585 this->UserLabelPrefix = ""; 586 587 switch (Triple.getArch()) { 588 default: 589 case llvm::Triple::x86_64: 590 this->MCountName = ".mcount"; 591 break; 592 } 593 } 594 }; 595 596 // Solaris target 597 template<typename Target> 598 class SolarisTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const override { 602 DefineStd(Builder, "sun", Opts); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__svr4__"); 606 Builder.defineMacro("__SVR4"); 607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 608 // newer, but to 500 for everything else. feature_test.h has a check to 609 // ensure that you are not using C99 with an old version of X/Open or C89 610 // with a new version. 611 if (Opts.C99) 612 Builder.defineMacro("_XOPEN_SOURCE", "600"); 613 else 614 Builder.defineMacro("_XOPEN_SOURCE", "500"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("__C99FEATURES__"); 617 Builder.defineMacro("_LARGEFILE_SOURCE"); 618 Builder.defineMacro("_LARGEFILE64_SOURCE"); 619 Builder.defineMacro("__EXTENSIONS__"); 620 Builder.defineMacro("_REENTRANT"); 621 } 622 public: 623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 624 this->UserLabelPrefix = ""; 625 this->WCharType = this->SignedInt; 626 // FIXME: WIntType should be SignedLong 627 } 628 }; 629 630 // Windows target 631 template<typename Target> 632 class WindowsTargetInfo : public OSTargetInfo<Target> { 633 protected: 634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 635 MacroBuilder &Builder) const override { 636 Builder.defineMacro("_WIN32"); 637 } 638 void getVisualStudioDefines(const LangOptions &Opts, 639 MacroBuilder &Builder) const { 640 if (Opts.CPlusPlus) { 641 if (Opts.RTTIData) 642 Builder.defineMacro("_CPPRTTI"); 643 644 if (Opts.CXXExceptions) 645 Builder.defineMacro("_CPPUNWIND"); 646 } 647 648 if (Opts.Bool) 649 Builder.defineMacro("__BOOL_DEFINED"); 650 651 if (!Opts.CharIsSigned) 652 Builder.defineMacro("_CHAR_UNSIGNED"); 653 654 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 655 // but it works for now. 656 if (Opts.POSIXThreads) 657 Builder.defineMacro("_MT"); 658 659 if (Opts.MSCompatibilityVersion) { 660 Builder.defineMacro("_MSC_VER", 661 Twine(Opts.MSCompatibilityVersion / 100000)); 662 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 663 // FIXME We cannot encode the revision information into 32-bits 664 Builder.defineMacro("_MSC_BUILD", Twine(1)); 665 666 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 667 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 668 } 669 670 if (Opts.MicrosoftExt) { 671 Builder.defineMacro("_MSC_EXTENSIONS"); 672 673 if (Opts.CPlusPlus11) { 674 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 675 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 676 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 677 } 678 } 679 680 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 681 } 682 683 public: 684 WindowsTargetInfo(const llvm::Triple &Triple) 685 : OSTargetInfo<Target>(Triple) {} 686 }; 687 688 template <typename Target> 689 class NaClTargetInfo : public OSTargetInfo<Target> { 690 protected: 691 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 692 MacroBuilder &Builder) const override { 693 if (Opts.POSIXThreads) 694 Builder.defineMacro("_REENTRANT"); 695 if (Opts.CPlusPlus) 696 Builder.defineMacro("_GNU_SOURCE"); 697 698 DefineStd(Builder, "unix", Opts); 699 Builder.defineMacro("__ELF__"); 700 Builder.defineMacro("__native_client__"); 701 } 702 703 public: 704 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 705 this->UserLabelPrefix = ""; 706 this->LongAlign = 32; 707 this->LongWidth = 32; 708 this->PointerAlign = 32; 709 this->PointerWidth = 32; 710 this->IntMaxType = TargetInfo::SignedLongLong; 711 this->Int64Type = TargetInfo::SignedLongLong; 712 this->DoubleAlign = 64; 713 this->LongDoubleWidth = 64; 714 this->LongDoubleAlign = 64; 715 this->LongLongWidth = 64; 716 this->LongLongAlign = 64; 717 this->SizeType = TargetInfo::UnsignedInt; 718 this->PtrDiffType = TargetInfo::SignedInt; 719 this->IntPtrType = TargetInfo::SignedInt; 720 // RegParmMax is inherited from the underlying architecture 721 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 722 if (Triple.getArch() == llvm::Triple::arm) { 723 // Handled in ARM's setABI(). 724 } else if (Triple.getArch() == llvm::Triple::x86) { 725 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 726 } else if (Triple.getArch() == llvm::Triple::x86_64) { 727 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 728 } else if (Triple.getArch() == llvm::Triple::mipsel) { 729 // Handled on mips' setDataLayoutString. 730 } else { 731 assert(Triple.getArch() == llvm::Triple::le32); 732 this->DataLayoutString = "e-p:32:32-i64:64"; 733 } 734 } 735 }; 736 737 //===----------------------------------------------------------------------===// 738 // Specific target implementations. 739 //===----------------------------------------------------------------------===// 740 741 // PPC abstract base class 742 class PPCTargetInfo : public TargetInfo { 743 static const Builtin::Info BuiltinInfo[]; 744 static const char * const GCCRegNames[]; 745 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 746 std::string CPU; 747 748 // Target cpu features. 749 bool HasVSX; 750 bool HasP8Vector; 751 bool HasP8Crypto; 752 bool HasDirectMove; 753 bool HasQPX; 754 bool HasHTM; 755 bool HasBPERMD; 756 bool HasExtDiv; 757 758 protected: 759 std::string ABI; 760 761 public: 762 PPCTargetInfo(const llvm::Triple &Triple) 763 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 764 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 765 HasBPERMD(false), HasExtDiv(false) { 766 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 767 SimdDefaultAlign = 128; 768 LongDoubleWidth = LongDoubleAlign = 128; 769 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 770 } 771 772 /// \brief Flags for architecture specific defines. 773 typedef enum { 774 ArchDefineNone = 0, 775 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 776 ArchDefinePpcgr = 1 << 1, 777 ArchDefinePpcsq = 1 << 2, 778 ArchDefine440 = 1 << 3, 779 ArchDefine603 = 1 << 4, 780 ArchDefine604 = 1 << 5, 781 ArchDefinePwr4 = 1 << 6, 782 ArchDefinePwr5 = 1 << 7, 783 ArchDefinePwr5x = 1 << 8, 784 ArchDefinePwr6 = 1 << 9, 785 ArchDefinePwr6x = 1 << 10, 786 ArchDefinePwr7 = 1 << 11, 787 ArchDefinePwr8 = 1 << 12, 788 ArchDefineA2 = 1 << 13, 789 ArchDefineA2q = 1 << 14 790 } ArchDefineTypes; 791 792 // Note: GCC recognizes the following additional cpus: 793 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 794 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 795 // titan, rs64. 796 bool setCPU(const std::string &Name) override { 797 bool CPUKnown = llvm::StringSwitch<bool>(Name) 798 .Case("generic", true) 799 .Case("440", true) 800 .Case("450", true) 801 .Case("601", true) 802 .Case("602", true) 803 .Case("603", true) 804 .Case("603e", true) 805 .Case("603ev", true) 806 .Case("604", true) 807 .Case("604e", true) 808 .Case("620", true) 809 .Case("630", true) 810 .Case("g3", true) 811 .Case("7400", true) 812 .Case("g4", true) 813 .Case("7450", true) 814 .Case("g4+", true) 815 .Case("750", true) 816 .Case("970", true) 817 .Case("g5", true) 818 .Case("a2", true) 819 .Case("a2q", true) 820 .Case("e500mc", true) 821 .Case("e5500", true) 822 .Case("power3", true) 823 .Case("pwr3", true) 824 .Case("power4", true) 825 .Case("pwr4", true) 826 .Case("power5", true) 827 .Case("pwr5", true) 828 .Case("power5x", true) 829 .Case("pwr5x", true) 830 .Case("power6", true) 831 .Case("pwr6", true) 832 .Case("power6x", true) 833 .Case("pwr6x", true) 834 .Case("power7", true) 835 .Case("pwr7", true) 836 .Case("power8", true) 837 .Case("pwr8", true) 838 .Case("powerpc", true) 839 .Case("ppc", true) 840 .Case("powerpc64", true) 841 .Case("ppc64", true) 842 .Case("powerpc64le", true) 843 .Case("ppc64le", true) 844 .Default(false); 845 846 if (CPUKnown) 847 CPU = Name; 848 849 return CPUKnown; 850 } 851 852 853 StringRef getABI() const override { return ABI; } 854 855 void getTargetBuiltins(const Builtin::Info *&Records, 856 unsigned &NumRecords) const override { 857 Records = BuiltinInfo; 858 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 859 } 860 861 bool isCLZForZeroUndef() const override { return false; } 862 863 void getTargetDefines(const LangOptions &Opts, 864 MacroBuilder &Builder) const override; 865 866 void initDefaultFeatures(llvm::StringMap<bool> &Features) const override; 867 868 bool handleTargetFeatures(std::vector<std::string> &Features, 869 DiagnosticsEngine &Diags) override; 870 bool hasFeature(StringRef Feature) const override; 871 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 872 bool Enabled) const override; 873 874 void getGCCRegNames(const char * const *&Names, 875 unsigned &NumNames) const override; 876 void getGCCRegAliases(const GCCRegAlias *&Aliases, 877 unsigned &NumAliases) const override; 878 bool validateAsmConstraint(const char *&Name, 879 TargetInfo::ConstraintInfo &Info) const override { 880 switch (*Name) { 881 default: return false; 882 case 'O': // Zero 883 break; 884 case 'b': // Base register 885 case 'f': // Floating point register 886 Info.setAllowsRegister(); 887 break; 888 // FIXME: The following are added to allow parsing. 889 // I just took a guess at what the actions should be. 890 // Also, is more specific checking needed? I.e. specific registers? 891 case 'd': // Floating point register (containing 64-bit value) 892 case 'v': // Altivec vector register 893 Info.setAllowsRegister(); 894 break; 895 case 'w': 896 switch (Name[1]) { 897 case 'd':// VSX vector register to hold vector double data 898 case 'f':// VSX vector register to hold vector float data 899 case 's':// VSX vector register to hold scalar float data 900 case 'a':// Any VSX register 901 case 'c':// An individual CR bit 902 break; 903 default: 904 return false; 905 } 906 Info.setAllowsRegister(); 907 Name++; // Skip over 'w'. 908 break; 909 case 'h': // `MQ', `CTR', or `LINK' register 910 case 'q': // `MQ' register 911 case 'c': // `CTR' register 912 case 'l': // `LINK' register 913 case 'x': // `CR' register (condition register) number 0 914 case 'y': // `CR' register (condition register) 915 case 'z': // `XER[CA]' carry bit (part of the XER register) 916 Info.setAllowsRegister(); 917 break; 918 case 'I': // Signed 16-bit constant 919 case 'J': // Unsigned 16-bit constant shifted left 16 bits 920 // (use `L' instead for SImode constants) 921 case 'K': // Unsigned 16-bit constant 922 case 'L': // Signed 16-bit constant shifted left 16 bits 923 case 'M': // Constant larger than 31 924 case 'N': // Exact power of 2 925 case 'P': // Constant whose negation is a signed 16-bit constant 926 case 'G': // Floating point constant that can be loaded into a 927 // register with one instruction per word 928 case 'H': // Integer/Floating point constant that can be loaded 929 // into a register using three instructions 930 break; 931 case 'm': // Memory operand. Note that on PowerPC targets, m can 932 // include addresses that update the base register. It 933 // is therefore only safe to use `m' in an asm statement 934 // if that asm statement accesses the operand exactly once. 935 // The asm statement must also use `%U<opno>' as a 936 // placeholder for the "update" flag in the corresponding 937 // load or store instruction. For example: 938 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 939 // is correct but: 940 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 941 // is not. Use es rather than m if you don't want the base 942 // register to be updated. 943 case 'e': 944 if (Name[1] != 's') 945 return false; 946 // es: A "stable" memory operand; that is, one which does not 947 // include any automodification of the base register. Unlike 948 // `m', this constraint can be used in asm statements that 949 // might access the operand several times, or that might not 950 // access it at all. 951 Info.setAllowsMemory(); 952 Name++; // Skip over 'e'. 953 break; 954 case 'Q': // Memory operand that is an offset from a register (it is 955 // usually better to use `m' or `es' in asm statements) 956 case 'Z': // Memory operand that is an indexed or indirect from a 957 // register (it is usually better to use `m' or `es' in 958 // asm statements) 959 Info.setAllowsMemory(); 960 Info.setAllowsRegister(); 961 break; 962 case 'R': // AIX TOC entry 963 case 'a': // Address operand that is an indexed or indirect from a 964 // register (`p' is preferable for asm statements) 965 case 'S': // Constant suitable as a 64-bit mask operand 966 case 'T': // Constant suitable as a 32-bit mask operand 967 case 'U': // System V Release 4 small data area reference 968 case 't': // AND masks that can be performed by two rldic{l, r} 969 // instructions 970 case 'W': // Vector constant that does not require memory 971 case 'j': // Vector constant that is all zeros. 972 break; 973 // End FIXME. 974 } 975 return true; 976 } 977 std::string convertConstraint(const char *&Constraint) const override { 978 std::string R; 979 switch (*Constraint) { 980 case 'e': 981 case 'w': 982 // Two-character constraint; add "^" hint for later parsing. 983 R = std::string("^") + std::string(Constraint, 2); 984 Constraint++; 985 break; 986 default: 987 return TargetInfo::convertConstraint(Constraint); 988 } 989 return R; 990 } 991 const char *getClobbers() const override { 992 return ""; 993 } 994 int getEHDataRegisterNumber(unsigned RegNo) const override { 995 if (RegNo == 0) return 3; 996 if (RegNo == 1) return 4; 997 return -1; 998 } 999 1000 bool hasSjLjLowering() const override { 1001 return true; 1002 } 1003 1004 bool useFloat128ManglingForLongDouble() const override { 1005 return LongDoubleWidth == 128 && 1006 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1007 getTriple().isOSBinFormatELF(); 1008 } 1009 }; 1010 1011 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1012 #define BUILTIN(ID, TYPE, ATTRS) \ 1013 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1014 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1015 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1016 #include "clang/Basic/BuiltinsPPC.def" 1017 }; 1018 1019 /// handleTargetFeatures - Perform initialization based on the user 1020 /// configured set of features. 1021 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1022 DiagnosticsEngine &Diags) { 1023 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1024 // Ignore disabled features. 1025 if (Features[i][0] == '-') 1026 continue; 1027 1028 StringRef Feature = StringRef(Features[i]).substr(1); 1029 1030 if (Feature == "vsx") { 1031 HasVSX = true; 1032 continue; 1033 } 1034 1035 if (Feature == "bpermd") { 1036 HasBPERMD = true; 1037 continue; 1038 } 1039 1040 if (Feature == "extdiv") { 1041 HasExtDiv = true; 1042 continue; 1043 } 1044 1045 if (Feature == "power8-vector") { 1046 HasP8Vector = true; 1047 continue; 1048 } 1049 1050 if (Feature == "crypto") { 1051 HasP8Crypto = true; 1052 continue; 1053 } 1054 1055 if (Feature == "direct-move") { 1056 HasDirectMove = true; 1057 continue; 1058 } 1059 1060 if (Feature == "qpx") { 1061 HasQPX = true; 1062 continue; 1063 } 1064 1065 if (Feature == "htm") { 1066 HasHTM = true; 1067 continue; 1068 } 1069 1070 // TODO: Finish this list and add an assert that we've handled them 1071 // all. 1072 } 1073 if (!HasVSX && (HasP8Vector || HasDirectMove)) { 1074 if (HasP8Vector) 1075 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << 1076 "-mno-vsx"; 1077 else if (HasDirectMove) 1078 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << 1079 "-mno-vsx"; 1080 return false; 1081 } 1082 1083 return true; 1084 } 1085 1086 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1087 /// #defines that are not tied to a specific subtarget. 1088 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1089 MacroBuilder &Builder) const { 1090 // Target identification. 1091 Builder.defineMacro("__ppc__"); 1092 Builder.defineMacro("__PPC__"); 1093 Builder.defineMacro("_ARCH_PPC"); 1094 Builder.defineMacro("__powerpc__"); 1095 Builder.defineMacro("__POWERPC__"); 1096 if (PointerWidth == 64) { 1097 Builder.defineMacro("_ARCH_PPC64"); 1098 Builder.defineMacro("__powerpc64__"); 1099 Builder.defineMacro("__ppc64__"); 1100 Builder.defineMacro("__PPC64__"); 1101 } 1102 1103 // Target properties. 1104 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1105 Builder.defineMacro("_LITTLE_ENDIAN"); 1106 } else { 1107 if (getTriple().getOS() != llvm::Triple::NetBSD && 1108 getTriple().getOS() != llvm::Triple::OpenBSD) 1109 Builder.defineMacro("_BIG_ENDIAN"); 1110 } 1111 1112 // ABI options. 1113 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1114 Builder.defineMacro("_CALL_ELF", "1"); 1115 if (ABI == "elfv2") 1116 Builder.defineMacro("_CALL_ELF", "2"); 1117 1118 // Subtarget options. 1119 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1120 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1121 1122 // FIXME: Should be controlled by command line option. 1123 if (LongDoubleWidth == 128) 1124 Builder.defineMacro("__LONG_DOUBLE_128__"); 1125 1126 if (Opts.AltiVec) { 1127 Builder.defineMacro("__VEC__", "10206"); 1128 Builder.defineMacro("__ALTIVEC__"); 1129 } 1130 1131 // CPU identification. 1132 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1133 .Case("440", ArchDefineName) 1134 .Case("450", ArchDefineName | ArchDefine440) 1135 .Case("601", ArchDefineName) 1136 .Case("602", ArchDefineName | ArchDefinePpcgr) 1137 .Case("603", ArchDefineName | ArchDefinePpcgr) 1138 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1139 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1140 .Case("604", ArchDefineName | ArchDefinePpcgr) 1141 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1142 .Case("620", ArchDefineName | ArchDefinePpcgr) 1143 .Case("630", ArchDefineName | ArchDefinePpcgr) 1144 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1145 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1146 .Case("750", ArchDefineName | ArchDefinePpcgr) 1147 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("a2", ArchDefineA2) 1150 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1151 .Case("pwr3", ArchDefinePpcgr) 1152 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1154 | ArchDefinePpcsq) 1155 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1156 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1158 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1160 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1161 | ArchDefinePpcsq) 1162 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1163 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1164 | ArchDefinePpcgr | ArchDefinePpcsq) 1165 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1166 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1167 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power3", ArchDefinePpcgr) 1169 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1171 | ArchDefinePpcsq) 1172 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1173 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1175 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1177 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1178 | ArchDefinePpcsq) 1179 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1180 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1181 | ArchDefinePpcgr | ArchDefinePpcsq) 1182 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1183 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1184 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Default(ArchDefineNone); 1186 1187 if (defs & ArchDefineName) 1188 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1189 if (defs & ArchDefinePpcgr) 1190 Builder.defineMacro("_ARCH_PPCGR"); 1191 if (defs & ArchDefinePpcsq) 1192 Builder.defineMacro("_ARCH_PPCSQ"); 1193 if (defs & ArchDefine440) 1194 Builder.defineMacro("_ARCH_440"); 1195 if (defs & ArchDefine603) 1196 Builder.defineMacro("_ARCH_603"); 1197 if (defs & ArchDefine604) 1198 Builder.defineMacro("_ARCH_604"); 1199 if (defs & ArchDefinePwr4) 1200 Builder.defineMacro("_ARCH_PWR4"); 1201 if (defs & ArchDefinePwr5) 1202 Builder.defineMacro("_ARCH_PWR5"); 1203 if (defs & ArchDefinePwr5x) 1204 Builder.defineMacro("_ARCH_PWR5X"); 1205 if (defs & ArchDefinePwr6) 1206 Builder.defineMacro("_ARCH_PWR6"); 1207 if (defs & ArchDefinePwr6x) 1208 Builder.defineMacro("_ARCH_PWR6X"); 1209 if (defs & ArchDefinePwr7) 1210 Builder.defineMacro("_ARCH_PWR7"); 1211 if (defs & ArchDefinePwr8) 1212 Builder.defineMacro("_ARCH_PWR8"); 1213 if (defs & ArchDefineA2) 1214 Builder.defineMacro("_ARCH_A2"); 1215 if (defs & ArchDefineA2q) { 1216 Builder.defineMacro("_ARCH_A2Q"); 1217 Builder.defineMacro("_ARCH_QP"); 1218 } 1219 1220 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1221 Builder.defineMacro("__bg__"); 1222 Builder.defineMacro("__THW_BLUEGENE__"); 1223 Builder.defineMacro("__bgq__"); 1224 Builder.defineMacro("__TOS_BGQ__"); 1225 } 1226 1227 if (HasVSX) 1228 Builder.defineMacro("__VSX__"); 1229 if (HasP8Vector) 1230 Builder.defineMacro("__POWER8_VECTOR__"); 1231 if (HasP8Crypto) 1232 Builder.defineMacro("__CRYPTO__"); 1233 if (HasHTM) 1234 Builder.defineMacro("__HTM__"); 1235 if (getTriple().getArch() == llvm::Triple::ppc64le || 1236 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1238 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1239 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1240 if (PointerWidth == 64) 1241 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1242 } 1243 1244 // FIXME: The following are not yet generated here by Clang, but are 1245 // generated by GCC: 1246 // 1247 // _SOFT_FLOAT_ 1248 // __RECIP_PRECISION__ 1249 // __APPLE_ALTIVEC__ 1250 // __RECIP__ 1251 // __RECIPF__ 1252 // __RSQRTE__ 1253 // __RSQRTEF__ 1254 // _SOFT_DOUBLE_ 1255 // __NO_LWSYNC__ 1256 // __HAVE_BSWAP__ 1257 // __LONGDOUBLE128 1258 // __CMODEL_MEDIUM__ 1259 // __CMODEL_LARGE__ 1260 // _CALL_SYSV 1261 // _CALL_DARWIN 1262 // __NO_FPRS__ 1263 } 1264 1265 void PPCTargetInfo::initDefaultFeatures(llvm::StringMap<bool> &Features) const { 1266 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("7400", true) 1268 .Case("g4", true) 1269 .Case("7450", true) 1270 .Case("g4+", true) 1271 .Case("970", true) 1272 .Case("g5", true) 1273 .Case("pwr6", true) 1274 .Case("pwr7", true) 1275 .Case("pwr8", true) 1276 .Case("ppc64", true) 1277 .Case("ppc64le", true) 1278 .Default(false); 1279 1280 Features["qpx"] = (CPU == "a2q"); 1281 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1282 .Case("ppc64le", true) 1283 .Case("pwr8", true) 1284 .Default(false); 1285 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1286 .Case("ppc64le", true) 1287 .Case("pwr8", true) 1288 .Default(false); 1289 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1290 .Case("ppc64le", true) 1291 .Case("pwr8", true) 1292 .Case("pwr7", true) 1293 .Default(false); 1294 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1295 .Case("ppc64le", true) 1296 .Case("pwr8", true) 1297 .Case("pwr7", true) 1298 .Default(false); 1299 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1300 .Case("ppc64le", true) 1301 .Case("pwr8", true) 1302 .Default(false); 1303 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1304 .Case("ppc64le", true) 1305 .Case("pwr8", true) 1306 .Case("pwr7", true) 1307 .Default(false); 1308 } 1309 1310 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1311 return llvm::StringSwitch<bool>(Feature) 1312 .Case("powerpc", true) 1313 .Case("vsx", HasVSX) 1314 .Case("power8-vector", HasP8Vector) 1315 .Case("crypto", HasP8Crypto) 1316 .Case("direct-move", HasDirectMove) 1317 .Case("qpx", HasQPX) 1318 .Case("htm", HasHTM) 1319 .Case("bpermd", HasBPERMD) 1320 .Case("extdiv", HasExtDiv) 1321 .Default(false); 1322 } 1323 1324 /* There is no clear way for the target to know which of the features in the 1325 final feature vector came from defaults and which are actually specified by 1326 the user. To that end, we use the fact that this function is not called on 1327 default features - only user specified ones. By the first time this 1328 function is called, the default features are populated. 1329 We then keep track of the features that the user specified so that we 1330 can ensure we do not override a user's request (only defaults). 1331 For example: 1332 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it) 1333 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed) 1334 1335 NOTE: Do not call this from PPCTargetInfo::initDefaultFeatures 1336 */ 1337 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1338 StringRef Name, bool Enabled) const { 1339 static llvm::StringMap<bool> ExplicitFeatures; 1340 ExplicitFeatures[Name] = Enabled; 1341 1342 // At this point, -mno-vsx turns off the dependent features but we respect 1343 // the user's requests. 1344 if (!Enabled && Name == "vsx") { 1345 Features["direct-move"] = ExplicitFeatures["direct-move"]; 1346 Features["power8-vector"] = ExplicitFeatures["power8-vector"]; 1347 } 1348 if ((Enabled && Name == "power8-vector") || 1349 (Enabled && Name == "direct-move")) { 1350 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) { 1351 Features["vsx"] = true; 1352 } 1353 } 1354 Features[Name] = Enabled; 1355 } 1356 1357 const char * const PPCTargetInfo::GCCRegNames[] = { 1358 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1359 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1360 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1361 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1362 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1363 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1364 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1365 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1366 "mq", "lr", "ctr", "ap", 1367 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1368 "xer", 1369 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1370 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1371 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1372 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1373 "vrsave", "vscr", 1374 "spe_acc", "spefscr", 1375 "sfp" 1376 }; 1377 1378 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1379 unsigned &NumNames) const { 1380 Names = GCCRegNames; 1381 NumNames = llvm::array_lengthof(GCCRegNames); 1382 } 1383 1384 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1385 // While some of these aliases do map to different registers 1386 // they still share the same register name. 1387 { { "0" }, "r0" }, 1388 { { "1"}, "r1" }, 1389 { { "2" }, "r2" }, 1390 { { "3" }, "r3" }, 1391 { { "4" }, "r4" }, 1392 { { "5" }, "r5" }, 1393 { { "6" }, "r6" }, 1394 { { "7" }, "r7" }, 1395 { { "8" }, "r8" }, 1396 { { "9" }, "r9" }, 1397 { { "10" }, "r10" }, 1398 { { "11" }, "r11" }, 1399 { { "12" }, "r12" }, 1400 { { "13" }, "r13" }, 1401 { { "14" }, "r14" }, 1402 { { "15" }, "r15" }, 1403 { { "16" }, "r16" }, 1404 { { "17" }, "r17" }, 1405 { { "18" }, "r18" }, 1406 { { "19" }, "r19" }, 1407 { { "20" }, "r20" }, 1408 { { "21" }, "r21" }, 1409 { { "22" }, "r22" }, 1410 { { "23" }, "r23" }, 1411 { { "24" }, "r24" }, 1412 { { "25" }, "r25" }, 1413 { { "26" }, "r26" }, 1414 { { "27" }, "r27" }, 1415 { { "28" }, "r28" }, 1416 { { "29" }, "r29" }, 1417 { { "30" }, "r30" }, 1418 { { "31" }, "r31" }, 1419 { { "fr0" }, "f0" }, 1420 { { "fr1" }, "f1" }, 1421 { { "fr2" }, "f2" }, 1422 { { "fr3" }, "f3" }, 1423 { { "fr4" }, "f4" }, 1424 { { "fr5" }, "f5" }, 1425 { { "fr6" }, "f6" }, 1426 { { "fr7" }, "f7" }, 1427 { { "fr8" }, "f8" }, 1428 { { "fr9" }, "f9" }, 1429 { { "fr10" }, "f10" }, 1430 { { "fr11" }, "f11" }, 1431 { { "fr12" }, "f12" }, 1432 { { "fr13" }, "f13" }, 1433 { { "fr14" }, "f14" }, 1434 { { "fr15" }, "f15" }, 1435 { { "fr16" }, "f16" }, 1436 { { "fr17" }, "f17" }, 1437 { { "fr18" }, "f18" }, 1438 { { "fr19" }, "f19" }, 1439 { { "fr20" }, "f20" }, 1440 { { "fr21" }, "f21" }, 1441 { { "fr22" }, "f22" }, 1442 { { "fr23" }, "f23" }, 1443 { { "fr24" }, "f24" }, 1444 { { "fr25" }, "f25" }, 1445 { { "fr26" }, "f26" }, 1446 { { "fr27" }, "f27" }, 1447 { { "fr28" }, "f28" }, 1448 { { "fr29" }, "f29" }, 1449 { { "fr30" }, "f30" }, 1450 { { "fr31" }, "f31" }, 1451 { { "cc" }, "cr0" }, 1452 }; 1453 1454 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1455 unsigned &NumAliases) const { 1456 Aliases = GCCRegAliases; 1457 NumAliases = llvm::array_lengthof(GCCRegAliases); 1458 } 1459 1460 class PPC32TargetInfo : public PPCTargetInfo { 1461 public: 1462 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1463 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1464 1465 switch (getTriple().getOS()) { 1466 case llvm::Triple::Linux: 1467 case llvm::Triple::FreeBSD: 1468 case llvm::Triple::NetBSD: 1469 SizeType = UnsignedInt; 1470 PtrDiffType = SignedInt; 1471 IntPtrType = SignedInt; 1472 break; 1473 default: 1474 break; 1475 } 1476 1477 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1478 LongDoubleWidth = LongDoubleAlign = 64; 1479 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1480 } 1481 1482 // PPC32 supports atomics up to 4 bytes. 1483 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1484 } 1485 1486 BuiltinVaListKind getBuiltinVaListKind() const override { 1487 // This is the ELF definition, and is overridden by the Darwin sub-target 1488 return TargetInfo::PowerABIBuiltinVaList; 1489 } 1490 }; 1491 1492 // Note: ABI differences may eventually require us to have a separate 1493 // TargetInfo for little endian. 1494 class PPC64TargetInfo : public PPCTargetInfo { 1495 public: 1496 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1497 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1498 IntMaxType = SignedLong; 1499 Int64Type = SignedLong; 1500 1501 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1502 DataLayoutString = "e-m:e-i64:64-n32:64"; 1503 ABI = "elfv2"; 1504 } else { 1505 DataLayoutString = "E-m:e-i64:64-n32:64"; 1506 ABI = "elfv1"; 1507 } 1508 1509 switch (getTriple().getOS()) { 1510 case llvm::Triple::FreeBSD: 1511 LongDoubleWidth = LongDoubleAlign = 64; 1512 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1513 break; 1514 case llvm::Triple::NetBSD: 1515 IntMaxType = SignedLongLong; 1516 Int64Type = SignedLongLong; 1517 break; 1518 default: 1519 break; 1520 } 1521 1522 // PPC64 supports atomics up to 8 bytes. 1523 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1524 } 1525 BuiltinVaListKind getBuiltinVaListKind() const override { 1526 return TargetInfo::CharPtrBuiltinVaList; 1527 } 1528 // PPC64 Linux-specific ABI options. 1529 bool setABI(const std::string &Name) override { 1530 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1531 ABI = Name; 1532 return true; 1533 } 1534 return false; 1535 } 1536 }; 1537 1538 class DarwinPPC32TargetInfo : 1539 public DarwinTargetInfo<PPC32TargetInfo> { 1540 public: 1541 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1542 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1543 HasAlignMac68kSupport = true; 1544 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1545 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1546 LongLongAlign = 32; 1547 SuitableAlign = 128; 1548 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1549 } 1550 BuiltinVaListKind getBuiltinVaListKind() const override { 1551 return TargetInfo::CharPtrBuiltinVaList; 1552 } 1553 }; 1554 1555 class DarwinPPC64TargetInfo : 1556 public DarwinTargetInfo<PPC64TargetInfo> { 1557 public: 1558 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1559 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1560 HasAlignMac68kSupport = true; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-i64:64-n32:64"; 1563 } 1564 }; 1565 1566 static const unsigned NVPTXAddrSpaceMap[] = { 1567 1, // opencl_global 1568 3, // opencl_local 1569 4, // opencl_constant 1570 // FIXME: generic has to be added to the target 1571 0, // opencl_generic 1572 1, // cuda_device 1573 4, // cuda_constant 1574 3, // cuda_shared 1575 }; 1576 class NVPTXTargetInfo : public TargetInfo { 1577 static const char * const GCCRegNames[]; 1578 static const Builtin::Info BuiltinInfo[]; 1579 1580 // The GPU profiles supported by the NVPTX backend 1581 enum GPUKind { 1582 GK_NONE, 1583 GK_SM20, 1584 GK_SM21, 1585 GK_SM30, 1586 GK_SM35, 1587 GK_SM37, 1588 } GPU; 1589 1590 public: 1591 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1592 BigEndian = false; 1593 TLSSupported = false; 1594 LongWidth = LongAlign = 64; 1595 AddrSpaceMap = &NVPTXAddrSpaceMap; 1596 UseAddrSpaceMapMangling = true; 1597 // Define available target features 1598 // These must be defined in sorted order! 1599 NoAsmVariants = true; 1600 // Set the default GPU to sm20 1601 GPU = GK_SM20; 1602 } 1603 void getTargetDefines(const LangOptions &Opts, 1604 MacroBuilder &Builder) const override { 1605 Builder.defineMacro("__PTX__"); 1606 Builder.defineMacro("__NVPTX__"); 1607 if (Opts.CUDAIsDevice) { 1608 // Set __CUDA_ARCH__ for the GPU specified. 1609 std::string CUDAArchCode; 1610 switch (GPU) { 1611 case GK_SM20: 1612 CUDAArchCode = "200"; 1613 break; 1614 case GK_SM21: 1615 CUDAArchCode = "210"; 1616 break; 1617 case GK_SM30: 1618 CUDAArchCode = "300"; 1619 break; 1620 case GK_SM35: 1621 CUDAArchCode = "350"; 1622 break; 1623 case GK_SM37: 1624 CUDAArchCode = "370"; 1625 break; 1626 default: 1627 llvm_unreachable("Unhandled target CPU"); 1628 } 1629 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1630 } 1631 } 1632 void getTargetBuiltins(const Builtin::Info *&Records, 1633 unsigned &NumRecords) const override { 1634 Records = BuiltinInfo; 1635 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1636 } 1637 bool hasFeature(StringRef Feature) const override { 1638 return Feature == "ptx" || Feature == "nvptx"; 1639 } 1640 1641 void getGCCRegNames(const char * const *&Names, 1642 unsigned &NumNames) const override; 1643 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1644 unsigned &NumAliases) const override { 1645 // No aliases. 1646 Aliases = nullptr; 1647 NumAliases = 0; 1648 } 1649 bool 1650 validateAsmConstraint(const char *&Name, 1651 TargetInfo::ConstraintInfo &Info) const override { 1652 switch (*Name) { 1653 default: return false; 1654 case 'c': 1655 case 'h': 1656 case 'r': 1657 case 'l': 1658 case 'f': 1659 case 'd': 1660 Info.setAllowsRegister(); 1661 return true; 1662 } 1663 } 1664 const char *getClobbers() const override { 1665 // FIXME: Is this really right? 1666 return ""; 1667 } 1668 BuiltinVaListKind getBuiltinVaListKind() const override { 1669 // FIXME: implement 1670 return TargetInfo::CharPtrBuiltinVaList; 1671 } 1672 bool setCPU(const std::string &Name) override { 1673 GPU = llvm::StringSwitch<GPUKind>(Name) 1674 .Case("sm_20", GK_SM20) 1675 .Case("sm_21", GK_SM21) 1676 .Case("sm_30", GK_SM30) 1677 .Case("sm_35", GK_SM35) 1678 .Case("sm_37", GK_SM37) 1679 .Default(GK_NONE); 1680 1681 return GPU != GK_NONE; 1682 } 1683 }; 1684 1685 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1686 #define BUILTIN(ID, TYPE, ATTRS) \ 1687 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1688 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1689 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1690 #include "clang/Basic/BuiltinsNVPTX.def" 1691 }; 1692 1693 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1694 "r0" 1695 }; 1696 1697 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1698 unsigned &NumNames) const { 1699 Names = GCCRegNames; 1700 NumNames = llvm::array_lengthof(GCCRegNames); 1701 } 1702 1703 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1704 public: 1705 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1706 PointerWidth = PointerAlign = 32; 1707 SizeType = TargetInfo::UnsignedInt; 1708 PtrDiffType = TargetInfo::SignedInt; 1709 IntPtrType = TargetInfo::SignedInt; 1710 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1711 } 1712 }; 1713 1714 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1715 public: 1716 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1717 PointerWidth = PointerAlign = 64; 1718 SizeType = TargetInfo::UnsignedLong; 1719 PtrDiffType = TargetInfo::SignedLong; 1720 IntPtrType = TargetInfo::SignedLong; 1721 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1722 } 1723 }; 1724 1725 static const unsigned AMDGPUAddrSpaceMap[] = { 1726 1, // opencl_global 1727 3, // opencl_local 1728 2, // opencl_constant 1729 4, // opencl_generic 1730 1, // cuda_device 1731 2, // cuda_constant 1732 3 // cuda_shared 1733 }; 1734 1735 // If you edit the description strings, make sure you update 1736 // getPointerWidthV(). 1737 1738 static const char *DataLayoutStringR600 = 1739 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1740 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1741 1742 static const char *DataLayoutStringR600DoubleOps = 1743 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1744 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1745 1746 static const char *DataLayoutStringSI = 1747 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1748 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1749 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1750 1751 class AMDGPUTargetInfo : public TargetInfo { 1752 static const Builtin::Info BuiltinInfo[]; 1753 static const char * const GCCRegNames[]; 1754 1755 /// \brief The GPU profiles supported by the AMDGPU target. 1756 enum GPUKind { 1757 GK_NONE, 1758 GK_R600, 1759 GK_R600_DOUBLE_OPS, 1760 GK_R700, 1761 GK_R700_DOUBLE_OPS, 1762 GK_EVERGREEN, 1763 GK_EVERGREEN_DOUBLE_OPS, 1764 GK_NORTHERN_ISLANDS, 1765 GK_CAYMAN, 1766 GK_SOUTHERN_ISLANDS, 1767 GK_SEA_ISLANDS, 1768 GK_VOLCANIC_ISLANDS 1769 } GPU; 1770 1771 bool hasFP64:1; 1772 bool hasFMAF:1; 1773 bool hasLDEXPF:1; 1774 1775 public: 1776 AMDGPUTargetInfo(const llvm::Triple &Triple) 1777 : TargetInfo(Triple) { 1778 1779 if (Triple.getArch() == llvm::Triple::amdgcn) { 1780 DataLayoutString = DataLayoutStringSI; 1781 GPU = GK_SOUTHERN_ISLANDS; 1782 hasFP64 = true; 1783 hasFMAF = true; 1784 hasLDEXPF = true; 1785 } else { 1786 DataLayoutString = DataLayoutStringR600; 1787 GPU = GK_R600; 1788 hasFP64 = false; 1789 hasFMAF = false; 1790 hasLDEXPF = false; 1791 } 1792 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1793 UseAddrSpaceMapMangling = true; 1794 } 1795 1796 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1797 if (GPU <= GK_CAYMAN) 1798 return 32; 1799 1800 switch(AddrSpace) { 1801 default: 1802 return 64; 1803 case 0: 1804 case 3: 1805 case 5: 1806 return 32; 1807 } 1808 } 1809 1810 const char * getClobbers() const override { 1811 return ""; 1812 } 1813 1814 void getGCCRegNames(const char * const *&Names, 1815 unsigned &NumNames) const override; 1816 1817 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1818 unsigned &NumAliases) const override { 1819 Aliases = nullptr; 1820 NumAliases = 0; 1821 } 1822 1823 bool validateAsmConstraint(const char *&Name, 1824 TargetInfo::ConstraintInfo &info) const override { 1825 return true; 1826 } 1827 1828 void getTargetBuiltins(const Builtin::Info *&Records, 1829 unsigned &NumRecords) const override { 1830 Records = BuiltinInfo; 1831 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1832 } 1833 1834 void getTargetDefines(const LangOptions &Opts, 1835 MacroBuilder &Builder) const override { 1836 Builder.defineMacro("__R600__"); 1837 if (hasFMAF) 1838 Builder.defineMacro("__HAS_FMAF__"); 1839 if (hasLDEXPF) 1840 Builder.defineMacro("__HAS_LDEXPF__"); 1841 if (hasFP64 && Opts.OpenCL) 1842 Builder.defineMacro("cl_khr_fp64"); 1843 if (Opts.OpenCL) { 1844 if (GPU >= GK_NORTHERN_ISLANDS) { 1845 Builder.defineMacro("cl_khr_byte_addressable_store"); 1846 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1847 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1848 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1849 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1850 } 1851 } 1852 } 1853 1854 BuiltinVaListKind getBuiltinVaListKind() const override { 1855 return TargetInfo::CharPtrBuiltinVaList; 1856 } 1857 1858 bool setCPU(const std::string &Name) override { 1859 GPU = llvm::StringSwitch<GPUKind>(Name) 1860 .Case("r600" , GK_R600) 1861 .Case("rv610", GK_R600) 1862 .Case("rv620", GK_R600) 1863 .Case("rv630", GK_R600) 1864 .Case("rv635", GK_R600) 1865 .Case("rs780", GK_R600) 1866 .Case("rs880", GK_R600) 1867 .Case("rv670", GK_R600_DOUBLE_OPS) 1868 .Case("rv710", GK_R700) 1869 .Case("rv730", GK_R700) 1870 .Case("rv740", GK_R700_DOUBLE_OPS) 1871 .Case("rv770", GK_R700_DOUBLE_OPS) 1872 .Case("palm", GK_EVERGREEN) 1873 .Case("cedar", GK_EVERGREEN) 1874 .Case("sumo", GK_EVERGREEN) 1875 .Case("sumo2", GK_EVERGREEN) 1876 .Case("redwood", GK_EVERGREEN) 1877 .Case("juniper", GK_EVERGREEN) 1878 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1879 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1880 .Case("barts", GK_NORTHERN_ISLANDS) 1881 .Case("turks", GK_NORTHERN_ISLANDS) 1882 .Case("caicos", GK_NORTHERN_ISLANDS) 1883 .Case("cayman", GK_CAYMAN) 1884 .Case("aruba", GK_CAYMAN) 1885 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1886 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1887 .Case("verde", GK_SOUTHERN_ISLANDS) 1888 .Case("oland", GK_SOUTHERN_ISLANDS) 1889 .Case("hainan", GK_SOUTHERN_ISLANDS) 1890 .Case("bonaire", GK_SEA_ISLANDS) 1891 .Case("kabini", GK_SEA_ISLANDS) 1892 .Case("kaveri", GK_SEA_ISLANDS) 1893 .Case("hawaii", GK_SEA_ISLANDS) 1894 .Case("mullins", GK_SEA_ISLANDS) 1895 .Case("tonga", GK_VOLCANIC_ISLANDS) 1896 .Case("iceland", GK_VOLCANIC_ISLANDS) 1897 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1898 .Default(GK_NONE); 1899 1900 if (GPU == GK_NONE) { 1901 return false; 1902 } 1903 1904 // Set the correct data layout 1905 switch (GPU) { 1906 case GK_NONE: 1907 case GK_R600: 1908 case GK_R700: 1909 case GK_EVERGREEN: 1910 case GK_NORTHERN_ISLANDS: 1911 DataLayoutString = DataLayoutStringR600; 1912 hasFP64 = false; 1913 hasFMAF = false; 1914 hasLDEXPF = false; 1915 break; 1916 case GK_R600_DOUBLE_OPS: 1917 case GK_R700_DOUBLE_OPS: 1918 case GK_EVERGREEN_DOUBLE_OPS: 1919 case GK_CAYMAN: 1920 DataLayoutString = DataLayoutStringR600DoubleOps; 1921 hasFP64 = true; 1922 hasFMAF = true; 1923 hasLDEXPF = false; 1924 break; 1925 case GK_SOUTHERN_ISLANDS: 1926 case GK_SEA_ISLANDS: 1927 case GK_VOLCANIC_ISLANDS: 1928 DataLayoutString = DataLayoutStringSI; 1929 hasFP64 = true; 1930 hasFMAF = true; 1931 hasLDEXPF = true; 1932 break; 1933 } 1934 1935 return true; 1936 } 1937 }; 1938 1939 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1940 #define BUILTIN(ID, TYPE, ATTRS) \ 1941 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1942 #include "clang/Basic/BuiltinsAMDGPU.def" 1943 }; 1944 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1945 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1946 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1947 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1948 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1949 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1950 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1951 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1952 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1953 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1954 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1955 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1956 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1957 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1958 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1959 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1960 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1961 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1962 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1963 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1964 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1965 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1966 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1967 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1968 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1969 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1970 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1971 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1972 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1973 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1974 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1975 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1976 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1977 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1978 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1979 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1980 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1981 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1982 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1983 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1984 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1985 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1986 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1987 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1988 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1989 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1990 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1991 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1992 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1993 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1994 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1995 }; 1996 1997 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1998 unsigned &NumNames) const { 1999 Names = GCCRegNames; 2000 NumNames = llvm::array_lengthof(GCCRegNames); 2001 } 2002 2003 // Namespace for x86 abstract base class 2004 const Builtin::Info BuiltinInfo[] = { 2005 #define BUILTIN(ID, TYPE, ATTRS) \ 2006 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2007 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2008 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2009 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2010 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2011 #include "clang/Basic/BuiltinsX86.def" 2012 }; 2013 2014 static const char* const GCCRegNames[] = { 2015 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2016 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2017 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2018 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2019 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2020 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2021 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2022 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2023 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2024 }; 2025 2026 const TargetInfo::AddlRegName AddlRegNames[] = { 2027 { { "al", "ah", "eax", "rax" }, 0 }, 2028 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2029 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2030 { { "dl", "dh", "edx", "rdx" }, 1 }, 2031 { { "esi", "rsi" }, 4 }, 2032 { { "edi", "rdi" }, 5 }, 2033 { { "esp", "rsp" }, 7 }, 2034 { { "ebp", "rbp" }, 6 }, 2035 }; 2036 2037 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2038 // most of the implementation can be shared. 2039 class X86TargetInfo : public TargetInfo { 2040 enum X86SSEEnum { 2041 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2042 } SSELevel; 2043 enum MMX3DNowEnum { 2044 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2045 } MMX3DNowLevel; 2046 enum XOPEnum { 2047 NoXOP, 2048 SSE4A, 2049 FMA4, 2050 XOP 2051 } XOPLevel; 2052 2053 bool HasAES; 2054 bool HasPCLMUL; 2055 bool HasLZCNT; 2056 bool HasRDRND; 2057 bool HasFSGSBASE; 2058 bool HasBMI; 2059 bool HasBMI2; 2060 bool HasPOPCNT; 2061 bool HasRTM; 2062 bool HasPRFCHW; 2063 bool HasRDSEED; 2064 bool HasADX; 2065 bool HasTBM; 2066 bool HasFMA; 2067 bool HasF16C; 2068 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2069 HasAVX512VL; 2070 bool HasSHA; 2071 bool HasCX16; 2072 2073 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2074 /// 2075 /// Each enumeration represents a particular CPU supported by Clang. These 2076 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2077 enum CPUKind { 2078 CK_Generic, 2079 2080 /// \name i386 2081 /// i386-generation processors. 2082 //@{ 2083 CK_i386, 2084 //@} 2085 2086 /// \name i486 2087 /// i486-generation processors. 2088 //@{ 2089 CK_i486, 2090 CK_WinChipC6, 2091 CK_WinChip2, 2092 CK_C3, 2093 //@} 2094 2095 /// \name i586 2096 /// i586-generation processors, P5 microarchitecture based. 2097 //@{ 2098 CK_i586, 2099 CK_Pentium, 2100 CK_PentiumMMX, 2101 //@} 2102 2103 /// \name i686 2104 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2105 //@{ 2106 CK_i686, 2107 CK_PentiumPro, 2108 CK_Pentium2, 2109 CK_Pentium3, 2110 CK_Pentium3M, 2111 CK_PentiumM, 2112 CK_C3_2, 2113 2114 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2115 /// Clang however has some logic to suport this. 2116 // FIXME: Warn, deprecate, and potentially remove this. 2117 CK_Yonah, 2118 //@} 2119 2120 /// \name Netburst 2121 /// Netburst microarchitecture based processors. 2122 //@{ 2123 CK_Pentium4, 2124 CK_Pentium4M, 2125 CK_Prescott, 2126 CK_Nocona, 2127 //@} 2128 2129 /// \name Core 2130 /// Core microarchitecture based processors. 2131 //@{ 2132 CK_Core2, 2133 2134 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2135 /// codename which GCC no longer accepts as an option to -march, but Clang 2136 /// has some logic for recognizing it. 2137 // FIXME: Warn, deprecate, and potentially remove this. 2138 CK_Penryn, 2139 //@} 2140 2141 /// \name Atom 2142 /// Atom processors 2143 //@{ 2144 CK_Bonnell, 2145 CK_Silvermont, 2146 //@} 2147 2148 /// \name Nehalem 2149 /// Nehalem microarchitecture based processors. 2150 CK_Nehalem, 2151 2152 /// \name Westmere 2153 /// Westmere microarchitecture based processors. 2154 CK_Westmere, 2155 2156 /// \name Sandy Bridge 2157 /// Sandy Bridge microarchitecture based processors. 2158 CK_SandyBridge, 2159 2160 /// \name Ivy Bridge 2161 /// Ivy Bridge microarchitecture based processors. 2162 CK_IvyBridge, 2163 2164 /// \name Haswell 2165 /// Haswell microarchitecture based processors. 2166 CK_Haswell, 2167 2168 /// \name Broadwell 2169 /// Broadwell microarchitecture based processors. 2170 CK_Broadwell, 2171 2172 /// \name Skylake 2173 /// Skylake microarchitecture based processors. 2174 CK_Skylake, 2175 2176 /// \name Knights Landing 2177 /// Knights Landing processor. 2178 CK_KNL, 2179 2180 /// \name K6 2181 /// K6 architecture processors. 2182 //@{ 2183 CK_K6, 2184 CK_K6_2, 2185 CK_K6_3, 2186 //@} 2187 2188 /// \name K7 2189 /// K7 architecture processors. 2190 //@{ 2191 CK_Athlon, 2192 CK_AthlonThunderbird, 2193 CK_Athlon4, 2194 CK_AthlonXP, 2195 CK_AthlonMP, 2196 //@} 2197 2198 /// \name K8 2199 /// K8 architecture processors. 2200 //@{ 2201 CK_Athlon64, 2202 CK_Athlon64SSE3, 2203 CK_AthlonFX, 2204 CK_K8, 2205 CK_K8SSE3, 2206 CK_Opteron, 2207 CK_OpteronSSE3, 2208 CK_AMDFAM10, 2209 //@} 2210 2211 /// \name Bobcat 2212 /// Bobcat architecture processors. 2213 //@{ 2214 CK_BTVER1, 2215 CK_BTVER2, 2216 //@} 2217 2218 /// \name Bulldozer 2219 /// Bulldozer architecture processors. 2220 //@{ 2221 CK_BDVER1, 2222 CK_BDVER2, 2223 CK_BDVER3, 2224 CK_BDVER4, 2225 //@} 2226 2227 /// This specification is deprecated and will be removed in the future. 2228 /// Users should prefer \see CK_K8. 2229 // FIXME: Warn on this when the CPU is set to it. 2230 //@{ 2231 CK_x86_64, 2232 //@} 2233 2234 /// \name Geode 2235 /// Geode processors. 2236 //@{ 2237 CK_Geode 2238 //@} 2239 } CPU; 2240 2241 enum FPMathKind { 2242 FP_Default, 2243 FP_SSE, 2244 FP_387 2245 } FPMath; 2246 2247 public: 2248 X86TargetInfo(const llvm::Triple &Triple) 2249 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2250 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2251 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2252 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2253 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2254 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2255 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2256 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2257 BigEndian = false; 2258 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2259 } 2260 unsigned getFloatEvalMethod() const override { 2261 // X87 evaluates with 80 bits "long double" precision. 2262 return SSELevel == NoSSE ? 2 : 0; 2263 } 2264 void getTargetBuiltins(const Builtin::Info *&Records, 2265 unsigned &NumRecords) const override { 2266 Records = BuiltinInfo; 2267 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2268 } 2269 void getGCCRegNames(const char * const *&Names, 2270 unsigned &NumNames) const override { 2271 Names = GCCRegNames; 2272 NumNames = llvm::array_lengthof(GCCRegNames); 2273 } 2274 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2275 unsigned &NumAliases) const override { 2276 Aliases = nullptr; 2277 NumAliases = 0; 2278 } 2279 void getGCCAddlRegNames(const AddlRegName *&Names, 2280 unsigned &NumNames) const override { 2281 Names = AddlRegNames; 2282 NumNames = llvm::array_lengthof(AddlRegNames); 2283 } 2284 bool validateCpuSupports(StringRef Name) const override; 2285 bool validateAsmConstraint(const char *&Name, 2286 TargetInfo::ConstraintInfo &info) const override; 2287 2288 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2289 2290 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2291 2292 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2293 2294 std::string convertConstraint(const char *&Constraint) const override; 2295 const char *getClobbers() const override { 2296 return "~{dirflag},~{fpsr},~{flags}"; 2297 } 2298 void getTargetDefines(const LangOptions &Opts, 2299 MacroBuilder &Builder) const override; 2300 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2301 bool Enabled); 2302 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2303 bool Enabled); 2304 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2305 bool Enabled); 2306 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2307 StringRef Name, bool Enabled) const override { 2308 setFeatureEnabledImpl(Features, Name, Enabled); 2309 } 2310 // This exists purely to cut down on the number of virtual calls in 2311 // initDefaultFeatures which calls this repeatedly. 2312 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2313 StringRef Name, bool Enabled); 2314 void initDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2315 bool hasFeature(StringRef Feature) const override; 2316 bool handleTargetFeatures(std::vector<std::string> &Features, 2317 DiagnosticsEngine &Diags) override; 2318 StringRef getABI() const override { 2319 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2320 return "avx512"; 2321 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2322 return "avx"; 2323 else if (getTriple().getArch() == llvm::Triple::x86 && 2324 MMX3DNowLevel == NoMMX3DNow) 2325 return "no-mmx"; 2326 return ""; 2327 } 2328 bool setCPU(const std::string &Name) override { 2329 CPU = llvm::StringSwitch<CPUKind>(Name) 2330 .Case("i386", CK_i386) 2331 .Case("i486", CK_i486) 2332 .Case("winchip-c6", CK_WinChipC6) 2333 .Case("winchip2", CK_WinChip2) 2334 .Case("c3", CK_C3) 2335 .Case("i586", CK_i586) 2336 .Case("pentium", CK_Pentium) 2337 .Case("pentium-mmx", CK_PentiumMMX) 2338 .Case("i686", CK_i686) 2339 .Case("pentiumpro", CK_PentiumPro) 2340 .Case("pentium2", CK_Pentium2) 2341 .Case("pentium3", CK_Pentium3) 2342 .Case("pentium3m", CK_Pentium3M) 2343 .Case("pentium-m", CK_PentiumM) 2344 .Case("c3-2", CK_C3_2) 2345 .Case("yonah", CK_Yonah) 2346 .Case("pentium4", CK_Pentium4) 2347 .Case("pentium4m", CK_Pentium4M) 2348 .Case("prescott", CK_Prescott) 2349 .Case("nocona", CK_Nocona) 2350 .Case("core2", CK_Core2) 2351 .Case("penryn", CK_Penryn) 2352 .Case("bonnell", CK_Bonnell) 2353 .Case("atom", CK_Bonnell) // Legacy name. 2354 .Case("silvermont", CK_Silvermont) 2355 .Case("slm", CK_Silvermont) // Legacy name. 2356 .Case("nehalem", CK_Nehalem) 2357 .Case("corei7", CK_Nehalem) // Legacy name. 2358 .Case("westmere", CK_Westmere) 2359 .Case("sandybridge", CK_SandyBridge) 2360 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2361 .Case("ivybridge", CK_IvyBridge) 2362 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2363 .Case("haswell", CK_Haswell) 2364 .Case("core-avx2", CK_Haswell) // Legacy name. 2365 .Case("broadwell", CK_Broadwell) 2366 .Case("skylake", CK_Skylake) 2367 .Case("skx", CK_Skylake) // Legacy name. 2368 .Case("knl", CK_KNL) 2369 .Case("k6", CK_K6) 2370 .Case("k6-2", CK_K6_2) 2371 .Case("k6-3", CK_K6_3) 2372 .Case("athlon", CK_Athlon) 2373 .Case("athlon-tbird", CK_AthlonThunderbird) 2374 .Case("athlon-4", CK_Athlon4) 2375 .Case("athlon-xp", CK_AthlonXP) 2376 .Case("athlon-mp", CK_AthlonMP) 2377 .Case("athlon64", CK_Athlon64) 2378 .Case("athlon64-sse3", CK_Athlon64SSE3) 2379 .Case("athlon-fx", CK_AthlonFX) 2380 .Case("k8", CK_K8) 2381 .Case("k8-sse3", CK_K8SSE3) 2382 .Case("opteron", CK_Opteron) 2383 .Case("opteron-sse3", CK_OpteronSSE3) 2384 .Case("barcelona", CK_AMDFAM10) 2385 .Case("amdfam10", CK_AMDFAM10) 2386 .Case("btver1", CK_BTVER1) 2387 .Case("btver2", CK_BTVER2) 2388 .Case("bdver1", CK_BDVER1) 2389 .Case("bdver2", CK_BDVER2) 2390 .Case("bdver3", CK_BDVER3) 2391 .Case("bdver4", CK_BDVER4) 2392 .Case("x86-64", CK_x86_64) 2393 .Case("geode", CK_Geode) 2394 .Default(CK_Generic); 2395 2396 // Perform any per-CPU checks necessary to determine if this CPU is 2397 // acceptable. 2398 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2399 // invalid without explaining *why*. 2400 switch (CPU) { 2401 case CK_Generic: 2402 // No processor selected! 2403 return false; 2404 2405 case CK_i386: 2406 case CK_i486: 2407 case CK_WinChipC6: 2408 case CK_WinChip2: 2409 case CK_C3: 2410 case CK_i586: 2411 case CK_Pentium: 2412 case CK_PentiumMMX: 2413 case CK_i686: 2414 case CK_PentiumPro: 2415 case CK_Pentium2: 2416 case CK_Pentium3: 2417 case CK_Pentium3M: 2418 case CK_PentiumM: 2419 case CK_Yonah: 2420 case CK_C3_2: 2421 case CK_Pentium4: 2422 case CK_Pentium4M: 2423 case CK_Prescott: 2424 case CK_K6: 2425 case CK_K6_2: 2426 case CK_K6_3: 2427 case CK_Athlon: 2428 case CK_AthlonThunderbird: 2429 case CK_Athlon4: 2430 case CK_AthlonXP: 2431 case CK_AthlonMP: 2432 case CK_Geode: 2433 // Only accept certain architectures when compiling in 32-bit mode. 2434 if (getTriple().getArch() != llvm::Triple::x86) 2435 return false; 2436 2437 // Fallthrough 2438 case CK_Nocona: 2439 case CK_Core2: 2440 case CK_Penryn: 2441 case CK_Bonnell: 2442 case CK_Silvermont: 2443 case CK_Nehalem: 2444 case CK_Westmere: 2445 case CK_SandyBridge: 2446 case CK_IvyBridge: 2447 case CK_Haswell: 2448 case CK_Broadwell: 2449 case CK_Skylake: 2450 case CK_KNL: 2451 case CK_Athlon64: 2452 case CK_Athlon64SSE3: 2453 case CK_AthlonFX: 2454 case CK_K8: 2455 case CK_K8SSE3: 2456 case CK_Opteron: 2457 case CK_OpteronSSE3: 2458 case CK_AMDFAM10: 2459 case CK_BTVER1: 2460 case CK_BTVER2: 2461 case CK_BDVER1: 2462 case CK_BDVER2: 2463 case CK_BDVER3: 2464 case CK_BDVER4: 2465 case CK_x86_64: 2466 return true; 2467 } 2468 llvm_unreachable("Unhandled CPU kind"); 2469 } 2470 2471 bool setFPMath(StringRef Name) override; 2472 2473 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2474 // We accept all non-ARM calling conventions 2475 return (CC == CC_X86ThisCall || 2476 CC == CC_X86FastCall || 2477 CC == CC_X86StdCall || 2478 CC == CC_X86VectorCall || 2479 CC == CC_C || 2480 CC == CC_X86Pascal || 2481 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2482 } 2483 2484 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2485 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2486 } 2487 2488 bool hasSjLjLowering() const override { 2489 return true; 2490 } 2491 }; 2492 2493 bool X86TargetInfo::setFPMath(StringRef Name) { 2494 if (Name == "387") { 2495 FPMath = FP_387; 2496 return true; 2497 } 2498 if (Name == "sse") { 2499 FPMath = FP_SSE; 2500 return true; 2501 } 2502 return false; 2503 } 2504 2505 void X86TargetInfo::initDefaultFeatures(llvm::StringMap<bool> &Features) const { 2506 // FIXME: This *really* should not be here. 2507 2508 // X86_64 always has SSE2. 2509 if (getTriple().getArch() == llvm::Triple::x86_64) 2510 setFeatureEnabledImpl(Features, "sse2", true); 2511 2512 switch (CPU) { 2513 case CK_Generic: 2514 case CK_i386: 2515 case CK_i486: 2516 case CK_i586: 2517 case CK_Pentium: 2518 case CK_i686: 2519 case CK_PentiumPro: 2520 break; 2521 case CK_PentiumMMX: 2522 case CK_Pentium2: 2523 case CK_K6: 2524 case CK_WinChipC6: 2525 setFeatureEnabledImpl(Features, "mmx", true); 2526 break; 2527 case CK_Pentium3: 2528 case CK_Pentium3M: 2529 case CK_C3_2: 2530 setFeatureEnabledImpl(Features, "sse", true); 2531 break; 2532 case CK_PentiumM: 2533 case CK_Pentium4: 2534 case CK_Pentium4M: 2535 case CK_x86_64: 2536 setFeatureEnabledImpl(Features, "sse2", true); 2537 break; 2538 case CK_Yonah: 2539 case CK_Prescott: 2540 case CK_Nocona: 2541 setFeatureEnabledImpl(Features, "sse3", true); 2542 setFeatureEnabledImpl(Features, "cx16", true); 2543 break; 2544 case CK_Core2: 2545 case CK_Bonnell: 2546 setFeatureEnabledImpl(Features, "ssse3", true); 2547 setFeatureEnabledImpl(Features, "cx16", true); 2548 break; 2549 case CK_Penryn: 2550 setFeatureEnabledImpl(Features, "sse4.1", true); 2551 setFeatureEnabledImpl(Features, "cx16", true); 2552 break; 2553 case CK_Skylake: 2554 setFeatureEnabledImpl(Features, "avx512f", true); 2555 setFeatureEnabledImpl(Features, "avx512cd", true); 2556 setFeatureEnabledImpl(Features, "avx512dq", true); 2557 setFeatureEnabledImpl(Features, "avx512bw", true); 2558 setFeatureEnabledImpl(Features, "avx512vl", true); 2559 // FALLTHROUGH 2560 case CK_Broadwell: 2561 setFeatureEnabledImpl(Features, "rdseed", true); 2562 setFeatureEnabledImpl(Features, "adx", true); 2563 // FALLTHROUGH 2564 case CK_Haswell: 2565 setFeatureEnabledImpl(Features, "avx2", true); 2566 setFeatureEnabledImpl(Features, "lzcnt", true); 2567 setFeatureEnabledImpl(Features, "bmi", true); 2568 setFeatureEnabledImpl(Features, "bmi2", true); 2569 setFeatureEnabledImpl(Features, "rtm", true); 2570 setFeatureEnabledImpl(Features, "fma", true); 2571 // FALLTHROUGH 2572 case CK_IvyBridge: 2573 setFeatureEnabledImpl(Features, "rdrnd", true); 2574 setFeatureEnabledImpl(Features, "f16c", true); 2575 setFeatureEnabledImpl(Features, "fsgsbase", true); 2576 // FALLTHROUGH 2577 case CK_SandyBridge: 2578 setFeatureEnabledImpl(Features, "avx", true); 2579 // FALLTHROUGH 2580 case CK_Westmere: 2581 case CK_Silvermont: 2582 setFeatureEnabledImpl(Features, "aes", true); 2583 setFeatureEnabledImpl(Features, "pclmul", true); 2584 // FALLTHROUGH 2585 case CK_Nehalem: 2586 setFeatureEnabledImpl(Features, "sse4.2", true); 2587 setFeatureEnabledImpl(Features, "cx16", true); 2588 break; 2589 case CK_KNL: 2590 setFeatureEnabledImpl(Features, "avx512f", true); 2591 setFeatureEnabledImpl(Features, "avx512cd", true); 2592 setFeatureEnabledImpl(Features, "avx512er", true); 2593 setFeatureEnabledImpl(Features, "avx512pf", true); 2594 setFeatureEnabledImpl(Features, "rdseed", true); 2595 setFeatureEnabledImpl(Features, "adx", true); 2596 setFeatureEnabledImpl(Features, "lzcnt", true); 2597 setFeatureEnabledImpl(Features, "bmi", true); 2598 setFeatureEnabledImpl(Features, "bmi2", true); 2599 setFeatureEnabledImpl(Features, "rtm", true); 2600 setFeatureEnabledImpl(Features, "fma", true); 2601 setFeatureEnabledImpl(Features, "rdrnd", true); 2602 setFeatureEnabledImpl(Features, "f16c", true); 2603 setFeatureEnabledImpl(Features, "fsgsbase", true); 2604 setFeatureEnabledImpl(Features, "aes", true); 2605 setFeatureEnabledImpl(Features, "pclmul", true); 2606 setFeatureEnabledImpl(Features, "cx16", true); 2607 break; 2608 case CK_K6_2: 2609 case CK_K6_3: 2610 case CK_WinChip2: 2611 case CK_C3: 2612 setFeatureEnabledImpl(Features, "3dnow", true); 2613 break; 2614 case CK_Athlon: 2615 case CK_AthlonThunderbird: 2616 case CK_Geode: 2617 setFeatureEnabledImpl(Features, "3dnowa", true); 2618 break; 2619 case CK_Athlon4: 2620 case CK_AthlonXP: 2621 case CK_AthlonMP: 2622 setFeatureEnabledImpl(Features, "sse", true); 2623 setFeatureEnabledImpl(Features, "3dnowa", true); 2624 break; 2625 case CK_K8: 2626 case CK_Opteron: 2627 case CK_Athlon64: 2628 case CK_AthlonFX: 2629 setFeatureEnabledImpl(Features, "sse2", true); 2630 setFeatureEnabledImpl(Features, "3dnowa", true); 2631 break; 2632 case CK_AMDFAM10: 2633 setFeatureEnabledImpl(Features, "sse4a", true); 2634 setFeatureEnabledImpl(Features, "lzcnt", true); 2635 setFeatureEnabledImpl(Features, "popcnt", true); 2636 // FALLTHROUGH 2637 case CK_K8SSE3: 2638 case CK_OpteronSSE3: 2639 case CK_Athlon64SSE3: 2640 setFeatureEnabledImpl(Features, "sse3", true); 2641 setFeatureEnabledImpl(Features, "3dnowa", true); 2642 break; 2643 case CK_BTVER2: 2644 setFeatureEnabledImpl(Features, "avx", true); 2645 setFeatureEnabledImpl(Features, "aes", true); 2646 setFeatureEnabledImpl(Features, "pclmul", true); 2647 setFeatureEnabledImpl(Features, "bmi", true); 2648 setFeatureEnabledImpl(Features, "f16c", true); 2649 // FALLTHROUGH 2650 case CK_BTVER1: 2651 setFeatureEnabledImpl(Features, "ssse3", true); 2652 setFeatureEnabledImpl(Features, "sse4a", true); 2653 setFeatureEnabledImpl(Features, "lzcnt", true); 2654 setFeatureEnabledImpl(Features, "popcnt", true); 2655 setFeatureEnabledImpl(Features, "prfchw", true); 2656 setFeatureEnabledImpl(Features, "cx16", true); 2657 break; 2658 case CK_BDVER4: 2659 setFeatureEnabledImpl(Features, "avx2", true); 2660 setFeatureEnabledImpl(Features, "bmi2", true); 2661 // FALLTHROUGH 2662 case CK_BDVER3: 2663 setFeatureEnabledImpl(Features, "fsgsbase", true); 2664 // FALLTHROUGH 2665 case CK_BDVER2: 2666 setFeatureEnabledImpl(Features, "bmi", true); 2667 setFeatureEnabledImpl(Features, "fma", true); 2668 setFeatureEnabledImpl(Features, "f16c", true); 2669 setFeatureEnabledImpl(Features, "tbm", true); 2670 // FALLTHROUGH 2671 case CK_BDVER1: 2672 // xop implies avx, sse4a and fma4. 2673 setFeatureEnabledImpl(Features, "xop", true); 2674 setFeatureEnabledImpl(Features, "lzcnt", true); 2675 setFeatureEnabledImpl(Features, "aes", true); 2676 setFeatureEnabledImpl(Features, "pclmul", true); 2677 setFeatureEnabledImpl(Features, "prfchw", true); 2678 setFeatureEnabledImpl(Features, "cx16", true); 2679 break; 2680 } 2681 } 2682 2683 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2684 X86SSEEnum Level, bool Enabled) { 2685 if (Enabled) { 2686 switch (Level) { 2687 case AVX512F: 2688 Features["avx512f"] = true; 2689 case AVX2: 2690 Features["avx2"] = true; 2691 case AVX: 2692 Features["avx"] = true; 2693 case SSE42: 2694 Features["sse4.2"] = true; 2695 case SSE41: 2696 Features["sse4.1"] = true; 2697 case SSSE3: 2698 Features["ssse3"] = true; 2699 case SSE3: 2700 Features["sse3"] = true; 2701 case SSE2: 2702 Features["sse2"] = true; 2703 case SSE1: 2704 Features["sse"] = true; 2705 case NoSSE: 2706 break; 2707 } 2708 return; 2709 } 2710 2711 switch (Level) { 2712 case NoSSE: 2713 case SSE1: 2714 Features["sse"] = false; 2715 case SSE2: 2716 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2717 Features["sha"] = false; 2718 case SSE3: 2719 Features["sse3"] = false; 2720 setXOPLevel(Features, NoXOP, false); 2721 case SSSE3: 2722 Features["ssse3"] = false; 2723 case SSE41: 2724 Features["sse4.1"] = false; 2725 case SSE42: 2726 Features["sse4.2"] = false; 2727 case AVX: 2728 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2729 setXOPLevel(Features, FMA4, false); 2730 case AVX2: 2731 Features["avx2"] = false; 2732 case AVX512F: 2733 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2734 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2735 Features["avx512vl"] = false; 2736 } 2737 } 2738 2739 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2740 MMX3DNowEnum Level, bool Enabled) { 2741 if (Enabled) { 2742 switch (Level) { 2743 case AMD3DNowAthlon: 2744 Features["3dnowa"] = true; 2745 case AMD3DNow: 2746 Features["3dnow"] = true; 2747 case MMX: 2748 Features["mmx"] = true; 2749 case NoMMX3DNow: 2750 break; 2751 } 2752 return; 2753 } 2754 2755 switch (Level) { 2756 case NoMMX3DNow: 2757 case MMX: 2758 Features["mmx"] = false; 2759 case AMD3DNow: 2760 Features["3dnow"] = false; 2761 case AMD3DNowAthlon: 2762 Features["3dnowa"] = false; 2763 } 2764 } 2765 2766 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2767 bool Enabled) { 2768 if (Enabled) { 2769 switch (Level) { 2770 case XOP: 2771 Features["xop"] = true; 2772 case FMA4: 2773 Features["fma4"] = true; 2774 setSSELevel(Features, AVX, true); 2775 case SSE4A: 2776 Features["sse4a"] = true; 2777 setSSELevel(Features, SSE3, true); 2778 case NoXOP: 2779 break; 2780 } 2781 return; 2782 } 2783 2784 switch (Level) { 2785 case NoXOP: 2786 case SSE4A: 2787 Features["sse4a"] = false; 2788 case FMA4: 2789 Features["fma4"] = false; 2790 case XOP: 2791 Features["xop"] = false; 2792 } 2793 } 2794 2795 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2796 StringRef Name, bool Enabled) { 2797 // This is a bit of a hack to deal with the sse4 target feature when used 2798 // as part of the target attribute. We handle sse4 correctly everywhere 2799 // else. See below for more information on how we handle the sse4 options. 2800 if (Name != "sse4") 2801 Features[Name] = Enabled; 2802 2803 if (Name == "mmx") { 2804 setMMXLevel(Features, MMX, Enabled); 2805 } else if (Name == "sse") { 2806 setSSELevel(Features, SSE1, Enabled); 2807 } else if (Name == "sse2") { 2808 setSSELevel(Features, SSE2, Enabled); 2809 } else if (Name == "sse3") { 2810 setSSELevel(Features, SSE3, Enabled); 2811 } else if (Name == "ssse3") { 2812 setSSELevel(Features, SSSE3, Enabled); 2813 } else if (Name == "sse4.2") { 2814 setSSELevel(Features, SSE42, Enabled); 2815 } else if (Name == "sse4.1") { 2816 setSSELevel(Features, SSE41, Enabled); 2817 } else if (Name == "3dnow") { 2818 setMMXLevel(Features, AMD3DNow, Enabled); 2819 } else if (Name == "3dnowa") { 2820 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2821 } else if (Name == "aes") { 2822 if (Enabled) 2823 setSSELevel(Features, SSE2, Enabled); 2824 } else if (Name == "pclmul") { 2825 if (Enabled) 2826 setSSELevel(Features, SSE2, Enabled); 2827 } else if (Name == "avx") { 2828 setSSELevel(Features, AVX, Enabled); 2829 } else if (Name == "avx2") { 2830 setSSELevel(Features, AVX2, Enabled); 2831 } else if (Name == "avx512f") { 2832 setSSELevel(Features, AVX512F, Enabled); 2833 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2834 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2835 if (Enabled) 2836 setSSELevel(Features, AVX512F, Enabled); 2837 } else if (Name == "fma") { 2838 if (Enabled) 2839 setSSELevel(Features, AVX, Enabled); 2840 } else if (Name == "fma4") { 2841 setXOPLevel(Features, FMA4, Enabled); 2842 } else if (Name == "xop") { 2843 setXOPLevel(Features, XOP, Enabled); 2844 } else if (Name == "sse4a") { 2845 setXOPLevel(Features, SSE4A, Enabled); 2846 } else if (Name == "f16c") { 2847 if (Enabled) 2848 setSSELevel(Features, AVX, Enabled); 2849 } else if (Name == "sha") { 2850 if (Enabled) 2851 setSSELevel(Features, SSE2, Enabled); 2852 } else if (Name == "sse4") { 2853 // We can get here via the __target__ attribute since that's not controlled 2854 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2855 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2856 // disabled. 2857 if (Enabled) 2858 setSSELevel(Features, SSE42, Enabled); 2859 else 2860 setSSELevel(Features, SSE41, Enabled); 2861 } 2862 } 2863 2864 /// handleTargetFeatures - Perform initialization based on the user 2865 /// configured set of features. 2866 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2867 DiagnosticsEngine &Diags) { 2868 // Remember the maximum enabled sselevel. 2869 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2870 // Ignore disabled features. 2871 if (Features[i][0] == '-') 2872 continue; 2873 2874 StringRef Feature = StringRef(Features[i]).substr(1); 2875 2876 if (Feature == "aes") { 2877 HasAES = true; 2878 continue; 2879 } 2880 2881 if (Feature == "pclmul") { 2882 HasPCLMUL = true; 2883 continue; 2884 } 2885 2886 if (Feature == "lzcnt") { 2887 HasLZCNT = true; 2888 continue; 2889 } 2890 2891 if (Feature == "rdrnd") { 2892 HasRDRND = true; 2893 continue; 2894 } 2895 2896 if (Feature == "fsgsbase") { 2897 HasFSGSBASE = true; 2898 continue; 2899 } 2900 2901 if (Feature == "bmi") { 2902 HasBMI = true; 2903 continue; 2904 } 2905 2906 if (Feature == "bmi2") { 2907 HasBMI2 = true; 2908 continue; 2909 } 2910 2911 if (Feature == "popcnt") { 2912 HasPOPCNT = true; 2913 continue; 2914 } 2915 2916 if (Feature == "rtm") { 2917 HasRTM = true; 2918 continue; 2919 } 2920 2921 if (Feature == "prfchw") { 2922 HasPRFCHW = true; 2923 continue; 2924 } 2925 2926 if (Feature == "rdseed") { 2927 HasRDSEED = true; 2928 continue; 2929 } 2930 2931 if (Feature == "adx") { 2932 HasADX = true; 2933 continue; 2934 } 2935 2936 if (Feature == "tbm") { 2937 HasTBM = true; 2938 continue; 2939 } 2940 2941 if (Feature == "fma") { 2942 HasFMA = true; 2943 continue; 2944 } 2945 2946 if (Feature == "f16c") { 2947 HasF16C = true; 2948 continue; 2949 } 2950 2951 if (Feature == "avx512cd") { 2952 HasAVX512CD = true; 2953 continue; 2954 } 2955 2956 if (Feature == "avx512er") { 2957 HasAVX512ER = true; 2958 continue; 2959 } 2960 2961 if (Feature == "avx512pf") { 2962 HasAVX512PF = true; 2963 continue; 2964 } 2965 2966 if (Feature == "avx512dq") { 2967 HasAVX512DQ = true; 2968 continue; 2969 } 2970 2971 if (Feature == "avx512bw") { 2972 HasAVX512BW = true; 2973 continue; 2974 } 2975 2976 if (Feature == "avx512vl") { 2977 HasAVX512VL = true; 2978 continue; 2979 } 2980 2981 if (Feature == "sha") { 2982 HasSHA = true; 2983 continue; 2984 } 2985 2986 if (Feature == "cx16") { 2987 HasCX16 = true; 2988 continue; 2989 } 2990 2991 assert(Features[i][0] == '+' && "Invalid target feature!"); 2992 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2993 .Case("avx512f", AVX512F) 2994 .Case("avx2", AVX2) 2995 .Case("avx", AVX) 2996 .Case("sse4.2", SSE42) 2997 .Case("sse4.1", SSE41) 2998 .Case("ssse3", SSSE3) 2999 .Case("sse3", SSE3) 3000 .Case("sse2", SSE2) 3001 .Case("sse", SSE1) 3002 .Default(NoSSE); 3003 SSELevel = std::max(SSELevel, Level); 3004 3005 MMX3DNowEnum ThreeDNowLevel = 3006 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3007 .Case("3dnowa", AMD3DNowAthlon) 3008 .Case("3dnow", AMD3DNow) 3009 .Case("mmx", MMX) 3010 .Default(NoMMX3DNow); 3011 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3012 3013 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3014 .Case("xop", XOP) 3015 .Case("fma4", FMA4) 3016 .Case("sse4a", SSE4A) 3017 .Default(NoXOP); 3018 XOPLevel = std::max(XOPLevel, XLevel); 3019 } 3020 3021 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3022 // Can't do this earlier because we need to be able to explicitly enable 3023 // popcnt and still disable sse4.2. 3024 if (!HasPOPCNT && SSELevel >= SSE42 && 3025 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 3026 HasPOPCNT = true; 3027 Features.push_back("+popcnt"); 3028 } 3029 3030 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3031 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 3032 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 3033 HasPRFCHW = true; 3034 Features.push_back("+prfchw"); 3035 } 3036 3037 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3038 // matches the selected sse level. 3039 if (FPMath == FP_SSE && SSELevel < SSE1) { 3040 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3041 return false; 3042 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3043 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3044 return false; 3045 } 3046 3047 // Don't tell the backend if we're turning off mmx; it will end up disabling 3048 // SSE, which we don't want. 3049 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3050 // then enable MMX. 3051 std::vector<std::string>::iterator it; 3052 it = std::find(Features.begin(), Features.end(), "-mmx"); 3053 if (it != Features.end()) 3054 Features.erase(it); 3055 else if (SSELevel > NoSSE) 3056 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3057 3058 SimdDefaultAlign = 3059 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 3060 return true; 3061 } 3062 3063 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3064 /// definitions for this particular subtarget. 3065 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3066 MacroBuilder &Builder) const { 3067 // Target identification. 3068 if (getTriple().getArch() == llvm::Triple::x86_64) { 3069 Builder.defineMacro("__amd64__"); 3070 Builder.defineMacro("__amd64"); 3071 Builder.defineMacro("__x86_64"); 3072 Builder.defineMacro("__x86_64__"); 3073 if (getTriple().getArchName() == "x86_64h") { 3074 Builder.defineMacro("__x86_64h"); 3075 Builder.defineMacro("__x86_64h__"); 3076 } 3077 } else { 3078 DefineStd(Builder, "i386", Opts); 3079 } 3080 3081 // Subtarget options. 3082 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3083 // truly should be based on -mtune options. 3084 switch (CPU) { 3085 case CK_Generic: 3086 break; 3087 case CK_i386: 3088 // The rest are coming from the i386 define above. 3089 Builder.defineMacro("__tune_i386__"); 3090 break; 3091 case CK_i486: 3092 case CK_WinChipC6: 3093 case CK_WinChip2: 3094 case CK_C3: 3095 defineCPUMacros(Builder, "i486"); 3096 break; 3097 case CK_PentiumMMX: 3098 Builder.defineMacro("__pentium_mmx__"); 3099 Builder.defineMacro("__tune_pentium_mmx__"); 3100 // Fallthrough 3101 case CK_i586: 3102 case CK_Pentium: 3103 defineCPUMacros(Builder, "i586"); 3104 defineCPUMacros(Builder, "pentium"); 3105 break; 3106 case CK_Pentium3: 3107 case CK_Pentium3M: 3108 case CK_PentiumM: 3109 Builder.defineMacro("__tune_pentium3__"); 3110 // Fallthrough 3111 case CK_Pentium2: 3112 case CK_C3_2: 3113 Builder.defineMacro("__tune_pentium2__"); 3114 // Fallthrough 3115 case CK_PentiumPro: 3116 Builder.defineMacro("__tune_i686__"); 3117 Builder.defineMacro("__tune_pentiumpro__"); 3118 // Fallthrough 3119 case CK_i686: 3120 Builder.defineMacro("__i686"); 3121 Builder.defineMacro("__i686__"); 3122 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3123 Builder.defineMacro("__pentiumpro"); 3124 Builder.defineMacro("__pentiumpro__"); 3125 break; 3126 case CK_Pentium4: 3127 case CK_Pentium4M: 3128 defineCPUMacros(Builder, "pentium4"); 3129 break; 3130 case CK_Yonah: 3131 case CK_Prescott: 3132 case CK_Nocona: 3133 defineCPUMacros(Builder, "nocona"); 3134 break; 3135 case CK_Core2: 3136 case CK_Penryn: 3137 defineCPUMacros(Builder, "core2"); 3138 break; 3139 case CK_Bonnell: 3140 defineCPUMacros(Builder, "atom"); 3141 break; 3142 case CK_Silvermont: 3143 defineCPUMacros(Builder, "slm"); 3144 break; 3145 case CK_Nehalem: 3146 case CK_Westmere: 3147 case CK_SandyBridge: 3148 case CK_IvyBridge: 3149 case CK_Haswell: 3150 case CK_Broadwell: 3151 // FIXME: Historically, we defined this legacy name, it would be nice to 3152 // remove it at some point. We've never exposed fine-grained names for 3153 // recent primary x86 CPUs, and we should keep it that way. 3154 defineCPUMacros(Builder, "corei7"); 3155 break; 3156 case CK_Skylake: 3157 // FIXME: Historically, we defined this legacy name, it would be nice to 3158 // remove it at some point. This is the only fine-grained CPU macro in the 3159 // main intel CPU line, and it would be better to not have these and force 3160 // people to use ISA macros. 3161 defineCPUMacros(Builder, "skx"); 3162 break; 3163 case CK_KNL: 3164 defineCPUMacros(Builder, "knl"); 3165 break; 3166 case CK_K6_2: 3167 Builder.defineMacro("__k6_2__"); 3168 Builder.defineMacro("__tune_k6_2__"); 3169 // Fallthrough 3170 case CK_K6_3: 3171 if (CPU != CK_K6_2) { // In case of fallthrough 3172 // FIXME: GCC may be enabling these in cases where some other k6 3173 // architecture is specified but -m3dnow is explicitly provided. The 3174 // exact semantics need to be determined and emulated here. 3175 Builder.defineMacro("__k6_3__"); 3176 Builder.defineMacro("__tune_k6_3__"); 3177 } 3178 // Fallthrough 3179 case CK_K6: 3180 defineCPUMacros(Builder, "k6"); 3181 break; 3182 case CK_Athlon: 3183 case CK_AthlonThunderbird: 3184 case CK_Athlon4: 3185 case CK_AthlonXP: 3186 case CK_AthlonMP: 3187 defineCPUMacros(Builder, "athlon"); 3188 if (SSELevel != NoSSE) { 3189 Builder.defineMacro("__athlon_sse__"); 3190 Builder.defineMacro("__tune_athlon_sse__"); 3191 } 3192 break; 3193 case CK_K8: 3194 case CK_K8SSE3: 3195 case CK_x86_64: 3196 case CK_Opteron: 3197 case CK_OpteronSSE3: 3198 case CK_Athlon64: 3199 case CK_Athlon64SSE3: 3200 case CK_AthlonFX: 3201 defineCPUMacros(Builder, "k8"); 3202 break; 3203 case CK_AMDFAM10: 3204 defineCPUMacros(Builder, "amdfam10"); 3205 break; 3206 case CK_BTVER1: 3207 defineCPUMacros(Builder, "btver1"); 3208 break; 3209 case CK_BTVER2: 3210 defineCPUMacros(Builder, "btver2"); 3211 break; 3212 case CK_BDVER1: 3213 defineCPUMacros(Builder, "bdver1"); 3214 break; 3215 case CK_BDVER2: 3216 defineCPUMacros(Builder, "bdver2"); 3217 break; 3218 case CK_BDVER3: 3219 defineCPUMacros(Builder, "bdver3"); 3220 break; 3221 case CK_BDVER4: 3222 defineCPUMacros(Builder, "bdver4"); 3223 break; 3224 case CK_Geode: 3225 defineCPUMacros(Builder, "geode"); 3226 break; 3227 } 3228 3229 // Target properties. 3230 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3231 3232 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3233 // functions in glibc header files that use FP Stack inline asm which the 3234 // backend can't deal with (PR879). 3235 Builder.defineMacro("__NO_MATH_INLINES"); 3236 3237 if (HasAES) 3238 Builder.defineMacro("__AES__"); 3239 3240 if (HasPCLMUL) 3241 Builder.defineMacro("__PCLMUL__"); 3242 3243 if (HasLZCNT) 3244 Builder.defineMacro("__LZCNT__"); 3245 3246 if (HasRDRND) 3247 Builder.defineMacro("__RDRND__"); 3248 3249 if (HasFSGSBASE) 3250 Builder.defineMacro("__FSGSBASE__"); 3251 3252 if (HasBMI) 3253 Builder.defineMacro("__BMI__"); 3254 3255 if (HasBMI2) 3256 Builder.defineMacro("__BMI2__"); 3257 3258 if (HasPOPCNT) 3259 Builder.defineMacro("__POPCNT__"); 3260 3261 if (HasRTM) 3262 Builder.defineMacro("__RTM__"); 3263 3264 if (HasPRFCHW) 3265 Builder.defineMacro("__PRFCHW__"); 3266 3267 if (HasRDSEED) 3268 Builder.defineMacro("__RDSEED__"); 3269 3270 if (HasADX) 3271 Builder.defineMacro("__ADX__"); 3272 3273 if (HasTBM) 3274 Builder.defineMacro("__TBM__"); 3275 3276 switch (XOPLevel) { 3277 case XOP: 3278 Builder.defineMacro("__XOP__"); 3279 case FMA4: 3280 Builder.defineMacro("__FMA4__"); 3281 case SSE4A: 3282 Builder.defineMacro("__SSE4A__"); 3283 case NoXOP: 3284 break; 3285 } 3286 3287 if (HasFMA) 3288 Builder.defineMacro("__FMA__"); 3289 3290 if (HasF16C) 3291 Builder.defineMacro("__F16C__"); 3292 3293 if (HasAVX512CD) 3294 Builder.defineMacro("__AVX512CD__"); 3295 if (HasAVX512ER) 3296 Builder.defineMacro("__AVX512ER__"); 3297 if (HasAVX512PF) 3298 Builder.defineMacro("__AVX512PF__"); 3299 if (HasAVX512DQ) 3300 Builder.defineMacro("__AVX512DQ__"); 3301 if (HasAVX512BW) 3302 Builder.defineMacro("__AVX512BW__"); 3303 if (HasAVX512VL) 3304 Builder.defineMacro("__AVX512VL__"); 3305 3306 if (HasSHA) 3307 Builder.defineMacro("__SHA__"); 3308 3309 if (HasCX16) 3310 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3311 3312 // Each case falls through to the previous one here. 3313 switch (SSELevel) { 3314 case AVX512F: 3315 Builder.defineMacro("__AVX512F__"); 3316 case AVX2: 3317 Builder.defineMacro("__AVX2__"); 3318 case AVX: 3319 Builder.defineMacro("__AVX__"); 3320 case SSE42: 3321 Builder.defineMacro("__SSE4_2__"); 3322 case SSE41: 3323 Builder.defineMacro("__SSE4_1__"); 3324 case SSSE3: 3325 Builder.defineMacro("__SSSE3__"); 3326 case SSE3: 3327 Builder.defineMacro("__SSE3__"); 3328 case SSE2: 3329 Builder.defineMacro("__SSE2__"); 3330 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3331 case SSE1: 3332 Builder.defineMacro("__SSE__"); 3333 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3334 case NoSSE: 3335 break; 3336 } 3337 3338 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3339 switch (SSELevel) { 3340 case AVX512F: 3341 case AVX2: 3342 case AVX: 3343 case SSE42: 3344 case SSE41: 3345 case SSSE3: 3346 case SSE3: 3347 case SSE2: 3348 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3349 break; 3350 case SSE1: 3351 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3352 break; 3353 default: 3354 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3355 } 3356 } 3357 3358 // Each case falls through to the previous one here. 3359 switch (MMX3DNowLevel) { 3360 case AMD3DNowAthlon: 3361 Builder.defineMacro("__3dNOW_A__"); 3362 case AMD3DNow: 3363 Builder.defineMacro("__3dNOW__"); 3364 case MMX: 3365 Builder.defineMacro("__MMX__"); 3366 case NoMMX3DNow: 3367 break; 3368 } 3369 3370 if (CPU >= CK_i486) { 3371 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3372 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3373 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3374 } 3375 if (CPU >= CK_i586) 3376 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3377 } 3378 3379 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3380 return llvm::StringSwitch<bool>(Feature) 3381 .Case("aes", HasAES) 3382 .Case("avx", SSELevel >= AVX) 3383 .Case("avx2", SSELevel >= AVX2) 3384 .Case("avx512f", SSELevel >= AVX512F) 3385 .Case("avx512cd", HasAVX512CD) 3386 .Case("avx512er", HasAVX512ER) 3387 .Case("avx512pf", HasAVX512PF) 3388 .Case("avx512dq", HasAVX512DQ) 3389 .Case("avx512bw", HasAVX512BW) 3390 .Case("avx512vl", HasAVX512VL) 3391 .Case("bmi", HasBMI) 3392 .Case("bmi2", HasBMI2) 3393 .Case("cx16", HasCX16) 3394 .Case("f16c", HasF16C) 3395 .Case("fma", HasFMA) 3396 .Case("fma4", XOPLevel >= FMA4) 3397 .Case("fsgsbase", HasFSGSBASE) 3398 .Case("lzcnt", HasLZCNT) 3399 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3400 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3401 .Case("mmx", MMX3DNowLevel >= MMX) 3402 .Case("pclmul", HasPCLMUL) 3403 .Case("popcnt", HasPOPCNT) 3404 .Case("prfchw", HasPRFCHW) 3405 .Case("rdrnd", HasRDRND) 3406 .Case("rdseed", HasRDSEED) 3407 .Case("rtm", HasRTM) 3408 .Case("sha", HasSHA) 3409 .Case("sse", SSELevel >= SSE1) 3410 .Case("sse2", SSELevel >= SSE2) 3411 .Case("sse3", SSELevel >= SSE3) 3412 .Case("ssse3", SSELevel >= SSSE3) 3413 .Case("sse4.1", SSELevel >= SSE41) 3414 .Case("sse4.2", SSELevel >= SSE42) 3415 .Case("sse4a", XOPLevel >= SSE4A) 3416 .Case("tbm", HasTBM) 3417 .Case("x86", true) 3418 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3419 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3420 .Case("xop", XOPLevel >= XOP) 3421 .Default(false); 3422 } 3423 3424 // We can't use a generic validation scheme for the features accepted here 3425 // versus subtarget features accepted in the target attribute because the 3426 // bitfield structure that's initialized in the runtime only supports the 3427 // below currently rather than the full range of subtarget features. (See 3428 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3429 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3430 return llvm::StringSwitch<bool>(FeatureStr) 3431 .Case("cmov", true) 3432 .Case("mmx", true) 3433 .Case("popcnt", true) 3434 .Case("sse", true) 3435 .Case("sse2", true) 3436 .Case("sse3", true) 3437 .Case("sse4.1", true) 3438 .Case("sse4.2", true) 3439 .Case("avx", true) 3440 .Case("avx2", true) 3441 .Case("sse4a", true) 3442 .Case("fma4", true) 3443 .Case("xop", true) 3444 .Case("fma", true) 3445 .Case("avx512f", true) 3446 .Case("bmi", true) 3447 .Case("bmi2", true) 3448 .Default(false); 3449 } 3450 3451 bool 3452 X86TargetInfo::validateAsmConstraint(const char *&Name, 3453 TargetInfo::ConstraintInfo &Info) const { 3454 switch (*Name) { 3455 default: return false; 3456 // Constant constraints. 3457 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3458 // instructions. 3459 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3460 // x86_64 instructions. 3461 case 's': 3462 Info.setRequiresImmediate(); 3463 return true; 3464 case 'I': 3465 Info.setRequiresImmediate(0, 31); 3466 return true; 3467 case 'J': 3468 Info.setRequiresImmediate(0, 63); 3469 return true; 3470 case 'K': 3471 Info.setRequiresImmediate(-128, 127); 3472 return true; 3473 case 'L': 3474 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3475 return true; 3476 case 'M': 3477 Info.setRequiresImmediate(0, 3); 3478 return true; 3479 case 'N': 3480 Info.setRequiresImmediate(0, 255); 3481 return true; 3482 case 'O': 3483 Info.setRequiresImmediate(0, 127); 3484 return true; 3485 // Register constraints. 3486 case 'Y': // 'Y' is the first character for several 2-character constraints. 3487 // Shift the pointer to the second character of the constraint. 3488 Name++; 3489 switch (*Name) { 3490 default: 3491 return false; 3492 case '0': // First SSE register. 3493 case 't': // Any SSE register, when SSE2 is enabled. 3494 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3495 case 'm': // Any MMX register, when inter-unit moves enabled. 3496 Info.setAllowsRegister(); 3497 return true; 3498 } 3499 case 'f': // Any x87 floating point stack register. 3500 // Constraint 'f' cannot be used for output operands. 3501 if (Info.ConstraintStr[0] == '=') 3502 return false; 3503 Info.setAllowsRegister(); 3504 return true; 3505 case 'a': // eax. 3506 case 'b': // ebx. 3507 case 'c': // ecx. 3508 case 'd': // edx. 3509 case 'S': // esi. 3510 case 'D': // edi. 3511 case 'A': // edx:eax. 3512 case 't': // Top of floating point stack. 3513 case 'u': // Second from top of floating point stack. 3514 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3515 case 'y': // Any MMX register. 3516 case 'x': // Any SSE register. 3517 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3518 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3519 case 'l': // "Index" registers: any general register that can be used as an 3520 // index in a base+index memory access. 3521 Info.setAllowsRegister(); 3522 return true; 3523 // Floating point constant constraints. 3524 case 'C': // SSE floating point constant. 3525 case 'G': // x87 floating point constant. 3526 return true; 3527 } 3528 } 3529 3530 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3531 unsigned Size) const { 3532 // Strip off constraint modifiers. 3533 while (Constraint[0] == '=' || 3534 Constraint[0] == '+' || 3535 Constraint[0] == '&') 3536 Constraint = Constraint.substr(1); 3537 3538 return validateOperandSize(Constraint, Size); 3539 } 3540 3541 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3542 unsigned Size) const { 3543 return validateOperandSize(Constraint, Size); 3544 } 3545 3546 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3547 unsigned Size) const { 3548 switch (Constraint[0]) { 3549 default: break; 3550 case 'y': 3551 return Size <= 64; 3552 case 'f': 3553 case 't': 3554 case 'u': 3555 return Size <= 128; 3556 case 'x': 3557 if (SSELevel >= AVX512F) 3558 // 512-bit zmm registers can be used if target supports AVX512F. 3559 return Size <= 512U; 3560 else if (SSELevel >= AVX) 3561 // 256-bit ymm registers can be used if target supports AVX. 3562 return Size <= 256U; 3563 return Size <= 128U; 3564 case 'Y': 3565 // 'Y' is the first character for several 2-character constraints. 3566 switch (Constraint[1]) { 3567 default: break; 3568 case 'm': 3569 // 'Ym' is synonymous with 'y'. 3570 return Size <= 64; 3571 case 'i': 3572 case 't': 3573 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3574 if (SSELevel >= AVX512F) 3575 return Size <= 512U; 3576 else if (SSELevel >= AVX) 3577 return Size <= 256U; 3578 return SSELevel >= SSE2 && Size <= 128U; 3579 } 3580 3581 } 3582 3583 return true; 3584 } 3585 3586 std::string 3587 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3588 switch (*Constraint) { 3589 case 'a': return std::string("{ax}"); 3590 case 'b': return std::string("{bx}"); 3591 case 'c': return std::string("{cx}"); 3592 case 'd': return std::string("{dx}"); 3593 case 'S': return std::string("{si}"); 3594 case 'D': return std::string("{di}"); 3595 case 'p': // address 3596 return std::string("im"); 3597 case 't': // top of floating point stack. 3598 return std::string("{st}"); 3599 case 'u': // second from top of floating point stack. 3600 return std::string("{st(1)}"); // second from top of floating point stack. 3601 default: 3602 return std::string(1, *Constraint); 3603 } 3604 } 3605 3606 // X86-32 generic target 3607 class X86_32TargetInfo : public X86TargetInfo { 3608 public: 3609 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3610 DoubleAlign = LongLongAlign = 32; 3611 LongDoubleWidth = 96; 3612 LongDoubleAlign = 32; 3613 SuitableAlign = 128; 3614 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3615 SizeType = UnsignedInt; 3616 PtrDiffType = SignedInt; 3617 IntPtrType = SignedInt; 3618 RegParmMax = 3; 3619 3620 // Use fpret for all types. 3621 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3622 (1 << TargetInfo::Double) | 3623 (1 << TargetInfo::LongDouble)); 3624 3625 // x86-32 has atomics up to 8 bytes 3626 // FIXME: Check that we actually have cmpxchg8b before setting 3627 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3628 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3629 } 3630 BuiltinVaListKind getBuiltinVaListKind() const override { 3631 return TargetInfo::CharPtrBuiltinVaList; 3632 } 3633 3634 int getEHDataRegisterNumber(unsigned RegNo) const override { 3635 if (RegNo == 0) return 0; 3636 if (RegNo == 1) return 2; 3637 return -1; 3638 } 3639 bool validateOperandSize(StringRef Constraint, 3640 unsigned Size) const override { 3641 switch (Constraint[0]) { 3642 default: break; 3643 case 'R': 3644 case 'q': 3645 case 'Q': 3646 case 'a': 3647 case 'b': 3648 case 'c': 3649 case 'd': 3650 case 'S': 3651 case 'D': 3652 return Size <= 32; 3653 case 'A': 3654 return Size <= 64; 3655 } 3656 3657 return X86TargetInfo::validateOperandSize(Constraint, Size); 3658 } 3659 }; 3660 3661 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3662 public: 3663 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3664 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3665 3666 unsigned getFloatEvalMethod() const override { 3667 unsigned Major, Minor, Micro; 3668 getTriple().getOSVersion(Major, Minor, Micro); 3669 // New NetBSD uses the default rounding mode. 3670 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3671 return X86_32TargetInfo::getFloatEvalMethod(); 3672 // NetBSD before 6.99.26 defaults to "double" rounding. 3673 return 1; 3674 } 3675 }; 3676 3677 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3678 public: 3679 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3680 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3681 SizeType = UnsignedLong; 3682 IntPtrType = SignedLong; 3683 PtrDiffType = SignedLong; 3684 } 3685 }; 3686 3687 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3688 public: 3689 BitrigI386TargetInfo(const llvm::Triple &Triple) 3690 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3691 SizeType = UnsignedLong; 3692 IntPtrType = SignedLong; 3693 PtrDiffType = SignedLong; 3694 } 3695 }; 3696 3697 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3698 public: 3699 DarwinI386TargetInfo(const llvm::Triple &Triple) 3700 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3701 LongDoubleWidth = 128; 3702 LongDoubleAlign = 128; 3703 SuitableAlign = 128; 3704 MaxVectorAlign = 256; 3705 SizeType = UnsignedLong; 3706 IntPtrType = SignedLong; 3707 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3708 HasAlignMac68kSupport = true; 3709 } 3710 3711 }; 3712 3713 // x86-32 Windows target 3714 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3715 public: 3716 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3717 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3718 WCharType = UnsignedShort; 3719 DoubleAlign = LongLongAlign = 64; 3720 bool IsWinCOFF = 3721 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3722 DataLayoutString = IsWinCOFF 3723 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3724 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3725 } 3726 void getTargetDefines(const LangOptions &Opts, 3727 MacroBuilder &Builder) const override { 3728 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3729 } 3730 }; 3731 3732 // x86-32 Windows Visual Studio target 3733 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3734 public: 3735 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3736 : WindowsX86_32TargetInfo(Triple) { 3737 LongDoubleWidth = LongDoubleAlign = 64; 3738 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3739 } 3740 void getTargetDefines(const LangOptions &Opts, 3741 MacroBuilder &Builder) const override { 3742 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3743 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3744 // The value of the following reflects processor type. 3745 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3746 // We lost the original triple, so we use the default. 3747 Builder.defineMacro("_M_IX86", "600"); 3748 } 3749 }; 3750 } // end anonymous namespace 3751 3752 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3753 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3754 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3755 // macro anyway for pre-processor compatibility. 3756 if (Opts.MicrosoftExt) 3757 Builder.defineMacro("__declspec", "__declspec"); 3758 else 3759 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3760 3761 if (!Opts.MicrosoftExt) { 3762 // Provide macros for all the calling convention keywords. Provide both 3763 // single and double underscore prefixed variants. These are available on 3764 // x64 as well as x86, even though they have no effect. 3765 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3766 for (const char *CC : CCs) { 3767 std::string GCCSpelling = "__attribute__((__"; 3768 GCCSpelling += CC; 3769 GCCSpelling += "__))"; 3770 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3771 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3772 } 3773 } 3774 } 3775 3776 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3777 Builder.defineMacro("__MSVCRT__"); 3778 Builder.defineMacro("__MINGW32__"); 3779 addCygMingDefines(Opts, Builder); 3780 } 3781 3782 namespace { 3783 // x86-32 MinGW target 3784 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3785 public: 3786 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3787 : WindowsX86_32TargetInfo(Triple) { 3788 LongDoubleWidth = 96; 3789 LongDoubleAlign = 128; 3790 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 3791 } 3792 void getTargetDefines(const LangOptions &Opts, 3793 MacroBuilder &Builder) const override { 3794 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3795 DefineStd(Builder, "WIN32", Opts); 3796 DefineStd(Builder, "WINNT", Opts); 3797 Builder.defineMacro("_X86_"); 3798 addMinGWDefines(Opts, Builder); 3799 } 3800 }; 3801 3802 // x86-32 Cygwin target 3803 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3804 public: 3805 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3806 : X86_32TargetInfo(Triple) { 3807 TLSSupported = false; 3808 WCharType = UnsignedShort; 3809 DoubleAlign = LongLongAlign = 64; 3810 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3811 } 3812 void getTargetDefines(const LangOptions &Opts, 3813 MacroBuilder &Builder) const override { 3814 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3815 Builder.defineMacro("_X86_"); 3816 Builder.defineMacro("__CYGWIN__"); 3817 Builder.defineMacro("__CYGWIN32__"); 3818 addCygMingDefines(Opts, Builder); 3819 DefineStd(Builder, "unix", Opts); 3820 if (Opts.CPlusPlus) 3821 Builder.defineMacro("_GNU_SOURCE"); 3822 } 3823 }; 3824 3825 // x86-32 Haiku target 3826 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3827 public: 3828 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3829 SizeType = UnsignedLong; 3830 IntPtrType = SignedLong; 3831 PtrDiffType = SignedLong; 3832 ProcessIDType = SignedLong; 3833 this->UserLabelPrefix = ""; 3834 this->TLSSupported = false; 3835 } 3836 void getTargetDefines(const LangOptions &Opts, 3837 MacroBuilder &Builder) const override { 3838 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3839 Builder.defineMacro("__INTEL__"); 3840 Builder.defineMacro("__HAIKU__"); 3841 } 3842 }; 3843 3844 // RTEMS Target 3845 template<typename Target> 3846 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3847 protected: 3848 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3849 MacroBuilder &Builder) const override { 3850 // RTEMS defines; list based off of gcc output 3851 3852 Builder.defineMacro("__rtems__"); 3853 Builder.defineMacro("__ELF__"); 3854 } 3855 3856 public: 3857 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3858 this->UserLabelPrefix = ""; 3859 3860 switch (Triple.getArch()) { 3861 default: 3862 case llvm::Triple::x86: 3863 // this->MCountName = ".mcount"; 3864 break; 3865 case llvm::Triple::mips: 3866 case llvm::Triple::mipsel: 3867 case llvm::Triple::ppc: 3868 case llvm::Triple::ppc64: 3869 case llvm::Triple::ppc64le: 3870 // this->MCountName = "_mcount"; 3871 break; 3872 case llvm::Triple::arm: 3873 // this->MCountName = "__mcount"; 3874 break; 3875 } 3876 } 3877 }; 3878 3879 // x86-32 RTEMS target 3880 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3881 public: 3882 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3883 SizeType = UnsignedLong; 3884 IntPtrType = SignedLong; 3885 PtrDiffType = SignedLong; 3886 this->UserLabelPrefix = ""; 3887 } 3888 void getTargetDefines(const LangOptions &Opts, 3889 MacroBuilder &Builder) const override { 3890 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3891 Builder.defineMacro("__INTEL__"); 3892 Builder.defineMacro("__rtems__"); 3893 } 3894 }; 3895 3896 // x86-64 generic target 3897 class X86_64TargetInfo : public X86TargetInfo { 3898 public: 3899 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3900 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3901 bool IsWinCOFF = 3902 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3903 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3904 LongDoubleWidth = 128; 3905 LongDoubleAlign = 128; 3906 LargeArrayMinWidth = 128; 3907 LargeArrayAlign = 128; 3908 SuitableAlign = 128; 3909 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3910 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3911 IntPtrType = IsX32 ? SignedInt : SignedLong; 3912 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3913 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3914 RegParmMax = 6; 3915 3916 // Pointers are 32-bit in x32. 3917 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3918 : IsWinCOFF 3919 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3920 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3921 3922 // Use fpret only for long double. 3923 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3924 3925 // Use fp2ret for _Complex long double. 3926 ComplexLongDoubleUsesFP2Ret = true; 3927 3928 // x86-64 has atomics up to 16 bytes. 3929 MaxAtomicPromoteWidth = 128; 3930 MaxAtomicInlineWidth = 128; 3931 } 3932 BuiltinVaListKind getBuiltinVaListKind() const override { 3933 return TargetInfo::X86_64ABIBuiltinVaList; 3934 } 3935 3936 int getEHDataRegisterNumber(unsigned RegNo) const override { 3937 if (RegNo == 0) return 0; 3938 if (RegNo == 1) return 1; 3939 return -1; 3940 } 3941 3942 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3943 return (CC == CC_C || 3944 CC == CC_X86VectorCall || 3945 CC == CC_IntelOclBicc || 3946 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3947 } 3948 3949 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3950 return CC_C; 3951 } 3952 3953 // for x32 we need it here explicitly 3954 bool hasInt128Type() const override { return true; } 3955 }; 3956 3957 // x86-64 Windows target 3958 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3959 public: 3960 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3961 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3962 WCharType = UnsignedShort; 3963 LongWidth = LongAlign = 32; 3964 DoubleAlign = LongLongAlign = 64; 3965 IntMaxType = SignedLongLong; 3966 Int64Type = SignedLongLong; 3967 SizeType = UnsignedLongLong; 3968 PtrDiffType = SignedLongLong; 3969 IntPtrType = SignedLongLong; 3970 this->UserLabelPrefix = ""; 3971 } 3972 3973 void getTargetDefines(const LangOptions &Opts, 3974 MacroBuilder &Builder) const override { 3975 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3976 Builder.defineMacro("_WIN64"); 3977 } 3978 3979 BuiltinVaListKind getBuiltinVaListKind() const override { 3980 return TargetInfo::CharPtrBuiltinVaList; 3981 } 3982 3983 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3984 switch (CC) { 3985 case CC_X86StdCall: 3986 case CC_X86ThisCall: 3987 case CC_X86FastCall: 3988 return CCCR_Ignore; 3989 case CC_C: 3990 case CC_X86VectorCall: 3991 case CC_IntelOclBicc: 3992 case CC_X86_64SysV: 3993 return CCCR_OK; 3994 default: 3995 return CCCR_Warning; 3996 } 3997 } 3998 }; 3999 4000 // x86-64 Windows Visual Studio target 4001 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4002 public: 4003 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4004 : WindowsX86_64TargetInfo(Triple) { 4005 LongDoubleWidth = LongDoubleAlign = 64; 4006 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4007 } 4008 void getTargetDefines(const LangOptions &Opts, 4009 MacroBuilder &Builder) const override { 4010 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4011 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4012 Builder.defineMacro("_M_X64", "100"); 4013 Builder.defineMacro("_M_AMD64", "100"); 4014 } 4015 }; 4016 4017 // x86-64 MinGW target 4018 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4019 public: 4020 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4021 : WindowsX86_64TargetInfo(Triple) { 4022 LongDoubleWidth = LongDoubleAlign = 128; 4023 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4024 } 4025 void getTargetDefines(const LangOptions &Opts, 4026 MacroBuilder &Builder) const override { 4027 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4028 DefineStd(Builder, "WIN64", Opts); 4029 Builder.defineMacro("__MINGW64__"); 4030 addMinGWDefines(Opts, Builder); 4031 4032 // GCC defines this macro when it is using __gxx_personality_seh0. 4033 if (!Opts.SjLjExceptions) 4034 Builder.defineMacro("__SEH__"); 4035 } 4036 }; 4037 4038 // x86-64 Cygwin target 4039 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4040 public: 4041 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4042 : X86_64TargetInfo(Triple) { 4043 TLSSupported = false; 4044 WCharType = UnsignedShort; 4045 } 4046 void getTargetDefines(const LangOptions &Opts, 4047 MacroBuilder &Builder) const override { 4048 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4049 Builder.defineMacro("__x86_64__"); 4050 Builder.defineMacro("__CYGWIN__"); 4051 Builder.defineMacro("__CYGWIN64__"); 4052 addCygMingDefines(Opts, Builder); 4053 DefineStd(Builder, "unix", Opts); 4054 if (Opts.CPlusPlus) 4055 Builder.defineMacro("_GNU_SOURCE"); 4056 4057 // GCC defines this macro when it is using __gxx_personality_seh0. 4058 if (!Opts.SjLjExceptions) 4059 Builder.defineMacro("__SEH__"); 4060 } 4061 }; 4062 4063 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4064 public: 4065 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4066 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4067 Int64Type = SignedLongLong; 4068 MaxVectorAlign = 256; 4069 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4070 llvm::Triple T = llvm::Triple(Triple); 4071 if (T.isiOS()) 4072 UseSignedCharForObjCBool = false; 4073 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4074 } 4075 }; 4076 4077 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4078 public: 4079 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4080 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4081 IntMaxType = SignedLongLong; 4082 Int64Type = SignedLongLong; 4083 } 4084 }; 4085 4086 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4087 public: 4088 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4089 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4090 IntMaxType = SignedLongLong; 4091 Int64Type = SignedLongLong; 4092 } 4093 }; 4094 4095 class ARMTargetInfo : public TargetInfo { 4096 // Possible FPU choices. 4097 enum FPUMode { 4098 VFP2FPU = (1 << 0), 4099 VFP3FPU = (1 << 1), 4100 VFP4FPU = (1 << 2), 4101 NeonFPU = (1 << 3), 4102 FPARMV8 = (1 << 4) 4103 }; 4104 4105 // Possible HWDiv features. 4106 enum HWDivMode { 4107 HWDivThumb = (1 << 0), 4108 HWDivARM = (1 << 1) 4109 }; 4110 4111 static bool FPUModeIsVFP(FPUMode Mode) { 4112 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4113 } 4114 4115 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4116 static const char * const GCCRegNames[]; 4117 4118 std::string ABI, CPU; 4119 4120 StringRef DefaultCPU; 4121 StringRef CPUProfile; 4122 StringRef CPUAttr; 4123 4124 enum { 4125 FP_Default, 4126 FP_VFP, 4127 FP_Neon 4128 } FPMath; 4129 4130 unsigned ArchISA; 4131 unsigned ArchKind; 4132 unsigned ArchProfile; 4133 unsigned ArchVersion; 4134 4135 unsigned FPU : 5; 4136 4137 unsigned IsAAPCS : 1; 4138 unsigned HWDiv : 2; 4139 4140 // Initialized via features. 4141 unsigned SoftFloat : 1; 4142 unsigned SoftFloatABI : 1; 4143 4144 unsigned CRC : 1; 4145 unsigned Crypto : 1; 4146 4147 // ACLE 6.5.1 Hardware floating point 4148 enum { 4149 HW_FP_HP = (1 << 1), /// half (16-bit) 4150 HW_FP_SP = (1 << 2), /// single (32-bit) 4151 HW_FP_DP = (1 << 3), /// double (64-bit) 4152 }; 4153 uint32_t HW_FP; 4154 4155 static const Builtin::Info BuiltinInfo[]; 4156 4157 void setABIAAPCS() { 4158 IsAAPCS = true; 4159 4160 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4161 const llvm::Triple &T = getTriple(); 4162 4163 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4164 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4165 T.getOS() == llvm::Triple::Bitrig) 4166 SizeType = UnsignedLong; 4167 else 4168 SizeType = UnsignedInt; 4169 4170 switch (T.getOS()) { 4171 case llvm::Triple::NetBSD: 4172 WCharType = SignedInt; 4173 break; 4174 case llvm::Triple::Win32: 4175 WCharType = UnsignedShort; 4176 break; 4177 case llvm::Triple::Linux: 4178 default: 4179 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4180 WCharType = UnsignedInt; 4181 break; 4182 } 4183 4184 UseBitFieldTypeAlignment = true; 4185 4186 ZeroLengthBitfieldBoundary = 0; 4187 4188 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4189 // so set preferred for small types to 32. 4190 if (T.isOSBinFormatMachO()) { 4191 DataLayoutString = 4192 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4193 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4194 } else if (T.isOSWindows()) { 4195 assert(!BigEndian && "Windows on ARM does not support big endian"); 4196 DataLayoutString = "e" 4197 "-m:w" 4198 "-p:32:32" 4199 "-i64:64" 4200 "-v128:64:128" 4201 "-a:0:32" 4202 "-n32" 4203 "-S64"; 4204 } else if (T.isOSNaCl()) { 4205 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4206 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4207 } else { 4208 DataLayoutString = 4209 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4210 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4211 } 4212 4213 // FIXME: Enumerated types are variable width in straight AAPCS. 4214 } 4215 4216 void setABIAPCS() { 4217 const llvm::Triple &T = getTriple(); 4218 4219 IsAAPCS = false; 4220 4221 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4222 4223 // size_t is unsigned int on FreeBSD. 4224 if (T.getOS() == llvm::Triple::FreeBSD) 4225 SizeType = UnsignedInt; 4226 else 4227 SizeType = UnsignedLong; 4228 4229 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4230 WCharType = SignedInt; 4231 4232 // Do not respect the alignment of bit-field types when laying out 4233 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4234 UseBitFieldTypeAlignment = false; 4235 4236 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4237 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4238 /// gcc. 4239 ZeroLengthBitfieldBoundary = 32; 4240 4241 if (T.isOSBinFormatMachO()) 4242 DataLayoutString = 4243 BigEndian 4244 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4245 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4246 else 4247 DataLayoutString = 4248 BigEndian 4249 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4250 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4251 4252 // FIXME: Override "preferred align" for double and long long. 4253 } 4254 4255 void setArchInfo() { 4256 StringRef ArchName = getTriple().getArchName(); 4257 4258 ArchISA = llvm::ARMTargetParser::parseArchISA(ArchName); 4259 DefaultCPU = getDefaultCPU(ArchName); 4260 4261 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName); 4262 if (ArchKind == llvm::ARM::AK_INVALID) 4263 // set arch of the CPU, either provided explicitly or hardcoded default 4264 ArchKind = llvm::ARMTargetParser::parseCPUArch(CPU); 4265 setArchInfo(ArchKind); 4266 } 4267 4268 void setArchInfo(unsigned Kind) { 4269 StringRef SubArch; 4270 4271 // cache TargetParser info 4272 ArchKind = Kind; 4273 SubArch = llvm::ARMTargetParser::getSubArch(ArchKind); 4274 ArchProfile = llvm::ARMTargetParser::parseArchProfile(SubArch); 4275 ArchVersion = llvm::ARMTargetParser::parseArchVersion(SubArch); 4276 4277 // cache CPU related strings 4278 CPUAttr = getCPUAttr(); 4279 CPUProfile = getCPUProfile(); 4280 } 4281 4282 void setAtomic() { 4283 // when triple does not specify a sub arch, 4284 // then we are not using inline atomics 4285 bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 4286 false : 4287 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4288 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4289 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4290 if (ArchProfile == llvm::ARM::PK_M) { 4291 MaxAtomicPromoteWidth = 32; 4292 if (ShouldUseInlineAtomic) 4293 MaxAtomicInlineWidth = 32; 4294 } 4295 else { 4296 MaxAtomicPromoteWidth = 64; 4297 if (ShouldUseInlineAtomic) 4298 MaxAtomicInlineWidth = 64; 4299 } 4300 } 4301 4302 bool isThumb() const { 4303 return (ArchISA == llvm::ARM::IK_THUMB); 4304 } 4305 4306 bool supportsThumb() const { 4307 return CPUAttr.count('T') || ArchVersion >= 6; 4308 } 4309 4310 bool supportsThumb2() const { 4311 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4312 } 4313 4314 StringRef getDefaultCPU(StringRef ArchName) const { 4315 const char *DefaultCPU = llvm::ARMTargetParser::getDefaultCPU(ArchName); 4316 return DefaultCPU ? DefaultCPU : ""; 4317 } 4318 4319 StringRef getCPUAttr() const { 4320 const char *CPUAttr; 4321 // For most sub-arches, the build attribute CPU name is enough. 4322 // For Cortex variants, it's slightly different. 4323 switch(ArchKind) { 4324 default: 4325 CPUAttr = llvm::ARMTargetParser::getCPUAttr(ArchKind); 4326 return CPUAttr ? CPUAttr : ""; 4327 case llvm::ARM::AK_ARMV6M: 4328 case llvm::ARM::AK_ARMV6SM: 4329 case llvm::ARM::AK_ARMV6HL: 4330 return "6M"; 4331 case llvm::ARM::AK_ARMV7S: 4332 return "7S"; 4333 case llvm::ARM::AK_ARMV7: 4334 case llvm::ARM::AK_ARMV7A: 4335 case llvm::ARM::AK_ARMV7L: 4336 case llvm::ARM::AK_ARMV7HL: 4337 return "7A"; 4338 case llvm::ARM::AK_ARMV7R: 4339 return "7R"; 4340 case llvm::ARM::AK_ARMV7M: 4341 return "7M"; 4342 case llvm::ARM::AK_ARMV7EM: 4343 return "7EM"; 4344 case llvm::ARM::AK_ARMV8A: 4345 return "8A"; 4346 case llvm::ARM::AK_ARMV8_1A: 4347 return "8_1A"; 4348 } 4349 } 4350 4351 StringRef getCPUProfile() const { 4352 switch(ArchProfile) { 4353 case llvm::ARM::PK_A: 4354 return "A"; 4355 case llvm::ARM::PK_R: 4356 return "R"; 4357 case llvm::ARM::PK_M: 4358 return "M"; 4359 default: 4360 return ""; 4361 } 4362 } 4363 4364 public: 4365 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4366 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4367 IsAAPCS(true), HW_FP(0) { 4368 BigEndian = IsBigEndian; 4369 4370 switch (getTriple().getOS()) { 4371 case llvm::Triple::NetBSD: 4372 PtrDiffType = SignedLong; 4373 break; 4374 default: 4375 PtrDiffType = SignedInt; 4376 break; 4377 } 4378 4379 // cache arch related info 4380 setArchInfo(); 4381 4382 // {} in inline assembly are neon specifiers, not assembly variant 4383 // specifiers. 4384 NoAsmVariants = true; 4385 4386 // FIXME: This duplicates code from the driver that sets the -target-abi 4387 // option - this code is used if -target-abi isn't passed and should 4388 // be unified in some way. 4389 if (Triple.isOSBinFormatMachO()) { 4390 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4391 // the frontend matches that. 4392 if (Triple.getEnvironment() == llvm::Triple::EABI || 4393 Triple.getOS() == llvm::Triple::UnknownOS || 4394 StringRef(CPU).startswith("cortex-m")) { 4395 setABI("aapcs"); 4396 } else { 4397 setABI("apcs-gnu"); 4398 } 4399 } else if (Triple.isOSWindows()) { 4400 // FIXME: this is invalid for WindowsCE 4401 setABI("aapcs"); 4402 } else { 4403 // Select the default based on the platform. 4404 switch (Triple.getEnvironment()) { 4405 case llvm::Triple::Android: 4406 case llvm::Triple::GNUEABI: 4407 case llvm::Triple::GNUEABIHF: 4408 setABI("aapcs-linux"); 4409 break; 4410 case llvm::Triple::EABIHF: 4411 case llvm::Triple::EABI: 4412 setABI("aapcs"); 4413 break; 4414 case llvm::Triple::GNU: 4415 setABI("apcs-gnu"); 4416 break; 4417 default: 4418 if (Triple.getOS() == llvm::Triple::NetBSD) 4419 setABI("apcs-gnu"); 4420 else 4421 setABI("aapcs"); 4422 break; 4423 } 4424 } 4425 4426 // ARM targets default to using the ARM C++ ABI. 4427 TheCXXABI.set(TargetCXXABI::GenericARM); 4428 4429 // ARM has atomics up to 8 bytes 4430 setAtomic(); 4431 4432 // Do force alignment of members that follow zero length bitfields. If 4433 // the alignment of the zero-length bitfield is greater than the member 4434 // that follows it, `bar', `bar' will be aligned as the type of the 4435 // zero length bitfield. 4436 UseZeroLengthBitfieldAlignment = true; 4437 } 4438 4439 StringRef getABI() const override { return ABI; } 4440 4441 bool setABI(const std::string &Name) override { 4442 ABI = Name; 4443 4444 // The defaults (above) are for AAPCS, check if we need to change them. 4445 // 4446 // FIXME: We need support for -meabi... we could just mangle it into the 4447 // name. 4448 if (Name == "apcs-gnu") { 4449 setABIAPCS(); 4450 return true; 4451 } 4452 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4453 setABIAAPCS(); 4454 return true; 4455 } 4456 return false; 4457 } 4458 4459 // FIXME: This should be based on Arch attributes, not CPU names. 4460 void initDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4461 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4462 Features["vfp2"] = true; 4463 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4464 Features["vfp3"] = true; 4465 Features["neon"] = true; 4466 } 4467 else if (CPU == "cortex-a5") { 4468 Features["vfp4"] = true; 4469 Features["neon"] = true; 4470 } else if (CPU == "swift" || CPU == "cortex-a7" || 4471 CPU == "cortex-a12" || CPU == "cortex-a15" || 4472 CPU == "cortex-a17" || CPU == "krait") { 4473 Features["vfp4"] = true; 4474 Features["neon"] = true; 4475 Features["hwdiv"] = true; 4476 Features["hwdiv-arm"] = true; 4477 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4478 CPU == "cortex-a72") { 4479 Features["fp-armv8"] = true; 4480 Features["neon"] = true; 4481 Features["hwdiv"] = true; 4482 Features["hwdiv-arm"] = true; 4483 Features["crc"] = true; 4484 Features["crypto"] = true; 4485 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || ArchVersion == 8) { 4486 Features["hwdiv"] = true; 4487 Features["hwdiv-arm"] = true; 4488 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4489 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4490 Features["hwdiv"] = true; 4491 } 4492 } 4493 4494 bool handleTargetFeatures(std::vector<std::string> &Features, 4495 DiagnosticsEngine &Diags) override { 4496 FPU = 0; 4497 CRC = 0; 4498 Crypto = 0; 4499 SoftFloat = SoftFloatABI = false; 4500 HWDiv = 0; 4501 4502 // This does not diagnose illegal cases like having both 4503 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4504 uint32_t HW_FP_remove = 0; 4505 for (const auto &Feature : Features) { 4506 if (Feature == "+soft-float") { 4507 SoftFloat = true; 4508 } else if (Feature == "+soft-float-abi") { 4509 SoftFloatABI = true; 4510 } else if (Feature == "+vfp2") { 4511 FPU |= VFP2FPU; 4512 HW_FP |= HW_FP_SP | HW_FP_DP; 4513 } else if (Feature == "+vfp3") { 4514 FPU |= VFP3FPU; 4515 HW_FP |= HW_FP_SP | HW_FP_DP; 4516 } else if (Feature == "+vfp4") { 4517 FPU |= VFP4FPU; 4518 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4519 } else if (Feature == "+fp-armv8") { 4520 FPU |= FPARMV8; 4521 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4522 } else if (Feature == "+neon") { 4523 FPU |= NeonFPU; 4524 HW_FP |= HW_FP_SP | HW_FP_DP; 4525 } else if (Feature == "+hwdiv") { 4526 HWDiv |= HWDivThumb; 4527 } else if (Feature == "+hwdiv-arm") { 4528 HWDiv |= HWDivARM; 4529 } else if (Feature == "+crc") { 4530 CRC = 1; 4531 } else if (Feature == "+crypto") { 4532 Crypto = 1; 4533 } else if (Feature == "+fp-only-sp") { 4534 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4535 } 4536 } 4537 HW_FP &= ~HW_FP_remove; 4538 4539 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4540 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4541 return false; 4542 } 4543 4544 if (FPMath == FP_Neon) 4545 Features.push_back("+neonfp"); 4546 else if (FPMath == FP_VFP) 4547 Features.push_back("-neonfp"); 4548 4549 // Remove front-end specific options which the backend handles differently. 4550 auto Feature = 4551 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4552 if (Feature != Features.end()) 4553 Features.erase(Feature); 4554 4555 return true; 4556 } 4557 4558 bool hasFeature(StringRef Feature) const override { 4559 return llvm::StringSwitch<bool>(Feature) 4560 .Case("arm", true) 4561 .Case("aarch32", true) 4562 .Case("softfloat", SoftFloat) 4563 .Case("thumb", isThumb()) 4564 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4565 .Case("hwdiv", HWDiv & HWDivThumb) 4566 .Case("hwdiv-arm", HWDiv & HWDivARM) 4567 .Default(false); 4568 } 4569 4570 bool setCPU(const std::string &Name) override { 4571 if (Name != "generic") 4572 setArchInfo(llvm::ARMTargetParser::parseCPUArch(Name)); 4573 4574 if (ArchKind == llvm::ARM::AK_INVALID) 4575 return false; 4576 setAtomic(); 4577 CPU = Name; 4578 return true; 4579 } 4580 4581 bool setFPMath(StringRef Name) override; 4582 4583 void getTargetDefines(const LangOptions &Opts, 4584 MacroBuilder &Builder) const override { 4585 // Target identification. 4586 Builder.defineMacro("__arm"); 4587 Builder.defineMacro("__arm__"); 4588 4589 // Target properties. 4590 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4591 if (!CPUAttr.empty()) 4592 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4593 4594 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4595 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4596 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4597 if (ArchVersion >= 8) { 4598 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4599 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4600 } 4601 4602 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4603 // is not defined for the M-profile. 4604 // NOTE that the deffault profile is assumed to be 'A' 4605 if (CPUProfile.empty() || CPUProfile != "M") 4606 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4607 4608 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4609 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4610 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4611 if (supportsThumb2()) 4612 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4613 else if (supportsThumb()) 4614 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4615 4616 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4617 // instruction set such as ARM or Thumb. 4618 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4619 4620 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4621 4622 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4623 if (!CPUProfile.empty()) 4624 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4625 4626 // ACLE 6.5.1 Hardware Floating Point 4627 if (HW_FP) 4628 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4629 4630 // ACLE predefines. 4631 Builder.defineMacro("__ARM_ACLE", "200"); 4632 4633 // Subtarget options. 4634 4635 // FIXME: It's more complicated than this and we don't really support 4636 // interworking. 4637 // Windows on ARM does not "support" interworking 4638 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4639 Builder.defineMacro("__THUMB_INTERWORK__"); 4640 4641 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4642 // Embedded targets on Darwin follow AAPCS, but not EABI. 4643 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4644 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4645 Builder.defineMacro("__ARM_EABI__"); 4646 Builder.defineMacro("__ARM_PCS", "1"); 4647 4648 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4649 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4650 } 4651 4652 if (SoftFloat) 4653 Builder.defineMacro("__SOFTFP__"); 4654 4655 if (CPU == "xscale") 4656 Builder.defineMacro("__XSCALE__"); 4657 4658 if (isThumb()) { 4659 Builder.defineMacro("__THUMBEL__"); 4660 Builder.defineMacro("__thumb__"); 4661 if (supportsThumb2()) 4662 Builder.defineMacro("__thumb2__"); 4663 } 4664 if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) 4665 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4666 4667 // Note, this is always on in gcc, even though it doesn't make sense. 4668 Builder.defineMacro("__APCS_32__"); 4669 4670 if (FPUModeIsVFP((FPUMode) FPU)) { 4671 Builder.defineMacro("__VFP_FP__"); 4672 if (FPU & VFP2FPU) 4673 Builder.defineMacro("__ARM_VFPV2__"); 4674 if (FPU & VFP3FPU) 4675 Builder.defineMacro("__ARM_VFPV3__"); 4676 if (FPU & VFP4FPU) 4677 Builder.defineMacro("__ARM_VFPV4__"); 4678 } 4679 4680 // This only gets set when Neon instructions are actually available, unlike 4681 // the VFP define, hence the soft float and arch check. This is subtly 4682 // different from gcc, we follow the intent which was that it should be set 4683 // when Neon instructions are actually available. 4684 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4685 Builder.defineMacro("__ARM_NEON"); 4686 Builder.defineMacro("__ARM_NEON__"); 4687 } 4688 4689 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4690 Opts.ShortWChar ? "2" : "4"); 4691 4692 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4693 Opts.ShortEnums ? "1" : "4"); 4694 4695 if (CRC) 4696 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4697 4698 if (Crypto) 4699 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4700 4701 if (ArchVersion >= 6 && CPUAttr != "6M") { 4702 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4703 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4704 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4705 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4706 } 4707 4708 bool is5EOrAbove = (ArchVersion >= 6 || 4709 (ArchVersion == 5 && CPUAttr.count('E'))); 4710 // FIXME: We are not getting all 32-bit ARM architectures 4711 bool is32Bit = (!isThumb() || supportsThumb2()); 4712 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM")) 4713 Builder.defineMacro("__ARM_FEATURE_DSP"); 4714 } 4715 4716 void getTargetBuiltins(const Builtin::Info *&Records, 4717 unsigned &NumRecords) const override { 4718 Records = BuiltinInfo; 4719 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4720 } 4721 bool isCLZForZeroUndef() const override { return false; } 4722 BuiltinVaListKind getBuiltinVaListKind() const override { 4723 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4724 } 4725 void getGCCRegNames(const char * const *&Names, 4726 unsigned &NumNames) const override; 4727 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4728 unsigned &NumAliases) const override; 4729 bool validateAsmConstraint(const char *&Name, 4730 TargetInfo::ConstraintInfo &Info) const override { 4731 switch (*Name) { 4732 default: break; 4733 case 'l': // r0-r7 4734 case 'h': // r8-r15 4735 case 'w': // VFP Floating point register single precision 4736 case 'P': // VFP Floating point register double precision 4737 Info.setAllowsRegister(); 4738 return true; 4739 case 'I': 4740 case 'J': 4741 case 'K': 4742 case 'L': 4743 case 'M': 4744 // FIXME 4745 return true; 4746 case 'Q': // A memory address that is a single base register. 4747 Info.setAllowsMemory(); 4748 return true; 4749 case 'U': // a memory reference... 4750 switch (Name[1]) { 4751 case 'q': // ...ARMV4 ldrsb 4752 case 'v': // ...VFP load/store (reg+constant offset) 4753 case 'y': // ...iWMMXt load/store 4754 case 't': // address valid for load/store opaque types wider 4755 // than 128-bits 4756 case 'n': // valid address for Neon doubleword vector load/store 4757 case 'm': // valid address for Neon element and structure load/store 4758 case 's': // valid address for non-offset loads/stores of quad-word 4759 // values in four ARM registers 4760 Info.setAllowsMemory(); 4761 Name++; 4762 return true; 4763 } 4764 } 4765 return false; 4766 } 4767 std::string convertConstraint(const char *&Constraint) const override { 4768 std::string R; 4769 switch (*Constraint) { 4770 case 'U': // Two-character constraint; add "^" hint for later parsing. 4771 R = std::string("^") + std::string(Constraint, 2); 4772 Constraint++; 4773 break; 4774 case 'p': // 'p' should be translated to 'r' by default. 4775 R = std::string("r"); 4776 break; 4777 default: 4778 return std::string(1, *Constraint); 4779 } 4780 return R; 4781 } 4782 bool 4783 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4784 std::string &SuggestedModifier) const override { 4785 bool isOutput = (Constraint[0] == '='); 4786 bool isInOut = (Constraint[0] == '+'); 4787 4788 // Strip off constraint modifiers. 4789 while (Constraint[0] == '=' || 4790 Constraint[0] == '+' || 4791 Constraint[0] == '&') 4792 Constraint = Constraint.substr(1); 4793 4794 switch (Constraint[0]) { 4795 default: break; 4796 case 'r': { 4797 switch (Modifier) { 4798 default: 4799 return (isInOut || isOutput || Size <= 64); 4800 case 'q': 4801 // A register of size 32 cannot fit a vector type. 4802 return false; 4803 } 4804 } 4805 } 4806 4807 return true; 4808 } 4809 const char *getClobbers() const override { 4810 // FIXME: Is this really right? 4811 return ""; 4812 } 4813 4814 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4815 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4816 } 4817 4818 int getEHDataRegisterNumber(unsigned RegNo) const override { 4819 if (RegNo == 0) return 0; 4820 if (RegNo == 1) return 1; 4821 return -1; 4822 } 4823 4824 bool hasSjLjLowering() const override { 4825 return true; 4826 } 4827 }; 4828 4829 bool ARMTargetInfo::setFPMath(StringRef Name) { 4830 if (Name == "neon") { 4831 FPMath = FP_Neon; 4832 return true; 4833 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4834 Name == "vfp4") { 4835 FPMath = FP_VFP; 4836 return true; 4837 } 4838 return false; 4839 } 4840 4841 const char * const ARMTargetInfo::GCCRegNames[] = { 4842 // Integer registers 4843 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4844 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4845 4846 // Float registers 4847 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4848 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4849 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4850 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4851 4852 // Double registers 4853 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4854 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4855 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4856 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4857 4858 // Quad registers 4859 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4860 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4861 }; 4862 4863 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4864 unsigned &NumNames) const { 4865 Names = GCCRegNames; 4866 NumNames = llvm::array_lengthof(GCCRegNames); 4867 } 4868 4869 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4870 { { "a1" }, "r0" }, 4871 { { "a2" }, "r1" }, 4872 { { "a3" }, "r2" }, 4873 { { "a4" }, "r3" }, 4874 { { "v1" }, "r4" }, 4875 { { "v2" }, "r5" }, 4876 { { "v3" }, "r6" }, 4877 { { "v4" }, "r7" }, 4878 { { "v5" }, "r8" }, 4879 { { "v6", "rfp" }, "r9" }, 4880 { { "sl" }, "r10" }, 4881 { { "fp" }, "r11" }, 4882 { { "ip" }, "r12" }, 4883 { { "r13" }, "sp" }, 4884 { { "r14" }, "lr" }, 4885 { { "r15" }, "pc" }, 4886 // The S, D and Q registers overlap, but aren't really aliases; we 4887 // don't want to substitute one of these for a different-sized one. 4888 }; 4889 4890 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4891 unsigned &NumAliases) const { 4892 Aliases = GCCRegAliases; 4893 NumAliases = llvm::array_lengthof(GCCRegAliases); 4894 } 4895 4896 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4897 #define BUILTIN(ID, TYPE, ATTRS) \ 4898 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4899 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4900 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4901 #include "clang/Basic/BuiltinsNEON.def" 4902 4903 #define BUILTIN(ID, TYPE, ATTRS) \ 4904 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr}, 4905 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4906 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr}, 4907 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4908 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4909 #include "clang/Basic/BuiltinsARM.def" 4910 }; 4911 4912 class ARMleTargetInfo : public ARMTargetInfo { 4913 public: 4914 ARMleTargetInfo(const llvm::Triple &Triple) 4915 : ARMTargetInfo(Triple, false) { } 4916 void getTargetDefines(const LangOptions &Opts, 4917 MacroBuilder &Builder) const override { 4918 Builder.defineMacro("__ARMEL__"); 4919 ARMTargetInfo::getTargetDefines(Opts, Builder); 4920 } 4921 }; 4922 4923 class ARMbeTargetInfo : public ARMTargetInfo { 4924 public: 4925 ARMbeTargetInfo(const llvm::Triple &Triple) 4926 : ARMTargetInfo(Triple, true) { } 4927 void getTargetDefines(const LangOptions &Opts, 4928 MacroBuilder &Builder) const override { 4929 Builder.defineMacro("__ARMEB__"); 4930 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4931 ARMTargetInfo::getTargetDefines(Opts, Builder); 4932 } 4933 }; 4934 4935 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4936 const llvm::Triple Triple; 4937 public: 4938 WindowsARMTargetInfo(const llvm::Triple &Triple) 4939 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4940 TLSSupported = false; 4941 WCharType = UnsignedShort; 4942 SizeType = UnsignedInt; 4943 UserLabelPrefix = ""; 4944 } 4945 void getVisualStudioDefines(const LangOptions &Opts, 4946 MacroBuilder &Builder) const { 4947 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4948 4949 // FIXME: this is invalid for WindowsCE 4950 Builder.defineMacro("_M_ARM_NT", "1"); 4951 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4952 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4953 4954 assert((Triple.getArch() == llvm::Triple::arm || 4955 Triple.getArch() == llvm::Triple::thumb) && 4956 "invalid architecture for Windows ARM target info"); 4957 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4958 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4959 4960 // TODO map the complete set of values 4961 // 31: VFPv3 40: VFPv4 4962 Builder.defineMacro("_M_ARM_FP", "31"); 4963 } 4964 BuiltinVaListKind getBuiltinVaListKind() const override { 4965 return TargetInfo::CharPtrBuiltinVaList; 4966 } 4967 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4968 switch (CC) { 4969 case CC_X86StdCall: 4970 case CC_X86ThisCall: 4971 case CC_X86FastCall: 4972 case CC_X86VectorCall: 4973 return CCCR_Ignore; 4974 case CC_C: 4975 return CCCR_OK; 4976 default: 4977 return CCCR_Warning; 4978 } 4979 } 4980 }; 4981 4982 // Windows ARM + Itanium C++ ABI Target 4983 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4984 public: 4985 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4986 : WindowsARMTargetInfo(Triple) { 4987 TheCXXABI.set(TargetCXXABI::GenericARM); 4988 } 4989 4990 void getTargetDefines(const LangOptions &Opts, 4991 MacroBuilder &Builder) const override { 4992 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4993 4994 if (Opts.MSVCCompat) 4995 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4996 } 4997 }; 4998 4999 // Windows ARM, MS (C++) ABI 5000 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5001 public: 5002 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5003 : WindowsARMTargetInfo(Triple) { 5004 TheCXXABI.set(TargetCXXABI::Microsoft); 5005 } 5006 5007 void getTargetDefines(const LangOptions &Opts, 5008 MacroBuilder &Builder) const override { 5009 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5010 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5011 } 5012 }; 5013 5014 // ARM MinGW target 5015 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5016 public: 5017 MinGWARMTargetInfo(const llvm::Triple &Triple) 5018 : WindowsARMTargetInfo(Triple) { 5019 TheCXXABI.set(TargetCXXABI::GenericARM); 5020 } 5021 5022 void getTargetDefines(const LangOptions &Opts, 5023 MacroBuilder &Builder) const override { 5024 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5025 DefineStd(Builder, "WIN32", Opts); 5026 DefineStd(Builder, "WINNT", Opts); 5027 Builder.defineMacro("_ARM_"); 5028 addMinGWDefines(Opts, Builder); 5029 } 5030 }; 5031 5032 // ARM Cygwin target 5033 class CygwinARMTargetInfo : public ARMleTargetInfo { 5034 public: 5035 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5036 TLSSupported = false; 5037 WCharType = UnsignedShort; 5038 DoubleAlign = LongLongAlign = 64; 5039 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5040 } 5041 void getTargetDefines(const LangOptions &Opts, 5042 MacroBuilder &Builder) const override { 5043 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5044 Builder.defineMacro("_ARM_"); 5045 Builder.defineMacro("__CYGWIN__"); 5046 Builder.defineMacro("__CYGWIN32__"); 5047 DefineStd(Builder, "unix", Opts); 5048 if (Opts.CPlusPlus) 5049 Builder.defineMacro("_GNU_SOURCE"); 5050 } 5051 }; 5052 5053 class DarwinARMTargetInfo : 5054 public DarwinTargetInfo<ARMleTargetInfo> { 5055 protected: 5056 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5057 MacroBuilder &Builder) const override { 5058 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5059 } 5060 5061 public: 5062 DarwinARMTargetInfo(const llvm::Triple &Triple) 5063 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5064 HasAlignMac68kSupport = true; 5065 // iOS always has 64-bit atomic instructions. 5066 // FIXME: This should be based off of the target features in 5067 // ARMleTargetInfo. 5068 MaxAtomicInlineWidth = 64; 5069 5070 // Darwin on iOS uses a variant of the ARM C++ ABI. 5071 TheCXXABI.set(TargetCXXABI::iOS); 5072 } 5073 }; 5074 5075 class AArch64TargetInfo : public TargetInfo { 5076 virtual void setDataLayoutString() = 0; 5077 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5078 static const char *const GCCRegNames[]; 5079 5080 enum FPUModeEnum { 5081 FPUMode, 5082 NeonMode 5083 }; 5084 5085 unsigned FPU; 5086 unsigned CRC; 5087 unsigned Crypto; 5088 5089 static const Builtin::Info BuiltinInfo[]; 5090 5091 std::string ABI; 5092 5093 public: 5094 AArch64TargetInfo(const llvm::Triple &Triple) 5095 : TargetInfo(Triple), ABI("aapcs") { 5096 5097 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5098 WCharType = SignedInt; 5099 5100 // NetBSD apparently prefers consistency across ARM targets to consistency 5101 // across 64-bit targets. 5102 Int64Type = SignedLongLong; 5103 IntMaxType = SignedLongLong; 5104 } else { 5105 WCharType = UnsignedInt; 5106 Int64Type = SignedLong; 5107 IntMaxType = SignedLong; 5108 } 5109 5110 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5111 MaxVectorAlign = 128; 5112 MaxAtomicInlineWidth = 128; 5113 MaxAtomicPromoteWidth = 128; 5114 5115 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5116 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5117 5118 // {} in inline assembly are neon specifiers, not assembly variant 5119 // specifiers. 5120 NoAsmVariants = true; 5121 5122 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5123 // contributes to the alignment of the containing aggregate in the same way 5124 // a plain (non bit-field) member of that type would, without exception for 5125 // zero-sized or anonymous bit-fields." 5126 UseBitFieldTypeAlignment = true; 5127 UseZeroLengthBitfieldAlignment = true; 5128 5129 // AArch64 targets default to using the ARM C++ ABI. 5130 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5131 } 5132 5133 StringRef getABI() const override { return ABI; } 5134 bool setABI(const std::string &Name) override { 5135 if (Name != "aapcs" && Name != "darwinpcs") 5136 return false; 5137 5138 ABI = Name; 5139 return true; 5140 } 5141 5142 bool setCPU(const std::string &Name) override { 5143 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5144 .Case("generic", true) 5145 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5146 .Case("cyclone", true) 5147 .Default(false); 5148 return CPUKnown; 5149 } 5150 5151 void getTargetDefines(const LangOptions &Opts, 5152 MacroBuilder &Builder) const override { 5153 // Target identification. 5154 Builder.defineMacro("__aarch64__"); 5155 5156 // Target properties. 5157 Builder.defineMacro("_LP64"); 5158 Builder.defineMacro("__LP64__"); 5159 5160 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5161 Builder.defineMacro("__ARM_ACLE", "200"); 5162 Builder.defineMacro("__ARM_ARCH", "8"); 5163 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5164 5165 Builder.defineMacro("__ARM_64BIT_STATE"); 5166 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5167 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5168 5169 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5170 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5171 Builder.defineMacro("__ARM_FEATURE_FMA"); 5172 Builder.defineMacro("__ARM_FEATURE_DIV"); 5173 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5174 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5175 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5176 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5177 5178 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5179 5180 // 0xe implies support for half, single and double precision operations. 5181 Builder.defineMacro("__ARM_FP", "0xe"); 5182 5183 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5184 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5185 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5186 5187 if (Opts.FastMath || Opts.FiniteMathOnly) 5188 Builder.defineMacro("__ARM_FP_FAST"); 5189 5190 if (Opts.C99 && !Opts.Freestanding) 5191 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5192 5193 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5194 5195 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5196 Opts.ShortEnums ? "1" : "4"); 5197 5198 if (FPU == NeonMode) { 5199 Builder.defineMacro("__ARM_NEON"); 5200 // 64-bit NEON supports half, single and double precision operations. 5201 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5202 } 5203 5204 if (CRC) 5205 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5206 5207 if (Crypto) 5208 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5209 5210 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5211 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5212 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5213 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5214 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5215 } 5216 5217 void getTargetBuiltins(const Builtin::Info *&Records, 5218 unsigned &NumRecords) const override { 5219 Records = BuiltinInfo; 5220 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5221 } 5222 5223 bool hasFeature(StringRef Feature) const override { 5224 return Feature == "aarch64" || 5225 Feature == "arm64" || 5226 Feature == "arm" || 5227 (Feature == "neon" && FPU == NeonMode); 5228 } 5229 5230 bool handleTargetFeatures(std::vector<std::string> &Features, 5231 DiagnosticsEngine &Diags) override { 5232 FPU = FPUMode; 5233 CRC = 0; 5234 Crypto = 0; 5235 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5236 if (Features[i] == "+neon") 5237 FPU = NeonMode; 5238 if (Features[i] == "+crc") 5239 CRC = 1; 5240 if (Features[i] == "+crypto") 5241 Crypto = 1; 5242 } 5243 5244 setDataLayoutString(); 5245 5246 return true; 5247 } 5248 5249 bool isCLZForZeroUndef() const override { return false; } 5250 5251 BuiltinVaListKind getBuiltinVaListKind() const override { 5252 return TargetInfo::AArch64ABIBuiltinVaList; 5253 } 5254 5255 void getGCCRegNames(const char *const *&Names, 5256 unsigned &NumNames) const override; 5257 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5258 unsigned &NumAliases) const override; 5259 5260 bool validateAsmConstraint(const char *&Name, 5261 TargetInfo::ConstraintInfo &Info) const override { 5262 switch (*Name) { 5263 default: 5264 return false; 5265 case 'w': // Floating point and SIMD registers (V0-V31) 5266 Info.setAllowsRegister(); 5267 return true; 5268 case 'I': // Constant that can be used with an ADD instruction 5269 case 'J': // Constant that can be used with a SUB instruction 5270 case 'K': // Constant that can be used with a 32-bit logical instruction 5271 case 'L': // Constant that can be used with a 64-bit logical instruction 5272 case 'M': // Constant that can be used as a 32-bit MOV immediate 5273 case 'N': // Constant that can be used as a 64-bit MOV immediate 5274 case 'Y': // Floating point constant zero 5275 case 'Z': // Integer constant zero 5276 return true; 5277 case 'Q': // A memory reference with base register and no offset 5278 Info.setAllowsMemory(); 5279 return true; 5280 case 'S': // A symbolic address 5281 Info.setAllowsRegister(); 5282 return true; 5283 case 'U': 5284 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5285 // Utf: A memory address suitable for ldp/stp in TF mode. 5286 // Usa: An absolute symbolic address. 5287 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5288 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5289 case 'z': // Zero register, wzr or xzr 5290 Info.setAllowsRegister(); 5291 return true; 5292 case 'x': // Floating point and SIMD registers (V0-V15) 5293 Info.setAllowsRegister(); 5294 return true; 5295 } 5296 return false; 5297 } 5298 5299 bool 5300 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5301 std::string &SuggestedModifier) const override { 5302 // Strip off constraint modifiers. 5303 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5304 Constraint = Constraint.substr(1); 5305 5306 switch (Constraint[0]) { 5307 default: 5308 return true; 5309 case 'z': 5310 case 'r': { 5311 switch (Modifier) { 5312 case 'x': 5313 case 'w': 5314 // For now assume that the person knows what they're 5315 // doing with the modifier. 5316 return true; 5317 default: 5318 // By default an 'r' constraint will be in the 'x' 5319 // registers. 5320 if (Size == 64) 5321 return true; 5322 5323 SuggestedModifier = "w"; 5324 return false; 5325 } 5326 } 5327 } 5328 } 5329 5330 const char *getClobbers() const override { return ""; } 5331 5332 int getEHDataRegisterNumber(unsigned RegNo) const override { 5333 if (RegNo == 0) 5334 return 0; 5335 if (RegNo == 1) 5336 return 1; 5337 return -1; 5338 } 5339 }; 5340 5341 const char *const AArch64TargetInfo::GCCRegNames[] = { 5342 // 32-bit Integer registers 5343 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5344 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5345 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5346 5347 // 64-bit Integer registers 5348 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5349 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5350 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5351 5352 // 32-bit floating point regsisters 5353 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5354 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5355 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5356 5357 // 64-bit floating point regsisters 5358 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5359 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5360 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5361 5362 // Vector registers 5363 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5364 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5365 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5366 }; 5367 5368 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5369 unsigned &NumNames) const { 5370 Names = GCCRegNames; 5371 NumNames = llvm::array_lengthof(GCCRegNames); 5372 } 5373 5374 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5375 { { "w31" }, "wsp" }, 5376 { { "x29" }, "fp" }, 5377 { { "x30" }, "lr" }, 5378 { { "x31" }, "sp" }, 5379 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5380 // don't want to substitute one of these for a different-sized one. 5381 }; 5382 5383 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5384 unsigned &NumAliases) const { 5385 Aliases = GCCRegAliases; 5386 NumAliases = llvm::array_lengthof(GCCRegAliases); 5387 } 5388 5389 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5390 #define BUILTIN(ID, TYPE, ATTRS) \ 5391 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5392 #include "clang/Basic/BuiltinsNEON.def" 5393 5394 #define BUILTIN(ID, TYPE, ATTRS) \ 5395 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5396 #include "clang/Basic/BuiltinsAArch64.def" 5397 }; 5398 5399 class AArch64leTargetInfo : public AArch64TargetInfo { 5400 void setDataLayoutString() override { 5401 if (getTriple().isOSBinFormatMachO()) 5402 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5403 else 5404 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5405 } 5406 5407 public: 5408 AArch64leTargetInfo(const llvm::Triple &Triple) 5409 : AArch64TargetInfo(Triple) { 5410 BigEndian = false; 5411 } 5412 void getTargetDefines(const LangOptions &Opts, 5413 MacroBuilder &Builder) const override { 5414 Builder.defineMacro("__AARCH64EL__"); 5415 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5416 } 5417 }; 5418 5419 class AArch64beTargetInfo : public AArch64TargetInfo { 5420 void setDataLayoutString() override { 5421 assert(!getTriple().isOSBinFormatMachO()); 5422 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5423 } 5424 5425 public: 5426 AArch64beTargetInfo(const llvm::Triple &Triple) 5427 : AArch64TargetInfo(Triple) { } 5428 void getTargetDefines(const LangOptions &Opts, 5429 MacroBuilder &Builder) const override { 5430 Builder.defineMacro("__AARCH64EB__"); 5431 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5432 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5433 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5434 } 5435 }; 5436 5437 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5438 protected: 5439 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5440 MacroBuilder &Builder) const override { 5441 Builder.defineMacro("__AARCH64_SIMD__"); 5442 Builder.defineMacro("__ARM64_ARCH_8__"); 5443 Builder.defineMacro("__ARM_NEON__"); 5444 Builder.defineMacro("__LITTLE_ENDIAN__"); 5445 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5446 Builder.defineMacro("__arm64", "1"); 5447 Builder.defineMacro("__arm64__", "1"); 5448 5449 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5450 } 5451 5452 public: 5453 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5454 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5455 Int64Type = SignedLongLong; 5456 WCharType = SignedInt; 5457 UseSignedCharForObjCBool = false; 5458 5459 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5460 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5461 5462 TheCXXABI.set(TargetCXXABI::iOS64); 5463 } 5464 5465 BuiltinVaListKind getBuiltinVaListKind() const override { 5466 return TargetInfo::CharPtrBuiltinVaList; 5467 } 5468 }; 5469 5470 // Hexagon abstract base class 5471 class HexagonTargetInfo : public TargetInfo { 5472 static const Builtin::Info BuiltinInfo[]; 5473 static const char * const GCCRegNames[]; 5474 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5475 std::string CPU; 5476 public: 5477 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5478 BigEndian = false; 5479 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5480 5481 // {} in inline assembly are packet specifiers, not assembly variant 5482 // specifiers. 5483 NoAsmVariants = true; 5484 } 5485 5486 void getTargetBuiltins(const Builtin::Info *&Records, 5487 unsigned &NumRecords) const override { 5488 Records = BuiltinInfo; 5489 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5490 } 5491 5492 bool validateAsmConstraint(const char *&Name, 5493 TargetInfo::ConstraintInfo &Info) const override { 5494 return true; 5495 } 5496 5497 void getTargetDefines(const LangOptions &Opts, 5498 MacroBuilder &Builder) const override; 5499 5500 bool hasFeature(StringRef Feature) const override { 5501 return Feature == "hexagon"; 5502 } 5503 5504 BuiltinVaListKind getBuiltinVaListKind() const override { 5505 return TargetInfo::CharPtrBuiltinVaList; 5506 } 5507 void getGCCRegNames(const char * const *&Names, 5508 unsigned &NumNames) const override; 5509 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5510 unsigned &NumAliases) const override; 5511 const char *getClobbers() const override { 5512 return ""; 5513 } 5514 5515 static const char *getHexagonCPUSuffix(StringRef Name) { 5516 return llvm::StringSwitch<const char*>(Name) 5517 .Case("hexagonv4", "4") 5518 .Case("hexagonv5", "5") 5519 .Default(nullptr); 5520 } 5521 5522 bool setCPU(const std::string &Name) override { 5523 if (!getHexagonCPUSuffix(Name)) 5524 return false; 5525 5526 CPU = Name; 5527 return true; 5528 } 5529 }; 5530 5531 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5532 MacroBuilder &Builder) const { 5533 Builder.defineMacro("qdsp6"); 5534 Builder.defineMacro("__qdsp6", "1"); 5535 Builder.defineMacro("__qdsp6__", "1"); 5536 5537 Builder.defineMacro("hexagon"); 5538 Builder.defineMacro("__hexagon", "1"); 5539 Builder.defineMacro("__hexagon__", "1"); 5540 5541 if(CPU == "hexagonv1") { 5542 Builder.defineMacro("__HEXAGON_V1__"); 5543 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5544 if(Opts.HexagonQdsp6Compat) { 5545 Builder.defineMacro("__QDSP6_V1__"); 5546 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5547 } 5548 } 5549 else if(CPU == "hexagonv2") { 5550 Builder.defineMacro("__HEXAGON_V2__"); 5551 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5552 if(Opts.HexagonQdsp6Compat) { 5553 Builder.defineMacro("__QDSP6_V2__"); 5554 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5555 } 5556 } 5557 else if(CPU == "hexagonv3") { 5558 Builder.defineMacro("__HEXAGON_V3__"); 5559 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5560 if(Opts.HexagonQdsp6Compat) { 5561 Builder.defineMacro("__QDSP6_V3__"); 5562 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5563 } 5564 } 5565 else if(CPU == "hexagonv4") { 5566 Builder.defineMacro("__HEXAGON_V4__"); 5567 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5568 if(Opts.HexagonQdsp6Compat) { 5569 Builder.defineMacro("__QDSP6_V4__"); 5570 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5571 } 5572 } 5573 else if(CPU == "hexagonv5") { 5574 Builder.defineMacro("__HEXAGON_V5__"); 5575 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5576 if(Opts.HexagonQdsp6Compat) { 5577 Builder.defineMacro("__QDSP6_V5__"); 5578 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5579 } 5580 } 5581 } 5582 5583 const char * const HexagonTargetInfo::GCCRegNames[] = { 5584 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5585 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5586 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5587 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5588 "p0", "p1", "p2", "p3", 5589 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5590 }; 5591 5592 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5593 unsigned &NumNames) const { 5594 Names = GCCRegNames; 5595 NumNames = llvm::array_lengthof(GCCRegNames); 5596 } 5597 5598 5599 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5600 { { "sp" }, "r29" }, 5601 { { "fp" }, "r30" }, 5602 { { "lr" }, "r31" }, 5603 }; 5604 5605 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5606 unsigned &NumAliases) const { 5607 Aliases = GCCRegAliases; 5608 NumAliases = llvm::array_lengthof(GCCRegAliases); 5609 } 5610 5611 5612 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5613 #define BUILTIN(ID, TYPE, ATTRS) \ 5614 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5615 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5616 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5617 #include "clang/Basic/BuiltinsHexagon.def" 5618 }; 5619 5620 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5621 class SparcTargetInfo : public TargetInfo { 5622 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5623 static const char * const GCCRegNames[]; 5624 bool SoftFloat; 5625 public: 5626 SparcTargetInfo(const llvm::Triple &Triple) 5627 : TargetInfo(Triple), SoftFloat(false) {} 5628 5629 bool handleTargetFeatures(std::vector<std::string> &Features, 5630 DiagnosticsEngine &Diags) override { 5631 // The backend doesn't actually handle soft float yet, but in case someone 5632 // is using the support for the front end continue to support it. 5633 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5634 if (Feature != Features.end()) { 5635 SoftFloat = true; 5636 Features.erase(Feature); 5637 } 5638 return true; 5639 } 5640 void getTargetDefines(const LangOptions &Opts, 5641 MacroBuilder &Builder) const override { 5642 DefineStd(Builder, "sparc", Opts); 5643 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5644 5645 if (SoftFloat) 5646 Builder.defineMacro("SOFT_FLOAT", "1"); 5647 } 5648 5649 bool hasFeature(StringRef Feature) const override { 5650 return llvm::StringSwitch<bool>(Feature) 5651 .Case("softfloat", SoftFloat) 5652 .Case("sparc", true) 5653 .Default(false); 5654 } 5655 5656 void getTargetBuiltins(const Builtin::Info *&Records, 5657 unsigned &NumRecords) const override { 5658 // FIXME: Implement! 5659 } 5660 BuiltinVaListKind getBuiltinVaListKind() const override { 5661 return TargetInfo::VoidPtrBuiltinVaList; 5662 } 5663 void getGCCRegNames(const char * const *&Names, 5664 unsigned &NumNames) const override; 5665 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5666 unsigned &NumAliases) const override; 5667 bool validateAsmConstraint(const char *&Name, 5668 TargetInfo::ConstraintInfo &info) const override { 5669 // FIXME: Implement! 5670 switch (*Name) { 5671 case 'I': // Signed 13-bit constant 5672 case 'J': // Zero 5673 case 'K': // 32-bit constant with the low 12 bits clear 5674 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5675 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5676 case 'N': // Same as 'K' but zext (required for SIMode) 5677 case 'O': // The constant 4096 5678 return true; 5679 } 5680 return false; 5681 } 5682 const char *getClobbers() const override { 5683 // FIXME: Implement! 5684 return ""; 5685 } 5686 }; 5687 5688 const char * const SparcTargetInfo::GCCRegNames[] = { 5689 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5690 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5691 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5692 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5693 }; 5694 5695 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5696 unsigned &NumNames) const { 5697 Names = GCCRegNames; 5698 NumNames = llvm::array_lengthof(GCCRegNames); 5699 } 5700 5701 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5702 { { "g0" }, "r0" }, 5703 { { "g1" }, "r1" }, 5704 { { "g2" }, "r2" }, 5705 { { "g3" }, "r3" }, 5706 { { "g4" }, "r4" }, 5707 { { "g5" }, "r5" }, 5708 { { "g6" }, "r6" }, 5709 { { "g7" }, "r7" }, 5710 { { "o0" }, "r8" }, 5711 { { "o1" }, "r9" }, 5712 { { "o2" }, "r10" }, 5713 { { "o3" }, "r11" }, 5714 { { "o4" }, "r12" }, 5715 { { "o5" }, "r13" }, 5716 { { "o6", "sp" }, "r14" }, 5717 { { "o7" }, "r15" }, 5718 { { "l0" }, "r16" }, 5719 { { "l1" }, "r17" }, 5720 { { "l2" }, "r18" }, 5721 { { "l3" }, "r19" }, 5722 { { "l4" }, "r20" }, 5723 { { "l5" }, "r21" }, 5724 { { "l6" }, "r22" }, 5725 { { "l7" }, "r23" }, 5726 { { "i0" }, "r24" }, 5727 { { "i1" }, "r25" }, 5728 { { "i2" }, "r26" }, 5729 { { "i3" }, "r27" }, 5730 { { "i4" }, "r28" }, 5731 { { "i5" }, "r29" }, 5732 { { "i6", "fp" }, "r30" }, 5733 { { "i7" }, "r31" }, 5734 }; 5735 5736 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5737 unsigned &NumAliases) const { 5738 Aliases = GCCRegAliases; 5739 NumAliases = llvm::array_lengthof(GCCRegAliases); 5740 } 5741 5742 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5743 class SparcV8TargetInfo : public SparcTargetInfo { 5744 public: 5745 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5746 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5747 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5748 switch (getTriple().getOS()) { 5749 default: 5750 SizeType = UnsignedInt; 5751 IntPtrType = SignedInt; 5752 PtrDiffType = SignedInt; 5753 break; 5754 case llvm::Triple::NetBSD: 5755 case llvm::Triple::OpenBSD: 5756 SizeType = UnsignedLong; 5757 IntPtrType = SignedLong; 5758 PtrDiffType = SignedLong; 5759 break; 5760 } 5761 } 5762 5763 void getTargetDefines(const LangOptions &Opts, 5764 MacroBuilder &Builder) const override { 5765 SparcTargetInfo::getTargetDefines(Opts, Builder); 5766 Builder.defineMacro("__sparcv8"); 5767 } 5768 }; 5769 5770 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5771 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5772 public: 5773 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5774 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5775 BigEndian = false; 5776 } 5777 }; 5778 5779 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5780 class SparcV9TargetInfo : public SparcTargetInfo { 5781 public: 5782 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5783 // FIXME: Support Sparc quad-precision long double? 5784 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5785 // This is an LP64 platform. 5786 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5787 5788 // OpenBSD uses long long for int64_t and intmax_t. 5789 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5790 IntMaxType = SignedLongLong; 5791 else 5792 IntMaxType = SignedLong; 5793 Int64Type = IntMaxType; 5794 5795 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5796 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5797 LongDoubleWidth = 128; 5798 LongDoubleAlign = 128; 5799 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5800 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5801 } 5802 5803 void getTargetDefines(const LangOptions &Opts, 5804 MacroBuilder &Builder) const override { 5805 SparcTargetInfo::getTargetDefines(Opts, Builder); 5806 Builder.defineMacro("__sparcv9"); 5807 Builder.defineMacro("__arch64__"); 5808 // Solaris doesn't need these variants, but the BSDs do. 5809 if (getTriple().getOS() != llvm::Triple::Solaris) { 5810 Builder.defineMacro("__sparc64__"); 5811 Builder.defineMacro("__sparc_v9__"); 5812 Builder.defineMacro("__sparcv9__"); 5813 } 5814 } 5815 5816 bool setCPU(const std::string &Name) override { 5817 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5818 .Case("v9", true) 5819 .Case("ultrasparc", true) 5820 .Case("ultrasparc3", true) 5821 .Case("niagara", true) 5822 .Case("niagara2", true) 5823 .Case("niagara3", true) 5824 .Case("niagara4", true) 5825 .Default(false); 5826 5827 // No need to store the CPU yet. There aren't any CPU-specific 5828 // macros to define. 5829 return CPUKnown; 5830 } 5831 }; 5832 5833 class SystemZTargetInfo : public TargetInfo { 5834 static const Builtin::Info BuiltinInfo[]; 5835 static const char *const GCCRegNames[]; 5836 std::string CPU; 5837 bool HasTransactionalExecution; 5838 bool HasVector; 5839 5840 public: 5841 SystemZTargetInfo(const llvm::Triple &Triple) 5842 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5843 IntMaxType = SignedLong; 5844 Int64Type = SignedLong; 5845 TLSSupported = true; 5846 IntWidth = IntAlign = 32; 5847 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5848 PointerWidth = PointerAlign = 64; 5849 LongDoubleWidth = 128; 5850 LongDoubleAlign = 64; 5851 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5852 DefaultAlignForAttributeAligned = 64; 5853 MinGlobalAlign = 16; 5854 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5855 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5856 } 5857 void getTargetDefines(const LangOptions &Opts, 5858 MacroBuilder &Builder) const override { 5859 Builder.defineMacro("__s390__"); 5860 Builder.defineMacro("__s390x__"); 5861 Builder.defineMacro("__zarch__"); 5862 Builder.defineMacro("__LONG_DOUBLE_128__"); 5863 if (HasTransactionalExecution) 5864 Builder.defineMacro("__HTM__"); 5865 if (Opts.ZVector) 5866 Builder.defineMacro("__VEC__", "10301"); 5867 } 5868 void getTargetBuiltins(const Builtin::Info *&Records, 5869 unsigned &NumRecords) const override { 5870 Records = BuiltinInfo; 5871 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5872 } 5873 5874 void getGCCRegNames(const char *const *&Names, 5875 unsigned &NumNames) const override; 5876 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5877 unsigned &NumAliases) const override { 5878 // No aliases. 5879 Aliases = nullptr; 5880 NumAliases = 0; 5881 } 5882 bool validateAsmConstraint(const char *&Name, 5883 TargetInfo::ConstraintInfo &info) const override; 5884 const char *getClobbers() const override { 5885 // FIXME: Is this really right? 5886 return ""; 5887 } 5888 BuiltinVaListKind getBuiltinVaListKind() const override { 5889 return TargetInfo::SystemZBuiltinVaList; 5890 } 5891 bool setCPU(const std::string &Name) override { 5892 CPU = Name; 5893 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5894 .Case("z10", true) 5895 .Case("z196", true) 5896 .Case("zEC12", true) 5897 .Case("z13", true) 5898 .Default(false); 5899 5900 return CPUKnown; 5901 } 5902 void initDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5903 if (CPU == "zEC12") 5904 Features["transactional-execution"] = true; 5905 if (CPU == "z13") { 5906 Features["transactional-execution"] = true; 5907 Features["vector"] = true; 5908 } 5909 } 5910 5911 bool handleTargetFeatures(std::vector<std::string> &Features, 5912 DiagnosticsEngine &Diags) override { 5913 HasTransactionalExecution = false; 5914 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5915 if (Features[i] == "+transactional-execution") 5916 HasTransactionalExecution = true; 5917 if (Features[i] == "+vector") 5918 HasVector = true; 5919 } 5920 // If we use the vector ABI, vector types are 64-bit aligned. 5921 if (HasVector) { 5922 MaxVectorAlign = 64; 5923 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5924 "-v128:64-a:8:16-n32:64"; 5925 } 5926 return true; 5927 } 5928 5929 bool hasFeature(StringRef Feature) const override { 5930 return llvm::StringSwitch<bool>(Feature) 5931 .Case("systemz", true) 5932 .Case("htm", HasTransactionalExecution) 5933 .Case("vx", HasVector) 5934 .Default(false); 5935 } 5936 5937 StringRef getABI() const override { 5938 if (HasVector) 5939 return "vector"; 5940 return ""; 5941 } 5942 5943 bool useFloat128ManglingForLongDouble() const override { 5944 return true; 5945 } 5946 }; 5947 5948 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5949 #define BUILTIN(ID, TYPE, ATTRS) \ 5950 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5951 #include "clang/Basic/BuiltinsSystemZ.def" 5952 }; 5953 5954 const char *const SystemZTargetInfo::GCCRegNames[] = { 5955 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5956 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5957 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5958 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5959 }; 5960 5961 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5962 unsigned &NumNames) const { 5963 Names = GCCRegNames; 5964 NumNames = llvm::array_lengthof(GCCRegNames); 5965 } 5966 5967 bool SystemZTargetInfo:: 5968 validateAsmConstraint(const char *&Name, 5969 TargetInfo::ConstraintInfo &Info) const { 5970 switch (*Name) { 5971 default: 5972 return false; 5973 5974 case 'a': // Address register 5975 case 'd': // Data register (equivalent to 'r') 5976 case 'f': // Floating-point register 5977 Info.setAllowsRegister(); 5978 return true; 5979 5980 case 'I': // Unsigned 8-bit constant 5981 case 'J': // Unsigned 12-bit constant 5982 case 'K': // Signed 16-bit constant 5983 case 'L': // Signed 20-bit displacement (on all targets we support) 5984 case 'M': // 0x7fffffff 5985 return true; 5986 5987 case 'Q': // Memory with base and unsigned 12-bit displacement 5988 case 'R': // Likewise, plus an index 5989 case 'S': // Memory with base and signed 20-bit displacement 5990 case 'T': // Likewise, plus an index 5991 Info.setAllowsMemory(); 5992 return true; 5993 } 5994 } 5995 5996 class MSP430TargetInfo : public TargetInfo { 5997 static const char * const GCCRegNames[]; 5998 public: 5999 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6000 BigEndian = false; 6001 TLSSupported = false; 6002 IntWidth = 16; IntAlign = 16; 6003 LongWidth = 32; LongLongWidth = 64; 6004 LongAlign = LongLongAlign = 16; 6005 PointerWidth = 16; PointerAlign = 16; 6006 SuitableAlign = 16; 6007 SizeType = UnsignedInt; 6008 IntMaxType = SignedLongLong; 6009 IntPtrType = SignedInt; 6010 PtrDiffType = SignedInt; 6011 SigAtomicType = SignedLong; 6012 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6013 } 6014 void getTargetDefines(const LangOptions &Opts, 6015 MacroBuilder &Builder) const override { 6016 Builder.defineMacro("MSP430"); 6017 Builder.defineMacro("__MSP430__"); 6018 // FIXME: defines for different 'flavours' of MCU 6019 } 6020 void getTargetBuiltins(const Builtin::Info *&Records, 6021 unsigned &NumRecords) const override { 6022 // FIXME: Implement. 6023 Records = nullptr; 6024 NumRecords = 0; 6025 } 6026 bool hasFeature(StringRef Feature) const override { 6027 return Feature == "msp430"; 6028 } 6029 void getGCCRegNames(const char * const *&Names, 6030 unsigned &NumNames) const override; 6031 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6032 unsigned &NumAliases) const override { 6033 // No aliases. 6034 Aliases = nullptr; 6035 NumAliases = 0; 6036 } 6037 bool 6038 validateAsmConstraint(const char *&Name, 6039 TargetInfo::ConstraintInfo &info) const override { 6040 // FIXME: implement 6041 switch (*Name) { 6042 case 'K': // the constant 1 6043 case 'L': // constant -1^20 .. 1^19 6044 case 'M': // constant 1-4: 6045 return true; 6046 } 6047 // No target constraints for now. 6048 return false; 6049 } 6050 const char *getClobbers() const override { 6051 // FIXME: Is this really right? 6052 return ""; 6053 } 6054 BuiltinVaListKind getBuiltinVaListKind() const override { 6055 // FIXME: implement 6056 return TargetInfo::CharPtrBuiltinVaList; 6057 } 6058 }; 6059 6060 const char * const MSP430TargetInfo::GCCRegNames[] = { 6061 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6062 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 6063 }; 6064 6065 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 6066 unsigned &NumNames) const { 6067 Names = GCCRegNames; 6068 NumNames = llvm::array_lengthof(GCCRegNames); 6069 } 6070 6071 // LLVM and Clang cannot be used directly to output native binaries for 6072 // target, but is used to compile C code to llvm bitcode with correct 6073 // type and alignment information. 6074 // 6075 // TCE uses the llvm bitcode as input and uses it for generating customized 6076 // target processor and program binary. TCE co-design environment is 6077 // publicly available in http://tce.cs.tut.fi 6078 6079 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6080 3, // opencl_global 6081 4, // opencl_local 6082 5, // opencl_constant 6083 // FIXME: generic has to be added to the target 6084 0, // opencl_generic 6085 0, // cuda_device 6086 0, // cuda_constant 6087 0 // cuda_shared 6088 }; 6089 6090 class TCETargetInfo : public TargetInfo{ 6091 public: 6092 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6093 TLSSupported = false; 6094 IntWidth = 32; 6095 LongWidth = LongLongWidth = 32; 6096 PointerWidth = 32; 6097 IntAlign = 32; 6098 LongAlign = LongLongAlign = 32; 6099 PointerAlign = 32; 6100 SuitableAlign = 32; 6101 SizeType = UnsignedInt; 6102 IntMaxType = SignedLong; 6103 IntPtrType = SignedInt; 6104 PtrDiffType = SignedInt; 6105 FloatWidth = 32; 6106 FloatAlign = 32; 6107 DoubleWidth = 32; 6108 DoubleAlign = 32; 6109 LongDoubleWidth = 32; 6110 LongDoubleAlign = 32; 6111 FloatFormat = &llvm::APFloat::IEEEsingle; 6112 DoubleFormat = &llvm::APFloat::IEEEsingle; 6113 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6114 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6115 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6116 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6117 UseAddrSpaceMapMangling = true; 6118 } 6119 6120 void getTargetDefines(const LangOptions &Opts, 6121 MacroBuilder &Builder) const override { 6122 DefineStd(Builder, "tce", Opts); 6123 Builder.defineMacro("__TCE__"); 6124 Builder.defineMacro("__TCE_V1__"); 6125 } 6126 bool hasFeature(StringRef Feature) const override { 6127 return Feature == "tce"; 6128 } 6129 6130 void getTargetBuiltins(const Builtin::Info *&Records, 6131 unsigned &NumRecords) const override {} 6132 const char *getClobbers() const override { 6133 return ""; 6134 } 6135 BuiltinVaListKind getBuiltinVaListKind() const override { 6136 return TargetInfo::VoidPtrBuiltinVaList; 6137 } 6138 void getGCCRegNames(const char * const *&Names, 6139 unsigned &NumNames) const override {} 6140 bool validateAsmConstraint(const char *&Name, 6141 TargetInfo::ConstraintInfo &info) const override{ 6142 return true; 6143 } 6144 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6145 unsigned &NumAliases) const override {} 6146 }; 6147 6148 class BPFTargetInfo : public TargetInfo { 6149 public: 6150 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6151 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6152 SizeType = UnsignedLong; 6153 PtrDiffType = SignedLong; 6154 IntPtrType = SignedLong; 6155 IntMaxType = SignedLong; 6156 Int64Type = SignedLong; 6157 RegParmMax = 5; 6158 if (Triple.getArch() == llvm::Triple::bpfeb) { 6159 BigEndian = true; 6160 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6161 } else { 6162 BigEndian = false; 6163 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6164 } 6165 MaxAtomicPromoteWidth = 64; 6166 MaxAtomicInlineWidth = 64; 6167 TLSSupported = false; 6168 } 6169 void getTargetDefines(const LangOptions &Opts, 6170 MacroBuilder &Builder) const override { 6171 DefineStd(Builder, "bpf", Opts); 6172 Builder.defineMacro("__BPF__"); 6173 } 6174 bool hasFeature(StringRef Feature) const override { 6175 return Feature == "bpf"; 6176 } 6177 6178 void getTargetBuiltins(const Builtin::Info *&Records, 6179 unsigned &NumRecords) const override {} 6180 const char *getClobbers() const override { 6181 return ""; 6182 } 6183 BuiltinVaListKind getBuiltinVaListKind() const override { 6184 return TargetInfo::VoidPtrBuiltinVaList; 6185 } 6186 void getGCCRegNames(const char * const *&Names, 6187 unsigned &NumNames) const override { 6188 Names = nullptr; 6189 NumNames = 0; 6190 } 6191 bool validateAsmConstraint(const char *&Name, 6192 TargetInfo::ConstraintInfo &info) const override { 6193 return true; 6194 } 6195 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6196 unsigned &NumAliases) const override { 6197 Aliases = nullptr; 6198 NumAliases = 0; 6199 } 6200 }; 6201 6202 class MipsTargetInfoBase : public TargetInfo { 6203 virtual void setDataLayoutString() = 0; 6204 6205 static const Builtin::Info BuiltinInfo[]; 6206 std::string CPU; 6207 bool IsMips16; 6208 bool IsMicromips; 6209 bool IsNan2008; 6210 bool IsSingleFloat; 6211 enum MipsFloatABI { 6212 HardFloat, SoftFloat 6213 } FloatABI; 6214 enum DspRevEnum { 6215 NoDSP, DSP1, DSP2 6216 } DspRev; 6217 bool HasMSA; 6218 6219 protected: 6220 bool HasFP64; 6221 std::string ABI; 6222 6223 public: 6224 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6225 const std::string &CPUStr) 6226 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6227 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6228 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6229 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6230 } 6231 6232 bool isNaN2008Default() const { 6233 return CPU == "mips32r6" || CPU == "mips64r6"; 6234 } 6235 6236 bool isFP64Default() const { 6237 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6238 } 6239 6240 bool isNan2008() const override { 6241 return IsNan2008; 6242 } 6243 6244 StringRef getABI() const override { return ABI; } 6245 bool setCPU(const std::string &Name) override { 6246 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6247 getTriple().getArch() == llvm::Triple::mipsel; 6248 CPU = Name; 6249 return llvm::StringSwitch<bool>(Name) 6250 .Case("mips1", IsMips32) 6251 .Case("mips2", IsMips32) 6252 .Case("mips3", true) 6253 .Case("mips4", true) 6254 .Case("mips5", true) 6255 .Case("mips32", IsMips32) 6256 .Case("mips32r2", IsMips32) 6257 .Case("mips32r3", IsMips32) 6258 .Case("mips32r5", IsMips32) 6259 .Case("mips32r6", IsMips32) 6260 .Case("mips64", true) 6261 .Case("mips64r2", true) 6262 .Case("mips64r3", true) 6263 .Case("mips64r5", true) 6264 .Case("mips64r6", true) 6265 .Case("octeon", true) 6266 .Default(false); 6267 } 6268 const std::string& getCPU() const { return CPU; } 6269 void initDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6270 if (CPU == "octeon") 6271 Features["mips64r2"] = Features["cnmips"] = true; 6272 else 6273 Features[CPU] = true; 6274 } 6275 6276 void getTargetDefines(const LangOptions &Opts, 6277 MacroBuilder &Builder) const override { 6278 Builder.defineMacro("__mips__"); 6279 Builder.defineMacro("_mips"); 6280 if (Opts.GNUMode) 6281 Builder.defineMacro("mips"); 6282 6283 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6284 6285 switch (FloatABI) { 6286 case HardFloat: 6287 Builder.defineMacro("__mips_hard_float", Twine(1)); 6288 break; 6289 case SoftFloat: 6290 Builder.defineMacro("__mips_soft_float", Twine(1)); 6291 break; 6292 } 6293 6294 if (IsSingleFloat) 6295 Builder.defineMacro("__mips_single_float", Twine(1)); 6296 6297 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6298 Builder.defineMacro("_MIPS_FPSET", 6299 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6300 6301 if (IsMips16) 6302 Builder.defineMacro("__mips16", Twine(1)); 6303 6304 if (IsMicromips) 6305 Builder.defineMacro("__mips_micromips", Twine(1)); 6306 6307 if (IsNan2008) 6308 Builder.defineMacro("__mips_nan2008", Twine(1)); 6309 6310 switch (DspRev) { 6311 default: 6312 break; 6313 case DSP1: 6314 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6315 Builder.defineMacro("__mips_dsp", Twine(1)); 6316 break; 6317 case DSP2: 6318 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6319 Builder.defineMacro("__mips_dspr2", Twine(1)); 6320 Builder.defineMacro("__mips_dsp", Twine(1)); 6321 break; 6322 } 6323 6324 if (HasMSA) 6325 Builder.defineMacro("__mips_msa", Twine(1)); 6326 6327 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6328 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6329 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6330 6331 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6332 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6333 } 6334 6335 void getTargetBuiltins(const Builtin::Info *&Records, 6336 unsigned &NumRecords) const override { 6337 Records = BuiltinInfo; 6338 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6339 } 6340 bool hasFeature(StringRef Feature) const override { 6341 return llvm::StringSwitch<bool>(Feature) 6342 .Case("mips", true) 6343 .Case("fp64", HasFP64) 6344 .Default(false); 6345 } 6346 BuiltinVaListKind getBuiltinVaListKind() const override { 6347 return TargetInfo::VoidPtrBuiltinVaList; 6348 } 6349 void getGCCRegNames(const char * const *&Names, 6350 unsigned &NumNames) const override { 6351 static const char *const GCCRegNames[] = { 6352 // CPU register names 6353 // Must match second column of GCCRegAliases 6354 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6355 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6356 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6357 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6358 // Floating point register names 6359 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6360 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6361 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6362 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6363 // Hi/lo and condition register names 6364 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6365 "$fcc5","$fcc6","$fcc7", 6366 // MSA register names 6367 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6368 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6369 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6370 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6371 // MSA control register names 6372 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6373 "$msarequest", "$msamap", "$msaunmap" 6374 }; 6375 Names = GCCRegNames; 6376 NumNames = llvm::array_lengthof(GCCRegNames); 6377 } 6378 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6379 unsigned &NumAliases) const override = 0; 6380 bool validateAsmConstraint(const char *&Name, 6381 TargetInfo::ConstraintInfo &Info) const override { 6382 switch (*Name) { 6383 default: 6384 return false; 6385 case 'r': // CPU registers. 6386 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6387 case 'y': // Equivalent to "r", backward compatibility only. 6388 case 'f': // floating-point registers. 6389 case 'c': // $25 for indirect jumps 6390 case 'l': // lo register 6391 case 'x': // hilo register pair 6392 Info.setAllowsRegister(); 6393 return true; 6394 case 'I': // Signed 16-bit constant 6395 case 'J': // Integer 0 6396 case 'K': // Unsigned 16-bit constant 6397 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6398 case 'M': // Constants not loadable via lui, addiu, or ori 6399 case 'N': // Constant -1 to -65535 6400 case 'O': // A signed 15-bit constant 6401 case 'P': // A constant between 1 go 65535 6402 return true; 6403 case 'R': // An address that can be used in a non-macro load or store 6404 Info.setAllowsMemory(); 6405 return true; 6406 case 'Z': 6407 if (Name[1] == 'C') { // An address usable by ll, and sc. 6408 Info.setAllowsMemory(); 6409 Name++; // Skip over 'Z'. 6410 return true; 6411 } 6412 return false; 6413 } 6414 } 6415 6416 std::string convertConstraint(const char *&Constraint) const override { 6417 std::string R; 6418 switch (*Constraint) { 6419 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6420 if (Constraint[1] == 'C') { 6421 R = std::string("^") + std::string(Constraint, 2); 6422 Constraint++; 6423 return R; 6424 } 6425 break; 6426 } 6427 return TargetInfo::convertConstraint(Constraint); 6428 } 6429 6430 const char *getClobbers() const override { 6431 // In GCC, $1 is not widely used in generated code (it's used only in a few 6432 // specific situations), so there is no real need for users to add it to 6433 // the clobbers list if they want to use it in their inline assembly code. 6434 // 6435 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6436 // code generation, so using it in inline assembly without adding it to the 6437 // clobbers list can cause conflicts between the inline assembly code and 6438 // the surrounding generated code. 6439 // 6440 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6441 // operands, which will conflict with the ".set at" assembler option (which 6442 // we use only for inline assembly, in order to maintain compatibility with 6443 // GCC) and will also conflict with the user's usage of $1. 6444 // 6445 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6446 // register for generated code is to automatically clobber $1 for all inline 6447 // assembly code. 6448 // 6449 // FIXME: We should automatically clobber $1 only for inline assembly code 6450 // which actually uses it. This would allow LLVM to use $1 for inline 6451 // assembly operands if the user's assembly code doesn't use it. 6452 return "~{$1}"; 6453 } 6454 6455 bool handleTargetFeatures(std::vector<std::string> &Features, 6456 DiagnosticsEngine &Diags) override { 6457 IsMips16 = false; 6458 IsMicromips = false; 6459 IsNan2008 = isNaN2008Default(); 6460 IsSingleFloat = false; 6461 FloatABI = HardFloat; 6462 DspRev = NoDSP; 6463 HasFP64 = isFP64Default(); 6464 6465 for (std::vector<std::string>::iterator it = Features.begin(), 6466 ie = Features.end(); it != ie; ++it) { 6467 if (*it == "+single-float") 6468 IsSingleFloat = true; 6469 else if (*it == "+soft-float") 6470 FloatABI = SoftFloat; 6471 else if (*it == "+mips16") 6472 IsMips16 = true; 6473 else if (*it == "+micromips") 6474 IsMicromips = true; 6475 else if (*it == "+dsp") 6476 DspRev = std::max(DspRev, DSP1); 6477 else if (*it == "+dspr2") 6478 DspRev = std::max(DspRev, DSP2); 6479 else if (*it == "+msa") 6480 HasMSA = true; 6481 else if (*it == "+fp64") 6482 HasFP64 = true; 6483 else if (*it == "-fp64") 6484 HasFP64 = false; 6485 else if (*it == "+nan2008") 6486 IsNan2008 = true; 6487 else if (*it == "-nan2008") 6488 IsNan2008 = false; 6489 } 6490 6491 setDataLayoutString(); 6492 6493 return true; 6494 } 6495 6496 int getEHDataRegisterNumber(unsigned RegNo) const override { 6497 if (RegNo == 0) return 4; 6498 if (RegNo == 1) return 5; 6499 return -1; 6500 } 6501 6502 bool isCLZForZeroUndef() const override { return false; } 6503 }; 6504 6505 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6506 #define BUILTIN(ID, TYPE, ATTRS) \ 6507 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6508 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6509 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6510 #include "clang/Basic/BuiltinsMips.def" 6511 }; 6512 6513 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6514 public: 6515 Mips32TargetInfoBase(const llvm::Triple &Triple) 6516 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6517 SizeType = UnsignedInt; 6518 PtrDiffType = SignedInt; 6519 Int64Type = SignedLongLong; 6520 IntMaxType = Int64Type; 6521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6522 } 6523 bool setABI(const std::string &Name) override { 6524 if (Name == "o32" || Name == "eabi") { 6525 ABI = Name; 6526 return true; 6527 } 6528 return false; 6529 } 6530 void getTargetDefines(const LangOptions &Opts, 6531 MacroBuilder &Builder) const override { 6532 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6533 6534 Builder.defineMacro("__mips", "32"); 6535 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6536 6537 const std::string& CPUStr = getCPU(); 6538 if (CPUStr == "mips32") 6539 Builder.defineMacro("__mips_isa_rev", "1"); 6540 else if (CPUStr == "mips32r2") 6541 Builder.defineMacro("__mips_isa_rev", "2"); 6542 else if (CPUStr == "mips32r3") 6543 Builder.defineMacro("__mips_isa_rev", "3"); 6544 else if (CPUStr == "mips32r5") 6545 Builder.defineMacro("__mips_isa_rev", "5"); 6546 else if (CPUStr == "mips32r6") 6547 Builder.defineMacro("__mips_isa_rev", "6"); 6548 6549 if (ABI == "o32") { 6550 Builder.defineMacro("__mips_o32"); 6551 Builder.defineMacro("_ABIO32", "1"); 6552 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6553 } 6554 else if (ABI == "eabi") 6555 Builder.defineMacro("__mips_eabi"); 6556 else 6557 llvm_unreachable("Invalid ABI for Mips32."); 6558 } 6559 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6560 unsigned &NumAliases) const override { 6561 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6562 { { "at" }, "$1" }, 6563 { { "v0" }, "$2" }, 6564 { { "v1" }, "$3" }, 6565 { { "a0" }, "$4" }, 6566 { { "a1" }, "$5" }, 6567 { { "a2" }, "$6" }, 6568 { { "a3" }, "$7" }, 6569 { { "t0" }, "$8" }, 6570 { { "t1" }, "$9" }, 6571 { { "t2" }, "$10" }, 6572 { { "t3" }, "$11" }, 6573 { { "t4" }, "$12" }, 6574 { { "t5" }, "$13" }, 6575 { { "t6" }, "$14" }, 6576 { { "t7" }, "$15" }, 6577 { { "s0" }, "$16" }, 6578 { { "s1" }, "$17" }, 6579 { { "s2" }, "$18" }, 6580 { { "s3" }, "$19" }, 6581 { { "s4" }, "$20" }, 6582 { { "s5" }, "$21" }, 6583 { { "s6" }, "$22" }, 6584 { { "s7" }, "$23" }, 6585 { { "t8" }, "$24" }, 6586 { { "t9" }, "$25" }, 6587 { { "k0" }, "$26" }, 6588 { { "k1" }, "$27" }, 6589 { { "gp" }, "$28" }, 6590 { { "sp","$sp" }, "$29" }, 6591 { { "fp","$fp" }, "$30" }, 6592 { { "ra" }, "$31" } 6593 }; 6594 Aliases = GCCRegAliases; 6595 NumAliases = llvm::array_lengthof(GCCRegAliases); 6596 } 6597 }; 6598 6599 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6600 void setDataLayoutString() override { 6601 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6602 } 6603 6604 public: 6605 Mips32EBTargetInfo(const llvm::Triple &Triple) 6606 : Mips32TargetInfoBase(Triple) { 6607 } 6608 void getTargetDefines(const LangOptions &Opts, 6609 MacroBuilder &Builder) const override { 6610 DefineStd(Builder, "MIPSEB", Opts); 6611 Builder.defineMacro("_MIPSEB"); 6612 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6613 } 6614 }; 6615 6616 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6617 void setDataLayoutString() override { 6618 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6619 } 6620 6621 public: 6622 Mips32ELTargetInfo(const llvm::Triple &Triple) 6623 : Mips32TargetInfoBase(Triple) { 6624 BigEndian = false; 6625 } 6626 void getTargetDefines(const LangOptions &Opts, 6627 MacroBuilder &Builder) const override { 6628 DefineStd(Builder, "MIPSEL", Opts); 6629 Builder.defineMacro("_MIPSEL"); 6630 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6631 } 6632 }; 6633 6634 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6635 public: 6636 Mips64TargetInfoBase(const llvm::Triple &Triple) 6637 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6638 LongDoubleWidth = LongDoubleAlign = 128; 6639 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6640 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6641 LongDoubleWidth = LongDoubleAlign = 64; 6642 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6643 } 6644 setN64ABITypes(); 6645 SuitableAlign = 128; 6646 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6647 } 6648 6649 void setN64ABITypes() { 6650 LongWidth = LongAlign = 64; 6651 PointerWidth = PointerAlign = 64; 6652 SizeType = UnsignedLong; 6653 PtrDiffType = SignedLong; 6654 Int64Type = SignedLong; 6655 IntMaxType = Int64Type; 6656 } 6657 6658 void setN32ABITypes() { 6659 LongWidth = LongAlign = 32; 6660 PointerWidth = PointerAlign = 32; 6661 SizeType = UnsignedInt; 6662 PtrDiffType = SignedInt; 6663 Int64Type = SignedLongLong; 6664 IntMaxType = Int64Type; 6665 } 6666 6667 bool setABI(const std::string &Name) override { 6668 if (Name == "n32") { 6669 setN32ABITypes(); 6670 ABI = Name; 6671 return true; 6672 } 6673 if (Name == "n64") { 6674 setN64ABITypes(); 6675 ABI = Name; 6676 return true; 6677 } 6678 return false; 6679 } 6680 6681 void getTargetDefines(const LangOptions &Opts, 6682 MacroBuilder &Builder) const override { 6683 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6684 6685 Builder.defineMacro("__mips", "64"); 6686 Builder.defineMacro("__mips64"); 6687 Builder.defineMacro("__mips64__"); 6688 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6689 6690 const std::string& CPUStr = getCPU(); 6691 if (CPUStr == "mips64") 6692 Builder.defineMacro("__mips_isa_rev", "1"); 6693 else if (CPUStr == "mips64r2") 6694 Builder.defineMacro("__mips_isa_rev", "2"); 6695 else if (CPUStr == "mips64r3") 6696 Builder.defineMacro("__mips_isa_rev", "3"); 6697 else if (CPUStr == "mips64r5") 6698 Builder.defineMacro("__mips_isa_rev", "5"); 6699 else if (CPUStr == "mips64r6") 6700 Builder.defineMacro("__mips_isa_rev", "6"); 6701 6702 if (ABI == "n32") { 6703 Builder.defineMacro("__mips_n32"); 6704 Builder.defineMacro("_ABIN32", "2"); 6705 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6706 } 6707 else if (ABI == "n64") { 6708 Builder.defineMacro("__mips_n64"); 6709 Builder.defineMacro("_ABI64", "3"); 6710 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6711 } 6712 else 6713 llvm_unreachable("Invalid ABI for Mips64."); 6714 } 6715 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6716 unsigned &NumAliases) const override { 6717 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6718 { { "at" }, "$1" }, 6719 { { "v0" }, "$2" }, 6720 { { "v1" }, "$3" }, 6721 { { "a0" }, "$4" }, 6722 { { "a1" }, "$5" }, 6723 { { "a2" }, "$6" }, 6724 { { "a3" }, "$7" }, 6725 { { "a4" }, "$8" }, 6726 { { "a5" }, "$9" }, 6727 { { "a6" }, "$10" }, 6728 { { "a7" }, "$11" }, 6729 { { "t0" }, "$12" }, 6730 { { "t1" }, "$13" }, 6731 { { "t2" }, "$14" }, 6732 { { "t3" }, "$15" }, 6733 { { "s0" }, "$16" }, 6734 { { "s1" }, "$17" }, 6735 { { "s2" }, "$18" }, 6736 { { "s3" }, "$19" }, 6737 { { "s4" }, "$20" }, 6738 { { "s5" }, "$21" }, 6739 { { "s6" }, "$22" }, 6740 { { "s7" }, "$23" }, 6741 { { "t8" }, "$24" }, 6742 { { "t9" }, "$25" }, 6743 { { "k0" }, "$26" }, 6744 { { "k1" }, "$27" }, 6745 { { "gp" }, "$28" }, 6746 { { "sp","$sp" }, "$29" }, 6747 { { "fp","$fp" }, "$30" }, 6748 { { "ra" }, "$31" } 6749 }; 6750 Aliases = GCCRegAliases; 6751 NumAliases = llvm::array_lengthof(GCCRegAliases); 6752 } 6753 6754 bool hasInt128Type() const override { return true; } 6755 }; 6756 6757 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6758 void setDataLayoutString() override { 6759 if (ABI == "n32") 6760 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6761 else 6762 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6763 6764 } 6765 6766 public: 6767 Mips64EBTargetInfo(const llvm::Triple &Triple) 6768 : Mips64TargetInfoBase(Triple) {} 6769 void getTargetDefines(const LangOptions &Opts, 6770 MacroBuilder &Builder) const override { 6771 DefineStd(Builder, "MIPSEB", Opts); 6772 Builder.defineMacro("_MIPSEB"); 6773 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6774 } 6775 }; 6776 6777 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6778 void setDataLayoutString() override { 6779 if (ABI == "n32") 6780 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6781 else 6782 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6783 } 6784 public: 6785 Mips64ELTargetInfo(const llvm::Triple &Triple) 6786 : Mips64TargetInfoBase(Triple) { 6787 // Default ABI is n64. 6788 BigEndian = false; 6789 } 6790 void getTargetDefines(const LangOptions &Opts, 6791 MacroBuilder &Builder) const override { 6792 DefineStd(Builder, "MIPSEL", Opts); 6793 Builder.defineMacro("_MIPSEL"); 6794 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6795 } 6796 }; 6797 6798 class PNaClTargetInfo : public TargetInfo { 6799 public: 6800 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6801 BigEndian = false; 6802 this->UserLabelPrefix = ""; 6803 this->LongAlign = 32; 6804 this->LongWidth = 32; 6805 this->PointerAlign = 32; 6806 this->PointerWidth = 32; 6807 this->IntMaxType = TargetInfo::SignedLongLong; 6808 this->Int64Type = TargetInfo::SignedLongLong; 6809 this->DoubleAlign = 64; 6810 this->LongDoubleWidth = 64; 6811 this->LongDoubleAlign = 64; 6812 this->SizeType = TargetInfo::UnsignedInt; 6813 this->PtrDiffType = TargetInfo::SignedInt; 6814 this->IntPtrType = TargetInfo::SignedInt; 6815 this->RegParmMax = 0; // Disallow regparm 6816 } 6817 6818 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6819 Builder.defineMacro("__le32__"); 6820 Builder.defineMacro("__pnacl__"); 6821 } 6822 void getTargetDefines(const LangOptions &Opts, 6823 MacroBuilder &Builder) const override { 6824 getArchDefines(Opts, Builder); 6825 } 6826 bool hasFeature(StringRef Feature) const override { 6827 return Feature == "pnacl"; 6828 } 6829 void getTargetBuiltins(const Builtin::Info *&Records, 6830 unsigned &NumRecords) const override { 6831 } 6832 BuiltinVaListKind getBuiltinVaListKind() const override { 6833 return TargetInfo::PNaClABIBuiltinVaList; 6834 } 6835 void getGCCRegNames(const char * const *&Names, 6836 unsigned &NumNames) const override; 6837 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6838 unsigned &NumAliases) const override; 6839 bool validateAsmConstraint(const char *&Name, 6840 TargetInfo::ConstraintInfo &Info) const override { 6841 return false; 6842 } 6843 6844 const char *getClobbers() const override { 6845 return ""; 6846 } 6847 }; 6848 6849 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6850 unsigned &NumNames) const { 6851 Names = nullptr; 6852 NumNames = 0; 6853 } 6854 6855 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6856 unsigned &NumAliases) const { 6857 Aliases = nullptr; 6858 NumAliases = 0; 6859 } 6860 6861 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6862 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6863 public: 6864 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6865 Mips32ELTargetInfo(Triple) { 6866 } 6867 6868 BuiltinVaListKind getBuiltinVaListKind() const override { 6869 return TargetInfo::PNaClABIBuiltinVaList; 6870 } 6871 }; 6872 6873 class Le64TargetInfo : public TargetInfo { 6874 static const Builtin::Info BuiltinInfo[]; 6875 6876 public: 6877 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6878 BigEndian = false; 6879 NoAsmVariants = true; 6880 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6881 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6882 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6883 } 6884 6885 void getTargetDefines(const LangOptions &Opts, 6886 MacroBuilder &Builder) const override { 6887 DefineStd(Builder, "unix", Opts); 6888 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6889 Builder.defineMacro("__ELF__"); 6890 } 6891 void getTargetBuiltins(const Builtin::Info *&Records, 6892 unsigned &NumRecords) const override { 6893 Records = BuiltinInfo; 6894 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6895 } 6896 BuiltinVaListKind getBuiltinVaListKind() const override { 6897 return TargetInfo::PNaClABIBuiltinVaList; 6898 } 6899 const char *getClobbers() const override { return ""; } 6900 void getGCCRegNames(const char *const *&Names, 6901 unsigned &NumNames) const override { 6902 Names = nullptr; 6903 NumNames = 0; 6904 } 6905 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6906 unsigned &NumAliases) const override { 6907 Aliases = nullptr; 6908 NumAliases = 0; 6909 } 6910 bool validateAsmConstraint(const char *&Name, 6911 TargetInfo::ConstraintInfo &Info) const override { 6912 return false; 6913 } 6914 6915 bool hasProtectedVisibility() const override { return false; } 6916 }; 6917 } // end anonymous namespace. 6918 6919 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6920 #define BUILTIN(ID, TYPE, ATTRS) \ 6921 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6922 #include "clang/Basic/BuiltinsLe64.def" 6923 }; 6924 6925 namespace { 6926 static const unsigned SPIRAddrSpaceMap[] = { 6927 1, // opencl_global 6928 3, // opencl_local 6929 2, // opencl_constant 6930 4, // opencl_generic 6931 0, // cuda_device 6932 0, // cuda_constant 6933 0 // cuda_shared 6934 }; 6935 class SPIRTargetInfo : public TargetInfo { 6936 public: 6937 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6938 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6939 "SPIR target must use unknown OS"); 6940 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6941 "SPIR target must use unknown environment type"); 6942 BigEndian = false; 6943 TLSSupported = false; 6944 LongWidth = LongAlign = 64; 6945 AddrSpaceMap = &SPIRAddrSpaceMap; 6946 UseAddrSpaceMapMangling = true; 6947 // Define available target features 6948 // These must be defined in sorted order! 6949 NoAsmVariants = true; 6950 } 6951 void getTargetDefines(const LangOptions &Opts, 6952 MacroBuilder &Builder) const override { 6953 DefineStd(Builder, "SPIR", Opts); 6954 } 6955 bool hasFeature(StringRef Feature) const override { 6956 return Feature == "spir"; 6957 } 6958 6959 void getTargetBuiltins(const Builtin::Info *&Records, 6960 unsigned &NumRecords) const override {} 6961 const char *getClobbers() const override { 6962 return ""; 6963 } 6964 void getGCCRegNames(const char * const *&Names, 6965 unsigned &NumNames) const override {} 6966 bool 6967 validateAsmConstraint(const char *&Name, 6968 TargetInfo::ConstraintInfo &info) const override { 6969 return true; 6970 } 6971 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6972 unsigned &NumAliases) const override {} 6973 BuiltinVaListKind getBuiltinVaListKind() const override { 6974 return TargetInfo::VoidPtrBuiltinVaList; 6975 } 6976 6977 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6978 return (CC == CC_SpirFunction || 6979 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6980 } 6981 6982 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6983 return CC_SpirFunction; 6984 } 6985 }; 6986 6987 6988 class SPIR32TargetInfo : public SPIRTargetInfo { 6989 public: 6990 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6991 PointerWidth = PointerAlign = 32; 6992 SizeType = TargetInfo::UnsignedInt; 6993 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6994 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6995 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6996 } 6997 void getTargetDefines(const LangOptions &Opts, 6998 MacroBuilder &Builder) const override { 6999 DefineStd(Builder, "SPIR32", Opts); 7000 } 7001 }; 7002 7003 class SPIR64TargetInfo : public SPIRTargetInfo { 7004 public: 7005 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7006 PointerWidth = PointerAlign = 64; 7007 SizeType = TargetInfo::UnsignedLong; 7008 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7009 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7010 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7011 } 7012 void getTargetDefines(const LangOptions &Opts, 7013 MacroBuilder &Builder) const override { 7014 DefineStd(Builder, "SPIR64", Opts); 7015 } 7016 }; 7017 7018 class XCoreTargetInfo : public TargetInfo { 7019 static const Builtin::Info BuiltinInfo[]; 7020 public: 7021 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7022 BigEndian = false; 7023 NoAsmVariants = true; 7024 LongLongAlign = 32; 7025 SuitableAlign = 32; 7026 DoubleAlign = LongDoubleAlign = 32; 7027 SizeType = UnsignedInt; 7028 PtrDiffType = SignedInt; 7029 IntPtrType = SignedInt; 7030 WCharType = UnsignedChar; 7031 WIntType = UnsignedInt; 7032 UseZeroLengthBitfieldAlignment = true; 7033 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7034 "-f64:32-a:0:32-n32"; 7035 } 7036 void getTargetDefines(const LangOptions &Opts, 7037 MacroBuilder &Builder) const override { 7038 Builder.defineMacro("__XS1B__"); 7039 } 7040 void getTargetBuiltins(const Builtin::Info *&Records, 7041 unsigned &NumRecords) const override { 7042 Records = BuiltinInfo; 7043 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7044 } 7045 BuiltinVaListKind getBuiltinVaListKind() const override { 7046 return TargetInfo::VoidPtrBuiltinVaList; 7047 } 7048 const char *getClobbers() const override { 7049 return ""; 7050 } 7051 void getGCCRegNames(const char * const *&Names, 7052 unsigned &NumNames) const override { 7053 static const char * const GCCRegNames[] = { 7054 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7055 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7056 }; 7057 Names = GCCRegNames; 7058 NumNames = llvm::array_lengthof(GCCRegNames); 7059 } 7060 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7061 unsigned &NumAliases) const override { 7062 Aliases = nullptr; 7063 NumAliases = 0; 7064 } 7065 bool validateAsmConstraint(const char *&Name, 7066 TargetInfo::ConstraintInfo &Info) const override { 7067 return false; 7068 } 7069 int getEHDataRegisterNumber(unsigned RegNo) const override { 7070 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7071 return (RegNo < 2)? RegNo : -1; 7072 } 7073 }; 7074 7075 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7076 #define BUILTIN(ID, TYPE, ATTRS) \ 7077 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7078 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7079 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7080 #include "clang/Basic/BuiltinsXCore.def" 7081 }; 7082 } // end anonymous namespace. 7083 7084 namespace { 7085 // x86_32 Android target 7086 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7087 public: 7088 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7089 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7090 SuitableAlign = 32; 7091 LongDoubleWidth = 64; 7092 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7093 } 7094 }; 7095 } // end anonymous namespace 7096 7097 namespace { 7098 // x86_64 Android target 7099 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7100 public: 7101 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7102 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7103 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7104 } 7105 7106 bool useFloat128ManglingForLongDouble() const override { 7107 return true; 7108 } 7109 }; 7110 } // end anonymous namespace 7111 7112 7113 //===----------------------------------------------------------------------===// 7114 // Driver code 7115 //===----------------------------------------------------------------------===// 7116 7117 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7118 llvm::Triple::OSType os = Triple.getOS(); 7119 7120 switch (Triple.getArch()) { 7121 default: 7122 return nullptr; 7123 7124 case llvm::Triple::xcore: 7125 return new XCoreTargetInfo(Triple); 7126 7127 case llvm::Triple::hexagon: 7128 return new HexagonTargetInfo(Triple); 7129 7130 case llvm::Triple::aarch64: 7131 if (Triple.isOSDarwin()) 7132 return new DarwinAArch64TargetInfo(Triple); 7133 7134 switch (os) { 7135 case llvm::Triple::FreeBSD: 7136 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7137 case llvm::Triple::Linux: 7138 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7139 case llvm::Triple::NetBSD: 7140 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7141 default: 7142 return new AArch64leTargetInfo(Triple); 7143 } 7144 7145 case llvm::Triple::aarch64_be: 7146 switch (os) { 7147 case llvm::Triple::FreeBSD: 7148 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7149 case llvm::Triple::Linux: 7150 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7151 case llvm::Triple::NetBSD: 7152 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7153 default: 7154 return new AArch64beTargetInfo(Triple); 7155 } 7156 7157 case llvm::Triple::arm: 7158 case llvm::Triple::thumb: 7159 if (Triple.isOSBinFormatMachO()) 7160 return new DarwinARMTargetInfo(Triple); 7161 7162 switch (os) { 7163 case llvm::Triple::Linux: 7164 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7165 case llvm::Triple::FreeBSD: 7166 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7167 case llvm::Triple::NetBSD: 7168 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7169 case llvm::Triple::OpenBSD: 7170 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7171 case llvm::Triple::Bitrig: 7172 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7173 case llvm::Triple::RTEMS: 7174 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7175 case llvm::Triple::NaCl: 7176 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7177 case llvm::Triple::Win32: 7178 switch (Triple.getEnvironment()) { 7179 case llvm::Triple::Cygnus: 7180 return new CygwinARMTargetInfo(Triple); 7181 case llvm::Triple::GNU: 7182 return new MinGWARMTargetInfo(Triple); 7183 case llvm::Triple::Itanium: 7184 return new ItaniumWindowsARMleTargetInfo(Triple); 7185 case llvm::Triple::MSVC: 7186 default: // Assume MSVC for unknown environments 7187 return new MicrosoftARMleTargetInfo(Triple); 7188 } 7189 default: 7190 return new ARMleTargetInfo(Triple); 7191 } 7192 7193 case llvm::Triple::armeb: 7194 case llvm::Triple::thumbeb: 7195 if (Triple.isOSDarwin()) 7196 return new DarwinARMTargetInfo(Triple); 7197 7198 switch (os) { 7199 case llvm::Triple::Linux: 7200 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7201 case llvm::Triple::FreeBSD: 7202 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7203 case llvm::Triple::NetBSD: 7204 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7205 case llvm::Triple::OpenBSD: 7206 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7207 case llvm::Triple::Bitrig: 7208 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7209 case llvm::Triple::RTEMS: 7210 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7211 case llvm::Triple::NaCl: 7212 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7213 default: 7214 return new ARMbeTargetInfo(Triple); 7215 } 7216 7217 case llvm::Triple::bpfeb: 7218 case llvm::Triple::bpfel: 7219 return new BPFTargetInfo(Triple); 7220 7221 case llvm::Triple::msp430: 7222 return new MSP430TargetInfo(Triple); 7223 7224 case llvm::Triple::mips: 7225 switch (os) { 7226 case llvm::Triple::Linux: 7227 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7228 case llvm::Triple::RTEMS: 7229 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7230 case llvm::Triple::FreeBSD: 7231 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7232 case llvm::Triple::NetBSD: 7233 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7234 default: 7235 return new Mips32EBTargetInfo(Triple); 7236 } 7237 7238 case llvm::Triple::mipsel: 7239 switch (os) { 7240 case llvm::Triple::Linux: 7241 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7242 case llvm::Triple::RTEMS: 7243 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7244 case llvm::Triple::FreeBSD: 7245 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7246 case llvm::Triple::NetBSD: 7247 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7248 case llvm::Triple::NaCl: 7249 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7250 default: 7251 return new Mips32ELTargetInfo(Triple); 7252 } 7253 7254 case llvm::Triple::mips64: 7255 switch (os) { 7256 case llvm::Triple::Linux: 7257 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7258 case llvm::Triple::RTEMS: 7259 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7260 case llvm::Triple::FreeBSD: 7261 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7262 case llvm::Triple::NetBSD: 7263 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7264 case llvm::Triple::OpenBSD: 7265 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7266 default: 7267 return new Mips64EBTargetInfo(Triple); 7268 } 7269 7270 case llvm::Triple::mips64el: 7271 switch (os) { 7272 case llvm::Triple::Linux: 7273 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7274 case llvm::Triple::RTEMS: 7275 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7276 case llvm::Triple::FreeBSD: 7277 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7278 case llvm::Triple::NetBSD: 7279 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7280 case llvm::Triple::OpenBSD: 7281 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7282 default: 7283 return new Mips64ELTargetInfo(Triple); 7284 } 7285 7286 case llvm::Triple::le32: 7287 switch (os) { 7288 case llvm::Triple::NaCl: 7289 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7290 default: 7291 return nullptr; 7292 } 7293 7294 case llvm::Triple::le64: 7295 return new Le64TargetInfo(Triple); 7296 7297 case llvm::Triple::ppc: 7298 if (Triple.isOSDarwin()) 7299 return new DarwinPPC32TargetInfo(Triple); 7300 switch (os) { 7301 case llvm::Triple::Linux: 7302 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7303 case llvm::Triple::FreeBSD: 7304 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7305 case llvm::Triple::NetBSD: 7306 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7307 case llvm::Triple::OpenBSD: 7308 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7309 case llvm::Triple::RTEMS: 7310 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7311 default: 7312 return new PPC32TargetInfo(Triple); 7313 } 7314 7315 case llvm::Triple::ppc64: 7316 if (Triple.isOSDarwin()) 7317 return new DarwinPPC64TargetInfo(Triple); 7318 switch (os) { 7319 case llvm::Triple::Linux: 7320 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7321 case llvm::Triple::Lv2: 7322 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7323 case llvm::Triple::FreeBSD: 7324 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7325 case llvm::Triple::NetBSD: 7326 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7327 default: 7328 return new PPC64TargetInfo(Triple); 7329 } 7330 7331 case llvm::Triple::ppc64le: 7332 switch (os) { 7333 case llvm::Triple::Linux: 7334 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7335 case llvm::Triple::NetBSD: 7336 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7337 default: 7338 return new PPC64TargetInfo(Triple); 7339 } 7340 7341 case llvm::Triple::nvptx: 7342 return new NVPTX32TargetInfo(Triple); 7343 case llvm::Triple::nvptx64: 7344 return new NVPTX64TargetInfo(Triple); 7345 7346 case llvm::Triple::amdgcn: 7347 case llvm::Triple::r600: 7348 return new AMDGPUTargetInfo(Triple); 7349 7350 case llvm::Triple::sparc: 7351 switch (os) { 7352 case llvm::Triple::Linux: 7353 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7354 case llvm::Triple::Solaris: 7355 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7356 case llvm::Triple::NetBSD: 7357 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7358 case llvm::Triple::OpenBSD: 7359 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7360 case llvm::Triple::RTEMS: 7361 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7362 default: 7363 return new SparcV8TargetInfo(Triple); 7364 } 7365 7366 // The 'sparcel' architecture copies all the above cases except for Solaris. 7367 case llvm::Triple::sparcel: 7368 switch (os) { 7369 case llvm::Triple::Linux: 7370 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7371 case llvm::Triple::NetBSD: 7372 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7373 case llvm::Triple::OpenBSD: 7374 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7375 case llvm::Triple::RTEMS: 7376 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7377 default: 7378 return new SparcV8elTargetInfo(Triple); 7379 } 7380 7381 case llvm::Triple::sparcv9: 7382 switch (os) { 7383 case llvm::Triple::Linux: 7384 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7385 case llvm::Triple::Solaris: 7386 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7387 case llvm::Triple::NetBSD: 7388 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7389 case llvm::Triple::OpenBSD: 7390 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7391 case llvm::Triple::FreeBSD: 7392 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7393 default: 7394 return new SparcV9TargetInfo(Triple); 7395 } 7396 7397 case llvm::Triple::systemz: 7398 switch (os) { 7399 case llvm::Triple::Linux: 7400 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7401 default: 7402 return new SystemZTargetInfo(Triple); 7403 } 7404 7405 case llvm::Triple::tce: 7406 return new TCETargetInfo(Triple); 7407 7408 case llvm::Triple::x86: 7409 if (Triple.isOSDarwin()) 7410 return new DarwinI386TargetInfo(Triple); 7411 7412 switch (os) { 7413 case llvm::Triple::CloudABI: 7414 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7415 case llvm::Triple::Linux: { 7416 switch (Triple.getEnvironment()) { 7417 default: 7418 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7419 case llvm::Triple::Android: 7420 return new AndroidX86_32TargetInfo(Triple); 7421 } 7422 } 7423 case llvm::Triple::DragonFly: 7424 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7425 case llvm::Triple::NetBSD: 7426 return new NetBSDI386TargetInfo(Triple); 7427 case llvm::Triple::OpenBSD: 7428 return new OpenBSDI386TargetInfo(Triple); 7429 case llvm::Triple::Bitrig: 7430 return new BitrigI386TargetInfo(Triple); 7431 case llvm::Triple::FreeBSD: 7432 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7433 case llvm::Triple::KFreeBSD: 7434 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7435 case llvm::Triple::Minix: 7436 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7437 case llvm::Triple::Solaris: 7438 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7439 case llvm::Triple::Win32: { 7440 switch (Triple.getEnvironment()) { 7441 case llvm::Triple::Cygnus: 7442 return new CygwinX86_32TargetInfo(Triple); 7443 case llvm::Triple::GNU: 7444 return new MinGWX86_32TargetInfo(Triple); 7445 case llvm::Triple::Itanium: 7446 case llvm::Triple::MSVC: 7447 default: // Assume MSVC for unknown environments 7448 return new MicrosoftX86_32TargetInfo(Triple); 7449 } 7450 } 7451 case llvm::Triple::Haiku: 7452 return new HaikuX86_32TargetInfo(Triple); 7453 case llvm::Triple::RTEMS: 7454 return new RTEMSX86_32TargetInfo(Triple); 7455 case llvm::Triple::NaCl: 7456 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7457 default: 7458 return new X86_32TargetInfo(Triple); 7459 } 7460 7461 case llvm::Triple::x86_64: 7462 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7463 return new DarwinX86_64TargetInfo(Triple); 7464 7465 switch (os) { 7466 case llvm::Triple::CloudABI: 7467 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7468 case llvm::Triple::Linux: { 7469 switch (Triple.getEnvironment()) { 7470 default: 7471 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7472 case llvm::Triple::Android: 7473 return new AndroidX86_64TargetInfo(Triple); 7474 } 7475 } 7476 case llvm::Triple::DragonFly: 7477 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7478 case llvm::Triple::NetBSD: 7479 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7480 case llvm::Triple::OpenBSD: 7481 return new OpenBSDX86_64TargetInfo(Triple); 7482 case llvm::Triple::Bitrig: 7483 return new BitrigX86_64TargetInfo(Triple); 7484 case llvm::Triple::FreeBSD: 7485 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7486 case llvm::Triple::KFreeBSD: 7487 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7488 case llvm::Triple::Solaris: 7489 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7490 case llvm::Triple::Win32: { 7491 switch (Triple.getEnvironment()) { 7492 case llvm::Triple::Cygnus: 7493 return new CygwinX86_64TargetInfo(Triple); 7494 case llvm::Triple::GNU: 7495 return new MinGWX86_64TargetInfo(Triple); 7496 case llvm::Triple::MSVC: 7497 default: // Assume MSVC for unknown environments 7498 return new MicrosoftX86_64TargetInfo(Triple); 7499 } 7500 } 7501 case llvm::Triple::NaCl: 7502 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7503 case llvm::Triple::PS4: 7504 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7505 default: 7506 return new X86_64TargetInfo(Triple); 7507 } 7508 7509 case llvm::Triple::spir: { 7510 if (Triple.getOS() != llvm::Triple::UnknownOS || 7511 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7512 return nullptr; 7513 return new SPIR32TargetInfo(Triple); 7514 } 7515 case llvm::Triple::spir64: { 7516 if (Triple.getOS() != llvm::Triple::UnknownOS || 7517 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7518 return nullptr; 7519 return new SPIR64TargetInfo(Triple); 7520 } 7521 } 7522 } 7523 7524 /// CreateTargetInfo - Return the target info object for the specified target 7525 /// options. 7526 TargetInfo * 7527 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7528 const std::shared_ptr<TargetOptions> &Opts) { 7529 llvm::Triple Triple(Opts->Triple); 7530 7531 // Construct the target 7532 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7533 if (!Target) { 7534 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7535 return nullptr; 7536 } 7537 Target->TargetOpts = Opts; 7538 7539 // Set the target CPU if specified. 7540 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7541 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7542 return nullptr; 7543 } 7544 7545 // Set the target ABI if specified. 7546 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7547 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7548 return nullptr; 7549 } 7550 7551 // Set the fp math unit. 7552 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7553 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7554 return nullptr; 7555 } 7556 7557 // Compute the default target features, we need the target to handle this 7558 // because features may have dependencies on one another. 7559 llvm::StringMap<bool> Features; 7560 Target->initDefaultFeatures(Features); 7561 7562 // Apply the user specified deltas. 7563 for (const auto &F : Opts->FeaturesAsWritten) { 7564 const char *Name = F.c_str(); 7565 // Apply the feature via the target. 7566 bool Enabled = Name[0] == '+'; 7567 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7568 } 7569 7570 // Add the features to the compile options. 7571 // 7572 // FIXME: If we are completely confident that we have the right set, we only 7573 // need to pass the minuses. 7574 Opts->Features.clear(); 7575 for (const auto &F : Features) 7576 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7577 7578 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7579 return nullptr; 7580 7581 return Target.release(); 7582 } 7583