1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.SanitizeAddress) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const std::string& triple) : 183 OSTargetInfo<Target>(triple) { 184 llvm::Triple T = llvm::Triple(triple); 185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 186 this->MCountName = "\01mcount"; 187 } 188 189 virtual std::string isValidSectionSpecifier(StringRef SR) const { 190 // Let MCSectionMachO validate this. 191 StringRef Segment, Section; 192 unsigned TAA, StubSize; 193 bool HasTAA; 194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 195 TAA, HasTAA, StubSize); 196 } 197 198 virtual const char *getStaticInitSectionSpecifier() const { 199 // FIXME: We should return 0 when building kexts. 200 return "__TEXT,__StaticInit,regular,pure_instructions"; 201 } 202 203 /// Darwin does not support protected visibility. Darwin's "default" 204 /// is very similar to ELF's "protected"; Darwin requires a "weak" 205 /// attribute on declarations that can be dynamically replaced. 206 virtual bool hasProtectedVisibility() const { 207 return false; 208 } 209 }; 210 211 212 // DragonFlyBSD Target 213 template<typename Target> 214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const { 218 // DragonFly defines; list based off of gcc output 219 Builder.defineMacro("__DragonFly__"); 220 Builder.defineMacro("__DragonFly_cc_version", "100001"); 221 Builder.defineMacro("__ELF__"); 222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 223 Builder.defineMacro("__tune_i386__"); 224 DefineStd(Builder, "unix", Opts); 225 } 226 public: 227 DragonFlyBSDTargetInfo(const std::string &triple) 228 : OSTargetInfo<Target>(triple) { 229 this->UserLabelPrefix = ""; 230 231 llvm::Triple Triple(triple); 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 } 260 public: 261 FreeBSDTargetInfo(const std::string &triple) 262 : OSTargetInfo<Target>(triple) { 263 this->UserLabelPrefix = ""; 264 265 llvm::Triple Triple(triple); 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 this->MCountName = "_mcount"; 277 break; 278 case llvm::Triple::arm: 279 this->MCountName = "__mcount"; 280 break; 281 } 282 283 } 284 }; 285 286 // Minix Target 287 template<typename Target> 288 class MinixTargetInfo : public OSTargetInfo<Target> { 289 protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // Minix defines 293 294 Builder.defineMacro("__minix", "3"); 295 Builder.defineMacro("_EM_WSIZE", "4"); 296 Builder.defineMacro("_EM_PSIZE", "4"); 297 Builder.defineMacro("_EM_SSIZE", "2"); 298 Builder.defineMacro("_EM_LSIZE", "4"); 299 Builder.defineMacro("_EM_FSIZE", "4"); 300 Builder.defineMacro("_EM_DSIZE", "8"); 301 Builder.defineMacro("__ELF__"); 302 DefineStd(Builder, "unix", Opts); 303 } 304 public: 305 MinixTargetInfo(const std::string &triple) 306 : OSTargetInfo<Target>(triple) { 307 this->UserLabelPrefix = ""; 308 } 309 }; 310 311 // Linux target 312 template<typename Target> 313 class LinuxTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const { 317 // Linux defines; list based off of gcc output 318 DefineStd(Builder, "unix", Opts); 319 DefineStd(Builder, "linux", Opts); 320 Builder.defineMacro("__gnu_linux__"); 321 Builder.defineMacro("__ELF__"); 322 if (Triple.getEnvironment() == llvm::Triple::Android) 323 Builder.defineMacro("__ANDROID__", "1"); 324 if (Opts.POSIXThreads) 325 Builder.defineMacro("_REENTRANT"); 326 if (Opts.CPlusPlus) 327 Builder.defineMacro("_GNU_SOURCE"); 328 } 329 public: 330 LinuxTargetInfo(const std::string& triple) 331 : OSTargetInfo<Target>(triple) { 332 this->UserLabelPrefix = ""; 333 this->WIntType = TargetInfo::UnsignedInt; 334 } 335 336 virtual const char *getStaticInitSectionSpecifier() const { 337 return ".text.startup"; 338 } 339 }; 340 341 // NetBSD Target 342 template<typename Target> 343 class NetBSDTargetInfo : public OSTargetInfo<Target> { 344 protected: 345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 346 MacroBuilder &Builder) const { 347 // NetBSD defines; list based off of gcc output 348 Builder.defineMacro("__NetBSD__"); 349 Builder.defineMacro("__unix__"); 350 Builder.defineMacro("__ELF__"); 351 if (Opts.POSIXThreads) 352 Builder.defineMacro("_POSIX_THREADS"); 353 } 354 public: 355 NetBSDTargetInfo(const std::string &triple) 356 : OSTargetInfo<Target>(triple) { 357 this->UserLabelPrefix = ""; 358 } 359 }; 360 361 // OpenBSD Target 362 template<typename Target> 363 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 364 protected: 365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 366 MacroBuilder &Builder) const { 367 // OpenBSD defines; list based off of gcc output 368 369 Builder.defineMacro("__OpenBSD__"); 370 DefineStd(Builder, "unix", Opts); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_REENTRANT"); 374 } 375 public: 376 OpenBSDTargetInfo(const std::string &triple) 377 : OSTargetInfo<Target>(triple) { 378 this->UserLabelPrefix = ""; 379 this->TLSSupported = false; 380 381 llvm::Triple Triple(triple); 382 switch (Triple.getArch()) { 383 default: 384 case llvm::Triple::x86: 385 case llvm::Triple::x86_64: 386 case llvm::Triple::arm: 387 case llvm::Triple::sparc: 388 this->MCountName = "__mcount"; 389 break; 390 case llvm::Triple::mips64: 391 case llvm::Triple::mips64el: 392 case llvm::Triple::ppc: 393 case llvm::Triple::sparcv9: 394 this->MCountName = "_mcount"; 395 break; 396 } 397 } 398 }; 399 400 // Bitrig Target 401 template<typename Target> 402 class BitrigTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const { 406 // Bitrig defines; list based off of gcc output 407 408 Builder.defineMacro("__Bitrig__"); 409 DefineStd(Builder, "unix", Opts); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 } 414 public: 415 BitrigTargetInfo(const std::string &triple) 416 : OSTargetInfo<Target>(triple) { 417 this->UserLabelPrefix = ""; 418 this->TLSSupported = false; 419 this->MCountName = "__mcount"; 420 } 421 }; 422 423 // PSP Target 424 template<typename Target> 425 class PSPTargetInfo : public OSTargetInfo<Target> { 426 protected: 427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 428 MacroBuilder &Builder) const { 429 // PSP defines; list based on the output of the pspdev gcc toolchain. 430 Builder.defineMacro("PSP"); 431 Builder.defineMacro("_PSP"); 432 Builder.defineMacro("__psp__"); 433 Builder.defineMacro("__ELF__"); 434 } 435 public: 436 PSPTargetInfo(const std::string& triple) 437 : OSTargetInfo<Target>(triple) { 438 this->UserLabelPrefix = ""; 439 } 440 }; 441 442 // PS3 PPU Target 443 template<typename Target> 444 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const { 448 // PS3 PPU defines. 449 Builder.defineMacro("__PPC__"); 450 Builder.defineMacro("__PPU__"); 451 Builder.defineMacro("__CELLOS_LV2__"); 452 Builder.defineMacro("__ELF__"); 453 Builder.defineMacro("__LP32__"); 454 Builder.defineMacro("_ARCH_PPC64"); 455 Builder.defineMacro("__powerpc64__"); 456 } 457 public: 458 PS3PPUTargetInfo(const std::string& triple) 459 : OSTargetInfo<Target>(triple) { 460 this->UserLabelPrefix = ""; 461 this->LongWidth = this->LongAlign = 32; 462 this->PointerWidth = this->PointerAlign = 32; 463 this->IntMaxType = TargetInfo::SignedLongLong; 464 this->UIntMaxType = TargetInfo::UnsignedLongLong; 465 this->Int64Type = TargetInfo::SignedLongLong; 466 this->SizeType = TargetInfo::UnsignedInt; 467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 469 } 470 }; 471 472 // FIXME: Need a real SPU target. 473 // PS3 SPU Target 474 template<typename Target> 475 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 476 protected: 477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 478 MacroBuilder &Builder) const { 479 // PS3 PPU defines. 480 Builder.defineMacro("__SPU__"); 481 Builder.defineMacro("__ELF__"); 482 } 483 public: 484 PS3SPUTargetInfo(const std::string& triple) 485 : OSTargetInfo<Target>(triple) { 486 this->UserLabelPrefix = ""; 487 } 488 }; 489 490 // AuroraUX target 491 template<typename Target> 492 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const { 496 DefineStd(Builder, "sun", Opts); 497 DefineStd(Builder, "unix", Opts); 498 Builder.defineMacro("__ELF__"); 499 Builder.defineMacro("__svr4__"); 500 Builder.defineMacro("__SVR4"); 501 } 502 public: 503 AuroraUXTargetInfo(const std::string& triple) 504 : OSTargetInfo<Target>(triple) { 505 this->UserLabelPrefix = ""; 506 this->WCharType = this->SignedLong; 507 // FIXME: WIntType should be SignedLong 508 } 509 }; 510 511 // Solaris target 512 template<typename Target> 513 class SolarisTargetInfo : public OSTargetInfo<Target> { 514 protected: 515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const { 517 DefineStd(Builder, "sun", Opts); 518 DefineStd(Builder, "unix", Opts); 519 Builder.defineMacro("__ELF__"); 520 Builder.defineMacro("__svr4__"); 521 Builder.defineMacro("__SVR4"); 522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 523 // newer, but to 500 for everything else. feature_test.h has a check to 524 // ensure that you are not using C99 with an old version of X/Open or C89 525 // with a new version. 526 if (Opts.C99 || Opts.C11) 527 Builder.defineMacro("_XOPEN_SOURCE", "600"); 528 else 529 Builder.defineMacro("_XOPEN_SOURCE", "500"); 530 if (Opts.CPlusPlus) 531 Builder.defineMacro("__C99FEATURES__"); 532 Builder.defineMacro("_LARGEFILE_SOURCE"); 533 Builder.defineMacro("_LARGEFILE64_SOURCE"); 534 Builder.defineMacro("__EXTENSIONS__"); 535 Builder.defineMacro("_REENTRANT"); 536 } 537 public: 538 SolarisTargetInfo(const std::string& triple) 539 : OSTargetInfo<Target>(triple) { 540 this->UserLabelPrefix = ""; 541 this->WCharType = this->SignedInt; 542 // FIXME: WIntType should be SignedLong 543 } 544 }; 545 546 // Windows target 547 template<typename Target> 548 class WindowsTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const { 552 Builder.defineMacro("_WIN32"); 553 } 554 void getVisualStudioDefines(const LangOptions &Opts, 555 MacroBuilder &Builder) const { 556 if (Opts.CPlusPlus) { 557 if (Opts.RTTI) 558 Builder.defineMacro("_CPPRTTI"); 559 560 if (Opts.Exceptions) 561 Builder.defineMacro("_CPPUNWIND"); 562 } 563 564 if (!Opts.CharIsSigned) 565 Builder.defineMacro("_CHAR_UNSIGNED"); 566 567 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 568 // but it works for now. 569 if (Opts.POSIXThreads) 570 Builder.defineMacro("_MT"); 571 572 if (Opts.MSCVersion != 0) 573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 574 575 if (Opts.MicrosoftExt) { 576 Builder.defineMacro("_MSC_EXTENSIONS"); 577 578 if (Opts.CPlusPlus11) { 579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 582 } 583 } 584 585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 586 } 587 588 public: 589 WindowsTargetInfo(const std::string &triple) 590 : OSTargetInfo<Target>(triple) {} 591 }; 592 593 template <typename Target> 594 class NaClTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const { 598 if (Opts.POSIXThreads) 599 Builder.defineMacro("_REENTRANT"); 600 if (Opts.CPlusPlus) 601 Builder.defineMacro("_GNU_SOURCE"); 602 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__native_client__"); 606 } 607 public: 608 NaClTargetInfo(const std::string &triple) 609 : OSTargetInfo<Target>(triple) { 610 this->UserLabelPrefix = ""; 611 this->LongAlign = 32; 612 this->LongWidth = 32; 613 this->PointerAlign = 32; 614 this->PointerWidth = 32; 615 this->IntMaxType = TargetInfo::SignedLongLong; 616 this->UIntMaxType = TargetInfo::UnsignedLongLong; 617 this->Int64Type = TargetInfo::SignedLongLong; 618 this->DoubleAlign = 64; 619 this->LongDoubleWidth = 64; 620 this->LongDoubleAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 this->RegParmMax = 2; 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 627 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 628 } 629 virtual typename Target::CallingConvCheckResult checkCallingConvention( 630 CallingConv CC) const { 631 return CC == CC_PnaclCall ? Target::CCCR_OK : 632 Target::checkCallingConvention(CC); 633 } 634 }; 635 } // end anonymous namespace. 636 637 //===----------------------------------------------------------------------===// 638 // Specific target implementations. 639 //===----------------------------------------------------------------------===// 640 641 namespace { 642 // PPC abstract base class 643 class PPCTargetInfo : public TargetInfo { 644 static const Builtin::Info BuiltinInfo[]; 645 static const char * const GCCRegNames[]; 646 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 647 std::string CPU; 648 public: 649 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 650 LongDoubleWidth = LongDoubleAlign = 128; 651 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 652 } 653 654 /// \brief Flags for architecture specific defines. 655 typedef enum { 656 ArchDefineNone = 0, 657 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 658 ArchDefinePpcgr = 1 << 1, 659 ArchDefinePpcsq = 1 << 2, 660 ArchDefine440 = 1 << 3, 661 ArchDefine603 = 1 << 4, 662 ArchDefine604 = 1 << 5, 663 ArchDefinePwr4 = 1 << 6, 664 ArchDefinePwr6 = 1 << 7 665 } ArchDefineTypes; 666 667 virtual bool setCPU(const std::string &Name) { 668 bool CPUKnown = llvm::StringSwitch<bool>(Name) 669 .Case("generic", true) 670 .Case("440", true) 671 .Case("450", true) 672 .Case("601", true) 673 .Case("602", true) 674 .Case("603", true) 675 .Case("603e", true) 676 .Case("603ev", true) 677 .Case("604", true) 678 .Case("604e", true) 679 .Case("620", true) 680 .Case("g3", true) 681 .Case("7400", true) 682 .Case("g4", true) 683 .Case("7450", true) 684 .Case("g4+", true) 685 .Case("750", true) 686 .Case("970", true) 687 .Case("g5", true) 688 .Case("a2", true) 689 .Case("e500mc", true) 690 .Case("e5500", true) 691 .Case("pwr6", true) 692 .Case("pwr7", true) 693 .Case("ppc", true) 694 .Case("ppc64", true) 695 .Default(false); 696 697 if (CPUKnown) 698 CPU = Name; 699 700 return CPUKnown; 701 } 702 703 virtual void getTargetBuiltins(const Builtin::Info *&Records, 704 unsigned &NumRecords) const { 705 Records = BuiltinInfo; 706 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 707 } 708 709 virtual bool isCLZForZeroUndef() const { return false; } 710 711 virtual void getTargetDefines(const LangOptions &Opts, 712 MacroBuilder &Builder) const; 713 714 virtual bool hasFeature(StringRef Feature) const; 715 716 virtual void getGCCRegNames(const char * const *&Names, 717 unsigned &NumNames) const; 718 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 719 unsigned &NumAliases) const; 720 virtual bool validateAsmConstraint(const char *&Name, 721 TargetInfo::ConstraintInfo &Info) const { 722 switch (*Name) { 723 default: return false; 724 case 'O': // Zero 725 break; 726 case 'b': // Base register 727 case 'f': // Floating point register 728 Info.setAllowsRegister(); 729 break; 730 // FIXME: The following are added to allow parsing. 731 // I just took a guess at what the actions should be. 732 // Also, is more specific checking needed? I.e. specific registers? 733 case 'd': // Floating point register (containing 64-bit value) 734 case 'v': // Altivec vector register 735 Info.setAllowsRegister(); 736 break; 737 case 'w': 738 switch (Name[1]) { 739 case 'd':// VSX vector register to hold vector double data 740 case 'f':// VSX vector register to hold vector float data 741 case 's':// VSX vector register to hold scalar float data 742 case 'a':// Any VSX register 743 break; 744 default: 745 return false; 746 } 747 Info.setAllowsRegister(); 748 Name++; // Skip over 'w'. 749 break; 750 case 'h': // `MQ', `CTR', or `LINK' register 751 case 'q': // `MQ' register 752 case 'c': // `CTR' register 753 case 'l': // `LINK' register 754 case 'x': // `CR' register (condition register) number 0 755 case 'y': // `CR' register (condition register) 756 case 'z': // `XER[CA]' carry bit (part of the XER register) 757 Info.setAllowsRegister(); 758 break; 759 case 'I': // Signed 16-bit constant 760 case 'J': // Unsigned 16-bit constant shifted left 16 bits 761 // (use `L' instead for SImode constants) 762 case 'K': // Unsigned 16-bit constant 763 case 'L': // Signed 16-bit constant shifted left 16 bits 764 case 'M': // Constant larger than 31 765 case 'N': // Exact power of 2 766 case 'P': // Constant whose negation is a signed 16-bit constant 767 case 'G': // Floating point constant that can be loaded into a 768 // register with one instruction per word 769 case 'H': // Integer/Floating point constant that can be loaded 770 // into a register using three instructions 771 break; 772 case 'm': // Memory operand. Note that on PowerPC targets, m can 773 // include addresses that update the base register. It 774 // is therefore only safe to use `m' in an asm statement 775 // if that asm statement accesses the operand exactly once. 776 // The asm statement must also use `%U<opno>' as a 777 // placeholder for the "update" flag in the corresponding 778 // load or store instruction. For example: 779 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 780 // is correct but: 781 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 782 // is not. Use es rather than m if you don't want the base 783 // register to be updated. 784 case 'e': 785 if (Name[1] != 's') 786 return false; 787 // es: A "stable" memory operand; that is, one which does not 788 // include any automodification of the base register. Unlike 789 // `m', this constraint can be used in asm statements that 790 // might access the operand several times, or that might not 791 // access it at all. 792 Info.setAllowsMemory(); 793 Name++; // Skip over 'e'. 794 break; 795 case 'Q': // Memory operand that is an offset from a register (it is 796 // usually better to use `m' or `es' in asm statements) 797 case 'Z': // Memory operand that is an indexed or indirect from a 798 // register (it is usually better to use `m' or `es' in 799 // asm statements) 800 Info.setAllowsMemory(); 801 Info.setAllowsRegister(); 802 break; 803 case 'R': // AIX TOC entry 804 case 'a': // Address operand that is an indexed or indirect from a 805 // register (`p' is preferable for asm statements) 806 case 'S': // Constant suitable as a 64-bit mask operand 807 case 'T': // Constant suitable as a 32-bit mask operand 808 case 'U': // System V Release 4 small data area reference 809 case 't': // AND masks that can be performed by two rldic{l, r} 810 // instructions 811 case 'W': // Vector constant that does not require memory 812 case 'j': // Vector constant that is all zeros. 813 break; 814 // End FIXME. 815 } 816 return true; 817 } 818 virtual const char *getClobbers() const { 819 return ""; 820 } 821 }; 822 823 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 824 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 825 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 826 ALL_LANGUAGES }, 827 #include "clang/Basic/BuiltinsPPC.def" 828 }; 829 830 831 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 832 /// #defines that are not tied to a specific subtarget. 833 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 834 MacroBuilder &Builder) const { 835 // Target identification. 836 Builder.defineMacro("__ppc__"); 837 Builder.defineMacro("_ARCH_PPC"); 838 Builder.defineMacro("__powerpc__"); 839 Builder.defineMacro("__POWERPC__"); 840 if (PointerWidth == 64) { 841 Builder.defineMacro("_ARCH_PPC64"); 842 Builder.defineMacro("__powerpc64__"); 843 Builder.defineMacro("__ppc64__"); 844 } else { 845 Builder.defineMacro("__ppc__"); 846 } 847 848 // Target properties. 849 if (getTriple().getOS() != llvm::Triple::NetBSD && 850 getTriple().getOS() != llvm::Triple::OpenBSD) 851 Builder.defineMacro("_BIG_ENDIAN"); 852 Builder.defineMacro("__BIG_ENDIAN__"); 853 854 // Subtarget options. 855 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 856 Builder.defineMacro("__REGISTER_PREFIX__", ""); 857 858 // FIXME: Should be controlled by command line option. 859 Builder.defineMacro("__LONG_DOUBLE_128__"); 860 861 if (Opts.AltiVec) { 862 Builder.defineMacro("__VEC__", "10206"); 863 Builder.defineMacro("__ALTIVEC__"); 864 } 865 866 // CPU identification. 867 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 868 .Case("440", ArchDefineName) 869 .Case("450", ArchDefineName | ArchDefine440) 870 .Case("601", ArchDefineName) 871 .Case("602", ArchDefineName | ArchDefinePpcgr) 872 .Case("603", ArchDefineName | ArchDefinePpcgr) 873 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 874 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 875 .Case("604", ArchDefineName | ArchDefinePpcgr) 876 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 877 .Case("620", ArchDefineName | ArchDefinePpcgr) 878 .Case("7400", ArchDefineName | ArchDefinePpcgr) 879 .Case("7450", ArchDefineName | ArchDefinePpcgr) 880 .Case("750", ArchDefineName | ArchDefinePpcgr) 881 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 882 | ArchDefinePpcsq) 883 .Case("pwr6", ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 884 .Case("pwr7", ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr 885 | ArchDefinePpcsq) 886 .Default(ArchDefineNone); 887 888 if (defs & ArchDefineName) 889 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 890 if (defs & ArchDefinePpcgr) 891 Builder.defineMacro("_ARCH_PPCGR"); 892 if (defs & ArchDefinePpcsq) 893 Builder.defineMacro("_ARCH_PPCSQ"); 894 if (defs & ArchDefine440) 895 Builder.defineMacro("_ARCH_440"); 896 if (defs & ArchDefine603) 897 Builder.defineMacro("_ARCH_603"); 898 if (defs & ArchDefine604) 899 Builder.defineMacro("_ARCH_604"); 900 if (defs & (ArchDefinePwr4 | ArchDefinePwr6)) 901 Builder.defineMacro("_ARCH_PWR4"); 902 if (defs & ArchDefinePwr6) { 903 Builder.defineMacro("_ARCH_PWR5"); 904 Builder.defineMacro("_ARCH_PWR6"); 905 } 906 } 907 908 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 909 return Feature == "powerpc"; 910 } 911 912 913 const char * const PPCTargetInfo::GCCRegNames[] = { 914 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 915 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 916 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 917 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 918 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 919 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 920 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 921 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 922 "mq", "lr", "ctr", "ap", 923 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 924 "xer", 925 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 926 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 927 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 928 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 929 "vrsave", "vscr", 930 "spe_acc", "spefscr", 931 "sfp" 932 }; 933 934 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 935 unsigned &NumNames) const { 936 Names = GCCRegNames; 937 NumNames = llvm::array_lengthof(GCCRegNames); 938 } 939 940 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 941 // While some of these aliases do map to different registers 942 // they still share the same register name. 943 { { "0" }, "r0" }, 944 { { "1"}, "r1" }, 945 { { "2" }, "r2" }, 946 { { "3" }, "r3" }, 947 { { "4" }, "r4" }, 948 { { "5" }, "r5" }, 949 { { "6" }, "r6" }, 950 { { "7" }, "r7" }, 951 { { "8" }, "r8" }, 952 { { "9" }, "r9" }, 953 { { "10" }, "r10" }, 954 { { "11" }, "r11" }, 955 { { "12" }, "r12" }, 956 { { "13" }, "r13" }, 957 { { "14" }, "r14" }, 958 { { "15" }, "r15" }, 959 { { "16" }, "r16" }, 960 { { "17" }, "r17" }, 961 { { "18" }, "r18" }, 962 { { "19" }, "r19" }, 963 { { "20" }, "r20" }, 964 { { "21" }, "r21" }, 965 { { "22" }, "r22" }, 966 { { "23" }, "r23" }, 967 { { "24" }, "r24" }, 968 { { "25" }, "r25" }, 969 { { "26" }, "r26" }, 970 { { "27" }, "r27" }, 971 { { "28" }, "r28" }, 972 { { "29" }, "r29" }, 973 { { "30" }, "r30" }, 974 { { "31" }, "r31" }, 975 { { "fr0" }, "f0" }, 976 { { "fr1" }, "f1" }, 977 { { "fr2" }, "f2" }, 978 { { "fr3" }, "f3" }, 979 { { "fr4" }, "f4" }, 980 { { "fr5" }, "f5" }, 981 { { "fr6" }, "f6" }, 982 { { "fr7" }, "f7" }, 983 { { "fr8" }, "f8" }, 984 { { "fr9" }, "f9" }, 985 { { "fr10" }, "f10" }, 986 { { "fr11" }, "f11" }, 987 { { "fr12" }, "f12" }, 988 { { "fr13" }, "f13" }, 989 { { "fr14" }, "f14" }, 990 { { "fr15" }, "f15" }, 991 { { "fr16" }, "f16" }, 992 { { "fr17" }, "f17" }, 993 { { "fr18" }, "f18" }, 994 { { "fr19" }, "f19" }, 995 { { "fr20" }, "f20" }, 996 { { "fr21" }, "f21" }, 997 { { "fr22" }, "f22" }, 998 { { "fr23" }, "f23" }, 999 { { "fr24" }, "f24" }, 1000 { { "fr25" }, "f25" }, 1001 { { "fr26" }, "f26" }, 1002 { { "fr27" }, "f27" }, 1003 { { "fr28" }, "f28" }, 1004 { { "fr29" }, "f29" }, 1005 { { "fr30" }, "f30" }, 1006 { { "fr31" }, "f31" }, 1007 { { "cc" }, "cr0" }, 1008 }; 1009 1010 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1011 unsigned &NumAliases) const { 1012 Aliases = GCCRegAliases; 1013 NumAliases = llvm::array_lengthof(GCCRegAliases); 1014 } 1015 } // end anonymous namespace. 1016 1017 namespace { 1018 class PPC32TargetInfo : public PPCTargetInfo { 1019 public: 1020 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 1021 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1022 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1023 1024 switch (getTriple().getOS()) { 1025 case llvm::Triple::Linux: 1026 case llvm::Triple::FreeBSD: 1027 case llvm::Triple::NetBSD: 1028 SizeType = UnsignedInt; 1029 PtrDiffType = SignedInt; 1030 IntPtrType = SignedInt; 1031 break; 1032 default: 1033 break; 1034 } 1035 1036 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1037 LongDoubleWidth = LongDoubleAlign = 64; 1038 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1039 } 1040 1041 // PPC32 supports atomics up to 4 bytes. 1042 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1043 } 1044 1045 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1046 // This is the ELF definition, and is overridden by the Darwin sub-target 1047 return TargetInfo::PowerABIBuiltinVaList; 1048 } 1049 }; 1050 } // end anonymous namespace. 1051 1052 namespace { 1053 class PPC64TargetInfo : public PPCTargetInfo { 1054 public: 1055 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 1056 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1057 IntMaxType = SignedLong; 1058 UIntMaxType = UnsignedLong; 1059 Int64Type = SignedLong; 1060 1061 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1062 LongDoubleWidth = LongDoubleAlign = 64; 1063 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1064 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1065 "i64:64:64-f32:32:32-f64:64:64-f128:64:64-" 1066 "v128:128:128-n32:64"; 1067 } else 1068 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1069 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1070 "v128:128:128-n32:64"; 1071 1072 // PPC64 supports atomics up to 8 bytes. 1073 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1074 } 1075 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1076 return TargetInfo::CharPtrBuiltinVaList; 1077 } 1078 }; 1079 } // end anonymous namespace. 1080 1081 1082 namespace { 1083 class DarwinPPC32TargetInfo : 1084 public DarwinTargetInfo<PPC32TargetInfo> { 1085 public: 1086 DarwinPPC32TargetInfo(const std::string& triple) 1087 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 1088 HasAlignMac68kSupport = true; 1089 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1090 LongLongAlign = 32; 1091 SuitableAlign = 128; 1092 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1093 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1094 } 1095 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1096 return TargetInfo::CharPtrBuiltinVaList; 1097 } 1098 }; 1099 1100 class DarwinPPC64TargetInfo : 1101 public DarwinTargetInfo<PPC64TargetInfo> { 1102 public: 1103 DarwinPPC64TargetInfo(const std::string& triple) 1104 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 1105 HasAlignMac68kSupport = true; 1106 SuitableAlign = 128; 1107 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1108 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1109 } 1110 }; 1111 } // end anonymous namespace. 1112 1113 namespace { 1114 static const unsigned NVPTXAddrSpaceMap[] = { 1115 1, // opencl_global 1116 3, // opencl_local 1117 4, // opencl_constant 1118 1, // cuda_device 1119 4, // cuda_constant 1120 3, // cuda_shared 1121 }; 1122 class NVPTXTargetInfo : public TargetInfo { 1123 static const char * const GCCRegNames[]; 1124 static const Builtin::Info BuiltinInfo[]; 1125 std::vector<llvm::StringRef> AvailableFeatures; 1126 public: 1127 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1128 BigEndian = false; 1129 TLSSupported = false; 1130 LongWidth = LongAlign = 64; 1131 AddrSpaceMap = &NVPTXAddrSpaceMap; 1132 // Define available target features 1133 // These must be defined in sorted order! 1134 NoAsmVariants = true; 1135 } 1136 virtual void getTargetDefines(const LangOptions &Opts, 1137 MacroBuilder &Builder) const { 1138 Builder.defineMacro("__PTX__"); 1139 Builder.defineMacro("__NVPTX__"); 1140 } 1141 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1142 unsigned &NumRecords) const { 1143 Records = BuiltinInfo; 1144 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1145 } 1146 virtual bool hasFeature(StringRef Feature) const { 1147 return Feature == "ptx" || Feature == "nvptx"; 1148 } 1149 1150 virtual void getGCCRegNames(const char * const *&Names, 1151 unsigned &NumNames) const; 1152 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1153 unsigned &NumAliases) const { 1154 // No aliases. 1155 Aliases = 0; 1156 NumAliases = 0; 1157 } 1158 virtual bool validateAsmConstraint(const char *&Name, 1159 TargetInfo::ConstraintInfo &info) const { 1160 // FIXME: implement 1161 return true; 1162 } 1163 virtual const char *getClobbers() const { 1164 // FIXME: Is this really right? 1165 return ""; 1166 } 1167 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1168 // FIXME: implement 1169 return TargetInfo::CharPtrBuiltinVaList; 1170 } 1171 virtual bool setCPU(const std::string &Name) { 1172 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1173 } 1174 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1175 StringRef Name, 1176 bool Enabled) const; 1177 }; 1178 1179 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1180 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1181 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1182 ALL_LANGUAGES }, 1183 #include "clang/Basic/BuiltinsNVPTX.def" 1184 }; 1185 1186 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1187 "r0" 1188 }; 1189 1190 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1191 unsigned &NumNames) const { 1192 Names = GCCRegNames; 1193 NumNames = llvm::array_lengthof(GCCRegNames); 1194 } 1195 1196 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1197 StringRef Name, 1198 bool Enabled) const { 1199 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1200 Name)) { 1201 Features[Name] = Enabled; 1202 return true; 1203 } else { 1204 return false; 1205 } 1206 } 1207 1208 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1209 public: 1210 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1211 PointerWidth = PointerAlign = 32; 1212 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1213 DescriptionString 1214 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1215 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1216 "n16:32:64"; 1217 } 1218 }; 1219 1220 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1221 public: 1222 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1223 PointerWidth = PointerAlign = 64; 1224 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1225 DescriptionString 1226 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1227 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1228 "n16:32:64"; 1229 } 1230 }; 1231 } 1232 1233 namespace { 1234 1235 static const unsigned R600AddrSpaceMap[] = { 1236 1, // opencl_global 1237 3, // opencl_local 1238 2, // opencl_constant 1239 1, // cuda_device 1240 2, // cuda_constant 1241 3 // cuda_shared 1242 }; 1243 1244 class R600TargetInfo : public TargetInfo { 1245 public: 1246 R600TargetInfo(const std::string& triple) : TargetInfo(triple) { 1247 DescriptionString = 1248 "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16" 1249 "-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:32:32" 1250 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64" 1251 "-v96:128:128-v128:128:128-v192:256:256-v256:256:256" 1252 "-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1253 "-n8:16:32:64"; 1254 AddrSpaceMap = &R600AddrSpaceMap; 1255 } 1256 1257 virtual const char * getClobbers() const { 1258 return ""; 1259 } 1260 1261 virtual void getGCCRegNames(const char * const *&Names, 1262 unsigned &numNames) const { 1263 Names = NULL; 1264 numNames = 0; 1265 } 1266 1267 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1268 unsigned &NumAliases) const { 1269 Aliases = NULL; 1270 NumAliases = 0; 1271 } 1272 1273 virtual bool validateAsmConstraint(const char *&Name, 1274 TargetInfo::ConstraintInfo &info) const { 1275 return true; 1276 } 1277 1278 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1279 unsigned &NumRecords) const { 1280 Records = NULL; 1281 NumRecords = 0; 1282 } 1283 1284 1285 virtual void getTargetDefines(const LangOptions &Opts, 1286 MacroBuilder &Builder) const { 1287 Builder.defineMacro("__R600__"); 1288 } 1289 1290 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1291 return TargetInfo::CharPtrBuiltinVaList; 1292 } 1293 1294 }; 1295 1296 } // end anonymous namespace 1297 1298 namespace { 1299 // MBlaze abstract base class 1300 class MBlazeTargetInfo : public TargetInfo { 1301 static const char * const GCCRegNames[]; 1302 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1303 1304 public: 1305 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1306 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1307 } 1308 1309 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1310 unsigned &NumRecords) const { 1311 // FIXME: Implement. 1312 Records = 0; 1313 NumRecords = 0; 1314 } 1315 1316 virtual void getTargetDefines(const LangOptions &Opts, 1317 MacroBuilder &Builder) const; 1318 1319 virtual bool hasFeature(StringRef Feature) const { 1320 return Feature == "mblaze"; 1321 } 1322 1323 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1324 return TargetInfo::CharPtrBuiltinVaList; 1325 } 1326 virtual const char *getTargetPrefix() const { 1327 return "mblaze"; 1328 } 1329 virtual void getGCCRegNames(const char * const *&Names, 1330 unsigned &NumNames) const; 1331 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1332 unsigned &NumAliases) const; 1333 virtual bool validateAsmConstraint(const char *&Name, 1334 TargetInfo::ConstraintInfo &Info) const { 1335 switch (*Name) { 1336 default: return false; 1337 case 'O': // Zero 1338 return true; 1339 case 'b': // Base register 1340 case 'f': // Floating point register 1341 Info.setAllowsRegister(); 1342 return true; 1343 } 1344 } 1345 virtual const char *getClobbers() const { 1346 return ""; 1347 } 1348 }; 1349 1350 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1351 /// #defines that are not tied to a specific subtarget. 1352 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1353 MacroBuilder &Builder) const { 1354 // Target identification. 1355 Builder.defineMacro("__microblaze__"); 1356 Builder.defineMacro("_ARCH_MICROBLAZE"); 1357 Builder.defineMacro("__MICROBLAZE__"); 1358 1359 // Target properties. 1360 Builder.defineMacro("_BIG_ENDIAN"); 1361 Builder.defineMacro("__BIG_ENDIAN__"); 1362 1363 // Subtarget options. 1364 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1365 } 1366 1367 1368 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1369 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1370 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1371 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1372 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1373 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1374 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1375 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1376 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1377 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1378 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1379 }; 1380 1381 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1382 unsigned &NumNames) const { 1383 Names = GCCRegNames; 1384 NumNames = llvm::array_lengthof(GCCRegNames); 1385 } 1386 1387 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1388 { {"f0"}, "r0" }, 1389 { {"f1"}, "r1" }, 1390 { {"f2"}, "r2" }, 1391 { {"f3"}, "r3" }, 1392 { {"f4"}, "r4" }, 1393 { {"f5"}, "r5" }, 1394 { {"f6"}, "r6" }, 1395 { {"f7"}, "r7" }, 1396 { {"f8"}, "r8" }, 1397 { {"f9"}, "r9" }, 1398 { {"f10"}, "r10" }, 1399 { {"f11"}, "r11" }, 1400 { {"f12"}, "r12" }, 1401 { {"f13"}, "r13" }, 1402 { {"f14"}, "r14" }, 1403 { {"f15"}, "r15" }, 1404 { {"f16"}, "r16" }, 1405 { {"f17"}, "r17" }, 1406 { {"f18"}, "r18" }, 1407 { {"f19"}, "r19" }, 1408 { {"f20"}, "r20" }, 1409 { {"f21"}, "r21" }, 1410 { {"f22"}, "r22" }, 1411 { {"f23"}, "r23" }, 1412 { {"f24"}, "r24" }, 1413 { {"f25"}, "r25" }, 1414 { {"f26"}, "r26" }, 1415 { {"f27"}, "r27" }, 1416 { {"f28"}, "r28" }, 1417 { {"f29"}, "r29" }, 1418 { {"f30"}, "r30" }, 1419 { {"f31"}, "r31" }, 1420 }; 1421 1422 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1423 unsigned &NumAliases) const { 1424 Aliases = GCCRegAliases; 1425 NumAliases = llvm::array_lengthof(GCCRegAliases); 1426 } 1427 } // end anonymous namespace. 1428 1429 namespace { 1430 // Namespace for x86 abstract base class 1431 const Builtin::Info BuiltinInfo[] = { 1432 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1433 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1434 ALL_LANGUAGES }, 1435 #include "clang/Basic/BuiltinsX86.def" 1436 }; 1437 1438 static const char* const GCCRegNames[] = { 1439 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1440 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1441 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1442 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1443 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1444 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1445 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1446 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1447 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1448 }; 1449 1450 const TargetInfo::AddlRegName AddlRegNames[] = { 1451 { { "al", "ah", "eax", "rax" }, 0 }, 1452 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1453 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1454 { { "dl", "dh", "edx", "rdx" }, 1 }, 1455 { { "esi", "rsi" }, 4 }, 1456 { { "edi", "rdi" }, 5 }, 1457 { { "esp", "rsp" }, 7 }, 1458 { { "ebp", "rbp" }, 6 }, 1459 }; 1460 1461 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1462 // most of the implementation can be shared. 1463 class X86TargetInfo : public TargetInfo { 1464 enum X86SSEEnum { 1465 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1466 } SSELevel; 1467 enum MMX3DNowEnum { 1468 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1469 } MMX3DNowLevel; 1470 1471 bool HasAES; 1472 bool HasPCLMUL; 1473 bool HasLZCNT; 1474 bool HasRDRND; 1475 bool HasBMI; 1476 bool HasBMI2; 1477 bool HasPOPCNT; 1478 bool HasRTM; 1479 bool HasSSE4a; 1480 bool HasFMA4; 1481 bool HasFMA; 1482 bool HasXOP; 1483 bool HasF16C; 1484 1485 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1486 /// 1487 /// Each enumeration represents a particular CPU supported by Clang. These 1488 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1489 enum CPUKind { 1490 CK_Generic, 1491 1492 /// \name i386 1493 /// i386-generation processors. 1494 //@{ 1495 CK_i386, 1496 //@} 1497 1498 /// \name i486 1499 /// i486-generation processors. 1500 //@{ 1501 CK_i486, 1502 CK_WinChipC6, 1503 CK_WinChip2, 1504 CK_C3, 1505 //@} 1506 1507 /// \name i586 1508 /// i586-generation processors, P5 microarchitecture based. 1509 //@{ 1510 CK_i586, 1511 CK_Pentium, 1512 CK_PentiumMMX, 1513 //@} 1514 1515 /// \name i686 1516 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1517 //@{ 1518 CK_i686, 1519 CK_PentiumPro, 1520 CK_Pentium2, 1521 CK_Pentium3, 1522 CK_Pentium3M, 1523 CK_PentiumM, 1524 CK_C3_2, 1525 1526 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1527 /// Clang however has some logic to suport this. 1528 // FIXME: Warn, deprecate, and potentially remove this. 1529 CK_Yonah, 1530 //@} 1531 1532 /// \name Netburst 1533 /// Netburst microarchitecture based processors. 1534 //@{ 1535 CK_Pentium4, 1536 CK_Pentium4M, 1537 CK_Prescott, 1538 CK_Nocona, 1539 //@} 1540 1541 /// \name Core 1542 /// Core microarchitecture based processors. 1543 //@{ 1544 CK_Core2, 1545 1546 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1547 /// codename which GCC no longer accepts as an option to -march, but Clang 1548 /// has some logic for recognizing it. 1549 // FIXME: Warn, deprecate, and potentially remove this. 1550 CK_Penryn, 1551 //@} 1552 1553 /// \name Atom 1554 /// Atom processors 1555 //@{ 1556 CK_Atom, 1557 //@} 1558 1559 /// \name Nehalem 1560 /// Nehalem microarchitecture based processors. 1561 //@{ 1562 CK_Corei7, 1563 CK_Corei7AVX, 1564 CK_CoreAVXi, 1565 CK_CoreAVX2, 1566 //@} 1567 1568 /// \name K6 1569 /// K6 architecture processors. 1570 //@{ 1571 CK_K6, 1572 CK_K6_2, 1573 CK_K6_3, 1574 //@} 1575 1576 /// \name K7 1577 /// K7 architecture processors. 1578 //@{ 1579 CK_Athlon, 1580 CK_AthlonThunderbird, 1581 CK_Athlon4, 1582 CK_AthlonXP, 1583 CK_AthlonMP, 1584 //@} 1585 1586 /// \name K8 1587 /// K8 architecture processors. 1588 //@{ 1589 CK_Athlon64, 1590 CK_Athlon64SSE3, 1591 CK_AthlonFX, 1592 CK_K8, 1593 CK_K8SSE3, 1594 CK_Opteron, 1595 CK_OpteronSSE3, 1596 CK_AMDFAM10, 1597 //@} 1598 1599 /// \name Bobcat 1600 /// Bobcat architecture processors. 1601 //@{ 1602 CK_BTVER1, 1603 //@} 1604 1605 /// \name Bulldozer 1606 /// Bulldozer architecture processors. 1607 //@{ 1608 CK_BDVER1, 1609 CK_BDVER2, 1610 //@} 1611 1612 /// This specification is deprecated and will be removed in the future. 1613 /// Users should prefer \see CK_K8. 1614 // FIXME: Warn on this when the CPU is set to it. 1615 CK_x86_64, 1616 //@} 1617 1618 /// \name Geode 1619 /// Geode processors. 1620 //@{ 1621 CK_Geode 1622 //@} 1623 } CPU; 1624 1625 public: 1626 X86TargetInfo(const std::string& triple) 1627 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1628 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1629 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasRTM(false), 1630 HasSSE4a(false), HasFMA4(false), HasFMA(false), HasXOP(false), 1631 HasF16C(false), CPU(CK_Generic) { 1632 BigEndian = false; 1633 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1634 } 1635 virtual unsigned getFloatEvalMethod() const { 1636 // X87 evaluates with 80 bits "long double" precision. 1637 return SSELevel == NoSSE ? 2 : 0; 1638 } 1639 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1640 unsigned &NumRecords) const { 1641 Records = BuiltinInfo; 1642 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1643 } 1644 virtual void getGCCRegNames(const char * const *&Names, 1645 unsigned &NumNames) const { 1646 Names = GCCRegNames; 1647 NumNames = llvm::array_lengthof(GCCRegNames); 1648 } 1649 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1650 unsigned &NumAliases) const { 1651 Aliases = 0; 1652 NumAliases = 0; 1653 } 1654 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1655 unsigned &NumNames) const { 1656 Names = AddlRegNames; 1657 NumNames = llvm::array_lengthof(AddlRegNames); 1658 } 1659 virtual bool validateAsmConstraint(const char *&Name, 1660 TargetInfo::ConstraintInfo &info) const; 1661 virtual std::string convertConstraint(const char *&Constraint) const; 1662 virtual const char *getClobbers() const { 1663 return "~{dirflag},~{fpsr},~{flags}"; 1664 } 1665 virtual void getTargetDefines(const LangOptions &Opts, 1666 MacroBuilder &Builder) const; 1667 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1668 StringRef Name, 1669 bool Enabled) const; 1670 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1671 virtual bool hasFeature(StringRef Feature) const; 1672 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1673 virtual const char* getABI() const { 1674 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1675 return "avx"; 1676 else if (getTriple().getArch() == llvm::Triple::x86 && 1677 MMX3DNowLevel == NoMMX3DNow) 1678 return "no-mmx"; 1679 return ""; 1680 } 1681 virtual bool setCPU(const std::string &Name) { 1682 CPU = llvm::StringSwitch<CPUKind>(Name) 1683 .Case("i386", CK_i386) 1684 .Case("i486", CK_i486) 1685 .Case("winchip-c6", CK_WinChipC6) 1686 .Case("winchip2", CK_WinChip2) 1687 .Case("c3", CK_C3) 1688 .Case("i586", CK_i586) 1689 .Case("pentium", CK_Pentium) 1690 .Case("pentium-mmx", CK_PentiumMMX) 1691 .Case("i686", CK_i686) 1692 .Case("pentiumpro", CK_PentiumPro) 1693 .Case("pentium2", CK_Pentium2) 1694 .Case("pentium3", CK_Pentium3) 1695 .Case("pentium3m", CK_Pentium3M) 1696 .Case("pentium-m", CK_PentiumM) 1697 .Case("c3-2", CK_C3_2) 1698 .Case("yonah", CK_Yonah) 1699 .Case("pentium4", CK_Pentium4) 1700 .Case("pentium4m", CK_Pentium4M) 1701 .Case("prescott", CK_Prescott) 1702 .Case("nocona", CK_Nocona) 1703 .Case("core2", CK_Core2) 1704 .Case("penryn", CK_Penryn) 1705 .Case("atom", CK_Atom) 1706 .Case("corei7", CK_Corei7) 1707 .Case("corei7-avx", CK_Corei7AVX) 1708 .Case("core-avx-i", CK_CoreAVXi) 1709 .Case("core-avx2", CK_CoreAVX2) 1710 .Case("k6", CK_K6) 1711 .Case("k6-2", CK_K6_2) 1712 .Case("k6-3", CK_K6_3) 1713 .Case("athlon", CK_Athlon) 1714 .Case("athlon-tbird", CK_AthlonThunderbird) 1715 .Case("athlon-4", CK_Athlon4) 1716 .Case("athlon-xp", CK_AthlonXP) 1717 .Case("athlon-mp", CK_AthlonMP) 1718 .Case("athlon64", CK_Athlon64) 1719 .Case("athlon64-sse3", CK_Athlon64SSE3) 1720 .Case("athlon-fx", CK_AthlonFX) 1721 .Case("k8", CK_K8) 1722 .Case("k8-sse3", CK_K8SSE3) 1723 .Case("opteron", CK_Opteron) 1724 .Case("opteron-sse3", CK_OpteronSSE3) 1725 .Case("amdfam10", CK_AMDFAM10) 1726 .Case("btver1", CK_BTVER1) 1727 .Case("bdver1", CK_BDVER1) 1728 .Case("bdver2", CK_BDVER2) 1729 .Case("x86-64", CK_x86_64) 1730 .Case("geode", CK_Geode) 1731 .Default(CK_Generic); 1732 1733 // Perform any per-CPU checks necessary to determine if this CPU is 1734 // acceptable. 1735 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1736 // invalid without explaining *why*. 1737 switch (CPU) { 1738 case CK_Generic: 1739 // No processor selected! 1740 return false; 1741 1742 case CK_i386: 1743 case CK_i486: 1744 case CK_WinChipC6: 1745 case CK_WinChip2: 1746 case CK_C3: 1747 case CK_i586: 1748 case CK_Pentium: 1749 case CK_PentiumMMX: 1750 case CK_i686: 1751 case CK_PentiumPro: 1752 case CK_Pentium2: 1753 case CK_Pentium3: 1754 case CK_Pentium3M: 1755 case CK_PentiumM: 1756 case CK_Yonah: 1757 case CK_C3_2: 1758 case CK_Pentium4: 1759 case CK_Pentium4M: 1760 case CK_Prescott: 1761 case CK_K6: 1762 case CK_K6_2: 1763 case CK_K6_3: 1764 case CK_Athlon: 1765 case CK_AthlonThunderbird: 1766 case CK_Athlon4: 1767 case CK_AthlonXP: 1768 case CK_AthlonMP: 1769 case CK_Geode: 1770 // Only accept certain architectures when compiling in 32-bit mode. 1771 if (getTriple().getArch() != llvm::Triple::x86) 1772 return false; 1773 1774 // Fallthrough 1775 case CK_Nocona: 1776 case CK_Core2: 1777 case CK_Penryn: 1778 case CK_Atom: 1779 case CK_Corei7: 1780 case CK_Corei7AVX: 1781 case CK_CoreAVXi: 1782 case CK_CoreAVX2: 1783 case CK_Athlon64: 1784 case CK_Athlon64SSE3: 1785 case CK_AthlonFX: 1786 case CK_K8: 1787 case CK_K8SSE3: 1788 case CK_Opteron: 1789 case CK_OpteronSSE3: 1790 case CK_AMDFAM10: 1791 case CK_BTVER1: 1792 case CK_BDVER1: 1793 case CK_BDVER2: 1794 case CK_x86_64: 1795 return true; 1796 } 1797 llvm_unreachable("Unhandled CPU kind"); 1798 } 1799 1800 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1801 // We accept all non-ARM calling conventions 1802 return (CC == CC_X86ThisCall || 1803 CC == CC_X86FastCall || 1804 CC == CC_X86StdCall || 1805 CC == CC_C || 1806 CC == CC_X86Pascal || 1807 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1808 } 1809 1810 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1811 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1812 } 1813 }; 1814 1815 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1816 // FIXME: This should not be here. 1817 Features["3dnow"] = false; 1818 Features["3dnowa"] = false; 1819 Features["mmx"] = false; 1820 Features["sse"] = false; 1821 Features["sse2"] = false; 1822 Features["sse3"] = false; 1823 Features["ssse3"] = false; 1824 Features["sse41"] = false; 1825 Features["sse42"] = false; 1826 Features["sse4a"] = false; 1827 Features["aes"] = false; 1828 Features["pclmul"] = false; 1829 Features["avx"] = false; 1830 Features["avx2"] = false; 1831 Features["lzcnt"] = false; 1832 Features["rdrand"] = false; 1833 Features["bmi"] = false; 1834 Features["bmi2"] = false; 1835 Features["popcnt"] = false; 1836 Features["rtm"] = false; 1837 Features["fma4"] = false; 1838 Features["fma"] = false; 1839 Features["xop"] = false; 1840 Features["f16c"] = false; 1841 1842 // FIXME: This *really* should not be here. 1843 1844 // X86_64 always has SSE2. 1845 if (getTriple().getArch() == llvm::Triple::x86_64) 1846 setFeatureEnabled(Features, "sse2", true); 1847 1848 switch (CPU) { 1849 case CK_Generic: 1850 case CK_i386: 1851 case CK_i486: 1852 case CK_i586: 1853 case CK_Pentium: 1854 case CK_i686: 1855 case CK_PentiumPro: 1856 break; 1857 case CK_PentiumMMX: 1858 case CK_Pentium2: 1859 setFeatureEnabled(Features, "mmx", true); 1860 break; 1861 case CK_Pentium3: 1862 case CK_Pentium3M: 1863 setFeatureEnabled(Features, "sse", true); 1864 break; 1865 case CK_PentiumM: 1866 case CK_Pentium4: 1867 case CK_Pentium4M: 1868 case CK_x86_64: 1869 setFeatureEnabled(Features, "sse2", true); 1870 break; 1871 case CK_Yonah: 1872 case CK_Prescott: 1873 case CK_Nocona: 1874 setFeatureEnabled(Features, "sse3", true); 1875 break; 1876 case CK_Core2: 1877 setFeatureEnabled(Features, "ssse3", true); 1878 break; 1879 case CK_Penryn: 1880 setFeatureEnabled(Features, "sse4.1", true); 1881 break; 1882 case CK_Atom: 1883 setFeatureEnabled(Features, "ssse3", true); 1884 break; 1885 case CK_Corei7: 1886 setFeatureEnabled(Features, "sse4", true); 1887 break; 1888 case CK_Corei7AVX: 1889 setFeatureEnabled(Features, "avx", true); 1890 setFeatureEnabled(Features, "aes", true); 1891 setFeatureEnabled(Features, "pclmul", true); 1892 break; 1893 case CK_CoreAVXi: 1894 setFeatureEnabled(Features, "avx", true); 1895 setFeatureEnabled(Features, "aes", true); 1896 setFeatureEnabled(Features, "pclmul", true); 1897 setFeatureEnabled(Features, "rdrnd", true); 1898 setFeatureEnabled(Features, "f16c", true); 1899 break; 1900 case CK_CoreAVX2: 1901 setFeatureEnabled(Features, "avx2", true); 1902 setFeatureEnabled(Features, "aes", true); 1903 setFeatureEnabled(Features, "pclmul", true); 1904 setFeatureEnabled(Features, "lzcnt", true); 1905 setFeatureEnabled(Features, "rdrnd", true); 1906 setFeatureEnabled(Features, "f16c", true); 1907 setFeatureEnabled(Features, "bmi", true); 1908 setFeatureEnabled(Features, "bmi2", true); 1909 setFeatureEnabled(Features, "rtm", true); 1910 setFeatureEnabled(Features, "fma", true); 1911 break; 1912 case CK_K6: 1913 case CK_WinChipC6: 1914 setFeatureEnabled(Features, "mmx", true); 1915 break; 1916 case CK_K6_2: 1917 case CK_K6_3: 1918 case CK_WinChip2: 1919 case CK_C3: 1920 setFeatureEnabled(Features, "3dnow", true); 1921 break; 1922 case CK_Athlon: 1923 case CK_AthlonThunderbird: 1924 case CK_Geode: 1925 setFeatureEnabled(Features, "3dnowa", true); 1926 break; 1927 case CK_Athlon4: 1928 case CK_AthlonXP: 1929 case CK_AthlonMP: 1930 setFeatureEnabled(Features, "sse", true); 1931 setFeatureEnabled(Features, "3dnowa", true); 1932 break; 1933 case CK_K8: 1934 case CK_Opteron: 1935 case CK_Athlon64: 1936 case CK_AthlonFX: 1937 setFeatureEnabled(Features, "sse2", true); 1938 setFeatureEnabled(Features, "3dnowa", true); 1939 break; 1940 case CK_K8SSE3: 1941 case CK_OpteronSSE3: 1942 case CK_Athlon64SSE3: 1943 setFeatureEnabled(Features, "sse3", true); 1944 setFeatureEnabled(Features, "3dnowa", true); 1945 break; 1946 case CK_AMDFAM10: 1947 setFeatureEnabled(Features, "sse3", true); 1948 setFeatureEnabled(Features, "sse4a", true); 1949 setFeatureEnabled(Features, "3dnowa", true); 1950 setFeatureEnabled(Features, "lzcnt", true); 1951 setFeatureEnabled(Features, "popcnt", true); 1952 break; 1953 case CK_BTVER1: 1954 setFeatureEnabled(Features, "ssse3", true); 1955 setFeatureEnabled(Features, "sse4a", true); 1956 setFeatureEnabled(Features, "lzcnt", true); 1957 setFeatureEnabled(Features, "popcnt", true); 1958 break; 1959 case CK_BDVER1: 1960 setFeatureEnabled(Features, "xop", true); 1961 setFeatureEnabled(Features, "lzcnt", true); 1962 setFeatureEnabled(Features, "aes", true); 1963 setFeatureEnabled(Features, "pclmul", true); 1964 break; 1965 case CK_BDVER2: 1966 setFeatureEnabled(Features, "xop", true); 1967 setFeatureEnabled(Features, "lzcnt", true); 1968 setFeatureEnabled(Features, "aes", true); 1969 setFeatureEnabled(Features, "pclmul", true); 1970 setFeatureEnabled(Features, "bmi", true); 1971 setFeatureEnabled(Features, "fma", true); 1972 setFeatureEnabled(Features, "f16c", true); 1973 break; 1974 case CK_C3_2: 1975 setFeatureEnabled(Features, "sse", true); 1976 break; 1977 } 1978 } 1979 1980 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1981 StringRef Name, 1982 bool Enabled) const { 1983 // FIXME: This *really* should not be here. We need some way of translating 1984 // options into llvm subtarget features. 1985 if (!Features.count(Name) && 1986 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 1987 Name != "rdrnd")) 1988 return false; 1989 1990 // FIXME: this should probably use a switch with fall through. 1991 1992 if (Enabled) { 1993 if (Name == "mmx") 1994 Features["mmx"] = true; 1995 else if (Name == "sse") 1996 Features["mmx"] = Features["sse"] = true; 1997 else if (Name == "sse2") 1998 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1999 else if (Name == "sse3") 2000 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2001 true; 2002 else if (Name == "ssse3") 2003 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2004 Features["ssse3"] = true; 2005 else if (Name == "sse4" || Name == "sse4.2") 2006 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2007 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2008 Features["popcnt"] = true; 2009 else if (Name == "sse4.1") 2010 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2011 Features["ssse3"] = Features["sse41"] = true; 2012 else if (Name == "3dnow") 2013 Features["mmx"] = Features["3dnow"] = true; 2014 else if (Name == "3dnowa") 2015 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 2016 else if (Name == "aes") 2017 Features["sse"] = Features["sse2"] = Features["aes"] = true; 2018 else if (Name == "pclmul") 2019 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 2020 else if (Name == "avx") 2021 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2022 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2023 Features["popcnt"] = Features["avx"] = true; 2024 else if (Name == "avx2") 2025 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2026 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2027 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 2028 else if (Name == "fma") 2029 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2030 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2031 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 2032 else if (Name == "fma4") 2033 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2034 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2035 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2036 Features["fma4"] = true; 2037 else if (Name == "xop") 2038 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2039 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2040 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 2041 Features["fma4"] = Features["xop"] = true; 2042 else if (Name == "sse4a") 2043 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 2044 Features["sse4a"] = true; 2045 else if (Name == "lzcnt") 2046 Features["lzcnt"] = true; 2047 else if (Name == "rdrnd") 2048 Features["rdrand"] = true; 2049 else if (Name == "bmi") 2050 Features["bmi"] = true; 2051 else if (Name == "bmi2") 2052 Features["bmi2"] = true; 2053 else if (Name == "popcnt") 2054 Features["popcnt"] = true; 2055 else if (Name == "f16c") 2056 Features["f16c"] = true; 2057 else if (Name == "rtm") 2058 Features["rtm"] = true; 2059 } else { 2060 if (Name == "mmx") 2061 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 2062 else if (Name == "sse") 2063 Features["sse"] = Features["sse2"] = Features["sse3"] = 2064 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2065 Features["sse4a"] = Features["avx"] = Features["avx2"] = 2066 Features["fma"] = Features["fma4"] = Features["aes"] = 2067 Features["pclmul"] = Features["xop"] = false; 2068 else if (Name == "sse2") 2069 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 2070 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 2071 Features["avx"] = Features["avx2"] = Features["fma"] = 2072 Features["fma4"] = Features["aes"] = Features["pclmul"] = 2073 Features["xop"] = false; 2074 else if (Name == "sse3") 2075 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 2076 Features["sse42"] = Features["sse4a"] = Features["avx"] = 2077 Features["avx2"] = Features["fma"] = Features["fma4"] = 2078 Features["xop"] = false; 2079 else if (Name == "ssse3") 2080 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 2081 Features["avx"] = Features["avx2"] = Features["fma"] = false; 2082 else if (Name == "sse4" || Name == "sse4.1") 2083 Features["sse41"] = Features["sse42"] = Features["avx"] = 2084 Features["avx2"] = Features["fma"] = false; 2085 else if (Name == "sse4.2") 2086 Features["sse42"] = Features["avx"] = Features["avx2"] = 2087 Features["fma"] = false; 2088 else if (Name == "3dnow") 2089 Features["3dnow"] = Features["3dnowa"] = false; 2090 else if (Name == "3dnowa") 2091 Features["3dnowa"] = false; 2092 else if (Name == "aes") 2093 Features["aes"] = false; 2094 else if (Name == "pclmul") 2095 Features["pclmul"] = false; 2096 else if (Name == "avx") 2097 Features["avx"] = Features["avx2"] = Features["fma"] = 2098 Features["fma4"] = Features["xop"] = false; 2099 else if (Name == "avx2") 2100 Features["avx2"] = false; 2101 else if (Name == "fma") 2102 Features["fma"] = false; 2103 else if (Name == "sse4a") 2104 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 2105 else if (Name == "lzcnt") 2106 Features["lzcnt"] = false; 2107 else if (Name == "rdrnd") 2108 Features["rdrand"] = false; 2109 else if (Name == "bmi") 2110 Features["bmi"] = false; 2111 else if (Name == "bmi2") 2112 Features["bmi2"] = false; 2113 else if (Name == "popcnt") 2114 Features["popcnt"] = false; 2115 else if (Name == "fma4") 2116 Features["fma4"] = Features["xop"] = false; 2117 else if (Name == "xop") 2118 Features["xop"] = false; 2119 else if (Name == "f16c") 2120 Features["f16c"] = false; 2121 else if (Name == "rtm") 2122 Features["rtm"] = false; 2123 } 2124 2125 return true; 2126 } 2127 2128 /// HandleTargetOptions - Perform initialization based on the user 2129 /// configured set of features. 2130 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 2131 // Remember the maximum enabled sselevel. 2132 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2133 // Ignore disabled features. 2134 if (Features[i][0] == '-') 2135 continue; 2136 2137 StringRef Feature = StringRef(Features[i]).substr(1); 2138 2139 if (Feature == "aes") { 2140 HasAES = true; 2141 continue; 2142 } 2143 2144 if (Feature == "pclmul") { 2145 HasPCLMUL = true; 2146 continue; 2147 } 2148 2149 if (Feature == "lzcnt") { 2150 HasLZCNT = true; 2151 continue; 2152 } 2153 2154 if (Feature == "rdrand") { 2155 HasRDRND = true; 2156 continue; 2157 } 2158 2159 if (Feature == "bmi") { 2160 HasBMI = true; 2161 continue; 2162 } 2163 2164 if (Feature == "bmi2") { 2165 HasBMI2 = true; 2166 continue; 2167 } 2168 2169 if (Feature == "popcnt") { 2170 HasPOPCNT = true; 2171 continue; 2172 } 2173 2174 if (Feature == "rtm") { 2175 HasRTM = true; 2176 continue; 2177 } 2178 2179 if (Feature == "sse4a") { 2180 HasSSE4a = true; 2181 continue; 2182 } 2183 2184 if (Feature == "fma4") { 2185 HasFMA4 = true; 2186 continue; 2187 } 2188 2189 if (Feature == "fma") { 2190 HasFMA = true; 2191 continue; 2192 } 2193 2194 if (Feature == "xop") { 2195 HasXOP = true; 2196 continue; 2197 } 2198 2199 if (Feature == "f16c") { 2200 HasF16C = true; 2201 continue; 2202 } 2203 2204 assert(Features[i][0] == '+' && "Invalid target feature!"); 2205 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2206 .Case("avx2", AVX2) 2207 .Case("avx", AVX) 2208 .Case("sse42", SSE42) 2209 .Case("sse41", SSE41) 2210 .Case("ssse3", SSSE3) 2211 .Case("sse3", SSE3) 2212 .Case("sse2", SSE2) 2213 .Case("sse", SSE1) 2214 .Default(NoSSE); 2215 SSELevel = std::max(SSELevel, Level); 2216 2217 MMX3DNowEnum ThreeDNowLevel = 2218 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2219 .Case("3dnowa", AMD3DNowAthlon) 2220 .Case("3dnow", AMD3DNow) 2221 .Case("mmx", MMX) 2222 .Default(NoMMX3DNow); 2223 2224 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2225 } 2226 2227 // Don't tell the backend if we're turning off mmx; it will end up disabling 2228 // SSE, which we don't want. 2229 std::vector<std::string>::iterator it; 2230 it = std::find(Features.begin(), Features.end(), "-mmx"); 2231 if (it != Features.end()) 2232 Features.erase(it); 2233 } 2234 2235 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2236 /// definitions for this particular subtarget. 2237 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2238 MacroBuilder &Builder) const { 2239 // Target identification. 2240 if (getTriple().getArch() == llvm::Triple::x86_64) { 2241 Builder.defineMacro("__amd64__"); 2242 Builder.defineMacro("__amd64"); 2243 Builder.defineMacro("__x86_64"); 2244 Builder.defineMacro("__x86_64__"); 2245 } else { 2246 DefineStd(Builder, "i386", Opts); 2247 } 2248 2249 // Subtarget options. 2250 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2251 // truly should be based on -mtune options. 2252 switch (CPU) { 2253 case CK_Generic: 2254 break; 2255 case CK_i386: 2256 // The rest are coming from the i386 define above. 2257 Builder.defineMacro("__tune_i386__"); 2258 break; 2259 case CK_i486: 2260 case CK_WinChipC6: 2261 case CK_WinChip2: 2262 case CK_C3: 2263 defineCPUMacros(Builder, "i486"); 2264 break; 2265 case CK_PentiumMMX: 2266 Builder.defineMacro("__pentium_mmx__"); 2267 Builder.defineMacro("__tune_pentium_mmx__"); 2268 // Fallthrough 2269 case CK_i586: 2270 case CK_Pentium: 2271 defineCPUMacros(Builder, "i586"); 2272 defineCPUMacros(Builder, "pentium"); 2273 break; 2274 case CK_Pentium3: 2275 case CK_Pentium3M: 2276 case CK_PentiumM: 2277 Builder.defineMacro("__tune_pentium3__"); 2278 // Fallthrough 2279 case CK_Pentium2: 2280 case CK_C3_2: 2281 Builder.defineMacro("__tune_pentium2__"); 2282 // Fallthrough 2283 case CK_PentiumPro: 2284 Builder.defineMacro("__tune_i686__"); 2285 Builder.defineMacro("__tune_pentiumpro__"); 2286 // Fallthrough 2287 case CK_i686: 2288 Builder.defineMacro("__i686"); 2289 Builder.defineMacro("__i686__"); 2290 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2291 Builder.defineMacro("__pentiumpro"); 2292 Builder.defineMacro("__pentiumpro__"); 2293 break; 2294 case CK_Pentium4: 2295 case CK_Pentium4M: 2296 defineCPUMacros(Builder, "pentium4"); 2297 break; 2298 case CK_Yonah: 2299 case CK_Prescott: 2300 case CK_Nocona: 2301 defineCPUMacros(Builder, "nocona"); 2302 break; 2303 case CK_Core2: 2304 case CK_Penryn: 2305 defineCPUMacros(Builder, "core2"); 2306 break; 2307 case CK_Atom: 2308 defineCPUMacros(Builder, "atom"); 2309 break; 2310 case CK_Corei7: 2311 case CK_Corei7AVX: 2312 case CK_CoreAVXi: 2313 case CK_CoreAVX2: 2314 defineCPUMacros(Builder, "corei7"); 2315 break; 2316 case CK_K6_2: 2317 Builder.defineMacro("__k6_2__"); 2318 Builder.defineMacro("__tune_k6_2__"); 2319 // Fallthrough 2320 case CK_K6_3: 2321 if (CPU != CK_K6_2) { // In case of fallthrough 2322 // FIXME: GCC may be enabling these in cases where some other k6 2323 // architecture is specified but -m3dnow is explicitly provided. The 2324 // exact semantics need to be determined and emulated here. 2325 Builder.defineMacro("__k6_3__"); 2326 Builder.defineMacro("__tune_k6_3__"); 2327 } 2328 // Fallthrough 2329 case CK_K6: 2330 defineCPUMacros(Builder, "k6"); 2331 break; 2332 case CK_Athlon: 2333 case CK_AthlonThunderbird: 2334 case CK_Athlon4: 2335 case CK_AthlonXP: 2336 case CK_AthlonMP: 2337 defineCPUMacros(Builder, "athlon"); 2338 if (SSELevel != NoSSE) { 2339 Builder.defineMacro("__athlon_sse__"); 2340 Builder.defineMacro("__tune_athlon_sse__"); 2341 } 2342 break; 2343 case CK_K8: 2344 case CK_K8SSE3: 2345 case CK_x86_64: 2346 case CK_Opteron: 2347 case CK_OpteronSSE3: 2348 case CK_Athlon64: 2349 case CK_Athlon64SSE3: 2350 case CK_AthlonFX: 2351 defineCPUMacros(Builder, "k8"); 2352 break; 2353 case CK_AMDFAM10: 2354 defineCPUMacros(Builder, "amdfam10"); 2355 break; 2356 case CK_BTVER1: 2357 defineCPUMacros(Builder, "btver1"); 2358 break; 2359 case CK_BDVER1: 2360 defineCPUMacros(Builder, "bdver1"); 2361 break; 2362 case CK_BDVER2: 2363 defineCPUMacros(Builder, "bdver2"); 2364 break; 2365 case CK_Geode: 2366 defineCPUMacros(Builder, "geode"); 2367 break; 2368 } 2369 2370 // Target properties. 2371 Builder.defineMacro("__LITTLE_ENDIAN__"); 2372 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2373 2374 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2375 // functions in glibc header files that use FP Stack inline asm which the 2376 // backend can't deal with (PR879). 2377 Builder.defineMacro("__NO_MATH_INLINES"); 2378 2379 if (HasAES) 2380 Builder.defineMacro("__AES__"); 2381 2382 if (HasPCLMUL) 2383 Builder.defineMacro("__PCLMUL__"); 2384 2385 if (HasLZCNT) 2386 Builder.defineMacro("__LZCNT__"); 2387 2388 if (HasRDRND) 2389 Builder.defineMacro("__RDRND__"); 2390 2391 if (HasBMI) 2392 Builder.defineMacro("__BMI__"); 2393 2394 if (HasBMI2) 2395 Builder.defineMacro("__BMI2__"); 2396 2397 if (HasPOPCNT) 2398 Builder.defineMacro("__POPCNT__"); 2399 2400 if (HasRTM) 2401 Builder.defineMacro("__RTM__"); 2402 2403 if (HasSSE4a) 2404 Builder.defineMacro("__SSE4A__"); 2405 2406 if (HasFMA4) 2407 Builder.defineMacro("__FMA4__"); 2408 2409 if (HasFMA) 2410 Builder.defineMacro("__FMA__"); 2411 2412 if (HasXOP) 2413 Builder.defineMacro("__XOP__"); 2414 2415 if (HasF16C) 2416 Builder.defineMacro("__F16C__"); 2417 2418 // Each case falls through to the previous one here. 2419 switch (SSELevel) { 2420 case AVX2: 2421 Builder.defineMacro("__AVX2__"); 2422 case AVX: 2423 Builder.defineMacro("__AVX__"); 2424 case SSE42: 2425 Builder.defineMacro("__SSE4_2__"); 2426 case SSE41: 2427 Builder.defineMacro("__SSE4_1__"); 2428 case SSSE3: 2429 Builder.defineMacro("__SSSE3__"); 2430 case SSE3: 2431 Builder.defineMacro("__SSE3__"); 2432 case SSE2: 2433 Builder.defineMacro("__SSE2__"); 2434 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2435 case SSE1: 2436 Builder.defineMacro("__SSE__"); 2437 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2438 case NoSSE: 2439 break; 2440 } 2441 2442 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2443 switch (SSELevel) { 2444 case AVX2: 2445 case AVX: 2446 case SSE42: 2447 case SSE41: 2448 case SSSE3: 2449 case SSE3: 2450 case SSE2: 2451 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2452 break; 2453 case SSE1: 2454 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2455 break; 2456 default: 2457 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2458 } 2459 } 2460 2461 // Each case falls through to the previous one here. 2462 switch (MMX3DNowLevel) { 2463 case AMD3DNowAthlon: 2464 Builder.defineMacro("__3dNOW_A__"); 2465 case AMD3DNow: 2466 Builder.defineMacro("__3dNOW__"); 2467 case MMX: 2468 Builder.defineMacro("__MMX__"); 2469 case NoMMX3DNow: 2470 break; 2471 } 2472 } 2473 2474 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2475 return llvm::StringSwitch<bool>(Feature) 2476 .Case("aes", HasAES) 2477 .Case("avx", SSELevel >= AVX) 2478 .Case("avx2", SSELevel >= AVX2) 2479 .Case("bmi", HasBMI) 2480 .Case("bmi2", HasBMI2) 2481 .Case("fma", HasFMA) 2482 .Case("fma4", HasFMA4) 2483 .Case("lzcnt", HasLZCNT) 2484 .Case("rdrnd", HasRDRND) 2485 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2486 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2487 .Case("mmx", MMX3DNowLevel >= MMX) 2488 .Case("pclmul", HasPCLMUL) 2489 .Case("popcnt", HasPOPCNT) 2490 .Case("rtm", HasRTM) 2491 .Case("sse", SSELevel >= SSE1) 2492 .Case("sse2", SSELevel >= SSE2) 2493 .Case("sse3", SSELevel >= SSE3) 2494 .Case("ssse3", SSELevel >= SSSE3) 2495 .Case("sse41", SSELevel >= SSE41) 2496 .Case("sse42", SSELevel >= SSE42) 2497 .Case("sse4a", HasSSE4a) 2498 .Case("x86", true) 2499 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2500 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2501 .Case("xop", HasXOP) 2502 .Case("f16c", HasF16C) 2503 .Default(false); 2504 } 2505 2506 bool 2507 X86TargetInfo::validateAsmConstraint(const char *&Name, 2508 TargetInfo::ConstraintInfo &Info) const { 2509 switch (*Name) { 2510 default: return false; 2511 case 'Y': // first letter of a pair: 2512 switch (*(Name+1)) { 2513 default: return false; 2514 case '0': // First SSE register. 2515 case 't': // Any SSE register, when SSE2 is enabled. 2516 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2517 case 'm': // any MMX register, when inter-unit moves enabled. 2518 break; // falls through to setAllowsRegister. 2519 } 2520 case 'a': // eax. 2521 case 'b': // ebx. 2522 case 'c': // ecx. 2523 case 'd': // edx. 2524 case 'S': // esi. 2525 case 'D': // edi. 2526 case 'A': // edx:eax. 2527 case 'f': // any x87 floating point stack register. 2528 case 't': // top of floating point stack. 2529 case 'u': // second from top of floating point stack. 2530 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2531 case 'y': // Any MMX register. 2532 case 'x': // Any SSE register. 2533 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2534 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2535 case 'l': // "Index" registers: any general register that can be used as an 2536 // index in a base+index memory access. 2537 Info.setAllowsRegister(); 2538 return true; 2539 case 'C': // SSE floating point constant. 2540 case 'G': // x87 floating point constant. 2541 case 'e': // 32-bit signed integer constant for use with zero-extending 2542 // x86_64 instructions. 2543 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2544 // x86_64 instructions. 2545 return true; 2546 } 2547 } 2548 2549 2550 std::string 2551 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2552 switch (*Constraint) { 2553 case 'a': return std::string("{ax}"); 2554 case 'b': return std::string("{bx}"); 2555 case 'c': return std::string("{cx}"); 2556 case 'd': return std::string("{dx}"); 2557 case 'S': return std::string("{si}"); 2558 case 'D': return std::string("{di}"); 2559 case 'p': // address 2560 return std::string("im"); 2561 case 't': // top of floating point stack. 2562 return std::string("{st}"); 2563 case 'u': // second from top of floating point stack. 2564 return std::string("{st(1)}"); // second from top of floating point stack. 2565 default: 2566 return std::string(1, *Constraint); 2567 } 2568 } 2569 } // end anonymous namespace 2570 2571 namespace { 2572 // X86-32 generic target 2573 class X86_32TargetInfo : public X86TargetInfo { 2574 public: 2575 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2576 DoubleAlign = LongLongAlign = 32; 2577 LongDoubleWidth = 96; 2578 LongDoubleAlign = 32; 2579 SuitableAlign = 128; 2580 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2581 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2582 "a0:0:64-f80:32:32-n8:16:32-S128"; 2583 SizeType = UnsignedInt; 2584 PtrDiffType = SignedInt; 2585 IntPtrType = SignedInt; 2586 RegParmMax = 3; 2587 2588 // Use fpret for all types. 2589 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2590 (1 << TargetInfo::Double) | 2591 (1 << TargetInfo::LongDouble)); 2592 2593 // x86-32 has atomics up to 8 bytes 2594 // FIXME: Check that we actually have cmpxchg8b before setting 2595 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2596 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2597 } 2598 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2599 return TargetInfo::CharPtrBuiltinVaList; 2600 } 2601 2602 int getEHDataRegisterNumber(unsigned RegNo) const { 2603 if (RegNo == 0) return 0; 2604 if (RegNo == 1) return 2; 2605 return -1; 2606 } 2607 virtual bool validateInputSize(StringRef Constraint, 2608 unsigned Size) const { 2609 switch (Constraint[0]) { 2610 default: break; 2611 case 'a': 2612 case 'b': 2613 case 'c': 2614 case 'd': 2615 return Size <= 32; 2616 } 2617 2618 return true; 2619 } 2620 }; 2621 } // end anonymous namespace 2622 2623 namespace { 2624 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2625 public: 2626 NetBSDI386TargetInfo(const std::string &triple) : 2627 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2628 } 2629 2630 virtual unsigned getFloatEvalMethod() const { 2631 // NetBSD defaults to "double" rounding 2632 return 1; 2633 } 2634 }; 2635 } // end anonymous namespace 2636 2637 namespace { 2638 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2639 public: 2640 OpenBSDI386TargetInfo(const std::string& triple) : 2641 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2642 SizeType = UnsignedLong; 2643 IntPtrType = SignedLong; 2644 PtrDiffType = SignedLong; 2645 } 2646 }; 2647 } // end anonymous namespace 2648 2649 namespace { 2650 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2651 public: 2652 BitrigI386TargetInfo(const std::string& triple) : 2653 BitrigTargetInfo<X86_32TargetInfo>(triple) { 2654 SizeType = UnsignedLong; 2655 IntPtrType = SignedLong; 2656 PtrDiffType = SignedLong; 2657 } 2658 }; 2659 } // end anonymous namespace 2660 2661 namespace { 2662 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2663 public: 2664 DarwinI386TargetInfo(const std::string& triple) : 2665 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2666 LongDoubleWidth = 128; 2667 LongDoubleAlign = 128; 2668 SuitableAlign = 128; 2669 MaxVectorAlign = 256; 2670 SizeType = UnsignedLong; 2671 IntPtrType = SignedLong; 2672 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2673 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2674 "a0:0:64-f80:128:128-n8:16:32-S128"; 2675 HasAlignMac68kSupport = true; 2676 } 2677 2678 }; 2679 } // end anonymous namespace 2680 2681 namespace { 2682 // x86-32 Windows target 2683 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2684 public: 2685 WindowsX86_32TargetInfo(const std::string& triple) 2686 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2687 TLSSupported = false; 2688 WCharType = UnsignedShort; 2689 DoubleAlign = LongLongAlign = 64; 2690 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2691 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2692 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2693 } 2694 virtual void getTargetDefines(const LangOptions &Opts, 2695 MacroBuilder &Builder) const { 2696 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2697 } 2698 }; 2699 } // end anonymous namespace 2700 2701 namespace { 2702 2703 // x86-32 Windows Visual Studio target 2704 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2705 public: 2706 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2707 : WindowsX86_32TargetInfo(triple) { 2708 LongDoubleWidth = LongDoubleAlign = 64; 2709 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2710 } 2711 virtual void getTargetDefines(const LangOptions &Opts, 2712 MacroBuilder &Builder) const { 2713 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2714 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2715 // The value of the following reflects processor type. 2716 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2717 // We lost the original triple, so we use the default. 2718 Builder.defineMacro("_M_IX86", "600"); 2719 } 2720 }; 2721 } // end anonymous namespace 2722 2723 namespace { 2724 // x86-32 MinGW target 2725 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2726 public: 2727 MinGWX86_32TargetInfo(const std::string& triple) 2728 : WindowsX86_32TargetInfo(triple) { 2729 } 2730 virtual void getTargetDefines(const LangOptions &Opts, 2731 MacroBuilder &Builder) const { 2732 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2733 DefineStd(Builder, "WIN32", Opts); 2734 DefineStd(Builder, "WINNT", Opts); 2735 Builder.defineMacro("_X86_"); 2736 Builder.defineMacro("__MSVCRT__"); 2737 Builder.defineMacro("__MINGW32__"); 2738 2739 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2740 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2741 if (Opts.MicrosoftExt) 2742 // Provide "as-is" __declspec. 2743 Builder.defineMacro("__declspec", "__declspec"); 2744 else 2745 // Provide alias of __attribute__ like mingw32-gcc. 2746 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2747 } 2748 }; 2749 } // end anonymous namespace 2750 2751 namespace { 2752 // x86-32 Cygwin target 2753 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2754 public: 2755 CygwinX86_32TargetInfo(const std::string& triple) 2756 : X86_32TargetInfo(triple) { 2757 TLSSupported = false; 2758 WCharType = UnsignedShort; 2759 DoubleAlign = LongLongAlign = 64; 2760 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2761 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2762 "a0:0:64-f80:32:32-n8:16:32-S32"; 2763 } 2764 virtual void getTargetDefines(const LangOptions &Opts, 2765 MacroBuilder &Builder) const { 2766 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2767 Builder.defineMacro("_X86_"); 2768 Builder.defineMacro("__CYGWIN__"); 2769 Builder.defineMacro("__CYGWIN32__"); 2770 DefineStd(Builder, "unix", Opts); 2771 if (Opts.CPlusPlus) 2772 Builder.defineMacro("_GNU_SOURCE"); 2773 } 2774 }; 2775 } // end anonymous namespace 2776 2777 namespace { 2778 // x86-32 Haiku target 2779 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2780 public: 2781 HaikuX86_32TargetInfo(const std::string& triple) 2782 : X86_32TargetInfo(triple) { 2783 SizeType = UnsignedLong; 2784 IntPtrType = SignedLong; 2785 PtrDiffType = SignedLong; 2786 ProcessIDType = SignedLong; 2787 this->UserLabelPrefix = ""; 2788 this->TLSSupported = false; 2789 } 2790 virtual void getTargetDefines(const LangOptions &Opts, 2791 MacroBuilder &Builder) const { 2792 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2793 Builder.defineMacro("__INTEL__"); 2794 Builder.defineMacro("__HAIKU__"); 2795 } 2796 }; 2797 } // end anonymous namespace 2798 2799 // RTEMS Target 2800 template<typename Target> 2801 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2802 protected: 2803 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2804 MacroBuilder &Builder) const { 2805 // RTEMS defines; list based off of gcc output 2806 2807 Builder.defineMacro("__rtems__"); 2808 Builder.defineMacro("__ELF__"); 2809 } 2810 public: 2811 RTEMSTargetInfo(const std::string &triple) 2812 : OSTargetInfo<Target>(triple) { 2813 this->UserLabelPrefix = ""; 2814 2815 llvm::Triple Triple(triple); 2816 switch (Triple.getArch()) { 2817 default: 2818 case llvm::Triple::x86: 2819 // this->MCountName = ".mcount"; 2820 break; 2821 case llvm::Triple::mips: 2822 case llvm::Triple::mipsel: 2823 case llvm::Triple::ppc: 2824 case llvm::Triple::ppc64: 2825 // this->MCountName = "_mcount"; 2826 break; 2827 case llvm::Triple::arm: 2828 // this->MCountName = "__mcount"; 2829 break; 2830 } 2831 2832 } 2833 }; 2834 2835 namespace { 2836 // x86-32 RTEMS target 2837 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2838 public: 2839 RTEMSX86_32TargetInfo(const std::string& triple) 2840 : X86_32TargetInfo(triple) { 2841 SizeType = UnsignedLong; 2842 IntPtrType = SignedLong; 2843 PtrDiffType = SignedLong; 2844 this->UserLabelPrefix = ""; 2845 } 2846 virtual void getTargetDefines(const LangOptions &Opts, 2847 MacroBuilder &Builder) const { 2848 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2849 Builder.defineMacro("__INTEL__"); 2850 Builder.defineMacro("__rtems__"); 2851 } 2852 }; 2853 } // end anonymous namespace 2854 2855 namespace { 2856 // x86-64 generic target 2857 class X86_64TargetInfo : public X86TargetInfo { 2858 public: 2859 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2860 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2861 LongDoubleWidth = 128; 2862 LongDoubleAlign = 128; 2863 LargeArrayMinWidth = 128; 2864 LargeArrayAlign = 128; 2865 SuitableAlign = 128; 2866 IntMaxType = SignedLong; 2867 UIntMaxType = UnsignedLong; 2868 Int64Type = SignedLong; 2869 RegParmMax = 6; 2870 2871 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2872 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2873 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2874 2875 // Use fpret only for long double. 2876 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2877 2878 // Use fp2ret for _Complex long double. 2879 ComplexLongDoubleUsesFP2Ret = true; 2880 2881 // x86-64 has atomics up to 16 bytes. 2882 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2883 // on CPUs with cmpxchg16b 2884 MaxAtomicPromoteWidth = 128; 2885 MaxAtomicInlineWidth = 64; 2886 } 2887 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2888 return TargetInfo::X86_64ABIBuiltinVaList; 2889 } 2890 2891 int getEHDataRegisterNumber(unsigned RegNo) const { 2892 if (RegNo == 0) return 0; 2893 if (RegNo == 1) return 1; 2894 return -1; 2895 } 2896 2897 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 2898 return TargetInfo::checkCallingConvention(CC); 2899 } 2900 2901 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 2902 return CC_C; 2903 } 2904 2905 }; 2906 } // end anonymous namespace 2907 2908 namespace { 2909 // x86-64 Windows target 2910 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2911 public: 2912 WindowsX86_64TargetInfo(const std::string& triple) 2913 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2914 TLSSupported = false; 2915 WCharType = UnsignedShort; 2916 LongWidth = LongAlign = 32; 2917 DoubleAlign = LongLongAlign = 64; 2918 IntMaxType = SignedLongLong; 2919 UIntMaxType = UnsignedLongLong; 2920 Int64Type = SignedLongLong; 2921 SizeType = UnsignedLongLong; 2922 PtrDiffType = SignedLongLong; 2923 IntPtrType = SignedLongLong; 2924 this->UserLabelPrefix = ""; 2925 } 2926 virtual void getTargetDefines(const LangOptions &Opts, 2927 MacroBuilder &Builder) const { 2928 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2929 Builder.defineMacro("_WIN64"); 2930 } 2931 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2932 return TargetInfo::CharPtrBuiltinVaList; 2933 } 2934 }; 2935 } // end anonymous namespace 2936 2937 namespace { 2938 // x86-64 Windows Visual Studio target 2939 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2940 public: 2941 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2942 : WindowsX86_64TargetInfo(triple) { 2943 LongDoubleWidth = LongDoubleAlign = 64; 2944 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2945 } 2946 virtual void getTargetDefines(const LangOptions &Opts, 2947 MacroBuilder &Builder) const { 2948 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2949 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2950 Builder.defineMacro("_M_X64"); 2951 Builder.defineMacro("_M_AMD64"); 2952 } 2953 }; 2954 } // end anonymous namespace 2955 2956 namespace { 2957 // x86-64 MinGW target 2958 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2959 public: 2960 MinGWX86_64TargetInfo(const std::string& triple) 2961 : WindowsX86_64TargetInfo(triple) { 2962 } 2963 virtual void getTargetDefines(const LangOptions &Opts, 2964 MacroBuilder &Builder) const { 2965 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2966 DefineStd(Builder, "WIN64", Opts); 2967 Builder.defineMacro("__MSVCRT__"); 2968 Builder.defineMacro("__MINGW32__"); 2969 Builder.defineMacro("__MINGW64__"); 2970 2971 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2972 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2973 if (Opts.MicrosoftExt) 2974 // Provide "as-is" __declspec. 2975 Builder.defineMacro("__declspec", "__declspec"); 2976 else 2977 // Provide alias of __attribute__ like mingw32-gcc. 2978 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2979 } 2980 }; 2981 } // end anonymous namespace 2982 2983 namespace { 2984 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2985 public: 2986 DarwinX86_64TargetInfo(const std::string& triple) 2987 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2988 Int64Type = SignedLongLong; 2989 MaxVectorAlign = 256; 2990 } 2991 }; 2992 } // end anonymous namespace 2993 2994 namespace { 2995 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2996 public: 2997 OpenBSDX86_64TargetInfo(const std::string& triple) 2998 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2999 IntMaxType = SignedLongLong; 3000 UIntMaxType = UnsignedLongLong; 3001 Int64Type = SignedLongLong; 3002 } 3003 }; 3004 } // end anonymous namespace 3005 3006 namespace { 3007 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3008 public: 3009 BitrigX86_64TargetInfo(const std::string& triple) 3010 : BitrigTargetInfo<X86_64TargetInfo>(triple) { 3011 IntMaxType = SignedLongLong; 3012 UIntMaxType = UnsignedLongLong; 3013 Int64Type = SignedLongLong; 3014 } 3015 }; 3016 } // end anonymous namespace 3017 3018 namespace { 3019 class ARMTargetInfo : public TargetInfo { 3020 // Possible FPU choices. 3021 enum FPUMode { 3022 VFP2FPU = (1 << 0), 3023 VFP3FPU = (1 << 1), 3024 VFP4FPU = (1 << 2), 3025 NeonFPU = (1 << 3) 3026 }; 3027 3028 static bool FPUModeIsVFP(FPUMode Mode) { 3029 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 3030 } 3031 3032 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3033 static const char * const GCCRegNames[]; 3034 3035 std::string ABI, CPU; 3036 3037 unsigned FPU : 4; 3038 3039 unsigned IsAAPCS : 1; 3040 unsigned IsThumb : 1; 3041 3042 // Initialized via features. 3043 unsigned SoftFloat : 1; 3044 unsigned SoftFloatABI : 1; 3045 3046 static const Builtin::Info BuiltinInfo[]; 3047 3048 public: 3049 ARMTargetInfo(const std::string &TripleStr) 3050 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s"), IsAAPCS(true) 3051 { 3052 BigEndian = false; 3053 SizeType = UnsignedInt; 3054 PtrDiffType = SignedInt; 3055 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3056 WCharType = UnsignedInt; 3057 3058 // {} in inline assembly are neon specifiers, not assembly variant 3059 // specifiers. 3060 NoAsmVariants = true; 3061 3062 // FIXME: Should we just treat this as a feature? 3063 IsThumb = getTriple().getArchName().startswith("thumb"); 3064 if (IsThumb) { 3065 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3066 // so set preferred for small types to 32. 3067 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3068 "i64:64:64-f32:32:32-f64:64:64-" 3069 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3070 } else { 3071 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3072 "i64:64:64-f32:32:32-f64:64:64-" 3073 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3074 } 3075 3076 // ARM targets default to using the ARM C++ ABI. 3077 CXXABI = CXXABI_ARM; 3078 3079 // ARM has atomics up to 8 bytes 3080 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 3081 MaxAtomicPromoteWidth = 64; 3082 3083 // Do force alignment of members that follow zero length bitfields. If 3084 // the alignment of the zero-length bitfield is greater than the member 3085 // that follows it, `bar', `bar' will be aligned as the type of the 3086 // zero length bitfield. 3087 UseZeroLengthBitfieldAlignment = true; 3088 } 3089 virtual const char *getABI() const { return ABI.c_str(); } 3090 virtual bool setABI(const std::string &Name) { 3091 ABI = Name; 3092 3093 // The defaults (above) are for AAPCS, check if we need to change them. 3094 // 3095 // FIXME: We need support for -meabi... we could just mangle it into the 3096 // name. 3097 if (Name == "apcs-gnu") { 3098 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3099 // size_t is unsigned int on FreeBSD. 3100 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3101 SizeType = UnsignedLong; 3102 3103 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3104 WCharType = SignedInt; 3105 3106 // Do not respect the alignment of bit-field types when laying out 3107 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3108 UseBitFieldTypeAlignment = false; 3109 3110 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3111 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3112 /// gcc. 3113 ZeroLengthBitfieldBoundary = 32; 3114 3115 IsAAPCS = false; 3116 3117 if (IsThumb) { 3118 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3119 // so set preferred for small types to 32. 3120 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3121 "i64:32:64-f32:32:32-f64:32:64-" 3122 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3123 } else { 3124 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3125 "i64:32:64-f32:32:32-f64:32:64-" 3126 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3127 } 3128 3129 // FIXME: Override "preferred align" for double and long long. 3130 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3131 IsAAPCS = true; 3132 // FIXME: Enumerated types are variable width in straight AAPCS. 3133 } else if (Name == "aapcs-linux") { 3134 IsAAPCS = true; 3135 } else 3136 return false; 3137 3138 return true; 3139 } 3140 3141 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3142 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3143 Features["vfp2"] = true; 3144 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 3145 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 3146 Features["neon"] = true; 3147 else if (CPU == "swift") { 3148 Features["vfp4"] = true; 3149 Features["neon"] = true; 3150 } 3151 } 3152 3153 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3154 StringRef Name, 3155 bool Enabled) const { 3156 if (Name == "soft-float" || Name == "soft-float-abi" || 3157 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" || 3158 Name == "d16" || Name == "neonfp") { 3159 Features[Name] = Enabled; 3160 } else 3161 return false; 3162 3163 return true; 3164 } 3165 3166 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3167 FPU = 0; 3168 SoftFloat = SoftFloatABI = false; 3169 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3170 if (Features[i] == "+soft-float") 3171 SoftFloat = true; 3172 else if (Features[i] == "+soft-float-abi") 3173 SoftFloatABI = true; 3174 else if (Features[i] == "+vfp2") 3175 FPU |= VFP2FPU; 3176 else if (Features[i] == "+vfp3") 3177 FPU |= VFP3FPU; 3178 else if (Features[i] == "+vfp4") 3179 FPU |= VFP4FPU; 3180 else if (Features[i] == "+neon") 3181 FPU |= NeonFPU; 3182 } 3183 3184 // Remove front-end specific options which the backend handles differently. 3185 std::vector<std::string>::iterator it; 3186 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3187 if (it != Features.end()) 3188 Features.erase(it); 3189 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3190 if (it != Features.end()) 3191 Features.erase(it); 3192 } 3193 3194 virtual bool hasFeature(StringRef Feature) const { 3195 return llvm::StringSwitch<bool>(Feature) 3196 .Case("arm", true) 3197 .Case("softfloat", SoftFloat) 3198 .Case("thumb", IsThumb) 3199 .Case("neon", FPU == NeonFPU && !SoftFloat && 3200 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3201 .Default(false); 3202 } 3203 // FIXME: Should we actually have some table instead of these switches? 3204 static const char *getCPUDefineSuffix(StringRef Name) { 3205 return llvm::StringSwitch<const char*>(Name) 3206 .Cases("arm8", "arm810", "4") 3207 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3208 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3209 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3210 .Case("ep9312", "4T") 3211 .Cases("arm10tdmi", "arm1020t", "5T") 3212 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3213 .Case("arm926ej-s", "5TEJ") 3214 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3215 .Cases("xscale", "iwmmxt", "5TE") 3216 .Case("arm1136j-s", "6J") 3217 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3218 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3219 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3220 .Cases("cortex-a5", "cortex-a8", "cortex-a9", "cortex-a15", "7A") 3221 .Case("cortex-r5", "7R") 3222 .Case("cortex-a9-mp", "7F") 3223 .Case("swift", "7S") 3224 .Cases("cortex-m3", "cortex-m4", "7M") 3225 .Case("cortex-m0", "6M") 3226 .Default(0); 3227 } 3228 static const char *getCPUProfile(StringRef Name) { 3229 return llvm::StringSwitch<const char*>(Name) 3230 .Cases("cortex-a8", "cortex-a9", "A") 3231 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3232 .Case("cortex-r5", "R") 3233 .Default(""); 3234 } 3235 virtual bool setCPU(const std::string &Name) { 3236 if (!getCPUDefineSuffix(Name)) 3237 return false; 3238 3239 CPU = Name; 3240 return true; 3241 } 3242 virtual void getTargetDefines(const LangOptions &Opts, 3243 MacroBuilder &Builder) const { 3244 // Target identification. 3245 Builder.defineMacro("__arm"); 3246 Builder.defineMacro("__arm__"); 3247 3248 // Target properties. 3249 Builder.defineMacro("__ARMEL__"); 3250 Builder.defineMacro("__LITTLE_ENDIAN__"); 3251 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3252 3253 StringRef CPUArch = getCPUDefineSuffix(CPU); 3254 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3255 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3256 StringRef CPUProfile = getCPUProfile(CPU); 3257 if (!CPUProfile.empty()) 3258 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3259 3260 // Subtarget options. 3261 3262 // FIXME: It's more complicated than this and we don't really support 3263 // interworking. 3264 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3265 Builder.defineMacro("__THUMB_INTERWORK__"); 3266 3267 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3268 // M-class CPUs on Darwin follow AAPCS, but not EABI. 3269 if (!(getTriple().isOSDarwin() && CPUProfile == "M")) 3270 Builder.defineMacro("__ARM_EABI__"); 3271 Builder.defineMacro("__ARM_PCS", "1"); 3272 3273 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3274 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3275 } 3276 3277 if (SoftFloat) 3278 Builder.defineMacro("__SOFTFP__"); 3279 3280 if (CPU == "xscale") 3281 Builder.defineMacro("__XSCALE__"); 3282 3283 bool IsARMv7 = CPUArch.startswith("7"); 3284 if (IsThumb) { 3285 Builder.defineMacro("__THUMBEL__"); 3286 Builder.defineMacro("__thumb__"); 3287 if (CPUArch == "6T2" || IsARMv7) 3288 Builder.defineMacro("__thumb2__"); 3289 } 3290 3291 // Note, this is always on in gcc, even though it doesn't make sense. 3292 Builder.defineMacro("__APCS_32__"); 3293 3294 if (FPUModeIsVFP((FPUMode) FPU)) { 3295 Builder.defineMacro("__VFP_FP__"); 3296 if (FPU & VFP2FPU) 3297 Builder.defineMacro("__ARM_VFPV2__"); 3298 if (FPU & VFP3FPU) 3299 Builder.defineMacro("__ARM_VFPV3__"); 3300 if (FPU & VFP4FPU) 3301 Builder.defineMacro("__ARM_VFPV4__"); 3302 } 3303 3304 // This only gets set when Neon instructions are actually available, unlike 3305 // the VFP define, hence the soft float and arch check. This is subtly 3306 // different from gcc, we follow the intent which was that it should be set 3307 // when Neon instructions are actually available. 3308 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3309 Builder.defineMacro("__ARM_NEON__"); 3310 } 3311 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3312 unsigned &NumRecords) const { 3313 Records = BuiltinInfo; 3314 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3315 } 3316 virtual bool isCLZForZeroUndef() const { return false; } 3317 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3318 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 3319 } 3320 virtual void getGCCRegNames(const char * const *&Names, 3321 unsigned &NumNames) const; 3322 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3323 unsigned &NumAliases) const; 3324 virtual bool validateAsmConstraint(const char *&Name, 3325 TargetInfo::ConstraintInfo &Info) const { 3326 switch (*Name) { 3327 default: break; 3328 case 'l': // r0-r7 3329 case 'h': // r8-r15 3330 case 'w': // VFP Floating point register single precision 3331 case 'P': // VFP Floating point register double precision 3332 Info.setAllowsRegister(); 3333 return true; 3334 case 'Q': // A memory address that is a single base register. 3335 Info.setAllowsMemory(); 3336 return true; 3337 case 'U': // a memory reference... 3338 switch (Name[1]) { 3339 case 'q': // ...ARMV4 ldrsb 3340 case 'v': // ...VFP load/store (reg+constant offset) 3341 case 'y': // ...iWMMXt load/store 3342 case 't': // address valid for load/store opaque types wider 3343 // than 128-bits 3344 case 'n': // valid address for Neon doubleword vector load/store 3345 case 'm': // valid address for Neon element and structure load/store 3346 case 's': // valid address for non-offset loads/stores of quad-word 3347 // values in four ARM registers 3348 Info.setAllowsMemory(); 3349 Name++; 3350 return true; 3351 } 3352 } 3353 return false; 3354 } 3355 virtual std::string convertConstraint(const char *&Constraint) const { 3356 std::string R; 3357 switch (*Constraint) { 3358 case 'U': // Two-character constraint; add "^" hint for later parsing. 3359 R = std::string("^") + std::string(Constraint, 2); 3360 Constraint++; 3361 break; 3362 case 'p': // 'p' should be translated to 'r' by default. 3363 R = std::string("r"); 3364 break; 3365 default: 3366 return std::string(1, *Constraint); 3367 } 3368 return R; 3369 } 3370 virtual bool validateConstraintModifier(StringRef Constraint, 3371 const char Modifier, 3372 unsigned Size) const { 3373 bool isOutput = (Constraint[0] == '='); 3374 bool isInOut = (Constraint[0] == '+'); 3375 3376 // Strip off constraint modifiers. 3377 while (Constraint[0] == '=' || 3378 Constraint[0] == '+' || 3379 Constraint[0] == '&') 3380 Constraint = Constraint.substr(1); 3381 3382 switch (Constraint[0]) { 3383 default: break; 3384 case 'r': { 3385 switch (Modifier) { 3386 default: 3387 return isInOut || (isOutput && Size >= 32) || 3388 (!isOutput && !isInOut && Size <= 32); 3389 case 'q': 3390 // A register of size 32 cannot fit a vector type. 3391 return false; 3392 } 3393 } 3394 } 3395 3396 return true; 3397 } 3398 virtual const char *getClobbers() const { 3399 // FIXME: Is this really right? 3400 return ""; 3401 } 3402 3403 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3404 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3405 } 3406 }; 3407 3408 const char * const ARMTargetInfo::GCCRegNames[] = { 3409 // Integer registers 3410 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3411 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3412 3413 // Float registers 3414 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3415 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3416 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3417 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3418 3419 // Double registers 3420 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3421 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3422 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3423 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3424 3425 // Quad registers 3426 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3427 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3428 }; 3429 3430 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3431 unsigned &NumNames) const { 3432 Names = GCCRegNames; 3433 NumNames = llvm::array_lengthof(GCCRegNames); 3434 } 3435 3436 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3437 { { "a1" }, "r0" }, 3438 { { "a2" }, "r1" }, 3439 { { "a3" }, "r2" }, 3440 { { "a4" }, "r3" }, 3441 { { "v1" }, "r4" }, 3442 { { "v2" }, "r5" }, 3443 { { "v3" }, "r6" }, 3444 { { "v4" }, "r7" }, 3445 { { "v5" }, "r8" }, 3446 { { "v6", "rfp" }, "r9" }, 3447 { { "sl" }, "r10" }, 3448 { { "fp" }, "r11" }, 3449 { { "ip" }, "r12" }, 3450 { { "r13" }, "sp" }, 3451 { { "r14" }, "lr" }, 3452 { { "r15" }, "pc" }, 3453 // The S, D and Q registers overlap, but aren't really aliases; we 3454 // don't want to substitute one of these for a different-sized one. 3455 }; 3456 3457 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3458 unsigned &NumAliases) const { 3459 Aliases = GCCRegAliases; 3460 NumAliases = llvm::array_lengthof(GCCRegAliases); 3461 } 3462 3463 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3464 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3465 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3466 ALL_LANGUAGES }, 3467 #include "clang/Basic/BuiltinsARM.def" 3468 }; 3469 } // end anonymous namespace. 3470 3471 namespace { 3472 class DarwinARMTargetInfo : 3473 public DarwinTargetInfo<ARMTargetInfo> { 3474 protected: 3475 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3476 MacroBuilder &Builder) const { 3477 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3478 } 3479 3480 public: 3481 DarwinARMTargetInfo(const std::string& triple) 3482 : DarwinTargetInfo<ARMTargetInfo>(triple) { 3483 HasAlignMac68kSupport = true; 3484 // iOS always has 64-bit atomic instructions. 3485 // FIXME: This should be based off of the target features in ARMTargetInfo. 3486 MaxAtomicInlineWidth = 64; 3487 } 3488 }; 3489 } // end anonymous namespace. 3490 3491 3492 namespace { 3493 // Hexagon abstract base class 3494 class HexagonTargetInfo : public TargetInfo { 3495 static const Builtin::Info BuiltinInfo[]; 3496 static const char * const GCCRegNames[]; 3497 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3498 std::string CPU; 3499 public: 3500 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3501 BigEndian = false; 3502 DescriptionString = ("e-p:32:32:32-" 3503 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 3504 "f64:64:64-f32:32:32-a0:0-n32"); 3505 3506 // {} in inline assembly are packet specifiers, not assembly variant 3507 // specifiers. 3508 NoAsmVariants = true; 3509 } 3510 3511 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3512 unsigned &NumRecords) const { 3513 Records = BuiltinInfo; 3514 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3515 } 3516 3517 virtual bool validateAsmConstraint(const char *&Name, 3518 TargetInfo::ConstraintInfo &Info) const { 3519 return true; 3520 } 3521 3522 virtual void getTargetDefines(const LangOptions &Opts, 3523 MacroBuilder &Builder) const; 3524 3525 virtual bool hasFeature(StringRef Feature) const { 3526 return Feature == "hexagon"; 3527 } 3528 3529 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3530 return TargetInfo::CharPtrBuiltinVaList; 3531 } 3532 virtual void getGCCRegNames(const char * const *&Names, 3533 unsigned &NumNames) const; 3534 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3535 unsigned &NumAliases) const; 3536 virtual const char *getClobbers() const { 3537 return ""; 3538 } 3539 3540 static const char *getHexagonCPUSuffix(StringRef Name) { 3541 return llvm::StringSwitch<const char*>(Name) 3542 .Case("hexagonv2", "2") 3543 .Case("hexagonv3", "3") 3544 .Case("hexagonv4", "4") 3545 .Case("hexagonv5", "5") 3546 .Default(0); 3547 } 3548 3549 virtual bool setCPU(const std::string &Name) { 3550 if (!getHexagonCPUSuffix(Name)) 3551 return false; 3552 3553 CPU = Name; 3554 return true; 3555 } 3556 }; 3557 3558 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3559 MacroBuilder &Builder) const { 3560 Builder.defineMacro("qdsp6"); 3561 Builder.defineMacro("__qdsp6", "1"); 3562 Builder.defineMacro("__qdsp6__", "1"); 3563 3564 Builder.defineMacro("hexagon"); 3565 Builder.defineMacro("__hexagon", "1"); 3566 Builder.defineMacro("__hexagon__", "1"); 3567 3568 if(CPU == "hexagonv1") { 3569 Builder.defineMacro("__HEXAGON_V1__"); 3570 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3571 if(Opts.HexagonQdsp6Compat) { 3572 Builder.defineMacro("__QDSP6_V1__"); 3573 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3574 } 3575 } 3576 else if(CPU == "hexagonv2") { 3577 Builder.defineMacro("__HEXAGON_V2__"); 3578 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3579 if(Opts.HexagonQdsp6Compat) { 3580 Builder.defineMacro("__QDSP6_V2__"); 3581 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3582 } 3583 } 3584 else if(CPU == "hexagonv3") { 3585 Builder.defineMacro("__HEXAGON_V3__"); 3586 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3587 if(Opts.HexagonQdsp6Compat) { 3588 Builder.defineMacro("__QDSP6_V3__"); 3589 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3590 } 3591 } 3592 else if(CPU == "hexagonv4") { 3593 Builder.defineMacro("__HEXAGON_V4__"); 3594 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3595 if(Opts.HexagonQdsp6Compat) { 3596 Builder.defineMacro("__QDSP6_V4__"); 3597 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3598 } 3599 } 3600 else if(CPU == "hexagonv5") { 3601 Builder.defineMacro("__HEXAGON_V5__"); 3602 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3603 if(Opts.HexagonQdsp6Compat) { 3604 Builder.defineMacro("__QDSP6_V5__"); 3605 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3606 } 3607 } 3608 } 3609 3610 const char * const HexagonTargetInfo::GCCRegNames[] = { 3611 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3612 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3613 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3614 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3615 "p0", "p1", "p2", "p3", 3616 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3617 }; 3618 3619 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3620 unsigned &NumNames) const { 3621 Names = GCCRegNames; 3622 NumNames = llvm::array_lengthof(GCCRegNames); 3623 } 3624 3625 3626 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3627 { { "sp" }, "r29" }, 3628 { { "fp" }, "r30" }, 3629 { { "lr" }, "r31" }, 3630 }; 3631 3632 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3633 unsigned &NumAliases) const { 3634 Aliases = GCCRegAliases; 3635 NumAliases = llvm::array_lengthof(GCCRegAliases); 3636 } 3637 3638 3639 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3640 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3641 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3642 ALL_LANGUAGES }, 3643 #include "clang/Basic/BuiltinsHexagon.def" 3644 }; 3645 } 3646 3647 3648 namespace { 3649 class SparcV8TargetInfo : public TargetInfo { 3650 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3651 static const char * const GCCRegNames[]; 3652 bool SoftFloat; 3653 public: 3654 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3655 // FIXME: Support Sparc quad-precision long double? 3656 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3657 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3658 } 3659 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3660 StringRef Name, 3661 bool Enabled) const { 3662 if (Name == "soft-float") 3663 Features[Name] = Enabled; 3664 else 3665 return false; 3666 3667 return true; 3668 } 3669 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3670 SoftFloat = false; 3671 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3672 if (Features[i] == "+soft-float") 3673 SoftFloat = true; 3674 } 3675 virtual void getTargetDefines(const LangOptions &Opts, 3676 MacroBuilder &Builder) const { 3677 DefineStd(Builder, "sparc", Opts); 3678 Builder.defineMacro("__sparcv8"); 3679 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3680 3681 if (SoftFloat) 3682 Builder.defineMacro("SOFT_FLOAT", "1"); 3683 } 3684 3685 virtual bool hasFeature(StringRef Feature) const { 3686 return llvm::StringSwitch<bool>(Feature) 3687 .Case("softfloat", SoftFloat) 3688 .Case("sparc", true) 3689 .Default(false); 3690 } 3691 3692 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3693 unsigned &NumRecords) const { 3694 // FIXME: Implement! 3695 } 3696 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3697 return TargetInfo::VoidPtrBuiltinVaList; 3698 } 3699 virtual void getGCCRegNames(const char * const *&Names, 3700 unsigned &NumNames) const; 3701 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3702 unsigned &NumAliases) const; 3703 virtual bool validateAsmConstraint(const char *&Name, 3704 TargetInfo::ConstraintInfo &info) const { 3705 // FIXME: Implement! 3706 return false; 3707 } 3708 virtual const char *getClobbers() const { 3709 // FIXME: Implement! 3710 return ""; 3711 } 3712 }; 3713 3714 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3715 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3716 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3717 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3718 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3719 }; 3720 3721 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3722 unsigned &NumNames) const { 3723 Names = GCCRegNames; 3724 NumNames = llvm::array_lengthof(GCCRegNames); 3725 } 3726 3727 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3728 { { "g0" }, "r0" }, 3729 { { "g1" }, "r1" }, 3730 { { "g2" }, "r2" }, 3731 { { "g3" }, "r3" }, 3732 { { "g4" }, "r4" }, 3733 { { "g5" }, "r5" }, 3734 { { "g6" }, "r6" }, 3735 { { "g7" }, "r7" }, 3736 { { "o0" }, "r8" }, 3737 { { "o1" }, "r9" }, 3738 { { "o2" }, "r10" }, 3739 { { "o3" }, "r11" }, 3740 { { "o4" }, "r12" }, 3741 { { "o5" }, "r13" }, 3742 { { "o6", "sp" }, "r14" }, 3743 { { "o7" }, "r15" }, 3744 { { "l0" }, "r16" }, 3745 { { "l1" }, "r17" }, 3746 { { "l2" }, "r18" }, 3747 { { "l3" }, "r19" }, 3748 { { "l4" }, "r20" }, 3749 { { "l5" }, "r21" }, 3750 { { "l6" }, "r22" }, 3751 { { "l7" }, "r23" }, 3752 { { "i0" }, "r24" }, 3753 { { "i1" }, "r25" }, 3754 { { "i2" }, "r26" }, 3755 { { "i3" }, "r27" }, 3756 { { "i4" }, "r28" }, 3757 { { "i5" }, "r29" }, 3758 { { "i6", "fp" }, "r30" }, 3759 { { "i7" }, "r31" }, 3760 }; 3761 3762 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3763 unsigned &NumAliases) const { 3764 Aliases = GCCRegAliases; 3765 NumAliases = llvm::array_lengthof(GCCRegAliases); 3766 } 3767 } // end anonymous namespace. 3768 3769 namespace { 3770 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3771 public: 3772 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3773 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3774 SizeType = UnsignedInt; 3775 PtrDiffType = SignedInt; 3776 } 3777 }; 3778 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3779 public: 3780 SolarisSparcV8TargetInfo(const std::string& triple) : 3781 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3782 SizeType = UnsignedInt; 3783 PtrDiffType = SignedInt; 3784 } 3785 }; 3786 } // end anonymous namespace. 3787 3788 namespace { 3789 class MSP430TargetInfo : public TargetInfo { 3790 static const char * const GCCRegNames[]; 3791 public: 3792 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3793 BigEndian = false; 3794 TLSSupported = false; 3795 IntWidth = 16; IntAlign = 16; 3796 LongWidth = 32; LongLongWidth = 64; 3797 LongAlign = LongLongAlign = 16; 3798 PointerWidth = 16; PointerAlign = 16; 3799 SuitableAlign = 16; 3800 SizeType = UnsignedInt; 3801 IntMaxType = SignedLong; 3802 UIntMaxType = UnsignedLong; 3803 IntPtrType = SignedShort; 3804 PtrDiffType = SignedInt; 3805 SigAtomicType = SignedLong; 3806 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3807 } 3808 virtual void getTargetDefines(const LangOptions &Opts, 3809 MacroBuilder &Builder) const { 3810 Builder.defineMacro("MSP430"); 3811 Builder.defineMacro("__MSP430__"); 3812 // FIXME: defines for different 'flavours' of MCU 3813 } 3814 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3815 unsigned &NumRecords) const { 3816 // FIXME: Implement. 3817 Records = 0; 3818 NumRecords = 0; 3819 } 3820 virtual bool hasFeature(StringRef Feature) const { 3821 return Feature == "msp430"; 3822 } 3823 virtual void getGCCRegNames(const char * const *&Names, 3824 unsigned &NumNames) const; 3825 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3826 unsigned &NumAliases) const { 3827 // No aliases. 3828 Aliases = 0; 3829 NumAliases = 0; 3830 } 3831 virtual bool validateAsmConstraint(const char *&Name, 3832 TargetInfo::ConstraintInfo &info) const { 3833 // No target constraints for now. 3834 return false; 3835 } 3836 virtual const char *getClobbers() const { 3837 // FIXME: Is this really right? 3838 return ""; 3839 } 3840 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3841 // FIXME: implement 3842 return TargetInfo::CharPtrBuiltinVaList; 3843 } 3844 }; 3845 3846 const char * const MSP430TargetInfo::GCCRegNames[] = { 3847 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3848 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3849 }; 3850 3851 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3852 unsigned &NumNames) const { 3853 Names = GCCRegNames; 3854 NumNames = llvm::array_lengthof(GCCRegNames); 3855 } 3856 } 3857 3858 namespace { 3859 3860 // LLVM and Clang cannot be used directly to output native binaries for 3861 // target, but is used to compile C code to llvm bitcode with correct 3862 // type and alignment information. 3863 // 3864 // TCE uses the llvm bitcode as input and uses it for generating customized 3865 // target processor and program binary. TCE co-design environment is 3866 // publicly available in http://tce.cs.tut.fi 3867 3868 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3869 3, // opencl_global 3870 4, // opencl_local 3871 5, // opencl_constant 3872 0, // cuda_device 3873 0, // cuda_constant 3874 0 // cuda_shared 3875 }; 3876 3877 class TCETargetInfo : public TargetInfo{ 3878 public: 3879 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3880 TLSSupported = false; 3881 IntWidth = 32; 3882 LongWidth = LongLongWidth = 32; 3883 PointerWidth = 32; 3884 IntAlign = 32; 3885 LongAlign = LongLongAlign = 32; 3886 PointerAlign = 32; 3887 SuitableAlign = 32; 3888 SizeType = UnsignedInt; 3889 IntMaxType = SignedLong; 3890 UIntMaxType = UnsignedLong; 3891 IntPtrType = SignedInt; 3892 PtrDiffType = SignedInt; 3893 FloatWidth = 32; 3894 FloatAlign = 32; 3895 DoubleWidth = 32; 3896 DoubleAlign = 32; 3897 LongDoubleWidth = 32; 3898 LongDoubleAlign = 32; 3899 FloatFormat = &llvm::APFloat::IEEEsingle; 3900 DoubleFormat = &llvm::APFloat::IEEEsingle; 3901 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3902 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3903 "i16:16:32-i32:32:32-i64:32:32-" 3904 "f32:32:32-f64:32:32-v64:32:32-" 3905 "v128:32:32-a0:0:32-n32"; 3906 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3907 } 3908 3909 virtual void getTargetDefines(const LangOptions &Opts, 3910 MacroBuilder &Builder) const { 3911 DefineStd(Builder, "tce", Opts); 3912 Builder.defineMacro("__TCE__"); 3913 Builder.defineMacro("__TCE_V1__"); 3914 } 3915 virtual bool hasFeature(StringRef Feature) const { 3916 return Feature == "tce"; 3917 } 3918 3919 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3920 unsigned &NumRecords) const {} 3921 virtual const char *getClobbers() const { 3922 return ""; 3923 } 3924 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3925 return TargetInfo::VoidPtrBuiltinVaList; 3926 } 3927 virtual void getGCCRegNames(const char * const *&Names, 3928 unsigned &NumNames) const {} 3929 virtual bool validateAsmConstraint(const char *&Name, 3930 TargetInfo::ConstraintInfo &info) const { 3931 return true; 3932 } 3933 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3934 unsigned &NumAliases) const {} 3935 }; 3936 } 3937 3938 namespace { 3939 class MipsTargetInfoBase : public TargetInfo { 3940 static const Builtin::Info BuiltinInfo[]; 3941 std::string CPU; 3942 bool IsMips16; 3943 enum MipsFloatABI { 3944 HardFloat, SingleFloat, SoftFloat 3945 } FloatABI; 3946 enum DspRevEnum { 3947 NoDSP, DSP1, DSP2 3948 } DspRev; 3949 3950 protected: 3951 std::string ABI; 3952 3953 public: 3954 MipsTargetInfoBase(const std::string& triple, 3955 const std::string& ABIStr, 3956 const std::string& CPUStr) 3957 : TargetInfo(triple), 3958 CPU(CPUStr), 3959 IsMips16(false), 3960 FloatABI(HardFloat), 3961 DspRev(NoDSP), 3962 ABI(ABIStr) 3963 {} 3964 3965 virtual const char *getABI() const { return ABI.c_str(); } 3966 virtual bool setABI(const std::string &Name) = 0; 3967 virtual bool setCPU(const std::string &Name) { 3968 CPU = Name; 3969 return true; 3970 } 3971 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3972 Features[ABI] = true; 3973 Features[CPU] = true; 3974 } 3975 3976 virtual void getTargetDefines(const LangOptions &Opts, 3977 MacroBuilder &Builder) const { 3978 DefineStd(Builder, "mips", Opts); 3979 Builder.defineMacro("_mips"); 3980 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3981 3982 switch (FloatABI) { 3983 case HardFloat: 3984 Builder.defineMacro("__mips_hard_float", Twine(1)); 3985 break; 3986 case SingleFloat: 3987 Builder.defineMacro("__mips_hard_float", Twine(1)); 3988 Builder.defineMacro("__mips_single_float", Twine(1)); 3989 break; 3990 case SoftFloat: 3991 Builder.defineMacro("__mips_soft_float", Twine(1)); 3992 break; 3993 } 3994 3995 if (IsMips16) 3996 Builder.defineMacro("__mips16", Twine(1)); 3997 3998 switch (DspRev) { 3999 default: 4000 break; 4001 case DSP1: 4002 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4003 Builder.defineMacro("__mips_dsp", Twine(1)); 4004 break; 4005 case DSP2: 4006 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4007 Builder.defineMacro("__mips_dspr2", Twine(1)); 4008 Builder.defineMacro("__mips_dsp", Twine(1)); 4009 break; 4010 } 4011 4012 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4013 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4014 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4015 4016 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4017 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4018 } 4019 4020 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4021 unsigned &NumRecords) const { 4022 Records = BuiltinInfo; 4023 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4024 } 4025 virtual bool hasFeature(StringRef Feature) const { 4026 return Feature == "mips"; 4027 } 4028 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4029 return TargetInfo::VoidPtrBuiltinVaList; 4030 } 4031 virtual void getGCCRegNames(const char * const *&Names, 4032 unsigned &NumNames) const { 4033 static const char * const GCCRegNames[] = { 4034 // CPU register names 4035 // Must match second column of GCCRegAliases 4036 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4037 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4038 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4039 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4040 // Floating point register names 4041 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4042 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4043 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4044 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4045 // Hi/lo and condition register names 4046 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4047 "$fcc5","$fcc6","$fcc7" 4048 }; 4049 Names = GCCRegNames; 4050 NumNames = llvm::array_lengthof(GCCRegNames); 4051 } 4052 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4053 unsigned &NumAliases) const = 0; 4054 virtual bool validateAsmConstraint(const char *&Name, 4055 TargetInfo::ConstraintInfo &Info) const { 4056 switch (*Name) { 4057 default: 4058 return false; 4059 4060 case 'r': // CPU registers. 4061 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4062 case 'y': // Equivalent to "r", backwards compatibility only. 4063 case 'f': // floating-point registers. 4064 case 'c': // $25 for indirect jumps 4065 case 'l': // lo register 4066 case 'x': // hilo register pair 4067 Info.setAllowsRegister(); 4068 return true; 4069 } 4070 } 4071 4072 virtual const char *getClobbers() const { 4073 // FIXME: Implement! 4074 return ""; 4075 } 4076 4077 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 4078 StringRef Name, 4079 bool Enabled) const { 4080 if (Name == "soft-float" || Name == "single-float" || 4081 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 4082 Name == "mips32" || Name == "mips32r2" || 4083 Name == "mips64" || Name == "mips64r2" || 4084 Name == "mips16" || Name == "dsp" || Name == "dspr2") { 4085 Features[Name] = Enabled; 4086 return true; 4087 } 4088 return false; 4089 } 4090 4091 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 4092 IsMips16 = false; 4093 FloatABI = HardFloat; 4094 DspRev = NoDSP; 4095 4096 for (std::vector<std::string>::iterator it = Features.begin(), 4097 ie = Features.end(); it != ie; ++it) { 4098 if (*it == "+single-float") 4099 FloatABI = SingleFloat; 4100 else if (*it == "+soft-float") 4101 FloatABI = SoftFloat; 4102 else if (*it == "+mips16") 4103 IsMips16 = true; 4104 else if (*it == "+dsp") 4105 DspRev = std::max(DspRev, DSP1); 4106 else if (*it == "+dspr2") 4107 DspRev = std::max(DspRev, DSP2); 4108 } 4109 4110 // Remove front-end specific option. 4111 std::vector<std::string>::iterator it = 4112 std::find(Features.begin(), Features.end(), "+soft-float"); 4113 if (it != Features.end()) 4114 Features.erase(it); 4115 } 4116 }; 4117 4118 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 4119 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4120 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4121 ALL_LANGUAGES }, 4122 #include "clang/Basic/BuiltinsMips.def" 4123 }; 4124 4125 class Mips32TargetInfoBase : public MipsTargetInfoBase { 4126 public: 4127 Mips32TargetInfoBase(const std::string& triple) : 4128 MipsTargetInfoBase(triple, "o32", "mips32") { 4129 SizeType = UnsignedInt; 4130 PtrDiffType = SignedInt; 4131 } 4132 virtual bool setABI(const std::string &Name) { 4133 if ((Name == "o32") || (Name == "eabi")) { 4134 ABI = Name; 4135 return true; 4136 } else 4137 return false; 4138 } 4139 virtual void getTargetDefines(const LangOptions &Opts, 4140 MacroBuilder &Builder) const { 4141 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4142 4143 if (ABI == "o32") { 4144 Builder.defineMacro("__mips_o32"); 4145 Builder.defineMacro("_ABIO32", "1"); 4146 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 4147 } 4148 else if (ABI == "eabi") 4149 Builder.defineMacro("__mips_eabi"); 4150 else 4151 llvm_unreachable("Invalid ABI for Mips32."); 4152 } 4153 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4154 unsigned &NumAliases) const { 4155 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4156 { { "at" }, "$1" }, 4157 { { "v0" }, "$2" }, 4158 { { "v1" }, "$3" }, 4159 { { "a0" }, "$4" }, 4160 { { "a1" }, "$5" }, 4161 { { "a2" }, "$6" }, 4162 { { "a3" }, "$7" }, 4163 { { "t0" }, "$8" }, 4164 { { "t1" }, "$9" }, 4165 { { "t2" }, "$10" }, 4166 { { "t3" }, "$11" }, 4167 { { "t4" }, "$12" }, 4168 { { "t5" }, "$13" }, 4169 { { "t6" }, "$14" }, 4170 { { "t7" }, "$15" }, 4171 { { "s0" }, "$16" }, 4172 { { "s1" }, "$17" }, 4173 { { "s2" }, "$18" }, 4174 { { "s3" }, "$19" }, 4175 { { "s4" }, "$20" }, 4176 { { "s5" }, "$21" }, 4177 { { "s6" }, "$22" }, 4178 { { "s7" }, "$23" }, 4179 { { "t8" }, "$24" }, 4180 { { "t9" }, "$25" }, 4181 { { "k0" }, "$26" }, 4182 { { "k1" }, "$27" }, 4183 { { "gp" }, "$28" }, 4184 { { "sp","$sp" }, "$29" }, 4185 { { "fp","$fp" }, "$30" }, 4186 { { "ra" }, "$31" } 4187 }; 4188 Aliases = GCCRegAliases; 4189 NumAliases = llvm::array_lengthof(GCCRegAliases); 4190 } 4191 }; 4192 4193 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 4194 public: 4195 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4196 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4197 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4198 } 4199 virtual void getTargetDefines(const LangOptions &Opts, 4200 MacroBuilder &Builder) const { 4201 DefineStd(Builder, "MIPSEB", Opts); 4202 Builder.defineMacro("_MIPSEB"); 4203 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4204 } 4205 }; 4206 4207 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 4208 public: 4209 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4210 BigEndian = false; 4211 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4212 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4213 } 4214 virtual void getTargetDefines(const LangOptions &Opts, 4215 MacroBuilder &Builder) const { 4216 DefineStd(Builder, "MIPSEL", Opts); 4217 Builder.defineMacro("_MIPSEL"); 4218 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4219 } 4220 }; 4221 4222 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4223 virtual void SetDescriptionString(const std::string &Name) = 0; 4224 public: 4225 Mips64TargetInfoBase(const std::string& triple) : 4226 MipsTargetInfoBase(triple, "n64", "mips64") { 4227 LongWidth = LongAlign = 64; 4228 PointerWidth = PointerAlign = 64; 4229 LongDoubleWidth = LongDoubleAlign = 128; 4230 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4231 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 4232 LongDoubleWidth = LongDoubleAlign = 64; 4233 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4234 } 4235 SuitableAlign = 128; 4236 } 4237 virtual bool setABI(const std::string &Name) { 4238 SetDescriptionString(Name); 4239 4240 if (Name != "n32" && Name != "n64") 4241 return false; 4242 4243 ABI = Name; 4244 4245 if (Name == "n32") { 4246 LongWidth = LongAlign = 32; 4247 PointerWidth = PointerAlign = 32; 4248 } 4249 4250 return true; 4251 } 4252 virtual void getTargetDefines(const LangOptions &Opts, 4253 MacroBuilder &Builder) const { 4254 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4255 4256 Builder.defineMacro("__mips64"); 4257 Builder.defineMacro("__mips64__"); 4258 4259 if (ABI == "n32") { 4260 Builder.defineMacro("__mips_n32"); 4261 Builder.defineMacro("_ABIN32", "2"); 4262 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4263 } 4264 else if (ABI == "n64") { 4265 Builder.defineMacro("__mips_n64"); 4266 Builder.defineMacro("_ABI64", "3"); 4267 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4268 } 4269 else 4270 llvm_unreachable("Invalid ABI for Mips64."); 4271 } 4272 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4273 unsigned &NumAliases) const { 4274 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4275 { { "at" }, "$1" }, 4276 { { "v0" }, "$2" }, 4277 { { "v1" }, "$3" }, 4278 { { "a0" }, "$4" }, 4279 { { "a1" }, "$5" }, 4280 { { "a2" }, "$6" }, 4281 { { "a3" }, "$7" }, 4282 { { "a4" }, "$8" }, 4283 { { "a5" }, "$9" }, 4284 { { "a6" }, "$10" }, 4285 { { "a7" }, "$11" }, 4286 { { "t0" }, "$12" }, 4287 { { "t1" }, "$13" }, 4288 { { "t2" }, "$14" }, 4289 { { "t3" }, "$15" }, 4290 { { "s0" }, "$16" }, 4291 { { "s1" }, "$17" }, 4292 { { "s2" }, "$18" }, 4293 { { "s3" }, "$19" }, 4294 { { "s4" }, "$20" }, 4295 { { "s5" }, "$21" }, 4296 { { "s6" }, "$22" }, 4297 { { "s7" }, "$23" }, 4298 { { "t8" }, "$24" }, 4299 { { "t9" }, "$25" }, 4300 { { "k0" }, "$26" }, 4301 { { "k1" }, "$27" }, 4302 { { "gp" }, "$28" }, 4303 { { "sp","$sp" }, "$29" }, 4304 { { "fp","$fp" }, "$30" }, 4305 { { "ra" }, "$31" } 4306 }; 4307 Aliases = GCCRegAliases; 4308 NumAliases = llvm::array_lengthof(GCCRegAliases); 4309 } 4310 }; 4311 4312 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 4313 virtual void SetDescriptionString(const std::string &Name) { 4314 // Change DescriptionString only if ABI is n32. 4315 if (Name == "n32") 4316 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4317 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4318 "v64:64:64-n32:64-S128"; 4319 } 4320 public: 4321 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4322 // Default ABI is n64. 4323 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4324 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4325 "v64:64:64-n32:64-S128"; 4326 } 4327 virtual void getTargetDefines(const LangOptions &Opts, 4328 MacroBuilder &Builder) const { 4329 DefineStd(Builder, "MIPSEB", Opts); 4330 Builder.defineMacro("_MIPSEB"); 4331 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4332 } 4333 }; 4334 4335 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4336 virtual void SetDescriptionString(const std::string &Name) { 4337 // Change DescriptionString only if ABI is n32. 4338 if (Name == "n32") 4339 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4340 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4341 "-v64:64:64-n32:64-S128"; 4342 } 4343 public: 4344 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4345 // Default ABI is n64. 4346 BigEndian = false; 4347 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4348 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4349 "v64:64:64-n32:64-S128"; 4350 } 4351 virtual void getTargetDefines(const LangOptions &Opts, 4352 MacroBuilder &Builder) const { 4353 DefineStd(Builder, "MIPSEL", Opts); 4354 Builder.defineMacro("_MIPSEL"); 4355 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4356 } 4357 }; 4358 } // end anonymous namespace. 4359 4360 namespace { 4361 class PNaClTargetInfo : public TargetInfo { 4362 public: 4363 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 4364 BigEndian = false; 4365 this->UserLabelPrefix = ""; 4366 this->LongAlign = 32; 4367 this->LongWidth = 32; 4368 this->PointerAlign = 32; 4369 this->PointerWidth = 32; 4370 this->IntMaxType = TargetInfo::SignedLongLong; 4371 this->UIntMaxType = TargetInfo::UnsignedLongLong; 4372 this->Int64Type = TargetInfo::SignedLongLong; 4373 this->DoubleAlign = 64; 4374 this->LongDoubleWidth = 64; 4375 this->LongDoubleAlign = 64; 4376 this->SizeType = TargetInfo::UnsignedInt; 4377 this->PtrDiffType = TargetInfo::SignedInt; 4378 this->IntPtrType = TargetInfo::SignedInt; 4379 this->RegParmMax = 2; 4380 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4381 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 4382 } 4383 4384 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4385 } 4386 virtual void getArchDefines(const LangOptions &Opts, 4387 MacroBuilder &Builder) const { 4388 Builder.defineMacro("__le32__"); 4389 Builder.defineMacro("__pnacl__"); 4390 } 4391 virtual void getTargetDefines(const LangOptions &Opts, 4392 MacroBuilder &Builder) const { 4393 Builder.defineMacro("__LITTLE_ENDIAN__"); 4394 getArchDefines(Opts, Builder); 4395 } 4396 virtual bool hasFeature(StringRef Feature) const { 4397 return Feature == "pnacl"; 4398 } 4399 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4400 unsigned &NumRecords) const { 4401 } 4402 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4403 return TargetInfo::PNaClABIBuiltinVaList; 4404 } 4405 virtual void getGCCRegNames(const char * const *&Names, 4406 unsigned &NumNames) const; 4407 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4408 unsigned &NumAliases) const; 4409 virtual bool validateAsmConstraint(const char *&Name, 4410 TargetInfo::ConstraintInfo &Info) const { 4411 return false; 4412 } 4413 4414 virtual const char *getClobbers() const { 4415 return ""; 4416 } 4417 }; 4418 4419 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 4420 unsigned &NumNames) const { 4421 Names = NULL; 4422 NumNames = 0; 4423 } 4424 4425 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4426 unsigned &NumAliases) const { 4427 Aliases = NULL; 4428 NumAliases = 0; 4429 } 4430 } // end anonymous namespace. 4431 4432 namespace { 4433 static const unsigned SPIRAddrSpaceMap[] = { 4434 1, // opencl_global 4435 3, // opencl_local 4436 2, // opencl_constant 4437 0, // cuda_device 4438 0, // cuda_constant 4439 0 // cuda_shared 4440 }; 4441 class SPIRTargetInfo : public TargetInfo { 4442 static const char * const GCCRegNames[]; 4443 static const Builtin::Info BuiltinInfo[]; 4444 std::vector<llvm::StringRef> AvailableFeatures; 4445 public: 4446 SPIRTargetInfo(const std::string& triple) : TargetInfo(triple) { 4447 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 4448 "SPIR target must use unknown OS"); 4449 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 4450 "SPIR target must use unknown environment type"); 4451 BigEndian = false; 4452 TLSSupported = false; 4453 LongWidth = LongAlign = 64; 4454 AddrSpaceMap = &SPIRAddrSpaceMap; 4455 // Define available target features 4456 // These must be defined in sorted order! 4457 NoAsmVariants = true; 4458 } 4459 virtual void getTargetDefines(const LangOptions &Opts, 4460 MacroBuilder &Builder) const { 4461 DefineStd(Builder, "SPIR", Opts); 4462 } 4463 virtual bool hasFeature(StringRef Feature) const { 4464 return Feature == "spir"; 4465 } 4466 4467 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4468 unsigned &NumRecords) const {} 4469 virtual const char *getClobbers() const { 4470 return ""; 4471 } 4472 virtual void getGCCRegNames(const char * const *&Names, 4473 unsigned &NumNames) const {} 4474 virtual bool validateAsmConstraint(const char *&Name, 4475 TargetInfo::ConstraintInfo &info) const { 4476 return true; 4477 } 4478 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4479 unsigned &NumAliases) const {} 4480 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4481 return TargetInfo::VoidPtrBuiltinVaList; 4482 } 4483 }; 4484 4485 4486 class SPIR32TargetInfo : public SPIRTargetInfo { 4487 public: 4488 SPIR32TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) { 4489 PointerWidth = PointerAlign = 32; 4490 SizeType = TargetInfo::UnsignedInt; 4491 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 4492 DescriptionString 4493 = "p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4494 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 4495 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 4496 "v512:512:512-v1024:1024:1024"; 4497 } 4498 }; 4499 4500 class SPIR64TargetInfo : public SPIRTargetInfo { 4501 public: 4502 SPIR64TargetInfo(const std::string& triple) : SPIRTargetInfo(triple) { 4503 PointerWidth = PointerAlign = 64; 4504 SizeType = TargetInfo::UnsignedLong; 4505 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 4506 DescriptionString 4507 = "p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4508 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 4509 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 4510 "v512:512:512-v1024:1024:1024"; 4511 } 4512 }; 4513 } 4514 4515 4516 //===----------------------------------------------------------------------===// 4517 // Driver code 4518 //===----------------------------------------------------------------------===// 4519 4520 static TargetInfo *AllocateTarget(const std::string &T) { 4521 llvm::Triple Triple(T); 4522 llvm::Triple::OSType os = Triple.getOS(); 4523 4524 switch (Triple.getArch()) { 4525 default: 4526 return NULL; 4527 4528 case llvm::Triple::hexagon: 4529 return new HexagonTargetInfo(T); 4530 4531 case llvm::Triple::arm: 4532 case llvm::Triple::thumb: 4533 if (Triple.isOSDarwin()) 4534 return new DarwinARMTargetInfo(T); 4535 4536 switch (os) { 4537 case llvm::Triple::Linux: 4538 return new LinuxTargetInfo<ARMTargetInfo>(T); 4539 case llvm::Triple::FreeBSD: 4540 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 4541 case llvm::Triple::NetBSD: 4542 return new NetBSDTargetInfo<ARMTargetInfo>(T); 4543 case llvm::Triple::OpenBSD: 4544 return new OpenBSDTargetInfo<ARMTargetInfo>(T); 4545 case llvm::Triple::Bitrig: 4546 return new BitrigTargetInfo<ARMTargetInfo>(T); 4547 case llvm::Triple::RTEMS: 4548 return new RTEMSTargetInfo<ARMTargetInfo>(T); 4549 case llvm::Triple::NaCl: 4550 return new NaClTargetInfo<ARMTargetInfo>(T); 4551 default: 4552 return new ARMTargetInfo(T); 4553 } 4554 4555 case llvm::Triple::msp430: 4556 return new MSP430TargetInfo(T); 4557 4558 case llvm::Triple::mips: 4559 switch (os) { 4560 case llvm::Triple::Linux: 4561 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 4562 case llvm::Triple::RTEMS: 4563 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 4564 case llvm::Triple::FreeBSD: 4565 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 4566 case llvm::Triple::NetBSD: 4567 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 4568 default: 4569 return new Mips32EBTargetInfo(T); 4570 } 4571 4572 case llvm::Triple::mipsel: 4573 switch (os) { 4574 case llvm::Triple::Linux: 4575 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 4576 case llvm::Triple::RTEMS: 4577 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 4578 case llvm::Triple::FreeBSD: 4579 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 4580 case llvm::Triple::NetBSD: 4581 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 4582 default: 4583 return new Mips32ELTargetInfo(T); 4584 } 4585 4586 case llvm::Triple::mips64: 4587 switch (os) { 4588 case llvm::Triple::Linux: 4589 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 4590 case llvm::Triple::RTEMS: 4591 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 4592 case llvm::Triple::FreeBSD: 4593 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 4594 case llvm::Triple::NetBSD: 4595 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 4596 case llvm::Triple::OpenBSD: 4597 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T); 4598 default: 4599 return new Mips64EBTargetInfo(T); 4600 } 4601 4602 case llvm::Triple::mips64el: 4603 switch (os) { 4604 case llvm::Triple::Linux: 4605 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 4606 case llvm::Triple::RTEMS: 4607 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 4608 case llvm::Triple::FreeBSD: 4609 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 4610 case llvm::Triple::NetBSD: 4611 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 4612 case llvm::Triple::OpenBSD: 4613 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T); 4614 default: 4615 return new Mips64ELTargetInfo(T); 4616 } 4617 4618 case llvm::Triple::le32: 4619 switch (os) { 4620 case llvm::Triple::NaCl: 4621 return new NaClTargetInfo<PNaClTargetInfo>(T); 4622 default: 4623 return NULL; 4624 } 4625 4626 case llvm::Triple::ppc: 4627 if (Triple.isOSDarwin()) 4628 return new DarwinPPC32TargetInfo(T); 4629 switch (os) { 4630 case llvm::Triple::Linux: 4631 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4632 case llvm::Triple::FreeBSD: 4633 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4634 case llvm::Triple::NetBSD: 4635 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4636 case llvm::Triple::OpenBSD: 4637 return new OpenBSDTargetInfo<PPC32TargetInfo>(T); 4638 case llvm::Triple::RTEMS: 4639 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4640 default: 4641 return new PPC32TargetInfo(T); 4642 } 4643 4644 case llvm::Triple::ppc64: 4645 if (Triple.isOSDarwin()) 4646 return new DarwinPPC64TargetInfo(T); 4647 switch (os) { 4648 case llvm::Triple::Linux: 4649 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4650 case llvm::Triple::Lv2: 4651 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4652 case llvm::Triple::FreeBSD: 4653 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4654 case llvm::Triple::NetBSD: 4655 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4656 default: 4657 return new PPC64TargetInfo(T); 4658 } 4659 4660 case llvm::Triple::nvptx: 4661 return new NVPTX32TargetInfo(T); 4662 case llvm::Triple::nvptx64: 4663 return new NVPTX64TargetInfo(T); 4664 4665 case llvm::Triple::mblaze: 4666 return new MBlazeTargetInfo(T); 4667 4668 case llvm::Triple::r600: 4669 return new R600TargetInfo(T); 4670 4671 case llvm::Triple::sparc: 4672 switch (os) { 4673 case llvm::Triple::Linux: 4674 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4675 case llvm::Triple::AuroraUX: 4676 return new AuroraUXSparcV8TargetInfo(T); 4677 case llvm::Triple::Solaris: 4678 return new SolarisSparcV8TargetInfo(T); 4679 case llvm::Triple::NetBSD: 4680 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4681 case llvm::Triple::OpenBSD: 4682 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T); 4683 case llvm::Triple::RTEMS: 4684 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4685 default: 4686 return new SparcV8TargetInfo(T); 4687 } 4688 4689 case llvm::Triple::tce: 4690 return new TCETargetInfo(T); 4691 4692 case llvm::Triple::x86: 4693 if (Triple.isOSDarwin()) 4694 return new DarwinI386TargetInfo(T); 4695 4696 switch (os) { 4697 case llvm::Triple::AuroraUX: 4698 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4699 case llvm::Triple::Linux: 4700 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4701 case llvm::Triple::DragonFly: 4702 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4703 case llvm::Triple::NetBSD: 4704 return new NetBSDI386TargetInfo(T); 4705 case llvm::Triple::OpenBSD: 4706 return new OpenBSDI386TargetInfo(T); 4707 case llvm::Triple::Bitrig: 4708 return new BitrigI386TargetInfo(T); 4709 case llvm::Triple::FreeBSD: 4710 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4711 case llvm::Triple::Minix: 4712 return new MinixTargetInfo<X86_32TargetInfo>(T); 4713 case llvm::Triple::Solaris: 4714 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4715 case llvm::Triple::Cygwin: 4716 return new CygwinX86_32TargetInfo(T); 4717 case llvm::Triple::MinGW32: 4718 return new MinGWX86_32TargetInfo(T); 4719 case llvm::Triple::Win32: 4720 return new VisualStudioWindowsX86_32TargetInfo(T); 4721 case llvm::Triple::Haiku: 4722 return new HaikuX86_32TargetInfo(T); 4723 case llvm::Triple::RTEMS: 4724 return new RTEMSX86_32TargetInfo(T); 4725 case llvm::Triple::NaCl: 4726 return new NaClTargetInfo<X86_32TargetInfo>(T); 4727 default: 4728 return new X86_32TargetInfo(T); 4729 } 4730 4731 case llvm::Triple::x86_64: 4732 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4733 return new DarwinX86_64TargetInfo(T); 4734 4735 switch (os) { 4736 case llvm::Triple::AuroraUX: 4737 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4738 case llvm::Triple::Linux: 4739 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4740 case llvm::Triple::DragonFly: 4741 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4742 case llvm::Triple::NetBSD: 4743 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4744 case llvm::Triple::OpenBSD: 4745 return new OpenBSDX86_64TargetInfo(T); 4746 case llvm::Triple::Bitrig: 4747 return new BitrigX86_64TargetInfo(T); 4748 case llvm::Triple::FreeBSD: 4749 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4750 case llvm::Triple::Solaris: 4751 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4752 case llvm::Triple::MinGW32: 4753 return new MinGWX86_64TargetInfo(T); 4754 case llvm::Triple::Win32: // This is what Triple.h supports now. 4755 return new VisualStudioWindowsX86_64TargetInfo(T); 4756 case llvm::Triple::NaCl: 4757 return new NaClTargetInfo<X86_64TargetInfo>(T); 4758 default: 4759 return new X86_64TargetInfo(T); 4760 } 4761 4762 case llvm::Triple::spir: { 4763 llvm::Triple Triple(T); 4764 if (Triple.getOS() != llvm::Triple::UnknownOS || 4765 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 4766 return NULL; 4767 return new SPIR32TargetInfo(T); 4768 } 4769 case llvm::Triple::spir64: { 4770 llvm::Triple Triple(T); 4771 if (Triple.getOS() != llvm::Triple::UnknownOS || 4772 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 4773 return NULL; 4774 return new SPIR64TargetInfo(T); 4775 } 4776 } 4777 } 4778 4779 /// CreateTargetInfo - Return the target info object for the specified target 4780 /// triple. 4781 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4782 TargetOptions *Opts) { 4783 llvm::Triple Triple(Opts->Triple); 4784 4785 // Construct the target 4786 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4787 if (!Target) { 4788 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4789 return 0; 4790 } 4791 Target->setTargetOpts(Opts); 4792 4793 // Set the target CPU if specified. 4794 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 4795 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 4796 return 0; 4797 } 4798 4799 // Set the target ABI if specified. 4800 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 4801 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 4802 return 0; 4803 } 4804 4805 // Set the target C++ ABI. 4806 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 4807 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 4808 return 0; 4809 } 4810 4811 // Compute the default target features, we need the target to handle this 4812 // because features may have dependencies on one another. 4813 llvm::StringMap<bool> Features; 4814 Target->getDefaultFeatures(Features); 4815 4816 // Apply the user specified deltas. 4817 // First the enables. 4818 for (std::vector<std::string>::const_iterator 4819 it = Opts->FeaturesAsWritten.begin(), 4820 ie = Opts->FeaturesAsWritten.end(); 4821 it != ie; ++it) { 4822 const char *Name = it->c_str(); 4823 4824 if (Name[0] != '+') 4825 continue; 4826 4827 // Apply the feature via the target. 4828 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4829 Diags.Report(diag::err_target_invalid_feature) << Name; 4830 return 0; 4831 } 4832 } 4833 4834 // Then the disables. 4835 for (std::vector<std::string>::const_iterator 4836 it = Opts->FeaturesAsWritten.begin(), 4837 ie = Opts->FeaturesAsWritten.end(); 4838 it != ie; ++it) { 4839 const char *Name = it->c_str(); 4840 4841 if (Name[0] == '+') 4842 continue; 4843 4844 // Apply the feature via the target. 4845 if (Name[0] != '-' || 4846 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4847 Diags.Report(diag::err_target_invalid_feature) << Name; 4848 return 0; 4849 } 4850 } 4851 4852 // Add the features to the compile options. 4853 // 4854 // FIXME: If we are completely confident that we have the right set, we only 4855 // need to pass the minuses. 4856 Opts->Features.clear(); 4857 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4858 ie = Features.end(); it != ie; ++it) 4859 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 4860 Target->HandleTargetFeatures(Opts->Features); 4861 4862 return Target.take(); 4863 } 4864