1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Type.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 96 if (!Opts.ObjCAutoRefCount) { 97 // __weak is always defined, for use in blocks and with objc pointers. 98 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 99 100 // Darwin defines __strong even in C mode (just to nothing). 101 if (Opts.getGC() != LangOptions::NonGC) 102 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 103 else 104 Builder.defineMacro("__strong", ""); 105 106 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 107 // allow this in C, since one might have block pointers in structs that 108 // are used in pure C code and in Objective-C ARC. 109 Builder.defineMacro("__unsafe_unretained", ""); 110 } 111 112 if (Opts.Static) 113 Builder.defineMacro("__STATIC__"); 114 else 115 Builder.defineMacro("__DYNAMIC__"); 116 117 if (Opts.POSIXThreads) 118 Builder.defineMacro("_REENTRANT"); 119 120 // Get the platform type and version number from the triple. 121 unsigned Maj, Min, Rev; 122 if (Triple.isMacOSX()) { 123 Triple.getMacOSXVersion(Maj, Min, Rev); 124 PlatformName = "macosx"; 125 } else { 126 Triple.getOSVersion(Maj, Min, Rev); 127 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 128 } 129 130 // If -target arch-pc-win32-macho option specified, we're 131 // generating code for Win32 ABI. No need to emit 132 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 133 if (PlatformName == "win32") { 134 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 135 return; 136 } 137 138 // Set the appropriate OS version define. 139 if (Triple.getOS() == llvm::Triple::IOS) { 140 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 141 char Str[6]; 142 Str[0] = '0' + Maj; 143 Str[1] = '0' + (Min / 10); 144 Str[2] = '0' + (Min % 10); 145 Str[3] = '0' + (Rev / 10); 146 Str[4] = '0' + (Rev % 10); 147 Str[5] = '\0'; 148 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 149 } else { 150 // Note that the Driver allows versions which aren't representable in the 151 // define (because we only get a single digit for the minor and micro 152 // revision numbers). So, we limit them to the maximum representable 153 // version. 154 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 155 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 156 char Str[5]; 157 Str[0] = '0' + (Maj / 10); 158 Str[1] = '0' + (Maj % 10); 159 Str[2] = '0' + std::min(Min, 9U); 160 Str[3] = '0' + std::min(Rev, 9U); 161 Str[4] = '\0'; 162 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 163 } 164 165 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 166 } 167 168 namespace { 169 template<typename Target> 170 class DarwinTargetInfo : public OSTargetInfo<Target> { 171 protected: 172 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 173 MacroBuilder &Builder) const { 174 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 175 this->PlatformMinVersion); 176 } 177 178 public: 179 DarwinTargetInfo(const std::string& triple) : 180 OSTargetInfo<Target>(triple) { 181 llvm::Triple T = llvm::Triple(triple); 182 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 183 this->MCountName = "\01mcount"; 184 } 185 186 virtual std::string isValidSectionSpecifier(StringRef SR) const { 187 // Let MCSectionMachO validate this. 188 StringRef Segment, Section; 189 unsigned TAA, StubSize; 190 bool HasTAA; 191 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 192 TAA, HasTAA, StubSize); 193 } 194 195 virtual const char *getStaticInitSectionSpecifier() const { 196 // FIXME: We should return 0 when building kexts. 197 return "__TEXT,__StaticInit,regular,pure_instructions"; 198 } 199 200 /// Darwin does not support protected visibility. Darwin's "default" 201 /// is very similar to ELF's "protected"; Darwin requires a "weak" 202 /// attribute on declarations that can be dynamically replaced. 203 virtual bool hasProtectedVisibility() const { 204 return false; 205 } 206 }; 207 208 209 // DragonFlyBSD Target 210 template<typename Target> 211 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const { 215 // DragonFly defines; list based off of gcc output 216 Builder.defineMacro("__DragonFly__"); 217 Builder.defineMacro("__DragonFly_cc_version", "100001"); 218 Builder.defineMacro("__ELF__"); 219 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 220 Builder.defineMacro("__tune_i386__"); 221 DefineStd(Builder, "unix", Opts); 222 } 223 public: 224 DragonFlyBSDTargetInfo(const std::string &triple) 225 : OSTargetInfo<Target>(triple) { 226 this->UserLabelPrefix = ""; 227 228 llvm::Triple Triple(triple); 229 switch (Triple.getArch()) { 230 default: 231 case llvm::Triple::x86: 232 case llvm::Triple::x86_64: 233 this->MCountName = ".mcount"; 234 break; 235 } 236 } 237 }; 238 239 // FreeBSD Target 240 template<typename Target> 241 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 242 protected: 243 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 244 MacroBuilder &Builder) const { 245 // FreeBSD defines; list based off of gcc output 246 247 unsigned Release = Triple.getOSMajorVersion(); 248 if (Release == 0U) 249 Release = 8; 250 251 Builder.defineMacro("__FreeBSD__", Twine(Release)); 252 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 253 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 254 DefineStd(Builder, "unix", Opts); 255 Builder.defineMacro("__ELF__"); 256 } 257 public: 258 FreeBSDTargetInfo(const std::string &triple) 259 : OSTargetInfo<Target>(triple) { 260 this->UserLabelPrefix = ""; 261 262 llvm::Triple Triple(triple); 263 switch (Triple.getArch()) { 264 default: 265 case llvm::Triple::x86: 266 case llvm::Triple::x86_64: 267 this->MCountName = ".mcount"; 268 break; 269 case llvm::Triple::mips: 270 case llvm::Triple::mipsel: 271 case llvm::Triple::ppc: 272 case llvm::Triple::ppc64: 273 this->MCountName = "_mcount"; 274 break; 275 case llvm::Triple::arm: 276 this->MCountName = "__mcount"; 277 break; 278 } 279 280 } 281 }; 282 283 // Minix Target 284 template<typename Target> 285 class MinixTargetInfo : public OSTargetInfo<Target> { 286 protected: 287 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 288 MacroBuilder &Builder) const { 289 // Minix defines 290 291 Builder.defineMacro("__minix", "3"); 292 Builder.defineMacro("_EM_WSIZE", "4"); 293 Builder.defineMacro("_EM_PSIZE", "4"); 294 Builder.defineMacro("_EM_SSIZE", "2"); 295 Builder.defineMacro("_EM_LSIZE", "4"); 296 Builder.defineMacro("_EM_FSIZE", "4"); 297 Builder.defineMacro("_EM_DSIZE", "8"); 298 Builder.defineMacro("__ELF__"); 299 DefineStd(Builder, "unix", Opts); 300 } 301 public: 302 MinixTargetInfo(const std::string &triple) 303 : OSTargetInfo<Target>(triple) { 304 this->UserLabelPrefix = ""; 305 } 306 }; 307 308 // Linux target 309 template<typename Target> 310 class LinuxTargetInfo : public OSTargetInfo<Target> { 311 protected: 312 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 313 MacroBuilder &Builder) const { 314 // Linux defines; list based off of gcc output 315 DefineStd(Builder, "unix", Opts); 316 DefineStd(Builder, "linux", Opts); 317 Builder.defineMacro("__gnu_linux__"); 318 Builder.defineMacro("__ELF__"); 319 if (Triple.getEnvironment() == llvm::Triple::ANDROIDEABI) 320 Builder.defineMacro("__ANDROID__", "1"); 321 if (Opts.POSIXThreads) 322 Builder.defineMacro("_REENTRANT"); 323 if (Opts.CPlusPlus) 324 Builder.defineMacro("_GNU_SOURCE"); 325 } 326 public: 327 LinuxTargetInfo(const std::string& triple) 328 : OSTargetInfo<Target>(triple) { 329 this->UserLabelPrefix = ""; 330 this->WIntType = TargetInfo::UnsignedInt; 331 } 332 333 virtual const char *getStaticInitSectionSpecifier() const { 334 return ".text.startup"; 335 } 336 }; 337 338 // NetBSD Target 339 template<typename Target> 340 class NetBSDTargetInfo : public OSTargetInfo<Target> { 341 protected: 342 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 343 MacroBuilder &Builder) const { 344 // NetBSD defines; list based off of gcc output 345 Builder.defineMacro("__NetBSD__"); 346 Builder.defineMacro("__unix__"); 347 Builder.defineMacro("__ELF__"); 348 if (Opts.POSIXThreads) 349 Builder.defineMacro("_POSIX_THREADS"); 350 } 351 public: 352 NetBSDTargetInfo(const std::string &triple) 353 : OSTargetInfo<Target>(triple) { 354 this->UserLabelPrefix = ""; 355 } 356 }; 357 358 // OpenBSD Target 359 template<typename Target> 360 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 361 protected: 362 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 363 MacroBuilder &Builder) const { 364 // OpenBSD defines; list based off of gcc output 365 366 Builder.defineMacro("__OpenBSD__"); 367 DefineStd(Builder, "unix", Opts); 368 Builder.defineMacro("__ELF__"); 369 if (Opts.POSIXThreads) 370 Builder.defineMacro("_REENTRANT"); 371 } 372 public: 373 OpenBSDTargetInfo(const std::string &triple) 374 : OSTargetInfo<Target>(triple) { 375 this->UserLabelPrefix = ""; 376 377 llvm::Triple Triple(triple); 378 switch (Triple.getArch()) { 379 default: 380 case llvm::Triple::x86: 381 case llvm::Triple::x86_64: 382 case llvm::Triple::arm: 383 case llvm::Triple::sparc: 384 this->MCountName = "__mcount"; 385 break; 386 case llvm::Triple::mips64: 387 case llvm::Triple::mips64el: 388 case llvm::Triple::ppc: 389 case llvm::Triple::sparcv9: 390 this->MCountName = "_mcount"; 391 break; 392 } 393 } 394 }; 395 396 // PSP Target 397 template<typename Target> 398 class PSPTargetInfo : public OSTargetInfo<Target> { 399 protected: 400 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 401 MacroBuilder &Builder) const { 402 // PSP defines; list based on the output of the pspdev gcc toolchain. 403 Builder.defineMacro("PSP"); 404 Builder.defineMacro("_PSP"); 405 Builder.defineMacro("__psp__"); 406 Builder.defineMacro("__ELF__"); 407 } 408 public: 409 PSPTargetInfo(const std::string& triple) 410 : OSTargetInfo<Target>(triple) { 411 this->UserLabelPrefix = ""; 412 } 413 }; 414 415 // PS3 PPU Target 416 template<typename Target> 417 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const { 421 // PS3 PPU defines. 422 Builder.defineMacro("__PPC__"); 423 Builder.defineMacro("__PPU__"); 424 Builder.defineMacro("__CELLOS_LV2__"); 425 Builder.defineMacro("__ELF__"); 426 Builder.defineMacro("__LP32__"); 427 Builder.defineMacro("_ARCH_PPC64"); 428 Builder.defineMacro("__powerpc64__"); 429 } 430 public: 431 PS3PPUTargetInfo(const std::string& triple) 432 : OSTargetInfo<Target>(triple) { 433 this->UserLabelPrefix = ""; 434 this->LongWidth = this->LongAlign = 32; 435 this->PointerWidth = this->PointerAlign = 32; 436 this->IntMaxType = TargetInfo::SignedLongLong; 437 this->UIntMaxType = TargetInfo::UnsignedLongLong; 438 this->Int64Type = TargetInfo::SignedLongLong; 439 this->SizeType = TargetInfo::UnsignedInt; 440 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 441 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 442 } 443 }; 444 445 // FIXME: Need a real SPU target. 446 // PS3 SPU Target 447 template<typename Target> 448 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 449 protected: 450 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 451 MacroBuilder &Builder) const { 452 // PS3 PPU defines. 453 Builder.defineMacro("__SPU__"); 454 Builder.defineMacro("__ELF__"); 455 } 456 public: 457 PS3SPUTargetInfo(const std::string& triple) 458 : OSTargetInfo<Target>(triple) { 459 this->UserLabelPrefix = ""; 460 } 461 }; 462 463 // AuroraUX target 464 template<typename Target> 465 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 466 protected: 467 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 468 MacroBuilder &Builder) const { 469 DefineStd(Builder, "sun", Opts); 470 DefineStd(Builder, "unix", Opts); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__svr4__"); 473 Builder.defineMacro("__SVR4"); 474 } 475 public: 476 AuroraUXTargetInfo(const std::string& triple) 477 : OSTargetInfo<Target>(triple) { 478 this->UserLabelPrefix = ""; 479 this->WCharType = this->SignedLong; 480 // FIXME: WIntType should be SignedLong 481 } 482 }; 483 484 // Solaris target 485 template<typename Target> 486 class SolarisTargetInfo : public OSTargetInfo<Target> { 487 protected: 488 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 489 MacroBuilder &Builder) const { 490 DefineStd(Builder, "sun", Opts); 491 DefineStd(Builder, "unix", Opts); 492 Builder.defineMacro("__ELF__"); 493 Builder.defineMacro("__svr4__"); 494 Builder.defineMacro("__SVR4"); 495 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 496 // newer, but to 500 for everything else. feature_test.h has a check to 497 // ensure that you are not using C99 with an old version of X/Open or C89 498 // with a new version. 499 if (Opts.C99 || Opts.C11) 500 Builder.defineMacro("_XOPEN_SOURCE", "600"); 501 else 502 Builder.defineMacro("_XOPEN_SOURCE", "500"); 503 if (Opts.CPlusPlus) 504 Builder.defineMacro("__C99FEATURES__"); 505 Builder.defineMacro("_LARGEFILE_SOURCE"); 506 Builder.defineMacro("_LARGEFILE64_SOURCE"); 507 Builder.defineMacro("__EXTENSIONS__"); 508 Builder.defineMacro("_REENTRANT"); 509 } 510 public: 511 SolarisTargetInfo(const std::string& triple) 512 : OSTargetInfo<Target>(triple) { 513 this->UserLabelPrefix = ""; 514 this->WCharType = this->SignedInt; 515 // FIXME: WIntType should be SignedLong 516 } 517 }; 518 519 // Windows target 520 template<typename Target> 521 class WindowsTargetInfo : public OSTargetInfo<Target> { 522 protected: 523 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 524 MacroBuilder &Builder) const { 525 Builder.defineMacro("_WIN32"); 526 } 527 void getVisualStudioDefines(const LangOptions &Opts, 528 MacroBuilder &Builder) const { 529 if (Opts.CPlusPlus) { 530 if (Opts.RTTI) 531 Builder.defineMacro("_CPPRTTI"); 532 533 if (Opts.Exceptions) 534 Builder.defineMacro("_CPPUNWIND"); 535 } 536 537 if (!Opts.CharIsSigned) 538 Builder.defineMacro("_CHAR_UNSIGNED"); 539 540 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 541 // but it works for now. 542 if (Opts.POSIXThreads) 543 Builder.defineMacro("_MT"); 544 545 if (Opts.MSCVersion != 0) 546 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 547 548 if (Opts.MicrosoftExt) { 549 Builder.defineMacro("_MSC_EXTENSIONS"); 550 551 if (Opts.CPlusPlus0x) { 552 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 553 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 554 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 555 } 556 } 557 558 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 559 } 560 561 public: 562 WindowsTargetInfo(const std::string &triple) 563 : OSTargetInfo<Target>(triple) {} 564 }; 565 566 } // end anonymous namespace. 567 568 //===----------------------------------------------------------------------===// 569 // Specific target implementations. 570 //===----------------------------------------------------------------------===// 571 572 namespace { 573 // PPC abstract base class 574 class PPCTargetInfo : public TargetInfo { 575 static const Builtin::Info BuiltinInfo[]; 576 static const char * const GCCRegNames[]; 577 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 578 std::string CPU; 579 public: 580 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 581 LongDoubleWidth = LongDoubleAlign = 128; 582 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 583 } 584 585 virtual bool setCPU(const std::string &Name) { 586 bool CPUKnown = llvm::StringSwitch<bool>(Name) 587 .Case("generic", true) 588 .Case("440", true) 589 .Case("450", true) 590 .Case("601", true) 591 .Case("602", true) 592 .Case("603", true) 593 .Case("603e", true) 594 .Case("603ev", true) 595 .Case("604", true) 596 .Case("604e", true) 597 .Case("620", true) 598 .Case("g3", true) 599 .Case("7400", true) 600 .Case("g4", true) 601 .Case("7450", true) 602 .Case("g4+", true) 603 .Case("750", true) 604 .Case("970", true) 605 .Case("g5", true) 606 .Case("a2", true) 607 .Case("pwr6", true) 608 .Case("pwr7", true) 609 .Case("ppc", true) 610 .Case("ppc64", true) 611 .Default(false); 612 613 if (CPUKnown) 614 CPU = Name; 615 616 return CPUKnown; 617 } 618 619 virtual void getTargetBuiltins(const Builtin::Info *&Records, 620 unsigned &NumRecords) const { 621 Records = BuiltinInfo; 622 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 623 } 624 625 virtual bool isCLZForZeroUndef() const { return false; } 626 627 virtual void getTargetDefines(const LangOptions &Opts, 628 MacroBuilder &Builder) const; 629 630 virtual bool hasFeature(StringRef Feature) const; 631 632 virtual void getGCCRegNames(const char * const *&Names, 633 unsigned &NumNames) const; 634 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 635 unsigned &NumAliases) const; 636 virtual bool validateAsmConstraint(const char *&Name, 637 TargetInfo::ConstraintInfo &Info) const { 638 switch (*Name) { 639 default: return false; 640 case 'O': // Zero 641 break; 642 case 'b': // Base register 643 case 'f': // Floating point register 644 Info.setAllowsRegister(); 645 break; 646 // FIXME: The following are added to allow parsing. 647 // I just took a guess at what the actions should be. 648 // Also, is more specific checking needed? I.e. specific registers? 649 case 'd': // Floating point register (containing 64-bit value) 650 case 'v': // Altivec vector register 651 Info.setAllowsRegister(); 652 break; 653 case 'w': 654 switch (Name[1]) { 655 case 'd':// VSX vector register to hold vector double data 656 case 'f':// VSX vector register to hold vector float data 657 case 's':// VSX vector register to hold scalar float data 658 case 'a':// Any VSX register 659 break; 660 default: 661 return false; 662 } 663 Info.setAllowsRegister(); 664 Name++; // Skip over 'w'. 665 break; 666 case 'h': // `MQ', `CTR', or `LINK' register 667 case 'q': // `MQ' register 668 case 'c': // `CTR' register 669 case 'l': // `LINK' register 670 case 'x': // `CR' register (condition register) number 0 671 case 'y': // `CR' register (condition register) 672 case 'z': // `XER[CA]' carry bit (part of the XER register) 673 Info.setAllowsRegister(); 674 break; 675 case 'I': // Signed 16-bit constant 676 case 'J': // Unsigned 16-bit constant shifted left 16 bits 677 // (use `L' instead for SImode constants) 678 case 'K': // Unsigned 16-bit constant 679 case 'L': // Signed 16-bit constant shifted left 16 bits 680 case 'M': // Constant larger than 31 681 case 'N': // Exact power of 2 682 case 'P': // Constant whose negation is a signed 16-bit constant 683 case 'G': // Floating point constant that can be loaded into a 684 // register with one instruction per word 685 case 'H': // Integer/Floating point constant that can be loaded 686 // into a register using three instructions 687 break; 688 case 'm': // Memory operand. Note that on PowerPC targets, m can 689 // include addresses that update the base register. It 690 // is therefore only safe to use `m' in an asm statement 691 // if that asm statement accesses the operand exactly once. 692 // The asm statement must also use `%U<opno>' as a 693 // placeholder for the "update" flag in the corresponding 694 // load or store instruction. For example: 695 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 696 // is correct but: 697 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 698 // is not. Use es rather than m if you don't want the base 699 // register to be updated. 700 case 'e': 701 if (Name[1] != 's') 702 return false; 703 // es: A "stable" memory operand; that is, one which does not 704 // include any automodification of the base register. Unlike 705 // `m', this constraint can be used in asm statements that 706 // might access the operand several times, or that might not 707 // access it at all. 708 Info.setAllowsMemory(); 709 Name++; // Skip over 'e'. 710 break; 711 case 'Q': // Memory operand that is an offset from a register (it is 712 // usually better to use `m' or `es' in asm statements) 713 case 'Z': // Memory operand that is an indexed or indirect from a 714 // register (it is usually better to use `m' or `es' in 715 // asm statements) 716 Info.setAllowsMemory(); 717 Info.setAllowsRegister(); 718 break; 719 case 'R': // AIX TOC entry 720 case 'a': // Address operand that is an indexed or indirect from a 721 // register (`p' is preferable for asm statements) 722 case 'S': // Constant suitable as a 64-bit mask operand 723 case 'T': // Constant suitable as a 32-bit mask operand 724 case 'U': // System V Release 4 small data area reference 725 case 't': // AND masks that can be performed by two rldic{l, r} 726 // instructions 727 case 'W': // Vector constant that does not require memory 728 case 'j': // Vector constant that is all zeros. 729 break; 730 // End FIXME. 731 } 732 return true; 733 } 734 virtual const char *getClobbers() const { 735 return ""; 736 } 737 }; 738 739 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 740 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 741 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 742 ALL_LANGUAGES }, 743 #include "clang/Basic/BuiltinsPPC.def" 744 }; 745 746 747 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 748 /// #defines that are not tied to a specific subtarget. 749 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 750 MacroBuilder &Builder) const { 751 // Target identification. 752 Builder.defineMacro("__ppc__"); 753 Builder.defineMacro("_ARCH_PPC"); 754 Builder.defineMacro("__powerpc__"); 755 Builder.defineMacro("__POWERPC__"); 756 if (PointerWidth == 64) { 757 Builder.defineMacro("_ARCH_PPC64"); 758 Builder.defineMacro("_LP64"); 759 Builder.defineMacro("__LP64__"); 760 Builder.defineMacro("__powerpc64__"); 761 Builder.defineMacro("__ppc64__"); 762 } else { 763 Builder.defineMacro("__ppc__"); 764 } 765 766 // Target properties. 767 if (getTriple().getOS() != llvm::Triple::NetBSD) 768 Builder.defineMacro("_BIG_ENDIAN"); 769 Builder.defineMacro("__BIG_ENDIAN__"); 770 771 // Subtarget options. 772 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 773 Builder.defineMacro("__REGISTER_PREFIX__", ""); 774 775 // FIXME: Should be controlled by command line option. 776 Builder.defineMacro("__LONG_DOUBLE_128__"); 777 778 if (Opts.AltiVec) { 779 Builder.defineMacro("__VEC__", "10206"); 780 Builder.defineMacro("__ALTIVEC__"); 781 } 782 783 // CPU identification. 784 if (CPU == "440") { 785 Builder.defineMacro("_ARCH_440"); 786 } else if (CPU == "450") { 787 Builder.defineMacro("_ARCH_440"); 788 Builder.defineMacro("_ARCH_450"); 789 } else if (CPU == "970") { 790 Builder.defineMacro("_ARCH_970"); 791 } else if (CPU == "pwr6") { 792 Builder.defineMacro("_ARCH_PWR6"); 793 } else if (CPU == "pwr7") { 794 Builder.defineMacro("_ARCH_PWR7"); 795 } 796 } 797 798 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 799 return Feature == "powerpc"; 800 } 801 802 803 const char * const PPCTargetInfo::GCCRegNames[] = { 804 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 805 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 806 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 807 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 808 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 809 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 810 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 811 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 812 "mq", "lr", "ctr", "ap", 813 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 814 "xer", 815 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 816 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 817 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 818 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 819 "vrsave", "vscr", 820 "spe_acc", "spefscr", 821 "sfp" 822 }; 823 824 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 825 unsigned &NumNames) const { 826 Names = GCCRegNames; 827 NumNames = llvm::array_lengthof(GCCRegNames); 828 } 829 830 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 831 // While some of these aliases do map to different registers 832 // they still share the same register name. 833 { { "0" }, "r0" }, 834 { { "1"}, "r1" }, 835 { { "2" }, "r2" }, 836 { { "3" }, "r3" }, 837 { { "4" }, "r4" }, 838 { { "5" }, "r5" }, 839 { { "6" }, "r6" }, 840 { { "7" }, "r7" }, 841 { { "8" }, "r8" }, 842 { { "9" }, "r9" }, 843 { { "10" }, "r10" }, 844 { { "11" }, "r11" }, 845 { { "12" }, "r12" }, 846 { { "13" }, "r13" }, 847 { { "14" }, "r14" }, 848 { { "15" }, "r15" }, 849 { { "16" }, "r16" }, 850 { { "17" }, "r17" }, 851 { { "18" }, "r18" }, 852 { { "19" }, "r19" }, 853 { { "20" }, "r20" }, 854 { { "21" }, "r21" }, 855 { { "22" }, "r22" }, 856 { { "23" }, "r23" }, 857 { { "24" }, "r24" }, 858 { { "25" }, "r25" }, 859 { { "26" }, "r26" }, 860 { { "27" }, "r27" }, 861 { { "28" }, "r28" }, 862 { { "29" }, "r29" }, 863 { { "30" }, "r30" }, 864 { { "31" }, "r31" }, 865 { { "fr0" }, "f0" }, 866 { { "fr1" }, "f1" }, 867 { { "fr2" }, "f2" }, 868 { { "fr3" }, "f3" }, 869 { { "fr4" }, "f4" }, 870 { { "fr5" }, "f5" }, 871 { { "fr6" }, "f6" }, 872 { { "fr7" }, "f7" }, 873 { { "fr8" }, "f8" }, 874 { { "fr9" }, "f9" }, 875 { { "fr10" }, "f10" }, 876 { { "fr11" }, "f11" }, 877 { { "fr12" }, "f12" }, 878 { { "fr13" }, "f13" }, 879 { { "fr14" }, "f14" }, 880 { { "fr15" }, "f15" }, 881 { { "fr16" }, "f16" }, 882 { { "fr17" }, "f17" }, 883 { { "fr18" }, "f18" }, 884 { { "fr19" }, "f19" }, 885 { { "fr20" }, "f20" }, 886 { { "fr21" }, "f21" }, 887 { { "fr22" }, "f22" }, 888 { { "fr23" }, "f23" }, 889 { { "fr24" }, "f24" }, 890 { { "fr25" }, "f25" }, 891 { { "fr26" }, "f26" }, 892 { { "fr27" }, "f27" }, 893 { { "fr28" }, "f28" }, 894 { { "fr29" }, "f29" }, 895 { { "fr30" }, "f30" }, 896 { { "fr31" }, "f31" }, 897 { { "cc" }, "cr0" }, 898 }; 899 900 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 901 unsigned &NumAliases) const { 902 Aliases = GCCRegAliases; 903 NumAliases = llvm::array_lengthof(GCCRegAliases); 904 } 905 } // end anonymous namespace. 906 907 namespace { 908 class PPC32TargetInfo : public PPCTargetInfo { 909 public: 910 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 911 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 912 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 913 914 switch (getTriple().getOS()) { 915 case llvm::Triple::Linux: 916 case llvm::Triple::FreeBSD: 917 case llvm::Triple::NetBSD: 918 SizeType = UnsignedInt; 919 PtrDiffType = SignedInt; 920 IntPtrType = SignedInt; 921 break; 922 default: 923 break; 924 } 925 926 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 927 LongDoubleWidth = LongDoubleAlign = 64; 928 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 929 } 930 } 931 932 virtual const char *getVAListDeclaration() const { 933 // This is the ELF definition, and is overridden by the Darwin sub-target 934 return "typedef struct __va_list_tag {" 935 " unsigned char gpr;" 936 " unsigned char fpr;" 937 " unsigned short reserved;" 938 " void* overflow_arg_area;" 939 " void* reg_save_area;" 940 "} __builtin_va_list[1];"; 941 } 942 }; 943 } // end anonymous namespace. 944 945 namespace { 946 class PPC64TargetInfo : public PPCTargetInfo { 947 public: 948 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 949 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 950 IntMaxType = SignedLong; 951 UIntMaxType = UnsignedLong; 952 Int64Type = SignedLong; 953 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 954 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 955 956 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 957 LongDoubleWidth = LongDoubleAlign = 64; 958 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 959 } 960 } 961 virtual const char *getVAListDeclaration() const { 962 return "typedef char* __builtin_va_list;"; 963 } 964 }; 965 } // end anonymous namespace. 966 967 968 namespace { 969 class DarwinPPC32TargetInfo : 970 public DarwinTargetInfo<PPC32TargetInfo> { 971 public: 972 DarwinPPC32TargetInfo(const std::string& triple) 973 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 974 HasAlignMac68kSupport = true; 975 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 976 LongLongAlign = 32; 977 SuitableAlign = 128; 978 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 979 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 980 } 981 virtual const char *getVAListDeclaration() const { 982 return "typedef char* __builtin_va_list;"; 983 } 984 }; 985 986 class DarwinPPC64TargetInfo : 987 public DarwinTargetInfo<PPC64TargetInfo> { 988 public: 989 DarwinPPC64TargetInfo(const std::string& triple) 990 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 991 HasAlignMac68kSupport = true; 992 SuitableAlign = 128; 993 } 994 }; 995 } // end anonymous namespace. 996 997 namespace { 998 static const unsigned NVPTXAddrSpaceMap[] = { 999 1, // opencl_global 1000 3, // opencl_local 1001 4, // opencl_constant 1002 1, // cuda_device 1003 4, // cuda_constant 1004 3, // cuda_shared 1005 }; 1006 class NVPTXTargetInfo : public TargetInfo { 1007 static const char * const GCCRegNames[]; 1008 static const Builtin::Info BuiltinInfo[]; 1009 std::vector<llvm::StringRef> AvailableFeatures; 1010 public: 1011 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1012 BigEndian = false; 1013 TLSSupported = false; 1014 LongWidth = LongAlign = 64; 1015 AddrSpaceMap = &NVPTXAddrSpaceMap; 1016 // Define available target features 1017 // These must be defined in sorted order! 1018 } 1019 virtual void getTargetDefines(const LangOptions &Opts, 1020 MacroBuilder &Builder) const { 1021 Builder.defineMacro("__PTX__"); 1022 Builder.defineMacro("__NVPTX__"); 1023 } 1024 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1025 unsigned &NumRecords) const { 1026 Records = BuiltinInfo; 1027 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1028 } 1029 virtual bool hasFeature(StringRef Feature) const { 1030 return Feature == "ptx" || Feature == "nvptx"; 1031 } 1032 1033 virtual void getGCCRegNames(const char * const *&Names, 1034 unsigned &NumNames) const; 1035 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1036 unsigned &NumAliases) const { 1037 // No aliases. 1038 Aliases = 0; 1039 NumAliases = 0; 1040 } 1041 virtual bool validateAsmConstraint(const char *&Name, 1042 TargetInfo::ConstraintInfo &info) const { 1043 // FIXME: implement 1044 return true; 1045 } 1046 virtual const char *getClobbers() const { 1047 // FIXME: Is this really right? 1048 return ""; 1049 } 1050 virtual const char *getVAListDeclaration() const { 1051 // FIXME: implement 1052 return "typedef char* __builtin_va_list;"; 1053 } 1054 virtual bool setCPU(const std::string &Name) { 1055 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1056 } 1057 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1058 StringRef Name, 1059 bool Enabled) const; 1060 }; 1061 1062 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1063 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1064 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1065 ALL_LANGUAGES }, 1066 #include "clang/Basic/BuiltinsNVPTX.def" 1067 }; 1068 1069 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1070 "r0" 1071 }; 1072 1073 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1074 unsigned &NumNames) const { 1075 Names = GCCRegNames; 1076 NumNames = llvm::array_lengthof(GCCRegNames); 1077 } 1078 1079 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1080 StringRef Name, 1081 bool Enabled) const { 1082 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1083 Name)) { 1084 Features[Name] = Enabled; 1085 return true; 1086 } else { 1087 return false; 1088 } 1089 } 1090 1091 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1092 public: 1093 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1094 PointerWidth = PointerAlign = 32; 1095 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1096 DescriptionString 1097 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1098 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1099 "n16:32:64"; 1100 } 1101 }; 1102 1103 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1104 public: 1105 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1106 PointerWidth = PointerAlign = 64; 1107 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1108 DescriptionString 1109 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1110 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1111 "n16:32:64"; 1112 } 1113 }; 1114 } 1115 1116 namespace { 1117 // MBlaze abstract base class 1118 class MBlazeTargetInfo : public TargetInfo { 1119 static const char * const GCCRegNames[]; 1120 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1121 1122 public: 1123 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1124 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1125 } 1126 1127 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1128 unsigned &NumRecords) const { 1129 // FIXME: Implement. 1130 Records = 0; 1131 NumRecords = 0; 1132 } 1133 1134 virtual void getTargetDefines(const LangOptions &Opts, 1135 MacroBuilder &Builder) const; 1136 1137 virtual bool hasFeature(StringRef Feature) const { 1138 return Feature == "mblaze"; 1139 } 1140 1141 virtual const char *getVAListDeclaration() const { 1142 return "typedef char* __builtin_va_list;"; 1143 } 1144 virtual const char *getTargetPrefix() const { 1145 return "mblaze"; 1146 } 1147 virtual void getGCCRegNames(const char * const *&Names, 1148 unsigned &NumNames) const; 1149 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1150 unsigned &NumAliases) const; 1151 virtual bool validateAsmConstraint(const char *&Name, 1152 TargetInfo::ConstraintInfo &Info) const { 1153 switch (*Name) { 1154 default: return false; 1155 case 'O': // Zero 1156 return true; 1157 case 'b': // Base register 1158 case 'f': // Floating point register 1159 Info.setAllowsRegister(); 1160 return true; 1161 } 1162 } 1163 virtual const char *getClobbers() const { 1164 return ""; 1165 } 1166 }; 1167 1168 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1169 /// #defines that are not tied to a specific subtarget. 1170 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1171 MacroBuilder &Builder) const { 1172 // Target identification. 1173 Builder.defineMacro("__microblaze__"); 1174 Builder.defineMacro("_ARCH_MICROBLAZE"); 1175 Builder.defineMacro("__MICROBLAZE__"); 1176 1177 // Target properties. 1178 Builder.defineMacro("_BIG_ENDIAN"); 1179 Builder.defineMacro("__BIG_ENDIAN__"); 1180 1181 // Subtarget options. 1182 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1183 } 1184 1185 1186 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1187 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1188 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1189 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1190 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1191 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1192 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1193 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1194 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1195 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1196 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1197 }; 1198 1199 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1200 unsigned &NumNames) const { 1201 Names = GCCRegNames; 1202 NumNames = llvm::array_lengthof(GCCRegNames); 1203 } 1204 1205 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1206 { {"f0"}, "r0" }, 1207 { {"f1"}, "r1" }, 1208 { {"f2"}, "r2" }, 1209 { {"f3"}, "r3" }, 1210 { {"f4"}, "r4" }, 1211 { {"f5"}, "r5" }, 1212 { {"f6"}, "r6" }, 1213 { {"f7"}, "r7" }, 1214 { {"f8"}, "r8" }, 1215 { {"f9"}, "r9" }, 1216 { {"f10"}, "r10" }, 1217 { {"f11"}, "r11" }, 1218 { {"f12"}, "r12" }, 1219 { {"f13"}, "r13" }, 1220 { {"f14"}, "r14" }, 1221 { {"f15"}, "r15" }, 1222 { {"f16"}, "r16" }, 1223 { {"f17"}, "r17" }, 1224 { {"f18"}, "r18" }, 1225 { {"f19"}, "r19" }, 1226 { {"f20"}, "r20" }, 1227 { {"f21"}, "r21" }, 1228 { {"f22"}, "r22" }, 1229 { {"f23"}, "r23" }, 1230 { {"f24"}, "r24" }, 1231 { {"f25"}, "r25" }, 1232 { {"f26"}, "r26" }, 1233 { {"f27"}, "r27" }, 1234 { {"f28"}, "r28" }, 1235 { {"f29"}, "r29" }, 1236 { {"f30"}, "r30" }, 1237 { {"f31"}, "r31" }, 1238 }; 1239 1240 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1241 unsigned &NumAliases) const { 1242 Aliases = GCCRegAliases; 1243 NumAliases = llvm::array_lengthof(GCCRegAliases); 1244 } 1245 } // end anonymous namespace. 1246 1247 namespace { 1248 // Namespace for x86 abstract base class 1249 const Builtin::Info BuiltinInfo[] = { 1250 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1251 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1252 ALL_LANGUAGES }, 1253 #include "clang/Basic/BuiltinsX86.def" 1254 }; 1255 1256 static const char* const GCCRegNames[] = { 1257 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1258 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1259 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1260 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1261 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1262 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1263 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1264 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1265 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1266 }; 1267 1268 const TargetInfo::AddlRegName AddlRegNames[] = { 1269 { { "al", "ah", "eax", "rax" }, 0 }, 1270 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1271 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1272 { { "dl", "dh", "edx", "rdx" }, 1 }, 1273 { { "esi", "rsi" }, 4 }, 1274 { { "edi", "rdi" }, 5 }, 1275 { { "esp", "rsp" }, 7 }, 1276 { { "ebp", "rbp" }, 6 }, 1277 }; 1278 1279 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1280 // most of the implementation can be shared. 1281 class X86TargetInfo : public TargetInfo { 1282 enum X86SSEEnum { 1283 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1284 } SSELevel; 1285 enum MMX3DNowEnum { 1286 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1287 } MMX3DNowLevel; 1288 1289 bool HasAES; 1290 bool HasPCLMUL; 1291 bool HasLZCNT; 1292 bool HasBMI; 1293 bool HasBMI2; 1294 bool HasPOPCNT; 1295 bool HasSSE4a; 1296 bool HasFMA4; 1297 bool HasFMA; 1298 bool HasXOP; 1299 1300 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1301 /// 1302 /// Each enumeration represents a particular CPU supported by Clang. These 1303 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1304 enum CPUKind { 1305 CK_Generic, 1306 1307 /// \name i386 1308 /// i386-generation processors. 1309 //@{ 1310 CK_i386, 1311 //@} 1312 1313 /// \name i486 1314 /// i486-generation processors. 1315 //@{ 1316 CK_i486, 1317 CK_WinChipC6, 1318 CK_WinChip2, 1319 CK_C3, 1320 //@} 1321 1322 /// \name i586 1323 /// i586-generation processors, P5 microarchitecture based. 1324 //@{ 1325 CK_i586, 1326 CK_Pentium, 1327 CK_PentiumMMX, 1328 //@} 1329 1330 /// \name i686 1331 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1332 //@{ 1333 CK_i686, 1334 CK_PentiumPro, 1335 CK_Pentium2, 1336 CK_Pentium3, 1337 CK_Pentium3M, 1338 CK_PentiumM, 1339 CK_C3_2, 1340 1341 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1342 /// Clang however has some logic to suport this. 1343 // FIXME: Warn, deprecate, and potentially remove this. 1344 CK_Yonah, 1345 //@} 1346 1347 /// \name Netburst 1348 /// Netburst microarchitecture based processors. 1349 //@{ 1350 CK_Pentium4, 1351 CK_Pentium4M, 1352 CK_Prescott, 1353 CK_Nocona, 1354 //@} 1355 1356 /// \name Core 1357 /// Core microarchitecture based processors. 1358 //@{ 1359 CK_Core2, 1360 1361 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1362 /// codename which GCC no longer accepts as an option to -march, but Clang 1363 /// has some logic for recognizing it. 1364 // FIXME: Warn, deprecate, and potentially remove this. 1365 CK_Penryn, 1366 //@} 1367 1368 /// \name Atom 1369 /// Atom processors 1370 //@{ 1371 CK_Atom, 1372 //@} 1373 1374 /// \name Nehalem 1375 /// Nehalem microarchitecture based processors. 1376 //@{ 1377 CK_Corei7, 1378 CK_Corei7AVX, 1379 CK_CoreAVXi, 1380 CK_CoreAVX2, 1381 //@} 1382 1383 /// \name K6 1384 /// K6 architecture processors. 1385 //@{ 1386 CK_K6, 1387 CK_K6_2, 1388 CK_K6_3, 1389 //@} 1390 1391 /// \name K7 1392 /// K7 architecture processors. 1393 //@{ 1394 CK_Athlon, 1395 CK_AthlonThunderbird, 1396 CK_Athlon4, 1397 CK_AthlonXP, 1398 CK_AthlonMP, 1399 //@} 1400 1401 /// \name K8 1402 /// K8 architecture processors. 1403 //@{ 1404 CK_Athlon64, 1405 CK_Athlon64SSE3, 1406 CK_AthlonFX, 1407 CK_K8, 1408 CK_K8SSE3, 1409 CK_Opteron, 1410 CK_OpteronSSE3, 1411 CK_AMDFAM10, 1412 //@} 1413 1414 /// \name Bobcat 1415 /// Bobcat architecture processors. 1416 //@{ 1417 CK_BTVER1, 1418 //@} 1419 1420 /// \name Bulldozer 1421 /// Bulldozer architecture processors. 1422 //@{ 1423 CK_BDVER1, 1424 CK_BDVER2, 1425 //@} 1426 1427 /// This specification is deprecated and will be removed in the future. 1428 /// Users should prefer \see CK_K8. 1429 // FIXME: Warn on this when the CPU is set to it. 1430 CK_x86_64, 1431 //@} 1432 1433 /// \name Geode 1434 /// Geode processors. 1435 //@{ 1436 CK_Geode 1437 //@} 1438 } CPU; 1439 1440 public: 1441 X86TargetInfo(const std::string& triple) 1442 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1443 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasBMI(false), 1444 HasBMI2(false), HasPOPCNT(false), HasSSE4a(false), HasFMA4(false), 1445 HasFMA(false), HasXOP(false), CPU(CK_Generic) { 1446 BigEndian = false; 1447 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1448 } 1449 virtual unsigned getFloatEvalMethod() const { 1450 // X87 evaluates with 80 bits "long double" precision. 1451 return SSELevel == NoSSE ? 2 : 0; 1452 } 1453 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1454 unsigned &NumRecords) const { 1455 Records = BuiltinInfo; 1456 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1457 } 1458 virtual void getGCCRegNames(const char * const *&Names, 1459 unsigned &NumNames) const { 1460 Names = GCCRegNames; 1461 NumNames = llvm::array_lengthof(GCCRegNames); 1462 } 1463 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1464 unsigned &NumAliases) const { 1465 Aliases = 0; 1466 NumAliases = 0; 1467 } 1468 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1469 unsigned &NumNames) const { 1470 Names = AddlRegNames; 1471 NumNames = llvm::array_lengthof(AddlRegNames); 1472 } 1473 virtual bool validateAsmConstraint(const char *&Name, 1474 TargetInfo::ConstraintInfo &info) const; 1475 virtual std::string convertConstraint(const char *&Constraint) const; 1476 virtual const char *getClobbers() const { 1477 return "~{dirflag},~{fpsr},~{flags}"; 1478 } 1479 virtual void getTargetDefines(const LangOptions &Opts, 1480 MacroBuilder &Builder) const; 1481 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1482 StringRef Name, 1483 bool Enabled) const; 1484 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1485 virtual bool hasFeature(StringRef Feature) const; 1486 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1487 virtual const char* getABI() const { 1488 if (PointerWidth == 64 && SSELevel >= AVX) 1489 return "avx"; 1490 else if (PointerWidth == 32 && MMX3DNowLevel == NoMMX3DNow) 1491 return "no-mmx"; 1492 return ""; 1493 } 1494 virtual bool setCPU(const std::string &Name) { 1495 CPU = llvm::StringSwitch<CPUKind>(Name) 1496 .Case("i386", CK_i386) 1497 .Case("i486", CK_i486) 1498 .Case("winchip-c6", CK_WinChipC6) 1499 .Case("winchip2", CK_WinChip2) 1500 .Case("c3", CK_C3) 1501 .Case("i586", CK_i586) 1502 .Case("pentium", CK_Pentium) 1503 .Case("pentium-mmx", CK_PentiumMMX) 1504 .Case("i686", CK_i686) 1505 .Case("pentiumpro", CK_PentiumPro) 1506 .Case("pentium2", CK_Pentium2) 1507 .Case("pentium3", CK_Pentium3) 1508 .Case("pentium3m", CK_Pentium3M) 1509 .Case("pentium-m", CK_PentiumM) 1510 .Case("c3-2", CK_C3_2) 1511 .Case("yonah", CK_Yonah) 1512 .Case("pentium4", CK_Pentium4) 1513 .Case("pentium4m", CK_Pentium4M) 1514 .Case("prescott", CK_Prescott) 1515 .Case("nocona", CK_Nocona) 1516 .Case("core2", CK_Core2) 1517 .Case("penryn", CK_Penryn) 1518 .Case("atom", CK_Atom) 1519 .Case("corei7", CK_Corei7) 1520 .Case("corei7-avx", CK_Corei7AVX) 1521 .Case("core-avx-i", CK_CoreAVXi) 1522 .Case("core-avx2", CK_CoreAVX2) 1523 .Case("k6", CK_K6) 1524 .Case("k6-2", CK_K6_2) 1525 .Case("k6-3", CK_K6_3) 1526 .Case("athlon", CK_Athlon) 1527 .Case("athlon-tbird", CK_AthlonThunderbird) 1528 .Case("athlon-4", CK_Athlon4) 1529 .Case("athlon-xp", CK_AthlonXP) 1530 .Case("athlon-mp", CK_AthlonMP) 1531 .Case("athlon64", CK_Athlon64) 1532 .Case("athlon64-sse3", CK_Athlon64SSE3) 1533 .Case("athlon-fx", CK_AthlonFX) 1534 .Case("k8", CK_K8) 1535 .Case("k8-sse3", CK_K8SSE3) 1536 .Case("opteron", CK_Opteron) 1537 .Case("opteron-sse3", CK_OpteronSSE3) 1538 .Case("amdfam10", CK_AMDFAM10) 1539 .Case("btver1", CK_BTVER1) 1540 .Case("bdver1", CK_BDVER1) 1541 .Case("bdver2", CK_BDVER2) 1542 .Case("x86-64", CK_x86_64) 1543 .Case("geode", CK_Geode) 1544 .Default(CK_Generic); 1545 1546 // Perform any per-CPU checks necessary to determine if this CPU is 1547 // acceptable. 1548 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1549 // invalid without explaining *why*. 1550 switch (CPU) { 1551 case CK_Generic: 1552 // No processor selected! 1553 return false; 1554 1555 case CK_i386: 1556 case CK_i486: 1557 case CK_WinChipC6: 1558 case CK_WinChip2: 1559 case CK_C3: 1560 case CK_i586: 1561 case CK_Pentium: 1562 case CK_PentiumMMX: 1563 case CK_i686: 1564 case CK_PentiumPro: 1565 case CK_Pentium2: 1566 case CK_Pentium3: 1567 case CK_Pentium3M: 1568 case CK_PentiumM: 1569 case CK_Yonah: 1570 case CK_C3_2: 1571 case CK_Pentium4: 1572 case CK_Pentium4M: 1573 case CK_Prescott: 1574 case CK_K6: 1575 case CK_K6_2: 1576 case CK_K6_3: 1577 case CK_Athlon: 1578 case CK_AthlonThunderbird: 1579 case CK_Athlon4: 1580 case CK_AthlonXP: 1581 case CK_AthlonMP: 1582 case CK_Geode: 1583 // Only accept certain architectures when compiling in 32-bit mode. 1584 if (PointerWidth != 32) 1585 return false; 1586 1587 // Fallthrough 1588 case CK_Nocona: 1589 case CK_Core2: 1590 case CK_Penryn: 1591 case CK_Atom: 1592 case CK_Corei7: 1593 case CK_Corei7AVX: 1594 case CK_CoreAVXi: 1595 case CK_CoreAVX2: 1596 case CK_Athlon64: 1597 case CK_Athlon64SSE3: 1598 case CK_AthlonFX: 1599 case CK_K8: 1600 case CK_K8SSE3: 1601 case CK_Opteron: 1602 case CK_OpteronSSE3: 1603 case CK_AMDFAM10: 1604 case CK_BTVER1: 1605 case CK_BDVER1: 1606 case CK_BDVER2: 1607 case CK_x86_64: 1608 return true; 1609 } 1610 llvm_unreachable("Unhandled CPU kind"); 1611 } 1612 }; 1613 1614 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1615 // FIXME: This should not be here. 1616 Features["3dnow"] = false; 1617 Features["3dnowa"] = false; 1618 Features["mmx"] = false; 1619 Features["sse"] = false; 1620 Features["sse2"] = false; 1621 Features["sse3"] = false; 1622 Features["ssse3"] = false; 1623 Features["sse41"] = false; 1624 Features["sse42"] = false; 1625 Features["sse4a"] = false; 1626 Features["aes"] = false; 1627 Features["pclmul"] = false; 1628 Features["avx"] = false; 1629 Features["avx2"] = false; 1630 Features["lzcnt"] = false; 1631 Features["bmi"] = false; 1632 Features["bmi2"] = false; 1633 Features["popcnt"] = false; 1634 Features["fma4"] = false; 1635 Features["fma"] = false; 1636 Features["xop"] = false; 1637 1638 // FIXME: This *really* should not be here. 1639 1640 // X86_64 always has SSE2. 1641 if (PointerWidth == 64) 1642 Features["sse2"] = Features["sse"] = Features["mmx"] = true; 1643 1644 switch (CPU) { 1645 case CK_Generic: 1646 case CK_i386: 1647 case CK_i486: 1648 case CK_i586: 1649 case CK_Pentium: 1650 case CK_i686: 1651 case CK_PentiumPro: 1652 break; 1653 case CK_PentiumMMX: 1654 case CK_Pentium2: 1655 setFeatureEnabled(Features, "mmx", true); 1656 break; 1657 case CK_Pentium3: 1658 case CK_Pentium3M: 1659 setFeatureEnabled(Features, "mmx", true); 1660 setFeatureEnabled(Features, "sse", true); 1661 break; 1662 case CK_PentiumM: 1663 case CK_Pentium4: 1664 case CK_Pentium4M: 1665 case CK_x86_64: 1666 setFeatureEnabled(Features, "mmx", true); 1667 setFeatureEnabled(Features, "sse2", true); 1668 break; 1669 case CK_Yonah: 1670 case CK_Prescott: 1671 case CK_Nocona: 1672 setFeatureEnabled(Features, "mmx", true); 1673 setFeatureEnabled(Features, "sse3", true); 1674 break; 1675 case CK_Core2: 1676 setFeatureEnabled(Features, "mmx", true); 1677 setFeatureEnabled(Features, "ssse3", true); 1678 break; 1679 case CK_Penryn: 1680 setFeatureEnabled(Features, "mmx", true); 1681 setFeatureEnabled(Features, "sse4.1", true); 1682 break; 1683 case CK_Atom: 1684 setFeatureEnabled(Features, "mmx", true); 1685 setFeatureEnabled(Features, "ssse3", true); 1686 break; 1687 case CK_Corei7: 1688 setFeatureEnabled(Features, "mmx", true); 1689 setFeatureEnabled(Features, "sse4", true); 1690 break; 1691 case CK_Corei7AVX: 1692 case CK_CoreAVXi: 1693 setFeatureEnabled(Features, "mmx", true); 1694 setFeatureEnabled(Features, "avx", true); 1695 setFeatureEnabled(Features, "aes", true); 1696 setFeatureEnabled(Features, "pclmul", true); 1697 break; 1698 case CK_CoreAVX2: 1699 setFeatureEnabled(Features, "mmx", true); 1700 setFeatureEnabled(Features, "avx2", true); 1701 setFeatureEnabled(Features, "aes", true); 1702 setFeatureEnabled(Features, "pclmul", true); 1703 setFeatureEnabled(Features, "lzcnt", true); 1704 setFeatureEnabled(Features, "bmi", true); 1705 setFeatureEnabled(Features, "bmi2", true); 1706 setFeatureEnabled(Features, "fma", true); 1707 break; 1708 case CK_K6: 1709 case CK_WinChipC6: 1710 setFeatureEnabled(Features, "mmx", true); 1711 break; 1712 case CK_K6_2: 1713 case CK_K6_3: 1714 case CK_WinChip2: 1715 case CK_C3: 1716 setFeatureEnabled(Features, "3dnow", true); 1717 break; 1718 case CK_Athlon: 1719 case CK_AthlonThunderbird: 1720 case CK_Geode: 1721 setFeatureEnabled(Features, "3dnowa", true); 1722 break; 1723 case CK_Athlon4: 1724 case CK_AthlonXP: 1725 case CK_AthlonMP: 1726 setFeatureEnabled(Features, "sse", true); 1727 setFeatureEnabled(Features, "3dnowa", true); 1728 break; 1729 case CK_K8: 1730 case CK_Opteron: 1731 case CK_Athlon64: 1732 case CK_AthlonFX: 1733 setFeatureEnabled(Features, "sse2", true); 1734 setFeatureEnabled(Features, "3dnowa", true); 1735 break; 1736 case CK_K8SSE3: 1737 case CK_OpteronSSE3: 1738 case CK_Athlon64SSE3: 1739 setFeatureEnabled(Features, "sse3", true); 1740 setFeatureEnabled(Features, "3dnowa", true); 1741 break; 1742 case CK_AMDFAM10: 1743 setFeatureEnabled(Features, "sse3", true); 1744 setFeatureEnabled(Features, "sse4a", true); 1745 setFeatureEnabled(Features, "3dnowa", true); 1746 break; 1747 case CK_BTVER1: 1748 setFeatureEnabled(Features, "ssse3", true); 1749 setFeatureEnabled(Features, "sse4a", true); 1750 break; 1751 case CK_BDVER1: 1752 case CK_BDVER2: 1753 setFeatureEnabled(Features, "avx", true); 1754 setFeatureEnabled(Features, "xop", true); 1755 setFeatureEnabled(Features, "aes", true); 1756 setFeatureEnabled(Features, "pclmul", true); 1757 break; 1758 case CK_C3_2: 1759 setFeatureEnabled(Features, "mmx", true); 1760 setFeatureEnabled(Features, "sse", true); 1761 break; 1762 } 1763 } 1764 1765 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1766 StringRef Name, 1767 bool Enabled) const { 1768 // FIXME: This *really* should not be here. We need some way of translating 1769 // options into llvm subtarget features. 1770 if (!Features.count(Name) && 1771 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1")) 1772 return false; 1773 1774 // FIXME: this should probably use a switch with fall through. 1775 1776 if (Enabled) { 1777 if (Name == "mmx") 1778 Features["mmx"] = true; 1779 else if (Name == "sse") 1780 Features["mmx"] = Features["sse"] = true; 1781 else if (Name == "sse2") 1782 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1783 else if (Name == "sse3") 1784 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1785 true; 1786 else if (Name == "ssse3") 1787 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1788 Features["ssse3"] = true; 1789 else if (Name == "sse4" || Name == "sse4.2") 1790 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1791 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1792 Features["popcnt"] = true; 1793 else if (Name == "sse4.1") 1794 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1795 Features["ssse3"] = Features["sse41"] = true; 1796 else if (Name == "3dnow") 1797 Features["mmx"] = Features["3dnow"] = true; 1798 else if (Name == "3dnowa") 1799 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 1800 else if (Name == "aes") 1801 Features["sse"] = Features["sse2"] = Features["aes"] = true; 1802 else if (Name == "pclmul") 1803 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 1804 else if (Name == "avx") 1805 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1806 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1807 Features["popcnt"] = Features["avx"] = true; 1808 else if (Name == "avx2") 1809 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1810 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1811 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 1812 else if (Name == "fma") 1813 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1814 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1815 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 1816 else if (Name == "fma4") 1817 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1818 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1819 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1820 Features["fma4"] = true; 1821 else if (Name == "xop") 1822 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1823 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1824 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1825 Features["fma4"] = Features["xop"] = true; 1826 else if (Name == "sse4a") 1827 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1828 Features["sse4a"] = true; 1829 else if (Name == "lzcnt") 1830 Features["lzcnt"] = true; 1831 else if (Name == "bmi") 1832 Features["bmi"] = true; 1833 else if (Name == "bmi2") 1834 Features["bmi2"] = true; 1835 else if (Name == "popcnt") 1836 Features["popcnt"] = true; 1837 } else { 1838 if (Name == "mmx") 1839 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 1840 else if (Name == "sse") 1841 Features["sse"] = Features["sse2"] = Features["sse3"] = 1842 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1843 Features["sse4a"] = Features["avx"] = Features["avx2"] = 1844 Features["fma"] = Features["fma4"] = Features["aes"] = 1845 Features["pclmul"] = Features["xop"] = false; 1846 else if (Name == "sse2") 1847 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 1848 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 1849 Features["avx"] = Features["avx2"] = Features["fma"] = 1850 Features["fma4"] = Features["aes"] = Features["pclmul"] = 1851 Features["xop"] = false; 1852 else if (Name == "sse3") 1853 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 1854 Features["sse42"] = Features["sse4a"] = Features["avx"] = 1855 Features["avx2"] = Features["fma"] = Features["fma4"] = 1856 Features["xop"] = false; 1857 else if (Name == "ssse3") 1858 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1859 Features["avx"] = Features["avx2"] = Features["fma"] = false; 1860 else if (Name == "sse4" || Name == "sse4.1") 1861 Features["sse41"] = Features["sse42"] = Features["avx"] = 1862 Features["avx2"] = Features["fma"] = false; 1863 else if (Name == "sse4.2") 1864 Features["sse42"] = Features["avx"] = Features["avx2"] = 1865 Features["fma"] = false; 1866 else if (Name == "3dnow") 1867 Features["3dnow"] = Features["3dnowa"] = false; 1868 else if (Name == "3dnowa") 1869 Features["3dnowa"] = false; 1870 else if (Name == "aes") 1871 Features["aes"] = false; 1872 else if (Name == "pclmul") 1873 Features["pclmul"] = false; 1874 else if (Name == "avx") 1875 Features["avx"] = Features["avx2"] = Features["fma"] = 1876 Features["fma4"] = Features["xop"] = false; 1877 else if (Name == "avx2") 1878 Features["avx2"] = false; 1879 else if (Name == "fma") 1880 Features["fma"] = false; 1881 else if (Name == "sse4a") 1882 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 1883 else if (Name == "lzcnt") 1884 Features["lzcnt"] = false; 1885 else if (Name == "bmi") 1886 Features["bmi"] = false; 1887 else if (Name == "bmi2") 1888 Features["bmi2"] = false; 1889 else if (Name == "popcnt") 1890 Features["popcnt"] = false; 1891 else if (Name == "fma4") 1892 Features["fma4"] = Features["xop"] = false; 1893 else if (Name == "xop") 1894 Features["xop"] = false; 1895 } 1896 1897 return true; 1898 } 1899 1900 /// HandleTargetOptions - Perform initialization based on the user 1901 /// configured set of features. 1902 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 1903 // Remember the maximum enabled sselevel. 1904 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1905 // Ignore disabled features. 1906 if (Features[i][0] == '-') 1907 continue; 1908 1909 StringRef Feature = StringRef(Features[i]).substr(1); 1910 1911 if (Feature == "aes") { 1912 HasAES = true; 1913 continue; 1914 } 1915 1916 if (Feature == "pclmul") { 1917 HasPCLMUL = true; 1918 continue; 1919 } 1920 1921 if (Feature == "lzcnt") { 1922 HasLZCNT = true; 1923 continue; 1924 } 1925 1926 if (Feature == "bmi") { 1927 HasBMI = true; 1928 continue; 1929 } 1930 1931 if (Feature == "bmi2") { 1932 HasBMI2 = true; 1933 continue; 1934 } 1935 1936 if (Feature == "popcnt") { 1937 HasPOPCNT = true; 1938 continue; 1939 } 1940 1941 if (Feature == "sse4a") { 1942 HasSSE4a = true; 1943 continue; 1944 } 1945 1946 if (Feature == "fma4") { 1947 HasFMA4 = true; 1948 continue; 1949 } 1950 1951 if (Feature == "fma") { 1952 HasFMA = true; 1953 continue; 1954 } 1955 1956 if (Feature == "xop") { 1957 HasXOP = true; 1958 continue; 1959 } 1960 1961 assert(Features[i][0] == '+' && "Invalid target feature!"); 1962 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 1963 .Case("avx2", AVX2) 1964 .Case("avx", AVX) 1965 .Case("sse42", SSE42) 1966 .Case("sse41", SSE41) 1967 .Case("ssse3", SSSE3) 1968 .Case("sse3", SSE3) 1969 .Case("sse2", SSE2) 1970 .Case("sse", SSE1) 1971 .Default(NoSSE); 1972 SSELevel = std::max(SSELevel, Level); 1973 1974 MMX3DNowEnum ThreeDNowLevel = 1975 llvm::StringSwitch<MMX3DNowEnum>(Feature) 1976 .Case("3dnowa", AMD3DNowAthlon) 1977 .Case("3dnow", AMD3DNow) 1978 .Case("mmx", MMX) 1979 .Default(NoMMX3DNow); 1980 1981 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 1982 } 1983 1984 // Don't tell the backend if we're turning off mmx; it will end up disabling 1985 // SSE, which we don't want. 1986 std::vector<std::string>::iterator it; 1987 it = std::find(Features.begin(), Features.end(), "-mmx"); 1988 if (it != Features.end()) 1989 Features.erase(it); 1990 } 1991 1992 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 1993 /// definitions for this particular subtarget. 1994 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 1995 MacroBuilder &Builder) const { 1996 // Target identification. 1997 if (PointerWidth == 64) { 1998 if (getLongWidth() == 64) { 1999 Builder.defineMacro("_LP64"); 2000 Builder.defineMacro("__LP64__"); 2001 } 2002 Builder.defineMacro("__amd64__"); 2003 Builder.defineMacro("__amd64"); 2004 Builder.defineMacro("__x86_64"); 2005 Builder.defineMacro("__x86_64__"); 2006 } else { 2007 DefineStd(Builder, "i386", Opts); 2008 } 2009 2010 // Subtarget options. 2011 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2012 // truly should be based on -mtune options. 2013 switch (CPU) { 2014 case CK_Generic: 2015 break; 2016 case CK_i386: 2017 // The rest are coming from the i386 define above. 2018 Builder.defineMacro("__tune_i386__"); 2019 break; 2020 case CK_i486: 2021 case CK_WinChipC6: 2022 case CK_WinChip2: 2023 case CK_C3: 2024 defineCPUMacros(Builder, "i486"); 2025 break; 2026 case CK_PentiumMMX: 2027 Builder.defineMacro("__pentium_mmx__"); 2028 Builder.defineMacro("__tune_pentium_mmx__"); 2029 // Fallthrough 2030 case CK_i586: 2031 case CK_Pentium: 2032 defineCPUMacros(Builder, "i586"); 2033 defineCPUMacros(Builder, "pentium"); 2034 break; 2035 case CK_Pentium3: 2036 case CK_Pentium3M: 2037 case CK_PentiumM: 2038 Builder.defineMacro("__tune_pentium3__"); 2039 // Fallthrough 2040 case CK_Pentium2: 2041 case CK_C3_2: 2042 Builder.defineMacro("__tune_pentium2__"); 2043 // Fallthrough 2044 case CK_PentiumPro: 2045 Builder.defineMacro("__tune_i686__"); 2046 Builder.defineMacro("__tune_pentiumpro__"); 2047 // Fallthrough 2048 case CK_i686: 2049 Builder.defineMacro("__i686"); 2050 Builder.defineMacro("__i686__"); 2051 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2052 Builder.defineMacro("__pentiumpro"); 2053 Builder.defineMacro("__pentiumpro__"); 2054 break; 2055 case CK_Pentium4: 2056 case CK_Pentium4M: 2057 defineCPUMacros(Builder, "pentium4"); 2058 break; 2059 case CK_Yonah: 2060 case CK_Prescott: 2061 case CK_Nocona: 2062 defineCPUMacros(Builder, "nocona"); 2063 break; 2064 case CK_Core2: 2065 case CK_Penryn: 2066 defineCPUMacros(Builder, "core2"); 2067 break; 2068 case CK_Atom: 2069 defineCPUMacros(Builder, "atom"); 2070 break; 2071 case CK_Corei7: 2072 case CK_Corei7AVX: 2073 case CK_CoreAVXi: 2074 case CK_CoreAVX2: 2075 defineCPUMacros(Builder, "corei7"); 2076 break; 2077 case CK_K6_2: 2078 Builder.defineMacro("__k6_2__"); 2079 Builder.defineMacro("__tune_k6_2__"); 2080 // Fallthrough 2081 case CK_K6_3: 2082 if (CPU != CK_K6_2) { // In case of fallthrough 2083 // FIXME: GCC may be enabling these in cases where some other k6 2084 // architecture is specified but -m3dnow is explicitly provided. The 2085 // exact semantics need to be determined and emulated here. 2086 Builder.defineMacro("__k6_3__"); 2087 Builder.defineMacro("__tune_k6_3__"); 2088 } 2089 // Fallthrough 2090 case CK_K6: 2091 defineCPUMacros(Builder, "k6"); 2092 break; 2093 case CK_Athlon: 2094 case CK_AthlonThunderbird: 2095 case CK_Athlon4: 2096 case CK_AthlonXP: 2097 case CK_AthlonMP: 2098 defineCPUMacros(Builder, "athlon"); 2099 if (SSELevel != NoSSE) { 2100 Builder.defineMacro("__athlon_sse__"); 2101 Builder.defineMacro("__tune_athlon_sse__"); 2102 } 2103 break; 2104 case CK_K8: 2105 case CK_K8SSE3: 2106 case CK_x86_64: 2107 case CK_Opteron: 2108 case CK_OpteronSSE3: 2109 case CK_Athlon64: 2110 case CK_Athlon64SSE3: 2111 case CK_AthlonFX: 2112 defineCPUMacros(Builder, "k8"); 2113 break; 2114 case CK_AMDFAM10: 2115 defineCPUMacros(Builder, "amdfam10"); 2116 break; 2117 case CK_BTVER1: 2118 defineCPUMacros(Builder, "btver1"); 2119 break; 2120 case CK_BDVER1: 2121 defineCPUMacros(Builder, "bdver1"); 2122 break; 2123 case CK_BDVER2: 2124 defineCPUMacros(Builder, "bdver2"); 2125 break; 2126 case CK_Geode: 2127 defineCPUMacros(Builder, "geode"); 2128 break; 2129 } 2130 2131 // Target properties. 2132 Builder.defineMacro("__LITTLE_ENDIAN__"); 2133 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2134 2135 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2136 // functions in glibc header files that use FP Stack inline asm which the 2137 // backend can't deal with (PR879). 2138 Builder.defineMacro("__NO_MATH_INLINES"); 2139 2140 if (HasAES) 2141 Builder.defineMacro("__AES__"); 2142 2143 if (HasPCLMUL) 2144 Builder.defineMacro("__PCLMUL__"); 2145 2146 if (HasLZCNT) 2147 Builder.defineMacro("__LZCNT__"); 2148 2149 if (HasBMI) 2150 Builder.defineMacro("__BMI__"); 2151 2152 if (HasBMI2) 2153 Builder.defineMacro("__BMI2__"); 2154 2155 if (HasPOPCNT) 2156 Builder.defineMacro("__POPCNT__"); 2157 2158 if (HasSSE4a) 2159 Builder.defineMacro("__SSE4A__"); 2160 2161 if (HasFMA4) 2162 Builder.defineMacro("__FMA4__"); 2163 2164 if (HasFMA) 2165 Builder.defineMacro("__FMA__"); 2166 2167 if (HasXOP) 2168 Builder.defineMacro("__XOP__"); 2169 2170 // Each case falls through to the previous one here. 2171 switch (SSELevel) { 2172 case AVX2: 2173 Builder.defineMacro("__AVX2__"); 2174 case AVX: 2175 Builder.defineMacro("__AVX__"); 2176 case SSE42: 2177 Builder.defineMacro("__SSE4_2__"); 2178 case SSE41: 2179 Builder.defineMacro("__SSE4_1__"); 2180 case SSSE3: 2181 Builder.defineMacro("__SSSE3__"); 2182 case SSE3: 2183 Builder.defineMacro("__SSE3__"); 2184 case SSE2: 2185 Builder.defineMacro("__SSE2__"); 2186 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2187 case SSE1: 2188 Builder.defineMacro("__SSE__"); 2189 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2190 case NoSSE: 2191 break; 2192 } 2193 2194 if (Opts.MicrosoftExt && PointerWidth == 32) { 2195 switch (SSELevel) { 2196 case AVX2: 2197 case AVX: 2198 case SSE42: 2199 case SSE41: 2200 case SSSE3: 2201 case SSE3: 2202 case SSE2: 2203 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2204 break; 2205 case SSE1: 2206 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2207 break; 2208 default: 2209 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2210 } 2211 } 2212 2213 // Each case falls through to the previous one here. 2214 switch (MMX3DNowLevel) { 2215 case AMD3DNowAthlon: 2216 Builder.defineMacro("__3dNOW_A__"); 2217 case AMD3DNow: 2218 Builder.defineMacro("__3dNOW__"); 2219 case MMX: 2220 Builder.defineMacro("__MMX__"); 2221 case NoMMX3DNow: 2222 break; 2223 } 2224 } 2225 2226 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2227 return llvm::StringSwitch<bool>(Feature) 2228 .Case("aes", HasAES) 2229 .Case("avx", SSELevel >= AVX) 2230 .Case("avx2", SSELevel >= AVX2) 2231 .Case("bmi", HasBMI) 2232 .Case("bmi2", HasBMI2) 2233 .Case("fma", HasFMA) 2234 .Case("fma4", HasFMA4) 2235 .Case("lzcnt", HasLZCNT) 2236 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2237 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2238 .Case("mmx", MMX3DNowLevel >= MMX) 2239 .Case("pclmul", HasPCLMUL) 2240 .Case("popcnt", HasPOPCNT) 2241 .Case("sse", SSELevel >= SSE1) 2242 .Case("sse2", SSELevel >= SSE2) 2243 .Case("sse3", SSELevel >= SSE3) 2244 .Case("ssse3", SSELevel >= SSSE3) 2245 .Case("sse41", SSELevel >= SSE41) 2246 .Case("sse42", SSELevel >= SSE42) 2247 .Case("sse4a", HasSSE4a) 2248 .Case("x86", true) 2249 .Case("x86_32", PointerWidth == 32) 2250 .Case("x86_64", PointerWidth == 64) 2251 .Case("xop", HasXOP) 2252 .Default(false); 2253 } 2254 2255 bool 2256 X86TargetInfo::validateAsmConstraint(const char *&Name, 2257 TargetInfo::ConstraintInfo &Info) const { 2258 switch (*Name) { 2259 default: return false; 2260 case 'Y': // first letter of a pair: 2261 switch (*(Name+1)) { 2262 default: return false; 2263 case '0': // First SSE register. 2264 case 't': // Any SSE register, when SSE2 is enabled. 2265 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2266 case 'm': // any MMX register, when inter-unit moves enabled. 2267 break; // falls through to setAllowsRegister. 2268 } 2269 case 'a': // eax. 2270 case 'b': // ebx. 2271 case 'c': // ecx. 2272 case 'd': // edx. 2273 case 'S': // esi. 2274 case 'D': // edi. 2275 case 'A': // edx:eax. 2276 case 'f': // any x87 floating point stack register. 2277 case 't': // top of floating point stack. 2278 case 'u': // second from top of floating point stack. 2279 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2280 case 'y': // Any MMX register. 2281 case 'x': // Any SSE register. 2282 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2283 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2284 case 'l': // "Index" registers: any general register that can be used as an 2285 // index in a base+index memory access. 2286 Info.setAllowsRegister(); 2287 return true; 2288 case 'C': // SSE floating point constant. 2289 case 'G': // x87 floating point constant. 2290 case 'e': // 32-bit signed integer constant for use with zero-extending 2291 // x86_64 instructions. 2292 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2293 // x86_64 instructions. 2294 return true; 2295 } 2296 } 2297 2298 2299 std::string 2300 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2301 switch (*Constraint) { 2302 case 'a': return std::string("{ax}"); 2303 case 'b': return std::string("{bx}"); 2304 case 'c': return std::string("{cx}"); 2305 case 'd': return std::string("{dx}"); 2306 case 'S': return std::string("{si}"); 2307 case 'D': return std::string("{di}"); 2308 case 'p': // address 2309 return std::string("im"); 2310 case 't': // top of floating point stack. 2311 return std::string("{st}"); 2312 case 'u': // second from top of floating point stack. 2313 return std::string("{st(1)}"); // second from top of floating point stack. 2314 default: 2315 return std::string(1, *Constraint); 2316 } 2317 } 2318 } // end anonymous namespace 2319 2320 namespace { 2321 // X86-32 generic target 2322 class X86_32TargetInfo : public X86TargetInfo { 2323 public: 2324 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2325 DoubleAlign = LongLongAlign = 32; 2326 LongDoubleWidth = 96; 2327 LongDoubleAlign = 32; 2328 SuitableAlign = 128; 2329 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2330 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2331 "a0:0:64-f80:32:32-n8:16:32-S128"; 2332 SizeType = UnsignedInt; 2333 PtrDiffType = SignedInt; 2334 IntPtrType = SignedInt; 2335 RegParmMax = 3; 2336 2337 // Use fpret for all types. 2338 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2339 (1 << TargetInfo::Double) | 2340 (1 << TargetInfo::LongDouble)); 2341 2342 // x86-32 has atomics up to 8 bytes 2343 // FIXME: Check that we actually have cmpxchg8b before setting 2344 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2345 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2346 } 2347 virtual const char *getVAListDeclaration() const { 2348 return "typedef char* __builtin_va_list;"; 2349 } 2350 2351 int getEHDataRegisterNumber(unsigned RegNo) const { 2352 if (RegNo == 0) return 0; 2353 if (RegNo == 1) return 2; 2354 return -1; 2355 } 2356 }; 2357 } // end anonymous namespace 2358 2359 namespace { 2360 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2361 public: 2362 NetBSDI386TargetInfo(const std::string &triple) : 2363 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2364 } 2365 2366 virtual unsigned getFloatEvalMethod() const { 2367 // NetBSD defaults to "double" rounding 2368 return 1; 2369 } 2370 }; 2371 } // end anonymous namespace 2372 2373 namespace { 2374 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2375 public: 2376 OpenBSDI386TargetInfo(const std::string& triple) : 2377 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2378 SizeType = UnsignedLong; 2379 IntPtrType = SignedLong; 2380 PtrDiffType = SignedLong; 2381 } 2382 }; 2383 } // end anonymous namespace 2384 2385 namespace { 2386 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2387 public: 2388 DarwinI386TargetInfo(const std::string& triple) : 2389 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2390 LongDoubleWidth = 128; 2391 LongDoubleAlign = 128; 2392 SuitableAlign = 128; 2393 SizeType = UnsignedLong; 2394 IntPtrType = SignedLong; 2395 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2396 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2397 "a0:0:64-f80:128:128-n8:16:32-S128"; 2398 HasAlignMac68kSupport = true; 2399 } 2400 2401 }; 2402 } // end anonymous namespace 2403 2404 namespace { 2405 // x86-32 Windows target 2406 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2407 public: 2408 WindowsX86_32TargetInfo(const std::string& triple) 2409 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2410 TLSSupported = false; 2411 WCharType = UnsignedShort; 2412 DoubleAlign = LongLongAlign = 64; 2413 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2414 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2415 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2416 } 2417 virtual void getTargetDefines(const LangOptions &Opts, 2418 MacroBuilder &Builder) const { 2419 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2420 } 2421 }; 2422 } // end anonymous namespace 2423 2424 namespace { 2425 2426 // x86-32 Windows Visual Studio target 2427 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2428 public: 2429 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2430 : WindowsX86_32TargetInfo(triple) { 2431 LongDoubleWidth = LongDoubleAlign = 64; 2432 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2433 } 2434 virtual void getTargetDefines(const LangOptions &Opts, 2435 MacroBuilder &Builder) const { 2436 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2437 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2438 // The value of the following reflects processor type. 2439 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2440 // We lost the original triple, so we use the default. 2441 Builder.defineMacro("_M_IX86", "600"); 2442 } 2443 }; 2444 } // end anonymous namespace 2445 2446 namespace { 2447 // x86-32 MinGW target 2448 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2449 public: 2450 MinGWX86_32TargetInfo(const std::string& triple) 2451 : WindowsX86_32TargetInfo(triple) { 2452 } 2453 virtual void getTargetDefines(const LangOptions &Opts, 2454 MacroBuilder &Builder) const { 2455 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2456 DefineStd(Builder, "WIN32", Opts); 2457 DefineStd(Builder, "WINNT", Opts); 2458 Builder.defineMacro("_X86_"); 2459 Builder.defineMacro("__MSVCRT__"); 2460 Builder.defineMacro("__MINGW32__"); 2461 2462 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2463 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2464 if (Opts.MicrosoftExt) 2465 // Provide "as-is" __declspec. 2466 Builder.defineMacro("__declspec", "__declspec"); 2467 else 2468 // Provide alias of __attribute__ like mingw32-gcc. 2469 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2470 } 2471 }; 2472 } // end anonymous namespace 2473 2474 namespace { 2475 // x86-32 Cygwin target 2476 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2477 public: 2478 CygwinX86_32TargetInfo(const std::string& triple) 2479 : X86_32TargetInfo(triple) { 2480 TLSSupported = false; 2481 WCharType = UnsignedShort; 2482 DoubleAlign = LongLongAlign = 64; 2483 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2484 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2485 "a0:0:64-f80:32:32-n8:16:32-S32"; 2486 } 2487 virtual void getTargetDefines(const LangOptions &Opts, 2488 MacroBuilder &Builder) const { 2489 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2490 Builder.defineMacro("__CYGWIN__"); 2491 Builder.defineMacro("__CYGWIN32__"); 2492 DefineStd(Builder, "unix", Opts); 2493 if (Opts.CPlusPlus) 2494 Builder.defineMacro("_GNU_SOURCE"); 2495 } 2496 }; 2497 } // end anonymous namespace 2498 2499 namespace { 2500 // x86-32 Haiku target 2501 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2502 public: 2503 HaikuX86_32TargetInfo(const std::string& triple) 2504 : X86_32TargetInfo(triple) { 2505 SizeType = UnsignedLong; 2506 IntPtrType = SignedLong; 2507 PtrDiffType = SignedLong; 2508 this->UserLabelPrefix = ""; 2509 } 2510 virtual void getTargetDefines(const LangOptions &Opts, 2511 MacroBuilder &Builder) const { 2512 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2513 Builder.defineMacro("__INTEL__"); 2514 Builder.defineMacro("__HAIKU__"); 2515 } 2516 }; 2517 } // end anonymous namespace 2518 2519 // RTEMS Target 2520 template<typename Target> 2521 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2522 protected: 2523 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2524 MacroBuilder &Builder) const { 2525 // RTEMS defines; list based off of gcc output 2526 2527 Builder.defineMacro("__rtems__"); 2528 Builder.defineMacro("__ELF__"); 2529 } 2530 public: 2531 RTEMSTargetInfo(const std::string &triple) 2532 : OSTargetInfo<Target>(triple) { 2533 this->UserLabelPrefix = ""; 2534 2535 llvm::Triple Triple(triple); 2536 switch (Triple.getArch()) { 2537 default: 2538 case llvm::Triple::x86: 2539 // this->MCountName = ".mcount"; 2540 break; 2541 case llvm::Triple::mips: 2542 case llvm::Triple::mipsel: 2543 case llvm::Triple::ppc: 2544 case llvm::Triple::ppc64: 2545 // this->MCountName = "_mcount"; 2546 break; 2547 case llvm::Triple::arm: 2548 // this->MCountName = "__mcount"; 2549 break; 2550 } 2551 2552 } 2553 }; 2554 2555 namespace { 2556 // x86-32 RTEMS target 2557 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2558 public: 2559 RTEMSX86_32TargetInfo(const std::string& triple) 2560 : X86_32TargetInfo(triple) { 2561 SizeType = UnsignedLong; 2562 IntPtrType = SignedLong; 2563 PtrDiffType = SignedLong; 2564 this->UserLabelPrefix = ""; 2565 } 2566 virtual void getTargetDefines(const LangOptions &Opts, 2567 MacroBuilder &Builder) const { 2568 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2569 Builder.defineMacro("__INTEL__"); 2570 Builder.defineMacro("__rtems__"); 2571 } 2572 }; 2573 } // end anonymous namespace 2574 2575 namespace { 2576 // x86-64 generic target 2577 class X86_64TargetInfo : public X86TargetInfo { 2578 public: 2579 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2580 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2581 LongDoubleWidth = 128; 2582 LongDoubleAlign = 128; 2583 LargeArrayMinWidth = 128; 2584 LargeArrayAlign = 128; 2585 SuitableAlign = 128; 2586 IntMaxType = SignedLong; 2587 UIntMaxType = UnsignedLong; 2588 Int64Type = SignedLong; 2589 RegParmMax = 6; 2590 2591 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2592 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2593 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2594 2595 // Use fpret only for long double. 2596 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2597 2598 // Use fp2ret for _Complex long double. 2599 ComplexLongDoubleUsesFP2Ret = true; 2600 2601 // x86-64 has atomics up to 16 bytes. 2602 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2603 // on CPUs with cmpxchg16b 2604 MaxAtomicPromoteWidth = 128; 2605 MaxAtomicInlineWidth = 64; 2606 } 2607 virtual const char *getVAListDeclaration() const { 2608 return "typedef struct __va_list_tag {" 2609 " unsigned gp_offset;" 2610 " unsigned fp_offset;" 2611 " void* overflow_arg_area;" 2612 " void* reg_save_area;" 2613 "} __va_list_tag;" 2614 "typedef __va_list_tag __builtin_va_list[1];"; 2615 } 2616 2617 int getEHDataRegisterNumber(unsigned RegNo) const { 2618 if (RegNo == 0) return 0; 2619 if (RegNo == 1) return 1; 2620 return -1; 2621 } 2622 }; 2623 } // end anonymous namespace 2624 2625 namespace { 2626 // x86-64 Windows target 2627 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2628 public: 2629 WindowsX86_64TargetInfo(const std::string& triple) 2630 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2631 TLSSupported = false; 2632 WCharType = UnsignedShort; 2633 LongWidth = LongAlign = 32; 2634 DoubleAlign = LongLongAlign = 64; 2635 IntMaxType = SignedLongLong; 2636 UIntMaxType = UnsignedLongLong; 2637 Int64Type = SignedLongLong; 2638 SizeType = UnsignedLongLong; 2639 PtrDiffType = SignedLongLong; 2640 IntPtrType = SignedLongLong; 2641 this->UserLabelPrefix = ""; 2642 } 2643 virtual void getTargetDefines(const LangOptions &Opts, 2644 MacroBuilder &Builder) const { 2645 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2646 Builder.defineMacro("_WIN64"); 2647 } 2648 virtual const char *getVAListDeclaration() const { 2649 return "typedef char* __builtin_va_list;"; 2650 } 2651 }; 2652 } // end anonymous namespace 2653 2654 namespace { 2655 // x86-64 Windows Visual Studio target 2656 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2657 public: 2658 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2659 : WindowsX86_64TargetInfo(triple) { 2660 LongDoubleWidth = LongDoubleAlign = 64; 2661 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2662 } 2663 virtual void getTargetDefines(const LangOptions &Opts, 2664 MacroBuilder &Builder) const { 2665 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2666 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2667 Builder.defineMacro("_M_X64"); 2668 Builder.defineMacro("_M_AMD64"); 2669 } 2670 }; 2671 } // end anonymous namespace 2672 2673 namespace { 2674 // x86-64 MinGW target 2675 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2676 public: 2677 MinGWX86_64TargetInfo(const std::string& triple) 2678 : WindowsX86_64TargetInfo(triple) { 2679 } 2680 virtual void getTargetDefines(const LangOptions &Opts, 2681 MacroBuilder &Builder) const { 2682 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2683 DefineStd(Builder, "WIN64", Opts); 2684 Builder.defineMacro("__MSVCRT__"); 2685 Builder.defineMacro("__MINGW32__"); 2686 Builder.defineMacro("__MINGW64__"); 2687 2688 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2689 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2690 if (Opts.MicrosoftExt) 2691 // Provide "as-is" __declspec. 2692 Builder.defineMacro("__declspec", "__declspec"); 2693 else 2694 // Provide alias of __attribute__ like mingw32-gcc. 2695 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2696 } 2697 }; 2698 } // end anonymous namespace 2699 2700 namespace { 2701 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2702 public: 2703 DarwinX86_64TargetInfo(const std::string& triple) 2704 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2705 Int64Type = SignedLongLong; 2706 } 2707 }; 2708 } // end anonymous namespace 2709 2710 namespace { 2711 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2712 public: 2713 OpenBSDX86_64TargetInfo(const std::string& triple) 2714 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2715 IntMaxType = SignedLongLong; 2716 UIntMaxType = UnsignedLongLong; 2717 Int64Type = SignedLongLong; 2718 } 2719 }; 2720 } // end anonymous namespace 2721 2722 namespace { 2723 class ARMTargetInfo : public TargetInfo { 2724 // Possible FPU choices. 2725 enum FPUMode { 2726 NoFPU, 2727 VFP2FPU, 2728 VFP3FPU, 2729 NeonFPU 2730 }; 2731 2732 static bool FPUModeIsVFP(FPUMode Mode) { 2733 return Mode >= VFP2FPU && Mode <= NeonFPU; 2734 } 2735 2736 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 2737 static const char * const GCCRegNames[]; 2738 2739 std::string ABI, CPU; 2740 2741 unsigned FPU : 3; 2742 2743 unsigned IsThumb : 1; 2744 2745 // Initialized via features. 2746 unsigned SoftFloat : 1; 2747 unsigned SoftFloatABI : 1; 2748 2749 static const Builtin::Info BuiltinInfo[]; 2750 2751 public: 2752 ARMTargetInfo(const std::string &TripleStr) 2753 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s") 2754 { 2755 BigEndian = false; 2756 SizeType = UnsignedInt; 2757 PtrDiffType = SignedInt; 2758 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 2759 WCharType = UnsignedInt; 2760 2761 // {} in inline assembly are neon specifiers, not assembly variant 2762 // specifiers. 2763 NoAsmVariants = true; 2764 2765 // FIXME: Should we just treat this as a feature? 2766 IsThumb = getTriple().getArchName().startswith("thumb"); 2767 if (IsThumb) { 2768 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2769 // so set preferred for small types to 32. 2770 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2771 "i64:64:64-f32:32:32-f64:64:64-" 2772 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 2773 } else { 2774 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2775 "i64:64:64-f32:32:32-f64:64:64-" 2776 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 2777 } 2778 2779 // ARM targets default to using the ARM C++ ABI. 2780 CXXABI = CXXABI_ARM; 2781 2782 // ARM has atomics up to 8 bytes 2783 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 2784 MaxAtomicPromoteWidth = 64; 2785 2786 // Do force alignment of members that follow zero length bitfields. If 2787 // the alignment of the zero-length bitfield is greater than the member 2788 // that follows it, `bar', `bar' will be aligned as the type of the 2789 // zero length bitfield. 2790 UseZeroLengthBitfieldAlignment = true; 2791 } 2792 virtual const char *getABI() const { return ABI.c_str(); } 2793 virtual bool setABI(const std::string &Name) { 2794 ABI = Name; 2795 2796 // The defaults (above) are for AAPCS, check if we need to change them. 2797 // 2798 // FIXME: We need support for -meabi... we could just mangle it into the 2799 // name. 2800 if (Name == "apcs-gnu") { 2801 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 2802 SizeType = UnsignedLong; 2803 2804 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 2805 WCharType = SignedInt; 2806 2807 // Do not respect the alignment of bit-field types when laying out 2808 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 2809 UseBitFieldTypeAlignment = false; 2810 2811 /// gcc forces the alignment to 4 bytes, regardless of the type of the 2812 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 2813 /// gcc. 2814 ZeroLengthBitfieldBoundary = 32; 2815 2816 if (IsThumb) { 2817 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2818 // so set preferred for small types to 32. 2819 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2820 "i64:32:64-f32:32:32-f64:32:64-" 2821 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2822 } else { 2823 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2824 "i64:32:64-f32:32:32-f64:32:64-" 2825 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2826 } 2827 2828 // FIXME: Override "preferred align" for double and long long. 2829 } else if (Name == "aapcs") { 2830 // FIXME: Enumerated types are variable width in straight AAPCS. 2831 } else if (Name == "aapcs-linux") { 2832 ; 2833 } else 2834 return false; 2835 2836 return true; 2837 } 2838 2839 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2840 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 2841 Features["vfp2"] = true; 2842 else if (CPU == "cortex-a8" || CPU == "cortex-a9") 2843 Features["neon"] = true; 2844 } 2845 2846 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 2847 StringRef Name, 2848 bool Enabled) const { 2849 if (Name == "soft-float" || Name == "soft-float-abi" || 2850 Name == "vfp2" || Name == "vfp3" || Name == "neon" || Name == "d16" || 2851 Name == "neonfp") { 2852 Features[Name] = Enabled; 2853 } else 2854 return false; 2855 2856 return true; 2857 } 2858 2859 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 2860 FPU = NoFPU; 2861 SoftFloat = SoftFloatABI = false; 2862 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 2863 if (Features[i] == "+soft-float") 2864 SoftFloat = true; 2865 else if (Features[i] == "+soft-float-abi") 2866 SoftFloatABI = true; 2867 else if (Features[i] == "+vfp2") 2868 FPU = VFP2FPU; 2869 else if (Features[i] == "+vfp3") 2870 FPU = VFP3FPU; 2871 else if (Features[i] == "+neon") 2872 FPU = NeonFPU; 2873 } 2874 2875 // Remove front-end specific options which the backend handles differently. 2876 std::vector<std::string>::iterator it; 2877 it = std::find(Features.begin(), Features.end(), "+soft-float"); 2878 if (it != Features.end()) 2879 Features.erase(it); 2880 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 2881 if (it != Features.end()) 2882 Features.erase(it); 2883 } 2884 2885 virtual bool hasFeature(StringRef Feature) const { 2886 return llvm::StringSwitch<bool>(Feature) 2887 .Case("arm", true) 2888 .Case("softfloat", SoftFloat) 2889 .Case("thumb", IsThumb) 2890 .Case("neon", FPU == NeonFPU && !SoftFloat && 2891 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 2892 .Default(false); 2893 } 2894 static const char *getCPUDefineSuffix(StringRef Name) { 2895 return llvm::StringSwitch<const char*>(Name) 2896 .Cases("arm8", "arm810", "4") 2897 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 2898 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 2899 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 2900 .Case("ep9312", "4T") 2901 .Cases("arm10tdmi", "arm1020t", "5T") 2902 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 2903 .Case("arm926ej-s", "5TEJ") 2904 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 2905 .Cases("xscale", "iwmmxt", "5TE") 2906 .Case("arm1136j-s", "6J") 2907 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 2908 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 2909 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 2910 .Cases("cortex-a8", "cortex-a9", "7A") 2911 .Case("cortex-m3", "7M") 2912 .Case("cortex-m4", "7M") 2913 .Case("cortex-m0", "6M") 2914 .Default(0); 2915 } 2916 virtual bool setCPU(const std::string &Name) { 2917 if (!getCPUDefineSuffix(Name)) 2918 return false; 2919 2920 CPU = Name; 2921 return true; 2922 } 2923 virtual void getTargetDefines(const LangOptions &Opts, 2924 MacroBuilder &Builder) const { 2925 // Target identification. 2926 Builder.defineMacro("__arm"); 2927 Builder.defineMacro("__arm__"); 2928 2929 // Target properties. 2930 Builder.defineMacro("__ARMEL__"); 2931 Builder.defineMacro("__LITTLE_ENDIAN__"); 2932 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2933 2934 StringRef CPUArch = getCPUDefineSuffix(CPU); 2935 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 2936 2937 // Subtarget options. 2938 2939 // FIXME: It's more complicated than this and we don't really support 2940 // interworking. 2941 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 2942 Builder.defineMacro("__THUMB_INTERWORK__"); 2943 2944 if (ABI == "aapcs" || ABI == "aapcs-linux") 2945 Builder.defineMacro("__ARM_EABI__"); 2946 2947 if (SoftFloat) 2948 Builder.defineMacro("__SOFTFP__"); 2949 2950 if (CPU == "xscale") 2951 Builder.defineMacro("__XSCALE__"); 2952 2953 bool IsARMv7 = CPUArch.startswith("7"); 2954 if (IsThumb) { 2955 Builder.defineMacro("__THUMBEL__"); 2956 Builder.defineMacro("__thumb__"); 2957 if (CPUArch == "6T2" || IsARMv7) 2958 Builder.defineMacro("__thumb2__"); 2959 } 2960 2961 // Note, this is always on in gcc, even though it doesn't make sense. 2962 Builder.defineMacro("__APCS_32__"); 2963 2964 if (FPUModeIsVFP((FPUMode) FPU)) 2965 Builder.defineMacro("__VFP_FP__"); 2966 2967 // This only gets set when Neon instructions are actually available, unlike 2968 // the VFP define, hence the soft float and arch check. This is subtly 2969 // different from gcc, we follow the intent which was that it should be set 2970 // when Neon instructions are actually available. 2971 if (FPU == NeonFPU && !SoftFloat && IsARMv7) 2972 Builder.defineMacro("__ARM_NEON__"); 2973 } 2974 virtual void getTargetBuiltins(const Builtin::Info *&Records, 2975 unsigned &NumRecords) const { 2976 Records = BuiltinInfo; 2977 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 2978 } 2979 virtual bool isCLZForZeroUndef() const { return false; } 2980 virtual const char *getVAListDeclaration() const { 2981 return "typedef void* __builtin_va_list;"; 2982 } 2983 virtual void getGCCRegNames(const char * const *&Names, 2984 unsigned &NumNames) const; 2985 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 2986 unsigned &NumAliases) const; 2987 virtual bool validateAsmConstraint(const char *&Name, 2988 TargetInfo::ConstraintInfo &Info) const { 2989 // FIXME: Check if this is complete 2990 switch (*Name) { 2991 default: 2992 case 'l': // r0-r7 2993 case 'h': // r8-r15 2994 case 'w': // VFP Floating point register single precision 2995 case 'P': // VFP Floating point register double precision 2996 Info.setAllowsRegister(); 2997 return true; 2998 case 'Q': // A memory address that is a single base register. 2999 Info.setAllowsMemory(); 3000 return true; 3001 case 'U': // a memory reference... 3002 switch (Name[1]) { 3003 case 'q': // ...ARMV4 ldrsb 3004 case 'v': // ...VFP load/store (reg+constant offset) 3005 case 'y': // ...iWMMXt load/store 3006 case 't': // address valid for load/store opaque types wider 3007 // than 128-bits 3008 case 'n': // valid address for Neon doubleword vector load/store 3009 case 'm': // valid address for Neon element and structure load/store 3010 case 's': // valid address for non-offset loads/stores of quad-word 3011 // values in four ARM registers 3012 Info.setAllowsMemory(); 3013 Name++; 3014 return true; 3015 } 3016 } 3017 return false; 3018 } 3019 virtual std::string convertConstraint(const char *&Constraint) const { 3020 std::string R; 3021 switch (*Constraint) { 3022 case 'U': // Two-character constraint; add "^" hint for later parsing. 3023 R = std::string("^") + std::string(Constraint, 2); 3024 Constraint++; 3025 break; 3026 case 'p': // 'p' should be translated to 'r' by default. 3027 R = std::string("r"); 3028 break; 3029 default: 3030 return std::string(1, *Constraint); 3031 } 3032 return R; 3033 } 3034 virtual const char *getClobbers() const { 3035 // FIXME: Is this really right? 3036 return ""; 3037 } 3038 }; 3039 3040 const char * const ARMTargetInfo::GCCRegNames[] = { 3041 // Integer registers 3042 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3043 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3044 3045 // Float registers 3046 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3047 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3048 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3049 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3050 3051 // Double registers 3052 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3053 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3054 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3055 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3056 3057 // Quad registers 3058 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3059 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3060 }; 3061 3062 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3063 unsigned &NumNames) const { 3064 Names = GCCRegNames; 3065 NumNames = llvm::array_lengthof(GCCRegNames); 3066 } 3067 3068 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3069 { { "a1" }, "r0" }, 3070 { { "a2" }, "r1" }, 3071 { { "a3" }, "r2" }, 3072 { { "a4" }, "r3" }, 3073 { { "v1" }, "r4" }, 3074 { { "v2" }, "r5" }, 3075 { { "v3" }, "r6" }, 3076 { { "v4" }, "r7" }, 3077 { { "v5" }, "r8" }, 3078 { { "v6", "rfp" }, "r9" }, 3079 { { "sl" }, "r10" }, 3080 { { "fp" }, "r11" }, 3081 { { "ip" }, "r12" }, 3082 { { "r13" }, "sp" }, 3083 { { "r14" }, "lr" }, 3084 { { "r15" }, "pc" }, 3085 // The S, D and Q registers overlap, but aren't really aliases; we 3086 // don't want to substitute one of these for a different-sized one. 3087 }; 3088 3089 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3090 unsigned &NumAliases) const { 3091 Aliases = GCCRegAliases; 3092 NumAliases = llvm::array_lengthof(GCCRegAliases); 3093 } 3094 3095 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3096 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3097 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3098 ALL_LANGUAGES }, 3099 #include "clang/Basic/BuiltinsARM.def" 3100 }; 3101 } // end anonymous namespace. 3102 3103 namespace { 3104 class DarwinARMTargetInfo : 3105 public DarwinTargetInfo<ARMTargetInfo> { 3106 protected: 3107 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3108 MacroBuilder &Builder) const { 3109 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3110 } 3111 3112 public: 3113 DarwinARMTargetInfo(const std::string& triple) 3114 : DarwinTargetInfo<ARMTargetInfo>(triple) { 3115 HasAlignMac68kSupport = true; 3116 // iOS always has 64-bit atomic instructions. 3117 // FIXME: This should be based off of the target features in ARMTargetInfo. 3118 MaxAtomicInlineWidth = 64; 3119 } 3120 }; 3121 } // end anonymous namespace. 3122 3123 3124 namespace { 3125 // Hexagon abstract base class 3126 class HexagonTargetInfo : public TargetInfo { 3127 static const Builtin::Info BuiltinInfo[]; 3128 static const char * const GCCRegNames[]; 3129 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3130 std::string CPU; 3131 public: 3132 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3133 BigEndian = false; 3134 DescriptionString = ("e-p:32:32:32-" 3135 "i64:64:64-i32:32:32-i16:16:16-i1:32:32" 3136 "f64:64:64-f32:32:32-a0:0-n32"); 3137 3138 // {} in inline assembly are packet specifiers, not assembly variant 3139 // specifiers. 3140 NoAsmVariants = true; 3141 } 3142 3143 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3144 unsigned &NumRecords) const { 3145 Records = BuiltinInfo; 3146 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3147 } 3148 3149 virtual bool validateAsmConstraint(const char *&Name, 3150 TargetInfo::ConstraintInfo &Info) const { 3151 return true; 3152 } 3153 3154 virtual void getTargetDefines(const LangOptions &Opts, 3155 MacroBuilder &Builder) const; 3156 3157 virtual bool hasFeature(StringRef Feature) const { 3158 return Feature == "hexagon"; 3159 } 3160 3161 virtual const char *getVAListDeclaration() const { 3162 return "typedef char* __builtin_va_list;"; 3163 } 3164 virtual void getGCCRegNames(const char * const *&Names, 3165 unsigned &NumNames) const; 3166 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3167 unsigned &NumAliases) const; 3168 virtual const char *getClobbers() const { 3169 return ""; 3170 } 3171 3172 static const char *getHexagonCPUSuffix(StringRef Name) { 3173 return llvm::StringSwitch<const char*>(Name) 3174 .Case("hexagonv2", "2") 3175 .Case("hexagonv3", "3") 3176 .Case("hexagonv4", "4") 3177 .Case("hexagonv5", "5") 3178 .Default(0); 3179 } 3180 3181 virtual bool setCPU(const std::string &Name) { 3182 if (!getHexagonCPUSuffix(Name)) 3183 return false; 3184 3185 CPU = Name; 3186 return true; 3187 } 3188 }; 3189 3190 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3191 MacroBuilder &Builder) const { 3192 Builder.defineMacro("qdsp6"); 3193 Builder.defineMacro("__qdsp6", "1"); 3194 Builder.defineMacro("__qdsp6__", "1"); 3195 3196 Builder.defineMacro("hexagon"); 3197 Builder.defineMacro("__hexagon", "1"); 3198 Builder.defineMacro("__hexagon__", "1"); 3199 3200 if(CPU == "hexagonv1") { 3201 Builder.defineMacro("__HEXAGON_V1__"); 3202 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3203 if(Opts.HexagonQdsp6Compat) { 3204 Builder.defineMacro("__QDSP6_V1__"); 3205 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3206 } 3207 } 3208 else if(CPU == "hexagonv2") { 3209 Builder.defineMacro("__HEXAGON_V2__"); 3210 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3211 if(Opts.HexagonQdsp6Compat) { 3212 Builder.defineMacro("__QDSP6_V2__"); 3213 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3214 } 3215 } 3216 else if(CPU == "hexagonv3") { 3217 Builder.defineMacro("__HEXAGON_V3__"); 3218 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3219 if(Opts.HexagonQdsp6Compat) { 3220 Builder.defineMacro("__QDSP6_V3__"); 3221 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3222 } 3223 } 3224 else if(CPU == "hexagonv4") { 3225 Builder.defineMacro("__HEXAGON_V4__"); 3226 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3227 if(Opts.HexagonQdsp6Compat) { 3228 Builder.defineMacro("__QDSP6_V4__"); 3229 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3230 } 3231 } 3232 else if(CPU == "hexagonv5") { 3233 Builder.defineMacro("__HEXAGON_V5__"); 3234 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3235 if(Opts.HexagonQdsp6Compat) { 3236 Builder.defineMacro("__QDSP6_V5__"); 3237 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3238 } 3239 } 3240 } 3241 3242 const char * const HexagonTargetInfo::GCCRegNames[] = { 3243 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3244 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3245 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3246 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3247 "p0", "p1", "p2", "p3", 3248 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3249 }; 3250 3251 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3252 unsigned &NumNames) const { 3253 Names = GCCRegNames; 3254 NumNames = llvm::array_lengthof(GCCRegNames); 3255 } 3256 3257 3258 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3259 { { "sp" }, "r29" }, 3260 { { "fp" }, "r30" }, 3261 { { "lr" }, "r31" }, 3262 }; 3263 3264 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3265 unsigned &NumAliases) const { 3266 Aliases = GCCRegAliases; 3267 NumAliases = llvm::array_lengthof(GCCRegAliases); 3268 } 3269 3270 3271 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3272 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3273 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3274 ALL_LANGUAGES }, 3275 #include "clang/Basic/BuiltinsHexagon.def" 3276 }; 3277 } 3278 3279 3280 namespace { 3281 class SparcV8TargetInfo : public TargetInfo { 3282 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3283 static const char * const GCCRegNames[]; 3284 bool SoftFloat; 3285 public: 3286 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3287 // FIXME: Support Sparc quad-precision long double? 3288 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3289 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3290 } 3291 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3292 StringRef Name, 3293 bool Enabled) const { 3294 if (Name == "soft-float") 3295 Features[Name] = Enabled; 3296 else 3297 return false; 3298 3299 return true; 3300 } 3301 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3302 SoftFloat = false; 3303 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3304 if (Features[i] == "+soft-float") 3305 SoftFloat = true; 3306 } 3307 virtual void getTargetDefines(const LangOptions &Opts, 3308 MacroBuilder &Builder) const { 3309 DefineStd(Builder, "sparc", Opts); 3310 Builder.defineMacro("__sparcv8"); 3311 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3312 3313 if (SoftFloat) 3314 Builder.defineMacro("SOFT_FLOAT", "1"); 3315 } 3316 3317 virtual bool hasFeature(StringRef Feature) const { 3318 return llvm::StringSwitch<bool>(Feature) 3319 .Case("softfloat", SoftFloat) 3320 .Case("sparc", true) 3321 .Default(false); 3322 } 3323 3324 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3325 unsigned &NumRecords) const { 3326 // FIXME: Implement! 3327 } 3328 virtual const char *getVAListDeclaration() const { 3329 return "typedef void* __builtin_va_list;"; 3330 } 3331 virtual void getGCCRegNames(const char * const *&Names, 3332 unsigned &NumNames) const; 3333 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3334 unsigned &NumAliases) const; 3335 virtual bool validateAsmConstraint(const char *&Name, 3336 TargetInfo::ConstraintInfo &info) const { 3337 // FIXME: Implement! 3338 return false; 3339 } 3340 virtual const char *getClobbers() const { 3341 // FIXME: Implement! 3342 return ""; 3343 } 3344 }; 3345 3346 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3347 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3348 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3349 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3350 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3351 }; 3352 3353 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3354 unsigned &NumNames) const { 3355 Names = GCCRegNames; 3356 NumNames = llvm::array_lengthof(GCCRegNames); 3357 } 3358 3359 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3360 { { "g0" }, "r0" }, 3361 { { "g1" }, "r1" }, 3362 { { "g2" }, "r2" }, 3363 { { "g3" }, "r3" }, 3364 { { "g4" }, "r4" }, 3365 { { "g5" }, "r5" }, 3366 { { "g6" }, "r6" }, 3367 { { "g7" }, "r7" }, 3368 { { "o0" }, "r8" }, 3369 { { "o1" }, "r9" }, 3370 { { "o2" }, "r10" }, 3371 { { "o3" }, "r11" }, 3372 { { "o4" }, "r12" }, 3373 { { "o5" }, "r13" }, 3374 { { "o6", "sp" }, "r14" }, 3375 { { "o7" }, "r15" }, 3376 { { "l0" }, "r16" }, 3377 { { "l1" }, "r17" }, 3378 { { "l2" }, "r18" }, 3379 { { "l3" }, "r19" }, 3380 { { "l4" }, "r20" }, 3381 { { "l5" }, "r21" }, 3382 { { "l6" }, "r22" }, 3383 { { "l7" }, "r23" }, 3384 { { "i0" }, "r24" }, 3385 { { "i1" }, "r25" }, 3386 { { "i2" }, "r26" }, 3387 { { "i3" }, "r27" }, 3388 { { "i4" }, "r28" }, 3389 { { "i5" }, "r29" }, 3390 { { "i6", "fp" }, "r30" }, 3391 { { "i7" }, "r31" }, 3392 }; 3393 3394 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3395 unsigned &NumAliases) const { 3396 Aliases = GCCRegAliases; 3397 NumAliases = llvm::array_lengthof(GCCRegAliases); 3398 } 3399 } // end anonymous namespace. 3400 3401 namespace { 3402 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3403 public: 3404 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3405 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3406 SizeType = UnsignedInt; 3407 PtrDiffType = SignedInt; 3408 } 3409 }; 3410 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3411 public: 3412 SolarisSparcV8TargetInfo(const std::string& triple) : 3413 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3414 SizeType = UnsignedInt; 3415 PtrDiffType = SignedInt; 3416 } 3417 }; 3418 } // end anonymous namespace. 3419 3420 namespace { 3421 class MSP430TargetInfo : public TargetInfo { 3422 static const char * const GCCRegNames[]; 3423 public: 3424 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3425 BigEndian = false; 3426 TLSSupported = false; 3427 IntWidth = 16; IntAlign = 16; 3428 LongWidth = 32; LongLongWidth = 64; 3429 LongAlign = LongLongAlign = 16; 3430 PointerWidth = 16; PointerAlign = 16; 3431 SuitableAlign = 16; 3432 SizeType = UnsignedInt; 3433 IntMaxType = SignedLong; 3434 UIntMaxType = UnsignedLong; 3435 IntPtrType = SignedShort; 3436 PtrDiffType = SignedInt; 3437 SigAtomicType = SignedLong; 3438 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3439 } 3440 virtual void getTargetDefines(const LangOptions &Opts, 3441 MacroBuilder &Builder) const { 3442 Builder.defineMacro("MSP430"); 3443 Builder.defineMacro("__MSP430__"); 3444 // FIXME: defines for different 'flavours' of MCU 3445 } 3446 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3447 unsigned &NumRecords) const { 3448 // FIXME: Implement. 3449 Records = 0; 3450 NumRecords = 0; 3451 } 3452 virtual bool hasFeature(StringRef Feature) const { 3453 return Feature == "msp430"; 3454 } 3455 virtual void getGCCRegNames(const char * const *&Names, 3456 unsigned &NumNames) const; 3457 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3458 unsigned &NumAliases) const { 3459 // No aliases. 3460 Aliases = 0; 3461 NumAliases = 0; 3462 } 3463 virtual bool validateAsmConstraint(const char *&Name, 3464 TargetInfo::ConstraintInfo &info) const { 3465 // No target constraints for now. 3466 return false; 3467 } 3468 virtual const char *getClobbers() const { 3469 // FIXME: Is this really right? 3470 return ""; 3471 } 3472 virtual const char *getVAListDeclaration() const { 3473 // FIXME: implement 3474 return "typedef char* __builtin_va_list;"; 3475 } 3476 }; 3477 3478 const char * const MSP430TargetInfo::GCCRegNames[] = { 3479 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3480 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3481 }; 3482 3483 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3484 unsigned &NumNames) const { 3485 Names = GCCRegNames; 3486 NumNames = llvm::array_lengthof(GCCRegNames); 3487 } 3488 } 3489 3490 namespace { 3491 3492 // LLVM and Clang cannot be used directly to output native binaries for 3493 // target, but is used to compile C code to llvm bitcode with correct 3494 // type and alignment information. 3495 // 3496 // TCE uses the llvm bitcode as input and uses it for generating customized 3497 // target processor and program binary. TCE co-design environment is 3498 // publicly available in http://tce.cs.tut.fi 3499 3500 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3501 3, // opencl_global 3502 4, // opencl_local 3503 5, // opencl_constant 3504 0, // cuda_device 3505 0, // cuda_constant 3506 0 // cuda_shared 3507 }; 3508 3509 class TCETargetInfo : public TargetInfo{ 3510 public: 3511 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3512 TLSSupported = false; 3513 IntWidth = 32; 3514 LongWidth = LongLongWidth = 32; 3515 PointerWidth = 32; 3516 IntAlign = 32; 3517 LongAlign = LongLongAlign = 32; 3518 PointerAlign = 32; 3519 SuitableAlign = 32; 3520 SizeType = UnsignedInt; 3521 IntMaxType = SignedLong; 3522 UIntMaxType = UnsignedLong; 3523 IntPtrType = SignedInt; 3524 PtrDiffType = SignedInt; 3525 FloatWidth = 32; 3526 FloatAlign = 32; 3527 DoubleWidth = 32; 3528 DoubleAlign = 32; 3529 LongDoubleWidth = 32; 3530 LongDoubleAlign = 32; 3531 FloatFormat = &llvm::APFloat::IEEEsingle; 3532 DoubleFormat = &llvm::APFloat::IEEEsingle; 3533 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3534 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3535 "i16:16:32-i32:32:32-i64:32:32-" 3536 "f32:32:32-f64:32:32-v64:32:32-" 3537 "v128:32:32-a0:0:32-n32"; 3538 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3539 } 3540 3541 virtual void getTargetDefines(const LangOptions &Opts, 3542 MacroBuilder &Builder) const { 3543 DefineStd(Builder, "tce", Opts); 3544 Builder.defineMacro("__TCE__"); 3545 Builder.defineMacro("__TCE_V1__"); 3546 } 3547 virtual bool hasFeature(StringRef Feature) const { 3548 return Feature == "tce"; 3549 } 3550 3551 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3552 unsigned &NumRecords) const {} 3553 virtual const char *getClobbers() const { 3554 return ""; 3555 } 3556 virtual const char *getVAListDeclaration() const { 3557 return "typedef void* __builtin_va_list;"; 3558 } 3559 virtual void getGCCRegNames(const char * const *&Names, 3560 unsigned &NumNames) const {} 3561 virtual bool validateAsmConstraint(const char *&Name, 3562 TargetInfo::ConstraintInfo &info) const { 3563 return true; 3564 } 3565 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3566 unsigned &NumAliases) const {} 3567 }; 3568 } 3569 3570 namespace { 3571 class MipsTargetInfoBase : public TargetInfo { 3572 std::string CPU; 3573 bool SoftFloat; 3574 bool SingleFloat; 3575 3576 protected: 3577 std::string ABI; 3578 3579 public: 3580 MipsTargetInfoBase(const std::string& triple, 3581 const std::string& ABIStr, 3582 const std::string& CPUStr) 3583 : TargetInfo(triple), 3584 CPU(CPUStr), 3585 SoftFloat(false), SingleFloat(false), 3586 ABI(ABIStr) 3587 {} 3588 3589 virtual const char *getABI() const { return ABI.c_str(); } 3590 virtual bool setABI(const std::string &Name) = 0; 3591 virtual bool setCPU(const std::string &Name) { 3592 CPU = Name; 3593 return true; 3594 } 3595 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3596 Features[ABI] = true; 3597 Features[CPU] = true; 3598 } 3599 3600 virtual void getArchDefines(const LangOptions &Opts, 3601 MacroBuilder &Builder) const { 3602 if (SoftFloat && SingleFloat) 3603 llvm_unreachable("Invalid float ABI for Mips."); 3604 else if (SoftFloat) 3605 Builder.defineMacro("__mips_soft_float", Twine(1)); 3606 else { 3607 Builder.defineMacro("__mips_hard_float", Twine(1)); 3608 if (SingleFloat) 3609 Builder.defineMacro("__mips_single_float", Twine(1)); 3610 } 3611 3612 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 3613 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 3614 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 3615 } 3616 3617 virtual void getTargetDefines(const LangOptions &Opts, 3618 MacroBuilder &Builder) const = 0; 3619 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3620 unsigned &NumRecords) const { 3621 // FIXME: Implement! 3622 } 3623 virtual bool hasFeature(StringRef Feature) const { 3624 return Feature == "mips"; 3625 } 3626 virtual const char *getVAListDeclaration() const { 3627 return "typedef void* __builtin_va_list;"; 3628 } 3629 virtual void getGCCRegNames(const char * const *&Names, 3630 unsigned &NumNames) const { 3631 static const char * const GCCRegNames[] = { 3632 // CPU register names 3633 // Must match second column of GCCRegAliases 3634 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3635 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3636 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3637 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 3638 // Floating point register names 3639 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3640 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3641 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3642 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 3643 // Hi/lo and condition register names 3644 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 3645 "$fcc5","$fcc6","$fcc7" 3646 }; 3647 Names = GCCRegNames; 3648 NumNames = llvm::array_lengthof(GCCRegNames); 3649 } 3650 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3651 unsigned &NumAliases) const = 0; 3652 virtual bool validateAsmConstraint(const char *&Name, 3653 TargetInfo::ConstraintInfo &Info) const { 3654 switch (*Name) { 3655 default: 3656 return false; 3657 3658 case 'r': // CPU registers. 3659 case 'd': // Equivalent to "r" unless generating MIPS16 code. 3660 case 'y': // Equivalent to "r", backwards compatibility only. 3661 case 'f': // floating-point registers. 3662 case 'c': // $25 for indirect jumps 3663 case 'l': // lo register 3664 case 'x': // hilo register pair 3665 Info.setAllowsRegister(); 3666 return true; 3667 } 3668 } 3669 3670 virtual const char *getClobbers() const { 3671 // FIXME: Implement! 3672 return ""; 3673 } 3674 3675 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3676 StringRef Name, 3677 bool Enabled) const { 3678 if (Name == "soft-float" || Name == "single-float" || 3679 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 3680 Name == "mips32" || Name == "mips32r2" || 3681 Name == "mips64" || Name == "mips64r2") { 3682 Features[Name] = Enabled; 3683 return true; 3684 } 3685 return false; 3686 } 3687 3688 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3689 SoftFloat = false; 3690 SingleFloat = false; 3691 3692 for (std::vector<std::string>::iterator it = Features.begin(), 3693 ie = Features.end(); it != ie; ++it) { 3694 if (*it == "+single-float") { 3695 SingleFloat = true; 3696 break; 3697 } 3698 3699 if (*it == "+soft-float") { 3700 SoftFloat = true; 3701 // This option is front-end specific. 3702 // Do not need to pass it to the backend. 3703 Features.erase(it); 3704 break; 3705 } 3706 } 3707 } 3708 }; 3709 3710 class Mips32TargetInfoBase : public MipsTargetInfoBase { 3711 public: 3712 Mips32TargetInfoBase(const std::string& triple) : 3713 MipsTargetInfoBase(triple, "o32", "mips32") { 3714 SizeType = UnsignedInt; 3715 PtrDiffType = SignedInt; 3716 } 3717 virtual bool setABI(const std::string &Name) { 3718 if ((Name == "o32") || (Name == "eabi")) { 3719 ABI = Name; 3720 return true; 3721 } else 3722 return false; 3723 } 3724 virtual void getArchDefines(const LangOptions &Opts, 3725 MacroBuilder &Builder) const { 3726 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3727 3728 if (ABI == "o32") { 3729 Builder.defineMacro("__mips_o32"); 3730 Builder.defineMacro("_ABIO32", "1"); 3731 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 3732 } 3733 else if (ABI == "eabi") 3734 Builder.defineMacro("__mips_eabi"); 3735 else 3736 llvm_unreachable("Invalid ABI for Mips32."); 3737 } 3738 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3739 unsigned &NumAliases) const { 3740 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3741 { { "at" }, "$1" }, 3742 { { "v0" }, "$2" }, 3743 { { "v1" }, "$3" }, 3744 { { "a0" }, "$4" }, 3745 { { "a1" }, "$5" }, 3746 { { "a2" }, "$6" }, 3747 { { "a3" }, "$7" }, 3748 { { "t0" }, "$8" }, 3749 { { "t1" }, "$9" }, 3750 { { "t2" }, "$10" }, 3751 { { "t3" }, "$11" }, 3752 { { "t4" }, "$12" }, 3753 { { "t5" }, "$13" }, 3754 { { "t6" }, "$14" }, 3755 { { "t7" }, "$15" }, 3756 { { "s0" }, "$16" }, 3757 { { "s1" }, "$17" }, 3758 { { "s2" }, "$18" }, 3759 { { "s3" }, "$19" }, 3760 { { "s4" }, "$20" }, 3761 { { "s5" }, "$21" }, 3762 { { "s6" }, "$22" }, 3763 { { "s7" }, "$23" }, 3764 { { "t8" }, "$24" }, 3765 { { "t9" }, "$25" }, 3766 { { "k0" }, "$26" }, 3767 { { "k1" }, "$27" }, 3768 { { "gp" }, "$28" }, 3769 { { "sp","$sp" }, "$29" }, 3770 { { "fp","$fp" }, "$30" }, 3771 { { "ra" }, "$31" } 3772 }; 3773 Aliases = GCCRegAliases; 3774 NumAliases = llvm::array_lengthof(GCCRegAliases); 3775 } 3776 }; 3777 3778 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 3779 public: 3780 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3781 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3782 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3783 } 3784 virtual void getTargetDefines(const LangOptions &Opts, 3785 MacroBuilder &Builder) const { 3786 DefineStd(Builder, "mips", Opts); 3787 Builder.defineMacro("_mips"); 3788 DefineStd(Builder, "MIPSEB", Opts); 3789 Builder.defineMacro("_MIPSEB"); 3790 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3791 getArchDefines(Opts, Builder); 3792 } 3793 }; 3794 3795 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 3796 public: 3797 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3798 BigEndian = false; 3799 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3800 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3801 } 3802 virtual void getTargetDefines(const LangOptions &Opts, 3803 MacroBuilder &Builder) const { 3804 DefineStd(Builder, "mips", Opts); 3805 Builder.defineMacro("_mips"); 3806 DefineStd(Builder, "MIPSEL", Opts); 3807 Builder.defineMacro("_MIPSEL"); 3808 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3809 getArchDefines(Opts, Builder); 3810 } 3811 }; 3812 3813 class Mips64TargetInfoBase : public MipsTargetInfoBase { 3814 virtual void SetDescriptionString(const std::string &Name) = 0; 3815 public: 3816 Mips64TargetInfoBase(const std::string& triple) : 3817 MipsTargetInfoBase(triple, "n64", "mips64") { 3818 LongWidth = LongAlign = 64; 3819 PointerWidth = PointerAlign = 64; 3820 LongDoubleWidth = LongDoubleAlign = 128; 3821 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3822 SuitableAlign = 128; 3823 } 3824 virtual bool setABI(const std::string &Name) { 3825 SetDescriptionString(Name); 3826 3827 if (Name != "n32" && Name != "n64") 3828 return false; 3829 3830 ABI = Name; 3831 3832 if (Name == "n32") { 3833 LongWidth = LongAlign = 32; 3834 PointerWidth = PointerAlign = 32; 3835 } 3836 3837 return true; 3838 } 3839 virtual void getArchDefines(const LangOptions &Opts, 3840 MacroBuilder &Builder) const { 3841 MipsTargetInfoBase::getArchDefines(Opts, Builder); 3842 3843 if (ABI == "n32") { 3844 Builder.defineMacro("__mips_n32"); 3845 Builder.defineMacro("_ABIN32", "2"); 3846 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 3847 } 3848 else if (ABI == "n64") { 3849 Builder.defineMacro("__mips_n64"); 3850 Builder.defineMacro("_ABI64", "3"); 3851 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 3852 } 3853 else 3854 llvm_unreachable("Invalid ABI for Mips64."); 3855 } 3856 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3857 unsigned &NumAliases) const { 3858 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3859 { { "at" }, "$1" }, 3860 { { "v0" }, "$2" }, 3861 { { "v1" }, "$3" }, 3862 { { "a0" }, "$4" }, 3863 { { "a1" }, "$5" }, 3864 { { "a2" }, "$6" }, 3865 { { "a3" }, "$7" }, 3866 { { "a4" }, "$8" }, 3867 { { "a5" }, "$9" }, 3868 { { "a6" }, "$10" }, 3869 { { "a7" }, "$11" }, 3870 { { "t0" }, "$12" }, 3871 { { "t1" }, "$13" }, 3872 { { "t2" }, "$14" }, 3873 { { "t3" }, "$15" }, 3874 { { "s0" }, "$16" }, 3875 { { "s1" }, "$17" }, 3876 { { "s2" }, "$18" }, 3877 { { "s3" }, "$19" }, 3878 { { "s4" }, "$20" }, 3879 { { "s5" }, "$21" }, 3880 { { "s6" }, "$22" }, 3881 { { "s7" }, "$23" }, 3882 { { "t8" }, "$24" }, 3883 { { "t9" }, "$25" }, 3884 { { "k0" }, "$26" }, 3885 { { "k1" }, "$27" }, 3886 { { "gp" }, "$28" }, 3887 { { "sp","$sp" }, "$29" }, 3888 { { "fp","$fp" }, "$30" }, 3889 { { "ra" }, "$31" } 3890 }; 3891 Aliases = GCCRegAliases; 3892 NumAliases = llvm::array_lengthof(GCCRegAliases); 3893 } 3894 }; 3895 3896 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 3897 virtual void SetDescriptionString(const std::string &Name) { 3898 // Change DescriptionString only if ABI is n32. 3899 if (Name == "n32") 3900 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3901 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3902 "v64:64:64-n32"; 3903 } 3904 public: 3905 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 3906 // Default ABI is n64. 3907 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3908 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3909 "v64:64:64-n32"; 3910 } 3911 virtual void getTargetDefines(const LangOptions &Opts, 3912 MacroBuilder &Builder) const { 3913 DefineStd(Builder, "mips", Opts); 3914 Builder.defineMacro("_mips"); 3915 DefineStd(Builder, "MIPSEB", Opts); 3916 Builder.defineMacro("_MIPSEB"); 3917 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3918 getArchDefines(Opts, Builder); 3919 } 3920 }; 3921 3922 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 3923 virtual void SetDescriptionString(const std::string &Name) { 3924 // Change DescriptionString only if ABI is n32. 3925 if (Name == "n32") 3926 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3927 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 3928 "-v64:64:64-n32"; 3929 } 3930 public: 3931 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 3932 // Default ABI is n64. 3933 BigEndian = false; 3934 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3935 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 3936 "v64:64:64-n32"; 3937 } 3938 virtual void getTargetDefines(const LangOptions &Opts, 3939 MacroBuilder &Builder) const { 3940 DefineStd(Builder, "mips", Opts); 3941 Builder.defineMacro("_mips"); 3942 DefineStd(Builder, "MIPSEL", Opts); 3943 Builder.defineMacro("_MIPSEL"); 3944 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3945 getArchDefines(Opts, Builder); 3946 } 3947 }; 3948 } // end anonymous namespace. 3949 3950 namespace { 3951 class PNaClTargetInfo : public TargetInfo { 3952 public: 3953 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 3954 BigEndian = false; 3955 this->UserLabelPrefix = ""; 3956 this->LongAlign = 32; 3957 this->LongWidth = 32; 3958 this->PointerAlign = 32; 3959 this->PointerWidth = 32; 3960 this->IntMaxType = TargetInfo::SignedLongLong; 3961 this->UIntMaxType = TargetInfo::UnsignedLongLong; 3962 this->Int64Type = TargetInfo::SignedLongLong; 3963 this->DoubleAlign = 64; 3964 this->LongDoubleWidth = 64; 3965 this->LongDoubleAlign = 64; 3966 this->SizeType = TargetInfo::UnsignedInt; 3967 this->PtrDiffType = TargetInfo::SignedInt; 3968 this->IntPtrType = TargetInfo::SignedInt; 3969 this->RegParmMax = 2; 3970 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 3971 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 3972 } 3973 3974 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3975 } 3976 virtual void getArchDefines(const LangOptions &Opts, 3977 MacroBuilder &Builder) const { 3978 Builder.defineMacro("__le32__"); 3979 Builder.defineMacro("__pnacl__"); 3980 } 3981 virtual void getTargetDefines(const LangOptions &Opts, 3982 MacroBuilder &Builder) const { 3983 DefineStd(Builder, "unix", Opts); 3984 Builder.defineMacro("__ELF__"); 3985 if (Opts.POSIXThreads) 3986 Builder.defineMacro("_REENTRANT"); 3987 if (Opts.CPlusPlus) 3988 Builder.defineMacro("_GNU_SOURCE"); 3989 3990 Builder.defineMacro("__LITTLE_ENDIAN__"); 3991 Builder.defineMacro("__native_client__"); 3992 getArchDefines(Opts, Builder); 3993 } 3994 virtual bool hasFeature(StringRef Feature) const { 3995 return Feature == "pnacl"; 3996 } 3997 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3998 unsigned &NumRecords) const { 3999 } 4000 virtual const char *getVAListDeclaration() const { 4001 return "typedef int __builtin_va_list[4];"; 4002 } 4003 virtual void getGCCRegNames(const char * const *&Names, 4004 unsigned &NumNames) const; 4005 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4006 unsigned &NumAliases) const; 4007 virtual bool validateAsmConstraint(const char *&Name, 4008 TargetInfo::ConstraintInfo &Info) const { 4009 return false; 4010 } 4011 4012 virtual const char *getClobbers() const { 4013 return ""; 4014 } 4015 }; 4016 4017 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 4018 unsigned &NumNames) const { 4019 Names = NULL; 4020 NumNames = 0; 4021 } 4022 4023 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4024 unsigned &NumAliases) const { 4025 Aliases = NULL; 4026 NumAliases = 0; 4027 } 4028 } // end anonymous namespace. 4029 4030 4031 //===----------------------------------------------------------------------===// 4032 // Driver code 4033 //===----------------------------------------------------------------------===// 4034 4035 static TargetInfo *AllocateTarget(const std::string &T) { 4036 llvm::Triple Triple(T); 4037 llvm::Triple::OSType os = Triple.getOS(); 4038 4039 switch (Triple.getArch()) { 4040 default: 4041 return NULL; 4042 4043 case llvm::Triple::hexagon: 4044 return new HexagonTargetInfo(T); 4045 4046 case llvm::Triple::arm: 4047 case llvm::Triple::thumb: 4048 if (Triple.isOSDarwin()) 4049 return new DarwinARMTargetInfo(T); 4050 4051 switch (os) { 4052 case llvm::Triple::Linux: 4053 return new LinuxTargetInfo<ARMTargetInfo>(T); 4054 case llvm::Triple::FreeBSD: 4055 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 4056 case llvm::Triple::NetBSD: 4057 return new NetBSDTargetInfo<ARMTargetInfo>(T); 4058 case llvm::Triple::RTEMS: 4059 return new RTEMSTargetInfo<ARMTargetInfo>(T); 4060 default: 4061 return new ARMTargetInfo(T); 4062 } 4063 4064 case llvm::Triple::msp430: 4065 return new MSP430TargetInfo(T); 4066 4067 case llvm::Triple::mips: 4068 switch (os) { 4069 case llvm::Triple::Linux: 4070 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 4071 case llvm::Triple::RTEMS: 4072 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 4073 case llvm::Triple::FreeBSD: 4074 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 4075 case llvm::Triple::NetBSD: 4076 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 4077 default: 4078 return new Mips32EBTargetInfo(T); 4079 } 4080 4081 case llvm::Triple::mipsel: 4082 switch (os) { 4083 case llvm::Triple::Linux: 4084 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 4085 case llvm::Triple::RTEMS: 4086 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 4087 case llvm::Triple::FreeBSD: 4088 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 4089 case llvm::Triple::NetBSD: 4090 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 4091 default: 4092 return new Mips32ELTargetInfo(T); 4093 } 4094 4095 case llvm::Triple::mips64: 4096 switch (os) { 4097 case llvm::Triple::Linux: 4098 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 4099 case llvm::Triple::RTEMS: 4100 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 4101 case llvm::Triple::FreeBSD: 4102 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 4103 case llvm::Triple::NetBSD: 4104 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 4105 default: 4106 return new Mips64EBTargetInfo(T); 4107 } 4108 4109 case llvm::Triple::mips64el: 4110 switch (os) { 4111 case llvm::Triple::Linux: 4112 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 4113 case llvm::Triple::RTEMS: 4114 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 4115 case llvm::Triple::FreeBSD: 4116 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 4117 case llvm::Triple::NetBSD: 4118 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 4119 default: 4120 return new Mips64ELTargetInfo(T); 4121 } 4122 4123 case llvm::Triple::le32: 4124 switch (os) { 4125 case llvm::Triple::NativeClient: 4126 return new PNaClTargetInfo(T); 4127 default: 4128 return NULL; 4129 } 4130 4131 case llvm::Triple::ppc: 4132 if (Triple.isOSDarwin()) 4133 return new DarwinPPC32TargetInfo(T); 4134 switch (os) { 4135 case llvm::Triple::Linux: 4136 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4137 case llvm::Triple::FreeBSD: 4138 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4139 case llvm::Triple::NetBSD: 4140 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4141 case llvm::Triple::RTEMS: 4142 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4143 default: 4144 return new PPC32TargetInfo(T); 4145 } 4146 4147 case llvm::Triple::ppc64: 4148 if (Triple.isOSDarwin()) 4149 return new DarwinPPC64TargetInfo(T); 4150 switch (os) { 4151 case llvm::Triple::Linux: 4152 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4153 case llvm::Triple::Lv2: 4154 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4155 case llvm::Triple::FreeBSD: 4156 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4157 case llvm::Triple::NetBSD: 4158 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4159 default: 4160 return new PPC64TargetInfo(T); 4161 } 4162 4163 case llvm::Triple::nvptx: 4164 return new NVPTX32TargetInfo(T); 4165 case llvm::Triple::nvptx64: 4166 return new NVPTX64TargetInfo(T); 4167 4168 case llvm::Triple::mblaze: 4169 return new MBlazeTargetInfo(T); 4170 4171 case llvm::Triple::sparc: 4172 switch (os) { 4173 case llvm::Triple::Linux: 4174 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4175 case llvm::Triple::AuroraUX: 4176 return new AuroraUXSparcV8TargetInfo(T); 4177 case llvm::Triple::Solaris: 4178 return new SolarisSparcV8TargetInfo(T); 4179 case llvm::Triple::NetBSD: 4180 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4181 case llvm::Triple::RTEMS: 4182 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4183 default: 4184 return new SparcV8TargetInfo(T); 4185 } 4186 4187 // FIXME: Need a real SPU target. 4188 case llvm::Triple::cellspu: 4189 return new PS3SPUTargetInfo<PPC64TargetInfo>(T); 4190 4191 case llvm::Triple::tce: 4192 return new TCETargetInfo(T); 4193 4194 case llvm::Triple::x86: 4195 if (Triple.isOSDarwin()) 4196 return new DarwinI386TargetInfo(T); 4197 4198 switch (os) { 4199 case llvm::Triple::AuroraUX: 4200 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4201 case llvm::Triple::Linux: 4202 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4203 case llvm::Triple::DragonFly: 4204 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4205 case llvm::Triple::NetBSD: 4206 return new NetBSDI386TargetInfo(T); 4207 case llvm::Triple::OpenBSD: 4208 return new OpenBSDI386TargetInfo(T); 4209 case llvm::Triple::FreeBSD: 4210 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4211 case llvm::Triple::Minix: 4212 return new MinixTargetInfo<X86_32TargetInfo>(T); 4213 case llvm::Triple::Solaris: 4214 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4215 case llvm::Triple::Cygwin: 4216 return new CygwinX86_32TargetInfo(T); 4217 case llvm::Triple::MinGW32: 4218 return new MinGWX86_32TargetInfo(T); 4219 case llvm::Triple::Win32: 4220 return new VisualStudioWindowsX86_32TargetInfo(T); 4221 case llvm::Triple::Haiku: 4222 return new HaikuX86_32TargetInfo(T); 4223 case llvm::Triple::RTEMS: 4224 return new RTEMSX86_32TargetInfo(T); 4225 default: 4226 return new X86_32TargetInfo(T); 4227 } 4228 4229 case llvm::Triple::x86_64: 4230 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4231 return new DarwinX86_64TargetInfo(T); 4232 4233 switch (os) { 4234 case llvm::Triple::AuroraUX: 4235 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4236 case llvm::Triple::Linux: 4237 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4238 case llvm::Triple::DragonFly: 4239 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4240 case llvm::Triple::NetBSD: 4241 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4242 case llvm::Triple::OpenBSD: 4243 return new OpenBSDX86_64TargetInfo(T); 4244 case llvm::Triple::FreeBSD: 4245 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4246 case llvm::Triple::Solaris: 4247 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4248 case llvm::Triple::MinGW32: 4249 return new MinGWX86_64TargetInfo(T); 4250 case llvm::Triple::Win32: // This is what Triple.h supports now. 4251 return new VisualStudioWindowsX86_64TargetInfo(T); 4252 default: 4253 return new X86_64TargetInfo(T); 4254 } 4255 } 4256 } 4257 4258 /// CreateTargetInfo - Return the target info object for the specified target 4259 /// triple. 4260 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4261 TargetOptions &Opts) { 4262 llvm::Triple Triple(Opts.Triple); 4263 4264 // Construct the target 4265 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4266 if (!Target) { 4267 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4268 return 0; 4269 } 4270 4271 // Set the target CPU if specified. 4272 if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) { 4273 Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU; 4274 return 0; 4275 } 4276 4277 // Set the target ABI if specified. 4278 if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) { 4279 Diags.Report(diag::err_target_unknown_abi) << Opts.ABI; 4280 return 0; 4281 } 4282 4283 // Set the target C++ ABI. 4284 if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) { 4285 Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI; 4286 return 0; 4287 } 4288 4289 // Compute the default target features, we need the target to handle this 4290 // because features may have dependencies on one another. 4291 llvm::StringMap<bool> Features; 4292 Target->getDefaultFeatures(Features); 4293 4294 // Apply the user specified deltas. 4295 // First the enables. 4296 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4297 ie = Opts.Features.end(); it != ie; ++it) { 4298 const char *Name = it->c_str(); 4299 4300 if (Name[0] != '+') 4301 continue; 4302 4303 // Apply the feature via the target. 4304 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4305 Diags.Report(diag::err_target_invalid_feature) << Name; 4306 return 0; 4307 } 4308 } 4309 4310 // Then the disables. 4311 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4312 ie = Opts.Features.end(); it != ie; ++it) { 4313 const char *Name = it->c_str(); 4314 4315 if (Name[0] == '+') 4316 continue; 4317 4318 // Apply the feature via the target. 4319 if (Name[0] != '-' || 4320 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4321 Diags.Report(diag::err_target_invalid_feature) << Name; 4322 return 0; 4323 } 4324 } 4325 4326 // Add the features to the compile options. 4327 // 4328 // FIXME: If we are completely confident that we have the right set, we only 4329 // need to pass the minuses. 4330 Opts.Features.clear(); 4331 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4332 ie = Features.end(); it != ie; ++it) 4333 Opts.Features.push_back((it->second ? "+" : "-") + it->first().str()); 4334 Target->HandleTargetFeatures(Opts.Features); 4335 4336 return Target.take(); 4337 } 4338