1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // Fuchsia Target 827 template<typename Target> 828 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 829 protected: 830 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 831 MacroBuilder &Builder) const override { 832 Builder.defineMacro("__Fuchsia__"); 833 Builder.defineMacro("__ELF__"); 834 if (Opts.POSIXThreads) 835 Builder.defineMacro("_REENTRANT"); 836 // Required by the libc++ locale support. 837 if (Opts.CPlusPlus) 838 Builder.defineMacro("_GNU_SOURCE"); 839 } 840 public: 841 FuchsiaTargetInfo(const llvm::Triple &Triple, 842 const TargetOptions &Opts) 843 : OSTargetInfo<Target>(Triple, Opts) { 844 this->MCountName = "__mcount"; 845 } 846 }; 847 848 // WebAssembly target 849 template <typename Target> 850 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 851 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 852 MacroBuilder &Builder) const final { 853 // A common platform macro. 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Follow g++ convention and predefine _GNU_SOURCE for C++. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 861 // As an optimization, group static init code together in a section. 862 const char *getStaticInitSectionSpecifier() const final { 863 return ".text.__startup"; 864 } 865 866 public: 867 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 868 const TargetOptions &Opts) 869 : OSTargetInfo<Target>(Triple, Opts) { 870 this->MCountName = "__mcount"; 871 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 872 } 873 }; 874 875 //===----------------------------------------------------------------------===// 876 // Specific target implementations. 877 //===----------------------------------------------------------------------===// 878 879 // PPC abstract base class 880 class PPCTargetInfo : public TargetInfo { 881 static const Builtin::Info BuiltinInfo[]; 882 static const char * const GCCRegNames[]; 883 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 884 std::string CPU; 885 886 // Target cpu features. 887 bool HasVSX; 888 bool HasP8Vector; 889 bool HasP8Crypto; 890 bool HasDirectMove; 891 bool HasQPX; 892 bool HasHTM; 893 bool HasBPERMD; 894 bool HasExtDiv; 895 bool HasP9Vector; 896 897 protected: 898 std::string ABI; 899 900 public: 901 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 902 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 903 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 904 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 905 SimdDefaultAlign = 128; 906 LongDoubleWidth = LongDoubleAlign = 128; 907 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 908 } 909 910 /// \brief Flags for architecture specific defines. 911 typedef enum { 912 ArchDefineNone = 0, 913 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 914 ArchDefinePpcgr = 1 << 1, 915 ArchDefinePpcsq = 1 << 2, 916 ArchDefine440 = 1 << 3, 917 ArchDefine603 = 1 << 4, 918 ArchDefine604 = 1 << 5, 919 ArchDefinePwr4 = 1 << 6, 920 ArchDefinePwr5 = 1 << 7, 921 ArchDefinePwr5x = 1 << 8, 922 ArchDefinePwr6 = 1 << 9, 923 ArchDefinePwr6x = 1 << 10, 924 ArchDefinePwr7 = 1 << 11, 925 ArchDefinePwr8 = 1 << 12, 926 ArchDefinePwr9 = 1 << 13, 927 ArchDefineA2 = 1 << 14, 928 ArchDefineA2q = 1 << 15 929 } ArchDefineTypes; 930 931 // Note: GCC recognizes the following additional cpus: 932 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 933 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 934 // titan, rs64. 935 bool setCPU(const std::string &Name) override { 936 bool CPUKnown = llvm::StringSwitch<bool>(Name) 937 .Case("generic", true) 938 .Case("440", true) 939 .Case("450", true) 940 .Case("601", true) 941 .Case("602", true) 942 .Case("603", true) 943 .Case("603e", true) 944 .Case("603ev", true) 945 .Case("604", true) 946 .Case("604e", true) 947 .Case("620", true) 948 .Case("630", true) 949 .Case("g3", true) 950 .Case("7400", true) 951 .Case("g4", true) 952 .Case("7450", true) 953 .Case("g4+", true) 954 .Case("750", true) 955 .Case("970", true) 956 .Case("g5", true) 957 .Case("a2", true) 958 .Case("a2q", true) 959 .Case("e500mc", true) 960 .Case("e5500", true) 961 .Case("power3", true) 962 .Case("pwr3", true) 963 .Case("power4", true) 964 .Case("pwr4", true) 965 .Case("power5", true) 966 .Case("pwr5", true) 967 .Case("power5x", true) 968 .Case("pwr5x", true) 969 .Case("power6", true) 970 .Case("pwr6", true) 971 .Case("power6x", true) 972 .Case("pwr6x", true) 973 .Case("power7", true) 974 .Case("pwr7", true) 975 .Case("power8", true) 976 .Case("pwr8", true) 977 .Case("power9", true) 978 .Case("pwr9", true) 979 .Case("powerpc", true) 980 .Case("ppc", true) 981 .Case("powerpc64", true) 982 .Case("ppc64", true) 983 .Case("powerpc64le", true) 984 .Case("ppc64le", true) 985 .Default(false); 986 987 if (CPUKnown) 988 CPU = Name; 989 990 return CPUKnown; 991 } 992 993 994 StringRef getABI() const override { return ABI; } 995 996 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 997 return llvm::makeArrayRef(BuiltinInfo, 998 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 999 } 1000 1001 bool isCLZForZeroUndef() const override { return false; } 1002 1003 void getTargetDefines(const LangOptions &Opts, 1004 MacroBuilder &Builder) const override; 1005 1006 bool 1007 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1008 StringRef CPU, 1009 const std::vector<std::string> &FeaturesVec) const override; 1010 1011 bool handleTargetFeatures(std::vector<std::string> &Features, 1012 DiagnosticsEngine &Diags) override; 1013 bool hasFeature(StringRef Feature) const override; 1014 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1015 bool Enabled) const override; 1016 1017 ArrayRef<const char *> getGCCRegNames() const override; 1018 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1019 bool validateAsmConstraint(const char *&Name, 1020 TargetInfo::ConstraintInfo &Info) const override { 1021 switch (*Name) { 1022 default: return false; 1023 case 'O': // Zero 1024 break; 1025 case 'b': // Base register 1026 case 'f': // Floating point register 1027 Info.setAllowsRegister(); 1028 break; 1029 // FIXME: The following are added to allow parsing. 1030 // I just took a guess at what the actions should be. 1031 // Also, is more specific checking needed? I.e. specific registers? 1032 case 'd': // Floating point register (containing 64-bit value) 1033 case 'v': // Altivec vector register 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'w': 1037 switch (Name[1]) { 1038 case 'd':// VSX vector register to hold vector double data 1039 case 'f':// VSX vector register to hold vector float data 1040 case 's':// VSX vector register to hold scalar float data 1041 case 'a':// Any VSX register 1042 case 'c':// An individual CR bit 1043 break; 1044 default: 1045 return false; 1046 } 1047 Info.setAllowsRegister(); 1048 Name++; // Skip over 'w'. 1049 break; 1050 case 'h': // `MQ', `CTR', or `LINK' register 1051 case 'q': // `MQ' register 1052 case 'c': // `CTR' register 1053 case 'l': // `LINK' register 1054 case 'x': // `CR' register (condition register) number 0 1055 case 'y': // `CR' register (condition register) 1056 case 'z': // `XER[CA]' carry bit (part of the XER register) 1057 Info.setAllowsRegister(); 1058 break; 1059 case 'I': // Signed 16-bit constant 1060 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1061 // (use `L' instead for SImode constants) 1062 case 'K': // Unsigned 16-bit constant 1063 case 'L': // Signed 16-bit constant shifted left 16 bits 1064 case 'M': // Constant larger than 31 1065 case 'N': // Exact power of 2 1066 case 'P': // Constant whose negation is a signed 16-bit constant 1067 case 'G': // Floating point constant that can be loaded into a 1068 // register with one instruction per word 1069 case 'H': // Integer/Floating point constant that can be loaded 1070 // into a register using three instructions 1071 break; 1072 case 'm': // Memory operand. Note that on PowerPC targets, m can 1073 // include addresses that update the base register. It 1074 // is therefore only safe to use `m' in an asm statement 1075 // if that asm statement accesses the operand exactly once. 1076 // The asm statement must also use `%U<opno>' as a 1077 // placeholder for the "update" flag in the corresponding 1078 // load or store instruction. For example: 1079 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1080 // is correct but: 1081 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1082 // is not. Use es rather than m if you don't want the base 1083 // register to be updated. 1084 case 'e': 1085 if (Name[1] != 's') 1086 return false; 1087 // es: A "stable" memory operand; that is, one which does not 1088 // include any automodification of the base register. Unlike 1089 // `m', this constraint can be used in asm statements that 1090 // might access the operand several times, or that might not 1091 // access it at all. 1092 Info.setAllowsMemory(); 1093 Name++; // Skip over 'e'. 1094 break; 1095 case 'Q': // Memory operand that is an offset from a register (it is 1096 // usually better to use `m' or `es' in asm statements) 1097 case 'Z': // Memory operand that is an indexed or indirect from a 1098 // register (it is usually better to use `m' or `es' in 1099 // asm statements) 1100 Info.setAllowsMemory(); 1101 Info.setAllowsRegister(); 1102 break; 1103 case 'R': // AIX TOC entry 1104 case 'a': // Address operand that is an indexed or indirect from a 1105 // register (`p' is preferable for asm statements) 1106 case 'S': // Constant suitable as a 64-bit mask operand 1107 case 'T': // Constant suitable as a 32-bit mask operand 1108 case 'U': // System V Release 4 small data area reference 1109 case 't': // AND masks that can be performed by two rldic{l, r} 1110 // instructions 1111 case 'W': // Vector constant that does not require memory 1112 case 'j': // Vector constant that is all zeros. 1113 break; 1114 // End FIXME. 1115 } 1116 return true; 1117 } 1118 std::string convertConstraint(const char *&Constraint) const override { 1119 std::string R; 1120 switch (*Constraint) { 1121 case 'e': 1122 case 'w': 1123 // Two-character constraint; add "^" hint for later parsing. 1124 R = std::string("^") + std::string(Constraint, 2); 1125 Constraint++; 1126 break; 1127 default: 1128 return TargetInfo::convertConstraint(Constraint); 1129 } 1130 return R; 1131 } 1132 const char *getClobbers() const override { 1133 return ""; 1134 } 1135 int getEHDataRegisterNumber(unsigned RegNo) const override { 1136 if (RegNo == 0) return 3; 1137 if (RegNo == 1) return 4; 1138 return -1; 1139 } 1140 1141 bool hasSjLjLowering() const override { 1142 return true; 1143 } 1144 1145 bool useFloat128ManglingForLongDouble() const override { 1146 return LongDoubleWidth == 128 && 1147 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1148 getTriple().isOSBinFormatELF(); 1149 } 1150 }; 1151 1152 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1153 #define BUILTIN(ID, TYPE, ATTRS) \ 1154 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1156 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1157 #include "clang/Basic/BuiltinsPPC.def" 1158 }; 1159 1160 /// handleTargetFeatures - Perform initialization based on the user 1161 /// configured set of features. 1162 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1163 DiagnosticsEngine &Diags) { 1164 for (const auto &Feature : Features) { 1165 if (Feature == "+vsx") { 1166 HasVSX = true; 1167 } else if (Feature == "+bpermd") { 1168 HasBPERMD = true; 1169 } else if (Feature == "+extdiv") { 1170 HasExtDiv = true; 1171 } else if (Feature == "+power8-vector") { 1172 HasP8Vector = true; 1173 } else if (Feature == "+crypto") { 1174 HasP8Crypto = true; 1175 } else if (Feature == "+direct-move") { 1176 HasDirectMove = true; 1177 } else if (Feature == "+qpx") { 1178 HasQPX = true; 1179 } else if (Feature == "+htm") { 1180 HasHTM = true; 1181 } else if (Feature == "+float128") { 1182 HasFloat128 = true; 1183 } else if (Feature == "+power9-vector") { 1184 HasP9Vector = true; 1185 } 1186 // TODO: Finish this list and add an assert that we've handled them 1187 // all. 1188 } 1189 1190 return true; 1191 } 1192 1193 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1194 /// #defines that are not tied to a specific subtarget. 1195 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1196 MacroBuilder &Builder) const { 1197 // Target identification. 1198 Builder.defineMacro("__ppc__"); 1199 Builder.defineMacro("__PPC__"); 1200 Builder.defineMacro("_ARCH_PPC"); 1201 Builder.defineMacro("__powerpc__"); 1202 Builder.defineMacro("__POWERPC__"); 1203 if (PointerWidth == 64) { 1204 Builder.defineMacro("_ARCH_PPC64"); 1205 Builder.defineMacro("__powerpc64__"); 1206 Builder.defineMacro("__ppc64__"); 1207 Builder.defineMacro("__PPC64__"); 1208 } 1209 1210 // Target properties. 1211 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1212 Builder.defineMacro("_LITTLE_ENDIAN"); 1213 } else { 1214 if (getTriple().getOS() != llvm::Triple::NetBSD && 1215 getTriple().getOS() != llvm::Triple::OpenBSD) 1216 Builder.defineMacro("_BIG_ENDIAN"); 1217 } 1218 1219 // ABI options. 1220 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1221 Builder.defineMacro("_CALL_ELF", "1"); 1222 if (ABI == "elfv2") 1223 Builder.defineMacro("_CALL_ELF", "2"); 1224 1225 // Subtarget options. 1226 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1227 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1228 1229 // FIXME: Should be controlled by command line option. 1230 if (LongDoubleWidth == 128) 1231 Builder.defineMacro("__LONG_DOUBLE_128__"); 1232 1233 if (Opts.AltiVec) { 1234 Builder.defineMacro("__VEC__", "10206"); 1235 Builder.defineMacro("__ALTIVEC__"); 1236 } 1237 1238 // CPU identification. 1239 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1240 .Case("440", ArchDefineName) 1241 .Case("450", ArchDefineName | ArchDefine440) 1242 .Case("601", ArchDefineName) 1243 .Case("602", ArchDefineName | ArchDefinePpcgr) 1244 .Case("603", ArchDefineName | ArchDefinePpcgr) 1245 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1246 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1247 .Case("604", ArchDefineName | ArchDefinePpcgr) 1248 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1249 .Case("620", ArchDefineName | ArchDefinePpcgr) 1250 .Case("630", ArchDefineName | ArchDefinePpcgr) 1251 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1252 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1253 .Case("750", ArchDefineName | ArchDefinePpcgr) 1254 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Case("a2", ArchDefineA2) 1257 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1258 .Case("pwr3", ArchDefinePpcgr) 1259 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1261 | ArchDefinePpcsq) 1262 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1263 | ArchDefinePpcgr | ArchDefinePpcsq) 1264 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1265 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1267 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1268 | ArchDefinePpcsq) 1269 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1270 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1271 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1273 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1276 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1277 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1278 | ArchDefinePpcsq) 1279 .Case("power3", ArchDefinePpcgr) 1280 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1282 | ArchDefinePpcsq) 1283 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1284 | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1286 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1288 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1289 | ArchDefinePpcsq) 1290 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1291 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1292 | ArchDefinePpcgr | ArchDefinePpcsq) 1293 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1294 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1297 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1298 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1299 | ArchDefinePpcsq) 1300 .Default(ArchDefineNone); 1301 1302 if (defs & ArchDefineName) 1303 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1304 if (defs & ArchDefinePpcgr) 1305 Builder.defineMacro("_ARCH_PPCGR"); 1306 if (defs & ArchDefinePpcsq) 1307 Builder.defineMacro("_ARCH_PPCSQ"); 1308 if (defs & ArchDefine440) 1309 Builder.defineMacro("_ARCH_440"); 1310 if (defs & ArchDefine603) 1311 Builder.defineMacro("_ARCH_603"); 1312 if (defs & ArchDefine604) 1313 Builder.defineMacro("_ARCH_604"); 1314 if (defs & ArchDefinePwr4) 1315 Builder.defineMacro("_ARCH_PWR4"); 1316 if (defs & ArchDefinePwr5) 1317 Builder.defineMacro("_ARCH_PWR5"); 1318 if (defs & ArchDefinePwr5x) 1319 Builder.defineMacro("_ARCH_PWR5X"); 1320 if (defs & ArchDefinePwr6) 1321 Builder.defineMacro("_ARCH_PWR6"); 1322 if (defs & ArchDefinePwr6x) 1323 Builder.defineMacro("_ARCH_PWR6X"); 1324 if (defs & ArchDefinePwr7) 1325 Builder.defineMacro("_ARCH_PWR7"); 1326 if (defs & ArchDefinePwr8) 1327 Builder.defineMacro("_ARCH_PWR8"); 1328 if (defs & ArchDefinePwr9) 1329 Builder.defineMacro("_ARCH_PWR9"); 1330 if (defs & ArchDefineA2) 1331 Builder.defineMacro("_ARCH_A2"); 1332 if (defs & ArchDefineA2q) { 1333 Builder.defineMacro("_ARCH_A2Q"); 1334 Builder.defineMacro("_ARCH_QP"); 1335 } 1336 1337 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1338 Builder.defineMacro("__bg__"); 1339 Builder.defineMacro("__THW_BLUEGENE__"); 1340 Builder.defineMacro("__bgq__"); 1341 Builder.defineMacro("__TOS_BGQ__"); 1342 } 1343 1344 if (HasVSX) 1345 Builder.defineMacro("__VSX__"); 1346 if (HasP8Vector) 1347 Builder.defineMacro("__POWER8_VECTOR__"); 1348 if (HasP8Crypto) 1349 Builder.defineMacro("__CRYPTO__"); 1350 if (HasHTM) 1351 Builder.defineMacro("__HTM__"); 1352 if (HasFloat128) 1353 Builder.defineMacro("__FLOAT128__"); 1354 if (HasP9Vector) 1355 Builder.defineMacro("__POWER9_VECTOR__"); 1356 1357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1360 if (PointerWidth == 64) 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1362 1363 // FIXME: The following are not yet generated here by Clang, but are 1364 // generated by GCC: 1365 // 1366 // _SOFT_FLOAT_ 1367 // __RECIP_PRECISION__ 1368 // __APPLE_ALTIVEC__ 1369 // __RECIP__ 1370 // __RECIPF__ 1371 // __RSQRTE__ 1372 // __RSQRTEF__ 1373 // _SOFT_DOUBLE_ 1374 // __NO_LWSYNC__ 1375 // __HAVE_BSWAP__ 1376 // __LONGDOUBLE128 1377 // __CMODEL_MEDIUM__ 1378 // __CMODEL_LARGE__ 1379 // _CALL_SYSV 1380 // _CALL_DARWIN 1381 // __NO_FPRS__ 1382 } 1383 1384 // Handle explicit options being passed to the compiler here: if we've 1385 // explicitly turned off vsx and turned on any of: 1386 // - power8-vector 1387 // - direct-move 1388 // - float128 1389 // - power9-vector 1390 // then go ahead and error since the customer has expressed an incompatible 1391 // set of options. 1392 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1393 const std::vector<std::string> &FeaturesVec) { 1394 1395 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1396 FeaturesVec.end()) { 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1398 FeaturesVec.end()) { 1399 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1400 << "-mno-vsx"; 1401 return false; 1402 } 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1405 FeaturesVec.end()) { 1406 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1407 << "-mno-vsx"; 1408 return false; 1409 } 1410 1411 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1412 FeaturesVec.end()) { 1413 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1414 << "-mno-vsx"; 1415 return false; 1416 } 1417 1418 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1419 FeaturesVec.end()) { 1420 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1421 << "-mno-vsx"; 1422 return false; 1423 } 1424 } 1425 1426 return true; 1427 } 1428 1429 bool PPCTargetInfo::initFeatureMap( 1430 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1431 const std::vector<std::string> &FeaturesVec) const { 1432 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("7400", true) 1434 .Case("g4", true) 1435 .Case("7450", true) 1436 .Case("g4+", true) 1437 .Case("970", true) 1438 .Case("g5", true) 1439 .Case("pwr6", true) 1440 .Case("pwr7", true) 1441 .Case("pwr8", true) 1442 .Case("pwr9", true) 1443 .Case("ppc64", true) 1444 .Case("ppc64le", true) 1445 .Default(false); 1446 1447 Features["qpx"] = (CPU == "a2q"); 1448 Features["power9-vector"] = (CPU == "pwr9"); 1449 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1450 .Case("ppc64le", true) 1451 .Case("pwr9", true) 1452 .Case("pwr8", true) 1453 .Default(false); 1454 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1455 .Case("ppc64le", true) 1456 .Case("pwr9", true) 1457 .Case("pwr8", true) 1458 .Default(false); 1459 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1460 .Case("ppc64le", true) 1461 .Case("pwr9", true) 1462 .Case("pwr8", true) 1463 .Case("pwr7", true) 1464 .Default(false); 1465 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1466 .Case("ppc64le", true) 1467 .Case("pwr9", true) 1468 .Case("pwr8", true) 1469 .Case("pwr7", true) 1470 .Default(false); 1471 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("ppc64le", true) 1473 .Case("pwr9", true) 1474 .Case("pwr8", true) 1475 .Default(false); 1476 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1477 .Case("ppc64le", true) 1478 .Case("pwr9", true) 1479 .Case("pwr8", true) 1480 .Case("pwr7", true) 1481 .Default(false); 1482 1483 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1484 return false; 1485 1486 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1487 } 1488 1489 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1490 return llvm::StringSwitch<bool>(Feature) 1491 .Case("powerpc", true) 1492 .Case("vsx", HasVSX) 1493 .Case("power8-vector", HasP8Vector) 1494 .Case("crypto", HasP8Crypto) 1495 .Case("direct-move", HasDirectMove) 1496 .Case("qpx", HasQPX) 1497 .Case("htm", HasHTM) 1498 .Case("bpermd", HasBPERMD) 1499 .Case("extdiv", HasExtDiv) 1500 .Case("float128", HasFloat128) 1501 .Case("power9-vector", HasP9Vector) 1502 .Default(false); 1503 } 1504 1505 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1506 StringRef Name, bool Enabled) const { 1507 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1508 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1509 // incompatible options. 1510 if (Enabled) { 1511 if (Name == "direct-move" || 1512 Name == "power8-vector" || 1513 Name == "float128" || 1514 Name == "power9-vector") { 1515 // power9-vector is really a superset of power8-vector so encode that. 1516 Features[Name] = Features["vsx"] = true; 1517 if (Name == "power9-vector") 1518 Features["power8-vector"] = true; 1519 } else { 1520 Features[Name] = true; 1521 } 1522 } else { 1523 if (Name == "vsx") { 1524 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1525 Features["float128"] = Features["power9-vector"] = false; 1526 } else { 1527 Features[Name] = false; 1528 } 1529 } 1530 } 1531 1532 const char * const PPCTargetInfo::GCCRegNames[] = { 1533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1535 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1536 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1539 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1540 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1541 "mq", "lr", "ctr", "ap", 1542 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1543 "xer", 1544 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1545 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1546 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1547 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1548 "vrsave", "vscr", 1549 "spe_acc", "spefscr", 1550 "sfp" 1551 }; 1552 1553 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1554 return llvm::makeArrayRef(GCCRegNames); 1555 } 1556 1557 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1558 // While some of these aliases do map to different registers 1559 // they still share the same register name. 1560 { { "0" }, "r0" }, 1561 { { "1"}, "r1" }, 1562 { { "2" }, "r2" }, 1563 { { "3" }, "r3" }, 1564 { { "4" }, "r4" }, 1565 { { "5" }, "r5" }, 1566 { { "6" }, "r6" }, 1567 { { "7" }, "r7" }, 1568 { { "8" }, "r8" }, 1569 { { "9" }, "r9" }, 1570 { { "10" }, "r10" }, 1571 { { "11" }, "r11" }, 1572 { { "12" }, "r12" }, 1573 { { "13" }, "r13" }, 1574 { { "14" }, "r14" }, 1575 { { "15" }, "r15" }, 1576 { { "16" }, "r16" }, 1577 { { "17" }, "r17" }, 1578 { { "18" }, "r18" }, 1579 { { "19" }, "r19" }, 1580 { { "20" }, "r20" }, 1581 { { "21" }, "r21" }, 1582 { { "22" }, "r22" }, 1583 { { "23" }, "r23" }, 1584 { { "24" }, "r24" }, 1585 { { "25" }, "r25" }, 1586 { { "26" }, "r26" }, 1587 { { "27" }, "r27" }, 1588 { { "28" }, "r28" }, 1589 { { "29" }, "r29" }, 1590 { { "30" }, "r30" }, 1591 { { "31" }, "r31" }, 1592 { { "fr0" }, "f0" }, 1593 { { "fr1" }, "f1" }, 1594 { { "fr2" }, "f2" }, 1595 { { "fr3" }, "f3" }, 1596 { { "fr4" }, "f4" }, 1597 { { "fr5" }, "f5" }, 1598 { { "fr6" }, "f6" }, 1599 { { "fr7" }, "f7" }, 1600 { { "fr8" }, "f8" }, 1601 { { "fr9" }, "f9" }, 1602 { { "fr10" }, "f10" }, 1603 { { "fr11" }, "f11" }, 1604 { { "fr12" }, "f12" }, 1605 { { "fr13" }, "f13" }, 1606 { { "fr14" }, "f14" }, 1607 { { "fr15" }, "f15" }, 1608 { { "fr16" }, "f16" }, 1609 { { "fr17" }, "f17" }, 1610 { { "fr18" }, "f18" }, 1611 { { "fr19" }, "f19" }, 1612 { { "fr20" }, "f20" }, 1613 { { "fr21" }, "f21" }, 1614 { { "fr22" }, "f22" }, 1615 { { "fr23" }, "f23" }, 1616 { { "fr24" }, "f24" }, 1617 { { "fr25" }, "f25" }, 1618 { { "fr26" }, "f26" }, 1619 { { "fr27" }, "f27" }, 1620 { { "fr28" }, "f28" }, 1621 { { "fr29" }, "f29" }, 1622 { { "fr30" }, "f30" }, 1623 { { "fr31" }, "f31" }, 1624 { { "cc" }, "cr0" }, 1625 }; 1626 1627 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1628 return llvm::makeArrayRef(GCCRegAliases); 1629 } 1630 1631 class PPC32TargetInfo : public PPCTargetInfo { 1632 public: 1633 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1634 : PPCTargetInfo(Triple, Opts) { 1635 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1636 1637 switch (getTriple().getOS()) { 1638 case llvm::Triple::Linux: 1639 case llvm::Triple::FreeBSD: 1640 case llvm::Triple::NetBSD: 1641 SizeType = UnsignedInt; 1642 PtrDiffType = SignedInt; 1643 IntPtrType = SignedInt; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1650 LongDoubleWidth = LongDoubleAlign = 64; 1651 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1652 } 1653 1654 // PPC32 supports atomics up to 4 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1656 } 1657 1658 BuiltinVaListKind getBuiltinVaListKind() const override { 1659 // This is the ELF definition, and is overridden by the Darwin sub-target 1660 return TargetInfo::PowerABIBuiltinVaList; 1661 } 1662 }; 1663 1664 // Note: ABI differences may eventually require us to have a separate 1665 // TargetInfo for little endian. 1666 class PPC64TargetInfo : public PPCTargetInfo { 1667 public: 1668 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : PPCTargetInfo(Triple, Opts) { 1670 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1671 IntMaxType = SignedLong; 1672 Int64Type = SignedLong; 1673 1674 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1675 resetDataLayout("e-m:e-i64:64-n32:64"); 1676 ABI = "elfv2"; 1677 } else { 1678 resetDataLayout("E-m:e-i64:64-n32:64"); 1679 ABI = "elfv1"; 1680 } 1681 1682 switch (getTriple().getOS()) { 1683 case llvm::Triple::FreeBSD: 1684 LongDoubleWidth = LongDoubleAlign = 64; 1685 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1686 break; 1687 case llvm::Triple::NetBSD: 1688 IntMaxType = SignedLongLong; 1689 Int64Type = SignedLongLong; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 // PPC64 supports atomics up to 8 bytes. 1696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1697 } 1698 BuiltinVaListKind getBuiltinVaListKind() const override { 1699 return TargetInfo::CharPtrBuiltinVaList; 1700 } 1701 // PPC64 Linux-specific ABI options. 1702 bool setABI(const std::string &Name) override { 1703 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1704 ABI = Name; 1705 return true; 1706 } 1707 return false; 1708 } 1709 }; 1710 1711 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1712 public: 1713 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1715 HasAlignMac68kSupport = true; 1716 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1717 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1718 LongLongAlign = 32; 1719 SuitableAlign = 128; 1720 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1721 } 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 return TargetInfo::CharPtrBuiltinVaList; 1724 } 1725 }; 1726 1727 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1728 public: 1729 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1730 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1731 HasAlignMac68kSupport = true; 1732 SuitableAlign = 128; 1733 resetDataLayout("E-m:o-i64:64-n32:64"); 1734 } 1735 }; 1736 1737 static const unsigned NVPTXAddrSpaceMap[] = { 1738 1, // opencl_global 1739 3, // opencl_local 1740 4, // opencl_constant 1741 // FIXME: generic has to be added to the target 1742 0, // opencl_generic 1743 1, // cuda_device 1744 4, // cuda_constant 1745 3, // cuda_shared 1746 }; 1747 1748 class NVPTXTargetInfo : public TargetInfo { 1749 static const char *const GCCRegNames[]; 1750 static const Builtin::Info BuiltinInfo[]; 1751 CudaArch GPU; 1752 1753 public: 1754 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1755 : TargetInfo(Triple) { 1756 TLSSupported = false; 1757 LongWidth = LongAlign = 64; 1758 AddrSpaceMap = &NVPTXAddrSpaceMap; 1759 UseAddrSpaceMapMangling = true; 1760 // Define available target features 1761 // These must be defined in sorted order! 1762 NoAsmVariants = true; 1763 GPU = CudaArch::SM_20; 1764 1765 // If possible, get a TargetInfo for our host triple, so we can match its 1766 // types. 1767 llvm::Triple HostTriple(Opts.HostTriple); 1768 if (HostTriple.isNVPTX()) 1769 return; 1770 std::unique_ptr<TargetInfo> HostTarget( 1771 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1772 if (!HostTarget) { 1773 return; 1774 } 1775 1776 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1777 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1778 BoolWidth = HostTarget->getBoolWidth(); 1779 BoolAlign = HostTarget->getBoolAlign(); 1780 IntWidth = HostTarget->getIntWidth(); 1781 IntAlign = HostTarget->getIntAlign(); 1782 HalfWidth = HostTarget->getHalfWidth(); 1783 HalfAlign = HostTarget->getHalfAlign(); 1784 FloatWidth = HostTarget->getFloatWidth(); 1785 FloatAlign = HostTarget->getFloatAlign(); 1786 DoubleWidth = HostTarget->getDoubleWidth(); 1787 DoubleAlign = HostTarget->getDoubleAlign(); 1788 LongWidth = HostTarget->getLongWidth(); 1789 LongAlign = HostTarget->getLongAlign(); 1790 LongLongWidth = HostTarget->getLongLongWidth(); 1791 LongLongAlign = HostTarget->getLongLongAlign(); 1792 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1793 NewAlign = HostTarget->getNewAlign(); 1794 DefaultAlignForAttributeAligned = 1795 HostTarget->getDefaultAlignForAttributeAligned(); 1796 SizeType = HostTarget->getSizeType(); 1797 IntMaxType = HostTarget->getIntMaxType(); 1798 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1799 IntPtrType = HostTarget->getIntPtrType(); 1800 WCharType = HostTarget->getWCharType(); 1801 WIntType = HostTarget->getWIntType(); 1802 Char16Type = HostTarget->getChar16Type(); 1803 Char32Type = HostTarget->getChar32Type(); 1804 Int64Type = HostTarget->getInt64Type(); 1805 SigAtomicType = HostTarget->getSigAtomicType(); 1806 ProcessIDType = HostTarget->getProcessIDType(); 1807 1808 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1809 UseZeroLengthBitfieldAlignment = 1810 HostTarget->useZeroLengthBitfieldAlignment(); 1811 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1812 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1813 1814 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1815 // we need those macros to be identical on host and device, because (among 1816 // other things) they affect which standard library classes are defined, and 1817 // we need all classes to be defined on both the host and device. 1818 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1819 1820 // Properties intentionally not copied from host: 1821 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1822 // host/device boundary. 1823 // - SuitableAlign: Not visible across the host/device boundary, and may 1824 // correctly be different on host/device, e.g. if host has wider vector 1825 // types than device. 1826 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1827 // as its double type, but that's not necessarily true on the host. 1828 // TODO: nvcc emits a warning when using long double on device; we should 1829 // do the same. 1830 } 1831 void getTargetDefines(const LangOptions &Opts, 1832 MacroBuilder &Builder) const override { 1833 Builder.defineMacro("__PTX__"); 1834 Builder.defineMacro("__NVPTX__"); 1835 if (Opts.CUDAIsDevice) { 1836 // Set __CUDA_ARCH__ for the GPU specified. 1837 std::string CUDAArchCode = [this] { 1838 switch (GPU) { 1839 case CudaArch::UNKNOWN: 1840 assert(false && "No GPU arch when compiling CUDA device code."); 1841 return ""; 1842 case CudaArch::SM_20: 1843 return "200"; 1844 case CudaArch::SM_21: 1845 return "210"; 1846 case CudaArch::SM_30: 1847 return "300"; 1848 case CudaArch::SM_32: 1849 return "320"; 1850 case CudaArch::SM_35: 1851 return "350"; 1852 case CudaArch::SM_37: 1853 return "370"; 1854 case CudaArch::SM_50: 1855 return "500"; 1856 case CudaArch::SM_52: 1857 return "520"; 1858 case CudaArch::SM_53: 1859 return "530"; 1860 case CudaArch::SM_60: 1861 return "600"; 1862 case CudaArch::SM_61: 1863 return "610"; 1864 case CudaArch::SM_62: 1865 return "620"; 1866 } 1867 llvm_unreachable("unhandled CudaArch"); 1868 }(); 1869 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1870 } 1871 } 1872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1873 return llvm::makeArrayRef(BuiltinInfo, 1874 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1875 } 1876 bool 1877 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1878 StringRef CPU, 1879 const std::vector<std::string> &FeaturesVec) const override { 1880 Features["satom"] = GPU >= CudaArch::SM_60; 1881 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1882 } 1883 1884 bool hasFeature(StringRef Feature) const override { 1885 return llvm::StringSwitch<bool>(Feature) 1886 .Cases("ptx", "nvptx", true) 1887 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1888 .Default(false); 1889 } 1890 1891 ArrayRef<const char *> getGCCRegNames() const override; 1892 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1893 // No aliases. 1894 return None; 1895 } 1896 bool validateAsmConstraint(const char *&Name, 1897 TargetInfo::ConstraintInfo &Info) const override { 1898 switch (*Name) { 1899 default: 1900 return false; 1901 case 'c': 1902 case 'h': 1903 case 'r': 1904 case 'l': 1905 case 'f': 1906 case 'd': 1907 Info.setAllowsRegister(); 1908 return true; 1909 } 1910 } 1911 const char *getClobbers() const override { 1912 // FIXME: Is this really right? 1913 return ""; 1914 } 1915 BuiltinVaListKind getBuiltinVaListKind() const override { 1916 // FIXME: implement 1917 return TargetInfo::CharPtrBuiltinVaList; 1918 } 1919 bool setCPU(const std::string &Name) override { 1920 GPU = StringToCudaArch(Name); 1921 return GPU != CudaArch::UNKNOWN; 1922 } 1923 void setSupportedOpenCLOpts() override { 1924 auto &Opts = getSupportedOpenCLOpts(); 1925 Opts.cl_clang_storage_class_specifiers = 1; 1926 Opts.cl_khr_gl_sharing = 1; 1927 Opts.cl_khr_icd = 1; 1928 1929 Opts.cl_khr_fp64 = 1; 1930 Opts.cl_khr_byte_addressable_store = 1; 1931 Opts.cl_khr_global_int32_base_atomics = 1; 1932 Opts.cl_khr_global_int32_extended_atomics = 1; 1933 Opts.cl_khr_local_int32_base_atomics = 1; 1934 Opts.cl_khr_local_int32_extended_atomics = 1; 1935 } 1936 }; 1937 1938 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1939 #define BUILTIN(ID, TYPE, ATTRS) \ 1940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1943 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1944 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1945 #include "clang/Basic/BuiltinsNVPTX.def" 1946 }; 1947 1948 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1949 1950 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1951 return llvm::makeArrayRef(GCCRegNames); 1952 } 1953 1954 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1955 public: 1956 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1957 : NVPTXTargetInfo(Triple, Opts) { 1958 LongWidth = LongAlign = 32; 1959 PointerWidth = PointerAlign = 32; 1960 SizeType = TargetInfo::UnsignedInt; 1961 PtrDiffType = TargetInfo::SignedInt; 1962 IntPtrType = TargetInfo::SignedInt; 1963 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1964 } 1965 }; 1966 1967 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1968 public: 1969 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1970 : NVPTXTargetInfo(Triple, Opts) { 1971 PointerWidth = PointerAlign = 64; 1972 SizeType = TargetInfo::UnsignedLong; 1973 PtrDiffType = TargetInfo::SignedLong; 1974 IntPtrType = TargetInfo::SignedLong; 1975 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1976 } 1977 }; 1978 1979 static const unsigned AMDGPUAddrSpaceMap[] = { 1980 1, // opencl_global 1981 3, // opencl_local 1982 2, // opencl_constant 1983 4, // opencl_generic 1984 1, // cuda_device 1985 2, // cuda_constant 1986 3 // cuda_shared 1987 }; 1988 1989 // If you edit the description strings, make sure you update 1990 // getPointerWidthV(). 1991 1992 static const char *const DataLayoutStringR600 = 1993 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1994 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1995 1996 static const char *const DataLayoutStringSI = 1997 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1998 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1999 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2000 2001 class AMDGPUTargetInfo final : public TargetInfo { 2002 static const Builtin::Info BuiltinInfo[]; 2003 static const char * const GCCRegNames[]; 2004 2005 /// \brief The GPU profiles supported by the AMDGPU target. 2006 enum GPUKind { 2007 GK_NONE, 2008 GK_R600, 2009 GK_R600_DOUBLE_OPS, 2010 GK_R700, 2011 GK_R700_DOUBLE_OPS, 2012 GK_EVERGREEN, 2013 GK_EVERGREEN_DOUBLE_OPS, 2014 GK_NORTHERN_ISLANDS, 2015 GK_CAYMAN, 2016 GK_GFX6, 2017 GK_GFX7, 2018 GK_GFX8 2019 } GPU; 2020 2021 bool hasFP64:1; 2022 bool hasFMAF:1; 2023 bool hasLDEXPF:1; 2024 bool hasFullSpeedFP32Denorms:1; 2025 2026 static bool isAMDGCN(const llvm::Triple &TT) { 2027 return TT.getArch() == llvm::Triple::amdgcn; 2028 } 2029 2030 public: 2031 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2032 : TargetInfo(Triple) , 2033 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2034 hasFP64(false), 2035 hasFMAF(false), 2036 hasLDEXPF(false), 2037 hasFullSpeedFP32Denorms(false){ 2038 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2039 hasFP64 = true; 2040 hasFMAF = true; 2041 hasLDEXPF = true; 2042 } 2043 2044 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2045 DataLayoutStringSI : DataLayoutStringR600); 2046 2047 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2048 UseAddrSpaceMapMangling = true; 2049 } 2050 2051 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2052 if (GPU <= GK_CAYMAN) 2053 return 32; 2054 2055 switch(AddrSpace) { 2056 default: 2057 return 64; 2058 case 0: 2059 case 3: 2060 case 5: 2061 return 32; 2062 } 2063 } 2064 2065 uint64_t getMaxPointerWidth() const override { 2066 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2067 } 2068 2069 const char * getClobbers() const override { 2070 return ""; 2071 } 2072 2073 ArrayRef<const char *> getGCCRegNames() const override; 2074 2075 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2076 return None; 2077 } 2078 2079 bool validateAsmConstraint(const char *&Name, 2080 TargetInfo::ConstraintInfo &Info) const override { 2081 switch (*Name) { 2082 default: break; 2083 case 'v': // vgpr 2084 case 's': // sgpr 2085 Info.setAllowsRegister(); 2086 return true; 2087 } 2088 return false; 2089 } 2090 2091 bool initFeatureMap(llvm::StringMap<bool> &Features, 2092 DiagnosticsEngine &Diags, StringRef CPU, 2093 const std::vector<std::string> &FeatureVec) const override; 2094 2095 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2096 TargetOptions &TargetOpts) const override { 2097 bool hasFP32Denormals = false; 2098 bool hasFP64Denormals = false; 2099 for (auto &I : TargetOpts.FeaturesAsWritten) { 2100 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2101 hasFP32Denormals = true; 2102 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2103 hasFP64Denormals = true; 2104 } 2105 if (!hasFP32Denormals) 2106 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2107 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2108 // Always do not flush fp64 denorms. 2109 if (!hasFP64Denormals && hasFP64) 2110 TargetOpts.Features.push_back("+fp64-denormals"); 2111 } 2112 2113 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2114 return llvm::makeArrayRef(BuiltinInfo, 2115 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2116 } 2117 2118 void getTargetDefines(const LangOptions &Opts, 2119 MacroBuilder &Builder) const override { 2120 if (getTriple().getArch() == llvm::Triple::amdgcn) 2121 Builder.defineMacro("__AMDGCN__"); 2122 else 2123 Builder.defineMacro("__R600__"); 2124 2125 if (hasFMAF) 2126 Builder.defineMacro("__HAS_FMAF__"); 2127 if (hasLDEXPF) 2128 Builder.defineMacro("__HAS_LDEXPF__"); 2129 if (hasFP64) 2130 Builder.defineMacro("__HAS_FP64__"); 2131 } 2132 2133 BuiltinVaListKind getBuiltinVaListKind() const override { 2134 return TargetInfo::CharPtrBuiltinVaList; 2135 } 2136 2137 static GPUKind parseR600Name(StringRef Name) { 2138 return llvm::StringSwitch<GPUKind>(Name) 2139 .Case("r600" , GK_R600) 2140 .Case("rv610", GK_R600) 2141 .Case("rv620", GK_R600) 2142 .Case("rv630", GK_R600) 2143 .Case("rv635", GK_R600) 2144 .Case("rs780", GK_R600) 2145 .Case("rs880", GK_R600) 2146 .Case("rv670", GK_R600_DOUBLE_OPS) 2147 .Case("rv710", GK_R700) 2148 .Case("rv730", GK_R700) 2149 .Case("rv740", GK_R700_DOUBLE_OPS) 2150 .Case("rv770", GK_R700_DOUBLE_OPS) 2151 .Case("palm", GK_EVERGREEN) 2152 .Case("cedar", GK_EVERGREEN) 2153 .Case("sumo", GK_EVERGREEN) 2154 .Case("sumo2", GK_EVERGREEN) 2155 .Case("redwood", GK_EVERGREEN) 2156 .Case("juniper", GK_EVERGREEN) 2157 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2158 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2159 .Case("barts", GK_NORTHERN_ISLANDS) 2160 .Case("turks", GK_NORTHERN_ISLANDS) 2161 .Case("caicos", GK_NORTHERN_ISLANDS) 2162 .Case("cayman", GK_CAYMAN) 2163 .Case("aruba", GK_CAYMAN) 2164 .Default(GK_NONE); 2165 } 2166 2167 static GPUKind parseAMDGCNName(StringRef Name) { 2168 return llvm::StringSwitch<GPUKind>(Name) 2169 .Case("tahiti", GK_GFX6) 2170 .Case("pitcairn", GK_GFX6) 2171 .Case("verde", GK_GFX6) 2172 .Case("oland", GK_GFX6) 2173 .Case("hainan", GK_GFX6) 2174 .Case("bonaire", GK_GFX7) 2175 .Case("kabini", GK_GFX7) 2176 .Case("kaveri", GK_GFX7) 2177 .Case("hawaii", GK_GFX7) 2178 .Case("mullins", GK_GFX7) 2179 .Case("gfx700", GK_GFX7) 2180 .Case("gfx701", GK_GFX7) 2181 .Case("gfx702", GK_GFX7) 2182 .Case("tonga", GK_GFX8) 2183 .Case("iceland", GK_GFX8) 2184 .Case("carrizo", GK_GFX8) 2185 .Case("fiji", GK_GFX8) 2186 .Case("stoney", GK_GFX8) 2187 .Case("polaris10", GK_GFX8) 2188 .Case("polaris11", GK_GFX8) 2189 .Case("gfx800", GK_GFX8) 2190 .Case("gfx801", GK_GFX8) 2191 .Case("gfx802", GK_GFX8) 2192 .Case("gfx803", GK_GFX8) 2193 .Case("gfx804", GK_GFX8) 2194 .Case("gfx810", GK_GFX8) 2195 .Default(GK_NONE); 2196 } 2197 2198 bool setCPU(const std::string &Name) override { 2199 if (getTriple().getArch() == llvm::Triple::amdgcn) 2200 GPU = parseAMDGCNName(Name); 2201 else 2202 GPU = parseR600Name(Name); 2203 2204 return GPU != GK_NONE; 2205 } 2206 2207 void setSupportedOpenCLOpts() override { 2208 auto &Opts = getSupportedOpenCLOpts(); 2209 Opts.cl_clang_storage_class_specifiers = 1; 2210 Opts.cl_khr_icd = 1; 2211 2212 if (hasFP64) 2213 Opts.cl_khr_fp64 = 1; 2214 if (GPU >= GK_EVERGREEN) { 2215 Opts.cl_khr_byte_addressable_store = 1; 2216 Opts.cl_khr_global_int32_base_atomics = 1; 2217 Opts.cl_khr_global_int32_extended_atomics = 1; 2218 Opts.cl_khr_local_int32_base_atomics = 1; 2219 Opts.cl_khr_local_int32_extended_atomics = 1; 2220 } 2221 if (GPU >= GK_GFX6) { 2222 Opts.cl_khr_fp16 = 1; 2223 Opts.cl_khr_int64_base_atomics = 1; 2224 Opts.cl_khr_int64_extended_atomics = 1; 2225 Opts.cl_khr_mipmap_image = 1; 2226 Opts.cl_khr_subgroups = 1; 2227 Opts.cl_khr_3d_image_writes = 1; 2228 Opts.cl_amd_media_ops = 1; 2229 Opts.cl_amd_media_ops2 = 1; 2230 } 2231 } 2232 2233 LangAS::ID getOpenCLImageAddrSpace() const override { 2234 return LangAS::opencl_constant; 2235 } 2236 2237 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2238 switch (CC) { 2239 default: 2240 return CCCR_Warning; 2241 case CC_C: 2242 case CC_OpenCLKernel: 2243 return CCCR_OK; 2244 } 2245 } 2246 }; 2247 2248 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2249 #define BUILTIN(ID, TYPE, ATTRS) \ 2250 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2251 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2252 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2253 #include "clang/Basic/BuiltinsAMDGPU.def" 2254 }; 2255 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2256 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2257 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2258 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2259 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2260 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2261 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2262 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2263 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2264 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2265 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2266 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2267 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2268 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2269 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2270 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2271 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2272 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2273 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2274 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2275 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2276 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2277 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2278 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2279 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2280 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2281 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2282 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2283 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2284 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2285 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2286 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2287 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2288 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2289 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2290 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2291 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2292 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2293 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2294 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2295 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2296 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2297 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2298 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2299 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2300 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2301 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2302 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2303 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2304 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2305 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2306 }; 2307 2308 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2309 return llvm::makeArrayRef(GCCRegNames); 2310 } 2311 2312 bool AMDGPUTargetInfo::initFeatureMap( 2313 llvm::StringMap<bool> &Features, 2314 DiagnosticsEngine &Diags, StringRef CPU, 2315 const std::vector<std::string> &FeatureVec) const { 2316 2317 // XXX - What does the member GPU mean if device name string passed here? 2318 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2319 if (CPU.empty()) 2320 CPU = "tahiti"; 2321 2322 switch (parseAMDGCNName(CPU)) { 2323 case GK_GFX6: 2324 case GK_GFX7: 2325 break; 2326 2327 case GK_GFX8: 2328 Features["s-memrealtime"] = true; 2329 Features["16-bit-insts"] = true; 2330 break; 2331 2332 case GK_NONE: 2333 return false; 2334 default: 2335 llvm_unreachable("unhandled subtarget"); 2336 } 2337 } else { 2338 if (CPU.empty()) 2339 CPU = "r600"; 2340 2341 switch (parseR600Name(CPU)) { 2342 case GK_R600: 2343 case GK_R700: 2344 case GK_EVERGREEN: 2345 case GK_NORTHERN_ISLANDS: 2346 break; 2347 case GK_R600_DOUBLE_OPS: 2348 case GK_R700_DOUBLE_OPS: 2349 case GK_EVERGREEN_DOUBLE_OPS: 2350 case GK_CAYMAN: 2351 Features["fp64"] = true; 2352 break; 2353 case GK_NONE: 2354 return false; 2355 default: 2356 llvm_unreachable("unhandled subtarget"); 2357 } 2358 } 2359 2360 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2361 } 2362 2363 const Builtin::Info BuiltinInfoX86[] = { 2364 #define BUILTIN(ID, TYPE, ATTRS) \ 2365 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2366 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2367 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2368 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2369 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2370 #include "clang/Basic/BuiltinsX86.def" 2371 2372 #define BUILTIN(ID, TYPE, ATTRS) \ 2373 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2374 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2375 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2376 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2377 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2378 #include "clang/Basic/BuiltinsX86_64.def" 2379 }; 2380 2381 2382 static const char* const GCCRegNames[] = { 2383 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2384 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2385 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2386 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2387 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2388 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2389 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2390 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2391 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2392 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2393 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2394 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2395 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2396 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2397 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2398 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2399 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2400 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2401 }; 2402 2403 const TargetInfo::AddlRegName AddlRegNames[] = { 2404 { { "al", "ah", "eax", "rax" }, 0 }, 2405 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2406 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2407 { { "dl", "dh", "edx", "rdx" }, 1 }, 2408 { { "esi", "rsi" }, 4 }, 2409 { { "edi", "rdi" }, 5 }, 2410 { { "esp", "rsp" }, 7 }, 2411 { { "ebp", "rbp" }, 6 }, 2412 { { "r8d", "r8w", "r8b" }, 38 }, 2413 { { "r9d", "r9w", "r9b" }, 39 }, 2414 { { "r10d", "r10w", "r10b" }, 40 }, 2415 { { "r11d", "r11w", "r11b" }, 41 }, 2416 { { "r12d", "r12w", "r12b" }, 42 }, 2417 { { "r13d", "r13w", "r13b" }, 43 }, 2418 { { "r14d", "r14w", "r14b" }, 44 }, 2419 { { "r15d", "r15w", "r15b" }, 45 }, 2420 }; 2421 2422 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2423 // most of the implementation can be shared. 2424 class X86TargetInfo : public TargetInfo { 2425 enum X86SSEEnum { 2426 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2427 } SSELevel = NoSSE; 2428 enum MMX3DNowEnum { 2429 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2430 } MMX3DNowLevel = NoMMX3DNow; 2431 enum XOPEnum { 2432 NoXOP, 2433 SSE4A, 2434 FMA4, 2435 XOP 2436 } XOPLevel = NoXOP; 2437 2438 bool HasAES = false; 2439 bool HasPCLMUL = false; 2440 bool HasLZCNT = false; 2441 bool HasRDRND = false; 2442 bool HasFSGSBASE = false; 2443 bool HasBMI = false; 2444 bool HasBMI2 = false; 2445 bool HasPOPCNT = false; 2446 bool HasRTM = false; 2447 bool HasPRFCHW = false; 2448 bool HasRDSEED = false; 2449 bool HasADX = false; 2450 bool HasTBM = false; 2451 bool HasFMA = false; 2452 bool HasF16C = false; 2453 bool HasAVX512CD = false; 2454 bool HasAVX512ER = false; 2455 bool HasAVX512PF = false; 2456 bool HasAVX512DQ = false; 2457 bool HasAVX512BW = false; 2458 bool HasAVX512VL = false; 2459 bool HasAVX512VBMI = false; 2460 bool HasAVX512IFMA = false; 2461 bool HasSHA = false; 2462 bool HasMPX = false; 2463 bool HasSGX = false; 2464 bool HasCX16 = false; 2465 bool HasFXSR = false; 2466 bool HasXSAVE = false; 2467 bool HasXSAVEOPT = false; 2468 bool HasXSAVEC = false; 2469 bool HasXSAVES = false; 2470 bool HasMWAITX = false; 2471 bool HasPKU = false; 2472 bool HasCLFLUSHOPT = false; 2473 bool HasPCOMMIT = false; 2474 bool HasCLWB = false; 2475 bool HasUMIP = false; 2476 bool HasMOVBE = false; 2477 bool HasPREFETCHWT1 = false; 2478 2479 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2480 /// 2481 /// Each enumeration represents a particular CPU supported by Clang. These 2482 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2483 enum CPUKind { 2484 CK_Generic, 2485 2486 /// \name i386 2487 /// i386-generation processors. 2488 //@{ 2489 CK_i386, 2490 //@} 2491 2492 /// \name i486 2493 /// i486-generation processors. 2494 //@{ 2495 CK_i486, 2496 CK_WinChipC6, 2497 CK_WinChip2, 2498 CK_C3, 2499 //@} 2500 2501 /// \name i586 2502 /// i586-generation processors, P5 microarchitecture based. 2503 //@{ 2504 CK_i586, 2505 CK_Pentium, 2506 CK_PentiumMMX, 2507 //@} 2508 2509 /// \name i686 2510 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2511 //@{ 2512 CK_i686, 2513 CK_PentiumPro, 2514 CK_Pentium2, 2515 CK_Pentium3, 2516 CK_Pentium3M, 2517 CK_PentiumM, 2518 CK_C3_2, 2519 2520 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2521 /// Clang however has some logic to suport this. 2522 // FIXME: Warn, deprecate, and potentially remove this. 2523 CK_Yonah, 2524 //@} 2525 2526 /// \name Netburst 2527 /// Netburst microarchitecture based processors. 2528 //@{ 2529 CK_Pentium4, 2530 CK_Pentium4M, 2531 CK_Prescott, 2532 CK_Nocona, 2533 //@} 2534 2535 /// \name Core 2536 /// Core microarchitecture based processors. 2537 //@{ 2538 CK_Core2, 2539 2540 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2541 /// codename which GCC no longer accepts as an option to -march, but Clang 2542 /// has some logic for recognizing it. 2543 // FIXME: Warn, deprecate, and potentially remove this. 2544 CK_Penryn, 2545 //@} 2546 2547 /// \name Atom 2548 /// Atom processors 2549 //@{ 2550 CK_Bonnell, 2551 CK_Silvermont, 2552 //@} 2553 2554 /// \name Nehalem 2555 /// Nehalem microarchitecture based processors. 2556 CK_Nehalem, 2557 2558 /// \name Westmere 2559 /// Westmere microarchitecture based processors. 2560 CK_Westmere, 2561 2562 /// \name Sandy Bridge 2563 /// Sandy Bridge microarchitecture based processors. 2564 CK_SandyBridge, 2565 2566 /// \name Ivy Bridge 2567 /// Ivy Bridge microarchitecture based processors. 2568 CK_IvyBridge, 2569 2570 /// \name Haswell 2571 /// Haswell microarchitecture based processors. 2572 CK_Haswell, 2573 2574 /// \name Broadwell 2575 /// Broadwell microarchitecture based processors. 2576 CK_Broadwell, 2577 2578 /// \name Skylake Client 2579 /// Skylake client microarchitecture based processors. 2580 CK_SkylakeClient, 2581 2582 /// \name Skylake Server 2583 /// Skylake server microarchitecture based processors. 2584 CK_SkylakeServer, 2585 2586 /// \name Cannonlake Client 2587 /// Cannonlake client microarchitecture based processors. 2588 CK_Cannonlake, 2589 2590 /// \name Knights Landing 2591 /// Knights Landing processor. 2592 CK_KNL, 2593 2594 /// \name Lakemont 2595 /// Lakemont microarchitecture based processors. 2596 CK_Lakemont, 2597 2598 /// \name K6 2599 /// K6 architecture processors. 2600 //@{ 2601 CK_K6, 2602 CK_K6_2, 2603 CK_K6_3, 2604 //@} 2605 2606 /// \name K7 2607 /// K7 architecture processors. 2608 //@{ 2609 CK_Athlon, 2610 CK_AthlonThunderbird, 2611 CK_Athlon4, 2612 CK_AthlonXP, 2613 CK_AthlonMP, 2614 //@} 2615 2616 /// \name K8 2617 /// K8 architecture processors. 2618 //@{ 2619 CK_Athlon64, 2620 CK_Athlon64SSE3, 2621 CK_AthlonFX, 2622 CK_K8, 2623 CK_K8SSE3, 2624 CK_Opteron, 2625 CK_OpteronSSE3, 2626 CK_AMDFAM10, 2627 //@} 2628 2629 /// \name Bobcat 2630 /// Bobcat architecture processors. 2631 //@{ 2632 CK_BTVER1, 2633 CK_BTVER2, 2634 //@} 2635 2636 /// \name Bulldozer 2637 /// Bulldozer architecture processors. 2638 //@{ 2639 CK_BDVER1, 2640 CK_BDVER2, 2641 CK_BDVER3, 2642 CK_BDVER4, 2643 //@} 2644 2645 /// This specification is deprecated and will be removed in the future. 2646 /// Users should prefer \see CK_K8. 2647 // FIXME: Warn on this when the CPU is set to it. 2648 //@{ 2649 CK_x86_64, 2650 //@} 2651 2652 /// \name Geode 2653 /// Geode processors. 2654 //@{ 2655 CK_Geode 2656 //@} 2657 } CPU = CK_Generic; 2658 2659 CPUKind getCPUKind(StringRef CPU) const { 2660 return llvm::StringSwitch<CPUKind>(CPU) 2661 .Case("i386", CK_i386) 2662 .Case("i486", CK_i486) 2663 .Case("winchip-c6", CK_WinChipC6) 2664 .Case("winchip2", CK_WinChip2) 2665 .Case("c3", CK_C3) 2666 .Case("i586", CK_i586) 2667 .Case("pentium", CK_Pentium) 2668 .Case("pentium-mmx", CK_PentiumMMX) 2669 .Case("i686", CK_i686) 2670 .Case("pentiumpro", CK_PentiumPro) 2671 .Case("pentium2", CK_Pentium2) 2672 .Case("pentium3", CK_Pentium3) 2673 .Case("pentium3m", CK_Pentium3M) 2674 .Case("pentium-m", CK_PentiumM) 2675 .Case("c3-2", CK_C3_2) 2676 .Case("yonah", CK_Yonah) 2677 .Case("pentium4", CK_Pentium4) 2678 .Case("pentium4m", CK_Pentium4M) 2679 .Case("prescott", CK_Prescott) 2680 .Case("nocona", CK_Nocona) 2681 .Case("core2", CK_Core2) 2682 .Case("penryn", CK_Penryn) 2683 .Case("bonnell", CK_Bonnell) 2684 .Case("atom", CK_Bonnell) // Legacy name. 2685 .Case("silvermont", CK_Silvermont) 2686 .Case("slm", CK_Silvermont) // Legacy name. 2687 .Case("nehalem", CK_Nehalem) 2688 .Case("corei7", CK_Nehalem) // Legacy name. 2689 .Case("westmere", CK_Westmere) 2690 .Case("sandybridge", CK_SandyBridge) 2691 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2692 .Case("ivybridge", CK_IvyBridge) 2693 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2694 .Case("haswell", CK_Haswell) 2695 .Case("core-avx2", CK_Haswell) // Legacy name. 2696 .Case("broadwell", CK_Broadwell) 2697 .Case("skylake", CK_SkylakeClient) 2698 .Case("skylake-avx512", CK_SkylakeServer) 2699 .Case("skx", CK_SkylakeServer) // Legacy name. 2700 .Case("cannonlake", CK_Cannonlake) 2701 .Case("knl", CK_KNL) 2702 .Case("lakemont", CK_Lakemont) 2703 .Case("k6", CK_K6) 2704 .Case("k6-2", CK_K6_2) 2705 .Case("k6-3", CK_K6_3) 2706 .Case("athlon", CK_Athlon) 2707 .Case("athlon-tbird", CK_AthlonThunderbird) 2708 .Case("athlon-4", CK_Athlon4) 2709 .Case("athlon-xp", CK_AthlonXP) 2710 .Case("athlon-mp", CK_AthlonMP) 2711 .Case("athlon64", CK_Athlon64) 2712 .Case("athlon64-sse3", CK_Athlon64SSE3) 2713 .Case("athlon-fx", CK_AthlonFX) 2714 .Case("k8", CK_K8) 2715 .Case("k8-sse3", CK_K8SSE3) 2716 .Case("opteron", CK_Opteron) 2717 .Case("opteron-sse3", CK_OpteronSSE3) 2718 .Case("barcelona", CK_AMDFAM10) 2719 .Case("amdfam10", CK_AMDFAM10) 2720 .Case("btver1", CK_BTVER1) 2721 .Case("btver2", CK_BTVER2) 2722 .Case("bdver1", CK_BDVER1) 2723 .Case("bdver2", CK_BDVER2) 2724 .Case("bdver3", CK_BDVER3) 2725 .Case("bdver4", CK_BDVER4) 2726 .Case("x86-64", CK_x86_64) 2727 .Case("geode", CK_Geode) 2728 .Default(CK_Generic); 2729 } 2730 2731 enum FPMathKind { 2732 FP_Default, 2733 FP_SSE, 2734 FP_387 2735 } FPMath = FP_Default; 2736 2737 public: 2738 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2739 : TargetInfo(Triple) { 2740 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2741 } 2742 unsigned getFloatEvalMethod() const override { 2743 // X87 evaluates with 80 bits "long double" precision. 2744 return SSELevel == NoSSE ? 2 : 0; 2745 } 2746 ArrayRef<const char *> getGCCRegNames() const override { 2747 return llvm::makeArrayRef(GCCRegNames); 2748 } 2749 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2750 return None; 2751 } 2752 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2753 return llvm::makeArrayRef(AddlRegNames); 2754 } 2755 bool validateCpuSupports(StringRef Name) const override; 2756 bool validateAsmConstraint(const char *&Name, 2757 TargetInfo::ConstraintInfo &info) const override; 2758 2759 bool validateGlobalRegisterVariable(StringRef RegName, 2760 unsigned RegSize, 2761 bool &HasSizeMismatch) const override { 2762 // esp and ebp are the only 32-bit registers the x86 backend can currently 2763 // handle. 2764 if (RegName.equals("esp") || RegName.equals("ebp")) { 2765 // Check that the register size is 32-bit. 2766 HasSizeMismatch = RegSize != 32; 2767 return true; 2768 } 2769 2770 return false; 2771 } 2772 2773 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2774 2775 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2776 2777 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2778 2779 std::string convertConstraint(const char *&Constraint) const override; 2780 const char *getClobbers() const override { 2781 return "~{dirflag},~{fpsr},~{flags}"; 2782 } 2783 void getTargetDefines(const LangOptions &Opts, 2784 MacroBuilder &Builder) const override; 2785 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2786 bool Enabled); 2787 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2788 bool Enabled); 2789 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2790 bool Enabled); 2791 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2792 StringRef Name, bool Enabled) const override { 2793 setFeatureEnabledImpl(Features, Name, Enabled); 2794 } 2795 // This exists purely to cut down on the number of virtual calls in 2796 // initFeatureMap which calls this repeatedly. 2797 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2798 StringRef Name, bool Enabled); 2799 bool 2800 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2801 StringRef CPU, 2802 const std::vector<std::string> &FeaturesVec) const override; 2803 bool hasFeature(StringRef Feature) const override; 2804 bool handleTargetFeatures(std::vector<std::string> &Features, 2805 DiagnosticsEngine &Diags) override; 2806 StringRef getABI() const override { 2807 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2808 return "avx512"; 2809 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2810 return "avx"; 2811 if (getTriple().getArch() == llvm::Triple::x86 && 2812 MMX3DNowLevel == NoMMX3DNow) 2813 return "no-mmx"; 2814 return ""; 2815 } 2816 bool setCPU(const std::string &Name) override { 2817 CPU = getCPUKind(Name); 2818 2819 // Perform any per-CPU checks necessary to determine if this CPU is 2820 // acceptable. 2821 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2822 // invalid without explaining *why*. 2823 switch (CPU) { 2824 case CK_Generic: 2825 // No processor selected! 2826 return false; 2827 2828 case CK_i386: 2829 case CK_i486: 2830 case CK_WinChipC6: 2831 case CK_WinChip2: 2832 case CK_C3: 2833 case CK_i586: 2834 case CK_Pentium: 2835 case CK_PentiumMMX: 2836 case CK_i686: 2837 case CK_PentiumPro: 2838 case CK_Pentium2: 2839 case CK_Pentium3: 2840 case CK_Pentium3M: 2841 case CK_PentiumM: 2842 case CK_Yonah: 2843 case CK_C3_2: 2844 case CK_Pentium4: 2845 case CK_Pentium4M: 2846 case CK_Lakemont: 2847 case CK_Prescott: 2848 case CK_K6: 2849 case CK_K6_2: 2850 case CK_K6_3: 2851 case CK_Athlon: 2852 case CK_AthlonThunderbird: 2853 case CK_Athlon4: 2854 case CK_AthlonXP: 2855 case CK_AthlonMP: 2856 case CK_Geode: 2857 // Only accept certain architectures when compiling in 32-bit mode. 2858 if (getTriple().getArch() != llvm::Triple::x86) 2859 return false; 2860 2861 // Fallthrough 2862 case CK_Nocona: 2863 case CK_Core2: 2864 case CK_Penryn: 2865 case CK_Bonnell: 2866 case CK_Silvermont: 2867 case CK_Nehalem: 2868 case CK_Westmere: 2869 case CK_SandyBridge: 2870 case CK_IvyBridge: 2871 case CK_Haswell: 2872 case CK_Broadwell: 2873 case CK_SkylakeClient: 2874 case CK_SkylakeServer: 2875 case CK_Cannonlake: 2876 case CK_KNL: 2877 case CK_Athlon64: 2878 case CK_Athlon64SSE3: 2879 case CK_AthlonFX: 2880 case CK_K8: 2881 case CK_K8SSE3: 2882 case CK_Opteron: 2883 case CK_OpteronSSE3: 2884 case CK_AMDFAM10: 2885 case CK_BTVER1: 2886 case CK_BTVER2: 2887 case CK_BDVER1: 2888 case CK_BDVER2: 2889 case CK_BDVER3: 2890 case CK_BDVER4: 2891 case CK_x86_64: 2892 return true; 2893 } 2894 llvm_unreachable("Unhandled CPU kind"); 2895 } 2896 2897 bool setFPMath(StringRef Name) override; 2898 2899 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2900 // Most of the non-ARM calling conventions are i386 conventions. 2901 switch (CC) { 2902 case CC_X86ThisCall: 2903 case CC_X86FastCall: 2904 case CC_X86StdCall: 2905 case CC_X86VectorCall: 2906 case CC_C: 2907 case CC_Swift: 2908 case CC_X86Pascal: 2909 case CC_IntelOclBicc: 2910 return CCCR_OK; 2911 default: 2912 return CCCR_Warning; 2913 } 2914 } 2915 2916 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2917 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2918 } 2919 2920 bool hasSjLjLowering() const override { 2921 return true; 2922 } 2923 2924 void setSupportedOpenCLOpts() override { 2925 getSupportedOpenCLOpts().setAll(); 2926 } 2927 }; 2928 2929 bool X86TargetInfo::setFPMath(StringRef Name) { 2930 if (Name == "387") { 2931 FPMath = FP_387; 2932 return true; 2933 } 2934 if (Name == "sse") { 2935 FPMath = FP_SSE; 2936 return true; 2937 } 2938 return false; 2939 } 2940 2941 bool X86TargetInfo::initFeatureMap( 2942 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2943 const std::vector<std::string> &FeaturesVec) const { 2944 // FIXME: This *really* should not be here. 2945 // X86_64 always has SSE2. 2946 if (getTriple().getArch() == llvm::Triple::x86_64) 2947 setFeatureEnabledImpl(Features, "sse2", true); 2948 2949 const CPUKind Kind = getCPUKind(CPU); 2950 2951 // Enable X87 for all X86 processors but Lakemont. 2952 if (Kind != CK_Lakemont) 2953 setFeatureEnabledImpl(Features, "x87", true); 2954 2955 switch (Kind) { 2956 case CK_Generic: 2957 case CK_i386: 2958 case CK_i486: 2959 case CK_i586: 2960 case CK_Pentium: 2961 case CK_i686: 2962 case CK_PentiumPro: 2963 case CK_Lakemont: 2964 break; 2965 case CK_PentiumMMX: 2966 case CK_Pentium2: 2967 case CK_K6: 2968 case CK_WinChipC6: 2969 setFeatureEnabledImpl(Features, "mmx", true); 2970 break; 2971 case CK_Pentium3: 2972 case CK_Pentium3M: 2973 case CK_C3_2: 2974 setFeatureEnabledImpl(Features, "sse", true); 2975 setFeatureEnabledImpl(Features, "fxsr", true); 2976 break; 2977 case CK_PentiumM: 2978 case CK_Pentium4: 2979 case CK_Pentium4M: 2980 case CK_x86_64: 2981 setFeatureEnabledImpl(Features, "sse2", true); 2982 setFeatureEnabledImpl(Features, "fxsr", true); 2983 break; 2984 case CK_Yonah: 2985 case CK_Prescott: 2986 case CK_Nocona: 2987 setFeatureEnabledImpl(Features, "sse3", true); 2988 setFeatureEnabledImpl(Features, "fxsr", true); 2989 setFeatureEnabledImpl(Features, "cx16", true); 2990 break; 2991 case CK_Core2: 2992 case CK_Bonnell: 2993 setFeatureEnabledImpl(Features, "ssse3", true); 2994 setFeatureEnabledImpl(Features, "fxsr", true); 2995 setFeatureEnabledImpl(Features, "cx16", true); 2996 break; 2997 case CK_Penryn: 2998 setFeatureEnabledImpl(Features, "sse4.1", true); 2999 setFeatureEnabledImpl(Features, "fxsr", true); 3000 setFeatureEnabledImpl(Features, "cx16", true); 3001 break; 3002 case CK_Cannonlake: 3003 setFeatureEnabledImpl(Features, "avx512ifma", true); 3004 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3005 setFeatureEnabledImpl(Features, "sha", true); 3006 setFeatureEnabledImpl(Features, "umip", true); 3007 // FALLTHROUGH 3008 case CK_SkylakeServer: 3009 setFeatureEnabledImpl(Features, "avx512f", true); 3010 setFeatureEnabledImpl(Features, "avx512cd", true); 3011 setFeatureEnabledImpl(Features, "avx512dq", true); 3012 setFeatureEnabledImpl(Features, "avx512bw", true); 3013 setFeatureEnabledImpl(Features, "avx512vl", true); 3014 setFeatureEnabledImpl(Features, "pku", true); 3015 setFeatureEnabledImpl(Features, "pcommit", true); 3016 setFeatureEnabledImpl(Features, "clwb", true); 3017 // FALLTHROUGH 3018 case CK_SkylakeClient: 3019 setFeatureEnabledImpl(Features, "xsavec", true); 3020 setFeatureEnabledImpl(Features, "xsaves", true); 3021 setFeatureEnabledImpl(Features, "mpx", true); 3022 setFeatureEnabledImpl(Features, "sgx", true); 3023 setFeatureEnabledImpl(Features, "clflushopt", true); 3024 // FALLTHROUGH 3025 case CK_Broadwell: 3026 setFeatureEnabledImpl(Features, "rdseed", true); 3027 setFeatureEnabledImpl(Features, "adx", true); 3028 // FALLTHROUGH 3029 case CK_Haswell: 3030 setFeatureEnabledImpl(Features, "avx2", true); 3031 setFeatureEnabledImpl(Features, "lzcnt", true); 3032 setFeatureEnabledImpl(Features, "bmi", true); 3033 setFeatureEnabledImpl(Features, "bmi2", true); 3034 setFeatureEnabledImpl(Features, "rtm", true); 3035 setFeatureEnabledImpl(Features, "fma", true); 3036 setFeatureEnabledImpl(Features, "movbe", true); 3037 // FALLTHROUGH 3038 case CK_IvyBridge: 3039 setFeatureEnabledImpl(Features, "rdrnd", true); 3040 setFeatureEnabledImpl(Features, "f16c", true); 3041 setFeatureEnabledImpl(Features, "fsgsbase", true); 3042 // FALLTHROUGH 3043 case CK_SandyBridge: 3044 setFeatureEnabledImpl(Features, "avx", true); 3045 setFeatureEnabledImpl(Features, "xsave", true); 3046 setFeatureEnabledImpl(Features, "xsaveopt", true); 3047 // FALLTHROUGH 3048 case CK_Westmere: 3049 case CK_Silvermont: 3050 setFeatureEnabledImpl(Features, "aes", true); 3051 setFeatureEnabledImpl(Features, "pclmul", true); 3052 // FALLTHROUGH 3053 case CK_Nehalem: 3054 setFeatureEnabledImpl(Features, "sse4.2", true); 3055 setFeatureEnabledImpl(Features, "fxsr", true); 3056 setFeatureEnabledImpl(Features, "cx16", true); 3057 break; 3058 case CK_KNL: 3059 setFeatureEnabledImpl(Features, "avx512f", true); 3060 setFeatureEnabledImpl(Features, "avx512cd", true); 3061 setFeatureEnabledImpl(Features, "avx512er", true); 3062 setFeatureEnabledImpl(Features, "avx512pf", true); 3063 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3064 setFeatureEnabledImpl(Features, "fxsr", true); 3065 setFeatureEnabledImpl(Features, "rdseed", true); 3066 setFeatureEnabledImpl(Features, "adx", true); 3067 setFeatureEnabledImpl(Features, "lzcnt", true); 3068 setFeatureEnabledImpl(Features, "bmi", true); 3069 setFeatureEnabledImpl(Features, "bmi2", true); 3070 setFeatureEnabledImpl(Features, "rtm", true); 3071 setFeatureEnabledImpl(Features, "fma", true); 3072 setFeatureEnabledImpl(Features, "rdrnd", true); 3073 setFeatureEnabledImpl(Features, "f16c", true); 3074 setFeatureEnabledImpl(Features, "fsgsbase", true); 3075 setFeatureEnabledImpl(Features, "aes", true); 3076 setFeatureEnabledImpl(Features, "pclmul", true); 3077 setFeatureEnabledImpl(Features, "cx16", true); 3078 setFeatureEnabledImpl(Features, "xsaveopt", true); 3079 setFeatureEnabledImpl(Features, "xsave", true); 3080 setFeatureEnabledImpl(Features, "movbe", true); 3081 break; 3082 case CK_K6_2: 3083 case CK_K6_3: 3084 case CK_WinChip2: 3085 case CK_C3: 3086 setFeatureEnabledImpl(Features, "3dnow", true); 3087 break; 3088 case CK_Athlon: 3089 case CK_AthlonThunderbird: 3090 case CK_Geode: 3091 setFeatureEnabledImpl(Features, "3dnowa", true); 3092 break; 3093 case CK_Athlon4: 3094 case CK_AthlonXP: 3095 case CK_AthlonMP: 3096 setFeatureEnabledImpl(Features, "sse", true); 3097 setFeatureEnabledImpl(Features, "3dnowa", true); 3098 setFeatureEnabledImpl(Features, "fxsr", true); 3099 break; 3100 case CK_K8: 3101 case CK_Opteron: 3102 case CK_Athlon64: 3103 case CK_AthlonFX: 3104 setFeatureEnabledImpl(Features, "sse2", true); 3105 setFeatureEnabledImpl(Features, "3dnowa", true); 3106 setFeatureEnabledImpl(Features, "fxsr", true); 3107 break; 3108 case CK_AMDFAM10: 3109 setFeatureEnabledImpl(Features, "sse4a", true); 3110 setFeatureEnabledImpl(Features, "lzcnt", true); 3111 setFeatureEnabledImpl(Features, "popcnt", true); 3112 // FALLTHROUGH 3113 case CK_K8SSE3: 3114 case CK_OpteronSSE3: 3115 case CK_Athlon64SSE3: 3116 setFeatureEnabledImpl(Features, "sse3", true); 3117 setFeatureEnabledImpl(Features, "3dnowa", true); 3118 setFeatureEnabledImpl(Features, "fxsr", true); 3119 break; 3120 case CK_BTVER2: 3121 setFeatureEnabledImpl(Features, "avx", true); 3122 setFeatureEnabledImpl(Features, "aes", true); 3123 setFeatureEnabledImpl(Features, "pclmul", true); 3124 setFeatureEnabledImpl(Features, "bmi", true); 3125 setFeatureEnabledImpl(Features, "f16c", true); 3126 setFeatureEnabledImpl(Features, "xsaveopt", true); 3127 // FALLTHROUGH 3128 case CK_BTVER1: 3129 setFeatureEnabledImpl(Features, "ssse3", true); 3130 setFeatureEnabledImpl(Features, "sse4a", true); 3131 setFeatureEnabledImpl(Features, "lzcnt", true); 3132 setFeatureEnabledImpl(Features, "popcnt", true); 3133 setFeatureEnabledImpl(Features, "prfchw", true); 3134 setFeatureEnabledImpl(Features, "cx16", true); 3135 setFeatureEnabledImpl(Features, "fxsr", true); 3136 break; 3137 case CK_BDVER4: 3138 setFeatureEnabledImpl(Features, "avx2", true); 3139 setFeatureEnabledImpl(Features, "bmi2", true); 3140 setFeatureEnabledImpl(Features, "mwaitx", true); 3141 // FALLTHROUGH 3142 case CK_BDVER3: 3143 setFeatureEnabledImpl(Features, "fsgsbase", true); 3144 setFeatureEnabledImpl(Features, "xsaveopt", true); 3145 // FALLTHROUGH 3146 case CK_BDVER2: 3147 setFeatureEnabledImpl(Features, "bmi", true); 3148 setFeatureEnabledImpl(Features, "fma", true); 3149 setFeatureEnabledImpl(Features, "f16c", true); 3150 setFeatureEnabledImpl(Features, "tbm", true); 3151 // FALLTHROUGH 3152 case CK_BDVER1: 3153 // xop implies avx, sse4a and fma4. 3154 setFeatureEnabledImpl(Features, "xop", true); 3155 setFeatureEnabledImpl(Features, "lzcnt", true); 3156 setFeatureEnabledImpl(Features, "aes", true); 3157 setFeatureEnabledImpl(Features, "pclmul", true); 3158 setFeatureEnabledImpl(Features, "prfchw", true); 3159 setFeatureEnabledImpl(Features, "cx16", true); 3160 setFeatureEnabledImpl(Features, "fxsr", true); 3161 setFeatureEnabledImpl(Features, "xsave", true); 3162 break; 3163 } 3164 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3165 return false; 3166 3167 // Can't do this earlier because we need to be able to explicitly enable 3168 // or disable these features and the things that they depend upon. 3169 3170 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3171 auto I = Features.find("sse4.2"); 3172 if (I != Features.end() && I->getValue() && 3173 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3174 FeaturesVec.end()) 3175 Features["popcnt"] = true; 3176 3177 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3178 I = Features.find("3dnow"); 3179 if (I != Features.end() && I->getValue() && 3180 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3181 FeaturesVec.end()) 3182 Features["prfchw"] = true; 3183 3184 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3185 // then enable MMX. 3186 I = Features.find("sse"); 3187 if (I != Features.end() && I->getValue() && 3188 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3189 FeaturesVec.end()) 3190 Features["mmx"] = true; 3191 3192 return true; 3193 } 3194 3195 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3196 X86SSEEnum Level, bool Enabled) { 3197 if (Enabled) { 3198 switch (Level) { 3199 case AVX512F: 3200 Features["avx512f"] = true; 3201 case AVX2: 3202 Features["avx2"] = true; 3203 case AVX: 3204 Features["avx"] = true; 3205 Features["xsave"] = true; 3206 case SSE42: 3207 Features["sse4.2"] = true; 3208 case SSE41: 3209 Features["sse4.1"] = true; 3210 case SSSE3: 3211 Features["ssse3"] = true; 3212 case SSE3: 3213 Features["sse3"] = true; 3214 case SSE2: 3215 Features["sse2"] = true; 3216 case SSE1: 3217 Features["sse"] = true; 3218 case NoSSE: 3219 break; 3220 } 3221 return; 3222 } 3223 3224 switch (Level) { 3225 case NoSSE: 3226 case SSE1: 3227 Features["sse"] = false; 3228 case SSE2: 3229 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3230 Features["sha"] = false; 3231 case SSE3: 3232 Features["sse3"] = false; 3233 setXOPLevel(Features, NoXOP, false); 3234 case SSSE3: 3235 Features["ssse3"] = false; 3236 case SSE41: 3237 Features["sse4.1"] = false; 3238 case SSE42: 3239 Features["sse4.2"] = false; 3240 case AVX: 3241 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3242 Features["xsaveopt"] = false; 3243 setXOPLevel(Features, FMA4, false); 3244 case AVX2: 3245 Features["avx2"] = false; 3246 case AVX512F: 3247 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3248 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3249 Features["avx512vl"] = Features["avx512vbmi"] = 3250 Features["avx512ifma"] = false; 3251 } 3252 } 3253 3254 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3255 MMX3DNowEnum Level, bool Enabled) { 3256 if (Enabled) { 3257 switch (Level) { 3258 case AMD3DNowAthlon: 3259 Features["3dnowa"] = true; 3260 case AMD3DNow: 3261 Features["3dnow"] = true; 3262 case MMX: 3263 Features["mmx"] = true; 3264 case NoMMX3DNow: 3265 break; 3266 } 3267 return; 3268 } 3269 3270 switch (Level) { 3271 case NoMMX3DNow: 3272 case MMX: 3273 Features["mmx"] = false; 3274 case AMD3DNow: 3275 Features["3dnow"] = false; 3276 case AMD3DNowAthlon: 3277 Features["3dnowa"] = false; 3278 } 3279 } 3280 3281 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3282 bool Enabled) { 3283 if (Enabled) { 3284 switch (Level) { 3285 case XOP: 3286 Features["xop"] = true; 3287 case FMA4: 3288 Features["fma4"] = true; 3289 setSSELevel(Features, AVX, true); 3290 case SSE4A: 3291 Features["sse4a"] = true; 3292 setSSELevel(Features, SSE3, true); 3293 case NoXOP: 3294 break; 3295 } 3296 return; 3297 } 3298 3299 switch (Level) { 3300 case NoXOP: 3301 case SSE4A: 3302 Features["sse4a"] = false; 3303 case FMA4: 3304 Features["fma4"] = false; 3305 case XOP: 3306 Features["xop"] = false; 3307 } 3308 } 3309 3310 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3311 StringRef Name, bool Enabled) { 3312 // This is a bit of a hack to deal with the sse4 target feature when used 3313 // as part of the target attribute. We handle sse4 correctly everywhere 3314 // else. See below for more information on how we handle the sse4 options. 3315 if (Name != "sse4") 3316 Features[Name] = Enabled; 3317 3318 if (Name == "mmx") { 3319 setMMXLevel(Features, MMX, Enabled); 3320 } else if (Name == "sse") { 3321 setSSELevel(Features, SSE1, Enabled); 3322 } else if (Name == "sse2") { 3323 setSSELevel(Features, SSE2, Enabled); 3324 } else if (Name == "sse3") { 3325 setSSELevel(Features, SSE3, Enabled); 3326 } else if (Name == "ssse3") { 3327 setSSELevel(Features, SSSE3, Enabled); 3328 } else if (Name == "sse4.2") { 3329 setSSELevel(Features, SSE42, Enabled); 3330 } else if (Name == "sse4.1") { 3331 setSSELevel(Features, SSE41, Enabled); 3332 } else if (Name == "3dnow") { 3333 setMMXLevel(Features, AMD3DNow, Enabled); 3334 } else if (Name == "3dnowa") { 3335 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3336 } else if (Name == "aes") { 3337 if (Enabled) 3338 setSSELevel(Features, SSE2, Enabled); 3339 } else if (Name == "pclmul") { 3340 if (Enabled) 3341 setSSELevel(Features, SSE2, Enabled); 3342 } else if (Name == "avx") { 3343 setSSELevel(Features, AVX, Enabled); 3344 } else if (Name == "avx2") { 3345 setSSELevel(Features, AVX2, Enabled); 3346 } else if (Name == "avx512f") { 3347 setSSELevel(Features, AVX512F, Enabled); 3348 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3349 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3350 Name == "avx512vbmi" || Name == "avx512ifma") { 3351 if (Enabled) 3352 setSSELevel(Features, AVX512F, Enabled); 3353 } else if (Name == "fma") { 3354 if (Enabled) 3355 setSSELevel(Features, AVX, Enabled); 3356 } else if (Name == "fma4") { 3357 setXOPLevel(Features, FMA4, Enabled); 3358 } else if (Name == "xop") { 3359 setXOPLevel(Features, XOP, Enabled); 3360 } else if (Name == "sse4a") { 3361 setXOPLevel(Features, SSE4A, Enabled); 3362 } else if (Name == "f16c") { 3363 if (Enabled) 3364 setSSELevel(Features, AVX, Enabled); 3365 } else if (Name == "sha") { 3366 if (Enabled) 3367 setSSELevel(Features, SSE2, Enabled); 3368 } else if (Name == "sse4") { 3369 // We can get here via the __target__ attribute since that's not controlled 3370 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3371 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3372 // disabled. 3373 if (Enabled) 3374 setSSELevel(Features, SSE42, Enabled); 3375 else 3376 setSSELevel(Features, SSE41, Enabled); 3377 } else if (Name == "xsave") { 3378 if (!Enabled) 3379 Features["xsaveopt"] = false; 3380 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3381 if (Enabled) 3382 Features["xsave"] = true; 3383 } 3384 } 3385 3386 /// handleTargetFeatures - Perform initialization based on the user 3387 /// configured set of features. 3388 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3389 DiagnosticsEngine &Diags) { 3390 for (const auto &Feature : Features) { 3391 if (Feature[0] != '+') 3392 continue; 3393 3394 if (Feature == "+aes") { 3395 HasAES = true; 3396 } else if (Feature == "+pclmul") { 3397 HasPCLMUL = true; 3398 } else if (Feature == "+lzcnt") { 3399 HasLZCNT = true; 3400 } else if (Feature == "+rdrnd") { 3401 HasRDRND = true; 3402 } else if (Feature == "+fsgsbase") { 3403 HasFSGSBASE = true; 3404 } else if (Feature == "+bmi") { 3405 HasBMI = true; 3406 } else if (Feature == "+bmi2") { 3407 HasBMI2 = true; 3408 } else if (Feature == "+popcnt") { 3409 HasPOPCNT = true; 3410 } else if (Feature == "+rtm") { 3411 HasRTM = true; 3412 } else if (Feature == "+prfchw") { 3413 HasPRFCHW = true; 3414 } else if (Feature == "+rdseed") { 3415 HasRDSEED = true; 3416 } else if (Feature == "+adx") { 3417 HasADX = true; 3418 } else if (Feature == "+tbm") { 3419 HasTBM = true; 3420 } else if (Feature == "+fma") { 3421 HasFMA = true; 3422 } else if (Feature == "+f16c") { 3423 HasF16C = true; 3424 } else if (Feature == "+avx512cd") { 3425 HasAVX512CD = true; 3426 } else if (Feature == "+avx512er") { 3427 HasAVX512ER = true; 3428 } else if (Feature == "+avx512pf") { 3429 HasAVX512PF = true; 3430 } else if (Feature == "+avx512dq") { 3431 HasAVX512DQ = true; 3432 } else if (Feature == "+avx512bw") { 3433 HasAVX512BW = true; 3434 } else if (Feature == "+avx512vl") { 3435 HasAVX512VL = true; 3436 } else if (Feature == "+avx512vbmi") { 3437 HasAVX512VBMI = true; 3438 } else if (Feature == "+avx512ifma") { 3439 HasAVX512IFMA = true; 3440 } else if (Feature == "+sha") { 3441 HasSHA = true; 3442 } else if (Feature == "+mpx") { 3443 HasMPX = true; 3444 } else if (Feature == "+movbe") { 3445 HasMOVBE = true; 3446 } else if (Feature == "+sgx") { 3447 HasSGX = true; 3448 } else if (Feature == "+cx16") { 3449 HasCX16 = true; 3450 } else if (Feature == "+fxsr") { 3451 HasFXSR = true; 3452 } else if (Feature == "+xsave") { 3453 HasXSAVE = true; 3454 } else if (Feature == "+xsaveopt") { 3455 HasXSAVEOPT = true; 3456 } else if (Feature == "+xsavec") { 3457 HasXSAVEC = true; 3458 } else if (Feature == "+xsaves") { 3459 HasXSAVES = true; 3460 } else if (Feature == "+mwaitx") { 3461 HasMWAITX = true; 3462 } else if (Feature == "+pku") { 3463 HasPKU = true; 3464 } else if (Feature == "+clflushopt") { 3465 HasCLFLUSHOPT = true; 3466 } else if (Feature == "+pcommit") { 3467 HasPCOMMIT = true; 3468 } else if (Feature == "+clwb") { 3469 HasCLWB = true; 3470 } else if (Feature == "+umip") { 3471 HasUMIP = true; 3472 } else if (Feature == "+prefetchwt1") { 3473 HasPREFETCHWT1 = true; 3474 } 3475 3476 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3477 .Case("+avx512f", AVX512F) 3478 .Case("+avx2", AVX2) 3479 .Case("+avx", AVX) 3480 .Case("+sse4.2", SSE42) 3481 .Case("+sse4.1", SSE41) 3482 .Case("+ssse3", SSSE3) 3483 .Case("+sse3", SSE3) 3484 .Case("+sse2", SSE2) 3485 .Case("+sse", SSE1) 3486 .Default(NoSSE); 3487 SSELevel = std::max(SSELevel, Level); 3488 3489 MMX3DNowEnum ThreeDNowLevel = 3490 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3491 .Case("+3dnowa", AMD3DNowAthlon) 3492 .Case("+3dnow", AMD3DNow) 3493 .Case("+mmx", MMX) 3494 .Default(NoMMX3DNow); 3495 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3496 3497 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3498 .Case("+xop", XOP) 3499 .Case("+fma4", FMA4) 3500 .Case("+sse4a", SSE4A) 3501 .Default(NoXOP); 3502 XOPLevel = std::max(XOPLevel, XLevel); 3503 } 3504 3505 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3506 // matches the selected sse level. 3507 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3508 (FPMath == FP_387 && SSELevel >= SSE1)) { 3509 Diags.Report(diag::err_target_unsupported_fpmath) << 3510 (FPMath == FP_SSE ? "sse" : "387"); 3511 return false; 3512 } 3513 3514 SimdDefaultAlign = 3515 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3516 return true; 3517 } 3518 3519 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3520 /// definitions for this particular subtarget. 3521 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3522 MacroBuilder &Builder) const { 3523 // Target identification. 3524 if (getTriple().getArch() == llvm::Triple::x86_64) { 3525 Builder.defineMacro("__amd64__"); 3526 Builder.defineMacro("__amd64"); 3527 Builder.defineMacro("__x86_64"); 3528 Builder.defineMacro("__x86_64__"); 3529 if (getTriple().getArchName() == "x86_64h") { 3530 Builder.defineMacro("__x86_64h"); 3531 Builder.defineMacro("__x86_64h__"); 3532 } 3533 } else { 3534 DefineStd(Builder, "i386", Opts); 3535 } 3536 3537 // Subtarget options. 3538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3539 // truly should be based on -mtune options. 3540 switch (CPU) { 3541 case CK_Generic: 3542 break; 3543 case CK_i386: 3544 // The rest are coming from the i386 define above. 3545 Builder.defineMacro("__tune_i386__"); 3546 break; 3547 case CK_i486: 3548 case CK_WinChipC6: 3549 case CK_WinChip2: 3550 case CK_C3: 3551 defineCPUMacros(Builder, "i486"); 3552 break; 3553 case CK_PentiumMMX: 3554 Builder.defineMacro("__pentium_mmx__"); 3555 Builder.defineMacro("__tune_pentium_mmx__"); 3556 // Fallthrough 3557 case CK_i586: 3558 case CK_Pentium: 3559 defineCPUMacros(Builder, "i586"); 3560 defineCPUMacros(Builder, "pentium"); 3561 break; 3562 case CK_Pentium3: 3563 case CK_Pentium3M: 3564 case CK_PentiumM: 3565 Builder.defineMacro("__tune_pentium3__"); 3566 // Fallthrough 3567 case CK_Pentium2: 3568 case CK_C3_2: 3569 Builder.defineMacro("__tune_pentium2__"); 3570 // Fallthrough 3571 case CK_PentiumPro: 3572 Builder.defineMacro("__tune_i686__"); 3573 Builder.defineMacro("__tune_pentiumpro__"); 3574 // Fallthrough 3575 case CK_i686: 3576 Builder.defineMacro("__i686"); 3577 Builder.defineMacro("__i686__"); 3578 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3579 Builder.defineMacro("__pentiumpro"); 3580 Builder.defineMacro("__pentiumpro__"); 3581 break; 3582 case CK_Pentium4: 3583 case CK_Pentium4M: 3584 defineCPUMacros(Builder, "pentium4"); 3585 break; 3586 case CK_Yonah: 3587 case CK_Prescott: 3588 case CK_Nocona: 3589 defineCPUMacros(Builder, "nocona"); 3590 break; 3591 case CK_Core2: 3592 case CK_Penryn: 3593 defineCPUMacros(Builder, "core2"); 3594 break; 3595 case CK_Bonnell: 3596 defineCPUMacros(Builder, "atom"); 3597 break; 3598 case CK_Silvermont: 3599 defineCPUMacros(Builder, "slm"); 3600 break; 3601 case CK_Nehalem: 3602 case CK_Westmere: 3603 case CK_SandyBridge: 3604 case CK_IvyBridge: 3605 case CK_Haswell: 3606 case CK_Broadwell: 3607 case CK_SkylakeClient: 3608 // FIXME: Historically, we defined this legacy name, it would be nice to 3609 // remove it at some point. We've never exposed fine-grained names for 3610 // recent primary x86 CPUs, and we should keep it that way. 3611 defineCPUMacros(Builder, "corei7"); 3612 break; 3613 case CK_SkylakeServer: 3614 defineCPUMacros(Builder, "skx"); 3615 break; 3616 case CK_Cannonlake: 3617 break; 3618 case CK_KNL: 3619 defineCPUMacros(Builder, "knl"); 3620 break; 3621 case CK_Lakemont: 3622 Builder.defineMacro("__tune_lakemont__"); 3623 break; 3624 case CK_K6_2: 3625 Builder.defineMacro("__k6_2__"); 3626 Builder.defineMacro("__tune_k6_2__"); 3627 // Fallthrough 3628 case CK_K6_3: 3629 if (CPU != CK_K6_2) { // In case of fallthrough 3630 // FIXME: GCC may be enabling these in cases where some other k6 3631 // architecture is specified but -m3dnow is explicitly provided. The 3632 // exact semantics need to be determined and emulated here. 3633 Builder.defineMacro("__k6_3__"); 3634 Builder.defineMacro("__tune_k6_3__"); 3635 } 3636 // Fallthrough 3637 case CK_K6: 3638 defineCPUMacros(Builder, "k6"); 3639 break; 3640 case CK_Athlon: 3641 case CK_AthlonThunderbird: 3642 case CK_Athlon4: 3643 case CK_AthlonXP: 3644 case CK_AthlonMP: 3645 defineCPUMacros(Builder, "athlon"); 3646 if (SSELevel != NoSSE) { 3647 Builder.defineMacro("__athlon_sse__"); 3648 Builder.defineMacro("__tune_athlon_sse__"); 3649 } 3650 break; 3651 case CK_K8: 3652 case CK_K8SSE3: 3653 case CK_x86_64: 3654 case CK_Opteron: 3655 case CK_OpteronSSE3: 3656 case CK_Athlon64: 3657 case CK_Athlon64SSE3: 3658 case CK_AthlonFX: 3659 defineCPUMacros(Builder, "k8"); 3660 break; 3661 case CK_AMDFAM10: 3662 defineCPUMacros(Builder, "amdfam10"); 3663 break; 3664 case CK_BTVER1: 3665 defineCPUMacros(Builder, "btver1"); 3666 break; 3667 case CK_BTVER2: 3668 defineCPUMacros(Builder, "btver2"); 3669 break; 3670 case CK_BDVER1: 3671 defineCPUMacros(Builder, "bdver1"); 3672 break; 3673 case CK_BDVER2: 3674 defineCPUMacros(Builder, "bdver2"); 3675 break; 3676 case CK_BDVER3: 3677 defineCPUMacros(Builder, "bdver3"); 3678 break; 3679 case CK_BDVER4: 3680 defineCPUMacros(Builder, "bdver4"); 3681 break; 3682 case CK_Geode: 3683 defineCPUMacros(Builder, "geode"); 3684 break; 3685 } 3686 3687 // Target properties. 3688 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3689 3690 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3691 // functions in glibc header files that use FP Stack inline asm which the 3692 // backend can't deal with (PR879). 3693 Builder.defineMacro("__NO_MATH_INLINES"); 3694 3695 if (HasAES) 3696 Builder.defineMacro("__AES__"); 3697 3698 if (HasPCLMUL) 3699 Builder.defineMacro("__PCLMUL__"); 3700 3701 if (HasLZCNT) 3702 Builder.defineMacro("__LZCNT__"); 3703 3704 if (HasRDRND) 3705 Builder.defineMacro("__RDRND__"); 3706 3707 if (HasFSGSBASE) 3708 Builder.defineMacro("__FSGSBASE__"); 3709 3710 if (HasBMI) 3711 Builder.defineMacro("__BMI__"); 3712 3713 if (HasBMI2) 3714 Builder.defineMacro("__BMI2__"); 3715 3716 if (HasPOPCNT) 3717 Builder.defineMacro("__POPCNT__"); 3718 3719 if (HasRTM) 3720 Builder.defineMacro("__RTM__"); 3721 3722 if (HasPRFCHW) 3723 Builder.defineMacro("__PRFCHW__"); 3724 3725 if (HasRDSEED) 3726 Builder.defineMacro("__RDSEED__"); 3727 3728 if (HasADX) 3729 Builder.defineMacro("__ADX__"); 3730 3731 if (HasTBM) 3732 Builder.defineMacro("__TBM__"); 3733 3734 if (HasMWAITX) 3735 Builder.defineMacro("__MWAITX__"); 3736 3737 switch (XOPLevel) { 3738 case XOP: 3739 Builder.defineMacro("__XOP__"); 3740 case FMA4: 3741 Builder.defineMacro("__FMA4__"); 3742 case SSE4A: 3743 Builder.defineMacro("__SSE4A__"); 3744 case NoXOP: 3745 break; 3746 } 3747 3748 if (HasFMA) 3749 Builder.defineMacro("__FMA__"); 3750 3751 if (HasF16C) 3752 Builder.defineMacro("__F16C__"); 3753 3754 if (HasAVX512CD) 3755 Builder.defineMacro("__AVX512CD__"); 3756 if (HasAVX512ER) 3757 Builder.defineMacro("__AVX512ER__"); 3758 if (HasAVX512PF) 3759 Builder.defineMacro("__AVX512PF__"); 3760 if (HasAVX512DQ) 3761 Builder.defineMacro("__AVX512DQ__"); 3762 if (HasAVX512BW) 3763 Builder.defineMacro("__AVX512BW__"); 3764 if (HasAVX512VL) 3765 Builder.defineMacro("__AVX512VL__"); 3766 if (HasAVX512VBMI) 3767 Builder.defineMacro("__AVX512VBMI__"); 3768 if (HasAVX512IFMA) 3769 Builder.defineMacro("__AVX512IFMA__"); 3770 3771 if (HasSHA) 3772 Builder.defineMacro("__SHA__"); 3773 3774 if (HasFXSR) 3775 Builder.defineMacro("__FXSR__"); 3776 if (HasXSAVE) 3777 Builder.defineMacro("__XSAVE__"); 3778 if (HasXSAVEOPT) 3779 Builder.defineMacro("__XSAVEOPT__"); 3780 if (HasXSAVEC) 3781 Builder.defineMacro("__XSAVEC__"); 3782 if (HasXSAVES) 3783 Builder.defineMacro("__XSAVES__"); 3784 if (HasPKU) 3785 Builder.defineMacro("__PKU__"); 3786 if (HasCX16) 3787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3788 3789 // Each case falls through to the previous one here. 3790 switch (SSELevel) { 3791 case AVX512F: 3792 Builder.defineMacro("__AVX512F__"); 3793 case AVX2: 3794 Builder.defineMacro("__AVX2__"); 3795 case AVX: 3796 Builder.defineMacro("__AVX__"); 3797 case SSE42: 3798 Builder.defineMacro("__SSE4_2__"); 3799 case SSE41: 3800 Builder.defineMacro("__SSE4_1__"); 3801 case SSSE3: 3802 Builder.defineMacro("__SSSE3__"); 3803 case SSE3: 3804 Builder.defineMacro("__SSE3__"); 3805 case SSE2: 3806 Builder.defineMacro("__SSE2__"); 3807 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3808 case SSE1: 3809 Builder.defineMacro("__SSE__"); 3810 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3811 case NoSSE: 3812 break; 3813 } 3814 3815 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3816 switch (SSELevel) { 3817 case AVX512F: 3818 case AVX2: 3819 case AVX: 3820 case SSE42: 3821 case SSE41: 3822 case SSSE3: 3823 case SSE3: 3824 case SSE2: 3825 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3826 break; 3827 case SSE1: 3828 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3829 break; 3830 default: 3831 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3832 } 3833 } 3834 3835 // Each case falls through to the previous one here. 3836 switch (MMX3DNowLevel) { 3837 case AMD3DNowAthlon: 3838 Builder.defineMacro("__3dNOW_A__"); 3839 case AMD3DNow: 3840 Builder.defineMacro("__3dNOW__"); 3841 case MMX: 3842 Builder.defineMacro("__MMX__"); 3843 case NoMMX3DNow: 3844 break; 3845 } 3846 3847 if (CPU >= CK_i486) { 3848 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3850 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3851 } 3852 if (CPU >= CK_i586) 3853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3854 } 3855 3856 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3857 return llvm::StringSwitch<bool>(Feature) 3858 .Case("aes", HasAES) 3859 .Case("avx", SSELevel >= AVX) 3860 .Case("avx2", SSELevel >= AVX2) 3861 .Case("avx512f", SSELevel >= AVX512F) 3862 .Case("avx512cd", HasAVX512CD) 3863 .Case("avx512er", HasAVX512ER) 3864 .Case("avx512pf", HasAVX512PF) 3865 .Case("avx512dq", HasAVX512DQ) 3866 .Case("avx512bw", HasAVX512BW) 3867 .Case("avx512vl", HasAVX512VL) 3868 .Case("avx512vbmi", HasAVX512VBMI) 3869 .Case("avx512ifma", HasAVX512IFMA) 3870 .Case("bmi", HasBMI) 3871 .Case("bmi2", HasBMI2) 3872 .Case("clflushopt", HasCLFLUSHOPT) 3873 .Case("clwb", HasCLWB) 3874 .Case("cx16", HasCX16) 3875 .Case("f16c", HasF16C) 3876 .Case("fma", HasFMA) 3877 .Case("fma4", XOPLevel >= FMA4) 3878 .Case("fsgsbase", HasFSGSBASE) 3879 .Case("fxsr", HasFXSR) 3880 .Case("lzcnt", HasLZCNT) 3881 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3882 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3883 .Case("mmx", MMX3DNowLevel >= MMX) 3884 .Case("movbe", HasMOVBE) 3885 .Case("mpx", HasMPX) 3886 .Case("pclmul", HasPCLMUL) 3887 .Case("pcommit", HasPCOMMIT) 3888 .Case("pku", HasPKU) 3889 .Case("popcnt", HasPOPCNT) 3890 .Case("prefetchwt1", HasPREFETCHWT1) 3891 .Case("prfchw", HasPRFCHW) 3892 .Case("rdrnd", HasRDRND) 3893 .Case("rdseed", HasRDSEED) 3894 .Case("rtm", HasRTM) 3895 .Case("sgx", HasSGX) 3896 .Case("sha", HasSHA) 3897 .Case("sse", SSELevel >= SSE1) 3898 .Case("sse2", SSELevel >= SSE2) 3899 .Case("sse3", SSELevel >= SSE3) 3900 .Case("ssse3", SSELevel >= SSSE3) 3901 .Case("sse4.1", SSELevel >= SSE41) 3902 .Case("sse4.2", SSELevel >= SSE42) 3903 .Case("sse4a", XOPLevel >= SSE4A) 3904 .Case("tbm", HasTBM) 3905 .Case("umip", HasUMIP) 3906 .Case("x86", true) 3907 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3908 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3909 .Case("xop", XOPLevel >= XOP) 3910 .Case("xsave", HasXSAVE) 3911 .Case("xsavec", HasXSAVEC) 3912 .Case("xsaves", HasXSAVES) 3913 .Case("xsaveopt", HasXSAVEOPT) 3914 .Default(false); 3915 } 3916 3917 // We can't use a generic validation scheme for the features accepted here 3918 // versus subtarget features accepted in the target attribute because the 3919 // bitfield structure that's initialized in the runtime only supports the 3920 // below currently rather than the full range of subtarget features. (See 3921 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3922 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3923 return llvm::StringSwitch<bool>(FeatureStr) 3924 .Case("cmov", true) 3925 .Case("mmx", true) 3926 .Case("popcnt", true) 3927 .Case("sse", true) 3928 .Case("sse2", true) 3929 .Case("sse3", true) 3930 .Case("ssse3", true) 3931 .Case("sse4.1", true) 3932 .Case("sse4.2", true) 3933 .Case("avx", true) 3934 .Case("avx2", true) 3935 .Case("sse4a", true) 3936 .Case("fma4", true) 3937 .Case("xop", true) 3938 .Case("fma", true) 3939 .Case("avx512f", true) 3940 .Case("bmi", true) 3941 .Case("bmi2", true) 3942 .Case("aes", true) 3943 .Case("pclmul", true) 3944 .Case("avx512vl", true) 3945 .Case("avx512bw", true) 3946 .Case("avx512dq", true) 3947 .Case("avx512cd", true) 3948 .Case("avx512er", true) 3949 .Case("avx512pf", true) 3950 .Case("avx512vbmi", true) 3951 .Case("avx512ifma", true) 3952 .Default(false); 3953 } 3954 3955 bool 3956 X86TargetInfo::validateAsmConstraint(const char *&Name, 3957 TargetInfo::ConstraintInfo &Info) const { 3958 switch (*Name) { 3959 default: return false; 3960 // Constant constraints. 3961 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3962 // instructions. 3963 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3964 // x86_64 instructions. 3965 case 's': 3966 Info.setRequiresImmediate(); 3967 return true; 3968 case 'I': 3969 Info.setRequiresImmediate(0, 31); 3970 return true; 3971 case 'J': 3972 Info.setRequiresImmediate(0, 63); 3973 return true; 3974 case 'K': 3975 Info.setRequiresImmediate(-128, 127); 3976 return true; 3977 case 'L': 3978 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3979 return true; 3980 case 'M': 3981 Info.setRequiresImmediate(0, 3); 3982 return true; 3983 case 'N': 3984 Info.setRequiresImmediate(0, 255); 3985 return true; 3986 case 'O': 3987 Info.setRequiresImmediate(0, 127); 3988 return true; 3989 // Register constraints. 3990 case 'Y': // 'Y' is the first character for several 2-character constraints. 3991 // Shift the pointer to the second character of the constraint. 3992 Name++; 3993 switch (*Name) { 3994 default: 3995 return false; 3996 case '0': // First SSE register. 3997 case 't': // Any SSE register, when SSE2 is enabled. 3998 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3999 case 'm': // Any MMX register, when inter-unit moves enabled. 4000 case 'k': // AVX512 arch mask registers: k1-k7. 4001 Info.setAllowsRegister(); 4002 return true; 4003 } 4004 case 'f': // Any x87 floating point stack register. 4005 // Constraint 'f' cannot be used for output operands. 4006 if (Info.ConstraintStr[0] == '=') 4007 return false; 4008 Info.setAllowsRegister(); 4009 return true; 4010 case 'a': // eax. 4011 case 'b': // ebx. 4012 case 'c': // ecx. 4013 case 'd': // edx. 4014 case 'S': // esi. 4015 case 'D': // edi. 4016 case 'A': // edx:eax. 4017 case 't': // Top of floating point stack. 4018 case 'u': // Second from top of floating point stack. 4019 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4020 case 'y': // Any MMX register. 4021 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4022 case 'x': // Any SSE register. 4023 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4024 // for intermideate k reg operations). 4025 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4026 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4027 case 'l': // "Index" registers: any general register that can be used as an 4028 // index in a base+index memory access. 4029 Info.setAllowsRegister(); 4030 return true; 4031 // Floating point constant constraints. 4032 case 'C': // SSE floating point constant. 4033 case 'G': // x87 floating point constant. 4034 return true; 4035 } 4036 } 4037 4038 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4039 unsigned Size) const { 4040 // Strip off constraint modifiers. 4041 while (Constraint[0] == '=' || 4042 Constraint[0] == '+' || 4043 Constraint[0] == '&') 4044 Constraint = Constraint.substr(1); 4045 4046 return validateOperandSize(Constraint, Size); 4047 } 4048 4049 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4050 unsigned Size) const { 4051 return validateOperandSize(Constraint, Size); 4052 } 4053 4054 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4055 unsigned Size) const { 4056 switch (Constraint[0]) { 4057 default: break; 4058 case 'k': 4059 // Registers k0-k7 (AVX512) size limit is 64 bit. 4060 case 'y': 4061 return Size <= 64; 4062 case 'f': 4063 case 't': 4064 case 'u': 4065 return Size <= 128; 4066 case 'v': 4067 case 'x': 4068 if (SSELevel >= AVX512F) 4069 // 512-bit zmm registers can be used if target supports AVX512F. 4070 return Size <= 512U; 4071 else if (SSELevel >= AVX) 4072 // 256-bit ymm registers can be used if target supports AVX. 4073 return Size <= 256U; 4074 return Size <= 128U; 4075 case 'Y': 4076 // 'Y' is the first character for several 2-character constraints. 4077 switch (Constraint[1]) { 4078 default: break; 4079 case 'm': 4080 // 'Ym' is synonymous with 'y'. 4081 case 'k': 4082 return Size <= 64; 4083 case 'i': 4084 case 't': 4085 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4086 if (SSELevel >= AVX512F) 4087 return Size <= 512U; 4088 else if (SSELevel >= AVX) 4089 return Size <= 256U; 4090 return SSELevel >= SSE2 && Size <= 128U; 4091 } 4092 4093 } 4094 4095 return true; 4096 } 4097 4098 std::string 4099 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4100 switch (*Constraint) { 4101 case 'a': return std::string("{ax}"); 4102 case 'b': return std::string("{bx}"); 4103 case 'c': return std::string("{cx}"); 4104 case 'd': return std::string("{dx}"); 4105 case 'S': return std::string("{si}"); 4106 case 'D': return std::string("{di}"); 4107 case 'p': // address 4108 return std::string("im"); 4109 case 't': // top of floating point stack. 4110 return std::string("{st}"); 4111 case 'u': // second from top of floating point stack. 4112 return std::string("{st(1)}"); // second from top of floating point stack. 4113 case 'Y': 4114 switch (Constraint[1]) { 4115 default: 4116 // Break from inner switch and fall through (copy single char), 4117 // continue parsing after copying the current constraint into 4118 // the return string. 4119 break; 4120 case 'k': 4121 // "^" hints llvm that this is a 2 letter constraint. 4122 // "Constraint++" is used to promote the string iterator 4123 // to the next constraint. 4124 return std::string("^") + std::string(Constraint++, 2); 4125 } 4126 LLVM_FALLTHROUGH; 4127 default: 4128 return std::string(1, *Constraint); 4129 } 4130 } 4131 4132 // X86-32 generic target 4133 class X86_32TargetInfo : public X86TargetInfo { 4134 public: 4135 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4136 : X86TargetInfo(Triple, Opts) { 4137 DoubleAlign = LongLongAlign = 32; 4138 LongDoubleWidth = 96; 4139 LongDoubleAlign = 32; 4140 SuitableAlign = 128; 4141 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4142 SizeType = UnsignedInt; 4143 PtrDiffType = SignedInt; 4144 IntPtrType = SignedInt; 4145 RegParmMax = 3; 4146 4147 // Use fpret for all types. 4148 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4149 (1 << TargetInfo::Double) | 4150 (1 << TargetInfo::LongDouble)); 4151 4152 // x86-32 has atomics up to 8 bytes 4153 // FIXME: Check that we actually have cmpxchg8b before setting 4154 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4155 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4156 } 4157 BuiltinVaListKind getBuiltinVaListKind() const override { 4158 return TargetInfo::CharPtrBuiltinVaList; 4159 } 4160 4161 int getEHDataRegisterNumber(unsigned RegNo) const override { 4162 if (RegNo == 0) return 0; 4163 if (RegNo == 1) return 2; 4164 return -1; 4165 } 4166 bool validateOperandSize(StringRef Constraint, 4167 unsigned Size) const override { 4168 switch (Constraint[0]) { 4169 default: break; 4170 case 'R': 4171 case 'q': 4172 case 'Q': 4173 case 'a': 4174 case 'b': 4175 case 'c': 4176 case 'd': 4177 case 'S': 4178 case 'D': 4179 return Size <= 32; 4180 case 'A': 4181 return Size <= 64; 4182 } 4183 4184 return X86TargetInfo::validateOperandSize(Constraint, Size); 4185 } 4186 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4187 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4188 Builtin::FirstTSBuiltin + 1); 4189 } 4190 }; 4191 4192 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4193 public: 4194 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4195 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4196 4197 unsigned getFloatEvalMethod() const override { 4198 unsigned Major, Minor, Micro; 4199 getTriple().getOSVersion(Major, Minor, Micro); 4200 // New NetBSD uses the default rounding mode. 4201 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4202 return X86_32TargetInfo::getFloatEvalMethod(); 4203 // NetBSD before 6.99.26 defaults to "double" rounding. 4204 return 1; 4205 } 4206 }; 4207 4208 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4209 public: 4210 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4211 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4212 SizeType = UnsignedLong; 4213 IntPtrType = SignedLong; 4214 PtrDiffType = SignedLong; 4215 } 4216 }; 4217 4218 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4219 public: 4220 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4221 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4222 SizeType = UnsignedLong; 4223 IntPtrType = SignedLong; 4224 PtrDiffType = SignedLong; 4225 } 4226 }; 4227 4228 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4229 public: 4230 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4231 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4232 LongDoubleWidth = 128; 4233 LongDoubleAlign = 128; 4234 SuitableAlign = 128; 4235 MaxVectorAlign = 256; 4236 // The watchOS simulator uses the builtin bool type for Objective-C. 4237 llvm::Triple T = llvm::Triple(Triple); 4238 if (T.isWatchOS()) 4239 UseSignedCharForObjCBool = false; 4240 SizeType = UnsignedLong; 4241 IntPtrType = SignedLong; 4242 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4243 HasAlignMac68kSupport = true; 4244 } 4245 4246 bool handleTargetFeatures(std::vector<std::string> &Features, 4247 DiagnosticsEngine &Diags) override { 4248 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4249 Diags)) 4250 return false; 4251 // We now know the features we have: we can decide how to align vectors. 4252 MaxVectorAlign = 4253 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4254 return true; 4255 } 4256 }; 4257 4258 // x86-32 Windows target 4259 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4260 public: 4261 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4262 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4263 WCharType = UnsignedShort; 4264 DoubleAlign = LongLongAlign = 64; 4265 bool IsWinCOFF = 4266 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4267 resetDataLayout(IsWinCOFF 4268 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4269 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4270 } 4271 void getTargetDefines(const LangOptions &Opts, 4272 MacroBuilder &Builder) const override { 4273 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4274 } 4275 }; 4276 4277 // x86-32 Windows Visual Studio target 4278 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4279 public: 4280 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4281 const TargetOptions &Opts) 4282 : WindowsX86_32TargetInfo(Triple, Opts) { 4283 LongDoubleWidth = LongDoubleAlign = 64; 4284 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4285 } 4286 void getTargetDefines(const LangOptions &Opts, 4287 MacroBuilder &Builder) const override { 4288 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4289 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4290 // The value of the following reflects processor type. 4291 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4292 // We lost the original triple, so we use the default. 4293 Builder.defineMacro("_M_IX86", "600"); 4294 } 4295 }; 4296 4297 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4298 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4299 // supports __declspec natively under -fms-extensions, but we define a no-op 4300 // __declspec macro anyway for pre-processor compatibility. 4301 if (Opts.MicrosoftExt) 4302 Builder.defineMacro("__declspec", "__declspec"); 4303 else 4304 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4305 4306 if (!Opts.MicrosoftExt) { 4307 // Provide macros for all the calling convention keywords. Provide both 4308 // single and double underscore prefixed variants. These are available on 4309 // x64 as well as x86, even though they have no effect. 4310 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4311 for (const char *CC : CCs) { 4312 std::string GCCSpelling = "__attribute__((__"; 4313 GCCSpelling += CC; 4314 GCCSpelling += "__))"; 4315 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4316 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4317 } 4318 } 4319 } 4320 4321 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4322 Builder.defineMacro("__MSVCRT__"); 4323 Builder.defineMacro("__MINGW32__"); 4324 addCygMingDefines(Opts, Builder); 4325 } 4326 4327 // x86-32 MinGW target 4328 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4329 public: 4330 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4331 : WindowsX86_32TargetInfo(Triple, Opts) {} 4332 void getTargetDefines(const LangOptions &Opts, 4333 MacroBuilder &Builder) const override { 4334 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4335 DefineStd(Builder, "WIN32", Opts); 4336 DefineStd(Builder, "WINNT", Opts); 4337 Builder.defineMacro("_X86_"); 4338 addMinGWDefines(Opts, Builder); 4339 } 4340 }; 4341 4342 // x86-32 Cygwin target 4343 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4344 public: 4345 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4346 : X86_32TargetInfo(Triple, Opts) { 4347 WCharType = UnsignedShort; 4348 DoubleAlign = LongLongAlign = 64; 4349 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4350 } 4351 void getTargetDefines(const LangOptions &Opts, 4352 MacroBuilder &Builder) const override { 4353 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4354 Builder.defineMacro("_X86_"); 4355 Builder.defineMacro("__CYGWIN__"); 4356 Builder.defineMacro("__CYGWIN32__"); 4357 addCygMingDefines(Opts, Builder); 4358 DefineStd(Builder, "unix", Opts); 4359 if (Opts.CPlusPlus) 4360 Builder.defineMacro("_GNU_SOURCE"); 4361 } 4362 }; 4363 4364 // x86-32 Haiku target 4365 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4366 public: 4367 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4368 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4369 } 4370 void getTargetDefines(const LangOptions &Opts, 4371 MacroBuilder &Builder) const override { 4372 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4373 Builder.defineMacro("__INTEL__"); 4374 } 4375 }; 4376 4377 // X86-32 MCU target 4378 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4379 public: 4380 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4381 : X86_32TargetInfo(Triple, Opts) { 4382 LongDoubleWidth = 64; 4383 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4384 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4385 WIntType = UnsignedInt; 4386 } 4387 4388 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4389 // On MCU we support only C calling convention. 4390 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4391 } 4392 4393 void getTargetDefines(const LangOptions &Opts, 4394 MacroBuilder &Builder) const override { 4395 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4396 Builder.defineMacro("__iamcu"); 4397 Builder.defineMacro("__iamcu__"); 4398 } 4399 4400 bool allowsLargerPreferedTypeAlignment() const override { 4401 return false; 4402 } 4403 }; 4404 4405 // RTEMS Target 4406 template<typename Target> 4407 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4408 protected: 4409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4410 MacroBuilder &Builder) const override { 4411 // RTEMS defines; list based off of gcc output 4412 4413 Builder.defineMacro("__rtems__"); 4414 Builder.defineMacro("__ELF__"); 4415 } 4416 4417 public: 4418 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4419 : OSTargetInfo<Target>(Triple, Opts) { 4420 switch (Triple.getArch()) { 4421 default: 4422 case llvm::Triple::x86: 4423 // this->MCountName = ".mcount"; 4424 break; 4425 case llvm::Triple::mips: 4426 case llvm::Triple::mipsel: 4427 case llvm::Triple::ppc: 4428 case llvm::Triple::ppc64: 4429 case llvm::Triple::ppc64le: 4430 // this->MCountName = "_mcount"; 4431 break; 4432 case llvm::Triple::arm: 4433 // this->MCountName = "__mcount"; 4434 break; 4435 } 4436 } 4437 }; 4438 4439 // x86-32 RTEMS target 4440 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4441 public: 4442 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4443 : X86_32TargetInfo(Triple, Opts) { 4444 SizeType = UnsignedLong; 4445 IntPtrType = SignedLong; 4446 PtrDiffType = SignedLong; 4447 } 4448 void getTargetDefines(const LangOptions &Opts, 4449 MacroBuilder &Builder) const override { 4450 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4451 Builder.defineMacro("__INTEL__"); 4452 Builder.defineMacro("__rtems__"); 4453 } 4454 }; 4455 4456 // x86-64 generic target 4457 class X86_64TargetInfo : public X86TargetInfo { 4458 public: 4459 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4460 : X86TargetInfo(Triple, Opts) { 4461 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4462 bool IsWinCOFF = 4463 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4464 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4465 LongDoubleWidth = 128; 4466 LongDoubleAlign = 128; 4467 LargeArrayMinWidth = 128; 4468 LargeArrayAlign = 128; 4469 SuitableAlign = 128; 4470 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4471 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4472 IntPtrType = IsX32 ? SignedInt : SignedLong; 4473 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4474 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4475 RegParmMax = 6; 4476 4477 // Pointers are 32-bit in x32. 4478 resetDataLayout(IsX32 4479 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4480 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4481 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4482 4483 // Use fpret only for long double. 4484 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4485 4486 // Use fp2ret for _Complex long double. 4487 ComplexLongDoubleUsesFP2Ret = true; 4488 4489 // Make __builtin_ms_va_list available. 4490 HasBuiltinMSVaList = true; 4491 4492 // x86-64 has atomics up to 16 bytes. 4493 MaxAtomicPromoteWidth = 128; 4494 MaxAtomicInlineWidth = 128; 4495 } 4496 BuiltinVaListKind getBuiltinVaListKind() const override { 4497 return TargetInfo::X86_64ABIBuiltinVaList; 4498 } 4499 4500 int getEHDataRegisterNumber(unsigned RegNo) const override { 4501 if (RegNo == 0) return 0; 4502 if (RegNo == 1) return 1; 4503 return -1; 4504 } 4505 4506 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4507 switch (CC) { 4508 case CC_C: 4509 case CC_Swift: 4510 case CC_X86VectorCall: 4511 case CC_IntelOclBicc: 4512 case CC_X86_64Win64: 4513 case CC_PreserveMost: 4514 case CC_PreserveAll: 4515 return CCCR_OK; 4516 default: 4517 return CCCR_Warning; 4518 } 4519 } 4520 4521 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4522 return CC_C; 4523 } 4524 4525 // for x32 we need it here explicitly 4526 bool hasInt128Type() const override { return true; } 4527 unsigned getUnwindWordWidth() const override { return 64; } 4528 unsigned getRegisterWidth() const override { return 64; } 4529 4530 bool validateGlobalRegisterVariable(StringRef RegName, 4531 unsigned RegSize, 4532 bool &HasSizeMismatch) const override { 4533 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4534 // handle. 4535 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4536 // Check that the register size is 64-bit. 4537 HasSizeMismatch = RegSize != 64; 4538 return true; 4539 } 4540 4541 // Check if the register is a 32-bit register the backend can handle. 4542 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4543 HasSizeMismatch); 4544 } 4545 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4546 return llvm::makeArrayRef(BuiltinInfoX86, 4547 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4548 } 4549 }; 4550 4551 // x86-64 Windows target 4552 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4553 public: 4554 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4555 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4556 WCharType = UnsignedShort; 4557 LongWidth = LongAlign = 32; 4558 DoubleAlign = LongLongAlign = 64; 4559 IntMaxType = SignedLongLong; 4560 Int64Type = SignedLongLong; 4561 SizeType = UnsignedLongLong; 4562 PtrDiffType = SignedLongLong; 4563 IntPtrType = SignedLongLong; 4564 } 4565 4566 void getTargetDefines(const LangOptions &Opts, 4567 MacroBuilder &Builder) const override { 4568 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4569 Builder.defineMacro("_WIN64"); 4570 } 4571 4572 BuiltinVaListKind getBuiltinVaListKind() const override { 4573 return TargetInfo::CharPtrBuiltinVaList; 4574 } 4575 4576 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4577 switch (CC) { 4578 case CC_X86StdCall: 4579 case CC_X86ThisCall: 4580 case CC_X86FastCall: 4581 return CCCR_Ignore; 4582 case CC_C: 4583 case CC_X86VectorCall: 4584 case CC_IntelOclBicc: 4585 case CC_X86_64SysV: 4586 case CC_Swift: 4587 return CCCR_OK; 4588 default: 4589 return CCCR_Warning; 4590 } 4591 } 4592 }; 4593 4594 // x86-64 Windows Visual Studio target 4595 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4596 public: 4597 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4598 const TargetOptions &Opts) 4599 : WindowsX86_64TargetInfo(Triple, Opts) { 4600 LongDoubleWidth = LongDoubleAlign = 64; 4601 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4602 } 4603 void getTargetDefines(const LangOptions &Opts, 4604 MacroBuilder &Builder) const override { 4605 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4606 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4607 Builder.defineMacro("_M_X64", "100"); 4608 Builder.defineMacro("_M_AMD64", "100"); 4609 } 4610 }; 4611 4612 // x86-64 MinGW target 4613 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4614 public: 4615 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4616 : WindowsX86_64TargetInfo(Triple, Opts) { 4617 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4618 // with x86 FP ops. Weird. 4619 LongDoubleWidth = LongDoubleAlign = 128; 4620 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4621 } 4622 4623 void getTargetDefines(const LangOptions &Opts, 4624 MacroBuilder &Builder) const override { 4625 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4626 DefineStd(Builder, "WIN64", Opts); 4627 Builder.defineMacro("__MINGW64__"); 4628 addMinGWDefines(Opts, Builder); 4629 4630 // GCC defines this macro when it is using __gxx_personality_seh0. 4631 if (!Opts.SjLjExceptions) 4632 Builder.defineMacro("__SEH__"); 4633 } 4634 }; 4635 4636 // x86-64 Cygwin target 4637 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4638 public: 4639 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4640 : X86_64TargetInfo(Triple, Opts) { 4641 TLSSupported = false; 4642 WCharType = UnsignedShort; 4643 } 4644 void getTargetDefines(const LangOptions &Opts, 4645 MacroBuilder &Builder) const override { 4646 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4647 Builder.defineMacro("__x86_64__"); 4648 Builder.defineMacro("__CYGWIN__"); 4649 Builder.defineMacro("__CYGWIN64__"); 4650 addCygMingDefines(Opts, Builder); 4651 DefineStd(Builder, "unix", Opts); 4652 if (Opts.CPlusPlus) 4653 Builder.defineMacro("_GNU_SOURCE"); 4654 4655 // GCC defines this macro when it is using __gxx_personality_seh0. 4656 if (!Opts.SjLjExceptions) 4657 Builder.defineMacro("__SEH__"); 4658 } 4659 }; 4660 4661 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4662 public: 4663 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4664 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4665 Int64Type = SignedLongLong; 4666 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4667 llvm::Triple T = llvm::Triple(Triple); 4668 if (T.isiOS()) 4669 UseSignedCharForObjCBool = false; 4670 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4671 } 4672 4673 bool handleTargetFeatures(std::vector<std::string> &Features, 4674 DiagnosticsEngine &Diags) override { 4675 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4676 Diags)) 4677 return false; 4678 // We now know the features we have: we can decide how to align vectors. 4679 MaxVectorAlign = 4680 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4681 return true; 4682 } 4683 }; 4684 4685 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4686 public: 4687 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4688 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4689 IntMaxType = SignedLongLong; 4690 Int64Type = SignedLongLong; 4691 } 4692 }; 4693 4694 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4695 public: 4696 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4697 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4698 IntMaxType = SignedLongLong; 4699 Int64Type = SignedLongLong; 4700 } 4701 }; 4702 4703 class ARMTargetInfo : public TargetInfo { 4704 // Possible FPU choices. 4705 enum FPUMode { 4706 VFP2FPU = (1 << 0), 4707 VFP3FPU = (1 << 1), 4708 VFP4FPU = (1 << 2), 4709 NeonFPU = (1 << 3), 4710 FPARMV8 = (1 << 4) 4711 }; 4712 4713 // Possible HWDiv features. 4714 enum HWDivMode { 4715 HWDivThumb = (1 << 0), 4716 HWDivARM = (1 << 1) 4717 }; 4718 4719 static bool FPUModeIsVFP(FPUMode Mode) { 4720 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4721 } 4722 4723 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4724 static const char * const GCCRegNames[]; 4725 4726 std::string ABI, CPU; 4727 4728 StringRef CPUProfile; 4729 StringRef CPUAttr; 4730 4731 enum { 4732 FP_Default, 4733 FP_VFP, 4734 FP_Neon 4735 } FPMath; 4736 4737 unsigned ArchISA; 4738 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4739 unsigned ArchProfile; 4740 unsigned ArchVersion; 4741 4742 unsigned FPU : 5; 4743 4744 unsigned IsAAPCS : 1; 4745 unsigned HWDiv : 2; 4746 4747 // Initialized via features. 4748 unsigned SoftFloat : 1; 4749 unsigned SoftFloatABI : 1; 4750 4751 unsigned CRC : 1; 4752 unsigned Crypto : 1; 4753 unsigned DSP : 1; 4754 unsigned Unaligned : 1; 4755 4756 enum { 4757 LDREX_B = (1 << 0), /// byte (8-bit) 4758 LDREX_H = (1 << 1), /// half (16-bit) 4759 LDREX_W = (1 << 2), /// word (32-bit) 4760 LDREX_D = (1 << 3), /// double (64-bit) 4761 }; 4762 4763 uint32_t LDREX; 4764 4765 // ACLE 6.5.1 Hardware floating point 4766 enum { 4767 HW_FP_HP = (1 << 1), /// half (16-bit) 4768 HW_FP_SP = (1 << 2), /// single (32-bit) 4769 HW_FP_DP = (1 << 3), /// double (64-bit) 4770 }; 4771 uint32_t HW_FP; 4772 4773 static const Builtin::Info BuiltinInfo[]; 4774 4775 void setABIAAPCS() { 4776 IsAAPCS = true; 4777 4778 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4779 const llvm::Triple &T = getTriple(); 4780 4781 // size_t is unsigned long on MachO-derived environments, NetBSD, 4782 // OpenBSD and Bitrig. 4783 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4784 T.getOS() == llvm::Triple::OpenBSD || 4785 T.getOS() == llvm::Triple::Bitrig) 4786 SizeType = UnsignedLong; 4787 else 4788 SizeType = UnsignedInt; 4789 4790 switch (T.getOS()) { 4791 case llvm::Triple::NetBSD: 4792 case llvm::Triple::OpenBSD: 4793 WCharType = SignedInt; 4794 break; 4795 case llvm::Triple::Win32: 4796 WCharType = UnsignedShort; 4797 break; 4798 case llvm::Triple::Linux: 4799 default: 4800 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4801 WCharType = UnsignedInt; 4802 break; 4803 } 4804 4805 UseBitFieldTypeAlignment = true; 4806 4807 ZeroLengthBitfieldBoundary = 0; 4808 4809 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4810 // so set preferred for small types to 32. 4811 if (T.isOSBinFormatMachO()) { 4812 resetDataLayout(BigEndian 4813 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4814 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4815 } else if (T.isOSWindows()) { 4816 assert(!BigEndian && "Windows on ARM does not support big endian"); 4817 resetDataLayout("e" 4818 "-m:w" 4819 "-p:32:32" 4820 "-i64:64" 4821 "-v128:64:128" 4822 "-a:0:32" 4823 "-n32" 4824 "-S64"); 4825 } else if (T.isOSNaCl()) { 4826 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4827 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4828 } else { 4829 resetDataLayout(BigEndian 4830 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4831 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4832 } 4833 4834 // FIXME: Enumerated types are variable width in straight AAPCS. 4835 } 4836 4837 void setABIAPCS(bool IsAAPCS16) { 4838 const llvm::Triple &T = getTriple(); 4839 4840 IsAAPCS = false; 4841 4842 if (IsAAPCS16) 4843 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4844 else 4845 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4846 4847 // size_t is unsigned int on FreeBSD. 4848 if (T.getOS() == llvm::Triple::FreeBSD) 4849 SizeType = UnsignedInt; 4850 else 4851 SizeType = UnsignedLong; 4852 4853 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4854 WCharType = SignedInt; 4855 4856 // Do not respect the alignment of bit-field types when laying out 4857 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4858 UseBitFieldTypeAlignment = false; 4859 4860 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4861 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4862 /// gcc. 4863 ZeroLengthBitfieldBoundary = 32; 4864 4865 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4866 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4867 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4868 } else if (T.isOSBinFormatMachO()) 4869 resetDataLayout( 4870 BigEndian 4871 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4872 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4873 else 4874 resetDataLayout( 4875 BigEndian 4876 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4877 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4878 4879 // FIXME: Override "preferred align" for double and long long. 4880 } 4881 4882 void setArchInfo() { 4883 StringRef ArchName = getTriple().getArchName(); 4884 4885 ArchISA = llvm::ARM::parseArchISA(ArchName); 4886 CPU = llvm::ARM::getDefaultCPU(ArchName); 4887 unsigned AK = llvm::ARM::parseArch(ArchName); 4888 if (AK != llvm::ARM::AK_INVALID) 4889 ArchKind = AK; 4890 setArchInfo(ArchKind); 4891 } 4892 4893 void setArchInfo(unsigned Kind) { 4894 StringRef SubArch; 4895 4896 // cache TargetParser info 4897 ArchKind = Kind; 4898 SubArch = llvm::ARM::getSubArch(ArchKind); 4899 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4900 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4901 4902 // cache CPU related strings 4903 CPUAttr = getCPUAttr(); 4904 CPUProfile = getCPUProfile(); 4905 } 4906 4907 void setAtomic() { 4908 // when triple does not specify a sub arch, 4909 // then we are not using inline atomics 4910 bool ShouldUseInlineAtomic = 4911 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4912 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4913 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4914 if (ArchProfile == llvm::ARM::PK_M) { 4915 MaxAtomicPromoteWidth = 32; 4916 if (ShouldUseInlineAtomic) 4917 MaxAtomicInlineWidth = 32; 4918 } 4919 else { 4920 MaxAtomicPromoteWidth = 64; 4921 if (ShouldUseInlineAtomic) 4922 MaxAtomicInlineWidth = 64; 4923 } 4924 } 4925 4926 bool isThumb() const { 4927 return (ArchISA == llvm::ARM::IK_THUMB); 4928 } 4929 4930 bool supportsThumb() const { 4931 return CPUAttr.count('T') || ArchVersion >= 6; 4932 } 4933 4934 bool supportsThumb2() const { 4935 return CPUAttr.equals("6T2") || 4936 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4937 } 4938 4939 StringRef getCPUAttr() const { 4940 // For most sub-arches, the build attribute CPU name is enough. 4941 // For Cortex variants, it's slightly different. 4942 switch(ArchKind) { 4943 default: 4944 return llvm::ARM::getCPUAttr(ArchKind); 4945 case llvm::ARM::AK_ARMV6M: 4946 return "6M"; 4947 case llvm::ARM::AK_ARMV7S: 4948 return "7S"; 4949 case llvm::ARM::AK_ARMV7A: 4950 return "7A"; 4951 case llvm::ARM::AK_ARMV7R: 4952 return "7R"; 4953 case llvm::ARM::AK_ARMV7M: 4954 return "7M"; 4955 case llvm::ARM::AK_ARMV7EM: 4956 return "7EM"; 4957 case llvm::ARM::AK_ARMV8A: 4958 return "8A"; 4959 case llvm::ARM::AK_ARMV8_1A: 4960 return "8_1A"; 4961 case llvm::ARM::AK_ARMV8_2A: 4962 return "8_2A"; 4963 case llvm::ARM::AK_ARMV8MBaseline: 4964 return "8M_BASE"; 4965 case llvm::ARM::AK_ARMV8MMainline: 4966 return "8M_MAIN"; 4967 case llvm::ARM::AK_ARMV8R: 4968 return "8R"; 4969 } 4970 } 4971 4972 StringRef getCPUProfile() const { 4973 switch(ArchProfile) { 4974 case llvm::ARM::PK_A: 4975 return "A"; 4976 case llvm::ARM::PK_R: 4977 return "R"; 4978 case llvm::ARM::PK_M: 4979 return "M"; 4980 default: 4981 return ""; 4982 } 4983 } 4984 4985 public: 4986 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4987 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4988 HW_FP(0) { 4989 4990 switch (getTriple().getOS()) { 4991 case llvm::Triple::NetBSD: 4992 case llvm::Triple::OpenBSD: 4993 PtrDiffType = SignedLong; 4994 break; 4995 default: 4996 PtrDiffType = SignedInt; 4997 break; 4998 } 4999 5000 // Cache arch related info. 5001 setArchInfo(); 5002 5003 // {} in inline assembly are neon specifiers, not assembly variant 5004 // specifiers. 5005 NoAsmVariants = true; 5006 5007 // FIXME: This duplicates code from the driver that sets the -target-abi 5008 // option - this code is used if -target-abi isn't passed and should 5009 // be unified in some way. 5010 if (Triple.isOSBinFormatMachO()) { 5011 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5012 // the frontend matches that. 5013 if (Triple.getEnvironment() == llvm::Triple::EABI || 5014 Triple.getOS() == llvm::Triple::UnknownOS || 5015 ArchProfile == llvm::ARM::PK_M) { 5016 setABI("aapcs"); 5017 } else if (Triple.isWatchABI()) { 5018 setABI("aapcs16"); 5019 } else { 5020 setABI("apcs-gnu"); 5021 } 5022 } else if (Triple.isOSWindows()) { 5023 // FIXME: this is invalid for WindowsCE 5024 setABI("aapcs"); 5025 } else { 5026 // Select the default based on the platform. 5027 switch (Triple.getEnvironment()) { 5028 case llvm::Triple::Android: 5029 case llvm::Triple::GNUEABI: 5030 case llvm::Triple::GNUEABIHF: 5031 case llvm::Triple::MuslEABI: 5032 case llvm::Triple::MuslEABIHF: 5033 setABI("aapcs-linux"); 5034 break; 5035 case llvm::Triple::EABIHF: 5036 case llvm::Triple::EABI: 5037 setABI("aapcs"); 5038 break; 5039 case llvm::Triple::GNU: 5040 setABI("apcs-gnu"); 5041 break; 5042 default: 5043 if (Triple.getOS() == llvm::Triple::NetBSD) 5044 setABI("apcs-gnu"); 5045 else 5046 setABI("aapcs"); 5047 break; 5048 } 5049 } 5050 5051 // ARM targets default to using the ARM C++ ABI. 5052 TheCXXABI.set(TargetCXXABI::GenericARM); 5053 5054 // ARM has atomics up to 8 bytes 5055 setAtomic(); 5056 5057 // Do force alignment of members that follow zero length bitfields. If 5058 // the alignment of the zero-length bitfield is greater than the member 5059 // that follows it, `bar', `bar' will be aligned as the type of the 5060 // zero length bitfield. 5061 UseZeroLengthBitfieldAlignment = true; 5062 5063 if (Triple.getOS() == llvm::Triple::Linux || 5064 Triple.getOS() == llvm::Triple::UnknownOS) 5065 this->MCountName = 5066 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5067 } 5068 5069 StringRef getABI() const override { return ABI; } 5070 5071 bool setABI(const std::string &Name) override { 5072 ABI = Name; 5073 5074 // The defaults (above) are for AAPCS, check if we need to change them. 5075 // 5076 // FIXME: We need support for -meabi... we could just mangle it into the 5077 // name. 5078 if (Name == "apcs-gnu" || Name == "aapcs16") { 5079 setABIAPCS(Name == "aapcs16"); 5080 return true; 5081 } 5082 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5083 setABIAAPCS(); 5084 return true; 5085 } 5086 return false; 5087 } 5088 5089 // FIXME: This should be based on Arch attributes, not CPU names. 5090 bool 5091 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5092 StringRef CPU, 5093 const std::vector<std::string> &FeaturesVec) const override { 5094 5095 std::vector<StringRef> TargetFeatures; 5096 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5097 5098 // get default FPU features 5099 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5100 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5101 5102 // get default Extension features 5103 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5104 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5105 5106 for (auto Feature : TargetFeatures) 5107 if (Feature[0] == '+') 5108 Features[Feature.drop_front(1)] = true; 5109 5110 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5111 } 5112 5113 bool handleTargetFeatures(std::vector<std::string> &Features, 5114 DiagnosticsEngine &Diags) override { 5115 FPU = 0; 5116 CRC = 0; 5117 Crypto = 0; 5118 DSP = 0; 5119 Unaligned = 1; 5120 SoftFloat = SoftFloatABI = false; 5121 HWDiv = 0; 5122 5123 // This does not diagnose illegal cases like having both 5124 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5125 uint32_t HW_FP_remove = 0; 5126 for (const auto &Feature : Features) { 5127 if (Feature == "+soft-float") { 5128 SoftFloat = true; 5129 } else if (Feature == "+soft-float-abi") { 5130 SoftFloatABI = true; 5131 } else if (Feature == "+vfp2") { 5132 FPU |= VFP2FPU; 5133 HW_FP |= HW_FP_SP | HW_FP_DP; 5134 } else if (Feature == "+vfp3") { 5135 FPU |= VFP3FPU; 5136 HW_FP |= HW_FP_SP | HW_FP_DP; 5137 } else if (Feature == "+vfp4") { 5138 FPU |= VFP4FPU; 5139 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5140 } else if (Feature == "+fp-armv8") { 5141 FPU |= FPARMV8; 5142 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5143 } else if (Feature == "+neon") { 5144 FPU |= NeonFPU; 5145 HW_FP |= HW_FP_SP | HW_FP_DP; 5146 } else if (Feature == "+hwdiv") { 5147 HWDiv |= HWDivThumb; 5148 } else if (Feature == "+hwdiv-arm") { 5149 HWDiv |= HWDivARM; 5150 } else if (Feature == "+crc") { 5151 CRC = 1; 5152 } else if (Feature == "+crypto") { 5153 Crypto = 1; 5154 } else if (Feature == "+dsp") { 5155 DSP = 1; 5156 } else if (Feature == "+fp-only-sp") { 5157 HW_FP_remove |= HW_FP_DP; 5158 } else if (Feature == "+strict-align") { 5159 Unaligned = 0; 5160 } else if (Feature == "+fp16") { 5161 HW_FP |= HW_FP_HP; 5162 } 5163 } 5164 HW_FP &= ~HW_FP_remove; 5165 5166 switch (ArchVersion) { 5167 case 6: 5168 if (ArchProfile == llvm::ARM::PK_M) 5169 LDREX = 0; 5170 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5171 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5172 else 5173 LDREX = LDREX_W; 5174 break; 5175 case 7: 5176 if (ArchProfile == llvm::ARM::PK_M) 5177 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5178 else 5179 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5180 break; 5181 case 8: 5182 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5183 } 5184 5185 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5186 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5187 return false; 5188 } 5189 5190 if (FPMath == FP_Neon) 5191 Features.push_back("+neonfp"); 5192 else if (FPMath == FP_VFP) 5193 Features.push_back("-neonfp"); 5194 5195 // Remove front-end specific options which the backend handles differently. 5196 auto Feature = 5197 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5198 if (Feature != Features.end()) 5199 Features.erase(Feature); 5200 5201 return true; 5202 } 5203 5204 bool hasFeature(StringRef Feature) const override { 5205 return llvm::StringSwitch<bool>(Feature) 5206 .Case("arm", true) 5207 .Case("aarch32", true) 5208 .Case("softfloat", SoftFloat) 5209 .Case("thumb", isThumb()) 5210 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5211 .Case("hwdiv", HWDiv & HWDivThumb) 5212 .Case("hwdiv-arm", HWDiv & HWDivARM) 5213 .Default(false); 5214 } 5215 5216 bool setCPU(const std::string &Name) override { 5217 if (Name != "generic") 5218 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5219 5220 if (ArchKind == llvm::ARM::AK_INVALID) 5221 return false; 5222 setAtomic(); 5223 CPU = Name; 5224 return true; 5225 } 5226 5227 bool setFPMath(StringRef Name) override; 5228 5229 void getTargetDefines(const LangOptions &Opts, 5230 MacroBuilder &Builder) const override { 5231 // Target identification. 5232 Builder.defineMacro("__arm"); 5233 Builder.defineMacro("__arm__"); 5234 // For bare-metal none-eabi. 5235 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5236 getTriple().getEnvironment() == llvm::Triple::EABI) 5237 Builder.defineMacro("__ELF__"); 5238 5239 // Target properties. 5240 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5241 5242 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5243 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5244 if (getTriple().isWatchABI()) 5245 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5246 5247 if (!CPUAttr.empty()) 5248 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5249 5250 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5251 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5252 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5253 5254 if (ArchVersion >= 8) { 5255 // ACLE 6.5.7 Crypto Extension 5256 if (Crypto) 5257 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5258 // ACLE 6.5.8 CRC32 Extension 5259 if (CRC) 5260 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5261 // ACLE 6.5.10 Numeric Maximum and Minimum 5262 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5263 // ACLE 6.5.9 Directed Rounding 5264 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5265 } 5266 5267 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5268 // is not defined for the M-profile. 5269 // NOTE that the default profile is assumed to be 'A' 5270 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5271 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5272 5273 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5274 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5275 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5276 // v7 and v8 architectures excluding v8-M Baseline. 5277 if (supportsThumb2()) 5278 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5279 else if (supportsThumb()) 5280 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5281 5282 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5283 // instruction set such as ARM or Thumb. 5284 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5285 5286 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5287 5288 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5289 if (!CPUProfile.empty()) 5290 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5291 5292 // ACLE 6.4.3 Unaligned access supported in hardware 5293 if (Unaligned) 5294 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5295 5296 // ACLE 6.4.4 LDREX/STREX 5297 if (LDREX) 5298 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5299 5300 // ACLE 6.4.5 CLZ 5301 if (ArchVersion == 5 || 5302 (ArchVersion == 6 && CPUProfile != "M") || 5303 ArchVersion > 6) 5304 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5305 5306 // ACLE 6.5.1 Hardware Floating Point 5307 if (HW_FP) 5308 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5309 5310 // ACLE predefines. 5311 Builder.defineMacro("__ARM_ACLE", "200"); 5312 5313 // FP16 support (we currently only support IEEE format). 5314 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5315 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5316 5317 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5318 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5319 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5320 5321 // Subtarget options. 5322 5323 // FIXME: It's more complicated than this and we don't really support 5324 // interworking. 5325 // Windows on ARM does not "support" interworking 5326 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5327 Builder.defineMacro("__THUMB_INTERWORK__"); 5328 5329 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5330 // Embedded targets on Darwin follow AAPCS, but not EABI. 5331 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5332 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5333 Builder.defineMacro("__ARM_EABI__"); 5334 Builder.defineMacro("__ARM_PCS", "1"); 5335 } 5336 5337 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5338 ABI == "aapcs16") 5339 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5340 5341 if (SoftFloat) 5342 Builder.defineMacro("__SOFTFP__"); 5343 5344 if (ArchKind == llvm::ARM::AK_XSCALE) 5345 Builder.defineMacro("__XSCALE__"); 5346 5347 if (isThumb()) { 5348 Builder.defineMacro("__THUMBEL__"); 5349 Builder.defineMacro("__thumb__"); 5350 if (supportsThumb2()) 5351 Builder.defineMacro("__thumb2__"); 5352 } 5353 5354 // ACLE 6.4.9 32-bit SIMD instructions 5355 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5356 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5357 5358 // ACLE 6.4.10 Hardware Integer Divide 5359 if (((HWDiv & HWDivThumb) && isThumb()) || 5360 ((HWDiv & HWDivARM) && !isThumb())) { 5361 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5362 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5363 } 5364 5365 // Note, this is always on in gcc, even though it doesn't make sense. 5366 Builder.defineMacro("__APCS_32__"); 5367 5368 if (FPUModeIsVFP((FPUMode) FPU)) { 5369 Builder.defineMacro("__VFP_FP__"); 5370 if (FPU & VFP2FPU) 5371 Builder.defineMacro("__ARM_VFPV2__"); 5372 if (FPU & VFP3FPU) 5373 Builder.defineMacro("__ARM_VFPV3__"); 5374 if (FPU & VFP4FPU) 5375 Builder.defineMacro("__ARM_VFPV4__"); 5376 } 5377 5378 // This only gets set when Neon instructions are actually available, unlike 5379 // the VFP define, hence the soft float and arch check. This is subtly 5380 // different from gcc, we follow the intent which was that it should be set 5381 // when Neon instructions are actually available. 5382 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5383 Builder.defineMacro("__ARM_NEON", "1"); 5384 Builder.defineMacro("__ARM_NEON__"); 5385 // current AArch32 NEON implementations do not support double-precision 5386 // floating-point even when it is present in VFP. 5387 Builder.defineMacro("__ARM_NEON_FP", 5388 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5389 } 5390 5391 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5392 Opts.ShortWChar ? "2" : "4"); 5393 5394 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5395 Opts.ShortEnums ? "1" : "4"); 5396 5397 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5400 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5401 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5402 } 5403 5404 // ACLE 6.4.7 DSP instructions 5405 if (DSP) { 5406 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5407 } 5408 5409 // ACLE 6.4.8 Saturation instructions 5410 bool SAT = false; 5411 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5412 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5413 SAT = true; 5414 } 5415 5416 // ACLE 6.4.6 Q (saturation) flag 5417 if (DSP || SAT) 5418 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5419 5420 if (Opts.UnsafeFPMath) 5421 Builder.defineMacro("__ARM_FP_FAST", "1"); 5422 5423 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5424 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5425 } 5426 5427 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5428 return llvm::makeArrayRef(BuiltinInfo, 5429 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5430 } 5431 bool isCLZForZeroUndef() const override { return false; } 5432 BuiltinVaListKind getBuiltinVaListKind() const override { 5433 return IsAAPCS 5434 ? AAPCSABIBuiltinVaList 5435 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5436 : TargetInfo::VoidPtrBuiltinVaList); 5437 } 5438 ArrayRef<const char *> getGCCRegNames() const override; 5439 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5440 bool validateAsmConstraint(const char *&Name, 5441 TargetInfo::ConstraintInfo &Info) const override { 5442 switch (*Name) { 5443 default: break; 5444 case 'l': // r0-r7 5445 case 'h': // r8-r15 5446 case 't': // VFP Floating point register single precision 5447 case 'w': // VFP Floating point register double precision 5448 Info.setAllowsRegister(); 5449 return true; 5450 case 'I': 5451 case 'J': 5452 case 'K': 5453 case 'L': 5454 case 'M': 5455 // FIXME 5456 return true; 5457 case 'Q': // A memory address that is a single base register. 5458 Info.setAllowsMemory(); 5459 return true; 5460 case 'U': // a memory reference... 5461 switch (Name[1]) { 5462 case 'q': // ...ARMV4 ldrsb 5463 case 'v': // ...VFP load/store (reg+constant offset) 5464 case 'y': // ...iWMMXt load/store 5465 case 't': // address valid for load/store opaque types wider 5466 // than 128-bits 5467 case 'n': // valid address for Neon doubleword vector load/store 5468 case 'm': // valid address for Neon element and structure load/store 5469 case 's': // valid address for non-offset loads/stores of quad-word 5470 // values in four ARM registers 5471 Info.setAllowsMemory(); 5472 Name++; 5473 return true; 5474 } 5475 } 5476 return false; 5477 } 5478 std::string convertConstraint(const char *&Constraint) const override { 5479 std::string R; 5480 switch (*Constraint) { 5481 case 'U': // Two-character constraint; add "^" hint for later parsing. 5482 R = std::string("^") + std::string(Constraint, 2); 5483 Constraint++; 5484 break; 5485 case 'p': // 'p' should be translated to 'r' by default. 5486 R = std::string("r"); 5487 break; 5488 default: 5489 return std::string(1, *Constraint); 5490 } 5491 return R; 5492 } 5493 bool 5494 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5495 std::string &SuggestedModifier) const override { 5496 bool isOutput = (Constraint[0] == '='); 5497 bool isInOut = (Constraint[0] == '+'); 5498 5499 // Strip off constraint modifiers. 5500 while (Constraint[0] == '=' || 5501 Constraint[0] == '+' || 5502 Constraint[0] == '&') 5503 Constraint = Constraint.substr(1); 5504 5505 switch (Constraint[0]) { 5506 default: break; 5507 case 'r': { 5508 switch (Modifier) { 5509 default: 5510 return (isInOut || isOutput || Size <= 64); 5511 case 'q': 5512 // A register of size 32 cannot fit a vector type. 5513 return false; 5514 } 5515 } 5516 } 5517 5518 return true; 5519 } 5520 const char *getClobbers() const override { 5521 // FIXME: Is this really right? 5522 return ""; 5523 } 5524 5525 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5526 switch (CC) { 5527 case CC_AAPCS: 5528 case CC_AAPCS_VFP: 5529 case CC_Swift: 5530 return CCCR_OK; 5531 default: 5532 return CCCR_Warning; 5533 } 5534 } 5535 5536 int getEHDataRegisterNumber(unsigned RegNo) const override { 5537 if (RegNo == 0) return 0; 5538 if (RegNo == 1) return 1; 5539 return -1; 5540 } 5541 5542 bool hasSjLjLowering() const override { 5543 return true; 5544 } 5545 }; 5546 5547 bool ARMTargetInfo::setFPMath(StringRef Name) { 5548 if (Name == "neon") { 5549 FPMath = FP_Neon; 5550 return true; 5551 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5552 Name == "vfp4") { 5553 FPMath = FP_VFP; 5554 return true; 5555 } 5556 return false; 5557 } 5558 5559 const char * const ARMTargetInfo::GCCRegNames[] = { 5560 // Integer registers 5561 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5562 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5563 5564 // Float registers 5565 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5566 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5567 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5568 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5569 5570 // Double registers 5571 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5572 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5573 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5574 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5575 5576 // Quad registers 5577 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5578 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5579 }; 5580 5581 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5582 return llvm::makeArrayRef(GCCRegNames); 5583 } 5584 5585 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5586 { { "a1" }, "r0" }, 5587 { { "a2" }, "r1" }, 5588 { { "a3" }, "r2" }, 5589 { { "a4" }, "r3" }, 5590 { { "v1" }, "r4" }, 5591 { { "v2" }, "r5" }, 5592 { { "v3" }, "r6" }, 5593 { { "v4" }, "r7" }, 5594 { { "v5" }, "r8" }, 5595 { { "v6", "rfp" }, "r9" }, 5596 { { "sl" }, "r10" }, 5597 { { "fp" }, "r11" }, 5598 { { "ip" }, "r12" }, 5599 { { "r13" }, "sp" }, 5600 { { "r14" }, "lr" }, 5601 { { "r15" }, "pc" }, 5602 // The S, D and Q registers overlap, but aren't really aliases; we 5603 // don't want to substitute one of these for a different-sized one. 5604 }; 5605 5606 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5607 return llvm::makeArrayRef(GCCRegAliases); 5608 } 5609 5610 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5611 #define BUILTIN(ID, TYPE, ATTRS) \ 5612 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5613 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5614 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5615 #include "clang/Basic/BuiltinsNEON.def" 5616 5617 #define BUILTIN(ID, TYPE, ATTRS) \ 5618 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5619 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5620 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5621 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5622 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5623 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5624 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5625 #include "clang/Basic/BuiltinsARM.def" 5626 }; 5627 5628 class ARMleTargetInfo : public ARMTargetInfo { 5629 public: 5630 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5631 : ARMTargetInfo(Triple, Opts) {} 5632 void getTargetDefines(const LangOptions &Opts, 5633 MacroBuilder &Builder) const override { 5634 Builder.defineMacro("__ARMEL__"); 5635 ARMTargetInfo::getTargetDefines(Opts, Builder); 5636 } 5637 }; 5638 5639 class ARMbeTargetInfo : public ARMTargetInfo { 5640 public: 5641 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5642 : ARMTargetInfo(Triple, Opts) {} 5643 void getTargetDefines(const LangOptions &Opts, 5644 MacroBuilder &Builder) const override { 5645 Builder.defineMacro("__ARMEB__"); 5646 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5647 ARMTargetInfo::getTargetDefines(Opts, Builder); 5648 } 5649 }; 5650 5651 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5652 const llvm::Triple Triple; 5653 public: 5654 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5655 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5656 WCharType = UnsignedShort; 5657 SizeType = UnsignedInt; 5658 } 5659 void getVisualStudioDefines(const LangOptions &Opts, 5660 MacroBuilder &Builder) const { 5661 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5662 5663 // FIXME: this is invalid for WindowsCE 5664 Builder.defineMacro("_M_ARM_NT", "1"); 5665 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5666 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5667 5668 assert((Triple.getArch() == llvm::Triple::arm || 5669 Triple.getArch() == llvm::Triple::thumb) && 5670 "invalid architecture for Windows ARM target info"); 5671 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5672 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5673 5674 // TODO map the complete set of values 5675 // 31: VFPv3 40: VFPv4 5676 Builder.defineMacro("_M_ARM_FP", "31"); 5677 } 5678 BuiltinVaListKind getBuiltinVaListKind() const override { 5679 return TargetInfo::CharPtrBuiltinVaList; 5680 } 5681 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5682 switch (CC) { 5683 case CC_X86StdCall: 5684 case CC_X86ThisCall: 5685 case CC_X86FastCall: 5686 case CC_X86VectorCall: 5687 return CCCR_Ignore; 5688 case CC_C: 5689 return CCCR_OK; 5690 default: 5691 return CCCR_Warning; 5692 } 5693 } 5694 }; 5695 5696 // Windows ARM + Itanium C++ ABI Target 5697 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5698 public: 5699 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5700 const TargetOptions &Opts) 5701 : WindowsARMTargetInfo(Triple, Opts) { 5702 TheCXXABI.set(TargetCXXABI::GenericARM); 5703 } 5704 5705 void getTargetDefines(const LangOptions &Opts, 5706 MacroBuilder &Builder) const override { 5707 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5708 5709 if (Opts.MSVCCompat) 5710 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5711 } 5712 }; 5713 5714 // Windows ARM, MS (C++) ABI 5715 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5716 public: 5717 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5718 const TargetOptions &Opts) 5719 : WindowsARMTargetInfo(Triple, Opts) { 5720 TheCXXABI.set(TargetCXXABI::Microsoft); 5721 } 5722 5723 void getTargetDefines(const LangOptions &Opts, 5724 MacroBuilder &Builder) const override { 5725 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5726 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5727 } 5728 }; 5729 5730 // ARM MinGW target 5731 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5732 public: 5733 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5734 : WindowsARMTargetInfo(Triple, Opts) { 5735 TheCXXABI.set(TargetCXXABI::GenericARM); 5736 } 5737 5738 void getTargetDefines(const LangOptions &Opts, 5739 MacroBuilder &Builder) const override { 5740 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5741 DefineStd(Builder, "WIN32", Opts); 5742 DefineStd(Builder, "WINNT", Opts); 5743 Builder.defineMacro("_ARM_"); 5744 addMinGWDefines(Opts, Builder); 5745 } 5746 }; 5747 5748 // ARM Cygwin target 5749 class CygwinARMTargetInfo : public ARMleTargetInfo { 5750 public: 5751 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5752 : ARMleTargetInfo(Triple, Opts) { 5753 TLSSupported = false; 5754 WCharType = UnsignedShort; 5755 DoubleAlign = LongLongAlign = 64; 5756 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5757 } 5758 void getTargetDefines(const LangOptions &Opts, 5759 MacroBuilder &Builder) const override { 5760 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5761 Builder.defineMacro("_ARM_"); 5762 Builder.defineMacro("__CYGWIN__"); 5763 Builder.defineMacro("__CYGWIN32__"); 5764 DefineStd(Builder, "unix", Opts); 5765 if (Opts.CPlusPlus) 5766 Builder.defineMacro("_GNU_SOURCE"); 5767 } 5768 }; 5769 5770 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5771 protected: 5772 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5773 MacroBuilder &Builder) const override { 5774 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5775 } 5776 5777 public: 5778 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5779 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5780 HasAlignMac68kSupport = true; 5781 // iOS always has 64-bit atomic instructions. 5782 // FIXME: This should be based off of the target features in 5783 // ARMleTargetInfo. 5784 MaxAtomicInlineWidth = 64; 5785 5786 if (Triple.isWatchABI()) { 5787 // Darwin on iOS uses a variant of the ARM C++ ABI. 5788 TheCXXABI.set(TargetCXXABI::WatchOS); 5789 5790 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5791 // size_t is long, it's a bit weird for it to be int. 5792 PtrDiffType = SignedLong; 5793 5794 // BOOL should be a real boolean on the new ABI 5795 UseSignedCharForObjCBool = false; 5796 } else 5797 TheCXXABI.set(TargetCXXABI::iOS); 5798 } 5799 }; 5800 5801 class AArch64TargetInfo : public TargetInfo { 5802 virtual void setDataLayout() = 0; 5803 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5804 static const char *const GCCRegNames[]; 5805 5806 enum FPUModeEnum { 5807 FPUMode, 5808 NeonMode 5809 }; 5810 5811 unsigned FPU; 5812 unsigned CRC; 5813 unsigned Crypto; 5814 unsigned Unaligned; 5815 unsigned V8_1A; 5816 5817 static const Builtin::Info BuiltinInfo[]; 5818 5819 std::string ABI; 5820 5821 public: 5822 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5823 : TargetInfo(Triple), ABI("aapcs") { 5824 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5825 WCharType = SignedInt; 5826 5827 // NetBSD apparently prefers consistency across ARM targets to consistency 5828 // across 64-bit targets. 5829 Int64Type = SignedLongLong; 5830 IntMaxType = SignedLongLong; 5831 } else { 5832 WCharType = UnsignedInt; 5833 Int64Type = SignedLong; 5834 IntMaxType = SignedLong; 5835 } 5836 5837 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5838 MaxVectorAlign = 128; 5839 MaxAtomicInlineWidth = 128; 5840 MaxAtomicPromoteWidth = 128; 5841 5842 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5843 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5844 5845 // {} in inline assembly are neon specifiers, not assembly variant 5846 // specifiers. 5847 NoAsmVariants = true; 5848 5849 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5850 // contributes to the alignment of the containing aggregate in the same way 5851 // a plain (non bit-field) member of that type would, without exception for 5852 // zero-sized or anonymous bit-fields." 5853 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5854 UseZeroLengthBitfieldAlignment = true; 5855 5856 // AArch64 targets default to using the ARM C++ ABI. 5857 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5858 5859 if (Triple.getOS() == llvm::Triple::Linux || 5860 Triple.getOS() == llvm::Triple::UnknownOS) 5861 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5862 } 5863 5864 StringRef getABI() const override { return ABI; } 5865 bool setABI(const std::string &Name) override { 5866 if (Name != "aapcs" && Name != "darwinpcs") 5867 return false; 5868 5869 ABI = Name; 5870 return true; 5871 } 5872 5873 bool setCPU(const std::string &Name) override { 5874 return Name == "generic" || 5875 llvm::AArch64::parseCPUArch(Name) != 5876 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5877 } 5878 5879 void getTargetDefines(const LangOptions &Opts, 5880 MacroBuilder &Builder) const override { 5881 // Target identification. 5882 Builder.defineMacro("__aarch64__"); 5883 5884 // Target properties. 5885 Builder.defineMacro("_LP64"); 5886 Builder.defineMacro("__LP64__"); 5887 5888 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5889 Builder.defineMacro("__ARM_ACLE", "200"); 5890 Builder.defineMacro("__ARM_ARCH", "8"); 5891 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5892 5893 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5894 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5895 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5896 5897 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5898 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5899 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5900 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5901 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5902 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5903 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5904 5905 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5906 5907 // 0xe implies support for half, single and double precision operations. 5908 Builder.defineMacro("__ARM_FP", "0xE"); 5909 5910 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5911 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5912 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5913 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5914 5915 if (Opts.UnsafeFPMath) 5916 Builder.defineMacro("__ARM_FP_FAST", "1"); 5917 5918 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5919 5920 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5921 Opts.ShortEnums ? "1" : "4"); 5922 5923 if (FPU == NeonMode) { 5924 Builder.defineMacro("__ARM_NEON", "1"); 5925 // 64-bit NEON supports half, single and double precision operations. 5926 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5927 } 5928 5929 if (CRC) 5930 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5931 5932 if (Crypto) 5933 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5934 5935 if (Unaligned) 5936 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5937 5938 if (V8_1A) 5939 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5940 5941 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5942 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5943 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5944 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5945 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5946 } 5947 5948 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5949 return llvm::makeArrayRef(BuiltinInfo, 5950 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5951 } 5952 5953 bool hasFeature(StringRef Feature) const override { 5954 return Feature == "aarch64" || 5955 Feature == "arm64" || 5956 Feature == "arm" || 5957 (Feature == "neon" && FPU == NeonMode); 5958 } 5959 5960 bool handleTargetFeatures(std::vector<std::string> &Features, 5961 DiagnosticsEngine &Diags) override { 5962 FPU = FPUMode; 5963 CRC = 0; 5964 Crypto = 0; 5965 Unaligned = 1; 5966 V8_1A = 0; 5967 5968 for (const auto &Feature : Features) { 5969 if (Feature == "+neon") 5970 FPU = NeonMode; 5971 if (Feature == "+crc") 5972 CRC = 1; 5973 if (Feature == "+crypto") 5974 Crypto = 1; 5975 if (Feature == "+strict-align") 5976 Unaligned = 0; 5977 if (Feature == "+v8.1a") 5978 V8_1A = 1; 5979 } 5980 5981 setDataLayout(); 5982 5983 return true; 5984 } 5985 5986 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5987 switch (CC) { 5988 case CC_C: 5989 case CC_Swift: 5990 case CC_PreserveMost: 5991 case CC_PreserveAll: 5992 return CCCR_OK; 5993 default: 5994 return CCCR_Warning; 5995 } 5996 } 5997 5998 bool isCLZForZeroUndef() const override { return false; } 5999 6000 BuiltinVaListKind getBuiltinVaListKind() const override { 6001 return TargetInfo::AArch64ABIBuiltinVaList; 6002 } 6003 6004 ArrayRef<const char *> getGCCRegNames() const override; 6005 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6006 6007 bool validateAsmConstraint(const char *&Name, 6008 TargetInfo::ConstraintInfo &Info) const override { 6009 switch (*Name) { 6010 default: 6011 return false; 6012 case 'w': // Floating point and SIMD registers (V0-V31) 6013 Info.setAllowsRegister(); 6014 return true; 6015 case 'I': // Constant that can be used with an ADD instruction 6016 case 'J': // Constant that can be used with a SUB instruction 6017 case 'K': // Constant that can be used with a 32-bit logical instruction 6018 case 'L': // Constant that can be used with a 64-bit logical instruction 6019 case 'M': // Constant that can be used as a 32-bit MOV immediate 6020 case 'N': // Constant that can be used as a 64-bit MOV immediate 6021 case 'Y': // Floating point constant zero 6022 case 'Z': // Integer constant zero 6023 return true; 6024 case 'Q': // A memory reference with base register and no offset 6025 Info.setAllowsMemory(); 6026 return true; 6027 case 'S': // A symbolic address 6028 Info.setAllowsRegister(); 6029 return true; 6030 case 'U': 6031 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6032 // Utf: A memory address suitable for ldp/stp in TF mode. 6033 // Usa: An absolute symbolic address. 6034 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6035 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6036 case 'z': // Zero register, wzr or xzr 6037 Info.setAllowsRegister(); 6038 return true; 6039 case 'x': // Floating point and SIMD registers (V0-V15) 6040 Info.setAllowsRegister(); 6041 return true; 6042 } 6043 return false; 6044 } 6045 6046 bool 6047 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6048 std::string &SuggestedModifier) const override { 6049 // Strip off constraint modifiers. 6050 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6051 Constraint = Constraint.substr(1); 6052 6053 switch (Constraint[0]) { 6054 default: 6055 return true; 6056 case 'z': 6057 case 'r': { 6058 switch (Modifier) { 6059 case 'x': 6060 case 'w': 6061 // For now assume that the person knows what they're 6062 // doing with the modifier. 6063 return true; 6064 default: 6065 // By default an 'r' constraint will be in the 'x' 6066 // registers. 6067 if (Size == 64) 6068 return true; 6069 6070 SuggestedModifier = "w"; 6071 return false; 6072 } 6073 } 6074 } 6075 } 6076 6077 const char *getClobbers() const override { return ""; } 6078 6079 int getEHDataRegisterNumber(unsigned RegNo) const override { 6080 if (RegNo == 0) 6081 return 0; 6082 if (RegNo == 1) 6083 return 1; 6084 return -1; 6085 } 6086 }; 6087 6088 const char *const AArch64TargetInfo::GCCRegNames[] = { 6089 // 32-bit Integer registers 6090 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6091 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6092 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6093 6094 // 64-bit Integer registers 6095 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6096 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6097 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6098 6099 // 32-bit floating point regsisters 6100 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6101 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6102 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6103 6104 // 64-bit floating point regsisters 6105 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6106 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6107 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6108 6109 // Vector registers 6110 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6111 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6112 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6113 }; 6114 6115 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6116 return llvm::makeArrayRef(GCCRegNames); 6117 } 6118 6119 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6120 { { "w31" }, "wsp" }, 6121 { { "x29" }, "fp" }, 6122 { { "x30" }, "lr" }, 6123 { { "x31" }, "sp" }, 6124 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6125 // don't want to substitute one of these for a different-sized one. 6126 }; 6127 6128 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6129 return llvm::makeArrayRef(GCCRegAliases); 6130 } 6131 6132 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6133 #define BUILTIN(ID, TYPE, ATTRS) \ 6134 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6135 #include "clang/Basic/BuiltinsNEON.def" 6136 6137 #define BUILTIN(ID, TYPE, ATTRS) \ 6138 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6139 #include "clang/Basic/BuiltinsAArch64.def" 6140 }; 6141 6142 class AArch64leTargetInfo : public AArch64TargetInfo { 6143 void setDataLayout() override { 6144 if (getTriple().isOSBinFormatMachO()) 6145 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6146 else 6147 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6148 } 6149 6150 public: 6151 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6152 : AArch64TargetInfo(Triple, Opts) { 6153 } 6154 void getTargetDefines(const LangOptions &Opts, 6155 MacroBuilder &Builder) const override { 6156 Builder.defineMacro("__AARCH64EL__"); 6157 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6158 } 6159 }; 6160 6161 class AArch64beTargetInfo : public AArch64TargetInfo { 6162 void setDataLayout() override { 6163 assert(!getTriple().isOSBinFormatMachO()); 6164 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6165 } 6166 6167 public: 6168 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6169 : AArch64TargetInfo(Triple, Opts) {} 6170 void getTargetDefines(const LangOptions &Opts, 6171 MacroBuilder &Builder) const override { 6172 Builder.defineMacro("__AARCH64EB__"); 6173 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6174 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6175 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6176 } 6177 }; 6178 6179 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6180 protected: 6181 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6182 MacroBuilder &Builder) const override { 6183 Builder.defineMacro("__AARCH64_SIMD__"); 6184 Builder.defineMacro("__ARM64_ARCH_8__"); 6185 Builder.defineMacro("__ARM_NEON__"); 6186 Builder.defineMacro("__LITTLE_ENDIAN__"); 6187 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6188 Builder.defineMacro("__arm64", "1"); 6189 Builder.defineMacro("__arm64__", "1"); 6190 6191 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6192 } 6193 6194 public: 6195 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6196 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6197 Int64Type = SignedLongLong; 6198 WCharType = SignedInt; 6199 UseSignedCharForObjCBool = false; 6200 6201 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6202 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6203 6204 TheCXXABI.set(TargetCXXABI::iOS64); 6205 } 6206 6207 BuiltinVaListKind getBuiltinVaListKind() const override { 6208 return TargetInfo::CharPtrBuiltinVaList; 6209 } 6210 }; 6211 6212 // Hexagon abstract base class 6213 class HexagonTargetInfo : public TargetInfo { 6214 static const Builtin::Info BuiltinInfo[]; 6215 static const char * const GCCRegNames[]; 6216 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6217 std::string CPU; 6218 bool HasHVX, HasHVXDouble; 6219 bool UseLongCalls; 6220 6221 public: 6222 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6223 : TargetInfo(Triple) { 6224 // Specify the vector alignment explicitly. For v512x1, the calculated 6225 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6226 // the required minimum of 64 bytes. 6227 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6228 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6229 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6230 SizeType = UnsignedInt; 6231 PtrDiffType = SignedInt; 6232 IntPtrType = SignedInt; 6233 6234 // {} in inline assembly are packet specifiers, not assembly variant 6235 // specifiers. 6236 NoAsmVariants = true; 6237 6238 LargeArrayMinWidth = 64; 6239 LargeArrayAlign = 64; 6240 UseBitFieldTypeAlignment = true; 6241 ZeroLengthBitfieldBoundary = 32; 6242 HasHVX = HasHVXDouble = false; 6243 UseLongCalls = false; 6244 } 6245 6246 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6247 return llvm::makeArrayRef(BuiltinInfo, 6248 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6249 } 6250 6251 bool validateAsmConstraint(const char *&Name, 6252 TargetInfo::ConstraintInfo &Info) const override { 6253 switch (*Name) { 6254 case 'v': 6255 case 'q': 6256 if (HasHVX) { 6257 Info.setAllowsRegister(); 6258 return true; 6259 } 6260 break; 6261 case 's': 6262 // Relocatable constant. 6263 return true; 6264 } 6265 return false; 6266 } 6267 6268 void getTargetDefines(const LangOptions &Opts, 6269 MacroBuilder &Builder) const override; 6270 6271 bool isCLZForZeroUndef() const override { return false; } 6272 6273 bool hasFeature(StringRef Feature) const override { 6274 return llvm::StringSwitch<bool>(Feature) 6275 .Case("hexagon", true) 6276 .Case("hvx", HasHVX) 6277 .Case("hvx-double", HasHVXDouble) 6278 .Case("long-calls", UseLongCalls) 6279 .Default(false); 6280 } 6281 6282 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6283 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6284 const override; 6285 6286 bool handleTargetFeatures(std::vector<std::string> &Features, 6287 DiagnosticsEngine &Diags) override; 6288 6289 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6290 bool Enabled) const override; 6291 6292 BuiltinVaListKind getBuiltinVaListKind() const override { 6293 return TargetInfo::CharPtrBuiltinVaList; 6294 } 6295 ArrayRef<const char *> getGCCRegNames() const override; 6296 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6297 const char *getClobbers() const override { 6298 return ""; 6299 } 6300 6301 static const char *getHexagonCPUSuffix(StringRef Name) { 6302 return llvm::StringSwitch<const char*>(Name) 6303 .Case("hexagonv4", "4") 6304 .Case("hexagonv5", "5") 6305 .Case("hexagonv55", "55") 6306 .Case("hexagonv60", "60") 6307 .Default(nullptr); 6308 } 6309 6310 bool setCPU(const std::string &Name) override { 6311 if (!getHexagonCPUSuffix(Name)) 6312 return false; 6313 CPU = Name; 6314 return true; 6315 } 6316 6317 int getEHDataRegisterNumber(unsigned RegNo) const override { 6318 return RegNo < 2 ? RegNo : -1; 6319 } 6320 }; 6321 6322 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6323 MacroBuilder &Builder) const { 6324 Builder.defineMacro("__qdsp6__", "1"); 6325 Builder.defineMacro("__hexagon__", "1"); 6326 6327 if (CPU == "hexagonv4") { 6328 Builder.defineMacro("__HEXAGON_V4__"); 6329 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6330 if (Opts.HexagonQdsp6Compat) { 6331 Builder.defineMacro("__QDSP6_V4__"); 6332 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6333 } 6334 } else if (CPU == "hexagonv5") { 6335 Builder.defineMacro("__HEXAGON_V5__"); 6336 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6337 if(Opts.HexagonQdsp6Compat) { 6338 Builder.defineMacro("__QDSP6_V5__"); 6339 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6340 } 6341 } else if (CPU == "hexagonv55") { 6342 Builder.defineMacro("__HEXAGON_V55__"); 6343 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6344 Builder.defineMacro("__QDSP6_V55__"); 6345 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6346 } else if (CPU == "hexagonv60") { 6347 Builder.defineMacro("__HEXAGON_V60__"); 6348 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6349 Builder.defineMacro("__QDSP6_V60__"); 6350 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6351 } 6352 6353 if (hasFeature("hvx")) { 6354 Builder.defineMacro("__HVX__"); 6355 if (hasFeature("hvx-double")) 6356 Builder.defineMacro("__HVXDBL__"); 6357 } 6358 } 6359 6360 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6361 DiagnosticsEngine &Diags, StringRef CPU, 6362 const std::vector<std::string> &FeaturesVec) const { 6363 // Default for v60: -hvx, -hvx-double. 6364 Features["hvx"] = false; 6365 Features["hvx-double"] = false; 6366 Features["long-calls"] = false; 6367 6368 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6369 } 6370 6371 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6372 DiagnosticsEngine &Diags) { 6373 for (auto &F : Features) { 6374 if (F == "+hvx") 6375 HasHVX = true; 6376 else if (F == "-hvx") 6377 HasHVX = HasHVXDouble = false; 6378 else if (F == "+hvx-double") 6379 HasHVX = HasHVXDouble = true; 6380 else if (F == "-hvx-double") 6381 HasHVXDouble = false; 6382 6383 if (F == "+long-calls") 6384 UseLongCalls = true; 6385 else if (F == "-long-calls") 6386 UseLongCalls = false; 6387 } 6388 return true; 6389 } 6390 6391 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6392 StringRef Name, bool Enabled) const { 6393 if (Enabled) { 6394 if (Name == "hvx-double") 6395 Features["hvx"] = true; 6396 } else { 6397 if (Name == "hvx") 6398 Features["hvx-double"] = false; 6399 } 6400 Features[Name] = Enabled; 6401 } 6402 6403 const char *const HexagonTargetInfo::GCCRegNames[] = { 6404 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6405 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6406 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6407 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6408 "p0", "p1", "p2", "p3", 6409 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6410 }; 6411 6412 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6413 return llvm::makeArrayRef(GCCRegNames); 6414 } 6415 6416 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6417 { { "sp" }, "r29" }, 6418 { { "fp" }, "r30" }, 6419 { { "lr" }, "r31" }, 6420 }; 6421 6422 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6423 return llvm::makeArrayRef(GCCRegAliases); 6424 } 6425 6426 6427 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6428 #define BUILTIN(ID, TYPE, ATTRS) \ 6429 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6430 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6431 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6432 #include "clang/Basic/BuiltinsHexagon.def" 6433 }; 6434 6435 class LanaiTargetInfo : public TargetInfo { 6436 // Class for Lanai (32-bit). 6437 // The CPU profiles supported by the Lanai backend 6438 enum CPUKind { 6439 CK_NONE, 6440 CK_V11, 6441 } CPU; 6442 6443 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6444 static const char *const GCCRegNames[]; 6445 6446 public: 6447 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6448 : TargetInfo(Triple) { 6449 // Description string has to be kept in sync with backend. 6450 resetDataLayout("E" // Big endian 6451 "-m:e" // ELF name manging 6452 "-p:32:32" // 32 bit pointers, 32 bit aligned 6453 "-i64:64" // 64 bit integers, 64 bit aligned 6454 "-a:0:32" // 32 bit alignment of objects of aggregate type 6455 "-n32" // 32 bit native integer width 6456 "-S64" // 64 bit natural stack alignment 6457 ); 6458 6459 // Setting RegParmMax equal to what mregparm was set to in the old 6460 // toolchain 6461 RegParmMax = 4; 6462 6463 // Set the default CPU to V11 6464 CPU = CK_V11; 6465 6466 // Temporary approach to make everything at least word-aligned and allow for 6467 // safely casting between pointers with different alignment requirements. 6468 // TODO: Remove this when there are no more cast align warnings on the 6469 // firmware. 6470 MinGlobalAlign = 32; 6471 } 6472 6473 void getTargetDefines(const LangOptions &Opts, 6474 MacroBuilder &Builder) const override { 6475 // Define __lanai__ when building for target lanai. 6476 Builder.defineMacro("__lanai__"); 6477 6478 // Set define for the CPU specified. 6479 switch (CPU) { 6480 case CK_V11: 6481 Builder.defineMacro("__LANAI_V11__"); 6482 break; 6483 case CK_NONE: 6484 llvm_unreachable("Unhandled target CPU"); 6485 } 6486 } 6487 6488 bool setCPU(const std::string &Name) override { 6489 CPU = llvm::StringSwitch<CPUKind>(Name) 6490 .Case("v11", CK_V11) 6491 .Default(CK_NONE); 6492 6493 return CPU != CK_NONE; 6494 } 6495 6496 bool hasFeature(StringRef Feature) const override { 6497 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6498 } 6499 6500 ArrayRef<const char *> getGCCRegNames() const override; 6501 6502 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6503 6504 BuiltinVaListKind getBuiltinVaListKind() const override { 6505 return TargetInfo::VoidPtrBuiltinVaList; 6506 } 6507 6508 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6509 6510 bool validateAsmConstraint(const char *&Name, 6511 TargetInfo::ConstraintInfo &info) const override { 6512 return false; 6513 } 6514 6515 const char *getClobbers() const override { return ""; } 6516 }; 6517 6518 const char *const LanaiTargetInfo::GCCRegNames[] = { 6519 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6520 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6521 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6522 6523 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6524 return llvm::makeArrayRef(GCCRegNames); 6525 } 6526 6527 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6528 {{"pc"}, "r2"}, 6529 {{"sp"}, "r4"}, 6530 {{"fp"}, "r5"}, 6531 {{"rv"}, "r8"}, 6532 {{"rr1"}, "r10"}, 6533 {{"rr2"}, "r11"}, 6534 {{"rca"}, "r15"}, 6535 }; 6536 6537 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6538 return llvm::makeArrayRef(GCCRegAliases); 6539 } 6540 6541 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6542 class SparcTargetInfo : public TargetInfo { 6543 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6544 static const char * const GCCRegNames[]; 6545 bool SoftFloat; 6546 public: 6547 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6548 : TargetInfo(Triple), SoftFloat(false) {} 6549 6550 int getEHDataRegisterNumber(unsigned RegNo) const override { 6551 if (RegNo == 0) return 24; 6552 if (RegNo == 1) return 25; 6553 return -1; 6554 } 6555 6556 bool handleTargetFeatures(std::vector<std::string> &Features, 6557 DiagnosticsEngine &Diags) override { 6558 // Check if software floating point is enabled 6559 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6560 if (Feature != Features.end()) { 6561 SoftFloat = true; 6562 } 6563 return true; 6564 } 6565 void getTargetDefines(const LangOptions &Opts, 6566 MacroBuilder &Builder) const override { 6567 DefineStd(Builder, "sparc", Opts); 6568 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6569 6570 if (SoftFloat) 6571 Builder.defineMacro("SOFT_FLOAT", "1"); 6572 } 6573 6574 bool hasFeature(StringRef Feature) const override { 6575 return llvm::StringSwitch<bool>(Feature) 6576 .Case("softfloat", SoftFloat) 6577 .Case("sparc", true) 6578 .Default(false); 6579 } 6580 6581 bool hasSjLjLowering() const override { 6582 return true; 6583 } 6584 6585 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6586 // FIXME: Implement! 6587 return None; 6588 } 6589 BuiltinVaListKind getBuiltinVaListKind() const override { 6590 return TargetInfo::VoidPtrBuiltinVaList; 6591 } 6592 ArrayRef<const char *> getGCCRegNames() const override; 6593 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6594 bool validateAsmConstraint(const char *&Name, 6595 TargetInfo::ConstraintInfo &info) const override { 6596 // FIXME: Implement! 6597 switch (*Name) { 6598 case 'I': // Signed 13-bit constant 6599 case 'J': // Zero 6600 case 'K': // 32-bit constant with the low 12 bits clear 6601 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6602 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6603 case 'N': // Same as 'K' but zext (required for SIMode) 6604 case 'O': // The constant 4096 6605 return true; 6606 } 6607 return false; 6608 } 6609 const char *getClobbers() const override { 6610 // FIXME: Implement! 6611 return ""; 6612 } 6613 6614 // No Sparc V7 for now, the backend doesn't support it anyway. 6615 enum CPUKind { 6616 CK_GENERIC, 6617 CK_V8, 6618 CK_SUPERSPARC, 6619 CK_SPARCLITE, 6620 CK_F934, 6621 CK_HYPERSPARC, 6622 CK_SPARCLITE86X, 6623 CK_SPARCLET, 6624 CK_TSC701, 6625 CK_V9, 6626 CK_ULTRASPARC, 6627 CK_ULTRASPARC3, 6628 CK_NIAGARA, 6629 CK_NIAGARA2, 6630 CK_NIAGARA3, 6631 CK_NIAGARA4, 6632 CK_MYRIAD2100, 6633 CK_MYRIAD2150, 6634 CK_MYRIAD2450, 6635 CK_LEON2, 6636 CK_LEON2_AT697E, 6637 CK_LEON2_AT697F, 6638 CK_LEON3, 6639 CK_LEON3_UT699, 6640 CK_LEON3_GR712RC, 6641 CK_LEON4, 6642 CK_LEON4_GR740 6643 } CPU = CK_GENERIC; 6644 6645 enum CPUGeneration { 6646 CG_V8, 6647 CG_V9, 6648 }; 6649 6650 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6651 switch (Kind) { 6652 case CK_GENERIC: 6653 case CK_V8: 6654 case CK_SUPERSPARC: 6655 case CK_SPARCLITE: 6656 case CK_F934: 6657 case CK_HYPERSPARC: 6658 case CK_SPARCLITE86X: 6659 case CK_SPARCLET: 6660 case CK_TSC701: 6661 case CK_MYRIAD2100: 6662 case CK_MYRIAD2150: 6663 case CK_MYRIAD2450: 6664 case CK_LEON2: 6665 case CK_LEON2_AT697E: 6666 case CK_LEON2_AT697F: 6667 case CK_LEON3: 6668 case CK_LEON3_UT699: 6669 case CK_LEON3_GR712RC: 6670 case CK_LEON4: 6671 case CK_LEON4_GR740: 6672 return CG_V8; 6673 case CK_V9: 6674 case CK_ULTRASPARC: 6675 case CK_ULTRASPARC3: 6676 case CK_NIAGARA: 6677 case CK_NIAGARA2: 6678 case CK_NIAGARA3: 6679 case CK_NIAGARA4: 6680 return CG_V9; 6681 } 6682 llvm_unreachable("Unexpected CPU kind"); 6683 } 6684 6685 CPUKind getCPUKind(StringRef Name) const { 6686 return llvm::StringSwitch<CPUKind>(Name) 6687 .Case("v8", CK_V8) 6688 .Case("supersparc", CK_SUPERSPARC) 6689 .Case("sparclite", CK_SPARCLITE) 6690 .Case("f934", CK_F934) 6691 .Case("hypersparc", CK_HYPERSPARC) 6692 .Case("sparclite86x", CK_SPARCLITE86X) 6693 .Case("sparclet", CK_SPARCLET) 6694 .Case("tsc701", CK_TSC701) 6695 .Case("v9", CK_V9) 6696 .Case("ultrasparc", CK_ULTRASPARC) 6697 .Case("ultrasparc3", CK_ULTRASPARC3) 6698 .Case("niagara", CK_NIAGARA) 6699 .Case("niagara2", CK_NIAGARA2) 6700 .Case("niagara3", CK_NIAGARA3) 6701 .Case("niagara4", CK_NIAGARA4) 6702 .Case("ma2100", CK_MYRIAD2100) 6703 .Case("ma2150", CK_MYRIAD2150) 6704 .Case("ma2450", CK_MYRIAD2450) 6705 // FIXME: the myriad2[.n] spellings are obsolete, 6706 // but a grace period is needed to allow updating dependent builds. 6707 .Case("myriad2", CK_MYRIAD2100) 6708 .Case("myriad2.1", CK_MYRIAD2100) 6709 .Case("myriad2.2", CK_MYRIAD2150) 6710 .Case("leon2", CK_LEON2) 6711 .Case("at697e", CK_LEON2_AT697E) 6712 .Case("at697f", CK_LEON2_AT697F) 6713 .Case("leon3", CK_LEON3) 6714 .Case("ut699", CK_LEON3_UT699) 6715 .Case("gr712rc", CK_LEON3_GR712RC) 6716 .Case("leon4", CK_LEON4) 6717 .Case("gr740", CK_LEON4_GR740) 6718 .Default(CK_GENERIC); 6719 } 6720 6721 bool setCPU(const std::string &Name) override { 6722 CPU = getCPUKind(Name); 6723 return CPU != CK_GENERIC; 6724 } 6725 }; 6726 6727 const char * const SparcTargetInfo::GCCRegNames[] = { 6728 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6729 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6730 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6731 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6732 }; 6733 6734 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6735 return llvm::makeArrayRef(GCCRegNames); 6736 } 6737 6738 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6739 { { "g0" }, "r0" }, 6740 { { "g1" }, "r1" }, 6741 { { "g2" }, "r2" }, 6742 { { "g3" }, "r3" }, 6743 { { "g4" }, "r4" }, 6744 { { "g5" }, "r5" }, 6745 { { "g6" }, "r6" }, 6746 { { "g7" }, "r7" }, 6747 { { "o0" }, "r8" }, 6748 { { "o1" }, "r9" }, 6749 { { "o2" }, "r10" }, 6750 { { "o3" }, "r11" }, 6751 { { "o4" }, "r12" }, 6752 { { "o5" }, "r13" }, 6753 { { "o6", "sp" }, "r14" }, 6754 { { "o7" }, "r15" }, 6755 { { "l0" }, "r16" }, 6756 { { "l1" }, "r17" }, 6757 { { "l2" }, "r18" }, 6758 { { "l3" }, "r19" }, 6759 { { "l4" }, "r20" }, 6760 { { "l5" }, "r21" }, 6761 { { "l6" }, "r22" }, 6762 { { "l7" }, "r23" }, 6763 { { "i0" }, "r24" }, 6764 { { "i1" }, "r25" }, 6765 { { "i2" }, "r26" }, 6766 { { "i3" }, "r27" }, 6767 { { "i4" }, "r28" }, 6768 { { "i5" }, "r29" }, 6769 { { "i6", "fp" }, "r30" }, 6770 { { "i7" }, "r31" }, 6771 }; 6772 6773 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6774 return llvm::makeArrayRef(GCCRegAliases); 6775 } 6776 6777 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6778 class SparcV8TargetInfo : public SparcTargetInfo { 6779 public: 6780 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6781 : SparcTargetInfo(Triple, Opts) { 6782 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6783 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6784 switch (getTriple().getOS()) { 6785 default: 6786 SizeType = UnsignedInt; 6787 IntPtrType = SignedInt; 6788 PtrDiffType = SignedInt; 6789 break; 6790 case llvm::Triple::NetBSD: 6791 case llvm::Triple::OpenBSD: 6792 SizeType = UnsignedLong; 6793 IntPtrType = SignedLong; 6794 PtrDiffType = SignedLong; 6795 break; 6796 } 6797 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6798 } 6799 6800 void getTargetDefines(const LangOptions &Opts, 6801 MacroBuilder &Builder) const override { 6802 SparcTargetInfo::getTargetDefines(Opts, Builder); 6803 switch (getCPUGeneration(CPU)) { 6804 case CG_V8: 6805 Builder.defineMacro("__sparcv8"); 6806 if (getTriple().getOS() != llvm::Triple::Solaris) 6807 Builder.defineMacro("__sparcv8__"); 6808 break; 6809 case CG_V9: 6810 Builder.defineMacro("__sparcv9"); 6811 if (getTriple().getOS() != llvm::Triple::Solaris) { 6812 Builder.defineMacro("__sparcv9__"); 6813 Builder.defineMacro("__sparc_v9__"); 6814 } 6815 break; 6816 } 6817 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6818 std::string MyriadArchValue, Myriad2Value; 6819 Builder.defineMacro("__sparc_v8__"); 6820 Builder.defineMacro("__leon__"); 6821 switch (CPU) { 6822 case CK_MYRIAD2150: 6823 MyriadArchValue = "__ma2150"; 6824 Myriad2Value = "2"; 6825 break; 6826 case CK_MYRIAD2450: 6827 MyriadArchValue = "__ma2450"; 6828 Myriad2Value = "2"; 6829 break; 6830 default: 6831 MyriadArchValue = "__ma2100"; 6832 Myriad2Value = "1"; 6833 break; 6834 } 6835 Builder.defineMacro(MyriadArchValue, "1"); 6836 Builder.defineMacro(MyriadArchValue+"__", "1"); 6837 Builder.defineMacro("__myriad2__", Myriad2Value); 6838 Builder.defineMacro("__myriad2", Myriad2Value); 6839 } 6840 } 6841 6842 bool hasSjLjLowering() const override { 6843 return true; 6844 } 6845 }; 6846 6847 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6848 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6849 public: 6850 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6851 : SparcV8TargetInfo(Triple, Opts) { 6852 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6853 } 6854 }; 6855 6856 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6857 class SparcV9TargetInfo : public SparcTargetInfo { 6858 public: 6859 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6860 : SparcTargetInfo(Triple, Opts) { 6861 // FIXME: Support Sparc quad-precision long double? 6862 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6863 // This is an LP64 platform. 6864 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6865 6866 // OpenBSD uses long long for int64_t and intmax_t. 6867 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6868 IntMaxType = SignedLongLong; 6869 else 6870 IntMaxType = SignedLong; 6871 Int64Type = IntMaxType; 6872 6873 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6874 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6875 LongDoubleWidth = 128; 6876 LongDoubleAlign = 128; 6877 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6878 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6879 } 6880 6881 void getTargetDefines(const LangOptions &Opts, 6882 MacroBuilder &Builder) const override { 6883 SparcTargetInfo::getTargetDefines(Opts, Builder); 6884 Builder.defineMacro("__sparcv9"); 6885 Builder.defineMacro("__arch64__"); 6886 // Solaris doesn't need these variants, but the BSDs do. 6887 if (getTriple().getOS() != llvm::Triple::Solaris) { 6888 Builder.defineMacro("__sparc64__"); 6889 Builder.defineMacro("__sparc_v9__"); 6890 Builder.defineMacro("__sparcv9__"); 6891 } 6892 } 6893 6894 bool setCPU(const std::string &Name) override { 6895 if (!SparcTargetInfo::setCPU(Name)) 6896 return false; 6897 return getCPUGeneration(CPU) == CG_V9; 6898 } 6899 }; 6900 6901 class SystemZTargetInfo : public TargetInfo { 6902 static const Builtin::Info BuiltinInfo[]; 6903 static const char *const GCCRegNames[]; 6904 std::string CPU; 6905 bool HasTransactionalExecution; 6906 bool HasVector; 6907 6908 public: 6909 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6910 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6911 HasVector(false) { 6912 IntMaxType = SignedLong; 6913 Int64Type = SignedLong; 6914 TLSSupported = true; 6915 IntWidth = IntAlign = 32; 6916 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6917 PointerWidth = PointerAlign = 64; 6918 LongDoubleWidth = 128; 6919 LongDoubleAlign = 64; 6920 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6921 DefaultAlignForAttributeAligned = 64; 6922 MinGlobalAlign = 16; 6923 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6924 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6925 } 6926 void getTargetDefines(const LangOptions &Opts, 6927 MacroBuilder &Builder) const override { 6928 Builder.defineMacro("__s390__"); 6929 Builder.defineMacro("__s390x__"); 6930 Builder.defineMacro("__zarch__"); 6931 Builder.defineMacro("__LONG_DOUBLE_128__"); 6932 6933 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6934 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6935 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6936 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6937 6938 if (HasTransactionalExecution) 6939 Builder.defineMacro("__HTM__"); 6940 if (Opts.ZVector) 6941 Builder.defineMacro("__VEC__", "10301"); 6942 } 6943 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6944 return llvm::makeArrayRef(BuiltinInfo, 6945 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6946 } 6947 6948 ArrayRef<const char *> getGCCRegNames() const override; 6949 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6950 // No aliases. 6951 return None; 6952 } 6953 bool validateAsmConstraint(const char *&Name, 6954 TargetInfo::ConstraintInfo &info) const override; 6955 const char *getClobbers() const override { 6956 // FIXME: Is this really right? 6957 return ""; 6958 } 6959 BuiltinVaListKind getBuiltinVaListKind() const override { 6960 return TargetInfo::SystemZBuiltinVaList; 6961 } 6962 bool setCPU(const std::string &Name) override { 6963 CPU = Name; 6964 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6965 .Case("z10", true) 6966 .Case("arch8", true) 6967 .Case("z196", true) 6968 .Case("arch9", true) 6969 .Case("zEC12", true) 6970 .Case("arch10", true) 6971 .Case("z13", true) 6972 .Case("arch11", true) 6973 .Default(false); 6974 6975 return CPUKnown; 6976 } 6977 bool 6978 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6979 StringRef CPU, 6980 const std::vector<std::string> &FeaturesVec) const override { 6981 if (CPU == "zEC12" || CPU == "arch10") 6982 Features["transactional-execution"] = true; 6983 if (CPU == "z13" || CPU == "arch11") { 6984 Features["transactional-execution"] = true; 6985 Features["vector"] = true; 6986 } 6987 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6988 } 6989 6990 bool handleTargetFeatures(std::vector<std::string> &Features, 6991 DiagnosticsEngine &Diags) override { 6992 HasTransactionalExecution = false; 6993 for (const auto &Feature : Features) { 6994 if (Feature == "+transactional-execution") 6995 HasTransactionalExecution = true; 6996 else if (Feature == "+vector") 6997 HasVector = true; 6998 } 6999 // If we use the vector ABI, vector types are 64-bit aligned. 7000 if (HasVector) { 7001 MaxVectorAlign = 64; 7002 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7003 "-v128:64-a:8:16-n32:64"); 7004 } 7005 return true; 7006 } 7007 7008 bool hasFeature(StringRef Feature) const override { 7009 return llvm::StringSwitch<bool>(Feature) 7010 .Case("systemz", true) 7011 .Case("htm", HasTransactionalExecution) 7012 .Case("vx", HasVector) 7013 .Default(false); 7014 } 7015 7016 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7017 switch (CC) { 7018 case CC_C: 7019 case CC_Swift: 7020 return CCCR_OK; 7021 default: 7022 return CCCR_Warning; 7023 } 7024 } 7025 7026 StringRef getABI() const override { 7027 if (HasVector) 7028 return "vector"; 7029 return ""; 7030 } 7031 7032 bool useFloat128ManglingForLongDouble() const override { 7033 return true; 7034 } 7035 }; 7036 7037 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7038 #define BUILTIN(ID, TYPE, ATTRS) \ 7039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7040 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7041 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7042 #include "clang/Basic/BuiltinsSystemZ.def" 7043 }; 7044 7045 const char *const SystemZTargetInfo::GCCRegNames[] = { 7046 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7047 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7048 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7049 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7050 }; 7051 7052 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7053 return llvm::makeArrayRef(GCCRegNames); 7054 } 7055 7056 bool SystemZTargetInfo:: 7057 validateAsmConstraint(const char *&Name, 7058 TargetInfo::ConstraintInfo &Info) const { 7059 switch (*Name) { 7060 default: 7061 return false; 7062 7063 case 'a': // Address register 7064 case 'd': // Data register (equivalent to 'r') 7065 case 'f': // Floating-point register 7066 Info.setAllowsRegister(); 7067 return true; 7068 7069 case 'I': // Unsigned 8-bit constant 7070 case 'J': // Unsigned 12-bit constant 7071 case 'K': // Signed 16-bit constant 7072 case 'L': // Signed 20-bit displacement (on all targets we support) 7073 case 'M': // 0x7fffffff 7074 return true; 7075 7076 case 'Q': // Memory with base and unsigned 12-bit displacement 7077 case 'R': // Likewise, plus an index 7078 case 'S': // Memory with base and signed 20-bit displacement 7079 case 'T': // Likewise, plus an index 7080 Info.setAllowsMemory(); 7081 return true; 7082 } 7083 } 7084 7085 class MSP430TargetInfo : public TargetInfo { 7086 static const char *const GCCRegNames[]; 7087 7088 public: 7089 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7090 : TargetInfo(Triple) { 7091 TLSSupported = false; 7092 IntWidth = 16; 7093 IntAlign = 16; 7094 LongWidth = 32; 7095 LongLongWidth = 64; 7096 LongAlign = LongLongAlign = 16; 7097 PointerWidth = 16; 7098 PointerAlign = 16; 7099 SuitableAlign = 16; 7100 SizeType = UnsignedInt; 7101 IntMaxType = SignedLongLong; 7102 IntPtrType = SignedInt; 7103 PtrDiffType = SignedInt; 7104 SigAtomicType = SignedLong; 7105 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7106 } 7107 void getTargetDefines(const LangOptions &Opts, 7108 MacroBuilder &Builder) const override { 7109 Builder.defineMacro("MSP430"); 7110 Builder.defineMacro("__MSP430__"); 7111 // FIXME: defines for different 'flavours' of MCU 7112 } 7113 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7114 // FIXME: Implement. 7115 return None; 7116 } 7117 bool hasFeature(StringRef Feature) const override { 7118 return Feature == "msp430"; 7119 } 7120 ArrayRef<const char *> getGCCRegNames() const override; 7121 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7122 // No aliases. 7123 return None; 7124 } 7125 bool validateAsmConstraint(const char *&Name, 7126 TargetInfo::ConstraintInfo &info) const override { 7127 // FIXME: implement 7128 switch (*Name) { 7129 case 'K': // the constant 1 7130 case 'L': // constant -1^20 .. 1^19 7131 case 'M': // constant 1-4: 7132 return true; 7133 } 7134 // No target constraints for now. 7135 return false; 7136 } 7137 const char *getClobbers() const override { 7138 // FIXME: Is this really right? 7139 return ""; 7140 } 7141 BuiltinVaListKind getBuiltinVaListKind() const override { 7142 // FIXME: implement 7143 return TargetInfo::CharPtrBuiltinVaList; 7144 } 7145 }; 7146 7147 const char *const MSP430TargetInfo::GCCRegNames[] = { 7148 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7149 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7150 7151 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7152 return llvm::makeArrayRef(GCCRegNames); 7153 } 7154 7155 // LLVM and Clang cannot be used directly to output native binaries for 7156 // target, but is used to compile C code to llvm bitcode with correct 7157 // type and alignment information. 7158 // 7159 // TCE uses the llvm bitcode as input and uses it for generating customized 7160 // target processor and program binary. TCE co-design environment is 7161 // publicly available in http://tce.cs.tut.fi 7162 7163 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7164 3, // opencl_global 7165 4, // opencl_local 7166 5, // opencl_constant 7167 // FIXME: generic has to be added to the target 7168 0, // opencl_generic 7169 0, // cuda_device 7170 0, // cuda_constant 7171 0 // cuda_shared 7172 }; 7173 7174 class TCETargetInfo : public TargetInfo { 7175 public: 7176 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7177 : TargetInfo(Triple) { 7178 TLSSupported = false; 7179 IntWidth = 32; 7180 LongWidth = LongLongWidth = 32; 7181 PointerWidth = 32; 7182 IntAlign = 32; 7183 LongAlign = LongLongAlign = 32; 7184 PointerAlign = 32; 7185 SuitableAlign = 32; 7186 SizeType = UnsignedInt; 7187 IntMaxType = SignedLong; 7188 IntPtrType = SignedInt; 7189 PtrDiffType = SignedInt; 7190 FloatWidth = 32; 7191 FloatAlign = 32; 7192 DoubleWidth = 32; 7193 DoubleAlign = 32; 7194 LongDoubleWidth = 32; 7195 LongDoubleAlign = 32; 7196 FloatFormat = &llvm::APFloat::IEEEsingle; 7197 DoubleFormat = &llvm::APFloat::IEEEsingle; 7198 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7199 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7200 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7201 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7202 UseAddrSpaceMapMangling = true; 7203 } 7204 7205 void getTargetDefines(const LangOptions &Opts, 7206 MacroBuilder &Builder) const override { 7207 DefineStd(Builder, "tce", Opts); 7208 Builder.defineMacro("__TCE__"); 7209 Builder.defineMacro("__TCE_V1__"); 7210 } 7211 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7212 7213 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7214 const char *getClobbers() const override { return ""; } 7215 BuiltinVaListKind getBuiltinVaListKind() const override { 7216 return TargetInfo::VoidPtrBuiltinVaList; 7217 } 7218 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7219 bool validateAsmConstraint(const char *&Name, 7220 TargetInfo::ConstraintInfo &info) const override { 7221 return true; 7222 } 7223 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7224 return None; 7225 } 7226 }; 7227 7228 class BPFTargetInfo : public TargetInfo { 7229 public: 7230 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7231 : TargetInfo(Triple) { 7232 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7233 SizeType = UnsignedLong; 7234 PtrDiffType = SignedLong; 7235 IntPtrType = SignedLong; 7236 IntMaxType = SignedLong; 7237 Int64Type = SignedLong; 7238 RegParmMax = 5; 7239 if (Triple.getArch() == llvm::Triple::bpfeb) { 7240 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7241 } else { 7242 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7243 } 7244 MaxAtomicPromoteWidth = 64; 7245 MaxAtomicInlineWidth = 64; 7246 TLSSupported = false; 7247 } 7248 void getTargetDefines(const LangOptions &Opts, 7249 MacroBuilder &Builder) const override { 7250 DefineStd(Builder, "bpf", Opts); 7251 Builder.defineMacro("__BPF__"); 7252 } 7253 bool hasFeature(StringRef Feature) const override { 7254 return Feature == "bpf"; 7255 } 7256 7257 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7258 const char *getClobbers() const override { 7259 return ""; 7260 } 7261 BuiltinVaListKind getBuiltinVaListKind() const override { 7262 return TargetInfo::VoidPtrBuiltinVaList; 7263 } 7264 ArrayRef<const char *> getGCCRegNames() const override { 7265 return None; 7266 } 7267 bool validateAsmConstraint(const char *&Name, 7268 TargetInfo::ConstraintInfo &info) const override { 7269 return true; 7270 } 7271 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7272 return None; 7273 } 7274 }; 7275 7276 class MipsTargetInfo : public TargetInfo { 7277 void setDataLayout() { 7278 StringRef Layout; 7279 7280 if (ABI == "o32") 7281 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7282 else if (ABI == "n32") 7283 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7284 else if (ABI == "n64") 7285 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7286 else 7287 llvm_unreachable("Invalid ABI"); 7288 7289 if (BigEndian) 7290 resetDataLayout(("E-" + Layout).str()); 7291 else 7292 resetDataLayout(("e-" + Layout).str()); 7293 } 7294 7295 7296 static const Builtin::Info BuiltinInfo[]; 7297 std::string CPU; 7298 bool IsMips16; 7299 bool IsMicromips; 7300 bool IsNan2008; 7301 bool IsSingleFloat; 7302 enum MipsFloatABI { 7303 HardFloat, SoftFloat 7304 } FloatABI; 7305 enum DspRevEnum { 7306 NoDSP, DSP1, DSP2 7307 } DspRev; 7308 bool HasMSA; 7309 7310 protected: 7311 bool HasFP64; 7312 std::string ABI; 7313 7314 public: 7315 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7316 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7317 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7318 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7319 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7320 7321 setABI((getTriple().getArch() == llvm::Triple::mips || 7322 getTriple().getArch() == llvm::Triple::mipsel) 7323 ? "o32" 7324 : "n64"); 7325 7326 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7327 } 7328 7329 bool isNaN2008Default() const { 7330 return CPU == "mips32r6" || CPU == "mips64r6"; 7331 } 7332 7333 bool isFP64Default() const { 7334 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7335 } 7336 7337 bool isNan2008() const override { 7338 return IsNan2008; 7339 } 7340 7341 bool processorSupportsGPR64() const { 7342 return llvm::StringSwitch<bool>(CPU) 7343 .Case("mips3", true) 7344 .Case("mips4", true) 7345 .Case("mips5", true) 7346 .Case("mips64", true) 7347 .Case("mips64r2", true) 7348 .Case("mips64r3", true) 7349 .Case("mips64r5", true) 7350 .Case("mips64r6", true) 7351 .Case("octeon", true) 7352 .Default(false); 7353 return false; 7354 } 7355 7356 StringRef getABI() const override { return ABI; } 7357 bool setABI(const std::string &Name) override { 7358 if (Name == "o32") { 7359 setO32ABITypes(); 7360 ABI = Name; 7361 return true; 7362 } 7363 7364 if (Name == "n32") { 7365 setN32ABITypes(); 7366 ABI = Name; 7367 return true; 7368 } 7369 if (Name == "n64") { 7370 setN64ABITypes(); 7371 ABI = Name; 7372 return true; 7373 } 7374 return false; 7375 } 7376 7377 void setO32ABITypes() { 7378 Int64Type = SignedLongLong; 7379 IntMaxType = Int64Type; 7380 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7381 LongDoubleWidth = LongDoubleAlign = 64; 7382 LongWidth = LongAlign = 32; 7383 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7384 PointerWidth = PointerAlign = 32; 7385 PtrDiffType = SignedInt; 7386 SizeType = UnsignedInt; 7387 SuitableAlign = 64; 7388 } 7389 7390 void setN32N64ABITypes() { 7391 LongDoubleWidth = LongDoubleAlign = 128; 7392 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7393 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7394 LongDoubleWidth = LongDoubleAlign = 64; 7395 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7396 } 7397 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7398 SuitableAlign = 128; 7399 } 7400 7401 void setN64ABITypes() { 7402 setN32N64ABITypes(); 7403 Int64Type = SignedLong; 7404 IntMaxType = Int64Type; 7405 LongWidth = LongAlign = 64; 7406 PointerWidth = PointerAlign = 64; 7407 PtrDiffType = SignedLong; 7408 SizeType = UnsignedLong; 7409 } 7410 7411 void setN32ABITypes() { 7412 setN32N64ABITypes(); 7413 Int64Type = SignedLongLong; 7414 IntMaxType = Int64Type; 7415 LongWidth = LongAlign = 32; 7416 PointerWidth = PointerAlign = 32; 7417 PtrDiffType = SignedInt; 7418 SizeType = UnsignedInt; 7419 } 7420 7421 bool setCPU(const std::string &Name) override { 7422 CPU = Name; 7423 return llvm::StringSwitch<bool>(Name) 7424 .Case("mips1", true) 7425 .Case("mips2", true) 7426 .Case("mips3", true) 7427 .Case("mips4", true) 7428 .Case("mips5", true) 7429 .Case("mips32", true) 7430 .Case("mips32r2", true) 7431 .Case("mips32r3", true) 7432 .Case("mips32r5", true) 7433 .Case("mips32r6", true) 7434 .Case("mips64", true) 7435 .Case("mips64r2", true) 7436 .Case("mips64r3", true) 7437 .Case("mips64r5", true) 7438 .Case("mips64r6", true) 7439 .Case("octeon", true) 7440 .Case("p5600", true) 7441 .Default(false); 7442 } 7443 const std::string& getCPU() const { return CPU; } 7444 bool 7445 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7446 StringRef CPU, 7447 const std::vector<std::string> &FeaturesVec) const override { 7448 if (CPU.empty()) 7449 CPU = getCPU(); 7450 if (CPU == "octeon") 7451 Features["mips64r2"] = Features["cnmips"] = true; 7452 else 7453 Features[CPU] = true; 7454 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7455 } 7456 7457 void getTargetDefines(const LangOptions &Opts, 7458 MacroBuilder &Builder) const override { 7459 if (BigEndian) { 7460 DefineStd(Builder, "MIPSEB", Opts); 7461 Builder.defineMacro("_MIPSEB"); 7462 } else { 7463 DefineStd(Builder, "MIPSEL", Opts); 7464 Builder.defineMacro("_MIPSEL"); 7465 } 7466 7467 Builder.defineMacro("__mips__"); 7468 Builder.defineMacro("_mips"); 7469 if (Opts.GNUMode) 7470 Builder.defineMacro("mips"); 7471 7472 if (ABI == "o32") { 7473 Builder.defineMacro("__mips", "32"); 7474 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7475 } else { 7476 Builder.defineMacro("__mips", "64"); 7477 Builder.defineMacro("__mips64"); 7478 Builder.defineMacro("__mips64__"); 7479 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7480 } 7481 7482 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7483 .Cases("mips32", "mips64", "1") 7484 .Cases("mips32r2", "mips64r2", "2") 7485 .Cases("mips32r3", "mips64r3", "3") 7486 .Cases("mips32r5", "mips64r5", "5") 7487 .Cases("mips32r6", "mips64r6", "6") 7488 .Default(""); 7489 if (!ISARev.empty()) 7490 Builder.defineMacro("__mips_isa_rev", ISARev); 7491 7492 if (ABI == "o32") { 7493 Builder.defineMacro("__mips_o32"); 7494 Builder.defineMacro("_ABIO32", "1"); 7495 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7496 } else if (ABI == "n32") { 7497 Builder.defineMacro("__mips_n32"); 7498 Builder.defineMacro("_ABIN32", "2"); 7499 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7500 } else if (ABI == "n64") { 7501 Builder.defineMacro("__mips_n64"); 7502 Builder.defineMacro("_ABI64", "3"); 7503 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7504 } else 7505 llvm_unreachable("Invalid ABI."); 7506 7507 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7508 7509 switch (FloatABI) { 7510 case HardFloat: 7511 Builder.defineMacro("__mips_hard_float", Twine(1)); 7512 break; 7513 case SoftFloat: 7514 Builder.defineMacro("__mips_soft_float", Twine(1)); 7515 break; 7516 } 7517 7518 if (IsSingleFloat) 7519 Builder.defineMacro("__mips_single_float", Twine(1)); 7520 7521 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7522 Builder.defineMacro("_MIPS_FPSET", 7523 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7524 7525 if (IsMips16) 7526 Builder.defineMacro("__mips16", Twine(1)); 7527 7528 if (IsMicromips) 7529 Builder.defineMacro("__mips_micromips", Twine(1)); 7530 7531 if (IsNan2008) 7532 Builder.defineMacro("__mips_nan2008", Twine(1)); 7533 7534 switch (DspRev) { 7535 default: 7536 break; 7537 case DSP1: 7538 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7539 Builder.defineMacro("__mips_dsp", Twine(1)); 7540 break; 7541 case DSP2: 7542 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7543 Builder.defineMacro("__mips_dspr2", Twine(1)); 7544 Builder.defineMacro("__mips_dsp", Twine(1)); 7545 break; 7546 } 7547 7548 if (HasMSA) 7549 Builder.defineMacro("__mips_msa", Twine(1)); 7550 7551 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7552 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7553 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7554 7555 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7556 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7557 7558 // These shouldn't be defined for MIPS-I but there's no need to check 7559 // for that since MIPS-I isn't supported. 7560 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7561 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7562 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7563 7564 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7565 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7566 // the instructions exist but using them violates the ABI since they 7567 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7568 if (ABI == "n32" || ABI == "n64") 7569 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7570 } 7571 7572 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7573 return llvm::makeArrayRef(BuiltinInfo, 7574 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7575 } 7576 bool hasFeature(StringRef Feature) const override { 7577 return llvm::StringSwitch<bool>(Feature) 7578 .Case("mips", true) 7579 .Case("fp64", HasFP64) 7580 .Default(false); 7581 } 7582 BuiltinVaListKind getBuiltinVaListKind() const override { 7583 return TargetInfo::VoidPtrBuiltinVaList; 7584 } 7585 ArrayRef<const char *> getGCCRegNames() const override { 7586 static const char *const GCCRegNames[] = { 7587 // CPU register names 7588 // Must match second column of GCCRegAliases 7589 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7590 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7591 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7592 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7593 // Floating point register names 7594 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7595 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7596 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7597 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7598 // Hi/lo and condition register names 7599 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7600 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7601 "$ac3hi","$ac3lo", 7602 // MSA register names 7603 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7604 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7605 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7606 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7607 // MSA control register names 7608 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7609 "$msarequest", "$msamap", "$msaunmap" 7610 }; 7611 return llvm::makeArrayRef(GCCRegNames); 7612 } 7613 bool validateAsmConstraint(const char *&Name, 7614 TargetInfo::ConstraintInfo &Info) const override { 7615 switch (*Name) { 7616 default: 7617 return false; 7618 case 'r': // CPU registers. 7619 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7620 case 'y': // Equivalent to "r", backward compatibility only. 7621 case 'f': // floating-point registers. 7622 case 'c': // $25 for indirect jumps 7623 case 'l': // lo register 7624 case 'x': // hilo register pair 7625 Info.setAllowsRegister(); 7626 return true; 7627 case 'I': // Signed 16-bit constant 7628 case 'J': // Integer 0 7629 case 'K': // Unsigned 16-bit constant 7630 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7631 case 'M': // Constants not loadable via lui, addiu, or ori 7632 case 'N': // Constant -1 to -65535 7633 case 'O': // A signed 15-bit constant 7634 case 'P': // A constant between 1 go 65535 7635 return true; 7636 case 'R': // An address that can be used in a non-macro load or store 7637 Info.setAllowsMemory(); 7638 return true; 7639 case 'Z': 7640 if (Name[1] == 'C') { // An address usable by ll, and sc. 7641 Info.setAllowsMemory(); 7642 Name++; // Skip over 'Z'. 7643 return true; 7644 } 7645 return false; 7646 } 7647 } 7648 7649 std::string convertConstraint(const char *&Constraint) const override { 7650 std::string R; 7651 switch (*Constraint) { 7652 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7653 if (Constraint[1] == 'C') { 7654 R = std::string("^") + std::string(Constraint, 2); 7655 Constraint++; 7656 return R; 7657 } 7658 break; 7659 } 7660 return TargetInfo::convertConstraint(Constraint); 7661 } 7662 7663 const char *getClobbers() const override { 7664 // In GCC, $1 is not widely used in generated code (it's used only in a few 7665 // specific situations), so there is no real need for users to add it to 7666 // the clobbers list if they want to use it in their inline assembly code. 7667 // 7668 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7669 // code generation, so using it in inline assembly without adding it to the 7670 // clobbers list can cause conflicts between the inline assembly code and 7671 // the surrounding generated code. 7672 // 7673 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7674 // operands, which will conflict with the ".set at" assembler option (which 7675 // we use only for inline assembly, in order to maintain compatibility with 7676 // GCC) and will also conflict with the user's usage of $1. 7677 // 7678 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7679 // register for generated code is to automatically clobber $1 for all inline 7680 // assembly code. 7681 // 7682 // FIXME: We should automatically clobber $1 only for inline assembly code 7683 // which actually uses it. This would allow LLVM to use $1 for inline 7684 // assembly operands if the user's assembly code doesn't use it. 7685 return "~{$1}"; 7686 } 7687 7688 bool handleTargetFeatures(std::vector<std::string> &Features, 7689 DiagnosticsEngine &Diags) override { 7690 IsMips16 = false; 7691 IsMicromips = false; 7692 IsNan2008 = isNaN2008Default(); 7693 IsSingleFloat = false; 7694 FloatABI = HardFloat; 7695 DspRev = NoDSP; 7696 HasFP64 = isFP64Default(); 7697 7698 for (const auto &Feature : Features) { 7699 if (Feature == "+single-float") 7700 IsSingleFloat = true; 7701 else if (Feature == "+soft-float") 7702 FloatABI = SoftFloat; 7703 else if (Feature == "+mips16") 7704 IsMips16 = true; 7705 else if (Feature == "+micromips") 7706 IsMicromips = true; 7707 else if (Feature == "+dsp") 7708 DspRev = std::max(DspRev, DSP1); 7709 else if (Feature == "+dspr2") 7710 DspRev = std::max(DspRev, DSP2); 7711 else if (Feature == "+msa") 7712 HasMSA = true; 7713 else if (Feature == "+fp64") 7714 HasFP64 = true; 7715 else if (Feature == "-fp64") 7716 HasFP64 = false; 7717 else if (Feature == "+nan2008") 7718 IsNan2008 = true; 7719 else if (Feature == "-nan2008") 7720 IsNan2008 = false; 7721 } 7722 7723 setDataLayout(); 7724 7725 return true; 7726 } 7727 7728 int getEHDataRegisterNumber(unsigned RegNo) const override { 7729 if (RegNo == 0) return 4; 7730 if (RegNo == 1) return 5; 7731 return -1; 7732 } 7733 7734 bool isCLZForZeroUndef() const override { return false; } 7735 7736 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7737 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7738 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7739 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7740 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7741 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7742 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7743 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7744 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7745 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7746 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7747 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7748 {{"ra"}, "$31"}}; 7749 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7750 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7751 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7752 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7753 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7754 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7755 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7756 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7757 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7758 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7759 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7760 {{"ra"}, "$31"}}; 7761 if (ABI == "o32") 7762 return llvm::makeArrayRef(O32RegAliases); 7763 return llvm::makeArrayRef(NewABIRegAliases); 7764 } 7765 7766 bool hasInt128Type() const override { 7767 return ABI == "n32" || ABI == "n64"; 7768 } 7769 7770 bool validateTarget(DiagnosticsEngine &Diags) const override { 7771 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7772 // this yet. It's better to fail here than on the backend assertion. 7773 if (processorSupportsGPR64() && ABI == "o32") { 7774 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7775 return false; 7776 } 7777 7778 // 64-bit ABI's require 64-bit CPU's. 7779 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7780 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7781 return false; 7782 } 7783 7784 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7785 // can't handle this yet. It's better to fail here than on the 7786 // backend assertion. 7787 if ((getTriple().getArch() == llvm::Triple::mips64 || 7788 getTriple().getArch() == llvm::Triple::mips64el) && 7789 ABI == "o32") { 7790 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7791 << ABI << getTriple().str(); 7792 return false; 7793 } 7794 7795 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7796 // can't handle this yet. It's better to fail here than on the 7797 // backend assertion. 7798 if ((getTriple().getArch() == llvm::Triple::mips || 7799 getTriple().getArch() == llvm::Triple::mipsel) && 7800 (ABI == "n32" || ABI == "n64")) { 7801 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7802 << ABI << getTriple().str(); 7803 return false; 7804 } 7805 7806 return true; 7807 } 7808 }; 7809 7810 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7811 #define BUILTIN(ID, TYPE, ATTRS) \ 7812 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7813 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7814 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7815 #include "clang/Basic/BuiltinsMips.def" 7816 }; 7817 7818 class PNaClTargetInfo : public TargetInfo { 7819 public: 7820 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7821 : TargetInfo(Triple) { 7822 this->LongAlign = 32; 7823 this->LongWidth = 32; 7824 this->PointerAlign = 32; 7825 this->PointerWidth = 32; 7826 this->IntMaxType = TargetInfo::SignedLongLong; 7827 this->Int64Type = TargetInfo::SignedLongLong; 7828 this->DoubleAlign = 64; 7829 this->LongDoubleWidth = 64; 7830 this->LongDoubleAlign = 64; 7831 this->SizeType = TargetInfo::UnsignedInt; 7832 this->PtrDiffType = TargetInfo::SignedInt; 7833 this->IntPtrType = TargetInfo::SignedInt; 7834 this->RegParmMax = 0; // Disallow regparm 7835 } 7836 7837 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7838 Builder.defineMacro("__le32__"); 7839 Builder.defineMacro("__pnacl__"); 7840 } 7841 void getTargetDefines(const LangOptions &Opts, 7842 MacroBuilder &Builder) const override { 7843 getArchDefines(Opts, Builder); 7844 } 7845 bool hasFeature(StringRef Feature) const override { 7846 return Feature == "pnacl"; 7847 } 7848 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7849 BuiltinVaListKind getBuiltinVaListKind() const override { 7850 return TargetInfo::PNaClABIBuiltinVaList; 7851 } 7852 ArrayRef<const char *> getGCCRegNames() const override; 7853 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7854 bool validateAsmConstraint(const char *&Name, 7855 TargetInfo::ConstraintInfo &Info) const override { 7856 return false; 7857 } 7858 7859 const char *getClobbers() const override { 7860 return ""; 7861 } 7862 }; 7863 7864 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7865 return None; 7866 } 7867 7868 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7869 return None; 7870 } 7871 7872 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7873 class NaClMips32TargetInfo : public MipsTargetInfo { 7874 public: 7875 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7876 : MipsTargetInfo(Triple, Opts) {} 7877 7878 BuiltinVaListKind getBuiltinVaListKind() const override { 7879 return TargetInfo::PNaClABIBuiltinVaList; 7880 } 7881 }; 7882 7883 class Le64TargetInfo : public TargetInfo { 7884 static const Builtin::Info BuiltinInfo[]; 7885 7886 public: 7887 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7888 : TargetInfo(Triple) { 7889 NoAsmVariants = true; 7890 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7891 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7892 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7893 } 7894 7895 void getTargetDefines(const LangOptions &Opts, 7896 MacroBuilder &Builder) const override { 7897 DefineStd(Builder, "unix", Opts); 7898 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7899 Builder.defineMacro("__ELF__"); 7900 } 7901 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7902 return llvm::makeArrayRef(BuiltinInfo, 7903 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7904 } 7905 BuiltinVaListKind getBuiltinVaListKind() const override { 7906 return TargetInfo::PNaClABIBuiltinVaList; 7907 } 7908 const char *getClobbers() const override { return ""; } 7909 ArrayRef<const char *> getGCCRegNames() const override { 7910 return None; 7911 } 7912 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7913 return None; 7914 } 7915 bool validateAsmConstraint(const char *&Name, 7916 TargetInfo::ConstraintInfo &Info) const override { 7917 return false; 7918 } 7919 7920 bool hasProtectedVisibility() const override { return false; } 7921 }; 7922 7923 class WebAssemblyTargetInfo : public TargetInfo { 7924 static const Builtin::Info BuiltinInfo[]; 7925 7926 enum SIMDEnum { 7927 NoSIMD, 7928 SIMD128, 7929 } SIMDLevel; 7930 7931 public: 7932 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7933 : TargetInfo(T), SIMDLevel(NoSIMD) { 7934 NoAsmVariants = true; 7935 SuitableAlign = 128; 7936 LargeArrayMinWidth = 128; 7937 LargeArrayAlign = 128; 7938 SimdDefaultAlign = 128; 7939 SigAtomicType = SignedLong; 7940 LongDoubleWidth = LongDoubleAlign = 128; 7941 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7942 SizeType = UnsignedInt; 7943 PtrDiffType = SignedInt; 7944 IntPtrType = SignedInt; 7945 } 7946 7947 protected: 7948 void getTargetDefines(const LangOptions &Opts, 7949 MacroBuilder &Builder) const override { 7950 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7951 if (SIMDLevel >= SIMD128) 7952 Builder.defineMacro("__wasm_simd128__"); 7953 } 7954 7955 private: 7956 bool 7957 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7958 StringRef CPU, 7959 const std::vector<std::string> &FeaturesVec) const override { 7960 if (CPU == "bleeding-edge") 7961 Features["simd128"] = true; 7962 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7963 } 7964 bool hasFeature(StringRef Feature) const final { 7965 return llvm::StringSwitch<bool>(Feature) 7966 .Case("simd128", SIMDLevel >= SIMD128) 7967 .Default(false); 7968 } 7969 bool handleTargetFeatures(std::vector<std::string> &Features, 7970 DiagnosticsEngine &Diags) final { 7971 for (const auto &Feature : Features) { 7972 if (Feature == "+simd128") { 7973 SIMDLevel = std::max(SIMDLevel, SIMD128); 7974 continue; 7975 } 7976 if (Feature == "-simd128") { 7977 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7978 continue; 7979 } 7980 7981 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7982 << "-target-feature"; 7983 return false; 7984 } 7985 return true; 7986 } 7987 bool setCPU(const std::string &Name) final { 7988 return llvm::StringSwitch<bool>(Name) 7989 .Case("mvp", true) 7990 .Case("bleeding-edge", true) 7991 .Case("generic", true) 7992 .Default(false); 7993 } 7994 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7995 return llvm::makeArrayRef(BuiltinInfo, 7996 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7997 } 7998 BuiltinVaListKind getBuiltinVaListKind() const final { 7999 return VoidPtrBuiltinVaList; 8000 } 8001 ArrayRef<const char *> getGCCRegNames() const final { 8002 return None; 8003 } 8004 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8005 return None; 8006 } 8007 bool 8008 validateAsmConstraint(const char *&Name, 8009 TargetInfo::ConstraintInfo &Info) const final { 8010 return false; 8011 } 8012 const char *getClobbers() const final { return ""; } 8013 bool isCLZForZeroUndef() const final { return false; } 8014 bool hasInt128Type() const final { return true; } 8015 IntType getIntTypeByWidth(unsigned BitWidth, 8016 bool IsSigned) const final { 8017 // WebAssembly prefers long long for explicitly 64-bit integers. 8018 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8019 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8020 } 8021 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8022 bool IsSigned) const final { 8023 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8024 return BitWidth == 64 8025 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8026 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8027 } 8028 }; 8029 8030 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8031 #define BUILTIN(ID, TYPE, ATTRS) \ 8032 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8033 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8034 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8035 #include "clang/Basic/BuiltinsWebAssembly.def" 8036 }; 8037 8038 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8039 public: 8040 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8041 const TargetOptions &Opts) 8042 : WebAssemblyTargetInfo(T, Opts) { 8043 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8044 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8045 } 8046 8047 protected: 8048 void getTargetDefines(const LangOptions &Opts, 8049 MacroBuilder &Builder) const override { 8050 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8051 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8052 } 8053 }; 8054 8055 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8056 public: 8057 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8058 const TargetOptions &Opts) 8059 : WebAssemblyTargetInfo(T, Opts) { 8060 LongAlign = LongWidth = 64; 8061 PointerAlign = PointerWidth = 64; 8062 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8063 SizeType = UnsignedLong; 8064 PtrDiffType = SignedLong; 8065 IntPtrType = SignedLong; 8066 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8067 } 8068 8069 protected: 8070 void getTargetDefines(const LangOptions &Opts, 8071 MacroBuilder &Builder) const override { 8072 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8073 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8074 } 8075 }; 8076 8077 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8078 #define BUILTIN(ID, TYPE, ATTRS) \ 8079 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8080 #include "clang/Basic/BuiltinsLe64.def" 8081 }; 8082 8083 static const unsigned SPIRAddrSpaceMap[] = { 8084 1, // opencl_global 8085 3, // opencl_local 8086 2, // opencl_constant 8087 4, // opencl_generic 8088 0, // cuda_device 8089 0, // cuda_constant 8090 0 // cuda_shared 8091 }; 8092 class SPIRTargetInfo : public TargetInfo { 8093 public: 8094 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8095 : TargetInfo(Triple) { 8096 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8097 "SPIR target must use unknown OS"); 8098 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8099 "SPIR target must use unknown environment type"); 8100 TLSSupported = false; 8101 LongWidth = LongAlign = 64; 8102 AddrSpaceMap = &SPIRAddrSpaceMap; 8103 UseAddrSpaceMapMangling = true; 8104 // Define available target features 8105 // These must be defined in sorted order! 8106 NoAsmVariants = true; 8107 } 8108 void getTargetDefines(const LangOptions &Opts, 8109 MacroBuilder &Builder) const override { 8110 DefineStd(Builder, "SPIR", Opts); 8111 } 8112 bool hasFeature(StringRef Feature) const override { 8113 return Feature == "spir"; 8114 } 8115 8116 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8117 const char *getClobbers() const override { return ""; } 8118 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8119 bool validateAsmConstraint(const char *&Name, 8120 TargetInfo::ConstraintInfo &info) const override { 8121 return true; 8122 } 8123 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8124 return None; 8125 } 8126 BuiltinVaListKind getBuiltinVaListKind() const override { 8127 return TargetInfo::VoidPtrBuiltinVaList; 8128 } 8129 8130 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8131 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8132 : CCCR_Warning; 8133 } 8134 8135 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8136 return CC_SpirFunction; 8137 } 8138 8139 void setSupportedOpenCLOpts() override { 8140 // Assume all OpenCL extensions and optional core features are supported 8141 // for SPIR since it is a generic target. 8142 getSupportedOpenCLOpts().setAll(); 8143 } 8144 }; 8145 8146 class SPIR32TargetInfo : public SPIRTargetInfo { 8147 public: 8148 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8149 : SPIRTargetInfo(Triple, Opts) { 8150 PointerWidth = PointerAlign = 32; 8151 SizeType = TargetInfo::UnsignedInt; 8152 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8153 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8154 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8155 } 8156 void getTargetDefines(const LangOptions &Opts, 8157 MacroBuilder &Builder) const override { 8158 DefineStd(Builder, "SPIR32", Opts); 8159 } 8160 }; 8161 8162 class SPIR64TargetInfo : public SPIRTargetInfo { 8163 public: 8164 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8165 : SPIRTargetInfo(Triple, Opts) { 8166 PointerWidth = PointerAlign = 64; 8167 SizeType = TargetInfo::UnsignedLong; 8168 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8169 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8170 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8171 } 8172 void getTargetDefines(const LangOptions &Opts, 8173 MacroBuilder &Builder) const override { 8174 DefineStd(Builder, "SPIR64", Opts); 8175 } 8176 }; 8177 8178 class XCoreTargetInfo : public TargetInfo { 8179 static const Builtin::Info BuiltinInfo[]; 8180 public: 8181 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8182 : TargetInfo(Triple) { 8183 NoAsmVariants = true; 8184 LongLongAlign = 32; 8185 SuitableAlign = 32; 8186 DoubleAlign = LongDoubleAlign = 32; 8187 SizeType = UnsignedInt; 8188 PtrDiffType = SignedInt; 8189 IntPtrType = SignedInt; 8190 WCharType = UnsignedChar; 8191 WIntType = UnsignedInt; 8192 UseZeroLengthBitfieldAlignment = true; 8193 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8194 "-f64:32-a:0:32-n32"); 8195 } 8196 void getTargetDefines(const LangOptions &Opts, 8197 MacroBuilder &Builder) const override { 8198 Builder.defineMacro("__XS1B__"); 8199 } 8200 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8201 return llvm::makeArrayRef(BuiltinInfo, 8202 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8203 } 8204 BuiltinVaListKind getBuiltinVaListKind() const override { 8205 return TargetInfo::VoidPtrBuiltinVaList; 8206 } 8207 const char *getClobbers() const override { 8208 return ""; 8209 } 8210 ArrayRef<const char *> getGCCRegNames() const override { 8211 static const char * const GCCRegNames[] = { 8212 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8213 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8214 }; 8215 return llvm::makeArrayRef(GCCRegNames); 8216 } 8217 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8218 return None; 8219 } 8220 bool validateAsmConstraint(const char *&Name, 8221 TargetInfo::ConstraintInfo &Info) const override { 8222 return false; 8223 } 8224 int getEHDataRegisterNumber(unsigned RegNo) const override { 8225 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8226 return (RegNo < 2)? RegNo : -1; 8227 } 8228 bool allowsLargerPreferedTypeAlignment() const override { 8229 return false; 8230 } 8231 }; 8232 8233 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8234 #define BUILTIN(ID, TYPE, ATTRS) \ 8235 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8236 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8237 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8238 #include "clang/Basic/BuiltinsXCore.def" 8239 }; 8240 8241 // x86_32 Android target 8242 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8243 public: 8244 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8245 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8246 SuitableAlign = 32; 8247 LongDoubleWidth = 64; 8248 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8249 } 8250 }; 8251 8252 // x86_64 Android target 8253 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8254 public: 8255 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8256 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8257 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8258 } 8259 8260 bool useFloat128ManglingForLongDouble() const override { 8261 return true; 8262 } 8263 }; 8264 8265 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8266 class RenderScript32TargetInfo : public ARMleTargetInfo { 8267 public: 8268 RenderScript32TargetInfo(const llvm::Triple &Triple, 8269 const TargetOptions &Opts) 8270 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8271 Triple.getOSName(), 8272 Triple.getEnvironmentName()), 8273 Opts) { 8274 IsRenderScriptTarget = true; 8275 LongWidth = LongAlign = 64; 8276 } 8277 void getTargetDefines(const LangOptions &Opts, 8278 MacroBuilder &Builder) const override { 8279 Builder.defineMacro("__RENDERSCRIPT__"); 8280 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8281 } 8282 }; 8283 8284 // 64-bit RenderScript is aarch64 8285 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8286 public: 8287 RenderScript64TargetInfo(const llvm::Triple &Triple, 8288 const TargetOptions &Opts) 8289 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8290 Triple.getOSName(), 8291 Triple.getEnvironmentName()), 8292 Opts) { 8293 IsRenderScriptTarget = true; 8294 } 8295 8296 void getTargetDefines(const LangOptions &Opts, 8297 MacroBuilder &Builder) const override { 8298 Builder.defineMacro("__RENDERSCRIPT__"); 8299 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8300 } 8301 }; 8302 8303 } // end anonymous namespace 8304 8305 //===----------------------------------------------------------------------===// 8306 // Driver code 8307 //===----------------------------------------------------------------------===// 8308 8309 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8310 const TargetOptions &Opts) { 8311 llvm::Triple::OSType os = Triple.getOS(); 8312 8313 switch (Triple.getArch()) { 8314 default: 8315 return nullptr; 8316 8317 case llvm::Triple::xcore: 8318 return new XCoreTargetInfo(Triple, Opts); 8319 8320 case llvm::Triple::hexagon: 8321 return new HexagonTargetInfo(Triple, Opts); 8322 8323 case llvm::Triple::lanai: 8324 return new LanaiTargetInfo(Triple, Opts); 8325 8326 case llvm::Triple::aarch64: 8327 if (Triple.isOSDarwin()) 8328 return new DarwinAArch64TargetInfo(Triple, Opts); 8329 8330 switch (os) { 8331 case llvm::Triple::CloudABI: 8332 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8333 case llvm::Triple::FreeBSD: 8334 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8335 case llvm::Triple::Fuchsia: 8336 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8337 case llvm::Triple::Linux: 8338 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8339 case llvm::Triple::NetBSD: 8340 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8341 default: 8342 return new AArch64leTargetInfo(Triple, Opts); 8343 } 8344 8345 case llvm::Triple::aarch64_be: 8346 switch (os) { 8347 case llvm::Triple::FreeBSD: 8348 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8349 case llvm::Triple::Fuchsia: 8350 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8351 case llvm::Triple::Linux: 8352 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8353 case llvm::Triple::NetBSD: 8354 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8355 default: 8356 return new AArch64beTargetInfo(Triple, Opts); 8357 } 8358 8359 case llvm::Triple::arm: 8360 case llvm::Triple::thumb: 8361 if (Triple.isOSBinFormatMachO()) 8362 return new DarwinARMTargetInfo(Triple, Opts); 8363 8364 switch (os) { 8365 case llvm::Triple::CloudABI: 8366 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8367 case llvm::Triple::Linux: 8368 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8369 case llvm::Triple::FreeBSD: 8370 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8371 case llvm::Triple::Fuchsia: 8372 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts); 8373 case llvm::Triple::NetBSD: 8374 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8375 case llvm::Triple::OpenBSD: 8376 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8377 case llvm::Triple::Bitrig: 8378 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8379 case llvm::Triple::RTEMS: 8380 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8381 case llvm::Triple::NaCl: 8382 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8383 case llvm::Triple::Win32: 8384 switch (Triple.getEnvironment()) { 8385 case llvm::Triple::Cygnus: 8386 return new CygwinARMTargetInfo(Triple, Opts); 8387 case llvm::Triple::GNU: 8388 return new MinGWARMTargetInfo(Triple, Opts); 8389 case llvm::Triple::Itanium: 8390 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8391 case llvm::Triple::MSVC: 8392 default: // Assume MSVC for unknown environments 8393 return new MicrosoftARMleTargetInfo(Triple, Opts); 8394 } 8395 default: 8396 return new ARMleTargetInfo(Triple, Opts); 8397 } 8398 8399 case llvm::Triple::armeb: 8400 case llvm::Triple::thumbeb: 8401 if (Triple.isOSDarwin()) 8402 return new DarwinARMTargetInfo(Triple, Opts); 8403 8404 switch (os) { 8405 case llvm::Triple::Linux: 8406 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8407 case llvm::Triple::FreeBSD: 8408 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8409 case llvm::Triple::Fuchsia: 8410 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8411 case llvm::Triple::NetBSD: 8412 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8413 case llvm::Triple::OpenBSD: 8414 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8415 case llvm::Triple::Bitrig: 8416 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8417 case llvm::Triple::RTEMS: 8418 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8419 case llvm::Triple::NaCl: 8420 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8421 default: 8422 return new ARMbeTargetInfo(Triple, Opts); 8423 } 8424 8425 case llvm::Triple::bpfeb: 8426 case llvm::Triple::bpfel: 8427 return new BPFTargetInfo(Triple, Opts); 8428 8429 case llvm::Triple::msp430: 8430 return new MSP430TargetInfo(Triple, Opts); 8431 8432 case llvm::Triple::mips: 8433 switch (os) { 8434 case llvm::Triple::Linux: 8435 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8436 case llvm::Triple::RTEMS: 8437 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8438 case llvm::Triple::FreeBSD: 8439 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8440 case llvm::Triple::NetBSD: 8441 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8442 default: 8443 return new MipsTargetInfo(Triple, Opts); 8444 } 8445 8446 case llvm::Triple::mipsel: 8447 switch (os) { 8448 case llvm::Triple::Linux: 8449 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8450 case llvm::Triple::RTEMS: 8451 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8452 case llvm::Triple::FreeBSD: 8453 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8454 case llvm::Triple::NetBSD: 8455 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8456 case llvm::Triple::NaCl: 8457 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8458 default: 8459 return new MipsTargetInfo(Triple, Opts); 8460 } 8461 8462 case llvm::Triple::mips64: 8463 switch (os) { 8464 case llvm::Triple::Linux: 8465 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8466 case llvm::Triple::RTEMS: 8467 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8468 case llvm::Triple::FreeBSD: 8469 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8470 case llvm::Triple::NetBSD: 8471 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8472 case llvm::Triple::OpenBSD: 8473 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8474 default: 8475 return new MipsTargetInfo(Triple, Opts); 8476 } 8477 8478 case llvm::Triple::mips64el: 8479 switch (os) { 8480 case llvm::Triple::Linux: 8481 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8482 case llvm::Triple::RTEMS: 8483 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8484 case llvm::Triple::FreeBSD: 8485 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8486 case llvm::Triple::NetBSD: 8487 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8488 case llvm::Triple::OpenBSD: 8489 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8490 default: 8491 return new MipsTargetInfo(Triple, Opts); 8492 } 8493 8494 case llvm::Triple::le32: 8495 switch (os) { 8496 case llvm::Triple::NaCl: 8497 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8498 default: 8499 return nullptr; 8500 } 8501 8502 case llvm::Triple::le64: 8503 return new Le64TargetInfo(Triple, Opts); 8504 8505 case llvm::Triple::ppc: 8506 if (Triple.isOSDarwin()) 8507 return new DarwinPPC32TargetInfo(Triple, Opts); 8508 switch (os) { 8509 case llvm::Triple::Linux: 8510 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8511 case llvm::Triple::FreeBSD: 8512 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8513 case llvm::Triple::NetBSD: 8514 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8515 case llvm::Triple::OpenBSD: 8516 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8517 case llvm::Triple::RTEMS: 8518 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8519 default: 8520 return new PPC32TargetInfo(Triple, Opts); 8521 } 8522 8523 case llvm::Triple::ppc64: 8524 if (Triple.isOSDarwin()) 8525 return new DarwinPPC64TargetInfo(Triple, Opts); 8526 switch (os) { 8527 case llvm::Triple::Linux: 8528 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8529 case llvm::Triple::Lv2: 8530 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8531 case llvm::Triple::FreeBSD: 8532 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8533 case llvm::Triple::NetBSD: 8534 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8535 default: 8536 return new PPC64TargetInfo(Triple, Opts); 8537 } 8538 8539 case llvm::Triple::ppc64le: 8540 switch (os) { 8541 case llvm::Triple::Linux: 8542 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8543 case llvm::Triple::NetBSD: 8544 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8545 default: 8546 return new PPC64TargetInfo(Triple, Opts); 8547 } 8548 8549 case llvm::Triple::nvptx: 8550 return new NVPTX32TargetInfo(Triple, Opts); 8551 case llvm::Triple::nvptx64: 8552 return new NVPTX64TargetInfo(Triple, Opts); 8553 8554 case llvm::Triple::amdgcn: 8555 case llvm::Triple::r600: 8556 return new AMDGPUTargetInfo(Triple, Opts); 8557 8558 case llvm::Triple::sparc: 8559 switch (os) { 8560 case llvm::Triple::Linux: 8561 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8562 case llvm::Triple::Solaris: 8563 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8564 case llvm::Triple::NetBSD: 8565 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8566 case llvm::Triple::OpenBSD: 8567 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8568 case llvm::Triple::RTEMS: 8569 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8570 default: 8571 return new SparcV8TargetInfo(Triple, Opts); 8572 } 8573 8574 // The 'sparcel' architecture copies all the above cases except for Solaris. 8575 case llvm::Triple::sparcel: 8576 switch (os) { 8577 case llvm::Triple::Linux: 8578 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8579 case llvm::Triple::NetBSD: 8580 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8581 case llvm::Triple::OpenBSD: 8582 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8583 case llvm::Triple::RTEMS: 8584 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8585 default: 8586 return new SparcV8elTargetInfo(Triple, Opts); 8587 } 8588 8589 case llvm::Triple::sparcv9: 8590 switch (os) { 8591 case llvm::Triple::Linux: 8592 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8593 case llvm::Triple::Solaris: 8594 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8595 case llvm::Triple::NetBSD: 8596 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8597 case llvm::Triple::OpenBSD: 8598 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8599 case llvm::Triple::FreeBSD: 8600 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8601 default: 8602 return new SparcV9TargetInfo(Triple, Opts); 8603 } 8604 8605 case llvm::Triple::systemz: 8606 switch (os) { 8607 case llvm::Triple::Linux: 8608 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8609 default: 8610 return new SystemZTargetInfo(Triple, Opts); 8611 } 8612 8613 case llvm::Triple::tce: 8614 return new TCETargetInfo(Triple, Opts); 8615 8616 case llvm::Triple::x86: 8617 if (Triple.isOSDarwin()) 8618 return new DarwinI386TargetInfo(Triple, Opts); 8619 8620 switch (os) { 8621 case llvm::Triple::CloudABI: 8622 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8623 case llvm::Triple::Linux: { 8624 switch (Triple.getEnvironment()) { 8625 default: 8626 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8627 case llvm::Triple::Android: 8628 return new AndroidX86_32TargetInfo(Triple, Opts); 8629 } 8630 } 8631 case llvm::Triple::DragonFly: 8632 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8633 case llvm::Triple::NetBSD: 8634 return new NetBSDI386TargetInfo(Triple, Opts); 8635 case llvm::Triple::OpenBSD: 8636 return new OpenBSDI386TargetInfo(Triple, Opts); 8637 case llvm::Triple::Bitrig: 8638 return new BitrigI386TargetInfo(Triple, Opts); 8639 case llvm::Triple::FreeBSD: 8640 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8641 case llvm::Triple::Fuchsia: 8642 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts); 8643 case llvm::Triple::KFreeBSD: 8644 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8645 case llvm::Triple::Minix: 8646 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8647 case llvm::Triple::Solaris: 8648 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8649 case llvm::Triple::Win32: { 8650 switch (Triple.getEnvironment()) { 8651 case llvm::Triple::Cygnus: 8652 return new CygwinX86_32TargetInfo(Triple, Opts); 8653 case llvm::Triple::GNU: 8654 return new MinGWX86_32TargetInfo(Triple, Opts); 8655 case llvm::Triple::Itanium: 8656 case llvm::Triple::MSVC: 8657 default: // Assume MSVC for unknown environments 8658 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8659 } 8660 } 8661 case llvm::Triple::Haiku: 8662 return new HaikuX86_32TargetInfo(Triple, Opts); 8663 case llvm::Triple::RTEMS: 8664 return new RTEMSX86_32TargetInfo(Triple, Opts); 8665 case llvm::Triple::NaCl: 8666 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8667 case llvm::Triple::ELFIAMCU: 8668 return new MCUX86_32TargetInfo(Triple, Opts); 8669 default: 8670 return new X86_32TargetInfo(Triple, Opts); 8671 } 8672 8673 case llvm::Triple::x86_64: 8674 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8675 return new DarwinX86_64TargetInfo(Triple, Opts); 8676 8677 switch (os) { 8678 case llvm::Triple::CloudABI: 8679 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8680 case llvm::Triple::Linux: { 8681 switch (Triple.getEnvironment()) { 8682 default: 8683 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8684 case llvm::Triple::Android: 8685 return new AndroidX86_64TargetInfo(Triple, Opts); 8686 } 8687 } 8688 case llvm::Triple::DragonFly: 8689 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8690 case llvm::Triple::NetBSD: 8691 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8692 case llvm::Triple::OpenBSD: 8693 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8694 case llvm::Triple::Bitrig: 8695 return new BitrigX86_64TargetInfo(Triple, Opts); 8696 case llvm::Triple::FreeBSD: 8697 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8698 case llvm::Triple::Fuchsia: 8699 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8700 case llvm::Triple::KFreeBSD: 8701 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8702 case llvm::Triple::Solaris: 8703 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8704 case llvm::Triple::Win32: { 8705 switch (Triple.getEnvironment()) { 8706 case llvm::Triple::Cygnus: 8707 return new CygwinX86_64TargetInfo(Triple, Opts); 8708 case llvm::Triple::GNU: 8709 return new MinGWX86_64TargetInfo(Triple, Opts); 8710 case llvm::Triple::MSVC: 8711 default: // Assume MSVC for unknown environments 8712 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8713 } 8714 } 8715 case llvm::Triple::Haiku: 8716 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8717 case llvm::Triple::NaCl: 8718 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8719 case llvm::Triple::PS4: 8720 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8721 default: 8722 return new X86_64TargetInfo(Triple, Opts); 8723 } 8724 8725 case llvm::Triple::spir: { 8726 if (Triple.getOS() != llvm::Triple::UnknownOS || 8727 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8728 return nullptr; 8729 return new SPIR32TargetInfo(Triple, Opts); 8730 } 8731 case llvm::Triple::spir64: { 8732 if (Triple.getOS() != llvm::Triple::UnknownOS || 8733 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8734 return nullptr; 8735 return new SPIR64TargetInfo(Triple, Opts); 8736 } 8737 case llvm::Triple::wasm32: 8738 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8739 return nullptr; 8740 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8741 case llvm::Triple::wasm64: 8742 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8743 return nullptr; 8744 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8745 8746 case llvm::Triple::renderscript32: 8747 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8748 case llvm::Triple::renderscript64: 8749 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8750 } 8751 } 8752 8753 /// CreateTargetInfo - Return the target info object for the specified target 8754 /// options. 8755 TargetInfo * 8756 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8757 const std::shared_ptr<TargetOptions> &Opts) { 8758 llvm::Triple Triple(Opts->Triple); 8759 8760 // Construct the target 8761 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8762 if (!Target) { 8763 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8764 return nullptr; 8765 } 8766 Target->TargetOpts = Opts; 8767 8768 // Set the target CPU if specified. 8769 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8770 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8771 return nullptr; 8772 } 8773 8774 // Set the target ABI if specified. 8775 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8776 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8777 return nullptr; 8778 } 8779 8780 // Set the fp math unit. 8781 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8782 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8783 return nullptr; 8784 } 8785 8786 // Compute the default target features, we need the target to handle this 8787 // because features may have dependencies on one another. 8788 llvm::StringMap<bool> Features; 8789 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8790 Opts->FeaturesAsWritten)) 8791 return nullptr; 8792 8793 // Add the features to the compile options. 8794 Opts->Features.clear(); 8795 for (const auto &F : Features) 8796 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8797 8798 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8799 return nullptr; 8800 8801 Target->setSupportedOpenCLOpts(); 8802 8803 if (!Target->validateTarget(Diags)) 8804 return nullptr; 8805 8806 return Target.release(); 8807 } 8808