1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macos"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 #ifndef FREEBSD_CC_VERSION 312 #define FREEBSD_CC_VERSION 0U 313 #endif 314 315 // FreeBSD Target 316 template<typename Target> 317 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const override { 321 // FreeBSD defines; list based off of gcc output 322 323 unsigned Release = Triple.getOSMajorVersion(); 324 if (Release == 0U) 325 Release = 8U; 326 unsigned CCVersion = FREEBSD_CC_VERSION; 327 if (CCVersion == 0U) 328 CCVersion = Release * 100000U + 1U; 329 330 Builder.defineMacro("__FreeBSD__", Twine(Release)); 331 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 332 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 333 DefineStd(Builder, "unix", Opts); 334 Builder.defineMacro("__ELF__"); 335 336 // On FreeBSD, wchar_t contains the number of the code point as 337 // used by the character set of the locale. These character sets are 338 // not necessarily a superset of ASCII. 339 // 340 // FIXME: This is wrong; the macro refers to the numerical values 341 // of wchar_t *literals*, which are not locale-dependent. However, 342 // FreeBSD systems apparently depend on us getting this wrong, and 343 // setting this to 1 is conforming even if all the basic source 344 // character literals have the same encoding as char and wchar_t. 345 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 346 } 347 public: 348 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 349 : OSTargetInfo<Target>(Triple, Opts) { 350 switch (Triple.getArch()) { 351 default: 352 case llvm::Triple::x86: 353 case llvm::Triple::x86_64: 354 this->MCountName = ".mcount"; 355 break; 356 case llvm::Triple::mips: 357 case llvm::Triple::mipsel: 358 case llvm::Triple::ppc: 359 case llvm::Triple::ppc64: 360 case llvm::Triple::ppc64le: 361 this->MCountName = "_mcount"; 362 break; 363 case llvm::Triple::arm: 364 this->MCountName = "__mcount"; 365 break; 366 } 367 } 368 }; 369 370 // GNU/kFreeBSD Target 371 template<typename Target> 372 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 373 protected: 374 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 375 MacroBuilder &Builder) const override { 376 // GNU/kFreeBSD defines; list based off of gcc output 377 378 DefineStd(Builder, "unix", Opts); 379 Builder.defineMacro("__FreeBSD_kernel__"); 380 Builder.defineMacro("__GLIBC__"); 381 Builder.defineMacro("__ELF__"); 382 if (Opts.POSIXThreads) 383 Builder.defineMacro("_REENTRANT"); 384 if (Opts.CPlusPlus) 385 Builder.defineMacro("_GNU_SOURCE"); 386 } 387 public: 388 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 389 : OSTargetInfo<Target>(Triple, Opts) {} 390 }; 391 392 // Haiku Target 393 template<typename Target> 394 class HaikuTargetInfo : public OSTargetInfo<Target> { 395 protected: 396 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 397 MacroBuilder &Builder) const override { 398 // Haiku defines; list based off of gcc output 399 Builder.defineMacro("__HAIKU__"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) { 406 this->SizeType = TargetInfo::UnsignedLong; 407 this->IntPtrType = TargetInfo::SignedLong; 408 this->PtrDiffType = TargetInfo::SignedLong; 409 this->ProcessIDType = TargetInfo::SignedLong; 410 this->TLSSupported = false; 411 412 } 413 }; 414 415 // Minix Target 416 template<typename Target> 417 class MinixTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const override { 421 // Minix defines 422 423 Builder.defineMacro("__minix", "3"); 424 Builder.defineMacro("_EM_WSIZE", "4"); 425 Builder.defineMacro("_EM_PSIZE", "4"); 426 Builder.defineMacro("_EM_SSIZE", "2"); 427 Builder.defineMacro("_EM_LSIZE", "4"); 428 Builder.defineMacro("_EM_FSIZE", "4"); 429 Builder.defineMacro("_EM_DSIZE", "8"); 430 Builder.defineMacro("__ELF__"); 431 DefineStd(Builder, "unix", Opts); 432 } 433 public: 434 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 435 : OSTargetInfo<Target>(Triple, Opts) {} 436 }; 437 438 // Linux target 439 template<typename Target> 440 class LinuxTargetInfo : public OSTargetInfo<Target> { 441 protected: 442 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 443 MacroBuilder &Builder) const override { 444 // Linux defines; list based off of gcc output 445 DefineStd(Builder, "unix", Opts); 446 DefineStd(Builder, "linux", Opts); 447 Builder.defineMacro("__gnu_linux__"); 448 Builder.defineMacro("__ELF__"); 449 if (Triple.isAndroid()) { 450 Builder.defineMacro("__ANDROID__", "1"); 451 unsigned Maj, Min, Rev; 452 Triple.getEnvironmentVersion(Maj, Min, Rev); 453 this->PlatformName = "android"; 454 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 455 } 456 if (Opts.POSIXThreads) 457 Builder.defineMacro("_REENTRANT"); 458 if (Opts.CPlusPlus) 459 Builder.defineMacro("_GNU_SOURCE"); 460 if (this->HasFloat128) 461 Builder.defineMacro("__FLOAT128__"); 462 } 463 public: 464 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 465 : OSTargetInfo<Target>(Triple, Opts) { 466 this->WIntType = TargetInfo::UnsignedInt; 467 468 switch (Triple.getArch()) { 469 default: 470 break; 471 case llvm::Triple::ppc: 472 case llvm::Triple::ppc64: 473 case llvm::Triple::ppc64le: 474 this->MCountName = "_mcount"; 475 break; 476 case llvm::Triple::x86: 477 case llvm::Triple::x86_64: 478 case llvm::Triple::systemz: 479 this->HasFloat128 = true; 480 break; 481 } 482 } 483 484 const char *getStaticInitSectionSpecifier() const override { 485 return ".text.startup"; 486 } 487 }; 488 489 // NetBSD Target 490 template<typename Target> 491 class NetBSDTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // NetBSD defines; list based off of gcc output 496 Builder.defineMacro("__NetBSD__"); 497 Builder.defineMacro("__unix__"); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_POSIX_THREADS"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 515 : OSTargetInfo<Target>(Triple, Opts) { 516 this->MCountName = "_mcount"; 517 } 518 }; 519 520 // OpenBSD Target 521 template<typename Target> 522 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // OpenBSD defines; list based off of gcc output 527 528 Builder.defineMacro("__OpenBSD__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 } 534 public: 535 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 536 : OSTargetInfo<Target>(Triple, Opts) { 537 this->TLSSupported = false; 538 539 switch (Triple.getArch()) { 540 default: 541 case llvm::Triple::x86: 542 case llvm::Triple::x86_64: 543 case llvm::Triple::arm: 544 case llvm::Triple::sparc: 545 this->MCountName = "__mcount"; 546 break; 547 case llvm::Triple::mips64: 548 case llvm::Triple::mips64el: 549 case llvm::Triple::ppc: 550 case llvm::Triple::sparcv9: 551 this->MCountName = "_mcount"; 552 break; 553 } 554 } 555 }; 556 557 // Bitrig Target 558 template<typename Target> 559 class BitrigTargetInfo : public OSTargetInfo<Target> { 560 protected: 561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 562 MacroBuilder &Builder) const override { 563 // Bitrig defines; list based off of gcc output 564 565 Builder.defineMacro("__Bitrig__"); 566 DefineStd(Builder, "unix", Opts); 567 Builder.defineMacro("__ELF__"); 568 if (Opts.POSIXThreads) 569 Builder.defineMacro("_REENTRANT"); 570 571 switch (Triple.getArch()) { 572 default: 573 break; 574 case llvm::Triple::arm: 575 case llvm::Triple::armeb: 576 case llvm::Triple::thumb: 577 case llvm::Triple::thumbeb: 578 Builder.defineMacro("__ARM_DWARF_EH__"); 579 break; 580 } 581 } 582 public: 583 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 584 : OSTargetInfo<Target>(Triple, Opts) { 585 this->MCountName = "__mcount"; 586 } 587 }; 588 589 // PSP Target 590 template<typename Target> 591 class PSPTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 // PSP defines; list based on the output of the pspdev gcc toolchain. 596 Builder.defineMacro("PSP"); 597 Builder.defineMacro("_PSP"); 598 Builder.defineMacro("__psp__"); 599 Builder.defineMacro("__ELF__"); 600 } 601 public: 602 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 // PS3 PPU Target 606 template<typename Target> 607 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 // PS3 PPU defines. 612 Builder.defineMacro("__PPC__"); 613 Builder.defineMacro("__PPU__"); 614 Builder.defineMacro("__CELLOS_LV2__"); 615 Builder.defineMacro("__ELF__"); 616 Builder.defineMacro("__LP32__"); 617 Builder.defineMacro("_ARCH_PPC64"); 618 Builder.defineMacro("__powerpc64__"); 619 } 620 public: 621 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 622 : OSTargetInfo<Target>(Triple, Opts) { 623 this->LongWidth = this->LongAlign = 32; 624 this->PointerWidth = this->PointerAlign = 32; 625 this->IntMaxType = TargetInfo::SignedLongLong; 626 this->Int64Type = TargetInfo::SignedLongLong; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 629 } 630 }; 631 632 template <typename Target> 633 class PS4OSTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("__FreeBSD__", "9"); 638 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 639 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 640 DefineStd(Builder, "unix", Opts); 641 Builder.defineMacro("__ELF__"); 642 Builder.defineMacro("__ORBIS__"); 643 } 644 public: 645 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 646 : OSTargetInfo<Target>(Triple, Opts) { 647 this->WCharType = this->UnsignedShort; 648 649 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 650 this->MaxTLSAlign = 256; 651 652 // On PS4, do not honor explicit bit field alignment, 653 // as in "__attribute__((aligned(2))) int b : 1;". 654 this->UseExplicitBitFieldAlignment = false; 655 656 switch (Triple.getArch()) { 657 default: 658 case llvm::Triple::x86_64: 659 this->MCountName = ".mcount"; 660 break; 661 } 662 } 663 }; 664 665 // Solaris target 666 template<typename Target> 667 class SolarisTargetInfo : public OSTargetInfo<Target> { 668 protected: 669 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 670 MacroBuilder &Builder) const override { 671 DefineStd(Builder, "sun", Opts); 672 DefineStd(Builder, "unix", Opts); 673 Builder.defineMacro("__ELF__"); 674 Builder.defineMacro("__svr4__"); 675 Builder.defineMacro("__SVR4"); 676 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 677 // newer, but to 500 for everything else. feature_test.h has a check to 678 // ensure that you are not using C99 with an old version of X/Open or C89 679 // with a new version. 680 if (Opts.C99) 681 Builder.defineMacro("_XOPEN_SOURCE", "600"); 682 else 683 Builder.defineMacro("_XOPEN_SOURCE", "500"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("__C99FEATURES__"); 686 Builder.defineMacro("_LARGEFILE_SOURCE"); 687 Builder.defineMacro("_LARGEFILE64_SOURCE"); 688 Builder.defineMacro("__EXTENSIONS__"); 689 Builder.defineMacro("_REENTRANT"); 690 } 691 public: 692 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 693 : OSTargetInfo<Target>(Triple, Opts) { 694 this->WCharType = this->SignedInt; 695 // FIXME: WIntType should be SignedLong 696 } 697 }; 698 699 // Windows target 700 template<typename Target> 701 class WindowsTargetInfo : public OSTargetInfo<Target> { 702 protected: 703 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 704 MacroBuilder &Builder) const override { 705 Builder.defineMacro("_WIN32"); 706 } 707 void getVisualStudioDefines(const LangOptions &Opts, 708 MacroBuilder &Builder) const { 709 if (Opts.CPlusPlus) { 710 if (Opts.RTTIData) 711 Builder.defineMacro("_CPPRTTI"); 712 713 if (Opts.CXXExceptions) 714 Builder.defineMacro("_CPPUNWIND"); 715 } 716 717 if (Opts.Bool) 718 Builder.defineMacro("__BOOL_DEFINED"); 719 720 if (!Opts.CharIsSigned) 721 Builder.defineMacro("_CHAR_UNSIGNED"); 722 723 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 724 // but it works for now. 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_MT"); 727 728 if (Opts.MSCompatibilityVersion) { 729 Builder.defineMacro("_MSC_VER", 730 Twine(Opts.MSCompatibilityVersion / 100000)); 731 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 732 // FIXME We cannot encode the revision information into 32-bits 733 Builder.defineMacro("_MSC_BUILD", Twine(1)); 734 735 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 736 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 737 738 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 739 if (Opts.CPlusPlus1z) 740 Builder.defineMacro("_MSVC_LANG", "201403L"); 741 else if (Opts.CPlusPlus14) 742 Builder.defineMacro("_MSVC_LANG", "201402L"); 743 } 744 } 745 746 if (Opts.MicrosoftExt) { 747 Builder.defineMacro("_MSC_EXTENSIONS"); 748 749 if (Opts.CPlusPlus11) { 750 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 751 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 752 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 753 } 754 } 755 756 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 757 } 758 759 public: 760 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 761 : OSTargetInfo<Target>(Triple, Opts) {} 762 }; 763 764 template <typename Target> 765 class NaClTargetInfo : public OSTargetInfo<Target> { 766 protected: 767 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 768 MacroBuilder &Builder) const override { 769 if (Opts.POSIXThreads) 770 Builder.defineMacro("_REENTRANT"); 771 if (Opts.CPlusPlus) 772 Builder.defineMacro("_GNU_SOURCE"); 773 774 DefineStd(Builder, "unix", Opts); 775 Builder.defineMacro("__ELF__"); 776 Builder.defineMacro("__native_client__"); 777 } 778 779 public: 780 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 781 : OSTargetInfo<Target>(Triple, Opts) { 782 this->LongAlign = 32; 783 this->LongWidth = 32; 784 this->PointerAlign = 32; 785 this->PointerWidth = 32; 786 this->IntMaxType = TargetInfo::SignedLongLong; 787 this->Int64Type = TargetInfo::SignedLongLong; 788 this->DoubleAlign = 64; 789 this->LongDoubleWidth = 64; 790 this->LongDoubleAlign = 64; 791 this->LongLongWidth = 64; 792 this->LongLongAlign = 64; 793 this->SizeType = TargetInfo::UnsignedInt; 794 this->PtrDiffType = TargetInfo::SignedInt; 795 this->IntPtrType = TargetInfo::SignedInt; 796 // RegParmMax is inherited from the underlying architecture 797 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 798 if (Triple.getArch() == llvm::Triple::arm) { 799 // Handled in ARM's setABI(). 800 } else if (Triple.getArch() == llvm::Triple::x86) { 801 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 802 } else if (Triple.getArch() == llvm::Triple::x86_64) { 803 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 804 } else if (Triple.getArch() == llvm::Triple::mipsel) { 805 // Handled on mips' setDataLayout. 806 } else { 807 assert(Triple.getArch() == llvm::Triple::le32); 808 this->resetDataLayout("e-p:32:32-i64:64"); 809 } 810 } 811 }; 812 813 // WebAssembly target 814 template <typename Target> 815 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 816 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 817 MacroBuilder &Builder) const final { 818 // A common platform macro. 819 if (Opts.POSIXThreads) 820 Builder.defineMacro("_REENTRANT"); 821 // Follow g++ convention and predefine _GNU_SOURCE for C++. 822 if (Opts.CPlusPlus) 823 Builder.defineMacro("_GNU_SOURCE"); 824 } 825 826 // As an optimization, group static init code together in a section. 827 const char *getStaticInitSectionSpecifier() const final { 828 return ".text.__startup"; 829 } 830 831 public: 832 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 833 const TargetOptions &Opts) 834 : OSTargetInfo<Target>(Triple, Opts) { 835 this->MCountName = "__mcount"; 836 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 837 } 838 }; 839 840 //===----------------------------------------------------------------------===// 841 // Specific target implementations. 842 //===----------------------------------------------------------------------===// 843 844 // PPC abstract base class 845 class PPCTargetInfo : public TargetInfo { 846 static const Builtin::Info BuiltinInfo[]; 847 static const char * const GCCRegNames[]; 848 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 849 std::string CPU; 850 851 // Target cpu features. 852 bool HasVSX; 853 bool HasP8Vector; 854 bool HasP8Crypto; 855 bool HasDirectMove; 856 bool HasQPX; 857 bool HasHTM; 858 bool HasBPERMD; 859 bool HasExtDiv; 860 861 protected: 862 std::string ABI; 863 864 public: 865 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 866 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 867 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 868 HasBPERMD(false), HasExtDiv(false) { 869 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 870 SimdDefaultAlign = 128; 871 LongDoubleWidth = LongDoubleAlign = 128; 872 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 873 } 874 875 /// \brief Flags for architecture specific defines. 876 typedef enum { 877 ArchDefineNone = 0, 878 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 879 ArchDefinePpcgr = 1 << 1, 880 ArchDefinePpcsq = 1 << 2, 881 ArchDefine440 = 1 << 3, 882 ArchDefine603 = 1 << 4, 883 ArchDefine604 = 1 << 5, 884 ArchDefinePwr4 = 1 << 6, 885 ArchDefinePwr5 = 1 << 7, 886 ArchDefinePwr5x = 1 << 8, 887 ArchDefinePwr6 = 1 << 9, 888 ArchDefinePwr6x = 1 << 10, 889 ArchDefinePwr7 = 1 << 11, 890 ArchDefinePwr8 = 1 << 12, 891 ArchDefinePwr9 = 1 << 13, 892 ArchDefineA2 = 1 << 14, 893 ArchDefineA2q = 1 << 15 894 } ArchDefineTypes; 895 896 // Note: GCC recognizes the following additional cpus: 897 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 898 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 899 // titan, rs64. 900 bool setCPU(const std::string &Name) override { 901 bool CPUKnown = llvm::StringSwitch<bool>(Name) 902 .Case("generic", true) 903 .Case("440", true) 904 .Case("450", true) 905 .Case("601", true) 906 .Case("602", true) 907 .Case("603", true) 908 .Case("603e", true) 909 .Case("603ev", true) 910 .Case("604", true) 911 .Case("604e", true) 912 .Case("620", true) 913 .Case("630", true) 914 .Case("g3", true) 915 .Case("7400", true) 916 .Case("g4", true) 917 .Case("7450", true) 918 .Case("g4+", true) 919 .Case("750", true) 920 .Case("970", true) 921 .Case("g5", true) 922 .Case("a2", true) 923 .Case("a2q", true) 924 .Case("e500mc", true) 925 .Case("e5500", true) 926 .Case("power3", true) 927 .Case("pwr3", true) 928 .Case("power4", true) 929 .Case("pwr4", true) 930 .Case("power5", true) 931 .Case("pwr5", true) 932 .Case("power5x", true) 933 .Case("pwr5x", true) 934 .Case("power6", true) 935 .Case("pwr6", true) 936 .Case("power6x", true) 937 .Case("pwr6x", true) 938 .Case("power7", true) 939 .Case("pwr7", true) 940 .Case("power8", true) 941 .Case("pwr8", true) 942 .Case("power9", true) 943 .Case("pwr9", true) 944 .Case("powerpc", true) 945 .Case("ppc", true) 946 .Case("powerpc64", true) 947 .Case("ppc64", true) 948 .Case("powerpc64le", true) 949 .Case("ppc64le", true) 950 .Default(false); 951 952 if (CPUKnown) 953 CPU = Name; 954 955 return CPUKnown; 956 } 957 958 959 StringRef getABI() const override { return ABI; } 960 961 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 962 return llvm::makeArrayRef(BuiltinInfo, 963 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 964 } 965 966 bool isCLZForZeroUndef() const override { return false; } 967 968 void getTargetDefines(const LangOptions &Opts, 969 MacroBuilder &Builder) const override; 970 971 bool 972 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 973 StringRef CPU, 974 const std::vector<std::string> &FeaturesVec) const override; 975 976 bool handleTargetFeatures(std::vector<std::string> &Features, 977 DiagnosticsEngine &Diags) override; 978 bool hasFeature(StringRef Feature) const override; 979 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 980 bool Enabled) const override; 981 982 ArrayRef<const char *> getGCCRegNames() const override; 983 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 984 bool validateAsmConstraint(const char *&Name, 985 TargetInfo::ConstraintInfo &Info) const override { 986 switch (*Name) { 987 default: return false; 988 case 'O': // Zero 989 break; 990 case 'b': // Base register 991 case 'f': // Floating point register 992 Info.setAllowsRegister(); 993 break; 994 // FIXME: The following are added to allow parsing. 995 // I just took a guess at what the actions should be. 996 // Also, is more specific checking needed? I.e. specific registers? 997 case 'd': // Floating point register (containing 64-bit value) 998 case 'v': // Altivec vector register 999 Info.setAllowsRegister(); 1000 break; 1001 case 'w': 1002 switch (Name[1]) { 1003 case 'd':// VSX vector register to hold vector double data 1004 case 'f':// VSX vector register to hold vector float data 1005 case 's':// VSX vector register to hold scalar float data 1006 case 'a':// Any VSX register 1007 case 'c':// An individual CR bit 1008 break; 1009 default: 1010 return false; 1011 } 1012 Info.setAllowsRegister(); 1013 Name++; // Skip over 'w'. 1014 break; 1015 case 'h': // `MQ', `CTR', or `LINK' register 1016 case 'q': // `MQ' register 1017 case 'c': // `CTR' register 1018 case 'l': // `LINK' register 1019 case 'x': // `CR' register (condition register) number 0 1020 case 'y': // `CR' register (condition register) 1021 case 'z': // `XER[CA]' carry bit (part of the XER register) 1022 Info.setAllowsRegister(); 1023 break; 1024 case 'I': // Signed 16-bit constant 1025 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1026 // (use `L' instead for SImode constants) 1027 case 'K': // Unsigned 16-bit constant 1028 case 'L': // Signed 16-bit constant shifted left 16 bits 1029 case 'M': // Constant larger than 31 1030 case 'N': // Exact power of 2 1031 case 'P': // Constant whose negation is a signed 16-bit constant 1032 case 'G': // Floating point constant that can be loaded into a 1033 // register with one instruction per word 1034 case 'H': // Integer/Floating point constant that can be loaded 1035 // into a register using three instructions 1036 break; 1037 case 'm': // Memory operand. Note that on PowerPC targets, m can 1038 // include addresses that update the base register. It 1039 // is therefore only safe to use `m' in an asm statement 1040 // if that asm statement accesses the operand exactly once. 1041 // The asm statement must also use `%U<opno>' as a 1042 // placeholder for the "update" flag in the corresponding 1043 // load or store instruction. For example: 1044 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1045 // is correct but: 1046 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1047 // is not. Use es rather than m if you don't want the base 1048 // register to be updated. 1049 case 'e': 1050 if (Name[1] != 's') 1051 return false; 1052 // es: A "stable" memory operand; that is, one which does not 1053 // include any automodification of the base register. Unlike 1054 // `m', this constraint can be used in asm statements that 1055 // might access the operand several times, or that might not 1056 // access it at all. 1057 Info.setAllowsMemory(); 1058 Name++; // Skip over 'e'. 1059 break; 1060 case 'Q': // Memory operand that is an offset from a register (it is 1061 // usually better to use `m' or `es' in asm statements) 1062 case 'Z': // Memory operand that is an indexed or indirect from a 1063 // register (it is usually better to use `m' or `es' in 1064 // asm statements) 1065 Info.setAllowsMemory(); 1066 Info.setAllowsRegister(); 1067 break; 1068 case 'R': // AIX TOC entry 1069 case 'a': // Address operand that is an indexed or indirect from a 1070 // register (`p' is preferable for asm statements) 1071 case 'S': // Constant suitable as a 64-bit mask operand 1072 case 'T': // Constant suitable as a 32-bit mask operand 1073 case 'U': // System V Release 4 small data area reference 1074 case 't': // AND masks that can be performed by two rldic{l, r} 1075 // instructions 1076 case 'W': // Vector constant that does not require memory 1077 case 'j': // Vector constant that is all zeros. 1078 break; 1079 // End FIXME. 1080 } 1081 return true; 1082 } 1083 std::string convertConstraint(const char *&Constraint) const override { 1084 std::string R; 1085 switch (*Constraint) { 1086 case 'e': 1087 case 'w': 1088 // Two-character constraint; add "^" hint for later parsing. 1089 R = std::string("^") + std::string(Constraint, 2); 1090 Constraint++; 1091 break; 1092 default: 1093 return TargetInfo::convertConstraint(Constraint); 1094 } 1095 return R; 1096 } 1097 const char *getClobbers() const override { 1098 return ""; 1099 } 1100 int getEHDataRegisterNumber(unsigned RegNo) const override { 1101 if (RegNo == 0) return 3; 1102 if (RegNo == 1) return 4; 1103 return -1; 1104 } 1105 1106 bool hasSjLjLowering() const override { 1107 return true; 1108 } 1109 1110 bool useFloat128ManglingForLongDouble() const override { 1111 return LongDoubleWidth == 128 && 1112 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1113 getTriple().isOSBinFormatELF(); 1114 } 1115 }; 1116 1117 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1118 #define BUILTIN(ID, TYPE, ATTRS) \ 1119 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1120 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1121 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1122 #include "clang/Basic/BuiltinsPPC.def" 1123 }; 1124 1125 /// handleTargetFeatures - Perform initialization based on the user 1126 /// configured set of features. 1127 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1128 DiagnosticsEngine &Diags) { 1129 for (const auto &Feature : Features) { 1130 if (Feature == "+vsx") { 1131 HasVSX = true; 1132 } else if (Feature == "+bpermd") { 1133 HasBPERMD = true; 1134 } else if (Feature == "+extdiv") { 1135 HasExtDiv = true; 1136 } else if (Feature == "+power8-vector") { 1137 HasP8Vector = true; 1138 } else if (Feature == "+crypto") { 1139 HasP8Crypto = true; 1140 } else if (Feature == "+direct-move") { 1141 HasDirectMove = true; 1142 } else if (Feature == "+qpx") { 1143 HasQPX = true; 1144 } else if (Feature == "+htm") { 1145 HasHTM = true; 1146 } else if (Feature == "+float128") { 1147 HasFloat128 = true; 1148 } 1149 // TODO: Finish this list and add an assert that we've handled them 1150 // all. 1151 } 1152 1153 return true; 1154 } 1155 1156 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1157 /// #defines that are not tied to a specific subtarget. 1158 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1159 MacroBuilder &Builder) const { 1160 // Target identification. 1161 Builder.defineMacro("__ppc__"); 1162 Builder.defineMacro("__PPC__"); 1163 Builder.defineMacro("_ARCH_PPC"); 1164 Builder.defineMacro("__powerpc__"); 1165 Builder.defineMacro("__POWERPC__"); 1166 if (PointerWidth == 64) { 1167 Builder.defineMacro("_ARCH_PPC64"); 1168 Builder.defineMacro("__powerpc64__"); 1169 Builder.defineMacro("__ppc64__"); 1170 Builder.defineMacro("__PPC64__"); 1171 } 1172 1173 // Target properties. 1174 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1175 Builder.defineMacro("_LITTLE_ENDIAN"); 1176 } else { 1177 if (getTriple().getOS() != llvm::Triple::NetBSD && 1178 getTriple().getOS() != llvm::Triple::OpenBSD) 1179 Builder.defineMacro("_BIG_ENDIAN"); 1180 } 1181 1182 // ABI options. 1183 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1184 Builder.defineMacro("_CALL_ELF", "1"); 1185 if (ABI == "elfv2") 1186 Builder.defineMacro("_CALL_ELF", "2"); 1187 1188 // Subtarget options. 1189 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1190 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1191 1192 // FIXME: Should be controlled by command line option. 1193 if (LongDoubleWidth == 128) 1194 Builder.defineMacro("__LONG_DOUBLE_128__"); 1195 1196 if (Opts.AltiVec) { 1197 Builder.defineMacro("__VEC__", "10206"); 1198 Builder.defineMacro("__ALTIVEC__"); 1199 } 1200 1201 // CPU identification. 1202 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1203 .Case("440", ArchDefineName) 1204 .Case("450", ArchDefineName | ArchDefine440) 1205 .Case("601", ArchDefineName) 1206 .Case("602", ArchDefineName | ArchDefinePpcgr) 1207 .Case("603", ArchDefineName | ArchDefinePpcgr) 1208 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1209 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1210 .Case("604", ArchDefineName | ArchDefinePpcgr) 1211 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1212 .Case("620", ArchDefineName | ArchDefinePpcgr) 1213 .Case("630", ArchDefineName | ArchDefinePpcgr) 1214 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1215 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1216 .Case("750", ArchDefineName | ArchDefinePpcgr) 1217 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1218 | ArchDefinePpcsq) 1219 .Case("a2", ArchDefineA2) 1220 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1221 .Case("pwr3", ArchDefinePpcgr) 1222 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1223 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1224 | ArchDefinePpcsq) 1225 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1226 | ArchDefinePpcgr | ArchDefinePpcsq) 1227 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1228 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1229 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1230 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1231 | ArchDefinePpcsq) 1232 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1233 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1234 | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1236 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1237 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1238 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1239 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1240 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1241 | ArchDefinePpcsq) 1242 .Case("power3", ArchDefinePpcgr) 1243 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1244 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1245 | ArchDefinePpcsq) 1246 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1247 | ArchDefinePpcgr | ArchDefinePpcsq) 1248 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1251 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1252 | ArchDefinePpcsq) 1253 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1254 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1255 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1257 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1258 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1259 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1260 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1261 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1262 | ArchDefinePpcsq) 1263 .Default(ArchDefineNone); 1264 1265 if (defs & ArchDefineName) 1266 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1267 if (defs & ArchDefinePpcgr) 1268 Builder.defineMacro("_ARCH_PPCGR"); 1269 if (defs & ArchDefinePpcsq) 1270 Builder.defineMacro("_ARCH_PPCSQ"); 1271 if (defs & ArchDefine440) 1272 Builder.defineMacro("_ARCH_440"); 1273 if (defs & ArchDefine603) 1274 Builder.defineMacro("_ARCH_603"); 1275 if (defs & ArchDefine604) 1276 Builder.defineMacro("_ARCH_604"); 1277 if (defs & ArchDefinePwr4) 1278 Builder.defineMacro("_ARCH_PWR4"); 1279 if (defs & ArchDefinePwr5) 1280 Builder.defineMacro("_ARCH_PWR5"); 1281 if (defs & ArchDefinePwr5x) 1282 Builder.defineMacro("_ARCH_PWR5X"); 1283 if (defs & ArchDefinePwr6) 1284 Builder.defineMacro("_ARCH_PWR6"); 1285 if (defs & ArchDefinePwr6x) 1286 Builder.defineMacro("_ARCH_PWR6X"); 1287 if (defs & ArchDefinePwr7) 1288 Builder.defineMacro("_ARCH_PWR7"); 1289 if (defs & ArchDefinePwr8) 1290 Builder.defineMacro("_ARCH_PWR8"); 1291 if (defs & ArchDefinePwr9) 1292 Builder.defineMacro("_ARCH_PWR9"); 1293 if (defs & ArchDefineA2) 1294 Builder.defineMacro("_ARCH_A2"); 1295 if (defs & ArchDefineA2q) { 1296 Builder.defineMacro("_ARCH_A2Q"); 1297 Builder.defineMacro("_ARCH_QP"); 1298 } 1299 1300 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1301 Builder.defineMacro("__bg__"); 1302 Builder.defineMacro("__THW_BLUEGENE__"); 1303 Builder.defineMacro("__bgq__"); 1304 Builder.defineMacro("__TOS_BGQ__"); 1305 } 1306 1307 if (HasVSX) 1308 Builder.defineMacro("__VSX__"); 1309 if (HasP8Vector) 1310 Builder.defineMacro("__POWER8_VECTOR__"); 1311 if (HasP8Crypto) 1312 Builder.defineMacro("__CRYPTO__"); 1313 if (HasHTM) 1314 Builder.defineMacro("__HTM__"); 1315 if (HasFloat128) 1316 Builder.defineMacro("__FLOAT128__"); 1317 1318 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1319 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1320 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1321 if (PointerWidth == 64) 1322 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1323 1324 // FIXME: The following are not yet generated here by Clang, but are 1325 // generated by GCC: 1326 // 1327 // _SOFT_FLOAT_ 1328 // __RECIP_PRECISION__ 1329 // __APPLE_ALTIVEC__ 1330 // __RECIP__ 1331 // __RECIPF__ 1332 // __RSQRTE__ 1333 // __RSQRTEF__ 1334 // _SOFT_DOUBLE_ 1335 // __NO_LWSYNC__ 1336 // __HAVE_BSWAP__ 1337 // __LONGDOUBLE128 1338 // __CMODEL_MEDIUM__ 1339 // __CMODEL_LARGE__ 1340 // _CALL_SYSV 1341 // _CALL_DARWIN 1342 // __NO_FPRS__ 1343 } 1344 1345 // Handle explicit options being passed to the compiler here: if we've 1346 // explicitly turned off vsx and turned on power8-vector or direct-move then 1347 // go ahead and error since the customer has expressed a somewhat incompatible 1348 // set of options. 1349 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1350 const std::vector<std::string> &FeaturesVec) { 1351 1352 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1353 FeaturesVec.end()) { 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 1361 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1362 FeaturesVec.end()) { 1363 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1364 << "-mno-vsx"; 1365 return false; 1366 } 1367 1368 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1369 FeaturesVec.end()) { 1370 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1371 << "-mno-vsx"; 1372 return false; 1373 } 1374 } 1375 1376 return true; 1377 } 1378 1379 bool PPCTargetInfo::initFeatureMap( 1380 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1381 const std::vector<std::string> &FeaturesVec) const { 1382 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1383 .Case("7400", true) 1384 .Case("g4", true) 1385 .Case("7450", true) 1386 .Case("g4+", true) 1387 .Case("970", true) 1388 .Case("g5", true) 1389 .Case("pwr6", true) 1390 .Case("pwr7", true) 1391 .Case("pwr8", true) 1392 .Case("pwr9", true) 1393 .Case("ppc64", true) 1394 .Case("ppc64le", true) 1395 .Default(false); 1396 1397 Features["qpx"] = (CPU == "a2q"); 1398 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1399 .Case("ppc64le", true) 1400 .Case("pwr9", true) 1401 .Case("pwr8", true) 1402 .Default(false); 1403 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1404 .Case("ppc64le", true) 1405 .Case("pwr9", true) 1406 .Case("pwr8", true) 1407 .Default(false); 1408 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1409 .Case("ppc64le", true) 1410 .Case("pwr9", true) 1411 .Case("pwr8", true) 1412 .Case("pwr7", true) 1413 .Default(false); 1414 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1415 .Case("ppc64le", true) 1416 .Case("pwr9", true) 1417 .Case("pwr8", true) 1418 .Case("pwr7", true) 1419 .Default(false); 1420 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Default(false); 1425 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1426 .Case("ppc64le", true) 1427 .Case("pwr9", true) 1428 .Case("pwr8", true) 1429 .Case("pwr7", true) 1430 .Default(false); 1431 1432 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1433 return false; 1434 1435 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1436 } 1437 1438 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1439 return llvm::StringSwitch<bool>(Feature) 1440 .Case("powerpc", true) 1441 .Case("vsx", HasVSX) 1442 .Case("power8-vector", HasP8Vector) 1443 .Case("crypto", HasP8Crypto) 1444 .Case("direct-move", HasDirectMove) 1445 .Case("qpx", HasQPX) 1446 .Case("htm", HasHTM) 1447 .Case("bpermd", HasBPERMD) 1448 .Case("extdiv", HasExtDiv) 1449 .Case("float128", HasFloat128) 1450 .Default(false); 1451 } 1452 1453 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1454 StringRef Name, bool Enabled) const { 1455 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1456 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1457 // incompatible options. 1458 if (Enabled) { 1459 if (Name == "direct-move") { 1460 Features[Name] = Features["vsx"] = true; 1461 } else if (Name == "power8-vector") { 1462 Features[Name] = Features["vsx"] = true; 1463 } else if (Name == "float128") { 1464 Features[Name] = Features["vsx"] = true; 1465 } else { 1466 Features[Name] = true; 1467 } 1468 } else { 1469 if (Name == "vsx") { 1470 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1471 Features["float128"] = false; 1472 } else { 1473 Features[Name] = false; 1474 } 1475 } 1476 } 1477 1478 const char * const PPCTargetInfo::GCCRegNames[] = { 1479 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1480 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1481 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1482 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1483 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1484 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1485 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1486 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1487 "mq", "lr", "ctr", "ap", 1488 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1489 "xer", 1490 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1491 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1492 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1493 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1494 "vrsave", "vscr", 1495 "spe_acc", "spefscr", 1496 "sfp" 1497 }; 1498 1499 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1500 return llvm::makeArrayRef(GCCRegNames); 1501 } 1502 1503 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1504 // While some of these aliases do map to different registers 1505 // they still share the same register name. 1506 { { "0" }, "r0" }, 1507 { { "1"}, "r1" }, 1508 { { "2" }, "r2" }, 1509 { { "3" }, "r3" }, 1510 { { "4" }, "r4" }, 1511 { { "5" }, "r5" }, 1512 { { "6" }, "r6" }, 1513 { { "7" }, "r7" }, 1514 { { "8" }, "r8" }, 1515 { { "9" }, "r9" }, 1516 { { "10" }, "r10" }, 1517 { { "11" }, "r11" }, 1518 { { "12" }, "r12" }, 1519 { { "13" }, "r13" }, 1520 { { "14" }, "r14" }, 1521 { { "15" }, "r15" }, 1522 { { "16" }, "r16" }, 1523 { { "17" }, "r17" }, 1524 { { "18" }, "r18" }, 1525 { { "19" }, "r19" }, 1526 { { "20" }, "r20" }, 1527 { { "21" }, "r21" }, 1528 { { "22" }, "r22" }, 1529 { { "23" }, "r23" }, 1530 { { "24" }, "r24" }, 1531 { { "25" }, "r25" }, 1532 { { "26" }, "r26" }, 1533 { { "27" }, "r27" }, 1534 { { "28" }, "r28" }, 1535 { { "29" }, "r29" }, 1536 { { "30" }, "r30" }, 1537 { { "31" }, "r31" }, 1538 { { "fr0" }, "f0" }, 1539 { { "fr1" }, "f1" }, 1540 { { "fr2" }, "f2" }, 1541 { { "fr3" }, "f3" }, 1542 { { "fr4" }, "f4" }, 1543 { { "fr5" }, "f5" }, 1544 { { "fr6" }, "f6" }, 1545 { { "fr7" }, "f7" }, 1546 { { "fr8" }, "f8" }, 1547 { { "fr9" }, "f9" }, 1548 { { "fr10" }, "f10" }, 1549 { { "fr11" }, "f11" }, 1550 { { "fr12" }, "f12" }, 1551 { { "fr13" }, "f13" }, 1552 { { "fr14" }, "f14" }, 1553 { { "fr15" }, "f15" }, 1554 { { "fr16" }, "f16" }, 1555 { { "fr17" }, "f17" }, 1556 { { "fr18" }, "f18" }, 1557 { { "fr19" }, "f19" }, 1558 { { "fr20" }, "f20" }, 1559 { { "fr21" }, "f21" }, 1560 { { "fr22" }, "f22" }, 1561 { { "fr23" }, "f23" }, 1562 { { "fr24" }, "f24" }, 1563 { { "fr25" }, "f25" }, 1564 { { "fr26" }, "f26" }, 1565 { { "fr27" }, "f27" }, 1566 { { "fr28" }, "f28" }, 1567 { { "fr29" }, "f29" }, 1568 { { "fr30" }, "f30" }, 1569 { { "fr31" }, "f31" }, 1570 { { "cc" }, "cr0" }, 1571 }; 1572 1573 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1574 return llvm::makeArrayRef(GCCRegAliases); 1575 } 1576 1577 class PPC32TargetInfo : public PPCTargetInfo { 1578 public: 1579 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1580 : PPCTargetInfo(Triple, Opts) { 1581 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1582 1583 switch (getTriple().getOS()) { 1584 case llvm::Triple::Linux: 1585 case llvm::Triple::FreeBSD: 1586 case llvm::Triple::NetBSD: 1587 SizeType = UnsignedInt; 1588 PtrDiffType = SignedInt; 1589 IntPtrType = SignedInt; 1590 break; 1591 default: 1592 break; 1593 } 1594 1595 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1596 LongDoubleWidth = LongDoubleAlign = 64; 1597 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1598 } 1599 1600 // PPC32 supports atomics up to 4 bytes. 1601 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1602 } 1603 1604 BuiltinVaListKind getBuiltinVaListKind() const override { 1605 // This is the ELF definition, and is overridden by the Darwin sub-target 1606 return TargetInfo::PowerABIBuiltinVaList; 1607 } 1608 }; 1609 1610 // Note: ABI differences may eventually require us to have a separate 1611 // TargetInfo for little endian. 1612 class PPC64TargetInfo : public PPCTargetInfo { 1613 public: 1614 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1615 : PPCTargetInfo(Triple, Opts) { 1616 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1617 IntMaxType = SignedLong; 1618 Int64Type = SignedLong; 1619 1620 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1621 resetDataLayout("e-m:e-i64:64-n32:64"); 1622 ABI = "elfv2"; 1623 } else { 1624 resetDataLayout("E-m:e-i64:64-n32:64"); 1625 ABI = "elfv1"; 1626 } 1627 1628 switch (getTriple().getOS()) { 1629 case llvm::Triple::FreeBSD: 1630 LongDoubleWidth = LongDoubleAlign = 64; 1631 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1632 break; 1633 case llvm::Triple::NetBSD: 1634 IntMaxType = SignedLongLong; 1635 Int64Type = SignedLongLong; 1636 break; 1637 default: 1638 break; 1639 } 1640 1641 // PPC64 supports atomics up to 8 bytes. 1642 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1643 } 1644 BuiltinVaListKind getBuiltinVaListKind() const override { 1645 return TargetInfo::CharPtrBuiltinVaList; 1646 } 1647 // PPC64 Linux-specific ABI options. 1648 bool setABI(const std::string &Name) override { 1649 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1650 ABI = Name; 1651 return true; 1652 } 1653 return false; 1654 } 1655 }; 1656 1657 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1658 public: 1659 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1660 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1661 HasAlignMac68kSupport = true; 1662 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1663 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1664 LongLongAlign = 32; 1665 SuitableAlign = 128; 1666 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1667 } 1668 BuiltinVaListKind getBuiltinVaListKind() const override { 1669 return TargetInfo::CharPtrBuiltinVaList; 1670 } 1671 }; 1672 1673 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1674 public: 1675 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1676 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1677 HasAlignMac68kSupport = true; 1678 SuitableAlign = 128; 1679 resetDataLayout("E-m:o-i64:64-n32:64"); 1680 } 1681 }; 1682 1683 static const unsigned NVPTXAddrSpaceMap[] = { 1684 1, // opencl_global 1685 3, // opencl_local 1686 4, // opencl_constant 1687 // FIXME: generic has to be added to the target 1688 0, // opencl_generic 1689 1, // cuda_device 1690 4, // cuda_constant 1691 3, // cuda_shared 1692 }; 1693 1694 class NVPTXTargetInfo : public TargetInfo { 1695 static const char *const GCCRegNames[]; 1696 static const Builtin::Info BuiltinInfo[]; 1697 1698 // The GPU profiles supported by the NVPTX backend 1699 enum GPUKind { 1700 GK_NONE, 1701 GK_SM20, 1702 GK_SM21, 1703 GK_SM30, 1704 GK_SM35, 1705 GK_SM37, 1706 GK_SM50, 1707 GK_SM52, 1708 GK_SM53, 1709 } GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 BigEndian = false; 1715 TLSSupported = false; 1716 LongWidth = LongAlign = 64; 1717 AddrSpaceMap = &NVPTXAddrSpaceMap; 1718 UseAddrSpaceMapMangling = true; 1719 // Define available target features 1720 // These must be defined in sorted order! 1721 NoAsmVariants = true; 1722 // Set the default GPU to sm20 1723 GPU = GK_SM20; 1724 1725 // If possible, get a TargetInfo for our host triple, so we can match its 1726 // types. 1727 llvm::Triple HostTriple(Opts.HostTriple); 1728 if (HostTriple.isNVPTX()) 1729 return; 1730 std::unique_ptr<TargetInfo> HostTarget( 1731 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1732 if (!HostTarget) { 1733 return; 1734 } 1735 1736 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1737 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1738 BoolWidth = HostTarget->getBoolWidth(); 1739 BoolAlign = HostTarget->getBoolAlign(); 1740 IntWidth = HostTarget->getIntWidth(); 1741 IntAlign = HostTarget->getIntAlign(); 1742 HalfWidth = HostTarget->getHalfWidth(); 1743 HalfAlign = HostTarget->getHalfAlign(); 1744 FloatWidth = HostTarget->getFloatWidth(); 1745 FloatAlign = HostTarget->getFloatAlign(); 1746 DoubleWidth = HostTarget->getDoubleWidth(); 1747 DoubleAlign = HostTarget->getDoubleAlign(); 1748 LongWidth = HostTarget->getLongWidth(); 1749 LongAlign = HostTarget->getLongAlign(); 1750 LongLongWidth = HostTarget->getLongLongWidth(); 1751 LongLongAlign = HostTarget->getLongLongAlign(); 1752 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1753 DefaultAlignForAttributeAligned = 1754 HostTarget->getDefaultAlignForAttributeAligned(); 1755 SizeType = HostTarget->getSizeType(); 1756 IntMaxType = HostTarget->getIntMaxType(); 1757 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1758 IntPtrType = HostTarget->getIntPtrType(); 1759 WCharType = HostTarget->getWCharType(); 1760 WIntType = HostTarget->getWIntType(); 1761 Char16Type = HostTarget->getChar16Type(); 1762 Char32Type = HostTarget->getChar32Type(); 1763 Int64Type = HostTarget->getInt64Type(); 1764 SigAtomicType = HostTarget->getSigAtomicType(); 1765 ProcessIDType = HostTarget->getProcessIDType(); 1766 1767 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1768 UseZeroLengthBitfieldAlignment = 1769 HostTarget->useZeroLengthBitfieldAlignment(); 1770 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1771 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1772 1773 // Properties intentionally not copied from host: 1774 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1775 // host/device boundary. 1776 // - SuitableAlign: Not visible across the host/device boundary, and may 1777 // correctly be different on host/device, e.g. if host has wider vector 1778 // types than device. 1779 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1780 // as its double type, but that's not necessarily true on the host. 1781 // TODO: nvcc emits a warning when using long double on device; we should 1782 // do the same. 1783 } 1784 void getTargetDefines(const LangOptions &Opts, 1785 MacroBuilder &Builder) const override { 1786 Builder.defineMacro("__PTX__"); 1787 Builder.defineMacro("__NVPTX__"); 1788 if (Opts.CUDAIsDevice) { 1789 // Set __CUDA_ARCH__ for the GPU specified. 1790 std::string CUDAArchCode; 1791 switch (GPU) { 1792 case GK_SM20: 1793 CUDAArchCode = "200"; 1794 break; 1795 case GK_SM21: 1796 CUDAArchCode = "210"; 1797 break; 1798 case GK_SM30: 1799 CUDAArchCode = "300"; 1800 break; 1801 case GK_SM35: 1802 CUDAArchCode = "350"; 1803 break; 1804 case GK_SM37: 1805 CUDAArchCode = "370"; 1806 break; 1807 case GK_SM50: 1808 CUDAArchCode = "500"; 1809 break; 1810 case GK_SM52: 1811 CUDAArchCode = "520"; 1812 break; 1813 case GK_SM53: 1814 CUDAArchCode = "530"; 1815 break; 1816 default: 1817 llvm_unreachable("Unhandled target CPU"); 1818 } 1819 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1820 } 1821 } 1822 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1823 return llvm::makeArrayRef(BuiltinInfo, 1824 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1825 } 1826 bool hasFeature(StringRef Feature) const override { 1827 return Feature == "ptx" || Feature == "nvptx"; 1828 } 1829 1830 ArrayRef<const char *> getGCCRegNames() const override; 1831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1832 // No aliases. 1833 return None; 1834 } 1835 bool validateAsmConstraint(const char *&Name, 1836 TargetInfo::ConstraintInfo &Info) const override { 1837 switch (*Name) { 1838 default: 1839 return false; 1840 case 'c': 1841 case 'h': 1842 case 'r': 1843 case 'l': 1844 case 'f': 1845 case 'd': 1846 Info.setAllowsRegister(); 1847 return true; 1848 } 1849 } 1850 const char *getClobbers() const override { 1851 // FIXME: Is this really right? 1852 return ""; 1853 } 1854 BuiltinVaListKind getBuiltinVaListKind() const override { 1855 // FIXME: implement 1856 return TargetInfo::CharPtrBuiltinVaList; 1857 } 1858 bool setCPU(const std::string &Name) override { 1859 GPU = llvm::StringSwitch<GPUKind>(Name) 1860 .Case("sm_20", GK_SM20) 1861 .Case("sm_21", GK_SM21) 1862 .Case("sm_30", GK_SM30) 1863 .Case("sm_35", GK_SM35) 1864 .Case("sm_37", GK_SM37) 1865 .Case("sm_50", GK_SM50) 1866 .Case("sm_52", GK_SM52) 1867 .Case("sm_53", GK_SM53) 1868 .Default(GK_NONE); 1869 1870 return GPU != GK_NONE; 1871 } 1872 void setSupportedOpenCLOpts() override { 1873 auto &Opts = getSupportedOpenCLOpts(); 1874 Opts.cl_clang_storage_class_specifiers = 1; 1875 Opts.cl_khr_gl_sharing = 1; 1876 Opts.cl_khr_icd = 1; 1877 1878 Opts.cl_khr_fp64 = 1; 1879 Opts.cl_khr_byte_addressable_store = 1; 1880 Opts.cl_khr_global_int32_base_atomics = 1; 1881 Opts.cl_khr_global_int32_extended_atomics = 1; 1882 Opts.cl_khr_local_int32_base_atomics = 1; 1883 Opts.cl_khr_local_int32_extended_atomics = 1; 1884 } 1885 }; 1886 1887 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1888 #define BUILTIN(ID, TYPE, ATTRS) \ 1889 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1890 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1891 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1892 #include "clang/Basic/BuiltinsNVPTX.def" 1893 }; 1894 1895 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1896 1897 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1898 return llvm::makeArrayRef(GCCRegNames); 1899 } 1900 1901 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1902 public: 1903 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1904 : NVPTXTargetInfo(Triple, Opts) { 1905 LongWidth = LongAlign = 32; 1906 PointerWidth = PointerAlign = 32; 1907 SizeType = TargetInfo::UnsignedInt; 1908 PtrDiffType = TargetInfo::SignedInt; 1909 IntPtrType = TargetInfo::SignedInt; 1910 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1911 } 1912 }; 1913 1914 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1915 public: 1916 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1917 : NVPTXTargetInfo(Triple, Opts) { 1918 PointerWidth = PointerAlign = 64; 1919 SizeType = TargetInfo::UnsignedLong; 1920 PtrDiffType = TargetInfo::SignedLong; 1921 IntPtrType = TargetInfo::SignedLong; 1922 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1923 } 1924 }; 1925 1926 static const unsigned AMDGPUAddrSpaceMap[] = { 1927 1, // opencl_global 1928 3, // opencl_local 1929 2, // opencl_constant 1930 4, // opencl_generic 1931 1, // cuda_device 1932 2, // cuda_constant 1933 3 // cuda_shared 1934 }; 1935 1936 // If you edit the description strings, make sure you update 1937 // getPointerWidthV(). 1938 1939 static const char *const DataLayoutStringR600 = 1940 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1941 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1942 1943 static const char *const DataLayoutStringSI = 1944 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1945 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1946 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1947 1948 class AMDGPUTargetInfo final : public TargetInfo { 1949 static const Builtin::Info BuiltinInfo[]; 1950 static const char * const GCCRegNames[]; 1951 1952 /// \brief The GPU profiles supported by the AMDGPU target. 1953 enum GPUKind { 1954 GK_NONE, 1955 GK_R600, 1956 GK_R600_DOUBLE_OPS, 1957 GK_R700, 1958 GK_R700_DOUBLE_OPS, 1959 GK_EVERGREEN, 1960 GK_EVERGREEN_DOUBLE_OPS, 1961 GK_NORTHERN_ISLANDS, 1962 GK_CAYMAN, 1963 GK_SOUTHERN_ISLANDS, 1964 GK_SEA_ISLANDS, 1965 GK_VOLCANIC_ISLANDS 1966 } GPU; 1967 1968 bool hasFP64:1; 1969 bool hasFMAF:1; 1970 bool hasLDEXPF:1; 1971 1972 static bool isAMDGCN(const llvm::Triple &TT) { 1973 return TT.getArch() == llvm::Triple::amdgcn; 1974 } 1975 1976 public: 1977 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1978 : TargetInfo(Triple) , 1979 GPU(isAMDGCN(Triple) ? GK_SOUTHERN_ISLANDS : GK_R600), 1980 hasFP64(false), 1981 hasFMAF(false), 1982 hasLDEXPF(false) { 1983 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1984 hasFP64 = true; 1985 hasFMAF = true; 1986 hasLDEXPF = true; 1987 } 1988 1989 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1990 DataLayoutStringSI : DataLayoutStringR600); 1991 1992 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1993 UseAddrSpaceMapMangling = true; 1994 } 1995 1996 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1997 if (GPU <= GK_CAYMAN) 1998 return 32; 1999 2000 switch(AddrSpace) { 2001 default: 2002 return 64; 2003 case 0: 2004 case 3: 2005 case 5: 2006 return 32; 2007 } 2008 } 2009 2010 const char * getClobbers() const override { 2011 return ""; 2012 } 2013 2014 ArrayRef<const char *> getGCCRegNames() const override; 2015 2016 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2017 return None; 2018 } 2019 2020 bool validateAsmConstraint(const char *&Name, 2021 TargetInfo::ConstraintInfo &Info) const override { 2022 switch (*Name) { 2023 default: break; 2024 case 'v': // vgpr 2025 case 's': // sgpr 2026 Info.setAllowsRegister(); 2027 return true; 2028 } 2029 return false; 2030 } 2031 2032 bool initFeatureMap(llvm::StringMap<bool> &Features, 2033 DiagnosticsEngine &Diags, StringRef CPU, 2034 const std::vector<std::string> &FeatureVec) const override; 2035 2036 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2037 return llvm::makeArrayRef(BuiltinInfo, 2038 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2039 } 2040 2041 void getTargetDefines(const LangOptions &Opts, 2042 MacroBuilder &Builder) const override { 2043 if (getTriple().getArch() == llvm::Triple::amdgcn) 2044 Builder.defineMacro("__AMDGCN__"); 2045 else 2046 Builder.defineMacro("__R600__"); 2047 2048 if (hasFMAF) 2049 Builder.defineMacro("__HAS_FMAF__"); 2050 if (hasLDEXPF) 2051 Builder.defineMacro("__HAS_LDEXPF__"); 2052 if (hasFP64) 2053 Builder.defineMacro("__HAS_FP64__"); 2054 } 2055 2056 BuiltinVaListKind getBuiltinVaListKind() const override { 2057 return TargetInfo::CharPtrBuiltinVaList; 2058 } 2059 2060 static GPUKind parseR600Name(StringRef Name) { 2061 return llvm::StringSwitch<GPUKind>(Name) 2062 .Case("r600" , GK_R600) 2063 .Case("rv610", GK_R600) 2064 .Case("rv620", GK_R600) 2065 .Case("rv630", GK_R600) 2066 .Case("rv635", GK_R600) 2067 .Case("rs780", GK_R600) 2068 .Case("rs880", GK_R600) 2069 .Case("rv670", GK_R600_DOUBLE_OPS) 2070 .Case("rv710", GK_R700) 2071 .Case("rv730", GK_R700) 2072 .Case("rv740", GK_R700_DOUBLE_OPS) 2073 .Case("rv770", GK_R700_DOUBLE_OPS) 2074 .Case("palm", GK_EVERGREEN) 2075 .Case("cedar", GK_EVERGREEN) 2076 .Case("sumo", GK_EVERGREEN) 2077 .Case("sumo2", GK_EVERGREEN) 2078 .Case("redwood", GK_EVERGREEN) 2079 .Case("juniper", GK_EVERGREEN) 2080 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2081 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2082 .Case("barts", GK_NORTHERN_ISLANDS) 2083 .Case("turks", GK_NORTHERN_ISLANDS) 2084 .Case("caicos", GK_NORTHERN_ISLANDS) 2085 .Case("cayman", GK_CAYMAN) 2086 .Case("aruba", GK_CAYMAN) 2087 .Default(GK_NONE); 2088 } 2089 2090 static GPUKind parseAMDGCNName(StringRef Name) { 2091 return llvm::StringSwitch<GPUKind>(Name) 2092 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2093 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2094 .Case("verde", GK_SOUTHERN_ISLANDS) 2095 .Case("oland", GK_SOUTHERN_ISLANDS) 2096 .Case("hainan", GK_SOUTHERN_ISLANDS) 2097 .Case("bonaire", GK_SEA_ISLANDS) 2098 .Case("kabini", GK_SEA_ISLANDS) 2099 .Case("kaveri", GK_SEA_ISLANDS) 2100 .Case("hawaii", GK_SEA_ISLANDS) 2101 .Case("mullins", GK_SEA_ISLANDS) 2102 .Case("tonga", GK_VOLCANIC_ISLANDS) 2103 .Case("iceland", GK_VOLCANIC_ISLANDS) 2104 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2105 .Case("fiji", GK_VOLCANIC_ISLANDS) 2106 .Case("stoney", GK_VOLCANIC_ISLANDS) 2107 .Default(GK_NONE); 2108 } 2109 2110 bool setCPU(const std::string &Name) override { 2111 if (getTriple().getArch() == llvm::Triple::amdgcn) 2112 GPU = parseAMDGCNName(Name); 2113 else 2114 GPU = parseR600Name(Name); 2115 2116 return GPU != GK_NONE; 2117 } 2118 2119 void setSupportedOpenCLOpts() override { 2120 auto &Opts = getSupportedOpenCLOpts(); 2121 Opts.cl_clang_storage_class_specifiers = 1; 2122 Opts.cl_khr_icd = 1; 2123 2124 if (hasFP64) 2125 Opts.cl_khr_fp64 = 1; 2126 if (GPU >= GK_EVERGREEN) { 2127 Opts.cl_khr_byte_addressable_store = 1; 2128 Opts.cl_khr_global_int32_base_atomics = 1; 2129 Opts.cl_khr_global_int32_extended_atomics = 1; 2130 Opts.cl_khr_local_int32_base_atomics = 1; 2131 Opts.cl_khr_local_int32_extended_atomics = 1; 2132 } 2133 if (GPU >= GK_SOUTHERN_ISLANDS) { 2134 Opts.cl_khr_fp16 = 1; 2135 Opts.cl_khr_int64_base_atomics = 1; 2136 Opts.cl_khr_int64_extended_atomics = 1; 2137 Opts.cl_khr_3d_image_writes = 1; 2138 } 2139 } 2140 }; 2141 2142 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2143 #define BUILTIN(ID, TYPE, ATTRS) \ 2144 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2145 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2146 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2147 #include "clang/Basic/BuiltinsAMDGPU.def" 2148 }; 2149 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2150 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2151 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2152 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2153 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2154 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2155 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2156 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2157 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2158 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2159 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2160 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2161 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2162 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2163 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2164 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2165 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2166 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2167 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2168 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2169 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2170 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2171 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2172 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2173 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2174 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2175 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2176 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2177 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2178 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2179 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2180 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2181 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2182 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2183 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2184 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2185 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2186 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2187 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2188 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2189 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2190 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2191 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2192 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2193 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2194 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2195 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2196 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2197 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2198 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2199 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2200 }; 2201 2202 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2203 return llvm::makeArrayRef(GCCRegNames); 2204 } 2205 2206 bool AMDGPUTargetInfo::initFeatureMap( 2207 llvm::StringMap<bool> &Features, 2208 DiagnosticsEngine &Diags, StringRef CPU, 2209 const std::vector<std::string> &FeatureVec) const { 2210 2211 // XXX - What does the member GPU mean if device name string passed here? 2212 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2213 if (CPU.empty()) 2214 CPU = "tahiti"; 2215 2216 switch (parseAMDGCNName(CPU)) { 2217 case GK_SOUTHERN_ISLANDS: 2218 case GK_SEA_ISLANDS: 2219 break; 2220 2221 case GK_VOLCANIC_ISLANDS: 2222 Features["s-memrealtime"] = true; 2223 Features["16-bit-insts"] = true; 2224 break; 2225 2226 case GK_NONE: 2227 return false; 2228 default: 2229 llvm_unreachable("unhandled subtarget"); 2230 } 2231 } else { 2232 if (CPU.empty()) 2233 CPU = "r600"; 2234 2235 switch (parseR600Name(CPU)) { 2236 case GK_R600: 2237 case GK_R700: 2238 case GK_EVERGREEN: 2239 case GK_NORTHERN_ISLANDS: 2240 break; 2241 case GK_R600_DOUBLE_OPS: 2242 case GK_R700_DOUBLE_OPS: 2243 case GK_EVERGREEN_DOUBLE_OPS: 2244 case GK_CAYMAN: 2245 Features["fp64"] = true; 2246 break; 2247 case GK_NONE: 2248 return false; 2249 default: 2250 llvm_unreachable("unhandled subtarget"); 2251 } 2252 } 2253 2254 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2255 } 2256 2257 // Namespace for x86 abstract base class 2258 const Builtin::Info BuiltinInfo[] = { 2259 #define BUILTIN(ID, TYPE, ATTRS) \ 2260 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2261 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2262 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2263 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2264 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2265 #include "clang/Basic/BuiltinsX86.def" 2266 }; 2267 2268 static const char* const GCCRegNames[] = { 2269 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2270 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2271 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2272 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2273 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2274 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2275 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2276 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2277 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2278 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2279 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2280 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2281 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2282 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2283 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2284 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2285 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2286 }; 2287 2288 const TargetInfo::AddlRegName AddlRegNames[] = { 2289 { { "al", "ah", "eax", "rax" }, 0 }, 2290 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2291 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2292 { { "dl", "dh", "edx", "rdx" }, 1 }, 2293 { { "esi", "rsi" }, 4 }, 2294 { { "edi", "rdi" }, 5 }, 2295 { { "esp", "rsp" }, 7 }, 2296 { { "ebp", "rbp" }, 6 }, 2297 { { "r8d", "r8w", "r8b" }, 38 }, 2298 { { "r9d", "r9w", "r9b" }, 39 }, 2299 { { "r10d", "r10w", "r10b" }, 40 }, 2300 { { "r11d", "r11w", "r11b" }, 41 }, 2301 { { "r12d", "r12w", "r12b" }, 42 }, 2302 { { "r13d", "r13w", "r13b" }, 43 }, 2303 { { "r14d", "r14w", "r14b" }, 44 }, 2304 { { "r15d", "r15w", "r15b" }, 45 }, 2305 }; 2306 2307 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2308 // most of the implementation can be shared. 2309 class X86TargetInfo : public TargetInfo { 2310 enum X86SSEEnum { 2311 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2312 } SSELevel = NoSSE; 2313 enum MMX3DNowEnum { 2314 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2315 } MMX3DNowLevel = NoMMX3DNow; 2316 enum XOPEnum { 2317 NoXOP, 2318 SSE4A, 2319 FMA4, 2320 XOP 2321 } XOPLevel = NoXOP; 2322 2323 bool HasAES = false; 2324 bool HasPCLMUL = false; 2325 bool HasLZCNT = false; 2326 bool HasRDRND = false; 2327 bool HasFSGSBASE = false; 2328 bool HasBMI = false; 2329 bool HasBMI2 = false; 2330 bool HasPOPCNT = false; 2331 bool HasRTM = false; 2332 bool HasPRFCHW = false; 2333 bool HasRDSEED = false; 2334 bool HasADX = false; 2335 bool HasTBM = false; 2336 bool HasFMA = false; 2337 bool HasF16C = false; 2338 bool HasAVX512CD = false; 2339 bool HasAVX512ER = false; 2340 bool HasAVX512PF = false; 2341 bool HasAVX512DQ = false; 2342 bool HasAVX512BW = false; 2343 bool HasAVX512VL = false; 2344 bool HasAVX512VBMI = false; 2345 bool HasAVX512IFMA = false; 2346 bool HasSHA = false; 2347 bool HasMPX = false; 2348 bool HasSGX = false; 2349 bool HasCX16 = false; 2350 bool HasFXSR = false; 2351 bool HasXSAVE = false; 2352 bool HasXSAVEOPT = false; 2353 bool HasXSAVEC = false; 2354 bool HasXSAVES = false; 2355 bool HasMWAITX = false; 2356 bool HasPKU = false; 2357 bool HasCLFLUSHOPT = false; 2358 bool HasPCOMMIT = false; 2359 bool HasCLWB = false; 2360 bool HasUMIP = false; 2361 bool HasMOVBE = false; 2362 bool HasPREFETCHWT1 = false; 2363 2364 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2365 /// 2366 /// Each enumeration represents a particular CPU supported by Clang. These 2367 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2368 enum CPUKind { 2369 CK_Generic, 2370 2371 /// \name i386 2372 /// i386-generation processors. 2373 //@{ 2374 CK_i386, 2375 //@} 2376 2377 /// \name i486 2378 /// i486-generation processors. 2379 //@{ 2380 CK_i486, 2381 CK_WinChipC6, 2382 CK_WinChip2, 2383 CK_C3, 2384 //@} 2385 2386 /// \name i586 2387 /// i586-generation processors, P5 microarchitecture based. 2388 //@{ 2389 CK_i586, 2390 CK_Pentium, 2391 CK_PentiumMMX, 2392 //@} 2393 2394 /// \name i686 2395 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2396 //@{ 2397 CK_i686, 2398 CK_PentiumPro, 2399 CK_Pentium2, 2400 CK_Pentium3, 2401 CK_Pentium3M, 2402 CK_PentiumM, 2403 CK_C3_2, 2404 2405 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2406 /// Clang however has some logic to suport this. 2407 // FIXME: Warn, deprecate, and potentially remove this. 2408 CK_Yonah, 2409 //@} 2410 2411 /// \name Netburst 2412 /// Netburst microarchitecture based processors. 2413 //@{ 2414 CK_Pentium4, 2415 CK_Pentium4M, 2416 CK_Prescott, 2417 CK_Nocona, 2418 //@} 2419 2420 /// \name Core 2421 /// Core microarchitecture based processors. 2422 //@{ 2423 CK_Core2, 2424 2425 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2426 /// codename which GCC no longer accepts as an option to -march, but Clang 2427 /// has some logic for recognizing it. 2428 // FIXME: Warn, deprecate, and potentially remove this. 2429 CK_Penryn, 2430 //@} 2431 2432 /// \name Atom 2433 /// Atom processors 2434 //@{ 2435 CK_Bonnell, 2436 CK_Silvermont, 2437 //@} 2438 2439 /// \name Nehalem 2440 /// Nehalem microarchitecture based processors. 2441 CK_Nehalem, 2442 2443 /// \name Westmere 2444 /// Westmere microarchitecture based processors. 2445 CK_Westmere, 2446 2447 /// \name Sandy Bridge 2448 /// Sandy Bridge microarchitecture based processors. 2449 CK_SandyBridge, 2450 2451 /// \name Ivy Bridge 2452 /// Ivy Bridge microarchitecture based processors. 2453 CK_IvyBridge, 2454 2455 /// \name Haswell 2456 /// Haswell microarchitecture based processors. 2457 CK_Haswell, 2458 2459 /// \name Broadwell 2460 /// Broadwell microarchitecture based processors. 2461 CK_Broadwell, 2462 2463 /// \name Skylake Client 2464 /// Skylake client microarchitecture based processors. 2465 CK_SkylakeClient, 2466 2467 /// \name Skylake Server 2468 /// Skylake server microarchitecture based processors. 2469 CK_SkylakeServer, 2470 2471 /// \name Cannonlake Client 2472 /// Cannonlake client microarchitecture based processors. 2473 CK_Cannonlake, 2474 2475 /// \name Knights Landing 2476 /// Knights Landing processor. 2477 CK_KNL, 2478 2479 /// \name Lakemont 2480 /// Lakemont microarchitecture based processors. 2481 CK_Lakemont, 2482 2483 /// \name K6 2484 /// K6 architecture processors. 2485 //@{ 2486 CK_K6, 2487 CK_K6_2, 2488 CK_K6_3, 2489 //@} 2490 2491 /// \name K7 2492 /// K7 architecture processors. 2493 //@{ 2494 CK_Athlon, 2495 CK_AthlonThunderbird, 2496 CK_Athlon4, 2497 CK_AthlonXP, 2498 CK_AthlonMP, 2499 //@} 2500 2501 /// \name K8 2502 /// K8 architecture processors. 2503 //@{ 2504 CK_Athlon64, 2505 CK_Athlon64SSE3, 2506 CK_AthlonFX, 2507 CK_K8, 2508 CK_K8SSE3, 2509 CK_Opteron, 2510 CK_OpteronSSE3, 2511 CK_AMDFAM10, 2512 //@} 2513 2514 /// \name Bobcat 2515 /// Bobcat architecture processors. 2516 //@{ 2517 CK_BTVER1, 2518 CK_BTVER2, 2519 //@} 2520 2521 /// \name Bulldozer 2522 /// Bulldozer architecture processors. 2523 //@{ 2524 CK_BDVER1, 2525 CK_BDVER2, 2526 CK_BDVER3, 2527 CK_BDVER4, 2528 //@} 2529 2530 /// This specification is deprecated and will be removed in the future. 2531 /// Users should prefer \see CK_K8. 2532 // FIXME: Warn on this when the CPU is set to it. 2533 //@{ 2534 CK_x86_64, 2535 //@} 2536 2537 /// \name Geode 2538 /// Geode processors. 2539 //@{ 2540 CK_Geode 2541 //@} 2542 } CPU = CK_Generic; 2543 2544 CPUKind getCPUKind(StringRef CPU) const { 2545 return llvm::StringSwitch<CPUKind>(CPU) 2546 .Case("i386", CK_i386) 2547 .Case("i486", CK_i486) 2548 .Case("winchip-c6", CK_WinChipC6) 2549 .Case("winchip2", CK_WinChip2) 2550 .Case("c3", CK_C3) 2551 .Case("i586", CK_i586) 2552 .Case("pentium", CK_Pentium) 2553 .Case("pentium-mmx", CK_PentiumMMX) 2554 .Case("i686", CK_i686) 2555 .Case("pentiumpro", CK_PentiumPro) 2556 .Case("pentium2", CK_Pentium2) 2557 .Case("pentium3", CK_Pentium3) 2558 .Case("pentium3m", CK_Pentium3M) 2559 .Case("pentium-m", CK_PentiumM) 2560 .Case("c3-2", CK_C3_2) 2561 .Case("yonah", CK_Yonah) 2562 .Case("pentium4", CK_Pentium4) 2563 .Case("pentium4m", CK_Pentium4M) 2564 .Case("prescott", CK_Prescott) 2565 .Case("nocona", CK_Nocona) 2566 .Case("core2", CK_Core2) 2567 .Case("penryn", CK_Penryn) 2568 .Case("bonnell", CK_Bonnell) 2569 .Case("atom", CK_Bonnell) // Legacy name. 2570 .Case("silvermont", CK_Silvermont) 2571 .Case("slm", CK_Silvermont) // Legacy name. 2572 .Case("nehalem", CK_Nehalem) 2573 .Case("corei7", CK_Nehalem) // Legacy name. 2574 .Case("westmere", CK_Westmere) 2575 .Case("sandybridge", CK_SandyBridge) 2576 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2577 .Case("ivybridge", CK_IvyBridge) 2578 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2579 .Case("haswell", CK_Haswell) 2580 .Case("core-avx2", CK_Haswell) // Legacy name. 2581 .Case("broadwell", CK_Broadwell) 2582 .Case("skylake", CK_SkylakeClient) 2583 .Case("skylake-avx512", CK_SkylakeServer) 2584 .Case("skx", CK_SkylakeServer) // Legacy name. 2585 .Case("cannonlake", CK_Cannonlake) 2586 .Case("knl", CK_KNL) 2587 .Case("lakemont", CK_Lakemont) 2588 .Case("k6", CK_K6) 2589 .Case("k6-2", CK_K6_2) 2590 .Case("k6-3", CK_K6_3) 2591 .Case("athlon", CK_Athlon) 2592 .Case("athlon-tbird", CK_AthlonThunderbird) 2593 .Case("athlon-4", CK_Athlon4) 2594 .Case("athlon-xp", CK_AthlonXP) 2595 .Case("athlon-mp", CK_AthlonMP) 2596 .Case("athlon64", CK_Athlon64) 2597 .Case("athlon64-sse3", CK_Athlon64SSE3) 2598 .Case("athlon-fx", CK_AthlonFX) 2599 .Case("k8", CK_K8) 2600 .Case("k8-sse3", CK_K8SSE3) 2601 .Case("opteron", CK_Opteron) 2602 .Case("opteron-sse3", CK_OpteronSSE3) 2603 .Case("barcelona", CK_AMDFAM10) 2604 .Case("amdfam10", CK_AMDFAM10) 2605 .Case("btver1", CK_BTVER1) 2606 .Case("btver2", CK_BTVER2) 2607 .Case("bdver1", CK_BDVER1) 2608 .Case("bdver2", CK_BDVER2) 2609 .Case("bdver3", CK_BDVER3) 2610 .Case("bdver4", CK_BDVER4) 2611 .Case("x86-64", CK_x86_64) 2612 .Case("geode", CK_Geode) 2613 .Default(CK_Generic); 2614 } 2615 2616 enum FPMathKind { 2617 FP_Default, 2618 FP_SSE, 2619 FP_387 2620 } FPMath = FP_Default; 2621 2622 public: 2623 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2624 : TargetInfo(Triple) { 2625 BigEndian = false; 2626 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2627 } 2628 unsigned getFloatEvalMethod() const override { 2629 // X87 evaluates with 80 bits "long double" precision. 2630 return SSELevel == NoSSE ? 2 : 0; 2631 } 2632 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2633 return llvm::makeArrayRef(BuiltinInfo, 2634 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2635 } 2636 ArrayRef<const char *> getGCCRegNames() const override { 2637 return llvm::makeArrayRef(GCCRegNames); 2638 } 2639 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2640 return None; 2641 } 2642 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2643 return llvm::makeArrayRef(AddlRegNames); 2644 } 2645 bool validateCpuSupports(StringRef Name) const override; 2646 bool validateAsmConstraint(const char *&Name, 2647 TargetInfo::ConstraintInfo &info) const override; 2648 2649 bool validateGlobalRegisterVariable(StringRef RegName, 2650 unsigned RegSize, 2651 bool &HasSizeMismatch) const override { 2652 // esp and ebp are the only 32-bit registers the x86 backend can currently 2653 // handle. 2654 if (RegName.equals("esp") || RegName.equals("ebp")) { 2655 // Check that the register size is 32-bit. 2656 HasSizeMismatch = RegSize != 32; 2657 return true; 2658 } 2659 2660 return false; 2661 } 2662 2663 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2664 2665 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2666 2667 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2668 2669 std::string convertConstraint(const char *&Constraint) const override; 2670 const char *getClobbers() const override { 2671 return "~{dirflag},~{fpsr},~{flags}"; 2672 } 2673 void getTargetDefines(const LangOptions &Opts, 2674 MacroBuilder &Builder) const override; 2675 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2676 bool Enabled); 2677 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2678 bool Enabled); 2679 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2680 bool Enabled); 2681 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2682 StringRef Name, bool Enabled) const override { 2683 setFeatureEnabledImpl(Features, Name, Enabled); 2684 } 2685 // This exists purely to cut down on the number of virtual calls in 2686 // initFeatureMap which calls this repeatedly. 2687 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2688 StringRef Name, bool Enabled); 2689 bool 2690 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2691 StringRef CPU, 2692 const std::vector<std::string> &FeaturesVec) const override; 2693 bool hasFeature(StringRef Feature) const override; 2694 bool handleTargetFeatures(std::vector<std::string> &Features, 2695 DiagnosticsEngine &Diags) override; 2696 StringRef getABI() const override { 2697 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2698 return "avx512"; 2699 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2700 return "avx"; 2701 if (getTriple().getArch() == llvm::Triple::x86 && 2702 MMX3DNowLevel == NoMMX3DNow) 2703 return "no-mmx"; 2704 return ""; 2705 } 2706 bool setCPU(const std::string &Name) override { 2707 CPU = getCPUKind(Name); 2708 2709 // Perform any per-CPU checks necessary to determine if this CPU is 2710 // acceptable. 2711 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2712 // invalid without explaining *why*. 2713 switch (CPU) { 2714 case CK_Generic: 2715 // No processor selected! 2716 return false; 2717 2718 case CK_i386: 2719 case CK_i486: 2720 case CK_WinChipC6: 2721 case CK_WinChip2: 2722 case CK_C3: 2723 case CK_i586: 2724 case CK_Pentium: 2725 case CK_PentiumMMX: 2726 case CK_i686: 2727 case CK_PentiumPro: 2728 case CK_Pentium2: 2729 case CK_Pentium3: 2730 case CK_Pentium3M: 2731 case CK_PentiumM: 2732 case CK_Yonah: 2733 case CK_C3_2: 2734 case CK_Pentium4: 2735 case CK_Pentium4M: 2736 case CK_Lakemont: 2737 case CK_Prescott: 2738 case CK_K6: 2739 case CK_K6_2: 2740 case CK_K6_3: 2741 case CK_Athlon: 2742 case CK_AthlonThunderbird: 2743 case CK_Athlon4: 2744 case CK_AthlonXP: 2745 case CK_AthlonMP: 2746 case CK_Geode: 2747 // Only accept certain architectures when compiling in 32-bit mode. 2748 if (getTriple().getArch() != llvm::Triple::x86) 2749 return false; 2750 2751 // Fallthrough 2752 case CK_Nocona: 2753 case CK_Core2: 2754 case CK_Penryn: 2755 case CK_Bonnell: 2756 case CK_Silvermont: 2757 case CK_Nehalem: 2758 case CK_Westmere: 2759 case CK_SandyBridge: 2760 case CK_IvyBridge: 2761 case CK_Haswell: 2762 case CK_Broadwell: 2763 case CK_SkylakeClient: 2764 case CK_SkylakeServer: 2765 case CK_Cannonlake: 2766 case CK_KNL: 2767 case CK_Athlon64: 2768 case CK_Athlon64SSE3: 2769 case CK_AthlonFX: 2770 case CK_K8: 2771 case CK_K8SSE3: 2772 case CK_Opteron: 2773 case CK_OpteronSSE3: 2774 case CK_AMDFAM10: 2775 case CK_BTVER1: 2776 case CK_BTVER2: 2777 case CK_BDVER1: 2778 case CK_BDVER2: 2779 case CK_BDVER3: 2780 case CK_BDVER4: 2781 case CK_x86_64: 2782 return true; 2783 } 2784 llvm_unreachable("Unhandled CPU kind"); 2785 } 2786 2787 bool setFPMath(StringRef Name) override; 2788 2789 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2790 // Most of the non-ARM calling conventions are i386 conventions. 2791 switch (CC) { 2792 case CC_X86ThisCall: 2793 case CC_X86FastCall: 2794 case CC_X86StdCall: 2795 case CC_X86VectorCall: 2796 case CC_C: 2797 case CC_Swift: 2798 case CC_X86Pascal: 2799 case CC_IntelOclBicc: 2800 return CCCR_OK; 2801 default: 2802 return CCCR_Warning; 2803 } 2804 } 2805 2806 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2807 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2808 } 2809 2810 bool hasSjLjLowering() const override { 2811 return true; 2812 } 2813 2814 void setSupportedOpenCLOpts() override { 2815 getSupportedOpenCLOpts().setAll(); 2816 } 2817 }; 2818 2819 bool X86TargetInfo::setFPMath(StringRef Name) { 2820 if (Name == "387") { 2821 FPMath = FP_387; 2822 return true; 2823 } 2824 if (Name == "sse") { 2825 FPMath = FP_SSE; 2826 return true; 2827 } 2828 return false; 2829 } 2830 2831 bool X86TargetInfo::initFeatureMap( 2832 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2833 const std::vector<std::string> &FeaturesVec) const { 2834 // FIXME: This *really* should not be here. 2835 // X86_64 always has SSE2. 2836 if (getTriple().getArch() == llvm::Triple::x86_64) 2837 setFeatureEnabledImpl(Features, "sse2", true); 2838 2839 const CPUKind Kind = getCPUKind(CPU); 2840 2841 // Enable X87 for all X86 processors but Lakemont. 2842 if (Kind != CK_Lakemont) 2843 setFeatureEnabledImpl(Features, "x87", true); 2844 2845 switch (Kind) { 2846 case CK_Generic: 2847 case CK_i386: 2848 case CK_i486: 2849 case CK_i586: 2850 case CK_Pentium: 2851 case CK_i686: 2852 case CK_PentiumPro: 2853 case CK_Lakemont: 2854 break; 2855 case CK_PentiumMMX: 2856 case CK_Pentium2: 2857 case CK_K6: 2858 case CK_WinChipC6: 2859 setFeatureEnabledImpl(Features, "mmx", true); 2860 break; 2861 case CK_Pentium3: 2862 case CK_Pentium3M: 2863 case CK_C3_2: 2864 setFeatureEnabledImpl(Features, "sse", true); 2865 setFeatureEnabledImpl(Features, "fxsr", true); 2866 break; 2867 case CK_PentiumM: 2868 case CK_Pentium4: 2869 case CK_Pentium4M: 2870 case CK_x86_64: 2871 setFeatureEnabledImpl(Features, "sse2", true); 2872 setFeatureEnabledImpl(Features, "fxsr", true); 2873 break; 2874 case CK_Yonah: 2875 case CK_Prescott: 2876 case CK_Nocona: 2877 setFeatureEnabledImpl(Features, "sse3", true); 2878 setFeatureEnabledImpl(Features, "fxsr", true); 2879 setFeatureEnabledImpl(Features, "cx16", true); 2880 break; 2881 case CK_Core2: 2882 case CK_Bonnell: 2883 setFeatureEnabledImpl(Features, "ssse3", true); 2884 setFeatureEnabledImpl(Features, "fxsr", true); 2885 setFeatureEnabledImpl(Features, "cx16", true); 2886 break; 2887 case CK_Penryn: 2888 setFeatureEnabledImpl(Features, "sse4.1", true); 2889 setFeatureEnabledImpl(Features, "fxsr", true); 2890 setFeatureEnabledImpl(Features, "cx16", true); 2891 break; 2892 case CK_Cannonlake: 2893 setFeatureEnabledImpl(Features, "avx512ifma", true); 2894 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2895 setFeatureEnabledImpl(Features, "sha", true); 2896 setFeatureEnabledImpl(Features, "umip", true); 2897 // FALLTHROUGH 2898 case CK_SkylakeServer: 2899 setFeatureEnabledImpl(Features, "avx512f", true); 2900 setFeatureEnabledImpl(Features, "avx512cd", true); 2901 setFeatureEnabledImpl(Features, "avx512dq", true); 2902 setFeatureEnabledImpl(Features, "avx512bw", true); 2903 setFeatureEnabledImpl(Features, "avx512vl", true); 2904 setFeatureEnabledImpl(Features, "pku", true); 2905 setFeatureEnabledImpl(Features, "pcommit", true); 2906 setFeatureEnabledImpl(Features, "clwb", true); 2907 // FALLTHROUGH 2908 case CK_SkylakeClient: 2909 setFeatureEnabledImpl(Features, "xsavec", true); 2910 setFeatureEnabledImpl(Features, "xsaves", true); 2911 setFeatureEnabledImpl(Features, "mpx", true); 2912 setFeatureEnabledImpl(Features, "sgx", true); 2913 setFeatureEnabledImpl(Features, "clflushopt", true); 2914 // FALLTHROUGH 2915 case CK_Broadwell: 2916 setFeatureEnabledImpl(Features, "rdseed", true); 2917 setFeatureEnabledImpl(Features, "adx", true); 2918 // FALLTHROUGH 2919 case CK_Haswell: 2920 setFeatureEnabledImpl(Features, "avx2", true); 2921 setFeatureEnabledImpl(Features, "lzcnt", true); 2922 setFeatureEnabledImpl(Features, "bmi", true); 2923 setFeatureEnabledImpl(Features, "bmi2", true); 2924 setFeatureEnabledImpl(Features, "rtm", true); 2925 setFeatureEnabledImpl(Features, "fma", true); 2926 setFeatureEnabledImpl(Features, "movbe", true); 2927 // FALLTHROUGH 2928 case CK_IvyBridge: 2929 setFeatureEnabledImpl(Features, "rdrnd", true); 2930 setFeatureEnabledImpl(Features, "f16c", true); 2931 setFeatureEnabledImpl(Features, "fsgsbase", true); 2932 // FALLTHROUGH 2933 case CK_SandyBridge: 2934 setFeatureEnabledImpl(Features, "avx", true); 2935 setFeatureEnabledImpl(Features, "xsave", true); 2936 setFeatureEnabledImpl(Features, "xsaveopt", true); 2937 // FALLTHROUGH 2938 case CK_Westmere: 2939 case CK_Silvermont: 2940 setFeatureEnabledImpl(Features, "aes", true); 2941 setFeatureEnabledImpl(Features, "pclmul", true); 2942 // FALLTHROUGH 2943 case CK_Nehalem: 2944 setFeatureEnabledImpl(Features, "sse4.2", true); 2945 setFeatureEnabledImpl(Features, "fxsr", true); 2946 setFeatureEnabledImpl(Features, "cx16", true); 2947 break; 2948 case CK_KNL: 2949 setFeatureEnabledImpl(Features, "avx512f", true); 2950 setFeatureEnabledImpl(Features, "avx512cd", true); 2951 setFeatureEnabledImpl(Features, "avx512er", true); 2952 setFeatureEnabledImpl(Features, "avx512pf", true); 2953 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2954 setFeatureEnabledImpl(Features, "fxsr", true); 2955 setFeatureEnabledImpl(Features, "rdseed", true); 2956 setFeatureEnabledImpl(Features, "adx", true); 2957 setFeatureEnabledImpl(Features, "lzcnt", true); 2958 setFeatureEnabledImpl(Features, "bmi", true); 2959 setFeatureEnabledImpl(Features, "bmi2", true); 2960 setFeatureEnabledImpl(Features, "rtm", true); 2961 setFeatureEnabledImpl(Features, "fma", true); 2962 setFeatureEnabledImpl(Features, "rdrnd", true); 2963 setFeatureEnabledImpl(Features, "f16c", true); 2964 setFeatureEnabledImpl(Features, "fsgsbase", true); 2965 setFeatureEnabledImpl(Features, "aes", true); 2966 setFeatureEnabledImpl(Features, "pclmul", true); 2967 setFeatureEnabledImpl(Features, "cx16", true); 2968 setFeatureEnabledImpl(Features, "xsaveopt", true); 2969 setFeatureEnabledImpl(Features, "xsave", true); 2970 setFeatureEnabledImpl(Features, "movbe", true); 2971 break; 2972 case CK_K6_2: 2973 case CK_K6_3: 2974 case CK_WinChip2: 2975 case CK_C3: 2976 setFeatureEnabledImpl(Features, "3dnow", true); 2977 break; 2978 case CK_Athlon: 2979 case CK_AthlonThunderbird: 2980 case CK_Geode: 2981 setFeatureEnabledImpl(Features, "3dnowa", true); 2982 break; 2983 case CK_Athlon4: 2984 case CK_AthlonXP: 2985 case CK_AthlonMP: 2986 setFeatureEnabledImpl(Features, "sse", true); 2987 setFeatureEnabledImpl(Features, "3dnowa", true); 2988 setFeatureEnabledImpl(Features, "fxsr", true); 2989 break; 2990 case CK_K8: 2991 case CK_Opteron: 2992 case CK_Athlon64: 2993 case CK_AthlonFX: 2994 setFeatureEnabledImpl(Features, "sse2", true); 2995 setFeatureEnabledImpl(Features, "3dnowa", true); 2996 setFeatureEnabledImpl(Features, "fxsr", true); 2997 break; 2998 case CK_AMDFAM10: 2999 setFeatureEnabledImpl(Features, "sse4a", true); 3000 setFeatureEnabledImpl(Features, "lzcnt", true); 3001 setFeatureEnabledImpl(Features, "popcnt", true); 3002 // FALLTHROUGH 3003 case CK_K8SSE3: 3004 case CK_OpteronSSE3: 3005 case CK_Athlon64SSE3: 3006 setFeatureEnabledImpl(Features, "sse3", true); 3007 setFeatureEnabledImpl(Features, "3dnowa", true); 3008 setFeatureEnabledImpl(Features, "fxsr", true); 3009 break; 3010 case CK_BTVER2: 3011 setFeatureEnabledImpl(Features, "avx", true); 3012 setFeatureEnabledImpl(Features, "aes", true); 3013 setFeatureEnabledImpl(Features, "pclmul", true); 3014 setFeatureEnabledImpl(Features, "bmi", true); 3015 setFeatureEnabledImpl(Features, "f16c", true); 3016 setFeatureEnabledImpl(Features, "xsaveopt", true); 3017 // FALLTHROUGH 3018 case CK_BTVER1: 3019 setFeatureEnabledImpl(Features, "ssse3", true); 3020 setFeatureEnabledImpl(Features, "sse4a", true); 3021 setFeatureEnabledImpl(Features, "lzcnt", true); 3022 setFeatureEnabledImpl(Features, "popcnt", true); 3023 setFeatureEnabledImpl(Features, "prfchw", true); 3024 setFeatureEnabledImpl(Features, "cx16", true); 3025 setFeatureEnabledImpl(Features, "fxsr", true); 3026 break; 3027 case CK_BDVER4: 3028 setFeatureEnabledImpl(Features, "avx2", true); 3029 setFeatureEnabledImpl(Features, "bmi2", true); 3030 setFeatureEnabledImpl(Features, "mwaitx", true); 3031 // FALLTHROUGH 3032 case CK_BDVER3: 3033 setFeatureEnabledImpl(Features, "fsgsbase", true); 3034 setFeatureEnabledImpl(Features, "xsaveopt", true); 3035 // FALLTHROUGH 3036 case CK_BDVER2: 3037 setFeatureEnabledImpl(Features, "bmi", true); 3038 setFeatureEnabledImpl(Features, "fma", true); 3039 setFeatureEnabledImpl(Features, "f16c", true); 3040 setFeatureEnabledImpl(Features, "tbm", true); 3041 // FALLTHROUGH 3042 case CK_BDVER1: 3043 // xop implies avx, sse4a and fma4. 3044 setFeatureEnabledImpl(Features, "xop", true); 3045 setFeatureEnabledImpl(Features, "lzcnt", true); 3046 setFeatureEnabledImpl(Features, "aes", true); 3047 setFeatureEnabledImpl(Features, "pclmul", true); 3048 setFeatureEnabledImpl(Features, "prfchw", true); 3049 setFeatureEnabledImpl(Features, "cx16", true); 3050 setFeatureEnabledImpl(Features, "fxsr", true); 3051 setFeatureEnabledImpl(Features, "xsave", true); 3052 break; 3053 } 3054 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3055 return false; 3056 3057 // Can't do this earlier because we need to be able to explicitly enable 3058 // or disable these features and the things that they depend upon. 3059 3060 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3061 auto I = Features.find("sse4.2"); 3062 if (I != Features.end() && I->getValue() && 3063 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3064 FeaturesVec.end()) 3065 Features["popcnt"] = true; 3066 3067 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3068 I = Features.find("3dnow"); 3069 if (I != Features.end() && I->getValue() && 3070 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3071 FeaturesVec.end()) 3072 Features["prfchw"] = true; 3073 3074 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3075 // then enable MMX. 3076 I = Features.find("sse"); 3077 if (I != Features.end() && I->getValue() && 3078 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3079 FeaturesVec.end()) 3080 Features["mmx"] = true; 3081 3082 return true; 3083 } 3084 3085 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3086 X86SSEEnum Level, bool Enabled) { 3087 if (Enabled) { 3088 switch (Level) { 3089 case AVX512F: 3090 Features["avx512f"] = true; 3091 case AVX2: 3092 Features["avx2"] = true; 3093 case AVX: 3094 Features["avx"] = true; 3095 Features["xsave"] = true; 3096 case SSE42: 3097 Features["sse4.2"] = true; 3098 case SSE41: 3099 Features["sse4.1"] = true; 3100 case SSSE3: 3101 Features["ssse3"] = true; 3102 case SSE3: 3103 Features["sse3"] = true; 3104 case SSE2: 3105 Features["sse2"] = true; 3106 case SSE1: 3107 Features["sse"] = true; 3108 case NoSSE: 3109 break; 3110 } 3111 return; 3112 } 3113 3114 switch (Level) { 3115 case NoSSE: 3116 case SSE1: 3117 Features["sse"] = false; 3118 case SSE2: 3119 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3120 Features["sha"] = false; 3121 case SSE3: 3122 Features["sse3"] = false; 3123 setXOPLevel(Features, NoXOP, false); 3124 case SSSE3: 3125 Features["ssse3"] = false; 3126 case SSE41: 3127 Features["sse4.1"] = false; 3128 case SSE42: 3129 Features["sse4.2"] = false; 3130 case AVX: 3131 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3132 Features["xsaveopt"] = false; 3133 setXOPLevel(Features, FMA4, false); 3134 case AVX2: 3135 Features["avx2"] = false; 3136 case AVX512F: 3137 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3138 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3139 Features["avx512vl"] = Features["avx512vbmi"] = 3140 Features["avx512ifma"] = false; 3141 } 3142 } 3143 3144 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3145 MMX3DNowEnum Level, bool Enabled) { 3146 if (Enabled) { 3147 switch (Level) { 3148 case AMD3DNowAthlon: 3149 Features["3dnowa"] = true; 3150 case AMD3DNow: 3151 Features["3dnow"] = true; 3152 case MMX: 3153 Features["mmx"] = true; 3154 case NoMMX3DNow: 3155 break; 3156 } 3157 return; 3158 } 3159 3160 switch (Level) { 3161 case NoMMX3DNow: 3162 case MMX: 3163 Features["mmx"] = false; 3164 case AMD3DNow: 3165 Features["3dnow"] = false; 3166 case AMD3DNowAthlon: 3167 Features["3dnowa"] = false; 3168 } 3169 } 3170 3171 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3172 bool Enabled) { 3173 if (Enabled) { 3174 switch (Level) { 3175 case XOP: 3176 Features["xop"] = true; 3177 case FMA4: 3178 Features["fma4"] = true; 3179 setSSELevel(Features, AVX, true); 3180 case SSE4A: 3181 Features["sse4a"] = true; 3182 setSSELevel(Features, SSE3, true); 3183 case NoXOP: 3184 break; 3185 } 3186 return; 3187 } 3188 3189 switch (Level) { 3190 case NoXOP: 3191 case SSE4A: 3192 Features["sse4a"] = false; 3193 case FMA4: 3194 Features["fma4"] = false; 3195 case XOP: 3196 Features["xop"] = false; 3197 } 3198 } 3199 3200 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3201 StringRef Name, bool Enabled) { 3202 // This is a bit of a hack to deal with the sse4 target feature when used 3203 // as part of the target attribute. We handle sse4 correctly everywhere 3204 // else. See below for more information on how we handle the sse4 options. 3205 if (Name != "sse4") 3206 Features[Name] = Enabled; 3207 3208 if (Name == "mmx") { 3209 setMMXLevel(Features, MMX, Enabled); 3210 } else if (Name == "sse") { 3211 setSSELevel(Features, SSE1, Enabled); 3212 } else if (Name == "sse2") { 3213 setSSELevel(Features, SSE2, Enabled); 3214 } else if (Name == "sse3") { 3215 setSSELevel(Features, SSE3, Enabled); 3216 } else if (Name == "ssse3") { 3217 setSSELevel(Features, SSSE3, Enabled); 3218 } else if (Name == "sse4.2") { 3219 setSSELevel(Features, SSE42, Enabled); 3220 } else if (Name == "sse4.1") { 3221 setSSELevel(Features, SSE41, Enabled); 3222 } else if (Name == "3dnow") { 3223 setMMXLevel(Features, AMD3DNow, Enabled); 3224 } else if (Name == "3dnowa") { 3225 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3226 } else if (Name == "aes") { 3227 if (Enabled) 3228 setSSELevel(Features, SSE2, Enabled); 3229 } else if (Name == "pclmul") { 3230 if (Enabled) 3231 setSSELevel(Features, SSE2, Enabled); 3232 } else if (Name == "avx") { 3233 setSSELevel(Features, AVX, Enabled); 3234 } else if (Name == "avx2") { 3235 setSSELevel(Features, AVX2, Enabled); 3236 } else if (Name == "avx512f") { 3237 setSSELevel(Features, AVX512F, Enabled); 3238 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3239 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3240 Name == "avx512vbmi" || Name == "avx512ifma") { 3241 if (Enabled) 3242 setSSELevel(Features, AVX512F, Enabled); 3243 } else if (Name == "fma") { 3244 if (Enabled) 3245 setSSELevel(Features, AVX, Enabled); 3246 } else if (Name == "fma4") { 3247 setXOPLevel(Features, FMA4, Enabled); 3248 } else if (Name == "xop") { 3249 setXOPLevel(Features, XOP, Enabled); 3250 } else if (Name == "sse4a") { 3251 setXOPLevel(Features, SSE4A, Enabled); 3252 } else if (Name == "f16c") { 3253 if (Enabled) 3254 setSSELevel(Features, AVX, Enabled); 3255 } else if (Name == "sha") { 3256 if (Enabled) 3257 setSSELevel(Features, SSE2, Enabled); 3258 } else if (Name == "sse4") { 3259 // We can get here via the __target__ attribute since that's not controlled 3260 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3261 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3262 // disabled. 3263 if (Enabled) 3264 setSSELevel(Features, SSE42, Enabled); 3265 else 3266 setSSELevel(Features, SSE41, Enabled); 3267 } else if (Name == "xsave") { 3268 if (!Enabled) 3269 Features["xsaveopt"] = false; 3270 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3271 if (Enabled) 3272 Features["xsave"] = true; 3273 } 3274 } 3275 3276 /// handleTargetFeatures - Perform initialization based on the user 3277 /// configured set of features. 3278 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3279 DiagnosticsEngine &Diags) { 3280 for (const auto &Feature : Features) { 3281 if (Feature[0] != '+') 3282 continue; 3283 3284 if (Feature == "+aes") { 3285 HasAES = true; 3286 } else if (Feature == "+pclmul") { 3287 HasPCLMUL = true; 3288 } else if (Feature == "+lzcnt") { 3289 HasLZCNT = true; 3290 } else if (Feature == "+rdrnd") { 3291 HasRDRND = true; 3292 } else if (Feature == "+fsgsbase") { 3293 HasFSGSBASE = true; 3294 } else if (Feature == "+bmi") { 3295 HasBMI = true; 3296 } else if (Feature == "+bmi2") { 3297 HasBMI2 = true; 3298 } else if (Feature == "+popcnt") { 3299 HasPOPCNT = true; 3300 } else if (Feature == "+rtm") { 3301 HasRTM = true; 3302 } else if (Feature == "+prfchw") { 3303 HasPRFCHW = true; 3304 } else if (Feature == "+rdseed") { 3305 HasRDSEED = true; 3306 } else if (Feature == "+adx") { 3307 HasADX = true; 3308 } else if (Feature == "+tbm") { 3309 HasTBM = true; 3310 } else if (Feature == "+fma") { 3311 HasFMA = true; 3312 } else if (Feature == "+f16c") { 3313 HasF16C = true; 3314 } else if (Feature == "+avx512cd") { 3315 HasAVX512CD = true; 3316 } else if (Feature == "+avx512er") { 3317 HasAVX512ER = true; 3318 } else if (Feature == "+avx512pf") { 3319 HasAVX512PF = true; 3320 } else if (Feature == "+avx512dq") { 3321 HasAVX512DQ = true; 3322 } else if (Feature == "+avx512bw") { 3323 HasAVX512BW = true; 3324 } else if (Feature == "+avx512vl") { 3325 HasAVX512VL = true; 3326 } else if (Feature == "+avx512vbmi") { 3327 HasAVX512VBMI = true; 3328 } else if (Feature == "+avx512ifma") { 3329 HasAVX512IFMA = true; 3330 } else if (Feature == "+sha") { 3331 HasSHA = true; 3332 } else if (Feature == "+mpx") { 3333 HasMPX = true; 3334 } else if (Feature == "+movbe") { 3335 HasMOVBE = true; 3336 } else if (Feature == "+sgx") { 3337 HasSGX = true; 3338 } else if (Feature == "+cx16") { 3339 HasCX16 = true; 3340 } else if (Feature == "+fxsr") { 3341 HasFXSR = true; 3342 } else if (Feature == "+xsave") { 3343 HasXSAVE = true; 3344 } else if (Feature == "+xsaveopt") { 3345 HasXSAVEOPT = true; 3346 } else if (Feature == "+xsavec") { 3347 HasXSAVEC = true; 3348 } else if (Feature == "+xsaves") { 3349 HasXSAVES = true; 3350 } else if (Feature == "+mwaitx") { 3351 HasMWAITX = true; 3352 } else if (Feature == "+pku") { 3353 HasPKU = true; 3354 } else if (Feature == "+clflushopt") { 3355 HasCLFLUSHOPT = true; 3356 } else if (Feature == "+pcommit") { 3357 HasPCOMMIT = true; 3358 } else if (Feature == "+clwb") { 3359 HasCLWB = true; 3360 } else if (Feature == "+umip") { 3361 HasUMIP = true; 3362 } else if (Feature == "+prefetchwt1") { 3363 HasPREFETCHWT1 = true; 3364 } 3365 3366 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3367 .Case("+avx512f", AVX512F) 3368 .Case("+avx2", AVX2) 3369 .Case("+avx", AVX) 3370 .Case("+sse4.2", SSE42) 3371 .Case("+sse4.1", SSE41) 3372 .Case("+ssse3", SSSE3) 3373 .Case("+sse3", SSE3) 3374 .Case("+sse2", SSE2) 3375 .Case("+sse", SSE1) 3376 .Default(NoSSE); 3377 SSELevel = std::max(SSELevel, Level); 3378 3379 MMX3DNowEnum ThreeDNowLevel = 3380 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3381 .Case("+3dnowa", AMD3DNowAthlon) 3382 .Case("+3dnow", AMD3DNow) 3383 .Case("+mmx", MMX) 3384 .Default(NoMMX3DNow); 3385 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3386 3387 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3388 .Case("+xop", XOP) 3389 .Case("+fma4", FMA4) 3390 .Case("+sse4a", SSE4A) 3391 .Default(NoXOP); 3392 XOPLevel = std::max(XOPLevel, XLevel); 3393 } 3394 3395 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3396 // matches the selected sse level. 3397 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3398 (FPMath == FP_387 && SSELevel >= SSE1)) { 3399 Diags.Report(diag::err_target_unsupported_fpmath) << 3400 (FPMath == FP_SSE ? "sse" : "387"); 3401 return false; 3402 } 3403 3404 SimdDefaultAlign = 3405 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3406 return true; 3407 } 3408 3409 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3410 /// definitions for this particular subtarget. 3411 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3412 MacroBuilder &Builder) const { 3413 // Target identification. 3414 if (getTriple().getArch() == llvm::Triple::x86_64) { 3415 Builder.defineMacro("__amd64__"); 3416 Builder.defineMacro("__amd64"); 3417 Builder.defineMacro("__x86_64"); 3418 Builder.defineMacro("__x86_64__"); 3419 if (getTriple().getArchName() == "x86_64h") { 3420 Builder.defineMacro("__x86_64h"); 3421 Builder.defineMacro("__x86_64h__"); 3422 } 3423 } else { 3424 DefineStd(Builder, "i386", Opts); 3425 } 3426 3427 // Subtarget options. 3428 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3429 // truly should be based on -mtune options. 3430 switch (CPU) { 3431 case CK_Generic: 3432 break; 3433 case CK_i386: 3434 // The rest are coming from the i386 define above. 3435 Builder.defineMacro("__tune_i386__"); 3436 break; 3437 case CK_i486: 3438 case CK_WinChipC6: 3439 case CK_WinChip2: 3440 case CK_C3: 3441 defineCPUMacros(Builder, "i486"); 3442 break; 3443 case CK_PentiumMMX: 3444 Builder.defineMacro("__pentium_mmx__"); 3445 Builder.defineMacro("__tune_pentium_mmx__"); 3446 // Fallthrough 3447 case CK_i586: 3448 case CK_Pentium: 3449 defineCPUMacros(Builder, "i586"); 3450 defineCPUMacros(Builder, "pentium"); 3451 break; 3452 case CK_Pentium3: 3453 case CK_Pentium3M: 3454 case CK_PentiumM: 3455 Builder.defineMacro("__tune_pentium3__"); 3456 // Fallthrough 3457 case CK_Pentium2: 3458 case CK_C3_2: 3459 Builder.defineMacro("__tune_pentium2__"); 3460 // Fallthrough 3461 case CK_PentiumPro: 3462 Builder.defineMacro("__tune_i686__"); 3463 Builder.defineMacro("__tune_pentiumpro__"); 3464 // Fallthrough 3465 case CK_i686: 3466 Builder.defineMacro("__i686"); 3467 Builder.defineMacro("__i686__"); 3468 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3469 Builder.defineMacro("__pentiumpro"); 3470 Builder.defineMacro("__pentiumpro__"); 3471 break; 3472 case CK_Pentium4: 3473 case CK_Pentium4M: 3474 defineCPUMacros(Builder, "pentium4"); 3475 break; 3476 case CK_Yonah: 3477 case CK_Prescott: 3478 case CK_Nocona: 3479 defineCPUMacros(Builder, "nocona"); 3480 break; 3481 case CK_Core2: 3482 case CK_Penryn: 3483 defineCPUMacros(Builder, "core2"); 3484 break; 3485 case CK_Bonnell: 3486 defineCPUMacros(Builder, "atom"); 3487 break; 3488 case CK_Silvermont: 3489 defineCPUMacros(Builder, "slm"); 3490 break; 3491 case CK_Nehalem: 3492 case CK_Westmere: 3493 case CK_SandyBridge: 3494 case CK_IvyBridge: 3495 case CK_Haswell: 3496 case CK_Broadwell: 3497 case CK_SkylakeClient: 3498 // FIXME: Historically, we defined this legacy name, it would be nice to 3499 // remove it at some point. We've never exposed fine-grained names for 3500 // recent primary x86 CPUs, and we should keep it that way. 3501 defineCPUMacros(Builder, "corei7"); 3502 break; 3503 case CK_SkylakeServer: 3504 defineCPUMacros(Builder, "skx"); 3505 break; 3506 case CK_Cannonlake: 3507 break; 3508 case CK_KNL: 3509 defineCPUMacros(Builder, "knl"); 3510 break; 3511 case CK_Lakemont: 3512 Builder.defineMacro("__tune_lakemont__"); 3513 break; 3514 case CK_K6_2: 3515 Builder.defineMacro("__k6_2__"); 3516 Builder.defineMacro("__tune_k6_2__"); 3517 // Fallthrough 3518 case CK_K6_3: 3519 if (CPU != CK_K6_2) { // In case of fallthrough 3520 // FIXME: GCC may be enabling these in cases where some other k6 3521 // architecture is specified but -m3dnow is explicitly provided. The 3522 // exact semantics need to be determined and emulated here. 3523 Builder.defineMacro("__k6_3__"); 3524 Builder.defineMacro("__tune_k6_3__"); 3525 } 3526 // Fallthrough 3527 case CK_K6: 3528 defineCPUMacros(Builder, "k6"); 3529 break; 3530 case CK_Athlon: 3531 case CK_AthlonThunderbird: 3532 case CK_Athlon4: 3533 case CK_AthlonXP: 3534 case CK_AthlonMP: 3535 defineCPUMacros(Builder, "athlon"); 3536 if (SSELevel != NoSSE) { 3537 Builder.defineMacro("__athlon_sse__"); 3538 Builder.defineMacro("__tune_athlon_sse__"); 3539 } 3540 break; 3541 case CK_K8: 3542 case CK_K8SSE3: 3543 case CK_x86_64: 3544 case CK_Opteron: 3545 case CK_OpteronSSE3: 3546 case CK_Athlon64: 3547 case CK_Athlon64SSE3: 3548 case CK_AthlonFX: 3549 defineCPUMacros(Builder, "k8"); 3550 break; 3551 case CK_AMDFAM10: 3552 defineCPUMacros(Builder, "amdfam10"); 3553 break; 3554 case CK_BTVER1: 3555 defineCPUMacros(Builder, "btver1"); 3556 break; 3557 case CK_BTVER2: 3558 defineCPUMacros(Builder, "btver2"); 3559 break; 3560 case CK_BDVER1: 3561 defineCPUMacros(Builder, "bdver1"); 3562 break; 3563 case CK_BDVER2: 3564 defineCPUMacros(Builder, "bdver2"); 3565 break; 3566 case CK_BDVER3: 3567 defineCPUMacros(Builder, "bdver3"); 3568 break; 3569 case CK_BDVER4: 3570 defineCPUMacros(Builder, "bdver4"); 3571 break; 3572 case CK_Geode: 3573 defineCPUMacros(Builder, "geode"); 3574 break; 3575 } 3576 3577 // Target properties. 3578 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3579 3580 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3581 // functions in glibc header files that use FP Stack inline asm which the 3582 // backend can't deal with (PR879). 3583 Builder.defineMacro("__NO_MATH_INLINES"); 3584 3585 if (HasAES) 3586 Builder.defineMacro("__AES__"); 3587 3588 if (HasPCLMUL) 3589 Builder.defineMacro("__PCLMUL__"); 3590 3591 if (HasLZCNT) 3592 Builder.defineMacro("__LZCNT__"); 3593 3594 if (HasRDRND) 3595 Builder.defineMacro("__RDRND__"); 3596 3597 if (HasFSGSBASE) 3598 Builder.defineMacro("__FSGSBASE__"); 3599 3600 if (HasBMI) 3601 Builder.defineMacro("__BMI__"); 3602 3603 if (HasBMI2) 3604 Builder.defineMacro("__BMI2__"); 3605 3606 if (HasPOPCNT) 3607 Builder.defineMacro("__POPCNT__"); 3608 3609 if (HasRTM) 3610 Builder.defineMacro("__RTM__"); 3611 3612 if (HasPRFCHW) 3613 Builder.defineMacro("__PRFCHW__"); 3614 3615 if (HasRDSEED) 3616 Builder.defineMacro("__RDSEED__"); 3617 3618 if (HasADX) 3619 Builder.defineMacro("__ADX__"); 3620 3621 if (HasTBM) 3622 Builder.defineMacro("__TBM__"); 3623 3624 if (HasMWAITX) 3625 Builder.defineMacro("__MWAITX__"); 3626 3627 switch (XOPLevel) { 3628 case XOP: 3629 Builder.defineMacro("__XOP__"); 3630 case FMA4: 3631 Builder.defineMacro("__FMA4__"); 3632 case SSE4A: 3633 Builder.defineMacro("__SSE4A__"); 3634 case NoXOP: 3635 break; 3636 } 3637 3638 if (HasFMA) 3639 Builder.defineMacro("__FMA__"); 3640 3641 if (HasF16C) 3642 Builder.defineMacro("__F16C__"); 3643 3644 if (HasAVX512CD) 3645 Builder.defineMacro("__AVX512CD__"); 3646 if (HasAVX512ER) 3647 Builder.defineMacro("__AVX512ER__"); 3648 if (HasAVX512PF) 3649 Builder.defineMacro("__AVX512PF__"); 3650 if (HasAVX512DQ) 3651 Builder.defineMacro("__AVX512DQ__"); 3652 if (HasAVX512BW) 3653 Builder.defineMacro("__AVX512BW__"); 3654 if (HasAVX512VL) 3655 Builder.defineMacro("__AVX512VL__"); 3656 if (HasAVX512VBMI) 3657 Builder.defineMacro("__AVX512VBMI__"); 3658 if (HasAVX512IFMA) 3659 Builder.defineMacro("__AVX512IFMA__"); 3660 3661 if (HasSHA) 3662 Builder.defineMacro("__SHA__"); 3663 3664 if (HasFXSR) 3665 Builder.defineMacro("__FXSR__"); 3666 if (HasXSAVE) 3667 Builder.defineMacro("__XSAVE__"); 3668 if (HasXSAVEOPT) 3669 Builder.defineMacro("__XSAVEOPT__"); 3670 if (HasXSAVEC) 3671 Builder.defineMacro("__XSAVEC__"); 3672 if (HasXSAVES) 3673 Builder.defineMacro("__XSAVES__"); 3674 if (HasPKU) 3675 Builder.defineMacro("__PKU__"); 3676 if (HasCX16) 3677 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3678 3679 // Each case falls through to the previous one here. 3680 switch (SSELevel) { 3681 case AVX512F: 3682 Builder.defineMacro("__AVX512F__"); 3683 case AVX2: 3684 Builder.defineMacro("__AVX2__"); 3685 case AVX: 3686 Builder.defineMacro("__AVX__"); 3687 case SSE42: 3688 Builder.defineMacro("__SSE4_2__"); 3689 case SSE41: 3690 Builder.defineMacro("__SSE4_1__"); 3691 case SSSE3: 3692 Builder.defineMacro("__SSSE3__"); 3693 case SSE3: 3694 Builder.defineMacro("__SSE3__"); 3695 case SSE2: 3696 Builder.defineMacro("__SSE2__"); 3697 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3698 case SSE1: 3699 Builder.defineMacro("__SSE__"); 3700 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3701 case NoSSE: 3702 break; 3703 } 3704 3705 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3706 switch (SSELevel) { 3707 case AVX512F: 3708 case AVX2: 3709 case AVX: 3710 case SSE42: 3711 case SSE41: 3712 case SSSE3: 3713 case SSE3: 3714 case SSE2: 3715 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3716 break; 3717 case SSE1: 3718 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3719 break; 3720 default: 3721 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3722 } 3723 } 3724 3725 // Each case falls through to the previous one here. 3726 switch (MMX3DNowLevel) { 3727 case AMD3DNowAthlon: 3728 Builder.defineMacro("__3dNOW_A__"); 3729 case AMD3DNow: 3730 Builder.defineMacro("__3dNOW__"); 3731 case MMX: 3732 Builder.defineMacro("__MMX__"); 3733 case NoMMX3DNow: 3734 break; 3735 } 3736 3737 if (CPU >= CK_i486) { 3738 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3739 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3740 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3741 } 3742 if (CPU >= CK_i586) 3743 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3744 } 3745 3746 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3747 return llvm::StringSwitch<bool>(Feature) 3748 .Case("aes", HasAES) 3749 .Case("avx", SSELevel >= AVX) 3750 .Case("avx2", SSELevel >= AVX2) 3751 .Case("avx512f", SSELevel >= AVX512F) 3752 .Case("avx512cd", HasAVX512CD) 3753 .Case("avx512er", HasAVX512ER) 3754 .Case("avx512pf", HasAVX512PF) 3755 .Case("avx512dq", HasAVX512DQ) 3756 .Case("avx512bw", HasAVX512BW) 3757 .Case("avx512vl", HasAVX512VL) 3758 .Case("avx512vbmi", HasAVX512VBMI) 3759 .Case("avx512ifma", HasAVX512IFMA) 3760 .Case("bmi", HasBMI) 3761 .Case("bmi2", HasBMI2) 3762 .Case("clflushopt", HasCLFLUSHOPT) 3763 .Case("clwb", HasCLWB) 3764 .Case("cx16", HasCX16) 3765 .Case("f16c", HasF16C) 3766 .Case("fma", HasFMA) 3767 .Case("fma4", XOPLevel >= FMA4) 3768 .Case("fsgsbase", HasFSGSBASE) 3769 .Case("fxsr", HasFXSR) 3770 .Case("lzcnt", HasLZCNT) 3771 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3772 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3773 .Case("mmx", MMX3DNowLevel >= MMX) 3774 .Case("movbe", HasMOVBE) 3775 .Case("mpx", HasMPX) 3776 .Case("pclmul", HasPCLMUL) 3777 .Case("pcommit", HasPCOMMIT) 3778 .Case("pku", HasPKU) 3779 .Case("popcnt", HasPOPCNT) 3780 .Case("prefetchwt1", HasPREFETCHWT1) 3781 .Case("prfchw", HasPRFCHW) 3782 .Case("rdrnd", HasRDRND) 3783 .Case("rdseed", HasRDSEED) 3784 .Case("rtm", HasRTM) 3785 .Case("sgx", HasSGX) 3786 .Case("sha", HasSHA) 3787 .Case("sse", SSELevel >= SSE1) 3788 .Case("sse2", SSELevel >= SSE2) 3789 .Case("sse3", SSELevel >= SSE3) 3790 .Case("ssse3", SSELevel >= SSSE3) 3791 .Case("sse4.1", SSELevel >= SSE41) 3792 .Case("sse4.2", SSELevel >= SSE42) 3793 .Case("sse4a", XOPLevel >= SSE4A) 3794 .Case("tbm", HasTBM) 3795 .Case("umip", HasUMIP) 3796 .Case("x86", true) 3797 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3798 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3799 .Case("xop", XOPLevel >= XOP) 3800 .Case("xsave", HasXSAVE) 3801 .Case("xsavec", HasXSAVEC) 3802 .Case("xsaves", HasXSAVES) 3803 .Case("xsaveopt", HasXSAVEOPT) 3804 .Default(false); 3805 } 3806 3807 // We can't use a generic validation scheme for the features accepted here 3808 // versus subtarget features accepted in the target attribute because the 3809 // bitfield structure that's initialized in the runtime only supports the 3810 // below currently rather than the full range of subtarget features. (See 3811 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3812 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3813 return llvm::StringSwitch<bool>(FeatureStr) 3814 .Case("cmov", true) 3815 .Case("mmx", true) 3816 .Case("popcnt", true) 3817 .Case("sse", true) 3818 .Case("sse2", true) 3819 .Case("sse3", true) 3820 .Case("ssse3", true) 3821 .Case("sse4.1", true) 3822 .Case("sse4.2", true) 3823 .Case("avx", true) 3824 .Case("avx2", true) 3825 .Case("sse4a", true) 3826 .Case("fma4", true) 3827 .Case("xop", true) 3828 .Case("fma", true) 3829 .Case("avx512f", true) 3830 .Case("bmi", true) 3831 .Case("bmi2", true) 3832 .Case("aes", true) 3833 .Case("pclmul", true) 3834 .Case("avx512vl", true) 3835 .Case("avx512bw", true) 3836 .Case("avx512dq", true) 3837 .Case("avx512cd", true) 3838 .Case("avx512er", true) 3839 .Case("avx512pf", true) 3840 .Case("avx512vbmi", true) 3841 .Case("avx512ifma", true) 3842 .Default(false); 3843 } 3844 3845 bool 3846 X86TargetInfo::validateAsmConstraint(const char *&Name, 3847 TargetInfo::ConstraintInfo &Info) const { 3848 switch (*Name) { 3849 default: return false; 3850 // Constant constraints. 3851 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3852 // instructions. 3853 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3854 // x86_64 instructions. 3855 case 's': 3856 Info.setRequiresImmediate(); 3857 return true; 3858 case 'I': 3859 Info.setRequiresImmediate(0, 31); 3860 return true; 3861 case 'J': 3862 Info.setRequiresImmediate(0, 63); 3863 return true; 3864 case 'K': 3865 Info.setRequiresImmediate(-128, 127); 3866 return true; 3867 case 'L': 3868 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3869 return true; 3870 case 'M': 3871 Info.setRequiresImmediate(0, 3); 3872 return true; 3873 case 'N': 3874 Info.setRequiresImmediate(0, 255); 3875 return true; 3876 case 'O': 3877 Info.setRequiresImmediate(0, 127); 3878 return true; 3879 // Register constraints. 3880 case 'Y': // 'Y' is the first character for several 2-character constraints. 3881 // Shift the pointer to the second character of the constraint. 3882 Name++; 3883 switch (*Name) { 3884 default: 3885 return false; 3886 case '0': // First SSE register. 3887 case 't': // Any SSE register, when SSE2 is enabled. 3888 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3889 case 'm': // Any MMX register, when inter-unit moves enabled. 3890 Info.setAllowsRegister(); 3891 return true; 3892 } 3893 case 'f': // Any x87 floating point stack register. 3894 // Constraint 'f' cannot be used for output operands. 3895 if (Info.ConstraintStr[0] == '=') 3896 return false; 3897 Info.setAllowsRegister(); 3898 return true; 3899 case 'a': // eax. 3900 case 'b': // ebx. 3901 case 'c': // ecx. 3902 case 'd': // edx. 3903 case 'S': // esi. 3904 case 'D': // edi. 3905 case 'A': // edx:eax. 3906 case 't': // Top of floating point stack. 3907 case 'u': // Second from top of floating point stack. 3908 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3909 case 'y': // Any MMX register. 3910 case 'x': // Any SSE register. 3911 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3912 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3913 case 'l': // "Index" registers: any general register that can be used as an 3914 // index in a base+index memory access. 3915 Info.setAllowsRegister(); 3916 return true; 3917 // Floating point constant constraints. 3918 case 'C': // SSE floating point constant. 3919 case 'G': // x87 floating point constant. 3920 return true; 3921 } 3922 } 3923 3924 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3925 unsigned Size) const { 3926 // Strip off constraint modifiers. 3927 while (Constraint[0] == '=' || 3928 Constraint[0] == '+' || 3929 Constraint[0] == '&') 3930 Constraint = Constraint.substr(1); 3931 3932 return validateOperandSize(Constraint, Size); 3933 } 3934 3935 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3936 unsigned Size) const { 3937 return validateOperandSize(Constraint, Size); 3938 } 3939 3940 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3941 unsigned Size) const { 3942 switch (Constraint[0]) { 3943 default: break; 3944 case 'y': 3945 return Size <= 64; 3946 case 'f': 3947 case 't': 3948 case 'u': 3949 return Size <= 128; 3950 case 'x': 3951 if (SSELevel >= AVX512F) 3952 // 512-bit zmm registers can be used if target supports AVX512F. 3953 return Size <= 512U; 3954 else if (SSELevel >= AVX) 3955 // 256-bit ymm registers can be used if target supports AVX. 3956 return Size <= 256U; 3957 return Size <= 128U; 3958 case 'Y': 3959 // 'Y' is the first character for several 2-character constraints. 3960 switch (Constraint[1]) { 3961 default: break; 3962 case 'm': 3963 // 'Ym' is synonymous with 'y'. 3964 return Size <= 64; 3965 case 'i': 3966 case 't': 3967 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3968 if (SSELevel >= AVX512F) 3969 return Size <= 512U; 3970 else if (SSELevel >= AVX) 3971 return Size <= 256U; 3972 return SSELevel >= SSE2 && Size <= 128U; 3973 } 3974 3975 } 3976 3977 return true; 3978 } 3979 3980 std::string 3981 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3982 switch (*Constraint) { 3983 case 'a': return std::string("{ax}"); 3984 case 'b': return std::string("{bx}"); 3985 case 'c': return std::string("{cx}"); 3986 case 'd': return std::string("{dx}"); 3987 case 'S': return std::string("{si}"); 3988 case 'D': return std::string("{di}"); 3989 case 'p': // address 3990 return std::string("im"); 3991 case 't': // top of floating point stack. 3992 return std::string("{st}"); 3993 case 'u': // second from top of floating point stack. 3994 return std::string("{st(1)}"); // second from top of floating point stack. 3995 default: 3996 return std::string(1, *Constraint); 3997 } 3998 } 3999 4000 // X86-32 generic target 4001 class X86_32TargetInfo : public X86TargetInfo { 4002 public: 4003 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4004 : X86TargetInfo(Triple, Opts) { 4005 DoubleAlign = LongLongAlign = 32; 4006 LongDoubleWidth = 96; 4007 LongDoubleAlign = 32; 4008 SuitableAlign = 128; 4009 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4010 SizeType = UnsignedInt; 4011 PtrDiffType = SignedInt; 4012 IntPtrType = SignedInt; 4013 RegParmMax = 3; 4014 4015 // Use fpret for all types. 4016 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4017 (1 << TargetInfo::Double) | 4018 (1 << TargetInfo::LongDouble)); 4019 4020 // x86-32 has atomics up to 8 bytes 4021 // FIXME: Check that we actually have cmpxchg8b before setting 4022 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4023 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4024 } 4025 BuiltinVaListKind getBuiltinVaListKind() const override { 4026 return TargetInfo::CharPtrBuiltinVaList; 4027 } 4028 4029 int getEHDataRegisterNumber(unsigned RegNo) const override { 4030 if (RegNo == 0) return 0; 4031 if (RegNo == 1) return 2; 4032 return -1; 4033 } 4034 bool validateOperandSize(StringRef Constraint, 4035 unsigned Size) const override { 4036 switch (Constraint[0]) { 4037 default: break; 4038 case 'R': 4039 case 'q': 4040 case 'Q': 4041 case 'a': 4042 case 'b': 4043 case 'c': 4044 case 'd': 4045 case 'S': 4046 case 'D': 4047 return Size <= 32; 4048 case 'A': 4049 return Size <= 64; 4050 } 4051 4052 return X86TargetInfo::validateOperandSize(Constraint, Size); 4053 } 4054 }; 4055 4056 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4057 public: 4058 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4059 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4060 4061 unsigned getFloatEvalMethod() const override { 4062 unsigned Major, Minor, Micro; 4063 getTriple().getOSVersion(Major, Minor, Micro); 4064 // New NetBSD uses the default rounding mode. 4065 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4066 return X86_32TargetInfo::getFloatEvalMethod(); 4067 // NetBSD before 6.99.26 defaults to "double" rounding. 4068 return 1; 4069 } 4070 }; 4071 4072 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4073 public: 4074 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4075 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4076 SizeType = UnsignedLong; 4077 IntPtrType = SignedLong; 4078 PtrDiffType = SignedLong; 4079 } 4080 }; 4081 4082 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4083 public: 4084 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4085 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4086 SizeType = UnsignedLong; 4087 IntPtrType = SignedLong; 4088 PtrDiffType = SignedLong; 4089 } 4090 }; 4091 4092 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4093 public: 4094 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4095 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4096 LongDoubleWidth = 128; 4097 LongDoubleAlign = 128; 4098 SuitableAlign = 128; 4099 MaxVectorAlign = 256; 4100 // The watchOS simulator uses the builtin bool type for Objective-C. 4101 llvm::Triple T = llvm::Triple(Triple); 4102 if (T.isWatchOS()) 4103 UseSignedCharForObjCBool = false; 4104 SizeType = UnsignedLong; 4105 IntPtrType = SignedLong; 4106 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4107 HasAlignMac68kSupport = true; 4108 } 4109 4110 bool handleTargetFeatures(std::vector<std::string> &Features, 4111 DiagnosticsEngine &Diags) override { 4112 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4113 Diags)) 4114 return false; 4115 // We now know the features we have: we can decide how to align vectors. 4116 MaxVectorAlign = 4117 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4118 return true; 4119 } 4120 }; 4121 4122 // x86-32 Windows target 4123 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4124 public: 4125 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4126 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4127 WCharType = UnsignedShort; 4128 DoubleAlign = LongLongAlign = 64; 4129 bool IsWinCOFF = 4130 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4131 resetDataLayout(IsWinCOFF 4132 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4133 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4134 } 4135 void getTargetDefines(const LangOptions &Opts, 4136 MacroBuilder &Builder) const override { 4137 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4138 } 4139 }; 4140 4141 // x86-32 Windows Visual Studio target 4142 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4143 public: 4144 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4145 const TargetOptions &Opts) 4146 : WindowsX86_32TargetInfo(Triple, Opts) { 4147 LongDoubleWidth = LongDoubleAlign = 64; 4148 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4149 } 4150 void getTargetDefines(const LangOptions &Opts, 4151 MacroBuilder &Builder) const override { 4152 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4153 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4154 // The value of the following reflects processor type. 4155 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4156 // We lost the original triple, so we use the default. 4157 Builder.defineMacro("_M_IX86", "600"); 4158 } 4159 }; 4160 4161 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4162 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4163 // supports __declspec natively under -fms-extensions, but we define a no-op 4164 // __declspec macro anyway for pre-processor compatibility. 4165 if (Opts.MicrosoftExt) 4166 Builder.defineMacro("__declspec", "__declspec"); 4167 else 4168 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4169 4170 if (!Opts.MicrosoftExt) { 4171 // Provide macros for all the calling convention keywords. Provide both 4172 // single and double underscore prefixed variants. These are available on 4173 // x64 as well as x86, even though they have no effect. 4174 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4175 for (const char *CC : CCs) { 4176 std::string GCCSpelling = "__attribute__((__"; 4177 GCCSpelling += CC; 4178 GCCSpelling += "__))"; 4179 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4180 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4181 } 4182 } 4183 } 4184 4185 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4186 Builder.defineMacro("__MSVCRT__"); 4187 Builder.defineMacro("__MINGW32__"); 4188 addCygMingDefines(Opts, Builder); 4189 } 4190 4191 // x86-32 MinGW target 4192 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4193 public: 4194 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4195 : WindowsX86_32TargetInfo(Triple, Opts) {} 4196 void getTargetDefines(const LangOptions &Opts, 4197 MacroBuilder &Builder) const override { 4198 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4199 DefineStd(Builder, "WIN32", Opts); 4200 DefineStd(Builder, "WINNT", Opts); 4201 Builder.defineMacro("_X86_"); 4202 addMinGWDefines(Opts, Builder); 4203 } 4204 }; 4205 4206 // x86-32 Cygwin target 4207 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4208 public: 4209 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4210 : X86_32TargetInfo(Triple, Opts) { 4211 WCharType = UnsignedShort; 4212 DoubleAlign = LongLongAlign = 64; 4213 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4214 } 4215 void getTargetDefines(const LangOptions &Opts, 4216 MacroBuilder &Builder) const override { 4217 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4218 Builder.defineMacro("_X86_"); 4219 Builder.defineMacro("__CYGWIN__"); 4220 Builder.defineMacro("__CYGWIN32__"); 4221 addCygMingDefines(Opts, Builder); 4222 DefineStd(Builder, "unix", Opts); 4223 if (Opts.CPlusPlus) 4224 Builder.defineMacro("_GNU_SOURCE"); 4225 } 4226 }; 4227 4228 // x86-32 Haiku target 4229 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4230 public: 4231 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4232 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4233 } 4234 void getTargetDefines(const LangOptions &Opts, 4235 MacroBuilder &Builder) const override { 4236 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4237 Builder.defineMacro("__INTEL__"); 4238 } 4239 }; 4240 4241 // X86-32 MCU target 4242 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4243 public: 4244 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4245 : X86_32TargetInfo(Triple, Opts) { 4246 LongDoubleWidth = 64; 4247 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4248 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4249 WIntType = UnsignedInt; 4250 } 4251 4252 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4253 // On MCU we support only C calling convention. 4254 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4255 } 4256 4257 void getTargetDefines(const LangOptions &Opts, 4258 MacroBuilder &Builder) const override { 4259 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4260 Builder.defineMacro("__iamcu"); 4261 Builder.defineMacro("__iamcu__"); 4262 } 4263 4264 bool allowsLargerPreferedTypeAlignment() const override { 4265 return false; 4266 } 4267 }; 4268 4269 // RTEMS Target 4270 template<typename Target> 4271 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4272 protected: 4273 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4274 MacroBuilder &Builder) const override { 4275 // RTEMS defines; list based off of gcc output 4276 4277 Builder.defineMacro("__rtems__"); 4278 Builder.defineMacro("__ELF__"); 4279 } 4280 4281 public: 4282 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4283 : OSTargetInfo<Target>(Triple, Opts) { 4284 switch (Triple.getArch()) { 4285 default: 4286 case llvm::Triple::x86: 4287 // this->MCountName = ".mcount"; 4288 break; 4289 case llvm::Triple::mips: 4290 case llvm::Triple::mipsel: 4291 case llvm::Triple::ppc: 4292 case llvm::Triple::ppc64: 4293 case llvm::Triple::ppc64le: 4294 // this->MCountName = "_mcount"; 4295 break; 4296 case llvm::Triple::arm: 4297 // this->MCountName = "__mcount"; 4298 break; 4299 } 4300 } 4301 }; 4302 4303 // x86-32 RTEMS target 4304 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4305 public: 4306 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4307 : X86_32TargetInfo(Triple, Opts) { 4308 SizeType = UnsignedLong; 4309 IntPtrType = SignedLong; 4310 PtrDiffType = SignedLong; 4311 } 4312 void getTargetDefines(const LangOptions &Opts, 4313 MacroBuilder &Builder) const override { 4314 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4315 Builder.defineMacro("__INTEL__"); 4316 Builder.defineMacro("__rtems__"); 4317 } 4318 }; 4319 4320 // x86-64 generic target 4321 class X86_64TargetInfo : public X86TargetInfo { 4322 public: 4323 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4324 : X86TargetInfo(Triple, Opts) { 4325 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4326 bool IsWinCOFF = 4327 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4328 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4329 LongDoubleWidth = 128; 4330 LongDoubleAlign = 128; 4331 LargeArrayMinWidth = 128; 4332 LargeArrayAlign = 128; 4333 SuitableAlign = 128; 4334 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4335 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4336 IntPtrType = IsX32 ? SignedInt : SignedLong; 4337 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4338 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4339 RegParmMax = 6; 4340 4341 // Pointers are 32-bit in x32. 4342 resetDataLayout(IsX32 4343 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4344 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4345 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4346 4347 // Use fpret only for long double. 4348 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4349 4350 // Use fp2ret for _Complex long double. 4351 ComplexLongDoubleUsesFP2Ret = true; 4352 4353 // Make __builtin_ms_va_list available. 4354 HasBuiltinMSVaList = true; 4355 4356 // x86-64 has atomics up to 16 bytes. 4357 MaxAtomicPromoteWidth = 128; 4358 MaxAtomicInlineWidth = 128; 4359 } 4360 BuiltinVaListKind getBuiltinVaListKind() const override { 4361 return TargetInfo::X86_64ABIBuiltinVaList; 4362 } 4363 4364 int getEHDataRegisterNumber(unsigned RegNo) const override { 4365 if (RegNo == 0) return 0; 4366 if (RegNo == 1) return 1; 4367 return -1; 4368 } 4369 4370 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4371 switch (CC) { 4372 case CC_C: 4373 case CC_Swift: 4374 case CC_X86VectorCall: 4375 case CC_IntelOclBicc: 4376 case CC_X86_64Win64: 4377 case CC_PreserveMost: 4378 case CC_PreserveAll: 4379 return CCCR_OK; 4380 default: 4381 return CCCR_Warning; 4382 } 4383 } 4384 4385 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4386 return CC_C; 4387 } 4388 4389 // for x32 we need it here explicitly 4390 bool hasInt128Type() const override { return true; } 4391 unsigned getUnwindWordWidth() const override { return 64; } 4392 unsigned getRegisterWidth() const override { return 64; } 4393 4394 bool validateGlobalRegisterVariable(StringRef RegName, 4395 unsigned RegSize, 4396 bool &HasSizeMismatch) const override { 4397 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4398 // handle. 4399 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4400 // Check that the register size is 64-bit. 4401 HasSizeMismatch = RegSize != 64; 4402 return true; 4403 } 4404 4405 // Check if the register is a 32-bit register the backend can handle. 4406 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4407 HasSizeMismatch); 4408 } 4409 }; 4410 4411 // x86-64 Windows target 4412 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4413 public: 4414 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4415 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4416 WCharType = UnsignedShort; 4417 LongWidth = LongAlign = 32; 4418 DoubleAlign = LongLongAlign = 64; 4419 IntMaxType = SignedLongLong; 4420 Int64Type = SignedLongLong; 4421 SizeType = UnsignedLongLong; 4422 PtrDiffType = SignedLongLong; 4423 IntPtrType = SignedLongLong; 4424 } 4425 4426 void getTargetDefines(const LangOptions &Opts, 4427 MacroBuilder &Builder) const override { 4428 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4429 Builder.defineMacro("_WIN64"); 4430 } 4431 4432 BuiltinVaListKind getBuiltinVaListKind() const override { 4433 return TargetInfo::CharPtrBuiltinVaList; 4434 } 4435 4436 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4437 switch (CC) { 4438 case CC_X86StdCall: 4439 case CC_X86ThisCall: 4440 case CC_X86FastCall: 4441 return CCCR_Ignore; 4442 case CC_C: 4443 case CC_X86VectorCall: 4444 case CC_IntelOclBicc: 4445 case CC_X86_64SysV: 4446 return CCCR_OK; 4447 default: 4448 return CCCR_Warning; 4449 } 4450 } 4451 }; 4452 4453 // x86-64 Windows Visual Studio target 4454 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4455 public: 4456 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4457 const TargetOptions &Opts) 4458 : WindowsX86_64TargetInfo(Triple, Opts) { 4459 LongDoubleWidth = LongDoubleAlign = 64; 4460 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4461 } 4462 void getTargetDefines(const LangOptions &Opts, 4463 MacroBuilder &Builder) const override { 4464 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4465 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4466 Builder.defineMacro("_M_X64", "100"); 4467 Builder.defineMacro("_M_AMD64", "100"); 4468 } 4469 }; 4470 4471 // x86-64 MinGW target 4472 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4473 public: 4474 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4475 : WindowsX86_64TargetInfo(Triple, Opts) { 4476 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4477 // with x86 FP ops. Weird. 4478 LongDoubleWidth = LongDoubleAlign = 128; 4479 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4480 } 4481 4482 void getTargetDefines(const LangOptions &Opts, 4483 MacroBuilder &Builder) const override { 4484 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4485 DefineStd(Builder, "WIN64", Opts); 4486 Builder.defineMacro("__MINGW64__"); 4487 addMinGWDefines(Opts, Builder); 4488 4489 // GCC defines this macro when it is using __gxx_personality_seh0. 4490 if (!Opts.SjLjExceptions) 4491 Builder.defineMacro("__SEH__"); 4492 } 4493 }; 4494 4495 // x86-64 Cygwin target 4496 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4497 public: 4498 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4499 : X86_64TargetInfo(Triple, Opts) { 4500 TLSSupported = false; 4501 WCharType = UnsignedShort; 4502 } 4503 void getTargetDefines(const LangOptions &Opts, 4504 MacroBuilder &Builder) const override { 4505 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4506 Builder.defineMacro("__x86_64__"); 4507 Builder.defineMacro("__CYGWIN__"); 4508 Builder.defineMacro("__CYGWIN64__"); 4509 addCygMingDefines(Opts, Builder); 4510 DefineStd(Builder, "unix", Opts); 4511 if (Opts.CPlusPlus) 4512 Builder.defineMacro("_GNU_SOURCE"); 4513 4514 // GCC defines this macro when it is using __gxx_personality_seh0. 4515 if (!Opts.SjLjExceptions) 4516 Builder.defineMacro("__SEH__"); 4517 } 4518 }; 4519 4520 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4521 public: 4522 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4523 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4524 Int64Type = SignedLongLong; 4525 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4526 llvm::Triple T = llvm::Triple(Triple); 4527 if (T.isiOS()) 4528 UseSignedCharForObjCBool = false; 4529 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4530 } 4531 4532 bool handleTargetFeatures(std::vector<std::string> &Features, 4533 DiagnosticsEngine &Diags) override { 4534 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4535 Diags)) 4536 return false; 4537 // We now know the features we have: we can decide how to align vectors. 4538 MaxVectorAlign = 4539 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4540 return true; 4541 } 4542 }; 4543 4544 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4545 public: 4546 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4547 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4548 IntMaxType = SignedLongLong; 4549 Int64Type = SignedLongLong; 4550 } 4551 }; 4552 4553 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4554 public: 4555 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4556 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4557 IntMaxType = SignedLongLong; 4558 Int64Type = SignedLongLong; 4559 } 4560 }; 4561 4562 class ARMTargetInfo : public TargetInfo { 4563 // Possible FPU choices. 4564 enum FPUMode { 4565 VFP2FPU = (1 << 0), 4566 VFP3FPU = (1 << 1), 4567 VFP4FPU = (1 << 2), 4568 NeonFPU = (1 << 3), 4569 FPARMV8 = (1 << 4) 4570 }; 4571 4572 // Possible HWDiv features. 4573 enum HWDivMode { 4574 HWDivThumb = (1 << 0), 4575 HWDivARM = (1 << 1) 4576 }; 4577 4578 static bool FPUModeIsVFP(FPUMode Mode) { 4579 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4580 } 4581 4582 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4583 static const char * const GCCRegNames[]; 4584 4585 std::string ABI, CPU; 4586 4587 StringRef CPUProfile; 4588 StringRef CPUAttr; 4589 4590 enum { 4591 FP_Default, 4592 FP_VFP, 4593 FP_Neon 4594 } FPMath; 4595 4596 unsigned ArchISA; 4597 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4598 unsigned ArchProfile; 4599 unsigned ArchVersion; 4600 4601 unsigned FPU : 5; 4602 4603 unsigned IsAAPCS : 1; 4604 unsigned HWDiv : 2; 4605 4606 // Initialized via features. 4607 unsigned SoftFloat : 1; 4608 unsigned SoftFloatABI : 1; 4609 4610 unsigned CRC : 1; 4611 unsigned Crypto : 1; 4612 unsigned DSP : 1; 4613 unsigned Unaligned : 1; 4614 4615 enum { 4616 LDREX_B = (1 << 0), /// byte (8-bit) 4617 LDREX_H = (1 << 1), /// half (16-bit) 4618 LDREX_W = (1 << 2), /// word (32-bit) 4619 LDREX_D = (1 << 3), /// double (64-bit) 4620 }; 4621 4622 uint32_t LDREX; 4623 4624 // ACLE 6.5.1 Hardware floating point 4625 enum { 4626 HW_FP_HP = (1 << 1), /// half (16-bit) 4627 HW_FP_SP = (1 << 2), /// single (32-bit) 4628 HW_FP_DP = (1 << 3), /// double (64-bit) 4629 }; 4630 uint32_t HW_FP; 4631 4632 static const Builtin::Info BuiltinInfo[]; 4633 4634 void setABIAAPCS() { 4635 IsAAPCS = true; 4636 4637 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4638 const llvm::Triple &T = getTriple(); 4639 4640 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4641 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4642 T.getOS() == llvm::Triple::Bitrig) 4643 SizeType = UnsignedLong; 4644 else 4645 SizeType = UnsignedInt; 4646 4647 switch (T.getOS()) { 4648 case llvm::Triple::NetBSD: 4649 WCharType = SignedInt; 4650 break; 4651 case llvm::Triple::Win32: 4652 WCharType = UnsignedShort; 4653 break; 4654 case llvm::Triple::Linux: 4655 default: 4656 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4657 WCharType = UnsignedInt; 4658 break; 4659 } 4660 4661 UseBitFieldTypeAlignment = true; 4662 4663 ZeroLengthBitfieldBoundary = 0; 4664 4665 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4666 // so set preferred for small types to 32. 4667 if (T.isOSBinFormatMachO()) { 4668 resetDataLayout(BigEndian 4669 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4670 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4671 } else if (T.isOSWindows()) { 4672 assert(!BigEndian && "Windows on ARM does not support big endian"); 4673 resetDataLayout("e" 4674 "-m:w" 4675 "-p:32:32" 4676 "-i64:64" 4677 "-v128:64:128" 4678 "-a:0:32" 4679 "-n32" 4680 "-S64"); 4681 } else if (T.isOSNaCl()) { 4682 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4683 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4684 } else { 4685 resetDataLayout(BigEndian 4686 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4687 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4688 } 4689 4690 // FIXME: Enumerated types are variable width in straight AAPCS. 4691 } 4692 4693 void setABIAPCS(bool IsAAPCS16) { 4694 const llvm::Triple &T = getTriple(); 4695 4696 IsAAPCS = false; 4697 4698 if (IsAAPCS16) 4699 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4700 else 4701 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4702 4703 // size_t is unsigned int on FreeBSD. 4704 if (T.getOS() == llvm::Triple::FreeBSD) 4705 SizeType = UnsignedInt; 4706 else 4707 SizeType = UnsignedLong; 4708 4709 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4710 WCharType = SignedInt; 4711 4712 // Do not respect the alignment of bit-field types when laying out 4713 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4714 UseBitFieldTypeAlignment = false; 4715 4716 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4717 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4718 /// gcc. 4719 ZeroLengthBitfieldBoundary = 32; 4720 4721 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4722 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4723 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4724 } else if (T.isOSBinFormatMachO()) 4725 resetDataLayout( 4726 BigEndian 4727 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4728 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4729 else 4730 resetDataLayout( 4731 BigEndian 4732 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4733 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4734 4735 // FIXME: Override "preferred align" for double and long long. 4736 } 4737 4738 void setArchInfo() { 4739 StringRef ArchName = getTriple().getArchName(); 4740 4741 ArchISA = llvm::ARM::parseArchISA(ArchName); 4742 CPU = llvm::ARM::getDefaultCPU(ArchName); 4743 unsigned AK = llvm::ARM::parseArch(ArchName); 4744 if (AK != llvm::ARM::AK_INVALID) 4745 ArchKind = AK; 4746 setArchInfo(ArchKind); 4747 } 4748 4749 void setArchInfo(unsigned Kind) { 4750 StringRef SubArch; 4751 4752 // cache TargetParser info 4753 ArchKind = Kind; 4754 SubArch = llvm::ARM::getSubArch(ArchKind); 4755 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4756 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4757 4758 // cache CPU related strings 4759 CPUAttr = getCPUAttr(); 4760 CPUProfile = getCPUProfile(); 4761 } 4762 4763 void setAtomic() { 4764 // when triple does not specify a sub arch, 4765 // then we are not using inline atomics 4766 bool ShouldUseInlineAtomic = 4767 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4768 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4769 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4770 if (ArchProfile == llvm::ARM::PK_M) { 4771 MaxAtomicPromoteWidth = 32; 4772 if (ShouldUseInlineAtomic) 4773 MaxAtomicInlineWidth = 32; 4774 } 4775 else { 4776 MaxAtomicPromoteWidth = 64; 4777 if (ShouldUseInlineAtomic) 4778 MaxAtomicInlineWidth = 64; 4779 } 4780 } 4781 4782 bool isThumb() const { 4783 return (ArchISA == llvm::ARM::IK_THUMB); 4784 } 4785 4786 bool supportsThumb() const { 4787 return CPUAttr.count('T') || ArchVersion >= 6; 4788 } 4789 4790 bool supportsThumb2() const { 4791 return CPUAttr.equals("6T2") || 4792 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4793 } 4794 4795 StringRef getCPUAttr() const { 4796 // For most sub-arches, the build attribute CPU name is enough. 4797 // For Cortex variants, it's slightly different. 4798 switch(ArchKind) { 4799 default: 4800 return llvm::ARM::getCPUAttr(ArchKind); 4801 case llvm::ARM::AK_ARMV6M: 4802 return "6M"; 4803 case llvm::ARM::AK_ARMV7S: 4804 return "7S"; 4805 case llvm::ARM::AK_ARMV7A: 4806 return "7A"; 4807 case llvm::ARM::AK_ARMV7R: 4808 return "7R"; 4809 case llvm::ARM::AK_ARMV7M: 4810 return "7M"; 4811 case llvm::ARM::AK_ARMV7EM: 4812 return "7EM"; 4813 case llvm::ARM::AK_ARMV8A: 4814 return "8A"; 4815 case llvm::ARM::AK_ARMV8_1A: 4816 return "8_1A"; 4817 case llvm::ARM::AK_ARMV8_2A: 4818 return "8_2A"; 4819 case llvm::ARM::AK_ARMV8MBaseline: 4820 return "8M_BASE"; 4821 case llvm::ARM::AK_ARMV8MMainline: 4822 return "8M_MAIN"; 4823 } 4824 } 4825 4826 StringRef getCPUProfile() const { 4827 switch(ArchProfile) { 4828 case llvm::ARM::PK_A: 4829 return "A"; 4830 case llvm::ARM::PK_R: 4831 return "R"; 4832 case llvm::ARM::PK_M: 4833 return "M"; 4834 default: 4835 return ""; 4836 } 4837 } 4838 4839 public: 4840 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4841 bool IsBigEndian) 4842 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4843 HW_FP(0) { 4844 BigEndian = IsBigEndian; 4845 4846 switch (getTriple().getOS()) { 4847 case llvm::Triple::NetBSD: 4848 PtrDiffType = SignedLong; 4849 break; 4850 default: 4851 PtrDiffType = SignedInt; 4852 break; 4853 } 4854 4855 // Cache arch related info. 4856 setArchInfo(); 4857 4858 // {} in inline assembly are neon specifiers, not assembly variant 4859 // specifiers. 4860 NoAsmVariants = true; 4861 4862 // FIXME: This duplicates code from the driver that sets the -target-abi 4863 // option - this code is used if -target-abi isn't passed and should 4864 // be unified in some way. 4865 if (Triple.isOSBinFormatMachO()) { 4866 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4867 // the frontend matches that. 4868 if (Triple.getEnvironment() == llvm::Triple::EABI || 4869 Triple.getOS() == llvm::Triple::UnknownOS || 4870 StringRef(CPU).startswith("cortex-m")) { 4871 setABI("aapcs"); 4872 } else if (Triple.isWatchABI()) { 4873 setABI("aapcs16"); 4874 } else { 4875 setABI("apcs-gnu"); 4876 } 4877 } else if (Triple.isOSWindows()) { 4878 // FIXME: this is invalid for WindowsCE 4879 setABI("aapcs"); 4880 } else { 4881 // Select the default based on the platform. 4882 switch (Triple.getEnvironment()) { 4883 case llvm::Triple::Android: 4884 case llvm::Triple::GNUEABI: 4885 case llvm::Triple::GNUEABIHF: 4886 case llvm::Triple::MuslEABI: 4887 case llvm::Triple::MuslEABIHF: 4888 setABI("aapcs-linux"); 4889 break; 4890 case llvm::Triple::EABIHF: 4891 case llvm::Triple::EABI: 4892 setABI("aapcs"); 4893 break; 4894 case llvm::Triple::GNU: 4895 setABI("apcs-gnu"); 4896 break; 4897 default: 4898 if (Triple.getOS() == llvm::Triple::NetBSD) 4899 setABI("apcs-gnu"); 4900 else 4901 setABI("aapcs"); 4902 break; 4903 } 4904 } 4905 4906 // ARM targets default to using the ARM C++ ABI. 4907 TheCXXABI.set(TargetCXXABI::GenericARM); 4908 4909 // ARM has atomics up to 8 bytes 4910 setAtomic(); 4911 4912 // Do force alignment of members that follow zero length bitfields. If 4913 // the alignment of the zero-length bitfield is greater than the member 4914 // that follows it, `bar', `bar' will be aligned as the type of the 4915 // zero length bitfield. 4916 UseZeroLengthBitfieldAlignment = true; 4917 4918 if (Triple.getOS() == llvm::Triple::Linux || 4919 Triple.getOS() == llvm::Triple::UnknownOS) 4920 this->MCountName = 4921 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4922 } 4923 4924 StringRef getABI() const override { return ABI; } 4925 4926 bool setABI(const std::string &Name) override { 4927 ABI = Name; 4928 4929 // The defaults (above) are for AAPCS, check if we need to change them. 4930 // 4931 // FIXME: We need support for -meabi... we could just mangle it into the 4932 // name. 4933 if (Name == "apcs-gnu" || Name == "aapcs16") { 4934 setABIAPCS(Name == "aapcs16"); 4935 return true; 4936 } 4937 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4938 setABIAAPCS(); 4939 return true; 4940 } 4941 return false; 4942 } 4943 4944 // FIXME: This should be based on Arch attributes, not CPU names. 4945 bool 4946 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4947 StringRef CPU, 4948 const std::vector<std::string> &FeaturesVec) const override { 4949 4950 std::vector<const char*> TargetFeatures; 4951 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4952 4953 // get default FPU features 4954 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4955 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4956 4957 // get default Extension features 4958 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4959 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4960 4961 for (const char *Feature : TargetFeatures) 4962 if (Feature[0] == '+') 4963 Features[Feature+1] = true; 4964 4965 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4966 } 4967 4968 bool handleTargetFeatures(std::vector<std::string> &Features, 4969 DiagnosticsEngine &Diags) override { 4970 FPU = 0; 4971 CRC = 0; 4972 Crypto = 0; 4973 DSP = 0; 4974 Unaligned = 1; 4975 SoftFloat = SoftFloatABI = false; 4976 HWDiv = 0; 4977 4978 // This does not diagnose illegal cases like having both 4979 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4980 uint32_t HW_FP_remove = 0; 4981 for (const auto &Feature : Features) { 4982 if (Feature == "+soft-float") { 4983 SoftFloat = true; 4984 } else if (Feature == "+soft-float-abi") { 4985 SoftFloatABI = true; 4986 } else if (Feature == "+vfp2") { 4987 FPU |= VFP2FPU; 4988 HW_FP |= HW_FP_SP | HW_FP_DP; 4989 } else if (Feature == "+vfp3") { 4990 FPU |= VFP3FPU; 4991 HW_FP |= HW_FP_SP | HW_FP_DP; 4992 } else if (Feature == "+vfp4") { 4993 FPU |= VFP4FPU; 4994 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4995 } else if (Feature == "+fp-armv8") { 4996 FPU |= FPARMV8; 4997 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4998 } else if (Feature == "+neon") { 4999 FPU |= NeonFPU; 5000 HW_FP |= HW_FP_SP | HW_FP_DP; 5001 } else if (Feature == "+hwdiv") { 5002 HWDiv |= HWDivThumb; 5003 } else if (Feature == "+hwdiv-arm") { 5004 HWDiv |= HWDivARM; 5005 } else if (Feature == "+crc") { 5006 CRC = 1; 5007 } else if (Feature == "+crypto") { 5008 Crypto = 1; 5009 } else if (Feature == "+dsp") { 5010 DSP = 1; 5011 } else if (Feature == "+fp-only-sp") { 5012 HW_FP_remove |= HW_FP_DP; 5013 } else if (Feature == "+strict-align") { 5014 Unaligned = 0; 5015 } else if (Feature == "+fp16") { 5016 HW_FP |= HW_FP_HP; 5017 } 5018 } 5019 HW_FP &= ~HW_FP_remove; 5020 5021 switch (ArchVersion) { 5022 case 6: 5023 if (ArchProfile == llvm::ARM::PK_M) 5024 LDREX = 0; 5025 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5026 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5027 else 5028 LDREX = LDREX_W; 5029 break; 5030 case 7: 5031 if (ArchProfile == llvm::ARM::PK_M) 5032 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5033 else 5034 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5035 break; 5036 case 8: 5037 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5038 } 5039 5040 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5041 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5042 return false; 5043 } 5044 5045 if (FPMath == FP_Neon) 5046 Features.push_back("+neonfp"); 5047 else if (FPMath == FP_VFP) 5048 Features.push_back("-neonfp"); 5049 5050 // Remove front-end specific options which the backend handles differently. 5051 auto Feature = 5052 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5053 if (Feature != Features.end()) 5054 Features.erase(Feature); 5055 5056 return true; 5057 } 5058 5059 bool hasFeature(StringRef Feature) const override { 5060 return llvm::StringSwitch<bool>(Feature) 5061 .Case("arm", true) 5062 .Case("aarch32", true) 5063 .Case("softfloat", SoftFloat) 5064 .Case("thumb", isThumb()) 5065 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5066 .Case("hwdiv", HWDiv & HWDivThumb) 5067 .Case("hwdiv-arm", HWDiv & HWDivARM) 5068 .Default(false); 5069 } 5070 5071 bool setCPU(const std::string &Name) override { 5072 if (Name != "generic") 5073 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5074 5075 if (ArchKind == llvm::ARM::AK_INVALID) 5076 return false; 5077 setAtomic(); 5078 CPU = Name; 5079 return true; 5080 } 5081 5082 bool setFPMath(StringRef Name) override; 5083 5084 void getTargetDefines(const LangOptions &Opts, 5085 MacroBuilder &Builder) const override { 5086 // Target identification. 5087 Builder.defineMacro("__arm"); 5088 Builder.defineMacro("__arm__"); 5089 // For bare-metal none-eabi. 5090 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5091 getTriple().getEnvironment() == llvm::Triple::EABI) 5092 Builder.defineMacro("__ELF__"); 5093 5094 // Target properties. 5095 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5096 5097 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5098 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5099 if (getTriple().isWatchABI()) 5100 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5101 5102 if (!CPUAttr.empty()) 5103 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5104 5105 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5106 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5107 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5108 5109 if (ArchVersion >= 8) { 5110 // ACLE 6.5.7 Crypto Extension 5111 if (Crypto) 5112 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5113 // ACLE 6.5.8 CRC32 Extension 5114 if (CRC) 5115 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5116 // ACLE 6.5.10 Numeric Maximum and Minimum 5117 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5118 // ACLE 6.5.9 Directed Rounding 5119 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5120 } 5121 5122 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5123 // is not defined for the M-profile. 5124 // NOTE that the default profile is assumed to be 'A' 5125 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5126 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5127 5128 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5129 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5130 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5131 // v7 and v8 architectures excluding v8-M Baseline. 5132 if (supportsThumb2()) 5133 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5134 else if (supportsThumb()) 5135 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5136 5137 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5138 // instruction set such as ARM or Thumb. 5139 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5140 5141 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5142 5143 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5144 if (!CPUProfile.empty()) 5145 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5146 5147 // ACLE 6.4.3 Unaligned access supported in hardware 5148 if (Unaligned) 5149 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5150 5151 // ACLE 6.4.4 LDREX/STREX 5152 if (LDREX) 5153 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5154 5155 // ACLE 6.4.5 CLZ 5156 if (ArchVersion == 5 || 5157 (ArchVersion == 6 && CPUProfile != "M") || 5158 ArchVersion > 6) 5159 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5160 5161 // ACLE 6.5.1 Hardware Floating Point 5162 if (HW_FP) 5163 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5164 5165 // ACLE predefines. 5166 Builder.defineMacro("__ARM_ACLE", "200"); 5167 5168 // FP16 support (we currently only support IEEE format). 5169 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5170 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5171 5172 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5173 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5174 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5175 5176 // Subtarget options. 5177 5178 // FIXME: It's more complicated than this and we don't really support 5179 // interworking. 5180 // Windows on ARM does not "support" interworking 5181 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5182 Builder.defineMacro("__THUMB_INTERWORK__"); 5183 5184 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5185 // Embedded targets on Darwin follow AAPCS, but not EABI. 5186 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5187 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5188 Builder.defineMacro("__ARM_EABI__"); 5189 Builder.defineMacro("__ARM_PCS", "1"); 5190 } 5191 5192 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5193 ABI == "aapcs16") 5194 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5195 5196 if (SoftFloat) 5197 Builder.defineMacro("__SOFTFP__"); 5198 5199 if (CPU == "xscale") 5200 Builder.defineMacro("__XSCALE__"); 5201 5202 if (isThumb()) { 5203 Builder.defineMacro("__THUMBEL__"); 5204 Builder.defineMacro("__thumb__"); 5205 if (supportsThumb2()) 5206 Builder.defineMacro("__thumb2__"); 5207 } 5208 5209 // ACLE 6.4.9 32-bit SIMD instructions 5210 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5211 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5212 5213 // ACLE 6.4.10 Hardware Integer Divide 5214 if (((HWDiv & HWDivThumb) && isThumb()) || 5215 ((HWDiv & HWDivARM) && !isThumb())) { 5216 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5217 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5218 } 5219 5220 // Note, this is always on in gcc, even though it doesn't make sense. 5221 Builder.defineMacro("__APCS_32__"); 5222 5223 if (FPUModeIsVFP((FPUMode) FPU)) { 5224 Builder.defineMacro("__VFP_FP__"); 5225 if (FPU & VFP2FPU) 5226 Builder.defineMacro("__ARM_VFPV2__"); 5227 if (FPU & VFP3FPU) 5228 Builder.defineMacro("__ARM_VFPV3__"); 5229 if (FPU & VFP4FPU) 5230 Builder.defineMacro("__ARM_VFPV4__"); 5231 } 5232 5233 // This only gets set when Neon instructions are actually available, unlike 5234 // the VFP define, hence the soft float and arch check. This is subtly 5235 // different from gcc, we follow the intent which was that it should be set 5236 // when Neon instructions are actually available. 5237 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5238 Builder.defineMacro("__ARM_NEON", "1"); 5239 Builder.defineMacro("__ARM_NEON__"); 5240 // current AArch32 NEON implementations do not support double-precision 5241 // floating-point even when it is present in VFP. 5242 Builder.defineMacro("__ARM_NEON_FP", 5243 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5244 } 5245 5246 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5247 Opts.ShortWChar ? "2" : "4"); 5248 5249 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5250 Opts.ShortEnums ? "1" : "4"); 5251 5252 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5257 } 5258 5259 // ACLE 6.4.7 DSP instructions 5260 if (DSP) { 5261 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5262 } 5263 5264 // ACLE 6.4.8 Saturation instructions 5265 bool SAT = false; 5266 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5267 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5268 SAT = true; 5269 } 5270 5271 // ACLE 6.4.6 Q (saturation) flag 5272 if (DSP || SAT) 5273 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5274 5275 if (Opts.UnsafeFPMath) 5276 Builder.defineMacro("__ARM_FP_FAST", "1"); 5277 5278 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5279 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5280 } 5281 5282 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5283 return llvm::makeArrayRef(BuiltinInfo, 5284 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5285 } 5286 bool isCLZForZeroUndef() const override { return false; } 5287 BuiltinVaListKind getBuiltinVaListKind() const override { 5288 return IsAAPCS 5289 ? AAPCSABIBuiltinVaList 5290 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5291 : TargetInfo::VoidPtrBuiltinVaList); 5292 } 5293 ArrayRef<const char *> getGCCRegNames() const override; 5294 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5295 bool validateAsmConstraint(const char *&Name, 5296 TargetInfo::ConstraintInfo &Info) const override { 5297 switch (*Name) { 5298 default: break; 5299 case 'l': // r0-r7 5300 case 'h': // r8-r15 5301 case 't': // VFP Floating point register single precision 5302 case 'w': // VFP Floating point register double precision 5303 Info.setAllowsRegister(); 5304 return true; 5305 case 'I': 5306 case 'J': 5307 case 'K': 5308 case 'L': 5309 case 'M': 5310 // FIXME 5311 return true; 5312 case 'Q': // A memory address that is a single base register. 5313 Info.setAllowsMemory(); 5314 return true; 5315 case 'U': // a memory reference... 5316 switch (Name[1]) { 5317 case 'q': // ...ARMV4 ldrsb 5318 case 'v': // ...VFP load/store (reg+constant offset) 5319 case 'y': // ...iWMMXt load/store 5320 case 't': // address valid for load/store opaque types wider 5321 // than 128-bits 5322 case 'n': // valid address for Neon doubleword vector load/store 5323 case 'm': // valid address for Neon element and structure load/store 5324 case 's': // valid address for non-offset loads/stores of quad-word 5325 // values in four ARM registers 5326 Info.setAllowsMemory(); 5327 Name++; 5328 return true; 5329 } 5330 } 5331 return false; 5332 } 5333 std::string convertConstraint(const char *&Constraint) const override { 5334 std::string R; 5335 switch (*Constraint) { 5336 case 'U': // Two-character constraint; add "^" hint for later parsing. 5337 R = std::string("^") + std::string(Constraint, 2); 5338 Constraint++; 5339 break; 5340 case 'p': // 'p' should be translated to 'r' by default. 5341 R = std::string("r"); 5342 break; 5343 default: 5344 return std::string(1, *Constraint); 5345 } 5346 return R; 5347 } 5348 bool 5349 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5350 std::string &SuggestedModifier) const override { 5351 bool isOutput = (Constraint[0] == '='); 5352 bool isInOut = (Constraint[0] == '+'); 5353 5354 // Strip off constraint modifiers. 5355 while (Constraint[0] == '=' || 5356 Constraint[0] == '+' || 5357 Constraint[0] == '&') 5358 Constraint = Constraint.substr(1); 5359 5360 switch (Constraint[0]) { 5361 default: break; 5362 case 'r': { 5363 switch (Modifier) { 5364 default: 5365 return (isInOut || isOutput || Size <= 64); 5366 case 'q': 5367 // A register of size 32 cannot fit a vector type. 5368 return false; 5369 } 5370 } 5371 } 5372 5373 return true; 5374 } 5375 const char *getClobbers() const override { 5376 // FIXME: Is this really right? 5377 return ""; 5378 } 5379 5380 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5381 switch (CC) { 5382 case CC_AAPCS: 5383 case CC_AAPCS_VFP: 5384 case CC_Swift: 5385 return CCCR_OK; 5386 default: 5387 return CCCR_Warning; 5388 } 5389 } 5390 5391 int getEHDataRegisterNumber(unsigned RegNo) const override { 5392 if (RegNo == 0) return 0; 5393 if (RegNo == 1) return 1; 5394 return -1; 5395 } 5396 5397 bool hasSjLjLowering() const override { 5398 return true; 5399 } 5400 }; 5401 5402 bool ARMTargetInfo::setFPMath(StringRef Name) { 5403 if (Name == "neon") { 5404 FPMath = FP_Neon; 5405 return true; 5406 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5407 Name == "vfp4") { 5408 FPMath = FP_VFP; 5409 return true; 5410 } 5411 return false; 5412 } 5413 5414 const char * const ARMTargetInfo::GCCRegNames[] = { 5415 // Integer registers 5416 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5417 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5418 5419 // Float registers 5420 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5421 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5422 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5423 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5424 5425 // Double registers 5426 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5427 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5428 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5429 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5430 5431 // Quad registers 5432 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5433 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5434 }; 5435 5436 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5437 return llvm::makeArrayRef(GCCRegNames); 5438 } 5439 5440 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5441 { { "a1" }, "r0" }, 5442 { { "a2" }, "r1" }, 5443 { { "a3" }, "r2" }, 5444 { { "a4" }, "r3" }, 5445 { { "v1" }, "r4" }, 5446 { { "v2" }, "r5" }, 5447 { { "v3" }, "r6" }, 5448 { { "v4" }, "r7" }, 5449 { { "v5" }, "r8" }, 5450 { { "v6", "rfp" }, "r9" }, 5451 { { "sl" }, "r10" }, 5452 { { "fp" }, "r11" }, 5453 { { "ip" }, "r12" }, 5454 { { "r13" }, "sp" }, 5455 { { "r14" }, "lr" }, 5456 { { "r15" }, "pc" }, 5457 // The S, D and Q registers overlap, but aren't really aliases; we 5458 // don't want to substitute one of these for a different-sized one. 5459 }; 5460 5461 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5462 return llvm::makeArrayRef(GCCRegAliases); 5463 } 5464 5465 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5466 #define BUILTIN(ID, TYPE, ATTRS) \ 5467 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5468 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5469 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5470 #include "clang/Basic/BuiltinsNEON.def" 5471 5472 #define BUILTIN(ID, TYPE, ATTRS) \ 5473 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5474 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5475 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5476 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5477 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5478 #include "clang/Basic/BuiltinsARM.def" 5479 }; 5480 5481 class ARMleTargetInfo : public ARMTargetInfo { 5482 public: 5483 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5484 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5485 void getTargetDefines(const LangOptions &Opts, 5486 MacroBuilder &Builder) const override { 5487 Builder.defineMacro("__ARMEL__"); 5488 ARMTargetInfo::getTargetDefines(Opts, Builder); 5489 } 5490 }; 5491 5492 class ARMbeTargetInfo : public ARMTargetInfo { 5493 public: 5494 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5495 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5496 void getTargetDefines(const LangOptions &Opts, 5497 MacroBuilder &Builder) const override { 5498 Builder.defineMacro("__ARMEB__"); 5499 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5500 ARMTargetInfo::getTargetDefines(Opts, Builder); 5501 } 5502 }; 5503 5504 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5505 const llvm::Triple Triple; 5506 public: 5507 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5508 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5509 WCharType = UnsignedShort; 5510 SizeType = UnsignedInt; 5511 } 5512 void getVisualStudioDefines(const LangOptions &Opts, 5513 MacroBuilder &Builder) const { 5514 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5515 5516 // FIXME: this is invalid for WindowsCE 5517 Builder.defineMacro("_M_ARM_NT", "1"); 5518 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5519 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5520 5521 assert((Triple.getArch() == llvm::Triple::arm || 5522 Triple.getArch() == llvm::Triple::thumb) && 5523 "invalid architecture for Windows ARM target info"); 5524 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5525 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5526 5527 // TODO map the complete set of values 5528 // 31: VFPv3 40: VFPv4 5529 Builder.defineMacro("_M_ARM_FP", "31"); 5530 } 5531 BuiltinVaListKind getBuiltinVaListKind() const override { 5532 return TargetInfo::CharPtrBuiltinVaList; 5533 } 5534 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5535 switch (CC) { 5536 case CC_X86StdCall: 5537 case CC_X86ThisCall: 5538 case CC_X86FastCall: 5539 case CC_X86VectorCall: 5540 return CCCR_Ignore; 5541 case CC_C: 5542 return CCCR_OK; 5543 default: 5544 return CCCR_Warning; 5545 } 5546 } 5547 }; 5548 5549 // Windows ARM + Itanium C++ ABI Target 5550 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5551 public: 5552 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5553 const TargetOptions &Opts) 5554 : WindowsARMTargetInfo(Triple, Opts) { 5555 TheCXXABI.set(TargetCXXABI::GenericARM); 5556 } 5557 5558 void getTargetDefines(const LangOptions &Opts, 5559 MacroBuilder &Builder) const override { 5560 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5561 5562 if (Opts.MSVCCompat) 5563 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5564 } 5565 }; 5566 5567 // Windows ARM, MS (C++) ABI 5568 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5569 public: 5570 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5571 const TargetOptions &Opts) 5572 : WindowsARMTargetInfo(Triple, Opts) { 5573 TheCXXABI.set(TargetCXXABI::Microsoft); 5574 } 5575 5576 void getTargetDefines(const LangOptions &Opts, 5577 MacroBuilder &Builder) const override { 5578 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5579 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5580 } 5581 }; 5582 5583 // ARM MinGW target 5584 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5585 public: 5586 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5587 : WindowsARMTargetInfo(Triple, Opts) { 5588 TheCXXABI.set(TargetCXXABI::GenericARM); 5589 } 5590 5591 void getTargetDefines(const LangOptions &Opts, 5592 MacroBuilder &Builder) const override { 5593 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5594 DefineStd(Builder, "WIN32", Opts); 5595 DefineStd(Builder, "WINNT", Opts); 5596 Builder.defineMacro("_ARM_"); 5597 addMinGWDefines(Opts, Builder); 5598 } 5599 }; 5600 5601 // ARM Cygwin target 5602 class CygwinARMTargetInfo : public ARMleTargetInfo { 5603 public: 5604 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5605 : ARMleTargetInfo(Triple, Opts) { 5606 TLSSupported = false; 5607 WCharType = UnsignedShort; 5608 DoubleAlign = LongLongAlign = 64; 5609 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5610 } 5611 void getTargetDefines(const LangOptions &Opts, 5612 MacroBuilder &Builder) const override { 5613 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5614 Builder.defineMacro("_ARM_"); 5615 Builder.defineMacro("__CYGWIN__"); 5616 Builder.defineMacro("__CYGWIN32__"); 5617 DefineStd(Builder, "unix", Opts); 5618 if (Opts.CPlusPlus) 5619 Builder.defineMacro("_GNU_SOURCE"); 5620 } 5621 }; 5622 5623 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5624 protected: 5625 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5626 MacroBuilder &Builder) const override { 5627 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5628 } 5629 5630 public: 5631 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5632 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5633 HasAlignMac68kSupport = true; 5634 // iOS always has 64-bit atomic instructions. 5635 // FIXME: This should be based off of the target features in 5636 // ARMleTargetInfo. 5637 MaxAtomicInlineWidth = 64; 5638 5639 if (Triple.isWatchABI()) { 5640 // Darwin on iOS uses a variant of the ARM C++ ABI. 5641 TheCXXABI.set(TargetCXXABI::WatchOS); 5642 5643 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5644 // size_t is long, it's a bit weird for it to be int. 5645 PtrDiffType = SignedLong; 5646 5647 // BOOL should be a real boolean on the new ABI 5648 UseSignedCharForObjCBool = false; 5649 } else 5650 TheCXXABI.set(TargetCXXABI::iOS); 5651 } 5652 }; 5653 5654 class AArch64TargetInfo : public TargetInfo { 5655 virtual void setDataLayout() = 0; 5656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5657 static const char *const GCCRegNames[]; 5658 5659 enum FPUModeEnum { 5660 FPUMode, 5661 NeonMode 5662 }; 5663 5664 unsigned FPU; 5665 unsigned CRC; 5666 unsigned Crypto; 5667 unsigned Unaligned; 5668 unsigned V8_1A; 5669 5670 static const Builtin::Info BuiltinInfo[]; 5671 5672 std::string ABI; 5673 5674 public: 5675 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5676 : TargetInfo(Triple), ABI("aapcs") { 5677 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5678 WCharType = SignedInt; 5679 5680 // NetBSD apparently prefers consistency across ARM targets to consistency 5681 // across 64-bit targets. 5682 Int64Type = SignedLongLong; 5683 IntMaxType = SignedLongLong; 5684 } else { 5685 WCharType = UnsignedInt; 5686 Int64Type = SignedLong; 5687 IntMaxType = SignedLong; 5688 } 5689 5690 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5691 MaxVectorAlign = 128; 5692 MaxAtomicInlineWidth = 128; 5693 MaxAtomicPromoteWidth = 128; 5694 5695 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5696 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5697 5698 // {} in inline assembly are neon specifiers, not assembly variant 5699 // specifiers. 5700 NoAsmVariants = true; 5701 5702 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5703 // contributes to the alignment of the containing aggregate in the same way 5704 // a plain (non bit-field) member of that type would, without exception for 5705 // zero-sized or anonymous bit-fields." 5706 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5707 UseZeroLengthBitfieldAlignment = true; 5708 5709 // AArch64 targets default to using the ARM C++ ABI. 5710 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5711 5712 if (Triple.getOS() == llvm::Triple::Linux || 5713 Triple.getOS() == llvm::Triple::UnknownOS) 5714 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5715 } 5716 5717 StringRef getABI() const override { return ABI; } 5718 bool setABI(const std::string &Name) override { 5719 if (Name != "aapcs" && Name != "darwinpcs") 5720 return false; 5721 5722 ABI = Name; 5723 return true; 5724 } 5725 5726 bool setCPU(const std::string &Name) override { 5727 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5728 .Case("generic", true) 5729 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5730 "cortex-a35", "exynos-m1", true) 5731 .Case("cortex-a73", true) 5732 .Case("cyclone", true) 5733 .Case("kryo", true) 5734 .Case("vulcan", true) 5735 .Default(false); 5736 return CPUKnown; 5737 } 5738 5739 void getTargetDefines(const LangOptions &Opts, 5740 MacroBuilder &Builder) const override { 5741 // Target identification. 5742 Builder.defineMacro("__aarch64__"); 5743 5744 // Target properties. 5745 Builder.defineMacro("_LP64"); 5746 Builder.defineMacro("__LP64__"); 5747 5748 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5749 Builder.defineMacro("__ARM_ACLE", "200"); 5750 Builder.defineMacro("__ARM_ARCH", "8"); 5751 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5752 5753 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5754 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5755 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5756 5757 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5758 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5759 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5760 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5761 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5762 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5763 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5764 5765 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5766 5767 // 0xe implies support for half, single and double precision operations. 5768 Builder.defineMacro("__ARM_FP", "0xE"); 5769 5770 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5771 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5772 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5773 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5774 5775 if (Opts.UnsafeFPMath) 5776 Builder.defineMacro("__ARM_FP_FAST", "1"); 5777 5778 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5779 5780 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5781 Opts.ShortEnums ? "1" : "4"); 5782 5783 if (FPU == NeonMode) { 5784 Builder.defineMacro("__ARM_NEON", "1"); 5785 // 64-bit NEON supports half, single and double precision operations. 5786 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5787 } 5788 5789 if (CRC) 5790 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5791 5792 if (Crypto) 5793 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5794 5795 if (Unaligned) 5796 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5797 5798 if (V8_1A) 5799 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5800 5801 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5804 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5805 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5806 } 5807 5808 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5809 return llvm::makeArrayRef(BuiltinInfo, 5810 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5811 } 5812 5813 bool hasFeature(StringRef Feature) const override { 5814 return Feature == "aarch64" || 5815 Feature == "arm64" || 5816 Feature == "arm" || 5817 (Feature == "neon" && FPU == NeonMode); 5818 } 5819 5820 bool handleTargetFeatures(std::vector<std::string> &Features, 5821 DiagnosticsEngine &Diags) override { 5822 FPU = FPUMode; 5823 CRC = 0; 5824 Crypto = 0; 5825 Unaligned = 1; 5826 V8_1A = 0; 5827 5828 for (const auto &Feature : Features) { 5829 if (Feature == "+neon") 5830 FPU = NeonMode; 5831 if (Feature == "+crc") 5832 CRC = 1; 5833 if (Feature == "+crypto") 5834 Crypto = 1; 5835 if (Feature == "+strict-align") 5836 Unaligned = 0; 5837 if (Feature == "+v8.1a") 5838 V8_1A = 1; 5839 } 5840 5841 setDataLayout(); 5842 5843 return true; 5844 } 5845 5846 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5847 switch (CC) { 5848 case CC_C: 5849 case CC_Swift: 5850 case CC_PreserveMost: 5851 case CC_PreserveAll: 5852 return CCCR_OK; 5853 default: 5854 return CCCR_Warning; 5855 } 5856 } 5857 5858 bool isCLZForZeroUndef() const override { return false; } 5859 5860 BuiltinVaListKind getBuiltinVaListKind() const override { 5861 return TargetInfo::AArch64ABIBuiltinVaList; 5862 } 5863 5864 ArrayRef<const char *> getGCCRegNames() const override; 5865 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5866 5867 bool validateAsmConstraint(const char *&Name, 5868 TargetInfo::ConstraintInfo &Info) const override { 5869 switch (*Name) { 5870 default: 5871 return false; 5872 case 'w': // Floating point and SIMD registers (V0-V31) 5873 Info.setAllowsRegister(); 5874 return true; 5875 case 'I': // Constant that can be used with an ADD instruction 5876 case 'J': // Constant that can be used with a SUB instruction 5877 case 'K': // Constant that can be used with a 32-bit logical instruction 5878 case 'L': // Constant that can be used with a 64-bit logical instruction 5879 case 'M': // Constant that can be used as a 32-bit MOV immediate 5880 case 'N': // Constant that can be used as a 64-bit MOV immediate 5881 case 'Y': // Floating point constant zero 5882 case 'Z': // Integer constant zero 5883 return true; 5884 case 'Q': // A memory reference with base register and no offset 5885 Info.setAllowsMemory(); 5886 return true; 5887 case 'S': // A symbolic address 5888 Info.setAllowsRegister(); 5889 return true; 5890 case 'U': 5891 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5892 // Utf: A memory address suitable for ldp/stp in TF mode. 5893 // Usa: An absolute symbolic address. 5894 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5895 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5896 case 'z': // Zero register, wzr or xzr 5897 Info.setAllowsRegister(); 5898 return true; 5899 case 'x': // Floating point and SIMD registers (V0-V15) 5900 Info.setAllowsRegister(); 5901 return true; 5902 } 5903 return false; 5904 } 5905 5906 bool 5907 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5908 std::string &SuggestedModifier) const override { 5909 // Strip off constraint modifiers. 5910 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5911 Constraint = Constraint.substr(1); 5912 5913 switch (Constraint[0]) { 5914 default: 5915 return true; 5916 case 'z': 5917 case 'r': { 5918 switch (Modifier) { 5919 case 'x': 5920 case 'w': 5921 // For now assume that the person knows what they're 5922 // doing with the modifier. 5923 return true; 5924 default: 5925 // By default an 'r' constraint will be in the 'x' 5926 // registers. 5927 if (Size == 64) 5928 return true; 5929 5930 SuggestedModifier = "w"; 5931 return false; 5932 } 5933 } 5934 } 5935 } 5936 5937 const char *getClobbers() const override { return ""; } 5938 5939 int getEHDataRegisterNumber(unsigned RegNo) const override { 5940 if (RegNo == 0) 5941 return 0; 5942 if (RegNo == 1) 5943 return 1; 5944 return -1; 5945 } 5946 }; 5947 5948 const char *const AArch64TargetInfo::GCCRegNames[] = { 5949 // 32-bit Integer registers 5950 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5951 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5952 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5953 5954 // 64-bit Integer registers 5955 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5956 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5957 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5958 5959 // 32-bit floating point regsisters 5960 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5961 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5962 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5963 5964 // 64-bit floating point regsisters 5965 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5966 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5967 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5968 5969 // Vector registers 5970 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5971 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5972 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5973 }; 5974 5975 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5976 return llvm::makeArrayRef(GCCRegNames); 5977 } 5978 5979 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5980 { { "w31" }, "wsp" }, 5981 { { "x29" }, "fp" }, 5982 { { "x30" }, "lr" }, 5983 { { "x31" }, "sp" }, 5984 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5985 // don't want to substitute one of these for a different-sized one. 5986 }; 5987 5988 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5989 return llvm::makeArrayRef(GCCRegAliases); 5990 } 5991 5992 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5993 #define BUILTIN(ID, TYPE, ATTRS) \ 5994 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5995 #include "clang/Basic/BuiltinsNEON.def" 5996 5997 #define BUILTIN(ID, TYPE, ATTRS) \ 5998 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5999 #include "clang/Basic/BuiltinsAArch64.def" 6000 }; 6001 6002 class AArch64leTargetInfo : public AArch64TargetInfo { 6003 void setDataLayout() override { 6004 if (getTriple().isOSBinFormatMachO()) 6005 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6006 else 6007 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6008 } 6009 6010 public: 6011 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6012 : AArch64TargetInfo(Triple, Opts) { 6013 BigEndian = false; 6014 } 6015 void getTargetDefines(const LangOptions &Opts, 6016 MacroBuilder &Builder) const override { 6017 Builder.defineMacro("__AARCH64EL__"); 6018 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6019 } 6020 }; 6021 6022 class AArch64beTargetInfo : public AArch64TargetInfo { 6023 void setDataLayout() override { 6024 assert(!getTriple().isOSBinFormatMachO()); 6025 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6026 } 6027 6028 public: 6029 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6030 : AArch64TargetInfo(Triple, Opts) {} 6031 void getTargetDefines(const LangOptions &Opts, 6032 MacroBuilder &Builder) const override { 6033 Builder.defineMacro("__AARCH64EB__"); 6034 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6035 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6036 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6037 } 6038 }; 6039 6040 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6041 protected: 6042 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6043 MacroBuilder &Builder) const override { 6044 Builder.defineMacro("__AARCH64_SIMD__"); 6045 Builder.defineMacro("__ARM64_ARCH_8__"); 6046 Builder.defineMacro("__ARM_NEON__"); 6047 Builder.defineMacro("__LITTLE_ENDIAN__"); 6048 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6049 Builder.defineMacro("__arm64", "1"); 6050 Builder.defineMacro("__arm64__", "1"); 6051 6052 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6053 } 6054 6055 public: 6056 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6057 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6058 Int64Type = SignedLongLong; 6059 WCharType = SignedInt; 6060 UseSignedCharForObjCBool = false; 6061 6062 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6063 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6064 6065 TheCXXABI.set(TargetCXXABI::iOS64); 6066 } 6067 6068 BuiltinVaListKind getBuiltinVaListKind() const override { 6069 return TargetInfo::CharPtrBuiltinVaList; 6070 } 6071 }; 6072 6073 // Hexagon abstract base class 6074 class HexagonTargetInfo : public TargetInfo { 6075 static const Builtin::Info BuiltinInfo[]; 6076 static const char * const GCCRegNames[]; 6077 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6078 std::string CPU; 6079 bool HasHVX, HasHVXDouble; 6080 6081 public: 6082 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6083 : TargetInfo(Triple) { 6084 BigEndian = false; 6085 // Specify the vector alignment explicitly. For v512x1, the calculated 6086 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6087 // the required minimum of 64 bytes. 6088 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6089 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6090 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6091 SizeType = UnsignedInt; 6092 PtrDiffType = SignedInt; 6093 IntPtrType = SignedInt; 6094 6095 // {} in inline assembly are packet specifiers, not assembly variant 6096 // specifiers. 6097 NoAsmVariants = true; 6098 6099 LargeArrayMinWidth = 64; 6100 LargeArrayAlign = 64; 6101 UseBitFieldTypeAlignment = true; 6102 ZeroLengthBitfieldBoundary = 32; 6103 HasHVX = HasHVXDouble = false; 6104 } 6105 6106 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6107 return llvm::makeArrayRef(BuiltinInfo, 6108 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6109 } 6110 6111 bool validateAsmConstraint(const char *&Name, 6112 TargetInfo::ConstraintInfo &Info) const override { 6113 switch (*Name) { 6114 case 'v': 6115 case 'q': 6116 if (HasHVX) { 6117 Info.setAllowsRegister(); 6118 return true; 6119 } 6120 break; 6121 case 's': 6122 // Relocatable constant. 6123 return true; 6124 } 6125 return false; 6126 } 6127 6128 void getTargetDefines(const LangOptions &Opts, 6129 MacroBuilder &Builder) const override; 6130 6131 bool isCLZForZeroUndef() const override { return false; } 6132 6133 bool hasFeature(StringRef Feature) const override { 6134 return llvm::StringSwitch<bool>(Feature) 6135 .Case("hexagon", true) 6136 .Case("hvx", HasHVX) 6137 .Case("hvx-double", HasHVXDouble) 6138 .Default(false); 6139 } 6140 6141 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6142 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6143 const override; 6144 6145 bool handleTargetFeatures(std::vector<std::string> &Features, 6146 DiagnosticsEngine &Diags) override; 6147 6148 BuiltinVaListKind getBuiltinVaListKind() const override { 6149 return TargetInfo::CharPtrBuiltinVaList; 6150 } 6151 ArrayRef<const char *> getGCCRegNames() const override; 6152 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6153 const char *getClobbers() const override { 6154 return ""; 6155 } 6156 6157 static const char *getHexagonCPUSuffix(StringRef Name) { 6158 return llvm::StringSwitch<const char*>(Name) 6159 .Case("hexagonv4", "4") 6160 .Case("hexagonv5", "5") 6161 .Case("hexagonv55", "55") 6162 .Case("hexagonv60", "60") 6163 .Default(nullptr); 6164 } 6165 6166 bool setCPU(const std::string &Name) override { 6167 if (!getHexagonCPUSuffix(Name)) 6168 return false; 6169 CPU = Name; 6170 return true; 6171 } 6172 6173 int getEHDataRegisterNumber(unsigned RegNo) const override { 6174 return RegNo < 2 ? RegNo : -1; 6175 } 6176 }; 6177 6178 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6179 MacroBuilder &Builder) const { 6180 Builder.defineMacro("__qdsp6__", "1"); 6181 Builder.defineMacro("__hexagon__", "1"); 6182 6183 if (CPU == "hexagonv4") { 6184 Builder.defineMacro("__HEXAGON_V4__"); 6185 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6186 if (Opts.HexagonQdsp6Compat) { 6187 Builder.defineMacro("__QDSP6_V4__"); 6188 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6189 } 6190 } else if (CPU == "hexagonv5") { 6191 Builder.defineMacro("__HEXAGON_V5__"); 6192 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6193 if(Opts.HexagonQdsp6Compat) { 6194 Builder.defineMacro("__QDSP6_V5__"); 6195 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6196 } 6197 } else if (CPU == "hexagonv55") { 6198 Builder.defineMacro("__HEXAGON_V55__"); 6199 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6200 Builder.defineMacro("__QDSP6_V55__"); 6201 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6202 } else if (CPU == "hexagonv60") { 6203 Builder.defineMacro("__HEXAGON_V60__"); 6204 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6205 Builder.defineMacro("__QDSP6_V60__"); 6206 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6207 } 6208 6209 if (hasFeature("hvx")) { 6210 Builder.defineMacro("__HVX__"); 6211 if (hasFeature("hvx-double")) 6212 Builder.defineMacro("__HVXDBL__"); 6213 } 6214 } 6215 6216 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6217 DiagnosticsEngine &Diags) { 6218 for (auto &F : Features) { 6219 if (F == "+hvx") 6220 HasHVX = true; 6221 else if (F == "-hvx") 6222 HasHVX = HasHVXDouble = false; 6223 else if (F == "+hvx-double") 6224 HasHVX = HasHVXDouble = true; 6225 else if (F == "-hvx-double") 6226 HasHVXDouble = false; 6227 } 6228 return true; 6229 } 6230 6231 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6232 DiagnosticsEngine &Diags, StringRef CPU, 6233 const std::vector<std::string> &FeaturesVec) const { 6234 // Default for v60: -hvx, -hvx-double. 6235 Features["hvx"] = false; 6236 Features["hvx-double"] = false; 6237 6238 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6239 } 6240 6241 6242 const char *const HexagonTargetInfo::GCCRegNames[] = { 6243 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6244 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6245 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6246 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6247 "p0", "p1", "p2", "p3", 6248 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6249 }; 6250 6251 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6252 return llvm::makeArrayRef(GCCRegNames); 6253 } 6254 6255 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6256 { { "sp" }, "r29" }, 6257 { { "fp" }, "r30" }, 6258 { { "lr" }, "r31" }, 6259 }; 6260 6261 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6262 return llvm::makeArrayRef(GCCRegAliases); 6263 } 6264 6265 6266 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6267 #define BUILTIN(ID, TYPE, ATTRS) \ 6268 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6269 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6270 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6271 #include "clang/Basic/BuiltinsHexagon.def" 6272 }; 6273 6274 class LanaiTargetInfo : public TargetInfo { 6275 // Class for Lanai (32-bit). 6276 // The CPU profiles supported by the Lanai backend 6277 enum CPUKind { 6278 CK_NONE, 6279 CK_V11, 6280 } CPU; 6281 6282 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6283 static const char *const GCCRegNames[]; 6284 6285 public: 6286 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6287 : TargetInfo(Triple) { 6288 // Description string has to be kept in sync with backend. 6289 resetDataLayout("E" // Big endian 6290 "-m:e" // ELF name manging 6291 "-p:32:32" // 32 bit pointers, 32 bit aligned 6292 "-i64:64" // 64 bit integers, 64 bit aligned 6293 "-a:0:32" // 32 bit alignment of objects of aggregate type 6294 "-n32" // 32 bit native integer width 6295 "-S64" // 64 bit natural stack alignment 6296 ); 6297 6298 // Setting RegParmMax equal to what mregparm was set to in the old 6299 // toolchain 6300 RegParmMax = 4; 6301 6302 // Set the default CPU to V11 6303 CPU = CK_V11; 6304 6305 // Temporary approach to make everything at least word-aligned and allow for 6306 // safely casting between pointers with different alignment requirements. 6307 // TODO: Remove this when there are no more cast align warnings on the 6308 // firmware. 6309 MinGlobalAlign = 32; 6310 } 6311 6312 void getTargetDefines(const LangOptions &Opts, 6313 MacroBuilder &Builder) const override { 6314 // Define __lanai__ when building for target lanai. 6315 Builder.defineMacro("__lanai__"); 6316 6317 // Set define for the CPU specified. 6318 switch (CPU) { 6319 case CK_V11: 6320 Builder.defineMacro("__LANAI_V11__"); 6321 break; 6322 case CK_NONE: 6323 llvm_unreachable("Unhandled target CPU"); 6324 } 6325 } 6326 6327 bool setCPU(const std::string &Name) override { 6328 CPU = llvm::StringSwitch<CPUKind>(Name) 6329 .Case("v11", CK_V11) 6330 .Default(CK_NONE); 6331 6332 return CPU != CK_NONE; 6333 } 6334 6335 bool hasFeature(StringRef Feature) const override { 6336 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6337 } 6338 6339 ArrayRef<const char *> getGCCRegNames() const override; 6340 6341 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6342 6343 BuiltinVaListKind getBuiltinVaListKind() const override { 6344 return TargetInfo::VoidPtrBuiltinVaList; 6345 } 6346 6347 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6348 6349 bool validateAsmConstraint(const char *&Name, 6350 TargetInfo::ConstraintInfo &info) const override { 6351 return false; 6352 } 6353 6354 const char *getClobbers() const override { return ""; } 6355 }; 6356 6357 const char *const LanaiTargetInfo::GCCRegNames[] = { 6358 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6359 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6360 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6361 6362 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6363 return llvm::makeArrayRef(GCCRegNames); 6364 } 6365 6366 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6367 {{"pc"}, "r2"}, 6368 {{"sp"}, "r4"}, 6369 {{"fp"}, "r5"}, 6370 {{"rv"}, "r8"}, 6371 {{"rr1"}, "r10"}, 6372 {{"rr2"}, "r11"}, 6373 {{"rca"}, "r15"}, 6374 }; 6375 6376 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6377 return llvm::makeArrayRef(GCCRegAliases); 6378 } 6379 6380 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6381 class SparcTargetInfo : public TargetInfo { 6382 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6383 static const char * const GCCRegNames[]; 6384 bool SoftFloat; 6385 public: 6386 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6387 : TargetInfo(Triple), SoftFloat(false) {} 6388 6389 int getEHDataRegisterNumber(unsigned RegNo) const override { 6390 if (RegNo == 0) return 24; 6391 if (RegNo == 1) return 25; 6392 return -1; 6393 } 6394 6395 bool handleTargetFeatures(std::vector<std::string> &Features, 6396 DiagnosticsEngine &Diags) override { 6397 // Check if software floating point is enabled 6398 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6399 if (Feature != Features.end()) { 6400 SoftFloat = true; 6401 } 6402 return true; 6403 } 6404 void getTargetDefines(const LangOptions &Opts, 6405 MacroBuilder &Builder) const override { 6406 DefineStd(Builder, "sparc", Opts); 6407 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6408 6409 if (SoftFloat) 6410 Builder.defineMacro("SOFT_FLOAT", "1"); 6411 } 6412 6413 bool hasFeature(StringRef Feature) const override { 6414 return llvm::StringSwitch<bool>(Feature) 6415 .Case("softfloat", SoftFloat) 6416 .Case("sparc", true) 6417 .Default(false); 6418 } 6419 6420 bool hasSjLjLowering() const override { 6421 return true; 6422 } 6423 6424 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6425 // FIXME: Implement! 6426 return None; 6427 } 6428 BuiltinVaListKind getBuiltinVaListKind() const override { 6429 return TargetInfo::VoidPtrBuiltinVaList; 6430 } 6431 ArrayRef<const char *> getGCCRegNames() const override; 6432 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6433 bool validateAsmConstraint(const char *&Name, 6434 TargetInfo::ConstraintInfo &info) const override { 6435 // FIXME: Implement! 6436 switch (*Name) { 6437 case 'I': // Signed 13-bit constant 6438 case 'J': // Zero 6439 case 'K': // 32-bit constant with the low 12 bits clear 6440 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6441 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6442 case 'N': // Same as 'K' but zext (required for SIMode) 6443 case 'O': // The constant 4096 6444 return true; 6445 } 6446 return false; 6447 } 6448 const char *getClobbers() const override { 6449 // FIXME: Implement! 6450 return ""; 6451 } 6452 6453 // No Sparc V7 for now, the backend doesn't support it anyway. 6454 enum CPUKind { 6455 CK_GENERIC, 6456 CK_V8, 6457 CK_SUPERSPARC, 6458 CK_SPARCLITE, 6459 CK_F934, 6460 CK_HYPERSPARC, 6461 CK_SPARCLITE86X, 6462 CK_SPARCLET, 6463 CK_TSC701, 6464 CK_V9, 6465 CK_ULTRASPARC, 6466 CK_ULTRASPARC3, 6467 CK_NIAGARA, 6468 CK_NIAGARA2, 6469 CK_NIAGARA3, 6470 CK_NIAGARA4, 6471 CK_MYRIAD2_1, 6472 CK_MYRIAD2_2 6473 } CPU = CK_GENERIC; 6474 6475 enum CPUGeneration { 6476 CG_V8, 6477 CG_V9, 6478 }; 6479 6480 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6481 switch (Kind) { 6482 case CK_GENERIC: 6483 case CK_V8: 6484 case CK_SUPERSPARC: 6485 case CK_SPARCLITE: 6486 case CK_F934: 6487 case CK_HYPERSPARC: 6488 case CK_SPARCLITE86X: 6489 case CK_SPARCLET: 6490 case CK_TSC701: 6491 case CK_MYRIAD2_1: 6492 case CK_MYRIAD2_2: 6493 return CG_V8; 6494 case CK_V9: 6495 case CK_ULTRASPARC: 6496 case CK_ULTRASPARC3: 6497 case CK_NIAGARA: 6498 case CK_NIAGARA2: 6499 case CK_NIAGARA3: 6500 case CK_NIAGARA4: 6501 return CG_V9; 6502 } 6503 llvm_unreachable("Unexpected CPU kind"); 6504 } 6505 6506 CPUKind getCPUKind(StringRef Name) const { 6507 return llvm::StringSwitch<CPUKind>(Name) 6508 .Case("v8", CK_V8) 6509 .Case("supersparc", CK_SUPERSPARC) 6510 .Case("sparclite", CK_SPARCLITE) 6511 .Case("f934", CK_F934) 6512 .Case("hypersparc", CK_HYPERSPARC) 6513 .Case("sparclite86x", CK_SPARCLITE86X) 6514 .Case("sparclet", CK_SPARCLET) 6515 .Case("tsc701", CK_TSC701) 6516 .Case("v9", CK_V9) 6517 .Case("ultrasparc", CK_ULTRASPARC) 6518 .Case("ultrasparc3", CK_ULTRASPARC3) 6519 .Case("niagara", CK_NIAGARA) 6520 .Case("niagara2", CK_NIAGARA2) 6521 .Case("niagara3", CK_NIAGARA3) 6522 .Case("niagara4", CK_NIAGARA4) 6523 .Case("myriad2", CK_MYRIAD2_1) 6524 .Case("myriad2.1", CK_MYRIAD2_1) 6525 .Case("myriad2.2", CK_MYRIAD2_2) 6526 .Default(CK_GENERIC); 6527 } 6528 6529 bool setCPU(const std::string &Name) override { 6530 CPU = getCPUKind(Name); 6531 return CPU != CK_GENERIC; 6532 } 6533 }; 6534 6535 const char * const SparcTargetInfo::GCCRegNames[] = { 6536 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6537 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6538 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6539 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6540 }; 6541 6542 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6543 return llvm::makeArrayRef(GCCRegNames); 6544 } 6545 6546 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6547 { { "g0" }, "r0" }, 6548 { { "g1" }, "r1" }, 6549 { { "g2" }, "r2" }, 6550 { { "g3" }, "r3" }, 6551 { { "g4" }, "r4" }, 6552 { { "g5" }, "r5" }, 6553 { { "g6" }, "r6" }, 6554 { { "g7" }, "r7" }, 6555 { { "o0" }, "r8" }, 6556 { { "o1" }, "r9" }, 6557 { { "o2" }, "r10" }, 6558 { { "o3" }, "r11" }, 6559 { { "o4" }, "r12" }, 6560 { { "o5" }, "r13" }, 6561 { { "o6", "sp" }, "r14" }, 6562 { { "o7" }, "r15" }, 6563 { { "l0" }, "r16" }, 6564 { { "l1" }, "r17" }, 6565 { { "l2" }, "r18" }, 6566 { { "l3" }, "r19" }, 6567 { { "l4" }, "r20" }, 6568 { { "l5" }, "r21" }, 6569 { { "l6" }, "r22" }, 6570 { { "l7" }, "r23" }, 6571 { { "i0" }, "r24" }, 6572 { { "i1" }, "r25" }, 6573 { { "i2" }, "r26" }, 6574 { { "i3" }, "r27" }, 6575 { { "i4" }, "r28" }, 6576 { { "i5" }, "r29" }, 6577 { { "i6", "fp" }, "r30" }, 6578 { { "i7" }, "r31" }, 6579 }; 6580 6581 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6582 return llvm::makeArrayRef(GCCRegAliases); 6583 } 6584 6585 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6586 class SparcV8TargetInfo : public SparcTargetInfo { 6587 public: 6588 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6589 : SparcTargetInfo(Triple, Opts) { 6590 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6591 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6592 switch (getTriple().getOS()) { 6593 default: 6594 SizeType = UnsignedInt; 6595 IntPtrType = SignedInt; 6596 PtrDiffType = SignedInt; 6597 break; 6598 case llvm::Triple::NetBSD: 6599 case llvm::Triple::OpenBSD: 6600 SizeType = UnsignedLong; 6601 IntPtrType = SignedLong; 6602 PtrDiffType = SignedLong; 6603 break; 6604 } 6605 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6606 } 6607 6608 void getTargetDefines(const LangOptions &Opts, 6609 MacroBuilder &Builder) const override { 6610 SparcTargetInfo::getTargetDefines(Opts, Builder); 6611 switch (getCPUGeneration(CPU)) { 6612 case CG_V8: 6613 Builder.defineMacro("__sparcv8"); 6614 if (getTriple().getOS() != llvm::Triple::Solaris) 6615 Builder.defineMacro("__sparcv8__"); 6616 break; 6617 case CG_V9: 6618 Builder.defineMacro("__sparcv9"); 6619 if (getTriple().getOS() != llvm::Triple::Solaris) { 6620 Builder.defineMacro("__sparcv9__"); 6621 Builder.defineMacro("__sparc_v9__"); 6622 } 6623 break; 6624 } 6625 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6626 switch (CPU) { 6627 case CK_MYRIAD2_1: 6628 Builder.defineMacro("__myriad2", "1"); 6629 Builder.defineMacro("__myriad2__", "1"); 6630 break; 6631 case CK_MYRIAD2_2: 6632 Builder.defineMacro("__myriad2", "2"); 6633 Builder.defineMacro("__myriad2__", "2"); 6634 break; 6635 default: 6636 break; 6637 } 6638 } 6639 } 6640 6641 bool hasSjLjLowering() const override { 6642 return true; 6643 } 6644 }; 6645 6646 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6647 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6648 public: 6649 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6650 : SparcV8TargetInfo(Triple, Opts) { 6651 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6652 BigEndian = false; 6653 } 6654 }; 6655 6656 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6657 class SparcV9TargetInfo : public SparcTargetInfo { 6658 public: 6659 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6660 : SparcTargetInfo(Triple, Opts) { 6661 // FIXME: Support Sparc quad-precision long double? 6662 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6663 // This is an LP64 platform. 6664 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6665 6666 // OpenBSD uses long long for int64_t and intmax_t. 6667 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6668 IntMaxType = SignedLongLong; 6669 else 6670 IntMaxType = SignedLong; 6671 Int64Type = IntMaxType; 6672 6673 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6674 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6675 LongDoubleWidth = 128; 6676 LongDoubleAlign = 128; 6677 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6678 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6679 } 6680 6681 void getTargetDefines(const LangOptions &Opts, 6682 MacroBuilder &Builder) const override { 6683 SparcTargetInfo::getTargetDefines(Opts, Builder); 6684 Builder.defineMacro("__sparcv9"); 6685 Builder.defineMacro("__arch64__"); 6686 // Solaris doesn't need these variants, but the BSDs do. 6687 if (getTriple().getOS() != llvm::Triple::Solaris) { 6688 Builder.defineMacro("__sparc64__"); 6689 Builder.defineMacro("__sparc_v9__"); 6690 Builder.defineMacro("__sparcv9__"); 6691 } 6692 } 6693 6694 bool setCPU(const std::string &Name) override { 6695 if (!SparcTargetInfo::setCPU(Name)) 6696 return false; 6697 return getCPUGeneration(CPU) == CG_V9; 6698 } 6699 }; 6700 6701 class SystemZTargetInfo : public TargetInfo { 6702 static const Builtin::Info BuiltinInfo[]; 6703 static const char *const GCCRegNames[]; 6704 std::string CPU; 6705 bool HasTransactionalExecution; 6706 bool HasVector; 6707 6708 public: 6709 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6710 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6711 HasVector(false) { 6712 IntMaxType = SignedLong; 6713 Int64Type = SignedLong; 6714 TLSSupported = true; 6715 IntWidth = IntAlign = 32; 6716 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6717 PointerWidth = PointerAlign = 64; 6718 LongDoubleWidth = 128; 6719 LongDoubleAlign = 64; 6720 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6721 DefaultAlignForAttributeAligned = 64; 6722 MinGlobalAlign = 16; 6723 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6724 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6725 } 6726 void getTargetDefines(const LangOptions &Opts, 6727 MacroBuilder &Builder) const override { 6728 Builder.defineMacro("__s390__"); 6729 Builder.defineMacro("__s390x__"); 6730 Builder.defineMacro("__zarch__"); 6731 Builder.defineMacro("__LONG_DOUBLE_128__"); 6732 6733 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6734 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6735 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6736 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6737 6738 if (HasTransactionalExecution) 6739 Builder.defineMacro("__HTM__"); 6740 if (Opts.ZVector) 6741 Builder.defineMacro("__VEC__", "10301"); 6742 } 6743 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6744 return llvm::makeArrayRef(BuiltinInfo, 6745 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6746 } 6747 6748 ArrayRef<const char *> getGCCRegNames() const override; 6749 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6750 // No aliases. 6751 return None; 6752 } 6753 bool validateAsmConstraint(const char *&Name, 6754 TargetInfo::ConstraintInfo &info) const override; 6755 const char *getClobbers() const override { 6756 // FIXME: Is this really right? 6757 return ""; 6758 } 6759 BuiltinVaListKind getBuiltinVaListKind() const override { 6760 return TargetInfo::SystemZBuiltinVaList; 6761 } 6762 bool setCPU(const std::string &Name) override { 6763 CPU = Name; 6764 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6765 .Case("z10", true) 6766 .Case("z196", true) 6767 .Case("zEC12", true) 6768 .Case("z13", true) 6769 .Default(false); 6770 6771 return CPUKnown; 6772 } 6773 bool 6774 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6775 StringRef CPU, 6776 const std::vector<std::string> &FeaturesVec) const override { 6777 if (CPU == "zEC12") 6778 Features["transactional-execution"] = true; 6779 if (CPU == "z13") { 6780 Features["transactional-execution"] = true; 6781 Features["vector"] = true; 6782 } 6783 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6784 } 6785 6786 bool handleTargetFeatures(std::vector<std::string> &Features, 6787 DiagnosticsEngine &Diags) override { 6788 HasTransactionalExecution = false; 6789 for (const auto &Feature : Features) { 6790 if (Feature == "+transactional-execution") 6791 HasTransactionalExecution = true; 6792 else if (Feature == "+vector") 6793 HasVector = true; 6794 } 6795 // If we use the vector ABI, vector types are 64-bit aligned. 6796 if (HasVector) { 6797 MaxVectorAlign = 64; 6798 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6799 "-v128:64-a:8:16-n32:64"); 6800 } 6801 return true; 6802 } 6803 6804 bool hasFeature(StringRef Feature) const override { 6805 return llvm::StringSwitch<bool>(Feature) 6806 .Case("systemz", true) 6807 .Case("htm", HasTransactionalExecution) 6808 .Case("vx", HasVector) 6809 .Default(false); 6810 } 6811 6812 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6813 switch (CC) { 6814 case CC_C: 6815 case CC_Swift: 6816 return CCCR_OK; 6817 default: 6818 return CCCR_Warning; 6819 } 6820 } 6821 6822 StringRef getABI() const override { 6823 if (HasVector) 6824 return "vector"; 6825 return ""; 6826 } 6827 6828 bool useFloat128ManglingForLongDouble() const override { 6829 return true; 6830 } 6831 }; 6832 6833 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6834 #define BUILTIN(ID, TYPE, ATTRS) \ 6835 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6836 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6837 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6838 #include "clang/Basic/BuiltinsSystemZ.def" 6839 }; 6840 6841 const char *const SystemZTargetInfo::GCCRegNames[] = { 6842 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6843 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6844 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6845 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6846 }; 6847 6848 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6849 return llvm::makeArrayRef(GCCRegNames); 6850 } 6851 6852 bool SystemZTargetInfo:: 6853 validateAsmConstraint(const char *&Name, 6854 TargetInfo::ConstraintInfo &Info) const { 6855 switch (*Name) { 6856 default: 6857 return false; 6858 6859 case 'a': // Address register 6860 case 'd': // Data register (equivalent to 'r') 6861 case 'f': // Floating-point register 6862 Info.setAllowsRegister(); 6863 return true; 6864 6865 case 'I': // Unsigned 8-bit constant 6866 case 'J': // Unsigned 12-bit constant 6867 case 'K': // Signed 16-bit constant 6868 case 'L': // Signed 20-bit displacement (on all targets we support) 6869 case 'M': // 0x7fffffff 6870 return true; 6871 6872 case 'Q': // Memory with base and unsigned 12-bit displacement 6873 case 'R': // Likewise, plus an index 6874 case 'S': // Memory with base and signed 20-bit displacement 6875 case 'T': // Likewise, plus an index 6876 Info.setAllowsMemory(); 6877 return true; 6878 } 6879 } 6880 6881 class MSP430TargetInfo : public TargetInfo { 6882 static const char *const GCCRegNames[]; 6883 6884 public: 6885 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6886 : TargetInfo(Triple) { 6887 BigEndian = false; 6888 TLSSupported = false; 6889 IntWidth = 16; 6890 IntAlign = 16; 6891 LongWidth = 32; 6892 LongLongWidth = 64; 6893 LongAlign = LongLongAlign = 16; 6894 PointerWidth = 16; 6895 PointerAlign = 16; 6896 SuitableAlign = 16; 6897 SizeType = UnsignedInt; 6898 IntMaxType = SignedLongLong; 6899 IntPtrType = SignedInt; 6900 PtrDiffType = SignedInt; 6901 SigAtomicType = SignedLong; 6902 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6903 } 6904 void getTargetDefines(const LangOptions &Opts, 6905 MacroBuilder &Builder) const override { 6906 Builder.defineMacro("MSP430"); 6907 Builder.defineMacro("__MSP430__"); 6908 // FIXME: defines for different 'flavours' of MCU 6909 } 6910 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6911 // FIXME: Implement. 6912 return None; 6913 } 6914 bool hasFeature(StringRef Feature) const override { 6915 return Feature == "msp430"; 6916 } 6917 ArrayRef<const char *> getGCCRegNames() const override; 6918 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6919 // No aliases. 6920 return None; 6921 } 6922 bool validateAsmConstraint(const char *&Name, 6923 TargetInfo::ConstraintInfo &info) const override { 6924 // FIXME: implement 6925 switch (*Name) { 6926 case 'K': // the constant 1 6927 case 'L': // constant -1^20 .. 1^19 6928 case 'M': // constant 1-4: 6929 return true; 6930 } 6931 // No target constraints for now. 6932 return false; 6933 } 6934 const char *getClobbers() const override { 6935 // FIXME: Is this really right? 6936 return ""; 6937 } 6938 BuiltinVaListKind getBuiltinVaListKind() const override { 6939 // FIXME: implement 6940 return TargetInfo::CharPtrBuiltinVaList; 6941 } 6942 }; 6943 6944 const char *const MSP430TargetInfo::GCCRegNames[] = { 6945 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6946 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6947 6948 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6949 return llvm::makeArrayRef(GCCRegNames); 6950 } 6951 6952 // LLVM and Clang cannot be used directly to output native binaries for 6953 // target, but is used to compile C code to llvm bitcode with correct 6954 // type and alignment information. 6955 // 6956 // TCE uses the llvm bitcode as input and uses it for generating customized 6957 // target processor and program binary. TCE co-design environment is 6958 // publicly available in http://tce.cs.tut.fi 6959 6960 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6961 3, // opencl_global 6962 4, // opencl_local 6963 5, // opencl_constant 6964 // FIXME: generic has to be added to the target 6965 0, // opencl_generic 6966 0, // cuda_device 6967 0, // cuda_constant 6968 0 // cuda_shared 6969 }; 6970 6971 class TCETargetInfo : public TargetInfo { 6972 public: 6973 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6974 : TargetInfo(Triple) { 6975 TLSSupported = false; 6976 IntWidth = 32; 6977 LongWidth = LongLongWidth = 32; 6978 PointerWidth = 32; 6979 IntAlign = 32; 6980 LongAlign = LongLongAlign = 32; 6981 PointerAlign = 32; 6982 SuitableAlign = 32; 6983 SizeType = UnsignedInt; 6984 IntMaxType = SignedLong; 6985 IntPtrType = SignedInt; 6986 PtrDiffType = SignedInt; 6987 FloatWidth = 32; 6988 FloatAlign = 32; 6989 DoubleWidth = 32; 6990 DoubleAlign = 32; 6991 LongDoubleWidth = 32; 6992 LongDoubleAlign = 32; 6993 FloatFormat = &llvm::APFloat::IEEEsingle; 6994 DoubleFormat = &llvm::APFloat::IEEEsingle; 6995 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6996 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6997 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6998 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6999 UseAddrSpaceMapMangling = true; 7000 } 7001 7002 void getTargetDefines(const LangOptions &Opts, 7003 MacroBuilder &Builder) const override { 7004 DefineStd(Builder, "tce", Opts); 7005 Builder.defineMacro("__TCE__"); 7006 Builder.defineMacro("__TCE_V1__"); 7007 } 7008 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7009 7010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7011 const char *getClobbers() const override { return ""; } 7012 BuiltinVaListKind getBuiltinVaListKind() const override { 7013 return TargetInfo::VoidPtrBuiltinVaList; 7014 } 7015 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7016 bool validateAsmConstraint(const char *&Name, 7017 TargetInfo::ConstraintInfo &info) const override { 7018 return true; 7019 } 7020 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7021 return None; 7022 } 7023 }; 7024 7025 class BPFTargetInfo : public TargetInfo { 7026 public: 7027 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7028 : TargetInfo(Triple) { 7029 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7030 SizeType = UnsignedLong; 7031 PtrDiffType = SignedLong; 7032 IntPtrType = SignedLong; 7033 IntMaxType = SignedLong; 7034 Int64Type = SignedLong; 7035 RegParmMax = 5; 7036 if (Triple.getArch() == llvm::Triple::bpfeb) { 7037 BigEndian = true; 7038 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7039 } else { 7040 BigEndian = false; 7041 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7042 } 7043 MaxAtomicPromoteWidth = 64; 7044 MaxAtomicInlineWidth = 64; 7045 TLSSupported = false; 7046 } 7047 void getTargetDefines(const LangOptions &Opts, 7048 MacroBuilder &Builder) const override { 7049 DefineStd(Builder, "bpf", Opts); 7050 Builder.defineMacro("__BPF__"); 7051 } 7052 bool hasFeature(StringRef Feature) const override { 7053 return Feature == "bpf"; 7054 } 7055 7056 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7057 const char *getClobbers() const override { 7058 return ""; 7059 } 7060 BuiltinVaListKind getBuiltinVaListKind() const override { 7061 return TargetInfo::VoidPtrBuiltinVaList; 7062 } 7063 ArrayRef<const char *> getGCCRegNames() const override { 7064 return None; 7065 } 7066 bool validateAsmConstraint(const char *&Name, 7067 TargetInfo::ConstraintInfo &info) const override { 7068 return true; 7069 } 7070 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7071 return None; 7072 } 7073 }; 7074 7075 class MipsTargetInfo : public TargetInfo { 7076 void setDataLayout() { 7077 StringRef Layout; 7078 7079 if (ABI == "o32") 7080 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7081 else if (ABI == "n32") 7082 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7083 else if (ABI == "n64") 7084 Layout = "m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7085 else 7086 llvm_unreachable("Invalid ABI"); 7087 7088 if (BigEndian) 7089 resetDataLayout(("E-" + Layout).str()); 7090 else 7091 resetDataLayout(("e-" + Layout).str()); 7092 } 7093 7094 7095 static const Builtin::Info BuiltinInfo[]; 7096 std::string CPU; 7097 bool IsMips16; 7098 bool IsMicromips; 7099 bool IsNan2008; 7100 bool IsSingleFloat; 7101 enum MipsFloatABI { 7102 HardFloat, SoftFloat 7103 } FloatABI; 7104 enum DspRevEnum { 7105 NoDSP, DSP1, DSP2 7106 } DspRev; 7107 bool HasMSA; 7108 7109 protected: 7110 bool HasFP64; 7111 std::string ABI; 7112 7113 public: 7114 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7115 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7116 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7117 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7118 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7119 BigEndian = getTriple().getArch() == llvm::Triple::mips || 7120 getTriple().getArch() == llvm::Triple::mips64; 7121 7122 setABI((getTriple().getArch() == llvm::Triple::mips || 7123 getTriple().getArch() == llvm::Triple::mipsel) 7124 ? "o32" 7125 : "n64"); 7126 7127 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7128 } 7129 7130 bool isNaN2008Default() const { 7131 return CPU == "mips32r6" || CPU == "mips64r6"; 7132 } 7133 7134 bool isFP64Default() const { 7135 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7136 } 7137 7138 bool isNan2008() const override { 7139 return IsNan2008; 7140 } 7141 7142 bool processorSupportsGPR64() const { 7143 return llvm::StringSwitch<bool>(CPU) 7144 .Case("mips3", true) 7145 .Case("mips4", true) 7146 .Case("mips5", true) 7147 .Case("mips64", true) 7148 .Case("mips64r2", true) 7149 .Case("mips64r3", true) 7150 .Case("mips64r5", true) 7151 .Case("mips64r6", true) 7152 .Case("octeon", true) 7153 .Default(false); 7154 return false; 7155 } 7156 7157 StringRef getABI() const override { return ABI; } 7158 bool setABI(const std::string &Name) override { 7159 if (Name == "o32") { 7160 setO32ABITypes(); 7161 ABI = Name; 7162 return true; 7163 } 7164 7165 if (Name == "n32") { 7166 setN32ABITypes(); 7167 ABI = Name; 7168 return true; 7169 } 7170 if (Name == "n64") { 7171 setN64ABITypes(); 7172 ABI = Name; 7173 return true; 7174 } 7175 return false; 7176 } 7177 7178 void setO32ABITypes() { 7179 Int64Type = SignedLongLong; 7180 IntMaxType = Int64Type; 7181 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7182 LongDoubleWidth = LongDoubleAlign = 64; 7183 LongWidth = LongAlign = 32; 7184 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7185 PointerWidth = PointerAlign = 32; 7186 PtrDiffType = SignedInt; 7187 SizeType = UnsignedInt; 7188 SuitableAlign = 64; 7189 } 7190 7191 void setN32N64ABITypes() { 7192 LongDoubleWidth = LongDoubleAlign = 128; 7193 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7194 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7195 LongDoubleWidth = LongDoubleAlign = 64; 7196 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7197 } 7198 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7199 SuitableAlign = 128; 7200 } 7201 7202 void setN64ABITypes() { 7203 setN32N64ABITypes(); 7204 Int64Type = SignedLong; 7205 IntMaxType = Int64Type; 7206 LongWidth = LongAlign = 64; 7207 PointerWidth = PointerAlign = 64; 7208 PtrDiffType = SignedLong; 7209 SizeType = UnsignedLong; 7210 } 7211 7212 void setN32ABITypes() { 7213 setN32N64ABITypes(); 7214 Int64Type = SignedLongLong; 7215 IntMaxType = Int64Type; 7216 LongWidth = LongAlign = 32; 7217 PointerWidth = PointerAlign = 32; 7218 PtrDiffType = SignedInt; 7219 SizeType = UnsignedInt; 7220 } 7221 7222 bool setCPU(const std::string &Name) override { 7223 CPU = Name; 7224 return llvm::StringSwitch<bool>(Name) 7225 .Case("mips1", true) 7226 .Case("mips2", true) 7227 .Case("mips3", true) 7228 .Case("mips4", true) 7229 .Case("mips5", true) 7230 .Case("mips32", true) 7231 .Case("mips32r2", true) 7232 .Case("mips32r3", true) 7233 .Case("mips32r5", true) 7234 .Case("mips32r6", true) 7235 .Case("mips64", true) 7236 .Case("mips64r2", true) 7237 .Case("mips64r3", true) 7238 .Case("mips64r5", true) 7239 .Case("mips64r6", true) 7240 .Case("octeon", true) 7241 .Case("p5600", true) 7242 .Default(false); 7243 } 7244 const std::string& getCPU() const { return CPU; } 7245 bool 7246 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7247 StringRef CPU, 7248 const std::vector<std::string> &FeaturesVec) const override { 7249 if (CPU.empty()) 7250 CPU = getCPU(); 7251 if (CPU == "octeon") 7252 Features["mips64r2"] = Features["cnmips"] = true; 7253 else 7254 Features[CPU] = true; 7255 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7256 } 7257 7258 void getTargetDefines(const LangOptions &Opts, 7259 MacroBuilder &Builder) const override { 7260 if (BigEndian) { 7261 DefineStd(Builder, "MIPSEB", Opts); 7262 Builder.defineMacro("_MIPSEB"); 7263 } else { 7264 DefineStd(Builder, "MIPSEL", Opts); 7265 Builder.defineMacro("_MIPSEL"); 7266 } 7267 7268 Builder.defineMacro("__mips__"); 7269 Builder.defineMacro("_mips"); 7270 if (Opts.GNUMode) 7271 Builder.defineMacro("mips"); 7272 7273 if (ABI == "o32") { 7274 Builder.defineMacro("__mips", "32"); 7275 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7276 } else { 7277 Builder.defineMacro("__mips", "64"); 7278 Builder.defineMacro("__mips64"); 7279 Builder.defineMacro("__mips64__"); 7280 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7281 } 7282 7283 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7284 .Cases("mips32", "mips64", "1") 7285 .Cases("mips32r2", "mips64r2", "2") 7286 .Cases("mips32r3", "mips64r3", "3") 7287 .Cases("mips32r5", "mips64r5", "5") 7288 .Cases("mips32r6", "mips64r6", "6") 7289 .Default(""); 7290 if (!ISARev.empty()) 7291 Builder.defineMacro("__mips_isa_rev", ISARev); 7292 7293 if (ABI == "o32") { 7294 Builder.defineMacro("__mips_o32"); 7295 Builder.defineMacro("_ABIO32", "1"); 7296 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7297 } else if (ABI == "n32") { 7298 Builder.defineMacro("__mips_n32"); 7299 Builder.defineMacro("_ABIN32", "2"); 7300 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7301 } else if (ABI == "n64") { 7302 Builder.defineMacro("__mips_n64"); 7303 Builder.defineMacro("_ABI64", "3"); 7304 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7305 } else 7306 llvm_unreachable("Invalid ABI."); 7307 7308 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7309 7310 switch (FloatABI) { 7311 case HardFloat: 7312 Builder.defineMacro("__mips_hard_float", Twine(1)); 7313 break; 7314 case SoftFloat: 7315 Builder.defineMacro("__mips_soft_float", Twine(1)); 7316 break; 7317 } 7318 7319 if (IsSingleFloat) 7320 Builder.defineMacro("__mips_single_float", Twine(1)); 7321 7322 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7323 Builder.defineMacro("_MIPS_FPSET", 7324 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7325 7326 if (IsMips16) 7327 Builder.defineMacro("__mips16", Twine(1)); 7328 7329 if (IsMicromips) 7330 Builder.defineMacro("__mips_micromips", Twine(1)); 7331 7332 if (IsNan2008) 7333 Builder.defineMacro("__mips_nan2008", Twine(1)); 7334 7335 switch (DspRev) { 7336 default: 7337 break; 7338 case DSP1: 7339 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7340 Builder.defineMacro("__mips_dsp", Twine(1)); 7341 break; 7342 case DSP2: 7343 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7344 Builder.defineMacro("__mips_dspr2", Twine(1)); 7345 Builder.defineMacro("__mips_dsp", Twine(1)); 7346 break; 7347 } 7348 7349 if (HasMSA) 7350 Builder.defineMacro("__mips_msa", Twine(1)); 7351 7352 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7353 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7354 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7355 7356 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7357 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7358 7359 // These shouldn't be defined for MIPS-I but there's no need to check 7360 // for that since MIPS-I isn't supported. 7361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7362 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7363 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7364 7365 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7366 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7367 // the instructions exist but using them violates the ABI since they 7368 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7369 if (ABI == "n32" || ABI == "n64") 7370 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7371 } 7372 7373 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7374 return llvm::makeArrayRef(BuiltinInfo, 7375 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7376 } 7377 bool hasFeature(StringRef Feature) const override { 7378 return llvm::StringSwitch<bool>(Feature) 7379 .Case("mips", true) 7380 .Case("fp64", HasFP64) 7381 .Default(false); 7382 } 7383 BuiltinVaListKind getBuiltinVaListKind() const override { 7384 return TargetInfo::VoidPtrBuiltinVaList; 7385 } 7386 ArrayRef<const char *> getGCCRegNames() const override { 7387 static const char *const GCCRegNames[] = { 7388 // CPU register names 7389 // Must match second column of GCCRegAliases 7390 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7391 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7392 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7393 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7394 // Floating point register names 7395 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7396 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7397 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7398 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7399 // Hi/lo and condition register names 7400 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7401 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7402 "$ac3hi","$ac3lo", 7403 // MSA register names 7404 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7405 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7406 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7407 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7408 // MSA control register names 7409 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7410 "$msarequest", "$msamap", "$msaunmap" 7411 }; 7412 return llvm::makeArrayRef(GCCRegNames); 7413 } 7414 bool validateAsmConstraint(const char *&Name, 7415 TargetInfo::ConstraintInfo &Info) const override { 7416 switch (*Name) { 7417 default: 7418 return false; 7419 case 'r': // CPU registers. 7420 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7421 case 'y': // Equivalent to "r", backward compatibility only. 7422 case 'f': // floating-point registers. 7423 case 'c': // $25 for indirect jumps 7424 case 'l': // lo register 7425 case 'x': // hilo register pair 7426 Info.setAllowsRegister(); 7427 return true; 7428 case 'I': // Signed 16-bit constant 7429 case 'J': // Integer 0 7430 case 'K': // Unsigned 16-bit constant 7431 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7432 case 'M': // Constants not loadable via lui, addiu, or ori 7433 case 'N': // Constant -1 to -65535 7434 case 'O': // A signed 15-bit constant 7435 case 'P': // A constant between 1 go 65535 7436 return true; 7437 case 'R': // An address that can be used in a non-macro load or store 7438 Info.setAllowsMemory(); 7439 return true; 7440 case 'Z': 7441 if (Name[1] == 'C') { // An address usable by ll, and sc. 7442 Info.setAllowsMemory(); 7443 Name++; // Skip over 'Z'. 7444 return true; 7445 } 7446 return false; 7447 } 7448 } 7449 7450 std::string convertConstraint(const char *&Constraint) const override { 7451 std::string R; 7452 switch (*Constraint) { 7453 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7454 if (Constraint[1] == 'C') { 7455 R = std::string("^") + std::string(Constraint, 2); 7456 Constraint++; 7457 return R; 7458 } 7459 break; 7460 } 7461 return TargetInfo::convertConstraint(Constraint); 7462 } 7463 7464 const char *getClobbers() const override { 7465 // In GCC, $1 is not widely used in generated code (it's used only in a few 7466 // specific situations), so there is no real need for users to add it to 7467 // the clobbers list if they want to use it in their inline assembly code. 7468 // 7469 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7470 // code generation, so using it in inline assembly without adding it to the 7471 // clobbers list can cause conflicts between the inline assembly code and 7472 // the surrounding generated code. 7473 // 7474 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7475 // operands, which will conflict with the ".set at" assembler option (which 7476 // we use only for inline assembly, in order to maintain compatibility with 7477 // GCC) and will also conflict with the user's usage of $1. 7478 // 7479 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7480 // register for generated code is to automatically clobber $1 for all inline 7481 // assembly code. 7482 // 7483 // FIXME: We should automatically clobber $1 only for inline assembly code 7484 // which actually uses it. This would allow LLVM to use $1 for inline 7485 // assembly operands if the user's assembly code doesn't use it. 7486 return "~{$1}"; 7487 } 7488 7489 bool handleTargetFeatures(std::vector<std::string> &Features, 7490 DiagnosticsEngine &Diags) override { 7491 IsMips16 = false; 7492 IsMicromips = false; 7493 IsNan2008 = isNaN2008Default(); 7494 IsSingleFloat = false; 7495 FloatABI = HardFloat; 7496 DspRev = NoDSP; 7497 HasFP64 = isFP64Default(); 7498 7499 for (const auto &Feature : Features) { 7500 if (Feature == "+single-float") 7501 IsSingleFloat = true; 7502 else if (Feature == "+soft-float") 7503 FloatABI = SoftFloat; 7504 else if (Feature == "+mips16") 7505 IsMips16 = true; 7506 else if (Feature == "+micromips") 7507 IsMicromips = true; 7508 else if (Feature == "+dsp") 7509 DspRev = std::max(DspRev, DSP1); 7510 else if (Feature == "+dspr2") 7511 DspRev = std::max(DspRev, DSP2); 7512 else if (Feature == "+msa") 7513 HasMSA = true; 7514 else if (Feature == "+fp64") 7515 HasFP64 = true; 7516 else if (Feature == "-fp64") 7517 HasFP64 = false; 7518 else if (Feature == "+nan2008") 7519 IsNan2008 = true; 7520 else if (Feature == "-nan2008") 7521 IsNan2008 = false; 7522 } 7523 7524 setDataLayout(); 7525 7526 return true; 7527 } 7528 7529 int getEHDataRegisterNumber(unsigned RegNo) const override { 7530 if (RegNo == 0) return 4; 7531 if (RegNo == 1) return 5; 7532 return -1; 7533 } 7534 7535 bool isCLZForZeroUndef() const override { return false; } 7536 7537 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7538 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7539 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7540 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7541 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7542 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7543 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7544 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7545 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7546 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7547 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7548 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7549 {{"ra"}, "$31"}}; 7550 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7551 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7552 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7553 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7554 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7555 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7556 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7557 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7558 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7559 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7560 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7561 {{"ra"}, "$31"}}; 7562 if (ABI == "o32") 7563 return llvm::makeArrayRef(O32RegAliases); 7564 return llvm::makeArrayRef(NewABIRegAliases); 7565 } 7566 7567 bool hasInt128Type() const override { 7568 return ABI == "n32" || ABI == "n64"; 7569 } 7570 7571 bool validateTarget(DiagnosticsEngine &Diags) const override { 7572 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7573 // this yet. It's better to fail here than on the backend assertion. 7574 if (processorSupportsGPR64() && ABI == "o32") { 7575 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7576 return false; 7577 } 7578 7579 // 64-bit ABI's require 64-bit CPU's. 7580 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7581 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7582 return false; 7583 } 7584 7585 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7586 // can't handle this yet. It's better to fail here than on the 7587 // backend assertion. 7588 if ((getTriple().getArch() == llvm::Triple::mips64 || 7589 getTriple().getArch() == llvm::Triple::mips64el) && 7590 ABI == "o32") { 7591 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7592 << ABI << getTriple().str(); 7593 return false; 7594 } 7595 7596 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7597 // can't handle this yet. It's better to fail here than on the 7598 // backend assertion. 7599 if ((getTriple().getArch() == llvm::Triple::mips || 7600 getTriple().getArch() == llvm::Triple::mipsel) && 7601 (ABI == "n32" || ABI == "n64")) { 7602 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7603 << ABI << getTriple().str(); 7604 return false; 7605 } 7606 7607 return true; 7608 } 7609 }; 7610 7611 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7612 #define BUILTIN(ID, TYPE, ATTRS) \ 7613 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7614 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7615 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7616 #include "clang/Basic/BuiltinsMips.def" 7617 }; 7618 7619 class PNaClTargetInfo : public TargetInfo { 7620 public: 7621 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7622 : TargetInfo(Triple) { 7623 BigEndian = false; 7624 this->LongAlign = 32; 7625 this->LongWidth = 32; 7626 this->PointerAlign = 32; 7627 this->PointerWidth = 32; 7628 this->IntMaxType = TargetInfo::SignedLongLong; 7629 this->Int64Type = TargetInfo::SignedLongLong; 7630 this->DoubleAlign = 64; 7631 this->LongDoubleWidth = 64; 7632 this->LongDoubleAlign = 64; 7633 this->SizeType = TargetInfo::UnsignedInt; 7634 this->PtrDiffType = TargetInfo::SignedInt; 7635 this->IntPtrType = TargetInfo::SignedInt; 7636 this->RegParmMax = 0; // Disallow regparm 7637 } 7638 7639 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7640 Builder.defineMacro("__le32__"); 7641 Builder.defineMacro("__pnacl__"); 7642 } 7643 void getTargetDefines(const LangOptions &Opts, 7644 MacroBuilder &Builder) const override { 7645 getArchDefines(Opts, Builder); 7646 } 7647 bool hasFeature(StringRef Feature) const override { 7648 return Feature == "pnacl"; 7649 } 7650 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7651 BuiltinVaListKind getBuiltinVaListKind() const override { 7652 return TargetInfo::PNaClABIBuiltinVaList; 7653 } 7654 ArrayRef<const char *> getGCCRegNames() const override; 7655 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7656 bool validateAsmConstraint(const char *&Name, 7657 TargetInfo::ConstraintInfo &Info) const override { 7658 return false; 7659 } 7660 7661 const char *getClobbers() const override { 7662 return ""; 7663 } 7664 }; 7665 7666 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7667 return None; 7668 } 7669 7670 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7671 return None; 7672 } 7673 7674 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7675 class NaClMips32TargetInfo : public MipsTargetInfo { 7676 public: 7677 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7678 : MipsTargetInfo(Triple, Opts) {} 7679 7680 BuiltinVaListKind getBuiltinVaListKind() const override { 7681 return TargetInfo::PNaClABIBuiltinVaList; 7682 } 7683 }; 7684 7685 class Le64TargetInfo : public TargetInfo { 7686 static const Builtin::Info BuiltinInfo[]; 7687 7688 public: 7689 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7690 : TargetInfo(Triple) { 7691 BigEndian = false; 7692 NoAsmVariants = true; 7693 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7694 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7695 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7696 } 7697 7698 void getTargetDefines(const LangOptions &Opts, 7699 MacroBuilder &Builder) const override { 7700 DefineStd(Builder, "unix", Opts); 7701 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7702 Builder.defineMacro("__ELF__"); 7703 } 7704 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7705 return llvm::makeArrayRef(BuiltinInfo, 7706 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7707 } 7708 BuiltinVaListKind getBuiltinVaListKind() const override { 7709 return TargetInfo::PNaClABIBuiltinVaList; 7710 } 7711 const char *getClobbers() const override { return ""; } 7712 ArrayRef<const char *> getGCCRegNames() const override { 7713 return None; 7714 } 7715 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7716 return None; 7717 } 7718 bool validateAsmConstraint(const char *&Name, 7719 TargetInfo::ConstraintInfo &Info) const override { 7720 return false; 7721 } 7722 7723 bool hasProtectedVisibility() const override { return false; } 7724 }; 7725 7726 class WebAssemblyTargetInfo : public TargetInfo { 7727 static const Builtin::Info BuiltinInfo[]; 7728 7729 enum SIMDEnum { 7730 NoSIMD, 7731 SIMD128, 7732 } SIMDLevel; 7733 7734 public: 7735 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7736 : TargetInfo(T), SIMDLevel(NoSIMD) { 7737 BigEndian = false; 7738 NoAsmVariants = true; 7739 SuitableAlign = 128; 7740 LargeArrayMinWidth = 128; 7741 LargeArrayAlign = 128; 7742 SimdDefaultAlign = 128; 7743 SigAtomicType = SignedLong; 7744 LongDoubleWidth = LongDoubleAlign = 128; 7745 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7746 } 7747 7748 protected: 7749 void getTargetDefines(const LangOptions &Opts, 7750 MacroBuilder &Builder) const override { 7751 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7752 if (SIMDLevel >= SIMD128) 7753 Builder.defineMacro("__wasm_simd128__"); 7754 } 7755 7756 private: 7757 bool 7758 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7759 StringRef CPU, 7760 const std::vector<std::string> &FeaturesVec) const override { 7761 if (CPU == "bleeding-edge") 7762 Features["simd128"] = true; 7763 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7764 } 7765 bool hasFeature(StringRef Feature) const final { 7766 return llvm::StringSwitch<bool>(Feature) 7767 .Case("simd128", SIMDLevel >= SIMD128) 7768 .Default(false); 7769 } 7770 bool handleTargetFeatures(std::vector<std::string> &Features, 7771 DiagnosticsEngine &Diags) final { 7772 for (const auto &Feature : Features) { 7773 if (Feature == "+simd128") { 7774 SIMDLevel = std::max(SIMDLevel, SIMD128); 7775 continue; 7776 } 7777 if (Feature == "-simd128") { 7778 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7779 continue; 7780 } 7781 7782 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7783 << "-target-feature"; 7784 return false; 7785 } 7786 return true; 7787 } 7788 bool setCPU(const std::string &Name) final { 7789 return llvm::StringSwitch<bool>(Name) 7790 .Case("mvp", true) 7791 .Case("bleeding-edge", true) 7792 .Case("generic", true) 7793 .Default(false); 7794 } 7795 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7796 return llvm::makeArrayRef(BuiltinInfo, 7797 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7798 } 7799 BuiltinVaListKind getBuiltinVaListKind() const final { 7800 return VoidPtrBuiltinVaList; 7801 } 7802 ArrayRef<const char *> getGCCRegNames() const final { 7803 return None; 7804 } 7805 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7806 return None; 7807 } 7808 bool 7809 validateAsmConstraint(const char *&Name, 7810 TargetInfo::ConstraintInfo &Info) const final { 7811 return false; 7812 } 7813 const char *getClobbers() const final { return ""; } 7814 bool isCLZForZeroUndef() const final { return false; } 7815 bool hasInt128Type() const final { return true; } 7816 IntType getIntTypeByWidth(unsigned BitWidth, 7817 bool IsSigned) const final { 7818 // WebAssembly prefers long long for explicitly 64-bit integers. 7819 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7820 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7821 } 7822 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7823 bool IsSigned) const final { 7824 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7825 return BitWidth == 64 7826 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7827 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7828 } 7829 }; 7830 7831 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7832 #define BUILTIN(ID, TYPE, ATTRS) \ 7833 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7834 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7835 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7836 #include "clang/Basic/BuiltinsWebAssembly.def" 7837 }; 7838 7839 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7840 public: 7841 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7842 const TargetOptions &Opts) 7843 : WebAssemblyTargetInfo(T, Opts) { 7844 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7845 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7846 } 7847 7848 protected: 7849 void getTargetDefines(const LangOptions &Opts, 7850 MacroBuilder &Builder) const override { 7851 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7852 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7853 } 7854 }; 7855 7856 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7857 public: 7858 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7859 const TargetOptions &Opts) 7860 : WebAssemblyTargetInfo(T, Opts) { 7861 LongAlign = LongWidth = 64; 7862 PointerAlign = PointerWidth = 64; 7863 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7864 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7865 } 7866 7867 protected: 7868 void getTargetDefines(const LangOptions &Opts, 7869 MacroBuilder &Builder) const override { 7870 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7871 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7872 } 7873 }; 7874 7875 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7876 #define BUILTIN(ID, TYPE, ATTRS) \ 7877 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7878 #include "clang/Basic/BuiltinsLe64.def" 7879 }; 7880 7881 static const unsigned SPIRAddrSpaceMap[] = { 7882 1, // opencl_global 7883 3, // opencl_local 7884 2, // opencl_constant 7885 4, // opencl_generic 7886 0, // cuda_device 7887 0, // cuda_constant 7888 0 // cuda_shared 7889 }; 7890 class SPIRTargetInfo : public TargetInfo { 7891 public: 7892 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7893 : TargetInfo(Triple) { 7894 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7895 "SPIR target must use unknown OS"); 7896 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7897 "SPIR target must use unknown environment type"); 7898 BigEndian = false; 7899 TLSSupported = false; 7900 LongWidth = LongAlign = 64; 7901 AddrSpaceMap = &SPIRAddrSpaceMap; 7902 UseAddrSpaceMapMangling = true; 7903 // Define available target features 7904 // These must be defined in sorted order! 7905 NoAsmVariants = true; 7906 } 7907 void getTargetDefines(const LangOptions &Opts, 7908 MacroBuilder &Builder) const override { 7909 DefineStd(Builder, "SPIR", Opts); 7910 } 7911 bool hasFeature(StringRef Feature) const override { 7912 return Feature == "spir"; 7913 } 7914 7915 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7916 const char *getClobbers() const override { return ""; } 7917 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7918 bool validateAsmConstraint(const char *&Name, 7919 TargetInfo::ConstraintInfo &info) const override { 7920 return true; 7921 } 7922 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7923 return None; 7924 } 7925 BuiltinVaListKind getBuiltinVaListKind() const override { 7926 return TargetInfo::VoidPtrBuiltinVaList; 7927 } 7928 7929 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7930 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7931 : CCCR_Warning; 7932 } 7933 7934 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7935 return CC_SpirFunction; 7936 } 7937 7938 void setSupportedOpenCLOpts() override { 7939 // Assume all OpenCL extensions and optional core features are supported 7940 // for SPIR since it is a generic target. 7941 getSupportedOpenCLOpts().setAll(); 7942 } 7943 }; 7944 7945 class SPIR32TargetInfo : public SPIRTargetInfo { 7946 public: 7947 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7948 : SPIRTargetInfo(Triple, Opts) { 7949 PointerWidth = PointerAlign = 32; 7950 SizeType = TargetInfo::UnsignedInt; 7951 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7952 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7953 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7954 } 7955 void getTargetDefines(const LangOptions &Opts, 7956 MacroBuilder &Builder) const override { 7957 DefineStd(Builder, "SPIR32", Opts); 7958 } 7959 }; 7960 7961 class SPIR64TargetInfo : public SPIRTargetInfo { 7962 public: 7963 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7964 : SPIRTargetInfo(Triple, Opts) { 7965 PointerWidth = PointerAlign = 64; 7966 SizeType = TargetInfo::UnsignedLong; 7967 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7968 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7969 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7970 } 7971 void getTargetDefines(const LangOptions &Opts, 7972 MacroBuilder &Builder) const override { 7973 DefineStd(Builder, "SPIR64", Opts); 7974 } 7975 }; 7976 7977 class XCoreTargetInfo : public TargetInfo { 7978 static const Builtin::Info BuiltinInfo[]; 7979 public: 7980 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7981 : TargetInfo(Triple) { 7982 BigEndian = false; 7983 NoAsmVariants = true; 7984 LongLongAlign = 32; 7985 SuitableAlign = 32; 7986 DoubleAlign = LongDoubleAlign = 32; 7987 SizeType = UnsignedInt; 7988 PtrDiffType = SignedInt; 7989 IntPtrType = SignedInt; 7990 WCharType = UnsignedChar; 7991 WIntType = UnsignedInt; 7992 UseZeroLengthBitfieldAlignment = true; 7993 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7994 "-f64:32-a:0:32-n32"); 7995 } 7996 void getTargetDefines(const LangOptions &Opts, 7997 MacroBuilder &Builder) const override { 7998 Builder.defineMacro("__XS1B__"); 7999 } 8000 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8001 return llvm::makeArrayRef(BuiltinInfo, 8002 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8003 } 8004 BuiltinVaListKind getBuiltinVaListKind() const override { 8005 return TargetInfo::VoidPtrBuiltinVaList; 8006 } 8007 const char *getClobbers() const override { 8008 return ""; 8009 } 8010 ArrayRef<const char *> getGCCRegNames() const override { 8011 static const char * const GCCRegNames[] = { 8012 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8013 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8014 }; 8015 return llvm::makeArrayRef(GCCRegNames); 8016 } 8017 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8018 return None; 8019 } 8020 bool validateAsmConstraint(const char *&Name, 8021 TargetInfo::ConstraintInfo &Info) const override { 8022 return false; 8023 } 8024 int getEHDataRegisterNumber(unsigned RegNo) const override { 8025 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8026 return (RegNo < 2)? RegNo : -1; 8027 } 8028 bool allowsLargerPreferedTypeAlignment() const override { 8029 return false; 8030 } 8031 }; 8032 8033 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8034 #define BUILTIN(ID, TYPE, ATTRS) \ 8035 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8036 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8037 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8038 #include "clang/Basic/BuiltinsXCore.def" 8039 }; 8040 8041 // x86_32 Android target 8042 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8043 public: 8044 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8045 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8046 SuitableAlign = 32; 8047 LongDoubleWidth = 64; 8048 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8049 } 8050 }; 8051 8052 // x86_64 Android target 8053 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8054 public: 8055 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8056 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8057 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8058 } 8059 8060 bool useFloat128ManglingForLongDouble() const override { 8061 return true; 8062 } 8063 }; 8064 } // end anonymous namespace 8065 8066 //===----------------------------------------------------------------------===// 8067 // Driver code 8068 //===----------------------------------------------------------------------===// 8069 8070 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8071 const TargetOptions &Opts) { 8072 llvm::Triple::OSType os = Triple.getOS(); 8073 8074 switch (Triple.getArch()) { 8075 default: 8076 return nullptr; 8077 8078 case llvm::Triple::xcore: 8079 return new XCoreTargetInfo(Triple, Opts); 8080 8081 case llvm::Triple::hexagon: 8082 return new HexagonTargetInfo(Triple, Opts); 8083 8084 case llvm::Triple::lanai: 8085 return new LanaiTargetInfo(Triple, Opts); 8086 8087 case llvm::Triple::aarch64: 8088 if (Triple.isOSDarwin()) 8089 return new DarwinAArch64TargetInfo(Triple, Opts); 8090 8091 switch (os) { 8092 case llvm::Triple::CloudABI: 8093 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8094 case llvm::Triple::FreeBSD: 8095 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8096 case llvm::Triple::Linux: 8097 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8098 case llvm::Triple::NetBSD: 8099 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8100 default: 8101 return new AArch64leTargetInfo(Triple, Opts); 8102 } 8103 8104 case llvm::Triple::aarch64_be: 8105 switch (os) { 8106 case llvm::Triple::FreeBSD: 8107 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8108 case llvm::Triple::Linux: 8109 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8110 case llvm::Triple::NetBSD: 8111 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8112 default: 8113 return new AArch64beTargetInfo(Triple, Opts); 8114 } 8115 8116 case llvm::Triple::arm: 8117 case llvm::Triple::thumb: 8118 if (Triple.isOSBinFormatMachO()) 8119 return new DarwinARMTargetInfo(Triple, Opts); 8120 8121 switch (os) { 8122 case llvm::Triple::Linux: 8123 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8124 case llvm::Triple::FreeBSD: 8125 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8126 case llvm::Triple::NetBSD: 8127 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8128 case llvm::Triple::OpenBSD: 8129 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8130 case llvm::Triple::Bitrig: 8131 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8132 case llvm::Triple::RTEMS: 8133 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8134 case llvm::Triple::NaCl: 8135 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8136 case llvm::Triple::Win32: 8137 switch (Triple.getEnvironment()) { 8138 case llvm::Triple::Cygnus: 8139 return new CygwinARMTargetInfo(Triple, Opts); 8140 case llvm::Triple::GNU: 8141 return new MinGWARMTargetInfo(Triple, Opts); 8142 case llvm::Triple::Itanium: 8143 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8144 case llvm::Triple::MSVC: 8145 default: // Assume MSVC for unknown environments 8146 return new MicrosoftARMleTargetInfo(Triple, Opts); 8147 } 8148 default: 8149 return new ARMleTargetInfo(Triple, Opts); 8150 } 8151 8152 case llvm::Triple::armeb: 8153 case llvm::Triple::thumbeb: 8154 if (Triple.isOSDarwin()) 8155 return new DarwinARMTargetInfo(Triple, Opts); 8156 8157 switch (os) { 8158 case llvm::Triple::Linux: 8159 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8160 case llvm::Triple::FreeBSD: 8161 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8162 case llvm::Triple::NetBSD: 8163 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8164 case llvm::Triple::OpenBSD: 8165 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8166 case llvm::Triple::Bitrig: 8167 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8168 case llvm::Triple::RTEMS: 8169 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8170 case llvm::Triple::NaCl: 8171 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8172 default: 8173 return new ARMbeTargetInfo(Triple, Opts); 8174 } 8175 8176 case llvm::Triple::bpfeb: 8177 case llvm::Triple::bpfel: 8178 return new BPFTargetInfo(Triple, Opts); 8179 8180 case llvm::Triple::msp430: 8181 return new MSP430TargetInfo(Triple, Opts); 8182 8183 case llvm::Triple::mips: 8184 switch (os) { 8185 case llvm::Triple::Linux: 8186 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8187 case llvm::Triple::RTEMS: 8188 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8189 case llvm::Triple::FreeBSD: 8190 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8191 case llvm::Triple::NetBSD: 8192 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8193 default: 8194 return new MipsTargetInfo(Triple, Opts); 8195 } 8196 8197 case llvm::Triple::mipsel: 8198 switch (os) { 8199 case llvm::Triple::Linux: 8200 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8201 case llvm::Triple::RTEMS: 8202 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8203 case llvm::Triple::FreeBSD: 8204 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8205 case llvm::Triple::NetBSD: 8206 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8207 case llvm::Triple::NaCl: 8208 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8209 default: 8210 return new MipsTargetInfo(Triple, Opts); 8211 } 8212 8213 case llvm::Triple::mips64: 8214 switch (os) { 8215 case llvm::Triple::Linux: 8216 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8217 case llvm::Triple::RTEMS: 8218 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8219 case llvm::Triple::FreeBSD: 8220 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8221 case llvm::Triple::NetBSD: 8222 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8223 case llvm::Triple::OpenBSD: 8224 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8225 default: 8226 return new MipsTargetInfo(Triple, Opts); 8227 } 8228 8229 case llvm::Triple::mips64el: 8230 switch (os) { 8231 case llvm::Triple::Linux: 8232 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8233 case llvm::Triple::RTEMS: 8234 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8235 case llvm::Triple::FreeBSD: 8236 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8237 case llvm::Triple::NetBSD: 8238 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8239 case llvm::Triple::OpenBSD: 8240 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8241 default: 8242 return new MipsTargetInfo(Triple, Opts); 8243 } 8244 8245 case llvm::Triple::le32: 8246 switch (os) { 8247 case llvm::Triple::NaCl: 8248 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8249 default: 8250 return nullptr; 8251 } 8252 8253 case llvm::Triple::le64: 8254 return new Le64TargetInfo(Triple, Opts); 8255 8256 case llvm::Triple::ppc: 8257 if (Triple.isOSDarwin()) 8258 return new DarwinPPC32TargetInfo(Triple, Opts); 8259 switch (os) { 8260 case llvm::Triple::Linux: 8261 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8262 case llvm::Triple::FreeBSD: 8263 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8264 case llvm::Triple::NetBSD: 8265 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8266 case llvm::Triple::OpenBSD: 8267 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8268 case llvm::Triple::RTEMS: 8269 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8270 default: 8271 return new PPC32TargetInfo(Triple, Opts); 8272 } 8273 8274 case llvm::Triple::ppc64: 8275 if (Triple.isOSDarwin()) 8276 return new DarwinPPC64TargetInfo(Triple, Opts); 8277 switch (os) { 8278 case llvm::Triple::Linux: 8279 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8280 case llvm::Triple::Lv2: 8281 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8282 case llvm::Triple::FreeBSD: 8283 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8284 case llvm::Triple::NetBSD: 8285 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8286 default: 8287 return new PPC64TargetInfo(Triple, Opts); 8288 } 8289 8290 case llvm::Triple::ppc64le: 8291 switch (os) { 8292 case llvm::Triple::Linux: 8293 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8294 case llvm::Triple::NetBSD: 8295 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8296 default: 8297 return new PPC64TargetInfo(Triple, Opts); 8298 } 8299 8300 case llvm::Triple::nvptx: 8301 return new NVPTX32TargetInfo(Triple, Opts); 8302 case llvm::Triple::nvptx64: 8303 return new NVPTX64TargetInfo(Triple, Opts); 8304 8305 case llvm::Triple::amdgcn: 8306 case llvm::Triple::r600: 8307 return new AMDGPUTargetInfo(Triple, Opts); 8308 8309 case llvm::Triple::sparc: 8310 switch (os) { 8311 case llvm::Triple::Linux: 8312 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8313 case llvm::Triple::Solaris: 8314 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8315 case llvm::Triple::NetBSD: 8316 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8317 case llvm::Triple::OpenBSD: 8318 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8319 case llvm::Triple::RTEMS: 8320 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8321 default: 8322 return new SparcV8TargetInfo(Triple, Opts); 8323 } 8324 8325 // The 'sparcel' architecture copies all the above cases except for Solaris. 8326 case llvm::Triple::sparcel: 8327 switch (os) { 8328 case llvm::Triple::Linux: 8329 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8330 case llvm::Triple::NetBSD: 8331 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8332 case llvm::Triple::OpenBSD: 8333 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8334 case llvm::Triple::RTEMS: 8335 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8336 default: 8337 return new SparcV8elTargetInfo(Triple, Opts); 8338 } 8339 8340 case llvm::Triple::sparcv9: 8341 switch (os) { 8342 case llvm::Triple::Linux: 8343 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8344 case llvm::Triple::Solaris: 8345 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8346 case llvm::Triple::NetBSD: 8347 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8348 case llvm::Triple::OpenBSD: 8349 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8350 case llvm::Triple::FreeBSD: 8351 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8352 default: 8353 return new SparcV9TargetInfo(Triple, Opts); 8354 } 8355 8356 case llvm::Triple::systemz: 8357 switch (os) { 8358 case llvm::Triple::Linux: 8359 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8360 default: 8361 return new SystemZTargetInfo(Triple, Opts); 8362 } 8363 8364 case llvm::Triple::tce: 8365 return new TCETargetInfo(Triple, Opts); 8366 8367 case llvm::Triple::x86: 8368 if (Triple.isOSDarwin()) 8369 return new DarwinI386TargetInfo(Triple, Opts); 8370 8371 switch (os) { 8372 case llvm::Triple::CloudABI: 8373 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8374 case llvm::Triple::Linux: { 8375 switch (Triple.getEnvironment()) { 8376 default: 8377 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8378 case llvm::Triple::Android: 8379 return new AndroidX86_32TargetInfo(Triple, Opts); 8380 } 8381 } 8382 case llvm::Triple::DragonFly: 8383 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8384 case llvm::Triple::NetBSD: 8385 return new NetBSDI386TargetInfo(Triple, Opts); 8386 case llvm::Triple::OpenBSD: 8387 return new OpenBSDI386TargetInfo(Triple, Opts); 8388 case llvm::Triple::Bitrig: 8389 return new BitrigI386TargetInfo(Triple, Opts); 8390 case llvm::Triple::FreeBSD: 8391 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8392 case llvm::Triple::KFreeBSD: 8393 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8394 case llvm::Triple::Minix: 8395 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8396 case llvm::Triple::Solaris: 8397 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8398 case llvm::Triple::Win32: { 8399 switch (Triple.getEnvironment()) { 8400 case llvm::Triple::Cygnus: 8401 return new CygwinX86_32TargetInfo(Triple, Opts); 8402 case llvm::Triple::GNU: 8403 return new MinGWX86_32TargetInfo(Triple, Opts); 8404 case llvm::Triple::Itanium: 8405 case llvm::Triple::MSVC: 8406 default: // Assume MSVC for unknown environments 8407 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8408 } 8409 } 8410 case llvm::Triple::Haiku: 8411 return new HaikuX86_32TargetInfo(Triple, Opts); 8412 case llvm::Triple::RTEMS: 8413 return new RTEMSX86_32TargetInfo(Triple, Opts); 8414 case llvm::Triple::NaCl: 8415 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8416 case llvm::Triple::ELFIAMCU: 8417 return new MCUX86_32TargetInfo(Triple, Opts); 8418 default: 8419 return new X86_32TargetInfo(Triple, Opts); 8420 } 8421 8422 case llvm::Triple::x86_64: 8423 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8424 return new DarwinX86_64TargetInfo(Triple, Opts); 8425 8426 switch (os) { 8427 case llvm::Triple::CloudABI: 8428 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8429 case llvm::Triple::Linux: { 8430 switch (Triple.getEnvironment()) { 8431 default: 8432 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8433 case llvm::Triple::Android: 8434 return new AndroidX86_64TargetInfo(Triple, Opts); 8435 } 8436 } 8437 case llvm::Triple::DragonFly: 8438 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8439 case llvm::Triple::NetBSD: 8440 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8441 case llvm::Triple::OpenBSD: 8442 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8443 case llvm::Triple::Bitrig: 8444 return new BitrigX86_64TargetInfo(Triple, Opts); 8445 case llvm::Triple::FreeBSD: 8446 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8447 case llvm::Triple::KFreeBSD: 8448 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8449 case llvm::Triple::Solaris: 8450 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8451 case llvm::Triple::Win32: { 8452 switch (Triple.getEnvironment()) { 8453 case llvm::Triple::Cygnus: 8454 return new CygwinX86_64TargetInfo(Triple, Opts); 8455 case llvm::Triple::GNU: 8456 return new MinGWX86_64TargetInfo(Triple, Opts); 8457 case llvm::Triple::MSVC: 8458 default: // Assume MSVC for unknown environments 8459 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8460 } 8461 } 8462 case llvm::Triple::Haiku: 8463 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8464 case llvm::Triple::NaCl: 8465 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8466 case llvm::Triple::PS4: 8467 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8468 default: 8469 return new X86_64TargetInfo(Triple, Opts); 8470 } 8471 8472 case llvm::Triple::spir: { 8473 if (Triple.getOS() != llvm::Triple::UnknownOS || 8474 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8475 return nullptr; 8476 return new SPIR32TargetInfo(Triple, Opts); 8477 } 8478 case llvm::Triple::spir64: { 8479 if (Triple.getOS() != llvm::Triple::UnknownOS || 8480 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8481 return nullptr; 8482 return new SPIR64TargetInfo(Triple, Opts); 8483 } 8484 case llvm::Triple::wasm32: 8485 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8486 return nullptr; 8487 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8488 case llvm::Triple::wasm64: 8489 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8490 return nullptr; 8491 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8492 } 8493 } 8494 8495 /// CreateTargetInfo - Return the target info object for the specified target 8496 /// options. 8497 TargetInfo * 8498 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8499 const std::shared_ptr<TargetOptions> &Opts) { 8500 llvm::Triple Triple(Opts->Triple); 8501 8502 // Construct the target 8503 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8504 if (!Target) { 8505 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8506 return nullptr; 8507 } 8508 Target->TargetOpts = Opts; 8509 8510 // Set the target CPU if specified. 8511 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8512 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8513 return nullptr; 8514 } 8515 8516 // Set the target ABI if specified. 8517 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8518 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8519 return nullptr; 8520 } 8521 8522 // Set the fp math unit. 8523 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8524 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8525 return nullptr; 8526 } 8527 8528 // Compute the default target features, we need the target to handle this 8529 // because features may have dependencies on one another. 8530 llvm::StringMap<bool> Features; 8531 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8532 Opts->FeaturesAsWritten)) 8533 return nullptr; 8534 8535 // Add the features to the compile options. 8536 Opts->Features.clear(); 8537 for (const auto &F : Features) 8538 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8539 8540 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8541 return nullptr; 8542 8543 Target->setSupportedOpenCLOpts(); 8544 8545 if (!Target->validateTarget(Diags)) 8546 return nullptr; 8547 8548 return Target.release(); 8549 } 8550