1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.has(SanitizerKind::Address)) 97 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 // CloudABI Target 188 template <typename Target> 189 class CloudABITargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 Builder.defineMacro("__CloudABI__"); 194 Builder.defineMacro("__ELF__"); 195 196 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 197 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 198 Builder.defineMacro("__STDC_UTF_16__"); 199 Builder.defineMacro("__STDC_UTF_32__"); 200 } 201 202 public: 203 CloudABITargetInfo(const llvm::Triple &Triple) 204 : OSTargetInfo<Target>(Triple) { 205 this->UserLabelPrefix = ""; 206 } 207 }; 208 209 template<typename Target> 210 class DarwinTargetInfo : public OSTargetInfo<Target> { 211 protected: 212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 213 MacroBuilder &Builder) const override { 214 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 215 this->PlatformMinVersion); 216 } 217 218 public: 219 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 220 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 221 this->MCountName = "\01mcount"; 222 } 223 224 std::string isValidSectionSpecifier(StringRef SR) const override { 225 // Let MCSectionMachO validate this. 226 StringRef Segment, Section; 227 unsigned TAA, StubSize; 228 bool HasTAA; 229 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 230 TAA, HasTAA, StubSize); 231 } 232 233 const char *getStaticInitSectionSpecifier() const override { 234 // FIXME: We should return 0 when building kexts. 235 return "__TEXT,__StaticInit,regular,pure_instructions"; 236 } 237 238 /// Darwin does not support protected visibility. Darwin's "default" 239 /// is very similar to ELF's "protected"; Darwin requires a "weak" 240 /// attribute on declarations that can be dynamically replaced. 241 bool hasProtectedVisibility() const override { 242 return false; 243 } 244 }; 245 246 247 // DragonFlyBSD Target 248 template<typename Target> 249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 250 protected: 251 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 252 MacroBuilder &Builder) const override { 253 // DragonFly defines; list based off of gcc output 254 Builder.defineMacro("__DragonFly__"); 255 Builder.defineMacro("__DragonFly_cc_version", "100001"); 256 Builder.defineMacro("__ELF__"); 257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 258 Builder.defineMacro("__tune_i386__"); 259 DefineStd(Builder, "unix", Opts); 260 } 261 public: 262 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 263 : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 } 273 } 274 }; 275 276 // FreeBSD Target 277 template<typename Target> 278 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 279 protected: 280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 281 MacroBuilder &Builder) const override { 282 // FreeBSD defines; list based off of gcc output 283 284 unsigned Release = Triple.getOSMajorVersion(); 285 if (Release == 0U) 286 Release = 8; 287 288 Builder.defineMacro("__FreeBSD__", Twine(Release)); 289 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 290 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 291 DefineStd(Builder, "unix", Opts); 292 Builder.defineMacro("__ELF__"); 293 294 // On FreeBSD, wchar_t contains the number of the code point as 295 // used by the character set of the locale. These character sets are 296 // not necessarily a superset of ASCII. 297 // 298 // FIXME: This is wrong; the macro refers to the numerical values 299 // of wchar_t *literals*, which are not locale-dependent. However, 300 // FreeBSD systems apparently depend on us getting this wrong, and 301 // setting this to 1 is conforming even if all the basic source 302 // character literals have the same encoding as char and wchar_t. 303 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 304 } 305 public: 306 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 307 this->UserLabelPrefix = ""; 308 309 switch (Triple.getArch()) { 310 default: 311 case llvm::Triple::x86: 312 case llvm::Triple::x86_64: 313 this->MCountName = ".mcount"; 314 break; 315 case llvm::Triple::mips: 316 case llvm::Triple::mipsel: 317 case llvm::Triple::ppc: 318 case llvm::Triple::ppc64: 319 case llvm::Triple::ppc64le: 320 this->MCountName = "_mcount"; 321 break; 322 case llvm::Triple::arm: 323 this->MCountName = "__mcount"; 324 break; 325 } 326 } 327 }; 328 329 // GNU/kFreeBSD Target 330 template<typename Target> 331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // GNU/kFreeBSD defines; list based off of gcc output 336 337 DefineStd(Builder, "unix", Opts); 338 Builder.defineMacro("__FreeBSD_kernel__"); 339 Builder.defineMacro("__GLIBC__"); 340 Builder.defineMacro("__ELF__"); 341 if (Opts.POSIXThreads) 342 Builder.defineMacro("_REENTRANT"); 343 if (Opts.CPlusPlus) 344 Builder.defineMacro("_GNU_SOURCE"); 345 } 346 public: 347 KFreeBSDTargetInfo(const llvm::Triple &Triple) 348 : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // Minix Target 354 template<typename Target> 355 class MinixTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const override { 359 // Minix defines 360 361 Builder.defineMacro("__minix", "3"); 362 Builder.defineMacro("_EM_WSIZE", "4"); 363 Builder.defineMacro("_EM_PSIZE", "4"); 364 Builder.defineMacro("_EM_SSIZE", "2"); 365 Builder.defineMacro("_EM_LSIZE", "4"); 366 Builder.defineMacro("_EM_FSIZE", "4"); 367 Builder.defineMacro("_EM_DSIZE", "8"); 368 Builder.defineMacro("__ELF__"); 369 DefineStd(Builder, "unix", Opts); 370 } 371 public: 372 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 373 this->UserLabelPrefix = ""; 374 } 375 }; 376 377 // Linux target 378 template<typename Target> 379 class LinuxTargetInfo : public OSTargetInfo<Target> { 380 protected: 381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 382 MacroBuilder &Builder) const override { 383 // Linux defines; list based off of gcc output 384 DefineStd(Builder, "unix", Opts); 385 DefineStd(Builder, "linux", Opts); 386 Builder.defineMacro("__gnu_linux__"); 387 Builder.defineMacro("__ELF__"); 388 if (Triple.getEnvironment() == llvm::Triple::Android) { 389 Builder.defineMacro("__ANDROID__", "1"); 390 unsigned Maj, Min, Rev; 391 Triple.getOSVersion(Maj, Min, Rev); 392 this->PlatformName = "android"; 393 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 394 } 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 402 this->UserLabelPrefix = ""; 403 this->WIntType = TargetInfo::UnsignedInt; 404 405 switch (Triple.getArch()) { 406 default: 407 break; 408 case llvm::Triple::ppc: 409 case llvm::Triple::ppc64: 410 case llvm::Triple::ppc64le: 411 this->MCountName = "_mcount"; 412 break; 413 } 414 } 415 416 const char *getStaticInitSectionSpecifier() const override { 417 return ".text.startup"; 418 } 419 }; 420 421 // NetBSD Target 422 template<typename Target> 423 class NetBSDTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // NetBSD defines; list based off of gcc output 428 Builder.defineMacro("__NetBSD__"); 429 Builder.defineMacro("__unix__"); 430 Builder.defineMacro("__ELF__"); 431 if (Opts.POSIXThreads) 432 Builder.defineMacro("_POSIX_THREADS"); 433 434 switch (Triple.getArch()) { 435 default: 436 break; 437 case llvm::Triple::arm: 438 case llvm::Triple::armeb: 439 case llvm::Triple::thumb: 440 case llvm::Triple::thumbeb: 441 Builder.defineMacro("__ARM_DWARF_EH__"); 442 break; 443 } 444 } 445 public: 446 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 } 449 }; 450 451 // OpenBSD Target 452 template<typename Target> 453 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // OpenBSD defines; list based off of gcc output 458 459 Builder.defineMacro("__OpenBSD__"); 460 DefineStd(Builder, "unix", Opts); 461 Builder.defineMacro("__ELF__"); 462 if (Opts.POSIXThreads) 463 Builder.defineMacro("_REENTRANT"); 464 } 465 public: 466 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 467 this->UserLabelPrefix = ""; 468 this->TLSSupported = false; 469 470 switch (Triple.getArch()) { 471 default: 472 case llvm::Triple::x86: 473 case llvm::Triple::x86_64: 474 case llvm::Triple::arm: 475 case llvm::Triple::sparc: 476 this->MCountName = "__mcount"; 477 break; 478 case llvm::Triple::mips64: 479 case llvm::Triple::mips64el: 480 case llvm::Triple::ppc: 481 case llvm::Triple::sparcv9: 482 this->MCountName = "_mcount"; 483 break; 484 } 485 } 486 }; 487 488 // Bitrig Target 489 template<typename Target> 490 class BitrigTargetInfo : public OSTargetInfo<Target> { 491 protected: 492 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 493 MacroBuilder &Builder) const override { 494 // Bitrig defines; list based off of gcc output 495 496 Builder.defineMacro("__Bitrig__"); 497 DefineStd(Builder, "unix", Opts); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_REENTRANT"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 515 this->UserLabelPrefix = ""; 516 this->MCountName = "__mcount"; 517 } 518 }; 519 520 // PSP Target 521 template<typename Target> 522 class PSPTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // PSP defines; list based on the output of the pspdev gcc toolchain. 527 Builder.defineMacro("PSP"); 528 Builder.defineMacro("_PSP"); 529 Builder.defineMacro("__psp__"); 530 Builder.defineMacro("__ELF__"); 531 } 532 public: 533 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 534 this->UserLabelPrefix = ""; 535 } 536 }; 537 538 // PS3 PPU Target 539 template<typename Target> 540 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 541 protected: 542 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 543 MacroBuilder &Builder) const override { 544 // PS3 PPU defines. 545 Builder.defineMacro("__PPC__"); 546 Builder.defineMacro("__PPU__"); 547 Builder.defineMacro("__CELLOS_LV2__"); 548 Builder.defineMacro("__ELF__"); 549 Builder.defineMacro("__LP32__"); 550 Builder.defineMacro("_ARCH_PPC64"); 551 Builder.defineMacro("__powerpc64__"); 552 } 553 public: 554 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 555 this->UserLabelPrefix = ""; 556 this->LongWidth = this->LongAlign = 32; 557 this->PointerWidth = this->PointerAlign = 32; 558 this->IntMaxType = TargetInfo::SignedLongLong; 559 this->Int64Type = TargetInfo::SignedLongLong; 560 this->SizeType = TargetInfo::UnsignedInt; 561 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 562 } 563 }; 564 565 template <typename Target> 566 class PS4OSTargetInfo : public OSTargetInfo<Target> { 567 protected: 568 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 569 MacroBuilder &Builder) const override { 570 Builder.defineMacro("__FreeBSD__", "9"); 571 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 572 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 573 DefineStd(Builder, "unix", Opts); 574 Builder.defineMacro("__ELF__"); 575 Builder.defineMacro("__PS4__"); 576 } 577 public: 578 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 579 this->WCharType = this->UnsignedShort; 580 581 this->UserLabelPrefix = ""; 582 583 switch (Triple.getArch()) { 584 default: 585 case llvm::Triple::x86_64: 586 this->MCountName = ".mcount"; 587 break; 588 } 589 } 590 }; 591 592 // Solaris target 593 template<typename Target> 594 class SolarisTargetInfo : public OSTargetInfo<Target> { 595 protected: 596 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 597 MacroBuilder &Builder) const override { 598 DefineStd(Builder, "sun", Opts); 599 DefineStd(Builder, "unix", Opts); 600 Builder.defineMacro("__ELF__"); 601 Builder.defineMacro("__svr4__"); 602 Builder.defineMacro("__SVR4"); 603 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 604 // newer, but to 500 for everything else. feature_test.h has a check to 605 // ensure that you are not using C99 with an old version of X/Open or C89 606 // with a new version. 607 if (Opts.C99) 608 Builder.defineMacro("_XOPEN_SOURCE", "600"); 609 else 610 Builder.defineMacro("_XOPEN_SOURCE", "500"); 611 if (Opts.CPlusPlus) 612 Builder.defineMacro("__C99FEATURES__"); 613 Builder.defineMacro("_LARGEFILE_SOURCE"); 614 Builder.defineMacro("_LARGEFILE64_SOURCE"); 615 Builder.defineMacro("__EXTENSIONS__"); 616 Builder.defineMacro("_REENTRANT"); 617 } 618 public: 619 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 620 this->UserLabelPrefix = ""; 621 this->WCharType = this->SignedInt; 622 // FIXME: WIntType should be SignedLong 623 } 624 }; 625 626 // Windows target 627 template<typename Target> 628 class WindowsTargetInfo : public OSTargetInfo<Target> { 629 protected: 630 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 631 MacroBuilder &Builder) const override { 632 Builder.defineMacro("_WIN32"); 633 } 634 void getVisualStudioDefines(const LangOptions &Opts, 635 MacroBuilder &Builder) const { 636 if (Opts.CPlusPlus) { 637 if (Opts.RTTIData) 638 Builder.defineMacro("_CPPRTTI"); 639 640 if (Opts.CXXExceptions) 641 Builder.defineMacro("_CPPUNWIND"); 642 } 643 644 if (!Opts.CharIsSigned) 645 Builder.defineMacro("_CHAR_UNSIGNED"); 646 647 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 648 // but it works for now. 649 if (Opts.POSIXThreads) 650 Builder.defineMacro("_MT"); 651 652 if (Opts.MSCompatibilityVersion) { 653 Builder.defineMacro("_MSC_VER", 654 Twine(Opts.MSCompatibilityVersion / 100000)); 655 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 656 // FIXME We cannot encode the revision information into 32-bits 657 Builder.defineMacro("_MSC_BUILD", Twine(1)); 658 659 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(19)) 660 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 661 } 662 663 if (Opts.MicrosoftExt) { 664 Builder.defineMacro("_MSC_EXTENSIONS"); 665 666 if (Opts.CPlusPlus11) { 667 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 668 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 669 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 670 } 671 } 672 673 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 674 } 675 676 public: 677 WindowsTargetInfo(const llvm::Triple &Triple) 678 : OSTargetInfo<Target>(Triple) {} 679 }; 680 681 template <typename Target> 682 class NaClTargetInfo : public OSTargetInfo<Target> { 683 protected: 684 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 685 MacroBuilder &Builder) const override { 686 if (Opts.POSIXThreads) 687 Builder.defineMacro("_REENTRANT"); 688 if (Opts.CPlusPlus) 689 Builder.defineMacro("_GNU_SOURCE"); 690 691 DefineStd(Builder, "unix", Opts); 692 Builder.defineMacro("__ELF__"); 693 Builder.defineMacro("__native_client__"); 694 } 695 696 public: 697 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 698 this->UserLabelPrefix = ""; 699 this->LongAlign = 32; 700 this->LongWidth = 32; 701 this->PointerAlign = 32; 702 this->PointerWidth = 32; 703 this->IntMaxType = TargetInfo::SignedLongLong; 704 this->Int64Type = TargetInfo::SignedLongLong; 705 this->DoubleAlign = 64; 706 this->LongDoubleWidth = 64; 707 this->LongDoubleAlign = 64; 708 this->LongLongWidth = 64; 709 this->LongLongAlign = 64; 710 this->SizeType = TargetInfo::UnsignedInt; 711 this->PtrDiffType = TargetInfo::SignedInt; 712 this->IntPtrType = TargetInfo::SignedInt; 713 // RegParmMax is inherited from the underlying architecture 714 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 715 if (Triple.getArch() == llvm::Triple::arm) { 716 this->DescriptionString = 717 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 718 } else if (Triple.getArch() == llvm::Triple::x86) { 719 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 720 } else if (Triple.getArch() == llvm::Triple::x86_64) { 721 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 722 } else if (Triple.getArch() == llvm::Triple::mipsel) { 723 // Handled on mips' setDescriptionString. 724 } else { 725 assert(Triple.getArch() == llvm::Triple::le32); 726 this->DescriptionString = "e-p:32:32-i64:64"; 727 } 728 } 729 }; 730 731 //===----------------------------------------------------------------------===// 732 // Specific target implementations. 733 //===----------------------------------------------------------------------===// 734 735 // PPC abstract base class 736 class PPCTargetInfo : public TargetInfo { 737 static const Builtin::Info BuiltinInfo[]; 738 static const char * const GCCRegNames[]; 739 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 740 std::string CPU; 741 742 // Target cpu features. 743 bool HasVSX; 744 bool HasP8Vector; 745 bool HasP8Crypto; 746 bool HasQPX; 747 748 protected: 749 std::string ABI; 750 751 public: 752 PPCTargetInfo(const llvm::Triple &Triple) 753 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 754 HasP8Crypto(false), HasQPX(false) { 755 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 756 LongDoubleWidth = LongDoubleAlign = 128; 757 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 758 } 759 760 /// \brief Flags for architecture specific defines. 761 typedef enum { 762 ArchDefineNone = 0, 763 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 764 ArchDefinePpcgr = 1 << 1, 765 ArchDefinePpcsq = 1 << 2, 766 ArchDefine440 = 1 << 3, 767 ArchDefine603 = 1 << 4, 768 ArchDefine604 = 1 << 5, 769 ArchDefinePwr4 = 1 << 6, 770 ArchDefinePwr5 = 1 << 7, 771 ArchDefinePwr5x = 1 << 8, 772 ArchDefinePwr6 = 1 << 9, 773 ArchDefinePwr6x = 1 << 10, 774 ArchDefinePwr7 = 1 << 11, 775 ArchDefinePwr8 = 1 << 12, 776 ArchDefineA2 = 1 << 13, 777 ArchDefineA2q = 1 << 14 778 } ArchDefineTypes; 779 780 // Note: GCC recognizes the following additional cpus: 781 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 782 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 783 // titan, rs64. 784 bool setCPU(const std::string &Name) override { 785 bool CPUKnown = llvm::StringSwitch<bool>(Name) 786 .Case("generic", true) 787 .Case("440", true) 788 .Case("450", true) 789 .Case("601", true) 790 .Case("602", true) 791 .Case("603", true) 792 .Case("603e", true) 793 .Case("603ev", true) 794 .Case("604", true) 795 .Case("604e", true) 796 .Case("620", true) 797 .Case("630", true) 798 .Case("g3", true) 799 .Case("7400", true) 800 .Case("g4", true) 801 .Case("7450", true) 802 .Case("g4+", true) 803 .Case("750", true) 804 .Case("970", true) 805 .Case("g5", true) 806 .Case("a2", true) 807 .Case("a2q", true) 808 .Case("e500mc", true) 809 .Case("e5500", true) 810 .Case("power3", true) 811 .Case("pwr3", true) 812 .Case("power4", true) 813 .Case("pwr4", true) 814 .Case("power5", true) 815 .Case("pwr5", true) 816 .Case("power5x", true) 817 .Case("pwr5x", true) 818 .Case("power6", true) 819 .Case("pwr6", true) 820 .Case("power6x", true) 821 .Case("pwr6x", true) 822 .Case("power7", true) 823 .Case("pwr7", true) 824 .Case("power8", true) 825 .Case("pwr8", true) 826 .Case("powerpc", true) 827 .Case("ppc", true) 828 .Case("powerpc64", true) 829 .Case("ppc64", true) 830 .Case("powerpc64le", true) 831 .Case("ppc64le", true) 832 .Default(false); 833 834 if (CPUKnown) 835 CPU = Name; 836 837 return CPUKnown; 838 } 839 840 841 StringRef getABI() const override { return ABI; } 842 843 void getTargetBuiltins(const Builtin::Info *&Records, 844 unsigned &NumRecords) const override { 845 Records = BuiltinInfo; 846 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 847 } 848 849 bool isCLZForZeroUndef() const override { return false; } 850 851 void getTargetDefines(const LangOptions &Opts, 852 MacroBuilder &Builder) const override; 853 854 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 855 856 bool handleTargetFeatures(std::vector<std::string> &Features, 857 DiagnosticsEngine &Diags) override; 858 bool hasFeature(StringRef Feature) const override; 859 860 void getGCCRegNames(const char * const *&Names, 861 unsigned &NumNames) const override; 862 void getGCCRegAliases(const GCCRegAlias *&Aliases, 863 unsigned &NumAliases) const override; 864 bool validateAsmConstraint(const char *&Name, 865 TargetInfo::ConstraintInfo &Info) const override { 866 switch (*Name) { 867 default: return false; 868 case 'O': // Zero 869 break; 870 case 'b': // Base register 871 case 'f': // Floating point register 872 Info.setAllowsRegister(); 873 break; 874 // FIXME: The following are added to allow parsing. 875 // I just took a guess at what the actions should be. 876 // Also, is more specific checking needed? I.e. specific registers? 877 case 'd': // Floating point register (containing 64-bit value) 878 case 'v': // Altivec vector register 879 Info.setAllowsRegister(); 880 break; 881 case 'w': 882 switch (Name[1]) { 883 case 'd':// VSX vector register to hold vector double data 884 case 'f':// VSX vector register to hold vector float data 885 case 's':// VSX vector register to hold scalar float data 886 case 'a':// Any VSX register 887 case 'c':// An individual CR bit 888 break; 889 default: 890 return false; 891 } 892 Info.setAllowsRegister(); 893 Name++; // Skip over 'w'. 894 break; 895 case 'h': // `MQ', `CTR', or `LINK' register 896 case 'q': // `MQ' register 897 case 'c': // `CTR' register 898 case 'l': // `LINK' register 899 case 'x': // `CR' register (condition register) number 0 900 case 'y': // `CR' register (condition register) 901 case 'z': // `XER[CA]' carry bit (part of the XER register) 902 Info.setAllowsRegister(); 903 break; 904 case 'I': // Signed 16-bit constant 905 case 'J': // Unsigned 16-bit constant shifted left 16 bits 906 // (use `L' instead for SImode constants) 907 case 'K': // Unsigned 16-bit constant 908 case 'L': // Signed 16-bit constant shifted left 16 bits 909 case 'M': // Constant larger than 31 910 case 'N': // Exact power of 2 911 case 'P': // Constant whose negation is a signed 16-bit constant 912 case 'G': // Floating point constant that can be loaded into a 913 // register with one instruction per word 914 case 'H': // Integer/Floating point constant that can be loaded 915 // into a register using three instructions 916 break; 917 case 'm': // Memory operand. Note that on PowerPC targets, m can 918 // include addresses that update the base register. It 919 // is therefore only safe to use `m' in an asm statement 920 // if that asm statement accesses the operand exactly once. 921 // The asm statement must also use `%U<opno>' as a 922 // placeholder for the "update" flag in the corresponding 923 // load or store instruction. For example: 924 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 925 // is correct but: 926 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 927 // is not. Use es rather than m if you don't want the base 928 // register to be updated. 929 case 'e': 930 if (Name[1] != 's') 931 return false; 932 // es: A "stable" memory operand; that is, one which does not 933 // include any automodification of the base register. Unlike 934 // `m', this constraint can be used in asm statements that 935 // might access the operand several times, or that might not 936 // access it at all. 937 Info.setAllowsMemory(); 938 Name++; // Skip over 'e'. 939 break; 940 case 'Q': // Memory operand that is an offset from a register (it is 941 // usually better to use `m' or `es' in asm statements) 942 case 'Z': // Memory operand that is an indexed or indirect from a 943 // register (it is usually better to use `m' or `es' in 944 // asm statements) 945 Info.setAllowsMemory(); 946 Info.setAllowsRegister(); 947 break; 948 case 'R': // AIX TOC entry 949 case 'a': // Address operand that is an indexed or indirect from a 950 // register (`p' is preferable for asm statements) 951 case 'S': // Constant suitable as a 64-bit mask operand 952 case 'T': // Constant suitable as a 32-bit mask operand 953 case 'U': // System V Release 4 small data area reference 954 case 't': // AND masks that can be performed by two rldic{l, r} 955 // instructions 956 case 'W': // Vector constant that does not require memory 957 case 'j': // Vector constant that is all zeros. 958 break; 959 // End FIXME. 960 } 961 return true; 962 } 963 std::string convertConstraint(const char *&Constraint) const override { 964 std::string R; 965 switch (*Constraint) { 966 case 'e': 967 case 'w': 968 // Two-character constraint; add "^" hint for later parsing. 969 R = std::string("^") + std::string(Constraint, 2); 970 Constraint++; 971 break; 972 default: 973 return TargetInfo::convertConstraint(Constraint); 974 } 975 return R; 976 } 977 const char *getClobbers() const override { 978 return ""; 979 } 980 int getEHDataRegisterNumber(unsigned RegNo) const override { 981 if (RegNo == 0) return 3; 982 if (RegNo == 1) return 4; 983 return -1; 984 } 985 986 bool hasSjLjLowering() const override { 987 return true; 988 } 989 }; 990 991 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 992 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 993 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 994 ALL_LANGUAGES }, 995 #include "clang/Basic/BuiltinsPPC.def" 996 }; 997 998 /// handleTargetFeatures - Perform initialization based on the user 999 /// configured set of features. 1000 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1001 DiagnosticsEngine &Diags) { 1002 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1003 // Ignore disabled features. 1004 if (Features[i][0] == '-') 1005 continue; 1006 1007 StringRef Feature = StringRef(Features[i]).substr(1); 1008 1009 if (Feature == "vsx") { 1010 HasVSX = true; 1011 continue; 1012 } 1013 1014 if (Feature == "power8-vector") { 1015 HasP8Vector = true; 1016 continue; 1017 } 1018 1019 if (Feature == "crypto") { 1020 HasP8Crypto = true; 1021 continue; 1022 } 1023 1024 if (Feature == "qpx") { 1025 HasQPX = true; 1026 continue; 1027 } 1028 1029 // TODO: Finish this list and add an assert that we've handled them 1030 // all. 1031 } 1032 1033 return true; 1034 } 1035 1036 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1037 /// #defines that are not tied to a specific subtarget. 1038 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1039 MacroBuilder &Builder) const { 1040 // Target identification. 1041 Builder.defineMacro("__ppc__"); 1042 Builder.defineMacro("__PPC__"); 1043 Builder.defineMacro("_ARCH_PPC"); 1044 Builder.defineMacro("__powerpc__"); 1045 Builder.defineMacro("__POWERPC__"); 1046 if (PointerWidth == 64) { 1047 Builder.defineMacro("_ARCH_PPC64"); 1048 Builder.defineMacro("__powerpc64__"); 1049 Builder.defineMacro("__ppc64__"); 1050 Builder.defineMacro("__PPC64__"); 1051 } 1052 1053 // Target properties. 1054 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1055 Builder.defineMacro("_LITTLE_ENDIAN"); 1056 } else { 1057 if (getTriple().getOS() != llvm::Triple::NetBSD && 1058 getTriple().getOS() != llvm::Triple::OpenBSD) 1059 Builder.defineMacro("_BIG_ENDIAN"); 1060 } 1061 1062 // ABI options. 1063 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1064 Builder.defineMacro("_CALL_ELF", "1"); 1065 if (ABI == "elfv2") 1066 Builder.defineMacro("_CALL_ELF", "2"); 1067 1068 // Subtarget options. 1069 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1070 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1071 1072 // FIXME: Should be controlled by command line option. 1073 if (LongDoubleWidth == 128) 1074 Builder.defineMacro("__LONG_DOUBLE_128__"); 1075 1076 if (Opts.AltiVec) { 1077 Builder.defineMacro("__VEC__", "10206"); 1078 Builder.defineMacro("__ALTIVEC__"); 1079 } 1080 1081 // CPU identification. 1082 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1083 .Case("440", ArchDefineName) 1084 .Case("450", ArchDefineName | ArchDefine440) 1085 .Case("601", ArchDefineName) 1086 .Case("602", ArchDefineName | ArchDefinePpcgr) 1087 .Case("603", ArchDefineName | ArchDefinePpcgr) 1088 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1089 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1090 .Case("604", ArchDefineName | ArchDefinePpcgr) 1091 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1092 .Case("620", ArchDefineName | ArchDefinePpcgr) 1093 .Case("630", ArchDefineName | ArchDefinePpcgr) 1094 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1095 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1096 .Case("750", ArchDefineName | ArchDefinePpcgr) 1097 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1098 | ArchDefinePpcsq) 1099 .Case("a2", ArchDefineA2) 1100 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1101 .Case("pwr3", ArchDefinePpcgr) 1102 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1103 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1104 | ArchDefinePpcsq) 1105 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1106 | ArchDefinePpcgr | ArchDefinePpcsq) 1107 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1108 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1109 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1110 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1111 | ArchDefinePpcsq) 1112 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1113 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1114 | ArchDefinePpcgr | ArchDefinePpcsq) 1115 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1116 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1117 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1118 .Case("power3", ArchDefinePpcgr) 1119 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1120 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1121 | ArchDefinePpcsq) 1122 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1123 | ArchDefinePpcgr | ArchDefinePpcsq) 1124 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1125 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1126 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1127 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1128 | ArchDefinePpcsq) 1129 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1130 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1131 | ArchDefinePpcgr | ArchDefinePpcsq) 1132 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1133 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1134 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1135 .Default(ArchDefineNone); 1136 1137 if (defs & ArchDefineName) 1138 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1139 if (defs & ArchDefinePpcgr) 1140 Builder.defineMacro("_ARCH_PPCGR"); 1141 if (defs & ArchDefinePpcsq) 1142 Builder.defineMacro("_ARCH_PPCSQ"); 1143 if (defs & ArchDefine440) 1144 Builder.defineMacro("_ARCH_440"); 1145 if (defs & ArchDefine603) 1146 Builder.defineMacro("_ARCH_603"); 1147 if (defs & ArchDefine604) 1148 Builder.defineMacro("_ARCH_604"); 1149 if (defs & ArchDefinePwr4) 1150 Builder.defineMacro("_ARCH_PWR4"); 1151 if (defs & ArchDefinePwr5) 1152 Builder.defineMacro("_ARCH_PWR5"); 1153 if (defs & ArchDefinePwr5x) 1154 Builder.defineMacro("_ARCH_PWR5X"); 1155 if (defs & ArchDefinePwr6) 1156 Builder.defineMacro("_ARCH_PWR6"); 1157 if (defs & ArchDefinePwr6x) 1158 Builder.defineMacro("_ARCH_PWR6X"); 1159 if (defs & ArchDefinePwr7) 1160 Builder.defineMacro("_ARCH_PWR7"); 1161 if (defs & ArchDefinePwr8) 1162 Builder.defineMacro("_ARCH_PWR8"); 1163 if (defs & ArchDefineA2) 1164 Builder.defineMacro("_ARCH_A2"); 1165 if (defs & ArchDefineA2q) { 1166 Builder.defineMacro("_ARCH_A2Q"); 1167 Builder.defineMacro("_ARCH_QP"); 1168 } 1169 1170 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1171 Builder.defineMacro("__bg__"); 1172 Builder.defineMacro("__THW_BLUEGENE__"); 1173 Builder.defineMacro("__bgq__"); 1174 Builder.defineMacro("__TOS_BGQ__"); 1175 } 1176 1177 if (HasVSX) 1178 Builder.defineMacro("__VSX__"); 1179 if (HasP8Vector) 1180 Builder.defineMacro("__POWER8_VECTOR__"); 1181 if (HasP8Crypto) 1182 Builder.defineMacro("__CRYPTO__"); 1183 1184 // FIXME: The following are not yet generated here by Clang, but are 1185 // generated by GCC: 1186 // 1187 // _SOFT_FLOAT_ 1188 // __RECIP_PRECISION__ 1189 // __APPLE_ALTIVEC__ 1190 // __RECIP__ 1191 // __RECIPF__ 1192 // __RSQRTE__ 1193 // __RSQRTEF__ 1194 // _SOFT_DOUBLE_ 1195 // __NO_LWSYNC__ 1196 // __HAVE_BSWAP__ 1197 // __LONGDOUBLE128 1198 // __CMODEL_MEDIUM__ 1199 // __CMODEL_LARGE__ 1200 // _CALL_SYSV 1201 // _CALL_DARWIN 1202 // __NO_FPRS__ 1203 } 1204 1205 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1206 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1207 .Case("7400", true) 1208 .Case("g4", true) 1209 .Case("7450", true) 1210 .Case("g4+", true) 1211 .Case("970", true) 1212 .Case("g5", true) 1213 .Case("pwr6", true) 1214 .Case("pwr7", true) 1215 .Case("pwr8", true) 1216 .Case("ppc64", true) 1217 .Case("ppc64le", true) 1218 .Default(false); 1219 1220 Features["qpx"] = (CPU == "a2q"); 1221 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1222 .Case("ppc64le", true) 1223 .Case("pwr8", true) 1224 .Default(false); 1225 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1226 .Case("ppc64le", true) 1227 .Case("pwr8", true) 1228 .Default(false); 1229 } 1230 1231 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1232 return llvm::StringSwitch<bool>(Feature) 1233 .Case("powerpc", true) 1234 .Case("vsx", HasVSX) 1235 .Case("power8-vector", HasP8Vector) 1236 .Case("crypto", HasP8Crypto) 1237 .Case("qpx", HasQPX) 1238 .Default(false); 1239 } 1240 1241 const char * const PPCTargetInfo::GCCRegNames[] = { 1242 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1243 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1244 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1245 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1246 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1247 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1248 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1249 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1250 "mq", "lr", "ctr", "ap", 1251 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1252 "xer", 1253 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1254 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1255 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1256 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1257 "vrsave", "vscr", 1258 "spe_acc", "spefscr", 1259 "sfp" 1260 }; 1261 1262 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1263 unsigned &NumNames) const { 1264 Names = GCCRegNames; 1265 NumNames = llvm::array_lengthof(GCCRegNames); 1266 } 1267 1268 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1269 // While some of these aliases do map to different registers 1270 // they still share the same register name. 1271 { { "0" }, "r0" }, 1272 { { "1"}, "r1" }, 1273 { { "2" }, "r2" }, 1274 { { "3" }, "r3" }, 1275 { { "4" }, "r4" }, 1276 { { "5" }, "r5" }, 1277 { { "6" }, "r6" }, 1278 { { "7" }, "r7" }, 1279 { { "8" }, "r8" }, 1280 { { "9" }, "r9" }, 1281 { { "10" }, "r10" }, 1282 { { "11" }, "r11" }, 1283 { { "12" }, "r12" }, 1284 { { "13" }, "r13" }, 1285 { { "14" }, "r14" }, 1286 { { "15" }, "r15" }, 1287 { { "16" }, "r16" }, 1288 { { "17" }, "r17" }, 1289 { { "18" }, "r18" }, 1290 { { "19" }, "r19" }, 1291 { { "20" }, "r20" }, 1292 { { "21" }, "r21" }, 1293 { { "22" }, "r22" }, 1294 { { "23" }, "r23" }, 1295 { { "24" }, "r24" }, 1296 { { "25" }, "r25" }, 1297 { { "26" }, "r26" }, 1298 { { "27" }, "r27" }, 1299 { { "28" }, "r28" }, 1300 { { "29" }, "r29" }, 1301 { { "30" }, "r30" }, 1302 { { "31" }, "r31" }, 1303 { { "fr0" }, "f0" }, 1304 { { "fr1" }, "f1" }, 1305 { { "fr2" }, "f2" }, 1306 { { "fr3" }, "f3" }, 1307 { { "fr4" }, "f4" }, 1308 { { "fr5" }, "f5" }, 1309 { { "fr6" }, "f6" }, 1310 { { "fr7" }, "f7" }, 1311 { { "fr8" }, "f8" }, 1312 { { "fr9" }, "f9" }, 1313 { { "fr10" }, "f10" }, 1314 { { "fr11" }, "f11" }, 1315 { { "fr12" }, "f12" }, 1316 { { "fr13" }, "f13" }, 1317 { { "fr14" }, "f14" }, 1318 { { "fr15" }, "f15" }, 1319 { { "fr16" }, "f16" }, 1320 { { "fr17" }, "f17" }, 1321 { { "fr18" }, "f18" }, 1322 { { "fr19" }, "f19" }, 1323 { { "fr20" }, "f20" }, 1324 { { "fr21" }, "f21" }, 1325 { { "fr22" }, "f22" }, 1326 { { "fr23" }, "f23" }, 1327 { { "fr24" }, "f24" }, 1328 { { "fr25" }, "f25" }, 1329 { { "fr26" }, "f26" }, 1330 { { "fr27" }, "f27" }, 1331 { { "fr28" }, "f28" }, 1332 { { "fr29" }, "f29" }, 1333 { { "fr30" }, "f30" }, 1334 { { "fr31" }, "f31" }, 1335 { { "cc" }, "cr0" }, 1336 }; 1337 1338 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1339 unsigned &NumAliases) const { 1340 Aliases = GCCRegAliases; 1341 NumAliases = llvm::array_lengthof(GCCRegAliases); 1342 } 1343 1344 class PPC32TargetInfo : public PPCTargetInfo { 1345 public: 1346 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1347 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1348 1349 switch (getTriple().getOS()) { 1350 case llvm::Triple::Linux: 1351 case llvm::Triple::FreeBSD: 1352 case llvm::Triple::NetBSD: 1353 SizeType = UnsignedInt; 1354 PtrDiffType = SignedInt; 1355 IntPtrType = SignedInt; 1356 break; 1357 default: 1358 break; 1359 } 1360 1361 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1362 LongDoubleWidth = LongDoubleAlign = 64; 1363 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1364 } 1365 1366 // PPC32 supports atomics up to 4 bytes. 1367 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1368 } 1369 1370 BuiltinVaListKind getBuiltinVaListKind() const override { 1371 // This is the ELF definition, and is overridden by the Darwin sub-target 1372 return TargetInfo::PowerABIBuiltinVaList; 1373 } 1374 }; 1375 1376 // Note: ABI differences may eventually require us to have a separate 1377 // TargetInfo for little endian. 1378 class PPC64TargetInfo : public PPCTargetInfo { 1379 public: 1380 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1381 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1382 IntMaxType = SignedLong; 1383 Int64Type = SignedLong; 1384 1385 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1386 DescriptionString = "e-m:e-i64:64-n32:64"; 1387 ABI = "elfv2"; 1388 } else { 1389 DescriptionString = "E-m:e-i64:64-n32:64"; 1390 ABI = "elfv1"; 1391 } 1392 1393 switch (getTriple().getOS()) { 1394 case llvm::Triple::FreeBSD: 1395 LongDoubleWidth = LongDoubleAlign = 64; 1396 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1397 break; 1398 case llvm::Triple::NetBSD: 1399 IntMaxType = SignedLongLong; 1400 Int64Type = SignedLongLong; 1401 break; 1402 default: 1403 break; 1404 } 1405 1406 // PPC64 supports atomics up to 8 bytes. 1407 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1408 } 1409 BuiltinVaListKind getBuiltinVaListKind() const override { 1410 return TargetInfo::CharPtrBuiltinVaList; 1411 } 1412 // PPC64 Linux-specifc ABI options. 1413 bool setABI(const std::string &Name) override { 1414 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1415 ABI = Name; 1416 return true; 1417 } 1418 return false; 1419 } 1420 }; 1421 1422 class DarwinPPC32TargetInfo : 1423 public DarwinTargetInfo<PPC32TargetInfo> { 1424 public: 1425 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1426 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1427 HasAlignMac68kSupport = true; 1428 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1429 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1430 LongLongAlign = 32; 1431 SuitableAlign = 128; 1432 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1433 } 1434 BuiltinVaListKind getBuiltinVaListKind() const override { 1435 return TargetInfo::CharPtrBuiltinVaList; 1436 } 1437 }; 1438 1439 class DarwinPPC64TargetInfo : 1440 public DarwinTargetInfo<PPC64TargetInfo> { 1441 public: 1442 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1443 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1444 HasAlignMac68kSupport = true; 1445 SuitableAlign = 128; 1446 DescriptionString = "E-m:o-i64:64-n32:64"; 1447 } 1448 }; 1449 1450 static const unsigned NVPTXAddrSpaceMap[] = { 1451 1, // opencl_global 1452 3, // opencl_local 1453 4, // opencl_constant 1454 // FIXME: generic has to be added to the target 1455 0, // opencl_generic 1456 1, // cuda_device 1457 4, // cuda_constant 1458 3, // cuda_shared 1459 }; 1460 class NVPTXTargetInfo : public TargetInfo { 1461 static const char * const GCCRegNames[]; 1462 static const Builtin::Info BuiltinInfo[]; 1463 1464 // The GPU profiles supported by the NVPTX backend 1465 enum GPUKind { 1466 GK_NONE, 1467 GK_SM20, 1468 GK_SM21, 1469 GK_SM30, 1470 GK_SM35, 1471 } GPU; 1472 1473 public: 1474 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1475 BigEndian = false; 1476 TLSSupported = false; 1477 LongWidth = LongAlign = 64; 1478 AddrSpaceMap = &NVPTXAddrSpaceMap; 1479 UseAddrSpaceMapMangling = true; 1480 // Define available target features 1481 // These must be defined in sorted order! 1482 NoAsmVariants = true; 1483 // Set the default GPU to sm20 1484 GPU = GK_SM20; 1485 } 1486 void getTargetDefines(const LangOptions &Opts, 1487 MacroBuilder &Builder) const override { 1488 Builder.defineMacro("__PTX__"); 1489 Builder.defineMacro("__NVPTX__"); 1490 if (Opts.CUDAIsDevice) { 1491 // Set __CUDA_ARCH__ for the GPU specified. 1492 std::string CUDAArchCode; 1493 switch (GPU) { 1494 case GK_SM20: 1495 CUDAArchCode = "200"; 1496 break; 1497 case GK_SM21: 1498 CUDAArchCode = "210"; 1499 break; 1500 case GK_SM30: 1501 CUDAArchCode = "300"; 1502 break; 1503 case GK_SM35: 1504 CUDAArchCode = "350"; 1505 break; 1506 default: 1507 llvm_unreachable("Unhandled target CPU"); 1508 } 1509 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1510 } 1511 } 1512 void getTargetBuiltins(const Builtin::Info *&Records, 1513 unsigned &NumRecords) const override { 1514 Records = BuiltinInfo; 1515 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1516 } 1517 bool hasFeature(StringRef Feature) const override { 1518 return Feature == "ptx" || Feature == "nvptx"; 1519 } 1520 1521 void getGCCRegNames(const char * const *&Names, 1522 unsigned &NumNames) const override; 1523 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1524 unsigned &NumAliases) const override { 1525 // No aliases. 1526 Aliases = nullptr; 1527 NumAliases = 0; 1528 } 1529 bool 1530 validateAsmConstraint(const char *&Name, 1531 TargetInfo::ConstraintInfo &Info) const override { 1532 switch (*Name) { 1533 default: return false; 1534 case 'c': 1535 case 'h': 1536 case 'r': 1537 case 'l': 1538 case 'f': 1539 case 'd': 1540 Info.setAllowsRegister(); 1541 return true; 1542 } 1543 } 1544 const char *getClobbers() const override { 1545 // FIXME: Is this really right? 1546 return ""; 1547 } 1548 BuiltinVaListKind getBuiltinVaListKind() const override { 1549 // FIXME: implement 1550 return TargetInfo::CharPtrBuiltinVaList; 1551 } 1552 bool setCPU(const std::string &Name) override { 1553 GPU = llvm::StringSwitch<GPUKind>(Name) 1554 .Case("sm_20", GK_SM20) 1555 .Case("sm_21", GK_SM21) 1556 .Case("sm_30", GK_SM30) 1557 .Case("sm_35", GK_SM35) 1558 .Default(GK_NONE); 1559 1560 return GPU != GK_NONE; 1561 } 1562 }; 1563 1564 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1565 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1566 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1567 ALL_LANGUAGES }, 1568 #include "clang/Basic/BuiltinsNVPTX.def" 1569 }; 1570 1571 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1572 "r0" 1573 }; 1574 1575 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1576 unsigned &NumNames) const { 1577 Names = GCCRegNames; 1578 NumNames = llvm::array_lengthof(GCCRegNames); 1579 } 1580 1581 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1582 public: 1583 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1584 PointerWidth = PointerAlign = 32; 1585 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1586 IntPtrType = TargetInfo::SignedInt; 1587 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1588 } 1589 }; 1590 1591 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1592 public: 1593 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1594 PointerWidth = PointerAlign = 64; 1595 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1596 IntPtrType = TargetInfo::SignedLongLong; 1597 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1598 } 1599 }; 1600 1601 static const unsigned R600AddrSpaceMap[] = { 1602 1, // opencl_global 1603 3, // opencl_local 1604 2, // opencl_constant 1605 4, // opencl_generic 1606 1, // cuda_device 1607 2, // cuda_constant 1608 3 // cuda_shared 1609 }; 1610 1611 // If you edit the description strings, make sure you update 1612 // getPointerWidthV(). 1613 1614 static const char *DescriptionStringR600 = 1615 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1616 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1617 1618 static const char *DescriptionStringR600DoubleOps = 1619 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1620 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1621 1622 static const char *DescriptionStringSI = 1623 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1624 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1625 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1626 1627 class R600TargetInfo : public TargetInfo { 1628 static const Builtin::Info BuiltinInfo[]; 1629 1630 /// \brief The GPU profiles supported by the R600 target. 1631 enum GPUKind { 1632 GK_NONE, 1633 GK_R600, 1634 GK_R600_DOUBLE_OPS, 1635 GK_R700, 1636 GK_R700_DOUBLE_OPS, 1637 GK_EVERGREEN, 1638 GK_EVERGREEN_DOUBLE_OPS, 1639 GK_NORTHERN_ISLANDS, 1640 GK_CAYMAN, 1641 GK_SOUTHERN_ISLANDS, 1642 GK_SEA_ISLANDS 1643 } GPU; 1644 1645 public: 1646 R600TargetInfo(const llvm::Triple &Triple) 1647 : TargetInfo(Triple) { 1648 1649 if (Triple.getArch() == llvm::Triple::amdgcn) { 1650 DescriptionString = DescriptionStringSI; 1651 GPU = GK_SOUTHERN_ISLANDS; 1652 } else { 1653 DescriptionString = DescriptionStringR600; 1654 GPU = GK_R600; 1655 } 1656 AddrSpaceMap = &R600AddrSpaceMap; 1657 UseAddrSpaceMapMangling = true; 1658 } 1659 1660 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1661 if (GPU <= GK_CAYMAN) 1662 return 32; 1663 1664 switch(AddrSpace) { 1665 default: 1666 return 64; 1667 case 0: 1668 case 3: 1669 case 5: 1670 return 32; 1671 } 1672 } 1673 1674 const char * getClobbers() const override { 1675 return ""; 1676 } 1677 1678 void getGCCRegNames(const char * const *&Names, 1679 unsigned &numNames) const override { 1680 Names = nullptr; 1681 numNames = 0; 1682 } 1683 1684 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1685 unsigned &NumAliases) const override { 1686 Aliases = nullptr; 1687 NumAliases = 0; 1688 } 1689 1690 bool validateAsmConstraint(const char *&Name, 1691 TargetInfo::ConstraintInfo &info) const override { 1692 return true; 1693 } 1694 1695 void getTargetBuiltins(const Builtin::Info *&Records, 1696 unsigned &NumRecords) const override { 1697 Records = BuiltinInfo; 1698 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1699 } 1700 1701 void getTargetDefines(const LangOptions &Opts, 1702 MacroBuilder &Builder) const override { 1703 Builder.defineMacro("__R600__"); 1704 if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL) 1705 Builder.defineMacro("cl_khr_fp64"); 1706 } 1707 1708 BuiltinVaListKind getBuiltinVaListKind() const override { 1709 return TargetInfo::CharPtrBuiltinVaList; 1710 } 1711 1712 bool setCPU(const std::string &Name) override { 1713 GPU = llvm::StringSwitch<GPUKind>(Name) 1714 .Case("r600" , GK_R600) 1715 .Case("rv610", GK_R600) 1716 .Case("rv620", GK_R600) 1717 .Case("rv630", GK_R600) 1718 .Case("rv635", GK_R600) 1719 .Case("rs780", GK_R600) 1720 .Case("rs880", GK_R600) 1721 .Case("rv670", GK_R600_DOUBLE_OPS) 1722 .Case("rv710", GK_R700) 1723 .Case("rv730", GK_R700) 1724 .Case("rv740", GK_R700_DOUBLE_OPS) 1725 .Case("rv770", GK_R700_DOUBLE_OPS) 1726 .Case("palm", GK_EVERGREEN) 1727 .Case("cedar", GK_EVERGREEN) 1728 .Case("sumo", GK_EVERGREEN) 1729 .Case("sumo2", GK_EVERGREEN) 1730 .Case("redwood", GK_EVERGREEN) 1731 .Case("juniper", GK_EVERGREEN) 1732 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1733 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1734 .Case("barts", GK_NORTHERN_ISLANDS) 1735 .Case("turks", GK_NORTHERN_ISLANDS) 1736 .Case("caicos", GK_NORTHERN_ISLANDS) 1737 .Case("cayman", GK_CAYMAN) 1738 .Case("aruba", GK_CAYMAN) 1739 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1740 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1741 .Case("verde", GK_SOUTHERN_ISLANDS) 1742 .Case("oland", GK_SOUTHERN_ISLANDS) 1743 .Case("hainan", GK_SOUTHERN_ISLANDS) 1744 .Case("bonaire", GK_SEA_ISLANDS) 1745 .Case("kabini", GK_SEA_ISLANDS) 1746 .Case("kaveri", GK_SEA_ISLANDS) 1747 .Case("hawaii", GK_SEA_ISLANDS) 1748 .Case("mullins", GK_SEA_ISLANDS) 1749 .Default(GK_NONE); 1750 1751 if (GPU == GK_NONE) { 1752 return false; 1753 } 1754 1755 // Set the correct data layout 1756 switch (GPU) { 1757 case GK_NONE: 1758 case GK_R600: 1759 case GK_R700: 1760 case GK_EVERGREEN: 1761 case GK_NORTHERN_ISLANDS: 1762 DescriptionString = DescriptionStringR600; 1763 break; 1764 case GK_R600_DOUBLE_OPS: 1765 case GK_R700_DOUBLE_OPS: 1766 case GK_EVERGREEN_DOUBLE_OPS: 1767 case GK_CAYMAN: 1768 DescriptionString = DescriptionStringR600DoubleOps; 1769 break; 1770 case GK_SOUTHERN_ISLANDS: 1771 case GK_SEA_ISLANDS: 1772 DescriptionString = DescriptionStringSI; 1773 break; 1774 } 1775 1776 return true; 1777 } 1778 }; 1779 1780 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1781 #define BUILTIN(ID, TYPE, ATTRS) \ 1782 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1783 #include "clang/Basic/BuiltinsR600.def" 1784 }; 1785 1786 // Namespace for x86 abstract base class 1787 const Builtin::Info BuiltinInfo[] = { 1788 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1789 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1790 ALL_LANGUAGES }, 1791 #include "clang/Basic/BuiltinsX86.def" 1792 }; 1793 1794 static const char* const GCCRegNames[] = { 1795 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1796 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1797 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1798 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1799 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1800 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1801 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1802 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1803 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1804 }; 1805 1806 const TargetInfo::AddlRegName AddlRegNames[] = { 1807 { { "al", "ah", "eax", "rax" }, 0 }, 1808 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1809 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1810 { { "dl", "dh", "edx", "rdx" }, 1 }, 1811 { { "esi", "rsi" }, 4 }, 1812 { { "edi", "rdi" }, 5 }, 1813 { { "esp", "rsp" }, 7 }, 1814 { { "ebp", "rbp" }, 6 }, 1815 }; 1816 1817 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1818 // most of the implementation can be shared. 1819 class X86TargetInfo : public TargetInfo { 1820 enum X86SSEEnum { 1821 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1822 } SSELevel; 1823 enum MMX3DNowEnum { 1824 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1825 } MMX3DNowLevel; 1826 enum XOPEnum { 1827 NoXOP, 1828 SSE4A, 1829 FMA4, 1830 XOP 1831 } XOPLevel; 1832 1833 bool HasAES; 1834 bool HasPCLMUL; 1835 bool HasLZCNT; 1836 bool HasRDRND; 1837 bool HasFSGSBASE; 1838 bool HasBMI; 1839 bool HasBMI2; 1840 bool HasPOPCNT; 1841 bool HasRTM; 1842 bool HasPRFCHW; 1843 bool HasRDSEED; 1844 bool HasADX; 1845 bool HasTBM; 1846 bool HasFMA; 1847 bool HasF16C; 1848 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1849 HasAVX512VL; 1850 bool HasSHA; 1851 bool HasCX16; 1852 1853 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1854 /// 1855 /// Each enumeration represents a particular CPU supported by Clang. These 1856 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1857 enum CPUKind { 1858 CK_Generic, 1859 1860 /// \name i386 1861 /// i386-generation processors. 1862 //@{ 1863 CK_i386, 1864 //@} 1865 1866 /// \name i486 1867 /// i486-generation processors. 1868 //@{ 1869 CK_i486, 1870 CK_WinChipC6, 1871 CK_WinChip2, 1872 CK_C3, 1873 //@} 1874 1875 /// \name i586 1876 /// i586-generation processors, P5 microarchitecture based. 1877 //@{ 1878 CK_i586, 1879 CK_Pentium, 1880 CK_PentiumMMX, 1881 //@} 1882 1883 /// \name i686 1884 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1885 //@{ 1886 CK_i686, 1887 CK_PentiumPro, 1888 CK_Pentium2, 1889 CK_Pentium3, 1890 CK_Pentium3M, 1891 CK_PentiumM, 1892 CK_C3_2, 1893 1894 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1895 /// Clang however has some logic to suport this. 1896 // FIXME: Warn, deprecate, and potentially remove this. 1897 CK_Yonah, 1898 //@} 1899 1900 /// \name Netburst 1901 /// Netburst microarchitecture based processors. 1902 //@{ 1903 CK_Pentium4, 1904 CK_Pentium4M, 1905 CK_Prescott, 1906 CK_Nocona, 1907 //@} 1908 1909 /// \name Core 1910 /// Core microarchitecture based processors. 1911 //@{ 1912 CK_Core2, 1913 1914 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1915 /// codename which GCC no longer accepts as an option to -march, but Clang 1916 /// has some logic for recognizing it. 1917 // FIXME: Warn, deprecate, and potentially remove this. 1918 CK_Penryn, 1919 //@} 1920 1921 /// \name Atom 1922 /// Atom processors 1923 //@{ 1924 CK_Bonnell, 1925 CK_Silvermont, 1926 //@} 1927 1928 /// \name Nehalem 1929 /// Nehalem microarchitecture based processors. 1930 CK_Nehalem, 1931 1932 /// \name Westmere 1933 /// Westmere microarchitecture based processors. 1934 CK_Westmere, 1935 1936 /// \name Sandy Bridge 1937 /// Sandy Bridge microarchitecture based processors. 1938 CK_SandyBridge, 1939 1940 /// \name Ivy Bridge 1941 /// Ivy Bridge microarchitecture based processors. 1942 CK_IvyBridge, 1943 1944 /// \name Haswell 1945 /// Haswell microarchitecture based processors. 1946 CK_Haswell, 1947 1948 /// \name Broadwell 1949 /// Broadwell microarchitecture based processors. 1950 CK_Broadwell, 1951 1952 /// \name Skylake 1953 /// Skylake microarchitecture based processors. 1954 CK_Skylake, 1955 1956 /// \name Knights Landing 1957 /// Knights Landing processor. 1958 CK_KNL, 1959 1960 /// \name K6 1961 /// K6 architecture processors. 1962 //@{ 1963 CK_K6, 1964 CK_K6_2, 1965 CK_K6_3, 1966 //@} 1967 1968 /// \name K7 1969 /// K7 architecture processors. 1970 //@{ 1971 CK_Athlon, 1972 CK_AthlonThunderbird, 1973 CK_Athlon4, 1974 CK_AthlonXP, 1975 CK_AthlonMP, 1976 //@} 1977 1978 /// \name K8 1979 /// K8 architecture processors. 1980 //@{ 1981 CK_Athlon64, 1982 CK_Athlon64SSE3, 1983 CK_AthlonFX, 1984 CK_K8, 1985 CK_K8SSE3, 1986 CK_Opteron, 1987 CK_OpteronSSE3, 1988 CK_AMDFAM10, 1989 //@} 1990 1991 /// \name Bobcat 1992 /// Bobcat architecture processors. 1993 //@{ 1994 CK_BTVER1, 1995 CK_BTVER2, 1996 //@} 1997 1998 /// \name Bulldozer 1999 /// Bulldozer architecture processors. 2000 //@{ 2001 CK_BDVER1, 2002 CK_BDVER2, 2003 CK_BDVER3, 2004 CK_BDVER4, 2005 //@} 2006 2007 /// This specification is deprecated and will be removed in the future. 2008 /// Users should prefer \see CK_K8. 2009 // FIXME: Warn on this when the CPU is set to it. 2010 //@{ 2011 CK_x86_64, 2012 //@} 2013 2014 /// \name Geode 2015 /// Geode processors. 2016 //@{ 2017 CK_Geode 2018 //@} 2019 } CPU; 2020 2021 enum FPMathKind { 2022 FP_Default, 2023 FP_SSE, 2024 FP_387 2025 } FPMath; 2026 2027 public: 2028 X86TargetInfo(const llvm::Triple &Triple) 2029 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2030 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2031 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2032 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2033 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2034 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2035 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2036 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2037 BigEndian = false; 2038 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2039 } 2040 unsigned getFloatEvalMethod() const override { 2041 // X87 evaluates with 80 bits "long double" precision. 2042 return SSELevel == NoSSE ? 2 : 0; 2043 } 2044 void getTargetBuiltins(const Builtin::Info *&Records, 2045 unsigned &NumRecords) const override { 2046 Records = BuiltinInfo; 2047 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2048 } 2049 void getGCCRegNames(const char * const *&Names, 2050 unsigned &NumNames) const override { 2051 Names = GCCRegNames; 2052 NumNames = llvm::array_lengthof(GCCRegNames); 2053 } 2054 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2055 unsigned &NumAliases) const override { 2056 Aliases = nullptr; 2057 NumAliases = 0; 2058 } 2059 void getGCCAddlRegNames(const AddlRegName *&Names, 2060 unsigned &NumNames) const override { 2061 Names = AddlRegNames; 2062 NumNames = llvm::array_lengthof(AddlRegNames); 2063 } 2064 bool validateAsmConstraint(const char *&Name, 2065 TargetInfo::ConstraintInfo &info) const override; 2066 2067 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2068 2069 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2070 2071 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2072 2073 std::string convertConstraint(const char *&Constraint) const override; 2074 const char *getClobbers() const override { 2075 return "~{dirflag},~{fpsr},~{flags}"; 2076 } 2077 void getTargetDefines(const LangOptions &Opts, 2078 MacroBuilder &Builder) const override; 2079 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2080 bool Enabled); 2081 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2082 bool Enabled); 2083 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2084 bool Enabled); 2085 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2086 StringRef Name, bool Enabled) const override { 2087 setFeatureEnabledImpl(Features, Name, Enabled); 2088 } 2089 // This exists purely to cut down on the number of virtual calls in 2090 // getDefaultFeatures which calls this repeatedly. 2091 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2092 StringRef Name, bool Enabled); 2093 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2094 bool hasFeature(StringRef Feature) const override; 2095 bool handleTargetFeatures(std::vector<std::string> &Features, 2096 DiagnosticsEngine &Diags) override; 2097 StringRef getABI() const override { 2098 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2099 return "avx"; 2100 else if (getTriple().getArch() == llvm::Triple::x86 && 2101 MMX3DNowLevel == NoMMX3DNow) 2102 return "no-mmx"; 2103 return ""; 2104 } 2105 bool setCPU(const std::string &Name) override { 2106 CPU = llvm::StringSwitch<CPUKind>(Name) 2107 .Case("i386", CK_i386) 2108 .Case("i486", CK_i486) 2109 .Case("winchip-c6", CK_WinChipC6) 2110 .Case("winchip2", CK_WinChip2) 2111 .Case("c3", CK_C3) 2112 .Case("i586", CK_i586) 2113 .Case("pentium", CK_Pentium) 2114 .Case("pentium-mmx", CK_PentiumMMX) 2115 .Case("i686", CK_i686) 2116 .Case("pentiumpro", CK_PentiumPro) 2117 .Case("pentium2", CK_Pentium2) 2118 .Case("pentium3", CK_Pentium3) 2119 .Case("pentium3m", CK_Pentium3M) 2120 .Case("pentium-m", CK_PentiumM) 2121 .Case("c3-2", CK_C3_2) 2122 .Case("yonah", CK_Yonah) 2123 .Case("pentium4", CK_Pentium4) 2124 .Case("pentium4m", CK_Pentium4M) 2125 .Case("prescott", CK_Prescott) 2126 .Case("nocona", CK_Nocona) 2127 .Case("core2", CK_Core2) 2128 .Case("penryn", CK_Penryn) 2129 .Case("bonnell", CK_Bonnell) 2130 .Case("atom", CK_Bonnell) // Legacy name. 2131 .Case("silvermont", CK_Silvermont) 2132 .Case("slm", CK_Silvermont) // Legacy name. 2133 .Case("nehalem", CK_Nehalem) 2134 .Case("corei7", CK_Nehalem) // Legacy name. 2135 .Case("westmere", CK_Westmere) 2136 .Case("sandybridge", CK_SandyBridge) 2137 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2138 .Case("ivybridge", CK_IvyBridge) 2139 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2140 .Case("haswell", CK_Haswell) 2141 .Case("core-avx2", CK_Haswell) // Legacy name. 2142 .Case("broadwell", CK_Broadwell) 2143 .Case("skylake", CK_Skylake) 2144 .Case("skx", CK_Skylake) // Legacy name. 2145 .Case("knl", CK_KNL) 2146 .Case("k6", CK_K6) 2147 .Case("k6-2", CK_K6_2) 2148 .Case("k6-3", CK_K6_3) 2149 .Case("athlon", CK_Athlon) 2150 .Case("athlon-tbird", CK_AthlonThunderbird) 2151 .Case("athlon-4", CK_Athlon4) 2152 .Case("athlon-xp", CK_AthlonXP) 2153 .Case("athlon-mp", CK_AthlonMP) 2154 .Case("athlon64", CK_Athlon64) 2155 .Case("athlon64-sse3", CK_Athlon64SSE3) 2156 .Case("athlon-fx", CK_AthlonFX) 2157 .Case("k8", CK_K8) 2158 .Case("k8-sse3", CK_K8SSE3) 2159 .Case("opteron", CK_Opteron) 2160 .Case("opteron-sse3", CK_OpteronSSE3) 2161 .Case("barcelona", CK_AMDFAM10) 2162 .Case("amdfam10", CK_AMDFAM10) 2163 .Case("btver1", CK_BTVER1) 2164 .Case("btver2", CK_BTVER2) 2165 .Case("bdver1", CK_BDVER1) 2166 .Case("bdver2", CK_BDVER2) 2167 .Case("bdver3", CK_BDVER3) 2168 .Case("bdver4", CK_BDVER4) 2169 .Case("x86-64", CK_x86_64) 2170 .Case("geode", CK_Geode) 2171 .Default(CK_Generic); 2172 2173 // Perform any per-CPU checks necessary to determine if this CPU is 2174 // acceptable. 2175 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2176 // invalid without explaining *why*. 2177 switch (CPU) { 2178 case CK_Generic: 2179 // No processor selected! 2180 return false; 2181 2182 case CK_i386: 2183 case CK_i486: 2184 case CK_WinChipC6: 2185 case CK_WinChip2: 2186 case CK_C3: 2187 case CK_i586: 2188 case CK_Pentium: 2189 case CK_PentiumMMX: 2190 case CK_i686: 2191 case CK_PentiumPro: 2192 case CK_Pentium2: 2193 case CK_Pentium3: 2194 case CK_Pentium3M: 2195 case CK_PentiumM: 2196 case CK_Yonah: 2197 case CK_C3_2: 2198 case CK_Pentium4: 2199 case CK_Pentium4M: 2200 case CK_Prescott: 2201 case CK_K6: 2202 case CK_K6_2: 2203 case CK_K6_3: 2204 case CK_Athlon: 2205 case CK_AthlonThunderbird: 2206 case CK_Athlon4: 2207 case CK_AthlonXP: 2208 case CK_AthlonMP: 2209 case CK_Geode: 2210 // Only accept certain architectures when compiling in 32-bit mode. 2211 if (getTriple().getArch() != llvm::Triple::x86) 2212 return false; 2213 2214 // Fallthrough 2215 case CK_Nocona: 2216 case CK_Core2: 2217 case CK_Penryn: 2218 case CK_Bonnell: 2219 case CK_Silvermont: 2220 case CK_Nehalem: 2221 case CK_Westmere: 2222 case CK_SandyBridge: 2223 case CK_IvyBridge: 2224 case CK_Haswell: 2225 case CK_Broadwell: 2226 case CK_Skylake: 2227 case CK_KNL: 2228 case CK_Athlon64: 2229 case CK_Athlon64SSE3: 2230 case CK_AthlonFX: 2231 case CK_K8: 2232 case CK_K8SSE3: 2233 case CK_Opteron: 2234 case CK_OpteronSSE3: 2235 case CK_AMDFAM10: 2236 case CK_BTVER1: 2237 case CK_BTVER2: 2238 case CK_BDVER1: 2239 case CK_BDVER2: 2240 case CK_BDVER3: 2241 case CK_BDVER4: 2242 case CK_x86_64: 2243 return true; 2244 } 2245 llvm_unreachable("Unhandled CPU kind"); 2246 } 2247 2248 bool setFPMath(StringRef Name) override; 2249 2250 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2251 // We accept all non-ARM calling conventions 2252 return (CC == CC_X86ThisCall || 2253 CC == CC_X86FastCall || 2254 CC == CC_X86StdCall || 2255 CC == CC_X86VectorCall || 2256 CC == CC_C || 2257 CC == CC_X86Pascal || 2258 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2259 } 2260 2261 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2262 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2263 } 2264 2265 bool hasSjLjLowering() const override { 2266 return true; 2267 } 2268 }; 2269 2270 bool X86TargetInfo::setFPMath(StringRef Name) { 2271 if (Name == "387") { 2272 FPMath = FP_387; 2273 return true; 2274 } 2275 if (Name == "sse") { 2276 FPMath = FP_SSE; 2277 return true; 2278 } 2279 return false; 2280 } 2281 2282 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2283 // FIXME: This *really* should not be here. 2284 2285 // X86_64 always has SSE2. 2286 if (getTriple().getArch() == llvm::Triple::x86_64) 2287 setFeatureEnabledImpl(Features, "sse2", true); 2288 2289 switch (CPU) { 2290 case CK_Generic: 2291 case CK_i386: 2292 case CK_i486: 2293 case CK_i586: 2294 case CK_Pentium: 2295 case CK_i686: 2296 case CK_PentiumPro: 2297 break; 2298 case CK_PentiumMMX: 2299 case CK_Pentium2: 2300 case CK_K6: 2301 case CK_WinChipC6: 2302 setFeatureEnabledImpl(Features, "mmx", true); 2303 break; 2304 case CK_Pentium3: 2305 case CK_Pentium3M: 2306 case CK_C3_2: 2307 setFeatureEnabledImpl(Features, "sse", true); 2308 break; 2309 case CK_PentiumM: 2310 case CK_Pentium4: 2311 case CK_Pentium4M: 2312 case CK_x86_64: 2313 setFeatureEnabledImpl(Features, "sse2", true); 2314 break; 2315 case CK_Yonah: 2316 case CK_Prescott: 2317 case CK_Nocona: 2318 setFeatureEnabledImpl(Features, "sse3", true); 2319 setFeatureEnabledImpl(Features, "cx16", true); 2320 break; 2321 case CK_Core2: 2322 case CK_Bonnell: 2323 setFeatureEnabledImpl(Features, "ssse3", true); 2324 setFeatureEnabledImpl(Features, "cx16", true); 2325 break; 2326 case CK_Penryn: 2327 setFeatureEnabledImpl(Features, "sse4.1", true); 2328 setFeatureEnabledImpl(Features, "cx16", true); 2329 break; 2330 case CK_Skylake: 2331 setFeatureEnabledImpl(Features, "avx512f", true); 2332 setFeatureEnabledImpl(Features, "avx512cd", true); 2333 setFeatureEnabledImpl(Features, "avx512dq", true); 2334 setFeatureEnabledImpl(Features, "avx512bw", true); 2335 setFeatureEnabledImpl(Features, "avx512vl", true); 2336 // FALLTHROUGH 2337 case CK_Broadwell: 2338 setFeatureEnabledImpl(Features, "rdseed", true); 2339 setFeatureEnabledImpl(Features, "adx", true); 2340 // FALLTHROUGH 2341 case CK_Haswell: 2342 setFeatureEnabledImpl(Features, "avx2", true); 2343 setFeatureEnabledImpl(Features, "lzcnt", true); 2344 setFeatureEnabledImpl(Features, "bmi", true); 2345 setFeatureEnabledImpl(Features, "bmi2", true); 2346 setFeatureEnabledImpl(Features, "rtm", true); 2347 setFeatureEnabledImpl(Features, "fma", true); 2348 // FALLTHROUGH 2349 case CK_IvyBridge: 2350 setFeatureEnabledImpl(Features, "rdrnd", true); 2351 setFeatureEnabledImpl(Features, "f16c", true); 2352 setFeatureEnabledImpl(Features, "fsgsbase", true); 2353 // FALLTHROUGH 2354 case CK_SandyBridge: 2355 setFeatureEnabledImpl(Features, "avx", true); 2356 // FALLTHROUGH 2357 case CK_Westmere: 2358 case CK_Silvermont: 2359 setFeatureEnabledImpl(Features, "aes", true); 2360 setFeatureEnabledImpl(Features, "pclmul", true); 2361 // FALLTHROUGH 2362 case CK_Nehalem: 2363 setFeatureEnabledImpl(Features, "sse4.2", true); 2364 setFeatureEnabledImpl(Features, "cx16", true); 2365 break; 2366 case CK_KNL: 2367 setFeatureEnabledImpl(Features, "avx512f", true); 2368 setFeatureEnabledImpl(Features, "avx512cd", true); 2369 setFeatureEnabledImpl(Features, "avx512er", true); 2370 setFeatureEnabledImpl(Features, "avx512pf", true); 2371 setFeatureEnabledImpl(Features, "rdseed", true); 2372 setFeatureEnabledImpl(Features, "adx", true); 2373 setFeatureEnabledImpl(Features, "lzcnt", true); 2374 setFeatureEnabledImpl(Features, "bmi", true); 2375 setFeatureEnabledImpl(Features, "bmi2", true); 2376 setFeatureEnabledImpl(Features, "rtm", true); 2377 setFeatureEnabledImpl(Features, "fma", true); 2378 setFeatureEnabledImpl(Features, "rdrnd", true); 2379 setFeatureEnabledImpl(Features, "f16c", true); 2380 setFeatureEnabledImpl(Features, "fsgsbase", true); 2381 setFeatureEnabledImpl(Features, "aes", true); 2382 setFeatureEnabledImpl(Features, "pclmul", true); 2383 setFeatureEnabledImpl(Features, "cx16", true); 2384 break; 2385 case CK_K6_2: 2386 case CK_K6_3: 2387 case CK_WinChip2: 2388 case CK_C3: 2389 setFeatureEnabledImpl(Features, "3dnow", true); 2390 break; 2391 case CK_Athlon: 2392 case CK_AthlonThunderbird: 2393 case CK_Geode: 2394 setFeatureEnabledImpl(Features, "3dnowa", true); 2395 break; 2396 case CK_Athlon4: 2397 case CK_AthlonXP: 2398 case CK_AthlonMP: 2399 setFeatureEnabledImpl(Features, "sse", true); 2400 setFeatureEnabledImpl(Features, "3dnowa", true); 2401 break; 2402 case CK_K8: 2403 case CK_Opteron: 2404 case CK_Athlon64: 2405 case CK_AthlonFX: 2406 setFeatureEnabledImpl(Features, "sse2", true); 2407 setFeatureEnabledImpl(Features, "3dnowa", true); 2408 break; 2409 case CK_AMDFAM10: 2410 setFeatureEnabledImpl(Features, "sse4a", true); 2411 setFeatureEnabledImpl(Features, "lzcnt", true); 2412 setFeatureEnabledImpl(Features, "popcnt", true); 2413 // FALLTHROUGH 2414 case CK_K8SSE3: 2415 case CK_OpteronSSE3: 2416 case CK_Athlon64SSE3: 2417 setFeatureEnabledImpl(Features, "sse3", true); 2418 setFeatureEnabledImpl(Features, "3dnowa", true); 2419 break; 2420 case CK_BTVER2: 2421 setFeatureEnabledImpl(Features, "avx", true); 2422 setFeatureEnabledImpl(Features, "aes", true); 2423 setFeatureEnabledImpl(Features, "pclmul", true); 2424 setFeatureEnabledImpl(Features, "bmi", true); 2425 setFeatureEnabledImpl(Features, "f16c", true); 2426 // FALLTHROUGH 2427 case CK_BTVER1: 2428 setFeatureEnabledImpl(Features, "ssse3", true); 2429 setFeatureEnabledImpl(Features, "sse4a", true); 2430 setFeatureEnabledImpl(Features, "lzcnt", true); 2431 setFeatureEnabledImpl(Features, "popcnt", true); 2432 setFeatureEnabledImpl(Features, "prfchw", true); 2433 setFeatureEnabledImpl(Features, "cx16", true); 2434 break; 2435 case CK_BDVER4: 2436 setFeatureEnabledImpl(Features, "avx2", true); 2437 setFeatureEnabledImpl(Features, "bmi2", true); 2438 // FALLTHROUGH 2439 case CK_BDVER3: 2440 setFeatureEnabledImpl(Features, "fsgsbase", true); 2441 // FALLTHROUGH 2442 case CK_BDVER2: 2443 setFeatureEnabledImpl(Features, "bmi", true); 2444 setFeatureEnabledImpl(Features, "fma", true); 2445 setFeatureEnabledImpl(Features, "f16c", true); 2446 setFeatureEnabledImpl(Features, "tbm", true); 2447 // FALLTHROUGH 2448 case CK_BDVER1: 2449 // xop implies avx, sse4a and fma4. 2450 setFeatureEnabledImpl(Features, "xop", true); 2451 setFeatureEnabledImpl(Features, "lzcnt", true); 2452 setFeatureEnabledImpl(Features, "aes", true); 2453 setFeatureEnabledImpl(Features, "pclmul", true); 2454 setFeatureEnabledImpl(Features, "prfchw", true); 2455 setFeatureEnabledImpl(Features, "cx16", true); 2456 break; 2457 } 2458 } 2459 2460 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2461 X86SSEEnum Level, bool Enabled) { 2462 if (Enabled) { 2463 switch (Level) { 2464 case AVX512F: 2465 Features["avx512f"] = true; 2466 case AVX2: 2467 Features["avx2"] = true; 2468 case AVX: 2469 Features["avx"] = true; 2470 case SSE42: 2471 Features["sse4.2"] = true; 2472 case SSE41: 2473 Features["sse4.1"] = true; 2474 case SSSE3: 2475 Features["ssse3"] = true; 2476 case SSE3: 2477 Features["sse3"] = true; 2478 case SSE2: 2479 Features["sse2"] = true; 2480 case SSE1: 2481 Features["sse"] = true; 2482 case NoSSE: 2483 break; 2484 } 2485 return; 2486 } 2487 2488 switch (Level) { 2489 case NoSSE: 2490 case SSE1: 2491 Features["sse"] = false; 2492 case SSE2: 2493 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2494 Features["sha"] = false; 2495 case SSE3: 2496 Features["sse3"] = false; 2497 setXOPLevel(Features, NoXOP, false); 2498 case SSSE3: 2499 Features["ssse3"] = false; 2500 case SSE41: 2501 Features["sse4.1"] = false; 2502 case SSE42: 2503 Features["sse4.2"] = false; 2504 case AVX: 2505 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2506 setXOPLevel(Features, FMA4, false); 2507 case AVX2: 2508 Features["avx2"] = false; 2509 case AVX512F: 2510 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2511 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2512 Features["avx512vl"] = false; 2513 } 2514 } 2515 2516 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2517 MMX3DNowEnum Level, bool Enabled) { 2518 if (Enabled) { 2519 switch (Level) { 2520 case AMD3DNowAthlon: 2521 Features["3dnowa"] = true; 2522 case AMD3DNow: 2523 Features["3dnow"] = true; 2524 case MMX: 2525 Features["mmx"] = true; 2526 case NoMMX3DNow: 2527 break; 2528 } 2529 return; 2530 } 2531 2532 switch (Level) { 2533 case NoMMX3DNow: 2534 case MMX: 2535 Features["mmx"] = false; 2536 case AMD3DNow: 2537 Features["3dnow"] = false; 2538 case AMD3DNowAthlon: 2539 Features["3dnowa"] = false; 2540 } 2541 } 2542 2543 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2544 bool Enabled) { 2545 if (Enabled) { 2546 switch (Level) { 2547 case XOP: 2548 Features["xop"] = true; 2549 case FMA4: 2550 Features["fma4"] = true; 2551 setSSELevel(Features, AVX, true); 2552 case SSE4A: 2553 Features["sse4a"] = true; 2554 setSSELevel(Features, SSE3, true); 2555 case NoXOP: 2556 break; 2557 } 2558 return; 2559 } 2560 2561 switch (Level) { 2562 case NoXOP: 2563 case SSE4A: 2564 Features["sse4a"] = false; 2565 case FMA4: 2566 Features["fma4"] = false; 2567 case XOP: 2568 Features["xop"] = false; 2569 } 2570 } 2571 2572 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2573 StringRef Name, bool Enabled) { 2574 // FIXME: This *really* should not be here. We need some way of translating 2575 // options into llvm subtarget features. 2576 if (Name == "sse4") 2577 Name = "sse4.2"; 2578 2579 Features[Name] = Enabled; 2580 2581 if (Name == "mmx") { 2582 setMMXLevel(Features, MMX, Enabled); 2583 } else if (Name == "sse") { 2584 setSSELevel(Features, SSE1, Enabled); 2585 } else if (Name == "sse2") { 2586 setSSELevel(Features, SSE2, Enabled); 2587 } else if (Name == "sse3") { 2588 setSSELevel(Features, SSE3, Enabled); 2589 } else if (Name == "ssse3") { 2590 setSSELevel(Features, SSSE3, Enabled); 2591 } else if (Name == "sse4.2") { 2592 setSSELevel(Features, SSE42, Enabled); 2593 } else if (Name == "sse4.1") { 2594 setSSELevel(Features, SSE41, Enabled); 2595 } else if (Name == "3dnow") { 2596 setMMXLevel(Features, AMD3DNow, Enabled); 2597 } else if (Name == "3dnowa") { 2598 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2599 } else if (Name == "aes") { 2600 if (Enabled) 2601 setSSELevel(Features, SSE2, Enabled); 2602 } else if (Name == "pclmul") { 2603 if (Enabled) 2604 setSSELevel(Features, SSE2, Enabled); 2605 } else if (Name == "avx") { 2606 setSSELevel(Features, AVX, Enabled); 2607 } else if (Name == "avx2") { 2608 setSSELevel(Features, AVX2, Enabled); 2609 } else if (Name == "avx512f") { 2610 setSSELevel(Features, AVX512F, Enabled); 2611 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2612 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2613 if (Enabled) 2614 setSSELevel(Features, AVX512F, Enabled); 2615 } else if (Name == "fma") { 2616 if (Enabled) 2617 setSSELevel(Features, AVX, Enabled); 2618 } else if (Name == "fma4") { 2619 setXOPLevel(Features, FMA4, Enabled); 2620 } else if (Name == "xop") { 2621 setXOPLevel(Features, XOP, Enabled); 2622 } else if (Name == "sse4a") { 2623 setXOPLevel(Features, SSE4A, Enabled); 2624 } else if (Name == "f16c") { 2625 if (Enabled) 2626 setSSELevel(Features, AVX, Enabled); 2627 } else if (Name == "sha") { 2628 if (Enabled) 2629 setSSELevel(Features, SSE2, Enabled); 2630 } 2631 } 2632 2633 /// handleTargetFeatures - Perform initialization based on the user 2634 /// configured set of features. 2635 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2636 DiagnosticsEngine &Diags) { 2637 // Remember the maximum enabled sselevel. 2638 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2639 // Ignore disabled features. 2640 if (Features[i][0] == '-') 2641 continue; 2642 2643 StringRef Feature = StringRef(Features[i]).substr(1); 2644 2645 if (Feature == "aes") { 2646 HasAES = true; 2647 continue; 2648 } 2649 2650 if (Feature == "pclmul") { 2651 HasPCLMUL = true; 2652 continue; 2653 } 2654 2655 if (Feature == "lzcnt") { 2656 HasLZCNT = true; 2657 continue; 2658 } 2659 2660 if (Feature == "rdrnd") { 2661 HasRDRND = true; 2662 continue; 2663 } 2664 2665 if (Feature == "fsgsbase") { 2666 HasFSGSBASE = true; 2667 continue; 2668 } 2669 2670 if (Feature == "bmi") { 2671 HasBMI = true; 2672 continue; 2673 } 2674 2675 if (Feature == "bmi2") { 2676 HasBMI2 = true; 2677 continue; 2678 } 2679 2680 if (Feature == "popcnt") { 2681 HasPOPCNT = true; 2682 continue; 2683 } 2684 2685 if (Feature == "rtm") { 2686 HasRTM = true; 2687 continue; 2688 } 2689 2690 if (Feature == "prfchw") { 2691 HasPRFCHW = true; 2692 continue; 2693 } 2694 2695 if (Feature == "rdseed") { 2696 HasRDSEED = true; 2697 continue; 2698 } 2699 2700 if (Feature == "adx") { 2701 HasADX = true; 2702 continue; 2703 } 2704 2705 if (Feature == "tbm") { 2706 HasTBM = true; 2707 continue; 2708 } 2709 2710 if (Feature == "fma") { 2711 HasFMA = true; 2712 continue; 2713 } 2714 2715 if (Feature == "f16c") { 2716 HasF16C = true; 2717 continue; 2718 } 2719 2720 if (Feature == "avx512cd") { 2721 HasAVX512CD = true; 2722 continue; 2723 } 2724 2725 if (Feature == "avx512er") { 2726 HasAVX512ER = true; 2727 continue; 2728 } 2729 2730 if (Feature == "avx512pf") { 2731 HasAVX512PF = true; 2732 continue; 2733 } 2734 2735 if (Feature == "avx512dq") { 2736 HasAVX512DQ = true; 2737 continue; 2738 } 2739 2740 if (Feature == "avx512bw") { 2741 HasAVX512BW = true; 2742 continue; 2743 } 2744 2745 if (Feature == "avx512vl") { 2746 HasAVX512VL = true; 2747 continue; 2748 } 2749 2750 if (Feature == "sha") { 2751 HasSHA = true; 2752 continue; 2753 } 2754 2755 if (Feature == "cx16") { 2756 HasCX16 = true; 2757 continue; 2758 } 2759 2760 assert(Features[i][0] == '+' && "Invalid target feature!"); 2761 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2762 .Case("avx512f", AVX512F) 2763 .Case("avx2", AVX2) 2764 .Case("avx", AVX) 2765 .Case("sse4.2", SSE42) 2766 .Case("sse4.1", SSE41) 2767 .Case("ssse3", SSSE3) 2768 .Case("sse3", SSE3) 2769 .Case("sse2", SSE2) 2770 .Case("sse", SSE1) 2771 .Default(NoSSE); 2772 SSELevel = std::max(SSELevel, Level); 2773 2774 MMX3DNowEnum ThreeDNowLevel = 2775 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2776 .Case("3dnowa", AMD3DNowAthlon) 2777 .Case("3dnow", AMD3DNow) 2778 .Case("mmx", MMX) 2779 .Default(NoMMX3DNow); 2780 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2781 2782 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2783 .Case("xop", XOP) 2784 .Case("fma4", FMA4) 2785 .Case("sse4a", SSE4A) 2786 .Default(NoXOP); 2787 XOPLevel = std::max(XOPLevel, XLevel); 2788 } 2789 2790 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2791 // Can't do this earlier because we need to be able to explicitly enable 2792 // popcnt and still disable sse4.2. 2793 if (!HasPOPCNT && SSELevel >= SSE42 && 2794 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2795 HasPOPCNT = true; 2796 Features.push_back("+popcnt"); 2797 } 2798 2799 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2800 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2801 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2802 HasPRFCHW = true; 2803 Features.push_back("+prfchw"); 2804 } 2805 2806 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2807 // matches the selected sse level. 2808 if (FPMath == FP_SSE && SSELevel < SSE1) { 2809 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2810 return false; 2811 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2812 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2813 return false; 2814 } 2815 2816 // Don't tell the backend if we're turning off mmx; it will end up disabling 2817 // SSE, which we don't want. 2818 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2819 // then enable MMX. 2820 std::vector<std::string>::iterator it; 2821 it = std::find(Features.begin(), Features.end(), "-mmx"); 2822 if (it != Features.end()) 2823 Features.erase(it); 2824 else if (SSELevel > NoSSE) 2825 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2826 return true; 2827 } 2828 2829 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2830 /// definitions for this particular subtarget. 2831 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2832 MacroBuilder &Builder) const { 2833 // Target identification. 2834 if (getTriple().getArch() == llvm::Triple::x86_64) { 2835 Builder.defineMacro("__amd64__"); 2836 Builder.defineMacro("__amd64"); 2837 Builder.defineMacro("__x86_64"); 2838 Builder.defineMacro("__x86_64__"); 2839 if (getTriple().getArchName() == "x86_64h") { 2840 Builder.defineMacro("__x86_64h"); 2841 Builder.defineMacro("__x86_64h__"); 2842 } 2843 } else { 2844 DefineStd(Builder, "i386", Opts); 2845 } 2846 2847 // Subtarget options. 2848 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2849 // truly should be based on -mtune options. 2850 switch (CPU) { 2851 case CK_Generic: 2852 break; 2853 case CK_i386: 2854 // The rest are coming from the i386 define above. 2855 Builder.defineMacro("__tune_i386__"); 2856 break; 2857 case CK_i486: 2858 case CK_WinChipC6: 2859 case CK_WinChip2: 2860 case CK_C3: 2861 defineCPUMacros(Builder, "i486"); 2862 break; 2863 case CK_PentiumMMX: 2864 Builder.defineMacro("__pentium_mmx__"); 2865 Builder.defineMacro("__tune_pentium_mmx__"); 2866 // Fallthrough 2867 case CK_i586: 2868 case CK_Pentium: 2869 defineCPUMacros(Builder, "i586"); 2870 defineCPUMacros(Builder, "pentium"); 2871 break; 2872 case CK_Pentium3: 2873 case CK_Pentium3M: 2874 case CK_PentiumM: 2875 Builder.defineMacro("__tune_pentium3__"); 2876 // Fallthrough 2877 case CK_Pentium2: 2878 case CK_C3_2: 2879 Builder.defineMacro("__tune_pentium2__"); 2880 // Fallthrough 2881 case CK_PentiumPro: 2882 Builder.defineMacro("__tune_i686__"); 2883 Builder.defineMacro("__tune_pentiumpro__"); 2884 // Fallthrough 2885 case CK_i686: 2886 Builder.defineMacro("__i686"); 2887 Builder.defineMacro("__i686__"); 2888 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2889 Builder.defineMacro("__pentiumpro"); 2890 Builder.defineMacro("__pentiumpro__"); 2891 break; 2892 case CK_Pentium4: 2893 case CK_Pentium4M: 2894 defineCPUMacros(Builder, "pentium4"); 2895 break; 2896 case CK_Yonah: 2897 case CK_Prescott: 2898 case CK_Nocona: 2899 defineCPUMacros(Builder, "nocona"); 2900 break; 2901 case CK_Core2: 2902 case CK_Penryn: 2903 defineCPUMacros(Builder, "core2"); 2904 break; 2905 case CK_Bonnell: 2906 defineCPUMacros(Builder, "atom"); 2907 break; 2908 case CK_Silvermont: 2909 defineCPUMacros(Builder, "slm"); 2910 break; 2911 case CK_Nehalem: 2912 case CK_Westmere: 2913 case CK_SandyBridge: 2914 case CK_IvyBridge: 2915 case CK_Haswell: 2916 case CK_Broadwell: 2917 // FIXME: Historically, we defined this legacy name, it would be nice to 2918 // remove it at some point. We've never exposed fine-grained names for 2919 // recent primary x86 CPUs, and we should keep it that way. 2920 defineCPUMacros(Builder, "corei7"); 2921 break; 2922 case CK_Skylake: 2923 // FIXME: Historically, we defined this legacy name, it would be nice to 2924 // remove it at some point. This is the only fine-grained CPU macro in the 2925 // main intel CPU line, and it would be better to not have these and force 2926 // people to use ISA macros. 2927 defineCPUMacros(Builder, "skx"); 2928 break; 2929 case CK_KNL: 2930 defineCPUMacros(Builder, "knl"); 2931 break; 2932 case CK_K6_2: 2933 Builder.defineMacro("__k6_2__"); 2934 Builder.defineMacro("__tune_k6_2__"); 2935 // Fallthrough 2936 case CK_K6_3: 2937 if (CPU != CK_K6_2) { // In case of fallthrough 2938 // FIXME: GCC may be enabling these in cases where some other k6 2939 // architecture is specified but -m3dnow is explicitly provided. The 2940 // exact semantics need to be determined and emulated here. 2941 Builder.defineMacro("__k6_3__"); 2942 Builder.defineMacro("__tune_k6_3__"); 2943 } 2944 // Fallthrough 2945 case CK_K6: 2946 defineCPUMacros(Builder, "k6"); 2947 break; 2948 case CK_Athlon: 2949 case CK_AthlonThunderbird: 2950 case CK_Athlon4: 2951 case CK_AthlonXP: 2952 case CK_AthlonMP: 2953 defineCPUMacros(Builder, "athlon"); 2954 if (SSELevel != NoSSE) { 2955 Builder.defineMacro("__athlon_sse__"); 2956 Builder.defineMacro("__tune_athlon_sse__"); 2957 } 2958 break; 2959 case CK_K8: 2960 case CK_K8SSE3: 2961 case CK_x86_64: 2962 case CK_Opteron: 2963 case CK_OpteronSSE3: 2964 case CK_Athlon64: 2965 case CK_Athlon64SSE3: 2966 case CK_AthlonFX: 2967 defineCPUMacros(Builder, "k8"); 2968 break; 2969 case CK_AMDFAM10: 2970 defineCPUMacros(Builder, "amdfam10"); 2971 break; 2972 case CK_BTVER1: 2973 defineCPUMacros(Builder, "btver1"); 2974 break; 2975 case CK_BTVER2: 2976 defineCPUMacros(Builder, "btver2"); 2977 break; 2978 case CK_BDVER1: 2979 defineCPUMacros(Builder, "bdver1"); 2980 break; 2981 case CK_BDVER2: 2982 defineCPUMacros(Builder, "bdver2"); 2983 break; 2984 case CK_BDVER3: 2985 defineCPUMacros(Builder, "bdver3"); 2986 break; 2987 case CK_BDVER4: 2988 defineCPUMacros(Builder, "bdver4"); 2989 break; 2990 case CK_Geode: 2991 defineCPUMacros(Builder, "geode"); 2992 break; 2993 } 2994 2995 // Target properties. 2996 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2997 2998 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2999 // functions in glibc header files that use FP Stack inline asm which the 3000 // backend can't deal with (PR879). 3001 Builder.defineMacro("__NO_MATH_INLINES"); 3002 3003 if (HasAES) 3004 Builder.defineMacro("__AES__"); 3005 3006 if (HasPCLMUL) 3007 Builder.defineMacro("__PCLMUL__"); 3008 3009 if (HasLZCNT) 3010 Builder.defineMacro("__LZCNT__"); 3011 3012 if (HasRDRND) 3013 Builder.defineMacro("__RDRND__"); 3014 3015 if (HasFSGSBASE) 3016 Builder.defineMacro("__FSGSBASE__"); 3017 3018 if (HasBMI) 3019 Builder.defineMacro("__BMI__"); 3020 3021 if (HasBMI2) 3022 Builder.defineMacro("__BMI2__"); 3023 3024 if (HasPOPCNT) 3025 Builder.defineMacro("__POPCNT__"); 3026 3027 if (HasRTM) 3028 Builder.defineMacro("__RTM__"); 3029 3030 if (HasPRFCHW) 3031 Builder.defineMacro("__PRFCHW__"); 3032 3033 if (HasRDSEED) 3034 Builder.defineMacro("__RDSEED__"); 3035 3036 if (HasADX) 3037 Builder.defineMacro("__ADX__"); 3038 3039 if (HasTBM) 3040 Builder.defineMacro("__TBM__"); 3041 3042 switch (XOPLevel) { 3043 case XOP: 3044 Builder.defineMacro("__XOP__"); 3045 case FMA4: 3046 Builder.defineMacro("__FMA4__"); 3047 case SSE4A: 3048 Builder.defineMacro("__SSE4A__"); 3049 case NoXOP: 3050 break; 3051 } 3052 3053 if (HasFMA) 3054 Builder.defineMacro("__FMA__"); 3055 3056 if (HasF16C) 3057 Builder.defineMacro("__F16C__"); 3058 3059 if (HasAVX512CD) 3060 Builder.defineMacro("__AVX512CD__"); 3061 if (HasAVX512ER) 3062 Builder.defineMacro("__AVX512ER__"); 3063 if (HasAVX512PF) 3064 Builder.defineMacro("__AVX512PF__"); 3065 if (HasAVX512DQ) 3066 Builder.defineMacro("__AVX512DQ__"); 3067 if (HasAVX512BW) 3068 Builder.defineMacro("__AVX512BW__"); 3069 if (HasAVX512VL) 3070 Builder.defineMacro("__AVX512VL__"); 3071 3072 if (HasSHA) 3073 Builder.defineMacro("__SHA__"); 3074 3075 if (HasCX16) 3076 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3077 3078 // Each case falls through to the previous one here. 3079 switch (SSELevel) { 3080 case AVX512F: 3081 Builder.defineMacro("__AVX512F__"); 3082 case AVX2: 3083 Builder.defineMacro("__AVX2__"); 3084 case AVX: 3085 Builder.defineMacro("__AVX__"); 3086 case SSE42: 3087 Builder.defineMacro("__SSE4_2__"); 3088 case SSE41: 3089 Builder.defineMacro("__SSE4_1__"); 3090 case SSSE3: 3091 Builder.defineMacro("__SSSE3__"); 3092 case SSE3: 3093 Builder.defineMacro("__SSE3__"); 3094 case SSE2: 3095 Builder.defineMacro("__SSE2__"); 3096 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3097 case SSE1: 3098 Builder.defineMacro("__SSE__"); 3099 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3100 case NoSSE: 3101 break; 3102 } 3103 3104 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3105 switch (SSELevel) { 3106 case AVX512F: 3107 case AVX2: 3108 case AVX: 3109 case SSE42: 3110 case SSE41: 3111 case SSSE3: 3112 case SSE3: 3113 case SSE2: 3114 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3115 break; 3116 case SSE1: 3117 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3118 break; 3119 default: 3120 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3121 } 3122 } 3123 3124 // Each case falls through to the previous one here. 3125 switch (MMX3DNowLevel) { 3126 case AMD3DNowAthlon: 3127 Builder.defineMacro("__3dNOW_A__"); 3128 case AMD3DNow: 3129 Builder.defineMacro("__3dNOW__"); 3130 case MMX: 3131 Builder.defineMacro("__MMX__"); 3132 case NoMMX3DNow: 3133 break; 3134 } 3135 3136 if (CPU >= CK_i486) { 3137 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3138 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3139 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3140 } 3141 if (CPU >= CK_i586) 3142 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3143 } 3144 3145 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3146 return llvm::StringSwitch<bool>(Feature) 3147 .Case("aes", HasAES) 3148 .Case("avx", SSELevel >= AVX) 3149 .Case("avx2", SSELevel >= AVX2) 3150 .Case("avx512f", SSELevel >= AVX512F) 3151 .Case("avx512cd", HasAVX512CD) 3152 .Case("avx512er", HasAVX512ER) 3153 .Case("avx512pf", HasAVX512PF) 3154 .Case("avx512dq", HasAVX512DQ) 3155 .Case("avx512bw", HasAVX512BW) 3156 .Case("avx512vl", HasAVX512VL) 3157 .Case("bmi", HasBMI) 3158 .Case("bmi2", HasBMI2) 3159 .Case("cx16", HasCX16) 3160 .Case("f16c", HasF16C) 3161 .Case("fma", HasFMA) 3162 .Case("fma4", XOPLevel >= FMA4) 3163 .Case("fsgsbase", HasFSGSBASE) 3164 .Case("lzcnt", HasLZCNT) 3165 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3166 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3167 .Case("mmx", MMX3DNowLevel >= MMX) 3168 .Case("pclmul", HasPCLMUL) 3169 .Case("popcnt", HasPOPCNT) 3170 .Case("prfchw", HasPRFCHW) 3171 .Case("rdrnd", HasRDRND) 3172 .Case("rdseed", HasRDSEED) 3173 .Case("rtm", HasRTM) 3174 .Case("sha", HasSHA) 3175 .Case("sse", SSELevel >= SSE1) 3176 .Case("sse2", SSELevel >= SSE2) 3177 .Case("sse3", SSELevel >= SSE3) 3178 .Case("ssse3", SSELevel >= SSSE3) 3179 .Case("sse4.1", SSELevel >= SSE41) 3180 .Case("sse4.2", SSELevel >= SSE42) 3181 .Case("sse4a", XOPLevel >= SSE4A) 3182 .Case("tbm", HasTBM) 3183 .Case("x86", true) 3184 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3185 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3186 .Case("xop", XOPLevel >= XOP) 3187 .Default(false); 3188 } 3189 3190 bool 3191 X86TargetInfo::validateAsmConstraint(const char *&Name, 3192 TargetInfo::ConstraintInfo &Info) const { 3193 switch (*Name) { 3194 default: return false; 3195 case 'I': 3196 Info.setRequiresImmediate(0, 31); 3197 return true; 3198 case 'J': 3199 Info.setRequiresImmediate(0, 63); 3200 return true; 3201 case 'K': 3202 Info.setRequiresImmediate(-128, 127); 3203 return true; 3204 case 'L': 3205 // FIXME: properly analyze this constraint: 3206 // must be one of 0xff, 0xffff, or 0xffffffff 3207 return true; 3208 case 'M': 3209 Info.setRequiresImmediate(0, 3); 3210 return true; 3211 case 'N': 3212 Info.setRequiresImmediate(0, 255); 3213 return true; 3214 case 'O': 3215 Info.setRequiresImmediate(0, 127); 3216 return true; 3217 case 'Y': // first letter of a pair: 3218 switch (*(Name+1)) { 3219 default: return false; 3220 case '0': // First SSE register. 3221 case 't': // Any SSE register, when SSE2 is enabled. 3222 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3223 case 'm': // any MMX register, when inter-unit moves enabled. 3224 break; // falls through to setAllowsRegister. 3225 } 3226 case 'f': // any x87 floating point stack register. 3227 // Constraint 'f' cannot be used for output operands. 3228 if (Info.ConstraintStr[0] == '=') 3229 return false; 3230 3231 Info.setAllowsRegister(); 3232 return true; 3233 case 'a': // eax. 3234 case 'b': // ebx. 3235 case 'c': // ecx. 3236 case 'd': // edx. 3237 case 'S': // esi. 3238 case 'D': // edi. 3239 case 'A': // edx:eax. 3240 case 't': // top of floating point stack. 3241 case 'u': // second from top of floating point stack. 3242 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3243 case 'y': // Any MMX register. 3244 case 'x': // Any SSE register. 3245 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3246 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3247 case 'l': // "Index" registers: any general register that can be used as an 3248 // index in a base+index memory access. 3249 Info.setAllowsRegister(); 3250 return true; 3251 case 'C': // SSE floating point constant. 3252 case 'G': // x87 floating point constant. 3253 case 'e': // 32-bit signed integer constant for use with zero-extending 3254 // x86_64 instructions. 3255 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3256 // x86_64 instructions. 3257 return true; 3258 } 3259 } 3260 3261 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3262 unsigned Size) const { 3263 // Strip off constraint modifiers. 3264 while (Constraint[0] == '=' || 3265 Constraint[0] == '+' || 3266 Constraint[0] == '&') 3267 Constraint = Constraint.substr(1); 3268 3269 return validateOperandSize(Constraint, Size); 3270 } 3271 3272 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3273 unsigned Size) const { 3274 return validateOperandSize(Constraint, Size); 3275 } 3276 3277 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3278 unsigned Size) const { 3279 switch (Constraint[0]) { 3280 default: break; 3281 case 'y': 3282 return Size <= 64; 3283 case 'f': 3284 case 't': 3285 case 'u': 3286 return Size <= 128; 3287 case 'x': 3288 // 256-bit ymm registers can be used if target supports AVX. 3289 return Size <= (SSELevel >= AVX ? 256U : 128U); 3290 } 3291 3292 return true; 3293 } 3294 3295 std::string 3296 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3297 switch (*Constraint) { 3298 case 'a': return std::string("{ax}"); 3299 case 'b': return std::string("{bx}"); 3300 case 'c': return std::string("{cx}"); 3301 case 'd': return std::string("{dx}"); 3302 case 'S': return std::string("{si}"); 3303 case 'D': return std::string("{di}"); 3304 case 'p': // address 3305 return std::string("im"); 3306 case 't': // top of floating point stack. 3307 return std::string("{st}"); 3308 case 'u': // second from top of floating point stack. 3309 return std::string("{st(1)}"); // second from top of floating point stack. 3310 default: 3311 return std::string(1, *Constraint); 3312 } 3313 } 3314 3315 // X86-32 generic target 3316 class X86_32TargetInfo : public X86TargetInfo { 3317 public: 3318 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3319 DoubleAlign = LongLongAlign = 32; 3320 LongDoubleWidth = 96; 3321 LongDoubleAlign = 32; 3322 SuitableAlign = 128; 3323 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3324 SizeType = UnsignedInt; 3325 PtrDiffType = SignedInt; 3326 IntPtrType = SignedInt; 3327 RegParmMax = 3; 3328 3329 // Use fpret for all types. 3330 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3331 (1 << TargetInfo::Double) | 3332 (1 << TargetInfo::LongDouble)); 3333 3334 // x86-32 has atomics up to 8 bytes 3335 // FIXME: Check that we actually have cmpxchg8b before setting 3336 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3337 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3338 } 3339 BuiltinVaListKind getBuiltinVaListKind() const override { 3340 return TargetInfo::CharPtrBuiltinVaList; 3341 } 3342 3343 int getEHDataRegisterNumber(unsigned RegNo) const override { 3344 if (RegNo == 0) return 0; 3345 if (RegNo == 1) return 2; 3346 return -1; 3347 } 3348 bool validateOperandSize(StringRef Constraint, 3349 unsigned Size) const override { 3350 switch (Constraint[0]) { 3351 default: break; 3352 case 'R': 3353 case 'q': 3354 case 'Q': 3355 case 'a': 3356 case 'b': 3357 case 'c': 3358 case 'd': 3359 case 'S': 3360 case 'D': 3361 return Size <= 32; 3362 case 'A': 3363 return Size <= 64; 3364 } 3365 3366 return X86TargetInfo::validateOperandSize(Constraint, Size); 3367 } 3368 }; 3369 3370 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3371 public: 3372 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3373 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3374 3375 unsigned getFloatEvalMethod() const override { 3376 unsigned Major, Minor, Micro; 3377 getTriple().getOSVersion(Major, Minor, Micro); 3378 // New NetBSD uses the default rounding mode. 3379 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3380 return X86_32TargetInfo::getFloatEvalMethod(); 3381 // NetBSD before 6.99.26 defaults to "double" rounding. 3382 return 1; 3383 } 3384 }; 3385 3386 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3387 public: 3388 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3389 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3390 SizeType = UnsignedLong; 3391 IntPtrType = SignedLong; 3392 PtrDiffType = SignedLong; 3393 } 3394 }; 3395 3396 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3397 public: 3398 BitrigI386TargetInfo(const llvm::Triple &Triple) 3399 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3400 SizeType = UnsignedLong; 3401 IntPtrType = SignedLong; 3402 PtrDiffType = SignedLong; 3403 } 3404 }; 3405 3406 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3407 public: 3408 DarwinI386TargetInfo(const llvm::Triple &Triple) 3409 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3410 LongDoubleWidth = 128; 3411 LongDoubleAlign = 128; 3412 SuitableAlign = 128; 3413 MaxVectorAlign = 256; 3414 SizeType = UnsignedLong; 3415 IntPtrType = SignedLong; 3416 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3417 HasAlignMac68kSupport = true; 3418 } 3419 3420 }; 3421 3422 // x86-32 Windows target 3423 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3424 public: 3425 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3426 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3427 WCharType = UnsignedShort; 3428 DoubleAlign = LongLongAlign = 64; 3429 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3430 } 3431 void getTargetDefines(const LangOptions &Opts, 3432 MacroBuilder &Builder) const override { 3433 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3434 } 3435 }; 3436 3437 // x86-32 Windows Visual Studio target 3438 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3439 public: 3440 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3441 : WindowsX86_32TargetInfo(Triple) { 3442 LongDoubleWidth = LongDoubleAlign = 64; 3443 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3444 } 3445 void getTargetDefines(const LangOptions &Opts, 3446 MacroBuilder &Builder) const override { 3447 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3448 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3449 // The value of the following reflects processor type. 3450 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3451 // We lost the original triple, so we use the default. 3452 Builder.defineMacro("_M_IX86", "600"); 3453 } 3454 }; 3455 } // end anonymous namespace 3456 3457 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3458 Builder.defineMacro("__MSVCRT__"); 3459 Builder.defineMacro("__MINGW32__"); 3460 3461 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3462 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3463 // macro anyway for pre-processor compatibility. 3464 if (Opts.MicrosoftExt) 3465 Builder.defineMacro("__declspec", "__declspec"); 3466 else 3467 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3468 3469 if (!Opts.MicrosoftExt) { 3470 // Provide macros for all the calling convention keywords. Provide both 3471 // single and double underscore prefixed variants. These are available on 3472 // x64 as well as x86, even though they have no effect. 3473 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3474 for (const char *CC : CCs) { 3475 std::string GCCSpelling = "__attribute__((__"; 3476 GCCSpelling += CC; 3477 GCCSpelling += "__))"; 3478 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3479 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3480 } 3481 } 3482 } 3483 3484 namespace { 3485 // x86-32 MinGW target 3486 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3487 public: 3488 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3489 : WindowsX86_32TargetInfo(Triple) {} 3490 void getTargetDefines(const LangOptions &Opts, 3491 MacroBuilder &Builder) const override { 3492 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3493 DefineStd(Builder, "WIN32", Opts); 3494 DefineStd(Builder, "WINNT", Opts); 3495 Builder.defineMacro("_X86_"); 3496 addMinGWDefines(Opts, Builder); 3497 } 3498 }; 3499 3500 // x86-32 Cygwin target 3501 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3502 public: 3503 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3504 : X86_32TargetInfo(Triple) { 3505 TLSSupported = false; 3506 WCharType = UnsignedShort; 3507 DoubleAlign = LongLongAlign = 64; 3508 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3509 } 3510 void getTargetDefines(const LangOptions &Opts, 3511 MacroBuilder &Builder) const override { 3512 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3513 Builder.defineMacro("_X86_"); 3514 Builder.defineMacro("__CYGWIN__"); 3515 Builder.defineMacro("__CYGWIN32__"); 3516 DefineStd(Builder, "unix", Opts); 3517 if (Opts.CPlusPlus) 3518 Builder.defineMacro("_GNU_SOURCE"); 3519 } 3520 }; 3521 3522 // x86-32 Haiku target 3523 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3524 public: 3525 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3526 SizeType = UnsignedLong; 3527 IntPtrType = SignedLong; 3528 PtrDiffType = SignedLong; 3529 ProcessIDType = SignedLong; 3530 this->UserLabelPrefix = ""; 3531 this->TLSSupported = false; 3532 } 3533 void getTargetDefines(const LangOptions &Opts, 3534 MacroBuilder &Builder) const override { 3535 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3536 Builder.defineMacro("__INTEL__"); 3537 Builder.defineMacro("__HAIKU__"); 3538 } 3539 }; 3540 3541 // RTEMS Target 3542 template<typename Target> 3543 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3544 protected: 3545 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3546 MacroBuilder &Builder) const override { 3547 // RTEMS defines; list based off of gcc output 3548 3549 Builder.defineMacro("__rtems__"); 3550 Builder.defineMacro("__ELF__"); 3551 } 3552 3553 public: 3554 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3555 this->UserLabelPrefix = ""; 3556 3557 switch (Triple.getArch()) { 3558 default: 3559 case llvm::Triple::x86: 3560 // this->MCountName = ".mcount"; 3561 break; 3562 case llvm::Triple::mips: 3563 case llvm::Triple::mipsel: 3564 case llvm::Triple::ppc: 3565 case llvm::Triple::ppc64: 3566 case llvm::Triple::ppc64le: 3567 // this->MCountName = "_mcount"; 3568 break; 3569 case llvm::Triple::arm: 3570 // this->MCountName = "__mcount"; 3571 break; 3572 } 3573 } 3574 }; 3575 3576 // x86-32 RTEMS target 3577 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3578 public: 3579 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3580 SizeType = UnsignedLong; 3581 IntPtrType = SignedLong; 3582 PtrDiffType = SignedLong; 3583 this->UserLabelPrefix = ""; 3584 } 3585 void getTargetDefines(const LangOptions &Opts, 3586 MacroBuilder &Builder) const override { 3587 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3588 Builder.defineMacro("__INTEL__"); 3589 Builder.defineMacro("__rtems__"); 3590 } 3591 }; 3592 3593 // x86-64 generic target 3594 class X86_64TargetInfo : public X86TargetInfo { 3595 public: 3596 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3597 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3598 bool IsWinCOFF = 3599 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3600 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3601 LongDoubleWidth = 128; 3602 LongDoubleAlign = 128; 3603 LargeArrayMinWidth = 128; 3604 LargeArrayAlign = 128; 3605 SuitableAlign = 128; 3606 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3607 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3608 IntPtrType = IsX32 ? SignedInt : SignedLong; 3609 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3610 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3611 RegParmMax = 6; 3612 3613 // Pointers are 32-bit in x32. 3614 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3615 : IsWinCOFF 3616 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3617 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3618 3619 // Use fpret only for long double. 3620 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3621 3622 // Use fp2ret for _Complex long double. 3623 ComplexLongDoubleUsesFP2Ret = true; 3624 3625 // x86-64 has atomics up to 16 bytes. 3626 MaxAtomicPromoteWidth = 128; 3627 MaxAtomicInlineWidth = 128; 3628 } 3629 BuiltinVaListKind getBuiltinVaListKind() const override { 3630 return TargetInfo::X86_64ABIBuiltinVaList; 3631 } 3632 3633 int getEHDataRegisterNumber(unsigned RegNo) const override { 3634 if (RegNo == 0) return 0; 3635 if (RegNo == 1) return 1; 3636 return -1; 3637 } 3638 3639 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3640 return (CC == CC_C || 3641 CC == CC_X86VectorCall || 3642 CC == CC_IntelOclBicc || 3643 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3644 } 3645 3646 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3647 return CC_C; 3648 } 3649 3650 // for x32 we need it here explicitly 3651 bool hasInt128Type() const override { return true; } 3652 }; 3653 3654 // x86-64 Windows target 3655 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3656 public: 3657 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3658 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3659 WCharType = UnsignedShort; 3660 LongWidth = LongAlign = 32; 3661 DoubleAlign = LongLongAlign = 64; 3662 IntMaxType = SignedLongLong; 3663 Int64Type = SignedLongLong; 3664 SizeType = UnsignedLongLong; 3665 PtrDiffType = SignedLongLong; 3666 IntPtrType = SignedLongLong; 3667 this->UserLabelPrefix = ""; 3668 } 3669 3670 void getTargetDefines(const LangOptions &Opts, 3671 MacroBuilder &Builder) const override { 3672 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3673 Builder.defineMacro("_WIN64"); 3674 } 3675 3676 BuiltinVaListKind getBuiltinVaListKind() const override { 3677 return TargetInfo::CharPtrBuiltinVaList; 3678 } 3679 3680 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3681 switch (CC) { 3682 case CC_X86StdCall: 3683 case CC_X86ThisCall: 3684 case CC_X86FastCall: 3685 return CCCR_Ignore; 3686 case CC_C: 3687 case CC_X86VectorCall: 3688 case CC_IntelOclBicc: 3689 case CC_X86_64SysV: 3690 return CCCR_OK; 3691 default: 3692 return CCCR_Warning; 3693 } 3694 } 3695 }; 3696 3697 // x86-64 Windows Visual Studio target 3698 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3699 public: 3700 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3701 : WindowsX86_64TargetInfo(Triple) { 3702 LongDoubleWidth = LongDoubleAlign = 64; 3703 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3704 } 3705 void getTargetDefines(const LangOptions &Opts, 3706 MacroBuilder &Builder) const override { 3707 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3708 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3709 Builder.defineMacro("_M_X64"); 3710 Builder.defineMacro("_M_AMD64"); 3711 } 3712 }; 3713 3714 // x86-64 MinGW target 3715 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3716 public: 3717 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3718 : WindowsX86_64TargetInfo(Triple) {} 3719 void getTargetDefines(const LangOptions &Opts, 3720 MacroBuilder &Builder) const override { 3721 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3722 DefineStd(Builder, "WIN64", Opts); 3723 Builder.defineMacro("__MINGW64__"); 3724 addMinGWDefines(Opts, Builder); 3725 3726 // GCC defines this macro when it is using __gxx_personality_seh0. 3727 if (!Opts.SjLjExceptions) 3728 Builder.defineMacro("__SEH__"); 3729 } 3730 }; 3731 3732 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3733 public: 3734 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3735 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3736 Int64Type = SignedLongLong; 3737 MaxVectorAlign = 256; 3738 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3739 llvm::Triple T = llvm::Triple(Triple); 3740 if (T.isiOS()) 3741 UseSignedCharForObjCBool = false; 3742 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3743 } 3744 }; 3745 3746 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3747 public: 3748 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3749 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3750 IntMaxType = SignedLongLong; 3751 Int64Type = SignedLongLong; 3752 } 3753 }; 3754 3755 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3756 public: 3757 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3758 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3759 IntMaxType = SignedLongLong; 3760 Int64Type = SignedLongLong; 3761 } 3762 }; 3763 3764 class ARMTargetInfo : public TargetInfo { 3765 // Possible FPU choices. 3766 enum FPUMode { 3767 VFP2FPU = (1 << 0), 3768 VFP3FPU = (1 << 1), 3769 VFP4FPU = (1 << 2), 3770 NeonFPU = (1 << 3), 3771 FPARMV8 = (1 << 4) 3772 }; 3773 3774 // Possible HWDiv features. 3775 enum HWDivMode { 3776 HWDivThumb = (1 << 0), 3777 HWDivARM = (1 << 1) 3778 }; 3779 3780 static bool FPUModeIsVFP(FPUMode Mode) { 3781 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3782 } 3783 3784 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3785 static const char * const GCCRegNames[]; 3786 3787 std::string ABI, CPU; 3788 3789 enum { 3790 FP_Default, 3791 FP_VFP, 3792 FP_Neon 3793 } FPMath; 3794 3795 unsigned FPU : 5; 3796 3797 unsigned IsAAPCS : 1; 3798 unsigned IsThumb : 1; 3799 unsigned HWDiv : 2; 3800 3801 // Initialized via features. 3802 unsigned SoftFloat : 1; 3803 unsigned SoftFloatABI : 1; 3804 3805 unsigned CRC : 1; 3806 unsigned Crypto : 1; 3807 3808 // ACLE 6.5.1 Hardware floating point 3809 enum { 3810 HW_FP_HP = (1 << 1), /// half (16-bit) 3811 HW_FP_SP = (1 << 2), /// single (32-bit) 3812 HW_FP_DP = (1 << 3), /// double (64-bit) 3813 }; 3814 uint32_t HW_FP; 3815 3816 static const Builtin::Info BuiltinInfo[]; 3817 3818 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3819 StringRef ArchName = T.getArchName(); 3820 if (T.getArch() == llvm::Triple::arm || 3821 T.getArch() == llvm::Triple::armeb) { 3822 StringRef VersionStr; 3823 if (ArchName.startswith("armv")) 3824 VersionStr = ArchName.substr(4, 1); 3825 else if (ArchName.startswith("armebv")) 3826 VersionStr = ArchName.substr(6, 1); 3827 else 3828 return false; 3829 unsigned Version; 3830 if (VersionStr.getAsInteger(10, Version)) 3831 return false; 3832 return Version >= 6; 3833 } 3834 assert(T.getArch() == llvm::Triple::thumb || 3835 T.getArch() == llvm::Triple::thumbeb); 3836 StringRef VersionStr; 3837 if (ArchName.startswith("thumbv")) 3838 VersionStr = ArchName.substr(6, 1); 3839 else if (ArchName.startswith("thumbebv")) 3840 VersionStr = ArchName.substr(8, 1); 3841 else 3842 return false; 3843 unsigned Version; 3844 if (VersionStr.getAsInteger(10, Version)) 3845 return false; 3846 return Version >= 7; 3847 } 3848 3849 void setABIAAPCS() { 3850 IsAAPCS = true; 3851 3852 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3853 const llvm::Triple &T = getTriple(); 3854 3855 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 3856 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 3857 T.getOS() == llvm::Triple::Bitrig) 3858 SizeType = UnsignedLong; 3859 else 3860 SizeType = UnsignedInt; 3861 3862 switch (T.getOS()) { 3863 case llvm::Triple::NetBSD: 3864 WCharType = SignedInt; 3865 break; 3866 case llvm::Triple::Win32: 3867 WCharType = UnsignedShort; 3868 break; 3869 case llvm::Triple::Linux: 3870 default: 3871 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3872 WCharType = UnsignedInt; 3873 break; 3874 } 3875 3876 UseBitFieldTypeAlignment = true; 3877 3878 ZeroLengthBitfieldBoundary = 0; 3879 3880 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3881 // so set preferred for small types to 32. 3882 if (T.isOSBinFormatMachO()) { 3883 DescriptionString = 3884 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3885 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3886 } else if (T.isOSWindows()) { 3887 assert(!BigEndian && "Windows on ARM does not support big endian"); 3888 DescriptionString = "e" 3889 "-m:w" 3890 "-p:32:32" 3891 "-i64:64" 3892 "-v128:64:128" 3893 "-a:0:32" 3894 "-n32" 3895 "-S64"; 3896 } else { 3897 DescriptionString = 3898 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3899 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3900 } 3901 3902 // FIXME: Enumerated types are variable width in straight AAPCS. 3903 } 3904 3905 void setABIAPCS() { 3906 const llvm::Triple &T = getTriple(); 3907 3908 IsAAPCS = false; 3909 3910 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3911 3912 // size_t is unsigned int on FreeBSD. 3913 if (T.getOS() == llvm::Triple::FreeBSD) 3914 SizeType = UnsignedInt; 3915 else 3916 SizeType = UnsignedLong; 3917 3918 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3919 WCharType = SignedInt; 3920 3921 // Do not respect the alignment of bit-field types when laying out 3922 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3923 UseBitFieldTypeAlignment = false; 3924 3925 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3926 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3927 /// gcc. 3928 ZeroLengthBitfieldBoundary = 32; 3929 3930 if (T.isOSBinFormatMachO()) 3931 DescriptionString = 3932 BigEndian 3933 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3934 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3935 else 3936 DescriptionString = 3937 BigEndian 3938 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3939 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3940 3941 // FIXME: Override "preferred align" for double and long long. 3942 } 3943 3944 public: 3945 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3946 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3947 IsAAPCS(true), HW_FP(0) { 3948 BigEndian = IsBigEndian; 3949 3950 switch (getTriple().getOS()) { 3951 case llvm::Triple::NetBSD: 3952 PtrDiffType = SignedLong; 3953 break; 3954 default: 3955 PtrDiffType = SignedInt; 3956 break; 3957 } 3958 3959 // {} in inline assembly are neon specifiers, not assembly variant 3960 // specifiers. 3961 NoAsmVariants = true; 3962 3963 // FIXME: Should we just treat this as a feature? 3964 IsThumb = getTriple().getArchName().startswith("thumb"); 3965 3966 // FIXME: This duplicates code from the driver that sets the -target-abi 3967 // option - this code is used if -target-abi isn't passed and should 3968 // be unified in some way. 3969 if (Triple.isOSBinFormatMachO()) { 3970 // The backend is hardwired to assume AAPCS for M-class processors, ensure 3971 // the frontend matches that. 3972 if (Triple.getEnvironment() == llvm::Triple::EABI || 3973 Triple.getOS() == llvm::Triple::UnknownOS || 3974 StringRef(CPU).startswith("cortex-m")) { 3975 setABI("aapcs"); 3976 } else { 3977 setABI("apcs-gnu"); 3978 } 3979 } else if (Triple.isOSWindows()) { 3980 // FIXME: this is invalid for WindowsCE 3981 setABI("aapcs"); 3982 } else { 3983 // Select the default based on the platform. 3984 switch (Triple.getEnvironment()) { 3985 case llvm::Triple::Android: 3986 case llvm::Triple::GNUEABI: 3987 case llvm::Triple::GNUEABIHF: 3988 setABI("aapcs-linux"); 3989 break; 3990 case llvm::Triple::EABIHF: 3991 case llvm::Triple::EABI: 3992 setABI("aapcs"); 3993 break; 3994 case llvm::Triple::GNU: 3995 setABI("apcs-gnu"); 3996 break; 3997 default: 3998 if (Triple.getOS() == llvm::Triple::NetBSD) 3999 setABI("apcs-gnu"); 4000 else 4001 setABI("aapcs"); 4002 break; 4003 } 4004 } 4005 4006 // ARM targets default to using the ARM C++ ABI. 4007 TheCXXABI.set(TargetCXXABI::GenericARM); 4008 4009 // ARM has atomics up to 8 bytes 4010 MaxAtomicPromoteWidth = 64; 4011 if (shouldUseInlineAtomic(getTriple())) 4012 MaxAtomicInlineWidth = 64; 4013 4014 // Do force alignment of members that follow zero length bitfields. If 4015 // the alignment of the zero-length bitfield is greater than the member 4016 // that follows it, `bar', `bar' will be aligned as the type of the 4017 // zero length bitfield. 4018 UseZeroLengthBitfieldAlignment = true; 4019 } 4020 StringRef getABI() const override { return ABI; } 4021 bool setABI(const std::string &Name) override { 4022 ABI = Name; 4023 4024 // The defaults (above) are for AAPCS, check if we need to change them. 4025 // 4026 // FIXME: We need support for -meabi... we could just mangle it into the 4027 // name. 4028 if (Name == "apcs-gnu") { 4029 setABIAPCS(); 4030 return true; 4031 } 4032 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4033 setABIAAPCS(); 4034 return true; 4035 } 4036 return false; 4037 } 4038 4039 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4040 StringRef ArchName = getTriple().getArchName(); 4041 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4042 Features["vfp2"] = true; 4043 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4044 Features["vfp3"] = true; 4045 Features["neon"] = true; 4046 } 4047 else if (CPU == "cortex-a5") { 4048 Features["vfp4"] = true; 4049 Features["neon"] = true; 4050 } else if (CPU == "swift" || CPU == "cortex-a7" || 4051 CPU == "cortex-a12" || CPU == "cortex-a15" || 4052 CPU == "cortex-a17" || CPU == "krait") { 4053 Features["vfp4"] = true; 4054 Features["neon"] = true; 4055 Features["hwdiv"] = true; 4056 Features["hwdiv-arm"] = true; 4057 } else if (CPU == "cyclone") { 4058 Features["v8fp"] = true; 4059 Features["neon"] = true; 4060 Features["hwdiv"] = true; 4061 Features["hwdiv-arm"] = true; 4062 } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") { 4063 Features["fp-armv8"] = true; 4064 Features["neon"] = true; 4065 Features["hwdiv"] = true; 4066 Features["hwdiv-arm"] = true; 4067 Features["crc"] = true; 4068 Features["crypto"] = true; 4069 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4070 // Enable the hwdiv extension for all v8a AArch32 cores by 4071 // default. 4072 ArchName == "armv8a" || ArchName == "armv8" || 4073 ArchName == "armebv8a" || ArchName == "armebv8" || 4074 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4075 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4076 Features["hwdiv"] = true; 4077 Features["hwdiv-arm"] = true; 4078 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4079 CPU == "sc300") { 4080 Features["hwdiv"] = true; 4081 } 4082 } 4083 4084 bool handleTargetFeatures(std::vector<std::string> &Features, 4085 DiagnosticsEngine &Diags) override { 4086 FPU = 0; 4087 CRC = 0; 4088 Crypto = 0; 4089 SoftFloat = SoftFloatABI = false; 4090 HWDiv = 0; 4091 4092 for (const auto &Feature : Features) { 4093 if (Feature == "+soft-float") { 4094 SoftFloat = true; 4095 } else if (Feature == "+soft-float-abi") { 4096 SoftFloatABI = true; 4097 } else if (Feature == "+vfp2") { 4098 FPU |= VFP2FPU; 4099 HW_FP = HW_FP_SP | HW_FP_DP; 4100 } else if (Feature == "+vfp3") { 4101 FPU |= VFP3FPU; 4102 HW_FP = HW_FP_SP | HW_FP_DP; 4103 } else if (Feature == "+vfp4") { 4104 FPU |= VFP4FPU; 4105 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4106 } else if (Feature == "+fp-armv8") { 4107 FPU |= FPARMV8; 4108 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4109 } else if (Feature == "+neon") { 4110 FPU |= NeonFPU; 4111 HW_FP = HW_FP_SP | HW_FP_DP; 4112 } else if (Feature == "+hwdiv") { 4113 HWDiv |= HWDivThumb; 4114 } else if (Feature == "+hwdiv-arm") { 4115 HWDiv |= HWDivARM; 4116 } else if (Feature == "+crc") { 4117 CRC = 1; 4118 } else if (Feature == "+crypto") { 4119 Crypto = 1; 4120 } else if (Feature == "+fp-only-sp") { 4121 HW_FP &= ~HW_FP_DP; 4122 } 4123 } 4124 4125 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4126 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4127 return false; 4128 } 4129 4130 if (FPMath == FP_Neon) 4131 Features.push_back("+neonfp"); 4132 else if (FPMath == FP_VFP) 4133 Features.push_back("-neonfp"); 4134 4135 // Remove front-end specific options which the backend handles differently. 4136 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4137 for (const auto &FEFeature : FrontEndFeatures) { 4138 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4139 if (Feature != Features.end()) 4140 Features.erase(Feature); 4141 } 4142 4143 return true; 4144 } 4145 4146 bool hasFeature(StringRef Feature) const override { 4147 return llvm::StringSwitch<bool>(Feature) 4148 .Case("arm", true) 4149 .Case("softfloat", SoftFloat) 4150 .Case("thumb", IsThumb) 4151 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4152 .Case("hwdiv", HWDiv & HWDivThumb) 4153 .Case("hwdiv-arm", HWDiv & HWDivARM) 4154 .Default(false); 4155 } 4156 // FIXME: Should we actually have some table instead of these switches? 4157 static const char *getCPUDefineSuffix(StringRef Name) { 4158 return llvm::StringSwitch<const char *>(Name) 4159 .Cases("arm8", "arm810", "4") 4160 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4161 "4") 4162 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4163 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4164 .Case("ep9312", "4T") 4165 .Cases("arm10tdmi", "arm1020t", "5T") 4166 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4167 .Case("arm926ej-s", "5TEJ") 4168 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4169 .Cases("xscale", "iwmmxt", "5TE") 4170 .Case("arm1136j-s", "6J") 4171 .Case("arm1136jf-s", "6") 4172 .Cases("mpcorenovfp", "mpcore", "6K") 4173 .Cases("arm1176jz-s", "arm1176jzf-s", "6K") 4174 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4175 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4176 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4177 "7A") 4178 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R") 4179 .Case("swift", "7S") 4180 .Case("cyclone", "8A") 4181 .Cases("sc300", "cortex-m3", "7M") 4182 .Cases("cortex-m4", "cortex-m7", "7EM") 4183 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4184 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4185 .Default(nullptr); 4186 } 4187 static const char *getCPUProfile(StringRef Name) { 4188 return llvm::StringSwitch<const char *>(Name) 4189 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4190 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4191 "A") 4192 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4193 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4194 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4195 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R") 4196 .Default(""); 4197 } 4198 bool setCPU(const std::string &Name) override { 4199 if (!getCPUDefineSuffix(Name)) 4200 return false; 4201 4202 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4203 StringRef Profile = getCPUProfile(Name); 4204 if (Profile == "M" && MaxAtomicInlineWidth) { 4205 MaxAtomicPromoteWidth = 32; 4206 MaxAtomicInlineWidth = 32; 4207 } 4208 4209 CPU = Name; 4210 return true; 4211 } 4212 bool setFPMath(StringRef Name) override; 4213 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4214 unsigned CPUArchVer) const { 4215 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4216 (CPUArch.find('M') != StringRef::npos); 4217 } 4218 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4219 unsigned CPUArchVer) const { 4220 // We check both CPUArchVer and ArchName because when only triple is 4221 // specified, the default CPU is arm1136j-s. 4222 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4223 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4224 } 4225 void getTargetDefines(const LangOptions &Opts, 4226 MacroBuilder &Builder) const override { 4227 // Target identification. 4228 Builder.defineMacro("__arm"); 4229 Builder.defineMacro("__arm__"); 4230 4231 // Target properties. 4232 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4233 4234 StringRef CPUArch = getCPUDefineSuffix(CPU); 4235 unsigned int CPUArchVer; 4236 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4237 llvm_unreachable("Invalid char for architecture version number"); 4238 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4239 4240 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4241 StringRef CPUProfile = getCPUProfile(CPU); 4242 StringRef ArchName = getTriple().getArchName(); 4243 4244 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4245 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4246 if (CPUArch[0] >= '8') { 4247 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4248 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4249 } 4250 4251 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4252 // is not defined for the M-profile. 4253 // NOTE that the deffault profile is assumed to be 'A' 4254 if (CPUProfile.empty() || CPUProfile != "M") 4255 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4256 4257 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4258 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4259 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4260 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4261 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4262 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4263 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4264 4265 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4266 // instruction set such as ARM or Thumb. 4267 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4268 4269 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4270 4271 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4272 if (!CPUProfile.empty()) 4273 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4274 4275 // ACLE 6.5.1 Hardware Floating Point 4276 if (HW_FP) 4277 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4278 4279 // ACLE predefines. 4280 Builder.defineMacro("__ARM_ACLE", "200"); 4281 4282 // Subtarget options. 4283 4284 // FIXME: It's more complicated than this and we don't really support 4285 // interworking. 4286 // Windows on ARM does not "support" interworking 4287 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4288 Builder.defineMacro("__THUMB_INTERWORK__"); 4289 4290 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4291 // Embedded targets on Darwin follow AAPCS, but not EABI. 4292 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4293 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4294 Builder.defineMacro("__ARM_EABI__"); 4295 Builder.defineMacro("__ARM_PCS", "1"); 4296 4297 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4298 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4299 } 4300 4301 if (SoftFloat) 4302 Builder.defineMacro("__SOFTFP__"); 4303 4304 if (CPU == "xscale") 4305 Builder.defineMacro("__XSCALE__"); 4306 4307 if (IsThumb) { 4308 Builder.defineMacro("__THUMBEL__"); 4309 Builder.defineMacro("__thumb__"); 4310 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4311 Builder.defineMacro("__thumb2__"); 4312 } 4313 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4314 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4315 4316 // Note, this is always on in gcc, even though it doesn't make sense. 4317 Builder.defineMacro("__APCS_32__"); 4318 4319 if (FPUModeIsVFP((FPUMode) FPU)) { 4320 Builder.defineMacro("__VFP_FP__"); 4321 if (FPU & VFP2FPU) 4322 Builder.defineMacro("__ARM_VFPV2__"); 4323 if (FPU & VFP3FPU) 4324 Builder.defineMacro("__ARM_VFPV3__"); 4325 if (FPU & VFP4FPU) 4326 Builder.defineMacro("__ARM_VFPV4__"); 4327 } 4328 4329 // This only gets set when Neon instructions are actually available, unlike 4330 // the VFP define, hence the soft float and arch check. This is subtly 4331 // different from gcc, we follow the intent which was that it should be set 4332 // when Neon instructions are actually available. 4333 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4334 Builder.defineMacro("__ARM_NEON"); 4335 Builder.defineMacro("__ARM_NEON__"); 4336 } 4337 4338 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4339 Opts.ShortWChar ? "2" : "4"); 4340 4341 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4342 Opts.ShortEnums ? "1" : "4"); 4343 4344 if (CRC) 4345 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4346 4347 if (Crypto) 4348 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4349 4350 if (CPUArchVer >= 6 && CPUArch != "6M") { 4351 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4352 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4353 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4354 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4355 } 4356 4357 bool is5EOrAbove = (CPUArchVer >= 6 || 4358 (CPUArchVer == 5 && 4359 CPUArch.find('E') != StringRef::npos)); 4360 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4361 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4362 Builder.defineMacro("__ARM_FEATURE_DSP"); 4363 } 4364 void getTargetBuiltins(const Builtin::Info *&Records, 4365 unsigned &NumRecords) const override { 4366 Records = BuiltinInfo; 4367 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4368 } 4369 bool isCLZForZeroUndef() const override { return false; } 4370 BuiltinVaListKind getBuiltinVaListKind() const override { 4371 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4372 } 4373 void getGCCRegNames(const char * const *&Names, 4374 unsigned &NumNames) const override; 4375 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4376 unsigned &NumAliases) const override; 4377 bool validateAsmConstraint(const char *&Name, 4378 TargetInfo::ConstraintInfo &Info) const override { 4379 switch (*Name) { 4380 default: break; 4381 case 'l': // r0-r7 4382 case 'h': // r8-r15 4383 case 'w': // VFP Floating point register single precision 4384 case 'P': // VFP Floating point register double precision 4385 Info.setAllowsRegister(); 4386 return true; 4387 case 'I': 4388 case 'J': 4389 case 'K': 4390 case 'L': 4391 case 'M': 4392 // FIXME 4393 return true; 4394 case 'Q': // A memory address that is a single base register. 4395 Info.setAllowsMemory(); 4396 return true; 4397 case 'U': // a memory reference... 4398 switch (Name[1]) { 4399 case 'q': // ...ARMV4 ldrsb 4400 case 'v': // ...VFP load/store (reg+constant offset) 4401 case 'y': // ...iWMMXt load/store 4402 case 't': // address valid for load/store opaque types wider 4403 // than 128-bits 4404 case 'n': // valid address for Neon doubleword vector load/store 4405 case 'm': // valid address for Neon element and structure load/store 4406 case 's': // valid address for non-offset loads/stores of quad-word 4407 // values in four ARM registers 4408 Info.setAllowsMemory(); 4409 Name++; 4410 return true; 4411 } 4412 } 4413 return false; 4414 } 4415 std::string convertConstraint(const char *&Constraint) const override { 4416 std::string R; 4417 switch (*Constraint) { 4418 case 'U': // Two-character constraint; add "^" hint for later parsing. 4419 R = std::string("^") + std::string(Constraint, 2); 4420 Constraint++; 4421 break; 4422 case 'p': // 'p' should be translated to 'r' by default. 4423 R = std::string("r"); 4424 break; 4425 default: 4426 return std::string(1, *Constraint); 4427 } 4428 return R; 4429 } 4430 bool 4431 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4432 std::string &SuggestedModifier) const override { 4433 bool isOutput = (Constraint[0] == '='); 4434 bool isInOut = (Constraint[0] == '+'); 4435 4436 // Strip off constraint modifiers. 4437 while (Constraint[0] == '=' || 4438 Constraint[0] == '+' || 4439 Constraint[0] == '&') 4440 Constraint = Constraint.substr(1); 4441 4442 switch (Constraint[0]) { 4443 default: break; 4444 case 'r': { 4445 switch (Modifier) { 4446 default: 4447 return (isInOut || isOutput || Size <= 64); 4448 case 'q': 4449 // A register of size 32 cannot fit a vector type. 4450 return false; 4451 } 4452 } 4453 } 4454 4455 return true; 4456 } 4457 const char *getClobbers() const override { 4458 // FIXME: Is this really right? 4459 return ""; 4460 } 4461 4462 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4463 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4464 } 4465 4466 int getEHDataRegisterNumber(unsigned RegNo) const override { 4467 if (RegNo == 0) return 0; 4468 if (RegNo == 1) return 1; 4469 return -1; 4470 } 4471 }; 4472 4473 bool ARMTargetInfo::setFPMath(StringRef Name) { 4474 if (Name == "neon") { 4475 FPMath = FP_Neon; 4476 return true; 4477 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4478 Name == "vfp4") { 4479 FPMath = FP_VFP; 4480 return true; 4481 } 4482 return false; 4483 } 4484 4485 const char * const ARMTargetInfo::GCCRegNames[] = { 4486 // Integer registers 4487 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4488 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4489 4490 // Float registers 4491 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4492 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4493 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4494 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4495 4496 // Double registers 4497 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4498 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4499 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4500 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4501 4502 // Quad registers 4503 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4504 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4505 }; 4506 4507 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4508 unsigned &NumNames) const { 4509 Names = GCCRegNames; 4510 NumNames = llvm::array_lengthof(GCCRegNames); 4511 } 4512 4513 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4514 { { "a1" }, "r0" }, 4515 { { "a2" }, "r1" }, 4516 { { "a3" }, "r2" }, 4517 { { "a4" }, "r3" }, 4518 { { "v1" }, "r4" }, 4519 { { "v2" }, "r5" }, 4520 { { "v3" }, "r6" }, 4521 { { "v4" }, "r7" }, 4522 { { "v5" }, "r8" }, 4523 { { "v6", "rfp" }, "r9" }, 4524 { { "sl" }, "r10" }, 4525 { { "fp" }, "r11" }, 4526 { { "ip" }, "r12" }, 4527 { { "r13" }, "sp" }, 4528 { { "r14" }, "lr" }, 4529 { { "r15" }, "pc" }, 4530 // The S, D and Q registers overlap, but aren't really aliases; we 4531 // don't want to substitute one of these for a different-sized one. 4532 }; 4533 4534 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4535 unsigned &NumAliases) const { 4536 Aliases = GCCRegAliases; 4537 NumAliases = llvm::array_lengthof(GCCRegAliases); 4538 } 4539 4540 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4541 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4542 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4543 ALL_LANGUAGES }, 4544 #include "clang/Basic/BuiltinsNEON.def" 4545 4546 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4547 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4548 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4549 ALL_LANGUAGES }, 4550 #include "clang/Basic/BuiltinsARM.def" 4551 }; 4552 4553 class ARMleTargetInfo : public ARMTargetInfo { 4554 public: 4555 ARMleTargetInfo(const llvm::Triple &Triple) 4556 : ARMTargetInfo(Triple, false) { } 4557 virtual void getTargetDefines(const LangOptions &Opts, 4558 MacroBuilder &Builder) const { 4559 Builder.defineMacro("__ARMEL__"); 4560 ARMTargetInfo::getTargetDefines(Opts, Builder); 4561 } 4562 }; 4563 4564 class ARMbeTargetInfo : public ARMTargetInfo { 4565 public: 4566 ARMbeTargetInfo(const llvm::Triple &Triple) 4567 : ARMTargetInfo(Triple, true) { } 4568 virtual void getTargetDefines(const LangOptions &Opts, 4569 MacroBuilder &Builder) const { 4570 Builder.defineMacro("__ARMEB__"); 4571 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4572 ARMTargetInfo::getTargetDefines(Opts, Builder); 4573 } 4574 }; 4575 4576 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4577 const llvm::Triple Triple; 4578 public: 4579 WindowsARMTargetInfo(const llvm::Triple &Triple) 4580 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4581 TLSSupported = false; 4582 WCharType = UnsignedShort; 4583 SizeType = UnsignedInt; 4584 UserLabelPrefix = ""; 4585 } 4586 void getVisualStudioDefines(const LangOptions &Opts, 4587 MacroBuilder &Builder) const { 4588 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4589 4590 // FIXME: this is invalid for WindowsCE 4591 Builder.defineMacro("_M_ARM_NT", "1"); 4592 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4593 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4594 4595 assert((Triple.getArch() == llvm::Triple::arm || 4596 Triple.getArch() == llvm::Triple::thumb) && 4597 "invalid architecture for Windows ARM target info"); 4598 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4599 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4600 4601 // TODO map the complete set of values 4602 // 31: VFPv3 40: VFPv4 4603 Builder.defineMacro("_M_ARM_FP", "31"); 4604 } 4605 BuiltinVaListKind getBuiltinVaListKind() const override { 4606 return TargetInfo::CharPtrBuiltinVaList; 4607 } 4608 }; 4609 4610 // Windows ARM + Itanium C++ ABI Target 4611 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4612 public: 4613 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4614 : WindowsARMTargetInfo(Triple) { 4615 TheCXXABI.set(TargetCXXABI::GenericARM); 4616 } 4617 4618 void getTargetDefines(const LangOptions &Opts, 4619 MacroBuilder &Builder) const override { 4620 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4621 4622 if (Opts.MSVCCompat) 4623 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4624 } 4625 }; 4626 4627 // Windows ARM, MS (C++) ABI 4628 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4629 public: 4630 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4631 : WindowsARMTargetInfo(Triple) { 4632 TheCXXABI.set(TargetCXXABI::Microsoft); 4633 } 4634 4635 void getTargetDefines(const LangOptions &Opts, 4636 MacroBuilder &Builder) const override { 4637 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4638 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4639 } 4640 }; 4641 4642 class DarwinARMTargetInfo : 4643 public DarwinTargetInfo<ARMleTargetInfo> { 4644 protected: 4645 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4646 MacroBuilder &Builder) const override { 4647 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4648 } 4649 4650 public: 4651 DarwinARMTargetInfo(const llvm::Triple &Triple) 4652 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4653 HasAlignMac68kSupport = true; 4654 // iOS always has 64-bit atomic instructions. 4655 // FIXME: This should be based off of the target features in 4656 // ARMleTargetInfo. 4657 MaxAtomicInlineWidth = 64; 4658 4659 // Darwin on iOS uses a variant of the ARM C++ ABI. 4660 TheCXXABI.set(TargetCXXABI::iOS); 4661 } 4662 }; 4663 4664 class AArch64TargetInfo : public TargetInfo { 4665 virtual void setDescriptionString() = 0; 4666 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4667 static const char *const GCCRegNames[]; 4668 4669 enum FPUModeEnum { 4670 FPUMode, 4671 NeonMode 4672 }; 4673 4674 unsigned FPU; 4675 unsigned CRC; 4676 unsigned Crypto; 4677 4678 static const Builtin::Info BuiltinInfo[]; 4679 4680 std::string ABI; 4681 4682 public: 4683 AArch64TargetInfo(const llvm::Triple &Triple) 4684 : TargetInfo(Triple), ABI("aapcs") { 4685 4686 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4687 WCharType = SignedInt; 4688 4689 // NetBSD apparently prefers consistency across ARM targets to consistency 4690 // across 64-bit targets. 4691 Int64Type = SignedLongLong; 4692 IntMaxType = SignedLongLong; 4693 } else { 4694 WCharType = UnsignedInt; 4695 Int64Type = SignedLong; 4696 IntMaxType = SignedLong; 4697 } 4698 4699 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4700 MaxVectorAlign = 128; 4701 RegParmMax = 8; 4702 MaxAtomicInlineWidth = 128; 4703 MaxAtomicPromoteWidth = 128; 4704 4705 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4706 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4707 4708 // {} in inline assembly are neon specifiers, not assembly variant 4709 // specifiers. 4710 NoAsmVariants = true; 4711 4712 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4713 // contributes to the alignment of the containing aggregate in the same way 4714 // a plain (non bit-field) member of that type would, without exception for 4715 // zero-sized or anonymous bit-fields." 4716 UseBitFieldTypeAlignment = true; 4717 UseZeroLengthBitfieldAlignment = true; 4718 4719 // AArch64 targets default to using the ARM C++ ABI. 4720 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4721 } 4722 4723 StringRef getABI() const override { return ABI; } 4724 bool setABI(const std::string &Name) override { 4725 if (Name != "aapcs" && Name != "darwinpcs") 4726 return false; 4727 4728 ABI = Name; 4729 return true; 4730 } 4731 4732 bool setCPU(const std::string &Name) override { 4733 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4734 .Case("generic", true) 4735 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4736 .Case("cyclone", true) 4737 .Default(false); 4738 return CPUKnown; 4739 } 4740 4741 virtual void getTargetDefines(const LangOptions &Opts, 4742 MacroBuilder &Builder) const override { 4743 // Target identification. 4744 Builder.defineMacro("__aarch64__"); 4745 4746 // Target properties. 4747 Builder.defineMacro("_LP64"); 4748 Builder.defineMacro("__LP64__"); 4749 4750 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4751 Builder.defineMacro("__ARM_ACLE", "200"); 4752 Builder.defineMacro("__ARM_ARCH", "8"); 4753 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4754 4755 Builder.defineMacro("__ARM_64BIT_STATE"); 4756 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4757 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4758 4759 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4760 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4761 Builder.defineMacro("__ARM_FEATURE_FMA"); 4762 Builder.defineMacro("__ARM_FEATURE_DIV"); 4763 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4764 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4765 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4766 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4767 4768 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4769 4770 // 0xe implies support for half, single and double precision operations. 4771 Builder.defineMacro("__ARM_FP", "0xe"); 4772 4773 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4774 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4775 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4776 4777 if (Opts.FastMath || Opts.FiniteMathOnly) 4778 Builder.defineMacro("__ARM_FP_FAST"); 4779 4780 if (Opts.C99 && !Opts.Freestanding) 4781 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4782 4783 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4784 4785 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4786 Opts.ShortEnums ? "1" : "4"); 4787 4788 if (FPU == NeonMode) { 4789 Builder.defineMacro("__ARM_NEON"); 4790 // 64-bit NEON supports half, single and double precision operations. 4791 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4792 } 4793 4794 if (CRC) 4795 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4796 4797 if (Crypto) 4798 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4799 } 4800 4801 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4802 unsigned &NumRecords) const override { 4803 Records = BuiltinInfo; 4804 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4805 } 4806 4807 bool hasFeature(StringRef Feature) const override { 4808 return Feature == "aarch64" || 4809 Feature == "arm64" || 4810 (Feature == "neon" && FPU == NeonMode); 4811 } 4812 4813 bool handleTargetFeatures(std::vector<std::string> &Features, 4814 DiagnosticsEngine &Diags) override { 4815 FPU = FPUMode; 4816 CRC = 0; 4817 Crypto = 0; 4818 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4819 if (Features[i] == "+neon") 4820 FPU = NeonMode; 4821 if (Features[i] == "+crc") 4822 CRC = 1; 4823 if (Features[i] == "+crypto") 4824 Crypto = 1; 4825 } 4826 4827 setDescriptionString(); 4828 4829 return true; 4830 } 4831 4832 bool isCLZForZeroUndef() const override { return false; } 4833 4834 BuiltinVaListKind getBuiltinVaListKind() const override { 4835 return TargetInfo::AArch64ABIBuiltinVaList; 4836 } 4837 4838 virtual void getGCCRegNames(const char *const *&Names, 4839 unsigned &NumNames) const override; 4840 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4841 unsigned &NumAliases) const override; 4842 4843 virtual bool 4844 validateAsmConstraint(const char *&Name, 4845 TargetInfo::ConstraintInfo &Info) const override { 4846 switch (*Name) { 4847 default: 4848 return false; 4849 case 'w': // Floating point and SIMD registers (V0-V31) 4850 Info.setAllowsRegister(); 4851 return true; 4852 case 'I': // Constant that can be used with an ADD instruction 4853 case 'J': // Constant that can be used with a SUB instruction 4854 case 'K': // Constant that can be used with a 32-bit logical instruction 4855 case 'L': // Constant that can be used with a 64-bit logical instruction 4856 case 'M': // Constant that can be used as a 32-bit MOV immediate 4857 case 'N': // Constant that can be used as a 64-bit MOV immediate 4858 case 'Y': // Floating point constant zero 4859 case 'Z': // Integer constant zero 4860 return true; 4861 case 'Q': // A memory reference with base register and no offset 4862 Info.setAllowsMemory(); 4863 return true; 4864 case 'S': // A symbolic address 4865 Info.setAllowsRegister(); 4866 return true; 4867 case 'U': 4868 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4869 // Utf: A memory address suitable for ldp/stp in TF mode. 4870 // Usa: An absolute symbolic address. 4871 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4872 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4873 case 'z': // Zero register, wzr or xzr 4874 Info.setAllowsRegister(); 4875 return true; 4876 case 'x': // Floating point and SIMD registers (V0-V15) 4877 Info.setAllowsRegister(); 4878 return true; 4879 } 4880 return false; 4881 } 4882 4883 bool 4884 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4885 std::string &SuggestedModifier) const override { 4886 // Strip off constraint modifiers. 4887 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4888 Constraint = Constraint.substr(1); 4889 4890 switch (Constraint[0]) { 4891 default: 4892 return true; 4893 case 'z': 4894 case 'r': { 4895 switch (Modifier) { 4896 case 'x': 4897 case 'w': 4898 // For now assume that the person knows what they're 4899 // doing with the modifier. 4900 return true; 4901 default: 4902 // By default an 'r' constraint will be in the 'x' 4903 // registers. 4904 if (Size == 64) 4905 return true; 4906 4907 SuggestedModifier = "w"; 4908 return false; 4909 } 4910 } 4911 } 4912 } 4913 4914 const char *getClobbers() const override { return ""; } 4915 4916 int getEHDataRegisterNumber(unsigned RegNo) const override { 4917 if (RegNo == 0) 4918 return 0; 4919 if (RegNo == 1) 4920 return 1; 4921 return -1; 4922 } 4923 }; 4924 4925 const char *const AArch64TargetInfo::GCCRegNames[] = { 4926 // 32-bit Integer registers 4927 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4928 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4929 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4930 4931 // 64-bit Integer registers 4932 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4933 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4934 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4935 4936 // 32-bit floating point regsisters 4937 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4938 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4939 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4940 4941 // 64-bit floating point regsisters 4942 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4943 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4944 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4945 4946 // Vector registers 4947 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4948 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4949 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4950 }; 4951 4952 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4953 unsigned &NumNames) const { 4954 Names = GCCRegNames; 4955 NumNames = llvm::array_lengthof(GCCRegNames); 4956 } 4957 4958 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4959 { { "w31" }, "wsp" }, 4960 { { "x29" }, "fp" }, 4961 { { "x30" }, "lr" }, 4962 { { "x31" }, "sp" }, 4963 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4964 // don't want to substitute one of these for a different-sized one. 4965 }; 4966 4967 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4968 unsigned &NumAliases) const { 4969 Aliases = GCCRegAliases; 4970 NumAliases = llvm::array_lengthof(GCCRegAliases); 4971 } 4972 4973 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4974 #define BUILTIN(ID, TYPE, ATTRS) \ 4975 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4976 #include "clang/Basic/BuiltinsNEON.def" 4977 4978 #define BUILTIN(ID, TYPE, ATTRS) \ 4979 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4980 #include "clang/Basic/BuiltinsAArch64.def" 4981 }; 4982 4983 class AArch64leTargetInfo : public AArch64TargetInfo { 4984 void setDescriptionString() override { 4985 if (getTriple().isOSBinFormatMachO()) 4986 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4987 else 4988 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4989 } 4990 4991 public: 4992 AArch64leTargetInfo(const llvm::Triple &Triple) 4993 : AArch64TargetInfo(Triple) { 4994 BigEndian = false; 4995 } 4996 void getTargetDefines(const LangOptions &Opts, 4997 MacroBuilder &Builder) const override { 4998 Builder.defineMacro("__AARCH64EL__"); 4999 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5000 } 5001 }; 5002 5003 class AArch64beTargetInfo : public AArch64TargetInfo { 5004 void setDescriptionString() override { 5005 assert(!getTriple().isOSBinFormatMachO()); 5006 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5007 } 5008 5009 public: 5010 AArch64beTargetInfo(const llvm::Triple &Triple) 5011 : AArch64TargetInfo(Triple) { } 5012 void getTargetDefines(const LangOptions &Opts, 5013 MacroBuilder &Builder) const override { 5014 Builder.defineMacro("__AARCH64EB__"); 5015 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5016 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5017 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5018 } 5019 }; 5020 5021 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5022 protected: 5023 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5024 MacroBuilder &Builder) const override { 5025 Builder.defineMacro("__AARCH64_SIMD__"); 5026 Builder.defineMacro("__ARM64_ARCH_8__"); 5027 Builder.defineMacro("__ARM_NEON__"); 5028 Builder.defineMacro("__LITTLE_ENDIAN__"); 5029 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5030 Builder.defineMacro("__arm64", "1"); 5031 Builder.defineMacro("__arm64__", "1"); 5032 5033 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5034 } 5035 5036 public: 5037 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5038 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5039 Int64Type = SignedLongLong; 5040 WCharType = SignedInt; 5041 UseSignedCharForObjCBool = false; 5042 5043 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5044 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5045 5046 TheCXXABI.set(TargetCXXABI::iOS64); 5047 } 5048 5049 BuiltinVaListKind getBuiltinVaListKind() const override { 5050 return TargetInfo::CharPtrBuiltinVaList; 5051 } 5052 }; 5053 5054 // Hexagon abstract base class 5055 class HexagonTargetInfo : public TargetInfo { 5056 static const Builtin::Info BuiltinInfo[]; 5057 static const char * const GCCRegNames[]; 5058 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5059 std::string CPU; 5060 public: 5061 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5062 BigEndian = false; 5063 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5064 5065 // {} in inline assembly are packet specifiers, not assembly variant 5066 // specifiers. 5067 NoAsmVariants = true; 5068 } 5069 5070 void getTargetBuiltins(const Builtin::Info *&Records, 5071 unsigned &NumRecords) const override { 5072 Records = BuiltinInfo; 5073 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5074 } 5075 5076 bool validateAsmConstraint(const char *&Name, 5077 TargetInfo::ConstraintInfo &Info) const override { 5078 return true; 5079 } 5080 5081 void getTargetDefines(const LangOptions &Opts, 5082 MacroBuilder &Builder) const override; 5083 5084 bool hasFeature(StringRef Feature) const override { 5085 return Feature == "hexagon"; 5086 } 5087 5088 BuiltinVaListKind getBuiltinVaListKind() const override { 5089 return TargetInfo::CharPtrBuiltinVaList; 5090 } 5091 void getGCCRegNames(const char * const *&Names, 5092 unsigned &NumNames) const override; 5093 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5094 unsigned &NumAliases) const override; 5095 const char *getClobbers() const override { 5096 return ""; 5097 } 5098 5099 static const char *getHexagonCPUSuffix(StringRef Name) { 5100 return llvm::StringSwitch<const char*>(Name) 5101 .Case("hexagonv4", "4") 5102 .Case("hexagonv5", "5") 5103 .Default(nullptr); 5104 } 5105 5106 bool setCPU(const std::string &Name) override { 5107 if (!getHexagonCPUSuffix(Name)) 5108 return false; 5109 5110 CPU = Name; 5111 return true; 5112 } 5113 }; 5114 5115 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5116 MacroBuilder &Builder) const { 5117 Builder.defineMacro("qdsp6"); 5118 Builder.defineMacro("__qdsp6", "1"); 5119 Builder.defineMacro("__qdsp6__", "1"); 5120 5121 Builder.defineMacro("hexagon"); 5122 Builder.defineMacro("__hexagon", "1"); 5123 Builder.defineMacro("__hexagon__", "1"); 5124 5125 if(CPU == "hexagonv1") { 5126 Builder.defineMacro("__HEXAGON_V1__"); 5127 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5128 if(Opts.HexagonQdsp6Compat) { 5129 Builder.defineMacro("__QDSP6_V1__"); 5130 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5131 } 5132 } 5133 else if(CPU == "hexagonv2") { 5134 Builder.defineMacro("__HEXAGON_V2__"); 5135 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5136 if(Opts.HexagonQdsp6Compat) { 5137 Builder.defineMacro("__QDSP6_V2__"); 5138 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5139 } 5140 } 5141 else if(CPU == "hexagonv3") { 5142 Builder.defineMacro("__HEXAGON_V3__"); 5143 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5144 if(Opts.HexagonQdsp6Compat) { 5145 Builder.defineMacro("__QDSP6_V3__"); 5146 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5147 } 5148 } 5149 else if(CPU == "hexagonv4") { 5150 Builder.defineMacro("__HEXAGON_V4__"); 5151 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5152 if(Opts.HexagonQdsp6Compat) { 5153 Builder.defineMacro("__QDSP6_V4__"); 5154 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5155 } 5156 } 5157 else if(CPU == "hexagonv5") { 5158 Builder.defineMacro("__HEXAGON_V5__"); 5159 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5160 if(Opts.HexagonQdsp6Compat) { 5161 Builder.defineMacro("__QDSP6_V5__"); 5162 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5163 } 5164 } 5165 } 5166 5167 const char * const HexagonTargetInfo::GCCRegNames[] = { 5168 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5169 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5170 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5171 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5172 "p0", "p1", "p2", "p3", 5173 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5174 }; 5175 5176 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5177 unsigned &NumNames) const { 5178 Names = GCCRegNames; 5179 NumNames = llvm::array_lengthof(GCCRegNames); 5180 } 5181 5182 5183 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5184 { { "sp" }, "r29" }, 5185 { { "fp" }, "r30" }, 5186 { { "lr" }, "r31" }, 5187 }; 5188 5189 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5190 unsigned &NumAliases) const { 5191 Aliases = GCCRegAliases; 5192 NumAliases = llvm::array_lengthof(GCCRegAliases); 5193 } 5194 5195 5196 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5197 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5198 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5199 ALL_LANGUAGES }, 5200 #include "clang/Basic/BuiltinsHexagon.def" 5201 }; 5202 5203 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5204 class SparcTargetInfo : public TargetInfo { 5205 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5206 static const char * const GCCRegNames[]; 5207 bool SoftFloat; 5208 public: 5209 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5210 5211 bool handleTargetFeatures(std::vector<std::string> &Features, 5212 DiagnosticsEngine &Diags) override { 5213 SoftFloat = false; 5214 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5215 if (Features[i] == "+soft-float") 5216 SoftFloat = true; 5217 return true; 5218 } 5219 void getTargetDefines(const LangOptions &Opts, 5220 MacroBuilder &Builder) const override { 5221 DefineStd(Builder, "sparc", Opts); 5222 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5223 5224 if (SoftFloat) 5225 Builder.defineMacro("SOFT_FLOAT", "1"); 5226 } 5227 5228 bool hasFeature(StringRef Feature) const override { 5229 return llvm::StringSwitch<bool>(Feature) 5230 .Case("softfloat", SoftFloat) 5231 .Case("sparc", true) 5232 .Default(false); 5233 } 5234 5235 void getTargetBuiltins(const Builtin::Info *&Records, 5236 unsigned &NumRecords) const override { 5237 // FIXME: Implement! 5238 } 5239 BuiltinVaListKind getBuiltinVaListKind() const override { 5240 return TargetInfo::VoidPtrBuiltinVaList; 5241 } 5242 void getGCCRegNames(const char * const *&Names, 5243 unsigned &NumNames) const override; 5244 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5245 unsigned &NumAliases) const override; 5246 bool validateAsmConstraint(const char *&Name, 5247 TargetInfo::ConstraintInfo &info) const override { 5248 // FIXME: Implement! 5249 switch (*Name) { 5250 case 'I': // Signed 13-bit constant 5251 case 'J': // Zero 5252 case 'K': // 32-bit constant with the low 12 bits clear 5253 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5254 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5255 case 'N': // Same as 'K' but zext (required for SIMode) 5256 case 'O': // The constant 4096 5257 return true; 5258 } 5259 return false; 5260 } 5261 const char *getClobbers() const override { 5262 // FIXME: Implement! 5263 return ""; 5264 } 5265 }; 5266 5267 const char * const SparcTargetInfo::GCCRegNames[] = { 5268 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5269 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5270 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5271 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5272 }; 5273 5274 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5275 unsigned &NumNames) const { 5276 Names = GCCRegNames; 5277 NumNames = llvm::array_lengthof(GCCRegNames); 5278 } 5279 5280 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5281 { { "g0" }, "r0" }, 5282 { { "g1" }, "r1" }, 5283 { { "g2" }, "r2" }, 5284 { { "g3" }, "r3" }, 5285 { { "g4" }, "r4" }, 5286 { { "g5" }, "r5" }, 5287 { { "g6" }, "r6" }, 5288 { { "g7" }, "r7" }, 5289 { { "o0" }, "r8" }, 5290 { { "o1" }, "r9" }, 5291 { { "o2" }, "r10" }, 5292 { { "o3" }, "r11" }, 5293 { { "o4" }, "r12" }, 5294 { { "o5" }, "r13" }, 5295 { { "o6", "sp" }, "r14" }, 5296 { { "o7" }, "r15" }, 5297 { { "l0" }, "r16" }, 5298 { { "l1" }, "r17" }, 5299 { { "l2" }, "r18" }, 5300 { { "l3" }, "r19" }, 5301 { { "l4" }, "r20" }, 5302 { { "l5" }, "r21" }, 5303 { { "l6" }, "r22" }, 5304 { { "l7" }, "r23" }, 5305 { { "i0" }, "r24" }, 5306 { { "i1" }, "r25" }, 5307 { { "i2" }, "r26" }, 5308 { { "i3" }, "r27" }, 5309 { { "i4" }, "r28" }, 5310 { { "i5" }, "r29" }, 5311 { { "i6", "fp" }, "r30" }, 5312 { { "i7" }, "r31" }, 5313 }; 5314 5315 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5316 unsigned &NumAliases) const { 5317 Aliases = GCCRegAliases; 5318 NumAliases = llvm::array_lengthof(GCCRegAliases); 5319 } 5320 5321 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5322 class SparcV8TargetInfo : public SparcTargetInfo { 5323 public: 5324 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5325 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5326 } 5327 5328 void getTargetDefines(const LangOptions &Opts, 5329 MacroBuilder &Builder) const override { 5330 SparcTargetInfo::getTargetDefines(Opts, Builder); 5331 Builder.defineMacro("__sparcv8"); 5332 } 5333 }; 5334 5335 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5336 class SparcV9TargetInfo : public SparcTargetInfo { 5337 public: 5338 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5339 // FIXME: Support Sparc quad-precision long double? 5340 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5341 // This is an LP64 platform. 5342 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5343 5344 // OpenBSD uses long long for int64_t and intmax_t. 5345 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5346 IntMaxType = SignedLongLong; 5347 else 5348 IntMaxType = SignedLong; 5349 Int64Type = IntMaxType; 5350 5351 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5352 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5353 LongDoubleWidth = 128; 5354 LongDoubleAlign = 128; 5355 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5356 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5357 } 5358 5359 void getTargetDefines(const LangOptions &Opts, 5360 MacroBuilder &Builder) const override { 5361 SparcTargetInfo::getTargetDefines(Opts, Builder); 5362 Builder.defineMacro("__sparcv9"); 5363 Builder.defineMacro("__arch64__"); 5364 // Solaris doesn't need these variants, but the BSDs do. 5365 if (getTriple().getOS() != llvm::Triple::Solaris) { 5366 Builder.defineMacro("__sparc64__"); 5367 Builder.defineMacro("__sparc_v9__"); 5368 Builder.defineMacro("__sparcv9__"); 5369 } 5370 } 5371 5372 bool setCPU(const std::string &Name) override { 5373 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5374 .Case("v9", true) 5375 .Case("ultrasparc", true) 5376 .Case("ultrasparc3", true) 5377 .Case("niagara", true) 5378 .Case("niagara2", true) 5379 .Case("niagara3", true) 5380 .Case("niagara4", true) 5381 .Default(false); 5382 5383 // No need to store the CPU yet. There aren't any CPU-specific 5384 // macros to define. 5385 return CPUKnown; 5386 } 5387 }; 5388 5389 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5390 public: 5391 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5392 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5393 SizeType = UnsignedInt; 5394 PtrDiffType = SignedInt; 5395 } 5396 }; 5397 5398 class SystemZTargetInfo : public TargetInfo { 5399 static const char *const GCCRegNames[]; 5400 5401 public: 5402 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5403 TLSSupported = true; 5404 IntWidth = IntAlign = 32; 5405 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5406 PointerWidth = PointerAlign = 64; 5407 LongDoubleWidth = 128; 5408 LongDoubleAlign = 64; 5409 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5410 MinGlobalAlign = 16; 5411 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5412 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5413 } 5414 void getTargetDefines(const LangOptions &Opts, 5415 MacroBuilder &Builder) const override { 5416 Builder.defineMacro("__s390__"); 5417 Builder.defineMacro("__s390x__"); 5418 Builder.defineMacro("__zarch__"); 5419 Builder.defineMacro("__LONG_DOUBLE_128__"); 5420 } 5421 void getTargetBuiltins(const Builtin::Info *&Records, 5422 unsigned &NumRecords) const override { 5423 // FIXME: Implement. 5424 Records = nullptr; 5425 NumRecords = 0; 5426 } 5427 5428 void getGCCRegNames(const char *const *&Names, 5429 unsigned &NumNames) const override; 5430 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5431 unsigned &NumAliases) const override { 5432 // No aliases. 5433 Aliases = nullptr; 5434 NumAliases = 0; 5435 } 5436 bool validateAsmConstraint(const char *&Name, 5437 TargetInfo::ConstraintInfo &info) const override; 5438 const char *getClobbers() const override { 5439 // FIXME: Is this really right? 5440 return ""; 5441 } 5442 BuiltinVaListKind getBuiltinVaListKind() const override { 5443 return TargetInfo::SystemZBuiltinVaList; 5444 } 5445 bool setCPU(const std::string &Name) override { 5446 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5447 .Case("z10", true) 5448 .Case("z196", true) 5449 .Case("zEC12", true) 5450 .Default(false); 5451 5452 // No need to store the CPU yet. There aren't any CPU-specific 5453 // macros to define. 5454 return CPUKnown; 5455 } 5456 }; 5457 5458 const char *const SystemZTargetInfo::GCCRegNames[] = { 5459 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5460 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5461 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5462 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5463 }; 5464 5465 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5466 unsigned &NumNames) const { 5467 Names = GCCRegNames; 5468 NumNames = llvm::array_lengthof(GCCRegNames); 5469 } 5470 5471 bool SystemZTargetInfo:: 5472 validateAsmConstraint(const char *&Name, 5473 TargetInfo::ConstraintInfo &Info) const { 5474 switch (*Name) { 5475 default: 5476 return false; 5477 5478 case 'a': // Address register 5479 case 'd': // Data register (equivalent to 'r') 5480 case 'f': // Floating-point register 5481 Info.setAllowsRegister(); 5482 return true; 5483 5484 case 'I': // Unsigned 8-bit constant 5485 case 'J': // Unsigned 12-bit constant 5486 case 'K': // Signed 16-bit constant 5487 case 'L': // Signed 20-bit displacement (on all targets we support) 5488 case 'M': // 0x7fffffff 5489 return true; 5490 5491 case 'Q': // Memory with base and unsigned 12-bit displacement 5492 case 'R': // Likewise, plus an index 5493 case 'S': // Memory with base and signed 20-bit displacement 5494 case 'T': // Likewise, plus an index 5495 Info.setAllowsMemory(); 5496 return true; 5497 } 5498 } 5499 5500 class MSP430TargetInfo : public TargetInfo { 5501 static const char * const GCCRegNames[]; 5502 public: 5503 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5504 BigEndian = false; 5505 TLSSupported = false; 5506 IntWidth = 16; IntAlign = 16; 5507 LongWidth = 32; LongLongWidth = 64; 5508 LongAlign = LongLongAlign = 16; 5509 PointerWidth = 16; PointerAlign = 16; 5510 SuitableAlign = 16; 5511 SizeType = UnsignedInt; 5512 IntMaxType = SignedLongLong; 5513 IntPtrType = SignedInt; 5514 PtrDiffType = SignedInt; 5515 SigAtomicType = SignedLong; 5516 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5517 } 5518 void getTargetDefines(const LangOptions &Opts, 5519 MacroBuilder &Builder) const override { 5520 Builder.defineMacro("MSP430"); 5521 Builder.defineMacro("__MSP430__"); 5522 // FIXME: defines for different 'flavours' of MCU 5523 } 5524 void getTargetBuiltins(const Builtin::Info *&Records, 5525 unsigned &NumRecords) const override { 5526 // FIXME: Implement. 5527 Records = nullptr; 5528 NumRecords = 0; 5529 } 5530 bool hasFeature(StringRef Feature) const override { 5531 return Feature == "msp430"; 5532 } 5533 void getGCCRegNames(const char * const *&Names, 5534 unsigned &NumNames) const override; 5535 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5536 unsigned &NumAliases) const override { 5537 // No aliases. 5538 Aliases = nullptr; 5539 NumAliases = 0; 5540 } 5541 bool 5542 validateAsmConstraint(const char *&Name, 5543 TargetInfo::ConstraintInfo &info) const override { 5544 // FIXME: implement 5545 switch (*Name) { 5546 case 'K': // the constant 1 5547 case 'L': // constant -1^20 .. 1^19 5548 case 'M': // constant 1-4: 5549 return true; 5550 } 5551 // No target constraints for now. 5552 return false; 5553 } 5554 const char *getClobbers() const override { 5555 // FIXME: Is this really right? 5556 return ""; 5557 } 5558 BuiltinVaListKind getBuiltinVaListKind() const override { 5559 // FIXME: implement 5560 return TargetInfo::CharPtrBuiltinVaList; 5561 } 5562 }; 5563 5564 const char * const MSP430TargetInfo::GCCRegNames[] = { 5565 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5566 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5567 }; 5568 5569 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5570 unsigned &NumNames) const { 5571 Names = GCCRegNames; 5572 NumNames = llvm::array_lengthof(GCCRegNames); 5573 } 5574 5575 // LLVM and Clang cannot be used directly to output native binaries for 5576 // target, but is used to compile C code to llvm bitcode with correct 5577 // type and alignment information. 5578 // 5579 // TCE uses the llvm bitcode as input and uses it for generating customized 5580 // target processor and program binary. TCE co-design environment is 5581 // publicly available in http://tce.cs.tut.fi 5582 5583 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5584 3, // opencl_global 5585 4, // opencl_local 5586 5, // opencl_constant 5587 // FIXME: generic has to be added to the target 5588 0, // opencl_generic 5589 0, // cuda_device 5590 0, // cuda_constant 5591 0 // cuda_shared 5592 }; 5593 5594 class TCETargetInfo : public TargetInfo{ 5595 public: 5596 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5597 TLSSupported = false; 5598 IntWidth = 32; 5599 LongWidth = LongLongWidth = 32; 5600 PointerWidth = 32; 5601 IntAlign = 32; 5602 LongAlign = LongLongAlign = 32; 5603 PointerAlign = 32; 5604 SuitableAlign = 32; 5605 SizeType = UnsignedInt; 5606 IntMaxType = SignedLong; 5607 IntPtrType = SignedInt; 5608 PtrDiffType = SignedInt; 5609 FloatWidth = 32; 5610 FloatAlign = 32; 5611 DoubleWidth = 32; 5612 DoubleAlign = 32; 5613 LongDoubleWidth = 32; 5614 LongDoubleAlign = 32; 5615 FloatFormat = &llvm::APFloat::IEEEsingle; 5616 DoubleFormat = &llvm::APFloat::IEEEsingle; 5617 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5618 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5619 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5620 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5621 UseAddrSpaceMapMangling = true; 5622 } 5623 5624 void getTargetDefines(const LangOptions &Opts, 5625 MacroBuilder &Builder) const override { 5626 DefineStd(Builder, "tce", Opts); 5627 Builder.defineMacro("__TCE__"); 5628 Builder.defineMacro("__TCE_V1__"); 5629 } 5630 bool hasFeature(StringRef Feature) const override { 5631 return Feature == "tce"; 5632 } 5633 5634 void getTargetBuiltins(const Builtin::Info *&Records, 5635 unsigned &NumRecords) const override {} 5636 const char *getClobbers() const override { 5637 return ""; 5638 } 5639 BuiltinVaListKind getBuiltinVaListKind() const override { 5640 return TargetInfo::VoidPtrBuiltinVaList; 5641 } 5642 void getGCCRegNames(const char * const *&Names, 5643 unsigned &NumNames) const override {} 5644 bool validateAsmConstraint(const char *&Name, 5645 TargetInfo::ConstraintInfo &info) const override{ 5646 return true; 5647 } 5648 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5649 unsigned &NumAliases) const override {} 5650 }; 5651 5652 class MipsTargetInfoBase : public TargetInfo { 5653 virtual void setDescriptionString() = 0; 5654 5655 static const Builtin::Info BuiltinInfo[]; 5656 std::string CPU; 5657 bool IsMips16; 5658 bool IsMicromips; 5659 bool IsNan2008; 5660 bool IsSingleFloat; 5661 enum MipsFloatABI { 5662 HardFloat, SoftFloat 5663 } FloatABI; 5664 enum DspRevEnum { 5665 NoDSP, DSP1, DSP2 5666 } DspRev; 5667 bool HasMSA; 5668 5669 protected: 5670 bool HasFP64; 5671 std::string ABI; 5672 5673 public: 5674 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5675 const std::string &CPUStr) 5676 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5677 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5678 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5679 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5680 } 5681 5682 bool isNaN2008Default() const { 5683 return CPU == "mips32r6" || CPU == "mips64r6"; 5684 } 5685 5686 bool isFP64Default() const { 5687 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5688 } 5689 5690 bool isNan2008() const override { 5691 return IsNan2008; 5692 } 5693 5694 StringRef getABI() const override { return ABI; } 5695 bool setCPU(const std::string &Name) override { 5696 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5697 getTriple().getArch() == llvm::Triple::mipsel; 5698 CPU = Name; 5699 return llvm::StringSwitch<bool>(Name) 5700 .Case("mips1", IsMips32) 5701 .Case("mips2", IsMips32) 5702 .Case("mips3", true) 5703 .Case("mips4", true) 5704 .Case("mips5", true) 5705 .Case("mips32", IsMips32) 5706 .Case("mips32r2", IsMips32) 5707 .Case("mips32r3", IsMips32) 5708 .Case("mips32r5", IsMips32) 5709 .Case("mips32r6", IsMips32) 5710 .Case("mips64", true) 5711 .Case("mips64r2", true) 5712 .Case("mips64r3", true) 5713 .Case("mips64r5", true) 5714 .Case("mips64r6", true) 5715 .Case("octeon", true) 5716 .Default(false); 5717 } 5718 const std::string& getCPU() const { return CPU; } 5719 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5720 if (CPU == "octeon") 5721 Features["mips64r2"] = Features["cnmips"] = true; 5722 else 5723 Features[CPU] = true; 5724 } 5725 5726 void getTargetDefines(const LangOptions &Opts, 5727 MacroBuilder &Builder) const override { 5728 Builder.defineMacro("__mips__"); 5729 Builder.defineMacro("_mips"); 5730 if (Opts.GNUMode) 5731 Builder.defineMacro("mips"); 5732 5733 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5734 5735 switch (FloatABI) { 5736 case HardFloat: 5737 Builder.defineMacro("__mips_hard_float", Twine(1)); 5738 break; 5739 case SoftFloat: 5740 Builder.defineMacro("__mips_soft_float", Twine(1)); 5741 break; 5742 } 5743 5744 if (IsSingleFloat) 5745 Builder.defineMacro("__mips_single_float", Twine(1)); 5746 5747 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5748 Builder.defineMacro("_MIPS_FPSET", 5749 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5750 5751 if (IsMips16) 5752 Builder.defineMacro("__mips16", Twine(1)); 5753 5754 if (IsMicromips) 5755 Builder.defineMacro("__mips_micromips", Twine(1)); 5756 5757 if (IsNan2008) 5758 Builder.defineMacro("__mips_nan2008", Twine(1)); 5759 5760 switch (DspRev) { 5761 default: 5762 break; 5763 case DSP1: 5764 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5765 Builder.defineMacro("__mips_dsp", Twine(1)); 5766 break; 5767 case DSP2: 5768 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5769 Builder.defineMacro("__mips_dspr2", Twine(1)); 5770 Builder.defineMacro("__mips_dsp", Twine(1)); 5771 break; 5772 } 5773 5774 if (HasMSA) 5775 Builder.defineMacro("__mips_msa", Twine(1)); 5776 5777 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5778 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5779 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5780 5781 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5782 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5783 } 5784 5785 void getTargetBuiltins(const Builtin::Info *&Records, 5786 unsigned &NumRecords) const override { 5787 Records = BuiltinInfo; 5788 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5789 } 5790 bool hasFeature(StringRef Feature) const override { 5791 return llvm::StringSwitch<bool>(Feature) 5792 .Case("mips", true) 5793 .Case("fp64", HasFP64) 5794 .Default(false); 5795 } 5796 BuiltinVaListKind getBuiltinVaListKind() const override { 5797 return TargetInfo::VoidPtrBuiltinVaList; 5798 } 5799 void getGCCRegNames(const char * const *&Names, 5800 unsigned &NumNames) const override { 5801 static const char *const GCCRegNames[] = { 5802 // CPU register names 5803 // Must match second column of GCCRegAliases 5804 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5805 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5806 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5807 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5808 // Floating point register names 5809 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5810 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5811 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5812 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5813 // Hi/lo and condition register names 5814 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5815 "$fcc5","$fcc6","$fcc7", 5816 // MSA register names 5817 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5818 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5819 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5820 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5821 // MSA control register names 5822 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5823 "$msarequest", "$msamap", "$msaunmap" 5824 }; 5825 Names = GCCRegNames; 5826 NumNames = llvm::array_lengthof(GCCRegNames); 5827 } 5828 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5829 unsigned &NumAliases) const override = 0; 5830 bool validateAsmConstraint(const char *&Name, 5831 TargetInfo::ConstraintInfo &Info) const override { 5832 switch (*Name) { 5833 default: 5834 return false; 5835 case 'r': // CPU registers. 5836 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5837 case 'y': // Equivalent to "r", backward compatibility only. 5838 case 'f': // floating-point registers. 5839 case 'c': // $25 for indirect jumps 5840 case 'l': // lo register 5841 case 'x': // hilo register pair 5842 Info.setAllowsRegister(); 5843 return true; 5844 case 'I': // Signed 16-bit constant 5845 case 'J': // Integer 0 5846 case 'K': // Unsigned 16-bit constant 5847 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 5848 case 'M': // Constants not loadable via lui, addiu, or ori 5849 case 'N': // Constant -1 to -65535 5850 case 'O': // A signed 15-bit constant 5851 case 'P': // A constant between 1 go 65535 5852 return true; 5853 case 'R': // An address that can be used in a non-macro load or store 5854 Info.setAllowsMemory(); 5855 return true; 5856 } 5857 } 5858 5859 const char *getClobbers() const override { 5860 // In GCC, $1 is not widely used in generated code (it's used only in a few 5861 // specific situations), so there is no real need for users to add it to 5862 // the clobbers list if they want to use it in their inline assembly code. 5863 // 5864 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 5865 // code generation, so using it in inline assembly without adding it to the 5866 // clobbers list can cause conflicts between the inline assembly code and 5867 // the surrounding generated code. 5868 // 5869 // Another problem is that LLVM is allowed to choose $1 for inline assembly 5870 // operands, which will conflict with the ".set at" assembler option (which 5871 // we use only for inline assembly, in order to maintain compatibility with 5872 // GCC) and will also conflict with the user's usage of $1. 5873 // 5874 // The easiest way to avoid these conflicts and keep $1 as an allocatable 5875 // register for generated code is to automatically clobber $1 for all inline 5876 // assembly code. 5877 // 5878 // FIXME: We should automatically clobber $1 only for inline assembly code 5879 // which actually uses it. This would allow LLVM to use $1 for inline 5880 // assembly operands if the user's assembly code doesn't use it. 5881 return "~{$1}"; 5882 } 5883 5884 bool handleTargetFeatures(std::vector<std::string> &Features, 5885 DiagnosticsEngine &Diags) override { 5886 IsMips16 = false; 5887 IsMicromips = false; 5888 IsNan2008 = isNaN2008Default(); 5889 IsSingleFloat = false; 5890 FloatABI = HardFloat; 5891 DspRev = NoDSP; 5892 HasFP64 = isFP64Default(); 5893 5894 for (std::vector<std::string>::iterator it = Features.begin(), 5895 ie = Features.end(); it != ie; ++it) { 5896 if (*it == "+single-float") 5897 IsSingleFloat = true; 5898 else if (*it == "+soft-float") 5899 FloatABI = SoftFloat; 5900 else if (*it == "+mips16") 5901 IsMips16 = true; 5902 else if (*it == "+micromips") 5903 IsMicromips = true; 5904 else if (*it == "+dsp") 5905 DspRev = std::max(DspRev, DSP1); 5906 else if (*it == "+dspr2") 5907 DspRev = std::max(DspRev, DSP2); 5908 else if (*it == "+msa") 5909 HasMSA = true; 5910 else if (*it == "+fp64") 5911 HasFP64 = true; 5912 else if (*it == "-fp64") 5913 HasFP64 = false; 5914 else if (*it == "+nan2008") 5915 IsNan2008 = true; 5916 else if (*it == "-nan2008") 5917 IsNan2008 = false; 5918 } 5919 5920 // Remove front-end specific options. 5921 std::vector<std::string>::iterator it = 5922 std::find(Features.begin(), Features.end(), "+soft-float"); 5923 if (it != Features.end()) 5924 Features.erase(it); 5925 5926 setDescriptionString(); 5927 5928 return true; 5929 } 5930 5931 int getEHDataRegisterNumber(unsigned RegNo) const override { 5932 if (RegNo == 0) return 4; 5933 if (RegNo == 1) return 5; 5934 return -1; 5935 } 5936 5937 bool isCLZForZeroUndef() const override { return false; } 5938 }; 5939 5940 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5941 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5942 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5943 ALL_LANGUAGES }, 5944 #include "clang/Basic/BuiltinsMips.def" 5945 }; 5946 5947 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5948 public: 5949 Mips32TargetInfoBase(const llvm::Triple &Triple) 5950 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5951 SizeType = UnsignedInt; 5952 PtrDiffType = SignedInt; 5953 Int64Type = SignedLongLong; 5954 IntMaxType = Int64Type; 5955 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5956 } 5957 bool setABI(const std::string &Name) override { 5958 if (Name == "o32" || Name == "eabi") { 5959 ABI = Name; 5960 return true; 5961 } 5962 return false; 5963 } 5964 void getTargetDefines(const LangOptions &Opts, 5965 MacroBuilder &Builder) const override { 5966 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5967 5968 Builder.defineMacro("__mips", "32"); 5969 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5970 5971 const std::string& CPUStr = getCPU(); 5972 if (CPUStr == "mips32") 5973 Builder.defineMacro("__mips_isa_rev", "1"); 5974 else if (CPUStr == "mips32r2") 5975 Builder.defineMacro("__mips_isa_rev", "2"); 5976 else if (CPUStr == "mips32r3") 5977 Builder.defineMacro("__mips_isa_rev", "3"); 5978 else if (CPUStr == "mips32r5") 5979 Builder.defineMacro("__mips_isa_rev", "5"); 5980 else if (CPUStr == "mips32r6") 5981 Builder.defineMacro("__mips_isa_rev", "6"); 5982 5983 if (ABI == "o32") { 5984 Builder.defineMacro("__mips_o32"); 5985 Builder.defineMacro("_ABIO32", "1"); 5986 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5987 } 5988 else if (ABI == "eabi") 5989 Builder.defineMacro("__mips_eabi"); 5990 else 5991 llvm_unreachable("Invalid ABI for Mips32."); 5992 } 5993 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5994 unsigned &NumAliases) const override { 5995 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5996 { { "at" }, "$1" }, 5997 { { "v0" }, "$2" }, 5998 { { "v1" }, "$3" }, 5999 { { "a0" }, "$4" }, 6000 { { "a1" }, "$5" }, 6001 { { "a2" }, "$6" }, 6002 { { "a3" }, "$7" }, 6003 { { "t0" }, "$8" }, 6004 { { "t1" }, "$9" }, 6005 { { "t2" }, "$10" }, 6006 { { "t3" }, "$11" }, 6007 { { "t4" }, "$12" }, 6008 { { "t5" }, "$13" }, 6009 { { "t6" }, "$14" }, 6010 { { "t7" }, "$15" }, 6011 { { "s0" }, "$16" }, 6012 { { "s1" }, "$17" }, 6013 { { "s2" }, "$18" }, 6014 { { "s3" }, "$19" }, 6015 { { "s4" }, "$20" }, 6016 { { "s5" }, "$21" }, 6017 { { "s6" }, "$22" }, 6018 { { "s7" }, "$23" }, 6019 { { "t8" }, "$24" }, 6020 { { "t9" }, "$25" }, 6021 { { "k0" }, "$26" }, 6022 { { "k1" }, "$27" }, 6023 { { "gp" }, "$28" }, 6024 { { "sp","$sp" }, "$29" }, 6025 { { "fp","$fp" }, "$30" }, 6026 { { "ra" }, "$31" } 6027 }; 6028 Aliases = GCCRegAliases; 6029 NumAliases = llvm::array_lengthof(GCCRegAliases); 6030 } 6031 }; 6032 6033 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6034 void setDescriptionString() override { 6035 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6036 } 6037 6038 public: 6039 Mips32EBTargetInfo(const llvm::Triple &Triple) 6040 : Mips32TargetInfoBase(Triple) { 6041 } 6042 void getTargetDefines(const LangOptions &Opts, 6043 MacroBuilder &Builder) const override { 6044 DefineStd(Builder, "MIPSEB", Opts); 6045 Builder.defineMacro("_MIPSEB"); 6046 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6047 } 6048 }; 6049 6050 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6051 void setDescriptionString() override { 6052 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6053 } 6054 6055 public: 6056 Mips32ELTargetInfo(const llvm::Triple &Triple) 6057 : Mips32TargetInfoBase(Triple) { 6058 BigEndian = false; 6059 } 6060 void getTargetDefines(const LangOptions &Opts, 6061 MacroBuilder &Builder) const override { 6062 DefineStd(Builder, "MIPSEL", Opts); 6063 Builder.defineMacro("_MIPSEL"); 6064 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6065 } 6066 }; 6067 6068 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6069 public: 6070 Mips64TargetInfoBase(const llvm::Triple &Triple) 6071 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6072 LongDoubleWidth = LongDoubleAlign = 128; 6073 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6074 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6075 LongDoubleWidth = LongDoubleAlign = 64; 6076 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6077 } 6078 setN64ABITypes(); 6079 SuitableAlign = 128; 6080 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6081 } 6082 6083 void setN64ABITypes() { 6084 LongWidth = LongAlign = 64; 6085 PointerWidth = PointerAlign = 64; 6086 SizeType = UnsignedLong; 6087 PtrDiffType = SignedLong; 6088 Int64Type = SignedLong; 6089 IntMaxType = Int64Type; 6090 } 6091 6092 void setN32ABITypes() { 6093 LongWidth = LongAlign = 32; 6094 PointerWidth = PointerAlign = 32; 6095 SizeType = UnsignedInt; 6096 PtrDiffType = SignedInt; 6097 Int64Type = SignedLongLong; 6098 IntMaxType = Int64Type; 6099 } 6100 6101 bool setABI(const std::string &Name) override { 6102 if (Name == "n32") { 6103 setN32ABITypes(); 6104 ABI = Name; 6105 return true; 6106 } 6107 if (Name == "n64") { 6108 setN64ABITypes(); 6109 ABI = Name; 6110 return true; 6111 } 6112 return false; 6113 } 6114 6115 void getTargetDefines(const LangOptions &Opts, 6116 MacroBuilder &Builder) const override { 6117 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6118 6119 Builder.defineMacro("__mips", "64"); 6120 Builder.defineMacro("__mips64"); 6121 Builder.defineMacro("__mips64__"); 6122 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6123 6124 const std::string& CPUStr = getCPU(); 6125 if (CPUStr == "mips64") 6126 Builder.defineMacro("__mips_isa_rev", "1"); 6127 else if (CPUStr == "mips64r2") 6128 Builder.defineMacro("__mips_isa_rev", "2"); 6129 else if (CPUStr == "mips64r3") 6130 Builder.defineMacro("__mips_isa_rev", "3"); 6131 else if (CPUStr == "mips64r5") 6132 Builder.defineMacro("__mips_isa_rev", "5"); 6133 else if (CPUStr == "mips64r6") 6134 Builder.defineMacro("__mips_isa_rev", "6"); 6135 6136 if (ABI == "n32") { 6137 Builder.defineMacro("__mips_n32"); 6138 Builder.defineMacro("_ABIN32", "2"); 6139 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6140 } 6141 else if (ABI == "n64") { 6142 Builder.defineMacro("__mips_n64"); 6143 Builder.defineMacro("_ABI64", "3"); 6144 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6145 } 6146 else 6147 llvm_unreachable("Invalid ABI for Mips64."); 6148 } 6149 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6150 unsigned &NumAliases) const override { 6151 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6152 { { "at" }, "$1" }, 6153 { { "v0" }, "$2" }, 6154 { { "v1" }, "$3" }, 6155 { { "a0" }, "$4" }, 6156 { { "a1" }, "$5" }, 6157 { { "a2" }, "$6" }, 6158 { { "a3" }, "$7" }, 6159 { { "a4" }, "$8" }, 6160 { { "a5" }, "$9" }, 6161 { { "a6" }, "$10" }, 6162 { { "a7" }, "$11" }, 6163 { { "t0" }, "$12" }, 6164 { { "t1" }, "$13" }, 6165 { { "t2" }, "$14" }, 6166 { { "t3" }, "$15" }, 6167 { { "s0" }, "$16" }, 6168 { { "s1" }, "$17" }, 6169 { { "s2" }, "$18" }, 6170 { { "s3" }, "$19" }, 6171 { { "s4" }, "$20" }, 6172 { { "s5" }, "$21" }, 6173 { { "s6" }, "$22" }, 6174 { { "s7" }, "$23" }, 6175 { { "t8" }, "$24" }, 6176 { { "t9" }, "$25" }, 6177 { { "k0" }, "$26" }, 6178 { { "k1" }, "$27" }, 6179 { { "gp" }, "$28" }, 6180 { { "sp","$sp" }, "$29" }, 6181 { { "fp","$fp" }, "$30" }, 6182 { { "ra" }, "$31" } 6183 }; 6184 Aliases = GCCRegAliases; 6185 NumAliases = llvm::array_lengthof(GCCRegAliases); 6186 } 6187 6188 bool hasInt128Type() const override { return true; } 6189 }; 6190 6191 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6192 void setDescriptionString() override { 6193 if (ABI == "n32") 6194 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6195 else 6196 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6197 6198 } 6199 6200 public: 6201 Mips64EBTargetInfo(const llvm::Triple &Triple) 6202 : Mips64TargetInfoBase(Triple) {} 6203 void getTargetDefines(const LangOptions &Opts, 6204 MacroBuilder &Builder) const override { 6205 DefineStd(Builder, "MIPSEB", Opts); 6206 Builder.defineMacro("_MIPSEB"); 6207 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6208 } 6209 }; 6210 6211 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6212 void setDescriptionString() override { 6213 if (ABI == "n32") 6214 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6215 else 6216 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6217 } 6218 public: 6219 Mips64ELTargetInfo(const llvm::Triple &Triple) 6220 : Mips64TargetInfoBase(Triple) { 6221 // Default ABI is n64. 6222 BigEndian = false; 6223 } 6224 void getTargetDefines(const LangOptions &Opts, 6225 MacroBuilder &Builder) const override { 6226 DefineStd(Builder, "MIPSEL", Opts); 6227 Builder.defineMacro("_MIPSEL"); 6228 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6229 } 6230 }; 6231 6232 class PNaClTargetInfo : public TargetInfo { 6233 public: 6234 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6235 BigEndian = false; 6236 this->UserLabelPrefix = ""; 6237 this->LongAlign = 32; 6238 this->LongWidth = 32; 6239 this->PointerAlign = 32; 6240 this->PointerWidth = 32; 6241 this->IntMaxType = TargetInfo::SignedLongLong; 6242 this->Int64Type = TargetInfo::SignedLongLong; 6243 this->DoubleAlign = 64; 6244 this->LongDoubleWidth = 64; 6245 this->LongDoubleAlign = 64; 6246 this->SizeType = TargetInfo::UnsignedInt; 6247 this->PtrDiffType = TargetInfo::SignedInt; 6248 this->IntPtrType = TargetInfo::SignedInt; 6249 this->RegParmMax = 0; // Disallow regparm 6250 } 6251 6252 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6253 } 6254 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6255 Builder.defineMacro("__le32__"); 6256 Builder.defineMacro("__pnacl__"); 6257 } 6258 void getTargetDefines(const LangOptions &Opts, 6259 MacroBuilder &Builder) const override { 6260 getArchDefines(Opts, Builder); 6261 } 6262 bool hasFeature(StringRef Feature) const override { 6263 return Feature == "pnacl"; 6264 } 6265 void getTargetBuiltins(const Builtin::Info *&Records, 6266 unsigned &NumRecords) const override { 6267 } 6268 BuiltinVaListKind getBuiltinVaListKind() const override { 6269 return TargetInfo::PNaClABIBuiltinVaList; 6270 } 6271 void getGCCRegNames(const char * const *&Names, 6272 unsigned &NumNames) const override; 6273 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6274 unsigned &NumAliases) const override; 6275 bool validateAsmConstraint(const char *&Name, 6276 TargetInfo::ConstraintInfo &Info) const override { 6277 return false; 6278 } 6279 6280 const char *getClobbers() const override { 6281 return ""; 6282 } 6283 }; 6284 6285 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6286 unsigned &NumNames) const { 6287 Names = nullptr; 6288 NumNames = 0; 6289 } 6290 6291 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6292 unsigned &NumAliases) const { 6293 Aliases = nullptr; 6294 NumAliases = 0; 6295 } 6296 6297 class Le64TargetInfo : public TargetInfo { 6298 static const Builtin::Info BuiltinInfo[]; 6299 6300 public: 6301 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6302 BigEndian = false; 6303 NoAsmVariants = true; 6304 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6305 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6306 DescriptionString = 6307 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6308 } 6309 6310 void getTargetDefines(const LangOptions &Opts, 6311 MacroBuilder &Builder) const override { 6312 DefineStd(Builder, "unix", Opts); 6313 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6314 Builder.defineMacro("__ELF__"); 6315 } 6316 void getTargetBuiltins(const Builtin::Info *&Records, 6317 unsigned &NumRecords) const override { 6318 Records = BuiltinInfo; 6319 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6320 } 6321 BuiltinVaListKind getBuiltinVaListKind() const override { 6322 return TargetInfo::PNaClABIBuiltinVaList; 6323 } 6324 const char *getClobbers() const override { return ""; } 6325 void getGCCRegNames(const char *const *&Names, 6326 unsigned &NumNames) const override { 6327 Names = nullptr; 6328 NumNames = 0; 6329 } 6330 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6331 unsigned &NumAliases) const override { 6332 Aliases = nullptr; 6333 NumAliases = 0; 6334 } 6335 bool validateAsmConstraint(const char *&Name, 6336 TargetInfo::ConstraintInfo &Info) const override { 6337 return false; 6338 } 6339 6340 bool hasProtectedVisibility() const override { return false; } 6341 }; 6342 } // end anonymous namespace. 6343 6344 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6345 #define BUILTIN(ID, TYPE, ATTRS) \ 6346 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6347 #include "clang/Basic/BuiltinsLe64.def" 6348 }; 6349 6350 namespace { 6351 static const unsigned SPIRAddrSpaceMap[] = { 6352 1, // opencl_global 6353 3, // opencl_local 6354 2, // opencl_constant 6355 4, // opencl_generic 6356 0, // cuda_device 6357 0, // cuda_constant 6358 0 // cuda_shared 6359 }; 6360 class SPIRTargetInfo : public TargetInfo { 6361 public: 6362 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6363 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6364 "SPIR target must use unknown OS"); 6365 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6366 "SPIR target must use unknown environment type"); 6367 BigEndian = false; 6368 TLSSupported = false; 6369 LongWidth = LongAlign = 64; 6370 AddrSpaceMap = &SPIRAddrSpaceMap; 6371 UseAddrSpaceMapMangling = true; 6372 // Define available target features 6373 // These must be defined in sorted order! 6374 NoAsmVariants = true; 6375 } 6376 void getTargetDefines(const LangOptions &Opts, 6377 MacroBuilder &Builder) const override { 6378 DefineStd(Builder, "SPIR", Opts); 6379 } 6380 bool hasFeature(StringRef Feature) const override { 6381 return Feature == "spir"; 6382 } 6383 6384 void getTargetBuiltins(const Builtin::Info *&Records, 6385 unsigned &NumRecords) const override {} 6386 const char *getClobbers() const override { 6387 return ""; 6388 } 6389 void getGCCRegNames(const char * const *&Names, 6390 unsigned &NumNames) const override {} 6391 bool 6392 validateAsmConstraint(const char *&Name, 6393 TargetInfo::ConstraintInfo &info) const override { 6394 return true; 6395 } 6396 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6397 unsigned &NumAliases) const override {} 6398 BuiltinVaListKind getBuiltinVaListKind() const override { 6399 return TargetInfo::VoidPtrBuiltinVaList; 6400 } 6401 6402 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6403 return (CC == CC_SpirFunction || 6404 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6405 } 6406 6407 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6408 return CC_SpirFunction; 6409 } 6410 }; 6411 6412 6413 class SPIR32TargetInfo : public SPIRTargetInfo { 6414 public: 6415 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6416 PointerWidth = PointerAlign = 32; 6417 SizeType = TargetInfo::UnsignedInt; 6418 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6419 DescriptionString 6420 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6421 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6422 } 6423 void getTargetDefines(const LangOptions &Opts, 6424 MacroBuilder &Builder) const override { 6425 DefineStd(Builder, "SPIR32", Opts); 6426 } 6427 }; 6428 6429 class SPIR64TargetInfo : public SPIRTargetInfo { 6430 public: 6431 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6432 PointerWidth = PointerAlign = 64; 6433 SizeType = TargetInfo::UnsignedLong; 6434 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6435 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6436 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6437 } 6438 void getTargetDefines(const LangOptions &Opts, 6439 MacroBuilder &Builder) const override { 6440 DefineStd(Builder, "SPIR64", Opts); 6441 } 6442 }; 6443 6444 class XCoreTargetInfo : public TargetInfo { 6445 static const Builtin::Info BuiltinInfo[]; 6446 public: 6447 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6448 BigEndian = false; 6449 NoAsmVariants = true; 6450 LongLongAlign = 32; 6451 SuitableAlign = 32; 6452 DoubleAlign = LongDoubleAlign = 32; 6453 SizeType = UnsignedInt; 6454 PtrDiffType = SignedInt; 6455 IntPtrType = SignedInt; 6456 WCharType = UnsignedChar; 6457 WIntType = UnsignedInt; 6458 UseZeroLengthBitfieldAlignment = true; 6459 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6460 "-f64:32-a:0:32-n32"; 6461 } 6462 void getTargetDefines(const LangOptions &Opts, 6463 MacroBuilder &Builder) const override { 6464 Builder.defineMacro("__XS1B__"); 6465 } 6466 void getTargetBuiltins(const Builtin::Info *&Records, 6467 unsigned &NumRecords) const override { 6468 Records = BuiltinInfo; 6469 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6470 } 6471 BuiltinVaListKind getBuiltinVaListKind() const override { 6472 return TargetInfo::VoidPtrBuiltinVaList; 6473 } 6474 const char *getClobbers() const override { 6475 return ""; 6476 } 6477 void getGCCRegNames(const char * const *&Names, 6478 unsigned &NumNames) const override { 6479 static const char * const GCCRegNames[] = { 6480 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6481 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6482 }; 6483 Names = GCCRegNames; 6484 NumNames = llvm::array_lengthof(GCCRegNames); 6485 } 6486 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6487 unsigned &NumAliases) const override { 6488 Aliases = nullptr; 6489 NumAliases = 0; 6490 } 6491 bool validateAsmConstraint(const char *&Name, 6492 TargetInfo::ConstraintInfo &Info) const override { 6493 return false; 6494 } 6495 int getEHDataRegisterNumber(unsigned RegNo) const override { 6496 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6497 return (RegNo < 2)? RegNo : -1; 6498 } 6499 }; 6500 6501 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6502 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6503 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6504 ALL_LANGUAGES }, 6505 #include "clang/Basic/BuiltinsXCore.def" 6506 }; 6507 } // end anonymous namespace. 6508 6509 6510 //===----------------------------------------------------------------------===// 6511 // Driver code 6512 //===----------------------------------------------------------------------===// 6513 6514 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6515 llvm::Triple::OSType os = Triple.getOS(); 6516 6517 switch (Triple.getArch()) { 6518 default: 6519 return nullptr; 6520 6521 case llvm::Triple::xcore: 6522 return new XCoreTargetInfo(Triple); 6523 6524 case llvm::Triple::hexagon: 6525 return new HexagonTargetInfo(Triple); 6526 6527 case llvm::Triple::aarch64: 6528 if (Triple.isOSDarwin()) 6529 return new DarwinAArch64TargetInfo(Triple); 6530 6531 switch (os) { 6532 case llvm::Triple::FreeBSD: 6533 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6534 case llvm::Triple::Linux: 6535 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6536 case llvm::Triple::NetBSD: 6537 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6538 default: 6539 return new AArch64leTargetInfo(Triple); 6540 } 6541 6542 case llvm::Triple::aarch64_be: 6543 switch (os) { 6544 case llvm::Triple::FreeBSD: 6545 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6546 case llvm::Triple::Linux: 6547 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6548 case llvm::Triple::NetBSD: 6549 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6550 default: 6551 return new AArch64beTargetInfo(Triple); 6552 } 6553 6554 case llvm::Triple::arm: 6555 case llvm::Triple::thumb: 6556 if (Triple.isOSBinFormatMachO()) 6557 return new DarwinARMTargetInfo(Triple); 6558 6559 switch (os) { 6560 case llvm::Triple::Linux: 6561 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6562 case llvm::Triple::FreeBSD: 6563 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6564 case llvm::Triple::NetBSD: 6565 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6566 case llvm::Triple::OpenBSD: 6567 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6568 case llvm::Triple::Bitrig: 6569 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6570 case llvm::Triple::RTEMS: 6571 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6572 case llvm::Triple::NaCl: 6573 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6574 case llvm::Triple::Win32: 6575 switch (Triple.getEnvironment()) { 6576 default: 6577 return new ARMleTargetInfo(Triple); 6578 case llvm::Triple::Itanium: 6579 return new ItaniumWindowsARMleTargetInfo(Triple); 6580 case llvm::Triple::MSVC: 6581 return new MicrosoftARMleTargetInfo(Triple); 6582 } 6583 default: 6584 return new ARMleTargetInfo(Triple); 6585 } 6586 6587 case llvm::Triple::armeb: 6588 case llvm::Triple::thumbeb: 6589 if (Triple.isOSDarwin()) 6590 return new DarwinARMTargetInfo(Triple); 6591 6592 switch (os) { 6593 case llvm::Triple::Linux: 6594 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6595 case llvm::Triple::FreeBSD: 6596 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6597 case llvm::Triple::NetBSD: 6598 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6599 case llvm::Triple::OpenBSD: 6600 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6601 case llvm::Triple::Bitrig: 6602 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6603 case llvm::Triple::RTEMS: 6604 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6605 case llvm::Triple::NaCl: 6606 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6607 default: 6608 return new ARMbeTargetInfo(Triple); 6609 } 6610 6611 case llvm::Triple::msp430: 6612 return new MSP430TargetInfo(Triple); 6613 6614 case llvm::Triple::mips: 6615 switch (os) { 6616 case llvm::Triple::Linux: 6617 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6618 case llvm::Triple::RTEMS: 6619 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6620 case llvm::Triple::FreeBSD: 6621 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6622 case llvm::Triple::NetBSD: 6623 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6624 default: 6625 return new Mips32EBTargetInfo(Triple); 6626 } 6627 6628 case llvm::Triple::mipsel: 6629 switch (os) { 6630 case llvm::Triple::Linux: 6631 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6632 case llvm::Triple::RTEMS: 6633 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6634 case llvm::Triple::FreeBSD: 6635 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6636 case llvm::Triple::NetBSD: 6637 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6638 case llvm::Triple::NaCl: 6639 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6640 default: 6641 return new Mips32ELTargetInfo(Triple); 6642 } 6643 6644 case llvm::Triple::mips64: 6645 switch (os) { 6646 case llvm::Triple::Linux: 6647 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6648 case llvm::Triple::RTEMS: 6649 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6650 case llvm::Triple::FreeBSD: 6651 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6652 case llvm::Triple::NetBSD: 6653 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6654 case llvm::Triple::OpenBSD: 6655 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6656 default: 6657 return new Mips64EBTargetInfo(Triple); 6658 } 6659 6660 case llvm::Triple::mips64el: 6661 switch (os) { 6662 case llvm::Triple::Linux: 6663 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6664 case llvm::Triple::RTEMS: 6665 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6666 case llvm::Triple::FreeBSD: 6667 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6668 case llvm::Triple::NetBSD: 6669 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6670 case llvm::Triple::OpenBSD: 6671 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6672 default: 6673 return new Mips64ELTargetInfo(Triple); 6674 } 6675 6676 case llvm::Triple::le32: 6677 switch (os) { 6678 case llvm::Triple::NaCl: 6679 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6680 default: 6681 return nullptr; 6682 } 6683 6684 case llvm::Triple::le64: 6685 return new Le64TargetInfo(Triple); 6686 6687 case llvm::Triple::ppc: 6688 if (Triple.isOSDarwin()) 6689 return new DarwinPPC32TargetInfo(Triple); 6690 switch (os) { 6691 case llvm::Triple::Linux: 6692 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6693 case llvm::Triple::FreeBSD: 6694 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6695 case llvm::Triple::NetBSD: 6696 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6697 case llvm::Triple::OpenBSD: 6698 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6699 case llvm::Triple::RTEMS: 6700 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6701 default: 6702 return new PPC32TargetInfo(Triple); 6703 } 6704 6705 case llvm::Triple::ppc64: 6706 if (Triple.isOSDarwin()) 6707 return new DarwinPPC64TargetInfo(Triple); 6708 switch (os) { 6709 case llvm::Triple::Linux: 6710 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6711 case llvm::Triple::Lv2: 6712 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6713 case llvm::Triple::FreeBSD: 6714 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6715 case llvm::Triple::NetBSD: 6716 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6717 default: 6718 return new PPC64TargetInfo(Triple); 6719 } 6720 6721 case llvm::Triple::ppc64le: 6722 switch (os) { 6723 case llvm::Triple::Linux: 6724 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6725 default: 6726 return new PPC64TargetInfo(Triple); 6727 } 6728 6729 case llvm::Triple::nvptx: 6730 return new NVPTX32TargetInfo(Triple); 6731 case llvm::Triple::nvptx64: 6732 return new NVPTX64TargetInfo(Triple); 6733 6734 case llvm::Triple::amdgcn: 6735 case llvm::Triple::r600: 6736 return new R600TargetInfo(Triple); 6737 6738 case llvm::Triple::sparc: 6739 switch (os) { 6740 case llvm::Triple::Linux: 6741 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6742 case llvm::Triple::Solaris: 6743 return new SolarisSparcV8TargetInfo(Triple); 6744 case llvm::Triple::NetBSD: 6745 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6746 case llvm::Triple::OpenBSD: 6747 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6748 case llvm::Triple::RTEMS: 6749 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6750 default: 6751 return new SparcV8TargetInfo(Triple); 6752 } 6753 6754 case llvm::Triple::sparcv9: 6755 switch (os) { 6756 case llvm::Triple::Linux: 6757 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6758 case llvm::Triple::Solaris: 6759 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6760 case llvm::Triple::NetBSD: 6761 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6762 case llvm::Triple::OpenBSD: 6763 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6764 case llvm::Triple::FreeBSD: 6765 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6766 default: 6767 return new SparcV9TargetInfo(Triple); 6768 } 6769 6770 case llvm::Triple::systemz: 6771 switch (os) { 6772 case llvm::Triple::Linux: 6773 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6774 default: 6775 return new SystemZTargetInfo(Triple); 6776 } 6777 6778 case llvm::Triple::tce: 6779 return new TCETargetInfo(Triple); 6780 6781 case llvm::Triple::x86: 6782 if (Triple.isOSDarwin()) 6783 return new DarwinI386TargetInfo(Triple); 6784 6785 switch (os) { 6786 case llvm::Triple::Linux: 6787 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6788 case llvm::Triple::DragonFly: 6789 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6790 case llvm::Triple::NetBSD: 6791 return new NetBSDI386TargetInfo(Triple); 6792 case llvm::Triple::OpenBSD: 6793 return new OpenBSDI386TargetInfo(Triple); 6794 case llvm::Triple::Bitrig: 6795 return new BitrigI386TargetInfo(Triple); 6796 case llvm::Triple::FreeBSD: 6797 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6798 case llvm::Triple::KFreeBSD: 6799 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6800 case llvm::Triple::Minix: 6801 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6802 case llvm::Triple::Solaris: 6803 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6804 case llvm::Triple::Win32: { 6805 switch (Triple.getEnvironment()) { 6806 default: 6807 return new X86_32TargetInfo(Triple); 6808 case llvm::Triple::Cygnus: 6809 return new CygwinX86_32TargetInfo(Triple); 6810 case llvm::Triple::GNU: 6811 return new MinGWX86_32TargetInfo(Triple); 6812 case llvm::Triple::Itanium: 6813 case llvm::Triple::MSVC: 6814 return new MicrosoftX86_32TargetInfo(Triple); 6815 } 6816 } 6817 case llvm::Triple::Haiku: 6818 return new HaikuX86_32TargetInfo(Triple); 6819 case llvm::Triple::RTEMS: 6820 return new RTEMSX86_32TargetInfo(Triple); 6821 case llvm::Triple::NaCl: 6822 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6823 default: 6824 return new X86_32TargetInfo(Triple); 6825 } 6826 6827 case llvm::Triple::x86_64: 6828 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6829 return new DarwinX86_64TargetInfo(Triple); 6830 6831 switch (os) { 6832 case llvm::Triple::CloudABI: 6833 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 6834 case llvm::Triple::Linux: 6835 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6836 case llvm::Triple::DragonFly: 6837 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6838 case llvm::Triple::NetBSD: 6839 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6840 case llvm::Triple::OpenBSD: 6841 return new OpenBSDX86_64TargetInfo(Triple); 6842 case llvm::Triple::Bitrig: 6843 return new BitrigX86_64TargetInfo(Triple); 6844 case llvm::Triple::FreeBSD: 6845 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6846 case llvm::Triple::KFreeBSD: 6847 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6848 case llvm::Triple::Solaris: 6849 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6850 case llvm::Triple::Win32: { 6851 switch (Triple.getEnvironment()) { 6852 default: 6853 return new X86_64TargetInfo(Triple); 6854 case llvm::Triple::GNU: 6855 return new MinGWX86_64TargetInfo(Triple); 6856 case llvm::Triple::MSVC: 6857 return new MicrosoftX86_64TargetInfo(Triple); 6858 } 6859 } 6860 case llvm::Triple::NaCl: 6861 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6862 case llvm::Triple::PS4: 6863 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 6864 default: 6865 return new X86_64TargetInfo(Triple); 6866 } 6867 6868 case llvm::Triple::spir: { 6869 if (Triple.getOS() != llvm::Triple::UnknownOS || 6870 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6871 return nullptr; 6872 return new SPIR32TargetInfo(Triple); 6873 } 6874 case llvm::Triple::spir64: { 6875 if (Triple.getOS() != llvm::Triple::UnknownOS || 6876 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6877 return nullptr; 6878 return new SPIR64TargetInfo(Triple); 6879 } 6880 } 6881 } 6882 6883 /// CreateTargetInfo - Return the target info object for the specified target 6884 /// triple. 6885 TargetInfo * 6886 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6887 const std::shared_ptr<TargetOptions> &Opts) { 6888 llvm::Triple Triple(Opts->Triple); 6889 6890 // Construct the target 6891 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6892 if (!Target) { 6893 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6894 return nullptr; 6895 } 6896 Target->TargetOpts = Opts; 6897 6898 // Set the target CPU if specified. 6899 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6900 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6901 return nullptr; 6902 } 6903 6904 // Set the target ABI if specified. 6905 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6906 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6907 return nullptr; 6908 } 6909 6910 // Set the fp math unit. 6911 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6912 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6913 return nullptr; 6914 } 6915 6916 // Compute the default target features, we need the target to handle this 6917 // because features may have dependencies on one another. 6918 llvm::StringMap<bool> Features; 6919 Target->getDefaultFeatures(Features); 6920 6921 // Apply the user specified deltas. 6922 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6923 I < N; ++I) { 6924 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6925 // Apply the feature via the target. 6926 bool Enabled = Name[0] == '+'; 6927 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6928 } 6929 6930 // Add the features to the compile options. 6931 // 6932 // FIXME: If we are completely confident that we have the right set, we only 6933 // need to pass the minuses. 6934 Opts->Features.clear(); 6935 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6936 ie = Features.end(); it != ie; ++it) 6937 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6938 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6939 return nullptr; 6940 6941 return Target.release(); 6942 } 6943