1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 this->UserLabelPrefix = ""; 584 585 switch (Triple.getArch()) { 586 default: 587 case llvm::Triple::x86_64: 588 this->MCountName = ".mcount"; 589 break; 590 } 591 } 592 }; 593 594 // Solaris target 595 template<typename Target> 596 class SolarisTargetInfo : public OSTargetInfo<Target> { 597 protected: 598 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 599 MacroBuilder &Builder) const override { 600 DefineStd(Builder, "sun", Opts); 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__svr4__"); 604 Builder.defineMacro("__SVR4"); 605 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 606 // newer, but to 500 for everything else. feature_test.h has a check to 607 // ensure that you are not using C99 with an old version of X/Open or C89 608 // with a new version. 609 if (Opts.C99) 610 Builder.defineMacro("_XOPEN_SOURCE", "600"); 611 else 612 Builder.defineMacro("_XOPEN_SOURCE", "500"); 613 if (Opts.CPlusPlus) 614 Builder.defineMacro("__C99FEATURES__"); 615 Builder.defineMacro("_LARGEFILE_SOURCE"); 616 Builder.defineMacro("_LARGEFILE64_SOURCE"); 617 Builder.defineMacro("__EXTENSIONS__"); 618 Builder.defineMacro("_REENTRANT"); 619 } 620 public: 621 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 622 this->UserLabelPrefix = ""; 623 this->WCharType = this->SignedInt; 624 // FIXME: WIntType should be SignedLong 625 } 626 }; 627 628 // Windows target 629 template<typename Target> 630 class WindowsTargetInfo : public OSTargetInfo<Target> { 631 protected: 632 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 633 MacroBuilder &Builder) const override { 634 Builder.defineMacro("_WIN32"); 635 } 636 void getVisualStudioDefines(const LangOptions &Opts, 637 MacroBuilder &Builder) const { 638 if (Opts.CPlusPlus) { 639 if (Opts.RTTIData) 640 Builder.defineMacro("_CPPRTTI"); 641 642 if (Opts.CXXExceptions) 643 Builder.defineMacro("_CPPUNWIND"); 644 } 645 646 if (!Opts.CharIsSigned) 647 Builder.defineMacro("_CHAR_UNSIGNED"); 648 649 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 650 // but it works for now. 651 if (Opts.POSIXThreads) 652 Builder.defineMacro("_MT"); 653 654 if (Opts.MSCompatibilityVersion) { 655 Builder.defineMacro("_MSC_VER", 656 Twine(Opts.MSCompatibilityVersion / 100000)); 657 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 658 // FIXME We cannot encode the revision information into 32-bits 659 Builder.defineMacro("_MSC_BUILD", Twine(1)); 660 661 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 662 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 663 } 664 665 if (Opts.MicrosoftExt) { 666 Builder.defineMacro("_MSC_EXTENSIONS"); 667 668 if (Opts.CPlusPlus11) { 669 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 670 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 671 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 672 } 673 } 674 675 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 676 } 677 678 public: 679 WindowsTargetInfo(const llvm::Triple &Triple) 680 : OSTargetInfo<Target>(Triple) {} 681 }; 682 683 template <typename Target> 684 class NaClTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 if (Opts.POSIXThreads) 689 Builder.defineMacro("_REENTRANT"); 690 if (Opts.CPlusPlus) 691 Builder.defineMacro("_GNU_SOURCE"); 692 693 DefineStd(Builder, "unix", Opts); 694 Builder.defineMacro("__ELF__"); 695 Builder.defineMacro("__native_client__"); 696 } 697 698 public: 699 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 700 this->UserLabelPrefix = ""; 701 this->LongAlign = 32; 702 this->LongWidth = 32; 703 this->PointerAlign = 32; 704 this->PointerWidth = 32; 705 this->IntMaxType = TargetInfo::SignedLongLong; 706 this->Int64Type = TargetInfo::SignedLongLong; 707 this->DoubleAlign = 64; 708 this->LongDoubleWidth = 64; 709 this->LongDoubleAlign = 64; 710 this->LongLongWidth = 64; 711 this->LongLongAlign = 64; 712 this->SizeType = TargetInfo::UnsignedInt; 713 this->PtrDiffType = TargetInfo::SignedInt; 714 this->IntPtrType = TargetInfo::SignedInt; 715 // RegParmMax is inherited from the underlying architecture 716 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 717 if (Triple.getArch() == llvm::Triple::arm) { 718 // Handled in ARM's setABI(). 719 } else if (Triple.getArch() == llvm::Triple::x86) { 720 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 721 } else if (Triple.getArch() == llvm::Triple::x86_64) { 722 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 723 } else if (Triple.getArch() == llvm::Triple::mipsel) { 724 // Handled on mips' setDescriptionString. 725 } else { 726 assert(Triple.getArch() == llvm::Triple::le32); 727 this->DescriptionString = "e-p:32:32-i64:64"; 728 } 729 } 730 }; 731 732 //===----------------------------------------------------------------------===// 733 // Specific target implementations. 734 //===----------------------------------------------------------------------===// 735 736 // PPC abstract base class 737 class PPCTargetInfo : public TargetInfo { 738 static const Builtin::Info BuiltinInfo[]; 739 static const char * const GCCRegNames[]; 740 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 741 std::string CPU; 742 743 // Target cpu features. 744 bool HasVSX; 745 bool HasP8Vector; 746 bool HasP8Crypto; 747 bool HasDirectMove; 748 bool HasQPX; 749 bool HasHTM; 750 bool HasBPERMD; 751 bool HasExtDiv; 752 753 protected: 754 std::string ABI; 755 756 public: 757 PPCTargetInfo(const llvm::Triple &Triple) 758 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 759 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 760 HasBPERMD(false), HasExtDiv(false) { 761 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 762 SimdDefaultAlign = 128; 763 LongDoubleWidth = LongDoubleAlign = 128; 764 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 765 } 766 767 /// \brief Flags for architecture specific defines. 768 typedef enum { 769 ArchDefineNone = 0, 770 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 771 ArchDefinePpcgr = 1 << 1, 772 ArchDefinePpcsq = 1 << 2, 773 ArchDefine440 = 1 << 3, 774 ArchDefine603 = 1 << 4, 775 ArchDefine604 = 1 << 5, 776 ArchDefinePwr4 = 1 << 6, 777 ArchDefinePwr5 = 1 << 7, 778 ArchDefinePwr5x = 1 << 8, 779 ArchDefinePwr6 = 1 << 9, 780 ArchDefinePwr6x = 1 << 10, 781 ArchDefinePwr7 = 1 << 11, 782 ArchDefinePwr8 = 1 << 12, 783 ArchDefineA2 = 1 << 13, 784 ArchDefineA2q = 1 << 14 785 } ArchDefineTypes; 786 787 // Note: GCC recognizes the following additional cpus: 788 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 789 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 790 // titan, rs64. 791 bool setCPU(const std::string &Name) override { 792 bool CPUKnown = llvm::StringSwitch<bool>(Name) 793 .Case("generic", true) 794 .Case("440", true) 795 .Case("450", true) 796 .Case("601", true) 797 .Case("602", true) 798 .Case("603", true) 799 .Case("603e", true) 800 .Case("603ev", true) 801 .Case("604", true) 802 .Case("604e", true) 803 .Case("620", true) 804 .Case("630", true) 805 .Case("g3", true) 806 .Case("7400", true) 807 .Case("g4", true) 808 .Case("7450", true) 809 .Case("g4+", true) 810 .Case("750", true) 811 .Case("970", true) 812 .Case("g5", true) 813 .Case("a2", true) 814 .Case("a2q", true) 815 .Case("e500mc", true) 816 .Case("e5500", true) 817 .Case("power3", true) 818 .Case("pwr3", true) 819 .Case("power4", true) 820 .Case("pwr4", true) 821 .Case("power5", true) 822 .Case("pwr5", true) 823 .Case("power5x", true) 824 .Case("pwr5x", true) 825 .Case("power6", true) 826 .Case("pwr6", true) 827 .Case("power6x", true) 828 .Case("pwr6x", true) 829 .Case("power7", true) 830 .Case("pwr7", true) 831 .Case("power8", true) 832 .Case("pwr8", true) 833 .Case("powerpc", true) 834 .Case("ppc", true) 835 .Case("powerpc64", true) 836 .Case("ppc64", true) 837 .Case("powerpc64le", true) 838 .Case("ppc64le", true) 839 .Default(false); 840 841 if (CPUKnown) 842 CPU = Name; 843 844 return CPUKnown; 845 } 846 847 848 StringRef getABI() const override { return ABI; } 849 850 void getTargetBuiltins(const Builtin::Info *&Records, 851 unsigned &NumRecords) const override { 852 Records = BuiltinInfo; 853 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 854 } 855 856 bool isCLZForZeroUndef() const override { return false; } 857 858 void getTargetDefines(const LangOptions &Opts, 859 MacroBuilder &Builder) const override; 860 861 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 862 863 bool handleTargetFeatures(std::vector<std::string> &Features, 864 DiagnosticsEngine &Diags) override; 865 bool hasFeature(StringRef Feature) const override; 866 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 867 bool Enabled) const override; 868 869 void getGCCRegNames(const char * const *&Names, 870 unsigned &NumNames) const override; 871 void getGCCRegAliases(const GCCRegAlias *&Aliases, 872 unsigned &NumAliases) const override; 873 bool validateAsmConstraint(const char *&Name, 874 TargetInfo::ConstraintInfo &Info) const override { 875 switch (*Name) { 876 default: return false; 877 case 'O': // Zero 878 break; 879 case 'b': // Base register 880 case 'f': // Floating point register 881 Info.setAllowsRegister(); 882 break; 883 // FIXME: The following are added to allow parsing. 884 // I just took a guess at what the actions should be. 885 // Also, is more specific checking needed? I.e. specific registers? 886 case 'd': // Floating point register (containing 64-bit value) 887 case 'v': // Altivec vector register 888 Info.setAllowsRegister(); 889 break; 890 case 'w': 891 switch (Name[1]) { 892 case 'd':// VSX vector register to hold vector double data 893 case 'f':// VSX vector register to hold vector float data 894 case 's':// VSX vector register to hold scalar float data 895 case 'a':// Any VSX register 896 case 'c':// An individual CR bit 897 break; 898 default: 899 return false; 900 } 901 Info.setAllowsRegister(); 902 Name++; // Skip over 'w'. 903 break; 904 case 'h': // `MQ', `CTR', or `LINK' register 905 case 'q': // `MQ' register 906 case 'c': // `CTR' register 907 case 'l': // `LINK' register 908 case 'x': // `CR' register (condition register) number 0 909 case 'y': // `CR' register (condition register) 910 case 'z': // `XER[CA]' carry bit (part of the XER register) 911 Info.setAllowsRegister(); 912 break; 913 case 'I': // Signed 16-bit constant 914 case 'J': // Unsigned 16-bit constant shifted left 16 bits 915 // (use `L' instead for SImode constants) 916 case 'K': // Unsigned 16-bit constant 917 case 'L': // Signed 16-bit constant shifted left 16 bits 918 case 'M': // Constant larger than 31 919 case 'N': // Exact power of 2 920 case 'P': // Constant whose negation is a signed 16-bit constant 921 case 'G': // Floating point constant that can be loaded into a 922 // register with one instruction per word 923 case 'H': // Integer/Floating point constant that can be loaded 924 // into a register using three instructions 925 break; 926 case 'm': // Memory operand. Note that on PowerPC targets, m can 927 // include addresses that update the base register. It 928 // is therefore only safe to use `m' in an asm statement 929 // if that asm statement accesses the operand exactly once. 930 // The asm statement must also use `%U<opno>' as a 931 // placeholder for the "update" flag in the corresponding 932 // load or store instruction. For example: 933 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 934 // is correct but: 935 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 936 // is not. Use es rather than m if you don't want the base 937 // register to be updated. 938 case 'e': 939 if (Name[1] != 's') 940 return false; 941 // es: A "stable" memory operand; that is, one which does not 942 // include any automodification of the base register. Unlike 943 // `m', this constraint can be used in asm statements that 944 // might access the operand several times, or that might not 945 // access it at all. 946 Info.setAllowsMemory(); 947 Name++; // Skip over 'e'. 948 break; 949 case 'Q': // Memory operand that is an offset from a register (it is 950 // usually better to use `m' or `es' in asm statements) 951 case 'Z': // Memory operand that is an indexed or indirect from a 952 // register (it is usually better to use `m' or `es' in 953 // asm statements) 954 Info.setAllowsMemory(); 955 Info.setAllowsRegister(); 956 break; 957 case 'R': // AIX TOC entry 958 case 'a': // Address operand that is an indexed or indirect from a 959 // register (`p' is preferable for asm statements) 960 case 'S': // Constant suitable as a 64-bit mask operand 961 case 'T': // Constant suitable as a 32-bit mask operand 962 case 'U': // System V Release 4 small data area reference 963 case 't': // AND masks that can be performed by two rldic{l, r} 964 // instructions 965 case 'W': // Vector constant that does not require memory 966 case 'j': // Vector constant that is all zeros. 967 break; 968 // End FIXME. 969 } 970 return true; 971 } 972 std::string convertConstraint(const char *&Constraint) const override { 973 std::string R; 974 switch (*Constraint) { 975 case 'e': 976 case 'w': 977 // Two-character constraint; add "^" hint for later parsing. 978 R = std::string("^") + std::string(Constraint, 2); 979 Constraint++; 980 break; 981 default: 982 return TargetInfo::convertConstraint(Constraint); 983 } 984 return R; 985 } 986 const char *getClobbers() const override { 987 return ""; 988 } 989 int getEHDataRegisterNumber(unsigned RegNo) const override { 990 if (RegNo == 0) return 3; 991 if (RegNo == 1) return 4; 992 return -1; 993 } 994 995 bool hasSjLjLowering() const override { 996 return true; 997 } 998 999 bool useFloat128ManglingForLongDouble() const override { 1000 return LongDoubleWidth == 128 && 1001 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1002 getTriple().isOSBinFormatELF(); 1003 } 1004 }; 1005 1006 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1007 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1008 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1009 ALL_LANGUAGES }, 1010 #include "clang/Basic/BuiltinsPPC.def" 1011 }; 1012 1013 /// handleTargetFeatures - Perform initialization based on the user 1014 /// configured set of features. 1015 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1016 DiagnosticsEngine &Diags) { 1017 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1018 // Ignore disabled features. 1019 if (Features[i][0] == '-') 1020 continue; 1021 1022 StringRef Feature = StringRef(Features[i]).substr(1); 1023 1024 if (Feature == "vsx") { 1025 HasVSX = true; 1026 continue; 1027 } 1028 1029 if (Feature == "bpermd") { 1030 HasBPERMD = true; 1031 continue; 1032 } 1033 1034 if (Feature == "extdiv") { 1035 HasExtDiv = true; 1036 continue; 1037 } 1038 1039 if (Feature == "power8-vector") { 1040 HasP8Vector = true; 1041 continue; 1042 } 1043 1044 if (Feature == "crypto") { 1045 HasP8Crypto = true; 1046 continue; 1047 } 1048 1049 if (Feature == "direct-move") { 1050 HasDirectMove = true; 1051 continue; 1052 } 1053 1054 if (Feature == "qpx") { 1055 HasQPX = true; 1056 continue; 1057 } 1058 1059 if (Feature == "htm") { 1060 HasHTM = true; 1061 continue; 1062 } 1063 1064 // TODO: Finish this list and add an assert that we've handled them 1065 // all. 1066 } 1067 if (!HasVSX && (HasP8Vector || HasDirectMove)) { 1068 if (HasP8Vector) 1069 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << 1070 "-mno-vsx"; 1071 else if (HasDirectMove) 1072 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << 1073 "-mno-vsx"; 1074 return false; 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 if (getTriple().getArch() == llvm::Triple::ppc64le || 1230 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1234 if (PointerWidth == 64) 1235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1236 } 1237 1238 // FIXME: The following are not yet generated here by Clang, but are 1239 // generated by GCC: 1240 // 1241 // _SOFT_FLOAT_ 1242 // __RECIP_PRECISION__ 1243 // __APPLE_ALTIVEC__ 1244 // __RECIP__ 1245 // __RECIPF__ 1246 // __RSQRTE__ 1247 // __RSQRTEF__ 1248 // _SOFT_DOUBLE_ 1249 // __NO_LWSYNC__ 1250 // __HAVE_BSWAP__ 1251 // __LONGDOUBLE128 1252 // __CMODEL_MEDIUM__ 1253 // __CMODEL_LARGE__ 1254 // _CALL_SYSV 1255 // _CALL_DARWIN 1256 // __NO_FPRS__ 1257 } 1258 1259 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1260 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1261 .Case("7400", true) 1262 .Case("g4", true) 1263 .Case("7450", true) 1264 .Case("g4+", true) 1265 .Case("970", true) 1266 .Case("g5", true) 1267 .Case("pwr6", true) 1268 .Case("pwr7", true) 1269 .Case("pwr8", true) 1270 .Case("ppc64", true) 1271 .Case("ppc64le", true) 1272 .Default(false); 1273 1274 Features["qpx"] = (CPU == "a2q"); 1275 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1276 .Case("ppc64le", true) 1277 .Case("pwr8", true) 1278 .Default(false); 1279 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1280 .Case("ppc64le", true) 1281 .Case("pwr8", true) 1282 .Default(false); 1283 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1284 .Case("ppc64le", true) 1285 .Case("pwr8", true) 1286 .Case("pwr7", true) 1287 .Default(false); 1288 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1289 .Case("ppc64le", true) 1290 .Case("pwr8", true) 1291 .Case("pwr7", true) 1292 .Default(false); 1293 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1294 .Case("ppc64le", true) 1295 .Case("pwr8", true) 1296 .Default(false); 1297 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1298 .Case("ppc64le", true) 1299 .Case("pwr8", true) 1300 .Case("pwr7", true) 1301 .Default(false); 1302 } 1303 1304 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1305 return llvm::StringSwitch<bool>(Feature) 1306 .Case("powerpc", true) 1307 .Case("vsx", HasVSX) 1308 .Case("power8-vector", HasP8Vector) 1309 .Case("crypto", HasP8Crypto) 1310 .Case("direct-move", HasDirectMove) 1311 .Case("qpx", HasQPX) 1312 .Case("htm", HasHTM) 1313 .Case("bpermd", HasBPERMD) 1314 .Case("extdiv", HasExtDiv) 1315 .Default(false); 1316 } 1317 1318 /* There is no clear way for the target to know which of the features in the 1319 final feature vector came from defaults and which are actually specified by 1320 the user. To that end, we use the fact that this function is not called on 1321 default features - only user specified ones. By the first time this 1322 function is called, the default features are populated. 1323 We then keep track of the features that the user specified so that we 1324 can ensure we do not override a user's request (only defaults). 1325 For example: 1326 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it) 1327 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed) 1328 1329 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures 1330 */ 1331 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1332 StringRef Name, bool Enabled) const { 1333 static llvm::StringMap<bool> ExplicitFeatures; 1334 ExplicitFeatures[Name] = Enabled; 1335 1336 // At this point, -mno-vsx turns off the dependent features but we respect 1337 // the user's requests. 1338 if (!Enabled && Name == "vsx") { 1339 Features["direct-move"] = ExplicitFeatures["direct-move"]; 1340 Features["power8-vector"] = ExplicitFeatures["power8-vector"]; 1341 } 1342 if ((Enabled && Name == "power8-vector") || 1343 (Enabled && Name == "direct-move")) { 1344 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) { 1345 Features["vsx"] = true; 1346 } 1347 } 1348 Features[Name] = Enabled; 1349 } 1350 1351 const char * const PPCTargetInfo::GCCRegNames[] = { 1352 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1353 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1354 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1355 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1356 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1357 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1358 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1359 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1360 "mq", "lr", "ctr", "ap", 1361 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1362 "xer", 1363 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1364 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1365 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1366 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1367 "vrsave", "vscr", 1368 "spe_acc", "spefscr", 1369 "sfp" 1370 }; 1371 1372 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1373 unsigned &NumNames) const { 1374 Names = GCCRegNames; 1375 NumNames = llvm::array_lengthof(GCCRegNames); 1376 } 1377 1378 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1379 // While some of these aliases do map to different registers 1380 // they still share the same register name. 1381 { { "0" }, "r0" }, 1382 { { "1"}, "r1" }, 1383 { { "2" }, "r2" }, 1384 { { "3" }, "r3" }, 1385 { { "4" }, "r4" }, 1386 { { "5" }, "r5" }, 1387 { { "6" }, "r6" }, 1388 { { "7" }, "r7" }, 1389 { { "8" }, "r8" }, 1390 { { "9" }, "r9" }, 1391 { { "10" }, "r10" }, 1392 { { "11" }, "r11" }, 1393 { { "12" }, "r12" }, 1394 { { "13" }, "r13" }, 1395 { { "14" }, "r14" }, 1396 { { "15" }, "r15" }, 1397 { { "16" }, "r16" }, 1398 { { "17" }, "r17" }, 1399 { { "18" }, "r18" }, 1400 { { "19" }, "r19" }, 1401 { { "20" }, "r20" }, 1402 { { "21" }, "r21" }, 1403 { { "22" }, "r22" }, 1404 { { "23" }, "r23" }, 1405 { { "24" }, "r24" }, 1406 { { "25" }, "r25" }, 1407 { { "26" }, "r26" }, 1408 { { "27" }, "r27" }, 1409 { { "28" }, "r28" }, 1410 { { "29" }, "r29" }, 1411 { { "30" }, "r30" }, 1412 { { "31" }, "r31" }, 1413 { { "fr0" }, "f0" }, 1414 { { "fr1" }, "f1" }, 1415 { { "fr2" }, "f2" }, 1416 { { "fr3" }, "f3" }, 1417 { { "fr4" }, "f4" }, 1418 { { "fr5" }, "f5" }, 1419 { { "fr6" }, "f6" }, 1420 { { "fr7" }, "f7" }, 1421 { { "fr8" }, "f8" }, 1422 { { "fr9" }, "f9" }, 1423 { { "fr10" }, "f10" }, 1424 { { "fr11" }, "f11" }, 1425 { { "fr12" }, "f12" }, 1426 { { "fr13" }, "f13" }, 1427 { { "fr14" }, "f14" }, 1428 { { "fr15" }, "f15" }, 1429 { { "fr16" }, "f16" }, 1430 { { "fr17" }, "f17" }, 1431 { { "fr18" }, "f18" }, 1432 { { "fr19" }, "f19" }, 1433 { { "fr20" }, "f20" }, 1434 { { "fr21" }, "f21" }, 1435 { { "fr22" }, "f22" }, 1436 { { "fr23" }, "f23" }, 1437 { { "fr24" }, "f24" }, 1438 { { "fr25" }, "f25" }, 1439 { { "fr26" }, "f26" }, 1440 { { "fr27" }, "f27" }, 1441 { { "fr28" }, "f28" }, 1442 { { "fr29" }, "f29" }, 1443 { { "fr30" }, "f30" }, 1444 { { "fr31" }, "f31" }, 1445 { { "cc" }, "cr0" }, 1446 }; 1447 1448 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1449 unsigned &NumAliases) const { 1450 Aliases = GCCRegAliases; 1451 NumAliases = llvm::array_lengthof(GCCRegAliases); 1452 } 1453 1454 class PPC32TargetInfo : public PPCTargetInfo { 1455 public: 1456 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1457 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1458 1459 switch (getTriple().getOS()) { 1460 case llvm::Triple::Linux: 1461 case llvm::Triple::FreeBSD: 1462 case llvm::Triple::NetBSD: 1463 SizeType = UnsignedInt; 1464 PtrDiffType = SignedInt; 1465 IntPtrType = SignedInt; 1466 break; 1467 default: 1468 break; 1469 } 1470 1471 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1472 LongDoubleWidth = LongDoubleAlign = 64; 1473 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1474 } 1475 1476 // PPC32 supports atomics up to 4 bytes. 1477 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1478 } 1479 1480 BuiltinVaListKind getBuiltinVaListKind() const override { 1481 // This is the ELF definition, and is overridden by the Darwin sub-target 1482 return TargetInfo::PowerABIBuiltinVaList; 1483 } 1484 }; 1485 1486 // Note: ABI differences may eventually require us to have a separate 1487 // TargetInfo for little endian. 1488 class PPC64TargetInfo : public PPCTargetInfo { 1489 public: 1490 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1491 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1492 IntMaxType = SignedLong; 1493 Int64Type = SignedLong; 1494 1495 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1496 DescriptionString = "e-m:e-i64:64-n32:64"; 1497 ABI = "elfv2"; 1498 } else { 1499 DescriptionString = "E-m:e-i64:64-n32:64"; 1500 ABI = "elfv1"; 1501 } 1502 1503 switch (getTriple().getOS()) { 1504 case llvm::Triple::FreeBSD: 1505 LongDoubleWidth = LongDoubleAlign = 64; 1506 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1507 break; 1508 case llvm::Triple::NetBSD: 1509 IntMaxType = SignedLongLong; 1510 Int64Type = SignedLongLong; 1511 break; 1512 default: 1513 break; 1514 } 1515 1516 // PPC64 supports atomics up to 8 bytes. 1517 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1518 } 1519 BuiltinVaListKind getBuiltinVaListKind() const override { 1520 return TargetInfo::CharPtrBuiltinVaList; 1521 } 1522 // PPC64 Linux-specific ABI options. 1523 bool setABI(const std::string &Name) override { 1524 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1525 ABI = Name; 1526 return true; 1527 } 1528 return false; 1529 } 1530 }; 1531 1532 class DarwinPPC32TargetInfo : 1533 public DarwinTargetInfo<PPC32TargetInfo> { 1534 public: 1535 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1536 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1537 HasAlignMac68kSupport = true; 1538 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1539 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1540 LongLongAlign = 32; 1541 SuitableAlign = 128; 1542 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1543 } 1544 BuiltinVaListKind getBuiltinVaListKind() const override { 1545 return TargetInfo::CharPtrBuiltinVaList; 1546 } 1547 }; 1548 1549 class DarwinPPC64TargetInfo : 1550 public DarwinTargetInfo<PPC64TargetInfo> { 1551 public: 1552 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1553 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1554 HasAlignMac68kSupport = true; 1555 SuitableAlign = 128; 1556 DescriptionString = "E-m:o-i64:64-n32:64"; 1557 } 1558 }; 1559 1560 static const unsigned NVPTXAddrSpaceMap[] = { 1561 1, // opencl_global 1562 3, // opencl_local 1563 4, // opencl_constant 1564 // FIXME: generic has to be added to the target 1565 0, // opencl_generic 1566 1, // cuda_device 1567 4, // cuda_constant 1568 3, // cuda_shared 1569 }; 1570 class NVPTXTargetInfo : public TargetInfo { 1571 static const char * const GCCRegNames[]; 1572 static const Builtin::Info BuiltinInfo[]; 1573 1574 // The GPU profiles supported by the NVPTX backend 1575 enum GPUKind { 1576 GK_NONE, 1577 GK_SM20, 1578 GK_SM21, 1579 GK_SM30, 1580 GK_SM35, 1581 GK_SM37, 1582 } GPU; 1583 1584 public: 1585 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1586 BigEndian = false; 1587 TLSSupported = false; 1588 LongWidth = LongAlign = 64; 1589 AddrSpaceMap = &NVPTXAddrSpaceMap; 1590 UseAddrSpaceMapMangling = true; 1591 // Define available target features 1592 // These must be defined in sorted order! 1593 NoAsmVariants = true; 1594 // Set the default GPU to sm20 1595 GPU = GK_SM20; 1596 } 1597 void getTargetDefines(const LangOptions &Opts, 1598 MacroBuilder &Builder) const override { 1599 Builder.defineMacro("__PTX__"); 1600 Builder.defineMacro("__NVPTX__"); 1601 if (Opts.CUDAIsDevice) { 1602 // Set __CUDA_ARCH__ for the GPU specified. 1603 std::string CUDAArchCode; 1604 switch (GPU) { 1605 case GK_SM20: 1606 CUDAArchCode = "200"; 1607 break; 1608 case GK_SM21: 1609 CUDAArchCode = "210"; 1610 break; 1611 case GK_SM30: 1612 CUDAArchCode = "300"; 1613 break; 1614 case GK_SM35: 1615 CUDAArchCode = "350"; 1616 break; 1617 case GK_SM37: 1618 CUDAArchCode = "370"; 1619 break; 1620 default: 1621 llvm_unreachable("Unhandled target CPU"); 1622 } 1623 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1624 } 1625 } 1626 void getTargetBuiltins(const Builtin::Info *&Records, 1627 unsigned &NumRecords) const override { 1628 Records = BuiltinInfo; 1629 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1630 } 1631 bool hasFeature(StringRef Feature) const override { 1632 return Feature == "ptx" || Feature == "nvptx"; 1633 } 1634 1635 void getGCCRegNames(const char * const *&Names, 1636 unsigned &NumNames) const override; 1637 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1638 unsigned &NumAliases) const override { 1639 // No aliases. 1640 Aliases = nullptr; 1641 NumAliases = 0; 1642 } 1643 bool 1644 validateAsmConstraint(const char *&Name, 1645 TargetInfo::ConstraintInfo &Info) const override { 1646 switch (*Name) { 1647 default: return false; 1648 case 'c': 1649 case 'h': 1650 case 'r': 1651 case 'l': 1652 case 'f': 1653 case 'd': 1654 Info.setAllowsRegister(); 1655 return true; 1656 } 1657 } 1658 const char *getClobbers() const override { 1659 // FIXME: Is this really right? 1660 return ""; 1661 } 1662 BuiltinVaListKind getBuiltinVaListKind() const override { 1663 // FIXME: implement 1664 return TargetInfo::CharPtrBuiltinVaList; 1665 } 1666 bool setCPU(const std::string &Name) override { 1667 GPU = llvm::StringSwitch<GPUKind>(Name) 1668 .Case("sm_20", GK_SM20) 1669 .Case("sm_21", GK_SM21) 1670 .Case("sm_30", GK_SM30) 1671 .Case("sm_35", GK_SM35) 1672 .Case("sm_37", GK_SM37) 1673 .Default(GK_NONE); 1674 1675 return GPU != GK_NONE; 1676 } 1677 }; 1678 1679 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1680 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1681 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1682 ALL_LANGUAGES }, 1683 #include "clang/Basic/BuiltinsNVPTX.def" 1684 }; 1685 1686 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1687 "r0" 1688 }; 1689 1690 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1691 unsigned &NumNames) const { 1692 Names = GCCRegNames; 1693 NumNames = llvm::array_lengthof(GCCRegNames); 1694 } 1695 1696 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1697 public: 1698 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1699 PointerWidth = PointerAlign = 32; 1700 SizeType = TargetInfo::UnsignedInt; 1701 PtrDiffType = TargetInfo::SignedInt; 1702 IntPtrType = TargetInfo::SignedInt; 1703 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1704 } 1705 }; 1706 1707 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1708 public: 1709 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1710 PointerWidth = PointerAlign = 64; 1711 SizeType = TargetInfo::UnsignedLong; 1712 PtrDiffType = TargetInfo::SignedLong; 1713 IntPtrType = TargetInfo::SignedLong; 1714 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1715 } 1716 }; 1717 1718 static const unsigned AMDGPUAddrSpaceMap[] = { 1719 1, // opencl_global 1720 3, // opencl_local 1721 2, // opencl_constant 1722 4, // opencl_generic 1723 1, // cuda_device 1724 2, // cuda_constant 1725 3 // cuda_shared 1726 }; 1727 1728 // If you edit the description strings, make sure you update 1729 // getPointerWidthV(). 1730 1731 static const char *DescriptionStringR600 = 1732 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1733 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1734 1735 static const char *DescriptionStringR600DoubleOps = 1736 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1737 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1738 1739 static const char *DescriptionStringSI = 1740 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1741 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1742 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1743 1744 class AMDGPUTargetInfo : public TargetInfo { 1745 static const Builtin::Info BuiltinInfo[]; 1746 static const char * const GCCRegNames[]; 1747 1748 /// \brief The GPU profiles supported by the AMDGPU target. 1749 enum GPUKind { 1750 GK_NONE, 1751 GK_R600, 1752 GK_R600_DOUBLE_OPS, 1753 GK_R700, 1754 GK_R700_DOUBLE_OPS, 1755 GK_EVERGREEN, 1756 GK_EVERGREEN_DOUBLE_OPS, 1757 GK_NORTHERN_ISLANDS, 1758 GK_CAYMAN, 1759 GK_SOUTHERN_ISLANDS, 1760 GK_SEA_ISLANDS, 1761 GK_VOLCANIC_ISLANDS 1762 } GPU; 1763 1764 bool hasFP64:1; 1765 bool hasFMAF:1; 1766 bool hasLDEXPF:1; 1767 1768 public: 1769 AMDGPUTargetInfo(const llvm::Triple &Triple) 1770 : TargetInfo(Triple) { 1771 1772 if (Triple.getArch() == llvm::Triple::amdgcn) { 1773 DescriptionString = DescriptionStringSI; 1774 GPU = GK_SOUTHERN_ISLANDS; 1775 hasFP64 = true; 1776 hasFMAF = true; 1777 hasLDEXPF = true; 1778 } else { 1779 DescriptionString = DescriptionStringR600; 1780 GPU = GK_R600; 1781 hasFP64 = false; 1782 hasFMAF = false; 1783 hasLDEXPF = false; 1784 } 1785 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1786 UseAddrSpaceMapMangling = true; 1787 } 1788 1789 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1790 if (GPU <= GK_CAYMAN) 1791 return 32; 1792 1793 switch(AddrSpace) { 1794 default: 1795 return 64; 1796 case 0: 1797 case 3: 1798 case 5: 1799 return 32; 1800 } 1801 } 1802 1803 const char * getClobbers() const override { 1804 return ""; 1805 } 1806 1807 void getGCCRegNames(const char * const *&Names, 1808 unsigned &NumNames) const override; 1809 1810 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1811 unsigned &NumAliases) const override { 1812 Aliases = nullptr; 1813 NumAliases = 0; 1814 } 1815 1816 bool validateAsmConstraint(const char *&Name, 1817 TargetInfo::ConstraintInfo &info) const override { 1818 return true; 1819 } 1820 1821 void getTargetBuiltins(const Builtin::Info *&Records, 1822 unsigned &NumRecords) const override { 1823 Records = BuiltinInfo; 1824 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1825 } 1826 1827 void getTargetDefines(const LangOptions &Opts, 1828 MacroBuilder &Builder) const override { 1829 Builder.defineMacro("__R600__"); 1830 if (hasFMAF) 1831 Builder.defineMacro("__HAS_FMAF__"); 1832 if (hasLDEXPF) 1833 Builder.defineMacro("__HAS_LDEXPF__"); 1834 if (hasFP64 && Opts.OpenCL) { 1835 Builder.defineMacro("cl_khr_fp64"); 1836 } 1837 } 1838 1839 BuiltinVaListKind getBuiltinVaListKind() const override { 1840 return TargetInfo::CharPtrBuiltinVaList; 1841 } 1842 1843 bool setCPU(const std::string &Name) override { 1844 GPU = llvm::StringSwitch<GPUKind>(Name) 1845 .Case("r600" , GK_R600) 1846 .Case("rv610", GK_R600) 1847 .Case("rv620", GK_R600) 1848 .Case("rv630", GK_R600) 1849 .Case("rv635", GK_R600) 1850 .Case("rs780", GK_R600) 1851 .Case("rs880", GK_R600) 1852 .Case("rv670", GK_R600_DOUBLE_OPS) 1853 .Case("rv710", GK_R700) 1854 .Case("rv730", GK_R700) 1855 .Case("rv740", GK_R700_DOUBLE_OPS) 1856 .Case("rv770", GK_R700_DOUBLE_OPS) 1857 .Case("palm", GK_EVERGREEN) 1858 .Case("cedar", GK_EVERGREEN) 1859 .Case("sumo", GK_EVERGREEN) 1860 .Case("sumo2", GK_EVERGREEN) 1861 .Case("redwood", GK_EVERGREEN) 1862 .Case("juniper", GK_EVERGREEN) 1863 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1864 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1865 .Case("barts", GK_NORTHERN_ISLANDS) 1866 .Case("turks", GK_NORTHERN_ISLANDS) 1867 .Case("caicos", GK_NORTHERN_ISLANDS) 1868 .Case("cayman", GK_CAYMAN) 1869 .Case("aruba", GK_CAYMAN) 1870 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1871 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1872 .Case("verde", GK_SOUTHERN_ISLANDS) 1873 .Case("oland", GK_SOUTHERN_ISLANDS) 1874 .Case("hainan", GK_SOUTHERN_ISLANDS) 1875 .Case("bonaire", GK_SEA_ISLANDS) 1876 .Case("kabini", GK_SEA_ISLANDS) 1877 .Case("kaveri", GK_SEA_ISLANDS) 1878 .Case("hawaii", GK_SEA_ISLANDS) 1879 .Case("mullins", GK_SEA_ISLANDS) 1880 .Case("tonga", GK_VOLCANIC_ISLANDS) 1881 .Case("iceland", GK_VOLCANIC_ISLANDS) 1882 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1883 .Default(GK_NONE); 1884 1885 if (GPU == GK_NONE) { 1886 return false; 1887 } 1888 1889 // Set the correct data layout 1890 switch (GPU) { 1891 case GK_NONE: 1892 case GK_R600: 1893 case GK_R700: 1894 case GK_EVERGREEN: 1895 case GK_NORTHERN_ISLANDS: 1896 DescriptionString = DescriptionStringR600; 1897 hasFP64 = false; 1898 hasFMAF = false; 1899 hasLDEXPF = false; 1900 break; 1901 case GK_R600_DOUBLE_OPS: 1902 case GK_R700_DOUBLE_OPS: 1903 case GK_EVERGREEN_DOUBLE_OPS: 1904 case GK_CAYMAN: 1905 DescriptionString = DescriptionStringR600DoubleOps; 1906 hasFP64 = true; 1907 hasFMAF = true; 1908 hasLDEXPF = false; 1909 break; 1910 case GK_SOUTHERN_ISLANDS: 1911 case GK_SEA_ISLANDS: 1912 case GK_VOLCANIC_ISLANDS: 1913 DescriptionString = DescriptionStringSI; 1914 hasFP64 = true; 1915 hasFMAF = true; 1916 hasLDEXPF = true; 1917 break; 1918 } 1919 1920 return true; 1921 } 1922 }; 1923 1924 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1925 #define BUILTIN(ID, TYPE, ATTRS) \ 1926 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1927 #include "clang/Basic/BuiltinsAMDGPU.def" 1928 }; 1929 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1930 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1931 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1932 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1933 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1934 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1935 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1936 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1937 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1938 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1939 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1940 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1941 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1942 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1943 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1944 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1945 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1946 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1947 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1948 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1949 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1950 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1951 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1952 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1953 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1954 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1955 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1956 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1957 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1958 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1959 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1960 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1961 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1962 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1963 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1964 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1965 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1966 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1967 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1968 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1969 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1970 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1971 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1972 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1973 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1974 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1975 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1976 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1977 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1978 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1979 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1980 }; 1981 1982 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1983 unsigned &NumNames) const { 1984 Names = GCCRegNames; 1985 NumNames = llvm::array_lengthof(GCCRegNames); 1986 } 1987 1988 // Namespace for x86 abstract base class 1989 const Builtin::Info BuiltinInfo[] = { 1990 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1991 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1992 ALL_LANGUAGES }, 1993 #include "clang/Basic/BuiltinsX86.def" 1994 }; 1995 1996 static const char* const GCCRegNames[] = { 1997 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1998 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1999 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2000 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2001 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2002 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2003 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2004 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2005 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2006 }; 2007 2008 const TargetInfo::AddlRegName AddlRegNames[] = { 2009 { { "al", "ah", "eax", "rax" }, 0 }, 2010 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2011 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2012 { { "dl", "dh", "edx", "rdx" }, 1 }, 2013 { { "esi", "rsi" }, 4 }, 2014 { { "edi", "rdi" }, 5 }, 2015 { { "esp", "rsp" }, 7 }, 2016 { { "ebp", "rbp" }, 6 }, 2017 }; 2018 2019 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2020 // most of the implementation can be shared. 2021 class X86TargetInfo : public TargetInfo { 2022 enum X86SSEEnum { 2023 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2024 } SSELevel; 2025 enum MMX3DNowEnum { 2026 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2027 } MMX3DNowLevel; 2028 enum XOPEnum { 2029 NoXOP, 2030 SSE4A, 2031 FMA4, 2032 XOP 2033 } XOPLevel; 2034 2035 bool HasAES; 2036 bool HasPCLMUL; 2037 bool HasLZCNT; 2038 bool HasRDRND; 2039 bool HasFSGSBASE; 2040 bool HasBMI; 2041 bool HasBMI2; 2042 bool HasPOPCNT; 2043 bool HasRTM; 2044 bool HasPRFCHW; 2045 bool HasRDSEED; 2046 bool HasADX; 2047 bool HasTBM; 2048 bool HasFMA; 2049 bool HasF16C; 2050 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2051 HasAVX512VL; 2052 bool HasSHA; 2053 bool HasCX16; 2054 2055 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2056 /// 2057 /// Each enumeration represents a particular CPU supported by Clang. These 2058 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2059 enum CPUKind { 2060 CK_Generic, 2061 2062 /// \name i386 2063 /// i386-generation processors. 2064 //@{ 2065 CK_i386, 2066 //@} 2067 2068 /// \name i486 2069 /// i486-generation processors. 2070 //@{ 2071 CK_i486, 2072 CK_WinChipC6, 2073 CK_WinChip2, 2074 CK_C3, 2075 //@} 2076 2077 /// \name i586 2078 /// i586-generation processors, P5 microarchitecture based. 2079 //@{ 2080 CK_i586, 2081 CK_Pentium, 2082 CK_PentiumMMX, 2083 //@} 2084 2085 /// \name i686 2086 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2087 //@{ 2088 CK_i686, 2089 CK_PentiumPro, 2090 CK_Pentium2, 2091 CK_Pentium3, 2092 CK_Pentium3M, 2093 CK_PentiumM, 2094 CK_C3_2, 2095 2096 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2097 /// Clang however has some logic to suport this. 2098 // FIXME: Warn, deprecate, and potentially remove this. 2099 CK_Yonah, 2100 //@} 2101 2102 /// \name Netburst 2103 /// Netburst microarchitecture based processors. 2104 //@{ 2105 CK_Pentium4, 2106 CK_Pentium4M, 2107 CK_Prescott, 2108 CK_Nocona, 2109 //@} 2110 2111 /// \name Core 2112 /// Core microarchitecture based processors. 2113 //@{ 2114 CK_Core2, 2115 2116 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2117 /// codename which GCC no longer accepts as an option to -march, but Clang 2118 /// has some logic for recognizing it. 2119 // FIXME: Warn, deprecate, and potentially remove this. 2120 CK_Penryn, 2121 //@} 2122 2123 /// \name Atom 2124 /// Atom processors 2125 //@{ 2126 CK_Bonnell, 2127 CK_Silvermont, 2128 //@} 2129 2130 /// \name Nehalem 2131 /// Nehalem microarchitecture based processors. 2132 CK_Nehalem, 2133 2134 /// \name Westmere 2135 /// Westmere microarchitecture based processors. 2136 CK_Westmere, 2137 2138 /// \name Sandy Bridge 2139 /// Sandy Bridge microarchitecture based processors. 2140 CK_SandyBridge, 2141 2142 /// \name Ivy Bridge 2143 /// Ivy Bridge microarchitecture based processors. 2144 CK_IvyBridge, 2145 2146 /// \name Haswell 2147 /// Haswell microarchitecture based processors. 2148 CK_Haswell, 2149 2150 /// \name Broadwell 2151 /// Broadwell microarchitecture based processors. 2152 CK_Broadwell, 2153 2154 /// \name Skylake 2155 /// Skylake microarchitecture based processors. 2156 CK_Skylake, 2157 2158 /// \name Knights Landing 2159 /// Knights Landing processor. 2160 CK_KNL, 2161 2162 /// \name K6 2163 /// K6 architecture processors. 2164 //@{ 2165 CK_K6, 2166 CK_K6_2, 2167 CK_K6_3, 2168 //@} 2169 2170 /// \name K7 2171 /// K7 architecture processors. 2172 //@{ 2173 CK_Athlon, 2174 CK_AthlonThunderbird, 2175 CK_Athlon4, 2176 CK_AthlonXP, 2177 CK_AthlonMP, 2178 //@} 2179 2180 /// \name K8 2181 /// K8 architecture processors. 2182 //@{ 2183 CK_Athlon64, 2184 CK_Athlon64SSE3, 2185 CK_AthlonFX, 2186 CK_K8, 2187 CK_K8SSE3, 2188 CK_Opteron, 2189 CK_OpteronSSE3, 2190 CK_AMDFAM10, 2191 //@} 2192 2193 /// \name Bobcat 2194 /// Bobcat architecture processors. 2195 //@{ 2196 CK_BTVER1, 2197 CK_BTVER2, 2198 //@} 2199 2200 /// \name Bulldozer 2201 /// Bulldozer architecture processors. 2202 //@{ 2203 CK_BDVER1, 2204 CK_BDVER2, 2205 CK_BDVER3, 2206 CK_BDVER4, 2207 //@} 2208 2209 /// This specification is deprecated and will be removed in the future. 2210 /// Users should prefer \see CK_K8. 2211 // FIXME: Warn on this when the CPU is set to it. 2212 //@{ 2213 CK_x86_64, 2214 //@} 2215 2216 /// \name Geode 2217 /// Geode processors. 2218 //@{ 2219 CK_Geode 2220 //@} 2221 } CPU; 2222 2223 enum FPMathKind { 2224 FP_Default, 2225 FP_SSE, 2226 FP_387 2227 } FPMath; 2228 2229 public: 2230 X86TargetInfo(const llvm::Triple &Triple) 2231 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2232 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2233 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2234 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2235 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2236 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2237 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2238 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2239 BigEndian = false; 2240 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2241 } 2242 unsigned getFloatEvalMethod() const override { 2243 // X87 evaluates with 80 bits "long double" precision. 2244 return SSELevel == NoSSE ? 2 : 0; 2245 } 2246 void getTargetBuiltins(const Builtin::Info *&Records, 2247 unsigned &NumRecords) const override { 2248 Records = BuiltinInfo; 2249 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2250 } 2251 void getGCCRegNames(const char * const *&Names, 2252 unsigned &NumNames) const override { 2253 Names = GCCRegNames; 2254 NumNames = llvm::array_lengthof(GCCRegNames); 2255 } 2256 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2257 unsigned &NumAliases) const override { 2258 Aliases = nullptr; 2259 NumAliases = 0; 2260 } 2261 void getGCCAddlRegNames(const AddlRegName *&Names, 2262 unsigned &NumNames) const override { 2263 Names = AddlRegNames; 2264 NumNames = llvm::array_lengthof(AddlRegNames); 2265 } 2266 bool validateCpuSupports(StringRef Name) const override; 2267 bool validateAsmConstraint(const char *&Name, 2268 TargetInfo::ConstraintInfo &info) const override; 2269 2270 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2271 2272 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2273 2274 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2275 2276 std::string convertConstraint(const char *&Constraint) const override; 2277 const char *getClobbers() const override { 2278 return "~{dirflag},~{fpsr},~{flags}"; 2279 } 2280 void getTargetDefines(const LangOptions &Opts, 2281 MacroBuilder &Builder) const override; 2282 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2283 bool Enabled); 2284 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2285 bool Enabled); 2286 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2287 bool Enabled); 2288 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2289 StringRef Name, bool Enabled) const override { 2290 setFeatureEnabledImpl(Features, Name, Enabled); 2291 } 2292 // This exists purely to cut down on the number of virtual calls in 2293 // getDefaultFeatures which calls this repeatedly. 2294 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2295 StringRef Name, bool Enabled); 2296 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2297 bool hasFeature(StringRef Feature) const override; 2298 bool handleTargetFeatures(std::vector<std::string> &Features, 2299 DiagnosticsEngine &Diags) override; 2300 StringRef getABI() const override { 2301 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2302 return "avx512"; 2303 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2304 return "avx"; 2305 else if (getTriple().getArch() == llvm::Triple::x86 && 2306 MMX3DNowLevel == NoMMX3DNow) 2307 return "no-mmx"; 2308 return ""; 2309 } 2310 bool setCPU(const std::string &Name) override { 2311 CPU = llvm::StringSwitch<CPUKind>(Name) 2312 .Case("i386", CK_i386) 2313 .Case("i486", CK_i486) 2314 .Case("winchip-c6", CK_WinChipC6) 2315 .Case("winchip2", CK_WinChip2) 2316 .Case("c3", CK_C3) 2317 .Case("i586", CK_i586) 2318 .Case("pentium", CK_Pentium) 2319 .Case("pentium-mmx", CK_PentiumMMX) 2320 .Case("i686", CK_i686) 2321 .Case("pentiumpro", CK_PentiumPro) 2322 .Case("pentium2", CK_Pentium2) 2323 .Case("pentium3", CK_Pentium3) 2324 .Case("pentium3m", CK_Pentium3M) 2325 .Case("pentium-m", CK_PentiumM) 2326 .Case("c3-2", CK_C3_2) 2327 .Case("yonah", CK_Yonah) 2328 .Case("pentium4", CK_Pentium4) 2329 .Case("pentium4m", CK_Pentium4M) 2330 .Case("prescott", CK_Prescott) 2331 .Case("nocona", CK_Nocona) 2332 .Case("core2", CK_Core2) 2333 .Case("penryn", CK_Penryn) 2334 .Case("bonnell", CK_Bonnell) 2335 .Case("atom", CK_Bonnell) // Legacy name. 2336 .Case("silvermont", CK_Silvermont) 2337 .Case("slm", CK_Silvermont) // Legacy name. 2338 .Case("nehalem", CK_Nehalem) 2339 .Case("corei7", CK_Nehalem) // Legacy name. 2340 .Case("westmere", CK_Westmere) 2341 .Case("sandybridge", CK_SandyBridge) 2342 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2343 .Case("ivybridge", CK_IvyBridge) 2344 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2345 .Case("haswell", CK_Haswell) 2346 .Case("core-avx2", CK_Haswell) // Legacy name. 2347 .Case("broadwell", CK_Broadwell) 2348 .Case("skylake", CK_Skylake) 2349 .Case("skx", CK_Skylake) // Legacy name. 2350 .Case("knl", CK_KNL) 2351 .Case("k6", CK_K6) 2352 .Case("k6-2", CK_K6_2) 2353 .Case("k6-3", CK_K6_3) 2354 .Case("athlon", CK_Athlon) 2355 .Case("athlon-tbird", CK_AthlonThunderbird) 2356 .Case("athlon-4", CK_Athlon4) 2357 .Case("athlon-xp", CK_AthlonXP) 2358 .Case("athlon-mp", CK_AthlonMP) 2359 .Case("athlon64", CK_Athlon64) 2360 .Case("athlon64-sse3", CK_Athlon64SSE3) 2361 .Case("athlon-fx", CK_AthlonFX) 2362 .Case("k8", CK_K8) 2363 .Case("k8-sse3", CK_K8SSE3) 2364 .Case("opteron", CK_Opteron) 2365 .Case("opteron-sse3", CK_OpteronSSE3) 2366 .Case("barcelona", CK_AMDFAM10) 2367 .Case("amdfam10", CK_AMDFAM10) 2368 .Case("btver1", CK_BTVER1) 2369 .Case("btver2", CK_BTVER2) 2370 .Case("bdver1", CK_BDVER1) 2371 .Case("bdver2", CK_BDVER2) 2372 .Case("bdver3", CK_BDVER3) 2373 .Case("bdver4", CK_BDVER4) 2374 .Case("x86-64", CK_x86_64) 2375 .Case("geode", CK_Geode) 2376 .Default(CK_Generic); 2377 2378 // Perform any per-CPU checks necessary to determine if this CPU is 2379 // acceptable. 2380 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2381 // invalid without explaining *why*. 2382 switch (CPU) { 2383 case CK_Generic: 2384 // No processor selected! 2385 return false; 2386 2387 case CK_i386: 2388 case CK_i486: 2389 case CK_WinChipC6: 2390 case CK_WinChip2: 2391 case CK_C3: 2392 case CK_i586: 2393 case CK_Pentium: 2394 case CK_PentiumMMX: 2395 case CK_i686: 2396 case CK_PentiumPro: 2397 case CK_Pentium2: 2398 case CK_Pentium3: 2399 case CK_Pentium3M: 2400 case CK_PentiumM: 2401 case CK_Yonah: 2402 case CK_C3_2: 2403 case CK_Pentium4: 2404 case CK_Pentium4M: 2405 case CK_Prescott: 2406 case CK_K6: 2407 case CK_K6_2: 2408 case CK_K6_3: 2409 case CK_Athlon: 2410 case CK_AthlonThunderbird: 2411 case CK_Athlon4: 2412 case CK_AthlonXP: 2413 case CK_AthlonMP: 2414 case CK_Geode: 2415 // Only accept certain architectures when compiling in 32-bit mode. 2416 if (getTriple().getArch() != llvm::Triple::x86) 2417 return false; 2418 2419 // Fallthrough 2420 case CK_Nocona: 2421 case CK_Core2: 2422 case CK_Penryn: 2423 case CK_Bonnell: 2424 case CK_Silvermont: 2425 case CK_Nehalem: 2426 case CK_Westmere: 2427 case CK_SandyBridge: 2428 case CK_IvyBridge: 2429 case CK_Haswell: 2430 case CK_Broadwell: 2431 case CK_Skylake: 2432 case CK_KNL: 2433 case CK_Athlon64: 2434 case CK_Athlon64SSE3: 2435 case CK_AthlonFX: 2436 case CK_K8: 2437 case CK_K8SSE3: 2438 case CK_Opteron: 2439 case CK_OpteronSSE3: 2440 case CK_AMDFAM10: 2441 case CK_BTVER1: 2442 case CK_BTVER2: 2443 case CK_BDVER1: 2444 case CK_BDVER2: 2445 case CK_BDVER3: 2446 case CK_BDVER4: 2447 case CK_x86_64: 2448 return true; 2449 } 2450 llvm_unreachable("Unhandled CPU kind"); 2451 } 2452 2453 bool setFPMath(StringRef Name) override; 2454 2455 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2456 // We accept all non-ARM calling conventions 2457 return (CC == CC_X86ThisCall || 2458 CC == CC_X86FastCall || 2459 CC == CC_X86StdCall || 2460 CC == CC_X86VectorCall || 2461 CC == CC_C || 2462 CC == CC_X86Pascal || 2463 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2464 } 2465 2466 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2467 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2468 } 2469 2470 bool hasSjLjLowering() const override { 2471 return true; 2472 } 2473 }; 2474 2475 bool X86TargetInfo::setFPMath(StringRef Name) { 2476 if (Name == "387") { 2477 FPMath = FP_387; 2478 return true; 2479 } 2480 if (Name == "sse") { 2481 FPMath = FP_SSE; 2482 return true; 2483 } 2484 return false; 2485 } 2486 2487 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2488 // FIXME: This *really* should not be here. 2489 2490 // X86_64 always has SSE2. 2491 if (getTriple().getArch() == llvm::Triple::x86_64) 2492 setFeatureEnabledImpl(Features, "sse2", true); 2493 2494 switch (CPU) { 2495 case CK_Generic: 2496 case CK_i386: 2497 case CK_i486: 2498 case CK_i586: 2499 case CK_Pentium: 2500 case CK_i686: 2501 case CK_PentiumPro: 2502 break; 2503 case CK_PentiumMMX: 2504 case CK_Pentium2: 2505 case CK_K6: 2506 case CK_WinChipC6: 2507 setFeatureEnabledImpl(Features, "mmx", true); 2508 break; 2509 case CK_Pentium3: 2510 case CK_Pentium3M: 2511 case CK_C3_2: 2512 setFeatureEnabledImpl(Features, "sse", true); 2513 break; 2514 case CK_PentiumM: 2515 case CK_Pentium4: 2516 case CK_Pentium4M: 2517 case CK_x86_64: 2518 setFeatureEnabledImpl(Features, "sse2", true); 2519 break; 2520 case CK_Yonah: 2521 case CK_Prescott: 2522 case CK_Nocona: 2523 setFeatureEnabledImpl(Features, "sse3", true); 2524 setFeatureEnabledImpl(Features, "cx16", true); 2525 break; 2526 case CK_Core2: 2527 case CK_Bonnell: 2528 setFeatureEnabledImpl(Features, "ssse3", true); 2529 setFeatureEnabledImpl(Features, "cx16", true); 2530 break; 2531 case CK_Penryn: 2532 setFeatureEnabledImpl(Features, "sse4.1", true); 2533 setFeatureEnabledImpl(Features, "cx16", true); 2534 break; 2535 case CK_Skylake: 2536 setFeatureEnabledImpl(Features, "avx512f", true); 2537 setFeatureEnabledImpl(Features, "avx512cd", true); 2538 setFeatureEnabledImpl(Features, "avx512dq", true); 2539 setFeatureEnabledImpl(Features, "avx512bw", true); 2540 setFeatureEnabledImpl(Features, "avx512vl", true); 2541 // FALLTHROUGH 2542 case CK_Broadwell: 2543 setFeatureEnabledImpl(Features, "rdseed", true); 2544 setFeatureEnabledImpl(Features, "adx", true); 2545 // FALLTHROUGH 2546 case CK_Haswell: 2547 setFeatureEnabledImpl(Features, "avx2", true); 2548 setFeatureEnabledImpl(Features, "lzcnt", true); 2549 setFeatureEnabledImpl(Features, "bmi", true); 2550 setFeatureEnabledImpl(Features, "bmi2", true); 2551 setFeatureEnabledImpl(Features, "rtm", true); 2552 setFeatureEnabledImpl(Features, "fma", true); 2553 // FALLTHROUGH 2554 case CK_IvyBridge: 2555 setFeatureEnabledImpl(Features, "rdrnd", true); 2556 setFeatureEnabledImpl(Features, "f16c", true); 2557 setFeatureEnabledImpl(Features, "fsgsbase", true); 2558 // FALLTHROUGH 2559 case CK_SandyBridge: 2560 setFeatureEnabledImpl(Features, "avx", true); 2561 // FALLTHROUGH 2562 case CK_Westmere: 2563 case CK_Silvermont: 2564 setFeatureEnabledImpl(Features, "aes", true); 2565 setFeatureEnabledImpl(Features, "pclmul", true); 2566 // FALLTHROUGH 2567 case CK_Nehalem: 2568 setFeatureEnabledImpl(Features, "sse4.2", true); 2569 setFeatureEnabledImpl(Features, "cx16", true); 2570 break; 2571 case CK_KNL: 2572 setFeatureEnabledImpl(Features, "avx512f", true); 2573 setFeatureEnabledImpl(Features, "avx512cd", true); 2574 setFeatureEnabledImpl(Features, "avx512er", true); 2575 setFeatureEnabledImpl(Features, "avx512pf", true); 2576 setFeatureEnabledImpl(Features, "rdseed", true); 2577 setFeatureEnabledImpl(Features, "adx", true); 2578 setFeatureEnabledImpl(Features, "lzcnt", true); 2579 setFeatureEnabledImpl(Features, "bmi", true); 2580 setFeatureEnabledImpl(Features, "bmi2", true); 2581 setFeatureEnabledImpl(Features, "rtm", true); 2582 setFeatureEnabledImpl(Features, "fma", true); 2583 setFeatureEnabledImpl(Features, "rdrnd", true); 2584 setFeatureEnabledImpl(Features, "f16c", true); 2585 setFeatureEnabledImpl(Features, "fsgsbase", true); 2586 setFeatureEnabledImpl(Features, "aes", true); 2587 setFeatureEnabledImpl(Features, "pclmul", true); 2588 setFeatureEnabledImpl(Features, "cx16", true); 2589 break; 2590 case CK_K6_2: 2591 case CK_K6_3: 2592 case CK_WinChip2: 2593 case CK_C3: 2594 setFeatureEnabledImpl(Features, "3dnow", true); 2595 break; 2596 case CK_Athlon: 2597 case CK_AthlonThunderbird: 2598 case CK_Geode: 2599 setFeatureEnabledImpl(Features, "3dnowa", true); 2600 break; 2601 case CK_Athlon4: 2602 case CK_AthlonXP: 2603 case CK_AthlonMP: 2604 setFeatureEnabledImpl(Features, "sse", true); 2605 setFeatureEnabledImpl(Features, "3dnowa", true); 2606 break; 2607 case CK_K8: 2608 case CK_Opteron: 2609 case CK_Athlon64: 2610 case CK_AthlonFX: 2611 setFeatureEnabledImpl(Features, "sse2", true); 2612 setFeatureEnabledImpl(Features, "3dnowa", true); 2613 break; 2614 case CK_AMDFAM10: 2615 setFeatureEnabledImpl(Features, "sse4a", true); 2616 setFeatureEnabledImpl(Features, "lzcnt", true); 2617 setFeatureEnabledImpl(Features, "popcnt", true); 2618 // FALLTHROUGH 2619 case CK_K8SSE3: 2620 case CK_OpteronSSE3: 2621 case CK_Athlon64SSE3: 2622 setFeatureEnabledImpl(Features, "sse3", true); 2623 setFeatureEnabledImpl(Features, "3dnowa", true); 2624 break; 2625 case CK_BTVER2: 2626 setFeatureEnabledImpl(Features, "avx", true); 2627 setFeatureEnabledImpl(Features, "aes", true); 2628 setFeatureEnabledImpl(Features, "pclmul", true); 2629 setFeatureEnabledImpl(Features, "bmi", true); 2630 setFeatureEnabledImpl(Features, "f16c", true); 2631 // FALLTHROUGH 2632 case CK_BTVER1: 2633 setFeatureEnabledImpl(Features, "ssse3", true); 2634 setFeatureEnabledImpl(Features, "sse4a", true); 2635 setFeatureEnabledImpl(Features, "lzcnt", true); 2636 setFeatureEnabledImpl(Features, "popcnt", true); 2637 setFeatureEnabledImpl(Features, "prfchw", true); 2638 setFeatureEnabledImpl(Features, "cx16", true); 2639 break; 2640 case CK_BDVER4: 2641 setFeatureEnabledImpl(Features, "avx2", true); 2642 setFeatureEnabledImpl(Features, "bmi2", true); 2643 // FALLTHROUGH 2644 case CK_BDVER3: 2645 setFeatureEnabledImpl(Features, "fsgsbase", true); 2646 // FALLTHROUGH 2647 case CK_BDVER2: 2648 setFeatureEnabledImpl(Features, "bmi", true); 2649 setFeatureEnabledImpl(Features, "fma", true); 2650 setFeatureEnabledImpl(Features, "f16c", true); 2651 setFeatureEnabledImpl(Features, "tbm", true); 2652 // FALLTHROUGH 2653 case CK_BDVER1: 2654 // xop implies avx, sse4a and fma4. 2655 setFeatureEnabledImpl(Features, "xop", true); 2656 setFeatureEnabledImpl(Features, "lzcnt", true); 2657 setFeatureEnabledImpl(Features, "aes", true); 2658 setFeatureEnabledImpl(Features, "pclmul", true); 2659 setFeatureEnabledImpl(Features, "prfchw", true); 2660 setFeatureEnabledImpl(Features, "cx16", true); 2661 break; 2662 } 2663 } 2664 2665 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2666 X86SSEEnum Level, bool Enabled) { 2667 if (Enabled) { 2668 switch (Level) { 2669 case AVX512F: 2670 Features["avx512f"] = true; 2671 case AVX2: 2672 Features["avx2"] = true; 2673 case AVX: 2674 Features["avx"] = true; 2675 case SSE42: 2676 Features["sse4.2"] = true; 2677 case SSE41: 2678 Features["sse4.1"] = true; 2679 case SSSE3: 2680 Features["ssse3"] = true; 2681 case SSE3: 2682 Features["sse3"] = true; 2683 case SSE2: 2684 Features["sse2"] = true; 2685 case SSE1: 2686 Features["sse"] = true; 2687 case NoSSE: 2688 break; 2689 } 2690 return; 2691 } 2692 2693 switch (Level) { 2694 case NoSSE: 2695 case SSE1: 2696 Features["sse"] = false; 2697 case SSE2: 2698 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2699 Features["sha"] = false; 2700 case SSE3: 2701 Features["sse3"] = false; 2702 setXOPLevel(Features, NoXOP, false); 2703 case SSSE3: 2704 Features["ssse3"] = false; 2705 case SSE41: 2706 Features["sse4.1"] = false; 2707 case SSE42: 2708 Features["sse4.2"] = false; 2709 case AVX: 2710 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2711 setXOPLevel(Features, FMA4, false); 2712 case AVX2: 2713 Features["avx2"] = false; 2714 case AVX512F: 2715 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2716 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2717 Features["avx512vl"] = false; 2718 } 2719 } 2720 2721 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2722 MMX3DNowEnum Level, bool Enabled) { 2723 if (Enabled) { 2724 switch (Level) { 2725 case AMD3DNowAthlon: 2726 Features["3dnowa"] = true; 2727 case AMD3DNow: 2728 Features["3dnow"] = true; 2729 case MMX: 2730 Features["mmx"] = true; 2731 case NoMMX3DNow: 2732 break; 2733 } 2734 return; 2735 } 2736 2737 switch (Level) { 2738 case NoMMX3DNow: 2739 case MMX: 2740 Features["mmx"] = false; 2741 case AMD3DNow: 2742 Features["3dnow"] = false; 2743 case AMD3DNowAthlon: 2744 Features["3dnowa"] = false; 2745 } 2746 } 2747 2748 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2749 bool Enabled) { 2750 if (Enabled) { 2751 switch (Level) { 2752 case XOP: 2753 Features["xop"] = true; 2754 case FMA4: 2755 Features["fma4"] = true; 2756 setSSELevel(Features, AVX, true); 2757 case SSE4A: 2758 Features["sse4a"] = true; 2759 setSSELevel(Features, SSE3, true); 2760 case NoXOP: 2761 break; 2762 } 2763 return; 2764 } 2765 2766 switch (Level) { 2767 case NoXOP: 2768 case SSE4A: 2769 Features["sse4a"] = false; 2770 case FMA4: 2771 Features["fma4"] = false; 2772 case XOP: 2773 Features["xop"] = false; 2774 } 2775 } 2776 2777 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2778 StringRef Name, bool Enabled) { 2779 // This is a bit of a hack to deal with the sse4 target feature when used 2780 // as part of the target attribute. We handle sse4 correctly everywhere 2781 // else. See below for more information on how we handle the sse4 options. 2782 if (Name != "sse4") 2783 Features[Name] = Enabled; 2784 2785 if (Name == "mmx") { 2786 setMMXLevel(Features, MMX, Enabled); 2787 } else if (Name == "sse") { 2788 setSSELevel(Features, SSE1, Enabled); 2789 } else if (Name == "sse2") { 2790 setSSELevel(Features, SSE2, Enabled); 2791 } else if (Name == "sse3") { 2792 setSSELevel(Features, SSE3, Enabled); 2793 } else if (Name == "ssse3") { 2794 setSSELevel(Features, SSSE3, Enabled); 2795 } else if (Name == "sse4.2") { 2796 setSSELevel(Features, SSE42, Enabled); 2797 } else if (Name == "sse4.1") { 2798 setSSELevel(Features, SSE41, Enabled); 2799 } else if (Name == "3dnow") { 2800 setMMXLevel(Features, AMD3DNow, Enabled); 2801 } else if (Name == "3dnowa") { 2802 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2803 } else if (Name == "aes") { 2804 if (Enabled) 2805 setSSELevel(Features, SSE2, Enabled); 2806 } else if (Name == "pclmul") { 2807 if (Enabled) 2808 setSSELevel(Features, SSE2, Enabled); 2809 } else if (Name == "avx") { 2810 setSSELevel(Features, AVX, Enabled); 2811 } else if (Name == "avx2") { 2812 setSSELevel(Features, AVX2, Enabled); 2813 } else if (Name == "avx512f") { 2814 setSSELevel(Features, AVX512F, Enabled); 2815 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2816 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2817 if (Enabled) 2818 setSSELevel(Features, AVX512F, Enabled); 2819 } else if (Name == "fma") { 2820 if (Enabled) 2821 setSSELevel(Features, AVX, Enabled); 2822 } else if (Name == "fma4") { 2823 setXOPLevel(Features, FMA4, Enabled); 2824 } else if (Name == "xop") { 2825 setXOPLevel(Features, XOP, Enabled); 2826 } else if (Name == "sse4a") { 2827 setXOPLevel(Features, SSE4A, Enabled); 2828 } else if (Name == "f16c") { 2829 if (Enabled) 2830 setSSELevel(Features, AVX, Enabled); 2831 } else if (Name == "sha") { 2832 if (Enabled) 2833 setSSELevel(Features, SSE2, Enabled); 2834 } else if (Name == "sse4") { 2835 // We can get here via the __target__ attribute since that's not controlled 2836 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2837 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2838 // disabled. 2839 if (Enabled) 2840 setSSELevel(Features, SSE42, Enabled); 2841 else 2842 setSSELevel(Features, SSE41, Enabled); 2843 } 2844 } 2845 2846 /// handleTargetFeatures - Perform initialization based on the user 2847 /// configured set of features. 2848 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2849 DiagnosticsEngine &Diags) { 2850 // Remember the maximum enabled sselevel. 2851 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2852 // Ignore disabled features. 2853 if (Features[i][0] == '-') 2854 continue; 2855 2856 StringRef Feature = StringRef(Features[i]).substr(1); 2857 2858 if (Feature == "aes") { 2859 HasAES = true; 2860 continue; 2861 } 2862 2863 if (Feature == "pclmul") { 2864 HasPCLMUL = true; 2865 continue; 2866 } 2867 2868 if (Feature == "lzcnt") { 2869 HasLZCNT = true; 2870 continue; 2871 } 2872 2873 if (Feature == "rdrnd") { 2874 HasRDRND = true; 2875 continue; 2876 } 2877 2878 if (Feature == "fsgsbase") { 2879 HasFSGSBASE = true; 2880 continue; 2881 } 2882 2883 if (Feature == "bmi") { 2884 HasBMI = true; 2885 continue; 2886 } 2887 2888 if (Feature == "bmi2") { 2889 HasBMI2 = true; 2890 continue; 2891 } 2892 2893 if (Feature == "popcnt") { 2894 HasPOPCNT = true; 2895 continue; 2896 } 2897 2898 if (Feature == "rtm") { 2899 HasRTM = true; 2900 continue; 2901 } 2902 2903 if (Feature == "prfchw") { 2904 HasPRFCHW = true; 2905 continue; 2906 } 2907 2908 if (Feature == "rdseed") { 2909 HasRDSEED = true; 2910 continue; 2911 } 2912 2913 if (Feature == "adx") { 2914 HasADX = true; 2915 continue; 2916 } 2917 2918 if (Feature == "tbm") { 2919 HasTBM = true; 2920 continue; 2921 } 2922 2923 if (Feature == "fma") { 2924 HasFMA = true; 2925 continue; 2926 } 2927 2928 if (Feature == "f16c") { 2929 HasF16C = true; 2930 continue; 2931 } 2932 2933 if (Feature == "avx512cd") { 2934 HasAVX512CD = true; 2935 continue; 2936 } 2937 2938 if (Feature == "avx512er") { 2939 HasAVX512ER = true; 2940 continue; 2941 } 2942 2943 if (Feature == "avx512pf") { 2944 HasAVX512PF = true; 2945 continue; 2946 } 2947 2948 if (Feature == "avx512dq") { 2949 HasAVX512DQ = true; 2950 continue; 2951 } 2952 2953 if (Feature == "avx512bw") { 2954 HasAVX512BW = true; 2955 continue; 2956 } 2957 2958 if (Feature == "avx512vl") { 2959 HasAVX512VL = true; 2960 continue; 2961 } 2962 2963 if (Feature == "sha") { 2964 HasSHA = true; 2965 continue; 2966 } 2967 2968 if (Feature == "cx16") { 2969 HasCX16 = true; 2970 continue; 2971 } 2972 2973 assert(Features[i][0] == '+' && "Invalid target feature!"); 2974 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2975 .Case("avx512f", AVX512F) 2976 .Case("avx2", AVX2) 2977 .Case("avx", AVX) 2978 .Case("sse4.2", SSE42) 2979 .Case("sse4.1", SSE41) 2980 .Case("ssse3", SSSE3) 2981 .Case("sse3", SSE3) 2982 .Case("sse2", SSE2) 2983 .Case("sse", SSE1) 2984 .Default(NoSSE); 2985 SSELevel = std::max(SSELevel, Level); 2986 2987 MMX3DNowEnum ThreeDNowLevel = 2988 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2989 .Case("3dnowa", AMD3DNowAthlon) 2990 .Case("3dnow", AMD3DNow) 2991 .Case("mmx", MMX) 2992 .Default(NoMMX3DNow); 2993 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2994 2995 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2996 .Case("xop", XOP) 2997 .Case("fma4", FMA4) 2998 .Case("sse4a", SSE4A) 2999 .Default(NoXOP); 3000 XOPLevel = std::max(XOPLevel, XLevel); 3001 } 3002 3003 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3004 // Can't do this earlier because we need to be able to explicitly enable 3005 // popcnt and still disable sse4.2. 3006 if (!HasPOPCNT && SSELevel >= SSE42 && 3007 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 3008 HasPOPCNT = true; 3009 Features.push_back("+popcnt"); 3010 } 3011 3012 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3013 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 3014 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 3015 HasPRFCHW = true; 3016 Features.push_back("+prfchw"); 3017 } 3018 3019 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3020 // matches the selected sse level. 3021 if (FPMath == FP_SSE && SSELevel < SSE1) { 3022 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3023 return false; 3024 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3025 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3026 return false; 3027 } 3028 3029 // Don't tell the backend if we're turning off mmx; it will end up disabling 3030 // SSE, which we don't want. 3031 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3032 // then enable MMX. 3033 std::vector<std::string>::iterator it; 3034 it = std::find(Features.begin(), Features.end(), "-mmx"); 3035 if (it != Features.end()) 3036 Features.erase(it); 3037 else if (SSELevel > NoSSE) 3038 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3039 3040 SimdDefaultAlign = 3041 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 3042 return true; 3043 } 3044 3045 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3046 /// definitions for this particular subtarget. 3047 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3048 MacroBuilder &Builder) const { 3049 // Target identification. 3050 if (getTriple().getArch() == llvm::Triple::x86_64) { 3051 Builder.defineMacro("__amd64__"); 3052 Builder.defineMacro("__amd64"); 3053 Builder.defineMacro("__x86_64"); 3054 Builder.defineMacro("__x86_64__"); 3055 if (getTriple().getArchName() == "x86_64h") { 3056 Builder.defineMacro("__x86_64h"); 3057 Builder.defineMacro("__x86_64h__"); 3058 } 3059 } else { 3060 DefineStd(Builder, "i386", Opts); 3061 } 3062 3063 // Subtarget options. 3064 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3065 // truly should be based on -mtune options. 3066 switch (CPU) { 3067 case CK_Generic: 3068 break; 3069 case CK_i386: 3070 // The rest are coming from the i386 define above. 3071 Builder.defineMacro("__tune_i386__"); 3072 break; 3073 case CK_i486: 3074 case CK_WinChipC6: 3075 case CK_WinChip2: 3076 case CK_C3: 3077 defineCPUMacros(Builder, "i486"); 3078 break; 3079 case CK_PentiumMMX: 3080 Builder.defineMacro("__pentium_mmx__"); 3081 Builder.defineMacro("__tune_pentium_mmx__"); 3082 // Fallthrough 3083 case CK_i586: 3084 case CK_Pentium: 3085 defineCPUMacros(Builder, "i586"); 3086 defineCPUMacros(Builder, "pentium"); 3087 break; 3088 case CK_Pentium3: 3089 case CK_Pentium3M: 3090 case CK_PentiumM: 3091 Builder.defineMacro("__tune_pentium3__"); 3092 // Fallthrough 3093 case CK_Pentium2: 3094 case CK_C3_2: 3095 Builder.defineMacro("__tune_pentium2__"); 3096 // Fallthrough 3097 case CK_PentiumPro: 3098 Builder.defineMacro("__tune_i686__"); 3099 Builder.defineMacro("__tune_pentiumpro__"); 3100 // Fallthrough 3101 case CK_i686: 3102 Builder.defineMacro("__i686"); 3103 Builder.defineMacro("__i686__"); 3104 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3105 Builder.defineMacro("__pentiumpro"); 3106 Builder.defineMacro("__pentiumpro__"); 3107 break; 3108 case CK_Pentium4: 3109 case CK_Pentium4M: 3110 defineCPUMacros(Builder, "pentium4"); 3111 break; 3112 case CK_Yonah: 3113 case CK_Prescott: 3114 case CK_Nocona: 3115 defineCPUMacros(Builder, "nocona"); 3116 break; 3117 case CK_Core2: 3118 case CK_Penryn: 3119 defineCPUMacros(Builder, "core2"); 3120 break; 3121 case CK_Bonnell: 3122 defineCPUMacros(Builder, "atom"); 3123 break; 3124 case CK_Silvermont: 3125 defineCPUMacros(Builder, "slm"); 3126 break; 3127 case CK_Nehalem: 3128 case CK_Westmere: 3129 case CK_SandyBridge: 3130 case CK_IvyBridge: 3131 case CK_Haswell: 3132 case CK_Broadwell: 3133 // FIXME: Historically, we defined this legacy name, it would be nice to 3134 // remove it at some point. We've never exposed fine-grained names for 3135 // recent primary x86 CPUs, and we should keep it that way. 3136 defineCPUMacros(Builder, "corei7"); 3137 break; 3138 case CK_Skylake: 3139 // FIXME: Historically, we defined this legacy name, it would be nice to 3140 // remove it at some point. This is the only fine-grained CPU macro in the 3141 // main intel CPU line, and it would be better to not have these and force 3142 // people to use ISA macros. 3143 defineCPUMacros(Builder, "skx"); 3144 break; 3145 case CK_KNL: 3146 defineCPUMacros(Builder, "knl"); 3147 break; 3148 case CK_K6_2: 3149 Builder.defineMacro("__k6_2__"); 3150 Builder.defineMacro("__tune_k6_2__"); 3151 // Fallthrough 3152 case CK_K6_3: 3153 if (CPU != CK_K6_2) { // In case of fallthrough 3154 // FIXME: GCC may be enabling these in cases where some other k6 3155 // architecture is specified but -m3dnow is explicitly provided. The 3156 // exact semantics need to be determined and emulated here. 3157 Builder.defineMacro("__k6_3__"); 3158 Builder.defineMacro("__tune_k6_3__"); 3159 } 3160 // Fallthrough 3161 case CK_K6: 3162 defineCPUMacros(Builder, "k6"); 3163 break; 3164 case CK_Athlon: 3165 case CK_AthlonThunderbird: 3166 case CK_Athlon4: 3167 case CK_AthlonXP: 3168 case CK_AthlonMP: 3169 defineCPUMacros(Builder, "athlon"); 3170 if (SSELevel != NoSSE) { 3171 Builder.defineMacro("__athlon_sse__"); 3172 Builder.defineMacro("__tune_athlon_sse__"); 3173 } 3174 break; 3175 case CK_K8: 3176 case CK_K8SSE3: 3177 case CK_x86_64: 3178 case CK_Opteron: 3179 case CK_OpteronSSE3: 3180 case CK_Athlon64: 3181 case CK_Athlon64SSE3: 3182 case CK_AthlonFX: 3183 defineCPUMacros(Builder, "k8"); 3184 break; 3185 case CK_AMDFAM10: 3186 defineCPUMacros(Builder, "amdfam10"); 3187 break; 3188 case CK_BTVER1: 3189 defineCPUMacros(Builder, "btver1"); 3190 break; 3191 case CK_BTVER2: 3192 defineCPUMacros(Builder, "btver2"); 3193 break; 3194 case CK_BDVER1: 3195 defineCPUMacros(Builder, "bdver1"); 3196 break; 3197 case CK_BDVER2: 3198 defineCPUMacros(Builder, "bdver2"); 3199 break; 3200 case CK_BDVER3: 3201 defineCPUMacros(Builder, "bdver3"); 3202 break; 3203 case CK_BDVER4: 3204 defineCPUMacros(Builder, "bdver4"); 3205 break; 3206 case CK_Geode: 3207 defineCPUMacros(Builder, "geode"); 3208 break; 3209 } 3210 3211 // Target properties. 3212 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3213 3214 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3215 // functions in glibc header files that use FP Stack inline asm which the 3216 // backend can't deal with (PR879). 3217 Builder.defineMacro("__NO_MATH_INLINES"); 3218 3219 if (HasAES) 3220 Builder.defineMacro("__AES__"); 3221 3222 if (HasPCLMUL) 3223 Builder.defineMacro("__PCLMUL__"); 3224 3225 if (HasLZCNT) 3226 Builder.defineMacro("__LZCNT__"); 3227 3228 if (HasRDRND) 3229 Builder.defineMacro("__RDRND__"); 3230 3231 if (HasFSGSBASE) 3232 Builder.defineMacro("__FSGSBASE__"); 3233 3234 if (HasBMI) 3235 Builder.defineMacro("__BMI__"); 3236 3237 if (HasBMI2) 3238 Builder.defineMacro("__BMI2__"); 3239 3240 if (HasPOPCNT) 3241 Builder.defineMacro("__POPCNT__"); 3242 3243 if (HasRTM) 3244 Builder.defineMacro("__RTM__"); 3245 3246 if (HasPRFCHW) 3247 Builder.defineMacro("__PRFCHW__"); 3248 3249 if (HasRDSEED) 3250 Builder.defineMacro("__RDSEED__"); 3251 3252 if (HasADX) 3253 Builder.defineMacro("__ADX__"); 3254 3255 if (HasTBM) 3256 Builder.defineMacro("__TBM__"); 3257 3258 switch (XOPLevel) { 3259 case XOP: 3260 Builder.defineMacro("__XOP__"); 3261 case FMA4: 3262 Builder.defineMacro("__FMA4__"); 3263 case SSE4A: 3264 Builder.defineMacro("__SSE4A__"); 3265 case NoXOP: 3266 break; 3267 } 3268 3269 if (HasFMA) 3270 Builder.defineMacro("__FMA__"); 3271 3272 if (HasF16C) 3273 Builder.defineMacro("__F16C__"); 3274 3275 if (HasAVX512CD) 3276 Builder.defineMacro("__AVX512CD__"); 3277 if (HasAVX512ER) 3278 Builder.defineMacro("__AVX512ER__"); 3279 if (HasAVX512PF) 3280 Builder.defineMacro("__AVX512PF__"); 3281 if (HasAVX512DQ) 3282 Builder.defineMacro("__AVX512DQ__"); 3283 if (HasAVX512BW) 3284 Builder.defineMacro("__AVX512BW__"); 3285 if (HasAVX512VL) 3286 Builder.defineMacro("__AVX512VL__"); 3287 3288 if (HasSHA) 3289 Builder.defineMacro("__SHA__"); 3290 3291 if (HasCX16) 3292 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3293 3294 // Each case falls through to the previous one here. 3295 switch (SSELevel) { 3296 case AVX512F: 3297 Builder.defineMacro("__AVX512F__"); 3298 case AVX2: 3299 Builder.defineMacro("__AVX2__"); 3300 case AVX: 3301 Builder.defineMacro("__AVX__"); 3302 case SSE42: 3303 Builder.defineMacro("__SSE4_2__"); 3304 case SSE41: 3305 Builder.defineMacro("__SSE4_1__"); 3306 case SSSE3: 3307 Builder.defineMacro("__SSSE3__"); 3308 case SSE3: 3309 Builder.defineMacro("__SSE3__"); 3310 case SSE2: 3311 Builder.defineMacro("__SSE2__"); 3312 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3313 case SSE1: 3314 Builder.defineMacro("__SSE__"); 3315 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3316 case NoSSE: 3317 break; 3318 } 3319 3320 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3321 switch (SSELevel) { 3322 case AVX512F: 3323 case AVX2: 3324 case AVX: 3325 case SSE42: 3326 case SSE41: 3327 case SSSE3: 3328 case SSE3: 3329 case SSE2: 3330 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3331 break; 3332 case SSE1: 3333 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3334 break; 3335 default: 3336 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3337 } 3338 } 3339 3340 // Each case falls through to the previous one here. 3341 switch (MMX3DNowLevel) { 3342 case AMD3DNowAthlon: 3343 Builder.defineMacro("__3dNOW_A__"); 3344 case AMD3DNow: 3345 Builder.defineMacro("__3dNOW__"); 3346 case MMX: 3347 Builder.defineMacro("__MMX__"); 3348 case NoMMX3DNow: 3349 break; 3350 } 3351 3352 if (CPU >= CK_i486) { 3353 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3354 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3355 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3356 } 3357 if (CPU >= CK_i586) 3358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3359 } 3360 3361 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3362 return llvm::StringSwitch<bool>(Feature) 3363 .Case("aes", HasAES) 3364 .Case("avx", SSELevel >= AVX) 3365 .Case("avx2", SSELevel >= AVX2) 3366 .Case("avx512f", SSELevel >= AVX512F) 3367 .Case("avx512cd", HasAVX512CD) 3368 .Case("avx512er", HasAVX512ER) 3369 .Case("avx512pf", HasAVX512PF) 3370 .Case("avx512dq", HasAVX512DQ) 3371 .Case("avx512bw", HasAVX512BW) 3372 .Case("avx512vl", HasAVX512VL) 3373 .Case("bmi", HasBMI) 3374 .Case("bmi2", HasBMI2) 3375 .Case("cx16", HasCX16) 3376 .Case("f16c", HasF16C) 3377 .Case("fma", HasFMA) 3378 .Case("fma4", XOPLevel >= FMA4) 3379 .Case("fsgsbase", HasFSGSBASE) 3380 .Case("lzcnt", HasLZCNT) 3381 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3382 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3383 .Case("mmx", MMX3DNowLevel >= MMX) 3384 .Case("pclmul", HasPCLMUL) 3385 .Case("popcnt", HasPOPCNT) 3386 .Case("prfchw", HasPRFCHW) 3387 .Case("rdrnd", HasRDRND) 3388 .Case("rdseed", HasRDSEED) 3389 .Case("rtm", HasRTM) 3390 .Case("sha", HasSHA) 3391 .Case("sse", SSELevel >= SSE1) 3392 .Case("sse2", SSELevel >= SSE2) 3393 .Case("sse3", SSELevel >= SSE3) 3394 .Case("ssse3", SSELevel >= SSSE3) 3395 .Case("sse4.1", SSELevel >= SSE41) 3396 .Case("sse4.2", SSELevel >= SSE42) 3397 .Case("sse4a", XOPLevel >= SSE4A) 3398 .Case("tbm", HasTBM) 3399 .Case("x86", true) 3400 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3401 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3402 .Case("xop", XOPLevel >= XOP) 3403 .Default(false); 3404 } 3405 3406 // We can't use a generic validation scheme for the features accepted here 3407 // versus subtarget features accepted in the target attribute because the 3408 // bitfield structure that's initialized in the runtime only supports the 3409 // below currently rather than the full range of subtarget features. (See 3410 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3411 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3412 return llvm::StringSwitch<bool>(FeatureStr) 3413 .Case("cmov", true) 3414 .Case("mmx", true) 3415 .Case("popcnt", true) 3416 .Case("sse", true) 3417 .Case("sse2", true) 3418 .Case("sse3", true) 3419 .Case("sse4.1", true) 3420 .Case("sse4.2", true) 3421 .Case("avx", true) 3422 .Case("avx2", true) 3423 .Case("sse4a", true) 3424 .Case("fma4", true) 3425 .Case("xop", true) 3426 .Case("fma", true) 3427 .Case("avx512f", true) 3428 .Case("bmi", true) 3429 .Case("bmi2", true) 3430 .Default(false); 3431 } 3432 3433 bool 3434 X86TargetInfo::validateAsmConstraint(const char *&Name, 3435 TargetInfo::ConstraintInfo &Info) const { 3436 switch (*Name) { 3437 default: return false; 3438 case 'I': 3439 Info.setRequiresImmediate(0, 31); 3440 return true; 3441 case 'J': 3442 Info.setRequiresImmediate(0, 63); 3443 return true; 3444 case 'K': 3445 Info.setRequiresImmediate(-128, 127); 3446 return true; 3447 case 'L': 3448 // FIXME: properly analyze this constraint: 3449 // must be one of 0xff, 0xffff, or 0xffffffff 3450 return true; 3451 case 'M': 3452 Info.setRequiresImmediate(0, 3); 3453 return true; 3454 case 'N': 3455 Info.setRequiresImmediate(0, 255); 3456 return true; 3457 case 'O': 3458 Info.setRequiresImmediate(0, 127); 3459 return true; 3460 case 'Y': // first letter of a pair: 3461 switch (*(Name+1)) { 3462 default: return false; 3463 case '0': // First SSE register. 3464 case 't': // Any SSE register, when SSE2 is enabled. 3465 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3466 case 'm': // any MMX register, when inter-unit moves enabled. 3467 break; // falls through to setAllowsRegister. 3468 } 3469 case 'f': // any x87 floating point stack register. 3470 // Constraint 'f' cannot be used for output operands. 3471 if (Info.ConstraintStr[0] == '=') 3472 return false; 3473 3474 Info.setAllowsRegister(); 3475 return true; 3476 case 'a': // eax. 3477 case 'b': // ebx. 3478 case 'c': // ecx. 3479 case 'd': // edx. 3480 case 'S': // esi. 3481 case 'D': // edi. 3482 case 'A': // edx:eax. 3483 case 't': // top of floating point stack. 3484 case 'u': // second from top of floating point stack. 3485 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3486 case 'y': // Any MMX register. 3487 case 'x': // Any SSE register. 3488 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3489 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3490 case 'l': // "Index" registers: any general register that can be used as an 3491 // index in a base+index memory access. 3492 Info.setAllowsRegister(); 3493 return true; 3494 case 'C': // SSE floating point constant. 3495 case 'G': // x87 floating point constant. 3496 case 'e': // 32-bit signed integer constant for use with zero-extending 3497 // x86_64 instructions. 3498 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3499 // x86_64 instructions. 3500 return true; 3501 } 3502 } 3503 3504 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3505 unsigned Size) const { 3506 // Strip off constraint modifiers. 3507 while (Constraint[0] == '=' || 3508 Constraint[0] == '+' || 3509 Constraint[0] == '&') 3510 Constraint = Constraint.substr(1); 3511 3512 return validateOperandSize(Constraint, Size); 3513 } 3514 3515 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3516 unsigned Size) const { 3517 return validateOperandSize(Constraint, Size); 3518 } 3519 3520 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3521 unsigned Size) const { 3522 switch (Constraint[0]) { 3523 default: break; 3524 case 'y': 3525 return Size <= 64; 3526 case 'f': 3527 case 't': 3528 case 'u': 3529 return Size <= 128; 3530 case 'x': 3531 // 256-bit ymm registers can be used if target supports AVX. 3532 return Size <= (SSELevel >= AVX ? 256U : 128U); 3533 } 3534 3535 return true; 3536 } 3537 3538 std::string 3539 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3540 switch (*Constraint) { 3541 case 'a': return std::string("{ax}"); 3542 case 'b': return std::string("{bx}"); 3543 case 'c': return std::string("{cx}"); 3544 case 'd': return std::string("{dx}"); 3545 case 'S': return std::string("{si}"); 3546 case 'D': return std::string("{di}"); 3547 case 'p': // address 3548 return std::string("im"); 3549 case 't': // top of floating point stack. 3550 return std::string("{st}"); 3551 case 'u': // second from top of floating point stack. 3552 return std::string("{st(1)}"); // second from top of floating point stack. 3553 default: 3554 return std::string(1, *Constraint); 3555 } 3556 } 3557 3558 // X86-32 generic target 3559 class X86_32TargetInfo : public X86TargetInfo { 3560 public: 3561 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3562 DoubleAlign = LongLongAlign = 32; 3563 LongDoubleWidth = 96; 3564 LongDoubleAlign = 32; 3565 SuitableAlign = 128; 3566 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3567 SizeType = UnsignedInt; 3568 PtrDiffType = SignedInt; 3569 IntPtrType = SignedInt; 3570 RegParmMax = 3; 3571 3572 // Use fpret for all types. 3573 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3574 (1 << TargetInfo::Double) | 3575 (1 << TargetInfo::LongDouble)); 3576 3577 // x86-32 has atomics up to 8 bytes 3578 // FIXME: Check that we actually have cmpxchg8b before setting 3579 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3580 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3581 } 3582 BuiltinVaListKind getBuiltinVaListKind() const override { 3583 return TargetInfo::CharPtrBuiltinVaList; 3584 } 3585 3586 int getEHDataRegisterNumber(unsigned RegNo) const override { 3587 if (RegNo == 0) return 0; 3588 if (RegNo == 1) return 2; 3589 return -1; 3590 } 3591 bool validateOperandSize(StringRef Constraint, 3592 unsigned Size) const override { 3593 switch (Constraint[0]) { 3594 default: break; 3595 case 'R': 3596 case 'q': 3597 case 'Q': 3598 case 'a': 3599 case 'b': 3600 case 'c': 3601 case 'd': 3602 case 'S': 3603 case 'D': 3604 return Size <= 32; 3605 case 'A': 3606 return Size <= 64; 3607 } 3608 3609 return X86TargetInfo::validateOperandSize(Constraint, Size); 3610 } 3611 }; 3612 3613 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3614 public: 3615 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3616 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3617 3618 unsigned getFloatEvalMethod() const override { 3619 unsigned Major, Minor, Micro; 3620 getTriple().getOSVersion(Major, Minor, Micro); 3621 // New NetBSD uses the default rounding mode. 3622 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3623 return X86_32TargetInfo::getFloatEvalMethod(); 3624 // NetBSD before 6.99.26 defaults to "double" rounding. 3625 return 1; 3626 } 3627 }; 3628 3629 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3630 public: 3631 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3632 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3633 SizeType = UnsignedLong; 3634 IntPtrType = SignedLong; 3635 PtrDiffType = SignedLong; 3636 } 3637 }; 3638 3639 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3640 public: 3641 BitrigI386TargetInfo(const llvm::Triple &Triple) 3642 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3643 SizeType = UnsignedLong; 3644 IntPtrType = SignedLong; 3645 PtrDiffType = SignedLong; 3646 } 3647 }; 3648 3649 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3650 public: 3651 DarwinI386TargetInfo(const llvm::Triple &Triple) 3652 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3653 LongDoubleWidth = 128; 3654 LongDoubleAlign = 128; 3655 SuitableAlign = 128; 3656 MaxVectorAlign = 256; 3657 SizeType = UnsignedLong; 3658 IntPtrType = SignedLong; 3659 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3660 HasAlignMac68kSupport = true; 3661 } 3662 3663 }; 3664 3665 // x86-32 Windows target 3666 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3667 public: 3668 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3669 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3670 WCharType = UnsignedShort; 3671 DoubleAlign = LongLongAlign = 64; 3672 bool IsWinCOFF = 3673 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3674 DescriptionString = IsWinCOFF 3675 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3676 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3677 } 3678 void getTargetDefines(const LangOptions &Opts, 3679 MacroBuilder &Builder) const override { 3680 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3681 } 3682 }; 3683 3684 // x86-32 Windows Visual Studio target 3685 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3686 public: 3687 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3688 : WindowsX86_32TargetInfo(Triple) { 3689 LongDoubleWidth = LongDoubleAlign = 64; 3690 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3691 } 3692 void getTargetDefines(const LangOptions &Opts, 3693 MacroBuilder &Builder) const override { 3694 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3695 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3696 // The value of the following reflects processor type. 3697 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3698 // We lost the original triple, so we use the default. 3699 Builder.defineMacro("_M_IX86", "600"); 3700 } 3701 }; 3702 } // end anonymous namespace 3703 3704 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3705 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3706 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3707 // macro anyway for pre-processor compatibility. 3708 if (Opts.MicrosoftExt) 3709 Builder.defineMacro("__declspec", "__declspec"); 3710 else 3711 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3712 3713 if (!Opts.MicrosoftExt) { 3714 // Provide macros for all the calling convention keywords. Provide both 3715 // single and double underscore prefixed variants. These are available on 3716 // x64 as well as x86, even though they have no effect. 3717 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3718 for (const char *CC : CCs) { 3719 std::string GCCSpelling = "__attribute__((__"; 3720 GCCSpelling += CC; 3721 GCCSpelling += "__))"; 3722 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3723 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3724 } 3725 } 3726 } 3727 3728 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3729 Builder.defineMacro("__MSVCRT__"); 3730 Builder.defineMacro("__MINGW32__"); 3731 addCygMingDefines(Opts, Builder); 3732 } 3733 3734 namespace { 3735 // x86-32 MinGW target 3736 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3737 public: 3738 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3739 : WindowsX86_32TargetInfo(Triple) {} 3740 void getTargetDefines(const LangOptions &Opts, 3741 MacroBuilder &Builder) const override { 3742 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3743 DefineStd(Builder, "WIN32", Opts); 3744 DefineStd(Builder, "WINNT", Opts); 3745 Builder.defineMacro("_X86_"); 3746 addMinGWDefines(Opts, Builder); 3747 } 3748 }; 3749 3750 // x86-32 Cygwin target 3751 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3752 public: 3753 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3754 : X86_32TargetInfo(Triple) { 3755 TLSSupported = false; 3756 WCharType = UnsignedShort; 3757 DoubleAlign = LongLongAlign = 64; 3758 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3759 } 3760 void getTargetDefines(const LangOptions &Opts, 3761 MacroBuilder &Builder) const override { 3762 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3763 Builder.defineMacro("_X86_"); 3764 Builder.defineMacro("__CYGWIN__"); 3765 Builder.defineMacro("__CYGWIN32__"); 3766 addCygMingDefines(Opts, Builder); 3767 DefineStd(Builder, "unix", Opts); 3768 if (Opts.CPlusPlus) 3769 Builder.defineMacro("_GNU_SOURCE"); 3770 } 3771 }; 3772 3773 // x86-32 Haiku target 3774 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3775 public: 3776 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3777 SizeType = UnsignedLong; 3778 IntPtrType = SignedLong; 3779 PtrDiffType = SignedLong; 3780 ProcessIDType = SignedLong; 3781 this->UserLabelPrefix = ""; 3782 this->TLSSupported = false; 3783 } 3784 void getTargetDefines(const LangOptions &Opts, 3785 MacroBuilder &Builder) const override { 3786 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3787 Builder.defineMacro("__INTEL__"); 3788 Builder.defineMacro("__HAIKU__"); 3789 } 3790 }; 3791 3792 // RTEMS Target 3793 template<typename Target> 3794 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3795 protected: 3796 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3797 MacroBuilder &Builder) const override { 3798 // RTEMS defines; list based off of gcc output 3799 3800 Builder.defineMacro("__rtems__"); 3801 Builder.defineMacro("__ELF__"); 3802 } 3803 3804 public: 3805 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3806 this->UserLabelPrefix = ""; 3807 3808 switch (Triple.getArch()) { 3809 default: 3810 case llvm::Triple::x86: 3811 // this->MCountName = ".mcount"; 3812 break; 3813 case llvm::Triple::mips: 3814 case llvm::Triple::mipsel: 3815 case llvm::Triple::ppc: 3816 case llvm::Triple::ppc64: 3817 case llvm::Triple::ppc64le: 3818 // this->MCountName = "_mcount"; 3819 break; 3820 case llvm::Triple::arm: 3821 // this->MCountName = "__mcount"; 3822 break; 3823 } 3824 } 3825 }; 3826 3827 // x86-32 RTEMS target 3828 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3829 public: 3830 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3831 SizeType = UnsignedLong; 3832 IntPtrType = SignedLong; 3833 PtrDiffType = SignedLong; 3834 this->UserLabelPrefix = ""; 3835 } 3836 void getTargetDefines(const LangOptions &Opts, 3837 MacroBuilder &Builder) const override { 3838 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3839 Builder.defineMacro("__INTEL__"); 3840 Builder.defineMacro("__rtems__"); 3841 } 3842 }; 3843 3844 // x86-64 generic target 3845 class X86_64TargetInfo : public X86TargetInfo { 3846 public: 3847 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3848 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3849 bool IsWinCOFF = 3850 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3851 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3852 LongDoubleWidth = 128; 3853 LongDoubleAlign = 128; 3854 LargeArrayMinWidth = 128; 3855 LargeArrayAlign = 128; 3856 SuitableAlign = 128; 3857 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3858 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3859 IntPtrType = IsX32 ? SignedInt : SignedLong; 3860 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3861 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3862 RegParmMax = 6; 3863 3864 // Pointers are 32-bit in x32. 3865 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3866 : IsWinCOFF 3867 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3868 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3869 3870 // Use fpret only for long double. 3871 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3872 3873 // Use fp2ret for _Complex long double. 3874 ComplexLongDoubleUsesFP2Ret = true; 3875 3876 // x86-64 has atomics up to 16 bytes. 3877 MaxAtomicPromoteWidth = 128; 3878 MaxAtomicInlineWidth = 128; 3879 } 3880 BuiltinVaListKind getBuiltinVaListKind() const override { 3881 return TargetInfo::X86_64ABIBuiltinVaList; 3882 } 3883 3884 int getEHDataRegisterNumber(unsigned RegNo) const override { 3885 if (RegNo == 0) return 0; 3886 if (RegNo == 1) return 1; 3887 return -1; 3888 } 3889 3890 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3891 return (CC == CC_C || 3892 CC == CC_X86VectorCall || 3893 CC == CC_IntelOclBicc || 3894 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3895 } 3896 3897 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3898 return CC_C; 3899 } 3900 3901 // for x32 we need it here explicitly 3902 bool hasInt128Type() const override { return true; } 3903 }; 3904 3905 // x86-64 Windows target 3906 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3907 public: 3908 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3909 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3910 WCharType = UnsignedShort; 3911 LongWidth = LongAlign = 32; 3912 DoubleAlign = LongLongAlign = 64; 3913 IntMaxType = SignedLongLong; 3914 Int64Type = SignedLongLong; 3915 SizeType = UnsignedLongLong; 3916 PtrDiffType = SignedLongLong; 3917 IntPtrType = SignedLongLong; 3918 this->UserLabelPrefix = ""; 3919 } 3920 3921 void getTargetDefines(const LangOptions &Opts, 3922 MacroBuilder &Builder) const override { 3923 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3924 Builder.defineMacro("_WIN64"); 3925 } 3926 3927 BuiltinVaListKind getBuiltinVaListKind() const override { 3928 return TargetInfo::CharPtrBuiltinVaList; 3929 } 3930 3931 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3932 switch (CC) { 3933 case CC_X86StdCall: 3934 case CC_X86ThisCall: 3935 case CC_X86FastCall: 3936 return CCCR_Ignore; 3937 case CC_C: 3938 case CC_X86VectorCall: 3939 case CC_IntelOclBicc: 3940 case CC_X86_64SysV: 3941 return CCCR_OK; 3942 default: 3943 return CCCR_Warning; 3944 } 3945 } 3946 }; 3947 3948 // x86-64 Windows Visual Studio target 3949 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3950 public: 3951 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3952 : WindowsX86_64TargetInfo(Triple) { 3953 LongDoubleWidth = LongDoubleAlign = 64; 3954 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3955 } 3956 void getTargetDefines(const LangOptions &Opts, 3957 MacroBuilder &Builder) const override { 3958 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3959 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3960 Builder.defineMacro("_M_X64"); 3961 Builder.defineMacro("_M_AMD64"); 3962 } 3963 }; 3964 3965 // x86-64 MinGW target 3966 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3967 public: 3968 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3969 : WindowsX86_64TargetInfo(Triple) {} 3970 void getTargetDefines(const LangOptions &Opts, 3971 MacroBuilder &Builder) const override { 3972 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3973 DefineStd(Builder, "WIN64", Opts); 3974 Builder.defineMacro("__MINGW64__"); 3975 addMinGWDefines(Opts, Builder); 3976 3977 // GCC defines this macro when it is using __gxx_personality_seh0. 3978 if (!Opts.SjLjExceptions) 3979 Builder.defineMacro("__SEH__"); 3980 } 3981 }; 3982 3983 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3984 public: 3985 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3986 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3987 Int64Type = SignedLongLong; 3988 MaxVectorAlign = 256; 3989 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3990 llvm::Triple T = llvm::Triple(Triple); 3991 if (T.isiOS()) 3992 UseSignedCharForObjCBool = false; 3993 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3994 } 3995 }; 3996 3997 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3998 public: 3999 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4000 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4001 IntMaxType = SignedLongLong; 4002 Int64Type = SignedLongLong; 4003 } 4004 }; 4005 4006 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4007 public: 4008 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4009 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4010 IntMaxType = SignedLongLong; 4011 Int64Type = SignedLongLong; 4012 } 4013 }; 4014 4015 class ARMTargetInfo : public TargetInfo { 4016 // Possible FPU choices. 4017 enum FPUMode { 4018 VFP2FPU = (1 << 0), 4019 VFP3FPU = (1 << 1), 4020 VFP4FPU = (1 << 2), 4021 NeonFPU = (1 << 3), 4022 FPARMV8 = (1 << 4) 4023 }; 4024 4025 // Possible HWDiv features. 4026 enum HWDivMode { 4027 HWDivThumb = (1 << 0), 4028 HWDivARM = (1 << 1) 4029 }; 4030 4031 static bool FPUModeIsVFP(FPUMode Mode) { 4032 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4033 } 4034 4035 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4036 static const char * const GCCRegNames[]; 4037 4038 std::string ABI, CPU; 4039 4040 enum { 4041 FP_Default, 4042 FP_VFP, 4043 FP_Neon 4044 } FPMath; 4045 4046 unsigned FPU : 5; 4047 4048 unsigned IsAAPCS : 1; 4049 unsigned IsThumb : 1; 4050 unsigned HWDiv : 2; 4051 4052 // Initialized via features. 4053 unsigned SoftFloat : 1; 4054 unsigned SoftFloatABI : 1; 4055 4056 unsigned CRC : 1; 4057 unsigned Crypto : 1; 4058 4059 // ACLE 6.5.1 Hardware floating point 4060 enum { 4061 HW_FP_HP = (1 << 1), /// half (16-bit) 4062 HW_FP_SP = (1 << 2), /// single (32-bit) 4063 HW_FP_DP = (1 << 3), /// double (64-bit) 4064 }; 4065 uint32_t HW_FP; 4066 4067 static const Builtin::Info BuiltinInfo[]; 4068 4069 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 4070 StringRef ArchName = T.getArchName(); 4071 if (T.getArch() == llvm::Triple::arm || 4072 T.getArch() == llvm::Triple::armeb) { 4073 StringRef VersionStr; 4074 if (ArchName.startswith("armv")) 4075 VersionStr = ArchName.substr(4, 1); 4076 else if (ArchName.startswith("armebv")) 4077 VersionStr = ArchName.substr(6, 1); 4078 else 4079 return false; 4080 unsigned Version; 4081 if (VersionStr.getAsInteger(10, Version)) 4082 return false; 4083 return Version >= 6; 4084 } 4085 assert(T.getArch() == llvm::Triple::thumb || 4086 T.getArch() == llvm::Triple::thumbeb); 4087 StringRef VersionStr; 4088 if (ArchName.startswith("thumbv")) 4089 VersionStr = ArchName.substr(6, 1); 4090 else if (ArchName.startswith("thumbebv")) 4091 VersionStr = ArchName.substr(8, 1); 4092 else 4093 return false; 4094 unsigned Version; 4095 if (VersionStr.getAsInteger(10, Version)) 4096 return false; 4097 return Version >= 7; 4098 } 4099 4100 void setABIAAPCS() { 4101 IsAAPCS = true; 4102 4103 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4104 const llvm::Triple &T = getTriple(); 4105 4106 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4107 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4108 T.getOS() == llvm::Triple::Bitrig) 4109 SizeType = UnsignedLong; 4110 else 4111 SizeType = UnsignedInt; 4112 4113 switch (T.getOS()) { 4114 case llvm::Triple::NetBSD: 4115 WCharType = SignedInt; 4116 break; 4117 case llvm::Triple::Win32: 4118 WCharType = UnsignedShort; 4119 break; 4120 case llvm::Triple::Linux: 4121 default: 4122 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4123 WCharType = UnsignedInt; 4124 break; 4125 } 4126 4127 UseBitFieldTypeAlignment = true; 4128 4129 ZeroLengthBitfieldBoundary = 0; 4130 4131 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4132 // so set preferred for small types to 32. 4133 if (T.isOSBinFormatMachO()) { 4134 DescriptionString = 4135 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4136 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4137 } else if (T.isOSWindows()) { 4138 assert(!BigEndian && "Windows on ARM does not support big endian"); 4139 DescriptionString = "e" 4140 "-m:w" 4141 "-p:32:32" 4142 "-i64:64" 4143 "-v128:64:128" 4144 "-a:0:32" 4145 "-n32" 4146 "-S64"; 4147 } else if (T.isOSNaCl()) { 4148 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4149 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4150 } else { 4151 DescriptionString = 4152 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4153 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4154 } 4155 4156 // FIXME: Enumerated types are variable width in straight AAPCS. 4157 } 4158 4159 void setABIAPCS() { 4160 const llvm::Triple &T = getTriple(); 4161 4162 IsAAPCS = false; 4163 4164 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4165 4166 // size_t is unsigned int on FreeBSD. 4167 if (T.getOS() == llvm::Triple::FreeBSD) 4168 SizeType = UnsignedInt; 4169 else 4170 SizeType = UnsignedLong; 4171 4172 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4173 WCharType = SignedInt; 4174 4175 // Do not respect the alignment of bit-field types when laying out 4176 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4177 UseBitFieldTypeAlignment = false; 4178 4179 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4180 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4181 /// gcc. 4182 ZeroLengthBitfieldBoundary = 32; 4183 4184 if (T.isOSBinFormatMachO()) 4185 DescriptionString = 4186 BigEndian 4187 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4188 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4189 else 4190 DescriptionString = 4191 BigEndian 4192 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4193 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4194 4195 // FIXME: Override "preferred align" for double and long long. 4196 } 4197 4198 public: 4199 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4200 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4201 IsAAPCS(true), HW_FP(0) { 4202 BigEndian = IsBigEndian; 4203 4204 switch (getTriple().getOS()) { 4205 case llvm::Triple::NetBSD: 4206 PtrDiffType = SignedLong; 4207 break; 4208 default: 4209 PtrDiffType = SignedInt; 4210 break; 4211 } 4212 4213 // {} in inline assembly are neon specifiers, not assembly variant 4214 // specifiers. 4215 NoAsmVariants = true; 4216 4217 // FIXME: Should we just treat this as a feature? 4218 IsThumb = getTriple().getArchName().startswith("thumb"); 4219 4220 // FIXME: This duplicates code from the driver that sets the -target-abi 4221 // option - this code is used if -target-abi isn't passed and should 4222 // be unified in some way. 4223 if (Triple.isOSBinFormatMachO()) { 4224 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4225 // the frontend matches that. 4226 if (Triple.getEnvironment() == llvm::Triple::EABI || 4227 Triple.getOS() == llvm::Triple::UnknownOS || 4228 StringRef(CPU).startswith("cortex-m")) { 4229 setABI("aapcs"); 4230 } else { 4231 setABI("apcs-gnu"); 4232 } 4233 } else if (Triple.isOSWindows()) { 4234 // FIXME: this is invalid for WindowsCE 4235 setABI("aapcs"); 4236 } else { 4237 // Select the default based on the platform. 4238 switch (Triple.getEnvironment()) { 4239 case llvm::Triple::Android: 4240 case llvm::Triple::GNUEABI: 4241 case llvm::Triple::GNUEABIHF: 4242 setABI("aapcs-linux"); 4243 break; 4244 case llvm::Triple::EABIHF: 4245 case llvm::Triple::EABI: 4246 setABI("aapcs"); 4247 break; 4248 case llvm::Triple::GNU: 4249 setABI("apcs-gnu"); 4250 break; 4251 default: 4252 if (Triple.getOS() == llvm::Triple::NetBSD) 4253 setABI("apcs-gnu"); 4254 else 4255 setABI("aapcs"); 4256 break; 4257 } 4258 } 4259 4260 // ARM targets default to using the ARM C++ ABI. 4261 TheCXXABI.set(TargetCXXABI::GenericARM); 4262 4263 // ARM has atomics up to 8 bytes 4264 MaxAtomicPromoteWidth = 64; 4265 if (shouldUseInlineAtomic(getTriple())) 4266 MaxAtomicInlineWidth = 64; 4267 4268 // Do force alignment of members that follow zero length bitfields. If 4269 // the alignment of the zero-length bitfield is greater than the member 4270 // that follows it, `bar', `bar' will be aligned as the type of the 4271 // zero length bitfield. 4272 UseZeroLengthBitfieldAlignment = true; 4273 } 4274 4275 StringRef getABI() const override { return ABI; } 4276 4277 bool setABI(const std::string &Name) override { 4278 ABI = Name; 4279 4280 // The defaults (above) are for AAPCS, check if we need to change them. 4281 // 4282 // FIXME: We need support for -meabi... we could just mangle it into the 4283 // name. 4284 if (Name == "apcs-gnu") { 4285 setABIAPCS(); 4286 return true; 4287 } 4288 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4289 setABIAAPCS(); 4290 return true; 4291 } 4292 return false; 4293 } 4294 4295 // FIXME: This should be based on Arch attributes, not CPU names. 4296 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4297 StringRef ArchName = getTriple().getArchName(); 4298 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName); 4299 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A || 4300 ArchKind == llvm::ARM::AK_ARMV8_1A); 4301 4302 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4303 Features["vfp2"] = true; 4304 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4305 Features["vfp3"] = true; 4306 Features["neon"] = true; 4307 } 4308 else if (CPU == "cortex-a5") { 4309 Features["vfp4"] = true; 4310 Features["neon"] = true; 4311 } else if (CPU == "swift" || CPU == "cortex-a7" || 4312 CPU == "cortex-a12" || CPU == "cortex-a15" || 4313 CPU == "cortex-a17" || CPU == "krait") { 4314 Features["vfp4"] = true; 4315 Features["neon"] = true; 4316 Features["hwdiv"] = true; 4317 Features["hwdiv-arm"] = true; 4318 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4319 CPU == "cortex-a72") { 4320 Features["fp-armv8"] = true; 4321 Features["neon"] = true; 4322 Features["hwdiv"] = true; 4323 Features["hwdiv-arm"] = true; 4324 Features["crc"] = true; 4325 Features["crypto"] = true; 4326 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) { 4327 Features["hwdiv"] = true; 4328 Features["hwdiv-arm"] = true; 4329 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4330 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4331 Features["hwdiv"] = true; 4332 } 4333 } 4334 4335 bool handleTargetFeatures(std::vector<std::string> &Features, 4336 DiagnosticsEngine &Diags) override { 4337 FPU = 0; 4338 CRC = 0; 4339 Crypto = 0; 4340 SoftFloat = SoftFloatABI = false; 4341 HWDiv = 0; 4342 4343 // This does not diagnose illegal cases like having both 4344 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4345 uint32_t HW_FP_remove = 0; 4346 for (const auto &Feature : Features) { 4347 if (Feature == "+soft-float") { 4348 SoftFloat = true; 4349 } else if (Feature == "+soft-float-abi") { 4350 SoftFloatABI = true; 4351 } else if (Feature == "+vfp2") { 4352 FPU |= VFP2FPU; 4353 HW_FP |= HW_FP_SP | HW_FP_DP; 4354 } else if (Feature == "+vfp3") { 4355 FPU |= VFP3FPU; 4356 HW_FP |= HW_FP_SP | HW_FP_DP; 4357 } else if (Feature == "+vfp4") { 4358 FPU |= VFP4FPU; 4359 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4360 } else if (Feature == "+fp-armv8") { 4361 FPU |= FPARMV8; 4362 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4363 } else if (Feature == "+neon") { 4364 FPU |= NeonFPU; 4365 HW_FP |= HW_FP_SP | HW_FP_DP; 4366 } else if (Feature == "+hwdiv") { 4367 HWDiv |= HWDivThumb; 4368 } else if (Feature == "+hwdiv-arm") { 4369 HWDiv |= HWDivARM; 4370 } else if (Feature == "+crc") { 4371 CRC = 1; 4372 } else if (Feature == "+crypto") { 4373 Crypto = 1; 4374 } else if (Feature == "+fp-only-sp") { 4375 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4376 } 4377 } 4378 HW_FP &= ~HW_FP_remove; 4379 4380 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4381 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4382 return false; 4383 } 4384 4385 if (FPMath == FP_Neon) 4386 Features.push_back("+neonfp"); 4387 else if (FPMath == FP_VFP) 4388 Features.push_back("-neonfp"); 4389 4390 // Remove front-end specific options which the backend handles differently. 4391 auto Feature = 4392 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4393 if (Feature != Features.end()) 4394 Features.erase(Feature); 4395 4396 return true; 4397 } 4398 4399 bool hasFeature(StringRef Feature) const override { 4400 return llvm::StringSwitch<bool>(Feature) 4401 .Case("arm", true) 4402 .Case("softfloat", SoftFloat) 4403 .Case("thumb", IsThumb) 4404 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4405 .Case("hwdiv", HWDiv & HWDivThumb) 4406 .Case("hwdiv-arm", HWDiv & HWDivARM) 4407 .Default(false); 4408 } 4409 const char *getCPUDefineSuffix(StringRef Name) const { 4410 if(Name == "generic") { 4411 auto subarch = getTriple().getSubArch(); 4412 switch (subarch) { 4413 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4414 return "8_1A"; 4415 default: 4416 break; 4417 } 4418 } 4419 4420 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4421 if (ArchKind == llvm::ARM::AK_INVALID) 4422 return ""; 4423 4424 // For most sub-arches, the build attribute CPU name is enough. 4425 // For Cortex variants, it's slightly different. 4426 switch(ArchKind) { 4427 default: 4428 return llvm::ARMTargetParser::getCPUAttr(ArchKind); 4429 case llvm::ARM::AK_ARMV6M: 4430 case llvm::ARM::AK_ARMV6SM: 4431 return "6M"; 4432 case llvm::ARM::AK_ARMV7: 4433 case llvm::ARM::AK_ARMV7A: 4434 case llvm::ARM::AK_ARMV7S: 4435 return "7A"; 4436 case llvm::ARM::AK_ARMV7R: 4437 return "7R"; 4438 case llvm::ARM::AK_ARMV7M: 4439 return "7M"; 4440 case llvm::ARM::AK_ARMV7EM: 4441 return "7EM"; 4442 case llvm::ARM::AK_ARMV8A: 4443 return "8A"; 4444 case llvm::ARM::AK_ARMV8_1A: 4445 return "8_1A"; 4446 } 4447 } 4448 const char *getCPUProfile(StringRef Name) const { 4449 if(Name == "generic") { 4450 auto subarch = getTriple().getSubArch(); 4451 switch (subarch) { 4452 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4453 return "A"; 4454 default: 4455 break; 4456 } 4457 } 4458 4459 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name); 4460 if (CPUArch == llvm::ARM::AK_INVALID) 4461 return ""; 4462 4463 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch); 4464 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) { 4465 case llvm::ARM::PK_A: 4466 return "A"; 4467 case llvm::ARM::PK_R: 4468 return "R"; 4469 case llvm::ARM::PK_M: 4470 return "M"; 4471 default: 4472 return ""; 4473 } 4474 } 4475 bool setCPU(const std::string &Name) override { 4476 if (!getCPUDefineSuffix(Name)) 4477 return false; 4478 4479 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4480 StringRef Profile = getCPUProfile(Name); 4481 if (Profile == "M" && MaxAtomicInlineWidth) { 4482 MaxAtomicPromoteWidth = 32; 4483 MaxAtomicInlineWidth = 32; 4484 } 4485 4486 CPU = Name; 4487 return true; 4488 } 4489 bool setFPMath(StringRef Name) override; 4490 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4491 unsigned CPUArchVer) const { 4492 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4493 (CPUArch.find('M') != StringRef::npos); 4494 } 4495 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4496 unsigned CPUArchVer) const { 4497 // We check both CPUArchVer and ArchName because when only triple is 4498 // specified, the default CPU is arm1136j-s. 4499 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4500 ArchName.endswith("v8.1a") || 4501 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4502 } 4503 void getTargetDefines(const LangOptions &Opts, 4504 MacroBuilder &Builder) const override { 4505 // Target identification. 4506 Builder.defineMacro("__arm"); 4507 Builder.defineMacro("__arm__"); 4508 4509 // Target properties. 4510 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4511 4512 StringRef CPUArch = getCPUDefineSuffix(CPU); 4513 unsigned int CPUArchVer; 4514 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4515 llvm_unreachable("Invalid char for architecture version number"); 4516 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4517 4518 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4519 StringRef CPUProfile = getCPUProfile(CPU); 4520 StringRef ArchName = getTriple().getArchName(); 4521 4522 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4523 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4524 if (CPUArch[0] >= '8') { 4525 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4526 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4527 } 4528 4529 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4530 // is not defined for the M-profile. 4531 // NOTE that the deffault profile is assumed to be 'A' 4532 if (CPUProfile.empty() || CPUProfile != "M") 4533 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4534 4535 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4536 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4537 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4538 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4539 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4540 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4541 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4542 4543 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4544 // instruction set such as ARM or Thumb. 4545 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4546 4547 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4548 4549 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4550 if (!CPUProfile.empty()) 4551 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4552 4553 // ACLE 6.5.1 Hardware Floating Point 4554 if (HW_FP) 4555 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4556 4557 // ACLE predefines. 4558 Builder.defineMacro("__ARM_ACLE", "200"); 4559 4560 // Subtarget options. 4561 4562 // FIXME: It's more complicated than this and we don't really support 4563 // interworking. 4564 // Windows on ARM does not "support" interworking 4565 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4566 Builder.defineMacro("__THUMB_INTERWORK__"); 4567 4568 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4569 // Embedded targets on Darwin follow AAPCS, but not EABI. 4570 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4571 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4572 Builder.defineMacro("__ARM_EABI__"); 4573 Builder.defineMacro("__ARM_PCS", "1"); 4574 4575 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4576 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4577 } 4578 4579 if (SoftFloat) 4580 Builder.defineMacro("__SOFTFP__"); 4581 4582 if (CPU == "xscale") 4583 Builder.defineMacro("__XSCALE__"); 4584 4585 if (IsThumb) { 4586 Builder.defineMacro("__THUMBEL__"); 4587 Builder.defineMacro("__thumb__"); 4588 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4589 Builder.defineMacro("__thumb2__"); 4590 } 4591 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4592 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4593 4594 // Note, this is always on in gcc, even though it doesn't make sense. 4595 Builder.defineMacro("__APCS_32__"); 4596 4597 if (FPUModeIsVFP((FPUMode) FPU)) { 4598 Builder.defineMacro("__VFP_FP__"); 4599 if (FPU & VFP2FPU) 4600 Builder.defineMacro("__ARM_VFPV2__"); 4601 if (FPU & VFP3FPU) 4602 Builder.defineMacro("__ARM_VFPV3__"); 4603 if (FPU & VFP4FPU) 4604 Builder.defineMacro("__ARM_VFPV4__"); 4605 } 4606 4607 // This only gets set when Neon instructions are actually available, unlike 4608 // the VFP define, hence the soft float and arch check. This is subtly 4609 // different from gcc, we follow the intent which was that it should be set 4610 // when Neon instructions are actually available. 4611 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4612 Builder.defineMacro("__ARM_NEON"); 4613 Builder.defineMacro("__ARM_NEON__"); 4614 } 4615 4616 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4617 Opts.ShortWChar ? "2" : "4"); 4618 4619 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4620 Opts.ShortEnums ? "1" : "4"); 4621 4622 if (CRC) 4623 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4624 4625 if (Crypto) 4626 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4627 4628 if (CPUArchVer >= 6 && CPUArch != "6M") { 4629 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4630 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4631 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4632 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4633 } 4634 4635 bool is5EOrAbove = (CPUArchVer >= 6 || 4636 (CPUArchVer == 5 && 4637 CPUArch.find('E') != StringRef::npos)); 4638 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4639 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4640 Builder.defineMacro("__ARM_FEATURE_DSP"); 4641 } 4642 void getTargetBuiltins(const Builtin::Info *&Records, 4643 unsigned &NumRecords) const override { 4644 Records = BuiltinInfo; 4645 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4646 } 4647 bool isCLZForZeroUndef() const override { return false; } 4648 BuiltinVaListKind getBuiltinVaListKind() const override { 4649 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4650 } 4651 void getGCCRegNames(const char * const *&Names, 4652 unsigned &NumNames) const override; 4653 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4654 unsigned &NumAliases) const override; 4655 bool validateAsmConstraint(const char *&Name, 4656 TargetInfo::ConstraintInfo &Info) const override { 4657 switch (*Name) { 4658 default: break; 4659 case 'l': // r0-r7 4660 case 'h': // r8-r15 4661 case 'w': // VFP Floating point register single precision 4662 case 'P': // VFP Floating point register double precision 4663 Info.setAllowsRegister(); 4664 return true; 4665 case 'I': 4666 case 'J': 4667 case 'K': 4668 case 'L': 4669 case 'M': 4670 // FIXME 4671 return true; 4672 case 'Q': // A memory address that is a single base register. 4673 Info.setAllowsMemory(); 4674 return true; 4675 case 'U': // a memory reference... 4676 switch (Name[1]) { 4677 case 'q': // ...ARMV4 ldrsb 4678 case 'v': // ...VFP load/store (reg+constant offset) 4679 case 'y': // ...iWMMXt load/store 4680 case 't': // address valid for load/store opaque types wider 4681 // than 128-bits 4682 case 'n': // valid address for Neon doubleword vector load/store 4683 case 'm': // valid address for Neon element and structure load/store 4684 case 's': // valid address for non-offset loads/stores of quad-word 4685 // values in four ARM registers 4686 Info.setAllowsMemory(); 4687 Name++; 4688 return true; 4689 } 4690 } 4691 return false; 4692 } 4693 std::string convertConstraint(const char *&Constraint) const override { 4694 std::string R; 4695 switch (*Constraint) { 4696 case 'U': // Two-character constraint; add "^" hint for later parsing. 4697 R = std::string("^") + std::string(Constraint, 2); 4698 Constraint++; 4699 break; 4700 case 'p': // 'p' should be translated to 'r' by default. 4701 R = std::string("r"); 4702 break; 4703 default: 4704 return std::string(1, *Constraint); 4705 } 4706 return R; 4707 } 4708 bool 4709 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4710 std::string &SuggestedModifier) const override { 4711 bool isOutput = (Constraint[0] == '='); 4712 bool isInOut = (Constraint[0] == '+'); 4713 4714 // Strip off constraint modifiers. 4715 while (Constraint[0] == '=' || 4716 Constraint[0] == '+' || 4717 Constraint[0] == '&') 4718 Constraint = Constraint.substr(1); 4719 4720 switch (Constraint[0]) { 4721 default: break; 4722 case 'r': { 4723 switch (Modifier) { 4724 default: 4725 return (isInOut || isOutput || Size <= 64); 4726 case 'q': 4727 // A register of size 32 cannot fit a vector type. 4728 return false; 4729 } 4730 } 4731 } 4732 4733 return true; 4734 } 4735 const char *getClobbers() const override { 4736 // FIXME: Is this really right? 4737 return ""; 4738 } 4739 4740 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4741 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4742 } 4743 4744 int getEHDataRegisterNumber(unsigned RegNo) const override { 4745 if (RegNo == 0) return 0; 4746 if (RegNo == 1) return 1; 4747 return -1; 4748 } 4749 }; 4750 4751 bool ARMTargetInfo::setFPMath(StringRef Name) { 4752 if (Name == "neon") { 4753 FPMath = FP_Neon; 4754 return true; 4755 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4756 Name == "vfp4") { 4757 FPMath = FP_VFP; 4758 return true; 4759 } 4760 return false; 4761 } 4762 4763 const char * const ARMTargetInfo::GCCRegNames[] = { 4764 // Integer registers 4765 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4766 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4767 4768 // Float registers 4769 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4770 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4771 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4772 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4773 4774 // Double registers 4775 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4776 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4777 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4778 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4779 4780 // Quad registers 4781 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4782 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4783 }; 4784 4785 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4786 unsigned &NumNames) const { 4787 Names = GCCRegNames; 4788 NumNames = llvm::array_lengthof(GCCRegNames); 4789 } 4790 4791 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4792 { { "a1" }, "r0" }, 4793 { { "a2" }, "r1" }, 4794 { { "a3" }, "r2" }, 4795 { { "a4" }, "r3" }, 4796 { { "v1" }, "r4" }, 4797 { { "v2" }, "r5" }, 4798 { { "v3" }, "r6" }, 4799 { { "v4" }, "r7" }, 4800 { { "v5" }, "r8" }, 4801 { { "v6", "rfp" }, "r9" }, 4802 { { "sl" }, "r10" }, 4803 { { "fp" }, "r11" }, 4804 { { "ip" }, "r12" }, 4805 { { "r13" }, "sp" }, 4806 { { "r14" }, "lr" }, 4807 { { "r15" }, "pc" }, 4808 // The S, D and Q registers overlap, but aren't really aliases; we 4809 // don't want to substitute one of these for a different-sized one. 4810 }; 4811 4812 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4813 unsigned &NumAliases) const { 4814 Aliases = GCCRegAliases; 4815 NumAliases = llvm::array_lengthof(GCCRegAliases); 4816 } 4817 4818 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4819 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4820 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4821 ALL_LANGUAGES }, 4822 #include "clang/Basic/BuiltinsNEON.def" 4823 4824 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4825 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4826 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4827 ALL_LANGUAGES }, 4828 #include "clang/Basic/BuiltinsARM.def" 4829 }; 4830 4831 class ARMleTargetInfo : public ARMTargetInfo { 4832 public: 4833 ARMleTargetInfo(const llvm::Triple &Triple) 4834 : ARMTargetInfo(Triple, false) { } 4835 void getTargetDefines(const LangOptions &Opts, 4836 MacroBuilder &Builder) const override { 4837 Builder.defineMacro("__ARMEL__"); 4838 ARMTargetInfo::getTargetDefines(Opts, Builder); 4839 } 4840 }; 4841 4842 class ARMbeTargetInfo : public ARMTargetInfo { 4843 public: 4844 ARMbeTargetInfo(const llvm::Triple &Triple) 4845 : ARMTargetInfo(Triple, true) { } 4846 void getTargetDefines(const LangOptions &Opts, 4847 MacroBuilder &Builder) const override { 4848 Builder.defineMacro("__ARMEB__"); 4849 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4850 ARMTargetInfo::getTargetDefines(Opts, Builder); 4851 } 4852 }; 4853 4854 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4855 const llvm::Triple Triple; 4856 public: 4857 WindowsARMTargetInfo(const llvm::Triple &Triple) 4858 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4859 TLSSupported = false; 4860 WCharType = UnsignedShort; 4861 SizeType = UnsignedInt; 4862 UserLabelPrefix = ""; 4863 } 4864 void getVisualStudioDefines(const LangOptions &Opts, 4865 MacroBuilder &Builder) const { 4866 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4867 4868 // FIXME: this is invalid for WindowsCE 4869 Builder.defineMacro("_M_ARM_NT", "1"); 4870 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4871 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4872 4873 assert((Triple.getArch() == llvm::Triple::arm || 4874 Triple.getArch() == llvm::Triple::thumb) && 4875 "invalid architecture for Windows ARM target info"); 4876 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4877 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4878 4879 // TODO map the complete set of values 4880 // 31: VFPv3 40: VFPv4 4881 Builder.defineMacro("_M_ARM_FP", "31"); 4882 } 4883 BuiltinVaListKind getBuiltinVaListKind() const override { 4884 return TargetInfo::CharPtrBuiltinVaList; 4885 } 4886 }; 4887 4888 // Windows ARM + Itanium C++ ABI Target 4889 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4890 public: 4891 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4892 : WindowsARMTargetInfo(Triple) { 4893 TheCXXABI.set(TargetCXXABI::GenericARM); 4894 } 4895 4896 void getTargetDefines(const LangOptions &Opts, 4897 MacroBuilder &Builder) const override { 4898 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4899 4900 if (Opts.MSVCCompat) 4901 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4902 } 4903 }; 4904 4905 // Windows ARM, MS (C++) ABI 4906 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4907 public: 4908 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4909 : WindowsARMTargetInfo(Triple) { 4910 TheCXXABI.set(TargetCXXABI::Microsoft); 4911 } 4912 4913 void getTargetDefines(const LangOptions &Opts, 4914 MacroBuilder &Builder) const override { 4915 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4916 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4917 } 4918 }; 4919 4920 class DarwinARMTargetInfo : 4921 public DarwinTargetInfo<ARMleTargetInfo> { 4922 protected: 4923 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4924 MacroBuilder &Builder) const override { 4925 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4926 } 4927 4928 public: 4929 DarwinARMTargetInfo(const llvm::Triple &Triple) 4930 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4931 HasAlignMac68kSupport = true; 4932 // iOS always has 64-bit atomic instructions. 4933 // FIXME: This should be based off of the target features in 4934 // ARMleTargetInfo. 4935 MaxAtomicInlineWidth = 64; 4936 4937 // Darwin on iOS uses a variant of the ARM C++ ABI. 4938 TheCXXABI.set(TargetCXXABI::iOS); 4939 } 4940 }; 4941 4942 class AArch64TargetInfo : public TargetInfo { 4943 virtual void setDescriptionString() = 0; 4944 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4945 static const char *const GCCRegNames[]; 4946 4947 enum FPUModeEnum { 4948 FPUMode, 4949 NeonMode 4950 }; 4951 4952 unsigned FPU; 4953 unsigned CRC; 4954 unsigned Crypto; 4955 4956 static const Builtin::Info BuiltinInfo[]; 4957 4958 std::string ABI; 4959 4960 public: 4961 AArch64TargetInfo(const llvm::Triple &Triple) 4962 : TargetInfo(Triple), ABI("aapcs") { 4963 4964 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4965 WCharType = SignedInt; 4966 4967 // NetBSD apparently prefers consistency across ARM targets to consistency 4968 // across 64-bit targets. 4969 Int64Type = SignedLongLong; 4970 IntMaxType = SignedLongLong; 4971 } else { 4972 WCharType = UnsignedInt; 4973 Int64Type = SignedLong; 4974 IntMaxType = SignedLong; 4975 } 4976 4977 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4978 MaxVectorAlign = 128; 4979 RegParmMax = 8; 4980 MaxAtomicInlineWidth = 128; 4981 MaxAtomicPromoteWidth = 128; 4982 4983 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4984 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4985 4986 // {} in inline assembly are neon specifiers, not assembly variant 4987 // specifiers. 4988 NoAsmVariants = true; 4989 4990 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4991 // contributes to the alignment of the containing aggregate in the same way 4992 // a plain (non bit-field) member of that type would, without exception for 4993 // zero-sized or anonymous bit-fields." 4994 UseBitFieldTypeAlignment = true; 4995 UseZeroLengthBitfieldAlignment = true; 4996 4997 // AArch64 targets default to using the ARM C++ ABI. 4998 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4999 } 5000 5001 StringRef getABI() const override { return ABI; } 5002 bool setABI(const std::string &Name) override { 5003 if (Name != "aapcs" && Name != "darwinpcs") 5004 return false; 5005 5006 ABI = Name; 5007 return true; 5008 } 5009 5010 bool setCPU(const std::string &Name) override { 5011 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5012 .Case("generic", true) 5013 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5014 .Case("cyclone", true) 5015 .Default(false); 5016 return CPUKnown; 5017 } 5018 5019 void getTargetDefines(const LangOptions &Opts, 5020 MacroBuilder &Builder) const override { 5021 // Target identification. 5022 Builder.defineMacro("__aarch64__"); 5023 5024 // Target properties. 5025 Builder.defineMacro("_LP64"); 5026 Builder.defineMacro("__LP64__"); 5027 5028 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5029 Builder.defineMacro("__ARM_ACLE", "200"); 5030 Builder.defineMacro("__ARM_ARCH", "8"); 5031 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5032 5033 Builder.defineMacro("__ARM_64BIT_STATE"); 5034 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5035 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5036 5037 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5038 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5039 Builder.defineMacro("__ARM_FEATURE_FMA"); 5040 Builder.defineMacro("__ARM_FEATURE_DIV"); 5041 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5042 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5043 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5044 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5045 5046 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5047 5048 // 0xe implies support for half, single and double precision operations. 5049 Builder.defineMacro("__ARM_FP", "0xe"); 5050 5051 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5052 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5053 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5054 5055 if (Opts.FastMath || Opts.FiniteMathOnly) 5056 Builder.defineMacro("__ARM_FP_FAST"); 5057 5058 if (Opts.C99 && !Opts.Freestanding) 5059 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5060 5061 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5062 5063 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5064 Opts.ShortEnums ? "1" : "4"); 5065 5066 if (FPU == NeonMode) { 5067 Builder.defineMacro("__ARM_NEON"); 5068 // 64-bit NEON supports half, single and double precision operations. 5069 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5070 } 5071 5072 if (CRC) 5073 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5074 5075 if (Crypto) 5076 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5077 5078 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5079 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5081 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5082 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5083 } 5084 5085 void getTargetBuiltins(const Builtin::Info *&Records, 5086 unsigned &NumRecords) const override { 5087 Records = BuiltinInfo; 5088 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5089 } 5090 5091 bool hasFeature(StringRef Feature) const override { 5092 return Feature == "aarch64" || 5093 Feature == "arm64" || 5094 (Feature == "neon" && FPU == NeonMode); 5095 } 5096 5097 bool handleTargetFeatures(std::vector<std::string> &Features, 5098 DiagnosticsEngine &Diags) override { 5099 FPU = FPUMode; 5100 CRC = 0; 5101 Crypto = 0; 5102 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5103 if (Features[i] == "+neon") 5104 FPU = NeonMode; 5105 if (Features[i] == "+crc") 5106 CRC = 1; 5107 if (Features[i] == "+crypto") 5108 Crypto = 1; 5109 } 5110 5111 setDescriptionString(); 5112 5113 return true; 5114 } 5115 5116 bool isCLZForZeroUndef() const override { return false; } 5117 5118 BuiltinVaListKind getBuiltinVaListKind() const override { 5119 return TargetInfo::AArch64ABIBuiltinVaList; 5120 } 5121 5122 void getGCCRegNames(const char *const *&Names, 5123 unsigned &NumNames) const override; 5124 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5125 unsigned &NumAliases) const override; 5126 5127 bool validateAsmConstraint(const char *&Name, 5128 TargetInfo::ConstraintInfo &Info) const override { 5129 switch (*Name) { 5130 default: 5131 return false; 5132 case 'w': // Floating point and SIMD registers (V0-V31) 5133 Info.setAllowsRegister(); 5134 return true; 5135 case 'I': // Constant that can be used with an ADD instruction 5136 case 'J': // Constant that can be used with a SUB instruction 5137 case 'K': // Constant that can be used with a 32-bit logical instruction 5138 case 'L': // Constant that can be used with a 64-bit logical instruction 5139 case 'M': // Constant that can be used as a 32-bit MOV immediate 5140 case 'N': // Constant that can be used as a 64-bit MOV immediate 5141 case 'Y': // Floating point constant zero 5142 case 'Z': // Integer constant zero 5143 return true; 5144 case 'Q': // A memory reference with base register and no offset 5145 Info.setAllowsMemory(); 5146 return true; 5147 case 'S': // A symbolic address 5148 Info.setAllowsRegister(); 5149 return true; 5150 case 'U': 5151 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5152 // Utf: A memory address suitable for ldp/stp in TF mode. 5153 // Usa: An absolute symbolic address. 5154 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5155 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5156 case 'z': // Zero register, wzr or xzr 5157 Info.setAllowsRegister(); 5158 return true; 5159 case 'x': // Floating point and SIMD registers (V0-V15) 5160 Info.setAllowsRegister(); 5161 return true; 5162 } 5163 return false; 5164 } 5165 5166 bool 5167 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5168 std::string &SuggestedModifier) const override { 5169 // Strip off constraint modifiers. 5170 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5171 Constraint = Constraint.substr(1); 5172 5173 switch (Constraint[0]) { 5174 default: 5175 return true; 5176 case 'z': 5177 case 'r': { 5178 switch (Modifier) { 5179 case 'x': 5180 case 'w': 5181 // For now assume that the person knows what they're 5182 // doing with the modifier. 5183 return true; 5184 default: 5185 // By default an 'r' constraint will be in the 'x' 5186 // registers. 5187 if (Size == 64) 5188 return true; 5189 5190 SuggestedModifier = "w"; 5191 return false; 5192 } 5193 } 5194 } 5195 } 5196 5197 const char *getClobbers() const override { return ""; } 5198 5199 int getEHDataRegisterNumber(unsigned RegNo) const override { 5200 if (RegNo == 0) 5201 return 0; 5202 if (RegNo == 1) 5203 return 1; 5204 return -1; 5205 } 5206 }; 5207 5208 const char *const AArch64TargetInfo::GCCRegNames[] = { 5209 // 32-bit Integer registers 5210 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5211 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5212 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5213 5214 // 64-bit Integer registers 5215 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5216 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5217 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5218 5219 // 32-bit floating point regsisters 5220 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5221 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5222 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5223 5224 // 64-bit floating point regsisters 5225 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5226 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5227 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5228 5229 // Vector registers 5230 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5231 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5232 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5233 }; 5234 5235 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5236 unsigned &NumNames) const { 5237 Names = GCCRegNames; 5238 NumNames = llvm::array_lengthof(GCCRegNames); 5239 } 5240 5241 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5242 { { "w31" }, "wsp" }, 5243 { { "x29" }, "fp" }, 5244 { { "x30" }, "lr" }, 5245 { { "x31" }, "sp" }, 5246 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5247 // don't want to substitute one of these for a different-sized one. 5248 }; 5249 5250 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5251 unsigned &NumAliases) const { 5252 Aliases = GCCRegAliases; 5253 NumAliases = llvm::array_lengthof(GCCRegAliases); 5254 } 5255 5256 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5257 #define BUILTIN(ID, TYPE, ATTRS) \ 5258 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5259 #include "clang/Basic/BuiltinsNEON.def" 5260 5261 #define BUILTIN(ID, TYPE, ATTRS) \ 5262 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5263 #include "clang/Basic/BuiltinsAArch64.def" 5264 }; 5265 5266 class AArch64leTargetInfo : public AArch64TargetInfo { 5267 void setDescriptionString() override { 5268 if (getTriple().isOSBinFormatMachO()) 5269 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5270 else 5271 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5272 } 5273 5274 public: 5275 AArch64leTargetInfo(const llvm::Triple &Triple) 5276 : AArch64TargetInfo(Triple) { 5277 BigEndian = false; 5278 } 5279 void getTargetDefines(const LangOptions &Opts, 5280 MacroBuilder &Builder) const override { 5281 Builder.defineMacro("__AARCH64EL__"); 5282 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5283 } 5284 }; 5285 5286 class AArch64beTargetInfo : public AArch64TargetInfo { 5287 void setDescriptionString() override { 5288 assert(!getTriple().isOSBinFormatMachO()); 5289 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5290 } 5291 5292 public: 5293 AArch64beTargetInfo(const llvm::Triple &Triple) 5294 : AArch64TargetInfo(Triple) { } 5295 void getTargetDefines(const LangOptions &Opts, 5296 MacroBuilder &Builder) const override { 5297 Builder.defineMacro("__AARCH64EB__"); 5298 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5299 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5300 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5301 } 5302 }; 5303 5304 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5305 protected: 5306 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5307 MacroBuilder &Builder) const override { 5308 Builder.defineMacro("__AARCH64_SIMD__"); 5309 Builder.defineMacro("__ARM64_ARCH_8__"); 5310 Builder.defineMacro("__ARM_NEON__"); 5311 Builder.defineMacro("__LITTLE_ENDIAN__"); 5312 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5313 Builder.defineMacro("__arm64", "1"); 5314 Builder.defineMacro("__arm64__", "1"); 5315 5316 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5317 } 5318 5319 public: 5320 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5321 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5322 Int64Type = SignedLongLong; 5323 WCharType = SignedInt; 5324 UseSignedCharForObjCBool = false; 5325 5326 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5327 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5328 5329 TheCXXABI.set(TargetCXXABI::iOS64); 5330 } 5331 5332 BuiltinVaListKind getBuiltinVaListKind() const override { 5333 return TargetInfo::CharPtrBuiltinVaList; 5334 } 5335 }; 5336 5337 // Hexagon abstract base class 5338 class HexagonTargetInfo : public TargetInfo { 5339 static const Builtin::Info BuiltinInfo[]; 5340 static const char * const GCCRegNames[]; 5341 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5342 std::string CPU; 5343 public: 5344 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5345 BigEndian = false; 5346 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5347 5348 // {} in inline assembly are packet specifiers, not assembly variant 5349 // specifiers. 5350 NoAsmVariants = true; 5351 } 5352 5353 void getTargetBuiltins(const Builtin::Info *&Records, 5354 unsigned &NumRecords) const override { 5355 Records = BuiltinInfo; 5356 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5357 } 5358 5359 bool validateAsmConstraint(const char *&Name, 5360 TargetInfo::ConstraintInfo &Info) const override { 5361 return true; 5362 } 5363 5364 void getTargetDefines(const LangOptions &Opts, 5365 MacroBuilder &Builder) const override; 5366 5367 bool hasFeature(StringRef Feature) const override { 5368 return Feature == "hexagon"; 5369 } 5370 5371 BuiltinVaListKind getBuiltinVaListKind() const override { 5372 return TargetInfo::CharPtrBuiltinVaList; 5373 } 5374 void getGCCRegNames(const char * const *&Names, 5375 unsigned &NumNames) const override; 5376 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5377 unsigned &NumAliases) const override; 5378 const char *getClobbers() const override { 5379 return ""; 5380 } 5381 5382 static const char *getHexagonCPUSuffix(StringRef Name) { 5383 return llvm::StringSwitch<const char*>(Name) 5384 .Case("hexagonv4", "4") 5385 .Case("hexagonv5", "5") 5386 .Default(nullptr); 5387 } 5388 5389 bool setCPU(const std::string &Name) override { 5390 if (!getHexagonCPUSuffix(Name)) 5391 return false; 5392 5393 CPU = Name; 5394 return true; 5395 } 5396 }; 5397 5398 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5399 MacroBuilder &Builder) const { 5400 Builder.defineMacro("qdsp6"); 5401 Builder.defineMacro("__qdsp6", "1"); 5402 Builder.defineMacro("__qdsp6__", "1"); 5403 5404 Builder.defineMacro("hexagon"); 5405 Builder.defineMacro("__hexagon", "1"); 5406 Builder.defineMacro("__hexagon__", "1"); 5407 5408 if(CPU == "hexagonv1") { 5409 Builder.defineMacro("__HEXAGON_V1__"); 5410 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5411 if(Opts.HexagonQdsp6Compat) { 5412 Builder.defineMacro("__QDSP6_V1__"); 5413 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5414 } 5415 } 5416 else if(CPU == "hexagonv2") { 5417 Builder.defineMacro("__HEXAGON_V2__"); 5418 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5419 if(Opts.HexagonQdsp6Compat) { 5420 Builder.defineMacro("__QDSP6_V2__"); 5421 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5422 } 5423 } 5424 else if(CPU == "hexagonv3") { 5425 Builder.defineMacro("__HEXAGON_V3__"); 5426 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5427 if(Opts.HexagonQdsp6Compat) { 5428 Builder.defineMacro("__QDSP6_V3__"); 5429 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5430 } 5431 } 5432 else if(CPU == "hexagonv4") { 5433 Builder.defineMacro("__HEXAGON_V4__"); 5434 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5435 if(Opts.HexagonQdsp6Compat) { 5436 Builder.defineMacro("__QDSP6_V4__"); 5437 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5438 } 5439 } 5440 else if(CPU == "hexagonv5") { 5441 Builder.defineMacro("__HEXAGON_V5__"); 5442 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5443 if(Opts.HexagonQdsp6Compat) { 5444 Builder.defineMacro("__QDSP6_V5__"); 5445 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5446 } 5447 } 5448 } 5449 5450 const char * const HexagonTargetInfo::GCCRegNames[] = { 5451 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5452 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5453 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5454 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5455 "p0", "p1", "p2", "p3", 5456 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5457 }; 5458 5459 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5460 unsigned &NumNames) const { 5461 Names = GCCRegNames; 5462 NumNames = llvm::array_lengthof(GCCRegNames); 5463 } 5464 5465 5466 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5467 { { "sp" }, "r29" }, 5468 { { "fp" }, "r30" }, 5469 { { "lr" }, "r31" }, 5470 }; 5471 5472 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5473 unsigned &NumAliases) const { 5474 Aliases = GCCRegAliases; 5475 NumAliases = llvm::array_lengthof(GCCRegAliases); 5476 } 5477 5478 5479 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5480 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5481 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5482 ALL_LANGUAGES }, 5483 #include "clang/Basic/BuiltinsHexagon.def" 5484 }; 5485 5486 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5487 class SparcTargetInfo : public TargetInfo { 5488 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5489 static const char * const GCCRegNames[]; 5490 bool SoftFloat; 5491 public: 5492 SparcTargetInfo(const llvm::Triple &Triple) 5493 : TargetInfo(Triple), SoftFloat(false) {} 5494 5495 bool handleTargetFeatures(std::vector<std::string> &Features, 5496 DiagnosticsEngine &Diags) override { 5497 // The backend doesn't actually handle soft float yet, but in case someone 5498 // is using the support for the front end continue to support it. 5499 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5500 if (Feature != Features.end()) { 5501 SoftFloat = true; 5502 Features.erase(Feature); 5503 } 5504 return true; 5505 } 5506 void getTargetDefines(const LangOptions &Opts, 5507 MacroBuilder &Builder) const override { 5508 DefineStd(Builder, "sparc", Opts); 5509 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5510 5511 if (SoftFloat) 5512 Builder.defineMacro("SOFT_FLOAT", "1"); 5513 } 5514 5515 bool hasFeature(StringRef Feature) const override { 5516 return llvm::StringSwitch<bool>(Feature) 5517 .Case("softfloat", SoftFloat) 5518 .Case("sparc", true) 5519 .Default(false); 5520 } 5521 5522 void getTargetBuiltins(const Builtin::Info *&Records, 5523 unsigned &NumRecords) const override { 5524 // FIXME: Implement! 5525 } 5526 BuiltinVaListKind getBuiltinVaListKind() const override { 5527 return TargetInfo::VoidPtrBuiltinVaList; 5528 } 5529 void getGCCRegNames(const char * const *&Names, 5530 unsigned &NumNames) const override; 5531 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5532 unsigned &NumAliases) const override; 5533 bool validateAsmConstraint(const char *&Name, 5534 TargetInfo::ConstraintInfo &info) const override { 5535 // FIXME: Implement! 5536 switch (*Name) { 5537 case 'I': // Signed 13-bit constant 5538 case 'J': // Zero 5539 case 'K': // 32-bit constant with the low 12 bits clear 5540 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5541 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5542 case 'N': // Same as 'K' but zext (required for SIMode) 5543 case 'O': // The constant 4096 5544 return true; 5545 } 5546 return false; 5547 } 5548 const char *getClobbers() const override { 5549 // FIXME: Implement! 5550 return ""; 5551 } 5552 }; 5553 5554 const char * const SparcTargetInfo::GCCRegNames[] = { 5555 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5556 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5557 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5558 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5559 }; 5560 5561 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5562 unsigned &NumNames) const { 5563 Names = GCCRegNames; 5564 NumNames = llvm::array_lengthof(GCCRegNames); 5565 } 5566 5567 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5568 { { "g0" }, "r0" }, 5569 { { "g1" }, "r1" }, 5570 { { "g2" }, "r2" }, 5571 { { "g3" }, "r3" }, 5572 { { "g4" }, "r4" }, 5573 { { "g5" }, "r5" }, 5574 { { "g6" }, "r6" }, 5575 { { "g7" }, "r7" }, 5576 { { "o0" }, "r8" }, 5577 { { "o1" }, "r9" }, 5578 { { "o2" }, "r10" }, 5579 { { "o3" }, "r11" }, 5580 { { "o4" }, "r12" }, 5581 { { "o5" }, "r13" }, 5582 { { "o6", "sp" }, "r14" }, 5583 { { "o7" }, "r15" }, 5584 { { "l0" }, "r16" }, 5585 { { "l1" }, "r17" }, 5586 { { "l2" }, "r18" }, 5587 { { "l3" }, "r19" }, 5588 { { "l4" }, "r20" }, 5589 { { "l5" }, "r21" }, 5590 { { "l6" }, "r22" }, 5591 { { "l7" }, "r23" }, 5592 { { "i0" }, "r24" }, 5593 { { "i1" }, "r25" }, 5594 { { "i2" }, "r26" }, 5595 { { "i3" }, "r27" }, 5596 { { "i4" }, "r28" }, 5597 { { "i5" }, "r29" }, 5598 { { "i6", "fp" }, "r30" }, 5599 { { "i7" }, "r31" }, 5600 }; 5601 5602 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5603 unsigned &NumAliases) const { 5604 Aliases = GCCRegAliases; 5605 NumAliases = llvm::array_lengthof(GCCRegAliases); 5606 } 5607 5608 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5609 class SparcV8TargetInfo : public SparcTargetInfo { 5610 public: 5611 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5612 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5613 // NetBSD uses long (same as llvm default); everyone else uses int. 5614 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5615 SizeType = UnsignedLong; 5616 IntPtrType = SignedLong; 5617 PtrDiffType = SignedLong; 5618 } else { 5619 SizeType = UnsignedInt; 5620 IntPtrType = SignedInt; 5621 PtrDiffType = SignedInt; 5622 } 5623 } 5624 5625 void getTargetDefines(const LangOptions &Opts, 5626 MacroBuilder &Builder) const override { 5627 SparcTargetInfo::getTargetDefines(Opts, Builder); 5628 Builder.defineMacro("__sparcv8"); 5629 } 5630 }; 5631 5632 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5633 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5634 public: 5635 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5636 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5637 BigEndian = false; 5638 } 5639 }; 5640 5641 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5642 class SparcV9TargetInfo : public SparcTargetInfo { 5643 public: 5644 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5645 // FIXME: Support Sparc quad-precision long double? 5646 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5647 // This is an LP64 platform. 5648 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5649 5650 // OpenBSD uses long long for int64_t and intmax_t. 5651 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5652 IntMaxType = SignedLongLong; 5653 else 5654 IntMaxType = SignedLong; 5655 Int64Type = IntMaxType; 5656 5657 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5658 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5659 LongDoubleWidth = 128; 5660 LongDoubleAlign = 128; 5661 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5662 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5663 } 5664 5665 void getTargetDefines(const LangOptions &Opts, 5666 MacroBuilder &Builder) const override { 5667 SparcTargetInfo::getTargetDefines(Opts, Builder); 5668 Builder.defineMacro("__sparcv9"); 5669 Builder.defineMacro("__arch64__"); 5670 // Solaris doesn't need these variants, but the BSDs do. 5671 if (getTriple().getOS() != llvm::Triple::Solaris) { 5672 Builder.defineMacro("__sparc64__"); 5673 Builder.defineMacro("__sparc_v9__"); 5674 Builder.defineMacro("__sparcv9__"); 5675 } 5676 } 5677 5678 bool setCPU(const std::string &Name) override { 5679 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5680 .Case("v9", true) 5681 .Case("ultrasparc", true) 5682 .Case("ultrasparc3", true) 5683 .Case("niagara", true) 5684 .Case("niagara2", true) 5685 .Case("niagara3", true) 5686 .Case("niagara4", true) 5687 .Default(false); 5688 5689 // No need to store the CPU yet. There aren't any CPU-specific 5690 // macros to define. 5691 return CPUKnown; 5692 } 5693 }; 5694 5695 class SystemZTargetInfo : public TargetInfo { 5696 static const Builtin::Info BuiltinInfo[]; 5697 static const char *const GCCRegNames[]; 5698 std::string CPU; 5699 bool HasTransactionalExecution; 5700 bool HasVector; 5701 5702 public: 5703 SystemZTargetInfo(const llvm::Triple &Triple) 5704 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5705 IntMaxType = SignedLong; 5706 Int64Type = SignedLong; 5707 TLSSupported = true; 5708 IntWidth = IntAlign = 32; 5709 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5710 PointerWidth = PointerAlign = 64; 5711 LongDoubleWidth = 128; 5712 LongDoubleAlign = 64; 5713 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5714 DefaultAlignForAttributeAligned = 64; 5715 MinGlobalAlign = 16; 5716 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5717 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5718 } 5719 void getTargetDefines(const LangOptions &Opts, 5720 MacroBuilder &Builder) const override { 5721 Builder.defineMacro("__s390__"); 5722 Builder.defineMacro("__s390x__"); 5723 Builder.defineMacro("__zarch__"); 5724 Builder.defineMacro("__LONG_DOUBLE_128__"); 5725 if (HasTransactionalExecution) 5726 Builder.defineMacro("__HTM__"); 5727 } 5728 void getTargetBuiltins(const Builtin::Info *&Records, 5729 unsigned &NumRecords) const override { 5730 Records = BuiltinInfo; 5731 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5732 } 5733 5734 void getGCCRegNames(const char *const *&Names, 5735 unsigned &NumNames) const override; 5736 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5737 unsigned &NumAliases) const override { 5738 // No aliases. 5739 Aliases = nullptr; 5740 NumAliases = 0; 5741 } 5742 bool validateAsmConstraint(const char *&Name, 5743 TargetInfo::ConstraintInfo &info) const override; 5744 const char *getClobbers() const override { 5745 // FIXME: Is this really right? 5746 return ""; 5747 } 5748 BuiltinVaListKind getBuiltinVaListKind() const override { 5749 return TargetInfo::SystemZBuiltinVaList; 5750 } 5751 bool setCPU(const std::string &Name) override { 5752 CPU = Name; 5753 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5754 .Case("z10", true) 5755 .Case("z196", true) 5756 .Case("zEC12", true) 5757 .Case("z13", true) 5758 .Default(false); 5759 5760 return CPUKnown; 5761 } 5762 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5763 if (CPU == "zEC12") 5764 Features["transactional-execution"] = true; 5765 if (CPU == "z13") { 5766 Features["transactional-execution"] = true; 5767 Features["vector"] = true; 5768 } 5769 } 5770 5771 bool handleTargetFeatures(std::vector<std::string> &Features, 5772 DiagnosticsEngine &Diags) override { 5773 HasTransactionalExecution = false; 5774 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5775 if (Features[i] == "+transactional-execution") 5776 HasTransactionalExecution = true; 5777 if (Features[i] == "+vector") 5778 HasVector = true; 5779 } 5780 // If we use the vector ABI, vector types are 64-bit aligned. 5781 if (HasVector) { 5782 MaxVectorAlign = 64; 5783 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5784 "-v128:64-a:8:16-n32:64"; 5785 } 5786 return true; 5787 } 5788 5789 bool hasFeature(StringRef Feature) const override { 5790 return llvm::StringSwitch<bool>(Feature) 5791 .Case("systemz", true) 5792 .Case("htm", HasTransactionalExecution) 5793 .Case("vx", HasVector) 5794 .Default(false); 5795 } 5796 5797 StringRef getABI() const override { 5798 if (HasVector) 5799 return "vector"; 5800 return ""; 5801 } 5802 5803 bool useFloat128ManglingForLongDouble() const override { 5804 return true; 5805 } 5806 }; 5807 5808 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5809 #define BUILTIN(ID, TYPE, ATTRS) \ 5810 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5811 #include "clang/Basic/BuiltinsSystemZ.def" 5812 }; 5813 5814 const char *const SystemZTargetInfo::GCCRegNames[] = { 5815 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5816 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5817 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5818 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5819 }; 5820 5821 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5822 unsigned &NumNames) const { 5823 Names = GCCRegNames; 5824 NumNames = llvm::array_lengthof(GCCRegNames); 5825 } 5826 5827 bool SystemZTargetInfo:: 5828 validateAsmConstraint(const char *&Name, 5829 TargetInfo::ConstraintInfo &Info) const { 5830 switch (*Name) { 5831 default: 5832 return false; 5833 5834 case 'a': // Address register 5835 case 'd': // Data register (equivalent to 'r') 5836 case 'f': // Floating-point register 5837 Info.setAllowsRegister(); 5838 return true; 5839 5840 case 'I': // Unsigned 8-bit constant 5841 case 'J': // Unsigned 12-bit constant 5842 case 'K': // Signed 16-bit constant 5843 case 'L': // Signed 20-bit displacement (on all targets we support) 5844 case 'M': // 0x7fffffff 5845 return true; 5846 5847 case 'Q': // Memory with base and unsigned 12-bit displacement 5848 case 'R': // Likewise, plus an index 5849 case 'S': // Memory with base and signed 20-bit displacement 5850 case 'T': // Likewise, plus an index 5851 Info.setAllowsMemory(); 5852 return true; 5853 } 5854 } 5855 5856 class MSP430TargetInfo : public TargetInfo { 5857 static const char * const GCCRegNames[]; 5858 public: 5859 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5860 BigEndian = false; 5861 TLSSupported = false; 5862 IntWidth = 16; IntAlign = 16; 5863 LongWidth = 32; LongLongWidth = 64; 5864 LongAlign = LongLongAlign = 16; 5865 PointerWidth = 16; PointerAlign = 16; 5866 SuitableAlign = 16; 5867 SizeType = UnsignedInt; 5868 IntMaxType = SignedLongLong; 5869 IntPtrType = SignedInt; 5870 PtrDiffType = SignedInt; 5871 SigAtomicType = SignedLong; 5872 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5873 } 5874 void getTargetDefines(const LangOptions &Opts, 5875 MacroBuilder &Builder) const override { 5876 Builder.defineMacro("MSP430"); 5877 Builder.defineMacro("__MSP430__"); 5878 // FIXME: defines for different 'flavours' of MCU 5879 } 5880 void getTargetBuiltins(const Builtin::Info *&Records, 5881 unsigned &NumRecords) const override { 5882 // FIXME: Implement. 5883 Records = nullptr; 5884 NumRecords = 0; 5885 } 5886 bool hasFeature(StringRef Feature) const override { 5887 return Feature == "msp430"; 5888 } 5889 void getGCCRegNames(const char * const *&Names, 5890 unsigned &NumNames) const override; 5891 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5892 unsigned &NumAliases) const override { 5893 // No aliases. 5894 Aliases = nullptr; 5895 NumAliases = 0; 5896 } 5897 bool 5898 validateAsmConstraint(const char *&Name, 5899 TargetInfo::ConstraintInfo &info) const override { 5900 // FIXME: implement 5901 switch (*Name) { 5902 case 'K': // the constant 1 5903 case 'L': // constant -1^20 .. 1^19 5904 case 'M': // constant 1-4: 5905 return true; 5906 } 5907 // No target constraints for now. 5908 return false; 5909 } 5910 const char *getClobbers() const override { 5911 // FIXME: Is this really right? 5912 return ""; 5913 } 5914 BuiltinVaListKind getBuiltinVaListKind() const override { 5915 // FIXME: implement 5916 return TargetInfo::CharPtrBuiltinVaList; 5917 } 5918 }; 5919 5920 const char * const MSP430TargetInfo::GCCRegNames[] = { 5921 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5922 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5923 }; 5924 5925 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5926 unsigned &NumNames) const { 5927 Names = GCCRegNames; 5928 NumNames = llvm::array_lengthof(GCCRegNames); 5929 } 5930 5931 // LLVM and Clang cannot be used directly to output native binaries for 5932 // target, but is used to compile C code to llvm bitcode with correct 5933 // type and alignment information. 5934 // 5935 // TCE uses the llvm bitcode as input and uses it for generating customized 5936 // target processor and program binary. TCE co-design environment is 5937 // publicly available in http://tce.cs.tut.fi 5938 5939 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5940 3, // opencl_global 5941 4, // opencl_local 5942 5, // opencl_constant 5943 // FIXME: generic has to be added to the target 5944 0, // opencl_generic 5945 0, // cuda_device 5946 0, // cuda_constant 5947 0 // cuda_shared 5948 }; 5949 5950 class TCETargetInfo : public TargetInfo{ 5951 public: 5952 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5953 TLSSupported = false; 5954 IntWidth = 32; 5955 LongWidth = LongLongWidth = 32; 5956 PointerWidth = 32; 5957 IntAlign = 32; 5958 LongAlign = LongLongAlign = 32; 5959 PointerAlign = 32; 5960 SuitableAlign = 32; 5961 SizeType = UnsignedInt; 5962 IntMaxType = SignedLong; 5963 IntPtrType = SignedInt; 5964 PtrDiffType = SignedInt; 5965 FloatWidth = 32; 5966 FloatAlign = 32; 5967 DoubleWidth = 32; 5968 DoubleAlign = 32; 5969 LongDoubleWidth = 32; 5970 LongDoubleAlign = 32; 5971 FloatFormat = &llvm::APFloat::IEEEsingle; 5972 DoubleFormat = &llvm::APFloat::IEEEsingle; 5973 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5974 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5975 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5976 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5977 UseAddrSpaceMapMangling = true; 5978 } 5979 5980 void getTargetDefines(const LangOptions &Opts, 5981 MacroBuilder &Builder) const override { 5982 DefineStd(Builder, "tce", Opts); 5983 Builder.defineMacro("__TCE__"); 5984 Builder.defineMacro("__TCE_V1__"); 5985 } 5986 bool hasFeature(StringRef Feature) const override { 5987 return Feature == "tce"; 5988 } 5989 5990 void getTargetBuiltins(const Builtin::Info *&Records, 5991 unsigned &NumRecords) const override {} 5992 const char *getClobbers() const override { 5993 return ""; 5994 } 5995 BuiltinVaListKind getBuiltinVaListKind() const override { 5996 return TargetInfo::VoidPtrBuiltinVaList; 5997 } 5998 void getGCCRegNames(const char * const *&Names, 5999 unsigned &NumNames) const override {} 6000 bool validateAsmConstraint(const char *&Name, 6001 TargetInfo::ConstraintInfo &info) const override{ 6002 return true; 6003 } 6004 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6005 unsigned &NumAliases) const override {} 6006 }; 6007 6008 class BPFTargetInfo : public TargetInfo { 6009 public: 6010 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6011 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6012 SizeType = UnsignedLong; 6013 PtrDiffType = SignedLong; 6014 IntPtrType = SignedLong; 6015 IntMaxType = SignedLong; 6016 Int64Type = SignedLong; 6017 RegParmMax = 5; 6018 if (Triple.getArch() == llvm::Triple::bpfeb) { 6019 BigEndian = true; 6020 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6021 } else { 6022 BigEndian = false; 6023 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6024 } 6025 MaxAtomicPromoteWidth = 64; 6026 MaxAtomicInlineWidth = 64; 6027 TLSSupported = false; 6028 } 6029 void getTargetDefines(const LangOptions &Opts, 6030 MacroBuilder &Builder) const override { 6031 DefineStd(Builder, "bpf", Opts); 6032 Builder.defineMacro("__BPF__"); 6033 } 6034 bool hasFeature(StringRef Feature) const override { 6035 return Feature == "bpf"; 6036 } 6037 6038 void getTargetBuiltins(const Builtin::Info *&Records, 6039 unsigned &NumRecords) const override {} 6040 const char *getClobbers() const override { 6041 return ""; 6042 } 6043 BuiltinVaListKind getBuiltinVaListKind() const override { 6044 return TargetInfo::VoidPtrBuiltinVaList; 6045 } 6046 void getGCCRegNames(const char * const *&Names, 6047 unsigned &NumNames) const override { 6048 Names = nullptr; 6049 NumNames = 0; 6050 } 6051 bool validateAsmConstraint(const char *&Name, 6052 TargetInfo::ConstraintInfo &info) const override { 6053 return true; 6054 } 6055 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6056 unsigned &NumAliases) const override { 6057 Aliases = nullptr; 6058 NumAliases = 0; 6059 } 6060 }; 6061 6062 class MipsTargetInfoBase : public TargetInfo { 6063 virtual void setDescriptionString() = 0; 6064 6065 static const Builtin::Info BuiltinInfo[]; 6066 std::string CPU; 6067 bool IsMips16; 6068 bool IsMicromips; 6069 bool IsNan2008; 6070 bool IsSingleFloat; 6071 enum MipsFloatABI { 6072 HardFloat, SoftFloat 6073 } FloatABI; 6074 enum DspRevEnum { 6075 NoDSP, DSP1, DSP2 6076 } DspRev; 6077 bool HasMSA; 6078 6079 protected: 6080 bool HasFP64; 6081 std::string ABI; 6082 6083 public: 6084 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6085 const std::string &CPUStr) 6086 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6087 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6088 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6089 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6090 } 6091 6092 bool isNaN2008Default() const { 6093 return CPU == "mips32r6" || CPU == "mips64r6"; 6094 } 6095 6096 bool isFP64Default() const { 6097 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6098 } 6099 6100 bool isNan2008() const override { 6101 return IsNan2008; 6102 } 6103 6104 StringRef getABI() const override { return ABI; } 6105 bool setCPU(const std::string &Name) override { 6106 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6107 getTriple().getArch() == llvm::Triple::mipsel; 6108 CPU = Name; 6109 return llvm::StringSwitch<bool>(Name) 6110 .Case("mips1", IsMips32) 6111 .Case("mips2", IsMips32) 6112 .Case("mips3", true) 6113 .Case("mips4", true) 6114 .Case("mips5", true) 6115 .Case("mips32", IsMips32) 6116 .Case("mips32r2", IsMips32) 6117 .Case("mips32r3", IsMips32) 6118 .Case("mips32r5", IsMips32) 6119 .Case("mips32r6", IsMips32) 6120 .Case("mips64", true) 6121 .Case("mips64r2", true) 6122 .Case("mips64r3", true) 6123 .Case("mips64r5", true) 6124 .Case("mips64r6", true) 6125 .Case("octeon", true) 6126 .Default(false); 6127 } 6128 const std::string& getCPU() const { return CPU; } 6129 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6130 if (CPU == "octeon") 6131 Features["mips64r2"] = Features["cnmips"] = true; 6132 else 6133 Features[CPU] = true; 6134 } 6135 6136 void getTargetDefines(const LangOptions &Opts, 6137 MacroBuilder &Builder) const override { 6138 Builder.defineMacro("__mips__"); 6139 Builder.defineMacro("_mips"); 6140 if (Opts.GNUMode) 6141 Builder.defineMacro("mips"); 6142 6143 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6144 6145 switch (FloatABI) { 6146 case HardFloat: 6147 Builder.defineMacro("__mips_hard_float", Twine(1)); 6148 break; 6149 case SoftFloat: 6150 Builder.defineMacro("__mips_soft_float", Twine(1)); 6151 break; 6152 } 6153 6154 if (IsSingleFloat) 6155 Builder.defineMacro("__mips_single_float", Twine(1)); 6156 6157 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6158 Builder.defineMacro("_MIPS_FPSET", 6159 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6160 6161 if (IsMips16) 6162 Builder.defineMacro("__mips16", Twine(1)); 6163 6164 if (IsMicromips) 6165 Builder.defineMacro("__mips_micromips", Twine(1)); 6166 6167 if (IsNan2008) 6168 Builder.defineMacro("__mips_nan2008", Twine(1)); 6169 6170 switch (DspRev) { 6171 default: 6172 break; 6173 case DSP1: 6174 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6175 Builder.defineMacro("__mips_dsp", Twine(1)); 6176 break; 6177 case DSP2: 6178 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6179 Builder.defineMacro("__mips_dspr2", Twine(1)); 6180 Builder.defineMacro("__mips_dsp", Twine(1)); 6181 break; 6182 } 6183 6184 if (HasMSA) 6185 Builder.defineMacro("__mips_msa", Twine(1)); 6186 6187 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6188 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6189 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6190 6191 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6192 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6193 } 6194 6195 void getTargetBuiltins(const Builtin::Info *&Records, 6196 unsigned &NumRecords) const override { 6197 Records = BuiltinInfo; 6198 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6199 } 6200 bool hasFeature(StringRef Feature) const override { 6201 return llvm::StringSwitch<bool>(Feature) 6202 .Case("mips", true) 6203 .Case("fp64", HasFP64) 6204 .Default(false); 6205 } 6206 BuiltinVaListKind getBuiltinVaListKind() const override { 6207 return TargetInfo::VoidPtrBuiltinVaList; 6208 } 6209 void getGCCRegNames(const char * const *&Names, 6210 unsigned &NumNames) const override { 6211 static const char *const GCCRegNames[] = { 6212 // CPU register names 6213 // Must match second column of GCCRegAliases 6214 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6215 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6216 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6217 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6218 // Floating point register names 6219 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6220 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6221 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6222 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6223 // Hi/lo and condition register names 6224 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6225 "$fcc5","$fcc6","$fcc7", 6226 // MSA register names 6227 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6228 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6229 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6230 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6231 // MSA control register names 6232 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6233 "$msarequest", "$msamap", "$msaunmap" 6234 }; 6235 Names = GCCRegNames; 6236 NumNames = llvm::array_lengthof(GCCRegNames); 6237 } 6238 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6239 unsigned &NumAliases) const override = 0; 6240 bool validateAsmConstraint(const char *&Name, 6241 TargetInfo::ConstraintInfo &Info) const override { 6242 switch (*Name) { 6243 default: 6244 return false; 6245 case 'r': // CPU registers. 6246 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6247 case 'y': // Equivalent to "r", backward compatibility only. 6248 case 'f': // floating-point registers. 6249 case 'c': // $25 for indirect jumps 6250 case 'l': // lo register 6251 case 'x': // hilo register pair 6252 Info.setAllowsRegister(); 6253 return true; 6254 case 'I': // Signed 16-bit constant 6255 case 'J': // Integer 0 6256 case 'K': // Unsigned 16-bit constant 6257 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6258 case 'M': // Constants not loadable via lui, addiu, or ori 6259 case 'N': // Constant -1 to -65535 6260 case 'O': // A signed 15-bit constant 6261 case 'P': // A constant between 1 go 65535 6262 return true; 6263 case 'R': // An address that can be used in a non-macro load or store 6264 Info.setAllowsMemory(); 6265 return true; 6266 case 'Z': 6267 if (Name[1] == 'C') { // An address usable by ll, and sc. 6268 Info.setAllowsMemory(); 6269 Name++; // Skip over 'Z'. 6270 return true; 6271 } 6272 return false; 6273 } 6274 } 6275 6276 std::string convertConstraint(const char *&Constraint) const override { 6277 std::string R; 6278 switch (*Constraint) { 6279 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6280 if (Constraint[1] == 'C') { 6281 R = std::string("^") + std::string(Constraint, 2); 6282 Constraint++; 6283 return R; 6284 } 6285 break; 6286 } 6287 return TargetInfo::convertConstraint(Constraint); 6288 } 6289 6290 const char *getClobbers() const override { 6291 // In GCC, $1 is not widely used in generated code (it's used only in a few 6292 // specific situations), so there is no real need for users to add it to 6293 // the clobbers list if they want to use it in their inline assembly code. 6294 // 6295 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6296 // code generation, so using it in inline assembly without adding it to the 6297 // clobbers list can cause conflicts between the inline assembly code and 6298 // the surrounding generated code. 6299 // 6300 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6301 // operands, which will conflict with the ".set at" assembler option (which 6302 // we use only for inline assembly, in order to maintain compatibility with 6303 // GCC) and will also conflict with the user's usage of $1. 6304 // 6305 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6306 // register for generated code is to automatically clobber $1 for all inline 6307 // assembly code. 6308 // 6309 // FIXME: We should automatically clobber $1 only for inline assembly code 6310 // which actually uses it. This would allow LLVM to use $1 for inline 6311 // assembly operands if the user's assembly code doesn't use it. 6312 return "~{$1}"; 6313 } 6314 6315 bool handleTargetFeatures(std::vector<std::string> &Features, 6316 DiagnosticsEngine &Diags) override { 6317 IsMips16 = false; 6318 IsMicromips = false; 6319 IsNan2008 = isNaN2008Default(); 6320 IsSingleFloat = false; 6321 FloatABI = HardFloat; 6322 DspRev = NoDSP; 6323 HasFP64 = isFP64Default(); 6324 6325 for (std::vector<std::string>::iterator it = Features.begin(), 6326 ie = Features.end(); it != ie; ++it) { 6327 if (*it == "+single-float") 6328 IsSingleFloat = true; 6329 else if (*it == "+soft-float") 6330 FloatABI = SoftFloat; 6331 else if (*it == "+mips16") 6332 IsMips16 = true; 6333 else if (*it == "+micromips") 6334 IsMicromips = true; 6335 else if (*it == "+dsp") 6336 DspRev = std::max(DspRev, DSP1); 6337 else if (*it == "+dspr2") 6338 DspRev = std::max(DspRev, DSP2); 6339 else if (*it == "+msa") 6340 HasMSA = true; 6341 else if (*it == "+fp64") 6342 HasFP64 = true; 6343 else if (*it == "-fp64") 6344 HasFP64 = false; 6345 else if (*it == "+nan2008") 6346 IsNan2008 = true; 6347 else if (*it == "-nan2008") 6348 IsNan2008 = false; 6349 } 6350 6351 setDescriptionString(); 6352 6353 return true; 6354 } 6355 6356 int getEHDataRegisterNumber(unsigned RegNo) const override { 6357 if (RegNo == 0) return 4; 6358 if (RegNo == 1) return 5; 6359 return -1; 6360 } 6361 6362 bool isCLZForZeroUndef() const override { return false; } 6363 }; 6364 6365 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6366 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6367 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6368 ALL_LANGUAGES }, 6369 #include "clang/Basic/BuiltinsMips.def" 6370 }; 6371 6372 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6373 public: 6374 Mips32TargetInfoBase(const llvm::Triple &Triple) 6375 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6376 SizeType = UnsignedInt; 6377 PtrDiffType = SignedInt; 6378 Int64Type = SignedLongLong; 6379 IntMaxType = Int64Type; 6380 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6381 } 6382 bool setABI(const std::string &Name) override { 6383 if (Name == "o32" || Name == "eabi") { 6384 ABI = Name; 6385 return true; 6386 } 6387 return false; 6388 } 6389 void getTargetDefines(const LangOptions &Opts, 6390 MacroBuilder &Builder) const override { 6391 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6392 6393 Builder.defineMacro("__mips", "32"); 6394 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6395 6396 const std::string& CPUStr = getCPU(); 6397 if (CPUStr == "mips32") 6398 Builder.defineMacro("__mips_isa_rev", "1"); 6399 else if (CPUStr == "mips32r2") 6400 Builder.defineMacro("__mips_isa_rev", "2"); 6401 else if (CPUStr == "mips32r3") 6402 Builder.defineMacro("__mips_isa_rev", "3"); 6403 else if (CPUStr == "mips32r5") 6404 Builder.defineMacro("__mips_isa_rev", "5"); 6405 else if (CPUStr == "mips32r6") 6406 Builder.defineMacro("__mips_isa_rev", "6"); 6407 6408 if (ABI == "o32") { 6409 Builder.defineMacro("__mips_o32"); 6410 Builder.defineMacro("_ABIO32", "1"); 6411 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6412 } 6413 else if (ABI == "eabi") 6414 Builder.defineMacro("__mips_eabi"); 6415 else 6416 llvm_unreachable("Invalid ABI for Mips32."); 6417 } 6418 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6419 unsigned &NumAliases) const override { 6420 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6421 { { "at" }, "$1" }, 6422 { { "v0" }, "$2" }, 6423 { { "v1" }, "$3" }, 6424 { { "a0" }, "$4" }, 6425 { { "a1" }, "$5" }, 6426 { { "a2" }, "$6" }, 6427 { { "a3" }, "$7" }, 6428 { { "t0" }, "$8" }, 6429 { { "t1" }, "$9" }, 6430 { { "t2" }, "$10" }, 6431 { { "t3" }, "$11" }, 6432 { { "t4" }, "$12" }, 6433 { { "t5" }, "$13" }, 6434 { { "t6" }, "$14" }, 6435 { { "t7" }, "$15" }, 6436 { { "s0" }, "$16" }, 6437 { { "s1" }, "$17" }, 6438 { { "s2" }, "$18" }, 6439 { { "s3" }, "$19" }, 6440 { { "s4" }, "$20" }, 6441 { { "s5" }, "$21" }, 6442 { { "s6" }, "$22" }, 6443 { { "s7" }, "$23" }, 6444 { { "t8" }, "$24" }, 6445 { { "t9" }, "$25" }, 6446 { { "k0" }, "$26" }, 6447 { { "k1" }, "$27" }, 6448 { { "gp" }, "$28" }, 6449 { { "sp","$sp" }, "$29" }, 6450 { { "fp","$fp" }, "$30" }, 6451 { { "ra" }, "$31" } 6452 }; 6453 Aliases = GCCRegAliases; 6454 NumAliases = llvm::array_lengthof(GCCRegAliases); 6455 } 6456 }; 6457 6458 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6459 void setDescriptionString() override { 6460 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6461 } 6462 6463 public: 6464 Mips32EBTargetInfo(const llvm::Triple &Triple) 6465 : Mips32TargetInfoBase(Triple) { 6466 } 6467 void getTargetDefines(const LangOptions &Opts, 6468 MacroBuilder &Builder) const override { 6469 DefineStd(Builder, "MIPSEB", Opts); 6470 Builder.defineMacro("_MIPSEB"); 6471 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6472 } 6473 }; 6474 6475 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6476 void setDescriptionString() override { 6477 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6478 } 6479 6480 public: 6481 Mips32ELTargetInfo(const llvm::Triple &Triple) 6482 : Mips32TargetInfoBase(Triple) { 6483 BigEndian = false; 6484 } 6485 void getTargetDefines(const LangOptions &Opts, 6486 MacroBuilder &Builder) const override { 6487 DefineStd(Builder, "MIPSEL", Opts); 6488 Builder.defineMacro("_MIPSEL"); 6489 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6490 } 6491 }; 6492 6493 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6494 public: 6495 Mips64TargetInfoBase(const llvm::Triple &Triple) 6496 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6497 LongDoubleWidth = LongDoubleAlign = 128; 6498 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6499 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6500 LongDoubleWidth = LongDoubleAlign = 64; 6501 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6502 } 6503 setN64ABITypes(); 6504 SuitableAlign = 128; 6505 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6506 } 6507 6508 void setN64ABITypes() { 6509 LongWidth = LongAlign = 64; 6510 PointerWidth = PointerAlign = 64; 6511 SizeType = UnsignedLong; 6512 PtrDiffType = SignedLong; 6513 Int64Type = SignedLong; 6514 IntMaxType = Int64Type; 6515 } 6516 6517 void setN32ABITypes() { 6518 LongWidth = LongAlign = 32; 6519 PointerWidth = PointerAlign = 32; 6520 SizeType = UnsignedInt; 6521 PtrDiffType = SignedInt; 6522 Int64Type = SignedLongLong; 6523 IntMaxType = Int64Type; 6524 } 6525 6526 bool setABI(const std::string &Name) override { 6527 if (Name == "n32") { 6528 setN32ABITypes(); 6529 ABI = Name; 6530 return true; 6531 } 6532 if (Name == "n64") { 6533 setN64ABITypes(); 6534 ABI = Name; 6535 return true; 6536 } 6537 return false; 6538 } 6539 6540 void getTargetDefines(const LangOptions &Opts, 6541 MacroBuilder &Builder) const override { 6542 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6543 6544 Builder.defineMacro("__mips", "64"); 6545 Builder.defineMacro("__mips64"); 6546 Builder.defineMacro("__mips64__"); 6547 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6548 6549 const std::string& CPUStr = getCPU(); 6550 if (CPUStr == "mips64") 6551 Builder.defineMacro("__mips_isa_rev", "1"); 6552 else if (CPUStr == "mips64r2") 6553 Builder.defineMacro("__mips_isa_rev", "2"); 6554 else if (CPUStr == "mips64r3") 6555 Builder.defineMacro("__mips_isa_rev", "3"); 6556 else if (CPUStr == "mips64r5") 6557 Builder.defineMacro("__mips_isa_rev", "5"); 6558 else if (CPUStr == "mips64r6") 6559 Builder.defineMacro("__mips_isa_rev", "6"); 6560 6561 if (ABI == "n32") { 6562 Builder.defineMacro("__mips_n32"); 6563 Builder.defineMacro("_ABIN32", "2"); 6564 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6565 } 6566 else if (ABI == "n64") { 6567 Builder.defineMacro("__mips_n64"); 6568 Builder.defineMacro("_ABI64", "3"); 6569 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6570 } 6571 else 6572 llvm_unreachable("Invalid ABI for Mips64."); 6573 } 6574 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6575 unsigned &NumAliases) const override { 6576 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6577 { { "at" }, "$1" }, 6578 { { "v0" }, "$2" }, 6579 { { "v1" }, "$3" }, 6580 { { "a0" }, "$4" }, 6581 { { "a1" }, "$5" }, 6582 { { "a2" }, "$6" }, 6583 { { "a3" }, "$7" }, 6584 { { "a4" }, "$8" }, 6585 { { "a5" }, "$9" }, 6586 { { "a6" }, "$10" }, 6587 { { "a7" }, "$11" }, 6588 { { "t0" }, "$12" }, 6589 { { "t1" }, "$13" }, 6590 { { "t2" }, "$14" }, 6591 { { "t3" }, "$15" }, 6592 { { "s0" }, "$16" }, 6593 { { "s1" }, "$17" }, 6594 { { "s2" }, "$18" }, 6595 { { "s3" }, "$19" }, 6596 { { "s4" }, "$20" }, 6597 { { "s5" }, "$21" }, 6598 { { "s6" }, "$22" }, 6599 { { "s7" }, "$23" }, 6600 { { "t8" }, "$24" }, 6601 { { "t9" }, "$25" }, 6602 { { "k0" }, "$26" }, 6603 { { "k1" }, "$27" }, 6604 { { "gp" }, "$28" }, 6605 { { "sp","$sp" }, "$29" }, 6606 { { "fp","$fp" }, "$30" }, 6607 { { "ra" }, "$31" } 6608 }; 6609 Aliases = GCCRegAliases; 6610 NumAliases = llvm::array_lengthof(GCCRegAliases); 6611 } 6612 6613 bool hasInt128Type() const override { return true; } 6614 }; 6615 6616 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6617 void setDescriptionString() override { 6618 if (ABI == "n32") 6619 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6620 else 6621 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6622 6623 } 6624 6625 public: 6626 Mips64EBTargetInfo(const llvm::Triple &Triple) 6627 : Mips64TargetInfoBase(Triple) {} 6628 void getTargetDefines(const LangOptions &Opts, 6629 MacroBuilder &Builder) const override { 6630 DefineStd(Builder, "MIPSEB", Opts); 6631 Builder.defineMacro("_MIPSEB"); 6632 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6633 } 6634 }; 6635 6636 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6637 void setDescriptionString() override { 6638 if (ABI == "n32") 6639 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6640 else 6641 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6642 } 6643 public: 6644 Mips64ELTargetInfo(const llvm::Triple &Triple) 6645 : Mips64TargetInfoBase(Triple) { 6646 // Default ABI is n64. 6647 BigEndian = false; 6648 } 6649 void getTargetDefines(const LangOptions &Opts, 6650 MacroBuilder &Builder) const override { 6651 DefineStd(Builder, "MIPSEL", Opts); 6652 Builder.defineMacro("_MIPSEL"); 6653 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6654 } 6655 }; 6656 6657 class PNaClTargetInfo : public TargetInfo { 6658 public: 6659 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6660 BigEndian = false; 6661 this->UserLabelPrefix = ""; 6662 this->LongAlign = 32; 6663 this->LongWidth = 32; 6664 this->PointerAlign = 32; 6665 this->PointerWidth = 32; 6666 this->IntMaxType = TargetInfo::SignedLongLong; 6667 this->Int64Type = TargetInfo::SignedLongLong; 6668 this->DoubleAlign = 64; 6669 this->LongDoubleWidth = 64; 6670 this->LongDoubleAlign = 64; 6671 this->SizeType = TargetInfo::UnsignedInt; 6672 this->PtrDiffType = TargetInfo::SignedInt; 6673 this->IntPtrType = TargetInfo::SignedInt; 6674 this->RegParmMax = 0; // Disallow regparm 6675 } 6676 6677 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6678 } 6679 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6680 Builder.defineMacro("__le32__"); 6681 Builder.defineMacro("__pnacl__"); 6682 } 6683 void getTargetDefines(const LangOptions &Opts, 6684 MacroBuilder &Builder) const override { 6685 getArchDefines(Opts, Builder); 6686 } 6687 bool hasFeature(StringRef Feature) const override { 6688 return Feature == "pnacl"; 6689 } 6690 void getTargetBuiltins(const Builtin::Info *&Records, 6691 unsigned &NumRecords) const override { 6692 } 6693 BuiltinVaListKind getBuiltinVaListKind() const override { 6694 return TargetInfo::PNaClABIBuiltinVaList; 6695 } 6696 void getGCCRegNames(const char * const *&Names, 6697 unsigned &NumNames) const override; 6698 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6699 unsigned &NumAliases) const override; 6700 bool validateAsmConstraint(const char *&Name, 6701 TargetInfo::ConstraintInfo &Info) const override { 6702 return false; 6703 } 6704 6705 const char *getClobbers() const override { 6706 return ""; 6707 } 6708 }; 6709 6710 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6711 unsigned &NumNames) const { 6712 Names = nullptr; 6713 NumNames = 0; 6714 } 6715 6716 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6717 unsigned &NumAliases) const { 6718 Aliases = nullptr; 6719 NumAliases = 0; 6720 } 6721 6722 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6723 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6724 public: 6725 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6726 Mips32ELTargetInfo(Triple) { 6727 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0; 6728 } 6729 6730 BuiltinVaListKind getBuiltinVaListKind() const override { 6731 return TargetInfo::PNaClABIBuiltinVaList; 6732 } 6733 }; 6734 6735 class Le64TargetInfo : public TargetInfo { 6736 static const Builtin::Info BuiltinInfo[]; 6737 6738 public: 6739 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6740 BigEndian = false; 6741 NoAsmVariants = true; 6742 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6744 DescriptionString = 6745 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6746 } 6747 6748 void getTargetDefines(const LangOptions &Opts, 6749 MacroBuilder &Builder) const override { 6750 DefineStd(Builder, "unix", Opts); 6751 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6752 Builder.defineMacro("__ELF__"); 6753 } 6754 void getTargetBuiltins(const Builtin::Info *&Records, 6755 unsigned &NumRecords) const override { 6756 Records = BuiltinInfo; 6757 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6758 } 6759 BuiltinVaListKind getBuiltinVaListKind() const override { 6760 return TargetInfo::PNaClABIBuiltinVaList; 6761 } 6762 const char *getClobbers() const override { return ""; } 6763 void getGCCRegNames(const char *const *&Names, 6764 unsigned &NumNames) const override { 6765 Names = nullptr; 6766 NumNames = 0; 6767 } 6768 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6769 unsigned &NumAliases) const override { 6770 Aliases = nullptr; 6771 NumAliases = 0; 6772 } 6773 bool validateAsmConstraint(const char *&Name, 6774 TargetInfo::ConstraintInfo &Info) const override { 6775 return false; 6776 } 6777 6778 bool hasProtectedVisibility() const override { return false; } 6779 }; 6780 } // end anonymous namespace. 6781 6782 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6783 #define BUILTIN(ID, TYPE, ATTRS) \ 6784 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6785 #include "clang/Basic/BuiltinsLe64.def" 6786 }; 6787 6788 namespace { 6789 static const unsigned SPIRAddrSpaceMap[] = { 6790 1, // opencl_global 6791 3, // opencl_local 6792 2, // opencl_constant 6793 4, // opencl_generic 6794 0, // cuda_device 6795 0, // cuda_constant 6796 0 // cuda_shared 6797 }; 6798 class SPIRTargetInfo : public TargetInfo { 6799 public: 6800 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6801 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6802 "SPIR target must use unknown OS"); 6803 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6804 "SPIR target must use unknown environment type"); 6805 BigEndian = false; 6806 TLSSupported = false; 6807 LongWidth = LongAlign = 64; 6808 AddrSpaceMap = &SPIRAddrSpaceMap; 6809 UseAddrSpaceMapMangling = true; 6810 // Define available target features 6811 // These must be defined in sorted order! 6812 NoAsmVariants = true; 6813 } 6814 void getTargetDefines(const LangOptions &Opts, 6815 MacroBuilder &Builder) const override { 6816 DefineStd(Builder, "SPIR", Opts); 6817 } 6818 bool hasFeature(StringRef Feature) const override { 6819 return Feature == "spir"; 6820 } 6821 6822 void getTargetBuiltins(const Builtin::Info *&Records, 6823 unsigned &NumRecords) const override {} 6824 const char *getClobbers() const override { 6825 return ""; 6826 } 6827 void getGCCRegNames(const char * const *&Names, 6828 unsigned &NumNames) const override {} 6829 bool 6830 validateAsmConstraint(const char *&Name, 6831 TargetInfo::ConstraintInfo &info) const override { 6832 return true; 6833 } 6834 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6835 unsigned &NumAliases) const override {} 6836 BuiltinVaListKind getBuiltinVaListKind() const override { 6837 return TargetInfo::VoidPtrBuiltinVaList; 6838 } 6839 6840 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6841 return (CC == CC_SpirFunction || 6842 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6843 } 6844 6845 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6846 return CC_SpirFunction; 6847 } 6848 }; 6849 6850 6851 class SPIR32TargetInfo : public SPIRTargetInfo { 6852 public: 6853 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6854 PointerWidth = PointerAlign = 32; 6855 SizeType = TargetInfo::UnsignedInt; 6856 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6857 DescriptionString 6858 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6859 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6860 } 6861 void getTargetDefines(const LangOptions &Opts, 6862 MacroBuilder &Builder) const override { 6863 DefineStd(Builder, "SPIR32", Opts); 6864 } 6865 }; 6866 6867 class SPIR64TargetInfo : public SPIRTargetInfo { 6868 public: 6869 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6870 PointerWidth = PointerAlign = 64; 6871 SizeType = TargetInfo::UnsignedLong; 6872 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6873 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6874 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6875 } 6876 void getTargetDefines(const LangOptions &Opts, 6877 MacroBuilder &Builder) const override { 6878 DefineStd(Builder, "SPIR64", Opts); 6879 } 6880 }; 6881 6882 class XCoreTargetInfo : public TargetInfo { 6883 static const Builtin::Info BuiltinInfo[]; 6884 public: 6885 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6886 BigEndian = false; 6887 NoAsmVariants = true; 6888 LongLongAlign = 32; 6889 SuitableAlign = 32; 6890 DoubleAlign = LongDoubleAlign = 32; 6891 SizeType = UnsignedInt; 6892 PtrDiffType = SignedInt; 6893 IntPtrType = SignedInt; 6894 WCharType = UnsignedChar; 6895 WIntType = UnsignedInt; 6896 UseZeroLengthBitfieldAlignment = true; 6897 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6898 "-f64:32-a:0:32-n32"; 6899 } 6900 void getTargetDefines(const LangOptions &Opts, 6901 MacroBuilder &Builder) const override { 6902 Builder.defineMacro("__XS1B__"); 6903 } 6904 void getTargetBuiltins(const Builtin::Info *&Records, 6905 unsigned &NumRecords) const override { 6906 Records = BuiltinInfo; 6907 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6908 } 6909 BuiltinVaListKind getBuiltinVaListKind() const override { 6910 return TargetInfo::VoidPtrBuiltinVaList; 6911 } 6912 const char *getClobbers() const override { 6913 return ""; 6914 } 6915 void getGCCRegNames(const char * const *&Names, 6916 unsigned &NumNames) const override { 6917 static const char * const GCCRegNames[] = { 6918 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6919 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6920 }; 6921 Names = GCCRegNames; 6922 NumNames = llvm::array_lengthof(GCCRegNames); 6923 } 6924 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6925 unsigned &NumAliases) const override { 6926 Aliases = nullptr; 6927 NumAliases = 0; 6928 } 6929 bool validateAsmConstraint(const char *&Name, 6930 TargetInfo::ConstraintInfo &Info) const override { 6931 return false; 6932 } 6933 int getEHDataRegisterNumber(unsigned RegNo) const override { 6934 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6935 return (RegNo < 2)? RegNo : -1; 6936 } 6937 }; 6938 6939 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6940 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6942 ALL_LANGUAGES }, 6943 #include "clang/Basic/BuiltinsXCore.def" 6944 }; 6945 } // end anonymous namespace. 6946 6947 namespace { 6948 // x86_32 Android target 6949 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6950 public: 6951 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6952 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6953 SuitableAlign = 32; 6954 LongDoubleWidth = 64; 6955 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6956 } 6957 }; 6958 } // end anonymous namespace 6959 6960 namespace { 6961 // x86_64 Android target 6962 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6963 public: 6964 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6965 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6966 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6967 } 6968 }; 6969 } // end anonymous namespace 6970 6971 6972 //===----------------------------------------------------------------------===// 6973 // Driver code 6974 //===----------------------------------------------------------------------===// 6975 6976 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6977 llvm::Triple::OSType os = Triple.getOS(); 6978 6979 switch (Triple.getArch()) { 6980 default: 6981 return nullptr; 6982 6983 case llvm::Triple::xcore: 6984 return new XCoreTargetInfo(Triple); 6985 6986 case llvm::Triple::hexagon: 6987 return new HexagonTargetInfo(Triple); 6988 6989 case llvm::Triple::aarch64: 6990 if (Triple.isOSDarwin()) 6991 return new DarwinAArch64TargetInfo(Triple); 6992 6993 switch (os) { 6994 case llvm::Triple::FreeBSD: 6995 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6996 case llvm::Triple::Linux: 6997 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6998 case llvm::Triple::NetBSD: 6999 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7000 default: 7001 return new AArch64leTargetInfo(Triple); 7002 } 7003 7004 case llvm::Triple::aarch64_be: 7005 switch (os) { 7006 case llvm::Triple::FreeBSD: 7007 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7008 case llvm::Triple::Linux: 7009 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7010 case llvm::Triple::NetBSD: 7011 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7012 default: 7013 return new AArch64beTargetInfo(Triple); 7014 } 7015 7016 case llvm::Triple::arm: 7017 case llvm::Triple::thumb: 7018 if (Triple.isOSBinFormatMachO()) 7019 return new DarwinARMTargetInfo(Triple); 7020 7021 switch (os) { 7022 case llvm::Triple::Linux: 7023 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7024 case llvm::Triple::FreeBSD: 7025 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7026 case llvm::Triple::NetBSD: 7027 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7028 case llvm::Triple::OpenBSD: 7029 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7030 case llvm::Triple::Bitrig: 7031 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7032 case llvm::Triple::RTEMS: 7033 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7034 case llvm::Triple::NaCl: 7035 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7036 case llvm::Triple::Win32: 7037 switch (Triple.getEnvironment()) { 7038 default: 7039 return new ARMleTargetInfo(Triple); 7040 case llvm::Triple::Itanium: 7041 return new ItaniumWindowsARMleTargetInfo(Triple); 7042 case llvm::Triple::MSVC: 7043 return new MicrosoftARMleTargetInfo(Triple); 7044 } 7045 default: 7046 return new ARMleTargetInfo(Triple); 7047 } 7048 7049 case llvm::Triple::armeb: 7050 case llvm::Triple::thumbeb: 7051 if (Triple.isOSDarwin()) 7052 return new DarwinARMTargetInfo(Triple); 7053 7054 switch (os) { 7055 case llvm::Triple::Linux: 7056 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7057 case llvm::Triple::FreeBSD: 7058 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7059 case llvm::Triple::NetBSD: 7060 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7061 case llvm::Triple::OpenBSD: 7062 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7063 case llvm::Triple::Bitrig: 7064 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7065 case llvm::Triple::RTEMS: 7066 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7067 case llvm::Triple::NaCl: 7068 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7069 default: 7070 return new ARMbeTargetInfo(Triple); 7071 } 7072 7073 case llvm::Triple::bpfeb: 7074 case llvm::Triple::bpfel: 7075 return new BPFTargetInfo(Triple); 7076 7077 case llvm::Triple::msp430: 7078 return new MSP430TargetInfo(Triple); 7079 7080 case llvm::Triple::mips: 7081 switch (os) { 7082 case llvm::Triple::Linux: 7083 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7084 case llvm::Triple::RTEMS: 7085 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7086 case llvm::Triple::FreeBSD: 7087 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7088 case llvm::Triple::NetBSD: 7089 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7090 default: 7091 return new Mips32EBTargetInfo(Triple); 7092 } 7093 7094 case llvm::Triple::mipsel: 7095 switch (os) { 7096 case llvm::Triple::Linux: 7097 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7098 case llvm::Triple::RTEMS: 7099 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7100 case llvm::Triple::FreeBSD: 7101 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7102 case llvm::Triple::NetBSD: 7103 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7104 case llvm::Triple::NaCl: 7105 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7106 default: 7107 return new Mips32ELTargetInfo(Triple); 7108 } 7109 7110 case llvm::Triple::mips64: 7111 switch (os) { 7112 case llvm::Triple::Linux: 7113 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7114 case llvm::Triple::RTEMS: 7115 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7116 case llvm::Triple::FreeBSD: 7117 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7118 case llvm::Triple::NetBSD: 7119 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7120 case llvm::Triple::OpenBSD: 7121 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7122 default: 7123 return new Mips64EBTargetInfo(Triple); 7124 } 7125 7126 case llvm::Triple::mips64el: 7127 switch (os) { 7128 case llvm::Triple::Linux: 7129 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7130 case llvm::Triple::RTEMS: 7131 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7132 case llvm::Triple::FreeBSD: 7133 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7134 case llvm::Triple::NetBSD: 7135 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7136 case llvm::Triple::OpenBSD: 7137 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7138 default: 7139 return new Mips64ELTargetInfo(Triple); 7140 } 7141 7142 case llvm::Triple::le32: 7143 switch (os) { 7144 case llvm::Triple::NaCl: 7145 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7146 default: 7147 return nullptr; 7148 } 7149 7150 case llvm::Triple::le64: 7151 return new Le64TargetInfo(Triple); 7152 7153 case llvm::Triple::ppc: 7154 if (Triple.isOSDarwin()) 7155 return new DarwinPPC32TargetInfo(Triple); 7156 switch (os) { 7157 case llvm::Triple::Linux: 7158 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7159 case llvm::Triple::FreeBSD: 7160 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7161 case llvm::Triple::NetBSD: 7162 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7163 case llvm::Triple::OpenBSD: 7164 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7165 case llvm::Triple::RTEMS: 7166 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7167 default: 7168 return new PPC32TargetInfo(Triple); 7169 } 7170 7171 case llvm::Triple::ppc64: 7172 if (Triple.isOSDarwin()) 7173 return new DarwinPPC64TargetInfo(Triple); 7174 switch (os) { 7175 case llvm::Triple::Linux: 7176 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7177 case llvm::Triple::Lv2: 7178 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7179 case llvm::Triple::FreeBSD: 7180 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7181 case llvm::Triple::NetBSD: 7182 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7183 default: 7184 return new PPC64TargetInfo(Triple); 7185 } 7186 7187 case llvm::Triple::ppc64le: 7188 switch (os) { 7189 case llvm::Triple::Linux: 7190 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7191 case llvm::Triple::NetBSD: 7192 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7193 default: 7194 return new PPC64TargetInfo(Triple); 7195 } 7196 7197 case llvm::Triple::nvptx: 7198 return new NVPTX32TargetInfo(Triple); 7199 case llvm::Triple::nvptx64: 7200 return new NVPTX64TargetInfo(Triple); 7201 7202 case llvm::Triple::amdgcn: 7203 case llvm::Triple::r600: 7204 return new AMDGPUTargetInfo(Triple); 7205 7206 case llvm::Triple::sparc: 7207 switch (os) { 7208 case llvm::Triple::Linux: 7209 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7210 case llvm::Triple::Solaris: 7211 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7212 case llvm::Triple::NetBSD: 7213 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7214 case llvm::Triple::OpenBSD: 7215 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7216 case llvm::Triple::RTEMS: 7217 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7218 default: 7219 return new SparcV8TargetInfo(Triple); 7220 } 7221 7222 // The 'sparcel' architecture copies all the above cases except for Solaris. 7223 case llvm::Triple::sparcel: 7224 switch (os) { 7225 case llvm::Triple::Linux: 7226 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7227 case llvm::Triple::NetBSD: 7228 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7229 case llvm::Triple::OpenBSD: 7230 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7231 case llvm::Triple::RTEMS: 7232 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7233 default: 7234 return new SparcV8elTargetInfo(Triple); 7235 } 7236 7237 case llvm::Triple::sparcv9: 7238 switch (os) { 7239 case llvm::Triple::Linux: 7240 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7241 case llvm::Triple::Solaris: 7242 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7243 case llvm::Triple::NetBSD: 7244 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7245 case llvm::Triple::OpenBSD: 7246 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7247 case llvm::Triple::FreeBSD: 7248 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7249 default: 7250 return new SparcV9TargetInfo(Triple); 7251 } 7252 7253 case llvm::Triple::systemz: 7254 switch (os) { 7255 case llvm::Triple::Linux: 7256 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7257 default: 7258 return new SystemZTargetInfo(Triple); 7259 } 7260 7261 case llvm::Triple::tce: 7262 return new TCETargetInfo(Triple); 7263 7264 case llvm::Triple::x86: 7265 if (Triple.isOSDarwin()) 7266 return new DarwinI386TargetInfo(Triple); 7267 7268 switch (os) { 7269 case llvm::Triple::CloudABI: 7270 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7271 case llvm::Triple::Linux: { 7272 switch (Triple.getEnvironment()) { 7273 default: 7274 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7275 case llvm::Triple::Android: 7276 return new AndroidX86_32TargetInfo(Triple); 7277 } 7278 } 7279 case llvm::Triple::DragonFly: 7280 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7281 case llvm::Triple::NetBSD: 7282 return new NetBSDI386TargetInfo(Triple); 7283 case llvm::Triple::OpenBSD: 7284 return new OpenBSDI386TargetInfo(Triple); 7285 case llvm::Triple::Bitrig: 7286 return new BitrigI386TargetInfo(Triple); 7287 case llvm::Triple::FreeBSD: 7288 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7289 case llvm::Triple::KFreeBSD: 7290 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7291 case llvm::Triple::Minix: 7292 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7293 case llvm::Triple::Solaris: 7294 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7295 case llvm::Triple::Win32: { 7296 switch (Triple.getEnvironment()) { 7297 default: 7298 return new X86_32TargetInfo(Triple); 7299 case llvm::Triple::Cygnus: 7300 return new CygwinX86_32TargetInfo(Triple); 7301 case llvm::Triple::GNU: 7302 return new MinGWX86_32TargetInfo(Triple); 7303 case llvm::Triple::Itanium: 7304 case llvm::Triple::MSVC: 7305 return new MicrosoftX86_32TargetInfo(Triple); 7306 } 7307 } 7308 case llvm::Triple::Haiku: 7309 return new HaikuX86_32TargetInfo(Triple); 7310 case llvm::Triple::RTEMS: 7311 return new RTEMSX86_32TargetInfo(Triple); 7312 case llvm::Triple::NaCl: 7313 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7314 default: 7315 return new X86_32TargetInfo(Triple); 7316 } 7317 7318 case llvm::Triple::x86_64: 7319 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7320 return new DarwinX86_64TargetInfo(Triple); 7321 7322 switch (os) { 7323 case llvm::Triple::CloudABI: 7324 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7325 case llvm::Triple::Linux: { 7326 switch (Triple.getEnvironment()) { 7327 default: 7328 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7329 case llvm::Triple::Android: 7330 return new AndroidX86_64TargetInfo(Triple); 7331 } 7332 } 7333 case llvm::Triple::DragonFly: 7334 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7335 case llvm::Triple::NetBSD: 7336 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7337 case llvm::Triple::OpenBSD: 7338 return new OpenBSDX86_64TargetInfo(Triple); 7339 case llvm::Triple::Bitrig: 7340 return new BitrigX86_64TargetInfo(Triple); 7341 case llvm::Triple::FreeBSD: 7342 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7343 case llvm::Triple::KFreeBSD: 7344 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7345 case llvm::Triple::Solaris: 7346 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7347 case llvm::Triple::Win32: { 7348 switch (Triple.getEnvironment()) { 7349 default: 7350 return new X86_64TargetInfo(Triple); 7351 case llvm::Triple::GNU: 7352 return new MinGWX86_64TargetInfo(Triple); 7353 case llvm::Triple::MSVC: 7354 return new MicrosoftX86_64TargetInfo(Triple); 7355 } 7356 } 7357 case llvm::Triple::NaCl: 7358 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7359 case llvm::Triple::PS4: 7360 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7361 default: 7362 return new X86_64TargetInfo(Triple); 7363 } 7364 7365 case llvm::Triple::spir: { 7366 if (Triple.getOS() != llvm::Triple::UnknownOS || 7367 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7368 return nullptr; 7369 return new SPIR32TargetInfo(Triple); 7370 } 7371 case llvm::Triple::spir64: { 7372 if (Triple.getOS() != llvm::Triple::UnknownOS || 7373 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7374 return nullptr; 7375 return new SPIR64TargetInfo(Triple); 7376 } 7377 } 7378 } 7379 7380 /// CreateTargetInfo - Return the target info object for the specified target 7381 /// triple. 7382 TargetInfo * 7383 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7384 const std::shared_ptr<TargetOptions> &Opts) { 7385 llvm::Triple Triple(Opts->Triple); 7386 7387 // Construct the target 7388 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7389 if (!Target) { 7390 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7391 return nullptr; 7392 } 7393 Target->TargetOpts = Opts; 7394 7395 // Set the target CPU if specified. 7396 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7397 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7398 return nullptr; 7399 } 7400 7401 // Set the target ABI if specified. 7402 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7403 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7404 return nullptr; 7405 } 7406 7407 // Set the fp math unit. 7408 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7409 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7410 return nullptr; 7411 } 7412 7413 // Compute the default target features, we need the target to handle this 7414 // because features may have dependencies on one another. 7415 llvm::StringMap<bool> Features; 7416 Target->getDefaultFeatures(Features); 7417 7418 // Apply the user specified deltas. 7419 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7420 I < N; ++I) { 7421 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7422 // Apply the feature via the target. 7423 bool Enabled = Name[0] == '+'; 7424 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7425 } 7426 7427 // Add the features to the compile options. 7428 // 7429 // FIXME: If we are completely confident that we have the right set, we only 7430 // need to pass the minuses. 7431 Opts->Features.clear(); 7432 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7433 ie = Features.end(); it != ie; ++it) 7434 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7435 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7436 return nullptr; 7437 7438 return Target.release(); 7439 } 7440