1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("__STDC_NO_THREADS__"); 121 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 122 // AddressSanitizer doesn't play well with source fortification, which is on 123 // by default on Darwin. 124 if (Opts.Sanitize.has(SanitizerKind::Address)) 125 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 126 127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 128 if (!Opts.ObjC1) { 129 // __weak is always defined, for use in blocks and with objc pointers. 130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 131 Builder.defineMacro("__strong", ""); 132 Builder.defineMacro("__unsafe_unretained", ""); 133 } 134 135 if (Opts.Static) 136 Builder.defineMacro("__STATIC__"); 137 else 138 Builder.defineMacro("__DYNAMIC__"); 139 140 if (Opts.POSIXThreads) 141 Builder.defineMacro("_REENTRANT"); 142 143 // Get the platform type and version number from the triple. 144 unsigned Maj, Min, Rev; 145 if (Triple.isMacOSX()) { 146 Triple.getMacOSXVersion(Maj, Min, Rev); 147 PlatformName = "macos"; 148 } else { 149 Triple.getOSVersion(Maj, Min, Rev); 150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 151 } 152 153 // If -target arch-pc-win32-macho option specified, we're 154 // generating code for Win32 ABI. No need to emit 155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 156 if (PlatformName == "win32") { 157 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 158 return; 159 } 160 161 // Set the appropriate OS version define. 162 if (Triple.isiOS()) { 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[7]; 165 if (Maj < 10) { 166 Str[0] = '0' + Maj; 167 Str[1] = '0' + (Min / 10); 168 Str[2] = '0' + (Min % 10); 169 Str[3] = '0' + (Rev / 10); 170 Str[4] = '0' + (Rev % 10); 171 Str[5] = '\0'; 172 } else { 173 // Handle versions >= 10. 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + (Min / 10); 177 Str[3] = '0' + (Min % 10); 178 Str[4] = '0' + (Rev / 10); 179 Str[5] = '0' + (Rev % 10); 180 Str[6] = '\0'; 181 } 182 if (Triple.isTvOS()) 183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 184 else 185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 186 Str); 187 188 } else if (Triple.isWatchOS()) { 189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[6]; 191 Str[0] = '0' + Maj; 192 Str[1] = '0' + (Min / 10); 193 Str[2] = '0' + (Min % 10); 194 Str[3] = '0' + (Rev / 10); 195 Str[4] = '0' + (Rev % 10); 196 Str[5] = '\0'; 197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 198 } else if (Triple.isMacOSX()) { 199 // Note that the Driver allows versions which aren't representable in the 200 // define (because we only get a single digit for the minor and micro 201 // revision numbers). So, we limit them to the maximum representable 202 // version. 203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 204 char Str[7]; 205 if (Maj < 10 || (Maj == 10 && Min < 10)) { 206 Str[0] = '0' + (Maj / 10); 207 Str[1] = '0' + (Maj % 10); 208 Str[2] = '0' + std::min(Min, 9U); 209 Str[3] = '0' + std::min(Rev, 9U); 210 Str[4] = '\0'; 211 } else { 212 // Handle versions > 10.9. 213 Str[0] = '0' + (Maj / 10); 214 Str[1] = '0' + (Maj % 10); 215 Str[2] = '0' + (Min / 10); 216 Str[3] = '0' + (Min % 10); 217 Str[4] = '0' + (Rev / 10); 218 Str[5] = '0' + (Rev % 10); 219 Str[6] = '\0'; 220 } 221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 222 } 223 224 // Tell users about the kernel if there is one. 225 if (Triple.isOSDarwin()) 226 Builder.defineMacro("__MACH__"); 227 228 // The Watch ABI uses Dwarf EH. 229 if(Triple.isWatchABI()) 230 Builder.defineMacro("__ARM_DWARF_EH__"); 231 232 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 233 } 234 235 template<typename Target> 236 class DarwinTargetInfo : public OSTargetInfo<Target> { 237 protected: 238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 239 MacroBuilder &Builder) const override { 240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 241 this->PlatformMinVersion); 242 } 243 244 public: 245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 246 : OSTargetInfo<Target>(Triple, Opts) { 247 // By default, no TLS, and we whitelist permitted architecture/OS 248 // combinations. 249 this->TLSSupported = false; 250 251 if (Triple.isMacOSX()) 252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 253 else if (Triple.isiOS()) { 254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 255 if (Triple.getArch() == llvm::Triple::x86_64 || 256 Triple.getArch() == llvm::Triple::aarch64) 257 this->TLSSupported = !Triple.isOSVersionLT(8); 258 else if (Triple.getArch() == llvm::Triple::x86 || 259 Triple.getArch() == llvm::Triple::arm || 260 Triple.getArch() == llvm::Triple::thumb) 261 this->TLSSupported = !Triple.isOSVersionLT(9); 262 } else if (Triple.isWatchOS()) 263 this->TLSSupported = !Triple.isOSVersionLT(2); 264 265 this->MCountName = "\01mcount"; 266 } 267 268 std::string isValidSectionSpecifier(StringRef SR) const override { 269 // Let MCSectionMachO validate this. 270 StringRef Segment, Section; 271 unsigned TAA, StubSize; 272 bool HasTAA; 273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 274 TAA, HasTAA, StubSize); 275 } 276 277 const char *getStaticInitSectionSpecifier() const override { 278 // FIXME: We should return 0 when building kexts. 279 return "__TEXT,__StaticInit,regular,pure_instructions"; 280 } 281 282 /// Darwin does not support protected visibility. Darwin's "default" 283 /// is very similar to ELF's "protected"; Darwin requires a "weak" 284 /// attribute on declarations that can be dynamically replaced. 285 bool hasProtectedVisibility() const override { 286 return false; 287 } 288 289 unsigned getExnObjectAlignment() const override { 290 // The alignment of an exception object is 8-bytes for darwin since 291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 292 // and therefore doesn't guarantee 16-byte alignment. 293 return 64; 294 } 295 }; 296 297 298 // DragonFlyBSD Target 299 template<typename Target> 300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 301 protected: 302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 303 MacroBuilder &Builder) const override { 304 // DragonFly defines; list based off of gcc output 305 Builder.defineMacro("__DragonFly__"); 306 Builder.defineMacro("__DragonFly_cc_version", "100001"); 307 Builder.defineMacro("__ELF__"); 308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 309 Builder.defineMacro("__tune_i386__"); 310 DefineStd(Builder, "unix", Opts); 311 } 312 public: 313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 314 : OSTargetInfo<Target>(Triple, Opts) { 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 } 322 } 323 }; 324 325 #ifndef FREEBSD_CC_VERSION 326 #define FREEBSD_CC_VERSION 0U 327 #endif 328 329 // FreeBSD Target 330 template<typename Target> 331 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // FreeBSD defines; list based off of gcc output 336 337 unsigned Release = Triple.getOSMajorVersion(); 338 if (Release == 0U) 339 Release = 8U; 340 unsigned CCVersion = FREEBSD_CC_VERSION; 341 if (CCVersion == 0U) 342 CCVersion = Release * 100000U + 1U; 343 344 Builder.defineMacro("__FreeBSD__", Twine(Release)); 345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 347 DefineStd(Builder, "unix", Opts); 348 Builder.defineMacro("__ELF__"); 349 350 // On FreeBSD, wchar_t contains the number of the code point as 351 // used by the character set of the locale. These character sets are 352 // not necessarily a superset of ASCII. 353 // 354 // FIXME: This is wrong; the macro refers to the numerical values 355 // of wchar_t *literals*, which are not locale-dependent. However, 356 // FreeBSD systems apparently depend on us getting this wrong, and 357 // setting this to 1 is conforming even if all the basic source 358 // character literals have the same encoding as char and wchar_t. 359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 360 } 361 public: 362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : OSTargetInfo<Target>(Triple, Opts) { 364 switch (Triple.getArch()) { 365 default: 366 case llvm::Triple::x86: 367 case llvm::Triple::x86_64: 368 this->MCountName = ".mcount"; 369 break; 370 case llvm::Triple::mips: 371 case llvm::Triple::mipsel: 372 case llvm::Triple::ppc: 373 case llvm::Triple::ppc64: 374 case llvm::Triple::ppc64le: 375 this->MCountName = "_mcount"; 376 break; 377 case llvm::Triple::arm: 378 this->MCountName = "__mcount"; 379 break; 380 } 381 } 382 }; 383 384 // GNU/kFreeBSD Target 385 template<typename Target> 386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // GNU/kFreeBSD defines; list based off of gcc output 391 392 DefineStd(Builder, "unix", Opts); 393 Builder.defineMacro("__FreeBSD_kernel__"); 394 Builder.defineMacro("__GLIBC__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 403 : OSTargetInfo<Target>(Triple, Opts) {} 404 }; 405 406 // Haiku Target 407 template<typename Target> 408 class HaikuTargetInfo : public OSTargetInfo<Target> { 409 protected: 410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 411 MacroBuilder &Builder) const override { 412 // Haiku defines; list based off of gcc output 413 Builder.defineMacro("__HAIKU__"); 414 Builder.defineMacro("__ELF__"); 415 DefineStd(Builder, "unix", Opts); 416 } 417 public: 418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 419 : OSTargetInfo<Target>(Triple, Opts) { 420 this->SizeType = TargetInfo::UnsignedLong; 421 this->IntPtrType = TargetInfo::SignedLong; 422 this->PtrDiffType = TargetInfo::SignedLong; 423 this->ProcessIDType = TargetInfo::SignedLong; 424 this->TLSSupported = false; 425 426 } 427 }; 428 429 // Minix Target 430 template<typename Target> 431 class MinixTargetInfo : public OSTargetInfo<Target> { 432 protected: 433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 434 MacroBuilder &Builder) const override { 435 // Minix defines 436 437 Builder.defineMacro("__minix", "3"); 438 Builder.defineMacro("_EM_WSIZE", "4"); 439 Builder.defineMacro("_EM_PSIZE", "4"); 440 Builder.defineMacro("_EM_SSIZE", "2"); 441 Builder.defineMacro("_EM_LSIZE", "4"); 442 Builder.defineMacro("_EM_FSIZE", "4"); 443 Builder.defineMacro("_EM_DSIZE", "8"); 444 Builder.defineMacro("__ELF__"); 445 DefineStd(Builder, "unix", Opts); 446 } 447 public: 448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 449 : OSTargetInfo<Target>(Triple, Opts) {} 450 }; 451 452 // Linux target 453 template<typename Target> 454 class LinuxTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // Linux defines; list based off of gcc output 459 DefineStd(Builder, "unix", Opts); 460 DefineStd(Builder, "linux", Opts); 461 Builder.defineMacro("__gnu_linux__"); 462 Builder.defineMacro("__ELF__"); 463 if (Triple.isAndroid()) { 464 Builder.defineMacro("__ANDROID__", "1"); 465 unsigned Maj, Min, Rev; 466 Triple.getEnvironmentVersion(Maj, Min, Rev); 467 this->PlatformName = "android"; 468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 469 if (Maj) 470 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 471 } 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 if (Opts.CPlusPlus) 475 Builder.defineMacro("_GNU_SOURCE"); 476 if (this->HasFloat128) 477 Builder.defineMacro("__FLOAT128__"); 478 } 479 public: 480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 481 : OSTargetInfo<Target>(Triple, Opts) { 482 this->WIntType = TargetInfo::UnsignedInt; 483 484 switch (Triple.getArch()) { 485 default: 486 break; 487 case llvm::Triple::ppc: 488 case llvm::Triple::ppc64: 489 case llvm::Triple::ppc64le: 490 this->MCountName = "_mcount"; 491 break; 492 case llvm::Triple::x86: 493 case llvm::Triple::x86_64: 494 case llvm::Triple::systemz: 495 this->HasFloat128 = true; 496 break; 497 } 498 } 499 500 const char *getStaticInitSectionSpecifier() const override { 501 return ".text.startup"; 502 } 503 }; 504 505 // NetBSD Target 506 template<typename Target> 507 class NetBSDTargetInfo : public OSTargetInfo<Target> { 508 protected: 509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 510 MacroBuilder &Builder) const override { 511 // NetBSD defines; list based off of gcc output 512 Builder.defineMacro("__NetBSD__"); 513 Builder.defineMacro("__unix__"); 514 Builder.defineMacro("__ELF__"); 515 if (Opts.POSIXThreads) 516 Builder.defineMacro("_REENTRANT"); 517 518 switch (Triple.getArch()) { 519 default: 520 break; 521 case llvm::Triple::arm: 522 case llvm::Triple::armeb: 523 case llvm::Triple::thumb: 524 case llvm::Triple::thumbeb: 525 Builder.defineMacro("__ARM_DWARF_EH__"); 526 break; 527 } 528 } 529 public: 530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 531 : OSTargetInfo<Target>(Triple, Opts) { 532 this->MCountName = "_mcount"; 533 } 534 }; 535 536 // OpenBSD Target 537 template<typename Target> 538 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 539 protected: 540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 541 MacroBuilder &Builder) const override { 542 // OpenBSD defines; list based off of gcc output 543 544 Builder.defineMacro("__OpenBSD__"); 545 DefineStd(Builder, "unix", Opts); 546 Builder.defineMacro("__ELF__"); 547 if (Opts.POSIXThreads) 548 Builder.defineMacro("_REENTRANT"); 549 if (this->HasFloat128) 550 Builder.defineMacro("__FLOAT128__"); 551 } 552 public: 553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 554 : OSTargetInfo<Target>(Triple, Opts) { 555 this->TLSSupported = false; 556 557 switch (Triple.getArch()) { 558 case llvm::Triple::x86: 559 case llvm::Triple::x86_64: 560 this->HasFloat128 = true; 561 // FALLTHROUGH 562 default: 563 this->MCountName = "__mcount"; 564 break; 565 case llvm::Triple::mips64: 566 case llvm::Triple::mips64el: 567 case llvm::Triple::ppc: 568 case llvm::Triple::sparcv9: 569 this->MCountName = "_mcount"; 570 break; 571 } 572 } 573 }; 574 575 // Bitrig Target 576 template<typename Target> 577 class BitrigTargetInfo : public OSTargetInfo<Target> { 578 protected: 579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const override { 581 // Bitrig defines; list based off of gcc output 582 583 Builder.defineMacro("__Bitrig__"); 584 DefineStd(Builder, "unix", Opts); 585 Builder.defineMacro("__ELF__"); 586 if (Opts.POSIXThreads) 587 Builder.defineMacro("_REENTRANT"); 588 589 switch (Triple.getArch()) { 590 default: 591 break; 592 case llvm::Triple::arm: 593 case llvm::Triple::armeb: 594 case llvm::Triple::thumb: 595 case llvm::Triple::thumbeb: 596 Builder.defineMacro("__ARM_DWARF_EH__"); 597 break; 598 } 599 } 600 public: 601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->MCountName = "__mcount"; 604 } 605 }; 606 607 // PSP Target 608 template<typename Target> 609 class PSPTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 // PSP defines; list based on the output of the pspdev gcc toolchain. 614 Builder.defineMacro("PSP"); 615 Builder.defineMacro("_PSP"); 616 Builder.defineMacro("__psp__"); 617 Builder.defineMacro("__ELF__"); 618 } 619 public: 620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 621 }; 622 623 // PS3 PPU Target 624 template<typename Target> 625 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 626 protected: 627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 628 MacroBuilder &Builder) const override { 629 // PS3 PPU defines. 630 Builder.defineMacro("__PPC__"); 631 Builder.defineMacro("__PPU__"); 632 Builder.defineMacro("__CELLOS_LV2__"); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__LP32__"); 635 Builder.defineMacro("_ARCH_PPC64"); 636 Builder.defineMacro("__powerpc64__"); 637 } 638 public: 639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 640 : OSTargetInfo<Target>(Triple, Opts) { 641 this->LongWidth = this->LongAlign = 32; 642 this->PointerWidth = this->PointerAlign = 32; 643 this->IntMaxType = TargetInfo::SignedLongLong; 644 this->Int64Type = TargetInfo::SignedLongLong; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 647 } 648 }; 649 650 template <typename Target> 651 class PS4OSTargetInfo : public OSTargetInfo<Target> { 652 protected: 653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 654 MacroBuilder &Builder) const override { 655 Builder.defineMacro("__FreeBSD__", "9"); 656 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 658 DefineStd(Builder, "unix", Opts); 659 Builder.defineMacro("__ELF__"); 660 Builder.defineMacro("__ORBIS__"); 661 } 662 public: 663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 664 : OSTargetInfo<Target>(Triple, Opts) { 665 this->WCharType = this->UnsignedShort; 666 667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 668 this->MaxTLSAlign = 256; 669 670 // On PS4, do not honor explicit bit field alignment, 671 // as in "__attribute__((aligned(2))) int b : 1;". 672 this->UseExplicitBitFieldAlignment = false; 673 674 switch (Triple.getArch()) { 675 default: 676 case llvm::Triple::x86_64: 677 this->MCountName = ".mcount"; 678 break; 679 } 680 } 681 }; 682 683 // Solaris target 684 template<typename Target> 685 class SolarisTargetInfo : public OSTargetInfo<Target> { 686 protected: 687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 688 MacroBuilder &Builder) const override { 689 DefineStd(Builder, "sun", Opts); 690 DefineStd(Builder, "unix", Opts); 691 Builder.defineMacro("__ELF__"); 692 Builder.defineMacro("__svr4__"); 693 Builder.defineMacro("__SVR4"); 694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 695 // newer, but to 500 for everything else. feature_test.h has a check to 696 // ensure that you are not using C99 with an old version of X/Open or C89 697 // with a new version. 698 if (Opts.C99) 699 Builder.defineMacro("_XOPEN_SOURCE", "600"); 700 else 701 Builder.defineMacro("_XOPEN_SOURCE", "500"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("__C99FEATURES__"); 704 Builder.defineMacro("_LARGEFILE_SOURCE"); 705 Builder.defineMacro("_LARGEFILE64_SOURCE"); 706 Builder.defineMacro("__EXTENSIONS__"); 707 Builder.defineMacro("_REENTRANT"); 708 } 709 public: 710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 711 : OSTargetInfo<Target>(Triple, Opts) { 712 this->WCharType = this->SignedInt; 713 // FIXME: WIntType should be SignedLong 714 } 715 }; 716 717 // Windows target 718 template<typename Target> 719 class WindowsTargetInfo : public OSTargetInfo<Target> { 720 protected: 721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 722 MacroBuilder &Builder) const override { 723 Builder.defineMacro("_WIN32"); 724 } 725 void getVisualStudioDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const { 727 if (Opts.CPlusPlus) { 728 if (Opts.RTTIData) 729 Builder.defineMacro("_CPPRTTI"); 730 731 if (Opts.CXXExceptions) 732 Builder.defineMacro("_CPPUNWIND"); 733 } 734 735 if (Opts.Bool) 736 Builder.defineMacro("__BOOL_DEFINED"); 737 738 if (!Opts.CharIsSigned) 739 Builder.defineMacro("_CHAR_UNSIGNED"); 740 741 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 742 // but it works for now. 743 if (Opts.POSIXThreads) 744 Builder.defineMacro("_MT"); 745 746 if (Opts.MSCompatibilityVersion) { 747 Builder.defineMacro("_MSC_VER", 748 Twine(Opts.MSCompatibilityVersion / 100000)); 749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 750 // FIXME We cannot encode the revision information into 32-bits 751 Builder.defineMacro("_MSC_BUILD", Twine(1)); 752 753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 755 756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 757 if (Opts.CPlusPlus1z) 758 Builder.defineMacro("_MSVC_LANG", "201403L"); 759 else if (Opts.CPlusPlus14) 760 Builder.defineMacro("_MSVC_LANG", "201402L"); 761 } 762 } 763 764 if (Opts.MicrosoftExt) { 765 Builder.defineMacro("_MSC_EXTENSIONS"); 766 767 if (Opts.CPlusPlus11) { 768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 771 } 772 } 773 774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 775 } 776 777 public: 778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 779 : OSTargetInfo<Target>(Triple, Opts) {} 780 }; 781 782 template <typename Target> 783 class NaClTargetInfo : public OSTargetInfo<Target> { 784 protected: 785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 786 MacroBuilder &Builder) const override { 787 if (Opts.POSIXThreads) 788 Builder.defineMacro("_REENTRANT"); 789 if (Opts.CPlusPlus) 790 Builder.defineMacro("_GNU_SOURCE"); 791 792 DefineStd(Builder, "unix", Opts); 793 Builder.defineMacro("__ELF__"); 794 Builder.defineMacro("__native_client__"); 795 } 796 797 public: 798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 799 : OSTargetInfo<Target>(Triple, Opts) { 800 this->LongAlign = 32; 801 this->LongWidth = 32; 802 this->PointerAlign = 32; 803 this->PointerWidth = 32; 804 this->IntMaxType = TargetInfo::SignedLongLong; 805 this->Int64Type = TargetInfo::SignedLongLong; 806 this->DoubleAlign = 64; 807 this->LongDoubleWidth = 64; 808 this->LongDoubleAlign = 64; 809 this->LongLongWidth = 64; 810 this->LongLongAlign = 64; 811 this->SizeType = TargetInfo::UnsignedInt; 812 this->PtrDiffType = TargetInfo::SignedInt; 813 this->IntPtrType = TargetInfo::SignedInt; 814 // RegParmMax is inherited from the underlying architecture. 815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 816 if (Triple.getArch() == llvm::Triple::arm) { 817 // Handled in ARM's setABI(). 818 } else if (Triple.getArch() == llvm::Triple::x86) { 819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 820 } else if (Triple.getArch() == llvm::Triple::x86_64) { 821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 822 } else if (Triple.getArch() == llvm::Triple::mipsel) { 823 // Handled on mips' setDataLayout. 824 } else { 825 assert(Triple.getArch() == llvm::Triple::le32); 826 this->resetDataLayout("e-p:32:32-i64:64"); 827 } 828 } 829 }; 830 831 // Fuchsia Target 832 template<typename Target> 833 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 834 protected: 835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 836 MacroBuilder &Builder) const override { 837 Builder.defineMacro("__Fuchsia__"); 838 Builder.defineMacro("__ELF__"); 839 if (Opts.POSIXThreads) 840 Builder.defineMacro("_REENTRANT"); 841 // Required by the libc++ locale support. 842 if (Opts.CPlusPlus) 843 Builder.defineMacro("_GNU_SOURCE"); 844 } 845 public: 846 FuchsiaTargetInfo(const llvm::Triple &Triple, 847 const TargetOptions &Opts) 848 : OSTargetInfo<Target>(Triple, Opts) { 849 this->MCountName = "__mcount"; 850 } 851 }; 852 853 // WebAssembly target 854 template <typename Target> 855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 857 MacroBuilder &Builder) const final { 858 // A common platform macro. 859 if (Opts.POSIXThreads) 860 Builder.defineMacro("_REENTRANT"); 861 // Follow g++ convention and predefine _GNU_SOURCE for C++. 862 if (Opts.CPlusPlus) 863 Builder.defineMacro("_GNU_SOURCE"); 864 } 865 866 // As an optimization, group static init code together in a section. 867 const char *getStaticInitSectionSpecifier() const final { 868 return ".text.__startup"; 869 } 870 871 public: 872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 873 const TargetOptions &Opts) 874 : OSTargetInfo<Target>(Triple, Opts) { 875 this->MCountName = "__mcount"; 876 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 877 } 878 }; 879 880 //===----------------------------------------------------------------------===// 881 // Specific target implementations. 882 //===----------------------------------------------------------------------===// 883 884 // PPC abstract base class 885 class PPCTargetInfo : public TargetInfo { 886 static const Builtin::Info BuiltinInfo[]; 887 static const char * const GCCRegNames[]; 888 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 889 std::string CPU; 890 891 // Target cpu features. 892 bool HasAltivec; 893 bool HasVSX; 894 bool HasP8Vector; 895 bool HasP8Crypto; 896 bool HasDirectMove; 897 bool HasQPX; 898 bool HasHTM; 899 bool HasBPERMD; 900 bool HasExtDiv; 901 bool HasP9Vector; 902 903 protected: 904 std::string ABI; 905 906 public: 907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 911 SuitableAlign = 128; 912 SimdDefaultAlign = 128; 913 LongDoubleWidth = LongDoubleAlign = 128; 914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 915 } 916 917 /// \brief Flags for architecture specific defines. 918 typedef enum { 919 ArchDefineNone = 0, 920 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 921 ArchDefinePpcgr = 1 << 1, 922 ArchDefinePpcsq = 1 << 2, 923 ArchDefine440 = 1 << 3, 924 ArchDefine603 = 1 << 4, 925 ArchDefine604 = 1 << 5, 926 ArchDefinePwr4 = 1 << 6, 927 ArchDefinePwr5 = 1 << 7, 928 ArchDefinePwr5x = 1 << 8, 929 ArchDefinePwr6 = 1 << 9, 930 ArchDefinePwr6x = 1 << 10, 931 ArchDefinePwr7 = 1 << 11, 932 ArchDefinePwr8 = 1 << 12, 933 ArchDefinePwr9 = 1 << 13, 934 ArchDefineA2 = 1 << 14, 935 ArchDefineA2q = 1 << 15 936 } ArchDefineTypes; 937 938 // Set the language option for altivec based on our value. 939 void adjust(LangOptions &Opts) override { 940 if (HasAltivec) 941 Opts.AltiVec = 1; 942 TargetInfo::adjust(Opts); 943 } 944 945 // Note: GCC recognizes the following additional cpus: 946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 948 // titan, rs64. 949 bool setCPU(const std::string &Name) override { 950 bool CPUKnown = llvm::StringSwitch<bool>(Name) 951 .Case("generic", true) 952 .Case("440", true) 953 .Case("450", true) 954 .Case("601", true) 955 .Case("602", true) 956 .Case("603", true) 957 .Case("603e", true) 958 .Case("603ev", true) 959 .Case("604", true) 960 .Case("604e", true) 961 .Case("620", true) 962 .Case("630", true) 963 .Case("g3", true) 964 .Case("7400", true) 965 .Case("g4", true) 966 .Case("7450", true) 967 .Case("g4+", true) 968 .Case("750", true) 969 .Case("970", true) 970 .Case("g5", true) 971 .Case("a2", true) 972 .Case("a2q", true) 973 .Case("e500mc", true) 974 .Case("e5500", true) 975 .Case("power3", true) 976 .Case("pwr3", true) 977 .Case("power4", true) 978 .Case("pwr4", true) 979 .Case("power5", true) 980 .Case("pwr5", true) 981 .Case("power5x", true) 982 .Case("pwr5x", true) 983 .Case("power6", true) 984 .Case("pwr6", true) 985 .Case("power6x", true) 986 .Case("pwr6x", true) 987 .Case("power7", true) 988 .Case("pwr7", true) 989 .Case("power8", true) 990 .Case("pwr8", true) 991 .Case("power9", true) 992 .Case("pwr9", true) 993 .Case("powerpc", true) 994 .Case("ppc", true) 995 .Case("powerpc64", true) 996 .Case("ppc64", true) 997 .Case("powerpc64le", true) 998 .Case("ppc64le", true) 999 .Default(false); 1000 1001 if (CPUKnown) 1002 CPU = Name; 1003 1004 return CPUKnown; 1005 } 1006 1007 1008 StringRef getABI() const override { return ABI; } 1009 1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1011 return llvm::makeArrayRef(BuiltinInfo, 1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1013 } 1014 1015 bool isCLZForZeroUndef() const override { return false; } 1016 1017 void getTargetDefines(const LangOptions &Opts, 1018 MacroBuilder &Builder) const override; 1019 1020 bool 1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1022 StringRef CPU, 1023 const std::vector<std::string> &FeaturesVec) const override; 1024 1025 bool handleTargetFeatures(std::vector<std::string> &Features, 1026 DiagnosticsEngine &Diags) override; 1027 bool hasFeature(StringRef Feature) const override; 1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1029 bool Enabled) const override; 1030 1031 ArrayRef<const char *> getGCCRegNames() const override; 1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1033 bool validateAsmConstraint(const char *&Name, 1034 TargetInfo::ConstraintInfo &Info) const override { 1035 switch (*Name) { 1036 default: return false; 1037 case 'O': // Zero 1038 break; 1039 case 'b': // Base register 1040 case 'f': // Floating point register 1041 Info.setAllowsRegister(); 1042 break; 1043 // FIXME: The following are added to allow parsing. 1044 // I just took a guess at what the actions should be. 1045 // Also, is more specific checking needed? I.e. specific registers? 1046 case 'd': // Floating point register (containing 64-bit value) 1047 case 'v': // Altivec vector register 1048 Info.setAllowsRegister(); 1049 break; 1050 case 'w': 1051 switch (Name[1]) { 1052 case 'd':// VSX vector register to hold vector double data 1053 case 'f':// VSX vector register to hold vector float data 1054 case 's':// VSX vector register to hold scalar float data 1055 case 'a':// Any VSX register 1056 case 'c':// An individual CR bit 1057 break; 1058 default: 1059 return false; 1060 } 1061 Info.setAllowsRegister(); 1062 Name++; // Skip over 'w'. 1063 break; 1064 case 'h': // `MQ', `CTR', or `LINK' register 1065 case 'q': // `MQ' register 1066 case 'c': // `CTR' register 1067 case 'l': // `LINK' register 1068 case 'x': // `CR' register (condition register) number 0 1069 case 'y': // `CR' register (condition register) 1070 case 'z': // `XER[CA]' carry bit (part of the XER register) 1071 Info.setAllowsRegister(); 1072 break; 1073 case 'I': // Signed 16-bit constant 1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1075 // (use `L' instead for SImode constants) 1076 case 'K': // Unsigned 16-bit constant 1077 case 'L': // Signed 16-bit constant shifted left 16 bits 1078 case 'M': // Constant larger than 31 1079 case 'N': // Exact power of 2 1080 case 'P': // Constant whose negation is a signed 16-bit constant 1081 case 'G': // Floating point constant that can be loaded into a 1082 // register with one instruction per word 1083 case 'H': // Integer/Floating point constant that can be loaded 1084 // into a register using three instructions 1085 break; 1086 case 'm': // Memory operand. Note that on PowerPC targets, m can 1087 // include addresses that update the base register. It 1088 // is therefore only safe to use `m' in an asm statement 1089 // if that asm statement accesses the operand exactly once. 1090 // The asm statement must also use `%U<opno>' as a 1091 // placeholder for the "update" flag in the corresponding 1092 // load or store instruction. For example: 1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1094 // is correct but: 1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1096 // is not. Use es rather than m if you don't want the base 1097 // register to be updated. 1098 case 'e': 1099 if (Name[1] != 's') 1100 return false; 1101 // es: A "stable" memory operand; that is, one which does not 1102 // include any automodification of the base register. Unlike 1103 // `m', this constraint can be used in asm statements that 1104 // might access the operand several times, or that might not 1105 // access it at all. 1106 Info.setAllowsMemory(); 1107 Name++; // Skip over 'e'. 1108 break; 1109 case 'Q': // Memory operand that is an offset from a register (it is 1110 // usually better to use `m' or `es' in asm statements) 1111 case 'Z': // Memory operand that is an indexed or indirect from a 1112 // register (it is usually better to use `m' or `es' in 1113 // asm statements) 1114 Info.setAllowsMemory(); 1115 Info.setAllowsRegister(); 1116 break; 1117 case 'R': // AIX TOC entry 1118 case 'a': // Address operand that is an indexed or indirect from a 1119 // register (`p' is preferable for asm statements) 1120 case 'S': // Constant suitable as a 64-bit mask operand 1121 case 'T': // Constant suitable as a 32-bit mask operand 1122 case 'U': // System V Release 4 small data area reference 1123 case 't': // AND masks that can be performed by two rldic{l, r} 1124 // instructions 1125 case 'W': // Vector constant that does not require memory 1126 case 'j': // Vector constant that is all zeros. 1127 break; 1128 // End FIXME. 1129 } 1130 return true; 1131 } 1132 std::string convertConstraint(const char *&Constraint) const override { 1133 std::string R; 1134 switch (*Constraint) { 1135 case 'e': 1136 case 'w': 1137 // Two-character constraint; add "^" hint for later parsing. 1138 R = std::string("^") + std::string(Constraint, 2); 1139 Constraint++; 1140 break; 1141 default: 1142 return TargetInfo::convertConstraint(Constraint); 1143 } 1144 return R; 1145 } 1146 const char *getClobbers() const override { 1147 return ""; 1148 } 1149 int getEHDataRegisterNumber(unsigned RegNo) const override { 1150 if (RegNo == 0) return 3; 1151 if (RegNo == 1) return 4; 1152 return -1; 1153 } 1154 1155 bool hasSjLjLowering() const override { 1156 return true; 1157 } 1158 1159 bool useFloat128ManglingForLongDouble() const override { 1160 return LongDoubleWidth == 128 && 1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1162 getTriple().isOSBinFormatELF(); 1163 } 1164 }; 1165 1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1167 #define BUILTIN(ID, TYPE, ATTRS) \ 1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1171 #include "clang/Basic/BuiltinsPPC.def" 1172 }; 1173 1174 /// handleTargetFeatures - Perform initialization based on the user 1175 /// configured set of features. 1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1177 DiagnosticsEngine &Diags) { 1178 for (const auto &Feature : Features) { 1179 if (Feature == "+altivec") { 1180 HasAltivec = true; 1181 } else if (Feature == "+vsx") { 1182 HasVSX = true; 1183 } else if (Feature == "+bpermd") { 1184 HasBPERMD = true; 1185 } else if (Feature == "+extdiv") { 1186 HasExtDiv = true; 1187 } else if (Feature == "+power8-vector") { 1188 HasP8Vector = true; 1189 } else if (Feature == "+crypto") { 1190 HasP8Crypto = true; 1191 } else if (Feature == "+direct-move") { 1192 HasDirectMove = true; 1193 } else if (Feature == "+qpx") { 1194 HasQPX = true; 1195 } else if (Feature == "+htm") { 1196 HasHTM = true; 1197 } else if (Feature == "+float128") { 1198 HasFloat128 = true; 1199 } else if (Feature == "+power9-vector") { 1200 HasP9Vector = true; 1201 } 1202 // TODO: Finish this list and add an assert that we've handled them 1203 // all. 1204 } 1205 1206 return true; 1207 } 1208 1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1210 /// #defines that are not tied to a specific subtarget. 1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1212 MacroBuilder &Builder) const { 1213 // Target identification. 1214 Builder.defineMacro("__ppc__"); 1215 Builder.defineMacro("__PPC__"); 1216 Builder.defineMacro("_ARCH_PPC"); 1217 Builder.defineMacro("__powerpc__"); 1218 Builder.defineMacro("__POWERPC__"); 1219 if (PointerWidth == 64) { 1220 Builder.defineMacro("_ARCH_PPC64"); 1221 Builder.defineMacro("__powerpc64__"); 1222 Builder.defineMacro("__ppc64__"); 1223 Builder.defineMacro("__PPC64__"); 1224 } 1225 1226 // Target properties. 1227 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1228 Builder.defineMacro("_LITTLE_ENDIAN"); 1229 } else { 1230 if (getTriple().getOS() != llvm::Triple::NetBSD && 1231 getTriple().getOS() != llvm::Triple::OpenBSD) 1232 Builder.defineMacro("_BIG_ENDIAN"); 1233 } 1234 1235 // ABI options. 1236 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1237 Builder.defineMacro("_CALL_ELF", "1"); 1238 if (ABI == "elfv2") 1239 Builder.defineMacro("_CALL_ELF", "2"); 1240 1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1242 // our suppport post-dates this and it should work on all 64-bit ppc linux 1243 // platforms. It is guaranteed to work on all elfv2 platforms. 1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1245 Builder.defineMacro("_CALL_LINUX", "1"); 1246 1247 // Subtarget options. 1248 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1250 1251 // FIXME: Should be controlled by command line option. 1252 if (LongDoubleWidth == 128) { 1253 Builder.defineMacro("__LONG_DOUBLE_128__"); 1254 Builder.defineMacro("__LONGDOUBLE128"); 1255 } 1256 1257 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1258 if (ABI == "elfv2" || 1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1261 1262 // CPU identification. 1263 ArchDefineTypes defs = 1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1265 .Case("440", ArchDefineName) 1266 .Case("450", ArchDefineName | ArchDefine440) 1267 .Case("601", ArchDefineName) 1268 .Case("602", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603", ArchDefineName | ArchDefinePpcgr) 1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1272 .Case("604", ArchDefineName | ArchDefinePpcgr) 1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1274 .Case("620", ArchDefineName | ArchDefinePpcgr) 1275 .Case("630", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1277 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1278 .Case("750", ArchDefineName | ArchDefinePpcgr) 1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1280 ArchDefinePpcsq) 1281 .Case("a2", ArchDefineA2) 1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1283 .Case("pwr3", ArchDefinePpcgr) 1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1286 ArchDefinePpcsq) 1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1288 ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1293 ArchDefinePpcsq) 1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1296 ArchDefinePpcgr | ArchDefinePpcsq) 1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("power3", ArchDefinePpcgr) 1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1307 ArchDefinePpcsq) 1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1309 ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1311 ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1314 ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1317 ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | 1319 ArchDefinePpcsq) 1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1321 ArchDefinePwr6 | ArchDefinePwr5x | 1322 ArchDefinePwr5 | ArchDefinePwr4 | 1323 ArchDefinePpcgr | ArchDefinePpcsq) 1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1325 ArchDefinePwr6x | ArchDefinePwr6 | 1326 ArchDefinePwr5x | ArchDefinePwr5 | 1327 ArchDefinePwr4 | ArchDefinePpcgr | 1328 ArchDefinePpcsq) 1329 // powerpc64le automatically defaults to at least power8. 1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1331 ArchDefinePwr6 | ArchDefinePwr5x | 1332 ArchDefinePwr5 | ArchDefinePwr4 | 1333 ArchDefinePpcgr | ArchDefinePpcsq) 1334 .Default(ArchDefineNone); 1335 1336 if (defs & ArchDefineName) 1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1338 if (defs & ArchDefinePpcgr) 1339 Builder.defineMacro("_ARCH_PPCGR"); 1340 if (defs & ArchDefinePpcsq) 1341 Builder.defineMacro("_ARCH_PPCSQ"); 1342 if (defs & ArchDefine440) 1343 Builder.defineMacro("_ARCH_440"); 1344 if (defs & ArchDefine603) 1345 Builder.defineMacro("_ARCH_603"); 1346 if (defs & ArchDefine604) 1347 Builder.defineMacro("_ARCH_604"); 1348 if (defs & ArchDefinePwr4) 1349 Builder.defineMacro("_ARCH_PWR4"); 1350 if (defs & ArchDefinePwr5) 1351 Builder.defineMacro("_ARCH_PWR5"); 1352 if (defs & ArchDefinePwr5x) 1353 Builder.defineMacro("_ARCH_PWR5X"); 1354 if (defs & ArchDefinePwr6) 1355 Builder.defineMacro("_ARCH_PWR6"); 1356 if (defs & ArchDefinePwr6x) 1357 Builder.defineMacro("_ARCH_PWR6X"); 1358 if (defs & ArchDefinePwr7) 1359 Builder.defineMacro("_ARCH_PWR7"); 1360 if (defs & ArchDefinePwr8) 1361 Builder.defineMacro("_ARCH_PWR8"); 1362 if (defs & ArchDefinePwr9) 1363 Builder.defineMacro("_ARCH_PWR9"); 1364 if (defs & ArchDefineA2) 1365 Builder.defineMacro("_ARCH_A2"); 1366 if (defs & ArchDefineA2q) { 1367 Builder.defineMacro("_ARCH_A2Q"); 1368 Builder.defineMacro("_ARCH_QP"); 1369 } 1370 1371 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1372 Builder.defineMacro("__bg__"); 1373 Builder.defineMacro("__THW_BLUEGENE__"); 1374 Builder.defineMacro("__bgq__"); 1375 Builder.defineMacro("__TOS_BGQ__"); 1376 } 1377 1378 if (HasAltivec) { 1379 Builder.defineMacro("__VEC__", "10206"); 1380 Builder.defineMacro("__ALTIVEC__"); 1381 } 1382 if (HasVSX) 1383 Builder.defineMacro("__VSX__"); 1384 if (HasP8Vector) 1385 Builder.defineMacro("__POWER8_VECTOR__"); 1386 if (HasP8Crypto) 1387 Builder.defineMacro("__CRYPTO__"); 1388 if (HasHTM) 1389 Builder.defineMacro("__HTM__"); 1390 if (HasFloat128) 1391 Builder.defineMacro("__FLOAT128__"); 1392 if (HasP9Vector) 1393 Builder.defineMacro("__POWER9_VECTOR__"); 1394 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1398 if (PointerWidth == 64) 1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1400 1401 // We have support for the bswap intrinsics so we can define this. 1402 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1403 1404 // FIXME: The following are not yet generated here by Clang, but are 1405 // generated by GCC: 1406 // 1407 // _SOFT_FLOAT_ 1408 // __RECIP_PRECISION__ 1409 // __APPLE_ALTIVEC__ 1410 // __RECIP__ 1411 // __RECIPF__ 1412 // __RSQRTE__ 1413 // __RSQRTEF__ 1414 // _SOFT_DOUBLE_ 1415 // __NO_LWSYNC__ 1416 // __CMODEL_MEDIUM__ 1417 // __CMODEL_LARGE__ 1418 // _CALL_SYSV 1419 // _CALL_DARWIN 1420 // __NO_FPRS__ 1421 } 1422 1423 // Handle explicit options being passed to the compiler here: if we've 1424 // explicitly turned off vsx and turned on any of: 1425 // - power8-vector 1426 // - direct-move 1427 // - float128 1428 // - power9-vector 1429 // then go ahead and error since the customer has expressed an incompatible 1430 // set of options. 1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1432 const std::vector<std::string> &FeaturesVec) { 1433 1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1435 FeaturesVec.end()) { 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1444 FeaturesVec.end()) { 1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1446 << "-mno-vsx"; 1447 return false; 1448 } 1449 1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1451 FeaturesVec.end()) { 1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1453 << "-mno-vsx"; 1454 return false; 1455 } 1456 1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1458 FeaturesVec.end()) { 1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1460 << "-mno-vsx"; 1461 return false; 1462 } 1463 } 1464 1465 return true; 1466 } 1467 1468 bool PPCTargetInfo::initFeatureMap( 1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1470 const std::vector<std::string> &FeaturesVec) const { 1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("7400", true) 1473 .Case("g4", true) 1474 .Case("7450", true) 1475 .Case("g4+", true) 1476 .Case("970", true) 1477 .Case("g5", true) 1478 .Case("pwr6", true) 1479 .Case("pwr7", true) 1480 .Case("pwr8", true) 1481 .Case("pwr9", true) 1482 .Case("ppc64", true) 1483 .Case("ppc64le", true) 1484 .Default(false); 1485 1486 Features["qpx"] = (CPU == "a2q"); 1487 Features["power9-vector"] = (CPU == "pwr9"); 1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("ppc64le", true) 1490 .Case("pwr9", true) 1491 .Case("pwr8", true) 1492 .Default(false); 1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1494 .Case("ppc64le", true) 1495 .Case("pwr9", true) 1496 .Case("pwr8", true) 1497 .Default(false); 1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1499 .Case("ppc64le", true) 1500 .Case("pwr9", true) 1501 .Case("pwr8", true) 1502 .Case("pwr7", true) 1503 .Default(false); 1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1505 .Case("ppc64le", true) 1506 .Case("pwr9", true) 1507 .Case("pwr8", true) 1508 .Case("pwr7", true) 1509 .Default(false); 1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Default(false); 1526 1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1528 return false; 1529 1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1531 } 1532 1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1534 return llvm::StringSwitch<bool>(Feature) 1535 .Case("powerpc", true) 1536 .Case("altivec", HasAltivec) 1537 .Case("vsx", HasVSX) 1538 .Case("power8-vector", HasP8Vector) 1539 .Case("crypto", HasP8Crypto) 1540 .Case("direct-move", HasDirectMove) 1541 .Case("qpx", HasQPX) 1542 .Case("htm", HasHTM) 1543 .Case("bpermd", HasBPERMD) 1544 .Case("extdiv", HasExtDiv) 1545 .Case("float128", HasFloat128) 1546 .Case("power9-vector", HasP9Vector) 1547 .Default(false); 1548 } 1549 1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1551 StringRef Name, bool Enabled) const { 1552 if (Enabled) { 1553 // If we're enabling any of the vsx based features then enable vsx and 1554 // altivec. We'll diagnose any problems later. 1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1556 .Case("vsx", true) 1557 .Case("direct-move", true) 1558 .Case("power8-vector", true) 1559 .Case("power9-vector", true) 1560 .Case("float128", true) 1561 .Default(false); 1562 if (FeatureHasVSX) 1563 Features["vsx"] = Features["altivec"] = true; 1564 if (Name == "power9-vector") 1565 Features["power8-vector"] = true; 1566 Features[Name] = true; 1567 } else { 1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1569 // features. 1570 if ((Name == "altivec") || (Name == "vsx")) 1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1572 Features["float128"] = Features["power9-vector"] = false; 1573 if (Name == "power8-vector") 1574 Features["power9-vector"] = false; 1575 Features[Name] = false; 1576 } 1577 } 1578 1579 const char * const PPCTargetInfo::GCCRegNames[] = { 1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1588 "mq", "lr", "ctr", "ap", 1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1590 "xer", 1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1595 "vrsave", "vscr", 1596 "spe_acc", "spefscr", 1597 "sfp" 1598 }; 1599 1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1601 return llvm::makeArrayRef(GCCRegNames); 1602 } 1603 1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1605 // While some of these aliases do map to different registers 1606 // they still share the same register name. 1607 { { "0" }, "r0" }, 1608 { { "1"}, "r1" }, 1609 { { "2" }, "r2" }, 1610 { { "3" }, "r3" }, 1611 { { "4" }, "r4" }, 1612 { { "5" }, "r5" }, 1613 { { "6" }, "r6" }, 1614 { { "7" }, "r7" }, 1615 { { "8" }, "r8" }, 1616 { { "9" }, "r9" }, 1617 { { "10" }, "r10" }, 1618 { { "11" }, "r11" }, 1619 { { "12" }, "r12" }, 1620 { { "13" }, "r13" }, 1621 { { "14" }, "r14" }, 1622 { { "15" }, "r15" }, 1623 { { "16" }, "r16" }, 1624 { { "17" }, "r17" }, 1625 { { "18" }, "r18" }, 1626 { { "19" }, "r19" }, 1627 { { "20" }, "r20" }, 1628 { { "21" }, "r21" }, 1629 { { "22" }, "r22" }, 1630 { { "23" }, "r23" }, 1631 { { "24" }, "r24" }, 1632 { { "25" }, "r25" }, 1633 { { "26" }, "r26" }, 1634 { { "27" }, "r27" }, 1635 { { "28" }, "r28" }, 1636 { { "29" }, "r29" }, 1637 { { "30" }, "r30" }, 1638 { { "31" }, "r31" }, 1639 { { "fr0" }, "f0" }, 1640 { { "fr1" }, "f1" }, 1641 { { "fr2" }, "f2" }, 1642 { { "fr3" }, "f3" }, 1643 { { "fr4" }, "f4" }, 1644 { { "fr5" }, "f5" }, 1645 { { "fr6" }, "f6" }, 1646 { { "fr7" }, "f7" }, 1647 { { "fr8" }, "f8" }, 1648 { { "fr9" }, "f9" }, 1649 { { "fr10" }, "f10" }, 1650 { { "fr11" }, "f11" }, 1651 { { "fr12" }, "f12" }, 1652 { { "fr13" }, "f13" }, 1653 { { "fr14" }, "f14" }, 1654 { { "fr15" }, "f15" }, 1655 { { "fr16" }, "f16" }, 1656 { { "fr17" }, "f17" }, 1657 { { "fr18" }, "f18" }, 1658 { { "fr19" }, "f19" }, 1659 { { "fr20" }, "f20" }, 1660 { { "fr21" }, "f21" }, 1661 { { "fr22" }, "f22" }, 1662 { { "fr23" }, "f23" }, 1663 { { "fr24" }, "f24" }, 1664 { { "fr25" }, "f25" }, 1665 { { "fr26" }, "f26" }, 1666 { { "fr27" }, "f27" }, 1667 { { "fr28" }, "f28" }, 1668 { { "fr29" }, "f29" }, 1669 { { "fr30" }, "f30" }, 1670 { { "fr31" }, "f31" }, 1671 { { "cc" }, "cr0" }, 1672 }; 1673 1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1675 return llvm::makeArrayRef(GCCRegAliases); 1676 } 1677 1678 class PPC32TargetInfo : public PPCTargetInfo { 1679 public: 1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1681 : PPCTargetInfo(Triple, Opts) { 1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::Linux: 1686 case llvm::Triple::FreeBSD: 1687 case llvm::Triple::NetBSD: 1688 SizeType = UnsignedInt; 1689 PtrDiffType = SignedInt; 1690 IntPtrType = SignedInt; 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1697 LongDoubleWidth = LongDoubleAlign = 64; 1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1699 } 1700 1701 // PPC32 supports atomics up to 4 bytes. 1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1703 } 1704 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 // This is the ELF definition, and is overridden by the Darwin sub-target 1707 return TargetInfo::PowerABIBuiltinVaList; 1708 } 1709 }; 1710 1711 // Note: ABI differences may eventually require us to have a separate 1712 // TargetInfo for little endian. 1713 class PPC64TargetInfo : public PPCTargetInfo { 1714 public: 1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : PPCTargetInfo(Triple, Opts) { 1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1718 IntMaxType = SignedLong; 1719 Int64Type = SignedLong; 1720 1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1722 resetDataLayout("e-m:e-i64:64-n32:64"); 1723 ABI = "elfv2"; 1724 } else { 1725 resetDataLayout("E-m:e-i64:64-n32:64"); 1726 ABI = "elfv1"; 1727 } 1728 1729 switch (getTriple().getOS()) { 1730 case llvm::Triple::FreeBSD: 1731 LongDoubleWidth = LongDoubleAlign = 64; 1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1733 break; 1734 case llvm::Triple::NetBSD: 1735 IntMaxType = SignedLongLong; 1736 Int64Type = SignedLongLong; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 // PPC64 supports atomics up to 8 bytes. 1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1744 } 1745 BuiltinVaListKind getBuiltinVaListKind() const override { 1746 return TargetInfo::CharPtrBuiltinVaList; 1747 } 1748 // PPC64 Linux-specific ABI options. 1749 bool setABI(const std::string &Name) override { 1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1751 ABI = Name; 1752 return true; 1753 } 1754 return false; 1755 } 1756 }; 1757 1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1759 public: 1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1762 HasAlignMac68kSupport = true; 1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1765 LongLongAlign = 32; 1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1767 } 1768 BuiltinVaListKind getBuiltinVaListKind() const override { 1769 return TargetInfo::CharPtrBuiltinVaList; 1770 } 1771 }; 1772 1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1774 public: 1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 resetDataLayout("E-m:o-i64:64-n32:64"); 1779 } 1780 }; 1781 1782 static const unsigned NVPTXAddrSpaceMap[] = { 1783 0, // Default 1784 1, // opencl_global 1785 3, // opencl_local 1786 4, // opencl_constant 1787 // FIXME: generic has to be added to the target 1788 0, // opencl_generic 1789 1, // cuda_device 1790 4, // cuda_constant 1791 3, // cuda_shared 1792 }; 1793 1794 class NVPTXTargetInfo : public TargetInfo { 1795 static const char *const GCCRegNames[]; 1796 static const Builtin::Info BuiltinInfo[]; 1797 CudaArch GPU; 1798 std::unique_ptr<TargetInfo> HostTarget; 1799 1800 public: 1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1802 unsigned TargetPointerWidth) 1803 : TargetInfo(Triple) { 1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1805 "NVPTX only supports 32- and 64-bit modes."); 1806 1807 TLSSupported = false; 1808 AddrSpaceMap = &NVPTXAddrSpaceMap; 1809 UseAddrSpaceMapMangling = true; 1810 1811 // Define available target features 1812 // These must be defined in sorted order! 1813 NoAsmVariants = true; 1814 GPU = CudaArch::SM_20; 1815 1816 if (TargetPointerWidth == 32) 1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1818 else 1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1820 1821 // If possible, get a TargetInfo for our host triple, so we can match its 1822 // types. 1823 llvm::Triple HostTriple(Opts.HostTriple); 1824 if (!HostTriple.isNVPTX()) 1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1826 1827 // If no host target, make some guesses about the data layout and return. 1828 if (!HostTarget) { 1829 LongWidth = LongAlign = TargetPointerWidth; 1830 PointerWidth = PointerAlign = TargetPointerWidth; 1831 switch (TargetPointerWidth) { 1832 case 32: 1833 SizeType = TargetInfo::UnsignedInt; 1834 PtrDiffType = TargetInfo::SignedInt; 1835 IntPtrType = TargetInfo::SignedInt; 1836 break; 1837 case 64: 1838 SizeType = TargetInfo::UnsignedLong; 1839 PtrDiffType = TargetInfo::SignedLong; 1840 IntPtrType = TargetInfo::SignedLong; 1841 break; 1842 default: 1843 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1844 } 1845 return; 1846 } 1847 1848 // Copy properties from host target. 1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1851 BoolWidth = HostTarget->getBoolWidth(); 1852 BoolAlign = HostTarget->getBoolAlign(); 1853 IntWidth = HostTarget->getIntWidth(); 1854 IntAlign = HostTarget->getIntAlign(); 1855 HalfWidth = HostTarget->getHalfWidth(); 1856 HalfAlign = HostTarget->getHalfAlign(); 1857 FloatWidth = HostTarget->getFloatWidth(); 1858 FloatAlign = HostTarget->getFloatAlign(); 1859 DoubleWidth = HostTarget->getDoubleWidth(); 1860 DoubleAlign = HostTarget->getDoubleAlign(); 1861 LongWidth = HostTarget->getLongWidth(); 1862 LongAlign = HostTarget->getLongAlign(); 1863 LongLongWidth = HostTarget->getLongLongWidth(); 1864 LongLongAlign = HostTarget->getLongLongAlign(); 1865 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1866 NewAlign = HostTarget->getNewAlign(); 1867 DefaultAlignForAttributeAligned = 1868 HostTarget->getDefaultAlignForAttributeAligned(); 1869 SizeType = HostTarget->getSizeType(); 1870 IntMaxType = HostTarget->getIntMaxType(); 1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1872 IntPtrType = HostTarget->getIntPtrType(); 1873 WCharType = HostTarget->getWCharType(); 1874 WIntType = HostTarget->getWIntType(); 1875 Char16Type = HostTarget->getChar16Type(); 1876 Char32Type = HostTarget->getChar32Type(); 1877 Int64Type = HostTarget->getInt64Type(); 1878 SigAtomicType = HostTarget->getSigAtomicType(); 1879 ProcessIDType = HostTarget->getProcessIDType(); 1880 1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1882 UseZeroLengthBitfieldAlignment = 1883 HostTarget->useZeroLengthBitfieldAlignment(); 1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1886 1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1888 // we need those macros to be identical on host and device, because (among 1889 // other things) they affect which standard library classes are defined, and 1890 // we need all classes to be defined on both the host and device. 1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1892 1893 // Properties intentionally not copied from host: 1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1895 // host/device boundary. 1896 // - SuitableAlign: Not visible across the host/device boundary, and may 1897 // correctly be different on host/device, e.g. if host has wider vector 1898 // types than device. 1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1900 // as its double type, but that's not necessarily true on the host. 1901 // TODO: nvcc emits a warning when using long double on device; we should 1902 // do the same. 1903 } 1904 void getTargetDefines(const LangOptions &Opts, 1905 MacroBuilder &Builder) const override { 1906 Builder.defineMacro("__PTX__"); 1907 Builder.defineMacro("__NVPTX__"); 1908 if (Opts.CUDAIsDevice) { 1909 // Set __CUDA_ARCH__ for the GPU specified. 1910 std::string CUDAArchCode = [this] { 1911 switch (GPU) { 1912 case CudaArch::UNKNOWN: 1913 assert(false && "No GPU arch when compiling CUDA device code."); 1914 return ""; 1915 case CudaArch::SM_20: 1916 return "200"; 1917 case CudaArch::SM_21: 1918 return "210"; 1919 case CudaArch::SM_30: 1920 return "300"; 1921 case CudaArch::SM_32: 1922 return "320"; 1923 case CudaArch::SM_35: 1924 return "350"; 1925 case CudaArch::SM_37: 1926 return "370"; 1927 case CudaArch::SM_50: 1928 return "500"; 1929 case CudaArch::SM_52: 1930 return "520"; 1931 case CudaArch::SM_53: 1932 return "530"; 1933 case CudaArch::SM_60: 1934 return "600"; 1935 case CudaArch::SM_61: 1936 return "610"; 1937 case CudaArch::SM_62: 1938 return "620"; 1939 } 1940 llvm_unreachable("unhandled CudaArch"); 1941 }(); 1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1943 } 1944 } 1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1946 return llvm::makeArrayRef(BuiltinInfo, 1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1948 } 1949 bool 1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1951 StringRef CPU, 1952 const std::vector<std::string> &FeaturesVec) const override { 1953 Features["satom"] = GPU >= CudaArch::SM_60; 1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1955 } 1956 1957 bool hasFeature(StringRef Feature) const override { 1958 return llvm::StringSwitch<bool>(Feature) 1959 .Cases("ptx", "nvptx", true) 1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1961 .Default(false); 1962 } 1963 1964 ArrayRef<const char *> getGCCRegNames() const override; 1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1966 // No aliases. 1967 return None; 1968 } 1969 bool validateAsmConstraint(const char *&Name, 1970 TargetInfo::ConstraintInfo &Info) const override { 1971 switch (*Name) { 1972 default: 1973 return false; 1974 case 'c': 1975 case 'h': 1976 case 'r': 1977 case 'l': 1978 case 'f': 1979 case 'd': 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 } 1984 const char *getClobbers() const override { 1985 // FIXME: Is this really right? 1986 return ""; 1987 } 1988 BuiltinVaListKind getBuiltinVaListKind() const override { 1989 // FIXME: implement 1990 return TargetInfo::CharPtrBuiltinVaList; 1991 } 1992 bool setCPU(const std::string &Name) override { 1993 GPU = StringToCudaArch(Name); 1994 return GPU != CudaArch::UNKNOWN; 1995 } 1996 void setSupportedOpenCLOpts() override { 1997 auto &Opts = getSupportedOpenCLOpts(); 1998 Opts.support("cl_clang_storage_class_specifiers"); 1999 Opts.support("cl_khr_gl_sharing"); 2000 Opts.support("cl_khr_icd"); 2001 2002 Opts.support("cl_khr_fp64"); 2003 Opts.support("cl_khr_byte_addressable_store"); 2004 Opts.support("cl_khr_global_int32_base_atomics"); 2005 Opts.support("cl_khr_global_int32_extended_atomics"); 2006 Opts.support("cl_khr_local_int32_base_atomics"); 2007 Opts.support("cl_khr_local_int32_extended_atomics"); 2008 } 2009 2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2011 // CUDA compilations support all of the host's calling conventions. 2012 // 2013 // TODO: We should warn if you apply a non-default CC to anything other than 2014 // a host function. 2015 if (HostTarget) 2016 return HostTarget->checkCallingConvention(CC); 2017 return CCCR_Warning; 2018 } 2019 }; 2020 2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2022 #define BUILTIN(ID, TYPE, ATTRS) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2028 #include "clang/Basic/BuiltinsNVPTX.def" 2029 }; 2030 2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2032 2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 static const LangAS::Map AMDGPUPrivateIsZeroMap = { 2038 4, // Default 2039 1, // opencl_global 2040 3, // opencl_local 2041 2, // opencl_constant 2042 4, // opencl_generic 2043 1, // cuda_device 2044 2, // cuda_constant 2045 3 // cuda_shared 2046 }; 2047 static const LangAS::Map AMDGPUGenericIsZeroMap = { 2048 0, // Default 2049 1, // opencl_global 2050 3, // opencl_local 2051 2, // opencl_constant 2052 0, // opencl_generic 2053 1, // cuda_device 2054 2, // cuda_constant 2055 3 // cuda_shared 2056 }; 2057 2058 // If you edit the description strings, make sure you update 2059 // getPointerWidthV(). 2060 2061 static const char *const DataLayoutStringR600 = 2062 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2063 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2064 2065 static const char *const DataLayoutStringSIPrivateIsZero = 2066 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2067 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2068 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2069 2070 static const char *const DataLayoutStringSIGenericIsZero = 2071 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2072 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2073 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2074 2075 class AMDGPUTargetInfo final : public TargetInfo { 2076 static const Builtin::Info BuiltinInfo[]; 2077 static const char * const GCCRegNames[]; 2078 2079 struct AddrSpace { 2080 unsigned Generic, Global, Local, Constant, Private; 2081 AddrSpace(bool IsGenericZero_ = false){ 2082 if (IsGenericZero_) { 2083 Generic = 0; 2084 Global = 1; 2085 Local = 3; 2086 Constant = 2; 2087 Private = 5; 2088 } else { 2089 Generic = 4; 2090 Global = 1; 2091 Local = 3; 2092 Constant = 2; 2093 Private = 0; 2094 } 2095 } 2096 }; 2097 2098 /// \brief The GPU profiles supported by the AMDGPU target. 2099 enum GPUKind { 2100 GK_NONE, 2101 GK_R600, 2102 GK_R600_DOUBLE_OPS, 2103 GK_R700, 2104 GK_R700_DOUBLE_OPS, 2105 GK_EVERGREEN, 2106 GK_EVERGREEN_DOUBLE_OPS, 2107 GK_NORTHERN_ISLANDS, 2108 GK_CAYMAN, 2109 GK_GFX6, 2110 GK_GFX7, 2111 GK_GFX8, 2112 GK_GFX9 2113 } GPU; 2114 2115 bool hasFP64:1; 2116 bool hasFMAF:1; 2117 bool hasLDEXPF:1; 2118 const AddrSpace AS; 2119 2120 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2121 return parseAMDGCNName(GPUName) >= GK_GFX9; 2122 } 2123 2124 static bool isAMDGCN(const llvm::Triple &TT) { 2125 return TT.getArch() == llvm::Triple::amdgcn; 2126 } 2127 2128 static bool isGenericZero(const llvm::Triple &TT) { 2129 return TT.getEnvironmentName() == "amdgiz" || 2130 TT.getEnvironmentName() == "amdgizcl"; 2131 } 2132 public: 2133 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2134 : TargetInfo(Triple) , 2135 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2136 hasFP64(false), 2137 hasFMAF(false), 2138 hasLDEXPF(false), 2139 AS(isGenericZero(Triple)){ 2140 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2141 hasFP64 = true; 2142 hasFMAF = true; 2143 hasLDEXPF = true; 2144 } 2145 auto IsGenericZero = isGenericZero(Triple); 2146 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2147 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2148 DataLayoutStringSIPrivateIsZero) 2149 : DataLayoutStringR600); 2150 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2151 2152 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap : 2153 &AMDGPUPrivateIsZeroMap; 2154 UseAddrSpaceMapMangling = true; 2155 } 2156 2157 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2158 if (GPU <= GK_CAYMAN) 2159 return 32; 2160 2161 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2162 return 32; 2163 } 2164 return 64; 2165 } 2166 2167 uint64_t getMaxPointerWidth() const override { 2168 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2169 } 2170 2171 const char * getClobbers() const override { 2172 return ""; 2173 } 2174 2175 ArrayRef<const char *> getGCCRegNames() const override; 2176 2177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2178 return None; 2179 } 2180 2181 bool validateAsmConstraint(const char *&Name, 2182 TargetInfo::ConstraintInfo &Info) const override { 2183 switch (*Name) { 2184 default: break; 2185 case 'v': // vgpr 2186 case 's': // sgpr 2187 Info.setAllowsRegister(); 2188 return true; 2189 } 2190 return false; 2191 } 2192 2193 bool initFeatureMap(llvm::StringMap<bool> &Features, 2194 DiagnosticsEngine &Diags, StringRef CPU, 2195 const std::vector<std::string> &FeatureVec) const override; 2196 2197 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2198 TargetOptions &TargetOpts) const override { 2199 bool hasFP32Denormals = false; 2200 bool hasFP64Denormals = false; 2201 for (auto &I : TargetOpts.FeaturesAsWritten) { 2202 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2203 hasFP32Denormals = true; 2204 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2205 hasFP64Denormals = true; 2206 } 2207 if (!hasFP32Denormals) 2208 TargetOpts.Features.push_back( 2209 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2210 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2211 // Always do not flush fp64 or fp16 denorms. 2212 if (!hasFP64Denormals && hasFP64) 2213 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2214 } 2215 2216 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2217 return llvm::makeArrayRef(BuiltinInfo, 2218 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2219 } 2220 2221 void getTargetDefines(const LangOptions &Opts, 2222 MacroBuilder &Builder) const override { 2223 if (getTriple().getArch() == llvm::Triple::amdgcn) 2224 Builder.defineMacro("__AMDGCN__"); 2225 else 2226 Builder.defineMacro("__R600__"); 2227 2228 if (hasFMAF) 2229 Builder.defineMacro("__HAS_FMAF__"); 2230 if (hasLDEXPF) 2231 Builder.defineMacro("__HAS_LDEXPF__"); 2232 if (hasFP64) 2233 Builder.defineMacro("__HAS_FP64__"); 2234 } 2235 2236 BuiltinVaListKind getBuiltinVaListKind() const override { 2237 return TargetInfo::CharPtrBuiltinVaList; 2238 } 2239 2240 static GPUKind parseR600Name(StringRef Name) { 2241 return llvm::StringSwitch<GPUKind>(Name) 2242 .Case("r600" , GK_R600) 2243 .Case("rv610", GK_R600) 2244 .Case("rv620", GK_R600) 2245 .Case("rv630", GK_R600) 2246 .Case("rv635", GK_R600) 2247 .Case("rs780", GK_R600) 2248 .Case("rs880", GK_R600) 2249 .Case("rv670", GK_R600_DOUBLE_OPS) 2250 .Case("rv710", GK_R700) 2251 .Case("rv730", GK_R700) 2252 .Case("rv740", GK_R700_DOUBLE_OPS) 2253 .Case("rv770", GK_R700_DOUBLE_OPS) 2254 .Case("palm", GK_EVERGREEN) 2255 .Case("cedar", GK_EVERGREEN) 2256 .Case("sumo", GK_EVERGREEN) 2257 .Case("sumo2", GK_EVERGREEN) 2258 .Case("redwood", GK_EVERGREEN) 2259 .Case("juniper", GK_EVERGREEN) 2260 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2261 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2262 .Case("barts", GK_NORTHERN_ISLANDS) 2263 .Case("turks", GK_NORTHERN_ISLANDS) 2264 .Case("caicos", GK_NORTHERN_ISLANDS) 2265 .Case("cayman", GK_CAYMAN) 2266 .Case("aruba", GK_CAYMAN) 2267 .Default(GK_NONE); 2268 } 2269 2270 static GPUKind parseAMDGCNName(StringRef Name) { 2271 return llvm::StringSwitch<GPUKind>(Name) 2272 .Case("tahiti", GK_GFX6) 2273 .Case("pitcairn", GK_GFX6) 2274 .Case("verde", GK_GFX6) 2275 .Case("oland", GK_GFX6) 2276 .Case("hainan", GK_GFX6) 2277 .Case("bonaire", GK_GFX7) 2278 .Case("kabini", GK_GFX7) 2279 .Case("kaveri", GK_GFX7) 2280 .Case("hawaii", GK_GFX7) 2281 .Case("mullins", GK_GFX7) 2282 .Case("gfx700", GK_GFX7) 2283 .Case("gfx701", GK_GFX7) 2284 .Case("gfx702", GK_GFX7) 2285 .Case("tonga", GK_GFX8) 2286 .Case("iceland", GK_GFX8) 2287 .Case("carrizo", GK_GFX8) 2288 .Case("fiji", GK_GFX8) 2289 .Case("stoney", GK_GFX8) 2290 .Case("polaris10", GK_GFX8) 2291 .Case("polaris11", GK_GFX8) 2292 .Case("gfx800", GK_GFX8) 2293 .Case("gfx801", GK_GFX8) 2294 .Case("gfx802", GK_GFX8) 2295 .Case("gfx803", GK_GFX8) 2296 .Case("gfx804", GK_GFX8) 2297 .Case("gfx810", GK_GFX8) 2298 .Case("gfx900", GK_GFX9) 2299 .Case("gfx901", GK_GFX9) 2300 .Default(GK_NONE); 2301 } 2302 2303 bool setCPU(const std::string &Name) override { 2304 if (getTriple().getArch() == llvm::Triple::amdgcn) 2305 GPU = parseAMDGCNName(Name); 2306 else 2307 GPU = parseR600Name(Name); 2308 2309 return GPU != GK_NONE; 2310 } 2311 2312 void setSupportedOpenCLOpts() override { 2313 auto &Opts = getSupportedOpenCLOpts(); 2314 Opts.support("cl_clang_storage_class_specifiers"); 2315 Opts.support("cl_khr_icd"); 2316 2317 if (hasFP64) 2318 Opts.support("cl_khr_fp64"); 2319 if (GPU >= GK_EVERGREEN) { 2320 Opts.support("cl_khr_byte_addressable_store"); 2321 Opts.support("cl_khr_global_int32_base_atomics"); 2322 Opts.support("cl_khr_global_int32_extended_atomics"); 2323 Opts.support("cl_khr_local_int32_base_atomics"); 2324 Opts.support("cl_khr_local_int32_extended_atomics"); 2325 } 2326 if (GPU >= GK_GFX6) { 2327 Opts.support("cl_khr_fp16"); 2328 Opts.support("cl_khr_int64_base_atomics"); 2329 Opts.support("cl_khr_int64_extended_atomics"); 2330 Opts.support("cl_khr_mipmap_image"); 2331 Opts.support("cl_khr_subgroups"); 2332 Opts.support("cl_khr_3d_image_writes"); 2333 Opts.support("cl_amd_media_ops"); 2334 Opts.support("cl_amd_media_ops2"); 2335 } 2336 } 2337 2338 LangAS::ID getOpenCLImageAddrSpace() const override { 2339 return LangAS::opencl_constant; 2340 } 2341 2342 /// \returns Target specific vtbl ptr address space. 2343 unsigned getVtblPtrAddressSpace() const override { 2344 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2345 // would be nice if we could use it here instead of using bare numbers (same 2346 // applies to getDWARFAddressSpace). 2347 return 2; // constant. 2348 } 2349 2350 /// \returns If a target requires an address within a target specific address 2351 /// space \p AddressSpace to be converted in order to be used, then return the 2352 /// corresponding target specific DWARF address space. 2353 /// 2354 /// \returns Otherwise return None and no conversion will be emitted in the 2355 /// DWARF. 2356 Optional<unsigned> getDWARFAddressSpace( 2357 unsigned AddressSpace) const override { 2358 const unsigned DWARF_Private = 1; 2359 const unsigned DWARF_Local = 2; 2360 if (AddressSpace == AS.Private) { 2361 return DWARF_Private; 2362 } else if (AddressSpace == AS.Local) { 2363 return DWARF_Local; 2364 } else { 2365 return None; 2366 } 2367 } 2368 2369 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2370 switch (CC) { 2371 default: 2372 return CCCR_Warning; 2373 case CC_C: 2374 case CC_OpenCLKernel: 2375 return CCCR_OK; 2376 } 2377 } 2378 2379 // In amdgcn target the null pointer in global, constant, and generic 2380 // address space has value 0 but in private and local address space has 2381 // value ~0. 2382 uint64_t getNullPointerValue(unsigned AS) const override { 2383 return AS == LangAS::opencl_local ? ~0 : 0; 2384 } 2385 }; 2386 2387 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2388 #define BUILTIN(ID, TYPE, ATTRS) \ 2389 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2390 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2391 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2392 #include "clang/Basic/BuiltinsAMDGPU.def" 2393 }; 2394 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2395 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2396 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2397 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2398 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2399 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2400 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2401 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2402 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2403 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2404 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2405 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2406 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2407 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2408 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2409 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2410 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2411 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2412 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2413 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2414 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2415 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2416 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2417 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2418 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2419 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2420 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2421 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2422 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2423 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2424 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2425 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2426 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2427 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2428 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2429 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2430 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2431 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2432 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2433 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2434 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2435 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2436 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2437 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2438 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2439 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2440 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2441 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2442 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2443 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2444 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2445 }; 2446 2447 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2448 return llvm::makeArrayRef(GCCRegNames); 2449 } 2450 2451 bool AMDGPUTargetInfo::initFeatureMap( 2452 llvm::StringMap<bool> &Features, 2453 DiagnosticsEngine &Diags, StringRef CPU, 2454 const std::vector<std::string> &FeatureVec) const { 2455 2456 // XXX - What does the member GPU mean if device name string passed here? 2457 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2458 if (CPU.empty()) 2459 CPU = "tahiti"; 2460 2461 switch (parseAMDGCNName(CPU)) { 2462 case GK_GFX6: 2463 case GK_GFX7: 2464 break; 2465 2466 case GK_GFX9: 2467 Features["gfx9-insts"] = true; 2468 LLVM_FALLTHROUGH; 2469 case GK_GFX8: 2470 Features["s-memrealtime"] = true; 2471 Features["16-bit-insts"] = true; 2472 Features["dpp"] = true; 2473 break; 2474 2475 case GK_NONE: 2476 return false; 2477 default: 2478 llvm_unreachable("unhandled subtarget"); 2479 } 2480 } else { 2481 if (CPU.empty()) 2482 CPU = "r600"; 2483 2484 switch (parseR600Name(CPU)) { 2485 case GK_R600: 2486 case GK_R700: 2487 case GK_EVERGREEN: 2488 case GK_NORTHERN_ISLANDS: 2489 break; 2490 case GK_R600_DOUBLE_OPS: 2491 case GK_R700_DOUBLE_OPS: 2492 case GK_EVERGREEN_DOUBLE_OPS: 2493 case GK_CAYMAN: 2494 Features["fp64"] = true; 2495 break; 2496 case GK_NONE: 2497 return false; 2498 default: 2499 llvm_unreachable("unhandled subtarget"); 2500 } 2501 } 2502 2503 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2504 } 2505 2506 const Builtin::Info BuiltinInfoX86[] = { 2507 #define BUILTIN(ID, TYPE, ATTRS) \ 2508 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2509 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2510 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2511 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2512 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2513 #include "clang/Basic/BuiltinsX86.def" 2514 2515 #define BUILTIN(ID, TYPE, ATTRS) \ 2516 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2517 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2518 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2519 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2520 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2521 #include "clang/Basic/BuiltinsX86_64.def" 2522 }; 2523 2524 2525 static const char* const GCCRegNames[] = { 2526 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2527 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2528 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2529 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2530 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2531 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2532 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2533 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2534 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2535 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2536 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2537 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2538 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2539 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2540 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2541 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2542 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2543 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2544 }; 2545 2546 const TargetInfo::AddlRegName AddlRegNames[] = { 2547 { { "al", "ah", "eax", "rax" }, 0 }, 2548 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2549 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2550 { { "dl", "dh", "edx", "rdx" }, 1 }, 2551 { { "esi", "rsi" }, 4 }, 2552 { { "edi", "rdi" }, 5 }, 2553 { { "esp", "rsp" }, 7 }, 2554 { { "ebp", "rbp" }, 6 }, 2555 { { "r8d", "r8w", "r8b" }, 38 }, 2556 { { "r9d", "r9w", "r9b" }, 39 }, 2557 { { "r10d", "r10w", "r10b" }, 40 }, 2558 { { "r11d", "r11w", "r11b" }, 41 }, 2559 { { "r12d", "r12w", "r12b" }, 42 }, 2560 { { "r13d", "r13w", "r13b" }, 43 }, 2561 { { "r14d", "r14w", "r14b" }, 44 }, 2562 { { "r15d", "r15w", "r15b" }, 45 }, 2563 }; 2564 2565 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2566 // most of the implementation can be shared. 2567 class X86TargetInfo : public TargetInfo { 2568 enum X86SSEEnum { 2569 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2570 } SSELevel = NoSSE; 2571 enum MMX3DNowEnum { 2572 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2573 } MMX3DNowLevel = NoMMX3DNow; 2574 enum XOPEnum { 2575 NoXOP, 2576 SSE4A, 2577 FMA4, 2578 XOP 2579 } XOPLevel = NoXOP; 2580 2581 bool HasAES = false; 2582 bool HasPCLMUL = false; 2583 bool HasLZCNT = false; 2584 bool HasRDRND = false; 2585 bool HasFSGSBASE = false; 2586 bool HasBMI = false; 2587 bool HasBMI2 = false; 2588 bool HasPOPCNT = false; 2589 bool HasRTM = false; 2590 bool HasPRFCHW = false; 2591 bool HasRDSEED = false; 2592 bool HasADX = false; 2593 bool HasTBM = false; 2594 bool HasFMA = false; 2595 bool HasF16C = false; 2596 bool HasAVX512CD = false; 2597 bool HasAVX512ER = false; 2598 bool HasAVX512PF = false; 2599 bool HasAVX512DQ = false; 2600 bool HasAVX512BW = false; 2601 bool HasAVX512VL = false; 2602 bool HasAVX512VBMI = false; 2603 bool HasAVX512IFMA = false; 2604 bool HasSHA = false; 2605 bool HasMPX = false; 2606 bool HasSGX = false; 2607 bool HasCX16 = false; 2608 bool HasFXSR = false; 2609 bool HasXSAVE = false; 2610 bool HasXSAVEOPT = false; 2611 bool HasXSAVEC = false; 2612 bool HasXSAVES = false; 2613 bool HasMWAITX = false; 2614 bool HasCLZERO = false; 2615 bool HasPKU = false; 2616 bool HasCLFLUSHOPT = false; 2617 bool HasCLWB = false; 2618 bool HasMOVBE = false; 2619 bool HasPREFETCHWT1 = false; 2620 2621 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2622 /// 2623 /// Each enumeration represents a particular CPU supported by Clang. These 2624 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2625 enum CPUKind { 2626 CK_Generic, 2627 2628 /// \name i386 2629 /// i386-generation processors. 2630 //@{ 2631 CK_i386, 2632 //@} 2633 2634 /// \name i486 2635 /// i486-generation processors. 2636 //@{ 2637 CK_i486, 2638 CK_WinChipC6, 2639 CK_WinChip2, 2640 CK_C3, 2641 //@} 2642 2643 /// \name i586 2644 /// i586-generation processors, P5 microarchitecture based. 2645 //@{ 2646 CK_i586, 2647 CK_Pentium, 2648 CK_PentiumMMX, 2649 //@} 2650 2651 /// \name i686 2652 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2653 //@{ 2654 CK_i686, 2655 CK_PentiumPro, 2656 CK_Pentium2, 2657 CK_Pentium3, 2658 CK_Pentium3M, 2659 CK_PentiumM, 2660 CK_C3_2, 2661 2662 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2663 /// Clang however has some logic to suport this. 2664 // FIXME: Warn, deprecate, and potentially remove this. 2665 CK_Yonah, 2666 //@} 2667 2668 /// \name Netburst 2669 /// Netburst microarchitecture based processors. 2670 //@{ 2671 CK_Pentium4, 2672 CK_Pentium4M, 2673 CK_Prescott, 2674 CK_Nocona, 2675 //@} 2676 2677 /// \name Core 2678 /// Core microarchitecture based processors. 2679 //@{ 2680 CK_Core2, 2681 2682 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2683 /// codename which GCC no longer accepts as an option to -march, but Clang 2684 /// has some logic for recognizing it. 2685 // FIXME: Warn, deprecate, and potentially remove this. 2686 CK_Penryn, 2687 //@} 2688 2689 /// \name Atom 2690 /// Atom processors 2691 //@{ 2692 CK_Bonnell, 2693 CK_Silvermont, 2694 //@} 2695 2696 /// \name Nehalem 2697 /// Nehalem microarchitecture based processors. 2698 CK_Nehalem, 2699 2700 /// \name Westmere 2701 /// Westmere microarchitecture based processors. 2702 CK_Westmere, 2703 2704 /// \name Sandy Bridge 2705 /// Sandy Bridge microarchitecture based processors. 2706 CK_SandyBridge, 2707 2708 /// \name Ivy Bridge 2709 /// Ivy Bridge microarchitecture based processors. 2710 CK_IvyBridge, 2711 2712 /// \name Haswell 2713 /// Haswell microarchitecture based processors. 2714 CK_Haswell, 2715 2716 /// \name Broadwell 2717 /// Broadwell microarchitecture based processors. 2718 CK_Broadwell, 2719 2720 /// \name Skylake Client 2721 /// Skylake client microarchitecture based processors. 2722 CK_SkylakeClient, 2723 2724 /// \name Skylake Server 2725 /// Skylake server microarchitecture based processors. 2726 CK_SkylakeServer, 2727 2728 /// \name Cannonlake Client 2729 /// Cannonlake client microarchitecture based processors. 2730 CK_Cannonlake, 2731 2732 /// \name Knights Landing 2733 /// Knights Landing processor. 2734 CK_KNL, 2735 2736 /// \name Lakemont 2737 /// Lakemont microarchitecture based processors. 2738 CK_Lakemont, 2739 2740 /// \name K6 2741 /// K6 architecture processors. 2742 //@{ 2743 CK_K6, 2744 CK_K6_2, 2745 CK_K6_3, 2746 //@} 2747 2748 /// \name K7 2749 /// K7 architecture processors. 2750 //@{ 2751 CK_Athlon, 2752 CK_AthlonThunderbird, 2753 CK_Athlon4, 2754 CK_AthlonXP, 2755 CK_AthlonMP, 2756 //@} 2757 2758 /// \name K8 2759 /// K8 architecture processors. 2760 //@{ 2761 CK_Athlon64, 2762 CK_Athlon64SSE3, 2763 CK_AthlonFX, 2764 CK_K8, 2765 CK_K8SSE3, 2766 CK_Opteron, 2767 CK_OpteronSSE3, 2768 CK_AMDFAM10, 2769 //@} 2770 2771 /// \name Bobcat 2772 /// Bobcat architecture processors. 2773 //@{ 2774 CK_BTVER1, 2775 CK_BTVER2, 2776 //@} 2777 2778 /// \name Bulldozer 2779 /// Bulldozer architecture processors. 2780 //@{ 2781 CK_BDVER1, 2782 CK_BDVER2, 2783 CK_BDVER3, 2784 CK_BDVER4, 2785 //@} 2786 2787 /// \name zen 2788 /// Zen architecture processors. 2789 //@{ 2790 CK_ZNVER1, 2791 //@} 2792 2793 /// This specification is deprecated and will be removed in the future. 2794 /// Users should prefer \see CK_K8. 2795 // FIXME: Warn on this when the CPU is set to it. 2796 //@{ 2797 CK_x86_64, 2798 //@} 2799 2800 /// \name Geode 2801 /// Geode processors. 2802 //@{ 2803 CK_Geode 2804 //@} 2805 } CPU = CK_Generic; 2806 2807 CPUKind getCPUKind(StringRef CPU) const { 2808 return llvm::StringSwitch<CPUKind>(CPU) 2809 .Case("i386", CK_i386) 2810 .Case("i486", CK_i486) 2811 .Case("winchip-c6", CK_WinChipC6) 2812 .Case("winchip2", CK_WinChip2) 2813 .Case("c3", CK_C3) 2814 .Case("i586", CK_i586) 2815 .Case("pentium", CK_Pentium) 2816 .Case("pentium-mmx", CK_PentiumMMX) 2817 .Case("i686", CK_i686) 2818 .Case("pentiumpro", CK_PentiumPro) 2819 .Case("pentium2", CK_Pentium2) 2820 .Case("pentium3", CK_Pentium3) 2821 .Case("pentium3m", CK_Pentium3M) 2822 .Case("pentium-m", CK_PentiumM) 2823 .Case("c3-2", CK_C3_2) 2824 .Case("yonah", CK_Yonah) 2825 .Case("pentium4", CK_Pentium4) 2826 .Case("pentium4m", CK_Pentium4M) 2827 .Case("prescott", CK_Prescott) 2828 .Case("nocona", CK_Nocona) 2829 .Case("core2", CK_Core2) 2830 .Case("penryn", CK_Penryn) 2831 .Case("bonnell", CK_Bonnell) 2832 .Case("atom", CK_Bonnell) // Legacy name. 2833 .Case("silvermont", CK_Silvermont) 2834 .Case("slm", CK_Silvermont) // Legacy name. 2835 .Case("nehalem", CK_Nehalem) 2836 .Case("corei7", CK_Nehalem) // Legacy name. 2837 .Case("westmere", CK_Westmere) 2838 .Case("sandybridge", CK_SandyBridge) 2839 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2840 .Case("ivybridge", CK_IvyBridge) 2841 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2842 .Case("haswell", CK_Haswell) 2843 .Case("core-avx2", CK_Haswell) // Legacy name. 2844 .Case("broadwell", CK_Broadwell) 2845 .Case("skylake", CK_SkylakeClient) 2846 .Case("skylake-avx512", CK_SkylakeServer) 2847 .Case("skx", CK_SkylakeServer) // Legacy name. 2848 .Case("cannonlake", CK_Cannonlake) 2849 .Case("knl", CK_KNL) 2850 .Case("lakemont", CK_Lakemont) 2851 .Case("k6", CK_K6) 2852 .Case("k6-2", CK_K6_2) 2853 .Case("k6-3", CK_K6_3) 2854 .Case("athlon", CK_Athlon) 2855 .Case("athlon-tbird", CK_AthlonThunderbird) 2856 .Case("athlon-4", CK_Athlon4) 2857 .Case("athlon-xp", CK_AthlonXP) 2858 .Case("athlon-mp", CK_AthlonMP) 2859 .Case("athlon64", CK_Athlon64) 2860 .Case("athlon64-sse3", CK_Athlon64SSE3) 2861 .Case("athlon-fx", CK_AthlonFX) 2862 .Case("k8", CK_K8) 2863 .Case("k8-sse3", CK_K8SSE3) 2864 .Case("opteron", CK_Opteron) 2865 .Case("opteron-sse3", CK_OpteronSSE3) 2866 .Case("barcelona", CK_AMDFAM10) 2867 .Case("amdfam10", CK_AMDFAM10) 2868 .Case("btver1", CK_BTVER1) 2869 .Case("btver2", CK_BTVER2) 2870 .Case("bdver1", CK_BDVER1) 2871 .Case("bdver2", CK_BDVER2) 2872 .Case("bdver3", CK_BDVER3) 2873 .Case("bdver4", CK_BDVER4) 2874 .Case("znver1", CK_ZNVER1) 2875 .Case("x86-64", CK_x86_64) 2876 .Case("geode", CK_Geode) 2877 .Default(CK_Generic); 2878 } 2879 2880 enum FPMathKind { 2881 FP_Default, 2882 FP_SSE, 2883 FP_387 2884 } FPMath = FP_Default; 2885 2886 public: 2887 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2888 : TargetInfo(Triple) { 2889 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2890 } 2891 unsigned getFloatEvalMethod() const override { 2892 // X87 evaluates with 80 bits "long double" precision. 2893 return SSELevel == NoSSE ? 2 : 0; 2894 } 2895 ArrayRef<const char *> getGCCRegNames() const override { 2896 return llvm::makeArrayRef(GCCRegNames); 2897 } 2898 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2899 return None; 2900 } 2901 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2902 return llvm::makeArrayRef(AddlRegNames); 2903 } 2904 bool validateCpuSupports(StringRef Name) const override; 2905 bool validateAsmConstraint(const char *&Name, 2906 TargetInfo::ConstraintInfo &info) const override; 2907 2908 bool validateGlobalRegisterVariable(StringRef RegName, 2909 unsigned RegSize, 2910 bool &HasSizeMismatch) const override { 2911 // esp and ebp are the only 32-bit registers the x86 backend can currently 2912 // handle. 2913 if (RegName.equals("esp") || RegName.equals("ebp")) { 2914 // Check that the register size is 32-bit. 2915 HasSizeMismatch = RegSize != 32; 2916 return true; 2917 } 2918 2919 return false; 2920 } 2921 2922 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2923 2924 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2925 2926 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2927 2928 std::string convertConstraint(const char *&Constraint) const override; 2929 const char *getClobbers() const override { 2930 return "~{dirflag},~{fpsr},~{flags}"; 2931 } 2932 2933 StringRef getConstraintRegister(const StringRef &Constraint, 2934 const StringRef &Expression) const override { 2935 StringRef::iterator I, E; 2936 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2937 if (isalpha(*I)) 2938 break; 2939 } 2940 if (I == E) 2941 return ""; 2942 switch (*I) { 2943 // For the register constraints, return the matching register name 2944 case 'a': 2945 return "ax"; 2946 case 'b': 2947 return "bx"; 2948 case 'c': 2949 return "cx"; 2950 case 'd': 2951 return "dx"; 2952 case 'S': 2953 return "si"; 2954 case 'D': 2955 return "di"; 2956 // In case the constraint is 'r' we need to return Expression 2957 case 'r': 2958 return Expression; 2959 default: 2960 // Default value if there is no constraint for the register 2961 return ""; 2962 } 2963 return ""; 2964 } 2965 2966 void getTargetDefines(const LangOptions &Opts, 2967 MacroBuilder &Builder) const override; 2968 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2969 bool Enabled); 2970 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2971 bool Enabled); 2972 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2973 bool Enabled); 2974 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2975 StringRef Name, bool Enabled) const override { 2976 setFeatureEnabledImpl(Features, Name, Enabled); 2977 } 2978 // This exists purely to cut down on the number of virtual calls in 2979 // initFeatureMap which calls this repeatedly. 2980 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2981 StringRef Name, bool Enabled); 2982 bool 2983 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2984 StringRef CPU, 2985 const std::vector<std::string> &FeaturesVec) const override; 2986 bool hasFeature(StringRef Feature) const override; 2987 bool handleTargetFeatures(std::vector<std::string> &Features, 2988 DiagnosticsEngine &Diags) override; 2989 StringRef getABI() const override { 2990 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2991 return "avx512"; 2992 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2993 return "avx"; 2994 if (getTriple().getArch() == llvm::Triple::x86 && 2995 MMX3DNowLevel == NoMMX3DNow) 2996 return "no-mmx"; 2997 return ""; 2998 } 2999 bool setCPU(const std::string &Name) override { 3000 CPU = getCPUKind(Name); 3001 3002 // Perform any per-CPU checks necessary to determine if this CPU is 3003 // acceptable. 3004 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3005 // invalid without explaining *why*. 3006 switch (CPU) { 3007 case CK_Generic: 3008 // No processor selected! 3009 return false; 3010 3011 case CK_i386: 3012 case CK_i486: 3013 case CK_WinChipC6: 3014 case CK_WinChip2: 3015 case CK_C3: 3016 case CK_i586: 3017 case CK_Pentium: 3018 case CK_PentiumMMX: 3019 case CK_i686: 3020 case CK_PentiumPro: 3021 case CK_Pentium2: 3022 case CK_Pentium3: 3023 case CK_Pentium3M: 3024 case CK_PentiumM: 3025 case CK_Yonah: 3026 case CK_C3_2: 3027 case CK_Pentium4: 3028 case CK_Pentium4M: 3029 case CK_Lakemont: 3030 case CK_Prescott: 3031 case CK_K6: 3032 case CK_K6_2: 3033 case CK_K6_3: 3034 case CK_Athlon: 3035 case CK_AthlonThunderbird: 3036 case CK_Athlon4: 3037 case CK_AthlonXP: 3038 case CK_AthlonMP: 3039 case CK_Geode: 3040 // Only accept certain architectures when compiling in 32-bit mode. 3041 if (getTriple().getArch() != llvm::Triple::x86) 3042 return false; 3043 3044 // Fallthrough 3045 case CK_Nocona: 3046 case CK_Core2: 3047 case CK_Penryn: 3048 case CK_Bonnell: 3049 case CK_Silvermont: 3050 case CK_Nehalem: 3051 case CK_Westmere: 3052 case CK_SandyBridge: 3053 case CK_IvyBridge: 3054 case CK_Haswell: 3055 case CK_Broadwell: 3056 case CK_SkylakeClient: 3057 case CK_SkylakeServer: 3058 case CK_Cannonlake: 3059 case CK_KNL: 3060 case CK_Athlon64: 3061 case CK_Athlon64SSE3: 3062 case CK_AthlonFX: 3063 case CK_K8: 3064 case CK_K8SSE3: 3065 case CK_Opteron: 3066 case CK_OpteronSSE3: 3067 case CK_AMDFAM10: 3068 case CK_BTVER1: 3069 case CK_BTVER2: 3070 case CK_BDVER1: 3071 case CK_BDVER2: 3072 case CK_BDVER3: 3073 case CK_BDVER4: 3074 case CK_ZNVER1: 3075 case CK_x86_64: 3076 return true; 3077 } 3078 llvm_unreachable("Unhandled CPU kind"); 3079 } 3080 3081 bool setFPMath(StringRef Name) override; 3082 3083 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3084 // Most of the non-ARM calling conventions are i386 conventions. 3085 switch (CC) { 3086 case CC_X86ThisCall: 3087 case CC_X86FastCall: 3088 case CC_X86StdCall: 3089 case CC_X86VectorCall: 3090 case CC_X86RegCall: 3091 case CC_C: 3092 case CC_Swift: 3093 case CC_X86Pascal: 3094 case CC_IntelOclBicc: 3095 return CCCR_OK; 3096 default: 3097 return CCCR_Warning; 3098 } 3099 } 3100 3101 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3102 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3103 } 3104 3105 bool hasSjLjLowering() const override { 3106 return true; 3107 } 3108 3109 void setSupportedOpenCLOpts() override { 3110 getSupportedOpenCLOpts().supportAll(); 3111 } 3112 }; 3113 3114 bool X86TargetInfo::setFPMath(StringRef Name) { 3115 if (Name == "387") { 3116 FPMath = FP_387; 3117 return true; 3118 } 3119 if (Name == "sse") { 3120 FPMath = FP_SSE; 3121 return true; 3122 } 3123 return false; 3124 } 3125 3126 bool X86TargetInfo::initFeatureMap( 3127 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3128 const std::vector<std::string> &FeaturesVec) const { 3129 // FIXME: This *really* should not be here. 3130 // X86_64 always has SSE2. 3131 if (getTriple().getArch() == llvm::Triple::x86_64) 3132 setFeatureEnabledImpl(Features, "sse2", true); 3133 3134 const CPUKind Kind = getCPUKind(CPU); 3135 3136 // Enable X87 for all X86 processors but Lakemont. 3137 if (Kind != CK_Lakemont) 3138 setFeatureEnabledImpl(Features, "x87", true); 3139 3140 switch (Kind) { 3141 case CK_Generic: 3142 case CK_i386: 3143 case CK_i486: 3144 case CK_i586: 3145 case CK_Pentium: 3146 case CK_i686: 3147 case CK_PentiumPro: 3148 case CK_Lakemont: 3149 break; 3150 case CK_PentiumMMX: 3151 case CK_Pentium2: 3152 case CK_K6: 3153 case CK_WinChipC6: 3154 setFeatureEnabledImpl(Features, "mmx", true); 3155 break; 3156 case CK_Pentium3: 3157 case CK_Pentium3M: 3158 case CK_C3_2: 3159 setFeatureEnabledImpl(Features, "sse", true); 3160 setFeatureEnabledImpl(Features, "fxsr", true); 3161 break; 3162 case CK_PentiumM: 3163 case CK_Pentium4: 3164 case CK_Pentium4M: 3165 case CK_x86_64: 3166 setFeatureEnabledImpl(Features, "sse2", true); 3167 setFeatureEnabledImpl(Features, "fxsr", true); 3168 break; 3169 case CK_Yonah: 3170 case CK_Prescott: 3171 case CK_Nocona: 3172 setFeatureEnabledImpl(Features, "sse3", true); 3173 setFeatureEnabledImpl(Features, "fxsr", true); 3174 setFeatureEnabledImpl(Features, "cx16", true); 3175 break; 3176 case CK_Core2: 3177 case CK_Bonnell: 3178 setFeatureEnabledImpl(Features, "ssse3", true); 3179 setFeatureEnabledImpl(Features, "fxsr", true); 3180 setFeatureEnabledImpl(Features, "cx16", true); 3181 break; 3182 case CK_Penryn: 3183 setFeatureEnabledImpl(Features, "sse4.1", true); 3184 setFeatureEnabledImpl(Features, "fxsr", true); 3185 setFeatureEnabledImpl(Features, "cx16", true); 3186 break; 3187 case CK_Cannonlake: 3188 setFeatureEnabledImpl(Features, "avx512ifma", true); 3189 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3190 setFeatureEnabledImpl(Features, "sha", true); 3191 LLVM_FALLTHROUGH; 3192 case CK_SkylakeServer: 3193 setFeatureEnabledImpl(Features, "avx512f", true); 3194 setFeatureEnabledImpl(Features, "avx512cd", true); 3195 setFeatureEnabledImpl(Features, "avx512dq", true); 3196 setFeatureEnabledImpl(Features, "avx512bw", true); 3197 setFeatureEnabledImpl(Features, "avx512vl", true); 3198 setFeatureEnabledImpl(Features, "pku", true); 3199 setFeatureEnabledImpl(Features, "clwb", true); 3200 LLVM_FALLTHROUGH; 3201 case CK_SkylakeClient: 3202 setFeatureEnabledImpl(Features, "xsavec", true); 3203 setFeatureEnabledImpl(Features, "xsaves", true); 3204 setFeatureEnabledImpl(Features, "mpx", true); 3205 setFeatureEnabledImpl(Features, "sgx", true); 3206 setFeatureEnabledImpl(Features, "clflushopt", true); 3207 setFeatureEnabledImpl(Features, "rtm", true); 3208 LLVM_FALLTHROUGH; 3209 case CK_Broadwell: 3210 setFeatureEnabledImpl(Features, "rdseed", true); 3211 setFeatureEnabledImpl(Features, "adx", true); 3212 LLVM_FALLTHROUGH; 3213 case CK_Haswell: 3214 setFeatureEnabledImpl(Features, "avx2", true); 3215 setFeatureEnabledImpl(Features, "lzcnt", true); 3216 setFeatureEnabledImpl(Features, "bmi", true); 3217 setFeatureEnabledImpl(Features, "bmi2", true); 3218 setFeatureEnabledImpl(Features, "fma", true); 3219 setFeatureEnabledImpl(Features, "movbe", true); 3220 LLVM_FALLTHROUGH; 3221 case CK_IvyBridge: 3222 setFeatureEnabledImpl(Features, "rdrnd", true); 3223 setFeatureEnabledImpl(Features, "f16c", true); 3224 setFeatureEnabledImpl(Features, "fsgsbase", true); 3225 LLVM_FALLTHROUGH; 3226 case CK_SandyBridge: 3227 setFeatureEnabledImpl(Features, "avx", true); 3228 setFeatureEnabledImpl(Features, "xsave", true); 3229 setFeatureEnabledImpl(Features, "xsaveopt", true); 3230 LLVM_FALLTHROUGH; 3231 case CK_Westmere: 3232 case CK_Silvermont: 3233 setFeatureEnabledImpl(Features, "aes", true); 3234 setFeatureEnabledImpl(Features, "pclmul", true); 3235 LLVM_FALLTHROUGH; 3236 case CK_Nehalem: 3237 setFeatureEnabledImpl(Features, "sse4.2", true); 3238 setFeatureEnabledImpl(Features, "fxsr", true); 3239 setFeatureEnabledImpl(Features, "cx16", true); 3240 break; 3241 case CK_KNL: 3242 setFeatureEnabledImpl(Features, "avx512f", true); 3243 setFeatureEnabledImpl(Features, "avx512cd", true); 3244 setFeatureEnabledImpl(Features, "avx512er", true); 3245 setFeatureEnabledImpl(Features, "avx512pf", true); 3246 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3247 setFeatureEnabledImpl(Features, "fxsr", true); 3248 setFeatureEnabledImpl(Features, "rdseed", true); 3249 setFeatureEnabledImpl(Features, "adx", true); 3250 setFeatureEnabledImpl(Features, "lzcnt", true); 3251 setFeatureEnabledImpl(Features, "bmi", true); 3252 setFeatureEnabledImpl(Features, "bmi2", true); 3253 setFeatureEnabledImpl(Features, "rtm", true); 3254 setFeatureEnabledImpl(Features, "fma", true); 3255 setFeatureEnabledImpl(Features, "rdrnd", true); 3256 setFeatureEnabledImpl(Features, "f16c", true); 3257 setFeatureEnabledImpl(Features, "fsgsbase", true); 3258 setFeatureEnabledImpl(Features, "aes", true); 3259 setFeatureEnabledImpl(Features, "pclmul", true); 3260 setFeatureEnabledImpl(Features, "cx16", true); 3261 setFeatureEnabledImpl(Features, "xsaveopt", true); 3262 setFeatureEnabledImpl(Features, "xsave", true); 3263 setFeatureEnabledImpl(Features, "movbe", true); 3264 break; 3265 case CK_K6_2: 3266 case CK_K6_3: 3267 case CK_WinChip2: 3268 case CK_C3: 3269 setFeatureEnabledImpl(Features, "3dnow", true); 3270 break; 3271 case CK_Athlon: 3272 case CK_AthlonThunderbird: 3273 case CK_Geode: 3274 setFeatureEnabledImpl(Features, "3dnowa", true); 3275 break; 3276 case CK_Athlon4: 3277 case CK_AthlonXP: 3278 case CK_AthlonMP: 3279 setFeatureEnabledImpl(Features, "sse", true); 3280 setFeatureEnabledImpl(Features, "3dnowa", true); 3281 setFeatureEnabledImpl(Features, "fxsr", true); 3282 break; 3283 case CK_K8: 3284 case CK_Opteron: 3285 case CK_Athlon64: 3286 case CK_AthlonFX: 3287 setFeatureEnabledImpl(Features, "sse2", true); 3288 setFeatureEnabledImpl(Features, "3dnowa", true); 3289 setFeatureEnabledImpl(Features, "fxsr", true); 3290 break; 3291 case CK_AMDFAM10: 3292 setFeatureEnabledImpl(Features, "sse4a", true); 3293 setFeatureEnabledImpl(Features, "lzcnt", true); 3294 setFeatureEnabledImpl(Features, "popcnt", true); 3295 LLVM_FALLTHROUGH; 3296 case CK_K8SSE3: 3297 case CK_OpteronSSE3: 3298 case CK_Athlon64SSE3: 3299 setFeatureEnabledImpl(Features, "sse3", true); 3300 setFeatureEnabledImpl(Features, "3dnowa", true); 3301 setFeatureEnabledImpl(Features, "fxsr", true); 3302 break; 3303 case CK_BTVER2: 3304 setFeatureEnabledImpl(Features, "avx", true); 3305 setFeatureEnabledImpl(Features, "aes", true); 3306 setFeatureEnabledImpl(Features, "pclmul", true); 3307 setFeatureEnabledImpl(Features, "bmi", true); 3308 setFeatureEnabledImpl(Features, "f16c", true); 3309 setFeatureEnabledImpl(Features, "xsaveopt", true); 3310 LLVM_FALLTHROUGH; 3311 case CK_BTVER1: 3312 setFeatureEnabledImpl(Features, "ssse3", true); 3313 setFeatureEnabledImpl(Features, "sse4a", true); 3314 setFeatureEnabledImpl(Features, "lzcnt", true); 3315 setFeatureEnabledImpl(Features, "popcnt", true); 3316 setFeatureEnabledImpl(Features, "prfchw", true); 3317 setFeatureEnabledImpl(Features, "cx16", true); 3318 setFeatureEnabledImpl(Features, "fxsr", true); 3319 break; 3320 case CK_ZNVER1: 3321 setFeatureEnabledImpl(Features, "adx", true); 3322 setFeatureEnabledImpl(Features, "aes", true); 3323 setFeatureEnabledImpl(Features, "avx2", true); 3324 setFeatureEnabledImpl(Features, "bmi", true); 3325 setFeatureEnabledImpl(Features, "bmi2", true); 3326 setFeatureEnabledImpl(Features, "clflushopt", true); 3327 setFeatureEnabledImpl(Features, "clzero", true); 3328 setFeatureEnabledImpl(Features, "cx16", true); 3329 setFeatureEnabledImpl(Features, "f16c", true); 3330 setFeatureEnabledImpl(Features, "fma", true); 3331 setFeatureEnabledImpl(Features, "fsgsbase", true); 3332 setFeatureEnabledImpl(Features, "fxsr", true); 3333 setFeatureEnabledImpl(Features, "lzcnt", true); 3334 setFeatureEnabledImpl(Features, "mwaitx", true); 3335 setFeatureEnabledImpl(Features, "movbe", true); 3336 setFeatureEnabledImpl(Features, "pclmul", true); 3337 setFeatureEnabledImpl(Features, "popcnt", true); 3338 setFeatureEnabledImpl(Features, "prfchw", true); 3339 setFeatureEnabledImpl(Features, "rdrnd", true); 3340 setFeatureEnabledImpl(Features, "rdseed", true); 3341 setFeatureEnabledImpl(Features, "sha", true); 3342 setFeatureEnabledImpl(Features, "sse4a", true); 3343 setFeatureEnabledImpl(Features, "xsave", true); 3344 setFeatureEnabledImpl(Features, "xsavec", true); 3345 setFeatureEnabledImpl(Features, "xsaveopt", true); 3346 setFeatureEnabledImpl(Features, "xsaves", true); 3347 break; 3348 case CK_BDVER4: 3349 setFeatureEnabledImpl(Features, "avx2", true); 3350 setFeatureEnabledImpl(Features, "bmi2", true); 3351 setFeatureEnabledImpl(Features, "mwaitx", true); 3352 LLVM_FALLTHROUGH; 3353 case CK_BDVER3: 3354 setFeatureEnabledImpl(Features, "fsgsbase", true); 3355 setFeatureEnabledImpl(Features, "xsaveopt", true); 3356 LLVM_FALLTHROUGH; 3357 case CK_BDVER2: 3358 setFeatureEnabledImpl(Features, "bmi", true); 3359 setFeatureEnabledImpl(Features, "fma", true); 3360 setFeatureEnabledImpl(Features, "f16c", true); 3361 setFeatureEnabledImpl(Features, "tbm", true); 3362 LLVM_FALLTHROUGH; 3363 case CK_BDVER1: 3364 // xop implies avx, sse4a and fma4. 3365 setFeatureEnabledImpl(Features, "xop", true); 3366 setFeatureEnabledImpl(Features, "lzcnt", true); 3367 setFeatureEnabledImpl(Features, "aes", true); 3368 setFeatureEnabledImpl(Features, "pclmul", true); 3369 setFeatureEnabledImpl(Features, "prfchw", true); 3370 setFeatureEnabledImpl(Features, "cx16", true); 3371 setFeatureEnabledImpl(Features, "fxsr", true); 3372 setFeatureEnabledImpl(Features, "xsave", true); 3373 break; 3374 } 3375 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3376 return false; 3377 3378 // Can't do this earlier because we need to be able to explicitly enable 3379 // or disable these features and the things that they depend upon. 3380 3381 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3382 auto I = Features.find("sse4.2"); 3383 if (I != Features.end() && I->getValue() && 3384 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3385 FeaturesVec.end()) 3386 Features["popcnt"] = true; 3387 3388 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3389 I = Features.find("3dnow"); 3390 if (I != Features.end() && I->getValue() && 3391 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3392 FeaturesVec.end()) 3393 Features["prfchw"] = true; 3394 3395 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3396 // then enable MMX. 3397 I = Features.find("sse"); 3398 if (I != Features.end() && I->getValue() && 3399 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3400 FeaturesVec.end()) 3401 Features["mmx"] = true; 3402 3403 return true; 3404 } 3405 3406 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3407 X86SSEEnum Level, bool Enabled) { 3408 if (Enabled) { 3409 switch (Level) { 3410 case AVX512F: 3411 Features["avx512f"] = true; 3412 case AVX2: 3413 Features["avx2"] = true; 3414 case AVX: 3415 Features["avx"] = true; 3416 Features["xsave"] = true; 3417 case SSE42: 3418 Features["sse4.2"] = true; 3419 case SSE41: 3420 Features["sse4.1"] = true; 3421 case SSSE3: 3422 Features["ssse3"] = true; 3423 case SSE3: 3424 Features["sse3"] = true; 3425 case SSE2: 3426 Features["sse2"] = true; 3427 case SSE1: 3428 Features["sse"] = true; 3429 case NoSSE: 3430 break; 3431 } 3432 return; 3433 } 3434 3435 switch (Level) { 3436 case NoSSE: 3437 case SSE1: 3438 Features["sse"] = false; 3439 case SSE2: 3440 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3441 Features["sha"] = false; 3442 case SSE3: 3443 Features["sse3"] = false; 3444 setXOPLevel(Features, NoXOP, false); 3445 case SSSE3: 3446 Features["ssse3"] = false; 3447 case SSE41: 3448 Features["sse4.1"] = false; 3449 case SSE42: 3450 Features["sse4.2"] = false; 3451 case AVX: 3452 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3453 Features["xsaveopt"] = false; 3454 setXOPLevel(Features, FMA4, false); 3455 case AVX2: 3456 Features["avx2"] = false; 3457 case AVX512F: 3458 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3459 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3460 Features["avx512vl"] = Features["avx512vbmi"] = 3461 Features["avx512ifma"] = false; 3462 } 3463 } 3464 3465 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3466 MMX3DNowEnum Level, bool Enabled) { 3467 if (Enabled) { 3468 switch (Level) { 3469 case AMD3DNowAthlon: 3470 Features["3dnowa"] = true; 3471 case AMD3DNow: 3472 Features["3dnow"] = true; 3473 case MMX: 3474 Features["mmx"] = true; 3475 case NoMMX3DNow: 3476 break; 3477 } 3478 return; 3479 } 3480 3481 switch (Level) { 3482 case NoMMX3DNow: 3483 case MMX: 3484 Features["mmx"] = false; 3485 case AMD3DNow: 3486 Features["3dnow"] = false; 3487 case AMD3DNowAthlon: 3488 Features["3dnowa"] = false; 3489 } 3490 } 3491 3492 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3493 bool Enabled) { 3494 if (Enabled) { 3495 switch (Level) { 3496 case XOP: 3497 Features["xop"] = true; 3498 case FMA4: 3499 Features["fma4"] = true; 3500 setSSELevel(Features, AVX, true); 3501 case SSE4A: 3502 Features["sse4a"] = true; 3503 setSSELevel(Features, SSE3, true); 3504 case NoXOP: 3505 break; 3506 } 3507 return; 3508 } 3509 3510 switch (Level) { 3511 case NoXOP: 3512 case SSE4A: 3513 Features["sse4a"] = false; 3514 case FMA4: 3515 Features["fma4"] = false; 3516 case XOP: 3517 Features["xop"] = false; 3518 } 3519 } 3520 3521 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3522 StringRef Name, bool Enabled) { 3523 // This is a bit of a hack to deal with the sse4 target feature when used 3524 // as part of the target attribute. We handle sse4 correctly everywhere 3525 // else. See below for more information on how we handle the sse4 options. 3526 if (Name != "sse4") 3527 Features[Name] = Enabled; 3528 3529 if (Name == "mmx") { 3530 setMMXLevel(Features, MMX, Enabled); 3531 } else if (Name == "sse") { 3532 setSSELevel(Features, SSE1, Enabled); 3533 } else if (Name == "sse2") { 3534 setSSELevel(Features, SSE2, Enabled); 3535 } else if (Name == "sse3") { 3536 setSSELevel(Features, SSE3, Enabled); 3537 } else if (Name == "ssse3") { 3538 setSSELevel(Features, SSSE3, Enabled); 3539 } else if (Name == "sse4.2") { 3540 setSSELevel(Features, SSE42, Enabled); 3541 } else if (Name == "sse4.1") { 3542 setSSELevel(Features, SSE41, Enabled); 3543 } else if (Name == "3dnow") { 3544 setMMXLevel(Features, AMD3DNow, Enabled); 3545 } else if (Name == "3dnowa") { 3546 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3547 } else if (Name == "aes") { 3548 if (Enabled) 3549 setSSELevel(Features, SSE2, Enabled); 3550 } else if (Name == "pclmul") { 3551 if (Enabled) 3552 setSSELevel(Features, SSE2, Enabled); 3553 } else if (Name == "avx") { 3554 setSSELevel(Features, AVX, Enabled); 3555 } else if (Name == "avx2") { 3556 setSSELevel(Features, AVX2, Enabled); 3557 } else if (Name == "avx512f") { 3558 setSSELevel(Features, AVX512F, Enabled); 3559 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3560 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3561 Name == "avx512vbmi" || Name == "avx512ifma") { 3562 if (Enabled) 3563 setSSELevel(Features, AVX512F, Enabled); 3564 // Enable BWI instruction if VBMI is being enabled. 3565 if (Name == "avx512vbmi" && Enabled) 3566 Features["avx512bw"] = true; 3567 // Also disable VBMI if BWI is being disabled. 3568 if (Name == "avx512bw" && !Enabled) 3569 Features["avx512vbmi"] = false; 3570 } else if (Name == "fma") { 3571 if (Enabled) 3572 setSSELevel(Features, AVX, Enabled); 3573 } else if (Name == "fma4") { 3574 setXOPLevel(Features, FMA4, Enabled); 3575 } else if (Name == "xop") { 3576 setXOPLevel(Features, XOP, Enabled); 3577 } else if (Name == "sse4a") { 3578 setXOPLevel(Features, SSE4A, Enabled); 3579 } else if (Name == "f16c") { 3580 if (Enabled) 3581 setSSELevel(Features, AVX, Enabled); 3582 } else if (Name == "sha") { 3583 if (Enabled) 3584 setSSELevel(Features, SSE2, Enabled); 3585 } else if (Name == "sse4") { 3586 // We can get here via the __target__ attribute since that's not controlled 3587 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3588 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3589 // disabled. 3590 if (Enabled) 3591 setSSELevel(Features, SSE42, Enabled); 3592 else 3593 setSSELevel(Features, SSE41, Enabled); 3594 } else if (Name == "xsave") { 3595 if (!Enabled) 3596 Features["xsaveopt"] = false; 3597 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3598 if (Enabled) 3599 Features["xsave"] = true; 3600 } 3601 } 3602 3603 /// handleTargetFeatures - Perform initialization based on the user 3604 /// configured set of features. 3605 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3606 DiagnosticsEngine &Diags) { 3607 for (const auto &Feature : Features) { 3608 if (Feature[0] != '+') 3609 continue; 3610 3611 if (Feature == "+aes") { 3612 HasAES = true; 3613 } else if (Feature == "+pclmul") { 3614 HasPCLMUL = true; 3615 } else if (Feature == "+lzcnt") { 3616 HasLZCNT = true; 3617 } else if (Feature == "+rdrnd") { 3618 HasRDRND = true; 3619 } else if (Feature == "+fsgsbase") { 3620 HasFSGSBASE = true; 3621 } else if (Feature == "+bmi") { 3622 HasBMI = true; 3623 } else if (Feature == "+bmi2") { 3624 HasBMI2 = true; 3625 } else if (Feature == "+popcnt") { 3626 HasPOPCNT = true; 3627 } else if (Feature == "+rtm") { 3628 HasRTM = true; 3629 } else if (Feature == "+prfchw") { 3630 HasPRFCHW = true; 3631 } else if (Feature == "+rdseed") { 3632 HasRDSEED = true; 3633 } else if (Feature == "+adx") { 3634 HasADX = true; 3635 } else if (Feature == "+tbm") { 3636 HasTBM = true; 3637 } else if (Feature == "+fma") { 3638 HasFMA = true; 3639 } else if (Feature == "+f16c") { 3640 HasF16C = true; 3641 } else if (Feature == "+avx512cd") { 3642 HasAVX512CD = true; 3643 } else if (Feature == "+avx512er") { 3644 HasAVX512ER = true; 3645 } else if (Feature == "+avx512pf") { 3646 HasAVX512PF = true; 3647 } else if (Feature == "+avx512dq") { 3648 HasAVX512DQ = true; 3649 } else if (Feature == "+avx512bw") { 3650 HasAVX512BW = true; 3651 } else if (Feature == "+avx512vl") { 3652 HasAVX512VL = true; 3653 } else if (Feature == "+avx512vbmi") { 3654 HasAVX512VBMI = true; 3655 } else if (Feature == "+avx512ifma") { 3656 HasAVX512IFMA = true; 3657 } else if (Feature == "+sha") { 3658 HasSHA = true; 3659 } else if (Feature == "+mpx") { 3660 HasMPX = true; 3661 } else if (Feature == "+movbe") { 3662 HasMOVBE = true; 3663 } else if (Feature == "+sgx") { 3664 HasSGX = true; 3665 } else if (Feature == "+cx16") { 3666 HasCX16 = true; 3667 } else if (Feature == "+fxsr") { 3668 HasFXSR = true; 3669 } else if (Feature == "+xsave") { 3670 HasXSAVE = true; 3671 } else if (Feature == "+xsaveopt") { 3672 HasXSAVEOPT = true; 3673 } else if (Feature == "+xsavec") { 3674 HasXSAVEC = true; 3675 } else if (Feature == "+xsaves") { 3676 HasXSAVES = true; 3677 } else if (Feature == "+mwaitx") { 3678 HasMWAITX = true; 3679 } else if (Feature == "+pku") { 3680 HasPKU = true; 3681 } else if (Feature == "+clflushopt") { 3682 HasCLFLUSHOPT = true; 3683 } else if (Feature == "+clwb") { 3684 HasCLWB = true; 3685 } else if (Feature == "+prefetchwt1") { 3686 HasPREFETCHWT1 = true; 3687 } else if (Feature == "+clzero") { 3688 HasCLZERO = true; 3689 } 3690 3691 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3692 .Case("+avx512f", AVX512F) 3693 .Case("+avx2", AVX2) 3694 .Case("+avx", AVX) 3695 .Case("+sse4.2", SSE42) 3696 .Case("+sse4.1", SSE41) 3697 .Case("+ssse3", SSSE3) 3698 .Case("+sse3", SSE3) 3699 .Case("+sse2", SSE2) 3700 .Case("+sse", SSE1) 3701 .Default(NoSSE); 3702 SSELevel = std::max(SSELevel, Level); 3703 3704 MMX3DNowEnum ThreeDNowLevel = 3705 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3706 .Case("+3dnowa", AMD3DNowAthlon) 3707 .Case("+3dnow", AMD3DNow) 3708 .Case("+mmx", MMX) 3709 .Default(NoMMX3DNow); 3710 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3711 3712 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3713 .Case("+xop", XOP) 3714 .Case("+fma4", FMA4) 3715 .Case("+sse4a", SSE4A) 3716 .Default(NoXOP); 3717 XOPLevel = std::max(XOPLevel, XLevel); 3718 } 3719 3720 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3721 // matches the selected sse level. 3722 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3723 (FPMath == FP_387 && SSELevel >= SSE1)) { 3724 Diags.Report(diag::err_target_unsupported_fpmath) << 3725 (FPMath == FP_SSE ? "sse" : "387"); 3726 return false; 3727 } 3728 3729 SimdDefaultAlign = 3730 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3731 return true; 3732 } 3733 3734 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3735 /// definitions for this particular subtarget. 3736 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3737 MacroBuilder &Builder) const { 3738 // Target identification. 3739 if (getTriple().getArch() == llvm::Triple::x86_64) { 3740 Builder.defineMacro("__amd64__"); 3741 Builder.defineMacro("__amd64"); 3742 Builder.defineMacro("__x86_64"); 3743 Builder.defineMacro("__x86_64__"); 3744 if (getTriple().getArchName() == "x86_64h") { 3745 Builder.defineMacro("__x86_64h"); 3746 Builder.defineMacro("__x86_64h__"); 3747 } 3748 } else { 3749 DefineStd(Builder, "i386", Opts); 3750 } 3751 3752 // Subtarget options. 3753 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3754 // truly should be based on -mtune options. 3755 switch (CPU) { 3756 case CK_Generic: 3757 break; 3758 case CK_i386: 3759 // The rest are coming from the i386 define above. 3760 Builder.defineMacro("__tune_i386__"); 3761 break; 3762 case CK_i486: 3763 case CK_WinChipC6: 3764 case CK_WinChip2: 3765 case CK_C3: 3766 defineCPUMacros(Builder, "i486"); 3767 break; 3768 case CK_PentiumMMX: 3769 Builder.defineMacro("__pentium_mmx__"); 3770 Builder.defineMacro("__tune_pentium_mmx__"); 3771 // Fallthrough 3772 case CK_i586: 3773 case CK_Pentium: 3774 defineCPUMacros(Builder, "i586"); 3775 defineCPUMacros(Builder, "pentium"); 3776 break; 3777 case CK_Pentium3: 3778 case CK_Pentium3M: 3779 case CK_PentiumM: 3780 Builder.defineMacro("__tune_pentium3__"); 3781 // Fallthrough 3782 case CK_Pentium2: 3783 case CK_C3_2: 3784 Builder.defineMacro("__tune_pentium2__"); 3785 // Fallthrough 3786 case CK_PentiumPro: 3787 Builder.defineMacro("__tune_i686__"); 3788 Builder.defineMacro("__tune_pentiumpro__"); 3789 // Fallthrough 3790 case CK_i686: 3791 Builder.defineMacro("__i686"); 3792 Builder.defineMacro("__i686__"); 3793 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3794 Builder.defineMacro("__pentiumpro"); 3795 Builder.defineMacro("__pentiumpro__"); 3796 break; 3797 case CK_Pentium4: 3798 case CK_Pentium4M: 3799 defineCPUMacros(Builder, "pentium4"); 3800 break; 3801 case CK_Yonah: 3802 case CK_Prescott: 3803 case CK_Nocona: 3804 defineCPUMacros(Builder, "nocona"); 3805 break; 3806 case CK_Core2: 3807 case CK_Penryn: 3808 defineCPUMacros(Builder, "core2"); 3809 break; 3810 case CK_Bonnell: 3811 defineCPUMacros(Builder, "atom"); 3812 break; 3813 case CK_Silvermont: 3814 defineCPUMacros(Builder, "slm"); 3815 break; 3816 case CK_Nehalem: 3817 case CK_Westmere: 3818 case CK_SandyBridge: 3819 case CK_IvyBridge: 3820 case CK_Haswell: 3821 case CK_Broadwell: 3822 case CK_SkylakeClient: 3823 // FIXME: Historically, we defined this legacy name, it would be nice to 3824 // remove it at some point. We've never exposed fine-grained names for 3825 // recent primary x86 CPUs, and we should keep it that way. 3826 defineCPUMacros(Builder, "corei7"); 3827 break; 3828 case CK_SkylakeServer: 3829 defineCPUMacros(Builder, "skx"); 3830 break; 3831 case CK_Cannonlake: 3832 break; 3833 case CK_KNL: 3834 defineCPUMacros(Builder, "knl"); 3835 break; 3836 case CK_Lakemont: 3837 Builder.defineMacro("__tune_lakemont__"); 3838 break; 3839 case CK_K6_2: 3840 Builder.defineMacro("__k6_2__"); 3841 Builder.defineMacro("__tune_k6_2__"); 3842 // Fallthrough 3843 case CK_K6_3: 3844 if (CPU != CK_K6_2) { // In case of fallthrough 3845 // FIXME: GCC may be enabling these in cases where some other k6 3846 // architecture is specified but -m3dnow is explicitly provided. The 3847 // exact semantics need to be determined and emulated here. 3848 Builder.defineMacro("__k6_3__"); 3849 Builder.defineMacro("__tune_k6_3__"); 3850 } 3851 // Fallthrough 3852 case CK_K6: 3853 defineCPUMacros(Builder, "k6"); 3854 break; 3855 case CK_Athlon: 3856 case CK_AthlonThunderbird: 3857 case CK_Athlon4: 3858 case CK_AthlonXP: 3859 case CK_AthlonMP: 3860 defineCPUMacros(Builder, "athlon"); 3861 if (SSELevel != NoSSE) { 3862 Builder.defineMacro("__athlon_sse__"); 3863 Builder.defineMacro("__tune_athlon_sse__"); 3864 } 3865 break; 3866 case CK_K8: 3867 case CK_K8SSE3: 3868 case CK_x86_64: 3869 case CK_Opteron: 3870 case CK_OpteronSSE3: 3871 case CK_Athlon64: 3872 case CK_Athlon64SSE3: 3873 case CK_AthlonFX: 3874 defineCPUMacros(Builder, "k8"); 3875 break; 3876 case CK_AMDFAM10: 3877 defineCPUMacros(Builder, "amdfam10"); 3878 break; 3879 case CK_BTVER1: 3880 defineCPUMacros(Builder, "btver1"); 3881 break; 3882 case CK_BTVER2: 3883 defineCPUMacros(Builder, "btver2"); 3884 break; 3885 case CK_BDVER1: 3886 defineCPUMacros(Builder, "bdver1"); 3887 break; 3888 case CK_BDVER2: 3889 defineCPUMacros(Builder, "bdver2"); 3890 break; 3891 case CK_BDVER3: 3892 defineCPUMacros(Builder, "bdver3"); 3893 break; 3894 case CK_BDVER4: 3895 defineCPUMacros(Builder, "bdver4"); 3896 break; 3897 case CK_ZNVER1: 3898 defineCPUMacros(Builder, "znver1"); 3899 break; 3900 case CK_Geode: 3901 defineCPUMacros(Builder, "geode"); 3902 break; 3903 } 3904 3905 // Target properties. 3906 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3907 3908 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3909 // functions in glibc header files that use FP Stack inline asm which the 3910 // backend can't deal with (PR879). 3911 Builder.defineMacro("__NO_MATH_INLINES"); 3912 3913 if (HasAES) 3914 Builder.defineMacro("__AES__"); 3915 3916 if (HasPCLMUL) 3917 Builder.defineMacro("__PCLMUL__"); 3918 3919 if (HasLZCNT) 3920 Builder.defineMacro("__LZCNT__"); 3921 3922 if (HasRDRND) 3923 Builder.defineMacro("__RDRND__"); 3924 3925 if (HasFSGSBASE) 3926 Builder.defineMacro("__FSGSBASE__"); 3927 3928 if (HasBMI) 3929 Builder.defineMacro("__BMI__"); 3930 3931 if (HasBMI2) 3932 Builder.defineMacro("__BMI2__"); 3933 3934 if (HasPOPCNT) 3935 Builder.defineMacro("__POPCNT__"); 3936 3937 if (HasRTM) 3938 Builder.defineMacro("__RTM__"); 3939 3940 if (HasPRFCHW) 3941 Builder.defineMacro("__PRFCHW__"); 3942 3943 if (HasRDSEED) 3944 Builder.defineMacro("__RDSEED__"); 3945 3946 if (HasADX) 3947 Builder.defineMacro("__ADX__"); 3948 3949 if (HasTBM) 3950 Builder.defineMacro("__TBM__"); 3951 3952 if (HasMWAITX) 3953 Builder.defineMacro("__MWAITX__"); 3954 3955 switch (XOPLevel) { 3956 case XOP: 3957 Builder.defineMacro("__XOP__"); 3958 case FMA4: 3959 Builder.defineMacro("__FMA4__"); 3960 case SSE4A: 3961 Builder.defineMacro("__SSE4A__"); 3962 case NoXOP: 3963 break; 3964 } 3965 3966 if (HasFMA) 3967 Builder.defineMacro("__FMA__"); 3968 3969 if (HasF16C) 3970 Builder.defineMacro("__F16C__"); 3971 3972 if (HasAVX512CD) 3973 Builder.defineMacro("__AVX512CD__"); 3974 if (HasAVX512ER) 3975 Builder.defineMacro("__AVX512ER__"); 3976 if (HasAVX512PF) 3977 Builder.defineMacro("__AVX512PF__"); 3978 if (HasAVX512DQ) 3979 Builder.defineMacro("__AVX512DQ__"); 3980 if (HasAVX512BW) 3981 Builder.defineMacro("__AVX512BW__"); 3982 if (HasAVX512VL) 3983 Builder.defineMacro("__AVX512VL__"); 3984 if (HasAVX512VBMI) 3985 Builder.defineMacro("__AVX512VBMI__"); 3986 if (HasAVX512IFMA) 3987 Builder.defineMacro("__AVX512IFMA__"); 3988 3989 if (HasSHA) 3990 Builder.defineMacro("__SHA__"); 3991 3992 if (HasFXSR) 3993 Builder.defineMacro("__FXSR__"); 3994 if (HasXSAVE) 3995 Builder.defineMacro("__XSAVE__"); 3996 if (HasXSAVEOPT) 3997 Builder.defineMacro("__XSAVEOPT__"); 3998 if (HasXSAVEC) 3999 Builder.defineMacro("__XSAVEC__"); 4000 if (HasXSAVES) 4001 Builder.defineMacro("__XSAVES__"); 4002 if (HasPKU) 4003 Builder.defineMacro("__PKU__"); 4004 if (HasCX16) 4005 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4006 if (HasCLFLUSHOPT) 4007 Builder.defineMacro("__CLFLUSHOPT__"); 4008 if (HasCLWB) 4009 Builder.defineMacro("__CLWB__"); 4010 if (HasMPX) 4011 Builder.defineMacro("__MPX__"); 4012 if (HasSGX) 4013 Builder.defineMacro("__SGX__"); 4014 if (HasPREFETCHWT1) 4015 Builder.defineMacro("__PREFETCHWT1__"); 4016 if (HasCLZERO) 4017 Builder.defineMacro("__CLZERO__"); 4018 4019 // Each case falls through to the previous one here. 4020 switch (SSELevel) { 4021 case AVX512F: 4022 Builder.defineMacro("__AVX512F__"); 4023 case AVX2: 4024 Builder.defineMacro("__AVX2__"); 4025 case AVX: 4026 Builder.defineMacro("__AVX__"); 4027 case SSE42: 4028 Builder.defineMacro("__SSE4_2__"); 4029 case SSE41: 4030 Builder.defineMacro("__SSE4_1__"); 4031 case SSSE3: 4032 Builder.defineMacro("__SSSE3__"); 4033 case SSE3: 4034 Builder.defineMacro("__SSE3__"); 4035 case SSE2: 4036 Builder.defineMacro("__SSE2__"); 4037 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4038 case SSE1: 4039 Builder.defineMacro("__SSE__"); 4040 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4041 case NoSSE: 4042 break; 4043 } 4044 4045 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4046 switch (SSELevel) { 4047 case AVX512F: 4048 case AVX2: 4049 case AVX: 4050 case SSE42: 4051 case SSE41: 4052 case SSSE3: 4053 case SSE3: 4054 case SSE2: 4055 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4056 break; 4057 case SSE1: 4058 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4059 break; 4060 default: 4061 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4062 } 4063 } 4064 4065 // Each case falls through to the previous one here. 4066 switch (MMX3DNowLevel) { 4067 case AMD3DNowAthlon: 4068 Builder.defineMacro("__3dNOW_A__"); 4069 case AMD3DNow: 4070 Builder.defineMacro("__3dNOW__"); 4071 case MMX: 4072 Builder.defineMacro("__MMX__"); 4073 case NoMMX3DNow: 4074 break; 4075 } 4076 4077 if (CPU >= CK_i486) { 4078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4079 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4080 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4081 } 4082 if (CPU >= CK_i586) 4083 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4084 } 4085 4086 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4087 return llvm::StringSwitch<bool>(Feature) 4088 .Case("aes", HasAES) 4089 .Case("avx", SSELevel >= AVX) 4090 .Case("avx2", SSELevel >= AVX2) 4091 .Case("avx512f", SSELevel >= AVX512F) 4092 .Case("avx512cd", HasAVX512CD) 4093 .Case("avx512er", HasAVX512ER) 4094 .Case("avx512pf", HasAVX512PF) 4095 .Case("avx512dq", HasAVX512DQ) 4096 .Case("avx512bw", HasAVX512BW) 4097 .Case("avx512vl", HasAVX512VL) 4098 .Case("avx512vbmi", HasAVX512VBMI) 4099 .Case("avx512ifma", HasAVX512IFMA) 4100 .Case("bmi", HasBMI) 4101 .Case("bmi2", HasBMI2) 4102 .Case("clflushopt", HasCLFLUSHOPT) 4103 .Case("clwb", HasCLWB) 4104 .Case("clzero", HasCLZERO) 4105 .Case("cx16", HasCX16) 4106 .Case("f16c", HasF16C) 4107 .Case("fma", HasFMA) 4108 .Case("fma4", XOPLevel >= FMA4) 4109 .Case("fsgsbase", HasFSGSBASE) 4110 .Case("fxsr", HasFXSR) 4111 .Case("lzcnt", HasLZCNT) 4112 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4113 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4114 .Case("mmx", MMX3DNowLevel >= MMX) 4115 .Case("movbe", HasMOVBE) 4116 .Case("mpx", HasMPX) 4117 .Case("pclmul", HasPCLMUL) 4118 .Case("pku", HasPKU) 4119 .Case("popcnt", HasPOPCNT) 4120 .Case("prefetchwt1", HasPREFETCHWT1) 4121 .Case("prfchw", HasPRFCHW) 4122 .Case("rdrnd", HasRDRND) 4123 .Case("rdseed", HasRDSEED) 4124 .Case("rtm", HasRTM) 4125 .Case("sgx", HasSGX) 4126 .Case("sha", HasSHA) 4127 .Case("sse", SSELevel >= SSE1) 4128 .Case("sse2", SSELevel >= SSE2) 4129 .Case("sse3", SSELevel >= SSE3) 4130 .Case("ssse3", SSELevel >= SSSE3) 4131 .Case("sse4.1", SSELevel >= SSE41) 4132 .Case("sse4.2", SSELevel >= SSE42) 4133 .Case("sse4a", XOPLevel >= SSE4A) 4134 .Case("tbm", HasTBM) 4135 .Case("x86", true) 4136 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4137 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4138 .Case("xop", XOPLevel >= XOP) 4139 .Case("xsave", HasXSAVE) 4140 .Case("xsavec", HasXSAVEC) 4141 .Case("xsaves", HasXSAVES) 4142 .Case("xsaveopt", HasXSAVEOPT) 4143 .Default(false); 4144 } 4145 4146 // We can't use a generic validation scheme for the features accepted here 4147 // versus subtarget features accepted in the target attribute because the 4148 // bitfield structure that's initialized in the runtime only supports the 4149 // below currently rather than the full range of subtarget features. (See 4150 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4151 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4152 return llvm::StringSwitch<bool>(FeatureStr) 4153 .Case("cmov", true) 4154 .Case("mmx", true) 4155 .Case("popcnt", true) 4156 .Case("sse", true) 4157 .Case("sse2", true) 4158 .Case("sse3", true) 4159 .Case("ssse3", true) 4160 .Case("sse4.1", true) 4161 .Case("sse4.2", true) 4162 .Case("avx", true) 4163 .Case("avx2", true) 4164 .Case("sse4a", true) 4165 .Case("fma4", true) 4166 .Case("xop", true) 4167 .Case("fma", true) 4168 .Case("avx512f", true) 4169 .Case("bmi", true) 4170 .Case("bmi2", true) 4171 .Case("aes", true) 4172 .Case("pclmul", true) 4173 .Case("avx512vl", true) 4174 .Case("avx512bw", true) 4175 .Case("avx512dq", true) 4176 .Case("avx512cd", true) 4177 .Case("avx512er", true) 4178 .Case("avx512pf", true) 4179 .Case("avx512vbmi", true) 4180 .Case("avx512ifma", true) 4181 .Default(false); 4182 } 4183 4184 bool 4185 X86TargetInfo::validateAsmConstraint(const char *&Name, 4186 TargetInfo::ConstraintInfo &Info) const { 4187 switch (*Name) { 4188 default: return false; 4189 // Constant constraints. 4190 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4191 // instructions. 4192 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4193 // x86_64 instructions. 4194 case 's': 4195 Info.setRequiresImmediate(); 4196 return true; 4197 case 'I': 4198 Info.setRequiresImmediate(0, 31); 4199 return true; 4200 case 'J': 4201 Info.setRequiresImmediate(0, 63); 4202 return true; 4203 case 'K': 4204 Info.setRequiresImmediate(-128, 127); 4205 return true; 4206 case 'L': 4207 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4208 return true; 4209 case 'M': 4210 Info.setRequiresImmediate(0, 3); 4211 return true; 4212 case 'N': 4213 Info.setRequiresImmediate(0, 255); 4214 return true; 4215 case 'O': 4216 Info.setRequiresImmediate(0, 127); 4217 return true; 4218 // Register constraints. 4219 case 'Y': // 'Y' is the first character for several 2-character constraints. 4220 // Shift the pointer to the second character of the constraint. 4221 Name++; 4222 switch (*Name) { 4223 default: 4224 return false; 4225 case '0': // First SSE register. 4226 case 't': // Any SSE register, when SSE2 is enabled. 4227 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4228 case 'm': // Any MMX register, when inter-unit moves enabled. 4229 case 'k': // AVX512 arch mask registers: k1-k7. 4230 Info.setAllowsRegister(); 4231 return true; 4232 } 4233 case 'f': // Any x87 floating point stack register. 4234 // Constraint 'f' cannot be used for output operands. 4235 if (Info.ConstraintStr[0] == '=') 4236 return false; 4237 Info.setAllowsRegister(); 4238 return true; 4239 case 'a': // eax. 4240 case 'b': // ebx. 4241 case 'c': // ecx. 4242 case 'd': // edx. 4243 case 'S': // esi. 4244 case 'D': // edi. 4245 case 'A': // edx:eax. 4246 case 't': // Top of floating point stack. 4247 case 'u': // Second from top of floating point stack. 4248 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4249 case 'y': // Any MMX register. 4250 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4251 case 'x': // Any SSE register. 4252 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4253 // for intermideate k reg operations). 4254 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4255 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4256 case 'l': // "Index" registers: any general register that can be used as an 4257 // index in a base+index memory access. 4258 Info.setAllowsRegister(); 4259 return true; 4260 // Floating point constant constraints. 4261 case 'C': // SSE floating point constant. 4262 case 'G': // x87 floating point constant. 4263 return true; 4264 } 4265 } 4266 4267 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4268 unsigned Size) const { 4269 // Strip off constraint modifiers. 4270 while (Constraint[0] == '=' || 4271 Constraint[0] == '+' || 4272 Constraint[0] == '&') 4273 Constraint = Constraint.substr(1); 4274 4275 return validateOperandSize(Constraint, Size); 4276 } 4277 4278 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4279 unsigned Size) const { 4280 return validateOperandSize(Constraint, Size); 4281 } 4282 4283 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4284 unsigned Size) const { 4285 switch (Constraint[0]) { 4286 default: break; 4287 case 'k': 4288 // Registers k0-k7 (AVX512) size limit is 64 bit. 4289 case 'y': 4290 return Size <= 64; 4291 case 'f': 4292 case 't': 4293 case 'u': 4294 return Size <= 128; 4295 case 'v': 4296 case 'x': 4297 if (SSELevel >= AVX512F) 4298 // 512-bit zmm registers can be used if target supports AVX512F. 4299 return Size <= 512U; 4300 else if (SSELevel >= AVX) 4301 // 256-bit ymm registers can be used if target supports AVX. 4302 return Size <= 256U; 4303 return Size <= 128U; 4304 case 'Y': 4305 // 'Y' is the first character for several 2-character constraints. 4306 switch (Constraint[1]) { 4307 default: break; 4308 case 'm': 4309 // 'Ym' is synonymous with 'y'. 4310 case 'k': 4311 return Size <= 64; 4312 case 'i': 4313 case 't': 4314 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4315 if (SSELevel >= AVX512F) 4316 return Size <= 512U; 4317 else if (SSELevel >= AVX) 4318 return Size <= 256U; 4319 return SSELevel >= SSE2 && Size <= 128U; 4320 } 4321 4322 } 4323 4324 return true; 4325 } 4326 4327 std::string 4328 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4329 switch (*Constraint) { 4330 case 'a': return std::string("{ax}"); 4331 case 'b': return std::string("{bx}"); 4332 case 'c': return std::string("{cx}"); 4333 case 'd': return std::string("{dx}"); 4334 case 'S': return std::string("{si}"); 4335 case 'D': return std::string("{di}"); 4336 case 'p': // address 4337 return std::string("im"); 4338 case 't': // top of floating point stack. 4339 return std::string("{st}"); 4340 case 'u': // second from top of floating point stack. 4341 return std::string("{st(1)}"); // second from top of floating point stack. 4342 case 'Y': 4343 switch (Constraint[1]) { 4344 default: 4345 // Break from inner switch and fall through (copy single char), 4346 // continue parsing after copying the current constraint into 4347 // the return string. 4348 break; 4349 case 'k': 4350 // "^" hints llvm that this is a 2 letter constraint. 4351 // "Constraint++" is used to promote the string iterator 4352 // to the next constraint. 4353 return std::string("^") + std::string(Constraint++, 2); 4354 } 4355 LLVM_FALLTHROUGH; 4356 default: 4357 return std::string(1, *Constraint); 4358 } 4359 } 4360 4361 // X86-32 generic target 4362 class X86_32TargetInfo : public X86TargetInfo { 4363 public: 4364 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4365 : X86TargetInfo(Triple, Opts) { 4366 DoubleAlign = LongLongAlign = 32; 4367 LongDoubleWidth = 96; 4368 LongDoubleAlign = 32; 4369 SuitableAlign = 128; 4370 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4371 SizeType = UnsignedInt; 4372 PtrDiffType = SignedInt; 4373 IntPtrType = SignedInt; 4374 RegParmMax = 3; 4375 4376 // Use fpret for all types. 4377 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4378 (1 << TargetInfo::Double) | 4379 (1 << TargetInfo::LongDouble)); 4380 4381 // x86-32 has atomics up to 8 bytes 4382 // FIXME: Check that we actually have cmpxchg8b before setting 4383 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4384 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4385 } 4386 BuiltinVaListKind getBuiltinVaListKind() const override { 4387 return TargetInfo::CharPtrBuiltinVaList; 4388 } 4389 4390 int getEHDataRegisterNumber(unsigned RegNo) const override { 4391 if (RegNo == 0) return 0; 4392 if (RegNo == 1) return 2; 4393 return -1; 4394 } 4395 bool validateOperandSize(StringRef Constraint, 4396 unsigned Size) const override { 4397 switch (Constraint[0]) { 4398 default: break; 4399 case 'R': 4400 case 'q': 4401 case 'Q': 4402 case 'a': 4403 case 'b': 4404 case 'c': 4405 case 'd': 4406 case 'S': 4407 case 'D': 4408 return Size <= 32; 4409 case 'A': 4410 return Size <= 64; 4411 } 4412 4413 return X86TargetInfo::validateOperandSize(Constraint, Size); 4414 } 4415 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4416 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4417 Builtin::FirstTSBuiltin + 1); 4418 } 4419 }; 4420 4421 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4422 public: 4423 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4424 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4425 4426 unsigned getFloatEvalMethod() const override { 4427 unsigned Major, Minor, Micro; 4428 getTriple().getOSVersion(Major, Minor, Micro); 4429 // New NetBSD uses the default rounding mode. 4430 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4431 return X86_32TargetInfo::getFloatEvalMethod(); 4432 // NetBSD before 6.99.26 defaults to "double" rounding. 4433 return 1; 4434 } 4435 }; 4436 4437 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4438 public: 4439 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4440 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4441 SizeType = UnsignedLong; 4442 IntPtrType = SignedLong; 4443 PtrDiffType = SignedLong; 4444 } 4445 }; 4446 4447 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4448 public: 4449 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4450 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4451 SizeType = UnsignedLong; 4452 IntPtrType = SignedLong; 4453 PtrDiffType = SignedLong; 4454 } 4455 }; 4456 4457 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4458 public: 4459 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4460 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4461 LongDoubleWidth = 128; 4462 LongDoubleAlign = 128; 4463 SuitableAlign = 128; 4464 MaxVectorAlign = 256; 4465 // The watchOS simulator uses the builtin bool type for Objective-C. 4466 llvm::Triple T = llvm::Triple(Triple); 4467 if (T.isWatchOS()) 4468 UseSignedCharForObjCBool = false; 4469 SizeType = UnsignedLong; 4470 IntPtrType = SignedLong; 4471 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4472 HasAlignMac68kSupport = true; 4473 } 4474 4475 bool handleTargetFeatures(std::vector<std::string> &Features, 4476 DiagnosticsEngine &Diags) override { 4477 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4478 Diags)) 4479 return false; 4480 // We now know the features we have: we can decide how to align vectors. 4481 MaxVectorAlign = 4482 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4483 return true; 4484 } 4485 }; 4486 4487 // x86-32 Windows target 4488 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4489 public: 4490 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4491 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4492 WCharType = UnsignedShort; 4493 DoubleAlign = LongLongAlign = 64; 4494 bool IsWinCOFF = 4495 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4496 resetDataLayout(IsWinCOFF 4497 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4498 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4499 } 4500 void getTargetDefines(const LangOptions &Opts, 4501 MacroBuilder &Builder) const override { 4502 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4503 } 4504 }; 4505 4506 // x86-32 Windows Visual Studio target 4507 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4508 public: 4509 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4510 const TargetOptions &Opts) 4511 : WindowsX86_32TargetInfo(Triple, Opts) { 4512 LongDoubleWidth = LongDoubleAlign = 64; 4513 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4514 } 4515 void getTargetDefines(const LangOptions &Opts, 4516 MacroBuilder &Builder) const override { 4517 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4518 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4519 // The value of the following reflects processor type. 4520 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4521 // We lost the original triple, so we use the default. 4522 Builder.defineMacro("_M_IX86", "600"); 4523 } 4524 }; 4525 4526 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4527 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4528 // supports __declspec natively under -fms-extensions, but we define a no-op 4529 // __declspec macro anyway for pre-processor compatibility. 4530 if (Opts.MicrosoftExt) 4531 Builder.defineMacro("__declspec", "__declspec"); 4532 else 4533 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4534 4535 if (!Opts.MicrosoftExt) { 4536 // Provide macros for all the calling convention keywords. Provide both 4537 // single and double underscore prefixed variants. These are available on 4538 // x64 as well as x86, even though they have no effect. 4539 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4540 for (const char *CC : CCs) { 4541 std::string GCCSpelling = "__attribute__((__"; 4542 GCCSpelling += CC; 4543 GCCSpelling += "__))"; 4544 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4545 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4546 } 4547 } 4548 } 4549 4550 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4551 Builder.defineMacro("__MSVCRT__"); 4552 Builder.defineMacro("__MINGW32__"); 4553 addCygMingDefines(Opts, Builder); 4554 } 4555 4556 // x86-32 MinGW target 4557 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4558 public: 4559 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4560 : WindowsX86_32TargetInfo(Triple, Opts) {} 4561 void getTargetDefines(const LangOptions &Opts, 4562 MacroBuilder &Builder) const override { 4563 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4564 DefineStd(Builder, "WIN32", Opts); 4565 DefineStd(Builder, "WINNT", Opts); 4566 Builder.defineMacro("_X86_"); 4567 addMinGWDefines(Opts, Builder); 4568 } 4569 }; 4570 4571 // x86-32 Cygwin target 4572 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4573 public: 4574 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4575 : X86_32TargetInfo(Triple, Opts) { 4576 WCharType = UnsignedShort; 4577 DoubleAlign = LongLongAlign = 64; 4578 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4579 } 4580 void getTargetDefines(const LangOptions &Opts, 4581 MacroBuilder &Builder) const override { 4582 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4583 Builder.defineMacro("_X86_"); 4584 Builder.defineMacro("__CYGWIN__"); 4585 Builder.defineMacro("__CYGWIN32__"); 4586 addCygMingDefines(Opts, Builder); 4587 DefineStd(Builder, "unix", Opts); 4588 if (Opts.CPlusPlus) 4589 Builder.defineMacro("_GNU_SOURCE"); 4590 } 4591 }; 4592 4593 // x86-32 Haiku target 4594 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4595 public: 4596 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4597 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4598 } 4599 void getTargetDefines(const LangOptions &Opts, 4600 MacroBuilder &Builder) const override { 4601 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4602 Builder.defineMacro("__INTEL__"); 4603 } 4604 }; 4605 4606 // X86-32 MCU target 4607 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4608 public: 4609 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4610 : X86_32TargetInfo(Triple, Opts) { 4611 LongDoubleWidth = 64; 4612 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4613 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4614 WIntType = UnsignedInt; 4615 } 4616 4617 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4618 // On MCU we support only C calling convention. 4619 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4620 } 4621 4622 void getTargetDefines(const LangOptions &Opts, 4623 MacroBuilder &Builder) const override { 4624 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4625 Builder.defineMacro("__iamcu"); 4626 Builder.defineMacro("__iamcu__"); 4627 } 4628 4629 bool allowsLargerPreferedTypeAlignment() const override { 4630 return false; 4631 } 4632 }; 4633 4634 // RTEMS Target 4635 template<typename Target> 4636 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4637 protected: 4638 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4639 MacroBuilder &Builder) const override { 4640 // RTEMS defines; list based off of gcc output 4641 4642 Builder.defineMacro("__rtems__"); 4643 Builder.defineMacro("__ELF__"); 4644 } 4645 4646 public: 4647 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4648 : OSTargetInfo<Target>(Triple, Opts) { 4649 switch (Triple.getArch()) { 4650 default: 4651 case llvm::Triple::x86: 4652 // this->MCountName = ".mcount"; 4653 break; 4654 case llvm::Triple::mips: 4655 case llvm::Triple::mipsel: 4656 case llvm::Triple::ppc: 4657 case llvm::Triple::ppc64: 4658 case llvm::Triple::ppc64le: 4659 // this->MCountName = "_mcount"; 4660 break; 4661 case llvm::Triple::arm: 4662 // this->MCountName = "__mcount"; 4663 break; 4664 } 4665 } 4666 }; 4667 4668 // x86-32 RTEMS target 4669 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4670 public: 4671 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4672 : X86_32TargetInfo(Triple, Opts) { 4673 SizeType = UnsignedLong; 4674 IntPtrType = SignedLong; 4675 PtrDiffType = SignedLong; 4676 } 4677 void getTargetDefines(const LangOptions &Opts, 4678 MacroBuilder &Builder) const override { 4679 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4680 Builder.defineMacro("__INTEL__"); 4681 Builder.defineMacro("__rtems__"); 4682 } 4683 }; 4684 4685 // x86-64 generic target 4686 class X86_64TargetInfo : public X86TargetInfo { 4687 public: 4688 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4689 : X86TargetInfo(Triple, Opts) { 4690 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4691 bool IsWinCOFF = 4692 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4693 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4694 LongDoubleWidth = 128; 4695 LongDoubleAlign = 128; 4696 LargeArrayMinWidth = 128; 4697 LargeArrayAlign = 128; 4698 SuitableAlign = 128; 4699 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4700 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4701 IntPtrType = IsX32 ? SignedInt : SignedLong; 4702 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4703 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4704 RegParmMax = 6; 4705 4706 // Pointers are 32-bit in x32. 4707 resetDataLayout(IsX32 4708 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4709 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4710 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4711 4712 // Use fpret only for long double. 4713 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4714 4715 // Use fp2ret for _Complex long double. 4716 ComplexLongDoubleUsesFP2Ret = true; 4717 4718 // Make __builtin_ms_va_list available. 4719 HasBuiltinMSVaList = true; 4720 4721 // x86-64 has atomics up to 16 bytes. 4722 MaxAtomicPromoteWidth = 128; 4723 MaxAtomicInlineWidth = 128; 4724 } 4725 BuiltinVaListKind getBuiltinVaListKind() const override { 4726 return TargetInfo::X86_64ABIBuiltinVaList; 4727 } 4728 4729 int getEHDataRegisterNumber(unsigned RegNo) const override { 4730 if (RegNo == 0) return 0; 4731 if (RegNo == 1) return 1; 4732 return -1; 4733 } 4734 4735 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4736 switch (CC) { 4737 case CC_C: 4738 case CC_Swift: 4739 case CC_X86VectorCall: 4740 case CC_IntelOclBicc: 4741 case CC_X86_64Win64: 4742 case CC_PreserveMost: 4743 case CC_PreserveAll: 4744 case CC_X86RegCall: 4745 return CCCR_OK; 4746 default: 4747 return CCCR_Warning; 4748 } 4749 } 4750 4751 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4752 return CC_C; 4753 } 4754 4755 // for x32 we need it here explicitly 4756 bool hasInt128Type() const override { return true; } 4757 unsigned getUnwindWordWidth() const override { return 64; } 4758 unsigned getRegisterWidth() const override { return 64; } 4759 4760 bool validateGlobalRegisterVariable(StringRef RegName, 4761 unsigned RegSize, 4762 bool &HasSizeMismatch) const override { 4763 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4764 // handle. 4765 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4766 // Check that the register size is 64-bit. 4767 HasSizeMismatch = RegSize != 64; 4768 return true; 4769 } 4770 4771 // Check if the register is a 32-bit register the backend can handle. 4772 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4773 HasSizeMismatch); 4774 } 4775 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4776 return llvm::makeArrayRef(BuiltinInfoX86, 4777 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4778 } 4779 }; 4780 4781 // x86-64 Windows target 4782 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4783 public: 4784 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4785 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4786 WCharType = UnsignedShort; 4787 LongWidth = LongAlign = 32; 4788 DoubleAlign = LongLongAlign = 64; 4789 IntMaxType = SignedLongLong; 4790 Int64Type = SignedLongLong; 4791 SizeType = UnsignedLongLong; 4792 PtrDiffType = SignedLongLong; 4793 IntPtrType = SignedLongLong; 4794 } 4795 4796 void getTargetDefines(const LangOptions &Opts, 4797 MacroBuilder &Builder) const override { 4798 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4799 Builder.defineMacro("_WIN64"); 4800 } 4801 4802 BuiltinVaListKind getBuiltinVaListKind() const override { 4803 return TargetInfo::CharPtrBuiltinVaList; 4804 } 4805 4806 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4807 switch (CC) { 4808 case CC_X86StdCall: 4809 case CC_X86ThisCall: 4810 case CC_X86FastCall: 4811 return CCCR_Ignore; 4812 case CC_C: 4813 case CC_X86VectorCall: 4814 case CC_IntelOclBicc: 4815 case CC_X86_64SysV: 4816 case CC_Swift: 4817 case CC_X86RegCall: 4818 return CCCR_OK; 4819 default: 4820 return CCCR_Warning; 4821 } 4822 } 4823 }; 4824 4825 // x86-64 Windows Visual Studio target 4826 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4827 public: 4828 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4829 const TargetOptions &Opts) 4830 : WindowsX86_64TargetInfo(Triple, Opts) { 4831 LongDoubleWidth = LongDoubleAlign = 64; 4832 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4833 } 4834 void getTargetDefines(const LangOptions &Opts, 4835 MacroBuilder &Builder) const override { 4836 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4837 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4838 Builder.defineMacro("_M_X64", "100"); 4839 Builder.defineMacro("_M_AMD64", "100"); 4840 } 4841 }; 4842 4843 // x86-64 MinGW target 4844 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4845 public: 4846 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4847 : WindowsX86_64TargetInfo(Triple, Opts) { 4848 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4849 // with x86 FP ops. Weird. 4850 LongDoubleWidth = LongDoubleAlign = 128; 4851 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4852 } 4853 4854 void getTargetDefines(const LangOptions &Opts, 4855 MacroBuilder &Builder) const override { 4856 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4857 DefineStd(Builder, "WIN64", Opts); 4858 Builder.defineMacro("__MINGW64__"); 4859 addMinGWDefines(Opts, Builder); 4860 4861 // GCC defines this macro when it is using __gxx_personality_seh0. 4862 if (!Opts.SjLjExceptions) 4863 Builder.defineMacro("__SEH__"); 4864 } 4865 }; 4866 4867 // x86-64 Cygwin target 4868 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4869 public: 4870 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4871 : X86_64TargetInfo(Triple, Opts) { 4872 TLSSupported = false; 4873 WCharType = UnsignedShort; 4874 } 4875 void getTargetDefines(const LangOptions &Opts, 4876 MacroBuilder &Builder) const override { 4877 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4878 Builder.defineMacro("__x86_64__"); 4879 Builder.defineMacro("__CYGWIN__"); 4880 Builder.defineMacro("__CYGWIN64__"); 4881 addCygMingDefines(Opts, Builder); 4882 DefineStd(Builder, "unix", Opts); 4883 if (Opts.CPlusPlus) 4884 Builder.defineMacro("_GNU_SOURCE"); 4885 4886 // GCC defines this macro when it is using __gxx_personality_seh0. 4887 if (!Opts.SjLjExceptions) 4888 Builder.defineMacro("__SEH__"); 4889 } 4890 }; 4891 4892 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4893 public: 4894 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4895 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4896 Int64Type = SignedLongLong; 4897 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4898 llvm::Triple T = llvm::Triple(Triple); 4899 if (T.isiOS()) 4900 UseSignedCharForObjCBool = false; 4901 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4902 } 4903 4904 bool handleTargetFeatures(std::vector<std::string> &Features, 4905 DiagnosticsEngine &Diags) override { 4906 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4907 Diags)) 4908 return false; 4909 // We now know the features we have: we can decide how to align vectors. 4910 MaxVectorAlign = 4911 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4912 return true; 4913 } 4914 }; 4915 4916 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4917 public: 4918 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4919 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4920 IntMaxType = SignedLongLong; 4921 Int64Type = SignedLongLong; 4922 } 4923 }; 4924 4925 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4926 public: 4927 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4928 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4929 IntMaxType = SignedLongLong; 4930 Int64Type = SignedLongLong; 4931 } 4932 }; 4933 4934 class ARMTargetInfo : public TargetInfo { 4935 // Possible FPU choices. 4936 enum FPUMode { 4937 VFP2FPU = (1 << 0), 4938 VFP3FPU = (1 << 1), 4939 VFP4FPU = (1 << 2), 4940 NeonFPU = (1 << 3), 4941 FPARMV8 = (1 << 4) 4942 }; 4943 4944 // Possible HWDiv features. 4945 enum HWDivMode { 4946 HWDivThumb = (1 << 0), 4947 HWDivARM = (1 << 1) 4948 }; 4949 4950 static bool FPUModeIsVFP(FPUMode Mode) { 4951 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4952 } 4953 4954 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4955 static const char * const GCCRegNames[]; 4956 4957 std::string ABI, CPU; 4958 4959 StringRef CPUProfile; 4960 StringRef CPUAttr; 4961 4962 enum { 4963 FP_Default, 4964 FP_VFP, 4965 FP_Neon 4966 } FPMath; 4967 4968 unsigned ArchISA; 4969 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4970 unsigned ArchProfile; 4971 unsigned ArchVersion; 4972 4973 unsigned FPU : 5; 4974 4975 unsigned IsAAPCS : 1; 4976 unsigned HWDiv : 2; 4977 4978 // Initialized via features. 4979 unsigned SoftFloat : 1; 4980 unsigned SoftFloatABI : 1; 4981 4982 unsigned CRC : 1; 4983 unsigned Crypto : 1; 4984 unsigned DSP : 1; 4985 unsigned Unaligned : 1; 4986 4987 enum { 4988 LDREX_B = (1 << 0), /// byte (8-bit) 4989 LDREX_H = (1 << 1), /// half (16-bit) 4990 LDREX_W = (1 << 2), /// word (32-bit) 4991 LDREX_D = (1 << 3), /// double (64-bit) 4992 }; 4993 4994 uint32_t LDREX; 4995 4996 // ACLE 6.5.1 Hardware floating point 4997 enum { 4998 HW_FP_HP = (1 << 1), /// half (16-bit) 4999 HW_FP_SP = (1 << 2), /// single (32-bit) 5000 HW_FP_DP = (1 << 3), /// double (64-bit) 5001 }; 5002 uint32_t HW_FP; 5003 5004 static const Builtin::Info BuiltinInfo[]; 5005 5006 void setABIAAPCS() { 5007 IsAAPCS = true; 5008 5009 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5010 const llvm::Triple &T = getTriple(); 5011 5012 // size_t is unsigned long on MachO-derived environments, NetBSD, 5013 // OpenBSD and Bitrig. 5014 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5015 T.getOS() == llvm::Triple::OpenBSD || 5016 T.getOS() == llvm::Triple::Bitrig) 5017 SizeType = UnsignedLong; 5018 else 5019 SizeType = UnsignedInt; 5020 5021 switch (T.getOS()) { 5022 case llvm::Triple::NetBSD: 5023 case llvm::Triple::OpenBSD: 5024 WCharType = SignedInt; 5025 break; 5026 case llvm::Triple::Win32: 5027 WCharType = UnsignedShort; 5028 break; 5029 case llvm::Triple::Linux: 5030 default: 5031 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5032 WCharType = UnsignedInt; 5033 break; 5034 } 5035 5036 UseBitFieldTypeAlignment = true; 5037 5038 ZeroLengthBitfieldBoundary = 0; 5039 5040 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5041 // so set preferred for small types to 32. 5042 if (T.isOSBinFormatMachO()) { 5043 resetDataLayout(BigEndian 5044 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5045 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5046 } else if (T.isOSWindows()) { 5047 assert(!BigEndian && "Windows on ARM does not support big endian"); 5048 resetDataLayout("e" 5049 "-m:w" 5050 "-p:32:32" 5051 "-i64:64" 5052 "-v128:64:128" 5053 "-a:0:32" 5054 "-n32" 5055 "-S64"); 5056 } else if (T.isOSNaCl()) { 5057 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5058 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5059 } else { 5060 resetDataLayout(BigEndian 5061 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5062 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5063 } 5064 5065 // FIXME: Enumerated types are variable width in straight AAPCS. 5066 } 5067 5068 void setABIAPCS(bool IsAAPCS16) { 5069 const llvm::Triple &T = getTriple(); 5070 5071 IsAAPCS = false; 5072 5073 if (IsAAPCS16) 5074 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5075 else 5076 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5077 5078 // size_t is unsigned int on FreeBSD. 5079 if (T.getOS() == llvm::Triple::FreeBSD) 5080 SizeType = UnsignedInt; 5081 else 5082 SizeType = UnsignedLong; 5083 5084 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5085 WCharType = SignedInt; 5086 5087 // Do not respect the alignment of bit-field types when laying out 5088 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5089 UseBitFieldTypeAlignment = false; 5090 5091 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5092 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5093 /// gcc. 5094 ZeroLengthBitfieldBoundary = 32; 5095 5096 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5097 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5098 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5099 } else if (T.isOSBinFormatMachO()) 5100 resetDataLayout( 5101 BigEndian 5102 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5103 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5104 else 5105 resetDataLayout( 5106 BigEndian 5107 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5108 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5109 5110 // FIXME: Override "preferred align" for double and long long. 5111 } 5112 5113 void setArchInfo() { 5114 StringRef ArchName = getTriple().getArchName(); 5115 5116 ArchISA = llvm::ARM::parseArchISA(ArchName); 5117 CPU = llvm::ARM::getDefaultCPU(ArchName); 5118 unsigned AK = llvm::ARM::parseArch(ArchName); 5119 if (AK != llvm::ARM::AK_INVALID) 5120 ArchKind = AK; 5121 setArchInfo(ArchKind); 5122 } 5123 5124 void setArchInfo(unsigned Kind) { 5125 StringRef SubArch; 5126 5127 // cache TargetParser info 5128 ArchKind = Kind; 5129 SubArch = llvm::ARM::getSubArch(ArchKind); 5130 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5131 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5132 5133 // cache CPU related strings 5134 CPUAttr = getCPUAttr(); 5135 CPUProfile = getCPUProfile(); 5136 } 5137 5138 void setAtomic() { 5139 // when triple does not specify a sub arch, 5140 // then we are not using inline atomics 5141 bool ShouldUseInlineAtomic = 5142 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5143 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5144 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5145 if (ArchProfile == llvm::ARM::PK_M) { 5146 MaxAtomicPromoteWidth = 32; 5147 if (ShouldUseInlineAtomic) 5148 MaxAtomicInlineWidth = 32; 5149 } 5150 else { 5151 MaxAtomicPromoteWidth = 64; 5152 if (ShouldUseInlineAtomic) 5153 MaxAtomicInlineWidth = 64; 5154 } 5155 } 5156 5157 bool isThumb() const { 5158 return (ArchISA == llvm::ARM::IK_THUMB); 5159 } 5160 5161 bool supportsThumb() const { 5162 return CPUAttr.count('T') || ArchVersion >= 6; 5163 } 5164 5165 bool supportsThumb2() const { 5166 return CPUAttr.equals("6T2") || 5167 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5168 } 5169 5170 StringRef getCPUAttr() const { 5171 // For most sub-arches, the build attribute CPU name is enough. 5172 // For Cortex variants, it's slightly different. 5173 switch(ArchKind) { 5174 default: 5175 return llvm::ARM::getCPUAttr(ArchKind); 5176 case llvm::ARM::AK_ARMV6M: 5177 return "6M"; 5178 case llvm::ARM::AK_ARMV7S: 5179 return "7S"; 5180 case llvm::ARM::AK_ARMV7A: 5181 return "7A"; 5182 case llvm::ARM::AK_ARMV7R: 5183 return "7R"; 5184 case llvm::ARM::AK_ARMV7M: 5185 return "7M"; 5186 case llvm::ARM::AK_ARMV7EM: 5187 return "7EM"; 5188 case llvm::ARM::AK_ARMV7VE: 5189 return "7VE"; 5190 case llvm::ARM::AK_ARMV8A: 5191 return "8A"; 5192 case llvm::ARM::AK_ARMV8_1A: 5193 return "8_1A"; 5194 case llvm::ARM::AK_ARMV8_2A: 5195 return "8_2A"; 5196 case llvm::ARM::AK_ARMV8MBaseline: 5197 return "8M_BASE"; 5198 case llvm::ARM::AK_ARMV8MMainline: 5199 return "8M_MAIN"; 5200 case llvm::ARM::AK_ARMV8R: 5201 return "8R"; 5202 } 5203 } 5204 5205 StringRef getCPUProfile() const { 5206 switch(ArchProfile) { 5207 case llvm::ARM::PK_A: 5208 return "A"; 5209 case llvm::ARM::PK_R: 5210 return "R"; 5211 case llvm::ARM::PK_M: 5212 return "M"; 5213 default: 5214 return ""; 5215 } 5216 } 5217 5218 public: 5219 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5220 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5221 HW_FP(0) { 5222 5223 switch (getTriple().getOS()) { 5224 case llvm::Triple::NetBSD: 5225 case llvm::Triple::OpenBSD: 5226 PtrDiffType = SignedLong; 5227 break; 5228 default: 5229 PtrDiffType = SignedInt; 5230 break; 5231 } 5232 5233 // Cache arch related info. 5234 setArchInfo(); 5235 5236 // {} in inline assembly are neon specifiers, not assembly variant 5237 // specifiers. 5238 NoAsmVariants = true; 5239 5240 // FIXME: This duplicates code from the driver that sets the -target-abi 5241 // option - this code is used if -target-abi isn't passed and should 5242 // be unified in some way. 5243 if (Triple.isOSBinFormatMachO()) { 5244 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5245 // the frontend matches that. 5246 if (Triple.getEnvironment() == llvm::Triple::EABI || 5247 Triple.getOS() == llvm::Triple::UnknownOS || 5248 ArchProfile == llvm::ARM::PK_M) { 5249 setABI("aapcs"); 5250 } else if (Triple.isWatchABI()) { 5251 setABI("aapcs16"); 5252 } else { 5253 setABI("apcs-gnu"); 5254 } 5255 } else if (Triple.isOSWindows()) { 5256 // FIXME: this is invalid for WindowsCE 5257 setABI("aapcs"); 5258 } else { 5259 // Select the default based on the platform. 5260 switch (Triple.getEnvironment()) { 5261 case llvm::Triple::Android: 5262 case llvm::Triple::GNUEABI: 5263 case llvm::Triple::GNUEABIHF: 5264 case llvm::Triple::MuslEABI: 5265 case llvm::Triple::MuslEABIHF: 5266 setABI("aapcs-linux"); 5267 break; 5268 case llvm::Triple::EABIHF: 5269 case llvm::Triple::EABI: 5270 setABI("aapcs"); 5271 break; 5272 case llvm::Triple::GNU: 5273 setABI("apcs-gnu"); 5274 break; 5275 default: 5276 if (Triple.getOS() == llvm::Triple::NetBSD) 5277 setABI("apcs-gnu"); 5278 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5279 setABI("aapcs-linux"); 5280 else 5281 setABI("aapcs"); 5282 break; 5283 } 5284 } 5285 5286 // ARM targets default to using the ARM C++ ABI. 5287 TheCXXABI.set(TargetCXXABI::GenericARM); 5288 5289 // ARM has atomics up to 8 bytes 5290 setAtomic(); 5291 5292 // Do force alignment of members that follow zero length bitfields. If 5293 // the alignment of the zero-length bitfield is greater than the member 5294 // that follows it, `bar', `bar' will be aligned as the type of the 5295 // zero length bitfield. 5296 UseZeroLengthBitfieldAlignment = true; 5297 5298 if (Triple.getOS() == llvm::Triple::Linux || 5299 Triple.getOS() == llvm::Triple::UnknownOS) 5300 this->MCountName = 5301 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5302 } 5303 5304 StringRef getABI() const override { return ABI; } 5305 5306 bool setABI(const std::string &Name) override { 5307 ABI = Name; 5308 5309 // The defaults (above) are for AAPCS, check if we need to change them. 5310 // 5311 // FIXME: We need support for -meabi... we could just mangle it into the 5312 // name. 5313 if (Name == "apcs-gnu" || Name == "aapcs16") { 5314 setABIAPCS(Name == "aapcs16"); 5315 return true; 5316 } 5317 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5318 setABIAAPCS(); 5319 return true; 5320 } 5321 return false; 5322 } 5323 5324 // FIXME: This should be based on Arch attributes, not CPU names. 5325 bool 5326 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5327 StringRef CPU, 5328 const std::vector<std::string> &FeaturesVec) const override { 5329 5330 std::vector<StringRef> TargetFeatures; 5331 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5332 5333 // get default FPU features 5334 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5335 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5336 5337 // get default Extension features 5338 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5339 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5340 5341 for (auto Feature : TargetFeatures) 5342 if (Feature[0] == '+') 5343 Features[Feature.drop_front(1)] = true; 5344 5345 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5346 } 5347 5348 bool handleTargetFeatures(std::vector<std::string> &Features, 5349 DiagnosticsEngine &Diags) override { 5350 FPU = 0; 5351 CRC = 0; 5352 Crypto = 0; 5353 DSP = 0; 5354 Unaligned = 1; 5355 SoftFloat = SoftFloatABI = false; 5356 HWDiv = 0; 5357 5358 // This does not diagnose illegal cases like having both 5359 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5360 uint32_t HW_FP_remove = 0; 5361 for (const auto &Feature : Features) { 5362 if (Feature == "+soft-float") { 5363 SoftFloat = true; 5364 } else if (Feature == "+soft-float-abi") { 5365 SoftFloatABI = true; 5366 } else if (Feature == "+vfp2") { 5367 FPU |= VFP2FPU; 5368 HW_FP |= HW_FP_SP | HW_FP_DP; 5369 } else if (Feature == "+vfp3") { 5370 FPU |= VFP3FPU; 5371 HW_FP |= HW_FP_SP | HW_FP_DP; 5372 } else if (Feature == "+vfp4") { 5373 FPU |= VFP4FPU; 5374 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5375 } else if (Feature == "+fp-armv8") { 5376 FPU |= FPARMV8; 5377 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5378 } else if (Feature == "+neon") { 5379 FPU |= NeonFPU; 5380 HW_FP |= HW_FP_SP | HW_FP_DP; 5381 } else if (Feature == "+hwdiv") { 5382 HWDiv |= HWDivThumb; 5383 } else if (Feature == "+hwdiv-arm") { 5384 HWDiv |= HWDivARM; 5385 } else if (Feature == "+crc") { 5386 CRC = 1; 5387 } else if (Feature == "+crypto") { 5388 Crypto = 1; 5389 } else if (Feature == "+dsp") { 5390 DSP = 1; 5391 } else if (Feature == "+fp-only-sp") { 5392 HW_FP_remove |= HW_FP_DP; 5393 } else if (Feature == "+strict-align") { 5394 Unaligned = 0; 5395 } else if (Feature == "+fp16") { 5396 HW_FP |= HW_FP_HP; 5397 } 5398 } 5399 HW_FP &= ~HW_FP_remove; 5400 5401 switch (ArchVersion) { 5402 case 6: 5403 if (ArchProfile == llvm::ARM::PK_M) 5404 LDREX = 0; 5405 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5406 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5407 else 5408 LDREX = LDREX_W; 5409 break; 5410 case 7: 5411 if (ArchProfile == llvm::ARM::PK_M) 5412 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5413 else 5414 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5415 break; 5416 case 8: 5417 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5418 } 5419 5420 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5421 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5422 return false; 5423 } 5424 5425 if (FPMath == FP_Neon) 5426 Features.push_back("+neonfp"); 5427 else if (FPMath == FP_VFP) 5428 Features.push_back("-neonfp"); 5429 5430 // Remove front-end specific options which the backend handles differently. 5431 auto Feature = 5432 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5433 if (Feature != Features.end()) 5434 Features.erase(Feature); 5435 5436 return true; 5437 } 5438 5439 bool hasFeature(StringRef Feature) const override { 5440 return llvm::StringSwitch<bool>(Feature) 5441 .Case("arm", true) 5442 .Case("aarch32", true) 5443 .Case("softfloat", SoftFloat) 5444 .Case("thumb", isThumb()) 5445 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5446 .Case("hwdiv", HWDiv & HWDivThumb) 5447 .Case("hwdiv-arm", HWDiv & HWDivARM) 5448 .Default(false); 5449 } 5450 5451 bool setCPU(const std::string &Name) override { 5452 if (Name != "generic") 5453 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5454 5455 if (ArchKind == llvm::ARM::AK_INVALID) 5456 return false; 5457 setAtomic(); 5458 CPU = Name; 5459 return true; 5460 } 5461 5462 bool setFPMath(StringRef Name) override; 5463 5464 void getTargetDefines(const LangOptions &Opts, 5465 MacroBuilder &Builder) const override { 5466 // Target identification. 5467 Builder.defineMacro("__arm"); 5468 Builder.defineMacro("__arm__"); 5469 // For bare-metal none-eabi. 5470 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5471 (getTriple().getEnvironment() == llvm::Triple::EABI || 5472 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5473 Builder.defineMacro("__ELF__"); 5474 5475 5476 // Target properties. 5477 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5478 5479 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5480 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5481 if (getTriple().isWatchABI()) 5482 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5483 5484 if (!CPUAttr.empty()) 5485 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5486 5487 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5488 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5489 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5490 5491 if (ArchVersion >= 8) { 5492 // ACLE 6.5.7 Crypto Extension 5493 if (Crypto) 5494 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5495 // ACLE 6.5.8 CRC32 Extension 5496 if (CRC) 5497 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5498 // ACLE 6.5.10 Numeric Maximum and Minimum 5499 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5500 // ACLE 6.5.9 Directed Rounding 5501 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5502 } 5503 5504 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5505 // is not defined for the M-profile. 5506 // NOTE that the default profile is assumed to be 'A' 5507 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5508 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5509 5510 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5511 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5512 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5513 // v7 and v8 architectures excluding v8-M Baseline. 5514 if (supportsThumb2()) 5515 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5516 else if (supportsThumb()) 5517 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5518 5519 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5520 // instruction set such as ARM or Thumb. 5521 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5522 5523 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5524 5525 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5526 if (!CPUProfile.empty()) 5527 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5528 5529 // ACLE 6.4.3 Unaligned access supported in hardware 5530 if (Unaligned) 5531 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5532 5533 // ACLE 6.4.4 LDREX/STREX 5534 if (LDREX) 5535 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5536 5537 // ACLE 6.4.5 CLZ 5538 if (ArchVersion == 5 || 5539 (ArchVersion == 6 && CPUProfile != "M") || 5540 ArchVersion > 6) 5541 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5542 5543 // ACLE 6.5.1 Hardware Floating Point 5544 if (HW_FP) 5545 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5546 5547 // ACLE predefines. 5548 Builder.defineMacro("__ARM_ACLE", "200"); 5549 5550 // FP16 support (we currently only support IEEE format). 5551 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5552 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5553 5554 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5555 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5556 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5557 5558 // Subtarget options. 5559 5560 // FIXME: It's more complicated than this and we don't really support 5561 // interworking. 5562 // Windows on ARM does not "support" interworking 5563 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5564 Builder.defineMacro("__THUMB_INTERWORK__"); 5565 5566 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5567 // Embedded targets on Darwin follow AAPCS, but not EABI. 5568 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5569 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5570 Builder.defineMacro("__ARM_EABI__"); 5571 Builder.defineMacro("__ARM_PCS", "1"); 5572 } 5573 5574 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5575 ABI == "aapcs16") 5576 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5577 5578 if (SoftFloat) 5579 Builder.defineMacro("__SOFTFP__"); 5580 5581 if (ArchKind == llvm::ARM::AK_XSCALE) 5582 Builder.defineMacro("__XSCALE__"); 5583 5584 if (isThumb()) { 5585 Builder.defineMacro("__THUMBEL__"); 5586 Builder.defineMacro("__thumb__"); 5587 if (supportsThumb2()) 5588 Builder.defineMacro("__thumb2__"); 5589 } 5590 5591 // ACLE 6.4.9 32-bit SIMD instructions 5592 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5593 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5594 5595 // ACLE 6.4.10 Hardware Integer Divide 5596 if (((HWDiv & HWDivThumb) && isThumb()) || 5597 ((HWDiv & HWDivARM) && !isThumb())) { 5598 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5599 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5600 } 5601 5602 // Note, this is always on in gcc, even though it doesn't make sense. 5603 Builder.defineMacro("__APCS_32__"); 5604 5605 if (FPUModeIsVFP((FPUMode) FPU)) { 5606 Builder.defineMacro("__VFP_FP__"); 5607 if (FPU & VFP2FPU) 5608 Builder.defineMacro("__ARM_VFPV2__"); 5609 if (FPU & VFP3FPU) 5610 Builder.defineMacro("__ARM_VFPV3__"); 5611 if (FPU & VFP4FPU) 5612 Builder.defineMacro("__ARM_VFPV4__"); 5613 if (FPU & FPARMV8) 5614 Builder.defineMacro("__ARM_FPV5__"); 5615 } 5616 5617 // This only gets set when Neon instructions are actually available, unlike 5618 // the VFP define, hence the soft float and arch check. This is subtly 5619 // different from gcc, we follow the intent which was that it should be set 5620 // when Neon instructions are actually available. 5621 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5622 Builder.defineMacro("__ARM_NEON", "1"); 5623 Builder.defineMacro("__ARM_NEON__"); 5624 // current AArch32 NEON implementations do not support double-precision 5625 // floating-point even when it is present in VFP. 5626 Builder.defineMacro("__ARM_NEON_FP", 5627 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5628 } 5629 5630 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5631 Opts.ShortWChar ? "2" : "4"); 5632 5633 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5634 Opts.ShortEnums ? "1" : "4"); 5635 5636 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5637 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5638 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5639 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5640 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5641 } 5642 5643 // ACLE 6.4.7 DSP instructions 5644 if (DSP) { 5645 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5646 } 5647 5648 // ACLE 6.4.8 Saturation instructions 5649 bool SAT = false; 5650 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5651 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5652 SAT = true; 5653 } 5654 5655 // ACLE 6.4.6 Q (saturation) flag 5656 if (DSP || SAT) 5657 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5658 5659 if (Opts.UnsafeFPMath) 5660 Builder.defineMacro("__ARM_FP_FAST", "1"); 5661 5662 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5663 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5664 } 5665 5666 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5667 return llvm::makeArrayRef(BuiltinInfo, 5668 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5669 } 5670 bool isCLZForZeroUndef() const override { return false; } 5671 BuiltinVaListKind getBuiltinVaListKind() const override { 5672 return IsAAPCS 5673 ? AAPCSABIBuiltinVaList 5674 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5675 : TargetInfo::VoidPtrBuiltinVaList); 5676 } 5677 ArrayRef<const char *> getGCCRegNames() const override; 5678 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5679 bool validateAsmConstraint(const char *&Name, 5680 TargetInfo::ConstraintInfo &Info) const override { 5681 switch (*Name) { 5682 default: break; 5683 case 'l': // r0-r7 5684 case 'h': // r8-r15 5685 case 't': // VFP Floating point register single precision 5686 case 'w': // VFP Floating point register double precision 5687 Info.setAllowsRegister(); 5688 return true; 5689 case 'I': 5690 case 'J': 5691 case 'K': 5692 case 'L': 5693 case 'M': 5694 // FIXME 5695 return true; 5696 case 'Q': // A memory address that is a single base register. 5697 Info.setAllowsMemory(); 5698 return true; 5699 case 'U': // a memory reference... 5700 switch (Name[1]) { 5701 case 'q': // ...ARMV4 ldrsb 5702 case 'v': // ...VFP load/store (reg+constant offset) 5703 case 'y': // ...iWMMXt load/store 5704 case 't': // address valid for load/store opaque types wider 5705 // than 128-bits 5706 case 'n': // valid address for Neon doubleword vector load/store 5707 case 'm': // valid address for Neon element and structure load/store 5708 case 's': // valid address for non-offset loads/stores of quad-word 5709 // values in four ARM registers 5710 Info.setAllowsMemory(); 5711 Name++; 5712 return true; 5713 } 5714 } 5715 return false; 5716 } 5717 std::string convertConstraint(const char *&Constraint) const override { 5718 std::string R; 5719 switch (*Constraint) { 5720 case 'U': // Two-character constraint; add "^" hint for later parsing. 5721 R = std::string("^") + std::string(Constraint, 2); 5722 Constraint++; 5723 break; 5724 case 'p': // 'p' should be translated to 'r' by default. 5725 R = std::string("r"); 5726 break; 5727 default: 5728 return std::string(1, *Constraint); 5729 } 5730 return R; 5731 } 5732 bool 5733 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5734 std::string &SuggestedModifier) const override { 5735 bool isOutput = (Constraint[0] == '='); 5736 bool isInOut = (Constraint[0] == '+'); 5737 5738 // Strip off constraint modifiers. 5739 while (Constraint[0] == '=' || 5740 Constraint[0] == '+' || 5741 Constraint[0] == '&') 5742 Constraint = Constraint.substr(1); 5743 5744 switch (Constraint[0]) { 5745 default: break; 5746 case 'r': { 5747 switch (Modifier) { 5748 default: 5749 return (isInOut || isOutput || Size <= 64); 5750 case 'q': 5751 // A register of size 32 cannot fit a vector type. 5752 return false; 5753 } 5754 } 5755 } 5756 5757 return true; 5758 } 5759 const char *getClobbers() const override { 5760 // FIXME: Is this really right? 5761 return ""; 5762 } 5763 5764 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5765 switch (CC) { 5766 case CC_AAPCS: 5767 case CC_AAPCS_VFP: 5768 case CC_Swift: 5769 return CCCR_OK; 5770 default: 5771 return CCCR_Warning; 5772 } 5773 } 5774 5775 int getEHDataRegisterNumber(unsigned RegNo) const override { 5776 if (RegNo == 0) return 0; 5777 if (RegNo == 1) return 1; 5778 return -1; 5779 } 5780 5781 bool hasSjLjLowering() const override { 5782 return true; 5783 } 5784 }; 5785 5786 bool ARMTargetInfo::setFPMath(StringRef Name) { 5787 if (Name == "neon") { 5788 FPMath = FP_Neon; 5789 return true; 5790 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5791 Name == "vfp4") { 5792 FPMath = FP_VFP; 5793 return true; 5794 } 5795 return false; 5796 } 5797 5798 const char * const ARMTargetInfo::GCCRegNames[] = { 5799 // Integer registers 5800 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5801 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5802 5803 // Float registers 5804 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5805 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5806 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5807 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5808 5809 // Double registers 5810 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5811 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5812 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5813 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5814 5815 // Quad registers 5816 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5817 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5818 }; 5819 5820 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5821 return llvm::makeArrayRef(GCCRegNames); 5822 } 5823 5824 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5825 { { "a1" }, "r0" }, 5826 { { "a2" }, "r1" }, 5827 { { "a3" }, "r2" }, 5828 { { "a4" }, "r3" }, 5829 { { "v1" }, "r4" }, 5830 { { "v2" }, "r5" }, 5831 { { "v3" }, "r6" }, 5832 { { "v4" }, "r7" }, 5833 { { "v5" }, "r8" }, 5834 { { "v6", "rfp" }, "r9" }, 5835 { { "sl" }, "r10" }, 5836 { { "fp" }, "r11" }, 5837 { { "ip" }, "r12" }, 5838 { { "r13" }, "sp" }, 5839 { { "r14" }, "lr" }, 5840 { { "r15" }, "pc" }, 5841 // The S, D and Q registers overlap, but aren't really aliases; we 5842 // don't want to substitute one of these for a different-sized one. 5843 }; 5844 5845 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5846 return llvm::makeArrayRef(GCCRegAliases); 5847 } 5848 5849 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5850 #define BUILTIN(ID, TYPE, ATTRS) \ 5851 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5852 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5853 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5854 #include "clang/Basic/BuiltinsNEON.def" 5855 5856 #define BUILTIN(ID, TYPE, ATTRS) \ 5857 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5858 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5859 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5860 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5861 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5862 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5863 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5864 #include "clang/Basic/BuiltinsARM.def" 5865 }; 5866 5867 class ARMleTargetInfo : public ARMTargetInfo { 5868 public: 5869 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5870 : ARMTargetInfo(Triple, Opts) {} 5871 void getTargetDefines(const LangOptions &Opts, 5872 MacroBuilder &Builder) const override { 5873 Builder.defineMacro("__ARMEL__"); 5874 ARMTargetInfo::getTargetDefines(Opts, Builder); 5875 } 5876 }; 5877 5878 class ARMbeTargetInfo : public ARMTargetInfo { 5879 public: 5880 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5881 : ARMTargetInfo(Triple, Opts) {} 5882 void getTargetDefines(const LangOptions &Opts, 5883 MacroBuilder &Builder) const override { 5884 Builder.defineMacro("__ARMEB__"); 5885 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5886 ARMTargetInfo::getTargetDefines(Opts, Builder); 5887 } 5888 }; 5889 5890 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5891 const llvm::Triple Triple; 5892 public: 5893 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5894 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5895 WCharType = UnsignedShort; 5896 SizeType = UnsignedInt; 5897 } 5898 void getVisualStudioDefines(const LangOptions &Opts, 5899 MacroBuilder &Builder) const { 5900 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5901 5902 // FIXME: this is invalid for WindowsCE 5903 Builder.defineMacro("_M_ARM_NT", "1"); 5904 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5905 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5906 5907 assert((Triple.getArch() == llvm::Triple::arm || 5908 Triple.getArch() == llvm::Triple::thumb) && 5909 "invalid architecture for Windows ARM target info"); 5910 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5911 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5912 5913 // TODO map the complete set of values 5914 // 31: VFPv3 40: VFPv4 5915 Builder.defineMacro("_M_ARM_FP", "31"); 5916 } 5917 BuiltinVaListKind getBuiltinVaListKind() const override { 5918 return TargetInfo::CharPtrBuiltinVaList; 5919 } 5920 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5921 switch (CC) { 5922 case CC_X86StdCall: 5923 case CC_X86ThisCall: 5924 case CC_X86FastCall: 5925 case CC_X86VectorCall: 5926 return CCCR_Ignore; 5927 case CC_C: 5928 return CCCR_OK; 5929 default: 5930 return CCCR_Warning; 5931 } 5932 } 5933 }; 5934 5935 // Windows ARM + Itanium C++ ABI Target 5936 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5937 public: 5938 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5939 const TargetOptions &Opts) 5940 : WindowsARMTargetInfo(Triple, Opts) { 5941 TheCXXABI.set(TargetCXXABI::GenericARM); 5942 } 5943 5944 void getTargetDefines(const LangOptions &Opts, 5945 MacroBuilder &Builder) const override { 5946 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5947 5948 if (Opts.MSVCCompat) 5949 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5950 } 5951 }; 5952 5953 // Windows ARM, MS (C++) ABI 5954 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5955 public: 5956 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5957 const TargetOptions &Opts) 5958 : WindowsARMTargetInfo(Triple, Opts) { 5959 TheCXXABI.set(TargetCXXABI::Microsoft); 5960 } 5961 5962 void getTargetDefines(const LangOptions &Opts, 5963 MacroBuilder &Builder) const override { 5964 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5965 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5966 } 5967 }; 5968 5969 // ARM MinGW target 5970 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5971 public: 5972 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5973 : WindowsARMTargetInfo(Triple, Opts) { 5974 TheCXXABI.set(TargetCXXABI::GenericARM); 5975 } 5976 5977 void getTargetDefines(const LangOptions &Opts, 5978 MacroBuilder &Builder) const override { 5979 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5980 DefineStd(Builder, "WIN32", Opts); 5981 DefineStd(Builder, "WINNT", Opts); 5982 Builder.defineMacro("_ARM_"); 5983 addMinGWDefines(Opts, Builder); 5984 } 5985 }; 5986 5987 // ARM Cygwin target 5988 class CygwinARMTargetInfo : public ARMleTargetInfo { 5989 public: 5990 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5991 : ARMleTargetInfo(Triple, Opts) { 5992 TLSSupported = false; 5993 WCharType = UnsignedShort; 5994 DoubleAlign = LongLongAlign = 64; 5995 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5996 } 5997 void getTargetDefines(const LangOptions &Opts, 5998 MacroBuilder &Builder) const override { 5999 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6000 Builder.defineMacro("_ARM_"); 6001 Builder.defineMacro("__CYGWIN__"); 6002 Builder.defineMacro("__CYGWIN32__"); 6003 DefineStd(Builder, "unix", Opts); 6004 if (Opts.CPlusPlus) 6005 Builder.defineMacro("_GNU_SOURCE"); 6006 } 6007 }; 6008 6009 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6010 protected: 6011 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6012 MacroBuilder &Builder) const override { 6013 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6014 } 6015 6016 public: 6017 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6018 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6019 HasAlignMac68kSupport = true; 6020 // iOS always has 64-bit atomic instructions. 6021 // FIXME: This should be based off of the target features in 6022 // ARMleTargetInfo. 6023 MaxAtomicInlineWidth = 64; 6024 6025 if (Triple.isWatchABI()) { 6026 // Darwin on iOS uses a variant of the ARM C++ ABI. 6027 TheCXXABI.set(TargetCXXABI::WatchOS); 6028 6029 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6030 // size_t is long, it's a bit weird for it to be int. 6031 PtrDiffType = SignedLong; 6032 6033 // BOOL should be a real boolean on the new ABI 6034 UseSignedCharForObjCBool = false; 6035 } else 6036 TheCXXABI.set(TargetCXXABI::iOS); 6037 } 6038 }; 6039 6040 class AArch64TargetInfo : public TargetInfo { 6041 virtual void setDataLayout() = 0; 6042 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6043 static const char *const GCCRegNames[]; 6044 6045 enum FPUModeEnum { 6046 FPUMode, 6047 NeonMode 6048 }; 6049 6050 unsigned FPU; 6051 unsigned CRC; 6052 unsigned Crypto; 6053 unsigned Unaligned; 6054 unsigned V8_1A; 6055 6056 static const Builtin::Info BuiltinInfo[]; 6057 6058 std::string ABI; 6059 6060 public: 6061 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6062 : TargetInfo(Triple), ABI("aapcs") { 6063 if (getTriple().getOS() == llvm::Triple::NetBSD || 6064 getTriple().getOS() == llvm::Triple::OpenBSD) { 6065 WCharType = SignedInt; 6066 6067 // NetBSD apparently prefers consistency across ARM targets to consistency 6068 // across 64-bit targets. 6069 Int64Type = SignedLongLong; 6070 IntMaxType = SignedLongLong; 6071 } else { 6072 WCharType = UnsignedInt; 6073 Int64Type = SignedLong; 6074 IntMaxType = SignedLong; 6075 } 6076 6077 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6078 MaxVectorAlign = 128; 6079 MaxAtomicInlineWidth = 128; 6080 MaxAtomicPromoteWidth = 128; 6081 6082 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6083 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6084 6085 // {} in inline assembly are neon specifiers, not assembly variant 6086 // specifiers. 6087 NoAsmVariants = true; 6088 6089 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6090 // contributes to the alignment of the containing aggregate in the same way 6091 // a plain (non bit-field) member of that type would, without exception for 6092 // zero-sized or anonymous bit-fields." 6093 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6094 UseZeroLengthBitfieldAlignment = true; 6095 6096 // AArch64 targets default to using the ARM C++ ABI. 6097 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6098 6099 if (Triple.getOS() == llvm::Triple::Linux) 6100 this->MCountName = "\01_mcount"; 6101 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6102 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6103 } 6104 6105 StringRef getABI() const override { return ABI; } 6106 bool setABI(const std::string &Name) override { 6107 if (Name != "aapcs" && Name != "darwinpcs") 6108 return false; 6109 6110 ABI = Name; 6111 return true; 6112 } 6113 6114 bool setCPU(const std::string &Name) override { 6115 return Name == "generic" || 6116 llvm::AArch64::parseCPUArch(Name) != 6117 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6118 } 6119 6120 void getTargetDefines(const LangOptions &Opts, 6121 MacroBuilder &Builder) const override { 6122 // Target identification. 6123 Builder.defineMacro("__aarch64__"); 6124 // For bare-metal none-eabi. 6125 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6126 (getTriple().getEnvironment() == llvm::Triple::EABI || 6127 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6128 Builder.defineMacro("__ELF__"); 6129 6130 // Target properties. 6131 Builder.defineMacro("_LP64"); 6132 Builder.defineMacro("__LP64__"); 6133 6134 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6135 Builder.defineMacro("__ARM_ACLE", "200"); 6136 Builder.defineMacro("__ARM_ARCH", "8"); 6137 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6138 6139 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6140 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6141 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6142 6143 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6144 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6145 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6146 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6147 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6148 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6149 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6150 6151 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6152 6153 // 0xe implies support for half, single and double precision operations. 6154 Builder.defineMacro("__ARM_FP", "0xE"); 6155 6156 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6157 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6158 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6159 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6160 6161 if (Opts.UnsafeFPMath) 6162 Builder.defineMacro("__ARM_FP_FAST", "1"); 6163 6164 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6165 6166 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6167 Opts.ShortEnums ? "1" : "4"); 6168 6169 if (FPU == NeonMode) { 6170 Builder.defineMacro("__ARM_NEON", "1"); 6171 // 64-bit NEON supports half, single and double precision operations. 6172 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6173 } 6174 6175 if (CRC) 6176 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6177 6178 if (Crypto) 6179 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6180 6181 if (Unaligned) 6182 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6183 6184 if (V8_1A) 6185 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6186 6187 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6189 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6190 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6191 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6192 } 6193 6194 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6195 return llvm::makeArrayRef(BuiltinInfo, 6196 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6197 } 6198 6199 bool hasFeature(StringRef Feature) const override { 6200 return Feature == "aarch64" || 6201 Feature == "arm64" || 6202 Feature == "arm" || 6203 (Feature == "neon" && FPU == NeonMode); 6204 } 6205 6206 bool handleTargetFeatures(std::vector<std::string> &Features, 6207 DiagnosticsEngine &Diags) override { 6208 FPU = FPUMode; 6209 CRC = 0; 6210 Crypto = 0; 6211 Unaligned = 1; 6212 V8_1A = 0; 6213 6214 for (const auto &Feature : Features) { 6215 if (Feature == "+neon") 6216 FPU = NeonMode; 6217 if (Feature == "+crc") 6218 CRC = 1; 6219 if (Feature == "+crypto") 6220 Crypto = 1; 6221 if (Feature == "+strict-align") 6222 Unaligned = 0; 6223 if (Feature == "+v8.1a") 6224 V8_1A = 1; 6225 } 6226 6227 setDataLayout(); 6228 6229 return true; 6230 } 6231 6232 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6233 switch (CC) { 6234 case CC_C: 6235 case CC_Swift: 6236 case CC_PreserveMost: 6237 case CC_PreserveAll: 6238 return CCCR_OK; 6239 default: 6240 return CCCR_Warning; 6241 } 6242 } 6243 6244 bool isCLZForZeroUndef() const override { return false; } 6245 6246 BuiltinVaListKind getBuiltinVaListKind() const override { 6247 return TargetInfo::AArch64ABIBuiltinVaList; 6248 } 6249 6250 ArrayRef<const char *> getGCCRegNames() const override; 6251 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6252 6253 bool validateAsmConstraint(const char *&Name, 6254 TargetInfo::ConstraintInfo &Info) const override { 6255 switch (*Name) { 6256 default: 6257 return false; 6258 case 'w': // Floating point and SIMD registers (V0-V31) 6259 Info.setAllowsRegister(); 6260 return true; 6261 case 'I': // Constant that can be used with an ADD instruction 6262 case 'J': // Constant that can be used with a SUB instruction 6263 case 'K': // Constant that can be used with a 32-bit logical instruction 6264 case 'L': // Constant that can be used with a 64-bit logical instruction 6265 case 'M': // Constant that can be used as a 32-bit MOV immediate 6266 case 'N': // Constant that can be used as a 64-bit MOV immediate 6267 case 'Y': // Floating point constant zero 6268 case 'Z': // Integer constant zero 6269 return true; 6270 case 'Q': // A memory reference with base register and no offset 6271 Info.setAllowsMemory(); 6272 return true; 6273 case 'S': // A symbolic address 6274 Info.setAllowsRegister(); 6275 return true; 6276 case 'U': 6277 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6278 // Utf: A memory address suitable for ldp/stp in TF mode. 6279 // Usa: An absolute symbolic address. 6280 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6281 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6282 case 'z': // Zero register, wzr or xzr 6283 Info.setAllowsRegister(); 6284 return true; 6285 case 'x': // Floating point and SIMD registers (V0-V15) 6286 Info.setAllowsRegister(); 6287 return true; 6288 } 6289 return false; 6290 } 6291 6292 bool 6293 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6294 std::string &SuggestedModifier) const override { 6295 // Strip off constraint modifiers. 6296 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6297 Constraint = Constraint.substr(1); 6298 6299 switch (Constraint[0]) { 6300 default: 6301 return true; 6302 case 'z': 6303 case 'r': { 6304 switch (Modifier) { 6305 case 'x': 6306 case 'w': 6307 // For now assume that the person knows what they're 6308 // doing with the modifier. 6309 return true; 6310 default: 6311 // By default an 'r' constraint will be in the 'x' 6312 // registers. 6313 if (Size == 64) 6314 return true; 6315 6316 SuggestedModifier = "w"; 6317 return false; 6318 } 6319 } 6320 } 6321 } 6322 6323 const char *getClobbers() const override { return ""; } 6324 6325 int getEHDataRegisterNumber(unsigned RegNo) const override { 6326 if (RegNo == 0) 6327 return 0; 6328 if (RegNo == 1) 6329 return 1; 6330 return -1; 6331 } 6332 }; 6333 6334 const char *const AArch64TargetInfo::GCCRegNames[] = { 6335 // 32-bit Integer registers 6336 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6337 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6338 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6339 6340 // 64-bit Integer registers 6341 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6342 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6343 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6344 6345 // 32-bit floating point regsisters 6346 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6347 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6348 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6349 6350 // 64-bit floating point regsisters 6351 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6352 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6353 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6354 6355 // Vector registers 6356 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6357 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6358 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6359 }; 6360 6361 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6362 return llvm::makeArrayRef(GCCRegNames); 6363 } 6364 6365 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6366 { { "w31" }, "wsp" }, 6367 { { "x29" }, "fp" }, 6368 { { "x30" }, "lr" }, 6369 { { "x31" }, "sp" }, 6370 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6371 // don't want to substitute one of these for a different-sized one. 6372 }; 6373 6374 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6375 return llvm::makeArrayRef(GCCRegAliases); 6376 } 6377 6378 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6379 #define BUILTIN(ID, TYPE, ATTRS) \ 6380 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6381 #include "clang/Basic/BuiltinsNEON.def" 6382 6383 #define BUILTIN(ID, TYPE, ATTRS) \ 6384 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6385 #include "clang/Basic/BuiltinsAArch64.def" 6386 }; 6387 6388 class AArch64leTargetInfo : public AArch64TargetInfo { 6389 void setDataLayout() override { 6390 if (getTriple().isOSBinFormatMachO()) 6391 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6392 else 6393 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6394 } 6395 6396 public: 6397 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6398 : AArch64TargetInfo(Triple, Opts) { 6399 } 6400 void getTargetDefines(const LangOptions &Opts, 6401 MacroBuilder &Builder) const override { 6402 Builder.defineMacro("__AARCH64EL__"); 6403 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6404 } 6405 }; 6406 6407 class AArch64beTargetInfo : public AArch64TargetInfo { 6408 void setDataLayout() override { 6409 assert(!getTriple().isOSBinFormatMachO()); 6410 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6411 } 6412 6413 public: 6414 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6415 : AArch64TargetInfo(Triple, Opts) {} 6416 void getTargetDefines(const LangOptions &Opts, 6417 MacroBuilder &Builder) const override { 6418 Builder.defineMacro("__AARCH64EB__"); 6419 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6420 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6421 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6422 } 6423 }; 6424 6425 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6426 protected: 6427 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6428 MacroBuilder &Builder) const override { 6429 Builder.defineMacro("__AARCH64_SIMD__"); 6430 Builder.defineMacro("__ARM64_ARCH_8__"); 6431 Builder.defineMacro("__ARM_NEON__"); 6432 Builder.defineMacro("__LITTLE_ENDIAN__"); 6433 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6434 Builder.defineMacro("__arm64", "1"); 6435 Builder.defineMacro("__arm64__", "1"); 6436 6437 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6438 } 6439 6440 public: 6441 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6442 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6443 Int64Type = SignedLongLong; 6444 WCharType = SignedInt; 6445 UseSignedCharForObjCBool = false; 6446 6447 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6448 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6449 6450 TheCXXABI.set(TargetCXXABI::iOS64); 6451 } 6452 6453 BuiltinVaListKind getBuiltinVaListKind() const override { 6454 return TargetInfo::CharPtrBuiltinVaList; 6455 } 6456 }; 6457 6458 // Hexagon abstract base class 6459 class HexagonTargetInfo : public TargetInfo { 6460 static const Builtin::Info BuiltinInfo[]; 6461 static const char * const GCCRegNames[]; 6462 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6463 std::string CPU; 6464 bool HasHVX, HasHVXDouble; 6465 bool UseLongCalls; 6466 6467 public: 6468 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6469 : TargetInfo(Triple) { 6470 // Specify the vector alignment explicitly. For v512x1, the calculated 6471 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6472 // the required minimum of 64 bytes. 6473 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6474 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6475 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6476 SizeType = UnsignedInt; 6477 PtrDiffType = SignedInt; 6478 IntPtrType = SignedInt; 6479 6480 // {} in inline assembly are packet specifiers, not assembly variant 6481 // specifiers. 6482 NoAsmVariants = true; 6483 6484 LargeArrayMinWidth = 64; 6485 LargeArrayAlign = 64; 6486 UseBitFieldTypeAlignment = true; 6487 ZeroLengthBitfieldBoundary = 32; 6488 HasHVX = HasHVXDouble = false; 6489 UseLongCalls = false; 6490 } 6491 6492 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6493 return llvm::makeArrayRef(BuiltinInfo, 6494 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6495 } 6496 6497 bool validateAsmConstraint(const char *&Name, 6498 TargetInfo::ConstraintInfo &Info) const override { 6499 switch (*Name) { 6500 case 'v': 6501 case 'q': 6502 if (HasHVX) { 6503 Info.setAllowsRegister(); 6504 return true; 6505 } 6506 break; 6507 case 's': 6508 // Relocatable constant. 6509 return true; 6510 } 6511 return false; 6512 } 6513 6514 void getTargetDefines(const LangOptions &Opts, 6515 MacroBuilder &Builder) const override; 6516 6517 bool isCLZForZeroUndef() const override { return false; } 6518 6519 bool hasFeature(StringRef Feature) const override { 6520 return llvm::StringSwitch<bool>(Feature) 6521 .Case("hexagon", true) 6522 .Case("hvx", HasHVX) 6523 .Case("hvx-double", HasHVXDouble) 6524 .Case("long-calls", UseLongCalls) 6525 .Default(false); 6526 } 6527 6528 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6529 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6530 const override; 6531 6532 bool handleTargetFeatures(std::vector<std::string> &Features, 6533 DiagnosticsEngine &Diags) override; 6534 6535 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6536 bool Enabled) const override; 6537 6538 BuiltinVaListKind getBuiltinVaListKind() const override { 6539 return TargetInfo::CharPtrBuiltinVaList; 6540 } 6541 ArrayRef<const char *> getGCCRegNames() const override; 6542 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6543 const char *getClobbers() const override { 6544 return ""; 6545 } 6546 6547 static const char *getHexagonCPUSuffix(StringRef Name) { 6548 return llvm::StringSwitch<const char*>(Name) 6549 .Case("hexagonv4", "4") 6550 .Case("hexagonv5", "5") 6551 .Case("hexagonv55", "55") 6552 .Case("hexagonv60", "60") 6553 .Case("hexagonv62", "62") 6554 .Default(nullptr); 6555 } 6556 6557 bool setCPU(const std::string &Name) override { 6558 if (!getHexagonCPUSuffix(Name)) 6559 return false; 6560 CPU = Name; 6561 return true; 6562 } 6563 6564 int getEHDataRegisterNumber(unsigned RegNo) const override { 6565 return RegNo < 2 ? RegNo : -1; 6566 } 6567 }; 6568 6569 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6570 MacroBuilder &Builder) const { 6571 Builder.defineMacro("__qdsp6__", "1"); 6572 Builder.defineMacro("__hexagon__", "1"); 6573 6574 if (CPU == "hexagonv4") { 6575 Builder.defineMacro("__HEXAGON_V4__"); 6576 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6577 if (Opts.HexagonQdsp6Compat) { 6578 Builder.defineMacro("__QDSP6_V4__"); 6579 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6580 } 6581 } else if (CPU == "hexagonv5") { 6582 Builder.defineMacro("__HEXAGON_V5__"); 6583 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6584 if(Opts.HexagonQdsp6Compat) { 6585 Builder.defineMacro("__QDSP6_V5__"); 6586 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6587 } 6588 } else if (CPU == "hexagonv55") { 6589 Builder.defineMacro("__HEXAGON_V55__"); 6590 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6591 Builder.defineMacro("__QDSP6_V55__"); 6592 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6593 } else if (CPU == "hexagonv60") { 6594 Builder.defineMacro("__HEXAGON_V60__"); 6595 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6596 Builder.defineMacro("__QDSP6_V60__"); 6597 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6598 } else if (CPU == "hexagonv62") { 6599 Builder.defineMacro("__HEXAGON_V62__"); 6600 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6601 } 6602 6603 if (hasFeature("hvx")) { 6604 Builder.defineMacro("__HVX__"); 6605 if (hasFeature("hvx-double")) 6606 Builder.defineMacro("__HVXDBL__"); 6607 } 6608 } 6609 6610 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6611 DiagnosticsEngine &Diags, StringRef CPU, 6612 const std::vector<std::string> &FeaturesVec) const { 6613 // Default for v60: -hvx, -hvx-double. 6614 Features["hvx"] = false; 6615 Features["hvx-double"] = false; 6616 Features["long-calls"] = false; 6617 6618 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6619 } 6620 6621 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6622 DiagnosticsEngine &Diags) { 6623 for (auto &F : Features) { 6624 if (F == "+hvx") 6625 HasHVX = true; 6626 else if (F == "-hvx") 6627 HasHVX = HasHVXDouble = false; 6628 else if (F == "+hvx-double") 6629 HasHVX = HasHVXDouble = true; 6630 else if (F == "-hvx-double") 6631 HasHVXDouble = false; 6632 6633 if (F == "+long-calls") 6634 UseLongCalls = true; 6635 else if (F == "-long-calls") 6636 UseLongCalls = false; 6637 } 6638 return true; 6639 } 6640 6641 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6642 StringRef Name, bool Enabled) const { 6643 if (Enabled) { 6644 if (Name == "hvx-double") 6645 Features["hvx"] = true; 6646 } else { 6647 if (Name == "hvx") 6648 Features["hvx-double"] = false; 6649 } 6650 Features[Name] = Enabled; 6651 } 6652 6653 const char *const HexagonTargetInfo::GCCRegNames[] = { 6654 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6655 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6656 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6657 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6658 "p0", "p1", "p2", "p3", 6659 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6660 }; 6661 6662 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6663 return llvm::makeArrayRef(GCCRegNames); 6664 } 6665 6666 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6667 { { "sp" }, "r29" }, 6668 { { "fp" }, "r30" }, 6669 { { "lr" }, "r31" }, 6670 }; 6671 6672 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6673 return llvm::makeArrayRef(GCCRegAliases); 6674 } 6675 6676 6677 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6678 #define BUILTIN(ID, TYPE, ATTRS) \ 6679 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6680 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6681 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6682 #include "clang/Basic/BuiltinsHexagon.def" 6683 }; 6684 6685 class LanaiTargetInfo : public TargetInfo { 6686 // Class for Lanai (32-bit). 6687 // The CPU profiles supported by the Lanai backend 6688 enum CPUKind { 6689 CK_NONE, 6690 CK_V11, 6691 } CPU; 6692 6693 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6694 static const char *const GCCRegNames[]; 6695 6696 public: 6697 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6698 : TargetInfo(Triple) { 6699 // Description string has to be kept in sync with backend. 6700 resetDataLayout("E" // Big endian 6701 "-m:e" // ELF name manging 6702 "-p:32:32" // 32 bit pointers, 32 bit aligned 6703 "-i64:64" // 64 bit integers, 64 bit aligned 6704 "-a:0:32" // 32 bit alignment of objects of aggregate type 6705 "-n32" // 32 bit native integer width 6706 "-S64" // 64 bit natural stack alignment 6707 ); 6708 6709 // Setting RegParmMax equal to what mregparm was set to in the old 6710 // toolchain 6711 RegParmMax = 4; 6712 6713 // Set the default CPU to V11 6714 CPU = CK_V11; 6715 6716 // Temporary approach to make everything at least word-aligned and allow for 6717 // safely casting between pointers with different alignment requirements. 6718 // TODO: Remove this when there are no more cast align warnings on the 6719 // firmware. 6720 MinGlobalAlign = 32; 6721 } 6722 6723 void getTargetDefines(const LangOptions &Opts, 6724 MacroBuilder &Builder) const override { 6725 // Define __lanai__ when building for target lanai. 6726 Builder.defineMacro("__lanai__"); 6727 6728 // Set define for the CPU specified. 6729 switch (CPU) { 6730 case CK_V11: 6731 Builder.defineMacro("__LANAI_V11__"); 6732 break; 6733 case CK_NONE: 6734 llvm_unreachable("Unhandled target CPU"); 6735 } 6736 } 6737 6738 bool setCPU(const std::string &Name) override { 6739 CPU = llvm::StringSwitch<CPUKind>(Name) 6740 .Case("v11", CK_V11) 6741 .Default(CK_NONE); 6742 6743 return CPU != CK_NONE; 6744 } 6745 6746 bool hasFeature(StringRef Feature) const override { 6747 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6748 } 6749 6750 ArrayRef<const char *> getGCCRegNames() const override; 6751 6752 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6753 6754 BuiltinVaListKind getBuiltinVaListKind() const override { 6755 return TargetInfo::VoidPtrBuiltinVaList; 6756 } 6757 6758 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6759 6760 bool validateAsmConstraint(const char *&Name, 6761 TargetInfo::ConstraintInfo &info) const override { 6762 return false; 6763 } 6764 6765 const char *getClobbers() const override { return ""; } 6766 }; 6767 6768 const char *const LanaiTargetInfo::GCCRegNames[] = { 6769 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6770 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6771 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6772 6773 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6774 return llvm::makeArrayRef(GCCRegNames); 6775 } 6776 6777 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6778 {{"pc"}, "r2"}, 6779 {{"sp"}, "r4"}, 6780 {{"fp"}, "r5"}, 6781 {{"rv"}, "r8"}, 6782 {{"rr1"}, "r10"}, 6783 {{"rr2"}, "r11"}, 6784 {{"rca"}, "r15"}, 6785 }; 6786 6787 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6788 return llvm::makeArrayRef(GCCRegAliases); 6789 } 6790 6791 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6792 class SparcTargetInfo : public TargetInfo { 6793 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6794 static const char * const GCCRegNames[]; 6795 bool SoftFloat; 6796 public: 6797 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6798 : TargetInfo(Triple), SoftFloat(false) {} 6799 6800 int getEHDataRegisterNumber(unsigned RegNo) const override { 6801 if (RegNo == 0) return 24; 6802 if (RegNo == 1) return 25; 6803 return -1; 6804 } 6805 6806 bool handleTargetFeatures(std::vector<std::string> &Features, 6807 DiagnosticsEngine &Diags) override { 6808 // Check if software floating point is enabled 6809 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6810 if (Feature != Features.end()) { 6811 SoftFloat = true; 6812 } 6813 return true; 6814 } 6815 void getTargetDefines(const LangOptions &Opts, 6816 MacroBuilder &Builder) const override { 6817 DefineStd(Builder, "sparc", Opts); 6818 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6819 6820 if (SoftFloat) 6821 Builder.defineMacro("SOFT_FLOAT", "1"); 6822 } 6823 6824 bool hasFeature(StringRef Feature) const override { 6825 return llvm::StringSwitch<bool>(Feature) 6826 .Case("softfloat", SoftFloat) 6827 .Case("sparc", true) 6828 .Default(false); 6829 } 6830 6831 bool hasSjLjLowering() const override { 6832 return true; 6833 } 6834 6835 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6836 // FIXME: Implement! 6837 return None; 6838 } 6839 BuiltinVaListKind getBuiltinVaListKind() const override { 6840 return TargetInfo::VoidPtrBuiltinVaList; 6841 } 6842 ArrayRef<const char *> getGCCRegNames() const override; 6843 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6844 bool validateAsmConstraint(const char *&Name, 6845 TargetInfo::ConstraintInfo &info) const override { 6846 // FIXME: Implement! 6847 switch (*Name) { 6848 case 'I': // Signed 13-bit constant 6849 case 'J': // Zero 6850 case 'K': // 32-bit constant with the low 12 bits clear 6851 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6852 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6853 case 'N': // Same as 'K' but zext (required for SIMode) 6854 case 'O': // The constant 4096 6855 return true; 6856 } 6857 return false; 6858 } 6859 const char *getClobbers() const override { 6860 // FIXME: Implement! 6861 return ""; 6862 } 6863 6864 // No Sparc V7 for now, the backend doesn't support it anyway. 6865 enum CPUKind { 6866 CK_GENERIC, 6867 CK_V8, 6868 CK_SUPERSPARC, 6869 CK_SPARCLITE, 6870 CK_F934, 6871 CK_HYPERSPARC, 6872 CK_SPARCLITE86X, 6873 CK_SPARCLET, 6874 CK_TSC701, 6875 CK_V9, 6876 CK_ULTRASPARC, 6877 CK_ULTRASPARC3, 6878 CK_NIAGARA, 6879 CK_NIAGARA2, 6880 CK_NIAGARA3, 6881 CK_NIAGARA4, 6882 CK_MYRIAD2100, 6883 CK_MYRIAD2150, 6884 CK_MYRIAD2450, 6885 CK_LEON2, 6886 CK_LEON2_AT697E, 6887 CK_LEON2_AT697F, 6888 CK_LEON3, 6889 CK_LEON3_UT699, 6890 CK_LEON3_GR712RC, 6891 CK_LEON4, 6892 CK_LEON4_GR740 6893 } CPU = CK_GENERIC; 6894 6895 enum CPUGeneration { 6896 CG_V8, 6897 CG_V9, 6898 }; 6899 6900 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6901 switch (Kind) { 6902 case CK_GENERIC: 6903 case CK_V8: 6904 case CK_SUPERSPARC: 6905 case CK_SPARCLITE: 6906 case CK_F934: 6907 case CK_HYPERSPARC: 6908 case CK_SPARCLITE86X: 6909 case CK_SPARCLET: 6910 case CK_TSC701: 6911 case CK_MYRIAD2100: 6912 case CK_MYRIAD2150: 6913 case CK_MYRIAD2450: 6914 case CK_LEON2: 6915 case CK_LEON2_AT697E: 6916 case CK_LEON2_AT697F: 6917 case CK_LEON3: 6918 case CK_LEON3_UT699: 6919 case CK_LEON3_GR712RC: 6920 case CK_LEON4: 6921 case CK_LEON4_GR740: 6922 return CG_V8; 6923 case CK_V9: 6924 case CK_ULTRASPARC: 6925 case CK_ULTRASPARC3: 6926 case CK_NIAGARA: 6927 case CK_NIAGARA2: 6928 case CK_NIAGARA3: 6929 case CK_NIAGARA4: 6930 return CG_V9; 6931 } 6932 llvm_unreachable("Unexpected CPU kind"); 6933 } 6934 6935 CPUKind getCPUKind(StringRef Name) const { 6936 return llvm::StringSwitch<CPUKind>(Name) 6937 .Case("v8", CK_V8) 6938 .Case("supersparc", CK_SUPERSPARC) 6939 .Case("sparclite", CK_SPARCLITE) 6940 .Case("f934", CK_F934) 6941 .Case("hypersparc", CK_HYPERSPARC) 6942 .Case("sparclite86x", CK_SPARCLITE86X) 6943 .Case("sparclet", CK_SPARCLET) 6944 .Case("tsc701", CK_TSC701) 6945 .Case("v9", CK_V9) 6946 .Case("ultrasparc", CK_ULTRASPARC) 6947 .Case("ultrasparc3", CK_ULTRASPARC3) 6948 .Case("niagara", CK_NIAGARA) 6949 .Case("niagara2", CK_NIAGARA2) 6950 .Case("niagara3", CK_NIAGARA3) 6951 .Case("niagara4", CK_NIAGARA4) 6952 .Case("ma2100", CK_MYRIAD2100) 6953 .Case("ma2150", CK_MYRIAD2150) 6954 .Case("ma2450", CK_MYRIAD2450) 6955 // FIXME: the myriad2[.n] spellings are obsolete, 6956 // but a grace period is needed to allow updating dependent builds. 6957 .Case("myriad2", CK_MYRIAD2100) 6958 .Case("myriad2.1", CK_MYRIAD2100) 6959 .Case("myriad2.2", CK_MYRIAD2150) 6960 .Case("leon2", CK_LEON2) 6961 .Case("at697e", CK_LEON2_AT697E) 6962 .Case("at697f", CK_LEON2_AT697F) 6963 .Case("leon3", CK_LEON3) 6964 .Case("ut699", CK_LEON3_UT699) 6965 .Case("gr712rc", CK_LEON3_GR712RC) 6966 .Case("leon4", CK_LEON4) 6967 .Case("gr740", CK_LEON4_GR740) 6968 .Default(CK_GENERIC); 6969 } 6970 6971 bool setCPU(const std::string &Name) override { 6972 CPU = getCPUKind(Name); 6973 return CPU != CK_GENERIC; 6974 } 6975 }; 6976 6977 const char * const SparcTargetInfo::GCCRegNames[] = { 6978 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6979 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6980 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6981 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6982 }; 6983 6984 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6985 return llvm::makeArrayRef(GCCRegNames); 6986 } 6987 6988 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6989 { { "g0" }, "r0" }, 6990 { { "g1" }, "r1" }, 6991 { { "g2" }, "r2" }, 6992 { { "g3" }, "r3" }, 6993 { { "g4" }, "r4" }, 6994 { { "g5" }, "r5" }, 6995 { { "g6" }, "r6" }, 6996 { { "g7" }, "r7" }, 6997 { { "o0" }, "r8" }, 6998 { { "o1" }, "r9" }, 6999 { { "o2" }, "r10" }, 7000 { { "o3" }, "r11" }, 7001 { { "o4" }, "r12" }, 7002 { { "o5" }, "r13" }, 7003 { { "o6", "sp" }, "r14" }, 7004 { { "o7" }, "r15" }, 7005 { { "l0" }, "r16" }, 7006 { { "l1" }, "r17" }, 7007 { { "l2" }, "r18" }, 7008 { { "l3" }, "r19" }, 7009 { { "l4" }, "r20" }, 7010 { { "l5" }, "r21" }, 7011 { { "l6" }, "r22" }, 7012 { { "l7" }, "r23" }, 7013 { { "i0" }, "r24" }, 7014 { { "i1" }, "r25" }, 7015 { { "i2" }, "r26" }, 7016 { { "i3" }, "r27" }, 7017 { { "i4" }, "r28" }, 7018 { { "i5" }, "r29" }, 7019 { { "i6", "fp" }, "r30" }, 7020 { { "i7" }, "r31" }, 7021 }; 7022 7023 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7024 return llvm::makeArrayRef(GCCRegAliases); 7025 } 7026 7027 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7028 class SparcV8TargetInfo : public SparcTargetInfo { 7029 public: 7030 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7031 : SparcTargetInfo(Triple, Opts) { 7032 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7033 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7034 switch (getTriple().getOS()) { 7035 default: 7036 SizeType = UnsignedInt; 7037 IntPtrType = SignedInt; 7038 PtrDiffType = SignedInt; 7039 break; 7040 case llvm::Triple::NetBSD: 7041 case llvm::Triple::OpenBSD: 7042 SizeType = UnsignedLong; 7043 IntPtrType = SignedLong; 7044 PtrDiffType = SignedLong; 7045 break; 7046 } 7047 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7048 // on up to 64 bits. 7049 MaxAtomicPromoteWidth = 64; 7050 MaxAtomicInlineWidth = 32; 7051 } 7052 7053 void getTargetDefines(const LangOptions &Opts, 7054 MacroBuilder &Builder) const override { 7055 SparcTargetInfo::getTargetDefines(Opts, Builder); 7056 switch (getCPUGeneration(CPU)) { 7057 case CG_V8: 7058 Builder.defineMacro("__sparcv8"); 7059 if (getTriple().getOS() != llvm::Triple::Solaris) 7060 Builder.defineMacro("__sparcv8__"); 7061 break; 7062 case CG_V9: 7063 Builder.defineMacro("__sparcv9"); 7064 if (getTriple().getOS() != llvm::Triple::Solaris) { 7065 Builder.defineMacro("__sparcv9__"); 7066 Builder.defineMacro("__sparc_v9__"); 7067 } 7068 break; 7069 } 7070 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7071 std::string MyriadArchValue, Myriad2Value; 7072 Builder.defineMacro("__sparc_v8__"); 7073 Builder.defineMacro("__leon__"); 7074 switch (CPU) { 7075 case CK_MYRIAD2150: 7076 MyriadArchValue = "__ma2150"; 7077 Myriad2Value = "2"; 7078 break; 7079 case CK_MYRIAD2450: 7080 MyriadArchValue = "__ma2450"; 7081 Myriad2Value = "2"; 7082 break; 7083 default: 7084 MyriadArchValue = "__ma2100"; 7085 Myriad2Value = "1"; 7086 break; 7087 } 7088 Builder.defineMacro(MyriadArchValue, "1"); 7089 Builder.defineMacro(MyriadArchValue+"__", "1"); 7090 Builder.defineMacro("__myriad2__", Myriad2Value); 7091 Builder.defineMacro("__myriad2", Myriad2Value); 7092 } 7093 } 7094 7095 bool hasSjLjLowering() const override { 7096 return true; 7097 } 7098 }; 7099 7100 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7101 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7102 public: 7103 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7104 : SparcV8TargetInfo(Triple, Opts) { 7105 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7106 } 7107 }; 7108 7109 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7110 class SparcV9TargetInfo : public SparcTargetInfo { 7111 public: 7112 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7113 : SparcTargetInfo(Triple, Opts) { 7114 // FIXME: Support Sparc quad-precision long double? 7115 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7116 // This is an LP64 platform. 7117 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7118 7119 // OpenBSD uses long long for int64_t and intmax_t. 7120 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7121 IntMaxType = SignedLongLong; 7122 else 7123 IntMaxType = SignedLong; 7124 Int64Type = IntMaxType; 7125 7126 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7127 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7128 LongDoubleWidth = 128; 7129 LongDoubleAlign = 128; 7130 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7131 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7132 } 7133 7134 void getTargetDefines(const LangOptions &Opts, 7135 MacroBuilder &Builder) const override { 7136 SparcTargetInfo::getTargetDefines(Opts, Builder); 7137 Builder.defineMacro("__sparcv9"); 7138 Builder.defineMacro("__arch64__"); 7139 // Solaris doesn't need these variants, but the BSDs do. 7140 if (getTriple().getOS() != llvm::Triple::Solaris) { 7141 Builder.defineMacro("__sparc64__"); 7142 Builder.defineMacro("__sparc_v9__"); 7143 Builder.defineMacro("__sparcv9__"); 7144 } 7145 } 7146 7147 bool setCPU(const std::string &Name) override { 7148 if (!SparcTargetInfo::setCPU(Name)) 7149 return false; 7150 return getCPUGeneration(CPU) == CG_V9; 7151 } 7152 }; 7153 7154 class SystemZTargetInfo : public TargetInfo { 7155 static const Builtin::Info BuiltinInfo[]; 7156 static const char *const GCCRegNames[]; 7157 std::string CPU; 7158 bool HasTransactionalExecution; 7159 bool HasVector; 7160 7161 public: 7162 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7163 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7164 HasVector(false) { 7165 IntMaxType = SignedLong; 7166 Int64Type = SignedLong; 7167 TLSSupported = true; 7168 IntWidth = IntAlign = 32; 7169 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7170 PointerWidth = PointerAlign = 64; 7171 LongDoubleWidth = 128; 7172 LongDoubleAlign = 64; 7173 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7174 DefaultAlignForAttributeAligned = 64; 7175 MinGlobalAlign = 16; 7176 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7177 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7178 } 7179 void getTargetDefines(const LangOptions &Opts, 7180 MacroBuilder &Builder) const override { 7181 Builder.defineMacro("__s390__"); 7182 Builder.defineMacro("__s390x__"); 7183 Builder.defineMacro("__zarch__"); 7184 Builder.defineMacro("__LONG_DOUBLE_128__"); 7185 7186 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7187 .Cases("arch8", "z10", "8") 7188 .Cases("arch9", "z196", "9") 7189 .Cases("arch10", "zEC12", "10") 7190 .Cases("arch11", "z13", "11") 7191 .Default(""); 7192 if (!ISARev.empty()) 7193 Builder.defineMacro("__ARCH__", ISARev); 7194 7195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7198 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7199 7200 if (HasTransactionalExecution) 7201 Builder.defineMacro("__HTM__"); 7202 if (HasVector) 7203 Builder.defineMacro("__VX__"); 7204 if (Opts.ZVector) 7205 Builder.defineMacro("__VEC__", "10301"); 7206 } 7207 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7208 return llvm::makeArrayRef(BuiltinInfo, 7209 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7210 } 7211 7212 ArrayRef<const char *> getGCCRegNames() const override; 7213 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7214 // No aliases. 7215 return None; 7216 } 7217 bool validateAsmConstraint(const char *&Name, 7218 TargetInfo::ConstraintInfo &info) const override; 7219 const char *getClobbers() const override { 7220 // FIXME: Is this really right? 7221 return ""; 7222 } 7223 BuiltinVaListKind getBuiltinVaListKind() const override { 7224 return TargetInfo::SystemZBuiltinVaList; 7225 } 7226 bool setCPU(const std::string &Name) override { 7227 CPU = Name; 7228 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7229 .Case("z10", true) 7230 .Case("arch8", true) 7231 .Case("z196", true) 7232 .Case("arch9", true) 7233 .Case("zEC12", true) 7234 .Case("arch10", true) 7235 .Case("z13", true) 7236 .Case("arch11", true) 7237 .Default(false); 7238 7239 return CPUKnown; 7240 } 7241 bool 7242 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7243 StringRef CPU, 7244 const std::vector<std::string> &FeaturesVec) const override { 7245 if (CPU == "zEC12" || CPU == "arch10") 7246 Features["transactional-execution"] = true; 7247 if (CPU == "z13" || CPU == "arch11") { 7248 Features["transactional-execution"] = true; 7249 Features["vector"] = true; 7250 } 7251 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7252 } 7253 7254 bool handleTargetFeatures(std::vector<std::string> &Features, 7255 DiagnosticsEngine &Diags) override { 7256 HasTransactionalExecution = false; 7257 for (const auto &Feature : Features) { 7258 if (Feature == "+transactional-execution") 7259 HasTransactionalExecution = true; 7260 else if (Feature == "+vector") 7261 HasVector = true; 7262 } 7263 // If we use the vector ABI, vector types are 64-bit aligned. 7264 if (HasVector) { 7265 MaxVectorAlign = 64; 7266 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7267 "-v128:64-a:8:16-n32:64"); 7268 } 7269 return true; 7270 } 7271 7272 bool hasFeature(StringRef Feature) const override { 7273 return llvm::StringSwitch<bool>(Feature) 7274 .Case("systemz", true) 7275 .Case("htm", HasTransactionalExecution) 7276 .Case("vx", HasVector) 7277 .Default(false); 7278 } 7279 7280 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7281 switch (CC) { 7282 case CC_C: 7283 case CC_Swift: 7284 return CCCR_OK; 7285 default: 7286 return CCCR_Warning; 7287 } 7288 } 7289 7290 StringRef getABI() const override { 7291 if (HasVector) 7292 return "vector"; 7293 return ""; 7294 } 7295 7296 bool useFloat128ManglingForLongDouble() const override { 7297 return true; 7298 } 7299 }; 7300 7301 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7302 #define BUILTIN(ID, TYPE, ATTRS) \ 7303 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7304 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7305 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7306 #include "clang/Basic/BuiltinsSystemZ.def" 7307 }; 7308 7309 const char *const SystemZTargetInfo::GCCRegNames[] = { 7310 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7311 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7312 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7313 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7314 }; 7315 7316 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7317 return llvm::makeArrayRef(GCCRegNames); 7318 } 7319 7320 bool SystemZTargetInfo:: 7321 validateAsmConstraint(const char *&Name, 7322 TargetInfo::ConstraintInfo &Info) const { 7323 switch (*Name) { 7324 default: 7325 return false; 7326 7327 case 'a': // Address register 7328 case 'd': // Data register (equivalent to 'r') 7329 case 'f': // Floating-point register 7330 Info.setAllowsRegister(); 7331 return true; 7332 7333 case 'I': // Unsigned 8-bit constant 7334 case 'J': // Unsigned 12-bit constant 7335 case 'K': // Signed 16-bit constant 7336 case 'L': // Signed 20-bit displacement (on all targets we support) 7337 case 'M': // 0x7fffffff 7338 return true; 7339 7340 case 'Q': // Memory with base and unsigned 12-bit displacement 7341 case 'R': // Likewise, plus an index 7342 case 'S': // Memory with base and signed 20-bit displacement 7343 case 'T': // Likewise, plus an index 7344 Info.setAllowsMemory(); 7345 return true; 7346 } 7347 } 7348 7349 class MSP430TargetInfo : public TargetInfo { 7350 static const char *const GCCRegNames[]; 7351 7352 public: 7353 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7354 : TargetInfo(Triple) { 7355 TLSSupported = false; 7356 IntWidth = 16; 7357 IntAlign = 16; 7358 LongWidth = 32; 7359 LongLongWidth = 64; 7360 LongAlign = LongLongAlign = 16; 7361 PointerWidth = 16; 7362 PointerAlign = 16; 7363 SuitableAlign = 16; 7364 SizeType = UnsignedInt; 7365 IntMaxType = SignedLongLong; 7366 IntPtrType = SignedInt; 7367 PtrDiffType = SignedInt; 7368 SigAtomicType = SignedLong; 7369 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7370 } 7371 void getTargetDefines(const LangOptions &Opts, 7372 MacroBuilder &Builder) const override { 7373 Builder.defineMacro("MSP430"); 7374 Builder.defineMacro("__MSP430__"); 7375 // FIXME: defines for different 'flavours' of MCU 7376 } 7377 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7378 // FIXME: Implement. 7379 return None; 7380 } 7381 bool hasFeature(StringRef Feature) const override { 7382 return Feature == "msp430"; 7383 } 7384 ArrayRef<const char *> getGCCRegNames() const override; 7385 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7386 // No aliases. 7387 return None; 7388 } 7389 bool validateAsmConstraint(const char *&Name, 7390 TargetInfo::ConstraintInfo &info) const override { 7391 // FIXME: implement 7392 switch (*Name) { 7393 case 'K': // the constant 1 7394 case 'L': // constant -1^20 .. 1^19 7395 case 'M': // constant 1-4: 7396 return true; 7397 } 7398 // No target constraints for now. 7399 return false; 7400 } 7401 const char *getClobbers() const override { 7402 // FIXME: Is this really right? 7403 return ""; 7404 } 7405 BuiltinVaListKind getBuiltinVaListKind() const override { 7406 // FIXME: implement 7407 return TargetInfo::CharPtrBuiltinVaList; 7408 } 7409 }; 7410 7411 const char *const MSP430TargetInfo::GCCRegNames[] = { 7412 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7413 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7414 7415 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7416 return llvm::makeArrayRef(GCCRegNames); 7417 } 7418 7419 // LLVM and Clang cannot be used directly to output native binaries for 7420 // target, but is used to compile C code to llvm bitcode with correct 7421 // type and alignment information. 7422 // 7423 // TCE uses the llvm bitcode as input and uses it for generating customized 7424 // target processor and program binary. TCE co-design environment is 7425 // publicly available in http://tce.cs.tut.fi 7426 7427 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7428 0, // Default 7429 3, // opencl_global 7430 4, // opencl_local 7431 5, // opencl_constant 7432 // FIXME: generic has to be added to the target 7433 0, // opencl_generic 7434 0, // cuda_device 7435 0, // cuda_constant 7436 0 // cuda_shared 7437 }; 7438 7439 class TCETargetInfo : public TargetInfo { 7440 public: 7441 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7442 : TargetInfo(Triple) { 7443 TLSSupported = false; 7444 IntWidth = 32; 7445 LongWidth = LongLongWidth = 32; 7446 PointerWidth = 32; 7447 IntAlign = 32; 7448 LongAlign = LongLongAlign = 32; 7449 PointerAlign = 32; 7450 SuitableAlign = 32; 7451 SizeType = UnsignedInt; 7452 IntMaxType = SignedLong; 7453 IntPtrType = SignedInt; 7454 PtrDiffType = SignedInt; 7455 FloatWidth = 32; 7456 FloatAlign = 32; 7457 DoubleWidth = 32; 7458 DoubleAlign = 32; 7459 LongDoubleWidth = 32; 7460 LongDoubleAlign = 32; 7461 FloatFormat = &llvm::APFloat::IEEEsingle(); 7462 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7463 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7464 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7465 "i16:16:32-i32:32:32-i64:32:32-" 7466 "f32:32:32-f64:32:32-v64:32:32-" 7467 "v128:32:32-v256:32:32-v512:32:32-" 7468 "v1024:32:32-a0:0:32-n32"); 7469 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7470 UseAddrSpaceMapMangling = true; 7471 } 7472 7473 void getTargetDefines(const LangOptions &Opts, 7474 MacroBuilder &Builder) const override { 7475 DefineStd(Builder, "tce", Opts); 7476 Builder.defineMacro("__TCE__"); 7477 Builder.defineMacro("__TCE_V1__"); 7478 } 7479 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7480 7481 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7482 const char *getClobbers() const override { return ""; } 7483 BuiltinVaListKind getBuiltinVaListKind() const override { 7484 return TargetInfo::VoidPtrBuiltinVaList; 7485 } 7486 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7487 bool validateAsmConstraint(const char *&Name, 7488 TargetInfo::ConstraintInfo &info) const override { 7489 return true; 7490 } 7491 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7492 return None; 7493 } 7494 }; 7495 7496 class TCELETargetInfo : public TCETargetInfo { 7497 public: 7498 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7499 : TCETargetInfo(Triple, Opts) { 7500 BigEndian = false; 7501 7502 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7503 "i16:16:32-i32:32:32-i64:32:32-" 7504 "f32:32:32-f64:32:32-v64:32:32-" 7505 "v128:32:32-v256:32:32-v512:32:32-" 7506 "v1024:32:32-a0:0:32-n32"); 7507 7508 } 7509 7510 virtual void getTargetDefines(const LangOptions &Opts, 7511 MacroBuilder &Builder) const { 7512 DefineStd(Builder, "tcele", Opts); 7513 Builder.defineMacro("__TCE__"); 7514 Builder.defineMacro("__TCE_V1__"); 7515 Builder.defineMacro("__TCELE__"); 7516 Builder.defineMacro("__TCELE_V1__"); 7517 } 7518 7519 }; 7520 7521 class BPFTargetInfo : public TargetInfo { 7522 public: 7523 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7524 : TargetInfo(Triple) { 7525 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7526 SizeType = UnsignedLong; 7527 PtrDiffType = SignedLong; 7528 IntPtrType = SignedLong; 7529 IntMaxType = SignedLong; 7530 Int64Type = SignedLong; 7531 RegParmMax = 5; 7532 if (Triple.getArch() == llvm::Triple::bpfeb) { 7533 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7534 } else { 7535 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7536 } 7537 MaxAtomicPromoteWidth = 64; 7538 MaxAtomicInlineWidth = 64; 7539 TLSSupported = false; 7540 } 7541 void getTargetDefines(const LangOptions &Opts, 7542 MacroBuilder &Builder) const override { 7543 DefineStd(Builder, "bpf", Opts); 7544 Builder.defineMacro("__BPF__"); 7545 } 7546 bool hasFeature(StringRef Feature) const override { 7547 return Feature == "bpf"; 7548 } 7549 7550 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7551 const char *getClobbers() const override { 7552 return ""; 7553 } 7554 BuiltinVaListKind getBuiltinVaListKind() const override { 7555 return TargetInfo::VoidPtrBuiltinVaList; 7556 } 7557 ArrayRef<const char *> getGCCRegNames() const override { 7558 return None; 7559 } 7560 bool validateAsmConstraint(const char *&Name, 7561 TargetInfo::ConstraintInfo &info) const override { 7562 return true; 7563 } 7564 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7565 return None; 7566 } 7567 }; 7568 7569 class MipsTargetInfo : public TargetInfo { 7570 void setDataLayout() { 7571 StringRef Layout; 7572 7573 if (ABI == "o32") 7574 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7575 else if (ABI == "n32") 7576 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7577 else if (ABI == "n64") 7578 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7579 else 7580 llvm_unreachable("Invalid ABI"); 7581 7582 if (BigEndian) 7583 resetDataLayout(("E-" + Layout).str()); 7584 else 7585 resetDataLayout(("e-" + Layout).str()); 7586 } 7587 7588 7589 static const Builtin::Info BuiltinInfo[]; 7590 std::string CPU; 7591 bool IsMips16; 7592 bool IsMicromips; 7593 bool IsNan2008; 7594 bool IsSingleFloat; 7595 bool IsNoABICalls; 7596 bool CanUseBSDABICalls; 7597 enum MipsFloatABI { 7598 HardFloat, SoftFloat 7599 } FloatABI; 7600 enum DspRevEnum { 7601 NoDSP, DSP1, DSP2 7602 } DspRev; 7603 bool HasMSA; 7604 7605 protected: 7606 bool HasFP64; 7607 std::string ABI; 7608 7609 public: 7610 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7611 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7612 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7613 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7614 HasMSA(false), HasFP64(false) { 7615 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7616 7617 setABI((getTriple().getArch() == llvm::Triple::mips || 7618 getTriple().getArch() == llvm::Triple::mipsel) 7619 ? "o32" 7620 : "n64"); 7621 7622 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7623 7624 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7625 Triple.getOS() == llvm::Triple::OpenBSD; 7626 } 7627 7628 bool isNaN2008Default() const { 7629 return CPU == "mips32r6" || CPU == "mips64r6"; 7630 } 7631 7632 bool isFP64Default() const { 7633 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7634 } 7635 7636 bool isNan2008() const override { 7637 return IsNan2008; 7638 } 7639 7640 bool processorSupportsGPR64() const { 7641 return llvm::StringSwitch<bool>(CPU) 7642 .Case("mips3", true) 7643 .Case("mips4", true) 7644 .Case("mips5", true) 7645 .Case("mips64", true) 7646 .Case("mips64r2", true) 7647 .Case("mips64r3", true) 7648 .Case("mips64r5", true) 7649 .Case("mips64r6", true) 7650 .Case("octeon", true) 7651 .Default(false); 7652 return false; 7653 } 7654 7655 StringRef getABI() const override { return ABI; } 7656 bool setABI(const std::string &Name) override { 7657 if (Name == "o32") { 7658 setO32ABITypes(); 7659 ABI = Name; 7660 return true; 7661 } 7662 7663 if (Name == "n32") { 7664 setN32ABITypes(); 7665 ABI = Name; 7666 return true; 7667 } 7668 if (Name == "n64") { 7669 setN64ABITypes(); 7670 ABI = Name; 7671 return true; 7672 } 7673 return false; 7674 } 7675 7676 void setO32ABITypes() { 7677 Int64Type = SignedLongLong; 7678 IntMaxType = Int64Type; 7679 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7680 LongDoubleWidth = LongDoubleAlign = 64; 7681 LongWidth = LongAlign = 32; 7682 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7683 PointerWidth = PointerAlign = 32; 7684 PtrDiffType = SignedInt; 7685 SizeType = UnsignedInt; 7686 SuitableAlign = 64; 7687 } 7688 7689 void setN32N64ABITypes() { 7690 LongDoubleWidth = LongDoubleAlign = 128; 7691 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7692 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7693 LongDoubleWidth = LongDoubleAlign = 64; 7694 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7695 } 7696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7697 SuitableAlign = 128; 7698 } 7699 7700 void setN64ABITypes() { 7701 setN32N64ABITypes(); 7702 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7703 Int64Type = SignedLongLong; 7704 } else { 7705 Int64Type = SignedLong; 7706 } 7707 IntMaxType = Int64Type; 7708 LongWidth = LongAlign = 64; 7709 PointerWidth = PointerAlign = 64; 7710 PtrDiffType = SignedLong; 7711 SizeType = UnsignedLong; 7712 } 7713 7714 void setN32ABITypes() { 7715 setN32N64ABITypes(); 7716 Int64Type = SignedLongLong; 7717 IntMaxType = Int64Type; 7718 LongWidth = LongAlign = 32; 7719 PointerWidth = PointerAlign = 32; 7720 PtrDiffType = SignedInt; 7721 SizeType = UnsignedInt; 7722 } 7723 7724 bool setCPU(const std::string &Name) override { 7725 CPU = Name; 7726 return llvm::StringSwitch<bool>(Name) 7727 .Case("mips1", true) 7728 .Case("mips2", true) 7729 .Case("mips3", true) 7730 .Case("mips4", true) 7731 .Case("mips5", true) 7732 .Case("mips32", true) 7733 .Case("mips32r2", true) 7734 .Case("mips32r3", true) 7735 .Case("mips32r5", true) 7736 .Case("mips32r6", true) 7737 .Case("mips64", true) 7738 .Case("mips64r2", true) 7739 .Case("mips64r3", true) 7740 .Case("mips64r5", true) 7741 .Case("mips64r6", true) 7742 .Case("octeon", true) 7743 .Case("p5600", true) 7744 .Default(false); 7745 } 7746 const std::string& getCPU() const { return CPU; } 7747 bool 7748 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7749 StringRef CPU, 7750 const std::vector<std::string> &FeaturesVec) const override { 7751 if (CPU.empty()) 7752 CPU = getCPU(); 7753 if (CPU == "octeon") 7754 Features["mips64r2"] = Features["cnmips"] = true; 7755 else 7756 Features[CPU] = true; 7757 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7758 } 7759 7760 void getTargetDefines(const LangOptions &Opts, 7761 MacroBuilder &Builder) const override { 7762 if (BigEndian) { 7763 DefineStd(Builder, "MIPSEB", Opts); 7764 Builder.defineMacro("_MIPSEB"); 7765 } else { 7766 DefineStd(Builder, "MIPSEL", Opts); 7767 Builder.defineMacro("_MIPSEL"); 7768 } 7769 7770 Builder.defineMacro("__mips__"); 7771 Builder.defineMacro("_mips"); 7772 if (Opts.GNUMode) 7773 Builder.defineMacro("mips"); 7774 7775 if (ABI == "o32") { 7776 Builder.defineMacro("__mips", "32"); 7777 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7778 } else { 7779 Builder.defineMacro("__mips", "64"); 7780 Builder.defineMacro("__mips64"); 7781 Builder.defineMacro("__mips64__"); 7782 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7783 } 7784 7785 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7786 .Cases("mips32", "mips64", "1") 7787 .Cases("mips32r2", "mips64r2", "2") 7788 .Cases("mips32r3", "mips64r3", "3") 7789 .Cases("mips32r5", "mips64r5", "5") 7790 .Cases("mips32r6", "mips64r6", "6") 7791 .Default(""); 7792 if (!ISARev.empty()) 7793 Builder.defineMacro("__mips_isa_rev", ISARev); 7794 7795 if (ABI == "o32") { 7796 Builder.defineMacro("__mips_o32"); 7797 Builder.defineMacro("_ABIO32", "1"); 7798 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7799 } else if (ABI == "n32") { 7800 Builder.defineMacro("__mips_n32"); 7801 Builder.defineMacro("_ABIN32", "2"); 7802 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7803 } else if (ABI == "n64") { 7804 Builder.defineMacro("__mips_n64"); 7805 Builder.defineMacro("_ABI64", "3"); 7806 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7807 } else 7808 llvm_unreachable("Invalid ABI."); 7809 7810 if (!IsNoABICalls) { 7811 Builder.defineMacro("__mips_abicalls"); 7812 if (CanUseBSDABICalls) 7813 Builder.defineMacro("__ABICALLS__"); 7814 } 7815 7816 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7817 7818 switch (FloatABI) { 7819 case HardFloat: 7820 Builder.defineMacro("__mips_hard_float", Twine(1)); 7821 break; 7822 case SoftFloat: 7823 Builder.defineMacro("__mips_soft_float", Twine(1)); 7824 break; 7825 } 7826 7827 if (IsSingleFloat) 7828 Builder.defineMacro("__mips_single_float", Twine(1)); 7829 7830 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7831 Builder.defineMacro("_MIPS_FPSET", 7832 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7833 7834 if (IsMips16) 7835 Builder.defineMacro("__mips16", Twine(1)); 7836 7837 if (IsMicromips) 7838 Builder.defineMacro("__mips_micromips", Twine(1)); 7839 7840 if (IsNan2008) 7841 Builder.defineMacro("__mips_nan2008", Twine(1)); 7842 7843 switch (DspRev) { 7844 default: 7845 break; 7846 case DSP1: 7847 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7848 Builder.defineMacro("__mips_dsp", Twine(1)); 7849 break; 7850 case DSP2: 7851 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7852 Builder.defineMacro("__mips_dspr2", Twine(1)); 7853 Builder.defineMacro("__mips_dsp", Twine(1)); 7854 break; 7855 } 7856 7857 if (HasMSA) 7858 Builder.defineMacro("__mips_msa", Twine(1)); 7859 7860 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7861 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7862 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7863 7864 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7865 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7866 7867 // These shouldn't be defined for MIPS-I but there's no need to check 7868 // for that since MIPS-I isn't supported. 7869 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7870 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7871 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7872 7873 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7874 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7875 // the instructions exist but using them violates the ABI since they 7876 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7877 if (ABI == "n32" || ABI == "n64") 7878 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7879 } 7880 7881 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7882 return llvm::makeArrayRef(BuiltinInfo, 7883 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7884 } 7885 bool hasFeature(StringRef Feature) const override { 7886 return llvm::StringSwitch<bool>(Feature) 7887 .Case("mips", true) 7888 .Case("fp64", HasFP64) 7889 .Default(false); 7890 } 7891 BuiltinVaListKind getBuiltinVaListKind() const override { 7892 return TargetInfo::VoidPtrBuiltinVaList; 7893 } 7894 ArrayRef<const char *> getGCCRegNames() const override { 7895 static const char *const GCCRegNames[] = { 7896 // CPU register names 7897 // Must match second column of GCCRegAliases 7898 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7899 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7900 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7901 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7902 // Floating point register names 7903 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7904 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7905 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7906 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7907 // Hi/lo and condition register names 7908 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7909 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7910 "$ac3hi","$ac3lo", 7911 // MSA register names 7912 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7913 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7914 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7915 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7916 // MSA control register names 7917 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7918 "$msarequest", "$msamap", "$msaunmap" 7919 }; 7920 return llvm::makeArrayRef(GCCRegNames); 7921 } 7922 bool validateAsmConstraint(const char *&Name, 7923 TargetInfo::ConstraintInfo &Info) const override { 7924 switch (*Name) { 7925 default: 7926 return false; 7927 case 'r': // CPU registers. 7928 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7929 case 'y': // Equivalent to "r", backward compatibility only. 7930 case 'f': // floating-point registers. 7931 case 'c': // $25 for indirect jumps 7932 case 'l': // lo register 7933 case 'x': // hilo register pair 7934 Info.setAllowsRegister(); 7935 return true; 7936 case 'I': // Signed 16-bit constant 7937 case 'J': // Integer 0 7938 case 'K': // Unsigned 16-bit constant 7939 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7940 case 'M': // Constants not loadable via lui, addiu, or ori 7941 case 'N': // Constant -1 to -65535 7942 case 'O': // A signed 15-bit constant 7943 case 'P': // A constant between 1 go 65535 7944 return true; 7945 case 'R': // An address that can be used in a non-macro load or store 7946 Info.setAllowsMemory(); 7947 return true; 7948 case 'Z': 7949 if (Name[1] == 'C') { // An address usable by ll, and sc. 7950 Info.setAllowsMemory(); 7951 Name++; // Skip over 'Z'. 7952 return true; 7953 } 7954 return false; 7955 } 7956 } 7957 7958 std::string convertConstraint(const char *&Constraint) const override { 7959 std::string R; 7960 switch (*Constraint) { 7961 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7962 if (Constraint[1] == 'C') { 7963 R = std::string("^") + std::string(Constraint, 2); 7964 Constraint++; 7965 return R; 7966 } 7967 break; 7968 } 7969 return TargetInfo::convertConstraint(Constraint); 7970 } 7971 7972 const char *getClobbers() const override { 7973 // In GCC, $1 is not widely used in generated code (it's used only in a few 7974 // specific situations), so there is no real need for users to add it to 7975 // the clobbers list if they want to use it in their inline assembly code. 7976 // 7977 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7978 // code generation, so using it in inline assembly without adding it to the 7979 // clobbers list can cause conflicts between the inline assembly code and 7980 // the surrounding generated code. 7981 // 7982 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7983 // operands, which will conflict with the ".set at" assembler option (which 7984 // we use only for inline assembly, in order to maintain compatibility with 7985 // GCC) and will also conflict with the user's usage of $1. 7986 // 7987 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7988 // register for generated code is to automatically clobber $1 for all inline 7989 // assembly code. 7990 // 7991 // FIXME: We should automatically clobber $1 only for inline assembly code 7992 // which actually uses it. This would allow LLVM to use $1 for inline 7993 // assembly operands if the user's assembly code doesn't use it. 7994 return "~{$1}"; 7995 } 7996 7997 bool handleTargetFeatures(std::vector<std::string> &Features, 7998 DiagnosticsEngine &Diags) override { 7999 IsMips16 = false; 8000 IsMicromips = false; 8001 IsNan2008 = isNaN2008Default(); 8002 IsSingleFloat = false; 8003 FloatABI = HardFloat; 8004 DspRev = NoDSP; 8005 HasFP64 = isFP64Default(); 8006 8007 for (const auto &Feature : Features) { 8008 if (Feature == "+single-float") 8009 IsSingleFloat = true; 8010 else if (Feature == "+soft-float") 8011 FloatABI = SoftFloat; 8012 else if (Feature == "+mips16") 8013 IsMips16 = true; 8014 else if (Feature == "+micromips") 8015 IsMicromips = true; 8016 else if (Feature == "+dsp") 8017 DspRev = std::max(DspRev, DSP1); 8018 else if (Feature == "+dspr2") 8019 DspRev = std::max(DspRev, DSP2); 8020 else if (Feature == "+msa") 8021 HasMSA = true; 8022 else if (Feature == "+fp64") 8023 HasFP64 = true; 8024 else if (Feature == "-fp64") 8025 HasFP64 = false; 8026 else if (Feature == "+nan2008") 8027 IsNan2008 = true; 8028 else if (Feature == "-nan2008") 8029 IsNan2008 = false; 8030 else if (Feature == "+noabicalls") 8031 IsNoABICalls = true; 8032 } 8033 8034 setDataLayout(); 8035 8036 return true; 8037 } 8038 8039 int getEHDataRegisterNumber(unsigned RegNo) const override { 8040 if (RegNo == 0) return 4; 8041 if (RegNo == 1) return 5; 8042 return -1; 8043 } 8044 8045 bool isCLZForZeroUndef() const override { return false; } 8046 8047 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8048 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8049 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8050 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8051 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8052 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8053 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8054 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8055 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8056 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8057 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8058 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8059 {{"ra"}, "$31"}}; 8060 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8061 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8062 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8063 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8064 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8065 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8066 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8067 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8068 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8069 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8070 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8071 {{"ra"}, "$31"}}; 8072 if (ABI == "o32") 8073 return llvm::makeArrayRef(O32RegAliases); 8074 return llvm::makeArrayRef(NewABIRegAliases); 8075 } 8076 8077 bool hasInt128Type() const override { 8078 return ABI == "n32" || ABI == "n64"; 8079 } 8080 8081 bool validateTarget(DiagnosticsEngine &Diags) const override { 8082 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8083 // this yet. It's better to fail here than on the backend assertion. 8084 if (processorSupportsGPR64() && ABI == "o32") { 8085 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8086 return false; 8087 } 8088 8089 // 64-bit ABI's require 64-bit CPU's. 8090 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8091 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8092 return false; 8093 } 8094 8095 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8096 // can't handle this yet. It's better to fail here than on the 8097 // backend assertion. 8098 if ((getTriple().getArch() == llvm::Triple::mips64 || 8099 getTriple().getArch() == llvm::Triple::mips64el) && 8100 ABI == "o32") { 8101 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8102 << ABI << getTriple().str(); 8103 return false; 8104 } 8105 8106 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8107 // can't handle this yet. It's better to fail here than on the 8108 // backend assertion. 8109 if ((getTriple().getArch() == llvm::Triple::mips || 8110 getTriple().getArch() == llvm::Triple::mipsel) && 8111 (ABI == "n32" || ABI == "n64")) { 8112 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8113 << ABI << getTriple().str(); 8114 return false; 8115 } 8116 8117 return true; 8118 } 8119 }; 8120 8121 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8122 #define BUILTIN(ID, TYPE, ATTRS) \ 8123 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8124 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8125 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8126 #include "clang/Basic/BuiltinsMips.def" 8127 }; 8128 8129 class PNaClTargetInfo : public TargetInfo { 8130 public: 8131 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8132 : TargetInfo(Triple) { 8133 this->LongAlign = 32; 8134 this->LongWidth = 32; 8135 this->PointerAlign = 32; 8136 this->PointerWidth = 32; 8137 this->IntMaxType = TargetInfo::SignedLongLong; 8138 this->Int64Type = TargetInfo::SignedLongLong; 8139 this->DoubleAlign = 64; 8140 this->LongDoubleWidth = 64; 8141 this->LongDoubleAlign = 64; 8142 this->SizeType = TargetInfo::UnsignedInt; 8143 this->PtrDiffType = TargetInfo::SignedInt; 8144 this->IntPtrType = TargetInfo::SignedInt; 8145 this->RegParmMax = 0; // Disallow regparm 8146 } 8147 8148 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8149 Builder.defineMacro("__le32__"); 8150 Builder.defineMacro("__pnacl__"); 8151 } 8152 void getTargetDefines(const LangOptions &Opts, 8153 MacroBuilder &Builder) const override { 8154 getArchDefines(Opts, Builder); 8155 } 8156 bool hasFeature(StringRef Feature) const override { 8157 return Feature == "pnacl"; 8158 } 8159 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8160 BuiltinVaListKind getBuiltinVaListKind() const override { 8161 return TargetInfo::PNaClABIBuiltinVaList; 8162 } 8163 ArrayRef<const char *> getGCCRegNames() const override; 8164 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8165 bool validateAsmConstraint(const char *&Name, 8166 TargetInfo::ConstraintInfo &Info) const override { 8167 return false; 8168 } 8169 8170 const char *getClobbers() const override { 8171 return ""; 8172 } 8173 }; 8174 8175 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8176 return None; 8177 } 8178 8179 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8180 return None; 8181 } 8182 8183 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8184 class NaClMips32TargetInfo : public MipsTargetInfo { 8185 public: 8186 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8187 : MipsTargetInfo(Triple, Opts) {} 8188 8189 BuiltinVaListKind getBuiltinVaListKind() const override { 8190 return TargetInfo::PNaClABIBuiltinVaList; 8191 } 8192 }; 8193 8194 class Le64TargetInfo : public TargetInfo { 8195 static const Builtin::Info BuiltinInfo[]; 8196 8197 public: 8198 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8199 : TargetInfo(Triple) { 8200 NoAsmVariants = true; 8201 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8202 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8203 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8204 } 8205 8206 void getTargetDefines(const LangOptions &Opts, 8207 MacroBuilder &Builder) const override { 8208 DefineStd(Builder, "unix", Opts); 8209 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8210 Builder.defineMacro("__ELF__"); 8211 } 8212 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8213 return llvm::makeArrayRef(BuiltinInfo, 8214 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8215 } 8216 BuiltinVaListKind getBuiltinVaListKind() const override { 8217 return TargetInfo::PNaClABIBuiltinVaList; 8218 } 8219 const char *getClobbers() const override { return ""; } 8220 ArrayRef<const char *> getGCCRegNames() const override { 8221 return None; 8222 } 8223 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8224 return None; 8225 } 8226 bool validateAsmConstraint(const char *&Name, 8227 TargetInfo::ConstraintInfo &Info) const override { 8228 return false; 8229 } 8230 8231 bool hasProtectedVisibility() const override { return false; } 8232 }; 8233 8234 class WebAssemblyTargetInfo : public TargetInfo { 8235 static const Builtin::Info BuiltinInfo[]; 8236 8237 enum SIMDEnum { 8238 NoSIMD, 8239 SIMD128, 8240 } SIMDLevel; 8241 8242 public: 8243 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8244 : TargetInfo(T), SIMDLevel(NoSIMD) { 8245 NoAsmVariants = true; 8246 SuitableAlign = 128; 8247 LargeArrayMinWidth = 128; 8248 LargeArrayAlign = 128; 8249 SimdDefaultAlign = 128; 8250 SigAtomicType = SignedLong; 8251 LongDoubleWidth = LongDoubleAlign = 128; 8252 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8253 SizeType = UnsignedInt; 8254 PtrDiffType = SignedInt; 8255 IntPtrType = SignedInt; 8256 } 8257 8258 protected: 8259 void getTargetDefines(const LangOptions &Opts, 8260 MacroBuilder &Builder) const override { 8261 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8262 if (SIMDLevel >= SIMD128) 8263 Builder.defineMacro("__wasm_simd128__"); 8264 } 8265 8266 private: 8267 bool 8268 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8269 StringRef CPU, 8270 const std::vector<std::string> &FeaturesVec) const override { 8271 if (CPU == "bleeding-edge") 8272 Features["simd128"] = true; 8273 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8274 } 8275 bool hasFeature(StringRef Feature) const final { 8276 return llvm::StringSwitch<bool>(Feature) 8277 .Case("simd128", SIMDLevel >= SIMD128) 8278 .Default(false); 8279 } 8280 bool handleTargetFeatures(std::vector<std::string> &Features, 8281 DiagnosticsEngine &Diags) final { 8282 for (const auto &Feature : Features) { 8283 if (Feature == "+simd128") { 8284 SIMDLevel = std::max(SIMDLevel, SIMD128); 8285 continue; 8286 } 8287 if (Feature == "-simd128") { 8288 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8289 continue; 8290 } 8291 8292 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8293 << "-target-feature"; 8294 return false; 8295 } 8296 return true; 8297 } 8298 bool setCPU(const std::string &Name) final { 8299 return llvm::StringSwitch<bool>(Name) 8300 .Case("mvp", true) 8301 .Case("bleeding-edge", true) 8302 .Case("generic", true) 8303 .Default(false); 8304 } 8305 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8306 return llvm::makeArrayRef(BuiltinInfo, 8307 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8308 } 8309 BuiltinVaListKind getBuiltinVaListKind() const final { 8310 return VoidPtrBuiltinVaList; 8311 } 8312 ArrayRef<const char *> getGCCRegNames() const final { 8313 return None; 8314 } 8315 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8316 return None; 8317 } 8318 bool 8319 validateAsmConstraint(const char *&Name, 8320 TargetInfo::ConstraintInfo &Info) const final { 8321 return false; 8322 } 8323 const char *getClobbers() const final { return ""; } 8324 bool isCLZForZeroUndef() const final { return false; } 8325 bool hasInt128Type() const final { return true; } 8326 IntType getIntTypeByWidth(unsigned BitWidth, 8327 bool IsSigned) const final { 8328 // WebAssembly prefers long long for explicitly 64-bit integers. 8329 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8330 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8331 } 8332 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8333 bool IsSigned) const final { 8334 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8335 return BitWidth == 64 8336 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8337 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8338 } 8339 }; 8340 8341 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8342 #define BUILTIN(ID, TYPE, ATTRS) \ 8343 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8344 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8345 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8346 #include "clang/Basic/BuiltinsWebAssembly.def" 8347 }; 8348 8349 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8350 public: 8351 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8352 const TargetOptions &Opts) 8353 : WebAssemblyTargetInfo(T, Opts) { 8354 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8355 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8356 } 8357 8358 protected: 8359 void getTargetDefines(const LangOptions &Opts, 8360 MacroBuilder &Builder) const override { 8361 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8362 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8363 } 8364 }; 8365 8366 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8367 public: 8368 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8369 const TargetOptions &Opts) 8370 : WebAssemblyTargetInfo(T, Opts) { 8371 LongAlign = LongWidth = 64; 8372 PointerAlign = PointerWidth = 64; 8373 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8374 SizeType = UnsignedLong; 8375 PtrDiffType = SignedLong; 8376 IntPtrType = SignedLong; 8377 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8378 } 8379 8380 protected: 8381 void getTargetDefines(const LangOptions &Opts, 8382 MacroBuilder &Builder) const override { 8383 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8384 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8385 } 8386 }; 8387 8388 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8389 #define BUILTIN(ID, TYPE, ATTRS) \ 8390 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8391 #include "clang/Basic/BuiltinsLe64.def" 8392 }; 8393 8394 static const unsigned SPIRAddrSpaceMap[] = { 8395 0, // Default 8396 1, // opencl_global 8397 3, // opencl_local 8398 2, // opencl_constant 8399 4, // opencl_generic 8400 0, // cuda_device 8401 0, // cuda_constant 8402 0 // cuda_shared 8403 }; 8404 class SPIRTargetInfo : public TargetInfo { 8405 public: 8406 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8407 : TargetInfo(Triple) { 8408 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8409 "SPIR target must use unknown OS"); 8410 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8411 "SPIR target must use unknown environment type"); 8412 TLSSupported = false; 8413 LongWidth = LongAlign = 64; 8414 AddrSpaceMap = &SPIRAddrSpaceMap; 8415 UseAddrSpaceMapMangling = true; 8416 // Define available target features 8417 // These must be defined in sorted order! 8418 NoAsmVariants = true; 8419 } 8420 void getTargetDefines(const LangOptions &Opts, 8421 MacroBuilder &Builder) const override { 8422 DefineStd(Builder, "SPIR", Opts); 8423 } 8424 bool hasFeature(StringRef Feature) const override { 8425 return Feature == "spir"; 8426 } 8427 8428 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8429 const char *getClobbers() const override { return ""; } 8430 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8431 bool validateAsmConstraint(const char *&Name, 8432 TargetInfo::ConstraintInfo &info) const override { 8433 return true; 8434 } 8435 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8436 return None; 8437 } 8438 BuiltinVaListKind getBuiltinVaListKind() const override { 8439 return TargetInfo::VoidPtrBuiltinVaList; 8440 } 8441 8442 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8443 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8444 : CCCR_Warning; 8445 } 8446 8447 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8448 return CC_SpirFunction; 8449 } 8450 8451 void setSupportedOpenCLOpts() override { 8452 // Assume all OpenCL extensions and optional core features are supported 8453 // for SPIR since it is a generic target. 8454 getSupportedOpenCLOpts().supportAll(); 8455 } 8456 }; 8457 8458 class SPIR32TargetInfo : public SPIRTargetInfo { 8459 public: 8460 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8461 : SPIRTargetInfo(Triple, Opts) { 8462 PointerWidth = PointerAlign = 32; 8463 SizeType = TargetInfo::UnsignedInt; 8464 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8465 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8466 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8467 } 8468 void getTargetDefines(const LangOptions &Opts, 8469 MacroBuilder &Builder) const override { 8470 DefineStd(Builder, "SPIR32", Opts); 8471 } 8472 }; 8473 8474 class SPIR64TargetInfo : public SPIRTargetInfo { 8475 public: 8476 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8477 : SPIRTargetInfo(Triple, Opts) { 8478 PointerWidth = PointerAlign = 64; 8479 SizeType = TargetInfo::UnsignedLong; 8480 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8481 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8482 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8483 } 8484 void getTargetDefines(const LangOptions &Opts, 8485 MacroBuilder &Builder) const override { 8486 DefineStd(Builder, "SPIR64", Opts); 8487 } 8488 }; 8489 8490 class XCoreTargetInfo : public TargetInfo { 8491 static const Builtin::Info BuiltinInfo[]; 8492 public: 8493 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8494 : TargetInfo(Triple) { 8495 NoAsmVariants = true; 8496 LongLongAlign = 32; 8497 SuitableAlign = 32; 8498 DoubleAlign = LongDoubleAlign = 32; 8499 SizeType = UnsignedInt; 8500 PtrDiffType = SignedInt; 8501 IntPtrType = SignedInt; 8502 WCharType = UnsignedChar; 8503 WIntType = UnsignedInt; 8504 UseZeroLengthBitfieldAlignment = true; 8505 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8506 "-f64:32-a:0:32-n32"); 8507 } 8508 void getTargetDefines(const LangOptions &Opts, 8509 MacroBuilder &Builder) const override { 8510 Builder.defineMacro("__XS1B__"); 8511 } 8512 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8513 return llvm::makeArrayRef(BuiltinInfo, 8514 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8515 } 8516 BuiltinVaListKind getBuiltinVaListKind() const override { 8517 return TargetInfo::VoidPtrBuiltinVaList; 8518 } 8519 const char *getClobbers() const override { 8520 return ""; 8521 } 8522 ArrayRef<const char *> getGCCRegNames() const override { 8523 static const char * const GCCRegNames[] = { 8524 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8525 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8526 }; 8527 return llvm::makeArrayRef(GCCRegNames); 8528 } 8529 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8530 return None; 8531 } 8532 bool validateAsmConstraint(const char *&Name, 8533 TargetInfo::ConstraintInfo &Info) const override { 8534 return false; 8535 } 8536 int getEHDataRegisterNumber(unsigned RegNo) const override { 8537 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8538 return (RegNo < 2)? RegNo : -1; 8539 } 8540 bool allowsLargerPreferedTypeAlignment() const override { 8541 return false; 8542 } 8543 }; 8544 8545 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8546 #define BUILTIN(ID, TYPE, ATTRS) \ 8547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8548 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8549 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8550 #include "clang/Basic/BuiltinsXCore.def" 8551 }; 8552 8553 // x86_32 Android target 8554 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8555 public: 8556 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8557 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8558 SuitableAlign = 32; 8559 LongDoubleWidth = 64; 8560 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8561 } 8562 }; 8563 8564 // x86_64 Android target 8565 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8566 public: 8567 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8568 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8569 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8570 } 8571 8572 bool useFloat128ManglingForLongDouble() const override { 8573 return true; 8574 } 8575 }; 8576 8577 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8578 class RenderScript32TargetInfo : public ARMleTargetInfo { 8579 public: 8580 RenderScript32TargetInfo(const llvm::Triple &Triple, 8581 const TargetOptions &Opts) 8582 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8583 Triple.getOSName(), 8584 Triple.getEnvironmentName()), 8585 Opts) { 8586 IsRenderScriptTarget = true; 8587 LongWidth = LongAlign = 64; 8588 } 8589 void getTargetDefines(const LangOptions &Opts, 8590 MacroBuilder &Builder) const override { 8591 Builder.defineMacro("__RENDERSCRIPT__"); 8592 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8593 } 8594 }; 8595 8596 // 64-bit RenderScript is aarch64 8597 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8598 public: 8599 RenderScript64TargetInfo(const llvm::Triple &Triple, 8600 const TargetOptions &Opts) 8601 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8602 Triple.getOSName(), 8603 Triple.getEnvironmentName()), 8604 Opts) { 8605 IsRenderScriptTarget = true; 8606 } 8607 8608 void getTargetDefines(const LangOptions &Opts, 8609 MacroBuilder &Builder) const override { 8610 Builder.defineMacro("__RENDERSCRIPT__"); 8611 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8612 } 8613 }; 8614 8615 /// Information about a specific microcontroller. 8616 struct MCUInfo { 8617 const char *Name; 8618 const char *DefineName; 8619 }; 8620 8621 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8622 static ArrayRef<MCUInfo> AVRMcus = { 8623 { "at90s1200", "__AVR_AT90S1200__" }, 8624 { "attiny11", "__AVR_ATtiny11__" }, 8625 { "attiny12", "__AVR_ATtiny12__" }, 8626 { "attiny15", "__AVR_ATtiny15__" }, 8627 { "attiny28", "__AVR_ATtiny28__" }, 8628 { "at90s2313", "__AVR_AT90S2313__" }, 8629 { "at90s2323", "__AVR_AT90S2323__" }, 8630 { "at90s2333", "__AVR_AT90S2333__" }, 8631 { "at90s2343", "__AVR_AT90S2343__" }, 8632 { "attiny22", "__AVR_ATtiny22__" }, 8633 { "attiny26", "__AVR_ATtiny26__" }, 8634 { "at86rf401", "__AVR_AT86RF401__" }, 8635 { "at90s4414", "__AVR_AT90S4414__" }, 8636 { "at90s4433", "__AVR_AT90S4433__" }, 8637 { "at90s4434", "__AVR_AT90S4434__" }, 8638 { "at90s8515", "__AVR_AT90S8515__" }, 8639 { "at90c8534", "__AVR_AT90c8534__" }, 8640 { "at90s8535", "__AVR_AT90S8535__" }, 8641 { "ata5272", "__AVR_ATA5272__" }, 8642 { "attiny13", "__AVR_ATtiny13__" }, 8643 { "attiny13a", "__AVR_ATtiny13A__" }, 8644 { "attiny2313", "__AVR_ATtiny2313__" }, 8645 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8646 { "attiny24", "__AVR_ATtiny24__" }, 8647 { "attiny24a", "__AVR_ATtiny24A__" }, 8648 { "attiny4313", "__AVR_ATtiny4313__" }, 8649 { "attiny44", "__AVR_ATtiny44__" }, 8650 { "attiny44a", "__AVR_ATtiny44A__" }, 8651 { "attiny84", "__AVR_ATtiny84__" }, 8652 { "attiny84a", "__AVR_ATtiny84A__" }, 8653 { "attiny25", "__AVR_ATtiny25__" }, 8654 { "attiny45", "__AVR_ATtiny45__" }, 8655 { "attiny85", "__AVR_ATtiny85__" }, 8656 { "attiny261", "__AVR_ATtiny261__" }, 8657 { "attiny261a", "__AVR_ATtiny261A__" }, 8658 { "attiny461", "__AVR_ATtiny461__" }, 8659 { "attiny461a", "__AVR_ATtiny461A__" }, 8660 { "attiny861", "__AVR_ATtiny861__" }, 8661 { "attiny861a", "__AVR_ATtiny861A__" }, 8662 { "attiny87", "__AVR_ATtiny87__" }, 8663 { "attiny43u", "__AVR_ATtiny43U__" }, 8664 { "attiny48", "__AVR_ATtiny48__" }, 8665 { "attiny88", "__AVR_ATtiny88__" }, 8666 { "attiny828", "__AVR_ATtiny828__" }, 8667 { "at43usb355", "__AVR_AT43USB355__" }, 8668 { "at76c711", "__AVR_AT76C711__" }, 8669 { "atmega103", "__AVR_ATmega103__" }, 8670 { "at43usb320", "__AVR_AT43USB320__" }, 8671 { "attiny167", "__AVR_ATtiny167__" }, 8672 { "at90usb82", "__AVR_AT90USB82__" }, 8673 { "at90usb162", "__AVR_AT90USB162__" }, 8674 { "ata5505", "__AVR_ATA5505__" }, 8675 { "atmega8u2", "__AVR_ATmega8U2__" }, 8676 { "atmega16u2", "__AVR_ATmega16U2__" }, 8677 { "atmega32u2", "__AVR_ATmega32U2__" }, 8678 { "attiny1634", "__AVR_ATtiny1634__" }, 8679 { "atmega8", "__AVR_ATmega8__" }, 8680 { "ata6289", "__AVR_ATA6289__" }, 8681 { "atmega8a", "__AVR_ATmega8A__" }, 8682 { "ata6285", "__AVR_ATA6285__" }, 8683 { "ata6286", "__AVR_ATA6286__" }, 8684 { "atmega48", "__AVR_ATmega48__" }, 8685 { "atmega48a", "__AVR_ATmega48A__" }, 8686 { "atmega48pa", "__AVR_ATmega48PA__" }, 8687 { "atmega48p", "__AVR_ATmega48P__" }, 8688 { "atmega88", "__AVR_ATmega88__" }, 8689 { "atmega88a", "__AVR_ATmega88A__" }, 8690 { "atmega88p", "__AVR_ATmega88P__" }, 8691 { "atmega88pa", "__AVR_ATmega88PA__" }, 8692 { "atmega8515", "__AVR_ATmega8515__" }, 8693 { "atmega8535", "__AVR_ATmega8535__" }, 8694 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8695 { "at90pwm1", "__AVR_AT90PWM1__" }, 8696 { "at90pwm2", "__AVR_AT90PWM2__" }, 8697 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8698 { "at90pwm3", "__AVR_AT90PWM3__" }, 8699 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8700 { "at90pwm81", "__AVR_AT90PWM81__" }, 8701 { "ata5790", "__AVR_ATA5790__" }, 8702 { "ata5795", "__AVR_ATA5795__" }, 8703 { "atmega16", "__AVR_ATmega16__" }, 8704 { "atmega16a", "__AVR_ATmega16A__" }, 8705 { "atmega161", "__AVR_ATmega161__" }, 8706 { "atmega162", "__AVR_ATmega162__" }, 8707 { "atmega163", "__AVR_ATmega163__" }, 8708 { "atmega164a", "__AVR_ATmega164A__" }, 8709 { "atmega164p", "__AVR_ATmega164P__" }, 8710 { "atmega164pa", "__AVR_ATmega164PA__" }, 8711 { "atmega165", "__AVR_ATmega165__" }, 8712 { "atmega165a", "__AVR_ATmega165A__" }, 8713 { "atmega165p", "__AVR_ATmega165P__" }, 8714 { "atmega165pa", "__AVR_ATmega165PA__" }, 8715 { "atmega168", "__AVR_ATmega168__" }, 8716 { "atmega168a", "__AVR_ATmega168A__" }, 8717 { "atmega168p", "__AVR_ATmega168P__" }, 8718 { "atmega168pa", "__AVR_ATmega168PA__" }, 8719 { "atmega169", "__AVR_ATmega169__" }, 8720 { "atmega169a", "__AVR_ATmega169A__" }, 8721 { "atmega169p", "__AVR_ATmega169P__" }, 8722 { "atmega169pa", "__AVR_ATmega169PA__" }, 8723 { "atmega32", "__AVR_ATmega32__" }, 8724 { "atmega32a", "__AVR_ATmega32A__" }, 8725 { "atmega323", "__AVR_ATmega323__" }, 8726 { "atmega324a", "__AVR_ATmega324A__" }, 8727 { "atmega324p", "__AVR_ATmega324P__" }, 8728 { "atmega324pa", "__AVR_ATmega324PA__" }, 8729 { "atmega325", "__AVR_ATmega325__" }, 8730 { "atmega325a", "__AVR_ATmega325A__" }, 8731 { "atmega325p", "__AVR_ATmega325P__" }, 8732 { "atmega325pa", "__AVR_ATmega325PA__" }, 8733 { "atmega3250", "__AVR_ATmega3250__" }, 8734 { "atmega3250a", "__AVR_ATmega3250A__" }, 8735 { "atmega3250p", "__AVR_ATmega3250P__" }, 8736 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8737 { "atmega328", "__AVR_ATmega328__" }, 8738 { "atmega328p", "__AVR_ATmega328P__" }, 8739 { "atmega329", "__AVR_ATmega329__" }, 8740 { "atmega329a", "__AVR_ATmega329A__" }, 8741 { "atmega329p", "__AVR_ATmega329P__" }, 8742 { "atmega329pa", "__AVR_ATmega329PA__" }, 8743 { "atmega3290", "__AVR_ATmega3290__" }, 8744 { "atmega3290a", "__AVR_ATmega3290A__" }, 8745 { "atmega3290p", "__AVR_ATmega3290P__" }, 8746 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8747 { "atmega406", "__AVR_ATmega406__" }, 8748 { "atmega64", "__AVR_ATmega64__" }, 8749 { "atmega64a", "__AVR_ATmega64A__" }, 8750 { "atmega640", "__AVR_ATmega640__" }, 8751 { "atmega644", "__AVR_ATmega644__" }, 8752 { "atmega644a", "__AVR_ATmega644A__" }, 8753 { "atmega644p", "__AVR_ATmega644P__" }, 8754 { "atmega644pa", "__AVR_ATmega644PA__" }, 8755 { "atmega645", "__AVR_ATmega645__" }, 8756 { "atmega645a", "__AVR_ATmega645A__" }, 8757 { "atmega645p", "__AVR_ATmega645P__" }, 8758 { "atmega649", "__AVR_ATmega649__" }, 8759 { "atmega649a", "__AVR_ATmega649A__" }, 8760 { "atmega649p", "__AVR_ATmega649P__" }, 8761 { "atmega6450", "__AVR_ATmega6450__" }, 8762 { "atmega6450a", "__AVR_ATmega6450A__" }, 8763 { "atmega6450p", "__AVR_ATmega6450P__" }, 8764 { "atmega6490", "__AVR_ATmega6490__" }, 8765 { "atmega6490a", "__AVR_ATmega6490A__" }, 8766 { "atmega6490p", "__AVR_ATmega6490P__" }, 8767 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8768 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8769 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8770 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8771 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8772 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8773 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8774 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8775 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8776 { "at90can32", "__AVR_AT90CAN32__" }, 8777 { "at90can64", "__AVR_AT90CAN64__" }, 8778 { "at90pwm161", "__AVR_AT90PWM161__" }, 8779 { "at90pwm216", "__AVR_AT90PWM216__" }, 8780 { "at90pwm316", "__AVR_AT90PWM316__" }, 8781 { "atmega32c1", "__AVR_ATmega32C1__" }, 8782 { "atmega64c1", "__AVR_ATmega64C1__" }, 8783 { "atmega16m1", "__AVR_ATmega16M1__" }, 8784 { "atmega32m1", "__AVR_ATmega32M1__" }, 8785 { "atmega64m1", "__AVR_ATmega64M1__" }, 8786 { "atmega16u4", "__AVR_ATmega16U4__" }, 8787 { "atmega32u4", "__AVR_ATmega32U4__" }, 8788 { "atmega32u6", "__AVR_ATmega32U6__" }, 8789 { "at90usb646", "__AVR_AT90USB646__" }, 8790 { "at90usb647", "__AVR_AT90USB647__" }, 8791 { "at90scr100", "__AVR_AT90SCR100__" }, 8792 { "at94k", "__AVR_AT94K__" }, 8793 { "m3000", "__AVR_AT000__" }, 8794 { "atmega128", "__AVR_ATmega128__" }, 8795 { "atmega128a", "__AVR_ATmega128A__" }, 8796 { "atmega1280", "__AVR_ATmega1280__" }, 8797 { "atmega1281", "__AVR_ATmega1281__" }, 8798 { "atmega1284", "__AVR_ATmega1284__" }, 8799 { "atmega1284p", "__AVR_ATmega1284P__" }, 8800 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8801 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8802 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8803 { "at90can128", "__AVR_AT90CAN128__" }, 8804 { "at90usb1286", "__AVR_AT90USB1286__" }, 8805 { "at90usb1287", "__AVR_AT90USB1287__" }, 8806 { "atmega2560", "__AVR_ATmega2560__" }, 8807 { "atmega2561", "__AVR_ATmega2561__" }, 8808 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8809 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8810 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8811 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8812 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8813 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8814 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8815 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8816 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8817 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8818 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8819 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8820 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8821 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8822 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8823 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8824 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8825 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8826 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8827 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8828 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8829 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8830 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8831 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8832 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8833 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8834 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8835 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8836 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8837 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8838 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8839 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8840 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8841 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8842 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8843 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8844 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8845 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8846 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8847 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8848 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8849 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8850 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8851 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8852 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8853 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8854 { "attiny4", "__AVR_ATtiny4__" }, 8855 { "attiny5", "__AVR_ATtiny5__" }, 8856 { "attiny9", "__AVR_ATtiny9__" }, 8857 { "attiny10", "__AVR_ATtiny10__" }, 8858 { "attiny20", "__AVR_ATtiny20__" }, 8859 { "attiny40", "__AVR_ATtiny40__" }, 8860 { "attiny102", "__AVR_ATtiny102__" }, 8861 { "attiny104", "__AVR_ATtiny104__" }, 8862 }; 8863 8864 // AVR Target 8865 class AVRTargetInfo : public TargetInfo { 8866 public: 8867 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8868 : TargetInfo(Triple) { 8869 TLSSupported = false; 8870 PointerWidth = 16; 8871 PointerAlign = 8; 8872 IntWidth = 16; 8873 IntAlign = 8; 8874 LongWidth = 32; 8875 LongAlign = 8; 8876 LongLongWidth = 64; 8877 LongLongAlign = 8; 8878 SuitableAlign = 8; 8879 DefaultAlignForAttributeAligned = 8; 8880 HalfWidth = 16; 8881 HalfAlign = 8; 8882 FloatWidth = 32; 8883 FloatAlign = 8; 8884 DoubleWidth = 32; 8885 DoubleAlign = 8; 8886 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8887 LongDoubleWidth = 32; 8888 LongDoubleAlign = 8; 8889 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8890 SizeType = UnsignedInt; 8891 PtrDiffType = SignedInt; 8892 IntPtrType = SignedInt; 8893 Char16Type = UnsignedInt; 8894 WCharType = SignedInt; 8895 WIntType = SignedInt; 8896 Char32Type = UnsignedLong; 8897 SigAtomicType = SignedChar; 8898 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8899 "-f32:32:32-f64:64:64-n8"); 8900 } 8901 8902 void getTargetDefines(const LangOptions &Opts, 8903 MacroBuilder &Builder) const override { 8904 Builder.defineMacro("AVR"); 8905 Builder.defineMacro("__AVR"); 8906 Builder.defineMacro("__AVR__"); 8907 8908 if (!this->CPU.empty()) { 8909 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8910 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8911 8912 if (It != AVRMcus.end()) 8913 Builder.defineMacro(It->DefineName); 8914 } 8915 } 8916 8917 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8918 return None; 8919 } 8920 8921 BuiltinVaListKind getBuiltinVaListKind() const override { 8922 return TargetInfo::VoidPtrBuiltinVaList; 8923 } 8924 8925 const char *getClobbers() const override { 8926 return ""; 8927 } 8928 8929 ArrayRef<const char *> getGCCRegNames() const override { 8930 static const char * const GCCRegNames[] = { 8931 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8932 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8933 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8934 "r24", "r25", "X", "Y", "Z", "SP" 8935 }; 8936 return llvm::makeArrayRef(GCCRegNames); 8937 } 8938 8939 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8940 return None; 8941 } 8942 8943 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8944 static const TargetInfo::AddlRegName AddlRegNames[] = { 8945 { { "r26", "r27"}, 26 }, 8946 { { "r28", "r29"}, 27 }, 8947 { { "r30", "r31"}, 28 }, 8948 { { "SPL", "SPH"}, 29 }, 8949 }; 8950 return llvm::makeArrayRef(AddlRegNames); 8951 } 8952 8953 bool validateAsmConstraint(const char *&Name, 8954 TargetInfo::ConstraintInfo &Info) const override { 8955 // There aren't any multi-character AVR specific constraints. 8956 if (StringRef(Name).size() > 1) return false; 8957 8958 switch (*Name) { 8959 default: return false; 8960 case 'a': // Simple upper registers 8961 case 'b': // Base pointer registers pairs 8962 case 'd': // Upper register 8963 case 'l': // Lower registers 8964 case 'e': // Pointer register pairs 8965 case 'q': // Stack pointer register 8966 case 'r': // Any register 8967 case 'w': // Special upper register pairs 8968 case 't': // Temporary register 8969 case 'x': case 'X': // Pointer register pair X 8970 case 'y': case 'Y': // Pointer register pair Y 8971 case 'z': case 'Z': // Pointer register pair Z 8972 Info.setAllowsRegister(); 8973 return true; 8974 case 'I': // 6-bit positive integer constant 8975 Info.setRequiresImmediate(0, 63); 8976 return true; 8977 case 'J': // 6-bit negative integer constant 8978 Info.setRequiresImmediate(-63, 0); 8979 return true; 8980 case 'K': // Integer constant (Range: 2) 8981 Info.setRequiresImmediate(2); 8982 return true; 8983 case 'L': // Integer constant (Range: 0) 8984 Info.setRequiresImmediate(0); 8985 return true; 8986 case 'M': // 8-bit integer constant 8987 Info.setRequiresImmediate(0, 0xff); 8988 return true; 8989 case 'N': // Integer constant (Range: -1) 8990 Info.setRequiresImmediate(-1); 8991 return true; 8992 case 'O': // Integer constant (Range: 8, 16, 24) 8993 Info.setRequiresImmediate({8, 16, 24}); 8994 return true; 8995 case 'P': // Integer constant (Range: 1) 8996 Info.setRequiresImmediate(1); 8997 return true; 8998 case 'R': // Integer constant (Range: -6 to 5) 8999 Info.setRequiresImmediate(-6, 5); 9000 return true; 9001 case 'G': // Floating point constant 9002 case 'Q': // A memory address based on Y or Z pointer with displacement. 9003 return true; 9004 } 9005 9006 return false; 9007 } 9008 9009 IntType getIntTypeByWidth(unsigned BitWidth, 9010 bool IsSigned) const final { 9011 // AVR prefers int for 16-bit integers. 9012 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9013 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9014 } 9015 9016 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9017 bool IsSigned) const final { 9018 // AVR uses int for int_least16_t and int_fast16_t. 9019 return BitWidth == 16 9020 ? (IsSigned ? SignedInt : UnsignedInt) 9021 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9022 } 9023 9024 bool setCPU(const std::string &Name) override { 9025 bool IsFamily = llvm::StringSwitch<bool>(Name) 9026 .Case("avr1", true) 9027 .Case("avr2", true) 9028 .Case("avr25", true) 9029 .Case("avr3", true) 9030 .Case("avr31", true) 9031 .Case("avr35", true) 9032 .Case("avr4", true) 9033 .Case("avr5", true) 9034 .Case("avr51", true) 9035 .Case("avr6", true) 9036 .Case("avrxmega1", true) 9037 .Case("avrxmega2", true) 9038 .Case("avrxmega3", true) 9039 .Case("avrxmega4", true) 9040 .Case("avrxmega5", true) 9041 .Case("avrxmega6", true) 9042 .Case("avrxmega7", true) 9043 .Case("avrtiny", true) 9044 .Default(false); 9045 9046 if (IsFamily) this->CPU = Name; 9047 9048 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9049 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9050 9051 if (IsMCU) this->CPU = Name; 9052 9053 return IsFamily || IsMCU; 9054 } 9055 9056 protected: 9057 std::string CPU; 9058 }; 9059 9060 } // end anonymous namespace 9061 9062 //===----------------------------------------------------------------------===// 9063 // Driver code 9064 //===----------------------------------------------------------------------===// 9065 9066 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9067 const TargetOptions &Opts) { 9068 llvm::Triple::OSType os = Triple.getOS(); 9069 9070 switch (Triple.getArch()) { 9071 default: 9072 return nullptr; 9073 9074 case llvm::Triple::xcore: 9075 return new XCoreTargetInfo(Triple, Opts); 9076 9077 case llvm::Triple::hexagon: 9078 return new HexagonTargetInfo(Triple, Opts); 9079 9080 case llvm::Triple::lanai: 9081 return new LanaiTargetInfo(Triple, Opts); 9082 9083 case llvm::Triple::aarch64: 9084 if (Triple.isOSDarwin()) 9085 return new DarwinAArch64TargetInfo(Triple, Opts); 9086 9087 switch (os) { 9088 case llvm::Triple::CloudABI: 9089 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9090 case llvm::Triple::FreeBSD: 9091 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9092 case llvm::Triple::Fuchsia: 9093 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9094 case llvm::Triple::Linux: 9095 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9096 case llvm::Triple::NetBSD: 9097 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9098 case llvm::Triple::OpenBSD: 9099 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9100 default: 9101 return new AArch64leTargetInfo(Triple, Opts); 9102 } 9103 9104 case llvm::Triple::aarch64_be: 9105 switch (os) { 9106 case llvm::Triple::FreeBSD: 9107 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9108 case llvm::Triple::Fuchsia: 9109 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9110 case llvm::Triple::Linux: 9111 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9112 case llvm::Triple::NetBSD: 9113 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9114 default: 9115 return new AArch64beTargetInfo(Triple, Opts); 9116 } 9117 9118 case llvm::Triple::arm: 9119 case llvm::Triple::thumb: 9120 if (Triple.isOSBinFormatMachO()) 9121 return new DarwinARMTargetInfo(Triple, Opts); 9122 9123 switch (os) { 9124 case llvm::Triple::CloudABI: 9125 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9126 case llvm::Triple::Linux: 9127 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9128 case llvm::Triple::FreeBSD: 9129 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9130 case llvm::Triple::NetBSD: 9131 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9132 case llvm::Triple::OpenBSD: 9133 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9134 case llvm::Triple::Bitrig: 9135 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9136 case llvm::Triple::RTEMS: 9137 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9138 case llvm::Triple::NaCl: 9139 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9140 case llvm::Triple::Win32: 9141 switch (Triple.getEnvironment()) { 9142 case llvm::Triple::Cygnus: 9143 return new CygwinARMTargetInfo(Triple, Opts); 9144 case llvm::Triple::GNU: 9145 return new MinGWARMTargetInfo(Triple, Opts); 9146 case llvm::Triple::Itanium: 9147 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9148 case llvm::Triple::MSVC: 9149 default: // Assume MSVC for unknown environments 9150 return new MicrosoftARMleTargetInfo(Triple, Opts); 9151 } 9152 default: 9153 return new ARMleTargetInfo(Triple, Opts); 9154 } 9155 9156 case llvm::Triple::armeb: 9157 case llvm::Triple::thumbeb: 9158 if (Triple.isOSDarwin()) 9159 return new DarwinARMTargetInfo(Triple, Opts); 9160 9161 switch (os) { 9162 case llvm::Triple::Linux: 9163 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9164 case llvm::Triple::FreeBSD: 9165 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9166 case llvm::Triple::NetBSD: 9167 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9168 case llvm::Triple::OpenBSD: 9169 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9170 case llvm::Triple::Bitrig: 9171 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9172 case llvm::Triple::RTEMS: 9173 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9174 case llvm::Triple::NaCl: 9175 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9176 default: 9177 return new ARMbeTargetInfo(Triple, Opts); 9178 } 9179 9180 case llvm::Triple::avr: 9181 return new AVRTargetInfo(Triple, Opts); 9182 case llvm::Triple::bpfeb: 9183 case llvm::Triple::bpfel: 9184 return new BPFTargetInfo(Triple, Opts); 9185 9186 case llvm::Triple::msp430: 9187 return new MSP430TargetInfo(Triple, Opts); 9188 9189 case llvm::Triple::mips: 9190 switch (os) { 9191 case llvm::Triple::Linux: 9192 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9193 case llvm::Triple::RTEMS: 9194 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9195 case llvm::Triple::FreeBSD: 9196 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9197 case llvm::Triple::NetBSD: 9198 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9199 default: 9200 return new MipsTargetInfo(Triple, Opts); 9201 } 9202 9203 case llvm::Triple::mipsel: 9204 switch (os) { 9205 case llvm::Triple::Linux: 9206 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9207 case llvm::Triple::RTEMS: 9208 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9209 case llvm::Triple::FreeBSD: 9210 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9211 case llvm::Triple::NetBSD: 9212 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9213 case llvm::Triple::NaCl: 9214 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9215 default: 9216 return new MipsTargetInfo(Triple, Opts); 9217 } 9218 9219 case llvm::Triple::mips64: 9220 switch (os) { 9221 case llvm::Triple::Linux: 9222 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9223 case llvm::Triple::RTEMS: 9224 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9225 case llvm::Triple::FreeBSD: 9226 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9227 case llvm::Triple::NetBSD: 9228 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9229 case llvm::Triple::OpenBSD: 9230 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9231 default: 9232 return new MipsTargetInfo(Triple, Opts); 9233 } 9234 9235 case llvm::Triple::mips64el: 9236 switch (os) { 9237 case llvm::Triple::Linux: 9238 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9239 case llvm::Triple::RTEMS: 9240 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9241 case llvm::Triple::FreeBSD: 9242 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9243 case llvm::Triple::NetBSD: 9244 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9245 case llvm::Triple::OpenBSD: 9246 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9247 default: 9248 return new MipsTargetInfo(Triple, Opts); 9249 } 9250 9251 case llvm::Triple::le32: 9252 switch (os) { 9253 case llvm::Triple::NaCl: 9254 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9255 default: 9256 return nullptr; 9257 } 9258 9259 case llvm::Triple::le64: 9260 return new Le64TargetInfo(Triple, Opts); 9261 9262 case llvm::Triple::ppc: 9263 if (Triple.isOSDarwin()) 9264 return new DarwinPPC32TargetInfo(Triple, Opts); 9265 switch (os) { 9266 case llvm::Triple::Linux: 9267 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9268 case llvm::Triple::FreeBSD: 9269 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9270 case llvm::Triple::NetBSD: 9271 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9272 case llvm::Triple::OpenBSD: 9273 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9274 case llvm::Triple::RTEMS: 9275 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9276 default: 9277 return new PPC32TargetInfo(Triple, Opts); 9278 } 9279 9280 case llvm::Triple::ppc64: 9281 if (Triple.isOSDarwin()) 9282 return new DarwinPPC64TargetInfo(Triple, Opts); 9283 switch (os) { 9284 case llvm::Triple::Linux: 9285 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9286 case llvm::Triple::Lv2: 9287 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9288 case llvm::Triple::FreeBSD: 9289 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9290 case llvm::Triple::NetBSD: 9291 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9292 default: 9293 return new PPC64TargetInfo(Triple, Opts); 9294 } 9295 9296 case llvm::Triple::ppc64le: 9297 switch (os) { 9298 case llvm::Triple::Linux: 9299 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9300 case llvm::Triple::NetBSD: 9301 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9302 default: 9303 return new PPC64TargetInfo(Triple, Opts); 9304 } 9305 9306 case llvm::Triple::nvptx: 9307 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9308 case llvm::Triple::nvptx64: 9309 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9310 9311 case llvm::Triple::amdgcn: 9312 case llvm::Triple::r600: 9313 return new AMDGPUTargetInfo(Triple, Opts); 9314 9315 case llvm::Triple::sparc: 9316 switch (os) { 9317 case llvm::Triple::Linux: 9318 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9319 case llvm::Triple::Solaris: 9320 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9321 case llvm::Triple::NetBSD: 9322 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9323 case llvm::Triple::OpenBSD: 9324 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9325 case llvm::Triple::RTEMS: 9326 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9327 default: 9328 return new SparcV8TargetInfo(Triple, Opts); 9329 } 9330 9331 // The 'sparcel' architecture copies all the above cases except for Solaris. 9332 case llvm::Triple::sparcel: 9333 switch (os) { 9334 case llvm::Triple::Linux: 9335 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9336 case llvm::Triple::NetBSD: 9337 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9338 case llvm::Triple::OpenBSD: 9339 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9340 case llvm::Triple::RTEMS: 9341 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9342 default: 9343 return new SparcV8elTargetInfo(Triple, Opts); 9344 } 9345 9346 case llvm::Triple::sparcv9: 9347 switch (os) { 9348 case llvm::Triple::Linux: 9349 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9350 case llvm::Triple::Solaris: 9351 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9352 case llvm::Triple::NetBSD: 9353 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9354 case llvm::Triple::OpenBSD: 9355 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9356 case llvm::Triple::FreeBSD: 9357 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9358 default: 9359 return new SparcV9TargetInfo(Triple, Opts); 9360 } 9361 9362 case llvm::Triple::systemz: 9363 switch (os) { 9364 case llvm::Triple::Linux: 9365 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9366 default: 9367 return new SystemZTargetInfo(Triple, Opts); 9368 } 9369 9370 case llvm::Triple::tce: 9371 return new TCETargetInfo(Triple, Opts); 9372 9373 case llvm::Triple::tcele: 9374 return new TCELETargetInfo(Triple, Opts); 9375 9376 case llvm::Triple::x86: 9377 if (Triple.isOSDarwin()) 9378 return new DarwinI386TargetInfo(Triple, Opts); 9379 9380 switch (os) { 9381 case llvm::Triple::CloudABI: 9382 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9383 case llvm::Triple::Linux: { 9384 switch (Triple.getEnvironment()) { 9385 default: 9386 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9387 case llvm::Triple::Android: 9388 return new AndroidX86_32TargetInfo(Triple, Opts); 9389 } 9390 } 9391 case llvm::Triple::DragonFly: 9392 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9393 case llvm::Triple::NetBSD: 9394 return new NetBSDI386TargetInfo(Triple, Opts); 9395 case llvm::Triple::OpenBSD: 9396 return new OpenBSDI386TargetInfo(Triple, Opts); 9397 case llvm::Triple::Bitrig: 9398 return new BitrigI386TargetInfo(Triple, Opts); 9399 case llvm::Triple::FreeBSD: 9400 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9401 case llvm::Triple::KFreeBSD: 9402 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9403 case llvm::Triple::Minix: 9404 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9405 case llvm::Triple::Solaris: 9406 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9407 case llvm::Triple::Win32: { 9408 switch (Triple.getEnvironment()) { 9409 case llvm::Triple::Cygnus: 9410 return new CygwinX86_32TargetInfo(Triple, Opts); 9411 case llvm::Triple::GNU: 9412 return new MinGWX86_32TargetInfo(Triple, Opts); 9413 case llvm::Triple::Itanium: 9414 case llvm::Triple::MSVC: 9415 default: // Assume MSVC for unknown environments 9416 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9417 } 9418 } 9419 case llvm::Triple::Haiku: 9420 return new HaikuX86_32TargetInfo(Triple, Opts); 9421 case llvm::Triple::RTEMS: 9422 return new RTEMSX86_32TargetInfo(Triple, Opts); 9423 case llvm::Triple::NaCl: 9424 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9425 case llvm::Triple::ELFIAMCU: 9426 return new MCUX86_32TargetInfo(Triple, Opts); 9427 default: 9428 return new X86_32TargetInfo(Triple, Opts); 9429 } 9430 9431 case llvm::Triple::x86_64: 9432 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9433 return new DarwinX86_64TargetInfo(Triple, Opts); 9434 9435 switch (os) { 9436 case llvm::Triple::CloudABI: 9437 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9438 case llvm::Triple::Linux: { 9439 switch (Triple.getEnvironment()) { 9440 default: 9441 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9442 case llvm::Triple::Android: 9443 return new AndroidX86_64TargetInfo(Triple, Opts); 9444 } 9445 } 9446 case llvm::Triple::DragonFly: 9447 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9448 case llvm::Triple::NetBSD: 9449 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9450 case llvm::Triple::OpenBSD: 9451 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9452 case llvm::Triple::Bitrig: 9453 return new BitrigX86_64TargetInfo(Triple, Opts); 9454 case llvm::Triple::FreeBSD: 9455 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9456 case llvm::Triple::Fuchsia: 9457 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9458 case llvm::Triple::KFreeBSD: 9459 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9460 case llvm::Triple::Solaris: 9461 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9462 case llvm::Triple::Win32: { 9463 switch (Triple.getEnvironment()) { 9464 case llvm::Triple::Cygnus: 9465 return new CygwinX86_64TargetInfo(Triple, Opts); 9466 case llvm::Triple::GNU: 9467 return new MinGWX86_64TargetInfo(Triple, Opts); 9468 case llvm::Triple::MSVC: 9469 default: // Assume MSVC for unknown environments 9470 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9471 } 9472 } 9473 case llvm::Triple::Haiku: 9474 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9475 case llvm::Triple::NaCl: 9476 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9477 case llvm::Triple::PS4: 9478 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9479 default: 9480 return new X86_64TargetInfo(Triple, Opts); 9481 } 9482 9483 case llvm::Triple::spir: { 9484 if (Triple.getOS() != llvm::Triple::UnknownOS || 9485 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9486 return nullptr; 9487 return new SPIR32TargetInfo(Triple, Opts); 9488 } 9489 case llvm::Triple::spir64: { 9490 if (Triple.getOS() != llvm::Triple::UnknownOS || 9491 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9492 return nullptr; 9493 return new SPIR64TargetInfo(Triple, Opts); 9494 } 9495 case llvm::Triple::wasm32: 9496 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9497 Triple.getVendor() != llvm::Triple::UnknownVendor || 9498 Triple.getOS() != llvm::Triple::UnknownOS || 9499 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9500 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9501 return nullptr; 9502 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9503 case llvm::Triple::wasm64: 9504 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9505 Triple.getVendor() != llvm::Triple::UnknownVendor || 9506 Triple.getOS() != llvm::Triple::UnknownOS || 9507 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9508 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9509 return nullptr; 9510 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9511 9512 case llvm::Triple::renderscript32: 9513 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9514 case llvm::Triple::renderscript64: 9515 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9516 } 9517 } 9518 9519 /// CreateTargetInfo - Return the target info object for the specified target 9520 /// options. 9521 TargetInfo * 9522 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9523 const std::shared_ptr<TargetOptions> &Opts) { 9524 llvm::Triple Triple(Opts->Triple); 9525 9526 // Construct the target 9527 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9528 if (!Target) { 9529 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9530 return nullptr; 9531 } 9532 Target->TargetOpts = Opts; 9533 9534 // Set the target CPU if specified. 9535 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9536 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9537 return nullptr; 9538 } 9539 9540 // Set the target ABI if specified. 9541 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9542 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9543 return nullptr; 9544 } 9545 9546 // Set the fp math unit. 9547 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9548 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9549 return nullptr; 9550 } 9551 9552 // Compute the default target features, we need the target to handle this 9553 // because features may have dependencies on one another. 9554 llvm::StringMap<bool> Features; 9555 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9556 Opts->FeaturesAsWritten)) 9557 return nullptr; 9558 9559 // Add the features to the compile options. 9560 Opts->Features.clear(); 9561 for (const auto &F : Features) 9562 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9563 9564 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9565 return nullptr; 9566 9567 Target->setSupportedOpenCLOpts(); 9568 Target->setOpenCLExtensionOpts(); 9569 9570 if (!Target->validateTarget(Diags)) 9571 return nullptr; 9572 9573 return Target.release(); 9574 } 9575