1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.has(SanitizerKind::Address)) 97 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 template<typename Target> 188 class DarwinTargetInfo : public OSTargetInfo<Target> { 189 protected: 190 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 191 MacroBuilder &Builder) const override { 192 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 193 this->PlatformMinVersion); 194 } 195 196 public: 197 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 198 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 199 this->MCountName = "\01mcount"; 200 } 201 202 std::string isValidSectionSpecifier(StringRef SR) const override { 203 // Let MCSectionMachO validate this. 204 StringRef Segment, Section; 205 unsigned TAA, StubSize; 206 bool HasTAA; 207 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 208 TAA, HasTAA, StubSize); 209 } 210 211 const char *getStaticInitSectionSpecifier() const override { 212 // FIXME: We should return 0 when building kexts. 213 return "__TEXT,__StaticInit,regular,pure_instructions"; 214 } 215 216 /// Darwin does not support protected visibility. Darwin's "default" 217 /// is very similar to ELF's "protected"; Darwin requires a "weak" 218 /// attribute on declarations that can be dynamically replaced. 219 bool hasProtectedVisibility() const override { 220 return false; 221 } 222 }; 223 224 225 // DragonFlyBSD Target 226 template<typename Target> 227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 228 protected: 229 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 230 MacroBuilder &Builder) const override { 231 // DragonFly defines; list based off of gcc output 232 Builder.defineMacro("__DragonFly__"); 233 Builder.defineMacro("__DragonFly_cc_version", "100001"); 234 Builder.defineMacro("__ELF__"); 235 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 236 Builder.defineMacro("__tune_i386__"); 237 DefineStd(Builder, "unix", Opts); 238 } 239 public: 240 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 241 : OSTargetInfo<Target>(Triple) { 242 this->UserLabelPrefix = ""; 243 244 switch (Triple.getArch()) { 245 default: 246 case llvm::Triple::x86: 247 case llvm::Triple::x86_64: 248 this->MCountName = ".mcount"; 249 break; 250 } 251 } 252 }; 253 254 // FreeBSD Target 255 template<typename Target> 256 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 257 protected: 258 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 259 MacroBuilder &Builder) const override { 260 // FreeBSD defines; list based off of gcc output 261 262 unsigned Release = Triple.getOSMajorVersion(); 263 if (Release == 0U) 264 Release = 8; 265 266 Builder.defineMacro("__FreeBSD__", Twine(Release)); 267 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 268 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 269 DefineStd(Builder, "unix", Opts); 270 Builder.defineMacro("__ELF__"); 271 272 // On FreeBSD, wchar_t contains the number of the code point as 273 // used by the character set of the locale. These character sets are 274 // not necessarily a superset of ASCII. 275 // 276 // FIXME: This is wrong; the macro refers to the numerical values 277 // of wchar_t *literals*, which are not locale-dependent. However, 278 // FreeBSD systems apparently depend on us getting this wrong, and 279 // setting this to 1 is conforming even if all the basic source 280 // character literals have the same encoding as char and wchar_t. 281 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 282 } 283 public: 284 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 285 this->UserLabelPrefix = ""; 286 287 switch (Triple.getArch()) { 288 default: 289 case llvm::Triple::x86: 290 case llvm::Triple::x86_64: 291 this->MCountName = ".mcount"; 292 break; 293 case llvm::Triple::mips: 294 case llvm::Triple::mipsel: 295 case llvm::Triple::ppc: 296 case llvm::Triple::ppc64: 297 case llvm::Triple::ppc64le: 298 this->MCountName = "_mcount"; 299 break; 300 case llvm::Triple::arm: 301 this->MCountName = "__mcount"; 302 break; 303 } 304 } 305 }; 306 307 // GNU/kFreeBSD Target 308 template<typename Target> 309 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 310 protected: 311 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 312 MacroBuilder &Builder) const override { 313 // GNU/kFreeBSD defines; list based off of gcc output 314 315 DefineStd(Builder, "unix", Opts); 316 Builder.defineMacro("__FreeBSD_kernel__"); 317 Builder.defineMacro("__GLIBC__"); 318 Builder.defineMacro("__ELF__"); 319 if (Opts.POSIXThreads) 320 Builder.defineMacro("_REENTRANT"); 321 if (Opts.CPlusPlus) 322 Builder.defineMacro("_GNU_SOURCE"); 323 } 324 public: 325 KFreeBSDTargetInfo(const llvm::Triple &Triple) 326 : OSTargetInfo<Target>(Triple) { 327 this->UserLabelPrefix = ""; 328 } 329 }; 330 331 // Minix Target 332 template<typename Target> 333 class MinixTargetInfo : public OSTargetInfo<Target> { 334 protected: 335 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 336 MacroBuilder &Builder) const override { 337 // Minix defines 338 339 Builder.defineMacro("__minix", "3"); 340 Builder.defineMacro("_EM_WSIZE", "4"); 341 Builder.defineMacro("_EM_PSIZE", "4"); 342 Builder.defineMacro("_EM_SSIZE", "2"); 343 Builder.defineMacro("_EM_LSIZE", "4"); 344 Builder.defineMacro("_EM_FSIZE", "4"); 345 Builder.defineMacro("_EM_DSIZE", "8"); 346 Builder.defineMacro("__ELF__"); 347 DefineStd(Builder, "unix", Opts); 348 } 349 public: 350 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 351 this->UserLabelPrefix = ""; 352 } 353 }; 354 355 // Linux target 356 template<typename Target> 357 class LinuxTargetInfo : public OSTargetInfo<Target> { 358 protected: 359 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 360 MacroBuilder &Builder) const override { 361 // Linux defines; list based off of gcc output 362 DefineStd(Builder, "unix", Opts); 363 DefineStd(Builder, "linux", Opts); 364 Builder.defineMacro("__gnu_linux__"); 365 Builder.defineMacro("__ELF__"); 366 if (Triple.getEnvironment() == llvm::Triple::Android) 367 Builder.defineMacro("__ANDROID__", "1"); 368 if (Opts.POSIXThreads) 369 Builder.defineMacro("_REENTRANT"); 370 if (Opts.CPlusPlus) 371 Builder.defineMacro("_GNU_SOURCE"); 372 } 373 public: 374 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 375 this->UserLabelPrefix = ""; 376 this->WIntType = TargetInfo::UnsignedInt; 377 378 switch (Triple.getArch()) { 379 default: 380 break; 381 case llvm::Triple::ppc: 382 case llvm::Triple::ppc64: 383 case llvm::Triple::ppc64le: 384 this->MCountName = "_mcount"; 385 break; 386 } 387 } 388 389 const char *getStaticInitSectionSpecifier() const override { 390 return ".text.startup"; 391 } 392 }; 393 394 // NetBSD Target 395 template<typename Target> 396 class NetBSDTargetInfo : public OSTargetInfo<Target> { 397 protected: 398 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 399 MacroBuilder &Builder) const override { 400 // NetBSD defines; list based off of gcc output 401 Builder.defineMacro("__NetBSD__"); 402 Builder.defineMacro("__unix__"); 403 Builder.defineMacro("__ELF__"); 404 if (Opts.POSIXThreads) 405 Builder.defineMacro("_POSIX_THREADS"); 406 407 switch (Triple.getArch()) { 408 default: 409 break; 410 case llvm::Triple::arm: 411 case llvm::Triple::armeb: 412 case llvm::Triple::thumb: 413 case llvm::Triple::thumbeb: 414 Builder.defineMacro("__ARM_DWARF_EH__"); 415 break; 416 } 417 } 418 public: 419 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 420 this->UserLabelPrefix = ""; 421 } 422 }; 423 424 // OpenBSD Target 425 template<typename Target> 426 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 427 protected: 428 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 429 MacroBuilder &Builder) const override { 430 // OpenBSD defines; list based off of gcc output 431 432 Builder.defineMacro("__OpenBSD__"); 433 DefineStd(Builder, "unix", Opts); 434 Builder.defineMacro("__ELF__"); 435 if (Opts.POSIXThreads) 436 Builder.defineMacro("_REENTRANT"); 437 } 438 public: 439 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 440 this->UserLabelPrefix = ""; 441 this->TLSSupported = false; 442 443 switch (Triple.getArch()) { 444 default: 445 case llvm::Triple::x86: 446 case llvm::Triple::x86_64: 447 case llvm::Triple::arm: 448 case llvm::Triple::sparc: 449 this->MCountName = "__mcount"; 450 break; 451 case llvm::Triple::mips64: 452 case llvm::Triple::mips64el: 453 case llvm::Triple::ppc: 454 case llvm::Triple::sparcv9: 455 this->MCountName = "_mcount"; 456 break; 457 } 458 } 459 }; 460 461 // Bitrig Target 462 template<typename Target> 463 class BitrigTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const override { 467 // Bitrig defines; list based off of gcc output 468 469 Builder.defineMacro("__Bitrig__"); 470 DefineStd(Builder, "unix", Opts); 471 Builder.defineMacro("__ELF__"); 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 475 switch (Triple.getArch()) { 476 default: 477 break; 478 case llvm::Triple::arm: 479 case llvm::Triple::armeb: 480 case llvm::Triple::thumb: 481 case llvm::Triple::thumbeb: 482 Builder.defineMacro("__ARM_DWARF_EH__"); 483 break; 484 } 485 } 486 public: 487 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 488 this->UserLabelPrefix = ""; 489 this->MCountName = "__mcount"; 490 } 491 }; 492 493 // PSP Target 494 template<typename Target> 495 class PSPTargetInfo : public OSTargetInfo<Target> { 496 protected: 497 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 498 MacroBuilder &Builder) const override { 499 // PSP defines; list based on the output of the pspdev gcc toolchain. 500 Builder.defineMacro("PSP"); 501 Builder.defineMacro("_PSP"); 502 Builder.defineMacro("__psp__"); 503 Builder.defineMacro("__ELF__"); 504 } 505 public: 506 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 507 this->UserLabelPrefix = ""; 508 } 509 }; 510 511 // PS3 PPU Target 512 template<typename Target> 513 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 514 protected: 515 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const override { 517 // PS3 PPU defines. 518 Builder.defineMacro("__PPC__"); 519 Builder.defineMacro("__PPU__"); 520 Builder.defineMacro("__CELLOS_LV2__"); 521 Builder.defineMacro("__ELF__"); 522 Builder.defineMacro("__LP32__"); 523 Builder.defineMacro("_ARCH_PPC64"); 524 Builder.defineMacro("__powerpc64__"); 525 } 526 public: 527 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 528 this->UserLabelPrefix = ""; 529 this->LongWidth = this->LongAlign = 32; 530 this->PointerWidth = this->PointerAlign = 32; 531 this->IntMaxType = TargetInfo::SignedLongLong; 532 this->Int64Type = TargetInfo::SignedLongLong; 533 this->SizeType = TargetInfo::UnsignedInt; 534 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 535 } 536 }; 537 538 template <typename Target> 539 class PS4OSTargetInfo : public OSTargetInfo<Target> { 540 protected: 541 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 542 MacroBuilder &Builder) const override { 543 Builder.defineMacro("__FreeBSD__", "9"); 544 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 545 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 546 DefineStd(Builder, "unix", Opts); 547 Builder.defineMacro("__ELF__"); 548 Builder.defineMacro("__PS4__"); 549 } 550 public: 551 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 552 this->WCharType = this->UnsignedShort; 553 554 this->UserLabelPrefix = ""; 555 556 switch (Triple.getArch()) { 557 default: 558 case llvm::Triple::x86_64: 559 this->MCountName = ".mcount"; 560 break; 561 } 562 } 563 }; 564 565 // Solaris target 566 template<typename Target> 567 class SolarisTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const override { 571 DefineStd(Builder, "sun", Opts); 572 DefineStd(Builder, "unix", Opts); 573 Builder.defineMacro("__ELF__"); 574 Builder.defineMacro("__svr4__"); 575 Builder.defineMacro("__SVR4"); 576 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 577 // newer, but to 500 for everything else. feature_test.h has a check to 578 // ensure that you are not using C99 with an old version of X/Open or C89 579 // with a new version. 580 if (Opts.C99) 581 Builder.defineMacro("_XOPEN_SOURCE", "600"); 582 else 583 Builder.defineMacro("_XOPEN_SOURCE", "500"); 584 if (Opts.CPlusPlus) 585 Builder.defineMacro("__C99FEATURES__"); 586 Builder.defineMacro("_LARGEFILE_SOURCE"); 587 Builder.defineMacro("_LARGEFILE64_SOURCE"); 588 Builder.defineMacro("__EXTENSIONS__"); 589 Builder.defineMacro("_REENTRANT"); 590 } 591 public: 592 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 593 this->UserLabelPrefix = ""; 594 this->WCharType = this->SignedInt; 595 // FIXME: WIntType should be SignedLong 596 } 597 }; 598 599 // Windows target 600 template<typename Target> 601 class WindowsTargetInfo : public OSTargetInfo<Target> { 602 protected: 603 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 604 MacroBuilder &Builder) const override { 605 Builder.defineMacro("_WIN32"); 606 } 607 void getVisualStudioDefines(const LangOptions &Opts, 608 MacroBuilder &Builder) const { 609 if (Opts.CPlusPlus) { 610 if (Opts.RTTIData) 611 Builder.defineMacro("_CPPRTTI"); 612 613 if (Opts.CXXExceptions) 614 Builder.defineMacro("_CPPUNWIND"); 615 } 616 617 if (!Opts.CharIsSigned) 618 Builder.defineMacro("_CHAR_UNSIGNED"); 619 620 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 621 // but it works for now. 622 if (Opts.POSIXThreads) 623 Builder.defineMacro("_MT"); 624 625 if (Opts.MSCompatibilityVersion) { 626 Builder.defineMacro("_MSC_VER", 627 Twine(Opts.MSCompatibilityVersion / 100000)); 628 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 629 // FIXME We cannot encode the revision information into 32-bits 630 Builder.defineMacro("_MSC_BUILD", Twine(1)); 631 } 632 633 if (Opts.MicrosoftExt) { 634 Builder.defineMacro("_MSC_EXTENSIONS"); 635 636 if (Opts.CPlusPlus11) { 637 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 638 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 639 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 640 } 641 } 642 643 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 644 } 645 646 public: 647 WindowsTargetInfo(const llvm::Triple &Triple) 648 : OSTargetInfo<Target>(Triple) {} 649 }; 650 651 template <typename Target> 652 class NaClTargetInfo : public OSTargetInfo<Target> { 653 protected: 654 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 655 MacroBuilder &Builder) const override { 656 if (Opts.POSIXThreads) 657 Builder.defineMacro("_REENTRANT"); 658 if (Opts.CPlusPlus) 659 Builder.defineMacro("_GNU_SOURCE"); 660 661 DefineStd(Builder, "unix", Opts); 662 Builder.defineMacro("__ELF__"); 663 Builder.defineMacro("__native_client__"); 664 } 665 666 public: 667 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 668 this->UserLabelPrefix = ""; 669 this->LongAlign = 32; 670 this->LongWidth = 32; 671 this->PointerAlign = 32; 672 this->PointerWidth = 32; 673 this->IntMaxType = TargetInfo::SignedLongLong; 674 this->Int64Type = TargetInfo::SignedLongLong; 675 this->DoubleAlign = 64; 676 this->LongDoubleWidth = 64; 677 this->LongDoubleAlign = 64; 678 this->LongLongWidth = 64; 679 this->LongLongAlign = 64; 680 this->SizeType = TargetInfo::UnsignedInt; 681 this->PtrDiffType = TargetInfo::SignedInt; 682 this->IntPtrType = TargetInfo::SignedInt; 683 // RegParmMax is inherited from the underlying architecture 684 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 685 if (Triple.getArch() == llvm::Triple::arm) { 686 this->DescriptionString = 687 "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 688 } else if (Triple.getArch() == llvm::Triple::x86) { 689 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 690 } else if (Triple.getArch() == llvm::Triple::x86_64) { 691 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 692 } else if (Triple.getArch() == llvm::Triple::mipsel) { 693 // Handled on mips' setDescriptionString. 694 } else { 695 assert(Triple.getArch() == llvm::Triple::le32); 696 this->DescriptionString = "e-p:32:32-i64:64"; 697 } 698 } 699 }; 700 } // end anonymous namespace. 701 702 //===----------------------------------------------------------------------===// 703 // Specific target implementations. 704 //===----------------------------------------------------------------------===// 705 706 namespace { 707 // PPC abstract base class 708 class PPCTargetInfo : public TargetInfo { 709 static const Builtin::Info BuiltinInfo[]; 710 static const char * const GCCRegNames[]; 711 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 712 std::string CPU; 713 714 // Target cpu features. 715 bool HasVSX; 716 bool HasP8Vector; 717 718 protected: 719 std::string ABI; 720 721 public: 722 PPCTargetInfo(const llvm::Triple &Triple) 723 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) { 724 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 725 LongDoubleWidth = LongDoubleAlign = 128; 726 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 727 } 728 729 /// \brief Flags for architecture specific defines. 730 typedef enum { 731 ArchDefineNone = 0, 732 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 733 ArchDefinePpcgr = 1 << 1, 734 ArchDefinePpcsq = 1 << 2, 735 ArchDefine440 = 1 << 3, 736 ArchDefine603 = 1 << 4, 737 ArchDefine604 = 1 << 5, 738 ArchDefinePwr4 = 1 << 6, 739 ArchDefinePwr5 = 1 << 7, 740 ArchDefinePwr5x = 1 << 8, 741 ArchDefinePwr6 = 1 << 9, 742 ArchDefinePwr6x = 1 << 10, 743 ArchDefinePwr7 = 1 << 11, 744 ArchDefinePwr8 = 1 << 12, 745 ArchDefineA2 = 1 << 13, 746 ArchDefineA2q = 1 << 14 747 } ArchDefineTypes; 748 749 // Note: GCC recognizes the following additional cpus: 750 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 751 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 752 // titan, rs64. 753 bool setCPU(const std::string &Name) override { 754 bool CPUKnown = llvm::StringSwitch<bool>(Name) 755 .Case("generic", true) 756 .Case("440", true) 757 .Case("450", true) 758 .Case("601", true) 759 .Case("602", true) 760 .Case("603", true) 761 .Case("603e", true) 762 .Case("603ev", true) 763 .Case("604", true) 764 .Case("604e", true) 765 .Case("620", true) 766 .Case("630", true) 767 .Case("g3", true) 768 .Case("7400", true) 769 .Case("g4", true) 770 .Case("7450", true) 771 .Case("g4+", true) 772 .Case("750", true) 773 .Case("970", true) 774 .Case("g5", true) 775 .Case("a2", true) 776 .Case("a2q", true) 777 .Case("e500mc", true) 778 .Case("e5500", true) 779 .Case("power3", true) 780 .Case("pwr3", true) 781 .Case("power4", true) 782 .Case("pwr4", true) 783 .Case("power5", true) 784 .Case("pwr5", true) 785 .Case("power5x", true) 786 .Case("pwr5x", true) 787 .Case("power6", true) 788 .Case("pwr6", true) 789 .Case("power6x", true) 790 .Case("pwr6x", true) 791 .Case("power7", true) 792 .Case("pwr7", true) 793 .Case("power8", true) 794 .Case("pwr8", true) 795 .Case("powerpc", true) 796 .Case("ppc", true) 797 .Case("powerpc64", true) 798 .Case("ppc64", true) 799 .Case("powerpc64le", true) 800 .Case("ppc64le", true) 801 .Default(false); 802 803 if (CPUKnown) 804 CPU = Name; 805 806 return CPUKnown; 807 } 808 809 810 StringRef getABI() const override { return ABI; } 811 812 void getTargetBuiltins(const Builtin::Info *&Records, 813 unsigned &NumRecords) const override { 814 Records = BuiltinInfo; 815 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 816 } 817 818 bool isCLZForZeroUndef() const override { return false; } 819 820 void getTargetDefines(const LangOptions &Opts, 821 MacroBuilder &Builder) const override; 822 823 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 824 825 bool handleTargetFeatures(std::vector<std::string> &Features, 826 DiagnosticsEngine &Diags) override; 827 bool hasFeature(StringRef Feature) const override; 828 829 void getGCCRegNames(const char * const *&Names, 830 unsigned &NumNames) const override; 831 void getGCCRegAliases(const GCCRegAlias *&Aliases, 832 unsigned &NumAliases) const override; 833 bool validateAsmConstraint(const char *&Name, 834 TargetInfo::ConstraintInfo &Info) const override { 835 switch (*Name) { 836 default: return false; 837 case 'O': // Zero 838 break; 839 case 'b': // Base register 840 case 'f': // Floating point register 841 Info.setAllowsRegister(); 842 break; 843 // FIXME: The following are added to allow parsing. 844 // I just took a guess at what the actions should be. 845 // Also, is more specific checking needed? I.e. specific registers? 846 case 'd': // Floating point register (containing 64-bit value) 847 case 'v': // Altivec vector register 848 Info.setAllowsRegister(); 849 break; 850 case 'w': 851 switch (Name[1]) { 852 case 'd':// VSX vector register to hold vector double data 853 case 'f':// VSX vector register to hold vector float data 854 case 's':// VSX vector register to hold scalar float data 855 case 'a':// Any VSX register 856 case 'c':// An individual CR bit 857 break; 858 default: 859 return false; 860 } 861 Info.setAllowsRegister(); 862 Name++; // Skip over 'w'. 863 break; 864 case 'h': // `MQ', `CTR', or `LINK' register 865 case 'q': // `MQ' register 866 case 'c': // `CTR' register 867 case 'l': // `LINK' register 868 case 'x': // `CR' register (condition register) number 0 869 case 'y': // `CR' register (condition register) 870 case 'z': // `XER[CA]' carry bit (part of the XER register) 871 Info.setAllowsRegister(); 872 break; 873 case 'I': // Signed 16-bit constant 874 case 'J': // Unsigned 16-bit constant shifted left 16 bits 875 // (use `L' instead for SImode constants) 876 case 'K': // Unsigned 16-bit constant 877 case 'L': // Signed 16-bit constant shifted left 16 bits 878 case 'M': // Constant larger than 31 879 case 'N': // Exact power of 2 880 case 'P': // Constant whose negation is a signed 16-bit constant 881 case 'G': // Floating point constant that can be loaded into a 882 // register with one instruction per word 883 case 'H': // Integer/Floating point constant that can be loaded 884 // into a register using three instructions 885 break; 886 case 'm': // Memory operand. Note that on PowerPC targets, m can 887 // include addresses that update the base register. It 888 // is therefore only safe to use `m' in an asm statement 889 // if that asm statement accesses the operand exactly once. 890 // The asm statement must also use `%U<opno>' as a 891 // placeholder for the "update" flag in the corresponding 892 // load or store instruction. For example: 893 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 894 // is correct but: 895 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 896 // is not. Use es rather than m if you don't want the base 897 // register to be updated. 898 case 'e': 899 if (Name[1] != 's') 900 return false; 901 // es: A "stable" memory operand; that is, one which does not 902 // include any automodification of the base register. Unlike 903 // `m', this constraint can be used in asm statements that 904 // might access the operand several times, or that might not 905 // access it at all. 906 Info.setAllowsMemory(); 907 Name++; // Skip over 'e'. 908 break; 909 case 'Q': // Memory operand that is an offset from a register (it is 910 // usually better to use `m' or `es' in asm statements) 911 case 'Z': // Memory operand that is an indexed or indirect from a 912 // register (it is usually better to use `m' or `es' in 913 // asm statements) 914 Info.setAllowsMemory(); 915 Info.setAllowsRegister(); 916 break; 917 case 'R': // AIX TOC entry 918 case 'a': // Address operand that is an indexed or indirect from a 919 // register (`p' is preferable for asm statements) 920 case 'S': // Constant suitable as a 64-bit mask operand 921 case 'T': // Constant suitable as a 32-bit mask operand 922 case 'U': // System V Release 4 small data area reference 923 case 't': // AND masks that can be performed by two rldic{l, r} 924 // instructions 925 case 'W': // Vector constant that does not require memory 926 case 'j': // Vector constant that is all zeros. 927 break; 928 // End FIXME. 929 } 930 return true; 931 } 932 std::string convertConstraint(const char *&Constraint) const override { 933 std::string R; 934 switch (*Constraint) { 935 case 'e': 936 case 'w': 937 // Two-character constraint; add "^" hint for later parsing. 938 R = std::string("^") + std::string(Constraint, 2); 939 Constraint++; 940 break; 941 default: 942 return TargetInfo::convertConstraint(Constraint); 943 } 944 return R; 945 } 946 const char *getClobbers() const override { 947 return ""; 948 } 949 int getEHDataRegisterNumber(unsigned RegNo) const override { 950 if (RegNo == 0) return 3; 951 if (RegNo == 1) return 4; 952 return -1; 953 } 954 }; 955 956 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 957 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 958 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 959 ALL_LANGUAGES }, 960 #include "clang/Basic/BuiltinsPPC.def" 961 }; 962 963 /// handleTargetFeatures - Perform initialization based on the user 964 /// configured set of features. 965 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 966 DiagnosticsEngine &Diags) { 967 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 968 // Ignore disabled features. 969 if (Features[i][0] == '-') 970 continue; 971 972 StringRef Feature = StringRef(Features[i]).substr(1); 973 974 if (Feature == "vsx") { 975 HasVSX = true; 976 continue; 977 } 978 979 if (Feature == "power8-vector") { 980 HasP8Vector = true; 981 continue; 982 } 983 984 // TODO: Finish this list and add an assert that we've handled them 985 // all. 986 } 987 988 return true; 989 } 990 991 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 992 /// #defines that are not tied to a specific subtarget. 993 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 994 MacroBuilder &Builder) const { 995 // Target identification. 996 Builder.defineMacro("__ppc__"); 997 Builder.defineMacro("__PPC__"); 998 Builder.defineMacro("_ARCH_PPC"); 999 Builder.defineMacro("__powerpc__"); 1000 Builder.defineMacro("__POWERPC__"); 1001 if (PointerWidth == 64) { 1002 Builder.defineMacro("_ARCH_PPC64"); 1003 Builder.defineMacro("__powerpc64__"); 1004 Builder.defineMacro("__ppc64__"); 1005 Builder.defineMacro("__PPC64__"); 1006 } 1007 1008 // Target properties. 1009 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1010 Builder.defineMacro("_LITTLE_ENDIAN"); 1011 } else { 1012 if (getTriple().getOS() != llvm::Triple::NetBSD && 1013 getTriple().getOS() != llvm::Triple::OpenBSD) 1014 Builder.defineMacro("_BIG_ENDIAN"); 1015 } 1016 1017 // ABI options. 1018 if (ABI == "elfv1") 1019 Builder.defineMacro("_CALL_ELF", "1"); 1020 if (ABI == "elfv2") 1021 Builder.defineMacro("_CALL_ELF", "2"); 1022 1023 // Subtarget options. 1024 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1025 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1026 1027 // FIXME: Should be controlled by command line option. 1028 if (LongDoubleWidth == 128) 1029 Builder.defineMacro("__LONG_DOUBLE_128__"); 1030 1031 if (Opts.AltiVec) { 1032 Builder.defineMacro("__VEC__", "10206"); 1033 Builder.defineMacro("__ALTIVEC__"); 1034 } 1035 1036 // CPU identification. 1037 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1038 .Case("440", ArchDefineName) 1039 .Case("450", ArchDefineName | ArchDefine440) 1040 .Case("601", ArchDefineName) 1041 .Case("602", ArchDefineName | ArchDefinePpcgr) 1042 .Case("603", ArchDefineName | ArchDefinePpcgr) 1043 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1044 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1045 .Case("604", ArchDefineName | ArchDefinePpcgr) 1046 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1047 .Case("620", ArchDefineName | ArchDefinePpcgr) 1048 .Case("630", ArchDefineName | ArchDefinePpcgr) 1049 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1050 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1051 .Case("750", ArchDefineName | ArchDefinePpcgr) 1052 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1053 | ArchDefinePpcsq) 1054 .Case("a2", ArchDefineA2) 1055 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1056 .Case("pwr3", ArchDefinePpcgr) 1057 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1058 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1059 | ArchDefinePpcsq) 1060 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1061 | ArchDefinePpcgr | ArchDefinePpcsq) 1062 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1063 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1064 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1065 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1066 | ArchDefinePpcsq) 1067 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1068 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1069 | ArchDefinePpcgr | ArchDefinePpcsq) 1070 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1071 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1072 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1073 .Case("power3", ArchDefinePpcgr) 1074 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1075 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1076 | ArchDefinePpcsq) 1077 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1078 | ArchDefinePpcgr | ArchDefinePpcsq) 1079 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1080 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1081 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1082 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1083 | ArchDefinePpcsq) 1084 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1085 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1086 | ArchDefinePpcgr | ArchDefinePpcsq) 1087 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1088 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1089 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1090 .Default(ArchDefineNone); 1091 1092 if (defs & ArchDefineName) 1093 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1094 if (defs & ArchDefinePpcgr) 1095 Builder.defineMacro("_ARCH_PPCGR"); 1096 if (defs & ArchDefinePpcsq) 1097 Builder.defineMacro("_ARCH_PPCSQ"); 1098 if (defs & ArchDefine440) 1099 Builder.defineMacro("_ARCH_440"); 1100 if (defs & ArchDefine603) 1101 Builder.defineMacro("_ARCH_603"); 1102 if (defs & ArchDefine604) 1103 Builder.defineMacro("_ARCH_604"); 1104 if (defs & ArchDefinePwr4) 1105 Builder.defineMacro("_ARCH_PWR4"); 1106 if (defs & ArchDefinePwr5) 1107 Builder.defineMacro("_ARCH_PWR5"); 1108 if (defs & ArchDefinePwr5x) 1109 Builder.defineMacro("_ARCH_PWR5X"); 1110 if (defs & ArchDefinePwr6) 1111 Builder.defineMacro("_ARCH_PWR6"); 1112 if (defs & ArchDefinePwr6x) 1113 Builder.defineMacro("_ARCH_PWR6X"); 1114 if (defs & ArchDefinePwr7) 1115 Builder.defineMacro("_ARCH_PWR7"); 1116 if (defs & ArchDefinePwr8) 1117 Builder.defineMacro("_ARCH_PWR8"); 1118 if (defs & ArchDefineA2) 1119 Builder.defineMacro("_ARCH_A2"); 1120 if (defs & ArchDefineA2q) { 1121 Builder.defineMacro("_ARCH_A2Q"); 1122 Builder.defineMacro("_ARCH_QP"); 1123 } 1124 1125 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1126 Builder.defineMacro("__bg__"); 1127 Builder.defineMacro("__THW_BLUEGENE__"); 1128 Builder.defineMacro("__bgq__"); 1129 Builder.defineMacro("__TOS_BGQ__"); 1130 } 1131 1132 if (HasVSX) 1133 Builder.defineMacro("__VSX__"); 1134 if (HasP8Vector) 1135 Builder.defineMacro("__POWER8_VECTOR__"); 1136 1137 // FIXME: The following are not yet generated here by Clang, but are 1138 // generated by GCC: 1139 // 1140 // _SOFT_FLOAT_ 1141 // __RECIP_PRECISION__ 1142 // __APPLE_ALTIVEC__ 1143 // __RECIP__ 1144 // __RECIPF__ 1145 // __RSQRTE__ 1146 // __RSQRTEF__ 1147 // _SOFT_DOUBLE_ 1148 // __NO_LWSYNC__ 1149 // __HAVE_BSWAP__ 1150 // __LONGDOUBLE128 1151 // __CMODEL_MEDIUM__ 1152 // __CMODEL_LARGE__ 1153 // _CALL_SYSV 1154 // _CALL_DARWIN 1155 // __NO_FPRS__ 1156 } 1157 1158 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1159 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1160 .Case("7400", true) 1161 .Case("g4", true) 1162 .Case("7450", true) 1163 .Case("g4+", true) 1164 .Case("970", true) 1165 .Case("g5", true) 1166 .Case("pwr6", true) 1167 .Case("pwr7", true) 1168 .Case("pwr8", true) 1169 .Case("ppc64", true) 1170 .Case("ppc64le", true) 1171 .Default(false); 1172 1173 Features["qpx"] = (CPU == "a2q"); 1174 } 1175 1176 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1177 return llvm::StringSwitch<bool>(Feature) 1178 .Case("powerpc", true) 1179 .Case("vsx", HasVSX) 1180 .Case("power8-vector", HasP8Vector) 1181 .Default(false); 1182 } 1183 1184 const char * const PPCTargetInfo::GCCRegNames[] = { 1185 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1186 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1187 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1188 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1189 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1190 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1191 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1192 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1193 "mq", "lr", "ctr", "ap", 1194 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1195 "xer", 1196 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1197 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1198 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1199 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1200 "vrsave", "vscr", 1201 "spe_acc", "spefscr", 1202 "sfp" 1203 }; 1204 1205 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1206 unsigned &NumNames) const { 1207 Names = GCCRegNames; 1208 NumNames = llvm::array_lengthof(GCCRegNames); 1209 } 1210 1211 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1212 // While some of these aliases do map to different registers 1213 // they still share the same register name. 1214 { { "0" }, "r0" }, 1215 { { "1"}, "r1" }, 1216 { { "2" }, "r2" }, 1217 { { "3" }, "r3" }, 1218 { { "4" }, "r4" }, 1219 { { "5" }, "r5" }, 1220 { { "6" }, "r6" }, 1221 { { "7" }, "r7" }, 1222 { { "8" }, "r8" }, 1223 { { "9" }, "r9" }, 1224 { { "10" }, "r10" }, 1225 { { "11" }, "r11" }, 1226 { { "12" }, "r12" }, 1227 { { "13" }, "r13" }, 1228 { { "14" }, "r14" }, 1229 { { "15" }, "r15" }, 1230 { { "16" }, "r16" }, 1231 { { "17" }, "r17" }, 1232 { { "18" }, "r18" }, 1233 { { "19" }, "r19" }, 1234 { { "20" }, "r20" }, 1235 { { "21" }, "r21" }, 1236 { { "22" }, "r22" }, 1237 { { "23" }, "r23" }, 1238 { { "24" }, "r24" }, 1239 { { "25" }, "r25" }, 1240 { { "26" }, "r26" }, 1241 { { "27" }, "r27" }, 1242 { { "28" }, "r28" }, 1243 { { "29" }, "r29" }, 1244 { { "30" }, "r30" }, 1245 { { "31" }, "r31" }, 1246 { { "fr0" }, "f0" }, 1247 { { "fr1" }, "f1" }, 1248 { { "fr2" }, "f2" }, 1249 { { "fr3" }, "f3" }, 1250 { { "fr4" }, "f4" }, 1251 { { "fr5" }, "f5" }, 1252 { { "fr6" }, "f6" }, 1253 { { "fr7" }, "f7" }, 1254 { { "fr8" }, "f8" }, 1255 { { "fr9" }, "f9" }, 1256 { { "fr10" }, "f10" }, 1257 { { "fr11" }, "f11" }, 1258 { { "fr12" }, "f12" }, 1259 { { "fr13" }, "f13" }, 1260 { { "fr14" }, "f14" }, 1261 { { "fr15" }, "f15" }, 1262 { { "fr16" }, "f16" }, 1263 { { "fr17" }, "f17" }, 1264 { { "fr18" }, "f18" }, 1265 { { "fr19" }, "f19" }, 1266 { { "fr20" }, "f20" }, 1267 { { "fr21" }, "f21" }, 1268 { { "fr22" }, "f22" }, 1269 { { "fr23" }, "f23" }, 1270 { { "fr24" }, "f24" }, 1271 { { "fr25" }, "f25" }, 1272 { { "fr26" }, "f26" }, 1273 { { "fr27" }, "f27" }, 1274 { { "fr28" }, "f28" }, 1275 { { "fr29" }, "f29" }, 1276 { { "fr30" }, "f30" }, 1277 { { "fr31" }, "f31" }, 1278 { { "cc" }, "cr0" }, 1279 }; 1280 1281 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1282 unsigned &NumAliases) const { 1283 Aliases = GCCRegAliases; 1284 NumAliases = llvm::array_lengthof(GCCRegAliases); 1285 } 1286 } // end anonymous namespace. 1287 1288 namespace { 1289 class PPC32TargetInfo : public PPCTargetInfo { 1290 public: 1291 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1292 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1293 1294 switch (getTriple().getOS()) { 1295 case llvm::Triple::Linux: 1296 case llvm::Triple::FreeBSD: 1297 case llvm::Triple::NetBSD: 1298 SizeType = UnsignedInt; 1299 PtrDiffType = SignedInt; 1300 IntPtrType = SignedInt; 1301 break; 1302 default: 1303 break; 1304 } 1305 1306 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1307 LongDoubleWidth = LongDoubleAlign = 64; 1308 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1309 } 1310 1311 // PPC32 supports atomics up to 4 bytes. 1312 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1313 } 1314 1315 BuiltinVaListKind getBuiltinVaListKind() const override { 1316 // This is the ELF definition, and is overridden by the Darwin sub-target 1317 return TargetInfo::PowerABIBuiltinVaList; 1318 } 1319 }; 1320 } // end anonymous namespace. 1321 1322 // Note: ABI differences may eventually require us to have a separate 1323 // TargetInfo for little endian. 1324 namespace { 1325 class PPC64TargetInfo : public PPCTargetInfo { 1326 public: 1327 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1328 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1329 IntMaxType = SignedLong; 1330 Int64Type = SignedLong; 1331 1332 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1333 DescriptionString = "e-m:e-i64:64-n32:64"; 1334 ABI = "elfv2"; 1335 } else { 1336 DescriptionString = "E-m:e-i64:64-n32:64"; 1337 ABI = "elfv1"; 1338 } 1339 1340 switch (getTriple().getOS()) { 1341 case llvm::Triple::FreeBSD: 1342 LongDoubleWidth = LongDoubleAlign = 64; 1343 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1344 break; 1345 case llvm::Triple::NetBSD: 1346 IntMaxType = SignedLongLong; 1347 Int64Type = SignedLongLong; 1348 break; 1349 default: 1350 break; 1351 } 1352 1353 // PPC64 supports atomics up to 8 bytes. 1354 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1355 } 1356 BuiltinVaListKind getBuiltinVaListKind() const override { 1357 return TargetInfo::CharPtrBuiltinVaList; 1358 } 1359 // PPC64 Linux-specifc ABI options. 1360 bool setABI(const std::string &Name) override { 1361 if (Name == "elfv1" || Name == "elfv2") { 1362 ABI = Name; 1363 return true; 1364 } 1365 return false; 1366 } 1367 }; 1368 } // end anonymous namespace. 1369 1370 1371 namespace { 1372 class DarwinPPC32TargetInfo : 1373 public DarwinTargetInfo<PPC32TargetInfo> { 1374 public: 1375 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1376 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1377 HasAlignMac68kSupport = true; 1378 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1379 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1380 LongLongAlign = 32; 1381 SuitableAlign = 128; 1382 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1383 } 1384 BuiltinVaListKind getBuiltinVaListKind() const override { 1385 return TargetInfo::CharPtrBuiltinVaList; 1386 } 1387 }; 1388 1389 class DarwinPPC64TargetInfo : 1390 public DarwinTargetInfo<PPC64TargetInfo> { 1391 public: 1392 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1393 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1394 HasAlignMac68kSupport = true; 1395 SuitableAlign = 128; 1396 DescriptionString = "E-m:o-i64:64-n32:64"; 1397 } 1398 }; 1399 } // end anonymous namespace. 1400 1401 namespace { 1402 static const unsigned NVPTXAddrSpaceMap[] = { 1403 1, // opencl_global 1404 3, // opencl_local 1405 4, // opencl_constant 1406 // FIXME: generic has to be added to the target 1407 0, // opencl_generic 1408 1, // cuda_device 1409 4, // cuda_constant 1410 3, // cuda_shared 1411 }; 1412 class NVPTXTargetInfo : public TargetInfo { 1413 static const char * const GCCRegNames[]; 1414 static const Builtin::Info BuiltinInfo[]; 1415 1416 // The GPU profiles supported by the NVPTX backend 1417 enum GPUKind { 1418 GK_NONE, 1419 GK_SM20, 1420 GK_SM21, 1421 GK_SM30, 1422 GK_SM35, 1423 } GPU; 1424 1425 public: 1426 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1427 BigEndian = false; 1428 TLSSupported = false; 1429 LongWidth = LongAlign = 64; 1430 AddrSpaceMap = &NVPTXAddrSpaceMap; 1431 UseAddrSpaceMapMangling = true; 1432 // Define available target features 1433 // These must be defined in sorted order! 1434 NoAsmVariants = true; 1435 // Set the default GPU to sm20 1436 GPU = GK_SM20; 1437 } 1438 void getTargetDefines(const LangOptions &Opts, 1439 MacroBuilder &Builder) const override { 1440 Builder.defineMacro("__PTX__"); 1441 Builder.defineMacro("__NVPTX__"); 1442 if (Opts.CUDAIsDevice) { 1443 // Set __CUDA_ARCH__ for the GPU specified. 1444 std::string CUDAArchCode; 1445 switch (GPU) { 1446 case GK_SM20: 1447 CUDAArchCode = "200"; 1448 break; 1449 case GK_SM21: 1450 CUDAArchCode = "210"; 1451 break; 1452 case GK_SM30: 1453 CUDAArchCode = "300"; 1454 break; 1455 case GK_SM35: 1456 CUDAArchCode = "350"; 1457 break; 1458 default: 1459 llvm_unreachable("Unhandled target CPU"); 1460 } 1461 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1462 } 1463 } 1464 void getTargetBuiltins(const Builtin::Info *&Records, 1465 unsigned &NumRecords) const override { 1466 Records = BuiltinInfo; 1467 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1468 } 1469 bool hasFeature(StringRef Feature) const override { 1470 return Feature == "ptx" || Feature == "nvptx"; 1471 } 1472 1473 void getGCCRegNames(const char * const *&Names, 1474 unsigned &NumNames) const override; 1475 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1476 unsigned &NumAliases) const override { 1477 // No aliases. 1478 Aliases = nullptr; 1479 NumAliases = 0; 1480 } 1481 bool 1482 validateAsmConstraint(const char *&Name, 1483 TargetInfo::ConstraintInfo &Info) const override { 1484 switch (*Name) { 1485 default: return false; 1486 case 'c': 1487 case 'h': 1488 case 'r': 1489 case 'l': 1490 case 'f': 1491 case 'd': 1492 Info.setAllowsRegister(); 1493 return true; 1494 } 1495 } 1496 const char *getClobbers() const override { 1497 // FIXME: Is this really right? 1498 return ""; 1499 } 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // FIXME: implement 1502 return TargetInfo::CharPtrBuiltinVaList; 1503 } 1504 bool setCPU(const std::string &Name) override { 1505 GPU = llvm::StringSwitch<GPUKind>(Name) 1506 .Case("sm_20", GK_SM20) 1507 .Case("sm_21", GK_SM21) 1508 .Case("sm_30", GK_SM30) 1509 .Case("sm_35", GK_SM35) 1510 .Default(GK_NONE); 1511 1512 return GPU != GK_NONE; 1513 } 1514 }; 1515 1516 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1517 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1518 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1519 ALL_LANGUAGES }, 1520 #include "clang/Basic/BuiltinsNVPTX.def" 1521 }; 1522 1523 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1524 "r0" 1525 }; 1526 1527 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1528 unsigned &NumNames) const { 1529 Names = GCCRegNames; 1530 NumNames = llvm::array_lengthof(GCCRegNames); 1531 } 1532 1533 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1534 public: 1535 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1536 PointerWidth = PointerAlign = 32; 1537 SizeType = PtrDiffType = TargetInfo::UnsignedInt; 1538 IntPtrType = TargetInfo::SignedInt; 1539 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1540 } 1541 }; 1542 1543 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1544 public: 1545 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1546 PointerWidth = PointerAlign = 64; 1547 SizeType = PtrDiffType = TargetInfo::UnsignedLongLong; 1548 IntPtrType = TargetInfo::SignedLongLong; 1549 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1550 } 1551 }; 1552 } 1553 1554 namespace { 1555 1556 static const unsigned R600AddrSpaceMap[] = { 1557 1, // opencl_global 1558 3, // opencl_local 1559 2, // opencl_constant 1560 4, // opencl_generic 1561 1, // cuda_device 1562 2, // cuda_constant 1563 3 // cuda_shared 1564 }; 1565 1566 // If you edit the description strings, make sure you update 1567 // getPointerWidthV(). 1568 1569 static const char *DescriptionStringR600 = 1570 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1571 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1572 1573 static const char *DescriptionStringR600DoubleOps = 1574 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1575 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1576 1577 static const char *DescriptionStringSI = 1578 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1579 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1580 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1581 1582 class R600TargetInfo : public TargetInfo { 1583 static const Builtin::Info BuiltinInfo[]; 1584 1585 /// \brief The GPU profiles supported by the R600 target. 1586 enum GPUKind { 1587 GK_NONE, 1588 GK_R600, 1589 GK_R600_DOUBLE_OPS, 1590 GK_R700, 1591 GK_R700_DOUBLE_OPS, 1592 GK_EVERGREEN, 1593 GK_EVERGREEN_DOUBLE_OPS, 1594 GK_NORTHERN_ISLANDS, 1595 GK_CAYMAN, 1596 GK_SOUTHERN_ISLANDS, 1597 GK_SEA_ISLANDS 1598 } GPU; 1599 1600 public: 1601 R600TargetInfo(const llvm::Triple &Triple) 1602 : TargetInfo(Triple) { 1603 1604 if (Triple.getArch() == llvm::Triple::amdgcn) { 1605 DescriptionString = DescriptionStringSI; 1606 GPU = GK_SOUTHERN_ISLANDS; 1607 } else { 1608 DescriptionString = DescriptionStringR600; 1609 GPU = GK_R600; 1610 } 1611 AddrSpaceMap = &R600AddrSpaceMap; 1612 UseAddrSpaceMapMangling = true; 1613 } 1614 1615 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1616 if (GPU <= GK_CAYMAN) 1617 return 32; 1618 1619 switch(AddrSpace) { 1620 default: 1621 return 64; 1622 case 0: 1623 case 3: 1624 case 5: 1625 return 32; 1626 } 1627 } 1628 1629 const char * getClobbers() const override { 1630 return ""; 1631 } 1632 1633 void getGCCRegNames(const char * const *&Names, 1634 unsigned &numNames) const override { 1635 Names = nullptr; 1636 numNames = 0; 1637 } 1638 1639 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1640 unsigned &NumAliases) const override { 1641 Aliases = nullptr; 1642 NumAliases = 0; 1643 } 1644 1645 bool validateAsmConstraint(const char *&Name, 1646 TargetInfo::ConstraintInfo &info) const override { 1647 return true; 1648 } 1649 1650 void getTargetBuiltins(const Builtin::Info *&Records, 1651 unsigned &NumRecords) const override { 1652 Records = BuiltinInfo; 1653 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1654 } 1655 1656 void getTargetDefines(const LangOptions &Opts, 1657 MacroBuilder &Builder) const override { 1658 Builder.defineMacro("__R600__"); 1659 if (GPU >= GK_SOUTHERN_ISLANDS && Opts.OpenCL) 1660 Builder.defineMacro("cl_khr_fp64"); 1661 } 1662 1663 BuiltinVaListKind getBuiltinVaListKind() const override { 1664 return TargetInfo::CharPtrBuiltinVaList; 1665 } 1666 1667 bool setCPU(const std::string &Name) override { 1668 GPU = llvm::StringSwitch<GPUKind>(Name) 1669 .Case("r600" , GK_R600) 1670 .Case("rv610", GK_R600) 1671 .Case("rv620", GK_R600) 1672 .Case("rv630", GK_R600) 1673 .Case("rv635", GK_R600) 1674 .Case("rs780", GK_R600) 1675 .Case("rs880", GK_R600) 1676 .Case("rv670", GK_R600_DOUBLE_OPS) 1677 .Case("rv710", GK_R700) 1678 .Case("rv730", GK_R700) 1679 .Case("rv740", GK_R700_DOUBLE_OPS) 1680 .Case("rv770", GK_R700_DOUBLE_OPS) 1681 .Case("palm", GK_EVERGREEN) 1682 .Case("cedar", GK_EVERGREEN) 1683 .Case("sumo", GK_EVERGREEN) 1684 .Case("sumo2", GK_EVERGREEN) 1685 .Case("redwood", GK_EVERGREEN) 1686 .Case("juniper", GK_EVERGREEN) 1687 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1688 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1689 .Case("barts", GK_NORTHERN_ISLANDS) 1690 .Case("turks", GK_NORTHERN_ISLANDS) 1691 .Case("caicos", GK_NORTHERN_ISLANDS) 1692 .Case("cayman", GK_CAYMAN) 1693 .Case("aruba", GK_CAYMAN) 1694 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1695 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1696 .Case("verde", GK_SOUTHERN_ISLANDS) 1697 .Case("oland", GK_SOUTHERN_ISLANDS) 1698 .Case("hainan", GK_SOUTHERN_ISLANDS) 1699 .Case("bonaire", GK_SEA_ISLANDS) 1700 .Case("kabini", GK_SEA_ISLANDS) 1701 .Case("kaveri", GK_SEA_ISLANDS) 1702 .Case("hawaii", GK_SEA_ISLANDS) 1703 .Case("mullins", GK_SEA_ISLANDS) 1704 .Default(GK_NONE); 1705 1706 if (GPU == GK_NONE) { 1707 return false; 1708 } 1709 1710 // Set the correct data layout 1711 switch (GPU) { 1712 case GK_NONE: 1713 case GK_R600: 1714 case GK_R700: 1715 case GK_EVERGREEN: 1716 case GK_NORTHERN_ISLANDS: 1717 DescriptionString = DescriptionStringR600; 1718 break; 1719 case GK_R600_DOUBLE_OPS: 1720 case GK_R700_DOUBLE_OPS: 1721 case GK_EVERGREEN_DOUBLE_OPS: 1722 case GK_CAYMAN: 1723 DescriptionString = DescriptionStringR600DoubleOps; 1724 break; 1725 case GK_SOUTHERN_ISLANDS: 1726 case GK_SEA_ISLANDS: 1727 DescriptionString = DescriptionStringSI; 1728 break; 1729 } 1730 1731 return true; 1732 } 1733 }; 1734 1735 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1736 #define BUILTIN(ID, TYPE, ATTRS) \ 1737 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1738 #include "clang/Basic/BuiltinsR600.def" 1739 }; 1740 1741 } // end anonymous namespace 1742 1743 namespace { 1744 // Namespace for x86 abstract base class 1745 const Builtin::Info BuiltinInfo[] = { 1746 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1747 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1748 ALL_LANGUAGES }, 1749 #include "clang/Basic/BuiltinsX86.def" 1750 }; 1751 1752 static const char* const GCCRegNames[] = { 1753 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1754 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1755 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1756 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1757 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1758 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1759 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1760 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1761 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1762 }; 1763 1764 const TargetInfo::AddlRegName AddlRegNames[] = { 1765 { { "al", "ah", "eax", "rax" }, 0 }, 1766 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1767 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1768 { { "dl", "dh", "edx", "rdx" }, 1 }, 1769 { { "esi", "rsi" }, 4 }, 1770 { { "edi", "rdi" }, 5 }, 1771 { { "esp", "rsp" }, 7 }, 1772 { { "ebp", "rbp" }, 6 }, 1773 }; 1774 1775 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1776 // most of the implementation can be shared. 1777 class X86TargetInfo : public TargetInfo { 1778 enum X86SSEEnum { 1779 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1780 } SSELevel; 1781 enum MMX3DNowEnum { 1782 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1783 } MMX3DNowLevel; 1784 enum XOPEnum { 1785 NoXOP, 1786 SSE4A, 1787 FMA4, 1788 XOP 1789 } XOPLevel; 1790 1791 bool HasAES; 1792 bool HasPCLMUL; 1793 bool HasLZCNT; 1794 bool HasRDRND; 1795 bool HasFSGSBASE; 1796 bool HasBMI; 1797 bool HasBMI2; 1798 bool HasPOPCNT; 1799 bool HasRTM; 1800 bool HasPRFCHW; 1801 bool HasRDSEED; 1802 bool HasADX; 1803 bool HasTBM; 1804 bool HasFMA; 1805 bool HasF16C; 1806 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1807 HasAVX512VL; 1808 bool HasSHA; 1809 bool HasCX16; 1810 1811 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1812 /// 1813 /// Each enumeration represents a particular CPU supported by Clang. These 1814 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1815 enum CPUKind { 1816 CK_Generic, 1817 1818 /// \name i386 1819 /// i386-generation processors. 1820 //@{ 1821 CK_i386, 1822 //@} 1823 1824 /// \name i486 1825 /// i486-generation processors. 1826 //@{ 1827 CK_i486, 1828 CK_WinChipC6, 1829 CK_WinChip2, 1830 CK_C3, 1831 //@} 1832 1833 /// \name i586 1834 /// i586-generation processors, P5 microarchitecture based. 1835 //@{ 1836 CK_i586, 1837 CK_Pentium, 1838 CK_PentiumMMX, 1839 //@} 1840 1841 /// \name i686 1842 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1843 //@{ 1844 CK_i686, 1845 CK_PentiumPro, 1846 CK_Pentium2, 1847 CK_Pentium3, 1848 CK_Pentium3M, 1849 CK_PentiumM, 1850 CK_C3_2, 1851 1852 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1853 /// Clang however has some logic to suport this. 1854 // FIXME: Warn, deprecate, and potentially remove this. 1855 CK_Yonah, 1856 //@} 1857 1858 /// \name Netburst 1859 /// Netburst microarchitecture based processors. 1860 //@{ 1861 CK_Pentium4, 1862 CK_Pentium4M, 1863 CK_Prescott, 1864 CK_Nocona, 1865 //@} 1866 1867 /// \name Core 1868 /// Core microarchitecture based processors. 1869 //@{ 1870 CK_Core2, 1871 1872 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1873 /// codename which GCC no longer accepts as an option to -march, but Clang 1874 /// has some logic for recognizing it. 1875 // FIXME: Warn, deprecate, and potentially remove this. 1876 CK_Penryn, 1877 //@} 1878 1879 /// \name Atom 1880 /// Atom processors 1881 //@{ 1882 CK_Bonnell, 1883 CK_Silvermont, 1884 //@} 1885 1886 /// \name Nehalem 1887 /// Nehalem microarchitecture based processors. 1888 CK_Nehalem, 1889 1890 /// \name Westmere 1891 /// Westmere microarchitecture based processors. 1892 CK_Westmere, 1893 1894 /// \name Sandy Bridge 1895 /// Sandy Bridge microarchitecture based processors. 1896 CK_SandyBridge, 1897 1898 /// \name Ivy Bridge 1899 /// Ivy Bridge microarchitecture based processors. 1900 CK_IvyBridge, 1901 1902 /// \name Haswell 1903 /// Haswell microarchitecture based processors. 1904 CK_Haswell, 1905 1906 /// \name Broadwell 1907 /// Broadwell microarchitecture based processors. 1908 CK_Broadwell, 1909 1910 /// \name Skylake 1911 /// Skylake microarchitecture based processors. 1912 CK_Skylake, 1913 1914 /// \name Knights Landing 1915 /// Knights Landing processor. 1916 CK_KNL, 1917 1918 /// \name K6 1919 /// K6 architecture processors. 1920 //@{ 1921 CK_K6, 1922 CK_K6_2, 1923 CK_K6_3, 1924 //@} 1925 1926 /// \name K7 1927 /// K7 architecture processors. 1928 //@{ 1929 CK_Athlon, 1930 CK_AthlonThunderbird, 1931 CK_Athlon4, 1932 CK_AthlonXP, 1933 CK_AthlonMP, 1934 //@} 1935 1936 /// \name K8 1937 /// K8 architecture processors. 1938 //@{ 1939 CK_Athlon64, 1940 CK_Athlon64SSE3, 1941 CK_AthlonFX, 1942 CK_K8, 1943 CK_K8SSE3, 1944 CK_Opteron, 1945 CK_OpteronSSE3, 1946 CK_AMDFAM10, 1947 //@} 1948 1949 /// \name Bobcat 1950 /// Bobcat architecture processors. 1951 //@{ 1952 CK_BTVER1, 1953 CK_BTVER2, 1954 //@} 1955 1956 /// \name Bulldozer 1957 /// Bulldozer architecture processors. 1958 //@{ 1959 CK_BDVER1, 1960 CK_BDVER2, 1961 CK_BDVER3, 1962 CK_BDVER4, 1963 //@} 1964 1965 /// This specification is deprecated and will be removed in the future. 1966 /// Users should prefer \see CK_K8. 1967 // FIXME: Warn on this when the CPU is set to it. 1968 //@{ 1969 CK_x86_64, 1970 //@} 1971 1972 /// \name Geode 1973 /// Geode processors. 1974 //@{ 1975 CK_Geode 1976 //@} 1977 } CPU; 1978 1979 enum FPMathKind { 1980 FP_Default, 1981 FP_SSE, 1982 FP_387 1983 } FPMath; 1984 1985 public: 1986 X86TargetInfo(const llvm::Triple &Triple) 1987 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1988 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1989 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 1990 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 1991 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 1992 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 1993 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 1994 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 1995 BigEndian = false; 1996 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1997 } 1998 unsigned getFloatEvalMethod() const override { 1999 // X87 evaluates with 80 bits "long double" precision. 2000 return SSELevel == NoSSE ? 2 : 0; 2001 } 2002 void getTargetBuiltins(const Builtin::Info *&Records, 2003 unsigned &NumRecords) const override { 2004 Records = BuiltinInfo; 2005 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2006 } 2007 void getGCCRegNames(const char * const *&Names, 2008 unsigned &NumNames) const override { 2009 Names = GCCRegNames; 2010 NumNames = llvm::array_lengthof(GCCRegNames); 2011 } 2012 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2013 unsigned &NumAliases) const override { 2014 Aliases = nullptr; 2015 NumAliases = 0; 2016 } 2017 void getGCCAddlRegNames(const AddlRegName *&Names, 2018 unsigned &NumNames) const override { 2019 Names = AddlRegNames; 2020 NumNames = llvm::array_lengthof(AddlRegNames); 2021 } 2022 bool validateAsmConstraint(const char *&Name, 2023 TargetInfo::ConstraintInfo &info) const override; 2024 2025 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2026 2027 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2028 2029 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2030 2031 std::string convertConstraint(const char *&Constraint) const override; 2032 const char *getClobbers() const override { 2033 return "~{dirflag},~{fpsr},~{flags}"; 2034 } 2035 void getTargetDefines(const LangOptions &Opts, 2036 MacroBuilder &Builder) const override; 2037 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2038 bool Enabled); 2039 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2040 bool Enabled); 2041 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2042 bool Enabled); 2043 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2044 StringRef Name, bool Enabled) const override { 2045 setFeatureEnabledImpl(Features, Name, Enabled); 2046 } 2047 // This exists purely to cut down on the number of virtual calls in 2048 // getDefaultFeatures which calls this repeatedly. 2049 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2050 StringRef Name, bool Enabled); 2051 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2052 bool hasFeature(StringRef Feature) const override; 2053 bool handleTargetFeatures(std::vector<std::string> &Features, 2054 DiagnosticsEngine &Diags) override; 2055 StringRef getABI() const override { 2056 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2057 return "avx"; 2058 else if (getTriple().getArch() == llvm::Triple::x86 && 2059 MMX3DNowLevel == NoMMX3DNow) 2060 return "no-mmx"; 2061 return ""; 2062 } 2063 bool setCPU(const std::string &Name) override { 2064 CPU = llvm::StringSwitch<CPUKind>(Name) 2065 .Case("i386", CK_i386) 2066 .Case("i486", CK_i486) 2067 .Case("winchip-c6", CK_WinChipC6) 2068 .Case("winchip2", CK_WinChip2) 2069 .Case("c3", CK_C3) 2070 .Case("i586", CK_i586) 2071 .Case("pentium", CK_Pentium) 2072 .Case("pentium-mmx", CK_PentiumMMX) 2073 .Case("i686", CK_i686) 2074 .Case("pentiumpro", CK_PentiumPro) 2075 .Case("pentium2", CK_Pentium2) 2076 .Case("pentium3", CK_Pentium3) 2077 .Case("pentium3m", CK_Pentium3M) 2078 .Case("pentium-m", CK_PentiumM) 2079 .Case("c3-2", CK_C3_2) 2080 .Case("yonah", CK_Yonah) 2081 .Case("pentium4", CK_Pentium4) 2082 .Case("pentium4m", CK_Pentium4M) 2083 .Case("prescott", CK_Prescott) 2084 .Case("nocona", CK_Nocona) 2085 .Case("core2", CK_Core2) 2086 .Case("penryn", CK_Penryn) 2087 .Case("bonnell", CK_Bonnell) 2088 .Case("atom", CK_Bonnell) // Legacy name. 2089 .Case("silvermont", CK_Silvermont) 2090 .Case("slm", CK_Silvermont) // Legacy name. 2091 .Case("nehalem", CK_Nehalem) 2092 .Case("corei7", CK_Nehalem) // Legacy name. 2093 .Case("westmere", CK_Westmere) 2094 .Case("sandybridge", CK_SandyBridge) 2095 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2096 .Case("ivybridge", CK_IvyBridge) 2097 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2098 .Case("haswell", CK_Haswell) 2099 .Case("core-avx2", CK_Haswell) // Legacy name. 2100 .Case("broadwell", CK_Broadwell) 2101 .Case("skylake", CK_Skylake) 2102 .Case("skx", CK_Skylake) // Legacy name. 2103 .Case("knl", CK_KNL) 2104 .Case("k6", CK_K6) 2105 .Case("k6-2", CK_K6_2) 2106 .Case("k6-3", CK_K6_3) 2107 .Case("athlon", CK_Athlon) 2108 .Case("athlon-tbird", CK_AthlonThunderbird) 2109 .Case("athlon-4", CK_Athlon4) 2110 .Case("athlon-xp", CK_AthlonXP) 2111 .Case("athlon-mp", CK_AthlonMP) 2112 .Case("athlon64", CK_Athlon64) 2113 .Case("athlon64-sse3", CK_Athlon64SSE3) 2114 .Case("athlon-fx", CK_AthlonFX) 2115 .Case("k8", CK_K8) 2116 .Case("k8-sse3", CK_K8SSE3) 2117 .Case("opteron", CK_Opteron) 2118 .Case("opteron-sse3", CK_OpteronSSE3) 2119 .Case("barcelona", CK_AMDFAM10) 2120 .Case("amdfam10", CK_AMDFAM10) 2121 .Case("btver1", CK_BTVER1) 2122 .Case("btver2", CK_BTVER2) 2123 .Case("bdver1", CK_BDVER1) 2124 .Case("bdver2", CK_BDVER2) 2125 .Case("bdver3", CK_BDVER3) 2126 .Case("bdver4", CK_BDVER4) 2127 .Case("x86-64", CK_x86_64) 2128 .Case("geode", CK_Geode) 2129 .Default(CK_Generic); 2130 2131 // Perform any per-CPU checks necessary to determine if this CPU is 2132 // acceptable. 2133 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2134 // invalid without explaining *why*. 2135 switch (CPU) { 2136 case CK_Generic: 2137 // No processor selected! 2138 return false; 2139 2140 case CK_i386: 2141 case CK_i486: 2142 case CK_WinChipC6: 2143 case CK_WinChip2: 2144 case CK_C3: 2145 case CK_i586: 2146 case CK_Pentium: 2147 case CK_PentiumMMX: 2148 case CK_i686: 2149 case CK_PentiumPro: 2150 case CK_Pentium2: 2151 case CK_Pentium3: 2152 case CK_Pentium3M: 2153 case CK_PentiumM: 2154 case CK_Yonah: 2155 case CK_C3_2: 2156 case CK_Pentium4: 2157 case CK_Pentium4M: 2158 case CK_Prescott: 2159 case CK_K6: 2160 case CK_K6_2: 2161 case CK_K6_3: 2162 case CK_Athlon: 2163 case CK_AthlonThunderbird: 2164 case CK_Athlon4: 2165 case CK_AthlonXP: 2166 case CK_AthlonMP: 2167 case CK_Geode: 2168 // Only accept certain architectures when compiling in 32-bit mode. 2169 if (getTriple().getArch() != llvm::Triple::x86) 2170 return false; 2171 2172 // Fallthrough 2173 case CK_Nocona: 2174 case CK_Core2: 2175 case CK_Penryn: 2176 case CK_Bonnell: 2177 case CK_Silvermont: 2178 case CK_Nehalem: 2179 case CK_Westmere: 2180 case CK_SandyBridge: 2181 case CK_IvyBridge: 2182 case CK_Haswell: 2183 case CK_Broadwell: 2184 case CK_Skylake: 2185 case CK_KNL: 2186 case CK_Athlon64: 2187 case CK_Athlon64SSE3: 2188 case CK_AthlonFX: 2189 case CK_K8: 2190 case CK_K8SSE3: 2191 case CK_Opteron: 2192 case CK_OpteronSSE3: 2193 case CK_AMDFAM10: 2194 case CK_BTVER1: 2195 case CK_BTVER2: 2196 case CK_BDVER1: 2197 case CK_BDVER2: 2198 case CK_BDVER3: 2199 case CK_BDVER4: 2200 case CK_x86_64: 2201 return true; 2202 } 2203 llvm_unreachable("Unhandled CPU kind"); 2204 } 2205 2206 bool setFPMath(StringRef Name) override; 2207 2208 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2209 // We accept all non-ARM calling conventions 2210 return (CC == CC_X86ThisCall || 2211 CC == CC_X86FastCall || 2212 CC == CC_X86StdCall || 2213 CC == CC_X86VectorCall || 2214 CC == CC_C || 2215 CC == CC_X86Pascal || 2216 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2217 } 2218 2219 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2220 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2221 } 2222 }; 2223 2224 bool X86TargetInfo::setFPMath(StringRef Name) { 2225 if (Name == "387") { 2226 FPMath = FP_387; 2227 return true; 2228 } 2229 if (Name == "sse") { 2230 FPMath = FP_SSE; 2231 return true; 2232 } 2233 return false; 2234 } 2235 2236 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2237 // FIXME: This *really* should not be here. 2238 2239 // X86_64 always has SSE2. 2240 if (getTriple().getArch() == llvm::Triple::x86_64) 2241 setFeatureEnabledImpl(Features, "sse2", true); 2242 2243 switch (CPU) { 2244 case CK_Generic: 2245 case CK_i386: 2246 case CK_i486: 2247 case CK_i586: 2248 case CK_Pentium: 2249 case CK_i686: 2250 case CK_PentiumPro: 2251 break; 2252 case CK_PentiumMMX: 2253 case CK_Pentium2: 2254 case CK_K6: 2255 case CK_WinChipC6: 2256 setFeatureEnabledImpl(Features, "mmx", true); 2257 break; 2258 case CK_Pentium3: 2259 case CK_Pentium3M: 2260 case CK_C3_2: 2261 setFeatureEnabledImpl(Features, "sse", true); 2262 break; 2263 case CK_PentiumM: 2264 case CK_Pentium4: 2265 case CK_Pentium4M: 2266 case CK_x86_64: 2267 setFeatureEnabledImpl(Features, "sse2", true); 2268 break; 2269 case CK_Yonah: 2270 case CK_Prescott: 2271 case CK_Nocona: 2272 setFeatureEnabledImpl(Features, "sse3", true); 2273 setFeatureEnabledImpl(Features, "cx16", true); 2274 break; 2275 case CK_Core2: 2276 case CK_Bonnell: 2277 setFeatureEnabledImpl(Features, "ssse3", true); 2278 setFeatureEnabledImpl(Features, "cx16", true); 2279 break; 2280 case CK_Penryn: 2281 setFeatureEnabledImpl(Features, "sse4.1", true); 2282 setFeatureEnabledImpl(Features, "cx16", true); 2283 break; 2284 case CK_Skylake: 2285 setFeatureEnabledImpl(Features, "avx512f", true); 2286 setFeatureEnabledImpl(Features, "avx512cd", true); 2287 setFeatureEnabledImpl(Features, "avx512dq", true); 2288 setFeatureEnabledImpl(Features, "avx512bw", true); 2289 setFeatureEnabledImpl(Features, "avx512vl", true); 2290 // FALLTHROUGH 2291 case CK_Broadwell: 2292 setFeatureEnabledImpl(Features, "rdseed", true); 2293 setFeatureEnabledImpl(Features, "adx", true); 2294 // FALLTHROUGH 2295 case CK_Haswell: 2296 setFeatureEnabledImpl(Features, "avx2", true); 2297 setFeatureEnabledImpl(Features, "lzcnt", true); 2298 setFeatureEnabledImpl(Features, "bmi", true); 2299 setFeatureEnabledImpl(Features, "bmi2", true); 2300 setFeatureEnabledImpl(Features, "rtm", true); 2301 setFeatureEnabledImpl(Features, "fma", true); 2302 // FALLTHROUGH 2303 case CK_IvyBridge: 2304 setFeatureEnabledImpl(Features, "rdrnd", true); 2305 setFeatureEnabledImpl(Features, "f16c", true); 2306 setFeatureEnabledImpl(Features, "fsgsbase", true); 2307 // FALLTHROUGH 2308 case CK_SandyBridge: 2309 setFeatureEnabledImpl(Features, "avx", true); 2310 // FALLTHROUGH 2311 case CK_Westmere: 2312 case CK_Silvermont: 2313 setFeatureEnabledImpl(Features, "aes", true); 2314 setFeatureEnabledImpl(Features, "pclmul", true); 2315 // FALLTHROUGH 2316 case CK_Nehalem: 2317 setFeatureEnabledImpl(Features, "sse4.2", true); 2318 setFeatureEnabledImpl(Features, "cx16", true); 2319 break; 2320 case CK_KNL: 2321 setFeatureEnabledImpl(Features, "avx512f", true); 2322 setFeatureEnabledImpl(Features, "avx512cd", true); 2323 setFeatureEnabledImpl(Features, "avx512er", true); 2324 setFeatureEnabledImpl(Features, "avx512pf", true); 2325 setFeatureEnabledImpl(Features, "rdseed", true); 2326 setFeatureEnabledImpl(Features, "adx", true); 2327 setFeatureEnabledImpl(Features, "lzcnt", true); 2328 setFeatureEnabledImpl(Features, "bmi", true); 2329 setFeatureEnabledImpl(Features, "bmi2", true); 2330 setFeatureEnabledImpl(Features, "rtm", true); 2331 setFeatureEnabledImpl(Features, "fma", true); 2332 setFeatureEnabledImpl(Features, "rdrnd", true); 2333 setFeatureEnabledImpl(Features, "f16c", true); 2334 setFeatureEnabledImpl(Features, "fsgsbase", true); 2335 setFeatureEnabledImpl(Features, "aes", true); 2336 setFeatureEnabledImpl(Features, "pclmul", true); 2337 setFeatureEnabledImpl(Features, "cx16", true); 2338 break; 2339 case CK_K6_2: 2340 case CK_K6_3: 2341 case CK_WinChip2: 2342 case CK_C3: 2343 setFeatureEnabledImpl(Features, "3dnow", true); 2344 break; 2345 case CK_Athlon: 2346 case CK_AthlonThunderbird: 2347 case CK_Geode: 2348 setFeatureEnabledImpl(Features, "3dnowa", true); 2349 break; 2350 case CK_Athlon4: 2351 case CK_AthlonXP: 2352 case CK_AthlonMP: 2353 setFeatureEnabledImpl(Features, "sse", true); 2354 setFeatureEnabledImpl(Features, "3dnowa", true); 2355 break; 2356 case CK_K8: 2357 case CK_Opteron: 2358 case CK_Athlon64: 2359 case CK_AthlonFX: 2360 setFeatureEnabledImpl(Features, "sse2", true); 2361 setFeatureEnabledImpl(Features, "3dnowa", true); 2362 break; 2363 case CK_AMDFAM10: 2364 setFeatureEnabledImpl(Features, "sse4a", true); 2365 setFeatureEnabledImpl(Features, "lzcnt", true); 2366 setFeatureEnabledImpl(Features, "popcnt", true); 2367 // FALLTHROUGH 2368 case CK_K8SSE3: 2369 case CK_OpteronSSE3: 2370 case CK_Athlon64SSE3: 2371 setFeatureEnabledImpl(Features, "sse3", true); 2372 setFeatureEnabledImpl(Features, "3dnowa", true); 2373 break; 2374 case CK_BTVER2: 2375 setFeatureEnabledImpl(Features, "avx", true); 2376 setFeatureEnabledImpl(Features, "aes", true); 2377 setFeatureEnabledImpl(Features, "pclmul", true); 2378 setFeatureEnabledImpl(Features, "bmi", true); 2379 setFeatureEnabledImpl(Features, "f16c", true); 2380 // FALLTHROUGH 2381 case CK_BTVER1: 2382 setFeatureEnabledImpl(Features, "ssse3", true); 2383 setFeatureEnabledImpl(Features, "sse4a", true); 2384 setFeatureEnabledImpl(Features, "lzcnt", true); 2385 setFeatureEnabledImpl(Features, "popcnt", true); 2386 setFeatureEnabledImpl(Features, "prfchw", true); 2387 setFeatureEnabledImpl(Features, "cx16", true); 2388 break; 2389 case CK_BDVER4: 2390 setFeatureEnabledImpl(Features, "avx2", true); 2391 setFeatureEnabledImpl(Features, "bmi2", true); 2392 // FALLTHROUGH 2393 case CK_BDVER3: 2394 setFeatureEnabledImpl(Features, "fsgsbase", true); 2395 // FALLTHROUGH 2396 case CK_BDVER2: 2397 setFeatureEnabledImpl(Features, "bmi", true); 2398 setFeatureEnabledImpl(Features, "fma", true); 2399 setFeatureEnabledImpl(Features, "f16c", true); 2400 setFeatureEnabledImpl(Features, "tbm", true); 2401 // FALLTHROUGH 2402 case CK_BDVER1: 2403 // xop implies avx, sse4a and fma4. 2404 setFeatureEnabledImpl(Features, "xop", true); 2405 setFeatureEnabledImpl(Features, "lzcnt", true); 2406 setFeatureEnabledImpl(Features, "aes", true); 2407 setFeatureEnabledImpl(Features, "pclmul", true); 2408 setFeatureEnabledImpl(Features, "prfchw", true); 2409 setFeatureEnabledImpl(Features, "cx16", true); 2410 break; 2411 } 2412 } 2413 2414 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2415 X86SSEEnum Level, bool Enabled) { 2416 if (Enabled) { 2417 switch (Level) { 2418 case AVX512F: 2419 Features["avx512f"] = true; 2420 case AVX2: 2421 Features["avx2"] = true; 2422 case AVX: 2423 Features["avx"] = true; 2424 case SSE42: 2425 Features["sse4.2"] = true; 2426 case SSE41: 2427 Features["sse4.1"] = true; 2428 case SSSE3: 2429 Features["ssse3"] = true; 2430 case SSE3: 2431 Features["sse3"] = true; 2432 case SSE2: 2433 Features["sse2"] = true; 2434 case SSE1: 2435 Features["sse"] = true; 2436 case NoSSE: 2437 break; 2438 } 2439 return; 2440 } 2441 2442 switch (Level) { 2443 case NoSSE: 2444 case SSE1: 2445 Features["sse"] = false; 2446 case SSE2: 2447 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2448 Features["sha"] = false; 2449 case SSE3: 2450 Features["sse3"] = false; 2451 setXOPLevel(Features, NoXOP, false); 2452 case SSSE3: 2453 Features["ssse3"] = false; 2454 case SSE41: 2455 Features["sse4.1"] = false; 2456 case SSE42: 2457 Features["sse4.2"] = false; 2458 case AVX: 2459 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2460 setXOPLevel(Features, FMA4, false); 2461 case AVX2: 2462 Features["avx2"] = false; 2463 case AVX512F: 2464 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2465 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2466 Features["avx512vl"] = false; 2467 } 2468 } 2469 2470 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2471 MMX3DNowEnum Level, bool Enabled) { 2472 if (Enabled) { 2473 switch (Level) { 2474 case AMD3DNowAthlon: 2475 Features["3dnowa"] = true; 2476 case AMD3DNow: 2477 Features["3dnow"] = true; 2478 case MMX: 2479 Features["mmx"] = true; 2480 case NoMMX3DNow: 2481 break; 2482 } 2483 return; 2484 } 2485 2486 switch (Level) { 2487 case NoMMX3DNow: 2488 case MMX: 2489 Features["mmx"] = false; 2490 case AMD3DNow: 2491 Features["3dnow"] = false; 2492 case AMD3DNowAthlon: 2493 Features["3dnowa"] = false; 2494 } 2495 } 2496 2497 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2498 bool Enabled) { 2499 if (Enabled) { 2500 switch (Level) { 2501 case XOP: 2502 Features["xop"] = true; 2503 case FMA4: 2504 Features["fma4"] = true; 2505 setSSELevel(Features, AVX, true); 2506 case SSE4A: 2507 Features["sse4a"] = true; 2508 setSSELevel(Features, SSE3, true); 2509 case NoXOP: 2510 break; 2511 } 2512 return; 2513 } 2514 2515 switch (Level) { 2516 case NoXOP: 2517 case SSE4A: 2518 Features["sse4a"] = false; 2519 case FMA4: 2520 Features["fma4"] = false; 2521 case XOP: 2522 Features["xop"] = false; 2523 } 2524 } 2525 2526 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2527 StringRef Name, bool Enabled) { 2528 // FIXME: This *really* should not be here. We need some way of translating 2529 // options into llvm subtarget features. 2530 if (Name == "sse4") 2531 Name = "sse4.2"; 2532 2533 Features[Name] = Enabled; 2534 2535 if (Name == "mmx") { 2536 setMMXLevel(Features, MMX, Enabled); 2537 } else if (Name == "sse") { 2538 setSSELevel(Features, SSE1, Enabled); 2539 } else if (Name == "sse2") { 2540 setSSELevel(Features, SSE2, Enabled); 2541 } else if (Name == "sse3") { 2542 setSSELevel(Features, SSE3, Enabled); 2543 } else if (Name == "ssse3") { 2544 setSSELevel(Features, SSSE3, Enabled); 2545 } else if (Name == "sse4.2") { 2546 setSSELevel(Features, SSE42, Enabled); 2547 } else if (Name == "sse4.1") { 2548 setSSELevel(Features, SSE41, Enabled); 2549 } else if (Name == "3dnow") { 2550 setMMXLevel(Features, AMD3DNow, Enabled); 2551 } else if (Name == "3dnowa") { 2552 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2553 } else if (Name == "aes") { 2554 if (Enabled) 2555 setSSELevel(Features, SSE2, Enabled); 2556 } else if (Name == "pclmul") { 2557 if (Enabled) 2558 setSSELevel(Features, SSE2, Enabled); 2559 } else if (Name == "avx") { 2560 setSSELevel(Features, AVX, Enabled); 2561 } else if (Name == "avx2") { 2562 setSSELevel(Features, AVX2, Enabled); 2563 } else if (Name == "avx512f") { 2564 setSSELevel(Features, AVX512F, Enabled); 2565 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2566 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2567 if (Enabled) 2568 setSSELevel(Features, AVX512F, Enabled); 2569 } else if (Name == "fma") { 2570 if (Enabled) 2571 setSSELevel(Features, AVX, Enabled); 2572 } else if (Name == "fma4") { 2573 setXOPLevel(Features, FMA4, Enabled); 2574 } else if (Name == "xop") { 2575 setXOPLevel(Features, XOP, Enabled); 2576 } else if (Name == "sse4a") { 2577 setXOPLevel(Features, SSE4A, Enabled); 2578 } else if (Name == "f16c") { 2579 if (Enabled) 2580 setSSELevel(Features, AVX, Enabled); 2581 } else if (Name == "sha") { 2582 if (Enabled) 2583 setSSELevel(Features, SSE2, Enabled); 2584 } 2585 } 2586 2587 /// handleTargetFeatures - Perform initialization based on the user 2588 /// configured set of features. 2589 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2590 DiagnosticsEngine &Diags) { 2591 // Remember the maximum enabled sselevel. 2592 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2593 // Ignore disabled features. 2594 if (Features[i][0] == '-') 2595 continue; 2596 2597 StringRef Feature = StringRef(Features[i]).substr(1); 2598 2599 if (Feature == "aes") { 2600 HasAES = true; 2601 continue; 2602 } 2603 2604 if (Feature == "pclmul") { 2605 HasPCLMUL = true; 2606 continue; 2607 } 2608 2609 if (Feature == "lzcnt") { 2610 HasLZCNT = true; 2611 continue; 2612 } 2613 2614 if (Feature == "rdrnd") { 2615 HasRDRND = true; 2616 continue; 2617 } 2618 2619 if (Feature == "fsgsbase") { 2620 HasFSGSBASE = true; 2621 continue; 2622 } 2623 2624 if (Feature == "bmi") { 2625 HasBMI = true; 2626 continue; 2627 } 2628 2629 if (Feature == "bmi2") { 2630 HasBMI2 = true; 2631 continue; 2632 } 2633 2634 if (Feature == "popcnt") { 2635 HasPOPCNT = true; 2636 continue; 2637 } 2638 2639 if (Feature == "rtm") { 2640 HasRTM = true; 2641 continue; 2642 } 2643 2644 if (Feature == "prfchw") { 2645 HasPRFCHW = true; 2646 continue; 2647 } 2648 2649 if (Feature == "rdseed") { 2650 HasRDSEED = true; 2651 continue; 2652 } 2653 2654 if (Feature == "adx") { 2655 HasADX = true; 2656 continue; 2657 } 2658 2659 if (Feature == "tbm") { 2660 HasTBM = true; 2661 continue; 2662 } 2663 2664 if (Feature == "fma") { 2665 HasFMA = true; 2666 continue; 2667 } 2668 2669 if (Feature == "f16c") { 2670 HasF16C = true; 2671 continue; 2672 } 2673 2674 if (Feature == "avx512cd") { 2675 HasAVX512CD = true; 2676 continue; 2677 } 2678 2679 if (Feature == "avx512er") { 2680 HasAVX512ER = true; 2681 continue; 2682 } 2683 2684 if (Feature == "avx512pf") { 2685 HasAVX512PF = true; 2686 continue; 2687 } 2688 2689 if (Feature == "avx512dq") { 2690 HasAVX512DQ = true; 2691 continue; 2692 } 2693 2694 if (Feature == "avx512bw") { 2695 HasAVX512BW = true; 2696 continue; 2697 } 2698 2699 if (Feature == "avx512vl") { 2700 HasAVX512VL = true; 2701 continue; 2702 } 2703 2704 if (Feature == "sha") { 2705 HasSHA = true; 2706 continue; 2707 } 2708 2709 if (Feature == "cx16") { 2710 HasCX16 = true; 2711 continue; 2712 } 2713 2714 assert(Features[i][0] == '+' && "Invalid target feature!"); 2715 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2716 .Case("avx512f", AVX512F) 2717 .Case("avx2", AVX2) 2718 .Case("avx", AVX) 2719 .Case("sse4.2", SSE42) 2720 .Case("sse4.1", SSE41) 2721 .Case("ssse3", SSSE3) 2722 .Case("sse3", SSE3) 2723 .Case("sse2", SSE2) 2724 .Case("sse", SSE1) 2725 .Default(NoSSE); 2726 SSELevel = std::max(SSELevel, Level); 2727 2728 MMX3DNowEnum ThreeDNowLevel = 2729 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2730 .Case("3dnowa", AMD3DNowAthlon) 2731 .Case("3dnow", AMD3DNow) 2732 .Case("mmx", MMX) 2733 .Default(NoMMX3DNow); 2734 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2735 2736 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2737 .Case("xop", XOP) 2738 .Case("fma4", FMA4) 2739 .Case("sse4a", SSE4A) 2740 .Default(NoXOP); 2741 XOPLevel = std::max(XOPLevel, XLevel); 2742 } 2743 2744 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2745 // Can't do this earlier because we need to be able to explicitly enable 2746 // popcnt and still disable sse4.2. 2747 if (!HasPOPCNT && SSELevel >= SSE42 && 2748 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2749 HasPOPCNT = true; 2750 Features.push_back("+popcnt"); 2751 } 2752 2753 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2754 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2755 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2756 HasPRFCHW = true; 2757 Features.push_back("+prfchw"); 2758 } 2759 2760 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2761 // matches the selected sse level. 2762 if (FPMath == FP_SSE && SSELevel < SSE1) { 2763 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2764 return false; 2765 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2766 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2767 return false; 2768 } 2769 2770 // Don't tell the backend if we're turning off mmx; it will end up disabling 2771 // SSE, which we don't want. 2772 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2773 // then enable MMX. 2774 std::vector<std::string>::iterator it; 2775 it = std::find(Features.begin(), Features.end(), "-mmx"); 2776 if (it != Features.end()) 2777 Features.erase(it); 2778 else if (SSELevel > NoSSE) 2779 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2780 return true; 2781 } 2782 2783 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2784 /// definitions for this particular subtarget. 2785 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2786 MacroBuilder &Builder) const { 2787 // Target identification. 2788 if (getTriple().getArch() == llvm::Triple::x86_64) { 2789 Builder.defineMacro("__amd64__"); 2790 Builder.defineMacro("__amd64"); 2791 Builder.defineMacro("__x86_64"); 2792 Builder.defineMacro("__x86_64__"); 2793 if (getTriple().getArchName() == "x86_64h") { 2794 Builder.defineMacro("__x86_64h"); 2795 Builder.defineMacro("__x86_64h__"); 2796 } 2797 } else { 2798 DefineStd(Builder, "i386", Opts); 2799 } 2800 2801 // Subtarget options. 2802 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2803 // truly should be based on -mtune options. 2804 switch (CPU) { 2805 case CK_Generic: 2806 break; 2807 case CK_i386: 2808 // The rest are coming from the i386 define above. 2809 Builder.defineMacro("__tune_i386__"); 2810 break; 2811 case CK_i486: 2812 case CK_WinChipC6: 2813 case CK_WinChip2: 2814 case CK_C3: 2815 defineCPUMacros(Builder, "i486"); 2816 break; 2817 case CK_PentiumMMX: 2818 Builder.defineMacro("__pentium_mmx__"); 2819 Builder.defineMacro("__tune_pentium_mmx__"); 2820 // Fallthrough 2821 case CK_i586: 2822 case CK_Pentium: 2823 defineCPUMacros(Builder, "i586"); 2824 defineCPUMacros(Builder, "pentium"); 2825 break; 2826 case CK_Pentium3: 2827 case CK_Pentium3M: 2828 case CK_PentiumM: 2829 Builder.defineMacro("__tune_pentium3__"); 2830 // Fallthrough 2831 case CK_Pentium2: 2832 case CK_C3_2: 2833 Builder.defineMacro("__tune_pentium2__"); 2834 // Fallthrough 2835 case CK_PentiumPro: 2836 Builder.defineMacro("__tune_i686__"); 2837 Builder.defineMacro("__tune_pentiumpro__"); 2838 // Fallthrough 2839 case CK_i686: 2840 Builder.defineMacro("__i686"); 2841 Builder.defineMacro("__i686__"); 2842 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2843 Builder.defineMacro("__pentiumpro"); 2844 Builder.defineMacro("__pentiumpro__"); 2845 break; 2846 case CK_Pentium4: 2847 case CK_Pentium4M: 2848 defineCPUMacros(Builder, "pentium4"); 2849 break; 2850 case CK_Yonah: 2851 case CK_Prescott: 2852 case CK_Nocona: 2853 defineCPUMacros(Builder, "nocona"); 2854 break; 2855 case CK_Core2: 2856 case CK_Penryn: 2857 defineCPUMacros(Builder, "core2"); 2858 break; 2859 case CK_Bonnell: 2860 defineCPUMacros(Builder, "atom"); 2861 break; 2862 case CK_Silvermont: 2863 defineCPUMacros(Builder, "slm"); 2864 break; 2865 case CK_Nehalem: 2866 case CK_Westmere: 2867 case CK_SandyBridge: 2868 case CK_IvyBridge: 2869 case CK_Haswell: 2870 case CK_Broadwell: 2871 // FIXME: Historically, we defined this legacy name, it would be nice to 2872 // remove it at some point. We've never exposed fine-grained names for 2873 // recent primary x86 CPUs, and we should keep it that way. 2874 defineCPUMacros(Builder, "corei7"); 2875 break; 2876 case CK_Skylake: 2877 // FIXME: Historically, we defined this legacy name, it would be nice to 2878 // remove it at some point. This is the only fine-grained CPU macro in the 2879 // main intel CPU line, and it would be better to not have these and force 2880 // people to use ISA macros. 2881 defineCPUMacros(Builder, "skx"); 2882 break; 2883 case CK_KNL: 2884 defineCPUMacros(Builder, "knl"); 2885 break; 2886 case CK_K6_2: 2887 Builder.defineMacro("__k6_2__"); 2888 Builder.defineMacro("__tune_k6_2__"); 2889 // Fallthrough 2890 case CK_K6_3: 2891 if (CPU != CK_K6_2) { // In case of fallthrough 2892 // FIXME: GCC may be enabling these in cases where some other k6 2893 // architecture is specified but -m3dnow is explicitly provided. The 2894 // exact semantics need to be determined and emulated here. 2895 Builder.defineMacro("__k6_3__"); 2896 Builder.defineMacro("__tune_k6_3__"); 2897 } 2898 // Fallthrough 2899 case CK_K6: 2900 defineCPUMacros(Builder, "k6"); 2901 break; 2902 case CK_Athlon: 2903 case CK_AthlonThunderbird: 2904 case CK_Athlon4: 2905 case CK_AthlonXP: 2906 case CK_AthlonMP: 2907 defineCPUMacros(Builder, "athlon"); 2908 if (SSELevel != NoSSE) { 2909 Builder.defineMacro("__athlon_sse__"); 2910 Builder.defineMacro("__tune_athlon_sse__"); 2911 } 2912 break; 2913 case CK_K8: 2914 case CK_K8SSE3: 2915 case CK_x86_64: 2916 case CK_Opteron: 2917 case CK_OpteronSSE3: 2918 case CK_Athlon64: 2919 case CK_Athlon64SSE3: 2920 case CK_AthlonFX: 2921 defineCPUMacros(Builder, "k8"); 2922 break; 2923 case CK_AMDFAM10: 2924 defineCPUMacros(Builder, "amdfam10"); 2925 break; 2926 case CK_BTVER1: 2927 defineCPUMacros(Builder, "btver1"); 2928 break; 2929 case CK_BTVER2: 2930 defineCPUMacros(Builder, "btver2"); 2931 break; 2932 case CK_BDVER1: 2933 defineCPUMacros(Builder, "bdver1"); 2934 break; 2935 case CK_BDVER2: 2936 defineCPUMacros(Builder, "bdver2"); 2937 break; 2938 case CK_BDVER3: 2939 defineCPUMacros(Builder, "bdver3"); 2940 break; 2941 case CK_BDVER4: 2942 defineCPUMacros(Builder, "bdver4"); 2943 break; 2944 case CK_Geode: 2945 defineCPUMacros(Builder, "geode"); 2946 break; 2947 } 2948 2949 // Target properties. 2950 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2951 2952 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2953 // functions in glibc header files that use FP Stack inline asm which the 2954 // backend can't deal with (PR879). 2955 Builder.defineMacro("__NO_MATH_INLINES"); 2956 2957 if (HasAES) 2958 Builder.defineMacro("__AES__"); 2959 2960 if (HasPCLMUL) 2961 Builder.defineMacro("__PCLMUL__"); 2962 2963 if (HasLZCNT) 2964 Builder.defineMacro("__LZCNT__"); 2965 2966 if (HasRDRND) 2967 Builder.defineMacro("__RDRND__"); 2968 2969 if (HasFSGSBASE) 2970 Builder.defineMacro("__FSGSBASE__"); 2971 2972 if (HasBMI) 2973 Builder.defineMacro("__BMI__"); 2974 2975 if (HasBMI2) 2976 Builder.defineMacro("__BMI2__"); 2977 2978 if (HasPOPCNT) 2979 Builder.defineMacro("__POPCNT__"); 2980 2981 if (HasRTM) 2982 Builder.defineMacro("__RTM__"); 2983 2984 if (HasPRFCHW) 2985 Builder.defineMacro("__PRFCHW__"); 2986 2987 if (HasRDSEED) 2988 Builder.defineMacro("__RDSEED__"); 2989 2990 if (HasADX) 2991 Builder.defineMacro("__ADX__"); 2992 2993 if (HasTBM) 2994 Builder.defineMacro("__TBM__"); 2995 2996 switch (XOPLevel) { 2997 case XOP: 2998 Builder.defineMacro("__XOP__"); 2999 case FMA4: 3000 Builder.defineMacro("__FMA4__"); 3001 case SSE4A: 3002 Builder.defineMacro("__SSE4A__"); 3003 case NoXOP: 3004 break; 3005 } 3006 3007 if (HasFMA) 3008 Builder.defineMacro("__FMA__"); 3009 3010 if (HasF16C) 3011 Builder.defineMacro("__F16C__"); 3012 3013 if (HasAVX512CD) 3014 Builder.defineMacro("__AVX512CD__"); 3015 if (HasAVX512ER) 3016 Builder.defineMacro("__AVX512ER__"); 3017 if (HasAVX512PF) 3018 Builder.defineMacro("__AVX512PF__"); 3019 if (HasAVX512DQ) 3020 Builder.defineMacro("__AVX512DQ__"); 3021 if (HasAVX512BW) 3022 Builder.defineMacro("__AVX512BW__"); 3023 if (HasAVX512VL) 3024 Builder.defineMacro("__AVX512VL__"); 3025 3026 if (HasSHA) 3027 Builder.defineMacro("__SHA__"); 3028 3029 if (HasCX16) 3030 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3031 3032 // Each case falls through to the previous one here. 3033 switch (SSELevel) { 3034 case AVX512F: 3035 Builder.defineMacro("__AVX512F__"); 3036 case AVX2: 3037 Builder.defineMacro("__AVX2__"); 3038 case AVX: 3039 Builder.defineMacro("__AVX__"); 3040 case SSE42: 3041 Builder.defineMacro("__SSE4_2__"); 3042 case SSE41: 3043 Builder.defineMacro("__SSE4_1__"); 3044 case SSSE3: 3045 Builder.defineMacro("__SSSE3__"); 3046 case SSE3: 3047 Builder.defineMacro("__SSE3__"); 3048 case SSE2: 3049 Builder.defineMacro("__SSE2__"); 3050 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3051 case SSE1: 3052 Builder.defineMacro("__SSE__"); 3053 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3054 case NoSSE: 3055 break; 3056 } 3057 3058 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3059 switch (SSELevel) { 3060 case AVX512F: 3061 case AVX2: 3062 case AVX: 3063 case SSE42: 3064 case SSE41: 3065 case SSSE3: 3066 case SSE3: 3067 case SSE2: 3068 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3069 break; 3070 case SSE1: 3071 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3072 break; 3073 default: 3074 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3075 } 3076 } 3077 3078 // Each case falls through to the previous one here. 3079 switch (MMX3DNowLevel) { 3080 case AMD3DNowAthlon: 3081 Builder.defineMacro("__3dNOW_A__"); 3082 case AMD3DNow: 3083 Builder.defineMacro("__3dNOW__"); 3084 case MMX: 3085 Builder.defineMacro("__MMX__"); 3086 case NoMMX3DNow: 3087 break; 3088 } 3089 3090 if (CPU >= CK_i486) { 3091 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3092 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3093 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3094 } 3095 if (CPU >= CK_i586) 3096 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3097 } 3098 3099 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3100 return llvm::StringSwitch<bool>(Feature) 3101 .Case("aes", HasAES) 3102 .Case("avx", SSELevel >= AVX) 3103 .Case("avx2", SSELevel >= AVX2) 3104 .Case("avx512f", SSELevel >= AVX512F) 3105 .Case("avx512cd", HasAVX512CD) 3106 .Case("avx512er", HasAVX512ER) 3107 .Case("avx512pf", HasAVX512PF) 3108 .Case("avx512dq", HasAVX512DQ) 3109 .Case("avx512bw", HasAVX512BW) 3110 .Case("avx512vl", HasAVX512VL) 3111 .Case("bmi", HasBMI) 3112 .Case("bmi2", HasBMI2) 3113 .Case("cx16", HasCX16) 3114 .Case("f16c", HasF16C) 3115 .Case("fma", HasFMA) 3116 .Case("fma4", XOPLevel >= FMA4) 3117 .Case("fsgsbase", HasFSGSBASE) 3118 .Case("lzcnt", HasLZCNT) 3119 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3120 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3121 .Case("mmx", MMX3DNowLevel >= MMX) 3122 .Case("pclmul", HasPCLMUL) 3123 .Case("popcnt", HasPOPCNT) 3124 .Case("prfchw", HasPRFCHW) 3125 .Case("rdrnd", HasRDRND) 3126 .Case("rdseed", HasRDSEED) 3127 .Case("rtm", HasRTM) 3128 .Case("sha", HasSHA) 3129 .Case("sse", SSELevel >= SSE1) 3130 .Case("sse2", SSELevel >= SSE2) 3131 .Case("sse3", SSELevel >= SSE3) 3132 .Case("ssse3", SSELevel >= SSSE3) 3133 .Case("sse4.1", SSELevel >= SSE41) 3134 .Case("sse4.2", SSELevel >= SSE42) 3135 .Case("sse4a", XOPLevel >= SSE4A) 3136 .Case("tbm", HasTBM) 3137 .Case("x86", true) 3138 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3139 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3140 .Case("xop", XOPLevel >= XOP) 3141 .Default(false); 3142 } 3143 3144 bool 3145 X86TargetInfo::validateAsmConstraint(const char *&Name, 3146 TargetInfo::ConstraintInfo &Info) const { 3147 switch (*Name) { 3148 default: return false; 3149 case 'I': 3150 Info.setRequiresImmediate(0, 31); 3151 return true; 3152 case 'J': 3153 Info.setRequiresImmediate(0, 63); 3154 return true; 3155 case 'K': 3156 Info.setRequiresImmediate(-128, 127); 3157 return true; 3158 case 'L': 3159 // FIXME: properly analyze this constraint: 3160 // must be one of 0xff, 0xffff, or 0xffffffff 3161 return true; 3162 case 'M': 3163 Info.setRequiresImmediate(0, 3); 3164 return true; 3165 case 'N': 3166 Info.setRequiresImmediate(0, 255); 3167 return true; 3168 case 'O': 3169 Info.setRequiresImmediate(0, 127); 3170 return true; 3171 case 'Y': // first letter of a pair: 3172 switch (*(Name+1)) { 3173 default: return false; 3174 case '0': // First SSE register. 3175 case 't': // Any SSE register, when SSE2 is enabled. 3176 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3177 case 'm': // any MMX register, when inter-unit moves enabled. 3178 break; // falls through to setAllowsRegister. 3179 } 3180 case 'f': // any x87 floating point stack register. 3181 // Constraint 'f' cannot be used for output operands. 3182 if (Info.ConstraintStr[0] == '=') 3183 return false; 3184 3185 Info.setAllowsRegister(); 3186 return true; 3187 case 'a': // eax. 3188 case 'b': // ebx. 3189 case 'c': // ecx. 3190 case 'd': // edx. 3191 case 'S': // esi. 3192 case 'D': // edi. 3193 case 'A': // edx:eax. 3194 case 't': // top of floating point stack. 3195 case 'u': // second from top of floating point stack. 3196 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3197 case 'y': // Any MMX register. 3198 case 'x': // Any SSE register. 3199 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3200 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3201 case 'l': // "Index" registers: any general register that can be used as an 3202 // index in a base+index memory access. 3203 Info.setAllowsRegister(); 3204 return true; 3205 case 'C': // SSE floating point constant. 3206 case 'G': // x87 floating point constant. 3207 case 'e': // 32-bit signed integer constant for use with zero-extending 3208 // x86_64 instructions. 3209 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3210 // x86_64 instructions. 3211 return true; 3212 } 3213 } 3214 3215 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3216 unsigned Size) const { 3217 // Strip off constraint modifiers. 3218 while (Constraint[0] == '=' || 3219 Constraint[0] == '+' || 3220 Constraint[0] == '&') 3221 Constraint = Constraint.substr(1); 3222 3223 return validateOperandSize(Constraint, Size); 3224 } 3225 3226 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3227 unsigned Size) const { 3228 return validateOperandSize(Constraint, Size); 3229 } 3230 3231 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3232 unsigned Size) const { 3233 switch (Constraint[0]) { 3234 default: break; 3235 case 'y': 3236 return Size <= 64; 3237 case 'f': 3238 case 't': 3239 case 'u': 3240 return Size <= 128; 3241 case 'x': 3242 // 256-bit ymm registers can be used if target supports AVX. 3243 return Size <= (SSELevel >= AVX ? 256U : 128U); 3244 } 3245 3246 return true; 3247 } 3248 3249 std::string 3250 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3251 switch (*Constraint) { 3252 case 'a': return std::string("{ax}"); 3253 case 'b': return std::string("{bx}"); 3254 case 'c': return std::string("{cx}"); 3255 case 'd': return std::string("{dx}"); 3256 case 'S': return std::string("{si}"); 3257 case 'D': return std::string("{di}"); 3258 case 'p': // address 3259 return std::string("im"); 3260 case 't': // top of floating point stack. 3261 return std::string("{st}"); 3262 case 'u': // second from top of floating point stack. 3263 return std::string("{st(1)}"); // second from top of floating point stack. 3264 default: 3265 return std::string(1, *Constraint); 3266 } 3267 } 3268 } // end anonymous namespace 3269 3270 namespace { 3271 // X86-32 generic target 3272 class X86_32TargetInfo : public X86TargetInfo { 3273 public: 3274 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3275 DoubleAlign = LongLongAlign = 32; 3276 LongDoubleWidth = 96; 3277 LongDoubleAlign = 32; 3278 SuitableAlign = 128; 3279 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3280 SizeType = UnsignedInt; 3281 PtrDiffType = SignedInt; 3282 IntPtrType = SignedInt; 3283 RegParmMax = 3; 3284 3285 // Use fpret for all types. 3286 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3287 (1 << TargetInfo::Double) | 3288 (1 << TargetInfo::LongDouble)); 3289 3290 // x86-32 has atomics up to 8 bytes 3291 // FIXME: Check that we actually have cmpxchg8b before setting 3292 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3293 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3294 } 3295 BuiltinVaListKind getBuiltinVaListKind() const override { 3296 return TargetInfo::CharPtrBuiltinVaList; 3297 } 3298 3299 int getEHDataRegisterNumber(unsigned RegNo) const override { 3300 if (RegNo == 0) return 0; 3301 if (RegNo == 1) return 2; 3302 return -1; 3303 } 3304 bool validateOperandSize(StringRef Constraint, 3305 unsigned Size) const override { 3306 switch (Constraint[0]) { 3307 default: break; 3308 case 'R': 3309 case 'q': 3310 case 'Q': 3311 case 'a': 3312 case 'b': 3313 case 'c': 3314 case 'd': 3315 case 'S': 3316 case 'D': 3317 return Size <= 32; 3318 case 'A': 3319 return Size <= 64; 3320 } 3321 3322 return X86TargetInfo::validateOperandSize(Constraint, Size); 3323 } 3324 }; 3325 } // end anonymous namespace 3326 3327 namespace { 3328 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3329 public: 3330 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3331 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3332 3333 unsigned getFloatEvalMethod() const override { 3334 unsigned Major, Minor, Micro; 3335 getTriple().getOSVersion(Major, Minor, Micro); 3336 // New NetBSD uses the default rounding mode. 3337 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3338 return X86_32TargetInfo::getFloatEvalMethod(); 3339 // NetBSD before 6.99.26 defaults to "double" rounding. 3340 return 1; 3341 } 3342 }; 3343 } // end anonymous namespace 3344 3345 namespace { 3346 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3347 public: 3348 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3349 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3350 SizeType = UnsignedLong; 3351 IntPtrType = SignedLong; 3352 PtrDiffType = SignedLong; 3353 } 3354 }; 3355 } // end anonymous namespace 3356 3357 namespace { 3358 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3359 public: 3360 BitrigI386TargetInfo(const llvm::Triple &Triple) 3361 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3362 SizeType = UnsignedLong; 3363 IntPtrType = SignedLong; 3364 PtrDiffType = SignedLong; 3365 } 3366 }; 3367 } // end anonymous namespace 3368 3369 namespace { 3370 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3371 public: 3372 DarwinI386TargetInfo(const llvm::Triple &Triple) 3373 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3374 LongDoubleWidth = 128; 3375 LongDoubleAlign = 128; 3376 SuitableAlign = 128; 3377 MaxVectorAlign = 256; 3378 SizeType = UnsignedLong; 3379 IntPtrType = SignedLong; 3380 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3381 HasAlignMac68kSupport = true; 3382 } 3383 3384 }; 3385 } // end anonymous namespace 3386 3387 namespace { 3388 // x86-32 Windows target 3389 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3390 public: 3391 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3392 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3393 WCharType = UnsignedShort; 3394 DoubleAlign = LongLongAlign = 64; 3395 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3396 } 3397 void getTargetDefines(const LangOptions &Opts, 3398 MacroBuilder &Builder) const override { 3399 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3400 } 3401 }; 3402 3403 // x86-32 Windows Visual Studio target 3404 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3405 public: 3406 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3407 : WindowsX86_32TargetInfo(Triple) { 3408 LongDoubleWidth = LongDoubleAlign = 64; 3409 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3410 } 3411 void getTargetDefines(const LangOptions &Opts, 3412 MacroBuilder &Builder) const override { 3413 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3414 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3415 // The value of the following reflects processor type. 3416 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3417 // We lost the original triple, so we use the default. 3418 Builder.defineMacro("_M_IX86", "600"); 3419 } 3420 }; 3421 } // end anonymous namespace 3422 3423 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3424 Builder.defineMacro("__MSVCRT__"); 3425 Builder.defineMacro("__MINGW32__"); 3426 3427 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3428 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3429 // macro anyway for pre-processor compatibility. 3430 if (Opts.MicrosoftExt) 3431 Builder.defineMacro("__declspec", "__declspec"); 3432 else 3433 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3434 3435 if (!Opts.MicrosoftExt) { 3436 // Provide macros for all the calling convention keywords. Provide both 3437 // single and double underscore prefixed variants. These are available on 3438 // x64 as well as x86, even though they have no effect. 3439 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3440 for (const char *CC : CCs) { 3441 std::string GCCSpelling = "__attribute__((__"; 3442 GCCSpelling += CC; 3443 GCCSpelling += "__))"; 3444 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3445 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3446 } 3447 } 3448 } 3449 3450 namespace { 3451 // x86-32 MinGW target 3452 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3453 public: 3454 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3455 : WindowsX86_32TargetInfo(Triple) {} 3456 void getTargetDefines(const LangOptions &Opts, 3457 MacroBuilder &Builder) const override { 3458 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3459 DefineStd(Builder, "WIN32", Opts); 3460 DefineStd(Builder, "WINNT", Opts); 3461 Builder.defineMacro("_X86_"); 3462 addMinGWDefines(Opts, Builder); 3463 } 3464 }; 3465 } // end anonymous namespace 3466 3467 namespace { 3468 // x86-32 Cygwin target 3469 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3470 public: 3471 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3472 : X86_32TargetInfo(Triple) { 3473 TLSSupported = false; 3474 WCharType = UnsignedShort; 3475 DoubleAlign = LongLongAlign = 64; 3476 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3477 } 3478 void getTargetDefines(const LangOptions &Opts, 3479 MacroBuilder &Builder) const override { 3480 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3481 Builder.defineMacro("_X86_"); 3482 Builder.defineMacro("__CYGWIN__"); 3483 Builder.defineMacro("__CYGWIN32__"); 3484 DefineStd(Builder, "unix", Opts); 3485 if (Opts.CPlusPlus) 3486 Builder.defineMacro("_GNU_SOURCE"); 3487 } 3488 }; 3489 } // end anonymous namespace 3490 3491 namespace { 3492 // x86-32 Haiku target 3493 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3494 public: 3495 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3496 SizeType = UnsignedLong; 3497 IntPtrType = SignedLong; 3498 PtrDiffType = SignedLong; 3499 ProcessIDType = SignedLong; 3500 this->UserLabelPrefix = ""; 3501 this->TLSSupported = false; 3502 } 3503 void getTargetDefines(const LangOptions &Opts, 3504 MacroBuilder &Builder) const override { 3505 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3506 Builder.defineMacro("__INTEL__"); 3507 Builder.defineMacro("__HAIKU__"); 3508 } 3509 }; 3510 } // end anonymous namespace 3511 3512 // RTEMS Target 3513 template<typename Target> 3514 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3515 protected: 3516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3517 MacroBuilder &Builder) const override { 3518 // RTEMS defines; list based off of gcc output 3519 3520 Builder.defineMacro("__rtems__"); 3521 Builder.defineMacro("__ELF__"); 3522 } 3523 3524 public: 3525 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3526 this->UserLabelPrefix = ""; 3527 3528 switch (Triple.getArch()) { 3529 default: 3530 case llvm::Triple::x86: 3531 // this->MCountName = ".mcount"; 3532 break; 3533 case llvm::Triple::mips: 3534 case llvm::Triple::mipsel: 3535 case llvm::Triple::ppc: 3536 case llvm::Triple::ppc64: 3537 case llvm::Triple::ppc64le: 3538 // this->MCountName = "_mcount"; 3539 break; 3540 case llvm::Triple::arm: 3541 // this->MCountName = "__mcount"; 3542 break; 3543 } 3544 } 3545 }; 3546 3547 namespace { 3548 // x86-32 RTEMS target 3549 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3550 public: 3551 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3552 SizeType = UnsignedLong; 3553 IntPtrType = SignedLong; 3554 PtrDiffType = SignedLong; 3555 this->UserLabelPrefix = ""; 3556 } 3557 void getTargetDefines(const LangOptions &Opts, 3558 MacroBuilder &Builder) const override { 3559 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3560 Builder.defineMacro("__INTEL__"); 3561 Builder.defineMacro("__rtems__"); 3562 } 3563 }; 3564 } // end anonymous namespace 3565 3566 namespace { 3567 // x86-64 generic target 3568 class X86_64TargetInfo : public X86TargetInfo { 3569 public: 3570 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3571 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3572 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3573 LongDoubleWidth = 128; 3574 LongDoubleAlign = 128; 3575 LargeArrayMinWidth = 128; 3576 LargeArrayAlign = 128; 3577 SuitableAlign = 128; 3578 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3579 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3580 IntPtrType = IsX32 ? SignedInt : SignedLong; 3581 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3582 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3583 RegParmMax = 6; 3584 3585 // Pointers are 32-bit in x32. 3586 DescriptionString = (IsX32) 3587 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3588 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3589 3590 // Use fpret only for long double. 3591 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3592 3593 // Use fp2ret for _Complex long double. 3594 ComplexLongDoubleUsesFP2Ret = true; 3595 3596 // x86-64 has atomics up to 16 bytes. 3597 MaxAtomicPromoteWidth = 128; 3598 MaxAtomicInlineWidth = 128; 3599 } 3600 BuiltinVaListKind getBuiltinVaListKind() const override { 3601 return TargetInfo::X86_64ABIBuiltinVaList; 3602 } 3603 3604 int getEHDataRegisterNumber(unsigned RegNo) const override { 3605 if (RegNo == 0) return 0; 3606 if (RegNo == 1) return 1; 3607 return -1; 3608 } 3609 3610 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3611 return (CC == CC_C || 3612 CC == CC_X86VectorCall || 3613 CC == CC_IntelOclBicc || 3614 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3615 } 3616 3617 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3618 return CC_C; 3619 } 3620 3621 // for x32 we need it here explicitly 3622 bool hasInt128Type() const override { return true; } 3623 }; 3624 } // end anonymous namespace 3625 3626 namespace { 3627 // x86-64 Windows target 3628 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3629 public: 3630 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3631 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3632 WCharType = UnsignedShort; 3633 LongWidth = LongAlign = 32; 3634 DoubleAlign = LongLongAlign = 64; 3635 IntMaxType = SignedLongLong; 3636 Int64Type = SignedLongLong; 3637 SizeType = UnsignedLongLong; 3638 PtrDiffType = SignedLongLong; 3639 IntPtrType = SignedLongLong; 3640 this->UserLabelPrefix = ""; 3641 } 3642 3643 void getTargetDefines(const LangOptions &Opts, 3644 MacroBuilder &Builder) const override { 3645 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3646 Builder.defineMacro("_WIN64"); 3647 } 3648 3649 BuiltinVaListKind getBuiltinVaListKind() const override { 3650 return TargetInfo::CharPtrBuiltinVaList; 3651 } 3652 3653 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3654 switch (CC) { 3655 case CC_X86StdCall: 3656 case CC_X86ThisCall: 3657 case CC_X86FastCall: 3658 return CCCR_Ignore; 3659 case CC_C: 3660 case CC_X86VectorCall: 3661 case CC_IntelOclBicc: 3662 case CC_X86_64SysV: 3663 return CCCR_OK; 3664 default: 3665 return CCCR_Warning; 3666 } 3667 } 3668 }; 3669 } // end anonymous namespace 3670 3671 namespace { 3672 // x86-64 Windows Visual Studio target 3673 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3674 public: 3675 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3676 : WindowsX86_64TargetInfo(Triple) { 3677 LongDoubleWidth = LongDoubleAlign = 64; 3678 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3679 } 3680 void getTargetDefines(const LangOptions &Opts, 3681 MacroBuilder &Builder) const override { 3682 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3683 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3684 Builder.defineMacro("_M_X64"); 3685 Builder.defineMacro("_M_AMD64"); 3686 } 3687 }; 3688 } // end anonymous namespace 3689 3690 namespace { 3691 // x86-64 MinGW target 3692 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3693 public: 3694 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3695 : WindowsX86_64TargetInfo(Triple) {} 3696 void getTargetDefines(const LangOptions &Opts, 3697 MacroBuilder &Builder) const override { 3698 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3699 DefineStd(Builder, "WIN64", Opts); 3700 Builder.defineMacro("__MINGW64__"); 3701 addMinGWDefines(Opts, Builder); 3702 3703 // GCC defines this macro when it is using __gxx_personality_seh0. 3704 if (!Opts.SjLjExceptions) 3705 Builder.defineMacro("__SEH__"); 3706 } 3707 }; 3708 } // end anonymous namespace 3709 3710 namespace { 3711 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3712 public: 3713 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3714 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3715 Int64Type = SignedLongLong; 3716 MaxVectorAlign = 256; 3717 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3718 llvm::Triple T = llvm::Triple(Triple); 3719 if (T.isiOS()) 3720 UseSignedCharForObjCBool = false; 3721 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3722 } 3723 }; 3724 } // end anonymous namespace 3725 3726 namespace { 3727 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3728 public: 3729 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3730 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3731 IntMaxType = SignedLongLong; 3732 Int64Type = SignedLongLong; 3733 } 3734 }; 3735 } // end anonymous namespace 3736 3737 namespace { 3738 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3739 public: 3740 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3741 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3742 IntMaxType = SignedLongLong; 3743 Int64Type = SignedLongLong; 3744 } 3745 }; 3746 } 3747 3748 3749 namespace { 3750 class ARMTargetInfo : public TargetInfo { 3751 // Possible FPU choices. 3752 enum FPUMode { 3753 VFP2FPU = (1 << 0), 3754 VFP3FPU = (1 << 1), 3755 VFP4FPU = (1 << 2), 3756 NeonFPU = (1 << 3), 3757 FPARMV8 = (1 << 4) 3758 }; 3759 3760 // Possible HWDiv features. 3761 enum HWDivMode { 3762 HWDivThumb = (1 << 0), 3763 HWDivARM = (1 << 1) 3764 }; 3765 3766 static bool FPUModeIsVFP(FPUMode Mode) { 3767 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3768 } 3769 3770 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3771 static const char * const GCCRegNames[]; 3772 3773 std::string ABI, CPU; 3774 3775 enum { 3776 FP_Default, 3777 FP_VFP, 3778 FP_Neon 3779 } FPMath; 3780 3781 unsigned FPU : 5; 3782 3783 unsigned IsAAPCS : 1; 3784 unsigned IsThumb : 1; 3785 unsigned HWDiv : 2; 3786 3787 // Initialized via features. 3788 unsigned SoftFloat : 1; 3789 unsigned SoftFloatABI : 1; 3790 3791 unsigned CRC : 1; 3792 unsigned Crypto : 1; 3793 3794 // ACLE 6.5.1 Hardware floating point 3795 enum { 3796 HW_FP_HP = (1 << 1), /// half (16-bit) 3797 HW_FP_SP = (1 << 2), /// single (32-bit) 3798 HW_FP_DP = (1 << 3), /// double (64-bit) 3799 }; 3800 uint32_t HW_FP; 3801 3802 static const Builtin::Info BuiltinInfo[]; 3803 3804 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3805 StringRef ArchName = T.getArchName(); 3806 if (T.getArch() == llvm::Triple::arm || 3807 T.getArch() == llvm::Triple::armeb) { 3808 StringRef VersionStr; 3809 if (ArchName.startswith("armv")) 3810 VersionStr = ArchName.substr(4, 1); 3811 else if (ArchName.startswith("armebv")) 3812 VersionStr = ArchName.substr(6, 1); 3813 else 3814 return false; 3815 unsigned Version; 3816 if (VersionStr.getAsInteger(10, Version)) 3817 return false; 3818 return Version >= 6; 3819 } 3820 assert(T.getArch() == llvm::Triple::thumb || 3821 T.getArch() == llvm::Triple::thumbeb); 3822 StringRef VersionStr; 3823 if (ArchName.startswith("thumbv")) 3824 VersionStr = ArchName.substr(6, 1); 3825 else if (ArchName.startswith("thumbebv")) 3826 VersionStr = ArchName.substr(8, 1); 3827 else 3828 return false; 3829 unsigned Version; 3830 if (VersionStr.getAsInteger(10, Version)) 3831 return false; 3832 return Version >= 7; 3833 } 3834 3835 void setABIAAPCS() { 3836 IsAAPCS = true; 3837 3838 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3839 const llvm::Triple &T = getTriple(); 3840 3841 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 3842 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 3843 T.getOS() == llvm::Triple::Bitrig) 3844 SizeType = UnsignedLong; 3845 else 3846 SizeType = UnsignedInt; 3847 3848 switch (T.getOS()) { 3849 case llvm::Triple::NetBSD: 3850 WCharType = SignedInt; 3851 break; 3852 case llvm::Triple::Win32: 3853 WCharType = UnsignedShort; 3854 break; 3855 case llvm::Triple::Linux: 3856 default: 3857 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3858 WCharType = UnsignedInt; 3859 break; 3860 } 3861 3862 UseBitFieldTypeAlignment = true; 3863 3864 ZeroLengthBitfieldBoundary = 0; 3865 3866 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3867 // so set preferred for small types to 32. 3868 if (T.isOSBinFormatMachO()) { 3869 DescriptionString = 3870 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3871 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3872 } else if (T.isOSWindows()) { 3873 // FIXME: this is invalid for WindowsCE 3874 assert(!BigEndian && "Windows on ARM does not support big endian"); 3875 DescriptionString = "e" 3876 "-m:e" 3877 "-p:32:32" 3878 "-i64:64" 3879 "-v128:64:128" 3880 "-a:0:32" 3881 "-n32" 3882 "-S64"; 3883 } else { 3884 DescriptionString = 3885 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 3886 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 3887 } 3888 3889 // FIXME: Enumerated types are variable width in straight AAPCS. 3890 } 3891 3892 void setABIAPCS() { 3893 const llvm::Triple &T = getTriple(); 3894 3895 IsAAPCS = false; 3896 3897 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3898 3899 // size_t is unsigned int on FreeBSD. 3900 if (T.getOS() == llvm::Triple::FreeBSD) 3901 SizeType = UnsignedInt; 3902 else 3903 SizeType = UnsignedLong; 3904 3905 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3906 WCharType = SignedInt; 3907 3908 // Do not respect the alignment of bit-field types when laying out 3909 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3910 UseBitFieldTypeAlignment = false; 3911 3912 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3913 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3914 /// gcc. 3915 ZeroLengthBitfieldBoundary = 32; 3916 3917 if (T.isOSBinFormatMachO()) 3918 DescriptionString = 3919 BigEndian 3920 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3921 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3922 else 3923 DescriptionString = 3924 BigEndian 3925 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 3926 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3927 3928 // FIXME: Override "preferred align" for double and long long. 3929 } 3930 3931 public: 3932 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3933 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3934 IsAAPCS(true), HW_FP(0) { 3935 BigEndian = IsBigEndian; 3936 3937 switch (getTriple().getOS()) { 3938 case llvm::Triple::NetBSD: 3939 PtrDiffType = SignedLong; 3940 break; 3941 default: 3942 PtrDiffType = SignedInt; 3943 break; 3944 } 3945 3946 // {} in inline assembly are neon specifiers, not assembly variant 3947 // specifiers. 3948 NoAsmVariants = true; 3949 3950 // FIXME: Should we just treat this as a feature? 3951 IsThumb = getTriple().getArchName().startswith("thumb"); 3952 3953 // FIXME: This duplicates code from the driver that sets the -target-abi 3954 // option - this code is used if -target-abi isn't passed and should 3955 // be unified in some way. 3956 if (Triple.isOSBinFormatMachO()) { 3957 // The backend is hardwired to assume AAPCS for M-class processors, ensure 3958 // the frontend matches that. 3959 if (Triple.getEnvironment() == llvm::Triple::EABI || 3960 Triple.getOS() == llvm::Triple::UnknownOS || 3961 StringRef(CPU).startswith("cortex-m")) { 3962 setABI("aapcs"); 3963 } else { 3964 setABI("apcs-gnu"); 3965 } 3966 } else if (Triple.isOSWindows()) { 3967 // FIXME: this is invalid for WindowsCE 3968 setABI("aapcs"); 3969 } else { 3970 // Select the default based on the platform. 3971 switch (Triple.getEnvironment()) { 3972 case llvm::Triple::Android: 3973 case llvm::Triple::GNUEABI: 3974 case llvm::Triple::GNUEABIHF: 3975 setABI("aapcs-linux"); 3976 break; 3977 case llvm::Triple::EABIHF: 3978 case llvm::Triple::EABI: 3979 setABI("aapcs"); 3980 break; 3981 case llvm::Triple::GNU: 3982 setABI("apcs-gnu"); 3983 break; 3984 default: 3985 if (Triple.getOS() == llvm::Triple::NetBSD) 3986 setABI("apcs-gnu"); 3987 else 3988 setABI("aapcs"); 3989 break; 3990 } 3991 } 3992 3993 // ARM targets default to using the ARM C++ ABI. 3994 TheCXXABI.set(TargetCXXABI::GenericARM); 3995 3996 // ARM has atomics up to 8 bytes 3997 MaxAtomicPromoteWidth = 64; 3998 if (shouldUseInlineAtomic(getTriple())) 3999 MaxAtomicInlineWidth = 64; 4000 4001 // Do force alignment of members that follow zero length bitfields. If 4002 // the alignment of the zero-length bitfield is greater than the member 4003 // that follows it, `bar', `bar' will be aligned as the type of the 4004 // zero length bitfield. 4005 UseZeroLengthBitfieldAlignment = true; 4006 } 4007 StringRef getABI() const override { return ABI; } 4008 bool setABI(const std::string &Name) override { 4009 ABI = Name; 4010 4011 // The defaults (above) are for AAPCS, check if we need to change them. 4012 // 4013 // FIXME: We need support for -meabi... we could just mangle it into the 4014 // name. 4015 if (Name == "apcs-gnu") { 4016 setABIAPCS(); 4017 return true; 4018 } 4019 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4020 setABIAAPCS(); 4021 return true; 4022 } 4023 return false; 4024 } 4025 4026 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4027 StringRef ArchName = getTriple().getArchName(); 4028 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4029 Features["vfp2"] = true; 4030 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4031 Features["vfp3"] = true; 4032 Features["neon"] = true; 4033 } 4034 else if (CPU == "cortex-a5") { 4035 Features["vfp4"] = true; 4036 Features["neon"] = true; 4037 } else if (CPU == "swift" || CPU == "cortex-a7" || 4038 CPU == "cortex-a12" || CPU == "cortex-a15" || 4039 CPU == "cortex-a17" || CPU == "krait") { 4040 Features["vfp4"] = true; 4041 Features["neon"] = true; 4042 Features["hwdiv"] = true; 4043 Features["hwdiv-arm"] = true; 4044 } else if (CPU == "cyclone") { 4045 Features["v8fp"] = true; 4046 Features["neon"] = true; 4047 Features["hwdiv"] = true; 4048 Features["hwdiv-arm"] = true; 4049 } else if (CPU == "cortex-a53" || CPU == "cortex-a57" || CPU == "cortex-a72") { 4050 Features["fp-armv8"] = true; 4051 Features["neon"] = true; 4052 Features["hwdiv"] = true; 4053 Features["hwdiv-arm"] = true; 4054 Features["crc"] = true; 4055 Features["crypto"] = true; 4056 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4057 // Enable the hwdiv extension for all v8a AArch32 cores by 4058 // default. 4059 ArchName == "armv8a" || ArchName == "armv8" || 4060 ArchName == "armebv8a" || ArchName == "armebv8" || 4061 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4062 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4063 Features["hwdiv"] = true; 4064 Features["hwdiv-arm"] = true; 4065 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4066 CPU == "sc300") { 4067 Features["hwdiv"] = true; 4068 } 4069 } 4070 4071 bool handleTargetFeatures(std::vector<std::string> &Features, 4072 DiagnosticsEngine &Diags) override { 4073 FPU = 0; 4074 CRC = 0; 4075 Crypto = 0; 4076 SoftFloat = SoftFloatABI = false; 4077 HWDiv = 0; 4078 4079 for (const auto &Feature : Features) { 4080 if (Feature == "+soft-float") { 4081 SoftFloat = true; 4082 } else if (Feature == "+soft-float-abi") { 4083 SoftFloatABI = true; 4084 } else if (Feature == "+vfp2") { 4085 FPU |= VFP2FPU; 4086 HW_FP = HW_FP_SP | HW_FP_DP; 4087 } else if (Feature == "+vfp3") { 4088 FPU |= VFP3FPU; 4089 HW_FP = HW_FP_SP | HW_FP_DP; 4090 } else if (Feature == "+vfp4") { 4091 FPU |= VFP4FPU; 4092 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4093 } else if (Feature == "+fp-armv8") { 4094 FPU |= FPARMV8; 4095 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4096 } else if (Feature == "+neon") { 4097 FPU |= NeonFPU; 4098 HW_FP = HW_FP_SP | HW_FP_DP; 4099 } else if (Feature == "+hwdiv") { 4100 HWDiv |= HWDivThumb; 4101 } else if (Feature == "+hwdiv-arm") { 4102 HWDiv |= HWDivARM; 4103 } else if (Feature == "+crc") { 4104 CRC = 1; 4105 } else if (Feature == "+crypto") { 4106 Crypto = 1; 4107 } else if (Feature == "+fp-only-sp") { 4108 HW_FP &= ~HW_FP_DP; 4109 } 4110 } 4111 4112 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4113 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4114 return false; 4115 } 4116 4117 if (FPMath == FP_Neon) 4118 Features.push_back("+neonfp"); 4119 else if (FPMath == FP_VFP) 4120 Features.push_back("-neonfp"); 4121 4122 // Remove front-end specific options which the backend handles differently. 4123 const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" }; 4124 for (const auto &FEFeature : FrontEndFeatures) { 4125 auto Feature = std::find(Features.begin(), Features.end(), FEFeature); 4126 if (Feature != Features.end()) 4127 Features.erase(Feature); 4128 } 4129 4130 return true; 4131 } 4132 4133 bool hasFeature(StringRef Feature) const override { 4134 return llvm::StringSwitch<bool>(Feature) 4135 .Case("arm", true) 4136 .Case("softfloat", SoftFloat) 4137 .Case("thumb", IsThumb) 4138 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4139 .Case("hwdiv", HWDiv & HWDivThumb) 4140 .Case("hwdiv-arm", HWDiv & HWDivARM) 4141 .Default(false); 4142 } 4143 // FIXME: Should we actually have some table instead of these switches? 4144 static const char *getCPUDefineSuffix(StringRef Name) { 4145 return llvm::StringSwitch<const char *>(Name) 4146 .Cases("arm8", "arm810", "4") 4147 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4148 "4") 4149 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4150 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4151 .Case("ep9312", "4T") 4152 .Cases("arm10tdmi", "arm1020t", "5T") 4153 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4154 .Case("arm926ej-s", "5TEJ") 4155 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4156 .Cases("xscale", "iwmmxt", "5TE") 4157 .Case("arm1136j-s", "6J") 4158 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4159 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4160 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4161 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4162 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4163 "7A") 4164 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "7R") 4165 .Case("swift", "7S") 4166 .Case("cyclone", "8A") 4167 .Cases("sc300", "cortex-m3", "7M") 4168 .Cases("cortex-m4", "cortex-m7", "7EM") 4169 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4170 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4171 .Default(nullptr); 4172 } 4173 static const char *getCPUProfile(StringRef Name) { 4174 return llvm::StringSwitch<const char *>(Name) 4175 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4176 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4177 "A") 4178 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4179 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4180 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4181 .Cases("cortex-r4", "cortex-r5", "cortex-r7", "R") 4182 .Default(""); 4183 } 4184 bool setCPU(const std::string &Name) override { 4185 if (!getCPUDefineSuffix(Name)) 4186 return false; 4187 4188 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4189 StringRef Profile = getCPUProfile(Name); 4190 if (Profile == "M" && MaxAtomicInlineWidth) { 4191 MaxAtomicPromoteWidth = 32; 4192 MaxAtomicInlineWidth = 32; 4193 } 4194 4195 CPU = Name; 4196 return true; 4197 } 4198 bool setFPMath(StringRef Name) override; 4199 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4200 unsigned CPUArchVer) const { 4201 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4202 (CPUArch.find('M') != StringRef::npos); 4203 } 4204 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4205 unsigned CPUArchVer) const { 4206 // We check both CPUArchVer and ArchName because when only triple is 4207 // specified, the default CPU is arm1136j-s. 4208 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4209 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4210 } 4211 void getTargetDefines(const LangOptions &Opts, 4212 MacroBuilder &Builder) const override { 4213 // Target identification. 4214 Builder.defineMacro("__arm"); 4215 Builder.defineMacro("__arm__"); 4216 4217 // Target properties. 4218 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4219 4220 StringRef CPUArch = getCPUDefineSuffix(CPU); 4221 unsigned int CPUArchVer; 4222 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4223 llvm_unreachable("Invalid char for architecture version number"); 4224 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4225 4226 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4227 StringRef CPUProfile = getCPUProfile(CPU); 4228 StringRef ArchName = getTriple().getArchName(); 4229 4230 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4231 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4232 if (CPUArch[0] >= '8') { 4233 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4234 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4235 } 4236 4237 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4238 // is not defined for the M-profile. 4239 // NOTE that the deffault profile is assumed to be 'A' 4240 if (CPUProfile.empty() || CPUProfile != "M") 4241 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4242 4243 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4244 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4245 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4246 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4247 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4248 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4249 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4250 4251 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4252 // instruction set such as ARM or Thumb. 4253 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4254 4255 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4256 4257 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4258 if (!CPUProfile.empty()) 4259 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4260 4261 // ACLE 6.5.1 Hardware Floating Point 4262 if (HW_FP) 4263 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4264 4265 // ACLE predefines. 4266 Builder.defineMacro("__ARM_ACLE", "200"); 4267 4268 // Subtarget options. 4269 4270 // FIXME: It's more complicated than this and we don't really support 4271 // interworking. 4272 // Windows on ARM does not "support" interworking 4273 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4274 Builder.defineMacro("__THUMB_INTERWORK__"); 4275 4276 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4277 // Embedded targets on Darwin follow AAPCS, but not EABI. 4278 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4279 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4280 Builder.defineMacro("__ARM_EABI__"); 4281 Builder.defineMacro("__ARM_PCS", "1"); 4282 4283 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4284 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4285 } 4286 4287 if (SoftFloat) 4288 Builder.defineMacro("__SOFTFP__"); 4289 4290 if (CPU == "xscale") 4291 Builder.defineMacro("__XSCALE__"); 4292 4293 if (IsThumb) { 4294 Builder.defineMacro("__THUMBEL__"); 4295 Builder.defineMacro("__thumb__"); 4296 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4297 Builder.defineMacro("__thumb2__"); 4298 } 4299 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4300 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4301 4302 // Note, this is always on in gcc, even though it doesn't make sense. 4303 Builder.defineMacro("__APCS_32__"); 4304 4305 if (FPUModeIsVFP((FPUMode) FPU)) { 4306 Builder.defineMacro("__VFP_FP__"); 4307 if (FPU & VFP2FPU) 4308 Builder.defineMacro("__ARM_VFPV2__"); 4309 if (FPU & VFP3FPU) 4310 Builder.defineMacro("__ARM_VFPV3__"); 4311 if (FPU & VFP4FPU) 4312 Builder.defineMacro("__ARM_VFPV4__"); 4313 } 4314 4315 // This only gets set when Neon instructions are actually available, unlike 4316 // the VFP define, hence the soft float and arch check. This is subtly 4317 // different from gcc, we follow the intent which was that it should be set 4318 // when Neon instructions are actually available. 4319 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4320 Builder.defineMacro("__ARM_NEON"); 4321 Builder.defineMacro("__ARM_NEON__"); 4322 } 4323 4324 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4325 Opts.ShortWChar ? "2" : "4"); 4326 4327 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4328 Opts.ShortEnums ? "1" : "4"); 4329 4330 if (CRC) 4331 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4332 4333 if (Crypto) 4334 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4335 4336 if (CPUArchVer >= 6 && CPUArch != "6M") { 4337 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4338 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4339 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4340 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4341 } 4342 4343 bool is5EOrAbove = (CPUArchVer >= 6 || 4344 (CPUArchVer == 5 && 4345 CPUArch.find('E') != StringRef::npos)); 4346 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4347 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4348 Builder.defineMacro("__ARM_FEATURE_DSP"); 4349 } 4350 void getTargetBuiltins(const Builtin::Info *&Records, 4351 unsigned &NumRecords) const override { 4352 Records = BuiltinInfo; 4353 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4354 } 4355 bool isCLZForZeroUndef() const override { return false; } 4356 BuiltinVaListKind getBuiltinVaListKind() const override { 4357 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4358 } 4359 void getGCCRegNames(const char * const *&Names, 4360 unsigned &NumNames) const override; 4361 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4362 unsigned &NumAliases) const override; 4363 bool validateAsmConstraint(const char *&Name, 4364 TargetInfo::ConstraintInfo &Info) const override { 4365 switch (*Name) { 4366 default: break; 4367 case 'l': // r0-r7 4368 case 'h': // r8-r15 4369 case 'w': // VFP Floating point register single precision 4370 case 'P': // VFP Floating point register double precision 4371 Info.setAllowsRegister(); 4372 return true; 4373 case 'I': 4374 case 'J': 4375 case 'K': 4376 case 'L': 4377 case 'M': 4378 // FIXME 4379 return true; 4380 case 'Q': // A memory address that is a single base register. 4381 Info.setAllowsMemory(); 4382 return true; 4383 case 'U': // a memory reference... 4384 switch (Name[1]) { 4385 case 'q': // ...ARMV4 ldrsb 4386 case 'v': // ...VFP load/store (reg+constant offset) 4387 case 'y': // ...iWMMXt load/store 4388 case 't': // address valid for load/store opaque types wider 4389 // than 128-bits 4390 case 'n': // valid address for Neon doubleword vector load/store 4391 case 'm': // valid address for Neon element and structure load/store 4392 case 's': // valid address for non-offset loads/stores of quad-word 4393 // values in four ARM registers 4394 Info.setAllowsMemory(); 4395 Name++; 4396 return true; 4397 } 4398 } 4399 return false; 4400 } 4401 std::string convertConstraint(const char *&Constraint) const override { 4402 std::string R; 4403 switch (*Constraint) { 4404 case 'U': // Two-character constraint; add "^" hint for later parsing. 4405 R = std::string("^") + std::string(Constraint, 2); 4406 Constraint++; 4407 break; 4408 case 'p': // 'p' should be translated to 'r' by default. 4409 R = std::string("r"); 4410 break; 4411 default: 4412 return std::string(1, *Constraint); 4413 } 4414 return R; 4415 } 4416 bool 4417 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4418 std::string &SuggestedModifier) const override { 4419 bool isOutput = (Constraint[0] == '='); 4420 bool isInOut = (Constraint[0] == '+'); 4421 4422 // Strip off constraint modifiers. 4423 while (Constraint[0] == '=' || 4424 Constraint[0] == '+' || 4425 Constraint[0] == '&') 4426 Constraint = Constraint.substr(1); 4427 4428 switch (Constraint[0]) { 4429 default: break; 4430 case 'r': { 4431 switch (Modifier) { 4432 default: 4433 return (isInOut || isOutput || Size <= 64); 4434 case 'q': 4435 // A register of size 32 cannot fit a vector type. 4436 return false; 4437 } 4438 } 4439 } 4440 4441 return true; 4442 } 4443 const char *getClobbers() const override { 4444 // FIXME: Is this really right? 4445 return ""; 4446 } 4447 4448 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4449 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4450 } 4451 4452 int getEHDataRegisterNumber(unsigned RegNo) const override { 4453 if (RegNo == 0) return 0; 4454 if (RegNo == 1) return 1; 4455 return -1; 4456 } 4457 }; 4458 4459 bool ARMTargetInfo::setFPMath(StringRef Name) { 4460 if (Name == "neon") { 4461 FPMath = FP_Neon; 4462 return true; 4463 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4464 Name == "vfp4") { 4465 FPMath = FP_VFP; 4466 return true; 4467 } 4468 return false; 4469 } 4470 4471 const char * const ARMTargetInfo::GCCRegNames[] = { 4472 // Integer registers 4473 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4474 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4475 4476 // Float registers 4477 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4478 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4479 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4480 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4481 4482 // Double registers 4483 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4484 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4485 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4486 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4487 4488 // Quad registers 4489 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4490 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4491 }; 4492 4493 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4494 unsigned &NumNames) const { 4495 Names = GCCRegNames; 4496 NumNames = llvm::array_lengthof(GCCRegNames); 4497 } 4498 4499 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4500 { { "a1" }, "r0" }, 4501 { { "a2" }, "r1" }, 4502 { { "a3" }, "r2" }, 4503 { { "a4" }, "r3" }, 4504 { { "v1" }, "r4" }, 4505 { { "v2" }, "r5" }, 4506 { { "v3" }, "r6" }, 4507 { { "v4" }, "r7" }, 4508 { { "v5" }, "r8" }, 4509 { { "v6", "rfp" }, "r9" }, 4510 { { "sl" }, "r10" }, 4511 { { "fp" }, "r11" }, 4512 { { "ip" }, "r12" }, 4513 { { "r13" }, "sp" }, 4514 { { "r14" }, "lr" }, 4515 { { "r15" }, "pc" }, 4516 // The S, D and Q registers overlap, but aren't really aliases; we 4517 // don't want to substitute one of these for a different-sized one. 4518 }; 4519 4520 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4521 unsigned &NumAliases) const { 4522 Aliases = GCCRegAliases; 4523 NumAliases = llvm::array_lengthof(GCCRegAliases); 4524 } 4525 4526 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4527 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4528 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4529 ALL_LANGUAGES }, 4530 #include "clang/Basic/BuiltinsNEON.def" 4531 4532 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4533 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4534 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4535 ALL_LANGUAGES }, 4536 #include "clang/Basic/BuiltinsARM.def" 4537 }; 4538 4539 class ARMleTargetInfo : public ARMTargetInfo { 4540 public: 4541 ARMleTargetInfo(const llvm::Triple &Triple) 4542 : ARMTargetInfo(Triple, false) { } 4543 virtual void getTargetDefines(const LangOptions &Opts, 4544 MacroBuilder &Builder) const { 4545 Builder.defineMacro("__ARMEL__"); 4546 ARMTargetInfo::getTargetDefines(Opts, Builder); 4547 } 4548 }; 4549 4550 class ARMbeTargetInfo : public ARMTargetInfo { 4551 public: 4552 ARMbeTargetInfo(const llvm::Triple &Triple) 4553 : ARMTargetInfo(Triple, true) { } 4554 virtual void getTargetDefines(const LangOptions &Opts, 4555 MacroBuilder &Builder) const { 4556 Builder.defineMacro("__ARMEB__"); 4557 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4558 ARMTargetInfo::getTargetDefines(Opts, Builder); 4559 } 4560 }; 4561 } // end anonymous namespace. 4562 4563 namespace { 4564 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4565 const llvm::Triple Triple; 4566 public: 4567 WindowsARMTargetInfo(const llvm::Triple &Triple) 4568 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4569 TLSSupported = false; 4570 WCharType = UnsignedShort; 4571 SizeType = UnsignedInt; 4572 UserLabelPrefix = ""; 4573 } 4574 void getVisualStudioDefines(const LangOptions &Opts, 4575 MacroBuilder &Builder) const { 4576 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4577 4578 // FIXME: this is invalid for WindowsCE 4579 Builder.defineMacro("_M_ARM_NT", "1"); 4580 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4581 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4582 4583 assert((Triple.getArch() == llvm::Triple::arm || 4584 Triple.getArch() == llvm::Triple::thumb) && 4585 "invalid architecture for Windows ARM target info"); 4586 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4587 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4588 4589 // TODO map the complete set of values 4590 // 31: VFPv3 40: VFPv4 4591 Builder.defineMacro("_M_ARM_FP", "31"); 4592 } 4593 BuiltinVaListKind getBuiltinVaListKind() const override { 4594 return TargetInfo::CharPtrBuiltinVaList; 4595 } 4596 }; 4597 4598 // Windows ARM + Itanium C++ ABI Target 4599 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4600 public: 4601 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4602 : WindowsARMTargetInfo(Triple) { 4603 TheCXXABI.set(TargetCXXABI::GenericARM); 4604 } 4605 4606 void getTargetDefines(const LangOptions &Opts, 4607 MacroBuilder &Builder) const override { 4608 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4609 4610 if (Opts.MSVCCompat) 4611 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4612 } 4613 }; 4614 4615 // Windows ARM, MS (C++) ABI 4616 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4617 public: 4618 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4619 : WindowsARMTargetInfo(Triple) { 4620 TheCXXABI.set(TargetCXXABI::Microsoft); 4621 } 4622 4623 void getTargetDefines(const LangOptions &Opts, 4624 MacroBuilder &Builder) const override { 4625 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4626 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4627 } 4628 }; 4629 } 4630 4631 4632 namespace { 4633 class DarwinARMTargetInfo : 4634 public DarwinTargetInfo<ARMleTargetInfo> { 4635 protected: 4636 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4637 MacroBuilder &Builder) const override { 4638 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4639 } 4640 4641 public: 4642 DarwinARMTargetInfo(const llvm::Triple &Triple) 4643 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4644 HasAlignMac68kSupport = true; 4645 // iOS always has 64-bit atomic instructions. 4646 // FIXME: This should be based off of the target features in 4647 // ARMleTargetInfo. 4648 MaxAtomicInlineWidth = 64; 4649 4650 // Darwin on iOS uses a variant of the ARM C++ ABI. 4651 TheCXXABI.set(TargetCXXABI::iOS); 4652 } 4653 }; 4654 } // end anonymous namespace. 4655 4656 4657 namespace { 4658 class AArch64TargetInfo : public TargetInfo { 4659 virtual void setDescriptionString() = 0; 4660 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4661 static const char *const GCCRegNames[]; 4662 4663 enum FPUModeEnum { 4664 FPUMode, 4665 NeonMode 4666 }; 4667 4668 unsigned FPU; 4669 unsigned CRC; 4670 unsigned Crypto; 4671 4672 static const Builtin::Info BuiltinInfo[]; 4673 4674 std::string ABI; 4675 4676 public: 4677 AArch64TargetInfo(const llvm::Triple &Triple) 4678 : TargetInfo(Triple), ABI("aapcs") { 4679 4680 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4681 WCharType = SignedInt; 4682 4683 // NetBSD apparently prefers consistency across ARM targets to consistency 4684 // across 64-bit targets. 4685 Int64Type = SignedLongLong; 4686 IntMaxType = SignedLongLong; 4687 } else { 4688 WCharType = UnsignedInt; 4689 Int64Type = SignedLong; 4690 IntMaxType = SignedLong; 4691 } 4692 4693 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4694 MaxVectorAlign = 128; 4695 RegParmMax = 8; 4696 MaxAtomicInlineWidth = 128; 4697 MaxAtomicPromoteWidth = 128; 4698 4699 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4700 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4701 4702 // {} in inline assembly are neon specifiers, not assembly variant 4703 // specifiers. 4704 NoAsmVariants = true; 4705 4706 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4707 // contributes to the alignment of the containing aggregate in the same way 4708 // a plain (non bit-field) member of that type would, without exception for 4709 // zero-sized or anonymous bit-fields." 4710 UseBitFieldTypeAlignment = true; 4711 UseZeroLengthBitfieldAlignment = true; 4712 4713 // AArch64 targets default to using the ARM C++ ABI. 4714 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4715 } 4716 4717 StringRef getABI() const override { return ABI; } 4718 bool setABI(const std::string &Name) override { 4719 if (Name != "aapcs" && Name != "darwinpcs") 4720 return false; 4721 4722 ABI = Name; 4723 return true; 4724 } 4725 4726 bool setCPU(const std::string &Name) override { 4727 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4728 .Case("generic", true) 4729 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4730 .Case("cyclone", true) 4731 .Default(false); 4732 return CPUKnown; 4733 } 4734 4735 virtual void getTargetDefines(const LangOptions &Opts, 4736 MacroBuilder &Builder) const override { 4737 // Target identification. 4738 Builder.defineMacro("__aarch64__"); 4739 4740 // Target properties. 4741 Builder.defineMacro("_LP64"); 4742 Builder.defineMacro("__LP64__"); 4743 4744 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4745 Builder.defineMacro("__ARM_ACLE", "200"); 4746 Builder.defineMacro("__ARM_ARCH", "8"); 4747 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4748 4749 Builder.defineMacro("__ARM_64BIT_STATE"); 4750 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4751 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4752 4753 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4754 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4755 Builder.defineMacro("__ARM_FEATURE_FMA"); 4756 Builder.defineMacro("__ARM_FEATURE_DIV"); 4757 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4758 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4759 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4760 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4761 4762 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4763 4764 // 0xe implies support for half, single and double precision operations. 4765 Builder.defineMacro("__ARM_FP", "0xe"); 4766 4767 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4768 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4769 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4770 4771 if (Opts.FastMath || Opts.FiniteMathOnly) 4772 Builder.defineMacro("__ARM_FP_FAST"); 4773 4774 if (Opts.C99 && !Opts.Freestanding) 4775 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4776 4777 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4778 4779 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4780 Opts.ShortEnums ? "1" : "4"); 4781 4782 if (FPU == NeonMode) { 4783 Builder.defineMacro("__ARM_NEON"); 4784 // 64-bit NEON supports half, single and double precision operations. 4785 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4786 } 4787 4788 if (CRC) 4789 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4790 4791 if (Crypto) 4792 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4793 } 4794 4795 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4796 unsigned &NumRecords) const override { 4797 Records = BuiltinInfo; 4798 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4799 } 4800 4801 bool hasFeature(StringRef Feature) const override { 4802 return Feature == "aarch64" || 4803 Feature == "arm64" || 4804 (Feature == "neon" && FPU == NeonMode); 4805 } 4806 4807 bool handleTargetFeatures(std::vector<std::string> &Features, 4808 DiagnosticsEngine &Diags) override { 4809 FPU = FPUMode; 4810 CRC = 0; 4811 Crypto = 0; 4812 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4813 if (Features[i] == "+neon") 4814 FPU = NeonMode; 4815 if (Features[i] == "+crc") 4816 CRC = 1; 4817 if (Features[i] == "+crypto") 4818 Crypto = 1; 4819 } 4820 4821 setDescriptionString(); 4822 4823 return true; 4824 } 4825 4826 bool isCLZForZeroUndef() const override { return false; } 4827 4828 BuiltinVaListKind getBuiltinVaListKind() const override { 4829 return TargetInfo::AArch64ABIBuiltinVaList; 4830 } 4831 4832 virtual void getGCCRegNames(const char *const *&Names, 4833 unsigned &NumNames) const override; 4834 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4835 unsigned &NumAliases) const override; 4836 4837 virtual bool 4838 validateAsmConstraint(const char *&Name, 4839 TargetInfo::ConstraintInfo &Info) const override { 4840 switch (*Name) { 4841 default: 4842 return false; 4843 case 'w': // Floating point and SIMD registers (V0-V31) 4844 Info.setAllowsRegister(); 4845 return true; 4846 case 'I': // Constant that can be used with an ADD instruction 4847 case 'J': // Constant that can be used with a SUB instruction 4848 case 'K': // Constant that can be used with a 32-bit logical instruction 4849 case 'L': // Constant that can be used with a 64-bit logical instruction 4850 case 'M': // Constant that can be used as a 32-bit MOV immediate 4851 case 'N': // Constant that can be used as a 64-bit MOV immediate 4852 case 'Y': // Floating point constant zero 4853 case 'Z': // Integer constant zero 4854 return true; 4855 case 'Q': // A memory reference with base register and no offset 4856 Info.setAllowsMemory(); 4857 return true; 4858 case 'S': // A symbolic address 4859 Info.setAllowsRegister(); 4860 return true; 4861 case 'U': 4862 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 4863 // Utf: A memory address suitable for ldp/stp in TF mode. 4864 // Usa: An absolute symbolic address. 4865 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 4866 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 4867 case 'z': // Zero register, wzr or xzr 4868 Info.setAllowsRegister(); 4869 return true; 4870 case 'x': // Floating point and SIMD registers (V0-V15) 4871 Info.setAllowsRegister(); 4872 return true; 4873 } 4874 return false; 4875 } 4876 4877 bool 4878 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4879 std::string &SuggestedModifier) const override { 4880 // Strip off constraint modifiers. 4881 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 4882 Constraint = Constraint.substr(1); 4883 4884 switch (Constraint[0]) { 4885 default: 4886 return true; 4887 case 'z': 4888 case 'r': { 4889 switch (Modifier) { 4890 case 'x': 4891 case 'w': 4892 // For now assume that the person knows what they're 4893 // doing with the modifier. 4894 return true; 4895 default: 4896 // By default an 'r' constraint will be in the 'x' 4897 // registers. 4898 if (Size == 64) 4899 return true; 4900 4901 SuggestedModifier = "w"; 4902 return false; 4903 } 4904 } 4905 } 4906 } 4907 4908 const char *getClobbers() const override { return ""; } 4909 4910 int getEHDataRegisterNumber(unsigned RegNo) const override { 4911 if (RegNo == 0) 4912 return 0; 4913 if (RegNo == 1) 4914 return 1; 4915 return -1; 4916 } 4917 }; 4918 4919 const char *const AArch64TargetInfo::GCCRegNames[] = { 4920 // 32-bit Integer registers 4921 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4922 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4923 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4924 4925 // 64-bit Integer registers 4926 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4927 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4928 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4929 4930 // 32-bit floating point regsisters 4931 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4932 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4933 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4934 4935 // 64-bit floating point regsisters 4936 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4937 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4938 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4939 4940 // Vector registers 4941 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4942 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4943 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4944 }; 4945 4946 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 4947 unsigned &NumNames) const { 4948 Names = GCCRegNames; 4949 NumNames = llvm::array_lengthof(GCCRegNames); 4950 } 4951 4952 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 4953 { { "w31" }, "wsp" }, 4954 { { "x29" }, "fp" }, 4955 { { "x30" }, "lr" }, 4956 { { "x31" }, "sp" }, 4957 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4958 // don't want to substitute one of these for a different-sized one. 4959 }; 4960 4961 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4962 unsigned &NumAliases) const { 4963 Aliases = GCCRegAliases; 4964 NumAliases = llvm::array_lengthof(GCCRegAliases); 4965 } 4966 4967 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 4968 #define BUILTIN(ID, TYPE, ATTRS) \ 4969 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4970 #include "clang/Basic/BuiltinsNEON.def" 4971 4972 #define BUILTIN(ID, TYPE, ATTRS) \ 4973 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4974 #include "clang/Basic/BuiltinsAArch64.def" 4975 }; 4976 4977 class AArch64leTargetInfo : public AArch64TargetInfo { 4978 void setDescriptionString() override { 4979 if (getTriple().isOSBinFormatMachO()) 4980 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4981 else 4982 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4983 } 4984 4985 public: 4986 AArch64leTargetInfo(const llvm::Triple &Triple) 4987 : AArch64TargetInfo(Triple) { 4988 BigEndian = false; 4989 } 4990 void getTargetDefines(const LangOptions &Opts, 4991 MacroBuilder &Builder) const override { 4992 Builder.defineMacro("__AARCH64EL__"); 4993 AArch64TargetInfo::getTargetDefines(Opts, Builder); 4994 } 4995 }; 4996 4997 class AArch64beTargetInfo : public AArch64TargetInfo { 4998 void setDescriptionString() override { 4999 assert(!getTriple().isOSBinFormatMachO()); 5000 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5001 } 5002 5003 public: 5004 AArch64beTargetInfo(const llvm::Triple &Triple) 5005 : AArch64TargetInfo(Triple) { } 5006 void getTargetDefines(const LangOptions &Opts, 5007 MacroBuilder &Builder) const override { 5008 Builder.defineMacro("__AARCH64EB__"); 5009 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5010 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5011 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5012 } 5013 }; 5014 } // end anonymous namespace. 5015 5016 namespace { 5017 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5018 protected: 5019 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5020 MacroBuilder &Builder) const override { 5021 Builder.defineMacro("__AARCH64_SIMD__"); 5022 Builder.defineMacro("__ARM64_ARCH_8__"); 5023 Builder.defineMacro("__ARM_NEON__"); 5024 Builder.defineMacro("__LITTLE_ENDIAN__"); 5025 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5026 Builder.defineMacro("__arm64", "1"); 5027 Builder.defineMacro("__arm64__", "1"); 5028 5029 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5030 } 5031 5032 public: 5033 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5034 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5035 Int64Type = SignedLongLong; 5036 WCharType = SignedInt; 5037 UseSignedCharForObjCBool = false; 5038 5039 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5040 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5041 5042 TheCXXABI.set(TargetCXXABI::iOS64); 5043 } 5044 5045 BuiltinVaListKind getBuiltinVaListKind() const override { 5046 return TargetInfo::CharPtrBuiltinVaList; 5047 } 5048 }; 5049 } // end anonymous namespace 5050 5051 namespace { 5052 // Hexagon abstract base class 5053 class HexagonTargetInfo : public TargetInfo { 5054 static const Builtin::Info BuiltinInfo[]; 5055 static const char * const GCCRegNames[]; 5056 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5057 std::string CPU; 5058 public: 5059 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5060 BigEndian = false; 5061 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5062 5063 // {} in inline assembly are packet specifiers, not assembly variant 5064 // specifiers. 5065 NoAsmVariants = true; 5066 } 5067 5068 void getTargetBuiltins(const Builtin::Info *&Records, 5069 unsigned &NumRecords) const override { 5070 Records = BuiltinInfo; 5071 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5072 } 5073 5074 bool validateAsmConstraint(const char *&Name, 5075 TargetInfo::ConstraintInfo &Info) const override { 5076 return true; 5077 } 5078 5079 void getTargetDefines(const LangOptions &Opts, 5080 MacroBuilder &Builder) const override; 5081 5082 bool hasFeature(StringRef Feature) const override { 5083 return Feature == "hexagon"; 5084 } 5085 5086 BuiltinVaListKind getBuiltinVaListKind() const override { 5087 return TargetInfo::CharPtrBuiltinVaList; 5088 } 5089 void getGCCRegNames(const char * const *&Names, 5090 unsigned &NumNames) const override; 5091 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5092 unsigned &NumAliases) const override; 5093 const char *getClobbers() const override { 5094 return ""; 5095 } 5096 5097 static const char *getHexagonCPUSuffix(StringRef Name) { 5098 return llvm::StringSwitch<const char*>(Name) 5099 .Case("hexagonv4", "4") 5100 .Case("hexagonv5", "5") 5101 .Default(nullptr); 5102 } 5103 5104 bool setCPU(const std::string &Name) override { 5105 if (!getHexagonCPUSuffix(Name)) 5106 return false; 5107 5108 CPU = Name; 5109 return true; 5110 } 5111 }; 5112 5113 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5114 MacroBuilder &Builder) const { 5115 Builder.defineMacro("qdsp6"); 5116 Builder.defineMacro("__qdsp6", "1"); 5117 Builder.defineMacro("__qdsp6__", "1"); 5118 5119 Builder.defineMacro("hexagon"); 5120 Builder.defineMacro("__hexagon", "1"); 5121 Builder.defineMacro("__hexagon__", "1"); 5122 5123 if(CPU == "hexagonv1") { 5124 Builder.defineMacro("__HEXAGON_V1__"); 5125 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5126 if(Opts.HexagonQdsp6Compat) { 5127 Builder.defineMacro("__QDSP6_V1__"); 5128 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5129 } 5130 } 5131 else if(CPU == "hexagonv2") { 5132 Builder.defineMacro("__HEXAGON_V2__"); 5133 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5134 if(Opts.HexagonQdsp6Compat) { 5135 Builder.defineMacro("__QDSP6_V2__"); 5136 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5137 } 5138 } 5139 else if(CPU == "hexagonv3") { 5140 Builder.defineMacro("__HEXAGON_V3__"); 5141 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5142 if(Opts.HexagonQdsp6Compat) { 5143 Builder.defineMacro("__QDSP6_V3__"); 5144 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5145 } 5146 } 5147 else if(CPU == "hexagonv4") { 5148 Builder.defineMacro("__HEXAGON_V4__"); 5149 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5150 if(Opts.HexagonQdsp6Compat) { 5151 Builder.defineMacro("__QDSP6_V4__"); 5152 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5153 } 5154 } 5155 else if(CPU == "hexagonv5") { 5156 Builder.defineMacro("__HEXAGON_V5__"); 5157 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5158 if(Opts.HexagonQdsp6Compat) { 5159 Builder.defineMacro("__QDSP6_V5__"); 5160 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5161 } 5162 } 5163 } 5164 5165 const char * const HexagonTargetInfo::GCCRegNames[] = { 5166 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5167 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5168 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5169 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5170 "p0", "p1", "p2", "p3", 5171 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5172 }; 5173 5174 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5175 unsigned &NumNames) const { 5176 Names = GCCRegNames; 5177 NumNames = llvm::array_lengthof(GCCRegNames); 5178 } 5179 5180 5181 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5182 { { "sp" }, "r29" }, 5183 { { "fp" }, "r30" }, 5184 { { "lr" }, "r31" }, 5185 }; 5186 5187 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5188 unsigned &NumAliases) const { 5189 Aliases = GCCRegAliases; 5190 NumAliases = llvm::array_lengthof(GCCRegAliases); 5191 } 5192 5193 5194 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5195 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5196 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5197 ALL_LANGUAGES }, 5198 #include "clang/Basic/BuiltinsHexagon.def" 5199 }; 5200 } 5201 5202 5203 namespace { 5204 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5205 class SparcTargetInfo : public TargetInfo { 5206 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5207 static const char * const GCCRegNames[]; 5208 bool SoftFloat; 5209 public: 5210 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 5211 5212 bool handleTargetFeatures(std::vector<std::string> &Features, 5213 DiagnosticsEngine &Diags) override { 5214 SoftFloat = false; 5215 for (unsigned i = 0, e = Features.size(); i != e; ++i) 5216 if (Features[i] == "+soft-float") 5217 SoftFloat = true; 5218 return true; 5219 } 5220 void getTargetDefines(const LangOptions &Opts, 5221 MacroBuilder &Builder) const override { 5222 DefineStd(Builder, "sparc", Opts); 5223 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5224 5225 if (SoftFloat) 5226 Builder.defineMacro("SOFT_FLOAT", "1"); 5227 } 5228 5229 bool hasFeature(StringRef Feature) const override { 5230 return llvm::StringSwitch<bool>(Feature) 5231 .Case("softfloat", SoftFloat) 5232 .Case("sparc", true) 5233 .Default(false); 5234 } 5235 5236 void getTargetBuiltins(const Builtin::Info *&Records, 5237 unsigned &NumRecords) const override { 5238 // FIXME: Implement! 5239 } 5240 BuiltinVaListKind getBuiltinVaListKind() const override { 5241 return TargetInfo::VoidPtrBuiltinVaList; 5242 } 5243 void getGCCRegNames(const char * const *&Names, 5244 unsigned &NumNames) const override; 5245 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5246 unsigned &NumAliases) const override; 5247 bool validateAsmConstraint(const char *&Name, 5248 TargetInfo::ConstraintInfo &info) const override { 5249 // FIXME: Implement! 5250 switch (*Name) { 5251 case 'I': // Signed 13-bit constant 5252 case 'J': // Zero 5253 case 'K': // 32-bit constant with the low 12 bits clear 5254 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5255 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5256 case 'N': // Same as 'K' but zext (required for SIMode) 5257 case 'O': // The constant 4096 5258 return true; 5259 } 5260 return false; 5261 } 5262 const char *getClobbers() const override { 5263 // FIXME: Implement! 5264 return ""; 5265 } 5266 }; 5267 5268 const char * const SparcTargetInfo::GCCRegNames[] = { 5269 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5270 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5271 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5272 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5273 }; 5274 5275 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5276 unsigned &NumNames) const { 5277 Names = GCCRegNames; 5278 NumNames = llvm::array_lengthof(GCCRegNames); 5279 } 5280 5281 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5282 { { "g0" }, "r0" }, 5283 { { "g1" }, "r1" }, 5284 { { "g2" }, "r2" }, 5285 { { "g3" }, "r3" }, 5286 { { "g4" }, "r4" }, 5287 { { "g5" }, "r5" }, 5288 { { "g6" }, "r6" }, 5289 { { "g7" }, "r7" }, 5290 { { "o0" }, "r8" }, 5291 { { "o1" }, "r9" }, 5292 { { "o2" }, "r10" }, 5293 { { "o3" }, "r11" }, 5294 { { "o4" }, "r12" }, 5295 { { "o5" }, "r13" }, 5296 { { "o6", "sp" }, "r14" }, 5297 { { "o7" }, "r15" }, 5298 { { "l0" }, "r16" }, 5299 { { "l1" }, "r17" }, 5300 { { "l2" }, "r18" }, 5301 { { "l3" }, "r19" }, 5302 { { "l4" }, "r20" }, 5303 { { "l5" }, "r21" }, 5304 { { "l6" }, "r22" }, 5305 { { "l7" }, "r23" }, 5306 { { "i0" }, "r24" }, 5307 { { "i1" }, "r25" }, 5308 { { "i2" }, "r26" }, 5309 { { "i3" }, "r27" }, 5310 { { "i4" }, "r28" }, 5311 { { "i5" }, "r29" }, 5312 { { "i6", "fp" }, "r30" }, 5313 { { "i7" }, "r31" }, 5314 }; 5315 5316 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5317 unsigned &NumAliases) const { 5318 Aliases = GCCRegAliases; 5319 NumAliases = llvm::array_lengthof(GCCRegAliases); 5320 } 5321 5322 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5323 class SparcV8TargetInfo : public SparcTargetInfo { 5324 public: 5325 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5326 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5327 } 5328 5329 void getTargetDefines(const LangOptions &Opts, 5330 MacroBuilder &Builder) const override { 5331 SparcTargetInfo::getTargetDefines(Opts, Builder); 5332 Builder.defineMacro("__sparcv8"); 5333 } 5334 }; 5335 5336 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5337 class SparcV9TargetInfo : public SparcTargetInfo { 5338 public: 5339 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5340 // FIXME: Support Sparc quad-precision long double? 5341 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5342 // This is an LP64 platform. 5343 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5344 5345 // OpenBSD uses long long for int64_t and intmax_t. 5346 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5347 IntMaxType = SignedLongLong; 5348 else 5349 IntMaxType = SignedLong; 5350 Int64Type = IntMaxType; 5351 5352 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5353 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5354 LongDoubleWidth = 128; 5355 LongDoubleAlign = 128; 5356 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5357 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5358 } 5359 5360 void getTargetDefines(const LangOptions &Opts, 5361 MacroBuilder &Builder) const override { 5362 SparcTargetInfo::getTargetDefines(Opts, Builder); 5363 Builder.defineMacro("__sparcv9"); 5364 Builder.defineMacro("__arch64__"); 5365 // Solaris doesn't need these variants, but the BSDs do. 5366 if (getTriple().getOS() != llvm::Triple::Solaris) { 5367 Builder.defineMacro("__sparc64__"); 5368 Builder.defineMacro("__sparc_v9__"); 5369 Builder.defineMacro("__sparcv9__"); 5370 } 5371 } 5372 5373 bool setCPU(const std::string &Name) override { 5374 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5375 .Case("v9", true) 5376 .Case("ultrasparc", true) 5377 .Case("ultrasparc3", true) 5378 .Case("niagara", true) 5379 .Case("niagara2", true) 5380 .Case("niagara3", true) 5381 .Case("niagara4", true) 5382 .Default(false); 5383 5384 // No need to store the CPU yet. There aren't any CPU-specific 5385 // macros to define. 5386 return CPUKnown; 5387 } 5388 }; 5389 5390 } // end anonymous namespace. 5391 5392 namespace { 5393 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5394 public: 5395 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5396 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5397 SizeType = UnsignedInt; 5398 PtrDiffType = SignedInt; 5399 } 5400 }; 5401 } // end anonymous namespace. 5402 5403 namespace { 5404 class SystemZTargetInfo : public TargetInfo { 5405 static const char *const GCCRegNames[]; 5406 5407 public: 5408 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5409 TLSSupported = true; 5410 IntWidth = IntAlign = 32; 5411 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5412 PointerWidth = PointerAlign = 64; 5413 LongDoubleWidth = 128; 5414 LongDoubleAlign = 64; 5415 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5416 MinGlobalAlign = 16; 5417 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5418 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5419 } 5420 void getTargetDefines(const LangOptions &Opts, 5421 MacroBuilder &Builder) const override { 5422 Builder.defineMacro("__s390__"); 5423 Builder.defineMacro("__s390x__"); 5424 Builder.defineMacro("__zarch__"); 5425 Builder.defineMacro("__LONG_DOUBLE_128__"); 5426 } 5427 void getTargetBuiltins(const Builtin::Info *&Records, 5428 unsigned &NumRecords) const override { 5429 // FIXME: Implement. 5430 Records = nullptr; 5431 NumRecords = 0; 5432 } 5433 5434 void getGCCRegNames(const char *const *&Names, 5435 unsigned &NumNames) const override; 5436 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5437 unsigned &NumAliases) const override { 5438 // No aliases. 5439 Aliases = nullptr; 5440 NumAliases = 0; 5441 } 5442 bool validateAsmConstraint(const char *&Name, 5443 TargetInfo::ConstraintInfo &info) const override; 5444 const char *getClobbers() const override { 5445 // FIXME: Is this really right? 5446 return ""; 5447 } 5448 BuiltinVaListKind getBuiltinVaListKind() const override { 5449 return TargetInfo::SystemZBuiltinVaList; 5450 } 5451 bool setCPU(const std::string &Name) override { 5452 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5453 .Case("z10", true) 5454 .Case("z196", true) 5455 .Case("zEC12", true) 5456 .Default(false); 5457 5458 // No need to store the CPU yet. There aren't any CPU-specific 5459 // macros to define. 5460 return CPUKnown; 5461 } 5462 }; 5463 5464 const char *const SystemZTargetInfo::GCCRegNames[] = { 5465 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5466 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5467 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5468 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5469 }; 5470 5471 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5472 unsigned &NumNames) const { 5473 Names = GCCRegNames; 5474 NumNames = llvm::array_lengthof(GCCRegNames); 5475 } 5476 5477 bool SystemZTargetInfo:: 5478 validateAsmConstraint(const char *&Name, 5479 TargetInfo::ConstraintInfo &Info) const { 5480 switch (*Name) { 5481 default: 5482 return false; 5483 5484 case 'a': // Address register 5485 case 'd': // Data register (equivalent to 'r') 5486 case 'f': // Floating-point register 5487 Info.setAllowsRegister(); 5488 return true; 5489 5490 case 'I': // Unsigned 8-bit constant 5491 case 'J': // Unsigned 12-bit constant 5492 case 'K': // Signed 16-bit constant 5493 case 'L': // Signed 20-bit displacement (on all targets we support) 5494 case 'M': // 0x7fffffff 5495 return true; 5496 5497 case 'Q': // Memory with base and unsigned 12-bit displacement 5498 case 'R': // Likewise, plus an index 5499 case 'S': // Memory with base and signed 20-bit displacement 5500 case 'T': // Likewise, plus an index 5501 Info.setAllowsMemory(); 5502 return true; 5503 } 5504 } 5505 } 5506 5507 namespace { 5508 class MSP430TargetInfo : public TargetInfo { 5509 static const char * const GCCRegNames[]; 5510 public: 5511 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5512 BigEndian = false; 5513 TLSSupported = false; 5514 IntWidth = 16; IntAlign = 16; 5515 LongWidth = 32; LongLongWidth = 64; 5516 LongAlign = LongLongAlign = 16; 5517 PointerWidth = 16; PointerAlign = 16; 5518 SuitableAlign = 16; 5519 SizeType = UnsignedInt; 5520 IntMaxType = SignedLongLong; 5521 IntPtrType = SignedInt; 5522 PtrDiffType = SignedInt; 5523 SigAtomicType = SignedLong; 5524 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5525 } 5526 void getTargetDefines(const LangOptions &Opts, 5527 MacroBuilder &Builder) const override { 5528 Builder.defineMacro("MSP430"); 5529 Builder.defineMacro("__MSP430__"); 5530 // FIXME: defines for different 'flavours' of MCU 5531 } 5532 void getTargetBuiltins(const Builtin::Info *&Records, 5533 unsigned &NumRecords) const override { 5534 // FIXME: Implement. 5535 Records = nullptr; 5536 NumRecords = 0; 5537 } 5538 bool hasFeature(StringRef Feature) const override { 5539 return Feature == "msp430"; 5540 } 5541 void getGCCRegNames(const char * const *&Names, 5542 unsigned &NumNames) const override; 5543 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5544 unsigned &NumAliases) const override { 5545 // No aliases. 5546 Aliases = nullptr; 5547 NumAliases = 0; 5548 } 5549 bool 5550 validateAsmConstraint(const char *&Name, 5551 TargetInfo::ConstraintInfo &info) const override { 5552 // FIXME: implement 5553 switch (*Name) { 5554 case 'K': // the constant 1 5555 case 'L': // constant -1^20 .. 1^19 5556 case 'M': // constant 1-4: 5557 return true; 5558 } 5559 // No target constraints for now. 5560 return false; 5561 } 5562 const char *getClobbers() const override { 5563 // FIXME: Is this really right? 5564 return ""; 5565 } 5566 BuiltinVaListKind getBuiltinVaListKind() const override { 5567 // FIXME: implement 5568 return TargetInfo::CharPtrBuiltinVaList; 5569 } 5570 }; 5571 5572 const char * const MSP430TargetInfo::GCCRegNames[] = { 5573 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5574 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5575 }; 5576 5577 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5578 unsigned &NumNames) const { 5579 Names = GCCRegNames; 5580 NumNames = llvm::array_lengthof(GCCRegNames); 5581 } 5582 } 5583 5584 namespace { 5585 5586 // LLVM and Clang cannot be used directly to output native binaries for 5587 // target, but is used to compile C code to llvm bitcode with correct 5588 // type and alignment information. 5589 // 5590 // TCE uses the llvm bitcode as input and uses it for generating customized 5591 // target processor and program binary. TCE co-design environment is 5592 // publicly available in http://tce.cs.tut.fi 5593 5594 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5595 3, // opencl_global 5596 4, // opencl_local 5597 5, // opencl_constant 5598 // FIXME: generic has to be added to the target 5599 0, // opencl_generic 5600 0, // cuda_device 5601 0, // cuda_constant 5602 0 // cuda_shared 5603 }; 5604 5605 class TCETargetInfo : public TargetInfo{ 5606 public: 5607 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5608 TLSSupported = false; 5609 IntWidth = 32; 5610 LongWidth = LongLongWidth = 32; 5611 PointerWidth = 32; 5612 IntAlign = 32; 5613 LongAlign = LongLongAlign = 32; 5614 PointerAlign = 32; 5615 SuitableAlign = 32; 5616 SizeType = UnsignedInt; 5617 IntMaxType = SignedLong; 5618 IntPtrType = SignedInt; 5619 PtrDiffType = SignedInt; 5620 FloatWidth = 32; 5621 FloatAlign = 32; 5622 DoubleWidth = 32; 5623 DoubleAlign = 32; 5624 LongDoubleWidth = 32; 5625 LongDoubleAlign = 32; 5626 FloatFormat = &llvm::APFloat::IEEEsingle; 5627 DoubleFormat = &llvm::APFloat::IEEEsingle; 5628 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5629 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5630 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5631 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5632 UseAddrSpaceMapMangling = true; 5633 } 5634 5635 void getTargetDefines(const LangOptions &Opts, 5636 MacroBuilder &Builder) const override { 5637 DefineStd(Builder, "tce", Opts); 5638 Builder.defineMacro("__TCE__"); 5639 Builder.defineMacro("__TCE_V1__"); 5640 } 5641 bool hasFeature(StringRef Feature) const override { 5642 return Feature == "tce"; 5643 } 5644 5645 void getTargetBuiltins(const Builtin::Info *&Records, 5646 unsigned &NumRecords) const override {} 5647 const char *getClobbers() const override { 5648 return ""; 5649 } 5650 BuiltinVaListKind getBuiltinVaListKind() const override { 5651 return TargetInfo::VoidPtrBuiltinVaList; 5652 } 5653 void getGCCRegNames(const char * const *&Names, 5654 unsigned &NumNames) const override {} 5655 bool validateAsmConstraint(const char *&Name, 5656 TargetInfo::ConstraintInfo &info) const override{ 5657 return true; 5658 } 5659 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5660 unsigned &NumAliases) const override {} 5661 }; 5662 } 5663 5664 namespace { 5665 class MipsTargetInfoBase : public TargetInfo { 5666 virtual void setDescriptionString() = 0; 5667 5668 static const Builtin::Info BuiltinInfo[]; 5669 std::string CPU; 5670 bool IsMips16; 5671 bool IsMicromips; 5672 bool IsNan2008; 5673 bool IsSingleFloat; 5674 enum MipsFloatABI { 5675 HardFloat, SoftFloat 5676 } FloatABI; 5677 enum DspRevEnum { 5678 NoDSP, DSP1, DSP2 5679 } DspRev; 5680 bool HasMSA; 5681 5682 protected: 5683 bool HasFP64; 5684 std::string ABI; 5685 5686 public: 5687 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5688 const std::string &CPUStr) 5689 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5690 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5691 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5692 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5693 } 5694 5695 bool isNaN2008Default() const { 5696 return CPU == "mips32r6" || CPU == "mips64r6"; 5697 } 5698 5699 bool isFP64Default() const { 5700 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5701 } 5702 5703 bool isNan2008() const override { 5704 return IsNan2008; 5705 } 5706 5707 StringRef getABI() const override { return ABI; } 5708 bool setCPU(const std::string &Name) override { 5709 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5710 getTriple().getArch() == llvm::Triple::mipsel; 5711 CPU = Name; 5712 return llvm::StringSwitch<bool>(Name) 5713 .Case("mips1", IsMips32) 5714 .Case("mips2", IsMips32) 5715 .Case("mips3", true) 5716 .Case("mips4", true) 5717 .Case("mips5", true) 5718 .Case("mips32", IsMips32) 5719 .Case("mips32r2", IsMips32) 5720 .Case("mips32r3", IsMips32) 5721 .Case("mips32r5", IsMips32) 5722 .Case("mips32r6", IsMips32) 5723 .Case("mips64", true) 5724 .Case("mips64r2", true) 5725 .Case("mips64r3", true) 5726 .Case("mips64r5", true) 5727 .Case("mips64r6", true) 5728 .Case("octeon", true) 5729 .Default(false); 5730 } 5731 const std::string& getCPU() const { return CPU; } 5732 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5733 if (CPU == "octeon") 5734 Features["mips64r2"] = Features["cnmips"] = true; 5735 else 5736 Features[CPU] = true; 5737 } 5738 5739 void getTargetDefines(const LangOptions &Opts, 5740 MacroBuilder &Builder) const override { 5741 Builder.defineMacro("__mips__"); 5742 Builder.defineMacro("_mips"); 5743 if (Opts.GNUMode) 5744 Builder.defineMacro("mips"); 5745 5746 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5747 5748 switch (FloatABI) { 5749 case HardFloat: 5750 Builder.defineMacro("__mips_hard_float", Twine(1)); 5751 break; 5752 case SoftFloat: 5753 Builder.defineMacro("__mips_soft_float", Twine(1)); 5754 break; 5755 } 5756 5757 if (IsSingleFloat) 5758 Builder.defineMacro("__mips_single_float", Twine(1)); 5759 5760 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5761 Builder.defineMacro("_MIPS_FPSET", 5762 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5763 5764 if (IsMips16) 5765 Builder.defineMacro("__mips16", Twine(1)); 5766 5767 if (IsMicromips) 5768 Builder.defineMacro("__mips_micromips", Twine(1)); 5769 5770 if (IsNan2008) 5771 Builder.defineMacro("__mips_nan2008", Twine(1)); 5772 5773 switch (DspRev) { 5774 default: 5775 break; 5776 case DSP1: 5777 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5778 Builder.defineMacro("__mips_dsp", Twine(1)); 5779 break; 5780 case DSP2: 5781 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5782 Builder.defineMacro("__mips_dspr2", Twine(1)); 5783 Builder.defineMacro("__mips_dsp", Twine(1)); 5784 break; 5785 } 5786 5787 if (HasMSA) 5788 Builder.defineMacro("__mips_msa", Twine(1)); 5789 5790 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5791 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5792 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5793 5794 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5795 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5796 } 5797 5798 void getTargetBuiltins(const Builtin::Info *&Records, 5799 unsigned &NumRecords) const override { 5800 Records = BuiltinInfo; 5801 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5802 } 5803 bool hasFeature(StringRef Feature) const override { 5804 return llvm::StringSwitch<bool>(Feature) 5805 .Case("mips", true) 5806 .Case("fp64", HasFP64) 5807 .Default(false); 5808 } 5809 BuiltinVaListKind getBuiltinVaListKind() const override { 5810 return TargetInfo::VoidPtrBuiltinVaList; 5811 } 5812 void getGCCRegNames(const char * const *&Names, 5813 unsigned &NumNames) const override { 5814 static const char *const GCCRegNames[] = { 5815 // CPU register names 5816 // Must match second column of GCCRegAliases 5817 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5818 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5819 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5820 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5821 // Floating point register names 5822 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5823 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5824 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5825 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5826 // Hi/lo and condition register names 5827 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5828 "$fcc5","$fcc6","$fcc7", 5829 // MSA register names 5830 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5831 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5832 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5833 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5834 // MSA control register names 5835 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5836 "$msarequest", "$msamap", "$msaunmap" 5837 }; 5838 Names = GCCRegNames; 5839 NumNames = llvm::array_lengthof(GCCRegNames); 5840 } 5841 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5842 unsigned &NumAliases) const override = 0; 5843 bool validateAsmConstraint(const char *&Name, 5844 TargetInfo::ConstraintInfo &Info) const override { 5845 switch (*Name) { 5846 default: 5847 return false; 5848 case 'r': // CPU registers. 5849 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5850 case 'y': // Equivalent to "r", backward compatibility only. 5851 case 'f': // floating-point registers. 5852 case 'c': // $25 for indirect jumps 5853 case 'l': // lo register 5854 case 'x': // hilo register pair 5855 Info.setAllowsRegister(); 5856 return true; 5857 case 'I': // Signed 16-bit constant 5858 case 'J': // Integer 0 5859 case 'K': // Unsigned 16-bit constant 5860 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 5861 case 'M': // Constants not loadable via lui, addiu, or ori 5862 case 'N': // Constant -1 to -65535 5863 case 'O': // A signed 15-bit constant 5864 case 'P': // A constant between 1 go 65535 5865 return true; 5866 case 'R': // An address that can be used in a non-macro load or store 5867 Info.setAllowsMemory(); 5868 return true; 5869 } 5870 } 5871 5872 const char *getClobbers() const override { 5873 // In GCC, $1 is not widely used in generated code (it's used only in a few 5874 // specific situations), so there is no real need for users to add it to 5875 // the clobbers list if they want to use it in their inline assembly code. 5876 // 5877 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 5878 // code generation, so using it in inline assembly without adding it to the 5879 // clobbers list can cause conflicts between the inline assembly code and 5880 // the surrounding generated code. 5881 // 5882 // Another problem is that LLVM is allowed to choose $1 for inline assembly 5883 // operands, which will conflict with the ".set at" assembler option (which 5884 // we use only for inline assembly, in order to maintain compatibility with 5885 // GCC) and will also conflict with the user's usage of $1. 5886 // 5887 // The easiest way to avoid these conflicts and keep $1 as an allocatable 5888 // register for generated code is to automatically clobber $1 for all inline 5889 // assembly code. 5890 // 5891 // FIXME: We should automatically clobber $1 only for inline assembly code 5892 // which actually uses it. This would allow LLVM to use $1 for inline 5893 // assembly operands if the user's assembly code doesn't use it. 5894 return "~{$1}"; 5895 } 5896 5897 bool handleTargetFeatures(std::vector<std::string> &Features, 5898 DiagnosticsEngine &Diags) override { 5899 IsMips16 = false; 5900 IsMicromips = false; 5901 IsNan2008 = isNaN2008Default(); 5902 IsSingleFloat = false; 5903 FloatABI = HardFloat; 5904 DspRev = NoDSP; 5905 HasFP64 = isFP64Default(); 5906 5907 for (std::vector<std::string>::iterator it = Features.begin(), 5908 ie = Features.end(); it != ie; ++it) { 5909 if (*it == "+single-float") 5910 IsSingleFloat = true; 5911 else if (*it == "+soft-float") 5912 FloatABI = SoftFloat; 5913 else if (*it == "+mips16") 5914 IsMips16 = true; 5915 else if (*it == "+micromips") 5916 IsMicromips = true; 5917 else if (*it == "+dsp") 5918 DspRev = std::max(DspRev, DSP1); 5919 else if (*it == "+dspr2") 5920 DspRev = std::max(DspRev, DSP2); 5921 else if (*it == "+msa") 5922 HasMSA = true; 5923 else if (*it == "+fp64") 5924 HasFP64 = true; 5925 else if (*it == "-fp64") 5926 HasFP64 = false; 5927 else if (*it == "+nan2008") 5928 IsNan2008 = true; 5929 else if (*it == "-nan2008") 5930 IsNan2008 = false; 5931 } 5932 5933 // Remove front-end specific options. 5934 std::vector<std::string>::iterator it = 5935 std::find(Features.begin(), Features.end(), "+soft-float"); 5936 if (it != Features.end()) 5937 Features.erase(it); 5938 5939 setDescriptionString(); 5940 5941 return true; 5942 } 5943 5944 int getEHDataRegisterNumber(unsigned RegNo) const override { 5945 if (RegNo == 0) return 4; 5946 if (RegNo == 1) return 5; 5947 return -1; 5948 } 5949 5950 bool isCLZForZeroUndef() const override { return false; } 5951 }; 5952 5953 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5954 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5955 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5956 ALL_LANGUAGES }, 5957 #include "clang/Basic/BuiltinsMips.def" 5958 }; 5959 5960 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5961 public: 5962 Mips32TargetInfoBase(const llvm::Triple &Triple) 5963 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5964 SizeType = UnsignedInt; 5965 PtrDiffType = SignedInt; 5966 Int64Type = SignedLongLong; 5967 IntMaxType = Int64Type; 5968 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5969 } 5970 bool setABI(const std::string &Name) override { 5971 if (Name == "o32" || Name == "eabi") { 5972 ABI = Name; 5973 return true; 5974 } 5975 return false; 5976 } 5977 void getTargetDefines(const LangOptions &Opts, 5978 MacroBuilder &Builder) const override { 5979 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5980 5981 Builder.defineMacro("__mips", "32"); 5982 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 5983 5984 const std::string& CPUStr = getCPU(); 5985 if (CPUStr == "mips32") 5986 Builder.defineMacro("__mips_isa_rev", "1"); 5987 else if (CPUStr == "mips32r2") 5988 Builder.defineMacro("__mips_isa_rev", "2"); 5989 else if (CPUStr == "mips32r3") 5990 Builder.defineMacro("__mips_isa_rev", "3"); 5991 else if (CPUStr == "mips32r5") 5992 Builder.defineMacro("__mips_isa_rev", "5"); 5993 else if (CPUStr == "mips32r6") 5994 Builder.defineMacro("__mips_isa_rev", "6"); 5995 5996 if (ABI == "o32") { 5997 Builder.defineMacro("__mips_o32"); 5998 Builder.defineMacro("_ABIO32", "1"); 5999 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6000 } 6001 else if (ABI == "eabi") 6002 Builder.defineMacro("__mips_eabi"); 6003 else 6004 llvm_unreachable("Invalid ABI for Mips32."); 6005 } 6006 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6007 unsigned &NumAliases) const override { 6008 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6009 { { "at" }, "$1" }, 6010 { { "v0" }, "$2" }, 6011 { { "v1" }, "$3" }, 6012 { { "a0" }, "$4" }, 6013 { { "a1" }, "$5" }, 6014 { { "a2" }, "$6" }, 6015 { { "a3" }, "$7" }, 6016 { { "t0" }, "$8" }, 6017 { { "t1" }, "$9" }, 6018 { { "t2" }, "$10" }, 6019 { { "t3" }, "$11" }, 6020 { { "t4" }, "$12" }, 6021 { { "t5" }, "$13" }, 6022 { { "t6" }, "$14" }, 6023 { { "t7" }, "$15" }, 6024 { { "s0" }, "$16" }, 6025 { { "s1" }, "$17" }, 6026 { { "s2" }, "$18" }, 6027 { { "s3" }, "$19" }, 6028 { { "s4" }, "$20" }, 6029 { { "s5" }, "$21" }, 6030 { { "s6" }, "$22" }, 6031 { { "s7" }, "$23" }, 6032 { { "t8" }, "$24" }, 6033 { { "t9" }, "$25" }, 6034 { { "k0" }, "$26" }, 6035 { { "k1" }, "$27" }, 6036 { { "gp" }, "$28" }, 6037 { { "sp","$sp" }, "$29" }, 6038 { { "fp","$fp" }, "$30" }, 6039 { { "ra" }, "$31" } 6040 }; 6041 Aliases = GCCRegAliases; 6042 NumAliases = llvm::array_lengthof(GCCRegAliases); 6043 } 6044 }; 6045 6046 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6047 void setDescriptionString() override { 6048 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6049 } 6050 6051 public: 6052 Mips32EBTargetInfo(const llvm::Triple &Triple) 6053 : Mips32TargetInfoBase(Triple) { 6054 } 6055 void getTargetDefines(const LangOptions &Opts, 6056 MacroBuilder &Builder) const override { 6057 DefineStd(Builder, "MIPSEB", Opts); 6058 Builder.defineMacro("_MIPSEB"); 6059 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6060 } 6061 }; 6062 6063 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6064 void setDescriptionString() override { 6065 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6066 } 6067 6068 public: 6069 Mips32ELTargetInfo(const llvm::Triple &Triple) 6070 : Mips32TargetInfoBase(Triple) { 6071 BigEndian = false; 6072 } 6073 void getTargetDefines(const LangOptions &Opts, 6074 MacroBuilder &Builder) const override { 6075 DefineStd(Builder, "MIPSEL", Opts); 6076 Builder.defineMacro("_MIPSEL"); 6077 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6078 } 6079 }; 6080 6081 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6082 public: 6083 Mips64TargetInfoBase(const llvm::Triple &Triple) 6084 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6085 LongDoubleWidth = LongDoubleAlign = 128; 6086 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6087 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6088 LongDoubleWidth = LongDoubleAlign = 64; 6089 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6090 } 6091 setN64ABITypes(); 6092 SuitableAlign = 128; 6093 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6094 } 6095 6096 void setN64ABITypes() { 6097 LongWidth = LongAlign = 64; 6098 PointerWidth = PointerAlign = 64; 6099 SizeType = UnsignedLong; 6100 PtrDiffType = SignedLong; 6101 Int64Type = SignedLong; 6102 IntMaxType = Int64Type; 6103 } 6104 6105 void setN32ABITypes() { 6106 LongWidth = LongAlign = 32; 6107 PointerWidth = PointerAlign = 32; 6108 SizeType = UnsignedInt; 6109 PtrDiffType = SignedInt; 6110 Int64Type = SignedLongLong; 6111 IntMaxType = Int64Type; 6112 } 6113 6114 bool setABI(const std::string &Name) override { 6115 if (Name == "n32") { 6116 setN32ABITypes(); 6117 ABI = Name; 6118 return true; 6119 } 6120 if (Name == "n64") { 6121 setN64ABITypes(); 6122 ABI = Name; 6123 return true; 6124 } 6125 return false; 6126 } 6127 6128 void getTargetDefines(const LangOptions &Opts, 6129 MacroBuilder &Builder) const override { 6130 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6131 6132 Builder.defineMacro("__mips", "64"); 6133 Builder.defineMacro("__mips64"); 6134 Builder.defineMacro("__mips64__"); 6135 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6136 6137 const std::string& CPUStr = getCPU(); 6138 if (CPUStr == "mips64") 6139 Builder.defineMacro("__mips_isa_rev", "1"); 6140 else if (CPUStr == "mips64r2") 6141 Builder.defineMacro("__mips_isa_rev", "2"); 6142 else if (CPUStr == "mips64r3") 6143 Builder.defineMacro("__mips_isa_rev", "3"); 6144 else if (CPUStr == "mips64r5") 6145 Builder.defineMacro("__mips_isa_rev", "5"); 6146 else if (CPUStr == "mips64r6") 6147 Builder.defineMacro("__mips_isa_rev", "6"); 6148 6149 if (ABI == "n32") { 6150 Builder.defineMacro("__mips_n32"); 6151 Builder.defineMacro("_ABIN32", "2"); 6152 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6153 } 6154 else if (ABI == "n64") { 6155 Builder.defineMacro("__mips_n64"); 6156 Builder.defineMacro("_ABI64", "3"); 6157 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6158 } 6159 else 6160 llvm_unreachable("Invalid ABI for Mips64."); 6161 } 6162 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6163 unsigned &NumAliases) const override { 6164 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6165 { { "at" }, "$1" }, 6166 { { "v0" }, "$2" }, 6167 { { "v1" }, "$3" }, 6168 { { "a0" }, "$4" }, 6169 { { "a1" }, "$5" }, 6170 { { "a2" }, "$6" }, 6171 { { "a3" }, "$7" }, 6172 { { "a4" }, "$8" }, 6173 { { "a5" }, "$9" }, 6174 { { "a6" }, "$10" }, 6175 { { "a7" }, "$11" }, 6176 { { "t0" }, "$12" }, 6177 { { "t1" }, "$13" }, 6178 { { "t2" }, "$14" }, 6179 { { "t3" }, "$15" }, 6180 { { "s0" }, "$16" }, 6181 { { "s1" }, "$17" }, 6182 { { "s2" }, "$18" }, 6183 { { "s3" }, "$19" }, 6184 { { "s4" }, "$20" }, 6185 { { "s5" }, "$21" }, 6186 { { "s6" }, "$22" }, 6187 { { "s7" }, "$23" }, 6188 { { "t8" }, "$24" }, 6189 { { "t9" }, "$25" }, 6190 { { "k0" }, "$26" }, 6191 { { "k1" }, "$27" }, 6192 { { "gp" }, "$28" }, 6193 { { "sp","$sp" }, "$29" }, 6194 { { "fp","$fp" }, "$30" }, 6195 { { "ra" }, "$31" } 6196 }; 6197 Aliases = GCCRegAliases; 6198 NumAliases = llvm::array_lengthof(GCCRegAliases); 6199 } 6200 6201 bool hasInt128Type() const override { return true; } 6202 }; 6203 6204 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6205 void setDescriptionString() override { 6206 if (ABI == "n32") 6207 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6208 else 6209 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6210 6211 } 6212 6213 public: 6214 Mips64EBTargetInfo(const llvm::Triple &Triple) 6215 : Mips64TargetInfoBase(Triple) {} 6216 void getTargetDefines(const LangOptions &Opts, 6217 MacroBuilder &Builder) const override { 6218 DefineStd(Builder, "MIPSEB", Opts); 6219 Builder.defineMacro("_MIPSEB"); 6220 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6221 } 6222 }; 6223 6224 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6225 void setDescriptionString() override { 6226 if (ABI == "n32") 6227 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6228 else 6229 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6230 } 6231 public: 6232 Mips64ELTargetInfo(const llvm::Triple &Triple) 6233 : Mips64TargetInfoBase(Triple) { 6234 // Default ABI is n64. 6235 BigEndian = false; 6236 } 6237 void getTargetDefines(const LangOptions &Opts, 6238 MacroBuilder &Builder) const override { 6239 DefineStd(Builder, "MIPSEL", Opts); 6240 Builder.defineMacro("_MIPSEL"); 6241 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6242 } 6243 }; 6244 } // end anonymous namespace. 6245 6246 namespace { 6247 class PNaClTargetInfo : public TargetInfo { 6248 public: 6249 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6250 BigEndian = false; 6251 this->UserLabelPrefix = ""; 6252 this->LongAlign = 32; 6253 this->LongWidth = 32; 6254 this->PointerAlign = 32; 6255 this->PointerWidth = 32; 6256 this->IntMaxType = TargetInfo::SignedLongLong; 6257 this->Int64Type = TargetInfo::SignedLongLong; 6258 this->DoubleAlign = 64; 6259 this->LongDoubleWidth = 64; 6260 this->LongDoubleAlign = 64; 6261 this->SizeType = TargetInfo::UnsignedInt; 6262 this->PtrDiffType = TargetInfo::SignedInt; 6263 this->IntPtrType = TargetInfo::SignedInt; 6264 this->RegParmMax = 0; // Disallow regparm 6265 } 6266 6267 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6268 } 6269 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6270 Builder.defineMacro("__le32__"); 6271 Builder.defineMacro("__pnacl__"); 6272 } 6273 void getTargetDefines(const LangOptions &Opts, 6274 MacroBuilder &Builder) const override { 6275 getArchDefines(Opts, Builder); 6276 } 6277 bool hasFeature(StringRef Feature) const override { 6278 return Feature == "pnacl"; 6279 } 6280 void getTargetBuiltins(const Builtin::Info *&Records, 6281 unsigned &NumRecords) const override { 6282 } 6283 BuiltinVaListKind getBuiltinVaListKind() const override { 6284 return TargetInfo::PNaClABIBuiltinVaList; 6285 } 6286 void getGCCRegNames(const char * const *&Names, 6287 unsigned &NumNames) const override; 6288 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6289 unsigned &NumAliases) const override; 6290 bool validateAsmConstraint(const char *&Name, 6291 TargetInfo::ConstraintInfo &Info) const override { 6292 return false; 6293 } 6294 6295 const char *getClobbers() const override { 6296 return ""; 6297 } 6298 }; 6299 6300 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6301 unsigned &NumNames) const { 6302 Names = nullptr; 6303 NumNames = 0; 6304 } 6305 6306 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6307 unsigned &NumAliases) const { 6308 Aliases = nullptr; 6309 NumAliases = 0; 6310 } 6311 } // end anonymous namespace. 6312 6313 namespace { 6314 class Le64TargetInfo : public TargetInfo { 6315 static const Builtin::Info BuiltinInfo[]; 6316 6317 public: 6318 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6319 BigEndian = false; 6320 NoAsmVariants = true; 6321 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6322 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6323 DescriptionString = 6324 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6325 } 6326 6327 void getTargetDefines(const LangOptions &Opts, 6328 MacroBuilder &Builder) const override { 6329 DefineStd(Builder, "unix", Opts); 6330 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6331 Builder.defineMacro("__ELF__"); 6332 } 6333 void getTargetBuiltins(const Builtin::Info *&Records, 6334 unsigned &NumRecords) const override { 6335 Records = BuiltinInfo; 6336 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6337 } 6338 BuiltinVaListKind getBuiltinVaListKind() const override { 6339 return TargetInfo::PNaClABIBuiltinVaList; 6340 } 6341 const char *getClobbers() const override { return ""; } 6342 void getGCCRegNames(const char *const *&Names, 6343 unsigned &NumNames) const override { 6344 Names = nullptr; 6345 NumNames = 0; 6346 } 6347 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6348 unsigned &NumAliases) const override { 6349 Aliases = nullptr; 6350 NumAliases = 0; 6351 } 6352 bool validateAsmConstraint(const char *&Name, 6353 TargetInfo::ConstraintInfo &Info) const override { 6354 return false; 6355 } 6356 6357 bool hasProtectedVisibility() const override { return false; } 6358 }; 6359 } // end anonymous namespace. 6360 6361 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6362 #define BUILTIN(ID, TYPE, ATTRS) \ 6363 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6364 #include "clang/Basic/BuiltinsLe64.def" 6365 }; 6366 6367 namespace { 6368 static const unsigned SPIRAddrSpaceMap[] = { 6369 1, // opencl_global 6370 3, // opencl_local 6371 2, // opencl_constant 6372 4, // opencl_generic 6373 0, // cuda_device 6374 0, // cuda_constant 6375 0 // cuda_shared 6376 }; 6377 class SPIRTargetInfo : public TargetInfo { 6378 public: 6379 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6380 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6381 "SPIR target must use unknown OS"); 6382 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6383 "SPIR target must use unknown environment type"); 6384 BigEndian = false; 6385 TLSSupported = false; 6386 LongWidth = LongAlign = 64; 6387 AddrSpaceMap = &SPIRAddrSpaceMap; 6388 UseAddrSpaceMapMangling = true; 6389 // Define available target features 6390 // These must be defined in sorted order! 6391 NoAsmVariants = true; 6392 } 6393 void getTargetDefines(const LangOptions &Opts, 6394 MacroBuilder &Builder) const override { 6395 DefineStd(Builder, "SPIR", Opts); 6396 } 6397 bool hasFeature(StringRef Feature) const override { 6398 return Feature == "spir"; 6399 } 6400 6401 void getTargetBuiltins(const Builtin::Info *&Records, 6402 unsigned &NumRecords) const override {} 6403 const char *getClobbers() const override { 6404 return ""; 6405 } 6406 void getGCCRegNames(const char * const *&Names, 6407 unsigned &NumNames) const override {} 6408 bool 6409 validateAsmConstraint(const char *&Name, 6410 TargetInfo::ConstraintInfo &info) const override { 6411 return true; 6412 } 6413 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6414 unsigned &NumAliases) const override {} 6415 BuiltinVaListKind getBuiltinVaListKind() const override { 6416 return TargetInfo::VoidPtrBuiltinVaList; 6417 } 6418 6419 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6420 return (CC == CC_SpirFunction || 6421 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6422 } 6423 6424 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6425 return CC_SpirFunction; 6426 } 6427 }; 6428 6429 6430 class SPIR32TargetInfo : public SPIRTargetInfo { 6431 public: 6432 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6433 PointerWidth = PointerAlign = 32; 6434 SizeType = TargetInfo::UnsignedInt; 6435 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6436 DescriptionString 6437 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6438 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6439 } 6440 void getTargetDefines(const LangOptions &Opts, 6441 MacroBuilder &Builder) const override { 6442 DefineStd(Builder, "SPIR32", Opts); 6443 } 6444 }; 6445 6446 class SPIR64TargetInfo : public SPIRTargetInfo { 6447 public: 6448 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6449 PointerWidth = PointerAlign = 64; 6450 SizeType = TargetInfo::UnsignedLong; 6451 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6452 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6453 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6454 } 6455 void getTargetDefines(const LangOptions &Opts, 6456 MacroBuilder &Builder) const override { 6457 DefineStd(Builder, "SPIR64", Opts); 6458 } 6459 }; 6460 } 6461 6462 namespace { 6463 class XCoreTargetInfo : public TargetInfo { 6464 static const Builtin::Info BuiltinInfo[]; 6465 public: 6466 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6467 BigEndian = false; 6468 NoAsmVariants = true; 6469 LongLongAlign = 32; 6470 SuitableAlign = 32; 6471 DoubleAlign = LongDoubleAlign = 32; 6472 SizeType = UnsignedInt; 6473 PtrDiffType = SignedInt; 6474 IntPtrType = SignedInt; 6475 WCharType = UnsignedChar; 6476 WIntType = UnsignedInt; 6477 UseZeroLengthBitfieldAlignment = true; 6478 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6479 "-f64:32-a:0:32-n32"; 6480 } 6481 void getTargetDefines(const LangOptions &Opts, 6482 MacroBuilder &Builder) const override { 6483 Builder.defineMacro("__XS1B__"); 6484 } 6485 void getTargetBuiltins(const Builtin::Info *&Records, 6486 unsigned &NumRecords) const override { 6487 Records = BuiltinInfo; 6488 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6489 } 6490 BuiltinVaListKind getBuiltinVaListKind() const override { 6491 return TargetInfo::VoidPtrBuiltinVaList; 6492 } 6493 const char *getClobbers() const override { 6494 return ""; 6495 } 6496 void getGCCRegNames(const char * const *&Names, 6497 unsigned &NumNames) const override { 6498 static const char * const GCCRegNames[] = { 6499 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6500 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6501 }; 6502 Names = GCCRegNames; 6503 NumNames = llvm::array_lengthof(GCCRegNames); 6504 } 6505 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6506 unsigned &NumAliases) const override { 6507 Aliases = nullptr; 6508 NumAliases = 0; 6509 } 6510 bool validateAsmConstraint(const char *&Name, 6511 TargetInfo::ConstraintInfo &Info) const override { 6512 return false; 6513 } 6514 int getEHDataRegisterNumber(unsigned RegNo) const override { 6515 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6516 return (RegNo < 2)? RegNo : -1; 6517 } 6518 }; 6519 6520 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6521 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6522 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6523 ALL_LANGUAGES }, 6524 #include "clang/Basic/BuiltinsXCore.def" 6525 }; 6526 } // end anonymous namespace. 6527 6528 6529 //===----------------------------------------------------------------------===// 6530 // Driver code 6531 //===----------------------------------------------------------------------===// 6532 6533 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6534 llvm::Triple::OSType os = Triple.getOS(); 6535 6536 switch (Triple.getArch()) { 6537 default: 6538 return nullptr; 6539 6540 case llvm::Triple::xcore: 6541 return new XCoreTargetInfo(Triple); 6542 6543 case llvm::Triple::hexagon: 6544 return new HexagonTargetInfo(Triple); 6545 6546 case llvm::Triple::aarch64: 6547 if (Triple.isOSDarwin()) 6548 return new DarwinAArch64TargetInfo(Triple); 6549 6550 switch (os) { 6551 case llvm::Triple::FreeBSD: 6552 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6553 case llvm::Triple::Linux: 6554 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6555 case llvm::Triple::NetBSD: 6556 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6557 default: 6558 return new AArch64leTargetInfo(Triple); 6559 } 6560 6561 case llvm::Triple::aarch64_be: 6562 switch (os) { 6563 case llvm::Triple::FreeBSD: 6564 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6565 case llvm::Triple::Linux: 6566 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6567 case llvm::Triple::NetBSD: 6568 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6569 default: 6570 return new AArch64beTargetInfo(Triple); 6571 } 6572 6573 case llvm::Triple::arm: 6574 case llvm::Triple::thumb: 6575 if (Triple.isOSBinFormatMachO()) 6576 return new DarwinARMTargetInfo(Triple); 6577 6578 switch (os) { 6579 case llvm::Triple::Linux: 6580 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6581 case llvm::Triple::FreeBSD: 6582 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6583 case llvm::Triple::NetBSD: 6584 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6585 case llvm::Triple::OpenBSD: 6586 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6587 case llvm::Triple::Bitrig: 6588 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6589 case llvm::Triple::RTEMS: 6590 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6591 case llvm::Triple::NaCl: 6592 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6593 case llvm::Triple::Win32: 6594 switch (Triple.getEnvironment()) { 6595 default: 6596 return new ARMleTargetInfo(Triple); 6597 case llvm::Triple::Itanium: 6598 return new ItaniumWindowsARMleTargetInfo(Triple); 6599 case llvm::Triple::MSVC: 6600 return new MicrosoftARMleTargetInfo(Triple); 6601 } 6602 default: 6603 return new ARMleTargetInfo(Triple); 6604 } 6605 6606 case llvm::Triple::armeb: 6607 case llvm::Triple::thumbeb: 6608 if (Triple.isOSDarwin()) 6609 return new DarwinARMTargetInfo(Triple); 6610 6611 switch (os) { 6612 case llvm::Triple::Linux: 6613 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6614 case llvm::Triple::FreeBSD: 6615 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6616 case llvm::Triple::NetBSD: 6617 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6618 case llvm::Triple::OpenBSD: 6619 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6620 case llvm::Triple::Bitrig: 6621 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6622 case llvm::Triple::RTEMS: 6623 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6624 case llvm::Triple::NaCl: 6625 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6626 default: 6627 return new ARMbeTargetInfo(Triple); 6628 } 6629 6630 case llvm::Triple::msp430: 6631 return new MSP430TargetInfo(Triple); 6632 6633 case llvm::Triple::mips: 6634 switch (os) { 6635 case llvm::Triple::Linux: 6636 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6637 case llvm::Triple::RTEMS: 6638 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6639 case llvm::Triple::FreeBSD: 6640 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6641 case llvm::Triple::NetBSD: 6642 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6643 default: 6644 return new Mips32EBTargetInfo(Triple); 6645 } 6646 6647 case llvm::Triple::mipsel: 6648 switch (os) { 6649 case llvm::Triple::Linux: 6650 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6651 case llvm::Triple::RTEMS: 6652 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6653 case llvm::Triple::FreeBSD: 6654 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6655 case llvm::Triple::NetBSD: 6656 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6657 case llvm::Triple::NaCl: 6658 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6659 default: 6660 return new Mips32ELTargetInfo(Triple); 6661 } 6662 6663 case llvm::Triple::mips64: 6664 switch (os) { 6665 case llvm::Triple::Linux: 6666 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6667 case llvm::Triple::RTEMS: 6668 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6669 case llvm::Triple::FreeBSD: 6670 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6671 case llvm::Triple::NetBSD: 6672 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6673 case llvm::Triple::OpenBSD: 6674 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6675 default: 6676 return new Mips64EBTargetInfo(Triple); 6677 } 6678 6679 case llvm::Triple::mips64el: 6680 switch (os) { 6681 case llvm::Triple::Linux: 6682 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6683 case llvm::Triple::RTEMS: 6684 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6685 case llvm::Triple::FreeBSD: 6686 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6687 case llvm::Triple::NetBSD: 6688 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6689 case llvm::Triple::OpenBSD: 6690 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6691 default: 6692 return new Mips64ELTargetInfo(Triple); 6693 } 6694 6695 case llvm::Triple::le32: 6696 switch (os) { 6697 case llvm::Triple::NaCl: 6698 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6699 default: 6700 return nullptr; 6701 } 6702 6703 case llvm::Triple::le64: 6704 return new Le64TargetInfo(Triple); 6705 6706 case llvm::Triple::ppc: 6707 if (Triple.isOSDarwin()) 6708 return new DarwinPPC32TargetInfo(Triple); 6709 switch (os) { 6710 case llvm::Triple::Linux: 6711 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6712 case llvm::Triple::FreeBSD: 6713 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6714 case llvm::Triple::NetBSD: 6715 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6716 case llvm::Triple::OpenBSD: 6717 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6718 case llvm::Triple::RTEMS: 6719 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6720 default: 6721 return new PPC32TargetInfo(Triple); 6722 } 6723 6724 case llvm::Triple::ppc64: 6725 if (Triple.isOSDarwin()) 6726 return new DarwinPPC64TargetInfo(Triple); 6727 switch (os) { 6728 case llvm::Triple::Linux: 6729 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6730 case llvm::Triple::Lv2: 6731 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6732 case llvm::Triple::FreeBSD: 6733 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6734 case llvm::Triple::NetBSD: 6735 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6736 default: 6737 return new PPC64TargetInfo(Triple); 6738 } 6739 6740 case llvm::Triple::ppc64le: 6741 switch (os) { 6742 case llvm::Triple::Linux: 6743 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6744 default: 6745 return new PPC64TargetInfo(Triple); 6746 } 6747 6748 case llvm::Triple::nvptx: 6749 return new NVPTX32TargetInfo(Triple); 6750 case llvm::Triple::nvptx64: 6751 return new NVPTX64TargetInfo(Triple); 6752 6753 case llvm::Triple::amdgcn: 6754 case llvm::Triple::r600: 6755 return new R600TargetInfo(Triple); 6756 6757 case llvm::Triple::sparc: 6758 switch (os) { 6759 case llvm::Triple::Linux: 6760 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6761 case llvm::Triple::Solaris: 6762 return new SolarisSparcV8TargetInfo(Triple); 6763 case llvm::Triple::NetBSD: 6764 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6765 case llvm::Triple::OpenBSD: 6766 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6767 case llvm::Triple::RTEMS: 6768 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6769 default: 6770 return new SparcV8TargetInfo(Triple); 6771 } 6772 6773 case llvm::Triple::sparcv9: 6774 switch (os) { 6775 case llvm::Triple::Linux: 6776 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6777 case llvm::Triple::Solaris: 6778 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6779 case llvm::Triple::NetBSD: 6780 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6781 case llvm::Triple::OpenBSD: 6782 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6783 case llvm::Triple::FreeBSD: 6784 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6785 default: 6786 return new SparcV9TargetInfo(Triple); 6787 } 6788 6789 case llvm::Triple::systemz: 6790 switch (os) { 6791 case llvm::Triple::Linux: 6792 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6793 default: 6794 return new SystemZTargetInfo(Triple); 6795 } 6796 6797 case llvm::Triple::tce: 6798 return new TCETargetInfo(Triple); 6799 6800 case llvm::Triple::x86: 6801 if (Triple.isOSDarwin()) 6802 return new DarwinI386TargetInfo(Triple); 6803 6804 switch (os) { 6805 case llvm::Triple::Linux: 6806 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6807 case llvm::Triple::DragonFly: 6808 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6809 case llvm::Triple::NetBSD: 6810 return new NetBSDI386TargetInfo(Triple); 6811 case llvm::Triple::OpenBSD: 6812 return new OpenBSDI386TargetInfo(Triple); 6813 case llvm::Triple::Bitrig: 6814 return new BitrigI386TargetInfo(Triple); 6815 case llvm::Triple::FreeBSD: 6816 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6817 case llvm::Triple::KFreeBSD: 6818 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6819 case llvm::Triple::Minix: 6820 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6821 case llvm::Triple::Solaris: 6822 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6823 case llvm::Triple::Win32: { 6824 switch (Triple.getEnvironment()) { 6825 default: 6826 return new X86_32TargetInfo(Triple); 6827 case llvm::Triple::Cygnus: 6828 return new CygwinX86_32TargetInfo(Triple); 6829 case llvm::Triple::GNU: 6830 return new MinGWX86_32TargetInfo(Triple); 6831 case llvm::Triple::Itanium: 6832 case llvm::Triple::MSVC: 6833 return new MicrosoftX86_32TargetInfo(Triple); 6834 } 6835 } 6836 case llvm::Triple::Haiku: 6837 return new HaikuX86_32TargetInfo(Triple); 6838 case llvm::Triple::RTEMS: 6839 return new RTEMSX86_32TargetInfo(Triple); 6840 case llvm::Triple::NaCl: 6841 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6842 default: 6843 return new X86_32TargetInfo(Triple); 6844 } 6845 6846 case llvm::Triple::x86_64: 6847 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6848 return new DarwinX86_64TargetInfo(Triple); 6849 6850 switch (os) { 6851 case llvm::Triple::Linux: 6852 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6853 case llvm::Triple::DragonFly: 6854 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6855 case llvm::Triple::NetBSD: 6856 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6857 case llvm::Triple::OpenBSD: 6858 return new OpenBSDX86_64TargetInfo(Triple); 6859 case llvm::Triple::Bitrig: 6860 return new BitrigX86_64TargetInfo(Triple); 6861 case llvm::Triple::FreeBSD: 6862 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6863 case llvm::Triple::KFreeBSD: 6864 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6865 case llvm::Triple::Solaris: 6866 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6867 case llvm::Triple::Win32: { 6868 switch (Triple.getEnvironment()) { 6869 default: 6870 return new X86_64TargetInfo(Triple); 6871 case llvm::Triple::GNU: 6872 return new MinGWX86_64TargetInfo(Triple); 6873 case llvm::Triple::MSVC: 6874 return new MicrosoftX86_64TargetInfo(Triple); 6875 } 6876 } 6877 case llvm::Triple::NaCl: 6878 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6879 case llvm::Triple::PS4: 6880 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 6881 default: 6882 return new X86_64TargetInfo(Triple); 6883 } 6884 6885 case llvm::Triple::spir: { 6886 if (Triple.getOS() != llvm::Triple::UnknownOS || 6887 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6888 return nullptr; 6889 return new SPIR32TargetInfo(Triple); 6890 } 6891 case llvm::Triple::spir64: { 6892 if (Triple.getOS() != llvm::Triple::UnknownOS || 6893 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6894 return nullptr; 6895 return new SPIR64TargetInfo(Triple); 6896 } 6897 } 6898 } 6899 6900 /// CreateTargetInfo - Return the target info object for the specified target 6901 /// triple. 6902 TargetInfo * 6903 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6904 const std::shared_ptr<TargetOptions> &Opts) { 6905 llvm::Triple Triple(Opts->Triple); 6906 6907 // Construct the target 6908 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6909 if (!Target) { 6910 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6911 return nullptr; 6912 } 6913 Target->TargetOpts = Opts; 6914 6915 // Set the target CPU if specified. 6916 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6917 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6918 return nullptr; 6919 } 6920 6921 // Set the target ABI if specified. 6922 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6923 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6924 return nullptr; 6925 } 6926 6927 // Set the fp math unit. 6928 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6929 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6930 return nullptr; 6931 } 6932 6933 // Compute the default target features, we need the target to handle this 6934 // because features may have dependencies on one another. 6935 llvm::StringMap<bool> Features; 6936 Target->getDefaultFeatures(Features); 6937 6938 // Apply the user specified deltas. 6939 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6940 I < N; ++I) { 6941 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6942 // Apply the feature via the target. 6943 bool Enabled = Name[0] == '+'; 6944 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6945 } 6946 6947 // Add the features to the compile options. 6948 // 6949 // FIXME: If we are completely confident that we have the right set, we only 6950 // need to pass the minuses. 6951 Opts->Features.clear(); 6952 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6953 ie = Features.end(); it != ie; ++it) 6954 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6955 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6956 return nullptr; 6957 6958 return Target.release(); 6959 } 6960