1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 using namespace clang; 34 35 //===----------------------------------------------------------------------===// 36 // Common code shared among targets. 37 //===----------------------------------------------------------------------===// 38 39 /// DefineStd - Define a macro name and standard variants. For example if 40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 41 /// when in GNU mode. 42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 43 const LangOptions &Opts) { 44 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 45 46 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 47 // in the user's namespace. 48 if (Opts.GNUMode) 49 Builder.defineMacro(MacroName); 50 51 // Define __unix. 52 Builder.defineMacro("__" + MacroName); 53 54 // Define __unix__. 55 Builder.defineMacro("__" + MacroName + "__"); 56 } 57 58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 59 bool Tuning = true) { 60 Builder.defineMacro("__" + CPUName); 61 Builder.defineMacro("__" + CPUName + "__"); 62 if (Tuning) 63 Builder.defineMacro("__tune_" + CPUName + "__"); 64 } 65 66 //===----------------------------------------------------------------------===// 67 // Defines specific to certain operating systems. 68 //===----------------------------------------------------------------------===// 69 70 namespace { 71 template<typename TgtInfo> 72 class OSTargetInfo : public TgtInfo { 73 protected: 74 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 75 MacroBuilder &Builder) const=0; 76 public: 77 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 78 void getTargetDefines(const LangOptions &Opts, 79 MacroBuilder &Builder) const override { 80 TgtInfo::getTargetDefines(Opts, Builder); 81 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 82 } 83 84 }; 85 } // end anonymous namespace 86 87 88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 89 const llvm::Triple &Triple, 90 StringRef &PlatformName, 91 VersionTuple &PlatformMinVersion) { 92 Builder.defineMacro("__APPLE_CC__", "6000"); 93 Builder.defineMacro("__APPLE__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.has(SanitizerKind::Address)) 98 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 99 100 if (!Opts.ObjCAutoRefCount) { 101 // __weak is always defined, for use in blocks and with objc pointers. 102 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 103 104 // Darwin defines __strong even in C mode (just to nothing). 105 if (Opts.getGC() != LangOptions::NonGC) 106 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 107 else 108 Builder.defineMacro("__strong", ""); 109 110 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 111 // allow this in C, since one might have block pointers in structs that 112 // are used in pure C code and in Objective-C ARC. 113 Builder.defineMacro("__unsafe_unretained", ""); 114 } 115 116 if (Opts.Static) 117 Builder.defineMacro("__STATIC__"); 118 else 119 Builder.defineMacro("__DYNAMIC__"); 120 121 if (Opts.POSIXThreads) 122 Builder.defineMacro("_REENTRANT"); 123 124 // Get the platform type and version number from the triple. 125 unsigned Maj, Min, Rev; 126 if (Triple.isMacOSX()) { 127 Triple.getMacOSXVersion(Maj, Min, Rev); 128 PlatformName = "macosx"; 129 } else { 130 Triple.getOSVersion(Maj, Min, Rev); 131 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 132 } 133 134 // If -target arch-pc-win32-macho option specified, we're 135 // generating code for Win32 ABI. No need to emit 136 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 137 if (PlatformName == "win32") { 138 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 139 return; 140 } 141 142 // Set the appropriate OS version define. 143 if (Triple.isiOS()) { 144 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 145 char Str[6]; 146 Str[0] = '0' + Maj; 147 Str[1] = '0' + (Min / 10); 148 Str[2] = '0' + (Min % 10); 149 Str[3] = '0' + (Rev / 10); 150 Str[4] = '0' + (Rev % 10); 151 Str[5] = '\0'; 152 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 153 Str); 154 } else if (Triple.isMacOSX()) { 155 // Note that the Driver allows versions which aren't representable in the 156 // define (because we only get a single digit for the minor and micro 157 // revision numbers). So, we limit them to the maximum representable 158 // version. 159 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 160 char Str[7]; 161 if (Maj < 10 || (Maj == 10 && Min < 10)) { 162 Str[0] = '0' + (Maj / 10); 163 Str[1] = '0' + (Maj % 10); 164 Str[2] = '0' + std::min(Min, 9U); 165 Str[3] = '0' + std::min(Rev, 9U); 166 Str[4] = '\0'; 167 } else { 168 // Handle versions > 10.9. 169 Str[0] = '0' + (Maj / 10); 170 Str[1] = '0' + (Maj % 10); 171 Str[2] = '0' + (Min / 10); 172 Str[3] = '0' + (Min % 10); 173 Str[4] = '0' + (Rev / 10); 174 Str[5] = '0' + (Rev % 10); 175 Str[6] = '\0'; 176 } 177 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 178 } 179 180 // Tell users about the kernel if there is one. 181 if (Triple.isOSDarwin()) 182 Builder.defineMacro("__MACH__"); 183 184 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 185 } 186 187 namespace { 188 // CloudABI Target 189 template <typename Target> 190 class CloudABITargetInfo : public OSTargetInfo<Target> { 191 protected: 192 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 193 MacroBuilder &Builder) const override { 194 Builder.defineMacro("__CloudABI__"); 195 Builder.defineMacro("__ELF__"); 196 197 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 198 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 199 Builder.defineMacro("__STDC_UTF_16__"); 200 Builder.defineMacro("__STDC_UTF_32__"); 201 } 202 203 public: 204 CloudABITargetInfo(const llvm::Triple &Triple) 205 : OSTargetInfo<Target>(Triple) { 206 this->UserLabelPrefix = ""; 207 } 208 }; 209 210 template<typename Target> 211 class DarwinTargetInfo : public OSTargetInfo<Target> { 212 protected: 213 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 214 MacroBuilder &Builder) const override { 215 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 216 this->PlatformMinVersion); 217 } 218 219 public: 220 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 221 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 222 this->MCountName = "\01mcount"; 223 } 224 225 std::string isValidSectionSpecifier(StringRef SR) const override { 226 // Let MCSectionMachO validate this. 227 StringRef Segment, Section; 228 unsigned TAA, StubSize; 229 bool HasTAA; 230 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 231 TAA, HasTAA, StubSize); 232 } 233 234 const char *getStaticInitSectionSpecifier() const override { 235 // FIXME: We should return 0 when building kexts. 236 return "__TEXT,__StaticInit,regular,pure_instructions"; 237 } 238 239 /// Darwin does not support protected visibility. Darwin's "default" 240 /// is very similar to ELF's "protected"; Darwin requires a "weak" 241 /// attribute on declarations that can be dynamically replaced. 242 bool hasProtectedVisibility() const override { 243 return false; 244 } 245 }; 246 247 248 // DragonFlyBSD Target 249 template<typename Target> 250 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 251 protected: 252 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 253 MacroBuilder &Builder) const override { 254 // DragonFly defines; list based off of gcc output 255 Builder.defineMacro("__DragonFly__"); 256 Builder.defineMacro("__DragonFly_cc_version", "100001"); 257 Builder.defineMacro("__ELF__"); 258 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 259 Builder.defineMacro("__tune_i386__"); 260 DefineStd(Builder, "unix", Opts); 261 } 262 public: 263 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 264 : OSTargetInfo<Target>(Triple) { 265 this->UserLabelPrefix = ""; 266 267 switch (Triple.getArch()) { 268 default: 269 case llvm::Triple::x86: 270 case llvm::Triple::x86_64: 271 this->MCountName = ".mcount"; 272 break; 273 } 274 } 275 }; 276 277 // FreeBSD Target 278 template<typename Target> 279 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 280 protected: 281 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 282 MacroBuilder &Builder) const override { 283 // FreeBSD defines; list based off of gcc output 284 285 unsigned Release = Triple.getOSMajorVersion(); 286 if (Release == 0U) 287 Release = 8; 288 289 Builder.defineMacro("__FreeBSD__", Twine(Release)); 290 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 291 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 292 DefineStd(Builder, "unix", Opts); 293 Builder.defineMacro("__ELF__"); 294 295 // On FreeBSD, wchar_t contains the number of the code point as 296 // used by the character set of the locale. These character sets are 297 // not necessarily a superset of ASCII. 298 // 299 // FIXME: This is wrong; the macro refers to the numerical values 300 // of wchar_t *literals*, which are not locale-dependent. However, 301 // FreeBSD systems apparently depend on us getting this wrong, and 302 // setting this to 1 is conforming even if all the basic source 303 // character literals have the same encoding as char and wchar_t. 304 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 305 } 306 public: 307 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 310 switch (Triple.getArch()) { 311 default: 312 case llvm::Triple::x86: 313 case llvm::Triple::x86_64: 314 this->MCountName = ".mcount"; 315 break; 316 case llvm::Triple::mips: 317 case llvm::Triple::mipsel: 318 case llvm::Triple::ppc: 319 case llvm::Triple::ppc64: 320 case llvm::Triple::ppc64le: 321 this->MCountName = "_mcount"; 322 break; 323 case llvm::Triple::arm: 324 this->MCountName = "__mcount"; 325 break; 326 } 327 } 328 }; 329 330 // GNU/kFreeBSD Target 331 template<typename Target> 332 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 333 protected: 334 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 335 MacroBuilder &Builder) const override { 336 // GNU/kFreeBSD defines; list based off of gcc output 337 338 DefineStd(Builder, "unix", Opts); 339 Builder.defineMacro("__FreeBSD_kernel__"); 340 Builder.defineMacro("__GLIBC__"); 341 Builder.defineMacro("__ELF__"); 342 if (Opts.POSIXThreads) 343 Builder.defineMacro("_REENTRANT"); 344 if (Opts.CPlusPlus) 345 Builder.defineMacro("_GNU_SOURCE"); 346 } 347 public: 348 KFreeBSDTargetInfo(const llvm::Triple &Triple) 349 : OSTargetInfo<Target>(Triple) { 350 this->UserLabelPrefix = ""; 351 } 352 }; 353 354 // Minix Target 355 template<typename Target> 356 class MinixTargetInfo : public OSTargetInfo<Target> { 357 protected: 358 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 359 MacroBuilder &Builder) const override { 360 // Minix defines 361 362 Builder.defineMacro("__minix", "3"); 363 Builder.defineMacro("_EM_WSIZE", "4"); 364 Builder.defineMacro("_EM_PSIZE", "4"); 365 Builder.defineMacro("_EM_SSIZE", "2"); 366 Builder.defineMacro("_EM_LSIZE", "4"); 367 Builder.defineMacro("_EM_FSIZE", "4"); 368 Builder.defineMacro("_EM_DSIZE", "8"); 369 Builder.defineMacro("__ELF__"); 370 DefineStd(Builder, "unix", Opts); 371 } 372 public: 373 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 374 this->UserLabelPrefix = ""; 375 } 376 }; 377 378 // Linux target 379 template<typename Target> 380 class LinuxTargetInfo : public OSTargetInfo<Target> { 381 protected: 382 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 383 MacroBuilder &Builder) const override { 384 // Linux defines; list based off of gcc output 385 DefineStd(Builder, "unix", Opts); 386 DefineStd(Builder, "linux", Opts); 387 Builder.defineMacro("__gnu_linux__"); 388 Builder.defineMacro("__ELF__"); 389 if (Triple.getEnvironment() == llvm::Triple::Android) { 390 Builder.defineMacro("__ANDROID__", "1"); 391 unsigned Maj, Min, Rev; 392 Triple.getEnvironmentVersion(Maj, Min, Rev); 393 this->PlatformName = "android"; 394 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 395 } 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 403 this->UserLabelPrefix = ""; 404 this->WIntType = TargetInfo::UnsignedInt; 405 406 switch (Triple.getArch()) { 407 default: 408 break; 409 case llvm::Triple::ppc: 410 case llvm::Triple::ppc64: 411 case llvm::Triple::ppc64le: 412 this->MCountName = "_mcount"; 413 break; 414 } 415 } 416 417 const char *getStaticInitSectionSpecifier() const override { 418 return ".text.startup"; 419 } 420 }; 421 422 // NetBSD Target 423 template<typename Target> 424 class NetBSDTargetInfo : public OSTargetInfo<Target> { 425 protected: 426 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 427 MacroBuilder &Builder) const override { 428 // NetBSD defines; list based off of gcc output 429 Builder.defineMacro("__NetBSD__"); 430 Builder.defineMacro("__unix__"); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_POSIX_THREADS"); 434 435 switch (Triple.getArch()) { 436 default: 437 break; 438 case llvm::Triple::arm: 439 case llvm::Triple::armeb: 440 case llvm::Triple::thumb: 441 case llvm::Triple::thumbeb: 442 Builder.defineMacro("__ARM_DWARF_EH__"); 443 break; 444 } 445 } 446 public: 447 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 448 this->UserLabelPrefix = ""; 449 this->MCountName = "_mcount"; 450 } 451 }; 452 453 // OpenBSD Target 454 template<typename Target> 455 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // OpenBSD defines; list based off of gcc output 460 461 Builder.defineMacro("__OpenBSD__"); 462 DefineStd(Builder, "unix", Opts); 463 Builder.defineMacro("__ELF__"); 464 if (Opts.POSIXThreads) 465 Builder.defineMacro("_REENTRANT"); 466 } 467 public: 468 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 469 this->UserLabelPrefix = ""; 470 this->TLSSupported = false; 471 472 switch (Triple.getArch()) { 473 default: 474 case llvm::Triple::x86: 475 case llvm::Triple::x86_64: 476 case llvm::Triple::arm: 477 case llvm::Triple::sparc: 478 this->MCountName = "__mcount"; 479 break; 480 case llvm::Triple::mips64: 481 case llvm::Triple::mips64el: 482 case llvm::Triple::ppc: 483 case llvm::Triple::sparcv9: 484 this->MCountName = "_mcount"; 485 break; 486 } 487 } 488 }; 489 490 // Bitrig Target 491 template<typename Target> 492 class BitrigTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const override { 496 // Bitrig defines; list based off of gcc output 497 498 Builder.defineMacro("__Bitrig__"); 499 DefineStd(Builder, "unix", Opts); 500 Builder.defineMacro("__ELF__"); 501 if (Opts.POSIXThreads) 502 Builder.defineMacro("_REENTRANT"); 503 504 switch (Triple.getArch()) { 505 default: 506 break; 507 case llvm::Triple::arm: 508 case llvm::Triple::armeb: 509 case llvm::Triple::thumb: 510 case llvm::Triple::thumbeb: 511 Builder.defineMacro("__ARM_DWARF_EH__"); 512 break; 513 } 514 } 515 public: 516 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 517 this->UserLabelPrefix = ""; 518 this->MCountName = "__mcount"; 519 } 520 }; 521 522 // PSP Target 523 template<typename Target> 524 class PSPTargetInfo : public OSTargetInfo<Target> { 525 protected: 526 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 527 MacroBuilder &Builder) const override { 528 // PSP defines; list based on the output of the pspdev gcc toolchain. 529 Builder.defineMacro("PSP"); 530 Builder.defineMacro("_PSP"); 531 Builder.defineMacro("__psp__"); 532 Builder.defineMacro("__ELF__"); 533 } 534 public: 535 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 536 this->UserLabelPrefix = ""; 537 } 538 }; 539 540 // PS3 PPU Target 541 template<typename Target> 542 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 543 protected: 544 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 545 MacroBuilder &Builder) const override { 546 // PS3 PPU defines. 547 Builder.defineMacro("__PPC__"); 548 Builder.defineMacro("__PPU__"); 549 Builder.defineMacro("__CELLOS_LV2__"); 550 Builder.defineMacro("__ELF__"); 551 Builder.defineMacro("__LP32__"); 552 Builder.defineMacro("_ARCH_PPC64"); 553 Builder.defineMacro("__powerpc64__"); 554 } 555 public: 556 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 557 this->UserLabelPrefix = ""; 558 this->LongWidth = this->LongAlign = 32; 559 this->PointerWidth = this->PointerAlign = 32; 560 this->IntMaxType = TargetInfo::SignedLongLong; 561 this->Int64Type = TargetInfo::SignedLongLong; 562 this->SizeType = TargetInfo::UnsignedInt; 563 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 564 } 565 }; 566 567 template <typename Target> 568 class PS4OSTargetInfo : public OSTargetInfo<Target> { 569 protected: 570 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 571 MacroBuilder &Builder) const override { 572 Builder.defineMacro("__FreeBSD__", "9"); 573 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 574 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 575 DefineStd(Builder, "unix", Opts); 576 Builder.defineMacro("__ELF__"); 577 Builder.defineMacro("__PS4__"); 578 } 579 public: 580 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 581 this->WCharType = this->UnsignedShort; 582 583 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 584 this->MaxTLSAlign = 256; 585 this->UserLabelPrefix = ""; 586 587 switch (Triple.getArch()) { 588 default: 589 case llvm::Triple::x86_64: 590 this->MCountName = ".mcount"; 591 break; 592 } 593 } 594 }; 595 596 // Solaris target 597 template<typename Target> 598 class SolarisTargetInfo : public OSTargetInfo<Target> { 599 protected: 600 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 601 MacroBuilder &Builder) const override { 602 DefineStd(Builder, "sun", Opts); 603 DefineStd(Builder, "unix", Opts); 604 Builder.defineMacro("__ELF__"); 605 Builder.defineMacro("__svr4__"); 606 Builder.defineMacro("__SVR4"); 607 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 608 // newer, but to 500 for everything else. feature_test.h has a check to 609 // ensure that you are not using C99 with an old version of X/Open or C89 610 // with a new version. 611 if (Opts.C99) 612 Builder.defineMacro("_XOPEN_SOURCE", "600"); 613 else 614 Builder.defineMacro("_XOPEN_SOURCE", "500"); 615 if (Opts.CPlusPlus) 616 Builder.defineMacro("__C99FEATURES__"); 617 Builder.defineMacro("_LARGEFILE_SOURCE"); 618 Builder.defineMacro("_LARGEFILE64_SOURCE"); 619 Builder.defineMacro("__EXTENSIONS__"); 620 Builder.defineMacro("_REENTRANT"); 621 } 622 public: 623 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 624 this->UserLabelPrefix = ""; 625 this->WCharType = this->SignedInt; 626 // FIXME: WIntType should be SignedLong 627 } 628 }; 629 630 // Windows target 631 template<typename Target> 632 class WindowsTargetInfo : public OSTargetInfo<Target> { 633 protected: 634 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 635 MacroBuilder &Builder) const override { 636 Builder.defineMacro("_WIN32"); 637 } 638 void getVisualStudioDefines(const LangOptions &Opts, 639 MacroBuilder &Builder) const { 640 if (Opts.CPlusPlus) { 641 if (Opts.RTTIData) 642 Builder.defineMacro("_CPPRTTI"); 643 644 if (Opts.CXXExceptions) 645 Builder.defineMacro("_CPPUNWIND"); 646 647 Builder.defineMacro("__BOOL_DEFINED"); 648 } 649 650 if (!Opts.CharIsSigned) 651 Builder.defineMacro("_CHAR_UNSIGNED"); 652 653 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 654 // but it works for now. 655 if (Opts.POSIXThreads) 656 Builder.defineMacro("_MT"); 657 658 if (Opts.MSCompatibilityVersion) { 659 Builder.defineMacro("_MSC_VER", 660 Twine(Opts.MSCompatibilityVersion / 100000)); 661 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 662 // FIXME We cannot encode the revision information into 32-bits 663 Builder.defineMacro("_MSC_BUILD", Twine(1)); 664 665 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 666 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 667 } 668 669 if (Opts.MicrosoftExt) { 670 Builder.defineMacro("_MSC_EXTENSIONS"); 671 672 if (Opts.CPlusPlus11) { 673 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 674 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 675 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 676 } 677 } 678 679 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 680 } 681 682 public: 683 WindowsTargetInfo(const llvm::Triple &Triple) 684 : OSTargetInfo<Target>(Triple) {} 685 }; 686 687 template <typename Target> 688 class NaClTargetInfo : public OSTargetInfo<Target> { 689 protected: 690 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 691 MacroBuilder &Builder) const override { 692 if (Opts.POSIXThreads) 693 Builder.defineMacro("_REENTRANT"); 694 if (Opts.CPlusPlus) 695 Builder.defineMacro("_GNU_SOURCE"); 696 697 DefineStd(Builder, "unix", Opts); 698 Builder.defineMacro("__ELF__"); 699 Builder.defineMacro("__native_client__"); 700 } 701 702 public: 703 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 704 this->UserLabelPrefix = ""; 705 this->LongAlign = 32; 706 this->LongWidth = 32; 707 this->PointerAlign = 32; 708 this->PointerWidth = 32; 709 this->IntMaxType = TargetInfo::SignedLongLong; 710 this->Int64Type = TargetInfo::SignedLongLong; 711 this->DoubleAlign = 64; 712 this->LongDoubleWidth = 64; 713 this->LongDoubleAlign = 64; 714 this->LongLongWidth = 64; 715 this->LongLongAlign = 64; 716 this->SizeType = TargetInfo::UnsignedInt; 717 this->PtrDiffType = TargetInfo::SignedInt; 718 this->IntPtrType = TargetInfo::SignedInt; 719 // RegParmMax is inherited from the underlying architecture 720 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 721 if (Triple.getArch() == llvm::Triple::arm) { 722 // Handled in ARM's setABI(). 723 } else if (Triple.getArch() == llvm::Triple::x86) { 724 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 725 } else if (Triple.getArch() == llvm::Triple::x86_64) { 726 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 727 } else if (Triple.getArch() == llvm::Triple::mipsel) { 728 // Handled on mips' setDescriptionString. 729 } else { 730 assert(Triple.getArch() == llvm::Triple::le32); 731 this->DescriptionString = "e-p:32:32-i64:64"; 732 } 733 } 734 }; 735 736 //===----------------------------------------------------------------------===// 737 // Specific target implementations. 738 //===----------------------------------------------------------------------===// 739 740 // PPC abstract base class 741 class PPCTargetInfo : public TargetInfo { 742 static const Builtin::Info BuiltinInfo[]; 743 static const char * const GCCRegNames[]; 744 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 745 std::string CPU; 746 747 // Target cpu features. 748 bool HasVSX; 749 bool HasP8Vector; 750 bool HasP8Crypto; 751 bool HasDirectMove; 752 bool HasQPX; 753 bool HasHTM; 754 bool HasBPERMD; 755 bool HasExtDiv; 756 757 protected: 758 std::string ABI; 759 760 public: 761 PPCTargetInfo(const llvm::Triple &Triple) 762 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 763 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 764 HasBPERMD(false), HasExtDiv(false) { 765 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 766 SimdDefaultAlign = 128; 767 LongDoubleWidth = LongDoubleAlign = 128; 768 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 769 } 770 771 /// \brief Flags for architecture specific defines. 772 typedef enum { 773 ArchDefineNone = 0, 774 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 775 ArchDefinePpcgr = 1 << 1, 776 ArchDefinePpcsq = 1 << 2, 777 ArchDefine440 = 1 << 3, 778 ArchDefine603 = 1 << 4, 779 ArchDefine604 = 1 << 5, 780 ArchDefinePwr4 = 1 << 6, 781 ArchDefinePwr5 = 1 << 7, 782 ArchDefinePwr5x = 1 << 8, 783 ArchDefinePwr6 = 1 << 9, 784 ArchDefinePwr6x = 1 << 10, 785 ArchDefinePwr7 = 1 << 11, 786 ArchDefinePwr8 = 1 << 12, 787 ArchDefineA2 = 1 << 13, 788 ArchDefineA2q = 1 << 14 789 } ArchDefineTypes; 790 791 // Note: GCC recognizes the following additional cpus: 792 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 793 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 794 // titan, rs64. 795 bool setCPU(const std::string &Name) override { 796 bool CPUKnown = llvm::StringSwitch<bool>(Name) 797 .Case("generic", true) 798 .Case("440", true) 799 .Case("450", true) 800 .Case("601", true) 801 .Case("602", true) 802 .Case("603", true) 803 .Case("603e", true) 804 .Case("603ev", true) 805 .Case("604", true) 806 .Case("604e", true) 807 .Case("620", true) 808 .Case("630", true) 809 .Case("g3", true) 810 .Case("7400", true) 811 .Case("g4", true) 812 .Case("7450", true) 813 .Case("g4+", true) 814 .Case("750", true) 815 .Case("970", true) 816 .Case("g5", true) 817 .Case("a2", true) 818 .Case("a2q", true) 819 .Case("e500mc", true) 820 .Case("e5500", true) 821 .Case("power3", true) 822 .Case("pwr3", true) 823 .Case("power4", true) 824 .Case("pwr4", true) 825 .Case("power5", true) 826 .Case("pwr5", true) 827 .Case("power5x", true) 828 .Case("pwr5x", true) 829 .Case("power6", true) 830 .Case("pwr6", true) 831 .Case("power6x", true) 832 .Case("pwr6x", true) 833 .Case("power7", true) 834 .Case("pwr7", true) 835 .Case("power8", true) 836 .Case("pwr8", true) 837 .Case("powerpc", true) 838 .Case("ppc", true) 839 .Case("powerpc64", true) 840 .Case("ppc64", true) 841 .Case("powerpc64le", true) 842 .Case("ppc64le", true) 843 .Default(false); 844 845 if (CPUKnown) 846 CPU = Name; 847 848 return CPUKnown; 849 } 850 851 852 StringRef getABI() const override { return ABI; } 853 854 void getTargetBuiltins(const Builtin::Info *&Records, 855 unsigned &NumRecords) const override { 856 Records = BuiltinInfo; 857 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 858 } 859 860 bool isCLZForZeroUndef() const override { return false; } 861 862 void getTargetDefines(const LangOptions &Opts, 863 MacroBuilder &Builder) const override; 864 865 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 866 867 bool handleTargetFeatures(std::vector<std::string> &Features, 868 DiagnosticsEngine &Diags) override; 869 bool hasFeature(StringRef Feature) const override; 870 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 871 bool Enabled) const override; 872 873 void getGCCRegNames(const char * const *&Names, 874 unsigned &NumNames) const override; 875 void getGCCRegAliases(const GCCRegAlias *&Aliases, 876 unsigned &NumAliases) const override; 877 bool validateAsmConstraint(const char *&Name, 878 TargetInfo::ConstraintInfo &Info) const override { 879 switch (*Name) { 880 default: return false; 881 case 'O': // Zero 882 break; 883 case 'b': // Base register 884 case 'f': // Floating point register 885 Info.setAllowsRegister(); 886 break; 887 // FIXME: The following are added to allow parsing. 888 // I just took a guess at what the actions should be. 889 // Also, is more specific checking needed? I.e. specific registers? 890 case 'd': // Floating point register (containing 64-bit value) 891 case 'v': // Altivec vector register 892 Info.setAllowsRegister(); 893 break; 894 case 'w': 895 switch (Name[1]) { 896 case 'd':// VSX vector register to hold vector double data 897 case 'f':// VSX vector register to hold vector float data 898 case 's':// VSX vector register to hold scalar float data 899 case 'a':// Any VSX register 900 case 'c':// An individual CR bit 901 break; 902 default: 903 return false; 904 } 905 Info.setAllowsRegister(); 906 Name++; // Skip over 'w'. 907 break; 908 case 'h': // `MQ', `CTR', or `LINK' register 909 case 'q': // `MQ' register 910 case 'c': // `CTR' register 911 case 'l': // `LINK' register 912 case 'x': // `CR' register (condition register) number 0 913 case 'y': // `CR' register (condition register) 914 case 'z': // `XER[CA]' carry bit (part of the XER register) 915 Info.setAllowsRegister(); 916 break; 917 case 'I': // Signed 16-bit constant 918 case 'J': // Unsigned 16-bit constant shifted left 16 bits 919 // (use `L' instead for SImode constants) 920 case 'K': // Unsigned 16-bit constant 921 case 'L': // Signed 16-bit constant shifted left 16 bits 922 case 'M': // Constant larger than 31 923 case 'N': // Exact power of 2 924 case 'P': // Constant whose negation is a signed 16-bit constant 925 case 'G': // Floating point constant that can be loaded into a 926 // register with one instruction per word 927 case 'H': // Integer/Floating point constant that can be loaded 928 // into a register using three instructions 929 break; 930 case 'm': // Memory operand. Note that on PowerPC targets, m can 931 // include addresses that update the base register. It 932 // is therefore only safe to use `m' in an asm statement 933 // if that asm statement accesses the operand exactly once. 934 // The asm statement must also use `%U<opno>' as a 935 // placeholder for the "update" flag in the corresponding 936 // load or store instruction. For example: 937 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 938 // is correct but: 939 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 940 // is not. Use es rather than m if you don't want the base 941 // register to be updated. 942 case 'e': 943 if (Name[1] != 's') 944 return false; 945 // es: A "stable" memory operand; that is, one which does not 946 // include any automodification of the base register. Unlike 947 // `m', this constraint can be used in asm statements that 948 // might access the operand several times, or that might not 949 // access it at all. 950 Info.setAllowsMemory(); 951 Name++; // Skip over 'e'. 952 break; 953 case 'Q': // Memory operand that is an offset from a register (it is 954 // usually better to use `m' or `es' in asm statements) 955 case 'Z': // Memory operand that is an indexed or indirect from a 956 // register (it is usually better to use `m' or `es' in 957 // asm statements) 958 Info.setAllowsMemory(); 959 Info.setAllowsRegister(); 960 break; 961 case 'R': // AIX TOC entry 962 case 'a': // Address operand that is an indexed or indirect from a 963 // register (`p' is preferable for asm statements) 964 case 'S': // Constant suitable as a 64-bit mask operand 965 case 'T': // Constant suitable as a 32-bit mask operand 966 case 'U': // System V Release 4 small data area reference 967 case 't': // AND masks that can be performed by two rldic{l, r} 968 // instructions 969 case 'W': // Vector constant that does not require memory 970 case 'j': // Vector constant that is all zeros. 971 break; 972 // End FIXME. 973 } 974 return true; 975 } 976 std::string convertConstraint(const char *&Constraint) const override { 977 std::string R; 978 switch (*Constraint) { 979 case 'e': 980 case 'w': 981 // Two-character constraint; add "^" hint for later parsing. 982 R = std::string("^") + std::string(Constraint, 2); 983 Constraint++; 984 break; 985 default: 986 return TargetInfo::convertConstraint(Constraint); 987 } 988 return R; 989 } 990 const char *getClobbers() const override { 991 return ""; 992 } 993 int getEHDataRegisterNumber(unsigned RegNo) const override { 994 if (RegNo == 0) return 3; 995 if (RegNo == 1) return 4; 996 return -1; 997 } 998 999 bool hasSjLjLowering() const override { 1000 return true; 1001 } 1002 1003 bool useFloat128ManglingForLongDouble() const override { 1004 return LongDoubleWidth == 128 && 1005 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1006 getTriple().isOSBinFormatELF(); 1007 } 1008 }; 1009 1010 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1011 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1012 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1013 ALL_LANGUAGES }, 1014 #include "clang/Basic/BuiltinsPPC.def" 1015 }; 1016 1017 /// handleTargetFeatures - Perform initialization based on the user 1018 /// configured set of features. 1019 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1020 DiagnosticsEngine &Diags) { 1021 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1022 // Ignore disabled features. 1023 if (Features[i][0] == '-') 1024 continue; 1025 1026 StringRef Feature = StringRef(Features[i]).substr(1); 1027 1028 if (Feature == "vsx") { 1029 HasVSX = true; 1030 continue; 1031 } 1032 1033 if (Feature == "bpermd") { 1034 HasBPERMD = true; 1035 continue; 1036 } 1037 1038 if (Feature == "extdiv") { 1039 HasExtDiv = true; 1040 continue; 1041 } 1042 1043 if (Feature == "power8-vector") { 1044 HasP8Vector = true; 1045 continue; 1046 } 1047 1048 if (Feature == "crypto") { 1049 HasP8Crypto = true; 1050 continue; 1051 } 1052 1053 if (Feature == "direct-move") { 1054 HasDirectMove = true; 1055 continue; 1056 } 1057 1058 if (Feature == "qpx") { 1059 HasQPX = true; 1060 continue; 1061 } 1062 1063 if (Feature == "htm") { 1064 HasHTM = true; 1065 continue; 1066 } 1067 1068 // TODO: Finish this list and add an assert that we've handled them 1069 // all. 1070 } 1071 if (!HasVSX && (HasP8Vector || HasDirectMove)) { 1072 if (HasP8Vector) 1073 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" << 1074 "-mno-vsx"; 1075 else if (HasDirectMove) 1076 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" << 1077 "-mno-vsx"; 1078 return false; 1079 } 1080 1081 return true; 1082 } 1083 1084 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1085 /// #defines that are not tied to a specific subtarget. 1086 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1087 MacroBuilder &Builder) const { 1088 // Target identification. 1089 Builder.defineMacro("__ppc__"); 1090 Builder.defineMacro("__PPC__"); 1091 Builder.defineMacro("_ARCH_PPC"); 1092 Builder.defineMacro("__powerpc__"); 1093 Builder.defineMacro("__POWERPC__"); 1094 if (PointerWidth == 64) { 1095 Builder.defineMacro("_ARCH_PPC64"); 1096 Builder.defineMacro("__powerpc64__"); 1097 Builder.defineMacro("__ppc64__"); 1098 Builder.defineMacro("__PPC64__"); 1099 } 1100 1101 // Target properties. 1102 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1103 Builder.defineMacro("_LITTLE_ENDIAN"); 1104 } else { 1105 if (getTriple().getOS() != llvm::Triple::NetBSD && 1106 getTriple().getOS() != llvm::Triple::OpenBSD) 1107 Builder.defineMacro("_BIG_ENDIAN"); 1108 } 1109 1110 // ABI options. 1111 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1112 Builder.defineMacro("_CALL_ELF", "1"); 1113 if (ABI == "elfv2") 1114 Builder.defineMacro("_CALL_ELF", "2"); 1115 1116 // Subtarget options. 1117 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1118 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1119 1120 // FIXME: Should be controlled by command line option. 1121 if (LongDoubleWidth == 128) 1122 Builder.defineMacro("__LONG_DOUBLE_128__"); 1123 1124 if (Opts.AltiVec) { 1125 Builder.defineMacro("__VEC__", "10206"); 1126 Builder.defineMacro("__ALTIVEC__"); 1127 } 1128 1129 // CPU identification. 1130 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1131 .Case("440", ArchDefineName) 1132 .Case("450", ArchDefineName | ArchDefine440) 1133 .Case("601", ArchDefineName) 1134 .Case("602", ArchDefineName | ArchDefinePpcgr) 1135 .Case("603", ArchDefineName | ArchDefinePpcgr) 1136 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1137 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1138 .Case("604", ArchDefineName | ArchDefinePpcgr) 1139 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1140 .Case("620", ArchDefineName | ArchDefinePpcgr) 1141 .Case("630", ArchDefineName | ArchDefinePpcgr) 1142 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1143 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1144 .Case("750", ArchDefineName | ArchDefinePpcgr) 1145 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1146 | ArchDefinePpcsq) 1147 .Case("a2", ArchDefineA2) 1148 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1149 .Case("pwr3", ArchDefinePpcgr) 1150 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1152 | ArchDefinePpcsq) 1153 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1154 | ArchDefinePpcgr | ArchDefinePpcsq) 1155 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1156 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1157 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1158 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1159 | ArchDefinePpcsq) 1160 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1161 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1162 | ArchDefinePpcgr | ArchDefinePpcsq) 1163 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1164 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1165 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1166 .Case("power3", ArchDefinePpcgr) 1167 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1169 | ArchDefinePpcsq) 1170 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1171 | ArchDefinePpcgr | ArchDefinePpcsq) 1172 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1175 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1176 | ArchDefinePpcsq) 1177 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1178 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1179 | ArchDefinePpcgr | ArchDefinePpcsq) 1180 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1181 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1182 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Default(ArchDefineNone); 1184 1185 if (defs & ArchDefineName) 1186 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1187 if (defs & ArchDefinePpcgr) 1188 Builder.defineMacro("_ARCH_PPCGR"); 1189 if (defs & ArchDefinePpcsq) 1190 Builder.defineMacro("_ARCH_PPCSQ"); 1191 if (defs & ArchDefine440) 1192 Builder.defineMacro("_ARCH_440"); 1193 if (defs & ArchDefine603) 1194 Builder.defineMacro("_ARCH_603"); 1195 if (defs & ArchDefine604) 1196 Builder.defineMacro("_ARCH_604"); 1197 if (defs & ArchDefinePwr4) 1198 Builder.defineMacro("_ARCH_PWR4"); 1199 if (defs & ArchDefinePwr5) 1200 Builder.defineMacro("_ARCH_PWR5"); 1201 if (defs & ArchDefinePwr5x) 1202 Builder.defineMacro("_ARCH_PWR5X"); 1203 if (defs & ArchDefinePwr6) 1204 Builder.defineMacro("_ARCH_PWR6"); 1205 if (defs & ArchDefinePwr6x) 1206 Builder.defineMacro("_ARCH_PWR6X"); 1207 if (defs & ArchDefinePwr7) 1208 Builder.defineMacro("_ARCH_PWR7"); 1209 if (defs & ArchDefinePwr8) 1210 Builder.defineMacro("_ARCH_PWR8"); 1211 if (defs & ArchDefineA2) 1212 Builder.defineMacro("_ARCH_A2"); 1213 if (defs & ArchDefineA2q) { 1214 Builder.defineMacro("_ARCH_A2Q"); 1215 Builder.defineMacro("_ARCH_QP"); 1216 } 1217 1218 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1219 Builder.defineMacro("__bg__"); 1220 Builder.defineMacro("__THW_BLUEGENE__"); 1221 Builder.defineMacro("__bgq__"); 1222 Builder.defineMacro("__TOS_BGQ__"); 1223 } 1224 1225 if (HasVSX) 1226 Builder.defineMacro("__VSX__"); 1227 if (HasP8Vector) 1228 Builder.defineMacro("__POWER8_VECTOR__"); 1229 if (HasP8Crypto) 1230 Builder.defineMacro("__CRYPTO__"); 1231 if (HasHTM) 1232 Builder.defineMacro("__HTM__"); 1233 if (getTriple().getArch() == llvm::Triple::ppc64le || 1234 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1236 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1237 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1238 if (PointerWidth == 64) 1239 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1240 } 1241 1242 // FIXME: The following are not yet generated here by Clang, but are 1243 // generated by GCC: 1244 // 1245 // _SOFT_FLOAT_ 1246 // __RECIP_PRECISION__ 1247 // __APPLE_ALTIVEC__ 1248 // __RECIP__ 1249 // __RECIPF__ 1250 // __RSQRTE__ 1251 // __RSQRTEF__ 1252 // _SOFT_DOUBLE_ 1253 // __NO_LWSYNC__ 1254 // __HAVE_BSWAP__ 1255 // __LONGDOUBLE128 1256 // __CMODEL_MEDIUM__ 1257 // __CMODEL_LARGE__ 1258 // _CALL_SYSV 1259 // _CALL_DARWIN 1260 // __NO_FPRS__ 1261 } 1262 1263 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1264 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1265 .Case("7400", true) 1266 .Case("g4", true) 1267 .Case("7450", true) 1268 .Case("g4+", true) 1269 .Case("970", true) 1270 .Case("g5", true) 1271 .Case("pwr6", true) 1272 .Case("pwr7", true) 1273 .Case("pwr8", true) 1274 .Case("ppc64", true) 1275 .Case("ppc64le", true) 1276 .Default(false); 1277 1278 Features["qpx"] = (CPU == "a2q"); 1279 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1280 .Case("ppc64le", true) 1281 .Case("pwr8", true) 1282 .Default(false); 1283 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1284 .Case("ppc64le", true) 1285 .Case("pwr8", true) 1286 .Default(false); 1287 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("ppc64le", true) 1289 .Case("pwr8", true) 1290 .Case("pwr7", true) 1291 .Default(false); 1292 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1293 .Case("ppc64le", true) 1294 .Case("pwr8", true) 1295 .Case("pwr7", true) 1296 .Default(false); 1297 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1298 .Case("ppc64le", true) 1299 .Case("pwr8", true) 1300 .Default(false); 1301 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1302 .Case("ppc64le", true) 1303 .Case("pwr8", true) 1304 .Case("pwr7", true) 1305 .Default(false); 1306 } 1307 1308 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1309 return llvm::StringSwitch<bool>(Feature) 1310 .Case("powerpc", true) 1311 .Case("vsx", HasVSX) 1312 .Case("power8-vector", HasP8Vector) 1313 .Case("crypto", HasP8Crypto) 1314 .Case("direct-move", HasDirectMove) 1315 .Case("qpx", HasQPX) 1316 .Case("htm", HasHTM) 1317 .Case("bpermd", HasBPERMD) 1318 .Case("extdiv", HasExtDiv) 1319 .Default(false); 1320 } 1321 1322 /* There is no clear way for the target to know which of the features in the 1323 final feature vector came from defaults and which are actually specified by 1324 the user. To that end, we use the fact that this function is not called on 1325 default features - only user specified ones. By the first time this 1326 function is called, the default features are populated. 1327 We then keep track of the features that the user specified so that we 1328 can ensure we do not override a user's request (only defaults). 1329 For example: 1330 -mcpu=pwr8 -mno-vsx (should disable vsx and everything that depends on it) 1331 -mcpu=pwr8 -mdirect-move -mno-vsx (should actually be diagnosed) 1332 1333 NOTE: Do not call this from PPCTargetInfo::getDefaultFeatures 1334 */ 1335 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1336 StringRef Name, bool Enabled) const { 1337 static llvm::StringMap<bool> ExplicitFeatures; 1338 ExplicitFeatures[Name] = Enabled; 1339 1340 // At this point, -mno-vsx turns off the dependent features but we respect 1341 // the user's requests. 1342 if (!Enabled && Name == "vsx") { 1343 Features["direct-move"] = ExplicitFeatures["direct-move"]; 1344 Features["power8-vector"] = ExplicitFeatures["power8-vector"]; 1345 } 1346 if ((Enabled && Name == "power8-vector") || 1347 (Enabled && Name == "direct-move")) { 1348 if (ExplicitFeatures.find("vsx") == ExplicitFeatures.end()) { 1349 Features["vsx"] = true; 1350 } 1351 } 1352 Features[Name] = Enabled; 1353 } 1354 1355 const char * const PPCTargetInfo::GCCRegNames[] = { 1356 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1357 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1358 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1359 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1360 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1361 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1362 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1363 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1364 "mq", "lr", "ctr", "ap", 1365 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1366 "xer", 1367 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1368 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1369 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1370 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1371 "vrsave", "vscr", 1372 "spe_acc", "spefscr", 1373 "sfp" 1374 }; 1375 1376 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1377 unsigned &NumNames) const { 1378 Names = GCCRegNames; 1379 NumNames = llvm::array_lengthof(GCCRegNames); 1380 } 1381 1382 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1383 // While some of these aliases do map to different registers 1384 // they still share the same register name. 1385 { { "0" }, "r0" }, 1386 { { "1"}, "r1" }, 1387 { { "2" }, "r2" }, 1388 { { "3" }, "r3" }, 1389 { { "4" }, "r4" }, 1390 { { "5" }, "r5" }, 1391 { { "6" }, "r6" }, 1392 { { "7" }, "r7" }, 1393 { { "8" }, "r8" }, 1394 { { "9" }, "r9" }, 1395 { { "10" }, "r10" }, 1396 { { "11" }, "r11" }, 1397 { { "12" }, "r12" }, 1398 { { "13" }, "r13" }, 1399 { { "14" }, "r14" }, 1400 { { "15" }, "r15" }, 1401 { { "16" }, "r16" }, 1402 { { "17" }, "r17" }, 1403 { { "18" }, "r18" }, 1404 { { "19" }, "r19" }, 1405 { { "20" }, "r20" }, 1406 { { "21" }, "r21" }, 1407 { { "22" }, "r22" }, 1408 { { "23" }, "r23" }, 1409 { { "24" }, "r24" }, 1410 { { "25" }, "r25" }, 1411 { { "26" }, "r26" }, 1412 { { "27" }, "r27" }, 1413 { { "28" }, "r28" }, 1414 { { "29" }, "r29" }, 1415 { { "30" }, "r30" }, 1416 { { "31" }, "r31" }, 1417 { { "fr0" }, "f0" }, 1418 { { "fr1" }, "f1" }, 1419 { { "fr2" }, "f2" }, 1420 { { "fr3" }, "f3" }, 1421 { { "fr4" }, "f4" }, 1422 { { "fr5" }, "f5" }, 1423 { { "fr6" }, "f6" }, 1424 { { "fr7" }, "f7" }, 1425 { { "fr8" }, "f8" }, 1426 { { "fr9" }, "f9" }, 1427 { { "fr10" }, "f10" }, 1428 { { "fr11" }, "f11" }, 1429 { { "fr12" }, "f12" }, 1430 { { "fr13" }, "f13" }, 1431 { { "fr14" }, "f14" }, 1432 { { "fr15" }, "f15" }, 1433 { { "fr16" }, "f16" }, 1434 { { "fr17" }, "f17" }, 1435 { { "fr18" }, "f18" }, 1436 { { "fr19" }, "f19" }, 1437 { { "fr20" }, "f20" }, 1438 { { "fr21" }, "f21" }, 1439 { { "fr22" }, "f22" }, 1440 { { "fr23" }, "f23" }, 1441 { { "fr24" }, "f24" }, 1442 { { "fr25" }, "f25" }, 1443 { { "fr26" }, "f26" }, 1444 { { "fr27" }, "f27" }, 1445 { { "fr28" }, "f28" }, 1446 { { "fr29" }, "f29" }, 1447 { { "fr30" }, "f30" }, 1448 { { "fr31" }, "f31" }, 1449 { { "cc" }, "cr0" }, 1450 }; 1451 1452 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1453 unsigned &NumAliases) const { 1454 Aliases = GCCRegAliases; 1455 NumAliases = llvm::array_lengthof(GCCRegAliases); 1456 } 1457 1458 class PPC32TargetInfo : public PPCTargetInfo { 1459 public: 1460 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1461 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1462 1463 switch (getTriple().getOS()) { 1464 case llvm::Triple::Linux: 1465 case llvm::Triple::FreeBSD: 1466 case llvm::Triple::NetBSD: 1467 SizeType = UnsignedInt; 1468 PtrDiffType = SignedInt; 1469 IntPtrType = SignedInt; 1470 break; 1471 default: 1472 break; 1473 } 1474 1475 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1476 LongDoubleWidth = LongDoubleAlign = 64; 1477 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1478 } 1479 1480 // PPC32 supports atomics up to 4 bytes. 1481 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1482 } 1483 1484 BuiltinVaListKind getBuiltinVaListKind() const override { 1485 // This is the ELF definition, and is overridden by the Darwin sub-target 1486 return TargetInfo::PowerABIBuiltinVaList; 1487 } 1488 }; 1489 1490 // Note: ABI differences may eventually require us to have a separate 1491 // TargetInfo for little endian. 1492 class PPC64TargetInfo : public PPCTargetInfo { 1493 public: 1494 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1495 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1496 IntMaxType = SignedLong; 1497 Int64Type = SignedLong; 1498 1499 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1500 DescriptionString = "e-m:e-i64:64-n32:64"; 1501 ABI = "elfv2"; 1502 } else { 1503 DescriptionString = "E-m:e-i64:64-n32:64"; 1504 ABI = "elfv1"; 1505 } 1506 1507 switch (getTriple().getOS()) { 1508 case llvm::Triple::FreeBSD: 1509 LongDoubleWidth = LongDoubleAlign = 64; 1510 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1511 break; 1512 case llvm::Triple::NetBSD: 1513 IntMaxType = SignedLongLong; 1514 Int64Type = SignedLongLong; 1515 break; 1516 default: 1517 break; 1518 } 1519 1520 // PPC64 supports atomics up to 8 bytes. 1521 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1522 } 1523 BuiltinVaListKind getBuiltinVaListKind() const override { 1524 return TargetInfo::CharPtrBuiltinVaList; 1525 } 1526 // PPC64 Linux-specific ABI options. 1527 bool setABI(const std::string &Name) override { 1528 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1529 ABI = Name; 1530 return true; 1531 } 1532 return false; 1533 } 1534 }; 1535 1536 class DarwinPPC32TargetInfo : 1537 public DarwinTargetInfo<PPC32TargetInfo> { 1538 public: 1539 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1540 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1541 HasAlignMac68kSupport = true; 1542 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1543 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1544 LongLongAlign = 32; 1545 SuitableAlign = 128; 1546 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1547 } 1548 BuiltinVaListKind getBuiltinVaListKind() const override { 1549 return TargetInfo::CharPtrBuiltinVaList; 1550 } 1551 }; 1552 1553 class DarwinPPC64TargetInfo : 1554 public DarwinTargetInfo<PPC64TargetInfo> { 1555 public: 1556 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1557 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1558 HasAlignMac68kSupport = true; 1559 SuitableAlign = 128; 1560 DescriptionString = "E-m:o-i64:64-n32:64"; 1561 } 1562 }; 1563 1564 static const unsigned NVPTXAddrSpaceMap[] = { 1565 1, // opencl_global 1566 3, // opencl_local 1567 4, // opencl_constant 1568 // FIXME: generic has to be added to the target 1569 0, // opencl_generic 1570 1, // cuda_device 1571 4, // cuda_constant 1572 3, // cuda_shared 1573 }; 1574 class NVPTXTargetInfo : public TargetInfo { 1575 static const char * const GCCRegNames[]; 1576 static const Builtin::Info BuiltinInfo[]; 1577 1578 // The GPU profiles supported by the NVPTX backend 1579 enum GPUKind { 1580 GK_NONE, 1581 GK_SM20, 1582 GK_SM21, 1583 GK_SM30, 1584 GK_SM35, 1585 GK_SM37, 1586 } GPU; 1587 1588 public: 1589 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1590 BigEndian = false; 1591 TLSSupported = false; 1592 LongWidth = LongAlign = 64; 1593 AddrSpaceMap = &NVPTXAddrSpaceMap; 1594 UseAddrSpaceMapMangling = true; 1595 // Define available target features 1596 // These must be defined in sorted order! 1597 NoAsmVariants = true; 1598 // Set the default GPU to sm20 1599 GPU = GK_SM20; 1600 } 1601 void getTargetDefines(const LangOptions &Opts, 1602 MacroBuilder &Builder) const override { 1603 Builder.defineMacro("__PTX__"); 1604 Builder.defineMacro("__NVPTX__"); 1605 if (Opts.CUDAIsDevice) { 1606 // Set __CUDA_ARCH__ for the GPU specified. 1607 std::string CUDAArchCode; 1608 switch (GPU) { 1609 case GK_SM20: 1610 CUDAArchCode = "200"; 1611 break; 1612 case GK_SM21: 1613 CUDAArchCode = "210"; 1614 break; 1615 case GK_SM30: 1616 CUDAArchCode = "300"; 1617 break; 1618 case GK_SM35: 1619 CUDAArchCode = "350"; 1620 break; 1621 case GK_SM37: 1622 CUDAArchCode = "370"; 1623 break; 1624 default: 1625 llvm_unreachable("Unhandled target CPU"); 1626 } 1627 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1628 } 1629 } 1630 void getTargetBuiltins(const Builtin::Info *&Records, 1631 unsigned &NumRecords) const override { 1632 Records = BuiltinInfo; 1633 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1634 } 1635 bool hasFeature(StringRef Feature) const override { 1636 return Feature == "ptx" || Feature == "nvptx"; 1637 } 1638 1639 void getGCCRegNames(const char * const *&Names, 1640 unsigned &NumNames) const override; 1641 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1642 unsigned &NumAliases) const override { 1643 // No aliases. 1644 Aliases = nullptr; 1645 NumAliases = 0; 1646 } 1647 bool 1648 validateAsmConstraint(const char *&Name, 1649 TargetInfo::ConstraintInfo &Info) const override { 1650 switch (*Name) { 1651 default: return false; 1652 case 'c': 1653 case 'h': 1654 case 'r': 1655 case 'l': 1656 case 'f': 1657 case 'd': 1658 Info.setAllowsRegister(); 1659 return true; 1660 } 1661 } 1662 const char *getClobbers() const override { 1663 // FIXME: Is this really right? 1664 return ""; 1665 } 1666 BuiltinVaListKind getBuiltinVaListKind() const override { 1667 // FIXME: implement 1668 return TargetInfo::CharPtrBuiltinVaList; 1669 } 1670 bool setCPU(const std::string &Name) override { 1671 GPU = llvm::StringSwitch<GPUKind>(Name) 1672 .Case("sm_20", GK_SM20) 1673 .Case("sm_21", GK_SM21) 1674 .Case("sm_30", GK_SM30) 1675 .Case("sm_35", GK_SM35) 1676 .Case("sm_37", GK_SM37) 1677 .Default(GK_NONE); 1678 1679 return GPU != GK_NONE; 1680 } 1681 }; 1682 1683 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1684 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1685 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1686 ALL_LANGUAGES }, 1687 #include "clang/Basic/BuiltinsNVPTX.def" 1688 }; 1689 1690 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1691 "r0" 1692 }; 1693 1694 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1695 unsigned &NumNames) const { 1696 Names = GCCRegNames; 1697 NumNames = llvm::array_lengthof(GCCRegNames); 1698 } 1699 1700 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1701 public: 1702 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1703 PointerWidth = PointerAlign = 32; 1704 SizeType = TargetInfo::UnsignedInt; 1705 PtrDiffType = TargetInfo::SignedInt; 1706 IntPtrType = TargetInfo::SignedInt; 1707 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1708 } 1709 }; 1710 1711 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1712 public: 1713 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1714 PointerWidth = PointerAlign = 64; 1715 SizeType = TargetInfo::UnsignedLong; 1716 PtrDiffType = TargetInfo::SignedLong; 1717 IntPtrType = TargetInfo::SignedLong; 1718 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1719 } 1720 }; 1721 1722 static const unsigned AMDGPUAddrSpaceMap[] = { 1723 1, // opencl_global 1724 3, // opencl_local 1725 2, // opencl_constant 1726 4, // opencl_generic 1727 1, // cuda_device 1728 2, // cuda_constant 1729 3 // cuda_shared 1730 }; 1731 1732 // If you edit the description strings, make sure you update 1733 // getPointerWidthV(). 1734 1735 static const char *DescriptionStringR600 = 1736 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1737 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1738 1739 static const char *DescriptionStringR600DoubleOps = 1740 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1741 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1742 1743 static const char *DescriptionStringSI = 1744 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1745 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1746 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1747 1748 class AMDGPUTargetInfo : public TargetInfo { 1749 static const Builtin::Info BuiltinInfo[]; 1750 static const char * const GCCRegNames[]; 1751 1752 /// \brief The GPU profiles supported by the AMDGPU target. 1753 enum GPUKind { 1754 GK_NONE, 1755 GK_R600, 1756 GK_R600_DOUBLE_OPS, 1757 GK_R700, 1758 GK_R700_DOUBLE_OPS, 1759 GK_EVERGREEN, 1760 GK_EVERGREEN_DOUBLE_OPS, 1761 GK_NORTHERN_ISLANDS, 1762 GK_CAYMAN, 1763 GK_SOUTHERN_ISLANDS, 1764 GK_SEA_ISLANDS, 1765 GK_VOLCANIC_ISLANDS 1766 } GPU; 1767 1768 bool hasFP64:1; 1769 bool hasFMAF:1; 1770 bool hasLDEXPF:1; 1771 1772 public: 1773 AMDGPUTargetInfo(const llvm::Triple &Triple) 1774 : TargetInfo(Triple) { 1775 1776 if (Triple.getArch() == llvm::Triple::amdgcn) { 1777 DescriptionString = DescriptionStringSI; 1778 GPU = GK_SOUTHERN_ISLANDS; 1779 hasFP64 = true; 1780 hasFMAF = true; 1781 hasLDEXPF = true; 1782 } else { 1783 DescriptionString = DescriptionStringR600; 1784 GPU = GK_R600; 1785 hasFP64 = false; 1786 hasFMAF = false; 1787 hasLDEXPF = false; 1788 } 1789 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1790 UseAddrSpaceMapMangling = true; 1791 } 1792 1793 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1794 if (GPU <= GK_CAYMAN) 1795 return 32; 1796 1797 switch(AddrSpace) { 1798 default: 1799 return 64; 1800 case 0: 1801 case 3: 1802 case 5: 1803 return 32; 1804 } 1805 } 1806 1807 const char * getClobbers() const override { 1808 return ""; 1809 } 1810 1811 void getGCCRegNames(const char * const *&Names, 1812 unsigned &NumNames) const override; 1813 1814 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1815 unsigned &NumAliases) const override { 1816 Aliases = nullptr; 1817 NumAliases = 0; 1818 } 1819 1820 bool validateAsmConstraint(const char *&Name, 1821 TargetInfo::ConstraintInfo &info) const override { 1822 return true; 1823 } 1824 1825 void getTargetBuiltins(const Builtin::Info *&Records, 1826 unsigned &NumRecords) const override { 1827 Records = BuiltinInfo; 1828 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1829 } 1830 1831 void getTargetDefines(const LangOptions &Opts, 1832 MacroBuilder &Builder) const override { 1833 Builder.defineMacro("__R600__"); 1834 if (hasFMAF) 1835 Builder.defineMacro("__HAS_FMAF__"); 1836 if (hasLDEXPF) 1837 Builder.defineMacro("__HAS_LDEXPF__"); 1838 if (hasFP64 && Opts.OpenCL) { 1839 Builder.defineMacro("cl_khr_fp64"); 1840 } 1841 } 1842 1843 BuiltinVaListKind getBuiltinVaListKind() const override { 1844 return TargetInfo::CharPtrBuiltinVaList; 1845 } 1846 1847 bool setCPU(const std::string &Name) override { 1848 GPU = llvm::StringSwitch<GPUKind>(Name) 1849 .Case("r600" , GK_R600) 1850 .Case("rv610", GK_R600) 1851 .Case("rv620", GK_R600) 1852 .Case("rv630", GK_R600) 1853 .Case("rv635", GK_R600) 1854 .Case("rs780", GK_R600) 1855 .Case("rs880", GK_R600) 1856 .Case("rv670", GK_R600_DOUBLE_OPS) 1857 .Case("rv710", GK_R700) 1858 .Case("rv730", GK_R700) 1859 .Case("rv740", GK_R700_DOUBLE_OPS) 1860 .Case("rv770", GK_R700_DOUBLE_OPS) 1861 .Case("palm", GK_EVERGREEN) 1862 .Case("cedar", GK_EVERGREEN) 1863 .Case("sumo", GK_EVERGREEN) 1864 .Case("sumo2", GK_EVERGREEN) 1865 .Case("redwood", GK_EVERGREEN) 1866 .Case("juniper", GK_EVERGREEN) 1867 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1868 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1869 .Case("barts", GK_NORTHERN_ISLANDS) 1870 .Case("turks", GK_NORTHERN_ISLANDS) 1871 .Case("caicos", GK_NORTHERN_ISLANDS) 1872 .Case("cayman", GK_CAYMAN) 1873 .Case("aruba", GK_CAYMAN) 1874 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1875 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1876 .Case("verde", GK_SOUTHERN_ISLANDS) 1877 .Case("oland", GK_SOUTHERN_ISLANDS) 1878 .Case("hainan", GK_SOUTHERN_ISLANDS) 1879 .Case("bonaire", GK_SEA_ISLANDS) 1880 .Case("kabini", GK_SEA_ISLANDS) 1881 .Case("kaveri", GK_SEA_ISLANDS) 1882 .Case("hawaii", GK_SEA_ISLANDS) 1883 .Case("mullins", GK_SEA_ISLANDS) 1884 .Case("tonga", GK_VOLCANIC_ISLANDS) 1885 .Case("iceland", GK_VOLCANIC_ISLANDS) 1886 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1887 .Default(GK_NONE); 1888 1889 if (GPU == GK_NONE) { 1890 return false; 1891 } 1892 1893 // Set the correct data layout 1894 switch (GPU) { 1895 case GK_NONE: 1896 case GK_R600: 1897 case GK_R700: 1898 case GK_EVERGREEN: 1899 case GK_NORTHERN_ISLANDS: 1900 DescriptionString = DescriptionStringR600; 1901 hasFP64 = false; 1902 hasFMAF = false; 1903 hasLDEXPF = false; 1904 break; 1905 case GK_R600_DOUBLE_OPS: 1906 case GK_R700_DOUBLE_OPS: 1907 case GK_EVERGREEN_DOUBLE_OPS: 1908 case GK_CAYMAN: 1909 DescriptionString = DescriptionStringR600DoubleOps; 1910 hasFP64 = true; 1911 hasFMAF = true; 1912 hasLDEXPF = false; 1913 break; 1914 case GK_SOUTHERN_ISLANDS: 1915 case GK_SEA_ISLANDS: 1916 case GK_VOLCANIC_ISLANDS: 1917 DescriptionString = DescriptionStringSI; 1918 hasFP64 = true; 1919 hasFMAF = true; 1920 hasLDEXPF = true; 1921 break; 1922 } 1923 1924 return true; 1925 } 1926 }; 1927 1928 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1929 #define BUILTIN(ID, TYPE, ATTRS) \ 1930 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1931 #include "clang/Basic/BuiltinsAMDGPU.def" 1932 }; 1933 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1934 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1935 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1936 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1937 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1938 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1939 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1940 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1941 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1942 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1943 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1944 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1945 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1946 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1947 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1948 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1949 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1950 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1951 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1952 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1953 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1954 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1955 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1956 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1957 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1958 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1959 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1960 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1961 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1962 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1963 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1964 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1965 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1966 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1967 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1968 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1969 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1970 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1971 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1972 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1973 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1974 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1975 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1976 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1977 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1978 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1979 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1980 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1981 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1982 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1983 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1984 }; 1985 1986 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 1987 unsigned &NumNames) const { 1988 Names = GCCRegNames; 1989 NumNames = llvm::array_lengthof(GCCRegNames); 1990 } 1991 1992 // Namespace for x86 abstract base class 1993 const Builtin::Info BuiltinInfo[] = { 1994 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1995 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1996 ALL_LANGUAGES }, 1997 #include "clang/Basic/BuiltinsX86.def" 1998 }; 1999 2000 static const char* const GCCRegNames[] = { 2001 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2002 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2003 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2004 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2005 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2006 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2007 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2008 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2009 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2010 }; 2011 2012 const TargetInfo::AddlRegName AddlRegNames[] = { 2013 { { "al", "ah", "eax", "rax" }, 0 }, 2014 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2015 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2016 { { "dl", "dh", "edx", "rdx" }, 1 }, 2017 { { "esi", "rsi" }, 4 }, 2018 { { "edi", "rdi" }, 5 }, 2019 { { "esp", "rsp" }, 7 }, 2020 { { "ebp", "rbp" }, 6 }, 2021 }; 2022 2023 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2024 // most of the implementation can be shared. 2025 class X86TargetInfo : public TargetInfo { 2026 enum X86SSEEnum { 2027 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2028 } SSELevel; 2029 enum MMX3DNowEnum { 2030 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2031 } MMX3DNowLevel; 2032 enum XOPEnum { 2033 NoXOP, 2034 SSE4A, 2035 FMA4, 2036 XOP 2037 } XOPLevel; 2038 2039 bool HasAES; 2040 bool HasPCLMUL; 2041 bool HasLZCNT; 2042 bool HasRDRND; 2043 bool HasFSGSBASE; 2044 bool HasBMI; 2045 bool HasBMI2; 2046 bool HasPOPCNT; 2047 bool HasRTM; 2048 bool HasPRFCHW; 2049 bool HasRDSEED; 2050 bool HasADX; 2051 bool HasTBM; 2052 bool HasFMA; 2053 bool HasF16C; 2054 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2055 HasAVX512VL; 2056 bool HasSHA; 2057 bool HasCX16; 2058 2059 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2060 /// 2061 /// Each enumeration represents a particular CPU supported by Clang. These 2062 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2063 enum CPUKind { 2064 CK_Generic, 2065 2066 /// \name i386 2067 /// i386-generation processors. 2068 //@{ 2069 CK_i386, 2070 //@} 2071 2072 /// \name i486 2073 /// i486-generation processors. 2074 //@{ 2075 CK_i486, 2076 CK_WinChipC6, 2077 CK_WinChip2, 2078 CK_C3, 2079 //@} 2080 2081 /// \name i586 2082 /// i586-generation processors, P5 microarchitecture based. 2083 //@{ 2084 CK_i586, 2085 CK_Pentium, 2086 CK_PentiumMMX, 2087 //@} 2088 2089 /// \name i686 2090 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2091 //@{ 2092 CK_i686, 2093 CK_PentiumPro, 2094 CK_Pentium2, 2095 CK_Pentium3, 2096 CK_Pentium3M, 2097 CK_PentiumM, 2098 CK_C3_2, 2099 2100 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2101 /// Clang however has some logic to suport this. 2102 // FIXME: Warn, deprecate, and potentially remove this. 2103 CK_Yonah, 2104 //@} 2105 2106 /// \name Netburst 2107 /// Netburst microarchitecture based processors. 2108 //@{ 2109 CK_Pentium4, 2110 CK_Pentium4M, 2111 CK_Prescott, 2112 CK_Nocona, 2113 //@} 2114 2115 /// \name Core 2116 /// Core microarchitecture based processors. 2117 //@{ 2118 CK_Core2, 2119 2120 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2121 /// codename which GCC no longer accepts as an option to -march, but Clang 2122 /// has some logic for recognizing it. 2123 // FIXME: Warn, deprecate, and potentially remove this. 2124 CK_Penryn, 2125 //@} 2126 2127 /// \name Atom 2128 /// Atom processors 2129 //@{ 2130 CK_Bonnell, 2131 CK_Silvermont, 2132 //@} 2133 2134 /// \name Nehalem 2135 /// Nehalem microarchitecture based processors. 2136 CK_Nehalem, 2137 2138 /// \name Westmere 2139 /// Westmere microarchitecture based processors. 2140 CK_Westmere, 2141 2142 /// \name Sandy Bridge 2143 /// Sandy Bridge microarchitecture based processors. 2144 CK_SandyBridge, 2145 2146 /// \name Ivy Bridge 2147 /// Ivy Bridge microarchitecture based processors. 2148 CK_IvyBridge, 2149 2150 /// \name Haswell 2151 /// Haswell microarchitecture based processors. 2152 CK_Haswell, 2153 2154 /// \name Broadwell 2155 /// Broadwell microarchitecture based processors. 2156 CK_Broadwell, 2157 2158 /// \name Skylake 2159 /// Skylake microarchitecture based processors. 2160 CK_Skylake, 2161 2162 /// \name Knights Landing 2163 /// Knights Landing processor. 2164 CK_KNL, 2165 2166 /// \name K6 2167 /// K6 architecture processors. 2168 //@{ 2169 CK_K6, 2170 CK_K6_2, 2171 CK_K6_3, 2172 //@} 2173 2174 /// \name K7 2175 /// K7 architecture processors. 2176 //@{ 2177 CK_Athlon, 2178 CK_AthlonThunderbird, 2179 CK_Athlon4, 2180 CK_AthlonXP, 2181 CK_AthlonMP, 2182 //@} 2183 2184 /// \name K8 2185 /// K8 architecture processors. 2186 //@{ 2187 CK_Athlon64, 2188 CK_Athlon64SSE3, 2189 CK_AthlonFX, 2190 CK_K8, 2191 CK_K8SSE3, 2192 CK_Opteron, 2193 CK_OpteronSSE3, 2194 CK_AMDFAM10, 2195 //@} 2196 2197 /// \name Bobcat 2198 /// Bobcat architecture processors. 2199 //@{ 2200 CK_BTVER1, 2201 CK_BTVER2, 2202 //@} 2203 2204 /// \name Bulldozer 2205 /// Bulldozer architecture processors. 2206 //@{ 2207 CK_BDVER1, 2208 CK_BDVER2, 2209 CK_BDVER3, 2210 CK_BDVER4, 2211 //@} 2212 2213 /// This specification is deprecated and will be removed in the future. 2214 /// Users should prefer \see CK_K8. 2215 // FIXME: Warn on this when the CPU is set to it. 2216 //@{ 2217 CK_x86_64, 2218 //@} 2219 2220 /// \name Geode 2221 /// Geode processors. 2222 //@{ 2223 CK_Geode 2224 //@} 2225 } CPU; 2226 2227 enum FPMathKind { 2228 FP_Default, 2229 FP_SSE, 2230 FP_387 2231 } FPMath; 2232 2233 public: 2234 X86TargetInfo(const llvm::Triple &Triple) 2235 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2236 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2237 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2238 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2239 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2240 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2241 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2242 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2243 BigEndian = false; 2244 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2245 } 2246 unsigned getFloatEvalMethod() const override { 2247 // X87 evaluates with 80 bits "long double" precision. 2248 return SSELevel == NoSSE ? 2 : 0; 2249 } 2250 void getTargetBuiltins(const Builtin::Info *&Records, 2251 unsigned &NumRecords) const override { 2252 Records = BuiltinInfo; 2253 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2254 } 2255 void getGCCRegNames(const char * const *&Names, 2256 unsigned &NumNames) const override { 2257 Names = GCCRegNames; 2258 NumNames = llvm::array_lengthof(GCCRegNames); 2259 } 2260 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2261 unsigned &NumAliases) const override { 2262 Aliases = nullptr; 2263 NumAliases = 0; 2264 } 2265 void getGCCAddlRegNames(const AddlRegName *&Names, 2266 unsigned &NumNames) const override { 2267 Names = AddlRegNames; 2268 NumNames = llvm::array_lengthof(AddlRegNames); 2269 } 2270 bool validateCpuSupports(StringRef Name) const override; 2271 bool validateAsmConstraint(const char *&Name, 2272 TargetInfo::ConstraintInfo &info) const override; 2273 2274 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2275 2276 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2277 2278 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2279 2280 std::string convertConstraint(const char *&Constraint) const override; 2281 const char *getClobbers() const override { 2282 return "~{dirflag},~{fpsr},~{flags}"; 2283 } 2284 void getTargetDefines(const LangOptions &Opts, 2285 MacroBuilder &Builder) const override; 2286 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2287 bool Enabled); 2288 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2289 bool Enabled); 2290 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2291 bool Enabled); 2292 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2293 StringRef Name, bool Enabled) const override { 2294 setFeatureEnabledImpl(Features, Name, Enabled); 2295 } 2296 // This exists purely to cut down on the number of virtual calls in 2297 // getDefaultFeatures which calls this repeatedly. 2298 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2299 StringRef Name, bool Enabled); 2300 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2301 bool hasFeature(StringRef Feature) const override; 2302 bool handleTargetFeatures(std::vector<std::string> &Features, 2303 DiagnosticsEngine &Diags) override; 2304 StringRef getABI() const override { 2305 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2306 return "avx512"; 2307 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2308 return "avx"; 2309 else if (getTriple().getArch() == llvm::Triple::x86 && 2310 MMX3DNowLevel == NoMMX3DNow) 2311 return "no-mmx"; 2312 return ""; 2313 } 2314 bool setCPU(const std::string &Name) override { 2315 CPU = llvm::StringSwitch<CPUKind>(Name) 2316 .Case("i386", CK_i386) 2317 .Case("i486", CK_i486) 2318 .Case("winchip-c6", CK_WinChipC6) 2319 .Case("winchip2", CK_WinChip2) 2320 .Case("c3", CK_C3) 2321 .Case("i586", CK_i586) 2322 .Case("pentium", CK_Pentium) 2323 .Case("pentium-mmx", CK_PentiumMMX) 2324 .Case("i686", CK_i686) 2325 .Case("pentiumpro", CK_PentiumPro) 2326 .Case("pentium2", CK_Pentium2) 2327 .Case("pentium3", CK_Pentium3) 2328 .Case("pentium3m", CK_Pentium3M) 2329 .Case("pentium-m", CK_PentiumM) 2330 .Case("c3-2", CK_C3_2) 2331 .Case("yonah", CK_Yonah) 2332 .Case("pentium4", CK_Pentium4) 2333 .Case("pentium4m", CK_Pentium4M) 2334 .Case("prescott", CK_Prescott) 2335 .Case("nocona", CK_Nocona) 2336 .Case("core2", CK_Core2) 2337 .Case("penryn", CK_Penryn) 2338 .Case("bonnell", CK_Bonnell) 2339 .Case("atom", CK_Bonnell) // Legacy name. 2340 .Case("silvermont", CK_Silvermont) 2341 .Case("slm", CK_Silvermont) // Legacy name. 2342 .Case("nehalem", CK_Nehalem) 2343 .Case("corei7", CK_Nehalem) // Legacy name. 2344 .Case("westmere", CK_Westmere) 2345 .Case("sandybridge", CK_SandyBridge) 2346 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2347 .Case("ivybridge", CK_IvyBridge) 2348 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2349 .Case("haswell", CK_Haswell) 2350 .Case("core-avx2", CK_Haswell) // Legacy name. 2351 .Case("broadwell", CK_Broadwell) 2352 .Case("skylake", CK_Skylake) 2353 .Case("skx", CK_Skylake) // Legacy name. 2354 .Case("knl", CK_KNL) 2355 .Case("k6", CK_K6) 2356 .Case("k6-2", CK_K6_2) 2357 .Case("k6-3", CK_K6_3) 2358 .Case("athlon", CK_Athlon) 2359 .Case("athlon-tbird", CK_AthlonThunderbird) 2360 .Case("athlon-4", CK_Athlon4) 2361 .Case("athlon-xp", CK_AthlonXP) 2362 .Case("athlon-mp", CK_AthlonMP) 2363 .Case("athlon64", CK_Athlon64) 2364 .Case("athlon64-sse3", CK_Athlon64SSE3) 2365 .Case("athlon-fx", CK_AthlonFX) 2366 .Case("k8", CK_K8) 2367 .Case("k8-sse3", CK_K8SSE3) 2368 .Case("opteron", CK_Opteron) 2369 .Case("opteron-sse3", CK_OpteronSSE3) 2370 .Case("barcelona", CK_AMDFAM10) 2371 .Case("amdfam10", CK_AMDFAM10) 2372 .Case("btver1", CK_BTVER1) 2373 .Case("btver2", CK_BTVER2) 2374 .Case("bdver1", CK_BDVER1) 2375 .Case("bdver2", CK_BDVER2) 2376 .Case("bdver3", CK_BDVER3) 2377 .Case("bdver4", CK_BDVER4) 2378 .Case("x86-64", CK_x86_64) 2379 .Case("geode", CK_Geode) 2380 .Default(CK_Generic); 2381 2382 // Perform any per-CPU checks necessary to determine if this CPU is 2383 // acceptable. 2384 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2385 // invalid without explaining *why*. 2386 switch (CPU) { 2387 case CK_Generic: 2388 // No processor selected! 2389 return false; 2390 2391 case CK_i386: 2392 case CK_i486: 2393 case CK_WinChipC6: 2394 case CK_WinChip2: 2395 case CK_C3: 2396 case CK_i586: 2397 case CK_Pentium: 2398 case CK_PentiumMMX: 2399 case CK_i686: 2400 case CK_PentiumPro: 2401 case CK_Pentium2: 2402 case CK_Pentium3: 2403 case CK_Pentium3M: 2404 case CK_PentiumM: 2405 case CK_Yonah: 2406 case CK_C3_2: 2407 case CK_Pentium4: 2408 case CK_Pentium4M: 2409 case CK_Prescott: 2410 case CK_K6: 2411 case CK_K6_2: 2412 case CK_K6_3: 2413 case CK_Athlon: 2414 case CK_AthlonThunderbird: 2415 case CK_Athlon4: 2416 case CK_AthlonXP: 2417 case CK_AthlonMP: 2418 case CK_Geode: 2419 // Only accept certain architectures when compiling in 32-bit mode. 2420 if (getTriple().getArch() != llvm::Triple::x86) 2421 return false; 2422 2423 // Fallthrough 2424 case CK_Nocona: 2425 case CK_Core2: 2426 case CK_Penryn: 2427 case CK_Bonnell: 2428 case CK_Silvermont: 2429 case CK_Nehalem: 2430 case CK_Westmere: 2431 case CK_SandyBridge: 2432 case CK_IvyBridge: 2433 case CK_Haswell: 2434 case CK_Broadwell: 2435 case CK_Skylake: 2436 case CK_KNL: 2437 case CK_Athlon64: 2438 case CK_Athlon64SSE3: 2439 case CK_AthlonFX: 2440 case CK_K8: 2441 case CK_K8SSE3: 2442 case CK_Opteron: 2443 case CK_OpteronSSE3: 2444 case CK_AMDFAM10: 2445 case CK_BTVER1: 2446 case CK_BTVER2: 2447 case CK_BDVER1: 2448 case CK_BDVER2: 2449 case CK_BDVER3: 2450 case CK_BDVER4: 2451 case CK_x86_64: 2452 return true; 2453 } 2454 llvm_unreachable("Unhandled CPU kind"); 2455 } 2456 2457 bool setFPMath(StringRef Name) override; 2458 2459 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2460 // We accept all non-ARM calling conventions 2461 return (CC == CC_X86ThisCall || 2462 CC == CC_X86FastCall || 2463 CC == CC_X86StdCall || 2464 CC == CC_X86VectorCall || 2465 CC == CC_C || 2466 CC == CC_X86Pascal || 2467 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2468 } 2469 2470 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2471 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2472 } 2473 2474 bool hasSjLjLowering() const override { 2475 return true; 2476 } 2477 }; 2478 2479 bool X86TargetInfo::setFPMath(StringRef Name) { 2480 if (Name == "387") { 2481 FPMath = FP_387; 2482 return true; 2483 } 2484 if (Name == "sse") { 2485 FPMath = FP_SSE; 2486 return true; 2487 } 2488 return false; 2489 } 2490 2491 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2492 // FIXME: This *really* should not be here. 2493 2494 // X86_64 always has SSE2. 2495 if (getTriple().getArch() == llvm::Triple::x86_64) 2496 setFeatureEnabledImpl(Features, "sse2", true); 2497 2498 switch (CPU) { 2499 case CK_Generic: 2500 case CK_i386: 2501 case CK_i486: 2502 case CK_i586: 2503 case CK_Pentium: 2504 case CK_i686: 2505 case CK_PentiumPro: 2506 break; 2507 case CK_PentiumMMX: 2508 case CK_Pentium2: 2509 case CK_K6: 2510 case CK_WinChipC6: 2511 setFeatureEnabledImpl(Features, "mmx", true); 2512 break; 2513 case CK_Pentium3: 2514 case CK_Pentium3M: 2515 case CK_C3_2: 2516 setFeatureEnabledImpl(Features, "sse", true); 2517 break; 2518 case CK_PentiumM: 2519 case CK_Pentium4: 2520 case CK_Pentium4M: 2521 case CK_x86_64: 2522 setFeatureEnabledImpl(Features, "sse2", true); 2523 break; 2524 case CK_Yonah: 2525 case CK_Prescott: 2526 case CK_Nocona: 2527 setFeatureEnabledImpl(Features, "sse3", true); 2528 setFeatureEnabledImpl(Features, "cx16", true); 2529 break; 2530 case CK_Core2: 2531 case CK_Bonnell: 2532 setFeatureEnabledImpl(Features, "ssse3", true); 2533 setFeatureEnabledImpl(Features, "cx16", true); 2534 break; 2535 case CK_Penryn: 2536 setFeatureEnabledImpl(Features, "sse4.1", true); 2537 setFeatureEnabledImpl(Features, "cx16", true); 2538 break; 2539 case CK_Skylake: 2540 setFeatureEnabledImpl(Features, "avx512f", true); 2541 setFeatureEnabledImpl(Features, "avx512cd", true); 2542 setFeatureEnabledImpl(Features, "avx512dq", true); 2543 setFeatureEnabledImpl(Features, "avx512bw", true); 2544 setFeatureEnabledImpl(Features, "avx512vl", true); 2545 // FALLTHROUGH 2546 case CK_Broadwell: 2547 setFeatureEnabledImpl(Features, "rdseed", true); 2548 setFeatureEnabledImpl(Features, "adx", true); 2549 // FALLTHROUGH 2550 case CK_Haswell: 2551 setFeatureEnabledImpl(Features, "avx2", true); 2552 setFeatureEnabledImpl(Features, "lzcnt", true); 2553 setFeatureEnabledImpl(Features, "bmi", true); 2554 setFeatureEnabledImpl(Features, "bmi2", true); 2555 setFeatureEnabledImpl(Features, "rtm", true); 2556 setFeatureEnabledImpl(Features, "fma", true); 2557 // FALLTHROUGH 2558 case CK_IvyBridge: 2559 setFeatureEnabledImpl(Features, "rdrnd", true); 2560 setFeatureEnabledImpl(Features, "f16c", true); 2561 setFeatureEnabledImpl(Features, "fsgsbase", true); 2562 // FALLTHROUGH 2563 case CK_SandyBridge: 2564 setFeatureEnabledImpl(Features, "avx", true); 2565 // FALLTHROUGH 2566 case CK_Westmere: 2567 case CK_Silvermont: 2568 setFeatureEnabledImpl(Features, "aes", true); 2569 setFeatureEnabledImpl(Features, "pclmul", true); 2570 // FALLTHROUGH 2571 case CK_Nehalem: 2572 setFeatureEnabledImpl(Features, "sse4.2", true); 2573 setFeatureEnabledImpl(Features, "cx16", true); 2574 break; 2575 case CK_KNL: 2576 setFeatureEnabledImpl(Features, "avx512f", true); 2577 setFeatureEnabledImpl(Features, "avx512cd", true); 2578 setFeatureEnabledImpl(Features, "avx512er", true); 2579 setFeatureEnabledImpl(Features, "avx512pf", true); 2580 setFeatureEnabledImpl(Features, "rdseed", true); 2581 setFeatureEnabledImpl(Features, "adx", true); 2582 setFeatureEnabledImpl(Features, "lzcnt", true); 2583 setFeatureEnabledImpl(Features, "bmi", true); 2584 setFeatureEnabledImpl(Features, "bmi2", true); 2585 setFeatureEnabledImpl(Features, "rtm", true); 2586 setFeatureEnabledImpl(Features, "fma", true); 2587 setFeatureEnabledImpl(Features, "rdrnd", true); 2588 setFeatureEnabledImpl(Features, "f16c", true); 2589 setFeatureEnabledImpl(Features, "fsgsbase", true); 2590 setFeatureEnabledImpl(Features, "aes", true); 2591 setFeatureEnabledImpl(Features, "pclmul", true); 2592 setFeatureEnabledImpl(Features, "cx16", true); 2593 break; 2594 case CK_K6_2: 2595 case CK_K6_3: 2596 case CK_WinChip2: 2597 case CK_C3: 2598 setFeatureEnabledImpl(Features, "3dnow", true); 2599 break; 2600 case CK_Athlon: 2601 case CK_AthlonThunderbird: 2602 case CK_Geode: 2603 setFeatureEnabledImpl(Features, "3dnowa", true); 2604 break; 2605 case CK_Athlon4: 2606 case CK_AthlonXP: 2607 case CK_AthlonMP: 2608 setFeatureEnabledImpl(Features, "sse", true); 2609 setFeatureEnabledImpl(Features, "3dnowa", true); 2610 break; 2611 case CK_K8: 2612 case CK_Opteron: 2613 case CK_Athlon64: 2614 case CK_AthlonFX: 2615 setFeatureEnabledImpl(Features, "sse2", true); 2616 setFeatureEnabledImpl(Features, "3dnowa", true); 2617 break; 2618 case CK_AMDFAM10: 2619 setFeatureEnabledImpl(Features, "sse4a", true); 2620 setFeatureEnabledImpl(Features, "lzcnt", true); 2621 setFeatureEnabledImpl(Features, "popcnt", true); 2622 // FALLTHROUGH 2623 case CK_K8SSE3: 2624 case CK_OpteronSSE3: 2625 case CK_Athlon64SSE3: 2626 setFeatureEnabledImpl(Features, "sse3", true); 2627 setFeatureEnabledImpl(Features, "3dnowa", true); 2628 break; 2629 case CK_BTVER2: 2630 setFeatureEnabledImpl(Features, "avx", true); 2631 setFeatureEnabledImpl(Features, "aes", true); 2632 setFeatureEnabledImpl(Features, "pclmul", true); 2633 setFeatureEnabledImpl(Features, "bmi", true); 2634 setFeatureEnabledImpl(Features, "f16c", true); 2635 // FALLTHROUGH 2636 case CK_BTVER1: 2637 setFeatureEnabledImpl(Features, "ssse3", true); 2638 setFeatureEnabledImpl(Features, "sse4a", true); 2639 setFeatureEnabledImpl(Features, "lzcnt", true); 2640 setFeatureEnabledImpl(Features, "popcnt", true); 2641 setFeatureEnabledImpl(Features, "prfchw", true); 2642 setFeatureEnabledImpl(Features, "cx16", true); 2643 break; 2644 case CK_BDVER4: 2645 setFeatureEnabledImpl(Features, "avx2", true); 2646 setFeatureEnabledImpl(Features, "bmi2", true); 2647 // FALLTHROUGH 2648 case CK_BDVER3: 2649 setFeatureEnabledImpl(Features, "fsgsbase", true); 2650 // FALLTHROUGH 2651 case CK_BDVER2: 2652 setFeatureEnabledImpl(Features, "bmi", true); 2653 setFeatureEnabledImpl(Features, "fma", true); 2654 setFeatureEnabledImpl(Features, "f16c", true); 2655 setFeatureEnabledImpl(Features, "tbm", true); 2656 // FALLTHROUGH 2657 case CK_BDVER1: 2658 // xop implies avx, sse4a and fma4. 2659 setFeatureEnabledImpl(Features, "xop", true); 2660 setFeatureEnabledImpl(Features, "lzcnt", true); 2661 setFeatureEnabledImpl(Features, "aes", true); 2662 setFeatureEnabledImpl(Features, "pclmul", true); 2663 setFeatureEnabledImpl(Features, "prfchw", true); 2664 setFeatureEnabledImpl(Features, "cx16", true); 2665 break; 2666 } 2667 } 2668 2669 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2670 X86SSEEnum Level, bool Enabled) { 2671 if (Enabled) { 2672 switch (Level) { 2673 case AVX512F: 2674 Features["avx512f"] = true; 2675 case AVX2: 2676 Features["avx2"] = true; 2677 case AVX: 2678 Features["avx"] = true; 2679 case SSE42: 2680 Features["sse4.2"] = true; 2681 case SSE41: 2682 Features["sse4.1"] = true; 2683 case SSSE3: 2684 Features["ssse3"] = true; 2685 case SSE3: 2686 Features["sse3"] = true; 2687 case SSE2: 2688 Features["sse2"] = true; 2689 case SSE1: 2690 Features["sse"] = true; 2691 case NoSSE: 2692 break; 2693 } 2694 return; 2695 } 2696 2697 switch (Level) { 2698 case NoSSE: 2699 case SSE1: 2700 Features["sse"] = false; 2701 case SSE2: 2702 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2703 Features["sha"] = false; 2704 case SSE3: 2705 Features["sse3"] = false; 2706 setXOPLevel(Features, NoXOP, false); 2707 case SSSE3: 2708 Features["ssse3"] = false; 2709 case SSE41: 2710 Features["sse4.1"] = false; 2711 case SSE42: 2712 Features["sse4.2"] = false; 2713 case AVX: 2714 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2715 setXOPLevel(Features, FMA4, false); 2716 case AVX2: 2717 Features["avx2"] = false; 2718 case AVX512F: 2719 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2720 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2721 Features["avx512vl"] = false; 2722 } 2723 } 2724 2725 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2726 MMX3DNowEnum Level, bool Enabled) { 2727 if (Enabled) { 2728 switch (Level) { 2729 case AMD3DNowAthlon: 2730 Features["3dnowa"] = true; 2731 case AMD3DNow: 2732 Features["3dnow"] = true; 2733 case MMX: 2734 Features["mmx"] = true; 2735 case NoMMX3DNow: 2736 break; 2737 } 2738 return; 2739 } 2740 2741 switch (Level) { 2742 case NoMMX3DNow: 2743 case MMX: 2744 Features["mmx"] = false; 2745 case AMD3DNow: 2746 Features["3dnow"] = false; 2747 case AMD3DNowAthlon: 2748 Features["3dnowa"] = false; 2749 } 2750 } 2751 2752 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2753 bool Enabled) { 2754 if (Enabled) { 2755 switch (Level) { 2756 case XOP: 2757 Features["xop"] = true; 2758 case FMA4: 2759 Features["fma4"] = true; 2760 setSSELevel(Features, AVX, true); 2761 case SSE4A: 2762 Features["sse4a"] = true; 2763 setSSELevel(Features, SSE3, true); 2764 case NoXOP: 2765 break; 2766 } 2767 return; 2768 } 2769 2770 switch (Level) { 2771 case NoXOP: 2772 case SSE4A: 2773 Features["sse4a"] = false; 2774 case FMA4: 2775 Features["fma4"] = false; 2776 case XOP: 2777 Features["xop"] = false; 2778 } 2779 } 2780 2781 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2782 StringRef Name, bool Enabled) { 2783 // This is a bit of a hack to deal with the sse4 target feature when used 2784 // as part of the target attribute. We handle sse4 correctly everywhere 2785 // else. See below for more information on how we handle the sse4 options. 2786 if (Name != "sse4") 2787 Features[Name] = Enabled; 2788 2789 if (Name == "mmx") { 2790 setMMXLevel(Features, MMX, Enabled); 2791 } else if (Name == "sse") { 2792 setSSELevel(Features, SSE1, Enabled); 2793 } else if (Name == "sse2") { 2794 setSSELevel(Features, SSE2, Enabled); 2795 } else if (Name == "sse3") { 2796 setSSELevel(Features, SSE3, Enabled); 2797 } else if (Name == "ssse3") { 2798 setSSELevel(Features, SSSE3, Enabled); 2799 } else if (Name == "sse4.2") { 2800 setSSELevel(Features, SSE42, Enabled); 2801 } else if (Name == "sse4.1") { 2802 setSSELevel(Features, SSE41, Enabled); 2803 } else if (Name == "3dnow") { 2804 setMMXLevel(Features, AMD3DNow, Enabled); 2805 } else if (Name == "3dnowa") { 2806 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2807 } else if (Name == "aes") { 2808 if (Enabled) 2809 setSSELevel(Features, SSE2, Enabled); 2810 } else if (Name == "pclmul") { 2811 if (Enabled) 2812 setSSELevel(Features, SSE2, Enabled); 2813 } else if (Name == "avx") { 2814 setSSELevel(Features, AVX, Enabled); 2815 } else if (Name == "avx2") { 2816 setSSELevel(Features, AVX2, Enabled); 2817 } else if (Name == "avx512f") { 2818 setSSELevel(Features, AVX512F, Enabled); 2819 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2820 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2821 if (Enabled) 2822 setSSELevel(Features, AVX512F, Enabled); 2823 } else if (Name == "fma") { 2824 if (Enabled) 2825 setSSELevel(Features, AVX, Enabled); 2826 } else if (Name == "fma4") { 2827 setXOPLevel(Features, FMA4, Enabled); 2828 } else if (Name == "xop") { 2829 setXOPLevel(Features, XOP, Enabled); 2830 } else if (Name == "sse4a") { 2831 setXOPLevel(Features, SSE4A, Enabled); 2832 } else if (Name == "f16c") { 2833 if (Enabled) 2834 setSSELevel(Features, AVX, Enabled); 2835 } else if (Name == "sha") { 2836 if (Enabled) 2837 setSSELevel(Features, SSE2, Enabled); 2838 } else if (Name == "sse4") { 2839 // We can get here via the __target__ attribute since that's not controlled 2840 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2841 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2842 // disabled. 2843 if (Enabled) 2844 setSSELevel(Features, SSE42, Enabled); 2845 else 2846 setSSELevel(Features, SSE41, Enabled); 2847 } 2848 } 2849 2850 /// handleTargetFeatures - Perform initialization based on the user 2851 /// configured set of features. 2852 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2853 DiagnosticsEngine &Diags) { 2854 // Remember the maximum enabled sselevel. 2855 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2856 // Ignore disabled features. 2857 if (Features[i][0] == '-') 2858 continue; 2859 2860 StringRef Feature = StringRef(Features[i]).substr(1); 2861 2862 if (Feature == "aes") { 2863 HasAES = true; 2864 continue; 2865 } 2866 2867 if (Feature == "pclmul") { 2868 HasPCLMUL = true; 2869 continue; 2870 } 2871 2872 if (Feature == "lzcnt") { 2873 HasLZCNT = true; 2874 continue; 2875 } 2876 2877 if (Feature == "rdrnd") { 2878 HasRDRND = true; 2879 continue; 2880 } 2881 2882 if (Feature == "fsgsbase") { 2883 HasFSGSBASE = true; 2884 continue; 2885 } 2886 2887 if (Feature == "bmi") { 2888 HasBMI = true; 2889 continue; 2890 } 2891 2892 if (Feature == "bmi2") { 2893 HasBMI2 = true; 2894 continue; 2895 } 2896 2897 if (Feature == "popcnt") { 2898 HasPOPCNT = true; 2899 continue; 2900 } 2901 2902 if (Feature == "rtm") { 2903 HasRTM = true; 2904 continue; 2905 } 2906 2907 if (Feature == "prfchw") { 2908 HasPRFCHW = true; 2909 continue; 2910 } 2911 2912 if (Feature == "rdseed") { 2913 HasRDSEED = true; 2914 continue; 2915 } 2916 2917 if (Feature == "adx") { 2918 HasADX = true; 2919 continue; 2920 } 2921 2922 if (Feature == "tbm") { 2923 HasTBM = true; 2924 continue; 2925 } 2926 2927 if (Feature == "fma") { 2928 HasFMA = true; 2929 continue; 2930 } 2931 2932 if (Feature == "f16c") { 2933 HasF16C = true; 2934 continue; 2935 } 2936 2937 if (Feature == "avx512cd") { 2938 HasAVX512CD = true; 2939 continue; 2940 } 2941 2942 if (Feature == "avx512er") { 2943 HasAVX512ER = true; 2944 continue; 2945 } 2946 2947 if (Feature == "avx512pf") { 2948 HasAVX512PF = true; 2949 continue; 2950 } 2951 2952 if (Feature == "avx512dq") { 2953 HasAVX512DQ = true; 2954 continue; 2955 } 2956 2957 if (Feature == "avx512bw") { 2958 HasAVX512BW = true; 2959 continue; 2960 } 2961 2962 if (Feature == "avx512vl") { 2963 HasAVX512VL = true; 2964 continue; 2965 } 2966 2967 if (Feature == "sha") { 2968 HasSHA = true; 2969 continue; 2970 } 2971 2972 if (Feature == "cx16") { 2973 HasCX16 = true; 2974 continue; 2975 } 2976 2977 assert(Features[i][0] == '+' && "Invalid target feature!"); 2978 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2979 .Case("avx512f", AVX512F) 2980 .Case("avx2", AVX2) 2981 .Case("avx", AVX) 2982 .Case("sse4.2", SSE42) 2983 .Case("sse4.1", SSE41) 2984 .Case("ssse3", SSSE3) 2985 .Case("sse3", SSE3) 2986 .Case("sse2", SSE2) 2987 .Case("sse", SSE1) 2988 .Default(NoSSE); 2989 SSELevel = std::max(SSELevel, Level); 2990 2991 MMX3DNowEnum ThreeDNowLevel = 2992 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2993 .Case("3dnowa", AMD3DNowAthlon) 2994 .Case("3dnow", AMD3DNow) 2995 .Case("mmx", MMX) 2996 .Default(NoMMX3DNow); 2997 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2998 2999 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3000 .Case("xop", XOP) 3001 .Case("fma4", FMA4) 3002 .Case("sse4a", SSE4A) 3003 .Default(NoXOP); 3004 XOPLevel = std::max(XOPLevel, XLevel); 3005 } 3006 3007 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3008 // Can't do this earlier because we need to be able to explicitly enable 3009 // popcnt and still disable sse4.2. 3010 if (!HasPOPCNT && SSELevel >= SSE42 && 3011 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 3012 HasPOPCNT = true; 3013 Features.push_back("+popcnt"); 3014 } 3015 3016 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3017 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 3018 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 3019 HasPRFCHW = true; 3020 Features.push_back("+prfchw"); 3021 } 3022 3023 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3024 // matches the selected sse level. 3025 if (FPMath == FP_SSE && SSELevel < SSE1) { 3026 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3027 return false; 3028 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3029 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3030 return false; 3031 } 3032 3033 // Don't tell the backend if we're turning off mmx; it will end up disabling 3034 // SSE, which we don't want. 3035 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3036 // then enable MMX. 3037 std::vector<std::string>::iterator it; 3038 it = std::find(Features.begin(), Features.end(), "-mmx"); 3039 if (it != Features.end()) 3040 Features.erase(it); 3041 else if (SSELevel > NoSSE) 3042 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3043 3044 SimdDefaultAlign = 3045 (getABI() == "avx512") ? 512 : (getABI() == "avx") ? 256 : 128; 3046 return true; 3047 } 3048 3049 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3050 /// definitions for this particular subtarget. 3051 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3052 MacroBuilder &Builder) const { 3053 // Target identification. 3054 if (getTriple().getArch() == llvm::Triple::x86_64) { 3055 Builder.defineMacro("__amd64__"); 3056 Builder.defineMacro("__amd64"); 3057 Builder.defineMacro("__x86_64"); 3058 Builder.defineMacro("__x86_64__"); 3059 if (getTriple().getArchName() == "x86_64h") { 3060 Builder.defineMacro("__x86_64h"); 3061 Builder.defineMacro("__x86_64h__"); 3062 } 3063 } else { 3064 DefineStd(Builder, "i386", Opts); 3065 } 3066 3067 // Subtarget options. 3068 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3069 // truly should be based on -mtune options. 3070 switch (CPU) { 3071 case CK_Generic: 3072 break; 3073 case CK_i386: 3074 // The rest are coming from the i386 define above. 3075 Builder.defineMacro("__tune_i386__"); 3076 break; 3077 case CK_i486: 3078 case CK_WinChipC6: 3079 case CK_WinChip2: 3080 case CK_C3: 3081 defineCPUMacros(Builder, "i486"); 3082 break; 3083 case CK_PentiumMMX: 3084 Builder.defineMacro("__pentium_mmx__"); 3085 Builder.defineMacro("__tune_pentium_mmx__"); 3086 // Fallthrough 3087 case CK_i586: 3088 case CK_Pentium: 3089 defineCPUMacros(Builder, "i586"); 3090 defineCPUMacros(Builder, "pentium"); 3091 break; 3092 case CK_Pentium3: 3093 case CK_Pentium3M: 3094 case CK_PentiumM: 3095 Builder.defineMacro("__tune_pentium3__"); 3096 // Fallthrough 3097 case CK_Pentium2: 3098 case CK_C3_2: 3099 Builder.defineMacro("__tune_pentium2__"); 3100 // Fallthrough 3101 case CK_PentiumPro: 3102 Builder.defineMacro("__tune_i686__"); 3103 Builder.defineMacro("__tune_pentiumpro__"); 3104 // Fallthrough 3105 case CK_i686: 3106 Builder.defineMacro("__i686"); 3107 Builder.defineMacro("__i686__"); 3108 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3109 Builder.defineMacro("__pentiumpro"); 3110 Builder.defineMacro("__pentiumpro__"); 3111 break; 3112 case CK_Pentium4: 3113 case CK_Pentium4M: 3114 defineCPUMacros(Builder, "pentium4"); 3115 break; 3116 case CK_Yonah: 3117 case CK_Prescott: 3118 case CK_Nocona: 3119 defineCPUMacros(Builder, "nocona"); 3120 break; 3121 case CK_Core2: 3122 case CK_Penryn: 3123 defineCPUMacros(Builder, "core2"); 3124 break; 3125 case CK_Bonnell: 3126 defineCPUMacros(Builder, "atom"); 3127 break; 3128 case CK_Silvermont: 3129 defineCPUMacros(Builder, "slm"); 3130 break; 3131 case CK_Nehalem: 3132 case CK_Westmere: 3133 case CK_SandyBridge: 3134 case CK_IvyBridge: 3135 case CK_Haswell: 3136 case CK_Broadwell: 3137 // FIXME: Historically, we defined this legacy name, it would be nice to 3138 // remove it at some point. We've never exposed fine-grained names for 3139 // recent primary x86 CPUs, and we should keep it that way. 3140 defineCPUMacros(Builder, "corei7"); 3141 break; 3142 case CK_Skylake: 3143 // FIXME: Historically, we defined this legacy name, it would be nice to 3144 // remove it at some point. This is the only fine-grained CPU macro in the 3145 // main intel CPU line, and it would be better to not have these and force 3146 // people to use ISA macros. 3147 defineCPUMacros(Builder, "skx"); 3148 break; 3149 case CK_KNL: 3150 defineCPUMacros(Builder, "knl"); 3151 break; 3152 case CK_K6_2: 3153 Builder.defineMacro("__k6_2__"); 3154 Builder.defineMacro("__tune_k6_2__"); 3155 // Fallthrough 3156 case CK_K6_3: 3157 if (CPU != CK_K6_2) { // In case of fallthrough 3158 // FIXME: GCC may be enabling these in cases where some other k6 3159 // architecture is specified but -m3dnow is explicitly provided. The 3160 // exact semantics need to be determined and emulated here. 3161 Builder.defineMacro("__k6_3__"); 3162 Builder.defineMacro("__tune_k6_3__"); 3163 } 3164 // Fallthrough 3165 case CK_K6: 3166 defineCPUMacros(Builder, "k6"); 3167 break; 3168 case CK_Athlon: 3169 case CK_AthlonThunderbird: 3170 case CK_Athlon4: 3171 case CK_AthlonXP: 3172 case CK_AthlonMP: 3173 defineCPUMacros(Builder, "athlon"); 3174 if (SSELevel != NoSSE) { 3175 Builder.defineMacro("__athlon_sse__"); 3176 Builder.defineMacro("__tune_athlon_sse__"); 3177 } 3178 break; 3179 case CK_K8: 3180 case CK_K8SSE3: 3181 case CK_x86_64: 3182 case CK_Opteron: 3183 case CK_OpteronSSE3: 3184 case CK_Athlon64: 3185 case CK_Athlon64SSE3: 3186 case CK_AthlonFX: 3187 defineCPUMacros(Builder, "k8"); 3188 break; 3189 case CK_AMDFAM10: 3190 defineCPUMacros(Builder, "amdfam10"); 3191 break; 3192 case CK_BTVER1: 3193 defineCPUMacros(Builder, "btver1"); 3194 break; 3195 case CK_BTVER2: 3196 defineCPUMacros(Builder, "btver2"); 3197 break; 3198 case CK_BDVER1: 3199 defineCPUMacros(Builder, "bdver1"); 3200 break; 3201 case CK_BDVER2: 3202 defineCPUMacros(Builder, "bdver2"); 3203 break; 3204 case CK_BDVER3: 3205 defineCPUMacros(Builder, "bdver3"); 3206 break; 3207 case CK_BDVER4: 3208 defineCPUMacros(Builder, "bdver4"); 3209 break; 3210 case CK_Geode: 3211 defineCPUMacros(Builder, "geode"); 3212 break; 3213 } 3214 3215 // Target properties. 3216 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3217 3218 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3219 // functions in glibc header files that use FP Stack inline asm which the 3220 // backend can't deal with (PR879). 3221 Builder.defineMacro("__NO_MATH_INLINES"); 3222 3223 if (HasAES) 3224 Builder.defineMacro("__AES__"); 3225 3226 if (HasPCLMUL) 3227 Builder.defineMacro("__PCLMUL__"); 3228 3229 if (HasLZCNT) 3230 Builder.defineMacro("__LZCNT__"); 3231 3232 if (HasRDRND) 3233 Builder.defineMacro("__RDRND__"); 3234 3235 if (HasFSGSBASE) 3236 Builder.defineMacro("__FSGSBASE__"); 3237 3238 if (HasBMI) 3239 Builder.defineMacro("__BMI__"); 3240 3241 if (HasBMI2) 3242 Builder.defineMacro("__BMI2__"); 3243 3244 if (HasPOPCNT) 3245 Builder.defineMacro("__POPCNT__"); 3246 3247 if (HasRTM) 3248 Builder.defineMacro("__RTM__"); 3249 3250 if (HasPRFCHW) 3251 Builder.defineMacro("__PRFCHW__"); 3252 3253 if (HasRDSEED) 3254 Builder.defineMacro("__RDSEED__"); 3255 3256 if (HasADX) 3257 Builder.defineMacro("__ADX__"); 3258 3259 if (HasTBM) 3260 Builder.defineMacro("__TBM__"); 3261 3262 switch (XOPLevel) { 3263 case XOP: 3264 Builder.defineMacro("__XOP__"); 3265 case FMA4: 3266 Builder.defineMacro("__FMA4__"); 3267 case SSE4A: 3268 Builder.defineMacro("__SSE4A__"); 3269 case NoXOP: 3270 break; 3271 } 3272 3273 if (HasFMA) 3274 Builder.defineMacro("__FMA__"); 3275 3276 if (HasF16C) 3277 Builder.defineMacro("__F16C__"); 3278 3279 if (HasAVX512CD) 3280 Builder.defineMacro("__AVX512CD__"); 3281 if (HasAVX512ER) 3282 Builder.defineMacro("__AVX512ER__"); 3283 if (HasAVX512PF) 3284 Builder.defineMacro("__AVX512PF__"); 3285 if (HasAVX512DQ) 3286 Builder.defineMacro("__AVX512DQ__"); 3287 if (HasAVX512BW) 3288 Builder.defineMacro("__AVX512BW__"); 3289 if (HasAVX512VL) 3290 Builder.defineMacro("__AVX512VL__"); 3291 3292 if (HasSHA) 3293 Builder.defineMacro("__SHA__"); 3294 3295 if (HasCX16) 3296 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3297 3298 // Each case falls through to the previous one here. 3299 switch (SSELevel) { 3300 case AVX512F: 3301 Builder.defineMacro("__AVX512F__"); 3302 case AVX2: 3303 Builder.defineMacro("__AVX2__"); 3304 case AVX: 3305 Builder.defineMacro("__AVX__"); 3306 case SSE42: 3307 Builder.defineMacro("__SSE4_2__"); 3308 case SSE41: 3309 Builder.defineMacro("__SSE4_1__"); 3310 case SSSE3: 3311 Builder.defineMacro("__SSSE3__"); 3312 case SSE3: 3313 Builder.defineMacro("__SSE3__"); 3314 case SSE2: 3315 Builder.defineMacro("__SSE2__"); 3316 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3317 case SSE1: 3318 Builder.defineMacro("__SSE__"); 3319 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3320 case NoSSE: 3321 break; 3322 } 3323 3324 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3325 switch (SSELevel) { 3326 case AVX512F: 3327 case AVX2: 3328 case AVX: 3329 case SSE42: 3330 case SSE41: 3331 case SSSE3: 3332 case SSE3: 3333 case SSE2: 3334 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3335 break; 3336 case SSE1: 3337 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3338 break; 3339 default: 3340 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3341 } 3342 } 3343 3344 // Each case falls through to the previous one here. 3345 switch (MMX3DNowLevel) { 3346 case AMD3DNowAthlon: 3347 Builder.defineMacro("__3dNOW_A__"); 3348 case AMD3DNow: 3349 Builder.defineMacro("__3dNOW__"); 3350 case MMX: 3351 Builder.defineMacro("__MMX__"); 3352 case NoMMX3DNow: 3353 break; 3354 } 3355 3356 if (CPU >= CK_i486) { 3357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3360 } 3361 if (CPU >= CK_i586) 3362 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3363 } 3364 3365 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3366 return llvm::StringSwitch<bool>(Feature) 3367 .Case("aes", HasAES) 3368 .Case("avx", SSELevel >= AVX) 3369 .Case("avx2", SSELevel >= AVX2) 3370 .Case("avx512f", SSELevel >= AVX512F) 3371 .Case("avx512cd", HasAVX512CD) 3372 .Case("avx512er", HasAVX512ER) 3373 .Case("avx512pf", HasAVX512PF) 3374 .Case("avx512dq", HasAVX512DQ) 3375 .Case("avx512bw", HasAVX512BW) 3376 .Case("avx512vl", HasAVX512VL) 3377 .Case("bmi", HasBMI) 3378 .Case("bmi2", HasBMI2) 3379 .Case("cx16", HasCX16) 3380 .Case("f16c", HasF16C) 3381 .Case("fma", HasFMA) 3382 .Case("fma4", XOPLevel >= FMA4) 3383 .Case("fsgsbase", HasFSGSBASE) 3384 .Case("lzcnt", HasLZCNT) 3385 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3386 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3387 .Case("mmx", MMX3DNowLevel >= MMX) 3388 .Case("pclmul", HasPCLMUL) 3389 .Case("popcnt", HasPOPCNT) 3390 .Case("prfchw", HasPRFCHW) 3391 .Case("rdrnd", HasRDRND) 3392 .Case("rdseed", HasRDSEED) 3393 .Case("rtm", HasRTM) 3394 .Case("sha", HasSHA) 3395 .Case("sse", SSELevel >= SSE1) 3396 .Case("sse2", SSELevel >= SSE2) 3397 .Case("sse3", SSELevel >= SSE3) 3398 .Case("ssse3", SSELevel >= SSSE3) 3399 .Case("sse4.1", SSELevel >= SSE41) 3400 .Case("sse4.2", SSELevel >= SSE42) 3401 .Case("sse4a", XOPLevel >= SSE4A) 3402 .Case("tbm", HasTBM) 3403 .Case("x86", true) 3404 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3405 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3406 .Case("xop", XOPLevel >= XOP) 3407 .Default(false); 3408 } 3409 3410 // We can't use a generic validation scheme for the features accepted here 3411 // versus subtarget features accepted in the target attribute because the 3412 // bitfield structure that's initialized in the runtime only supports the 3413 // below currently rather than the full range of subtarget features. (See 3414 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3415 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3416 return llvm::StringSwitch<bool>(FeatureStr) 3417 .Case("cmov", true) 3418 .Case("mmx", true) 3419 .Case("popcnt", true) 3420 .Case("sse", true) 3421 .Case("sse2", true) 3422 .Case("sse3", true) 3423 .Case("sse4.1", true) 3424 .Case("sse4.2", true) 3425 .Case("avx", true) 3426 .Case("avx2", true) 3427 .Case("sse4a", true) 3428 .Case("fma4", true) 3429 .Case("xop", true) 3430 .Case("fma", true) 3431 .Case("avx512f", true) 3432 .Case("bmi", true) 3433 .Case("bmi2", true) 3434 .Default(false); 3435 } 3436 3437 bool 3438 X86TargetInfo::validateAsmConstraint(const char *&Name, 3439 TargetInfo::ConstraintInfo &Info) const { 3440 switch (*Name) { 3441 default: return false; 3442 case 'I': 3443 Info.setRequiresImmediate(0, 31); 3444 return true; 3445 case 'J': 3446 Info.setRequiresImmediate(0, 63); 3447 return true; 3448 case 'K': 3449 Info.setRequiresImmediate(-128, 127); 3450 return true; 3451 case 'L': 3452 // FIXME: properly analyze this constraint: 3453 // must be one of 0xff, 0xffff, or 0xffffffff 3454 return true; 3455 case 'M': 3456 Info.setRequiresImmediate(0, 3); 3457 return true; 3458 case 'N': 3459 Info.setRequiresImmediate(0, 255); 3460 return true; 3461 case 'O': 3462 Info.setRequiresImmediate(0, 127); 3463 return true; 3464 case 'Y': // first letter of a pair: 3465 switch (*(Name+1)) { 3466 default: return false; 3467 case '0': // First SSE register. 3468 case 't': // Any SSE register, when SSE2 is enabled. 3469 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3470 case 'm': // any MMX register, when inter-unit moves enabled. 3471 break; // falls through to setAllowsRegister. 3472 } 3473 case 'f': // any x87 floating point stack register. 3474 // Constraint 'f' cannot be used for output operands. 3475 if (Info.ConstraintStr[0] == '=') 3476 return false; 3477 3478 Info.setAllowsRegister(); 3479 return true; 3480 case 'a': // eax. 3481 case 'b': // ebx. 3482 case 'c': // ecx. 3483 case 'd': // edx. 3484 case 'S': // esi. 3485 case 'D': // edi. 3486 case 'A': // edx:eax. 3487 case 't': // top of floating point stack. 3488 case 'u': // second from top of floating point stack. 3489 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3490 case 'y': // Any MMX register. 3491 case 'x': // Any SSE register. 3492 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3493 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3494 case 'l': // "Index" registers: any general register that can be used as an 3495 // index in a base+index memory access. 3496 Info.setAllowsRegister(); 3497 return true; 3498 case 'C': // SSE floating point constant. 3499 case 'G': // x87 floating point constant. 3500 case 'e': // 32-bit signed integer constant for use with zero-extending 3501 // x86_64 instructions. 3502 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3503 // x86_64 instructions. 3504 return true; 3505 } 3506 } 3507 3508 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3509 unsigned Size) const { 3510 // Strip off constraint modifiers. 3511 while (Constraint[0] == '=' || 3512 Constraint[0] == '+' || 3513 Constraint[0] == '&') 3514 Constraint = Constraint.substr(1); 3515 3516 return validateOperandSize(Constraint, Size); 3517 } 3518 3519 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3520 unsigned Size) const { 3521 return validateOperandSize(Constraint, Size); 3522 } 3523 3524 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3525 unsigned Size) const { 3526 switch (Constraint[0]) { 3527 default: break; 3528 case 'y': 3529 return Size <= 64; 3530 case 'f': 3531 case 't': 3532 case 'u': 3533 return Size <= 128; 3534 case 'x': 3535 // 256-bit ymm registers can be used if target supports AVX. 3536 return Size <= (SSELevel >= AVX ? 256U : 128U); 3537 } 3538 3539 return true; 3540 } 3541 3542 std::string 3543 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3544 switch (*Constraint) { 3545 case 'a': return std::string("{ax}"); 3546 case 'b': return std::string("{bx}"); 3547 case 'c': return std::string("{cx}"); 3548 case 'd': return std::string("{dx}"); 3549 case 'S': return std::string("{si}"); 3550 case 'D': return std::string("{di}"); 3551 case 'p': // address 3552 return std::string("im"); 3553 case 't': // top of floating point stack. 3554 return std::string("{st}"); 3555 case 'u': // second from top of floating point stack. 3556 return std::string("{st(1)}"); // second from top of floating point stack. 3557 default: 3558 return std::string(1, *Constraint); 3559 } 3560 } 3561 3562 // X86-32 generic target 3563 class X86_32TargetInfo : public X86TargetInfo { 3564 public: 3565 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3566 DoubleAlign = LongLongAlign = 32; 3567 LongDoubleWidth = 96; 3568 LongDoubleAlign = 32; 3569 SuitableAlign = 128; 3570 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3571 SizeType = UnsignedInt; 3572 PtrDiffType = SignedInt; 3573 IntPtrType = SignedInt; 3574 RegParmMax = 3; 3575 3576 // Use fpret for all types. 3577 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3578 (1 << TargetInfo::Double) | 3579 (1 << TargetInfo::LongDouble)); 3580 3581 // x86-32 has atomics up to 8 bytes 3582 // FIXME: Check that we actually have cmpxchg8b before setting 3583 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3584 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3585 } 3586 BuiltinVaListKind getBuiltinVaListKind() const override { 3587 return TargetInfo::CharPtrBuiltinVaList; 3588 } 3589 3590 int getEHDataRegisterNumber(unsigned RegNo) const override { 3591 if (RegNo == 0) return 0; 3592 if (RegNo == 1) return 2; 3593 return -1; 3594 } 3595 bool validateOperandSize(StringRef Constraint, 3596 unsigned Size) const override { 3597 switch (Constraint[0]) { 3598 default: break; 3599 case 'R': 3600 case 'q': 3601 case 'Q': 3602 case 'a': 3603 case 'b': 3604 case 'c': 3605 case 'd': 3606 case 'S': 3607 case 'D': 3608 return Size <= 32; 3609 case 'A': 3610 return Size <= 64; 3611 } 3612 3613 return X86TargetInfo::validateOperandSize(Constraint, Size); 3614 } 3615 }; 3616 3617 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3618 public: 3619 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3620 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3621 3622 unsigned getFloatEvalMethod() const override { 3623 unsigned Major, Minor, Micro; 3624 getTriple().getOSVersion(Major, Minor, Micro); 3625 // New NetBSD uses the default rounding mode. 3626 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3627 return X86_32TargetInfo::getFloatEvalMethod(); 3628 // NetBSD before 6.99.26 defaults to "double" rounding. 3629 return 1; 3630 } 3631 }; 3632 3633 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3634 public: 3635 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3636 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3637 SizeType = UnsignedLong; 3638 IntPtrType = SignedLong; 3639 PtrDiffType = SignedLong; 3640 } 3641 }; 3642 3643 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3644 public: 3645 BitrigI386TargetInfo(const llvm::Triple &Triple) 3646 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3647 SizeType = UnsignedLong; 3648 IntPtrType = SignedLong; 3649 PtrDiffType = SignedLong; 3650 } 3651 }; 3652 3653 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3654 public: 3655 DarwinI386TargetInfo(const llvm::Triple &Triple) 3656 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3657 LongDoubleWidth = 128; 3658 LongDoubleAlign = 128; 3659 SuitableAlign = 128; 3660 MaxVectorAlign = 256; 3661 SizeType = UnsignedLong; 3662 IntPtrType = SignedLong; 3663 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3664 HasAlignMac68kSupport = true; 3665 } 3666 3667 }; 3668 3669 // x86-32 Windows target 3670 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3671 public: 3672 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3673 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3674 WCharType = UnsignedShort; 3675 DoubleAlign = LongLongAlign = 64; 3676 bool IsWinCOFF = 3677 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3678 DescriptionString = IsWinCOFF 3679 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3680 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3681 } 3682 void getTargetDefines(const LangOptions &Opts, 3683 MacroBuilder &Builder) const override { 3684 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3685 } 3686 }; 3687 3688 // x86-32 Windows Visual Studio target 3689 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3690 public: 3691 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3692 : WindowsX86_32TargetInfo(Triple) { 3693 LongDoubleWidth = LongDoubleAlign = 64; 3694 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3695 } 3696 void getTargetDefines(const LangOptions &Opts, 3697 MacroBuilder &Builder) const override { 3698 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3699 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3700 // The value of the following reflects processor type. 3701 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3702 // We lost the original triple, so we use the default. 3703 Builder.defineMacro("_M_IX86", "600"); 3704 } 3705 }; 3706 } // end anonymous namespace 3707 3708 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3709 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3710 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3711 // macro anyway for pre-processor compatibility. 3712 if (Opts.MicrosoftExt) 3713 Builder.defineMacro("__declspec", "__declspec"); 3714 else 3715 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3716 3717 if (!Opts.MicrosoftExt) { 3718 // Provide macros for all the calling convention keywords. Provide both 3719 // single and double underscore prefixed variants. These are available on 3720 // x64 as well as x86, even though they have no effect. 3721 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3722 for (const char *CC : CCs) { 3723 std::string GCCSpelling = "__attribute__((__"; 3724 GCCSpelling += CC; 3725 GCCSpelling += "__))"; 3726 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3727 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3728 } 3729 } 3730 } 3731 3732 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3733 Builder.defineMacro("__MSVCRT__"); 3734 Builder.defineMacro("__MINGW32__"); 3735 addCygMingDefines(Opts, Builder); 3736 } 3737 3738 namespace { 3739 // x86-32 MinGW target 3740 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3741 public: 3742 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3743 : WindowsX86_32TargetInfo(Triple) {} 3744 void getTargetDefines(const LangOptions &Opts, 3745 MacroBuilder &Builder) const override { 3746 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3747 DefineStd(Builder, "WIN32", Opts); 3748 DefineStd(Builder, "WINNT", Opts); 3749 Builder.defineMacro("_X86_"); 3750 addMinGWDefines(Opts, Builder); 3751 } 3752 }; 3753 3754 // x86-32 Cygwin target 3755 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3756 public: 3757 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3758 : X86_32TargetInfo(Triple) { 3759 TLSSupported = false; 3760 WCharType = UnsignedShort; 3761 DoubleAlign = LongLongAlign = 64; 3762 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3763 } 3764 void getTargetDefines(const LangOptions &Opts, 3765 MacroBuilder &Builder) const override { 3766 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3767 Builder.defineMacro("_X86_"); 3768 Builder.defineMacro("__CYGWIN__"); 3769 Builder.defineMacro("__CYGWIN32__"); 3770 addCygMingDefines(Opts, Builder); 3771 DefineStd(Builder, "unix", Opts); 3772 if (Opts.CPlusPlus) 3773 Builder.defineMacro("_GNU_SOURCE"); 3774 } 3775 }; 3776 3777 // x86-32 Haiku target 3778 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3779 public: 3780 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3781 SizeType = UnsignedLong; 3782 IntPtrType = SignedLong; 3783 PtrDiffType = SignedLong; 3784 ProcessIDType = SignedLong; 3785 this->UserLabelPrefix = ""; 3786 this->TLSSupported = false; 3787 } 3788 void getTargetDefines(const LangOptions &Opts, 3789 MacroBuilder &Builder) const override { 3790 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3791 Builder.defineMacro("__INTEL__"); 3792 Builder.defineMacro("__HAIKU__"); 3793 } 3794 }; 3795 3796 // RTEMS Target 3797 template<typename Target> 3798 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3799 protected: 3800 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3801 MacroBuilder &Builder) const override { 3802 // RTEMS defines; list based off of gcc output 3803 3804 Builder.defineMacro("__rtems__"); 3805 Builder.defineMacro("__ELF__"); 3806 } 3807 3808 public: 3809 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3810 this->UserLabelPrefix = ""; 3811 3812 switch (Triple.getArch()) { 3813 default: 3814 case llvm::Triple::x86: 3815 // this->MCountName = ".mcount"; 3816 break; 3817 case llvm::Triple::mips: 3818 case llvm::Triple::mipsel: 3819 case llvm::Triple::ppc: 3820 case llvm::Triple::ppc64: 3821 case llvm::Triple::ppc64le: 3822 // this->MCountName = "_mcount"; 3823 break; 3824 case llvm::Triple::arm: 3825 // this->MCountName = "__mcount"; 3826 break; 3827 } 3828 } 3829 }; 3830 3831 // x86-32 RTEMS target 3832 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3833 public: 3834 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3835 SizeType = UnsignedLong; 3836 IntPtrType = SignedLong; 3837 PtrDiffType = SignedLong; 3838 this->UserLabelPrefix = ""; 3839 } 3840 void getTargetDefines(const LangOptions &Opts, 3841 MacroBuilder &Builder) const override { 3842 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3843 Builder.defineMacro("__INTEL__"); 3844 Builder.defineMacro("__rtems__"); 3845 } 3846 }; 3847 3848 // x86-64 generic target 3849 class X86_64TargetInfo : public X86TargetInfo { 3850 public: 3851 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3852 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3853 bool IsWinCOFF = 3854 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3855 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3856 LongDoubleWidth = 128; 3857 LongDoubleAlign = 128; 3858 LargeArrayMinWidth = 128; 3859 LargeArrayAlign = 128; 3860 SuitableAlign = 128; 3861 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3862 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3863 IntPtrType = IsX32 ? SignedInt : SignedLong; 3864 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3865 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3866 RegParmMax = 6; 3867 3868 // Pointers are 32-bit in x32. 3869 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3870 : IsWinCOFF 3871 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3872 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3873 3874 // Use fpret only for long double. 3875 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3876 3877 // Use fp2ret for _Complex long double. 3878 ComplexLongDoubleUsesFP2Ret = true; 3879 3880 // x86-64 has atomics up to 16 bytes. 3881 MaxAtomicPromoteWidth = 128; 3882 MaxAtomicInlineWidth = 128; 3883 } 3884 BuiltinVaListKind getBuiltinVaListKind() const override { 3885 return TargetInfo::X86_64ABIBuiltinVaList; 3886 } 3887 3888 int getEHDataRegisterNumber(unsigned RegNo) const override { 3889 if (RegNo == 0) return 0; 3890 if (RegNo == 1) return 1; 3891 return -1; 3892 } 3893 3894 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3895 return (CC == CC_C || 3896 CC == CC_X86VectorCall || 3897 CC == CC_IntelOclBicc || 3898 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3899 } 3900 3901 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3902 return CC_C; 3903 } 3904 3905 // for x32 we need it here explicitly 3906 bool hasInt128Type() const override { return true; } 3907 }; 3908 3909 // x86-64 Windows target 3910 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3911 public: 3912 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3913 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3914 WCharType = UnsignedShort; 3915 LongWidth = LongAlign = 32; 3916 DoubleAlign = LongLongAlign = 64; 3917 IntMaxType = SignedLongLong; 3918 Int64Type = SignedLongLong; 3919 SizeType = UnsignedLongLong; 3920 PtrDiffType = SignedLongLong; 3921 IntPtrType = SignedLongLong; 3922 this->UserLabelPrefix = ""; 3923 } 3924 3925 void getTargetDefines(const LangOptions &Opts, 3926 MacroBuilder &Builder) const override { 3927 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3928 Builder.defineMacro("_WIN64"); 3929 } 3930 3931 BuiltinVaListKind getBuiltinVaListKind() const override { 3932 return TargetInfo::CharPtrBuiltinVaList; 3933 } 3934 3935 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3936 switch (CC) { 3937 case CC_X86StdCall: 3938 case CC_X86ThisCall: 3939 case CC_X86FastCall: 3940 return CCCR_Ignore; 3941 case CC_C: 3942 case CC_X86VectorCall: 3943 case CC_IntelOclBicc: 3944 case CC_X86_64SysV: 3945 return CCCR_OK; 3946 default: 3947 return CCCR_Warning; 3948 } 3949 } 3950 }; 3951 3952 // x86-64 Windows Visual Studio target 3953 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3954 public: 3955 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3956 : WindowsX86_64TargetInfo(Triple) { 3957 LongDoubleWidth = LongDoubleAlign = 64; 3958 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3959 } 3960 void getTargetDefines(const LangOptions &Opts, 3961 MacroBuilder &Builder) const override { 3962 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3963 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3964 Builder.defineMacro("_M_X64"); 3965 Builder.defineMacro("_M_AMD64"); 3966 } 3967 }; 3968 3969 // x86-64 MinGW target 3970 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3971 public: 3972 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3973 : WindowsX86_64TargetInfo(Triple) {} 3974 void getTargetDefines(const LangOptions &Opts, 3975 MacroBuilder &Builder) const override { 3976 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3977 DefineStd(Builder, "WIN64", Opts); 3978 Builder.defineMacro("__MINGW64__"); 3979 addMinGWDefines(Opts, Builder); 3980 3981 // GCC defines this macro when it is using __gxx_personality_seh0. 3982 if (!Opts.SjLjExceptions) 3983 Builder.defineMacro("__SEH__"); 3984 } 3985 }; 3986 3987 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3988 public: 3989 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3990 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3991 Int64Type = SignedLongLong; 3992 MaxVectorAlign = 256; 3993 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3994 llvm::Triple T = llvm::Triple(Triple); 3995 if (T.isiOS()) 3996 UseSignedCharForObjCBool = false; 3997 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3998 } 3999 }; 4000 4001 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4002 public: 4003 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4004 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4005 IntMaxType = SignedLongLong; 4006 Int64Type = SignedLongLong; 4007 } 4008 }; 4009 4010 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4011 public: 4012 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4013 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4014 IntMaxType = SignedLongLong; 4015 Int64Type = SignedLongLong; 4016 } 4017 }; 4018 4019 class ARMTargetInfo : public TargetInfo { 4020 // Possible FPU choices. 4021 enum FPUMode { 4022 VFP2FPU = (1 << 0), 4023 VFP3FPU = (1 << 1), 4024 VFP4FPU = (1 << 2), 4025 NeonFPU = (1 << 3), 4026 FPARMV8 = (1 << 4) 4027 }; 4028 4029 // Possible HWDiv features. 4030 enum HWDivMode { 4031 HWDivThumb = (1 << 0), 4032 HWDivARM = (1 << 1) 4033 }; 4034 4035 static bool FPUModeIsVFP(FPUMode Mode) { 4036 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4037 } 4038 4039 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4040 static const char * const GCCRegNames[]; 4041 4042 std::string ABI, CPU; 4043 4044 enum { 4045 FP_Default, 4046 FP_VFP, 4047 FP_Neon 4048 } FPMath; 4049 4050 unsigned FPU : 5; 4051 4052 unsigned IsAAPCS : 1; 4053 unsigned IsThumb : 1; 4054 unsigned HWDiv : 2; 4055 4056 // Initialized via features. 4057 unsigned SoftFloat : 1; 4058 unsigned SoftFloatABI : 1; 4059 4060 unsigned CRC : 1; 4061 unsigned Crypto : 1; 4062 4063 // ACLE 6.5.1 Hardware floating point 4064 enum { 4065 HW_FP_HP = (1 << 1), /// half (16-bit) 4066 HW_FP_SP = (1 << 2), /// single (32-bit) 4067 HW_FP_DP = (1 << 3), /// double (64-bit) 4068 }; 4069 uint32_t HW_FP; 4070 4071 static const Builtin::Info BuiltinInfo[]; 4072 4073 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 4074 StringRef ArchName = T.getArchName(); 4075 if (T.getArch() == llvm::Triple::arm || 4076 T.getArch() == llvm::Triple::armeb) { 4077 StringRef VersionStr; 4078 if (ArchName.startswith("armv")) 4079 VersionStr = ArchName.substr(4, 1); 4080 else if (ArchName.startswith("armebv")) 4081 VersionStr = ArchName.substr(6, 1); 4082 else 4083 return false; 4084 unsigned Version; 4085 if (VersionStr.getAsInteger(10, Version)) 4086 return false; 4087 return Version >= 6; 4088 } 4089 assert(T.getArch() == llvm::Triple::thumb || 4090 T.getArch() == llvm::Triple::thumbeb); 4091 StringRef VersionStr; 4092 if (ArchName.startswith("thumbv")) 4093 VersionStr = ArchName.substr(6, 1); 4094 else if (ArchName.startswith("thumbebv")) 4095 VersionStr = ArchName.substr(8, 1); 4096 else 4097 return false; 4098 unsigned Version; 4099 if (VersionStr.getAsInteger(10, Version)) 4100 return false; 4101 return Version >= 7; 4102 } 4103 4104 void setABIAAPCS() { 4105 IsAAPCS = true; 4106 4107 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4108 const llvm::Triple &T = getTriple(); 4109 4110 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4111 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4112 T.getOS() == llvm::Triple::Bitrig) 4113 SizeType = UnsignedLong; 4114 else 4115 SizeType = UnsignedInt; 4116 4117 switch (T.getOS()) { 4118 case llvm::Triple::NetBSD: 4119 WCharType = SignedInt; 4120 break; 4121 case llvm::Triple::Win32: 4122 WCharType = UnsignedShort; 4123 break; 4124 case llvm::Triple::Linux: 4125 default: 4126 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4127 WCharType = UnsignedInt; 4128 break; 4129 } 4130 4131 UseBitFieldTypeAlignment = true; 4132 4133 ZeroLengthBitfieldBoundary = 0; 4134 4135 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4136 // so set preferred for small types to 32. 4137 if (T.isOSBinFormatMachO()) { 4138 DescriptionString = 4139 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4140 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4141 } else if (T.isOSWindows()) { 4142 assert(!BigEndian && "Windows on ARM does not support big endian"); 4143 DescriptionString = "e" 4144 "-m:w" 4145 "-p:32:32" 4146 "-i64:64" 4147 "-v128:64:128" 4148 "-a:0:32" 4149 "-n32" 4150 "-S64"; 4151 } else if (T.isOSNaCl()) { 4152 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4153 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4154 } else { 4155 DescriptionString = 4156 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4157 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4158 } 4159 4160 // FIXME: Enumerated types are variable width in straight AAPCS. 4161 } 4162 4163 void setABIAPCS() { 4164 const llvm::Triple &T = getTriple(); 4165 4166 IsAAPCS = false; 4167 4168 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4169 4170 // size_t is unsigned int on FreeBSD. 4171 if (T.getOS() == llvm::Triple::FreeBSD) 4172 SizeType = UnsignedInt; 4173 else 4174 SizeType = UnsignedLong; 4175 4176 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4177 WCharType = SignedInt; 4178 4179 // Do not respect the alignment of bit-field types when laying out 4180 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4181 UseBitFieldTypeAlignment = false; 4182 4183 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4184 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4185 /// gcc. 4186 ZeroLengthBitfieldBoundary = 32; 4187 4188 if (T.isOSBinFormatMachO()) 4189 DescriptionString = 4190 BigEndian 4191 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4192 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4193 else 4194 DescriptionString = 4195 BigEndian 4196 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4197 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4198 4199 // FIXME: Override "preferred align" for double and long long. 4200 } 4201 4202 public: 4203 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4204 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4205 IsAAPCS(true), HW_FP(0) { 4206 BigEndian = IsBigEndian; 4207 4208 switch (getTriple().getOS()) { 4209 case llvm::Triple::NetBSD: 4210 PtrDiffType = SignedLong; 4211 break; 4212 default: 4213 PtrDiffType = SignedInt; 4214 break; 4215 } 4216 4217 // {} in inline assembly are neon specifiers, not assembly variant 4218 // specifiers. 4219 NoAsmVariants = true; 4220 4221 // FIXME: Should we just treat this as a feature? 4222 IsThumb = getTriple().getArchName().startswith("thumb"); 4223 4224 // FIXME: This duplicates code from the driver that sets the -target-abi 4225 // option - this code is used if -target-abi isn't passed and should 4226 // be unified in some way. 4227 if (Triple.isOSBinFormatMachO()) { 4228 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4229 // the frontend matches that. 4230 if (Triple.getEnvironment() == llvm::Triple::EABI || 4231 Triple.getOS() == llvm::Triple::UnknownOS || 4232 StringRef(CPU).startswith("cortex-m")) { 4233 setABI("aapcs"); 4234 } else { 4235 setABI("apcs-gnu"); 4236 } 4237 } else if (Triple.isOSWindows()) { 4238 // FIXME: this is invalid for WindowsCE 4239 setABI("aapcs"); 4240 } else { 4241 // Select the default based on the platform. 4242 switch (Triple.getEnvironment()) { 4243 case llvm::Triple::Android: 4244 case llvm::Triple::GNUEABI: 4245 case llvm::Triple::GNUEABIHF: 4246 setABI("aapcs-linux"); 4247 break; 4248 case llvm::Triple::EABIHF: 4249 case llvm::Triple::EABI: 4250 setABI("aapcs"); 4251 break; 4252 case llvm::Triple::GNU: 4253 setABI("apcs-gnu"); 4254 break; 4255 default: 4256 if (Triple.getOS() == llvm::Triple::NetBSD) 4257 setABI("apcs-gnu"); 4258 else 4259 setABI("aapcs"); 4260 break; 4261 } 4262 } 4263 4264 // ARM targets default to using the ARM C++ ABI. 4265 TheCXXABI.set(TargetCXXABI::GenericARM); 4266 4267 // ARM has atomics up to 8 bytes 4268 MaxAtomicPromoteWidth = 64; 4269 if (shouldUseInlineAtomic(getTriple())) 4270 MaxAtomicInlineWidth = 64; 4271 4272 // Do force alignment of members that follow zero length bitfields. If 4273 // the alignment of the zero-length bitfield is greater than the member 4274 // that follows it, `bar', `bar' will be aligned as the type of the 4275 // zero length bitfield. 4276 UseZeroLengthBitfieldAlignment = true; 4277 } 4278 4279 StringRef getABI() const override { return ABI; } 4280 4281 bool setABI(const std::string &Name) override { 4282 ABI = Name; 4283 4284 // The defaults (above) are for AAPCS, check if we need to change them. 4285 // 4286 // FIXME: We need support for -meabi... we could just mangle it into the 4287 // name. 4288 if (Name == "apcs-gnu") { 4289 setABIAPCS(); 4290 return true; 4291 } 4292 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4293 setABIAAPCS(); 4294 return true; 4295 } 4296 return false; 4297 } 4298 4299 // FIXME: This should be based on Arch attributes, not CPU names. 4300 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4301 StringRef ArchName = getTriple().getArchName(); 4302 unsigned ArchKind = llvm::ARMTargetParser::parseArch(ArchName); 4303 bool IsV8 = (ArchKind == llvm::ARM::AK_ARMV8A || 4304 ArchKind == llvm::ARM::AK_ARMV8_1A); 4305 4306 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4307 Features["vfp2"] = true; 4308 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4309 Features["vfp3"] = true; 4310 Features["neon"] = true; 4311 } 4312 else if (CPU == "cortex-a5") { 4313 Features["vfp4"] = true; 4314 Features["neon"] = true; 4315 } else if (CPU == "swift" || CPU == "cortex-a7" || 4316 CPU == "cortex-a12" || CPU == "cortex-a15" || 4317 CPU == "cortex-a17" || CPU == "krait") { 4318 Features["vfp4"] = true; 4319 Features["neon"] = true; 4320 Features["hwdiv"] = true; 4321 Features["hwdiv-arm"] = true; 4322 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4323 CPU == "cortex-a72") { 4324 Features["fp-armv8"] = true; 4325 Features["neon"] = true; 4326 Features["hwdiv"] = true; 4327 Features["hwdiv-arm"] = true; 4328 Features["crc"] = true; 4329 Features["crypto"] = true; 4330 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || IsV8) { 4331 Features["hwdiv"] = true; 4332 Features["hwdiv-arm"] = true; 4333 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4334 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4335 Features["hwdiv"] = true; 4336 } 4337 } 4338 4339 bool handleTargetFeatures(std::vector<std::string> &Features, 4340 DiagnosticsEngine &Diags) override { 4341 FPU = 0; 4342 CRC = 0; 4343 Crypto = 0; 4344 SoftFloat = SoftFloatABI = false; 4345 HWDiv = 0; 4346 4347 // This does not diagnose illegal cases like having both 4348 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4349 uint32_t HW_FP_remove = 0; 4350 for (const auto &Feature : Features) { 4351 if (Feature == "+soft-float") { 4352 SoftFloat = true; 4353 } else if (Feature == "+soft-float-abi") { 4354 SoftFloatABI = true; 4355 } else if (Feature == "+vfp2") { 4356 FPU |= VFP2FPU; 4357 HW_FP |= HW_FP_SP | HW_FP_DP; 4358 } else if (Feature == "+vfp3") { 4359 FPU |= VFP3FPU; 4360 HW_FP |= HW_FP_SP | HW_FP_DP; 4361 } else if (Feature == "+vfp4") { 4362 FPU |= VFP4FPU; 4363 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4364 } else if (Feature == "+fp-armv8") { 4365 FPU |= FPARMV8; 4366 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4367 } else if (Feature == "+neon") { 4368 FPU |= NeonFPU; 4369 HW_FP |= HW_FP_SP | HW_FP_DP; 4370 } else if (Feature == "+hwdiv") { 4371 HWDiv |= HWDivThumb; 4372 } else if (Feature == "+hwdiv-arm") { 4373 HWDiv |= HWDivARM; 4374 } else if (Feature == "+crc") { 4375 CRC = 1; 4376 } else if (Feature == "+crypto") { 4377 Crypto = 1; 4378 } else if (Feature == "+fp-only-sp") { 4379 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4380 } 4381 } 4382 HW_FP &= ~HW_FP_remove; 4383 4384 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4385 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4386 return false; 4387 } 4388 4389 if (FPMath == FP_Neon) 4390 Features.push_back("+neonfp"); 4391 else if (FPMath == FP_VFP) 4392 Features.push_back("-neonfp"); 4393 4394 // Remove front-end specific options which the backend handles differently. 4395 auto Feature = 4396 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4397 if (Feature != Features.end()) 4398 Features.erase(Feature); 4399 4400 return true; 4401 } 4402 4403 bool hasFeature(StringRef Feature) const override { 4404 return llvm::StringSwitch<bool>(Feature) 4405 .Case("arm", true) 4406 .Case("softfloat", SoftFloat) 4407 .Case("thumb", IsThumb) 4408 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4409 .Case("hwdiv", HWDiv & HWDivThumb) 4410 .Case("hwdiv-arm", HWDiv & HWDivARM) 4411 .Default(false); 4412 } 4413 const char *getCPUDefineSuffix(StringRef Name) const { 4414 if(Name == "generic") { 4415 auto subarch = getTriple().getSubArch(); 4416 switch (subarch) { 4417 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4418 return "8_1A"; 4419 default: 4420 break; 4421 } 4422 } 4423 4424 unsigned ArchKind = llvm::ARMTargetParser::parseCPUArch(Name); 4425 if (ArchKind == llvm::ARM::AK_INVALID) 4426 return ""; 4427 4428 // For most sub-arches, the build attribute CPU name is enough. 4429 // For Cortex variants, it's slightly different. 4430 switch(ArchKind) { 4431 default: 4432 return llvm::ARMTargetParser::getCPUAttr(ArchKind); 4433 case llvm::ARM::AK_ARMV6M: 4434 case llvm::ARM::AK_ARMV6SM: 4435 return "6M"; 4436 case llvm::ARM::AK_ARMV7: 4437 case llvm::ARM::AK_ARMV7A: 4438 case llvm::ARM::AK_ARMV7S: 4439 return "7A"; 4440 case llvm::ARM::AK_ARMV7R: 4441 return "7R"; 4442 case llvm::ARM::AK_ARMV7M: 4443 return "7M"; 4444 case llvm::ARM::AK_ARMV7EM: 4445 return "7EM"; 4446 case llvm::ARM::AK_ARMV8A: 4447 return "8A"; 4448 case llvm::ARM::AK_ARMV8_1A: 4449 return "8_1A"; 4450 } 4451 } 4452 const char *getCPUProfile(StringRef Name) const { 4453 if(Name == "generic") { 4454 auto subarch = getTriple().getSubArch(); 4455 switch (subarch) { 4456 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4457 return "A"; 4458 default: 4459 break; 4460 } 4461 } 4462 4463 unsigned CPUArch = llvm::ARMTargetParser::parseCPUArch(Name); 4464 if (CPUArch == llvm::ARM::AK_INVALID) 4465 return ""; 4466 4467 StringRef ArchName = llvm::ARMTargetParser::getArchName(CPUArch); 4468 switch(llvm::ARMTargetParser::parseArchProfile(ArchName)) { 4469 case llvm::ARM::PK_A: 4470 return "A"; 4471 case llvm::ARM::PK_R: 4472 return "R"; 4473 case llvm::ARM::PK_M: 4474 return "M"; 4475 default: 4476 return ""; 4477 } 4478 } 4479 bool setCPU(const std::string &Name) override { 4480 if (!getCPUDefineSuffix(Name)) 4481 return false; 4482 4483 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4484 StringRef Profile = getCPUProfile(Name); 4485 if (Profile == "M" && MaxAtomicInlineWidth) { 4486 MaxAtomicPromoteWidth = 32; 4487 MaxAtomicInlineWidth = 32; 4488 } 4489 4490 CPU = Name; 4491 return true; 4492 } 4493 bool setFPMath(StringRef Name) override; 4494 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4495 unsigned CPUArchVer) const { 4496 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4497 (CPUArch.find('M') != StringRef::npos); 4498 } 4499 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4500 unsigned CPUArchVer) const { 4501 // We check both CPUArchVer and ArchName because when only triple is 4502 // specified, the default CPU is arm1136j-s. 4503 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4504 ArchName.endswith("v8.1a") || 4505 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4506 } 4507 void getTargetDefines(const LangOptions &Opts, 4508 MacroBuilder &Builder) const override { 4509 // Target identification. 4510 Builder.defineMacro("__arm"); 4511 Builder.defineMacro("__arm__"); 4512 4513 // Target properties. 4514 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4515 4516 StringRef CPUArch = getCPUDefineSuffix(CPU); 4517 unsigned int CPUArchVer; 4518 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4519 llvm_unreachable("Invalid char for architecture version number"); 4520 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4521 4522 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4523 StringRef CPUProfile = getCPUProfile(CPU); 4524 StringRef ArchName = getTriple().getArchName(); 4525 4526 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4527 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4528 if (CPUArch[0] >= '8') { 4529 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4530 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4531 } 4532 4533 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4534 // is not defined for the M-profile. 4535 // NOTE that the deffault profile is assumed to be 'A' 4536 if (CPUProfile.empty() || CPUProfile != "M") 4537 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4538 4539 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4540 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4541 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4542 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4543 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4544 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4545 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4546 4547 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4548 // instruction set such as ARM or Thumb. 4549 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4550 4551 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4552 4553 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4554 if (!CPUProfile.empty()) 4555 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4556 4557 // ACLE 6.5.1 Hardware Floating Point 4558 if (HW_FP) 4559 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4560 4561 // ACLE predefines. 4562 Builder.defineMacro("__ARM_ACLE", "200"); 4563 4564 // Subtarget options. 4565 4566 // FIXME: It's more complicated than this and we don't really support 4567 // interworking. 4568 // Windows on ARM does not "support" interworking 4569 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4570 Builder.defineMacro("__THUMB_INTERWORK__"); 4571 4572 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4573 // Embedded targets on Darwin follow AAPCS, but not EABI. 4574 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4575 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4576 Builder.defineMacro("__ARM_EABI__"); 4577 Builder.defineMacro("__ARM_PCS", "1"); 4578 4579 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4580 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4581 } 4582 4583 if (SoftFloat) 4584 Builder.defineMacro("__SOFTFP__"); 4585 4586 if (CPU == "xscale") 4587 Builder.defineMacro("__XSCALE__"); 4588 4589 if (IsThumb) { 4590 Builder.defineMacro("__THUMBEL__"); 4591 Builder.defineMacro("__thumb__"); 4592 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4593 Builder.defineMacro("__thumb2__"); 4594 } 4595 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4596 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4597 4598 // Note, this is always on in gcc, even though it doesn't make sense. 4599 Builder.defineMacro("__APCS_32__"); 4600 4601 if (FPUModeIsVFP((FPUMode) FPU)) { 4602 Builder.defineMacro("__VFP_FP__"); 4603 if (FPU & VFP2FPU) 4604 Builder.defineMacro("__ARM_VFPV2__"); 4605 if (FPU & VFP3FPU) 4606 Builder.defineMacro("__ARM_VFPV3__"); 4607 if (FPU & VFP4FPU) 4608 Builder.defineMacro("__ARM_VFPV4__"); 4609 } 4610 4611 // This only gets set when Neon instructions are actually available, unlike 4612 // the VFP define, hence the soft float and arch check. This is subtly 4613 // different from gcc, we follow the intent which was that it should be set 4614 // when Neon instructions are actually available. 4615 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4616 Builder.defineMacro("__ARM_NEON"); 4617 Builder.defineMacro("__ARM_NEON__"); 4618 } 4619 4620 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4621 Opts.ShortWChar ? "2" : "4"); 4622 4623 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4624 Opts.ShortEnums ? "1" : "4"); 4625 4626 if (CRC) 4627 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4628 4629 if (Crypto) 4630 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4631 4632 if (CPUArchVer >= 6 && CPUArch != "6M") { 4633 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4634 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4635 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4636 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4637 } 4638 4639 bool is5EOrAbove = (CPUArchVer >= 6 || 4640 (CPUArchVer == 5 && 4641 CPUArch.find('E') != StringRef::npos)); 4642 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4643 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4644 Builder.defineMacro("__ARM_FEATURE_DSP"); 4645 } 4646 void getTargetBuiltins(const Builtin::Info *&Records, 4647 unsigned &NumRecords) const override { 4648 Records = BuiltinInfo; 4649 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4650 } 4651 bool isCLZForZeroUndef() const override { return false; } 4652 BuiltinVaListKind getBuiltinVaListKind() const override { 4653 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4654 } 4655 void getGCCRegNames(const char * const *&Names, 4656 unsigned &NumNames) const override; 4657 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4658 unsigned &NumAliases) const override; 4659 bool validateAsmConstraint(const char *&Name, 4660 TargetInfo::ConstraintInfo &Info) const override { 4661 switch (*Name) { 4662 default: break; 4663 case 'l': // r0-r7 4664 case 'h': // r8-r15 4665 case 'w': // VFP Floating point register single precision 4666 case 'P': // VFP Floating point register double precision 4667 Info.setAllowsRegister(); 4668 return true; 4669 case 'I': 4670 case 'J': 4671 case 'K': 4672 case 'L': 4673 case 'M': 4674 // FIXME 4675 return true; 4676 case 'Q': // A memory address that is a single base register. 4677 Info.setAllowsMemory(); 4678 return true; 4679 case 'U': // a memory reference... 4680 switch (Name[1]) { 4681 case 'q': // ...ARMV4 ldrsb 4682 case 'v': // ...VFP load/store (reg+constant offset) 4683 case 'y': // ...iWMMXt load/store 4684 case 't': // address valid for load/store opaque types wider 4685 // than 128-bits 4686 case 'n': // valid address for Neon doubleword vector load/store 4687 case 'm': // valid address for Neon element and structure load/store 4688 case 's': // valid address for non-offset loads/stores of quad-word 4689 // values in four ARM registers 4690 Info.setAllowsMemory(); 4691 Name++; 4692 return true; 4693 } 4694 } 4695 return false; 4696 } 4697 std::string convertConstraint(const char *&Constraint) const override { 4698 std::string R; 4699 switch (*Constraint) { 4700 case 'U': // Two-character constraint; add "^" hint for later parsing. 4701 R = std::string("^") + std::string(Constraint, 2); 4702 Constraint++; 4703 break; 4704 case 'p': // 'p' should be translated to 'r' by default. 4705 R = std::string("r"); 4706 break; 4707 default: 4708 return std::string(1, *Constraint); 4709 } 4710 return R; 4711 } 4712 bool 4713 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4714 std::string &SuggestedModifier) const override { 4715 bool isOutput = (Constraint[0] == '='); 4716 bool isInOut = (Constraint[0] == '+'); 4717 4718 // Strip off constraint modifiers. 4719 while (Constraint[0] == '=' || 4720 Constraint[0] == '+' || 4721 Constraint[0] == '&') 4722 Constraint = Constraint.substr(1); 4723 4724 switch (Constraint[0]) { 4725 default: break; 4726 case 'r': { 4727 switch (Modifier) { 4728 default: 4729 return (isInOut || isOutput || Size <= 64); 4730 case 'q': 4731 // A register of size 32 cannot fit a vector type. 4732 return false; 4733 } 4734 } 4735 } 4736 4737 return true; 4738 } 4739 const char *getClobbers() const override { 4740 // FIXME: Is this really right? 4741 return ""; 4742 } 4743 4744 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4745 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4746 } 4747 4748 int getEHDataRegisterNumber(unsigned RegNo) const override { 4749 if (RegNo == 0) return 0; 4750 if (RegNo == 1) return 1; 4751 return -1; 4752 } 4753 4754 bool hasSjLjLowering() const override { 4755 return true; 4756 } 4757 }; 4758 4759 bool ARMTargetInfo::setFPMath(StringRef Name) { 4760 if (Name == "neon") { 4761 FPMath = FP_Neon; 4762 return true; 4763 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4764 Name == "vfp4") { 4765 FPMath = FP_VFP; 4766 return true; 4767 } 4768 return false; 4769 } 4770 4771 const char * const ARMTargetInfo::GCCRegNames[] = { 4772 // Integer registers 4773 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4774 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4775 4776 // Float registers 4777 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4778 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4779 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4780 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4781 4782 // Double registers 4783 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4784 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4785 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4786 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4787 4788 // Quad registers 4789 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4790 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4791 }; 4792 4793 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4794 unsigned &NumNames) const { 4795 Names = GCCRegNames; 4796 NumNames = llvm::array_lengthof(GCCRegNames); 4797 } 4798 4799 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4800 { { "a1" }, "r0" }, 4801 { { "a2" }, "r1" }, 4802 { { "a3" }, "r2" }, 4803 { { "a4" }, "r3" }, 4804 { { "v1" }, "r4" }, 4805 { { "v2" }, "r5" }, 4806 { { "v3" }, "r6" }, 4807 { { "v4" }, "r7" }, 4808 { { "v5" }, "r8" }, 4809 { { "v6", "rfp" }, "r9" }, 4810 { { "sl" }, "r10" }, 4811 { { "fp" }, "r11" }, 4812 { { "ip" }, "r12" }, 4813 { { "r13" }, "sp" }, 4814 { { "r14" }, "lr" }, 4815 { { "r15" }, "pc" }, 4816 // The S, D and Q registers overlap, but aren't really aliases; we 4817 // don't want to substitute one of these for a different-sized one. 4818 }; 4819 4820 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4821 unsigned &NumAliases) const { 4822 Aliases = GCCRegAliases; 4823 NumAliases = llvm::array_lengthof(GCCRegAliases); 4824 } 4825 4826 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4827 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4829 ALL_LANGUAGES }, 4830 #include "clang/Basic/BuiltinsNEON.def" 4831 4832 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4833 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4834 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4835 ALL_LANGUAGES }, 4836 #include "clang/Basic/BuiltinsARM.def" 4837 }; 4838 4839 class ARMleTargetInfo : public ARMTargetInfo { 4840 public: 4841 ARMleTargetInfo(const llvm::Triple &Triple) 4842 : ARMTargetInfo(Triple, false) { } 4843 void getTargetDefines(const LangOptions &Opts, 4844 MacroBuilder &Builder) const override { 4845 Builder.defineMacro("__ARMEL__"); 4846 ARMTargetInfo::getTargetDefines(Opts, Builder); 4847 } 4848 }; 4849 4850 class ARMbeTargetInfo : public ARMTargetInfo { 4851 public: 4852 ARMbeTargetInfo(const llvm::Triple &Triple) 4853 : ARMTargetInfo(Triple, true) { } 4854 void getTargetDefines(const LangOptions &Opts, 4855 MacroBuilder &Builder) const override { 4856 Builder.defineMacro("__ARMEB__"); 4857 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4858 ARMTargetInfo::getTargetDefines(Opts, Builder); 4859 } 4860 }; 4861 4862 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4863 const llvm::Triple Triple; 4864 public: 4865 WindowsARMTargetInfo(const llvm::Triple &Triple) 4866 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4867 TLSSupported = false; 4868 WCharType = UnsignedShort; 4869 SizeType = UnsignedInt; 4870 UserLabelPrefix = ""; 4871 } 4872 void getVisualStudioDefines(const LangOptions &Opts, 4873 MacroBuilder &Builder) const { 4874 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4875 4876 // FIXME: this is invalid for WindowsCE 4877 Builder.defineMacro("_M_ARM_NT", "1"); 4878 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4879 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4880 4881 assert((Triple.getArch() == llvm::Triple::arm || 4882 Triple.getArch() == llvm::Triple::thumb) && 4883 "invalid architecture for Windows ARM target info"); 4884 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4885 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4886 4887 // TODO map the complete set of values 4888 // 31: VFPv3 40: VFPv4 4889 Builder.defineMacro("_M_ARM_FP", "31"); 4890 } 4891 BuiltinVaListKind getBuiltinVaListKind() const override { 4892 return TargetInfo::CharPtrBuiltinVaList; 4893 } 4894 }; 4895 4896 // Windows ARM + Itanium C++ ABI Target 4897 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4898 public: 4899 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4900 : WindowsARMTargetInfo(Triple) { 4901 TheCXXABI.set(TargetCXXABI::GenericARM); 4902 } 4903 4904 void getTargetDefines(const LangOptions &Opts, 4905 MacroBuilder &Builder) const override { 4906 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4907 4908 if (Opts.MSVCCompat) 4909 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4910 } 4911 }; 4912 4913 // Windows ARM, MS (C++) ABI 4914 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4915 public: 4916 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4917 : WindowsARMTargetInfo(Triple) { 4918 TheCXXABI.set(TargetCXXABI::Microsoft); 4919 } 4920 4921 void getTargetDefines(const LangOptions &Opts, 4922 MacroBuilder &Builder) const override { 4923 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4924 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4925 } 4926 }; 4927 4928 // ARM MinGW target 4929 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 4930 public: 4931 MinGWARMTargetInfo(const llvm::Triple &Triple) 4932 : WindowsARMTargetInfo(Triple) { 4933 TheCXXABI.set(TargetCXXABI::GenericARM); 4934 } 4935 4936 void getTargetDefines(const LangOptions &Opts, 4937 MacroBuilder &Builder) const override { 4938 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4939 DefineStd(Builder, "WIN32", Opts); 4940 DefineStd(Builder, "WINNT", Opts); 4941 Builder.defineMacro("_ARM_"); 4942 addMinGWDefines(Opts, Builder); 4943 } 4944 }; 4945 4946 // ARM Cygwin target 4947 class CygwinARMTargetInfo : public ARMleTargetInfo { 4948 public: 4949 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 4950 TLSSupported = false; 4951 WCharType = UnsignedShort; 4952 DoubleAlign = LongLongAlign = 64; 4953 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4954 } 4955 void getTargetDefines(const LangOptions &Opts, 4956 MacroBuilder &Builder) const override { 4957 ARMleTargetInfo::getTargetDefines(Opts, Builder); 4958 Builder.defineMacro("_ARM_"); 4959 Builder.defineMacro("__CYGWIN__"); 4960 Builder.defineMacro("__CYGWIN32__"); 4961 DefineStd(Builder, "unix", Opts); 4962 if (Opts.CPlusPlus) 4963 Builder.defineMacro("_GNU_SOURCE"); 4964 } 4965 }; 4966 4967 class DarwinARMTargetInfo : 4968 public DarwinTargetInfo<ARMleTargetInfo> { 4969 protected: 4970 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4971 MacroBuilder &Builder) const override { 4972 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4973 } 4974 4975 public: 4976 DarwinARMTargetInfo(const llvm::Triple &Triple) 4977 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4978 HasAlignMac68kSupport = true; 4979 // iOS always has 64-bit atomic instructions. 4980 // FIXME: This should be based off of the target features in 4981 // ARMleTargetInfo. 4982 MaxAtomicInlineWidth = 64; 4983 4984 // Darwin on iOS uses a variant of the ARM C++ ABI. 4985 TheCXXABI.set(TargetCXXABI::iOS); 4986 } 4987 }; 4988 4989 class AArch64TargetInfo : public TargetInfo { 4990 virtual void setDescriptionString() = 0; 4991 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4992 static const char *const GCCRegNames[]; 4993 4994 enum FPUModeEnum { 4995 FPUMode, 4996 NeonMode 4997 }; 4998 4999 unsigned FPU; 5000 unsigned CRC; 5001 unsigned Crypto; 5002 5003 static const Builtin::Info BuiltinInfo[]; 5004 5005 std::string ABI; 5006 5007 public: 5008 AArch64TargetInfo(const llvm::Triple &Triple) 5009 : TargetInfo(Triple), ABI("aapcs") { 5010 5011 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5012 WCharType = SignedInt; 5013 5014 // NetBSD apparently prefers consistency across ARM targets to consistency 5015 // across 64-bit targets. 5016 Int64Type = SignedLongLong; 5017 IntMaxType = SignedLongLong; 5018 } else { 5019 WCharType = UnsignedInt; 5020 Int64Type = SignedLong; 5021 IntMaxType = SignedLong; 5022 } 5023 5024 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5025 MaxVectorAlign = 128; 5026 RegParmMax = 8; 5027 MaxAtomicInlineWidth = 128; 5028 MaxAtomicPromoteWidth = 128; 5029 5030 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5031 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5032 5033 // {} in inline assembly are neon specifiers, not assembly variant 5034 // specifiers. 5035 NoAsmVariants = true; 5036 5037 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5038 // contributes to the alignment of the containing aggregate in the same way 5039 // a plain (non bit-field) member of that type would, without exception for 5040 // zero-sized or anonymous bit-fields." 5041 UseBitFieldTypeAlignment = true; 5042 UseZeroLengthBitfieldAlignment = true; 5043 5044 // AArch64 targets default to using the ARM C++ ABI. 5045 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5046 } 5047 5048 StringRef getABI() const override { return ABI; } 5049 bool setABI(const std::string &Name) override { 5050 if (Name != "aapcs" && Name != "darwinpcs") 5051 return false; 5052 5053 ABI = Name; 5054 return true; 5055 } 5056 5057 bool setCPU(const std::string &Name) override { 5058 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5059 .Case("generic", true) 5060 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5061 .Case("cyclone", true) 5062 .Default(false); 5063 return CPUKnown; 5064 } 5065 5066 void getTargetDefines(const LangOptions &Opts, 5067 MacroBuilder &Builder) const override { 5068 // Target identification. 5069 Builder.defineMacro("__aarch64__"); 5070 5071 // Target properties. 5072 Builder.defineMacro("_LP64"); 5073 Builder.defineMacro("__LP64__"); 5074 5075 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5076 Builder.defineMacro("__ARM_ACLE", "200"); 5077 Builder.defineMacro("__ARM_ARCH", "8"); 5078 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5079 5080 Builder.defineMacro("__ARM_64BIT_STATE"); 5081 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5082 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 5083 5084 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 5085 Builder.defineMacro("__ARM_FEATURE_CLZ"); 5086 Builder.defineMacro("__ARM_FEATURE_FMA"); 5087 Builder.defineMacro("__ARM_FEATURE_DIV"); 5088 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 5089 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5090 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 5091 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 5092 5093 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5094 5095 // 0xe implies support for half, single and double precision operations. 5096 Builder.defineMacro("__ARM_FP", "0xe"); 5097 5098 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5099 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5100 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 5101 5102 if (Opts.FastMath || Opts.FiniteMathOnly) 5103 Builder.defineMacro("__ARM_FP_FAST"); 5104 5105 if (Opts.C99 && !Opts.Freestanding) 5106 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5107 5108 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5109 5110 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5111 Opts.ShortEnums ? "1" : "4"); 5112 5113 if (FPU == NeonMode) { 5114 Builder.defineMacro("__ARM_NEON"); 5115 // 64-bit NEON supports half, single and double precision operations. 5116 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 5117 } 5118 5119 if (CRC) 5120 Builder.defineMacro("__ARM_FEATURE_CRC32"); 5121 5122 if (Crypto) 5123 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 5124 5125 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5126 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5127 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5128 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5129 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5130 } 5131 5132 void getTargetBuiltins(const Builtin::Info *&Records, 5133 unsigned &NumRecords) const override { 5134 Records = BuiltinInfo; 5135 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5136 } 5137 5138 bool hasFeature(StringRef Feature) const override { 5139 return Feature == "aarch64" || 5140 Feature == "arm64" || 5141 (Feature == "neon" && FPU == NeonMode); 5142 } 5143 5144 bool handleTargetFeatures(std::vector<std::string> &Features, 5145 DiagnosticsEngine &Diags) override { 5146 FPU = FPUMode; 5147 CRC = 0; 5148 Crypto = 0; 5149 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5150 if (Features[i] == "+neon") 5151 FPU = NeonMode; 5152 if (Features[i] == "+crc") 5153 CRC = 1; 5154 if (Features[i] == "+crypto") 5155 Crypto = 1; 5156 } 5157 5158 setDescriptionString(); 5159 5160 return true; 5161 } 5162 5163 bool isCLZForZeroUndef() const override { return false; } 5164 5165 BuiltinVaListKind getBuiltinVaListKind() const override { 5166 return TargetInfo::AArch64ABIBuiltinVaList; 5167 } 5168 5169 void getGCCRegNames(const char *const *&Names, 5170 unsigned &NumNames) const override; 5171 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5172 unsigned &NumAliases) const override; 5173 5174 bool validateAsmConstraint(const char *&Name, 5175 TargetInfo::ConstraintInfo &Info) const override { 5176 switch (*Name) { 5177 default: 5178 return false; 5179 case 'w': // Floating point and SIMD registers (V0-V31) 5180 Info.setAllowsRegister(); 5181 return true; 5182 case 'I': // Constant that can be used with an ADD instruction 5183 case 'J': // Constant that can be used with a SUB instruction 5184 case 'K': // Constant that can be used with a 32-bit logical instruction 5185 case 'L': // Constant that can be used with a 64-bit logical instruction 5186 case 'M': // Constant that can be used as a 32-bit MOV immediate 5187 case 'N': // Constant that can be used as a 64-bit MOV immediate 5188 case 'Y': // Floating point constant zero 5189 case 'Z': // Integer constant zero 5190 return true; 5191 case 'Q': // A memory reference with base register and no offset 5192 Info.setAllowsMemory(); 5193 return true; 5194 case 'S': // A symbolic address 5195 Info.setAllowsRegister(); 5196 return true; 5197 case 'U': 5198 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5199 // Utf: A memory address suitable for ldp/stp in TF mode. 5200 // Usa: An absolute symbolic address. 5201 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5202 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5203 case 'z': // Zero register, wzr or xzr 5204 Info.setAllowsRegister(); 5205 return true; 5206 case 'x': // Floating point and SIMD registers (V0-V15) 5207 Info.setAllowsRegister(); 5208 return true; 5209 } 5210 return false; 5211 } 5212 5213 bool 5214 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5215 std::string &SuggestedModifier) const override { 5216 // Strip off constraint modifiers. 5217 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5218 Constraint = Constraint.substr(1); 5219 5220 switch (Constraint[0]) { 5221 default: 5222 return true; 5223 case 'z': 5224 case 'r': { 5225 switch (Modifier) { 5226 case 'x': 5227 case 'w': 5228 // For now assume that the person knows what they're 5229 // doing with the modifier. 5230 return true; 5231 default: 5232 // By default an 'r' constraint will be in the 'x' 5233 // registers. 5234 if (Size == 64) 5235 return true; 5236 5237 SuggestedModifier = "w"; 5238 return false; 5239 } 5240 } 5241 } 5242 } 5243 5244 const char *getClobbers() const override { return ""; } 5245 5246 int getEHDataRegisterNumber(unsigned RegNo) const override { 5247 if (RegNo == 0) 5248 return 0; 5249 if (RegNo == 1) 5250 return 1; 5251 return -1; 5252 } 5253 }; 5254 5255 const char *const AArch64TargetInfo::GCCRegNames[] = { 5256 // 32-bit Integer registers 5257 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5258 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5259 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5260 5261 // 64-bit Integer registers 5262 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5263 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5264 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5265 5266 // 32-bit floating point regsisters 5267 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5268 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5269 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5270 5271 // 64-bit floating point regsisters 5272 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5273 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5274 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5275 5276 // Vector registers 5277 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5278 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5279 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5280 }; 5281 5282 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5283 unsigned &NumNames) const { 5284 Names = GCCRegNames; 5285 NumNames = llvm::array_lengthof(GCCRegNames); 5286 } 5287 5288 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5289 { { "w31" }, "wsp" }, 5290 { { "x29" }, "fp" }, 5291 { { "x30" }, "lr" }, 5292 { { "x31" }, "sp" }, 5293 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5294 // don't want to substitute one of these for a different-sized one. 5295 }; 5296 5297 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5298 unsigned &NumAliases) const { 5299 Aliases = GCCRegAliases; 5300 NumAliases = llvm::array_lengthof(GCCRegAliases); 5301 } 5302 5303 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5304 #define BUILTIN(ID, TYPE, ATTRS) \ 5305 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5306 #include "clang/Basic/BuiltinsNEON.def" 5307 5308 #define BUILTIN(ID, TYPE, ATTRS) \ 5309 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5310 #include "clang/Basic/BuiltinsAArch64.def" 5311 }; 5312 5313 class AArch64leTargetInfo : public AArch64TargetInfo { 5314 void setDescriptionString() override { 5315 if (getTriple().isOSBinFormatMachO()) 5316 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5317 else 5318 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5319 } 5320 5321 public: 5322 AArch64leTargetInfo(const llvm::Triple &Triple) 5323 : AArch64TargetInfo(Triple) { 5324 BigEndian = false; 5325 } 5326 void getTargetDefines(const LangOptions &Opts, 5327 MacroBuilder &Builder) const override { 5328 Builder.defineMacro("__AARCH64EL__"); 5329 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5330 } 5331 }; 5332 5333 class AArch64beTargetInfo : public AArch64TargetInfo { 5334 void setDescriptionString() override { 5335 assert(!getTriple().isOSBinFormatMachO()); 5336 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5337 } 5338 5339 public: 5340 AArch64beTargetInfo(const llvm::Triple &Triple) 5341 : AArch64TargetInfo(Triple) { } 5342 void getTargetDefines(const LangOptions &Opts, 5343 MacroBuilder &Builder) const override { 5344 Builder.defineMacro("__AARCH64EB__"); 5345 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5346 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5347 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5348 } 5349 }; 5350 5351 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5352 protected: 5353 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5354 MacroBuilder &Builder) const override { 5355 Builder.defineMacro("__AARCH64_SIMD__"); 5356 Builder.defineMacro("__ARM64_ARCH_8__"); 5357 Builder.defineMacro("__ARM_NEON__"); 5358 Builder.defineMacro("__LITTLE_ENDIAN__"); 5359 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5360 Builder.defineMacro("__arm64", "1"); 5361 Builder.defineMacro("__arm64__", "1"); 5362 5363 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5364 } 5365 5366 public: 5367 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5368 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5369 Int64Type = SignedLongLong; 5370 WCharType = SignedInt; 5371 UseSignedCharForObjCBool = false; 5372 5373 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5374 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5375 5376 TheCXXABI.set(TargetCXXABI::iOS64); 5377 } 5378 5379 BuiltinVaListKind getBuiltinVaListKind() const override { 5380 return TargetInfo::CharPtrBuiltinVaList; 5381 } 5382 }; 5383 5384 // Hexagon abstract base class 5385 class HexagonTargetInfo : public TargetInfo { 5386 static const Builtin::Info BuiltinInfo[]; 5387 static const char * const GCCRegNames[]; 5388 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5389 std::string CPU; 5390 public: 5391 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5392 BigEndian = false; 5393 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5394 5395 // {} in inline assembly are packet specifiers, not assembly variant 5396 // specifiers. 5397 NoAsmVariants = true; 5398 } 5399 5400 void getTargetBuiltins(const Builtin::Info *&Records, 5401 unsigned &NumRecords) const override { 5402 Records = BuiltinInfo; 5403 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5404 } 5405 5406 bool validateAsmConstraint(const char *&Name, 5407 TargetInfo::ConstraintInfo &Info) const override { 5408 return true; 5409 } 5410 5411 void getTargetDefines(const LangOptions &Opts, 5412 MacroBuilder &Builder) const override; 5413 5414 bool hasFeature(StringRef Feature) const override { 5415 return Feature == "hexagon"; 5416 } 5417 5418 BuiltinVaListKind getBuiltinVaListKind() const override { 5419 return TargetInfo::CharPtrBuiltinVaList; 5420 } 5421 void getGCCRegNames(const char * const *&Names, 5422 unsigned &NumNames) const override; 5423 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5424 unsigned &NumAliases) const override; 5425 const char *getClobbers() const override { 5426 return ""; 5427 } 5428 5429 static const char *getHexagonCPUSuffix(StringRef Name) { 5430 return llvm::StringSwitch<const char*>(Name) 5431 .Case("hexagonv4", "4") 5432 .Case("hexagonv5", "5") 5433 .Default(nullptr); 5434 } 5435 5436 bool setCPU(const std::string &Name) override { 5437 if (!getHexagonCPUSuffix(Name)) 5438 return false; 5439 5440 CPU = Name; 5441 return true; 5442 } 5443 }; 5444 5445 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5446 MacroBuilder &Builder) const { 5447 Builder.defineMacro("qdsp6"); 5448 Builder.defineMacro("__qdsp6", "1"); 5449 Builder.defineMacro("__qdsp6__", "1"); 5450 5451 Builder.defineMacro("hexagon"); 5452 Builder.defineMacro("__hexagon", "1"); 5453 Builder.defineMacro("__hexagon__", "1"); 5454 5455 if(CPU == "hexagonv1") { 5456 Builder.defineMacro("__HEXAGON_V1__"); 5457 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5458 if(Opts.HexagonQdsp6Compat) { 5459 Builder.defineMacro("__QDSP6_V1__"); 5460 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5461 } 5462 } 5463 else if(CPU == "hexagonv2") { 5464 Builder.defineMacro("__HEXAGON_V2__"); 5465 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5466 if(Opts.HexagonQdsp6Compat) { 5467 Builder.defineMacro("__QDSP6_V2__"); 5468 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5469 } 5470 } 5471 else if(CPU == "hexagonv3") { 5472 Builder.defineMacro("__HEXAGON_V3__"); 5473 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5474 if(Opts.HexagonQdsp6Compat) { 5475 Builder.defineMacro("__QDSP6_V3__"); 5476 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5477 } 5478 } 5479 else if(CPU == "hexagonv4") { 5480 Builder.defineMacro("__HEXAGON_V4__"); 5481 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5482 if(Opts.HexagonQdsp6Compat) { 5483 Builder.defineMacro("__QDSP6_V4__"); 5484 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5485 } 5486 } 5487 else if(CPU == "hexagonv5") { 5488 Builder.defineMacro("__HEXAGON_V5__"); 5489 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5490 if(Opts.HexagonQdsp6Compat) { 5491 Builder.defineMacro("__QDSP6_V5__"); 5492 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5493 } 5494 } 5495 } 5496 5497 const char * const HexagonTargetInfo::GCCRegNames[] = { 5498 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5499 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5500 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5501 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5502 "p0", "p1", "p2", "p3", 5503 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5504 }; 5505 5506 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5507 unsigned &NumNames) const { 5508 Names = GCCRegNames; 5509 NumNames = llvm::array_lengthof(GCCRegNames); 5510 } 5511 5512 5513 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5514 { { "sp" }, "r29" }, 5515 { { "fp" }, "r30" }, 5516 { { "lr" }, "r31" }, 5517 }; 5518 5519 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5520 unsigned &NumAliases) const { 5521 Aliases = GCCRegAliases; 5522 NumAliases = llvm::array_lengthof(GCCRegAliases); 5523 } 5524 5525 5526 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5527 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5528 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5529 ALL_LANGUAGES }, 5530 #include "clang/Basic/BuiltinsHexagon.def" 5531 }; 5532 5533 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5534 class SparcTargetInfo : public TargetInfo { 5535 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5536 static const char * const GCCRegNames[]; 5537 bool SoftFloat; 5538 public: 5539 SparcTargetInfo(const llvm::Triple &Triple) 5540 : TargetInfo(Triple), SoftFloat(false) {} 5541 5542 bool handleTargetFeatures(std::vector<std::string> &Features, 5543 DiagnosticsEngine &Diags) override { 5544 // The backend doesn't actually handle soft float yet, but in case someone 5545 // is using the support for the front end continue to support it. 5546 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5547 if (Feature != Features.end()) { 5548 SoftFloat = true; 5549 Features.erase(Feature); 5550 } 5551 return true; 5552 } 5553 void getTargetDefines(const LangOptions &Opts, 5554 MacroBuilder &Builder) const override { 5555 DefineStd(Builder, "sparc", Opts); 5556 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5557 5558 if (SoftFloat) 5559 Builder.defineMacro("SOFT_FLOAT", "1"); 5560 } 5561 5562 bool hasFeature(StringRef Feature) const override { 5563 return llvm::StringSwitch<bool>(Feature) 5564 .Case("softfloat", SoftFloat) 5565 .Case("sparc", true) 5566 .Default(false); 5567 } 5568 5569 void getTargetBuiltins(const Builtin::Info *&Records, 5570 unsigned &NumRecords) const override { 5571 // FIXME: Implement! 5572 } 5573 BuiltinVaListKind getBuiltinVaListKind() const override { 5574 return TargetInfo::VoidPtrBuiltinVaList; 5575 } 5576 void getGCCRegNames(const char * const *&Names, 5577 unsigned &NumNames) const override; 5578 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5579 unsigned &NumAliases) const override; 5580 bool validateAsmConstraint(const char *&Name, 5581 TargetInfo::ConstraintInfo &info) const override { 5582 // FIXME: Implement! 5583 switch (*Name) { 5584 case 'I': // Signed 13-bit constant 5585 case 'J': // Zero 5586 case 'K': // 32-bit constant with the low 12 bits clear 5587 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5588 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5589 case 'N': // Same as 'K' but zext (required for SIMode) 5590 case 'O': // The constant 4096 5591 return true; 5592 } 5593 return false; 5594 } 5595 const char *getClobbers() const override { 5596 // FIXME: Implement! 5597 return ""; 5598 } 5599 }; 5600 5601 const char * const SparcTargetInfo::GCCRegNames[] = { 5602 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5603 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5604 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5605 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5606 }; 5607 5608 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5609 unsigned &NumNames) const { 5610 Names = GCCRegNames; 5611 NumNames = llvm::array_lengthof(GCCRegNames); 5612 } 5613 5614 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5615 { { "g0" }, "r0" }, 5616 { { "g1" }, "r1" }, 5617 { { "g2" }, "r2" }, 5618 { { "g3" }, "r3" }, 5619 { { "g4" }, "r4" }, 5620 { { "g5" }, "r5" }, 5621 { { "g6" }, "r6" }, 5622 { { "g7" }, "r7" }, 5623 { { "o0" }, "r8" }, 5624 { { "o1" }, "r9" }, 5625 { { "o2" }, "r10" }, 5626 { { "o3" }, "r11" }, 5627 { { "o4" }, "r12" }, 5628 { { "o5" }, "r13" }, 5629 { { "o6", "sp" }, "r14" }, 5630 { { "o7" }, "r15" }, 5631 { { "l0" }, "r16" }, 5632 { { "l1" }, "r17" }, 5633 { { "l2" }, "r18" }, 5634 { { "l3" }, "r19" }, 5635 { { "l4" }, "r20" }, 5636 { { "l5" }, "r21" }, 5637 { { "l6" }, "r22" }, 5638 { { "l7" }, "r23" }, 5639 { { "i0" }, "r24" }, 5640 { { "i1" }, "r25" }, 5641 { { "i2" }, "r26" }, 5642 { { "i3" }, "r27" }, 5643 { { "i4" }, "r28" }, 5644 { { "i5" }, "r29" }, 5645 { { "i6", "fp" }, "r30" }, 5646 { { "i7" }, "r31" }, 5647 }; 5648 5649 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5650 unsigned &NumAliases) const { 5651 Aliases = GCCRegAliases; 5652 NumAliases = llvm::array_lengthof(GCCRegAliases); 5653 } 5654 5655 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5656 class SparcV8TargetInfo : public SparcTargetInfo { 5657 public: 5658 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5659 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5660 // NetBSD uses long (same as llvm default); everyone else uses int. 5661 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5662 SizeType = UnsignedLong; 5663 IntPtrType = SignedLong; 5664 PtrDiffType = SignedLong; 5665 } else { 5666 SizeType = UnsignedInt; 5667 IntPtrType = SignedInt; 5668 PtrDiffType = SignedInt; 5669 } 5670 } 5671 5672 void getTargetDefines(const LangOptions &Opts, 5673 MacroBuilder &Builder) const override { 5674 SparcTargetInfo::getTargetDefines(Opts, Builder); 5675 Builder.defineMacro("__sparcv8"); 5676 } 5677 }; 5678 5679 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5680 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5681 public: 5682 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5683 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5684 BigEndian = false; 5685 } 5686 }; 5687 5688 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5689 class SparcV9TargetInfo : public SparcTargetInfo { 5690 public: 5691 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5692 // FIXME: Support Sparc quad-precision long double? 5693 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5694 // This is an LP64 platform. 5695 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5696 5697 // OpenBSD uses long long for int64_t and intmax_t. 5698 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5699 IntMaxType = SignedLongLong; 5700 else 5701 IntMaxType = SignedLong; 5702 Int64Type = IntMaxType; 5703 5704 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5705 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5706 LongDoubleWidth = 128; 5707 LongDoubleAlign = 128; 5708 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5709 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5710 } 5711 5712 void getTargetDefines(const LangOptions &Opts, 5713 MacroBuilder &Builder) const override { 5714 SparcTargetInfo::getTargetDefines(Opts, Builder); 5715 Builder.defineMacro("__sparcv9"); 5716 Builder.defineMacro("__arch64__"); 5717 // Solaris doesn't need these variants, but the BSDs do. 5718 if (getTriple().getOS() != llvm::Triple::Solaris) { 5719 Builder.defineMacro("__sparc64__"); 5720 Builder.defineMacro("__sparc_v9__"); 5721 Builder.defineMacro("__sparcv9__"); 5722 } 5723 } 5724 5725 bool setCPU(const std::string &Name) override { 5726 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5727 .Case("v9", true) 5728 .Case("ultrasparc", true) 5729 .Case("ultrasparc3", true) 5730 .Case("niagara", true) 5731 .Case("niagara2", true) 5732 .Case("niagara3", true) 5733 .Case("niagara4", true) 5734 .Default(false); 5735 5736 // No need to store the CPU yet. There aren't any CPU-specific 5737 // macros to define. 5738 return CPUKnown; 5739 } 5740 }; 5741 5742 class SystemZTargetInfo : public TargetInfo { 5743 static const Builtin::Info BuiltinInfo[]; 5744 static const char *const GCCRegNames[]; 5745 std::string CPU; 5746 bool HasTransactionalExecution; 5747 bool HasVector; 5748 5749 public: 5750 SystemZTargetInfo(const llvm::Triple &Triple) 5751 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5752 IntMaxType = SignedLong; 5753 Int64Type = SignedLong; 5754 TLSSupported = true; 5755 IntWidth = IntAlign = 32; 5756 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5757 PointerWidth = PointerAlign = 64; 5758 LongDoubleWidth = 128; 5759 LongDoubleAlign = 64; 5760 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5761 DefaultAlignForAttributeAligned = 64; 5762 MinGlobalAlign = 16; 5763 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5764 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5765 } 5766 void getTargetDefines(const LangOptions &Opts, 5767 MacroBuilder &Builder) const override { 5768 Builder.defineMacro("__s390__"); 5769 Builder.defineMacro("__s390x__"); 5770 Builder.defineMacro("__zarch__"); 5771 Builder.defineMacro("__LONG_DOUBLE_128__"); 5772 if (HasTransactionalExecution) 5773 Builder.defineMacro("__HTM__"); 5774 } 5775 void getTargetBuiltins(const Builtin::Info *&Records, 5776 unsigned &NumRecords) const override { 5777 Records = BuiltinInfo; 5778 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5779 } 5780 5781 void getGCCRegNames(const char *const *&Names, 5782 unsigned &NumNames) const override; 5783 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5784 unsigned &NumAliases) const override { 5785 // No aliases. 5786 Aliases = nullptr; 5787 NumAliases = 0; 5788 } 5789 bool validateAsmConstraint(const char *&Name, 5790 TargetInfo::ConstraintInfo &info) const override; 5791 const char *getClobbers() const override { 5792 // FIXME: Is this really right? 5793 return ""; 5794 } 5795 BuiltinVaListKind getBuiltinVaListKind() const override { 5796 return TargetInfo::SystemZBuiltinVaList; 5797 } 5798 bool setCPU(const std::string &Name) override { 5799 CPU = Name; 5800 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5801 .Case("z10", true) 5802 .Case("z196", true) 5803 .Case("zEC12", true) 5804 .Case("z13", true) 5805 .Default(false); 5806 5807 return CPUKnown; 5808 } 5809 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5810 if (CPU == "zEC12") 5811 Features["transactional-execution"] = true; 5812 if (CPU == "z13") { 5813 Features["transactional-execution"] = true; 5814 Features["vector"] = true; 5815 } 5816 } 5817 5818 bool handleTargetFeatures(std::vector<std::string> &Features, 5819 DiagnosticsEngine &Diags) override { 5820 HasTransactionalExecution = false; 5821 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5822 if (Features[i] == "+transactional-execution") 5823 HasTransactionalExecution = true; 5824 if (Features[i] == "+vector") 5825 HasVector = true; 5826 } 5827 // If we use the vector ABI, vector types are 64-bit aligned. 5828 if (HasVector) { 5829 MaxVectorAlign = 64; 5830 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5831 "-v128:64-a:8:16-n32:64"; 5832 } 5833 return true; 5834 } 5835 5836 bool hasFeature(StringRef Feature) const override { 5837 return llvm::StringSwitch<bool>(Feature) 5838 .Case("systemz", true) 5839 .Case("htm", HasTransactionalExecution) 5840 .Case("vx", HasVector) 5841 .Default(false); 5842 } 5843 5844 StringRef getABI() const override { 5845 if (HasVector) 5846 return "vector"; 5847 return ""; 5848 } 5849 5850 bool useFloat128ManglingForLongDouble() const override { 5851 return true; 5852 } 5853 }; 5854 5855 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5856 #define BUILTIN(ID, TYPE, ATTRS) \ 5857 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5858 #include "clang/Basic/BuiltinsSystemZ.def" 5859 }; 5860 5861 const char *const SystemZTargetInfo::GCCRegNames[] = { 5862 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5863 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5864 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5865 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5866 }; 5867 5868 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5869 unsigned &NumNames) const { 5870 Names = GCCRegNames; 5871 NumNames = llvm::array_lengthof(GCCRegNames); 5872 } 5873 5874 bool SystemZTargetInfo:: 5875 validateAsmConstraint(const char *&Name, 5876 TargetInfo::ConstraintInfo &Info) const { 5877 switch (*Name) { 5878 default: 5879 return false; 5880 5881 case 'a': // Address register 5882 case 'd': // Data register (equivalent to 'r') 5883 case 'f': // Floating-point register 5884 Info.setAllowsRegister(); 5885 return true; 5886 5887 case 'I': // Unsigned 8-bit constant 5888 case 'J': // Unsigned 12-bit constant 5889 case 'K': // Signed 16-bit constant 5890 case 'L': // Signed 20-bit displacement (on all targets we support) 5891 case 'M': // 0x7fffffff 5892 return true; 5893 5894 case 'Q': // Memory with base and unsigned 12-bit displacement 5895 case 'R': // Likewise, plus an index 5896 case 'S': // Memory with base and signed 20-bit displacement 5897 case 'T': // Likewise, plus an index 5898 Info.setAllowsMemory(); 5899 return true; 5900 } 5901 } 5902 5903 class MSP430TargetInfo : public TargetInfo { 5904 static const char * const GCCRegNames[]; 5905 public: 5906 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5907 BigEndian = false; 5908 TLSSupported = false; 5909 IntWidth = 16; IntAlign = 16; 5910 LongWidth = 32; LongLongWidth = 64; 5911 LongAlign = LongLongAlign = 16; 5912 PointerWidth = 16; PointerAlign = 16; 5913 SuitableAlign = 16; 5914 SizeType = UnsignedInt; 5915 IntMaxType = SignedLongLong; 5916 IntPtrType = SignedInt; 5917 PtrDiffType = SignedInt; 5918 SigAtomicType = SignedLong; 5919 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5920 } 5921 void getTargetDefines(const LangOptions &Opts, 5922 MacroBuilder &Builder) const override { 5923 Builder.defineMacro("MSP430"); 5924 Builder.defineMacro("__MSP430__"); 5925 // FIXME: defines for different 'flavours' of MCU 5926 } 5927 void getTargetBuiltins(const Builtin::Info *&Records, 5928 unsigned &NumRecords) const override { 5929 // FIXME: Implement. 5930 Records = nullptr; 5931 NumRecords = 0; 5932 } 5933 bool hasFeature(StringRef Feature) const override { 5934 return Feature == "msp430"; 5935 } 5936 void getGCCRegNames(const char * const *&Names, 5937 unsigned &NumNames) const override; 5938 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5939 unsigned &NumAliases) const override { 5940 // No aliases. 5941 Aliases = nullptr; 5942 NumAliases = 0; 5943 } 5944 bool 5945 validateAsmConstraint(const char *&Name, 5946 TargetInfo::ConstraintInfo &info) const override { 5947 // FIXME: implement 5948 switch (*Name) { 5949 case 'K': // the constant 1 5950 case 'L': // constant -1^20 .. 1^19 5951 case 'M': // constant 1-4: 5952 return true; 5953 } 5954 // No target constraints for now. 5955 return false; 5956 } 5957 const char *getClobbers() const override { 5958 // FIXME: Is this really right? 5959 return ""; 5960 } 5961 BuiltinVaListKind getBuiltinVaListKind() const override { 5962 // FIXME: implement 5963 return TargetInfo::CharPtrBuiltinVaList; 5964 } 5965 }; 5966 5967 const char * const MSP430TargetInfo::GCCRegNames[] = { 5968 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5969 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5970 }; 5971 5972 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5973 unsigned &NumNames) const { 5974 Names = GCCRegNames; 5975 NumNames = llvm::array_lengthof(GCCRegNames); 5976 } 5977 5978 // LLVM and Clang cannot be used directly to output native binaries for 5979 // target, but is used to compile C code to llvm bitcode with correct 5980 // type and alignment information. 5981 // 5982 // TCE uses the llvm bitcode as input and uses it for generating customized 5983 // target processor and program binary. TCE co-design environment is 5984 // publicly available in http://tce.cs.tut.fi 5985 5986 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5987 3, // opencl_global 5988 4, // opencl_local 5989 5, // opencl_constant 5990 // FIXME: generic has to be added to the target 5991 0, // opencl_generic 5992 0, // cuda_device 5993 0, // cuda_constant 5994 0 // cuda_shared 5995 }; 5996 5997 class TCETargetInfo : public TargetInfo{ 5998 public: 5999 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6000 TLSSupported = false; 6001 IntWidth = 32; 6002 LongWidth = LongLongWidth = 32; 6003 PointerWidth = 32; 6004 IntAlign = 32; 6005 LongAlign = LongLongAlign = 32; 6006 PointerAlign = 32; 6007 SuitableAlign = 32; 6008 SizeType = UnsignedInt; 6009 IntMaxType = SignedLong; 6010 IntPtrType = SignedInt; 6011 PtrDiffType = SignedInt; 6012 FloatWidth = 32; 6013 FloatAlign = 32; 6014 DoubleWidth = 32; 6015 DoubleAlign = 32; 6016 LongDoubleWidth = 32; 6017 LongDoubleAlign = 32; 6018 FloatFormat = &llvm::APFloat::IEEEsingle; 6019 DoubleFormat = &llvm::APFloat::IEEEsingle; 6020 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6021 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6022 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6023 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6024 UseAddrSpaceMapMangling = true; 6025 } 6026 6027 void getTargetDefines(const LangOptions &Opts, 6028 MacroBuilder &Builder) const override { 6029 DefineStd(Builder, "tce", Opts); 6030 Builder.defineMacro("__TCE__"); 6031 Builder.defineMacro("__TCE_V1__"); 6032 } 6033 bool hasFeature(StringRef Feature) const override { 6034 return Feature == "tce"; 6035 } 6036 6037 void getTargetBuiltins(const Builtin::Info *&Records, 6038 unsigned &NumRecords) const override {} 6039 const char *getClobbers() const override { 6040 return ""; 6041 } 6042 BuiltinVaListKind getBuiltinVaListKind() const override { 6043 return TargetInfo::VoidPtrBuiltinVaList; 6044 } 6045 void getGCCRegNames(const char * const *&Names, 6046 unsigned &NumNames) const override {} 6047 bool validateAsmConstraint(const char *&Name, 6048 TargetInfo::ConstraintInfo &info) const override{ 6049 return true; 6050 } 6051 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6052 unsigned &NumAliases) const override {} 6053 }; 6054 6055 class BPFTargetInfo : public TargetInfo { 6056 public: 6057 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6058 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6059 SizeType = UnsignedLong; 6060 PtrDiffType = SignedLong; 6061 IntPtrType = SignedLong; 6062 IntMaxType = SignedLong; 6063 Int64Type = SignedLong; 6064 RegParmMax = 5; 6065 if (Triple.getArch() == llvm::Triple::bpfeb) { 6066 BigEndian = true; 6067 DescriptionString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6068 } else { 6069 BigEndian = false; 6070 DescriptionString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6071 } 6072 MaxAtomicPromoteWidth = 64; 6073 MaxAtomicInlineWidth = 64; 6074 TLSSupported = false; 6075 } 6076 void getTargetDefines(const LangOptions &Opts, 6077 MacroBuilder &Builder) const override { 6078 DefineStd(Builder, "bpf", Opts); 6079 Builder.defineMacro("__BPF__"); 6080 } 6081 bool hasFeature(StringRef Feature) const override { 6082 return Feature == "bpf"; 6083 } 6084 6085 void getTargetBuiltins(const Builtin::Info *&Records, 6086 unsigned &NumRecords) const override {} 6087 const char *getClobbers() const override { 6088 return ""; 6089 } 6090 BuiltinVaListKind getBuiltinVaListKind() const override { 6091 return TargetInfo::VoidPtrBuiltinVaList; 6092 } 6093 void getGCCRegNames(const char * const *&Names, 6094 unsigned &NumNames) const override { 6095 Names = nullptr; 6096 NumNames = 0; 6097 } 6098 bool validateAsmConstraint(const char *&Name, 6099 TargetInfo::ConstraintInfo &info) const override { 6100 return true; 6101 } 6102 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6103 unsigned &NumAliases) const override { 6104 Aliases = nullptr; 6105 NumAliases = 0; 6106 } 6107 }; 6108 6109 class MipsTargetInfoBase : public TargetInfo { 6110 virtual void setDescriptionString() = 0; 6111 6112 static const Builtin::Info BuiltinInfo[]; 6113 std::string CPU; 6114 bool IsMips16; 6115 bool IsMicromips; 6116 bool IsNan2008; 6117 bool IsSingleFloat; 6118 enum MipsFloatABI { 6119 HardFloat, SoftFloat 6120 } FloatABI; 6121 enum DspRevEnum { 6122 NoDSP, DSP1, DSP2 6123 } DspRev; 6124 bool HasMSA; 6125 6126 protected: 6127 bool HasFP64; 6128 std::string ABI; 6129 6130 public: 6131 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6132 const std::string &CPUStr) 6133 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6134 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6135 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6136 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6137 } 6138 6139 bool isNaN2008Default() const { 6140 return CPU == "mips32r6" || CPU == "mips64r6"; 6141 } 6142 6143 bool isFP64Default() const { 6144 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6145 } 6146 6147 bool isNan2008() const override { 6148 return IsNan2008; 6149 } 6150 6151 StringRef getABI() const override { return ABI; } 6152 bool setCPU(const std::string &Name) override { 6153 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6154 getTriple().getArch() == llvm::Triple::mipsel; 6155 CPU = Name; 6156 return llvm::StringSwitch<bool>(Name) 6157 .Case("mips1", IsMips32) 6158 .Case("mips2", IsMips32) 6159 .Case("mips3", true) 6160 .Case("mips4", true) 6161 .Case("mips5", true) 6162 .Case("mips32", IsMips32) 6163 .Case("mips32r2", IsMips32) 6164 .Case("mips32r3", IsMips32) 6165 .Case("mips32r5", IsMips32) 6166 .Case("mips32r6", IsMips32) 6167 .Case("mips64", true) 6168 .Case("mips64r2", true) 6169 .Case("mips64r3", true) 6170 .Case("mips64r5", true) 6171 .Case("mips64r6", true) 6172 .Case("octeon", true) 6173 .Default(false); 6174 } 6175 const std::string& getCPU() const { return CPU; } 6176 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6177 if (CPU == "octeon") 6178 Features["mips64r2"] = Features["cnmips"] = true; 6179 else 6180 Features[CPU] = true; 6181 } 6182 6183 void getTargetDefines(const LangOptions &Opts, 6184 MacroBuilder &Builder) const override { 6185 Builder.defineMacro("__mips__"); 6186 Builder.defineMacro("_mips"); 6187 if (Opts.GNUMode) 6188 Builder.defineMacro("mips"); 6189 6190 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6191 6192 switch (FloatABI) { 6193 case HardFloat: 6194 Builder.defineMacro("__mips_hard_float", Twine(1)); 6195 break; 6196 case SoftFloat: 6197 Builder.defineMacro("__mips_soft_float", Twine(1)); 6198 break; 6199 } 6200 6201 if (IsSingleFloat) 6202 Builder.defineMacro("__mips_single_float", Twine(1)); 6203 6204 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6205 Builder.defineMacro("_MIPS_FPSET", 6206 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6207 6208 if (IsMips16) 6209 Builder.defineMacro("__mips16", Twine(1)); 6210 6211 if (IsMicromips) 6212 Builder.defineMacro("__mips_micromips", Twine(1)); 6213 6214 if (IsNan2008) 6215 Builder.defineMacro("__mips_nan2008", Twine(1)); 6216 6217 switch (DspRev) { 6218 default: 6219 break; 6220 case DSP1: 6221 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6222 Builder.defineMacro("__mips_dsp", Twine(1)); 6223 break; 6224 case DSP2: 6225 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6226 Builder.defineMacro("__mips_dspr2", Twine(1)); 6227 Builder.defineMacro("__mips_dsp", Twine(1)); 6228 break; 6229 } 6230 6231 if (HasMSA) 6232 Builder.defineMacro("__mips_msa", Twine(1)); 6233 6234 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6235 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6236 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6237 6238 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6239 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6240 } 6241 6242 void getTargetBuiltins(const Builtin::Info *&Records, 6243 unsigned &NumRecords) const override { 6244 Records = BuiltinInfo; 6245 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6246 } 6247 bool hasFeature(StringRef Feature) const override { 6248 return llvm::StringSwitch<bool>(Feature) 6249 .Case("mips", true) 6250 .Case("fp64", HasFP64) 6251 .Default(false); 6252 } 6253 BuiltinVaListKind getBuiltinVaListKind() const override { 6254 return TargetInfo::VoidPtrBuiltinVaList; 6255 } 6256 void getGCCRegNames(const char * const *&Names, 6257 unsigned &NumNames) const override { 6258 static const char *const GCCRegNames[] = { 6259 // CPU register names 6260 // Must match second column of GCCRegAliases 6261 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6262 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6263 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6264 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6265 // Floating point register names 6266 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6267 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6268 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6269 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6270 // Hi/lo and condition register names 6271 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6272 "$fcc5","$fcc6","$fcc7", 6273 // MSA register names 6274 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6275 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6276 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6277 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6278 // MSA control register names 6279 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6280 "$msarequest", "$msamap", "$msaunmap" 6281 }; 6282 Names = GCCRegNames; 6283 NumNames = llvm::array_lengthof(GCCRegNames); 6284 } 6285 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6286 unsigned &NumAliases) const override = 0; 6287 bool validateAsmConstraint(const char *&Name, 6288 TargetInfo::ConstraintInfo &Info) const override { 6289 switch (*Name) { 6290 default: 6291 return false; 6292 case 'r': // CPU registers. 6293 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6294 case 'y': // Equivalent to "r", backward compatibility only. 6295 case 'f': // floating-point registers. 6296 case 'c': // $25 for indirect jumps 6297 case 'l': // lo register 6298 case 'x': // hilo register pair 6299 Info.setAllowsRegister(); 6300 return true; 6301 case 'I': // Signed 16-bit constant 6302 case 'J': // Integer 0 6303 case 'K': // Unsigned 16-bit constant 6304 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6305 case 'M': // Constants not loadable via lui, addiu, or ori 6306 case 'N': // Constant -1 to -65535 6307 case 'O': // A signed 15-bit constant 6308 case 'P': // A constant between 1 go 65535 6309 return true; 6310 case 'R': // An address that can be used in a non-macro load or store 6311 Info.setAllowsMemory(); 6312 return true; 6313 case 'Z': 6314 if (Name[1] == 'C') { // An address usable by ll, and sc. 6315 Info.setAllowsMemory(); 6316 Name++; // Skip over 'Z'. 6317 return true; 6318 } 6319 return false; 6320 } 6321 } 6322 6323 std::string convertConstraint(const char *&Constraint) const override { 6324 std::string R; 6325 switch (*Constraint) { 6326 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6327 if (Constraint[1] == 'C') { 6328 R = std::string("^") + std::string(Constraint, 2); 6329 Constraint++; 6330 return R; 6331 } 6332 break; 6333 } 6334 return TargetInfo::convertConstraint(Constraint); 6335 } 6336 6337 const char *getClobbers() const override { 6338 // In GCC, $1 is not widely used in generated code (it's used only in a few 6339 // specific situations), so there is no real need for users to add it to 6340 // the clobbers list if they want to use it in their inline assembly code. 6341 // 6342 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6343 // code generation, so using it in inline assembly without adding it to the 6344 // clobbers list can cause conflicts between the inline assembly code and 6345 // the surrounding generated code. 6346 // 6347 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6348 // operands, which will conflict with the ".set at" assembler option (which 6349 // we use only for inline assembly, in order to maintain compatibility with 6350 // GCC) and will also conflict with the user's usage of $1. 6351 // 6352 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6353 // register for generated code is to automatically clobber $1 for all inline 6354 // assembly code. 6355 // 6356 // FIXME: We should automatically clobber $1 only for inline assembly code 6357 // which actually uses it. This would allow LLVM to use $1 for inline 6358 // assembly operands if the user's assembly code doesn't use it. 6359 return "~{$1}"; 6360 } 6361 6362 bool handleTargetFeatures(std::vector<std::string> &Features, 6363 DiagnosticsEngine &Diags) override { 6364 IsMips16 = false; 6365 IsMicromips = false; 6366 IsNan2008 = isNaN2008Default(); 6367 IsSingleFloat = false; 6368 FloatABI = HardFloat; 6369 DspRev = NoDSP; 6370 HasFP64 = isFP64Default(); 6371 6372 for (std::vector<std::string>::iterator it = Features.begin(), 6373 ie = Features.end(); it != ie; ++it) { 6374 if (*it == "+single-float") 6375 IsSingleFloat = true; 6376 else if (*it == "+soft-float") 6377 FloatABI = SoftFloat; 6378 else if (*it == "+mips16") 6379 IsMips16 = true; 6380 else if (*it == "+micromips") 6381 IsMicromips = true; 6382 else if (*it == "+dsp") 6383 DspRev = std::max(DspRev, DSP1); 6384 else if (*it == "+dspr2") 6385 DspRev = std::max(DspRev, DSP2); 6386 else if (*it == "+msa") 6387 HasMSA = true; 6388 else if (*it == "+fp64") 6389 HasFP64 = true; 6390 else if (*it == "-fp64") 6391 HasFP64 = false; 6392 else if (*it == "+nan2008") 6393 IsNan2008 = true; 6394 else if (*it == "-nan2008") 6395 IsNan2008 = false; 6396 } 6397 6398 setDescriptionString(); 6399 6400 return true; 6401 } 6402 6403 int getEHDataRegisterNumber(unsigned RegNo) const override { 6404 if (RegNo == 0) return 4; 6405 if (RegNo == 1) return 5; 6406 return -1; 6407 } 6408 6409 bool isCLZForZeroUndef() const override { return false; } 6410 }; 6411 6412 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6413 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6414 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6415 ALL_LANGUAGES }, 6416 #include "clang/Basic/BuiltinsMips.def" 6417 }; 6418 6419 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6420 public: 6421 Mips32TargetInfoBase(const llvm::Triple &Triple) 6422 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6423 SizeType = UnsignedInt; 6424 PtrDiffType = SignedInt; 6425 Int64Type = SignedLongLong; 6426 IntMaxType = Int64Type; 6427 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6428 } 6429 bool setABI(const std::string &Name) override { 6430 if (Name == "o32" || Name == "eabi") { 6431 ABI = Name; 6432 return true; 6433 } 6434 return false; 6435 } 6436 void getTargetDefines(const LangOptions &Opts, 6437 MacroBuilder &Builder) const override { 6438 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6439 6440 Builder.defineMacro("__mips", "32"); 6441 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6442 6443 const std::string& CPUStr = getCPU(); 6444 if (CPUStr == "mips32") 6445 Builder.defineMacro("__mips_isa_rev", "1"); 6446 else if (CPUStr == "mips32r2") 6447 Builder.defineMacro("__mips_isa_rev", "2"); 6448 else if (CPUStr == "mips32r3") 6449 Builder.defineMacro("__mips_isa_rev", "3"); 6450 else if (CPUStr == "mips32r5") 6451 Builder.defineMacro("__mips_isa_rev", "5"); 6452 else if (CPUStr == "mips32r6") 6453 Builder.defineMacro("__mips_isa_rev", "6"); 6454 6455 if (ABI == "o32") { 6456 Builder.defineMacro("__mips_o32"); 6457 Builder.defineMacro("_ABIO32", "1"); 6458 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6459 } 6460 else if (ABI == "eabi") 6461 Builder.defineMacro("__mips_eabi"); 6462 else 6463 llvm_unreachable("Invalid ABI for Mips32."); 6464 } 6465 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6466 unsigned &NumAliases) const override { 6467 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6468 { { "at" }, "$1" }, 6469 { { "v0" }, "$2" }, 6470 { { "v1" }, "$3" }, 6471 { { "a0" }, "$4" }, 6472 { { "a1" }, "$5" }, 6473 { { "a2" }, "$6" }, 6474 { { "a3" }, "$7" }, 6475 { { "t0" }, "$8" }, 6476 { { "t1" }, "$9" }, 6477 { { "t2" }, "$10" }, 6478 { { "t3" }, "$11" }, 6479 { { "t4" }, "$12" }, 6480 { { "t5" }, "$13" }, 6481 { { "t6" }, "$14" }, 6482 { { "t7" }, "$15" }, 6483 { { "s0" }, "$16" }, 6484 { { "s1" }, "$17" }, 6485 { { "s2" }, "$18" }, 6486 { { "s3" }, "$19" }, 6487 { { "s4" }, "$20" }, 6488 { { "s5" }, "$21" }, 6489 { { "s6" }, "$22" }, 6490 { { "s7" }, "$23" }, 6491 { { "t8" }, "$24" }, 6492 { { "t9" }, "$25" }, 6493 { { "k0" }, "$26" }, 6494 { { "k1" }, "$27" }, 6495 { { "gp" }, "$28" }, 6496 { { "sp","$sp" }, "$29" }, 6497 { { "fp","$fp" }, "$30" }, 6498 { { "ra" }, "$31" } 6499 }; 6500 Aliases = GCCRegAliases; 6501 NumAliases = llvm::array_lengthof(GCCRegAliases); 6502 } 6503 }; 6504 6505 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6506 void setDescriptionString() override { 6507 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6508 } 6509 6510 public: 6511 Mips32EBTargetInfo(const llvm::Triple &Triple) 6512 : Mips32TargetInfoBase(Triple) { 6513 } 6514 void getTargetDefines(const LangOptions &Opts, 6515 MacroBuilder &Builder) const override { 6516 DefineStd(Builder, "MIPSEB", Opts); 6517 Builder.defineMacro("_MIPSEB"); 6518 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6519 } 6520 }; 6521 6522 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6523 void setDescriptionString() override { 6524 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6525 } 6526 6527 public: 6528 Mips32ELTargetInfo(const llvm::Triple &Triple) 6529 : Mips32TargetInfoBase(Triple) { 6530 BigEndian = false; 6531 } 6532 void getTargetDefines(const LangOptions &Opts, 6533 MacroBuilder &Builder) const override { 6534 DefineStd(Builder, "MIPSEL", Opts); 6535 Builder.defineMacro("_MIPSEL"); 6536 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6537 } 6538 }; 6539 6540 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6541 public: 6542 Mips64TargetInfoBase(const llvm::Triple &Triple) 6543 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6544 LongDoubleWidth = LongDoubleAlign = 128; 6545 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6546 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6547 LongDoubleWidth = LongDoubleAlign = 64; 6548 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6549 } 6550 setN64ABITypes(); 6551 SuitableAlign = 128; 6552 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6553 } 6554 6555 void setN64ABITypes() { 6556 LongWidth = LongAlign = 64; 6557 PointerWidth = PointerAlign = 64; 6558 SizeType = UnsignedLong; 6559 PtrDiffType = SignedLong; 6560 Int64Type = SignedLong; 6561 IntMaxType = Int64Type; 6562 } 6563 6564 void setN32ABITypes() { 6565 LongWidth = LongAlign = 32; 6566 PointerWidth = PointerAlign = 32; 6567 SizeType = UnsignedInt; 6568 PtrDiffType = SignedInt; 6569 Int64Type = SignedLongLong; 6570 IntMaxType = Int64Type; 6571 } 6572 6573 bool setABI(const std::string &Name) override { 6574 if (Name == "n32") { 6575 setN32ABITypes(); 6576 ABI = Name; 6577 return true; 6578 } 6579 if (Name == "n64") { 6580 setN64ABITypes(); 6581 ABI = Name; 6582 return true; 6583 } 6584 return false; 6585 } 6586 6587 void getTargetDefines(const LangOptions &Opts, 6588 MacroBuilder &Builder) const override { 6589 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6590 6591 Builder.defineMacro("__mips", "64"); 6592 Builder.defineMacro("__mips64"); 6593 Builder.defineMacro("__mips64__"); 6594 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6595 6596 const std::string& CPUStr = getCPU(); 6597 if (CPUStr == "mips64") 6598 Builder.defineMacro("__mips_isa_rev", "1"); 6599 else if (CPUStr == "mips64r2") 6600 Builder.defineMacro("__mips_isa_rev", "2"); 6601 else if (CPUStr == "mips64r3") 6602 Builder.defineMacro("__mips_isa_rev", "3"); 6603 else if (CPUStr == "mips64r5") 6604 Builder.defineMacro("__mips_isa_rev", "5"); 6605 else if (CPUStr == "mips64r6") 6606 Builder.defineMacro("__mips_isa_rev", "6"); 6607 6608 if (ABI == "n32") { 6609 Builder.defineMacro("__mips_n32"); 6610 Builder.defineMacro("_ABIN32", "2"); 6611 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6612 } 6613 else if (ABI == "n64") { 6614 Builder.defineMacro("__mips_n64"); 6615 Builder.defineMacro("_ABI64", "3"); 6616 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6617 } 6618 else 6619 llvm_unreachable("Invalid ABI for Mips64."); 6620 } 6621 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6622 unsigned &NumAliases) const override { 6623 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6624 { { "at" }, "$1" }, 6625 { { "v0" }, "$2" }, 6626 { { "v1" }, "$3" }, 6627 { { "a0" }, "$4" }, 6628 { { "a1" }, "$5" }, 6629 { { "a2" }, "$6" }, 6630 { { "a3" }, "$7" }, 6631 { { "a4" }, "$8" }, 6632 { { "a5" }, "$9" }, 6633 { { "a6" }, "$10" }, 6634 { { "a7" }, "$11" }, 6635 { { "t0" }, "$12" }, 6636 { { "t1" }, "$13" }, 6637 { { "t2" }, "$14" }, 6638 { { "t3" }, "$15" }, 6639 { { "s0" }, "$16" }, 6640 { { "s1" }, "$17" }, 6641 { { "s2" }, "$18" }, 6642 { { "s3" }, "$19" }, 6643 { { "s4" }, "$20" }, 6644 { { "s5" }, "$21" }, 6645 { { "s6" }, "$22" }, 6646 { { "s7" }, "$23" }, 6647 { { "t8" }, "$24" }, 6648 { { "t9" }, "$25" }, 6649 { { "k0" }, "$26" }, 6650 { { "k1" }, "$27" }, 6651 { { "gp" }, "$28" }, 6652 { { "sp","$sp" }, "$29" }, 6653 { { "fp","$fp" }, "$30" }, 6654 { { "ra" }, "$31" } 6655 }; 6656 Aliases = GCCRegAliases; 6657 NumAliases = llvm::array_lengthof(GCCRegAliases); 6658 } 6659 6660 bool hasInt128Type() const override { return true; } 6661 }; 6662 6663 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6664 void setDescriptionString() override { 6665 if (ABI == "n32") 6666 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6667 else 6668 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6669 6670 } 6671 6672 public: 6673 Mips64EBTargetInfo(const llvm::Triple &Triple) 6674 : Mips64TargetInfoBase(Triple) {} 6675 void getTargetDefines(const LangOptions &Opts, 6676 MacroBuilder &Builder) const override { 6677 DefineStd(Builder, "MIPSEB", Opts); 6678 Builder.defineMacro("_MIPSEB"); 6679 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6680 } 6681 }; 6682 6683 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6684 void setDescriptionString() override { 6685 if (ABI == "n32") 6686 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6687 else 6688 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6689 } 6690 public: 6691 Mips64ELTargetInfo(const llvm::Triple &Triple) 6692 : Mips64TargetInfoBase(Triple) { 6693 // Default ABI is n64. 6694 BigEndian = false; 6695 } 6696 void getTargetDefines(const LangOptions &Opts, 6697 MacroBuilder &Builder) const override { 6698 DefineStd(Builder, "MIPSEL", Opts); 6699 Builder.defineMacro("_MIPSEL"); 6700 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6701 } 6702 }; 6703 6704 class PNaClTargetInfo : public TargetInfo { 6705 public: 6706 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6707 BigEndian = false; 6708 this->UserLabelPrefix = ""; 6709 this->LongAlign = 32; 6710 this->LongWidth = 32; 6711 this->PointerAlign = 32; 6712 this->PointerWidth = 32; 6713 this->IntMaxType = TargetInfo::SignedLongLong; 6714 this->Int64Type = TargetInfo::SignedLongLong; 6715 this->DoubleAlign = 64; 6716 this->LongDoubleWidth = 64; 6717 this->LongDoubleAlign = 64; 6718 this->SizeType = TargetInfo::UnsignedInt; 6719 this->PtrDiffType = TargetInfo::SignedInt; 6720 this->IntPtrType = TargetInfo::SignedInt; 6721 this->RegParmMax = 0; // Disallow regparm 6722 } 6723 6724 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6725 } 6726 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6727 Builder.defineMacro("__le32__"); 6728 Builder.defineMacro("__pnacl__"); 6729 } 6730 void getTargetDefines(const LangOptions &Opts, 6731 MacroBuilder &Builder) const override { 6732 getArchDefines(Opts, Builder); 6733 } 6734 bool hasFeature(StringRef Feature) const override { 6735 return Feature == "pnacl"; 6736 } 6737 void getTargetBuiltins(const Builtin::Info *&Records, 6738 unsigned &NumRecords) const override { 6739 } 6740 BuiltinVaListKind getBuiltinVaListKind() const override { 6741 return TargetInfo::PNaClABIBuiltinVaList; 6742 } 6743 void getGCCRegNames(const char * const *&Names, 6744 unsigned &NumNames) const override; 6745 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6746 unsigned &NumAliases) const override; 6747 bool validateAsmConstraint(const char *&Name, 6748 TargetInfo::ConstraintInfo &Info) const override { 6749 return false; 6750 } 6751 6752 const char *getClobbers() const override { 6753 return ""; 6754 } 6755 }; 6756 6757 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6758 unsigned &NumNames) const { 6759 Names = nullptr; 6760 NumNames = 0; 6761 } 6762 6763 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6764 unsigned &NumAliases) const { 6765 Aliases = nullptr; 6766 NumAliases = 0; 6767 } 6768 6769 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6770 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6771 public: 6772 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6773 Mips32ELTargetInfo(Triple) { 6774 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 0; 6775 } 6776 6777 BuiltinVaListKind getBuiltinVaListKind() const override { 6778 return TargetInfo::PNaClABIBuiltinVaList; 6779 } 6780 }; 6781 6782 class Le64TargetInfo : public TargetInfo { 6783 static const Builtin::Info BuiltinInfo[]; 6784 6785 public: 6786 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6787 BigEndian = false; 6788 NoAsmVariants = true; 6789 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6790 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6791 DescriptionString = 6792 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6793 } 6794 6795 void getTargetDefines(const LangOptions &Opts, 6796 MacroBuilder &Builder) const override { 6797 DefineStd(Builder, "unix", Opts); 6798 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6799 Builder.defineMacro("__ELF__"); 6800 } 6801 void getTargetBuiltins(const Builtin::Info *&Records, 6802 unsigned &NumRecords) const override { 6803 Records = BuiltinInfo; 6804 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6805 } 6806 BuiltinVaListKind getBuiltinVaListKind() const override { 6807 return TargetInfo::PNaClABIBuiltinVaList; 6808 } 6809 const char *getClobbers() const override { return ""; } 6810 void getGCCRegNames(const char *const *&Names, 6811 unsigned &NumNames) const override { 6812 Names = nullptr; 6813 NumNames = 0; 6814 } 6815 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6816 unsigned &NumAliases) const override { 6817 Aliases = nullptr; 6818 NumAliases = 0; 6819 } 6820 bool validateAsmConstraint(const char *&Name, 6821 TargetInfo::ConstraintInfo &Info) const override { 6822 return false; 6823 } 6824 6825 bool hasProtectedVisibility() const override { return false; } 6826 }; 6827 } // end anonymous namespace. 6828 6829 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6830 #define BUILTIN(ID, TYPE, ATTRS) \ 6831 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6832 #include "clang/Basic/BuiltinsLe64.def" 6833 }; 6834 6835 namespace { 6836 static const unsigned SPIRAddrSpaceMap[] = { 6837 1, // opencl_global 6838 3, // opencl_local 6839 2, // opencl_constant 6840 4, // opencl_generic 6841 0, // cuda_device 6842 0, // cuda_constant 6843 0 // cuda_shared 6844 }; 6845 class SPIRTargetInfo : public TargetInfo { 6846 public: 6847 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6848 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6849 "SPIR target must use unknown OS"); 6850 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6851 "SPIR target must use unknown environment type"); 6852 BigEndian = false; 6853 TLSSupported = false; 6854 LongWidth = LongAlign = 64; 6855 AddrSpaceMap = &SPIRAddrSpaceMap; 6856 UseAddrSpaceMapMangling = true; 6857 // Define available target features 6858 // These must be defined in sorted order! 6859 NoAsmVariants = true; 6860 } 6861 void getTargetDefines(const LangOptions &Opts, 6862 MacroBuilder &Builder) const override { 6863 DefineStd(Builder, "SPIR", Opts); 6864 } 6865 bool hasFeature(StringRef Feature) const override { 6866 return Feature == "spir"; 6867 } 6868 6869 void getTargetBuiltins(const Builtin::Info *&Records, 6870 unsigned &NumRecords) const override {} 6871 const char *getClobbers() const override { 6872 return ""; 6873 } 6874 void getGCCRegNames(const char * const *&Names, 6875 unsigned &NumNames) const override {} 6876 bool 6877 validateAsmConstraint(const char *&Name, 6878 TargetInfo::ConstraintInfo &info) const override { 6879 return true; 6880 } 6881 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6882 unsigned &NumAliases) const override {} 6883 BuiltinVaListKind getBuiltinVaListKind() const override { 6884 return TargetInfo::VoidPtrBuiltinVaList; 6885 } 6886 6887 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6888 return (CC == CC_SpirFunction || 6889 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6890 } 6891 6892 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6893 return CC_SpirFunction; 6894 } 6895 }; 6896 6897 6898 class SPIR32TargetInfo : public SPIRTargetInfo { 6899 public: 6900 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6901 PointerWidth = PointerAlign = 32; 6902 SizeType = TargetInfo::UnsignedInt; 6903 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6904 DescriptionString 6905 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6906 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6907 } 6908 void getTargetDefines(const LangOptions &Opts, 6909 MacroBuilder &Builder) const override { 6910 DefineStd(Builder, "SPIR32", Opts); 6911 } 6912 }; 6913 6914 class SPIR64TargetInfo : public SPIRTargetInfo { 6915 public: 6916 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6917 PointerWidth = PointerAlign = 64; 6918 SizeType = TargetInfo::UnsignedLong; 6919 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6920 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6921 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6922 } 6923 void getTargetDefines(const LangOptions &Opts, 6924 MacroBuilder &Builder) const override { 6925 DefineStd(Builder, "SPIR64", Opts); 6926 } 6927 }; 6928 6929 class XCoreTargetInfo : public TargetInfo { 6930 static const Builtin::Info BuiltinInfo[]; 6931 public: 6932 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6933 BigEndian = false; 6934 NoAsmVariants = true; 6935 LongLongAlign = 32; 6936 SuitableAlign = 32; 6937 DoubleAlign = LongDoubleAlign = 32; 6938 SizeType = UnsignedInt; 6939 PtrDiffType = SignedInt; 6940 IntPtrType = SignedInt; 6941 WCharType = UnsignedChar; 6942 WIntType = UnsignedInt; 6943 UseZeroLengthBitfieldAlignment = true; 6944 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6945 "-f64:32-a:0:32-n32"; 6946 } 6947 void getTargetDefines(const LangOptions &Opts, 6948 MacroBuilder &Builder) const override { 6949 Builder.defineMacro("__XS1B__"); 6950 } 6951 void getTargetBuiltins(const Builtin::Info *&Records, 6952 unsigned &NumRecords) const override { 6953 Records = BuiltinInfo; 6954 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6955 } 6956 BuiltinVaListKind getBuiltinVaListKind() const override { 6957 return TargetInfo::VoidPtrBuiltinVaList; 6958 } 6959 const char *getClobbers() const override { 6960 return ""; 6961 } 6962 void getGCCRegNames(const char * const *&Names, 6963 unsigned &NumNames) const override { 6964 static const char * const GCCRegNames[] = { 6965 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6966 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6967 }; 6968 Names = GCCRegNames; 6969 NumNames = llvm::array_lengthof(GCCRegNames); 6970 } 6971 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6972 unsigned &NumAliases) const override { 6973 Aliases = nullptr; 6974 NumAliases = 0; 6975 } 6976 bool validateAsmConstraint(const char *&Name, 6977 TargetInfo::ConstraintInfo &Info) const override { 6978 return false; 6979 } 6980 int getEHDataRegisterNumber(unsigned RegNo) const override { 6981 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6982 return (RegNo < 2)? RegNo : -1; 6983 } 6984 }; 6985 6986 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6987 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6988 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6989 ALL_LANGUAGES }, 6990 #include "clang/Basic/BuiltinsXCore.def" 6991 }; 6992 } // end anonymous namespace. 6993 6994 namespace { 6995 // x86_32 Android target 6996 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6997 public: 6998 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6999 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7000 SuitableAlign = 32; 7001 LongDoubleWidth = 64; 7002 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7003 } 7004 }; 7005 } // end anonymous namespace 7006 7007 namespace { 7008 // x86_64 Android target 7009 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7010 public: 7011 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7012 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7013 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7014 } 7015 }; 7016 } // end anonymous namespace 7017 7018 7019 //===----------------------------------------------------------------------===// 7020 // Driver code 7021 //===----------------------------------------------------------------------===// 7022 7023 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7024 llvm::Triple::OSType os = Triple.getOS(); 7025 7026 switch (Triple.getArch()) { 7027 default: 7028 return nullptr; 7029 7030 case llvm::Triple::xcore: 7031 return new XCoreTargetInfo(Triple); 7032 7033 case llvm::Triple::hexagon: 7034 return new HexagonTargetInfo(Triple); 7035 7036 case llvm::Triple::aarch64: 7037 if (Triple.isOSDarwin()) 7038 return new DarwinAArch64TargetInfo(Triple); 7039 7040 switch (os) { 7041 case llvm::Triple::FreeBSD: 7042 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7043 case llvm::Triple::Linux: 7044 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7045 case llvm::Triple::NetBSD: 7046 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7047 default: 7048 return new AArch64leTargetInfo(Triple); 7049 } 7050 7051 case llvm::Triple::aarch64_be: 7052 switch (os) { 7053 case llvm::Triple::FreeBSD: 7054 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7055 case llvm::Triple::Linux: 7056 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7057 case llvm::Triple::NetBSD: 7058 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7059 default: 7060 return new AArch64beTargetInfo(Triple); 7061 } 7062 7063 case llvm::Triple::arm: 7064 case llvm::Triple::thumb: 7065 if (Triple.isOSBinFormatMachO()) 7066 return new DarwinARMTargetInfo(Triple); 7067 7068 switch (os) { 7069 case llvm::Triple::Linux: 7070 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7071 case llvm::Triple::FreeBSD: 7072 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7073 case llvm::Triple::NetBSD: 7074 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7075 case llvm::Triple::OpenBSD: 7076 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7077 case llvm::Triple::Bitrig: 7078 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7079 case llvm::Triple::RTEMS: 7080 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7081 case llvm::Triple::NaCl: 7082 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7083 case llvm::Triple::Win32: 7084 switch (Triple.getEnvironment()) { 7085 default: 7086 return new ARMleTargetInfo(Triple); 7087 case llvm::Triple::Cygnus: 7088 return new CygwinARMTargetInfo(Triple); 7089 case llvm::Triple::GNU: 7090 return new MinGWARMTargetInfo(Triple); 7091 case llvm::Triple::Itanium: 7092 return new ItaniumWindowsARMleTargetInfo(Triple); 7093 case llvm::Triple::MSVC: 7094 return new MicrosoftARMleTargetInfo(Triple); 7095 } 7096 default: 7097 return new ARMleTargetInfo(Triple); 7098 } 7099 7100 case llvm::Triple::armeb: 7101 case llvm::Triple::thumbeb: 7102 if (Triple.isOSDarwin()) 7103 return new DarwinARMTargetInfo(Triple); 7104 7105 switch (os) { 7106 case llvm::Triple::Linux: 7107 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7108 case llvm::Triple::FreeBSD: 7109 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7110 case llvm::Triple::NetBSD: 7111 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7112 case llvm::Triple::OpenBSD: 7113 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7114 case llvm::Triple::Bitrig: 7115 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7116 case llvm::Triple::RTEMS: 7117 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7118 case llvm::Triple::NaCl: 7119 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7120 default: 7121 return new ARMbeTargetInfo(Triple); 7122 } 7123 7124 case llvm::Triple::bpfeb: 7125 case llvm::Triple::bpfel: 7126 return new BPFTargetInfo(Triple); 7127 7128 case llvm::Triple::msp430: 7129 return new MSP430TargetInfo(Triple); 7130 7131 case llvm::Triple::mips: 7132 switch (os) { 7133 case llvm::Triple::Linux: 7134 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7135 case llvm::Triple::RTEMS: 7136 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7137 case llvm::Triple::FreeBSD: 7138 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7139 case llvm::Triple::NetBSD: 7140 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7141 default: 7142 return new Mips32EBTargetInfo(Triple); 7143 } 7144 7145 case llvm::Triple::mipsel: 7146 switch (os) { 7147 case llvm::Triple::Linux: 7148 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7149 case llvm::Triple::RTEMS: 7150 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7151 case llvm::Triple::FreeBSD: 7152 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7153 case llvm::Triple::NetBSD: 7154 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7155 case llvm::Triple::NaCl: 7156 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7157 default: 7158 return new Mips32ELTargetInfo(Triple); 7159 } 7160 7161 case llvm::Triple::mips64: 7162 switch (os) { 7163 case llvm::Triple::Linux: 7164 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7165 case llvm::Triple::RTEMS: 7166 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7167 case llvm::Triple::FreeBSD: 7168 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7169 case llvm::Triple::NetBSD: 7170 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7171 case llvm::Triple::OpenBSD: 7172 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7173 default: 7174 return new Mips64EBTargetInfo(Triple); 7175 } 7176 7177 case llvm::Triple::mips64el: 7178 switch (os) { 7179 case llvm::Triple::Linux: 7180 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7181 case llvm::Triple::RTEMS: 7182 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7183 case llvm::Triple::FreeBSD: 7184 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7185 case llvm::Triple::NetBSD: 7186 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7187 case llvm::Triple::OpenBSD: 7188 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7189 default: 7190 return new Mips64ELTargetInfo(Triple); 7191 } 7192 7193 case llvm::Triple::le32: 7194 switch (os) { 7195 case llvm::Triple::NaCl: 7196 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7197 default: 7198 return nullptr; 7199 } 7200 7201 case llvm::Triple::le64: 7202 return new Le64TargetInfo(Triple); 7203 7204 case llvm::Triple::ppc: 7205 if (Triple.isOSDarwin()) 7206 return new DarwinPPC32TargetInfo(Triple); 7207 switch (os) { 7208 case llvm::Triple::Linux: 7209 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7210 case llvm::Triple::FreeBSD: 7211 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7212 case llvm::Triple::NetBSD: 7213 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7214 case llvm::Triple::OpenBSD: 7215 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7216 case llvm::Triple::RTEMS: 7217 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7218 default: 7219 return new PPC32TargetInfo(Triple); 7220 } 7221 7222 case llvm::Triple::ppc64: 7223 if (Triple.isOSDarwin()) 7224 return new DarwinPPC64TargetInfo(Triple); 7225 switch (os) { 7226 case llvm::Triple::Linux: 7227 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7228 case llvm::Triple::Lv2: 7229 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7230 case llvm::Triple::FreeBSD: 7231 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7232 case llvm::Triple::NetBSD: 7233 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7234 default: 7235 return new PPC64TargetInfo(Triple); 7236 } 7237 7238 case llvm::Triple::ppc64le: 7239 switch (os) { 7240 case llvm::Triple::Linux: 7241 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7242 case llvm::Triple::NetBSD: 7243 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7244 default: 7245 return new PPC64TargetInfo(Triple); 7246 } 7247 7248 case llvm::Triple::nvptx: 7249 return new NVPTX32TargetInfo(Triple); 7250 case llvm::Triple::nvptx64: 7251 return new NVPTX64TargetInfo(Triple); 7252 7253 case llvm::Triple::amdgcn: 7254 case llvm::Triple::r600: 7255 return new AMDGPUTargetInfo(Triple); 7256 7257 case llvm::Triple::sparc: 7258 switch (os) { 7259 case llvm::Triple::Linux: 7260 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7261 case llvm::Triple::Solaris: 7262 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7263 case llvm::Triple::NetBSD: 7264 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7265 case llvm::Triple::OpenBSD: 7266 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7267 case llvm::Triple::RTEMS: 7268 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7269 default: 7270 return new SparcV8TargetInfo(Triple); 7271 } 7272 7273 // The 'sparcel' architecture copies all the above cases except for Solaris. 7274 case llvm::Triple::sparcel: 7275 switch (os) { 7276 case llvm::Triple::Linux: 7277 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7278 case llvm::Triple::NetBSD: 7279 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7280 case llvm::Triple::OpenBSD: 7281 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7282 case llvm::Triple::RTEMS: 7283 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7284 default: 7285 return new SparcV8elTargetInfo(Triple); 7286 } 7287 7288 case llvm::Triple::sparcv9: 7289 switch (os) { 7290 case llvm::Triple::Linux: 7291 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7292 case llvm::Triple::Solaris: 7293 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7294 case llvm::Triple::NetBSD: 7295 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7296 case llvm::Triple::OpenBSD: 7297 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7298 case llvm::Triple::FreeBSD: 7299 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7300 default: 7301 return new SparcV9TargetInfo(Triple); 7302 } 7303 7304 case llvm::Triple::systemz: 7305 switch (os) { 7306 case llvm::Triple::Linux: 7307 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7308 default: 7309 return new SystemZTargetInfo(Triple); 7310 } 7311 7312 case llvm::Triple::tce: 7313 return new TCETargetInfo(Triple); 7314 7315 case llvm::Triple::x86: 7316 if (Triple.isOSDarwin()) 7317 return new DarwinI386TargetInfo(Triple); 7318 7319 switch (os) { 7320 case llvm::Triple::CloudABI: 7321 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7322 case llvm::Triple::Linux: { 7323 switch (Triple.getEnvironment()) { 7324 default: 7325 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7326 case llvm::Triple::Android: 7327 return new AndroidX86_32TargetInfo(Triple); 7328 } 7329 } 7330 case llvm::Triple::DragonFly: 7331 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7332 case llvm::Triple::NetBSD: 7333 return new NetBSDI386TargetInfo(Triple); 7334 case llvm::Triple::OpenBSD: 7335 return new OpenBSDI386TargetInfo(Triple); 7336 case llvm::Triple::Bitrig: 7337 return new BitrigI386TargetInfo(Triple); 7338 case llvm::Triple::FreeBSD: 7339 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7340 case llvm::Triple::KFreeBSD: 7341 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7342 case llvm::Triple::Minix: 7343 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7344 case llvm::Triple::Solaris: 7345 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7346 case llvm::Triple::Win32: { 7347 switch (Triple.getEnvironment()) { 7348 default: 7349 return new X86_32TargetInfo(Triple); 7350 case llvm::Triple::Cygnus: 7351 return new CygwinX86_32TargetInfo(Triple); 7352 case llvm::Triple::GNU: 7353 return new MinGWX86_32TargetInfo(Triple); 7354 case llvm::Triple::Itanium: 7355 case llvm::Triple::MSVC: 7356 return new MicrosoftX86_32TargetInfo(Triple); 7357 } 7358 } 7359 case llvm::Triple::Haiku: 7360 return new HaikuX86_32TargetInfo(Triple); 7361 case llvm::Triple::RTEMS: 7362 return new RTEMSX86_32TargetInfo(Triple); 7363 case llvm::Triple::NaCl: 7364 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7365 default: 7366 return new X86_32TargetInfo(Triple); 7367 } 7368 7369 case llvm::Triple::x86_64: 7370 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7371 return new DarwinX86_64TargetInfo(Triple); 7372 7373 switch (os) { 7374 case llvm::Triple::CloudABI: 7375 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7376 case llvm::Triple::Linux: { 7377 switch (Triple.getEnvironment()) { 7378 default: 7379 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7380 case llvm::Triple::Android: 7381 return new AndroidX86_64TargetInfo(Triple); 7382 } 7383 } 7384 case llvm::Triple::DragonFly: 7385 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7386 case llvm::Triple::NetBSD: 7387 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7388 case llvm::Triple::OpenBSD: 7389 return new OpenBSDX86_64TargetInfo(Triple); 7390 case llvm::Triple::Bitrig: 7391 return new BitrigX86_64TargetInfo(Triple); 7392 case llvm::Triple::FreeBSD: 7393 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7394 case llvm::Triple::KFreeBSD: 7395 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7396 case llvm::Triple::Solaris: 7397 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7398 case llvm::Triple::Win32: { 7399 switch (Triple.getEnvironment()) { 7400 default: 7401 return new X86_64TargetInfo(Triple); 7402 case llvm::Triple::GNU: 7403 return new MinGWX86_64TargetInfo(Triple); 7404 case llvm::Triple::MSVC: 7405 return new MicrosoftX86_64TargetInfo(Triple); 7406 } 7407 } 7408 case llvm::Triple::NaCl: 7409 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7410 case llvm::Triple::PS4: 7411 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7412 default: 7413 return new X86_64TargetInfo(Triple); 7414 } 7415 7416 case llvm::Triple::spir: { 7417 if (Triple.getOS() != llvm::Triple::UnknownOS || 7418 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7419 return nullptr; 7420 return new SPIR32TargetInfo(Triple); 7421 } 7422 case llvm::Triple::spir64: { 7423 if (Triple.getOS() != llvm::Triple::UnknownOS || 7424 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7425 return nullptr; 7426 return new SPIR64TargetInfo(Triple); 7427 } 7428 } 7429 } 7430 7431 /// CreateTargetInfo - Return the target info object for the specified target 7432 /// triple. 7433 TargetInfo * 7434 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7435 const std::shared_ptr<TargetOptions> &Opts) { 7436 llvm::Triple Triple(Opts->Triple); 7437 7438 // Construct the target 7439 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7440 if (!Target) { 7441 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7442 return nullptr; 7443 } 7444 Target->TargetOpts = Opts; 7445 7446 // Set the target CPU if specified. 7447 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7448 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7449 return nullptr; 7450 } 7451 7452 // Set the target ABI if specified. 7453 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7454 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7455 return nullptr; 7456 } 7457 7458 // Set the fp math unit. 7459 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7460 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7461 return nullptr; 7462 } 7463 7464 // Compute the default target features, we need the target to handle this 7465 // because features may have dependencies on one another. 7466 llvm::StringMap<bool> Features; 7467 Target->getDefaultFeatures(Features); 7468 7469 // Apply the user specified deltas. 7470 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7471 I < N; ++I) { 7472 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7473 // Apply the feature via the target. 7474 bool Enabled = Name[0] == '+'; 7475 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7476 } 7477 7478 // Add the features to the compile options. 7479 // 7480 // FIXME: If we are completely confident that we have the right set, we only 7481 // need to pass the minuses. 7482 Opts->Features.clear(); 7483 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7484 ie = Features.end(); it != ie; ++it) 7485 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7486 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7487 return nullptr; 7488 7489 return Target.release(); 7490 } 7491