1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 // FreeBSD Target 300 template<typename Target> 301 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 302 protected: 303 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 304 MacroBuilder &Builder) const override { 305 // FreeBSD defines; list based off of gcc output 306 307 unsigned Release = Triple.getOSMajorVersion(); 308 if (Release == 0U) 309 Release = 8; 310 311 Builder.defineMacro("__FreeBSD__", Twine(Release)); 312 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 313 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 314 DefineStd(Builder, "unix", Opts); 315 Builder.defineMacro("__ELF__"); 316 317 // On FreeBSD, wchar_t contains the number of the code point as 318 // used by the character set of the locale. These character sets are 319 // not necessarily a superset of ASCII. 320 // 321 // FIXME: This is wrong; the macro refers to the numerical values 322 // of wchar_t *literals*, which are not locale-dependent. However, 323 // FreeBSD systems apparently depend on us getting this wrong, and 324 // setting this to 1 is conforming even if all the basic source 325 // character literals have the same encoding as char and wchar_t. 326 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 327 } 328 public: 329 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 330 this->UserLabelPrefix = ""; 331 332 switch (Triple.getArch()) { 333 default: 334 case llvm::Triple::x86: 335 case llvm::Triple::x86_64: 336 this->MCountName = ".mcount"; 337 break; 338 case llvm::Triple::mips: 339 case llvm::Triple::mipsel: 340 case llvm::Triple::ppc: 341 case llvm::Triple::ppc64: 342 case llvm::Triple::ppc64le: 343 this->MCountName = "_mcount"; 344 break; 345 case llvm::Triple::arm: 346 this->MCountName = "__mcount"; 347 break; 348 } 349 } 350 }; 351 352 // GNU/kFreeBSD Target 353 template<typename Target> 354 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 355 protected: 356 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 357 MacroBuilder &Builder) const override { 358 // GNU/kFreeBSD defines; list based off of gcc output 359 360 DefineStd(Builder, "unix", Opts); 361 Builder.defineMacro("__FreeBSD_kernel__"); 362 Builder.defineMacro("__GLIBC__"); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 if (Opts.CPlusPlus) 367 Builder.defineMacro("_GNU_SOURCE"); 368 } 369 public: 370 KFreeBSDTargetInfo(const llvm::Triple &Triple) 371 : OSTargetInfo<Target>(Triple) { 372 this->UserLabelPrefix = ""; 373 } 374 }; 375 376 // Minix Target 377 template<typename Target> 378 class MinixTargetInfo : public OSTargetInfo<Target> { 379 protected: 380 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 381 MacroBuilder &Builder) const override { 382 // Minix defines 383 384 Builder.defineMacro("__minix", "3"); 385 Builder.defineMacro("_EM_WSIZE", "4"); 386 Builder.defineMacro("_EM_PSIZE", "4"); 387 Builder.defineMacro("_EM_SSIZE", "2"); 388 Builder.defineMacro("_EM_LSIZE", "4"); 389 Builder.defineMacro("_EM_FSIZE", "4"); 390 Builder.defineMacro("_EM_DSIZE", "8"); 391 Builder.defineMacro("__ELF__"); 392 DefineStd(Builder, "unix", Opts); 393 } 394 public: 395 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 396 this->UserLabelPrefix = ""; 397 } 398 }; 399 400 // Linux target 401 template<typename Target> 402 class LinuxTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const override { 406 // Linux defines; list based off of gcc output 407 DefineStd(Builder, "unix", Opts); 408 DefineStd(Builder, "linux", Opts); 409 Builder.defineMacro("__gnu_linux__"); 410 Builder.defineMacro("__ELF__"); 411 if (Triple.isAndroid()) { 412 Builder.defineMacro("__ANDROID__", "1"); 413 unsigned Maj, Min, Rev; 414 Triple.getEnvironmentVersion(Maj, Min, Rev); 415 this->PlatformName = "android"; 416 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 417 } 418 if (Opts.POSIXThreads) 419 Builder.defineMacro("_REENTRANT"); 420 if (Opts.CPlusPlus) 421 Builder.defineMacro("_GNU_SOURCE"); 422 } 423 public: 424 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 425 this->UserLabelPrefix = ""; 426 this->WIntType = TargetInfo::UnsignedInt; 427 428 switch (Triple.getArch()) { 429 default: 430 break; 431 case llvm::Triple::ppc: 432 case llvm::Triple::ppc64: 433 case llvm::Triple::ppc64le: 434 this->MCountName = "_mcount"; 435 break; 436 } 437 } 438 439 const char *getStaticInitSectionSpecifier() const override { 440 return ".text.startup"; 441 } 442 }; 443 444 // NetBSD Target 445 template<typename Target> 446 class NetBSDTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // NetBSD defines; list based off of gcc output 451 Builder.defineMacro("__NetBSD__"); 452 Builder.defineMacro("__unix__"); 453 Builder.defineMacro("__ELF__"); 454 if (Opts.POSIXThreads) 455 Builder.defineMacro("_POSIX_THREADS"); 456 457 switch (Triple.getArch()) { 458 default: 459 break; 460 case llvm::Triple::arm: 461 case llvm::Triple::armeb: 462 case llvm::Triple::thumb: 463 case llvm::Triple::thumbeb: 464 Builder.defineMacro("__ARM_DWARF_EH__"); 465 break; 466 } 467 } 468 public: 469 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->MCountName = "_mcount"; 472 } 473 }; 474 475 // OpenBSD Target 476 template<typename Target> 477 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 478 protected: 479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 480 MacroBuilder &Builder) const override { 481 // OpenBSD defines; list based off of gcc output 482 483 Builder.defineMacro("__OpenBSD__"); 484 DefineStd(Builder, "unix", Opts); 485 Builder.defineMacro("__ELF__"); 486 if (Opts.POSIXThreads) 487 Builder.defineMacro("_REENTRANT"); 488 } 489 public: 490 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->TLSSupported = false; 493 494 switch (Triple.getArch()) { 495 default: 496 case llvm::Triple::x86: 497 case llvm::Triple::x86_64: 498 case llvm::Triple::arm: 499 case llvm::Triple::sparc: 500 this->MCountName = "__mcount"; 501 break; 502 case llvm::Triple::mips64: 503 case llvm::Triple::mips64el: 504 case llvm::Triple::ppc: 505 case llvm::Triple::sparcv9: 506 this->MCountName = "_mcount"; 507 break; 508 } 509 } 510 }; 511 512 // Bitrig Target 513 template<typename Target> 514 class BitrigTargetInfo : public OSTargetInfo<Target> { 515 protected: 516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 517 MacroBuilder &Builder) const override { 518 // Bitrig defines; list based off of gcc output 519 520 Builder.defineMacro("__Bitrig__"); 521 DefineStd(Builder, "unix", Opts); 522 Builder.defineMacro("__ELF__"); 523 if (Opts.POSIXThreads) 524 Builder.defineMacro("_REENTRANT"); 525 526 switch (Triple.getArch()) { 527 default: 528 break; 529 case llvm::Triple::arm: 530 case llvm::Triple::armeb: 531 case llvm::Triple::thumb: 532 case llvm::Triple::thumbeb: 533 Builder.defineMacro("__ARM_DWARF_EH__"); 534 break; 535 } 536 } 537 public: 538 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 539 this->UserLabelPrefix = ""; 540 this->MCountName = "__mcount"; 541 } 542 }; 543 544 // PSP Target 545 template<typename Target> 546 class PSPTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 // PSP defines; list based on the output of the pspdev gcc toolchain. 551 Builder.defineMacro("PSP"); 552 Builder.defineMacro("_PSP"); 553 Builder.defineMacro("__psp__"); 554 Builder.defineMacro("__ELF__"); 555 } 556 public: 557 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 } 560 }; 561 562 // PS3 PPU Target 563 template<typename Target> 564 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 565 protected: 566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 567 MacroBuilder &Builder) const override { 568 // PS3 PPU defines. 569 Builder.defineMacro("__PPC__"); 570 Builder.defineMacro("__PPU__"); 571 Builder.defineMacro("__CELLOS_LV2__"); 572 Builder.defineMacro("__ELF__"); 573 Builder.defineMacro("__LP32__"); 574 Builder.defineMacro("_ARCH_PPC64"); 575 Builder.defineMacro("__powerpc64__"); 576 } 577 public: 578 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 579 this->UserLabelPrefix = ""; 580 this->LongWidth = this->LongAlign = 32; 581 this->PointerWidth = this->PointerAlign = 32; 582 this->IntMaxType = TargetInfo::SignedLongLong; 583 this->Int64Type = TargetInfo::SignedLongLong; 584 this->SizeType = TargetInfo::UnsignedInt; 585 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 586 } 587 }; 588 589 template <typename Target> 590 class PS4OSTargetInfo : public OSTargetInfo<Target> { 591 protected: 592 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 593 MacroBuilder &Builder) const override { 594 Builder.defineMacro("__FreeBSD__", "9"); 595 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 596 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 597 DefineStd(Builder, "unix", Opts); 598 Builder.defineMacro("__ELF__"); 599 Builder.defineMacro("__PS4__"); 600 } 601 public: 602 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 603 this->WCharType = this->UnsignedShort; 604 605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 606 this->MaxTLSAlign = 256; 607 this->UserLabelPrefix = ""; 608 609 // On PS4, do not honor explicit bit field alignment, 610 // as in "__attribute__((aligned(2))) int b : 1;". 611 this->UseExplicitBitFieldAlignment = false; 612 613 switch (Triple.getArch()) { 614 default: 615 case llvm::Triple::x86_64: 616 this->MCountName = ".mcount"; 617 break; 618 } 619 } 620 }; 621 622 // Solaris target 623 template<typename Target> 624 class SolarisTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 DefineStd(Builder, "sun", Opts); 629 DefineStd(Builder, "unix", Opts); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__svr4__"); 632 Builder.defineMacro("__SVR4"); 633 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 634 // newer, but to 500 for everything else. feature_test.h has a check to 635 // ensure that you are not using C99 with an old version of X/Open or C89 636 // with a new version. 637 if (Opts.C99) 638 Builder.defineMacro("_XOPEN_SOURCE", "600"); 639 else 640 Builder.defineMacro("_XOPEN_SOURCE", "500"); 641 if (Opts.CPlusPlus) 642 Builder.defineMacro("__C99FEATURES__"); 643 Builder.defineMacro("_LARGEFILE_SOURCE"); 644 Builder.defineMacro("_LARGEFILE64_SOURCE"); 645 Builder.defineMacro("__EXTENSIONS__"); 646 Builder.defineMacro("_REENTRANT"); 647 } 648 public: 649 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 650 this->UserLabelPrefix = ""; 651 this->WCharType = this->SignedInt; 652 // FIXME: WIntType should be SignedLong 653 } 654 }; 655 656 // Windows target 657 template<typename Target> 658 class WindowsTargetInfo : public OSTargetInfo<Target> { 659 protected: 660 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 661 MacroBuilder &Builder) const override { 662 Builder.defineMacro("_WIN32"); 663 } 664 void getVisualStudioDefines(const LangOptions &Opts, 665 MacroBuilder &Builder) const { 666 if (Opts.CPlusPlus) { 667 if (Opts.RTTIData) 668 Builder.defineMacro("_CPPRTTI"); 669 670 if (Opts.CXXExceptions) 671 Builder.defineMacro("_CPPUNWIND"); 672 } 673 674 if (Opts.Bool) 675 Builder.defineMacro("__BOOL_DEFINED"); 676 677 if (!Opts.CharIsSigned) 678 Builder.defineMacro("_CHAR_UNSIGNED"); 679 680 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 681 // but it works for now. 682 if (Opts.POSIXThreads) 683 Builder.defineMacro("_MT"); 684 685 if (Opts.MSCompatibilityVersion) { 686 Builder.defineMacro("_MSC_VER", 687 Twine(Opts.MSCompatibilityVersion / 100000)); 688 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 689 // FIXME We cannot encode the revision information into 32-bits 690 Builder.defineMacro("_MSC_BUILD", Twine(1)); 691 692 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 693 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 694 } 695 696 if (Opts.MicrosoftExt) { 697 Builder.defineMacro("_MSC_EXTENSIONS"); 698 699 if (Opts.CPlusPlus11) { 700 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 701 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 702 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 703 } 704 } 705 706 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 707 } 708 709 public: 710 WindowsTargetInfo(const llvm::Triple &Triple) 711 : OSTargetInfo<Target>(Triple) {} 712 }; 713 714 template <typename Target> 715 class NaClTargetInfo : public OSTargetInfo<Target> { 716 protected: 717 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 718 MacroBuilder &Builder) const override { 719 if (Opts.POSIXThreads) 720 Builder.defineMacro("_REENTRANT"); 721 if (Opts.CPlusPlus) 722 Builder.defineMacro("_GNU_SOURCE"); 723 724 DefineStd(Builder, "unix", Opts); 725 Builder.defineMacro("__ELF__"); 726 Builder.defineMacro("__native_client__"); 727 } 728 729 public: 730 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 731 this->UserLabelPrefix = ""; 732 this->LongAlign = 32; 733 this->LongWidth = 32; 734 this->PointerAlign = 32; 735 this->PointerWidth = 32; 736 this->IntMaxType = TargetInfo::SignedLongLong; 737 this->Int64Type = TargetInfo::SignedLongLong; 738 this->DoubleAlign = 64; 739 this->LongDoubleWidth = 64; 740 this->LongDoubleAlign = 64; 741 this->LongLongWidth = 64; 742 this->LongLongAlign = 64; 743 this->SizeType = TargetInfo::UnsignedInt; 744 this->PtrDiffType = TargetInfo::SignedInt; 745 this->IntPtrType = TargetInfo::SignedInt; 746 // RegParmMax is inherited from the underlying architecture 747 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 748 if (Triple.getArch() == llvm::Triple::arm) { 749 // Handled in ARM's setABI(). 750 } else if (Triple.getArch() == llvm::Triple::x86) { 751 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 752 } else if (Triple.getArch() == llvm::Triple::x86_64) { 753 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 754 } else if (Triple.getArch() == llvm::Triple::mipsel) { 755 // Handled on mips' setDataLayoutString. 756 } else { 757 assert(Triple.getArch() == llvm::Triple::le32); 758 this->DataLayoutString = "e-p:32:32-i64:64"; 759 } 760 } 761 }; 762 763 // WebAssembly target 764 template <typename Target> 765 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 766 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 767 MacroBuilder &Builder) const final { 768 // A common platform macro. 769 if (Opts.POSIXThreads) 770 Builder.defineMacro("_REENTRANT"); 771 // Follow g++ convention and predefine _GNU_SOURCE for C++. 772 if (Opts.CPlusPlus) 773 Builder.defineMacro("_GNU_SOURCE"); 774 } 775 776 // As an optimization, group static init code together in a section. 777 const char *getStaticInitSectionSpecifier() const final { 778 return ".text.__startup"; 779 } 780 781 public: 782 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 783 : OSTargetInfo<Target>(Triple) { 784 this->MCountName = "__mcount"; 785 this->UserLabelPrefix = ""; 786 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 787 } 788 }; 789 790 //===----------------------------------------------------------------------===// 791 // Specific target implementations. 792 //===----------------------------------------------------------------------===// 793 794 // PPC abstract base class 795 class PPCTargetInfo : public TargetInfo { 796 static const Builtin::Info BuiltinInfo[]; 797 static const char * const GCCRegNames[]; 798 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 799 std::string CPU; 800 801 // Target cpu features. 802 bool HasVSX; 803 bool HasP8Vector; 804 bool HasP8Crypto; 805 bool HasDirectMove; 806 bool HasQPX; 807 bool HasHTM; 808 bool HasBPERMD; 809 bool HasExtDiv; 810 811 protected: 812 std::string ABI; 813 814 public: 815 PPCTargetInfo(const llvm::Triple &Triple) 816 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 817 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 818 HasBPERMD(false), HasExtDiv(false) { 819 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 820 SimdDefaultAlign = 128; 821 LongDoubleWidth = LongDoubleAlign = 128; 822 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 823 } 824 825 /// \brief Flags for architecture specific defines. 826 typedef enum { 827 ArchDefineNone = 0, 828 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 829 ArchDefinePpcgr = 1 << 1, 830 ArchDefinePpcsq = 1 << 2, 831 ArchDefine440 = 1 << 3, 832 ArchDefine603 = 1 << 4, 833 ArchDefine604 = 1 << 5, 834 ArchDefinePwr4 = 1 << 6, 835 ArchDefinePwr5 = 1 << 7, 836 ArchDefinePwr5x = 1 << 8, 837 ArchDefinePwr6 = 1 << 9, 838 ArchDefinePwr6x = 1 << 10, 839 ArchDefinePwr7 = 1 << 11, 840 ArchDefinePwr8 = 1 << 12, 841 ArchDefineA2 = 1 << 13, 842 ArchDefineA2q = 1 << 14 843 } ArchDefineTypes; 844 845 // Note: GCC recognizes the following additional cpus: 846 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 847 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 848 // titan, rs64. 849 bool setCPU(const std::string &Name) override { 850 bool CPUKnown = llvm::StringSwitch<bool>(Name) 851 .Case("generic", true) 852 .Case("440", true) 853 .Case("450", true) 854 .Case("601", true) 855 .Case("602", true) 856 .Case("603", true) 857 .Case("603e", true) 858 .Case("603ev", true) 859 .Case("604", true) 860 .Case("604e", true) 861 .Case("620", true) 862 .Case("630", true) 863 .Case("g3", true) 864 .Case("7400", true) 865 .Case("g4", true) 866 .Case("7450", true) 867 .Case("g4+", true) 868 .Case("750", true) 869 .Case("970", true) 870 .Case("g5", true) 871 .Case("a2", true) 872 .Case("a2q", true) 873 .Case("e500mc", true) 874 .Case("e5500", true) 875 .Case("power3", true) 876 .Case("pwr3", true) 877 .Case("power4", true) 878 .Case("pwr4", true) 879 .Case("power5", true) 880 .Case("pwr5", true) 881 .Case("power5x", true) 882 .Case("pwr5x", true) 883 .Case("power6", true) 884 .Case("pwr6", true) 885 .Case("power6x", true) 886 .Case("pwr6x", true) 887 .Case("power7", true) 888 .Case("pwr7", true) 889 .Case("power8", true) 890 .Case("pwr8", true) 891 .Case("powerpc", true) 892 .Case("ppc", true) 893 .Case("powerpc64", true) 894 .Case("ppc64", true) 895 .Case("powerpc64le", true) 896 .Case("ppc64le", true) 897 .Default(false); 898 899 if (CPUKnown) 900 CPU = Name; 901 902 return CPUKnown; 903 } 904 905 906 StringRef getABI() const override { return ABI; } 907 908 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 909 return llvm::makeArrayRef(BuiltinInfo, 910 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 911 } 912 913 bool isCLZForZeroUndef() const override { return false; } 914 915 void getTargetDefines(const LangOptions &Opts, 916 MacroBuilder &Builder) const override; 917 918 bool 919 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 920 StringRef CPU, 921 const std::vector<std::string> &FeaturesVec) const override; 922 923 bool handleTargetFeatures(std::vector<std::string> &Features, 924 DiagnosticsEngine &Diags) override; 925 bool hasFeature(StringRef Feature) const override; 926 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 927 bool Enabled) const override; 928 929 ArrayRef<const char *> getGCCRegNames() const override; 930 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 931 bool validateAsmConstraint(const char *&Name, 932 TargetInfo::ConstraintInfo &Info) const override { 933 switch (*Name) { 934 default: return false; 935 case 'O': // Zero 936 break; 937 case 'b': // Base register 938 case 'f': // Floating point register 939 Info.setAllowsRegister(); 940 break; 941 // FIXME: The following are added to allow parsing. 942 // I just took a guess at what the actions should be. 943 // Also, is more specific checking needed? I.e. specific registers? 944 case 'd': // Floating point register (containing 64-bit value) 945 case 'v': // Altivec vector register 946 Info.setAllowsRegister(); 947 break; 948 case 'w': 949 switch (Name[1]) { 950 case 'd':// VSX vector register to hold vector double data 951 case 'f':// VSX vector register to hold vector float data 952 case 's':// VSX vector register to hold scalar float data 953 case 'a':// Any VSX register 954 case 'c':// An individual CR bit 955 break; 956 default: 957 return false; 958 } 959 Info.setAllowsRegister(); 960 Name++; // Skip over 'w'. 961 break; 962 case 'h': // `MQ', `CTR', or `LINK' register 963 case 'q': // `MQ' register 964 case 'c': // `CTR' register 965 case 'l': // `LINK' register 966 case 'x': // `CR' register (condition register) number 0 967 case 'y': // `CR' register (condition register) 968 case 'z': // `XER[CA]' carry bit (part of the XER register) 969 Info.setAllowsRegister(); 970 break; 971 case 'I': // Signed 16-bit constant 972 case 'J': // Unsigned 16-bit constant shifted left 16 bits 973 // (use `L' instead for SImode constants) 974 case 'K': // Unsigned 16-bit constant 975 case 'L': // Signed 16-bit constant shifted left 16 bits 976 case 'M': // Constant larger than 31 977 case 'N': // Exact power of 2 978 case 'P': // Constant whose negation is a signed 16-bit constant 979 case 'G': // Floating point constant that can be loaded into a 980 // register with one instruction per word 981 case 'H': // Integer/Floating point constant that can be loaded 982 // into a register using three instructions 983 break; 984 case 'm': // Memory operand. Note that on PowerPC targets, m can 985 // include addresses that update the base register. It 986 // is therefore only safe to use `m' in an asm statement 987 // if that asm statement accesses the operand exactly once. 988 // The asm statement must also use `%U<opno>' as a 989 // placeholder for the "update" flag in the corresponding 990 // load or store instruction. For example: 991 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 992 // is correct but: 993 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 994 // is not. Use es rather than m if you don't want the base 995 // register to be updated. 996 case 'e': 997 if (Name[1] != 's') 998 return false; 999 // es: A "stable" memory operand; that is, one which does not 1000 // include any automodification of the base register. Unlike 1001 // `m', this constraint can be used in asm statements that 1002 // might access the operand several times, or that might not 1003 // access it at all. 1004 Info.setAllowsMemory(); 1005 Name++; // Skip over 'e'. 1006 break; 1007 case 'Q': // Memory operand that is an offset from a register (it is 1008 // usually better to use `m' or `es' in asm statements) 1009 case 'Z': // Memory operand that is an indexed or indirect from a 1010 // register (it is usually better to use `m' or `es' in 1011 // asm statements) 1012 Info.setAllowsMemory(); 1013 Info.setAllowsRegister(); 1014 break; 1015 case 'R': // AIX TOC entry 1016 case 'a': // Address operand that is an indexed or indirect from a 1017 // register (`p' is preferable for asm statements) 1018 case 'S': // Constant suitable as a 64-bit mask operand 1019 case 'T': // Constant suitable as a 32-bit mask operand 1020 case 'U': // System V Release 4 small data area reference 1021 case 't': // AND masks that can be performed by two rldic{l, r} 1022 // instructions 1023 case 'W': // Vector constant that does not require memory 1024 case 'j': // Vector constant that is all zeros. 1025 break; 1026 // End FIXME. 1027 } 1028 return true; 1029 } 1030 std::string convertConstraint(const char *&Constraint) const override { 1031 std::string R; 1032 switch (*Constraint) { 1033 case 'e': 1034 case 'w': 1035 // Two-character constraint; add "^" hint for later parsing. 1036 R = std::string("^") + std::string(Constraint, 2); 1037 Constraint++; 1038 break; 1039 default: 1040 return TargetInfo::convertConstraint(Constraint); 1041 } 1042 return R; 1043 } 1044 const char *getClobbers() const override { 1045 return ""; 1046 } 1047 int getEHDataRegisterNumber(unsigned RegNo) const override { 1048 if (RegNo == 0) return 3; 1049 if (RegNo == 1) return 4; 1050 return -1; 1051 } 1052 1053 bool hasSjLjLowering() const override { 1054 return true; 1055 } 1056 1057 bool useFloat128ManglingForLongDouble() const override { 1058 return LongDoubleWidth == 128 && 1059 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1060 getTriple().isOSBinFormatELF(); 1061 } 1062 }; 1063 1064 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1065 #define BUILTIN(ID, TYPE, ATTRS) \ 1066 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1068 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1069 #include "clang/Basic/BuiltinsPPC.def" 1070 }; 1071 1072 /// handleTargetFeatures - Perform initialization based on the user 1073 /// configured set of features. 1074 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1075 DiagnosticsEngine &Diags) { 1076 for (const auto &Feature : Features) { 1077 if (Feature == "+vsx") { 1078 HasVSX = true; 1079 } else if (Feature == "+bpermd") { 1080 HasBPERMD = true; 1081 } else if (Feature == "+extdiv") { 1082 HasExtDiv = true; 1083 } else if (Feature == "+power8-vector") { 1084 HasP8Vector = true; 1085 } else if (Feature == "+crypto") { 1086 HasP8Crypto = true; 1087 } else if (Feature == "+direct-move") { 1088 HasDirectMove = true; 1089 } else if (Feature == "+qpx") { 1090 HasQPX = true; 1091 } else if (Feature == "+htm") { 1092 HasHTM = true; 1093 } 1094 // TODO: Finish this list and add an assert that we've handled them 1095 // all. 1096 } 1097 1098 return true; 1099 } 1100 1101 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1102 /// #defines that are not tied to a specific subtarget. 1103 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1104 MacroBuilder &Builder) const { 1105 // Target identification. 1106 Builder.defineMacro("__ppc__"); 1107 Builder.defineMacro("__PPC__"); 1108 Builder.defineMacro("_ARCH_PPC"); 1109 Builder.defineMacro("__powerpc__"); 1110 Builder.defineMacro("__POWERPC__"); 1111 if (PointerWidth == 64) { 1112 Builder.defineMacro("_ARCH_PPC64"); 1113 Builder.defineMacro("__powerpc64__"); 1114 Builder.defineMacro("__ppc64__"); 1115 Builder.defineMacro("__PPC64__"); 1116 } 1117 1118 // Target properties. 1119 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1120 Builder.defineMacro("_LITTLE_ENDIAN"); 1121 } else { 1122 if (getTriple().getOS() != llvm::Triple::NetBSD && 1123 getTriple().getOS() != llvm::Triple::OpenBSD) 1124 Builder.defineMacro("_BIG_ENDIAN"); 1125 } 1126 1127 // ABI options. 1128 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1129 Builder.defineMacro("_CALL_ELF", "1"); 1130 if (ABI == "elfv2") 1131 Builder.defineMacro("_CALL_ELF", "2"); 1132 1133 // Subtarget options. 1134 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1135 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1136 1137 // FIXME: Should be controlled by command line option. 1138 if (LongDoubleWidth == 128) 1139 Builder.defineMacro("__LONG_DOUBLE_128__"); 1140 1141 if (Opts.AltiVec) { 1142 Builder.defineMacro("__VEC__", "10206"); 1143 Builder.defineMacro("__ALTIVEC__"); 1144 } 1145 1146 // CPU identification. 1147 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1148 .Case("440", ArchDefineName) 1149 .Case("450", ArchDefineName | ArchDefine440) 1150 .Case("601", ArchDefineName) 1151 .Case("602", ArchDefineName | ArchDefinePpcgr) 1152 .Case("603", ArchDefineName | ArchDefinePpcgr) 1153 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1154 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1155 .Case("604", ArchDefineName | ArchDefinePpcgr) 1156 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1157 .Case("620", ArchDefineName | ArchDefinePpcgr) 1158 .Case("630", ArchDefineName | ArchDefinePpcgr) 1159 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1160 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1161 .Case("750", ArchDefineName | ArchDefinePpcgr) 1162 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1163 | ArchDefinePpcsq) 1164 .Case("a2", ArchDefineA2) 1165 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1166 .Case("pwr3", ArchDefinePpcgr) 1167 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1169 | ArchDefinePpcsq) 1170 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1171 | ArchDefinePpcgr | ArchDefinePpcsq) 1172 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1175 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1176 | ArchDefinePpcsq) 1177 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1178 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1179 | ArchDefinePpcgr | ArchDefinePpcsq) 1180 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1181 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1182 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("power3", ArchDefinePpcgr) 1184 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1186 | ArchDefinePpcsq) 1187 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1188 | ArchDefinePpcgr | ArchDefinePpcsq) 1189 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1190 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1191 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1192 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1193 | ArchDefinePpcsq) 1194 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1195 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1196 | ArchDefinePpcgr | ArchDefinePpcsq) 1197 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1198 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1199 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Default(ArchDefineNone); 1201 1202 if (defs & ArchDefineName) 1203 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1204 if (defs & ArchDefinePpcgr) 1205 Builder.defineMacro("_ARCH_PPCGR"); 1206 if (defs & ArchDefinePpcsq) 1207 Builder.defineMacro("_ARCH_PPCSQ"); 1208 if (defs & ArchDefine440) 1209 Builder.defineMacro("_ARCH_440"); 1210 if (defs & ArchDefine603) 1211 Builder.defineMacro("_ARCH_603"); 1212 if (defs & ArchDefine604) 1213 Builder.defineMacro("_ARCH_604"); 1214 if (defs & ArchDefinePwr4) 1215 Builder.defineMacro("_ARCH_PWR4"); 1216 if (defs & ArchDefinePwr5) 1217 Builder.defineMacro("_ARCH_PWR5"); 1218 if (defs & ArchDefinePwr5x) 1219 Builder.defineMacro("_ARCH_PWR5X"); 1220 if (defs & ArchDefinePwr6) 1221 Builder.defineMacro("_ARCH_PWR6"); 1222 if (defs & ArchDefinePwr6x) 1223 Builder.defineMacro("_ARCH_PWR6X"); 1224 if (defs & ArchDefinePwr7) 1225 Builder.defineMacro("_ARCH_PWR7"); 1226 if (defs & ArchDefinePwr8) 1227 Builder.defineMacro("_ARCH_PWR8"); 1228 if (defs & ArchDefineA2) 1229 Builder.defineMacro("_ARCH_A2"); 1230 if (defs & ArchDefineA2q) { 1231 Builder.defineMacro("_ARCH_A2Q"); 1232 Builder.defineMacro("_ARCH_QP"); 1233 } 1234 1235 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1236 Builder.defineMacro("__bg__"); 1237 Builder.defineMacro("__THW_BLUEGENE__"); 1238 Builder.defineMacro("__bgq__"); 1239 Builder.defineMacro("__TOS_BGQ__"); 1240 } 1241 1242 if (HasVSX) 1243 Builder.defineMacro("__VSX__"); 1244 if (HasP8Vector) 1245 Builder.defineMacro("__POWER8_VECTOR__"); 1246 if (HasP8Crypto) 1247 Builder.defineMacro("__CRYPTO__"); 1248 if (HasHTM) 1249 Builder.defineMacro("__HTM__"); 1250 1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1254 if (PointerWidth == 64) 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1256 1257 // FIXME: The following are not yet generated here by Clang, but are 1258 // generated by GCC: 1259 // 1260 // _SOFT_FLOAT_ 1261 // __RECIP_PRECISION__ 1262 // __APPLE_ALTIVEC__ 1263 // __RECIP__ 1264 // __RECIPF__ 1265 // __RSQRTE__ 1266 // __RSQRTEF__ 1267 // _SOFT_DOUBLE_ 1268 // __NO_LWSYNC__ 1269 // __HAVE_BSWAP__ 1270 // __LONGDOUBLE128 1271 // __CMODEL_MEDIUM__ 1272 // __CMODEL_LARGE__ 1273 // _CALL_SYSV 1274 // _CALL_DARWIN 1275 // __NO_FPRS__ 1276 } 1277 1278 // Handle explicit options being passed to the compiler here: if we've 1279 // explicitly turned off vsx and turned on power8-vector or direct-move then 1280 // go ahead and error since the customer has expressed a somewhat incompatible 1281 // set of options. 1282 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1283 const std::vector<std::string> &FeaturesVec) { 1284 1285 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1286 FeaturesVec.end()) { 1287 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1288 FeaturesVec.end()) { 1289 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1290 << "-mno-vsx"; 1291 return false; 1292 } 1293 1294 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1295 FeaturesVec.end()) { 1296 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1297 << "-mno-vsx"; 1298 return false; 1299 } 1300 } 1301 1302 return true; 1303 } 1304 1305 bool PPCTargetInfo::initFeatureMap( 1306 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1307 const std::vector<std::string> &FeaturesVec) const { 1308 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1309 .Case("7400", true) 1310 .Case("g4", true) 1311 .Case("7450", true) 1312 .Case("g4+", true) 1313 .Case("970", true) 1314 .Case("g5", true) 1315 .Case("pwr6", true) 1316 .Case("pwr7", true) 1317 .Case("pwr8", true) 1318 .Case("ppc64", true) 1319 .Case("ppc64le", true) 1320 .Default(false); 1321 1322 Features["qpx"] = (CPU == "a2q"); 1323 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1324 .Case("ppc64le", true) 1325 .Case("pwr8", true) 1326 .Default(false); 1327 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1328 .Case("ppc64le", true) 1329 .Case("pwr8", true) 1330 .Default(false); 1331 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1332 .Case("ppc64le", true) 1333 .Case("pwr8", true) 1334 .Case("pwr7", true) 1335 .Default(false); 1336 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1337 .Case("ppc64le", true) 1338 .Case("pwr8", true) 1339 .Case("pwr7", true) 1340 .Default(false); 1341 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1342 .Case("ppc64le", true) 1343 .Case("pwr8", true) 1344 .Default(false); 1345 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1346 .Case("ppc64le", true) 1347 .Case("pwr8", true) 1348 .Case("pwr7", true) 1349 .Default(false); 1350 1351 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1352 return false; 1353 1354 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1355 } 1356 1357 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1358 return llvm::StringSwitch<bool>(Feature) 1359 .Case("powerpc", true) 1360 .Case("vsx", HasVSX) 1361 .Case("power8-vector", HasP8Vector) 1362 .Case("crypto", HasP8Crypto) 1363 .Case("direct-move", HasDirectMove) 1364 .Case("qpx", HasQPX) 1365 .Case("htm", HasHTM) 1366 .Case("bpermd", HasBPERMD) 1367 .Case("extdiv", HasExtDiv) 1368 .Default(false); 1369 } 1370 1371 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1372 StringRef Name, bool Enabled) const { 1373 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1374 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1375 // incompatible options. 1376 if (Enabled) { 1377 if (Name == "vsx") { 1378 Features[Name] = true; 1379 } else if (Name == "direct-move") { 1380 Features[Name] = Features["vsx"] = true; 1381 } else if (Name == "power8-vector") { 1382 Features[Name] = Features["vsx"] = true; 1383 } else { 1384 Features[Name] = true; 1385 } 1386 } else { 1387 if (Name == "vsx") { 1388 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1389 false; 1390 } else { 1391 Features[Name] = false; 1392 } 1393 } 1394 } 1395 1396 const char * const PPCTargetInfo::GCCRegNames[] = { 1397 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1398 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1399 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1400 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1405 "mq", "lr", "ctr", "ap", 1406 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1407 "xer", 1408 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1409 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1410 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1411 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1412 "vrsave", "vscr", 1413 "spe_acc", "spefscr", 1414 "sfp" 1415 }; 1416 1417 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1418 return llvm::makeArrayRef(GCCRegNames); 1419 } 1420 1421 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1422 // While some of these aliases do map to different registers 1423 // they still share the same register name. 1424 { { "0" }, "r0" }, 1425 { { "1"}, "r1" }, 1426 { { "2" }, "r2" }, 1427 { { "3" }, "r3" }, 1428 { { "4" }, "r4" }, 1429 { { "5" }, "r5" }, 1430 { { "6" }, "r6" }, 1431 { { "7" }, "r7" }, 1432 { { "8" }, "r8" }, 1433 { { "9" }, "r9" }, 1434 { { "10" }, "r10" }, 1435 { { "11" }, "r11" }, 1436 { { "12" }, "r12" }, 1437 { { "13" }, "r13" }, 1438 { { "14" }, "r14" }, 1439 { { "15" }, "r15" }, 1440 { { "16" }, "r16" }, 1441 { { "17" }, "r17" }, 1442 { { "18" }, "r18" }, 1443 { { "19" }, "r19" }, 1444 { { "20" }, "r20" }, 1445 { { "21" }, "r21" }, 1446 { { "22" }, "r22" }, 1447 { { "23" }, "r23" }, 1448 { { "24" }, "r24" }, 1449 { { "25" }, "r25" }, 1450 { { "26" }, "r26" }, 1451 { { "27" }, "r27" }, 1452 { { "28" }, "r28" }, 1453 { { "29" }, "r29" }, 1454 { { "30" }, "r30" }, 1455 { { "31" }, "r31" }, 1456 { { "fr0" }, "f0" }, 1457 { { "fr1" }, "f1" }, 1458 { { "fr2" }, "f2" }, 1459 { { "fr3" }, "f3" }, 1460 { { "fr4" }, "f4" }, 1461 { { "fr5" }, "f5" }, 1462 { { "fr6" }, "f6" }, 1463 { { "fr7" }, "f7" }, 1464 { { "fr8" }, "f8" }, 1465 { { "fr9" }, "f9" }, 1466 { { "fr10" }, "f10" }, 1467 { { "fr11" }, "f11" }, 1468 { { "fr12" }, "f12" }, 1469 { { "fr13" }, "f13" }, 1470 { { "fr14" }, "f14" }, 1471 { { "fr15" }, "f15" }, 1472 { { "fr16" }, "f16" }, 1473 { { "fr17" }, "f17" }, 1474 { { "fr18" }, "f18" }, 1475 { { "fr19" }, "f19" }, 1476 { { "fr20" }, "f20" }, 1477 { { "fr21" }, "f21" }, 1478 { { "fr22" }, "f22" }, 1479 { { "fr23" }, "f23" }, 1480 { { "fr24" }, "f24" }, 1481 { { "fr25" }, "f25" }, 1482 { { "fr26" }, "f26" }, 1483 { { "fr27" }, "f27" }, 1484 { { "fr28" }, "f28" }, 1485 { { "fr29" }, "f29" }, 1486 { { "fr30" }, "f30" }, 1487 { { "fr31" }, "f31" }, 1488 { { "cc" }, "cr0" }, 1489 }; 1490 1491 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1492 return llvm::makeArrayRef(GCCRegAliases); 1493 } 1494 1495 class PPC32TargetInfo : public PPCTargetInfo { 1496 public: 1497 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1498 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1499 1500 switch (getTriple().getOS()) { 1501 case llvm::Triple::Linux: 1502 case llvm::Triple::FreeBSD: 1503 case llvm::Triple::NetBSD: 1504 SizeType = UnsignedInt; 1505 PtrDiffType = SignedInt; 1506 IntPtrType = SignedInt; 1507 break; 1508 default: 1509 break; 1510 } 1511 1512 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1513 LongDoubleWidth = LongDoubleAlign = 64; 1514 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1515 } 1516 1517 // PPC32 supports atomics up to 4 bytes. 1518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1519 } 1520 1521 BuiltinVaListKind getBuiltinVaListKind() const override { 1522 // This is the ELF definition, and is overridden by the Darwin sub-target 1523 return TargetInfo::PowerABIBuiltinVaList; 1524 } 1525 }; 1526 1527 // Note: ABI differences may eventually require us to have a separate 1528 // TargetInfo for little endian. 1529 class PPC64TargetInfo : public PPCTargetInfo { 1530 public: 1531 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1532 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1533 IntMaxType = SignedLong; 1534 Int64Type = SignedLong; 1535 1536 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1537 DataLayoutString = "e-m:e-i64:64-n32:64"; 1538 ABI = "elfv2"; 1539 } else { 1540 DataLayoutString = "E-m:e-i64:64-n32:64"; 1541 ABI = "elfv1"; 1542 } 1543 1544 switch (getTriple().getOS()) { 1545 case llvm::Triple::FreeBSD: 1546 LongDoubleWidth = LongDoubleAlign = 64; 1547 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1548 break; 1549 case llvm::Triple::NetBSD: 1550 IntMaxType = SignedLongLong; 1551 Int64Type = SignedLongLong; 1552 break; 1553 default: 1554 break; 1555 } 1556 1557 // PPC64 supports atomics up to 8 bytes. 1558 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1559 } 1560 BuiltinVaListKind getBuiltinVaListKind() const override { 1561 return TargetInfo::CharPtrBuiltinVaList; 1562 } 1563 // PPC64 Linux-specific ABI options. 1564 bool setABI(const std::string &Name) override { 1565 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1566 ABI = Name; 1567 return true; 1568 } 1569 return false; 1570 } 1571 }; 1572 1573 class DarwinPPC32TargetInfo : 1574 public DarwinTargetInfo<PPC32TargetInfo> { 1575 public: 1576 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1577 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1578 HasAlignMac68kSupport = true; 1579 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1580 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1581 LongLongAlign = 32; 1582 SuitableAlign = 128; 1583 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1584 } 1585 BuiltinVaListKind getBuiltinVaListKind() const override { 1586 return TargetInfo::CharPtrBuiltinVaList; 1587 } 1588 }; 1589 1590 class DarwinPPC64TargetInfo : 1591 public DarwinTargetInfo<PPC64TargetInfo> { 1592 public: 1593 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1594 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1595 HasAlignMac68kSupport = true; 1596 SuitableAlign = 128; 1597 DataLayoutString = "E-m:o-i64:64-n32:64"; 1598 } 1599 }; 1600 1601 static const unsigned NVPTXAddrSpaceMap[] = { 1602 1, // opencl_global 1603 3, // opencl_local 1604 4, // opencl_constant 1605 // FIXME: generic has to be added to the target 1606 0, // opencl_generic 1607 1, // cuda_device 1608 4, // cuda_constant 1609 3, // cuda_shared 1610 }; 1611 1612 class NVPTXTargetInfo : public TargetInfo { 1613 static const char *const GCCRegNames[]; 1614 static const Builtin::Info BuiltinInfo[]; 1615 1616 // The GPU profiles supported by the NVPTX backend 1617 enum GPUKind { 1618 GK_NONE, 1619 GK_SM20, 1620 GK_SM21, 1621 GK_SM30, 1622 GK_SM35, 1623 GK_SM37, 1624 } GPU; 1625 1626 public: 1627 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1628 BigEndian = false; 1629 TLSSupported = false; 1630 LongWidth = LongAlign = 64; 1631 AddrSpaceMap = &NVPTXAddrSpaceMap; 1632 UseAddrSpaceMapMangling = true; 1633 // Define available target features 1634 // These must be defined in sorted order! 1635 NoAsmVariants = true; 1636 // Set the default GPU to sm20 1637 GPU = GK_SM20; 1638 } 1639 void getTargetDefines(const LangOptions &Opts, 1640 MacroBuilder &Builder) const override { 1641 Builder.defineMacro("__PTX__"); 1642 Builder.defineMacro("__NVPTX__"); 1643 if (Opts.CUDAIsDevice) { 1644 // Set __CUDA_ARCH__ for the GPU specified. 1645 std::string CUDAArchCode; 1646 switch (GPU) { 1647 case GK_SM20: 1648 CUDAArchCode = "200"; 1649 break; 1650 case GK_SM21: 1651 CUDAArchCode = "210"; 1652 break; 1653 case GK_SM30: 1654 CUDAArchCode = "300"; 1655 break; 1656 case GK_SM35: 1657 CUDAArchCode = "350"; 1658 break; 1659 case GK_SM37: 1660 CUDAArchCode = "370"; 1661 break; 1662 default: 1663 llvm_unreachable("Unhandled target CPU"); 1664 } 1665 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1666 } 1667 } 1668 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1669 return llvm::makeArrayRef(BuiltinInfo, 1670 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1671 } 1672 bool hasFeature(StringRef Feature) const override { 1673 return Feature == "ptx" || Feature == "nvptx"; 1674 } 1675 1676 ArrayRef<const char *> getGCCRegNames() const override; 1677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1678 // No aliases. 1679 return None; 1680 } 1681 bool validateAsmConstraint(const char *&Name, 1682 TargetInfo::ConstraintInfo &Info) const override { 1683 switch (*Name) { 1684 default: 1685 return false; 1686 case 'c': 1687 case 'h': 1688 case 'r': 1689 case 'l': 1690 case 'f': 1691 case 'd': 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 } 1696 const char *getClobbers() const override { 1697 // FIXME: Is this really right? 1698 return ""; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 // FIXME: implement 1702 return TargetInfo::CharPtrBuiltinVaList; 1703 } 1704 bool setCPU(const std::string &Name) override { 1705 GPU = llvm::StringSwitch<GPUKind>(Name) 1706 .Case("sm_20", GK_SM20) 1707 .Case("sm_21", GK_SM21) 1708 .Case("sm_30", GK_SM30) 1709 .Case("sm_35", GK_SM35) 1710 .Case("sm_37", GK_SM37) 1711 .Default(GK_NONE); 1712 1713 return GPU != GK_NONE; 1714 } 1715 }; 1716 1717 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1718 #define BUILTIN(ID, TYPE, ATTRS) \ 1719 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1720 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1721 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1722 #include "clang/Basic/BuiltinsNVPTX.def" 1723 }; 1724 1725 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1726 1727 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1728 return llvm::makeArrayRef(GCCRegNames); 1729 } 1730 1731 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1732 public: 1733 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1734 LongWidth = LongAlign = 32; 1735 PointerWidth = PointerAlign = 32; 1736 SizeType = TargetInfo::UnsignedInt; 1737 PtrDiffType = TargetInfo::SignedInt; 1738 IntPtrType = TargetInfo::SignedInt; 1739 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1740 } 1741 }; 1742 1743 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1744 public: 1745 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1746 PointerWidth = PointerAlign = 64; 1747 SizeType = TargetInfo::UnsignedLong; 1748 PtrDiffType = TargetInfo::SignedLong; 1749 IntPtrType = TargetInfo::SignedLong; 1750 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1751 } 1752 }; 1753 1754 static const unsigned AMDGPUAddrSpaceMap[] = { 1755 1, // opencl_global 1756 3, // opencl_local 1757 2, // opencl_constant 1758 4, // opencl_generic 1759 1, // cuda_device 1760 2, // cuda_constant 1761 3 // cuda_shared 1762 }; 1763 1764 // If you edit the description strings, make sure you update 1765 // getPointerWidthV(). 1766 1767 static const char *const DataLayoutStringR600 = 1768 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1769 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1770 1771 static const char *const DataLayoutStringR600DoubleOps = 1772 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1773 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1774 1775 static const char *const DataLayoutStringSI = 1776 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1777 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1778 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1779 1780 class AMDGPUTargetInfo : public TargetInfo { 1781 static const Builtin::Info BuiltinInfo[]; 1782 static const char * const GCCRegNames[]; 1783 1784 /// \brief The GPU profiles supported by the AMDGPU target. 1785 enum GPUKind { 1786 GK_NONE, 1787 GK_R600, 1788 GK_R600_DOUBLE_OPS, 1789 GK_R700, 1790 GK_R700_DOUBLE_OPS, 1791 GK_EVERGREEN, 1792 GK_EVERGREEN_DOUBLE_OPS, 1793 GK_NORTHERN_ISLANDS, 1794 GK_CAYMAN, 1795 GK_SOUTHERN_ISLANDS, 1796 GK_SEA_ISLANDS, 1797 GK_VOLCANIC_ISLANDS 1798 } GPU; 1799 1800 bool hasFP64:1; 1801 bool hasFMAF:1; 1802 bool hasLDEXPF:1; 1803 1804 public: 1805 AMDGPUTargetInfo(const llvm::Triple &Triple) 1806 : TargetInfo(Triple) { 1807 1808 if (Triple.getArch() == llvm::Triple::amdgcn) { 1809 DataLayoutString = DataLayoutStringSI; 1810 GPU = GK_SOUTHERN_ISLANDS; 1811 hasFP64 = true; 1812 hasFMAF = true; 1813 hasLDEXPF = true; 1814 } else { 1815 DataLayoutString = DataLayoutStringR600; 1816 GPU = GK_R600; 1817 hasFP64 = false; 1818 hasFMAF = false; 1819 hasLDEXPF = false; 1820 } 1821 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1822 UseAddrSpaceMapMangling = true; 1823 } 1824 1825 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1826 if (GPU <= GK_CAYMAN) 1827 return 32; 1828 1829 switch(AddrSpace) { 1830 default: 1831 return 64; 1832 case 0: 1833 case 3: 1834 case 5: 1835 return 32; 1836 } 1837 } 1838 1839 const char * getClobbers() const override { 1840 return ""; 1841 } 1842 1843 ArrayRef<const char *> getGCCRegNames() const override; 1844 1845 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1846 return None; 1847 } 1848 1849 bool validateAsmConstraint(const char *&Name, 1850 TargetInfo::ConstraintInfo &Info) const override { 1851 switch (*Name) { 1852 default: break; 1853 case 'v': // vgpr 1854 case 's': // sgpr 1855 Info.setAllowsRegister(); 1856 return true; 1857 } 1858 return false; 1859 } 1860 1861 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1862 return llvm::makeArrayRef(BuiltinInfo, 1863 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1864 } 1865 1866 void getTargetDefines(const LangOptions &Opts, 1867 MacroBuilder &Builder) const override { 1868 Builder.defineMacro("__R600__"); 1869 if (hasFMAF) 1870 Builder.defineMacro("__HAS_FMAF__"); 1871 if (hasLDEXPF) 1872 Builder.defineMacro("__HAS_LDEXPF__"); 1873 if (hasFP64 && Opts.OpenCL) 1874 Builder.defineMacro("cl_khr_fp64"); 1875 if (Opts.OpenCL) { 1876 if (GPU >= GK_NORTHERN_ISLANDS) { 1877 Builder.defineMacro("cl_khr_byte_addressable_store"); 1878 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1879 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1880 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1881 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1882 } 1883 } 1884 } 1885 1886 BuiltinVaListKind getBuiltinVaListKind() const override { 1887 return TargetInfo::CharPtrBuiltinVaList; 1888 } 1889 1890 bool setCPU(const std::string &Name) override { 1891 GPU = llvm::StringSwitch<GPUKind>(Name) 1892 .Case("r600" , GK_R600) 1893 .Case("rv610", GK_R600) 1894 .Case("rv620", GK_R600) 1895 .Case("rv630", GK_R600) 1896 .Case("rv635", GK_R600) 1897 .Case("rs780", GK_R600) 1898 .Case("rs880", GK_R600) 1899 .Case("rv670", GK_R600_DOUBLE_OPS) 1900 .Case("rv710", GK_R700) 1901 .Case("rv730", GK_R700) 1902 .Case("rv740", GK_R700_DOUBLE_OPS) 1903 .Case("rv770", GK_R700_DOUBLE_OPS) 1904 .Case("palm", GK_EVERGREEN) 1905 .Case("cedar", GK_EVERGREEN) 1906 .Case("sumo", GK_EVERGREEN) 1907 .Case("sumo2", GK_EVERGREEN) 1908 .Case("redwood", GK_EVERGREEN) 1909 .Case("juniper", GK_EVERGREEN) 1910 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1911 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1912 .Case("barts", GK_NORTHERN_ISLANDS) 1913 .Case("turks", GK_NORTHERN_ISLANDS) 1914 .Case("caicos", GK_NORTHERN_ISLANDS) 1915 .Case("cayman", GK_CAYMAN) 1916 .Case("aruba", GK_CAYMAN) 1917 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1918 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1919 .Case("verde", GK_SOUTHERN_ISLANDS) 1920 .Case("oland", GK_SOUTHERN_ISLANDS) 1921 .Case("hainan", GK_SOUTHERN_ISLANDS) 1922 .Case("bonaire", GK_SEA_ISLANDS) 1923 .Case("kabini", GK_SEA_ISLANDS) 1924 .Case("kaveri", GK_SEA_ISLANDS) 1925 .Case("hawaii", GK_SEA_ISLANDS) 1926 .Case("mullins", GK_SEA_ISLANDS) 1927 .Case("tonga", GK_VOLCANIC_ISLANDS) 1928 .Case("iceland", GK_VOLCANIC_ISLANDS) 1929 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1930 .Default(GK_NONE); 1931 1932 if (GPU == GK_NONE) { 1933 return false; 1934 } 1935 1936 // Set the correct data layout 1937 switch (GPU) { 1938 case GK_NONE: 1939 case GK_R600: 1940 case GK_R700: 1941 case GK_EVERGREEN: 1942 case GK_NORTHERN_ISLANDS: 1943 DataLayoutString = DataLayoutStringR600; 1944 hasFP64 = false; 1945 hasFMAF = false; 1946 hasLDEXPF = false; 1947 break; 1948 case GK_R600_DOUBLE_OPS: 1949 case GK_R700_DOUBLE_OPS: 1950 case GK_EVERGREEN_DOUBLE_OPS: 1951 case GK_CAYMAN: 1952 DataLayoutString = DataLayoutStringR600DoubleOps; 1953 hasFP64 = true; 1954 hasFMAF = true; 1955 hasLDEXPF = false; 1956 break; 1957 case GK_SOUTHERN_ISLANDS: 1958 case GK_SEA_ISLANDS: 1959 case GK_VOLCANIC_ISLANDS: 1960 DataLayoutString = DataLayoutStringSI; 1961 hasFP64 = true; 1962 hasFMAF = true; 1963 hasLDEXPF = true; 1964 break; 1965 } 1966 1967 return true; 1968 } 1969 }; 1970 1971 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1972 #define BUILTIN(ID, TYPE, ATTRS) \ 1973 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1974 #include "clang/Basic/BuiltinsAMDGPU.def" 1975 }; 1976 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1977 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1978 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1979 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1980 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1981 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1982 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1983 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1984 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1985 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1986 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1987 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1988 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1989 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1990 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1991 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1992 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1993 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1994 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1995 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1996 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1997 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1998 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1999 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2000 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2001 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2002 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2003 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2004 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2005 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2006 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2007 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2008 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2009 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2010 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2011 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2012 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2013 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2014 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2015 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2016 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2017 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2018 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2019 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2020 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2021 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2022 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2023 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2024 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2025 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2026 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2027 }; 2028 2029 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2030 return llvm::makeArrayRef(GCCRegNames); 2031 } 2032 2033 // Namespace for x86 abstract base class 2034 const Builtin::Info BuiltinInfo[] = { 2035 #define BUILTIN(ID, TYPE, ATTRS) \ 2036 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2037 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2038 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2039 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2041 #include "clang/Basic/BuiltinsX86.def" 2042 }; 2043 2044 static const char* const GCCRegNames[] = { 2045 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2046 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2047 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2048 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2049 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2050 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2051 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2052 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2053 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2054 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2055 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2056 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2057 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2058 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2059 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2060 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2061 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2062 }; 2063 2064 const TargetInfo::AddlRegName AddlRegNames[] = { 2065 { { "al", "ah", "eax", "rax" }, 0 }, 2066 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2067 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2068 { { "dl", "dh", "edx", "rdx" }, 1 }, 2069 { { "esi", "rsi" }, 4 }, 2070 { { "edi", "rdi" }, 5 }, 2071 { { "esp", "rsp" }, 7 }, 2072 { { "ebp", "rbp" }, 6 }, 2073 { { "r8d", "r8w", "r8b" }, 38 }, 2074 { { "r9d", "r9w", "r9b" }, 39 }, 2075 { { "r10d", "r10w", "r10b" }, 40 }, 2076 { { "r11d", "r11w", "r11b" }, 41 }, 2077 { { "r12d", "r12w", "r12b" }, 42 }, 2078 { { "r13d", "r13w", "r13b" }, 43 }, 2079 { { "r14d", "r14w", "r14b" }, 44 }, 2080 { { "r15d", "r15w", "r15b" }, 45 }, 2081 }; 2082 2083 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2084 // most of the implementation can be shared. 2085 class X86TargetInfo : public TargetInfo { 2086 enum X86SSEEnum { 2087 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2088 } SSELevel = NoSSE; 2089 enum MMX3DNowEnum { 2090 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2091 } MMX3DNowLevel = NoMMX3DNow; 2092 enum XOPEnum { 2093 NoXOP, 2094 SSE4A, 2095 FMA4, 2096 XOP 2097 } XOPLevel = NoXOP; 2098 2099 bool HasAES = false; 2100 bool HasPCLMUL = false; 2101 bool HasLZCNT = false; 2102 bool HasRDRND = false; 2103 bool HasFSGSBASE = false; 2104 bool HasBMI = false; 2105 bool HasBMI2 = false; 2106 bool HasPOPCNT = false; 2107 bool HasRTM = false; 2108 bool HasPRFCHW = false; 2109 bool HasRDSEED = false; 2110 bool HasADX = false; 2111 bool HasTBM = false; 2112 bool HasFMA = false; 2113 bool HasF16C = false; 2114 bool HasAVX512CD = false; 2115 bool HasAVX512ER = false; 2116 bool HasAVX512PF = false; 2117 bool HasAVX512DQ = false; 2118 bool HasAVX512BW = false; 2119 bool HasAVX512VL = false; 2120 bool HasSHA = false; 2121 bool HasCX16 = false; 2122 bool HasFXSR = false; 2123 bool HasXSAVE = false; 2124 bool HasXSAVEOPT = false; 2125 bool HasXSAVEC = false; 2126 bool HasXSAVES = false; 2127 bool HasPKU = false; 2128 2129 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2130 /// 2131 /// Each enumeration represents a particular CPU supported by Clang. These 2132 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2133 enum CPUKind { 2134 CK_Generic, 2135 2136 /// \name i386 2137 /// i386-generation processors. 2138 //@{ 2139 CK_i386, 2140 //@} 2141 2142 /// \name i486 2143 /// i486-generation processors. 2144 //@{ 2145 CK_i486, 2146 CK_WinChipC6, 2147 CK_WinChip2, 2148 CK_C3, 2149 //@} 2150 2151 /// \name i586 2152 /// i586-generation processors, P5 microarchitecture based. 2153 //@{ 2154 CK_i586, 2155 CK_Pentium, 2156 CK_PentiumMMX, 2157 //@} 2158 2159 /// \name i686 2160 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2161 //@{ 2162 CK_i686, 2163 CK_PentiumPro, 2164 CK_Pentium2, 2165 CK_Pentium3, 2166 CK_Pentium3M, 2167 CK_PentiumM, 2168 CK_C3_2, 2169 2170 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2171 /// Clang however has some logic to suport this. 2172 // FIXME: Warn, deprecate, and potentially remove this. 2173 CK_Yonah, 2174 //@} 2175 2176 /// \name Netburst 2177 /// Netburst microarchitecture based processors. 2178 //@{ 2179 CK_Pentium4, 2180 CK_Pentium4M, 2181 CK_Prescott, 2182 CK_Nocona, 2183 //@} 2184 2185 /// \name Core 2186 /// Core microarchitecture based processors. 2187 //@{ 2188 CK_Core2, 2189 2190 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2191 /// codename which GCC no longer accepts as an option to -march, but Clang 2192 /// has some logic for recognizing it. 2193 // FIXME: Warn, deprecate, and potentially remove this. 2194 CK_Penryn, 2195 //@} 2196 2197 /// \name Atom 2198 /// Atom processors 2199 //@{ 2200 CK_Bonnell, 2201 CK_Silvermont, 2202 //@} 2203 2204 /// \name Nehalem 2205 /// Nehalem microarchitecture based processors. 2206 CK_Nehalem, 2207 2208 /// \name Westmere 2209 /// Westmere microarchitecture based processors. 2210 CK_Westmere, 2211 2212 /// \name Sandy Bridge 2213 /// Sandy Bridge microarchitecture based processors. 2214 CK_SandyBridge, 2215 2216 /// \name Ivy Bridge 2217 /// Ivy Bridge microarchitecture based processors. 2218 CK_IvyBridge, 2219 2220 /// \name Haswell 2221 /// Haswell microarchitecture based processors. 2222 CK_Haswell, 2223 2224 /// \name Broadwell 2225 /// Broadwell microarchitecture based processors. 2226 CK_Broadwell, 2227 2228 /// \name Skylake 2229 /// Skylake microarchitecture based processors. 2230 CK_Skylake, 2231 2232 /// \name Knights Landing 2233 /// Knights Landing processor. 2234 CK_KNL, 2235 2236 /// \name K6 2237 /// K6 architecture processors. 2238 //@{ 2239 CK_K6, 2240 CK_K6_2, 2241 CK_K6_3, 2242 //@} 2243 2244 /// \name K7 2245 /// K7 architecture processors. 2246 //@{ 2247 CK_Athlon, 2248 CK_AthlonThunderbird, 2249 CK_Athlon4, 2250 CK_AthlonXP, 2251 CK_AthlonMP, 2252 //@} 2253 2254 /// \name K8 2255 /// K8 architecture processors. 2256 //@{ 2257 CK_Athlon64, 2258 CK_Athlon64SSE3, 2259 CK_AthlonFX, 2260 CK_K8, 2261 CK_K8SSE3, 2262 CK_Opteron, 2263 CK_OpteronSSE3, 2264 CK_AMDFAM10, 2265 //@} 2266 2267 /// \name Bobcat 2268 /// Bobcat architecture processors. 2269 //@{ 2270 CK_BTVER1, 2271 CK_BTVER2, 2272 //@} 2273 2274 /// \name Bulldozer 2275 /// Bulldozer architecture processors. 2276 //@{ 2277 CK_BDVER1, 2278 CK_BDVER2, 2279 CK_BDVER3, 2280 CK_BDVER4, 2281 //@} 2282 2283 /// This specification is deprecated and will be removed in the future. 2284 /// Users should prefer \see CK_K8. 2285 // FIXME: Warn on this when the CPU is set to it. 2286 //@{ 2287 CK_x86_64, 2288 //@} 2289 2290 /// \name Geode 2291 /// Geode processors. 2292 //@{ 2293 CK_Geode 2294 //@} 2295 } CPU = CK_Generic; 2296 2297 CPUKind getCPUKind(StringRef CPU) const { 2298 return llvm::StringSwitch<CPUKind>(CPU) 2299 .Case("i386", CK_i386) 2300 .Case("i486", CK_i486) 2301 .Case("winchip-c6", CK_WinChipC6) 2302 .Case("winchip2", CK_WinChip2) 2303 .Case("c3", CK_C3) 2304 .Case("i586", CK_i586) 2305 .Case("pentium", CK_Pentium) 2306 .Case("pentium-mmx", CK_PentiumMMX) 2307 .Case("i686", CK_i686) 2308 .Case("pentiumpro", CK_PentiumPro) 2309 .Case("pentium2", CK_Pentium2) 2310 .Case("pentium3", CK_Pentium3) 2311 .Case("pentium3m", CK_Pentium3M) 2312 .Case("pentium-m", CK_PentiumM) 2313 .Case("c3-2", CK_C3_2) 2314 .Case("yonah", CK_Yonah) 2315 .Case("pentium4", CK_Pentium4) 2316 .Case("pentium4m", CK_Pentium4M) 2317 .Case("prescott", CK_Prescott) 2318 .Case("nocona", CK_Nocona) 2319 .Case("core2", CK_Core2) 2320 .Case("penryn", CK_Penryn) 2321 .Case("bonnell", CK_Bonnell) 2322 .Case("atom", CK_Bonnell) // Legacy name. 2323 .Case("silvermont", CK_Silvermont) 2324 .Case("slm", CK_Silvermont) // Legacy name. 2325 .Case("nehalem", CK_Nehalem) 2326 .Case("corei7", CK_Nehalem) // Legacy name. 2327 .Case("westmere", CK_Westmere) 2328 .Case("sandybridge", CK_SandyBridge) 2329 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2330 .Case("ivybridge", CK_IvyBridge) 2331 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2332 .Case("haswell", CK_Haswell) 2333 .Case("core-avx2", CK_Haswell) // Legacy name. 2334 .Case("broadwell", CK_Broadwell) 2335 .Case("skylake", CK_Skylake) 2336 .Case("skx", CK_Skylake) // Legacy name. 2337 .Case("knl", CK_KNL) 2338 .Case("k6", CK_K6) 2339 .Case("k6-2", CK_K6_2) 2340 .Case("k6-3", CK_K6_3) 2341 .Case("athlon", CK_Athlon) 2342 .Case("athlon-tbird", CK_AthlonThunderbird) 2343 .Case("athlon-4", CK_Athlon4) 2344 .Case("athlon-xp", CK_AthlonXP) 2345 .Case("athlon-mp", CK_AthlonMP) 2346 .Case("athlon64", CK_Athlon64) 2347 .Case("athlon64-sse3", CK_Athlon64SSE3) 2348 .Case("athlon-fx", CK_AthlonFX) 2349 .Case("k8", CK_K8) 2350 .Case("k8-sse3", CK_K8SSE3) 2351 .Case("opteron", CK_Opteron) 2352 .Case("opteron-sse3", CK_OpteronSSE3) 2353 .Case("barcelona", CK_AMDFAM10) 2354 .Case("amdfam10", CK_AMDFAM10) 2355 .Case("btver1", CK_BTVER1) 2356 .Case("btver2", CK_BTVER2) 2357 .Case("bdver1", CK_BDVER1) 2358 .Case("bdver2", CK_BDVER2) 2359 .Case("bdver3", CK_BDVER3) 2360 .Case("bdver4", CK_BDVER4) 2361 .Case("x86-64", CK_x86_64) 2362 .Case("geode", CK_Geode) 2363 .Default(CK_Generic); 2364 } 2365 2366 enum FPMathKind { 2367 FP_Default, 2368 FP_SSE, 2369 FP_387 2370 } FPMath = FP_Default; 2371 2372 public: 2373 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2374 BigEndian = false; 2375 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2376 } 2377 unsigned getFloatEvalMethod() const override { 2378 // X87 evaluates with 80 bits "long double" precision. 2379 return SSELevel == NoSSE ? 2 : 0; 2380 } 2381 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2382 return llvm::makeArrayRef(BuiltinInfo, 2383 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2384 } 2385 ArrayRef<const char *> getGCCRegNames() const override { 2386 return llvm::makeArrayRef(GCCRegNames); 2387 } 2388 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2389 return None; 2390 } 2391 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2392 return llvm::makeArrayRef(AddlRegNames); 2393 } 2394 bool validateCpuSupports(StringRef Name) const override; 2395 bool validateAsmConstraint(const char *&Name, 2396 TargetInfo::ConstraintInfo &info) const override; 2397 2398 bool validateGlobalRegisterVariable(StringRef RegName, 2399 unsigned RegSize, 2400 bool &HasSizeMismatch) const override { 2401 // esp and ebp are the only 32-bit registers the x86 backend can currently 2402 // handle. 2403 if (RegName.equals("esp") || RegName.equals("ebp")) { 2404 // Check that the register size is 32-bit. 2405 HasSizeMismatch = RegSize != 32; 2406 return true; 2407 } 2408 2409 return false; 2410 } 2411 2412 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2413 2414 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2415 2416 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2417 2418 std::string convertConstraint(const char *&Constraint) const override; 2419 const char *getClobbers() const override { 2420 return "~{dirflag},~{fpsr},~{flags}"; 2421 } 2422 void getTargetDefines(const LangOptions &Opts, 2423 MacroBuilder &Builder) const override; 2424 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2425 bool Enabled); 2426 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2427 bool Enabled); 2428 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2429 bool Enabled); 2430 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2431 StringRef Name, bool Enabled) const override { 2432 setFeatureEnabledImpl(Features, Name, Enabled); 2433 } 2434 // This exists purely to cut down on the number of virtual calls in 2435 // initFeatureMap which calls this repeatedly. 2436 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2437 StringRef Name, bool Enabled); 2438 bool 2439 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2440 StringRef CPU, 2441 const std::vector<std::string> &FeaturesVec) const override; 2442 bool hasFeature(StringRef Feature) const override; 2443 bool handleTargetFeatures(std::vector<std::string> &Features, 2444 DiagnosticsEngine &Diags) override; 2445 StringRef getABI() const override { 2446 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2447 return "avx512"; 2448 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2449 return "avx"; 2450 if (getTriple().getArch() == llvm::Triple::x86 && 2451 MMX3DNowLevel == NoMMX3DNow) 2452 return "no-mmx"; 2453 return ""; 2454 } 2455 bool setCPU(const std::string &Name) override { 2456 CPU = getCPUKind(Name); 2457 2458 // Perform any per-CPU checks necessary to determine if this CPU is 2459 // acceptable. 2460 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2461 // invalid without explaining *why*. 2462 switch (CPU) { 2463 case CK_Generic: 2464 // No processor selected! 2465 return false; 2466 2467 case CK_i386: 2468 case CK_i486: 2469 case CK_WinChipC6: 2470 case CK_WinChip2: 2471 case CK_C3: 2472 case CK_i586: 2473 case CK_Pentium: 2474 case CK_PentiumMMX: 2475 case CK_i686: 2476 case CK_PentiumPro: 2477 case CK_Pentium2: 2478 case CK_Pentium3: 2479 case CK_Pentium3M: 2480 case CK_PentiumM: 2481 case CK_Yonah: 2482 case CK_C3_2: 2483 case CK_Pentium4: 2484 case CK_Pentium4M: 2485 case CK_Prescott: 2486 case CK_K6: 2487 case CK_K6_2: 2488 case CK_K6_3: 2489 case CK_Athlon: 2490 case CK_AthlonThunderbird: 2491 case CK_Athlon4: 2492 case CK_AthlonXP: 2493 case CK_AthlonMP: 2494 case CK_Geode: 2495 // Only accept certain architectures when compiling in 32-bit mode. 2496 if (getTriple().getArch() != llvm::Triple::x86) 2497 return false; 2498 2499 // Fallthrough 2500 case CK_Nocona: 2501 case CK_Core2: 2502 case CK_Penryn: 2503 case CK_Bonnell: 2504 case CK_Silvermont: 2505 case CK_Nehalem: 2506 case CK_Westmere: 2507 case CK_SandyBridge: 2508 case CK_IvyBridge: 2509 case CK_Haswell: 2510 case CK_Broadwell: 2511 case CK_Skylake: 2512 case CK_KNL: 2513 case CK_Athlon64: 2514 case CK_Athlon64SSE3: 2515 case CK_AthlonFX: 2516 case CK_K8: 2517 case CK_K8SSE3: 2518 case CK_Opteron: 2519 case CK_OpteronSSE3: 2520 case CK_AMDFAM10: 2521 case CK_BTVER1: 2522 case CK_BTVER2: 2523 case CK_BDVER1: 2524 case CK_BDVER2: 2525 case CK_BDVER3: 2526 case CK_BDVER4: 2527 case CK_x86_64: 2528 return true; 2529 } 2530 llvm_unreachable("Unhandled CPU kind"); 2531 } 2532 2533 bool setFPMath(StringRef Name) override; 2534 2535 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2536 // We accept all non-ARM calling conventions 2537 return (CC == CC_X86ThisCall || 2538 CC == CC_X86FastCall || 2539 CC == CC_X86StdCall || 2540 CC == CC_X86VectorCall || 2541 CC == CC_C || 2542 CC == CC_X86Pascal || 2543 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2544 } 2545 2546 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2547 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2548 } 2549 2550 bool hasSjLjLowering() const override { 2551 return true; 2552 } 2553 }; 2554 2555 bool X86TargetInfo::setFPMath(StringRef Name) { 2556 if (Name == "387") { 2557 FPMath = FP_387; 2558 return true; 2559 } 2560 if (Name == "sse") { 2561 FPMath = FP_SSE; 2562 return true; 2563 } 2564 return false; 2565 } 2566 2567 bool X86TargetInfo::initFeatureMap( 2568 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2569 const std::vector<std::string> &FeaturesVec) const { 2570 // FIXME: This *really* should not be here. 2571 // X86_64 always has SSE2. 2572 if (getTriple().getArch() == llvm::Triple::x86_64) 2573 setFeatureEnabledImpl(Features, "sse2", true); 2574 2575 switch (getCPUKind(CPU)) { 2576 case CK_Generic: 2577 case CK_i386: 2578 case CK_i486: 2579 case CK_i586: 2580 case CK_Pentium: 2581 case CK_i686: 2582 case CK_PentiumPro: 2583 break; 2584 case CK_PentiumMMX: 2585 case CK_Pentium2: 2586 case CK_K6: 2587 case CK_WinChipC6: 2588 setFeatureEnabledImpl(Features, "mmx", true); 2589 break; 2590 case CK_Pentium3: 2591 case CK_Pentium3M: 2592 case CK_C3_2: 2593 setFeatureEnabledImpl(Features, "sse", true); 2594 setFeatureEnabledImpl(Features, "fxsr", true); 2595 break; 2596 case CK_PentiumM: 2597 case CK_Pentium4: 2598 case CK_Pentium4M: 2599 case CK_x86_64: 2600 setFeatureEnabledImpl(Features, "sse2", true); 2601 setFeatureEnabledImpl(Features, "fxsr", true); 2602 break; 2603 case CK_Yonah: 2604 case CK_Prescott: 2605 case CK_Nocona: 2606 setFeatureEnabledImpl(Features, "sse3", true); 2607 setFeatureEnabledImpl(Features, "fxsr", true); 2608 setFeatureEnabledImpl(Features, "cx16", true); 2609 break; 2610 case CK_Core2: 2611 case CK_Bonnell: 2612 setFeatureEnabledImpl(Features, "ssse3", true); 2613 setFeatureEnabledImpl(Features, "fxsr", true); 2614 setFeatureEnabledImpl(Features, "cx16", true); 2615 break; 2616 case CK_Penryn: 2617 setFeatureEnabledImpl(Features, "sse4.1", true); 2618 setFeatureEnabledImpl(Features, "fxsr", true); 2619 setFeatureEnabledImpl(Features, "cx16", true); 2620 break; 2621 case CK_Skylake: 2622 setFeatureEnabledImpl(Features, "avx512f", true); 2623 setFeatureEnabledImpl(Features, "avx512cd", true); 2624 setFeatureEnabledImpl(Features, "avx512dq", true); 2625 setFeatureEnabledImpl(Features, "avx512bw", true); 2626 setFeatureEnabledImpl(Features, "avx512vl", true); 2627 setFeatureEnabledImpl(Features, "xsavec", true); 2628 setFeatureEnabledImpl(Features, "xsaves", true); 2629 setFeatureEnabledImpl(Features, "pku", true); 2630 // FALLTHROUGH 2631 case CK_Broadwell: 2632 setFeatureEnabledImpl(Features, "rdseed", true); 2633 setFeatureEnabledImpl(Features, "adx", true); 2634 // FALLTHROUGH 2635 case CK_Haswell: 2636 setFeatureEnabledImpl(Features, "avx2", true); 2637 setFeatureEnabledImpl(Features, "lzcnt", true); 2638 setFeatureEnabledImpl(Features, "bmi", true); 2639 setFeatureEnabledImpl(Features, "bmi2", true); 2640 setFeatureEnabledImpl(Features, "rtm", true); 2641 setFeatureEnabledImpl(Features, "fma", true); 2642 // FALLTHROUGH 2643 case CK_IvyBridge: 2644 setFeatureEnabledImpl(Features, "rdrnd", true); 2645 setFeatureEnabledImpl(Features, "f16c", true); 2646 setFeatureEnabledImpl(Features, "fsgsbase", true); 2647 // FALLTHROUGH 2648 case CK_SandyBridge: 2649 setFeatureEnabledImpl(Features, "avx", true); 2650 setFeatureEnabledImpl(Features, "xsave", true); 2651 setFeatureEnabledImpl(Features, "xsaveopt", true); 2652 // FALLTHROUGH 2653 case CK_Westmere: 2654 case CK_Silvermont: 2655 setFeatureEnabledImpl(Features, "aes", true); 2656 setFeatureEnabledImpl(Features, "pclmul", true); 2657 // FALLTHROUGH 2658 case CK_Nehalem: 2659 setFeatureEnabledImpl(Features, "sse4.2", true); 2660 setFeatureEnabledImpl(Features, "fxsr", true); 2661 setFeatureEnabledImpl(Features, "cx16", true); 2662 break; 2663 case CK_KNL: 2664 setFeatureEnabledImpl(Features, "avx512f", true); 2665 setFeatureEnabledImpl(Features, "avx512cd", true); 2666 setFeatureEnabledImpl(Features, "avx512er", true); 2667 setFeatureEnabledImpl(Features, "avx512pf", true); 2668 setFeatureEnabledImpl(Features, "fxsr", true); 2669 setFeatureEnabledImpl(Features, "rdseed", true); 2670 setFeatureEnabledImpl(Features, "adx", true); 2671 setFeatureEnabledImpl(Features, "lzcnt", true); 2672 setFeatureEnabledImpl(Features, "bmi", true); 2673 setFeatureEnabledImpl(Features, "bmi2", true); 2674 setFeatureEnabledImpl(Features, "rtm", true); 2675 setFeatureEnabledImpl(Features, "fma", true); 2676 setFeatureEnabledImpl(Features, "rdrnd", true); 2677 setFeatureEnabledImpl(Features, "f16c", true); 2678 setFeatureEnabledImpl(Features, "fsgsbase", true); 2679 setFeatureEnabledImpl(Features, "aes", true); 2680 setFeatureEnabledImpl(Features, "pclmul", true); 2681 setFeatureEnabledImpl(Features, "cx16", true); 2682 setFeatureEnabledImpl(Features, "xsaveopt", true); 2683 setFeatureEnabledImpl(Features, "xsave", true); 2684 break; 2685 case CK_K6_2: 2686 case CK_K6_3: 2687 case CK_WinChip2: 2688 case CK_C3: 2689 setFeatureEnabledImpl(Features, "3dnow", true); 2690 break; 2691 case CK_Athlon: 2692 case CK_AthlonThunderbird: 2693 case CK_Geode: 2694 setFeatureEnabledImpl(Features, "3dnowa", true); 2695 break; 2696 case CK_Athlon4: 2697 case CK_AthlonXP: 2698 case CK_AthlonMP: 2699 setFeatureEnabledImpl(Features, "sse", true); 2700 setFeatureEnabledImpl(Features, "3dnowa", true); 2701 setFeatureEnabledImpl(Features, "fxsr", true); 2702 break; 2703 case CK_K8: 2704 case CK_Opteron: 2705 case CK_Athlon64: 2706 case CK_AthlonFX: 2707 setFeatureEnabledImpl(Features, "sse2", true); 2708 setFeatureEnabledImpl(Features, "3dnowa", true); 2709 setFeatureEnabledImpl(Features, "fxsr", true); 2710 break; 2711 case CK_AMDFAM10: 2712 setFeatureEnabledImpl(Features, "sse4a", true); 2713 setFeatureEnabledImpl(Features, "lzcnt", true); 2714 setFeatureEnabledImpl(Features, "popcnt", true); 2715 // FALLTHROUGH 2716 case CK_K8SSE3: 2717 case CK_OpteronSSE3: 2718 case CK_Athlon64SSE3: 2719 setFeatureEnabledImpl(Features, "sse3", true); 2720 setFeatureEnabledImpl(Features, "3dnowa", true); 2721 setFeatureEnabledImpl(Features, "fxsr", true); 2722 break; 2723 case CK_BTVER2: 2724 setFeatureEnabledImpl(Features, "avx", true); 2725 setFeatureEnabledImpl(Features, "aes", true); 2726 setFeatureEnabledImpl(Features, "pclmul", true); 2727 setFeatureEnabledImpl(Features, "bmi", true); 2728 setFeatureEnabledImpl(Features, "f16c", true); 2729 setFeatureEnabledImpl(Features, "xsaveopt", true); 2730 // FALLTHROUGH 2731 case CK_BTVER1: 2732 setFeatureEnabledImpl(Features, "ssse3", true); 2733 setFeatureEnabledImpl(Features, "sse4a", true); 2734 setFeatureEnabledImpl(Features, "lzcnt", true); 2735 setFeatureEnabledImpl(Features, "popcnt", true); 2736 setFeatureEnabledImpl(Features, "prfchw", true); 2737 setFeatureEnabledImpl(Features, "cx16", true); 2738 setFeatureEnabledImpl(Features, "fxsr", true); 2739 setFeatureEnabledImpl(Features, "xsave", true); 2740 break; 2741 case CK_BDVER4: 2742 setFeatureEnabledImpl(Features, "avx2", true); 2743 setFeatureEnabledImpl(Features, "bmi2", true); 2744 // FALLTHROUGH 2745 case CK_BDVER3: 2746 setFeatureEnabledImpl(Features, "fsgsbase", true); 2747 setFeatureEnabledImpl(Features, "xsaveopt", true); 2748 // FALLTHROUGH 2749 case CK_BDVER2: 2750 setFeatureEnabledImpl(Features, "bmi", true); 2751 setFeatureEnabledImpl(Features, "fma", true); 2752 setFeatureEnabledImpl(Features, "f16c", true); 2753 setFeatureEnabledImpl(Features, "tbm", true); 2754 // FALLTHROUGH 2755 case CK_BDVER1: 2756 // xop implies avx, sse4a and fma4. 2757 setFeatureEnabledImpl(Features, "xop", true); 2758 setFeatureEnabledImpl(Features, "lzcnt", true); 2759 setFeatureEnabledImpl(Features, "aes", true); 2760 setFeatureEnabledImpl(Features, "pclmul", true); 2761 setFeatureEnabledImpl(Features, "prfchw", true); 2762 setFeatureEnabledImpl(Features, "cx16", true); 2763 setFeatureEnabledImpl(Features, "fxsr", true); 2764 setFeatureEnabledImpl(Features, "xsave", true); 2765 break; 2766 } 2767 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2768 return false; 2769 2770 // Can't do this earlier because we need to be able to explicitly enable 2771 // or disable these features and the things that they depend upon. 2772 2773 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2774 auto I = Features.find("sse4.2"); 2775 if (I != Features.end() && I->getValue() && 2776 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2777 FeaturesVec.end()) 2778 Features["popcnt"] = true; 2779 2780 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2781 I = Features.find("3dnow"); 2782 if (I != Features.end() && I->getValue() && 2783 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2784 FeaturesVec.end()) 2785 Features["prfchw"] = true; 2786 2787 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2788 // then enable MMX. 2789 I = Features.find("sse"); 2790 if (I != Features.end() && I->getValue() && 2791 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2792 FeaturesVec.end()) 2793 Features["mmx"] = true; 2794 2795 return true; 2796 } 2797 2798 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2799 X86SSEEnum Level, bool Enabled) { 2800 if (Enabled) { 2801 switch (Level) { 2802 case AVX512F: 2803 Features["avx512f"] = true; 2804 case AVX2: 2805 Features["avx2"] = true; 2806 case AVX: 2807 Features["avx"] = true; 2808 Features["xsave"] = true; 2809 case SSE42: 2810 Features["sse4.2"] = true; 2811 case SSE41: 2812 Features["sse4.1"] = true; 2813 case SSSE3: 2814 Features["ssse3"] = true; 2815 case SSE3: 2816 Features["sse3"] = true; 2817 case SSE2: 2818 Features["sse2"] = true; 2819 case SSE1: 2820 Features["sse"] = true; 2821 case NoSSE: 2822 break; 2823 } 2824 return; 2825 } 2826 2827 switch (Level) { 2828 case NoSSE: 2829 case SSE1: 2830 Features["sse"] = false; 2831 case SSE2: 2832 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2833 Features["sha"] = false; 2834 case SSE3: 2835 Features["sse3"] = false; 2836 setXOPLevel(Features, NoXOP, false); 2837 case SSSE3: 2838 Features["ssse3"] = false; 2839 case SSE41: 2840 Features["sse4.1"] = false; 2841 case SSE42: 2842 Features["sse4.2"] = false; 2843 case AVX: 2844 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2845 Features["xsaveopt"] = false; 2846 setXOPLevel(Features, FMA4, false); 2847 case AVX2: 2848 Features["avx2"] = false; 2849 case AVX512F: 2850 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2851 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2852 Features["avx512vl"] = false; 2853 } 2854 } 2855 2856 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2857 MMX3DNowEnum Level, bool Enabled) { 2858 if (Enabled) { 2859 switch (Level) { 2860 case AMD3DNowAthlon: 2861 Features["3dnowa"] = true; 2862 case AMD3DNow: 2863 Features["3dnow"] = true; 2864 case MMX: 2865 Features["mmx"] = true; 2866 case NoMMX3DNow: 2867 break; 2868 } 2869 return; 2870 } 2871 2872 switch (Level) { 2873 case NoMMX3DNow: 2874 case MMX: 2875 Features["mmx"] = false; 2876 case AMD3DNow: 2877 Features["3dnow"] = false; 2878 case AMD3DNowAthlon: 2879 Features["3dnowa"] = false; 2880 } 2881 } 2882 2883 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2884 bool Enabled) { 2885 if (Enabled) { 2886 switch (Level) { 2887 case XOP: 2888 Features["xop"] = true; 2889 case FMA4: 2890 Features["fma4"] = true; 2891 setSSELevel(Features, AVX, true); 2892 case SSE4A: 2893 Features["sse4a"] = true; 2894 setSSELevel(Features, SSE3, true); 2895 case NoXOP: 2896 break; 2897 } 2898 return; 2899 } 2900 2901 switch (Level) { 2902 case NoXOP: 2903 case SSE4A: 2904 Features["sse4a"] = false; 2905 case FMA4: 2906 Features["fma4"] = false; 2907 case XOP: 2908 Features["xop"] = false; 2909 } 2910 } 2911 2912 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2913 StringRef Name, bool Enabled) { 2914 // This is a bit of a hack to deal with the sse4 target feature when used 2915 // as part of the target attribute. We handle sse4 correctly everywhere 2916 // else. See below for more information on how we handle the sse4 options. 2917 if (Name != "sse4") 2918 Features[Name] = Enabled; 2919 2920 if (Name == "mmx") { 2921 setMMXLevel(Features, MMX, Enabled); 2922 } else if (Name == "sse") { 2923 setSSELevel(Features, SSE1, Enabled); 2924 } else if (Name == "sse2") { 2925 setSSELevel(Features, SSE2, Enabled); 2926 } else if (Name == "sse3") { 2927 setSSELevel(Features, SSE3, Enabled); 2928 } else if (Name == "ssse3") { 2929 setSSELevel(Features, SSSE3, Enabled); 2930 } else if (Name == "sse4.2") { 2931 setSSELevel(Features, SSE42, Enabled); 2932 } else if (Name == "sse4.1") { 2933 setSSELevel(Features, SSE41, Enabled); 2934 } else if (Name == "3dnow") { 2935 setMMXLevel(Features, AMD3DNow, Enabled); 2936 } else if (Name == "3dnowa") { 2937 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2938 } else if (Name == "aes") { 2939 if (Enabled) 2940 setSSELevel(Features, SSE2, Enabled); 2941 } else if (Name == "pclmul") { 2942 if (Enabled) 2943 setSSELevel(Features, SSE2, Enabled); 2944 } else if (Name == "avx") { 2945 setSSELevel(Features, AVX, Enabled); 2946 } else if (Name == "avx2") { 2947 setSSELevel(Features, AVX2, Enabled); 2948 } else if (Name == "avx512f") { 2949 setSSELevel(Features, AVX512F, Enabled); 2950 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2951 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2952 if (Enabled) 2953 setSSELevel(Features, AVX512F, Enabled); 2954 } else if (Name == "fma") { 2955 if (Enabled) 2956 setSSELevel(Features, AVX, Enabled); 2957 } else if (Name == "fma4") { 2958 setXOPLevel(Features, FMA4, Enabled); 2959 } else if (Name == "xop") { 2960 setXOPLevel(Features, XOP, Enabled); 2961 } else if (Name == "sse4a") { 2962 setXOPLevel(Features, SSE4A, Enabled); 2963 } else if (Name == "f16c") { 2964 if (Enabled) 2965 setSSELevel(Features, AVX, Enabled); 2966 } else if (Name == "sha") { 2967 if (Enabled) 2968 setSSELevel(Features, SSE2, Enabled); 2969 } else if (Name == "sse4") { 2970 // We can get here via the __target__ attribute since that's not controlled 2971 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2972 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2973 // disabled. 2974 if (Enabled) 2975 setSSELevel(Features, SSE42, Enabled); 2976 else 2977 setSSELevel(Features, SSE41, Enabled); 2978 } else if (Name == "xsave") { 2979 if (Enabled) 2980 setSSELevel(Features, AVX, Enabled); 2981 else 2982 Features["xsaveopt"] = false; 2983 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2984 if (Enabled) { 2985 Features["xsave"] = true; 2986 setSSELevel(Features, AVX, Enabled); 2987 } 2988 } 2989 } 2990 2991 /// handleTargetFeatures - Perform initialization based on the user 2992 /// configured set of features. 2993 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2994 DiagnosticsEngine &Diags) { 2995 for (const auto &Feature : Features) { 2996 if (Feature[0] != '+') 2997 continue; 2998 2999 if (Feature == "+aes") { 3000 HasAES = true; 3001 } else if (Feature == "+pclmul") { 3002 HasPCLMUL = true; 3003 } else if (Feature == "+lzcnt") { 3004 HasLZCNT = true; 3005 } else if (Feature == "+rdrnd") { 3006 HasRDRND = true; 3007 } else if (Feature == "+fsgsbase") { 3008 HasFSGSBASE = true; 3009 } else if (Feature == "+bmi") { 3010 HasBMI = true; 3011 } else if (Feature == "+bmi2") { 3012 HasBMI2 = true; 3013 } else if (Feature == "+popcnt") { 3014 HasPOPCNT = true; 3015 } else if (Feature == "+rtm") { 3016 HasRTM = true; 3017 } else if (Feature == "+prfchw") { 3018 HasPRFCHW = true; 3019 } else if (Feature == "+rdseed") { 3020 HasRDSEED = true; 3021 } else if (Feature == "+adx") { 3022 HasADX = true; 3023 } else if (Feature == "+tbm") { 3024 HasTBM = true; 3025 } else if (Feature == "+fma") { 3026 HasFMA = true; 3027 } else if (Feature == "+f16c") { 3028 HasF16C = true; 3029 } else if (Feature == "+avx512cd") { 3030 HasAVX512CD = true; 3031 } else if (Feature == "+avx512er") { 3032 HasAVX512ER = true; 3033 } else if (Feature == "+avx512pf") { 3034 HasAVX512PF = true; 3035 } else if (Feature == "+avx512dq") { 3036 HasAVX512DQ = true; 3037 } else if (Feature == "+avx512bw") { 3038 HasAVX512BW = true; 3039 } else if (Feature == "+avx512vl") { 3040 HasAVX512VL = true; 3041 } else if (Feature == "+sha") { 3042 HasSHA = true; 3043 } else if (Feature == "+cx16") { 3044 HasCX16 = true; 3045 } else if (Feature == "+fxsr") { 3046 HasFXSR = true; 3047 } else if (Feature == "+xsave") { 3048 HasXSAVE = true; 3049 } else if (Feature == "+xsaveopt") { 3050 HasXSAVEOPT = true; 3051 } else if (Feature == "+xsavec") { 3052 HasXSAVEC = true; 3053 } else if (Feature == "+xsaves") { 3054 HasXSAVES = true; 3055 } else if (Feature == "+pku") { 3056 HasPKU = true; 3057 } 3058 3059 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3060 .Case("+avx512f", AVX512F) 3061 .Case("+avx2", AVX2) 3062 .Case("+avx", AVX) 3063 .Case("+sse4.2", SSE42) 3064 .Case("+sse4.1", SSE41) 3065 .Case("+ssse3", SSSE3) 3066 .Case("+sse3", SSE3) 3067 .Case("+sse2", SSE2) 3068 .Case("+sse", SSE1) 3069 .Default(NoSSE); 3070 SSELevel = std::max(SSELevel, Level); 3071 3072 MMX3DNowEnum ThreeDNowLevel = 3073 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3074 .Case("+3dnowa", AMD3DNowAthlon) 3075 .Case("+3dnow", AMD3DNow) 3076 .Case("+mmx", MMX) 3077 .Default(NoMMX3DNow); 3078 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3079 3080 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3081 .Case("+xop", XOP) 3082 .Case("+fma4", FMA4) 3083 .Case("+sse4a", SSE4A) 3084 .Default(NoXOP); 3085 XOPLevel = std::max(XOPLevel, XLevel); 3086 } 3087 3088 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3089 // matches the selected sse level. 3090 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3091 (FPMath == FP_387 && SSELevel >= SSE1)) { 3092 Diags.Report(diag::err_target_unsupported_fpmath) << 3093 (FPMath == FP_SSE ? "sse" : "387"); 3094 return false; 3095 } 3096 3097 SimdDefaultAlign = 3098 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3099 return true; 3100 } 3101 3102 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3103 /// definitions for this particular subtarget. 3104 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3105 MacroBuilder &Builder) const { 3106 // Target identification. 3107 if (getTriple().getArch() == llvm::Triple::x86_64) { 3108 Builder.defineMacro("__amd64__"); 3109 Builder.defineMacro("__amd64"); 3110 Builder.defineMacro("__x86_64"); 3111 Builder.defineMacro("__x86_64__"); 3112 if (getTriple().getArchName() == "x86_64h") { 3113 Builder.defineMacro("__x86_64h"); 3114 Builder.defineMacro("__x86_64h__"); 3115 } 3116 } else { 3117 DefineStd(Builder, "i386", Opts); 3118 } 3119 3120 // Subtarget options. 3121 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3122 // truly should be based on -mtune options. 3123 switch (CPU) { 3124 case CK_Generic: 3125 break; 3126 case CK_i386: 3127 // The rest are coming from the i386 define above. 3128 Builder.defineMacro("__tune_i386__"); 3129 break; 3130 case CK_i486: 3131 case CK_WinChipC6: 3132 case CK_WinChip2: 3133 case CK_C3: 3134 defineCPUMacros(Builder, "i486"); 3135 break; 3136 case CK_PentiumMMX: 3137 Builder.defineMacro("__pentium_mmx__"); 3138 Builder.defineMacro("__tune_pentium_mmx__"); 3139 // Fallthrough 3140 case CK_i586: 3141 case CK_Pentium: 3142 defineCPUMacros(Builder, "i586"); 3143 defineCPUMacros(Builder, "pentium"); 3144 break; 3145 case CK_Pentium3: 3146 case CK_Pentium3M: 3147 case CK_PentiumM: 3148 Builder.defineMacro("__tune_pentium3__"); 3149 // Fallthrough 3150 case CK_Pentium2: 3151 case CK_C3_2: 3152 Builder.defineMacro("__tune_pentium2__"); 3153 // Fallthrough 3154 case CK_PentiumPro: 3155 Builder.defineMacro("__tune_i686__"); 3156 Builder.defineMacro("__tune_pentiumpro__"); 3157 // Fallthrough 3158 case CK_i686: 3159 Builder.defineMacro("__i686"); 3160 Builder.defineMacro("__i686__"); 3161 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3162 Builder.defineMacro("__pentiumpro"); 3163 Builder.defineMacro("__pentiumpro__"); 3164 break; 3165 case CK_Pentium4: 3166 case CK_Pentium4M: 3167 defineCPUMacros(Builder, "pentium4"); 3168 break; 3169 case CK_Yonah: 3170 case CK_Prescott: 3171 case CK_Nocona: 3172 defineCPUMacros(Builder, "nocona"); 3173 break; 3174 case CK_Core2: 3175 case CK_Penryn: 3176 defineCPUMacros(Builder, "core2"); 3177 break; 3178 case CK_Bonnell: 3179 defineCPUMacros(Builder, "atom"); 3180 break; 3181 case CK_Silvermont: 3182 defineCPUMacros(Builder, "slm"); 3183 break; 3184 case CK_Nehalem: 3185 case CK_Westmere: 3186 case CK_SandyBridge: 3187 case CK_IvyBridge: 3188 case CK_Haswell: 3189 case CK_Broadwell: 3190 // FIXME: Historically, we defined this legacy name, it would be nice to 3191 // remove it at some point. We've never exposed fine-grained names for 3192 // recent primary x86 CPUs, and we should keep it that way. 3193 defineCPUMacros(Builder, "corei7"); 3194 break; 3195 case CK_Skylake: 3196 // FIXME: Historically, we defined this legacy name, it would be nice to 3197 // remove it at some point. This is the only fine-grained CPU macro in the 3198 // main intel CPU line, and it would be better to not have these and force 3199 // people to use ISA macros. 3200 defineCPUMacros(Builder, "skx"); 3201 break; 3202 case CK_KNL: 3203 defineCPUMacros(Builder, "knl"); 3204 break; 3205 case CK_K6_2: 3206 Builder.defineMacro("__k6_2__"); 3207 Builder.defineMacro("__tune_k6_2__"); 3208 // Fallthrough 3209 case CK_K6_3: 3210 if (CPU != CK_K6_2) { // In case of fallthrough 3211 // FIXME: GCC may be enabling these in cases where some other k6 3212 // architecture is specified but -m3dnow is explicitly provided. The 3213 // exact semantics need to be determined and emulated here. 3214 Builder.defineMacro("__k6_3__"); 3215 Builder.defineMacro("__tune_k6_3__"); 3216 } 3217 // Fallthrough 3218 case CK_K6: 3219 defineCPUMacros(Builder, "k6"); 3220 break; 3221 case CK_Athlon: 3222 case CK_AthlonThunderbird: 3223 case CK_Athlon4: 3224 case CK_AthlonXP: 3225 case CK_AthlonMP: 3226 defineCPUMacros(Builder, "athlon"); 3227 if (SSELevel != NoSSE) { 3228 Builder.defineMacro("__athlon_sse__"); 3229 Builder.defineMacro("__tune_athlon_sse__"); 3230 } 3231 break; 3232 case CK_K8: 3233 case CK_K8SSE3: 3234 case CK_x86_64: 3235 case CK_Opteron: 3236 case CK_OpteronSSE3: 3237 case CK_Athlon64: 3238 case CK_Athlon64SSE3: 3239 case CK_AthlonFX: 3240 defineCPUMacros(Builder, "k8"); 3241 break; 3242 case CK_AMDFAM10: 3243 defineCPUMacros(Builder, "amdfam10"); 3244 break; 3245 case CK_BTVER1: 3246 defineCPUMacros(Builder, "btver1"); 3247 break; 3248 case CK_BTVER2: 3249 defineCPUMacros(Builder, "btver2"); 3250 break; 3251 case CK_BDVER1: 3252 defineCPUMacros(Builder, "bdver1"); 3253 break; 3254 case CK_BDVER2: 3255 defineCPUMacros(Builder, "bdver2"); 3256 break; 3257 case CK_BDVER3: 3258 defineCPUMacros(Builder, "bdver3"); 3259 break; 3260 case CK_BDVER4: 3261 defineCPUMacros(Builder, "bdver4"); 3262 break; 3263 case CK_Geode: 3264 defineCPUMacros(Builder, "geode"); 3265 break; 3266 } 3267 3268 // Target properties. 3269 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3270 3271 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3272 // functions in glibc header files that use FP Stack inline asm which the 3273 // backend can't deal with (PR879). 3274 Builder.defineMacro("__NO_MATH_INLINES"); 3275 3276 if (HasAES) 3277 Builder.defineMacro("__AES__"); 3278 3279 if (HasPCLMUL) 3280 Builder.defineMacro("__PCLMUL__"); 3281 3282 if (HasLZCNT) 3283 Builder.defineMacro("__LZCNT__"); 3284 3285 if (HasRDRND) 3286 Builder.defineMacro("__RDRND__"); 3287 3288 if (HasFSGSBASE) 3289 Builder.defineMacro("__FSGSBASE__"); 3290 3291 if (HasBMI) 3292 Builder.defineMacro("__BMI__"); 3293 3294 if (HasBMI2) 3295 Builder.defineMacro("__BMI2__"); 3296 3297 if (HasPOPCNT) 3298 Builder.defineMacro("__POPCNT__"); 3299 3300 if (HasRTM) 3301 Builder.defineMacro("__RTM__"); 3302 3303 if (HasPRFCHW) 3304 Builder.defineMacro("__PRFCHW__"); 3305 3306 if (HasRDSEED) 3307 Builder.defineMacro("__RDSEED__"); 3308 3309 if (HasADX) 3310 Builder.defineMacro("__ADX__"); 3311 3312 if (HasTBM) 3313 Builder.defineMacro("__TBM__"); 3314 3315 switch (XOPLevel) { 3316 case XOP: 3317 Builder.defineMacro("__XOP__"); 3318 case FMA4: 3319 Builder.defineMacro("__FMA4__"); 3320 case SSE4A: 3321 Builder.defineMacro("__SSE4A__"); 3322 case NoXOP: 3323 break; 3324 } 3325 3326 if (HasFMA) 3327 Builder.defineMacro("__FMA__"); 3328 3329 if (HasF16C) 3330 Builder.defineMacro("__F16C__"); 3331 3332 if (HasAVX512CD) 3333 Builder.defineMacro("__AVX512CD__"); 3334 if (HasAVX512ER) 3335 Builder.defineMacro("__AVX512ER__"); 3336 if (HasAVX512PF) 3337 Builder.defineMacro("__AVX512PF__"); 3338 if (HasAVX512DQ) 3339 Builder.defineMacro("__AVX512DQ__"); 3340 if (HasAVX512BW) 3341 Builder.defineMacro("__AVX512BW__"); 3342 if (HasAVX512VL) 3343 Builder.defineMacro("__AVX512VL__"); 3344 3345 if (HasSHA) 3346 Builder.defineMacro("__SHA__"); 3347 3348 if (HasFXSR) 3349 Builder.defineMacro("__FXSR__"); 3350 if (HasXSAVE) 3351 Builder.defineMacro("__XSAVE__"); 3352 if (HasXSAVEOPT) 3353 Builder.defineMacro("__XSAVEOPT__"); 3354 if (HasXSAVEC) 3355 Builder.defineMacro("__XSAVEC__"); 3356 if (HasXSAVES) 3357 Builder.defineMacro("__XSAVES__"); 3358 if (HasPKU) 3359 Builder.defineMacro("__PKU__"); 3360 if (HasCX16) 3361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3362 3363 // Each case falls through to the previous one here. 3364 switch (SSELevel) { 3365 case AVX512F: 3366 Builder.defineMacro("__AVX512F__"); 3367 case AVX2: 3368 Builder.defineMacro("__AVX2__"); 3369 case AVX: 3370 Builder.defineMacro("__AVX__"); 3371 case SSE42: 3372 Builder.defineMacro("__SSE4_2__"); 3373 case SSE41: 3374 Builder.defineMacro("__SSE4_1__"); 3375 case SSSE3: 3376 Builder.defineMacro("__SSSE3__"); 3377 case SSE3: 3378 Builder.defineMacro("__SSE3__"); 3379 case SSE2: 3380 Builder.defineMacro("__SSE2__"); 3381 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3382 case SSE1: 3383 Builder.defineMacro("__SSE__"); 3384 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3385 case NoSSE: 3386 break; 3387 } 3388 3389 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3390 switch (SSELevel) { 3391 case AVX512F: 3392 case AVX2: 3393 case AVX: 3394 case SSE42: 3395 case SSE41: 3396 case SSSE3: 3397 case SSE3: 3398 case SSE2: 3399 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3400 break; 3401 case SSE1: 3402 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3403 break; 3404 default: 3405 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3406 } 3407 } 3408 3409 // Each case falls through to the previous one here. 3410 switch (MMX3DNowLevel) { 3411 case AMD3DNowAthlon: 3412 Builder.defineMacro("__3dNOW_A__"); 3413 case AMD3DNow: 3414 Builder.defineMacro("__3dNOW__"); 3415 case MMX: 3416 Builder.defineMacro("__MMX__"); 3417 case NoMMX3DNow: 3418 break; 3419 } 3420 3421 if (CPU >= CK_i486) { 3422 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3423 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3424 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3425 } 3426 if (CPU >= CK_i586) 3427 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3428 } 3429 3430 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3431 return llvm::StringSwitch<bool>(Feature) 3432 .Case("aes", HasAES) 3433 .Case("avx", SSELevel >= AVX) 3434 .Case("avx2", SSELevel >= AVX2) 3435 .Case("avx512f", SSELevel >= AVX512F) 3436 .Case("avx512cd", HasAVX512CD) 3437 .Case("avx512er", HasAVX512ER) 3438 .Case("avx512pf", HasAVX512PF) 3439 .Case("avx512dq", HasAVX512DQ) 3440 .Case("avx512bw", HasAVX512BW) 3441 .Case("avx512vl", HasAVX512VL) 3442 .Case("bmi", HasBMI) 3443 .Case("bmi2", HasBMI2) 3444 .Case("cx16", HasCX16) 3445 .Case("f16c", HasF16C) 3446 .Case("fma", HasFMA) 3447 .Case("fma4", XOPLevel >= FMA4) 3448 .Case("fsgsbase", HasFSGSBASE) 3449 .Case("fxsr", HasFXSR) 3450 .Case("lzcnt", HasLZCNT) 3451 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3452 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3453 .Case("mmx", MMX3DNowLevel >= MMX) 3454 .Case("pclmul", HasPCLMUL) 3455 .Case("popcnt", HasPOPCNT) 3456 .Case("prfchw", HasPRFCHW) 3457 .Case("rdrnd", HasRDRND) 3458 .Case("rdseed", HasRDSEED) 3459 .Case("rtm", HasRTM) 3460 .Case("sha", HasSHA) 3461 .Case("sse", SSELevel >= SSE1) 3462 .Case("sse2", SSELevel >= SSE2) 3463 .Case("sse3", SSELevel >= SSE3) 3464 .Case("ssse3", SSELevel >= SSSE3) 3465 .Case("sse4.1", SSELevel >= SSE41) 3466 .Case("sse4.2", SSELevel >= SSE42) 3467 .Case("sse4a", XOPLevel >= SSE4A) 3468 .Case("tbm", HasTBM) 3469 .Case("x86", true) 3470 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3471 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3472 .Case("xop", XOPLevel >= XOP) 3473 .Case("xsave", HasXSAVE) 3474 .Case("xsavec", HasXSAVEC) 3475 .Case("xsaves", HasXSAVES) 3476 .Case("xsaveopt", HasXSAVEOPT) 3477 .Case("pku", HasPKU) 3478 .Default(false); 3479 } 3480 3481 // We can't use a generic validation scheme for the features accepted here 3482 // versus subtarget features accepted in the target attribute because the 3483 // bitfield structure that's initialized in the runtime only supports the 3484 // below currently rather than the full range of subtarget features. (See 3485 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3486 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3487 return llvm::StringSwitch<bool>(FeatureStr) 3488 .Case("cmov", true) 3489 .Case("mmx", true) 3490 .Case("popcnt", true) 3491 .Case("sse", true) 3492 .Case("sse2", true) 3493 .Case("sse3", true) 3494 .Case("sse4.1", true) 3495 .Case("sse4.2", true) 3496 .Case("avx", true) 3497 .Case("avx2", true) 3498 .Case("sse4a", true) 3499 .Case("fma4", true) 3500 .Case("xop", true) 3501 .Case("fma", true) 3502 .Case("avx512f", true) 3503 .Case("bmi", true) 3504 .Case("bmi2", true) 3505 .Default(false); 3506 } 3507 3508 bool 3509 X86TargetInfo::validateAsmConstraint(const char *&Name, 3510 TargetInfo::ConstraintInfo &Info) const { 3511 switch (*Name) { 3512 default: return false; 3513 // Constant constraints. 3514 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3515 // instructions. 3516 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3517 // x86_64 instructions. 3518 case 's': 3519 Info.setRequiresImmediate(); 3520 return true; 3521 case 'I': 3522 Info.setRequiresImmediate(0, 31); 3523 return true; 3524 case 'J': 3525 Info.setRequiresImmediate(0, 63); 3526 return true; 3527 case 'K': 3528 Info.setRequiresImmediate(-128, 127); 3529 return true; 3530 case 'L': 3531 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3532 return true; 3533 case 'M': 3534 Info.setRequiresImmediate(0, 3); 3535 return true; 3536 case 'N': 3537 Info.setRequiresImmediate(0, 255); 3538 return true; 3539 case 'O': 3540 Info.setRequiresImmediate(0, 127); 3541 return true; 3542 // Register constraints. 3543 case 'Y': // 'Y' is the first character for several 2-character constraints. 3544 // Shift the pointer to the second character of the constraint. 3545 Name++; 3546 switch (*Name) { 3547 default: 3548 return false; 3549 case '0': // First SSE register. 3550 case 't': // Any SSE register, when SSE2 is enabled. 3551 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3552 case 'm': // Any MMX register, when inter-unit moves enabled. 3553 Info.setAllowsRegister(); 3554 return true; 3555 } 3556 case 'f': // Any x87 floating point stack register. 3557 // Constraint 'f' cannot be used for output operands. 3558 if (Info.ConstraintStr[0] == '=') 3559 return false; 3560 Info.setAllowsRegister(); 3561 return true; 3562 case 'a': // eax. 3563 case 'b': // ebx. 3564 case 'c': // ecx. 3565 case 'd': // edx. 3566 case 'S': // esi. 3567 case 'D': // edi. 3568 case 'A': // edx:eax. 3569 case 't': // Top of floating point stack. 3570 case 'u': // Second from top of floating point stack. 3571 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3572 case 'y': // Any MMX register. 3573 case 'x': // Any SSE register. 3574 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3575 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3576 case 'l': // "Index" registers: any general register that can be used as an 3577 // index in a base+index memory access. 3578 Info.setAllowsRegister(); 3579 return true; 3580 // Floating point constant constraints. 3581 case 'C': // SSE floating point constant. 3582 case 'G': // x87 floating point constant. 3583 return true; 3584 } 3585 } 3586 3587 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3588 unsigned Size) const { 3589 // Strip off constraint modifiers. 3590 while (Constraint[0] == '=' || 3591 Constraint[0] == '+' || 3592 Constraint[0] == '&') 3593 Constraint = Constraint.substr(1); 3594 3595 return validateOperandSize(Constraint, Size); 3596 } 3597 3598 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3599 unsigned Size) const { 3600 return validateOperandSize(Constraint, Size); 3601 } 3602 3603 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3604 unsigned Size) const { 3605 switch (Constraint[0]) { 3606 default: break; 3607 case 'y': 3608 return Size <= 64; 3609 case 'f': 3610 case 't': 3611 case 'u': 3612 return Size <= 128; 3613 case 'x': 3614 if (SSELevel >= AVX512F) 3615 // 512-bit zmm registers can be used if target supports AVX512F. 3616 return Size <= 512U; 3617 else if (SSELevel >= AVX) 3618 // 256-bit ymm registers can be used if target supports AVX. 3619 return Size <= 256U; 3620 return Size <= 128U; 3621 case 'Y': 3622 // 'Y' is the first character for several 2-character constraints. 3623 switch (Constraint[1]) { 3624 default: break; 3625 case 'm': 3626 // 'Ym' is synonymous with 'y'. 3627 return Size <= 64; 3628 case 'i': 3629 case 't': 3630 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3631 if (SSELevel >= AVX512F) 3632 return Size <= 512U; 3633 else if (SSELevel >= AVX) 3634 return Size <= 256U; 3635 return SSELevel >= SSE2 && Size <= 128U; 3636 } 3637 3638 } 3639 3640 return true; 3641 } 3642 3643 std::string 3644 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3645 switch (*Constraint) { 3646 case 'a': return std::string("{ax}"); 3647 case 'b': return std::string("{bx}"); 3648 case 'c': return std::string("{cx}"); 3649 case 'd': return std::string("{dx}"); 3650 case 'S': return std::string("{si}"); 3651 case 'D': return std::string("{di}"); 3652 case 'p': // address 3653 return std::string("im"); 3654 case 't': // top of floating point stack. 3655 return std::string("{st}"); 3656 case 'u': // second from top of floating point stack. 3657 return std::string("{st(1)}"); // second from top of floating point stack. 3658 default: 3659 return std::string(1, *Constraint); 3660 } 3661 } 3662 3663 // X86-32 generic target 3664 class X86_32TargetInfo : public X86TargetInfo { 3665 public: 3666 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3667 DoubleAlign = LongLongAlign = 32; 3668 LongDoubleWidth = 96; 3669 LongDoubleAlign = 32; 3670 SuitableAlign = 128; 3671 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3672 SizeType = UnsignedInt; 3673 PtrDiffType = SignedInt; 3674 IntPtrType = SignedInt; 3675 RegParmMax = 3; 3676 3677 // Use fpret for all types. 3678 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3679 (1 << TargetInfo::Double) | 3680 (1 << TargetInfo::LongDouble)); 3681 3682 // x86-32 has atomics up to 8 bytes 3683 // FIXME: Check that we actually have cmpxchg8b before setting 3684 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3685 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3686 } 3687 BuiltinVaListKind getBuiltinVaListKind() const override { 3688 return TargetInfo::CharPtrBuiltinVaList; 3689 } 3690 3691 int getEHDataRegisterNumber(unsigned RegNo) const override { 3692 if (RegNo == 0) return 0; 3693 if (RegNo == 1) return 2; 3694 return -1; 3695 } 3696 bool validateOperandSize(StringRef Constraint, 3697 unsigned Size) const override { 3698 switch (Constraint[0]) { 3699 default: break; 3700 case 'R': 3701 case 'q': 3702 case 'Q': 3703 case 'a': 3704 case 'b': 3705 case 'c': 3706 case 'd': 3707 case 'S': 3708 case 'D': 3709 return Size <= 32; 3710 case 'A': 3711 return Size <= 64; 3712 } 3713 3714 return X86TargetInfo::validateOperandSize(Constraint, Size); 3715 } 3716 }; 3717 3718 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3719 public: 3720 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3721 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3722 3723 unsigned getFloatEvalMethod() const override { 3724 unsigned Major, Minor, Micro; 3725 getTriple().getOSVersion(Major, Minor, Micro); 3726 // New NetBSD uses the default rounding mode. 3727 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3728 return X86_32TargetInfo::getFloatEvalMethod(); 3729 // NetBSD before 6.99.26 defaults to "double" rounding. 3730 return 1; 3731 } 3732 }; 3733 3734 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3735 public: 3736 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3737 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3738 SizeType = UnsignedLong; 3739 IntPtrType = SignedLong; 3740 PtrDiffType = SignedLong; 3741 } 3742 }; 3743 3744 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3745 public: 3746 BitrigI386TargetInfo(const llvm::Triple &Triple) 3747 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3748 SizeType = UnsignedLong; 3749 IntPtrType = SignedLong; 3750 PtrDiffType = SignedLong; 3751 } 3752 }; 3753 3754 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3755 public: 3756 DarwinI386TargetInfo(const llvm::Triple &Triple) 3757 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3758 LongDoubleWidth = 128; 3759 LongDoubleAlign = 128; 3760 SuitableAlign = 128; 3761 MaxVectorAlign = 256; 3762 // The watchOS simulator uses the builtin bool type for Objective-C. 3763 llvm::Triple T = llvm::Triple(Triple); 3764 if (T.isWatchOS()) 3765 UseSignedCharForObjCBool = false; 3766 SizeType = UnsignedLong; 3767 IntPtrType = SignedLong; 3768 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3769 HasAlignMac68kSupport = true; 3770 } 3771 3772 bool handleTargetFeatures(std::vector<std::string> &Features, 3773 DiagnosticsEngine &Diags) override { 3774 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3775 Diags)) 3776 return false; 3777 // We now know the features we have: we can decide how to align vectors. 3778 MaxVectorAlign = 3779 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3780 return true; 3781 } 3782 }; 3783 3784 // x86-32 Windows target 3785 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3786 public: 3787 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3788 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3789 WCharType = UnsignedShort; 3790 DoubleAlign = LongLongAlign = 64; 3791 bool IsWinCOFF = 3792 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3793 DataLayoutString = IsWinCOFF 3794 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3795 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3796 } 3797 void getTargetDefines(const LangOptions &Opts, 3798 MacroBuilder &Builder) const override { 3799 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3800 } 3801 }; 3802 3803 // x86-32 Windows Visual Studio target 3804 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3805 public: 3806 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3807 : WindowsX86_32TargetInfo(Triple) { 3808 LongDoubleWidth = LongDoubleAlign = 64; 3809 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3810 } 3811 void getTargetDefines(const LangOptions &Opts, 3812 MacroBuilder &Builder) const override { 3813 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3814 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3815 // The value of the following reflects processor type. 3816 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3817 // We lost the original triple, so we use the default. 3818 Builder.defineMacro("_M_IX86", "600"); 3819 } 3820 }; 3821 3822 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3823 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3824 // supports __declspec natively under -fms-extensions, but we define a no-op 3825 // __declspec macro anyway for pre-processor compatibility. 3826 if (Opts.MicrosoftExt) 3827 Builder.defineMacro("__declspec", "__declspec"); 3828 else 3829 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3830 3831 if (!Opts.MicrosoftExt) { 3832 // Provide macros for all the calling convention keywords. Provide both 3833 // single and double underscore prefixed variants. These are available on 3834 // x64 as well as x86, even though they have no effect. 3835 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3836 for (const char *CC : CCs) { 3837 std::string GCCSpelling = "__attribute__((__"; 3838 GCCSpelling += CC; 3839 GCCSpelling += "__))"; 3840 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3841 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3842 } 3843 } 3844 } 3845 3846 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3847 Builder.defineMacro("__MSVCRT__"); 3848 Builder.defineMacro("__MINGW32__"); 3849 addCygMingDefines(Opts, Builder); 3850 } 3851 3852 // x86-32 MinGW target 3853 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3854 public: 3855 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3856 : WindowsX86_32TargetInfo(Triple) {} 3857 void getTargetDefines(const LangOptions &Opts, 3858 MacroBuilder &Builder) const override { 3859 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3860 DefineStd(Builder, "WIN32", Opts); 3861 DefineStd(Builder, "WINNT", Opts); 3862 Builder.defineMacro("_X86_"); 3863 addMinGWDefines(Opts, Builder); 3864 } 3865 }; 3866 3867 // x86-32 Cygwin target 3868 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3869 public: 3870 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3871 : X86_32TargetInfo(Triple) { 3872 WCharType = UnsignedShort; 3873 DoubleAlign = LongLongAlign = 64; 3874 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3875 } 3876 void getTargetDefines(const LangOptions &Opts, 3877 MacroBuilder &Builder) const override { 3878 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3879 Builder.defineMacro("_X86_"); 3880 Builder.defineMacro("__CYGWIN__"); 3881 Builder.defineMacro("__CYGWIN32__"); 3882 addCygMingDefines(Opts, Builder); 3883 DefineStd(Builder, "unix", Opts); 3884 if (Opts.CPlusPlus) 3885 Builder.defineMacro("_GNU_SOURCE"); 3886 } 3887 }; 3888 3889 // x86-32 Haiku target 3890 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3891 public: 3892 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3893 SizeType = UnsignedLong; 3894 IntPtrType = SignedLong; 3895 PtrDiffType = SignedLong; 3896 ProcessIDType = SignedLong; 3897 this->UserLabelPrefix = ""; 3898 this->TLSSupported = false; 3899 } 3900 void getTargetDefines(const LangOptions &Opts, 3901 MacroBuilder &Builder) const override { 3902 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3903 Builder.defineMacro("__INTEL__"); 3904 Builder.defineMacro("__HAIKU__"); 3905 } 3906 }; 3907 3908 // X86-32 MCU target 3909 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3910 public: 3911 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3912 LongDoubleWidth = 64; 3913 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3914 DataLayoutString = 3915 "e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"; 3916 UserLabelPrefix = ""; 3917 WIntType = UnsignedInt; 3918 } 3919 3920 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3921 // On MCU we support only C calling convention. 3922 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3923 } 3924 3925 void getTargetDefines(const LangOptions &Opts, 3926 MacroBuilder &Builder) const override { 3927 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3928 Builder.defineMacro("__iamcu"); 3929 Builder.defineMacro("__iamcu__"); 3930 } 3931 3932 bool allowsLargerPreferedTypeAlignment() const override { 3933 return false; 3934 } 3935 }; 3936 3937 // RTEMS Target 3938 template<typename Target> 3939 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3940 protected: 3941 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3942 MacroBuilder &Builder) const override { 3943 // RTEMS defines; list based off of gcc output 3944 3945 Builder.defineMacro("__rtems__"); 3946 Builder.defineMacro("__ELF__"); 3947 } 3948 3949 public: 3950 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3951 this->UserLabelPrefix = ""; 3952 3953 switch (Triple.getArch()) { 3954 default: 3955 case llvm::Triple::x86: 3956 // this->MCountName = ".mcount"; 3957 break; 3958 case llvm::Triple::mips: 3959 case llvm::Triple::mipsel: 3960 case llvm::Triple::ppc: 3961 case llvm::Triple::ppc64: 3962 case llvm::Triple::ppc64le: 3963 // this->MCountName = "_mcount"; 3964 break; 3965 case llvm::Triple::arm: 3966 // this->MCountName = "__mcount"; 3967 break; 3968 } 3969 } 3970 }; 3971 3972 // x86-32 RTEMS target 3973 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3974 public: 3975 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3976 SizeType = UnsignedLong; 3977 IntPtrType = SignedLong; 3978 PtrDiffType = SignedLong; 3979 this->UserLabelPrefix = ""; 3980 } 3981 void getTargetDefines(const LangOptions &Opts, 3982 MacroBuilder &Builder) const override { 3983 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3984 Builder.defineMacro("__INTEL__"); 3985 Builder.defineMacro("__rtems__"); 3986 } 3987 }; 3988 3989 // x86-64 generic target 3990 class X86_64TargetInfo : public X86TargetInfo { 3991 public: 3992 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3993 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3994 bool IsWinCOFF = 3995 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3996 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3997 LongDoubleWidth = 128; 3998 LongDoubleAlign = 128; 3999 LargeArrayMinWidth = 128; 4000 LargeArrayAlign = 128; 4001 SuitableAlign = 128; 4002 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4003 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4004 IntPtrType = IsX32 ? SignedInt : SignedLong; 4005 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4006 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4007 RegParmMax = 6; 4008 4009 // Pointers are 32-bit in x32. 4010 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4011 : IsWinCOFF 4012 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4013 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 4014 4015 // Use fpret only for long double. 4016 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4017 4018 // Use fp2ret for _Complex long double. 4019 ComplexLongDoubleUsesFP2Ret = true; 4020 4021 // Make __builtin_ms_va_list available. 4022 HasBuiltinMSVaList = true; 4023 4024 // x86-64 has atomics up to 16 bytes. 4025 MaxAtomicPromoteWidth = 128; 4026 MaxAtomicInlineWidth = 128; 4027 } 4028 BuiltinVaListKind getBuiltinVaListKind() const override { 4029 return TargetInfo::X86_64ABIBuiltinVaList; 4030 } 4031 4032 int getEHDataRegisterNumber(unsigned RegNo) const override { 4033 if (RegNo == 0) return 0; 4034 if (RegNo == 1) return 1; 4035 return -1; 4036 } 4037 4038 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4039 return (CC == CC_C || 4040 CC == CC_X86VectorCall || 4041 CC == CC_IntelOclBicc || 4042 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4043 } 4044 4045 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4046 return CC_C; 4047 } 4048 4049 // for x32 we need it here explicitly 4050 bool hasInt128Type() const override { return true; } 4051 unsigned getUnwindWordWidth() const override { return 64; } 4052 unsigned getRegisterWidth() const override { return 64; } 4053 4054 bool validateGlobalRegisterVariable(StringRef RegName, 4055 unsigned RegSize, 4056 bool &HasSizeMismatch) const override { 4057 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4058 // handle. 4059 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4060 // Check that the register size is 64-bit. 4061 HasSizeMismatch = RegSize != 64; 4062 return true; 4063 } 4064 4065 // Check if the register is a 32-bit register the backend can handle. 4066 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4067 HasSizeMismatch); 4068 } 4069 }; 4070 4071 // x86-64 Windows target 4072 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4073 public: 4074 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4075 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4076 WCharType = UnsignedShort; 4077 LongWidth = LongAlign = 32; 4078 DoubleAlign = LongLongAlign = 64; 4079 IntMaxType = SignedLongLong; 4080 Int64Type = SignedLongLong; 4081 SizeType = UnsignedLongLong; 4082 PtrDiffType = SignedLongLong; 4083 IntPtrType = SignedLongLong; 4084 this->UserLabelPrefix = ""; 4085 } 4086 4087 void getTargetDefines(const LangOptions &Opts, 4088 MacroBuilder &Builder) const override { 4089 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4090 Builder.defineMacro("_WIN64"); 4091 } 4092 4093 BuiltinVaListKind getBuiltinVaListKind() const override { 4094 return TargetInfo::CharPtrBuiltinVaList; 4095 } 4096 4097 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4098 switch (CC) { 4099 case CC_X86StdCall: 4100 case CC_X86ThisCall: 4101 case CC_X86FastCall: 4102 return CCCR_Ignore; 4103 case CC_C: 4104 case CC_X86VectorCall: 4105 case CC_IntelOclBicc: 4106 case CC_X86_64SysV: 4107 return CCCR_OK; 4108 default: 4109 return CCCR_Warning; 4110 } 4111 } 4112 }; 4113 4114 // x86-64 Windows Visual Studio target 4115 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4116 public: 4117 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4118 : WindowsX86_64TargetInfo(Triple) { 4119 LongDoubleWidth = LongDoubleAlign = 64; 4120 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4121 } 4122 void getTargetDefines(const LangOptions &Opts, 4123 MacroBuilder &Builder) const override { 4124 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4125 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4126 Builder.defineMacro("_M_X64", "100"); 4127 Builder.defineMacro("_M_AMD64", "100"); 4128 } 4129 }; 4130 4131 // x86-64 MinGW target 4132 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4133 public: 4134 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4135 : WindowsX86_64TargetInfo(Triple) { 4136 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4137 // with x86 FP ops. Weird. 4138 LongDoubleWidth = LongDoubleAlign = 128; 4139 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4140 } 4141 4142 void getTargetDefines(const LangOptions &Opts, 4143 MacroBuilder &Builder) const override { 4144 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4145 DefineStd(Builder, "WIN64", Opts); 4146 Builder.defineMacro("__MINGW64__"); 4147 addMinGWDefines(Opts, Builder); 4148 4149 // GCC defines this macro when it is using __gxx_personality_seh0. 4150 if (!Opts.SjLjExceptions) 4151 Builder.defineMacro("__SEH__"); 4152 } 4153 }; 4154 4155 // x86-64 Cygwin target 4156 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4157 public: 4158 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4159 : X86_64TargetInfo(Triple) { 4160 TLSSupported = false; 4161 WCharType = UnsignedShort; 4162 } 4163 void getTargetDefines(const LangOptions &Opts, 4164 MacroBuilder &Builder) const override { 4165 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4166 Builder.defineMacro("__x86_64__"); 4167 Builder.defineMacro("__CYGWIN__"); 4168 Builder.defineMacro("__CYGWIN64__"); 4169 addCygMingDefines(Opts, Builder); 4170 DefineStd(Builder, "unix", Opts); 4171 if (Opts.CPlusPlus) 4172 Builder.defineMacro("_GNU_SOURCE"); 4173 4174 // GCC defines this macro when it is using __gxx_personality_seh0. 4175 if (!Opts.SjLjExceptions) 4176 Builder.defineMacro("__SEH__"); 4177 } 4178 }; 4179 4180 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4181 public: 4182 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4183 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4184 Int64Type = SignedLongLong; 4185 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4186 llvm::Triple T = llvm::Triple(Triple); 4187 if (T.isiOS()) 4188 UseSignedCharForObjCBool = false; 4189 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4190 } 4191 4192 bool handleTargetFeatures(std::vector<std::string> &Features, 4193 DiagnosticsEngine &Diags) override { 4194 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4195 Diags)) 4196 return false; 4197 // We now know the features we have: we can decide how to align vectors. 4198 MaxVectorAlign = 4199 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4200 return true; 4201 } 4202 }; 4203 4204 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4205 public: 4206 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4207 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4208 IntMaxType = SignedLongLong; 4209 Int64Type = SignedLongLong; 4210 } 4211 }; 4212 4213 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4214 public: 4215 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4216 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4217 IntMaxType = SignedLongLong; 4218 Int64Type = SignedLongLong; 4219 } 4220 }; 4221 4222 class ARMTargetInfo : public TargetInfo { 4223 // Possible FPU choices. 4224 enum FPUMode { 4225 VFP2FPU = (1 << 0), 4226 VFP3FPU = (1 << 1), 4227 VFP4FPU = (1 << 2), 4228 NeonFPU = (1 << 3), 4229 FPARMV8 = (1 << 4) 4230 }; 4231 4232 // Possible HWDiv features. 4233 enum HWDivMode { 4234 HWDivThumb = (1 << 0), 4235 HWDivARM = (1 << 1) 4236 }; 4237 4238 static bool FPUModeIsVFP(FPUMode Mode) { 4239 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4240 } 4241 4242 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4243 static const char * const GCCRegNames[]; 4244 4245 std::string ABI, CPU; 4246 4247 StringRef CPUProfile; 4248 StringRef CPUAttr; 4249 4250 enum { 4251 FP_Default, 4252 FP_VFP, 4253 FP_Neon 4254 } FPMath; 4255 4256 unsigned ArchISA; 4257 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4258 unsigned ArchProfile; 4259 unsigned ArchVersion; 4260 4261 unsigned FPU : 5; 4262 4263 unsigned IsAAPCS : 1; 4264 unsigned HWDiv : 2; 4265 4266 // Initialized via features. 4267 unsigned SoftFloat : 1; 4268 unsigned SoftFloatABI : 1; 4269 4270 unsigned CRC : 1; 4271 unsigned Crypto : 1; 4272 unsigned DSP : 1; 4273 unsigned Unaligned : 1; 4274 4275 enum { 4276 LDREX_B = (1 << 0), /// byte (8-bit) 4277 LDREX_H = (1 << 1), /// half (16-bit) 4278 LDREX_W = (1 << 2), /// word (32-bit) 4279 LDREX_D = (1 << 3), /// double (64-bit) 4280 }; 4281 4282 uint32_t LDREX; 4283 4284 // ACLE 6.5.1 Hardware floating point 4285 enum { 4286 HW_FP_HP = (1 << 1), /// half (16-bit) 4287 HW_FP_SP = (1 << 2), /// single (32-bit) 4288 HW_FP_DP = (1 << 3), /// double (64-bit) 4289 }; 4290 uint32_t HW_FP; 4291 4292 static const Builtin::Info BuiltinInfo[]; 4293 4294 void setABIAAPCS() { 4295 IsAAPCS = true; 4296 4297 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4298 const llvm::Triple &T = getTriple(); 4299 4300 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4301 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4302 T.getOS() == llvm::Triple::Bitrig) 4303 SizeType = UnsignedLong; 4304 else 4305 SizeType = UnsignedInt; 4306 4307 switch (T.getOS()) { 4308 case llvm::Triple::NetBSD: 4309 WCharType = SignedInt; 4310 break; 4311 case llvm::Triple::Win32: 4312 WCharType = UnsignedShort; 4313 break; 4314 case llvm::Triple::Linux: 4315 default: 4316 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4317 WCharType = UnsignedInt; 4318 break; 4319 } 4320 4321 UseBitFieldTypeAlignment = true; 4322 4323 ZeroLengthBitfieldBoundary = 0; 4324 4325 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4326 // so set preferred for small types to 32. 4327 if (T.isOSBinFormatMachO()) { 4328 DataLayoutString = 4329 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4330 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4331 } else if (T.isOSWindows()) { 4332 assert(!BigEndian && "Windows on ARM does not support big endian"); 4333 DataLayoutString = "e" 4334 "-m:w" 4335 "-p:32:32" 4336 "-i64:64" 4337 "-v128:64:128" 4338 "-a:0:32" 4339 "-n32" 4340 "-S64"; 4341 } else if (T.isOSNaCl()) { 4342 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4343 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4344 } else { 4345 DataLayoutString = 4346 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4347 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4348 } 4349 4350 // FIXME: Enumerated types are variable width in straight AAPCS. 4351 } 4352 4353 void setABIAPCS(bool IsAAPCS16) { 4354 const llvm::Triple &T = getTriple(); 4355 4356 IsAAPCS = false; 4357 4358 if (IsAAPCS16) 4359 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4360 else 4361 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4362 4363 // size_t is unsigned int on FreeBSD. 4364 if (T.getOS() == llvm::Triple::FreeBSD) 4365 SizeType = UnsignedInt; 4366 else 4367 SizeType = UnsignedLong; 4368 4369 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4370 WCharType = SignedInt; 4371 4372 // Do not respect the alignment of bit-field types when laying out 4373 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4374 UseBitFieldTypeAlignment = false; 4375 4376 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4377 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4378 /// gcc. 4379 ZeroLengthBitfieldBoundary = 32; 4380 4381 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4382 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4383 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4384 } else if (T.isOSBinFormatMachO()) 4385 DataLayoutString = 4386 BigEndian 4387 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4388 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4389 else 4390 DataLayoutString = 4391 BigEndian 4392 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4393 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4394 4395 // FIXME: Override "preferred align" for double and long long. 4396 } 4397 4398 void setArchInfo() { 4399 StringRef ArchName = getTriple().getArchName(); 4400 4401 ArchISA = llvm::ARM::parseArchISA(ArchName); 4402 CPU = llvm::ARM::getDefaultCPU(ArchName); 4403 unsigned AK = llvm::ARM::parseArch(ArchName); 4404 if (AK != llvm::ARM::AK_INVALID) 4405 ArchKind = AK; 4406 setArchInfo(ArchKind); 4407 } 4408 4409 void setArchInfo(unsigned Kind) { 4410 StringRef SubArch; 4411 4412 // cache TargetParser info 4413 ArchKind = Kind; 4414 SubArch = llvm::ARM::getSubArch(ArchKind); 4415 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4416 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4417 4418 // cache CPU related strings 4419 CPUAttr = getCPUAttr(); 4420 CPUProfile = getCPUProfile(); 4421 } 4422 4423 void setAtomic() { 4424 // when triple does not specify a sub arch, 4425 // then we are not using inline atomics 4426 bool ShouldUseInlineAtomic = 4427 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4428 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4429 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4430 if (ArchProfile == llvm::ARM::PK_M) { 4431 MaxAtomicPromoteWidth = 32; 4432 if (ShouldUseInlineAtomic) 4433 MaxAtomicInlineWidth = 32; 4434 } 4435 else { 4436 MaxAtomicPromoteWidth = 64; 4437 if (ShouldUseInlineAtomic) 4438 MaxAtomicInlineWidth = 64; 4439 } 4440 } 4441 4442 bool isThumb() const { 4443 return (ArchISA == llvm::ARM::IK_THUMB); 4444 } 4445 4446 bool supportsThumb() const { 4447 return CPUAttr.count('T') || ArchVersion >= 6; 4448 } 4449 4450 bool supportsThumb2() const { 4451 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4452 } 4453 4454 StringRef getCPUAttr() const { 4455 // For most sub-arches, the build attribute CPU name is enough. 4456 // For Cortex variants, it's slightly different. 4457 switch(ArchKind) { 4458 default: 4459 return llvm::ARM::getCPUAttr(ArchKind); 4460 case llvm::ARM::AK_ARMV6M: 4461 return "6M"; 4462 case llvm::ARM::AK_ARMV7S: 4463 return "7S"; 4464 case llvm::ARM::AK_ARMV7A: 4465 return "7A"; 4466 case llvm::ARM::AK_ARMV7R: 4467 return "7R"; 4468 case llvm::ARM::AK_ARMV7M: 4469 return "7M"; 4470 case llvm::ARM::AK_ARMV7EM: 4471 return "7EM"; 4472 case llvm::ARM::AK_ARMV8A: 4473 return "8A"; 4474 case llvm::ARM::AK_ARMV8_1A: 4475 return "8_1A"; 4476 case llvm::ARM::AK_ARMV8_2A: 4477 return "8_2A"; 4478 } 4479 } 4480 4481 StringRef getCPUProfile() const { 4482 switch(ArchProfile) { 4483 case llvm::ARM::PK_A: 4484 return "A"; 4485 case llvm::ARM::PK_R: 4486 return "R"; 4487 case llvm::ARM::PK_M: 4488 return "M"; 4489 default: 4490 return ""; 4491 } 4492 } 4493 4494 public: 4495 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4496 : TargetInfo(Triple), FPMath(FP_Default), 4497 IsAAPCS(true), LDREX(0), HW_FP(0) { 4498 BigEndian = IsBigEndian; 4499 4500 switch (getTriple().getOS()) { 4501 case llvm::Triple::NetBSD: 4502 PtrDiffType = SignedLong; 4503 break; 4504 default: 4505 PtrDiffType = SignedInt; 4506 break; 4507 } 4508 4509 // Cache arch related info. 4510 setArchInfo(); 4511 4512 // {} in inline assembly are neon specifiers, not assembly variant 4513 // specifiers. 4514 NoAsmVariants = true; 4515 4516 // FIXME: This duplicates code from the driver that sets the -target-abi 4517 // option - this code is used if -target-abi isn't passed and should 4518 // be unified in some way. 4519 if (Triple.isOSBinFormatMachO()) { 4520 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4521 // the frontend matches that. 4522 if (Triple.getEnvironment() == llvm::Triple::EABI || 4523 Triple.getOS() == llvm::Triple::UnknownOS || 4524 StringRef(CPU).startswith("cortex-m")) { 4525 setABI("aapcs"); 4526 } else if (Triple.isWatchABI()) { 4527 setABI("aapcs16"); 4528 } else { 4529 setABI("apcs-gnu"); 4530 } 4531 } else if (Triple.isOSWindows()) { 4532 // FIXME: this is invalid for WindowsCE 4533 setABI("aapcs"); 4534 } else { 4535 // Select the default based on the platform. 4536 switch (Triple.getEnvironment()) { 4537 case llvm::Triple::Android: 4538 case llvm::Triple::GNUEABI: 4539 case llvm::Triple::GNUEABIHF: 4540 setABI("aapcs-linux"); 4541 break; 4542 case llvm::Triple::EABIHF: 4543 case llvm::Triple::EABI: 4544 setABI("aapcs"); 4545 break; 4546 case llvm::Triple::GNU: 4547 setABI("apcs-gnu"); 4548 break; 4549 default: 4550 if (Triple.getOS() == llvm::Triple::NetBSD) 4551 setABI("apcs-gnu"); 4552 else 4553 setABI("aapcs"); 4554 break; 4555 } 4556 } 4557 4558 // ARM targets default to using the ARM C++ ABI. 4559 TheCXXABI.set(TargetCXXABI::GenericARM); 4560 4561 // ARM has atomics up to 8 bytes 4562 setAtomic(); 4563 4564 // Do force alignment of members that follow zero length bitfields. If 4565 // the alignment of the zero-length bitfield is greater than the member 4566 // that follows it, `bar', `bar' will be aligned as the type of the 4567 // zero length bitfield. 4568 UseZeroLengthBitfieldAlignment = true; 4569 } 4570 4571 StringRef getABI() const override { return ABI; } 4572 4573 bool setABI(const std::string &Name) override { 4574 ABI = Name; 4575 4576 // The defaults (above) are for AAPCS, check if we need to change them. 4577 // 4578 // FIXME: We need support for -meabi... we could just mangle it into the 4579 // name. 4580 if (Name == "apcs-gnu" || Name == "aapcs16") { 4581 setABIAPCS(Name == "aapcs16"); 4582 return true; 4583 } 4584 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4585 setABIAAPCS(); 4586 return true; 4587 } 4588 return false; 4589 } 4590 4591 // FIXME: This should be based on Arch attributes, not CPU names. 4592 bool 4593 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4594 StringRef CPU, 4595 const std::vector<std::string> &FeaturesVec) const override { 4596 4597 std::vector<const char*> TargetFeatures; 4598 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4599 4600 // get default FPU features 4601 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4602 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4603 4604 // get default Extension features 4605 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4606 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4607 4608 for (const char *Feature : TargetFeatures) 4609 if (Feature[0] == '+') 4610 Features[Feature+1] = true; 4611 4612 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4613 } 4614 4615 bool handleTargetFeatures(std::vector<std::string> &Features, 4616 DiagnosticsEngine &Diags) override { 4617 FPU = 0; 4618 CRC = 0; 4619 Crypto = 0; 4620 DSP = 0; 4621 Unaligned = 1; 4622 SoftFloat = SoftFloatABI = false; 4623 HWDiv = 0; 4624 4625 // This does not diagnose illegal cases like having both 4626 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4627 uint32_t HW_FP_remove = 0; 4628 for (const auto &Feature : Features) { 4629 if (Feature == "+soft-float") { 4630 SoftFloat = true; 4631 } else if (Feature == "+soft-float-abi") { 4632 SoftFloatABI = true; 4633 } else if (Feature == "+vfp2") { 4634 FPU |= VFP2FPU; 4635 HW_FP |= HW_FP_SP | HW_FP_DP; 4636 } else if (Feature == "+vfp3") { 4637 FPU |= VFP3FPU; 4638 HW_FP |= HW_FP_SP | HW_FP_DP; 4639 } else if (Feature == "+vfp4") { 4640 FPU |= VFP4FPU; 4641 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4642 } else if (Feature == "+fp-armv8") { 4643 FPU |= FPARMV8; 4644 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4645 } else if (Feature == "+neon") { 4646 FPU |= NeonFPU; 4647 HW_FP |= HW_FP_SP | HW_FP_DP; 4648 } else if (Feature == "+hwdiv") { 4649 HWDiv |= HWDivThumb; 4650 } else if (Feature == "+hwdiv-arm") { 4651 HWDiv |= HWDivARM; 4652 } else if (Feature == "+crc") { 4653 CRC = 1; 4654 } else if (Feature == "+crypto") { 4655 Crypto = 1; 4656 } else if (Feature == "+dsp") { 4657 DSP = 1; 4658 } else if (Feature == "+fp-only-sp") { 4659 HW_FP_remove |= HW_FP_DP; 4660 } else if (Feature == "+strict-align") { 4661 Unaligned = 0; 4662 } else if (Feature == "+fp16") { 4663 HW_FP |= HW_FP_HP; 4664 } 4665 } 4666 HW_FP &= ~HW_FP_remove; 4667 4668 switch (ArchVersion) { 4669 case 6: 4670 if (ArchProfile == llvm::ARM::PK_M) 4671 LDREX = 0; 4672 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4673 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4674 else 4675 LDREX = LDREX_W; 4676 break; 4677 case 7: 4678 if (ArchProfile == llvm::ARM::PK_M) 4679 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4680 else 4681 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4682 break; 4683 case 8: 4684 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4685 } 4686 4687 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4688 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4689 return false; 4690 } 4691 4692 if (FPMath == FP_Neon) 4693 Features.push_back("+neonfp"); 4694 else if (FPMath == FP_VFP) 4695 Features.push_back("-neonfp"); 4696 4697 // Remove front-end specific options which the backend handles differently. 4698 auto Feature = 4699 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4700 if (Feature != Features.end()) 4701 Features.erase(Feature); 4702 4703 return true; 4704 } 4705 4706 bool hasFeature(StringRef Feature) const override { 4707 return llvm::StringSwitch<bool>(Feature) 4708 .Case("arm", true) 4709 .Case("aarch32", true) 4710 .Case("softfloat", SoftFloat) 4711 .Case("thumb", isThumb()) 4712 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4713 .Case("hwdiv", HWDiv & HWDivThumb) 4714 .Case("hwdiv-arm", HWDiv & HWDivARM) 4715 .Default(false); 4716 } 4717 4718 bool setCPU(const std::string &Name) override { 4719 if (Name != "generic") 4720 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4721 4722 if (ArchKind == llvm::ARM::AK_INVALID) 4723 return false; 4724 setAtomic(); 4725 CPU = Name; 4726 return true; 4727 } 4728 4729 bool setFPMath(StringRef Name) override; 4730 4731 void getTargetDefines(const LangOptions &Opts, 4732 MacroBuilder &Builder) const override { 4733 // Target identification. 4734 Builder.defineMacro("__arm"); 4735 Builder.defineMacro("__arm__"); 4736 4737 // Target properties. 4738 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4739 4740 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4741 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4742 if (getTriple().isWatchABI()) 4743 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4744 4745 if (!CPUAttr.empty()) 4746 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4747 4748 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4749 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4750 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4751 4752 if (ArchVersion >= 8) { 4753 // ACLE 6.5.7 Crypto Extension 4754 if (Crypto) 4755 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4756 // ACLE 6.5.8 CRC32 Extension 4757 if (CRC) 4758 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4759 // ACLE 6.5.10 Numeric Maximum and Minimum 4760 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4761 // ACLE 6.5.9 Directed Rounding 4762 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4763 } 4764 4765 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4766 // is not defined for the M-profile. 4767 // NOTE that the deffault profile is assumed to be 'A' 4768 if (CPUProfile.empty() || CPUProfile != "M") 4769 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4770 4771 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4772 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4773 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4774 if (supportsThumb2()) 4775 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4776 else if (supportsThumb()) 4777 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4778 4779 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4780 // instruction set such as ARM or Thumb. 4781 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4782 4783 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4784 4785 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4786 if (!CPUProfile.empty()) 4787 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4788 4789 // ACLE 6.4.3 Unaligned access supported in hardware 4790 if (Unaligned) 4791 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4792 4793 // ACLE 6.4.4 LDREX/STREX 4794 if (LDREX) 4795 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4796 4797 // ACLE 6.4.5 CLZ 4798 if (ArchVersion == 5 || 4799 (ArchVersion == 6 && CPUProfile != "M") || 4800 ArchVersion > 6) 4801 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4802 4803 // ACLE 6.5.1 Hardware Floating Point 4804 if (HW_FP) 4805 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4806 4807 // ACLE predefines. 4808 Builder.defineMacro("__ARM_ACLE", "200"); 4809 4810 // FP16 support (we currently only support IEEE format). 4811 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4812 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4813 4814 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4815 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4816 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4817 4818 // Subtarget options. 4819 4820 // FIXME: It's more complicated than this and we don't really support 4821 // interworking. 4822 // Windows on ARM does not "support" interworking 4823 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4824 Builder.defineMacro("__THUMB_INTERWORK__"); 4825 4826 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4827 // Embedded targets on Darwin follow AAPCS, but not EABI. 4828 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4829 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4830 Builder.defineMacro("__ARM_EABI__"); 4831 Builder.defineMacro("__ARM_PCS", "1"); 4832 4833 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4834 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4835 } 4836 4837 if (SoftFloat) 4838 Builder.defineMacro("__SOFTFP__"); 4839 4840 if (CPU == "xscale") 4841 Builder.defineMacro("__XSCALE__"); 4842 4843 if (isThumb()) { 4844 Builder.defineMacro("__THUMBEL__"); 4845 Builder.defineMacro("__thumb__"); 4846 if (supportsThumb2()) 4847 Builder.defineMacro("__thumb2__"); 4848 } 4849 4850 // ACLE 6.4.9 32-bit SIMD instructions 4851 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4852 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4853 4854 // ACLE 6.4.10 Hardware Integer Divide 4855 if (((HWDiv & HWDivThumb) && isThumb()) || 4856 ((HWDiv & HWDivARM) && !isThumb())) { 4857 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4858 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4859 } 4860 4861 // Note, this is always on in gcc, even though it doesn't make sense. 4862 Builder.defineMacro("__APCS_32__"); 4863 4864 if (FPUModeIsVFP((FPUMode) FPU)) { 4865 Builder.defineMacro("__VFP_FP__"); 4866 if (FPU & VFP2FPU) 4867 Builder.defineMacro("__ARM_VFPV2__"); 4868 if (FPU & VFP3FPU) 4869 Builder.defineMacro("__ARM_VFPV3__"); 4870 if (FPU & VFP4FPU) 4871 Builder.defineMacro("__ARM_VFPV4__"); 4872 } 4873 4874 // This only gets set when Neon instructions are actually available, unlike 4875 // the VFP define, hence the soft float and arch check. This is subtly 4876 // different from gcc, we follow the intent which was that it should be set 4877 // when Neon instructions are actually available. 4878 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4879 Builder.defineMacro("__ARM_NEON", "1"); 4880 Builder.defineMacro("__ARM_NEON__"); 4881 // current AArch32 NEON implementations do not support double-precision 4882 // floating-point even when it is present in VFP. 4883 Builder.defineMacro("__ARM_NEON_FP", 4884 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4885 } 4886 4887 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4888 Opts.ShortWChar ? "2" : "4"); 4889 4890 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4891 Opts.ShortEnums ? "1" : "4"); 4892 4893 if (ArchVersion >= 6 && CPUAttr != "6M") { 4894 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4895 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4896 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4897 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4898 } 4899 4900 // ACLE 6.4.7 DSP instructions 4901 if (DSP) { 4902 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4903 } 4904 4905 // ACLE 6.4.8 Saturation instructions 4906 bool SAT = false; 4907 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4908 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4909 SAT = true; 4910 } 4911 4912 // ACLE 6.4.6 Q (saturation) flag 4913 if (DSP || SAT) 4914 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4915 4916 if (Opts.UnsafeFPMath) 4917 Builder.defineMacro("__ARM_FP_FAST", "1"); 4918 4919 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4920 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4921 } 4922 4923 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4924 return llvm::makeArrayRef(BuiltinInfo, 4925 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4926 } 4927 bool isCLZForZeroUndef() const override { return false; } 4928 BuiltinVaListKind getBuiltinVaListKind() const override { 4929 return IsAAPCS 4930 ? AAPCSABIBuiltinVaList 4931 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 4932 : TargetInfo::VoidPtrBuiltinVaList); 4933 } 4934 ArrayRef<const char *> getGCCRegNames() const override; 4935 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4936 bool validateAsmConstraint(const char *&Name, 4937 TargetInfo::ConstraintInfo &Info) const override { 4938 switch (*Name) { 4939 default: break; 4940 case 'l': // r0-r7 4941 case 'h': // r8-r15 4942 case 't': // VFP Floating point register single precision 4943 case 'w': // VFP Floating point register double precision 4944 Info.setAllowsRegister(); 4945 return true; 4946 case 'I': 4947 case 'J': 4948 case 'K': 4949 case 'L': 4950 case 'M': 4951 // FIXME 4952 return true; 4953 case 'Q': // A memory address that is a single base register. 4954 Info.setAllowsMemory(); 4955 return true; 4956 case 'U': // a memory reference... 4957 switch (Name[1]) { 4958 case 'q': // ...ARMV4 ldrsb 4959 case 'v': // ...VFP load/store (reg+constant offset) 4960 case 'y': // ...iWMMXt load/store 4961 case 't': // address valid for load/store opaque types wider 4962 // than 128-bits 4963 case 'n': // valid address for Neon doubleword vector load/store 4964 case 'm': // valid address for Neon element and structure load/store 4965 case 's': // valid address for non-offset loads/stores of quad-word 4966 // values in four ARM registers 4967 Info.setAllowsMemory(); 4968 Name++; 4969 return true; 4970 } 4971 } 4972 return false; 4973 } 4974 std::string convertConstraint(const char *&Constraint) const override { 4975 std::string R; 4976 switch (*Constraint) { 4977 case 'U': // Two-character constraint; add "^" hint for later parsing. 4978 R = std::string("^") + std::string(Constraint, 2); 4979 Constraint++; 4980 break; 4981 case 'p': // 'p' should be translated to 'r' by default. 4982 R = std::string("r"); 4983 break; 4984 default: 4985 return std::string(1, *Constraint); 4986 } 4987 return R; 4988 } 4989 bool 4990 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4991 std::string &SuggestedModifier) const override { 4992 bool isOutput = (Constraint[0] == '='); 4993 bool isInOut = (Constraint[0] == '+'); 4994 4995 // Strip off constraint modifiers. 4996 while (Constraint[0] == '=' || 4997 Constraint[0] == '+' || 4998 Constraint[0] == '&') 4999 Constraint = Constraint.substr(1); 5000 5001 switch (Constraint[0]) { 5002 default: break; 5003 case 'r': { 5004 switch (Modifier) { 5005 default: 5006 return (isInOut || isOutput || Size <= 64); 5007 case 'q': 5008 // A register of size 32 cannot fit a vector type. 5009 return false; 5010 } 5011 } 5012 } 5013 5014 return true; 5015 } 5016 const char *getClobbers() const override { 5017 // FIXME: Is this really right? 5018 return ""; 5019 } 5020 5021 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5022 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5023 } 5024 5025 int getEHDataRegisterNumber(unsigned RegNo) const override { 5026 if (RegNo == 0) return 0; 5027 if (RegNo == 1) return 1; 5028 return -1; 5029 } 5030 5031 bool hasSjLjLowering() const override { 5032 return true; 5033 } 5034 }; 5035 5036 bool ARMTargetInfo::setFPMath(StringRef Name) { 5037 if (Name == "neon") { 5038 FPMath = FP_Neon; 5039 return true; 5040 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5041 Name == "vfp4") { 5042 FPMath = FP_VFP; 5043 return true; 5044 } 5045 return false; 5046 } 5047 5048 const char * const ARMTargetInfo::GCCRegNames[] = { 5049 // Integer registers 5050 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5051 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5052 5053 // Float registers 5054 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5055 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5056 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5057 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5058 5059 // Double registers 5060 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5061 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5062 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5063 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5064 5065 // Quad registers 5066 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5067 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5068 }; 5069 5070 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5071 return llvm::makeArrayRef(GCCRegNames); 5072 } 5073 5074 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5075 { { "a1" }, "r0" }, 5076 { { "a2" }, "r1" }, 5077 { { "a3" }, "r2" }, 5078 { { "a4" }, "r3" }, 5079 { { "v1" }, "r4" }, 5080 { { "v2" }, "r5" }, 5081 { { "v3" }, "r6" }, 5082 { { "v4" }, "r7" }, 5083 { { "v5" }, "r8" }, 5084 { { "v6", "rfp" }, "r9" }, 5085 { { "sl" }, "r10" }, 5086 { { "fp" }, "r11" }, 5087 { { "ip" }, "r12" }, 5088 { { "r13" }, "sp" }, 5089 { { "r14" }, "lr" }, 5090 { { "r15" }, "pc" }, 5091 // The S, D and Q registers overlap, but aren't really aliases; we 5092 // don't want to substitute one of these for a different-sized one. 5093 }; 5094 5095 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5096 return llvm::makeArrayRef(GCCRegAliases); 5097 } 5098 5099 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5100 #define BUILTIN(ID, TYPE, ATTRS) \ 5101 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5102 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5103 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5104 #include "clang/Basic/BuiltinsNEON.def" 5105 5106 #define BUILTIN(ID, TYPE, ATTRS) \ 5107 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5108 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5109 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5110 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5111 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5112 #include "clang/Basic/BuiltinsARM.def" 5113 }; 5114 5115 class ARMleTargetInfo : public ARMTargetInfo { 5116 public: 5117 ARMleTargetInfo(const llvm::Triple &Triple) 5118 : ARMTargetInfo(Triple, false) { } 5119 void getTargetDefines(const LangOptions &Opts, 5120 MacroBuilder &Builder) const override { 5121 Builder.defineMacro("__ARMEL__"); 5122 ARMTargetInfo::getTargetDefines(Opts, Builder); 5123 } 5124 }; 5125 5126 class ARMbeTargetInfo : public ARMTargetInfo { 5127 public: 5128 ARMbeTargetInfo(const llvm::Triple &Triple) 5129 : ARMTargetInfo(Triple, true) { } 5130 void getTargetDefines(const LangOptions &Opts, 5131 MacroBuilder &Builder) const override { 5132 Builder.defineMacro("__ARMEB__"); 5133 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5134 ARMTargetInfo::getTargetDefines(Opts, Builder); 5135 } 5136 }; 5137 5138 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5139 const llvm::Triple Triple; 5140 public: 5141 WindowsARMTargetInfo(const llvm::Triple &Triple) 5142 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5143 WCharType = UnsignedShort; 5144 SizeType = UnsignedInt; 5145 UserLabelPrefix = ""; 5146 } 5147 void getVisualStudioDefines(const LangOptions &Opts, 5148 MacroBuilder &Builder) const { 5149 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5150 5151 // FIXME: this is invalid for WindowsCE 5152 Builder.defineMacro("_M_ARM_NT", "1"); 5153 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5154 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5155 5156 assert((Triple.getArch() == llvm::Triple::arm || 5157 Triple.getArch() == llvm::Triple::thumb) && 5158 "invalid architecture for Windows ARM target info"); 5159 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5160 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5161 5162 // TODO map the complete set of values 5163 // 31: VFPv3 40: VFPv4 5164 Builder.defineMacro("_M_ARM_FP", "31"); 5165 } 5166 BuiltinVaListKind getBuiltinVaListKind() const override { 5167 return TargetInfo::CharPtrBuiltinVaList; 5168 } 5169 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5170 switch (CC) { 5171 case CC_X86StdCall: 5172 case CC_X86ThisCall: 5173 case CC_X86FastCall: 5174 case CC_X86VectorCall: 5175 return CCCR_Ignore; 5176 case CC_C: 5177 return CCCR_OK; 5178 default: 5179 return CCCR_Warning; 5180 } 5181 } 5182 }; 5183 5184 // Windows ARM + Itanium C++ ABI Target 5185 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5186 public: 5187 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5188 : WindowsARMTargetInfo(Triple) { 5189 TheCXXABI.set(TargetCXXABI::GenericARM); 5190 } 5191 5192 void getTargetDefines(const LangOptions &Opts, 5193 MacroBuilder &Builder) const override { 5194 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5195 5196 if (Opts.MSVCCompat) 5197 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5198 } 5199 }; 5200 5201 // Windows ARM, MS (C++) ABI 5202 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5203 public: 5204 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5205 : WindowsARMTargetInfo(Triple) { 5206 TheCXXABI.set(TargetCXXABI::Microsoft); 5207 } 5208 5209 void getTargetDefines(const LangOptions &Opts, 5210 MacroBuilder &Builder) const override { 5211 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5212 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5213 } 5214 }; 5215 5216 // ARM MinGW target 5217 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5218 public: 5219 MinGWARMTargetInfo(const llvm::Triple &Triple) 5220 : WindowsARMTargetInfo(Triple) { 5221 TheCXXABI.set(TargetCXXABI::GenericARM); 5222 } 5223 5224 void getTargetDefines(const LangOptions &Opts, 5225 MacroBuilder &Builder) const override { 5226 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5227 DefineStd(Builder, "WIN32", Opts); 5228 DefineStd(Builder, "WINNT", Opts); 5229 Builder.defineMacro("_ARM_"); 5230 addMinGWDefines(Opts, Builder); 5231 } 5232 }; 5233 5234 // ARM Cygwin target 5235 class CygwinARMTargetInfo : public ARMleTargetInfo { 5236 public: 5237 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5238 TLSSupported = false; 5239 WCharType = UnsignedShort; 5240 DoubleAlign = LongLongAlign = 64; 5241 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5242 } 5243 void getTargetDefines(const LangOptions &Opts, 5244 MacroBuilder &Builder) const override { 5245 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5246 Builder.defineMacro("_ARM_"); 5247 Builder.defineMacro("__CYGWIN__"); 5248 Builder.defineMacro("__CYGWIN32__"); 5249 DefineStd(Builder, "unix", Opts); 5250 if (Opts.CPlusPlus) 5251 Builder.defineMacro("_GNU_SOURCE"); 5252 } 5253 }; 5254 5255 class DarwinARMTargetInfo : 5256 public DarwinTargetInfo<ARMleTargetInfo> { 5257 protected: 5258 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5259 MacroBuilder &Builder) const override { 5260 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5261 } 5262 5263 public: 5264 DarwinARMTargetInfo(const llvm::Triple &Triple) 5265 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5266 HasAlignMac68kSupport = true; 5267 // iOS always has 64-bit atomic instructions. 5268 // FIXME: This should be based off of the target features in 5269 // ARMleTargetInfo. 5270 MaxAtomicInlineWidth = 64; 5271 5272 if (Triple.isWatchABI()) { 5273 // Darwin on iOS uses a variant of the ARM C++ ABI. 5274 TheCXXABI.set(TargetCXXABI::WatchOS); 5275 5276 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5277 // size_t is long, it's a bit weird for it to be int. 5278 PtrDiffType = SignedLong; 5279 5280 // BOOL should be a real boolean on the new ABI 5281 UseSignedCharForObjCBool = false; 5282 } else 5283 TheCXXABI.set(TargetCXXABI::iOS); 5284 } 5285 }; 5286 5287 class AArch64TargetInfo : public TargetInfo { 5288 virtual void setDataLayoutString() = 0; 5289 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5290 static const char *const GCCRegNames[]; 5291 5292 enum FPUModeEnum { 5293 FPUMode, 5294 NeonMode 5295 }; 5296 5297 unsigned FPU; 5298 unsigned CRC; 5299 unsigned Crypto; 5300 unsigned Unaligned; 5301 unsigned V8_1A; 5302 5303 static const Builtin::Info BuiltinInfo[]; 5304 5305 std::string ABI; 5306 5307 public: 5308 AArch64TargetInfo(const llvm::Triple &Triple) 5309 : TargetInfo(Triple), ABI("aapcs") { 5310 5311 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5312 WCharType = SignedInt; 5313 5314 // NetBSD apparently prefers consistency across ARM targets to consistency 5315 // across 64-bit targets. 5316 Int64Type = SignedLongLong; 5317 IntMaxType = SignedLongLong; 5318 } else { 5319 WCharType = UnsignedInt; 5320 Int64Type = SignedLong; 5321 IntMaxType = SignedLong; 5322 } 5323 5324 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5325 MaxVectorAlign = 128; 5326 MaxAtomicInlineWidth = 128; 5327 MaxAtomicPromoteWidth = 128; 5328 5329 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5330 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5331 5332 // {} in inline assembly are neon specifiers, not assembly variant 5333 // specifiers. 5334 NoAsmVariants = true; 5335 5336 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5337 // contributes to the alignment of the containing aggregate in the same way 5338 // a plain (non bit-field) member of that type would, without exception for 5339 // zero-sized or anonymous bit-fields." 5340 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5341 UseZeroLengthBitfieldAlignment = true; 5342 5343 // AArch64 targets default to using the ARM C++ ABI. 5344 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5345 } 5346 5347 StringRef getABI() const override { return ABI; } 5348 bool setABI(const std::string &Name) override { 5349 if (Name != "aapcs" && Name != "darwinpcs") 5350 return false; 5351 5352 ABI = Name; 5353 return true; 5354 } 5355 5356 bool setCPU(const std::string &Name) override { 5357 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5358 .Case("generic", true) 5359 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5360 "cortex-a35", "exynos-m1", true) 5361 .Case("cyclone", true) 5362 .Case("kryo", true) 5363 .Default(false); 5364 return CPUKnown; 5365 } 5366 5367 void getTargetDefines(const LangOptions &Opts, 5368 MacroBuilder &Builder) const override { 5369 // Target identification. 5370 Builder.defineMacro("__aarch64__"); 5371 5372 // Target properties. 5373 Builder.defineMacro("_LP64"); 5374 Builder.defineMacro("__LP64__"); 5375 5376 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5377 Builder.defineMacro("__ARM_ACLE", "200"); 5378 Builder.defineMacro("__ARM_ARCH", "8"); 5379 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5380 5381 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5382 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5383 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5384 5385 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5386 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5387 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5388 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5389 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5390 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5391 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5392 5393 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5394 5395 // 0xe implies support for half, single and double precision operations. 5396 Builder.defineMacro("__ARM_FP", "0xE"); 5397 5398 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5399 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5400 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5401 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5402 5403 if (Opts.UnsafeFPMath) 5404 Builder.defineMacro("__ARM_FP_FAST", "1"); 5405 5406 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5407 5408 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5409 Opts.ShortEnums ? "1" : "4"); 5410 5411 if (FPU == NeonMode) { 5412 Builder.defineMacro("__ARM_NEON", "1"); 5413 // 64-bit NEON supports half, single and double precision operations. 5414 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5415 } 5416 5417 if (CRC) 5418 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5419 5420 if (Crypto) 5421 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5422 5423 if (Unaligned) 5424 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5425 5426 if (V8_1A) 5427 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5428 5429 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5430 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5431 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5432 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5433 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5434 } 5435 5436 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5437 return llvm::makeArrayRef(BuiltinInfo, 5438 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5439 } 5440 5441 bool hasFeature(StringRef Feature) const override { 5442 return Feature == "aarch64" || 5443 Feature == "arm64" || 5444 Feature == "arm" || 5445 (Feature == "neon" && FPU == NeonMode); 5446 } 5447 5448 bool handleTargetFeatures(std::vector<std::string> &Features, 5449 DiagnosticsEngine &Diags) override { 5450 FPU = FPUMode; 5451 CRC = 0; 5452 Crypto = 0; 5453 Unaligned = 1; 5454 V8_1A = 0; 5455 5456 for (const auto &Feature : Features) { 5457 if (Feature == "+neon") 5458 FPU = NeonMode; 5459 if (Feature == "+crc") 5460 CRC = 1; 5461 if (Feature == "+crypto") 5462 Crypto = 1; 5463 if (Feature == "+strict-align") 5464 Unaligned = 0; 5465 if (Feature == "+v8.1a") 5466 V8_1A = 1; 5467 } 5468 5469 setDataLayoutString(); 5470 5471 return true; 5472 } 5473 5474 bool isCLZForZeroUndef() const override { return false; } 5475 5476 BuiltinVaListKind getBuiltinVaListKind() const override { 5477 return TargetInfo::AArch64ABIBuiltinVaList; 5478 } 5479 5480 ArrayRef<const char *> getGCCRegNames() const override; 5481 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5482 5483 bool validateAsmConstraint(const char *&Name, 5484 TargetInfo::ConstraintInfo &Info) const override { 5485 switch (*Name) { 5486 default: 5487 return false; 5488 case 'w': // Floating point and SIMD registers (V0-V31) 5489 Info.setAllowsRegister(); 5490 return true; 5491 case 'I': // Constant that can be used with an ADD instruction 5492 case 'J': // Constant that can be used with a SUB instruction 5493 case 'K': // Constant that can be used with a 32-bit logical instruction 5494 case 'L': // Constant that can be used with a 64-bit logical instruction 5495 case 'M': // Constant that can be used as a 32-bit MOV immediate 5496 case 'N': // Constant that can be used as a 64-bit MOV immediate 5497 case 'Y': // Floating point constant zero 5498 case 'Z': // Integer constant zero 5499 return true; 5500 case 'Q': // A memory reference with base register and no offset 5501 Info.setAllowsMemory(); 5502 return true; 5503 case 'S': // A symbolic address 5504 Info.setAllowsRegister(); 5505 return true; 5506 case 'U': 5507 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5508 // Utf: A memory address suitable for ldp/stp in TF mode. 5509 // Usa: An absolute symbolic address. 5510 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5511 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5512 case 'z': // Zero register, wzr or xzr 5513 Info.setAllowsRegister(); 5514 return true; 5515 case 'x': // Floating point and SIMD registers (V0-V15) 5516 Info.setAllowsRegister(); 5517 return true; 5518 } 5519 return false; 5520 } 5521 5522 bool 5523 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5524 std::string &SuggestedModifier) const override { 5525 // Strip off constraint modifiers. 5526 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5527 Constraint = Constraint.substr(1); 5528 5529 switch (Constraint[0]) { 5530 default: 5531 return true; 5532 case 'z': 5533 case 'r': { 5534 switch (Modifier) { 5535 case 'x': 5536 case 'w': 5537 // For now assume that the person knows what they're 5538 // doing with the modifier. 5539 return true; 5540 default: 5541 // By default an 'r' constraint will be in the 'x' 5542 // registers. 5543 if (Size == 64) 5544 return true; 5545 5546 SuggestedModifier = "w"; 5547 return false; 5548 } 5549 } 5550 } 5551 } 5552 5553 const char *getClobbers() const override { return ""; } 5554 5555 int getEHDataRegisterNumber(unsigned RegNo) const override { 5556 if (RegNo == 0) 5557 return 0; 5558 if (RegNo == 1) 5559 return 1; 5560 return -1; 5561 } 5562 }; 5563 5564 const char *const AArch64TargetInfo::GCCRegNames[] = { 5565 // 32-bit Integer registers 5566 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5567 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5568 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5569 5570 // 64-bit Integer registers 5571 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5572 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5573 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5574 5575 // 32-bit floating point regsisters 5576 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5577 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5578 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5579 5580 // 64-bit floating point regsisters 5581 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5582 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5583 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5584 5585 // Vector registers 5586 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5587 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5588 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5589 }; 5590 5591 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5592 return llvm::makeArrayRef(GCCRegNames); 5593 } 5594 5595 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5596 { { "w31" }, "wsp" }, 5597 { { "x29" }, "fp" }, 5598 { { "x30" }, "lr" }, 5599 { { "x31" }, "sp" }, 5600 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5601 // don't want to substitute one of these for a different-sized one. 5602 }; 5603 5604 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5605 return llvm::makeArrayRef(GCCRegAliases); 5606 } 5607 5608 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5609 #define BUILTIN(ID, TYPE, ATTRS) \ 5610 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5611 #include "clang/Basic/BuiltinsNEON.def" 5612 5613 #define BUILTIN(ID, TYPE, ATTRS) \ 5614 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5615 #include "clang/Basic/BuiltinsAArch64.def" 5616 }; 5617 5618 class AArch64leTargetInfo : public AArch64TargetInfo { 5619 void setDataLayoutString() override { 5620 if (getTriple().isOSBinFormatMachO()) 5621 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5622 else 5623 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5624 } 5625 5626 public: 5627 AArch64leTargetInfo(const llvm::Triple &Triple) 5628 : AArch64TargetInfo(Triple) { 5629 BigEndian = false; 5630 } 5631 void getTargetDefines(const LangOptions &Opts, 5632 MacroBuilder &Builder) const override { 5633 Builder.defineMacro("__AARCH64EL__"); 5634 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5635 } 5636 }; 5637 5638 class AArch64beTargetInfo : public AArch64TargetInfo { 5639 void setDataLayoutString() override { 5640 assert(!getTriple().isOSBinFormatMachO()); 5641 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5642 } 5643 5644 public: 5645 AArch64beTargetInfo(const llvm::Triple &Triple) 5646 : AArch64TargetInfo(Triple) { } 5647 void getTargetDefines(const LangOptions &Opts, 5648 MacroBuilder &Builder) const override { 5649 Builder.defineMacro("__AARCH64EB__"); 5650 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5651 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5652 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5653 } 5654 }; 5655 5656 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5657 protected: 5658 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5659 MacroBuilder &Builder) const override { 5660 Builder.defineMacro("__AARCH64_SIMD__"); 5661 Builder.defineMacro("__ARM64_ARCH_8__"); 5662 Builder.defineMacro("__ARM_NEON__"); 5663 Builder.defineMacro("__LITTLE_ENDIAN__"); 5664 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5665 Builder.defineMacro("__arm64", "1"); 5666 Builder.defineMacro("__arm64__", "1"); 5667 5668 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5669 } 5670 5671 public: 5672 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5673 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5674 Int64Type = SignedLongLong; 5675 WCharType = SignedInt; 5676 UseSignedCharForObjCBool = false; 5677 5678 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5679 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5680 5681 TheCXXABI.set(TargetCXXABI::iOS64); 5682 } 5683 5684 BuiltinVaListKind getBuiltinVaListKind() const override { 5685 return TargetInfo::CharPtrBuiltinVaList; 5686 } 5687 }; 5688 5689 // Hexagon abstract base class 5690 class HexagonTargetInfo : public TargetInfo { 5691 static const Builtin::Info BuiltinInfo[]; 5692 static const char * const GCCRegNames[]; 5693 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5694 std::string CPU; 5695 bool HasHVX, HasHVXDouble; 5696 5697 public: 5698 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5699 BigEndian = false; 5700 // Specify the vector alignment explicitly. For v512x1, the calculated 5701 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5702 // the required minimum of 64 bytes. 5703 DataLayoutString = "e-m:e-p:32:32:32-a:0-n16:32-" 5704 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5705 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"; 5706 SizeType = UnsignedInt; 5707 PtrDiffType = SignedInt; 5708 IntPtrType = SignedInt; 5709 5710 // {} in inline assembly are packet specifiers, not assembly variant 5711 // specifiers. 5712 NoAsmVariants = true; 5713 5714 LargeArrayMinWidth = 64; 5715 LargeArrayAlign = 64; 5716 UseBitFieldTypeAlignment = true; 5717 ZeroLengthBitfieldBoundary = 32; 5718 HasHVX = HasHVXDouble = false; 5719 } 5720 5721 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5722 return llvm::makeArrayRef(BuiltinInfo, 5723 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5724 } 5725 5726 bool validateAsmConstraint(const char *&Name, 5727 TargetInfo::ConstraintInfo &Info) const override { 5728 return true; 5729 } 5730 5731 void getTargetDefines(const LangOptions &Opts, 5732 MacroBuilder &Builder) const override; 5733 5734 bool isCLZForZeroUndef() const override { return false; } 5735 5736 bool hasFeature(StringRef Feature) const override { 5737 return llvm::StringSwitch<bool>(Feature) 5738 .Case("hexagon", true) 5739 .Case("hvx", HasHVX) 5740 .Case("hvx-double", HasHVXDouble) 5741 .Default(false); 5742 } 5743 5744 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5745 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5746 const override; 5747 5748 bool handleTargetFeatures(std::vector<std::string> &Features, 5749 DiagnosticsEngine &Diags) override; 5750 5751 BuiltinVaListKind getBuiltinVaListKind() const override { 5752 return TargetInfo::CharPtrBuiltinVaList; 5753 } 5754 ArrayRef<const char *> getGCCRegNames() const override; 5755 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5756 const char *getClobbers() const override { 5757 return ""; 5758 } 5759 5760 static const char *getHexagonCPUSuffix(StringRef Name) { 5761 return llvm::StringSwitch<const char*>(Name) 5762 .Case("hexagonv4", "4") 5763 .Case("hexagonv5", "5") 5764 .Case("hexagonv55", "55") 5765 .Case("hexagonv60", "60") 5766 .Default(nullptr); 5767 } 5768 5769 bool setCPU(const std::string &Name) override { 5770 if (!getHexagonCPUSuffix(Name)) 5771 return false; 5772 CPU = Name; 5773 return true; 5774 } 5775 5776 int getEHDataRegisterNumber(unsigned RegNo) const override { 5777 return RegNo < 2 ? RegNo : -1; 5778 } 5779 }; 5780 5781 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5782 MacroBuilder &Builder) const { 5783 Builder.defineMacro("__qdsp6__", "1"); 5784 Builder.defineMacro("__hexagon__", "1"); 5785 5786 if (CPU == "hexagonv4") { 5787 Builder.defineMacro("__HEXAGON_V4__"); 5788 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5789 if (Opts.HexagonQdsp6Compat) { 5790 Builder.defineMacro("__QDSP6_V4__"); 5791 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5792 } 5793 } else if (CPU == "hexagonv5") { 5794 Builder.defineMacro("__HEXAGON_V5__"); 5795 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5796 if(Opts.HexagonQdsp6Compat) { 5797 Builder.defineMacro("__QDSP6_V5__"); 5798 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5799 } 5800 } else if (CPU == "hexagonv60") { 5801 Builder.defineMacro("__HEXAGON_V60__"); 5802 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5803 Builder.defineMacro("__QDSP6_V60__"); 5804 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5805 } 5806 } 5807 5808 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5809 DiagnosticsEngine &Diags) { 5810 for (auto &F : Features) { 5811 if (F == "+hvx") 5812 HasHVX = true; 5813 else if (F == "-hvx") 5814 HasHVX = HasHVXDouble = false; 5815 else if (F == "+hvx-double") 5816 HasHVX = HasHVXDouble = true; 5817 else if (F == "-hvx-double") 5818 HasHVXDouble = false; 5819 } 5820 return true; 5821 } 5822 5823 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5824 DiagnosticsEngine &Diags, StringRef CPU, 5825 const std::vector<std::string> &FeaturesVec) const { 5826 // Default for v60: -hvx, -hvx-double. 5827 Features["hvx"] = false; 5828 Features["hvx-double"] = false; 5829 5830 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5831 } 5832 5833 5834 const char *const HexagonTargetInfo::GCCRegNames[] = { 5835 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5836 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5837 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5838 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5839 "p0", "p1", "p2", "p3", 5840 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5841 }; 5842 5843 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5844 return llvm::makeArrayRef(GCCRegNames); 5845 } 5846 5847 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5848 { { "sp" }, "r29" }, 5849 { { "fp" }, "r30" }, 5850 { { "lr" }, "r31" }, 5851 }; 5852 5853 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5854 return llvm::makeArrayRef(GCCRegAliases); 5855 } 5856 5857 5858 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5859 #define BUILTIN(ID, TYPE, ATTRS) \ 5860 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5861 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5862 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5863 #include "clang/Basic/BuiltinsHexagon.def" 5864 }; 5865 5866 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5867 class SparcTargetInfo : public TargetInfo { 5868 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5869 static const char * const GCCRegNames[]; 5870 bool SoftFloat; 5871 public: 5872 SparcTargetInfo(const llvm::Triple &Triple) 5873 : TargetInfo(Triple), SoftFloat(false) {} 5874 5875 bool handleTargetFeatures(std::vector<std::string> &Features, 5876 DiagnosticsEngine &Diags) override { 5877 // The backend doesn't actually handle soft float yet, but in case someone 5878 // is using the support for the front end continue to support it. 5879 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5880 if (Feature != Features.end()) { 5881 SoftFloat = true; 5882 Features.erase(Feature); 5883 } 5884 return true; 5885 } 5886 void getTargetDefines(const LangOptions &Opts, 5887 MacroBuilder &Builder) const override { 5888 DefineStd(Builder, "sparc", Opts); 5889 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5890 5891 if (SoftFloat) 5892 Builder.defineMacro("SOFT_FLOAT", "1"); 5893 } 5894 5895 bool hasFeature(StringRef Feature) const override { 5896 return llvm::StringSwitch<bool>(Feature) 5897 .Case("softfloat", SoftFloat) 5898 .Case("sparc", true) 5899 .Default(false); 5900 } 5901 5902 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5903 // FIXME: Implement! 5904 return None; 5905 } 5906 BuiltinVaListKind getBuiltinVaListKind() const override { 5907 return TargetInfo::VoidPtrBuiltinVaList; 5908 } 5909 ArrayRef<const char *> getGCCRegNames() const override; 5910 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5911 bool validateAsmConstraint(const char *&Name, 5912 TargetInfo::ConstraintInfo &info) const override { 5913 // FIXME: Implement! 5914 switch (*Name) { 5915 case 'I': // Signed 13-bit constant 5916 case 'J': // Zero 5917 case 'K': // 32-bit constant with the low 12 bits clear 5918 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5919 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5920 case 'N': // Same as 'K' but zext (required for SIMode) 5921 case 'O': // The constant 4096 5922 return true; 5923 } 5924 return false; 5925 } 5926 const char *getClobbers() const override { 5927 // FIXME: Implement! 5928 return ""; 5929 } 5930 5931 // No Sparc V7 for now, the backend doesn't support it anyway. 5932 enum CPUKind { 5933 CK_GENERIC, 5934 CK_V8, 5935 CK_SUPERSPARC, 5936 CK_SPARCLITE, 5937 CK_F934, 5938 CK_HYPERSPARC, 5939 CK_SPARCLITE86X, 5940 CK_SPARCLET, 5941 CK_TSC701, 5942 CK_V9, 5943 CK_ULTRASPARC, 5944 CK_ULTRASPARC3, 5945 CK_NIAGARA, 5946 CK_NIAGARA2, 5947 CK_NIAGARA3, 5948 CK_NIAGARA4 5949 } CPU = CK_GENERIC; 5950 5951 enum CPUGeneration { 5952 CG_V8, 5953 CG_V9, 5954 }; 5955 5956 CPUGeneration getCPUGeneration(CPUKind Kind) const { 5957 switch (Kind) { 5958 case CK_GENERIC: 5959 case CK_V8: 5960 case CK_SUPERSPARC: 5961 case CK_SPARCLITE: 5962 case CK_F934: 5963 case CK_HYPERSPARC: 5964 case CK_SPARCLITE86X: 5965 case CK_SPARCLET: 5966 case CK_TSC701: 5967 return CG_V8; 5968 case CK_V9: 5969 case CK_ULTRASPARC: 5970 case CK_ULTRASPARC3: 5971 case CK_NIAGARA: 5972 case CK_NIAGARA2: 5973 case CK_NIAGARA3: 5974 case CK_NIAGARA4: 5975 return CG_V9; 5976 } 5977 llvm_unreachable("Unexpected CPU kind"); 5978 } 5979 5980 CPUKind getCPUKind(StringRef Name) const { 5981 return llvm::StringSwitch<CPUKind>(Name) 5982 .Case("v8", CK_V8) 5983 .Case("supersparc", CK_SUPERSPARC) 5984 .Case("sparclite", CK_SPARCLITE) 5985 .Case("f934", CK_F934) 5986 .Case("hypersparc", CK_HYPERSPARC) 5987 .Case("sparclite86x", CK_SPARCLITE86X) 5988 .Case("sparclet", CK_SPARCLET) 5989 .Case("tsc701", CK_TSC701) 5990 .Case("v9", CK_V9) 5991 .Case("ultrasparc", CK_ULTRASPARC) 5992 .Case("ultrasparc3", CK_ULTRASPARC3) 5993 .Case("niagara", CK_NIAGARA) 5994 .Case("niagara2", CK_NIAGARA2) 5995 .Case("niagara3", CK_NIAGARA3) 5996 .Case("niagara4", CK_NIAGARA4) 5997 .Default(CK_GENERIC); 5998 } 5999 6000 bool setCPU(const std::string &Name) override { 6001 CPU = getCPUKind(Name); 6002 return CPU != CK_GENERIC; 6003 } 6004 }; 6005 6006 const char * const SparcTargetInfo::GCCRegNames[] = { 6007 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6008 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6009 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6010 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6011 }; 6012 6013 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6014 return llvm::makeArrayRef(GCCRegNames); 6015 } 6016 6017 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6018 { { "g0" }, "r0" }, 6019 { { "g1" }, "r1" }, 6020 { { "g2" }, "r2" }, 6021 { { "g3" }, "r3" }, 6022 { { "g4" }, "r4" }, 6023 { { "g5" }, "r5" }, 6024 { { "g6" }, "r6" }, 6025 { { "g7" }, "r7" }, 6026 { { "o0" }, "r8" }, 6027 { { "o1" }, "r9" }, 6028 { { "o2" }, "r10" }, 6029 { { "o3" }, "r11" }, 6030 { { "o4" }, "r12" }, 6031 { { "o5" }, "r13" }, 6032 { { "o6", "sp" }, "r14" }, 6033 { { "o7" }, "r15" }, 6034 { { "l0" }, "r16" }, 6035 { { "l1" }, "r17" }, 6036 { { "l2" }, "r18" }, 6037 { { "l3" }, "r19" }, 6038 { { "l4" }, "r20" }, 6039 { { "l5" }, "r21" }, 6040 { { "l6" }, "r22" }, 6041 { { "l7" }, "r23" }, 6042 { { "i0" }, "r24" }, 6043 { { "i1" }, "r25" }, 6044 { { "i2" }, "r26" }, 6045 { { "i3" }, "r27" }, 6046 { { "i4" }, "r28" }, 6047 { { "i5" }, "r29" }, 6048 { { "i6", "fp" }, "r30" }, 6049 { { "i7" }, "r31" }, 6050 }; 6051 6052 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6053 return llvm::makeArrayRef(GCCRegAliases); 6054 } 6055 6056 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6057 class SparcV8TargetInfo : public SparcTargetInfo { 6058 public: 6059 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6060 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6061 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6062 switch (getTriple().getOS()) { 6063 default: 6064 SizeType = UnsignedInt; 6065 IntPtrType = SignedInt; 6066 PtrDiffType = SignedInt; 6067 break; 6068 case llvm::Triple::NetBSD: 6069 case llvm::Triple::OpenBSD: 6070 SizeType = UnsignedLong; 6071 IntPtrType = SignedLong; 6072 PtrDiffType = SignedLong; 6073 break; 6074 } 6075 } 6076 6077 void getTargetDefines(const LangOptions &Opts, 6078 MacroBuilder &Builder) const override { 6079 SparcTargetInfo::getTargetDefines(Opts, Builder); 6080 switch (getCPUGeneration(CPU)) { 6081 case CG_V8: 6082 Builder.defineMacro("__sparcv8"); 6083 if (getTriple().getOS() != llvm::Triple::Solaris) 6084 Builder.defineMacro("__sparcv8__"); 6085 break; 6086 case CG_V9: 6087 Builder.defineMacro("__sparcv9"); 6088 if (getTriple().getOS() != llvm::Triple::Solaris) { 6089 Builder.defineMacro("__sparcv9__"); 6090 Builder.defineMacro("__sparc_v9__"); 6091 } 6092 break; 6093 } 6094 } 6095 }; 6096 6097 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6098 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6099 public: 6100 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6101 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6102 BigEndian = false; 6103 } 6104 }; 6105 6106 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6107 class SparcV9TargetInfo : public SparcTargetInfo { 6108 public: 6109 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6110 // FIXME: Support Sparc quad-precision long double? 6111 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6112 // This is an LP64 platform. 6113 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6114 6115 // OpenBSD uses long long for int64_t and intmax_t. 6116 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6117 IntMaxType = SignedLongLong; 6118 else 6119 IntMaxType = SignedLong; 6120 Int64Type = IntMaxType; 6121 6122 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6123 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6124 LongDoubleWidth = 128; 6125 LongDoubleAlign = 128; 6126 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6127 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6128 } 6129 6130 void getTargetDefines(const LangOptions &Opts, 6131 MacroBuilder &Builder) const override { 6132 SparcTargetInfo::getTargetDefines(Opts, Builder); 6133 Builder.defineMacro("__sparcv9"); 6134 Builder.defineMacro("__arch64__"); 6135 // Solaris doesn't need these variants, but the BSDs do. 6136 if (getTriple().getOS() != llvm::Triple::Solaris) { 6137 Builder.defineMacro("__sparc64__"); 6138 Builder.defineMacro("__sparc_v9__"); 6139 Builder.defineMacro("__sparcv9__"); 6140 } 6141 } 6142 6143 bool setCPU(const std::string &Name) override { 6144 if (!SparcTargetInfo::setCPU(Name)) 6145 return false; 6146 return getCPUGeneration(CPU) == CG_V9; 6147 } 6148 }; 6149 6150 class SystemZTargetInfo : public TargetInfo { 6151 static const Builtin::Info BuiltinInfo[]; 6152 static const char *const GCCRegNames[]; 6153 std::string CPU; 6154 bool HasTransactionalExecution; 6155 bool HasVector; 6156 6157 public: 6158 SystemZTargetInfo(const llvm::Triple &Triple) 6159 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6160 HasVector(false) { 6161 IntMaxType = SignedLong; 6162 Int64Type = SignedLong; 6163 TLSSupported = true; 6164 IntWidth = IntAlign = 32; 6165 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6166 PointerWidth = PointerAlign = 64; 6167 LongDoubleWidth = 128; 6168 LongDoubleAlign = 64; 6169 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6170 DefaultAlignForAttributeAligned = 64; 6171 MinGlobalAlign = 16; 6172 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6173 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6174 } 6175 void getTargetDefines(const LangOptions &Opts, 6176 MacroBuilder &Builder) const override { 6177 Builder.defineMacro("__s390__"); 6178 Builder.defineMacro("__s390x__"); 6179 Builder.defineMacro("__zarch__"); 6180 Builder.defineMacro("__LONG_DOUBLE_128__"); 6181 6182 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6183 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6184 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6185 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6186 6187 if (HasTransactionalExecution) 6188 Builder.defineMacro("__HTM__"); 6189 if (Opts.ZVector) 6190 Builder.defineMacro("__VEC__", "10301"); 6191 } 6192 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6193 return llvm::makeArrayRef(BuiltinInfo, 6194 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6195 } 6196 6197 ArrayRef<const char *> getGCCRegNames() const override; 6198 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6199 // No aliases. 6200 return None; 6201 } 6202 bool validateAsmConstraint(const char *&Name, 6203 TargetInfo::ConstraintInfo &info) const override; 6204 const char *getClobbers() const override { 6205 // FIXME: Is this really right? 6206 return ""; 6207 } 6208 BuiltinVaListKind getBuiltinVaListKind() const override { 6209 return TargetInfo::SystemZBuiltinVaList; 6210 } 6211 bool setCPU(const std::string &Name) override { 6212 CPU = Name; 6213 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6214 .Case("z10", true) 6215 .Case("z196", true) 6216 .Case("zEC12", true) 6217 .Case("z13", true) 6218 .Default(false); 6219 6220 return CPUKnown; 6221 } 6222 bool 6223 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6224 StringRef CPU, 6225 const std::vector<std::string> &FeaturesVec) const override { 6226 if (CPU == "zEC12") 6227 Features["transactional-execution"] = true; 6228 if (CPU == "z13") { 6229 Features["transactional-execution"] = true; 6230 Features["vector"] = true; 6231 } 6232 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6233 } 6234 6235 bool handleTargetFeatures(std::vector<std::string> &Features, 6236 DiagnosticsEngine &Diags) override { 6237 HasTransactionalExecution = false; 6238 for (const auto &Feature : Features) { 6239 if (Feature == "+transactional-execution") 6240 HasTransactionalExecution = true; 6241 else if (Feature == "+vector") 6242 HasVector = true; 6243 } 6244 // If we use the vector ABI, vector types are 64-bit aligned. 6245 if (HasVector) { 6246 MaxVectorAlign = 64; 6247 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6248 "-v128:64-a:8:16-n32:64"; 6249 } 6250 return true; 6251 } 6252 6253 bool hasFeature(StringRef Feature) const override { 6254 return llvm::StringSwitch<bool>(Feature) 6255 .Case("systemz", true) 6256 .Case("htm", HasTransactionalExecution) 6257 .Case("vx", HasVector) 6258 .Default(false); 6259 } 6260 6261 StringRef getABI() const override { 6262 if (HasVector) 6263 return "vector"; 6264 return ""; 6265 } 6266 6267 bool useFloat128ManglingForLongDouble() const override { 6268 return true; 6269 } 6270 }; 6271 6272 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6273 #define BUILTIN(ID, TYPE, ATTRS) \ 6274 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6275 #include "clang/Basic/BuiltinsSystemZ.def" 6276 }; 6277 6278 const char *const SystemZTargetInfo::GCCRegNames[] = { 6279 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6280 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6281 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6282 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6283 }; 6284 6285 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6286 return llvm::makeArrayRef(GCCRegNames); 6287 } 6288 6289 bool SystemZTargetInfo:: 6290 validateAsmConstraint(const char *&Name, 6291 TargetInfo::ConstraintInfo &Info) const { 6292 switch (*Name) { 6293 default: 6294 return false; 6295 6296 case 'a': // Address register 6297 case 'd': // Data register (equivalent to 'r') 6298 case 'f': // Floating-point register 6299 Info.setAllowsRegister(); 6300 return true; 6301 6302 case 'I': // Unsigned 8-bit constant 6303 case 'J': // Unsigned 12-bit constant 6304 case 'K': // Signed 16-bit constant 6305 case 'L': // Signed 20-bit displacement (on all targets we support) 6306 case 'M': // 0x7fffffff 6307 return true; 6308 6309 case 'Q': // Memory with base and unsigned 12-bit displacement 6310 case 'R': // Likewise, plus an index 6311 case 'S': // Memory with base and signed 20-bit displacement 6312 case 'T': // Likewise, plus an index 6313 Info.setAllowsMemory(); 6314 return true; 6315 } 6316 } 6317 6318 class MSP430TargetInfo : public TargetInfo { 6319 static const char *const GCCRegNames[]; 6320 6321 public: 6322 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6323 BigEndian = false; 6324 TLSSupported = false; 6325 IntWidth = 16; 6326 IntAlign = 16; 6327 LongWidth = 32; 6328 LongLongWidth = 64; 6329 LongAlign = LongLongAlign = 16; 6330 PointerWidth = 16; 6331 PointerAlign = 16; 6332 SuitableAlign = 16; 6333 SizeType = UnsignedInt; 6334 IntMaxType = SignedLongLong; 6335 IntPtrType = SignedInt; 6336 PtrDiffType = SignedInt; 6337 SigAtomicType = SignedLong; 6338 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6339 } 6340 void getTargetDefines(const LangOptions &Opts, 6341 MacroBuilder &Builder) const override { 6342 Builder.defineMacro("MSP430"); 6343 Builder.defineMacro("__MSP430__"); 6344 // FIXME: defines for different 'flavours' of MCU 6345 } 6346 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6347 // FIXME: Implement. 6348 return None; 6349 } 6350 bool hasFeature(StringRef Feature) const override { 6351 return Feature == "msp430"; 6352 } 6353 ArrayRef<const char *> getGCCRegNames() const override; 6354 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6355 // No aliases. 6356 return None; 6357 } 6358 bool validateAsmConstraint(const char *&Name, 6359 TargetInfo::ConstraintInfo &info) const override { 6360 // FIXME: implement 6361 switch (*Name) { 6362 case 'K': // the constant 1 6363 case 'L': // constant -1^20 .. 1^19 6364 case 'M': // constant 1-4: 6365 return true; 6366 } 6367 // No target constraints for now. 6368 return false; 6369 } 6370 const char *getClobbers() const override { 6371 // FIXME: Is this really right? 6372 return ""; 6373 } 6374 BuiltinVaListKind getBuiltinVaListKind() const override { 6375 // FIXME: implement 6376 return TargetInfo::CharPtrBuiltinVaList; 6377 } 6378 }; 6379 6380 const char *const MSP430TargetInfo::GCCRegNames[] = { 6381 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6382 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6383 6384 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6385 return llvm::makeArrayRef(GCCRegNames); 6386 } 6387 6388 // LLVM and Clang cannot be used directly to output native binaries for 6389 // target, but is used to compile C code to llvm bitcode with correct 6390 // type and alignment information. 6391 // 6392 // TCE uses the llvm bitcode as input and uses it for generating customized 6393 // target processor and program binary. TCE co-design environment is 6394 // publicly available in http://tce.cs.tut.fi 6395 6396 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6397 3, // opencl_global 6398 4, // opencl_local 6399 5, // opencl_constant 6400 // FIXME: generic has to be added to the target 6401 0, // opencl_generic 6402 0, // cuda_device 6403 0, // cuda_constant 6404 0 // cuda_shared 6405 }; 6406 6407 class TCETargetInfo : public TargetInfo { 6408 public: 6409 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6410 TLSSupported = false; 6411 IntWidth = 32; 6412 LongWidth = LongLongWidth = 32; 6413 PointerWidth = 32; 6414 IntAlign = 32; 6415 LongAlign = LongLongAlign = 32; 6416 PointerAlign = 32; 6417 SuitableAlign = 32; 6418 SizeType = UnsignedInt; 6419 IntMaxType = SignedLong; 6420 IntPtrType = SignedInt; 6421 PtrDiffType = SignedInt; 6422 FloatWidth = 32; 6423 FloatAlign = 32; 6424 DoubleWidth = 32; 6425 DoubleAlign = 32; 6426 LongDoubleWidth = 32; 6427 LongDoubleAlign = 32; 6428 FloatFormat = &llvm::APFloat::IEEEsingle; 6429 DoubleFormat = &llvm::APFloat::IEEEsingle; 6430 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6431 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6432 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6433 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6434 UseAddrSpaceMapMangling = true; 6435 } 6436 6437 void getTargetDefines(const LangOptions &Opts, 6438 MacroBuilder &Builder) const override { 6439 DefineStd(Builder, "tce", Opts); 6440 Builder.defineMacro("__TCE__"); 6441 Builder.defineMacro("__TCE_V1__"); 6442 } 6443 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6444 6445 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6446 const char *getClobbers() const override { return ""; } 6447 BuiltinVaListKind getBuiltinVaListKind() const override { 6448 return TargetInfo::VoidPtrBuiltinVaList; 6449 } 6450 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6451 bool validateAsmConstraint(const char *&Name, 6452 TargetInfo::ConstraintInfo &info) const override { 6453 return true; 6454 } 6455 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6456 return None; 6457 } 6458 }; 6459 6460 class BPFTargetInfo : public TargetInfo { 6461 public: 6462 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6463 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6464 SizeType = UnsignedLong; 6465 PtrDiffType = SignedLong; 6466 IntPtrType = SignedLong; 6467 IntMaxType = SignedLong; 6468 Int64Type = SignedLong; 6469 RegParmMax = 5; 6470 if (Triple.getArch() == llvm::Triple::bpfeb) { 6471 BigEndian = true; 6472 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6473 } else { 6474 BigEndian = false; 6475 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6476 } 6477 MaxAtomicPromoteWidth = 64; 6478 MaxAtomicInlineWidth = 64; 6479 TLSSupported = false; 6480 } 6481 void getTargetDefines(const LangOptions &Opts, 6482 MacroBuilder &Builder) const override { 6483 DefineStd(Builder, "bpf", Opts); 6484 Builder.defineMacro("__BPF__"); 6485 } 6486 bool hasFeature(StringRef Feature) const override { 6487 return Feature == "bpf"; 6488 } 6489 6490 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6491 const char *getClobbers() const override { 6492 return ""; 6493 } 6494 BuiltinVaListKind getBuiltinVaListKind() const override { 6495 return TargetInfo::VoidPtrBuiltinVaList; 6496 } 6497 ArrayRef<const char *> getGCCRegNames() const override { 6498 return None; 6499 } 6500 bool validateAsmConstraint(const char *&Name, 6501 TargetInfo::ConstraintInfo &info) const override { 6502 return true; 6503 } 6504 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6505 return None; 6506 } 6507 }; 6508 6509 class MipsTargetInfoBase : public TargetInfo { 6510 virtual void setDataLayoutString() = 0; 6511 6512 static const Builtin::Info BuiltinInfo[]; 6513 std::string CPU; 6514 bool IsMips16; 6515 bool IsMicromips; 6516 bool IsNan2008; 6517 bool IsSingleFloat; 6518 enum MipsFloatABI { 6519 HardFloat, SoftFloat 6520 } FloatABI; 6521 enum DspRevEnum { 6522 NoDSP, DSP1, DSP2 6523 } DspRev; 6524 bool HasMSA; 6525 6526 protected: 6527 bool HasFP64; 6528 std::string ABI; 6529 6530 public: 6531 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6532 const std::string &CPUStr) 6533 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6534 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6535 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6536 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6537 } 6538 6539 bool isNaN2008Default() const { 6540 return CPU == "mips32r6" || CPU == "mips64r6"; 6541 } 6542 6543 bool isFP64Default() const { 6544 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6545 } 6546 6547 bool isNan2008() const override { 6548 return IsNan2008; 6549 } 6550 6551 StringRef getABI() const override { return ABI; } 6552 bool setCPU(const std::string &Name) override { 6553 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6554 getTriple().getArch() == llvm::Triple::mipsel; 6555 CPU = Name; 6556 return llvm::StringSwitch<bool>(Name) 6557 .Case("mips1", IsMips32) 6558 .Case("mips2", IsMips32) 6559 .Case("mips3", true) 6560 .Case("mips4", true) 6561 .Case("mips5", true) 6562 .Case("mips32", IsMips32) 6563 .Case("mips32r2", IsMips32) 6564 .Case("mips32r3", IsMips32) 6565 .Case("mips32r5", IsMips32) 6566 .Case("mips32r6", IsMips32) 6567 .Case("mips64", true) 6568 .Case("mips64r2", true) 6569 .Case("mips64r3", true) 6570 .Case("mips64r5", true) 6571 .Case("mips64r6", true) 6572 .Case("octeon", true) 6573 .Case("p5600", true) 6574 .Default(false); 6575 } 6576 const std::string& getCPU() const { return CPU; } 6577 bool 6578 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6579 StringRef CPU, 6580 const std::vector<std::string> &FeaturesVec) const override { 6581 if (CPU == "octeon") 6582 Features["mips64r2"] = Features["cnmips"] = true; 6583 else 6584 Features[CPU] = true; 6585 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6586 } 6587 6588 void getTargetDefines(const LangOptions &Opts, 6589 MacroBuilder &Builder) const override { 6590 Builder.defineMacro("__mips__"); 6591 Builder.defineMacro("_mips"); 6592 if (Opts.GNUMode) 6593 Builder.defineMacro("mips"); 6594 6595 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6596 6597 switch (FloatABI) { 6598 case HardFloat: 6599 Builder.defineMacro("__mips_hard_float", Twine(1)); 6600 break; 6601 case SoftFloat: 6602 Builder.defineMacro("__mips_soft_float", Twine(1)); 6603 break; 6604 } 6605 6606 if (IsSingleFloat) 6607 Builder.defineMacro("__mips_single_float", Twine(1)); 6608 6609 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6610 Builder.defineMacro("_MIPS_FPSET", 6611 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6612 6613 if (IsMips16) 6614 Builder.defineMacro("__mips16", Twine(1)); 6615 6616 if (IsMicromips) 6617 Builder.defineMacro("__mips_micromips", Twine(1)); 6618 6619 if (IsNan2008) 6620 Builder.defineMacro("__mips_nan2008", Twine(1)); 6621 6622 switch (DspRev) { 6623 default: 6624 break; 6625 case DSP1: 6626 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6627 Builder.defineMacro("__mips_dsp", Twine(1)); 6628 break; 6629 case DSP2: 6630 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6631 Builder.defineMacro("__mips_dspr2", Twine(1)); 6632 Builder.defineMacro("__mips_dsp", Twine(1)); 6633 break; 6634 } 6635 6636 if (HasMSA) 6637 Builder.defineMacro("__mips_msa", Twine(1)); 6638 6639 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6640 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6641 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6642 6643 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6644 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6645 6646 // These shouldn't be defined for MIPS-I but there's no need to check 6647 // for that since MIPS-I isn't supported. 6648 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6649 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6650 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6651 } 6652 6653 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6654 return llvm::makeArrayRef(BuiltinInfo, 6655 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6656 } 6657 bool hasFeature(StringRef Feature) const override { 6658 return llvm::StringSwitch<bool>(Feature) 6659 .Case("mips", true) 6660 .Case("fp64", HasFP64) 6661 .Default(false); 6662 } 6663 BuiltinVaListKind getBuiltinVaListKind() const override { 6664 return TargetInfo::VoidPtrBuiltinVaList; 6665 } 6666 ArrayRef<const char *> getGCCRegNames() const override { 6667 static const char *const GCCRegNames[] = { 6668 // CPU register names 6669 // Must match second column of GCCRegAliases 6670 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6671 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6672 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6673 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6674 // Floating point register names 6675 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6676 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6677 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6678 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6679 // Hi/lo and condition register names 6680 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6681 "$fcc5","$fcc6","$fcc7", 6682 // MSA register names 6683 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6684 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6685 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6686 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6687 // MSA control register names 6688 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6689 "$msarequest", "$msamap", "$msaunmap" 6690 }; 6691 return llvm::makeArrayRef(GCCRegNames); 6692 } 6693 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6694 bool validateAsmConstraint(const char *&Name, 6695 TargetInfo::ConstraintInfo &Info) const override { 6696 switch (*Name) { 6697 default: 6698 return false; 6699 case 'r': // CPU registers. 6700 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6701 case 'y': // Equivalent to "r", backward compatibility only. 6702 case 'f': // floating-point registers. 6703 case 'c': // $25 for indirect jumps 6704 case 'l': // lo register 6705 case 'x': // hilo register pair 6706 Info.setAllowsRegister(); 6707 return true; 6708 case 'I': // Signed 16-bit constant 6709 case 'J': // Integer 0 6710 case 'K': // Unsigned 16-bit constant 6711 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6712 case 'M': // Constants not loadable via lui, addiu, or ori 6713 case 'N': // Constant -1 to -65535 6714 case 'O': // A signed 15-bit constant 6715 case 'P': // A constant between 1 go 65535 6716 return true; 6717 case 'R': // An address that can be used in a non-macro load or store 6718 Info.setAllowsMemory(); 6719 return true; 6720 case 'Z': 6721 if (Name[1] == 'C') { // An address usable by ll, and sc. 6722 Info.setAllowsMemory(); 6723 Name++; // Skip over 'Z'. 6724 return true; 6725 } 6726 return false; 6727 } 6728 } 6729 6730 std::string convertConstraint(const char *&Constraint) const override { 6731 std::string R; 6732 switch (*Constraint) { 6733 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6734 if (Constraint[1] == 'C') { 6735 R = std::string("^") + std::string(Constraint, 2); 6736 Constraint++; 6737 return R; 6738 } 6739 break; 6740 } 6741 return TargetInfo::convertConstraint(Constraint); 6742 } 6743 6744 const char *getClobbers() const override { 6745 // In GCC, $1 is not widely used in generated code (it's used only in a few 6746 // specific situations), so there is no real need for users to add it to 6747 // the clobbers list if they want to use it in their inline assembly code. 6748 // 6749 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6750 // code generation, so using it in inline assembly without adding it to the 6751 // clobbers list can cause conflicts between the inline assembly code and 6752 // the surrounding generated code. 6753 // 6754 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6755 // operands, which will conflict with the ".set at" assembler option (which 6756 // we use only for inline assembly, in order to maintain compatibility with 6757 // GCC) and will also conflict with the user's usage of $1. 6758 // 6759 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6760 // register for generated code is to automatically clobber $1 for all inline 6761 // assembly code. 6762 // 6763 // FIXME: We should automatically clobber $1 only for inline assembly code 6764 // which actually uses it. This would allow LLVM to use $1 for inline 6765 // assembly operands if the user's assembly code doesn't use it. 6766 return "~{$1}"; 6767 } 6768 6769 bool handleTargetFeatures(std::vector<std::string> &Features, 6770 DiagnosticsEngine &Diags) override { 6771 IsMips16 = false; 6772 IsMicromips = false; 6773 IsNan2008 = isNaN2008Default(); 6774 IsSingleFloat = false; 6775 FloatABI = HardFloat; 6776 DspRev = NoDSP; 6777 HasFP64 = isFP64Default(); 6778 6779 for (const auto &Feature : Features) { 6780 if (Feature == "+single-float") 6781 IsSingleFloat = true; 6782 else if (Feature == "+soft-float") 6783 FloatABI = SoftFloat; 6784 else if (Feature == "+mips16") 6785 IsMips16 = true; 6786 else if (Feature == "+micromips") 6787 IsMicromips = true; 6788 else if (Feature == "+dsp") 6789 DspRev = std::max(DspRev, DSP1); 6790 else if (Feature == "+dspr2") 6791 DspRev = std::max(DspRev, DSP2); 6792 else if (Feature == "+msa") 6793 HasMSA = true; 6794 else if (Feature == "+fp64") 6795 HasFP64 = true; 6796 else if (Feature == "-fp64") 6797 HasFP64 = false; 6798 else if (Feature == "+nan2008") 6799 IsNan2008 = true; 6800 else if (Feature == "-nan2008") 6801 IsNan2008 = false; 6802 } 6803 6804 setDataLayoutString(); 6805 6806 return true; 6807 } 6808 6809 int getEHDataRegisterNumber(unsigned RegNo) const override { 6810 if (RegNo == 0) return 4; 6811 if (RegNo == 1) return 5; 6812 return -1; 6813 } 6814 6815 bool isCLZForZeroUndef() const override { return false; } 6816 }; 6817 6818 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6819 #define BUILTIN(ID, TYPE, ATTRS) \ 6820 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6821 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6822 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6823 #include "clang/Basic/BuiltinsMips.def" 6824 }; 6825 6826 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6827 public: 6828 Mips32TargetInfoBase(const llvm::Triple &Triple) 6829 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6830 SizeType = UnsignedInt; 6831 PtrDiffType = SignedInt; 6832 Int64Type = SignedLongLong; 6833 IntMaxType = Int64Type; 6834 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6835 } 6836 bool setABI(const std::string &Name) override { 6837 if (Name == "o32" || Name == "eabi") { 6838 ABI = Name; 6839 return true; 6840 } 6841 return false; 6842 } 6843 void getTargetDefines(const LangOptions &Opts, 6844 MacroBuilder &Builder) const override { 6845 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6846 6847 Builder.defineMacro("__mips", "32"); 6848 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6849 6850 const std::string& CPUStr = getCPU(); 6851 if (CPUStr == "mips32") 6852 Builder.defineMacro("__mips_isa_rev", "1"); 6853 else if (CPUStr == "mips32r2") 6854 Builder.defineMacro("__mips_isa_rev", "2"); 6855 else if (CPUStr == "mips32r3") 6856 Builder.defineMacro("__mips_isa_rev", "3"); 6857 else if (CPUStr == "mips32r5") 6858 Builder.defineMacro("__mips_isa_rev", "5"); 6859 else if (CPUStr == "mips32r6") 6860 Builder.defineMacro("__mips_isa_rev", "6"); 6861 6862 if (ABI == "o32") { 6863 Builder.defineMacro("__mips_o32"); 6864 Builder.defineMacro("_ABIO32", "1"); 6865 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6866 } 6867 else if (ABI == "eabi") 6868 Builder.defineMacro("__mips_eabi"); 6869 else 6870 llvm_unreachable("Invalid ABI for Mips32."); 6871 } 6872 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6873 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6874 { { "at" }, "$1" }, 6875 { { "v0" }, "$2" }, 6876 { { "v1" }, "$3" }, 6877 { { "a0" }, "$4" }, 6878 { { "a1" }, "$5" }, 6879 { { "a2" }, "$6" }, 6880 { { "a3" }, "$7" }, 6881 { { "t0" }, "$8" }, 6882 { { "t1" }, "$9" }, 6883 { { "t2" }, "$10" }, 6884 { { "t3" }, "$11" }, 6885 { { "t4" }, "$12" }, 6886 { { "t5" }, "$13" }, 6887 { { "t6" }, "$14" }, 6888 { { "t7" }, "$15" }, 6889 { { "s0" }, "$16" }, 6890 { { "s1" }, "$17" }, 6891 { { "s2" }, "$18" }, 6892 { { "s3" }, "$19" }, 6893 { { "s4" }, "$20" }, 6894 { { "s5" }, "$21" }, 6895 { { "s6" }, "$22" }, 6896 { { "s7" }, "$23" }, 6897 { { "t8" }, "$24" }, 6898 { { "t9" }, "$25" }, 6899 { { "k0" }, "$26" }, 6900 { { "k1" }, "$27" }, 6901 { { "gp" }, "$28" }, 6902 { { "sp","$sp" }, "$29" }, 6903 { { "fp","$fp" }, "$30" }, 6904 { { "ra" }, "$31" } 6905 }; 6906 return llvm::makeArrayRef(GCCRegAliases); 6907 } 6908 }; 6909 6910 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6911 void setDataLayoutString() override { 6912 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6913 } 6914 6915 public: 6916 Mips32EBTargetInfo(const llvm::Triple &Triple) 6917 : Mips32TargetInfoBase(Triple) { 6918 } 6919 void getTargetDefines(const LangOptions &Opts, 6920 MacroBuilder &Builder) const override { 6921 DefineStd(Builder, "MIPSEB", Opts); 6922 Builder.defineMacro("_MIPSEB"); 6923 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6924 } 6925 }; 6926 6927 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6928 void setDataLayoutString() override { 6929 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6930 } 6931 6932 public: 6933 Mips32ELTargetInfo(const llvm::Triple &Triple) 6934 : Mips32TargetInfoBase(Triple) { 6935 BigEndian = false; 6936 } 6937 void getTargetDefines(const LangOptions &Opts, 6938 MacroBuilder &Builder) const override { 6939 DefineStd(Builder, "MIPSEL", Opts); 6940 Builder.defineMacro("_MIPSEL"); 6941 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6942 } 6943 }; 6944 6945 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6946 public: 6947 Mips64TargetInfoBase(const llvm::Triple &Triple) 6948 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6949 LongDoubleWidth = LongDoubleAlign = 128; 6950 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6951 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6952 LongDoubleWidth = LongDoubleAlign = 64; 6953 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6954 } 6955 setN64ABITypes(); 6956 SuitableAlign = 128; 6957 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6958 } 6959 6960 void setN64ABITypes() { 6961 LongWidth = LongAlign = 64; 6962 PointerWidth = PointerAlign = 64; 6963 SizeType = UnsignedLong; 6964 PtrDiffType = SignedLong; 6965 Int64Type = SignedLong; 6966 IntMaxType = Int64Type; 6967 } 6968 6969 void setN32ABITypes() { 6970 LongWidth = LongAlign = 32; 6971 PointerWidth = PointerAlign = 32; 6972 SizeType = UnsignedInt; 6973 PtrDiffType = SignedInt; 6974 Int64Type = SignedLongLong; 6975 IntMaxType = Int64Type; 6976 } 6977 6978 bool setABI(const std::string &Name) override { 6979 if (Name == "n32") { 6980 setN32ABITypes(); 6981 ABI = Name; 6982 return true; 6983 } 6984 if (Name == "n64") { 6985 setN64ABITypes(); 6986 ABI = Name; 6987 return true; 6988 } 6989 return false; 6990 } 6991 6992 void getTargetDefines(const LangOptions &Opts, 6993 MacroBuilder &Builder) const override { 6994 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6995 6996 Builder.defineMacro("__mips", "64"); 6997 Builder.defineMacro("__mips64"); 6998 Builder.defineMacro("__mips64__"); 6999 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7000 7001 const std::string& CPUStr = getCPU(); 7002 if (CPUStr == "mips64") 7003 Builder.defineMacro("__mips_isa_rev", "1"); 7004 else if (CPUStr == "mips64r2") 7005 Builder.defineMacro("__mips_isa_rev", "2"); 7006 else if (CPUStr == "mips64r3") 7007 Builder.defineMacro("__mips_isa_rev", "3"); 7008 else if (CPUStr == "mips64r5") 7009 Builder.defineMacro("__mips_isa_rev", "5"); 7010 else if (CPUStr == "mips64r6") 7011 Builder.defineMacro("__mips_isa_rev", "6"); 7012 7013 if (ABI == "n32") { 7014 Builder.defineMacro("__mips_n32"); 7015 Builder.defineMacro("_ABIN32", "2"); 7016 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7017 } 7018 else if (ABI == "n64") { 7019 Builder.defineMacro("__mips_n64"); 7020 Builder.defineMacro("_ABI64", "3"); 7021 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7022 } 7023 else 7024 llvm_unreachable("Invalid ABI for Mips64."); 7025 7026 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7027 } 7028 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7029 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7030 { { "at" }, "$1" }, 7031 { { "v0" }, "$2" }, 7032 { { "v1" }, "$3" }, 7033 { { "a0" }, "$4" }, 7034 { { "a1" }, "$5" }, 7035 { { "a2" }, "$6" }, 7036 { { "a3" }, "$7" }, 7037 { { "a4" }, "$8" }, 7038 { { "a5" }, "$9" }, 7039 { { "a6" }, "$10" }, 7040 { { "a7" }, "$11" }, 7041 { { "t0" }, "$12" }, 7042 { { "t1" }, "$13" }, 7043 { { "t2" }, "$14" }, 7044 { { "t3" }, "$15" }, 7045 { { "s0" }, "$16" }, 7046 { { "s1" }, "$17" }, 7047 { { "s2" }, "$18" }, 7048 { { "s3" }, "$19" }, 7049 { { "s4" }, "$20" }, 7050 { { "s5" }, "$21" }, 7051 { { "s6" }, "$22" }, 7052 { { "s7" }, "$23" }, 7053 { { "t8" }, "$24" }, 7054 { { "t9" }, "$25" }, 7055 { { "k0" }, "$26" }, 7056 { { "k1" }, "$27" }, 7057 { { "gp" }, "$28" }, 7058 { { "sp","$sp" }, "$29" }, 7059 { { "fp","$fp" }, "$30" }, 7060 { { "ra" }, "$31" } 7061 }; 7062 return llvm::makeArrayRef(GCCRegAliases); 7063 } 7064 7065 bool hasInt128Type() const override { return true; } 7066 }; 7067 7068 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7069 void setDataLayoutString() override { 7070 if (ABI == "n32") 7071 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7072 else 7073 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7074 7075 } 7076 7077 public: 7078 Mips64EBTargetInfo(const llvm::Triple &Triple) 7079 : Mips64TargetInfoBase(Triple) {} 7080 void getTargetDefines(const LangOptions &Opts, 7081 MacroBuilder &Builder) const override { 7082 DefineStd(Builder, "MIPSEB", Opts); 7083 Builder.defineMacro("_MIPSEB"); 7084 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7085 } 7086 }; 7087 7088 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7089 void setDataLayoutString() override { 7090 if (ABI == "n32") 7091 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7092 else 7093 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7094 } 7095 public: 7096 Mips64ELTargetInfo(const llvm::Triple &Triple) 7097 : Mips64TargetInfoBase(Triple) { 7098 // Default ABI is n64. 7099 BigEndian = false; 7100 } 7101 void getTargetDefines(const LangOptions &Opts, 7102 MacroBuilder &Builder) const override { 7103 DefineStd(Builder, "MIPSEL", Opts); 7104 Builder.defineMacro("_MIPSEL"); 7105 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7106 } 7107 }; 7108 7109 class PNaClTargetInfo : public TargetInfo { 7110 public: 7111 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7112 BigEndian = false; 7113 this->UserLabelPrefix = ""; 7114 this->LongAlign = 32; 7115 this->LongWidth = 32; 7116 this->PointerAlign = 32; 7117 this->PointerWidth = 32; 7118 this->IntMaxType = TargetInfo::SignedLongLong; 7119 this->Int64Type = TargetInfo::SignedLongLong; 7120 this->DoubleAlign = 64; 7121 this->LongDoubleWidth = 64; 7122 this->LongDoubleAlign = 64; 7123 this->SizeType = TargetInfo::UnsignedInt; 7124 this->PtrDiffType = TargetInfo::SignedInt; 7125 this->IntPtrType = TargetInfo::SignedInt; 7126 this->RegParmMax = 0; // Disallow regparm 7127 } 7128 7129 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7130 Builder.defineMacro("__le32__"); 7131 Builder.defineMacro("__pnacl__"); 7132 } 7133 void getTargetDefines(const LangOptions &Opts, 7134 MacroBuilder &Builder) const override { 7135 getArchDefines(Opts, Builder); 7136 } 7137 bool hasFeature(StringRef Feature) const override { 7138 return Feature == "pnacl"; 7139 } 7140 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7141 BuiltinVaListKind getBuiltinVaListKind() const override { 7142 return TargetInfo::PNaClABIBuiltinVaList; 7143 } 7144 ArrayRef<const char *> getGCCRegNames() const override; 7145 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7146 bool validateAsmConstraint(const char *&Name, 7147 TargetInfo::ConstraintInfo &Info) const override { 7148 return false; 7149 } 7150 7151 const char *getClobbers() const override { 7152 return ""; 7153 } 7154 }; 7155 7156 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7157 return None; 7158 } 7159 7160 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7161 return None; 7162 } 7163 7164 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7165 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7166 public: 7167 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7168 Mips32ELTargetInfo(Triple) { 7169 } 7170 7171 BuiltinVaListKind getBuiltinVaListKind() const override { 7172 return TargetInfo::PNaClABIBuiltinVaList; 7173 } 7174 }; 7175 7176 class Le64TargetInfo : public TargetInfo { 7177 static const Builtin::Info BuiltinInfo[]; 7178 7179 public: 7180 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7181 BigEndian = false; 7182 NoAsmVariants = true; 7183 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7184 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7185 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7186 } 7187 7188 void getTargetDefines(const LangOptions &Opts, 7189 MacroBuilder &Builder) const override { 7190 DefineStd(Builder, "unix", Opts); 7191 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7192 Builder.defineMacro("__ELF__"); 7193 } 7194 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7195 return llvm::makeArrayRef(BuiltinInfo, 7196 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7197 } 7198 BuiltinVaListKind getBuiltinVaListKind() const override { 7199 return TargetInfo::PNaClABIBuiltinVaList; 7200 } 7201 const char *getClobbers() const override { return ""; } 7202 ArrayRef<const char *> getGCCRegNames() const override { 7203 return None; 7204 } 7205 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7206 return None; 7207 } 7208 bool validateAsmConstraint(const char *&Name, 7209 TargetInfo::ConstraintInfo &Info) const override { 7210 return false; 7211 } 7212 7213 bool hasProtectedVisibility() const override { return false; } 7214 }; 7215 7216 class WebAssemblyTargetInfo : public TargetInfo { 7217 static const Builtin::Info BuiltinInfo[]; 7218 7219 enum SIMDEnum { 7220 NoSIMD, 7221 SIMD128, 7222 } SIMDLevel; 7223 7224 public: 7225 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7226 : TargetInfo(T), SIMDLevel(NoSIMD) { 7227 BigEndian = false; 7228 NoAsmVariants = true; 7229 SuitableAlign = 128; 7230 LargeArrayMinWidth = 128; 7231 LargeArrayAlign = 128; 7232 SimdDefaultAlign = 128; 7233 SigAtomicType = SignedLong; 7234 LongDoubleWidth = LongDoubleAlign = 128; 7235 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7236 } 7237 7238 protected: 7239 void getTargetDefines(const LangOptions &Opts, 7240 MacroBuilder &Builder) const override { 7241 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7242 if (SIMDLevel >= SIMD128) 7243 Builder.defineMacro("__wasm_simd128__"); 7244 } 7245 7246 private: 7247 bool 7248 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7249 StringRef CPU, 7250 const std::vector<std::string> &FeaturesVec) const override { 7251 if (CPU == "bleeding-edge") 7252 Features["simd128"] = true; 7253 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7254 } 7255 bool hasFeature(StringRef Feature) const final { 7256 return llvm::StringSwitch<bool>(Feature) 7257 .Case("simd128", SIMDLevel >= SIMD128) 7258 .Default(false); 7259 } 7260 bool handleTargetFeatures(std::vector<std::string> &Features, 7261 DiagnosticsEngine &Diags) final { 7262 for (const auto &Feature : Features) { 7263 if (Feature == "+simd128") { 7264 SIMDLevel = std::max(SIMDLevel, SIMD128); 7265 continue; 7266 } 7267 if (Feature == "-simd128") { 7268 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7269 continue; 7270 } 7271 7272 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7273 << "-target-feature"; 7274 return false; 7275 } 7276 return true; 7277 } 7278 bool setCPU(const std::string &Name) final { 7279 return llvm::StringSwitch<bool>(Name) 7280 .Case("mvp", true) 7281 .Case("bleeding-edge", true) 7282 .Case("generic", true) 7283 .Default(false); 7284 } 7285 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7286 return llvm::makeArrayRef(BuiltinInfo, 7287 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7288 } 7289 BuiltinVaListKind getBuiltinVaListKind() const final { 7290 return VoidPtrBuiltinVaList; 7291 } 7292 ArrayRef<const char *> getGCCRegNames() const final { 7293 return None; 7294 } 7295 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7296 return None; 7297 } 7298 bool 7299 validateAsmConstraint(const char *&Name, 7300 TargetInfo::ConstraintInfo &Info) const final { 7301 return false; 7302 } 7303 const char *getClobbers() const final { return ""; } 7304 bool isCLZForZeroUndef() const final { return false; } 7305 bool hasInt128Type() const final { return true; } 7306 IntType getIntTypeByWidth(unsigned BitWidth, 7307 bool IsSigned) const final { 7308 // WebAssembly prefers long long for explicitly 64-bit integers. 7309 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7310 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7311 } 7312 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7313 bool IsSigned) const final { 7314 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7315 return BitWidth == 64 7316 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7317 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7318 } 7319 }; 7320 7321 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7322 #define BUILTIN(ID, TYPE, ATTRS) \ 7323 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7324 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7325 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7326 #include "clang/Basic/BuiltinsWebAssembly.def" 7327 }; 7328 7329 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7330 public: 7331 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7332 : WebAssemblyTargetInfo(T) { 7333 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7334 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7335 } 7336 7337 protected: 7338 void getTargetDefines(const LangOptions &Opts, 7339 MacroBuilder &Builder) const override { 7340 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7341 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7342 } 7343 }; 7344 7345 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7346 public: 7347 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7348 : WebAssemblyTargetInfo(T) { 7349 LongAlign = LongWidth = 64; 7350 PointerAlign = PointerWidth = 64; 7351 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7352 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7353 } 7354 7355 protected: 7356 void getTargetDefines(const LangOptions &Opts, 7357 MacroBuilder &Builder) const override { 7358 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7359 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7360 } 7361 }; 7362 7363 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7364 #define BUILTIN(ID, TYPE, ATTRS) \ 7365 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7366 #include "clang/Basic/BuiltinsLe64.def" 7367 }; 7368 7369 static const unsigned SPIRAddrSpaceMap[] = { 7370 1, // opencl_global 7371 3, // opencl_local 7372 2, // opencl_constant 7373 4, // opencl_generic 7374 0, // cuda_device 7375 0, // cuda_constant 7376 0 // cuda_shared 7377 }; 7378 class SPIRTargetInfo : public TargetInfo { 7379 public: 7380 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7381 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7382 "SPIR target must use unknown OS"); 7383 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7384 "SPIR target must use unknown environment type"); 7385 BigEndian = false; 7386 TLSSupported = false; 7387 LongWidth = LongAlign = 64; 7388 AddrSpaceMap = &SPIRAddrSpaceMap; 7389 UseAddrSpaceMapMangling = true; 7390 // Define available target features 7391 // These must be defined in sorted order! 7392 NoAsmVariants = true; 7393 } 7394 void getTargetDefines(const LangOptions &Opts, 7395 MacroBuilder &Builder) const override { 7396 DefineStd(Builder, "SPIR", Opts); 7397 } 7398 bool hasFeature(StringRef Feature) const override { 7399 return Feature == "spir"; 7400 } 7401 7402 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7403 const char *getClobbers() const override { return ""; } 7404 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7405 bool validateAsmConstraint(const char *&Name, 7406 TargetInfo::ConstraintInfo &info) const override { 7407 return true; 7408 } 7409 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7410 return None; 7411 } 7412 BuiltinVaListKind getBuiltinVaListKind() const override { 7413 return TargetInfo::VoidPtrBuiltinVaList; 7414 } 7415 7416 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7417 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7418 : CCCR_Warning; 7419 } 7420 7421 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7422 return CC_SpirFunction; 7423 } 7424 }; 7425 7426 class SPIR32TargetInfo : public SPIRTargetInfo { 7427 public: 7428 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7429 PointerWidth = PointerAlign = 32; 7430 SizeType = TargetInfo::UnsignedInt; 7431 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7432 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7433 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7434 } 7435 void getTargetDefines(const LangOptions &Opts, 7436 MacroBuilder &Builder) const override { 7437 DefineStd(Builder, "SPIR32", Opts); 7438 } 7439 }; 7440 7441 class SPIR64TargetInfo : public SPIRTargetInfo { 7442 public: 7443 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7444 PointerWidth = PointerAlign = 64; 7445 SizeType = TargetInfo::UnsignedLong; 7446 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7447 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7448 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7449 } 7450 void getTargetDefines(const LangOptions &Opts, 7451 MacroBuilder &Builder) const override { 7452 DefineStd(Builder, "SPIR64", Opts); 7453 } 7454 }; 7455 7456 class XCoreTargetInfo : public TargetInfo { 7457 static const Builtin::Info BuiltinInfo[]; 7458 public: 7459 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7460 BigEndian = false; 7461 NoAsmVariants = true; 7462 LongLongAlign = 32; 7463 SuitableAlign = 32; 7464 DoubleAlign = LongDoubleAlign = 32; 7465 SizeType = UnsignedInt; 7466 PtrDiffType = SignedInt; 7467 IntPtrType = SignedInt; 7468 WCharType = UnsignedChar; 7469 WIntType = UnsignedInt; 7470 UseZeroLengthBitfieldAlignment = true; 7471 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7472 "-f64:32-a:0:32-n32"; 7473 } 7474 void getTargetDefines(const LangOptions &Opts, 7475 MacroBuilder &Builder) const override { 7476 Builder.defineMacro("__XS1B__"); 7477 } 7478 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7479 return llvm::makeArrayRef(BuiltinInfo, 7480 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7481 } 7482 BuiltinVaListKind getBuiltinVaListKind() const override { 7483 return TargetInfo::VoidPtrBuiltinVaList; 7484 } 7485 const char *getClobbers() const override { 7486 return ""; 7487 } 7488 ArrayRef<const char *> getGCCRegNames() const override { 7489 static const char * const GCCRegNames[] = { 7490 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7491 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7492 }; 7493 return llvm::makeArrayRef(GCCRegNames); 7494 } 7495 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7496 return None; 7497 } 7498 bool validateAsmConstraint(const char *&Name, 7499 TargetInfo::ConstraintInfo &Info) const override { 7500 return false; 7501 } 7502 int getEHDataRegisterNumber(unsigned RegNo) const override { 7503 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7504 return (RegNo < 2)? RegNo : -1; 7505 } 7506 bool allowsLargerPreferedTypeAlignment() const override { 7507 return false; 7508 } 7509 }; 7510 7511 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7512 #define BUILTIN(ID, TYPE, ATTRS) \ 7513 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7514 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7515 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7516 #include "clang/Basic/BuiltinsXCore.def" 7517 }; 7518 7519 // x86_32 Android target 7520 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7521 public: 7522 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7523 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7524 SuitableAlign = 32; 7525 LongDoubleWidth = 64; 7526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7527 } 7528 }; 7529 7530 // x86_64 Android target 7531 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7532 public: 7533 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7534 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7535 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7536 } 7537 7538 bool useFloat128ManglingForLongDouble() const override { 7539 return true; 7540 } 7541 }; 7542 } // end anonymous namespace 7543 7544 //===----------------------------------------------------------------------===// 7545 // Driver code 7546 //===----------------------------------------------------------------------===// 7547 7548 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7549 llvm::Triple::OSType os = Triple.getOS(); 7550 7551 switch (Triple.getArch()) { 7552 default: 7553 return nullptr; 7554 7555 case llvm::Triple::xcore: 7556 return new XCoreTargetInfo(Triple); 7557 7558 case llvm::Triple::hexagon: 7559 return new HexagonTargetInfo(Triple); 7560 7561 case llvm::Triple::aarch64: 7562 if (Triple.isOSDarwin()) 7563 return new DarwinAArch64TargetInfo(Triple); 7564 7565 switch (os) { 7566 case llvm::Triple::CloudABI: 7567 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7568 case llvm::Triple::FreeBSD: 7569 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7570 case llvm::Triple::Linux: 7571 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7572 case llvm::Triple::NetBSD: 7573 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7574 default: 7575 return new AArch64leTargetInfo(Triple); 7576 } 7577 7578 case llvm::Triple::aarch64_be: 7579 switch (os) { 7580 case llvm::Triple::FreeBSD: 7581 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7582 case llvm::Triple::Linux: 7583 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7584 case llvm::Triple::NetBSD: 7585 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7586 default: 7587 return new AArch64beTargetInfo(Triple); 7588 } 7589 7590 case llvm::Triple::arm: 7591 case llvm::Triple::thumb: 7592 if (Triple.isOSBinFormatMachO()) 7593 return new DarwinARMTargetInfo(Triple); 7594 7595 switch (os) { 7596 case llvm::Triple::Linux: 7597 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7598 case llvm::Triple::FreeBSD: 7599 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7600 case llvm::Triple::NetBSD: 7601 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7602 case llvm::Triple::OpenBSD: 7603 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7604 case llvm::Triple::Bitrig: 7605 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7606 case llvm::Triple::RTEMS: 7607 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7608 case llvm::Triple::NaCl: 7609 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7610 case llvm::Triple::Win32: 7611 switch (Triple.getEnvironment()) { 7612 case llvm::Triple::Cygnus: 7613 return new CygwinARMTargetInfo(Triple); 7614 case llvm::Triple::GNU: 7615 return new MinGWARMTargetInfo(Triple); 7616 case llvm::Triple::Itanium: 7617 return new ItaniumWindowsARMleTargetInfo(Triple); 7618 case llvm::Triple::MSVC: 7619 default: // Assume MSVC for unknown environments 7620 return new MicrosoftARMleTargetInfo(Triple); 7621 } 7622 default: 7623 return new ARMleTargetInfo(Triple); 7624 } 7625 7626 case llvm::Triple::armeb: 7627 case llvm::Triple::thumbeb: 7628 if (Triple.isOSDarwin()) 7629 return new DarwinARMTargetInfo(Triple); 7630 7631 switch (os) { 7632 case llvm::Triple::Linux: 7633 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7634 case llvm::Triple::FreeBSD: 7635 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7636 case llvm::Triple::NetBSD: 7637 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7638 case llvm::Triple::OpenBSD: 7639 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7640 case llvm::Triple::Bitrig: 7641 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7642 case llvm::Triple::RTEMS: 7643 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7644 case llvm::Triple::NaCl: 7645 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7646 default: 7647 return new ARMbeTargetInfo(Triple); 7648 } 7649 7650 case llvm::Triple::bpfeb: 7651 case llvm::Triple::bpfel: 7652 return new BPFTargetInfo(Triple); 7653 7654 case llvm::Triple::msp430: 7655 return new MSP430TargetInfo(Triple); 7656 7657 case llvm::Triple::mips: 7658 switch (os) { 7659 case llvm::Triple::Linux: 7660 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7661 case llvm::Triple::RTEMS: 7662 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7663 case llvm::Triple::FreeBSD: 7664 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7665 case llvm::Triple::NetBSD: 7666 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7667 default: 7668 return new Mips32EBTargetInfo(Triple); 7669 } 7670 7671 case llvm::Triple::mipsel: 7672 switch (os) { 7673 case llvm::Triple::Linux: 7674 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7675 case llvm::Triple::RTEMS: 7676 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7677 case llvm::Triple::FreeBSD: 7678 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7679 case llvm::Triple::NetBSD: 7680 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7681 case llvm::Triple::NaCl: 7682 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7683 default: 7684 return new Mips32ELTargetInfo(Triple); 7685 } 7686 7687 case llvm::Triple::mips64: 7688 switch (os) { 7689 case llvm::Triple::Linux: 7690 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7691 case llvm::Triple::RTEMS: 7692 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7693 case llvm::Triple::FreeBSD: 7694 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7695 case llvm::Triple::NetBSD: 7696 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7697 case llvm::Triple::OpenBSD: 7698 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7699 default: 7700 return new Mips64EBTargetInfo(Triple); 7701 } 7702 7703 case llvm::Triple::mips64el: 7704 switch (os) { 7705 case llvm::Triple::Linux: 7706 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7707 case llvm::Triple::RTEMS: 7708 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7709 case llvm::Triple::FreeBSD: 7710 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7711 case llvm::Triple::NetBSD: 7712 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7713 case llvm::Triple::OpenBSD: 7714 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7715 default: 7716 return new Mips64ELTargetInfo(Triple); 7717 } 7718 7719 case llvm::Triple::le32: 7720 switch (os) { 7721 case llvm::Triple::NaCl: 7722 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7723 default: 7724 return nullptr; 7725 } 7726 7727 case llvm::Triple::le64: 7728 return new Le64TargetInfo(Triple); 7729 7730 case llvm::Triple::ppc: 7731 if (Triple.isOSDarwin()) 7732 return new DarwinPPC32TargetInfo(Triple); 7733 switch (os) { 7734 case llvm::Triple::Linux: 7735 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7736 case llvm::Triple::FreeBSD: 7737 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7738 case llvm::Triple::NetBSD: 7739 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7740 case llvm::Triple::OpenBSD: 7741 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7742 case llvm::Triple::RTEMS: 7743 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7744 default: 7745 return new PPC32TargetInfo(Triple); 7746 } 7747 7748 case llvm::Triple::ppc64: 7749 if (Triple.isOSDarwin()) 7750 return new DarwinPPC64TargetInfo(Triple); 7751 switch (os) { 7752 case llvm::Triple::Linux: 7753 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7754 case llvm::Triple::Lv2: 7755 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7756 case llvm::Triple::FreeBSD: 7757 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7758 case llvm::Triple::NetBSD: 7759 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7760 default: 7761 return new PPC64TargetInfo(Triple); 7762 } 7763 7764 case llvm::Triple::ppc64le: 7765 switch (os) { 7766 case llvm::Triple::Linux: 7767 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7768 case llvm::Triple::NetBSD: 7769 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7770 default: 7771 return new PPC64TargetInfo(Triple); 7772 } 7773 7774 case llvm::Triple::nvptx: 7775 return new NVPTX32TargetInfo(Triple); 7776 case llvm::Triple::nvptx64: 7777 return new NVPTX64TargetInfo(Triple); 7778 7779 case llvm::Triple::amdgcn: 7780 case llvm::Triple::r600: 7781 return new AMDGPUTargetInfo(Triple); 7782 7783 case llvm::Triple::sparc: 7784 switch (os) { 7785 case llvm::Triple::Linux: 7786 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7787 case llvm::Triple::Solaris: 7788 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7789 case llvm::Triple::NetBSD: 7790 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7791 case llvm::Triple::OpenBSD: 7792 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7793 case llvm::Triple::RTEMS: 7794 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7795 default: 7796 return new SparcV8TargetInfo(Triple); 7797 } 7798 7799 // The 'sparcel' architecture copies all the above cases except for Solaris. 7800 case llvm::Triple::sparcel: 7801 switch (os) { 7802 case llvm::Triple::Linux: 7803 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7804 case llvm::Triple::NetBSD: 7805 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7806 case llvm::Triple::OpenBSD: 7807 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7808 case llvm::Triple::RTEMS: 7809 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7810 default: 7811 return new SparcV8elTargetInfo(Triple); 7812 } 7813 7814 case llvm::Triple::sparcv9: 7815 switch (os) { 7816 case llvm::Triple::Linux: 7817 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7818 case llvm::Triple::Solaris: 7819 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7820 case llvm::Triple::NetBSD: 7821 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7822 case llvm::Triple::OpenBSD: 7823 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7824 case llvm::Triple::FreeBSD: 7825 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7826 default: 7827 return new SparcV9TargetInfo(Triple); 7828 } 7829 7830 case llvm::Triple::systemz: 7831 switch (os) { 7832 case llvm::Triple::Linux: 7833 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7834 default: 7835 return new SystemZTargetInfo(Triple); 7836 } 7837 7838 case llvm::Triple::tce: 7839 return new TCETargetInfo(Triple); 7840 7841 case llvm::Triple::x86: 7842 if (Triple.isOSDarwin()) 7843 return new DarwinI386TargetInfo(Triple); 7844 7845 switch (os) { 7846 case llvm::Triple::CloudABI: 7847 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7848 case llvm::Triple::Linux: { 7849 switch (Triple.getEnvironment()) { 7850 default: 7851 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7852 case llvm::Triple::Android: 7853 return new AndroidX86_32TargetInfo(Triple); 7854 } 7855 } 7856 case llvm::Triple::DragonFly: 7857 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7858 case llvm::Triple::NetBSD: 7859 return new NetBSDI386TargetInfo(Triple); 7860 case llvm::Triple::OpenBSD: 7861 return new OpenBSDI386TargetInfo(Triple); 7862 case llvm::Triple::Bitrig: 7863 return new BitrigI386TargetInfo(Triple); 7864 case llvm::Triple::FreeBSD: 7865 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7866 case llvm::Triple::KFreeBSD: 7867 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7868 case llvm::Triple::Minix: 7869 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7870 case llvm::Triple::Solaris: 7871 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7872 case llvm::Triple::Win32: { 7873 switch (Triple.getEnvironment()) { 7874 case llvm::Triple::Cygnus: 7875 return new CygwinX86_32TargetInfo(Triple); 7876 case llvm::Triple::GNU: 7877 return new MinGWX86_32TargetInfo(Triple); 7878 case llvm::Triple::Itanium: 7879 case llvm::Triple::MSVC: 7880 default: // Assume MSVC for unknown environments 7881 return new MicrosoftX86_32TargetInfo(Triple); 7882 } 7883 } 7884 case llvm::Triple::Haiku: 7885 return new HaikuX86_32TargetInfo(Triple); 7886 case llvm::Triple::RTEMS: 7887 return new RTEMSX86_32TargetInfo(Triple); 7888 case llvm::Triple::NaCl: 7889 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7890 case llvm::Triple::ELFIAMCU: 7891 return new MCUX86_32TargetInfo(Triple); 7892 default: 7893 return new X86_32TargetInfo(Triple); 7894 } 7895 7896 case llvm::Triple::x86_64: 7897 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7898 return new DarwinX86_64TargetInfo(Triple); 7899 7900 switch (os) { 7901 case llvm::Triple::CloudABI: 7902 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7903 case llvm::Triple::Linux: { 7904 switch (Triple.getEnvironment()) { 7905 default: 7906 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7907 case llvm::Triple::Android: 7908 return new AndroidX86_64TargetInfo(Triple); 7909 } 7910 } 7911 case llvm::Triple::DragonFly: 7912 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7913 case llvm::Triple::NetBSD: 7914 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7915 case llvm::Triple::OpenBSD: 7916 return new OpenBSDX86_64TargetInfo(Triple); 7917 case llvm::Triple::Bitrig: 7918 return new BitrigX86_64TargetInfo(Triple); 7919 case llvm::Triple::FreeBSD: 7920 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7921 case llvm::Triple::KFreeBSD: 7922 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7923 case llvm::Triple::Solaris: 7924 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7925 case llvm::Triple::Win32: { 7926 switch (Triple.getEnvironment()) { 7927 case llvm::Triple::Cygnus: 7928 return new CygwinX86_64TargetInfo(Triple); 7929 case llvm::Triple::GNU: 7930 return new MinGWX86_64TargetInfo(Triple); 7931 case llvm::Triple::MSVC: 7932 default: // Assume MSVC for unknown environments 7933 return new MicrosoftX86_64TargetInfo(Triple); 7934 } 7935 } 7936 case llvm::Triple::NaCl: 7937 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7938 case llvm::Triple::PS4: 7939 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7940 default: 7941 return new X86_64TargetInfo(Triple); 7942 } 7943 7944 case llvm::Triple::spir: { 7945 if (Triple.getOS() != llvm::Triple::UnknownOS || 7946 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7947 return nullptr; 7948 return new SPIR32TargetInfo(Triple); 7949 } 7950 case llvm::Triple::spir64: { 7951 if (Triple.getOS() != llvm::Triple::UnknownOS || 7952 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7953 return nullptr; 7954 return new SPIR64TargetInfo(Triple); 7955 } 7956 case llvm::Triple::wasm32: 7957 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7958 return nullptr; 7959 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7960 case llvm::Triple::wasm64: 7961 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7962 return nullptr; 7963 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7964 } 7965 } 7966 7967 /// CreateTargetInfo - Return the target info object for the specified target 7968 /// options. 7969 TargetInfo * 7970 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7971 const std::shared_ptr<TargetOptions> &Opts) { 7972 llvm::Triple Triple(Opts->Triple); 7973 7974 // Construct the target 7975 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7976 if (!Target) { 7977 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7978 return nullptr; 7979 } 7980 Target->TargetOpts = Opts; 7981 7982 // Set the target CPU if specified. 7983 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7984 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7985 return nullptr; 7986 } 7987 7988 // Set the target ABI if specified. 7989 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7990 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7991 return nullptr; 7992 } 7993 7994 // Set the fp math unit. 7995 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7996 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7997 return nullptr; 7998 } 7999 8000 // Compute the default target features, we need the target to handle this 8001 // because features may have dependencies on one another. 8002 llvm::StringMap<bool> Features; 8003 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8004 Opts->FeaturesAsWritten)) 8005 return nullptr; 8006 8007 // Add the features to the compile options. 8008 Opts->Features.clear(); 8009 for (const auto &F : Features) 8010 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8011 8012 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8013 return nullptr; 8014 8015 return Target.release(); 8016 } 8017