1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 namespace {
187 template<typename Target>
188 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
193                      this->PlatformMinVersion);
194   }
195 
196 public:
197   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
198     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
199     this->MCountName = "\01mcount";
200   }
201 
202   std::string isValidSectionSpecifier(StringRef SR) const override {
203     // Let MCSectionMachO validate this.
204     StringRef Segment, Section;
205     unsigned TAA, StubSize;
206     bool HasTAA;
207     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
208                                                        TAA, HasTAA, StubSize);
209   }
210 
211   const char *getStaticInitSectionSpecifier() const override {
212     // FIXME: We should return 0 when building kexts.
213     return "__TEXT,__StaticInit,regular,pure_instructions";
214   }
215 
216   /// Darwin does not support protected visibility.  Darwin's "default"
217   /// is very similar to ELF's "protected";  Darwin requires a "weak"
218   /// attribute on declarations that can be dynamically replaced.
219   bool hasProtectedVisibility() const override {
220     return false;
221   }
222 };
223 
224 
225 // DragonFlyBSD Target
226 template<typename Target>
227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 protected:
229   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
230                     MacroBuilder &Builder) const override {
231     // DragonFly defines; list based off of gcc output
232     Builder.defineMacro("__DragonFly__");
233     Builder.defineMacro("__DragonFly_cc_version", "100001");
234     Builder.defineMacro("__ELF__");
235     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
236     Builder.defineMacro("__tune_i386__");
237     DefineStd(Builder, "unix", Opts);
238   }
239 public:
240   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
241       : OSTargetInfo<Target>(Triple) {
242     this->UserLabelPrefix = "";
243 
244     switch (Triple.getArch()) {
245     default:
246     case llvm::Triple::x86:
247     case llvm::Triple::x86_64:
248       this->MCountName = ".mcount";
249       break;
250     }
251   }
252 };
253 
254 // FreeBSD Target
255 template<typename Target>
256 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 protected:
258   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
259                     MacroBuilder &Builder) const override {
260     // FreeBSD defines; list based off of gcc output
261 
262     unsigned Release = Triple.getOSMajorVersion();
263     if (Release == 0U)
264       Release = 8;
265 
266     Builder.defineMacro("__FreeBSD__", Twine(Release));
267     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
268     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
269     DefineStd(Builder, "unix", Opts);
270     Builder.defineMacro("__ELF__");
271 
272     // On FreeBSD, wchar_t contains the number of the code point as
273     // used by the character set of the locale. These character sets are
274     // not necessarily a superset of ASCII.
275     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
276   }
277 public:
278   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
279     this->UserLabelPrefix = "";
280 
281     switch (Triple.getArch()) {
282     default:
283     case llvm::Triple::x86:
284     case llvm::Triple::x86_64:
285       this->MCountName = ".mcount";
286       break;
287     case llvm::Triple::mips:
288     case llvm::Triple::mipsel:
289     case llvm::Triple::ppc:
290     case llvm::Triple::ppc64:
291     case llvm::Triple::ppc64le:
292       this->MCountName = "_mcount";
293       break;
294     case llvm::Triple::arm:
295       this->MCountName = "__mcount";
296       break;
297     }
298   }
299 };
300 
301 // GNU/kFreeBSD Target
302 template<typename Target>
303 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
304 protected:
305   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
306                     MacroBuilder &Builder) const override {
307     // GNU/kFreeBSD defines; list based off of gcc output
308 
309     DefineStd(Builder, "unix", Opts);
310     Builder.defineMacro("__FreeBSD_kernel__");
311     Builder.defineMacro("__GLIBC__");
312     Builder.defineMacro("__ELF__");
313     if (Opts.POSIXThreads)
314       Builder.defineMacro("_REENTRANT");
315     if (Opts.CPlusPlus)
316       Builder.defineMacro("_GNU_SOURCE");
317   }
318 public:
319   KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
320     this->UserLabelPrefix = "";
321   }
322 };
323 
324 // Minix Target
325 template<typename Target>
326 class MinixTargetInfo : public OSTargetInfo<Target> {
327 protected:
328   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
329                     MacroBuilder &Builder) const override {
330     // Minix defines
331 
332     Builder.defineMacro("__minix", "3");
333     Builder.defineMacro("_EM_WSIZE", "4");
334     Builder.defineMacro("_EM_PSIZE", "4");
335     Builder.defineMacro("_EM_SSIZE", "2");
336     Builder.defineMacro("_EM_LSIZE", "4");
337     Builder.defineMacro("_EM_FSIZE", "4");
338     Builder.defineMacro("_EM_DSIZE", "8");
339     Builder.defineMacro("__ELF__");
340     DefineStd(Builder, "unix", Opts);
341   }
342 public:
343   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
344     this->UserLabelPrefix = "";
345   }
346 };
347 
348 // Linux target
349 template<typename Target>
350 class LinuxTargetInfo : public OSTargetInfo<Target> {
351 protected:
352   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
353                     MacroBuilder &Builder) const override {
354     // Linux defines; list based off of gcc output
355     DefineStd(Builder, "unix", Opts);
356     DefineStd(Builder, "linux", Opts);
357     Builder.defineMacro("__gnu_linux__");
358     Builder.defineMacro("__ELF__");
359     if (Triple.getEnvironment() == llvm::Triple::Android)
360       Builder.defineMacro("__ANDROID__", "1");
361     if (Opts.POSIXThreads)
362       Builder.defineMacro("_REENTRANT");
363     if (Opts.CPlusPlus)
364       Builder.defineMacro("_GNU_SOURCE");
365   }
366 public:
367   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368     this->UserLabelPrefix = "";
369     this->WIntType = TargetInfo::UnsignedInt;
370 
371     switch (Triple.getArch()) {
372     default:
373       break;
374     case llvm::Triple::ppc:
375     case llvm::Triple::ppc64:
376     case llvm::Triple::ppc64le:
377       this->MCountName = "_mcount";
378       break;
379     }
380   }
381 
382   const char *getStaticInitSectionSpecifier() const override {
383     return ".text.startup";
384   }
385 };
386 
387 // NetBSD Target
388 template<typename Target>
389 class NetBSDTargetInfo : public OSTargetInfo<Target> {
390 protected:
391   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
392                     MacroBuilder &Builder) const override {
393     // NetBSD defines; list based off of gcc output
394     Builder.defineMacro("__NetBSD__");
395     Builder.defineMacro("__unix__");
396     Builder.defineMacro("__ELF__");
397     if (Opts.POSIXThreads)
398       Builder.defineMacro("_POSIX_THREADS");
399 
400     switch (Triple.getArch()) {
401     default:
402       break;
403     case llvm::Triple::arm:
404     case llvm::Triple::armeb:
405     case llvm::Triple::thumb:
406     case llvm::Triple::thumbeb:
407       Builder.defineMacro("__ARM_DWARF_EH__");
408       break;
409     }
410   }
411 public:
412   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
413     this->UserLabelPrefix = "";
414   }
415 };
416 
417 // OpenBSD Target
418 template<typename Target>
419 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
420 protected:
421   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
422                     MacroBuilder &Builder) const override {
423     // OpenBSD defines; list based off of gcc output
424 
425     Builder.defineMacro("__OpenBSD__");
426     DefineStd(Builder, "unix", Opts);
427     Builder.defineMacro("__ELF__");
428     if (Opts.POSIXThreads)
429       Builder.defineMacro("_REENTRANT");
430   }
431 public:
432   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
433     this->UserLabelPrefix = "";
434     this->TLSSupported = false;
435 
436       switch (Triple.getArch()) {
437         default:
438         case llvm::Triple::x86:
439         case llvm::Triple::x86_64:
440         case llvm::Triple::arm:
441         case llvm::Triple::sparc:
442           this->MCountName = "__mcount";
443           break;
444         case llvm::Triple::mips64:
445         case llvm::Triple::mips64el:
446         case llvm::Triple::ppc:
447         case llvm::Triple::sparcv9:
448           this->MCountName = "_mcount";
449           break;
450       }
451   }
452 };
453 
454 // Bitrig Target
455 template<typename Target>
456 class BitrigTargetInfo : public OSTargetInfo<Target> {
457 protected:
458   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
459                     MacroBuilder &Builder) const override {
460     // Bitrig defines; list based off of gcc output
461 
462     Builder.defineMacro("__Bitrig__");
463     DefineStd(Builder, "unix", Opts);
464     Builder.defineMacro("__ELF__");
465     if (Opts.POSIXThreads)
466       Builder.defineMacro("_REENTRANT");
467   }
468 public:
469   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
470     this->UserLabelPrefix = "";
471     this->MCountName = "__mcount";
472   }
473 };
474 
475 // PSP Target
476 template<typename Target>
477 class PSPTargetInfo : public OSTargetInfo<Target> {
478 protected:
479   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                     MacroBuilder &Builder) const override {
481     // PSP defines; list based on the output of the pspdev gcc toolchain.
482     Builder.defineMacro("PSP");
483     Builder.defineMacro("_PSP");
484     Builder.defineMacro("__psp__");
485     Builder.defineMacro("__ELF__");
486   }
487 public:
488   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
489     this->UserLabelPrefix = "";
490   }
491 };
492 
493 // PS3 PPU Target
494 template<typename Target>
495 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
496 protected:
497   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
498                     MacroBuilder &Builder) const override {
499     // PS3 PPU defines.
500     Builder.defineMacro("__PPC__");
501     Builder.defineMacro("__PPU__");
502     Builder.defineMacro("__CELLOS_LV2__");
503     Builder.defineMacro("__ELF__");
504     Builder.defineMacro("__LP32__");
505     Builder.defineMacro("_ARCH_PPC64");
506     Builder.defineMacro("__powerpc64__");
507   }
508 public:
509   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
510     this->UserLabelPrefix = "";
511     this->LongWidth = this->LongAlign = 32;
512     this->PointerWidth = this->PointerAlign = 32;
513     this->IntMaxType = TargetInfo::SignedLongLong;
514     this->Int64Type = TargetInfo::SignedLongLong;
515     this->SizeType = TargetInfo::UnsignedInt;
516     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
517   }
518 };
519 
520 // Solaris target
521 template<typename Target>
522 class SolarisTargetInfo : public OSTargetInfo<Target> {
523 protected:
524   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525                     MacroBuilder &Builder) const override {
526     DefineStd(Builder, "sun", Opts);
527     DefineStd(Builder, "unix", Opts);
528     Builder.defineMacro("__ELF__");
529     Builder.defineMacro("__svr4__");
530     Builder.defineMacro("__SVR4");
531     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
532     // newer, but to 500 for everything else.  feature_test.h has a check to
533     // ensure that you are not using C99 with an old version of X/Open or C89
534     // with a new version.
535     if (Opts.C99)
536       Builder.defineMacro("_XOPEN_SOURCE", "600");
537     else
538       Builder.defineMacro("_XOPEN_SOURCE", "500");
539     if (Opts.CPlusPlus)
540       Builder.defineMacro("__C99FEATURES__");
541     Builder.defineMacro("_LARGEFILE_SOURCE");
542     Builder.defineMacro("_LARGEFILE64_SOURCE");
543     Builder.defineMacro("__EXTENSIONS__");
544     Builder.defineMacro("_REENTRANT");
545   }
546 public:
547   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
548     this->UserLabelPrefix = "";
549     this->WCharType = this->SignedInt;
550     // FIXME: WIntType should be SignedLong
551   }
552 };
553 
554 // Windows target
555 template<typename Target>
556 class WindowsTargetInfo : public OSTargetInfo<Target> {
557 protected:
558   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
559                     MacroBuilder &Builder) const override {
560     Builder.defineMacro("_WIN32");
561   }
562   void getVisualStudioDefines(const LangOptions &Opts,
563                               MacroBuilder &Builder) const {
564     if (Opts.CPlusPlus) {
565       if (Opts.RTTIData)
566         Builder.defineMacro("_CPPRTTI");
567 
568       if (Opts.Exceptions)
569         Builder.defineMacro("_CPPUNWIND");
570     }
571 
572     if (!Opts.CharIsSigned)
573       Builder.defineMacro("_CHAR_UNSIGNED");
574 
575     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
576     //        but it works for now.
577     if (Opts.POSIXThreads)
578       Builder.defineMacro("_MT");
579 
580     if (Opts.MSCompatibilityVersion) {
581       Builder.defineMacro("_MSC_VER",
582                           Twine(Opts.MSCompatibilityVersion / 100000));
583       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
584       // FIXME We cannot encode the revision information into 32-bits
585       Builder.defineMacro("_MSC_BUILD", Twine(1));
586     }
587 
588     if (Opts.MicrosoftExt) {
589       Builder.defineMacro("_MSC_EXTENSIONS");
590 
591       if (Opts.CPlusPlus11) {
592         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
593         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
594         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
595       }
596     }
597 
598     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
599   }
600 
601 public:
602   WindowsTargetInfo(const llvm::Triple &Triple)
603       : OSTargetInfo<Target>(Triple) {}
604 };
605 
606 template <typename Target>
607 class NaClTargetInfo : public OSTargetInfo<Target> {
608 protected:
609   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
610                     MacroBuilder &Builder) const override {
611     if (Opts.POSIXThreads)
612       Builder.defineMacro("_REENTRANT");
613     if (Opts.CPlusPlus)
614       Builder.defineMacro("_GNU_SOURCE");
615 
616     DefineStd(Builder, "unix", Opts);
617     Builder.defineMacro("__ELF__");
618     Builder.defineMacro("__native_client__");
619   }
620 
621 public:
622   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
623     this->UserLabelPrefix = "";
624     this->LongAlign = 32;
625     this->LongWidth = 32;
626     this->PointerAlign = 32;
627     this->PointerWidth = 32;
628     this->IntMaxType = TargetInfo::SignedLongLong;
629     this->Int64Type = TargetInfo::SignedLongLong;
630     this->DoubleAlign = 64;
631     this->LongDoubleWidth = 64;
632     this->LongDoubleAlign = 64;
633     this->LongLongWidth = 64;
634     this->LongLongAlign = 64;
635     this->SizeType = TargetInfo::UnsignedInt;
636     this->PtrDiffType = TargetInfo::SignedInt;
637     this->IntPtrType = TargetInfo::SignedInt;
638     // RegParmMax is inherited from the underlying architecture
639     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
640     if (Triple.getArch() == llvm::Triple::arm) {
641       this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128";
642     } else if (Triple.getArch() == llvm::Triple::x86) {
643       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
644     } else if (Triple.getArch() == llvm::Triple::x86_64) {
645       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
646     } else if (Triple.getArch() == llvm::Triple::mipsel) {
647       // Handled on mips' setDescriptionString.
648     } else {
649       assert(Triple.getArch() == llvm::Triple::le32);
650       this->DescriptionString = "e-p:32:32-i64:64";
651     }
652   }
653   typename Target::CallingConvCheckResult checkCallingConvention(
654       CallingConv CC) const override {
655     return CC == CC_PnaclCall ? Target::CCCR_OK :
656         Target::checkCallingConvention(CC);
657   }
658 };
659 } // end anonymous namespace.
660 
661 //===----------------------------------------------------------------------===//
662 // Specific target implementations.
663 //===----------------------------------------------------------------------===//
664 
665 namespace {
666 // PPC abstract base class
667 class PPCTargetInfo : public TargetInfo {
668   static const Builtin::Info BuiltinInfo[];
669   static const char * const GCCRegNames[];
670   static const TargetInfo::GCCRegAlias GCCRegAliases[];
671   std::string CPU;
672 
673   // Target cpu features.
674   bool HasVSX;
675   bool HasP8Vector;
676 
677 protected:
678   std::string ABI;
679 
680 public:
681   PPCTargetInfo(const llvm::Triple &Triple)
682     : TargetInfo(Triple), HasVSX(false), HasP8Vector(false) {
683     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
684     LongDoubleWidth = LongDoubleAlign = 128;
685     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
686   }
687 
688   /// \brief Flags for architecture specific defines.
689   typedef enum {
690     ArchDefineNone  = 0,
691     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
692     ArchDefinePpcgr = 1 << 1,
693     ArchDefinePpcsq = 1 << 2,
694     ArchDefine440   = 1 << 3,
695     ArchDefine603   = 1 << 4,
696     ArchDefine604   = 1 << 5,
697     ArchDefinePwr4  = 1 << 6,
698     ArchDefinePwr5  = 1 << 7,
699     ArchDefinePwr5x = 1 << 8,
700     ArchDefinePwr6  = 1 << 9,
701     ArchDefinePwr6x = 1 << 10,
702     ArchDefinePwr7  = 1 << 11,
703     ArchDefinePwr8  = 1 << 12,
704     ArchDefineA2    = 1 << 13,
705     ArchDefineA2q   = 1 << 14
706   } ArchDefineTypes;
707 
708   // Note: GCC recognizes the following additional cpus:
709   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
710   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
711   //  titan, rs64.
712   bool setCPU(const std::string &Name) override {
713     bool CPUKnown = llvm::StringSwitch<bool>(Name)
714       .Case("generic", true)
715       .Case("440", true)
716       .Case("450", true)
717       .Case("601", true)
718       .Case("602", true)
719       .Case("603", true)
720       .Case("603e", true)
721       .Case("603ev", true)
722       .Case("604", true)
723       .Case("604e", true)
724       .Case("620", true)
725       .Case("630", true)
726       .Case("g3", true)
727       .Case("7400", true)
728       .Case("g4", true)
729       .Case("7450", true)
730       .Case("g4+", true)
731       .Case("750", true)
732       .Case("970", true)
733       .Case("g5", true)
734       .Case("a2", true)
735       .Case("a2q", true)
736       .Case("e500mc", true)
737       .Case("e5500", true)
738       .Case("power3", true)
739       .Case("pwr3", true)
740       .Case("power4", true)
741       .Case("pwr4", true)
742       .Case("power5", true)
743       .Case("pwr5", true)
744       .Case("power5x", true)
745       .Case("pwr5x", true)
746       .Case("power6", true)
747       .Case("pwr6", true)
748       .Case("power6x", true)
749       .Case("pwr6x", true)
750       .Case("power7", true)
751       .Case("pwr7", true)
752       .Case("power8", true)
753       .Case("pwr8", true)
754       .Case("powerpc", true)
755       .Case("ppc", true)
756       .Case("powerpc64", true)
757       .Case("ppc64", true)
758       .Case("powerpc64le", true)
759       .Case("ppc64le", true)
760       .Default(false);
761 
762     if (CPUKnown)
763       CPU = Name;
764 
765     return CPUKnown;
766   }
767 
768 
769   StringRef getABI() const override { return ABI; }
770 
771   void getTargetBuiltins(const Builtin::Info *&Records,
772                          unsigned &NumRecords) const override {
773     Records = BuiltinInfo;
774     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
775   }
776 
777   bool isCLZForZeroUndef() const override { return false; }
778 
779   void getTargetDefines(const LangOptions &Opts,
780                         MacroBuilder &Builder) const override;
781 
782   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
783 
784   bool handleTargetFeatures(std::vector<std::string> &Features,
785                             DiagnosticsEngine &Diags) override;
786   bool hasFeature(StringRef Feature) const override;
787 
788   void getGCCRegNames(const char * const *&Names,
789                       unsigned &NumNames) const override;
790   void getGCCRegAliases(const GCCRegAlias *&Aliases,
791                         unsigned &NumAliases) const override;
792   bool validateAsmConstraint(const char *&Name,
793                              TargetInfo::ConstraintInfo &Info) const override {
794     switch (*Name) {
795     default: return false;
796     case 'O': // Zero
797       break;
798     case 'b': // Base register
799     case 'f': // Floating point register
800       Info.setAllowsRegister();
801       break;
802     // FIXME: The following are added to allow parsing.
803     // I just took a guess at what the actions should be.
804     // Also, is more specific checking needed?  I.e. specific registers?
805     case 'd': // Floating point register (containing 64-bit value)
806     case 'v': // Altivec vector register
807       Info.setAllowsRegister();
808       break;
809     case 'w':
810       switch (Name[1]) {
811         case 'd':// VSX vector register to hold vector double data
812         case 'f':// VSX vector register to hold vector float data
813         case 's':// VSX vector register to hold scalar float data
814         case 'a':// Any VSX register
815         case 'c':// An individual CR bit
816           break;
817         default:
818           return false;
819       }
820       Info.setAllowsRegister();
821       Name++; // Skip over 'w'.
822       break;
823     case 'h': // `MQ', `CTR', or `LINK' register
824     case 'q': // `MQ' register
825     case 'c': // `CTR' register
826     case 'l': // `LINK' register
827     case 'x': // `CR' register (condition register) number 0
828     case 'y': // `CR' register (condition register)
829     case 'z': // `XER[CA]' carry bit (part of the XER register)
830       Info.setAllowsRegister();
831       break;
832     case 'I': // Signed 16-bit constant
833     case 'J': // Unsigned 16-bit constant shifted left 16 bits
834               //  (use `L' instead for SImode constants)
835     case 'K': // Unsigned 16-bit constant
836     case 'L': // Signed 16-bit constant shifted left 16 bits
837     case 'M': // Constant larger than 31
838     case 'N': // Exact power of 2
839     case 'P': // Constant whose negation is a signed 16-bit constant
840     case 'G': // Floating point constant that can be loaded into a
841               // register with one instruction per word
842     case 'H': // Integer/Floating point constant that can be loaded
843               // into a register using three instructions
844       break;
845     case 'm': // Memory operand. Note that on PowerPC targets, m can
846               // include addresses that update the base register. It
847               // is therefore only safe to use `m' in an asm statement
848               // if that asm statement accesses the operand exactly once.
849               // The asm statement must also use `%U<opno>' as a
850               // placeholder for the "update" flag in the corresponding
851               // load or store instruction. For example:
852               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
853               // is correct but:
854               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
855               // is not. Use es rather than m if you don't want the base
856               // register to be updated.
857     case 'e':
858       if (Name[1] != 's')
859           return false;
860               // es: A "stable" memory operand; that is, one which does not
861               // include any automodification of the base register. Unlike
862               // `m', this constraint can be used in asm statements that
863               // might access the operand several times, or that might not
864               // access it at all.
865       Info.setAllowsMemory();
866       Name++; // Skip over 'e'.
867       break;
868     case 'Q': // Memory operand that is an offset from a register (it is
869               // usually better to use `m' or `es' in asm statements)
870     case 'Z': // Memory operand that is an indexed or indirect from a
871               // register (it is usually better to use `m' or `es' in
872               // asm statements)
873       Info.setAllowsMemory();
874       Info.setAllowsRegister();
875       break;
876     case 'R': // AIX TOC entry
877     case 'a': // Address operand that is an indexed or indirect from a
878               // register (`p' is preferable for asm statements)
879     case 'S': // Constant suitable as a 64-bit mask operand
880     case 'T': // Constant suitable as a 32-bit mask operand
881     case 'U': // System V Release 4 small data area reference
882     case 't': // AND masks that can be performed by two rldic{l, r}
883               // instructions
884     case 'W': // Vector constant that does not require memory
885     case 'j': // Vector constant that is all zeros.
886       break;
887     // End FIXME.
888     }
889     return true;
890   }
891   std::string convertConstraint(const char *&Constraint) const override {
892     std::string R;
893     switch (*Constraint) {
894     case 'e':
895     case 'w':
896       // Two-character constraint; add "^" hint for later parsing.
897       R = std::string("^") + std::string(Constraint, 2);
898       Constraint++;
899       break;
900     default:
901       return TargetInfo::convertConstraint(Constraint);
902     }
903     return R;
904   }
905   const char *getClobbers() const override {
906     return "";
907   }
908   int getEHDataRegisterNumber(unsigned RegNo) const override {
909     if (RegNo == 0) return 3;
910     if (RegNo == 1) return 4;
911     return -1;
912   }
913 };
914 
915 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
916 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
917 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
918                                               ALL_LANGUAGES },
919 #include "clang/Basic/BuiltinsPPC.def"
920 };
921 
922   /// handleTargetFeatures - Perform initialization based on the user
923 /// configured set of features.
924 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
925                                          DiagnosticsEngine &Diags) {
926   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
927     // Ignore disabled features.
928     if (Features[i][0] == '-')
929       continue;
930 
931     StringRef Feature = StringRef(Features[i]).substr(1);
932 
933     if (Feature == "vsx") {
934       HasVSX = true;
935       continue;
936     }
937 
938     if (Feature == "power8-vector") {
939       HasP8Vector = true;
940       continue;
941     }
942 
943     // TODO: Finish this list and add an assert that we've handled them
944     // all.
945   }
946 
947   return true;
948 }
949 
950 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
951 /// #defines that are not tied to a specific subtarget.
952 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
953                                      MacroBuilder &Builder) const {
954   // Target identification.
955   Builder.defineMacro("__ppc__");
956   Builder.defineMacro("__PPC__");
957   Builder.defineMacro("_ARCH_PPC");
958   Builder.defineMacro("__powerpc__");
959   Builder.defineMacro("__POWERPC__");
960   if (PointerWidth == 64) {
961     Builder.defineMacro("_ARCH_PPC64");
962     Builder.defineMacro("__powerpc64__");
963     Builder.defineMacro("__ppc64__");
964     Builder.defineMacro("__PPC64__");
965   }
966 
967   // Target properties.
968   if (getTriple().getArch() == llvm::Triple::ppc64le) {
969     Builder.defineMacro("_LITTLE_ENDIAN");
970   } else {
971     if (getTriple().getOS() != llvm::Triple::NetBSD &&
972         getTriple().getOS() != llvm::Triple::OpenBSD)
973       Builder.defineMacro("_BIG_ENDIAN");
974   }
975 
976   // ABI options.
977   if (ABI == "elfv1")
978     Builder.defineMacro("_CALL_ELF", "1");
979   if (ABI == "elfv2")
980     Builder.defineMacro("_CALL_ELF", "2");
981 
982   // Subtarget options.
983   Builder.defineMacro("__NATURAL_ALIGNMENT__");
984   Builder.defineMacro("__REGISTER_PREFIX__", "");
985 
986   // FIXME: Should be controlled by command line option.
987   if (LongDoubleWidth == 128)
988     Builder.defineMacro("__LONG_DOUBLE_128__");
989 
990   if (Opts.AltiVec) {
991     Builder.defineMacro("__VEC__", "10206");
992     Builder.defineMacro("__ALTIVEC__");
993   }
994 
995   // CPU identification.
996   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
997     .Case("440",   ArchDefineName)
998     .Case("450",   ArchDefineName | ArchDefine440)
999     .Case("601",   ArchDefineName)
1000     .Case("602",   ArchDefineName | ArchDefinePpcgr)
1001     .Case("603",   ArchDefineName | ArchDefinePpcgr)
1002     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1003     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
1004     .Case("604",   ArchDefineName | ArchDefinePpcgr)
1005     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1006     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1007     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1008     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1009     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1010     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1011     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1012                      | ArchDefinePpcsq)
1013     .Case("a2",    ArchDefineA2)
1014     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1015     .Case("pwr3",  ArchDefinePpcgr)
1016     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1017     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1018                      | ArchDefinePpcsq)
1019     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1020                      | ArchDefinePpcgr | ArchDefinePpcsq)
1021     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1022                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1023     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1024                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1025                      | ArchDefinePpcsq)
1026     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1027                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1028                      | ArchDefinePpcgr | ArchDefinePpcsq)
1029     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1030                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1031                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("power3",  ArchDefinePpcgr)
1033     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1034     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1035                        | ArchDefinePpcsq)
1036     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1037                        | ArchDefinePpcgr | ArchDefinePpcsq)
1038     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1039                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1040     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1041                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1042                        | ArchDefinePpcsq)
1043     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1044                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1045                        | ArchDefinePpcgr | ArchDefinePpcsq)
1046     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1047                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1048                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1049     .Default(ArchDefineNone);
1050 
1051   if (defs & ArchDefineName)
1052     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1053   if (defs & ArchDefinePpcgr)
1054     Builder.defineMacro("_ARCH_PPCGR");
1055   if (defs & ArchDefinePpcsq)
1056     Builder.defineMacro("_ARCH_PPCSQ");
1057   if (defs & ArchDefine440)
1058     Builder.defineMacro("_ARCH_440");
1059   if (defs & ArchDefine603)
1060     Builder.defineMacro("_ARCH_603");
1061   if (defs & ArchDefine604)
1062     Builder.defineMacro("_ARCH_604");
1063   if (defs & ArchDefinePwr4)
1064     Builder.defineMacro("_ARCH_PWR4");
1065   if (defs & ArchDefinePwr5)
1066     Builder.defineMacro("_ARCH_PWR5");
1067   if (defs & ArchDefinePwr5x)
1068     Builder.defineMacro("_ARCH_PWR5X");
1069   if (defs & ArchDefinePwr6)
1070     Builder.defineMacro("_ARCH_PWR6");
1071   if (defs & ArchDefinePwr6x)
1072     Builder.defineMacro("_ARCH_PWR6X");
1073   if (defs & ArchDefinePwr7)
1074     Builder.defineMacro("_ARCH_PWR7");
1075   if (defs & ArchDefinePwr8)
1076     Builder.defineMacro("_ARCH_PWR8");
1077   if (defs & ArchDefineA2)
1078     Builder.defineMacro("_ARCH_A2");
1079   if (defs & ArchDefineA2q) {
1080     Builder.defineMacro("_ARCH_A2Q");
1081     Builder.defineMacro("_ARCH_QP");
1082   }
1083 
1084   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1085     Builder.defineMacro("__bg__");
1086     Builder.defineMacro("__THW_BLUEGENE__");
1087     Builder.defineMacro("__bgq__");
1088     Builder.defineMacro("__TOS_BGQ__");
1089   }
1090 
1091   if (HasVSX)
1092     Builder.defineMacro("__VSX__");
1093   if (HasP8Vector)
1094     Builder.defineMacro("__POWER8_VECTOR__");
1095 
1096   // FIXME: The following are not yet generated here by Clang, but are
1097   //        generated by GCC:
1098   //
1099   //   _SOFT_FLOAT_
1100   //   __RECIP_PRECISION__
1101   //   __APPLE_ALTIVEC__
1102   //   __RECIP__
1103   //   __RECIPF__
1104   //   __RSQRTE__
1105   //   __RSQRTEF__
1106   //   _SOFT_DOUBLE_
1107   //   __NO_LWSYNC__
1108   //   __HAVE_BSWAP__
1109   //   __LONGDOUBLE128
1110   //   __CMODEL_MEDIUM__
1111   //   __CMODEL_LARGE__
1112   //   _CALL_SYSV
1113   //   _CALL_DARWIN
1114   //   __NO_FPRS__
1115 }
1116 
1117 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1118   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1119     .Case("7400", true)
1120     .Case("g4", true)
1121     .Case("7450", true)
1122     .Case("g4+", true)
1123     .Case("970", true)
1124     .Case("g5", true)
1125     .Case("pwr6", true)
1126     .Case("pwr7", true)
1127     .Case("pwr8", true)
1128     .Case("ppc64", true)
1129     .Case("ppc64le", true)
1130     .Default(false);
1131 
1132   Features["qpx"] = (CPU == "a2q");
1133 
1134   if (!ABI.empty())
1135     Features[ABI] = true;
1136 }
1137 
1138 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1139   return llvm::StringSwitch<bool>(Feature)
1140     .Case("powerpc", true)
1141     .Case("vsx", HasVSX)
1142     .Case("power8-vector", HasP8Vector)
1143     .Default(false);
1144 }
1145 
1146 
1147 const char * const PPCTargetInfo::GCCRegNames[] = {
1148   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1149   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1150   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1151   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1152   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1153   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1154   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1155   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1156   "mq", "lr", "ctr", "ap",
1157   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1158   "xer",
1159   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1160   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1161   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1162   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1163   "vrsave", "vscr",
1164   "spe_acc", "spefscr",
1165   "sfp"
1166 };
1167 
1168 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1169                                    unsigned &NumNames) const {
1170   Names = GCCRegNames;
1171   NumNames = llvm::array_lengthof(GCCRegNames);
1172 }
1173 
1174 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1175   // While some of these aliases do map to different registers
1176   // they still share the same register name.
1177   { { "0" }, "r0" },
1178   { { "1"}, "r1" },
1179   { { "2" }, "r2" },
1180   { { "3" }, "r3" },
1181   { { "4" }, "r4" },
1182   { { "5" }, "r5" },
1183   { { "6" }, "r6" },
1184   { { "7" }, "r7" },
1185   { { "8" }, "r8" },
1186   { { "9" }, "r9" },
1187   { { "10" }, "r10" },
1188   { { "11" }, "r11" },
1189   { { "12" }, "r12" },
1190   { { "13" }, "r13" },
1191   { { "14" }, "r14" },
1192   { { "15" }, "r15" },
1193   { { "16" }, "r16" },
1194   { { "17" }, "r17" },
1195   { { "18" }, "r18" },
1196   { { "19" }, "r19" },
1197   { { "20" }, "r20" },
1198   { { "21" }, "r21" },
1199   { { "22" }, "r22" },
1200   { { "23" }, "r23" },
1201   { { "24" }, "r24" },
1202   { { "25" }, "r25" },
1203   { { "26" }, "r26" },
1204   { { "27" }, "r27" },
1205   { { "28" }, "r28" },
1206   { { "29" }, "r29" },
1207   { { "30" }, "r30" },
1208   { { "31" }, "r31" },
1209   { { "fr0" }, "f0" },
1210   { { "fr1" }, "f1" },
1211   { { "fr2" }, "f2" },
1212   { { "fr3" }, "f3" },
1213   { { "fr4" }, "f4" },
1214   { { "fr5" }, "f5" },
1215   { { "fr6" }, "f6" },
1216   { { "fr7" }, "f7" },
1217   { { "fr8" }, "f8" },
1218   { { "fr9" }, "f9" },
1219   { { "fr10" }, "f10" },
1220   { { "fr11" }, "f11" },
1221   { { "fr12" }, "f12" },
1222   { { "fr13" }, "f13" },
1223   { { "fr14" }, "f14" },
1224   { { "fr15" }, "f15" },
1225   { { "fr16" }, "f16" },
1226   { { "fr17" }, "f17" },
1227   { { "fr18" }, "f18" },
1228   { { "fr19" }, "f19" },
1229   { { "fr20" }, "f20" },
1230   { { "fr21" }, "f21" },
1231   { { "fr22" }, "f22" },
1232   { { "fr23" }, "f23" },
1233   { { "fr24" }, "f24" },
1234   { { "fr25" }, "f25" },
1235   { { "fr26" }, "f26" },
1236   { { "fr27" }, "f27" },
1237   { { "fr28" }, "f28" },
1238   { { "fr29" }, "f29" },
1239   { { "fr30" }, "f30" },
1240   { { "fr31" }, "f31" },
1241   { { "cc" }, "cr0" },
1242 };
1243 
1244 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1245                                      unsigned &NumAliases) const {
1246   Aliases = GCCRegAliases;
1247   NumAliases = llvm::array_lengthof(GCCRegAliases);
1248 }
1249 } // end anonymous namespace.
1250 
1251 namespace {
1252 class PPC32TargetInfo : public PPCTargetInfo {
1253 public:
1254   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1255     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1256 
1257     switch (getTriple().getOS()) {
1258     case llvm::Triple::Linux:
1259     case llvm::Triple::FreeBSD:
1260     case llvm::Triple::NetBSD:
1261       SizeType = UnsignedInt;
1262       PtrDiffType = SignedInt;
1263       IntPtrType = SignedInt;
1264       break;
1265     default:
1266       break;
1267     }
1268 
1269     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1270       LongDoubleWidth = LongDoubleAlign = 64;
1271       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1272     }
1273 
1274     // PPC32 supports atomics up to 4 bytes.
1275     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1276   }
1277 
1278   BuiltinVaListKind getBuiltinVaListKind() const override {
1279     // This is the ELF definition, and is overridden by the Darwin sub-target
1280     return TargetInfo::PowerABIBuiltinVaList;
1281   }
1282 };
1283 } // end anonymous namespace.
1284 
1285 // Note: ABI differences may eventually require us to have a separate
1286 // TargetInfo for little endian.
1287 namespace {
1288 class PPC64TargetInfo : public PPCTargetInfo {
1289 public:
1290   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1291     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1292     IntMaxType = SignedLong;
1293     Int64Type = SignedLong;
1294 
1295     if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1296       DescriptionString = "e-m:e-i64:64-n32:64";
1297       ABI = "elfv2";
1298     } else {
1299       DescriptionString = "E-m:e-i64:64-n32:64";
1300       ABI = "elfv1";
1301     }
1302 
1303     switch (getTriple().getOS()) {
1304     case llvm::Triple::FreeBSD:
1305       LongDoubleWidth = LongDoubleAlign = 64;
1306       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1307       break;
1308     case llvm::Triple::NetBSD:
1309       IntMaxType = SignedLongLong;
1310       Int64Type = SignedLongLong;
1311       break;
1312     default:
1313       break;
1314     }
1315 
1316     // PPC64 supports atomics up to 8 bytes.
1317     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1318   }
1319   BuiltinVaListKind getBuiltinVaListKind() const override {
1320     return TargetInfo::CharPtrBuiltinVaList;
1321   }
1322   // PPC64 Linux-specifc ABI options.
1323   bool setABI(const std::string &Name) override {
1324     if (Name == "elfv1" || Name == "elfv2") {
1325       ABI = Name;
1326       return true;
1327     }
1328     return false;
1329   }
1330 };
1331 } // end anonymous namespace.
1332 
1333 
1334 namespace {
1335 class DarwinPPC32TargetInfo :
1336   public DarwinTargetInfo<PPC32TargetInfo> {
1337 public:
1338   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1339       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1340     HasAlignMac68kSupport = true;
1341     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1342     PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1343     LongLongAlign = 32;
1344     SuitableAlign = 128;
1345     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1346   }
1347   BuiltinVaListKind getBuiltinVaListKind() const override {
1348     return TargetInfo::CharPtrBuiltinVaList;
1349   }
1350 };
1351 
1352 class DarwinPPC64TargetInfo :
1353   public DarwinTargetInfo<PPC64TargetInfo> {
1354 public:
1355   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1356       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1357     HasAlignMac68kSupport = true;
1358     SuitableAlign = 128;
1359     DescriptionString = "E-m:o-i64:64-n32:64";
1360   }
1361 };
1362 } // end anonymous namespace.
1363 
1364 namespace {
1365   static const unsigned NVPTXAddrSpaceMap[] = {
1366     1,    // opencl_global
1367     3,    // opencl_local
1368     4,    // opencl_constant
1369     1,    // cuda_device
1370     4,    // cuda_constant
1371     3,    // cuda_shared
1372   };
1373   class NVPTXTargetInfo : public TargetInfo {
1374     static const char * const GCCRegNames[];
1375     static const Builtin::Info BuiltinInfo[];
1376   public:
1377     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1378       BigEndian = false;
1379       TLSSupported = false;
1380       LongWidth = LongAlign = 64;
1381       AddrSpaceMap = &NVPTXAddrSpaceMap;
1382       UseAddrSpaceMapMangling = true;
1383       // Define available target features
1384       // These must be defined in sorted order!
1385       NoAsmVariants = true;
1386     }
1387     void getTargetDefines(const LangOptions &Opts,
1388                           MacroBuilder &Builder) const override {
1389       Builder.defineMacro("__PTX__");
1390       Builder.defineMacro("__NVPTX__");
1391     }
1392     void getTargetBuiltins(const Builtin::Info *&Records,
1393                            unsigned &NumRecords) const override {
1394       Records = BuiltinInfo;
1395       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1396     }
1397     bool hasFeature(StringRef Feature) const override {
1398       return Feature == "ptx" || Feature == "nvptx";
1399     }
1400 
1401     void getGCCRegNames(const char * const *&Names,
1402                         unsigned &NumNames) const override;
1403     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1404                                   unsigned &NumAliases) const override {
1405       // No aliases.
1406       Aliases = nullptr;
1407       NumAliases = 0;
1408     }
1409     bool validateAsmConstraint(const char *&Name,
1410                                TargetInfo::ConstraintInfo &Info) const override {
1411       switch (*Name) {
1412       default: return false;
1413       case 'c':
1414       case 'h':
1415       case 'r':
1416       case 'l':
1417       case 'f':
1418       case 'd':
1419         Info.setAllowsRegister();
1420         return true;
1421       }
1422     }
1423     const char *getClobbers() const override {
1424       // FIXME: Is this really right?
1425       return "";
1426     }
1427     BuiltinVaListKind getBuiltinVaListKind() const override {
1428       // FIXME: implement
1429       return TargetInfo::CharPtrBuiltinVaList;
1430     }
1431     bool setCPU(const std::string &Name) override {
1432       bool Valid = llvm::StringSwitch<bool>(Name)
1433         .Case("sm_20", true)
1434         .Case("sm_21", true)
1435         .Case("sm_30", true)
1436         .Case("sm_35", true)
1437         .Default(false);
1438 
1439       return Valid;
1440     }
1441   };
1442 
1443   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1444 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1445 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1446                                               ALL_LANGUAGES },
1447 #include "clang/Basic/BuiltinsNVPTX.def"
1448   };
1449 
1450   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1451     "r0"
1452   };
1453 
1454   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1455                                      unsigned &NumNames) const {
1456     Names = GCCRegNames;
1457     NumNames = llvm::array_lengthof(GCCRegNames);
1458   }
1459 
1460   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1461   public:
1462     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1463       PointerWidth = PointerAlign = 32;
1464       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1465       IntPtrType = TargetInfo::SignedInt;
1466       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1467   }
1468   };
1469 
1470   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1471   public:
1472     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1473       PointerWidth = PointerAlign = 64;
1474       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1475       IntPtrType = TargetInfo::SignedLongLong;
1476       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1477   }
1478   };
1479 }
1480 
1481 namespace {
1482 
1483 static const unsigned R600AddrSpaceMap[] = {
1484   1,    // opencl_global
1485   3,    // opencl_local
1486   2,    // opencl_constant
1487   1,    // cuda_device
1488   2,    // cuda_constant
1489   3     // cuda_shared
1490 };
1491 
1492 // If you edit the description strings, make sure you update
1493 // getPointerWidthV().
1494 
1495 static const char *DescriptionStringR600 =
1496   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1497   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1498 
1499 static const char *DescriptionStringR600DoubleOps =
1500   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1501   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1502 
1503 static const char *DescriptionStringSI =
1504   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1505   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1506   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1507 
1508 class R600TargetInfo : public TargetInfo {
1509   static const Builtin::Info BuiltinInfo[];
1510 
1511   /// \brief The GPU profiles supported by the R600 target.
1512   enum GPUKind {
1513     GK_NONE,
1514     GK_R600,
1515     GK_R600_DOUBLE_OPS,
1516     GK_R700,
1517     GK_R700_DOUBLE_OPS,
1518     GK_EVERGREEN,
1519     GK_EVERGREEN_DOUBLE_OPS,
1520     GK_NORTHERN_ISLANDS,
1521     GK_CAYMAN,
1522     GK_SOUTHERN_ISLANDS,
1523     GK_SEA_ISLANDS
1524   } GPU;
1525 
1526 public:
1527   R600TargetInfo(const llvm::Triple &Triple)
1528       : TargetInfo(Triple), GPU(GK_R600) {
1529     DescriptionString = DescriptionStringR600;
1530     AddrSpaceMap = &R600AddrSpaceMap;
1531     UseAddrSpaceMapMangling = true;
1532   }
1533 
1534   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1535     if (GPU <= GK_CAYMAN)
1536       return 32;
1537 
1538     switch(AddrSpace) {
1539       default:
1540         return 64;
1541       case 0:
1542       case 3:
1543       case 5:
1544         return 32;
1545     }
1546   }
1547 
1548   const char * getClobbers() const override {
1549     return "";
1550   }
1551 
1552   void getGCCRegNames(const char * const *&Names,
1553                       unsigned &numNames) const override {
1554     Names = nullptr;
1555     numNames = 0;
1556   }
1557 
1558   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1559                         unsigned &NumAliases) const override {
1560     Aliases = nullptr;
1561     NumAliases = 0;
1562   }
1563 
1564   bool validateAsmConstraint(const char *&Name,
1565                              TargetInfo::ConstraintInfo &info) const override {
1566     return true;
1567   }
1568 
1569   void getTargetBuiltins(const Builtin::Info *&Records,
1570                          unsigned &NumRecords) const override {
1571     Records = BuiltinInfo;
1572     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1573   }
1574 
1575   void getTargetDefines(const LangOptions &Opts,
1576                         MacroBuilder &Builder) const override {
1577     Builder.defineMacro("__R600__");
1578   }
1579 
1580   BuiltinVaListKind getBuiltinVaListKind() const override {
1581     return TargetInfo::CharPtrBuiltinVaList;
1582   }
1583 
1584   bool setCPU(const std::string &Name) override {
1585     GPU = llvm::StringSwitch<GPUKind>(Name)
1586       .Case("r600" ,    GK_R600)
1587       .Case("rv610",    GK_R600)
1588       .Case("rv620",    GK_R600)
1589       .Case("rv630",    GK_R600)
1590       .Case("rv635",    GK_R600)
1591       .Case("rs780",    GK_R600)
1592       .Case("rs880",    GK_R600)
1593       .Case("rv670",    GK_R600_DOUBLE_OPS)
1594       .Case("rv710",    GK_R700)
1595       .Case("rv730",    GK_R700)
1596       .Case("rv740",    GK_R700_DOUBLE_OPS)
1597       .Case("rv770",    GK_R700_DOUBLE_OPS)
1598       .Case("palm",     GK_EVERGREEN)
1599       .Case("cedar",    GK_EVERGREEN)
1600       .Case("sumo",     GK_EVERGREEN)
1601       .Case("sumo2",    GK_EVERGREEN)
1602       .Case("redwood",  GK_EVERGREEN)
1603       .Case("juniper",  GK_EVERGREEN)
1604       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1605       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1606       .Case("barts",    GK_NORTHERN_ISLANDS)
1607       .Case("turks",    GK_NORTHERN_ISLANDS)
1608       .Case("caicos",   GK_NORTHERN_ISLANDS)
1609       .Case("cayman",   GK_CAYMAN)
1610       .Case("aruba",    GK_CAYMAN)
1611       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1612       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1613       .Case("verde",    GK_SOUTHERN_ISLANDS)
1614       .Case("oland",    GK_SOUTHERN_ISLANDS)
1615       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1616       .Case("bonaire",  GK_SEA_ISLANDS)
1617       .Case("kabini",   GK_SEA_ISLANDS)
1618       .Case("kaveri",   GK_SEA_ISLANDS)
1619       .Case("hawaii",   GK_SEA_ISLANDS)
1620       .Case("mullins",  GK_SEA_ISLANDS)
1621       .Default(GK_NONE);
1622 
1623     if (GPU == GK_NONE) {
1624       return false;
1625     }
1626 
1627     // Set the correct data layout
1628     switch (GPU) {
1629     case GK_NONE:
1630     case GK_R600:
1631     case GK_R700:
1632     case GK_EVERGREEN:
1633     case GK_NORTHERN_ISLANDS:
1634       DescriptionString = DescriptionStringR600;
1635       break;
1636     case GK_R600_DOUBLE_OPS:
1637     case GK_R700_DOUBLE_OPS:
1638     case GK_EVERGREEN_DOUBLE_OPS:
1639     case GK_CAYMAN:
1640       DescriptionString = DescriptionStringR600DoubleOps;
1641       break;
1642     case GK_SOUTHERN_ISLANDS:
1643     case GK_SEA_ISLANDS:
1644       DescriptionString = DescriptionStringSI;
1645       break;
1646     }
1647 
1648     return true;
1649   }
1650 };
1651 
1652 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1653 #define BUILTIN(ID, TYPE, ATTRS)                \
1654   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1655 #include "clang/Basic/BuiltinsR600.def"
1656 };
1657 
1658 } // end anonymous namespace
1659 
1660 namespace {
1661 // Namespace for x86 abstract base class
1662 const Builtin::Info BuiltinInfo[] = {
1663 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1664 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1665                                               ALL_LANGUAGES },
1666 #include "clang/Basic/BuiltinsX86.def"
1667 };
1668 
1669 static const char* const GCCRegNames[] = {
1670   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1671   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1672   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1673   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1674   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1675   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1676   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1677   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1678   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1679 };
1680 
1681 const TargetInfo::AddlRegName AddlRegNames[] = {
1682   { { "al", "ah", "eax", "rax" }, 0 },
1683   { { "bl", "bh", "ebx", "rbx" }, 3 },
1684   { { "cl", "ch", "ecx", "rcx" }, 2 },
1685   { { "dl", "dh", "edx", "rdx" }, 1 },
1686   { { "esi", "rsi" }, 4 },
1687   { { "edi", "rdi" }, 5 },
1688   { { "esp", "rsp" }, 7 },
1689   { { "ebp", "rbp" }, 6 },
1690 };
1691 
1692 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1693 // most of the implementation can be shared.
1694 class X86TargetInfo : public TargetInfo {
1695   enum X86SSEEnum {
1696     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1697   } SSELevel;
1698   enum MMX3DNowEnum {
1699     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1700   } MMX3DNowLevel;
1701   enum XOPEnum {
1702     NoXOP,
1703     SSE4A,
1704     FMA4,
1705     XOP
1706   } XOPLevel;
1707 
1708   bool HasAES;
1709   bool HasPCLMUL;
1710   bool HasLZCNT;
1711   bool HasRDRND;
1712   bool HasFSGSBASE;
1713   bool HasBMI;
1714   bool HasBMI2;
1715   bool HasPOPCNT;
1716   bool HasRTM;
1717   bool HasPRFCHW;
1718   bool HasRDSEED;
1719   bool HasADX;
1720   bool HasTBM;
1721   bool HasFMA;
1722   bool HasF16C;
1723   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL;
1724   bool HasSHA;
1725   bool HasCX16;
1726 
1727   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1728   ///
1729   /// Each enumeration represents a particular CPU supported by Clang. These
1730   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1731   enum CPUKind {
1732     CK_Generic,
1733 
1734     /// \name i386
1735     /// i386-generation processors.
1736     //@{
1737     CK_i386,
1738     //@}
1739 
1740     /// \name i486
1741     /// i486-generation processors.
1742     //@{
1743     CK_i486,
1744     CK_WinChipC6,
1745     CK_WinChip2,
1746     CK_C3,
1747     //@}
1748 
1749     /// \name i586
1750     /// i586-generation processors, P5 microarchitecture based.
1751     //@{
1752     CK_i586,
1753     CK_Pentium,
1754     CK_PentiumMMX,
1755     //@}
1756 
1757     /// \name i686
1758     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1759     //@{
1760     CK_i686,
1761     CK_PentiumPro,
1762     CK_Pentium2,
1763     CK_Pentium3,
1764     CK_Pentium3M,
1765     CK_PentiumM,
1766     CK_C3_2,
1767 
1768     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1769     /// Clang however has some logic to suport this.
1770     // FIXME: Warn, deprecate, and potentially remove this.
1771     CK_Yonah,
1772     //@}
1773 
1774     /// \name Netburst
1775     /// Netburst microarchitecture based processors.
1776     //@{
1777     CK_Pentium4,
1778     CK_Pentium4M,
1779     CK_Prescott,
1780     CK_Nocona,
1781     //@}
1782 
1783     /// \name Core
1784     /// Core microarchitecture based processors.
1785     //@{
1786     CK_Core2,
1787 
1788     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1789     /// codename which GCC no longer accepts as an option to -march, but Clang
1790     /// has some logic for recognizing it.
1791     // FIXME: Warn, deprecate, and potentially remove this.
1792     CK_Penryn,
1793     //@}
1794 
1795     /// \name Atom
1796     /// Atom processors
1797     //@{
1798     CK_Atom,
1799     CK_Silvermont,
1800     //@}
1801 
1802     /// \name Nehalem
1803     /// Nehalem microarchitecture based processors.
1804     //@{
1805     CK_Corei7,
1806     CK_Corei7AVX,
1807     CK_CoreAVXi,
1808     CK_CoreAVX2,
1809     CK_Broadwell,
1810     //@}
1811 
1812     /// \name Knights Landing
1813     /// Knights Landing processor.
1814     CK_KNL,
1815 
1816     /// \name Skylake Server
1817     /// Skylake server processor.
1818     CK_SKX,
1819 
1820     /// \name K6
1821     /// K6 architecture processors.
1822     //@{
1823     CK_K6,
1824     CK_K6_2,
1825     CK_K6_3,
1826     //@}
1827 
1828     /// \name K7
1829     /// K7 architecture processors.
1830     //@{
1831     CK_Athlon,
1832     CK_AthlonThunderbird,
1833     CK_Athlon4,
1834     CK_AthlonXP,
1835     CK_AthlonMP,
1836     //@}
1837 
1838     /// \name K8
1839     /// K8 architecture processors.
1840     //@{
1841     CK_Athlon64,
1842     CK_Athlon64SSE3,
1843     CK_AthlonFX,
1844     CK_K8,
1845     CK_K8SSE3,
1846     CK_Opteron,
1847     CK_OpteronSSE3,
1848     CK_AMDFAM10,
1849     //@}
1850 
1851     /// \name Bobcat
1852     /// Bobcat architecture processors.
1853     //@{
1854     CK_BTVER1,
1855     CK_BTVER2,
1856     //@}
1857 
1858     /// \name Bulldozer
1859     /// Bulldozer architecture processors.
1860     //@{
1861     CK_BDVER1,
1862     CK_BDVER2,
1863     CK_BDVER3,
1864     CK_BDVER4,
1865     //@}
1866 
1867     /// This specification is deprecated and will be removed in the future.
1868     /// Users should prefer \see CK_K8.
1869     // FIXME: Warn on this when the CPU is set to it.
1870     CK_x86_64,
1871     //@}
1872 
1873     /// \name Geode
1874     /// Geode processors.
1875     //@{
1876     CK_Geode
1877     //@}
1878   } CPU;
1879 
1880   enum FPMathKind {
1881     FP_Default,
1882     FP_SSE,
1883     FP_387
1884   } FPMath;
1885 
1886 public:
1887   X86TargetInfo(const llvm::Triple &Triple)
1888       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1889         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1890         HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false),
1891         HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false),
1892         HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false),
1893         HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false),
1894         HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false),
1895         HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) {
1896     BigEndian = false;
1897     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1898   }
1899   unsigned getFloatEvalMethod() const override {
1900     // X87 evaluates with 80 bits "long double" precision.
1901     return SSELevel == NoSSE ? 2 : 0;
1902   }
1903   void getTargetBuiltins(const Builtin::Info *&Records,
1904                                  unsigned &NumRecords) const override {
1905     Records = BuiltinInfo;
1906     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1907   }
1908   void getGCCRegNames(const char * const *&Names,
1909                       unsigned &NumNames) const override {
1910     Names = GCCRegNames;
1911     NumNames = llvm::array_lengthof(GCCRegNames);
1912   }
1913   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1914                         unsigned &NumAliases) const override {
1915     Aliases = nullptr;
1916     NumAliases = 0;
1917   }
1918   void getGCCAddlRegNames(const AddlRegName *&Names,
1919                           unsigned &NumNames) const override {
1920     Names = AddlRegNames;
1921     NumNames = llvm::array_lengthof(AddlRegNames);
1922   }
1923   bool validateAsmConstraint(const char *&Name,
1924                                      TargetInfo::ConstraintInfo &info) const override;
1925 
1926   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1927 
1928   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1929 
1930   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1931 
1932   std::string convertConstraint(const char *&Constraint) const override;
1933   const char *getClobbers() const override {
1934     return "~{dirflag},~{fpsr},~{flags}";
1935   }
1936   void getTargetDefines(const LangOptions &Opts,
1937                         MacroBuilder &Builder) const override;
1938   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1939                           bool Enabled);
1940   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1941                           bool Enabled);
1942   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1943                           bool Enabled);
1944   void setFeatureEnabled(llvm::StringMap<bool> &Features,
1945                          StringRef Name, bool Enabled) const override {
1946     setFeatureEnabledImpl(Features, Name, Enabled);
1947   }
1948   // This exists purely to cut down on the number of virtual calls in
1949   // getDefaultFeatures which calls this repeatedly.
1950   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1951                                     StringRef Name, bool Enabled);
1952   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
1953   bool hasFeature(StringRef Feature) const override;
1954   bool handleTargetFeatures(std::vector<std::string> &Features,
1955                             DiagnosticsEngine &Diags) override;
1956   StringRef getABI() const override {
1957     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1958       return "avx";
1959     else if (getTriple().getArch() == llvm::Triple::x86 &&
1960              MMX3DNowLevel == NoMMX3DNow)
1961       return "no-mmx";
1962     return "";
1963   }
1964   bool setCPU(const std::string &Name) override {
1965     CPU = llvm::StringSwitch<CPUKind>(Name)
1966       .Case("i386", CK_i386)
1967       .Case("i486", CK_i486)
1968       .Case("winchip-c6", CK_WinChipC6)
1969       .Case("winchip2", CK_WinChip2)
1970       .Case("c3", CK_C3)
1971       .Case("i586", CK_i586)
1972       .Case("pentium", CK_Pentium)
1973       .Case("pentium-mmx", CK_PentiumMMX)
1974       .Case("i686", CK_i686)
1975       .Case("pentiumpro", CK_PentiumPro)
1976       .Case("pentium2", CK_Pentium2)
1977       .Case("pentium3", CK_Pentium3)
1978       .Case("pentium3m", CK_Pentium3M)
1979       .Case("pentium-m", CK_PentiumM)
1980       .Case("c3-2", CK_C3_2)
1981       .Case("yonah", CK_Yonah)
1982       .Case("pentium4", CK_Pentium4)
1983       .Case("pentium4m", CK_Pentium4M)
1984       .Case("prescott", CK_Prescott)
1985       .Case("nocona", CK_Nocona)
1986       .Case("core2", CK_Core2)
1987       .Case("penryn", CK_Penryn)
1988       .Case("atom", CK_Atom)
1989       .Case("slm", CK_Silvermont)
1990       .Case("corei7", CK_Corei7)
1991       .Case("corei7-avx", CK_Corei7AVX)
1992       .Case("core-avx-i", CK_CoreAVXi)
1993       .Case("core-avx2", CK_CoreAVX2)
1994       .Case("broadwell", CK_Broadwell)
1995       .Case("knl", CK_KNL)
1996       .Case("skx", CK_SKX)
1997       .Case("k6", CK_K6)
1998       .Case("k6-2", CK_K6_2)
1999       .Case("k6-3", CK_K6_3)
2000       .Case("athlon", CK_Athlon)
2001       .Case("athlon-tbird", CK_AthlonThunderbird)
2002       .Case("athlon-4", CK_Athlon4)
2003       .Case("athlon-xp", CK_AthlonXP)
2004       .Case("athlon-mp", CK_AthlonMP)
2005       .Case("athlon64", CK_Athlon64)
2006       .Case("athlon64-sse3", CK_Athlon64SSE3)
2007       .Case("athlon-fx", CK_AthlonFX)
2008       .Case("k8", CK_K8)
2009       .Case("k8-sse3", CK_K8SSE3)
2010       .Case("opteron", CK_Opteron)
2011       .Case("opteron-sse3", CK_OpteronSSE3)
2012       .Case("amdfam10", CK_AMDFAM10)
2013       .Case("btver1", CK_BTVER1)
2014       .Case("btver2", CK_BTVER2)
2015       .Case("bdver1", CK_BDVER1)
2016       .Case("bdver2", CK_BDVER2)
2017       .Case("bdver3", CK_BDVER3)
2018       .Case("bdver4", CK_BDVER4)
2019       .Case("x86-64", CK_x86_64)
2020       .Case("geode", CK_Geode)
2021       .Default(CK_Generic);
2022 
2023     // Perform any per-CPU checks necessary to determine if this CPU is
2024     // acceptable.
2025     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2026     // invalid without explaining *why*.
2027     switch (CPU) {
2028     case CK_Generic:
2029       // No processor selected!
2030       return false;
2031 
2032     case CK_i386:
2033     case CK_i486:
2034     case CK_WinChipC6:
2035     case CK_WinChip2:
2036     case CK_C3:
2037     case CK_i586:
2038     case CK_Pentium:
2039     case CK_PentiumMMX:
2040     case CK_i686:
2041     case CK_PentiumPro:
2042     case CK_Pentium2:
2043     case CK_Pentium3:
2044     case CK_Pentium3M:
2045     case CK_PentiumM:
2046     case CK_Yonah:
2047     case CK_C3_2:
2048     case CK_Pentium4:
2049     case CK_Pentium4M:
2050     case CK_Prescott:
2051     case CK_K6:
2052     case CK_K6_2:
2053     case CK_K6_3:
2054     case CK_Athlon:
2055     case CK_AthlonThunderbird:
2056     case CK_Athlon4:
2057     case CK_AthlonXP:
2058     case CK_AthlonMP:
2059     case CK_Geode:
2060       // Only accept certain architectures when compiling in 32-bit mode.
2061       if (getTriple().getArch() != llvm::Triple::x86)
2062         return false;
2063 
2064       // Fallthrough
2065     case CK_Nocona:
2066     case CK_Core2:
2067     case CK_Penryn:
2068     case CK_Atom:
2069     case CK_Silvermont:
2070     case CK_Corei7:
2071     case CK_Corei7AVX:
2072     case CK_CoreAVXi:
2073     case CK_CoreAVX2:
2074     case CK_Broadwell:
2075     case CK_KNL:
2076     case CK_SKX:
2077     case CK_Athlon64:
2078     case CK_Athlon64SSE3:
2079     case CK_AthlonFX:
2080     case CK_K8:
2081     case CK_K8SSE3:
2082     case CK_Opteron:
2083     case CK_OpteronSSE3:
2084     case CK_AMDFAM10:
2085     case CK_BTVER1:
2086     case CK_BTVER2:
2087     case CK_BDVER1:
2088     case CK_BDVER2:
2089     case CK_BDVER3:
2090     case CK_BDVER4:
2091     case CK_x86_64:
2092       return true;
2093     }
2094     llvm_unreachable("Unhandled CPU kind");
2095   }
2096 
2097   bool setFPMath(StringRef Name) override;
2098 
2099   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2100     // We accept all non-ARM calling conventions
2101     return (CC == CC_X86ThisCall ||
2102             CC == CC_X86FastCall ||
2103             CC == CC_X86StdCall ||
2104             CC == CC_X86VectorCall ||
2105             CC == CC_C ||
2106             CC == CC_X86Pascal ||
2107             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2108   }
2109 
2110   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2111     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2112   }
2113 };
2114 
2115 bool X86TargetInfo::setFPMath(StringRef Name) {
2116   if (Name == "387") {
2117     FPMath = FP_387;
2118     return true;
2119   }
2120   if (Name == "sse") {
2121     FPMath = FP_SSE;
2122     return true;
2123   }
2124   return false;
2125 }
2126 
2127 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2128   // FIXME: This *really* should not be here.
2129 
2130   // X86_64 always has SSE2.
2131   if (getTriple().getArch() == llvm::Triple::x86_64)
2132     setFeatureEnabledImpl(Features, "sse2", true);
2133 
2134   switch (CPU) {
2135   case CK_Generic:
2136   case CK_i386:
2137   case CK_i486:
2138   case CK_i586:
2139   case CK_Pentium:
2140   case CK_i686:
2141   case CK_PentiumPro:
2142     break;
2143   case CK_PentiumMMX:
2144   case CK_Pentium2:
2145     setFeatureEnabledImpl(Features, "mmx", true);
2146     break;
2147   case CK_Pentium3:
2148   case CK_Pentium3M:
2149     setFeatureEnabledImpl(Features, "sse", true);
2150     break;
2151   case CK_PentiumM:
2152   case CK_Pentium4:
2153   case CK_Pentium4M:
2154   case CK_x86_64:
2155     setFeatureEnabledImpl(Features, "sse2", true);
2156     break;
2157   case CK_Yonah:
2158   case CK_Prescott:
2159   case CK_Nocona:
2160     setFeatureEnabledImpl(Features, "sse3", true);
2161     setFeatureEnabledImpl(Features, "cx16", true);
2162     break;
2163   case CK_Core2:
2164     setFeatureEnabledImpl(Features, "ssse3", true);
2165     setFeatureEnabledImpl(Features, "cx16", true);
2166     break;
2167   case CK_Penryn:
2168     setFeatureEnabledImpl(Features, "sse4.1", true);
2169     setFeatureEnabledImpl(Features, "cx16", true);
2170     break;
2171   case CK_Atom:
2172     setFeatureEnabledImpl(Features, "ssse3", true);
2173     setFeatureEnabledImpl(Features, "cx16", true);
2174     break;
2175   case CK_Silvermont:
2176     setFeatureEnabledImpl(Features, "sse4.2", true);
2177     setFeatureEnabledImpl(Features, "aes", true);
2178     setFeatureEnabledImpl(Features, "cx16", true);
2179     setFeatureEnabledImpl(Features, "pclmul", true);
2180     break;
2181   case CK_Corei7:
2182     setFeatureEnabledImpl(Features, "sse4.2", true);
2183     setFeatureEnabledImpl(Features, "cx16", true);
2184     break;
2185   case CK_Corei7AVX:
2186     setFeatureEnabledImpl(Features, "avx", true);
2187     setFeatureEnabledImpl(Features, "aes", true);
2188     setFeatureEnabledImpl(Features, "cx16", true);
2189     setFeatureEnabledImpl(Features, "pclmul", true);
2190     break;
2191   case CK_CoreAVXi:
2192     setFeatureEnabledImpl(Features, "avx", true);
2193     setFeatureEnabledImpl(Features, "aes", true);
2194     setFeatureEnabledImpl(Features, "cx16", true);
2195     setFeatureEnabledImpl(Features, "pclmul", true);
2196     setFeatureEnabledImpl(Features, "rdrnd", true);
2197     setFeatureEnabledImpl(Features, "f16c", true);
2198     setFeatureEnabledImpl(Features, "fsgsbase", true);
2199     break;
2200   case CK_CoreAVX2:
2201     setFeatureEnabledImpl(Features, "avx2", true);
2202     setFeatureEnabledImpl(Features, "aes", true);
2203     setFeatureEnabledImpl(Features, "cx16", true);
2204     setFeatureEnabledImpl(Features, "pclmul", true);
2205     setFeatureEnabledImpl(Features, "lzcnt", true);
2206     setFeatureEnabledImpl(Features, "rdrnd", true);
2207     setFeatureEnabledImpl(Features, "f16c", true);
2208     setFeatureEnabledImpl(Features, "fsgsbase", true);
2209     setFeatureEnabledImpl(Features, "bmi", true);
2210     setFeatureEnabledImpl(Features, "bmi2", true);
2211     setFeatureEnabledImpl(Features, "rtm", true);
2212     setFeatureEnabledImpl(Features, "fma", true);
2213     break;
2214   case CK_Broadwell:
2215     setFeatureEnabledImpl(Features, "avx2", true);
2216     setFeatureEnabledImpl(Features, "aes", true);
2217     setFeatureEnabledImpl(Features, "cx16", true);
2218     setFeatureEnabledImpl(Features, "pclmul", true);
2219     setFeatureEnabledImpl(Features, "lzcnt", true);
2220     setFeatureEnabledImpl(Features, "rdrnd", true);
2221     setFeatureEnabledImpl(Features, "f16c", true);
2222     setFeatureEnabledImpl(Features, "fsgsbase", true);
2223     setFeatureEnabledImpl(Features, "bmi", true);
2224     setFeatureEnabledImpl(Features, "bmi2", true);
2225     setFeatureEnabledImpl(Features, "rtm", true);
2226     setFeatureEnabledImpl(Features, "fma", true);
2227     setFeatureEnabledImpl(Features, "rdseed", true);
2228     setFeatureEnabledImpl(Features, "adx", true);
2229     break;
2230   case CK_KNL:
2231     setFeatureEnabledImpl(Features, "avx512f", true);
2232     setFeatureEnabledImpl(Features, "avx512cd", true);
2233     setFeatureEnabledImpl(Features, "avx512er", true);
2234     setFeatureEnabledImpl(Features, "avx512pf", true);
2235     setFeatureEnabledImpl(Features, "aes", true);
2236     setFeatureEnabledImpl(Features, "cx16", true);
2237     setFeatureEnabledImpl(Features, "pclmul", true);
2238     setFeatureEnabledImpl(Features, "lzcnt", true);
2239     setFeatureEnabledImpl(Features, "rdrnd", true);
2240     setFeatureEnabledImpl(Features, "f16c", true);
2241     setFeatureEnabledImpl(Features, "fsgsbase", true);
2242     setFeatureEnabledImpl(Features, "bmi", true);
2243     setFeatureEnabledImpl(Features, "bmi2", true);
2244     setFeatureEnabledImpl(Features, "rtm", true);
2245     setFeatureEnabledImpl(Features, "fma", true);
2246     setFeatureEnabledImpl(Features, "rdseed", true);
2247     setFeatureEnabledImpl(Features, "adx", true);
2248     break;
2249   case CK_SKX:
2250     setFeatureEnabledImpl(Features, "avx512f", true);
2251     setFeatureEnabledImpl(Features, "avx512cd", true);
2252     setFeatureEnabledImpl(Features, "avx512dq", true);
2253     setFeatureEnabledImpl(Features, "avx512bw", true);
2254     setFeatureEnabledImpl(Features, "avx512vl", true);
2255     setFeatureEnabledImpl(Features, "aes", true);
2256     setFeatureEnabledImpl(Features, "cx16", true);
2257     setFeatureEnabledImpl(Features, "pclmul", true);
2258     setFeatureEnabledImpl(Features, "lzcnt", true);
2259     setFeatureEnabledImpl(Features, "rdrnd", true);
2260     setFeatureEnabledImpl(Features, "f16c", true);
2261     setFeatureEnabledImpl(Features, "fsgsbase", true);
2262     setFeatureEnabledImpl(Features, "bmi", true);
2263     setFeatureEnabledImpl(Features, "bmi2", true);
2264     setFeatureEnabledImpl(Features, "rtm", true);
2265     setFeatureEnabledImpl(Features, "fma", true);
2266     setFeatureEnabledImpl(Features, "rdseed", true);
2267     setFeatureEnabledImpl(Features, "adx", true);
2268     break;
2269   case CK_K6:
2270   case CK_WinChipC6:
2271     setFeatureEnabledImpl(Features, "mmx", true);
2272     break;
2273   case CK_K6_2:
2274   case CK_K6_3:
2275   case CK_WinChip2:
2276   case CK_C3:
2277     setFeatureEnabledImpl(Features, "3dnow", true);
2278     break;
2279   case CK_Athlon:
2280   case CK_AthlonThunderbird:
2281   case CK_Geode:
2282     setFeatureEnabledImpl(Features, "3dnowa", true);
2283     break;
2284   case CK_Athlon4:
2285   case CK_AthlonXP:
2286   case CK_AthlonMP:
2287     setFeatureEnabledImpl(Features, "sse", true);
2288     setFeatureEnabledImpl(Features, "3dnowa", true);
2289     break;
2290   case CK_K8:
2291   case CK_Opteron:
2292   case CK_Athlon64:
2293   case CK_AthlonFX:
2294     setFeatureEnabledImpl(Features, "sse2", true);
2295     setFeatureEnabledImpl(Features, "3dnowa", true);
2296     break;
2297   case CK_K8SSE3:
2298   case CK_OpteronSSE3:
2299   case CK_Athlon64SSE3:
2300     setFeatureEnabledImpl(Features, "sse3", true);
2301     setFeatureEnabledImpl(Features, "3dnowa", true);
2302     break;
2303   case CK_AMDFAM10:
2304     setFeatureEnabledImpl(Features, "sse3", true);
2305     setFeatureEnabledImpl(Features, "sse4a", true);
2306     setFeatureEnabledImpl(Features, "3dnowa", true);
2307     setFeatureEnabledImpl(Features, "lzcnt", true);
2308     setFeatureEnabledImpl(Features, "popcnt", true);
2309     break;
2310   case CK_BTVER1:
2311     setFeatureEnabledImpl(Features, "ssse3", true);
2312     setFeatureEnabledImpl(Features, "sse4a", true);
2313     setFeatureEnabledImpl(Features, "cx16", true);
2314     setFeatureEnabledImpl(Features, "lzcnt", true);
2315     setFeatureEnabledImpl(Features, "popcnt", true);
2316     setFeatureEnabledImpl(Features, "prfchw", true);
2317     break;
2318   case CK_BTVER2:
2319     setFeatureEnabledImpl(Features, "avx", true);
2320     setFeatureEnabledImpl(Features, "sse4a", true);
2321     setFeatureEnabledImpl(Features, "lzcnt", true);
2322     setFeatureEnabledImpl(Features, "aes", true);
2323     setFeatureEnabledImpl(Features, "pclmul", true);
2324     setFeatureEnabledImpl(Features, "prfchw", true);
2325     setFeatureEnabledImpl(Features, "bmi", true);
2326     setFeatureEnabledImpl(Features, "f16c", true);
2327     setFeatureEnabledImpl(Features, "cx16", true);
2328     break;
2329   case CK_BDVER1:
2330     setFeatureEnabledImpl(Features, "xop", true);
2331     setFeatureEnabledImpl(Features, "lzcnt", true);
2332     setFeatureEnabledImpl(Features, "aes", true);
2333     setFeatureEnabledImpl(Features, "pclmul", true);
2334     setFeatureEnabledImpl(Features, "prfchw", true);
2335     setFeatureEnabledImpl(Features, "cx16", true);
2336     break;
2337   case CK_BDVER4:
2338     setFeatureEnabledImpl(Features, "avx2", true);
2339     setFeatureEnabledImpl(Features, "bmi2", true);
2340     // FALLTHROUGH
2341   case CK_BDVER3:
2342     setFeatureEnabledImpl(Features, "fsgsbase", true);
2343     // FALLTHROUGH
2344   case CK_BDVER2:
2345     setFeatureEnabledImpl(Features, "xop", true);
2346     setFeatureEnabledImpl(Features, "lzcnt", true);
2347     setFeatureEnabledImpl(Features, "aes", true);
2348     setFeatureEnabledImpl(Features, "pclmul", true);
2349     setFeatureEnabledImpl(Features, "prfchw", true);
2350     setFeatureEnabledImpl(Features, "bmi", true);
2351     setFeatureEnabledImpl(Features, "fma", true);
2352     setFeatureEnabledImpl(Features, "f16c", true);
2353     setFeatureEnabledImpl(Features, "tbm", true);
2354     setFeatureEnabledImpl(Features, "cx16", true);
2355     break;
2356   case CK_C3_2:
2357     setFeatureEnabledImpl(Features, "sse", true);
2358     break;
2359   }
2360 }
2361 
2362 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2363                                 X86SSEEnum Level, bool Enabled) {
2364   if (Enabled) {
2365     switch (Level) {
2366     case AVX512F:
2367       Features["avx512f"] = true;
2368     case AVX2:
2369       Features["avx2"] = true;
2370     case AVX:
2371       Features["avx"] = true;
2372     case SSE42:
2373       Features["sse4.2"] = true;
2374     case SSE41:
2375       Features["sse4.1"] = true;
2376     case SSSE3:
2377       Features["ssse3"] = true;
2378     case SSE3:
2379       Features["sse3"] = true;
2380     case SSE2:
2381       Features["sse2"] = true;
2382     case SSE1:
2383       Features["sse"] = true;
2384     case NoSSE:
2385       break;
2386     }
2387     return;
2388   }
2389 
2390   switch (Level) {
2391   case NoSSE:
2392   case SSE1:
2393     Features["sse"] = false;
2394   case SSE2:
2395     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2396       Features["sha"] = false;
2397   case SSE3:
2398     Features["sse3"] = false;
2399     setXOPLevel(Features, NoXOP, false);
2400   case SSSE3:
2401     Features["ssse3"] = false;
2402   case SSE41:
2403     Features["sse4.1"] = false;
2404   case SSE42:
2405     Features["sse4.2"] = false;
2406   case AVX:
2407     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2408     setXOPLevel(Features, FMA4, false);
2409   case AVX2:
2410     Features["avx2"] = false;
2411   case AVX512F:
2412     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] =
2413     Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false;
2414   }
2415 }
2416 
2417 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2418                                 MMX3DNowEnum Level, bool Enabled) {
2419   if (Enabled) {
2420     switch (Level) {
2421     case AMD3DNowAthlon:
2422       Features["3dnowa"] = true;
2423     case AMD3DNow:
2424       Features["3dnow"] = true;
2425     case MMX:
2426       Features["mmx"] = true;
2427     case NoMMX3DNow:
2428       break;
2429     }
2430     return;
2431   }
2432 
2433   switch (Level) {
2434   case NoMMX3DNow:
2435   case MMX:
2436     Features["mmx"] = false;
2437   case AMD3DNow:
2438     Features["3dnow"] = false;
2439   case AMD3DNowAthlon:
2440     Features["3dnowa"] = false;
2441   }
2442 }
2443 
2444 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2445                                 bool Enabled) {
2446   if (Enabled) {
2447     switch (Level) {
2448     case XOP:
2449       Features["xop"] = true;
2450     case FMA4:
2451       Features["fma4"] = true;
2452       setSSELevel(Features, AVX, true);
2453     case SSE4A:
2454       Features["sse4a"] = true;
2455       setSSELevel(Features, SSE3, true);
2456     case NoXOP:
2457       break;
2458     }
2459     return;
2460   }
2461 
2462   switch (Level) {
2463   case NoXOP:
2464   case SSE4A:
2465     Features["sse4a"] = false;
2466   case FMA4:
2467     Features["fma4"] = false;
2468   case XOP:
2469     Features["xop"] = false;
2470   }
2471 }
2472 
2473 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2474                                           StringRef Name, bool Enabled) {
2475   // FIXME: This *really* should not be here.  We need some way of translating
2476   // options into llvm subtarget features.
2477   if (Name == "sse4")
2478     Name = "sse4.2";
2479 
2480   Features[Name] = Enabled;
2481 
2482   if (Name == "mmx") {
2483     setMMXLevel(Features, MMX, Enabled);
2484   } else if (Name == "sse") {
2485     setSSELevel(Features, SSE1, Enabled);
2486   } else if (Name == "sse2") {
2487     setSSELevel(Features, SSE2, Enabled);
2488   } else if (Name == "sse3") {
2489     setSSELevel(Features, SSE3, Enabled);
2490   } else if (Name == "ssse3") {
2491     setSSELevel(Features, SSSE3, Enabled);
2492   } else if (Name == "sse4.2") {
2493     setSSELevel(Features, SSE42, Enabled);
2494   } else if (Name == "sse4.1") {
2495     setSSELevel(Features, SSE41, Enabled);
2496   } else if (Name == "3dnow") {
2497     setMMXLevel(Features, AMD3DNow, Enabled);
2498   } else if (Name == "3dnowa") {
2499     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2500   } else if (Name == "aes") {
2501     if (Enabled)
2502       setSSELevel(Features, SSE2, Enabled);
2503   } else if (Name == "pclmul") {
2504     if (Enabled)
2505       setSSELevel(Features, SSE2, Enabled);
2506   } else if (Name == "avx") {
2507     setSSELevel(Features, AVX, Enabled);
2508   } else if (Name == "avx2") {
2509     setSSELevel(Features, AVX2, Enabled);
2510   } else if (Name == "avx512f") {
2511     setSSELevel(Features, AVX512F, Enabled);
2512   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2513           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2514     if (Enabled)
2515       setSSELevel(Features, AVX512F, Enabled);
2516   } else if (Name == "fma") {
2517     if (Enabled)
2518       setSSELevel(Features, AVX, Enabled);
2519   } else if (Name == "fma4") {
2520     setXOPLevel(Features, FMA4, Enabled);
2521   } else if (Name == "xop") {
2522     setXOPLevel(Features, XOP, Enabled);
2523   } else if (Name == "sse4a") {
2524     setXOPLevel(Features, SSE4A, Enabled);
2525   } else if (Name == "f16c") {
2526     if (Enabled)
2527       setSSELevel(Features, AVX, Enabled);
2528   } else if (Name == "sha") {
2529     if (Enabled)
2530       setSSELevel(Features, SSE2, Enabled);
2531   }
2532 }
2533 
2534 /// handleTargetFeatures - Perform initialization based on the user
2535 /// configured set of features.
2536 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2537                                          DiagnosticsEngine &Diags) {
2538   // Remember the maximum enabled sselevel.
2539   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2540     // Ignore disabled features.
2541     if (Features[i][0] == '-')
2542       continue;
2543 
2544     StringRef Feature = StringRef(Features[i]).substr(1);
2545 
2546     if (Feature == "aes") {
2547       HasAES = true;
2548       continue;
2549     }
2550 
2551     if (Feature == "pclmul") {
2552       HasPCLMUL = true;
2553       continue;
2554     }
2555 
2556     if (Feature == "lzcnt") {
2557       HasLZCNT = true;
2558       continue;
2559     }
2560 
2561     if (Feature == "rdrnd") {
2562       HasRDRND = true;
2563       continue;
2564     }
2565 
2566     if (Feature == "fsgsbase") {
2567       HasFSGSBASE = true;
2568       continue;
2569     }
2570 
2571     if (Feature == "bmi") {
2572       HasBMI = true;
2573       continue;
2574     }
2575 
2576     if (Feature == "bmi2") {
2577       HasBMI2 = true;
2578       continue;
2579     }
2580 
2581     if (Feature == "popcnt") {
2582       HasPOPCNT = true;
2583       continue;
2584     }
2585 
2586     if (Feature == "rtm") {
2587       HasRTM = true;
2588       continue;
2589     }
2590 
2591     if (Feature == "prfchw") {
2592       HasPRFCHW = true;
2593       continue;
2594     }
2595 
2596     if (Feature == "rdseed") {
2597       HasRDSEED = true;
2598       continue;
2599     }
2600 
2601     if (Feature == "adx") {
2602       HasADX = true;
2603       continue;
2604     }
2605 
2606     if (Feature == "tbm") {
2607       HasTBM = true;
2608       continue;
2609     }
2610 
2611     if (Feature == "fma") {
2612       HasFMA = true;
2613       continue;
2614     }
2615 
2616     if (Feature == "f16c") {
2617       HasF16C = true;
2618       continue;
2619     }
2620 
2621     if (Feature == "avx512cd") {
2622       HasAVX512CD = true;
2623       continue;
2624     }
2625 
2626     if (Feature == "avx512er") {
2627       HasAVX512ER = true;
2628       continue;
2629     }
2630 
2631     if (Feature == "avx512pf") {
2632       HasAVX512PF = true;
2633       continue;
2634     }
2635 
2636     if (Feature == "avx512dq") {
2637       HasAVX512DQ = true;
2638       continue;
2639     }
2640 
2641     if (Feature == "avx512bw") {
2642       HasAVX512BW = true;
2643       continue;
2644     }
2645 
2646     if (Feature == "avx512vl") {
2647       HasAVX512VL = true;
2648       continue;
2649     }
2650 
2651     if (Feature == "sha") {
2652       HasSHA = true;
2653       continue;
2654     }
2655 
2656     if (Feature == "cx16") {
2657       HasCX16 = true;
2658       continue;
2659     }
2660 
2661     assert(Features[i][0] == '+' && "Invalid target feature!");
2662     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2663       .Case("avx512f", AVX512F)
2664       .Case("avx2", AVX2)
2665       .Case("avx", AVX)
2666       .Case("sse4.2", SSE42)
2667       .Case("sse4.1", SSE41)
2668       .Case("ssse3", SSSE3)
2669       .Case("sse3", SSE3)
2670       .Case("sse2", SSE2)
2671       .Case("sse", SSE1)
2672       .Default(NoSSE);
2673     SSELevel = std::max(SSELevel, Level);
2674 
2675     MMX3DNowEnum ThreeDNowLevel =
2676       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2677         .Case("3dnowa", AMD3DNowAthlon)
2678         .Case("3dnow", AMD3DNow)
2679         .Case("mmx", MMX)
2680         .Default(NoMMX3DNow);
2681     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2682 
2683     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2684         .Case("xop", XOP)
2685         .Case("fma4", FMA4)
2686         .Case("sse4a", SSE4A)
2687         .Default(NoXOP);
2688     XOPLevel = std::max(XOPLevel, XLevel);
2689   }
2690 
2691   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2692   // Can't do this earlier because we need to be able to explicitly enable
2693   // popcnt and still disable sse4.2.
2694   if (!HasPOPCNT && SSELevel >= SSE42 &&
2695       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2696     HasPOPCNT = true;
2697     Features.push_back("+popcnt");
2698   }
2699 
2700   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2701   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2702       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2703     HasPRFCHW = true;
2704     Features.push_back("+prfchw");
2705   }
2706 
2707   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2708   // matches the selected sse level.
2709   if (FPMath == FP_SSE && SSELevel < SSE1) {
2710     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2711     return false;
2712   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2713     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2714     return false;
2715   }
2716 
2717   // Don't tell the backend if we're turning off mmx; it will end up disabling
2718   // SSE, which we don't want.
2719   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2720   // then enable MMX.
2721   std::vector<std::string>::iterator it;
2722   it = std::find(Features.begin(), Features.end(), "-mmx");
2723   if (it != Features.end())
2724     Features.erase(it);
2725   else if (SSELevel > NoSSE)
2726     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2727   return true;
2728 }
2729 
2730 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2731 /// definitions for this particular subtarget.
2732 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2733                                      MacroBuilder &Builder) const {
2734   // Target identification.
2735   if (getTriple().getArch() == llvm::Triple::x86_64) {
2736     Builder.defineMacro("__amd64__");
2737     Builder.defineMacro("__amd64");
2738     Builder.defineMacro("__x86_64");
2739     Builder.defineMacro("__x86_64__");
2740     if (getTriple().getArchName() == "x86_64h") {
2741       Builder.defineMacro("__x86_64h");
2742       Builder.defineMacro("__x86_64h__");
2743     }
2744   } else {
2745     DefineStd(Builder, "i386", Opts);
2746   }
2747 
2748   // Subtarget options.
2749   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2750   // truly should be based on -mtune options.
2751   switch (CPU) {
2752   case CK_Generic:
2753     break;
2754   case CK_i386:
2755     // The rest are coming from the i386 define above.
2756     Builder.defineMacro("__tune_i386__");
2757     break;
2758   case CK_i486:
2759   case CK_WinChipC6:
2760   case CK_WinChip2:
2761   case CK_C3:
2762     defineCPUMacros(Builder, "i486");
2763     break;
2764   case CK_PentiumMMX:
2765     Builder.defineMacro("__pentium_mmx__");
2766     Builder.defineMacro("__tune_pentium_mmx__");
2767     // Fallthrough
2768   case CK_i586:
2769   case CK_Pentium:
2770     defineCPUMacros(Builder, "i586");
2771     defineCPUMacros(Builder, "pentium");
2772     break;
2773   case CK_Pentium3:
2774   case CK_Pentium3M:
2775   case CK_PentiumM:
2776     Builder.defineMacro("__tune_pentium3__");
2777     // Fallthrough
2778   case CK_Pentium2:
2779   case CK_C3_2:
2780     Builder.defineMacro("__tune_pentium2__");
2781     // Fallthrough
2782   case CK_PentiumPro:
2783     Builder.defineMacro("__tune_i686__");
2784     Builder.defineMacro("__tune_pentiumpro__");
2785     // Fallthrough
2786   case CK_i686:
2787     Builder.defineMacro("__i686");
2788     Builder.defineMacro("__i686__");
2789     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2790     Builder.defineMacro("__pentiumpro");
2791     Builder.defineMacro("__pentiumpro__");
2792     break;
2793   case CK_Pentium4:
2794   case CK_Pentium4M:
2795     defineCPUMacros(Builder, "pentium4");
2796     break;
2797   case CK_Yonah:
2798   case CK_Prescott:
2799   case CK_Nocona:
2800     defineCPUMacros(Builder, "nocona");
2801     break;
2802   case CK_Core2:
2803   case CK_Penryn:
2804     defineCPUMacros(Builder, "core2");
2805     break;
2806   case CK_Atom:
2807     defineCPUMacros(Builder, "atom");
2808     break;
2809   case CK_Silvermont:
2810     defineCPUMacros(Builder, "slm");
2811     break;
2812   case CK_Corei7:
2813   case CK_Corei7AVX:
2814   case CK_CoreAVXi:
2815   case CK_CoreAVX2:
2816   case CK_Broadwell:
2817     defineCPUMacros(Builder, "corei7");
2818     break;
2819   case CK_KNL:
2820     defineCPUMacros(Builder, "knl");
2821     break;
2822   case CK_SKX:
2823     defineCPUMacros(Builder, "skx");
2824     break;
2825   case CK_K6_2:
2826     Builder.defineMacro("__k6_2__");
2827     Builder.defineMacro("__tune_k6_2__");
2828     // Fallthrough
2829   case CK_K6_3:
2830     if (CPU != CK_K6_2) {  // In case of fallthrough
2831       // FIXME: GCC may be enabling these in cases where some other k6
2832       // architecture is specified but -m3dnow is explicitly provided. The
2833       // exact semantics need to be determined and emulated here.
2834       Builder.defineMacro("__k6_3__");
2835       Builder.defineMacro("__tune_k6_3__");
2836     }
2837     // Fallthrough
2838   case CK_K6:
2839     defineCPUMacros(Builder, "k6");
2840     break;
2841   case CK_Athlon:
2842   case CK_AthlonThunderbird:
2843   case CK_Athlon4:
2844   case CK_AthlonXP:
2845   case CK_AthlonMP:
2846     defineCPUMacros(Builder, "athlon");
2847     if (SSELevel != NoSSE) {
2848       Builder.defineMacro("__athlon_sse__");
2849       Builder.defineMacro("__tune_athlon_sse__");
2850     }
2851     break;
2852   case CK_K8:
2853   case CK_K8SSE3:
2854   case CK_x86_64:
2855   case CK_Opteron:
2856   case CK_OpteronSSE3:
2857   case CK_Athlon64:
2858   case CK_Athlon64SSE3:
2859   case CK_AthlonFX:
2860     defineCPUMacros(Builder, "k8");
2861     break;
2862   case CK_AMDFAM10:
2863     defineCPUMacros(Builder, "amdfam10");
2864     break;
2865   case CK_BTVER1:
2866     defineCPUMacros(Builder, "btver1");
2867     break;
2868   case CK_BTVER2:
2869     defineCPUMacros(Builder, "btver2");
2870     break;
2871   case CK_BDVER1:
2872     defineCPUMacros(Builder, "bdver1");
2873     break;
2874   case CK_BDVER2:
2875     defineCPUMacros(Builder, "bdver2");
2876     break;
2877   case CK_BDVER3:
2878     defineCPUMacros(Builder, "bdver3");
2879     break;
2880   case CK_BDVER4:
2881     defineCPUMacros(Builder, "bdver4");
2882     break;
2883   case CK_Geode:
2884     defineCPUMacros(Builder, "geode");
2885     break;
2886   }
2887 
2888   // Target properties.
2889   Builder.defineMacro("__REGISTER_PREFIX__", "");
2890 
2891   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2892   // functions in glibc header files that use FP Stack inline asm which the
2893   // backend can't deal with (PR879).
2894   Builder.defineMacro("__NO_MATH_INLINES");
2895 
2896   if (HasAES)
2897     Builder.defineMacro("__AES__");
2898 
2899   if (HasPCLMUL)
2900     Builder.defineMacro("__PCLMUL__");
2901 
2902   if (HasLZCNT)
2903     Builder.defineMacro("__LZCNT__");
2904 
2905   if (HasRDRND)
2906     Builder.defineMacro("__RDRND__");
2907 
2908   if (HasFSGSBASE)
2909     Builder.defineMacro("__FSGSBASE__");
2910 
2911   if (HasBMI)
2912     Builder.defineMacro("__BMI__");
2913 
2914   if (HasBMI2)
2915     Builder.defineMacro("__BMI2__");
2916 
2917   if (HasPOPCNT)
2918     Builder.defineMacro("__POPCNT__");
2919 
2920   if (HasRTM)
2921     Builder.defineMacro("__RTM__");
2922 
2923   if (HasPRFCHW)
2924     Builder.defineMacro("__PRFCHW__");
2925 
2926   if (HasRDSEED)
2927     Builder.defineMacro("__RDSEED__");
2928 
2929   if (HasADX)
2930     Builder.defineMacro("__ADX__");
2931 
2932   if (HasTBM)
2933     Builder.defineMacro("__TBM__");
2934 
2935   switch (XOPLevel) {
2936   case XOP:
2937     Builder.defineMacro("__XOP__");
2938   case FMA4:
2939     Builder.defineMacro("__FMA4__");
2940   case SSE4A:
2941     Builder.defineMacro("__SSE4A__");
2942   case NoXOP:
2943     break;
2944   }
2945 
2946   if (HasFMA)
2947     Builder.defineMacro("__FMA__");
2948 
2949   if (HasF16C)
2950     Builder.defineMacro("__F16C__");
2951 
2952   if (HasAVX512CD)
2953     Builder.defineMacro("__AVX512CD__");
2954   if (HasAVX512ER)
2955     Builder.defineMacro("__AVX512ER__");
2956   if (HasAVX512PF)
2957     Builder.defineMacro("__AVX512PF__");
2958   if (HasAVX512DQ)
2959     Builder.defineMacro("__AVX512DQ__");
2960   if (HasAVX512BW)
2961     Builder.defineMacro("__AVX512BW__");
2962   if (HasAVX512VL)
2963     Builder.defineMacro("__AVX512VL__");
2964 
2965   if (HasSHA)
2966     Builder.defineMacro("__SHA__");
2967 
2968   if (HasCX16)
2969     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2970 
2971   // Each case falls through to the previous one here.
2972   switch (SSELevel) {
2973   case AVX512F:
2974     Builder.defineMacro("__AVX512F__");
2975   case AVX2:
2976     Builder.defineMacro("__AVX2__");
2977   case AVX:
2978     Builder.defineMacro("__AVX__");
2979   case SSE42:
2980     Builder.defineMacro("__SSE4_2__");
2981   case SSE41:
2982     Builder.defineMacro("__SSE4_1__");
2983   case SSSE3:
2984     Builder.defineMacro("__SSSE3__");
2985   case SSE3:
2986     Builder.defineMacro("__SSE3__");
2987   case SSE2:
2988     Builder.defineMacro("__SSE2__");
2989     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2990   case SSE1:
2991     Builder.defineMacro("__SSE__");
2992     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2993   case NoSSE:
2994     break;
2995   }
2996 
2997   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2998     switch (SSELevel) {
2999     case AVX512F:
3000     case AVX2:
3001     case AVX:
3002     case SSE42:
3003     case SSE41:
3004     case SSSE3:
3005     case SSE3:
3006     case SSE2:
3007       Builder.defineMacro("_M_IX86_FP", Twine(2));
3008       break;
3009     case SSE1:
3010       Builder.defineMacro("_M_IX86_FP", Twine(1));
3011       break;
3012     default:
3013       Builder.defineMacro("_M_IX86_FP", Twine(0));
3014     }
3015   }
3016 
3017   // Each case falls through to the previous one here.
3018   switch (MMX3DNowLevel) {
3019   case AMD3DNowAthlon:
3020     Builder.defineMacro("__3dNOW_A__");
3021   case AMD3DNow:
3022     Builder.defineMacro("__3dNOW__");
3023   case MMX:
3024     Builder.defineMacro("__MMX__");
3025   case NoMMX3DNow:
3026     break;
3027   }
3028 
3029   if (CPU >= CK_i486) {
3030     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3031     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3032     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3033   }
3034   if (CPU >= CK_i586)
3035     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3036 }
3037 
3038 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3039   return llvm::StringSwitch<bool>(Feature)
3040       .Case("aes", HasAES)
3041       .Case("avx", SSELevel >= AVX)
3042       .Case("avx2", SSELevel >= AVX2)
3043       .Case("avx512f", SSELevel >= AVX512F)
3044       .Case("avx512cd", HasAVX512CD)
3045       .Case("avx512er", HasAVX512ER)
3046       .Case("avx512pf", HasAVX512PF)
3047       .Case("avx512dq", HasAVX512DQ)
3048       .Case("avx512bw", HasAVX512BW)
3049       .Case("avx512vl", HasAVX512VL)
3050       .Case("bmi", HasBMI)
3051       .Case("bmi2", HasBMI2)
3052       .Case("cx16", HasCX16)
3053       .Case("f16c", HasF16C)
3054       .Case("fma", HasFMA)
3055       .Case("fma4", XOPLevel >= FMA4)
3056       .Case("fsgsbase", HasFSGSBASE)
3057       .Case("lzcnt", HasLZCNT)
3058       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3059       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3060       .Case("mmx", MMX3DNowLevel >= MMX)
3061       .Case("pclmul", HasPCLMUL)
3062       .Case("popcnt", HasPOPCNT)
3063       .Case("prfchw", HasPRFCHW)
3064       .Case("rdrnd", HasRDRND)
3065       .Case("rdseed", HasRDSEED)
3066       .Case("rtm", HasRTM)
3067       .Case("sha", HasSHA)
3068       .Case("sse", SSELevel >= SSE1)
3069       .Case("sse2", SSELevel >= SSE2)
3070       .Case("sse3", SSELevel >= SSE3)
3071       .Case("ssse3", SSELevel >= SSSE3)
3072       .Case("sse4.1", SSELevel >= SSE41)
3073       .Case("sse4.2", SSELevel >= SSE42)
3074       .Case("sse4a", XOPLevel >= SSE4A)
3075       .Case("tbm", HasTBM)
3076       .Case("x86", true)
3077       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3078       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3079       .Case("xop", XOPLevel >= XOP)
3080       .Default(false);
3081 }
3082 
3083 bool
3084 X86TargetInfo::validateAsmConstraint(const char *&Name,
3085                                      TargetInfo::ConstraintInfo &Info) const {
3086   switch (*Name) {
3087   default: return false;
3088   case 'Y': // first letter of a pair:
3089     switch (*(Name+1)) {
3090     default: return false;
3091     case '0':  // First SSE register.
3092     case 't':  // Any SSE register, when SSE2 is enabled.
3093     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3094     case 'm':  // any MMX register, when inter-unit moves enabled.
3095       break;   // falls through to setAllowsRegister.
3096   }
3097   case 'f': // any x87 floating point stack register.
3098     // Constraint 'f' cannot be used for output operands.
3099     if (Info.ConstraintStr[0] == '=')
3100       return false;
3101 
3102     Info.setAllowsRegister();
3103     return true;
3104   case 'a': // eax.
3105   case 'b': // ebx.
3106   case 'c': // ecx.
3107   case 'd': // edx.
3108   case 'S': // esi.
3109   case 'D': // edi.
3110   case 'A': // edx:eax.
3111   case 't': // top of floating point stack.
3112   case 'u': // second from top of floating point stack.
3113   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3114   case 'y': // Any MMX register.
3115   case 'x': // Any SSE register.
3116   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3117   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3118   case 'l': // "Index" registers: any general register that can be used as an
3119             // index in a base+index memory access.
3120     Info.setAllowsRegister();
3121     return true;
3122   case 'C': // SSE floating point constant.
3123   case 'G': // x87 floating point constant.
3124   case 'e': // 32-bit signed integer constant for use with zero-extending
3125             // x86_64 instructions.
3126   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3127             // x86_64 instructions.
3128     return true;
3129   }
3130 }
3131 
3132 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3133                                        unsigned Size) const {
3134   // Strip off constraint modifiers.
3135   while (Constraint[0] == '=' ||
3136          Constraint[0] == '+' ||
3137          Constraint[0] == '&')
3138     Constraint = Constraint.substr(1);
3139 
3140   return validateOperandSize(Constraint, Size);
3141 }
3142 
3143 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3144                                       unsigned Size) const {
3145   return validateOperandSize(Constraint, Size);
3146 }
3147 
3148 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3149                                         unsigned Size) const {
3150   switch (Constraint[0]) {
3151   default: break;
3152   case 'y':
3153     return Size <= 64;
3154   case 'f':
3155   case 't':
3156   case 'u':
3157     return Size <= 128;
3158   case 'x':
3159     // 256-bit ymm registers can be used if target supports AVX.
3160     return Size <= (SSELevel >= AVX ? 256U : 128U);
3161   }
3162 
3163   return true;
3164 }
3165 
3166 std::string
3167 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3168   switch (*Constraint) {
3169   case 'a': return std::string("{ax}");
3170   case 'b': return std::string("{bx}");
3171   case 'c': return std::string("{cx}");
3172   case 'd': return std::string("{dx}");
3173   case 'S': return std::string("{si}");
3174   case 'D': return std::string("{di}");
3175   case 'p': // address
3176     return std::string("im");
3177   case 't': // top of floating point stack.
3178     return std::string("{st}");
3179   case 'u': // second from top of floating point stack.
3180     return std::string("{st(1)}"); // second from top of floating point stack.
3181   default:
3182     return std::string(1, *Constraint);
3183   }
3184 }
3185 } // end anonymous namespace
3186 
3187 namespace {
3188 // X86-32 generic target
3189 class X86_32TargetInfo : public X86TargetInfo {
3190 public:
3191   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3192     DoubleAlign = LongLongAlign = 32;
3193     LongDoubleWidth = 96;
3194     LongDoubleAlign = 32;
3195     SuitableAlign = 128;
3196     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3197     SizeType = UnsignedInt;
3198     PtrDiffType = SignedInt;
3199     IntPtrType = SignedInt;
3200     RegParmMax = 3;
3201 
3202     // Use fpret for all types.
3203     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3204                              (1 << TargetInfo::Double) |
3205                              (1 << TargetInfo::LongDouble));
3206 
3207     // x86-32 has atomics up to 8 bytes
3208     // FIXME: Check that we actually have cmpxchg8b before setting
3209     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3210     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3211   }
3212   BuiltinVaListKind getBuiltinVaListKind() const override {
3213     return TargetInfo::CharPtrBuiltinVaList;
3214   }
3215 
3216   int getEHDataRegisterNumber(unsigned RegNo) const override {
3217     if (RegNo == 0) return 0;
3218     if (RegNo == 1) return 2;
3219     return -1;
3220   }
3221   bool validateOperandSize(StringRef Constraint,
3222                            unsigned Size) const override {
3223     switch (Constraint[0]) {
3224     default: break;
3225     case 'R':
3226     case 'q':
3227     case 'Q':
3228     case 'a':
3229     case 'b':
3230     case 'c':
3231     case 'd':
3232     case 'S':
3233     case 'D':
3234       return Size <= 32;
3235     case 'A':
3236       return Size <= 64;
3237     }
3238 
3239     return X86TargetInfo::validateOperandSize(Constraint, Size);
3240   }
3241 };
3242 } // end anonymous namespace
3243 
3244 namespace {
3245 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3246 public:
3247   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3248       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3249 
3250   unsigned getFloatEvalMethod() const override {
3251     unsigned Major, Minor, Micro;
3252     getTriple().getOSVersion(Major, Minor, Micro);
3253     // New NetBSD uses the default rounding mode.
3254     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3255       return X86_32TargetInfo::getFloatEvalMethod();
3256     // NetBSD before 6.99.26 defaults to "double" rounding.
3257     return 1;
3258   }
3259 };
3260 } // end anonymous namespace
3261 
3262 namespace {
3263 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3264 public:
3265   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3266       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3267     SizeType = UnsignedLong;
3268     IntPtrType = SignedLong;
3269     PtrDiffType = SignedLong;
3270   }
3271 };
3272 } // end anonymous namespace
3273 
3274 namespace {
3275 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3276 public:
3277   BitrigI386TargetInfo(const llvm::Triple &Triple)
3278       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3279     SizeType = UnsignedLong;
3280     IntPtrType = SignedLong;
3281     PtrDiffType = SignedLong;
3282   }
3283 };
3284 } // end anonymous namespace
3285 
3286 namespace {
3287 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3288 public:
3289   DarwinI386TargetInfo(const llvm::Triple &Triple)
3290       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3291     LongDoubleWidth = 128;
3292     LongDoubleAlign = 128;
3293     SuitableAlign = 128;
3294     MaxVectorAlign = 256;
3295     SizeType = UnsignedLong;
3296     IntPtrType = SignedLong;
3297     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3298     HasAlignMac68kSupport = true;
3299   }
3300 
3301 };
3302 } // end anonymous namespace
3303 
3304 namespace {
3305 // x86-32 Windows target
3306 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3307 public:
3308   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3309       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3310     WCharType = UnsignedShort;
3311     DoubleAlign = LongLongAlign = 64;
3312     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3313   }
3314   void getTargetDefines(const LangOptions &Opts,
3315                         MacroBuilder &Builder) const override {
3316     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3317   }
3318 };
3319 
3320 // x86-32 Windows Visual Studio target
3321 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3322 public:
3323   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3324       : WindowsX86_32TargetInfo(Triple) {
3325     LongDoubleWidth = LongDoubleAlign = 64;
3326     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3327   }
3328   void getTargetDefines(const LangOptions &Opts,
3329                         MacroBuilder &Builder) const override {
3330     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3331     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3332     // The value of the following reflects processor type.
3333     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3334     // We lost the original triple, so we use the default.
3335     Builder.defineMacro("_M_IX86", "600");
3336   }
3337 };
3338 } // end anonymous namespace
3339 
3340 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3341   Builder.defineMacro("__MSVCRT__");
3342   Builder.defineMacro("__MINGW32__");
3343 
3344   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3345   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3346   // macro anyway for pre-processor compatibility.
3347   if (Opts.MicrosoftExt)
3348     Builder.defineMacro("__declspec", "__declspec");
3349   else
3350     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3351 
3352   if (!Opts.MicrosoftExt) {
3353     // Provide macros for all the calling convention keywords.  Provide both
3354     // single and double underscore prefixed variants.  These are available on
3355     // x64 as well as x86, even though they have no effect.
3356     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3357     for (const char *CC : CCs) {
3358       std::string GCCSpelling = "__attribute__((__";
3359       GCCSpelling += CC;
3360       GCCSpelling += "__))";
3361       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3362       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3363     }
3364   }
3365 }
3366 
3367 namespace {
3368 // x86-32 MinGW target
3369 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3370 public:
3371   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3372       : WindowsX86_32TargetInfo(Triple) {}
3373   void getTargetDefines(const LangOptions &Opts,
3374                         MacroBuilder &Builder) const override {
3375     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3376     DefineStd(Builder, "WIN32", Opts);
3377     DefineStd(Builder, "WINNT", Opts);
3378     Builder.defineMacro("_X86_");
3379     addMinGWDefines(Opts, Builder);
3380   }
3381 };
3382 } // end anonymous namespace
3383 
3384 namespace {
3385 // x86-32 Cygwin target
3386 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3387 public:
3388   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3389       : X86_32TargetInfo(Triple) {
3390     TLSSupported = false;
3391     WCharType = UnsignedShort;
3392     DoubleAlign = LongLongAlign = 64;
3393     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3394   }
3395   void getTargetDefines(const LangOptions &Opts,
3396                         MacroBuilder &Builder) const override {
3397     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3398     Builder.defineMacro("_X86_");
3399     Builder.defineMacro("__CYGWIN__");
3400     Builder.defineMacro("__CYGWIN32__");
3401     DefineStd(Builder, "unix", Opts);
3402     if (Opts.CPlusPlus)
3403       Builder.defineMacro("_GNU_SOURCE");
3404   }
3405 };
3406 } // end anonymous namespace
3407 
3408 namespace {
3409 // x86-32 Haiku target
3410 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3411 public:
3412   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3413     SizeType = UnsignedLong;
3414     IntPtrType = SignedLong;
3415     PtrDiffType = SignedLong;
3416     ProcessIDType = SignedLong;
3417     this->UserLabelPrefix = "";
3418     this->TLSSupported = false;
3419   }
3420   void getTargetDefines(const LangOptions &Opts,
3421                         MacroBuilder &Builder) const override {
3422     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3423     Builder.defineMacro("__INTEL__");
3424     Builder.defineMacro("__HAIKU__");
3425   }
3426 };
3427 } // end anonymous namespace
3428 
3429 // RTEMS Target
3430 template<typename Target>
3431 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3432 protected:
3433   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3434                     MacroBuilder &Builder) const override {
3435     // RTEMS defines; list based off of gcc output
3436 
3437     Builder.defineMacro("__rtems__");
3438     Builder.defineMacro("__ELF__");
3439   }
3440 
3441 public:
3442   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3443     this->UserLabelPrefix = "";
3444 
3445     switch (Triple.getArch()) {
3446     default:
3447     case llvm::Triple::x86:
3448       // this->MCountName = ".mcount";
3449       break;
3450     case llvm::Triple::mips:
3451     case llvm::Triple::mipsel:
3452     case llvm::Triple::ppc:
3453     case llvm::Triple::ppc64:
3454     case llvm::Triple::ppc64le:
3455       // this->MCountName = "_mcount";
3456       break;
3457     case llvm::Triple::arm:
3458       // this->MCountName = "__mcount";
3459       break;
3460     }
3461   }
3462 };
3463 
3464 namespace {
3465 // x86-32 RTEMS target
3466 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3467 public:
3468   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3469     SizeType = UnsignedLong;
3470     IntPtrType = SignedLong;
3471     PtrDiffType = SignedLong;
3472     this->UserLabelPrefix = "";
3473   }
3474   void getTargetDefines(const LangOptions &Opts,
3475                         MacroBuilder &Builder) const override {
3476     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3477     Builder.defineMacro("__INTEL__");
3478     Builder.defineMacro("__rtems__");
3479   }
3480 };
3481 } // end anonymous namespace
3482 
3483 namespace {
3484 // x86-64 generic target
3485 class X86_64TargetInfo : public X86TargetInfo {
3486 public:
3487   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3488     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3489     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3490     LongDoubleWidth = 128;
3491     LongDoubleAlign = 128;
3492     LargeArrayMinWidth = 128;
3493     LargeArrayAlign = 128;
3494     SuitableAlign = 128;
3495     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3496     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3497     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3498     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3499     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3500     RegParmMax = 6;
3501 
3502     DescriptionString = (IsX32)
3503                             ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
3504                             : "e-m:e-"            "i64:64-f80:128-n8:16:32:64-S128";
3505 
3506     // Use fpret only for long double.
3507     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3508 
3509     // Use fp2ret for _Complex long double.
3510     ComplexLongDoubleUsesFP2Ret = true;
3511 
3512     // x86-64 has atomics up to 16 bytes.
3513     MaxAtomicPromoteWidth = 128;
3514     MaxAtomicInlineWidth = 128;
3515   }
3516   BuiltinVaListKind getBuiltinVaListKind() const override {
3517     return TargetInfo::X86_64ABIBuiltinVaList;
3518   }
3519 
3520   int getEHDataRegisterNumber(unsigned RegNo) const override {
3521     if (RegNo == 0) return 0;
3522     if (RegNo == 1) return 1;
3523     return -1;
3524   }
3525 
3526   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3527     return (CC == CC_C ||
3528             CC == CC_X86VectorCall ||
3529             CC == CC_IntelOclBicc ||
3530             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3531   }
3532 
3533   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3534     return CC_C;
3535   }
3536 
3537   // for x32 we need it here explicitly
3538   bool hasInt128Type() const override { return true; }
3539 };
3540 } // end anonymous namespace
3541 
3542 namespace {
3543 // x86-64 Windows target
3544 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3545 public:
3546   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3547       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3548     WCharType = UnsignedShort;
3549     LongWidth = LongAlign = 32;
3550     DoubleAlign = LongLongAlign = 64;
3551     IntMaxType = SignedLongLong;
3552     Int64Type = SignedLongLong;
3553     SizeType = UnsignedLongLong;
3554     PtrDiffType = SignedLongLong;
3555     IntPtrType = SignedLongLong;
3556     this->UserLabelPrefix = "";
3557   }
3558   void getTargetDefines(const LangOptions &Opts,
3559                                 MacroBuilder &Builder) const override {
3560     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3561     Builder.defineMacro("_WIN64");
3562   }
3563   BuiltinVaListKind getBuiltinVaListKind() const override {
3564     return TargetInfo::CharPtrBuiltinVaList;
3565   }
3566   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3567     return (CC == CC_C ||
3568             CC == CC_X86VectorCall ||
3569             CC == CC_IntelOclBicc ||
3570             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3571   }
3572 };
3573 } // end anonymous namespace
3574 
3575 namespace {
3576 // x86-64 Windows Visual Studio target
3577 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3578 public:
3579   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3580       : WindowsX86_64TargetInfo(Triple) {
3581     LongDoubleWidth = LongDoubleAlign = 64;
3582     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3583   }
3584   void getTargetDefines(const LangOptions &Opts,
3585                         MacroBuilder &Builder) const override {
3586     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3587     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3588     Builder.defineMacro("_M_X64");
3589     Builder.defineMacro("_M_AMD64");
3590   }
3591 };
3592 } // end anonymous namespace
3593 
3594 namespace {
3595 // x86-64 MinGW target
3596 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3597 public:
3598   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3599       : WindowsX86_64TargetInfo(Triple) {}
3600   void getTargetDefines(const LangOptions &Opts,
3601                         MacroBuilder &Builder) const override {
3602     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3603     DefineStd(Builder, "WIN64", Opts);
3604     Builder.defineMacro("__MINGW64__");
3605     addMinGWDefines(Opts, Builder);
3606   }
3607 };
3608 } // end anonymous namespace
3609 
3610 namespace {
3611 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3612 public:
3613   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3614       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3615     Int64Type = SignedLongLong;
3616     MaxVectorAlign = 256;
3617     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3618     llvm::Triple T = llvm::Triple(Triple);
3619     if (T.isiOS())
3620       UseSignedCharForObjCBool = false;
3621     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3622   }
3623 };
3624 } // end anonymous namespace
3625 
3626 namespace {
3627 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3628 public:
3629   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3630       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3631     IntMaxType = SignedLongLong;
3632     Int64Type = SignedLongLong;
3633   }
3634 };
3635 } // end anonymous namespace
3636 
3637 namespace {
3638 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3639 public:
3640   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3641       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3642     IntMaxType = SignedLongLong;
3643     Int64Type = SignedLongLong;
3644   }
3645 };
3646 }
3647 
3648 
3649 namespace {
3650 class ARMTargetInfo : public TargetInfo {
3651   // Possible FPU choices.
3652   enum FPUMode {
3653     VFP2FPU = (1 << 0),
3654     VFP3FPU = (1 << 1),
3655     VFP4FPU = (1 << 2),
3656     NeonFPU = (1 << 3),
3657     FPARMV8 = (1 << 4)
3658   };
3659 
3660   // Possible HWDiv features.
3661   enum HWDivMode {
3662     HWDivThumb = (1 << 0),
3663     HWDivARM = (1 << 1)
3664   };
3665 
3666   static bool FPUModeIsVFP(FPUMode Mode) {
3667     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3668   }
3669 
3670   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3671   static const char * const GCCRegNames[];
3672 
3673   std::string ABI, CPU;
3674 
3675   enum {
3676     FP_Default,
3677     FP_VFP,
3678     FP_Neon
3679   } FPMath;
3680 
3681   unsigned FPU : 5;
3682 
3683   unsigned IsAAPCS : 1;
3684   unsigned IsThumb : 1;
3685   unsigned HWDiv : 2;
3686 
3687   // Initialized via features.
3688   unsigned SoftFloat : 1;
3689   unsigned SoftFloatABI : 1;
3690 
3691   unsigned CRC : 1;
3692   unsigned Crypto : 1;
3693 
3694   // ACLE 6.5.1 Hardware floating point
3695   enum {
3696     HW_FP_HP = (1 << 1), /// half (16-bit)
3697     HW_FP_SP = (1 << 2), /// single (32-bit)
3698     HW_FP_DP = (1 << 3), /// double (64-bit)
3699   };
3700   uint32_t HW_FP;
3701 
3702   static const Builtin::Info BuiltinInfo[];
3703 
3704   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3705     StringRef ArchName = T.getArchName();
3706     if (T.getArch() == llvm::Triple::arm ||
3707         T.getArch() == llvm::Triple::armeb) {
3708       StringRef VersionStr;
3709       if (ArchName.startswith("armv"))
3710         VersionStr = ArchName.substr(4, 1);
3711       else if (ArchName.startswith("armebv"))
3712         VersionStr = ArchName.substr(6, 1);
3713       else
3714         return false;
3715       unsigned Version;
3716       if (VersionStr.getAsInteger(10, Version))
3717         return false;
3718       return Version >= 6;
3719     }
3720     assert(T.getArch() == llvm::Triple::thumb ||
3721            T.getArch() == llvm::Triple::thumbeb);
3722     StringRef VersionStr;
3723     if (ArchName.startswith("thumbv"))
3724       VersionStr = ArchName.substr(6, 1);
3725     else if (ArchName.startswith("thumbebv"))
3726       VersionStr = ArchName.substr(8, 1);
3727     else
3728       return false;
3729     unsigned Version;
3730     if (VersionStr.getAsInteger(10, Version))
3731       return false;
3732     return Version >= 7;
3733   }
3734 
3735   void setABIAAPCS() {
3736     IsAAPCS = true;
3737 
3738     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3739     const llvm::Triple &T = getTriple();
3740 
3741     // size_t is unsigned long on MachO-derived environments and NetBSD.
3742     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3743       SizeType = UnsignedLong;
3744     else
3745       SizeType = UnsignedInt;
3746 
3747     switch (T.getOS()) {
3748     case llvm::Triple::NetBSD:
3749       WCharType = SignedInt;
3750       break;
3751     case llvm::Triple::Win32:
3752       WCharType = UnsignedShort;
3753       break;
3754     case llvm::Triple::Linux:
3755     default:
3756       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3757       WCharType = UnsignedInt;
3758       break;
3759     }
3760 
3761     UseBitFieldTypeAlignment = true;
3762 
3763     ZeroLengthBitfieldBoundary = 0;
3764 
3765     // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3766     // so set preferred for small types to 32.
3767     if (T.isOSBinFormatMachO()) {
3768       DescriptionString =
3769           BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3770                     : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3771     } else if (T.isOSWindows()) {
3772       // FIXME: this is invalid for WindowsCE
3773       assert(!BigEndian && "Windows on ARM does not support big endian");
3774       DescriptionString = "e"
3775                           "-m:e"
3776                           "-p:32:32"
3777                           "-i64:64"
3778                           "-v128:64:128"
3779                           "-a:0:32"
3780                           "-n32"
3781                           "-S64";
3782     } else {
3783       DescriptionString =
3784           BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
3785                     : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64";
3786     }
3787 
3788     // FIXME: Enumerated types are variable width in straight AAPCS.
3789   }
3790 
3791   void setABIAPCS() {
3792     const llvm::Triple &T = getTriple();
3793 
3794     IsAAPCS = false;
3795 
3796     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3797 
3798     // size_t is unsigned int on FreeBSD.
3799     if (T.getOS() == llvm::Triple::FreeBSD)
3800       SizeType = UnsignedInt;
3801     else
3802       SizeType = UnsignedLong;
3803 
3804     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3805     WCharType = SignedInt;
3806 
3807     // Do not respect the alignment of bit-field types when laying out
3808     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3809     UseBitFieldTypeAlignment = false;
3810 
3811     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3812     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3813     /// gcc.
3814     ZeroLengthBitfieldBoundary = 32;
3815 
3816     if (T.isOSBinFormatMachO())
3817       DescriptionString =
3818           BigEndian
3819               ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3820               : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3821     else
3822       DescriptionString =
3823           BigEndian
3824               ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
3825               : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3826 
3827     // FIXME: Override "preferred align" for double and long long.
3828   }
3829 
3830 public:
3831   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3832       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3833         IsAAPCS(true), HW_FP(0) {
3834     BigEndian = IsBigEndian;
3835 
3836     switch (getTriple().getOS()) {
3837     case llvm::Triple::NetBSD:
3838       PtrDiffType = SignedLong;
3839       break;
3840     default:
3841       PtrDiffType = SignedInt;
3842       break;
3843     }
3844 
3845     // {} in inline assembly are neon specifiers, not assembly variant
3846     // specifiers.
3847     NoAsmVariants = true;
3848 
3849     // FIXME: Should we just treat this as a feature?
3850     IsThumb = getTriple().getArchName().startswith("thumb");
3851 
3852     setABI("aapcs-linux");
3853 
3854     // ARM targets default to using the ARM C++ ABI.
3855     TheCXXABI.set(TargetCXXABI::GenericARM);
3856 
3857     // ARM has atomics up to 8 bytes
3858     MaxAtomicPromoteWidth = 64;
3859     if (shouldUseInlineAtomic(getTriple()))
3860       MaxAtomicInlineWidth = 64;
3861 
3862     // Do force alignment of members that follow zero length bitfields.  If
3863     // the alignment of the zero-length bitfield is greater than the member
3864     // that follows it, `bar', `bar' will be aligned as the  type of the
3865     // zero length bitfield.
3866     UseZeroLengthBitfieldAlignment = true;
3867   }
3868   StringRef getABI() const override { return ABI; }
3869   bool setABI(const std::string &Name) override {
3870     ABI = Name;
3871 
3872     // The defaults (above) are for AAPCS, check if we need to change them.
3873     //
3874     // FIXME: We need support for -meabi... we could just mangle it into the
3875     // name.
3876     if (Name == "apcs-gnu") {
3877       setABIAPCS();
3878       return true;
3879     }
3880     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3881       setABIAAPCS();
3882       return true;
3883     }
3884     return false;
3885   }
3886 
3887   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3888     if (IsAAPCS)
3889       Features["aapcs"] = true;
3890     else
3891       Features["apcs"] = true;
3892 
3893     StringRef ArchName = getTriple().getArchName();
3894     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3895       Features["vfp2"] = true;
3896     else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3897              CPU == "cortex-a9-mp") {
3898       Features["vfp3"] = true;
3899       Features["neon"] = true;
3900     }
3901     else if (CPU == "cortex-a5") {
3902       Features["vfp4"] = true;
3903       Features["neon"] = true;
3904     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3905                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3906                CPU == "cortex-a17" || CPU == "krait") {
3907       Features["vfp4"] = true;
3908       Features["neon"] = true;
3909       Features["hwdiv"] = true;
3910       Features["hwdiv-arm"] = true;
3911     } else if (CPU == "cyclone") {
3912       Features["v8fp"] = true;
3913       Features["neon"] = true;
3914       Features["hwdiv"] = true;
3915       Features["hwdiv-arm"] = true;
3916     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3917       Features["fp-armv8"] = true;
3918       Features["neon"] = true;
3919       Features["hwdiv"] = true;
3920       Features["hwdiv-arm"] = true;
3921       Features["crc"] = true;
3922       Features["crypto"] = true;
3923     } else if (CPU == "cortex-r5" ||
3924                // Enable the hwdiv extension for all v8a AArch32 cores by
3925                // default.
3926                ArchName == "armv8a" || ArchName == "armv8" ||
3927                ArchName == "armebv8a" || ArchName == "armebv8" ||
3928                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3929                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3930       Features["hwdiv"] = true;
3931       Features["hwdiv-arm"] = true;
3932     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
3933       Features["hwdiv"] = true;
3934     }
3935   }
3936 
3937   bool handleTargetFeatures(std::vector<std::string> &Features,
3938                             DiagnosticsEngine &Diags) override {
3939     FPU = 0;
3940     CRC = 0;
3941     Crypto = 0;
3942     SoftFloat = SoftFloatABI = false;
3943     HWDiv = 0;
3944 
3945     for (const auto &Feature : Features) {
3946       if (Feature == "+soft-float") {
3947         SoftFloat = true;
3948       } else if (Feature == "+soft-float-abi") {
3949         SoftFloatABI = true;
3950       } else if (Feature == "+vfp2") {
3951         FPU |= VFP2FPU;
3952         HW_FP = HW_FP_SP | HW_FP_DP;
3953       } else if (Feature == "+vfp3") {
3954         FPU |= VFP3FPU;
3955         HW_FP = HW_FP_SP | HW_FP_DP;
3956       } else if (Feature == "+vfp4") {
3957         FPU |= VFP4FPU;
3958         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3959       } else if (Feature == "+fp-armv8") {
3960         FPU |= FPARMV8;
3961         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3962       } else if (Feature == "+neon") {
3963         FPU |= NeonFPU;
3964         HW_FP = HW_FP_SP | HW_FP_DP;
3965       } else if (Feature == "+hwdiv") {
3966         HWDiv |= HWDivThumb;
3967       } else if (Feature == "+hwdiv-arm") {
3968         HWDiv |= HWDivARM;
3969       } else if (Feature == "+crc") {
3970         CRC = 1;
3971       } else if (Feature == "+crypto") {
3972         Crypto = 1;
3973       } else if (Feature == "+fp-only-sp") {
3974         HW_FP &= ~HW_FP_DP;
3975       }
3976     }
3977 
3978     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3979       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3980       return false;
3981     }
3982 
3983     if (FPMath == FP_Neon)
3984       Features.push_back("+neonfp");
3985     else if (FPMath == FP_VFP)
3986       Features.push_back("-neonfp");
3987 
3988     // Remove front-end specific options which the backend handles differently.
3989     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
3990     for (const auto &FEFeature : FrontEndFeatures) {
3991       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
3992       if (Feature != Features.end())
3993         Features.erase(Feature);
3994     }
3995 
3996     return true;
3997   }
3998 
3999   bool hasFeature(StringRef Feature) const override {
4000     return llvm::StringSwitch<bool>(Feature)
4001         .Case("arm", true)
4002         .Case("softfloat", SoftFloat)
4003         .Case("thumb", IsThumb)
4004         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
4005         .Case("hwdiv", HWDiv & HWDivThumb)
4006         .Case("hwdiv-arm", HWDiv & HWDivARM)
4007         .Default(false);
4008   }
4009   // FIXME: Should we actually have some table instead of these switches?
4010   static const char *getCPUDefineSuffix(StringRef Name) {
4011     return llvm::StringSwitch<const char*>(Name)
4012       .Cases("arm8", "arm810", "4")
4013       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
4014       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4015       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4016       .Case("ep9312", "4T")
4017       .Cases("arm10tdmi", "arm1020t", "5T")
4018       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4019       .Case("arm926ej-s", "5TEJ")
4020       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4021       .Cases("xscale", "iwmmxt", "5TE")
4022       .Case("arm1136j-s", "6J")
4023       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4024       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4025       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4026       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
4027       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "7A")
4028       .Cases("cortex-r4", "cortex-r5", "7R")
4029       .Case("swift", "7S")
4030       .Case("cyclone", "8A")
4031       .Case("cortex-m3", "7M")
4032       .Cases("cortex-m4", "cortex-m7", "7EM")
4033       .Case("cortex-m0", "6M")
4034       .Cases("cortex-a53", "cortex-a57", "8A")
4035       .Default(nullptr);
4036   }
4037   static const char *getCPUProfile(StringRef Name) {
4038     return llvm::StringSwitch<const char*>(Name)
4039       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4040       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", "A")
4041       .Cases("cortex-a53", "cortex-a57", "A")
4042       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4043       .Cases("cortex-r4", "cortex-r5", "R")
4044       .Default("");
4045   }
4046   bool setCPU(const std::string &Name) override {
4047     if (!getCPUDefineSuffix(Name))
4048       return false;
4049 
4050     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4051     StringRef Profile = getCPUProfile(Name);
4052     if (Profile == "M" && MaxAtomicInlineWidth) {
4053       MaxAtomicPromoteWidth = 32;
4054       MaxAtomicInlineWidth = 32;
4055     }
4056 
4057     CPU = Name;
4058     return true;
4059   }
4060   bool setFPMath(StringRef Name) override;
4061   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4062                      unsigned CPUArchVer) const {
4063     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4064            (CPUArch.find('M') != StringRef::npos);
4065   }
4066   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4067                       unsigned CPUArchVer) const {
4068     // We check both CPUArchVer and ArchName because when only triple is
4069     // specified, the default CPU is arm1136j-s.
4070     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4071            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4072   }
4073   void getTargetDefines(const LangOptions &Opts,
4074                         MacroBuilder &Builder) const override {
4075     // Target identification.
4076     Builder.defineMacro("__arm");
4077     Builder.defineMacro("__arm__");
4078 
4079     // Target properties.
4080     Builder.defineMacro("__REGISTER_PREFIX__", "");
4081 
4082     StringRef CPUArch = getCPUDefineSuffix(CPU);
4083     unsigned int CPUArchVer;
4084     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4085       llvm_unreachable("Invalid char for architecture version number");
4086     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4087 
4088     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4089     StringRef CPUProfile = getCPUProfile(CPU);
4090     StringRef ArchName = getTriple().getArchName();
4091 
4092     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4093     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4094     if (CPUArch[0] >= '8') {
4095       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4096       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4097     }
4098 
4099     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4100     // is not defined for the M-profile.
4101     // NOTE that the deffault profile is assumed to be 'A'
4102     if (CPUProfile.empty() || CPUProfile != "M")
4103       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4104 
4105     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4106     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4107     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4108     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4109       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4110     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4111       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4112 
4113     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4114     // instruction set such as ARM or Thumb.
4115     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4116 
4117     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4118 
4119     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4120     if (!CPUProfile.empty())
4121       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4122 
4123     // ACLE 6.5.1 Hardware Floating Point
4124     if (HW_FP)
4125       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4126 
4127     // ACLE predefines.
4128     Builder.defineMacro("__ARM_ACLE", "200");
4129 
4130     // Subtarget options.
4131 
4132     // FIXME: It's more complicated than this and we don't really support
4133     // interworking.
4134     // Windows on ARM does not "support" interworking
4135     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4136       Builder.defineMacro("__THUMB_INTERWORK__");
4137 
4138     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4139       // Embedded targets on Darwin follow AAPCS, but not EABI.
4140       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4141       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4142         Builder.defineMacro("__ARM_EABI__");
4143       Builder.defineMacro("__ARM_PCS", "1");
4144 
4145       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4146         Builder.defineMacro("__ARM_PCS_VFP", "1");
4147     }
4148 
4149     if (SoftFloat)
4150       Builder.defineMacro("__SOFTFP__");
4151 
4152     if (CPU == "xscale")
4153       Builder.defineMacro("__XSCALE__");
4154 
4155     if (IsThumb) {
4156       Builder.defineMacro("__THUMBEL__");
4157       Builder.defineMacro("__thumb__");
4158       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4159         Builder.defineMacro("__thumb2__");
4160     }
4161     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4162       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4163 
4164     // Note, this is always on in gcc, even though it doesn't make sense.
4165     Builder.defineMacro("__APCS_32__");
4166 
4167     if (FPUModeIsVFP((FPUMode) FPU)) {
4168       Builder.defineMacro("__VFP_FP__");
4169       if (FPU & VFP2FPU)
4170         Builder.defineMacro("__ARM_VFPV2__");
4171       if (FPU & VFP3FPU)
4172         Builder.defineMacro("__ARM_VFPV3__");
4173       if (FPU & VFP4FPU)
4174         Builder.defineMacro("__ARM_VFPV4__");
4175     }
4176 
4177     // This only gets set when Neon instructions are actually available, unlike
4178     // the VFP define, hence the soft float and arch check. This is subtly
4179     // different from gcc, we follow the intent which was that it should be set
4180     // when Neon instructions are actually available.
4181     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4182       Builder.defineMacro("__ARM_NEON");
4183       Builder.defineMacro("__ARM_NEON__");
4184     }
4185 
4186     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4187                         Opts.ShortWChar ? "2" : "4");
4188 
4189     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4190                         Opts.ShortEnums ? "1" : "4");
4191 
4192     if (CRC)
4193       Builder.defineMacro("__ARM_FEATURE_CRC32");
4194 
4195     if (Crypto)
4196       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4197 
4198     if (CPUArchVer >= 6 && CPUArch != "6M") {
4199       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4200       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4201       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4202       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4203     }
4204   }
4205   void getTargetBuiltins(const Builtin::Info *&Records,
4206                          unsigned &NumRecords) const override {
4207     Records = BuiltinInfo;
4208     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4209   }
4210   bool isCLZForZeroUndef() const override { return false; }
4211   BuiltinVaListKind getBuiltinVaListKind() const override {
4212     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4213   }
4214   void getGCCRegNames(const char * const *&Names,
4215                       unsigned &NumNames) const override;
4216   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4217                         unsigned &NumAliases) const override;
4218   bool validateAsmConstraint(const char *&Name,
4219                              TargetInfo::ConstraintInfo &Info) const override {
4220     switch (*Name) {
4221     default: break;
4222     case 'l': // r0-r7
4223     case 'h': // r8-r15
4224     case 'w': // VFP Floating point register single precision
4225     case 'P': // VFP Floating point register double precision
4226       Info.setAllowsRegister();
4227       return true;
4228     case 'Q': // A memory address that is a single base register.
4229       Info.setAllowsMemory();
4230       return true;
4231     case 'U': // a memory reference...
4232       switch (Name[1]) {
4233       case 'q': // ...ARMV4 ldrsb
4234       case 'v': // ...VFP load/store (reg+constant offset)
4235       case 'y': // ...iWMMXt load/store
4236       case 't': // address valid for load/store opaque types wider
4237                 // than 128-bits
4238       case 'n': // valid address for Neon doubleword vector load/store
4239       case 'm': // valid address for Neon element and structure load/store
4240       case 's': // valid address for non-offset loads/stores of quad-word
4241                 // values in four ARM registers
4242         Info.setAllowsMemory();
4243         Name++;
4244         return true;
4245       }
4246     }
4247     return false;
4248   }
4249   std::string convertConstraint(const char *&Constraint) const override {
4250     std::string R;
4251     switch (*Constraint) {
4252     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4253       R = std::string("^") + std::string(Constraint, 2);
4254       Constraint++;
4255       break;
4256     case 'p': // 'p' should be translated to 'r' by default.
4257       R = std::string("r");
4258       break;
4259     default:
4260       return std::string(1, *Constraint);
4261     }
4262     return R;
4263   }
4264   bool
4265   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4266                              std::string &SuggestedModifier) const override {
4267     bool isOutput = (Constraint[0] == '=');
4268     bool isInOut = (Constraint[0] == '+');
4269 
4270     // Strip off constraint modifiers.
4271     while (Constraint[0] == '=' ||
4272            Constraint[0] == '+' ||
4273            Constraint[0] == '&')
4274       Constraint = Constraint.substr(1);
4275 
4276     switch (Constraint[0]) {
4277     default: break;
4278     case 'r': {
4279       switch (Modifier) {
4280       default:
4281         return (isInOut || isOutput || Size <= 64);
4282       case 'q':
4283         // A register of size 32 cannot fit a vector type.
4284         return false;
4285       }
4286     }
4287     }
4288 
4289     return true;
4290   }
4291   const char *getClobbers() const override {
4292     // FIXME: Is this really right?
4293     return "";
4294   }
4295 
4296   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4297     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4298   }
4299 
4300   int getEHDataRegisterNumber(unsigned RegNo) const override {
4301     if (RegNo == 0) return 0;
4302     if (RegNo == 1) return 1;
4303     return -1;
4304   }
4305 };
4306 
4307 bool ARMTargetInfo::setFPMath(StringRef Name) {
4308   if (Name == "neon") {
4309     FPMath = FP_Neon;
4310     return true;
4311   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4312              Name == "vfp4") {
4313     FPMath = FP_VFP;
4314     return true;
4315   }
4316   return false;
4317 }
4318 
4319 const char * const ARMTargetInfo::GCCRegNames[] = {
4320   // Integer registers
4321   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4322   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4323 
4324   // Float registers
4325   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4326   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4327   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4328   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4329 
4330   // Double registers
4331   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4332   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4333   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4334   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4335 
4336   // Quad registers
4337   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4338   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4339 };
4340 
4341 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4342                                    unsigned &NumNames) const {
4343   Names = GCCRegNames;
4344   NumNames = llvm::array_lengthof(GCCRegNames);
4345 }
4346 
4347 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4348   { { "a1" }, "r0" },
4349   { { "a2" }, "r1" },
4350   { { "a3" }, "r2" },
4351   { { "a4" }, "r3" },
4352   { { "v1" }, "r4" },
4353   { { "v2" }, "r5" },
4354   { { "v3" }, "r6" },
4355   { { "v4" }, "r7" },
4356   { { "v5" }, "r8" },
4357   { { "v6", "rfp" }, "r9" },
4358   { { "sl" }, "r10" },
4359   { { "fp" }, "r11" },
4360   { { "ip" }, "r12" },
4361   { { "r13" }, "sp" },
4362   { { "r14" }, "lr" },
4363   { { "r15" }, "pc" },
4364   // The S, D and Q registers overlap, but aren't really aliases; we
4365   // don't want to substitute one of these for a different-sized one.
4366 };
4367 
4368 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4369                                        unsigned &NumAliases) const {
4370   Aliases = GCCRegAliases;
4371   NumAliases = llvm::array_lengthof(GCCRegAliases);
4372 }
4373 
4374 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4375 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4376 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4377                                               ALL_LANGUAGES },
4378 #include "clang/Basic/BuiltinsNEON.def"
4379 
4380 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4381 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4382 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4383                                               ALL_LANGUAGES },
4384 #include "clang/Basic/BuiltinsARM.def"
4385 };
4386 
4387 class ARMleTargetInfo : public ARMTargetInfo {
4388 public:
4389   ARMleTargetInfo(const llvm::Triple &Triple)
4390     : ARMTargetInfo(Triple, false) { }
4391   virtual void getTargetDefines(const LangOptions &Opts,
4392                                 MacroBuilder &Builder) const {
4393     Builder.defineMacro("__ARMEL__");
4394     ARMTargetInfo::getTargetDefines(Opts, Builder);
4395   }
4396 };
4397 
4398 class ARMbeTargetInfo : public ARMTargetInfo {
4399 public:
4400   ARMbeTargetInfo(const llvm::Triple &Triple)
4401     : ARMTargetInfo(Triple, true) { }
4402   virtual void getTargetDefines(const LangOptions &Opts,
4403                                 MacroBuilder &Builder) const {
4404     Builder.defineMacro("__ARMEB__");
4405     Builder.defineMacro("__ARM_BIG_ENDIAN");
4406     ARMTargetInfo::getTargetDefines(Opts, Builder);
4407   }
4408 };
4409 } // end anonymous namespace.
4410 
4411 namespace {
4412 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4413   const llvm::Triple Triple;
4414 public:
4415   WindowsARMTargetInfo(const llvm::Triple &Triple)
4416     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4417     TLSSupported = false;
4418     WCharType = UnsignedShort;
4419     SizeType = UnsignedInt;
4420     UserLabelPrefix = "";
4421   }
4422   void getVisualStudioDefines(const LangOptions &Opts,
4423                               MacroBuilder &Builder) const {
4424     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4425 
4426     // FIXME: this is invalid for WindowsCE
4427     Builder.defineMacro("_M_ARM_NT", "1");
4428     Builder.defineMacro("_M_ARMT", "_M_ARM");
4429     Builder.defineMacro("_M_THUMB", "_M_ARM");
4430 
4431     assert((Triple.getArch() == llvm::Triple::arm ||
4432             Triple.getArch() == llvm::Triple::thumb) &&
4433            "invalid architecture for Windows ARM target info");
4434     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4435     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4436 
4437     // TODO map the complete set of values
4438     // 31: VFPv3 40: VFPv4
4439     Builder.defineMacro("_M_ARM_FP", "31");
4440   }
4441   BuiltinVaListKind getBuiltinVaListKind() const override {
4442     return TargetInfo::CharPtrBuiltinVaList;
4443   }
4444 };
4445 
4446 // Windows ARM + Itanium C++ ABI Target
4447 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4448 public:
4449   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4450     : WindowsARMTargetInfo(Triple) {
4451     TheCXXABI.set(TargetCXXABI::GenericARM);
4452   }
4453 
4454   void getTargetDefines(const LangOptions &Opts,
4455                         MacroBuilder &Builder) const override {
4456     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4457 
4458     if (Opts.MSVCCompat)
4459       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4460   }
4461 };
4462 
4463 // Windows ARM, MS (C++) ABI
4464 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4465 public:
4466   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4467     : WindowsARMTargetInfo(Triple) {
4468     TheCXXABI.set(TargetCXXABI::Microsoft);
4469   }
4470 
4471   void getTargetDefines(const LangOptions &Opts,
4472                         MacroBuilder &Builder) const override {
4473     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4474     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4475   }
4476 };
4477 }
4478 
4479 
4480 namespace {
4481 class DarwinARMTargetInfo :
4482   public DarwinTargetInfo<ARMleTargetInfo> {
4483 protected:
4484   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4485                     MacroBuilder &Builder) const override {
4486     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4487   }
4488 
4489 public:
4490   DarwinARMTargetInfo(const llvm::Triple &Triple)
4491       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4492     HasAlignMac68kSupport = true;
4493     // iOS always has 64-bit atomic instructions.
4494     // FIXME: This should be based off of the target features in ARMleTargetInfo.
4495     MaxAtomicInlineWidth = 64;
4496 
4497     // Darwin on iOS uses a variant of the ARM C++ ABI.
4498     TheCXXABI.set(TargetCXXABI::iOS);
4499   }
4500 };
4501 } // end anonymous namespace.
4502 
4503 
4504 namespace {
4505 class AArch64TargetInfo : public TargetInfo {
4506   virtual void setDescriptionString() = 0;
4507   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4508   static const char *const GCCRegNames[];
4509 
4510   enum FPUModeEnum {
4511     FPUMode,
4512     NeonMode
4513   };
4514 
4515   unsigned FPU;
4516   unsigned CRC;
4517   unsigned Crypto;
4518 
4519   static const Builtin::Info BuiltinInfo[];
4520 
4521   std::string ABI;
4522 
4523 public:
4524   AArch64TargetInfo(const llvm::Triple &Triple)
4525       : TargetInfo(Triple), ABI("aapcs") {
4526 
4527     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4528       WCharType = SignedInt;
4529 
4530       // NetBSD apparently prefers consistency across ARM targets to consistency
4531       // across 64-bit targets.
4532       Int64Type = SignedLongLong;
4533       IntMaxType = SignedLongLong;
4534     } else {
4535       WCharType = UnsignedInt;
4536       Int64Type = SignedLong;
4537       IntMaxType = SignedLong;
4538     }
4539 
4540     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4541     MaxVectorAlign = 128;
4542     RegParmMax = 8;
4543     MaxAtomicInlineWidth = 128;
4544     MaxAtomicPromoteWidth = 128;
4545 
4546     LongDoubleWidth = LongDoubleAlign = 128;
4547     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4548 
4549     // {} in inline assembly are neon specifiers, not assembly variant
4550     // specifiers.
4551     NoAsmVariants = true;
4552 
4553     // AArch64 targets default to using the ARM C++ ABI.
4554     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4555   }
4556 
4557   StringRef getABI() const override { return ABI; }
4558   virtual bool setABI(const std::string &Name) override {
4559     if (Name != "aapcs" && Name != "darwinpcs")
4560       return false;
4561 
4562     ABI = Name;
4563     return true;
4564   }
4565 
4566   virtual bool setCPU(const std::string &Name) override {
4567     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4568                         .Case("generic", true)
4569                         .Cases("cortex-a53", "cortex-a57", true)
4570                         .Case("cyclone", true)
4571                         .Default(false);
4572     return CPUKnown;
4573   }
4574 
4575   virtual void getTargetDefines(const LangOptions &Opts,
4576                                 MacroBuilder &Builder) const  override {
4577     // Target identification.
4578     Builder.defineMacro("__aarch64__");
4579 
4580     // Target properties.
4581     Builder.defineMacro("_LP64");
4582     Builder.defineMacro("__LP64__");
4583 
4584     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4585     Builder.defineMacro("__ARM_ACLE", "200");
4586     Builder.defineMacro("__ARM_ARCH", "8");
4587     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4588 
4589     Builder.defineMacro("__ARM_64BIT_STATE");
4590     Builder.defineMacro("__ARM_PCS_AAPCS64");
4591     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4592 
4593     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4594     Builder.defineMacro("__ARM_FEATURE_CLZ");
4595     Builder.defineMacro("__ARM_FEATURE_FMA");
4596     Builder.defineMacro("__ARM_FEATURE_DIV");
4597     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4598     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4599     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4600     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4601 
4602     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4603 
4604     // 0xe implies support for half, single and double precision operations.
4605     Builder.defineMacro("__ARM_FP", "0xe");
4606 
4607     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4608     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4609     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4610 
4611     if (Opts.FastMath || Opts.FiniteMathOnly)
4612       Builder.defineMacro("__ARM_FP_FAST");
4613 
4614     if (Opts.C99 && !Opts.Freestanding)
4615       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4616 
4617     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4618 
4619     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4620                         Opts.ShortEnums ? "1" : "4");
4621 
4622     if (FPU == NeonMode) {
4623       Builder.defineMacro("__ARM_NEON");
4624       // 64-bit NEON supports half, single and double precision operations.
4625       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4626     }
4627 
4628     if (CRC)
4629       Builder.defineMacro("__ARM_FEATURE_CRC32");
4630 
4631     if (Crypto)
4632       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4633   }
4634 
4635   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4636                                  unsigned &NumRecords) const override {
4637     Records = BuiltinInfo;
4638     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4639   }
4640 
4641   virtual bool hasFeature(StringRef Feature) const override {
4642     return Feature == "aarch64" ||
4643       Feature == "arm64" ||
4644       (Feature == "neon" && FPU == NeonMode);
4645   }
4646 
4647   bool handleTargetFeatures(std::vector<std::string> &Features,
4648                             DiagnosticsEngine &Diags) override {
4649     FPU = FPUMode;
4650     CRC = 0;
4651     Crypto = 0;
4652     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4653       if (Features[i] == "+neon")
4654         FPU = NeonMode;
4655       if (Features[i] == "+crc")
4656         CRC = 1;
4657       if (Features[i] == "+crypto")
4658         Crypto = 1;
4659     }
4660 
4661     setDescriptionString();
4662 
4663     return true;
4664   }
4665 
4666   virtual bool isCLZForZeroUndef() const override { return false; }
4667 
4668   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4669     return TargetInfo::AArch64ABIBuiltinVaList;
4670   }
4671 
4672   virtual void getGCCRegNames(const char *const *&Names,
4673                               unsigned &NumNames) const override;
4674   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4675                                 unsigned &NumAliases) const override;
4676 
4677   virtual bool validateAsmConstraint(const char *&Name,
4678                                      TargetInfo::ConstraintInfo &Info) const override {
4679     switch (*Name) {
4680     default:
4681       return false;
4682     case 'w': // Floating point and SIMD registers (V0-V31)
4683       Info.setAllowsRegister();
4684       return true;
4685     case 'I': // Constant that can be used with an ADD instruction
4686     case 'J': // Constant that can be used with a SUB instruction
4687     case 'K': // Constant that can be used with a 32-bit logical instruction
4688     case 'L': // Constant that can be used with a 64-bit logical instruction
4689     case 'M': // Constant that can be used as a 32-bit MOV immediate
4690     case 'N': // Constant that can be used as a 64-bit MOV immediate
4691     case 'Y': // Floating point constant zero
4692     case 'Z': // Integer constant zero
4693       return true;
4694     case 'Q': // A memory reference with base register and no offset
4695       Info.setAllowsMemory();
4696       return true;
4697     case 'S': // A symbolic address
4698       Info.setAllowsRegister();
4699       return true;
4700     case 'U':
4701       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
4702       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4703       // Usa: An absolute symbolic address
4704       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4705       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
4706     case 'z': // Zero register, wzr or xzr
4707       Info.setAllowsRegister();
4708       return true;
4709     case 'x': // Floating point and SIMD registers (V0-V15)
4710       Info.setAllowsRegister();
4711       return true;
4712     }
4713     return false;
4714   }
4715 
4716   bool
4717   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4718                              std::string &SuggestedModifier) const override {
4719     // Strip off constraint modifiers.
4720     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4721       Constraint = Constraint.substr(1);
4722 
4723     switch (Constraint[0]) {
4724     default:
4725       return true;
4726     case 'z':
4727     case 'r': {
4728       switch (Modifier) {
4729       case 'x':
4730       case 'w':
4731         // For now assume that the person knows what they're
4732         // doing with the modifier.
4733         return true;
4734       default:
4735         // By default an 'r' constraint will be in the 'x'
4736         // registers.
4737         if (Size == 64)
4738           return true;
4739 
4740         SuggestedModifier = "w";
4741         return false;
4742       }
4743     }
4744     }
4745   }
4746 
4747   virtual const char *getClobbers() const override { return ""; }
4748 
4749   int getEHDataRegisterNumber(unsigned RegNo) const override {
4750     if (RegNo == 0)
4751       return 0;
4752     if (RegNo == 1)
4753       return 1;
4754     return -1;
4755   }
4756 };
4757 
4758 const char *const AArch64TargetInfo::GCCRegNames[] = {
4759   // 32-bit Integer registers
4760   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4761   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4762   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4763 
4764   // 64-bit Integer registers
4765   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4766   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4767   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4768 
4769   // 32-bit floating point regsisters
4770   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4771   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4772   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4773 
4774   // 64-bit floating point regsisters
4775   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4776   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4777   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4778 
4779   // Vector registers
4780   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4781   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4782   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4783 };
4784 
4785 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4786                                      unsigned &NumNames) const {
4787   Names = GCCRegNames;
4788   NumNames = llvm::array_lengthof(GCCRegNames);
4789 }
4790 
4791 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4792   { { "w31" }, "wsp" },
4793   { { "x29" }, "fp" },
4794   { { "x30" }, "lr" },
4795   { { "x31" }, "sp" },
4796   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4797   // don't want to substitute one of these for a different-sized one.
4798 };
4799 
4800 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4801                                        unsigned &NumAliases) const {
4802   Aliases = GCCRegAliases;
4803   NumAliases = llvm::array_lengthof(GCCRegAliases);
4804 }
4805 
4806 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4807 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4808   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4809 #include "clang/Basic/BuiltinsNEON.def"
4810 
4811 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4812   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4813 #include "clang/Basic/BuiltinsAArch64.def"
4814 };
4815 
4816 class AArch64leTargetInfo : public AArch64TargetInfo {
4817   void setDescriptionString() override {
4818     if (getTriple().isOSBinFormatMachO())
4819       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4820     else
4821       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4822   }
4823 
4824 public:
4825   AArch64leTargetInfo(const llvm::Triple &Triple)
4826     : AArch64TargetInfo(Triple) {
4827     BigEndian = false;
4828     }
4829   void getTargetDefines(const LangOptions &Opts,
4830                         MacroBuilder &Builder) const override {
4831     Builder.defineMacro("__AARCH64EL__");
4832     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4833   }
4834 };
4835 
4836 class AArch64beTargetInfo : public AArch64TargetInfo {
4837   void setDescriptionString() override {
4838     assert(!getTriple().isOSBinFormatMachO());
4839     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4840   }
4841 
4842 public:
4843   AArch64beTargetInfo(const llvm::Triple &Triple)
4844     : AArch64TargetInfo(Triple) { }
4845   void getTargetDefines(const LangOptions &Opts,
4846                         MacroBuilder &Builder) const override {
4847     Builder.defineMacro("__AARCH64EB__");
4848     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4849     Builder.defineMacro("__ARM_BIG_ENDIAN");
4850     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4851   }
4852 };
4853 } // end anonymous namespace.
4854 
4855 namespace {
4856 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4857 protected:
4858   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4859                     MacroBuilder &Builder) const override {
4860     Builder.defineMacro("__AARCH64_SIMD__");
4861     Builder.defineMacro("__ARM64_ARCH_8__");
4862     Builder.defineMacro("__ARM_NEON__");
4863     Builder.defineMacro("__LITTLE_ENDIAN__");
4864     Builder.defineMacro("__REGISTER_PREFIX__", "");
4865     Builder.defineMacro("__arm64", "1");
4866     Builder.defineMacro("__arm64__", "1");
4867 
4868     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4869   }
4870 
4871 public:
4872   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4873       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4874     Int64Type = SignedLongLong;
4875     WCharType = SignedInt;
4876     UseSignedCharForObjCBool = false;
4877 
4878     LongDoubleWidth = LongDoubleAlign = 64;
4879     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4880 
4881     TheCXXABI.set(TargetCXXABI::iOS64);
4882   }
4883 
4884   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4885     return TargetInfo::CharPtrBuiltinVaList;
4886   }
4887 };
4888 } // end anonymous namespace
4889 
4890 namespace {
4891 // Hexagon abstract base class
4892 class HexagonTargetInfo : public TargetInfo {
4893   static const Builtin::Info BuiltinInfo[];
4894   static const char * const GCCRegNames[];
4895   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4896   std::string CPU;
4897 public:
4898   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4899     BigEndian = false;
4900     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4901 
4902     // {} in inline assembly are packet specifiers, not assembly variant
4903     // specifiers.
4904     NoAsmVariants = true;
4905   }
4906 
4907   void getTargetBuiltins(const Builtin::Info *&Records,
4908                          unsigned &NumRecords) const override {
4909     Records = BuiltinInfo;
4910     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4911   }
4912 
4913   bool validateAsmConstraint(const char *&Name,
4914                              TargetInfo::ConstraintInfo &Info) const override {
4915     return true;
4916   }
4917 
4918   void getTargetDefines(const LangOptions &Opts,
4919                         MacroBuilder &Builder) const override;
4920 
4921   bool hasFeature(StringRef Feature) const override {
4922     return Feature == "hexagon";
4923   }
4924 
4925   BuiltinVaListKind getBuiltinVaListKind() const override {
4926     return TargetInfo::CharPtrBuiltinVaList;
4927   }
4928   void getGCCRegNames(const char * const *&Names,
4929                       unsigned &NumNames) const override;
4930   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4931                         unsigned &NumAliases) const override;
4932   const char *getClobbers() const override {
4933     return "";
4934   }
4935 
4936   static const char *getHexagonCPUSuffix(StringRef Name) {
4937     return llvm::StringSwitch<const char*>(Name)
4938       .Case("hexagonv4", "4")
4939       .Case("hexagonv5", "5")
4940       .Default(nullptr);
4941   }
4942 
4943   bool setCPU(const std::string &Name) override {
4944     if (!getHexagonCPUSuffix(Name))
4945       return false;
4946 
4947     CPU = Name;
4948     return true;
4949   }
4950 };
4951 
4952 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4953                                 MacroBuilder &Builder) const {
4954   Builder.defineMacro("qdsp6");
4955   Builder.defineMacro("__qdsp6", "1");
4956   Builder.defineMacro("__qdsp6__", "1");
4957 
4958   Builder.defineMacro("hexagon");
4959   Builder.defineMacro("__hexagon", "1");
4960   Builder.defineMacro("__hexagon__", "1");
4961 
4962   if(CPU == "hexagonv1") {
4963     Builder.defineMacro("__HEXAGON_V1__");
4964     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4965     if(Opts.HexagonQdsp6Compat) {
4966       Builder.defineMacro("__QDSP6_V1__");
4967       Builder.defineMacro("__QDSP6_ARCH__", "1");
4968     }
4969   }
4970   else if(CPU == "hexagonv2") {
4971     Builder.defineMacro("__HEXAGON_V2__");
4972     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4973     if(Opts.HexagonQdsp6Compat) {
4974       Builder.defineMacro("__QDSP6_V2__");
4975       Builder.defineMacro("__QDSP6_ARCH__", "2");
4976     }
4977   }
4978   else if(CPU == "hexagonv3") {
4979     Builder.defineMacro("__HEXAGON_V3__");
4980     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4981     if(Opts.HexagonQdsp6Compat) {
4982       Builder.defineMacro("__QDSP6_V3__");
4983       Builder.defineMacro("__QDSP6_ARCH__", "3");
4984     }
4985   }
4986   else if(CPU == "hexagonv4") {
4987     Builder.defineMacro("__HEXAGON_V4__");
4988     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4989     if(Opts.HexagonQdsp6Compat) {
4990       Builder.defineMacro("__QDSP6_V4__");
4991       Builder.defineMacro("__QDSP6_ARCH__", "4");
4992     }
4993   }
4994   else if(CPU == "hexagonv5") {
4995     Builder.defineMacro("__HEXAGON_V5__");
4996     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4997     if(Opts.HexagonQdsp6Compat) {
4998       Builder.defineMacro("__QDSP6_V5__");
4999       Builder.defineMacro("__QDSP6_ARCH__", "5");
5000     }
5001   }
5002 }
5003 
5004 const char * const HexagonTargetInfo::GCCRegNames[] = {
5005   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5006   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5007   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5008   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
5009   "p0", "p1", "p2", "p3",
5010   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
5011 };
5012 
5013 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5014                                    unsigned &NumNames) const {
5015   Names = GCCRegNames;
5016   NumNames = llvm::array_lengthof(GCCRegNames);
5017 }
5018 
5019 
5020 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5021   { { "sp" }, "r29" },
5022   { { "fp" }, "r30" },
5023   { { "lr" }, "r31" },
5024  };
5025 
5026 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5027                                      unsigned &NumAliases) const {
5028   Aliases = GCCRegAliases;
5029   NumAliases = llvm::array_lengthof(GCCRegAliases);
5030 }
5031 
5032 
5033 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5034 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5035 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5036                                               ALL_LANGUAGES },
5037 #include "clang/Basic/BuiltinsHexagon.def"
5038 };
5039 }
5040 
5041 
5042 namespace {
5043 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5044 class SparcTargetInfo : public TargetInfo {
5045   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5046   static const char * const GCCRegNames[];
5047   bool SoftFloat;
5048 public:
5049   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5050 
5051   bool handleTargetFeatures(std::vector<std::string> &Features,
5052                             DiagnosticsEngine &Diags) override {
5053     SoftFloat = false;
5054     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5055       if (Features[i] == "+soft-float")
5056         SoftFloat = true;
5057     return true;
5058   }
5059   void getTargetDefines(const LangOptions &Opts,
5060                         MacroBuilder &Builder) const override {
5061     DefineStd(Builder, "sparc", Opts);
5062     Builder.defineMacro("__REGISTER_PREFIX__", "");
5063 
5064     if (SoftFloat)
5065       Builder.defineMacro("SOFT_FLOAT", "1");
5066   }
5067 
5068   bool hasFeature(StringRef Feature) const override {
5069     return llvm::StringSwitch<bool>(Feature)
5070              .Case("softfloat", SoftFloat)
5071              .Case("sparc", true)
5072              .Default(false);
5073   }
5074 
5075   void getTargetBuiltins(const Builtin::Info *&Records,
5076                          unsigned &NumRecords) const override {
5077     // FIXME: Implement!
5078   }
5079   BuiltinVaListKind getBuiltinVaListKind() const override {
5080     return TargetInfo::VoidPtrBuiltinVaList;
5081   }
5082   void getGCCRegNames(const char * const *&Names,
5083                       unsigned &NumNames) const override;
5084   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5085                         unsigned &NumAliases) const override;
5086   bool validateAsmConstraint(const char *&Name,
5087                              TargetInfo::ConstraintInfo &info) const override {
5088     // FIXME: Implement!
5089     return false;
5090   }
5091   const char *getClobbers() const override {
5092     // FIXME: Implement!
5093     return "";
5094   }
5095 };
5096 
5097 const char * const SparcTargetInfo::GCCRegNames[] = {
5098   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5099   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5100   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5101   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5102 };
5103 
5104 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5105                                      unsigned &NumNames) const {
5106   Names = GCCRegNames;
5107   NumNames = llvm::array_lengthof(GCCRegNames);
5108 }
5109 
5110 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5111   { { "g0" }, "r0" },
5112   { { "g1" }, "r1" },
5113   { { "g2" }, "r2" },
5114   { { "g3" }, "r3" },
5115   { { "g4" }, "r4" },
5116   { { "g5" }, "r5" },
5117   { { "g6" }, "r6" },
5118   { { "g7" }, "r7" },
5119   { { "o0" }, "r8" },
5120   { { "o1" }, "r9" },
5121   { { "o2" }, "r10" },
5122   { { "o3" }, "r11" },
5123   { { "o4" }, "r12" },
5124   { { "o5" }, "r13" },
5125   { { "o6", "sp" }, "r14" },
5126   { { "o7" }, "r15" },
5127   { { "l0" }, "r16" },
5128   { { "l1" }, "r17" },
5129   { { "l2" }, "r18" },
5130   { { "l3" }, "r19" },
5131   { { "l4" }, "r20" },
5132   { { "l5" }, "r21" },
5133   { { "l6" }, "r22" },
5134   { { "l7" }, "r23" },
5135   { { "i0" }, "r24" },
5136   { { "i1" }, "r25" },
5137   { { "i2" }, "r26" },
5138   { { "i3" }, "r27" },
5139   { { "i4" }, "r28" },
5140   { { "i5" }, "r29" },
5141   { { "i6", "fp" }, "r30" },
5142   { { "i7" }, "r31" },
5143 };
5144 
5145 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5146                                        unsigned &NumAliases) const {
5147   Aliases = GCCRegAliases;
5148   NumAliases = llvm::array_lengthof(GCCRegAliases);
5149 }
5150 
5151 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5152 class SparcV8TargetInfo : public SparcTargetInfo {
5153 public:
5154   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5155     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5156   }
5157 
5158   void getTargetDefines(const LangOptions &Opts,
5159                         MacroBuilder &Builder) const override {
5160     SparcTargetInfo::getTargetDefines(Opts, Builder);
5161     Builder.defineMacro("__sparcv8");
5162   }
5163 };
5164 
5165 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5166 class SparcV9TargetInfo : public SparcTargetInfo {
5167 public:
5168   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5169     // FIXME: Support Sparc quad-precision long double?
5170     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5171     // This is an LP64 platform.
5172     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5173 
5174     // OpenBSD uses long long for int64_t and intmax_t.
5175     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5176       IntMaxType = SignedLongLong;
5177     else
5178       IntMaxType = SignedLong;
5179     Int64Type = IntMaxType;
5180 
5181     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5182     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5183     LongDoubleWidth = 128;
5184     LongDoubleAlign = 128;
5185     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5186     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5187   }
5188 
5189   void getTargetDefines(const LangOptions &Opts,
5190                         MacroBuilder &Builder) const override {
5191     SparcTargetInfo::getTargetDefines(Opts, Builder);
5192     Builder.defineMacro("__sparcv9");
5193     Builder.defineMacro("__arch64__");
5194     // Solaris doesn't need these variants, but the BSDs do.
5195     if (getTriple().getOS() != llvm::Triple::Solaris) {
5196       Builder.defineMacro("__sparc64__");
5197       Builder.defineMacro("__sparc_v9__");
5198       Builder.defineMacro("__sparcv9__");
5199     }
5200   }
5201 
5202   bool setCPU(const std::string &Name) override {
5203     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5204       .Case("v9", true)
5205       .Case("ultrasparc", true)
5206       .Case("ultrasparc3", true)
5207       .Case("niagara", true)
5208       .Case("niagara2", true)
5209       .Case("niagara3", true)
5210       .Case("niagara4", true)
5211       .Default(false);
5212 
5213     // No need to store the CPU yet.  There aren't any CPU-specific
5214     // macros to define.
5215     return CPUKnown;
5216   }
5217 };
5218 
5219 } // end anonymous namespace.
5220 
5221 namespace {
5222 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5223 public:
5224   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5225       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5226     SizeType = UnsignedInt;
5227     PtrDiffType = SignedInt;
5228   }
5229 };
5230 } // end anonymous namespace.
5231 
5232 namespace {
5233 class SystemZTargetInfo : public TargetInfo {
5234   static const char *const GCCRegNames[];
5235 
5236 public:
5237   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5238     TLSSupported = true;
5239     IntWidth = IntAlign = 32;
5240     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5241     PointerWidth = PointerAlign = 64;
5242     LongDoubleWidth = 128;
5243     LongDoubleAlign = 64;
5244     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5245     MinGlobalAlign = 16;
5246     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5247     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5248   }
5249   void getTargetDefines(const LangOptions &Opts,
5250                         MacroBuilder &Builder) const override {
5251     Builder.defineMacro("__s390__");
5252     Builder.defineMacro("__s390x__");
5253     Builder.defineMacro("__zarch__");
5254     Builder.defineMacro("__LONG_DOUBLE_128__");
5255   }
5256   void getTargetBuiltins(const Builtin::Info *&Records,
5257                          unsigned &NumRecords) const override {
5258     // FIXME: Implement.
5259     Records = nullptr;
5260     NumRecords = 0;
5261   }
5262 
5263   void getGCCRegNames(const char *const *&Names,
5264                       unsigned &NumNames) const override;
5265   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5266                         unsigned &NumAliases) const override {
5267     // No aliases.
5268     Aliases = nullptr;
5269     NumAliases = 0;
5270   }
5271   bool validateAsmConstraint(const char *&Name,
5272                              TargetInfo::ConstraintInfo &info) const override;
5273   const char *getClobbers() const override {
5274     // FIXME: Is this really right?
5275     return "";
5276   }
5277   BuiltinVaListKind getBuiltinVaListKind() const override {
5278     return TargetInfo::SystemZBuiltinVaList;
5279   }
5280   bool setCPU(const std::string &Name) override {
5281     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5282       .Case("z10", true)
5283       .Case("z196", true)
5284       .Case("zEC12", true)
5285       .Default(false);
5286 
5287     // No need to store the CPU yet.  There aren't any CPU-specific
5288     // macros to define.
5289     return CPUKnown;
5290   }
5291 };
5292 
5293 const char *const SystemZTargetInfo::GCCRegNames[] = {
5294   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5295   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5296   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5297   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5298 };
5299 
5300 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5301                                        unsigned &NumNames) const {
5302   Names = GCCRegNames;
5303   NumNames = llvm::array_lengthof(GCCRegNames);
5304 }
5305 
5306 bool SystemZTargetInfo::
5307 validateAsmConstraint(const char *&Name,
5308                       TargetInfo::ConstraintInfo &Info) const {
5309   switch (*Name) {
5310   default:
5311     return false;
5312 
5313   case 'a': // Address register
5314   case 'd': // Data register (equivalent to 'r')
5315   case 'f': // Floating-point register
5316     Info.setAllowsRegister();
5317     return true;
5318 
5319   case 'I': // Unsigned 8-bit constant
5320   case 'J': // Unsigned 12-bit constant
5321   case 'K': // Signed 16-bit constant
5322   case 'L': // Signed 20-bit displacement (on all targets we support)
5323   case 'M': // 0x7fffffff
5324     return true;
5325 
5326   case 'Q': // Memory with base and unsigned 12-bit displacement
5327   case 'R': // Likewise, plus an index
5328   case 'S': // Memory with base and signed 20-bit displacement
5329   case 'T': // Likewise, plus an index
5330     Info.setAllowsMemory();
5331     return true;
5332   }
5333 }
5334 }
5335 
5336 namespace {
5337   class MSP430TargetInfo : public TargetInfo {
5338     static const char * const GCCRegNames[];
5339   public:
5340     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5341       BigEndian = false;
5342       TLSSupported = false;
5343       IntWidth = 16; IntAlign = 16;
5344       LongWidth = 32; LongLongWidth = 64;
5345       LongAlign = LongLongAlign = 16;
5346       PointerWidth = 16; PointerAlign = 16;
5347       SuitableAlign = 16;
5348       SizeType = UnsignedInt;
5349       IntMaxType = SignedLongLong;
5350       IntPtrType = SignedInt;
5351       PtrDiffType = SignedInt;
5352       SigAtomicType = SignedLong;
5353       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5354     }
5355     void getTargetDefines(const LangOptions &Opts,
5356                           MacroBuilder &Builder) const override {
5357       Builder.defineMacro("MSP430");
5358       Builder.defineMacro("__MSP430__");
5359       // FIXME: defines for different 'flavours' of MCU
5360     }
5361     void getTargetBuiltins(const Builtin::Info *&Records,
5362                            unsigned &NumRecords) const override {
5363       // FIXME: Implement.
5364       Records = nullptr;
5365       NumRecords = 0;
5366     }
5367     bool hasFeature(StringRef Feature) const override {
5368       return Feature == "msp430";
5369     }
5370     void getGCCRegNames(const char * const *&Names,
5371                         unsigned &NumNames) const override;
5372     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5373                           unsigned &NumAliases) const override {
5374       // No aliases.
5375       Aliases = nullptr;
5376       NumAliases = 0;
5377     }
5378     bool validateAsmConstraint(const char *&Name,
5379                                TargetInfo::ConstraintInfo &info) const override {
5380       // No target constraints for now.
5381       return false;
5382     }
5383     const char *getClobbers() const override {
5384       // FIXME: Is this really right?
5385       return "";
5386     }
5387     BuiltinVaListKind getBuiltinVaListKind() const override {
5388       // FIXME: implement
5389       return TargetInfo::CharPtrBuiltinVaList;
5390    }
5391   };
5392 
5393   const char * const MSP430TargetInfo::GCCRegNames[] = {
5394     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5395     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5396   };
5397 
5398   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5399                                         unsigned &NumNames) const {
5400     Names = GCCRegNames;
5401     NumNames = llvm::array_lengthof(GCCRegNames);
5402   }
5403 }
5404 
5405 namespace {
5406 
5407   // LLVM and Clang cannot be used directly to output native binaries for
5408   // target, but is used to compile C code to llvm bitcode with correct
5409   // type and alignment information.
5410   //
5411   // TCE uses the llvm bitcode as input and uses it for generating customized
5412   // target processor and program binary. TCE co-design environment is
5413   // publicly available in http://tce.cs.tut.fi
5414 
5415   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5416       3, // opencl_global
5417       4, // opencl_local
5418       5, // opencl_constant
5419       0, // cuda_device
5420       0, // cuda_constant
5421       0  // cuda_shared
5422   };
5423 
5424   class TCETargetInfo : public TargetInfo{
5425   public:
5426     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5427       TLSSupported = false;
5428       IntWidth = 32;
5429       LongWidth = LongLongWidth = 32;
5430       PointerWidth = 32;
5431       IntAlign = 32;
5432       LongAlign = LongLongAlign = 32;
5433       PointerAlign = 32;
5434       SuitableAlign = 32;
5435       SizeType = UnsignedInt;
5436       IntMaxType = SignedLong;
5437       IntPtrType = SignedInt;
5438       PtrDiffType = SignedInt;
5439       FloatWidth = 32;
5440       FloatAlign = 32;
5441       DoubleWidth = 32;
5442       DoubleAlign = 32;
5443       LongDoubleWidth = 32;
5444       LongDoubleAlign = 32;
5445       FloatFormat = &llvm::APFloat::IEEEsingle;
5446       DoubleFormat = &llvm::APFloat::IEEEsingle;
5447       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5448       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5449                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5450       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5451       UseAddrSpaceMapMangling = true;
5452     }
5453 
5454     void getTargetDefines(const LangOptions &Opts,
5455                           MacroBuilder &Builder) const override {
5456       DefineStd(Builder, "tce", Opts);
5457       Builder.defineMacro("__TCE__");
5458       Builder.defineMacro("__TCE_V1__");
5459     }
5460     bool hasFeature(StringRef Feature) const override {
5461       return Feature == "tce";
5462     }
5463 
5464     void getTargetBuiltins(const Builtin::Info *&Records,
5465                            unsigned &NumRecords) const override {}
5466     const char *getClobbers() const override {
5467       return "";
5468     }
5469     BuiltinVaListKind getBuiltinVaListKind() const override {
5470       return TargetInfo::VoidPtrBuiltinVaList;
5471     }
5472     void getGCCRegNames(const char * const *&Names,
5473                         unsigned &NumNames) const override {}
5474     bool validateAsmConstraint(const char *&Name,
5475                                TargetInfo::ConstraintInfo &info) const override{
5476       return true;
5477     }
5478     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5479                           unsigned &NumAliases) const override {}
5480   };
5481 }
5482 
5483 namespace {
5484 class MipsTargetInfoBase : public TargetInfo {
5485   virtual void setDescriptionString() = 0;
5486 
5487   static const Builtin::Info BuiltinInfo[];
5488   std::string CPU;
5489   bool IsMips16;
5490   bool IsMicromips;
5491   bool IsNan2008;
5492   bool IsSingleFloat;
5493   enum MipsFloatABI {
5494     HardFloat, SoftFloat
5495   } FloatABI;
5496   enum DspRevEnum {
5497     NoDSP, DSP1, DSP2
5498   } DspRev;
5499   bool HasMSA;
5500 
5501 protected:
5502   bool HasFP64;
5503   std::string ABI;
5504 
5505 public:
5506   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5507                      const std::string &CPUStr)
5508       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5509         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5510         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5511 
5512   bool isNaN2008Default() const {
5513     return CPU == "mips32r6" || CPU == "mips64r6";
5514   }
5515 
5516   bool isFP64Default() const {
5517     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5518   }
5519 
5520   StringRef getABI() const override { return ABI; }
5521   bool setCPU(const std::string &Name) override {
5522     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5523                     getTriple().getArch() == llvm::Triple::mipsel;
5524     CPU = Name;
5525     return llvm::StringSwitch<bool>(Name)
5526         .Case("mips1", IsMips32)
5527         .Case("mips2", IsMips32)
5528         .Case("mips3", true)
5529         .Case("mips4", true)
5530         .Case("mips5", true)
5531         .Case("mips32", IsMips32)
5532         .Case("mips32r2", IsMips32)
5533         .Case("mips32r6", IsMips32)
5534         .Case("mips64", true)
5535         .Case("mips64r2", true)
5536         .Case("mips64r6", true)
5537         .Case("octeon", true)
5538         .Default(false);
5539   }
5540   const std::string& getCPU() const { return CPU; }
5541   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5542     // The backend enables certain ABI's by default according to the
5543     // architecture.
5544     // Disable both possible defaults so that we don't end up with multiple
5545     // ABI's selected and trigger an assertion.
5546     Features["o32"] = false;
5547     Features["n64"] = false;
5548 
5549     Features[ABI] = true;
5550     if (CPU == "octeon")
5551       Features["mips64r2"] = Features["cnmips"] = true;
5552     else
5553       Features[CPU] = true;
5554   }
5555 
5556   void getTargetDefines(const LangOptions &Opts,
5557                         MacroBuilder &Builder) const override {
5558     Builder.defineMacro("__mips__");
5559     Builder.defineMacro("_mips");
5560     if (Opts.GNUMode)
5561       Builder.defineMacro("mips");
5562 
5563     Builder.defineMacro("__REGISTER_PREFIX__", "");
5564 
5565     switch (FloatABI) {
5566     case HardFloat:
5567       Builder.defineMacro("__mips_hard_float", Twine(1));
5568       break;
5569     case SoftFloat:
5570       Builder.defineMacro("__mips_soft_float", Twine(1));
5571       break;
5572     }
5573 
5574     if (IsSingleFloat)
5575       Builder.defineMacro("__mips_single_float", Twine(1));
5576 
5577     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5578     Builder.defineMacro("_MIPS_FPSET",
5579                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5580 
5581     if (IsMips16)
5582       Builder.defineMacro("__mips16", Twine(1));
5583 
5584     if (IsMicromips)
5585       Builder.defineMacro("__mips_micromips", Twine(1));
5586 
5587     if (IsNan2008)
5588       Builder.defineMacro("__mips_nan2008", Twine(1));
5589 
5590     switch (DspRev) {
5591     default:
5592       break;
5593     case DSP1:
5594       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5595       Builder.defineMacro("__mips_dsp", Twine(1));
5596       break;
5597     case DSP2:
5598       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5599       Builder.defineMacro("__mips_dspr2", Twine(1));
5600       Builder.defineMacro("__mips_dsp", Twine(1));
5601       break;
5602     }
5603 
5604     if (HasMSA)
5605       Builder.defineMacro("__mips_msa", Twine(1));
5606 
5607     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5608     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5609     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5610 
5611     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5612     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5613   }
5614 
5615   void getTargetBuiltins(const Builtin::Info *&Records,
5616                          unsigned &NumRecords) const override {
5617     Records = BuiltinInfo;
5618     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5619   }
5620   bool hasFeature(StringRef Feature) const override {
5621     return llvm::StringSwitch<bool>(Feature)
5622       .Case("mips", true)
5623       .Case("fp64", HasFP64)
5624       .Default(false);
5625   }
5626   BuiltinVaListKind getBuiltinVaListKind() const override {
5627     return TargetInfo::VoidPtrBuiltinVaList;
5628   }
5629   void getGCCRegNames(const char * const *&Names,
5630                       unsigned &NumNames) const override {
5631     static const char *const GCCRegNames[] = {
5632       // CPU register names
5633       // Must match second column of GCCRegAliases
5634       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5635       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5636       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5637       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5638       // Floating point register names
5639       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5640       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5641       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5642       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5643       // Hi/lo and condition register names
5644       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5645       "$fcc5","$fcc6","$fcc7",
5646       // MSA register names
5647       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5648       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5649       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5650       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5651       // MSA control register names
5652       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5653       "$msarequest", "$msamap", "$msaunmap"
5654     };
5655     Names = GCCRegNames;
5656     NumNames = llvm::array_lengthof(GCCRegNames);
5657   }
5658   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5659                         unsigned &NumAliases) const override = 0;
5660   bool validateAsmConstraint(const char *&Name,
5661                              TargetInfo::ConstraintInfo &Info) const override {
5662     switch (*Name) {
5663     default:
5664       return false;
5665 
5666     case 'r': // CPU registers.
5667     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5668     case 'y': // Equivalent to "r", backward compatibility only.
5669     case 'f': // floating-point registers.
5670     case 'c': // $25 for indirect jumps
5671     case 'l': // lo register
5672     case 'x': // hilo register pair
5673       Info.setAllowsRegister();
5674       return true;
5675     case 'R': // An address that can be used in a non-macro load or store
5676       Info.setAllowsMemory();
5677       return true;
5678     }
5679   }
5680 
5681   const char *getClobbers() const override {
5682     // FIXME: Implement!
5683     return "";
5684   }
5685 
5686   bool handleTargetFeatures(std::vector<std::string> &Features,
5687                             DiagnosticsEngine &Diags) override {
5688     IsMips16 = false;
5689     IsMicromips = false;
5690     IsNan2008 = isNaN2008Default();
5691     IsSingleFloat = false;
5692     FloatABI = HardFloat;
5693     DspRev = NoDSP;
5694     HasFP64 = isFP64Default();
5695 
5696     for (std::vector<std::string>::iterator it = Features.begin(),
5697          ie = Features.end(); it != ie; ++it) {
5698       if (*it == "+single-float")
5699         IsSingleFloat = true;
5700       else if (*it == "+soft-float")
5701         FloatABI = SoftFloat;
5702       else if (*it == "+mips16")
5703         IsMips16 = true;
5704       else if (*it == "+micromips")
5705         IsMicromips = true;
5706       else if (*it == "+dsp")
5707         DspRev = std::max(DspRev, DSP1);
5708       else if (*it == "+dspr2")
5709         DspRev = std::max(DspRev, DSP2);
5710       else if (*it == "+msa")
5711         HasMSA = true;
5712       else if (*it == "+fp64")
5713         HasFP64 = true;
5714       else if (*it == "-fp64")
5715         HasFP64 = false;
5716       else if (*it == "+nan2008")
5717         IsNan2008 = true;
5718       else if (*it == "-nan2008")
5719         IsNan2008 = false;
5720     }
5721 
5722     // Remove front-end specific options.
5723     std::vector<std::string>::iterator it =
5724       std::find(Features.begin(), Features.end(), "+soft-float");
5725     if (it != Features.end())
5726       Features.erase(it);
5727 
5728     setDescriptionString();
5729 
5730     return true;
5731   }
5732 
5733   int getEHDataRegisterNumber(unsigned RegNo) const override {
5734     if (RegNo == 0) return 4;
5735     if (RegNo == 1) return 5;
5736     return -1;
5737   }
5738 
5739   bool isCLZForZeroUndef() const override { return false; }
5740 };
5741 
5742 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5743 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5744 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5745                                               ALL_LANGUAGES },
5746 #include "clang/Basic/BuiltinsMips.def"
5747 };
5748 
5749 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5750 public:
5751   Mips32TargetInfoBase(const llvm::Triple &Triple)
5752       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5753     SizeType = UnsignedInt;
5754     PtrDiffType = SignedInt;
5755     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5756   }
5757   bool setABI(const std::string &Name) override {
5758     if (Name == "o32" || Name == "eabi") {
5759       ABI = Name;
5760       return true;
5761     }
5762     return false;
5763   }
5764   void getTargetDefines(const LangOptions &Opts,
5765                         MacroBuilder &Builder) const override {
5766     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5767 
5768     Builder.defineMacro("__mips", "32");
5769     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5770 
5771     const std::string& CPUStr = getCPU();
5772     if (CPUStr == "mips32")
5773       Builder.defineMacro("__mips_isa_rev", "1");
5774     else if (CPUStr == "mips32r2")
5775       Builder.defineMacro("__mips_isa_rev", "2");
5776 
5777     if (ABI == "o32") {
5778       Builder.defineMacro("__mips_o32");
5779       Builder.defineMacro("_ABIO32", "1");
5780       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5781     }
5782     else if (ABI == "eabi")
5783       Builder.defineMacro("__mips_eabi");
5784     else
5785       llvm_unreachable("Invalid ABI for Mips32.");
5786   }
5787   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5788                         unsigned &NumAliases) const override {
5789     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5790       { { "at" },  "$1" },
5791       { { "v0" },  "$2" },
5792       { { "v1" },  "$3" },
5793       { { "a0" },  "$4" },
5794       { { "a1" },  "$5" },
5795       { { "a2" },  "$6" },
5796       { { "a3" },  "$7" },
5797       { { "t0" },  "$8" },
5798       { { "t1" },  "$9" },
5799       { { "t2" }, "$10" },
5800       { { "t3" }, "$11" },
5801       { { "t4" }, "$12" },
5802       { { "t5" }, "$13" },
5803       { { "t6" }, "$14" },
5804       { { "t7" }, "$15" },
5805       { { "s0" }, "$16" },
5806       { { "s1" }, "$17" },
5807       { { "s2" }, "$18" },
5808       { { "s3" }, "$19" },
5809       { { "s4" }, "$20" },
5810       { { "s5" }, "$21" },
5811       { { "s6" }, "$22" },
5812       { { "s7" }, "$23" },
5813       { { "t8" }, "$24" },
5814       { { "t9" }, "$25" },
5815       { { "k0" }, "$26" },
5816       { { "k1" }, "$27" },
5817       { { "gp" }, "$28" },
5818       { { "sp","$sp" }, "$29" },
5819       { { "fp","$fp" }, "$30" },
5820       { { "ra" }, "$31" }
5821     };
5822     Aliases = GCCRegAliases;
5823     NumAliases = llvm::array_lengthof(GCCRegAliases);
5824   }
5825 };
5826 
5827 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5828   void setDescriptionString() override {
5829     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5830   }
5831 
5832 public:
5833   Mips32EBTargetInfo(const llvm::Triple &Triple)
5834       : Mips32TargetInfoBase(Triple) {
5835   }
5836   void getTargetDefines(const LangOptions &Opts,
5837                         MacroBuilder &Builder) const override {
5838     DefineStd(Builder, "MIPSEB", Opts);
5839     Builder.defineMacro("_MIPSEB");
5840     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5841   }
5842 };
5843 
5844 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5845   void setDescriptionString() override {
5846     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5847   }
5848 
5849 public:
5850   Mips32ELTargetInfo(const llvm::Triple &Triple)
5851       : Mips32TargetInfoBase(Triple) {
5852     BigEndian = false;
5853   }
5854   void getTargetDefines(const LangOptions &Opts,
5855                         MacroBuilder &Builder) const override {
5856     DefineStd(Builder, "MIPSEL", Opts);
5857     Builder.defineMacro("_MIPSEL");
5858     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5859   }
5860 };
5861 
5862 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5863 public:
5864   Mips64TargetInfoBase(const llvm::Triple &Triple)
5865       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5866     LongDoubleWidth = LongDoubleAlign = 128;
5867     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5868     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5869       LongDoubleWidth = LongDoubleAlign = 64;
5870       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5871     }
5872     setN64ABITypes();
5873     SuitableAlign = 128;
5874     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5875   }
5876 
5877   void setN64ABITypes() {
5878     LongWidth = LongAlign = 64;
5879     PointerWidth = PointerAlign = 64;
5880     SizeType = UnsignedLong;
5881     PtrDiffType = SignedLong;
5882   }
5883 
5884   void setN32ABITypes() {
5885     LongWidth = LongAlign = 32;
5886     PointerWidth = PointerAlign = 32;
5887     SizeType = UnsignedInt;
5888     PtrDiffType = SignedInt;
5889   }
5890 
5891   bool setABI(const std::string &Name) override {
5892     if (Name == "n32") {
5893       setN32ABITypes();
5894       ABI = Name;
5895       return true;
5896     }
5897     if (Name == "n64") {
5898       setN64ABITypes();
5899       ABI = Name;
5900       return true;
5901     }
5902     return false;
5903   }
5904 
5905   void getTargetDefines(const LangOptions &Opts,
5906                         MacroBuilder &Builder) const override {
5907     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5908 
5909     Builder.defineMacro("__mips", "64");
5910     Builder.defineMacro("__mips64");
5911     Builder.defineMacro("__mips64__");
5912     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5913 
5914     const std::string& CPUStr = getCPU();
5915     if (CPUStr == "mips64")
5916       Builder.defineMacro("__mips_isa_rev", "1");
5917     else if (CPUStr == "mips64r2")
5918       Builder.defineMacro("__mips_isa_rev", "2");
5919 
5920     if (ABI == "n32") {
5921       Builder.defineMacro("__mips_n32");
5922       Builder.defineMacro("_ABIN32", "2");
5923       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5924     }
5925     else if (ABI == "n64") {
5926       Builder.defineMacro("__mips_n64");
5927       Builder.defineMacro("_ABI64", "3");
5928       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5929     }
5930     else
5931       llvm_unreachable("Invalid ABI for Mips64.");
5932   }
5933   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5934                         unsigned &NumAliases) const override {
5935     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5936       { { "at" },  "$1" },
5937       { { "v0" },  "$2" },
5938       { { "v1" },  "$3" },
5939       { { "a0" },  "$4" },
5940       { { "a1" },  "$5" },
5941       { { "a2" },  "$6" },
5942       { { "a3" },  "$7" },
5943       { { "a4" },  "$8" },
5944       { { "a5" },  "$9" },
5945       { { "a6" }, "$10" },
5946       { { "a7" }, "$11" },
5947       { { "t0" }, "$12" },
5948       { { "t1" }, "$13" },
5949       { { "t2" }, "$14" },
5950       { { "t3" }, "$15" },
5951       { { "s0" }, "$16" },
5952       { { "s1" }, "$17" },
5953       { { "s2" }, "$18" },
5954       { { "s3" }, "$19" },
5955       { { "s4" }, "$20" },
5956       { { "s5" }, "$21" },
5957       { { "s6" }, "$22" },
5958       { { "s7" }, "$23" },
5959       { { "t8" }, "$24" },
5960       { { "t9" }, "$25" },
5961       { { "k0" }, "$26" },
5962       { { "k1" }, "$27" },
5963       { { "gp" }, "$28" },
5964       { { "sp","$sp" }, "$29" },
5965       { { "fp","$fp" }, "$30" },
5966       { { "ra" }, "$31" }
5967     };
5968     Aliases = GCCRegAliases;
5969     NumAliases = llvm::array_lengthof(GCCRegAliases);
5970   }
5971 
5972   bool hasInt128Type() const override { return true; }
5973 };
5974 
5975 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5976   void setDescriptionString() override {
5977     if (ABI == "n32")
5978       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5979     else
5980       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5981 
5982   }
5983 
5984 public:
5985   Mips64EBTargetInfo(const llvm::Triple &Triple)
5986       : Mips64TargetInfoBase(Triple) {}
5987   void getTargetDefines(const LangOptions &Opts,
5988                         MacroBuilder &Builder) const override {
5989     DefineStd(Builder, "MIPSEB", Opts);
5990     Builder.defineMacro("_MIPSEB");
5991     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5992   }
5993 };
5994 
5995 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5996   void setDescriptionString() override {
5997     if (ABI == "n32")
5998       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5999     else
6000       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
6001   }
6002 public:
6003   Mips64ELTargetInfo(const llvm::Triple &Triple)
6004       : Mips64TargetInfoBase(Triple) {
6005     // Default ABI is n64.
6006     BigEndian = false;
6007   }
6008   void getTargetDefines(const LangOptions &Opts,
6009                         MacroBuilder &Builder) const override {
6010     DefineStd(Builder, "MIPSEL", Opts);
6011     Builder.defineMacro("_MIPSEL");
6012     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6013   }
6014 };
6015 } // end anonymous namespace.
6016 
6017 namespace {
6018 class PNaClTargetInfo : public TargetInfo {
6019 public:
6020   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6021     BigEndian = false;
6022     this->UserLabelPrefix = "";
6023     this->LongAlign = 32;
6024     this->LongWidth = 32;
6025     this->PointerAlign = 32;
6026     this->PointerWidth = 32;
6027     this->IntMaxType = TargetInfo::SignedLongLong;
6028     this->Int64Type = TargetInfo::SignedLongLong;
6029     this->DoubleAlign = 64;
6030     this->LongDoubleWidth = 64;
6031     this->LongDoubleAlign = 64;
6032     this->SizeType = TargetInfo::UnsignedInt;
6033     this->PtrDiffType = TargetInfo::SignedInt;
6034     this->IntPtrType = TargetInfo::SignedInt;
6035     this->RegParmMax = 0; // Disallow regparm
6036   }
6037 
6038   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6039   }
6040   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6041     Builder.defineMacro("__le32__");
6042     Builder.defineMacro("__pnacl__");
6043   }
6044   void getTargetDefines(const LangOptions &Opts,
6045                         MacroBuilder &Builder) const override {
6046     getArchDefines(Opts, Builder);
6047   }
6048   bool hasFeature(StringRef Feature) const override {
6049     return Feature == "pnacl";
6050   }
6051   void getTargetBuiltins(const Builtin::Info *&Records,
6052                          unsigned &NumRecords) const override {
6053   }
6054   BuiltinVaListKind getBuiltinVaListKind() const override {
6055     return TargetInfo::PNaClABIBuiltinVaList;
6056   }
6057   void getGCCRegNames(const char * const *&Names,
6058                       unsigned &NumNames) const override;
6059   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6060                         unsigned &NumAliases) const override;
6061   bool validateAsmConstraint(const char *&Name,
6062                              TargetInfo::ConstraintInfo &Info) const override {
6063     return false;
6064   }
6065 
6066   const char *getClobbers() const override {
6067     return "";
6068   }
6069 };
6070 
6071 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6072                                      unsigned &NumNames) const {
6073   Names = nullptr;
6074   NumNames = 0;
6075 }
6076 
6077 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6078                                        unsigned &NumAliases) const {
6079   Aliases = nullptr;
6080   NumAliases = 0;
6081 }
6082 } // end anonymous namespace.
6083 
6084 namespace {
6085 class Le64TargetInfo : public TargetInfo {
6086   static const Builtin::Info BuiltinInfo[];
6087 
6088 public:
6089   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6090     BigEndian = false;
6091     NoAsmVariants = true;
6092     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6093     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6094     DescriptionString =
6095         "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64";
6096   }
6097 
6098   void getTargetDefines(const LangOptions &Opts,
6099                         MacroBuilder &Builder) const override {
6100     DefineStd(Builder, "unix", Opts);
6101     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6102     Builder.defineMacro("__ELF__");
6103   }
6104   void getTargetBuiltins(const Builtin::Info *&Records,
6105                          unsigned &NumRecords) const override {
6106     Records = BuiltinInfo;
6107     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6108   }
6109   BuiltinVaListKind getBuiltinVaListKind() const override {
6110     return TargetInfo::PNaClABIBuiltinVaList;
6111   }
6112   const char *getClobbers() const override { return ""; }
6113   void getGCCRegNames(const char *const *&Names,
6114                       unsigned &NumNames) const override {
6115     Names = nullptr;
6116     NumNames = 0;
6117   }
6118   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6119                         unsigned &NumAliases) const override {
6120     Aliases = nullptr;
6121     NumAliases = 0;
6122   }
6123   bool validateAsmConstraint(const char *&Name,
6124                              TargetInfo::ConstraintInfo &Info) const override {
6125     return false;
6126   }
6127 
6128   bool hasProtectedVisibility() const override { return false; }
6129 };
6130 } // end anonymous namespace.
6131 
6132 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6133 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6134   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6135 #include "clang/Basic/BuiltinsLe64.def"
6136 };
6137 
6138 namespace {
6139   static const unsigned SPIRAddrSpaceMap[] = {
6140     1,    // opencl_global
6141     3,    // opencl_local
6142     2,    // opencl_constant
6143     0,    // cuda_device
6144     0,    // cuda_constant
6145     0     // cuda_shared
6146   };
6147   class SPIRTargetInfo : public TargetInfo {
6148   public:
6149     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6150       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6151         "SPIR target must use unknown OS");
6152       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6153         "SPIR target must use unknown environment type");
6154       BigEndian = false;
6155       TLSSupported = false;
6156       LongWidth = LongAlign = 64;
6157       AddrSpaceMap = &SPIRAddrSpaceMap;
6158       UseAddrSpaceMapMangling = true;
6159       // Define available target features
6160       // These must be defined in sorted order!
6161       NoAsmVariants = true;
6162     }
6163     void getTargetDefines(const LangOptions &Opts,
6164                           MacroBuilder &Builder) const override {
6165       DefineStd(Builder, "SPIR", Opts);
6166     }
6167     bool hasFeature(StringRef Feature) const override {
6168       return Feature == "spir";
6169     }
6170 
6171     void getTargetBuiltins(const Builtin::Info *&Records,
6172                            unsigned &NumRecords) const override {}
6173     const char *getClobbers() const override {
6174       return "";
6175     }
6176     void getGCCRegNames(const char * const *&Names,
6177                         unsigned &NumNames) const override {}
6178     bool validateAsmConstraint(const char *&Name,
6179                                TargetInfo::ConstraintInfo &info) const override {
6180       return true;
6181     }
6182     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6183                           unsigned &NumAliases) const override {}
6184     BuiltinVaListKind getBuiltinVaListKind() const override {
6185       return TargetInfo::VoidPtrBuiltinVaList;
6186     }
6187   };
6188 
6189 
6190   class SPIR32TargetInfo : public SPIRTargetInfo {
6191   public:
6192     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6193       PointerWidth = PointerAlign = 32;
6194       SizeType     = TargetInfo::UnsignedInt;
6195       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6196       DescriptionString
6197         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6198           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6199     }
6200     void getTargetDefines(const LangOptions &Opts,
6201                           MacroBuilder &Builder) const override {
6202       DefineStd(Builder, "SPIR32", Opts);
6203     }
6204   };
6205 
6206   class SPIR64TargetInfo : public SPIRTargetInfo {
6207   public:
6208     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6209       PointerWidth = PointerAlign = 64;
6210       SizeType     = TargetInfo::UnsignedLong;
6211       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6212       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6213                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6214     }
6215     void getTargetDefines(const LangOptions &Opts,
6216                           MacroBuilder &Builder) const override {
6217       DefineStd(Builder, "SPIR64", Opts);
6218     }
6219   };
6220 }
6221 
6222 namespace {
6223 class XCoreTargetInfo : public TargetInfo {
6224   static const Builtin::Info BuiltinInfo[];
6225 public:
6226   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6227     BigEndian = false;
6228     NoAsmVariants = true;
6229     LongLongAlign = 32;
6230     SuitableAlign = 32;
6231     DoubleAlign = LongDoubleAlign = 32;
6232     SizeType = UnsignedInt;
6233     PtrDiffType = SignedInt;
6234     IntPtrType = SignedInt;
6235     WCharType = UnsignedChar;
6236     WIntType = UnsignedInt;
6237     UseZeroLengthBitfieldAlignment = true;
6238     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6239                         "-f64:32-a:0:32-n32";
6240   }
6241   void getTargetDefines(const LangOptions &Opts,
6242                         MacroBuilder &Builder) const override {
6243     Builder.defineMacro("__XS1B__");
6244   }
6245   void getTargetBuiltins(const Builtin::Info *&Records,
6246                          unsigned &NumRecords) const override {
6247     Records = BuiltinInfo;
6248     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6249   }
6250   BuiltinVaListKind getBuiltinVaListKind() const override {
6251     return TargetInfo::VoidPtrBuiltinVaList;
6252   }
6253   const char *getClobbers() const override {
6254     return "";
6255   }
6256   void getGCCRegNames(const char * const *&Names,
6257                       unsigned &NumNames) const override {
6258     static const char * const GCCRegNames[] = {
6259       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6260       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6261     };
6262     Names = GCCRegNames;
6263     NumNames = llvm::array_lengthof(GCCRegNames);
6264   }
6265   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6266                         unsigned &NumAliases) const override {
6267     Aliases = nullptr;
6268     NumAliases = 0;
6269   }
6270   bool validateAsmConstraint(const char *&Name,
6271                              TargetInfo::ConstraintInfo &Info) const override {
6272     return false;
6273   }
6274   int getEHDataRegisterNumber(unsigned RegNo) const override {
6275     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6276     return (RegNo < 2)? RegNo : -1;
6277   }
6278 };
6279 
6280 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6281 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6282 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6283                                               ALL_LANGUAGES },
6284 #include "clang/Basic/BuiltinsXCore.def"
6285 };
6286 } // end anonymous namespace.
6287 
6288 
6289 //===----------------------------------------------------------------------===//
6290 // Driver code
6291 //===----------------------------------------------------------------------===//
6292 
6293 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6294   llvm::Triple::OSType os = Triple.getOS();
6295 
6296   switch (Triple.getArch()) {
6297   default:
6298     return nullptr;
6299 
6300   case llvm::Triple::xcore:
6301     return new XCoreTargetInfo(Triple);
6302 
6303   case llvm::Triple::hexagon:
6304     return new HexagonTargetInfo(Triple);
6305 
6306   case llvm::Triple::aarch64:
6307     if (Triple.isOSDarwin())
6308       return new DarwinAArch64TargetInfo(Triple);
6309 
6310     switch (os) {
6311     case llvm::Triple::Linux:
6312       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6313     case llvm::Triple::NetBSD:
6314       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6315     default:
6316       return new AArch64leTargetInfo(Triple);
6317     }
6318 
6319   case llvm::Triple::aarch64_be:
6320     switch (os) {
6321     case llvm::Triple::Linux:
6322       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6323     case llvm::Triple::NetBSD:
6324       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6325     default:
6326       return new AArch64beTargetInfo(Triple);
6327     }
6328 
6329   case llvm::Triple::arm:
6330   case llvm::Triple::thumb:
6331     if (Triple.isOSBinFormatMachO())
6332       return new DarwinARMTargetInfo(Triple);
6333 
6334     switch (os) {
6335     case llvm::Triple::Linux:
6336       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6337     case llvm::Triple::FreeBSD:
6338       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6339     case llvm::Triple::NetBSD:
6340       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6341     case llvm::Triple::OpenBSD:
6342       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6343     case llvm::Triple::Bitrig:
6344       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6345     case llvm::Triple::RTEMS:
6346       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6347     case llvm::Triple::NaCl:
6348       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6349     case llvm::Triple::Win32:
6350       switch (Triple.getEnvironment()) {
6351       default:
6352         return new ARMleTargetInfo(Triple);
6353       case llvm::Triple::Itanium:
6354         return new ItaniumWindowsARMleTargetInfo(Triple);
6355       case llvm::Triple::MSVC:
6356         return new MicrosoftARMleTargetInfo(Triple);
6357       }
6358     default:
6359       return new ARMleTargetInfo(Triple);
6360     }
6361 
6362   case llvm::Triple::armeb:
6363   case llvm::Triple::thumbeb:
6364     if (Triple.isOSDarwin())
6365       return new DarwinARMTargetInfo(Triple);
6366 
6367     switch (os) {
6368     case llvm::Triple::Linux:
6369       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6370     case llvm::Triple::FreeBSD:
6371       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6372     case llvm::Triple::NetBSD:
6373       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6374     case llvm::Triple::OpenBSD:
6375       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6376     case llvm::Triple::Bitrig:
6377       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6378     case llvm::Triple::RTEMS:
6379       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6380     case llvm::Triple::NaCl:
6381       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6382     default:
6383       return new ARMbeTargetInfo(Triple);
6384     }
6385 
6386   case llvm::Triple::msp430:
6387     return new MSP430TargetInfo(Triple);
6388 
6389   case llvm::Triple::mips:
6390     switch (os) {
6391     case llvm::Triple::Linux:
6392       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6393     case llvm::Triple::RTEMS:
6394       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6395     case llvm::Triple::FreeBSD:
6396       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6397     case llvm::Triple::NetBSD:
6398       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6399     default:
6400       return new Mips32EBTargetInfo(Triple);
6401     }
6402 
6403   case llvm::Triple::mipsel:
6404     switch (os) {
6405     case llvm::Triple::Linux:
6406       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6407     case llvm::Triple::RTEMS:
6408       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6409     case llvm::Triple::FreeBSD:
6410       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6411     case llvm::Triple::NetBSD:
6412       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6413     case llvm::Triple::NaCl:
6414       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6415     default:
6416       return new Mips32ELTargetInfo(Triple);
6417     }
6418 
6419   case llvm::Triple::mips64:
6420     switch (os) {
6421     case llvm::Triple::Linux:
6422       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6423     case llvm::Triple::RTEMS:
6424       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6425     case llvm::Triple::FreeBSD:
6426       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6427     case llvm::Triple::NetBSD:
6428       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6429     case llvm::Triple::OpenBSD:
6430       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6431     default:
6432       return new Mips64EBTargetInfo(Triple);
6433     }
6434 
6435   case llvm::Triple::mips64el:
6436     switch (os) {
6437     case llvm::Triple::Linux:
6438       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6439     case llvm::Triple::RTEMS:
6440       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6441     case llvm::Triple::FreeBSD:
6442       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6443     case llvm::Triple::NetBSD:
6444       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6445     case llvm::Triple::OpenBSD:
6446       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6447     default:
6448       return new Mips64ELTargetInfo(Triple);
6449     }
6450 
6451   case llvm::Triple::le32:
6452     switch (os) {
6453       case llvm::Triple::NaCl:
6454         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6455       default:
6456         return nullptr;
6457     }
6458 
6459   case llvm::Triple::le64:
6460     return new Le64TargetInfo(Triple);
6461 
6462   case llvm::Triple::ppc:
6463     if (Triple.isOSDarwin())
6464       return new DarwinPPC32TargetInfo(Triple);
6465     switch (os) {
6466     case llvm::Triple::Linux:
6467       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6468     case llvm::Triple::FreeBSD:
6469       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6470     case llvm::Triple::NetBSD:
6471       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6472     case llvm::Triple::OpenBSD:
6473       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6474     case llvm::Triple::RTEMS:
6475       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6476     default:
6477       return new PPC32TargetInfo(Triple);
6478     }
6479 
6480   case llvm::Triple::ppc64:
6481     if (Triple.isOSDarwin())
6482       return new DarwinPPC64TargetInfo(Triple);
6483     switch (os) {
6484     case llvm::Triple::Linux:
6485       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6486     case llvm::Triple::Lv2:
6487       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6488     case llvm::Triple::FreeBSD:
6489       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6490     case llvm::Triple::NetBSD:
6491       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6492     default:
6493       return new PPC64TargetInfo(Triple);
6494     }
6495 
6496   case llvm::Triple::ppc64le:
6497     switch (os) {
6498     case llvm::Triple::Linux:
6499       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6500     default:
6501       return new PPC64TargetInfo(Triple);
6502     }
6503 
6504   case llvm::Triple::nvptx:
6505     return new NVPTX32TargetInfo(Triple);
6506   case llvm::Triple::nvptx64:
6507     return new NVPTX64TargetInfo(Triple);
6508 
6509   case llvm::Triple::r600:
6510     return new R600TargetInfo(Triple);
6511 
6512   case llvm::Triple::sparc:
6513     switch (os) {
6514     case llvm::Triple::Linux:
6515       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6516     case llvm::Triple::Solaris:
6517       return new SolarisSparcV8TargetInfo(Triple);
6518     case llvm::Triple::NetBSD:
6519       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6520     case llvm::Triple::OpenBSD:
6521       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6522     case llvm::Triple::RTEMS:
6523       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6524     default:
6525       return new SparcV8TargetInfo(Triple);
6526     }
6527 
6528   case llvm::Triple::sparcv9:
6529     switch (os) {
6530     case llvm::Triple::Linux:
6531       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6532     case llvm::Triple::Solaris:
6533       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6534     case llvm::Triple::NetBSD:
6535       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6536     case llvm::Triple::OpenBSD:
6537       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6538     case llvm::Triple::FreeBSD:
6539       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6540     default:
6541       return new SparcV9TargetInfo(Triple);
6542     }
6543 
6544   case llvm::Triple::systemz:
6545     switch (os) {
6546     case llvm::Triple::Linux:
6547       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6548     default:
6549       return new SystemZTargetInfo(Triple);
6550     }
6551 
6552   case llvm::Triple::tce:
6553     return new TCETargetInfo(Triple);
6554 
6555   case llvm::Triple::x86:
6556     if (Triple.isOSDarwin())
6557       return new DarwinI386TargetInfo(Triple);
6558 
6559     switch (os) {
6560     case llvm::Triple::Linux:
6561       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6562     case llvm::Triple::DragonFly:
6563       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6564     case llvm::Triple::NetBSD:
6565       return new NetBSDI386TargetInfo(Triple);
6566     case llvm::Triple::OpenBSD:
6567       return new OpenBSDI386TargetInfo(Triple);
6568     case llvm::Triple::Bitrig:
6569       return new BitrigI386TargetInfo(Triple);
6570     case llvm::Triple::FreeBSD:
6571       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6572     case llvm::Triple::KFreeBSD:
6573       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6574     case llvm::Triple::Minix:
6575       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6576     case llvm::Triple::Solaris:
6577       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6578     case llvm::Triple::Win32: {
6579       switch (Triple.getEnvironment()) {
6580       default:
6581         return new X86_32TargetInfo(Triple);
6582       case llvm::Triple::Cygnus:
6583         return new CygwinX86_32TargetInfo(Triple);
6584       case llvm::Triple::GNU:
6585         return new MinGWX86_32TargetInfo(Triple);
6586       case llvm::Triple::Itanium:
6587       case llvm::Triple::MSVC:
6588         return new MicrosoftX86_32TargetInfo(Triple);
6589       }
6590     }
6591     case llvm::Triple::Haiku:
6592       return new HaikuX86_32TargetInfo(Triple);
6593     case llvm::Triple::RTEMS:
6594       return new RTEMSX86_32TargetInfo(Triple);
6595     case llvm::Triple::NaCl:
6596       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6597     default:
6598       return new X86_32TargetInfo(Triple);
6599     }
6600 
6601   case llvm::Triple::x86_64:
6602     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6603       return new DarwinX86_64TargetInfo(Triple);
6604 
6605     switch (os) {
6606     case llvm::Triple::Linux:
6607       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6608     case llvm::Triple::DragonFly:
6609       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6610     case llvm::Triple::NetBSD:
6611       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6612     case llvm::Triple::OpenBSD:
6613       return new OpenBSDX86_64TargetInfo(Triple);
6614     case llvm::Triple::Bitrig:
6615       return new BitrigX86_64TargetInfo(Triple);
6616     case llvm::Triple::FreeBSD:
6617       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6618     case llvm::Triple::KFreeBSD:
6619       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6620     case llvm::Triple::Solaris:
6621       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6622     case llvm::Triple::Win32: {
6623       switch (Triple.getEnvironment()) {
6624       default:
6625         return new X86_64TargetInfo(Triple);
6626       case llvm::Triple::GNU:
6627         return new MinGWX86_64TargetInfo(Triple);
6628       case llvm::Triple::MSVC:
6629         return new MicrosoftX86_64TargetInfo(Triple);
6630       }
6631     }
6632     case llvm::Triple::NaCl:
6633       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6634     default:
6635       return new X86_64TargetInfo(Triple);
6636     }
6637 
6638     case llvm::Triple::spir: {
6639       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6640           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6641         return nullptr;
6642       return new SPIR32TargetInfo(Triple);
6643     }
6644     case llvm::Triple::spir64: {
6645       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6646           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6647         return nullptr;
6648       return new SPIR64TargetInfo(Triple);
6649     }
6650   }
6651 }
6652 
6653 /// CreateTargetInfo - Return the target info object for the specified target
6654 /// triple.
6655 TargetInfo *
6656 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6657                              const std::shared_ptr<TargetOptions> &Opts) {
6658   llvm::Triple Triple(Opts->Triple);
6659 
6660   // Construct the target
6661   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6662   if (!Target) {
6663     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6664     return nullptr;
6665   }
6666   Target->TargetOpts = Opts;
6667 
6668   // Set the target CPU if specified.
6669   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6670     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6671     return nullptr;
6672   }
6673 
6674   // Set the target ABI if specified.
6675   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6676     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6677     return nullptr;
6678   }
6679 
6680   // Set the fp math unit.
6681   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6682     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6683     return nullptr;
6684   }
6685 
6686   // Compute the default target features, we need the target to handle this
6687   // because features may have dependencies on one another.
6688   llvm::StringMap<bool> Features;
6689   Target->getDefaultFeatures(Features);
6690 
6691   // Apply the user specified deltas.
6692   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6693        I < N; ++I) {
6694     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6695     // Apply the feature via the target.
6696     bool Enabled = Name[0] == '+';
6697     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6698   }
6699 
6700   // Add the features to the compile options.
6701   //
6702   // FIXME: If we are completely confident that we have the right set, we only
6703   // need to pass the minuses.
6704   Opts->Features.clear();
6705   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6706          ie = Features.end(); it != ie; ++it)
6707     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6708   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6709     return nullptr;
6710 
6711   return Target.release();
6712 }
6713