1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // WebAssembly target 827 template <typename Target> 828 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 829 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 830 MacroBuilder &Builder) const final { 831 // A common platform macro. 832 if (Opts.POSIXThreads) 833 Builder.defineMacro("_REENTRANT"); 834 // Follow g++ convention and predefine _GNU_SOURCE for C++. 835 if (Opts.CPlusPlus) 836 Builder.defineMacro("_GNU_SOURCE"); 837 } 838 839 // As an optimization, group static init code together in a section. 840 const char *getStaticInitSectionSpecifier() const final { 841 return ".text.__startup"; 842 } 843 844 public: 845 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 850 } 851 }; 852 853 //===----------------------------------------------------------------------===// 854 // Specific target implementations. 855 //===----------------------------------------------------------------------===// 856 857 // PPC abstract base class 858 class PPCTargetInfo : public TargetInfo { 859 static const Builtin::Info BuiltinInfo[]; 860 static const char * const GCCRegNames[]; 861 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 862 std::string CPU; 863 864 // Target cpu features. 865 bool HasVSX; 866 bool HasP8Vector; 867 bool HasP8Crypto; 868 bool HasDirectMove; 869 bool HasQPX; 870 bool HasHTM; 871 bool HasBPERMD; 872 bool HasExtDiv; 873 874 protected: 875 std::string ABI; 876 877 public: 878 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 879 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 880 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 881 HasBPERMD(false), HasExtDiv(false) { 882 SimdDefaultAlign = 128; 883 LongDoubleWidth = LongDoubleAlign = 128; 884 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 885 } 886 887 /// \brief Flags for architecture specific defines. 888 typedef enum { 889 ArchDefineNone = 0, 890 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 891 ArchDefinePpcgr = 1 << 1, 892 ArchDefinePpcsq = 1 << 2, 893 ArchDefine440 = 1 << 3, 894 ArchDefine603 = 1 << 4, 895 ArchDefine604 = 1 << 5, 896 ArchDefinePwr4 = 1 << 6, 897 ArchDefinePwr5 = 1 << 7, 898 ArchDefinePwr5x = 1 << 8, 899 ArchDefinePwr6 = 1 << 9, 900 ArchDefinePwr6x = 1 << 10, 901 ArchDefinePwr7 = 1 << 11, 902 ArchDefinePwr8 = 1 << 12, 903 ArchDefinePwr9 = 1 << 13, 904 ArchDefineA2 = 1 << 14, 905 ArchDefineA2q = 1 << 15 906 } ArchDefineTypes; 907 908 // Note: GCC recognizes the following additional cpus: 909 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 910 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 911 // titan, rs64. 912 bool setCPU(const std::string &Name) override { 913 bool CPUKnown = llvm::StringSwitch<bool>(Name) 914 .Case("generic", true) 915 .Case("440", true) 916 .Case("450", true) 917 .Case("601", true) 918 .Case("602", true) 919 .Case("603", true) 920 .Case("603e", true) 921 .Case("603ev", true) 922 .Case("604", true) 923 .Case("604e", true) 924 .Case("620", true) 925 .Case("630", true) 926 .Case("g3", true) 927 .Case("7400", true) 928 .Case("g4", true) 929 .Case("7450", true) 930 .Case("g4+", true) 931 .Case("750", true) 932 .Case("970", true) 933 .Case("g5", true) 934 .Case("a2", true) 935 .Case("a2q", true) 936 .Case("e500mc", true) 937 .Case("e5500", true) 938 .Case("power3", true) 939 .Case("pwr3", true) 940 .Case("power4", true) 941 .Case("pwr4", true) 942 .Case("power5", true) 943 .Case("pwr5", true) 944 .Case("power5x", true) 945 .Case("pwr5x", true) 946 .Case("power6", true) 947 .Case("pwr6", true) 948 .Case("power6x", true) 949 .Case("pwr6x", true) 950 .Case("power7", true) 951 .Case("pwr7", true) 952 .Case("power8", true) 953 .Case("pwr8", true) 954 .Case("power9", true) 955 .Case("pwr9", true) 956 .Case("powerpc", true) 957 .Case("ppc", true) 958 .Case("powerpc64", true) 959 .Case("ppc64", true) 960 .Case("powerpc64le", true) 961 .Case("ppc64le", true) 962 .Default(false); 963 964 if (CPUKnown) 965 CPU = Name; 966 967 return CPUKnown; 968 } 969 970 971 StringRef getABI() const override { return ABI; } 972 973 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 974 return llvm::makeArrayRef(BuiltinInfo, 975 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 976 } 977 978 bool isCLZForZeroUndef() const override { return false; } 979 980 void getTargetDefines(const LangOptions &Opts, 981 MacroBuilder &Builder) const override; 982 983 bool 984 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 985 StringRef CPU, 986 const std::vector<std::string> &FeaturesVec) const override; 987 988 bool handleTargetFeatures(std::vector<std::string> &Features, 989 DiagnosticsEngine &Diags) override; 990 bool hasFeature(StringRef Feature) const override; 991 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 992 bool Enabled) const override; 993 994 ArrayRef<const char *> getGCCRegNames() const override; 995 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 996 bool validateAsmConstraint(const char *&Name, 997 TargetInfo::ConstraintInfo &Info) const override { 998 switch (*Name) { 999 default: return false; 1000 case 'O': // Zero 1001 break; 1002 case 'b': // Base register 1003 case 'f': // Floating point register 1004 Info.setAllowsRegister(); 1005 break; 1006 // FIXME: The following are added to allow parsing. 1007 // I just took a guess at what the actions should be. 1008 // Also, is more specific checking needed? I.e. specific registers? 1009 case 'd': // Floating point register (containing 64-bit value) 1010 case 'v': // Altivec vector register 1011 Info.setAllowsRegister(); 1012 break; 1013 case 'w': 1014 switch (Name[1]) { 1015 case 'd':// VSX vector register to hold vector double data 1016 case 'f':// VSX vector register to hold vector float data 1017 case 's':// VSX vector register to hold scalar float data 1018 case 'a':// Any VSX register 1019 case 'c':// An individual CR bit 1020 break; 1021 default: 1022 return false; 1023 } 1024 Info.setAllowsRegister(); 1025 Name++; // Skip over 'w'. 1026 break; 1027 case 'h': // `MQ', `CTR', or `LINK' register 1028 case 'q': // `MQ' register 1029 case 'c': // `CTR' register 1030 case 'l': // `LINK' register 1031 case 'x': // `CR' register (condition register) number 0 1032 case 'y': // `CR' register (condition register) 1033 case 'z': // `XER[CA]' carry bit (part of the XER register) 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'I': // Signed 16-bit constant 1037 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1038 // (use `L' instead for SImode constants) 1039 case 'K': // Unsigned 16-bit constant 1040 case 'L': // Signed 16-bit constant shifted left 16 bits 1041 case 'M': // Constant larger than 31 1042 case 'N': // Exact power of 2 1043 case 'P': // Constant whose negation is a signed 16-bit constant 1044 case 'G': // Floating point constant that can be loaded into a 1045 // register with one instruction per word 1046 case 'H': // Integer/Floating point constant that can be loaded 1047 // into a register using three instructions 1048 break; 1049 case 'm': // Memory operand. Note that on PowerPC targets, m can 1050 // include addresses that update the base register. It 1051 // is therefore only safe to use `m' in an asm statement 1052 // if that asm statement accesses the operand exactly once. 1053 // The asm statement must also use `%U<opno>' as a 1054 // placeholder for the "update" flag in the corresponding 1055 // load or store instruction. For example: 1056 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1057 // is correct but: 1058 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1059 // is not. Use es rather than m if you don't want the base 1060 // register to be updated. 1061 case 'e': 1062 if (Name[1] != 's') 1063 return false; 1064 // es: A "stable" memory operand; that is, one which does not 1065 // include any automodification of the base register. Unlike 1066 // `m', this constraint can be used in asm statements that 1067 // might access the operand several times, or that might not 1068 // access it at all. 1069 Info.setAllowsMemory(); 1070 Name++; // Skip over 'e'. 1071 break; 1072 case 'Q': // Memory operand that is an offset from a register (it is 1073 // usually better to use `m' or `es' in asm statements) 1074 case 'Z': // Memory operand that is an indexed or indirect from a 1075 // register (it is usually better to use `m' or `es' in 1076 // asm statements) 1077 Info.setAllowsMemory(); 1078 Info.setAllowsRegister(); 1079 break; 1080 case 'R': // AIX TOC entry 1081 case 'a': // Address operand that is an indexed or indirect from a 1082 // register (`p' is preferable for asm statements) 1083 case 'S': // Constant suitable as a 64-bit mask operand 1084 case 'T': // Constant suitable as a 32-bit mask operand 1085 case 'U': // System V Release 4 small data area reference 1086 case 't': // AND masks that can be performed by two rldic{l, r} 1087 // instructions 1088 case 'W': // Vector constant that does not require memory 1089 case 'j': // Vector constant that is all zeros. 1090 break; 1091 // End FIXME. 1092 } 1093 return true; 1094 } 1095 std::string convertConstraint(const char *&Constraint) const override { 1096 std::string R; 1097 switch (*Constraint) { 1098 case 'e': 1099 case 'w': 1100 // Two-character constraint; add "^" hint for later parsing. 1101 R = std::string("^") + std::string(Constraint, 2); 1102 Constraint++; 1103 break; 1104 default: 1105 return TargetInfo::convertConstraint(Constraint); 1106 } 1107 return R; 1108 } 1109 const char *getClobbers() const override { 1110 return ""; 1111 } 1112 int getEHDataRegisterNumber(unsigned RegNo) const override { 1113 if (RegNo == 0) return 3; 1114 if (RegNo == 1) return 4; 1115 return -1; 1116 } 1117 1118 bool hasSjLjLowering() const override { 1119 return true; 1120 } 1121 1122 bool useFloat128ManglingForLongDouble() const override { 1123 return LongDoubleWidth == 128 && 1124 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1125 getTriple().isOSBinFormatELF(); 1126 } 1127 }; 1128 1129 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1130 #define BUILTIN(ID, TYPE, ATTRS) \ 1131 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1132 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1133 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1134 #include "clang/Basic/BuiltinsPPC.def" 1135 }; 1136 1137 /// handleTargetFeatures - Perform initialization based on the user 1138 /// configured set of features. 1139 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1140 DiagnosticsEngine &Diags) { 1141 for (const auto &Feature : Features) { 1142 if (Feature == "+vsx") { 1143 HasVSX = true; 1144 } else if (Feature == "+bpermd") { 1145 HasBPERMD = true; 1146 } else if (Feature == "+extdiv") { 1147 HasExtDiv = true; 1148 } else if (Feature == "+power8-vector") { 1149 HasP8Vector = true; 1150 } else if (Feature == "+crypto") { 1151 HasP8Crypto = true; 1152 } else if (Feature == "+direct-move") { 1153 HasDirectMove = true; 1154 } else if (Feature == "+qpx") { 1155 HasQPX = true; 1156 } else if (Feature == "+htm") { 1157 HasHTM = true; 1158 } else if (Feature == "+float128") { 1159 HasFloat128 = true; 1160 } 1161 // TODO: Finish this list and add an assert that we've handled them 1162 // all. 1163 } 1164 1165 return true; 1166 } 1167 1168 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1169 /// #defines that are not tied to a specific subtarget. 1170 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1171 MacroBuilder &Builder) const { 1172 // Target identification. 1173 Builder.defineMacro("__ppc__"); 1174 Builder.defineMacro("__PPC__"); 1175 Builder.defineMacro("_ARCH_PPC"); 1176 Builder.defineMacro("__powerpc__"); 1177 Builder.defineMacro("__POWERPC__"); 1178 if (PointerWidth == 64) { 1179 Builder.defineMacro("_ARCH_PPC64"); 1180 Builder.defineMacro("__powerpc64__"); 1181 Builder.defineMacro("__ppc64__"); 1182 Builder.defineMacro("__PPC64__"); 1183 } 1184 1185 // Target properties. 1186 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1187 Builder.defineMacro("_LITTLE_ENDIAN"); 1188 } else { 1189 if (getTriple().getOS() != llvm::Triple::NetBSD && 1190 getTriple().getOS() != llvm::Triple::OpenBSD) 1191 Builder.defineMacro("_BIG_ENDIAN"); 1192 } 1193 1194 // ABI options. 1195 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1196 Builder.defineMacro("_CALL_ELF", "1"); 1197 if (ABI == "elfv2") 1198 Builder.defineMacro("_CALL_ELF", "2"); 1199 1200 // Subtarget options. 1201 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1202 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1203 1204 // FIXME: Should be controlled by command line option. 1205 if (LongDoubleWidth == 128) 1206 Builder.defineMacro("__LONG_DOUBLE_128__"); 1207 1208 if (Opts.AltiVec) { 1209 Builder.defineMacro("__VEC__", "10206"); 1210 Builder.defineMacro("__ALTIVEC__"); 1211 } 1212 1213 // CPU identification. 1214 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1215 .Case("440", ArchDefineName) 1216 .Case("450", ArchDefineName | ArchDefine440) 1217 .Case("601", ArchDefineName) 1218 .Case("602", ArchDefineName | ArchDefinePpcgr) 1219 .Case("603", ArchDefineName | ArchDefinePpcgr) 1220 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1221 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1222 .Case("604", ArchDefineName | ArchDefinePpcgr) 1223 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1224 .Case("620", ArchDefineName | ArchDefinePpcgr) 1225 .Case("630", ArchDefineName | ArchDefinePpcgr) 1226 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1227 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1228 .Case("750", ArchDefineName | ArchDefinePpcgr) 1229 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1230 | ArchDefinePpcsq) 1231 .Case("a2", ArchDefineA2) 1232 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1233 .Case("pwr3", ArchDefinePpcgr) 1234 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1235 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1236 | ArchDefinePpcsq) 1237 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1238 | ArchDefinePpcgr | ArchDefinePpcsq) 1239 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1240 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1242 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1243 | ArchDefinePpcsq) 1244 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1245 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1246 | ArchDefinePpcgr | ArchDefinePpcsq) 1247 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1248 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1249 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1250 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1251 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1252 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1253 | ArchDefinePpcsq) 1254 .Case("power3", ArchDefinePpcgr) 1255 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1256 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1257 | ArchDefinePpcsq) 1258 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1259 | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1261 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1262 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1263 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1264 | ArchDefinePpcsq) 1265 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1266 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1267 | ArchDefinePpcgr | ArchDefinePpcsq) 1268 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1269 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1270 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1271 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1272 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1273 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1274 | ArchDefinePpcsq) 1275 .Default(ArchDefineNone); 1276 1277 if (defs & ArchDefineName) 1278 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1279 if (defs & ArchDefinePpcgr) 1280 Builder.defineMacro("_ARCH_PPCGR"); 1281 if (defs & ArchDefinePpcsq) 1282 Builder.defineMacro("_ARCH_PPCSQ"); 1283 if (defs & ArchDefine440) 1284 Builder.defineMacro("_ARCH_440"); 1285 if (defs & ArchDefine603) 1286 Builder.defineMacro("_ARCH_603"); 1287 if (defs & ArchDefine604) 1288 Builder.defineMacro("_ARCH_604"); 1289 if (defs & ArchDefinePwr4) 1290 Builder.defineMacro("_ARCH_PWR4"); 1291 if (defs & ArchDefinePwr5) 1292 Builder.defineMacro("_ARCH_PWR5"); 1293 if (defs & ArchDefinePwr5x) 1294 Builder.defineMacro("_ARCH_PWR5X"); 1295 if (defs & ArchDefinePwr6) 1296 Builder.defineMacro("_ARCH_PWR6"); 1297 if (defs & ArchDefinePwr6x) 1298 Builder.defineMacro("_ARCH_PWR6X"); 1299 if (defs & ArchDefinePwr7) 1300 Builder.defineMacro("_ARCH_PWR7"); 1301 if (defs & ArchDefinePwr8) 1302 Builder.defineMacro("_ARCH_PWR8"); 1303 if (defs & ArchDefinePwr9) 1304 Builder.defineMacro("_ARCH_PWR9"); 1305 if (defs & ArchDefineA2) 1306 Builder.defineMacro("_ARCH_A2"); 1307 if (defs & ArchDefineA2q) { 1308 Builder.defineMacro("_ARCH_A2Q"); 1309 Builder.defineMacro("_ARCH_QP"); 1310 } 1311 1312 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1313 Builder.defineMacro("__bg__"); 1314 Builder.defineMacro("__THW_BLUEGENE__"); 1315 Builder.defineMacro("__bgq__"); 1316 Builder.defineMacro("__TOS_BGQ__"); 1317 } 1318 1319 if (HasVSX) 1320 Builder.defineMacro("__VSX__"); 1321 if (HasP8Vector) 1322 Builder.defineMacro("__POWER8_VECTOR__"); 1323 if (HasP8Crypto) 1324 Builder.defineMacro("__CRYPTO__"); 1325 if (HasHTM) 1326 Builder.defineMacro("__HTM__"); 1327 if (HasFloat128) 1328 Builder.defineMacro("__FLOAT128__"); 1329 1330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1333 if (PointerWidth == 64) 1334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1335 1336 // FIXME: The following are not yet generated here by Clang, but are 1337 // generated by GCC: 1338 // 1339 // _SOFT_FLOAT_ 1340 // __RECIP_PRECISION__ 1341 // __APPLE_ALTIVEC__ 1342 // __RECIP__ 1343 // __RECIPF__ 1344 // __RSQRTE__ 1345 // __RSQRTEF__ 1346 // _SOFT_DOUBLE_ 1347 // __NO_LWSYNC__ 1348 // __HAVE_BSWAP__ 1349 // __LONGDOUBLE128 1350 // __CMODEL_MEDIUM__ 1351 // __CMODEL_LARGE__ 1352 // _CALL_SYSV 1353 // _CALL_DARWIN 1354 // __NO_FPRS__ 1355 } 1356 1357 // Handle explicit options being passed to the compiler here: if we've 1358 // explicitly turned off vsx and turned on power8-vector or direct-move then 1359 // go ahead and error since the customer has expressed a somewhat incompatible 1360 // set of options. 1361 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1362 const std::vector<std::string> &FeaturesVec) { 1363 1364 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1365 FeaturesVec.end()) { 1366 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1367 FeaturesVec.end()) { 1368 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1369 << "-mno-vsx"; 1370 return false; 1371 } 1372 1373 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1374 FeaturesVec.end()) { 1375 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1376 << "-mno-vsx"; 1377 return false; 1378 } 1379 1380 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1381 FeaturesVec.end()) { 1382 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1383 << "-mno-vsx"; 1384 return false; 1385 } 1386 } 1387 1388 return true; 1389 } 1390 1391 bool PPCTargetInfo::initFeatureMap( 1392 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1393 const std::vector<std::string> &FeaturesVec) const { 1394 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1395 .Case("7400", true) 1396 .Case("g4", true) 1397 .Case("7450", true) 1398 .Case("g4+", true) 1399 .Case("970", true) 1400 .Case("g5", true) 1401 .Case("pwr6", true) 1402 .Case("pwr7", true) 1403 .Case("pwr8", true) 1404 .Case("pwr9", true) 1405 .Case("ppc64", true) 1406 .Case("ppc64le", true) 1407 .Default(false); 1408 1409 Features["qpx"] = (CPU == "a2q"); 1410 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1411 .Case("ppc64le", true) 1412 .Case("pwr9", true) 1413 .Case("pwr8", true) 1414 .Default(false); 1415 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1416 .Case("ppc64le", true) 1417 .Case("pwr9", true) 1418 .Case("pwr8", true) 1419 .Default(false); 1420 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1421 .Case("ppc64le", true) 1422 .Case("pwr9", true) 1423 .Case("pwr8", true) 1424 .Case("pwr7", true) 1425 .Default(false); 1426 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1427 .Case("ppc64le", true) 1428 .Case("pwr9", true) 1429 .Case("pwr8", true) 1430 .Case("pwr7", true) 1431 .Default(false); 1432 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("ppc64le", true) 1434 .Case("pwr9", true) 1435 .Case("pwr8", true) 1436 .Default(false); 1437 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1438 .Case("ppc64le", true) 1439 .Case("pwr9", true) 1440 .Case("pwr8", true) 1441 .Case("pwr7", true) 1442 .Default(false); 1443 1444 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1445 return false; 1446 1447 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1448 } 1449 1450 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1451 return llvm::StringSwitch<bool>(Feature) 1452 .Case("powerpc", true) 1453 .Case("vsx", HasVSX) 1454 .Case("power8-vector", HasP8Vector) 1455 .Case("crypto", HasP8Crypto) 1456 .Case("direct-move", HasDirectMove) 1457 .Case("qpx", HasQPX) 1458 .Case("htm", HasHTM) 1459 .Case("bpermd", HasBPERMD) 1460 .Case("extdiv", HasExtDiv) 1461 .Case("float128", HasFloat128) 1462 .Default(false); 1463 } 1464 1465 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1466 StringRef Name, bool Enabled) const { 1467 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1468 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1469 // incompatible options. 1470 if (Enabled) { 1471 if (Name == "direct-move") { 1472 Features[Name] = Features["vsx"] = true; 1473 } else if (Name == "power8-vector") { 1474 Features[Name] = Features["vsx"] = true; 1475 } else if (Name == "float128") { 1476 Features[Name] = Features["vsx"] = true; 1477 } else { 1478 Features[Name] = true; 1479 } 1480 } else { 1481 if (Name == "vsx") { 1482 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1483 Features["float128"] = false; 1484 } else { 1485 Features[Name] = false; 1486 } 1487 } 1488 } 1489 1490 const char * const PPCTargetInfo::GCCRegNames[] = { 1491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1492 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1493 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1494 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1495 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1496 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1497 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1498 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1499 "mq", "lr", "ctr", "ap", 1500 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1501 "xer", 1502 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1503 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1504 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1505 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1506 "vrsave", "vscr", 1507 "spe_acc", "spefscr", 1508 "sfp" 1509 }; 1510 1511 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1512 return llvm::makeArrayRef(GCCRegNames); 1513 } 1514 1515 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1516 // While some of these aliases do map to different registers 1517 // they still share the same register name. 1518 { { "0" }, "r0" }, 1519 { { "1"}, "r1" }, 1520 { { "2" }, "r2" }, 1521 { { "3" }, "r3" }, 1522 { { "4" }, "r4" }, 1523 { { "5" }, "r5" }, 1524 { { "6" }, "r6" }, 1525 { { "7" }, "r7" }, 1526 { { "8" }, "r8" }, 1527 { { "9" }, "r9" }, 1528 { { "10" }, "r10" }, 1529 { { "11" }, "r11" }, 1530 { { "12" }, "r12" }, 1531 { { "13" }, "r13" }, 1532 { { "14" }, "r14" }, 1533 { { "15" }, "r15" }, 1534 { { "16" }, "r16" }, 1535 { { "17" }, "r17" }, 1536 { { "18" }, "r18" }, 1537 { { "19" }, "r19" }, 1538 { { "20" }, "r20" }, 1539 { { "21" }, "r21" }, 1540 { { "22" }, "r22" }, 1541 { { "23" }, "r23" }, 1542 { { "24" }, "r24" }, 1543 { { "25" }, "r25" }, 1544 { { "26" }, "r26" }, 1545 { { "27" }, "r27" }, 1546 { { "28" }, "r28" }, 1547 { { "29" }, "r29" }, 1548 { { "30" }, "r30" }, 1549 { { "31" }, "r31" }, 1550 { { "fr0" }, "f0" }, 1551 { { "fr1" }, "f1" }, 1552 { { "fr2" }, "f2" }, 1553 { { "fr3" }, "f3" }, 1554 { { "fr4" }, "f4" }, 1555 { { "fr5" }, "f5" }, 1556 { { "fr6" }, "f6" }, 1557 { { "fr7" }, "f7" }, 1558 { { "fr8" }, "f8" }, 1559 { { "fr9" }, "f9" }, 1560 { { "fr10" }, "f10" }, 1561 { { "fr11" }, "f11" }, 1562 { { "fr12" }, "f12" }, 1563 { { "fr13" }, "f13" }, 1564 { { "fr14" }, "f14" }, 1565 { { "fr15" }, "f15" }, 1566 { { "fr16" }, "f16" }, 1567 { { "fr17" }, "f17" }, 1568 { { "fr18" }, "f18" }, 1569 { { "fr19" }, "f19" }, 1570 { { "fr20" }, "f20" }, 1571 { { "fr21" }, "f21" }, 1572 { { "fr22" }, "f22" }, 1573 { { "fr23" }, "f23" }, 1574 { { "fr24" }, "f24" }, 1575 { { "fr25" }, "f25" }, 1576 { { "fr26" }, "f26" }, 1577 { { "fr27" }, "f27" }, 1578 { { "fr28" }, "f28" }, 1579 { { "fr29" }, "f29" }, 1580 { { "fr30" }, "f30" }, 1581 { { "fr31" }, "f31" }, 1582 { { "cc" }, "cr0" }, 1583 }; 1584 1585 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1586 return llvm::makeArrayRef(GCCRegAliases); 1587 } 1588 1589 class PPC32TargetInfo : public PPCTargetInfo { 1590 public: 1591 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1592 : PPCTargetInfo(Triple, Opts) { 1593 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1594 1595 switch (getTriple().getOS()) { 1596 case llvm::Triple::Linux: 1597 case llvm::Triple::FreeBSD: 1598 case llvm::Triple::NetBSD: 1599 SizeType = UnsignedInt; 1600 PtrDiffType = SignedInt; 1601 IntPtrType = SignedInt; 1602 break; 1603 default: 1604 break; 1605 } 1606 1607 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1608 LongDoubleWidth = LongDoubleAlign = 64; 1609 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1610 } 1611 1612 // PPC32 supports atomics up to 4 bytes. 1613 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1614 } 1615 1616 BuiltinVaListKind getBuiltinVaListKind() const override { 1617 // This is the ELF definition, and is overridden by the Darwin sub-target 1618 return TargetInfo::PowerABIBuiltinVaList; 1619 } 1620 }; 1621 1622 // Note: ABI differences may eventually require us to have a separate 1623 // TargetInfo for little endian. 1624 class PPC64TargetInfo : public PPCTargetInfo { 1625 public: 1626 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1627 : PPCTargetInfo(Triple, Opts) { 1628 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1629 IntMaxType = SignedLong; 1630 Int64Type = SignedLong; 1631 1632 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1633 resetDataLayout("e-m:e-i64:64-n32:64"); 1634 ABI = "elfv2"; 1635 } else { 1636 resetDataLayout("E-m:e-i64:64-n32:64"); 1637 ABI = "elfv1"; 1638 } 1639 1640 switch (getTriple().getOS()) { 1641 case llvm::Triple::FreeBSD: 1642 LongDoubleWidth = LongDoubleAlign = 64; 1643 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1644 break; 1645 case llvm::Triple::NetBSD: 1646 IntMaxType = SignedLongLong; 1647 Int64Type = SignedLongLong; 1648 break; 1649 default: 1650 break; 1651 } 1652 1653 // PPC64 supports atomics up to 8 bytes. 1654 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1655 } 1656 BuiltinVaListKind getBuiltinVaListKind() const override { 1657 return TargetInfo::CharPtrBuiltinVaList; 1658 } 1659 // PPC64 Linux-specific ABI options. 1660 bool setABI(const std::string &Name) override { 1661 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1662 ABI = Name; 1663 return true; 1664 } 1665 return false; 1666 } 1667 }; 1668 1669 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1670 public: 1671 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1672 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1673 HasAlignMac68kSupport = true; 1674 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1675 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1676 LongLongAlign = 32; 1677 SuitableAlign = 128; 1678 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1679 } 1680 BuiltinVaListKind getBuiltinVaListKind() const override { 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 }; 1684 1685 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1686 public: 1687 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1688 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1689 HasAlignMac68kSupport = true; 1690 SuitableAlign = 128; 1691 resetDataLayout("E-m:o-i64:64-n32:64"); 1692 } 1693 }; 1694 1695 static const unsigned NVPTXAddrSpaceMap[] = { 1696 1, // opencl_global 1697 3, // opencl_local 1698 4, // opencl_constant 1699 // FIXME: generic has to be added to the target 1700 0, // opencl_generic 1701 1, // cuda_device 1702 4, // cuda_constant 1703 3, // cuda_shared 1704 }; 1705 1706 class NVPTXTargetInfo : public TargetInfo { 1707 static const char *const GCCRegNames[]; 1708 static const Builtin::Info BuiltinInfo[]; 1709 CudaArch GPU; 1710 1711 public: 1712 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : TargetInfo(Triple) { 1714 TLSSupported = false; 1715 LongWidth = LongAlign = 64; 1716 AddrSpaceMap = &NVPTXAddrSpaceMap; 1717 UseAddrSpaceMapMangling = true; 1718 // Define available target features 1719 // These must be defined in sorted order! 1720 NoAsmVariants = true; 1721 GPU = CudaArch::SM_20; 1722 1723 // If possible, get a TargetInfo for our host triple, so we can match its 1724 // types. 1725 llvm::Triple HostTriple(Opts.HostTriple); 1726 if (HostTriple.isNVPTX()) 1727 return; 1728 std::unique_ptr<TargetInfo> HostTarget( 1729 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1730 if (!HostTarget) { 1731 return; 1732 } 1733 1734 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1735 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1736 BoolWidth = HostTarget->getBoolWidth(); 1737 BoolAlign = HostTarget->getBoolAlign(); 1738 IntWidth = HostTarget->getIntWidth(); 1739 IntAlign = HostTarget->getIntAlign(); 1740 HalfWidth = HostTarget->getHalfWidth(); 1741 HalfAlign = HostTarget->getHalfAlign(); 1742 FloatWidth = HostTarget->getFloatWidth(); 1743 FloatAlign = HostTarget->getFloatAlign(); 1744 DoubleWidth = HostTarget->getDoubleWidth(); 1745 DoubleAlign = HostTarget->getDoubleAlign(); 1746 LongWidth = HostTarget->getLongWidth(); 1747 LongAlign = HostTarget->getLongAlign(); 1748 LongLongWidth = HostTarget->getLongLongWidth(); 1749 LongLongAlign = HostTarget->getLongLongAlign(); 1750 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1751 DefaultAlignForAttributeAligned = 1752 HostTarget->getDefaultAlignForAttributeAligned(); 1753 SizeType = HostTarget->getSizeType(); 1754 IntMaxType = HostTarget->getIntMaxType(); 1755 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1756 IntPtrType = HostTarget->getIntPtrType(); 1757 WCharType = HostTarget->getWCharType(); 1758 WIntType = HostTarget->getWIntType(); 1759 Char16Type = HostTarget->getChar16Type(); 1760 Char32Type = HostTarget->getChar32Type(); 1761 Int64Type = HostTarget->getInt64Type(); 1762 SigAtomicType = HostTarget->getSigAtomicType(); 1763 ProcessIDType = HostTarget->getProcessIDType(); 1764 1765 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1766 UseZeroLengthBitfieldAlignment = 1767 HostTarget->useZeroLengthBitfieldAlignment(); 1768 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1769 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1770 1771 // Properties intentionally not copied from host: 1772 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1773 // host/device boundary. 1774 // - SuitableAlign: Not visible across the host/device boundary, and may 1775 // correctly be different on host/device, e.g. if host has wider vector 1776 // types than device. 1777 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1778 // as its double type, but that's not necessarily true on the host. 1779 // TODO: nvcc emits a warning when using long double on device; we should 1780 // do the same. 1781 } 1782 void getTargetDefines(const LangOptions &Opts, 1783 MacroBuilder &Builder) const override { 1784 Builder.defineMacro("__PTX__"); 1785 Builder.defineMacro("__NVPTX__"); 1786 if (Opts.CUDAIsDevice) { 1787 // Set __CUDA_ARCH__ for the GPU specified. 1788 std::string CUDAArchCode = [this] { 1789 switch (GPU) { 1790 case CudaArch::UNKNOWN: 1791 assert(false && "No GPU arch when compiling CUDA device code."); 1792 return ""; 1793 case CudaArch::SM_20: 1794 return "200"; 1795 case CudaArch::SM_21: 1796 return "210"; 1797 case CudaArch::SM_30: 1798 return "300"; 1799 case CudaArch::SM_32: 1800 return "320"; 1801 case CudaArch::SM_35: 1802 return "350"; 1803 case CudaArch::SM_37: 1804 return "370"; 1805 case CudaArch::SM_50: 1806 return "500"; 1807 case CudaArch::SM_52: 1808 return "520"; 1809 case CudaArch::SM_53: 1810 return "530"; 1811 case CudaArch::SM_60: 1812 return "600"; 1813 case CudaArch::SM_61: 1814 return "610"; 1815 case CudaArch::SM_62: 1816 return "620"; 1817 } 1818 llvm_unreachable("unhandled CudaArch"); 1819 }(); 1820 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1821 } 1822 } 1823 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1824 return llvm::makeArrayRef(BuiltinInfo, 1825 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1826 } 1827 bool hasFeature(StringRef Feature) const override { 1828 return Feature == "ptx" || Feature == "nvptx"; 1829 } 1830 1831 ArrayRef<const char *> getGCCRegNames() const override; 1832 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1833 // No aliases. 1834 return None; 1835 } 1836 bool validateAsmConstraint(const char *&Name, 1837 TargetInfo::ConstraintInfo &Info) const override { 1838 switch (*Name) { 1839 default: 1840 return false; 1841 case 'c': 1842 case 'h': 1843 case 'r': 1844 case 'l': 1845 case 'f': 1846 case 'd': 1847 Info.setAllowsRegister(); 1848 return true; 1849 } 1850 } 1851 const char *getClobbers() const override { 1852 // FIXME: Is this really right? 1853 return ""; 1854 } 1855 BuiltinVaListKind getBuiltinVaListKind() const override { 1856 // FIXME: implement 1857 return TargetInfo::CharPtrBuiltinVaList; 1858 } 1859 bool setCPU(const std::string &Name) override { 1860 GPU = StringToCudaArch(Name); 1861 return GPU != CudaArch::UNKNOWN; 1862 } 1863 void setSupportedOpenCLOpts() override { 1864 auto &Opts = getSupportedOpenCLOpts(); 1865 Opts.cl_clang_storage_class_specifiers = 1; 1866 Opts.cl_khr_gl_sharing = 1; 1867 Opts.cl_khr_icd = 1; 1868 1869 Opts.cl_khr_fp64 = 1; 1870 Opts.cl_khr_byte_addressable_store = 1; 1871 Opts.cl_khr_global_int32_base_atomics = 1; 1872 Opts.cl_khr_global_int32_extended_atomics = 1; 1873 Opts.cl_khr_local_int32_base_atomics = 1; 1874 Opts.cl_khr_local_int32_extended_atomics = 1; 1875 } 1876 }; 1877 1878 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1879 #define BUILTIN(ID, TYPE, ATTRS) \ 1880 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1881 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1882 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1883 #include "clang/Basic/BuiltinsNVPTX.def" 1884 }; 1885 1886 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1887 1888 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1889 return llvm::makeArrayRef(GCCRegNames); 1890 } 1891 1892 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1893 public: 1894 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1895 : NVPTXTargetInfo(Triple, Opts) { 1896 LongWidth = LongAlign = 32; 1897 PointerWidth = PointerAlign = 32; 1898 SizeType = TargetInfo::UnsignedInt; 1899 PtrDiffType = TargetInfo::SignedInt; 1900 IntPtrType = TargetInfo::SignedInt; 1901 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1902 } 1903 }; 1904 1905 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1906 public: 1907 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1908 : NVPTXTargetInfo(Triple, Opts) { 1909 PointerWidth = PointerAlign = 64; 1910 SizeType = TargetInfo::UnsignedLong; 1911 PtrDiffType = TargetInfo::SignedLong; 1912 IntPtrType = TargetInfo::SignedLong; 1913 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1914 } 1915 }; 1916 1917 static const unsigned AMDGPUAddrSpaceMap[] = { 1918 1, // opencl_global 1919 3, // opencl_local 1920 2, // opencl_constant 1921 4, // opencl_generic 1922 1, // cuda_device 1923 2, // cuda_constant 1924 3 // cuda_shared 1925 }; 1926 1927 // If you edit the description strings, make sure you update 1928 // getPointerWidthV(). 1929 1930 static const char *const DataLayoutStringR600 = 1931 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1932 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1933 1934 static const char *const DataLayoutStringSI = 1935 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1936 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1937 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1938 1939 class AMDGPUTargetInfo final : public TargetInfo { 1940 static const Builtin::Info BuiltinInfo[]; 1941 static const char * const GCCRegNames[]; 1942 1943 /// \brief The GPU profiles supported by the AMDGPU target. 1944 enum GPUKind { 1945 GK_NONE, 1946 GK_R600, 1947 GK_R600_DOUBLE_OPS, 1948 GK_R700, 1949 GK_R700_DOUBLE_OPS, 1950 GK_EVERGREEN, 1951 GK_EVERGREEN_DOUBLE_OPS, 1952 GK_NORTHERN_ISLANDS, 1953 GK_CAYMAN, 1954 GK_GFX6, 1955 GK_GFX7, 1956 GK_GFX8 1957 } GPU; 1958 1959 bool hasFP64:1; 1960 bool hasFMAF:1; 1961 bool hasLDEXPF:1; 1962 bool hasDenormSupport:1; 1963 1964 static bool isAMDGCN(const llvm::Triple &TT) { 1965 return TT.getArch() == llvm::Triple::amdgcn; 1966 } 1967 1968 public: 1969 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1970 : TargetInfo(Triple) , 1971 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 1972 hasFP64(false), 1973 hasFMAF(false), 1974 hasLDEXPF(false), 1975 hasDenormSupport(false){ 1976 if (getTriple().getArch() == llvm::Triple::amdgcn) { 1977 hasFP64 = true; 1978 hasFMAF = true; 1979 hasLDEXPF = true; 1980 } 1981 if (Opts.CPU == "fiji") 1982 hasDenormSupport = true; 1983 1984 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 1985 DataLayoutStringSI : DataLayoutStringR600); 1986 1987 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1988 UseAddrSpaceMapMangling = true; 1989 } 1990 1991 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1992 if (GPU <= GK_CAYMAN) 1993 return 32; 1994 1995 switch(AddrSpace) { 1996 default: 1997 return 64; 1998 case 0: 1999 case 3: 2000 case 5: 2001 return 32; 2002 } 2003 } 2004 2005 uint64_t getMaxPointerWidth() const override { 2006 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2007 } 2008 2009 const char * getClobbers() const override { 2010 return ""; 2011 } 2012 2013 ArrayRef<const char *> getGCCRegNames() const override; 2014 2015 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2016 return None; 2017 } 2018 2019 bool validateAsmConstraint(const char *&Name, 2020 TargetInfo::ConstraintInfo &Info) const override { 2021 switch (*Name) { 2022 default: break; 2023 case 'v': // vgpr 2024 case 's': // sgpr 2025 Info.setAllowsRegister(); 2026 return true; 2027 } 2028 return false; 2029 } 2030 2031 bool initFeatureMap(llvm::StringMap<bool> &Features, 2032 DiagnosticsEngine &Diags, StringRef CPU, 2033 const std::vector<std::string> &FeatureVec) const override; 2034 2035 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2036 TargetOptions &TargetOpts) const override { 2037 if (!hasDenormSupport) 2038 return; 2039 bool hasFP32Denormals = false; 2040 bool hasFP64Denormals = false; 2041 for (auto &I : TargetOpts.FeaturesAsWritten) { 2042 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2043 hasFP32Denormals = true; 2044 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2045 hasFP64Denormals = true; 2046 } 2047 if (!hasFP32Denormals) 2048 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2049 Twine("fp32-denormals")).str()); 2050 if (!hasFP64Denormals && hasFP64) 2051 TargetOpts.Features.push_back((Twine(CGOpts.FlushDenorm ? '-' : '+') + 2052 Twine("fp64-denormals")).str()); 2053 } 2054 2055 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2056 return llvm::makeArrayRef(BuiltinInfo, 2057 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2058 } 2059 2060 void getTargetDefines(const LangOptions &Opts, 2061 MacroBuilder &Builder) const override { 2062 if (getTriple().getArch() == llvm::Triple::amdgcn) 2063 Builder.defineMacro("__AMDGCN__"); 2064 else 2065 Builder.defineMacro("__R600__"); 2066 2067 if (hasFMAF) 2068 Builder.defineMacro("__HAS_FMAF__"); 2069 if (hasLDEXPF) 2070 Builder.defineMacro("__HAS_LDEXPF__"); 2071 if (hasFP64) 2072 Builder.defineMacro("__HAS_FP64__"); 2073 } 2074 2075 BuiltinVaListKind getBuiltinVaListKind() const override { 2076 return TargetInfo::CharPtrBuiltinVaList; 2077 } 2078 2079 static GPUKind parseR600Name(StringRef Name) { 2080 return llvm::StringSwitch<GPUKind>(Name) 2081 .Case("r600" , GK_R600) 2082 .Case("rv610", GK_R600) 2083 .Case("rv620", GK_R600) 2084 .Case("rv630", GK_R600) 2085 .Case("rv635", GK_R600) 2086 .Case("rs780", GK_R600) 2087 .Case("rs880", GK_R600) 2088 .Case("rv670", GK_R600_DOUBLE_OPS) 2089 .Case("rv710", GK_R700) 2090 .Case("rv730", GK_R700) 2091 .Case("rv740", GK_R700_DOUBLE_OPS) 2092 .Case("rv770", GK_R700_DOUBLE_OPS) 2093 .Case("palm", GK_EVERGREEN) 2094 .Case("cedar", GK_EVERGREEN) 2095 .Case("sumo", GK_EVERGREEN) 2096 .Case("sumo2", GK_EVERGREEN) 2097 .Case("redwood", GK_EVERGREEN) 2098 .Case("juniper", GK_EVERGREEN) 2099 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2100 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2101 .Case("barts", GK_NORTHERN_ISLANDS) 2102 .Case("turks", GK_NORTHERN_ISLANDS) 2103 .Case("caicos", GK_NORTHERN_ISLANDS) 2104 .Case("cayman", GK_CAYMAN) 2105 .Case("aruba", GK_CAYMAN) 2106 .Default(GK_NONE); 2107 } 2108 2109 static GPUKind parseAMDGCNName(StringRef Name) { 2110 return llvm::StringSwitch<GPUKind>(Name) 2111 .Case("tahiti", GK_GFX6) 2112 .Case("pitcairn", GK_GFX6) 2113 .Case("verde", GK_GFX6) 2114 .Case("oland", GK_GFX6) 2115 .Case("hainan", GK_GFX6) 2116 .Case("bonaire", GK_GFX7) 2117 .Case("kabini", GK_GFX7) 2118 .Case("kaveri", GK_GFX7) 2119 .Case("hawaii", GK_GFX7) 2120 .Case("mullins", GK_GFX7) 2121 .Case("tonga", GK_GFX8) 2122 .Case("iceland", GK_GFX8) 2123 .Case("carrizo", GK_GFX8) 2124 .Case("fiji", GK_GFX8) 2125 .Case("stoney", GK_GFX8) 2126 .Case("polaris10", GK_GFX8) 2127 .Case("polaris11", GK_GFX8) 2128 .Default(GK_NONE); 2129 } 2130 2131 bool setCPU(const std::string &Name) override { 2132 if (getTriple().getArch() == llvm::Triple::amdgcn) 2133 GPU = parseAMDGCNName(Name); 2134 else 2135 GPU = parseR600Name(Name); 2136 2137 return GPU != GK_NONE; 2138 } 2139 2140 void setSupportedOpenCLOpts() override { 2141 auto &Opts = getSupportedOpenCLOpts(); 2142 Opts.cl_clang_storage_class_specifiers = 1; 2143 Opts.cl_khr_icd = 1; 2144 2145 if (hasFP64) 2146 Opts.cl_khr_fp64 = 1; 2147 if (GPU >= GK_EVERGREEN) { 2148 Opts.cl_khr_byte_addressable_store = 1; 2149 Opts.cl_khr_global_int32_base_atomics = 1; 2150 Opts.cl_khr_global_int32_extended_atomics = 1; 2151 Opts.cl_khr_local_int32_base_atomics = 1; 2152 Opts.cl_khr_local_int32_extended_atomics = 1; 2153 } 2154 if (GPU >= GK_GFX6) { 2155 Opts.cl_khr_fp16 = 1; 2156 Opts.cl_khr_int64_base_atomics = 1; 2157 Opts.cl_khr_int64_extended_atomics = 1; 2158 Opts.cl_khr_mipmap_image = 1; 2159 Opts.cl_khr_subgroups = 1; 2160 Opts.cl_khr_3d_image_writes = 1; 2161 Opts.cl_amd_media_ops = 1; 2162 Opts.cl_amd_media_ops2 = 1; 2163 } 2164 } 2165 2166 LangAS::ID getOpenCLImageAddrSpace() const override { 2167 return LangAS::opencl_constant; 2168 } 2169 2170 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2171 switch (CC) { 2172 default: 2173 return CCCR_Warning; 2174 case CC_C: 2175 case CC_OpenCLKernel: 2176 return CCCR_OK; 2177 } 2178 } 2179 }; 2180 2181 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2182 #define BUILTIN(ID, TYPE, ATTRS) \ 2183 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2184 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2185 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2186 #include "clang/Basic/BuiltinsAMDGPU.def" 2187 }; 2188 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2189 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2190 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2191 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2192 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2193 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2194 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2195 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2196 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2197 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2198 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2199 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2200 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2201 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2202 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2203 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2204 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2205 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2206 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2207 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2208 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2209 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2210 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2211 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2212 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2213 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2214 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2215 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2216 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2217 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2218 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2219 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2220 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2221 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2222 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2223 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2224 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2225 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2226 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2227 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2228 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2229 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2230 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2231 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2232 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2233 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2234 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2235 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2236 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2237 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2238 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2239 }; 2240 2241 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2242 return llvm::makeArrayRef(GCCRegNames); 2243 } 2244 2245 bool AMDGPUTargetInfo::initFeatureMap( 2246 llvm::StringMap<bool> &Features, 2247 DiagnosticsEngine &Diags, StringRef CPU, 2248 const std::vector<std::string> &FeatureVec) const { 2249 2250 // XXX - What does the member GPU mean if device name string passed here? 2251 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2252 if (CPU.empty()) 2253 CPU = "tahiti"; 2254 2255 switch (parseAMDGCNName(CPU)) { 2256 case GK_GFX6: 2257 case GK_GFX7: 2258 break; 2259 2260 case GK_GFX8: 2261 Features["s-memrealtime"] = true; 2262 Features["16-bit-insts"] = true; 2263 break; 2264 2265 case GK_NONE: 2266 return false; 2267 default: 2268 llvm_unreachable("unhandled subtarget"); 2269 } 2270 } else { 2271 if (CPU.empty()) 2272 CPU = "r600"; 2273 2274 switch (parseR600Name(CPU)) { 2275 case GK_R600: 2276 case GK_R700: 2277 case GK_EVERGREEN: 2278 case GK_NORTHERN_ISLANDS: 2279 break; 2280 case GK_R600_DOUBLE_OPS: 2281 case GK_R700_DOUBLE_OPS: 2282 case GK_EVERGREEN_DOUBLE_OPS: 2283 case GK_CAYMAN: 2284 Features["fp64"] = true; 2285 break; 2286 case GK_NONE: 2287 return false; 2288 default: 2289 llvm_unreachable("unhandled subtarget"); 2290 } 2291 } 2292 2293 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2294 } 2295 2296 // Namespace for x86 abstract base class 2297 const Builtin::Info BuiltinInfo[] = { 2298 #define BUILTIN(ID, TYPE, ATTRS) \ 2299 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2300 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2301 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2302 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2303 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2304 #include "clang/Basic/BuiltinsX86.def" 2305 }; 2306 2307 static const char* const GCCRegNames[] = { 2308 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2309 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2310 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2311 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2312 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2313 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2314 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2315 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2316 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2317 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2318 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2319 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2320 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2321 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2322 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2323 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2324 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2325 }; 2326 2327 const TargetInfo::AddlRegName AddlRegNames[] = { 2328 { { "al", "ah", "eax", "rax" }, 0 }, 2329 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2330 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2331 { { "dl", "dh", "edx", "rdx" }, 1 }, 2332 { { "esi", "rsi" }, 4 }, 2333 { { "edi", "rdi" }, 5 }, 2334 { { "esp", "rsp" }, 7 }, 2335 { { "ebp", "rbp" }, 6 }, 2336 { { "r8d", "r8w", "r8b" }, 38 }, 2337 { { "r9d", "r9w", "r9b" }, 39 }, 2338 { { "r10d", "r10w", "r10b" }, 40 }, 2339 { { "r11d", "r11w", "r11b" }, 41 }, 2340 { { "r12d", "r12w", "r12b" }, 42 }, 2341 { { "r13d", "r13w", "r13b" }, 43 }, 2342 { { "r14d", "r14w", "r14b" }, 44 }, 2343 { { "r15d", "r15w", "r15b" }, 45 }, 2344 }; 2345 2346 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2347 // most of the implementation can be shared. 2348 class X86TargetInfo : public TargetInfo { 2349 enum X86SSEEnum { 2350 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2351 } SSELevel = NoSSE; 2352 enum MMX3DNowEnum { 2353 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2354 } MMX3DNowLevel = NoMMX3DNow; 2355 enum XOPEnum { 2356 NoXOP, 2357 SSE4A, 2358 FMA4, 2359 XOP 2360 } XOPLevel = NoXOP; 2361 2362 bool HasAES = false; 2363 bool HasPCLMUL = false; 2364 bool HasLZCNT = false; 2365 bool HasRDRND = false; 2366 bool HasFSGSBASE = false; 2367 bool HasBMI = false; 2368 bool HasBMI2 = false; 2369 bool HasPOPCNT = false; 2370 bool HasRTM = false; 2371 bool HasPRFCHW = false; 2372 bool HasRDSEED = false; 2373 bool HasADX = false; 2374 bool HasTBM = false; 2375 bool HasFMA = false; 2376 bool HasF16C = false; 2377 bool HasAVX512CD = false; 2378 bool HasAVX512ER = false; 2379 bool HasAVX512PF = false; 2380 bool HasAVX512DQ = false; 2381 bool HasAVX512BW = false; 2382 bool HasAVX512VL = false; 2383 bool HasAVX512VBMI = false; 2384 bool HasAVX512IFMA = false; 2385 bool HasSHA = false; 2386 bool HasMPX = false; 2387 bool HasSGX = false; 2388 bool HasCX16 = false; 2389 bool HasFXSR = false; 2390 bool HasXSAVE = false; 2391 bool HasXSAVEOPT = false; 2392 bool HasXSAVEC = false; 2393 bool HasXSAVES = false; 2394 bool HasMWAITX = false; 2395 bool HasPKU = false; 2396 bool HasCLFLUSHOPT = false; 2397 bool HasPCOMMIT = false; 2398 bool HasCLWB = false; 2399 bool HasUMIP = false; 2400 bool HasMOVBE = false; 2401 bool HasPREFETCHWT1 = false; 2402 2403 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2404 /// 2405 /// Each enumeration represents a particular CPU supported by Clang. These 2406 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2407 enum CPUKind { 2408 CK_Generic, 2409 2410 /// \name i386 2411 /// i386-generation processors. 2412 //@{ 2413 CK_i386, 2414 //@} 2415 2416 /// \name i486 2417 /// i486-generation processors. 2418 //@{ 2419 CK_i486, 2420 CK_WinChipC6, 2421 CK_WinChip2, 2422 CK_C3, 2423 //@} 2424 2425 /// \name i586 2426 /// i586-generation processors, P5 microarchitecture based. 2427 //@{ 2428 CK_i586, 2429 CK_Pentium, 2430 CK_PentiumMMX, 2431 //@} 2432 2433 /// \name i686 2434 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2435 //@{ 2436 CK_i686, 2437 CK_PentiumPro, 2438 CK_Pentium2, 2439 CK_Pentium3, 2440 CK_Pentium3M, 2441 CK_PentiumM, 2442 CK_C3_2, 2443 2444 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2445 /// Clang however has some logic to suport this. 2446 // FIXME: Warn, deprecate, and potentially remove this. 2447 CK_Yonah, 2448 //@} 2449 2450 /// \name Netburst 2451 /// Netburst microarchitecture based processors. 2452 //@{ 2453 CK_Pentium4, 2454 CK_Pentium4M, 2455 CK_Prescott, 2456 CK_Nocona, 2457 //@} 2458 2459 /// \name Core 2460 /// Core microarchitecture based processors. 2461 //@{ 2462 CK_Core2, 2463 2464 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2465 /// codename which GCC no longer accepts as an option to -march, but Clang 2466 /// has some logic for recognizing it. 2467 // FIXME: Warn, deprecate, and potentially remove this. 2468 CK_Penryn, 2469 //@} 2470 2471 /// \name Atom 2472 /// Atom processors 2473 //@{ 2474 CK_Bonnell, 2475 CK_Silvermont, 2476 //@} 2477 2478 /// \name Nehalem 2479 /// Nehalem microarchitecture based processors. 2480 CK_Nehalem, 2481 2482 /// \name Westmere 2483 /// Westmere microarchitecture based processors. 2484 CK_Westmere, 2485 2486 /// \name Sandy Bridge 2487 /// Sandy Bridge microarchitecture based processors. 2488 CK_SandyBridge, 2489 2490 /// \name Ivy Bridge 2491 /// Ivy Bridge microarchitecture based processors. 2492 CK_IvyBridge, 2493 2494 /// \name Haswell 2495 /// Haswell microarchitecture based processors. 2496 CK_Haswell, 2497 2498 /// \name Broadwell 2499 /// Broadwell microarchitecture based processors. 2500 CK_Broadwell, 2501 2502 /// \name Skylake Client 2503 /// Skylake client microarchitecture based processors. 2504 CK_SkylakeClient, 2505 2506 /// \name Skylake Server 2507 /// Skylake server microarchitecture based processors. 2508 CK_SkylakeServer, 2509 2510 /// \name Cannonlake Client 2511 /// Cannonlake client microarchitecture based processors. 2512 CK_Cannonlake, 2513 2514 /// \name Knights Landing 2515 /// Knights Landing processor. 2516 CK_KNL, 2517 2518 /// \name Lakemont 2519 /// Lakemont microarchitecture based processors. 2520 CK_Lakemont, 2521 2522 /// \name K6 2523 /// K6 architecture processors. 2524 //@{ 2525 CK_K6, 2526 CK_K6_2, 2527 CK_K6_3, 2528 //@} 2529 2530 /// \name K7 2531 /// K7 architecture processors. 2532 //@{ 2533 CK_Athlon, 2534 CK_AthlonThunderbird, 2535 CK_Athlon4, 2536 CK_AthlonXP, 2537 CK_AthlonMP, 2538 //@} 2539 2540 /// \name K8 2541 /// K8 architecture processors. 2542 //@{ 2543 CK_Athlon64, 2544 CK_Athlon64SSE3, 2545 CK_AthlonFX, 2546 CK_K8, 2547 CK_K8SSE3, 2548 CK_Opteron, 2549 CK_OpteronSSE3, 2550 CK_AMDFAM10, 2551 //@} 2552 2553 /// \name Bobcat 2554 /// Bobcat architecture processors. 2555 //@{ 2556 CK_BTVER1, 2557 CK_BTVER2, 2558 //@} 2559 2560 /// \name Bulldozer 2561 /// Bulldozer architecture processors. 2562 //@{ 2563 CK_BDVER1, 2564 CK_BDVER2, 2565 CK_BDVER3, 2566 CK_BDVER4, 2567 //@} 2568 2569 /// This specification is deprecated and will be removed in the future. 2570 /// Users should prefer \see CK_K8. 2571 // FIXME: Warn on this when the CPU is set to it. 2572 //@{ 2573 CK_x86_64, 2574 //@} 2575 2576 /// \name Geode 2577 /// Geode processors. 2578 //@{ 2579 CK_Geode 2580 //@} 2581 } CPU = CK_Generic; 2582 2583 CPUKind getCPUKind(StringRef CPU) const { 2584 return llvm::StringSwitch<CPUKind>(CPU) 2585 .Case("i386", CK_i386) 2586 .Case("i486", CK_i486) 2587 .Case("winchip-c6", CK_WinChipC6) 2588 .Case("winchip2", CK_WinChip2) 2589 .Case("c3", CK_C3) 2590 .Case("i586", CK_i586) 2591 .Case("pentium", CK_Pentium) 2592 .Case("pentium-mmx", CK_PentiumMMX) 2593 .Case("i686", CK_i686) 2594 .Case("pentiumpro", CK_PentiumPro) 2595 .Case("pentium2", CK_Pentium2) 2596 .Case("pentium3", CK_Pentium3) 2597 .Case("pentium3m", CK_Pentium3M) 2598 .Case("pentium-m", CK_PentiumM) 2599 .Case("c3-2", CK_C3_2) 2600 .Case("yonah", CK_Yonah) 2601 .Case("pentium4", CK_Pentium4) 2602 .Case("pentium4m", CK_Pentium4M) 2603 .Case("prescott", CK_Prescott) 2604 .Case("nocona", CK_Nocona) 2605 .Case("core2", CK_Core2) 2606 .Case("penryn", CK_Penryn) 2607 .Case("bonnell", CK_Bonnell) 2608 .Case("atom", CK_Bonnell) // Legacy name. 2609 .Case("silvermont", CK_Silvermont) 2610 .Case("slm", CK_Silvermont) // Legacy name. 2611 .Case("nehalem", CK_Nehalem) 2612 .Case("corei7", CK_Nehalem) // Legacy name. 2613 .Case("westmere", CK_Westmere) 2614 .Case("sandybridge", CK_SandyBridge) 2615 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2616 .Case("ivybridge", CK_IvyBridge) 2617 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2618 .Case("haswell", CK_Haswell) 2619 .Case("core-avx2", CK_Haswell) // Legacy name. 2620 .Case("broadwell", CK_Broadwell) 2621 .Case("skylake", CK_SkylakeClient) 2622 .Case("skylake-avx512", CK_SkylakeServer) 2623 .Case("skx", CK_SkylakeServer) // Legacy name. 2624 .Case("cannonlake", CK_Cannonlake) 2625 .Case("knl", CK_KNL) 2626 .Case("lakemont", CK_Lakemont) 2627 .Case("k6", CK_K6) 2628 .Case("k6-2", CK_K6_2) 2629 .Case("k6-3", CK_K6_3) 2630 .Case("athlon", CK_Athlon) 2631 .Case("athlon-tbird", CK_AthlonThunderbird) 2632 .Case("athlon-4", CK_Athlon4) 2633 .Case("athlon-xp", CK_AthlonXP) 2634 .Case("athlon-mp", CK_AthlonMP) 2635 .Case("athlon64", CK_Athlon64) 2636 .Case("athlon64-sse3", CK_Athlon64SSE3) 2637 .Case("athlon-fx", CK_AthlonFX) 2638 .Case("k8", CK_K8) 2639 .Case("k8-sse3", CK_K8SSE3) 2640 .Case("opteron", CK_Opteron) 2641 .Case("opteron-sse3", CK_OpteronSSE3) 2642 .Case("barcelona", CK_AMDFAM10) 2643 .Case("amdfam10", CK_AMDFAM10) 2644 .Case("btver1", CK_BTVER1) 2645 .Case("btver2", CK_BTVER2) 2646 .Case("bdver1", CK_BDVER1) 2647 .Case("bdver2", CK_BDVER2) 2648 .Case("bdver3", CK_BDVER3) 2649 .Case("bdver4", CK_BDVER4) 2650 .Case("x86-64", CK_x86_64) 2651 .Case("geode", CK_Geode) 2652 .Default(CK_Generic); 2653 } 2654 2655 enum FPMathKind { 2656 FP_Default, 2657 FP_SSE, 2658 FP_387 2659 } FPMath = FP_Default; 2660 2661 public: 2662 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2663 : TargetInfo(Triple) { 2664 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2665 } 2666 unsigned getFloatEvalMethod() const override { 2667 // X87 evaluates with 80 bits "long double" precision. 2668 return SSELevel == NoSSE ? 2 : 0; 2669 } 2670 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2671 return llvm::makeArrayRef(BuiltinInfo, 2672 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2673 } 2674 ArrayRef<const char *> getGCCRegNames() const override { 2675 return llvm::makeArrayRef(GCCRegNames); 2676 } 2677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2678 return None; 2679 } 2680 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2681 return llvm::makeArrayRef(AddlRegNames); 2682 } 2683 bool validateCpuSupports(StringRef Name) const override; 2684 bool validateAsmConstraint(const char *&Name, 2685 TargetInfo::ConstraintInfo &info) const override; 2686 2687 bool validateGlobalRegisterVariable(StringRef RegName, 2688 unsigned RegSize, 2689 bool &HasSizeMismatch) const override { 2690 // esp and ebp are the only 32-bit registers the x86 backend can currently 2691 // handle. 2692 if (RegName.equals("esp") || RegName.equals("ebp")) { 2693 // Check that the register size is 32-bit. 2694 HasSizeMismatch = RegSize != 32; 2695 return true; 2696 } 2697 2698 return false; 2699 } 2700 2701 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2702 2703 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2704 2705 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2706 2707 std::string convertConstraint(const char *&Constraint) const override; 2708 const char *getClobbers() const override { 2709 return "~{dirflag},~{fpsr},~{flags}"; 2710 } 2711 void getTargetDefines(const LangOptions &Opts, 2712 MacroBuilder &Builder) const override; 2713 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2714 bool Enabled); 2715 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2716 bool Enabled); 2717 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2718 bool Enabled); 2719 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2720 StringRef Name, bool Enabled) const override { 2721 setFeatureEnabledImpl(Features, Name, Enabled); 2722 } 2723 // This exists purely to cut down on the number of virtual calls in 2724 // initFeatureMap which calls this repeatedly. 2725 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2726 StringRef Name, bool Enabled); 2727 bool 2728 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2729 StringRef CPU, 2730 const std::vector<std::string> &FeaturesVec) const override; 2731 bool hasFeature(StringRef Feature) const override; 2732 bool handleTargetFeatures(std::vector<std::string> &Features, 2733 DiagnosticsEngine &Diags) override; 2734 StringRef getABI() const override { 2735 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2736 return "avx512"; 2737 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2738 return "avx"; 2739 if (getTriple().getArch() == llvm::Triple::x86 && 2740 MMX3DNowLevel == NoMMX3DNow) 2741 return "no-mmx"; 2742 return ""; 2743 } 2744 bool setCPU(const std::string &Name) override { 2745 CPU = getCPUKind(Name); 2746 2747 // Perform any per-CPU checks necessary to determine if this CPU is 2748 // acceptable. 2749 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2750 // invalid without explaining *why*. 2751 switch (CPU) { 2752 case CK_Generic: 2753 // No processor selected! 2754 return false; 2755 2756 case CK_i386: 2757 case CK_i486: 2758 case CK_WinChipC6: 2759 case CK_WinChip2: 2760 case CK_C3: 2761 case CK_i586: 2762 case CK_Pentium: 2763 case CK_PentiumMMX: 2764 case CK_i686: 2765 case CK_PentiumPro: 2766 case CK_Pentium2: 2767 case CK_Pentium3: 2768 case CK_Pentium3M: 2769 case CK_PentiumM: 2770 case CK_Yonah: 2771 case CK_C3_2: 2772 case CK_Pentium4: 2773 case CK_Pentium4M: 2774 case CK_Lakemont: 2775 case CK_Prescott: 2776 case CK_K6: 2777 case CK_K6_2: 2778 case CK_K6_3: 2779 case CK_Athlon: 2780 case CK_AthlonThunderbird: 2781 case CK_Athlon4: 2782 case CK_AthlonXP: 2783 case CK_AthlonMP: 2784 case CK_Geode: 2785 // Only accept certain architectures when compiling in 32-bit mode. 2786 if (getTriple().getArch() != llvm::Triple::x86) 2787 return false; 2788 2789 // Fallthrough 2790 case CK_Nocona: 2791 case CK_Core2: 2792 case CK_Penryn: 2793 case CK_Bonnell: 2794 case CK_Silvermont: 2795 case CK_Nehalem: 2796 case CK_Westmere: 2797 case CK_SandyBridge: 2798 case CK_IvyBridge: 2799 case CK_Haswell: 2800 case CK_Broadwell: 2801 case CK_SkylakeClient: 2802 case CK_SkylakeServer: 2803 case CK_Cannonlake: 2804 case CK_KNL: 2805 case CK_Athlon64: 2806 case CK_Athlon64SSE3: 2807 case CK_AthlonFX: 2808 case CK_K8: 2809 case CK_K8SSE3: 2810 case CK_Opteron: 2811 case CK_OpteronSSE3: 2812 case CK_AMDFAM10: 2813 case CK_BTVER1: 2814 case CK_BTVER2: 2815 case CK_BDVER1: 2816 case CK_BDVER2: 2817 case CK_BDVER3: 2818 case CK_BDVER4: 2819 case CK_x86_64: 2820 return true; 2821 } 2822 llvm_unreachable("Unhandled CPU kind"); 2823 } 2824 2825 bool setFPMath(StringRef Name) override; 2826 2827 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2828 // Most of the non-ARM calling conventions are i386 conventions. 2829 switch (CC) { 2830 case CC_X86ThisCall: 2831 case CC_X86FastCall: 2832 case CC_X86StdCall: 2833 case CC_X86VectorCall: 2834 case CC_C: 2835 case CC_Swift: 2836 case CC_X86Pascal: 2837 case CC_IntelOclBicc: 2838 return CCCR_OK; 2839 default: 2840 return CCCR_Warning; 2841 } 2842 } 2843 2844 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2845 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2846 } 2847 2848 bool hasSjLjLowering() const override { 2849 return true; 2850 } 2851 2852 void setSupportedOpenCLOpts() override { 2853 getSupportedOpenCLOpts().setAll(); 2854 } 2855 }; 2856 2857 bool X86TargetInfo::setFPMath(StringRef Name) { 2858 if (Name == "387") { 2859 FPMath = FP_387; 2860 return true; 2861 } 2862 if (Name == "sse") { 2863 FPMath = FP_SSE; 2864 return true; 2865 } 2866 return false; 2867 } 2868 2869 bool X86TargetInfo::initFeatureMap( 2870 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2871 const std::vector<std::string> &FeaturesVec) const { 2872 // FIXME: This *really* should not be here. 2873 // X86_64 always has SSE2. 2874 if (getTriple().getArch() == llvm::Triple::x86_64) 2875 setFeatureEnabledImpl(Features, "sse2", true); 2876 2877 const CPUKind Kind = getCPUKind(CPU); 2878 2879 // Enable X87 for all X86 processors but Lakemont. 2880 if (Kind != CK_Lakemont) 2881 setFeatureEnabledImpl(Features, "x87", true); 2882 2883 switch (Kind) { 2884 case CK_Generic: 2885 case CK_i386: 2886 case CK_i486: 2887 case CK_i586: 2888 case CK_Pentium: 2889 case CK_i686: 2890 case CK_PentiumPro: 2891 case CK_Lakemont: 2892 break; 2893 case CK_PentiumMMX: 2894 case CK_Pentium2: 2895 case CK_K6: 2896 case CK_WinChipC6: 2897 setFeatureEnabledImpl(Features, "mmx", true); 2898 break; 2899 case CK_Pentium3: 2900 case CK_Pentium3M: 2901 case CK_C3_2: 2902 setFeatureEnabledImpl(Features, "sse", true); 2903 setFeatureEnabledImpl(Features, "fxsr", true); 2904 break; 2905 case CK_PentiumM: 2906 case CK_Pentium4: 2907 case CK_Pentium4M: 2908 case CK_x86_64: 2909 setFeatureEnabledImpl(Features, "sse2", true); 2910 setFeatureEnabledImpl(Features, "fxsr", true); 2911 break; 2912 case CK_Yonah: 2913 case CK_Prescott: 2914 case CK_Nocona: 2915 setFeatureEnabledImpl(Features, "sse3", true); 2916 setFeatureEnabledImpl(Features, "fxsr", true); 2917 setFeatureEnabledImpl(Features, "cx16", true); 2918 break; 2919 case CK_Core2: 2920 case CK_Bonnell: 2921 setFeatureEnabledImpl(Features, "ssse3", true); 2922 setFeatureEnabledImpl(Features, "fxsr", true); 2923 setFeatureEnabledImpl(Features, "cx16", true); 2924 break; 2925 case CK_Penryn: 2926 setFeatureEnabledImpl(Features, "sse4.1", true); 2927 setFeatureEnabledImpl(Features, "fxsr", true); 2928 setFeatureEnabledImpl(Features, "cx16", true); 2929 break; 2930 case CK_Cannonlake: 2931 setFeatureEnabledImpl(Features, "avx512ifma", true); 2932 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2933 setFeatureEnabledImpl(Features, "sha", true); 2934 setFeatureEnabledImpl(Features, "umip", true); 2935 // FALLTHROUGH 2936 case CK_SkylakeServer: 2937 setFeatureEnabledImpl(Features, "avx512f", true); 2938 setFeatureEnabledImpl(Features, "avx512cd", true); 2939 setFeatureEnabledImpl(Features, "avx512dq", true); 2940 setFeatureEnabledImpl(Features, "avx512bw", true); 2941 setFeatureEnabledImpl(Features, "avx512vl", true); 2942 setFeatureEnabledImpl(Features, "pku", true); 2943 setFeatureEnabledImpl(Features, "pcommit", true); 2944 setFeatureEnabledImpl(Features, "clwb", true); 2945 // FALLTHROUGH 2946 case CK_SkylakeClient: 2947 setFeatureEnabledImpl(Features, "xsavec", true); 2948 setFeatureEnabledImpl(Features, "xsaves", true); 2949 setFeatureEnabledImpl(Features, "mpx", true); 2950 setFeatureEnabledImpl(Features, "sgx", true); 2951 setFeatureEnabledImpl(Features, "clflushopt", true); 2952 // FALLTHROUGH 2953 case CK_Broadwell: 2954 setFeatureEnabledImpl(Features, "rdseed", true); 2955 setFeatureEnabledImpl(Features, "adx", true); 2956 // FALLTHROUGH 2957 case CK_Haswell: 2958 setFeatureEnabledImpl(Features, "avx2", true); 2959 setFeatureEnabledImpl(Features, "lzcnt", true); 2960 setFeatureEnabledImpl(Features, "bmi", true); 2961 setFeatureEnabledImpl(Features, "bmi2", true); 2962 setFeatureEnabledImpl(Features, "rtm", true); 2963 setFeatureEnabledImpl(Features, "fma", true); 2964 setFeatureEnabledImpl(Features, "movbe", true); 2965 // FALLTHROUGH 2966 case CK_IvyBridge: 2967 setFeatureEnabledImpl(Features, "rdrnd", true); 2968 setFeatureEnabledImpl(Features, "f16c", true); 2969 setFeatureEnabledImpl(Features, "fsgsbase", true); 2970 // FALLTHROUGH 2971 case CK_SandyBridge: 2972 setFeatureEnabledImpl(Features, "avx", true); 2973 setFeatureEnabledImpl(Features, "xsave", true); 2974 setFeatureEnabledImpl(Features, "xsaveopt", true); 2975 // FALLTHROUGH 2976 case CK_Westmere: 2977 case CK_Silvermont: 2978 setFeatureEnabledImpl(Features, "aes", true); 2979 setFeatureEnabledImpl(Features, "pclmul", true); 2980 // FALLTHROUGH 2981 case CK_Nehalem: 2982 setFeatureEnabledImpl(Features, "sse4.2", true); 2983 setFeatureEnabledImpl(Features, "fxsr", true); 2984 setFeatureEnabledImpl(Features, "cx16", true); 2985 break; 2986 case CK_KNL: 2987 setFeatureEnabledImpl(Features, "avx512f", true); 2988 setFeatureEnabledImpl(Features, "avx512cd", true); 2989 setFeatureEnabledImpl(Features, "avx512er", true); 2990 setFeatureEnabledImpl(Features, "avx512pf", true); 2991 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2992 setFeatureEnabledImpl(Features, "fxsr", true); 2993 setFeatureEnabledImpl(Features, "rdseed", true); 2994 setFeatureEnabledImpl(Features, "adx", true); 2995 setFeatureEnabledImpl(Features, "lzcnt", true); 2996 setFeatureEnabledImpl(Features, "bmi", true); 2997 setFeatureEnabledImpl(Features, "bmi2", true); 2998 setFeatureEnabledImpl(Features, "rtm", true); 2999 setFeatureEnabledImpl(Features, "fma", true); 3000 setFeatureEnabledImpl(Features, "rdrnd", true); 3001 setFeatureEnabledImpl(Features, "f16c", true); 3002 setFeatureEnabledImpl(Features, "fsgsbase", true); 3003 setFeatureEnabledImpl(Features, "aes", true); 3004 setFeatureEnabledImpl(Features, "pclmul", true); 3005 setFeatureEnabledImpl(Features, "cx16", true); 3006 setFeatureEnabledImpl(Features, "xsaveopt", true); 3007 setFeatureEnabledImpl(Features, "xsave", true); 3008 setFeatureEnabledImpl(Features, "movbe", true); 3009 break; 3010 case CK_K6_2: 3011 case CK_K6_3: 3012 case CK_WinChip2: 3013 case CK_C3: 3014 setFeatureEnabledImpl(Features, "3dnow", true); 3015 break; 3016 case CK_Athlon: 3017 case CK_AthlonThunderbird: 3018 case CK_Geode: 3019 setFeatureEnabledImpl(Features, "3dnowa", true); 3020 break; 3021 case CK_Athlon4: 3022 case CK_AthlonXP: 3023 case CK_AthlonMP: 3024 setFeatureEnabledImpl(Features, "sse", true); 3025 setFeatureEnabledImpl(Features, "3dnowa", true); 3026 setFeatureEnabledImpl(Features, "fxsr", true); 3027 break; 3028 case CK_K8: 3029 case CK_Opteron: 3030 case CK_Athlon64: 3031 case CK_AthlonFX: 3032 setFeatureEnabledImpl(Features, "sse2", true); 3033 setFeatureEnabledImpl(Features, "3dnowa", true); 3034 setFeatureEnabledImpl(Features, "fxsr", true); 3035 break; 3036 case CK_AMDFAM10: 3037 setFeatureEnabledImpl(Features, "sse4a", true); 3038 setFeatureEnabledImpl(Features, "lzcnt", true); 3039 setFeatureEnabledImpl(Features, "popcnt", true); 3040 // FALLTHROUGH 3041 case CK_K8SSE3: 3042 case CK_OpteronSSE3: 3043 case CK_Athlon64SSE3: 3044 setFeatureEnabledImpl(Features, "sse3", true); 3045 setFeatureEnabledImpl(Features, "3dnowa", true); 3046 setFeatureEnabledImpl(Features, "fxsr", true); 3047 break; 3048 case CK_BTVER2: 3049 setFeatureEnabledImpl(Features, "avx", true); 3050 setFeatureEnabledImpl(Features, "aes", true); 3051 setFeatureEnabledImpl(Features, "pclmul", true); 3052 setFeatureEnabledImpl(Features, "bmi", true); 3053 setFeatureEnabledImpl(Features, "f16c", true); 3054 setFeatureEnabledImpl(Features, "xsaveopt", true); 3055 // FALLTHROUGH 3056 case CK_BTVER1: 3057 setFeatureEnabledImpl(Features, "ssse3", true); 3058 setFeatureEnabledImpl(Features, "sse4a", true); 3059 setFeatureEnabledImpl(Features, "lzcnt", true); 3060 setFeatureEnabledImpl(Features, "popcnt", true); 3061 setFeatureEnabledImpl(Features, "prfchw", true); 3062 setFeatureEnabledImpl(Features, "cx16", true); 3063 setFeatureEnabledImpl(Features, "fxsr", true); 3064 break; 3065 case CK_BDVER4: 3066 setFeatureEnabledImpl(Features, "avx2", true); 3067 setFeatureEnabledImpl(Features, "bmi2", true); 3068 setFeatureEnabledImpl(Features, "mwaitx", true); 3069 // FALLTHROUGH 3070 case CK_BDVER3: 3071 setFeatureEnabledImpl(Features, "fsgsbase", true); 3072 setFeatureEnabledImpl(Features, "xsaveopt", true); 3073 // FALLTHROUGH 3074 case CK_BDVER2: 3075 setFeatureEnabledImpl(Features, "bmi", true); 3076 setFeatureEnabledImpl(Features, "fma", true); 3077 setFeatureEnabledImpl(Features, "f16c", true); 3078 setFeatureEnabledImpl(Features, "tbm", true); 3079 // FALLTHROUGH 3080 case CK_BDVER1: 3081 // xop implies avx, sse4a and fma4. 3082 setFeatureEnabledImpl(Features, "xop", true); 3083 setFeatureEnabledImpl(Features, "lzcnt", true); 3084 setFeatureEnabledImpl(Features, "aes", true); 3085 setFeatureEnabledImpl(Features, "pclmul", true); 3086 setFeatureEnabledImpl(Features, "prfchw", true); 3087 setFeatureEnabledImpl(Features, "cx16", true); 3088 setFeatureEnabledImpl(Features, "fxsr", true); 3089 setFeatureEnabledImpl(Features, "xsave", true); 3090 break; 3091 } 3092 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3093 return false; 3094 3095 // Can't do this earlier because we need to be able to explicitly enable 3096 // or disable these features and the things that they depend upon. 3097 3098 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3099 auto I = Features.find("sse4.2"); 3100 if (I != Features.end() && I->getValue() && 3101 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3102 FeaturesVec.end()) 3103 Features["popcnt"] = true; 3104 3105 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3106 I = Features.find("3dnow"); 3107 if (I != Features.end() && I->getValue() && 3108 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3109 FeaturesVec.end()) 3110 Features["prfchw"] = true; 3111 3112 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3113 // then enable MMX. 3114 I = Features.find("sse"); 3115 if (I != Features.end() && I->getValue() && 3116 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3117 FeaturesVec.end()) 3118 Features["mmx"] = true; 3119 3120 return true; 3121 } 3122 3123 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3124 X86SSEEnum Level, bool Enabled) { 3125 if (Enabled) { 3126 switch (Level) { 3127 case AVX512F: 3128 Features["avx512f"] = true; 3129 case AVX2: 3130 Features["avx2"] = true; 3131 case AVX: 3132 Features["avx"] = true; 3133 Features["xsave"] = true; 3134 case SSE42: 3135 Features["sse4.2"] = true; 3136 case SSE41: 3137 Features["sse4.1"] = true; 3138 case SSSE3: 3139 Features["ssse3"] = true; 3140 case SSE3: 3141 Features["sse3"] = true; 3142 case SSE2: 3143 Features["sse2"] = true; 3144 case SSE1: 3145 Features["sse"] = true; 3146 case NoSSE: 3147 break; 3148 } 3149 return; 3150 } 3151 3152 switch (Level) { 3153 case NoSSE: 3154 case SSE1: 3155 Features["sse"] = false; 3156 case SSE2: 3157 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3158 Features["sha"] = false; 3159 case SSE3: 3160 Features["sse3"] = false; 3161 setXOPLevel(Features, NoXOP, false); 3162 case SSSE3: 3163 Features["ssse3"] = false; 3164 case SSE41: 3165 Features["sse4.1"] = false; 3166 case SSE42: 3167 Features["sse4.2"] = false; 3168 case AVX: 3169 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3170 Features["xsaveopt"] = false; 3171 setXOPLevel(Features, FMA4, false); 3172 case AVX2: 3173 Features["avx2"] = false; 3174 case AVX512F: 3175 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3176 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3177 Features["avx512vl"] = Features["avx512vbmi"] = 3178 Features["avx512ifma"] = false; 3179 } 3180 } 3181 3182 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3183 MMX3DNowEnum Level, bool Enabled) { 3184 if (Enabled) { 3185 switch (Level) { 3186 case AMD3DNowAthlon: 3187 Features["3dnowa"] = true; 3188 case AMD3DNow: 3189 Features["3dnow"] = true; 3190 case MMX: 3191 Features["mmx"] = true; 3192 case NoMMX3DNow: 3193 break; 3194 } 3195 return; 3196 } 3197 3198 switch (Level) { 3199 case NoMMX3DNow: 3200 case MMX: 3201 Features["mmx"] = false; 3202 case AMD3DNow: 3203 Features["3dnow"] = false; 3204 case AMD3DNowAthlon: 3205 Features["3dnowa"] = false; 3206 } 3207 } 3208 3209 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3210 bool Enabled) { 3211 if (Enabled) { 3212 switch (Level) { 3213 case XOP: 3214 Features["xop"] = true; 3215 case FMA4: 3216 Features["fma4"] = true; 3217 setSSELevel(Features, AVX, true); 3218 case SSE4A: 3219 Features["sse4a"] = true; 3220 setSSELevel(Features, SSE3, true); 3221 case NoXOP: 3222 break; 3223 } 3224 return; 3225 } 3226 3227 switch (Level) { 3228 case NoXOP: 3229 case SSE4A: 3230 Features["sse4a"] = false; 3231 case FMA4: 3232 Features["fma4"] = false; 3233 case XOP: 3234 Features["xop"] = false; 3235 } 3236 } 3237 3238 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3239 StringRef Name, bool Enabled) { 3240 // This is a bit of a hack to deal with the sse4 target feature when used 3241 // as part of the target attribute. We handle sse4 correctly everywhere 3242 // else. See below for more information on how we handle the sse4 options. 3243 if (Name != "sse4") 3244 Features[Name] = Enabled; 3245 3246 if (Name == "mmx") { 3247 setMMXLevel(Features, MMX, Enabled); 3248 } else if (Name == "sse") { 3249 setSSELevel(Features, SSE1, Enabled); 3250 } else if (Name == "sse2") { 3251 setSSELevel(Features, SSE2, Enabled); 3252 } else if (Name == "sse3") { 3253 setSSELevel(Features, SSE3, Enabled); 3254 } else if (Name == "ssse3") { 3255 setSSELevel(Features, SSSE3, Enabled); 3256 } else if (Name == "sse4.2") { 3257 setSSELevel(Features, SSE42, Enabled); 3258 } else if (Name == "sse4.1") { 3259 setSSELevel(Features, SSE41, Enabled); 3260 } else if (Name == "3dnow") { 3261 setMMXLevel(Features, AMD3DNow, Enabled); 3262 } else if (Name == "3dnowa") { 3263 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3264 } else if (Name == "aes") { 3265 if (Enabled) 3266 setSSELevel(Features, SSE2, Enabled); 3267 } else if (Name == "pclmul") { 3268 if (Enabled) 3269 setSSELevel(Features, SSE2, Enabled); 3270 } else if (Name == "avx") { 3271 setSSELevel(Features, AVX, Enabled); 3272 } else if (Name == "avx2") { 3273 setSSELevel(Features, AVX2, Enabled); 3274 } else if (Name == "avx512f") { 3275 setSSELevel(Features, AVX512F, Enabled); 3276 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3277 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3278 Name == "avx512vbmi" || Name == "avx512ifma") { 3279 if (Enabled) 3280 setSSELevel(Features, AVX512F, Enabled); 3281 } else if (Name == "fma") { 3282 if (Enabled) 3283 setSSELevel(Features, AVX, Enabled); 3284 } else if (Name == "fma4") { 3285 setXOPLevel(Features, FMA4, Enabled); 3286 } else if (Name == "xop") { 3287 setXOPLevel(Features, XOP, Enabled); 3288 } else if (Name == "sse4a") { 3289 setXOPLevel(Features, SSE4A, Enabled); 3290 } else if (Name == "f16c") { 3291 if (Enabled) 3292 setSSELevel(Features, AVX, Enabled); 3293 } else if (Name == "sha") { 3294 if (Enabled) 3295 setSSELevel(Features, SSE2, Enabled); 3296 } else if (Name == "sse4") { 3297 // We can get here via the __target__ attribute since that's not controlled 3298 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3299 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3300 // disabled. 3301 if (Enabled) 3302 setSSELevel(Features, SSE42, Enabled); 3303 else 3304 setSSELevel(Features, SSE41, Enabled); 3305 } else if (Name == "xsave") { 3306 if (!Enabled) 3307 Features["xsaveopt"] = false; 3308 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3309 if (Enabled) 3310 Features["xsave"] = true; 3311 } 3312 } 3313 3314 /// handleTargetFeatures - Perform initialization based on the user 3315 /// configured set of features. 3316 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3317 DiagnosticsEngine &Diags) { 3318 for (const auto &Feature : Features) { 3319 if (Feature[0] != '+') 3320 continue; 3321 3322 if (Feature == "+aes") { 3323 HasAES = true; 3324 } else if (Feature == "+pclmul") { 3325 HasPCLMUL = true; 3326 } else if (Feature == "+lzcnt") { 3327 HasLZCNT = true; 3328 } else if (Feature == "+rdrnd") { 3329 HasRDRND = true; 3330 } else if (Feature == "+fsgsbase") { 3331 HasFSGSBASE = true; 3332 } else if (Feature == "+bmi") { 3333 HasBMI = true; 3334 } else if (Feature == "+bmi2") { 3335 HasBMI2 = true; 3336 } else if (Feature == "+popcnt") { 3337 HasPOPCNT = true; 3338 } else if (Feature == "+rtm") { 3339 HasRTM = true; 3340 } else if (Feature == "+prfchw") { 3341 HasPRFCHW = true; 3342 } else if (Feature == "+rdseed") { 3343 HasRDSEED = true; 3344 } else if (Feature == "+adx") { 3345 HasADX = true; 3346 } else if (Feature == "+tbm") { 3347 HasTBM = true; 3348 } else if (Feature == "+fma") { 3349 HasFMA = true; 3350 } else if (Feature == "+f16c") { 3351 HasF16C = true; 3352 } else if (Feature == "+avx512cd") { 3353 HasAVX512CD = true; 3354 } else if (Feature == "+avx512er") { 3355 HasAVX512ER = true; 3356 } else if (Feature == "+avx512pf") { 3357 HasAVX512PF = true; 3358 } else if (Feature == "+avx512dq") { 3359 HasAVX512DQ = true; 3360 } else if (Feature == "+avx512bw") { 3361 HasAVX512BW = true; 3362 } else if (Feature == "+avx512vl") { 3363 HasAVX512VL = true; 3364 } else if (Feature == "+avx512vbmi") { 3365 HasAVX512VBMI = true; 3366 } else if (Feature == "+avx512ifma") { 3367 HasAVX512IFMA = true; 3368 } else if (Feature == "+sha") { 3369 HasSHA = true; 3370 } else if (Feature == "+mpx") { 3371 HasMPX = true; 3372 } else if (Feature == "+movbe") { 3373 HasMOVBE = true; 3374 } else if (Feature == "+sgx") { 3375 HasSGX = true; 3376 } else if (Feature == "+cx16") { 3377 HasCX16 = true; 3378 } else if (Feature == "+fxsr") { 3379 HasFXSR = true; 3380 } else if (Feature == "+xsave") { 3381 HasXSAVE = true; 3382 } else if (Feature == "+xsaveopt") { 3383 HasXSAVEOPT = true; 3384 } else if (Feature == "+xsavec") { 3385 HasXSAVEC = true; 3386 } else if (Feature == "+xsaves") { 3387 HasXSAVES = true; 3388 } else if (Feature == "+mwaitx") { 3389 HasMWAITX = true; 3390 } else if (Feature == "+pku") { 3391 HasPKU = true; 3392 } else if (Feature == "+clflushopt") { 3393 HasCLFLUSHOPT = true; 3394 } else if (Feature == "+pcommit") { 3395 HasPCOMMIT = true; 3396 } else if (Feature == "+clwb") { 3397 HasCLWB = true; 3398 } else if (Feature == "+umip") { 3399 HasUMIP = true; 3400 } else if (Feature == "+prefetchwt1") { 3401 HasPREFETCHWT1 = true; 3402 } 3403 3404 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3405 .Case("+avx512f", AVX512F) 3406 .Case("+avx2", AVX2) 3407 .Case("+avx", AVX) 3408 .Case("+sse4.2", SSE42) 3409 .Case("+sse4.1", SSE41) 3410 .Case("+ssse3", SSSE3) 3411 .Case("+sse3", SSE3) 3412 .Case("+sse2", SSE2) 3413 .Case("+sse", SSE1) 3414 .Default(NoSSE); 3415 SSELevel = std::max(SSELevel, Level); 3416 3417 MMX3DNowEnum ThreeDNowLevel = 3418 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3419 .Case("+3dnowa", AMD3DNowAthlon) 3420 .Case("+3dnow", AMD3DNow) 3421 .Case("+mmx", MMX) 3422 .Default(NoMMX3DNow); 3423 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3424 3425 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3426 .Case("+xop", XOP) 3427 .Case("+fma4", FMA4) 3428 .Case("+sse4a", SSE4A) 3429 .Default(NoXOP); 3430 XOPLevel = std::max(XOPLevel, XLevel); 3431 } 3432 3433 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3434 // matches the selected sse level. 3435 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3436 (FPMath == FP_387 && SSELevel >= SSE1)) { 3437 Diags.Report(diag::err_target_unsupported_fpmath) << 3438 (FPMath == FP_SSE ? "sse" : "387"); 3439 return false; 3440 } 3441 3442 SimdDefaultAlign = 3443 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3444 return true; 3445 } 3446 3447 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3448 /// definitions for this particular subtarget. 3449 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3450 MacroBuilder &Builder) const { 3451 // Target identification. 3452 if (getTriple().getArch() == llvm::Triple::x86_64) { 3453 Builder.defineMacro("__amd64__"); 3454 Builder.defineMacro("__amd64"); 3455 Builder.defineMacro("__x86_64"); 3456 Builder.defineMacro("__x86_64__"); 3457 if (getTriple().getArchName() == "x86_64h") { 3458 Builder.defineMacro("__x86_64h"); 3459 Builder.defineMacro("__x86_64h__"); 3460 } 3461 } else { 3462 DefineStd(Builder, "i386", Opts); 3463 } 3464 3465 // Subtarget options. 3466 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3467 // truly should be based on -mtune options. 3468 switch (CPU) { 3469 case CK_Generic: 3470 break; 3471 case CK_i386: 3472 // The rest are coming from the i386 define above. 3473 Builder.defineMacro("__tune_i386__"); 3474 break; 3475 case CK_i486: 3476 case CK_WinChipC6: 3477 case CK_WinChip2: 3478 case CK_C3: 3479 defineCPUMacros(Builder, "i486"); 3480 break; 3481 case CK_PentiumMMX: 3482 Builder.defineMacro("__pentium_mmx__"); 3483 Builder.defineMacro("__tune_pentium_mmx__"); 3484 // Fallthrough 3485 case CK_i586: 3486 case CK_Pentium: 3487 defineCPUMacros(Builder, "i586"); 3488 defineCPUMacros(Builder, "pentium"); 3489 break; 3490 case CK_Pentium3: 3491 case CK_Pentium3M: 3492 case CK_PentiumM: 3493 Builder.defineMacro("__tune_pentium3__"); 3494 // Fallthrough 3495 case CK_Pentium2: 3496 case CK_C3_2: 3497 Builder.defineMacro("__tune_pentium2__"); 3498 // Fallthrough 3499 case CK_PentiumPro: 3500 Builder.defineMacro("__tune_i686__"); 3501 Builder.defineMacro("__tune_pentiumpro__"); 3502 // Fallthrough 3503 case CK_i686: 3504 Builder.defineMacro("__i686"); 3505 Builder.defineMacro("__i686__"); 3506 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3507 Builder.defineMacro("__pentiumpro"); 3508 Builder.defineMacro("__pentiumpro__"); 3509 break; 3510 case CK_Pentium4: 3511 case CK_Pentium4M: 3512 defineCPUMacros(Builder, "pentium4"); 3513 break; 3514 case CK_Yonah: 3515 case CK_Prescott: 3516 case CK_Nocona: 3517 defineCPUMacros(Builder, "nocona"); 3518 break; 3519 case CK_Core2: 3520 case CK_Penryn: 3521 defineCPUMacros(Builder, "core2"); 3522 break; 3523 case CK_Bonnell: 3524 defineCPUMacros(Builder, "atom"); 3525 break; 3526 case CK_Silvermont: 3527 defineCPUMacros(Builder, "slm"); 3528 break; 3529 case CK_Nehalem: 3530 case CK_Westmere: 3531 case CK_SandyBridge: 3532 case CK_IvyBridge: 3533 case CK_Haswell: 3534 case CK_Broadwell: 3535 case CK_SkylakeClient: 3536 // FIXME: Historically, we defined this legacy name, it would be nice to 3537 // remove it at some point. We've never exposed fine-grained names for 3538 // recent primary x86 CPUs, and we should keep it that way. 3539 defineCPUMacros(Builder, "corei7"); 3540 break; 3541 case CK_SkylakeServer: 3542 defineCPUMacros(Builder, "skx"); 3543 break; 3544 case CK_Cannonlake: 3545 break; 3546 case CK_KNL: 3547 defineCPUMacros(Builder, "knl"); 3548 break; 3549 case CK_Lakemont: 3550 Builder.defineMacro("__tune_lakemont__"); 3551 break; 3552 case CK_K6_2: 3553 Builder.defineMacro("__k6_2__"); 3554 Builder.defineMacro("__tune_k6_2__"); 3555 // Fallthrough 3556 case CK_K6_3: 3557 if (CPU != CK_K6_2) { // In case of fallthrough 3558 // FIXME: GCC may be enabling these in cases where some other k6 3559 // architecture is specified but -m3dnow is explicitly provided. The 3560 // exact semantics need to be determined and emulated here. 3561 Builder.defineMacro("__k6_3__"); 3562 Builder.defineMacro("__tune_k6_3__"); 3563 } 3564 // Fallthrough 3565 case CK_K6: 3566 defineCPUMacros(Builder, "k6"); 3567 break; 3568 case CK_Athlon: 3569 case CK_AthlonThunderbird: 3570 case CK_Athlon4: 3571 case CK_AthlonXP: 3572 case CK_AthlonMP: 3573 defineCPUMacros(Builder, "athlon"); 3574 if (SSELevel != NoSSE) { 3575 Builder.defineMacro("__athlon_sse__"); 3576 Builder.defineMacro("__tune_athlon_sse__"); 3577 } 3578 break; 3579 case CK_K8: 3580 case CK_K8SSE3: 3581 case CK_x86_64: 3582 case CK_Opteron: 3583 case CK_OpteronSSE3: 3584 case CK_Athlon64: 3585 case CK_Athlon64SSE3: 3586 case CK_AthlonFX: 3587 defineCPUMacros(Builder, "k8"); 3588 break; 3589 case CK_AMDFAM10: 3590 defineCPUMacros(Builder, "amdfam10"); 3591 break; 3592 case CK_BTVER1: 3593 defineCPUMacros(Builder, "btver1"); 3594 break; 3595 case CK_BTVER2: 3596 defineCPUMacros(Builder, "btver2"); 3597 break; 3598 case CK_BDVER1: 3599 defineCPUMacros(Builder, "bdver1"); 3600 break; 3601 case CK_BDVER2: 3602 defineCPUMacros(Builder, "bdver2"); 3603 break; 3604 case CK_BDVER3: 3605 defineCPUMacros(Builder, "bdver3"); 3606 break; 3607 case CK_BDVER4: 3608 defineCPUMacros(Builder, "bdver4"); 3609 break; 3610 case CK_Geode: 3611 defineCPUMacros(Builder, "geode"); 3612 break; 3613 } 3614 3615 // Target properties. 3616 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3617 3618 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3619 // functions in glibc header files that use FP Stack inline asm which the 3620 // backend can't deal with (PR879). 3621 Builder.defineMacro("__NO_MATH_INLINES"); 3622 3623 if (HasAES) 3624 Builder.defineMacro("__AES__"); 3625 3626 if (HasPCLMUL) 3627 Builder.defineMacro("__PCLMUL__"); 3628 3629 if (HasLZCNT) 3630 Builder.defineMacro("__LZCNT__"); 3631 3632 if (HasRDRND) 3633 Builder.defineMacro("__RDRND__"); 3634 3635 if (HasFSGSBASE) 3636 Builder.defineMacro("__FSGSBASE__"); 3637 3638 if (HasBMI) 3639 Builder.defineMacro("__BMI__"); 3640 3641 if (HasBMI2) 3642 Builder.defineMacro("__BMI2__"); 3643 3644 if (HasPOPCNT) 3645 Builder.defineMacro("__POPCNT__"); 3646 3647 if (HasRTM) 3648 Builder.defineMacro("__RTM__"); 3649 3650 if (HasPRFCHW) 3651 Builder.defineMacro("__PRFCHW__"); 3652 3653 if (HasRDSEED) 3654 Builder.defineMacro("__RDSEED__"); 3655 3656 if (HasADX) 3657 Builder.defineMacro("__ADX__"); 3658 3659 if (HasTBM) 3660 Builder.defineMacro("__TBM__"); 3661 3662 if (HasMWAITX) 3663 Builder.defineMacro("__MWAITX__"); 3664 3665 switch (XOPLevel) { 3666 case XOP: 3667 Builder.defineMacro("__XOP__"); 3668 case FMA4: 3669 Builder.defineMacro("__FMA4__"); 3670 case SSE4A: 3671 Builder.defineMacro("__SSE4A__"); 3672 case NoXOP: 3673 break; 3674 } 3675 3676 if (HasFMA) 3677 Builder.defineMacro("__FMA__"); 3678 3679 if (HasF16C) 3680 Builder.defineMacro("__F16C__"); 3681 3682 if (HasAVX512CD) 3683 Builder.defineMacro("__AVX512CD__"); 3684 if (HasAVX512ER) 3685 Builder.defineMacro("__AVX512ER__"); 3686 if (HasAVX512PF) 3687 Builder.defineMacro("__AVX512PF__"); 3688 if (HasAVX512DQ) 3689 Builder.defineMacro("__AVX512DQ__"); 3690 if (HasAVX512BW) 3691 Builder.defineMacro("__AVX512BW__"); 3692 if (HasAVX512VL) 3693 Builder.defineMacro("__AVX512VL__"); 3694 if (HasAVX512VBMI) 3695 Builder.defineMacro("__AVX512VBMI__"); 3696 if (HasAVX512IFMA) 3697 Builder.defineMacro("__AVX512IFMA__"); 3698 3699 if (HasSHA) 3700 Builder.defineMacro("__SHA__"); 3701 3702 if (HasFXSR) 3703 Builder.defineMacro("__FXSR__"); 3704 if (HasXSAVE) 3705 Builder.defineMacro("__XSAVE__"); 3706 if (HasXSAVEOPT) 3707 Builder.defineMacro("__XSAVEOPT__"); 3708 if (HasXSAVEC) 3709 Builder.defineMacro("__XSAVEC__"); 3710 if (HasXSAVES) 3711 Builder.defineMacro("__XSAVES__"); 3712 if (HasPKU) 3713 Builder.defineMacro("__PKU__"); 3714 if (HasCX16) 3715 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3716 3717 // Each case falls through to the previous one here. 3718 switch (SSELevel) { 3719 case AVX512F: 3720 Builder.defineMacro("__AVX512F__"); 3721 case AVX2: 3722 Builder.defineMacro("__AVX2__"); 3723 case AVX: 3724 Builder.defineMacro("__AVX__"); 3725 case SSE42: 3726 Builder.defineMacro("__SSE4_2__"); 3727 case SSE41: 3728 Builder.defineMacro("__SSE4_1__"); 3729 case SSSE3: 3730 Builder.defineMacro("__SSSE3__"); 3731 case SSE3: 3732 Builder.defineMacro("__SSE3__"); 3733 case SSE2: 3734 Builder.defineMacro("__SSE2__"); 3735 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3736 case SSE1: 3737 Builder.defineMacro("__SSE__"); 3738 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3739 case NoSSE: 3740 break; 3741 } 3742 3743 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3744 switch (SSELevel) { 3745 case AVX512F: 3746 case AVX2: 3747 case AVX: 3748 case SSE42: 3749 case SSE41: 3750 case SSSE3: 3751 case SSE3: 3752 case SSE2: 3753 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3754 break; 3755 case SSE1: 3756 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3757 break; 3758 default: 3759 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3760 } 3761 } 3762 3763 // Each case falls through to the previous one here. 3764 switch (MMX3DNowLevel) { 3765 case AMD3DNowAthlon: 3766 Builder.defineMacro("__3dNOW_A__"); 3767 case AMD3DNow: 3768 Builder.defineMacro("__3dNOW__"); 3769 case MMX: 3770 Builder.defineMacro("__MMX__"); 3771 case NoMMX3DNow: 3772 break; 3773 } 3774 3775 if (CPU >= CK_i486) { 3776 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3777 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3778 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3779 } 3780 if (CPU >= CK_i586) 3781 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3782 } 3783 3784 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3785 return llvm::StringSwitch<bool>(Feature) 3786 .Case("aes", HasAES) 3787 .Case("avx", SSELevel >= AVX) 3788 .Case("avx2", SSELevel >= AVX2) 3789 .Case("avx512f", SSELevel >= AVX512F) 3790 .Case("avx512cd", HasAVX512CD) 3791 .Case("avx512er", HasAVX512ER) 3792 .Case("avx512pf", HasAVX512PF) 3793 .Case("avx512dq", HasAVX512DQ) 3794 .Case("avx512bw", HasAVX512BW) 3795 .Case("avx512vl", HasAVX512VL) 3796 .Case("avx512vbmi", HasAVX512VBMI) 3797 .Case("avx512ifma", HasAVX512IFMA) 3798 .Case("bmi", HasBMI) 3799 .Case("bmi2", HasBMI2) 3800 .Case("clflushopt", HasCLFLUSHOPT) 3801 .Case("clwb", HasCLWB) 3802 .Case("cx16", HasCX16) 3803 .Case("f16c", HasF16C) 3804 .Case("fma", HasFMA) 3805 .Case("fma4", XOPLevel >= FMA4) 3806 .Case("fsgsbase", HasFSGSBASE) 3807 .Case("fxsr", HasFXSR) 3808 .Case("lzcnt", HasLZCNT) 3809 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3810 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3811 .Case("mmx", MMX3DNowLevel >= MMX) 3812 .Case("movbe", HasMOVBE) 3813 .Case("mpx", HasMPX) 3814 .Case("pclmul", HasPCLMUL) 3815 .Case("pcommit", HasPCOMMIT) 3816 .Case("pku", HasPKU) 3817 .Case("popcnt", HasPOPCNT) 3818 .Case("prefetchwt1", HasPREFETCHWT1) 3819 .Case("prfchw", HasPRFCHW) 3820 .Case("rdrnd", HasRDRND) 3821 .Case("rdseed", HasRDSEED) 3822 .Case("rtm", HasRTM) 3823 .Case("sgx", HasSGX) 3824 .Case("sha", HasSHA) 3825 .Case("sse", SSELevel >= SSE1) 3826 .Case("sse2", SSELevel >= SSE2) 3827 .Case("sse3", SSELevel >= SSE3) 3828 .Case("ssse3", SSELevel >= SSSE3) 3829 .Case("sse4.1", SSELevel >= SSE41) 3830 .Case("sse4.2", SSELevel >= SSE42) 3831 .Case("sse4a", XOPLevel >= SSE4A) 3832 .Case("tbm", HasTBM) 3833 .Case("umip", HasUMIP) 3834 .Case("x86", true) 3835 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3836 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3837 .Case("xop", XOPLevel >= XOP) 3838 .Case("xsave", HasXSAVE) 3839 .Case("xsavec", HasXSAVEC) 3840 .Case("xsaves", HasXSAVES) 3841 .Case("xsaveopt", HasXSAVEOPT) 3842 .Default(false); 3843 } 3844 3845 // We can't use a generic validation scheme for the features accepted here 3846 // versus subtarget features accepted in the target attribute because the 3847 // bitfield structure that's initialized in the runtime only supports the 3848 // below currently rather than the full range of subtarget features. (See 3849 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3850 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3851 return llvm::StringSwitch<bool>(FeatureStr) 3852 .Case("cmov", true) 3853 .Case("mmx", true) 3854 .Case("popcnt", true) 3855 .Case("sse", true) 3856 .Case("sse2", true) 3857 .Case("sse3", true) 3858 .Case("ssse3", true) 3859 .Case("sse4.1", true) 3860 .Case("sse4.2", true) 3861 .Case("avx", true) 3862 .Case("avx2", true) 3863 .Case("sse4a", true) 3864 .Case("fma4", true) 3865 .Case("xop", true) 3866 .Case("fma", true) 3867 .Case("avx512f", true) 3868 .Case("bmi", true) 3869 .Case("bmi2", true) 3870 .Case("aes", true) 3871 .Case("pclmul", true) 3872 .Case("avx512vl", true) 3873 .Case("avx512bw", true) 3874 .Case("avx512dq", true) 3875 .Case("avx512cd", true) 3876 .Case("avx512er", true) 3877 .Case("avx512pf", true) 3878 .Case("avx512vbmi", true) 3879 .Case("avx512ifma", true) 3880 .Default(false); 3881 } 3882 3883 bool 3884 X86TargetInfo::validateAsmConstraint(const char *&Name, 3885 TargetInfo::ConstraintInfo &Info) const { 3886 switch (*Name) { 3887 default: return false; 3888 // Constant constraints. 3889 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3890 // instructions. 3891 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3892 // x86_64 instructions. 3893 case 's': 3894 Info.setRequiresImmediate(); 3895 return true; 3896 case 'I': 3897 Info.setRequiresImmediate(0, 31); 3898 return true; 3899 case 'J': 3900 Info.setRequiresImmediate(0, 63); 3901 return true; 3902 case 'K': 3903 Info.setRequiresImmediate(-128, 127); 3904 return true; 3905 case 'L': 3906 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3907 return true; 3908 case 'M': 3909 Info.setRequiresImmediate(0, 3); 3910 return true; 3911 case 'N': 3912 Info.setRequiresImmediate(0, 255); 3913 return true; 3914 case 'O': 3915 Info.setRequiresImmediate(0, 127); 3916 return true; 3917 // Register constraints. 3918 case 'Y': // 'Y' is the first character for several 2-character constraints. 3919 // Shift the pointer to the second character of the constraint. 3920 Name++; 3921 switch (*Name) { 3922 default: 3923 return false; 3924 case '0': // First SSE register. 3925 case 't': // Any SSE register, when SSE2 is enabled. 3926 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3927 case 'm': // Any MMX register, when inter-unit moves enabled. 3928 Info.setAllowsRegister(); 3929 return true; 3930 } 3931 case 'f': // Any x87 floating point stack register. 3932 // Constraint 'f' cannot be used for output operands. 3933 if (Info.ConstraintStr[0] == '=') 3934 return false; 3935 Info.setAllowsRegister(); 3936 return true; 3937 case 'a': // eax. 3938 case 'b': // ebx. 3939 case 'c': // ecx. 3940 case 'd': // edx. 3941 case 'S': // esi. 3942 case 'D': // edi. 3943 case 'A': // edx:eax. 3944 case 't': // Top of floating point stack. 3945 case 'u': // Second from top of floating point stack. 3946 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3947 case 'y': // Any MMX register. 3948 case 'x': // Any SSE register. 3949 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3950 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3951 case 'l': // "Index" registers: any general register that can be used as an 3952 // index in a base+index memory access. 3953 Info.setAllowsRegister(); 3954 return true; 3955 // Floating point constant constraints. 3956 case 'C': // SSE floating point constant. 3957 case 'G': // x87 floating point constant. 3958 return true; 3959 } 3960 } 3961 3962 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3963 unsigned Size) const { 3964 // Strip off constraint modifiers. 3965 while (Constraint[0] == '=' || 3966 Constraint[0] == '+' || 3967 Constraint[0] == '&') 3968 Constraint = Constraint.substr(1); 3969 3970 return validateOperandSize(Constraint, Size); 3971 } 3972 3973 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3974 unsigned Size) const { 3975 return validateOperandSize(Constraint, Size); 3976 } 3977 3978 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3979 unsigned Size) const { 3980 switch (Constraint[0]) { 3981 default: break; 3982 case 'y': 3983 return Size <= 64; 3984 case 'f': 3985 case 't': 3986 case 'u': 3987 return Size <= 128; 3988 case 'x': 3989 if (SSELevel >= AVX512F) 3990 // 512-bit zmm registers can be used if target supports AVX512F. 3991 return Size <= 512U; 3992 else if (SSELevel >= AVX) 3993 // 256-bit ymm registers can be used if target supports AVX. 3994 return Size <= 256U; 3995 return Size <= 128U; 3996 case 'Y': 3997 // 'Y' is the first character for several 2-character constraints. 3998 switch (Constraint[1]) { 3999 default: break; 4000 case 'm': 4001 // 'Ym' is synonymous with 'y'. 4002 return Size <= 64; 4003 case 'i': 4004 case 't': 4005 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4006 if (SSELevel >= AVX512F) 4007 return Size <= 512U; 4008 else if (SSELevel >= AVX) 4009 return Size <= 256U; 4010 return SSELevel >= SSE2 && Size <= 128U; 4011 } 4012 4013 } 4014 4015 return true; 4016 } 4017 4018 std::string 4019 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4020 switch (*Constraint) { 4021 case 'a': return std::string("{ax}"); 4022 case 'b': return std::string("{bx}"); 4023 case 'c': return std::string("{cx}"); 4024 case 'd': return std::string("{dx}"); 4025 case 'S': return std::string("{si}"); 4026 case 'D': return std::string("{di}"); 4027 case 'p': // address 4028 return std::string("im"); 4029 case 't': // top of floating point stack. 4030 return std::string("{st}"); 4031 case 'u': // second from top of floating point stack. 4032 return std::string("{st(1)}"); // second from top of floating point stack. 4033 default: 4034 return std::string(1, *Constraint); 4035 } 4036 } 4037 4038 // X86-32 generic target 4039 class X86_32TargetInfo : public X86TargetInfo { 4040 public: 4041 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4042 : X86TargetInfo(Triple, Opts) { 4043 DoubleAlign = LongLongAlign = 32; 4044 LongDoubleWidth = 96; 4045 LongDoubleAlign = 32; 4046 SuitableAlign = 128; 4047 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4048 SizeType = UnsignedInt; 4049 PtrDiffType = SignedInt; 4050 IntPtrType = SignedInt; 4051 RegParmMax = 3; 4052 4053 // Use fpret for all types. 4054 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4055 (1 << TargetInfo::Double) | 4056 (1 << TargetInfo::LongDouble)); 4057 4058 // x86-32 has atomics up to 8 bytes 4059 // FIXME: Check that we actually have cmpxchg8b before setting 4060 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4061 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4062 } 4063 BuiltinVaListKind getBuiltinVaListKind() const override { 4064 return TargetInfo::CharPtrBuiltinVaList; 4065 } 4066 4067 int getEHDataRegisterNumber(unsigned RegNo) const override { 4068 if (RegNo == 0) return 0; 4069 if (RegNo == 1) return 2; 4070 return -1; 4071 } 4072 bool validateOperandSize(StringRef Constraint, 4073 unsigned Size) const override { 4074 switch (Constraint[0]) { 4075 default: break; 4076 case 'R': 4077 case 'q': 4078 case 'Q': 4079 case 'a': 4080 case 'b': 4081 case 'c': 4082 case 'd': 4083 case 'S': 4084 case 'D': 4085 return Size <= 32; 4086 case 'A': 4087 return Size <= 64; 4088 } 4089 4090 return X86TargetInfo::validateOperandSize(Constraint, Size); 4091 } 4092 }; 4093 4094 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4095 public: 4096 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4097 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4098 4099 unsigned getFloatEvalMethod() const override { 4100 unsigned Major, Minor, Micro; 4101 getTriple().getOSVersion(Major, Minor, Micro); 4102 // New NetBSD uses the default rounding mode. 4103 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4104 return X86_32TargetInfo::getFloatEvalMethod(); 4105 // NetBSD before 6.99.26 defaults to "double" rounding. 4106 return 1; 4107 } 4108 }; 4109 4110 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4111 public: 4112 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4113 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4114 SizeType = UnsignedLong; 4115 IntPtrType = SignedLong; 4116 PtrDiffType = SignedLong; 4117 } 4118 }; 4119 4120 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4121 public: 4122 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4123 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4124 SizeType = UnsignedLong; 4125 IntPtrType = SignedLong; 4126 PtrDiffType = SignedLong; 4127 } 4128 }; 4129 4130 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4131 public: 4132 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4133 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4134 LongDoubleWidth = 128; 4135 LongDoubleAlign = 128; 4136 SuitableAlign = 128; 4137 MaxVectorAlign = 256; 4138 // The watchOS simulator uses the builtin bool type for Objective-C. 4139 llvm::Triple T = llvm::Triple(Triple); 4140 if (T.isWatchOS()) 4141 UseSignedCharForObjCBool = false; 4142 SizeType = UnsignedLong; 4143 IntPtrType = SignedLong; 4144 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4145 HasAlignMac68kSupport = true; 4146 } 4147 4148 bool handleTargetFeatures(std::vector<std::string> &Features, 4149 DiagnosticsEngine &Diags) override { 4150 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4151 Diags)) 4152 return false; 4153 // We now know the features we have: we can decide how to align vectors. 4154 MaxVectorAlign = 4155 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4156 return true; 4157 } 4158 }; 4159 4160 // x86-32 Windows target 4161 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4162 public: 4163 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4164 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4165 WCharType = UnsignedShort; 4166 DoubleAlign = LongLongAlign = 64; 4167 bool IsWinCOFF = 4168 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4169 resetDataLayout(IsWinCOFF 4170 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4171 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4172 } 4173 void getTargetDefines(const LangOptions &Opts, 4174 MacroBuilder &Builder) const override { 4175 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4176 } 4177 }; 4178 4179 // x86-32 Windows Visual Studio target 4180 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4181 public: 4182 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4183 const TargetOptions &Opts) 4184 : WindowsX86_32TargetInfo(Triple, Opts) { 4185 LongDoubleWidth = LongDoubleAlign = 64; 4186 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4187 } 4188 void getTargetDefines(const LangOptions &Opts, 4189 MacroBuilder &Builder) const override { 4190 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4191 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4192 // The value of the following reflects processor type. 4193 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4194 // We lost the original triple, so we use the default. 4195 Builder.defineMacro("_M_IX86", "600"); 4196 } 4197 }; 4198 4199 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4200 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4201 // supports __declspec natively under -fms-extensions, but we define a no-op 4202 // __declspec macro anyway for pre-processor compatibility. 4203 if (Opts.MicrosoftExt) 4204 Builder.defineMacro("__declspec", "__declspec"); 4205 else 4206 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4207 4208 if (!Opts.MicrosoftExt) { 4209 // Provide macros for all the calling convention keywords. Provide both 4210 // single and double underscore prefixed variants. These are available on 4211 // x64 as well as x86, even though they have no effect. 4212 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4213 for (const char *CC : CCs) { 4214 std::string GCCSpelling = "__attribute__((__"; 4215 GCCSpelling += CC; 4216 GCCSpelling += "__))"; 4217 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4218 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4219 } 4220 } 4221 } 4222 4223 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4224 Builder.defineMacro("__MSVCRT__"); 4225 Builder.defineMacro("__MINGW32__"); 4226 addCygMingDefines(Opts, Builder); 4227 } 4228 4229 // x86-32 MinGW target 4230 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4231 public: 4232 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4233 : WindowsX86_32TargetInfo(Triple, Opts) {} 4234 void getTargetDefines(const LangOptions &Opts, 4235 MacroBuilder &Builder) const override { 4236 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4237 DefineStd(Builder, "WIN32", Opts); 4238 DefineStd(Builder, "WINNT", Opts); 4239 Builder.defineMacro("_X86_"); 4240 addMinGWDefines(Opts, Builder); 4241 } 4242 }; 4243 4244 // x86-32 Cygwin target 4245 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4246 public: 4247 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4248 : X86_32TargetInfo(Triple, Opts) { 4249 WCharType = UnsignedShort; 4250 DoubleAlign = LongLongAlign = 64; 4251 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4252 } 4253 void getTargetDefines(const LangOptions &Opts, 4254 MacroBuilder &Builder) const override { 4255 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4256 Builder.defineMacro("_X86_"); 4257 Builder.defineMacro("__CYGWIN__"); 4258 Builder.defineMacro("__CYGWIN32__"); 4259 addCygMingDefines(Opts, Builder); 4260 DefineStd(Builder, "unix", Opts); 4261 if (Opts.CPlusPlus) 4262 Builder.defineMacro("_GNU_SOURCE"); 4263 } 4264 }; 4265 4266 // x86-32 Haiku target 4267 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4268 public: 4269 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4270 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4271 } 4272 void getTargetDefines(const LangOptions &Opts, 4273 MacroBuilder &Builder) const override { 4274 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4275 Builder.defineMacro("__INTEL__"); 4276 } 4277 }; 4278 4279 // X86-32 MCU target 4280 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4281 public: 4282 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4283 : X86_32TargetInfo(Triple, Opts) { 4284 LongDoubleWidth = 64; 4285 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4286 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4287 WIntType = UnsignedInt; 4288 } 4289 4290 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4291 // On MCU we support only C calling convention. 4292 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4293 } 4294 4295 void getTargetDefines(const LangOptions &Opts, 4296 MacroBuilder &Builder) const override { 4297 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4298 Builder.defineMacro("__iamcu"); 4299 Builder.defineMacro("__iamcu__"); 4300 } 4301 4302 bool allowsLargerPreferedTypeAlignment() const override { 4303 return false; 4304 } 4305 }; 4306 4307 // RTEMS Target 4308 template<typename Target> 4309 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4310 protected: 4311 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4312 MacroBuilder &Builder) const override { 4313 // RTEMS defines; list based off of gcc output 4314 4315 Builder.defineMacro("__rtems__"); 4316 Builder.defineMacro("__ELF__"); 4317 } 4318 4319 public: 4320 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4321 : OSTargetInfo<Target>(Triple, Opts) { 4322 switch (Triple.getArch()) { 4323 default: 4324 case llvm::Triple::x86: 4325 // this->MCountName = ".mcount"; 4326 break; 4327 case llvm::Triple::mips: 4328 case llvm::Triple::mipsel: 4329 case llvm::Triple::ppc: 4330 case llvm::Triple::ppc64: 4331 case llvm::Triple::ppc64le: 4332 // this->MCountName = "_mcount"; 4333 break; 4334 case llvm::Triple::arm: 4335 // this->MCountName = "__mcount"; 4336 break; 4337 } 4338 } 4339 }; 4340 4341 // x86-32 RTEMS target 4342 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4343 public: 4344 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4345 : X86_32TargetInfo(Triple, Opts) { 4346 SizeType = UnsignedLong; 4347 IntPtrType = SignedLong; 4348 PtrDiffType = SignedLong; 4349 } 4350 void getTargetDefines(const LangOptions &Opts, 4351 MacroBuilder &Builder) const override { 4352 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4353 Builder.defineMacro("__INTEL__"); 4354 Builder.defineMacro("__rtems__"); 4355 } 4356 }; 4357 4358 // x86-64 generic target 4359 class X86_64TargetInfo : public X86TargetInfo { 4360 public: 4361 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4362 : X86TargetInfo(Triple, Opts) { 4363 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4364 bool IsWinCOFF = 4365 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4366 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4367 LongDoubleWidth = 128; 4368 LongDoubleAlign = 128; 4369 LargeArrayMinWidth = 128; 4370 LargeArrayAlign = 128; 4371 SuitableAlign = 128; 4372 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4373 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4374 IntPtrType = IsX32 ? SignedInt : SignedLong; 4375 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4376 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4377 RegParmMax = 6; 4378 4379 // Pointers are 32-bit in x32. 4380 resetDataLayout(IsX32 4381 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4382 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4383 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4384 4385 // Use fpret only for long double. 4386 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4387 4388 // Use fp2ret for _Complex long double. 4389 ComplexLongDoubleUsesFP2Ret = true; 4390 4391 // Make __builtin_ms_va_list available. 4392 HasBuiltinMSVaList = true; 4393 4394 // x86-64 has atomics up to 16 bytes. 4395 MaxAtomicPromoteWidth = 128; 4396 MaxAtomicInlineWidth = 128; 4397 } 4398 BuiltinVaListKind getBuiltinVaListKind() const override { 4399 return TargetInfo::X86_64ABIBuiltinVaList; 4400 } 4401 4402 int getEHDataRegisterNumber(unsigned RegNo) const override { 4403 if (RegNo == 0) return 0; 4404 if (RegNo == 1) return 1; 4405 return -1; 4406 } 4407 4408 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4409 switch (CC) { 4410 case CC_C: 4411 case CC_Swift: 4412 case CC_X86VectorCall: 4413 case CC_IntelOclBicc: 4414 case CC_X86_64Win64: 4415 case CC_PreserveMost: 4416 case CC_PreserveAll: 4417 return CCCR_OK; 4418 default: 4419 return CCCR_Warning; 4420 } 4421 } 4422 4423 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4424 return CC_C; 4425 } 4426 4427 // for x32 we need it here explicitly 4428 bool hasInt128Type() const override { return true; } 4429 unsigned getUnwindWordWidth() const override { return 64; } 4430 unsigned getRegisterWidth() const override { return 64; } 4431 4432 bool validateGlobalRegisterVariable(StringRef RegName, 4433 unsigned RegSize, 4434 bool &HasSizeMismatch) const override { 4435 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4436 // handle. 4437 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4438 // Check that the register size is 64-bit. 4439 HasSizeMismatch = RegSize != 64; 4440 return true; 4441 } 4442 4443 // Check if the register is a 32-bit register the backend can handle. 4444 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4445 HasSizeMismatch); 4446 } 4447 }; 4448 4449 // x86-64 Windows target 4450 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4451 public: 4452 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4453 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4454 WCharType = UnsignedShort; 4455 LongWidth = LongAlign = 32; 4456 DoubleAlign = LongLongAlign = 64; 4457 IntMaxType = SignedLongLong; 4458 Int64Type = SignedLongLong; 4459 SizeType = UnsignedLongLong; 4460 PtrDiffType = SignedLongLong; 4461 IntPtrType = SignedLongLong; 4462 } 4463 4464 void getTargetDefines(const LangOptions &Opts, 4465 MacroBuilder &Builder) const override { 4466 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4467 Builder.defineMacro("_WIN64"); 4468 } 4469 4470 BuiltinVaListKind getBuiltinVaListKind() const override { 4471 return TargetInfo::CharPtrBuiltinVaList; 4472 } 4473 4474 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4475 switch (CC) { 4476 case CC_X86StdCall: 4477 case CC_X86ThisCall: 4478 case CC_X86FastCall: 4479 return CCCR_Ignore; 4480 case CC_C: 4481 case CC_X86VectorCall: 4482 case CC_IntelOclBicc: 4483 case CC_X86_64SysV: 4484 return CCCR_OK; 4485 default: 4486 return CCCR_Warning; 4487 } 4488 } 4489 }; 4490 4491 // x86-64 Windows Visual Studio target 4492 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4493 public: 4494 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4495 const TargetOptions &Opts) 4496 : WindowsX86_64TargetInfo(Triple, Opts) { 4497 LongDoubleWidth = LongDoubleAlign = 64; 4498 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4499 } 4500 void getTargetDefines(const LangOptions &Opts, 4501 MacroBuilder &Builder) const override { 4502 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4503 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4504 Builder.defineMacro("_M_X64", "100"); 4505 Builder.defineMacro("_M_AMD64", "100"); 4506 } 4507 }; 4508 4509 // x86-64 MinGW target 4510 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4511 public: 4512 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4513 : WindowsX86_64TargetInfo(Triple, Opts) { 4514 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4515 // with x86 FP ops. Weird. 4516 LongDoubleWidth = LongDoubleAlign = 128; 4517 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4518 } 4519 4520 void getTargetDefines(const LangOptions &Opts, 4521 MacroBuilder &Builder) const override { 4522 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4523 DefineStd(Builder, "WIN64", Opts); 4524 Builder.defineMacro("__MINGW64__"); 4525 addMinGWDefines(Opts, Builder); 4526 4527 // GCC defines this macro when it is using __gxx_personality_seh0. 4528 if (!Opts.SjLjExceptions) 4529 Builder.defineMacro("__SEH__"); 4530 } 4531 }; 4532 4533 // x86-64 Cygwin target 4534 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4535 public: 4536 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4537 : X86_64TargetInfo(Triple, Opts) { 4538 TLSSupported = false; 4539 WCharType = UnsignedShort; 4540 } 4541 void getTargetDefines(const LangOptions &Opts, 4542 MacroBuilder &Builder) const override { 4543 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4544 Builder.defineMacro("__x86_64__"); 4545 Builder.defineMacro("__CYGWIN__"); 4546 Builder.defineMacro("__CYGWIN64__"); 4547 addCygMingDefines(Opts, Builder); 4548 DefineStd(Builder, "unix", Opts); 4549 if (Opts.CPlusPlus) 4550 Builder.defineMacro("_GNU_SOURCE"); 4551 4552 // GCC defines this macro when it is using __gxx_personality_seh0. 4553 if (!Opts.SjLjExceptions) 4554 Builder.defineMacro("__SEH__"); 4555 } 4556 }; 4557 4558 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4559 public: 4560 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4561 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4562 Int64Type = SignedLongLong; 4563 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4564 llvm::Triple T = llvm::Triple(Triple); 4565 if (T.isiOS()) 4566 UseSignedCharForObjCBool = false; 4567 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4568 } 4569 4570 bool handleTargetFeatures(std::vector<std::string> &Features, 4571 DiagnosticsEngine &Diags) override { 4572 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4573 Diags)) 4574 return false; 4575 // We now know the features we have: we can decide how to align vectors. 4576 MaxVectorAlign = 4577 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4578 return true; 4579 } 4580 }; 4581 4582 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4583 public: 4584 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4585 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4586 IntMaxType = SignedLongLong; 4587 Int64Type = SignedLongLong; 4588 } 4589 }; 4590 4591 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4592 public: 4593 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4594 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4595 IntMaxType = SignedLongLong; 4596 Int64Type = SignedLongLong; 4597 } 4598 }; 4599 4600 class ARMTargetInfo : public TargetInfo { 4601 // Possible FPU choices. 4602 enum FPUMode { 4603 VFP2FPU = (1 << 0), 4604 VFP3FPU = (1 << 1), 4605 VFP4FPU = (1 << 2), 4606 NeonFPU = (1 << 3), 4607 FPARMV8 = (1 << 4) 4608 }; 4609 4610 // Possible HWDiv features. 4611 enum HWDivMode { 4612 HWDivThumb = (1 << 0), 4613 HWDivARM = (1 << 1) 4614 }; 4615 4616 static bool FPUModeIsVFP(FPUMode Mode) { 4617 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4618 } 4619 4620 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4621 static const char * const GCCRegNames[]; 4622 4623 std::string ABI, CPU; 4624 4625 StringRef CPUProfile; 4626 StringRef CPUAttr; 4627 4628 enum { 4629 FP_Default, 4630 FP_VFP, 4631 FP_Neon 4632 } FPMath; 4633 4634 unsigned ArchISA; 4635 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4636 unsigned ArchProfile; 4637 unsigned ArchVersion; 4638 4639 unsigned FPU : 5; 4640 4641 unsigned IsAAPCS : 1; 4642 unsigned HWDiv : 2; 4643 4644 // Initialized via features. 4645 unsigned SoftFloat : 1; 4646 unsigned SoftFloatABI : 1; 4647 4648 unsigned CRC : 1; 4649 unsigned Crypto : 1; 4650 unsigned DSP : 1; 4651 unsigned Unaligned : 1; 4652 4653 enum { 4654 LDREX_B = (1 << 0), /// byte (8-bit) 4655 LDREX_H = (1 << 1), /// half (16-bit) 4656 LDREX_W = (1 << 2), /// word (32-bit) 4657 LDREX_D = (1 << 3), /// double (64-bit) 4658 }; 4659 4660 uint32_t LDREX; 4661 4662 // ACLE 6.5.1 Hardware floating point 4663 enum { 4664 HW_FP_HP = (1 << 1), /// half (16-bit) 4665 HW_FP_SP = (1 << 2), /// single (32-bit) 4666 HW_FP_DP = (1 << 3), /// double (64-bit) 4667 }; 4668 uint32_t HW_FP; 4669 4670 static const Builtin::Info BuiltinInfo[]; 4671 4672 void setABIAAPCS() { 4673 IsAAPCS = true; 4674 4675 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4676 const llvm::Triple &T = getTriple(); 4677 4678 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4679 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4680 T.getOS() == llvm::Triple::Bitrig) 4681 SizeType = UnsignedLong; 4682 else 4683 SizeType = UnsignedInt; 4684 4685 switch (T.getOS()) { 4686 case llvm::Triple::NetBSD: 4687 WCharType = SignedInt; 4688 break; 4689 case llvm::Triple::Win32: 4690 WCharType = UnsignedShort; 4691 break; 4692 case llvm::Triple::Linux: 4693 default: 4694 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4695 WCharType = UnsignedInt; 4696 break; 4697 } 4698 4699 UseBitFieldTypeAlignment = true; 4700 4701 ZeroLengthBitfieldBoundary = 0; 4702 4703 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4704 // so set preferred for small types to 32. 4705 if (T.isOSBinFormatMachO()) { 4706 resetDataLayout(BigEndian 4707 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4708 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4709 } else if (T.isOSWindows()) { 4710 assert(!BigEndian && "Windows on ARM does not support big endian"); 4711 resetDataLayout("e" 4712 "-m:w" 4713 "-p:32:32" 4714 "-i64:64" 4715 "-v128:64:128" 4716 "-a:0:32" 4717 "-n32" 4718 "-S64"); 4719 } else if (T.isOSNaCl()) { 4720 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4721 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4722 } else { 4723 resetDataLayout(BigEndian 4724 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4725 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4726 } 4727 4728 // FIXME: Enumerated types are variable width in straight AAPCS. 4729 } 4730 4731 void setABIAPCS(bool IsAAPCS16) { 4732 const llvm::Triple &T = getTriple(); 4733 4734 IsAAPCS = false; 4735 4736 if (IsAAPCS16) 4737 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4738 else 4739 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4740 4741 // size_t is unsigned int on FreeBSD. 4742 if (T.getOS() == llvm::Triple::FreeBSD) 4743 SizeType = UnsignedInt; 4744 else 4745 SizeType = UnsignedLong; 4746 4747 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4748 WCharType = SignedInt; 4749 4750 // Do not respect the alignment of bit-field types when laying out 4751 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4752 UseBitFieldTypeAlignment = false; 4753 4754 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4755 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4756 /// gcc. 4757 ZeroLengthBitfieldBoundary = 32; 4758 4759 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4760 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4761 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4762 } else if (T.isOSBinFormatMachO()) 4763 resetDataLayout( 4764 BigEndian 4765 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4766 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4767 else 4768 resetDataLayout( 4769 BigEndian 4770 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4771 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4772 4773 // FIXME: Override "preferred align" for double and long long. 4774 } 4775 4776 void setArchInfo() { 4777 StringRef ArchName = getTriple().getArchName(); 4778 4779 ArchISA = llvm::ARM::parseArchISA(ArchName); 4780 CPU = llvm::ARM::getDefaultCPU(ArchName); 4781 unsigned AK = llvm::ARM::parseArch(ArchName); 4782 if (AK != llvm::ARM::AK_INVALID) 4783 ArchKind = AK; 4784 setArchInfo(ArchKind); 4785 } 4786 4787 void setArchInfo(unsigned Kind) { 4788 StringRef SubArch; 4789 4790 // cache TargetParser info 4791 ArchKind = Kind; 4792 SubArch = llvm::ARM::getSubArch(ArchKind); 4793 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4794 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4795 4796 // cache CPU related strings 4797 CPUAttr = getCPUAttr(); 4798 CPUProfile = getCPUProfile(); 4799 } 4800 4801 void setAtomic() { 4802 // when triple does not specify a sub arch, 4803 // then we are not using inline atomics 4804 bool ShouldUseInlineAtomic = 4805 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4806 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4807 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4808 if (ArchProfile == llvm::ARM::PK_M) { 4809 MaxAtomicPromoteWidth = 32; 4810 if (ShouldUseInlineAtomic) 4811 MaxAtomicInlineWidth = 32; 4812 } 4813 else { 4814 MaxAtomicPromoteWidth = 64; 4815 if (ShouldUseInlineAtomic) 4816 MaxAtomicInlineWidth = 64; 4817 } 4818 } 4819 4820 bool isThumb() const { 4821 return (ArchISA == llvm::ARM::IK_THUMB); 4822 } 4823 4824 bool supportsThumb() const { 4825 return CPUAttr.count('T') || ArchVersion >= 6; 4826 } 4827 4828 bool supportsThumb2() const { 4829 return CPUAttr.equals("6T2") || 4830 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4831 } 4832 4833 StringRef getCPUAttr() const { 4834 // For most sub-arches, the build attribute CPU name is enough. 4835 // For Cortex variants, it's slightly different. 4836 switch(ArchKind) { 4837 default: 4838 return llvm::ARM::getCPUAttr(ArchKind); 4839 case llvm::ARM::AK_ARMV6M: 4840 return "6M"; 4841 case llvm::ARM::AK_ARMV7S: 4842 return "7S"; 4843 case llvm::ARM::AK_ARMV7A: 4844 return "7A"; 4845 case llvm::ARM::AK_ARMV7R: 4846 return "7R"; 4847 case llvm::ARM::AK_ARMV7M: 4848 return "7M"; 4849 case llvm::ARM::AK_ARMV7EM: 4850 return "7EM"; 4851 case llvm::ARM::AK_ARMV8A: 4852 return "8A"; 4853 case llvm::ARM::AK_ARMV8_1A: 4854 return "8_1A"; 4855 case llvm::ARM::AK_ARMV8_2A: 4856 return "8_2A"; 4857 case llvm::ARM::AK_ARMV8MBaseline: 4858 return "8M_BASE"; 4859 case llvm::ARM::AK_ARMV8MMainline: 4860 return "8M_MAIN"; 4861 } 4862 } 4863 4864 StringRef getCPUProfile() const { 4865 switch(ArchProfile) { 4866 case llvm::ARM::PK_A: 4867 return "A"; 4868 case llvm::ARM::PK_R: 4869 return "R"; 4870 case llvm::ARM::PK_M: 4871 return "M"; 4872 default: 4873 return ""; 4874 } 4875 } 4876 4877 public: 4878 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4879 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4880 HW_FP(0) { 4881 4882 switch (getTriple().getOS()) { 4883 case llvm::Triple::NetBSD: 4884 PtrDiffType = SignedLong; 4885 break; 4886 default: 4887 PtrDiffType = SignedInt; 4888 break; 4889 } 4890 4891 // Cache arch related info. 4892 setArchInfo(); 4893 4894 // {} in inline assembly are neon specifiers, not assembly variant 4895 // specifiers. 4896 NoAsmVariants = true; 4897 4898 // FIXME: This duplicates code from the driver that sets the -target-abi 4899 // option - this code is used if -target-abi isn't passed and should 4900 // be unified in some way. 4901 if (Triple.isOSBinFormatMachO()) { 4902 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4903 // the frontend matches that. 4904 if (Triple.getEnvironment() == llvm::Triple::EABI || 4905 Triple.getOS() == llvm::Triple::UnknownOS || 4906 ArchProfile == llvm::ARM::PK_M) { 4907 setABI("aapcs"); 4908 } else if (Triple.isWatchABI()) { 4909 setABI("aapcs16"); 4910 } else { 4911 setABI("apcs-gnu"); 4912 } 4913 } else if (Triple.isOSWindows()) { 4914 // FIXME: this is invalid for WindowsCE 4915 setABI("aapcs"); 4916 } else { 4917 // Select the default based on the platform. 4918 switch (Triple.getEnvironment()) { 4919 case llvm::Triple::Android: 4920 case llvm::Triple::GNUEABI: 4921 case llvm::Triple::GNUEABIHF: 4922 case llvm::Triple::MuslEABI: 4923 case llvm::Triple::MuslEABIHF: 4924 setABI("aapcs-linux"); 4925 break; 4926 case llvm::Triple::EABIHF: 4927 case llvm::Triple::EABI: 4928 setABI("aapcs"); 4929 break; 4930 case llvm::Triple::GNU: 4931 setABI("apcs-gnu"); 4932 break; 4933 default: 4934 if (Triple.getOS() == llvm::Triple::NetBSD) 4935 setABI("apcs-gnu"); 4936 else 4937 setABI("aapcs"); 4938 break; 4939 } 4940 } 4941 4942 // ARM targets default to using the ARM C++ ABI. 4943 TheCXXABI.set(TargetCXXABI::GenericARM); 4944 4945 // ARM has atomics up to 8 bytes 4946 setAtomic(); 4947 4948 // Do force alignment of members that follow zero length bitfields. If 4949 // the alignment of the zero-length bitfield is greater than the member 4950 // that follows it, `bar', `bar' will be aligned as the type of the 4951 // zero length bitfield. 4952 UseZeroLengthBitfieldAlignment = true; 4953 4954 if (Triple.getOS() == llvm::Triple::Linux || 4955 Triple.getOS() == llvm::Triple::UnknownOS) 4956 this->MCountName = 4957 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4958 } 4959 4960 StringRef getABI() const override { return ABI; } 4961 4962 bool setABI(const std::string &Name) override { 4963 ABI = Name; 4964 4965 // The defaults (above) are for AAPCS, check if we need to change them. 4966 // 4967 // FIXME: We need support for -meabi... we could just mangle it into the 4968 // name. 4969 if (Name == "apcs-gnu" || Name == "aapcs16") { 4970 setABIAPCS(Name == "aapcs16"); 4971 return true; 4972 } 4973 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4974 setABIAAPCS(); 4975 return true; 4976 } 4977 return false; 4978 } 4979 4980 // FIXME: This should be based on Arch attributes, not CPU names. 4981 bool 4982 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4983 StringRef CPU, 4984 const std::vector<std::string> &FeaturesVec) const override { 4985 4986 std::vector<const char*> TargetFeatures; 4987 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4988 4989 // get default FPU features 4990 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4991 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4992 4993 // get default Extension features 4994 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4995 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4996 4997 for (const char *Feature : TargetFeatures) 4998 if (Feature[0] == '+') 4999 Features[Feature+1] = true; 5000 5001 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5002 } 5003 5004 bool handleTargetFeatures(std::vector<std::string> &Features, 5005 DiagnosticsEngine &Diags) override { 5006 FPU = 0; 5007 CRC = 0; 5008 Crypto = 0; 5009 DSP = 0; 5010 Unaligned = 1; 5011 SoftFloat = SoftFloatABI = false; 5012 HWDiv = 0; 5013 5014 // This does not diagnose illegal cases like having both 5015 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5016 uint32_t HW_FP_remove = 0; 5017 for (const auto &Feature : Features) { 5018 if (Feature == "+soft-float") { 5019 SoftFloat = true; 5020 } else if (Feature == "+soft-float-abi") { 5021 SoftFloatABI = true; 5022 } else if (Feature == "+vfp2") { 5023 FPU |= VFP2FPU; 5024 HW_FP |= HW_FP_SP | HW_FP_DP; 5025 } else if (Feature == "+vfp3") { 5026 FPU |= VFP3FPU; 5027 HW_FP |= HW_FP_SP | HW_FP_DP; 5028 } else if (Feature == "+vfp4") { 5029 FPU |= VFP4FPU; 5030 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5031 } else if (Feature == "+fp-armv8") { 5032 FPU |= FPARMV8; 5033 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5034 } else if (Feature == "+neon") { 5035 FPU |= NeonFPU; 5036 HW_FP |= HW_FP_SP | HW_FP_DP; 5037 } else if (Feature == "+hwdiv") { 5038 HWDiv |= HWDivThumb; 5039 } else if (Feature == "+hwdiv-arm") { 5040 HWDiv |= HWDivARM; 5041 } else if (Feature == "+crc") { 5042 CRC = 1; 5043 } else if (Feature == "+crypto") { 5044 Crypto = 1; 5045 } else if (Feature == "+dsp") { 5046 DSP = 1; 5047 } else if (Feature == "+fp-only-sp") { 5048 HW_FP_remove |= HW_FP_DP; 5049 } else if (Feature == "+strict-align") { 5050 Unaligned = 0; 5051 } else if (Feature == "+fp16") { 5052 HW_FP |= HW_FP_HP; 5053 } 5054 } 5055 HW_FP &= ~HW_FP_remove; 5056 5057 switch (ArchVersion) { 5058 case 6: 5059 if (ArchProfile == llvm::ARM::PK_M) 5060 LDREX = 0; 5061 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5062 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5063 else 5064 LDREX = LDREX_W; 5065 break; 5066 case 7: 5067 if (ArchProfile == llvm::ARM::PK_M) 5068 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5069 else 5070 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5071 break; 5072 case 8: 5073 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5074 } 5075 5076 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5077 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5078 return false; 5079 } 5080 5081 if (FPMath == FP_Neon) 5082 Features.push_back("+neonfp"); 5083 else if (FPMath == FP_VFP) 5084 Features.push_back("-neonfp"); 5085 5086 // Remove front-end specific options which the backend handles differently. 5087 auto Feature = 5088 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5089 if (Feature != Features.end()) 5090 Features.erase(Feature); 5091 5092 return true; 5093 } 5094 5095 bool hasFeature(StringRef Feature) const override { 5096 return llvm::StringSwitch<bool>(Feature) 5097 .Case("arm", true) 5098 .Case("aarch32", true) 5099 .Case("softfloat", SoftFloat) 5100 .Case("thumb", isThumb()) 5101 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5102 .Case("hwdiv", HWDiv & HWDivThumb) 5103 .Case("hwdiv-arm", HWDiv & HWDivARM) 5104 .Default(false); 5105 } 5106 5107 bool setCPU(const std::string &Name) override { 5108 if (Name != "generic") 5109 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5110 5111 if (ArchKind == llvm::ARM::AK_INVALID) 5112 return false; 5113 setAtomic(); 5114 CPU = Name; 5115 return true; 5116 } 5117 5118 bool setFPMath(StringRef Name) override; 5119 5120 void getTargetDefines(const LangOptions &Opts, 5121 MacroBuilder &Builder) const override { 5122 // Target identification. 5123 Builder.defineMacro("__arm"); 5124 Builder.defineMacro("__arm__"); 5125 // For bare-metal none-eabi. 5126 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5127 getTriple().getEnvironment() == llvm::Triple::EABI) 5128 Builder.defineMacro("__ELF__"); 5129 5130 // Target properties. 5131 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5132 5133 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5134 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5135 if (getTriple().isWatchABI()) 5136 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5137 5138 if (!CPUAttr.empty()) 5139 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5140 5141 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5142 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5143 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5144 5145 if (ArchVersion >= 8) { 5146 // ACLE 6.5.7 Crypto Extension 5147 if (Crypto) 5148 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5149 // ACLE 6.5.8 CRC32 Extension 5150 if (CRC) 5151 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5152 // ACLE 6.5.10 Numeric Maximum and Minimum 5153 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5154 // ACLE 6.5.9 Directed Rounding 5155 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5156 } 5157 5158 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5159 // is not defined for the M-profile. 5160 // NOTE that the default profile is assumed to be 'A' 5161 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5162 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5163 5164 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5165 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5166 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5167 // v7 and v8 architectures excluding v8-M Baseline. 5168 if (supportsThumb2()) 5169 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5170 else if (supportsThumb()) 5171 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5172 5173 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5174 // instruction set such as ARM or Thumb. 5175 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5176 5177 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5178 5179 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5180 if (!CPUProfile.empty()) 5181 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5182 5183 // ACLE 6.4.3 Unaligned access supported in hardware 5184 if (Unaligned) 5185 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5186 5187 // ACLE 6.4.4 LDREX/STREX 5188 if (LDREX) 5189 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5190 5191 // ACLE 6.4.5 CLZ 5192 if (ArchVersion == 5 || 5193 (ArchVersion == 6 && CPUProfile != "M") || 5194 ArchVersion > 6) 5195 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5196 5197 // ACLE 6.5.1 Hardware Floating Point 5198 if (HW_FP) 5199 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5200 5201 // ACLE predefines. 5202 Builder.defineMacro("__ARM_ACLE", "200"); 5203 5204 // FP16 support (we currently only support IEEE format). 5205 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5206 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5207 5208 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5209 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5210 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5211 5212 // Subtarget options. 5213 5214 // FIXME: It's more complicated than this and we don't really support 5215 // interworking. 5216 // Windows on ARM does not "support" interworking 5217 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5218 Builder.defineMacro("__THUMB_INTERWORK__"); 5219 5220 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5221 // Embedded targets on Darwin follow AAPCS, but not EABI. 5222 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5223 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5224 Builder.defineMacro("__ARM_EABI__"); 5225 Builder.defineMacro("__ARM_PCS", "1"); 5226 } 5227 5228 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5229 ABI == "aapcs16") 5230 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5231 5232 if (SoftFloat) 5233 Builder.defineMacro("__SOFTFP__"); 5234 5235 if (ArchKind == llvm::ARM::AK_XSCALE) 5236 Builder.defineMacro("__XSCALE__"); 5237 5238 if (isThumb()) { 5239 Builder.defineMacro("__THUMBEL__"); 5240 Builder.defineMacro("__thumb__"); 5241 if (supportsThumb2()) 5242 Builder.defineMacro("__thumb2__"); 5243 } 5244 5245 // ACLE 6.4.9 32-bit SIMD instructions 5246 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5247 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5248 5249 // ACLE 6.4.10 Hardware Integer Divide 5250 if (((HWDiv & HWDivThumb) && isThumb()) || 5251 ((HWDiv & HWDivARM) && !isThumb())) { 5252 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5253 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5254 } 5255 5256 // Note, this is always on in gcc, even though it doesn't make sense. 5257 Builder.defineMacro("__APCS_32__"); 5258 5259 if (FPUModeIsVFP((FPUMode) FPU)) { 5260 Builder.defineMacro("__VFP_FP__"); 5261 if (FPU & VFP2FPU) 5262 Builder.defineMacro("__ARM_VFPV2__"); 5263 if (FPU & VFP3FPU) 5264 Builder.defineMacro("__ARM_VFPV3__"); 5265 if (FPU & VFP4FPU) 5266 Builder.defineMacro("__ARM_VFPV4__"); 5267 } 5268 5269 // This only gets set when Neon instructions are actually available, unlike 5270 // the VFP define, hence the soft float and arch check. This is subtly 5271 // different from gcc, we follow the intent which was that it should be set 5272 // when Neon instructions are actually available. 5273 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5274 Builder.defineMacro("__ARM_NEON", "1"); 5275 Builder.defineMacro("__ARM_NEON__"); 5276 // current AArch32 NEON implementations do not support double-precision 5277 // floating-point even when it is present in VFP. 5278 Builder.defineMacro("__ARM_NEON_FP", 5279 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5280 } 5281 5282 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5283 Opts.ShortWChar ? "2" : "4"); 5284 5285 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5286 Opts.ShortEnums ? "1" : "4"); 5287 5288 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5292 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5293 } 5294 5295 // ACLE 6.4.7 DSP instructions 5296 if (DSP) { 5297 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5298 } 5299 5300 // ACLE 6.4.8 Saturation instructions 5301 bool SAT = false; 5302 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5303 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5304 SAT = true; 5305 } 5306 5307 // ACLE 6.4.6 Q (saturation) flag 5308 if (DSP || SAT) 5309 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5310 5311 if (Opts.UnsafeFPMath) 5312 Builder.defineMacro("__ARM_FP_FAST", "1"); 5313 5314 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5315 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5316 } 5317 5318 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5319 return llvm::makeArrayRef(BuiltinInfo, 5320 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5321 } 5322 bool isCLZForZeroUndef() const override { return false; } 5323 BuiltinVaListKind getBuiltinVaListKind() const override { 5324 return IsAAPCS 5325 ? AAPCSABIBuiltinVaList 5326 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5327 : TargetInfo::VoidPtrBuiltinVaList); 5328 } 5329 ArrayRef<const char *> getGCCRegNames() const override; 5330 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5331 bool validateAsmConstraint(const char *&Name, 5332 TargetInfo::ConstraintInfo &Info) const override { 5333 switch (*Name) { 5334 default: break; 5335 case 'l': // r0-r7 5336 case 'h': // r8-r15 5337 case 't': // VFP Floating point register single precision 5338 case 'w': // VFP Floating point register double precision 5339 Info.setAllowsRegister(); 5340 return true; 5341 case 'I': 5342 case 'J': 5343 case 'K': 5344 case 'L': 5345 case 'M': 5346 // FIXME 5347 return true; 5348 case 'Q': // A memory address that is a single base register. 5349 Info.setAllowsMemory(); 5350 return true; 5351 case 'U': // a memory reference... 5352 switch (Name[1]) { 5353 case 'q': // ...ARMV4 ldrsb 5354 case 'v': // ...VFP load/store (reg+constant offset) 5355 case 'y': // ...iWMMXt load/store 5356 case 't': // address valid for load/store opaque types wider 5357 // than 128-bits 5358 case 'n': // valid address for Neon doubleword vector load/store 5359 case 'm': // valid address for Neon element and structure load/store 5360 case 's': // valid address for non-offset loads/stores of quad-word 5361 // values in four ARM registers 5362 Info.setAllowsMemory(); 5363 Name++; 5364 return true; 5365 } 5366 } 5367 return false; 5368 } 5369 std::string convertConstraint(const char *&Constraint) const override { 5370 std::string R; 5371 switch (*Constraint) { 5372 case 'U': // Two-character constraint; add "^" hint for later parsing. 5373 R = std::string("^") + std::string(Constraint, 2); 5374 Constraint++; 5375 break; 5376 case 'p': // 'p' should be translated to 'r' by default. 5377 R = std::string("r"); 5378 break; 5379 default: 5380 return std::string(1, *Constraint); 5381 } 5382 return R; 5383 } 5384 bool 5385 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5386 std::string &SuggestedModifier) const override { 5387 bool isOutput = (Constraint[0] == '='); 5388 bool isInOut = (Constraint[0] == '+'); 5389 5390 // Strip off constraint modifiers. 5391 while (Constraint[0] == '=' || 5392 Constraint[0] == '+' || 5393 Constraint[0] == '&') 5394 Constraint = Constraint.substr(1); 5395 5396 switch (Constraint[0]) { 5397 default: break; 5398 case 'r': { 5399 switch (Modifier) { 5400 default: 5401 return (isInOut || isOutput || Size <= 64); 5402 case 'q': 5403 // A register of size 32 cannot fit a vector type. 5404 return false; 5405 } 5406 } 5407 } 5408 5409 return true; 5410 } 5411 const char *getClobbers() const override { 5412 // FIXME: Is this really right? 5413 return ""; 5414 } 5415 5416 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5417 switch (CC) { 5418 case CC_AAPCS: 5419 case CC_AAPCS_VFP: 5420 case CC_Swift: 5421 return CCCR_OK; 5422 default: 5423 return CCCR_Warning; 5424 } 5425 } 5426 5427 int getEHDataRegisterNumber(unsigned RegNo) const override { 5428 if (RegNo == 0) return 0; 5429 if (RegNo == 1) return 1; 5430 return -1; 5431 } 5432 5433 bool hasSjLjLowering() const override { 5434 return true; 5435 } 5436 }; 5437 5438 bool ARMTargetInfo::setFPMath(StringRef Name) { 5439 if (Name == "neon") { 5440 FPMath = FP_Neon; 5441 return true; 5442 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5443 Name == "vfp4") { 5444 FPMath = FP_VFP; 5445 return true; 5446 } 5447 return false; 5448 } 5449 5450 const char * const ARMTargetInfo::GCCRegNames[] = { 5451 // Integer registers 5452 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5453 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5454 5455 // Float registers 5456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5460 5461 // Double registers 5462 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5463 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5464 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5465 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5466 5467 // Quad registers 5468 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5469 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5470 }; 5471 5472 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5473 return llvm::makeArrayRef(GCCRegNames); 5474 } 5475 5476 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5477 { { "a1" }, "r0" }, 5478 { { "a2" }, "r1" }, 5479 { { "a3" }, "r2" }, 5480 { { "a4" }, "r3" }, 5481 { { "v1" }, "r4" }, 5482 { { "v2" }, "r5" }, 5483 { { "v3" }, "r6" }, 5484 { { "v4" }, "r7" }, 5485 { { "v5" }, "r8" }, 5486 { { "v6", "rfp" }, "r9" }, 5487 { { "sl" }, "r10" }, 5488 { { "fp" }, "r11" }, 5489 { { "ip" }, "r12" }, 5490 { { "r13" }, "sp" }, 5491 { { "r14" }, "lr" }, 5492 { { "r15" }, "pc" }, 5493 // The S, D and Q registers overlap, but aren't really aliases; we 5494 // don't want to substitute one of these for a different-sized one. 5495 }; 5496 5497 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5498 return llvm::makeArrayRef(GCCRegAliases); 5499 } 5500 5501 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5502 #define BUILTIN(ID, TYPE, ATTRS) \ 5503 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5504 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5505 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5506 #include "clang/Basic/BuiltinsNEON.def" 5507 5508 #define BUILTIN(ID, TYPE, ATTRS) \ 5509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5510 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5511 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5512 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5513 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5514 #include "clang/Basic/BuiltinsARM.def" 5515 }; 5516 5517 class ARMleTargetInfo : public ARMTargetInfo { 5518 public: 5519 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5520 : ARMTargetInfo(Triple, Opts) {} 5521 void getTargetDefines(const LangOptions &Opts, 5522 MacroBuilder &Builder) const override { 5523 Builder.defineMacro("__ARMEL__"); 5524 ARMTargetInfo::getTargetDefines(Opts, Builder); 5525 } 5526 }; 5527 5528 class ARMbeTargetInfo : public ARMTargetInfo { 5529 public: 5530 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5531 : ARMTargetInfo(Triple, Opts) {} 5532 void getTargetDefines(const LangOptions &Opts, 5533 MacroBuilder &Builder) const override { 5534 Builder.defineMacro("__ARMEB__"); 5535 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5536 ARMTargetInfo::getTargetDefines(Opts, Builder); 5537 } 5538 }; 5539 5540 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5541 const llvm::Triple Triple; 5542 public: 5543 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5544 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5545 WCharType = UnsignedShort; 5546 SizeType = UnsignedInt; 5547 } 5548 void getVisualStudioDefines(const LangOptions &Opts, 5549 MacroBuilder &Builder) const { 5550 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5551 5552 // FIXME: this is invalid for WindowsCE 5553 Builder.defineMacro("_M_ARM_NT", "1"); 5554 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5555 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5556 5557 assert((Triple.getArch() == llvm::Triple::arm || 5558 Triple.getArch() == llvm::Triple::thumb) && 5559 "invalid architecture for Windows ARM target info"); 5560 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5561 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5562 5563 // TODO map the complete set of values 5564 // 31: VFPv3 40: VFPv4 5565 Builder.defineMacro("_M_ARM_FP", "31"); 5566 } 5567 BuiltinVaListKind getBuiltinVaListKind() const override { 5568 return TargetInfo::CharPtrBuiltinVaList; 5569 } 5570 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5571 switch (CC) { 5572 case CC_X86StdCall: 5573 case CC_X86ThisCall: 5574 case CC_X86FastCall: 5575 case CC_X86VectorCall: 5576 return CCCR_Ignore; 5577 case CC_C: 5578 return CCCR_OK; 5579 default: 5580 return CCCR_Warning; 5581 } 5582 } 5583 }; 5584 5585 // Windows ARM + Itanium C++ ABI Target 5586 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5587 public: 5588 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5589 const TargetOptions &Opts) 5590 : WindowsARMTargetInfo(Triple, Opts) { 5591 TheCXXABI.set(TargetCXXABI::GenericARM); 5592 } 5593 5594 void getTargetDefines(const LangOptions &Opts, 5595 MacroBuilder &Builder) const override { 5596 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5597 5598 if (Opts.MSVCCompat) 5599 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5600 } 5601 }; 5602 5603 // Windows ARM, MS (C++) ABI 5604 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5605 public: 5606 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5607 const TargetOptions &Opts) 5608 : WindowsARMTargetInfo(Triple, Opts) { 5609 TheCXXABI.set(TargetCXXABI::Microsoft); 5610 } 5611 5612 void getTargetDefines(const LangOptions &Opts, 5613 MacroBuilder &Builder) const override { 5614 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5615 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5616 } 5617 }; 5618 5619 // ARM MinGW target 5620 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5621 public: 5622 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5623 : WindowsARMTargetInfo(Triple, Opts) { 5624 TheCXXABI.set(TargetCXXABI::GenericARM); 5625 } 5626 5627 void getTargetDefines(const LangOptions &Opts, 5628 MacroBuilder &Builder) const override { 5629 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5630 DefineStd(Builder, "WIN32", Opts); 5631 DefineStd(Builder, "WINNT", Opts); 5632 Builder.defineMacro("_ARM_"); 5633 addMinGWDefines(Opts, Builder); 5634 } 5635 }; 5636 5637 // ARM Cygwin target 5638 class CygwinARMTargetInfo : public ARMleTargetInfo { 5639 public: 5640 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5641 : ARMleTargetInfo(Triple, Opts) { 5642 TLSSupported = false; 5643 WCharType = UnsignedShort; 5644 DoubleAlign = LongLongAlign = 64; 5645 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5646 } 5647 void getTargetDefines(const LangOptions &Opts, 5648 MacroBuilder &Builder) const override { 5649 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5650 Builder.defineMacro("_ARM_"); 5651 Builder.defineMacro("__CYGWIN__"); 5652 Builder.defineMacro("__CYGWIN32__"); 5653 DefineStd(Builder, "unix", Opts); 5654 if (Opts.CPlusPlus) 5655 Builder.defineMacro("_GNU_SOURCE"); 5656 } 5657 }; 5658 5659 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5660 protected: 5661 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5662 MacroBuilder &Builder) const override { 5663 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5664 } 5665 5666 public: 5667 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5668 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5669 HasAlignMac68kSupport = true; 5670 // iOS always has 64-bit atomic instructions. 5671 // FIXME: This should be based off of the target features in 5672 // ARMleTargetInfo. 5673 MaxAtomicInlineWidth = 64; 5674 5675 if (Triple.isWatchABI()) { 5676 // Darwin on iOS uses a variant of the ARM C++ ABI. 5677 TheCXXABI.set(TargetCXXABI::WatchOS); 5678 5679 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5680 // size_t is long, it's a bit weird for it to be int. 5681 PtrDiffType = SignedLong; 5682 5683 // BOOL should be a real boolean on the new ABI 5684 UseSignedCharForObjCBool = false; 5685 } else 5686 TheCXXABI.set(TargetCXXABI::iOS); 5687 } 5688 }; 5689 5690 class AArch64TargetInfo : public TargetInfo { 5691 virtual void setDataLayout() = 0; 5692 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5693 static const char *const GCCRegNames[]; 5694 5695 enum FPUModeEnum { 5696 FPUMode, 5697 NeonMode 5698 }; 5699 5700 unsigned FPU; 5701 unsigned CRC; 5702 unsigned Crypto; 5703 unsigned Unaligned; 5704 unsigned V8_1A; 5705 5706 static const Builtin::Info BuiltinInfo[]; 5707 5708 std::string ABI; 5709 5710 public: 5711 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5712 : TargetInfo(Triple), ABI("aapcs") { 5713 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5714 WCharType = SignedInt; 5715 5716 // NetBSD apparently prefers consistency across ARM targets to consistency 5717 // across 64-bit targets. 5718 Int64Type = SignedLongLong; 5719 IntMaxType = SignedLongLong; 5720 } else { 5721 WCharType = UnsignedInt; 5722 Int64Type = SignedLong; 5723 IntMaxType = SignedLong; 5724 } 5725 5726 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5727 MaxVectorAlign = 128; 5728 MaxAtomicInlineWidth = 128; 5729 MaxAtomicPromoteWidth = 128; 5730 5731 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5732 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5733 5734 // {} in inline assembly are neon specifiers, not assembly variant 5735 // specifiers. 5736 NoAsmVariants = true; 5737 5738 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5739 // contributes to the alignment of the containing aggregate in the same way 5740 // a plain (non bit-field) member of that type would, without exception for 5741 // zero-sized or anonymous bit-fields." 5742 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5743 UseZeroLengthBitfieldAlignment = true; 5744 5745 // AArch64 targets default to using the ARM C++ ABI. 5746 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5747 5748 if (Triple.getOS() == llvm::Triple::Linux || 5749 Triple.getOS() == llvm::Triple::UnknownOS) 5750 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5751 } 5752 5753 StringRef getABI() const override { return ABI; } 5754 bool setABI(const std::string &Name) override { 5755 if (Name != "aapcs" && Name != "darwinpcs") 5756 return false; 5757 5758 ABI = Name; 5759 return true; 5760 } 5761 5762 bool setCPU(const std::string &Name) override { 5763 return Name == "generic" || 5764 llvm::AArch64::parseCPUArch(Name) != 5765 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5766 } 5767 5768 void getTargetDefines(const LangOptions &Opts, 5769 MacroBuilder &Builder) const override { 5770 // Target identification. 5771 Builder.defineMacro("__aarch64__"); 5772 5773 // Target properties. 5774 Builder.defineMacro("_LP64"); 5775 Builder.defineMacro("__LP64__"); 5776 5777 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5778 Builder.defineMacro("__ARM_ACLE", "200"); 5779 Builder.defineMacro("__ARM_ARCH", "8"); 5780 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5781 5782 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5783 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5784 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5785 5786 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5787 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5788 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5789 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5790 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5791 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5792 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5793 5794 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5795 5796 // 0xe implies support for half, single and double precision operations. 5797 Builder.defineMacro("__ARM_FP", "0xE"); 5798 5799 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5800 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5801 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5802 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5803 5804 if (Opts.UnsafeFPMath) 5805 Builder.defineMacro("__ARM_FP_FAST", "1"); 5806 5807 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5808 5809 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5810 Opts.ShortEnums ? "1" : "4"); 5811 5812 if (FPU == NeonMode) { 5813 Builder.defineMacro("__ARM_NEON", "1"); 5814 // 64-bit NEON supports half, single and double precision operations. 5815 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5816 } 5817 5818 if (CRC) 5819 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5820 5821 if (Crypto) 5822 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5823 5824 if (Unaligned) 5825 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5826 5827 if (V8_1A) 5828 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5829 5830 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5831 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5833 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5834 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5835 } 5836 5837 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5838 return llvm::makeArrayRef(BuiltinInfo, 5839 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5840 } 5841 5842 bool hasFeature(StringRef Feature) const override { 5843 return Feature == "aarch64" || 5844 Feature == "arm64" || 5845 Feature == "arm" || 5846 (Feature == "neon" && FPU == NeonMode); 5847 } 5848 5849 bool handleTargetFeatures(std::vector<std::string> &Features, 5850 DiagnosticsEngine &Diags) override { 5851 FPU = FPUMode; 5852 CRC = 0; 5853 Crypto = 0; 5854 Unaligned = 1; 5855 V8_1A = 0; 5856 5857 for (const auto &Feature : Features) { 5858 if (Feature == "+neon") 5859 FPU = NeonMode; 5860 if (Feature == "+crc") 5861 CRC = 1; 5862 if (Feature == "+crypto") 5863 Crypto = 1; 5864 if (Feature == "+strict-align") 5865 Unaligned = 0; 5866 if (Feature == "+v8.1a") 5867 V8_1A = 1; 5868 } 5869 5870 setDataLayout(); 5871 5872 return true; 5873 } 5874 5875 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5876 switch (CC) { 5877 case CC_C: 5878 case CC_Swift: 5879 case CC_PreserveMost: 5880 case CC_PreserveAll: 5881 return CCCR_OK; 5882 default: 5883 return CCCR_Warning; 5884 } 5885 } 5886 5887 bool isCLZForZeroUndef() const override { return false; } 5888 5889 BuiltinVaListKind getBuiltinVaListKind() const override { 5890 return TargetInfo::AArch64ABIBuiltinVaList; 5891 } 5892 5893 ArrayRef<const char *> getGCCRegNames() const override; 5894 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5895 5896 bool validateAsmConstraint(const char *&Name, 5897 TargetInfo::ConstraintInfo &Info) const override { 5898 switch (*Name) { 5899 default: 5900 return false; 5901 case 'w': // Floating point and SIMD registers (V0-V31) 5902 Info.setAllowsRegister(); 5903 return true; 5904 case 'I': // Constant that can be used with an ADD instruction 5905 case 'J': // Constant that can be used with a SUB instruction 5906 case 'K': // Constant that can be used with a 32-bit logical instruction 5907 case 'L': // Constant that can be used with a 64-bit logical instruction 5908 case 'M': // Constant that can be used as a 32-bit MOV immediate 5909 case 'N': // Constant that can be used as a 64-bit MOV immediate 5910 case 'Y': // Floating point constant zero 5911 case 'Z': // Integer constant zero 5912 return true; 5913 case 'Q': // A memory reference with base register and no offset 5914 Info.setAllowsMemory(); 5915 return true; 5916 case 'S': // A symbolic address 5917 Info.setAllowsRegister(); 5918 return true; 5919 case 'U': 5920 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5921 // Utf: A memory address suitable for ldp/stp in TF mode. 5922 // Usa: An absolute symbolic address. 5923 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5924 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5925 case 'z': // Zero register, wzr or xzr 5926 Info.setAllowsRegister(); 5927 return true; 5928 case 'x': // Floating point and SIMD registers (V0-V15) 5929 Info.setAllowsRegister(); 5930 return true; 5931 } 5932 return false; 5933 } 5934 5935 bool 5936 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5937 std::string &SuggestedModifier) const override { 5938 // Strip off constraint modifiers. 5939 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5940 Constraint = Constraint.substr(1); 5941 5942 switch (Constraint[0]) { 5943 default: 5944 return true; 5945 case 'z': 5946 case 'r': { 5947 switch (Modifier) { 5948 case 'x': 5949 case 'w': 5950 // For now assume that the person knows what they're 5951 // doing with the modifier. 5952 return true; 5953 default: 5954 // By default an 'r' constraint will be in the 'x' 5955 // registers. 5956 if (Size == 64) 5957 return true; 5958 5959 SuggestedModifier = "w"; 5960 return false; 5961 } 5962 } 5963 } 5964 } 5965 5966 const char *getClobbers() const override { return ""; } 5967 5968 int getEHDataRegisterNumber(unsigned RegNo) const override { 5969 if (RegNo == 0) 5970 return 0; 5971 if (RegNo == 1) 5972 return 1; 5973 return -1; 5974 } 5975 }; 5976 5977 const char *const AArch64TargetInfo::GCCRegNames[] = { 5978 // 32-bit Integer registers 5979 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5980 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5981 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5982 5983 // 64-bit Integer registers 5984 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5985 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5986 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5987 5988 // 32-bit floating point regsisters 5989 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5990 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5991 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5992 5993 // 64-bit floating point regsisters 5994 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5995 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5996 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5997 5998 // Vector registers 5999 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6000 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6001 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6002 }; 6003 6004 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6005 return llvm::makeArrayRef(GCCRegNames); 6006 } 6007 6008 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6009 { { "w31" }, "wsp" }, 6010 { { "x29" }, "fp" }, 6011 { { "x30" }, "lr" }, 6012 { { "x31" }, "sp" }, 6013 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6014 // don't want to substitute one of these for a different-sized one. 6015 }; 6016 6017 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6018 return llvm::makeArrayRef(GCCRegAliases); 6019 } 6020 6021 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6022 #define BUILTIN(ID, TYPE, ATTRS) \ 6023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6024 #include "clang/Basic/BuiltinsNEON.def" 6025 6026 #define BUILTIN(ID, TYPE, ATTRS) \ 6027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6028 #include "clang/Basic/BuiltinsAArch64.def" 6029 }; 6030 6031 class AArch64leTargetInfo : public AArch64TargetInfo { 6032 void setDataLayout() override { 6033 if (getTriple().isOSBinFormatMachO()) 6034 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6035 else 6036 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6037 } 6038 6039 public: 6040 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6041 : AArch64TargetInfo(Triple, Opts) { 6042 } 6043 void getTargetDefines(const LangOptions &Opts, 6044 MacroBuilder &Builder) const override { 6045 Builder.defineMacro("__AARCH64EL__"); 6046 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6047 } 6048 }; 6049 6050 class AArch64beTargetInfo : public AArch64TargetInfo { 6051 void setDataLayout() override { 6052 assert(!getTriple().isOSBinFormatMachO()); 6053 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6054 } 6055 6056 public: 6057 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6058 : AArch64TargetInfo(Triple, Opts) {} 6059 void getTargetDefines(const LangOptions &Opts, 6060 MacroBuilder &Builder) const override { 6061 Builder.defineMacro("__AARCH64EB__"); 6062 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6063 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6064 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6065 } 6066 }; 6067 6068 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6069 protected: 6070 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6071 MacroBuilder &Builder) const override { 6072 Builder.defineMacro("__AARCH64_SIMD__"); 6073 Builder.defineMacro("__ARM64_ARCH_8__"); 6074 Builder.defineMacro("__ARM_NEON__"); 6075 Builder.defineMacro("__LITTLE_ENDIAN__"); 6076 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6077 Builder.defineMacro("__arm64", "1"); 6078 Builder.defineMacro("__arm64__", "1"); 6079 6080 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6081 } 6082 6083 public: 6084 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6085 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6086 Int64Type = SignedLongLong; 6087 WCharType = SignedInt; 6088 UseSignedCharForObjCBool = false; 6089 6090 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6091 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6092 6093 TheCXXABI.set(TargetCXXABI::iOS64); 6094 } 6095 6096 BuiltinVaListKind getBuiltinVaListKind() const override { 6097 return TargetInfo::CharPtrBuiltinVaList; 6098 } 6099 }; 6100 6101 // Hexagon abstract base class 6102 class HexagonTargetInfo : public TargetInfo { 6103 static const Builtin::Info BuiltinInfo[]; 6104 static const char * const GCCRegNames[]; 6105 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6106 std::string CPU; 6107 bool HasHVX, HasHVXDouble; 6108 bool UseLongCalls; 6109 6110 public: 6111 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6112 : TargetInfo(Triple) { 6113 // Specify the vector alignment explicitly. For v512x1, the calculated 6114 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6115 // the required minimum of 64 bytes. 6116 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6117 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6118 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6119 SizeType = UnsignedInt; 6120 PtrDiffType = SignedInt; 6121 IntPtrType = SignedInt; 6122 6123 // {} in inline assembly are packet specifiers, not assembly variant 6124 // specifiers. 6125 NoAsmVariants = true; 6126 6127 LargeArrayMinWidth = 64; 6128 LargeArrayAlign = 64; 6129 UseBitFieldTypeAlignment = true; 6130 ZeroLengthBitfieldBoundary = 32; 6131 HasHVX = HasHVXDouble = false; 6132 UseLongCalls = false; 6133 } 6134 6135 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6136 return llvm::makeArrayRef(BuiltinInfo, 6137 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6138 } 6139 6140 bool validateAsmConstraint(const char *&Name, 6141 TargetInfo::ConstraintInfo &Info) const override { 6142 switch (*Name) { 6143 case 'v': 6144 case 'q': 6145 if (HasHVX) { 6146 Info.setAllowsRegister(); 6147 return true; 6148 } 6149 break; 6150 case 's': 6151 // Relocatable constant. 6152 return true; 6153 } 6154 return false; 6155 } 6156 6157 void getTargetDefines(const LangOptions &Opts, 6158 MacroBuilder &Builder) const override; 6159 6160 bool isCLZForZeroUndef() const override { return false; } 6161 6162 bool hasFeature(StringRef Feature) const override { 6163 return llvm::StringSwitch<bool>(Feature) 6164 .Case("hexagon", true) 6165 .Case("hvx", HasHVX) 6166 .Case("hvx-double", HasHVXDouble) 6167 .Case("long-calls", UseLongCalls) 6168 .Default(false); 6169 } 6170 6171 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6172 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6173 const override; 6174 6175 bool handleTargetFeatures(std::vector<std::string> &Features, 6176 DiagnosticsEngine &Diags) override; 6177 6178 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6179 bool Enabled) const override; 6180 6181 BuiltinVaListKind getBuiltinVaListKind() const override { 6182 return TargetInfo::CharPtrBuiltinVaList; 6183 } 6184 ArrayRef<const char *> getGCCRegNames() const override; 6185 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6186 const char *getClobbers() const override { 6187 return ""; 6188 } 6189 6190 static const char *getHexagonCPUSuffix(StringRef Name) { 6191 return llvm::StringSwitch<const char*>(Name) 6192 .Case("hexagonv4", "4") 6193 .Case("hexagonv5", "5") 6194 .Case("hexagonv55", "55") 6195 .Case("hexagonv60", "60") 6196 .Default(nullptr); 6197 } 6198 6199 bool setCPU(const std::string &Name) override { 6200 if (!getHexagonCPUSuffix(Name)) 6201 return false; 6202 CPU = Name; 6203 return true; 6204 } 6205 6206 int getEHDataRegisterNumber(unsigned RegNo) const override { 6207 return RegNo < 2 ? RegNo : -1; 6208 } 6209 }; 6210 6211 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6212 MacroBuilder &Builder) const { 6213 Builder.defineMacro("__qdsp6__", "1"); 6214 Builder.defineMacro("__hexagon__", "1"); 6215 6216 if (CPU == "hexagonv4") { 6217 Builder.defineMacro("__HEXAGON_V4__"); 6218 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6219 if (Opts.HexagonQdsp6Compat) { 6220 Builder.defineMacro("__QDSP6_V4__"); 6221 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6222 } 6223 } else if (CPU == "hexagonv5") { 6224 Builder.defineMacro("__HEXAGON_V5__"); 6225 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6226 if(Opts.HexagonQdsp6Compat) { 6227 Builder.defineMacro("__QDSP6_V5__"); 6228 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6229 } 6230 } else if (CPU == "hexagonv55") { 6231 Builder.defineMacro("__HEXAGON_V55__"); 6232 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6233 Builder.defineMacro("__QDSP6_V55__"); 6234 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6235 } else if (CPU == "hexagonv60") { 6236 Builder.defineMacro("__HEXAGON_V60__"); 6237 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6238 Builder.defineMacro("__QDSP6_V60__"); 6239 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6240 } 6241 6242 if (hasFeature("hvx")) { 6243 Builder.defineMacro("__HVX__"); 6244 if (hasFeature("hvx-double")) 6245 Builder.defineMacro("__HVXDBL__"); 6246 } 6247 } 6248 6249 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6250 DiagnosticsEngine &Diags, StringRef CPU, 6251 const std::vector<std::string> &FeaturesVec) const { 6252 // Default for v60: -hvx, -hvx-double. 6253 Features["hvx"] = false; 6254 Features["hvx-double"] = false; 6255 Features["long-calls"] = false; 6256 6257 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6258 } 6259 6260 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6261 DiagnosticsEngine &Diags) { 6262 for (auto &F : Features) { 6263 if (F == "+hvx") 6264 HasHVX = true; 6265 else if (F == "-hvx") 6266 HasHVX = HasHVXDouble = false; 6267 else if (F == "+hvx-double") 6268 HasHVX = HasHVXDouble = true; 6269 else if (F == "-hvx-double") 6270 HasHVXDouble = false; 6271 6272 if (F == "+long-calls") 6273 UseLongCalls = true; 6274 else if (F == "-long-calls") 6275 UseLongCalls = false; 6276 } 6277 return true; 6278 } 6279 6280 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6281 StringRef Name, bool Enabled) const { 6282 if (Enabled) { 6283 if (Name == "hvx-double") 6284 Features["hvx"] = true; 6285 } else { 6286 if (Name == "hvx") 6287 Features["hvx-double"] = false; 6288 } 6289 Features[Name] = Enabled; 6290 } 6291 6292 const char *const HexagonTargetInfo::GCCRegNames[] = { 6293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6295 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6296 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6297 "p0", "p1", "p2", "p3", 6298 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6299 }; 6300 6301 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6302 return llvm::makeArrayRef(GCCRegNames); 6303 } 6304 6305 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6306 { { "sp" }, "r29" }, 6307 { { "fp" }, "r30" }, 6308 { { "lr" }, "r31" }, 6309 }; 6310 6311 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6312 return llvm::makeArrayRef(GCCRegAliases); 6313 } 6314 6315 6316 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6317 #define BUILTIN(ID, TYPE, ATTRS) \ 6318 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6319 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6320 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6321 #include "clang/Basic/BuiltinsHexagon.def" 6322 }; 6323 6324 class LanaiTargetInfo : public TargetInfo { 6325 // Class for Lanai (32-bit). 6326 // The CPU profiles supported by the Lanai backend 6327 enum CPUKind { 6328 CK_NONE, 6329 CK_V11, 6330 } CPU; 6331 6332 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6333 static const char *const GCCRegNames[]; 6334 6335 public: 6336 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6337 : TargetInfo(Triple) { 6338 // Description string has to be kept in sync with backend. 6339 resetDataLayout("E" // Big endian 6340 "-m:e" // ELF name manging 6341 "-p:32:32" // 32 bit pointers, 32 bit aligned 6342 "-i64:64" // 64 bit integers, 64 bit aligned 6343 "-a:0:32" // 32 bit alignment of objects of aggregate type 6344 "-n32" // 32 bit native integer width 6345 "-S64" // 64 bit natural stack alignment 6346 ); 6347 6348 // Setting RegParmMax equal to what mregparm was set to in the old 6349 // toolchain 6350 RegParmMax = 4; 6351 6352 // Set the default CPU to V11 6353 CPU = CK_V11; 6354 6355 // Temporary approach to make everything at least word-aligned and allow for 6356 // safely casting between pointers with different alignment requirements. 6357 // TODO: Remove this when there are no more cast align warnings on the 6358 // firmware. 6359 MinGlobalAlign = 32; 6360 } 6361 6362 void getTargetDefines(const LangOptions &Opts, 6363 MacroBuilder &Builder) const override { 6364 // Define __lanai__ when building for target lanai. 6365 Builder.defineMacro("__lanai__"); 6366 6367 // Set define for the CPU specified. 6368 switch (CPU) { 6369 case CK_V11: 6370 Builder.defineMacro("__LANAI_V11__"); 6371 break; 6372 case CK_NONE: 6373 llvm_unreachable("Unhandled target CPU"); 6374 } 6375 } 6376 6377 bool setCPU(const std::string &Name) override { 6378 CPU = llvm::StringSwitch<CPUKind>(Name) 6379 .Case("v11", CK_V11) 6380 .Default(CK_NONE); 6381 6382 return CPU != CK_NONE; 6383 } 6384 6385 bool hasFeature(StringRef Feature) const override { 6386 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6387 } 6388 6389 ArrayRef<const char *> getGCCRegNames() const override; 6390 6391 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6392 6393 BuiltinVaListKind getBuiltinVaListKind() const override { 6394 return TargetInfo::VoidPtrBuiltinVaList; 6395 } 6396 6397 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6398 6399 bool validateAsmConstraint(const char *&Name, 6400 TargetInfo::ConstraintInfo &info) const override { 6401 return false; 6402 } 6403 6404 const char *getClobbers() const override { return ""; } 6405 }; 6406 6407 const char *const LanaiTargetInfo::GCCRegNames[] = { 6408 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6409 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6410 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6411 6412 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6413 return llvm::makeArrayRef(GCCRegNames); 6414 } 6415 6416 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6417 {{"pc"}, "r2"}, 6418 {{"sp"}, "r4"}, 6419 {{"fp"}, "r5"}, 6420 {{"rv"}, "r8"}, 6421 {{"rr1"}, "r10"}, 6422 {{"rr2"}, "r11"}, 6423 {{"rca"}, "r15"}, 6424 }; 6425 6426 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6427 return llvm::makeArrayRef(GCCRegAliases); 6428 } 6429 6430 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6431 class SparcTargetInfo : public TargetInfo { 6432 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6433 static const char * const GCCRegNames[]; 6434 bool SoftFloat; 6435 public: 6436 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6437 : TargetInfo(Triple), SoftFloat(false) {} 6438 6439 int getEHDataRegisterNumber(unsigned RegNo) const override { 6440 if (RegNo == 0) return 24; 6441 if (RegNo == 1) return 25; 6442 return -1; 6443 } 6444 6445 bool handleTargetFeatures(std::vector<std::string> &Features, 6446 DiagnosticsEngine &Diags) override { 6447 // Check if software floating point is enabled 6448 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6449 if (Feature != Features.end()) { 6450 SoftFloat = true; 6451 } 6452 return true; 6453 } 6454 void getTargetDefines(const LangOptions &Opts, 6455 MacroBuilder &Builder) const override { 6456 DefineStd(Builder, "sparc", Opts); 6457 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6458 6459 if (SoftFloat) 6460 Builder.defineMacro("SOFT_FLOAT", "1"); 6461 } 6462 6463 bool hasFeature(StringRef Feature) const override { 6464 return llvm::StringSwitch<bool>(Feature) 6465 .Case("softfloat", SoftFloat) 6466 .Case("sparc", true) 6467 .Default(false); 6468 } 6469 6470 bool hasSjLjLowering() const override { 6471 return true; 6472 } 6473 6474 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6475 // FIXME: Implement! 6476 return None; 6477 } 6478 BuiltinVaListKind getBuiltinVaListKind() const override { 6479 return TargetInfo::VoidPtrBuiltinVaList; 6480 } 6481 ArrayRef<const char *> getGCCRegNames() const override; 6482 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6483 bool validateAsmConstraint(const char *&Name, 6484 TargetInfo::ConstraintInfo &info) const override { 6485 // FIXME: Implement! 6486 switch (*Name) { 6487 case 'I': // Signed 13-bit constant 6488 case 'J': // Zero 6489 case 'K': // 32-bit constant with the low 12 bits clear 6490 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6491 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6492 case 'N': // Same as 'K' but zext (required for SIMode) 6493 case 'O': // The constant 4096 6494 return true; 6495 } 6496 return false; 6497 } 6498 const char *getClobbers() const override { 6499 // FIXME: Implement! 6500 return ""; 6501 } 6502 6503 // No Sparc V7 for now, the backend doesn't support it anyway. 6504 enum CPUKind { 6505 CK_GENERIC, 6506 CK_V8, 6507 CK_SUPERSPARC, 6508 CK_SPARCLITE, 6509 CK_F934, 6510 CK_HYPERSPARC, 6511 CK_SPARCLITE86X, 6512 CK_SPARCLET, 6513 CK_TSC701, 6514 CK_V9, 6515 CK_ULTRASPARC, 6516 CK_ULTRASPARC3, 6517 CK_NIAGARA, 6518 CK_NIAGARA2, 6519 CK_NIAGARA3, 6520 CK_NIAGARA4, 6521 CK_MYRIAD2100, 6522 CK_MYRIAD2150, 6523 CK_MYRIAD2450, 6524 CK_LEON2, 6525 CK_LEON2_AT697E, 6526 CK_LEON2_AT697F, 6527 CK_LEON3, 6528 CK_LEON3_UT699, 6529 CK_LEON3_GR712RC, 6530 CK_LEON4, 6531 CK_LEON4_GR740 6532 } CPU = CK_GENERIC; 6533 6534 enum CPUGeneration { 6535 CG_V8, 6536 CG_V9, 6537 }; 6538 6539 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6540 switch (Kind) { 6541 case CK_GENERIC: 6542 case CK_V8: 6543 case CK_SUPERSPARC: 6544 case CK_SPARCLITE: 6545 case CK_F934: 6546 case CK_HYPERSPARC: 6547 case CK_SPARCLITE86X: 6548 case CK_SPARCLET: 6549 case CK_TSC701: 6550 case CK_MYRIAD2100: 6551 case CK_MYRIAD2150: 6552 case CK_MYRIAD2450: 6553 case CK_LEON2: 6554 case CK_LEON2_AT697E: 6555 case CK_LEON2_AT697F: 6556 case CK_LEON3: 6557 case CK_LEON3_UT699: 6558 case CK_LEON3_GR712RC: 6559 case CK_LEON4: 6560 case CK_LEON4_GR740: 6561 return CG_V8; 6562 case CK_V9: 6563 case CK_ULTRASPARC: 6564 case CK_ULTRASPARC3: 6565 case CK_NIAGARA: 6566 case CK_NIAGARA2: 6567 case CK_NIAGARA3: 6568 case CK_NIAGARA4: 6569 return CG_V9; 6570 } 6571 llvm_unreachable("Unexpected CPU kind"); 6572 } 6573 6574 CPUKind getCPUKind(StringRef Name) const { 6575 return llvm::StringSwitch<CPUKind>(Name) 6576 .Case("v8", CK_V8) 6577 .Case("supersparc", CK_SUPERSPARC) 6578 .Case("sparclite", CK_SPARCLITE) 6579 .Case("f934", CK_F934) 6580 .Case("hypersparc", CK_HYPERSPARC) 6581 .Case("sparclite86x", CK_SPARCLITE86X) 6582 .Case("sparclet", CK_SPARCLET) 6583 .Case("tsc701", CK_TSC701) 6584 .Case("v9", CK_V9) 6585 .Case("ultrasparc", CK_ULTRASPARC) 6586 .Case("ultrasparc3", CK_ULTRASPARC3) 6587 .Case("niagara", CK_NIAGARA) 6588 .Case("niagara2", CK_NIAGARA2) 6589 .Case("niagara3", CK_NIAGARA3) 6590 .Case("niagara4", CK_NIAGARA4) 6591 .Case("ma2100", CK_MYRIAD2100) 6592 .Case("ma2150", CK_MYRIAD2150) 6593 .Case("ma2450", CK_MYRIAD2450) 6594 // FIXME: the myriad2[.n] spellings are obsolete, 6595 // but a grace period is needed to allow updating dependent builds. 6596 .Case("myriad2", CK_MYRIAD2100) 6597 .Case("myriad2.1", CK_MYRIAD2100) 6598 .Case("myriad2.2", CK_MYRIAD2150) 6599 .Case("leon2", CK_LEON2) 6600 .Case("at697e", CK_LEON2_AT697E) 6601 .Case("at697f", CK_LEON2_AT697F) 6602 .Case("leon3", CK_LEON3) 6603 .Case("ut699", CK_LEON3_UT699) 6604 .Case("gr712rc", CK_LEON3_GR712RC) 6605 .Case("leon4", CK_LEON4) 6606 .Case("gr740", CK_LEON4_GR740) 6607 .Default(CK_GENERIC); 6608 } 6609 6610 bool setCPU(const std::string &Name) override { 6611 CPU = getCPUKind(Name); 6612 return CPU != CK_GENERIC; 6613 } 6614 }; 6615 6616 const char * const SparcTargetInfo::GCCRegNames[] = { 6617 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6618 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6619 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6620 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6621 }; 6622 6623 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6624 return llvm::makeArrayRef(GCCRegNames); 6625 } 6626 6627 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6628 { { "g0" }, "r0" }, 6629 { { "g1" }, "r1" }, 6630 { { "g2" }, "r2" }, 6631 { { "g3" }, "r3" }, 6632 { { "g4" }, "r4" }, 6633 { { "g5" }, "r5" }, 6634 { { "g6" }, "r6" }, 6635 { { "g7" }, "r7" }, 6636 { { "o0" }, "r8" }, 6637 { { "o1" }, "r9" }, 6638 { { "o2" }, "r10" }, 6639 { { "o3" }, "r11" }, 6640 { { "o4" }, "r12" }, 6641 { { "o5" }, "r13" }, 6642 { { "o6", "sp" }, "r14" }, 6643 { { "o7" }, "r15" }, 6644 { { "l0" }, "r16" }, 6645 { { "l1" }, "r17" }, 6646 { { "l2" }, "r18" }, 6647 { { "l3" }, "r19" }, 6648 { { "l4" }, "r20" }, 6649 { { "l5" }, "r21" }, 6650 { { "l6" }, "r22" }, 6651 { { "l7" }, "r23" }, 6652 { { "i0" }, "r24" }, 6653 { { "i1" }, "r25" }, 6654 { { "i2" }, "r26" }, 6655 { { "i3" }, "r27" }, 6656 { { "i4" }, "r28" }, 6657 { { "i5" }, "r29" }, 6658 { { "i6", "fp" }, "r30" }, 6659 { { "i7" }, "r31" }, 6660 }; 6661 6662 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6663 return llvm::makeArrayRef(GCCRegAliases); 6664 } 6665 6666 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6667 class SparcV8TargetInfo : public SparcTargetInfo { 6668 public: 6669 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6670 : SparcTargetInfo(Triple, Opts) { 6671 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6672 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6673 switch (getTriple().getOS()) { 6674 default: 6675 SizeType = UnsignedInt; 6676 IntPtrType = SignedInt; 6677 PtrDiffType = SignedInt; 6678 break; 6679 case llvm::Triple::NetBSD: 6680 case llvm::Triple::OpenBSD: 6681 SizeType = UnsignedLong; 6682 IntPtrType = SignedLong; 6683 PtrDiffType = SignedLong; 6684 break; 6685 } 6686 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6687 } 6688 6689 void getTargetDefines(const LangOptions &Opts, 6690 MacroBuilder &Builder) const override { 6691 SparcTargetInfo::getTargetDefines(Opts, Builder); 6692 switch (getCPUGeneration(CPU)) { 6693 case CG_V8: 6694 Builder.defineMacro("__sparcv8"); 6695 if (getTriple().getOS() != llvm::Triple::Solaris) 6696 Builder.defineMacro("__sparcv8__"); 6697 break; 6698 case CG_V9: 6699 Builder.defineMacro("__sparcv9"); 6700 if (getTriple().getOS() != llvm::Triple::Solaris) { 6701 Builder.defineMacro("__sparcv9__"); 6702 Builder.defineMacro("__sparc_v9__"); 6703 } 6704 break; 6705 } 6706 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6707 std::string MyriadArchValue, Myriad2Value; 6708 Builder.defineMacro("__sparc_v8__"); 6709 Builder.defineMacro("__leon__"); 6710 switch (CPU) { 6711 case CK_MYRIAD2150: 6712 MyriadArchValue = "__ma2150"; 6713 Myriad2Value = "2"; 6714 break; 6715 case CK_MYRIAD2450: 6716 MyriadArchValue = "__ma2450"; 6717 Myriad2Value = "2"; 6718 break; 6719 default: 6720 MyriadArchValue = "__ma2100"; 6721 Myriad2Value = "1"; 6722 break; 6723 } 6724 Builder.defineMacro(MyriadArchValue, "1"); 6725 Builder.defineMacro(MyriadArchValue+"__", "1"); 6726 Builder.defineMacro("__myriad2__", Myriad2Value); 6727 Builder.defineMacro("__myriad2", Myriad2Value); 6728 } 6729 } 6730 6731 bool hasSjLjLowering() const override { 6732 return true; 6733 } 6734 }; 6735 6736 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6737 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6738 public: 6739 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6740 : SparcV8TargetInfo(Triple, Opts) { 6741 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6742 } 6743 }; 6744 6745 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6746 class SparcV9TargetInfo : public SparcTargetInfo { 6747 public: 6748 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6749 : SparcTargetInfo(Triple, Opts) { 6750 // FIXME: Support Sparc quad-precision long double? 6751 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6752 // This is an LP64 platform. 6753 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6754 6755 // OpenBSD uses long long for int64_t and intmax_t. 6756 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6757 IntMaxType = SignedLongLong; 6758 else 6759 IntMaxType = SignedLong; 6760 Int64Type = IntMaxType; 6761 6762 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6763 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6764 LongDoubleWidth = 128; 6765 LongDoubleAlign = 128; 6766 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6767 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6768 } 6769 6770 void getTargetDefines(const LangOptions &Opts, 6771 MacroBuilder &Builder) const override { 6772 SparcTargetInfo::getTargetDefines(Opts, Builder); 6773 Builder.defineMacro("__sparcv9"); 6774 Builder.defineMacro("__arch64__"); 6775 // Solaris doesn't need these variants, but the BSDs do. 6776 if (getTriple().getOS() != llvm::Triple::Solaris) { 6777 Builder.defineMacro("__sparc64__"); 6778 Builder.defineMacro("__sparc_v9__"); 6779 Builder.defineMacro("__sparcv9__"); 6780 } 6781 } 6782 6783 bool setCPU(const std::string &Name) override { 6784 if (!SparcTargetInfo::setCPU(Name)) 6785 return false; 6786 return getCPUGeneration(CPU) == CG_V9; 6787 } 6788 }; 6789 6790 class SystemZTargetInfo : public TargetInfo { 6791 static const Builtin::Info BuiltinInfo[]; 6792 static const char *const GCCRegNames[]; 6793 std::string CPU; 6794 bool HasTransactionalExecution; 6795 bool HasVector; 6796 6797 public: 6798 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6799 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6800 HasVector(false) { 6801 IntMaxType = SignedLong; 6802 Int64Type = SignedLong; 6803 TLSSupported = true; 6804 IntWidth = IntAlign = 32; 6805 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6806 PointerWidth = PointerAlign = 64; 6807 LongDoubleWidth = 128; 6808 LongDoubleAlign = 64; 6809 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6810 DefaultAlignForAttributeAligned = 64; 6811 MinGlobalAlign = 16; 6812 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6813 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6814 } 6815 void getTargetDefines(const LangOptions &Opts, 6816 MacroBuilder &Builder) const override { 6817 Builder.defineMacro("__s390__"); 6818 Builder.defineMacro("__s390x__"); 6819 Builder.defineMacro("__zarch__"); 6820 Builder.defineMacro("__LONG_DOUBLE_128__"); 6821 6822 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6823 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6824 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6825 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6826 6827 if (HasTransactionalExecution) 6828 Builder.defineMacro("__HTM__"); 6829 if (Opts.ZVector) 6830 Builder.defineMacro("__VEC__", "10301"); 6831 } 6832 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6833 return llvm::makeArrayRef(BuiltinInfo, 6834 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6835 } 6836 6837 ArrayRef<const char *> getGCCRegNames() const override; 6838 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6839 // No aliases. 6840 return None; 6841 } 6842 bool validateAsmConstraint(const char *&Name, 6843 TargetInfo::ConstraintInfo &info) const override; 6844 const char *getClobbers() const override { 6845 // FIXME: Is this really right? 6846 return ""; 6847 } 6848 BuiltinVaListKind getBuiltinVaListKind() const override { 6849 return TargetInfo::SystemZBuiltinVaList; 6850 } 6851 bool setCPU(const std::string &Name) override { 6852 CPU = Name; 6853 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6854 .Case("z10", true) 6855 .Case("z196", true) 6856 .Case("zEC12", true) 6857 .Case("z13", true) 6858 .Default(false); 6859 6860 return CPUKnown; 6861 } 6862 bool 6863 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6864 StringRef CPU, 6865 const std::vector<std::string> &FeaturesVec) const override { 6866 if (CPU == "zEC12") 6867 Features["transactional-execution"] = true; 6868 if (CPU == "z13") { 6869 Features["transactional-execution"] = true; 6870 Features["vector"] = true; 6871 } 6872 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6873 } 6874 6875 bool handleTargetFeatures(std::vector<std::string> &Features, 6876 DiagnosticsEngine &Diags) override { 6877 HasTransactionalExecution = false; 6878 for (const auto &Feature : Features) { 6879 if (Feature == "+transactional-execution") 6880 HasTransactionalExecution = true; 6881 else if (Feature == "+vector") 6882 HasVector = true; 6883 } 6884 // If we use the vector ABI, vector types are 64-bit aligned. 6885 if (HasVector) { 6886 MaxVectorAlign = 64; 6887 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6888 "-v128:64-a:8:16-n32:64"); 6889 } 6890 return true; 6891 } 6892 6893 bool hasFeature(StringRef Feature) const override { 6894 return llvm::StringSwitch<bool>(Feature) 6895 .Case("systemz", true) 6896 .Case("htm", HasTransactionalExecution) 6897 .Case("vx", HasVector) 6898 .Default(false); 6899 } 6900 6901 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6902 switch (CC) { 6903 case CC_C: 6904 case CC_Swift: 6905 return CCCR_OK; 6906 default: 6907 return CCCR_Warning; 6908 } 6909 } 6910 6911 StringRef getABI() const override { 6912 if (HasVector) 6913 return "vector"; 6914 return ""; 6915 } 6916 6917 bool useFloat128ManglingForLongDouble() const override { 6918 return true; 6919 } 6920 }; 6921 6922 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6923 #define BUILTIN(ID, TYPE, ATTRS) \ 6924 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6925 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6926 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6927 #include "clang/Basic/BuiltinsSystemZ.def" 6928 }; 6929 6930 const char *const SystemZTargetInfo::GCCRegNames[] = { 6931 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6932 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6933 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6934 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6935 }; 6936 6937 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6938 return llvm::makeArrayRef(GCCRegNames); 6939 } 6940 6941 bool SystemZTargetInfo:: 6942 validateAsmConstraint(const char *&Name, 6943 TargetInfo::ConstraintInfo &Info) const { 6944 switch (*Name) { 6945 default: 6946 return false; 6947 6948 case 'a': // Address register 6949 case 'd': // Data register (equivalent to 'r') 6950 case 'f': // Floating-point register 6951 Info.setAllowsRegister(); 6952 return true; 6953 6954 case 'I': // Unsigned 8-bit constant 6955 case 'J': // Unsigned 12-bit constant 6956 case 'K': // Signed 16-bit constant 6957 case 'L': // Signed 20-bit displacement (on all targets we support) 6958 case 'M': // 0x7fffffff 6959 return true; 6960 6961 case 'Q': // Memory with base and unsigned 12-bit displacement 6962 case 'R': // Likewise, plus an index 6963 case 'S': // Memory with base and signed 20-bit displacement 6964 case 'T': // Likewise, plus an index 6965 Info.setAllowsMemory(); 6966 return true; 6967 } 6968 } 6969 6970 class MSP430TargetInfo : public TargetInfo { 6971 static const char *const GCCRegNames[]; 6972 6973 public: 6974 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6975 : TargetInfo(Triple) { 6976 TLSSupported = false; 6977 IntWidth = 16; 6978 IntAlign = 16; 6979 LongWidth = 32; 6980 LongLongWidth = 64; 6981 LongAlign = LongLongAlign = 16; 6982 PointerWidth = 16; 6983 PointerAlign = 16; 6984 SuitableAlign = 16; 6985 SizeType = UnsignedInt; 6986 IntMaxType = SignedLongLong; 6987 IntPtrType = SignedInt; 6988 PtrDiffType = SignedInt; 6989 SigAtomicType = SignedLong; 6990 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6991 } 6992 void getTargetDefines(const LangOptions &Opts, 6993 MacroBuilder &Builder) const override { 6994 Builder.defineMacro("MSP430"); 6995 Builder.defineMacro("__MSP430__"); 6996 // FIXME: defines for different 'flavours' of MCU 6997 } 6998 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6999 // FIXME: Implement. 7000 return None; 7001 } 7002 bool hasFeature(StringRef Feature) const override { 7003 return Feature == "msp430"; 7004 } 7005 ArrayRef<const char *> getGCCRegNames() const override; 7006 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7007 // No aliases. 7008 return None; 7009 } 7010 bool validateAsmConstraint(const char *&Name, 7011 TargetInfo::ConstraintInfo &info) const override { 7012 // FIXME: implement 7013 switch (*Name) { 7014 case 'K': // the constant 1 7015 case 'L': // constant -1^20 .. 1^19 7016 case 'M': // constant 1-4: 7017 return true; 7018 } 7019 // No target constraints for now. 7020 return false; 7021 } 7022 const char *getClobbers() const override { 7023 // FIXME: Is this really right? 7024 return ""; 7025 } 7026 BuiltinVaListKind getBuiltinVaListKind() const override { 7027 // FIXME: implement 7028 return TargetInfo::CharPtrBuiltinVaList; 7029 } 7030 }; 7031 7032 const char *const MSP430TargetInfo::GCCRegNames[] = { 7033 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7034 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7035 7036 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7037 return llvm::makeArrayRef(GCCRegNames); 7038 } 7039 7040 // LLVM and Clang cannot be used directly to output native binaries for 7041 // target, but is used to compile C code to llvm bitcode with correct 7042 // type and alignment information. 7043 // 7044 // TCE uses the llvm bitcode as input and uses it for generating customized 7045 // target processor and program binary. TCE co-design environment is 7046 // publicly available in http://tce.cs.tut.fi 7047 7048 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7049 3, // opencl_global 7050 4, // opencl_local 7051 5, // opencl_constant 7052 // FIXME: generic has to be added to the target 7053 0, // opencl_generic 7054 0, // cuda_device 7055 0, // cuda_constant 7056 0 // cuda_shared 7057 }; 7058 7059 class TCETargetInfo : public TargetInfo { 7060 public: 7061 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7062 : TargetInfo(Triple) { 7063 TLSSupported = false; 7064 IntWidth = 32; 7065 LongWidth = LongLongWidth = 32; 7066 PointerWidth = 32; 7067 IntAlign = 32; 7068 LongAlign = LongLongAlign = 32; 7069 PointerAlign = 32; 7070 SuitableAlign = 32; 7071 SizeType = UnsignedInt; 7072 IntMaxType = SignedLong; 7073 IntPtrType = SignedInt; 7074 PtrDiffType = SignedInt; 7075 FloatWidth = 32; 7076 FloatAlign = 32; 7077 DoubleWidth = 32; 7078 DoubleAlign = 32; 7079 LongDoubleWidth = 32; 7080 LongDoubleAlign = 32; 7081 FloatFormat = &llvm::APFloat::IEEEsingle; 7082 DoubleFormat = &llvm::APFloat::IEEEsingle; 7083 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7084 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7085 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7086 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7087 UseAddrSpaceMapMangling = true; 7088 } 7089 7090 void getTargetDefines(const LangOptions &Opts, 7091 MacroBuilder &Builder) const override { 7092 DefineStd(Builder, "tce", Opts); 7093 Builder.defineMacro("__TCE__"); 7094 Builder.defineMacro("__TCE_V1__"); 7095 } 7096 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7097 7098 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7099 const char *getClobbers() const override { return ""; } 7100 BuiltinVaListKind getBuiltinVaListKind() const override { 7101 return TargetInfo::VoidPtrBuiltinVaList; 7102 } 7103 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7104 bool validateAsmConstraint(const char *&Name, 7105 TargetInfo::ConstraintInfo &info) const override { 7106 return true; 7107 } 7108 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7109 return None; 7110 } 7111 }; 7112 7113 class BPFTargetInfo : public TargetInfo { 7114 public: 7115 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7116 : TargetInfo(Triple) { 7117 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7118 SizeType = UnsignedLong; 7119 PtrDiffType = SignedLong; 7120 IntPtrType = SignedLong; 7121 IntMaxType = SignedLong; 7122 Int64Type = SignedLong; 7123 RegParmMax = 5; 7124 if (Triple.getArch() == llvm::Triple::bpfeb) { 7125 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7126 } else { 7127 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7128 } 7129 MaxAtomicPromoteWidth = 64; 7130 MaxAtomicInlineWidth = 64; 7131 TLSSupported = false; 7132 } 7133 void getTargetDefines(const LangOptions &Opts, 7134 MacroBuilder &Builder) const override { 7135 DefineStd(Builder, "bpf", Opts); 7136 Builder.defineMacro("__BPF__"); 7137 } 7138 bool hasFeature(StringRef Feature) const override { 7139 return Feature == "bpf"; 7140 } 7141 7142 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7143 const char *getClobbers() const override { 7144 return ""; 7145 } 7146 BuiltinVaListKind getBuiltinVaListKind() const override { 7147 return TargetInfo::VoidPtrBuiltinVaList; 7148 } 7149 ArrayRef<const char *> getGCCRegNames() const override { 7150 return None; 7151 } 7152 bool validateAsmConstraint(const char *&Name, 7153 TargetInfo::ConstraintInfo &info) const override { 7154 return true; 7155 } 7156 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7157 return None; 7158 } 7159 }; 7160 7161 class MipsTargetInfo : public TargetInfo { 7162 void setDataLayout() { 7163 StringRef Layout; 7164 7165 if (ABI == "o32") 7166 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7167 else if (ABI == "n32") 7168 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7169 else if (ABI == "n64") 7170 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7171 else 7172 llvm_unreachable("Invalid ABI"); 7173 7174 if (BigEndian) 7175 resetDataLayout(("E-" + Layout).str()); 7176 else 7177 resetDataLayout(("e-" + Layout).str()); 7178 } 7179 7180 7181 static const Builtin::Info BuiltinInfo[]; 7182 std::string CPU; 7183 bool IsMips16; 7184 bool IsMicromips; 7185 bool IsNan2008; 7186 bool IsSingleFloat; 7187 enum MipsFloatABI { 7188 HardFloat, SoftFloat 7189 } FloatABI; 7190 enum DspRevEnum { 7191 NoDSP, DSP1, DSP2 7192 } DspRev; 7193 bool HasMSA; 7194 7195 protected: 7196 bool HasFP64; 7197 std::string ABI; 7198 7199 public: 7200 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7201 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7202 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7203 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7204 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7205 7206 setABI((getTriple().getArch() == llvm::Triple::mips || 7207 getTriple().getArch() == llvm::Triple::mipsel) 7208 ? "o32" 7209 : "n64"); 7210 7211 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7212 } 7213 7214 bool isNaN2008Default() const { 7215 return CPU == "mips32r6" || CPU == "mips64r6"; 7216 } 7217 7218 bool isFP64Default() const { 7219 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7220 } 7221 7222 bool isNan2008() const override { 7223 return IsNan2008; 7224 } 7225 7226 bool processorSupportsGPR64() const { 7227 return llvm::StringSwitch<bool>(CPU) 7228 .Case("mips3", true) 7229 .Case("mips4", true) 7230 .Case("mips5", true) 7231 .Case("mips64", true) 7232 .Case("mips64r2", true) 7233 .Case("mips64r3", true) 7234 .Case("mips64r5", true) 7235 .Case("mips64r6", true) 7236 .Case("octeon", true) 7237 .Default(false); 7238 return false; 7239 } 7240 7241 StringRef getABI() const override { return ABI; } 7242 bool setABI(const std::string &Name) override { 7243 if (Name == "o32") { 7244 setO32ABITypes(); 7245 ABI = Name; 7246 return true; 7247 } 7248 7249 if (Name == "n32") { 7250 setN32ABITypes(); 7251 ABI = Name; 7252 return true; 7253 } 7254 if (Name == "n64") { 7255 setN64ABITypes(); 7256 ABI = Name; 7257 return true; 7258 } 7259 return false; 7260 } 7261 7262 void setO32ABITypes() { 7263 Int64Type = SignedLongLong; 7264 IntMaxType = Int64Type; 7265 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7266 LongDoubleWidth = LongDoubleAlign = 64; 7267 LongWidth = LongAlign = 32; 7268 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7269 PointerWidth = PointerAlign = 32; 7270 PtrDiffType = SignedInt; 7271 SizeType = UnsignedInt; 7272 SuitableAlign = 64; 7273 } 7274 7275 void setN32N64ABITypes() { 7276 LongDoubleWidth = LongDoubleAlign = 128; 7277 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7278 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7279 LongDoubleWidth = LongDoubleAlign = 64; 7280 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7281 } 7282 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7283 SuitableAlign = 128; 7284 } 7285 7286 void setN64ABITypes() { 7287 setN32N64ABITypes(); 7288 Int64Type = SignedLong; 7289 IntMaxType = Int64Type; 7290 LongWidth = LongAlign = 64; 7291 PointerWidth = PointerAlign = 64; 7292 PtrDiffType = SignedLong; 7293 SizeType = UnsignedLong; 7294 } 7295 7296 void setN32ABITypes() { 7297 setN32N64ABITypes(); 7298 Int64Type = SignedLongLong; 7299 IntMaxType = Int64Type; 7300 LongWidth = LongAlign = 32; 7301 PointerWidth = PointerAlign = 32; 7302 PtrDiffType = SignedInt; 7303 SizeType = UnsignedInt; 7304 } 7305 7306 bool setCPU(const std::string &Name) override { 7307 CPU = Name; 7308 return llvm::StringSwitch<bool>(Name) 7309 .Case("mips1", true) 7310 .Case("mips2", true) 7311 .Case("mips3", true) 7312 .Case("mips4", true) 7313 .Case("mips5", true) 7314 .Case("mips32", true) 7315 .Case("mips32r2", true) 7316 .Case("mips32r3", true) 7317 .Case("mips32r5", true) 7318 .Case("mips32r6", true) 7319 .Case("mips64", true) 7320 .Case("mips64r2", true) 7321 .Case("mips64r3", true) 7322 .Case("mips64r5", true) 7323 .Case("mips64r6", true) 7324 .Case("octeon", true) 7325 .Case("p5600", true) 7326 .Default(false); 7327 } 7328 const std::string& getCPU() const { return CPU; } 7329 bool 7330 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7331 StringRef CPU, 7332 const std::vector<std::string> &FeaturesVec) const override { 7333 if (CPU.empty()) 7334 CPU = getCPU(); 7335 if (CPU == "octeon") 7336 Features["mips64r2"] = Features["cnmips"] = true; 7337 else 7338 Features[CPU] = true; 7339 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7340 } 7341 7342 void getTargetDefines(const LangOptions &Opts, 7343 MacroBuilder &Builder) const override { 7344 if (BigEndian) { 7345 DefineStd(Builder, "MIPSEB", Opts); 7346 Builder.defineMacro("_MIPSEB"); 7347 } else { 7348 DefineStd(Builder, "MIPSEL", Opts); 7349 Builder.defineMacro("_MIPSEL"); 7350 } 7351 7352 Builder.defineMacro("__mips__"); 7353 Builder.defineMacro("_mips"); 7354 if (Opts.GNUMode) 7355 Builder.defineMacro("mips"); 7356 7357 if (ABI == "o32") { 7358 Builder.defineMacro("__mips", "32"); 7359 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7360 } else { 7361 Builder.defineMacro("__mips", "64"); 7362 Builder.defineMacro("__mips64"); 7363 Builder.defineMacro("__mips64__"); 7364 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7365 } 7366 7367 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7368 .Cases("mips32", "mips64", "1") 7369 .Cases("mips32r2", "mips64r2", "2") 7370 .Cases("mips32r3", "mips64r3", "3") 7371 .Cases("mips32r5", "mips64r5", "5") 7372 .Cases("mips32r6", "mips64r6", "6") 7373 .Default(""); 7374 if (!ISARev.empty()) 7375 Builder.defineMacro("__mips_isa_rev", ISARev); 7376 7377 if (ABI == "o32") { 7378 Builder.defineMacro("__mips_o32"); 7379 Builder.defineMacro("_ABIO32", "1"); 7380 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7381 } else if (ABI == "n32") { 7382 Builder.defineMacro("__mips_n32"); 7383 Builder.defineMacro("_ABIN32", "2"); 7384 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7385 } else if (ABI == "n64") { 7386 Builder.defineMacro("__mips_n64"); 7387 Builder.defineMacro("_ABI64", "3"); 7388 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7389 } else 7390 llvm_unreachable("Invalid ABI."); 7391 7392 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7393 7394 switch (FloatABI) { 7395 case HardFloat: 7396 Builder.defineMacro("__mips_hard_float", Twine(1)); 7397 break; 7398 case SoftFloat: 7399 Builder.defineMacro("__mips_soft_float", Twine(1)); 7400 break; 7401 } 7402 7403 if (IsSingleFloat) 7404 Builder.defineMacro("__mips_single_float", Twine(1)); 7405 7406 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7407 Builder.defineMacro("_MIPS_FPSET", 7408 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7409 7410 if (IsMips16) 7411 Builder.defineMacro("__mips16", Twine(1)); 7412 7413 if (IsMicromips) 7414 Builder.defineMacro("__mips_micromips", Twine(1)); 7415 7416 if (IsNan2008) 7417 Builder.defineMacro("__mips_nan2008", Twine(1)); 7418 7419 switch (DspRev) { 7420 default: 7421 break; 7422 case DSP1: 7423 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7424 Builder.defineMacro("__mips_dsp", Twine(1)); 7425 break; 7426 case DSP2: 7427 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7428 Builder.defineMacro("__mips_dspr2", Twine(1)); 7429 Builder.defineMacro("__mips_dsp", Twine(1)); 7430 break; 7431 } 7432 7433 if (HasMSA) 7434 Builder.defineMacro("__mips_msa", Twine(1)); 7435 7436 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7437 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7438 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7439 7440 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7441 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7442 7443 // These shouldn't be defined for MIPS-I but there's no need to check 7444 // for that since MIPS-I isn't supported. 7445 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7446 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7447 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7448 7449 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7450 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7451 // the instructions exist but using them violates the ABI since they 7452 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7453 if (ABI == "n32" || ABI == "n64") 7454 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7455 } 7456 7457 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7458 return llvm::makeArrayRef(BuiltinInfo, 7459 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7460 } 7461 bool hasFeature(StringRef Feature) const override { 7462 return llvm::StringSwitch<bool>(Feature) 7463 .Case("mips", true) 7464 .Case("fp64", HasFP64) 7465 .Default(false); 7466 } 7467 BuiltinVaListKind getBuiltinVaListKind() const override { 7468 return TargetInfo::VoidPtrBuiltinVaList; 7469 } 7470 ArrayRef<const char *> getGCCRegNames() const override { 7471 static const char *const GCCRegNames[] = { 7472 // CPU register names 7473 // Must match second column of GCCRegAliases 7474 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7475 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7476 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7477 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7478 // Floating point register names 7479 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7480 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7481 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7482 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7483 // Hi/lo and condition register names 7484 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7485 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7486 "$ac3hi","$ac3lo", 7487 // MSA register names 7488 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7489 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7490 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7491 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7492 // MSA control register names 7493 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7494 "$msarequest", "$msamap", "$msaunmap" 7495 }; 7496 return llvm::makeArrayRef(GCCRegNames); 7497 } 7498 bool validateAsmConstraint(const char *&Name, 7499 TargetInfo::ConstraintInfo &Info) const override { 7500 switch (*Name) { 7501 default: 7502 return false; 7503 case 'r': // CPU registers. 7504 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7505 case 'y': // Equivalent to "r", backward compatibility only. 7506 case 'f': // floating-point registers. 7507 case 'c': // $25 for indirect jumps 7508 case 'l': // lo register 7509 case 'x': // hilo register pair 7510 Info.setAllowsRegister(); 7511 return true; 7512 case 'I': // Signed 16-bit constant 7513 case 'J': // Integer 0 7514 case 'K': // Unsigned 16-bit constant 7515 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7516 case 'M': // Constants not loadable via lui, addiu, or ori 7517 case 'N': // Constant -1 to -65535 7518 case 'O': // A signed 15-bit constant 7519 case 'P': // A constant between 1 go 65535 7520 return true; 7521 case 'R': // An address that can be used in a non-macro load or store 7522 Info.setAllowsMemory(); 7523 return true; 7524 case 'Z': 7525 if (Name[1] == 'C') { // An address usable by ll, and sc. 7526 Info.setAllowsMemory(); 7527 Name++; // Skip over 'Z'. 7528 return true; 7529 } 7530 return false; 7531 } 7532 } 7533 7534 std::string convertConstraint(const char *&Constraint) const override { 7535 std::string R; 7536 switch (*Constraint) { 7537 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7538 if (Constraint[1] == 'C') { 7539 R = std::string("^") + std::string(Constraint, 2); 7540 Constraint++; 7541 return R; 7542 } 7543 break; 7544 } 7545 return TargetInfo::convertConstraint(Constraint); 7546 } 7547 7548 const char *getClobbers() const override { 7549 // In GCC, $1 is not widely used in generated code (it's used only in a few 7550 // specific situations), so there is no real need for users to add it to 7551 // the clobbers list if they want to use it in their inline assembly code. 7552 // 7553 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7554 // code generation, so using it in inline assembly without adding it to the 7555 // clobbers list can cause conflicts between the inline assembly code and 7556 // the surrounding generated code. 7557 // 7558 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7559 // operands, which will conflict with the ".set at" assembler option (which 7560 // we use only for inline assembly, in order to maintain compatibility with 7561 // GCC) and will also conflict with the user's usage of $1. 7562 // 7563 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7564 // register for generated code is to automatically clobber $1 for all inline 7565 // assembly code. 7566 // 7567 // FIXME: We should automatically clobber $1 only for inline assembly code 7568 // which actually uses it. This would allow LLVM to use $1 for inline 7569 // assembly operands if the user's assembly code doesn't use it. 7570 return "~{$1}"; 7571 } 7572 7573 bool handleTargetFeatures(std::vector<std::string> &Features, 7574 DiagnosticsEngine &Diags) override { 7575 IsMips16 = false; 7576 IsMicromips = false; 7577 IsNan2008 = isNaN2008Default(); 7578 IsSingleFloat = false; 7579 FloatABI = HardFloat; 7580 DspRev = NoDSP; 7581 HasFP64 = isFP64Default(); 7582 7583 for (const auto &Feature : Features) { 7584 if (Feature == "+single-float") 7585 IsSingleFloat = true; 7586 else if (Feature == "+soft-float") 7587 FloatABI = SoftFloat; 7588 else if (Feature == "+mips16") 7589 IsMips16 = true; 7590 else if (Feature == "+micromips") 7591 IsMicromips = true; 7592 else if (Feature == "+dsp") 7593 DspRev = std::max(DspRev, DSP1); 7594 else if (Feature == "+dspr2") 7595 DspRev = std::max(DspRev, DSP2); 7596 else if (Feature == "+msa") 7597 HasMSA = true; 7598 else if (Feature == "+fp64") 7599 HasFP64 = true; 7600 else if (Feature == "-fp64") 7601 HasFP64 = false; 7602 else if (Feature == "+nan2008") 7603 IsNan2008 = true; 7604 else if (Feature == "-nan2008") 7605 IsNan2008 = false; 7606 } 7607 7608 setDataLayout(); 7609 7610 return true; 7611 } 7612 7613 int getEHDataRegisterNumber(unsigned RegNo) const override { 7614 if (RegNo == 0) return 4; 7615 if (RegNo == 1) return 5; 7616 return -1; 7617 } 7618 7619 bool isCLZForZeroUndef() const override { return false; } 7620 7621 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7622 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7623 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7624 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7625 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7626 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7627 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7628 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7629 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7630 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7631 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7632 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7633 {{"ra"}, "$31"}}; 7634 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7635 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7636 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7637 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7638 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7639 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7640 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7641 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7642 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7643 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7644 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7645 {{"ra"}, "$31"}}; 7646 if (ABI == "o32") 7647 return llvm::makeArrayRef(O32RegAliases); 7648 return llvm::makeArrayRef(NewABIRegAliases); 7649 } 7650 7651 bool hasInt128Type() const override { 7652 return ABI == "n32" || ABI == "n64"; 7653 } 7654 7655 bool validateTarget(DiagnosticsEngine &Diags) const override { 7656 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7657 // this yet. It's better to fail here than on the backend assertion. 7658 if (processorSupportsGPR64() && ABI == "o32") { 7659 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7660 return false; 7661 } 7662 7663 // 64-bit ABI's require 64-bit CPU's. 7664 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7665 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7666 return false; 7667 } 7668 7669 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7670 // can't handle this yet. It's better to fail here than on the 7671 // backend assertion. 7672 if ((getTriple().getArch() == llvm::Triple::mips64 || 7673 getTriple().getArch() == llvm::Triple::mips64el) && 7674 ABI == "o32") { 7675 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7676 << ABI << getTriple().str(); 7677 return false; 7678 } 7679 7680 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7681 // can't handle this yet. It's better to fail here than on the 7682 // backend assertion. 7683 if ((getTriple().getArch() == llvm::Triple::mips || 7684 getTriple().getArch() == llvm::Triple::mipsel) && 7685 (ABI == "n32" || ABI == "n64")) { 7686 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7687 << ABI << getTriple().str(); 7688 return false; 7689 } 7690 7691 return true; 7692 } 7693 }; 7694 7695 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7696 #define BUILTIN(ID, TYPE, ATTRS) \ 7697 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7698 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7699 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7700 #include "clang/Basic/BuiltinsMips.def" 7701 }; 7702 7703 class PNaClTargetInfo : public TargetInfo { 7704 public: 7705 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7706 : TargetInfo(Triple) { 7707 this->LongAlign = 32; 7708 this->LongWidth = 32; 7709 this->PointerAlign = 32; 7710 this->PointerWidth = 32; 7711 this->IntMaxType = TargetInfo::SignedLongLong; 7712 this->Int64Type = TargetInfo::SignedLongLong; 7713 this->DoubleAlign = 64; 7714 this->LongDoubleWidth = 64; 7715 this->LongDoubleAlign = 64; 7716 this->SizeType = TargetInfo::UnsignedInt; 7717 this->PtrDiffType = TargetInfo::SignedInt; 7718 this->IntPtrType = TargetInfo::SignedInt; 7719 this->RegParmMax = 0; // Disallow regparm 7720 } 7721 7722 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7723 Builder.defineMacro("__le32__"); 7724 Builder.defineMacro("__pnacl__"); 7725 } 7726 void getTargetDefines(const LangOptions &Opts, 7727 MacroBuilder &Builder) const override { 7728 getArchDefines(Opts, Builder); 7729 } 7730 bool hasFeature(StringRef Feature) const override { 7731 return Feature == "pnacl"; 7732 } 7733 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7734 BuiltinVaListKind getBuiltinVaListKind() const override { 7735 return TargetInfo::PNaClABIBuiltinVaList; 7736 } 7737 ArrayRef<const char *> getGCCRegNames() const override; 7738 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7739 bool validateAsmConstraint(const char *&Name, 7740 TargetInfo::ConstraintInfo &Info) const override { 7741 return false; 7742 } 7743 7744 const char *getClobbers() const override { 7745 return ""; 7746 } 7747 }; 7748 7749 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7750 return None; 7751 } 7752 7753 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7754 return None; 7755 } 7756 7757 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7758 class NaClMips32TargetInfo : public MipsTargetInfo { 7759 public: 7760 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7761 : MipsTargetInfo(Triple, Opts) {} 7762 7763 BuiltinVaListKind getBuiltinVaListKind() const override { 7764 return TargetInfo::PNaClABIBuiltinVaList; 7765 } 7766 }; 7767 7768 class Le64TargetInfo : public TargetInfo { 7769 static const Builtin::Info BuiltinInfo[]; 7770 7771 public: 7772 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7773 : TargetInfo(Triple) { 7774 NoAsmVariants = true; 7775 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7776 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7777 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7778 } 7779 7780 void getTargetDefines(const LangOptions &Opts, 7781 MacroBuilder &Builder) const override { 7782 DefineStd(Builder, "unix", Opts); 7783 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7784 Builder.defineMacro("__ELF__"); 7785 } 7786 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7787 return llvm::makeArrayRef(BuiltinInfo, 7788 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7789 } 7790 BuiltinVaListKind getBuiltinVaListKind() const override { 7791 return TargetInfo::PNaClABIBuiltinVaList; 7792 } 7793 const char *getClobbers() const override { return ""; } 7794 ArrayRef<const char *> getGCCRegNames() const override { 7795 return None; 7796 } 7797 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7798 return None; 7799 } 7800 bool validateAsmConstraint(const char *&Name, 7801 TargetInfo::ConstraintInfo &Info) const override { 7802 return false; 7803 } 7804 7805 bool hasProtectedVisibility() const override { return false; } 7806 }; 7807 7808 class WebAssemblyTargetInfo : public TargetInfo { 7809 static const Builtin::Info BuiltinInfo[]; 7810 7811 enum SIMDEnum { 7812 NoSIMD, 7813 SIMD128, 7814 } SIMDLevel; 7815 7816 public: 7817 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7818 : TargetInfo(T), SIMDLevel(NoSIMD) { 7819 NoAsmVariants = true; 7820 SuitableAlign = 128; 7821 LargeArrayMinWidth = 128; 7822 LargeArrayAlign = 128; 7823 SimdDefaultAlign = 128; 7824 SigAtomicType = SignedLong; 7825 LongDoubleWidth = LongDoubleAlign = 128; 7826 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7827 SizeType = UnsignedInt; 7828 PtrDiffType = SignedInt; 7829 IntPtrType = SignedInt; 7830 } 7831 7832 protected: 7833 void getTargetDefines(const LangOptions &Opts, 7834 MacroBuilder &Builder) const override { 7835 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7836 if (SIMDLevel >= SIMD128) 7837 Builder.defineMacro("__wasm_simd128__"); 7838 } 7839 7840 private: 7841 bool 7842 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7843 StringRef CPU, 7844 const std::vector<std::string> &FeaturesVec) const override { 7845 if (CPU == "bleeding-edge") 7846 Features["simd128"] = true; 7847 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7848 } 7849 bool hasFeature(StringRef Feature) const final { 7850 return llvm::StringSwitch<bool>(Feature) 7851 .Case("simd128", SIMDLevel >= SIMD128) 7852 .Default(false); 7853 } 7854 bool handleTargetFeatures(std::vector<std::string> &Features, 7855 DiagnosticsEngine &Diags) final { 7856 for (const auto &Feature : Features) { 7857 if (Feature == "+simd128") { 7858 SIMDLevel = std::max(SIMDLevel, SIMD128); 7859 continue; 7860 } 7861 if (Feature == "-simd128") { 7862 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7863 continue; 7864 } 7865 7866 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7867 << "-target-feature"; 7868 return false; 7869 } 7870 return true; 7871 } 7872 bool setCPU(const std::string &Name) final { 7873 return llvm::StringSwitch<bool>(Name) 7874 .Case("mvp", true) 7875 .Case("bleeding-edge", true) 7876 .Case("generic", true) 7877 .Default(false); 7878 } 7879 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7880 return llvm::makeArrayRef(BuiltinInfo, 7881 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7882 } 7883 BuiltinVaListKind getBuiltinVaListKind() const final { 7884 return VoidPtrBuiltinVaList; 7885 } 7886 ArrayRef<const char *> getGCCRegNames() const final { 7887 return None; 7888 } 7889 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7890 return None; 7891 } 7892 bool 7893 validateAsmConstraint(const char *&Name, 7894 TargetInfo::ConstraintInfo &Info) const final { 7895 return false; 7896 } 7897 const char *getClobbers() const final { return ""; } 7898 bool isCLZForZeroUndef() const final { return false; } 7899 bool hasInt128Type() const final { return true; } 7900 IntType getIntTypeByWidth(unsigned BitWidth, 7901 bool IsSigned) const final { 7902 // WebAssembly prefers long long for explicitly 64-bit integers. 7903 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7904 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7905 } 7906 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7907 bool IsSigned) const final { 7908 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7909 return BitWidth == 64 7910 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7911 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7912 } 7913 }; 7914 7915 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7916 #define BUILTIN(ID, TYPE, ATTRS) \ 7917 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7918 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7919 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7920 #include "clang/Basic/BuiltinsWebAssembly.def" 7921 }; 7922 7923 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7924 public: 7925 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7926 const TargetOptions &Opts) 7927 : WebAssemblyTargetInfo(T, Opts) { 7928 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7929 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7930 } 7931 7932 protected: 7933 void getTargetDefines(const LangOptions &Opts, 7934 MacroBuilder &Builder) const override { 7935 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7936 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7937 } 7938 }; 7939 7940 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7941 public: 7942 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7943 const TargetOptions &Opts) 7944 : WebAssemblyTargetInfo(T, Opts) { 7945 LongAlign = LongWidth = 64; 7946 PointerAlign = PointerWidth = 64; 7947 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7948 SizeType = UnsignedLong; 7949 PtrDiffType = SignedLong; 7950 IntPtrType = SignedLong; 7951 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7952 } 7953 7954 protected: 7955 void getTargetDefines(const LangOptions &Opts, 7956 MacroBuilder &Builder) const override { 7957 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7958 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7959 } 7960 }; 7961 7962 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7963 #define BUILTIN(ID, TYPE, ATTRS) \ 7964 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7965 #include "clang/Basic/BuiltinsLe64.def" 7966 }; 7967 7968 static const unsigned SPIRAddrSpaceMap[] = { 7969 1, // opencl_global 7970 3, // opencl_local 7971 2, // opencl_constant 7972 4, // opencl_generic 7973 0, // cuda_device 7974 0, // cuda_constant 7975 0 // cuda_shared 7976 }; 7977 class SPIRTargetInfo : public TargetInfo { 7978 public: 7979 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7980 : TargetInfo(Triple) { 7981 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7982 "SPIR target must use unknown OS"); 7983 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7984 "SPIR target must use unknown environment type"); 7985 TLSSupported = false; 7986 LongWidth = LongAlign = 64; 7987 AddrSpaceMap = &SPIRAddrSpaceMap; 7988 UseAddrSpaceMapMangling = true; 7989 // Define available target features 7990 // These must be defined in sorted order! 7991 NoAsmVariants = true; 7992 } 7993 void getTargetDefines(const LangOptions &Opts, 7994 MacroBuilder &Builder) const override { 7995 DefineStd(Builder, "SPIR", Opts); 7996 } 7997 bool hasFeature(StringRef Feature) const override { 7998 return Feature == "spir"; 7999 } 8000 8001 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8002 const char *getClobbers() const override { return ""; } 8003 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8004 bool validateAsmConstraint(const char *&Name, 8005 TargetInfo::ConstraintInfo &info) const override { 8006 return true; 8007 } 8008 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8009 return None; 8010 } 8011 BuiltinVaListKind getBuiltinVaListKind() const override { 8012 return TargetInfo::VoidPtrBuiltinVaList; 8013 } 8014 8015 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8016 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8017 : CCCR_Warning; 8018 } 8019 8020 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8021 return CC_SpirFunction; 8022 } 8023 8024 void setSupportedOpenCLOpts() override { 8025 // Assume all OpenCL extensions and optional core features are supported 8026 // for SPIR since it is a generic target. 8027 getSupportedOpenCLOpts().setAll(); 8028 } 8029 }; 8030 8031 class SPIR32TargetInfo : public SPIRTargetInfo { 8032 public: 8033 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8034 : SPIRTargetInfo(Triple, Opts) { 8035 PointerWidth = PointerAlign = 32; 8036 SizeType = TargetInfo::UnsignedInt; 8037 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8038 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8039 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8040 } 8041 void getTargetDefines(const LangOptions &Opts, 8042 MacroBuilder &Builder) const override { 8043 DefineStd(Builder, "SPIR32", Opts); 8044 } 8045 }; 8046 8047 class SPIR64TargetInfo : public SPIRTargetInfo { 8048 public: 8049 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8050 : SPIRTargetInfo(Triple, Opts) { 8051 PointerWidth = PointerAlign = 64; 8052 SizeType = TargetInfo::UnsignedLong; 8053 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8054 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8055 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8056 } 8057 void getTargetDefines(const LangOptions &Opts, 8058 MacroBuilder &Builder) const override { 8059 DefineStd(Builder, "SPIR64", Opts); 8060 } 8061 }; 8062 8063 class XCoreTargetInfo : public TargetInfo { 8064 static const Builtin::Info BuiltinInfo[]; 8065 public: 8066 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8067 : TargetInfo(Triple) { 8068 NoAsmVariants = true; 8069 LongLongAlign = 32; 8070 SuitableAlign = 32; 8071 DoubleAlign = LongDoubleAlign = 32; 8072 SizeType = UnsignedInt; 8073 PtrDiffType = SignedInt; 8074 IntPtrType = SignedInt; 8075 WCharType = UnsignedChar; 8076 WIntType = UnsignedInt; 8077 UseZeroLengthBitfieldAlignment = true; 8078 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8079 "-f64:32-a:0:32-n32"); 8080 } 8081 void getTargetDefines(const LangOptions &Opts, 8082 MacroBuilder &Builder) const override { 8083 Builder.defineMacro("__XS1B__"); 8084 } 8085 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8086 return llvm::makeArrayRef(BuiltinInfo, 8087 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8088 } 8089 BuiltinVaListKind getBuiltinVaListKind() const override { 8090 return TargetInfo::VoidPtrBuiltinVaList; 8091 } 8092 const char *getClobbers() const override { 8093 return ""; 8094 } 8095 ArrayRef<const char *> getGCCRegNames() const override { 8096 static const char * const GCCRegNames[] = { 8097 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8098 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8099 }; 8100 return llvm::makeArrayRef(GCCRegNames); 8101 } 8102 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8103 return None; 8104 } 8105 bool validateAsmConstraint(const char *&Name, 8106 TargetInfo::ConstraintInfo &Info) const override { 8107 return false; 8108 } 8109 int getEHDataRegisterNumber(unsigned RegNo) const override { 8110 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8111 return (RegNo < 2)? RegNo : -1; 8112 } 8113 bool allowsLargerPreferedTypeAlignment() const override { 8114 return false; 8115 } 8116 }; 8117 8118 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8119 #define BUILTIN(ID, TYPE, ATTRS) \ 8120 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8121 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8122 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8123 #include "clang/Basic/BuiltinsXCore.def" 8124 }; 8125 8126 // x86_32 Android target 8127 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8128 public: 8129 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8130 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8131 SuitableAlign = 32; 8132 LongDoubleWidth = 64; 8133 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8134 } 8135 }; 8136 8137 // x86_64 Android target 8138 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8139 public: 8140 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8141 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8142 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8143 } 8144 8145 bool useFloat128ManglingForLongDouble() const override { 8146 return true; 8147 } 8148 }; 8149 8150 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8151 class RenderScript32TargetInfo : public ARMleTargetInfo { 8152 public: 8153 RenderScript32TargetInfo(const llvm::Triple &Triple, 8154 const TargetOptions &Opts) 8155 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8156 Triple.getOSName(), 8157 Triple.getEnvironmentName()), 8158 Opts) { 8159 IsRenderScriptTarget = true; 8160 LongWidth = LongAlign = 64; 8161 } 8162 void getTargetDefines(const LangOptions &Opts, 8163 MacroBuilder &Builder) const override { 8164 Builder.defineMacro("__RENDERSCRIPT__"); 8165 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8166 } 8167 }; 8168 8169 // 64-bit RenderScript is aarch64 8170 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8171 public: 8172 RenderScript64TargetInfo(const llvm::Triple &Triple, 8173 const TargetOptions &Opts) 8174 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8175 Triple.getOSName(), 8176 Triple.getEnvironmentName()), 8177 Opts) { 8178 IsRenderScriptTarget = true; 8179 } 8180 8181 void getTargetDefines(const LangOptions &Opts, 8182 MacroBuilder &Builder) const override { 8183 Builder.defineMacro("__RENDERSCRIPT__"); 8184 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8185 } 8186 }; 8187 8188 } // end anonymous namespace 8189 8190 //===----------------------------------------------------------------------===// 8191 // Driver code 8192 //===----------------------------------------------------------------------===// 8193 8194 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8195 const TargetOptions &Opts) { 8196 llvm::Triple::OSType os = Triple.getOS(); 8197 8198 switch (Triple.getArch()) { 8199 default: 8200 return nullptr; 8201 8202 case llvm::Triple::xcore: 8203 return new XCoreTargetInfo(Triple, Opts); 8204 8205 case llvm::Triple::hexagon: 8206 return new HexagonTargetInfo(Triple, Opts); 8207 8208 case llvm::Triple::lanai: 8209 return new LanaiTargetInfo(Triple, Opts); 8210 8211 case llvm::Triple::aarch64: 8212 if (Triple.isOSDarwin()) 8213 return new DarwinAArch64TargetInfo(Triple, Opts); 8214 8215 switch (os) { 8216 case llvm::Triple::CloudABI: 8217 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8218 case llvm::Triple::FreeBSD: 8219 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8220 case llvm::Triple::Linux: 8221 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8222 case llvm::Triple::NetBSD: 8223 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8224 default: 8225 return new AArch64leTargetInfo(Triple, Opts); 8226 } 8227 8228 case llvm::Triple::aarch64_be: 8229 switch (os) { 8230 case llvm::Triple::FreeBSD: 8231 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8232 case llvm::Triple::Linux: 8233 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8234 case llvm::Triple::NetBSD: 8235 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8236 default: 8237 return new AArch64beTargetInfo(Triple, Opts); 8238 } 8239 8240 case llvm::Triple::arm: 8241 case llvm::Triple::thumb: 8242 if (Triple.isOSBinFormatMachO()) 8243 return new DarwinARMTargetInfo(Triple, Opts); 8244 8245 switch (os) { 8246 case llvm::Triple::CloudABI: 8247 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8248 case llvm::Triple::Linux: 8249 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8250 case llvm::Triple::FreeBSD: 8251 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8252 case llvm::Triple::NetBSD: 8253 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8254 case llvm::Triple::OpenBSD: 8255 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8256 case llvm::Triple::Bitrig: 8257 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8258 case llvm::Triple::RTEMS: 8259 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8260 case llvm::Triple::NaCl: 8261 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8262 case llvm::Triple::Win32: 8263 switch (Triple.getEnvironment()) { 8264 case llvm::Triple::Cygnus: 8265 return new CygwinARMTargetInfo(Triple, Opts); 8266 case llvm::Triple::GNU: 8267 return new MinGWARMTargetInfo(Triple, Opts); 8268 case llvm::Triple::Itanium: 8269 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8270 case llvm::Triple::MSVC: 8271 default: // Assume MSVC for unknown environments 8272 return new MicrosoftARMleTargetInfo(Triple, Opts); 8273 } 8274 default: 8275 return new ARMleTargetInfo(Triple, Opts); 8276 } 8277 8278 case llvm::Triple::armeb: 8279 case llvm::Triple::thumbeb: 8280 if (Triple.isOSDarwin()) 8281 return new DarwinARMTargetInfo(Triple, Opts); 8282 8283 switch (os) { 8284 case llvm::Triple::Linux: 8285 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8286 case llvm::Triple::FreeBSD: 8287 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8288 case llvm::Triple::NetBSD: 8289 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8290 case llvm::Triple::OpenBSD: 8291 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8292 case llvm::Triple::Bitrig: 8293 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8294 case llvm::Triple::RTEMS: 8295 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8296 case llvm::Triple::NaCl: 8297 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8298 default: 8299 return new ARMbeTargetInfo(Triple, Opts); 8300 } 8301 8302 case llvm::Triple::bpfeb: 8303 case llvm::Triple::bpfel: 8304 return new BPFTargetInfo(Triple, Opts); 8305 8306 case llvm::Triple::msp430: 8307 return new MSP430TargetInfo(Triple, Opts); 8308 8309 case llvm::Triple::mips: 8310 switch (os) { 8311 case llvm::Triple::Linux: 8312 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8313 case llvm::Triple::RTEMS: 8314 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8315 case llvm::Triple::FreeBSD: 8316 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8317 case llvm::Triple::NetBSD: 8318 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8319 default: 8320 return new MipsTargetInfo(Triple, Opts); 8321 } 8322 8323 case llvm::Triple::mipsel: 8324 switch (os) { 8325 case llvm::Triple::Linux: 8326 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8327 case llvm::Triple::RTEMS: 8328 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8329 case llvm::Triple::FreeBSD: 8330 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8331 case llvm::Triple::NetBSD: 8332 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8333 case llvm::Triple::NaCl: 8334 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8335 default: 8336 return new MipsTargetInfo(Triple, Opts); 8337 } 8338 8339 case llvm::Triple::mips64: 8340 switch (os) { 8341 case llvm::Triple::Linux: 8342 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8343 case llvm::Triple::RTEMS: 8344 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8345 case llvm::Triple::FreeBSD: 8346 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8347 case llvm::Triple::NetBSD: 8348 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8349 case llvm::Triple::OpenBSD: 8350 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8351 default: 8352 return new MipsTargetInfo(Triple, Opts); 8353 } 8354 8355 case llvm::Triple::mips64el: 8356 switch (os) { 8357 case llvm::Triple::Linux: 8358 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8359 case llvm::Triple::RTEMS: 8360 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8361 case llvm::Triple::FreeBSD: 8362 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8363 case llvm::Triple::NetBSD: 8364 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8365 case llvm::Triple::OpenBSD: 8366 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8367 default: 8368 return new MipsTargetInfo(Triple, Opts); 8369 } 8370 8371 case llvm::Triple::le32: 8372 switch (os) { 8373 case llvm::Triple::NaCl: 8374 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8375 default: 8376 return nullptr; 8377 } 8378 8379 case llvm::Triple::le64: 8380 return new Le64TargetInfo(Triple, Opts); 8381 8382 case llvm::Triple::ppc: 8383 if (Triple.isOSDarwin()) 8384 return new DarwinPPC32TargetInfo(Triple, Opts); 8385 switch (os) { 8386 case llvm::Triple::Linux: 8387 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8388 case llvm::Triple::FreeBSD: 8389 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8390 case llvm::Triple::NetBSD: 8391 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8392 case llvm::Triple::OpenBSD: 8393 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8394 case llvm::Triple::RTEMS: 8395 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8396 default: 8397 return new PPC32TargetInfo(Triple, Opts); 8398 } 8399 8400 case llvm::Triple::ppc64: 8401 if (Triple.isOSDarwin()) 8402 return new DarwinPPC64TargetInfo(Triple, Opts); 8403 switch (os) { 8404 case llvm::Triple::Linux: 8405 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8406 case llvm::Triple::Lv2: 8407 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8408 case llvm::Triple::FreeBSD: 8409 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8410 case llvm::Triple::NetBSD: 8411 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8412 default: 8413 return new PPC64TargetInfo(Triple, Opts); 8414 } 8415 8416 case llvm::Triple::ppc64le: 8417 switch (os) { 8418 case llvm::Triple::Linux: 8419 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8420 case llvm::Triple::NetBSD: 8421 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8422 default: 8423 return new PPC64TargetInfo(Triple, Opts); 8424 } 8425 8426 case llvm::Triple::nvptx: 8427 return new NVPTX32TargetInfo(Triple, Opts); 8428 case llvm::Triple::nvptx64: 8429 return new NVPTX64TargetInfo(Triple, Opts); 8430 8431 case llvm::Triple::amdgcn: 8432 case llvm::Triple::r600: 8433 return new AMDGPUTargetInfo(Triple, Opts); 8434 8435 case llvm::Triple::sparc: 8436 switch (os) { 8437 case llvm::Triple::Linux: 8438 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8439 case llvm::Triple::Solaris: 8440 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8441 case llvm::Triple::NetBSD: 8442 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8443 case llvm::Triple::OpenBSD: 8444 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8445 case llvm::Triple::RTEMS: 8446 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8447 default: 8448 return new SparcV8TargetInfo(Triple, Opts); 8449 } 8450 8451 // The 'sparcel' architecture copies all the above cases except for Solaris. 8452 case llvm::Triple::sparcel: 8453 switch (os) { 8454 case llvm::Triple::Linux: 8455 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8456 case llvm::Triple::NetBSD: 8457 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8458 case llvm::Triple::OpenBSD: 8459 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8460 case llvm::Triple::RTEMS: 8461 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8462 default: 8463 return new SparcV8elTargetInfo(Triple, Opts); 8464 } 8465 8466 case llvm::Triple::sparcv9: 8467 switch (os) { 8468 case llvm::Triple::Linux: 8469 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8470 case llvm::Triple::Solaris: 8471 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8472 case llvm::Triple::NetBSD: 8473 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8474 case llvm::Triple::OpenBSD: 8475 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8476 case llvm::Triple::FreeBSD: 8477 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8478 default: 8479 return new SparcV9TargetInfo(Triple, Opts); 8480 } 8481 8482 case llvm::Triple::systemz: 8483 switch (os) { 8484 case llvm::Triple::Linux: 8485 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8486 default: 8487 return new SystemZTargetInfo(Triple, Opts); 8488 } 8489 8490 case llvm::Triple::tce: 8491 return new TCETargetInfo(Triple, Opts); 8492 8493 case llvm::Triple::x86: 8494 if (Triple.isOSDarwin()) 8495 return new DarwinI386TargetInfo(Triple, Opts); 8496 8497 switch (os) { 8498 case llvm::Triple::CloudABI: 8499 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8500 case llvm::Triple::Linux: { 8501 switch (Triple.getEnvironment()) { 8502 default: 8503 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8504 case llvm::Triple::Android: 8505 return new AndroidX86_32TargetInfo(Triple, Opts); 8506 } 8507 } 8508 case llvm::Triple::DragonFly: 8509 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8510 case llvm::Triple::NetBSD: 8511 return new NetBSDI386TargetInfo(Triple, Opts); 8512 case llvm::Triple::OpenBSD: 8513 return new OpenBSDI386TargetInfo(Triple, Opts); 8514 case llvm::Triple::Bitrig: 8515 return new BitrigI386TargetInfo(Triple, Opts); 8516 case llvm::Triple::FreeBSD: 8517 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8518 case llvm::Triple::KFreeBSD: 8519 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8520 case llvm::Triple::Minix: 8521 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8522 case llvm::Triple::Solaris: 8523 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8524 case llvm::Triple::Win32: { 8525 switch (Triple.getEnvironment()) { 8526 case llvm::Triple::Cygnus: 8527 return new CygwinX86_32TargetInfo(Triple, Opts); 8528 case llvm::Triple::GNU: 8529 return new MinGWX86_32TargetInfo(Triple, Opts); 8530 case llvm::Triple::Itanium: 8531 case llvm::Triple::MSVC: 8532 default: // Assume MSVC for unknown environments 8533 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8534 } 8535 } 8536 case llvm::Triple::Haiku: 8537 return new HaikuX86_32TargetInfo(Triple, Opts); 8538 case llvm::Triple::RTEMS: 8539 return new RTEMSX86_32TargetInfo(Triple, Opts); 8540 case llvm::Triple::NaCl: 8541 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8542 case llvm::Triple::ELFIAMCU: 8543 return new MCUX86_32TargetInfo(Triple, Opts); 8544 default: 8545 return new X86_32TargetInfo(Triple, Opts); 8546 } 8547 8548 case llvm::Triple::x86_64: 8549 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8550 return new DarwinX86_64TargetInfo(Triple, Opts); 8551 8552 switch (os) { 8553 case llvm::Triple::CloudABI: 8554 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8555 case llvm::Triple::Linux: { 8556 switch (Triple.getEnvironment()) { 8557 default: 8558 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8559 case llvm::Triple::Android: 8560 return new AndroidX86_64TargetInfo(Triple, Opts); 8561 } 8562 } 8563 case llvm::Triple::DragonFly: 8564 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8565 case llvm::Triple::NetBSD: 8566 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8567 case llvm::Triple::OpenBSD: 8568 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8569 case llvm::Triple::Bitrig: 8570 return new BitrigX86_64TargetInfo(Triple, Opts); 8571 case llvm::Triple::FreeBSD: 8572 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8573 case llvm::Triple::KFreeBSD: 8574 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8575 case llvm::Triple::Solaris: 8576 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8577 case llvm::Triple::Win32: { 8578 switch (Triple.getEnvironment()) { 8579 case llvm::Triple::Cygnus: 8580 return new CygwinX86_64TargetInfo(Triple, Opts); 8581 case llvm::Triple::GNU: 8582 return new MinGWX86_64TargetInfo(Triple, Opts); 8583 case llvm::Triple::MSVC: 8584 default: // Assume MSVC for unknown environments 8585 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8586 } 8587 } 8588 case llvm::Triple::Haiku: 8589 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8590 case llvm::Triple::NaCl: 8591 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8592 case llvm::Triple::PS4: 8593 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8594 default: 8595 return new X86_64TargetInfo(Triple, Opts); 8596 } 8597 8598 case llvm::Triple::spir: { 8599 if (Triple.getOS() != llvm::Triple::UnknownOS || 8600 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8601 return nullptr; 8602 return new SPIR32TargetInfo(Triple, Opts); 8603 } 8604 case llvm::Triple::spir64: { 8605 if (Triple.getOS() != llvm::Triple::UnknownOS || 8606 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8607 return nullptr; 8608 return new SPIR64TargetInfo(Triple, Opts); 8609 } 8610 case llvm::Triple::wasm32: 8611 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8612 return nullptr; 8613 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8614 case llvm::Triple::wasm64: 8615 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8616 return nullptr; 8617 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8618 8619 case llvm::Triple::renderscript32: 8620 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8621 case llvm::Triple::renderscript64: 8622 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8623 } 8624 } 8625 8626 /// CreateTargetInfo - Return the target info object for the specified target 8627 /// options. 8628 TargetInfo * 8629 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8630 const std::shared_ptr<TargetOptions> &Opts) { 8631 llvm::Triple Triple(Opts->Triple); 8632 8633 // Construct the target 8634 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8635 if (!Target) { 8636 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8637 return nullptr; 8638 } 8639 Target->TargetOpts = Opts; 8640 8641 // Set the target CPU if specified. 8642 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8643 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8644 return nullptr; 8645 } 8646 8647 // Set the target ABI if specified. 8648 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8649 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8650 return nullptr; 8651 } 8652 8653 // Set the fp math unit. 8654 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8655 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8656 return nullptr; 8657 } 8658 8659 // Compute the default target features, we need the target to handle this 8660 // because features may have dependencies on one another. 8661 llvm::StringMap<bool> Features; 8662 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8663 Opts->FeaturesAsWritten)) 8664 return nullptr; 8665 8666 // Add the features to the compile options. 8667 Opts->Features.clear(); 8668 for (const auto &F : Features) 8669 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8670 8671 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8672 return nullptr; 8673 8674 Target->setSupportedOpenCLOpts(); 8675 8676 if (!Target->validateTarget(Diags)) 8677 return nullptr; 8678 8679 return Target.release(); 8680 } 8681