1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 const char *getStaticInitSectionSpecifier() const override { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const override { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const override { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const override { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 486 } 487 }; 488 489 // AuroraUX target 490 template<typename Target> 491 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 DefineStd(Builder, "sun", Opts); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 Builder.defineMacro("__svr4__"); 499 Builder.defineMacro("__SVR4"); 500 } 501 public: 502 AuroraUXTargetInfo(const llvm::Triple &Triple) 503 : OSTargetInfo<Target>(Triple) { 504 this->UserLabelPrefix = ""; 505 this->WCharType = this->SignedLong; 506 // FIXME: WIntType should be SignedLong 507 } 508 }; 509 510 // Solaris target 511 template<typename Target> 512 class SolarisTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const override { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 522 // newer, but to 500 for everything else. feature_test.h has a check to 523 // ensure that you are not using C99 with an old version of X/Open or C89 524 // with a new version. 525 if (Opts.C99 || Opts.C11) 526 Builder.defineMacro("_XOPEN_SOURCE", "600"); 527 else 528 Builder.defineMacro("_XOPEN_SOURCE", "500"); 529 if (Opts.CPlusPlus) 530 Builder.defineMacro("__C99FEATURES__"); 531 Builder.defineMacro("_LARGEFILE_SOURCE"); 532 Builder.defineMacro("_LARGEFILE64_SOURCE"); 533 Builder.defineMacro("__EXTENSIONS__"); 534 Builder.defineMacro("_REENTRANT"); 535 } 536 public: 537 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 538 this->UserLabelPrefix = ""; 539 this->WCharType = this->SignedInt; 540 // FIXME: WIntType should be SignedLong 541 } 542 }; 543 544 // Windows target 545 template<typename Target> 546 class WindowsTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 Builder.defineMacro("_WIN32"); 551 } 552 void getVisualStudioDefines(const LangOptions &Opts, 553 MacroBuilder &Builder) const { 554 if (Opts.CPlusPlus) { 555 if (Opts.RTTI) 556 Builder.defineMacro("_CPPRTTI"); 557 558 if (Opts.Exceptions) 559 Builder.defineMacro("_CPPUNWIND"); 560 } 561 562 if (!Opts.CharIsSigned) 563 Builder.defineMacro("_CHAR_UNSIGNED"); 564 565 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 566 // but it works for now. 567 if (Opts.POSIXThreads) 568 Builder.defineMacro("_MT"); 569 570 if (Opts.MSCVersion != 0) 571 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 572 573 if (Opts.MicrosoftExt) { 574 Builder.defineMacro("_MSC_EXTENSIONS"); 575 576 if (Opts.CPlusPlus11) { 577 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 578 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 579 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 580 } 581 } 582 583 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 584 } 585 586 public: 587 WindowsTargetInfo(const llvm::Triple &Triple) 588 : OSTargetInfo<Target>(Triple) {} 589 }; 590 591 template <typename Target> 592 class NaClTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const override { 596 if (Opts.POSIXThreads) 597 Builder.defineMacro("_REENTRANT"); 598 if (Opts.CPlusPlus) 599 Builder.defineMacro("_GNU_SOURCE"); 600 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__native_client__"); 604 } 605 606 public: 607 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 608 this->UserLabelPrefix = ""; 609 this->LongAlign = 32; 610 this->LongWidth = 32; 611 this->PointerAlign = 32; 612 this->PointerWidth = 32; 613 this->IntMaxType = TargetInfo::SignedLongLong; 614 this->UIntMaxType = TargetInfo::UnsignedLongLong; 615 this->Int64Type = TargetInfo::SignedLongLong; 616 this->DoubleAlign = 64; 617 this->LongDoubleWidth = 64; 618 this->LongDoubleAlign = 64; 619 this->LongLongWidth = 64; 620 this->LongLongAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 if (Triple.getArch() == llvm::Triple::arm) { 627 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 628 } else if (Triple.getArch() == llvm::Triple::x86) { 629 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 630 } else if (Triple.getArch() == llvm::Triple::x86_64) { 631 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 632 } else if (Triple.getArch() == llvm::Triple::mipsel) { 633 // Handled on mips' setDescriptionString. 634 } else { 635 assert(Triple.getArch() == llvm::Triple::le32); 636 this->DescriptionString = "e-p:32:32-i64:64"; 637 } 638 } 639 typename Target::CallingConvCheckResult checkCallingConvention( 640 CallingConv CC) const override { 641 return CC == CC_PnaclCall ? Target::CCCR_OK : 642 Target::checkCallingConvention(CC); 643 } 644 }; 645 } // end anonymous namespace. 646 647 //===----------------------------------------------------------------------===// 648 // Specific target implementations. 649 //===----------------------------------------------------------------------===// 650 651 namespace { 652 // PPC abstract base class 653 class PPCTargetInfo : public TargetInfo { 654 static const Builtin::Info BuiltinInfo[]; 655 static const char * const GCCRegNames[]; 656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 657 std::string CPU; 658 659 // Target cpu features. 660 bool HasVSX; 661 662 public: 663 PPCTargetInfo(const llvm::Triple &Triple) 664 : TargetInfo(Triple), HasVSX(false) { 665 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 666 LongDoubleWidth = LongDoubleAlign = 128; 667 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 668 } 669 670 /// \brief Flags for architecture specific defines. 671 typedef enum { 672 ArchDefineNone = 0, 673 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 674 ArchDefinePpcgr = 1 << 1, 675 ArchDefinePpcsq = 1 << 2, 676 ArchDefine440 = 1 << 3, 677 ArchDefine603 = 1 << 4, 678 ArchDefine604 = 1 << 5, 679 ArchDefinePwr4 = 1 << 6, 680 ArchDefinePwr5 = 1 << 7, 681 ArchDefinePwr5x = 1 << 8, 682 ArchDefinePwr6 = 1 << 9, 683 ArchDefinePwr6x = 1 << 10, 684 ArchDefinePwr7 = 1 << 11, 685 ArchDefineA2 = 1 << 12, 686 ArchDefineA2q = 1 << 13 687 } ArchDefineTypes; 688 689 // Note: GCC recognizes the following additional cpus: 690 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 691 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 692 // titan, rs64. 693 bool setCPU(const std::string &Name) override { 694 bool CPUKnown = llvm::StringSwitch<bool>(Name) 695 .Case("generic", true) 696 .Case("440", true) 697 .Case("450", true) 698 .Case("601", true) 699 .Case("602", true) 700 .Case("603", true) 701 .Case("603e", true) 702 .Case("603ev", true) 703 .Case("604", true) 704 .Case("604e", true) 705 .Case("620", true) 706 .Case("630", true) 707 .Case("g3", true) 708 .Case("7400", true) 709 .Case("g4", true) 710 .Case("7450", true) 711 .Case("g4+", true) 712 .Case("750", true) 713 .Case("970", true) 714 .Case("g5", true) 715 .Case("a2", true) 716 .Case("a2q", true) 717 .Case("e500mc", true) 718 .Case("e5500", true) 719 .Case("power3", true) 720 .Case("pwr3", true) 721 .Case("power4", true) 722 .Case("pwr4", true) 723 .Case("power5", true) 724 .Case("pwr5", true) 725 .Case("power5x", true) 726 .Case("pwr5x", true) 727 .Case("power6", true) 728 .Case("pwr6", true) 729 .Case("power6x", true) 730 .Case("pwr6x", true) 731 .Case("power7", true) 732 .Case("pwr7", true) 733 .Case("powerpc", true) 734 .Case("ppc", true) 735 .Case("powerpc64", true) 736 .Case("ppc64", true) 737 .Case("powerpc64le", true) 738 .Case("ppc64le", true) 739 .Default(false); 740 741 if (CPUKnown) 742 CPU = Name; 743 744 return CPUKnown; 745 } 746 747 void getTargetBuiltins(const Builtin::Info *&Records, 748 unsigned &NumRecords) const override { 749 Records = BuiltinInfo; 750 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 751 } 752 753 bool isCLZForZeroUndef() const override { return false; } 754 755 void getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const override; 757 758 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 759 760 bool handleTargetFeatures(std::vector<std::string> &Features, 761 DiagnosticsEngine &Diags) override; 762 bool hasFeature(StringRef Feature) const override; 763 764 void getGCCRegNames(const char * const *&Names, 765 unsigned &NumNames) const override; 766 void getGCCRegAliases(const GCCRegAlias *&Aliases, 767 unsigned &NumAliases) const override; 768 bool validateAsmConstraint(const char *&Name, 769 TargetInfo::ConstraintInfo &Info) const override { 770 switch (*Name) { 771 default: return false; 772 case 'O': // Zero 773 break; 774 case 'b': // Base register 775 case 'f': // Floating point register 776 Info.setAllowsRegister(); 777 break; 778 // FIXME: The following are added to allow parsing. 779 // I just took a guess at what the actions should be. 780 // Also, is more specific checking needed? I.e. specific registers? 781 case 'd': // Floating point register (containing 64-bit value) 782 case 'v': // Altivec vector register 783 Info.setAllowsRegister(); 784 break; 785 case 'w': 786 switch (Name[1]) { 787 case 'd':// VSX vector register to hold vector double data 788 case 'f':// VSX vector register to hold vector float data 789 case 's':// VSX vector register to hold scalar float data 790 case 'a':// Any VSX register 791 case 'c':// An individual CR bit 792 break; 793 default: 794 return false; 795 } 796 Info.setAllowsRegister(); 797 Name++; // Skip over 'w'. 798 break; 799 case 'h': // `MQ', `CTR', or `LINK' register 800 case 'q': // `MQ' register 801 case 'c': // `CTR' register 802 case 'l': // `LINK' register 803 case 'x': // `CR' register (condition register) number 0 804 case 'y': // `CR' register (condition register) 805 case 'z': // `XER[CA]' carry bit (part of the XER register) 806 Info.setAllowsRegister(); 807 break; 808 case 'I': // Signed 16-bit constant 809 case 'J': // Unsigned 16-bit constant shifted left 16 bits 810 // (use `L' instead for SImode constants) 811 case 'K': // Unsigned 16-bit constant 812 case 'L': // Signed 16-bit constant shifted left 16 bits 813 case 'M': // Constant larger than 31 814 case 'N': // Exact power of 2 815 case 'P': // Constant whose negation is a signed 16-bit constant 816 case 'G': // Floating point constant that can be loaded into a 817 // register with one instruction per word 818 case 'H': // Integer/Floating point constant that can be loaded 819 // into a register using three instructions 820 break; 821 case 'm': // Memory operand. Note that on PowerPC targets, m can 822 // include addresses that update the base register. It 823 // is therefore only safe to use `m' in an asm statement 824 // if that asm statement accesses the operand exactly once. 825 // The asm statement must also use `%U<opno>' as a 826 // placeholder for the "update" flag in the corresponding 827 // load or store instruction. For example: 828 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 829 // is correct but: 830 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 831 // is not. Use es rather than m if you don't want the base 832 // register to be updated. 833 case 'e': 834 if (Name[1] != 's') 835 return false; 836 // es: A "stable" memory operand; that is, one which does not 837 // include any automodification of the base register. Unlike 838 // `m', this constraint can be used in asm statements that 839 // might access the operand several times, or that might not 840 // access it at all. 841 Info.setAllowsMemory(); 842 Name++; // Skip over 'e'. 843 break; 844 case 'Q': // Memory operand that is an offset from a register (it is 845 // usually better to use `m' or `es' in asm statements) 846 case 'Z': // Memory operand that is an indexed or indirect from a 847 // register (it is usually better to use `m' or `es' in 848 // asm statements) 849 Info.setAllowsMemory(); 850 Info.setAllowsRegister(); 851 break; 852 case 'R': // AIX TOC entry 853 case 'a': // Address operand that is an indexed or indirect from a 854 // register (`p' is preferable for asm statements) 855 case 'S': // Constant suitable as a 64-bit mask operand 856 case 'T': // Constant suitable as a 32-bit mask operand 857 case 'U': // System V Release 4 small data area reference 858 case 't': // AND masks that can be performed by two rldic{l, r} 859 // instructions 860 case 'W': // Vector constant that does not require memory 861 case 'j': // Vector constant that is all zeros. 862 break; 863 // End FIXME. 864 } 865 return true; 866 } 867 std::string convertConstraint(const char *&Constraint) const override { 868 std::string R; 869 switch (*Constraint) { 870 case 'e': 871 case 'w': 872 // Two-character constraint; add "^" hint for later parsing. 873 R = std::string("^") + std::string(Constraint, 2); 874 Constraint++; 875 break; 876 default: 877 return TargetInfo::convertConstraint(Constraint); 878 } 879 return R; 880 } 881 const char *getClobbers() const override { 882 return ""; 883 } 884 int getEHDataRegisterNumber(unsigned RegNo) const override { 885 if (RegNo == 0) return 3; 886 if (RegNo == 1) return 4; 887 return -1; 888 } 889 }; 890 891 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 892 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 894 ALL_LANGUAGES }, 895 #include "clang/Basic/BuiltinsPPC.def" 896 }; 897 898 /// handleTargetFeatures - Perform initialization based on the user 899 /// configured set of features. 900 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 901 DiagnosticsEngine &Diags) { 902 // Remember the maximum enabled sselevel. 903 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 904 // Ignore disabled features. 905 if (Features[i][0] == '-') 906 continue; 907 908 StringRef Feature = StringRef(Features[i]).substr(1); 909 910 if (Feature == "vsx") { 911 HasVSX = true; 912 continue; 913 } 914 915 // TODO: Finish this list and add an assert that we've handled them 916 // all. 917 } 918 919 return true; 920 } 921 922 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 923 /// #defines that are not tied to a specific subtarget. 924 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 925 MacroBuilder &Builder) const { 926 // Target identification. 927 Builder.defineMacro("__ppc__"); 928 Builder.defineMacro("__PPC__"); 929 Builder.defineMacro("_ARCH_PPC"); 930 Builder.defineMacro("__powerpc__"); 931 Builder.defineMacro("__POWERPC__"); 932 if (PointerWidth == 64) { 933 Builder.defineMacro("_ARCH_PPC64"); 934 Builder.defineMacro("__powerpc64__"); 935 Builder.defineMacro("__ppc64__"); 936 Builder.defineMacro("__PPC64__"); 937 } 938 939 // Target properties. 940 if (getTriple().getArch() == llvm::Triple::ppc64le) { 941 Builder.defineMacro("_LITTLE_ENDIAN"); 942 Builder.defineMacro("_CALL_ELF","2"); 943 } else { 944 if (getTriple().getOS() != llvm::Triple::NetBSD && 945 getTriple().getOS() != llvm::Triple::OpenBSD) 946 Builder.defineMacro("_BIG_ENDIAN"); 947 } 948 949 // Subtarget options. 950 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 951 Builder.defineMacro("__REGISTER_PREFIX__", ""); 952 953 // FIXME: Should be controlled by command line option. 954 if (LongDoubleWidth == 128) 955 Builder.defineMacro("__LONG_DOUBLE_128__"); 956 957 if (Opts.AltiVec) { 958 Builder.defineMacro("__VEC__", "10206"); 959 Builder.defineMacro("__ALTIVEC__"); 960 } 961 962 // CPU identification. 963 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 964 .Case("440", ArchDefineName) 965 .Case("450", ArchDefineName | ArchDefine440) 966 .Case("601", ArchDefineName) 967 .Case("602", ArchDefineName | ArchDefinePpcgr) 968 .Case("603", ArchDefineName | ArchDefinePpcgr) 969 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 970 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 971 .Case("604", ArchDefineName | ArchDefinePpcgr) 972 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 973 .Case("620", ArchDefineName | ArchDefinePpcgr) 974 .Case("630", ArchDefineName | ArchDefinePpcgr) 975 .Case("7400", ArchDefineName | ArchDefinePpcgr) 976 .Case("7450", ArchDefineName | ArchDefinePpcgr) 977 .Case("750", ArchDefineName | ArchDefinePpcgr) 978 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 979 | ArchDefinePpcsq) 980 .Case("a2", ArchDefineA2) 981 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 982 .Case("pwr3", ArchDefinePpcgr) 983 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 984 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 985 | ArchDefinePpcsq) 986 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 987 | ArchDefinePpcgr | ArchDefinePpcsq) 988 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 989 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 990 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 991 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 992 | ArchDefinePpcsq) 993 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 994 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 995 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 996 .Case("power3", ArchDefinePpcgr) 997 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 998 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 999 | ArchDefinePpcsq) 1000 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1001 | ArchDefinePpcgr | ArchDefinePpcsq) 1002 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1003 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1004 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1005 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1006 | ArchDefinePpcsq) 1007 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1008 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1009 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1010 .Default(ArchDefineNone); 1011 1012 if (defs & ArchDefineName) 1013 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1014 if (defs & ArchDefinePpcgr) 1015 Builder.defineMacro("_ARCH_PPCGR"); 1016 if (defs & ArchDefinePpcsq) 1017 Builder.defineMacro("_ARCH_PPCSQ"); 1018 if (defs & ArchDefine440) 1019 Builder.defineMacro("_ARCH_440"); 1020 if (defs & ArchDefine603) 1021 Builder.defineMacro("_ARCH_603"); 1022 if (defs & ArchDefine604) 1023 Builder.defineMacro("_ARCH_604"); 1024 if (defs & ArchDefinePwr4) 1025 Builder.defineMacro("_ARCH_PWR4"); 1026 if (defs & ArchDefinePwr5) 1027 Builder.defineMacro("_ARCH_PWR5"); 1028 if (defs & ArchDefinePwr5x) 1029 Builder.defineMacro("_ARCH_PWR5X"); 1030 if (defs & ArchDefinePwr6) 1031 Builder.defineMacro("_ARCH_PWR6"); 1032 if (defs & ArchDefinePwr6x) 1033 Builder.defineMacro("_ARCH_PWR6X"); 1034 if (defs & ArchDefinePwr7) 1035 Builder.defineMacro("_ARCH_PWR7"); 1036 if (defs & ArchDefineA2) 1037 Builder.defineMacro("_ARCH_A2"); 1038 if (defs & ArchDefineA2q) { 1039 Builder.defineMacro("_ARCH_A2Q"); 1040 Builder.defineMacro("_ARCH_QP"); 1041 } 1042 1043 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1044 Builder.defineMacro("__bg__"); 1045 Builder.defineMacro("__THW_BLUEGENE__"); 1046 Builder.defineMacro("__bgq__"); 1047 Builder.defineMacro("__TOS_BGQ__"); 1048 } 1049 1050 if (HasVSX) 1051 Builder.defineMacro("__VSX__"); 1052 1053 // FIXME: The following are not yet generated here by Clang, but are 1054 // generated by GCC: 1055 // 1056 // _SOFT_FLOAT_ 1057 // __RECIP_PRECISION__ 1058 // __APPLE_ALTIVEC__ 1059 // __RECIP__ 1060 // __RECIPF__ 1061 // __RSQRTE__ 1062 // __RSQRTEF__ 1063 // _SOFT_DOUBLE_ 1064 // __NO_LWSYNC__ 1065 // __HAVE_BSWAP__ 1066 // __LONGDOUBLE128 1067 // __CMODEL_MEDIUM__ 1068 // __CMODEL_LARGE__ 1069 // _CALL_SYSV 1070 // _CALL_DARWIN 1071 // __NO_FPRS__ 1072 } 1073 1074 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1075 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1076 .Case("7400", true) 1077 .Case("g4", true) 1078 .Case("7450", true) 1079 .Case("g4+", true) 1080 .Case("970", true) 1081 .Case("g5", true) 1082 .Case("pwr6", true) 1083 .Case("pwr7", true) 1084 .Case("ppc64", true) 1085 .Case("ppc64le", true) 1086 .Default(false); 1087 1088 Features["qpx"] = (CPU == "a2q"); 1089 } 1090 1091 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1092 return Feature == "powerpc"; 1093 } 1094 1095 1096 const char * const PPCTargetInfo::GCCRegNames[] = { 1097 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1098 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1099 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1100 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1101 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1102 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1103 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1104 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1105 "mq", "lr", "ctr", "ap", 1106 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1107 "xer", 1108 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1109 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1110 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1111 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1112 "vrsave", "vscr", 1113 "spe_acc", "spefscr", 1114 "sfp" 1115 }; 1116 1117 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1118 unsigned &NumNames) const { 1119 Names = GCCRegNames; 1120 NumNames = llvm::array_lengthof(GCCRegNames); 1121 } 1122 1123 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1124 // While some of these aliases do map to different registers 1125 // they still share the same register name. 1126 { { "0" }, "r0" }, 1127 { { "1"}, "r1" }, 1128 { { "2" }, "r2" }, 1129 { { "3" }, "r3" }, 1130 { { "4" }, "r4" }, 1131 { { "5" }, "r5" }, 1132 { { "6" }, "r6" }, 1133 { { "7" }, "r7" }, 1134 { { "8" }, "r8" }, 1135 { { "9" }, "r9" }, 1136 { { "10" }, "r10" }, 1137 { { "11" }, "r11" }, 1138 { { "12" }, "r12" }, 1139 { { "13" }, "r13" }, 1140 { { "14" }, "r14" }, 1141 { { "15" }, "r15" }, 1142 { { "16" }, "r16" }, 1143 { { "17" }, "r17" }, 1144 { { "18" }, "r18" }, 1145 { { "19" }, "r19" }, 1146 { { "20" }, "r20" }, 1147 { { "21" }, "r21" }, 1148 { { "22" }, "r22" }, 1149 { { "23" }, "r23" }, 1150 { { "24" }, "r24" }, 1151 { { "25" }, "r25" }, 1152 { { "26" }, "r26" }, 1153 { { "27" }, "r27" }, 1154 { { "28" }, "r28" }, 1155 { { "29" }, "r29" }, 1156 { { "30" }, "r30" }, 1157 { { "31" }, "r31" }, 1158 { { "fr0" }, "f0" }, 1159 { { "fr1" }, "f1" }, 1160 { { "fr2" }, "f2" }, 1161 { { "fr3" }, "f3" }, 1162 { { "fr4" }, "f4" }, 1163 { { "fr5" }, "f5" }, 1164 { { "fr6" }, "f6" }, 1165 { { "fr7" }, "f7" }, 1166 { { "fr8" }, "f8" }, 1167 { { "fr9" }, "f9" }, 1168 { { "fr10" }, "f10" }, 1169 { { "fr11" }, "f11" }, 1170 { { "fr12" }, "f12" }, 1171 { { "fr13" }, "f13" }, 1172 { { "fr14" }, "f14" }, 1173 { { "fr15" }, "f15" }, 1174 { { "fr16" }, "f16" }, 1175 { { "fr17" }, "f17" }, 1176 { { "fr18" }, "f18" }, 1177 { { "fr19" }, "f19" }, 1178 { { "fr20" }, "f20" }, 1179 { { "fr21" }, "f21" }, 1180 { { "fr22" }, "f22" }, 1181 { { "fr23" }, "f23" }, 1182 { { "fr24" }, "f24" }, 1183 { { "fr25" }, "f25" }, 1184 { { "fr26" }, "f26" }, 1185 { { "fr27" }, "f27" }, 1186 { { "fr28" }, "f28" }, 1187 { { "fr29" }, "f29" }, 1188 { { "fr30" }, "f30" }, 1189 { { "fr31" }, "f31" }, 1190 { { "cc" }, "cr0" }, 1191 }; 1192 1193 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1194 unsigned &NumAliases) const { 1195 Aliases = GCCRegAliases; 1196 NumAliases = llvm::array_lengthof(GCCRegAliases); 1197 } 1198 } // end anonymous namespace. 1199 1200 namespace { 1201 class PPC32TargetInfo : public PPCTargetInfo { 1202 public: 1203 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1204 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1205 1206 switch (getTriple().getOS()) { 1207 case llvm::Triple::Linux: 1208 case llvm::Triple::FreeBSD: 1209 case llvm::Triple::NetBSD: 1210 SizeType = UnsignedInt; 1211 PtrDiffType = SignedInt; 1212 IntPtrType = SignedInt; 1213 break; 1214 default: 1215 break; 1216 } 1217 1218 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1219 LongDoubleWidth = LongDoubleAlign = 64; 1220 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1221 } 1222 1223 // PPC32 supports atomics up to 4 bytes. 1224 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1225 } 1226 1227 BuiltinVaListKind getBuiltinVaListKind() const override { 1228 // This is the ELF definition, and is overridden by the Darwin sub-target 1229 return TargetInfo::PowerABIBuiltinVaList; 1230 } 1231 }; 1232 } // end anonymous namespace. 1233 1234 // Note: ABI differences may eventually require us to have a separate 1235 // TargetInfo for little endian. 1236 namespace { 1237 class PPC64TargetInfo : public PPCTargetInfo { 1238 public: 1239 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1240 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1241 IntMaxType = SignedLong; 1242 UIntMaxType = UnsignedLong; 1243 Int64Type = SignedLong; 1244 1245 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1246 LongDoubleWidth = LongDoubleAlign = 64; 1247 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1248 DescriptionString = "E-m:e-i64:64-n32:64"; 1249 } else { 1250 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1251 DescriptionString = "e-m:e-i64:64-n32:64"; 1252 } else { 1253 DescriptionString = "E-m:e-i64:64-n32:64"; 1254 } 1255 } 1256 1257 // PPC64 supports atomics up to 8 bytes. 1258 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1259 } 1260 BuiltinVaListKind getBuiltinVaListKind() const override { 1261 return TargetInfo::CharPtrBuiltinVaList; 1262 } 1263 }; 1264 } // end anonymous namespace. 1265 1266 1267 namespace { 1268 class DarwinPPC32TargetInfo : 1269 public DarwinTargetInfo<PPC32TargetInfo> { 1270 public: 1271 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1272 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1273 HasAlignMac68kSupport = true; 1274 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1275 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1276 LongLongAlign = 32; 1277 SuitableAlign = 128; 1278 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1279 } 1280 BuiltinVaListKind getBuiltinVaListKind() const override { 1281 return TargetInfo::CharPtrBuiltinVaList; 1282 } 1283 }; 1284 1285 class DarwinPPC64TargetInfo : 1286 public DarwinTargetInfo<PPC64TargetInfo> { 1287 public: 1288 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1289 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1290 HasAlignMac68kSupport = true; 1291 SuitableAlign = 128; 1292 DescriptionString = "E-m:o-i64:64-n32:64"; 1293 } 1294 }; 1295 } // end anonymous namespace. 1296 1297 namespace { 1298 static const unsigned NVPTXAddrSpaceMap[] = { 1299 1, // opencl_global 1300 3, // opencl_local 1301 4, // opencl_constant 1302 1, // cuda_device 1303 4, // cuda_constant 1304 3, // cuda_shared 1305 }; 1306 class NVPTXTargetInfo : public TargetInfo { 1307 static const char * const GCCRegNames[]; 1308 static const Builtin::Info BuiltinInfo[]; 1309 public: 1310 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1311 BigEndian = false; 1312 TLSSupported = false; 1313 LongWidth = LongAlign = 64; 1314 AddrSpaceMap = &NVPTXAddrSpaceMap; 1315 UseAddrSpaceMapMangling = true; 1316 // Define available target features 1317 // These must be defined in sorted order! 1318 NoAsmVariants = true; 1319 } 1320 void getTargetDefines(const LangOptions &Opts, 1321 MacroBuilder &Builder) const override { 1322 Builder.defineMacro("__PTX__"); 1323 Builder.defineMacro("__NVPTX__"); 1324 } 1325 void getTargetBuiltins(const Builtin::Info *&Records, 1326 unsigned &NumRecords) const override { 1327 Records = BuiltinInfo; 1328 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1329 } 1330 bool hasFeature(StringRef Feature) const override { 1331 return Feature == "ptx" || Feature == "nvptx"; 1332 } 1333 1334 void getGCCRegNames(const char * const *&Names, 1335 unsigned &NumNames) const override; 1336 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1337 unsigned &NumAliases) const override { 1338 // No aliases. 1339 Aliases = 0; 1340 NumAliases = 0; 1341 } 1342 bool validateAsmConstraint(const char *&Name, 1343 TargetInfo::ConstraintInfo &Info) const override { 1344 switch (*Name) { 1345 default: return false; 1346 case 'c': 1347 case 'h': 1348 case 'r': 1349 case 'l': 1350 case 'f': 1351 case 'd': 1352 Info.setAllowsRegister(); 1353 return true; 1354 } 1355 } 1356 const char *getClobbers() const override { 1357 // FIXME: Is this really right? 1358 return ""; 1359 } 1360 BuiltinVaListKind getBuiltinVaListKind() const override { 1361 // FIXME: implement 1362 return TargetInfo::CharPtrBuiltinVaList; 1363 } 1364 bool setCPU(const std::string &Name) override { 1365 bool Valid = llvm::StringSwitch<bool>(Name) 1366 .Case("sm_20", true) 1367 .Case("sm_21", true) 1368 .Case("sm_30", true) 1369 .Case("sm_35", true) 1370 .Default(false); 1371 1372 return Valid; 1373 } 1374 }; 1375 1376 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1377 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1378 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1379 ALL_LANGUAGES }, 1380 #include "clang/Basic/BuiltinsNVPTX.def" 1381 }; 1382 1383 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1384 "r0" 1385 }; 1386 1387 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1388 unsigned &NumNames) const { 1389 Names = GCCRegNames; 1390 NumNames = llvm::array_lengthof(GCCRegNames); 1391 } 1392 1393 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1394 public: 1395 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1396 PointerWidth = PointerAlign = 32; 1397 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1398 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1399 } 1400 }; 1401 1402 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1403 public: 1404 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1405 PointerWidth = PointerAlign = 64; 1406 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1407 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1408 } 1409 }; 1410 } 1411 1412 namespace { 1413 1414 static const unsigned R600AddrSpaceMap[] = { 1415 1, // opencl_global 1416 3, // opencl_local 1417 2, // opencl_constant 1418 1, // cuda_device 1419 2, // cuda_constant 1420 3 // cuda_shared 1421 }; 1422 1423 static const char *DescriptionStringR600 = 1424 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1425 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1426 1427 static const char *DescriptionStringR600DoubleOps = 1428 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1429 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1430 1431 static const char *DescriptionStringSI = 1432 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1433 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1434 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1435 1436 class R600TargetInfo : public TargetInfo { 1437 /// \brief The GPU profiles supported by the R600 target. 1438 enum GPUKind { 1439 GK_NONE, 1440 GK_R600, 1441 GK_R600_DOUBLE_OPS, 1442 GK_R700, 1443 GK_R700_DOUBLE_OPS, 1444 GK_EVERGREEN, 1445 GK_EVERGREEN_DOUBLE_OPS, 1446 GK_NORTHERN_ISLANDS, 1447 GK_CAYMAN, 1448 GK_SOUTHERN_ISLANDS, 1449 GK_SEA_ISLANDS 1450 } GPU; 1451 1452 public: 1453 R600TargetInfo(const llvm::Triple &Triple) 1454 : TargetInfo(Triple), GPU(GK_R600) { 1455 DescriptionString = DescriptionStringR600; 1456 AddrSpaceMap = &R600AddrSpaceMap; 1457 UseAddrSpaceMapMangling = true; 1458 } 1459 1460 const char * getClobbers() const override { 1461 return ""; 1462 } 1463 1464 void getGCCRegNames(const char * const *&Names, 1465 unsigned &numNames) const override { 1466 Names = NULL; 1467 numNames = 0; 1468 } 1469 1470 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1471 unsigned &NumAliases) const override { 1472 Aliases = NULL; 1473 NumAliases = 0; 1474 } 1475 1476 bool validateAsmConstraint(const char *&Name, 1477 TargetInfo::ConstraintInfo &info) const override { 1478 return true; 1479 } 1480 1481 void getTargetBuiltins(const Builtin::Info *&Records, 1482 unsigned &NumRecords) const override { 1483 Records = NULL; 1484 NumRecords = 0; 1485 } 1486 1487 1488 void getTargetDefines(const LangOptions &Opts, 1489 MacroBuilder &Builder) const override { 1490 Builder.defineMacro("__R600__"); 1491 } 1492 1493 BuiltinVaListKind getBuiltinVaListKind() const override { 1494 return TargetInfo::CharPtrBuiltinVaList; 1495 } 1496 1497 bool setCPU(const std::string &Name) override { 1498 GPU = llvm::StringSwitch<GPUKind>(Name) 1499 .Case("r600" , GK_R600) 1500 .Case("rv610", GK_R600) 1501 .Case("rv620", GK_R600) 1502 .Case("rv630", GK_R600) 1503 .Case("rv635", GK_R600) 1504 .Case("rs780", GK_R600) 1505 .Case("rs880", GK_R600) 1506 .Case("rv670", GK_R600_DOUBLE_OPS) 1507 .Case("rv710", GK_R700) 1508 .Case("rv730", GK_R700) 1509 .Case("rv740", GK_R700_DOUBLE_OPS) 1510 .Case("rv770", GK_R700_DOUBLE_OPS) 1511 .Case("palm", GK_EVERGREEN) 1512 .Case("cedar", GK_EVERGREEN) 1513 .Case("sumo", GK_EVERGREEN) 1514 .Case("sumo2", GK_EVERGREEN) 1515 .Case("redwood", GK_EVERGREEN) 1516 .Case("juniper", GK_EVERGREEN) 1517 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1518 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1519 .Case("barts", GK_NORTHERN_ISLANDS) 1520 .Case("turks", GK_NORTHERN_ISLANDS) 1521 .Case("caicos", GK_NORTHERN_ISLANDS) 1522 .Case("cayman", GK_CAYMAN) 1523 .Case("aruba", GK_CAYMAN) 1524 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1525 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1526 .Case("verde", GK_SOUTHERN_ISLANDS) 1527 .Case("oland", GK_SOUTHERN_ISLANDS) 1528 .Case("bonaire", GK_SEA_ISLANDS) 1529 .Case("kabini", GK_SEA_ISLANDS) 1530 .Case("kaveri", GK_SEA_ISLANDS) 1531 .Case("hawaii", GK_SEA_ISLANDS) 1532 .Default(GK_NONE); 1533 1534 if (GPU == GK_NONE) { 1535 return false; 1536 } 1537 1538 // Set the correct data layout 1539 switch (GPU) { 1540 case GK_NONE: 1541 case GK_R600: 1542 case GK_R700: 1543 case GK_EVERGREEN: 1544 case GK_NORTHERN_ISLANDS: 1545 DescriptionString = DescriptionStringR600; 1546 break; 1547 case GK_R600_DOUBLE_OPS: 1548 case GK_R700_DOUBLE_OPS: 1549 case GK_EVERGREEN_DOUBLE_OPS: 1550 case GK_CAYMAN: 1551 DescriptionString = DescriptionStringR600DoubleOps; 1552 break; 1553 case GK_SOUTHERN_ISLANDS: 1554 case GK_SEA_ISLANDS: 1555 DescriptionString = DescriptionStringSI; 1556 break; 1557 } 1558 1559 return true; 1560 } 1561 }; 1562 1563 } // end anonymous namespace 1564 1565 namespace { 1566 // Namespace for x86 abstract base class 1567 const Builtin::Info BuiltinInfo[] = { 1568 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1569 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1570 ALL_LANGUAGES }, 1571 #include "clang/Basic/BuiltinsX86.def" 1572 }; 1573 1574 static const char* const GCCRegNames[] = { 1575 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1576 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1577 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1578 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1579 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1580 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1581 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1582 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1583 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1584 }; 1585 1586 const TargetInfo::AddlRegName AddlRegNames[] = { 1587 { { "al", "ah", "eax", "rax" }, 0 }, 1588 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1589 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1590 { { "dl", "dh", "edx", "rdx" }, 1 }, 1591 { { "esi", "rsi" }, 4 }, 1592 { { "edi", "rdi" }, 5 }, 1593 { { "esp", "rsp" }, 7 }, 1594 { { "ebp", "rbp" }, 6 }, 1595 }; 1596 1597 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1598 // most of the implementation can be shared. 1599 class X86TargetInfo : public TargetInfo { 1600 enum X86SSEEnum { 1601 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1602 } SSELevel; 1603 enum MMX3DNowEnum { 1604 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1605 } MMX3DNowLevel; 1606 enum XOPEnum { 1607 NoXOP, 1608 SSE4A, 1609 FMA4, 1610 XOP 1611 } XOPLevel; 1612 1613 bool HasAES; 1614 bool HasPCLMUL; 1615 bool HasLZCNT; 1616 bool HasRDRND; 1617 bool HasBMI; 1618 bool HasBMI2; 1619 bool HasPOPCNT; 1620 bool HasRTM; 1621 bool HasPRFCHW; 1622 bool HasRDSEED; 1623 bool HasTBM; 1624 bool HasFMA; 1625 bool HasF16C; 1626 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1627 bool HasSHA; 1628 bool HasCX16; 1629 1630 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1631 /// 1632 /// Each enumeration represents a particular CPU supported by Clang. These 1633 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1634 enum CPUKind { 1635 CK_Generic, 1636 1637 /// \name i386 1638 /// i386-generation processors. 1639 //@{ 1640 CK_i386, 1641 //@} 1642 1643 /// \name i486 1644 /// i486-generation processors. 1645 //@{ 1646 CK_i486, 1647 CK_WinChipC6, 1648 CK_WinChip2, 1649 CK_C3, 1650 //@} 1651 1652 /// \name i586 1653 /// i586-generation processors, P5 microarchitecture based. 1654 //@{ 1655 CK_i586, 1656 CK_Pentium, 1657 CK_PentiumMMX, 1658 //@} 1659 1660 /// \name i686 1661 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1662 //@{ 1663 CK_i686, 1664 CK_PentiumPro, 1665 CK_Pentium2, 1666 CK_Pentium3, 1667 CK_Pentium3M, 1668 CK_PentiumM, 1669 CK_C3_2, 1670 1671 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1672 /// Clang however has some logic to suport this. 1673 // FIXME: Warn, deprecate, and potentially remove this. 1674 CK_Yonah, 1675 //@} 1676 1677 /// \name Netburst 1678 /// Netburst microarchitecture based processors. 1679 //@{ 1680 CK_Pentium4, 1681 CK_Pentium4M, 1682 CK_Prescott, 1683 CK_Nocona, 1684 //@} 1685 1686 /// \name Core 1687 /// Core microarchitecture based processors. 1688 //@{ 1689 CK_Core2, 1690 1691 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1692 /// codename which GCC no longer accepts as an option to -march, but Clang 1693 /// has some logic for recognizing it. 1694 // FIXME: Warn, deprecate, and potentially remove this. 1695 CK_Penryn, 1696 //@} 1697 1698 /// \name Atom 1699 /// Atom processors 1700 //@{ 1701 CK_Atom, 1702 CK_Silvermont, 1703 //@} 1704 1705 /// \name Nehalem 1706 /// Nehalem microarchitecture based processors. 1707 //@{ 1708 CK_Corei7, 1709 CK_Corei7AVX, 1710 CK_CoreAVXi, 1711 CK_CoreAVX2, 1712 //@} 1713 1714 /// \name Knights Landing 1715 /// Knights Landing processor. 1716 CK_KNL, 1717 1718 /// \name K6 1719 /// K6 architecture processors. 1720 //@{ 1721 CK_K6, 1722 CK_K6_2, 1723 CK_K6_3, 1724 //@} 1725 1726 /// \name K7 1727 /// K7 architecture processors. 1728 //@{ 1729 CK_Athlon, 1730 CK_AthlonThunderbird, 1731 CK_Athlon4, 1732 CK_AthlonXP, 1733 CK_AthlonMP, 1734 //@} 1735 1736 /// \name K8 1737 /// K8 architecture processors. 1738 //@{ 1739 CK_Athlon64, 1740 CK_Athlon64SSE3, 1741 CK_AthlonFX, 1742 CK_K8, 1743 CK_K8SSE3, 1744 CK_Opteron, 1745 CK_OpteronSSE3, 1746 CK_AMDFAM10, 1747 //@} 1748 1749 /// \name Bobcat 1750 /// Bobcat architecture processors. 1751 //@{ 1752 CK_BTVER1, 1753 CK_BTVER2, 1754 //@} 1755 1756 /// \name Bulldozer 1757 /// Bulldozer architecture processors. 1758 //@{ 1759 CK_BDVER1, 1760 CK_BDVER2, 1761 CK_BDVER3, 1762 //@} 1763 1764 /// This specification is deprecated and will be removed in the future. 1765 /// Users should prefer \see CK_K8. 1766 // FIXME: Warn on this when the CPU is set to it. 1767 CK_x86_64, 1768 //@} 1769 1770 /// \name Geode 1771 /// Geode processors. 1772 //@{ 1773 CK_Geode 1774 //@} 1775 } CPU; 1776 1777 enum FPMathKind { 1778 FP_Default, 1779 FP_SSE, 1780 FP_387 1781 } FPMath; 1782 1783 public: 1784 X86TargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1786 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1787 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1788 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1789 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1790 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1791 FPMath(FP_Default) { 1792 BigEndian = false; 1793 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1794 } 1795 unsigned getFloatEvalMethod() const override { 1796 // X87 evaluates with 80 bits "long double" precision. 1797 return SSELevel == NoSSE ? 2 : 0; 1798 } 1799 void getTargetBuiltins(const Builtin::Info *&Records, 1800 unsigned &NumRecords) const override { 1801 Records = BuiltinInfo; 1802 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1803 } 1804 void getGCCRegNames(const char * const *&Names, 1805 unsigned &NumNames) const override { 1806 Names = GCCRegNames; 1807 NumNames = llvm::array_lengthof(GCCRegNames); 1808 } 1809 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1810 unsigned &NumAliases) const override { 1811 Aliases = 0; 1812 NumAliases = 0; 1813 } 1814 void getGCCAddlRegNames(const AddlRegName *&Names, 1815 unsigned &NumNames) const override { 1816 Names = AddlRegNames; 1817 NumNames = llvm::array_lengthof(AddlRegNames); 1818 } 1819 bool validateAsmConstraint(const char *&Name, 1820 TargetInfo::ConstraintInfo &info) const override; 1821 std::string convertConstraint(const char *&Constraint) const override; 1822 const char *getClobbers() const override { 1823 return "~{dirflag},~{fpsr},~{flags}"; 1824 } 1825 void getTargetDefines(const LangOptions &Opts, 1826 MacroBuilder &Builder) const override; 1827 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1828 bool Enabled); 1829 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1830 bool Enabled); 1831 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1832 bool Enabled); 1833 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1834 StringRef Name, bool Enabled) const override { 1835 setFeatureEnabledImpl(Features, Name, Enabled); 1836 } 1837 // This exists purely to cut down on the number of virtual calls in 1838 // getDefaultFeatures which calls this repeatedly. 1839 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1840 StringRef Name, bool Enabled); 1841 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1842 bool hasFeature(StringRef Feature) const override; 1843 bool handleTargetFeatures(std::vector<std::string> &Features, 1844 DiagnosticsEngine &Diags) override; 1845 const char* getABI() const override { 1846 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1847 return "avx"; 1848 else if (getTriple().getArch() == llvm::Triple::x86 && 1849 MMX3DNowLevel == NoMMX3DNow) 1850 return "no-mmx"; 1851 return ""; 1852 } 1853 bool setCPU(const std::string &Name) override { 1854 CPU = llvm::StringSwitch<CPUKind>(Name) 1855 .Case("i386", CK_i386) 1856 .Case("i486", CK_i486) 1857 .Case("winchip-c6", CK_WinChipC6) 1858 .Case("winchip2", CK_WinChip2) 1859 .Case("c3", CK_C3) 1860 .Case("i586", CK_i586) 1861 .Case("pentium", CK_Pentium) 1862 .Case("pentium-mmx", CK_PentiumMMX) 1863 .Case("i686", CK_i686) 1864 .Case("pentiumpro", CK_PentiumPro) 1865 .Case("pentium2", CK_Pentium2) 1866 .Case("pentium3", CK_Pentium3) 1867 .Case("pentium3m", CK_Pentium3M) 1868 .Case("pentium-m", CK_PentiumM) 1869 .Case("c3-2", CK_C3_2) 1870 .Case("yonah", CK_Yonah) 1871 .Case("pentium4", CK_Pentium4) 1872 .Case("pentium4m", CK_Pentium4M) 1873 .Case("prescott", CK_Prescott) 1874 .Case("nocona", CK_Nocona) 1875 .Case("core2", CK_Core2) 1876 .Case("penryn", CK_Penryn) 1877 .Case("atom", CK_Atom) 1878 .Case("slm", CK_Silvermont) 1879 .Case("corei7", CK_Corei7) 1880 .Case("corei7-avx", CK_Corei7AVX) 1881 .Case("core-avx-i", CK_CoreAVXi) 1882 .Case("core-avx2", CK_CoreAVX2) 1883 .Case("knl", CK_KNL) 1884 .Case("k6", CK_K6) 1885 .Case("k6-2", CK_K6_2) 1886 .Case("k6-3", CK_K6_3) 1887 .Case("athlon", CK_Athlon) 1888 .Case("athlon-tbird", CK_AthlonThunderbird) 1889 .Case("athlon-4", CK_Athlon4) 1890 .Case("athlon-xp", CK_AthlonXP) 1891 .Case("athlon-mp", CK_AthlonMP) 1892 .Case("athlon64", CK_Athlon64) 1893 .Case("athlon64-sse3", CK_Athlon64SSE3) 1894 .Case("athlon-fx", CK_AthlonFX) 1895 .Case("k8", CK_K8) 1896 .Case("k8-sse3", CK_K8SSE3) 1897 .Case("opteron", CK_Opteron) 1898 .Case("opteron-sse3", CK_OpteronSSE3) 1899 .Case("amdfam10", CK_AMDFAM10) 1900 .Case("btver1", CK_BTVER1) 1901 .Case("btver2", CK_BTVER2) 1902 .Case("bdver1", CK_BDVER1) 1903 .Case("bdver2", CK_BDVER2) 1904 .Case("bdver3", CK_BDVER3) 1905 .Case("x86-64", CK_x86_64) 1906 .Case("geode", CK_Geode) 1907 .Default(CK_Generic); 1908 1909 // Perform any per-CPU checks necessary to determine if this CPU is 1910 // acceptable. 1911 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1912 // invalid without explaining *why*. 1913 switch (CPU) { 1914 case CK_Generic: 1915 // No processor selected! 1916 return false; 1917 1918 case CK_i386: 1919 case CK_i486: 1920 case CK_WinChipC6: 1921 case CK_WinChip2: 1922 case CK_C3: 1923 case CK_i586: 1924 case CK_Pentium: 1925 case CK_PentiumMMX: 1926 case CK_i686: 1927 case CK_PentiumPro: 1928 case CK_Pentium2: 1929 case CK_Pentium3: 1930 case CK_Pentium3M: 1931 case CK_PentiumM: 1932 case CK_Yonah: 1933 case CK_C3_2: 1934 case CK_Pentium4: 1935 case CK_Pentium4M: 1936 case CK_Prescott: 1937 case CK_K6: 1938 case CK_K6_2: 1939 case CK_K6_3: 1940 case CK_Athlon: 1941 case CK_AthlonThunderbird: 1942 case CK_Athlon4: 1943 case CK_AthlonXP: 1944 case CK_AthlonMP: 1945 case CK_Geode: 1946 // Only accept certain architectures when compiling in 32-bit mode. 1947 if (getTriple().getArch() != llvm::Triple::x86) 1948 return false; 1949 1950 // Fallthrough 1951 case CK_Nocona: 1952 case CK_Core2: 1953 case CK_Penryn: 1954 case CK_Atom: 1955 case CK_Silvermont: 1956 case CK_Corei7: 1957 case CK_Corei7AVX: 1958 case CK_CoreAVXi: 1959 case CK_CoreAVX2: 1960 case CK_KNL: 1961 case CK_Athlon64: 1962 case CK_Athlon64SSE3: 1963 case CK_AthlonFX: 1964 case CK_K8: 1965 case CK_K8SSE3: 1966 case CK_Opteron: 1967 case CK_OpteronSSE3: 1968 case CK_AMDFAM10: 1969 case CK_BTVER1: 1970 case CK_BTVER2: 1971 case CK_BDVER1: 1972 case CK_BDVER2: 1973 case CK_BDVER3: 1974 case CK_x86_64: 1975 return true; 1976 } 1977 llvm_unreachable("Unhandled CPU kind"); 1978 } 1979 1980 bool setFPMath(StringRef Name) override; 1981 1982 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1983 // We accept all non-ARM calling conventions 1984 return (CC == CC_X86ThisCall || 1985 CC == CC_X86FastCall || 1986 CC == CC_X86StdCall || 1987 CC == CC_C || 1988 CC == CC_X86Pascal || 1989 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1990 } 1991 1992 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 1993 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1994 } 1995 }; 1996 1997 bool X86TargetInfo::setFPMath(StringRef Name) { 1998 if (Name == "387") { 1999 FPMath = FP_387; 2000 return true; 2001 } 2002 if (Name == "sse") { 2003 FPMath = FP_SSE; 2004 return true; 2005 } 2006 return false; 2007 } 2008 2009 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2010 // FIXME: This *really* should not be here. 2011 2012 // X86_64 always has SSE2. 2013 if (getTriple().getArch() == llvm::Triple::x86_64) 2014 setFeatureEnabledImpl(Features, "sse2", true); 2015 2016 switch (CPU) { 2017 case CK_Generic: 2018 case CK_i386: 2019 case CK_i486: 2020 case CK_i586: 2021 case CK_Pentium: 2022 case CK_i686: 2023 case CK_PentiumPro: 2024 break; 2025 case CK_PentiumMMX: 2026 case CK_Pentium2: 2027 setFeatureEnabledImpl(Features, "mmx", true); 2028 break; 2029 case CK_Pentium3: 2030 case CK_Pentium3M: 2031 setFeatureEnabledImpl(Features, "sse", true); 2032 break; 2033 case CK_PentiumM: 2034 case CK_Pentium4: 2035 case CK_Pentium4M: 2036 case CK_x86_64: 2037 setFeatureEnabledImpl(Features, "sse2", true); 2038 break; 2039 case CK_Yonah: 2040 case CK_Prescott: 2041 case CK_Nocona: 2042 setFeatureEnabledImpl(Features, "sse3", true); 2043 setFeatureEnabledImpl(Features, "cx16", true); 2044 break; 2045 case CK_Core2: 2046 setFeatureEnabledImpl(Features, "ssse3", true); 2047 setFeatureEnabledImpl(Features, "cx16", true); 2048 break; 2049 case CK_Penryn: 2050 setFeatureEnabledImpl(Features, "sse4.1", true); 2051 setFeatureEnabledImpl(Features, "cx16", true); 2052 break; 2053 case CK_Atom: 2054 setFeatureEnabledImpl(Features, "ssse3", true); 2055 setFeatureEnabledImpl(Features, "cx16", true); 2056 break; 2057 case CK_Silvermont: 2058 setFeatureEnabledImpl(Features, "sse4.2", true); 2059 setFeatureEnabledImpl(Features, "aes", true); 2060 setFeatureEnabledImpl(Features, "cx16", true); 2061 setFeatureEnabledImpl(Features, "pclmul", true); 2062 break; 2063 case CK_Corei7: 2064 setFeatureEnabledImpl(Features, "sse4.2", true); 2065 setFeatureEnabledImpl(Features, "cx16", true); 2066 break; 2067 case CK_Corei7AVX: 2068 setFeatureEnabledImpl(Features, "avx", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 setFeatureEnabledImpl(Features, "pclmul", true); 2072 break; 2073 case CK_CoreAVXi: 2074 setFeatureEnabledImpl(Features, "avx", true); 2075 setFeatureEnabledImpl(Features, "aes", true); 2076 setFeatureEnabledImpl(Features, "pclmul", true); 2077 setFeatureEnabledImpl(Features, "rdrnd", true); 2078 setFeatureEnabledImpl(Features, "f16c", true); 2079 break; 2080 case CK_CoreAVX2: 2081 setFeatureEnabledImpl(Features, "avx2", true); 2082 setFeatureEnabledImpl(Features, "aes", true); 2083 setFeatureEnabledImpl(Features, "pclmul", true); 2084 setFeatureEnabledImpl(Features, "lzcnt", true); 2085 setFeatureEnabledImpl(Features, "rdrnd", true); 2086 setFeatureEnabledImpl(Features, "f16c", true); 2087 setFeatureEnabledImpl(Features, "bmi", true); 2088 setFeatureEnabledImpl(Features, "bmi2", true); 2089 setFeatureEnabledImpl(Features, "rtm", true); 2090 setFeatureEnabledImpl(Features, "fma", true); 2091 setFeatureEnabledImpl(Features, "cx16", true); 2092 break; 2093 case CK_KNL: 2094 setFeatureEnabledImpl(Features, "avx512f", true); 2095 setFeatureEnabledImpl(Features, "avx512cd", true); 2096 setFeatureEnabledImpl(Features, "avx512er", true); 2097 setFeatureEnabledImpl(Features, "avx512pf", true); 2098 setFeatureEnabledImpl(Features, "aes", true); 2099 setFeatureEnabledImpl(Features, "pclmul", true); 2100 setFeatureEnabledImpl(Features, "lzcnt", true); 2101 setFeatureEnabledImpl(Features, "rdrnd", true); 2102 setFeatureEnabledImpl(Features, "f16c", true); 2103 setFeatureEnabledImpl(Features, "bmi", true); 2104 setFeatureEnabledImpl(Features, "bmi2", true); 2105 setFeatureEnabledImpl(Features, "rtm", true); 2106 setFeatureEnabledImpl(Features, "fma", true); 2107 break; 2108 case CK_K6: 2109 case CK_WinChipC6: 2110 setFeatureEnabledImpl(Features, "mmx", true); 2111 break; 2112 case CK_K6_2: 2113 case CK_K6_3: 2114 case CK_WinChip2: 2115 case CK_C3: 2116 setFeatureEnabledImpl(Features, "3dnow", true); 2117 break; 2118 case CK_Athlon: 2119 case CK_AthlonThunderbird: 2120 case CK_Geode: 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_Athlon4: 2124 case CK_AthlonXP: 2125 case CK_AthlonMP: 2126 setFeatureEnabledImpl(Features, "sse", true); 2127 setFeatureEnabledImpl(Features, "3dnowa", true); 2128 break; 2129 case CK_K8: 2130 case CK_Opteron: 2131 case CK_Athlon64: 2132 case CK_AthlonFX: 2133 setFeatureEnabledImpl(Features, "sse2", true); 2134 setFeatureEnabledImpl(Features, "3dnowa", true); 2135 break; 2136 case CK_K8SSE3: 2137 case CK_OpteronSSE3: 2138 case CK_Athlon64SSE3: 2139 setFeatureEnabledImpl(Features, "sse3", true); 2140 setFeatureEnabledImpl(Features, "3dnowa", true); 2141 break; 2142 case CK_AMDFAM10: 2143 setFeatureEnabledImpl(Features, "sse3", true); 2144 setFeatureEnabledImpl(Features, "sse4a", true); 2145 setFeatureEnabledImpl(Features, "3dnowa", true); 2146 setFeatureEnabledImpl(Features, "lzcnt", true); 2147 setFeatureEnabledImpl(Features, "popcnt", true); 2148 break; 2149 case CK_BTVER1: 2150 setFeatureEnabledImpl(Features, "ssse3", true); 2151 setFeatureEnabledImpl(Features, "sse4a", true); 2152 setFeatureEnabledImpl(Features, "cx16", true); 2153 setFeatureEnabledImpl(Features, "lzcnt", true); 2154 setFeatureEnabledImpl(Features, "popcnt", true); 2155 setFeatureEnabledImpl(Features, "prfchw", true); 2156 break; 2157 case CK_BTVER2: 2158 setFeatureEnabledImpl(Features, "avx", true); 2159 setFeatureEnabledImpl(Features, "sse4a", true); 2160 setFeatureEnabledImpl(Features, "lzcnt", true); 2161 setFeatureEnabledImpl(Features, "aes", true); 2162 setFeatureEnabledImpl(Features, "pclmul", true); 2163 setFeatureEnabledImpl(Features, "prfchw", true); 2164 setFeatureEnabledImpl(Features, "bmi", true); 2165 setFeatureEnabledImpl(Features, "f16c", true); 2166 setFeatureEnabledImpl(Features, "cx16", true); 2167 break; 2168 case CK_BDVER1: 2169 setFeatureEnabledImpl(Features, "xop", true); 2170 setFeatureEnabledImpl(Features, "lzcnt", true); 2171 setFeatureEnabledImpl(Features, "aes", true); 2172 setFeatureEnabledImpl(Features, "pclmul", true); 2173 setFeatureEnabledImpl(Features, "prfchw", true); 2174 setFeatureEnabledImpl(Features, "cx16", true); 2175 break; 2176 case CK_BDVER2: 2177 case CK_BDVER3: 2178 setFeatureEnabledImpl(Features, "xop", true); 2179 setFeatureEnabledImpl(Features, "lzcnt", true); 2180 setFeatureEnabledImpl(Features, "aes", true); 2181 setFeatureEnabledImpl(Features, "pclmul", true); 2182 setFeatureEnabledImpl(Features, "prfchw", true); 2183 setFeatureEnabledImpl(Features, "bmi", true); 2184 setFeatureEnabledImpl(Features, "fma", true); 2185 setFeatureEnabledImpl(Features, "f16c", true); 2186 setFeatureEnabledImpl(Features, "tbm", true); 2187 setFeatureEnabledImpl(Features, "cx16", true); 2188 break; 2189 case CK_C3_2: 2190 setFeatureEnabledImpl(Features, "sse", true); 2191 break; 2192 } 2193 } 2194 2195 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2196 X86SSEEnum Level, bool Enabled) { 2197 if (Enabled) { 2198 switch (Level) { 2199 case AVX512F: 2200 Features["avx512f"] = true; 2201 case AVX2: 2202 Features["avx2"] = true; 2203 case AVX: 2204 Features["avx"] = true; 2205 case SSE42: 2206 Features["sse4.2"] = true; 2207 case SSE41: 2208 Features["sse4.1"] = true; 2209 case SSSE3: 2210 Features["ssse3"] = true; 2211 case SSE3: 2212 Features["sse3"] = true; 2213 case SSE2: 2214 Features["sse2"] = true; 2215 case SSE1: 2216 Features["sse"] = true; 2217 case NoSSE: 2218 break; 2219 } 2220 return; 2221 } 2222 2223 switch (Level) { 2224 case NoSSE: 2225 case SSE1: 2226 Features["sse"] = false; 2227 case SSE2: 2228 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2229 Features["sha"] = false; 2230 case SSE3: 2231 Features["sse3"] = false; 2232 setXOPLevel(Features, NoXOP, false); 2233 case SSSE3: 2234 Features["ssse3"] = false; 2235 case SSE41: 2236 Features["sse4.1"] = false; 2237 case SSE42: 2238 Features["sse4.2"] = false; 2239 case AVX: 2240 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2241 setXOPLevel(Features, FMA4, false); 2242 case AVX2: 2243 Features["avx2"] = false; 2244 case AVX512F: 2245 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2246 Features["avx512pf"] = false; 2247 } 2248 } 2249 2250 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2251 MMX3DNowEnum Level, bool Enabled) { 2252 if (Enabled) { 2253 switch (Level) { 2254 case AMD3DNowAthlon: 2255 Features["3dnowa"] = true; 2256 case AMD3DNow: 2257 Features["3dnow"] = true; 2258 case MMX: 2259 Features["mmx"] = true; 2260 case NoMMX3DNow: 2261 break; 2262 } 2263 return; 2264 } 2265 2266 switch (Level) { 2267 case NoMMX3DNow: 2268 case MMX: 2269 Features["mmx"] = false; 2270 case AMD3DNow: 2271 Features["3dnow"] = false; 2272 case AMD3DNowAthlon: 2273 Features["3dnowa"] = false; 2274 } 2275 } 2276 2277 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2278 bool Enabled) { 2279 if (Enabled) { 2280 switch (Level) { 2281 case XOP: 2282 Features["xop"] = true; 2283 case FMA4: 2284 Features["fma4"] = true; 2285 setSSELevel(Features, AVX, true); 2286 case SSE4A: 2287 Features["sse4a"] = true; 2288 setSSELevel(Features, SSE3, true); 2289 case NoXOP: 2290 break; 2291 } 2292 return; 2293 } 2294 2295 switch (Level) { 2296 case NoXOP: 2297 case SSE4A: 2298 Features["sse4a"] = false; 2299 case FMA4: 2300 Features["fma4"] = false; 2301 case XOP: 2302 Features["xop"] = false; 2303 } 2304 } 2305 2306 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2307 StringRef Name, bool Enabled) { 2308 // FIXME: This *really* should not be here. We need some way of translating 2309 // options into llvm subtarget features. 2310 if (Name == "sse4") 2311 Name = "sse4.2"; 2312 2313 Features[Name] = Enabled; 2314 2315 if (Name == "mmx") { 2316 setMMXLevel(Features, MMX, Enabled); 2317 } else if (Name == "sse") { 2318 setSSELevel(Features, SSE1, Enabled); 2319 } else if (Name == "sse2") { 2320 setSSELevel(Features, SSE2, Enabled); 2321 } else if (Name == "sse3") { 2322 setSSELevel(Features, SSE3, Enabled); 2323 } else if (Name == "ssse3") { 2324 setSSELevel(Features, SSSE3, Enabled); 2325 } else if (Name == "sse4.2") { 2326 setSSELevel(Features, SSE42, Enabled); 2327 } else if (Name == "sse4.1") { 2328 setSSELevel(Features, SSE41, Enabled); 2329 } else if (Name == "3dnow") { 2330 setMMXLevel(Features, AMD3DNow, Enabled); 2331 } else if (Name == "3dnowa") { 2332 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2333 } else if (Name == "aes") { 2334 if (Enabled) 2335 setSSELevel(Features, SSE2, Enabled); 2336 } else if (Name == "pclmul") { 2337 if (Enabled) 2338 setSSELevel(Features, SSE2, Enabled); 2339 } else if (Name == "avx") { 2340 setSSELevel(Features, AVX, Enabled); 2341 } else if (Name == "avx2") { 2342 setSSELevel(Features, AVX2, Enabled); 2343 } else if (Name == "avx512f") { 2344 setSSELevel(Features, AVX512F, Enabled); 2345 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2346 if (Enabled) 2347 setSSELevel(Features, AVX512F, Enabled); 2348 } else if (Name == "fma") { 2349 if (Enabled) 2350 setSSELevel(Features, AVX, Enabled); 2351 } else if (Name == "fma4") { 2352 setXOPLevel(Features, FMA4, Enabled); 2353 } else if (Name == "xop") { 2354 setXOPLevel(Features, XOP, Enabled); 2355 } else if (Name == "sse4a") { 2356 setXOPLevel(Features, SSE4A, Enabled); 2357 } else if (Name == "f16c") { 2358 if (Enabled) 2359 setSSELevel(Features, AVX, Enabled); 2360 } else if (Name == "sha") { 2361 if (Enabled) 2362 setSSELevel(Features, SSE2, Enabled); 2363 } 2364 } 2365 2366 /// handleTargetFeatures - Perform initialization based on the user 2367 /// configured set of features. 2368 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2369 DiagnosticsEngine &Diags) { 2370 // Remember the maximum enabled sselevel. 2371 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2372 // Ignore disabled features. 2373 if (Features[i][0] == '-') 2374 continue; 2375 2376 StringRef Feature = StringRef(Features[i]).substr(1); 2377 2378 if (Feature == "aes") { 2379 HasAES = true; 2380 continue; 2381 } 2382 2383 if (Feature == "pclmul") { 2384 HasPCLMUL = true; 2385 continue; 2386 } 2387 2388 if (Feature == "lzcnt") { 2389 HasLZCNT = true; 2390 continue; 2391 } 2392 2393 if (Feature == "rdrnd") { 2394 HasRDRND = true; 2395 continue; 2396 } 2397 2398 if (Feature == "bmi") { 2399 HasBMI = true; 2400 continue; 2401 } 2402 2403 if (Feature == "bmi2") { 2404 HasBMI2 = true; 2405 continue; 2406 } 2407 2408 if (Feature == "popcnt") { 2409 HasPOPCNT = true; 2410 continue; 2411 } 2412 2413 if (Feature == "rtm") { 2414 HasRTM = true; 2415 continue; 2416 } 2417 2418 if (Feature == "prfchw") { 2419 HasPRFCHW = true; 2420 continue; 2421 } 2422 2423 if (Feature == "rdseed") { 2424 HasRDSEED = true; 2425 continue; 2426 } 2427 2428 if (Feature == "tbm") { 2429 HasTBM = true; 2430 continue; 2431 } 2432 2433 if (Feature == "fma") { 2434 HasFMA = true; 2435 continue; 2436 } 2437 2438 if (Feature == "f16c") { 2439 HasF16C = true; 2440 continue; 2441 } 2442 2443 if (Feature == "avx512cd") { 2444 HasAVX512CD = true; 2445 continue; 2446 } 2447 2448 if (Feature == "avx512er") { 2449 HasAVX512ER = true; 2450 continue; 2451 } 2452 2453 if (Feature == "avx512pf") { 2454 HasAVX512PF = true; 2455 continue; 2456 } 2457 2458 if (Feature == "sha") { 2459 HasSHA = true; 2460 continue; 2461 } 2462 2463 if (Feature == "cx16") { 2464 HasCX16 = true; 2465 continue; 2466 } 2467 2468 assert(Features[i][0] == '+' && "Invalid target feature!"); 2469 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2470 .Case("avx512f", AVX512F) 2471 .Case("avx2", AVX2) 2472 .Case("avx", AVX) 2473 .Case("sse4.2", SSE42) 2474 .Case("sse4.1", SSE41) 2475 .Case("ssse3", SSSE3) 2476 .Case("sse3", SSE3) 2477 .Case("sse2", SSE2) 2478 .Case("sse", SSE1) 2479 .Default(NoSSE); 2480 SSELevel = std::max(SSELevel, Level); 2481 2482 MMX3DNowEnum ThreeDNowLevel = 2483 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2484 .Case("3dnowa", AMD3DNowAthlon) 2485 .Case("3dnow", AMD3DNow) 2486 .Case("mmx", MMX) 2487 .Default(NoMMX3DNow); 2488 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2489 2490 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2491 .Case("xop", XOP) 2492 .Case("fma4", FMA4) 2493 .Case("sse4a", SSE4A) 2494 .Default(NoXOP); 2495 XOPLevel = std::max(XOPLevel, XLevel); 2496 } 2497 2498 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2499 // Can't do this earlier because we need to be able to explicitly enable 2500 // popcnt and still disable sse4.2. 2501 if (!HasPOPCNT && SSELevel >= SSE42 && 2502 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2503 HasPOPCNT = true; 2504 Features.push_back("+popcnt"); 2505 } 2506 2507 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2508 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2509 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2510 HasPRFCHW = true; 2511 Features.push_back("+prfchw"); 2512 } 2513 2514 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2515 // matches the selected sse level. 2516 if (FPMath == FP_SSE && SSELevel < SSE1) { 2517 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2518 return false; 2519 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2520 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2521 return false; 2522 } 2523 2524 // Don't tell the backend if we're turning off mmx; it will end up disabling 2525 // SSE, which we don't want. 2526 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2527 // then enable MMX. 2528 std::vector<std::string>::iterator it; 2529 it = std::find(Features.begin(), Features.end(), "-mmx"); 2530 if (it != Features.end()) 2531 Features.erase(it); 2532 else if (SSELevel > NoSSE) 2533 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2534 return true; 2535 } 2536 2537 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2538 /// definitions for this particular subtarget. 2539 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2540 MacroBuilder &Builder) const { 2541 // Target identification. 2542 if (getTriple().getArch() == llvm::Triple::x86_64) { 2543 Builder.defineMacro("__amd64__"); 2544 Builder.defineMacro("__amd64"); 2545 Builder.defineMacro("__x86_64"); 2546 Builder.defineMacro("__x86_64__"); 2547 } else { 2548 DefineStd(Builder, "i386", Opts); 2549 } 2550 2551 // Subtarget options. 2552 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2553 // truly should be based on -mtune options. 2554 switch (CPU) { 2555 case CK_Generic: 2556 break; 2557 case CK_i386: 2558 // The rest are coming from the i386 define above. 2559 Builder.defineMacro("__tune_i386__"); 2560 break; 2561 case CK_i486: 2562 case CK_WinChipC6: 2563 case CK_WinChip2: 2564 case CK_C3: 2565 defineCPUMacros(Builder, "i486"); 2566 break; 2567 case CK_PentiumMMX: 2568 Builder.defineMacro("__pentium_mmx__"); 2569 Builder.defineMacro("__tune_pentium_mmx__"); 2570 // Fallthrough 2571 case CK_i586: 2572 case CK_Pentium: 2573 defineCPUMacros(Builder, "i586"); 2574 defineCPUMacros(Builder, "pentium"); 2575 break; 2576 case CK_Pentium3: 2577 case CK_Pentium3M: 2578 case CK_PentiumM: 2579 Builder.defineMacro("__tune_pentium3__"); 2580 // Fallthrough 2581 case CK_Pentium2: 2582 case CK_C3_2: 2583 Builder.defineMacro("__tune_pentium2__"); 2584 // Fallthrough 2585 case CK_PentiumPro: 2586 Builder.defineMacro("__tune_i686__"); 2587 Builder.defineMacro("__tune_pentiumpro__"); 2588 // Fallthrough 2589 case CK_i686: 2590 Builder.defineMacro("__i686"); 2591 Builder.defineMacro("__i686__"); 2592 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2593 Builder.defineMacro("__pentiumpro"); 2594 Builder.defineMacro("__pentiumpro__"); 2595 break; 2596 case CK_Pentium4: 2597 case CK_Pentium4M: 2598 defineCPUMacros(Builder, "pentium4"); 2599 break; 2600 case CK_Yonah: 2601 case CK_Prescott: 2602 case CK_Nocona: 2603 defineCPUMacros(Builder, "nocona"); 2604 break; 2605 case CK_Core2: 2606 case CK_Penryn: 2607 defineCPUMacros(Builder, "core2"); 2608 break; 2609 case CK_Atom: 2610 defineCPUMacros(Builder, "atom"); 2611 break; 2612 case CK_Silvermont: 2613 defineCPUMacros(Builder, "slm"); 2614 break; 2615 case CK_Corei7: 2616 case CK_Corei7AVX: 2617 case CK_CoreAVXi: 2618 case CK_CoreAVX2: 2619 defineCPUMacros(Builder, "corei7"); 2620 break; 2621 case CK_KNL: 2622 defineCPUMacros(Builder, "knl"); 2623 break; 2624 case CK_K6_2: 2625 Builder.defineMacro("__k6_2__"); 2626 Builder.defineMacro("__tune_k6_2__"); 2627 // Fallthrough 2628 case CK_K6_3: 2629 if (CPU != CK_K6_2) { // In case of fallthrough 2630 // FIXME: GCC may be enabling these in cases where some other k6 2631 // architecture is specified but -m3dnow is explicitly provided. The 2632 // exact semantics need to be determined and emulated here. 2633 Builder.defineMacro("__k6_3__"); 2634 Builder.defineMacro("__tune_k6_3__"); 2635 } 2636 // Fallthrough 2637 case CK_K6: 2638 defineCPUMacros(Builder, "k6"); 2639 break; 2640 case CK_Athlon: 2641 case CK_AthlonThunderbird: 2642 case CK_Athlon4: 2643 case CK_AthlonXP: 2644 case CK_AthlonMP: 2645 defineCPUMacros(Builder, "athlon"); 2646 if (SSELevel != NoSSE) { 2647 Builder.defineMacro("__athlon_sse__"); 2648 Builder.defineMacro("__tune_athlon_sse__"); 2649 } 2650 break; 2651 case CK_K8: 2652 case CK_K8SSE3: 2653 case CK_x86_64: 2654 case CK_Opteron: 2655 case CK_OpteronSSE3: 2656 case CK_Athlon64: 2657 case CK_Athlon64SSE3: 2658 case CK_AthlonFX: 2659 defineCPUMacros(Builder, "k8"); 2660 break; 2661 case CK_AMDFAM10: 2662 defineCPUMacros(Builder, "amdfam10"); 2663 break; 2664 case CK_BTVER1: 2665 defineCPUMacros(Builder, "btver1"); 2666 break; 2667 case CK_BTVER2: 2668 defineCPUMacros(Builder, "btver2"); 2669 break; 2670 case CK_BDVER1: 2671 defineCPUMacros(Builder, "bdver1"); 2672 break; 2673 case CK_BDVER2: 2674 defineCPUMacros(Builder, "bdver2"); 2675 break; 2676 case CK_BDVER3: 2677 defineCPUMacros(Builder, "bdver3"); 2678 break; 2679 case CK_Geode: 2680 defineCPUMacros(Builder, "geode"); 2681 break; 2682 } 2683 2684 // Target properties. 2685 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2686 2687 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2688 // functions in glibc header files that use FP Stack inline asm which the 2689 // backend can't deal with (PR879). 2690 Builder.defineMacro("__NO_MATH_INLINES"); 2691 2692 if (HasAES) 2693 Builder.defineMacro("__AES__"); 2694 2695 if (HasPCLMUL) 2696 Builder.defineMacro("__PCLMUL__"); 2697 2698 if (HasLZCNT) 2699 Builder.defineMacro("__LZCNT__"); 2700 2701 if (HasRDRND) 2702 Builder.defineMacro("__RDRND__"); 2703 2704 if (HasBMI) 2705 Builder.defineMacro("__BMI__"); 2706 2707 if (HasBMI2) 2708 Builder.defineMacro("__BMI2__"); 2709 2710 if (HasPOPCNT) 2711 Builder.defineMacro("__POPCNT__"); 2712 2713 if (HasRTM) 2714 Builder.defineMacro("__RTM__"); 2715 2716 if (HasPRFCHW) 2717 Builder.defineMacro("__PRFCHW__"); 2718 2719 if (HasRDSEED) 2720 Builder.defineMacro("__RDSEED__"); 2721 2722 if (HasTBM) 2723 Builder.defineMacro("__TBM__"); 2724 2725 switch (XOPLevel) { 2726 case XOP: 2727 Builder.defineMacro("__XOP__"); 2728 case FMA4: 2729 Builder.defineMacro("__FMA4__"); 2730 case SSE4A: 2731 Builder.defineMacro("__SSE4A__"); 2732 case NoXOP: 2733 break; 2734 } 2735 2736 if (HasFMA) 2737 Builder.defineMacro("__FMA__"); 2738 2739 if (HasF16C) 2740 Builder.defineMacro("__F16C__"); 2741 2742 if (HasAVX512CD) 2743 Builder.defineMacro("__AVX512CD__"); 2744 if (HasAVX512ER) 2745 Builder.defineMacro("__AVX512ER__"); 2746 if (HasAVX512PF) 2747 Builder.defineMacro("__AVX512PF__"); 2748 2749 if (HasSHA) 2750 Builder.defineMacro("__SHA__"); 2751 2752 if (HasCX16) 2753 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2754 2755 // Each case falls through to the previous one here. 2756 switch (SSELevel) { 2757 case AVX512F: 2758 Builder.defineMacro("__AVX512F__"); 2759 case AVX2: 2760 Builder.defineMacro("__AVX2__"); 2761 case AVX: 2762 Builder.defineMacro("__AVX__"); 2763 case SSE42: 2764 Builder.defineMacro("__SSE4_2__"); 2765 case SSE41: 2766 Builder.defineMacro("__SSE4_1__"); 2767 case SSSE3: 2768 Builder.defineMacro("__SSSE3__"); 2769 case SSE3: 2770 Builder.defineMacro("__SSE3__"); 2771 case SSE2: 2772 Builder.defineMacro("__SSE2__"); 2773 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2774 case SSE1: 2775 Builder.defineMacro("__SSE__"); 2776 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2777 case NoSSE: 2778 break; 2779 } 2780 2781 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2782 switch (SSELevel) { 2783 case AVX512F: 2784 case AVX2: 2785 case AVX: 2786 case SSE42: 2787 case SSE41: 2788 case SSSE3: 2789 case SSE3: 2790 case SSE2: 2791 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2792 break; 2793 case SSE1: 2794 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2795 break; 2796 default: 2797 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2798 } 2799 } 2800 2801 // Each case falls through to the previous one here. 2802 switch (MMX3DNowLevel) { 2803 case AMD3DNowAthlon: 2804 Builder.defineMacro("__3dNOW_A__"); 2805 case AMD3DNow: 2806 Builder.defineMacro("__3dNOW__"); 2807 case MMX: 2808 Builder.defineMacro("__MMX__"); 2809 case NoMMX3DNow: 2810 break; 2811 } 2812 2813 if (CPU >= CK_i486) { 2814 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2815 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2817 } 2818 if (CPU >= CK_i586) 2819 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2820 } 2821 2822 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2823 return llvm::StringSwitch<bool>(Feature) 2824 .Case("aes", HasAES) 2825 .Case("avx", SSELevel >= AVX) 2826 .Case("avx2", SSELevel >= AVX2) 2827 .Case("avx512f", SSELevel >= AVX512F) 2828 .Case("avx512cd", HasAVX512CD) 2829 .Case("avx512er", HasAVX512ER) 2830 .Case("avx512pf", HasAVX512PF) 2831 .Case("bmi", HasBMI) 2832 .Case("bmi2", HasBMI2) 2833 .Case("cx16", HasCX16) 2834 .Case("f16c", HasF16C) 2835 .Case("fma", HasFMA) 2836 .Case("fma4", XOPLevel >= FMA4) 2837 .Case("tbm", HasTBM) 2838 .Case("lzcnt", HasLZCNT) 2839 .Case("rdrnd", HasRDRND) 2840 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2841 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2842 .Case("mmx", MMX3DNowLevel >= MMX) 2843 .Case("pclmul", HasPCLMUL) 2844 .Case("popcnt", HasPOPCNT) 2845 .Case("rtm", HasRTM) 2846 .Case("prfchw", HasPRFCHW) 2847 .Case("rdseed", HasRDSEED) 2848 .Case("sha", HasSHA) 2849 .Case("sse", SSELevel >= SSE1) 2850 .Case("sse2", SSELevel >= SSE2) 2851 .Case("sse3", SSELevel >= SSE3) 2852 .Case("ssse3", SSELevel >= SSSE3) 2853 .Case("sse4.1", SSELevel >= SSE41) 2854 .Case("sse4.2", SSELevel >= SSE42) 2855 .Case("sse4a", XOPLevel >= SSE4A) 2856 .Case("x86", true) 2857 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2858 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2859 .Case("xop", XOPLevel >= XOP) 2860 .Default(false); 2861 } 2862 2863 bool 2864 X86TargetInfo::validateAsmConstraint(const char *&Name, 2865 TargetInfo::ConstraintInfo &Info) const { 2866 switch (*Name) { 2867 default: return false; 2868 case 'Y': // first letter of a pair: 2869 switch (*(Name+1)) { 2870 default: return false; 2871 case '0': // First SSE register. 2872 case 't': // Any SSE register, when SSE2 is enabled. 2873 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2874 case 'm': // any MMX register, when inter-unit moves enabled. 2875 break; // falls through to setAllowsRegister. 2876 } 2877 case 'a': // eax. 2878 case 'b': // ebx. 2879 case 'c': // ecx. 2880 case 'd': // edx. 2881 case 'S': // esi. 2882 case 'D': // edi. 2883 case 'A': // edx:eax. 2884 case 'f': // any x87 floating point stack register. 2885 case 't': // top of floating point stack. 2886 case 'u': // second from top of floating point stack. 2887 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2888 case 'y': // Any MMX register. 2889 case 'x': // Any SSE register. 2890 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2891 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2892 case 'l': // "Index" registers: any general register that can be used as an 2893 // index in a base+index memory access. 2894 Info.setAllowsRegister(); 2895 return true; 2896 case 'C': // SSE floating point constant. 2897 case 'G': // x87 floating point constant. 2898 case 'e': // 32-bit signed integer constant for use with zero-extending 2899 // x86_64 instructions. 2900 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2901 // x86_64 instructions. 2902 return true; 2903 } 2904 } 2905 2906 2907 std::string 2908 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2909 switch (*Constraint) { 2910 case 'a': return std::string("{ax}"); 2911 case 'b': return std::string("{bx}"); 2912 case 'c': return std::string("{cx}"); 2913 case 'd': return std::string("{dx}"); 2914 case 'S': return std::string("{si}"); 2915 case 'D': return std::string("{di}"); 2916 case 'p': // address 2917 return std::string("im"); 2918 case 't': // top of floating point stack. 2919 return std::string("{st}"); 2920 case 'u': // second from top of floating point stack. 2921 return std::string("{st(1)}"); // second from top of floating point stack. 2922 default: 2923 return std::string(1, *Constraint); 2924 } 2925 } 2926 } // end anonymous namespace 2927 2928 namespace { 2929 // X86-32 generic target 2930 class X86_32TargetInfo : public X86TargetInfo { 2931 public: 2932 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2933 DoubleAlign = LongLongAlign = 32; 2934 LongDoubleWidth = 96; 2935 LongDoubleAlign = 32; 2936 SuitableAlign = 128; 2937 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2938 SizeType = UnsignedInt; 2939 PtrDiffType = SignedInt; 2940 IntPtrType = SignedInt; 2941 RegParmMax = 3; 2942 2943 // Use fpret for all types. 2944 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2945 (1 << TargetInfo::Double) | 2946 (1 << TargetInfo::LongDouble)); 2947 2948 // x86-32 has atomics up to 8 bytes 2949 // FIXME: Check that we actually have cmpxchg8b before setting 2950 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2951 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2952 } 2953 BuiltinVaListKind getBuiltinVaListKind() const override { 2954 return TargetInfo::CharPtrBuiltinVaList; 2955 } 2956 2957 int getEHDataRegisterNumber(unsigned RegNo) const override { 2958 if (RegNo == 0) return 0; 2959 if (RegNo == 1) return 2; 2960 return -1; 2961 } 2962 bool validateInputSize(StringRef Constraint, 2963 unsigned Size) const override { 2964 switch (Constraint[0]) { 2965 default: break; 2966 case 'a': 2967 case 'b': 2968 case 'c': 2969 case 'd': 2970 return Size <= 32; 2971 } 2972 2973 return true; 2974 } 2975 }; 2976 } // end anonymous namespace 2977 2978 namespace { 2979 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2980 public: 2981 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2982 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2983 2984 unsigned getFloatEvalMethod() const override { 2985 unsigned Major, Minor, Micro; 2986 getTriple().getOSVersion(Major, Minor, Micro); 2987 // New NetBSD uses the default rounding mode. 2988 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2989 return X86_32TargetInfo::getFloatEvalMethod(); 2990 // NetBSD before 6.99.26 defaults to "double" rounding. 2991 return 1; 2992 } 2993 }; 2994 } // end anonymous namespace 2995 2996 namespace { 2997 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2998 public: 2999 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3000 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3001 SizeType = UnsignedLong; 3002 IntPtrType = SignedLong; 3003 PtrDiffType = SignedLong; 3004 } 3005 }; 3006 } // end anonymous namespace 3007 3008 namespace { 3009 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3010 public: 3011 BitrigI386TargetInfo(const llvm::Triple &Triple) 3012 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3013 SizeType = UnsignedLong; 3014 IntPtrType = SignedLong; 3015 PtrDiffType = SignedLong; 3016 } 3017 }; 3018 } // end anonymous namespace 3019 3020 namespace { 3021 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3022 public: 3023 DarwinI386TargetInfo(const llvm::Triple &Triple) 3024 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3025 LongDoubleWidth = 128; 3026 LongDoubleAlign = 128; 3027 SuitableAlign = 128; 3028 MaxVectorAlign = 256; 3029 SizeType = UnsignedLong; 3030 IntPtrType = SignedLong; 3031 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3032 HasAlignMac68kSupport = true; 3033 } 3034 3035 }; 3036 } // end anonymous namespace 3037 3038 namespace { 3039 // x86-32 Windows target 3040 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3041 public: 3042 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3043 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3044 TLSSupported = false; 3045 WCharType = UnsignedShort; 3046 DoubleAlign = LongLongAlign = 64; 3047 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3048 } 3049 void getTargetDefines(const LangOptions &Opts, 3050 MacroBuilder &Builder) const override { 3051 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3052 } 3053 }; 3054 } // end anonymous namespace 3055 3056 namespace { 3057 3058 // x86-32 Windows Visual Studio target 3059 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3060 public: 3061 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3062 : WindowsX86_32TargetInfo(Triple) { 3063 LongDoubleWidth = LongDoubleAlign = 64; 3064 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3065 } 3066 void getTargetDefines(const LangOptions &Opts, 3067 MacroBuilder &Builder) const override { 3068 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3069 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3070 // The value of the following reflects processor type. 3071 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3072 // We lost the original triple, so we use the default. 3073 Builder.defineMacro("_M_IX86", "600"); 3074 } 3075 }; 3076 } // end anonymous namespace 3077 3078 namespace { 3079 // x86-32 MinGW target 3080 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3081 public: 3082 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3083 : WindowsX86_32TargetInfo(Triple) {} 3084 void getTargetDefines(const LangOptions &Opts, 3085 MacroBuilder &Builder) const override { 3086 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3087 DefineStd(Builder, "WIN32", Opts); 3088 DefineStd(Builder, "WINNT", Opts); 3089 Builder.defineMacro("_X86_"); 3090 Builder.defineMacro("__MSVCRT__"); 3091 Builder.defineMacro("__MINGW32__"); 3092 3093 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3094 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3095 if (Opts.MicrosoftExt) 3096 // Provide "as-is" __declspec. 3097 Builder.defineMacro("__declspec", "__declspec"); 3098 else 3099 // Provide alias of __attribute__ like mingw32-gcc. 3100 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3101 } 3102 }; 3103 } // end anonymous namespace 3104 3105 namespace { 3106 // x86-32 Cygwin target 3107 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3108 public: 3109 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3110 : X86_32TargetInfo(Triple) { 3111 TLSSupported = false; 3112 WCharType = UnsignedShort; 3113 DoubleAlign = LongLongAlign = 64; 3114 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3115 } 3116 void getTargetDefines(const LangOptions &Opts, 3117 MacroBuilder &Builder) const override { 3118 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3119 Builder.defineMacro("_X86_"); 3120 Builder.defineMacro("__CYGWIN__"); 3121 Builder.defineMacro("__CYGWIN32__"); 3122 DefineStd(Builder, "unix", Opts); 3123 if (Opts.CPlusPlus) 3124 Builder.defineMacro("_GNU_SOURCE"); 3125 } 3126 }; 3127 } // end anonymous namespace 3128 3129 namespace { 3130 // x86-32 Haiku target 3131 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3132 public: 3133 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3134 SizeType = UnsignedLong; 3135 IntPtrType = SignedLong; 3136 PtrDiffType = SignedLong; 3137 ProcessIDType = SignedLong; 3138 this->UserLabelPrefix = ""; 3139 this->TLSSupported = false; 3140 } 3141 void getTargetDefines(const LangOptions &Opts, 3142 MacroBuilder &Builder) const override { 3143 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3144 Builder.defineMacro("__INTEL__"); 3145 Builder.defineMacro("__HAIKU__"); 3146 } 3147 }; 3148 } // end anonymous namespace 3149 3150 // RTEMS Target 3151 template<typename Target> 3152 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3153 protected: 3154 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3155 MacroBuilder &Builder) const override { 3156 // RTEMS defines; list based off of gcc output 3157 3158 Builder.defineMacro("__rtems__"); 3159 Builder.defineMacro("__ELF__"); 3160 } 3161 3162 public: 3163 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3164 this->UserLabelPrefix = ""; 3165 3166 switch (Triple.getArch()) { 3167 default: 3168 case llvm::Triple::x86: 3169 // this->MCountName = ".mcount"; 3170 break; 3171 case llvm::Triple::mips: 3172 case llvm::Triple::mipsel: 3173 case llvm::Triple::ppc: 3174 case llvm::Triple::ppc64: 3175 case llvm::Triple::ppc64le: 3176 // this->MCountName = "_mcount"; 3177 break; 3178 case llvm::Triple::arm: 3179 // this->MCountName = "__mcount"; 3180 break; 3181 } 3182 } 3183 }; 3184 3185 namespace { 3186 // x86-32 RTEMS target 3187 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3188 public: 3189 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3190 SizeType = UnsignedLong; 3191 IntPtrType = SignedLong; 3192 PtrDiffType = SignedLong; 3193 this->UserLabelPrefix = ""; 3194 } 3195 void getTargetDefines(const LangOptions &Opts, 3196 MacroBuilder &Builder) const override { 3197 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3198 Builder.defineMacro("__INTEL__"); 3199 Builder.defineMacro("__rtems__"); 3200 } 3201 }; 3202 } // end anonymous namespace 3203 3204 namespace { 3205 // x86-64 generic target 3206 class X86_64TargetInfo : public X86TargetInfo { 3207 public: 3208 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3209 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3210 LongDoubleWidth = 128; 3211 LongDoubleAlign = 128; 3212 LargeArrayMinWidth = 128; 3213 LargeArrayAlign = 128; 3214 SuitableAlign = 128; 3215 IntMaxType = SignedLong; 3216 UIntMaxType = UnsignedLong; 3217 Int64Type = SignedLong; 3218 RegParmMax = 6; 3219 3220 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3221 3222 // Use fpret only for long double. 3223 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3224 3225 // Use fp2ret for _Complex long double. 3226 ComplexLongDoubleUsesFP2Ret = true; 3227 3228 // x86-64 has atomics up to 16 bytes. 3229 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3230 // on CPUs with cmpxchg16b 3231 MaxAtomicPromoteWidth = 128; 3232 MaxAtomicInlineWidth = 64; 3233 } 3234 BuiltinVaListKind getBuiltinVaListKind() const override { 3235 return TargetInfo::X86_64ABIBuiltinVaList; 3236 } 3237 3238 int getEHDataRegisterNumber(unsigned RegNo) const override { 3239 if (RegNo == 0) return 0; 3240 if (RegNo == 1) return 1; 3241 return -1; 3242 } 3243 3244 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3245 return (CC == CC_C || 3246 CC == CC_IntelOclBicc || 3247 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3248 } 3249 3250 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3251 return CC_C; 3252 } 3253 3254 }; 3255 } // end anonymous namespace 3256 3257 namespace { 3258 // x86-64 Windows target 3259 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3260 public: 3261 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3262 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3263 TLSSupported = false; 3264 WCharType = UnsignedShort; 3265 LongWidth = LongAlign = 32; 3266 DoubleAlign = LongLongAlign = 64; 3267 IntMaxType = SignedLongLong; 3268 UIntMaxType = UnsignedLongLong; 3269 Int64Type = SignedLongLong; 3270 SizeType = UnsignedLongLong; 3271 PtrDiffType = SignedLongLong; 3272 IntPtrType = SignedLongLong; 3273 this->UserLabelPrefix = ""; 3274 } 3275 void getTargetDefines(const LangOptions &Opts, 3276 MacroBuilder &Builder) const override { 3277 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3278 Builder.defineMacro("_WIN64"); 3279 } 3280 BuiltinVaListKind getBuiltinVaListKind() const override { 3281 return TargetInfo::CharPtrBuiltinVaList; 3282 } 3283 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3284 return (CC == CC_C || 3285 CC == CC_IntelOclBicc || 3286 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3287 } 3288 }; 3289 } // end anonymous namespace 3290 3291 namespace { 3292 // x86-64 Windows Visual Studio target 3293 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3294 public: 3295 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3296 : WindowsX86_64TargetInfo(Triple) { 3297 LongDoubleWidth = LongDoubleAlign = 64; 3298 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3299 } 3300 void getTargetDefines(const LangOptions &Opts, 3301 MacroBuilder &Builder) const override { 3302 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3303 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3304 Builder.defineMacro("_M_X64"); 3305 Builder.defineMacro("_M_AMD64"); 3306 } 3307 }; 3308 } // end anonymous namespace 3309 3310 namespace { 3311 // x86-64 MinGW target 3312 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3313 public: 3314 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3315 : WindowsX86_64TargetInfo(Triple) {} 3316 void getTargetDefines(const LangOptions &Opts, 3317 MacroBuilder &Builder) const override { 3318 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3319 DefineStd(Builder, "WIN64", Opts); 3320 Builder.defineMacro("__MSVCRT__"); 3321 Builder.defineMacro("__MINGW32__"); 3322 Builder.defineMacro("__MINGW64__"); 3323 3324 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3325 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3326 if (Opts.MicrosoftExt) 3327 // Provide "as-is" __declspec. 3328 Builder.defineMacro("__declspec", "__declspec"); 3329 else 3330 // Provide alias of __attribute__ like mingw32-gcc. 3331 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3332 } 3333 }; 3334 } // end anonymous namespace 3335 3336 namespace { 3337 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3338 public: 3339 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3340 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3341 Int64Type = SignedLongLong; 3342 MaxVectorAlign = 256; 3343 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3344 } 3345 }; 3346 } // end anonymous namespace 3347 3348 namespace { 3349 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3350 public: 3351 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3352 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3353 IntMaxType = SignedLongLong; 3354 UIntMaxType = UnsignedLongLong; 3355 Int64Type = SignedLongLong; 3356 } 3357 }; 3358 } // end anonymous namespace 3359 3360 namespace { 3361 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3362 public: 3363 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3364 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3365 IntMaxType = SignedLongLong; 3366 UIntMaxType = UnsignedLongLong; 3367 Int64Type = SignedLongLong; 3368 } 3369 }; 3370 } 3371 3372 namespace { 3373 class AArch64TargetInfo : public TargetInfo { 3374 virtual void setDescriptionString() = 0; 3375 static const char * const GCCRegNames[]; 3376 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3377 3378 enum FPUModeEnum { 3379 FPUMode, 3380 NeonMode 3381 }; 3382 3383 unsigned FPU; 3384 unsigned Crypto; 3385 static const Builtin::Info BuiltinInfo[]; 3386 3387 public: 3388 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3389 LongWidth = LongAlign = 64; 3390 LongDoubleWidth = LongDoubleAlign = 128; 3391 PointerWidth = PointerAlign = 64; 3392 SuitableAlign = 128; 3393 3394 WCharType = UnsignedInt; 3395 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3396 WCharType = SignedInt; 3397 Int64Type = SignedLongLong; 3398 IntMaxType = SignedLongLong; 3399 UIntMaxType = UnsignedLongLong; 3400 } else { 3401 WCharType = UnsignedInt; 3402 Int64Type = SignedLong; 3403 IntMaxType = SignedLong; 3404 UIntMaxType = UnsignedLong; 3405 } 3406 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3407 3408 // AArch64 backend supports 64-bit operations at the moment. In principle 3409 // 128-bit is possible if register-pairs are used. 3410 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3411 3412 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3413 } 3414 void getTargetDefines(const LangOptions &Opts, 3415 MacroBuilder &Builder) const override { 3416 // GCC defines theses currently 3417 Builder.defineMacro("__aarch64__"); 3418 3419 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3420 Builder.defineMacro("__ARM_ACLE", "200"); 3421 Builder.defineMacro("__ARM_ARCH", "8"); 3422 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3423 3424 Builder.defineMacro("__ARM_64BIT_STATE"); 3425 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3426 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3427 3428 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3429 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3430 Builder.defineMacro("__ARM_FEATURE_FMA"); 3431 Builder.defineMacro("__ARM_FEATURE_DIV"); 3432 3433 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3434 3435 // 0xe implies support for half, single and double precision operations. 3436 Builder.defineMacro("__ARM_FP", "0xe"); 3437 3438 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3439 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3440 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3441 3442 if (Opts.FastMath || Opts.FiniteMathOnly) 3443 Builder.defineMacro("__ARM_FP_FAST"); 3444 3445 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3446 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3447 3448 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3449 Opts.ShortWChar ? "2" : "4"); 3450 3451 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3452 Opts.ShortEnums ? "1" : "4"); 3453 3454 if (FPU == NeonMode) { 3455 Builder.defineMacro("__ARM_NEON"); 3456 // 64-bit NEON supports half, single and double precision operations. 3457 Builder.defineMacro("__ARM_NEON_FP", "7"); 3458 } 3459 3460 if (Crypto) { 3461 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3462 } 3463 } 3464 void getTargetBuiltins(const Builtin::Info *&Records, 3465 unsigned &NumRecords) const override { 3466 Records = BuiltinInfo; 3467 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3468 } 3469 bool hasFeature(StringRef Feature) const override { 3470 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3471 } 3472 3473 bool setCPU(const std::string &Name) override { 3474 return llvm::StringSwitch<bool>(Name) 3475 .Case("generic", true) 3476 .Cases("cortex-a53", "cortex-a57", true) 3477 .Default(false); 3478 } 3479 3480 bool handleTargetFeatures(std::vector<std::string> &Features, 3481 DiagnosticsEngine &Diags) override { 3482 FPU = FPUMode; 3483 Crypto = 0; 3484 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3485 if (Features[i] == "+neon") 3486 FPU = NeonMode; 3487 if (Features[i] == "+crypto") 3488 Crypto = 1; 3489 } 3490 3491 setDescriptionString(); 3492 3493 return true; 3494 } 3495 3496 void getGCCRegNames(const char *const *&Names, 3497 unsigned &NumNames) const override; 3498 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3499 unsigned &NumAliases) const override; 3500 3501 bool isCLZForZeroUndef() const override { return false; } 3502 3503 bool validateAsmConstraint(const char *&Name, 3504 TargetInfo::ConstraintInfo &Info) const override { 3505 switch (*Name) { 3506 default: return false; 3507 case 'w': // An FP/SIMD vector register 3508 Info.setAllowsRegister(); 3509 return true; 3510 case 'I': // Constant that can be used with an ADD instruction 3511 case 'J': // Constant that can be used with a SUB instruction 3512 case 'K': // Constant that can be used with a 32-bit logical instruction 3513 case 'L': // Constant that can be used with a 64-bit logical instruction 3514 case 'M': // Constant that can be used as a 32-bit MOV immediate 3515 case 'N': // Constant that can be used as a 64-bit MOV immediate 3516 case 'Y': // Floating point constant zero 3517 case 'Z': // Integer constant zero 3518 return true; 3519 case 'Q': // A memory reference with base register and no offset 3520 Info.setAllowsMemory(); 3521 return true; 3522 case 'S': // A symbolic address 3523 Info.setAllowsRegister(); 3524 return true; 3525 case 'U': 3526 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3527 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3528 // Usa: An absolute symbolic address 3529 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3530 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3531 } 3532 } 3533 3534 const char *getClobbers() const override { 3535 // There are no AArch64 clobbers shared by all asm statements. 3536 return ""; 3537 } 3538 3539 BuiltinVaListKind getBuiltinVaListKind() const override { 3540 return TargetInfo::AArch64ABIBuiltinVaList; 3541 } 3542 }; 3543 3544 const char * const AArch64TargetInfo::GCCRegNames[] = { 3545 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3546 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3547 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3548 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3549 3550 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3551 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3552 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3553 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3554 3555 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3556 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3557 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3558 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3559 3560 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3561 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3562 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3563 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3564 3565 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3566 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3567 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3568 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3569 3570 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3571 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3572 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3573 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3574 3575 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3576 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3577 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3578 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3579 }; 3580 3581 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3582 unsigned &NumNames) const { 3583 Names = GCCRegNames; 3584 NumNames = llvm::array_lengthof(GCCRegNames); 3585 } 3586 3587 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3588 { { "x16" }, "ip0"}, 3589 { { "x17" }, "ip1"}, 3590 { { "x29" }, "fp" }, 3591 { { "x30" }, "lr" } 3592 }; 3593 3594 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3595 unsigned &NumAliases) const { 3596 Aliases = GCCRegAliases; 3597 NumAliases = llvm::array_lengthof(GCCRegAliases); 3598 3599 } 3600 3601 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3602 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3603 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3604 ALL_LANGUAGES }, 3605 #define GET_NEON_BUILTINS 3606 #include "clang/Basic/arm_neon.inc" 3607 #undef GET_NEON_BUILTINS 3608 3609 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3610 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3611 ALL_LANGUAGES }, 3612 #include "clang/Basic/BuiltinsAArch64.def" 3613 }; 3614 3615 class AArch64leTargetInfo : public AArch64TargetInfo { 3616 void setDescriptionString() override { 3617 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3618 } 3619 3620 public: 3621 AArch64leTargetInfo(const llvm::Triple &Triple) 3622 : AArch64TargetInfo(Triple) { 3623 BigEndian = false; 3624 } 3625 void getTargetDefines(const LangOptions &Opts, 3626 MacroBuilder &Builder) const override { 3627 Builder.defineMacro("__AARCH64EL__"); 3628 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3629 } 3630 }; 3631 3632 class AArch64beTargetInfo : public AArch64TargetInfo { 3633 void setDescriptionString() override { 3634 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3635 } 3636 3637 public: 3638 AArch64beTargetInfo(const llvm::Triple &Triple) 3639 : AArch64TargetInfo(Triple) { } 3640 void getTargetDefines(const LangOptions &Opts, 3641 MacroBuilder &Builder) const override { 3642 Builder.defineMacro("__AARCH64EB__"); 3643 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3644 Builder.defineMacro("__ARM_BIG_ENDIAN"); 3645 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3646 } 3647 }; 3648 3649 } // end anonymous namespace 3650 3651 namespace { 3652 class ARMTargetInfo : public TargetInfo { 3653 // Possible FPU choices. 3654 enum FPUMode { 3655 VFP2FPU = (1 << 0), 3656 VFP3FPU = (1 << 1), 3657 VFP4FPU = (1 << 2), 3658 NeonFPU = (1 << 3), 3659 FPARMV8 = (1 << 4) 3660 }; 3661 3662 // Possible HWDiv features. 3663 enum HWDivMode { 3664 HWDivThumb = (1 << 0), 3665 HWDivARM = (1 << 1) 3666 }; 3667 3668 static bool FPUModeIsVFP(FPUMode Mode) { 3669 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3670 } 3671 3672 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3673 static const char * const GCCRegNames[]; 3674 3675 std::string ABI, CPU; 3676 3677 enum { 3678 FP_Default, 3679 FP_VFP, 3680 FP_Neon 3681 } FPMath; 3682 3683 unsigned FPU : 5; 3684 3685 unsigned IsAAPCS : 1; 3686 unsigned IsThumb : 1; 3687 unsigned HWDiv : 2; 3688 3689 // Initialized via features. 3690 unsigned SoftFloat : 1; 3691 unsigned SoftFloatABI : 1; 3692 3693 unsigned CRC : 1; 3694 unsigned Crypto : 1; 3695 3696 static const Builtin::Info BuiltinInfo[]; 3697 3698 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3699 // On linux, binaries targeting old cpus call functions in libgcc to 3700 // perform atomic operations. The implementation in libgcc then calls into 3701 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3702 // is that if we assume the kernel is at least as recent as the hardware, 3703 // it is safe to use atomic instructions on armv6 and newer. 3704 if (!T.isOSLinux() && 3705 T.getOS() != llvm::Triple::FreeBSD && 3706 T.getOS() != llvm::Triple::NetBSD && 3707 T.getOS() != llvm::Triple::Bitrig) 3708 return false; 3709 StringRef ArchName = T.getArchName(); 3710 if (T.getArch() == llvm::Triple::arm || 3711 T.getArch() == llvm::Triple::armeb) { 3712 StringRef VersionStr; 3713 if (ArchName.startswith("armv")) 3714 VersionStr = ArchName.substr(4); 3715 else if (ArchName.startswith("armebv")) 3716 VersionStr = ArchName.substr(6); 3717 else 3718 return false; 3719 unsigned Version; 3720 if (VersionStr.getAsInteger(10, Version)) 3721 return false; 3722 return Version >= 6; 3723 } 3724 assert(T.getArch() == llvm::Triple::thumb || 3725 T.getArch() == llvm::Triple::thumbeb); 3726 StringRef VersionStr; 3727 if (ArchName.startswith("thumbv")) 3728 VersionStr = ArchName.substr(6); 3729 else if (ArchName.startswith("thumbebv")) 3730 VersionStr = ArchName.substr(8); 3731 else 3732 return false; 3733 unsigned Version; 3734 if (VersionStr.getAsInteger(10, Version)) 3735 return false; 3736 return Version >= 7; 3737 } 3738 3739 void setABIAAPCS() { 3740 IsAAPCS = true; 3741 3742 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3743 const llvm::Triple &T = getTriple(); 3744 3745 // size_t is unsigned long on Darwin and NetBSD. 3746 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3747 SizeType = UnsignedLong; 3748 else 3749 SizeType = UnsignedInt; 3750 3751 if (T.getOS() == llvm::Triple::NetBSD) { 3752 WCharType = SignedInt; 3753 } else { 3754 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3755 WCharType = UnsignedInt; 3756 } 3757 3758 UseBitFieldTypeAlignment = true; 3759 3760 ZeroLengthBitfieldBoundary = 0; 3761 3762 if (IsThumb) { 3763 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3764 // so set preferred for small types to 32. 3765 if (T.isOSBinFormatMachO()) 3766 DescriptionString = BigEndian ? 3767 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3768 "v128:64:128-a:0:32-n32-S64" : 3769 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3770 "v128:64:128-a:0:32-n32-S64"; 3771 else 3772 DescriptionString = BigEndian ? 3773 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3774 "v128:64:128-a:0:32-n32-S64" : 3775 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3776 "v128:64:128-a:0:32-n32-S64"; 3777 3778 } else { 3779 if (T.isOSBinFormatMachO()) 3780 DescriptionString = BigEndian ? 3781 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3782 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3783 else 3784 DescriptionString = BigEndian ? 3785 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3786 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3787 } 3788 3789 // FIXME: Enumerated types are variable width in straight AAPCS. 3790 } 3791 3792 void setABIAPCS() { 3793 const llvm::Triple &T = getTriple(); 3794 3795 IsAAPCS = false; 3796 3797 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3798 3799 // size_t is unsigned int on FreeBSD. 3800 if (T.getOS() == llvm::Triple::FreeBSD) 3801 SizeType = UnsignedInt; 3802 else 3803 SizeType = UnsignedLong; 3804 3805 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3806 WCharType = SignedInt; 3807 3808 // Do not respect the alignment of bit-field types when laying out 3809 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3810 UseBitFieldTypeAlignment = false; 3811 3812 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3813 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3814 /// gcc. 3815 ZeroLengthBitfieldBoundary = 32; 3816 3817 if (IsThumb) { 3818 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3819 // so set preferred for small types to 32. 3820 if (T.isOSBinFormatMachO()) 3821 DescriptionString = BigEndian ? 3822 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3823 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3824 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3825 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3826 else 3827 DescriptionString = BigEndian ? 3828 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3829 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3830 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3831 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3832 } else { 3833 if (T.isOSBinFormatMachO()) 3834 DescriptionString = BigEndian ? 3835 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3836 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3837 else 3838 DescriptionString = BigEndian ? 3839 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3840 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3841 } 3842 3843 // FIXME: Override "preferred align" for double and long long. 3844 } 3845 3846 public: 3847 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3848 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3849 IsAAPCS(true) { 3850 BigEndian = IsBigEndian; 3851 3852 switch (getTriple().getOS()) { 3853 case llvm::Triple::NetBSD: 3854 PtrDiffType = SignedLong; 3855 break; 3856 default: 3857 PtrDiffType = SignedInt; 3858 break; 3859 } 3860 3861 // {} in inline assembly are neon specifiers, not assembly variant 3862 // specifiers. 3863 NoAsmVariants = true; 3864 3865 // FIXME: Should we just treat this as a feature? 3866 IsThumb = getTriple().getArchName().startswith("thumb"); 3867 3868 setABI("aapcs-linux"); 3869 3870 // ARM targets default to using the ARM C++ ABI. 3871 TheCXXABI.set(TargetCXXABI::GenericARM); 3872 3873 // ARM has atomics up to 8 bytes 3874 MaxAtomicPromoteWidth = 64; 3875 if (shouldUseInlineAtomic(getTriple())) 3876 MaxAtomicInlineWidth = 64; 3877 3878 // Do force alignment of members that follow zero length bitfields. If 3879 // the alignment of the zero-length bitfield is greater than the member 3880 // that follows it, `bar', `bar' will be aligned as the type of the 3881 // zero length bitfield. 3882 UseZeroLengthBitfieldAlignment = true; 3883 } 3884 const char *getABI() const override { return ABI.c_str(); } 3885 bool setABI(const std::string &Name) override { 3886 ABI = Name; 3887 3888 // The defaults (above) are for AAPCS, check if we need to change them. 3889 // 3890 // FIXME: We need support for -meabi... we could just mangle it into the 3891 // name. 3892 if (Name == "apcs-gnu") { 3893 setABIAPCS(); 3894 return true; 3895 } 3896 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3897 setABIAAPCS(); 3898 return true; 3899 } 3900 return false; 3901 } 3902 3903 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3904 if (IsAAPCS) 3905 Features["aapcs"] = true; 3906 else 3907 Features["apcs"] = true; 3908 3909 StringRef ArchName = getTriple().getArchName(); 3910 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3911 Features["vfp2"] = true; 3912 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3913 CPU == "cortex-a9-mp") { 3914 Features["vfp3"] = true; 3915 Features["neon"] = true; 3916 } 3917 else if (CPU == "cortex-a5") { 3918 Features["vfp4"] = true; 3919 Features["neon"] = true; 3920 } else if (CPU == "swift" || CPU == "cortex-a7" || 3921 CPU == "cortex-a12" || CPU == "cortex-a15" || 3922 CPU == "krait") { 3923 Features["vfp4"] = true; 3924 Features["neon"] = true; 3925 Features["hwdiv"] = true; 3926 Features["hwdiv-arm"] = true; 3927 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3928 Features["fp-armv8"] = true; 3929 Features["neon"] = true; 3930 Features["hwdiv"] = true; 3931 Features["hwdiv-arm"] = true; 3932 Features["crc"] = true; 3933 Features["crypto"] = true; 3934 } else if (CPU == "cortex-r5" || 3935 // Enable the hwdiv extension for all v8a AArch32 cores by 3936 // default. 3937 ArchName == "armv8a" || ArchName == "armv8" || 3938 ArchName == "armebv8a" || ArchName == "armebv8" || 3939 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3940 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3941 Features["hwdiv"] = true; 3942 Features["hwdiv-arm"] = true; 3943 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3944 Features["hwdiv"] = true; 3945 } 3946 } 3947 3948 bool handleTargetFeatures(std::vector<std::string> &Features, 3949 DiagnosticsEngine &Diags) override { 3950 FPU = 0; 3951 CRC = 0; 3952 Crypto = 0; 3953 SoftFloat = SoftFloatABI = false; 3954 HWDiv = 0; 3955 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3956 if (Features[i] == "+soft-float") 3957 SoftFloat = true; 3958 else if (Features[i] == "+soft-float-abi") 3959 SoftFloatABI = true; 3960 else if (Features[i] == "+vfp2") 3961 FPU |= VFP2FPU; 3962 else if (Features[i] == "+vfp3") 3963 FPU |= VFP3FPU; 3964 else if (Features[i] == "+vfp4") 3965 FPU |= VFP4FPU; 3966 else if (Features[i] == "+fp-armv8") 3967 FPU |= FPARMV8; 3968 else if (Features[i] == "+neon") 3969 FPU |= NeonFPU; 3970 else if (Features[i] == "+hwdiv") 3971 HWDiv |= HWDivThumb; 3972 else if (Features[i] == "+hwdiv-arm") 3973 HWDiv |= HWDivARM; 3974 else if (Features[i] == "+crc") 3975 CRC = 1; 3976 else if (Features[i] == "+crypto") 3977 Crypto = 1; 3978 } 3979 3980 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3981 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3982 return false; 3983 } 3984 3985 if (FPMath == FP_Neon) 3986 Features.push_back("+neonfp"); 3987 else if (FPMath == FP_VFP) 3988 Features.push_back("-neonfp"); 3989 3990 // Remove front-end specific options which the backend handles differently. 3991 std::vector<std::string>::iterator it; 3992 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3993 if (it != Features.end()) 3994 Features.erase(it); 3995 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3996 if (it != Features.end()) 3997 Features.erase(it); 3998 return true; 3999 } 4000 4001 bool hasFeature(StringRef Feature) const override { 4002 return llvm::StringSwitch<bool>(Feature) 4003 .Case("arm", true) 4004 .Case("softfloat", SoftFloat) 4005 .Case("thumb", IsThumb) 4006 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4007 .Case("hwdiv", HWDiv & HWDivThumb) 4008 .Case("hwdiv-arm", HWDiv & HWDivARM) 4009 .Default(false); 4010 } 4011 // FIXME: Should we actually have some table instead of these switches? 4012 static const char *getCPUDefineSuffix(StringRef Name) { 4013 return llvm::StringSwitch<const char*>(Name) 4014 .Cases("arm8", "arm810", "4") 4015 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 4016 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4017 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4018 .Case("ep9312", "4T") 4019 .Cases("arm10tdmi", "arm1020t", "5T") 4020 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4021 .Case("arm926ej-s", "5TEJ") 4022 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4023 .Cases("xscale", "iwmmxt", "5TE") 4024 .Case("arm1136j-s", "6J") 4025 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4026 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4027 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4028 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 4029 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 4030 .Cases("cortex-r4", "cortex-r5", "7R") 4031 .Case("swift", "7S") 4032 .Cases("cortex-m3", "cortex-m4", "7M") 4033 .Case("cortex-m0", "6M") 4034 .Cases("cortex-a53", "cortex-a57", "8A") 4035 .Default(0); 4036 } 4037 static const char *getCPUProfile(StringRef Name) { 4038 return llvm::StringSwitch<const char*>(Name) 4039 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4040 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4041 .Cases("cortex-a53", "cortex-a57", "A") 4042 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4043 .Cases("cortex-r4", "cortex-r5", "R") 4044 .Default(""); 4045 } 4046 bool setCPU(const std::string &Name) override { 4047 if (!getCPUDefineSuffix(Name)) 4048 return false; 4049 4050 CPU = Name; 4051 return true; 4052 } 4053 bool setFPMath(StringRef Name) override; 4054 void getTargetDefines(const LangOptions &Opts, 4055 MacroBuilder &Builder) const override { 4056 // Target identification. 4057 Builder.defineMacro("__arm"); 4058 Builder.defineMacro("__arm__"); 4059 4060 // Target properties. 4061 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4062 4063 StringRef CPUArch = getCPUDefineSuffix(CPU); 4064 unsigned int CPUArchVer; 4065 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4066 llvm_unreachable("Invalid char for architecture version number"); 4067 } 4068 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4069 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4070 StringRef CPUProfile = getCPUProfile(CPU); 4071 if (!CPUProfile.empty()) 4072 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4073 4074 // Subtarget options. 4075 4076 // FIXME: It's more complicated than this and we don't really support 4077 // interworking. 4078 if (5 <= CPUArchVer && CPUArchVer <= 8) 4079 Builder.defineMacro("__THUMB_INTERWORK__"); 4080 4081 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4082 // Embedded targets on Darwin follow AAPCS, but not EABI. 4083 if (!getTriple().isOSDarwin()) 4084 Builder.defineMacro("__ARM_EABI__"); 4085 Builder.defineMacro("__ARM_PCS", "1"); 4086 4087 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4088 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4089 } 4090 4091 if (SoftFloat) 4092 Builder.defineMacro("__SOFTFP__"); 4093 4094 if (CPU == "xscale") 4095 Builder.defineMacro("__XSCALE__"); 4096 4097 if (IsThumb) { 4098 Builder.defineMacro("__THUMBEL__"); 4099 Builder.defineMacro("__thumb__"); 4100 // We check both CPUArchVer and ArchName because when only triple is 4101 // specified, the default CPU is arm1136j-s. 4102 StringRef ArchName = getTriple().getArchName(); 4103 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4104 ArchName.endswith("v7") || ArchName.endswith("v8")) 4105 Builder.defineMacro("__thumb2__"); 4106 } 4107 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4108 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4109 4110 // Note, this is always on in gcc, even though it doesn't make sense. 4111 Builder.defineMacro("__APCS_32__"); 4112 4113 if (FPUModeIsVFP((FPUMode) FPU)) { 4114 Builder.defineMacro("__VFP_FP__"); 4115 if (FPU & VFP2FPU) 4116 Builder.defineMacro("__ARM_VFPV2__"); 4117 if (FPU & VFP3FPU) 4118 Builder.defineMacro("__ARM_VFPV3__"); 4119 if (FPU & VFP4FPU) 4120 Builder.defineMacro("__ARM_VFPV4__"); 4121 } 4122 4123 // This only gets set when Neon instructions are actually available, unlike 4124 // the VFP define, hence the soft float and arch check. This is subtly 4125 // different from gcc, we follow the intent which was that it should be set 4126 // when Neon instructions are actually available. 4127 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4128 Builder.defineMacro("__ARM_NEON"); 4129 Builder.defineMacro("__ARM_NEON__"); 4130 } 4131 4132 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4133 Opts.ShortWChar ? "2" : "4"); 4134 4135 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4136 Opts.ShortEnums ? "1" : "4"); 4137 4138 if (CRC) 4139 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4140 4141 if (Crypto) 4142 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4143 4144 if (CPUArchVer >= 6 && CPUArch != "6M") { 4145 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4146 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4147 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4148 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4149 } 4150 } 4151 void getTargetBuiltins(const Builtin::Info *&Records, 4152 unsigned &NumRecords) const override { 4153 Records = BuiltinInfo; 4154 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4155 } 4156 bool isCLZForZeroUndef() const override { return false; } 4157 BuiltinVaListKind getBuiltinVaListKind() const override { 4158 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4159 } 4160 void getGCCRegNames(const char * const *&Names, 4161 unsigned &NumNames) const override; 4162 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4163 unsigned &NumAliases) const override; 4164 bool validateAsmConstraint(const char *&Name, 4165 TargetInfo::ConstraintInfo &Info) const override { 4166 switch (*Name) { 4167 default: break; 4168 case 'l': // r0-r7 4169 case 'h': // r8-r15 4170 case 'w': // VFP Floating point register single precision 4171 case 'P': // VFP Floating point register double precision 4172 Info.setAllowsRegister(); 4173 return true; 4174 case 'Q': // A memory address that is a single base register. 4175 Info.setAllowsMemory(); 4176 return true; 4177 case 'U': // a memory reference... 4178 switch (Name[1]) { 4179 case 'q': // ...ARMV4 ldrsb 4180 case 'v': // ...VFP load/store (reg+constant offset) 4181 case 'y': // ...iWMMXt load/store 4182 case 't': // address valid for load/store opaque types wider 4183 // than 128-bits 4184 case 'n': // valid address for Neon doubleword vector load/store 4185 case 'm': // valid address for Neon element and structure load/store 4186 case 's': // valid address for non-offset loads/stores of quad-word 4187 // values in four ARM registers 4188 Info.setAllowsMemory(); 4189 Name++; 4190 return true; 4191 } 4192 } 4193 return false; 4194 } 4195 std::string convertConstraint(const char *&Constraint) const override { 4196 std::string R; 4197 switch (*Constraint) { 4198 case 'U': // Two-character constraint; add "^" hint for later parsing. 4199 R = std::string("^") + std::string(Constraint, 2); 4200 Constraint++; 4201 break; 4202 case 'p': // 'p' should be translated to 'r' by default. 4203 R = std::string("r"); 4204 break; 4205 default: 4206 return std::string(1, *Constraint); 4207 } 4208 return R; 4209 } 4210 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4211 unsigned Size) const override { 4212 bool isOutput = (Constraint[0] == '='); 4213 bool isInOut = (Constraint[0] == '+'); 4214 4215 // Strip off constraint modifiers. 4216 while (Constraint[0] == '=' || 4217 Constraint[0] == '+' || 4218 Constraint[0] == '&') 4219 Constraint = Constraint.substr(1); 4220 4221 switch (Constraint[0]) { 4222 default: break; 4223 case 'r': { 4224 switch (Modifier) { 4225 default: 4226 return (isInOut || isOutput || Size <= 64); 4227 case 'q': 4228 // A register of size 32 cannot fit a vector type. 4229 return false; 4230 } 4231 } 4232 } 4233 4234 return true; 4235 } 4236 const char *getClobbers() const override { 4237 // FIXME: Is this really right? 4238 return ""; 4239 } 4240 4241 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4242 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4243 } 4244 4245 int getEHDataRegisterNumber(unsigned RegNo) const override { 4246 if (RegNo == 0) return 0; 4247 if (RegNo == 1) return 1; 4248 return -1; 4249 } 4250 }; 4251 4252 bool ARMTargetInfo::setFPMath(StringRef Name) { 4253 if (Name == "neon") { 4254 FPMath = FP_Neon; 4255 return true; 4256 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4257 Name == "vfp4") { 4258 FPMath = FP_VFP; 4259 return true; 4260 } 4261 return false; 4262 } 4263 4264 const char * const ARMTargetInfo::GCCRegNames[] = { 4265 // Integer registers 4266 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4267 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4268 4269 // Float registers 4270 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4271 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4272 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4273 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4274 4275 // Double registers 4276 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4277 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4278 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4279 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4280 4281 // Quad registers 4282 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4283 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4284 }; 4285 4286 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4287 unsigned &NumNames) const { 4288 Names = GCCRegNames; 4289 NumNames = llvm::array_lengthof(GCCRegNames); 4290 } 4291 4292 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4293 { { "a1" }, "r0" }, 4294 { { "a2" }, "r1" }, 4295 { { "a3" }, "r2" }, 4296 { { "a4" }, "r3" }, 4297 { { "v1" }, "r4" }, 4298 { { "v2" }, "r5" }, 4299 { { "v3" }, "r6" }, 4300 { { "v4" }, "r7" }, 4301 { { "v5" }, "r8" }, 4302 { { "v6", "rfp" }, "r9" }, 4303 { { "sl" }, "r10" }, 4304 { { "fp" }, "r11" }, 4305 { { "ip" }, "r12" }, 4306 { { "r13" }, "sp" }, 4307 { { "r14" }, "lr" }, 4308 { { "r15" }, "pc" }, 4309 // The S, D and Q registers overlap, but aren't really aliases; we 4310 // don't want to substitute one of these for a different-sized one. 4311 }; 4312 4313 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4314 unsigned &NumAliases) const { 4315 Aliases = GCCRegAliases; 4316 NumAliases = llvm::array_lengthof(GCCRegAliases); 4317 } 4318 4319 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4320 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4321 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4322 ALL_LANGUAGES }, 4323 #define GET_NEON_BUILTINS 4324 #include "clang/Basic/arm_neon.inc" 4325 #undef GET_NEON_BUILTINS 4326 4327 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4328 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4329 ALL_LANGUAGES }, 4330 #include "clang/Basic/BuiltinsARM.def" 4331 }; 4332 4333 class ARMleTargetInfo : public ARMTargetInfo { 4334 public: 4335 ARMleTargetInfo(const llvm::Triple &Triple) 4336 : ARMTargetInfo(Triple, false) { } 4337 virtual void getTargetDefines(const LangOptions &Opts, 4338 MacroBuilder &Builder) const { 4339 Builder.defineMacro("__ARMEL__"); 4340 ARMTargetInfo::getTargetDefines(Opts, Builder); 4341 } 4342 }; 4343 4344 class ARMbeTargetInfo : public ARMTargetInfo { 4345 public: 4346 ARMbeTargetInfo(const llvm::Triple &Triple) 4347 : ARMTargetInfo(Triple, true) { } 4348 virtual void getTargetDefines(const LangOptions &Opts, 4349 MacroBuilder &Builder) const { 4350 Builder.defineMacro("__ARMEB__"); 4351 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4352 ARMTargetInfo::getTargetDefines(Opts, Builder); 4353 } 4354 }; 4355 } // end anonymous namespace. 4356 4357 namespace { 4358 class DarwinARMTargetInfo : 4359 public DarwinTargetInfo<ARMleTargetInfo> { 4360 protected: 4361 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4362 MacroBuilder &Builder) const override { 4363 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4364 } 4365 4366 public: 4367 DarwinARMTargetInfo(const llvm::Triple &Triple) 4368 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4369 HasAlignMac68kSupport = true; 4370 // iOS always has 64-bit atomic instructions. 4371 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4372 MaxAtomicInlineWidth = 64; 4373 4374 // Darwin on iOS uses a variant of the ARM C++ ABI. 4375 TheCXXABI.set(TargetCXXABI::iOS); 4376 } 4377 }; 4378 } // end anonymous namespace. 4379 4380 4381 namespace { 4382 // Hexagon abstract base class 4383 class HexagonTargetInfo : public TargetInfo { 4384 static const Builtin::Info BuiltinInfo[]; 4385 static const char * const GCCRegNames[]; 4386 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4387 std::string CPU; 4388 public: 4389 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4390 BigEndian = false; 4391 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4392 4393 // {} in inline assembly are packet specifiers, not assembly variant 4394 // specifiers. 4395 NoAsmVariants = true; 4396 } 4397 4398 void getTargetBuiltins(const Builtin::Info *&Records, 4399 unsigned &NumRecords) const override { 4400 Records = BuiltinInfo; 4401 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4402 } 4403 4404 bool validateAsmConstraint(const char *&Name, 4405 TargetInfo::ConstraintInfo &Info) const override { 4406 return true; 4407 } 4408 4409 void getTargetDefines(const LangOptions &Opts, 4410 MacroBuilder &Builder) const override; 4411 4412 bool hasFeature(StringRef Feature) const override { 4413 return Feature == "hexagon"; 4414 } 4415 4416 BuiltinVaListKind getBuiltinVaListKind() const override { 4417 return TargetInfo::CharPtrBuiltinVaList; 4418 } 4419 void getGCCRegNames(const char * const *&Names, 4420 unsigned &NumNames) const override; 4421 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4422 unsigned &NumAliases) const override; 4423 const char *getClobbers() const override { 4424 return ""; 4425 } 4426 4427 static const char *getHexagonCPUSuffix(StringRef Name) { 4428 return llvm::StringSwitch<const char*>(Name) 4429 .Case("hexagonv4", "4") 4430 .Case("hexagonv5", "5") 4431 .Default(0); 4432 } 4433 4434 bool setCPU(const std::string &Name) override { 4435 if (!getHexagonCPUSuffix(Name)) 4436 return false; 4437 4438 CPU = Name; 4439 return true; 4440 } 4441 }; 4442 4443 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4444 MacroBuilder &Builder) const { 4445 Builder.defineMacro("qdsp6"); 4446 Builder.defineMacro("__qdsp6", "1"); 4447 Builder.defineMacro("__qdsp6__", "1"); 4448 4449 Builder.defineMacro("hexagon"); 4450 Builder.defineMacro("__hexagon", "1"); 4451 Builder.defineMacro("__hexagon__", "1"); 4452 4453 if(CPU == "hexagonv1") { 4454 Builder.defineMacro("__HEXAGON_V1__"); 4455 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4456 if(Opts.HexagonQdsp6Compat) { 4457 Builder.defineMacro("__QDSP6_V1__"); 4458 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4459 } 4460 } 4461 else if(CPU == "hexagonv2") { 4462 Builder.defineMacro("__HEXAGON_V2__"); 4463 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4464 if(Opts.HexagonQdsp6Compat) { 4465 Builder.defineMacro("__QDSP6_V2__"); 4466 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4467 } 4468 } 4469 else if(CPU == "hexagonv3") { 4470 Builder.defineMacro("__HEXAGON_V3__"); 4471 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4472 if(Opts.HexagonQdsp6Compat) { 4473 Builder.defineMacro("__QDSP6_V3__"); 4474 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4475 } 4476 } 4477 else if(CPU == "hexagonv4") { 4478 Builder.defineMacro("__HEXAGON_V4__"); 4479 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4480 if(Opts.HexagonQdsp6Compat) { 4481 Builder.defineMacro("__QDSP6_V4__"); 4482 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4483 } 4484 } 4485 else if(CPU == "hexagonv5") { 4486 Builder.defineMacro("__HEXAGON_V5__"); 4487 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4488 if(Opts.HexagonQdsp6Compat) { 4489 Builder.defineMacro("__QDSP6_V5__"); 4490 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4491 } 4492 } 4493 } 4494 4495 const char * const HexagonTargetInfo::GCCRegNames[] = { 4496 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4497 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4498 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4499 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4500 "p0", "p1", "p2", "p3", 4501 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4502 }; 4503 4504 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4505 unsigned &NumNames) const { 4506 Names = GCCRegNames; 4507 NumNames = llvm::array_lengthof(GCCRegNames); 4508 } 4509 4510 4511 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4512 { { "sp" }, "r29" }, 4513 { { "fp" }, "r30" }, 4514 { { "lr" }, "r31" }, 4515 }; 4516 4517 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4518 unsigned &NumAliases) const { 4519 Aliases = GCCRegAliases; 4520 NumAliases = llvm::array_lengthof(GCCRegAliases); 4521 } 4522 4523 4524 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4525 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4526 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4527 ALL_LANGUAGES }, 4528 #include "clang/Basic/BuiltinsHexagon.def" 4529 }; 4530 } 4531 4532 4533 namespace { 4534 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4535 class SparcTargetInfo : public TargetInfo { 4536 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4537 static const char * const GCCRegNames[]; 4538 bool SoftFloat; 4539 public: 4540 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4541 4542 bool handleTargetFeatures(std::vector<std::string> &Features, 4543 DiagnosticsEngine &Diags) override { 4544 SoftFloat = false; 4545 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4546 if (Features[i] == "+soft-float") 4547 SoftFloat = true; 4548 return true; 4549 } 4550 void getTargetDefines(const LangOptions &Opts, 4551 MacroBuilder &Builder) const override { 4552 DefineStd(Builder, "sparc", Opts); 4553 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4554 4555 if (SoftFloat) 4556 Builder.defineMacro("SOFT_FLOAT", "1"); 4557 } 4558 4559 bool hasFeature(StringRef Feature) const override { 4560 return llvm::StringSwitch<bool>(Feature) 4561 .Case("softfloat", SoftFloat) 4562 .Case("sparc", true) 4563 .Default(false); 4564 } 4565 4566 void getTargetBuiltins(const Builtin::Info *&Records, 4567 unsigned &NumRecords) const override { 4568 // FIXME: Implement! 4569 } 4570 BuiltinVaListKind getBuiltinVaListKind() const override { 4571 return TargetInfo::VoidPtrBuiltinVaList; 4572 } 4573 void getGCCRegNames(const char * const *&Names, 4574 unsigned &NumNames) const override; 4575 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4576 unsigned &NumAliases) const override; 4577 bool validateAsmConstraint(const char *&Name, 4578 TargetInfo::ConstraintInfo &info) const override { 4579 // FIXME: Implement! 4580 return false; 4581 } 4582 const char *getClobbers() const override { 4583 // FIXME: Implement! 4584 return ""; 4585 } 4586 }; 4587 4588 const char * const SparcTargetInfo::GCCRegNames[] = { 4589 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4590 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4591 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4592 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4593 }; 4594 4595 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4596 unsigned &NumNames) const { 4597 Names = GCCRegNames; 4598 NumNames = llvm::array_lengthof(GCCRegNames); 4599 } 4600 4601 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4602 { { "g0" }, "r0" }, 4603 { { "g1" }, "r1" }, 4604 { { "g2" }, "r2" }, 4605 { { "g3" }, "r3" }, 4606 { { "g4" }, "r4" }, 4607 { { "g5" }, "r5" }, 4608 { { "g6" }, "r6" }, 4609 { { "g7" }, "r7" }, 4610 { { "o0" }, "r8" }, 4611 { { "o1" }, "r9" }, 4612 { { "o2" }, "r10" }, 4613 { { "o3" }, "r11" }, 4614 { { "o4" }, "r12" }, 4615 { { "o5" }, "r13" }, 4616 { { "o6", "sp" }, "r14" }, 4617 { { "o7" }, "r15" }, 4618 { { "l0" }, "r16" }, 4619 { { "l1" }, "r17" }, 4620 { { "l2" }, "r18" }, 4621 { { "l3" }, "r19" }, 4622 { { "l4" }, "r20" }, 4623 { { "l5" }, "r21" }, 4624 { { "l6" }, "r22" }, 4625 { { "l7" }, "r23" }, 4626 { { "i0" }, "r24" }, 4627 { { "i1" }, "r25" }, 4628 { { "i2" }, "r26" }, 4629 { { "i3" }, "r27" }, 4630 { { "i4" }, "r28" }, 4631 { { "i5" }, "r29" }, 4632 { { "i6", "fp" }, "r30" }, 4633 { { "i7" }, "r31" }, 4634 }; 4635 4636 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4637 unsigned &NumAliases) const { 4638 Aliases = GCCRegAliases; 4639 NumAliases = llvm::array_lengthof(GCCRegAliases); 4640 } 4641 4642 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4643 class SparcV8TargetInfo : public SparcTargetInfo { 4644 public: 4645 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4646 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4647 } 4648 4649 void getTargetDefines(const LangOptions &Opts, 4650 MacroBuilder &Builder) const override { 4651 SparcTargetInfo::getTargetDefines(Opts, Builder); 4652 Builder.defineMacro("__sparcv8"); 4653 } 4654 }; 4655 4656 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4657 class SparcV9TargetInfo : public SparcTargetInfo { 4658 public: 4659 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4660 // FIXME: Support Sparc quad-precision long double? 4661 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4662 // This is an LP64 platform. 4663 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4664 4665 // OpenBSD uses long long for int64_t and intmax_t. 4666 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4667 IntMaxType = SignedLongLong; 4668 UIntMaxType = UnsignedLongLong; 4669 } else { 4670 IntMaxType = SignedLong; 4671 UIntMaxType = UnsignedLong; 4672 } 4673 Int64Type = IntMaxType; 4674 4675 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4676 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4677 LongDoubleWidth = 128; 4678 LongDoubleAlign = 128; 4679 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4680 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4681 } 4682 4683 void getTargetDefines(const LangOptions &Opts, 4684 MacroBuilder &Builder) const override { 4685 SparcTargetInfo::getTargetDefines(Opts, Builder); 4686 Builder.defineMacro("__sparcv9"); 4687 Builder.defineMacro("__arch64__"); 4688 // Solaris and its derivative AuroraUX don't need these variants, but the 4689 // BSDs do. 4690 if (getTriple().getOS() != llvm::Triple::Solaris && 4691 getTriple().getOS() != llvm::Triple::AuroraUX) { 4692 Builder.defineMacro("__sparc64__"); 4693 Builder.defineMacro("__sparc_v9__"); 4694 Builder.defineMacro("__sparcv9__"); 4695 } 4696 } 4697 4698 bool setCPU(const std::string &Name) override { 4699 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4700 .Case("v9", true) 4701 .Case("ultrasparc", true) 4702 .Case("ultrasparc3", true) 4703 .Case("niagara", true) 4704 .Case("niagara2", true) 4705 .Case("niagara3", true) 4706 .Case("niagara4", true) 4707 .Default(false); 4708 4709 // No need to store the CPU yet. There aren't any CPU-specific 4710 // macros to define. 4711 return CPUKnown; 4712 } 4713 }; 4714 4715 } // end anonymous namespace. 4716 4717 namespace { 4718 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4719 public: 4720 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4721 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4722 SizeType = UnsignedInt; 4723 PtrDiffType = SignedInt; 4724 } 4725 }; 4726 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4727 public: 4728 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4729 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4730 SizeType = UnsignedInt; 4731 PtrDiffType = SignedInt; 4732 } 4733 }; 4734 } // end anonymous namespace. 4735 4736 namespace { 4737 class SystemZTargetInfo : public TargetInfo { 4738 static const char *const GCCRegNames[]; 4739 4740 public: 4741 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4742 TLSSupported = true; 4743 IntWidth = IntAlign = 32; 4744 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4745 PointerWidth = PointerAlign = 64; 4746 LongDoubleWidth = 128; 4747 LongDoubleAlign = 64; 4748 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4749 MinGlobalAlign = 16; 4750 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4751 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4752 } 4753 void getTargetDefines(const LangOptions &Opts, 4754 MacroBuilder &Builder) const override { 4755 Builder.defineMacro("__s390__"); 4756 Builder.defineMacro("__s390x__"); 4757 Builder.defineMacro("__zarch__"); 4758 Builder.defineMacro("__LONG_DOUBLE_128__"); 4759 } 4760 void getTargetBuiltins(const Builtin::Info *&Records, 4761 unsigned &NumRecords) const override { 4762 // FIXME: Implement. 4763 Records = 0; 4764 NumRecords = 0; 4765 } 4766 4767 void getGCCRegNames(const char *const *&Names, 4768 unsigned &NumNames) const override; 4769 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4770 unsigned &NumAliases) const override { 4771 // No aliases. 4772 Aliases = 0; 4773 NumAliases = 0; 4774 } 4775 bool validateAsmConstraint(const char *&Name, 4776 TargetInfo::ConstraintInfo &info) const override; 4777 const char *getClobbers() const override { 4778 // FIXME: Is this really right? 4779 return ""; 4780 } 4781 BuiltinVaListKind getBuiltinVaListKind() const override { 4782 return TargetInfo::SystemZBuiltinVaList; 4783 } 4784 bool setCPU(const std::string &Name) override { 4785 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4786 .Case("z10", true) 4787 .Case("z196", true) 4788 .Case("zEC12", true) 4789 .Default(false); 4790 4791 // No need to store the CPU yet. There aren't any CPU-specific 4792 // macros to define. 4793 return CPUKnown; 4794 } 4795 }; 4796 4797 const char *const SystemZTargetInfo::GCCRegNames[] = { 4798 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4799 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4800 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4801 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4802 }; 4803 4804 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4805 unsigned &NumNames) const { 4806 Names = GCCRegNames; 4807 NumNames = llvm::array_lengthof(GCCRegNames); 4808 } 4809 4810 bool SystemZTargetInfo:: 4811 validateAsmConstraint(const char *&Name, 4812 TargetInfo::ConstraintInfo &Info) const { 4813 switch (*Name) { 4814 default: 4815 return false; 4816 4817 case 'a': // Address register 4818 case 'd': // Data register (equivalent to 'r') 4819 case 'f': // Floating-point register 4820 Info.setAllowsRegister(); 4821 return true; 4822 4823 case 'I': // Unsigned 8-bit constant 4824 case 'J': // Unsigned 12-bit constant 4825 case 'K': // Signed 16-bit constant 4826 case 'L': // Signed 20-bit displacement (on all targets we support) 4827 case 'M': // 0x7fffffff 4828 return true; 4829 4830 case 'Q': // Memory with base and unsigned 12-bit displacement 4831 case 'R': // Likewise, plus an index 4832 case 'S': // Memory with base and signed 20-bit displacement 4833 case 'T': // Likewise, plus an index 4834 Info.setAllowsMemory(); 4835 return true; 4836 } 4837 } 4838 } 4839 4840 namespace { 4841 class MSP430TargetInfo : public TargetInfo { 4842 static const char * const GCCRegNames[]; 4843 public: 4844 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4845 BigEndian = false; 4846 TLSSupported = false; 4847 IntWidth = 16; IntAlign = 16; 4848 LongWidth = 32; LongLongWidth = 64; 4849 LongAlign = LongLongAlign = 16; 4850 PointerWidth = 16; PointerAlign = 16; 4851 SuitableAlign = 16; 4852 SizeType = UnsignedInt; 4853 IntMaxType = SignedLongLong; 4854 UIntMaxType = UnsignedLongLong; 4855 IntPtrType = SignedInt; 4856 PtrDiffType = SignedInt; 4857 SigAtomicType = SignedLong; 4858 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4859 } 4860 void getTargetDefines(const LangOptions &Opts, 4861 MacroBuilder &Builder) const override { 4862 Builder.defineMacro("MSP430"); 4863 Builder.defineMacro("__MSP430__"); 4864 // FIXME: defines for different 'flavours' of MCU 4865 } 4866 void getTargetBuiltins(const Builtin::Info *&Records, 4867 unsigned &NumRecords) const override { 4868 // FIXME: Implement. 4869 Records = 0; 4870 NumRecords = 0; 4871 } 4872 bool hasFeature(StringRef Feature) const override { 4873 return Feature == "msp430"; 4874 } 4875 void getGCCRegNames(const char * const *&Names, 4876 unsigned &NumNames) const override; 4877 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4878 unsigned &NumAliases) const override { 4879 // No aliases. 4880 Aliases = 0; 4881 NumAliases = 0; 4882 } 4883 bool validateAsmConstraint(const char *&Name, 4884 TargetInfo::ConstraintInfo &info) const override { 4885 // No target constraints for now. 4886 return false; 4887 } 4888 const char *getClobbers() const override { 4889 // FIXME: Is this really right? 4890 return ""; 4891 } 4892 BuiltinVaListKind getBuiltinVaListKind() const override { 4893 // FIXME: implement 4894 return TargetInfo::CharPtrBuiltinVaList; 4895 } 4896 }; 4897 4898 const char * const MSP430TargetInfo::GCCRegNames[] = { 4899 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4900 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4901 }; 4902 4903 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4904 unsigned &NumNames) const { 4905 Names = GCCRegNames; 4906 NumNames = llvm::array_lengthof(GCCRegNames); 4907 } 4908 } 4909 4910 namespace { 4911 4912 // LLVM and Clang cannot be used directly to output native binaries for 4913 // target, but is used to compile C code to llvm bitcode with correct 4914 // type and alignment information. 4915 // 4916 // TCE uses the llvm bitcode as input and uses it for generating customized 4917 // target processor and program binary. TCE co-design environment is 4918 // publicly available in http://tce.cs.tut.fi 4919 4920 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4921 3, // opencl_global 4922 4, // opencl_local 4923 5, // opencl_constant 4924 0, // cuda_device 4925 0, // cuda_constant 4926 0 // cuda_shared 4927 }; 4928 4929 class TCETargetInfo : public TargetInfo{ 4930 public: 4931 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4932 TLSSupported = false; 4933 IntWidth = 32; 4934 LongWidth = LongLongWidth = 32; 4935 PointerWidth = 32; 4936 IntAlign = 32; 4937 LongAlign = LongLongAlign = 32; 4938 PointerAlign = 32; 4939 SuitableAlign = 32; 4940 SizeType = UnsignedInt; 4941 IntMaxType = SignedLong; 4942 UIntMaxType = UnsignedLong; 4943 IntPtrType = SignedInt; 4944 PtrDiffType = SignedInt; 4945 FloatWidth = 32; 4946 FloatAlign = 32; 4947 DoubleWidth = 32; 4948 DoubleAlign = 32; 4949 LongDoubleWidth = 32; 4950 LongDoubleAlign = 32; 4951 FloatFormat = &llvm::APFloat::IEEEsingle; 4952 DoubleFormat = &llvm::APFloat::IEEEsingle; 4953 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4954 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4955 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4956 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4957 UseAddrSpaceMapMangling = true; 4958 } 4959 4960 void getTargetDefines(const LangOptions &Opts, 4961 MacroBuilder &Builder) const override { 4962 DefineStd(Builder, "tce", Opts); 4963 Builder.defineMacro("__TCE__"); 4964 Builder.defineMacro("__TCE_V1__"); 4965 } 4966 bool hasFeature(StringRef Feature) const override { 4967 return Feature == "tce"; 4968 } 4969 4970 void getTargetBuiltins(const Builtin::Info *&Records, 4971 unsigned &NumRecords) const override {} 4972 const char *getClobbers() const override { 4973 return ""; 4974 } 4975 BuiltinVaListKind getBuiltinVaListKind() const override { 4976 return TargetInfo::VoidPtrBuiltinVaList; 4977 } 4978 void getGCCRegNames(const char * const *&Names, 4979 unsigned &NumNames) const override {} 4980 bool validateAsmConstraint(const char *&Name, 4981 TargetInfo::ConstraintInfo &info) const override{ 4982 return true; 4983 } 4984 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4985 unsigned &NumAliases) const override {} 4986 }; 4987 } 4988 4989 namespace { 4990 class MipsTargetInfoBase : public TargetInfo { 4991 virtual void setDescriptionString() = 0; 4992 4993 static const Builtin::Info BuiltinInfo[]; 4994 std::string CPU; 4995 bool IsMips16; 4996 bool IsMicromips; 4997 bool IsNan2008; 4998 bool IsSingleFloat; 4999 enum MipsFloatABI { 5000 HardFloat, SoftFloat 5001 } FloatABI; 5002 enum DspRevEnum { 5003 NoDSP, DSP1, DSP2 5004 } DspRev; 5005 bool HasMSA; 5006 5007 protected: 5008 bool HasFP64; 5009 std::string ABI; 5010 5011 public: 5012 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5013 const std::string &CPUStr) 5014 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5015 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5016 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5017 5018 const char *getABI() const override { return ABI.c_str(); } 5019 bool setABI(const std::string &Name) override = 0; 5020 bool setCPU(const std::string &Name) override { 5021 CPU = Name; 5022 return true; 5023 } 5024 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5025 // The backend enables certain ABI's by default according to the 5026 // architecture. 5027 // Disable both possible defaults so that we don't end up with multiple 5028 // ABI's selected and trigger an assertion. 5029 Features["o32"] = false; 5030 Features["n64"] = false; 5031 5032 Features[ABI] = true; 5033 Features[CPU] = true; 5034 } 5035 5036 void getTargetDefines(const LangOptions &Opts, 5037 MacroBuilder &Builder) const override { 5038 Builder.defineMacro("__mips__"); 5039 Builder.defineMacro("_mips"); 5040 if (Opts.GNUMode) 5041 Builder.defineMacro("mips"); 5042 5043 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5044 5045 switch (FloatABI) { 5046 case HardFloat: 5047 Builder.defineMacro("__mips_hard_float", Twine(1)); 5048 break; 5049 case SoftFloat: 5050 Builder.defineMacro("__mips_soft_float", Twine(1)); 5051 break; 5052 } 5053 5054 if (IsSingleFloat) 5055 Builder.defineMacro("__mips_single_float", Twine(1)); 5056 5057 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5058 Builder.defineMacro("_MIPS_FPSET", 5059 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5060 5061 if (IsMips16) 5062 Builder.defineMacro("__mips16", Twine(1)); 5063 5064 if (IsMicromips) 5065 Builder.defineMacro("__mips_micromips", Twine(1)); 5066 5067 if (IsNan2008) 5068 Builder.defineMacro("__mips_nan2008", Twine(1)); 5069 5070 switch (DspRev) { 5071 default: 5072 break; 5073 case DSP1: 5074 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5075 Builder.defineMacro("__mips_dsp", Twine(1)); 5076 break; 5077 case DSP2: 5078 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5079 Builder.defineMacro("__mips_dspr2", Twine(1)); 5080 Builder.defineMacro("__mips_dsp", Twine(1)); 5081 break; 5082 } 5083 5084 if (HasMSA) 5085 Builder.defineMacro("__mips_msa", Twine(1)); 5086 5087 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5088 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5089 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5090 5091 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5092 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5093 } 5094 5095 void getTargetBuiltins(const Builtin::Info *&Records, 5096 unsigned &NumRecords) const override { 5097 Records = BuiltinInfo; 5098 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5099 } 5100 bool hasFeature(StringRef Feature) const override { 5101 return llvm::StringSwitch<bool>(Feature) 5102 .Case("mips", true) 5103 .Case("fp64", HasFP64) 5104 .Default(false); 5105 } 5106 BuiltinVaListKind getBuiltinVaListKind() const override { 5107 return TargetInfo::VoidPtrBuiltinVaList; 5108 } 5109 void getGCCRegNames(const char * const *&Names, 5110 unsigned &NumNames) const override { 5111 static const char *const GCCRegNames[] = { 5112 // CPU register names 5113 // Must match second column of GCCRegAliases 5114 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5115 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5116 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5117 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5118 // Floating point register names 5119 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5120 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5121 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5122 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5123 // Hi/lo and condition register names 5124 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5125 "$fcc5","$fcc6","$fcc7", 5126 // MSA register names 5127 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5128 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5129 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5130 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5131 // MSA control register names 5132 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5133 "$msarequest", "$msamap", "$msaunmap" 5134 }; 5135 Names = GCCRegNames; 5136 NumNames = llvm::array_lengthof(GCCRegNames); 5137 } 5138 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5139 unsigned &NumAliases) const override = 0; 5140 bool validateAsmConstraint(const char *&Name, 5141 TargetInfo::ConstraintInfo &Info) const override { 5142 switch (*Name) { 5143 default: 5144 return false; 5145 5146 case 'r': // CPU registers. 5147 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5148 case 'y': // Equivalent to "r", backwards compatibility only. 5149 case 'f': // floating-point registers. 5150 case 'c': // $25 for indirect jumps 5151 case 'l': // lo register 5152 case 'x': // hilo register pair 5153 Info.setAllowsRegister(); 5154 return true; 5155 case 'R': // An address that can be used in a non-macro load or store 5156 Info.setAllowsMemory(); 5157 return true; 5158 } 5159 } 5160 5161 const char *getClobbers() const override { 5162 // FIXME: Implement! 5163 return ""; 5164 } 5165 5166 bool handleTargetFeatures(std::vector<std::string> &Features, 5167 DiagnosticsEngine &Diags) override { 5168 IsMips16 = false; 5169 IsMicromips = false; 5170 IsNan2008 = false; 5171 IsSingleFloat = false; 5172 FloatABI = HardFloat; 5173 DspRev = NoDSP; 5174 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5175 5176 for (std::vector<std::string>::iterator it = Features.begin(), 5177 ie = Features.end(); it != ie; ++it) { 5178 if (*it == "+single-float") 5179 IsSingleFloat = true; 5180 else if (*it == "+soft-float") 5181 FloatABI = SoftFloat; 5182 else if (*it == "+mips16") 5183 IsMips16 = true; 5184 else if (*it == "+micromips") 5185 IsMicromips = true; 5186 else if (*it == "+dsp") 5187 DspRev = std::max(DspRev, DSP1); 5188 else if (*it == "+dspr2") 5189 DspRev = std::max(DspRev, DSP2); 5190 else if (*it == "+msa") 5191 HasMSA = true; 5192 else if (*it == "+fp64") 5193 HasFP64 = true; 5194 else if (*it == "-fp64") 5195 HasFP64 = false; 5196 else if (*it == "+nan2008") 5197 IsNan2008 = true; 5198 } 5199 5200 // Remove front-end specific options. 5201 std::vector<std::string>::iterator it = 5202 std::find(Features.begin(), Features.end(), "+soft-float"); 5203 if (it != Features.end()) 5204 Features.erase(it); 5205 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5206 if (it != Features.end()) 5207 Features.erase(it); 5208 5209 setDescriptionString(); 5210 5211 return true; 5212 } 5213 5214 int getEHDataRegisterNumber(unsigned RegNo) const override { 5215 if (RegNo == 0) return 4; 5216 if (RegNo == 1) return 5; 5217 return -1; 5218 } 5219 }; 5220 5221 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5222 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5223 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5224 ALL_LANGUAGES }, 5225 #include "clang/Basic/BuiltinsMips.def" 5226 }; 5227 5228 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5229 public: 5230 Mips32TargetInfoBase(const llvm::Triple &Triple) 5231 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5232 SizeType = UnsignedInt; 5233 PtrDiffType = SignedInt; 5234 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5235 } 5236 bool setABI(const std::string &Name) override { 5237 if ((Name == "o32") || (Name == "eabi")) { 5238 ABI = Name; 5239 return true; 5240 } else if (Name == "32") { 5241 ABI = "o32"; 5242 return true; 5243 } else 5244 return false; 5245 } 5246 void getTargetDefines(const LangOptions &Opts, 5247 MacroBuilder &Builder) const override { 5248 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5249 5250 Builder.defineMacro("__mips", "32"); 5251 5252 if (ABI == "o32") { 5253 Builder.defineMacro("__mips_o32"); 5254 Builder.defineMacro("_ABIO32", "1"); 5255 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5256 } 5257 else if (ABI == "eabi") 5258 Builder.defineMacro("__mips_eabi"); 5259 else 5260 llvm_unreachable("Invalid ABI for Mips32."); 5261 } 5262 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5263 unsigned &NumAliases) const override { 5264 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5265 { { "at" }, "$1" }, 5266 { { "v0" }, "$2" }, 5267 { { "v1" }, "$3" }, 5268 { { "a0" }, "$4" }, 5269 { { "a1" }, "$5" }, 5270 { { "a2" }, "$6" }, 5271 { { "a3" }, "$7" }, 5272 { { "t0" }, "$8" }, 5273 { { "t1" }, "$9" }, 5274 { { "t2" }, "$10" }, 5275 { { "t3" }, "$11" }, 5276 { { "t4" }, "$12" }, 5277 { { "t5" }, "$13" }, 5278 { { "t6" }, "$14" }, 5279 { { "t7" }, "$15" }, 5280 { { "s0" }, "$16" }, 5281 { { "s1" }, "$17" }, 5282 { { "s2" }, "$18" }, 5283 { { "s3" }, "$19" }, 5284 { { "s4" }, "$20" }, 5285 { { "s5" }, "$21" }, 5286 { { "s6" }, "$22" }, 5287 { { "s7" }, "$23" }, 5288 { { "t8" }, "$24" }, 5289 { { "t9" }, "$25" }, 5290 { { "k0" }, "$26" }, 5291 { { "k1" }, "$27" }, 5292 { { "gp" }, "$28" }, 5293 { { "sp","$sp" }, "$29" }, 5294 { { "fp","$fp" }, "$30" }, 5295 { { "ra" }, "$31" } 5296 }; 5297 Aliases = GCCRegAliases; 5298 NumAliases = llvm::array_lengthof(GCCRegAliases); 5299 } 5300 }; 5301 5302 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5303 void setDescriptionString() override { 5304 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5305 } 5306 5307 public: 5308 Mips32EBTargetInfo(const llvm::Triple &Triple) 5309 : Mips32TargetInfoBase(Triple) { 5310 } 5311 void getTargetDefines(const LangOptions &Opts, 5312 MacroBuilder &Builder) const override { 5313 DefineStd(Builder, "MIPSEB", Opts); 5314 Builder.defineMacro("_MIPSEB"); 5315 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5316 } 5317 }; 5318 5319 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5320 void setDescriptionString() override { 5321 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5322 } 5323 5324 public: 5325 Mips32ELTargetInfo(const llvm::Triple &Triple) 5326 : Mips32TargetInfoBase(Triple) { 5327 BigEndian = false; 5328 } 5329 void getTargetDefines(const LangOptions &Opts, 5330 MacroBuilder &Builder) const override { 5331 DefineStd(Builder, "MIPSEL", Opts); 5332 Builder.defineMacro("_MIPSEL"); 5333 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5334 } 5335 }; 5336 5337 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5338 public: 5339 Mips64TargetInfoBase(const llvm::Triple &Triple) 5340 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5341 LongWidth = LongAlign = 64; 5342 PointerWidth = PointerAlign = 64; 5343 LongDoubleWidth = LongDoubleAlign = 128; 5344 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5345 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5346 LongDoubleWidth = LongDoubleAlign = 64; 5347 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5348 } 5349 SuitableAlign = 128; 5350 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5351 } 5352 bool setABI(const std::string &Name) override { 5353 if (Name == "n32") { 5354 LongWidth = LongAlign = 32; 5355 PointerWidth = PointerAlign = 32; 5356 ABI = Name; 5357 return true; 5358 } else if (Name == "n64") { 5359 ABI = Name; 5360 return true; 5361 } else if (Name == "64") { 5362 ABI = "n64"; 5363 return true; 5364 } else 5365 return false; 5366 } 5367 void getTargetDefines(const LangOptions &Opts, 5368 MacroBuilder &Builder) const override { 5369 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5370 5371 Builder.defineMacro("__mips", "64"); 5372 Builder.defineMacro("__mips64"); 5373 Builder.defineMacro("__mips64__"); 5374 5375 if (ABI == "n32") { 5376 Builder.defineMacro("__mips_n32"); 5377 Builder.defineMacro("_ABIN32", "2"); 5378 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5379 } 5380 else if (ABI == "n64") { 5381 Builder.defineMacro("__mips_n64"); 5382 Builder.defineMacro("_ABI64", "3"); 5383 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5384 } 5385 else 5386 llvm_unreachable("Invalid ABI for Mips64."); 5387 } 5388 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5389 unsigned &NumAliases) const override { 5390 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5391 { { "at" }, "$1" }, 5392 { { "v0" }, "$2" }, 5393 { { "v1" }, "$3" }, 5394 { { "a0" }, "$4" }, 5395 { { "a1" }, "$5" }, 5396 { { "a2" }, "$6" }, 5397 { { "a3" }, "$7" }, 5398 { { "a4" }, "$8" }, 5399 { { "a5" }, "$9" }, 5400 { { "a6" }, "$10" }, 5401 { { "a7" }, "$11" }, 5402 { { "t0" }, "$12" }, 5403 { { "t1" }, "$13" }, 5404 { { "t2" }, "$14" }, 5405 { { "t3" }, "$15" }, 5406 { { "s0" }, "$16" }, 5407 { { "s1" }, "$17" }, 5408 { { "s2" }, "$18" }, 5409 { { "s3" }, "$19" }, 5410 { { "s4" }, "$20" }, 5411 { { "s5" }, "$21" }, 5412 { { "s6" }, "$22" }, 5413 { { "s7" }, "$23" }, 5414 { { "t8" }, "$24" }, 5415 { { "t9" }, "$25" }, 5416 { { "k0" }, "$26" }, 5417 { { "k1" }, "$27" }, 5418 { { "gp" }, "$28" }, 5419 { { "sp","$sp" }, "$29" }, 5420 { { "fp","$fp" }, "$30" }, 5421 { { "ra" }, "$31" } 5422 }; 5423 Aliases = GCCRegAliases; 5424 NumAliases = llvm::array_lengthof(GCCRegAliases); 5425 } 5426 }; 5427 5428 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5429 void setDescriptionString() override { 5430 if (ABI == "n32") 5431 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5432 else 5433 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5434 5435 } 5436 5437 public: 5438 Mips64EBTargetInfo(const llvm::Triple &Triple) 5439 : Mips64TargetInfoBase(Triple) {} 5440 void getTargetDefines(const LangOptions &Opts, 5441 MacroBuilder &Builder) const override { 5442 DefineStd(Builder, "MIPSEB", Opts); 5443 Builder.defineMacro("_MIPSEB"); 5444 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5445 } 5446 }; 5447 5448 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5449 void setDescriptionString() override { 5450 if (ABI == "n32") 5451 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5452 else 5453 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5454 } 5455 public: 5456 Mips64ELTargetInfo(const llvm::Triple &Triple) 5457 : Mips64TargetInfoBase(Triple) { 5458 // Default ABI is n64. 5459 BigEndian = false; 5460 } 5461 void getTargetDefines(const LangOptions &Opts, 5462 MacroBuilder &Builder) const override { 5463 DefineStd(Builder, "MIPSEL", Opts); 5464 Builder.defineMacro("_MIPSEL"); 5465 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5466 } 5467 }; 5468 } // end anonymous namespace. 5469 5470 namespace { 5471 class PNaClTargetInfo : public TargetInfo { 5472 public: 5473 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5474 BigEndian = false; 5475 this->UserLabelPrefix = ""; 5476 this->LongAlign = 32; 5477 this->LongWidth = 32; 5478 this->PointerAlign = 32; 5479 this->PointerWidth = 32; 5480 this->IntMaxType = TargetInfo::SignedLongLong; 5481 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5482 this->Int64Type = TargetInfo::SignedLongLong; 5483 this->DoubleAlign = 64; 5484 this->LongDoubleWidth = 64; 5485 this->LongDoubleAlign = 64; 5486 this->SizeType = TargetInfo::UnsignedInt; 5487 this->PtrDiffType = TargetInfo::SignedInt; 5488 this->IntPtrType = TargetInfo::SignedInt; 5489 this->RegParmMax = 0; // Disallow regparm 5490 } 5491 5492 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5493 } 5494 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5495 Builder.defineMacro("__le32__"); 5496 Builder.defineMacro("__pnacl__"); 5497 } 5498 void getTargetDefines(const LangOptions &Opts, 5499 MacroBuilder &Builder) const override { 5500 getArchDefines(Opts, Builder); 5501 } 5502 bool hasFeature(StringRef Feature) const override { 5503 return Feature == "pnacl"; 5504 } 5505 void getTargetBuiltins(const Builtin::Info *&Records, 5506 unsigned &NumRecords) const override { 5507 } 5508 BuiltinVaListKind getBuiltinVaListKind() const override { 5509 return TargetInfo::PNaClABIBuiltinVaList; 5510 } 5511 void getGCCRegNames(const char * const *&Names, 5512 unsigned &NumNames) const override; 5513 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5514 unsigned &NumAliases) const override; 5515 bool validateAsmConstraint(const char *&Name, 5516 TargetInfo::ConstraintInfo &Info) const override { 5517 return false; 5518 } 5519 5520 const char *getClobbers() const override { 5521 return ""; 5522 } 5523 }; 5524 5525 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5526 unsigned &NumNames) const { 5527 Names = NULL; 5528 NumNames = 0; 5529 } 5530 5531 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5532 unsigned &NumAliases) const { 5533 Aliases = NULL; 5534 NumAliases = 0; 5535 } 5536 } // end anonymous namespace. 5537 5538 namespace { 5539 static const unsigned SPIRAddrSpaceMap[] = { 5540 1, // opencl_global 5541 3, // opencl_local 5542 2, // opencl_constant 5543 0, // cuda_device 5544 0, // cuda_constant 5545 0 // cuda_shared 5546 }; 5547 class SPIRTargetInfo : public TargetInfo { 5548 public: 5549 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5550 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5551 "SPIR target must use unknown OS"); 5552 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5553 "SPIR target must use unknown environment type"); 5554 BigEndian = false; 5555 TLSSupported = false; 5556 LongWidth = LongAlign = 64; 5557 AddrSpaceMap = &SPIRAddrSpaceMap; 5558 UseAddrSpaceMapMangling = true; 5559 // Define available target features 5560 // These must be defined in sorted order! 5561 NoAsmVariants = true; 5562 } 5563 void getTargetDefines(const LangOptions &Opts, 5564 MacroBuilder &Builder) const override { 5565 DefineStd(Builder, "SPIR", Opts); 5566 } 5567 bool hasFeature(StringRef Feature) const override { 5568 return Feature == "spir"; 5569 } 5570 5571 void getTargetBuiltins(const Builtin::Info *&Records, 5572 unsigned &NumRecords) const override {} 5573 const char *getClobbers() const override { 5574 return ""; 5575 } 5576 void getGCCRegNames(const char * const *&Names, 5577 unsigned &NumNames) const override {} 5578 bool validateAsmConstraint(const char *&Name, 5579 TargetInfo::ConstraintInfo &info) const override { 5580 return true; 5581 } 5582 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5583 unsigned &NumAliases) const override {} 5584 BuiltinVaListKind getBuiltinVaListKind() const override { 5585 return TargetInfo::VoidPtrBuiltinVaList; 5586 } 5587 }; 5588 5589 5590 class SPIR32TargetInfo : public SPIRTargetInfo { 5591 public: 5592 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5593 PointerWidth = PointerAlign = 32; 5594 SizeType = TargetInfo::UnsignedInt; 5595 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5596 DescriptionString 5597 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5598 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5599 } 5600 void getTargetDefines(const LangOptions &Opts, 5601 MacroBuilder &Builder) const override { 5602 DefineStd(Builder, "SPIR32", Opts); 5603 } 5604 }; 5605 5606 class SPIR64TargetInfo : public SPIRTargetInfo { 5607 public: 5608 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5609 PointerWidth = PointerAlign = 64; 5610 SizeType = TargetInfo::UnsignedLong; 5611 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5612 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5613 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5614 } 5615 void getTargetDefines(const LangOptions &Opts, 5616 MacroBuilder &Builder) const override { 5617 DefineStd(Builder, "SPIR64", Opts); 5618 } 5619 }; 5620 } 5621 5622 namespace { 5623 class XCoreTargetInfo : public TargetInfo { 5624 static const Builtin::Info BuiltinInfo[]; 5625 public: 5626 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5627 BigEndian = false; 5628 NoAsmVariants = true; 5629 LongLongAlign = 32; 5630 SuitableAlign = 32; 5631 DoubleAlign = LongDoubleAlign = 32; 5632 SizeType = UnsignedInt; 5633 PtrDiffType = SignedInt; 5634 IntPtrType = SignedInt; 5635 WCharType = UnsignedChar; 5636 WIntType = UnsignedInt; 5637 UseZeroLengthBitfieldAlignment = true; 5638 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5639 "-f64:32-a:0:32-n32"; 5640 } 5641 void getTargetDefines(const LangOptions &Opts, 5642 MacroBuilder &Builder) const override { 5643 Builder.defineMacro("__XS1B__"); 5644 } 5645 void getTargetBuiltins(const Builtin::Info *&Records, 5646 unsigned &NumRecords) const override { 5647 Records = BuiltinInfo; 5648 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5649 } 5650 BuiltinVaListKind getBuiltinVaListKind() const override { 5651 return TargetInfo::VoidPtrBuiltinVaList; 5652 } 5653 const char *getClobbers() const override { 5654 return ""; 5655 } 5656 void getGCCRegNames(const char * const *&Names, 5657 unsigned &NumNames) const override { 5658 static const char * const GCCRegNames[] = { 5659 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5660 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5661 }; 5662 Names = GCCRegNames; 5663 NumNames = llvm::array_lengthof(GCCRegNames); 5664 } 5665 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5666 unsigned &NumAliases) const override { 5667 Aliases = NULL; 5668 NumAliases = 0; 5669 } 5670 bool validateAsmConstraint(const char *&Name, 5671 TargetInfo::ConstraintInfo &Info) const override { 5672 return false; 5673 } 5674 int getEHDataRegisterNumber(unsigned RegNo) const override { 5675 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5676 return (RegNo < 2)? RegNo : -1; 5677 } 5678 }; 5679 5680 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5681 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5682 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5683 ALL_LANGUAGES }, 5684 #include "clang/Basic/BuiltinsXCore.def" 5685 }; 5686 } // end anonymous namespace. 5687 5688 5689 //===----------------------------------------------------------------------===// 5690 // Driver code 5691 //===----------------------------------------------------------------------===// 5692 5693 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5694 llvm::Triple::OSType os = Triple.getOS(); 5695 5696 switch (Triple.getArch()) { 5697 default: 5698 return NULL; 5699 5700 case llvm::Triple::xcore: 5701 return new XCoreTargetInfo(Triple); 5702 5703 case llvm::Triple::hexagon: 5704 return new HexagonTargetInfo(Triple); 5705 5706 case llvm::Triple::aarch64: 5707 switch (os) { 5708 case llvm::Triple::Linux: 5709 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 5710 case llvm::Triple::NetBSD: 5711 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 5712 default: 5713 return new AArch64leTargetInfo(Triple); 5714 } 5715 5716 case llvm::Triple::aarch64_be: 5717 switch (os) { 5718 case llvm::Triple::Linux: 5719 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 5720 case llvm::Triple::NetBSD: 5721 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 5722 default: 5723 return new AArch64beTargetInfo(Triple); 5724 } 5725 5726 case llvm::Triple::arm: 5727 case llvm::Triple::thumb: 5728 if (Triple.isOSBinFormatMachO()) 5729 return new DarwinARMTargetInfo(Triple); 5730 5731 switch (os) { 5732 case llvm::Triple::Linux: 5733 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 5734 case llvm::Triple::FreeBSD: 5735 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 5736 case llvm::Triple::NetBSD: 5737 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 5738 case llvm::Triple::OpenBSD: 5739 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 5740 case llvm::Triple::Bitrig: 5741 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 5742 case llvm::Triple::RTEMS: 5743 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 5744 case llvm::Triple::NaCl: 5745 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 5746 default: 5747 return new ARMleTargetInfo(Triple); 5748 } 5749 5750 case llvm::Triple::armeb: 5751 case llvm::Triple::thumbeb: 5752 if (Triple.isOSDarwin()) 5753 return new DarwinARMTargetInfo(Triple); 5754 5755 switch (os) { 5756 case llvm::Triple::Linux: 5757 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 5758 case llvm::Triple::FreeBSD: 5759 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 5760 case llvm::Triple::NetBSD: 5761 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 5762 case llvm::Triple::OpenBSD: 5763 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 5764 case llvm::Triple::Bitrig: 5765 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 5766 case llvm::Triple::RTEMS: 5767 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 5768 case llvm::Triple::NaCl: 5769 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 5770 default: 5771 return new ARMbeTargetInfo(Triple); 5772 } 5773 5774 case llvm::Triple::msp430: 5775 return new MSP430TargetInfo(Triple); 5776 5777 case llvm::Triple::mips: 5778 switch (os) { 5779 case llvm::Triple::Linux: 5780 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5781 case llvm::Triple::RTEMS: 5782 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5783 case llvm::Triple::FreeBSD: 5784 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5785 case llvm::Triple::NetBSD: 5786 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5787 default: 5788 return new Mips32EBTargetInfo(Triple); 5789 } 5790 5791 case llvm::Triple::mipsel: 5792 switch (os) { 5793 case llvm::Triple::Linux: 5794 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5795 case llvm::Triple::RTEMS: 5796 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5797 case llvm::Triple::FreeBSD: 5798 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5799 case llvm::Triple::NetBSD: 5800 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5801 case llvm::Triple::NaCl: 5802 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5803 default: 5804 return new Mips32ELTargetInfo(Triple); 5805 } 5806 5807 case llvm::Triple::mips64: 5808 switch (os) { 5809 case llvm::Triple::Linux: 5810 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5811 case llvm::Triple::RTEMS: 5812 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5813 case llvm::Triple::FreeBSD: 5814 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5815 case llvm::Triple::NetBSD: 5816 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5817 case llvm::Triple::OpenBSD: 5818 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5819 default: 5820 return new Mips64EBTargetInfo(Triple); 5821 } 5822 5823 case llvm::Triple::mips64el: 5824 switch (os) { 5825 case llvm::Triple::Linux: 5826 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5827 case llvm::Triple::RTEMS: 5828 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5829 case llvm::Triple::FreeBSD: 5830 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5831 case llvm::Triple::NetBSD: 5832 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5833 case llvm::Triple::OpenBSD: 5834 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5835 default: 5836 return new Mips64ELTargetInfo(Triple); 5837 } 5838 5839 case llvm::Triple::le32: 5840 switch (os) { 5841 case llvm::Triple::NaCl: 5842 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5843 default: 5844 return NULL; 5845 } 5846 5847 case llvm::Triple::ppc: 5848 if (Triple.isOSDarwin()) 5849 return new DarwinPPC32TargetInfo(Triple); 5850 switch (os) { 5851 case llvm::Triple::Linux: 5852 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5853 case llvm::Triple::FreeBSD: 5854 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5855 case llvm::Triple::NetBSD: 5856 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5857 case llvm::Triple::OpenBSD: 5858 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5859 case llvm::Triple::RTEMS: 5860 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5861 default: 5862 return new PPC32TargetInfo(Triple); 5863 } 5864 5865 case llvm::Triple::ppc64: 5866 if (Triple.isOSDarwin()) 5867 return new DarwinPPC64TargetInfo(Triple); 5868 switch (os) { 5869 case llvm::Triple::Linux: 5870 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5871 case llvm::Triple::Lv2: 5872 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5873 case llvm::Triple::FreeBSD: 5874 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5875 case llvm::Triple::NetBSD: 5876 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5877 default: 5878 return new PPC64TargetInfo(Triple); 5879 } 5880 5881 case llvm::Triple::ppc64le: 5882 switch (os) { 5883 case llvm::Triple::Linux: 5884 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5885 default: 5886 return new PPC64TargetInfo(Triple); 5887 } 5888 5889 case llvm::Triple::nvptx: 5890 return new NVPTX32TargetInfo(Triple); 5891 case llvm::Triple::nvptx64: 5892 return new NVPTX64TargetInfo(Triple); 5893 5894 case llvm::Triple::r600: 5895 return new R600TargetInfo(Triple); 5896 5897 case llvm::Triple::sparc: 5898 switch (os) { 5899 case llvm::Triple::Linux: 5900 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5901 case llvm::Triple::AuroraUX: 5902 return new AuroraUXSparcV8TargetInfo(Triple); 5903 case llvm::Triple::Solaris: 5904 return new SolarisSparcV8TargetInfo(Triple); 5905 case llvm::Triple::NetBSD: 5906 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5907 case llvm::Triple::OpenBSD: 5908 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5909 case llvm::Triple::RTEMS: 5910 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5911 default: 5912 return new SparcV8TargetInfo(Triple); 5913 } 5914 5915 case llvm::Triple::sparcv9: 5916 switch (os) { 5917 case llvm::Triple::Linux: 5918 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5919 case llvm::Triple::AuroraUX: 5920 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5921 case llvm::Triple::Solaris: 5922 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5923 case llvm::Triple::NetBSD: 5924 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5925 case llvm::Triple::OpenBSD: 5926 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5927 case llvm::Triple::FreeBSD: 5928 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5929 default: 5930 return new SparcV9TargetInfo(Triple); 5931 } 5932 5933 case llvm::Triple::systemz: 5934 switch (os) { 5935 case llvm::Triple::Linux: 5936 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5937 default: 5938 return new SystemZTargetInfo(Triple); 5939 } 5940 5941 case llvm::Triple::tce: 5942 return new TCETargetInfo(Triple); 5943 5944 case llvm::Triple::x86: 5945 if (Triple.isOSDarwin()) 5946 return new DarwinI386TargetInfo(Triple); 5947 5948 switch (os) { 5949 case llvm::Triple::AuroraUX: 5950 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5951 case llvm::Triple::Linux: 5952 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5953 case llvm::Triple::DragonFly: 5954 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5955 case llvm::Triple::NetBSD: 5956 return new NetBSDI386TargetInfo(Triple); 5957 case llvm::Triple::OpenBSD: 5958 return new OpenBSDI386TargetInfo(Triple); 5959 case llvm::Triple::Bitrig: 5960 return new BitrigI386TargetInfo(Triple); 5961 case llvm::Triple::FreeBSD: 5962 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5963 case llvm::Triple::KFreeBSD: 5964 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5965 case llvm::Triple::Minix: 5966 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5967 case llvm::Triple::Solaris: 5968 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5969 case llvm::Triple::Win32: { 5970 switch (Triple.getEnvironment()) { 5971 default: 5972 return new X86_32TargetInfo(Triple); 5973 case llvm::Triple::Cygnus: 5974 return new CygwinX86_32TargetInfo(Triple); 5975 case llvm::Triple::GNU: 5976 return new MinGWX86_32TargetInfo(Triple); 5977 case llvm::Triple::MSVC: 5978 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5979 } 5980 } 5981 case llvm::Triple::Haiku: 5982 return new HaikuX86_32TargetInfo(Triple); 5983 case llvm::Triple::RTEMS: 5984 return new RTEMSX86_32TargetInfo(Triple); 5985 case llvm::Triple::NaCl: 5986 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5987 default: 5988 return new X86_32TargetInfo(Triple); 5989 } 5990 5991 case llvm::Triple::x86_64: 5992 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 5993 return new DarwinX86_64TargetInfo(Triple); 5994 5995 switch (os) { 5996 case llvm::Triple::AuroraUX: 5997 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5998 case llvm::Triple::Linux: 5999 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6000 case llvm::Triple::DragonFly: 6001 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6002 case llvm::Triple::NetBSD: 6003 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6004 case llvm::Triple::OpenBSD: 6005 return new OpenBSDX86_64TargetInfo(Triple); 6006 case llvm::Triple::Bitrig: 6007 return new BitrigX86_64TargetInfo(Triple); 6008 case llvm::Triple::FreeBSD: 6009 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6010 case llvm::Triple::KFreeBSD: 6011 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6012 case llvm::Triple::Solaris: 6013 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6014 case llvm::Triple::Win32: { 6015 switch (Triple.getEnvironment()) { 6016 default: 6017 return new X86_64TargetInfo(Triple); 6018 case llvm::Triple::GNU: 6019 return new MinGWX86_64TargetInfo(Triple); 6020 case llvm::Triple::MSVC: 6021 return new VisualStudioWindowsX86_64TargetInfo(Triple); 6022 } 6023 } 6024 case llvm::Triple::NaCl: 6025 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6026 default: 6027 return new X86_64TargetInfo(Triple); 6028 } 6029 6030 case llvm::Triple::spir: { 6031 if (Triple.getOS() != llvm::Triple::UnknownOS || 6032 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6033 return NULL; 6034 return new SPIR32TargetInfo(Triple); 6035 } 6036 case llvm::Triple::spir64: { 6037 if (Triple.getOS() != llvm::Triple::UnknownOS || 6038 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6039 return NULL; 6040 return new SPIR64TargetInfo(Triple); 6041 } 6042 } 6043 } 6044 6045 /// CreateTargetInfo - Return the target info object for the specified target 6046 /// triple. 6047 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6048 TargetOptions *Opts) { 6049 llvm::Triple Triple(Opts->Triple); 6050 6051 // Construct the target 6052 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6053 if (!Target) { 6054 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6055 return 0; 6056 } 6057 Target->setTargetOpts(Opts); 6058 6059 // Set the target CPU if specified. 6060 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6061 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6062 return 0; 6063 } 6064 6065 // Set the target ABI if specified. 6066 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6067 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6068 return 0; 6069 } 6070 6071 // Set the fp math unit. 6072 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6073 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6074 return 0; 6075 } 6076 6077 // Compute the default target features, we need the target to handle this 6078 // because features may have dependencies on one another. 6079 llvm::StringMap<bool> Features; 6080 Target->getDefaultFeatures(Features); 6081 6082 // Apply the user specified deltas. 6083 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6084 I < N; ++I) { 6085 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6086 // Apply the feature via the target. 6087 bool Enabled = Name[0] == '+'; 6088 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6089 } 6090 6091 // Add the features to the compile options. 6092 // 6093 // FIXME: If we are completely confident that we have the right set, we only 6094 // need to pass the minuses. 6095 Opts->Features.clear(); 6096 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6097 ie = Features.end(); it != ie; ++it) 6098 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6099 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6100 return 0; 6101 6102 return Target.release(); 6103 } 6104