1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 69 const TargetOptions &Opts); 70 71 //===----------------------------------------------------------------------===// 72 // Defines specific to certain operating systems. 73 //===----------------------------------------------------------------------===// 74 75 namespace { 76 template<typename TgtInfo> 77 class OSTargetInfo : public TgtInfo { 78 protected: 79 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 80 MacroBuilder &Builder) const=0; 81 public: 82 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 83 : TgtInfo(Triple, Opts) {} 84 void getTargetDefines(const LangOptions &Opts, 85 MacroBuilder &Builder) const override { 86 TgtInfo::getTargetDefines(Opts, Builder); 87 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 88 } 89 90 }; 91 92 // CloudABI Target 93 template <typename Target> 94 class CloudABITargetInfo : public OSTargetInfo<Target> { 95 protected: 96 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 97 MacroBuilder &Builder) const override { 98 Builder.defineMacro("__CloudABI__"); 99 Builder.defineMacro("__ELF__"); 100 101 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 102 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 103 Builder.defineMacro("__STDC_UTF_16__"); 104 Builder.defineMacro("__STDC_UTF_32__"); 105 } 106 107 public: 108 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 109 : OSTargetInfo<Target>(Triple, Opts) {} 110 }; 111 112 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 113 const llvm::Triple &Triple, 114 StringRef &PlatformName, 115 VersionTuple &PlatformMinVersion) { 116 Builder.defineMacro("__APPLE_CC__", "6000"); 117 Builder.defineMacro("__APPLE__"); 118 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 119 // AddressSanitizer doesn't play well with source fortification, which is on 120 // by default on Darwin. 121 if (Opts.Sanitize.has(SanitizerKind::Address)) 122 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 123 124 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 125 if (!Opts.ObjC1) { 126 // __weak is always defined, for use in blocks and with objc pointers. 127 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 128 Builder.defineMacro("__strong", ""); 129 Builder.defineMacro("__unsafe_unretained", ""); 130 } 131 132 if (Opts.Static) 133 Builder.defineMacro("__STATIC__"); 134 else 135 Builder.defineMacro("__DYNAMIC__"); 136 137 if (Opts.POSIXThreads) 138 Builder.defineMacro("_REENTRANT"); 139 140 // Get the platform type and version number from the triple. 141 unsigned Maj, Min, Rev; 142 if (Triple.isMacOSX()) { 143 Triple.getMacOSXVersion(Maj, Min, Rev); 144 PlatformName = "macosx"; 145 } else { 146 Triple.getOSVersion(Maj, Min, Rev); 147 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 148 } 149 150 // If -target arch-pc-win32-macho option specified, we're 151 // generating code for Win32 ABI. No need to emit 152 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 153 if (PlatformName == "win32") { 154 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 155 return; 156 } 157 158 // Set the appropriate OS version define. 159 if (Triple.isiOS()) { 160 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[6]; 162 Str[0] = '0' + Maj; 163 Str[1] = '0' + (Min / 10); 164 Str[2] = '0' + (Min % 10); 165 Str[3] = '0' + (Rev / 10); 166 Str[4] = '0' + (Rev % 10); 167 Str[5] = '\0'; 168 if (Triple.isTvOS()) 169 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 170 else 171 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 172 Str); 173 174 } else if (Triple.isWatchOS()) { 175 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 176 char Str[6]; 177 Str[0] = '0' + Maj; 178 Str[1] = '0' + (Min / 10); 179 Str[2] = '0' + (Min % 10); 180 Str[3] = '0' + (Rev / 10); 181 Str[4] = '0' + (Rev % 10); 182 Str[5] = '\0'; 183 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 184 } else if (Triple.isMacOSX()) { 185 // Note that the Driver allows versions which aren't representable in the 186 // define (because we only get a single digit for the minor and micro 187 // revision numbers). So, we limit them to the maximum representable 188 // version. 189 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[7]; 191 if (Maj < 10 || (Maj == 10 && Min < 10)) { 192 Str[0] = '0' + (Maj / 10); 193 Str[1] = '0' + (Maj % 10); 194 Str[2] = '0' + std::min(Min, 9U); 195 Str[3] = '0' + std::min(Rev, 9U); 196 Str[4] = '\0'; 197 } else { 198 // Handle versions > 10.9. 199 Str[0] = '0' + (Maj / 10); 200 Str[1] = '0' + (Maj % 10); 201 Str[2] = '0' + (Min / 10); 202 Str[3] = '0' + (Min % 10); 203 Str[4] = '0' + (Rev / 10); 204 Str[5] = '0' + (Rev % 10); 205 Str[6] = '\0'; 206 } 207 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 208 } 209 210 // Tell users about the kernel if there is one. 211 if (Triple.isOSDarwin()) 212 Builder.defineMacro("__MACH__"); 213 214 // The Watch ABI uses Dwarf EH. 215 if(Triple.isWatchABI()) 216 Builder.defineMacro("__ARM_DWARF_EH__"); 217 218 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 219 } 220 221 template<typename Target> 222 class DarwinTargetInfo : public OSTargetInfo<Target> { 223 protected: 224 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 225 MacroBuilder &Builder) const override { 226 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 227 this->PlatformMinVersion); 228 } 229 230 public: 231 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 232 : OSTargetInfo<Target>(Triple, Opts) { 233 // By default, no TLS, and we whitelist permitted architecture/OS 234 // combinations. 235 this->TLSSupported = false; 236 237 if (Triple.isMacOSX()) 238 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 239 else if (Triple.isiOS()) { 240 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 241 if (Triple.getArch() == llvm::Triple::x86_64 || 242 Triple.getArch() == llvm::Triple::aarch64) 243 this->TLSSupported = !Triple.isOSVersionLT(8); 244 else if (Triple.getArch() == llvm::Triple::x86 || 245 Triple.getArch() == llvm::Triple::arm || 246 Triple.getArch() == llvm::Triple::thumb) 247 this->TLSSupported = !Triple.isOSVersionLT(9); 248 } else if (Triple.isWatchOS()) 249 this->TLSSupported = !Triple.isOSVersionLT(2); 250 251 this->MCountName = "\01mcount"; 252 } 253 254 std::string isValidSectionSpecifier(StringRef SR) const override { 255 // Let MCSectionMachO validate this. 256 StringRef Segment, Section; 257 unsigned TAA, StubSize; 258 bool HasTAA; 259 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 260 TAA, HasTAA, StubSize); 261 } 262 263 const char *getStaticInitSectionSpecifier() const override { 264 // FIXME: We should return 0 when building kexts. 265 return "__TEXT,__StaticInit,regular,pure_instructions"; 266 } 267 268 /// Darwin does not support protected visibility. Darwin's "default" 269 /// is very similar to ELF's "protected"; Darwin requires a "weak" 270 /// attribute on declarations that can be dynamically replaced. 271 bool hasProtectedVisibility() const override { 272 return false; 273 } 274 275 unsigned getExnObjectAlignment() const override { 276 // The alignment of an exception object is 8-bytes for darwin since 277 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 278 // and therefore doesn't guarantee 16-byte alignment. 279 return 64; 280 } 281 }; 282 283 284 // DragonFlyBSD Target 285 template<typename Target> 286 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 287 protected: 288 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 289 MacroBuilder &Builder) const override { 290 // DragonFly defines; list based off of gcc output 291 Builder.defineMacro("__DragonFly__"); 292 Builder.defineMacro("__DragonFly_cc_version", "100001"); 293 Builder.defineMacro("__ELF__"); 294 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 295 Builder.defineMacro("__tune_i386__"); 296 DefineStd(Builder, "unix", Opts); 297 } 298 public: 299 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 300 : OSTargetInfo<Target>(Triple, Opts) { 301 switch (Triple.getArch()) { 302 default: 303 case llvm::Triple::x86: 304 case llvm::Triple::x86_64: 305 this->MCountName = ".mcount"; 306 break; 307 } 308 } 309 }; 310 311 #ifndef FREEBSD_CC_VERSION 312 #define FREEBSD_CC_VERSION 0U 313 #endif 314 315 // FreeBSD Target 316 template<typename Target> 317 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const override { 321 // FreeBSD defines; list based off of gcc output 322 323 unsigned Release = Triple.getOSMajorVersion(); 324 if (Release == 0U) 325 Release = 8U; 326 unsigned CCVersion = FREEBSD_CC_VERSION; 327 if (CCVersion == 0U) 328 CCVersion = Release * 100000U + 1U; 329 330 Builder.defineMacro("__FreeBSD__", Twine(Release)); 331 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 332 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 333 DefineStd(Builder, "unix", Opts); 334 Builder.defineMacro("__ELF__"); 335 336 // On FreeBSD, wchar_t contains the number of the code point as 337 // used by the character set of the locale. These character sets are 338 // not necessarily a superset of ASCII. 339 // 340 // FIXME: This is wrong; the macro refers to the numerical values 341 // of wchar_t *literals*, which are not locale-dependent. However, 342 // FreeBSD systems apparently depend on us getting this wrong, and 343 // setting this to 1 is conforming even if all the basic source 344 // character literals have the same encoding as char and wchar_t. 345 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 346 } 347 public: 348 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 349 : OSTargetInfo<Target>(Triple, Opts) { 350 switch (Triple.getArch()) { 351 default: 352 case llvm::Triple::x86: 353 case llvm::Triple::x86_64: 354 this->MCountName = ".mcount"; 355 break; 356 case llvm::Triple::mips: 357 case llvm::Triple::mipsel: 358 case llvm::Triple::ppc: 359 case llvm::Triple::ppc64: 360 case llvm::Triple::ppc64le: 361 this->MCountName = "_mcount"; 362 break; 363 case llvm::Triple::arm: 364 this->MCountName = "__mcount"; 365 break; 366 } 367 } 368 }; 369 370 // GNU/kFreeBSD Target 371 template<typename Target> 372 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 373 protected: 374 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 375 MacroBuilder &Builder) const override { 376 // GNU/kFreeBSD defines; list based off of gcc output 377 378 DefineStd(Builder, "unix", Opts); 379 Builder.defineMacro("__FreeBSD_kernel__"); 380 Builder.defineMacro("__GLIBC__"); 381 Builder.defineMacro("__ELF__"); 382 if (Opts.POSIXThreads) 383 Builder.defineMacro("_REENTRANT"); 384 if (Opts.CPlusPlus) 385 Builder.defineMacro("_GNU_SOURCE"); 386 } 387 public: 388 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 389 : OSTargetInfo<Target>(Triple, Opts) {} 390 }; 391 392 // Haiku Target 393 template<typename Target> 394 class HaikuTargetInfo : public OSTargetInfo<Target> { 395 protected: 396 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 397 MacroBuilder &Builder) const override { 398 // Haiku defines; list based off of gcc output 399 Builder.defineMacro("__HAIKU__"); 400 Builder.defineMacro("__ELF__"); 401 DefineStd(Builder, "unix", Opts); 402 } 403 public: 404 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 405 : OSTargetInfo<Target>(Triple, Opts) { 406 this->SizeType = TargetInfo::UnsignedLong; 407 this->IntPtrType = TargetInfo::SignedLong; 408 this->PtrDiffType = TargetInfo::SignedLong; 409 this->ProcessIDType = TargetInfo::SignedLong; 410 this->TLSSupported = false; 411 412 } 413 }; 414 415 // Minix Target 416 template<typename Target> 417 class MinixTargetInfo : public OSTargetInfo<Target> { 418 protected: 419 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 420 MacroBuilder &Builder) const override { 421 // Minix defines 422 423 Builder.defineMacro("__minix", "3"); 424 Builder.defineMacro("_EM_WSIZE", "4"); 425 Builder.defineMacro("_EM_PSIZE", "4"); 426 Builder.defineMacro("_EM_SSIZE", "2"); 427 Builder.defineMacro("_EM_LSIZE", "4"); 428 Builder.defineMacro("_EM_FSIZE", "4"); 429 Builder.defineMacro("_EM_DSIZE", "8"); 430 Builder.defineMacro("__ELF__"); 431 DefineStd(Builder, "unix", Opts); 432 } 433 public: 434 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 435 : OSTargetInfo<Target>(Triple, Opts) {} 436 }; 437 438 // Linux target 439 template<typename Target> 440 class LinuxTargetInfo : public OSTargetInfo<Target> { 441 protected: 442 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 443 MacroBuilder &Builder) const override { 444 // Linux defines; list based off of gcc output 445 DefineStd(Builder, "unix", Opts); 446 DefineStd(Builder, "linux", Opts); 447 Builder.defineMacro("__gnu_linux__"); 448 Builder.defineMacro("__ELF__"); 449 if (Triple.isAndroid()) { 450 Builder.defineMacro("__ANDROID__", "1"); 451 unsigned Maj, Min, Rev; 452 Triple.getEnvironmentVersion(Maj, Min, Rev); 453 this->PlatformName = "android"; 454 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 455 } 456 if (Opts.POSIXThreads) 457 Builder.defineMacro("_REENTRANT"); 458 if (Opts.CPlusPlus) 459 Builder.defineMacro("_GNU_SOURCE"); 460 if (this->HasFloat128) 461 Builder.defineMacro("__FLOAT128__"); 462 } 463 public: 464 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 465 : OSTargetInfo<Target>(Triple, Opts) { 466 this->WIntType = TargetInfo::UnsignedInt; 467 468 switch (Triple.getArch()) { 469 default: 470 break; 471 case llvm::Triple::ppc: 472 case llvm::Triple::ppc64: 473 case llvm::Triple::ppc64le: 474 this->MCountName = "_mcount"; 475 break; 476 case llvm::Triple::x86: 477 case llvm::Triple::x86_64: 478 case llvm::Triple::systemz: 479 this->HasFloat128 = true; 480 break; 481 } 482 } 483 484 const char *getStaticInitSectionSpecifier() const override { 485 return ".text.startup"; 486 } 487 }; 488 489 // NetBSD Target 490 template<typename Target> 491 class NetBSDTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // NetBSD defines; list based off of gcc output 496 Builder.defineMacro("__NetBSD__"); 497 Builder.defineMacro("__unix__"); 498 Builder.defineMacro("__ELF__"); 499 if (Opts.POSIXThreads) 500 Builder.defineMacro("_POSIX_THREADS"); 501 502 switch (Triple.getArch()) { 503 default: 504 break; 505 case llvm::Triple::arm: 506 case llvm::Triple::armeb: 507 case llvm::Triple::thumb: 508 case llvm::Triple::thumbeb: 509 Builder.defineMacro("__ARM_DWARF_EH__"); 510 break; 511 } 512 } 513 public: 514 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 515 : OSTargetInfo<Target>(Triple, Opts) { 516 this->MCountName = "_mcount"; 517 } 518 }; 519 520 // OpenBSD Target 521 template<typename Target> 522 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 // OpenBSD defines; list based off of gcc output 527 528 Builder.defineMacro("__OpenBSD__"); 529 DefineStd(Builder, "unix", Opts); 530 Builder.defineMacro("__ELF__"); 531 if (Opts.POSIXThreads) 532 Builder.defineMacro("_REENTRANT"); 533 } 534 public: 535 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 536 : OSTargetInfo<Target>(Triple, Opts) { 537 this->TLSSupported = false; 538 539 switch (Triple.getArch()) { 540 default: 541 case llvm::Triple::x86: 542 case llvm::Triple::x86_64: 543 case llvm::Triple::arm: 544 case llvm::Triple::sparc: 545 this->MCountName = "__mcount"; 546 break; 547 case llvm::Triple::mips64: 548 case llvm::Triple::mips64el: 549 case llvm::Triple::ppc: 550 case llvm::Triple::sparcv9: 551 this->MCountName = "_mcount"; 552 break; 553 } 554 } 555 }; 556 557 // Bitrig Target 558 template<typename Target> 559 class BitrigTargetInfo : public OSTargetInfo<Target> { 560 protected: 561 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 562 MacroBuilder &Builder) const override { 563 // Bitrig defines; list based off of gcc output 564 565 Builder.defineMacro("__Bitrig__"); 566 DefineStd(Builder, "unix", Opts); 567 Builder.defineMacro("__ELF__"); 568 if (Opts.POSIXThreads) 569 Builder.defineMacro("_REENTRANT"); 570 571 switch (Triple.getArch()) { 572 default: 573 break; 574 case llvm::Triple::arm: 575 case llvm::Triple::armeb: 576 case llvm::Triple::thumb: 577 case llvm::Triple::thumbeb: 578 Builder.defineMacro("__ARM_DWARF_EH__"); 579 break; 580 } 581 } 582 public: 583 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 584 : OSTargetInfo<Target>(Triple, Opts) { 585 this->MCountName = "__mcount"; 586 } 587 }; 588 589 // PSP Target 590 template<typename Target> 591 class PSPTargetInfo : public OSTargetInfo<Target> { 592 protected: 593 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 594 MacroBuilder &Builder) const override { 595 // PSP defines; list based on the output of the pspdev gcc toolchain. 596 Builder.defineMacro("PSP"); 597 Builder.defineMacro("_PSP"); 598 Builder.defineMacro("__psp__"); 599 Builder.defineMacro("__ELF__"); 600 } 601 public: 602 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 603 }; 604 605 // PS3 PPU Target 606 template<typename Target> 607 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 608 protected: 609 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 610 MacroBuilder &Builder) const override { 611 // PS3 PPU defines. 612 Builder.defineMacro("__PPC__"); 613 Builder.defineMacro("__PPU__"); 614 Builder.defineMacro("__CELLOS_LV2__"); 615 Builder.defineMacro("__ELF__"); 616 Builder.defineMacro("__LP32__"); 617 Builder.defineMacro("_ARCH_PPC64"); 618 Builder.defineMacro("__powerpc64__"); 619 } 620 public: 621 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 622 : OSTargetInfo<Target>(Triple, Opts) { 623 this->LongWidth = this->LongAlign = 32; 624 this->PointerWidth = this->PointerAlign = 32; 625 this->IntMaxType = TargetInfo::SignedLongLong; 626 this->Int64Type = TargetInfo::SignedLongLong; 627 this->SizeType = TargetInfo::UnsignedInt; 628 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 629 } 630 }; 631 632 template <typename Target> 633 class PS4OSTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("__FreeBSD__", "9"); 638 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 639 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 640 DefineStd(Builder, "unix", Opts); 641 Builder.defineMacro("__ELF__"); 642 Builder.defineMacro("__ORBIS__"); 643 } 644 public: 645 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 646 : OSTargetInfo<Target>(Triple, Opts) { 647 this->WCharType = this->UnsignedShort; 648 649 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 650 this->MaxTLSAlign = 256; 651 652 // On PS4, do not honor explicit bit field alignment, 653 // as in "__attribute__((aligned(2))) int b : 1;". 654 this->UseExplicitBitFieldAlignment = false; 655 656 switch (Triple.getArch()) { 657 default: 658 case llvm::Triple::x86_64: 659 this->MCountName = ".mcount"; 660 break; 661 } 662 } 663 }; 664 665 // Solaris target 666 template<typename Target> 667 class SolarisTargetInfo : public OSTargetInfo<Target> { 668 protected: 669 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 670 MacroBuilder &Builder) const override { 671 DefineStd(Builder, "sun", Opts); 672 DefineStd(Builder, "unix", Opts); 673 Builder.defineMacro("__ELF__"); 674 Builder.defineMacro("__svr4__"); 675 Builder.defineMacro("__SVR4"); 676 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 677 // newer, but to 500 for everything else. feature_test.h has a check to 678 // ensure that you are not using C99 with an old version of X/Open or C89 679 // with a new version. 680 if (Opts.C99) 681 Builder.defineMacro("_XOPEN_SOURCE", "600"); 682 else 683 Builder.defineMacro("_XOPEN_SOURCE", "500"); 684 if (Opts.CPlusPlus) 685 Builder.defineMacro("__C99FEATURES__"); 686 Builder.defineMacro("_LARGEFILE_SOURCE"); 687 Builder.defineMacro("_LARGEFILE64_SOURCE"); 688 Builder.defineMacro("__EXTENSIONS__"); 689 Builder.defineMacro("_REENTRANT"); 690 } 691 public: 692 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 693 : OSTargetInfo<Target>(Triple, Opts) { 694 this->WCharType = this->SignedInt; 695 // FIXME: WIntType should be SignedLong 696 } 697 }; 698 699 // Windows target 700 template<typename Target> 701 class WindowsTargetInfo : public OSTargetInfo<Target> { 702 protected: 703 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 704 MacroBuilder &Builder) const override { 705 Builder.defineMacro("_WIN32"); 706 } 707 void getVisualStudioDefines(const LangOptions &Opts, 708 MacroBuilder &Builder) const { 709 if (Opts.CPlusPlus) { 710 if (Opts.RTTIData) 711 Builder.defineMacro("_CPPRTTI"); 712 713 if (Opts.CXXExceptions) 714 Builder.defineMacro("_CPPUNWIND"); 715 } 716 717 if (Opts.Bool) 718 Builder.defineMacro("__BOOL_DEFINED"); 719 720 if (!Opts.CharIsSigned) 721 Builder.defineMacro("_CHAR_UNSIGNED"); 722 723 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 724 // but it works for now. 725 if (Opts.POSIXThreads) 726 Builder.defineMacro("_MT"); 727 728 if (Opts.MSCompatibilityVersion) { 729 Builder.defineMacro("_MSC_VER", 730 Twine(Opts.MSCompatibilityVersion / 100000)); 731 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 732 // FIXME We cannot encode the revision information into 32-bits 733 Builder.defineMacro("_MSC_BUILD", Twine(1)); 734 735 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 736 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 737 } 738 739 if (Opts.MicrosoftExt) { 740 Builder.defineMacro("_MSC_EXTENSIONS"); 741 742 if (Opts.CPlusPlus11) { 743 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 744 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 745 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 746 } 747 } 748 749 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 750 } 751 752 public: 753 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 754 : OSTargetInfo<Target>(Triple, Opts) {} 755 }; 756 757 template <typename Target> 758 class NaClTargetInfo : public OSTargetInfo<Target> { 759 protected: 760 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 761 MacroBuilder &Builder) const override { 762 if (Opts.POSIXThreads) 763 Builder.defineMacro("_REENTRANT"); 764 if (Opts.CPlusPlus) 765 Builder.defineMacro("_GNU_SOURCE"); 766 767 DefineStd(Builder, "unix", Opts); 768 Builder.defineMacro("__ELF__"); 769 Builder.defineMacro("__native_client__"); 770 } 771 772 public: 773 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) { 775 this->LongAlign = 32; 776 this->LongWidth = 32; 777 this->PointerAlign = 32; 778 this->PointerWidth = 32; 779 this->IntMaxType = TargetInfo::SignedLongLong; 780 this->Int64Type = TargetInfo::SignedLongLong; 781 this->DoubleAlign = 64; 782 this->LongDoubleWidth = 64; 783 this->LongDoubleAlign = 64; 784 this->LongLongWidth = 64; 785 this->LongLongAlign = 64; 786 this->SizeType = TargetInfo::UnsignedInt; 787 this->PtrDiffType = TargetInfo::SignedInt; 788 this->IntPtrType = TargetInfo::SignedInt; 789 // RegParmMax is inherited from the underlying architecture 790 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 791 if (Triple.getArch() == llvm::Triple::arm) { 792 // Handled in ARM's setABI(). 793 } else if (Triple.getArch() == llvm::Triple::x86) { 794 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 795 } else if (Triple.getArch() == llvm::Triple::x86_64) { 796 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 797 } else if (Triple.getArch() == llvm::Triple::mipsel) { 798 // Handled on mips' setDataLayout. 799 } else { 800 assert(Triple.getArch() == llvm::Triple::le32); 801 this->resetDataLayout("e-p:32:32-i64:64"); 802 } 803 } 804 }; 805 806 // WebAssembly target 807 template <typename Target> 808 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 809 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 810 MacroBuilder &Builder) const final { 811 // A common platform macro. 812 if (Opts.POSIXThreads) 813 Builder.defineMacro("_REENTRANT"); 814 // Follow g++ convention and predefine _GNU_SOURCE for C++. 815 if (Opts.CPlusPlus) 816 Builder.defineMacro("_GNU_SOURCE"); 817 } 818 819 // As an optimization, group static init code together in a section. 820 const char *getStaticInitSectionSpecifier() const final { 821 return ".text.__startup"; 822 } 823 824 public: 825 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 826 const TargetOptions &Opts) 827 : OSTargetInfo<Target>(Triple, Opts) { 828 this->MCountName = "__mcount"; 829 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 830 } 831 }; 832 833 //===----------------------------------------------------------------------===// 834 // Specific target implementations. 835 //===----------------------------------------------------------------------===// 836 837 // PPC abstract base class 838 class PPCTargetInfo : public TargetInfo { 839 static const Builtin::Info BuiltinInfo[]; 840 static const char * const GCCRegNames[]; 841 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 842 std::string CPU; 843 844 // Target cpu features. 845 bool HasVSX; 846 bool HasP8Vector; 847 bool HasP8Crypto; 848 bool HasDirectMove; 849 bool HasQPX; 850 bool HasHTM; 851 bool HasBPERMD; 852 bool HasExtDiv; 853 854 protected: 855 std::string ABI; 856 857 public: 858 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 859 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 860 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 861 HasBPERMD(false), HasExtDiv(false) { 862 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 863 SimdDefaultAlign = 128; 864 LongDoubleWidth = LongDoubleAlign = 128; 865 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 866 } 867 868 /// \brief Flags for architecture specific defines. 869 typedef enum { 870 ArchDefineNone = 0, 871 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 872 ArchDefinePpcgr = 1 << 1, 873 ArchDefinePpcsq = 1 << 2, 874 ArchDefine440 = 1 << 3, 875 ArchDefine603 = 1 << 4, 876 ArchDefine604 = 1 << 5, 877 ArchDefinePwr4 = 1 << 6, 878 ArchDefinePwr5 = 1 << 7, 879 ArchDefinePwr5x = 1 << 8, 880 ArchDefinePwr6 = 1 << 9, 881 ArchDefinePwr6x = 1 << 10, 882 ArchDefinePwr7 = 1 << 11, 883 ArchDefinePwr8 = 1 << 12, 884 ArchDefinePwr9 = 1 << 13, 885 ArchDefineA2 = 1 << 14, 886 ArchDefineA2q = 1 << 15 887 } ArchDefineTypes; 888 889 // Note: GCC recognizes the following additional cpus: 890 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 891 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 892 // titan, rs64. 893 bool setCPU(const std::string &Name) override { 894 bool CPUKnown = llvm::StringSwitch<bool>(Name) 895 .Case("generic", true) 896 .Case("440", true) 897 .Case("450", true) 898 .Case("601", true) 899 .Case("602", true) 900 .Case("603", true) 901 .Case("603e", true) 902 .Case("603ev", true) 903 .Case("604", true) 904 .Case("604e", true) 905 .Case("620", true) 906 .Case("630", true) 907 .Case("g3", true) 908 .Case("7400", true) 909 .Case("g4", true) 910 .Case("7450", true) 911 .Case("g4+", true) 912 .Case("750", true) 913 .Case("970", true) 914 .Case("g5", true) 915 .Case("a2", true) 916 .Case("a2q", true) 917 .Case("e500mc", true) 918 .Case("e5500", true) 919 .Case("power3", true) 920 .Case("pwr3", true) 921 .Case("power4", true) 922 .Case("pwr4", true) 923 .Case("power5", true) 924 .Case("pwr5", true) 925 .Case("power5x", true) 926 .Case("pwr5x", true) 927 .Case("power6", true) 928 .Case("pwr6", true) 929 .Case("power6x", true) 930 .Case("pwr6x", true) 931 .Case("power7", true) 932 .Case("pwr7", true) 933 .Case("power8", true) 934 .Case("pwr8", true) 935 .Case("power9", true) 936 .Case("pwr9", true) 937 .Case("powerpc", true) 938 .Case("ppc", true) 939 .Case("powerpc64", true) 940 .Case("ppc64", true) 941 .Case("powerpc64le", true) 942 .Case("ppc64le", true) 943 .Default(false); 944 945 if (CPUKnown) 946 CPU = Name; 947 948 return CPUKnown; 949 } 950 951 952 StringRef getABI() const override { return ABI; } 953 954 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 955 return llvm::makeArrayRef(BuiltinInfo, 956 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 957 } 958 959 bool isCLZForZeroUndef() const override { return false; } 960 961 void getTargetDefines(const LangOptions &Opts, 962 MacroBuilder &Builder) const override; 963 964 bool 965 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 966 StringRef CPU, 967 const std::vector<std::string> &FeaturesVec) const override; 968 969 bool handleTargetFeatures(std::vector<std::string> &Features, 970 DiagnosticsEngine &Diags) override; 971 bool hasFeature(StringRef Feature) const override; 972 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 973 bool Enabled) const override; 974 975 ArrayRef<const char *> getGCCRegNames() const override; 976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 977 bool validateAsmConstraint(const char *&Name, 978 TargetInfo::ConstraintInfo &Info) const override { 979 switch (*Name) { 980 default: return false; 981 case 'O': // Zero 982 break; 983 case 'b': // Base register 984 case 'f': // Floating point register 985 Info.setAllowsRegister(); 986 break; 987 // FIXME: The following are added to allow parsing. 988 // I just took a guess at what the actions should be. 989 // Also, is more specific checking needed? I.e. specific registers? 990 case 'd': // Floating point register (containing 64-bit value) 991 case 'v': // Altivec vector register 992 Info.setAllowsRegister(); 993 break; 994 case 'w': 995 switch (Name[1]) { 996 case 'd':// VSX vector register to hold vector double data 997 case 'f':// VSX vector register to hold vector float data 998 case 's':// VSX vector register to hold scalar float data 999 case 'a':// Any VSX register 1000 case 'c':// An individual CR bit 1001 break; 1002 default: 1003 return false; 1004 } 1005 Info.setAllowsRegister(); 1006 Name++; // Skip over 'w'. 1007 break; 1008 case 'h': // `MQ', `CTR', or `LINK' register 1009 case 'q': // `MQ' register 1010 case 'c': // `CTR' register 1011 case 'l': // `LINK' register 1012 case 'x': // `CR' register (condition register) number 0 1013 case 'y': // `CR' register (condition register) 1014 case 'z': // `XER[CA]' carry bit (part of the XER register) 1015 Info.setAllowsRegister(); 1016 break; 1017 case 'I': // Signed 16-bit constant 1018 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1019 // (use `L' instead for SImode constants) 1020 case 'K': // Unsigned 16-bit constant 1021 case 'L': // Signed 16-bit constant shifted left 16 bits 1022 case 'M': // Constant larger than 31 1023 case 'N': // Exact power of 2 1024 case 'P': // Constant whose negation is a signed 16-bit constant 1025 case 'G': // Floating point constant that can be loaded into a 1026 // register with one instruction per word 1027 case 'H': // Integer/Floating point constant that can be loaded 1028 // into a register using three instructions 1029 break; 1030 case 'm': // Memory operand. Note that on PowerPC targets, m can 1031 // include addresses that update the base register. It 1032 // is therefore only safe to use `m' in an asm statement 1033 // if that asm statement accesses the operand exactly once. 1034 // The asm statement must also use `%U<opno>' as a 1035 // placeholder for the "update" flag in the corresponding 1036 // load or store instruction. For example: 1037 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1038 // is correct but: 1039 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1040 // is not. Use es rather than m if you don't want the base 1041 // register to be updated. 1042 case 'e': 1043 if (Name[1] != 's') 1044 return false; 1045 // es: A "stable" memory operand; that is, one which does not 1046 // include any automodification of the base register. Unlike 1047 // `m', this constraint can be used in asm statements that 1048 // might access the operand several times, or that might not 1049 // access it at all. 1050 Info.setAllowsMemory(); 1051 Name++; // Skip over 'e'. 1052 break; 1053 case 'Q': // Memory operand that is an offset from a register (it is 1054 // usually better to use `m' or `es' in asm statements) 1055 case 'Z': // Memory operand that is an indexed or indirect from a 1056 // register (it is usually better to use `m' or `es' in 1057 // asm statements) 1058 Info.setAllowsMemory(); 1059 Info.setAllowsRegister(); 1060 break; 1061 case 'R': // AIX TOC entry 1062 case 'a': // Address operand that is an indexed or indirect from a 1063 // register (`p' is preferable for asm statements) 1064 case 'S': // Constant suitable as a 64-bit mask operand 1065 case 'T': // Constant suitable as a 32-bit mask operand 1066 case 'U': // System V Release 4 small data area reference 1067 case 't': // AND masks that can be performed by two rldic{l, r} 1068 // instructions 1069 case 'W': // Vector constant that does not require memory 1070 case 'j': // Vector constant that is all zeros. 1071 break; 1072 // End FIXME. 1073 } 1074 return true; 1075 } 1076 std::string convertConstraint(const char *&Constraint) const override { 1077 std::string R; 1078 switch (*Constraint) { 1079 case 'e': 1080 case 'w': 1081 // Two-character constraint; add "^" hint for later parsing. 1082 R = std::string("^") + std::string(Constraint, 2); 1083 Constraint++; 1084 break; 1085 default: 1086 return TargetInfo::convertConstraint(Constraint); 1087 } 1088 return R; 1089 } 1090 const char *getClobbers() const override { 1091 return ""; 1092 } 1093 int getEHDataRegisterNumber(unsigned RegNo) const override { 1094 if (RegNo == 0) return 3; 1095 if (RegNo == 1) return 4; 1096 return -1; 1097 } 1098 1099 bool hasSjLjLowering() const override { 1100 return true; 1101 } 1102 1103 bool useFloat128ManglingForLongDouble() const override { 1104 return LongDoubleWidth == 128 && 1105 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1106 getTriple().isOSBinFormatELF(); 1107 } 1108 }; 1109 1110 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1111 #define BUILTIN(ID, TYPE, ATTRS) \ 1112 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1113 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1114 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1115 #include "clang/Basic/BuiltinsPPC.def" 1116 }; 1117 1118 /// handleTargetFeatures - Perform initialization based on the user 1119 /// configured set of features. 1120 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1121 DiagnosticsEngine &Diags) { 1122 for (const auto &Feature : Features) { 1123 if (Feature == "+vsx") { 1124 HasVSX = true; 1125 } else if (Feature == "+bpermd") { 1126 HasBPERMD = true; 1127 } else if (Feature == "+extdiv") { 1128 HasExtDiv = true; 1129 } else if (Feature == "+power8-vector") { 1130 HasP8Vector = true; 1131 } else if (Feature == "+crypto") { 1132 HasP8Crypto = true; 1133 } else if (Feature == "+direct-move") { 1134 HasDirectMove = true; 1135 } else if (Feature == "+qpx") { 1136 HasQPX = true; 1137 } else if (Feature == "+htm") { 1138 HasHTM = true; 1139 } else if (Feature == "+float128") { 1140 HasFloat128 = true; 1141 } 1142 // TODO: Finish this list and add an assert that we've handled them 1143 // all. 1144 } 1145 1146 return true; 1147 } 1148 1149 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1150 /// #defines that are not tied to a specific subtarget. 1151 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1152 MacroBuilder &Builder) const { 1153 // Target identification. 1154 Builder.defineMacro("__ppc__"); 1155 Builder.defineMacro("__PPC__"); 1156 Builder.defineMacro("_ARCH_PPC"); 1157 Builder.defineMacro("__powerpc__"); 1158 Builder.defineMacro("__POWERPC__"); 1159 if (PointerWidth == 64) { 1160 Builder.defineMacro("_ARCH_PPC64"); 1161 Builder.defineMacro("__powerpc64__"); 1162 Builder.defineMacro("__ppc64__"); 1163 Builder.defineMacro("__PPC64__"); 1164 } 1165 1166 // Target properties. 1167 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1168 Builder.defineMacro("_LITTLE_ENDIAN"); 1169 } else { 1170 if (getTriple().getOS() != llvm::Triple::NetBSD && 1171 getTriple().getOS() != llvm::Triple::OpenBSD) 1172 Builder.defineMacro("_BIG_ENDIAN"); 1173 } 1174 1175 // ABI options. 1176 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1177 Builder.defineMacro("_CALL_ELF", "1"); 1178 if (ABI == "elfv2") 1179 Builder.defineMacro("_CALL_ELF", "2"); 1180 1181 // Subtarget options. 1182 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1183 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1184 1185 // FIXME: Should be controlled by command line option. 1186 if (LongDoubleWidth == 128) 1187 Builder.defineMacro("__LONG_DOUBLE_128__"); 1188 1189 if (Opts.AltiVec) { 1190 Builder.defineMacro("__VEC__", "10206"); 1191 Builder.defineMacro("__ALTIVEC__"); 1192 } 1193 1194 // CPU identification. 1195 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1196 .Case("440", ArchDefineName) 1197 .Case("450", ArchDefineName | ArchDefine440) 1198 .Case("601", ArchDefineName) 1199 .Case("602", ArchDefineName | ArchDefinePpcgr) 1200 .Case("603", ArchDefineName | ArchDefinePpcgr) 1201 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1202 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1203 .Case("604", ArchDefineName | ArchDefinePpcgr) 1204 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1205 .Case("620", ArchDefineName | ArchDefinePpcgr) 1206 .Case("630", ArchDefineName | ArchDefinePpcgr) 1207 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1208 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1209 .Case("750", ArchDefineName | ArchDefinePpcgr) 1210 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1211 | ArchDefinePpcsq) 1212 .Case("a2", ArchDefineA2) 1213 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1214 .Case("pwr3", ArchDefinePpcgr) 1215 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1216 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1217 | ArchDefinePpcsq) 1218 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1219 | ArchDefinePpcgr | ArchDefinePpcsq) 1220 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1221 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1222 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1223 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1224 | ArchDefinePpcsq) 1225 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1226 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1227 | ArchDefinePpcgr | ArchDefinePpcsq) 1228 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1229 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1230 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1231 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1232 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1233 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1234 | ArchDefinePpcsq) 1235 .Case("power3", ArchDefinePpcgr) 1236 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1237 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1238 | ArchDefinePpcsq) 1239 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1240 | ArchDefinePpcgr | ArchDefinePpcsq) 1241 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1242 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1243 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1244 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1245 | ArchDefinePpcsq) 1246 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1247 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1248 | ArchDefinePpcgr | ArchDefinePpcsq) 1249 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1250 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1251 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1252 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1253 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1254 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Default(ArchDefineNone); 1257 1258 if (defs & ArchDefineName) 1259 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1260 if (defs & ArchDefinePpcgr) 1261 Builder.defineMacro("_ARCH_PPCGR"); 1262 if (defs & ArchDefinePpcsq) 1263 Builder.defineMacro("_ARCH_PPCSQ"); 1264 if (defs & ArchDefine440) 1265 Builder.defineMacro("_ARCH_440"); 1266 if (defs & ArchDefine603) 1267 Builder.defineMacro("_ARCH_603"); 1268 if (defs & ArchDefine604) 1269 Builder.defineMacro("_ARCH_604"); 1270 if (defs & ArchDefinePwr4) 1271 Builder.defineMacro("_ARCH_PWR4"); 1272 if (defs & ArchDefinePwr5) 1273 Builder.defineMacro("_ARCH_PWR5"); 1274 if (defs & ArchDefinePwr5x) 1275 Builder.defineMacro("_ARCH_PWR5X"); 1276 if (defs & ArchDefinePwr6) 1277 Builder.defineMacro("_ARCH_PWR6"); 1278 if (defs & ArchDefinePwr6x) 1279 Builder.defineMacro("_ARCH_PWR6X"); 1280 if (defs & ArchDefinePwr7) 1281 Builder.defineMacro("_ARCH_PWR7"); 1282 if (defs & ArchDefinePwr8) 1283 Builder.defineMacro("_ARCH_PWR8"); 1284 if (defs & ArchDefinePwr9) 1285 Builder.defineMacro("_ARCH_PWR9"); 1286 if (defs & ArchDefineA2) 1287 Builder.defineMacro("_ARCH_A2"); 1288 if (defs & ArchDefineA2q) { 1289 Builder.defineMacro("_ARCH_A2Q"); 1290 Builder.defineMacro("_ARCH_QP"); 1291 } 1292 1293 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1294 Builder.defineMacro("__bg__"); 1295 Builder.defineMacro("__THW_BLUEGENE__"); 1296 Builder.defineMacro("__bgq__"); 1297 Builder.defineMacro("__TOS_BGQ__"); 1298 } 1299 1300 if (HasVSX) 1301 Builder.defineMacro("__VSX__"); 1302 if (HasP8Vector) 1303 Builder.defineMacro("__POWER8_VECTOR__"); 1304 if (HasP8Crypto) 1305 Builder.defineMacro("__CRYPTO__"); 1306 if (HasHTM) 1307 Builder.defineMacro("__HTM__"); 1308 if (HasFloat128) 1309 Builder.defineMacro("__FLOAT128__"); 1310 1311 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1312 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1314 if (PointerWidth == 64) 1315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1316 1317 // FIXME: The following are not yet generated here by Clang, but are 1318 // generated by GCC: 1319 // 1320 // _SOFT_FLOAT_ 1321 // __RECIP_PRECISION__ 1322 // __APPLE_ALTIVEC__ 1323 // __RECIP__ 1324 // __RECIPF__ 1325 // __RSQRTE__ 1326 // __RSQRTEF__ 1327 // _SOFT_DOUBLE_ 1328 // __NO_LWSYNC__ 1329 // __HAVE_BSWAP__ 1330 // __LONGDOUBLE128 1331 // __CMODEL_MEDIUM__ 1332 // __CMODEL_LARGE__ 1333 // _CALL_SYSV 1334 // _CALL_DARWIN 1335 // __NO_FPRS__ 1336 } 1337 1338 // Handle explicit options being passed to the compiler here: if we've 1339 // explicitly turned off vsx and turned on power8-vector or direct-move then 1340 // go ahead and error since the customer has expressed a somewhat incompatible 1341 // set of options. 1342 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1343 const std::vector<std::string> &FeaturesVec) { 1344 1345 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1346 FeaturesVec.end()) { 1347 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1348 FeaturesVec.end()) { 1349 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1350 << "-mno-vsx"; 1351 return false; 1352 } 1353 1354 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1355 FeaturesVec.end()) { 1356 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1357 << "-mno-vsx"; 1358 return false; 1359 } 1360 1361 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1362 FeaturesVec.end()) { 1363 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1364 << "-mno-vsx"; 1365 return false; 1366 } 1367 } 1368 1369 return true; 1370 } 1371 1372 bool PPCTargetInfo::initFeatureMap( 1373 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1374 const std::vector<std::string> &FeaturesVec) const { 1375 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1376 .Case("7400", true) 1377 .Case("g4", true) 1378 .Case("7450", true) 1379 .Case("g4+", true) 1380 .Case("970", true) 1381 .Case("g5", true) 1382 .Case("pwr6", true) 1383 .Case("pwr7", true) 1384 .Case("pwr8", true) 1385 .Case("pwr9", true) 1386 .Case("ppc64", true) 1387 .Case("ppc64le", true) 1388 .Default(false); 1389 1390 Features["qpx"] = (CPU == "a2q"); 1391 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1392 .Case("ppc64le", true) 1393 .Case("pwr9", true) 1394 .Case("pwr8", true) 1395 .Default(false); 1396 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1397 .Case("ppc64le", true) 1398 .Case("pwr9", true) 1399 .Case("pwr8", true) 1400 .Default(false); 1401 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1402 .Case("ppc64le", true) 1403 .Case("pwr9", true) 1404 .Case("pwr8", true) 1405 .Case("pwr7", true) 1406 .Default(false); 1407 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1408 .Case("ppc64le", true) 1409 .Case("pwr9", true) 1410 .Case("pwr8", true) 1411 .Case("pwr7", true) 1412 .Default(false); 1413 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1414 .Case("ppc64le", true) 1415 .Case("pwr9", true) 1416 .Case("pwr8", true) 1417 .Default(false); 1418 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1419 .Case("ppc64le", true) 1420 .Case("pwr9", true) 1421 .Case("pwr8", true) 1422 .Case("pwr7", true) 1423 .Default(false); 1424 1425 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1426 return false; 1427 1428 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1429 } 1430 1431 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1432 return llvm::StringSwitch<bool>(Feature) 1433 .Case("powerpc", true) 1434 .Case("vsx", HasVSX) 1435 .Case("power8-vector", HasP8Vector) 1436 .Case("crypto", HasP8Crypto) 1437 .Case("direct-move", HasDirectMove) 1438 .Case("qpx", HasQPX) 1439 .Case("htm", HasHTM) 1440 .Case("bpermd", HasBPERMD) 1441 .Case("extdiv", HasExtDiv) 1442 .Case("float128", HasFloat128) 1443 .Default(false); 1444 } 1445 1446 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1447 StringRef Name, bool Enabled) const { 1448 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1449 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1450 // incompatible options. 1451 if (Enabled) { 1452 if (Name == "direct-move") { 1453 Features[Name] = Features["vsx"] = true; 1454 } else if (Name == "power8-vector") { 1455 Features[Name] = Features["vsx"] = true; 1456 } else if (Name == "float128") { 1457 Features[Name] = Features["vsx"] = true; 1458 } else { 1459 Features[Name] = true; 1460 } 1461 } else { 1462 if (Name == "vsx") { 1463 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1464 Features["float128"] = false; 1465 } else { 1466 Features[Name] = false; 1467 } 1468 } 1469 } 1470 1471 const char * const PPCTargetInfo::GCCRegNames[] = { 1472 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1473 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1474 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1475 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1476 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1477 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1478 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1479 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1480 "mq", "lr", "ctr", "ap", 1481 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1482 "xer", 1483 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1484 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1485 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1486 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1487 "vrsave", "vscr", 1488 "spe_acc", "spefscr", 1489 "sfp" 1490 }; 1491 1492 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1493 return llvm::makeArrayRef(GCCRegNames); 1494 } 1495 1496 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1497 // While some of these aliases do map to different registers 1498 // they still share the same register name. 1499 { { "0" }, "r0" }, 1500 { { "1"}, "r1" }, 1501 { { "2" }, "r2" }, 1502 { { "3" }, "r3" }, 1503 { { "4" }, "r4" }, 1504 { { "5" }, "r5" }, 1505 { { "6" }, "r6" }, 1506 { { "7" }, "r7" }, 1507 { { "8" }, "r8" }, 1508 { { "9" }, "r9" }, 1509 { { "10" }, "r10" }, 1510 { { "11" }, "r11" }, 1511 { { "12" }, "r12" }, 1512 { { "13" }, "r13" }, 1513 { { "14" }, "r14" }, 1514 { { "15" }, "r15" }, 1515 { { "16" }, "r16" }, 1516 { { "17" }, "r17" }, 1517 { { "18" }, "r18" }, 1518 { { "19" }, "r19" }, 1519 { { "20" }, "r20" }, 1520 { { "21" }, "r21" }, 1521 { { "22" }, "r22" }, 1522 { { "23" }, "r23" }, 1523 { { "24" }, "r24" }, 1524 { { "25" }, "r25" }, 1525 { { "26" }, "r26" }, 1526 { { "27" }, "r27" }, 1527 { { "28" }, "r28" }, 1528 { { "29" }, "r29" }, 1529 { { "30" }, "r30" }, 1530 { { "31" }, "r31" }, 1531 { { "fr0" }, "f0" }, 1532 { { "fr1" }, "f1" }, 1533 { { "fr2" }, "f2" }, 1534 { { "fr3" }, "f3" }, 1535 { { "fr4" }, "f4" }, 1536 { { "fr5" }, "f5" }, 1537 { { "fr6" }, "f6" }, 1538 { { "fr7" }, "f7" }, 1539 { { "fr8" }, "f8" }, 1540 { { "fr9" }, "f9" }, 1541 { { "fr10" }, "f10" }, 1542 { { "fr11" }, "f11" }, 1543 { { "fr12" }, "f12" }, 1544 { { "fr13" }, "f13" }, 1545 { { "fr14" }, "f14" }, 1546 { { "fr15" }, "f15" }, 1547 { { "fr16" }, "f16" }, 1548 { { "fr17" }, "f17" }, 1549 { { "fr18" }, "f18" }, 1550 { { "fr19" }, "f19" }, 1551 { { "fr20" }, "f20" }, 1552 { { "fr21" }, "f21" }, 1553 { { "fr22" }, "f22" }, 1554 { { "fr23" }, "f23" }, 1555 { { "fr24" }, "f24" }, 1556 { { "fr25" }, "f25" }, 1557 { { "fr26" }, "f26" }, 1558 { { "fr27" }, "f27" }, 1559 { { "fr28" }, "f28" }, 1560 { { "fr29" }, "f29" }, 1561 { { "fr30" }, "f30" }, 1562 { { "fr31" }, "f31" }, 1563 { { "cc" }, "cr0" }, 1564 }; 1565 1566 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1567 return llvm::makeArrayRef(GCCRegAliases); 1568 } 1569 1570 class PPC32TargetInfo : public PPCTargetInfo { 1571 public: 1572 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1573 : PPCTargetInfo(Triple, Opts) { 1574 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1575 1576 switch (getTriple().getOS()) { 1577 case llvm::Triple::Linux: 1578 case llvm::Triple::FreeBSD: 1579 case llvm::Triple::NetBSD: 1580 SizeType = UnsignedInt; 1581 PtrDiffType = SignedInt; 1582 IntPtrType = SignedInt; 1583 break; 1584 default: 1585 break; 1586 } 1587 1588 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1589 LongDoubleWidth = LongDoubleAlign = 64; 1590 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1591 } 1592 1593 // PPC32 supports atomics up to 4 bytes. 1594 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1595 } 1596 1597 BuiltinVaListKind getBuiltinVaListKind() const override { 1598 // This is the ELF definition, and is overridden by the Darwin sub-target 1599 return TargetInfo::PowerABIBuiltinVaList; 1600 } 1601 }; 1602 1603 // Note: ABI differences may eventually require us to have a separate 1604 // TargetInfo for little endian. 1605 class PPC64TargetInfo : public PPCTargetInfo { 1606 public: 1607 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1608 : PPCTargetInfo(Triple, Opts) { 1609 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1610 IntMaxType = SignedLong; 1611 Int64Type = SignedLong; 1612 1613 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1614 resetDataLayout("e-m:e-i64:64-n32:64"); 1615 ABI = "elfv2"; 1616 } else { 1617 resetDataLayout("E-m:e-i64:64-n32:64"); 1618 ABI = "elfv1"; 1619 } 1620 1621 switch (getTriple().getOS()) { 1622 case llvm::Triple::FreeBSD: 1623 LongDoubleWidth = LongDoubleAlign = 64; 1624 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1625 break; 1626 case llvm::Triple::NetBSD: 1627 IntMaxType = SignedLongLong; 1628 Int64Type = SignedLongLong; 1629 break; 1630 default: 1631 break; 1632 } 1633 1634 // PPC64 supports atomics up to 8 bytes. 1635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1636 } 1637 BuiltinVaListKind getBuiltinVaListKind() const override { 1638 return TargetInfo::CharPtrBuiltinVaList; 1639 } 1640 // PPC64 Linux-specific ABI options. 1641 bool setABI(const std::string &Name) override { 1642 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1643 ABI = Name; 1644 return true; 1645 } 1646 return false; 1647 } 1648 }; 1649 1650 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1651 public: 1652 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1653 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1654 HasAlignMac68kSupport = true; 1655 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1656 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1657 LongLongAlign = 32; 1658 SuitableAlign = 128; 1659 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1660 } 1661 BuiltinVaListKind getBuiltinVaListKind() const override { 1662 return TargetInfo::CharPtrBuiltinVaList; 1663 } 1664 }; 1665 1666 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1667 public: 1668 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1670 HasAlignMac68kSupport = true; 1671 SuitableAlign = 128; 1672 resetDataLayout("E-m:o-i64:64-n32:64"); 1673 } 1674 }; 1675 1676 static const unsigned NVPTXAddrSpaceMap[] = { 1677 1, // opencl_global 1678 3, // opencl_local 1679 4, // opencl_constant 1680 // FIXME: generic has to be added to the target 1681 0, // opencl_generic 1682 1, // cuda_device 1683 4, // cuda_constant 1684 3, // cuda_shared 1685 }; 1686 1687 class NVPTXTargetInfo : public TargetInfo { 1688 static const char *const GCCRegNames[]; 1689 static const Builtin::Info BuiltinInfo[]; 1690 1691 // The GPU profiles supported by the NVPTX backend 1692 enum GPUKind { 1693 GK_NONE, 1694 GK_SM20, 1695 GK_SM21, 1696 GK_SM30, 1697 GK_SM35, 1698 GK_SM37, 1699 GK_SM50, 1700 GK_SM52, 1701 GK_SM53, 1702 } GPU; 1703 1704 public: 1705 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1706 : TargetInfo(Triple) { 1707 BigEndian = false; 1708 TLSSupported = false; 1709 LongWidth = LongAlign = 64; 1710 AddrSpaceMap = &NVPTXAddrSpaceMap; 1711 UseAddrSpaceMapMangling = true; 1712 // Define available target features 1713 // These must be defined in sorted order! 1714 NoAsmVariants = true; 1715 // Set the default GPU to sm20 1716 GPU = GK_SM20; 1717 1718 // If possible, get a TargetInfo for our host triple, so we can match its 1719 // types. 1720 llvm::Triple HostTriple(Opts.HostTriple); 1721 if (HostTriple.isNVPTX()) 1722 return; 1723 std::unique_ptr<TargetInfo> HostTarget( 1724 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1725 if (!HostTarget) { 1726 return; 1727 } 1728 1729 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1730 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1731 BoolWidth = HostTarget->getBoolWidth(); 1732 BoolAlign = HostTarget->getBoolAlign(); 1733 IntWidth = HostTarget->getIntWidth(); 1734 IntAlign = HostTarget->getIntAlign(); 1735 HalfWidth = HostTarget->getHalfWidth(); 1736 HalfAlign = HostTarget->getHalfAlign(); 1737 FloatWidth = HostTarget->getFloatWidth(); 1738 FloatAlign = HostTarget->getFloatAlign(); 1739 DoubleWidth = HostTarget->getDoubleWidth(); 1740 DoubleAlign = HostTarget->getDoubleAlign(); 1741 LongWidth = HostTarget->getLongWidth(); 1742 LongAlign = HostTarget->getLongAlign(); 1743 LongLongWidth = HostTarget->getLongLongWidth(); 1744 LongLongAlign = HostTarget->getLongLongAlign(); 1745 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1746 DefaultAlignForAttributeAligned = 1747 HostTarget->getDefaultAlignForAttributeAligned(); 1748 SizeType = HostTarget->getSizeType(); 1749 IntMaxType = HostTarget->getIntMaxType(); 1750 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1751 IntPtrType = HostTarget->getIntPtrType(); 1752 WCharType = HostTarget->getWCharType(); 1753 WIntType = HostTarget->getWIntType(); 1754 Char16Type = HostTarget->getChar16Type(); 1755 Char32Type = HostTarget->getChar32Type(); 1756 Int64Type = HostTarget->getInt64Type(); 1757 SigAtomicType = HostTarget->getSigAtomicType(); 1758 ProcessIDType = HostTarget->getProcessIDType(); 1759 1760 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1761 UseZeroLengthBitfieldAlignment = 1762 HostTarget->useZeroLengthBitfieldAlignment(); 1763 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1764 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1765 1766 // Properties intentionally not copied from host: 1767 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1768 // host/device boundary. 1769 // - SuitableAlign: Not visible across the host/device boundary, and may 1770 // correctly be different on host/device, e.g. if host has wider vector 1771 // types than device. 1772 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1773 // as its double type, but that's not necessarily true on the host. 1774 // TODO: nvcc emits a warning when using long double on device; we should 1775 // do the same. 1776 } 1777 void getTargetDefines(const LangOptions &Opts, 1778 MacroBuilder &Builder) const override { 1779 Builder.defineMacro("__PTX__"); 1780 Builder.defineMacro("__NVPTX__"); 1781 if (Opts.CUDAIsDevice) { 1782 // Set __CUDA_ARCH__ for the GPU specified. 1783 std::string CUDAArchCode; 1784 switch (GPU) { 1785 case GK_SM20: 1786 CUDAArchCode = "200"; 1787 break; 1788 case GK_SM21: 1789 CUDAArchCode = "210"; 1790 break; 1791 case GK_SM30: 1792 CUDAArchCode = "300"; 1793 break; 1794 case GK_SM35: 1795 CUDAArchCode = "350"; 1796 break; 1797 case GK_SM37: 1798 CUDAArchCode = "370"; 1799 break; 1800 case GK_SM50: 1801 CUDAArchCode = "500"; 1802 break; 1803 case GK_SM52: 1804 CUDAArchCode = "520"; 1805 break; 1806 case GK_SM53: 1807 CUDAArchCode = "530"; 1808 break; 1809 default: 1810 llvm_unreachable("Unhandled target CPU"); 1811 } 1812 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1813 } 1814 } 1815 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1816 return llvm::makeArrayRef(BuiltinInfo, 1817 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1818 } 1819 bool hasFeature(StringRef Feature) const override { 1820 return Feature == "ptx" || Feature == "nvptx"; 1821 } 1822 1823 ArrayRef<const char *> getGCCRegNames() const override; 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 // No aliases. 1826 return None; 1827 } 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &Info) const override { 1830 switch (*Name) { 1831 default: 1832 return false; 1833 case 'c': 1834 case 'h': 1835 case 'r': 1836 case 'l': 1837 case 'f': 1838 case 'd': 1839 Info.setAllowsRegister(); 1840 return true; 1841 } 1842 } 1843 const char *getClobbers() const override { 1844 // FIXME: Is this really right? 1845 return ""; 1846 } 1847 BuiltinVaListKind getBuiltinVaListKind() const override { 1848 // FIXME: implement 1849 return TargetInfo::CharPtrBuiltinVaList; 1850 } 1851 bool setCPU(const std::string &Name) override { 1852 GPU = llvm::StringSwitch<GPUKind>(Name) 1853 .Case("sm_20", GK_SM20) 1854 .Case("sm_21", GK_SM21) 1855 .Case("sm_30", GK_SM30) 1856 .Case("sm_35", GK_SM35) 1857 .Case("sm_37", GK_SM37) 1858 .Case("sm_50", GK_SM50) 1859 .Case("sm_52", GK_SM52) 1860 .Case("sm_53", GK_SM53) 1861 .Default(GK_NONE); 1862 1863 return GPU != GK_NONE; 1864 } 1865 }; 1866 1867 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1868 #define BUILTIN(ID, TYPE, ATTRS) \ 1869 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1870 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1871 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1872 #include "clang/Basic/BuiltinsNVPTX.def" 1873 }; 1874 1875 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1876 1877 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1878 return llvm::makeArrayRef(GCCRegNames); 1879 } 1880 1881 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1882 public: 1883 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1884 : NVPTXTargetInfo(Triple, Opts) { 1885 LongWidth = LongAlign = 32; 1886 PointerWidth = PointerAlign = 32; 1887 SizeType = TargetInfo::UnsignedInt; 1888 PtrDiffType = TargetInfo::SignedInt; 1889 IntPtrType = TargetInfo::SignedInt; 1890 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1891 } 1892 }; 1893 1894 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1895 public: 1896 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1897 : NVPTXTargetInfo(Triple, Opts) { 1898 PointerWidth = PointerAlign = 64; 1899 SizeType = TargetInfo::UnsignedLong; 1900 PtrDiffType = TargetInfo::SignedLong; 1901 IntPtrType = TargetInfo::SignedLong; 1902 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1903 } 1904 }; 1905 1906 static const unsigned AMDGPUAddrSpaceMap[] = { 1907 1, // opencl_global 1908 3, // opencl_local 1909 2, // opencl_constant 1910 4, // opencl_generic 1911 1, // cuda_device 1912 2, // cuda_constant 1913 3 // cuda_shared 1914 }; 1915 1916 // If you edit the description strings, make sure you update 1917 // getPointerWidthV(). 1918 1919 static const char *const DataLayoutStringR600 = 1920 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1921 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1922 1923 static const char *const DataLayoutStringSI = 1924 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1925 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1926 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1927 1928 class AMDGPUTargetInfo : public TargetInfo { 1929 static const Builtin::Info BuiltinInfo[]; 1930 static const char * const GCCRegNames[]; 1931 1932 /// \brief The GPU profiles supported by the AMDGPU target. 1933 enum GPUKind { 1934 GK_NONE, 1935 GK_R600, 1936 GK_R600_DOUBLE_OPS, 1937 GK_R700, 1938 GK_R700_DOUBLE_OPS, 1939 GK_EVERGREEN, 1940 GK_EVERGREEN_DOUBLE_OPS, 1941 GK_NORTHERN_ISLANDS, 1942 GK_CAYMAN, 1943 GK_SOUTHERN_ISLANDS, 1944 GK_SEA_ISLANDS, 1945 GK_VOLCANIC_ISLANDS 1946 } GPU; 1947 1948 bool hasFP64:1; 1949 bool hasFMAF:1; 1950 bool hasLDEXPF:1; 1951 1952 public: 1953 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 1954 : TargetInfo(Triple) { 1955 if (Triple.getArch() == llvm::Triple::amdgcn) { 1956 resetDataLayout(DataLayoutStringSI); 1957 GPU = GK_SOUTHERN_ISLANDS; 1958 hasFP64 = true; 1959 hasFMAF = true; 1960 hasLDEXPF = true; 1961 } else { 1962 resetDataLayout(DataLayoutStringR600); 1963 GPU = GK_R600; 1964 hasFP64 = false; 1965 hasFMAF = false; 1966 hasLDEXPF = false; 1967 } 1968 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1969 UseAddrSpaceMapMangling = true; 1970 } 1971 1972 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1973 if (GPU <= GK_CAYMAN) 1974 return 32; 1975 1976 switch(AddrSpace) { 1977 default: 1978 return 64; 1979 case 0: 1980 case 3: 1981 case 5: 1982 return 32; 1983 } 1984 } 1985 1986 const char * getClobbers() const override { 1987 return ""; 1988 } 1989 1990 ArrayRef<const char *> getGCCRegNames() const override; 1991 1992 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1993 return None; 1994 } 1995 1996 bool validateAsmConstraint(const char *&Name, 1997 TargetInfo::ConstraintInfo &Info) const override { 1998 switch (*Name) { 1999 default: break; 2000 case 'v': // vgpr 2001 case 's': // sgpr 2002 Info.setAllowsRegister(); 2003 return true; 2004 } 2005 return false; 2006 } 2007 2008 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2009 return llvm::makeArrayRef(BuiltinInfo, 2010 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2011 } 2012 2013 void getTargetDefines(const LangOptions &Opts, 2014 MacroBuilder &Builder) const override { 2015 if (getTriple().getArch() == llvm::Triple::amdgcn) 2016 Builder.defineMacro("__AMDGCN__"); 2017 else 2018 Builder.defineMacro("__R600__"); 2019 2020 if (hasFMAF) 2021 Builder.defineMacro("__HAS_FMAF__"); 2022 if (hasLDEXPF) 2023 Builder.defineMacro("__HAS_LDEXPF__"); 2024 } 2025 2026 BuiltinVaListKind getBuiltinVaListKind() const override { 2027 return TargetInfo::CharPtrBuiltinVaList; 2028 } 2029 2030 bool setCPU(const std::string &Name) override { 2031 GPU = llvm::StringSwitch<GPUKind>(Name) 2032 .Case("r600" , GK_R600) 2033 .Case("rv610", GK_R600) 2034 .Case("rv620", GK_R600) 2035 .Case("rv630", GK_R600) 2036 .Case("rv635", GK_R600) 2037 .Case("rs780", GK_R600) 2038 .Case("rs880", GK_R600) 2039 .Case("rv670", GK_R600_DOUBLE_OPS) 2040 .Case("rv710", GK_R700) 2041 .Case("rv730", GK_R700) 2042 .Case("rv740", GK_R700_DOUBLE_OPS) 2043 .Case("rv770", GK_R700_DOUBLE_OPS) 2044 .Case("palm", GK_EVERGREEN) 2045 .Case("cedar", GK_EVERGREEN) 2046 .Case("sumo", GK_EVERGREEN) 2047 .Case("sumo2", GK_EVERGREEN) 2048 .Case("redwood", GK_EVERGREEN) 2049 .Case("juniper", GK_EVERGREEN) 2050 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2051 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2052 .Case("barts", GK_NORTHERN_ISLANDS) 2053 .Case("turks", GK_NORTHERN_ISLANDS) 2054 .Case("caicos", GK_NORTHERN_ISLANDS) 2055 .Case("cayman", GK_CAYMAN) 2056 .Case("aruba", GK_CAYMAN) 2057 .Case("tahiti", GK_SOUTHERN_ISLANDS) 2058 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 2059 .Case("verde", GK_SOUTHERN_ISLANDS) 2060 .Case("oland", GK_SOUTHERN_ISLANDS) 2061 .Case("hainan", GK_SOUTHERN_ISLANDS) 2062 .Case("bonaire", GK_SEA_ISLANDS) 2063 .Case("kabini", GK_SEA_ISLANDS) 2064 .Case("kaveri", GK_SEA_ISLANDS) 2065 .Case("hawaii", GK_SEA_ISLANDS) 2066 .Case("mullins", GK_SEA_ISLANDS) 2067 .Case("tonga", GK_VOLCANIC_ISLANDS) 2068 .Case("iceland", GK_VOLCANIC_ISLANDS) 2069 .Case("carrizo", GK_VOLCANIC_ISLANDS) 2070 .Case("fiji", GK_VOLCANIC_ISLANDS) 2071 .Case("stoney", GK_VOLCANIC_ISLANDS) 2072 .Default(GK_NONE); 2073 2074 if (GPU == GK_NONE) { 2075 return false; 2076 } 2077 2078 // Set the correct data layout 2079 switch (GPU) { 2080 case GK_NONE: 2081 case GK_R600: 2082 case GK_R700: 2083 case GK_EVERGREEN: 2084 case GK_NORTHERN_ISLANDS: 2085 resetDataLayout(DataLayoutStringR600); 2086 hasFP64 = false; 2087 hasFMAF = false; 2088 hasLDEXPF = false; 2089 break; 2090 case GK_R600_DOUBLE_OPS: 2091 case GK_R700_DOUBLE_OPS: 2092 case GK_EVERGREEN_DOUBLE_OPS: 2093 case GK_CAYMAN: 2094 resetDataLayout(DataLayoutStringR600); 2095 hasFP64 = true; 2096 hasFMAF = true; 2097 hasLDEXPF = false; 2098 break; 2099 case GK_SOUTHERN_ISLANDS: 2100 case GK_SEA_ISLANDS: 2101 case GK_VOLCANIC_ISLANDS: 2102 resetDataLayout(DataLayoutStringSI); 2103 hasFP64 = true; 2104 hasFMAF = true; 2105 hasLDEXPF = true; 2106 break; 2107 } 2108 2109 return true; 2110 } 2111 2112 void setSupportedOpenCLOpts() override { 2113 auto &Opts = getSupportedOpenCLOpts(); 2114 Opts.cl_clang_storage_class_specifiers = 1; 2115 Opts.cl_khr_gl_sharing = 1; 2116 Opts.cl_khr_gl_event = 1; 2117 Opts.cl_khr_d3d10_sharing = 1; 2118 Opts.cl_khr_subgroups = 1; 2119 2120 if (hasFP64) 2121 Opts.cl_khr_fp64 = 1; 2122 if (GPU >= GK_NORTHERN_ISLANDS) { 2123 Opts.cl_khr_byte_addressable_store = 1; 2124 Opts.cl_khr_global_int32_base_atomics = 1; 2125 Opts.cl_khr_global_int32_extended_atomics = 1; 2126 Opts.cl_khr_local_int32_base_atomics = 1; 2127 Opts.cl_khr_local_int32_extended_atomics = 1; 2128 } 2129 if (GPU >= GK_SOUTHERN_ISLANDS) 2130 Opts.cl_khr_fp16 = 1; 2131 Opts.cl_khr_int64_base_atomics = 1; 2132 Opts.cl_khr_int64_extended_atomics = 1; 2133 Opts.cl_khr_3d_image_writes = 1; 2134 Opts.cl_khr_gl_msaa_sharing = 1; 2135 } 2136 }; 2137 2138 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2139 #define BUILTIN(ID, TYPE, ATTRS) \ 2140 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2141 #include "clang/Basic/BuiltinsAMDGPU.def" 2142 }; 2143 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2144 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2145 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2146 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2147 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2148 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2149 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2150 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2151 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2152 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2153 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2154 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2155 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2156 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2157 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2158 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2159 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2160 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2161 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2162 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2163 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2164 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2165 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2166 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2167 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2168 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2169 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2170 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2171 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2172 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2173 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2174 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2175 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2176 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2177 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2178 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2179 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2180 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2181 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2182 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2183 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2184 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2185 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2186 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2187 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2188 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2189 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2190 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2191 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2192 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2193 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2194 }; 2195 2196 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2197 return llvm::makeArrayRef(GCCRegNames); 2198 } 2199 2200 // Namespace for x86 abstract base class 2201 const Builtin::Info BuiltinInfo[] = { 2202 #define BUILTIN(ID, TYPE, ATTRS) \ 2203 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2204 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2205 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2206 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2207 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2208 #include "clang/Basic/BuiltinsX86.def" 2209 }; 2210 2211 static const char* const GCCRegNames[] = { 2212 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2213 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2214 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2215 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2216 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2217 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2218 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2219 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2220 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2221 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2222 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2223 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2224 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2225 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2226 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2227 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2228 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2229 }; 2230 2231 const TargetInfo::AddlRegName AddlRegNames[] = { 2232 { { "al", "ah", "eax", "rax" }, 0 }, 2233 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2234 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2235 { { "dl", "dh", "edx", "rdx" }, 1 }, 2236 { { "esi", "rsi" }, 4 }, 2237 { { "edi", "rdi" }, 5 }, 2238 { { "esp", "rsp" }, 7 }, 2239 { { "ebp", "rbp" }, 6 }, 2240 { { "r8d", "r8w", "r8b" }, 38 }, 2241 { { "r9d", "r9w", "r9b" }, 39 }, 2242 { { "r10d", "r10w", "r10b" }, 40 }, 2243 { { "r11d", "r11w", "r11b" }, 41 }, 2244 { { "r12d", "r12w", "r12b" }, 42 }, 2245 { { "r13d", "r13w", "r13b" }, 43 }, 2246 { { "r14d", "r14w", "r14b" }, 44 }, 2247 { { "r15d", "r15w", "r15b" }, 45 }, 2248 }; 2249 2250 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2251 // most of the implementation can be shared. 2252 class X86TargetInfo : public TargetInfo { 2253 enum X86SSEEnum { 2254 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2255 } SSELevel = NoSSE; 2256 enum MMX3DNowEnum { 2257 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2258 } MMX3DNowLevel = NoMMX3DNow; 2259 enum XOPEnum { 2260 NoXOP, 2261 SSE4A, 2262 FMA4, 2263 XOP 2264 } XOPLevel = NoXOP; 2265 2266 bool HasAES = false; 2267 bool HasPCLMUL = false; 2268 bool HasLZCNT = false; 2269 bool HasRDRND = false; 2270 bool HasFSGSBASE = false; 2271 bool HasBMI = false; 2272 bool HasBMI2 = false; 2273 bool HasPOPCNT = false; 2274 bool HasRTM = false; 2275 bool HasPRFCHW = false; 2276 bool HasRDSEED = false; 2277 bool HasADX = false; 2278 bool HasTBM = false; 2279 bool HasFMA = false; 2280 bool HasF16C = false; 2281 bool HasAVX512CD = false; 2282 bool HasAVX512ER = false; 2283 bool HasAVX512PF = false; 2284 bool HasAVX512DQ = false; 2285 bool HasAVX512BW = false; 2286 bool HasAVX512VL = false; 2287 bool HasAVX512VBMI = false; 2288 bool HasAVX512IFMA = false; 2289 bool HasSHA = false; 2290 bool HasMPX = false; 2291 bool HasSGX = false; 2292 bool HasCX16 = false; 2293 bool HasFXSR = false; 2294 bool HasXSAVE = false; 2295 bool HasXSAVEOPT = false; 2296 bool HasXSAVEC = false; 2297 bool HasXSAVES = false; 2298 bool HasMWAITX = false; 2299 bool HasPKU = false; 2300 bool HasCLFLUSHOPT = false; 2301 bool HasPCOMMIT = false; 2302 bool HasCLWB = false; 2303 bool HasUMIP = false; 2304 bool HasMOVBE = false; 2305 bool HasPREFETCHWT1 = false; 2306 2307 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2308 /// 2309 /// Each enumeration represents a particular CPU supported by Clang. These 2310 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2311 enum CPUKind { 2312 CK_Generic, 2313 2314 /// \name i386 2315 /// i386-generation processors. 2316 //@{ 2317 CK_i386, 2318 //@} 2319 2320 /// \name i486 2321 /// i486-generation processors. 2322 //@{ 2323 CK_i486, 2324 CK_WinChipC6, 2325 CK_WinChip2, 2326 CK_C3, 2327 //@} 2328 2329 /// \name i586 2330 /// i586-generation processors, P5 microarchitecture based. 2331 //@{ 2332 CK_i586, 2333 CK_Pentium, 2334 CK_PentiumMMX, 2335 //@} 2336 2337 /// \name i686 2338 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2339 //@{ 2340 CK_i686, 2341 CK_PentiumPro, 2342 CK_Pentium2, 2343 CK_Pentium3, 2344 CK_Pentium3M, 2345 CK_PentiumM, 2346 CK_C3_2, 2347 2348 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2349 /// Clang however has some logic to suport this. 2350 // FIXME: Warn, deprecate, and potentially remove this. 2351 CK_Yonah, 2352 //@} 2353 2354 /// \name Netburst 2355 /// Netburst microarchitecture based processors. 2356 //@{ 2357 CK_Pentium4, 2358 CK_Pentium4M, 2359 CK_Prescott, 2360 CK_Nocona, 2361 //@} 2362 2363 /// \name Core 2364 /// Core microarchitecture based processors. 2365 //@{ 2366 CK_Core2, 2367 2368 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2369 /// codename which GCC no longer accepts as an option to -march, but Clang 2370 /// has some logic for recognizing it. 2371 // FIXME: Warn, deprecate, and potentially remove this. 2372 CK_Penryn, 2373 //@} 2374 2375 /// \name Atom 2376 /// Atom processors 2377 //@{ 2378 CK_Bonnell, 2379 CK_Silvermont, 2380 //@} 2381 2382 /// \name Nehalem 2383 /// Nehalem microarchitecture based processors. 2384 CK_Nehalem, 2385 2386 /// \name Westmere 2387 /// Westmere microarchitecture based processors. 2388 CK_Westmere, 2389 2390 /// \name Sandy Bridge 2391 /// Sandy Bridge microarchitecture based processors. 2392 CK_SandyBridge, 2393 2394 /// \name Ivy Bridge 2395 /// Ivy Bridge microarchitecture based processors. 2396 CK_IvyBridge, 2397 2398 /// \name Haswell 2399 /// Haswell microarchitecture based processors. 2400 CK_Haswell, 2401 2402 /// \name Broadwell 2403 /// Broadwell microarchitecture based processors. 2404 CK_Broadwell, 2405 2406 /// \name Skylake Client 2407 /// Skylake client microarchitecture based processors. 2408 CK_SkylakeClient, 2409 2410 /// \name Skylake Server 2411 /// Skylake server microarchitecture based processors. 2412 CK_SkylakeServer, 2413 2414 /// \name Cannonlake Client 2415 /// Cannonlake client microarchitecture based processors. 2416 CK_Cannonlake, 2417 2418 /// \name Knights Landing 2419 /// Knights Landing processor. 2420 CK_KNL, 2421 2422 /// \name Lakemont 2423 /// Lakemont microarchitecture based processors. 2424 CK_Lakemont, 2425 2426 /// \name K6 2427 /// K6 architecture processors. 2428 //@{ 2429 CK_K6, 2430 CK_K6_2, 2431 CK_K6_3, 2432 //@} 2433 2434 /// \name K7 2435 /// K7 architecture processors. 2436 //@{ 2437 CK_Athlon, 2438 CK_AthlonThunderbird, 2439 CK_Athlon4, 2440 CK_AthlonXP, 2441 CK_AthlonMP, 2442 //@} 2443 2444 /// \name K8 2445 /// K8 architecture processors. 2446 //@{ 2447 CK_Athlon64, 2448 CK_Athlon64SSE3, 2449 CK_AthlonFX, 2450 CK_K8, 2451 CK_K8SSE3, 2452 CK_Opteron, 2453 CK_OpteronSSE3, 2454 CK_AMDFAM10, 2455 //@} 2456 2457 /// \name Bobcat 2458 /// Bobcat architecture processors. 2459 //@{ 2460 CK_BTVER1, 2461 CK_BTVER2, 2462 //@} 2463 2464 /// \name Bulldozer 2465 /// Bulldozer architecture processors. 2466 //@{ 2467 CK_BDVER1, 2468 CK_BDVER2, 2469 CK_BDVER3, 2470 CK_BDVER4, 2471 //@} 2472 2473 /// This specification is deprecated and will be removed in the future. 2474 /// Users should prefer \see CK_K8. 2475 // FIXME: Warn on this when the CPU is set to it. 2476 //@{ 2477 CK_x86_64, 2478 //@} 2479 2480 /// \name Geode 2481 /// Geode processors. 2482 //@{ 2483 CK_Geode 2484 //@} 2485 } CPU = CK_Generic; 2486 2487 CPUKind getCPUKind(StringRef CPU) const { 2488 return llvm::StringSwitch<CPUKind>(CPU) 2489 .Case("i386", CK_i386) 2490 .Case("i486", CK_i486) 2491 .Case("winchip-c6", CK_WinChipC6) 2492 .Case("winchip2", CK_WinChip2) 2493 .Case("c3", CK_C3) 2494 .Case("i586", CK_i586) 2495 .Case("pentium", CK_Pentium) 2496 .Case("pentium-mmx", CK_PentiumMMX) 2497 .Case("i686", CK_i686) 2498 .Case("pentiumpro", CK_PentiumPro) 2499 .Case("pentium2", CK_Pentium2) 2500 .Case("pentium3", CK_Pentium3) 2501 .Case("pentium3m", CK_Pentium3M) 2502 .Case("pentium-m", CK_PentiumM) 2503 .Case("c3-2", CK_C3_2) 2504 .Case("yonah", CK_Yonah) 2505 .Case("pentium4", CK_Pentium4) 2506 .Case("pentium4m", CK_Pentium4M) 2507 .Case("prescott", CK_Prescott) 2508 .Case("nocona", CK_Nocona) 2509 .Case("core2", CK_Core2) 2510 .Case("penryn", CK_Penryn) 2511 .Case("bonnell", CK_Bonnell) 2512 .Case("atom", CK_Bonnell) // Legacy name. 2513 .Case("silvermont", CK_Silvermont) 2514 .Case("slm", CK_Silvermont) // Legacy name. 2515 .Case("nehalem", CK_Nehalem) 2516 .Case("corei7", CK_Nehalem) // Legacy name. 2517 .Case("westmere", CK_Westmere) 2518 .Case("sandybridge", CK_SandyBridge) 2519 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2520 .Case("ivybridge", CK_IvyBridge) 2521 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2522 .Case("haswell", CK_Haswell) 2523 .Case("core-avx2", CK_Haswell) // Legacy name. 2524 .Case("broadwell", CK_Broadwell) 2525 .Case("skylake", CK_SkylakeClient) 2526 .Case("skylake-avx512", CK_SkylakeServer) 2527 .Case("skx", CK_SkylakeServer) // Legacy name. 2528 .Case("cannonlake", CK_Cannonlake) 2529 .Case("knl", CK_KNL) 2530 .Case("lakemont", CK_Lakemont) 2531 .Case("k6", CK_K6) 2532 .Case("k6-2", CK_K6_2) 2533 .Case("k6-3", CK_K6_3) 2534 .Case("athlon", CK_Athlon) 2535 .Case("athlon-tbird", CK_AthlonThunderbird) 2536 .Case("athlon-4", CK_Athlon4) 2537 .Case("athlon-xp", CK_AthlonXP) 2538 .Case("athlon-mp", CK_AthlonMP) 2539 .Case("athlon64", CK_Athlon64) 2540 .Case("athlon64-sse3", CK_Athlon64SSE3) 2541 .Case("athlon-fx", CK_AthlonFX) 2542 .Case("k8", CK_K8) 2543 .Case("k8-sse3", CK_K8SSE3) 2544 .Case("opteron", CK_Opteron) 2545 .Case("opteron-sse3", CK_OpteronSSE3) 2546 .Case("barcelona", CK_AMDFAM10) 2547 .Case("amdfam10", CK_AMDFAM10) 2548 .Case("btver1", CK_BTVER1) 2549 .Case("btver2", CK_BTVER2) 2550 .Case("bdver1", CK_BDVER1) 2551 .Case("bdver2", CK_BDVER2) 2552 .Case("bdver3", CK_BDVER3) 2553 .Case("bdver4", CK_BDVER4) 2554 .Case("x86-64", CK_x86_64) 2555 .Case("geode", CK_Geode) 2556 .Default(CK_Generic); 2557 } 2558 2559 enum FPMathKind { 2560 FP_Default, 2561 FP_SSE, 2562 FP_387 2563 } FPMath = FP_Default; 2564 2565 public: 2566 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2567 : TargetInfo(Triple) { 2568 BigEndian = false; 2569 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2570 } 2571 unsigned getFloatEvalMethod() const override { 2572 // X87 evaluates with 80 bits "long double" precision. 2573 return SSELevel == NoSSE ? 2 : 0; 2574 } 2575 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2576 return llvm::makeArrayRef(BuiltinInfo, 2577 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2578 } 2579 ArrayRef<const char *> getGCCRegNames() const override { 2580 return llvm::makeArrayRef(GCCRegNames); 2581 } 2582 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2583 return None; 2584 } 2585 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2586 return llvm::makeArrayRef(AddlRegNames); 2587 } 2588 bool validateCpuSupports(StringRef Name) const override; 2589 bool validateAsmConstraint(const char *&Name, 2590 TargetInfo::ConstraintInfo &info) const override; 2591 2592 bool validateGlobalRegisterVariable(StringRef RegName, 2593 unsigned RegSize, 2594 bool &HasSizeMismatch) const override { 2595 // esp and ebp are the only 32-bit registers the x86 backend can currently 2596 // handle. 2597 if (RegName.equals("esp") || RegName.equals("ebp")) { 2598 // Check that the register size is 32-bit. 2599 HasSizeMismatch = RegSize != 32; 2600 return true; 2601 } 2602 2603 return false; 2604 } 2605 2606 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2607 2608 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2609 2610 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2611 2612 std::string convertConstraint(const char *&Constraint) const override; 2613 const char *getClobbers() const override { 2614 return "~{dirflag},~{fpsr},~{flags}"; 2615 } 2616 void getTargetDefines(const LangOptions &Opts, 2617 MacroBuilder &Builder) const override; 2618 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2619 bool Enabled); 2620 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2621 bool Enabled); 2622 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2623 bool Enabled); 2624 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2625 StringRef Name, bool Enabled) const override { 2626 setFeatureEnabledImpl(Features, Name, Enabled); 2627 } 2628 // This exists purely to cut down on the number of virtual calls in 2629 // initFeatureMap which calls this repeatedly. 2630 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2631 StringRef Name, bool Enabled); 2632 bool 2633 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2634 StringRef CPU, 2635 const std::vector<std::string> &FeaturesVec) const override; 2636 bool hasFeature(StringRef Feature) const override; 2637 bool handleTargetFeatures(std::vector<std::string> &Features, 2638 DiagnosticsEngine &Diags) override; 2639 StringRef getABI() const override { 2640 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2641 return "avx512"; 2642 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2643 return "avx"; 2644 if (getTriple().getArch() == llvm::Triple::x86 && 2645 MMX3DNowLevel == NoMMX3DNow) 2646 return "no-mmx"; 2647 return ""; 2648 } 2649 bool setCPU(const std::string &Name) override { 2650 CPU = getCPUKind(Name); 2651 2652 // Perform any per-CPU checks necessary to determine if this CPU is 2653 // acceptable. 2654 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2655 // invalid without explaining *why*. 2656 switch (CPU) { 2657 case CK_Generic: 2658 // No processor selected! 2659 return false; 2660 2661 case CK_i386: 2662 case CK_i486: 2663 case CK_WinChipC6: 2664 case CK_WinChip2: 2665 case CK_C3: 2666 case CK_i586: 2667 case CK_Pentium: 2668 case CK_PentiumMMX: 2669 case CK_i686: 2670 case CK_PentiumPro: 2671 case CK_Pentium2: 2672 case CK_Pentium3: 2673 case CK_Pentium3M: 2674 case CK_PentiumM: 2675 case CK_Yonah: 2676 case CK_C3_2: 2677 case CK_Pentium4: 2678 case CK_Pentium4M: 2679 case CK_Lakemont: 2680 case CK_Prescott: 2681 case CK_K6: 2682 case CK_K6_2: 2683 case CK_K6_3: 2684 case CK_Athlon: 2685 case CK_AthlonThunderbird: 2686 case CK_Athlon4: 2687 case CK_AthlonXP: 2688 case CK_AthlonMP: 2689 case CK_Geode: 2690 // Only accept certain architectures when compiling in 32-bit mode. 2691 if (getTriple().getArch() != llvm::Triple::x86) 2692 return false; 2693 2694 // Fallthrough 2695 case CK_Nocona: 2696 case CK_Core2: 2697 case CK_Penryn: 2698 case CK_Bonnell: 2699 case CK_Silvermont: 2700 case CK_Nehalem: 2701 case CK_Westmere: 2702 case CK_SandyBridge: 2703 case CK_IvyBridge: 2704 case CK_Haswell: 2705 case CK_Broadwell: 2706 case CK_SkylakeClient: 2707 case CK_SkylakeServer: 2708 case CK_Cannonlake: 2709 case CK_KNL: 2710 case CK_Athlon64: 2711 case CK_Athlon64SSE3: 2712 case CK_AthlonFX: 2713 case CK_K8: 2714 case CK_K8SSE3: 2715 case CK_Opteron: 2716 case CK_OpteronSSE3: 2717 case CK_AMDFAM10: 2718 case CK_BTVER1: 2719 case CK_BTVER2: 2720 case CK_BDVER1: 2721 case CK_BDVER2: 2722 case CK_BDVER3: 2723 case CK_BDVER4: 2724 case CK_x86_64: 2725 return true; 2726 } 2727 llvm_unreachable("Unhandled CPU kind"); 2728 } 2729 2730 bool setFPMath(StringRef Name) override; 2731 2732 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2733 // Most of the non-ARM calling conventions are i386 conventions. 2734 switch (CC) { 2735 case CC_X86ThisCall: 2736 case CC_X86FastCall: 2737 case CC_X86StdCall: 2738 case CC_X86VectorCall: 2739 case CC_C: 2740 case CC_Swift: 2741 case CC_X86Pascal: 2742 case CC_IntelOclBicc: 2743 return CCCR_OK; 2744 default: 2745 return CCCR_Warning; 2746 } 2747 } 2748 2749 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2750 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2751 } 2752 2753 bool hasSjLjLowering() const override { 2754 return true; 2755 } 2756 2757 void setSupportedOpenCLOpts() override { 2758 getSupportedOpenCLOpts().setAll(); 2759 } 2760 }; 2761 2762 bool X86TargetInfo::setFPMath(StringRef Name) { 2763 if (Name == "387") { 2764 FPMath = FP_387; 2765 return true; 2766 } 2767 if (Name == "sse") { 2768 FPMath = FP_SSE; 2769 return true; 2770 } 2771 return false; 2772 } 2773 2774 bool X86TargetInfo::initFeatureMap( 2775 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2776 const std::vector<std::string> &FeaturesVec) const { 2777 // FIXME: This *really* should not be here. 2778 // X86_64 always has SSE2. 2779 if (getTriple().getArch() == llvm::Triple::x86_64) 2780 setFeatureEnabledImpl(Features, "sse2", true); 2781 2782 const CPUKind Kind = getCPUKind(CPU); 2783 2784 // Enable X87 for all X86 processors but Lakemont. 2785 if (Kind != CK_Lakemont) 2786 setFeatureEnabledImpl(Features, "x87", true); 2787 2788 switch (Kind) { 2789 case CK_Generic: 2790 case CK_i386: 2791 case CK_i486: 2792 case CK_i586: 2793 case CK_Pentium: 2794 case CK_i686: 2795 case CK_PentiumPro: 2796 case CK_Lakemont: 2797 break; 2798 case CK_PentiumMMX: 2799 case CK_Pentium2: 2800 case CK_K6: 2801 case CK_WinChipC6: 2802 setFeatureEnabledImpl(Features, "mmx", true); 2803 break; 2804 case CK_Pentium3: 2805 case CK_Pentium3M: 2806 case CK_C3_2: 2807 setFeatureEnabledImpl(Features, "sse", true); 2808 setFeatureEnabledImpl(Features, "fxsr", true); 2809 break; 2810 case CK_PentiumM: 2811 case CK_Pentium4: 2812 case CK_Pentium4M: 2813 case CK_x86_64: 2814 setFeatureEnabledImpl(Features, "sse2", true); 2815 setFeatureEnabledImpl(Features, "fxsr", true); 2816 break; 2817 case CK_Yonah: 2818 case CK_Prescott: 2819 case CK_Nocona: 2820 setFeatureEnabledImpl(Features, "sse3", true); 2821 setFeatureEnabledImpl(Features, "fxsr", true); 2822 setFeatureEnabledImpl(Features, "cx16", true); 2823 break; 2824 case CK_Core2: 2825 case CK_Bonnell: 2826 setFeatureEnabledImpl(Features, "ssse3", true); 2827 setFeatureEnabledImpl(Features, "fxsr", true); 2828 setFeatureEnabledImpl(Features, "cx16", true); 2829 break; 2830 case CK_Penryn: 2831 setFeatureEnabledImpl(Features, "sse4.1", true); 2832 setFeatureEnabledImpl(Features, "fxsr", true); 2833 setFeatureEnabledImpl(Features, "cx16", true); 2834 break; 2835 case CK_Cannonlake: 2836 setFeatureEnabledImpl(Features, "avx512ifma", true); 2837 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2838 setFeatureEnabledImpl(Features, "sha", true); 2839 setFeatureEnabledImpl(Features, "umip", true); 2840 // FALLTHROUGH 2841 case CK_SkylakeServer: 2842 setFeatureEnabledImpl(Features, "avx512f", true); 2843 setFeatureEnabledImpl(Features, "avx512cd", true); 2844 setFeatureEnabledImpl(Features, "avx512dq", true); 2845 setFeatureEnabledImpl(Features, "avx512bw", true); 2846 setFeatureEnabledImpl(Features, "avx512vl", true); 2847 setFeatureEnabledImpl(Features, "pku", true); 2848 setFeatureEnabledImpl(Features, "pcommit", true); 2849 setFeatureEnabledImpl(Features, "clwb", true); 2850 // FALLTHROUGH 2851 case CK_SkylakeClient: 2852 setFeatureEnabledImpl(Features, "xsavec", true); 2853 setFeatureEnabledImpl(Features, "xsaves", true); 2854 setFeatureEnabledImpl(Features, "mpx", true); 2855 setFeatureEnabledImpl(Features, "sgx", true); 2856 setFeatureEnabledImpl(Features, "clflushopt", true); 2857 // FALLTHROUGH 2858 case CK_Broadwell: 2859 setFeatureEnabledImpl(Features, "rdseed", true); 2860 setFeatureEnabledImpl(Features, "adx", true); 2861 // FALLTHROUGH 2862 case CK_Haswell: 2863 setFeatureEnabledImpl(Features, "avx2", true); 2864 setFeatureEnabledImpl(Features, "lzcnt", true); 2865 setFeatureEnabledImpl(Features, "bmi", true); 2866 setFeatureEnabledImpl(Features, "bmi2", true); 2867 setFeatureEnabledImpl(Features, "rtm", true); 2868 setFeatureEnabledImpl(Features, "fma", true); 2869 setFeatureEnabledImpl(Features, "movbe", true); 2870 // FALLTHROUGH 2871 case CK_IvyBridge: 2872 setFeatureEnabledImpl(Features, "rdrnd", true); 2873 setFeatureEnabledImpl(Features, "f16c", true); 2874 setFeatureEnabledImpl(Features, "fsgsbase", true); 2875 // FALLTHROUGH 2876 case CK_SandyBridge: 2877 setFeatureEnabledImpl(Features, "avx", true); 2878 setFeatureEnabledImpl(Features, "xsave", true); 2879 setFeatureEnabledImpl(Features, "xsaveopt", true); 2880 // FALLTHROUGH 2881 case CK_Westmere: 2882 case CK_Silvermont: 2883 setFeatureEnabledImpl(Features, "aes", true); 2884 setFeatureEnabledImpl(Features, "pclmul", true); 2885 // FALLTHROUGH 2886 case CK_Nehalem: 2887 setFeatureEnabledImpl(Features, "sse4.2", true); 2888 setFeatureEnabledImpl(Features, "fxsr", true); 2889 setFeatureEnabledImpl(Features, "cx16", true); 2890 break; 2891 case CK_KNL: 2892 setFeatureEnabledImpl(Features, "avx512f", true); 2893 setFeatureEnabledImpl(Features, "avx512cd", true); 2894 setFeatureEnabledImpl(Features, "avx512er", true); 2895 setFeatureEnabledImpl(Features, "avx512pf", true); 2896 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2897 setFeatureEnabledImpl(Features, "fxsr", true); 2898 setFeatureEnabledImpl(Features, "rdseed", true); 2899 setFeatureEnabledImpl(Features, "adx", true); 2900 setFeatureEnabledImpl(Features, "lzcnt", true); 2901 setFeatureEnabledImpl(Features, "bmi", true); 2902 setFeatureEnabledImpl(Features, "bmi2", true); 2903 setFeatureEnabledImpl(Features, "rtm", true); 2904 setFeatureEnabledImpl(Features, "fma", true); 2905 setFeatureEnabledImpl(Features, "rdrnd", true); 2906 setFeatureEnabledImpl(Features, "f16c", true); 2907 setFeatureEnabledImpl(Features, "fsgsbase", true); 2908 setFeatureEnabledImpl(Features, "aes", true); 2909 setFeatureEnabledImpl(Features, "pclmul", true); 2910 setFeatureEnabledImpl(Features, "cx16", true); 2911 setFeatureEnabledImpl(Features, "xsaveopt", true); 2912 setFeatureEnabledImpl(Features, "xsave", true); 2913 setFeatureEnabledImpl(Features, "movbe", true); 2914 break; 2915 case CK_K6_2: 2916 case CK_K6_3: 2917 case CK_WinChip2: 2918 case CK_C3: 2919 setFeatureEnabledImpl(Features, "3dnow", true); 2920 break; 2921 case CK_Athlon: 2922 case CK_AthlonThunderbird: 2923 case CK_Geode: 2924 setFeatureEnabledImpl(Features, "3dnowa", true); 2925 break; 2926 case CK_Athlon4: 2927 case CK_AthlonXP: 2928 case CK_AthlonMP: 2929 setFeatureEnabledImpl(Features, "sse", true); 2930 setFeatureEnabledImpl(Features, "3dnowa", true); 2931 setFeatureEnabledImpl(Features, "fxsr", true); 2932 break; 2933 case CK_K8: 2934 case CK_Opteron: 2935 case CK_Athlon64: 2936 case CK_AthlonFX: 2937 setFeatureEnabledImpl(Features, "sse2", true); 2938 setFeatureEnabledImpl(Features, "3dnowa", true); 2939 setFeatureEnabledImpl(Features, "fxsr", true); 2940 break; 2941 case CK_AMDFAM10: 2942 setFeatureEnabledImpl(Features, "sse4a", true); 2943 setFeatureEnabledImpl(Features, "lzcnt", true); 2944 setFeatureEnabledImpl(Features, "popcnt", true); 2945 // FALLTHROUGH 2946 case CK_K8SSE3: 2947 case CK_OpteronSSE3: 2948 case CK_Athlon64SSE3: 2949 setFeatureEnabledImpl(Features, "sse3", true); 2950 setFeatureEnabledImpl(Features, "3dnowa", true); 2951 setFeatureEnabledImpl(Features, "fxsr", true); 2952 break; 2953 case CK_BTVER2: 2954 setFeatureEnabledImpl(Features, "avx", true); 2955 setFeatureEnabledImpl(Features, "aes", true); 2956 setFeatureEnabledImpl(Features, "pclmul", true); 2957 setFeatureEnabledImpl(Features, "bmi", true); 2958 setFeatureEnabledImpl(Features, "f16c", true); 2959 setFeatureEnabledImpl(Features, "xsaveopt", true); 2960 // FALLTHROUGH 2961 case CK_BTVER1: 2962 setFeatureEnabledImpl(Features, "ssse3", true); 2963 setFeatureEnabledImpl(Features, "sse4a", true); 2964 setFeatureEnabledImpl(Features, "lzcnt", true); 2965 setFeatureEnabledImpl(Features, "popcnt", true); 2966 setFeatureEnabledImpl(Features, "prfchw", true); 2967 setFeatureEnabledImpl(Features, "cx16", true); 2968 setFeatureEnabledImpl(Features, "fxsr", true); 2969 break; 2970 case CK_BDVER4: 2971 setFeatureEnabledImpl(Features, "avx2", true); 2972 setFeatureEnabledImpl(Features, "bmi2", true); 2973 setFeatureEnabledImpl(Features, "mwaitx", true); 2974 // FALLTHROUGH 2975 case CK_BDVER3: 2976 setFeatureEnabledImpl(Features, "fsgsbase", true); 2977 setFeatureEnabledImpl(Features, "xsaveopt", true); 2978 // FALLTHROUGH 2979 case CK_BDVER2: 2980 setFeatureEnabledImpl(Features, "bmi", true); 2981 setFeatureEnabledImpl(Features, "fma", true); 2982 setFeatureEnabledImpl(Features, "f16c", true); 2983 setFeatureEnabledImpl(Features, "tbm", true); 2984 // FALLTHROUGH 2985 case CK_BDVER1: 2986 // xop implies avx, sse4a and fma4. 2987 setFeatureEnabledImpl(Features, "xop", true); 2988 setFeatureEnabledImpl(Features, "lzcnt", true); 2989 setFeatureEnabledImpl(Features, "aes", true); 2990 setFeatureEnabledImpl(Features, "pclmul", true); 2991 setFeatureEnabledImpl(Features, "prfchw", true); 2992 setFeatureEnabledImpl(Features, "cx16", true); 2993 setFeatureEnabledImpl(Features, "fxsr", true); 2994 setFeatureEnabledImpl(Features, "xsave", true); 2995 break; 2996 } 2997 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2998 return false; 2999 3000 // Can't do this earlier because we need to be able to explicitly enable 3001 // or disable these features and the things that they depend upon. 3002 3003 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3004 auto I = Features.find("sse4.2"); 3005 if (I != Features.end() && I->getValue() && 3006 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3007 FeaturesVec.end()) 3008 Features["popcnt"] = true; 3009 3010 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3011 I = Features.find("3dnow"); 3012 if (I != Features.end() && I->getValue() && 3013 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3014 FeaturesVec.end()) 3015 Features["prfchw"] = true; 3016 3017 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3018 // then enable MMX. 3019 I = Features.find("sse"); 3020 if (I != Features.end() && I->getValue() && 3021 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3022 FeaturesVec.end()) 3023 Features["mmx"] = true; 3024 3025 return true; 3026 } 3027 3028 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3029 X86SSEEnum Level, bool Enabled) { 3030 if (Enabled) { 3031 switch (Level) { 3032 case AVX512F: 3033 Features["avx512f"] = true; 3034 case AVX2: 3035 Features["avx2"] = true; 3036 case AVX: 3037 Features["avx"] = true; 3038 Features["xsave"] = true; 3039 case SSE42: 3040 Features["sse4.2"] = true; 3041 case SSE41: 3042 Features["sse4.1"] = true; 3043 case SSSE3: 3044 Features["ssse3"] = true; 3045 case SSE3: 3046 Features["sse3"] = true; 3047 case SSE2: 3048 Features["sse2"] = true; 3049 case SSE1: 3050 Features["sse"] = true; 3051 case NoSSE: 3052 break; 3053 } 3054 return; 3055 } 3056 3057 switch (Level) { 3058 case NoSSE: 3059 case SSE1: 3060 Features["sse"] = false; 3061 case SSE2: 3062 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3063 Features["sha"] = false; 3064 case SSE3: 3065 Features["sse3"] = false; 3066 setXOPLevel(Features, NoXOP, false); 3067 case SSSE3: 3068 Features["ssse3"] = false; 3069 case SSE41: 3070 Features["sse4.1"] = false; 3071 case SSE42: 3072 Features["sse4.2"] = false; 3073 case AVX: 3074 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3075 Features["xsaveopt"] = false; 3076 setXOPLevel(Features, FMA4, false); 3077 case AVX2: 3078 Features["avx2"] = false; 3079 case AVX512F: 3080 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3081 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3082 Features["avx512vl"] = Features["avx512vbmi"] = 3083 Features["avx512ifma"] = false; 3084 } 3085 } 3086 3087 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3088 MMX3DNowEnum Level, bool Enabled) { 3089 if (Enabled) { 3090 switch (Level) { 3091 case AMD3DNowAthlon: 3092 Features["3dnowa"] = true; 3093 case AMD3DNow: 3094 Features["3dnow"] = true; 3095 case MMX: 3096 Features["mmx"] = true; 3097 case NoMMX3DNow: 3098 break; 3099 } 3100 return; 3101 } 3102 3103 switch (Level) { 3104 case NoMMX3DNow: 3105 case MMX: 3106 Features["mmx"] = false; 3107 case AMD3DNow: 3108 Features["3dnow"] = false; 3109 case AMD3DNowAthlon: 3110 Features["3dnowa"] = false; 3111 } 3112 } 3113 3114 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3115 bool Enabled) { 3116 if (Enabled) { 3117 switch (Level) { 3118 case XOP: 3119 Features["xop"] = true; 3120 case FMA4: 3121 Features["fma4"] = true; 3122 setSSELevel(Features, AVX, true); 3123 case SSE4A: 3124 Features["sse4a"] = true; 3125 setSSELevel(Features, SSE3, true); 3126 case NoXOP: 3127 break; 3128 } 3129 return; 3130 } 3131 3132 switch (Level) { 3133 case NoXOP: 3134 case SSE4A: 3135 Features["sse4a"] = false; 3136 case FMA4: 3137 Features["fma4"] = false; 3138 case XOP: 3139 Features["xop"] = false; 3140 } 3141 } 3142 3143 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3144 StringRef Name, bool Enabled) { 3145 // This is a bit of a hack to deal with the sse4 target feature when used 3146 // as part of the target attribute. We handle sse4 correctly everywhere 3147 // else. See below for more information on how we handle the sse4 options. 3148 if (Name != "sse4") 3149 Features[Name] = Enabled; 3150 3151 if (Name == "mmx") { 3152 setMMXLevel(Features, MMX, Enabled); 3153 } else if (Name == "sse") { 3154 setSSELevel(Features, SSE1, Enabled); 3155 } else if (Name == "sse2") { 3156 setSSELevel(Features, SSE2, Enabled); 3157 } else if (Name == "sse3") { 3158 setSSELevel(Features, SSE3, Enabled); 3159 } else if (Name == "ssse3") { 3160 setSSELevel(Features, SSSE3, Enabled); 3161 } else if (Name == "sse4.2") { 3162 setSSELevel(Features, SSE42, Enabled); 3163 } else if (Name == "sse4.1") { 3164 setSSELevel(Features, SSE41, Enabled); 3165 } else if (Name == "3dnow") { 3166 setMMXLevel(Features, AMD3DNow, Enabled); 3167 } else if (Name == "3dnowa") { 3168 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3169 } else if (Name == "aes") { 3170 if (Enabled) 3171 setSSELevel(Features, SSE2, Enabled); 3172 } else if (Name == "pclmul") { 3173 if (Enabled) 3174 setSSELevel(Features, SSE2, Enabled); 3175 } else if (Name == "avx") { 3176 setSSELevel(Features, AVX, Enabled); 3177 } else if (Name == "avx2") { 3178 setSSELevel(Features, AVX2, Enabled); 3179 } else if (Name == "avx512f") { 3180 setSSELevel(Features, AVX512F, Enabled); 3181 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3182 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3183 Name == "avx512vbmi" || Name == "avx512ifma") { 3184 if (Enabled) 3185 setSSELevel(Features, AVX512F, Enabled); 3186 } else if (Name == "fma") { 3187 if (Enabled) 3188 setSSELevel(Features, AVX, Enabled); 3189 } else if (Name == "fma4") { 3190 setXOPLevel(Features, FMA4, Enabled); 3191 } else if (Name == "xop") { 3192 setXOPLevel(Features, XOP, Enabled); 3193 } else if (Name == "sse4a") { 3194 setXOPLevel(Features, SSE4A, Enabled); 3195 } else if (Name == "f16c") { 3196 if (Enabled) 3197 setSSELevel(Features, AVX, Enabled); 3198 } else if (Name == "sha") { 3199 if (Enabled) 3200 setSSELevel(Features, SSE2, Enabled); 3201 } else if (Name == "sse4") { 3202 // We can get here via the __target__ attribute since that's not controlled 3203 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3204 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3205 // disabled. 3206 if (Enabled) 3207 setSSELevel(Features, SSE42, Enabled); 3208 else 3209 setSSELevel(Features, SSE41, Enabled); 3210 } else if (Name == "xsave") { 3211 if (!Enabled) 3212 Features["xsaveopt"] = false; 3213 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3214 if (Enabled) 3215 Features["xsave"] = true; 3216 } 3217 } 3218 3219 /// handleTargetFeatures - Perform initialization based on the user 3220 /// configured set of features. 3221 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3222 DiagnosticsEngine &Diags) { 3223 for (const auto &Feature : Features) { 3224 if (Feature[0] != '+') 3225 continue; 3226 3227 if (Feature == "+aes") { 3228 HasAES = true; 3229 } else if (Feature == "+pclmul") { 3230 HasPCLMUL = true; 3231 } else if (Feature == "+lzcnt") { 3232 HasLZCNT = true; 3233 } else if (Feature == "+rdrnd") { 3234 HasRDRND = true; 3235 } else if (Feature == "+fsgsbase") { 3236 HasFSGSBASE = true; 3237 } else if (Feature == "+bmi") { 3238 HasBMI = true; 3239 } else if (Feature == "+bmi2") { 3240 HasBMI2 = true; 3241 } else if (Feature == "+popcnt") { 3242 HasPOPCNT = true; 3243 } else if (Feature == "+rtm") { 3244 HasRTM = true; 3245 } else if (Feature == "+prfchw") { 3246 HasPRFCHW = true; 3247 } else if (Feature == "+rdseed") { 3248 HasRDSEED = true; 3249 } else if (Feature == "+adx") { 3250 HasADX = true; 3251 } else if (Feature == "+tbm") { 3252 HasTBM = true; 3253 } else if (Feature == "+fma") { 3254 HasFMA = true; 3255 } else if (Feature == "+f16c") { 3256 HasF16C = true; 3257 } else if (Feature == "+avx512cd") { 3258 HasAVX512CD = true; 3259 } else if (Feature == "+avx512er") { 3260 HasAVX512ER = true; 3261 } else if (Feature == "+avx512pf") { 3262 HasAVX512PF = true; 3263 } else if (Feature == "+avx512dq") { 3264 HasAVX512DQ = true; 3265 } else if (Feature == "+avx512bw") { 3266 HasAVX512BW = true; 3267 } else if (Feature == "+avx512vl") { 3268 HasAVX512VL = true; 3269 } else if (Feature == "+avx512vbmi") { 3270 HasAVX512VBMI = true; 3271 } else if (Feature == "+avx512ifma") { 3272 HasAVX512IFMA = true; 3273 } else if (Feature == "+sha") { 3274 HasSHA = true; 3275 } else if (Feature == "+mpx") { 3276 HasMPX = true; 3277 } else if (Feature == "+movbe") { 3278 HasMOVBE = true; 3279 } else if (Feature == "+sgx") { 3280 HasSGX = true; 3281 } else if (Feature == "+cx16") { 3282 HasCX16 = true; 3283 } else if (Feature == "+fxsr") { 3284 HasFXSR = true; 3285 } else if (Feature == "+xsave") { 3286 HasXSAVE = true; 3287 } else if (Feature == "+xsaveopt") { 3288 HasXSAVEOPT = true; 3289 } else if (Feature == "+xsavec") { 3290 HasXSAVEC = true; 3291 } else if (Feature == "+xsaves") { 3292 HasXSAVES = true; 3293 } else if (Feature == "+mwaitx") { 3294 HasMWAITX = true; 3295 } else if (Feature == "+pku") { 3296 HasPKU = true; 3297 } else if (Feature == "+clflushopt") { 3298 HasCLFLUSHOPT = true; 3299 } else if (Feature == "+pcommit") { 3300 HasPCOMMIT = true; 3301 } else if (Feature == "+clwb") { 3302 HasCLWB = true; 3303 } else if (Feature == "+umip") { 3304 HasUMIP = true; 3305 } else if (Feature == "+prefetchwt1") { 3306 HasPREFETCHWT1 = true; 3307 } 3308 3309 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3310 .Case("+avx512f", AVX512F) 3311 .Case("+avx2", AVX2) 3312 .Case("+avx", AVX) 3313 .Case("+sse4.2", SSE42) 3314 .Case("+sse4.1", SSE41) 3315 .Case("+ssse3", SSSE3) 3316 .Case("+sse3", SSE3) 3317 .Case("+sse2", SSE2) 3318 .Case("+sse", SSE1) 3319 .Default(NoSSE); 3320 SSELevel = std::max(SSELevel, Level); 3321 3322 MMX3DNowEnum ThreeDNowLevel = 3323 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3324 .Case("+3dnowa", AMD3DNowAthlon) 3325 .Case("+3dnow", AMD3DNow) 3326 .Case("+mmx", MMX) 3327 .Default(NoMMX3DNow); 3328 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3329 3330 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3331 .Case("+xop", XOP) 3332 .Case("+fma4", FMA4) 3333 .Case("+sse4a", SSE4A) 3334 .Default(NoXOP); 3335 XOPLevel = std::max(XOPLevel, XLevel); 3336 } 3337 3338 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3339 // matches the selected sse level. 3340 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3341 (FPMath == FP_387 && SSELevel >= SSE1)) { 3342 Diags.Report(diag::err_target_unsupported_fpmath) << 3343 (FPMath == FP_SSE ? "sse" : "387"); 3344 return false; 3345 } 3346 3347 SimdDefaultAlign = 3348 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3349 return true; 3350 } 3351 3352 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3353 /// definitions for this particular subtarget. 3354 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3355 MacroBuilder &Builder) const { 3356 // Target identification. 3357 if (getTriple().getArch() == llvm::Triple::x86_64) { 3358 Builder.defineMacro("__amd64__"); 3359 Builder.defineMacro("__amd64"); 3360 Builder.defineMacro("__x86_64"); 3361 Builder.defineMacro("__x86_64__"); 3362 if (getTriple().getArchName() == "x86_64h") { 3363 Builder.defineMacro("__x86_64h"); 3364 Builder.defineMacro("__x86_64h__"); 3365 } 3366 } else { 3367 DefineStd(Builder, "i386", Opts); 3368 } 3369 3370 // Subtarget options. 3371 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3372 // truly should be based on -mtune options. 3373 switch (CPU) { 3374 case CK_Generic: 3375 break; 3376 case CK_i386: 3377 // The rest are coming from the i386 define above. 3378 Builder.defineMacro("__tune_i386__"); 3379 break; 3380 case CK_i486: 3381 case CK_WinChipC6: 3382 case CK_WinChip2: 3383 case CK_C3: 3384 defineCPUMacros(Builder, "i486"); 3385 break; 3386 case CK_PentiumMMX: 3387 Builder.defineMacro("__pentium_mmx__"); 3388 Builder.defineMacro("__tune_pentium_mmx__"); 3389 // Fallthrough 3390 case CK_i586: 3391 case CK_Pentium: 3392 defineCPUMacros(Builder, "i586"); 3393 defineCPUMacros(Builder, "pentium"); 3394 break; 3395 case CK_Pentium3: 3396 case CK_Pentium3M: 3397 case CK_PentiumM: 3398 Builder.defineMacro("__tune_pentium3__"); 3399 // Fallthrough 3400 case CK_Pentium2: 3401 case CK_C3_2: 3402 Builder.defineMacro("__tune_pentium2__"); 3403 // Fallthrough 3404 case CK_PentiumPro: 3405 Builder.defineMacro("__tune_i686__"); 3406 Builder.defineMacro("__tune_pentiumpro__"); 3407 // Fallthrough 3408 case CK_i686: 3409 Builder.defineMacro("__i686"); 3410 Builder.defineMacro("__i686__"); 3411 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3412 Builder.defineMacro("__pentiumpro"); 3413 Builder.defineMacro("__pentiumpro__"); 3414 break; 3415 case CK_Pentium4: 3416 case CK_Pentium4M: 3417 defineCPUMacros(Builder, "pentium4"); 3418 break; 3419 case CK_Yonah: 3420 case CK_Prescott: 3421 case CK_Nocona: 3422 defineCPUMacros(Builder, "nocona"); 3423 break; 3424 case CK_Core2: 3425 case CK_Penryn: 3426 defineCPUMacros(Builder, "core2"); 3427 break; 3428 case CK_Bonnell: 3429 defineCPUMacros(Builder, "atom"); 3430 break; 3431 case CK_Silvermont: 3432 defineCPUMacros(Builder, "slm"); 3433 break; 3434 case CK_Nehalem: 3435 case CK_Westmere: 3436 case CK_SandyBridge: 3437 case CK_IvyBridge: 3438 case CK_Haswell: 3439 case CK_Broadwell: 3440 case CK_SkylakeClient: 3441 // FIXME: Historically, we defined this legacy name, it would be nice to 3442 // remove it at some point. We've never exposed fine-grained names for 3443 // recent primary x86 CPUs, and we should keep it that way. 3444 defineCPUMacros(Builder, "corei7"); 3445 break; 3446 case CK_SkylakeServer: 3447 defineCPUMacros(Builder, "skx"); 3448 break; 3449 case CK_Cannonlake: 3450 break; 3451 case CK_KNL: 3452 defineCPUMacros(Builder, "knl"); 3453 break; 3454 case CK_Lakemont: 3455 Builder.defineMacro("__tune_lakemont__"); 3456 break; 3457 case CK_K6_2: 3458 Builder.defineMacro("__k6_2__"); 3459 Builder.defineMacro("__tune_k6_2__"); 3460 // Fallthrough 3461 case CK_K6_3: 3462 if (CPU != CK_K6_2) { // In case of fallthrough 3463 // FIXME: GCC may be enabling these in cases where some other k6 3464 // architecture is specified but -m3dnow is explicitly provided. The 3465 // exact semantics need to be determined and emulated here. 3466 Builder.defineMacro("__k6_3__"); 3467 Builder.defineMacro("__tune_k6_3__"); 3468 } 3469 // Fallthrough 3470 case CK_K6: 3471 defineCPUMacros(Builder, "k6"); 3472 break; 3473 case CK_Athlon: 3474 case CK_AthlonThunderbird: 3475 case CK_Athlon4: 3476 case CK_AthlonXP: 3477 case CK_AthlonMP: 3478 defineCPUMacros(Builder, "athlon"); 3479 if (SSELevel != NoSSE) { 3480 Builder.defineMacro("__athlon_sse__"); 3481 Builder.defineMacro("__tune_athlon_sse__"); 3482 } 3483 break; 3484 case CK_K8: 3485 case CK_K8SSE3: 3486 case CK_x86_64: 3487 case CK_Opteron: 3488 case CK_OpteronSSE3: 3489 case CK_Athlon64: 3490 case CK_Athlon64SSE3: 3491 case CK_AthlonFX: 3492 defineCPUMacros(Builder, "k8"); 3493 break; 3494 case CK_AMDFAM10: 3495 defineCPUMacros(Builder, "amdfam10"); 3496 break; 3497 case CK_BTVER1: 3498 defineCPUMacros(Builder, "btver1"); 3499 break; 3500 case CK_BTVER2: 3501 defineCPUMacros(Builder, "btver2"); 3502 break; 3503 case CK_BDVER1: 3504 defineCPUMacros(Builder, "bdver1"); 3505 break; 3506 case CK_BDVER2: 3507 defineCPUMacros(Builder, "bdver2"); 3508 break; 3509 case CK_BDVER3: 3510 defineCPUMacros(Builder, "bdver3"); 3511 break; 3512 case CK_BDVER4: 3513 defineCPUMacros(Builder, "bdver4"); 3514 break; 3515 case CK_Geode: 3516 defineCPUMacros(Builder, "geode"); 3517 break; 3518 } 3519 3520 // Target properties. 3521 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3522 3523 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3524 // functions in glibc header files that use FP Stack inline asm which the 3525 // backend can't deal with (PR879). 3526 Builder.defineMacro("__NO_MATH_INLINES"); 3527 3528 if (HasAES) 3529 Builder.defineMacro("__AES__"); 3530 3531 if (HasPCLMUL) 3532 Builder.defineMacro("__PCLMUL__"); 3533 3534 if (HasLZCNT) 3535 Builder.defineMacro("__LZCNT__"); 3536 3537 if (HasRDRND) 3538 Builder.defineMacro("__RDRND__"); 3539 3540 if (HasFSGSBASE) 3541 Builder.defineMacro("__FSGSBASE__"); 3542 3543 if (HasBMI) 3544 Builder.defineMacro("__BMI__"); 3545 3546 if (HasBMI2) 3547 Builder.defineMacro("__BMI2__"); 3548 3549 if (HasPOPCNT) 3550 Builder.defineMacro("__POPCNT__"); 3551 3552 if (HasRTM) 3553 Builder.defineMacro("__RTM__"); 3554 3555 if (HasPRFCHW) 3556 Builder.defineMacro("__PRFCHW__"); 3557 3558 if (HasRDSEED) 3559 Builder.defineMacro("__RDSEED__"); 3560 3561 if (HasADX) 3562 Builder.defineMacro("__ADX__"); 3563 3564 if (HasTBM) 3565 Builder.defineMacro("__TBM__"); 3566 3567 if (HasMWAITX) 3568 Builder.defineMacro("__MWAITX__"); 3569 3570 switch (XOPLevel) { 3571 case XOP: 3572 Builder.defineMacro("__XOP__"); 3573 case FMA4: 3574 Builder.defineMacro("__FMA4__"); 3575 case SSE4A: 3576 Builder.defineMacro("__SSE4A__"); 3577 case NoXOP: 3578 break; 3579 } 3580 3581 if (HasFMA) 3582 Builder.defineMacro("__FMA__"); 3583 3584 if (HasF16C) 3585 Builder.defineMacro("__F16C__"); 3586 3587 if (HasAVX512CD) 3588 Builder.defineMacro("__AVX512CD__"); 3589 if (HasAVX512ER) 3590 Builder.defineMacro("__AVX512ER__"); 3591 if (HasAVX512PF) 3592 Builder.defineMacro("__AVX512PF__"); 3593 if (HasAVX512DQ) 3594 Builder.defineMacro("__AVX512DQ__"); 3595 if (HasAVX512BW) 3596 Builder.defineMacro("__AVX512BW__"); 3597 if (HasAVX512VL) 3598 Builder.defineMacro("__AVX512VL__"); 3599 if (HasAVX512VBMI) 3600 Builder.defineMacro("__AVX512VBMI__"); 3601 if (HasAVX512IFMA) 3602 Builder.defineMacro("__AVX512IFMA__"); 3603 3604 if (HasSHA) 3605 Builder.defineMacro("__SHA__"); 3606 3607 if (HasFXSR) 3608 Builder.defineMacro("__FXSR__"); 3609 if (HasXSAVE) 3610 Builder.defineMacro("__XSAVE__"); 3611 if (HasXSAVEOPT) 3612 Builder.defineMacro("__XSAVEOPT__"); 3613 if (HasXSAVEC) 3614 Builder.defineMacro("__XSAVEC__"); 3615 if (HasXSAVES) 3616 Builder.defineMacro("__XSAVES__"); 3617 if (HasPKU) 3618 Builder.defineMacro("__PKU__"); 3619 if (HasCX16) 3620 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3621 3622 // Each case falls through to the previous one here. 3623 switch (SSELevel) { 3624 case AVX512F: 3625 Builder.defineMacro("__AVX512F__"); 3626 case AVX2: 3627 Builder.defineMacro("__AVX2__"); 3628 case AVX: 3629 Builder.defineMacro("__AVX__"); 3630 case SSE42: 3631 Builder.defineMacro("__SSE4_2__"); 3632 case SSE41: 3633 Builder.defineMacro("__SSE4_1__"); 3634 case SSSE3: 3635 Builder.defineMacro("__SSSE3__"); 3636 case SSE3: 3637 Builder.defineMacro("__SSE3__"); 3638 case SSE2: 3639 Builder.defineMacro("__SSE2__"); 3640 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3641 case SSE1: 3642 Builder.defineMacro("__SSE__"); 3643 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3644 case NoSSE: 3645 break; 3646 } 3647 3648 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3649 switch (SSELevel) { 3650 case AVX512F: 3651 case AVX2: 3652 case AVX: 3653 case SSE42: 3654 case SSE41: 3655 case SSSE3: 3656 case SSE3: 3657 case SSE2: 3658 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3659 break; 3660 case SSE1: 3661 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3662 break; 3663 default: 3664 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3665 } 3666 } 3667 3668 // Each case falls through to the previous one here. 3669 switch (MMX3DNowLevel) { 3670 case AMD3DNowAthlon: 3671 Builder.defineMacro("__3dNOW_A__"); 3672 case AMD3DNow: 3673 Builder.defineMacro("__3dNOW__"); 3674 case MMX: 3675 Builder.defineMacro("__MMX__"); 3676 case NoMMX3DNow: 3677 break; 3678 } 3679 3680 if (CPU >= CK_i486) { 3681 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3682 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3683 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3684 } 3685 if (CPU >= CK_i586) 3686 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3687 } 3688 3689 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3690 return llvm::StringSwitch<bool>(Feature) 3691 .Case("aes", HasAES) 3692 .Case("avx", SSELevel >= AVX) 3693 .Case("avx2", SSELevel >= AVX2) 3694 .Case("avx512f", SSELevel >= AVX512F) 3695 .Case("avx512cd", HasAVX512CD) 3696 .Case("avx512er", HasAVX512ER) 3697 .Case("avx512pf", HasAVX512PF) 3698 .Case("avx512dq", HasAVX512DQ) 3699 .Case("avx512bw", HasAVX512BW) 3700 .Case("avx512vl", HasAVX512VL) 3701 .Case("avx512vbmi", HasAVX512VBMI) 3702 .Case("avx512ifma", HasAVX512IFMA) 3703 .Case("bmi", HasBMI) 3704 .Case("bmi2", HasBMI2) 3705 .Case("clflushopt", HasCLFLUSHOPT) 3706 .Case("clwb", HasCLWB) 3707 .Case("cx16", HasCX16) 3708 .Case("f16c", HasF16C) 3709 .Case("fma", HasFMA) 3710 .Case("fma4", XOPLevel >= FMA4) 3711 .Case("fsgsbase", HasFSGSBASE) 3712 .Case("fxsr", HasFXSR) 3713 .Case("lzcnt", HasLZCNT) 3714 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3715 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3716 .Case("mmx", MMX3DNowLevel >= MMX) 3717 .Case("movbe", HasMOVBE) 3718 .Case("mpx", HasMPX) 3719 .Case("pclmul", HasPCLMUL) 3720 .Case("pcommit", HasPCOMMIT) 3721 .Case("pku", HasPKU) 3722 .Case("popcnt", HasPOPCNT) 3723 .Case("prefetchwt1", HasPREFETCHWT1) 3724 .Case("prfchw", HasPRFCHW) 3725 .Case("rdrnd", HasRDRND) 3726 .Case("rdseed", HasRDSEED) 3727 .Case("rtm", HasRTM) 3728 .Case("sgx", HasSGX) 3729 .Case("sha", HasSHA) 3730 .Case("sse", SSELevel >= SSE1) 3731 .Case("sse2", SSELevel >= SSE2) 3732 .Case("sse3", SSELevel >= SSE3) 3733 .Case("ssse3", SSELevel >= SSSE3) 3734 .Case("sse4.1", SSELevel >= SSE41) 3735 .Case("sse4.2", SSELevel >= SSE42) 3736 .Case("sse4a", XOPLevel >= SSE4A) 3737 .Case("tbm", HasTBM) 3738 .Case("umip", HasUMIP) 3739 .Case("x86", true) 3740 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3741 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3742 .Case("xop", XOPLevel >= XOP) 3743 .Case("xsave", HasXSAVE) 3744 .Case("xsavec", HasXSAVEC) 3745 .Case("xsaves", HasXSAVES) 3746 .Case("xsaveopt", HasXSAVEOPT) 3747 .Default(false); 3748 } 3749 3750 // We can't use a generic validation scheme for the features accepted here 3751 // versus subtarget features accepted in the target attribute because the 3752 // bitfield structure that's initialized in the runtime only supports the 3753 // below currently rather than the full range of subtarget features. (See 3754 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3755 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3756 return llvm::StringSwitch<bool>(FeatureStr) 3757 .Case("cmov", true) 3758 .Case("mmx", true) 3759 .Case("popcnt", true) 3760 .Case("sse", true) 3761 .Case("sse2", true) 3762 .Case("sse3", true) 3763 .Case("ssse3", true) 3764 .Case("sse4.1", true) 3765 .Case("sse4.2", true) 3766 .Case("avx", true) 3767 .Case("avx2", true) 3768 .Case("sse4a", true) 3769 .Case("fma4", true) 3770 .Case("xop", true) 3771 .Case("fma", true) 3772 .Case("avx512f", true) 3773 .Case("bmi", true) 3774 .Case("bmi2", true) 3775 .Case("aes", true) 3776 .Case("pclmul", true) 3777 .Case("avx512vl", true) 3778 .Case("avx512bw", true) 3779 .Case("avx512dq", true) 3780 .Case("avx512cd", true) 3781 .Case("avx512er", true) 3782 .Case("avx512pf", true) 3783 .Case("avx512vbmi", true) 3784 .Case("avx512ifma", true) 3785 .Default(false); 3786 } 3787 3788 bool 3789 X86TargetInfo::validateAsmConstraint(const char *&Name, 3790 TargetInfo::ConstraintInfo &Info) const { 3791 switch (*Name) { 3792 default: return false; 3793 // Constant constraints. 3794 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3795 // instructions. 3796 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3797 // x86_64 instructions. 3798 case 's': 3799 Info.setRequiresImmediate(); 3800 return true; 3801 case 'I': 3802 Info.setRequiresImmediate(0, 31); 3803 return true; 3804 case 'J': 3805 Info.setRequiresImmediate(0, 63); 3806 return true; 3807 case 'K': 3808 Info.setRequiresImmediate(-128, 127); 3809 return true; 3810 case 'L': 3811 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3812 return true; 3813 case 'M': 3814 Info.setRequiresImmediate(0, 3); 3815 return true; 3816 case 'N': 3817 Info.setRequiresImmediate(0, 255); 3818 return true; 3819 case 'O': 3820 Info.setRequiresImmediate(0, 127); 3821 return true; 3822 // Register constraints. 3823 case 'Y': // 'Y' is the first character for several 2-character constraints. 3824 // Shift the pointer to the second character of the constraint. 3825 Name++; 3826 switch (*Name) { 3827 default: 3828 return false; 3829 case '0': // First SSE register. 3830 case 't': // Any SSE register, when SSE2 is enabled. 3831 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3832 case 'm': // Any MMX register, when inter-unit moves enabled. 3833 Info.setAllowsRegister(); 3834 return true; 3835 } 3836 case 'f': // Any x87 floating point stack register. 3837 // Constraint 'f' cannot be used for output operands. 3838 if (Info.ConstraintStr[0] == '=') 3839 return false; 3840 Info.setAllowsRegister(); 3841 return true; 3842 case 'a': // eax. 3843 case 'b': // ebx. 3844 case 'c': // ecx. 3845 case 'd': // edx. 3846 case 'S': // esi. 3847 case 'D': // edi. 3848 case 'A': // edx:eax. 3849 case 't': // Top of floating point stack. 3850 case 'u': // Second from top of floating point stack. 3851 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3852 case 'y': // Any MMX register. 3853 case 'x': // Any SSE register. 3854 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3855 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3856 case 'l': // "Index" registers: any general register that can be used as an 3857 // index in a base+index memory access. 3858 Info.setAllowsRegister(); 3859 return true; 3860 // Floating point constant constraints. 3861 case 'C': // SSE floating point constant. 3862 case 'G': // x87 floating point constant. 3863 return true; 3864 } 3865 } 3866 3867 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3868 unsigned Size) const { 3869 // Strip off constraint modifiers. 3870 while (Constraint[0] == '=' || 3871 Constraint[0] == '+' || 3872 Constraint[0] == '&') 3873 Constraint = Constraint.substr(1); 3874 3875 return validateOperandSize(Constraint, Size); 3876 } 3877 3878 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3879 unsigned Size) const { 3880 return validateOperandSize(Constraint, Size); 3881 } 3882 3883 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3884 unsigned Size) const { 3885 switch (Constraint[0]) { 3886 default: break; 3887 case 'y': 3888 return Size <= 64; 3889 case 'f': 3890 case 't': 3891 case 'u': 3892 return Size <= 128; 3893 case 'x': 3894 if (SSELevel >= AVX512F) 3895 // 512-bit zmm registers can be used if target supports AVX512F. 3896 return Size <= 512U; 3897 else if (SSELevel >= AVX) 3898 // 256-bit ymm registers can be used if target supports AVX. 3899 return Size <= 256U; 3900 return Size <= 128U; 3901 case 'Y': 3902 // 'Y' is the first character for several 2-character constraints. 3903 switch (Constraint[1]) { 3904 default: break; 3905 case 'm': 3906 // 'Ym' is synonymous with 'y'. 3907 return Size <= 64; 3908 case 'i': 3909 case 't': 3910 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3911 if (SSELevel >= AVX512F) 3912 return Size <= 512U; 3913 else if (SSELevel >= AVX) 3914 return Size <= 256U; 3915 return SSELevel >= SSE2 && Size <= 128U; 3916 } 3917 3918 } 3919 3920 return true; 3921 } 3922 3923 std::string 3924 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3925 switch (*Constraint) { 3926 case 'a': return std::string("{ax}"); 3927 case 'b': return std::string("{bx}"); 3928 case 'c': return std::string("{cx}"); 3929 case 'd': return std::string("{dx}"); 3930 case 'S': return std::string("{si}"); 3931 case 'D': return std::string("{di}"); 3932 case 'p': // address 3933 return std::string("im"); 3934 case 't': // top of floating point stack. 3935 return std::string("{st}"); 3936 case 'u': // second from top of floating point stack. 3937 return std::string("{st(1)}"); // second from top of floating point stack. 3938 default: 3939 return std::string(1, *Constraint); 3940 } 3941 } 3942 3943 // X86-32 generic target 3944 class X86_32TargetInfo : public X86TargetInfo { 3945 public: 3946 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 3947 : X86TargetInfo(Triple, Opts) { 3948 DoubleAlign = LongLongAlign = 32; 3949 LongDoubleWidth = 96; 3950 LongDoubleAlign = 32; 3951 SuitableAlign = 128; 3952 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 3953 SizeType = UnsignedInt; 3954 PtrDiffType = SignedInt; 3955 IntPtrType = SignedInt; 3956 RegParmMax = 3; 3957 3958 // Use fpret for all types. 3959 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3960 (1 << TargetInfo::Double) | 3961 (1 << TargetInfo::LongDouble)); 3962 3963 // x86-32 has atomics up to 8 bytes 3964 // FIXME: Check that we actually have cmpxchg8b before setting 3965 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3966 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3967 } 3968 BuiltinVaListKind getBuiltinVaListKind() const override { 3969 return TargetInfo::CharPtrBuiltinVaList; 3970 } 3971 3972 int getEHDataRegisterNumber(unsigned RegNo) const override { 3973 if (RegNo == 0) return 0; 3974 if (RegNo == 1) return 2; 3975 return -1; 3976 } 3977 bool validateOperandSize(StringRef Constraint, 3978 unsigned Size) const override { 3979 switch (Constraint[0]) { 3980 default: break; 3981 case 'R': 3982 case 'q': 3983 case 'Q': 3984 case 'a': 3985 case 'b': 3986 case 'c': 3987 case 'd': 3988 case 'S': 3989 case 'D': 3990 return Size <= 32; 3991 case 'A': 3992 return Size <= 64; 3993 } 3994 3995 return X86TargetInfo::validateOperandSize(Constraint, Size); 3996 } 3997 }; 3998 3999 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4000 public: 4001 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4002 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4003 4004 unsigned getFloatEvalMethod() const override { 4005 unsigned Major, Minor, Micro; 4006 getTriple().getOSVersion(Major, Minor, Micro); 4007 // New NetBSD uses the default rounding mode. 4008 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4009 return X86_32TargetInfo::getFloatEvalMethod(); 4010 // NetBSD before 6.99.26 defaults to "double" rounding. 4011 return 1; 4012 } 4013 }; 4014 4015 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4016 public: 4017 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4018 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4019 SizeType = UnsignedLong; 4020 IntPtrType = SignedLong; 4021 PtrDiffType = SignedLong; 4022 } 4023 }; 4024 4025 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4026 public: 4027 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4028 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4029 SizeType = UnsignedLong; 4030 IntPtrType = SignedLong; 4031 PtrDiffType = SignedLong; 4032 } 4033 }; 4034 4035 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4036 public: 4037 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4038 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4039 LongDoubleWidth = 128; 4040 LongDoubleAlign = 128; 4041 SuitableAlign = 128; 4042 MaxVectorAlign = 256; 4043 // The watchOS simulator uses the builtin bool type for Objective-C. 4044 llvm::Triple T = llvm::Triple(Triple); 4045 if (T.isWatchOS()) 4046 UseSignedCharForObjCBool = false; 4047 SizeType = UnsignedLong; 4048 IntPtrType = SignedLong; 4049 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4050 HasAlignMac68kSupport = true; 4051 } 4052 4053 bool handleTargetFeatures(std::vector<std::string> &Features, 4054 DiagnosticsEngine &Diags) override { 4055 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4056 Diags)) 4057 return false; 4058 // We now know the features we have: we can decide how to align vectors. 4059 MaxVectorAlign = 4060 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4061 return true; 4062 } 4063 }; 4064 4065 // x86-32 Windows target 4066 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4067 public: 4068 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4069 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4070 WCharType = UnsignedShort; 4071 DoubleAlign = LongLongAlign = 64; 4072 bool IsWinCOFF = 4073 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4074 resetDataLayout(IsWinCOFF 4075 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4076 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4077 } 4078 void getTargetDefines(const LangOptions &Opts, 4079 MacroBuilder &Builder) const override { 4080 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4081 } 4082 }; 4083 4084 // x86-32 Windows Visual Studio target 4085 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4086 public: 4087 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4088 const TargetOptions &Opts) 4089 : WindowsX86_32TargetInfo(Triple, Opts) { 4090 LongDoubleWidth = LongDoubleAlign = 64; 4091 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4092 } 4093 void getTargetDefines(const LangOptions &Opts, 4094 MacroBuilder &Builder) const override { 4095 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4096 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4097 // The value of the following reflects processor type. 4098 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4099 // We lost the original triple, so we use the default. 4100 Builder.defineMacro("_M_IX86", "600"); 4101 } 4102 }; 4103 4104 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4105 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4106 // supports __declspec natively under -fms-extensions, but we define a no-op 4107 // __declspec macro anyway for pre-processor compatibility. 4108 if (Opts.MicrosoftExt) 4109 Builder.defineMacro("__declspec", "__declspec"); 4110 else 4111 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4112 4113 if (!Opts.MicrosoftExt) { 4114 // Provide macros for all the calling convention keywords. Provide both 4115 // single and double underscore prefixed variants. These are available on 4116 // x64 as well as x86, even though they have no effect. 4117 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4118 for (const char *CC : CCs) { 4119 std::string GCCSpelling = "__attribute__((__"; 4120 GCCSpelling += CC; 4121 GCCSpelling += "__))"; 4122 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4123 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4124 } 4125 } 4126 } 4127 4128 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4129 Builder.defineMacro("__MSVCRT__"); 4130 Builder.defineMacro("__MINGW32__"); 4131 addCygMingDefines(Opts, Builder); 4132 } 4133 4134 // x86-32 MinGW target 4135 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4136 public: 4137 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4138 : WindowsX86_32TargetInfo(Triple, Opts) {} 4139 void getTargetDefines(const LangOptions &Opts, 4140 MacroBuilder &Builder) const override { 4141 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4142 DefineStd(Builder, "WIN32", Opts); 4143 DefineStd(Builder, "WINNT", Opts); 4144 Builder.defineMacro("_X86_"); 4145 addMinGWDefines(Opts, Builder); 4146 } 4147 }; 4148 4149 // x86-32 Cygwin target 4150 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4151 public: 4152 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4153 : X86_32TargetInfo(Triple, Opts) { 4154 WCharType = UnsignedShort; 4155 DoubleAlign = LongLongAlign = 64; 4156 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4157 } 4158 void getTargetDefines(const LangOptions &Opts, 4159 MacroBuilder &Builder) const override { 4160 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4161 Builder.defineMacro("_X86_"); 4162 Builder.defineMacro("__CYGWIN__"); 4163 Builder.defineMacro("__CYGWIN32__"); 4164 addCygMingDefines(Opts, Builder); 4165 DefineStd(Builder, "unix", Opts); 4166 if (Opts.CPlusPlus) 4167 Builder.defineMacro("_GNU_SOURCE"); 4168 } 4169 }; 4170 4171 // x86-32 Haiku target 4172 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4173 public: 4174 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4175 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4176 } 4177 void getTargetDefines(const LangOptions &Opts, 4178 MacroBuilder &Builder) const override { 4179 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4180 Builder.defineMacro("__INTEL__"); 4181 } 4182 }; 4183 4184 // X86-32 MCU target 4185 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4186 public: 4187 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4188 : X86_32TargetInfo(Triple, Opts) { 4189 LongDoubleWidth = 64; 4190 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4191 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4192 WIntType = UnsignedInt; 4193 } 4194 4195 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4196 // On MCU we support only C calling convention. 4197 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4198 } 4199 4200 void getTargetDefines(const LangOptions &Opts, 4201 MacroBuilder &Builder) const override { 4202 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4203 Builder.defineMacro("__iamcu"); 4204 Builder.defineMacro("__iamcu__"); 4205 } 4206 4207 bool allowsLargerPreferedTypeAlignment() const override { 4208 return false; 4209 } 4210 }; 4211 4212 // RTEMS Target 4213 template<typename Target> 4214 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4215 protected: 4216 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4217 MacroBuilder &Builder) const override { 4218 // RTEMS defines; list based off of gcc output 4219 4220 Builder.defineMacro("__rtems__"); 4221 Builder.defineMacro("__ELF__"); 4222 } 4223 4224 public: 4225 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4226 : OSTargetInfo<Target>(Triple, Opts) { 4227 switch (Triple.getArch()) { 4228 default: 4229 case llvm::Triple::x86: 4230 // this->MCountName = ".mcount"; 4231 break; 4232 case llvm::Triple::mips: 4233 case llvm::Triple::mipsel: 4234 case llvm::Triple::ppc: 4235 case llvm::Triple::ppc64: 4236 case llvm::Triple::ppc64le: 4237 // this->MCountName = "_mcount"; 4238 break; 4239 case llvm::Triple::arm: 4240 // this->MCountName = "__mcount"; 4241 break; 4242 } 4243 } 4244 }; 4245 4246 // x86-32 RTEMS target 4247 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4248 public: 4249 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4250 : X86_32TargetInfo(Triple, Opts) { 4251 SizeType = UnsignedLong; 4252 IntPtrType = SignedLong; 4253 PtrDiffType = SignedLong; 4254 } 4255 void getTargetDefines(const LangOptions &Opts, 4256 MacroBuilder &Builder) const override { 4257 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4258 Builder.defineMacro("__INTEL__"); 4259 Builder.defineMacro("__rtems__"); 4260 } 4261 }; 4262 4263 // x86-64 generic target 4264 class X86_64TargetInfo : public X86TargetInfo { 4265 public: 4266 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4267 : X86TargetInfo(Triple, Opts) { 4268 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4269 bool IsWinCOFF = 4270 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4271 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4272 LongDoubleWidth = 128; 4273 LongDoubleAlign = 128; 4274 LargeArrayMinWidth = 128; 4275 LargeArrayAlign = 128; 4276 SuitableAlign = 128; 4277 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4278 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4279 IntPtrType = IsX32 ? SignedInt : SignedLong; 4280 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4281 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4282 RegParmMax = 6; 4283 4284 // Pointers are 32-bit in x32. 4285 resetDataLayout(IsX32 4286 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4287 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4288 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4289 4290 // Use fpret only for long double. 4291 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4292 4293 // Use fp2ret for _Complex long double. 4294 ComplexLongDoubleUsesFP2Ret = true; 4295 4296 // Make __builtin_ms_va_list available. 4297 HasBuiltinMSVaList = true; 4298 4299 // x86-64 has atomics up to 16 bytes. 4300 MaxAtomicPromoteWidth = 128; 4301 MaxAtomicInlineWidth = 128; 4302 } 4303 BuiltinVaListKind getBuiltinVaListKind() const override { 4304 return TargetInfo::X86_64ABIBuiltinVaList; 4305 } 4306 4307 int getEHDataRegisterNumber(unsigned RegNo) const override { 4308 if (RegNo == 0) return 0; 4309 if (RegNo == 1) return 1; 4310 return -1; 4311 } 4312 4313 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4314 switch (CC) { 4315 case CC_C: 4316 case CC_Swift: 4317 case CC_X86VectorCall: 4318 case CC_IntelOclBicc: 4319 case CC_X86_64Win64: 4320 case CC_PreserveMost: 4321 case CC_PreserveAll: 4322 return CCCR_OK; 4323 default: 4324 return CCCR_Warning; 4325 } 4326 } 4327 4328 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4329 return CC_C; 4330 } 4331 4332 // for x32 we need it here explicitly 4333 bool hasInt128Type() const override { return true; } 4334 unsigned getUnwindWordWidth() const override { return 64; } 4335 unsigned getRegisterWidth() const override { return 64; } 4336 4337 bool validateGlobalRegisterVariable(StringRef RegName, 4338 unsigned RegSize, 4339 bool &HasSizeMismatch) const override { 4340 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4341 // handle. 4342 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4343 // Check that the register size is 64-bit. 4344 HasSizeMismatch = RegSize != 64; 4345 return true; 4346 } 4347 4348 // Check if the register is a 32-bit register the backend can handle. 4349 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4350 HasSizeMismatch); 4351 } 4352 }; 4353 4354 // x86-64 Windows target 4355 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4356 public: 4357 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4358 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4359 WCharType = UnsignedShort; 4360 LongWidth = LongAlign = 32; 4361 DoubleAlign = LongLongAlign = 64; 4362 IntMaxType = SignedLongLong; 4363 Int64Type = SignedLongLong; 4364 SizeType = UnsignedLongLong; 4365 PtrDiffType = SignedLongLong; 4366 IntPtrType = SignedLongLong; 4367 } 4368 4369 void getTargetDefines(const LangOptions &Opts, 4370 MacroBuilder &Builder) const override { 4371 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4372 Builder.defineMacro("_WIN64"); 4373 } 4374 4375 BuiltinVaListKind getBuiltinVaListKind() const override { 4376 return TargetInfo::CharPtrBuiltinVaList; 4377 } 4378 4379 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4380 switch (CC) { 4381 case CC_X86StdCall: 4382 case CC_X86ThisCall: 4383 case CC_X86FastCall: 4384 return CCCR_Ignore; 4385 case CC_C: 4386 case CC_X86VectorCall: 4387 case CC_IntelOclBicc: 4388 case CC_X86_64SysV: 4389 return CCCR_OK; 4390 default: 4391 return CCCR_Warning; 4392 } 4393 } 4394 }; 4395 4396 // x86-64 Windows Visual Studio target 4397 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4398 public: 4399 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4400 const TargetOptions &Opts) 4401 : WindowsX86_64TargetInfo(Triple, Opts) { 4402 LongDoubleWidth = LongDoubleAlign = 64; 4403 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4404 } 4405 void getTargetDefines(const LangOptions &Opts, 4406 MacroBuilder &Builder) const override { 4407 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4408 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4409 Builder.defineMacro("_M_X64", "100"); 4410 Builder.defineMacro("_M_AMD64", "100"); 4411 } 4412 }; 4413 4414 // x86-64 MinGW target 4415 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4416 public: 4417 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4418 : WindowsX86_64TargetInfo(Triple, Opts) { 4419 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4420 // with x86 FP ops. Weird. 4421 LongDoubleWidth = LongDoubleAlign = 128; 4422 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4423 } 4424 4425 void getTargetDefines(const LangOptions &Opts, 4426 MacroBuilder &Builder) const override { 4427 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4428 DefineStd(Builder, "WIN64", Opts); 4429 Builder.defineMacro("__MINGW64__"); 4430 addMinGWDefines(Opts, Builder); 4431 4432 // GCC defines this macro when it is using __gxx_personality_seh0. 4433 if (!Opts.SjLjExceptions) 4434 Builder.defineMacro("__SEH__"); 4435 } 4436 }; 4437 4438 // x86-64 Cygwin target 4439 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4440 public: 4441 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4442 : X86_64TargetInfo(Triple, Opts) { 4443 TLSSupported = false; 4444 WCharType = UnsignedShort; 4445 } 4446 void getTargetDefines(const LangOptions &Opts, 4447 MacroBuilder &Builder) const override { 4448 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4449 Builder.defineMacro("__x86_64__"); 4450 Builder.defineMacro("__CYGWIN__"); 4451 Builder.defineMacro("__CYGWIN64__"); 4452 addCygMingDefines(Opts, Builder); 4453 DefineStd(Builder, "unix", Opts); 4454 if (Opts.CPlusPlus) 4455 Builder.defineMacro("_GNU_SOURCE"); 4456 4457 // GCC defines this macro when it is using __gxx_personality_seh0. 4458 if (!Opts.SjLjExceptions) 4459 Builder.defineMacro("__SEH__"); 4460 } 4461 }; 4462 4463 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4464 public: 4465 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4466 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4467 Int64Type = SignedLongLong; 4468 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4469 llvm::Triple T = llvm::Triple(Triple); 4470 if (T.isiOS()) 4471 UseSignedCharForObjCBool = false; 4472 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4473 } 4474 4475 bool handleTargetFeatures(std::vector<std::string> &Features, 4476 DiagnosticsEngine &Diags) override { 4477 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4478 Diags)) 4479 return false; 4480 // We now know the features we have: we can decide how to align vectors. 4481 MaxVectorAlign = 4482 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4483 return true; 4484 } 4485 }; 4486 4487 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4488 public: 4489 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4490 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4491 IntMaxType = SignedLongLong; 4492 Int64Type = SignedLongLong; 4493 } 4494 }; 4495 4496 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4497 public: 4498 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4499 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4500 IntMaxType = SignedLongLong; 4501 Int64Type = SignedLongLong; 4502 } 4503 }; 4504 4505 class ARMTargetInfo : public TargetInfo { 4506 // Possible FPU choices. 4507 enum FPUMode { 4508 VFP2FPU = (1 << 0), 4509 VFP3FPU = (1 << 1), 4510 VFP4FPU = (1 << 2), 4511 NeonFPU = (1 << 3), 4512 FPARMV8 = (1 << 4) 4513 }; 4514 4515 // Possible HWDiv features. 4516 enum HWDivMode { 4517 HWDivThumb = (1 << 0), 4518 HWDivARM = (1 << 1) 4519 }; 4520 4521 static bool FPUModeIsVFP(FPUMode Mode) { 4522 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4523 } 4524 4525 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4526 static const char * const GCCRegNames[]; 4527 4528 std::string ABI, CPU; 4529 4530 StringRef CPUProfile; 4531 StringRef CPUAttr; 4532 4533 enum { 4534 FP_Default, 4535 FP_VFP, 4536 FP_Neon 4537 } FPMath; 4538 4539 unsigned ArchISA; 4540 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4541 unsigned ArchProfile; 4542 unsigned ArchVersion; 4543 4544 unsigned FPU : 5; 4545 4546 unsigned IsAAPCS : 1; 4547 unsigned HWDiv : 2; 4548 4549 // Initialized via features. 4550 unsigned SoftFloat : 1; 4551 unsigned SoftFloatABI : 1; 4552 4553 unsigned CRC : 1; 4554 unsigned Crypto : 1; 4555 unsigned DSP : 1; 4556 unsigned Unaligned : 1; 4557 4558 enum { 4559 LDREX_B = (1 << 0), /// byte (8-bit) 4560 LDREX_H = (1 << 1), /// half (16-bit) 4561 LDREX_W = (1 << 2), /// word (32-bit) 4562 LDREX_D = (1 << 3), /// double (64-bit) 4563 }; 4564 4565 uint32_t LDREX; 4566 4567 // ACLE 6.5.1 Hardware floating point 4568 enum { 4569 HW_FP_HP = (1 << 1), /// half (16-bit) 4570 HW_FP_SP = (1 << 2), /// single (32-bit) 4571 HW_FP_DP = (1 << 3), /// double (64-bit) 4572 }; 4573 uint32_t HW_FP; 4574 4575 static const Builtin::Info BuiltinInfo[]; 4576 4577 void setABIAAPCS() { 4578 IsAAPCS = true; 4579 4580 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4581 const llvm::Triple &T = getTriple(); 4582 4583 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4584 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4585 T.getOS() == llvm::Triple::Bitrig) 4586 SizeType = UnsignedLong; 4587 else 4588 SizeType = UnsignedInt; 4589 4590 switch (T.getOS()) { 4591 case llvm::Triple::NetBSD: 4592 WCharType = SignedInt; 4593 break; 4594 case llvm::Triple::Win32: 4595 WCharType = UnsignedShort; 4596 break; 4597 case llvm::Triple::Linux: 4598 default: 4599 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4600 WCharType = UnsignedInt; 4601 break; 4602 } 4603 4604 UseBitFieldTypeAlignment = true; 4605 4606 ZeroLengthBitfieldBoundary = 0; 4607 4608 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4609 // so set preferred for small types to 32. 4610 if (T.isOSBinFormatMachO()) { 4611 resetDataLayout(BigEndian 4612 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4613 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4614 } else if (T.isOSWindows()) { 4615 assert(!BigEndian && "Windows on ARM does not support big endian"); 4616 resetDataLayout("e" 4617 "-m:w" 4618 "-p:32:32" 4619 "-i64:64" 4620 "-v128:64:128" 4621 "-a:0:32" 4622 "-n32" 4623 "-S64"); 4624 } else if (T.isOSNaCl()) { 4625 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4626 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4627 } else { 4628 resetDataLayout(BigEndian 4629 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4630 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4631 } 4632 4633 // FIXME: Enumerated types are variable width in straight AAPCS. 4634 } 4635 4636 void setABIAPCS(bool IsAAPCS16) { 4637 const llvm::Triple &T = getTriple(); 4638 4639 IsAAPCS = false; 4640 4641 if (IsAAPCS16) 4642 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4643 else 4644 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4645 4646 // size_t is unsigned int on FreeBSD. 4647 if (T.getOS() == llvm::Triple::FreeBSD) 4648 SizeType = UnsignedInt; 4649 else 4650 SizeType = UnsignedLong; 4651 4652 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4653 WCharType = SignedInt; 4654 4655 // Do not respect the alignment of bit-field types when laying out 4656 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4657 UseBitFieldTypeAlignment = false; 4658 4659 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4660 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4661 /// gcc. 4662 ZeroLengthBitfieldBoundary = 32; 4663 4664 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4665 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4666 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4667 } else if (T.isOSBinFormatMachO()) 4668 resetDataLayout( 4669 BigEndian 4670 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4671 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4672 else 4673 resetDataLayout( 4674 BigEndian 4675 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4676 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4677 4678 // FIXME: Override "preferred align" for double and long long. 4679 } 4680 4681 void setArchInfo() { 4682 StringRef ArchName = getTriple().getArchName(); 4683 4684 ArchISA = llvm::ARM::parseArchISA(ArchName); 4685 CPU = llvm::ARM::getDefaultCPU(ArchName); 4686 unsigned AK = llvm::ARM::parseArch(ArchName); 4687 if (AK != llvm::ARM::AK_INVALID) 4688 ArchKind = AK; 4689 setArchInfo(ArchKind); 4690 } 4691 4692 void setArchInfo(unsigned Kind) { 4693 StringRef SubArch; 4694 4695 // cache TargetParser info 4696 ArchKind = Kind; 4697 SubArch = llvm::ARM::getSubArch(ArchKind); 4698 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4699 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4700 4701 // cache CPU related strings 4702 CPUAttr = getCPUAttr(); 4703 CPUProfile = getCPUProfile(); 4704 } 4705 4706 void setAtomic() { 4707 // when triple does not specify a sub arch, 4708 // then we are not using inline atomics 4709 bool ShouldUseInlineAtomic = 4710 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4711 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4712 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4713 if (ArchProfile == llvm::ARM::PK_M) { 4714 MaxAtomicPromoteWidth = 32; 4715 if (ShouldUseInlineAtomic) 4716 MaxAtomicInlineWidth = 32; 4717 } 4718 else { 4719 MaxAtomicPromoteWidth = 64; 4720 if (ShouldUseInlineAtomic) 4721 MaxAtomicInlineWidth = 64; 4722 } 4723 } 4724 4725 bool isThumb() const { 4726 return (ArchISA == llvm::ARM::IK_THUMB); 4727 } 4728 4729 bool supportsThumb() const { 4730 return CPUAttr.count('T') || ArchVersion >= 6; 4731 } 4732 4733 bool supportsThumb2() const { 4734 return CPUAttr.equals("6T2") || 4735 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4736 } 4737 4738 StringRef getCPUAttr() const { 4739 // For most sub-arches, the build attribute CPU name is enough. 4740 // For Cortex variants, it's slightly different. 4741 switch(ArchKind) { 4742 default: 4743 return llvm::ARM::getCPUAttr(ArchKind); 4744 case llvm::ARM::AK_ARMV6M: 4745 return "6M"; 4746 case llvm::ARM::AK_ARMV7S: 4747 return "7S"; 4748 case llvm::ARM::AK_ARMV7A: 4749 return "7A"; 4750 case llvm::ARM::AK_ARMV7R: 4751 return "7R"; 4752 case llvm::ARM::AK_ARMV7M: 4753 return "7M"; 4754 case llvm::ARM::AK_ARMV7EM: 4755 return "7EM"; 4756 case llvm::ARM::AK_ARMV8A: 4757 return "8A"; 4758 case llvm::ARM::AK_ARMV8_1A: 4759 return "8_1A"; 4760 case llvm::ARM::AK_ARMV8_2A: 4761 return "8_2A"; 4762 case llvm::ARM::AK_ARMV8MBaseline: 4763 return "8M_BASE"; 4764 case llvm::ARM::AK_ARMV8MMainline: 4765 return "8M_MAIN"; 4766 } 4767 } 4768 4769 StringRef getCPUProfile() const { 4770 switch(ArchProfile) { 4771 case llvm::ARM::PK_A: 4772 return "A"; 4773 case llvm::ARM::PK_R: 4774 return "R"; 4775 case llvm::ARM::PK_M: 4776 return "M"; 4777 default: 4778 return ""; 4779 } 4780 } 4781 4782 public: 4783 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 4784 bool IsBigEndian) 4785 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4786 HW_FP(0) { 4787 BigEndian = IsBigEndian; 4788 4789 switch (getTriple().getOS()) { 4790 case llvm::Triple::NetBSD: 4791 PtrDiffType = SignedLong; 4792 break; 4793 default: 4794 PtrDiffType = SignedInt; 4795 break; 4796 } 4797 4798 // Cache arch related info. 4799 setArchInfo(); 4800 4801 // {} in inline assembly are neon specifiers, not assembly variant 4802 // specifiers. 4803 NoAsmVariants = true; 4804 4805 // FIXME: This duplicates code from the driver that sets the -target-abi 4806 // option - this code is used if -target-abi isn't passed and should 4807 // be unified in some way. 4808 if (Triple.isOSBinFormatMachO()) { 4809 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4810 // the frontend matches that. 4811 if (Triple.getEnvironment() == llvm::Triple::EABI || 4812 Triple.getOS() == llvm::Triple::UnknownOS || 4813 StringRef(CPU).startswith("cortex-m")) { 4814 setABI("aapcs"); 4815 } else if (Triple.isWatchABI()) { 4816 setABI("aapcs16"); 4817 } else { 4818 setABI("apcs-gnu"); 4819 } 4820 } else if (Triple.isOSWindows()) { 4821 // FIXME: this is invalid for WindowsCE 4822 setABI("aapcs"); 4823 } else { 4824 // Select the default based on the platform. 4825 switch (Triple.getEnvironment()) { 4826 case llvm::Triple::Android: 4827 case llvm::Triple::GNUEABI: 4828 case llvm::Triple::GNUEABIHF: 4829 setABI("aapcs-linux"); 4830 break; 4831 case llvm::Triple::EABIHF: 4832 case llvm::Triple::EABI: 4833 setABI("aapcs"); 4834 break; 4835 case llvm::Triple::GNU: 4836 setABI("apcs-gnu"); 4837 break; 4838 default: 4839 if (Triple.getOS() == llvm::Triple::NetBSD) 4840 setABI("apcs-gnu"); 4841 else 4842 setABI("aapcs"); 4843 break; 4844 } 4845 } 4846 4847 // ARM targets default to using the ARM C++ ABI. 4848 TheCXXABI.set(TargetCXXABI::GenericARM); 4849 4850 // ARM has atomics up to 8 bytes 4851 setAtomic(); 4852 4853 // Do force alignment of members that follow zero length bitfields. If 4854 // the alignment of the zero-length bitfield is greater than the member 4855 // that follows it, `bar', `bar' will be aligned as the type of the 4856 // zero length bitfield. 4857 UseZeroLengthBitfieldAlignment = true; 4858 4859 if (Triple.getOS() == llvm::Triple::Linux || 4860 Triple.getOS() == llvm::Triple::UnknownOS) 4861 this->MCountName = 4862 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 4863 } 4864 4865 StringRef getABI() const override { return ABI; } 4866 4867 bool setABI(const std::string &Name) override { 4868 ABI = Name; 4869 4870 // The defaults (above) are for AAPCS, check if we need to change them. 4871 // 4872 // FIXME: We need support for -meabi... we could just mangle it into the 4873 // name. 4874 if (Name == "apcs-gnu" || Name == "aapcs16") { 4875 setABIAPCS(Name == "aapcs16"); 4876 return true; 4877 } 4878 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4879 setABIAAPCS(); 4880 return true; 4881 } 4882 return false; 4883 } 4884 4885 // FIXME: This should be based on Arch attributes, not CPU names. 4886 bool 4887 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4888 StringRef CPU, 4889 const std::vector<std::string> &FeaturesVec) const override { 4890 4891 std::vector<const char*> TargetFeatures; 4892 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4893 4894 // get default FPU features 4895 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4896 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4897 4898 // get default Extension features 4899 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4900 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4901 4902 for (const char *Feature : TargetFeatures) 4903 if (Feature[0] == '+') 4904 Features[Feature+1] = true; 4905 4906 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4907 } 4908 4909 bool handleTargetFeatures(std::vector<std::string> &Features, 4910 DiagnosticsEngine &Diags) override { 4911 FPU = 0; 4912 CRC = 0; 4913 Crypto = 0; 4914 DSP = 0; 4915 Unaligned = 1; 4916 SoftFloat = SoftFloatABI = false; 4917 HWDiv = 0; 4918 4919 // This does not diagnose illegal cases like having both 4920 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4921 uint32_t HW_FP_remove = 0; 4922 for (const auto &Feature : Features) { 4923 if (Feature == "+soft-float") { 4924 SoftFloat = true; 4925 } else if (Feature == "+soft-float-abi") { 4926 SoftFloatABI = true; 4927 } else if (Feature == "+vfp2") { 4928 FPU |= VFP2FPU; 4929 HW_FP |= HW_FP_SP | HW_FP_DP; 4930 } else if (Feature == "+vfp3") { 4931 FPU |= VFP3FPU; 4932 HW_FP |= HW_FP_SP | HW_FP_DP; 4933 } else if (Feature == "+vfp4") { 4934 FPU |= VFP4FPU; 4935 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4936 } else if (Feature == "+fp-armv8") { 4937 FPU |= FPARMV8; 4938 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4939 } else if (Feature == "+neon") { 4940 FPU |= NeonFPU; 4941 HW_FP |= HW_FP_SP | HW_FP_DP; 4942 } else if (Feature == "+hwdiv") { 4943 HWDiv |= HWDivThumb; 4944 } else if (Feature == "+hwdiv-arm") { 4945 HWDiv |= HWDivARM; 4946 } else if (Feature == "+crc") { 4947 CRC = 1; 4948 } else if (Feature == "+crypto") { 4949 Crypto = 1; 4950 } else if (Feature == "+dsp") { 4951 DSP = 1; 4952 } else if (Feature == "+fp-only-sp") { 4953 HW_FP_remove |= HW_FP_DP; 4954 } else if (Feature == "+strict-align") { 4955 Unaligned = 0; 4956 } else if (Feature == "+fp16") { 4957 HW_FP |= HW_FP_HP; 4958 } 4959 } 4960 HW_FP &= ~HW_FP_remove; 4961 4962 switch (ArchVersion) { 4963 case 6: 4964 if (ArchProfile == llvm::ARM::PK_M) 4965 LDREX = 0; 4966 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4967 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4968 else 4969 LDREX = LDREX_W; 4970 break; 4971 case 7: 4972 if (ArchProfile == llvm::ARM::PK_M) 4973 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4974 else 4975 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4976 break; 4977 case 8: 4978 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4979 } 4980 4981 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4982 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4983 return false; 4984 } 4985 4986 if (FPMath == FP_Neon) 4987 Features.push_back("+neonfp"); 4988 else if (FPMath == FP_VFP) 4989 Features.push_back("-neonfp"); 4990 4991 // Remove front-end specific options which the backend handles differently. 4992 auto Feature = 4993 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4994 if (Feature != Features.end()) 4995 Features.erase(Feature); 4996 4997 return true; 4998 } 4999 5000 bool hasFeature(StringRef Feature) const override { 5001 return llvm::StringSwitch<bool>(Feature) 5002 .Case("arm", true) 5003 .Case("aarch32", true) 5004 .Case("softfloat", SoftFloat) 5005 .Case("thumb", isThumb()) 5006 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5007 .Case("hwdiv", HWDiv & HWDivThumb) 5008 .Case("hwdiv-arm", HWDiv & HWDivARM) 5009 .Default(false); 5010 } 5011 5012 bool setCPU(const std::string &Name) override { 5013 if (Name != "generic") 5014 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5015 5016 if (ArchKind == llvm::ARM::AK_INVALID) 5017 return false; 5018 setAtomic(); 5019 CPU = Name; 5020 return true; 5021 } 5022 5023 bool setFPMath(StringRef Name) override; 5024 5025 void getTargetDefines(const LangOptions &Opts, 5026 MacroBuilder &Builder) const override { 5027 // Target identification. 5028 Builder.defineMacro("__arm"); 5029 Builder.defineMacro("__arm__"); 5030 // For bare-metal none-eabi. 5031 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5032 getTriple().getEnvironment() == llvm::Triple::EABI) 5033 Builder.defineMacro("__ELF__"); 5034 5035 // Target properties. 5036 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5037 5038 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5039 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5040 if (getTriple().isWatchABI()) 5041 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5042 5043 if (!CPUAttr.empty()) 5044 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5045 5046 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5047 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5048 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5049 5050 if (ArchVersion >= 8) { 5051 // ACLE 6.5.7 Crypto Extension 5052 if (Crypto) 5053 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5054 // ACLE 6.5.8 CRC32 Extension 5055 if (CRC) 5056 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5057 // ACLE 6.5.10 Numeric Maximum and Minimum 5058 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5059 // ACLE 6.5.9 Directed Rounding 5060 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5061 } 5062 5063 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5064 // is not defined for the M-profile. 5065 // NOTE that the default profile is assumed to be 'A' 5066 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5067 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5068 5069 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5070 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5071 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5072 // v7 and v8 architectures excluding v8-M Baseline. 5073 if (supportsThumb2()) 5074 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5075 else if (supportsThumb()) 5076 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5077 5078 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5079 // instruction set such as ARM or Thumb. 5080 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5081 5082 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5083 5084 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5085 if (!CPUProfile.empty()) 5086 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5087 5088 // ACLE 6.4.3 Unaligned access supported in hardware 5089 if (Unaligned) 5090 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5091 5092 // ACLE 6.4.4 LDREX/STREX 5093 if (LDREX) 5094 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5095 5096 // ACLE 6.4.5 CLZ 5097 if (ArchVersion == 5 || 5098 (ArchVersion == 6 && CPUProfile != "M") || 5099 ArchVersion > 6) 5100 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5101 5102 // ACLE 6.5.1 Hardware Floating Point 5103 if (HW_FP) 5104 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5105 5106 // ACLE predefines. 5107 Builder.defineMacro("__ARM_ACLE", "200"); 5108 5109 // FP16 support (we currently only support IEEE format). 5110 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5111 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5112 5113 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5114 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5115 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5116 5117 // Subtarget options. 5118 5119 // FIXME: It's more complicated than this and we don't really support 5120 // interworking. 5121 // Windows on ARM does not "support" interworking 5122 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5123 Builder.defineMacro("__THUMB_INTERWORK__"); 5124 5125 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5126 // Embedded targets on Darwin follow AAPCS, but not EABI. 5127 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5128 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5129 Builder.defineMacro("__ARM_EABI__"); 5130 Builder.defineMacro("__ARM_PCS", "1"); 5131 } 5132 5133 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5134 ABI == "aapcs16") 5135 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5136 5137 if (SoftFloat) 5138 Builder.defineMacro("__SOFTFP__"); 5139 5140 if (CPU == "xscale") 5141 Builder.defineMacro("__XSCALE__"); 5142 5143 if (isThumb()) { 5144 Builder.defineMacro("__THUMBEL__"); 5145 Builder.defineMacro("__thumb__"); 5146 if (supportsThumb2()) 5147 Builder.defineMacro("__thumb2__"); 5148 } 5149 5150 // ACLE 6.4.9 32-bit SIMD instructions 5151 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5152 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5153 5154 // ACLE 6.4.10 Hardware Integer Divide 5155 if (((HWDiv & HWDivThumb) && isThumb()) || 5156 ((HWDiv & HWDivARM) && !isThumb())) { 5157 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5158 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5159 } 5160 5161 // Note, this is always on in gcc, even though it doesn't make sense. 5162 Builder.defineMacro("__APCS_32__"); 5163 5164 if (FPUModeIsVFP((FPUMode) FPU)) { 5165 Builder.defineMacro("__VFP_FP__"); 5166 if (FPU & VFP2FPU) 5167 Builder.defineMacro("__ARM_VFPV2__"); 5168 if (FPU & VFP3FPU) 5169 Builder.defineMacro("__ARM_VFPV3__"); 5170 if (FPU & VFP4FPU) 5171 Builder.defineMacro("__ARM_VFPV4__"); 5172 } 5173 5174 // This only gets set when Neon instructions are actually available, unlike 5175 // the VFP define, hence the soft float and arch check. This is subtly 5176 // different from gcc, we follow the intent which was that it should be set 5177 // when Neon instructions are actually available. 5178 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5179 Builder.defineMacro("__ARM_NEON", "1"); 5180 Builder.defineMacro("__ARM_NEON__"); 5181 // current AArch32 NEON implementations do not support double-precision 5182 // floating-point even when it is present in VFP. 5183 Builder.defineMacro("__ARM_NEON_FP", 5184 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5185 } 5186 5187 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5188 Opts.ShortWChar ? "2" : "4"); 5189 5190 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5191 Opts.ShortEnums ? "1" : "4"); 5192 5193 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5194 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5195 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5196 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5197 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5198 } 5199 5200 // ACLE 6.4.7 DSP instructions 5201 if (DSP) { 5202 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5203 } 5204 5205 // ACLE 6.4.8 Saturation instructions 5206 bool SAT = false; 5207 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5208 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5209 SAT = true; 5210 } 5211 5212 // ACLE 6.4.6 Q (saturation) flag 5213 if (DSP || SAT) 5214 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5215 5216 if (Opts.UnsafeFPMath) 5217 Builder.defineMacro("__ARM_FP_FAST", "1"); 5218 5219 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5220 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5221 } 5222 5223 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5224 return llvm::makeArrayRef(BuiltinInfo, 5225 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5226 } 5227 bool isCLZForZeroUndef() const override { return false; } 5228 BuiltinVaListKind getBuiltinVaListKind() const override { 5229 return IsAAPCS 5230 ? AAPCSABIBuiltinVaList 5231 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5232 : TargetInfo::VoidPtrBuiltinVaList); 5233 } 5234 ArrayRef<const char *> getGCCRegNames() const override; 5235 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5236 bool validateAsmConstraint(const char *&Name, 5237 TargetInfo::ConstraintInfo &Info) const override { 5238 switch (*Name) { 5239 default: break; 5240 case 'l': // r0-r7 5241 case 'h': // r8-r15 5242 case 't': // VFP Floating point register single precision 5243 case 'w': // VFP Floating point register double precision 5244 Info.setAllowsRegister(); 5245 return true; 5246 case 'I': 5247 case 'J': 5248 case 'K': 5249 case 'L': 5250 case 'M': 5251 // FIXME 5252 return true; 5253 case 'Q': // A memory address that is a single base register. 5254 Info.setAllowsMemory(); 5255 return true; 5256 case 'U': // a memory reference... 5257 switch (Name[1]) { 5258 case 'q': // ...ARMV4 ldrsb 5259 case 'v': // ...VFP load/store (reg+constant offset) 5260 case 'y': // ...iWMMXt load/store 5261 case 't': // address valid for load/store opaque types wider 5262 // than 128-bits 5263 case 'n': // valid address for Neon doubleword vector load/store 5264 case 'm': // valid address for Neon element and structure load/store 5265 case 's': // valid address for non-offset loads/stores of quad-word 5266 // values in four ARM registers 5267 Info.setAllowsMemory(); 5268 Name++; 5269 return true; 5270 } 5271 } 5272 return false; 5273 } 5274 std::string convertConstraint(const char *&Constraint) const override { 5275 std::string R; 5276 switch (*Constraint) { 5277 case 'U': // Two-character constraint; add "^" hint for later parsing. 5278 R = std::string("^") + std::string(Constraint, 2); 5279 Constraint++; 5280 break; 5281 case 'p': // 'p' should be translated to 'r' by default. 5282 R = std::string("r"); 5283 break; 5284 default: 5285 return std::string(1, *Constraint); 5286 } 5287 return R; 5288 } 5289 bool 5290 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5291 std::string &SuggestedModifier) const override { 5292 bool isOutput = (Constraint[0] == '='); 5293 bool isInOut = (Constraint[0] == '+'); 5294 5295 // Strip off constraint modifiers. 5296 while (Constraint[0] == '=' || 5297 Constraint[0] == '+' || 5298 Constraint[0] == '&') 5299 Constraint = Constraint.substr(1); 5300 5301 switch (Constraint[0]) { 5302 default: break; 5303 case 'r': { 5304 switch (Modifier) { 5305 default: 5306 return (isInOut || isOutput || Size <= 64); 5307 case 'q': 5308 // A register of size 32 cannot fit a vector type. 5309 return false; 5310 } 5311 } 5312 } 5313 5314 return true; 5315 } 5316 const char *getClobbers() const override { 5317 // FIXME: Is this really right? 5318 return ""; 5319 } 5320 5321 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5322 switch (CC) { 5323 case CC_AAPCS: 5324 case CC_AAPCS_VFP: 5325 case CC_Swift: 5326 return CCCR_OK; 5327 default: 5328 return CCCR_Warning; 5329 } 5330 } 5331 5332 int getEHDataRegisterNumber(unsigned RegNo) const override { 5333 if (RegNo == 0) return 0; 5334 if (RegNo == 1) return 1; 5335 return -1; 5336 } 5337 5338 bool hasSjLjLowering() const override { 5339 return true; 5340 } 5341 }; 5342 5343 bool ARMTargetInfo::setFPMath(StringRef Name) { 5344 if (Name == "neon") { 5345 FPMath = FP_Neon; 5346 return true; 5347 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5348 Name == "vfp4") { 5349 FPMath = FP_VFP; 5350 return true; 5351 } 5352 return false; 5353 } 5354 5355 const char * const ARMTargetInfo::GCCRegNames[] = { 5356 // Integer registers 5357 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5358 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5359 5360 // Float registers 5361 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5362 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5363 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5364 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5365 5366 // Double registers 5367 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5368 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5369 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5370 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5371 5372 // Quad registers 5373 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5374 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5375 }; 5376 5377 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5378 return llvm::makeArrayRef(GCCRegNames); 5379 } 5380 5381 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5382 { { "a1" }, "r0" }, 5383 { { "a2" }, "r1" }, 5384 { { "a3" }, "r2" }, 5385 { { "a4" }, "r3" }, 5386 { { "v1" }, "r4" }, 5387 { { "v2" }, "r5" }, 5388 { { "v3" }, "r6" }, 5389 { { "v4" }, "r7" }, 5390 { { "v5" }, "r8" }, 5391 { { "v6", "rfp" }, "r9" }, 5392 { { "sl" }, "r10" }, 5393 { { "fp" }, "r11" }, 5394 { { "ip" }, "r12" }, 5395 { { "r13" }, "sp" }, 5396 { { "r14" }, "lr" }, 5397 { { "r15" }, "pc" }, 5398 // The S, D and Q registers overlap, but aren't really aliases; we 5399 // don't want to substitute one of these for a different-sized one. 5400 }; 5401 5402 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5403 return llvm::makeArrayRef(GCCRegAliases); 5404 } 5405 5406 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5407 #define BUILTIN(ID, TYPE, ATTRS) \ 5408 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5409 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5410 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5411 #include "clang/Basic/BuiltinsNEON.def" 5412 5413 #define BUILTIN(ID, TYPE, ATTRS) \ 5414 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5415 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5416 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5417 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5418 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5419 #include "clang/Basic/BuiltinsARM.def" 5420 }; 5421 5422 class ARMleTargetInfo : public ARMTargetInfo { 5423 public: 5424 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5425 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/false) {} 5426 void getTargetDefines(const LangOptions &Opts, 5427 MacroBuilder &Builder) const override { 5428 Builder.defineMacro("__ARMEL__"); 5429 ARMTargetInfo::getTargetDefines(Opts, Builder); 5430 } 5431 }; 5432 5433 class ARMbeTargetInfo : public ARMTargetInfo { 5434 public: 5435 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5436 : ARMTargetInfo(Triple, Opts, /*BigEndian=*/true) {} 5437 void getTargetDefines(const LangOptions &Opts, 5438 MacroBuilder &Builder) const override { 5439 Builder.defineMacro("__ARMEB__"); 5440 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5441 ARMTargetInfo::getTargetDefines(Opts, Builder); 5442 } 5443 }; 5444 5445 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5446 const llvm::Triple Triple; 5447 public: 5448 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5449 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5450 WCharType = UnsignedShort; 5451 SizeType = UnsignedInt; 5452 } 5453 void getVisualStudioDefines(const LangOptions &Opts, 5454 MacroBuilder &Builder) const { 5455 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5456 5457 // FIXME: this is invalid for WindowsCE 5458 Builder.defineMacro("_M_ARM_NT", "1"); 5459 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5460 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5461 5462 assert((Triple.getArch() == llvm::Triple::arm || 5463 Triple.getArch() == llvm::Triple::thumb) && 5464 "invalid architecture for Windows ARM target info"); 5465 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5466 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5467 5468 // TODO map the complete set of values 5469 // 31: VFPv3 40: VFPv4 5470 Builder.defineMacro("_M_ARM_FP", "31"); 5471 } 5472 BuiltinVaListKind getBuiltinVaListKind() const override { 5473 return TargetInfo::CharPtrBuiltinVaList; 5474 } 5475 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5476 switch (CC) { 5477 case CC_X86StdCall: 5478 case CC_X86ThisCall: 5479 case CC_X86FastCall: 5480 case CC_X86VectorCall: 5481 return CCCR_Ignore; 5482 case CC_C: 5483 return CCCR_OK; 5484 default: 5485 return CCCR_Warning; 5486 } 5487 } 5488 }; 5489 5490 // Windows ARM + Itanium C++ ABI Target 5491 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5492 public: 5493 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5494 const TargetOptions &Opts) 5495 : WindowsARMTargetInfo(Triple, Opts) { 5496 TheCXXABI.set(TargetCXXABI::GenericARM); 5497 } 5498 5499 void getTargetDefines(const LangOptions &Opts, 5500 MacroBuilder &Builder) const override { 5501 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5502 5503 if (Opts.MSVCCompat) 5504 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5505 } 5506 }; 5507 5508 // Windows ARM, MS (C++) ABI 5509 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5510 public: 5511 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5512 const TargetOptions &Opts) 5513 : WindowsARMTargetInfo(Triple, Opts) { 5514 TheCXXABI.set(TargetCXXABI::Microsoft); 5515 } 5516 5517 void getTargetDefines(const LangOptions &Opts, 5518 MacroBuilder &Builder) const override { 5519 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5520 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5521 } 5522 }; 5523 5524 // ARM MinGW target 5525 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5526 public: 5527 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5528 : WindowsARMTargetInfo(Triple, Opts) { 5529 TheCXXABI.set(TargetCXXABI::GenericARM); 5530 } 5531 5532 void getTargetDefines(const LangOptions &Opts, 5533 MacroBuilder &Builder) const override { 5534 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5535 DefineStd(Builder, "WIN32", Opts); 5536 DefineStd(Builder, "WINNT", Opts); 5537 Builder.defineMacro("_ARM_"); 5538 addMinGWDefines(Opts, Builder); 5539 } 5540 }; 5541 5542 // ARM Cygwin target 5543 class CygwinARMTargetInfo : public ARMleTargetInfo { 5544 public: 5545 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5546 : ARMleTargetInfo(Triple, Opts) { 5547 TLSSupported = false; 5548 WCharType = UnsignedShort; 5549 DoubleAlign = LongLongAlign = 64; 5550 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5551 } 5552 void getTargetDefines(const LangOptions &Opts, 5553 MacroBuilder &Builder) const override { 5554 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5555 Builder.defineMacro("_ARM_"); 5556 Builder.defineMacro("__CYGWIN__"); 5557 Builder.defineMacro("__CYGWIN32__"); 5558 DefineStd(Builder, "unix", Opts); 5559 if (Opts.CPlusPlus) 5560 Builder.defineMacro("_GNU_SOURCE"); 5561 } 5562 }; 5563 5564 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5565 protected: 5566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5567 MacroBuilder &Builder) const override { 5568 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5569 } 5570 5571 public: 5572 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5573 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5574 HasAlignMac68kSupport = true; 5575 // iOS always has 64-bit atomic instructions. 5576 // FIXME: This should be based off of the target features in 5577 // ARMleTargetInfo. 5578 MaxAtomicInlineWidth = 64; 5579 5580 if (Triple.isWatchABI()) { 5581 // Darwin on iOS uses a variant of the ARM C++ ABI. 5582 TheCXXABI.set(TargetCXXABI::WatchOS); 5583 5584 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5585 // size_t is long, it's a bit weird for it to be int. 5586 PtrDiffType = SignedLong; 5587 5588 // BOOL should be a real boolean on the new ABI 5589 UseSignedCharForObjCBool = false; 5590 } else 5591 TheCXXABI.set(TargetCXXABI::iOS); 5592 } 5593 }; 5594 5595 class AArch64TargetInfo : public TargetInfo { 5596 virtual void setDataLayout() = 0; 5597 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5598 static const char *const GCCRegNames[]; 5599 5600 enum FPUModeEnum { 5601 FPUMode, 5602 NeonMode 5603 }; 5604 5605 unsigned FPU; 5606 unsigned CRC; 5607 unsigned Crypto; 5608 unsigned Unaligned; 5609 unsigned V8_1A; 5610 5611 static const Builtin::Info BuiltinInfo[]; 5612 5613 std::string ABI; 5614 5615 public: 5616 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5617 : TargetInfo(Triple), ABI("aapcs") { 5618 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5619 WCharType = SignedInt; 5620 5621 // NetBSD apparently prefers consistency across ARM targets to consistency 5622 // across 64-bit targets. 5623 Int64Type = SignedLongLong; 5624 IntMaxType = SignedLongLong; 5625 } else { 5626 WCharType = UnsignedInt; 5627 Int64Type = SignedLong; 5628 IntMaxType = SignedLong; 5629 } 5630 5631 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5632 MaxVectorAlign = 128; 5633 MaxAtomicInlineWidth = 128; 5634 MaxAtomicPromoteWidth = 128; 5635 5636 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5637 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5638 5639 // {} in inline assembly are neon specifiers, not assembly variant 5640 // specifiers. 5641 NoAsmVariants = true; 5642 5643 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5644 // contributes to the alignment of the containing aggregate in the same way 5645 // a plain (non bit-field) member of that type would, without exception for 5646 // zero-sized or anonymous bit-fields." 5647 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5648 UseZeroLengthBitfieldAlignment = true; 5649 5650 // AArch64 targets default to using the ARM C++ ABI. 5651 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5652 5653 if (Triple.getOS() == llvm::Triple::Linux || 5654 Triple.getOS() == llvm::Triple::UnknownOS) 5655 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5656 } 5657 5658 StringRef getABI() const override { return ABI; } 5659 bool setABI(const std::string &Name) override { 5660 if (Name != "aapcs" && Name != "darwinpcs") 5661 return false; 5662 5663 ABI = Name; 5664 return true; 5665 } 5666 5667 bool setCPU(const std::string &Name) override { 5668 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5669 .Case("generic", true) 5670 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5671 "cortex-a35", "exynos-m1", true) 5672 .Case("cyclone", true) 5673 .Case("kryo", true) 5674 .Default(false); 5675 return CPUKnown; 5676 } 5677 5678 void getTargetDefines(const LangOptions &Opts, 5679 MacroBuilder &Builder) const override { 5680 // Target identification. 5681 Builder.defineMacro("__aarch64__"); 5682 5683 // Target properties. 5684 Builder.defineMacro("_LP64"); 5685 Builder.defineMacro("__LP64__"); 5686 5687 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5688 Builder.defineMacro("__ARM_ACLE", "200"); 5689 Builder.defineMacro("__ARM_ARCH", "8"); 5690 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5691 5692 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5693 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5694 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5695 5696 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5697 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5698 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5699 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5700 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5701 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5702 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5703 5704 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5705 5706 // 0xe implies support for half, single and double precision operations. 5707 Builder.defineMacro("__ARM_FP", "0xE"); 5708 5709 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5710 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5711 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5712 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5713 5714 if (Opts.UnsafeFPMath) 5715 Builder.defineMacro("__ARM_FP_FAST", "1"); 5716 5717 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5718 5719 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5720 Opts.ShortEnums ? "1" : "4"); 5721 5722 if (FPU == NeonMode) { 5723 Builder.defineMacro("__ARM_NEON", "1"); 5724 // 64-bit NEON supports half, single and double precision operations. 5725 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5726 } 5727 5728 if (CRC) 5729 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5730 5731 if (Crypto) 5732 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5733 5734 if (Unaligned) 5735 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5736 5737 if (V8_1A) 5738 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5739 5740 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5741 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5742 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5743 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5744 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5745 } 5746 5747 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5748 return llvm::makeArrayRef(BuiltinInfo, 5749 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5750 } 5751 5752 bool hasFeature(StringRef Feature) const override { 5753 return Feature == "aarch64" || 5754 Feature == "arm64" || 5755 Feature == "arm" || 5756 (Feature == "neon" && FPU == NeonMode); 5757 } 5758 5759 bool handleTargetFeatures(std::vector<std::string> &Features, 5760 DiagnosticsEngine &Diags) override { 5761 FPU = FPUMode; 5762 CRC = 0; 5763 Crypto = 0; 5764 Unaligned = 1; 5765 V8_1A = 0; 5766 5767 for (const auto &Feature : Features) { 5768 if (Feature == "+neon") 5769 FPU = NeonMode; 5770 if (Feature == "+crc") 5771 CRC = 1; 5772 if (Feature == "+crypto") 5773 Crypto = 1; 5774 if (Feature == "+strict-align") 5775 Unaligned = 0; 5776 if (Feature == "+v8.1a") 5777 V8_1A = 1; 5778 } 5779 5780 setDataLayout(); 5781 5782 return true; 5783 } 5784 5785 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5786 switch (CC) { 5787 case CC_C: 5788 case CC_Swift: 5789 case CC_PreserveMost: 5790 case CC_PreserveAll: 5791 return CCCR_OK; 5792 default: 5793 return CCCR_Warning; 5794 } 5795 } 5796 5797 bool isCLZForZeroUndef() const override { return false; } 5798 5799 BuiltinVaListKind getBuiltinVaListKind() const override { 5800 return TargetInfo::AArch64ABIBuiltinVaList; 5801 } 5802 5803 ArrayRef<const char *> getGCCRegNames() const override; 5804 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5805 5806 bool validateAsmConstraint(const char *&Name, 5807 TargetInfo::ConstraintInfo &Info) const override { 5808 switch (*Name) { 5809 default: 5810 return false; 5811 case 'w': // Floating point and SIMD registers (V0-V31) 5812 Info.setAllowsRegister(); 5813 return true; 5814 case 'I': // Constant that can be used with an ADD instruction 5815 case 'J': // Constant that can be used with a SUB instruction 5816 case 'K': // Constant that can be used with a 32-bit logical instruction 5817 case 'L': // Constant that can be used with a 64-bit logical instruction 5818 case 'M': // Constant that can be used as a 32-bit MOV immediate 5819 case 'N': // Constant that can be used as a 64-bit MOV immediate 5820 case 'Y': // Floating point constant zero 5821 case 'Z': // Integer constant zero 5822 return true; 5823 case 'Q': // A memory reference with base register and no offset 5824 Info.setAllowsMemory(); 5825 return true; 5826 case 'S': // A symbolic address 5827 Info.setAllowsRegister(); 5828 return true; 5829 case 'U': 5830 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5831 // Utf: A memory address suitable for ldp/stp in TF mode. 5832 // Usa: An absolute symbolic address. 5833 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5834 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5835 case 'z': // Zero register, wzr or xzr 5836 Info.setAllowsRegister(); 5837 return true; 5838 case 'x': // Floating point and SIMD registers (V0-V15) 5839 Info.setAllowsRegister(); 5840 return true; 5841 } 5842 return false; 5843 } 5844 5845 bool 5846 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5847 std::string &SuggestedModifier) const override { 5848 // Strip off constraint modifiers. 5849 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5850 Constraint = Constraint.substr(1); 5851 5852 switch (Constraint[0]) { 5853 default: 5854 return true; 5855 case 'z': 5856 case 'r': { 5857 switch (Modifier) { 5858 case 'x': 5859 case 'w': 5860 // For now assume that the person knows what they're 5861 // doing with the modifier. 5862 return true; 5863 default: 5864 // By default an 'r' constraint will be in the 'x' 5865 // registers. 5866 if (Size == 64) 5867 return true; 5868 5869 SuggestedModifier = "w"; 5870 return false; 5871 } 5872 } 5873 } 5874 } 5875 5876 const char *getClobbers() const override { return ""; } 5877 5878 int getEHDataRegisterNumber(unsigned RegNo) const override { 5879 if (RegNo == 0) 5880 return 0; 5881 if (RegNo == 1) 5882 return 1; 5883 return -1; 5884 } 5885 }; 5886 5887 const char *const AArch64TargetInfo::GCCRegNames[] = { 5888 // 32-bit Integer registers 5889 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5890 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5891 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5892 5893 // 64-bit Integer registers 5894 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5895 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5896 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5897 5898 // 32-bit floating point regsisters 5899 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5900 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5901 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5902 5903 // 64-bit floating point regsisters 5904 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5905 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5906 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5907 5908 // Vector registers 5909 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5910 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5911 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5912 }; 5913 5914 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5915 return llvm::makeArrayRef(GCCRegNames); 5916 } 5917 5918 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5919 { { "w31" }, "wsp" }, 5920 { { "x29" }, "fp" }, 5921 { { "x30" }, "lr" }, 5922 { { "x31" }, "sp" }, 5923 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5924 // don't want to substitute one of these for a different-sized one. 5925 }; 5926 5927 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5928 return llvm::makeArrayRef(GCCRegAliases); 5929 } 5930 5931 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5932 #define BUILTIN(ID, TYPE, ATTRS) \ 5933 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5934 #include "clang/Basic/BuiltinsNEON.def" 5935 5936 #define BUILTIN(ID, TYPE, ATTRS) \ 5937 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5938 #include "clang/Basic/BuiltinsAArch64.def" 5939 }; 5940 5941 class AArch64leTargetInfo : public AArch64TargetInfo { 5942 void setDataLayout() override { 5943 if (getTriple().isOSBinFormatMachO()) 5944 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 5945 else 5946 resetDataLayout("e-m:e-i64:64-i128:128-n32:64-S128"); 5947 } 5948 5949 public: 5950 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5951 : AArch64TargetInfo(Triple, Opts) { 5952 BigEndian = false; 5953 } 5954 void getTargetDefines(const LangOptions &Opts, 5955 MacroBuilder &Builder) const override { 5956 Builder.defineMacro("__AARCH64EL__"); 5957 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5958 } 5959 }; 5960 5961 class AArch64beTargetInfo : public AArch64TargetInfo { 5962 void setDataLayout() override { 5963 assert(!getTriple().isOSBinFormatMachO()); 5964 resetDataLayout("E-m:e-i64:64-i128:128-n32:64-S128"); 5965 } 5966 5967 public: 5968 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5969 : AArch64TargetInfo(Triple, Opts) {} 5970 void getTargetDefines(const LangOptions &Opts, 5971 MacroBuilder &Builder) const override { 5972 Builder.defineMacro("__AARCH64EB__"); 5973 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5974 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5975 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5976 } 5977 }; 5978 5979 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5980 protected: 5981 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5982 MacroBuilder &Builder) const override { 5983 Builder.defineMacro("__AARCH64_SIMD__"); 5984 Builder.defineMacro("__ARM64_ARCH_8__"); 5985 Builder.defineMacro("__ARM_NEON__"); 5986 Builder.defineMacro("__LITTLE_ENDIAN__"); 5987 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5988 Builder.defineMacro("__arm64", "1"); 5989 Builder.defineMacro("__arm64__", "1"); 5990 5991 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5992 } 5993 5994 public: 5995 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5996 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 5997 Int64Type = SignedLongLong; 5998 WCharType = SignedInt; 5999 UseSignedCharForObjCBool = false; 6000 6001 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6002 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6003 6004 TheCXXABI.set(TargetCXXABI::iOS64); 6005 } 6006 6007 BuiltinVaListKind getBuiltinVaListKind() const override { 6008 return TargetInfo::CharPtrBuiltinVaList; 6009 } 6010 }; 6011 6012 // Hexagon abstract base class 6013 class HexagonTargetInfo : public TargetInfo { 6014 static const Builtin::Info BuiltinInfo[]; 6015 static const char * const GCCRegNames[]; 6016 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6017 std::string CPU; 6018 bool HasHVX, HasHVXDouble; 6019 6020 public: 6021 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6022 : TargetInfo(Triple) { 6023 BigEndian = false; 6024 // Specify the vector alignment explicitly. For v512x1, the calculated 6025 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6026 // the required minimum of 64 bytes. 6027 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6028 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6029 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6030 SizeType = UnsignedInt; 6031 PtrDiffType = SignedInt; 6032 IntPtrType = SignedInt; 6033 6034 // {} in inline assembly are packet specifiers, not assembly variant 6035 // specifiers. 6036 NoAsmVariants = true; 6037 6038 LargeArrayMinWidth = 64; 6039 LargeArrayAlign = 64; 6040 UseBitFieldTypeAlignment = true; 6041 ZeroLengthBitfieldBoundary = 32; 6042 HasHVX = HasHVXDouble = false; 6043 } 6044 6045 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6046 return llvm::makeArrayRef(BuiltinInfo, 6047 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6048 } 6049 6050 bool validateAsmConstraint(const char *&Name, 6051 TargetInfo::ConstraintInfo &Info) const override { 6052 switch (*Name) { 6053 case 'v': 6054 case 'q': 6055 if (HasHVX) { 6056 Info.setAllowsRegister(); 6057 return true; 6058 } 6059 break; 6060 case 's': 6061 // Relocatable constant. 6062 return true; 6063 } 6064 return false; 6065 } 6066 6067 void getTargetDefines(const LangOptions &Opts, 6068 MacroBuilder &Builder) const override; 6069 6070 bool isCLZForZeroUndef() const override { return false; } 6071 6072 bool hasFeature(StringRef Feature) const override { 6073 return llvm::StringSwitch<bool>(Feature) 6074 .Case("hexagon", true) 6075 .Case("hvx", HasHVX) 6076 .Case("hvx-double", HasHVXDouble) 6077 .Default(false); 6078 } 6079 6080 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6081 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6082 const override; 6083 6084 bool handleTargetFeatures(std::vector<std::string> &Features, 6085 DiagnosticsEngine &Diags) override; 6086 6087 BuiltinVaListKind getBuiltinVaListKind() const override { 6088 return TargetInfo::CharPtrBuiltinVaList; 6089 } 6090 ArrayRef<const char *> getGCCRegNames() const override; 6091 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6092 const char *getClobbers() const override { 6093 return ""; 6094 } 6095 6096 static const char *getHexagonCPUSuffix(StringRef Name) { 6097 return llvm::StringSwitch<const char*>(Name) 6098 .Case("hexagonv4", "4") 6099 .Case("hexagonv5", "5") 6100 .Case("hexagonv55", "55") 6101 .Case("hexagonv60", "60") 6102 .Default(nullptr); 6103 } 6104 6105 bool setCPU(const std::string &Name) override { 6106 if (!getHexagonCPUSuffix(Name)) 6107 return false; 6108 CPU = Name; 6109 return true; 6110 } 6111 6112 int getEHDataRegisterNumber(unsigned RegNo) const override { 6113 return RegNo < 2 ? RegNo : -1; 6114 } 6115 }; 6116 6117 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6118 MacroBuilder &Builder) const { 6119 Builder.defineMacro("__qdsp6__", "1"); 6120 Builder.defineMacro("__hexagon__", "1"); 6121 6122 if (CPU == "hexagonv4") { 6123 Builder.defineMacro("__HEXAGON_V4__"); 6124 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6125 if (Opts.HexagonQdsp6Compat) { 6126 Builder.defineMacro("__QDSP6_V4__"); 6127 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6128 } 6129 } else if (CPU == "hexagonv5") { 6130 Builder.defineMacro("__HEXAGON_V5__"); 6131 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6132 if(Opts.HexagonQdsp6Compat) { 6133 Builder.defineMacro("__QDSP6_V5__"); 6134 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6135 } 6136 } else if (CPU == "hexagonv55") { 6137 Builder.defineMacro("__HEXAGON_V55__"); 6138 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6139 Builder.defineMacro("__QDSP6_V55__"); 6140 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6141 } else if (CPU == "hexagonv60") { 6142 Builder.defineMacro("__HEXAGON_V60__"); 6143 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6144 Builder.defineMacro("__QDSP6_V60__"); 6145 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6146 } 6147 6148 if (hasFeature("hvx")) { 6149 Builder.defineMacro("__HVX__"); 6150 if (hasFeature("hvx-double")) 6151 Builder.defineMacro("__HVXDBL__"); 6152 } 6153 } 6154 6155 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6156 DiagnosticsEngine &Diags) { 6157 for (auto &F : Features) { 6158 if (F == "+hvx") 6159 HasHVX = true; 6160 else if (F == "-hvx") 6161 HasHVX = HasHVXDouble = false; 6162 else if (F == "+hvx-double") 6163 HasHVX = HasHVXDouble = true; 6164 else if (F == "-hvx-double") 6165 HasHVXDouble = false; 6166 } 6167 return true; 6168 } 6169 6170 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6171 DiagnosticsEngine &Diags, StringRef CPU, 6172 const std::vector<std::string> &FeaturesVec) const { 6173 // Default for v60: -hvx, -hvx-double. 6174 Features["hvx"] = false; 6175 Features["hvx-double"] = false; 6176 6177 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6178 } 6179 6180 6181 const char *const HexagonTargetInfo::GCCRegNames[] = { 6182 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6183 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6184 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6185 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6186 "p0", "p1", "p2", "p3", 6187 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6188 }; 6189 6190 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6191 return llvm::makeArrayRef(GCCRegNames); 6192 } 6193 6194 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6195 { { "sp" }, "r29" }, 6196 { { "fp" }, "r30" }, 6197 { { "lr" }, "r31" }, 6198 }; 6199 6200 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6201 return llvm::makeArrayRef(GCCRegAliases); 6202 } 6203 6204 6205 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6206 #define BUILTIN(ID, TYPE, ATTRS) \ 6207 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6208 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6209 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6210 #include "clang/Basic/BuiltinsHexagon.def" 6211 }; 6212 6213 class LanaiTargetInfo : public TargetInfo { 6214 // Class for Lanai (32-bit). 6215 // The CPU profiles supported by the Lanai backend 6216 enum CPUKind { 6217 CK_NONE, 6218 CK_V11, 6219 } CPU; 6220 6221 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6222 static const char *const GCCRegNames[]; 6223 6224 public: 6225 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6226 : TargetInfo(Triple) { 6227 // Description string has to be kept in sync with backend. 6228 resetDataLayout("E" // Big endian 6229 "-m:e" // ELF name manging 6230 "-p:32:32" // 32 bit pointers, 32 bit aligned 6231 "-i64:64" // 64 bit integers, 64 bit aligned 6232 "-a:0:32" // 32 bit alignment of objects of aggregate type 6233 "-n32" // 32 bit native integer width 6234 "-S64" // 64 bit natural stack alignment 6235 ); 6236 6237 // Setting RegParmMax equal to what mregparm was set to in the old 6238 // toolchain 6239 RegParmMax = 4; 6240 6241 // Set the default CPU to V11 6242 CPU = CK_V11; 6243 6244 // Temporary approach to make everything at least word-aligned and allow for 6245 // safely casting between pointers with different alignment requirements. 6246 // TODO: Remove this when there are no more cast align warnings on the 6247 // firmware. 6248 MinGlobalAlign = 32; 6249 } 6250 6251 void getTargetDefines(const LangOptions &Opts, 6252 MacroBuilder &Builder) const override { 6253 // Define __lanai__ when building for target lanai. 6254 Builder.defineMacro("__lanai__"); 6255 6256 // Set define for the CPU specified. 6257 switch (CPU) { 6258 case CK_V11: 6259 Builder.defineMacro("__LANAI_V11__"); 6260 break; 6261 case CK_NONE: 6262 llvm_unreachable("Unhandled target CPU"); 6263 } 6264 } 6265 6266 bool setCPU(const std::string &Name) override { 6267 CPU = llvm::StringSwitch<CPUKind>(Name) 6268 .Case("v11", CK_V11) 6269 .Default(CK_NONE); 6270 6271 return CPU != CK_NONE; 6272 } 6273 6274 bool hasFeature(StringRef Feature) const override { 6275 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6276 } 6277 6278 ArrayRef<const char *> getGCCRegNames() const override; 6279 6280 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6281 6282 BuiltinVaListKind getBuiltinVaListKind() const override { 6283 return TargetInfo::VoidPtrBuiltinVaList; 6284 } 6285 6286 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6287 6288 bool validateAsmConstraint(const char *&Name, 6289 TargetInfo::ConstraintInfo &info) const override { 6290 return false; 6291 } 6292 6293 const char *getClobbers() const override { return ""; } 6294 }; 6295 6296 const char *const LanaiTargetInfo::GCCRegNames[] = { 6297 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6298 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6299 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6300 6301 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6302 return llvm::makeArrayRef(GCCRegNames); 6303 } 6304 6305 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6306 {{"pc"}, "r2"}, 6307 {{"sp"}, "r4"}, 6308 {{"fp"}, "r5"}, 6309 {{"rv"}, "r8"}, 6310 {{"rr1"}, "r10"}, 6311 {{"rr2"}, "r11"}, 6312 {{"rca"}, "r15"}, 6313 }; 6314 6315 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6316 return llvm::makeArrayRef(GCCRegAliases); 6317 } 6318 6319 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6320 class SparcTargetInfo : public TargetInfo { 6321 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6322 static const char * const GCCRegNames[]; 6323 bool SoftFloat; 6324 public: 6325 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6326 : TargetInfo(Triple), SoftFloat(false) {} 6327 6328 int getEHDataRegisterNumber(unsigned RegNo) const override { 6329 if (RegNo == 0) return 24; 6330 if (RegNo == 1) return 25; 6331 return -1; 6332 } 6333 6334 bool handleTargetFeatures(std::vector<std::string> &Features, 6335 DiagnosticsEngine &Diags) override { 6336 // The backend doesn't actually handle soft float yet, but in case someone 6337 // is using the support for the front end continue to support it. 6338 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6339 if (Feature != Features.end()) { 6340 SoftFloat = true; 6341 Features.erase(Feature); 6342 } 6343 return true; 6344 } 6345 void getTargetDefines(const LangOptions &Opts, 6346 MacroBuilder &Builder) const override { 6347 DefineStd(Builder, "sparc", Opts); 6348 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6349 6350 if (SoftFloat) 6351 Builder.defineMacro("SOFT_FLOAT", "1"); 6352 } 6353 6354 bool hasFeature(StringRef Feature) const override { 6355 return llvm::StringSwitch<bool>(Feature) 6356 .Case("softfloat", SoftFloat) 6357 .Case("sparc", true) 6358 .Default(false); 6359 } 6360 6361 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6362 // FIXME: Implement! 6363 return None; 6364 } 6365 BuiltinVaListKind getBuiltinVaListKind() const override { 6366 return TargetInfo::VoidPtrBuiltinVaList; 6367 } 6368 ArrayRef<const char *> getGCCRegNames() const override; 6369 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6370 bool validateAsmConstraint(const char *&Name, 6371 TargetInfo::ConstraintInfo &info) const override { 6372 // FIXME: Implement! 6373 switch (*Name) { 6374 case 'I': // Signed 13-bit constant 6375 case 'J': // Zero 6376 case 'K': // 32-bit constant with the low 12 bits clear 6377 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6378 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6379 case 'N': // Same as 'K' but zext (required for SIMode) 6380 case 'O': // The constant 4096 6381 return true; 6382 } 6383 return false; 6384 } 6385 const char *getClobbers() const override { 6386 // FIXME: Implement! 6387 return ""; 6388 } 6389 6390 // No Sparc V7 for now, the backend doesn't support it anyway. 6391 enum CPUKind { 6392 CK_GENERIC, 6393 CK_V8, 6394 CK_SUPERSPARC, 6395 CK_SPARCLITE, 6396 CK_F934, 6397 CK_HYPERSPARC, 6398 CK_SPARCLITE86X, 6399 CK_SPARCLET, 6400 CK_TSC701, 6401 CK_V9, 6402 CK_ULTRASPARC, 6403 CK_ULTRASPARC3, 6404 CK_NIAGARA, 6405 CK_NIAGARA2, 6406 CK_NIAGARA3, 6407 CK_NIAGARA4, 6408 CK_MYRIAD2_1, 6409 CK_MYRIAD2_2 6410 } CPU = CK_GENERIC; 6411 6412 enum CPUGeneration { 6413 CG_V8, 6414 CG_V9, 6415 }; 6416 6417 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6418 switch (Kind) { 6419 case CK_GENERIC: 6420 case CK_V8: 6421 case CK_SUPERSPARC: 6422 case CK_SPARCLITE: 6423 case CK_F934: 6424 case CK_HYPERSPARC: 6425 case CK_SPARCLITE86X: 6426 case CK_SPARCLET: 6427 case CK_TSC701: 6428 case CK_MYRIAD2_1: 6429 case CK_MYRIAD2_2: 6430 return CG_V8; 6431 case CK_V9: 6432 case CK_ULTRASPARC: 6433 case CK_ULTRASPARC3: 6434 case CK_NIAGARA: 6435 case CK_NIAGARA2: 6436 case CK_NIAGARA3: 6437 case CK_NIAGARA4: 6438 return CG_V9; 6439 } 6440 llvm_unreachable("Unexpected CPU kind"); 6441 } 6442 6443 CPUKind getCPUKind(StringRef Name) const { 6444 return llvm::StringSwitch<CPUKind>(Name) 6445 .Case("v8", CK_V8) 6446 .Case("supersparc", CK_SUPERSPARC) 6447 .Case("sparclite", CK_SPARCLITE) 6448 .Case("f934", CK_F934) 6449 .Case("hypersparc", CK_HYPERSPARC) 6450 .Case("sparclite86x", CK_SPARCLITE86X) 6451 .Case("sparclet", CK_SPARCLET) 6452 .Case("tsc701", CK_TSC701) 6453 .Case("v9", CK_V9) 6454 .Case("ultrasparc", CK_ULTRASPARC) 6455 .Case("ultrasparc3", CK_ULTRASPARC3) 6456 .Case("niagara", CK_NIAGARA) 6457 .Case("niagara2", CK_NIAGARA2) 6458 .Case("niagara3", CK_NIAGARA3) 6459 .Case("niagara4", CK_NIAGARA4) 6460 .Case("myriad2", CK_MYRIAD2_1) 6461 .Case("myriad2.1", CK_MYRIAD2_1) 6462 .Case("myriad2.2", CK_MYRIAD2_2) 6463 .Default(CK_GENERIC); 6464 } 6465 6466 bool setCPU(const std::string &Name) override { 6467 CPU = getCPUKind(Name); 6468 return CPU != CK_GENERIC; 6469 } 6470 }; 6471 6472 const char * const SparcTargetInfo::GCCRegNames[] = { 6473 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6474 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6475 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6476 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6477 }; 6478 6479 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6480 return llvm::makeArrayRef(GCCRegNames); 6481 } 6482 6483 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6484 { { "g0" }, "r0" }, 6485 { { "g1" }, "r1" }, 6486 { { "g2" }, "r2" }, 6487 { { "g3" }, "r3" }, 6488 { { "g4" }, "r4" }, 6489 { { "g5" }, "r5" }, 6490 { { "g6" }, "r6" }, 6491 { { "g7" }, "r7" }, 6492 { { "o0" }, "r8" }, 6493 { { "o1" }, "r9" }, 6494 { { "o2" }, "r10" }, 6495 { { "o3" }, "r11" }, 6496 { { "o4" }, "r12" }, 6497 { { "o5" }, "r13" }, 6498 { { "o6", "sp" }, "r14" }, 6499 { { "o7" }, "r15" }, 6500 { { "l0" }, "r16" }, 6501 { { "l1" }, "r17" }, 6502 { { "l2" }, "r18" }, 6503 { { "l3" }, "r19" }, 6504 { { "l4" }, "r20" }, 6505 { { "l5" }, "r21" }, 6506 { { "l6" }, "r22" }, 6507 { { "l7" }, "r23" }, 6508 { { "i0" }, "r24" }, 6509 { { "i1" }, "r25" }, 6510 { { "i2" }, "r26" }, 6511 { { "i3" }, "r27" }, 6512 { { "i4" }, "r28" }, 6513 { { "i5" }, "r29" }, 6514 { { "i6", "fp" }, "r30" }, 6515 { { "i7" }, "r31" }, 6516 }; 6517 6518 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6519 return llvm::makeArrayRef(GCCRegAliases); 6520 } 6521 6522 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6523 class SparcV8TargetInfo : public SparcTargetInfo { 6524 public: 6525 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6526 : SparcTargetInfo(Triple, Opts) { 6527 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6528 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6529 switch (getTriple().getOS()) { 6530 default: 6531 SizeType = UnsignedInt; 6532 IntPtrType = SignedInt; 6533 PtrDiffType = SignedInt; 6534 break; 6535 case llvm::Triple::NetBSD: 6536 case llvm::Triple::OpenBSD: 6537 SizeType = UnsignedLong; 6538 IntPtrType = SignedLong; 6539 PtrDiffType = SignedLong; 6540 break; 6541 } 6542 } 6543 6544 void getTargetDefines(const LangOptions &Opts, 6545 MacroBuilder &Builder) const override { 6546 SparcTargetInfo::getTargetDefines(Opts, Builder); 6547 switch (getCPUGeneration(CPU)) { 6548 case CG_V8: 6549 Builder.defineMacro("__sparcv8"); 6550 if (getTriple().getOS() != llvm::Triple::Solaris) 6551 Builder.defineMacro("__sparcv8__"); 6552 break; 6553 case CG_V9: 6554 Builder.defineMacro("__sparcv9"); 6555 if (getTriple().getOS() != llvm::Triple::Solaris) { 6556 Builder.defineMacro("__sparcv9__"); 6557 Builder.defineMacro("__sparc_v9__"); 6558 } 6559 break; 6560 } 6561 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6562 switch (CPU) { 6563 case CK_MYRIAD2_1: 6564 Builder.defineMacro("__myriad2", "1"); 6565 Builder.defineMacro("__myriad2__", "1"); 6566 break; 6567 case CK_MYRIAD2_2: 6568 Builder.defineMacro("__myriad2", "2"); 6569 Builder.defineMacro("__myriad2__", "2"); 6570 break; 6571 default: 6572 break; 6573 } 6574 } 6575 } 6576 6577 bool hasSjLjLowering() const override { 6578 return true; 6579 } 6580 }; 6581 6582 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6583 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6584 public: 6585 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6586 : SparcV8TargetInfo(Triple, Opts) { 6587 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6588 BigEndian = false; 6589 } 6590 }; 6591 6592 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6593 class SparcV9TargetInfo : public SparcTargetInfo { 6594 public: 6595 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6596 : SparcTargetInfo(Triple, Opts) { 6597 // FIXME: Support Sparc quad-precision long double? 6598 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6599 // This is an LP64 platform. 6600 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6601 6602 // OpenBSD uses long long for int64_t and intmax_t. 6603 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6604 IntMaxType = SignedLongLong; 6605 else 6606 IntMaxType = SignedLong; 6607 Int64Type = IntMaxType; 6608 6609 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6610 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6611 LongDoubleWidth = 128; 6612 LongDoubleAlign = 128; 6613 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6614 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6615 } 6616 6617 void getTargetDefines(const LangOptions &Opts, 6618 MacroBuilder &Builder) const override { 6619 SparcTargetInfo::getTargetDefines(Opts, Builder); 6620 Builder.defineMacro("__sparcv9"); 6621 Builder.defineMacro("__arch64__"); 6622 // Solaris doesn't need these variants, but the BSDs do. 6623 if (getTriple().getOS() != llvm::Triple::Solaris) { 6624 Builder.defineMacro("__sparc64__"); 6625 Builder.defineMacro("__sparc_v9__"); 6626 Builder.defineMacro("__sparcv9__"); 6627 } 6628 } 6629 6630 bool setCPU(const std::string &Name) override { 6631 if (!SparcTargetInfo::setCPU(Name)) 6632 return false; 6633 return getCPUGeneration(CPU) == CG_V9; 6634 } 6635 }; 6636 6637 class SystemZTargetInfo : public TargetInfo { 6638 static const Builtin::Info BuiltinInfo[]; 6639 static const char *const GCCRegNames[]; 6640 std::string CPU; 6641 bool HasTransactionalExecution; 6642 bool HasVector; 6643 6644 public: 6645 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6646 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6647 HasVector(false) { 6648 IntMaxType = SignedLong; 6649 Int64Type = SignedLong; 6650 TLSSupported = true; 6651 IntWidth = IntAlign = 32; 6652 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6653 PointerWidth = PointerAlign = 64; 6654 LongDoubleWidth = 128; 6655 LongDoubleAlign = 64; 6656 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6657 DefaultAlignForAttributeAligned = 64; 6658 MinGlobalAlign = 16; 6659 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6660 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6661 } 6662 void getTargetDefines(const LangOptions &Opts, 6663 MacroBuilder &Builder) const override { 6664 Builder.defineMacro("__s390__"); 6665 Builder.defineMacro("__s390x__"); 6666 Builder.defineMacro("__zarch__"); 6667 Builder.defineMacro("__LONG_DOUBLE_128__"); 6668 6669 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6670 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6671 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6672 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6673 6674 if (HasTransactionalExecution) 6675 Builder.defineMacro("__HTM__"); 6676 if (Opts.ZVector) 6677 Builder.defineMacro("__VEC__", "10301"); 6678 } 6679 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6680 return llvm::makeArrayRef(BuiltinInfo, 6681 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6682 } 6683 6684 ArrayRef<const char *> getGCCRegNames() const override; 6685 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6686 // No aliases. 6687 return None; 6688 } 6689 bool validateAsmConstraint(const char *&Name, 6690 TargetInfo::ConstraintInfo &info) const override; 6691 const char *getClobbers() const override { 6692 // FIXME: Is this really right? 6693 return ""; 6694 } 6695 BuiltinVaListKind getBuiltinVaListKind() const override { 6696 return TargetInfo::SystemZBuiltinVaList; 6697 } 6698 bool setCPU(const std::string &Name) override { 6699 CPU = Name; 6700 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6701 .Case("z10", true) 6702 .Case("z196", true) 6703 .Case("zEC12", true) 6704 .Case("z13", true) 6705 .Default(false); 6706 6707 return CPUKnown; 6708 } 6709 bool 6710 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6711 StringRef CPU, 6712 const std::vector<std::string> &FeaturesVec) const override { 6713 if (CPU == "zEC12") 6714 Features["transactional-execution"] = true; 6715 if (CPU == "z13") { 6716 Features["transactional-execution"] = true; 6717 Features["vector"] = true; 6718 } 6719 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6720 } 6721 6722 bool handleTargetFeatures(std::vector<std::string> &Features, 6723 DiagnosticsEngine &Diags) override { 6724 HasTransactionalExecution = false; 6725 for (const auto &Feature : Features) { 6726 if (Feature == "+transactional-execution") 6727 HasTransactionalExecution = true; 6728 else if (Feature == "+vector") 6729 HasVector = true; 6730 } 6731 // If we use the vector ABI, vector types are 64-bit aligned. 6732 if (HasVector) { 6733 MaxVectorAlign = 64; 6734 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6735 "-v128:64-a:8:16-n32:64"); 6736 } 6737 return true; 6738 } 6739 6740 bool hasFeature(StringRef Feature) const override { 6741 return llvm::StringSwitch<bool>(Feature) 6742 .Case("systemz", true) 6743 .Case("htm", HasTransactionalExecution) 6744 .Case("vx", HasVector) 6745 .Default(false); 6746 } 6747 6748 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6749 switch (CC) { 6750 case CC_C: 6751 case CC_Swift: 6752 return CCCR_OK; 6753 default: 6754 return CCCR_Warning; 6755 } 6756 } 6757 6758 StringRef getABI() const override { 6759 if (HasVector) 6760 return "vector"; 6761 return ""; 6762 } 6763 6764 bool useFloat128ManglingForLongDouble() const override { 6765 return true; 6766 } 6767 }; 6768 6769 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6770 #define BUILTIN(ID, TYPE, ATTRS) \ 6771 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6772 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 6773 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 6774 #include "clang/Basic/BuiltinsSystemZ.def" 6775 }; 6776 6777 const char *const SystemZTargetInfo::GCCRegNames[] = { 6778 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6779 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6780 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6781 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6782 }; 6783 6784 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6785 return llvm::makeArrayRef(GCCRegNames); 6786 } 6787 6788 bool SystemZTargetInfo:: 6789 validateAsmConstraint(const char *&Name, 6790 TargetInfo::ConstraintInfo &Info) const { 6791 switch (*Name) { 6792 default: 6793 return false; 6794 6795 case 'a': // Address register 6796 case 'd': // Data register (equivalent to 'r') 6797 case 'f': // Floating-point register 6798 Info.setAllowsRegister(); 6799 return true; 6800 6801 case 'I': // Unsigned 8-bit constant 6802 case 'J': // Unsigned 12-bit constant 6803 case 'K': // Signed 16-bit constant 6804 case 'L': // Signed 20-bit displacement (on all targets we support) 6805 case 'M': // 0x7fffffff 6806 return true; 6807 6808 case 'Q': // Memory with base and unsigned 12-bit displacement 6809 case 'R': // Likewise, plus an index 6810 case 'S': // Memory with base and signed 20-bit displacement 6811 case 'T': // Likewise, plus an index 6812 Info.setAllowsMemory(); 6813 return true; 6814 } 6815 } 6816 6817 class MSP430TargetInfo : public TargetInfo { 6818 static const char *const GCCRegNames[]; 6819 6820 public: 6821 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6822 : TargetInfo(Triple) { 6823 BigEndian = false; 6824 TLSSupported = false; 6825 IntWidth = 16; 6826 IntAlign = 16; 6827 LongWidth = 32; 6828 LongLongWidth = 64; 6829 LongAlign = LongLongAlign = 16; 6830 PointerWidth = 16; 6831 PointerAlign = 16; 6832 SuitableAlign = 16; 6833 SizeType = UnsignedInt; 6834 IntMaxType = SignedLongLong; 6835 IntPtrType = SignedInt; 6836 PtrDiffType = SignedInt; 6837 SigAtomicType = SignedLong; 6838 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 6839 } 6840 void getTargetDefines(const LangOptions &Opts, 6841 MacroBuilder &Builder) const override { 6842 Builder.defineMacro("MSP430"); 6843 Builder.defineMacro("__MSP430__"); 6844 // FIXME: defines for different 'flavours' of MCU 6845 } 6846 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6847 // FIXME: Implement. 6848 return None; 6849 } 6850 bool hasFeature(StringRef Feature) const override { 6851 return Feature == "msp430"; 6852 } 6853 ArrayRef<const char *> getGCCRegNames() const override; 6854 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6855 // No aliases. 6856 return None; 6857 } 6858 bool validateAsmConstraint(const char *&Name, 6859 TargetInfo::ConstraintInfo &info) const override { 6860 // FIXME: implement 6861 switch (*Name) { 6862 case 'K': // the constant 1 6863 case 'L': // constant -1^20 .. 1^19 6864 case 'M': // constant 1-4: 6865 return true; 6866 } 6867 // No target constraints for now. 6868 return false; 6869 } 6870 const char *getClobbers() const override { 6871 // FIXME: Is this really right? 6872 return ""; 6873 } 6874 BuiltinVaListKind getBuiltinVaListKind() const override { 6875 // FIXME: implement 6876 return TargetInfo::CharPtrBuiltinVaList; 6877 } 6878 }; 6879 6880 const char *const MSP430TargetInfo::GCCRegNames[] = { 6881 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6882 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6883 6884 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6885 return llvm::makeArrayRef(GCCRegNames); 6886 } 6887 6888 // LLVM and Clang cannot be used directly to output native binaries for 6889 // target, but is used to compile C code to llvm bitcode with correct 6890 // type and alignment information. 6891 // 6892 // TCE uses the llvm bitcode as input and uses it for generating customized 6893 // target processor and program binary. TCE co-design environment is 6894 // publicly available in http://tce.cs.tut.fi 6895 6896 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6897 3, // opencl_global 6898 4, // opencl_local 6899 5, // opencl_constant 6900 // FIXME: generic has to be added to the target 6901 0, // opencl_generic 6902 0, // cuda_device 6903 0, // cuda_constant 6904 0 // cuda_shared 6905 }; 6906 6907 class TCETargetInfo : public TargetInfo { 6908 public: 6909 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6910 : TargetInfo(Triple) { 6911 TLSSupported = false; 6912 IntWidth = 32; 6913 LongWidth = LongLongWidth = 32; 6914 PointerWidth = 32; 6915 IntAlign = 32; 6916 LongAlign = LongLongAlign = 32; 6917 PointerAlign = 32; 6918 SuitableAlign = 32; 6919 SizeType = UnsignedInt; 6920 IntMaxType = SignedLong; 6921 IntPtrType = SignedInt; 6922 PtrDiffType = SignedInt; 6923 FloatWidth = 32; 6924 FloatAlign = 32; 6925 DoubleWidth = 32; 6926 DoubleAlign = 32; 6927 LongDoubleWidth = 32; 6928 LongDoubleAlign = 32; 6929 FloatFormat = &llvm::APFloat::IEEEsingle; 6930 DoubleFormat = &llvm::APFloat::IEEEsingle; 6931 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6932 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 6933 "-f64:32-v64:32-v128:32-a:0:32-n32"); 6934 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6935 UseAddrSpaceMapMangling = true; 6936 } 6937 6938 void getTargetDefines(const LangOptions &Opts, 6939 MacroBuilder &Builder) const override { 6940 DefineStd(Builder, "tce", Opts); 6941 Builder.defineMacro("__TCE__"); 6942 Builder.defineMacro("__TCE_V1__"); 6943 } 6944 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6945 6946 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6947 const char *getClobbers() const override { return ""; } 6948 BuiltinVaListKind getBuiltinVaListKind() const override { 6949 return TargetInfo::VoidPtrBuiltinVaList; 6950 } 6951 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6952 bool validateAsmConstraint(const char *&Name, 6953 TargetInfo::ConstraintInfo &info) const override { 6954 return true; 6955 } 6956 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6957 return None; 6958 } 6959 }; 6960 6961 class BPFTargetInfo : public TargetInfo { 6962 public: 6963 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6964 : TargetInfo(Triple) { 6965 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6966 SizeType = UnsignedLong; 6967 PtrDiffType = SignedLong; 6968 IntPtrType = SignedLong; 6969 IntMaxType = SignedLong; 6970 Int64Type = SignedLong; 6971 RegParmMax = 5; 6972 if (Triple.getArch() == llvm::Triple::bpfeb) { 6973 BigEndian = true; 6974 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 6975 } else { 6976 BigEndian = false; 6977 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 6978 } 6979 MaxAtomicPromoteWidth = 64; 6980 MaxAtomicInlineWidth = 64; 6981 TLSSupported = false; 6982 } 6983 void getTargetDefines(const LangOptions &Opts, 6984 MacroBuilder &Builder) const override { 6985 DefineStd(Builder, "bpf", Opts); 6986 Builder.defineMacro("__BPF__"); 6987 } 6988 bool hasFeature(StringRef Feature) const override { 6989 return Feature == "bpf"; 6990 } 6991 6992 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6993 const char *getClobbers() const override { 6994 return ""; 6995 } 6996 BuiltinVaListKind getBuiltinVaListKind() const override { 6997 return TargetInfo::VoidPtrBuiltinVaList; 6998 } 6999 ArrayRef<const char *> getGCCRegNames() const override { 7000 return None; 7001 } 7002 bool validateAsmConstraint(const char *&Name, 7003 TargetInfo::ConstraintInfo &info) const override { 7004 return true; 7005 } 7006 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7007 return None; 7008 } 7009 }; 7010 7011 class MipsTargetInfoBase : public TargetInfo { 7012 virtual void setDataLayout() = 0; 7013 7014 static const Builtin::Info BuiltinInfo[]; 7015 std::string CPU; 7016 bool IsMips16; 7017 bool IsMicromips; 7018 bool IsNan2008; 7019 bool IsSingleFloat; 7020 enum MipsFloatABI { 7021 HardFloat, SoftFloat 7022 } FloatABI; 7023 enum DspRevEnum { 7024 NoDSP, DSP1, DSP2 7025 } DspRev; 7026 bool HasMSA; 7027 7028 protected: 7029 bool HasFP64; 7030 std::string ABI; 7031 7032 public: 7033 MipsTargetInfoBase(const llvm::Triple &Triple, const TargetOptions &, 7034 const std::string &ABIStr, const std::string &CPUStr) 7035 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 7036 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7037 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 7038 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7039 } 7040 7041 bool isNaN2008Default() const { 7042 return CPU == "mips32r6" || CPU == "mips64r6"; 7043 } 7044 7045 bool isFP64Default() const { 7046 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7047 } 7048 7049 bool isNan2008() const override { 7050 return IsNan2008; 7051 } 7052 7053 StringRef getABI() const override { return ABI; } 7054 bool setCPU(const std::string &Name) override { 7055 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 7056 getTriple().getArch() == llvm::Triple::mipsel; 7057 CPU = Name; 7058 return llvm::StringSwitch<bool>(Name) 7059 .Case("mips1", IsMips32) 7060 .Case("mips2", IsMips32) 7061 .Case("mips3", true) 7062 .Case("mips4", true) 7063 .Case("mips5", true) 7064 .Case("mips32", IsMips32) 7065 .Case("mips32r2", IsMips32) 7066 .Case("mips32r3", IsMips32) 7067 .Case("mips32r5", IsMips32) 7068 .Case("mips32r6", IsMips32) 7069 .Case("mips64", true) 7070 .Case("mips64r2", true) 7071 .Case("mips64r3", true) 7072 .Case("mips64r5", true) 7073 .Case("mips64r6", true) 7074 .Case("octeon", true) 7075 .Case("p5600", true) 7076 .Default(false); 7077 } 7078 const std::string& getCPU() const { return CPU; } 7079 bool 7080 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7081 StringRef CPU, 7082 const std::vector<std::string> &FeaturesVec) const override { 7083 if (CPU.empty()) 7084 CPU = getCPU(); 7085 if (CPU == "octeon") 7086 Features["mips64r2"] = Features["cnmips"] = true; 7087 else 7088 Features[CPU] = true; 7089 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7090 } 7091 7092 void getTargetDefines(const LangOptions &Opts, 7093 MacroBuilder &Builder) const override { 7094 Builder.defineMacro("__mips__"); 7095 Builder.defineMacro("_mips"); 7096 if (Opts.GNUMode) 7097 Builder.defineMacro("mips"); 7098 7099 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7100 7101 switch (FloatABI) { 7102 case HardFloat: 7103 Builder.defineMacro("__mips_hard_float", Twine(1)); 7104 break; 7105 case SoftFloat: 7106 Builder.defineMacro("__mips_soft_float", Twine(1)); 7107 break; 7108 } 7109 7110 if (IsSingleFloat) 7111 Builder.defineMacro("__mips_single_float", Twine(1)); 7112 7113 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7114 Builder.defineMacro("_MIPS_FPSET", 7115 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7116 7117 if (IsMips16) 7118 Builder.defineMacro("__mips16", Twine(1)); 7119 7120 if (IsMicromips) 7121 Builder.defineMacro("__mips_micromips", Twine(1)); 7122 7123 if (IsNan2008) 7124 Builder.defineMacro("__mips_nan2008", Twine(1)); 7125 7126 switch (DspRev) { 7127 default: 7128 break; 7129 case DSP1: 7130 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7131 Builder.defineMacro("__mips_dsp", Twine(1)); 7132 break; 7133 case DSP2: 7134 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7135 Builder.defineMacro("__mips_dspr2", Twine(1)); 7136 Builder.defineMacro("__mips_dsp", Twine(1)); 7137 break; 7138 } 7139 7140 if (HasMSA) 7141 Builder.defineMacro("__mips_msa", Twine(1)); 7142 7143 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7144 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7145 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7146 7147 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7148 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7149 7150 // These shouldn't be defined for MIPS-I but there's no need to check 7151 // for that since MIPS-I isn't supported. 7152 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7153 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7154 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7155 } 7156 7157 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7158 return llvm::makeArrayRef(BuiltinInfo, 7159 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7160 } 7161 bool hasFeature(StringRef Feature) const override { 7162 return llvm::StringSwitch<bool>(Feature) 7163 .Case("mips", true) 7164 .Case("fp64", HasFP64) 7165 .Default(false); 7166 } 7167 BuiltinVaListKind getBuiltinVaListKind() const override { 7168 return TargetInfo::VoidPtrBuiltinVaList; 7169 } 7170 ArrayRef<const char *> getGCCRegNames() const override { 7171 static const char *const GCCRegNames[] = { 7172 // CPU register names 7173 // Must match second column of GCCRegAliases 7174 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7175 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7176 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7177 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7178 // Floating point register names 7179 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7180 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7181 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7182 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7183 // Hi/lo and condition register names 7184 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7185 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7186 "$ac3hi","$ac3lo", 7187 // MSA register names 7188 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7189 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7190 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7191 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7192 // MSA control register names 7193 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7194 "$msarequest", "$msamap", "$msaunmap" 7195 }; 7196 return llvm::makeArrayRef(GCCRegNames); 7197 } 7198 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 7199 bool validateAsmConstraint(const char *&Name, 7200 TargetInfo::ConstraintInfo &Info) const override { 7201 switch (*Name) { 7202 default: 7203 return false; 7204 case 'r': // CPU registers. 7205 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7206 case 'y': // Equivalent to "r", backward compatibility only. 7207 case 'f': // floating-point registers. 7208 case 'c': // $25 for indirect jumps 7209 case 'l': // lo register 7210 case 'x': // hilo register pair 7211 Info.setAllowsRegister(); 7212 return true; 7213 case 'I': // Signed 16-bit constant 7214 case 'J': // Integer 0 7215 case 'K': // Unsigned 16-bit constant 7216 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7217 case 'M': // Constants not loadable via lui, addiu, or ori 7218 case 'N': // Constant -1 to -65535 7219 case 'O': // A signed 15-bit constant 7220 case 'P': // A constant between 1 go 65535 7221 return true; 7222 case 'R': // An address that can be used in a non-macro load or store 7223 Info.setAllowsMemory(); 7224 return true; 7225 case 'Z': 7226 if (Name[1] == 'C') { // An address usable by ll, and sc. 7227 Info.setAllowsMemory(); 7228 Name++; // Skip over 'Z'. 7229 return true; 7230 } 7231 return false; 7232 } 7233 } 7234 7235 std::string convertConstraint(const char *&Constraint) const override { 7236 std::string R; 7237 switch (*Constraint) { 7238 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7239 if (Constraint[1] == 'C') { 7240 R = std::string("^") + std::string(Constraint, 2); 7241 Constraint++; 7242 return R; 7243 } 7244 break; 7245 } 7246 return TargetInfo::convertConstraint(Constraint); 7247 } 7248 7249 const char *getClobbers() const override { 7250 // In GCC, $1 is not widely used in generated code (it's used only in a few 7251 // specific situations), so there is no real need for users to add it to 7252 // the clobbers list if they want to use it in their inline assembly code. 7253 // 7254 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7255 // code generation, so using it in inline assembly without adding it to the 7256 // clobbers list can cause conflicts between the inline assembly code and 7257 // the surrounding generated code. 7258 // 7259 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7260 // operands, which will conflict with the ".set at" assembler option (which 7261 // we use only for inline assembly, in order to maintain compatibility with 7262 // GCC) and will also conflict with the user's usage of $1. 7263 // 7264 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7265 // register for generated code is to automatically clobber $1 for all inline 7266 // assembly code. 7267 // 7268 // FIXME: We should automatically clobber $1 only for inline assembly code 7269 // which actually uses it. This would allow LLVM to use $1 for inline 7270 // assembly operands if the user's assembly code doesn't use it. 7271 return "~{$1}"; 7272 } 7273 7274 bool handleTargetFeatures(std::vector<std::string> &Features, 7275 DiagnosticsEngine &Diags) override { 7276 IsMips16 = false; 7277 IsMicromips = false; 7278 IsNan2008 = isNaN2008Default(); 7279 IsSingleFloat = false; 7280 FloatABI = HardFloat; 7281 DspRev = NoDSP; 7282 HasFP64 = isFP64Default(); 7283 7284 for (const auto &Feature : Features) { 7285 if (Feature == "+single-float") 7286 IsSingleFloat = true; 7287 else if (Feature == "+soft-float") 7288 FloatABI = SoftFloat; 7289 else if (Feature == "+mips16") 7290 IsMips16 = true; 7291 else if (Feature == "+micromips") 7292 IsMicromips = true; 7293 else if (Feature == "+dsp") 7294 DspRev = std::max(DspRev, DSP1); 7295 else if (Feature == "+dspr2") 7296 DspRev = std::max(DspRev, DSP2); 7297 else if (Feature == "+msa") 7298 HasMSA = true; 7299 else if (Feature == "+fp64") 7300 HasFP64 = true; 7301 else if (Feature == "-fp64") 7302 HasFP64 = false; 7303 else if (Feature == "+nan2008") 7304 IsNan2008 = true; 7305 else if (Feature == "-nan2008") 7306 IsNan2008 = false; 7307 } 7308 7309 setDataLayout(); 7310 7311 return true; 7312 } 7313 7314 int getEHDataRegisterNumber(unsigned RegNo) const override { 7315 if (RegNo == 0) return 4; 7316 if (RegNo == 1) return 5; 7317 return -1; 7318 } 7319 7320 bool isCLZForZeroUndef() const override { return false; } 7321 }; 7322 7323 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 7324 #define BUILTIN(ID, TYPE, ATTRS) \ 7325 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7326 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7327 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7328 #include "clang/Basic/BuiltinsMips.def" 7329 }; 7330 7331 class Mips32TargetInfoBase : public MipsTargetInfoBase { 7332 public: 7333 Mips32TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7334 : MipsTargetInfoBase(Triple, Opts, "o32", "mips32r2") { 7335 SizeType = UnsignedInt; 7336 PtrDiffType = SignedInt; 7337 Int64Type = SignedLongLong; 7338 IntMaxType = Int64Type; 7339 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7340 } 7341 bool setABI(const std::string &Name) override { 7342 if (Name == "o32" || Name == "eabi") { 7343 ABI = Name; 7344 return true; 7345 } 7346 return false; 7347 } 7348 void getTargetDefines(const LangOptions &Opts, 7349 MacroBuilder &Builder) const override { 7350 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7351 7352 Builder.defineMacro("__mips", "32"); 7353 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7354 7355 const std::string& CPUStr = getCPU(); 7356 if (CPUStr == "mips32") 7357 Builder.defineMacro("__mips_isa_rev", "1"); 7358 else if (CPUStr == "mips32r2") 7359 Builder.defineMacro("__mips_isa_rev", "2"); 7360 else if (CPUStr == "mips32r3") 7361 Builder.defineMacro("__mips_isa_rev", "3"); 7362 else if (CPUStr == "mips32r5") 7363 Builder.defineMacro("__mips_isa_rev", "5"); 7364 else if (CPUStr == "mips32r6") 7365 Builder.defineMacro("__mips_isa_rev", "6"); 7366 7367 if (ABI == "o32") { 7368 Builder.defineMacro("__mips_o32"); 7369 Builder.defineMacro("_ABIO32", "1"); 7370 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7371 } 7372 else if (ABI == "eabi") 7373 Builder.defineMacro("__mips_eabi"); 7374 else 7375 llvm_unreachable("Invalid ABI for Mips32."); 7376 } 7377 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7378 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7379 { { "at" }, "$1" }, 7380 { { "v0" }, "$2" }, 7381 { { "v1" }, "$3" }, 7382 { { "a0" }, "$4" }, 7383 { { "a1" }, "$5" }, 7384 { { "a2" }, "$6" }, 7385 { { "a3" }, "$7" }, 7386 { { "t0" }, "$8" }, 7387 { { "t1" }, "$9" }, 7388 { { "t2" }, "$10" }, 7389 { { "t3" }, "$11" }, 7390 { { "t4" }, "$12" }, 7391 { { "t5" }, "$13" }, 7392 { { "t6" }, "$14" }, 7393 { { "t7" }, "$15" }, 7394 { { "s0" }, "$16" }, 7395 { { "s1" }, "$17" }, 7396 { { "s2" }, "$18" }, 7397 { { "s3" }, "$19" }, 7398 { { "s4" }, "$20" }, 7399 { { "s5" }, "$21" }, 7400 { { "s6" }, "$22" }, 7401 { { "s7" }, "$23" }, 7402 { { "t8" }, "$24" }, 7403 { { "t9" }, "$25" }, 7404 { { "k0" }, "$26" }, 7405 { { "k1" }, "$27" }, 7406 { { "gp" }, "$28" }, 7407 { { "sp","$sp" }, "$29" }, 7408 { { "fp","$fp" }, "$30" }, 7409 { { "ra" }, "$31" } 7410 }; 7411 return llvm::makeArrayRef(GCCRegAliases); 7412 } 7413 }; 7414 7415 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 7416 void setDataLayout() override { 7417 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7418 } 7419 7420 public: 7421 Mips32EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7422 : Mips32TargetInfoBase(Triple, Opts) { 7423 } 7424 void getTargetDefines(const LangOptions &Opts, 7425 MacroBuilder &Builder) const override { 7426 DefineStd(Builder, "MIPSEB", Opts); 7427 Builder.defineMacro("_MIPSEB"); 7428 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7429 } 7430 }; 7431 7432 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7433 void setDataLayout() override { 7434 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"); 7435 } 7436 7437 public: 7438 Mips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7439 : Mips32TargetInfoBase(Triple, Opts) { 7440 BigEndian = false; 7441 } 7442 void getTargetDefines(const LangOptions &Opts, 7443 MacroBuilder &Builder) const override { 7444 DefineStd(Builder, "MIPSEL", Opts); 7445 Builder.defineMacro("_MIPSEL"); 7446 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7447 } 7448 }; 7449 7450 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7451 public: 7452 Mips64TargetInfoBase(const llvm::Triple &Triple, const TargetOptions &Opts) 7453 : MipsTargetInfoBase(Triple, Opts, "n64", "mips64r2") { 7454 LongDoubleWidth = LongDoubleAlign = 128; 7455 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7456 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7457 LongDoubleWidth = LongDoubleAlign = 64; 7458 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7459 } 7460 setN64ABITypes(); 7461 SuitableAlign = 128; 7462 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7463 } 7464 7465 void setN64ABITypes() { 7466 LongWidth = LongAlign = 64; 7467 PointerWidth = PointerAlign = 64; 7468 SizeType = UnsignedLong; 7469 PtrDiffType = SignedLong; 7470 Int64Type = SignedLong; 7471 IntMaxType = Int64Type; 7472 } 7473 7474 void setN32ABITypes() { 7475 LongWidth = LongAlign = 32; 7476 PointerWidth = PointerAlign = 32; 7477 SizeType = UnsignedInt; 7478 PtrDiffType = SignedInt; 7479 Int64Type = SignedLongLong; 7480 IntMaxType = Int64Type; 7481 } 7482 7483 bool setABI(const std::string &Name) override { 7484 if (Name == "n32") { 7485 setN32ABITypes(); 7486 ABI = Name; 7487 return true; 7488 } 7489 if (Name == "n64") { 7490 setN64ABITypes(); 7491 ABI = Name; 7492 return true; 7493 } 7494 return false; 7495 } 7496 7497 void getTargetDefines(const LangOptions &Opts, 7498 MacroBuilder &Builder) const override { 7499 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7500 7501 Builder.defineMacro("__mips", "64"); 7502 Builder.defineMacro("__mips64"); 7503 Builder.defineMacro("__mips64__"); 7504 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7505 7506 const std::string& CPUStr = getCPU(); 7507 if (CPUStr == "mips64") 7508 Builder.defineMacro("__mips_isa_rev", "1"); 7509 else if (CPUStr == "mips64r2") 7510 Builder.defineMacro("__mips_isa_rev", "2"); 7511 else if (CPUStr == "mips64r3") 7512 Builder.defineMacro("__mips_isa_rev", "3"); 7513 else if (CPUStr == "mips64r5") 7514 Builder.defineMacro("__mips_isa_rev", "5"); 7515 else if (CPUStr == "mips64r6") 7516 Builder.defineMacro("__mips_isa_rev", "6"); 7517 7518 if (ABI == "n32") { 7519 Builder.defineMacro("__mips_n32"); 7520 Builder.defineMacro("_ABIN32", "2"); 7521 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7522 } 7523 else if (ABI == "n64") { 7524 Builder.defineMacro("__mips_n64"); 7525 Builder.defineMacro("_ABI64", "3"); 7526 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7527 } 7528 else 7529 llvm_unreachable("Invalid ABI for Mips64."); 7530 7531 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7532 } 7533 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7534 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7535 { { "at" }, "$1" }, 7536 { { "v0" }, "$2" }, 7537 { { "v1" }, "$3" }, 7538 { { "a0" }, "$4" }, 7539 { { "a1" }, "$5" }, 7540 { { "a2" }, "$6" }, 7541 { { "a3" }, "$7" }, 7542 { { "a4" }, "$8" }, 7543 { { "a5" }, "$9" }, 7544 { { "a6" }, "$10" }, 7545 { { "a7" }, "$11" }, 7546 { { "t0" }, "$12" }, 7547 { { "t1" }, "$13" }, 7548 { { "t2" }, "$14" }, 7549 { { "t3" }, "$15" }, 7550 { { "s0" }, "$16" }, 7551 { { "s1" }, "$17" }, 7552 { { "s2" }, "$18" }, 7553 { { "s3" }, "$19" }, 7554 { { "s4" }, "$20" }, 7555 { { "s5" }, "$21" }, 7556 { { "s6" }, "$22" }, 7557 { { "s7" }, "$23" }, 7558 { { "t8" }, "$24" }, 7559 { { "t9" }, "$25" }, 7560 { { "k0" }, "$26" }, 7561 { { "k1" }, "$27" }, 7562 { { "gp" }, "$28" }, 7563 { { "sp","$sp" }, "$29" }, 7564 { { "fp","$fp" }, "$30" }, 7565 { { "ra" }, "$31" } 7566 }; 7567 return llvm::makeArrayRef(GCCRegAliases); 7568 } 7569 7570 bool hasInt128Type() const override { return true; } 7571 }; 7572 7573 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7574 void setDataLayout() override { 7575 if (ABI == "n32") 7576 resetDataLayout("E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7577 else 7578 resetDataLayout("E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7579 } 7580 7581 public: 7582 Mips64EBTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7583 : Mips64TargetInfoBase(Triple, Opts) {} 7584 void getTargetDefines(const LangOptions &Opts, 7585 MacroBuilder &Builder) const override { 7586 DefineStd(Builder, "MIPSEB", Opts); 7587 Builder.defineMacro("_MIPSEB"); 7588 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7589 } 7590 }; 7591 7592 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7593 void setDataLayout() override { 7594 if (ABI == "n32") 7595 resetDataLayout("e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7596 else 7597 resetDataLayout("e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"); 7598 } 7599 public: 7600 Mips64ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7601 : Mips64TargetInfoBase(Triple, Opts) { 7602 // Default ABI is n64. 7603 BigEndian = false; 7604 } 7605 void getTargetDefines(const LangOptions &Opts, 7606 MacroBuilder &Builder) const override { 7607 DefineStd(Builder, "MIPSEL", Opts); 7608 Builder.defineMacro("_MIPSEL"); 7609 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7610 } 7611 }; 7612 7613 class PNaClTargetInfo : public TargetInfo { 7614 public: 7615 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7616 : TargetInfo(Triple) { 7617 BigEndian = false; 7618 this->LongAlign = 32; 7619 this->LongWidth = 32; 7620 this->PointerAlign = 32; 7621 this->PointerWidth = 32; 7622 this->IntMaxType = TargetInfo::SignedLongLong; 7623 this->Int64Type = TargetInfo::SignedLongLong; 7624 this->DoubleAlign = 64; 7625 this->LongDoubleWidth = 64; 7626 this->LongDoubleAlign = 64; 7627 this->SizeType = TargetInfo::UnsignedInt; 7628 this->PtrDiffType = TargetInfo::SignedInt; 7629 this->IntPtrType = TargetInfo::SignedInt; 7630 this->RegParmMax = 0; // Disallow regparm 7631 } 7632 7633 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7634 Builder.defineMacro("__le32__"); 7635 Builder.defineMacro("__pnacl__"); 7636 } 7637 void getTargetDefines(const LangOptions &Opts, 7638 MacroBuilder &Builder) const override { 7639 getArchDefines(Opts, Builder); 7640 } 7641 bool hasFeature(StringRef Feature) const override { 7642 return Feature == "pnacl"; 7643 } 7644 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7645 BuiltinVaListKind getBuiltinVaListKind() const override { 7646 return TargetInfo::PNaClABIBuiltinVaList; 7647 } 7648 ArrayRef<const char *> getGCCRegNames() const override; 7649 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7650 bool validateAsmConstraint(const char *&Name, 7651 TargetInfo::ConstraintInfo &Info) const override { 7652 return false; 7653 } 7654 7655 const char *getClobbers() const override { 7656 return ""; 7657 } 7658 }; 7659 7660 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7661 return None; 7662 } 7663 7664 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7665 return None; 7666 } 7667 7668 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7669 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7670 public: 7671 NaClMips32ELTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7672 : Mips32ELTargetInfo(Triple, Opts) {} 7673 7674 BuiltinVaListKind getBuiltinVaListKind() const override { 7675 return TargetInfo::PNaClABIBuiltinVaList; 7676 } 7677 }; 7678 7679 class Le64TargetInfo : public TargetInfo { 7680 static const Builtin::Info BuiltinInfo[]; 7681 7682 public: 7683 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7684 : TargetInfo(Triple) { 7685 BigEndian = false; 7686 NoAsmVariants = true; 7687 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7688 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7689 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7690 } 7691 7692 void getTargetDefines(const LangOptions &Opts, 7693 MacroBuilder &Builder) const override { 7694 DefineStd(Builder, "unix", Opts); 7695 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7696 Builder.defineMacro("__ELF__"); 7697 } 7698 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7699 return llvm::makeArrayRef(BuiltinInfo, 7700 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7701 } 7702 BuiltinVaListKind getBuiltinVaListKind() const override { 7703 return TargetInfo::PNaClABIBuiltinVaList; 7704 } 7705 const char *getClobbers() const override { return ""; } 7706 ArrayRef<const char *> getGCCRegNames() const override { 7707 return None; 7708 } 7709 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7710 return None; 7711 } 7712 bool validateAsmConstraint(const char *&Name, 7713 TargetInfo::ConstraintInfo &Info) const override { 7714 return false; 7715 } 7716 7717 bool hasProtectedVisibility() const override { return false; } 7718 }; 7719 7720 class WebAssemblyTargetInfo : public TargetInfo { 7721 static const Builtin::Info BuiltinInfo[]; 7722 7723 enum SIMDEnum { 7724 NoSIMD, 7725 SIMD128, 7726 } SIMDLevel; 7727 7728 public: 7729 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7730 : TargetInfo(T), SIMDLevel(NoSIMD) { 7731 BigEndian = false; 7732 NoAsmVariants = true; 7733 SuitableAlign = 128; 7734 LargeArrayMinWidth = 128; 7735 LargeArrayAlign = 128; 7736 SimdDefaultAlign = 128; 7737 SigAtomicType = SignedLong; 7738 LongDoubleWidth = LongDoubleAlign = 128; 7739 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7740 } 7741 7742 protected: 7743 void getTargetDefines(const LangOptions &Opts, 7744 MacroBuilder &Builder) const override { 7745 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7746 if (SIMDLevel >= SIMD128) 7747 Builder.defineMacro("__wasm_simd128__"); 7748 } 7749 7750 private: 7751 bool 7752 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7753 StringRef CPU, 7754 const std::vector<std::string> &FeaturesVec) const override { 7755 if (CPU == "bleeding-edge") 7756 Features["simd128"] = true; 7757 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7758 } 7759 bool hasFeature(StringRef Feature) const final { 7760 return llvm::StringSwitch<bool>(Feature) 7761 .Case("simd128", SIMDLevel >= SIMD128) 7762 .Default(false); 7763 } 7764 bool handleTargetFeatures(std::vector<std::string> &Features, 7765 DiagnosticsEngine &Diags) final { 7766 for (const auto &Feature : Features) { 7767 if (Feature == "+simd128") { 7768 SIMDLevel = std::max(SIMDLevel, SIMD128); 7769 continue; 7770 } 7771 if (Feature == "-simd128") { 7772 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7773 continue; 7774 } 7775 7776 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7777 << "-target-feature"; 7778 return false; 7779 } 7780 return true; 7781 } 7782 bool setCPU(const std::string &Name) final { 7783 return llvm::StringSwitch<bool>(Name) 7784 .Case("mvp", true) 7785 .Case("bleeding-edge", true) 7786 .Case("generic", true) 7787 .Default(false); 7788 } 7789 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7790 return llvm::makeArrayRef(BuiltinInfo, 7791 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7792 } 7793 BuiltinVaListKind getBuiltinVaListKind() const final { 7794 return VoidPtrBuiltinVaList; 7795 } 7796 ArrayRef<const char *> getGCCRegNames() const final { 7797 return None; 7798 } 7799 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7800 return None; 7801 } 7802 bool 7803 validateAsmConstraint(const char *&Name, 7804 TargetInfo::ConstraintInfo &Info) const final { 7805 return false; 7806 } 7807 const char *getClobbers() const final { return ""; } 7808 bool isCLZForZeroUndef() const final { return false; } 7809 bool hasInt128Type() const final { return true; } 7810 IntType getIntTypeByWidth(unsigned BitWidth, 7811 bool IsSigned) const final { 7812 // WebAssembly prefers long long for explicitly 64-bit integers. 7813 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7814 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7815 } 7816 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7817 bool IsSigned) const final { 7818 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7819 return BitWidth == 64 7820 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7821 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7822 } 7823 }; 7824 7825 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7826 #define BUILTIN(ID, TYPE, ATTRS) \ 7827 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7828 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7829 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7830 #include "clang/Basic/BuiltinsWebAssembly.def" 7831 }; 7832 7833 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7834 public: 7835 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 7836 const TargetOptions &Opts) 7837 : WebAssemblyTargetInfo(T, Opts) { 7838 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7839 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 7840 } 7841 7842 protected: 7843 void getTargetDefines(const LangOptions &Opts, 7844 MacroBuilder &Builder) const override { 7845 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7846 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7847 } 7848 }; 7849 7850 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7851 public: 7852 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 7853 const TargetOptions &Opts) 7854 : WebAssemblyTargetInfo(T, Opts) { 7855 LongAlign = LongWidth = 64; 7856 PointerAlign = PointerWidth = 64; 7857 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7858 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7859 } 7860 7861 protected: 7862 void getTargetDefines(const LangOptions &Opts, 7863 MacroBuilder &Builder) const override { 7864 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7865 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7866 } 7867 }; 7868 7869 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7870 #define BUILTIN(ID, TYPE, ATTRS) \ 7871 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7872 #include "clang/Basic/BuiltinsLe64.def" 7873 }; 7874 7875 static const unsigned SPIRAddrSpaceMap[] = { 7876 1, // opencl_global 7877 3, // opencl_local 7878 2, // opencl_constant 7879 4, // opencl_generic 7880 0, // cuda_device 7881 0, // cuda_constant 7882 0 // cuda_shared 7883 }; 7884 class SPIRTargetInfo : public TargetInfo { 7885 public: 7886 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7887 : TargetInfo(Triple) { 7888 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7889 "SPIR target must use unknown OS"); 7890 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7891 "SPIR target must use unknown environment type"); 7892 BigEndian = false; 7893 TLSSupported = false; 7894 LongWidth = LongAlign = 64; 7895 AddrSpaceMap = &SPIRAddrSpaceMap; 7896 UseAddrSpaceMapMangling = true; 7897 // Define available target features 7898 // These must be defined in sorted order! 7899 NoAsmVariants = true; 7900 } 7901 void getTargetDefines(const LangOptions &Opts, 7902 MacroBuilder &Builder) const override { 7903 DefineStd(Builder, "SPIR", Opts); 7904 } 7905 bool hasFeature(StringRef Feature) const override { 7906 return Feature == "spir"; 7907 } 7908 7909 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7910 const char *getClobbers() const override { return ""; } 7911 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7912 bool validateAsmConstraint(const char *&Name, 7913 TargetInfo::ConstraintInfo &info) const override { 7914 return true; 7915 } 7916 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7917 return None; 7918 } 7919 BuiltinVaListKind getBuiltinVaListKind() const override { 7920 return TargetInfo::VoidPtrBuiltinVaList; 7921 } 7922 7923 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7924 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7925 : CCCR_Warning; 7926 } 7927 7928 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7929 return CC_SpirFunction; 7930 } 7931 7932 void setSupportedOpenCLOpts() override { 7933 // Assume all OpenCL extensions and optional core features are supported 7934 // for SPIR since it is a generic target. 7935 getSupportedOpenCLOpts().setAll(); 7936 } 7937 }; 7938 7939 class SPIR32TargetInfo : public SPIRTargetInfo { 7940 public: 7941 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7942 : SPIRTargetInfo(Triple, Opts) { 7943 PointerWidth = PointerAlign = 32; 7944 SizeType = TargetInfo::UnsignedInt; 7945 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7946 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7947 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7948 } 7949 void getTargetDefines(const LangOptions &Opts, 7950 MacroBuilder &Builder) const override { 7951 DefineStd(Builder, "SPIR32", Opts); 7952 } 7953 }; 7954 7955 class SPIR64TargetInfo : public SPIRTargetInfo { 7956 public: 7957 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7958 : SPIRTargetInfo(Triple, Opts) { 7959 PointerWidth = PointerAlign = 64; 7960 SizeType = TargetInfo::UnsignedLong; 7961 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7962 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7963 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 7964 } 7965 void getTargetDefines(const LangOptions &Opts, 7966 MacroBuilder &Builder) const override { 7967 DefineStd(Builder, "SPIR64", Opts); 7968 } 7969 }; 7970 7971 class XCoreTargetInfo : public TargetInfo { 7972 static const Builtin::Info BuiltinInfo[]; 7973 public: 7974 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7975 : TargetInfo(Triple) { 7976 BigEndian = false; 7977 NoAsmVariants = true; 7978 LongLongAlign = 32; 7979 SuitableAlign = 32; 7980 DoubleAlign = LongDoubleAlign = 32; 7981 SizeType = UnsignedInt; 7982 PtrDiffType = SignedInt; 7983 IntPtrType = SignedInt; 7984 WCharType = UnsignedChar; 7985 WIntType = UnsignedInt; 7986 UseZeroLengthBitfieldAlignment = true; 7987 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7988 "-f64:32-a:0:32-n32"); 7989 } 7990 void getTargetDefines(const LangOptions &Opts, 7991 MacroBuilder &Builder) const override { 7992 Builder.defineMacro("__XS1B__"); 7993 } 7994 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7995 return llvm::makeArrayRef(BuiltinInfo, 7996 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7997 } 7998 BuiltinVaListKind getBuiltinVaListKind() const override { 7999 return TargetInfo::VoidPtrBuiltinVaList; 8000 } 8001 const char *getClobbers() const override { 8002 return ""; 8003 } 8004 ArrayRef<const char *> getGCCRegNames() const override { 8005 static const char * const GCCRegNames[] = { 8006 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8007 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8008 }; 8009 return llvm::makeArrayRef(GCCRegNames); 8010 } 8011 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8012 return None; 8013 } 8014 bool validateAsmConstraint(const char *&Name, 8015 TargetInfo::ConstraintInfo &Info) const override { 8016 return false; 8017 } 8018 int getEHDataRegisterNumber(unsigned RegNo) const override { 8019 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8020 return (RegNo < 2)? RegNo : -1; 8021 } 8022 bool allowsLargerPreferedTypeAlignment() const override { 8023 return false; 8024 } 8025 }; 8026 8027 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8028 #define BUILTIN(ID, TYPE, ATTRS) \ 8029 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8030 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8031 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8032 #include "clang/Basic/BuiltinsXCore.def" 8033 }; 8034 8035 // x86_32 Android target 8036 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8037 public: 8038 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8039 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8040 SuitableAlign = 32; 8041 LongDoubleWidth = 64; 8042 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8043 } 8044 }; 8045 8046 // x86_64 Android target 8047 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8048 public: 8049 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8050 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8051 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8052 } 8053 8054 bool useFloat128ManglingForLongDouble() const override { 8055 return true; 8056 } 8057 }; 8058 } // end anonymous namespace 8059 8060 //===----------------------------------------------------------------------===// 8061 // Driver code 8062 //===----------------------------------------------------------------------===// 8063 8064 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8065 const TargetOptions &Opts) { 8066 llvm::Triple::OSType os = Triple.getOS(); 8067 8068 switch (Triple.getArch()) { 8069 default: 8070 return nullptr; 8071 8072 case llvm::Triple::xcore: 8073 return new XCoreTargetInfo(Triple, Opts); 8074 8075 case llvm::Triple::hexagon: 8076 return new HexagonTargetInfo(Triple, Opts); 8077 8078 case llvm::Triple::lanai: 8079 return new LanaiTargetInfo(Triple, Opts); 8080 8081 case llvm::Triple::aarch64: 8082 if (Triple.isOSDarwin()) 8083 return new DarwinAArch64TargetInfo(Triple, Opts); 8084 8085 switch (os) { 8086 case llvm::Triple::CloudABI: 8087 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8088 case llvm::Triple::FreeBSD: 8089 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8090 case llvm::Triple::Linux: 8091 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8092 case llvm::Triple::NetBSD: 8093 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8094 default: 8095 return new AArch64leTargetInfo(Triple, Opts); 8096 } 8097 8098 case llvm::Triple::aarch64_be: 8099 switch (os) { 8100 case llvm::Triple::FreeBSD: 8101 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8102 case llvm::Triple::Linux: 8103 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8104 case llvm::Triple::NetBSD: 8105 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8106 default: 8107 return new AArch64beTargetInfo(Triple, Opts); 8108 } 8109 8110 case llvm::Triple::arm: 8111 case llvm::Triple::thumb: 8112 if (Triple.isOSBinFormatMachO()) 8113 return new DarwinARMTargetInfo(Triple, Opts); 8114 8115 switch (os) { 8116 case llvm::Triple::Linux: 8117 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8118 case llvm::Triple::FreeBSD: 8119 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8120 case llvm::Triple::NetBSD: 8121 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8122 case llvm::Triple::OpenBSD: 8123 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8124 case llvm::Triple::Bitrig: 8125 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8126 case llvm::Triple::RTEMS: 8127 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8128 case llvm::Triple::NaCl: 8129 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8130 case llvm::Triple::Win32: 8131 switch (Triple.getEnvironment()) { 8132 case llvm::Triple::Cygnus: 8133 return new CygwinARMTargetInfo(Triple, Opts); 8134 case llvm::Triple::GNU: 8135 return new MinGWARMTargetInfo(Triple, Opts); 8136 case llvm::Triple::Itanium: 8137 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8138 case llvm::Triple::MSVC: 8139 default: // Assume MSVC for unknown environments 8140 return new MicrosoftARMleTargetInfo(Triple, Opts); 8141 } 8142 default: 8143 return new ARMleTargetInfo(Triple, Opts); 8144 } 8145 8146 case llvm::Triple::armeb: 8147 case llvm::Triple::thumbeb: 8148 if (Triple.isOSDarwin()) 8149 return new DarwinARMTargetInfo(Triple, Opts); 8150 8151 switch (os) { 8152 case llvm::Triple::Linux: 8153 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8154 case llvm::Triple::FreeBSD: 8155 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8156 case llvm::Triple::NetBSD: 8157 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8158 case llvm::Triple::OpenBSD: 8159 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8160 case llvm::Triple::Bitrig: 8161 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8162 case llvm::Triple::RTEMS: 8163 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8164 case llvm::Triple::NaCl: 8165 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8166 default: 8167 return new ARMbeTargetInfo(Triple, Opts); 8168 } 8169 8170 case llvm::Triple::bpfeb: 8171 case llvm::Triple::bpfel: 8172 return new BPFTargetInfo(Triple, Opts); 8173 8174 case llvm::Triple::msp430: 8175 return new MSP430TargetInfo(Triple, Opts); 8176 8177 case llvm::Triple::mips: 8178 switch (os) { 8179 case llvm::Triple::Linux: 8180 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8181 case llvm::Triple::RTEMS: 8182 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8183 case llvm::Triple::FreeBSD: 8184 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8185 case llvm::Triple::NetBSD: 8186 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple, Opts); 8187 default: 8188 return new Mips32EBTargetInfo(Triple, Opts); 8189 } 8190 8191 case llvm::Triple::mipsel: 8192 switch (os) { 8193 case llvm::Triple::Linux: 8194 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8195 case llvm::Triple::RTEMS: 8196 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8197 case llvm::Triple::FreeBSD: 8198 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8199 case llvm::Triple::NetBSD: 8200 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple, Opts); 8201 case llvm::Triple::NaCl: 8202 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple, Opts); 8203 default: 8204 return new Mips32ELTargetInfo(Triple, Opts); 8205 } 8206 8207 case llvm::Triple::mips64: 8208 switch (os) { 8209 case llvm::Triple::Linux: 8210 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8211 case llvm::Triple::RTEMS: 8212 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8213 case llvm::Triple::FreeBSD: 8214 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8215 case llvm::Triple::NetBSD: 8216 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8217 case llvm::Triple::OpenBSD: 8218 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple, Opts); 8219 default: 8220 return new Mips64EBTargetInfo(Triple, Opts); 8221 } 8222 8223 case llvm::Triple::mips64el: 8224 switch (os) { 8225 case llvm::Triple::Linux: 8226 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8227 case llvm::Triple::RTEMS: 8228 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8229 case llvm::Triple::FreeBSD: 8230 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8231 case llvm::Triple::NetBSD: 8232 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8233 case llvm::Triple::OpenBSD: 8234 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple, Opts); 8235 default: 8236 return new Mips64ELTargetInfo(Triple, Opts); 8237 } 8238 8239 case llvm::Triple::le32: 8240 switch (os) { 8241 case llvm::Triple::NaCl: 8242 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8243 default: 8244 return nullptr; 8245 } 8246 8247 case llvm::Triple::le64: 8248 return new Le64TargetInfo(Triple, Opts); 8249 8250 case llvm::Triple::ppc: 8251 if (Triple.isOSDarwin()) 8252 return new DarwinPPC32TargetInfo(Triple, Opts); 8253 switch (os) { 8254 case llvm::Triple::Linux: 8255 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8256 case llvm::Triple::FreeBSD: 8257 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8258 case llvm::Triple::NetBSD: 8259 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8260 case llvm::Triple::OpenBSD: 8261 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8262 case llvm::Triple::RTEMS: 8263 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8264 default: 8265 return new PPC32TargetInfo(Triple, Opts); 8266 } 8267 8268 case llvm::Triple::ppc64: 8269 if (Triple.isOSDarwin()) 8270 return new DarwinPPC64TargetInfo(Triple, Opts); 8271 switch (os) { 8272 case llvm::Triple::Linux: 8273 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8274 case llvm::Triple::Lv2: 8275 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8276 case llvm::Triple::FreeBSD: 8277 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8278 case llvm::Triple::NetBSD: 8279 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8280 default: 8281 return new PPC64TargetInfo(Triple, Opts); 8282 } 8283 8284 case llvm::Triple::ppc64le: 8285 switch (os) { 8286 case llvm::Triple::Linux: 8287 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8288 case llvm::Triple::NetBSD: 8289 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8290 default: 8291 return new PPC64TargetInfo(Triple, Opts); 8292 } 8293 8294 case llvm::Triple::nvptx: 8295 return new NVPTX32TargetInfo(Triple, Opts); 8296 case llvm::Triple::nvptx64: 8297 return new NVPTX64TargetInfo(Triple, Opts); 8298 8299 case llvm::Triple::amdgcn: 8300 case llvm::Triple::r600: 8301 return new AMDGPUTargetInfo(Triple, Opts); 8302 8303 case llvm::Triple::sparc: 8304 switch (os) { 8305 case llvm::Triple::Linux: 8306 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8307 case llvm::Triple::Solaris: 8308 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8309 case llvm::Triple::NetBSD: 8310 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8311 case llvm::Triple::OpenBSD: 8312 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8313 case llvm::Triple::RTEMS: 8314 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8315 default: 8316 return new SparcV8TargetInfo(Triple, Opts); 8317 } 8318 8319 // The 'sparcel' architecture copies all the above cases except for Solaris. 8320 case llvm::Triple::sparcel: 8321 switch (os) { 8322 case llvm::Triple::Linux: 8323 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8324 case llvm::Triple::NetBSD: 8325 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8326 case llvm::Triple::OpenBSD: 8327 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8328 case llvm::Triple::RTEMS: 8329 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8330 default: 8331 return new SparcV8elTargetInfo(Triple, Opts); 8332 } 8333 8334 case llvm::Triple::sparcv9: 8335 switch (os) { 8336 case llvm::Triple::Linux: 8337 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8338 case llvm::Triple::Solaris: 8339 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8340 case llvm::Triple::NetBSD: 8341 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8342 case llvm::Triple::OpenBSD: 8343 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8344 case llvm::Triple::FreeBSD: 8345 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8346 default: 8347 return new SparcV9TargetInfo(Triple, Opts); 8348 } 8349 8350 case llvm::Triple::systemz: 8351 switch (os) { 8352 case llvm::Triple::Linux: 8353 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8354 default: 8355 return new SystemZTargetInfo(Triple, Opts); 8356 } 8357 8358 case llvm::Triple::tce: 8359 return new TCETargetInfo(Triple, Opts); 8360 8361 case llvm::Triple::x86: 8362 if (Triple.isOSDarwin()) 8363 return new DarwinI386TargetInfo(Triple, Opts); 8364 8365 switch (os) { 8366 case llvm::Triple::CloudABI: 8367 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8368 case llvm::Triple::Linux: { 8369 switch (Triple.getEnvironment()) { 8370 default: 8371 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8372 case llvm::Triple::Android: 8373 return new AndroidX86_32TargetInfo(Triple, Opts); 8374 } 8375 } 8376 case llvm::Triple::DragonFly: 8377 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8378 case llvm::Triple::NetBSD: 8379 return new NetBSDI386TargetInfo(Triple, Opts); 8380 case llvm::Triple::OpenBSD: 8381 return new OpenBSDI386TargetInfo(Triple, Opts); 8382 case llvm::Triple::Bitrig: 8383 return new BitrigI386TargetInfo(Triple, Opts); 8384 case llvm::Triple::FreeBSD: 8385 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8386 case llvm::Triple::KFreeBSD: 8387 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8388 case llvm::Triple::Minix: 8389 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8390 case llvm::Triple::Solaris: 8391 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8392 case llvm::Triple::Win32: { 8393 switch (Triple.getEnvironment()) { 8394 case llvm::Triple::Cygnus: 8395 return new CygwinX86_32TargetInfo(Triple, Opts); 8396 case llvm::Triple::GNU: 8397 return new MinGWX86_32TargetInfo(Triple, Opts); 8398 case llvm::Triple::Itanium: 8399 case llvm::Triple::MSVC: 8400 default: // Assume MSVC for unknown environments 8401 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8402 } 8403 } 8404 case llvm::Triple::Haiku: 8405 return new HaikuX86_32TargetInfo(Triple, Opts); 8406 case llvm::Triple::RTEMS: 8407 return new RTEMSX86_32TargetInfo(Triple, Opts); 8408 case llvm::Triple::NaCl: 8409 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8410 case llvm::Triple::ELFIAMCU: 8411 return new MCUX86_32TargetInfo(Triple, Opts); 8412 default: 8413 return new X86_32TargetInfo(Triple, Opts); 8414 } 8415 8416 case llvm::Triple::x86_64: 8417 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8418 return new DarwinX86_64TargetInfo(Triple, Opts); 8419 8420 switch (os) { 8421 case llvm::Triple::CloudABI: 8422 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8423 case llvm::Triple::Linux: { 8424 switch (Triple.getEnvironment()) { 8425 default: 8426 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8427 case llvm::Triple::Android: 8428 return new AndroidX86_64TargetInfo(Triple, Opts); 8429 } 8430 } 8431 case llvm::Triple::DragonFly: 8432 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8433 case llvm::Triple::NetBSD: 8434 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8435 case llvm::Triple::OpenBSD: 8436 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8437 case llvm::Triple::Bitrig: 8438 return new BitrigX86_64TargetInfo(Triple, Opts); 8439 case llvm::Triple::FreeBSD: 8440 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8441 case llvm::Triple::KFreeBSD: 8442 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8443 case llvm::Triple::Solaris: 8444 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8445 case llvm::Triple::Win32: { 8446 switch (Triple.getEnvironment()) { 8447 case llvm::Triple::Cygnus: 8448 return new CygwinX86_64TargetInfo(Triple, Opts); 8449 case llvm::Triple::GNU: 8450 return new MinGWX86_64TargetInfo(Triple, Opts); 8451 case llvm::Triple::MSVC: 8452 default: // Assume MSVC for unknown environments 8453 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8454 } 8455 } 8456 case llvm::Triple::Haiku: 8457 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8458 case llvm::Triple::NaCl: 8459 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8460 case llvm::Triple::PS4: 8461 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8462 default: 8463 return new X86_64TargetInfo(Triple, Opts); 8464 } 8465 8466 case llvm::Triple::spir: { 8467 if (Triple.getOS() != llvm::Triple::UnknownOS || 8468 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8469 return nullptr; 8470 return new SPIR32TargetInfo(Triple, Opts); 8471 } 8472 case llvm::Triple::spir64: { 8473 if (Triple.getOS() != llvm::Triple::UnknownOS || 8474 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8475 return nullptr; 8476 return new SPIR64TargetInfo(Triple, Opts); 8477 } 8478 case llvm::Triple::wasm32: 8479 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8480 return nullptr; 8481 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8482 case llvm::Triple::wasm64: 8483 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8484 return nullptr; 8485 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8486 } 8487 } 8488 8489 /// CreateTargetInfo - Return the target info object for the specified target 8490 /// options. 8491 TargetInfo * 8492 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8493 const std::shared_ptr<TargetOptions> &Opts) { 8494 llvm::Triple Triple(Opts->Triple); 8495 8496 // Construct the target 8497 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8498 if (!Target) { 8499 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8500 return nullptr; 8501 } 8502 Target->TargetOpts = Opts; 8503 8504 // Set the target CPU if specified. 8505 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8506 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8507 return nullptr; 8508 } 8509 8510 // Set the target ABI if specified. 8511 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8512 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8513 return nullptr; 8514 } 8515 8516 // Set the fp math unit. 8517 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8518 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8519 return nullptr; 8520 } 8521 8522 // Compute the default target features, we need the target to handle this 8523 // because features may have dependencies on one another. 8524 llvm::StringMap<bool> Features; 8525 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8526 Opts->FeaturesAsWritten)) 8527 return nullptr; 8528 8529 // Add the features to the compile options. 8530 Opts->Features.clear(); 8531 for (const auto &F : Features) 8532 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8533 8534 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8535 return nullptr; 8536 8537 Target->setSupportedOpenCLOpts(); 8538 8539 return Target.release(); 8540 } 8541