1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 virtual std::string isValidSectionSpecifier(StringRef SR) const { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 virtual const char *getStaticInitSectionSpecifier() const { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 virtual bool hasProtectedVisibility() const { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 virtual const char *getStaticInitSectionSpecifier() const { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 486 } 487 }; 488 489 // AuroraUX target 490 template<typename Target> 491 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const { 495 DefineStd(Builder, "sun", Opts); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 Builder.defineMacro("__svr4__"); 499 Builder.defineMacro("__SVR4"); 500 } 501 public: 502 AuroraUXTargetInfo(const llvm::Triple &Triple) 503 : OSTargetInfo<Target>(Triple) { 504 this->UserLabelPrefix = ""; 505 this->WCharType = this->SignedLong; 506 // FIXME: WIntType should be SignedLong 507 } 508 }; 509 510 // Solaris target 511 template<typename Target> 512 class SolarisTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 522 // newer, but to 500 for everything else. feature_test.h has a check to 523 // ensure that you are not using C99 with an old version of X/Open or C89 524 // with a new version. 525 if (Opts.C99 || Opts.C11) 526 Builder.defineMacro("_XOPEN_SOURCE", "600"); 527 else 528 Builder.defineMacro("_XOPEN_SOURCE", "500"); 529 if (Opts.CPlusPlus) 530 Builder.defineMacro("__C99FEATURES__"); 531 Builder.defineMacro("_LARGEFILE_SOURCE"); 532 Builder.defineMacro("_LARGEFILE64_SOURCE"); 533 Builder.defineMacro("__EXTENSIONS__"); 534 Builder.defineMacro("_REENTRANT"); 535 } 536 public: 537 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 538 this->UserLabelPrefix = ""; 539 this->WCharType = this->SignedInt; 540 // FIXME: WIntType should be SignedLong 541 } 542 }; 543 544 // Windows target 545 template<typename Target> 546 class WindowsTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const { 550 Builder.defineMacro("_WIN32"); 551 } 552 void getVisualStudioDefines(const LangOptions &Opts, 553 MacroBuilder &Builder) const { 554 if (Opts.CPlusPlus) { 555 if (Opts.RTTI) 556 Builder.defineMacro("_CPPRTTI"); 557 558 if (Opts.Exceptions) 559 Builder.defineMacro("_CPPUNWIND"); 560 } 561 562 if (!Opts.CharIsSigned) 563 Builder.defineMacro("_CHAR_UNSIGNED"); 564 565 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 566 // but it works for now. 567 if (Opts.POSIXThreads) 568 Builder.defineMacro("_MT"); 569 570 if (Opts.MSCVersion != 0) 571 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 572 573 if (Opts.MicrosoftExt) { 574 Builder.defineMacro("_MSC_EXTENSIONS"); 575 576 if (Opts.CPlusPlus11) { 577 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 578 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 579 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 580 } 581 } 582 583 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 584 } 585 586 public: 587 WindowsTargetInfo(const llvm::Triple &Triple) 588 : OSTargetInfo<Target>(Triple) {} 589 }; 590 591 template <typename Target> 592 class NaClTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const { 596 if (Opts.POSIXThreads) 597 Builder.defineMacro("_REENTRANT"); 598 if (Opts.CPlusPlus) 599 Builder.defineMacro("_GNU_SOURCE"); 600 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__native_client__"); 604 } 605 606 public: 607 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 608 this->UserLabelPrefix = ""; 609 this->LongAlign = 32; 610 this->LongWidth = 32; 611 this->PointerAlign = 32; 612 this->PointerWidth = 32; 613 this->IntMaxType = TargetInfo::SignedLongLong; 614 this->UIntMaxType = TargetInfo::UnsignedLongLong; 615 this->Int64Type = TargetInfo::SignedLongLong; 616 this->DoubleAlign = 64; 617 this->LongDoubleWidth = 64; 618 this->LongDoubleAlign = 64; 619 this->LongLongWidth = 64; 620 this->LongLongAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 if (Triple.getArch() == llvm::Triple::arm) { 627 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 628 } else if (Triple.getArch() == llvm::Triple::x86) { 629 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 630 } else if (Triple.getArch() == llvm::Triple::x86_64) { 631 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 632 } else if (Triple.getArch() == llvm::Triple::mipsel) { 633 // Handled on mips' setDescriptionString. 634 } else { 635 assert(Triple.getArch() == llvm::Triple::le32); 636 this->DescriptionString = "e-p:32:32-i64:64"; 637 } 638 } 639 virtual typename Target::CallingConvCheckResult checkCallingConvention( 640 CallingConv CC) const { 641 return CC == CC_PnaclCall ? Target::CCCR_OK : 642 Target::checkCallingConvention(CC); 643 } 644 }; 645 } // end anonymous namespace. 646 647 //===----------------------------------------------------------------------===// 648 // Specific target implementations. 649 //===----------------------------------------------------------------------===// 650 651 namespace { 652 // PPC abstract base class 653 class PPCTargetInfo : public TargetInfo { 654 static const Builtin::Info BuiltinInfo[]; 655 static const char * const GCCRegNames[]; 656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 657 std::string CPU; 658 659 // Target cpu features. 660 bool HasVSX; 661 662 public: 663 PPCTargetInfo(const llvm::Triple &Triple) 664 : TargetInfo(Triple), HasVSX(false) { 665 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 666 LongDoubleWidth = LongDoubleAlign = 128; 667 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 668 } 669 670 /// \brief Flags for architecture specific defines. 671 typedef enum { 672 ArchDefineNone = 0, 673 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 674 ArchDefinePpcgr = 1 << 1, 675 ArchDefinePpcsq = 1 << 2, 676 ArchDefine440 = 1 << 3, 677 ArchDefine603 = 1 << 4, 678 ArchDefine604 = 1 << 5, 679 ArchDefinePwr4 = 1 << 6, 680 ArchDefinePwr5 = 1 << 7, 681 ArchDefinePwr5x = 1 << 8, 682 ArchDefinePwr6 = 1 << 9, 683 ArchDefinePwr6x = 1 << 10, 684 ArchDefinePwr7 = 1 << 11, 685 ArchDefineA2 = 1 << 12, 686 ArchDefineA2q = 1 << 13 687 } ArchDefineTypes; 688 689 // Note: GCC recognizes the following additional cpus: 690 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 691 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 692 // titan, rs64. 693 virtual bool setCPU(const std::string &Name) { 694 bool CPUKnown = llvm::StringSwitch<bool>(Name) 695 .Case("generic", true) 696 .Case("440", true) 697 .Case("450", true) 698 .Case("601", true) 699 .Case("602", true) 700 .Case("603", true) 701 .Case("603e", true) 702 .Case("603ev", true) 703 .Case("604", true) 704 .Case("604e", true) 705 .Case("620", true) 706 .Case("630", true) 707 .Case("g3", true) 708 .Case("7400", true) 709 .Case("g4", true) 710 .Case("7450", true) 711 .Case("g4+", true) 712 .Case("750", true) 713 .Case("970", true) 714 .Case("g5", true) 715 .Case("a2", true) 716 .Case("a2q", true) 717 .Case("e500mc", true) 718 .Case("e5500", true) 719 .Case("power3", true) 720 .Case("pwr3", true) 721 .Case("power4", true) 722 .Case("pwr4", true) 723 .Case("power5", true) 724 .Case("pwr5", true) 725 .Case("power5x", true) 726 .Case("pwr5x", true) 727 .Case("power6", true) 728 .Case("pwr6", true) 729 .Case("power6x", true) 730 .Case("pwr6x", true) 731 .Case("power7", true) 732 .Case("pwr7", true) 733 .Case("powerpc", true) 734 .Case("ppc", true) 735 .Case("powerpc64", true) 736 .Case("ppc64", true) 737 .Case("powerpc64le", true) 738 .Case("ppc64le", true) 739 .Default(false); 740 741 if (CPUKnown) 742 CPU = Name; 743 744 return CPUKnown; 745 } 746 747 virtual void getTargetBuiltins(const Builtin::Info *&Records, 748 unsigned &NumRecords) const { 749 Records = BuiltinInfo; 750 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 751 } 752 753 virtual bool isCLZForZeroUndef() const { return false; } 754 755 virtual void getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const; 757 758 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 759 760 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 761 DiagnosticsEngine &Diags); 762 virtual bool hasFeature(StringRef Feature) const; 763 764 virtual void getGCCRegNames(const char * const *&Names, 765 unsigned &NumNames) const; 766 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 767 unsigned &NumAliases) const; 768 virtual bool validateAsmConstraint(const char *&Name, 769 TargetInfo::ConstraintInfo &Info) const { 770 switch (*Name) { 771 default: return false; 772 case 'O': // Zero 773 break; 774 case 'b': // Base register 775 case 'f': // Floating point register 776 Info.setAllowsRegister(); 777 break; 778 // FIXME: The following are added to allow parsing. 779 // I just took a guess at what the actions should be. 780 // Also, is more specific checking needed? I.e. specific registers? 781 case 'd': // Floating point register (containing 64-bit value) 782 case 'v': // Altivec vector register 783 Info.setAllowsRegister(); 784 break; 785 case 'w': 786 switch (Name[1]) { 787 case 'd':// VSX vector register to hold vector double data 788 case 'f':// VSX vector register to hold vector float data 789 case 's':// VSX vector register to hold scalar float data 790 case 'a':// Any VSX register 791 case 'c':// An individual CR bit 792 break; 793 default: 794 return false; 795 } 796 Info.setAllowsRegister(); 797 Name++; // Skip over 'w'. 798 break; 799 case 'h': // `MQ', `CTR', or `LINK' register 800 case 'q': // `MQ' register 801 case 'c': // `CTR' register 802 case 'l': // `LINK' register 803 case 'x': // `CR' register (condition register) number 0 804 case 'y': // `CR' register (condition register) 805 case 'z': // `XER[CA]' carry bit (part of the XER register) 806 Info.setAllowsRegister(); 807 break; 808 case 'I': // Signed 16-bit constant 809 case 'J': // Unsigned 16-bit constant shifted left 16 bits 810 // (use `L' instead for SImode constants) 811 case 'K': // Unsigned 16-bit constant 812 case 'L': // Signed 16-bit constant shifted left 16 bits 813 case 'M': // Constant larger than 31 814 case 'N': // Exact power of 2 815 case 'P': // Constant whose negation is a signed 16-bit constant 816 case 'G': // Floating point constant that can be loaded into a 817 // register with one instruction per word 818 case 'H': // Integer/Floating point constant that can be loaded 819 // into a register using three instructions 820 break; 821 case 'm': // Memory operand. Note that on PowerPC targets, m can 822 // include addresses that update the base register. It 823 // is therefore only safe to use `m' in an asm statement 824 // if that asm statement accesses the operand exactly once. 825 // The asm statement must also use `%U<opno>' as a 826 // placeholder for the "update" flag in the corresponding 827 // load or store instruction. For example: 828 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 829 // is correct but: 830 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 831 // is not. Use es rather than m if you don't want the base 832 // register to be updated. 833 case 'e': 834 if (Name[1] != 's') 835 return false; 836 // es: A "stable" memory operand; that is, one which does not 837 // include any automodification of the base register. Unlike 838 // `m', this constraint can be used in asm statements that 839 // might access the operand several times, or that might not 840 // access it at all. 841 Info.setAllowsMemory(); 842 Name++; // Skip over 'e'. 843 break; 844 case 'Q': // Memory operand that is an offset from a register (it is 845 // usually better to use `m' or `es' in asm statements) 846 case 'Z': // Memory operand that is an indexed or indirect from a 847 // register (it is usually better to use `m' or `es' in 848 // asm statements) 849 Info.setAllowsMemory(); 850 Info.setAllowsRegister(); 851 break; 852 case 'R': // AIX TOC entry 853 case 'a': // Address operand that is an indexed or indirect from a 854 // register (`p' is preferable for asm statements) 855 case 'S': // Constant suitable as a 64-bit mask operand 856 case 'T': // Constant suitable as a 32-bit mask operand 857 case 'U': // System V Release 4 small data area reference 858 case 't': // AND masks that can be performed by two rldic{l, r} 859 // instructions 860 case 'W': // Vector constant that does not require memory 861 case 'j': // Vector constant that is all zeros. 862 break; 863 // End FIXME. 864 } 865 return true; 866 } 867 virtual std::string convertConstraint(const char *&Constraint) const { 868 std::string R; 869 switch (*Constraint) { 870 case 'e': 871 case 'w': 872 // Two-character constraint; add "^" hint for later parsing. 873 R = std::string("^") + std::string(Constraint, 2); 874 Constraint++; 875 break; 876 default: 877 return TargetInfo::convertConstraint(Constraint); 878 } 879 return R; 880 } 881 virtual const char *getClobbers() const { 882 return ""; 883 } 884 int getEHDataRegisterNumber(unsigned RegNo) const { 885 if (RegNo == 0) return 3; 886 if (RegNo == 1) return 4; 887 return -1; 888 } 889 }; 890 891 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 892 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 894 ALL_LANGUAGES }, 895 #include "clang/Basic/BuiltinsPPC.def" 896 }; 897 898 /// handleTargetFeatures - Perform initialization based on the user 899 /// configured set of features. 900 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 901 DiagnosticsEngine &Diags) { 902 // Remember the maximum enabled sselevel. 903 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 904 // Ignore disabled features. 905 if (Features[i][0] == '-') 906 continue; 907 908 StringRef Feature = StringRef(Features[i]).substr(1); 909 910 if (Feature == "vsx") { 911 HasVSX = true; 912 continue; 913 } 914 915 // TODO: Finish this list and add an assert that we've handled them 916 // all. 917 } 918 919 return true; 920 } 921 922 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 923 /// #defines that are not tied to a specific subtarget. 924 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 925 MacroBuilder &Builder) const { 926 // Target identification. 927 Builder.defineMacro("__ppc__"); 928 Builder.defineMacro("__PPC__"); 929 Builder.defineMacro("_ARCH_PPC"); 930 Builder.defineMacro("__powerpc__"); 931 Builder.defineMacro("__POWERPC__"); 932 if (PointerWidth == 64) { 933 Builder.defineMacro("_ARCH_PPC64"); 934 Builder.defineMacro("__powerpc64__"); 935 Builder.defineMacro("__ppc64__"); 936 Builder.defineMacro("__PPC64__"); 937 } 938 939 // Target properties. 940 if (getTriple().getArch() == llvm::Triple::ppc64le) { 941 Builder.defineMacro("_LITTLE_ENDIAN"); 942 Builder.defineMacro("__LITTLE_ENDIAN__"); 943 } else { 944 if (getTriple().getOS() != llvm::Triple::NetBSD && 945 getTriple().getOS() != llvm::Triple::OpenBSD) 946 Builder.defineMacro("_BIG_ENDIAN"); 947 Builder.defineMacro("__BIG_ENDIAN__"); 948 } 949 950 // Subtarget options. 951 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 952 Builder.defineMacro("__REGISTER_PREFIX__", ""); 953 954 // FIXME: Should be controlled by command line option. 955 if (LongDoubleWidth == 128) 956 Builder.defineMacro("__LONG_DOUBLE_128__"); 957 958 if (Opts.AltiVec) { 959 Builder.defineMacro("__VEC__", "10206"); 960 Builder.defineMacro("__ALTIVEC__"); 961 } 962 963 // CPU identification. 964 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 965 .Case("440", ArchDefineName) 966 .Case("450", ArchDefineName | ArchDefine440) 967 .Case("601", ArchDefineName) 968 .Case("602", ArchDefineName | ArchDefinePpcgr) 969 .Case("603", ArchDefineName | ArchDefinePpcgr) 970 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 971 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 972 .Case("604", ArchDefineName | ArchDefinePpcgr) 973 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 974 .Case("620", ArchDefineName | ArchDefinePpcgr) 975 .Case("630", ArchDefineName | ArchDefinePpcgr) 976 .Case("7400", ArchDefineName | ArchDefinePpcgr) 977 .Case("7450", ArchDefineName | ArchDefinePpcgr) 978 .Case("750", ArchDefineName | ArchDefinePpcgr) 979 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 980 | ArchDefinePpcsq) 981 .Case("a2", ArchDefineA2) 982 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 983 .Case("pwr3", ArchDefinePpcgr) 984 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 985 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 986 | ArchDefinePpcsq) 987 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 988 | ArchDefinePpcgr | ArchDefinePpcsq) 989 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 990 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 991 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 992 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 993 | ArchDefinePpcsq) 994 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 995 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 996 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 997 .Case("power3", ArchDefinePpcgr) 998 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 999 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1000 | ArchDefinePpcsq) 1001 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1002 | ArchDefinePpcgr | ArchDefinePpcsq) 1003 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1004 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1005 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1006 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1007 | ArchDefinePpcsq) 1008 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1009 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1010 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1011 .Default(ArchDefineNone); 1012 1013 if (defs & ArchDefineName) 1014 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1015 if (defs & ArchDefinePpcgr) 1016 Builder.defineMacro("_ARCH_PPCGR"); 1017 if (defs & ArchDefinePpcsq) 1018 Builder.defineMacro("_ARCH_PPCSQ"); 1019 if (defs & ArchDefine440) 1020 Builder.defineMacro("_ARCH_440"); 1021 if (defs & ArchDefine603) 1022 Builder.defineMacro("_ARCH_603"); 1023 if (defs & ArchDefine604) 1024 Builder.defineMacro("_ARCH_604"); 1025 if (defs & ArchDefinePwr4) 1026 Builder.defineMacro("_ARCH_PWR4"); 1027 if (defs & ArchDefinePwr5) 1028 Builder.defineMacro("_ARCH_PWR5"); 1029 if (defs & ArchDefinePwr5x) 1030 Builder.defineMacro("_ARCH_PWR5X"); 1031 if (defs & ArchDefinePwr6) 1032 Builder.defineMacro("_ARCH_PWR6"); 1033 if (defs & ArchDefinePwr6x) 1034 Builder.defineMacro("_ARCH_PWR6X"); 1035 if (defs & ArchDefinePwr7) 1036 Builder.defineMacro("_ARCH_PWR7"); 1037 if (defs & ArchDefineA2) 1038 Builder.defineMacro("_ARCH_A2"); 1039 if (defs & ArchDefineA2q) { 1040 Builder.defineMacro("_ARCH_A2Q"); 1041 Builder.defineMacro("_ARCH_QP"); 1042 } 1043 1044 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1045 Builder.defineMacro("__bg__"); 1046 Builder.defineMacro("__THW_BLUEGENE__"); 1047 Builder.defineMacro("__bgq__"); 1048 Builder.defineMacro("__TOS_BGQ__"); 1049 } 1050 1051 if (HasVSX) 1052 Builder.defineMacro("__VSX__"); 1053 1054 // FIXME: The following are not yet generated here by Clang, but are 1055 // generated by GCC: 1056 // 1057 // _SOFT_FLOAT_ 1058 // __RECIP_PRECISION__ 1059 // __APPLE_ALTIVEC__ 1060 // __RECIP__ 1061 // __RECIPF__ 1062 // __RSQRTE__ 1063 // __RSQRTEF__ 1064 // _SOFT_DOUBLE_ 1065 // __NO_LWSYNC__ 1066 // __HAVE_BSWAP__ 1067 // __LONGDOUBLE128 1068 // __CMODEL_MEDIUM__ 1069 // __CMODEL_LARGE__ 1070 // _CALL_SYSV 1071 // _CALL_DARWIN 1072 // __NO_FPRS__ 1073 } 1074 1075 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1076 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1077 .Case("7400", true) 1078 .Case("g4", true) 1079 .Case("7450", true) 1080 .Case("g4+", true) 1081 .Case("970", true) 1082 .Case("g5", true) 1083 .Case("pwr6", true) 1084 .Case("pwr7", true) 1085 .Case("ppc64", true) 1086 .Case("ppc64le", true) 1087 .Default(false); 1088 1089 Features["qpx"] = (CPU == "a2q"); 1090 } 1091 1092 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1093 return Feature == "powerpc"; 1094 } 1095 1096 1097 const char * const PPCTargetInfo::GCCRegNames[] = { 1098 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1099 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1100 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1101 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1102 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1103 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1104 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1105 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1106 "mq", "lr", "ctr", "ap", 1107 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1108 "xer", 1109 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1110 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1111 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1112 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1113 "vrsave", "vscr", 1114 "spe_acc", "spefscr", 1115 "sfp" 1116 }; 1117 1118 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1119 unsigned &NumNames) const { 1120 Names = GCCRegNames; 1121 NumNames = llvm::array_lengthof(GCCRegNames); 1122 } 1123 1124 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1125 // While some of these aliases do map to different registers 1126 // they still share the same register name. 1127 { { "0" }, "r0" }, 1128 { { "1"}, "r1" }, 1129 { { "2" }, "r2" }, 1130 { { "3" }, "r3" }, 1131 { { "4" }, "r4" }, 1132 { { "5" }, "r5" }, 1133 { { "6" }, "r6" }, 1134 { { "7" }, "r7" }, 1135 { { "8" }, "r8" }, 1136 { { "9" }, "r9" }, 1137 { { "10" }, "r10" }, 1138 { { "11" }, "r11" }, 1139 { { "12" }, "r12" }, 1140 { { "13" }, "r13" }, 1141 { { "14" }, "r14" }, 1142 { { "15" }, "r15" }, 1143 { { "16" }, "r16" }, 1144 { { "17" }, "r17" }, 1145 { { "18" }, "r18" }, 1146 { { "19" }, "r19" }, 1147 { { "20" }, "r20" }, 1148 { { "21" }, "r21" }, 1149 { { "22" }, "r22" }, 1150 { { "23" }, "r23" }, 1151 { { "24" }, "r24" }, 1152 { { "25" }, "r25" }, 1153 { { "26" }, "r26" }, 1154 { { "27" }, "r27" }, 1155 { { "28" }, "r28" }, 1156 { { "29" }, "r29" }, 1157 { { "30" }, "r30" }, 1158 { { "31" }, "r31" }, 1159 { { "fr0" }, "f0" }, 1160 { { "fr1" }, "f1" }, 1161 { { "fr2" }, "f2" }, 1162 { { "fr3" }, "f3" }, 1163 { { "fr4" }, "f4" }, 1164 { { "fr5" }, "f5" }, 1165 { { "fr6" }, "f6" }, 1166 { { "fr7" }, "f7" }, 1167 { { "fr8" }, "f8" }, 1168 { { "fr9" }, "f9" }, 1169 { { "fr10" }, "f10" }, 1170 { { "fr11" }, "f11" }, 1171 { { "fr12" }, "f12" }, 1172 { { "fr13" }, "f13" }, 1173 { { "fr14" }, "f14" }, 1174 { { "fr15" }, "f15" }, 1175 { { "fr16" }, "f16" }, 1176 { { "fr17" }, "f17" }, 1177 { { "fr18" }, "f18" }, 1178 { { "fr19" }, "f19" }, 1179 { { "fr20" }, "f20" }, 1180 { { "fr21" }, "f21" }, 1181 { { "fr22" }, "f22" }, 1182 { { "fr23" }, "f23" }, 1183 { { "fr24" }, "f24" }, 1184 { { "fr25" }, "f25" }, 1185 { { "fr26" }, "f26" }, 1186 { { "fr27" }, "f27" }, 1187 { { "fr28" }, "f28" }, 1188 { { "fr29" }, "f29" }, 1189 { { "fr30" }, "f30" }, 1190 { { "fr31" }, "f31" }, 1191 { { "cc" }, "cr0" }, 1192 }; 1193 1194 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1195 unsigned &NumAliases) const { 1196 Aliases = GCCRegAliases; 1197 NumAliases = llvm::array_lengthof(GCCRegAliases); 1198 } 1199 } // end anonymous namespace. 1200 1201 namespace { 1202 class PPC32TargetInfo : public PPCTargetInfo { 1203 public: 1204 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1205 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1206 1207 switch (getTriple().getOS()) { 1208 case llvm::Triple::Linux: 1209 case llvm::Triple::FreeBSD: 1210 case llvm::Triple::NetBSD: 1211 SizeType = UnsignedInt; 1212 PtrDiffType = SignedInt; 1213 IntPtrType = SignedInt; 1214 break; 1215 default: 1216 break; 1217 } 1218 1219 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1220 LongDoubleWidth = LongDoubleAlign = 64; 1221 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1222 } 1223 1224 // PPC32 supports atomics up to 4 bytes. 1225 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1226 } 1227 1228 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1229 // This is the ELF definition, and is overridden by the Darwin sub-target 1230 return TargetInfo::PowerABIBuiltinVaList; 1231 } 1232 }; 1233 } // end anonymous namespace. 1234 1235 // Note: ABI differences may eventually require us to have a separate 1236 // TargetInfo for little endian. 1237 namespace { 1238 class PPC64TargetInfo : public PPCTargetInfo { 1239 public: 1240 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1241 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1242 IntMaxType = SignedLong; 1243 UIntMaxType = UnsignedLong; 1244 Int64Type = SignedLong; 1245 1246 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1247 LongDoubleWidth = LongDoubleAlign = 64; 1248 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1249 DescriptionString = "E-m:e-i64:64-n32:64"; 1250 } else 1251 DescriptionString = "E-m:e-i64:64-n32:64"; 1252 1253 // PPC64 supports atomics up to 8 bytes. 1254 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1255 } 1256 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1257 return TargetInfo::CharPtrBuiltinVaList; 1258 } 1259 }; 1260 } // end anonymous namespace. 1261 1262 1263 namespace { 1264 class DarwinPPC32TargetInfo : 1265 public DarwinTargetInfo<PPC32TargetInfo> { 1266 public: 1267 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1268 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1269 HasAlignMac68kSupport = true; 1270 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1271 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1272 LongLongAlign = 32; 1273 SuitableAlign = 128; 1274 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1275 } 1276 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1277 return TargetInfo::CharPtrBuiltinVaList; 1278 } 1279 }; 1280 1281 class DarwinPPC64TargetInfo : 1282 public DarwinTargetInfo<PPC64TargetInfo> { 1283 public: 1284 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1285 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1286 HasAlignMac68kSupport = true; 1287 SuitableAlign = 128; 1288 DescriptionString = "E-m:o-i64:64-n32:64"; 1289 } 1290 }; 1291 } // end anonymous namespace. 1292 1293 namespace { 1294 static const unsigned NVPTXAddrSpaceMap[] = { 1295 1, // opencl_global 1296 3, // opencl_local 1297 4, // opencl_constant 1298 1, // cuda_device 1299 4, // cuda_constant 1300 3, // cuda_shared 1301 }; 1302 class NVPTXTargetInfo : public TargetInfo { 1303 static const char * const GCCRegNames[]; 1304 static const Builtin::Info BuiltinInfo[]; 1305 public: 1306 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1307 BigEndian = false; 1308 TLSSupported = false; 1309 LongWidth = LongAlign = 64; 1310 AddrSpaceMap = &NVPTXAddrSpaceMap; 1311 UseAddrSpaceMapMangling = true; 1312 // Define available target features 1313 // These must be defined in sorted order! 1314 NoAsmVariants = true; 1315 } 1316 virtual void getTargetDefines(const LangOptions &Opts, 1317 MacroBuilder &Builder) const { 1318 Builder.defineMacro("__PTX__"); 1319 Builder.defineMacro("__NVPTX__"); 1320 } 1321 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1322 unsigned &NumRecords) const { 1323 Records = BuiltinInfo; 1324 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1325 } 1326 virtual bool hasFeature(StringRef Feature) const { 1327 return Feature == "ptx" || Feature == "nvptx"; 1328 } 1329 1330 virtual void getGCCRegNames(const char * const *&Names, 1331 unsigned &NumNames) const; 1332 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1333 unsigned &NumAliases) const { 1334 // No aliases. 1335 Aliases = 0; 1336 NumAliases = 0; 1337 } 1338 virtual bool validateAsmConstraint(const char *&Name, 1339 TargetInfo::ConstraintInfo &Info) const { 1340 switch (*Name) { 1341 default: return false; 1342 case 'c': 1343 case 'h': 1344 case 'r': 1345 case 'l': 1346 case 'f': 1347 case 'd': 1348 Info.setAllowsRegister(); 1349 return true; 1350 } 1351 } 1352 virtual const char *getClobbers() const { 1353 // FIXME: Is this really right? 1354 return ""; 1355 } 1356 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1357 // FIXME: implement 1358 return TargetInfo::CharPtrBuiltinVaList; 1359 } 1360 virtual bool setCPU(const std::string &Name) { 1361 bool Valid = llvm::StringSwitch<bool>(Name) 1362 .Case("sm_20", true) 1363 .Case("sm_21", true) 1364 .Case("sm_30", true) 1365 .Case("sm_35", true) 1366 .Default(false); 1367 1368 return Valid; 1369 } 1370 }; 1371 1372 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1373 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1374 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1375 ALL_LANGUAGES }, 1376 #include "clang/Basic/BuiltinsNVPTX.def" 1377 }; 1378 1379 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1380 "r0" 1381 }; 1382 1383 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1384 unsigned &NumNames) const { 1385 Names = GCCRegNames; 1386 NumNames = llvm::array_lengthof(GCCRegNames); 1387 } 1388 1389 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1390 public: 1391 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1392 PointerWidth = PointerAlign = 32; 1393 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1394 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1395 } 1396 }; 1397 1398 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1399 public: 1400 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1401 PointerWidth = PointerAlign = 64; 1402 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1403 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1404 } 1405 }; 1406 } 1407 1408 namespace { 1409 1410 static const unsigned R600AddrSpaceMap[] = { 1411 1, // opencl_global 1412 3, // opencl_local 1413 2, // opencl_constant 1414 1, // cuda_device 1415 2, // cuda_constant 1416 3 // cuda_shared 1417 }; 1418 1419 static const char *DescriptionStringR600 = 1420 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1421 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1422 1423 static const char *DescriptionStringR600DoubleOps = 1424 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1425 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1426 1427 static const char *DescriptionStringSI = 1428 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1429 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1430 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1431 1432 class R600TargetInfo : public TargetInfo { 1433 /// \brief The GPU profiles supported by the R600 target. 1434 enum GPUKind { 1435 GK_NONE, 1436 GK_R600, 1437 GK_R600_DOUBLE_OPS, 1438 GK_R700, 1439 GK_R700_DOUBLE_OPS, 1440 GK_EVERGREEN, 1441 GK_EVERGREEN_DOUBLE_OPS, 1442 GK_NORTHERN_ISLANDS, 1443 GK_CAYMAN, 1444 GK_SOUTHERN_ISLANDS, 1445 GK_SEA_ISLANDS 1446 } GPU; 1447 1448 public: 1449 R600TargetInfo(const llvm::Triple &Triple) 1450 : TargetInfo(Triple), GPU(GK_R600) { 1451 DescriptionString = DescriptionStringR600; 1452 AddrSpaceMap = &R600AddrSpaceMap; 1453 UseAddrSpaceMapMangling = true; 1454 } 1455 1456 virtual const char * getClobbers() const { 1457 return ""; 1458 } 1459 1460 virtual void getGCCRegNames(const char * const *&Names, 1461 unsigned &numNames) const { 1462 Names = NULL; 1463 numNames = 0; 1464 } 1465 1466 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1467 unsigned &NumAliases) const { 1468 Aliases = NULL; 1469 NumAliases = 0; 1470 } 1471 1472 virtual bool validateAsmConstraint(const char *&Name, 1473 TargetInfo::ConstraintInfo &info) const { 1474 return true; 1475 } 1476 1477 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1478 unsigned &NumRecords) const { 1479 Records = NULL; 1480 NumRecords = 0; 1481 } 1482 1483 1484 virtual void getTargetDefines(const LangOptions &Opts, 1485 MacroBuilder &Builder) const { 1486 Builder.defineMacro("__R600__"); 1487 } 1488 1489 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1490 return TargetInfo::CharPtrBuiltinVaList; 1491 } 1492 1493 virtual bool setCPU(const std::string &Name) { 1494 GPU = llvm::StringSwitch<GPUKind>(Name) 1495 .Case("r600" , GK_R600) 1496 .Case("rv610", GK_R600) 1497 .Case("rv620", GK_R600) 1498 .Case("rv630", GK_R600) 1499 .Case("rv635", GK_R600) 1500 .Case("rs780", GK_R600) 1501 .Case("rs880", GK_R600) 1502 .Case("rv670", GK_R600_DOUBLE_OPS) 1503 .Case("rv710", GK_R700) 1504 .Case("rv730", GK_R700) 1505 .Case("rv740", GK_R700_DOUBLE_OPS) 1506 .Case("rv770", GK_R700_DOUBLE_OPS) 1507 .Case("palm", GK_EVERGREEN) 1508 .Case("cedar", GK_EVERGREEN) 1509 .Case("sumo", GK_EVERGREEN) 1510 .Case("sumo2", GK_EVERGREEN) 1511 .Case("redwood", GK_EVERGREEN) 1512 .Case("juniper", GK_EVERGREEN) 1513 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1514 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1515 .Case("barts", GK_NORTHERN_ISLANDS) 1516 .Case("turks", GK_NORTHERN_ISLANDS) 1517 .Case("caicos", GK_NORTHERN_ISLANDS) 1518 .Case("cayman", GK_CAYMAN) 1519 .Case("aruba", GK_CAYMAN) 1520 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1521 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1522 .Case("verde", GK_SOUTHERN_ISLANDS) 1523 .Case("oland", GK_SOUTHERN_ISLANDS) 1524 .Case("bonaire", GK_SEA_ISLANDS) 1525 .Case("kabini", GK_SEA_ISLANDS) 1526 .Case("kaveri", GK_SEA_ISLANDS) 1527 .Case("hawaii", GK_SEA_ISLANDS) 1528 .Default(GK_NONE); 1529 1530 if (GPU == GK_NONE) { 1531 return false; 1532 } 1533 1534 // Set the correct data layout 1535 switch (GPU) { 1536 case GK_NONE: 1537 case GK_R600: 1538 case GK_R700: 1539 case GK_EVERGREEN: 1540 case GK_NORTHERN_ISLANDS: 1541 DescriptionString = DescriptionStringR600; 1542 break; 1543 case GK_R600_DOUBLE_OPS: 1544 case GK_R700_DOUBLE_OPS: 1545 case GK_EVERGREEN_DOUBLE_OPS: 1546 case GK_CAYMAN: 1547 DescriptionString = DescriptionStringR600DoubleOps; 1548 break; 1549 case GK_SOUTHERN_ISLANDS: 1550 case GK_SEA_ISLANDS: 1551 DescriptionString = DescriptionStringSI; 1552 break; 1553 } 1554 1555 return true; 1556 } 1557 }; 1558 1559 } // end anonymous namespace 1560 1561 namespace { 1562 // Namespace for x86 abstract base class 1563 const Builtin::Info BuiltinInfo[] = { 1564 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1565 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1566 ALL_LANGUAGES }, 1567 #include "clang/Basic/BuiltinsX86.def" 1568 }; 1569 1570 static const char* const GCCRegNames[] = { 1571 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1572 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1573 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1574 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1575 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1576 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1577 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1578 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1579 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1580 }; 1581 1582 const TargetInfo::AddlRegName AddlRegNames[] = { 1583 { { "al", "ah", "eax", "rax" }, 0 }, 1584 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1585 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1586 { { "dl", "dh", "edx", "rdx" }, 1 }, 1587 { { "esi", "rsi" }, 4 }, 1588 { { "edi", "rdi" }, 5 }, 1589 { { "esp", "rsp" }, 7 }, 1590 { { "ebp", "rbp" }, 6 }, 1591 }; 1592 1593 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1594 // most of the implementation can be shared. 1595 class X86TargetInfo : public TargetInfo { 1596 enum X86SSEEnum { 1597 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1598 } SSELevel; 1599 enum MMX3DNowEnum { 1600 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1601 } MMX3DNowLevel; 1602 enum XOPEnum { 1603 NoXOP, 1604 SSE4A, 1605 FMA4, 1606 XOP 1607 } XOPLevel; 1608 1609 bool HasAES; 1610 bool HasPCLMUL; 1611 bool HasLZCNT; 1612 bool HasRDRND; 1613 bool HasBMI; 1614 bool HasBMI2; 1615 bool HasPOPCNT; 1616 bool HasRTM; 1617 bool HasPRFCHW; 1618 bool HasRDSEED; 1619 bool HasTBM; 1620 bool HasFMA; 1621 bool HasF16C; 1622 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1623 bool HasSHA; 1624 bool HasCX16; 1625 1626 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1627 /// 1628 /// Each enumeration represents a particular CPU supported by Clang. These 1629 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1630 enum CPUKind { 1631 CK_Generic, 1632 1633 /// \name i386 1634 /// i386-generation processors. 1635 //@{ 1636 CK_i386, 1637 //@} 1638 1639 /// \name i486 1640 /// i486-generation processors. 1641 //@{ 1642 CK_i486, 1643 CK_WinChipC6, 1644 CK_WinChip2, 1645 CK_C3, 1646 //@} 1647 1648 /// \name i586 1649 /// i586-generation processors, P5 microarchitecture based. 1650 //@{ 1651 CK_i586, 1652 CK_Pentium, 1653 CK_PentiumMMX, 1654 //@} 1655 1656 /// \name i686 1657 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1658 //@{ 1659 CK_i686, 1660 CK_PentiumPro, 1661 CK_Pentium2, 1662 CK_Pentium3, 1663 CK_Pentium3M, 1664 CK_PentiumM, 1665 CK_C3_2, 1666 1667 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1668 /// Clang however has some logic to suport this. 1669 // FIXME: Warn, deprecate, and potentially remove this. 1670 CK_Yonah, 1671 //@} 1672 1673 /// \name Netburst 1674 /// Netburst microarchitecture based processors. 1675 //@{ 1676 CK_Pentium4, 1677 CK_Pentium4M, 1678 CK_Prescott, 1679 CK_Nocona, 1680 //@} 1681 1682 /// \name Core 1683 /// Core microarchitecture based processors. 1684 //@{ 1685 CK_Core2, 1686 1687 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1688 /// codename which GCC no longer accepts as an option to -march, but Clang 1689 /// has some logic for recognizing it. 1690 // FIXME: Warn, deprecate, and potentially remove this. 1691 CK_Penryn, 1692 //@} 1693 1694 /// \name Atom 1695 /// Atom processors 1696 //@{ 1697 CK_Atom, 1698 CK_Silvermont, 1699 //@} 1700 1701 /// \name Nehalem 1702 /// Nehalem microarchitecture based processors. 1703 //@{ 1704 CK_Corei7, 1705 CK_Corei7AVX, 1706 CK_CoreAVXi, 1707 CK_CoreAVX2, 1708 //@} 1709 1710 /// \name Knights Landing 1711 /// Knights Landing processor. 1712 CK_KNL, 1713 1714 /// \name K6 1715 /// K6 architecture processors. 1716 //@{ 1717 CK_K6, 1718 CK_K6_2, 1719 CK_K6_3, 1720 //@} 1721 1722 /// \name K7 1723 /// K7 architecture processors. 1724 //@{ 1725 CK_Athlon, 1726 CK_AthlonThunderbird, 1727 CK_Athlon4, 1728 CK_AthlonXP, 1729 CK_AthlonMP, 1730 //@} 1731 1732 /// \name K8 1733 /// K8 architecture processors. 1734 //@{ 1735 CK_Athlon64, 1736 CK_Athlon64SSE3, 1737 CK_AthlonFX, 1738 CK_K8, 1739 CK_K8SSE3, 1740 CK_Opteron, 1741 CK_OpteronSSE3, 1742 CK_AMDFAM10, 1743 //@} 1744 1745 /// \name Bobcat 1746 /// Bobcat architecture processors. 1747 //@{ 1748 CK_BTVER1, 1749 CK_BTVER2, 1750 //@} 1751 1752 /// \name Bulldozer 1753 /// Bulldozer architecture processors. 1754 //@{ 1755 CK_BDVER1, 1756 CK_BDVER2, 1757 CK_BDVER3, 1758 //@} 1759 1760 /// This specification is deprecated and will be removed in the future. 1761 /// Users should prefer \see CK_K8. 1762 // FIXME: Warn on this when the CPU is set to it. 1763 CK_x86_64, 1764 //@} 1765 1766 /// \name Geode 1767 /// Geode processors. 1768 //@{ 1769 CK_Geode 1770 //@} 1771 } CPU; 1772 1773 enum FPMathKind { 1774 FP_Default, 1775 FP_SSE, 1776 FP_387 1777 } FPMath; 1778 1779 public: 1780 X86TargetInfo(const llvm::Triple &Triple) 1781 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1782 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1783 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1784 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1785 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1786 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1787 FPMath(FP_Default) { 1788 BigEndian = false; 1789 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1790 } 1791 virtual unsigned getFloatEvalMethod() const { 1792 // X87 evaluates with 80 bits "long double" precision. 1793 return SSELevel == NoSSE ? 2 : 0; 1794 } 1795 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1796 unsigned &NumRecords) const { 1797 Records = BuiltinInfo; 1798 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1799 } 1800 virtual void getGCCRegNames(const char * const *&Names, 1801 unsigned &NumNames) const { 1802 Names = GCCRegNames; 1803 NumNames = llvm::array_lengthof(GCCRegNames); 1804 } 1805 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1806 unsigned &NumAliases) const { 1807 Aliases = 0; 1808 NumAliases = 0; 1809 } 1810 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1811 unsigned &NumNames) const { 1812 Names = AddlRegNames; 1813 NumNames = llvm::array_lengthof(AddlRegNames); 1814 } 1815 virtual bool validateAsmConstraint(const char *&Name, 1816 TargetInfo::ConstraintInfo &info) const; 1817 virtual std::string convertConstraint(const char *&Constraint) const; 1818 virtual const char *getClobbers() const { 1819 return "~{dirflag},~{fpsr},~{flags}"; 1820 } 1821 virtual void getTargetDefines(const LangOptions &Opts, 1822 MacroBuilder &Builder) const; 1823 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1824 bool Enabled); 1825 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1826 bool Enabled); 1827 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1828 bool Enabled); 1829 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1830 StringRef Name, bool Enabled) const { 1831 setFeatureEnabledImpl(Features, Name, Enabled); 1832 } 1833 // This exists purely to cut down on the number of virtual calls in 1834 // getDefaultFeatures which calls this repeatedly. 1835 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1836 StringRef Name, bool Enabled); 1837 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1838 virtual bool hasFeature(StringRef Feature) const; 1839 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1840 DiagnosticsEngine &Diags); 1841 virtual const char* getABI() const { 1842 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1843 return "avx"; 1844 else if (getTriple().getArch() == llvm::Triple::x86 && 1845 MMX3DNowLevel == NoMMX3DNow) 1846 return "no-mmx"; 1847 return ""; 1848 } 1849 virtual bool setCPU(const std::string &Name) { 1850 CPU = llvm::StringSwitch<CPUKind>(Name) 1851 .Case("i386", CK_i386) 1852 .Case("i486", CK_i486) 1853 .Case("winchip-c6", CK_WinChipC6) 1854 .Case("winchip2", CK_WinChip2) 1855 .Case("c3", CK_C3) 1856 .Case("i586", CK_i586) 1857 .Case("pentium", CK_Pentium) 1858 .Case("pentium-mmx", CK_PentiumMMX) 1859 .Case("i686", CK_i686) 1860 .Case("pentiumpro", CK_PentiumPro) 1861 .Case("pentium2", CK_Pentium2) 1862 .Case("pentium3", CK_Pentium3) 1863 .Case("pentium3m", CK_Pentium3M) 1864 .Case("pentium-m", CK_PentiumM) 1865 .Case("c3-2", CK_C3_2) 1866 .Case("yonah", CK_Yonah) 1867 .Case("pentium4", CK_Pentium4) 1868 .Case("pentium4m", CK_Pentium4M) 1869 .Case("prescott", CK_Prescott) 1870 .Case("nocona", CK_Nocona) 1871 .Case("core2", CK_Core2) 1872 .Case("penryn", CK_Penryn) 1873 .Case("atom", CK_Atom) 1874 .Case("slm", CK_Silvermont) 1875 .Case("corei7", CK_Corei7) 1876 .Case("corei7-avx", CK_Corei7AVX) 1877 .Case("core-avx-i", CK_CoreAVXi) 1878 .Case("core-avx2", CK_CoreAVX2) 1879 .Case("knl", CK_KNL) 1880 .Case("k6", CK_K6) 1881 .Case("k6-2", CK_K6_2) 1882 .Case("k6-3", CK_K6_3) 1883 .Case("athlon", CK_Athlon) 1884 .Case("athlon-tbird", CK_AthlonThunderbird) 1885 .Case("athlon-4", CK_Athlon4) 1886 .Case("athlon-xp", CK_AthlonXP) 1887 .Case("athlon-mp", CK_AthlonMP) 1888 .Case("athlon64", CK_Athlon64) 1889 .Case("athlon64-sse3", CK_Athlon64SSE3) 1890 .Case("athlon-fx", CK_AthlonFX) 1891 .Case("k8", CK_K8) 1892 .Case("k8-sse3", CK_K8SSE3) 1893 .Case("opteron", CK_Opteron) 1894 .Case("opteron-sse3", CK_OpteronSSE3) 1895 .Case("amdfam10", CK_AMDFAM10) 1896 .Case("btver1", CK_BTVER1) 1897 .Case("btver2", CK_BTVER2) 1898 .Case("bdver1", CK_BDVER1) 1899 .Case("bdver2", CK_BDVER2) 1900 .Case("bdver3", CK_BDVER3) 1901 .Case("x86-64", CK_x86_64) 1902 .Case("geode", CK_Geode) 1903 .Default(CK_Generic); 1904 1905 // Perform any per-CPU checks necessary to determine if this CPU is 1906 // acceptable. 1907 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1908 // invalid without explaining *why*. 1909 switch (CPU) { 1910 case CK_Generic: 1911 // No processor selected! 1912 return false; 1913 1914 case CK_i386: 1915 case CK_i486: 1916 case CK_WinChipC6: 1917 case CK_WinChip2: 1918 case CK_C3: 1919 case CK_i586: 1920 case CK_Pentium: 1921 case CK_PentiumMMX: 1922 case CK_i686: 1923 case CK_PentiumPro: 1924 case CK_Pentium2: 1925 case CK_Pentium3: 1926 case CK_Pentium3M: 1927 case CK_PentiumM: 1928 case CK_Yonah: 1929 case CK_C3_2: 1930 case CK_Pentium4: 1931 case CK_Pentium4M: 1932 case CK_Prescott: 1933 case CK_K6: 1934 case CK_K6_2: 1935 case CK_K6_3: 1936 case CK_Athlon: 1937 case CK_AthlonThunderbird: 1938 case CK_Athlon4: 1939 case CK_AthlonXP: 1940 case CK_AthlonMP: 1941 case CK_Geode: 1942 // Only accept certain architectures when compiling in 32-bit mode. 1943 if (getTriple().getArch() != llvm::Triple::x86) 1944 return false; 1945 1946 // Fallthrough 1947 case CK_Nocona: 1948 case CK_Core2: 1949 case CK_Penryn: 1950 case CK_Atom: 1951 case CK_Silvermont: 1952 case CK_Corei7: 1953 case CK_Corei7AVX: 1954 case CK_CoreAVXi: 1955 case CK_CoreAVX2: 1956 case CK_KNL: 1957 case CK_Athlon64: 1958 case CK_Athlon64SSE3: 1959 case CK_AthlonFX: 1960 case CK_K8: 1961 case CK_K8SSE3: 1962 case CK_Opteron: 1963 case CK_OpteronSSE3: 1964 case CK_AMDFAM10: 1965 case CK_BTVER1: 1966 case CK_BTVER2: 1967 case CK_BDVER1: 1968 case CK_BDVER2: 1969 case CK_BDVER3: 1970 case CK_x86_64: 1971 return true; 1972 } 1973 llvm_unreachable("Unhandled CPU kind"); 1974 } 1975 1976 virtual bool setFPMath(StringRef Name); 1977 1978 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1979 // We accept all non-ARM calling conventions 1980 return (CC == CC_X86ThisCall || 1981 CC == CC_X86FastCall || 1982 CC == CC_X86StdCall || 1983 CC == CC_C || 1984 CC == CC_X86Pascal || 1985 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1986 } 1987 1988 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1989 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1990 } 1991 }; 1992 1993 bool X86TargetInfo::setFPMath(StringRef Name) { 1994 if (Name == "387") { 1995 FPMath = FP_387; 1996 return true; 1997 } 1998 if (Name == "sse") { 1999 FPMath = FP_SSE; 2000 return true; 2001 } 2002 return false; 2003 } 2004 2005 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2006 // FIXME: This *really* should not be here. 2007 2008 // X86_64 always has SSE2. 2009 if (getTriple().getArch() == llvm::Triple::x86_64) 2010 setFeatureEnabledImpl(Features, "sse2", true); 2011 2012 switch (CPU) { 2013 case CK_Generic: 2014 case CK_i386: 2015 case CK_i486: 2016 case CK_i586: 2017 case CK_Pentium: 2018 case CK_i686: 2019 case CK_PentiumPro: 2020 break; 2021 case CK_PentiumMMX: 2022 case CK_Pentium2: 2023 setFeatureEnabledImpl(Features, "mmx", true); 2024 break; 2025 case CK_Pentium3: 2026 case CK_Pentium3M: 2027 setFeatureEnabledImpl(Features, "sse", true); 2028 break; 2029 case CK_PentiumM: 2030 case CK_Pentium4: 2031 case CK_Pentium4M: 2032 case CK_x86_64: 2033 setFeatureEnabledImpl(Features, "sse2", true); 2034 break; 2035 case CK_Yonah: 2036 case CK_Prescott: 2037 case CK_Nocona: 2038 setFeatureEnabledImpl(Features, "sse3", true); 2039 setFeatureEnabledImpl(Features, "cx16", true); 2040 break; 2041 case CK_Core2: 2042 setFeatureEnabledImpl(Features, "ssse3", true); 2043 setFeatureEnabledImpl(Features, "cx16", true); 2044 break; 2045 case CK_Penryn: 2046 setFeatureEnabledImpl(Features, "sse4.1", true); 2047 setFeatureEnabledImpl(Features, "cx16", true); 2048 break; 2049 case CK_Atom: 2050 setFeatureEnabledImpl(Features, "ssse3", true); 2051 setFeatureEnabledImpl(Features, "cx16", true); 2052 break; 2053 case CK_Silvermont: 2054 setFeatureEnabledImpl(Features, "sse4.2", true); 2055 setFeatureEnabledImpl(Features, "aes", true); 2056 setFeatureEnabledImpl(Features, "cx16", true); 2057 setFeatureEnabledImpl(Features, "pclmul", true); 2058 break; 2059 case CK_Corei7: 2060 setFeatureEnabledImpl(Features, "sse4.2", true); 2061 setFeatureEnabledImpl(Features, "cx16", true); 2062 break; 2063 case CK_Corei7AVX: 2064 setFeatureEnabledImpl(Features, "avx", true); 2065 setFeatureEnabledImpl(Features, "aes", true); 2066 setFeatureEnabledImpl(Features, "cx16", true); 2067 setFeatureEnabledImpl(Features, "pclmul", true); 2068 break; 2069 case CK_CoreAVXi: 2070 setFeatureEnabledImpl(Features, "avx", true); 2071 setFeatureEnabledImpl(Features, "aes", true); 2072 setFeatureEnabledImpl(Features, "pclmul", true); 2073 setFeatureEnabledImpl(Features, "rdrnd", true); 2074 setFeatureEnabledImpl(Features, "f16c", true); 2075 break; 2076 case CK_CoreAVX2: 2077 setFeatureEnabledImpl(Features, "avx2", true); 2078 setFeatureEnabledImpl(Features, "aes", true); 2079 setFeatureEnabledImpl(Features, "pclmul", true); 2080 setFeatureEnabledImpl(Features, "lzcnt", true); 2081 setFeatureEnabledImpl(Features, "rdrnd", true); 2082 setFeatureEnabledImpl(Features, "f16c", true); 2083 setFeatureEnabledImpl(Features, "bmi", true); 2084 setFeatureEnabledImpl(Features, "bmi2", true); 2085 setFeatureEnabledImpl(Features, "rtm", true); 2086 setFeatureEnabledImpl(Features, "fma", true); 2087 setFeatureEnabledImpl(Features, "cx16", true); 2088 break; 2089 case CK_KNL: 2090 setFeatureEnabledImpl(Features, "avx512f", true); 2091 setFeatureEnabledImpl(Features, "avx512cd", true); 2092 setFeatureEnabledImpl(Features, "avx512er", true); 2093 setFeatureEnabledImpl(Features, "avx512pf", true); 2094 setFeatureEnabledImpl(Features, "aes", true); 2095 setFeatureEnabledImpl(Features, "pclmul", true); 2096 setFeatureEnabledImpl(Features, "lzcnt", true); 2097 setFeatureEnabledImpl(Features, "rdrnd", true); 2098 setFeatureEnabledImpl(Features, "f16c", true); 2099 setFeatureEnabledImpl(Features, "bmi", true); 2100 setFeatureEnabledImpl(Features, "bmi2", true); 2101 setFeatureEnabledImpl(Features, "rtm", true); 2102 setFeatureEnabledImpl(Features, "fma", true); 2103 break; 2104 case CK_K6: 2105 case CK_WinChipC6: 2106 setFeatureEnabledImpl(Features, "mmx", true); 2107 break; 2108 case CK_K6_2: 2109 case CK_K6_3: 2110 case CK_WinChip2: 2111 case CK_C3: 2112 setFeatureEnabledImpl(Features, "3dnow", true); 2113 break; 2114 case CK_Athlon: 2115 case CK_AthlonThunderbird: 2116 case CK_Geode: 2117 setFeatureEnabledImpl(Features, "3dnowa", true); 2118 break; 2119 case CK_Athlon4: 2120 case CK_AthlonXP: 2121 case CK_AthlonMP: 2122 setFeatureEnabledImpl(Features, "sse", true); 2123 setFeatureEnabledImpl(Features, "3dnowa", true); 2124 break; 2125 case CK_K8: 2126 case CK_Opteron: 2127 case CK_Athlon64: 2128 case CK_AthlonFX: 2129 setFeatureEnabledImpl(Features, "sse2", true); 2130 setFeatureEnabledImpl(Features, "3dnowa", true); 2131 break; 2132 case CK_K8SSE3: 2133 case CK_OpteronSSE3: 2134 case CK_Athlon64SSE3: 2135 setFeatureEnabledImpl(Features, "sse3", true); 2136 setFeatureEnabledImpl(Features, "3dnowa", true); 2137 break; 2138 case CK_AMDFAM10: 2139 setFeatureEnabledImpl(Features, "sse3", true); 2140 setFeatureEnabledImpl(Features, "sse4a", true); 2141 setFeatureEnabledImpl(Features, "3dnowa", true); 2142 setFeatureEnabledImpl(Features, "lzcnt", true); 2143 setFeatureEnabledImpl(Features, "popcnt", true); 2144 break; 2145 case CK_BTVER1: 2146 setFeatureEnabledImpl(Features, "ssse3", true); 2147 setFeatureEnabledImpl(Features, "sse4a", true); 2148 setFeatureEnabledImpl(Features, "cx16", true); 2149 setFeatureEnabledImpl(Features, "lzcnt", true); 2150 setFeatureEnabledImpl(Features, "popcnt", true); 2151 setFeatureEnabledImpl(Features, "prfchw", true); 2152 break; 2153 case CK_BTVER2: 2154 setFeatureEnabledImpl(Features, "avx", true); 2155 setFeatureEnabledImpl(Features, "sse4a", true); 2156 setFeatureEnabledImpl(Features, "lzcnt", true); 2157 setFeatureEnabledImpl(Features, "aes", true); 2158 setFeatureEnabledImpl(Features, "pclmul", true); 2159 setFeatureEnabledImpl(Features, "prfchw", true); 2160 setFeatureEnabledImpl(Features, "bmi", true); 2161 setFeatureEnabledImpl(Features, "f16c", true); 2162 setFeatureEnabledImpl(Features, "cx16", true); 2163 break; 2164 case CK_BDVER1: 2165 setFeatureEnabledImpl(Features, "xop", true); 2166 setFeatureEnabledImpl(Features, "lzcnt", true); 2167 setFeatureEnabledImpl(Features, "aes", true); 2168 setFeatureEnabledImpl(Features, "pclmul", true); 2169 setFeatureEnabledImpl(Features, "prfchw", true); 2170 setFeatureEnabledImpl(Features, "cx16", true); 2171 break; 2172 case CK_BDVER2: 2173 case CK_BDVER3: 2174 setFeatureEnabledImpl(Features, "xop", true); 2175 setFeatureEnabledImpl(Features, "lzcnt", true); 2176 setFeatureEnabledImpl(Features, "aes", true); 2177 setFeatureEnabledImpl(Features, "pclmul", true); 2178 setFeatureEnabledImpl(Features, "prfchw", true); 2179 setFeatureEnabledImpl(Features, "bmi", true); 2180 setFeatureEnabledImpl(Features, "fma", true); 2181 setFeatureEnabledImpl(Features, "f16c", true); 2182 setFeatureEnabledImpl(Features, "tbm", true); 2183 setFeatureEnabledImpl(Features, "cx16", true); 2184 break; 2185 case CK_C3_2: 2186 setFeatureEnabledImpl(Features, "sse", true); 2187 break; 2188 } 2189 } 2190 2191 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2192 X86SSEEnum Level, bool Enabled) { 2193 if (Enabled) { 2194 switch (Level) { 2195 case AVX512F: 2196 Features["avx512f"] = true; 2197 case AVX2: 2198 Features["avx2"] = true; 2199 case AVX: 2200 Features["avx"] = true; 2201 case SSE42: 2202 Features["sse4.2"] = true; 2203 case SSE41: 2204 Features["sse4.1"] = true; 2205 case SSSE3: 2206 Features["ssse3"] = true; 2207 case SSE3: 2208 Features["sse3"] = true; 2209 case SSE2: 2210 Features["sse2"] = true; 2211 case SSE1: 2212 Features["sse"] = true; 2213 case NoSSE: 2214 break; 2215 } 2216 return; 2217 } 2218 2219 switch (Level) { 2220 case NoSSE: 2221 case SSE1: 2222 Features["sse"] = false; 2223 case SSE2: 2224 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2225 Features["sha"] = false; 2226 case SSE3: 2227 Features["sse3"] = false; 2228 setXOPLevel(Features, NoXOP, false); 2229 case SSSE3: 2230 Features["ssse3"] = false; 2231 case SSE41: 2232 Features["sse4.1"] = false; 2233 case SSE42: 2234 Features["sse4.2"] = false; 2235 case AVX: 2236 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2237 setXOPLevel(Features, FMA4, false); 2238 case AVX2: 2239 Features["avx2"] = false; 2240 case AVX512F: 2241 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2242 Features["avx512pf"] = false; 2243 } 2244 } 2245 2246 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2247 MMX3DNowEnum Level, bool Enabled) { 2248 if (Enabled) { 2249 switch (Level) { 2250 case AMD3DNowAthlon: 2251 Features["3dnowa"] = true; 2252 case AMD3DNow: 2253 Features["3dnow"] = true; 2254 case MMX: 2255 Features["mmx"] = true; 2256 case NoMMX3DNow: 2257 break; 2258 } 2259 return; 2260 } 2261 2262 switch (Level) { 2263 case NoMMX3DNow: 2264 case MMX: 2265 Features["mmx"] = false; 2266 case AMD3DNow: 2267 Features["3dnow"] = false; 2268 case AMD3DNowAthlon: 2269 Features["3dnowa"] = false; 2270 } 2271 } 2272 2273 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2274 bool Enabled) { 2275 if (Enabled) { 2276 switch (Level) { 2277 case XOP: 2278 Features["xop"] = true; 2279 case FMA4: 2280 Features["fma4"] = true; 2281 setSSELevel(Features, AVX, true); 2282 case SSE4A: 2283 Features["sse4a"] = true; 2284 setSSELevel(Features, SSE3, true); 2285 case NoXOP: 2286 break; 2287 } 2288 return; 2289 } 2290 2291 switch (Level) { 2292 case NoXOP: 2293 case SSE4A: 2294 Features["sse4a"] = false; 2295 case FMA4: 2296 Features["fma4"] = false; 2297 case XOP: 2298 Features["xop"] = false; 2299 } 2300 } 2301 2302 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2303 StringRef Name, bool Enabled) { 2304 // FIXME: This *really* should not be here. We need some way of translating 2305 // options into llvm subtarget features. 2306 if (Name == "sse4") 2307 Name = "sse4.2"; 2308 2309 Features[Name] = Enabled; 2310 2311 if (Name == "mmx") { 2312 setMMXLevel(Features, MMX, Enabled); 2313 } else if (Name == "sse") { 2314 setSSELevel(Features, SSE1, Enabled); 2315 } else if (Name == "sse2") { 2316 setSSELevel(Features, SSE2, Enabled); 2317 } else if (Name == "sse3") { 2318 setSSELevel(Features, SSE3, Enabled); 2319 } else if (Name == "ssse3") { 2320 setSSELevel(Features, SSSE3, Enabled); 2321 } else if (Name == "sse4.2") { 2322 setSSELevel(Features, SSE42, Enabled); 2323 } else if (Name == "sse4.1") { 2324 setSSELevel(Features, SSE41, Enabled); 2325 } else if (Name == "3dnow") { 2326 setMMXLevel(Features, AMD3DNow, Enabled); 2327 } else if (Name == "3dnowa") { 2328 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2329 } else if (Name == "aes") { 2330 if (Enabled) 2331 setSSELevel(Features, SSE2, Enabled); 2332 } else if (Name == "pclmul") { 2333 if (Enabled) 2334 setSSELevel(Features, SSE2, Enabled); 2335 } else if (Name == "avx") { 2336 setSSELevel(Features, AVX, Enabled); 2337 } else if (Name == "avx2") { 2338 setSSELevel(Features, AVX2, Enabled); 2339 } else if (Name == "avx512f") { 2340 setSSELevel(Features, AVX512F, Enabled); 2341 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2342 if (Enabled) 2343 setSSELevel(Features, AVX512F, Enabled); 2344 } else if (Name == "fma") { 2345 if (Enabled) 2346 setSSELevel(Features, AVX, Enabled); 2347 } else if (Name == "fma4") { 2348 setXOPLevel(Features, FMA4, Enabled); 2349 } else if (Name == "xop") { 2350 setXOPLevel(Features, XOP, Enabled); 2351 } else if (Name == "sse4a") { 2352 setXOPLevel(Features, SSE4A, Enabled); 2353 } else if (Name == "f16c") { 2354 if (Enabled) 2355 setSSELevel(Features, AVX, Enabled); 2356 } else if (Name == "sha") { 2357 if (Enabled) 2358 setSSELevel(Features, SSE2, Enabled); 2359 } 2360 } 2361 2362 /// handleTargetFeatures - Perform initialization based on the user 2363 /// configured set of features. 2364 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2365 DiagnosticsEngine &Diags) { 2366 // Remember the maximum enabled sselevel. 2367 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2368 // Ignore disabled features. 2369 if (Features[i][0] == '-') 2370 continue; 2371 2372 StringRef Feature = StringRef(Features[i]).substr(1); 2373 2374 if (Feature == "aes") { 2375 HasAES = true; 2376 continue; 2377 } 2378 2379 if (Feature == "pclmul") { 2380 HasPCLMUL = true; 2381 continue; 2382 } 2383 2384 if (Feature == "lzcnt") { 2385 HasLZCNT = true; 2386 continue; 2387 } 2388 2389 if (Feature == "rdrnd") { 2390 HasRDRND = true; 2391 continue; 2392 } 2393 2394 if (Feature == "bmi") { 2395 HasBMI = true; 2396 continue; 2397 } 2398 2399 if (Feature == "bmi2") { 2400 HasBMI2 = true; 2401 continue; 2402 } 2403 2404 if (Feature == "popcnt") { 2405 HasPOPCNT = true; 2406 continue; 2407 } 2408 2409 if (Feature == "rtm") { 2410 HasRTM = true; 2411 continue; 2412 } 2413 2414 if (Feature == "prfchw") { 2415 HasPRFCHW = true; 2416 continue; 2417 } 2418 2419 if (Feature == "rdseed") { 2420 HasRDSEED = true; 2421 continue; 2422 } 2423 2424 if (Feature == "tbm") { 2425 HasTBM = true; 2426 continue; 2427 } 2428 2429 if (Feature == "fma") { 2430 HasFMA = true; 2431 continue; 2432 } 2433 2434 if (Feature == "f16c") { 2435 HasF16C = true; 2436 continue; 2437 } 2438 2439 if (Feature == "avx512cd") { 2440 HasAVX512CD = true; 2441 continue; 2442 } 2443 2444 if (Feature == "avx512er") { 2445 HasAVX512ER = true; 2446 continue; 2447 } 2448 2449 if (Feature == "avx512pf") { 2450 HasAVX512PF = true; 2451 continue; 2452 } 2453 2454 if (Feature == "sha") { 2455 HasSHA = true; 2456 continue; 2457 } 2458 2459 if (Feature == "cx16") { 2460 HasCX16 = true; 2461 continue; 2462 } 2463 2464 assert(Features[i][0] == '+' && "Invalid target feature!"); 2465 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2466 .Case("avx512f", AVX512F) 2467 .Case("avx2", AVX2) 2468 .Case("avx", AVX) 2469 .Case("sse4.2", SSE42) 2470 .Case("sse4.1", SSE41) 2471 .Case("ssse3", SSSE3) 2472 .Case("sse3", SSE3) 2473 .Case("sse2", SSE2) 2474 .Case("sse", SSE1) 2475 .Default(NoSSE); 2476 SSELevel = std::max(SSELevel, Level); 2477 2478 MMX3DNowEnum ThreeDNowLevel = 2479 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2480 .Case("3dnowa", AMD3DNowAthlon) 2481 .Case("3dnow", AMD3DNow) 2482 .Case("mmx", MMX) 2483 .Default(NoMMX3DNow); 2484 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2485 2486 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2487 .Case("xop", XOP) 2488 .Case("fma4", FMA4) 2489 .Case("sse4a", SSE4A) 2490 .Default(NoXOP); 2491 XOPLevel = std::max(XOPLevel, XLevel); 2492 } 2493 2494 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2495 // Can't do this earlier because we need to be able to explicitly enable 2496 // popcnt and still disable sse4.2. 2497 if (!HasPOPCNT && SSELevel >= SSE42 && 2498 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2499 HasPOPCNT = true; 2500 Features.push_back("+popcnt"); 2501 } 2502 2503 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2504 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2505 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2506 HasPRFCHW = true; 2507 Features.push_back("+prfchw"); 2508 } 2509 2510 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2511 // matches the selected sse level. 2512 if (FPMath == FP_SSE && SSELevel < SSE1) { 2513 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2514 return false; 2515 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2516 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2517 return false; 2518 } 2519 2520 // Don't tell the backend if we're turning off mmx; it will end up disabling 2521 // SSE, which we don't want. 2522 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2523 // then enable MMX. 2524 std::vector<std::string>::iterator it; 2525 it = std::find(Features.begin(), Features.end(), "-mmx"); 2526 if (it != Features.end()) 2527 Features.erase(it); 2528 else if (SSELevel > NoSSE) 2529 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2530 return true; 2531 } 2532 2533 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2534 /// definitions for this particular subtarget. 2535 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2536 MacroBuilder &Builder) const { 2537 // Target identification. 2538 if (getTriple().getArch() == llvm::Triple::x86_64) { 2539 Builder.defineMacro("__amd64__"); 2540 Builder.defineMacro("__amd64"); 2541 Builder.defineMacro("__x86_64"); 2542 Builder.defineMacro("__x86_64__"); 2543 } else { 2544 DefineStd(Builder, "i386", Opts); 2545 } 2546 2547 // Subtarget options. 2548 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2549 // truly should be based on -mtune options. 2550 switch (CPU) { 2551 case CK_Generic: 2552 break; 2553 case CK_i386: 2554 // The rest are coming from the i386 define above. 2555 Builder.defineMacro("__tune_i386__"); 2556 break; 2557 case CK_i486: 2558 case CK_WinChipC6: 2559 case CK_WinChip2: 2560 case CK_C3: 2561 defineCPUMacros(Builder, "i486"); 2562 break; 2563 case CK_PentiumMMX: 2564 Builder.defineMacro("__pentium_mmx__"); 2565 Builder.defineMacro("__tune_pentium_mmx__"); 2566 // Fallthrough 2567 case CK_i586: 2568 case CK_Pentium: 2569 defineCPUMacros(Builder, "i586"); 2570 defineCPUMacros(Builder, "pentium"); 2571 break; 2572 case CK_Pentium3: 2573 case CK_Pentium3M: 2574 case CK_PentiumM: 2575 Builder.defineMacro("__tune_pentium3__"); 2576 // Fallthrough 2577 case CK_Pentium2: 2578 case CK_C3_2: 2579 Builder.defineMacro("__tune_pentium2__"); 2580 // Fallthrough 2581 case CK_PentiumPro: 2582 Builder.defineMacro("__tune_i686__"); 2583 Builder.defineMacro("__tune_pentiumpro__"); 2584 // Fallthrough 2585 case CK_i686: 2586 Builder.defineMacro("__i686"); 2587 Builder.defineMacro("__i686__"); 2588 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2589 Builder.defineMacro("__pentiumpro"); 2590 Builder.defineMacro("__pentiumpro__"); 2591 break; 2592 case CK_Pentium4: 2593 case CK_Pentium4M: 2594 defineCPUMacros(Builder, "pentium4"); 2595 break; 2596 case CK_Yonah: 2597 case CK_Prescott: 2598 case CK_Nocona: 2599 defineCPUMacros(Builder, "nocona"); 2600 break; 2601 case CK_Core2: 2602 case CK_Penryn: 2603 defineCPUMacros(Builder, "core2"); 2604 break; 2605 case CK_Atom: 2606 defineCPUMacros(Builder, "atom"); 2607 break; 2608 case CK_Silvermont: 2609 defineCPUMacros(Builder, "slm"); 2610 break; 2611 case CK_Corei7: 2612 case CK_Corei7AVX: 2613 case CK_CoreAVXi: 2614 case CK_CoreAVX2: 2615 defineCPUMacros(Builder, "corei7"); 2616 break; 2617 case CK_KNL: 2618 defineCPUMacros(Builder, "knl"); 2619 break; 2620 case CK_K6_2: 2621 Builder.defineMacro("__k6_2__"); 2622 Builder.defineMacro("__tune_k6_2__"); 2623 // Fallthrough 2624 case CK_K6_3: 2625 if (CPU != CK_K6_2) { // In case of fallthrough 2626 // FIXME: GCC may be enabling these in cases where some other k6 2627 // architecture is specified but -m3dnow is explicitly provided. The 2628 // exact semantics need to be determined and emulated here. 2629 Builder.defineMacro("__k6_3__"); 2630 Builder.defineMacro("__tune_k6_3__"); 2631 } 2632 // Fallthrough 2633 case CK_K6: 2634 defineCPUMacros(Builder, "k6"); 2635 break; 2636 case CK_Athlon: 2637 case CK_AthlonThunderbird: 2638 case CK_Athlon4: 2639 case CK_AthlonXP: 2640 case CK_AthlonMP: 2641 defineCPUMacros(Builder, "athlon"); 2642 if (SSELevel != NoSSE) { 2643 Builder.defineMacro("__athlon_sse__"); 2644 Builder.defineMacro("__tune_athlon_sse__"); 2645 } 2646 break; 2647 case CK_K8: 2648 case CK_K8SSE3: 2649 case CK_x86_64: 2650 case CK_Opteron: 2651 case CK_OpteronSSE3: 2652 case CK_Athlon64: 2653 case CK_Athlon64SSE3: 2654 case CK_AthlonFX: 2655 defineCPUMacros(Builder, "k8"); 2656 break; 2657 case CK_AMDFAM10: 2658 defineCPUMacros(Builder, "amdfam10"); 2659 break; 2660 case CK_BTVER1: 2661 defineCPUMacros(Builder, "btver1"); 2662 break; 2663 case CK_BTVER2: 2664 defineCPUMacros(Builder, "btver2"); 2665 break; 2666 case CK_BDVER1: 2667 defineCPUMacros(Builder, "bdver1"); 2668 break; 2669 case CK_BDVER2: 2670 defineCPUMacros(Builder, "bdver2"); 2671 break; 2672 case CK_BDVER3: 2673 defineCPUMacros(Builder, "bdver3"); 2674 break; 2675 case CK_Geode: 2676 defineCPUMacros(Builder, "geode"); 2677 break; 2678 } 2679 2680 // Target properties. 2681 Builder.defineMacro("__LITTLE_ENDIAN__"); 2682 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2683 2684 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2685 // functions in glibc header files that use FP Stack inline asm which the 2686 // backend can't deal with (PR879). 2687 Builder.defineMacro("__NO_MATH_INLINES"); 2688 2689 if (HasAES) 2690 Builder.defineMacro("__AES__"); 2691 2692 if (HasPCLMUL) 2693 Builder.defineMacro("__PCLMUL__"); 2694 2695 if (HasLZCNT) 2696 Builder.defineMacro("__LZCNT__"); 2697 2698 if (HasRDRND) 2699 Builder.defineMacro("__RDRND__"); 2700 2701 if (HasBMI) 2702 Builder.defineMacro("__BMI__"); 2703 2704 if (HasBMI2) 2705 Builder.defineMacro("__BMI2__"); 2706 2707 if (HasPOPCNT) 2708 Builder.defineMacro("__POPCNT__"); 2709 2710 if (HasRTM) 2711 Builder.defineMacro("__RTM__"); 2712 2713 if (HasPRFCHW) 2714 Builder.defineMacro("__PRFCHW__"); 2715 2716 if (HasRDSEED) 2717 Builder.defineMacro("__RDSEED__"); 2718 2719 if (HasTBM) 2720 Builder.defineMacro("__TBM__"); 2721 2722 switch (XOPLevel) { 2723 case XOP: 2724 Builder.defineMacro("__XOP__"); 2725 case FMA4: 2726 Builder.defineMacro("__FMA4__"); 2727 case SSE4A: 2728 Builder.defineMacro("__SSE4A__"); 2729 case NoXOP: 2730 break; 2731 } 2732 2733 if (HasFMA) 2734 Builder.defineMacro("__FMA__"); 2735 2736 if (HasF16C) 2737 Builder.defineMacro("__F16C__"); 2738 2739 if (HasAVX512CD) 2740 Builder.defineMacro("__AVX512CD__"); 2741 if (HasAVX512ER) 2742 Builder.defineMacro("__AVX512ER__"); 2743 if (HasAVX512PF) 2744 Builder.defineMacro("__AVX512PF__"); 2745 2746 if (HasSHA) 2747 Builder.defineMacro("__SHA__"); 2748 2749 if (HasCX16) 2750 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2751 2752 // Each case falls through to the previous one here. 2753 switch (SSELevel) { 2754 case AVX512F: 2755 Builder.defineMacro("__AVX512F__"); 2756 case AVX2: 2757 Builder.defineMacro("__AVX2__"); 2758 case AVX: 2759 Builder.defineMacro("__AVX__"); 2760 case SSE42: 2761 Builder.defineMacro("__SSE4_2__"); 2762 case SSE41: 2763 Builder.defineMacro("__SSE4_1__"); 2764 case SSSE3: 2765 Builder.defineMacro("__SSSE3__"); 2766 case SSE3: 2767 Builder.defineMacro("__SSE3__"); 2768 case SSE2: 2769 Builder.defineMacro("__SSE2__"); 2770 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2771 case SSE1: 2772 Builder.defineMacro("__SSE__"); 2773 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2774 case NoSSE: 2775 break; 2776 } 2777 2778 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2779 switch (SSELevel) { 2780 case AVX512F: 2781 case AVX2: 2782 case AVX: 2783 case SSE42: 2784 case SSE41: 2785 case SSSE3: 2786 case SSE3: 2787 case SSE2: 2788 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2789 break; 2790 case SSE1: 2791 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2792 break; 2793 default: 2794 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2795 } 2796 } 2797 2798 // Each case falls through to the previous one here. 2799 switch (MMX3DNowLevel) { 2800 case AMD3DNowAthlon: 2801 Builder.defineMacro("__3dNOW_A__"); 2802 case AMD3DNow: 2803 Builder.defineMacro("__3dNOW__"); 2804 case MMX: 2805 Builder.defineMacro("__MMX__"); 2806 case NoMMX3DNow: 2807 break; 2808 } 2809 2810 if (CPU >= CK_i486) { 2811 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2812 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2814 } 2815 if (CPU >= CK_i586) 2816 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2817 } 2818 2819 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2820 return llvm::StringSwitch<bool>(Feature) 2821 .Case("aes", HasAES) 2822 .Case("avx", SSELevel >= AVX) 2823 .Case("avx2", SSELevel >= AVX2) 2824 .Case("avx512f", SSELevel >= AVX512F) 2825 .Case("avx512cd", HasAVX512CD) 2826 .Case("avx512er", HasAVX512ER) 2827 .Case("avx512pf", HasAVX512PF) 2828 .Case("bmi", HasBMI) 2829 .Case("bmi2", HasBMI2) 2830 .Case("cx16", HasCX16) 2831 .Case("f16c", HasF16C) 2832 .Case("fma", HasFMA) 2833 .Case("fma4", XOPLevel >= FMA4) 2834 .Case("tbm", HasTBM) 2835 .Case("lzcnt", HasLZCNT) 2836 .Case("rdrnd", HasRDRND) 2837 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2838 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2839 .Case("mmx", MMX3DNowLevel >= MMX) 2840 .Case("pclmul", HasPCLMUL) 2841 .Case("popcnt", HasPOPCNT) 2842 .Case("rtm", HasRTM) 2843 .Case("prfchw", HasPRFCHW) 2844 .Case("rdseed", HasRDSEED) 2845 .Case("sha", HasSHA) 2846 .Case("sse", SSELevel >= SSE1) 2847 .Case("sse2", SSELevel >= SSE2) 2848 .Case("sse3", SSELevel >= SSE3) 2849 .Case("ssse3", SSELevel >= SSSE3) 2850 .Case("sse4.1", SSELevel >= SSE41) 2851 .Case("sse4.2", SSELevel >= SSE42) 2852 .Case("sse4a", XOPLevel >= SSE4A) 2853 .Case("x86", true) 2854 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2855 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2856 .Case("xop", XOPLevel >= XOP) 2857 .Default(false); 2858 } 2859 2860 bool 2861 X86TargetInfo::validateAsmConstraint(const char *&Name, 2862 TargetInfo::ConstraintInfo &Info) const { 2863 switch (*Name) { 2864 default: return false; 2865 case 'Y': // first letter of a pair: 2866 switch (*(Name+1)) { 2867 default: return false; 2868 case '0': // First SSE register. 2869 case 't': // Any SSE register, when SSE2 is enabled. 2870 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2871 case 'm': // any MMX register, when inter-unit moves enabled. 2872 break; // falls through to setAllowsRegister. 2873 } 2874 case 'a': // eax. 2875 case 'b': // ebx. 2876 case 'c': // ecx. 2877 case 'd': // edx. 2878 case 'S': // esi. 2879 case 'D': // edi. 2880 case 'A': // edx:eax. 2881 case 'f': // any x87 floating point stack register. 2882 case 't': // top of floating point stack. 2883 case 'u': // second from top of floating point stack. 2884 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2885 case 'y': // Any MMX register. 2886 case 'x': // Any SSE register. 2887 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2888 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2889 case 'l': // "Index" registers: any general register that can be used as an 2890 // index in a base+index memory access. 2891 Info.setAllowsRegister(); 2892 return true; 2893 case 'C': // SSE floating point constant. 2894 case 'G': // x87 floating point constant. 2895 case 'e': // 32-bit signed integer constant for use with zero-extending 2896 // x86_64 instructions. 2897 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2898 // x86_64 instructions. 2899 return true; 2900 } 2901 } 2902 2903 2904 std::string 2905 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2906 switch (*Constraint) { 2907 case 'a': return std::string("{ax}"); 2908 case 'b': return std::string("{bx}"); 2909 case 'c': return std::string("{cx}"); 2910 case 'd': return std::string("{dx}"); 2911 case 'S': return std::string("{si}"); 2912 case 'D': return std::string("{di}"); 2913 case 'p': // address 2914 return std::string("im"); 2915 case 't': // top of floating point stack. 2916 return std::string("{st}"); 2917 case 'u': // second from top of floating point stack. 2918 return std::string("{st(1)}"); // second from top of floating point stack. 2919 default: 2920 return std::string(1, *Constraint); 2921 } 2922 } 2923 } // end anonymous namespace 2924 2925 namespace { 2926 // X86-32 generic target 2927 class X86_32TargetInfo : public X86TargetInfo { 2928 public: 2929 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2930 DoubleAlign = LongLongAlign = 32; 2931 LongDoubleWidth = 96; 2932 LongDoubleAlign = 32; 2933 SuitableAlign = 128; 2934 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2935 SizeType = UnsignedInt; 2936 PtrDiffType = SignedInt; 2937 IntPtrType = SignedInt; 2938 RegParmMax = 3; 2939 2940 // Use fpret for all types. 2941 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2942 (1 << TargetInfo::Double) | 2943 (1 << TargetInfo::LongDouble)); 2944 2945 // x86-32 has atomics up to 8 bytes 2946 // FIXME: Check that we actually have cmpxchg8b before setting 2947 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2948 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2949 } 2950 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2951 return TargetInfo::CharPtrBuiltinVaList; 2952 } 2953 2954 int getEHDataRegisterNumber(unsigned RegNo) const { 2955 if (RegNo == 0) return 0; 2956 if (RegNo == 1) return 2; 2957 return -1; 2958 } 2959 virtual bool validateInputSize(StringRef Constraint, 2960 unsigned Size) const { 2961 switch (Constraint[0]) { 2962 default: break; 2963 case 'a': 2964 case 'b': 2965 case 'c': 2966 case 'd': 2967 return Size <= 32; 2968 } 2969 2970 return true; 2971 } 2972 }; 2973 } // end anonymous namespace 2974 2975 namespace { 2976 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2977 public: 2978 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2979 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2980 2981 virtual unsigned getFloatEvalMethod() const { 2982 unsigned Major, Minor, Micro; 2983 getTriple().getOSVersion(Major, Minor, Micro); 2984 // New NetBSD uses the default rounding mode. 2985 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2986 return X86_32TargetInfo::getFloatEvalMethod(); 2987 // NetBSD before 6.99.26 defaults to "double" rounding. 2988 return 1; 2989 } 2990 }; 2991 } // end anonymous namespace 2992 2993 namespace { 2994 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2995 public: 2996 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2997 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2998 SizeType = UnsignedLong; 2999 IntPtrType = SignedLong; 3000 PtrDiffType = SignedLong; 3001 } 3002 }; 3003 } // end anonymous namespace 3004 3005 namespace { 3006 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3007 public: 3008 BitrigI386TargetInfo(const llvm::Triple &Triple) 3009 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3010 SizeType = UnsignedLong; 3011 IntPtrType = SignedLong; 3012 PtrDiffType = SignedLong; 3013 } 3014 }; 3015 } // end anonymous namespace 3016 3017 namespace { 3018 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3019 public: 3020 DarwinI386TargetInfo(const llvm::Triple &Triple) 3021 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3022 LongDoubleWidth = 128; 3023 LongDoubleAlign = 128; 3024 SuitableAlign = 128; 3025 MaxVectorAlign = 256; 3026 SizeType = UnsignedLong; 3027 IntPtrType = SignedLong; 3028 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3029 HasAlignMac68kSupport = true; 3030 } 3031 3032 }; 3033 } // end anonymous namespace 3034 3035 namespace { 3036 // x86-32 Windows target 3037 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3038 public: 3039 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3040 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3041 TLSSupported = false; 3042 WCharType = UnsignedShort; 3043 DoubleAlign = LongLongAlign = 64; 3044 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3045 } 3046 virtual void getTargetDefines(const LangOptions &Opts, 3047 MacroBuilder &Builder) const { 3048 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3049 } 3050 }; 3051 } // end anonymous namespace 3052 3053 namespace { 3054 3055 // x86-32 Windows Visual Studio target 3056 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3057 public: 3058 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3059 : WindowsX86_32TargetInfo(Triple) { 3060 LongDoubleWidth = LongDoubleAlign = 64; 3061 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3062 } 3063 virtual void getTargetDefines(const LangOptions &Opts, 3064 MacroBuilder &Builder) const { 3065 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3066 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3067 // The value of the following reflects processor type. 3068 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3069 // We lost the original triple, so we use the default. 3070 Builder.defineMacro("_M_IX86", "600"); 3071 } 3072 }; 3073 } // end anonymous namespace 3074 3075 namespace { 3076 // x86-32 MinGW target 3077 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3078 public: 3079 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3080 : WindowsX86_32TargetInfo(Triple) {} 3081 virtual void getTargetDefines(const LangOptions &Opts, 3082 MacroBuilder &Builder) const { 3083 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3084 DefineStd(Builder, "WIN32", Opts); 3085 DefineStd(Builder, "WINNT", Opts); 3086 Builder.defineMacro("_X86_"); 3087 Builder.defineMacro("__MSVCRT__"); 3088 Builder.defineMacro("__MINGW32__"); 3089 3090 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3091 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3092 if (Opts.MicrosoftExt) 3093 // Provide "as-is" __declspec. 3094 Builder.defineMacro("__declspec", "__declspec"); 3095 else 3096 // Provide alias of __attribute__ like mingw32-gcc. 3097 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3098 } 3099 }; 3100 } // end anonymous namespace 3101 3102 namespace { 3103 // x86-32 Cygwin target 3104 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3105 public: 3106 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3107 : X86_32TargetInfo(Triple) { 3108 TLSSupported = false; 3109 WCharType = UnsignedShort; 3110 DoubleAlign = LongLongAlign = 64; 3111 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3112 } 3113 virtual void getTargetDefines(const LangOptions &Opts, 3114 MacroBuilder &Builder) const { 3115 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3116 Builder.defineMacro("_X86_"); 3117 Builder.defineMacro("__CYGWIN__"); 3118 Builder.defineMacro("__CYGWIN32__"); 3119 DefineStd(Builder, "unix", Opts); 3120 if (Opts.CPlusPlus) 3121 Builder.defineMacro("_GNU_SOURCE"); 3122 } 3123 }; 3124 } // end anonymous namespace 3125 3126 namespace { 3127 // x86-32 Haiku target 3128 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3129 public: 3130 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3131 SizeType = UnsignedLong; 3132 IntPtrType = SignedLong; 3133 PtrDiffType = SignedLong; 3134 ProcessIDType = SignedLong; 3135 this->UserLabelPrefix = ""; 3136 this->TLSSupported = false; 3137 } 3138 virtual void getTargetDefines(const LangOptions &Opts, 3139 MacroBuilder &Builder) const { 3140 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3141 Builder.defineMacro("__INTEL__"); 3142 Builder.defineMacro("__HAIKU__"); 3143 } 3144 }; 3145 } // end anonymous namespace 3146 3147 // RTEMS Target 3148 template<typename Target> 3149 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3150 protected: 3151 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3152 MacroBuilder &Builder) const { 3153 // RTEMS defines; list based off of gcc output 3154 3155 Builder.defineMacro("__rtems__"); 3156 Builder.defineMacro("__ELF__"); 3157 } 3158 3159 public: 3160 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3161 this->UserLabelPrefix = ""; 3162 3163 switch (Triple.getArch()) { 3164 default: 3165 case llvm::Triple::x86: 3166 // this->MCountName = ".mcount"; 3167 break; 3168 case llvm::Triple::mips: 3169 case llvm::Triple::mipsel: 3170 case llvm::Triple::ppc: 3171 case llvm::Triple::ppc64: 3172 case llvm::Triple::ppc64le: 3173 // this->MCountName = "_mcount"; 3174 break; 3175 case llvm::Triple::arm: 3176 // this->MCountName = "__mcount"; 3177 break; 3178 } 3179 } 3180 }; 3181 3182 namespace { 3183 // x86-32 RTEMS target 3184 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3185 public: 3186 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3187 SizeType = UnsignedLong; 3188 IntPtrType = SignedLong; 3189 PtrDiffType = SignedLong; 3190 this->UserLabelPrefix = ""; 3191 } 3192 virtual void getTargetDefines(const LangOptions &Opts, 3193 MacroBuilder &Builder) const { 3194 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3195 Builder.defineMacro("__INTEL__"); 3196 Builder.defineMacro("__rtems__"); 3197 } 3198 }; 3199 } // end anonymous namespace 3200 3201 namespace { 3202 // x86-64 generic target 3203 class X86_64TargetInfo : public X86TargetInfo { 3204 public: 3205 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3206 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3207 LongDoubleWidth = 128; 3208 LongDoubleAlign = 128; 3209 LargeArrayMinWidth = 128; 3210 LargeArrayAlign = 128; 3211 SuitableAlign = 128; 3212 IntMaxType = SignedLong; 3213 UIntMaxType = UnsignedLong; 3214 Int64Type = SignedLong; 3215 RegParmMax = 6; 3216 3217 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3218 3219 // Use fpret only for long double. 3220 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3221 3222 // Use fp2ret for _Complex long double. 3223 ComplexLongDoubleUsesFP2Ret = true; 3224 3225 // x86-64 has atomics up to 16 bytes. 3226 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3227 // on CPUs with cmpxchg16b 3228 MaxAtomicPromoteWidth = 128; 3229 MaxAtomicInlineWidth = 64; 3230 } 3231 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3232 return TargetInfo::X86_64ABIBuiltinVaList; 3233 } 3234 3235 int getEHDataRegisterNumber(unsigned RegNo) const { 3236 if (RegNo == 0) return 0; 3237 if (RegNo == 1) return 1; 3238 return -1; 3239 } 3240 3241 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3242 return (CC == CC_C || 3243 CC == CC_IntelOclBicc || 3244 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3245 } 3246 3247 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3248 return CC_C; 3249 } 3250 3251 }; 3252 } // end anonymous namespace 3253 3254 namespace { 3255 // x86-64 Windows target 3256 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3257 public: 3258 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3259 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3260 TLSSupported = false; 3261 WCharType = UnsignedShort; 3262 LongWidth = LongAlign = 32; 3263 DoubleAlign = LongLongAlign = 64; 3264 IntMaxType = SignedLongLong; 3265 UIntMaxType = UnsignedLongLong; 3266 Int64Type = SignedLongLong; 3267 SizeType = UnsignedLongLong; 3268 PtrDiffType = SignedLongLong; 3269 IntPtrType = SignedLongLong; 3270 this->UserLabelPrefix = ""; 3271 } 3272 virtual void getTargetDefines(const LangOptions &Opts, 3273 MacroBuilder &Builder) const { 3274 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3275 Builder.defineMacro("_WIN64"); 3276 } 3277 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3278 return TargetInfo::CharPtrBuiltinVaList; 3279 } 3280 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3281 return (CC == CC_C || 3282 CC == CC_IntelOclBicc || 3283 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3284 } 3285 }; 3286 } // end anonymous namespace 3287 3288 namespace { 3289 // x86-64 Windows Visual Studio target 3290 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3291 public: 3292 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3293 : WindowsX86_64TargetInfo(Triple) { 3294 LongDoubleWidth = LongDoubleAlign = 64; 3295 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3296 } 3297 virtual void getTargetDefines(const LangOptions &Opts, 3298 MacroBuilder &Builder) const { 3299 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3300 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3301 Builder.defineMacro("_M_X64"); 3302 Builder.defineMacro("_M_AMD64"); 3303 } 3304 }; 3305 } // end anonymous namespace 3306 3307 namespace { 3308 // x86-64 MinGW target 3309 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3310 public: 3311 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3312 : WindowsX86_64TargetInfo(Triple) {} 3313 virtual void getTargetDefines(const LangOptions &Opts, 3314 MacroBuilder &Builder) const { 3315 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3316 DefineStd(Builder, "WIN64", Opts); 3317 Builder.defineMacro("__MSVCRT__"); 3318 Builder.defineMacro("__MINGW32__"); 3319 Builder.defineMacro("__MINGW64__"); 3320 3321 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3322 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3323 if (Opts.MicrosoftExt) 3324 // Provide "as-is" __declspec. 3325 Builder.defineMacro("__declspec", "__declspec"); 3326 else 3327 // Provide alias of __attribute__ like mingw32-gcc. 3328 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3329 } 3330 }; 3331 } // end anonymous namespace 3332 3333 namespace { 3334 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3335 public: 3336 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3337 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3338 Int64Type = SignedLongLong; 3339 MaxVectorAlign = 256; 3340 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3341 } 3342 }; 3343 } // end anonymous namespace 3344 3345 namespace { 3346 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3347 public: 3348 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3349 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3350 IntMaxType = SignedLongLong; 3351 UIntMaxType = UnsignedLongLong; 3352 Int64Type = SignedLongLong; 3353 } 3354 }; 3355 } // end anonymous namespace 3356 3357 namespace { 3358 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3359 public: 3360 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3361 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3362 IntMaxType = SignedLongLong; 3363 UIntMaxType = UnsignedLongLong; 3364 Int64Type = SignedLongLong; 3365 } 3366 }; 3367 } 3368 3369 namespace { 3370 class AArch64TargetInfo : public TargetInfo { 3371 virtual void setDescriptionString() = 0; 3372 static const char * const GCCRegNames[]; 3373 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3374 3375 enum FPUModeEnum { 3376 FPUMode, 3377 NeonMode 3378 }; 3379 3380 unsigned FPU; 3381 unsigned Crypto; 3382 static const Builtin::Info BuiltinInfo[]; 3383 3384 public: 3385 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3386 IntMaxType = SignedLong; 3387 UIntMaxType = UnsignedLong; 3388 Int64Type = SignedLong; 3389 LongWidth = LongAlign = 64; 3390 LongDoubleWidth = LongDoubleAlign = 128; 3391 PointerWidth = PointerAlign = 64; 3392 SuitableAlign = 128; 3393 3394 WCharType = UnsignedInt; 3395 if (getTriple().getOS() == llvm::Triple::NetBSD) 3396 WCharType = SignedInt; 3397 else 3398 WCharType = UnsignedInt; 3399 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3400 3401 // AArch64 backend supports 64-bit operations at the moment. In principle 3402 // 128-bit is possible if register-pairs are used. 3403 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3404 3405 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3406 } 3407 virtual void getTargetDefines(const LangOptions &Opts, 3408 MacroBuilder &Builder) const { 3409 // GCC defines theses currently 3410 Builder.defineMacro("__aarch64__"); 3411 3412 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3413 Builder.defineMacro("__ARM_ACLE", "200"); 3414 Builder.defineMacro("__ARM_ARCH", "8"); 3415 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3416 3417 Builder.defineMacro("__ARM_64BIT_STATE"); 3418 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3419 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3420 3421 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3422 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3423 Builder.defineMacro("__ARM_FEATURE_FMA"); 3424 Builder.defineMacro("__ARM_FEATURE_DIV"); 3425 3426 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3427 3428 // 0xe implies support for half, single and double precision operations. 3429 Builder.defineMacro("__ARM_FP", "0xe"); 3430 3431 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3432 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3433 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3434 3435 if (Opts.FastMath || Opts.FiniteMathOnly) 3436 Builder.defineMacro("__ARM_FP_FAST"); 3437 3438 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3439 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3440 3441 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3442 Opts.ShortWChar ? "2" : "4"); 3443 3444 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3445 Opts.ShortEnums ? "1" : "4"); 3446 3447 if (BigEndian) 3448 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3449 3450 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3451 if (BigEndian) 3452 Builder.defineMacro("__BIG_ENDIAN__"); 3453 else 3454 Builder.defineMacro("__LITTLE_ENDIAN__"); 3455 } 3456 3457 if (FPU == NeonMode) { 3458 Builder.defineMacro("__ARM_NEON"); 3459 // 64-bit NEON supports half, single and double precision operations. 3460 Builder.defineMacro("__ARM_NEON_FP", "7"); 3461 } 3462 3463 if (Crypto) { 3464 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3465 } 3466 } 3467 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3468 unsigned &NumRecords) const { 3469 Records = BuiltinInfo; 3470 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3471 } 3472 virtual bool hasFeature(StringRef Feature) const { 3473 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3474 } 3475 3476 virtual bool setCPU(const std::string &Name) { 3477 return llvm::StringSwitch<bool>(Name) 3478 .Case("generic", true) 3479 .Cases("cortex-a53", "cortex-a57", true) 3480 .Default(false); 3481 } 3482 3483 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3484 DiagnosticsEngine &Diags) { 3485 FPU = FPUMode; 3486 Crypto = 0; 3487 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3488 if (Features[i] == "+neon") 3489 FPU = NeonMode; 3490 if (Features[i] == "+crypto") 3491 Crypto = 1; 3492 } 3493 3494 setDescriptionString(); 3495 3496 return true; 3497 } 3498 3499 virtual void getGCCRegNames(const char *const *&Names, 3500 unsigned &NumNames) const; 3501 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3502 unsigned &NumAliases) const; 3503 3504 virtual bool isCLZForZeroUndef() const { return false; } 3505 3506 virtual bool validateAsmConstraint(const char *&Name, 3507 TargetInfo::ConstraintInfo &Info) const { 3508 switch (*Name) { 3509 default: return false; 3510 case 'w': // An FP/SIMD vector register 3511 Info.setAllowsRegister(); 3512 return true; 3513 case 'I': // Constant that can be used with an ADD instruction 3514 case 'J': // Constant that can be used with a SUB instruction 3515 case 'K': // Constant that can be used with a 32-bit logical instruction 3516 case 'L': // Constant that can be used with a 64-bit logical instruction 3517 case 'M': // Constant that can be used as a 32-bit MOV immediate 3518 case 'N': // Constant that can be used as a 64-bit MOV immediate 3519 case 'Y': // Floating point constant zero 3520 case 'Z': // Integer constant zero 3521 return true; 3522 case 'Q': // A memory reference with base register and no offset 3523 Info.setAllowsMemory(); 3524 return true; 3525 case 'S': // A symbolic address 3526 Info.setAllowsRegister(); 3527 return true; 3528 case 'U': 3529 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3530 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3531 // Usa: An absolute symbolic address 3532 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3533 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3534 } 3535 } 3536 3537 virtual const char *getClobbers() const { 3538 // There are no AArch64 clobbers shared by all asm statements. 3539 return ""; 3540 } 3541 3542 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3543 return TargetInfo::AArch64ABIBuiltinVaList; 3544 } 3545 }; 3546 3547 const char * const AArch64TargetInfo::GCCRegNames[] = { 3548 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3549 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3550 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3551 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3552 3553 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3554 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3555 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3556 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3557 3558 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3559 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3560 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3561 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3562 3563 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3564 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3565 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3566 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3567 3568 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3569 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3570 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3571 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3572 3573 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3574 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3575 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3576 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3577 3578 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3579 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3580 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3581 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3582 }; 3583 3584 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3585 unsigned &NumNames) const { 3586 Names = GCCRegNames; 3587 NumNames = llvm::array_lengthof(GCCRegNames); 3588 } 3589 3590 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3591 { { "x16" }, "ip0"}, 3592 { { "x17" }, "ip1"}, 3593 { { "x29" }, "fp" }, 3594 { { "x30" }, "lr" } 3595 }; 3596 3597 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3598 unsigned &NumAliases) const { 3599 Aliases = GCCRegAliases; 3600 NumAliases = llvm::array_lengthof(GCCRegAliases); 3601 3602 } 3603 3604 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3605 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3606 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3607 ALL_LANGUAGES }, 3608 #define GET_NEON_BUILTINS 3609 #include "clang/Basic/arm_neon.inc" 3610 #undef GET_NEON_BUILTINS 3611 3612 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3613 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3614 ALL_LANGUAGES }, 3615 #include "clang/Basic/BuiltinsAArch64.def" 3616 }; 3617 3618 class AArch64leTargetInfo : public AArch64TargetInfo { 3619 virtual void setDescriptionString() { 3620 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3621 } 3622 3623 public: 3624 AArch64leTargetInfo(const llvm::Triple &Triple) 3625 : AArch64TargetInfo(Triple) { 3626 BigEndian = false; 3627 } 3628 virtual void getTargetDefines(const LangOptions &Opts, 3629 MacroBuilder &Builder) const { 3630 Builder.defineMacro("__AARCH64EL__"); 3631 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3632 } 3633 }; 3634 3635 class AArch64beTargetInfo : public AArch64TargetInfo { 3636 virtual void setDescriptionString() { 3637 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3638 } 3639 3640 public: 3641 AArch64beTargetInfo(const llvm::Triple &Triple) 3642 : AArch64TargetInfo(Triple) { } 3643 virtual void getTargetDefines(const LangOptions &Opts, 3644 MacroBuilder &Builder) const { 3645 Builder.defineMacro("__AARCH64EB__"); 3646 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3647 } 3648 }; 3649 3650 } // end anonymous namespace 3651 3652 namespace { 3653 class ARMTargetInfo : public TargetInfo { 3654 // Possible FPU choices. 3655 enum FPUMode { 3656 VFP2FPU = (1 << 0), 3657 VFP3FPU = (1 << 1), 3658 VFP4FPU = (1 << 2), 3659 NeonFPU = (1 << 3), 3660 FPARMV8 = (1 << 4) 3661 }; 3662 3663 // Possible HWDiv features. 3664 enum HWDivMode { 3665 HWDivThumb = (1 << 0), 3666 HWDivARM = (1 << 1) 3667 }; 3668 3669 static bool FPUModeIsVFP(FPUMode Mode) { 3670 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3671 } 3672 3673 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3674 static const char * const GCCRegNames[]; 3675 3676 std::string ABI, CPU; 3677 3678 enum { 3679 FP_Default, 3680 FP_VFP, 3681 FP_Neon 3682 } FPMath; 3683 3684 unsigned FPU : 5; 3685 3686 unsigned IsAAPCS : 1; 3687 unsigned IsThumb : 1; 3688 unsigned HWDiv : 2; 3689 3690 // Initialized via features. 3691 unsigned SoftFloat : 1; 3692 unsigned SoftFloatABI : 1; 3693 3694 unsigned CRC : 1; 3695 unsigned Crypto : 1; 3696 3697 static const Builtin::Info BuiltinInfo[]; 3698 3699 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3700 // On linux, binaries targeting old cpus call functions in libgcc to 3701 // perform atomic operations. The implementation in libgcc then calls into 3702 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3703 // is that if we assume the kernel is at least as recent as the hardware, 3704 // it is safe to use atomic instructions on armv6 and newer. 3705 if (!T.isOSLinux() && 3706 T.getOS() != llvm::Triple::FreeBSD && 3707 T.getOS() != llvm::Triple::NetBSD && 3708 T.getOS() != llvm::Triple::Bitrig) 3709 return false; 3710 StringRef ArchName = T.getArchName(); 3711 if (T.getArch() == llvm::Triple::arm) { 3712 if (!ArchName.startswith("armv")) 3713 return false; 3714 StringRef VersionStr = ArchName.substr(4); 3715 unsigned Version; 3716 if (VersionStr.getAsInteger(10, Version)) 3717 return false; 3718 return Version >= 6; 3719 } 3720 assert(T.getArch() == llvm::Triple::thumb); 3721 if (!ArchName.startswith("thumbv")) 3722 return false; 3723 StringRef VersionStr = ArchName.substr(6); 3724 unsigned Version; 3725 if (VersionStr.getAsInteger(10, Version)) 3726 return false; 3727 return Version >= 7; 3728 } 3729 3730 void setABIAAPCS() { 3731 IsAAPCS = true; 3732 3733 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3734 const llvm::Triple &T = getTriple(); 3735 3736 // size_t is unsigned long on Darwin and NetBSD. 3737 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3738 SizeType = UnsignedLong; 3739 else 3740 SizeType = UnsignedInt; 3741 3742 if (T.getOS() == llvm::Triple::NetBSD) { 3743 WCharType = SignedInt; 3744 } else { 3745 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3746 WCharType = UnsignedInt; 3747 } 3748 3749 UseBitFieldTypeAlignment = true; 3750 3751 ZeroLengthBitfieldBoundary = 0; 3752 3753 if (IsThumb) { 3754 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3755 // so set preferred for small types to 32. 3756 if (T.isOSBinFormatMachO()) 3757 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3758 "v128:64:128-a:0:32-n32-S64"; 3759 else 3760 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3761 "v128:64:128-a:0:32-n32-S64"; 3762 3763 } else { 3764 if (T.isOSBinFormatMachO()) 3765 DescriptionString = "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3766 else 3767 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3768 } 3769 3770 // FIXME: Enumerated types are variable width in straight AAPCS. 3771 } 3772 3773 void setABIAPCS() { 3774 const llvm::Triple &T = getTriple(); 3775 3776 IsAAPCS = false; 3777 3778 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3779 3780 // size_t is unsigned int on FreeBSD. 3781 if (T.getOS() == llvm::Triple::FreeBSD) 3782 SizeType = UnsignedInt; 3783 else 3784 SizeType = UnsignedLong; 3785 3786 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3787 WCharType = SignedInt; 3788 3789 // Do not respect the alignment of bit-field types when laying out 3790 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3791 UseBitFieldTypeAlignment = false; 3792 3793 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3794 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3795 /// gcc. 3796 ZeroLengthBitfieldBoundary = 32; 3797 3798 if (IsThumb) { 3799 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3800 // so set preferred for small types to 32. 3801 if (T.isOSBinFormatMachO()) 3802 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3803 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3804 else 3805 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3806 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3807 } else { 3808 if (T.isOSBinFormatMachO()) 3809 DescriptionString = 3810 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3811 else 3812 DescriptionString = 3813 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3814 } 3815 3816 // FIXME: Override "preferred align" for double and long long. 3817 } 3818 3819 public: 3820 ARMTargetInfo(const llvm::Triple &Triple) 3821 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3822 IsAAPCS(true) { 3823 BigEndian = false; 3824 switch (getTriple().getOS()) { 3825 case llvm::Triple::NetBSD: 3826 PtrDiffType = SignedLong; 3827 break; 3828 default: 3829 PtrDiffType = SignedInt; 3830 break; 3831 } 3832 3833 // {} in inline assembly are neon specifiers, not assembly variant 3834 // specifiers. 3835 NoAsmVariants = true; 3836 3837 // FIXME: Should we just treat this as a feature? 3838 IsThumb = getTriple().getArchName().startswith("thumb"); 3839 3840 setABI("aapcs-linux"); 3841 3842 // ARM targets default to using the ARM C++ ABI. 3843 TheCXXABI.set(TargetCXXABI::GenericARM); 3844 3845 // ARM has atomics up to 8 bytes 3846 MaxAtomicPromoteWidth = 64; 3847 if (shouldUseInlineAtomic(getTriple())) 3848 MaxAtomicInlineWidth = 64; 3849 3850 // Do force alignment of members that follow zero length bitfields. If 3851 // the alignment of the zero-length bitfield is greater than the member 3852 // that follows it, `bar', `bar' will be aligned as the type of the 3853 // zero length bitfield. 3854 UseZeroLengthBitfieldAlignment = true; 3855 } 3856 virtual const char *getABI() const { return ABI.c_str(); } 3857 virtual bool setABI(const std::string &Name) { 3858 ABI = Name; 3859 3860 // The defaults (above) are for AAPCS, check if we need to change them. 3861 // 3862 // FIXME: We need support for -meabi... we could just mangle it into the 3863 // name. 3864 if (Name == "apcs-gnu") { 3865 setABIAPCS(); 3866 return true; 3867 } 3868 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3869 setABIAAPCS(); 3870 return true; 3871 } 3872 return false; 3873 } 3874 3875 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3876 if (IsAAPCS) 3877 Features["aapcs"] = true; 3878 else 3879 Features["apcs"] = true; 3880 3881 StringRef ArchName = getTriple().getArchName(); 3882 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3883 Features["vfp2"] = true; 3884 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3885 CPU == "cortex-a9-mp") { 3886 Features["vfp3"] = true; 3887 Features["neon"] = true; 3888 } 3889 else if (CPU == "cortex-a5") { 3890 Features["vfp4"] = true; 3891 Features["neon"] = true; 3892 } else if (CPU == "swift" || CPU == "cortex-a7" || 3893 CPU == "cortex-a12" || CPU == "cortex-a15" || 3894 CPU == "krait") { 3895 Features["vfp4"] = true; 3896 Features["neon"] = true; 3897 Features["hwdiv"] = true; 3898 Features["hwdiv-arm"] = true; 3899 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3900 Features["fp-armv8"] = true; 3901 Features["neon"] = true; 3902 Features["hwdiv"] = true; 3903 Features["hwdiv-arm"] = true; 3904 Features["crc"] = true; 3905 Features["crypto"] = true; 3906 } else if (CPU == "cortex-r5" || 3907 // Enable the hwdiv extension for all v8a AArch32 cores by 3908 // default. 3909 ArchName == "armv8a" || ArchName == "armv8" || 3910 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3911 Features["hwdiv"] = true; 3912 Features["hwdiv-arm"] = true; 3913 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3914 Features["hwdiv"] = true; 3915 } 3916 } 3917 3918 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3919 DiagnosticsEngine &Diags) { 3920 FPU = 0; 3921 CRC = 0; 3922 Crypto = 0; 3923 SoftFloat = SoftFloatABI = false; 3924 HWDiv = 0; 3925 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3926 if (Features[i] == "+soft-float") 3927 SoftFloat = true; 3928 else if (Features[i] == "+soft-float-abi") 3929 SoftFloatABI = true; 3930 else if (Features[i] == "+vfp2") 3931 FPU |= VFP2FPU; 3932 else if (Features[i] == "+vfp3") 3933 FPU |= VFP3FPU; 3934 else if (Features[i] == "+vfp4") 3935 FPU |= VFP4FPU; 3936 else if (Features[i] == "+fp-armv8") 3937 FPU |= FPARMV8; 3938 else if (Features[i] == "+neon") 3939 FPU |= NeonFPU; 3940 else if (Features[i] == "+hwdiv") 3941 HWDiv |= HWDivThumb; 3942 else if (Features[i] == "+hwdiv-arm") 3943 HWDiv |= HWDivARM; 3944 else if (Features[i] == "+crc") 3945 CRC = 1; 3946 else if (Features[i] == "+crypto") 3947 Crypto = 1; 3948 } 3949 3950 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3951 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3952 return false; 3953 } 3954 3955 if (FPMath == FP_Neon) 3956 Features.push_back("+neonfp"); 3957 else if (FPMath == FP_VFP) 3958 Features.push_back("-neonfp"); 3959 3960 // Remove front-end specific options which the backend handles differently. 3961 std::vector<std::string>::iterator it; 3962 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3963 if (it != Features.end()) 3964 Features.erase(it); 3965 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3966 if (it != Features.end()) 3967 Features.erase(it); 3968 return true; 3969 } 3970 3971 virtual bool hasFeature(StringRef Feature) const { 3972 return llvm::StringSwitch<bool>(Feature) 3973 .Case("arm", true) 3974 .Case("softfloat", SoftFloat) 3975 .Case("thumb", IsThumb) 3976 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3977 .Case("hwdiv", HWDiv & HWDivThumb) 3978 .Case("hwdiv-arm", HWDiv & HWDivARM) 3979 .Default(false); 3980 } 3981 // FIXME: Should we actually have some table instead of these switches? 3982 static const char *getCPUDefineSuffix(StringRef Name) { 3983 return llvm::StringSwitch<const char*>(Name) 3984 .Cases("arm8", "arm810", "4") 3985 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3986 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3987 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3988 .Case("ep9312", "4T") 3989 .Cases("arm10tdmi", "arm1020t", "5T") 3990 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3991 .Case("arm926ej-s", "5TEJ") 3992 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3993 .Cases("xscale", "iwmmxt", "5TE") 3994 .Case("arm1136j-s", "6J") 3995 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3996 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3997 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3998 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3999 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 4000 .Cases("cortex-r4", "cortex-r5", "7R") 4001 .Case("swift", "7S") 4002 .Cases("cortex-m3", "cortex-m4", "7M") 4003 .Case("cortex-m0", "6M") 4004 .Cases("cortex-a53", "cortex-a57", "8A") 4005 .Default(0); 4006 } 4007 static const char *getCPUProfile(StringRef Name) { 4008 return llvm::StringSwitch<const char*>(Name) 4009 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4010 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4011 .Cases("cortex-a53", "cortex-a57", "A") 4012 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4013 .Cases("cortex-r4", "cortex-r5", "R") 4014 .Default(""); 4015 } 4016 virtual bool setCPU(const std::string &Name) { 4017 if (!getCPUDefineSuffix(Name)) 4018 return false; 4019 4020 CPU = Name; 4021 return true; 4022 } 4023 virtual bool setFPMath(StringRef Name); 4024 virtual void getTargetDefines(const LangOptions &Opts, 4025 MacroBuilder &Builder) const { 4026 // Target identification. 4027 Builder.defineMacro("__arm"); 4028 Builder.defineMacro("__arm__"); 4029 4030 // Target properties. 4031 Builder.defineMacro("__ARMEL__"); 4032 Builder.defineMacro("__LITTLE_ENDIAN__"); 4033 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4034 4035 StringRef CPUArch = getCPUDefineSuffix(CPU); 4036 unsigned int CPUArchVer; 4037 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4038 llvm_unreachable("Invalid char for architecture version number"); 4039 } 4040 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4041 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4042 StringRef CPUProfile = getCPUProfile(CPU); 4043 if (!CPUProfile.empty()) 4044 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4045 4046 // Subtarget options. 4047 4048 // FIXME: It's more complicated than this and we don't really support 4049 // interworking. 4050 if (5 <= CPUArchVer && CPUArchVer <= 8) 4051 Builder.defineMacro("__THUMB_INTERWORK__"); 4052 4053 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4054 // Embedded targets on Darwin follow AAPCS, but not EABI. 4055 if (!getTriple().isOSDarwin()) 4056 Builder.defineMacro("__ARM_EABI__"); 4057 Builder.defineMacro("__ARM_PCS", "1"); 4058 4059 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4060 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4061 } 4062 4063 if (SoftFloat) 4064 Builder.defineMacro("__SOFTFP__"); 4065 4066 if (CPU == "xscale") 4067 Builder.defineMacro("__XSCALE__"); 4068 4069 if (IsThumb) { 4070 Builder.defineMacro("__THUMBEL__"); 4071 Builder.defineMacro("__thumb__"); 4072 // We check both CPUArchVer and ArchName because when only triple is 4073 // specified, the default CPU is arm1136j-s. 4074 StringRef ArchName = getTriple().getArchName(); 4075 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4076 ArchName.endswith("v7") || ArchName.endswith("v8")) 4077 Builder.defineMacro("__thumb2__"); 4078 } 4079 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4080 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4081 4082 // Note, this is always on in gcc, even though it doesn't make sense. 4083 Builder.defineMacro("__APCS_32__"); 4084 4085 if (FPUModeIsVFP((FPUMode) FPU)) { 4086 Builder.defineMacro("__VFP_FP__"); 4087 if (FPU & VFP2FPU) 4088 Builder.defineMacro("__ARM_VFPV2__"); 4089 if (FPU & VFP3FPU) 4090 Builder.defineMacro("__ARM_VFPV3__"); 4091 if (FPU & VFP4FPU) 4092 Builder.defineMacro("__ARM_VFPV4__"); 4093 } 4094 4095 // This only gets set when Neon instructions are actually available, unlike 4096 // the VFP define, hence the soft float and arch check. This is subtly 4097 // different from gcc, we follow the intent which was that it should be set 4098 // when Neon instructions are actually available. 4099 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4100 Builder.defineMacro("__ARM_NEON"); 4101 Builder.defineMacro("__ARM_NEON__"); 4102 } 4103 4104 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4105 Opts.ShortWChar ? "2" : "4"); 4106 4107 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4108 Opts.ShortEnums ? "1" : "4"); 4109 4110 if (CRC) 4111 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4112 4113 if (Crypto) 4114 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4115 4116 if (CPUArchVer >= 6 && CPUArch != "6M") { 4117 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4118 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4119 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4120 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4121 } 4122 } 4123 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4124 unsigned &NumRecords) const { 4125 Records = BuiltinInfo; 4126 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4127 } 4128 virtual bool isCLZForZeroUndef() const { return false; } 4129 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4130 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4131 } 4132 virtual void getGCCRegNames(const char * const *&Names, 4133 unsigned &NumNames) const; 4134 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4135 unsigned &NumAliases) const; 4136 virtual bool validateAsmConstraint(const char *&Name, 4137 TargetInfo::ConstraintInfo &Info) const { 4138 switch (*Name) { 4139 default: break; 4140 case 'l': // r0-r7 4141 case 'h': // r8-r15 4142 case 'w': // VFP Floating point register single precision 4143 case 'P': // VFP Floating point register double precision 4144 Info.setAllowsRegister(); 4145 return true; 4146 case 'Q': // A memory address that is a single base register. 4147 Info.setAllowsMemory(); 4148 return true; 4149 case 'U': // a memory reference... 4150 switch (Name[1]) { 4151 case 'q': // ...ARMV4 ldrsb 4152 case 'v': // ...VFP load/store (reg+constant offset) 4153 case 'y': // ...iWMMXt load/store 4154 case 't': // address valid for load/store opaque types wider 4155 // than 128-bits 4156 case 'n': // valid address for Neon doubleword vector load/store 4157 case 'm': // valid address for Neon element and structure load/store 4158 case 's': // valid address for non-offset loads/stores of quad-word 4159 // values in four ARM registers 4160 Info.setAllowsMemory(); 4161 Name++; 4162 return true; 4163 } 4164 } 4165 return false; 4166 } 4167 virtual std::string convertConstraint(const char *&Constraint) const { 4168 std::string R; 4169 switch (*Constraint) { 4170 case 'U': // Two-character constraint; add "^" hint for later parsing. 4171 R = std::string("^") + std::string(Constraint, 2); 4172 Constraint++; 4173 break; 4174 case 'p': // 'p' should be translated to 'r' by default. 4175 R = std::string("r"); 4176 break; 4177 default: 4178 return std::string(1, *Constraint); 4179 } 4180 return R; 4181 } 4182 virtual bool validateConstraintModifier(StringRef Constraint, 4183 const char Modifier, 4184 unsigned Size) const { 4185 bool isOutput = (Constraint[0] == '='); 4186 bool isInOut = (Constraint[0] == '+'); 4187 4188 // Strip off constraint modifiers. 4189 while (Constraint[0] == '=' || 4190 Constraint[0] == '+' || 4191 Constraint[0] == '&') 4192 Constraint = Constraint.substr(1); 4193 4194 switch (Constraint[0]) { 4195 default: break; 4196 case 'r': { 4197 switch (Modifier) { 4198 default: 4199 return (isInOut || isOutput || Size <= 64); 4200 case 'q': 4201 // A register of size 32 cannot fit a vector type. 4202 return false; 4203 } 4204 } 4205 } 4206 4207 return true; 4208 } 4209 virtual const char *getClobbers() const { 4210 // FIXME: Is this really right? 4211 return ""; 4212 } 4213 4214 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4215 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4216 } 4217 4218 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4219 if (RegNo == 0) return 0; 4220 if (RegNo == 1) return 1; 4221 return -1; 4222 } 4223 }; 4224 4225 bool ARMTargetInfo::setFPMath(StringRef Name) { 4226 if (Name == "neon") { 4227 FPMath = FP_Neon; 4228 return true; 4229 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4230 Name == "vfp4") { 4231 FPMath = FP_VFP; 4232 return true; 4233 } 4234 return false; 4235 } 4236 4237 const char * const ARMTargetInfo::GCCRegNames[] = { 4238 // Integer registers 4239 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4240 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4241 4242 // Float registers 4243 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4244 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4245 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4246 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4247 4248 // Double registers 4249 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4250 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4251 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4252 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4253 4254 // Quad registers 4255 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4256 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4257 }; 4258 4259 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4260 unsigned &NumNames) const { 4261 Names = GCCRegNames; 4262 NumNames = llvm::array_lengthof(GCCRegNames); 4263 } 4264 4265 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4266 { { "a1" }, "r0" }, 4267 { { "a2" }, "r1" }, 4268 { { "a3" }, "r2" }, 4269 { { "a4" }, "r3" }, 4270 { { "v1" }, "r4" }, 4271 { { "v2" }, "r5" }, 4272 { { "v3" }, "r6" }, 4273 { { "v4" }, "r7" }, 4274 { { "v5" }, "r8" }, 4275 { { "v6", "rfp" }, "r9" }, 4276 { { "sl" }, "r10" }, 4277 { { "fp" }, "r11" }, 4278 { { "ip" }, "r12" }, 4279 { { "r13" }, "sp" }, 4280 { { "r14" }, "lr" }, 4281 { { "r15" }, "pc" }, 4282 // The S, D and Q registers overlap, but aren't really aliases; we 4283 // don't want to substitute one of these for a different-sized one. 4284 }; 4285 4286 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4287 unsigned &NumAliases) const { 4288 Aliases = GCCRegAliases; 4289 NumAliases = llvm::array_lengthof(GCCRegAliases); 4290 } 4291 4292 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4293 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4294 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4295 ALL_LANGUAGES }, 4296 #define GET_NEON_BUILTINS 4297 #include "clang/Basic/arm_neon.inc" 4298 #undef GET_NEON_BUILTINS 4299 4300 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4301 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4302 ALL_LANGUAGES }, 4303 #include "clang/Basic/BuiltinsARM.def" 4304 }; 4305 } // end anonymous namespace. 4306 4307 namespace { 4308 class DarwinARMTargetInfo : 4309 public DarwinTargetInfo<ARMTargetInfo> { 4310 protected: 4311 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4312 MacroBuilder &Builder) const { 4313 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4314 } 4315 4316 public: 4317 DarwinARMTargetInfo(const llvm::Triple &Triple) 4318 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4319 HasAlignMac68kSupport = true; 4320 // iOS always has 64-bit atomic instructions. 4321 // FIXME: This should be based off of the target features in ARMTargetInfo. 4322 MaxAtomicInlineWidth = 64; 4323 4324 // Darwin on iOS uses a variant of the ARM C++ ABI. 4325 TheCXXABI.set(TargetCXXABI::iOS); 4326 } 4327 }; 4328 } // end anonymous namespace. 4329 4330 4331 namespace { 4332 // Hexagon abstract base class 4333 class HexagonTargetInfo : public TargetInfo { 4334 static const Builtin::Info BuiltinInfo[]; 4335 static const char * const GCCRegNames[]; 4336 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4337 std::string CPU; 4338 public: 4339 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4340 BigEndian = false; 4341 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4342 4343 // {} in inline assembly are packet specifiers, not assembly variant 4344 // specifiers. 4345 NoAsmVariants = true; 4346 } 4347 4348 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4349 unsigned &NumRecords) const { 4350 Records = BuiltinInfo; 4351 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4352 } 4353 4354 virtual bool validateAsmConstraint(const char *&Name, 4355 TargetInfo::ConstraintInfo &Info) const { 4356 return true; 4357 } 4358 4359 virtual void getTargetDefines(const LangOptions &Opts, 4360 MacroBuilder &Builder) const; 4361 4362 virtual bool hasFeature(StringRef Feature) const { 4363 return Feature == "hexagon"; 4364 } 4365 4366 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4367 return TargetInfo::CharPtrBuiltinVaList; 4368 } 4369 virtual void getGCCRegNames(const char * const *&Names, 4370 unsigned &NumNames) const; 4371 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4372 unsigned &NumAliases) const; 4373 virtual const char *getClobbers() const { 4374 return ""; 4375 } 4376 4377 static const char *getHexagonCPUSuffix(StringRef Name) { 4378 return llvm::StringSwitch<const char*>(Name) 4379 .Case("hexagonv4", "4") 4380 .Case("hexagonv5", "5") 4381 .Default(0); 4382 } 4383 4384 virtual bool setCPU(const std::string &Name) { 4385 if (!getHexagonCPUSuffix(Name)) 4386 return false; 4387 4388 CPU = Name; 4389 return true; 4390 } 4391 }; 4392 4393 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4394 MacroBuilder &Builder) const { 4395 Builder.defineMacro("qdsp6"); 4396 Builder.defineMacro("__qdsp6", "1"); 4397 Builder.defineMacro("__qdsp6__", "1"); 4398 4399 Builder.defineMacro("hexagon"); 4400 Builder.defineMacro("__hexagon", "1"); 4401 Builder.defineMacro("__hexagon__", "1"); 4402 4403 if(CPU == "hexagonv1") { 4404 Builder.defineMacro("__HEXAGON_V1__"); 4405 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4406 if(Opts.HexagonQdsp6Compat) { 4407 Builder.defineMacro("__QDSP6_V1__"); 4408 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4409 } 4410 } 4411 else if(CPU == "hexagonv2") { 4412 Builder.defineMacro("__HEXAGON_V2__"); 4413 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4414 if(Opts.HexagonQdsp6Compat) { 4415 Builder.defineMacro("__QDSP6_V2__"); 4416 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4417 } 4418 } 4419 else if(CPU == "hexagonv3") { 4420 Builder.defineMacro("__HEXAGON_V3__"); 4421 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4422 if(Opts.HexagonQdsp6Compat) { 4423 Builder.defineMacro("__QDSP6_V3__"); 4424 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4425 } 4426 } 4427 else if(CPU == "hexagonv4") { 4428 Builder.defineMacro("__HEXAGON_V4__"); 4429 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4430 if(Opts.HexagonQdsp6Compat) { 4431 Builder.defineMacro("__QDSP6_V4__"); 4432 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4433 } 4434 } 4435 else if(CPU == "hexagonv5") { 4436 Builder.defineMacro("__HEXAGON_V5__"); 4437 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4438 if(Opts.HexagonQdsp6Compat) { 4439 Builder.defineMacro("__QDSP6_V5__"); 4440 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4441 } 4442 } 4443 } 4444 4445 const char * const HexagonTargetInfo::GCCRegNames[] = { 4446 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4447 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4448 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4449 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4450 "p0", "p1", "p2", "p3", 4451 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4452 }; 4453 4454 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4455 unsigned &NumNames) const { 4456 Names = GCCRegNames; 4457 NumNames = llvm::array_lengthof(GCCRegNames); 4458 } 4459 4460 4461 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4462 { { "sp" }, "r29" }, 4463 { { "fp" }, "r30" }, 4464 { { "lr" }, "r31" }, 4465 }; 4466 4467 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4468 unsigned &NumAliases) const { 4469 Aliases = GCCRegAliases; 4470 NumAliases = llvm::array_lengthof(GCCRegAliases); 4471 } 4472 4473 4474 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4475 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4476 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4477 ALL_LANGUAGES }, 4478 #include "clang/Basic/BuiltinsHexagon.def" 4479 }; 4480 } 4481 4482 4483 namespace { 4484 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4485 class SparcTargetInfo : public TargetInfo { 4486 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4487 static const char * const GCCRegNames[]; 4488 bool SoftFloat; 4489 public: 4490 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4491 4492 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4493 DiagnosticsEngine &Diags) { 4494 SoftFloat = false; 4495 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4496 if (Features[i] == "+soft-float") 4497 SoftFloat = true; 4498 return true; 4499 } 4500 virtual void getTargetDefines(const LangOptions &Opts, 4501 MacroBuilder &Builder) const { 4502 DefineStd(Builder, "sparc", Opts); 4503 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4504 4505 if (SoftFloat) 4506 Builder.defineMacro("SOFT_FLOAT", "1"); 4507 } 4508 4509 virtual bool hasFeature(StringRef Feature) const { 4510 return llvm::StringSwitch<bool>(Feature) 4511 .Case("softfloat", SoftFloat) 4512 .Case("sparc", true) 4513 .Default(false); 4514 } 4515 4516 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4517 unsigned &NumRecords) const { 4518 // FIXME: Implement! 4519 } 4520 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4521 return TargetInfo::VoidPtrBuiltinVaList; 4522 } 4523 virtual void getGCCRegNames(const char * const *&Names, 4524 unsigned &NumNames) const; 4525 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4526 unsigned &NumAliases) const; 4527 virtual bool validateAsmConstraint(const char *&Name, 4528 TargetInfo::ConstraintInfo &info) const { 4529 // FIXME: Implement! 4530 return false; 4531 } 4532 virtual const char *getClobbers() const { 4533 // FIXME: Implement! 4534 return ""; 4535 } 4536 }; 4537 4538 const char * const SparcTargetInfo::GCCRegNames[] = { 4539 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4540 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4541 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4542 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4543 }; 4544 4545 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4546 unsigned &NumNames) const { 4547 Names = GCCRegNames; 4548 NumNames = llvm::array_lengthof(GCCRegNames); 4549 } 4550 4551 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4552 { { "g0" }, "r0" }, 4553 { { "g1" }, "r1" }, 4554 { { "g2" }, "r2" }, 4555 { { "g3" }, "r3" }, 4556 { { "g4" }, "r4" }, 4557 { { "g5" }, "r5" }, 4558 { { "g6" }, "r6" }, 4559 { { "g7" }, "r7" }, 4560 { { "o0" }, "r8" }, 4561 { { "o1" }, "r9" }, 4562 { { "o2" }, "r10" }, 4563 { { "o3" }, "r11" }, 4564 { { "o4" }, "r12" }, 4565 { { "o5" }, "r13" }, 4566 { { "o6", "sp" }, "r14" }, 4567 { { "o7" }, "r15" }, 4568 { { "l0" }, "r16" }, 4569 { { "l1" }, "r17" }, 4570 { { "l2" }, "r18" }, 4571 { { "l3" }, "r19" }, 4572 { { "l4" }, "r20" }, 4573 { { "l5" }, "r21" }, 4574 { { "l6" }, "r22" }, 4575 { { "l7" }, "r23" }, 4576 { { "i0" }, "r24" }, 4577 { { "i1" }, "r25" }, 4578 { { "i2" }, "r26" }, 4579 { { "i3" }, "r27" }, 4580 { { "i4" }, "r28" }, 4581 { { "i5" }, "r29" }, 4582 { { "i6", "fp" }, "r30" }, 4583 { { "i7" }, "r31" }, 4584 }; 4585 4586 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4587 unsigned &NumAliases) const { 4588 Aliases = GCCRegAliases; 4589 NumAliases = llvm::array_lengthof(GCCRegAliases); 4590 } 4591 4592 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4593 class SparcV8TargetInfo : public SparcTargetInfo { 4594 public: 4595 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4596 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4597 } 4598 4599 virtual void getTargetDefines(const LangOptions &Opts, 4600 MacroBuilder &Builder) const { 4601 SparcTargetInfo::getTargetDefines(Opts, Builder); 4602 Builder.defineMacro("__sparcv8"); 4603 } 4604 }; 4605 4606 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4607 class SparcV9TargetInfo : public SparcTargetInfo { 4608 public: 4609 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4610 // FIXME: Support Sparc quad-precision long double? 4611 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4612 // This is an LP64 platform. 4613 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4614 4615 // OpenBSD uses long long for int64_t and intmax_t. 4616 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4617 IntMaxType = SignedLongLong; 4618 UIntMaxType = UnsignedLongLong; 4619 } else { 4620 IntMaxType = SignedLong; 4621 UIntMaxType = UnsignedLong; 4622 } 4623 Int64Type = IntMaxType; 4624 4625 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4626 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4627 LongDoubleWidth = 128; 4628 LongDoubleAlign = 128; 4629 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4630 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4631 } 4632 4633 virtual void getTargetDefines(const LangOptions &Opts, 4634 MacroBuilder &Builder) const { 4635 SparcTargetInfo::getTargetDefines(Opts, Builder); 4636 Builder.defineMacro("__sparcv9"); 4637 Builder.defineMacro("__arch64__"); 4638 // Solaris and its derivative AuroraUX don't need these variants, but the 4639 // BSDs do. 4640 if (getTriple().getOS() != llvm::Triple::Solaris && 4641 getTriple().getOS() != llvm::Triple::AuroraUX) { 4642 Builder.defineMacro("__sparc64__"); 4643 Builder.defineMacro("__sparc_v9__"); 4644 Builder.defineMacro("__sparcv9__"); 4645 } 4646 } 4647 4648 virtual bool setCPU(const std::string &Name) { 4649 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4650 .Case("v9", true) 4651 .Case("ultrasparc", true) 4652 .Case("ultrasparc3", true) 4653 .Case("niagara", true) 4654 .Case("niagara2", true) 4655 .Case("niagara3", true) 4656 .Case("niagara4", true) 4657 .Default(false); 4658 4659 // No need to store the CPU yet. There aren't any CPU-specific 4660 // macros to define. 4661 return CPUKnown; 4662 } 4663 }; 4664 4665 } // end anonymous namespace. 4666 4667 namespace { 4668 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4669 public: 4670 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4671 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4672 SizeType = UnsignedInt; 4673 PtrDiffType = SignedInt; 4674 } 4675 }; 4676 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4677 public: 4678 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4679 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4680 SizeType = UnsignedInt; 4681 PtrDiffType = SignedInt; 4682 } 4683 }; 4684 } // end anonymous namespace. 4685 4686 namespace { 4687 class SystemZTargetInfo : public TargetInfo { 4688 static const char *const GCCRegNames[]; 4689 4690 public: 4691 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4692 TLSSupported = true; 4693 IntWidth = IntAlign = 32; 4694 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4695 PointerWidth = PointerAlign = 64; 4696 LongDoubleWidth = 128; 4697 LongDoubleAlign = 64; 4698 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4699 MinGlobalAlign = 16; 4700 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4701 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4702 } 4703 virtual void getTargetDefines(const LangOptions &Opts, 4704 MacroBuilder &Builder) const { 4705 Builder.defineMacro("__s390__"); 4706 Builder.defineMacro("__s390x__"); 4707 Builder.defineMacro("__zarch__"); 4708 Builder.defineMacro("__LONG_DOUBLE_128__"); 4709 } 4710 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4711 unsigned &NumRecords) const { 4712 // FIXME: Implement. 4713 Records = 0; 4714 NumRecords = 0; 4715 } 4716 4717 virtual void getGCCRegNames(const char *const *&Names, 4718 unsigned &NumNames) const; 4719 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4720 unsigned &NumAliases) const { 4721 // No aliases. 4722 Aliases = 0; 4723 NumAliases = 0; 4724 } 4725 virtual bool validateAsmConstraint(const char *&Name, 4726 TargetInfo::ConstraintInfo &info) const; 4727 virtual const char *getClobbers() const { 4728 // FIXME: Is this really right? 4729 return ""; 4730 } 4731 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4732 return TargetInfo::SystemZBuiltinVaList; 4733 } 4734 virtual bool setCPU(const std::string &Name) { 4735 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4736 .Case("z10", true) 4737 .Case("z196", true) 4738 .Case("zEC12", true) 4739 .Default(false); 4740 4741 // No need to store the CPU yet. There aren't any CPU-specific 4742 // macros to define. 4743 return CPUKnown; 4744 } 4745 }; 4746 4747 const char *const SystemZTargetInfo::GCCRegNames[] = { 4748 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4749 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4750 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4751 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4752 }; 4753 4754 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4755 unsigned &NumNames) const { 4756 Names = GCCRegNames; 4757 NumNames = llvm::array_lengthof(GCCRegNames); 4758 } 4759 4760 bool SystemZTargetInfo:: 4761 validateAsmConstraint(const char *&Name, 4762 TargetInfo::ConstraintInfo &Info) const { 4763 switch (*Name) { 4764 default: 4765 return false; 4766 4767 case 'a': // Address register 4768 case 'd': // Data register (equivalent to 'r') 4769 case 'f': // Floating-point register 4770 Info.setAllowsRegister(); 4771 return true; 4772 4773 case 'I': // Unsigned 8-bit constant 4774 case 'J': // Unsigned 12-bit constant 4775 case 'K': // Signed 16-bit constant 4776 case 'L': // Signed 20-bit displacement (on all targets we support) 4777 case 'M': // 0x7fffffff 4778 return true; 4779 4780 case 'Q': // Memory with base and unsigned 12-bit displacement 4781 case 'R': // Likewise, plus an index 4782 case 'S': // Memory with base and signed 20-bit displacement 4783 case 'T': // Likewise, plus an index 4784 Info.setAllowsMemory(); 4785 return true; 4786 } 4787 } 4788 } 4789 4790 namespace { 4791 class MSP430TargetInfo : public TargetInfo { 4792 static const char * const GCCRegNames[]; 4793 public: 4794 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4795 BigEndian = false; 4796 TLSSupported = false; 4797 IntWidth = 16; IntAlign = 16; 4798 LongWidth = 32; LongLongWidth = 64; 4799 LongAlign = LongLongAlign = 16; 4800 PointerWidth = 16; PointerAlign = 16; 4801 SuitableAlign = 16; 4802 SizeType = UnsignedInt; 4803 IntMaxType = SignedLongLong; 4804 UIntMaxType = UnsignedLongLong; 4805 IntPtrType = SignedInt; 4806 PtrDiffType = SignedInt; 4807 SigAtomicType = SignedLong; 4808 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4809 } 4810 virtual void getTargetDefines(const LangOptions &Opts, 4811 MacroBuilder &Builder) const { 4812 Builder.defineMacro("MSP430"); 4813 Builder.defineMacro("__MSP430__"); 4814 // FIXME: defines for different 'flavours' of MCU 4815 } 4816 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4817 unsigned &NumRecords) const { 4818 // FIXME: Implement. 4819 Records = 0; 4820 NumRecords = 0; 4821 } 4822 virtual bool hasFeature(StringRef Feature) const { 4823 return Feature == "msp430"; 4824 } 4825 virtual void getGCCRegNames(const char * const *&Names, 4826 unsigned &NumNames) const; 4827 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4828 unsigned &NumAliases) const { 4829 // No aliases. 4830 Aliases = 0; 4831 NumAliases = 0; 4832 } 4833 virtual bool validateAsmConstraint(const char *&Name, 4834 TargetInfo::ConstraintInfo &info) const { 4835 // No target constraints for now. 4836 return false; 4837 } 4838 virtual const char *getClobbers() const { 4839 // FIXME: Is this really right? 4840 return ""; 4841 } 4842 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4843 // FIXME: implement 4844 return TargetInfo::CharPtrBuiltinVaList; 4845 } 4846 }; 4847 4848 const char * const MSP430TargetInfo::GCCRegNames[] = { 4849 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4850 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4851 }; 4852 4853 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4854 unsigned &NumNames) const { 4855 Names = GCCRegNames; 4856 NumNames = llvm::array_lengthof(GCCRegNames); 4857 } 4858 } 4859 4860 namespace { 4861 4862 // LLVM and Clang cannot be used directly to output native binaries for 4863 // target, but is used to compile C code to llvm bitcode with correct 4864 // type and alignment information. 4865 // 4866 // TCE uses the llvm bitcode as input and uses it for generating customized 4867 // target processor and program binary. TCE co-design environment is 4868 // publicly available in http://tce.cs.tut.fi 4869 4870 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4871 3, // opencl_global 4872 4, // opencl_local 4873 5, // opencl_constant 4874 0, // cuda_device 4875 0, // cuda_constant 4876 0 // cuda_shared 4877 }; 4878 4879 class TCETargetInfo : public TargetInfo{ 4880 public: 4881 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4882 TLSSupported = false; 4883 IntWidth = 32; 4884 LongWidth = LongLongWidth = 32; 4885 PointerWidth = 32; 4886 IntAlign = 32; 4887 LongAlign = LongLongAlign = 32; 4888 PointerAlign = 32; 4889 SuitableAlign = 32; 4890 SizeType = UnsignedInt; 4891 IntMaxType = SignedLong; 4892 UIntMaxType = UnsignedLong; 4893 IntPtrType = SignedInt; 4894 PtrDiffType = SignedInt; 4895 FloatWidth = 32; 4896 FloatAlign = 32; 4897 DoubleWidth = 32; 4898 DoubleAlign = 32; 4899 LongDoubleWidth = 32; 4900 LongDoubleAlign = 32; 4901 FloatFormat = &llvm::APFloat::IEEEsingle; 4902 DoubleFormat = &llvm::APFloat::IEEEsingle; 4903 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4904 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4905 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4906 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4907 UseAddrSpaceMapMangling = true; 4908 } 4909 4910 virtual void getTargetDefines(const LangOptions &Opts, 4911 MacroBuilder &Builder) const { 4912 DefineStd(Builder, "tce", Opts); 4913 Builder.defineMacro("__TCE__"); 4914 Builder.defineMacro("__TCE_V1__"); 4915 } 4916 virtual bool hasFeature(StringRef Feature) const { 4917 return Feature == "tce"; 4918 } 4919 4920 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4921 unsigned &NumRecords) const {} 4922 virtual const char *getClobbers() const { 4923 return ""; 4924 } 4925 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4926 return TargetInfo::VoidPtrBuiltinVaList; 4927 } 4928 virtual void getGCCRegNames(const char * const *&Names, 4929 unsigned &NumNames) const {} 4930 virtual bool validateAsmConstraint(const char *&Name, 4931 TargetInfo::ConstraintInfo &info) const { 4932 return true; 4933 } 4934 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4935 unsigned &NumAliases) const {} 4936 }; 4937 } 4938 4939 namespace { 4940 class MipsTargetInfoBase : public TargetInfo { 4941 virtual void setDescriptionString() = 0; 4942 4943 static const Builtin::Info BuiltinInfo[]; 4944 std::string CPU; 4945 bool IsMips16; 4946 bool IsMicromips; 4947 bool IsNan2008; 4948 bool IsSingleFloat; 4949 enum MipsFloatABI { 4950 HardFloat, SoftFloat 4951 } FloatABI; 4952 enum DspRevEnum { 4953 NoDSP, DSP1, DSP2 4954 } DspRev; 4955 bool HasMSA; 4956 4957 protected: 4958 bool HasFP64; 4959 std::string ABI; 4960 4961 public: 4962 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4963 const std::string &CPUStr) 4964 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4965 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4966 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4967 4968 virtual const char *getABI() const { return ABI.c_str(); } 4969 virtual bool setABI(const std::string &Name) = 0; 4970 virtual bool setCPU(const std::string &Name) { 4971 CPU = Name; 4972 return true; 4973 } 4974 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4975 // The backend enables certain ABI's by default according to the 4976 // architecture. 4977 // Disable both possible defaults so that we don't end up with multiple 4978 // ABI's selected and trigger an assertion. 4979 Features["o32"] = false; 4980 Features["n64"] = false; 4981 4982 Features[ABI] = true; 4983 Features[CPU] = true; 4984 } 4985 4986 virtual void getTargetDefines(const LangOptions &Opts, 4987 MacroBuilder &Builder) const { 4988 Builder.defineMacro("__mips__"); 4989 Builder.defineMacro("_mips"); 4990 if (Opts.GNUMode) 4991 Builder.defineMacro("mips"); 4992 4993 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4994 4995 switch (FloatABI) { 4996 case HardFloat: 4997 Builder.defineMacro("__mips_hard_float", Twine(1)); 4998 break; 4999 case SoftFloat: 5000 Builder.defineMacro("__mips_soft_float", Twine(1)); 5001 break; 5002 } 5003 5004 if (IsSingleFloat) 5005 Builder.defineMacro("__mips_single_float", Twine(1)); 5006 5007 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5008 Builder.defineMacro("_MIPS_FPSET", 5009 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5010 5011 if (IsMips16) 5012 Builder.defineMacro("__mips16", Twine(1)); 5013 5014 if (IsMicromips) 5015 Builder.defineMacro("__mips_micromips", Twine(1)); 5016 5017 if (IsNan2008) 5018 Builder.defineMacro("__mips_nan2008", Twine(1)); 5019 5020 switch (DspRev) { 5021 default: 5022 break; 5023 case DSP1: 5024 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5025 Builder.defineMacro("__mips_dsp", Twine(1)); 5026 break; 5027 case DSP2: 5028 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5029 Builder.defineMacro("__mips_dspr2", Twine(1)); 5030 Builder.defineMacro("__mips_dsp", Twine(1)); 5031 break; 5032 } 5033 5034 if (HasMSA) 5035 Builder.defineMacro("__mips_msa", Twine(1)); 5036 5037 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5038 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5039 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5040 5041 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5042 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5043 } 5044 5045 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5046 unsigned &NumRecords) const { 5047 Records = BuiltinInfo; 5048 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5049 } 5050 virtual bool hasFeature(StringRef Feature) const { 5051 return llvm::StringSwitch<bool>(Feature) 5052 .Case("mips", true) 5053 .Case("fp64", HasFP64) 5054 .Default(false); 5055 } 5056 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5057 return TargetInfo::VoidPtrBuiltinVaList; 5058 } 5059 virtual void getGCCRegNames(const char * const *&Names, 5060 unsigned &NumNames) const { 5061 static const char *const GCCRegNames[] = { 5062 // CPU register names 5063 // Must match second column of GCCRegAliases 5064 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5065 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5066 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5067 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5068 // Floating point register names 5069 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5070 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5071 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5072 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5073 // Hi/lo and condition register names 5074 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5075 "$fcc5","$fcc6","$fcc7", 5076 // MSA register names 5077 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5078 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5079 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5080 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5081 // MSA control register names 5082 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5083 "$msarequest", "$msamap", "$msaunmap" 5084 }; 5085 Names = GCCRegNames; 5086 NumNames = llvm::array_lengthof(GCCRegNames); 5087 } 5088 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5089 unsigned &NumAliases) const = 0; 5090 virtual bool validateAsmConstraint(const char *&Name, 5091 TargetInfo::ConstraintInfo &Info) const { 5092 switch (*Name) { 5093 default: 5094 return false; 5095 5096 case 'r': // CPU registers. 5097 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5098 case 'y': // Equivalent to "r", backwards compatibility only. 5099 case 'f': // floating-point registers. 5100 case 'c': // $25 for indirect jumps 5101 case 'l': // lo register 5102 case 'x': // hilo register pair 5103 Info.setAllowsRegister(); 5104 return true; 5105 case 'R': // An address that can be used in a non-macro load or store 5106 Info.setAllowsMemory(); 5107 return true; 5108 } 5109 } 5110 5111 virtual const char *getClobbers() const { 5112 // FIXME: Implement! 5113 return ""; 5114 } 5115 5116 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 5117 DiagnosticsEngine &Diags) { 5118 IsMips16 = false; 5119 IsMicromips = false; 5120 IsNan2008 = false; 5121 IsSingleFloat = false; 5122 FloatABI = HardFloat; 5123 DspRev = NoDSP; 5124 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5125 5126 for (std::vector<std::string>::iterator it = Features.begin(), 5127 ie = Features.end(); it != ie; ++it) { 5128 if (*it == "+single-float") 5129 IsSingleFloat = true; 5130 else if (*it == "+soft-float") 5131 FloatABI = SoftFloat; 5132 else if (*it == "+mips16") 5133 IsMips16 = true; 5134 else if (*it == "+micromips") 5135 IsMicromips = true; 5136 else if (*it == "+dsp") 5137 DspRev = std::max(DspRev, DSP1); 5138 else if (*it == "+dspr2") 5139 DspRev = std::max(DspRev, DSP2); 5140 else if (*it == "+msa") 5141 HasMSA = true; 5142 else if (*it == "+fp64") 5143 HasFP64 = true; 5144 else if (*it == "-fp64") 5145 HasFP64 = false; 5146 else if (*it == "+nan2008") 5147 IsNan2008 = true; 5148 } 5149 5150 // Remove front-end specific options. 5151 std::vector<std::string>::iterator it = 5152 std::find(Features.begin(), Features.end(), "+soft-float"); 5153 if (it != Features.end()) 5154 Features.erase(it); 5155 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5156 if (it != Features.end()) 5157 Features.erase(it); 5158 5159 setDescriptionString(); 5160 5161 return true; 5162 } 5163 5164 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5165 if (RegNo == 0) return 4; 5166 if (RegNo == 1) return 5; 5167 return -1; 5168 } 5169 }; 5170 5171 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5172 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5173 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5174 ALL_LANGUAGES }, 5175 #include "clang/Basic/BuiltinsMips.def" 5176 }; 5177 5178 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5179 public: 5180 Mips32TargetInfoBase(const llvm::Triple &Triple) 5181 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5182 SizeType = UnsignedInt; 5183 PtrDiffType = SignedInt; 5184 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5185 } 5186 virtual bool setABI(const std::string &Name) { 5187 if ((Name == "o32") || (Name == "eabi")) { 5188 ABI = Name; 5189 return true; 5190 } else if (Name == "32") { 5191 ABI = "o32"; 5192 return true; 5193 } else 5194 return false; 5195 } 5196 virtual void getTargetDefines(const LangOptions &Opts, 5197 MacroBuilder &Builder) const { 5198 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5199 5200 Builder.defineMacro("__mips", "32"); 5201 5202 if (ABI == "o32") { 5203 Builder.defineMacro("__mips_o32"); 5204 Builder.defineMacro("_ABIO32", "1"); 5205 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5206 } 5207 else if (ABI == "eabi") 5208 Builder.defineMacro("__mips_eabi"); 5209 else 5210 llvm_unreachable("Invalid ABI for Mips32."); 5211 } 5212 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5213 unsigned &NumAliases) const { 5214 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5215 { { "at" }, "$1" }, 5216 { { "v0" }, "$2" }, 5217 { { "v1" }, "$3" }, 5218 { { "a0" }, "$4" }, 5219 { { "a1" }, "$5" }, 5220 { { "a2" }, "$6" }, 5221 { { "a3" }, "$7" }, 5222 { { "t0" }, "$8" }, 5223 { { "t1" }, "$9" }, 5224 { { "t2" }, "$10" }, 5225 { { "t3" }, "$11" }, 5226 { { "t4" }, "$12" }, 5227 { { "t5" }, "$13" }, 5228 { { "t6" }, "$14" }, 5229 { { "t7" }, "$15" }, 5230 { { "s0" }, "$16" }, 5231 { { "s1" }, "$17" }, 5232 { { "s2" }, "$18" }, 5233 { { "s3" }, "$19" }, 5234 { { "s4" }, "$20" }, 5235 { { "s5" }, "$21" }, 5236 { { "s6" }, "$22" }, 5237 { { "s7" }, "$23" }, 5238 { { "t8" }, "$24" }, 5239 { { "t9" }, "$25" }, 5240 { { "k0" }, "$26" }, 5241 { { "k1" }, "$27" }, 5242 { { "gp" }, "$28" }, 5243 { { "sp","$sp" }, "$29" }, 5244 { { "fp","$fp" }, "$30" }, 5245 { { "ra" }, "$31" } 5246 }; 5247 Aliases = GCCRegAliases; 5248 NumAliases = llvm::array_lengthof(GCCRegAliases); 5249 } 5250 }; 5251 5252 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5253 virtual void setDescriptionString() { 5254 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5255 } 5256 5257 public: 5258 Mips32EBTargetInfo(const llvm::Triple &Triple) 5259 : Mips32TargetInfoBase(Triple) { 5260 } 5261 virtual void getTargetDefines(const LangOptions &Opts, 5262 MacroBuilder &Builder) const { 5263 DefineStd(Builder, "MIPSEB", Opts); 5264 Builder.defineMacro("_MIPSEB"); 5265 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5266 } 5267 }; 5268 5269 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5270 virtual void setDescriptionString() { 5271 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5272 } 5273 5274 public: 5275 Mips32ELTargetInfo(const llvm::Triple &Triple) 5276 : Mips32TargetInfoBase(Triple) { 5277 BigEndian = false; 5278 } 5279 virtual void getTargetDefines(const LangOptions &Opts, 5280 MacroBuilder &Builder) const { 5281 DefineStd(Builder, "MIPSEL", Opts); 5282 Builder.defineMacro("_MIPSEL"); 5283 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5284 } 5285 }; 5286 5287 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5288 public: 5289 Mips64TargetInfoBase(const llvm::Triple &Triple) 5290 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5291 LongWidth = LongAlign = 64; 5292 PointerWidth = PointerAlign = 64; 5293 LongDoubleWidth = LongDoubleAlign = 128; 5294 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5295 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5296 LongDoubleWidth = LongDoubleAlign = 64; 5297 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5298 } 5299 SuitableAlign = 128; 5300 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5301 } 5302 virtual bool setABI(const std::string &Name) { 5303 if (Name == "n32") { 5304 LongWidth = LongAlign = 32; 5305 PointerWidth = PointerAlign = 32; 5306 ABI = Name; 5307 return true; 5308 } else if (Name == "n64") { 5309 ABI = Name; 5310 return true; 5311 } else if (Name == "64") { 5312 ABI = "n64"; 5313 return true; 5314 } else 5315 return false; 5316 } 5317 virtual void getTargetDefines(const LangOptions &Opts, 5318 MacroBuilder &Builder) const { 5319 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5320 5321 Builder.defineMacro("__mips", "64"); 5322 Builder.defineMacro("__mips64"); 5323 Builder.defineMacro("__mips64__"); 5324 5325 if (ABI == "n32") { 5326 Builder.defineMacro("__mips_n32"); 5327 Builder.defineMacro("_ABIN32", "2"); 5328 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5329 } 5330 else if (ABI == "n64") { 5331 Builder.defineMacro("__mips_n64"); 5332 Builder.defineMacro("_ABI64", "3"); 5333 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5334 } 5335 else 5336 llvm_unreachable("Invalid ABI for Mips64."); 5337 } 5338 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5339 unsigned &NumAliases) const { 5340 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5341 { { "at" }, "$1" }, 5342 { { "v0" }, "$2" }, 5343 { { "v1" }, "$3" }, 5344 { { "a0" }, "$4" }, 5345 { { "a1" }, "$5" }, 5346 { { "a2" }, "$6" }, 5347 { { "a3" }, "$7" }, 5348 { { "a4" }, "$8" }, 5349 { { "a5" }, "$9" }, 5350 { { "a6" }, "$10" }, 5351 { { "a7" }, "$11" }, 5352 { { "t0" }, "$12" }, 5353 { { "t1" }, "$13" }, 5354 { { "t2" }, "$14" }, 5355 { { "t3" }, "$15" }, 5356 { { "s0" }, "$16" }, 5357 { { "s1" }, "$17" }, 5358 { { "s2" }, "$18" }, 5359 { { "s3" }, "$19" }, 5360 { { "s4" }, "$20" }, 5361 { { "s5" }, "$21" }, 5362 { { "s6" }, "$22" }, 5363 { { "s7" }, "$23" }, 5364 { { "t8" }, "$24" }, 5365 { { "t9" }, "$25" }, 5366 { { "k0" }, "$26" }, 5367 { { "k1" }, "$27" }, 5368 { { "gp" }, "$28" }, 5369 { { "sp","$sp" }, "$29" }, 5370 { { "fp","$fp" }, "$30" }, 5371 { { "ra" }, "$31" } 5372 }; 5373 Aliases = GCCRegAliases; 5374 NumAliases = llvm::array_lengthof(GCCRegAliases); 5375 } 5376 }; 5377 5378 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5379 virtual void setDescriptionString() { 5380 if (ABI == "n32") 5381 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5382 else 5383 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5384 5385 } 5386 5387 public: 5388 Mips64EBTargetInfo(const llvm::Triple &Triple) 5389 : Mips64TargetInfoBase(Triple) {} 5390 virtual void getTargetDefines(const LangOptions &Opts, 5391 MacroBuilder &Builder) const { 5392 DefineStd(Builder, "MIPSEB", Opts); 5393 Builder.defineMacro("_MIPSEB"); 5394 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5395 } 5396 }; 5397 5398 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5399 virtual void setDescriptionString() { 5400 if (ABI == "n32") 5401 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5402 else 5403 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5404 } 5405 public: 5406 Mips64ELTargetInfo(const llvm::Triple &Triple) 5407 : Mips64TargetInfoBase(Triple) { 5408 // Default ABI is n64. 5409 BigEndian = false; 5410 } 5411 virtual void getTargetDefines(const LangOptions &Opts, 5412 MacroBuilder &Builder) const { 5413 DefineStd(Builder, "MIPSEL", Opts); 5414 Builder.defineMacro("_MIPSEL"); 5415 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5416 } 5417 }; 5418 } // end anonymous namespace. 5419 5420 namespace { 5421 class PNaClTargetInfo : public TargetInfo { 5422 public: 5423 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5424 BigEndian = false; 5425 this->UserLabelPrefix = ""; 5426 this->LongAlign = 32; 5427 this->LongWidth = 32; 5428 this->PointerAlign = 32; 5429 this->PointerWidth = 32; 5430 this->IntMaxType = TargetInfo::SignedLongLong; 5431 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5432 this->Int64Type = TargetInfo::SignedLongLong; 5433 this->DoubleAlign = 64; 5434 this->LongDoubleWidth = 64; 5435 this->LongDoubleAlign = 64; 5436 this->SizeType = TargetInfo::UnsignedInt; 5437 this->PtrDiffType = TargetInfo::SignedInt; 5438 this->IntPtrType = TargetInfo::SignedInt; 5439 this->RegParmMax = 0; // Disallow regparm 5440 } 5441 5442 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5443 } 5444 virtual void getArchDefines(const LangOptions &Opts, 5445 MacroBuilder &Builder) const { 5446 Builder.defineMacro("__le32__"); 5447 Builder.defineMacro("__pnacl__"); 5448 } 5449 virtual void getTargetDefines(const LangOptions &Opts, 5450 MacroBuilder &Builder) const { 5451 Builder.defineMacro("__LITTLE_ENDIAN__"); 5452 getArchDefines(Opts, Builder); 5453 } 5454 virtual bool hasFeature(StringRef Feature) const { 5455 return Feature == "pnacl"; 5456 } 5457 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5458 unsigned &NumRecords) const { 5459 } 5460 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5461 return TargetInfo::PNaClABIBuiltinVaList; 5462 } 5463 virtual void getGCCRegNames(const char * const *&Names, 5464 unsigned &NumNames) const; 5465 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5466 unsigned &NumAliases) const; 5467 virtual bool validateAsmConstraint(const char *&Name, 5468 TargetInfo::ConstraintInfo &Info) const { 5469 return false; 5470 } 5471 5472 virtual const char *getClobbers() const { 5473 return ""; 5474 } 5475 }; 5476 5477 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5478 unsigned &NumNames) const { 5479 Names = NULL; 5480 NumNames = 0; 5481 } 5482 5483 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5484 unsigned &NumAliases) const { 5485 Aliases = NULL; 5486 NumAliases = 0; 5487 } 5488 } // end anonymous namespace. 5489 5490 namespace { 5491 static const unsigned SPIRAddrSpaceMap[] = { 5492 1, // opencl_global 5493 3, // opencl_local 5494 2, // opencl_constant 5495 0, // cuda_device 5496 0, // cuda_constant 5497 0 // cuda_shared 5498 }; 5499 class SPIRTargetInfo : public TargetInfo { 5500 public: 5501 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5502 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5503 "SPIR target must use unknown OS"); 5504 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5505 "SPIR target must use unknown environment type"); 5506 BigEndian = false; 5507 TLSSupported = false; 5508 LongWidth = LongAlign = 64; 5509 AddrSpaceMap = &SPIRAddrSpaceMap; 5510 UseAddrSpaceMapMangling = true; 5511 // Define available target features 5512 // These must be defined in sorted order! 5513 NoAsmVariants = true; 5514 } 5515 virtual void getTargetDefines(const LangOptions &Opts, 5516 MacroBuilder &Builder) const { 5517 DefineStd(Builder, "SPIR", Opts); 5518 } 5519 virtual bool hasFeature(StringRef Feature) const { 5520 return Feature == "spir"; 5521 } 5522 5523 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5524 unsigned &NumRecords) const {} 5525 virtual const char *getClobbers() const { 5526 return ""; 5527 } 5528 virtual void getGCCRegNames(const char * const *&Names, 5529 unsigned &NumNames) const {} 5530 virtual bool validateAsmConstraint(const char *&Name, 5531 TargetInfo::ConstraintInfo &info) const { 5532 return true; 5533 } 5534 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5535 unsigned &NumAliases) const {} 5536 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5537 return TargetInfo::VoidPtrBuiltinVaList; 5538 } 5539 }; 5540 5541 5542 class SPIR32TargetInfo : public SPIRTargetInfo { 5543 public: 5544 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5545 PointerWidth = PointerAlign = 32; 5546 SizeType = TargetInfo::UnsignedInt; 5547 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5548 DescriptionString 5549 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5550 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5551 } 5552 virtual void getTargetDefines(const LangOptions &Opts, 5553 MacroBuilder &Builder) const { 5554 DefineStd(Builder, "SPIR32", Opts); 5555 } 5556 }; 5557 5558 class SPIR64TargetInfo : public SPIRTargetInfo { 5559 public: 5560 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5561 PointerWidth = PointerAlign = 64; 5562 SizeType = TargetInfo::UnsignedLong; 5563 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5564 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5565 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5566 } 5567 virtual void getTargetDefines(const LangOptions &Opts, 5568 MacroBuilder &Builder) const { 5569 DefineStd(Builder, "SPIR64", Opts); 5570 } 5571 }; 5572 } 5573 5574 namespace { 5575 class XCoreTargetInfo : public TargetInfo { 5576 static const Builtin::Info BuiltinInfo[]; 5577 public: 5578 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5579 BigEndian = false; 5580 NoAsmVariants = true; 5581 LongLongAlign = 32; 5582 SuitableAlign = 32; 5583 DoubleAlign = LongDoubleAlign = 32; 5584 SizeType = UnsignedInt; 5585 PtrDiffType = SignedInt; 5586 IntPtrType = SignedInt; 5587 WCharType = UnsignedChar; 5588 WIntType = UnsignedInt; 5589 UseZeroLengthBitfieldAlignment = true; 5590 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5591 "-f64:32-a:0:32-n32"; 5592 } 5593 virtual void getTargetDefines(const LangOptions &Opts, 5594 MacroBuilder &Builder) const { 5595 Builder.defineMacro("__XS1B__"); 5596 } 5597 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5598 unsigned &NumRecords) const { 5599 Records = BuiltinInfo; 5600 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5601 } 5602 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5603 return TargetInfo::VoidPtrBuiltinVaList; 5604 } 5605 virtual const char *getClobbers() const { 5606 return ""; 5607 } 5608 virtual void getGCCRegNames(const char * const *&Names, 5609 unsigned &NumNames) const { 5610 static const char * const GCCRegNames[] = { 5611 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5612 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5613 }; 5614 Names = GCCRegNames; 5615 NumNames = llvm::array_lengthof(GCCRegNames); 5616 } 5617 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5618 unsigned &NumAliases) const { 5619 Aliases = NULL; 5620 NumAliases = 0; 5621 } 5622 virtual bool validateAsmConstraint(const char *&Name, 5623 TargetInfo::ConstraintInfo &Info) const { 5624 return false; 5625 } 5626 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5627 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5628 return (RegNo < 2)? RegNo : -1; 5629 } 5630 }; 5631 5632 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5633 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5634 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5635 ALL_LANGUAGES }, 5636 #include "clang/Basic/BuiltinsXCore.def" 5637 }; 5638 } // end anonymous namespace. 5639 5640 5641 //===----------------------------------------------------------------------===// 5642 // Driver code 5643 //===----------------------------------------------------------------------===// 5644 5645 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5646 llvm::Triple::OSType os = Triple.getOS(); 5647 5648 switch (Triple.getArch()) { 5649 default: 5650 return NULL; 5651 5652 case llvm::Triple::xcore: 5653 return new XCoreTargetInfo(Triple); 5654 5655 case llvm::Triple::hexagon: 5656 return new HexagonTargetInfo(Triple); 5657 5658 case llvm::Triple::aarch64: 5659 switch (os) { 5660 case llvm::Triple::Linux: 5661 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 5662 case llvm::Triple::NetBSD: 5663 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 5664 default: 5665 return new AArch64leTargetInfo(Triple); 5666 } 5667 5668 case llvm::Triple::aarch64_be: 5669 switch (os) { 5670 case llvm::Triple::Linux: 5671 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 5672 case llvm::Triple::NetBSD: 5673 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 5674 default: 5675 return new AArch64beTargetInfo(Triple); 5676 } 5677 5678 case llvm::Triple::arm: 5679 case llvm::Triple::thumb: 5680 if (Triple.isOSBinFormatMachO()) 5681 return new DarwinARMTargetInfo(Triple); 5682 5683 switch (os) { 5684 case llvm::Triple::Linux: 5685 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5686 case llvm::Triple::FreeBSD: 5687 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5688 case llvm::Triple::NetBSD: 5689 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5690 case llvm::Triple::OpenBSD: 5691 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5692 case llvm::Triple::Bitrig: 5693 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5694 case llvm::Triple::RTEMS: 5695 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5696 case llvm::Triple::NaCl: 5697 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5698 default: 5699 return new ARMTargetInfo(Triple); 5700 } 5701 5702 case llvm::Triple::msp430: 5703 return new MSP430TargetInfo(Triple); 5704 5705 case llvm::Triple::mips: 5706 switch (os) { 5707 case llvm::Triple::Linux: 5708 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5709 case llvm::Triple::RTEMS: 5710 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5711 case llvm::Triple::FreeBSD: 5712 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5713 case llvm::Triple::NetBSD: 5714 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5715 default: 5716 return new Mips32EBTargetInfo(Triple); 5717 } 5718 5719 case llvm::Triple::mipsel: 5720 switch (os) { 5721 case llvm::Triple::Linux: 5722 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5723 case llvm::Triple::RTEMS: 5724 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5725 case llvm::Triple::FreeBSD: 5726 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5727 case llvm::Triple::NetBSD: 5728 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5729 case llvm::Triple::NaCl: 5730 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5731 default: 5732 return new Mips32ELTargetInfo(Triple); 5733 } 5734 5735 case llvm::Triple::mips64: 5736 switch (os) { 5737 case llvm::Triple::Linux: 5738 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5739 case llvm::Triple::RTEMS: 5740 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5741 case llvm::Triple::FreeBSD: 5742 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5743 case llvm::Triple::NetBSD: 5744 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5745 case llvm::Triple::OpenBSD: 5746 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5747 default: 5748 return new Mips64EBTargetInfo(Triple); 5749 } 5750 5751 case llvm::Triple::mips64el: 5752 switch (os) { 5753 case llvm::Triple::Linux: 5754 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5755 case llvm::Triple::RTEMS: 5756 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5757 case llvm::Triple::FreeBSD: 5758 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5759 case llvm::Triple::NetBSD: 5760 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5761 case llvm::Triple::OpenBSD: 5762 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5763 default: 5764 return new Mips64ELTargetInfo(Triple); 5765 } 5766 5767 case llvm::Triple::le32: 5768 switch (os) { 5769 case llvm::Triple::NaCl: 5770 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5771 default: 5772 return NULL; 5773 } 5774 5775 case llvm::Triple::ppc: 5776 if (Triple.isOSDarwin()) 5777 return new DarwinPPC32TargetInfo(Triple); 5778 switch (os) { 5779 case llvm::Triple::Linux: 5780 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5781 case llvm::Triple::FreeBSD: 5782 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5783 case llvm::Triple::NetBSD: 5784 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5785 case llvm::Triple::OpenBSD: 5786 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5787 case llvm::Triple::RTEMS: 5788 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5789 default: 5790 return new PPC32TargetInfo(Triple); 5791 } 5792 5793 case llvm::Triple::ppc64: 5794 if (Triple.isOSDarwin()) 5795 return new DarwinPPC64TargetInfo(Triple); 5796 switch (os) { 5797 case llvm::Triple::Linux: 5798 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5799 case llvm::Triple::Lv2: 5800 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5801 case llvm::Triple::FreeBSD: 5802 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5803 case llvm::Triple::NetBSD: 5804 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5805 default: 5806 return new PPC64TargetInfo(Triple); 5807 } 5808 5809 case llvm::Triple::ppc64le: 5810 switch (os) { 5811 case llvm::Triple::Linux: 5812 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5813 default: 5814 return new PPC64TargetInfo(Triple); 5815 } 5816 5817 case llvm::Triple::nvptx: 5818 return new NVPTX32TargetInfo(Triple); 5819 case llvm::Triple::nvptx64: 5820 return new NVPTX64TargetInfo(Triple); 5821 5822 case llvm::Triple::r600: 5823 return new R600TargetInfo(Triple); 5824 5825 case llvm::Triple::sparc: 5826 switch (os) { 5827 case llvm::Triple::Linux: 5828 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5829 case llvm::Triple::AuroraUX: 5830 return new AuroraUXSparcV8TargetInfo(Triple); 5831 case llvm::Triple::Solaris: 5832 return new SolarisSparcV8TargetInfo(Triple); 5833 case llvm::Triple::NetBSD: 5834 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5835 case llvm::Triple::OpenBSD: 5836 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5837 case llvm::Triple::RTEMS: 5838 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5839 default: 5840 return new SparcV8TargetInfo(Triple); 5841 } 5842 5843 case llvm::Triple::sparcv9: 5844 switch (os) { 5845 case llvm::Triple::Linux: 5846 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5847 case llvm::Triple::AuroraUX: 5848 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5849 case llvm::Triple::Solaris: 5850 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5851 case llvm::Triple::NetBSD: 5852 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5853 case llvm::Triple::OpenBSD: 5854 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5855 case llvm::Triple::FreeBSD: 5856 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5857 default: 5858 return new SparcV9TargetInfo(Triple); 5859 } 5860 5861 case llvm::Triple::systemz: 5862 switch (os) { 5863 case llvm::Triple::Linux: 5864 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5865 default: 5866 return new SystemZTargetInfo(Triple); 5867 } 5868 5869 case llvm::Triple::tce: 5870 return new TCETargetInfo(Triple); 5871 5872 case llvm::Triple::x86: 5873 if (Triple.isOSDarwin()) 5874 return new DarwinI386TargetInfo(Triple); 5875 5876 switch (os) { 5877 case llvm::Triple::AuroraUX: 5878 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5879 case llvm::Triple::Linux: 5880 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5881 case llvm::Triple::DragonFly: 5882 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5883 case llvm::Triple::NetBSD: 5884 return new NetBSDI386TargetInfo(Triple); 5885 case llvm::Triple::OpenBSD: 5886 return new OpenBSDI386TargetInfo(Triple); 5887 case llvm::Triple::Bitrig: 5888 return new BitrigI386TargetInfo(Triple); 5889 case llvm::Triple::FreeBSD: 5890 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5891 case llvm::Triple::KFreeBSD: 5892 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5893 case llvm::Triple::Minix: 5894 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5895 case llvm::Triple::Solaris: 5896 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5897 case llvm::Triple::Cygwin: 5898 return new CygwinX86_32TargetInfo(Triple); 5899 case llvm::Triple::MinGW32: 5900 return new MinGWX86_32TargetInfo(Triple); 5901 case llvm::Triple::Win32: 5902 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5903 case llvm::Triple::Haiku: 5904 return new HaikuX86_32TargetInfo(Triple); 5905 case llvm::Triple::RTEMS: 5906 return new RTEMSX86_32TargetInfo(Triple); 5907 case llvm::Triple::NaCl: 5908 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5909 default: 5910 return new X86_32TargetInfo(Triple); 5911 } 5912 5913 case llvm::Triple::x86_64: 5914 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5915 return new DarwinX86_64TargetInfo(Triple); 5916 5917 switch (os) { 5918 case llvm::Triple::AuroraUX: 5919 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5920 case llvm::Triple::Linux: 5921 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5922 case llvm::Triple::DragonFly: 5923 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5924 case llvm::Triple::NetBSD: 5925 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5926 case llvm::Triple::OpenBSD: 5927 return new OpenBSDX86_64TargetInfo(Triple); 5928 case llvm::Triple::Bitrig: 5929 return new BitrigX86_64TargetInfo(Triple); 5930 case llvm::Triple::FreeBSD: 5931 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5932 case llvm::Triple::KFreeBSD: 5933 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5934 case llvm::Triple::Solaris: 5935 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5936 case llvm::Triple::MinGW32: 5937 return new MinGWX86_64TargetInfo(Triple); 5938 case llvm::Triple::Win32: // This is what Triple.h supports now. 5939 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5940 case llvm::Triple::NaCl: 5941 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5942 default: 5943 return new X86_64TargetInfo(Triple); 5944 } 5945 5946 case llvm::Triple::spir: { 5947 if (Triple.getOS() != llvm::Triple::UnknownOS || 5948 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5949 return NULL; 5950 return new SPIR32TargetInfo(Triple); 5951 } 5952 case llvm::Triple::spir64: { 5953 if (Triple.getOS() != llvm::Triple::UnknownOS || 5954 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5955 return NULL; 5956 return new SPIR64TargetInfo(Triple); 5957 } 5958 } 5959 } 5960 5961 /// CreateTargetInfo - Return the target info object for the specified target 5962 /// triple. 5963 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5964 TargetOptions *Opts) { 5965 llvm::Triple Triple(Opts->Triple); 5966 5967 // Construct the target 5968 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5969 if (!Target) { 5970 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5971 return 0; 5972 } 5973 Target->setTargetOpts(Opts); 5974 5975 // Set the target CPU if specified. 5976 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5977 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5978 return 0; 5979 } 5980 5981 // Set the target ABI if specified. 5982 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5983 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5984 return 0; 5985 } 5986 5987 // Set the fp math unit. 5988 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5989 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5990 return 0; 5991 } 5992 5993 // Compute the default target features, we need the target to handle this 5994 // because features may have dependencies on one another. 5995 llvm::StringMap<bool> Features; 5996 Target->getDefaultFeatures(Features); 5997 5998 // Apply the user specified deltas. 5999 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6000 I < N; ++I) { 6001 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6002 // Apply the feature via the target. 6003 bool Enabled = Name[0] == '+'; 6004 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6005 } 6006 6007 // Add the features to the compile options. 6008 // 6009 // FIXME: If we are completely confident that we have the right set, we only 6010 // need to pass the minuses. 6011 Opts->Features.clear(); 6012 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6013 ie = Features.end(); it != ie; ++it) 6014 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6015 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6016 return 0; 6017 6018 return Target.take(); 6019 } 6020