1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 virtual std::string isValidSectionSpecifier(StringRef SR) const { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 virtual const char *getStaticInitSectionSpecifier() const { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 virtual bool hasProtectedVisibility() const { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 virtual const char *getStaticInitSectionSpecifier() const { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 486 } 487 }; 488 489 // AuroraUX target 490 template<typename Target> 491 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const { 495 DefineStd(Builder, "sun", Opts); 496 DefineStd(Builder, "unix", Opts); 497 Builder.defineMacro("__ELF__"); 498 Builder.defineMacro("__svr4__"); 499 Builder.defineMacro("__SVR4"); 500 } 501 public: 502 AuroraUXTargetInfo(const llvm::Triple &Triple) 503 : OSTargetInfo<Target>(Triple) { 504 this->UserLabelPrefix = ""; 505 this->WCharType = this->SignedLong; 506 // FIXME: WIntType should be SignedLong 507 } 508 }; 509 510 // Solaris target 511 template<typename Target> 512 class SolarisTargetInfo : public OSTargetInfo<Target> { 513 protected: 514 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 515 MacroBuilder &Builder) const { 516 DefineStd(Builder, "sun", Opts); 517 DefineStd(Builder, "unix", Opts); 518 Builder.defineMacro("__ELF__"); 519 Builder.defineMacro("__svr4__"); 520 Builder.defineMacro("__SVR4"); 521 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 522 // newer, but to 500 for everything else. feature_test.h has a check to 523 // ensure that you are not using C99 with an old version of X/Open or C89 524 // with a new version. 525 if (Opts.C99 || Opts.C11) 526 Builder.defineMacro("_XOPEN_SOURCE", "600"); 527 else 528 Builder.defineMacro("_XOPEN_SOURCE", "500"); 529 if (Opts.CPlusPlus) 530 Builder.defineMacro("__C99FEATURES__"); 531 Builder.defineMacro("_LARGEFILE_SOURCE"); 532 Builder.defineMacro("_LARGEFILE64_SOURCE"); 533 Builder.defineMacro("__EXTENSIONS__"); 534 Builder.defineMacro("_REENTRANT"); 535 } 536 public: 537 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 538 this->UserLabelPrefix = ""; 539 this->WCharType = this->SignedInt; 540 // FIXME: WIntType should be SignedLong 541 } 542 }; 543 544 // Windows target 545 template<typename Target> 546 class WindowsTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const { 550 Builder.defineMacro("_WIN32"); 551 } 552 void getVisualStudioDefines(const LangOptions &Opts, 553 MacroBuilder &Builder) const { 554 if (Opts.CPlusPlus) { 555 if (Opts.RTTI) 556 Builder.defineMacro("_CPPRTTI"); 557 558 if (Opts.Exceptions) 559 Builder.defineMacro("_CPPUNWIND"); 560 } 561 562 if (!Opts.CharIsSigned) 563 Builder.defineMacro("_CHAR_UNSIGNED"); 564 565 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 566 // but it works for now. 567 if (Opts.POSIXThreads) 568 Builder.defineMacro("_MT"); 569 570 if (Opts.MSCVersion != 0) 571 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 572 573 if (Opts.MicrosoftExt) { 574 Builder.defineMacro("_MSC_EXTENSIONS"); 575 576 if (Opts.CPlusPlus11) { 577 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 578 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 579 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 580 } 581 } 582 583 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 584 } 585 586 public: 587 WindowsTargetInfo(const llvm::Triple &Triple) 588 : OSTargetInfo<Target>(Triple) {} 589 }; 590 591 template <typename Target> 592 class NaClTargetInfo : public OSTargetInfo<Target> { 593 protected: 594 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 595 MacroBuilder &Builder) const { 596 if (Opts.POSIXThreads) 597 Builder.defineMacro("_REENTRANT"); 598 if (Opts.CPlusPlus) 599 Builder.defineMacro("_GNU_SOURCE"); 600 601 DefineStd(Builder, "unix", Opts); 602 Builder.defineMacro("__ELF__"); 603 Builder.defineMacro("__native_client__"); 604 } 605 606 public: 607 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 608 this->UserLabelPrefix = ""; 609 this->LongAlign = 32; 610 this->LongWidth = 32; 611 this->PointerAlign = 32; 612 this->PointerWidth = 32; 613 this->IntMaxType = TargetInfo::SignedLongLong; 614 this->UIntMaxType = TargetInfo::UnsignedLongLong; 615 this->Int64Type = TargetInfo::SignedLongLong; 616 this->DoubleAlign = 64; 617 this->LongDoubleWidth = 64; 618 this->LongDoubleAlign = 64; 619 this->LongLongWidth = 64; 620 this->LongLongAlign = 64; 621 this->SizeType = TargetInfo::UnsignedInt; 622 this->PtrDiffType = TargetInfo::SignedInt; 623 this->IntPtrType = TargetInfo::SignedInt; 624 // RegParmMax is inherited from the underlying architecture 625 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 626 if (Triple.getArch() == llvm::Triple::arm) { 627 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 628 } else if (Triple.getArch() == llvm::Triple::x86) { 629 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 630 } else if (Triple.getArch() == llvm::Triple::x86_64) { 631 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 632 } else if (Triple.getArch() == llvm::Triple::mipsel) { 633 // Handled on mips' setDescriptionString. 634 } else { 635 assert(Triple.getArch() == llvm::Triple::le32); 636 this->DescriptionString = "e-p:32:32-i64:64"; 637 } 638 } 639 virtual typename Target::CallingConvCheckResult checkCallingConvention( 640 CallingConv CC) const { 641 return CC == CC_PnaclCall ? Target::CCCR_OK : 642 Target::checkCallingConvention(CC); 643 } 644 }; 645 } // end anonymous namespace. 646 647 //===----------------------------------------------------------------------===// 648 // Specific target implementations. 649 //===----------------------------------------------------------------------===// 650 651 namespace { 652 // PPC abstract base class 653 class PPCTargetInfo : public TargetInfo { 654 static const Builtin::Info BuiltinInfo[]; 655 static const char * const GCCRegNames[]; 656 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 657 std::string CPU; 658 659 // Target cpu features. 660 bool HasVSX; 661 662 public: 663 PPCTargetInfo(const llvm::Triple &Triple) 664 : TargetInfo(Triple), HasVSX(false) { 665 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 666 LongDoubleWidth = LongDoubleAlign = 128; 667 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 668 } 669 670 /// \brief Flags for architecture specific defines. 671 typedef enum { 672 ArchDefineNone = 0, 673 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 674 ArchDefinePpcgr = 1 << 1, 675 ArchDefinePpcsq = 1 << 2, 676 ArchDefine440 = 1 << 3, 677 ArchDefine603 = 1 << 4, 678 ArchDefine604 = 1 << 5, 679 ArchDefinePwr4 = 1 << 6, 680 ArchDefinePwr5 = 1 << 7, 681 ArchDefinePwr5x = 1 << 8, 682 ArchDefinePwr6 = 1 << 9, 683 ArchDefinePwr6x = 1 << 10, 684 ArchDefinePwr7 = 1 << 11, 685 ArchDefineA2 = 1 << 12, 686 ArchDefineA2q = 1 << 13 687 } ArchDefineTypes; 688 689 // Note: GCC recognizes the following additional cpus: 690 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 691 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 692 // titan, rs64. 693 virtual bool setCPU(const std::string &Name) { 694 bool CPUKnown = llvm::StringSwitch<bool>(Name) 695 .Case("generic", true) 696 .Case("440", true) 697 .Case("450", true) 698 .Case("601", true) 699 .Case("602", true) 700 .Case("603", true) 701 .Case("603e", true) 702 .Case("603ev", true) 703 .Case("604", true) 704 .Case("604e", true) 705 .Case("620", true) 706 .Case("630", true) 707 .Case("g3", true) 708 .Case("7400", true) 709 .Case("g4", true) 710 .Case("7450", true) 711 .Case("g4+", true) 712 .Case("750", true) 713 .Case("970", true) 714 .Case("g5", true) 715 .Case("a2", true) 716 .Case("a2q", true) 717 .Case("e500mc", true) 718 .Case("e5500", true) 719 .Case("power3", true) 720 .Case("pwr3", true) 721 .Case("power4", true) 722 .Case("pwr4", true) 723 .Case("power5", true) 724 .Case("pwr5", true) 725 .Case("power5x", true) 726 .Case("pwr5x", true) 727 .Case("power6", true) 728 .Case("pwr6", true) 729 .Case("power6x", true) 730 .Case("pwr6x", true) 731 .Case("power7", true) 732 .Case("pwr7", true) 733 .Case("powerpc", true) 734 .Case("ppc", true) 735 .Case("powerpc64", true) 736 .Case("ppc64", true) 737 .Case("powerpc64le", true) 738 .Case("ppc64le", true) 739 .Default(false); 740 741 if (CPUKnown) 742 CPU = Name; 743 744 return CPUKnown; 745 } 746 747 virtual void getTargetBuiltins(const Builtin::Info *&Records, 748 unsigned &NumRecords) const { 749 Records = BuiltinInfo; 750 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 751 } 752 753 virtual bool isCLZForZeroUndef() const { return false; } 754 755 virtual void getTargetDefines(const LangOptions &Opts, 756 MacroBuilder &Builder) const; 757 758 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 759 760 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 761 DiagnosticsEngine &Diags); 762 virtual bool hasFeature(StringRef Feature) const; 763 764 virtual void getGCCRegNames(const char * const *&Names, 765 unsigned &NumNames) const; 766 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 767 unsigned &NumAliases) const; 768 virtual bool validateAsmConstraint(const char *&Name, 769 TargetInfo::ConstraintInfo &Info) const { 770 switch (*Name) { 771 default: return false; 772 case 'O': // Zero 773 break; 774 case 'b': // Base register 775 case 'f': // Floating point register 776 Info.setAllowsRegister(); 777 break; 778 // FIXME: The following are added to allow parsing. 779 // I just took a guess at what the actions should be. 780 // Also, is more specific checking needed? I.e. specific registers? 781 case 'd': // Floating point register (containing 64-bit value) 782 case 'v': // Altivec vector register 783 Info.setAllowsRegister(); 784 break; 785 case 'w': 786 switch (Name[1]) { 787 case 'd':// VSX vector register to hold vector double data 788 case 'f':// VSX vector register to hold vector float data 789 case 's':// VSX vector register to hold scalar float data 790 case 'a':// Any VSX register 791 case 'c':// An individual CR bit 792 break; 793 default: 794 return false; 795 } 796 Info.setAllowsRegister(); 797 Name++; // Skip over 'w'. 798 break; 799 case 'h': // `MQ', `CTR', or `LINK' register 800 case 'q': // `MQ' register 801 case 'c': // `CTR' register 802 case 'l': // `LINK' register 803 case 'x': // `CR' register (condition register) number 0 804 case 'y': // `CR' register (condition register) 805 case 'z': // `XER[CA]' carry bit (part of the XER register) 806 Info.setAllowsRegister(); 807 break; 808 case 'I': // Signed 16-bit constant 809 case 'J': // Unsigned 16-bit constant shifted left 16 bits 810 // (use `L' instead for SImode constants) 811 case 'K': // Unsigned 16-bit constant 812 case 'L': // Signed 16-bit constant shifted left 16 bits 813 case 'M': // Constant larger than 31 814 case 'N': // Exact power of 2 815 case 'P': // Constant whose negation is a signed 16-bit constant 816 case 'G': // Floating point constant that can be loaded into a 817 // register with one instruction per word 818 case 'H': // Integer/Floating point constant that can be loaded 819 // into a register using three instructions 820 break; 821 case 'm': // Memory operand. Note that on PowerPC targets, m can 822 // include addresses that update the base register. It 823 // is therefore only safe to use `m' in an asm statement 824 // if that asm statement accesses the operand exactly once. 825 // The asm statement must also use `%U<opno>' as a 826 // placeholder for the "update" flag in the corresponding 827 // load or store instruction. For example: 828 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 829 // is correct but: 830 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 831 // is not. Use es rather than m if you don't want the base 832 // register to be updated. 833 case 'e': 834 if (Name[1] != 's') 835 return false; 836 // es: A "stable" memory operand; that is, one which does not 837 // include any automodification of the base register. Unlike 838 // `m', this constraint can be used in asm statements that 839 // might access the operand several times, or that might not 840 // access it at all. 841 Info.setAllowsMemory(); 842 Name++; // Skip over 'e'. 843 break; 844 case 'Q': // Memory operand that is an offset from a register (it is 845 // usually better to use `m' or `es' in asm statements) 846 case 'Z': // Memory operand that is an indexed or indirect from a 847 // register (it is usually better to use `m' or `es' in 848 // asm statements) 849 Info.setAllowsMemory(); 850 Info.setAllowsRegister(); 851 break; 852 case 'R': // AIX TOC entry 853 case 'a': // Address operand that is an indexed or indirect from a 854 // register (`p' is preferable for asm statements) 855 case 'S': // Constant suitable as a 64-bit mask operand 856 case 'T': // Constant suitable as a 32-bit mask operand 857 case 'U': // System V Release 4 small data area reference 858 case 't': // AND masks that can be performed by two rldic{l, r} 859 // instructions 860 case 'W': // Vector constant that does not require memory 861 case 'j': // Vector constant that is all zeros. 862 break; 863 // End FIXME. 864 } 865 return true; 866 } 867 virtual std::string convertConstraint(const char *&Constraint) const { 868 std::string R; 869 switch (*Constraint) { 870 case 'e': 871 case 'w': 872 // Two-character constraint; add "^" hint for later parsing. 873 R = std::string("^") + std::string(Constraint, 2); 874 Constraint++; 875 break; 876 default: 877 return TargetInfo::convertConstraint(Constraint); 878 } 879 return R; 880 } 881 virtual const char *getClobbers() const { 882 return ""; 883 } 884 int getEHDataRegisterNumber(unsigned RegNo) const { 885 if (RegNo == 0) return 3; 886 if (RegNo == 1) return 4; 887 return -1; 888 } 889 }; 890 891 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 892 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 894 ALL_LANGUAGES }, 895 #include "clang/Basic/BuiltinsPPC.def" 896 }; 897 898 /// handleTargetFeatures - Perform initialization based on the user 899 /// configured set of features. 900 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 901 DiagnosticsEngine &Diags) { 902 // Remember the maximum enabled sselevel. 903 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 904 // Ignore disabled features. 905 if (Features[i][0] == '-') 906 continue; 907 908 StringRef Feature = StringRef(Features[i]).substr(1); 909 910 if (Feature == "vsx") { 911 HasVSX = true; 912 continue; 913 } 914 915 // TODO: Finish this list and add an assert that we've handled them 916 // all. 917 } 918 919 return true; 920 } 921 922 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 923 /// #defines that are not tied to a specific subtarget. 924 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 925 MacroBuilder &Builder) const { 926 // Target identification. 927 Builder.defineMacro("__ppc__"); 928 Builder.defineMacro("__PPC__"); 929 Builder.defineMacro("_ARCH_PPC"); 930 Builder.defineMacro("__powerpc__"); 931 Builder.defineMacro("__POWERPC__"); 932 if (PointerWidth == 64) { 933 Builder.defineMacro("_ARCH_PPC64"); 934 Builder.defineMacro("__powerpc64__"); 935 Builder.defineMacro("__ppc64__"); 936 Builder.defineMacro("__PPC64__"); 937 } 938 939 // Target properties. 940 if (getTriple().getArch() == llvm::Triple::ppc64le) { 941 Builder.defineMacro("_LITTLE_ENDIAN"); 942 } else { 943 if (getTriple().getOS() != llvm::Triple::NetBSD && 944 getTriple().getOS() != llvm::Triple::OpenBSD) 945 Builder.defineMacro("_BIG_ENDIAN"); 946 } 947 948 // Subtarget options. 949 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 950 Builder.defineMacro("__REGISTER_PREFIX__", ""); 951 952 // FIXME: Should be controlled by command line option. 953 if (LongDoubleWidth == 128) 954 Builder.defineMacro("__LONG_DOUBLE_128__"); 955 956 if (Opts.AltiVec) { 957 Builder.defineMacro("__VEC__", "10206"); 958 Builder.defineMacro("__ALTIVEC__"); 959 } 960 961 // CPU identification. 962 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 963 .Case("440", ArchDefineName) 964 .Case("450", ArchDefineName | ArchDefine440) 965 .Case("601", ArchDefineName) 966 .Case("602", ArchDefineName | ArchDefinePpcgr) 967 .Case("603", ArchDefineName | ArchDefinePpcgr) 968 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 969 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 970 .Case("604", ArchDefineName | ArchDefinePpcgr) 971 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 972 .Case("620", ArchDefineName | ArchDefinePpcgr) 973 .Case("630", ArchDefineName | ArchDefinePpcgr) 974 .Case("7400", ArchDefineName | ArchDefinePpcgr) 975 .Case("7450", ArchDefineName | ArchDefinePpcgr) 976 .Case("750", ArchDefineName | ArchDefinePpcgr) 977 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 978 | ArchDefinePpcsq) 979 .Case("a2", ArchDefineA2) 980 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 981 .Case("pwr3", ArchDefinePpcgr) 982 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 983 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 984 | ArchDefinePpcsq) 985 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 986 | ArchDefinePpcgr | ArchDefinePpcsq) 987 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 988 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 989 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 990 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 991 | ArchDefinePpcsq) 992 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 993 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 994 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 995 .Case("power3", ArchDefinePpcgr) 996 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 997 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 998 | ArchDefinePpcsq) 999 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1000 | ArchDefinePpcgr | ArchDefinePpcsq) 1001 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1002 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1003 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1004 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1005 | ArchDefinePpcsq) 1006 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1007 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1008 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1009 .Default(ArchDefineNone); 1010 1011 if (defs & ArchDefineName) 1012 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1013 if (defs & ArchDefinePpcgr) 1014 Builder.defineMacro("_ARCH_PPCGR"); 1015 if (defs & ArchDefinePpcsq) 1016 Builder.defineMacro("_ARCH_PPCSQ"); 1017 if (defs & ArchDefine440) 1018 Builder.defineMacro("_ARCH_440"); 1019 if (defs & ArchDefine603) 1020 Builder.defineMacro("_ARCH_603"); 1021 if (defs & ArchDefine604) 1022 Builder.defineMacro("_ARCH_604"); 1023 if (defs & ArchDefinePwr4) 1024 Builder.defineMacro("_ARCH_PWR4"); 1025 if (defs & ArchDefinePwr5) 1026 Builder.defineMacro("_ARCH_PWR5"); 1027 if (defs & ArchDefinePwr5x) 1028 Builder.defineMacro("_ARCH_PWR5X"); 1029 if (defs & ArchDefinePwr6) 1030 Builder.defineMacro("_ARCH_PWR6"); 1031 if (defs & ArchDefinePwr6x) 1032 Builder.defineMacro("_ARCH_PWR6X"); 1033 if (defs & ArchDefinePwr7) 1034 Builder.defineMacro("_ARCH_PWR7"); 1035 if (defs & ArchDefineA2) 1036 Builder.defineMacro("_ARCH_A2"); 1037 if (defs & ArchDefineA2q) { 1038 Builder.defineMacro("_ARCH_A2Q"); 1039 Builder.defineMacro("_ARCH_QP"); 1040 } 1041 1042 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1043 Builder.defineMacro("__bg__"); 1044 Builder.defineMacro("__THW_BLUEGENE__"); 1045 Builder.defineMacro("__bgq__"); 1046 Builder.defineMacro("__TOS_BGQ__"); 1047 } 1048 1049 if (HasVSX) 1050 Builder.defineMacro("__VSX__"); 1051 1052 // FIXME: The following are not yet generated here by Clang, but are 1053 // generated by GCC: 1054 // 1055 // _SOFT_FLOAT_ 1056 // __RECIP_PRECISION__ 1057 // __APPLE_ALTIVEC__ 1058 // __RECIP__ 1059 // __RECIPF__ 1060 // __RSQRTE__ 1061 // __RSQRTEF__ 1062 // _SOFT_DOUBLE_ 1063 // __NO_LWSYNC__ 1064 // __HAVE_BSWAP__ 1065 // __LONGDOUBLE128 1066 // __CMODEL_MEDIUM__ 1067 // __CMODEL_LARGE__ 1068 // _CALL_SYSV 1069 // _CALL_DARWIN 1070 // __NO_FPRS__ 1071 } 1072 1073 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1074 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1075 .Case("7400", true) 1076 .Case("g4", true) 1077 .Case("7450", true) 1078 .Case("g4+", true) 1079 .Case("970", true) 1080 .Case("g5", true) 1081 .Case("pwr6", true) 1082 .Case("pwr7", true) 1083 .Case("ppc64", true) 1084 .Case("ppc64le", true) 1085 .Default(false); 1086 1087 Features["qpx"] = (CPU == "a2q"); 1088 } 1089 1090 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1091 return Feature == "powerpc"; 1092 } 1093 1094 1095 const char * const PPCTargetInfo::GCCRegNames[] = { 1096 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1097 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1098 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1099 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1100 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1101 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1102 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1103 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1104 "mq", "lr", "ctr", "ap", 1105 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1106 "xer", 1107 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1108 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1109 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1110 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1111 "vrsave", "vscr", 1112 "spe_acc", "spefscr", 1113 "sfp" 1114 }; 1115 1116 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1117 unsigned &NumNames) const { 1118 Names = GCCRegNames; 1119 NumNames = llvm::array_lengthof(GCCRegNames); 1120 } 1121 1122 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1123 // While some of these aliases do map to different registers 1124 // they still share the same register name. 1125 { { "0" }, "r0" }, 1126 { { "1"}, "r1" }, 1127 { { "2" }, "r2" }, 1128 { { "3" }, "r3" }, 1129 { { "4" }, "r4" }, 1130 { { "5" }, "r5" }, 1131 { { "6" }, "r6" }, 1132 { { "7" }, "r7" }, 1133 { { "8" }, "r8" }, 1134 { { "9" }, "r9" }, 1135 { { "10" }, "r10" }, 1136 { { "11" }, "r11" }, 1137 { { "12" }, "r12" }, 1138 { { "13" }, "r13" }, 1139 { { "14" }, "r14" }, 1140 { { "15" }, "r15" }, 1141 { { "16" }, "r16" }, 1142 { { "17" }, "r17" }, 1143 { { "18" }, "r18" }, 1144 { { "19" }, "r19" }, 1145 { { "20" }, "r20" }, 1146 { { "21" }, "r21" }, 1147 { { "22" }, "r22" }, 1148 { { "23" }, "r23" }, 1149 { { "24" }, "r24" }, 1150 { { "25" }, "r25" }, 1151 { { "26" }, "r26" }, 1152 { { "27" }, "r27" }, 1153 { { "28" }, "r28" }, 1154 { { "29" }, "r29" }, 1155 { { "30" }, "r30" }, 1156 { { "31" }, "r31" }, 1157 { { "fr0" }, "f0" }, 1158 { { "fr1" }, "f1" }, 1159 { { "fr2" }, "f2" }, 1160 { { "fr3" }, "f3" }, 1161 { { "fr4" }, "f4" }, 1162 { { "fr5" }, "f5" }, 1163 { { "fr6" }, "f6" }, 1164 { { "fr7" }, "f7" }, 1165 { { "fr8" }, "f8" }, 1166 { { "fr9" }, "f9" }, 1167 { { "fr10" }, "f10" }, 1168 { { "fr11" }, "f11" }, 1169 { { "fr12" }, "f12" }, 1170 { { "fr13" }, "f13" }, 1171 { { "fr14" }, "f14" }, 1172 { { "fr15" }, "f15" }, 1173 { { "fr16" }, "f16" }, 1174 { { "fr17" }, "f17" }, 1175 { { "fr18" }, "f18" }, 1176 { { "fr19" }, "f19" }, 1177 { { "fr20" }, "f20" }, 1178 { { "fr21" }, "f21" }, 1179 { { "fr22" }, "f22" }, 1180 { { "fr23" }, "f23" }, 1181 { { "fr24" }, "f24" }, 1182 { { "fr25" }, "f25" }, 1183 { { "fr26" }, "f26" }, 1184 { { "fr27" }, "f27" }, 1185 { { "fr28" }, "f28" }, 1186 { { "fr29" }, "f29" }, 1187 { { "fr30" }, "f30" }, 1188 { { "fr31" }, "f31" }, 1189 { { "cc" }, "cr0" }, 1190 }; 1191 1192 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1193 unsigned &NumAliases) const { 1194 Aliases = GCCRegAliases; 1195 NumAliases = llvm::array_lengthof(GCCRegAliases); 1196 } 1197 } // end anonymous namespace. 1198 1199 namespace { 1200 class PPC32TargetInfo : public PPCTargetInfo { 1201 public: 1202 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1203 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1204 1205 switch (getTriple().getOS()) { 1206 case llvm::Triple::Linux: 1207 case llvm::Triple::FreeBSD: 1208 case llvm::Triple::NetBSD: 1209 SizeType = UnsignedInt; 1210 PtrDiffType = SignedInt; 1211 IntPtrType = SignedInt; 1212 break; 1213 default: 1214 break; 1215 } 1216 1217 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1218 LongDoubleWidth = LongDoubleAlign = 64; 1219 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1220 } 1221 1222 // PPC32 supports atomics up to 4 bytes. 1223 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1224 } 1225 1226 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1227 // This is the ELF definition, and is overridden by the Darwin sub-target 1228 return TargetInfo::PowerABIBuiltinVaList; 1229 } 1230 }; 1231 } // end anonymous namespace. 1232 1233 // Note: ABI differences may eventually require us to have a separate 1234 // TargetInfo for little endian. 1235 namespace { 1236 class PPC64TargetInfo : public PPCTargetInfo { 1237 public: 1238 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1239 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1240 IntMaxType = SignedLong; 1241 UIntMaxType = UnsignedLong; 1242 Int64Type = SignedLong; 1243 1244 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1245 LongDoubleWidth = LongDoubleAlign = 64; 1246 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1247 DescriptionString = "E-m:e-i64:64-n32:64"; 1248 } else 1249 DescriptionString = "E-m:e-i64:64-n32:64"; 1250 1251 // PPC64 supports atomics up to 8 bytes. 1252 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1253 } 1254 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1255 return TargetInfo::CharPtrBuiltinVaList; 1256 } 1257 }; 1258 } // end anonymous namespace. 1259 1260 1261 namespace { 1262 class DarwinPPC32TargetInfo : 1263 public DarwinTargetInfo<PPC32TargetInfo> { 1264 public: 1265 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1266 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1267 HasAlignMac68kSupport = true; 1268 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1269 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1270 LongLongAlign = 32; 1271 SuitableAlign = 128; 1272 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1273 } 1274 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1275 return TargetInfo::CharPtrBuiltinVaList; 1276 } 1277 }; 1278 1279 class DarwinPPC64TargetInfo : 1280 public DarwinTargetInfo<PPC64TargetInfo> { 1281 public: 1282 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1283 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1284 HasAlignMac68kSupport = true; 1285 SuitableAlign = 128; 1286 DescriptionString = "E-m:o-i64:64-n32:64"; 1287 } 1288 }; 1289 } // end anonymous namespace. 1290 1291 namespace { 1292 static const unsigned NVPTXAddrSpaceMap[] = { 1293 1, // opencl_global 1294 3, // opencl_local 1295 4, // opencl_constant 1296 1, // cuda_device 1297 4, // cuda_constant 1298 3, // cuda_shared 1299 }; 1300 class NVPTXTargetInfo : public TargetInfo { 1301 static const char * const GCCRegNames[]; 1302 static const Builtin::Info BuiltinInfo[]; 1303 public: 1304 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1305 BigEndian = false; 1306 TLSSupported = false; 1307 LongWidth = LongAlign = 64; 1308 AddrSpaceMap = &NVPTXAddrSpaceMap; 1309 UseAddrSpaceMapMangling = true; 1310 // Define available target features 1311 // These must be defined in sorted order! 1312 NoAsmVariants = true; 1313 } 1314 virtual void getTargetDefines(const LangOptions &Opts, 1315 MacroBuilder &Builder) const { 1316 Builder.defineMacro("__PTX__"); 1317 Builder.defineMacro("__NVPTX__"); 1318 } 1319 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1320 unsigned &NumRecords) const { 1321 Records = BuiltinInfo; 1322 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1323 } 1324 virtual bool hasFeature(StringRef Feature) const { 1325 return Feature == "ptx" || Feature == "nvptx"; 1326 } 1327 1328 virtual void getGCCRegNames(const char * const *&Names, 1329 unsigned &NumNames) const; 1330 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1331 unsigned &NumAliases) const { 1332 // No aliases. 1333 Aliases = 0; 1334 NumAliases = 0; 1335 } 1336 virtual bool validateAsmConstraint(const char *&Name, 1337 TargetInfo::ConstraintInfo &Info) const { 1338 switch (*Name) { 1339 default: return false; 1340 case 'c': 1341 case 'h': 1342 case 'r': 1343 case 'l': 1344 case 'f': 1345 case 'd': 1346 Info.setAllowsRegister(); 1347 return true; 1348 } 1349 } 1350 virtual const char *getClobbers() const { 1351 // FIXME: Is this really right? 1352 return ""; 1353 } 1354 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1355 // FIXME: implement 1356 return TargetInfo::CharPtrBuiltinVaList; 1357 } 1358 virtual bool setCPU(const std::string &Name) { 1359 bool Valid = llvm::StringSwitch<bool>(Name) 1360 .Case("sm_20", true) 1361 .Case("sm_21", true) 1362 .Case("sm_30", true) 1363 .Case("sm_35", true) 1364 .Default(false); 1365 1366 return Valid; 1367 } 1368 }; 1369 1370 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1371 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1372 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1373 ALL_LANGUAGES }, 1374 #include "clang/Basic/BuiltinsNVPTX.def" 1375 }; 1376 1377 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1378 "r0" 1379 }; 1380 1381 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1382 unsigned &NumNames) const { 1383 Names = GCCRegNames; 1384 NumNames = llvm::array_lengthof(GCCRegNames); 1385 } 1386 1387 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1388 public: 1389 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1390 PointerWidth = PointerAlign = 32; 1391 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1392 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1393 } 1394 }; 1395 1396 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1397 public: 1398 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1399 PointerWidth = PointerAlign = 64; 1400 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1401 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1402 } 1403 }; 1404 } 1405 1406 namespace { 1407 1408 static const unsigned R600AddrSpaceMap[] = { 1409 1, // opencl_global 1410 3, // opencl_local 1411 2, // opencl_constant 1412 1, // cuda_device 1413 2, // cuda_constant 1414 3 // cuda_shared 1415 }; 1416 1417 static const char *DescriptionStringR600 = 1418 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1419 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1420 1421 static const char *DescriptionStringR600DoubleOps = 1422 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1423 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1424 1425 static const char *DescriptionStringSI = 1426 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1427 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1428 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1429 1430 class R600TargetInfo : public TargetInfo { 1431 /// \brief The GPU profiles supported by the R600 target. 1432 enum GPUKind { 1433 GK_NONE, 1434 GK_R600, 1435 GK_R600_DOUBLE_OPS, 1436 GK_R700, 1437 GK_R700_DOUBLE_OPS, 1438 GK_EVERGREEN, 1439 GK_EVERGREEN_DOUBLE_OPS, 1440 GK_NORTHERN_ISLANDS, 1441 GK_CAYMAN, 1442 GK_SOUTHERN_ISLANDS, 1443 GK_SEA_ISLANDS 1444 } GPU; 1445 1446 public: 1447 R600TargetInfo(const llvm::Triple &Triple) 1448 : TargetInfo(Triple), GPU(GK_R600) { 1449 DescriptionString = DescriptionStringR600; 1450 AddrSpaceMap = &R600AddrSpaceMap; 1451 UseAddrSpaceMapMangling = true; 1452 } 1453 1454 virtual const char * getClobbers() const { 1455 return ""; 1456 } 1457 1458 virtual void getGCCRegNames(const char * const *&Names, 1459 unsigned &numNames) const { 1460 Names = NULL; 1461 numNames = 0; 1462 } 1463 1464 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1465 unsigned &NumAliases) const { 1466 Aliases = NULL; 1467 NumAliases = 0; 1468 } 1469 1470 virtual bool validateAsmConstraint(const char *&Name, 1471 TargetInfo::ConstraintInfo &info) const { 1472 return true; 1473 } 1474 1475 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1476 unsigned &NumRecords) const { 1477 Records = NULL; 1478 NumRecords = 0; 1479 } 1480 1481 1482 virtual void getTargetDefines(const LangOptions &Opts, 1483 MacroBuilder &Builder) const { 1484 Builder.defineMacro("__R600__"); 1485 } 1486 1487 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1488 return TargetInfo::CharPtrBuiltinVaList; 1489 } 1490 1491 virtual bool setCPU(const std::string &Name) { 1492 GPU = llvm::StringSwitch<GPUKind>(Name) 1493 .Case("r600" , GK_R600) 1494 .Case("rv610", GK_R600) 1495 .Case("rv620", GK_R600) 1496 .Case("rv630", GK_R600) 1497 .Case("rv635", GK_R600) 1498 .Case("rs780", GK_R600) 1499 .Case("rs880", GK_R600) 1500 .Case("rv670", GK_R600_DOUBLE_OPS) 1501 .Case("rv710", GK_R700) 1502 .Case("rv730", GK_R700) 1503 .Case("rv740", GK_R700_DOUBLE_OPS) 1504 .Case("rv770", GK_R700_DOUBLE_OPS) 1505 .Case("palm", GK_EVERGREEN) 1506 .Case("cedar", GK_EVERGREEN) 1507 .Case("sumo", GK_EVERGREEN) 1508 .Case("sumo2", GK_EVERGREEN) 1509 .Case("redwood", GK_EVERGREEN) 1510 .Case("juniper", GK_EVERGREEN) 1511 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1512 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1513 .Case("barts", GK_NORTHERN_ISLANDS) 1514 .Case("turks", GK_NORTHERN_ISLANDS) 1515 .Case("caicos", GK_NORTHERN_ISLANDS) 1516 .Case("cayman", GK_CAYMAN) 1517 .Case("aruba", GK_CAYMAN) 1518 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1519 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1520 .Case("verde", GK_SOUTHERN_ISLANDS) 1521 .Case("oland", GK_SOUTHERN_ISLANDS) 1522 .Case("bonaire", GK_SEA_ISLANDS) 1523 .Case("kabini", GK_SEA_ISLANDS) 1524 .Case("kaveri", GK_SEA_ISLANDS) 1525 .Case("hawaii", GK_SEA_ISLANDS) 1526 .Default(GK_NONE); 1527 1528 if (GPU == GK_NONE) { 1529 return false; 1530 } 1531 1532 // Set the correct data layout 1533 switch (GPU) { 1534 case GK_NONE: 1535 case GK_R600: 1536 case GK_R700: 1537 case GK_EVERGREEN: 1538 case GK_NORTHERN_ISLANDS: 1539 DescriptionString = DescriptionStringR600; 1540 break; 1541 case GK_R600_DOUBLE_OPS: 1542 case GK_R700_DOUBLE_OPS: 1543 case GK_EVERGREEN_DOUBLE_OPS: 1544 case GK_CAYMAN: 1545 DescriptionString = DescriptionStringR600DoubleOps; 1546 break; 1547 case GK_SOUTHERN_ISLANDS: 1548 case GK_SEA_ISLANDS: 1549 DescriptionString = DescriptionStringSI; 1550 break; 1551 } 1552 1553 return true; 1554 } 1555 }; 1556 1557 } // end anonymous namespace 1558 1559 namespace { 1560 // Namespace for x86 abstract base class 1561 const Builtin::Info BuiltinInfo[] = { 1562 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1563 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1564 ALL_LANGUAGES }, 1565 #include "clang/Basic/BuiltinsX86.def" 1566 }; 1567 1568 static const char* const GCCRegNames[] = { 1569 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1570 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1571 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1572 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1573 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1574 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1575 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1576 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1577 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1578 }; 1579 1580 const TargetInfo::AddlRegName AddlRegNames[] = { 1581 { { "al", "ah", "eax", "rax" }, 0 }, 1582 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1583 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1584 { { "dl", "dh", "edx", "rdx" }, 1 }, 1585 { { "esi", "rsi" }, 4 }, 1586 { { "edi", "rdi" }, 5 }, 1587 { { "esp", "rsp" }, 7 }, 1588 { { "ebp", "rbp" }, 6 }, 1589 }; 1590 1591 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1592 // most of the implementation can be shared. 1593 class X86TargetInfo : public TargetInfo { 1594 enum X86SSEEnum { 1595 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1596 } SSELevel; 1597 enum MMX3DNowEnum { 1598 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1599 } MMX3DNowLevel; 1600 enum XOPEnum { 1601 NoXOP, 1602 SSE4A, 1603 FMA4, 1604 XOP 1605 } XOPLevel; 1606 1607 bool HasAES; 1608 bool HasPCLMUL; 1609 bool HasLZCNT; 1610 bool HasRDRND; 1611 bool HasBMI; 1612 bool HasBMI2; 1613 bool HasPOPCNT; 1614 bool HasRTM; 1615 bool HasPRFCHW; 1616 bool HasRDSEED; 1617 bool HasTBM; 1618 bool HasFMA; 1619 bool HasF16C; 1620 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1621 bool HasSHA; 1622 bool HasCX16; 1623 1624 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1625 /// 1626 /// Each enumeration represents a particular CPU supported by Clang. These 1627 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1628 enum CPUKind { 1629 CK_Generic, 1630 1631 /// \name i386 1632 /// i386-generation processors. 1633 //@{ 1634 CK_i386, 1635 //@} 1636 1637 /// \name i486 1638 /// i486-generation processors. 1639 //@{ 1640 CK_i486, 1641 CK_WinChipC6, 1642 CK_WinChip2, 1643 CK_C3, 1644 //@} 1645 1646 /// \name i586 1647 /// i586-generation processors, P5 microarchitecture based. 1648 //@{ 1649 CK_i586, 1650 CK_Pentium, 1651 CK_PentiumMMX, 1652 //@} 1653 1654 /// \name i686 1655 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1656 //@{ 1657 CK_i686, 1658 CK_PentiumPro, 1659 CK_Pentium2, 1660 CK_Pentium3, 1661 CK_Pentium3M, 1662 CK_PentiumM, 1663 CK_C3_2, 1664 1665 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1666 /// Clang however has some logic to suport this. 1667 // FIXME: Warn, deprecate, and potentially remove this. 1668 CK_Yonah, 1669 //@} 1670 1671 /// \name Netburst 1672 /// Netburst microarchitecture based processors. 1673 //@{ 1674 CK_Pentium4, 1675 CK_Pentium4M, 1676 CK_Prescott, 1677 CK_Nocona, 1678 //@} 1679 1680 /// \name Core 1681 /// Core microarchitecture based processors. 1682 //@{ 1683 CK_Core2, 1684 1685 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1686 /// codename which GCC no longer accepts as an option to -march, but Clang 1687 /// has some logic for recognizing it. 1688 // FIXME: Warn, deprecate, and potentially remove this. 1689 CK_Penryn, 1690 //@} 1691 1692 /// \name Atom 1693 /// Atom processors 1694 //@{ 1695 CK_Atom, 1696 CK_Silvermont, 1697 //@} 1698 1699 /// \name Nehalem 1700 /// Nehalem microarchitecture based processors. 1701 //@{ 1702 CK_Corei7, 1703 CK_Corei7AVX, 1704 CK_CoreAVXi, 1705 CK_CoreAVX2, 1706 //@} 1707 1708 /// \name Knights Landing 1709 /// Knights Landing processor. 1710 CK_KNL, 1711 1712 /// \name K6 1713 /// K6 architecture processors. 1714 //@{ 1715 CK_K6, 1716 CK_K6_2, 1717 CK_K6_3, 1718 //@} 1719 1720 /// \name K7 1721 /// K7 architecture processors. 1722 //@{ 1723 CK_Athlon, 1724 CK_AthlonThunderbird, 1725 CK_Athlon4, 1726 CK_AthlonXP, 1727 CK_AthlonMP, 1728 //@} 1729 1730 /// \name K8 1731 /// K8 architecture processors. 1732 //@{ 1733 CK_Athlon64, 1734 CK_Athlon64SSE3, 1735 CK_AthlonFX, 1736 CK_K8, 1737 CK_K8SSE3, 1738 CK_Opteron, 1739 CK_OpteronSSE3, 1740 CK_AMDFAM10, 1741 //@} 1742 1743 /// \name Bobcat 1744 /// Bobcat architecture processors. 1745 //@{ 1746 CK_BTVER1, 1747 CK_BTVER2, 1748 //@} 1749 1750 /// \name Bulldozer 1751 /// Bulldozer architecture processors. 1752 //@{ 1753 CK_BDVER1, 1754 CK_BDVER2, 1755 CK_BDVER3, 1756 //@} 1757 1758 /// This specification is deprecated and will be removed in the future. 1759 /// Users should prefer \see CK_K8. 1760 // FIXME: Warn on this when the CPU is set to it. 1761 CK_x86_64, 1762 //@} 1763 1764 /// \name Geode 1765 /// Geode processors. 1766 //@{ 1767 CK_Geode 1768 //@} 1769 } CPU; 1770 1771 enum FPMathKind { 1772 FP_Default, 1773 FP_SSE, 1774 FP_387 1775 } FPMath; 1776 1777 public: 1778 X86TargetInfo(const llvm::Triple &Triple) 1779 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1780 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1781 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1782 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1783 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1784 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1785 FPMath(FP_Default) { 1786 BigEndian = false; 1787 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1788 } 1789 virtual unsigned getFloatEvalMethod() const { 1790 // X87 evaluates with 80 bits "long double" precision. 1791 return SSELevel == NoSSE ? 2 : 0; 1792 } 1793 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1794 unsigned &NumRecords) const { 1795 Records = BuiltinInfo; 1796 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1797 } 1798 virtual void getGCCRegNames(const char * const *&Names, 1799 unsigned &NumNames) const { 1800 Names = GCCRegNames; 1801 NumNames = llvm::array_lengthof(GCCRegNames); 1802 } 1803 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1804 unsigned &NumAliases) const { 1805 Aliases = 0; 1806 NumAliases = 0; 1807 } 1808 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1809 unsigned &NumNames) const { 1810 Names = AddlRegNames; 1811 NumNames = llvm::array_lengthof(AddlRegNames); 1812 } 1813 virtual bool validateAsmConstraint(const char *&Name, 1814 TargetInfo::ConstraintInfo &info) const; 1815 virtual std::string convertConstraint(const char *&Constraint) const; 1816 virtual const char *getClobbers() const { 1817 return "~{dirflag},~{fpsr},~{flags}"; 1818 } 1819 virtual void getTargetDefines(const LangOptions &Opts, 1820 MacroBuilder &Builder) const; 1821 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1822 bool Enabled); 1823 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1824 bool Enabled); 1825 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1826 bool Enabled); 1827 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1828 StringRef Name, bool Enabled) const { 1829 setFeatureEnabledImpl(Features, Name, Enabled); 1830 } 1831 // This exists purely to cut down on the number of virtual calls in 1832 // getDefaultFeatures which calls this repeatedly. 1833 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1834 StringRef Name, bool Enabled); 1835 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1836 virtual bool hasFeature(StringRef Feature) const; 1837 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1838 DiagnosticsEngine &Diags); 1839 virtual const char* getABI() const { 1840 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1841 return "avx"; 1842 else if (getTriple().getArch() == llvm::Triple::x86 && 1843 MMX3DNowLevel == NoMMX3DNow) 1844 return "no-mmx"; 1845 return ""; 1846 } 1847 virtual bool setCPU(const std::string &Name) { 1848 CPU = llvm::StringSwitch<CPUKind>(Name) 1849 .Case("i386", CK_i386) 1850 .Case("i486", CK_i486) 1851 .Case("winchip-c6", CK_WinChipC6) 1852 .Case("winchip2", CK_WinChip2) 1853 .Case("c3", CK_C3) 1854 .Case("i586", CK_i586) 1855 .Case("pentium", CK_Pentium) 1856 .Case("pentium-mmx", CK_PentiumMMX) 1857 .Case("i686", CK_i686) 1858 .Case("pentiumpro", CK_PentiumPro) 1859 .Case("pentium2", CK_Pentium2) 1860 .Case("pentium3", CK_Pentium3) 1861 .Case("pentium3m", CK_Pentium3M) 1862 .Case("pentium-m", CK_PentiumM) 1863 .Case("c3-2", CK_C3_2) 1864 .Case("yonah", CK_Yonah) 1865 .Case("pentium4", CK_Pentium4) 1866 .Case("pentium4m", CK_Pentium4M) 1867 .Case("prescott", CK_Prescott) 1868 .Case("nocona", CK_Nocona) 1869 .Case("core2", CK_Core2) 1870 .Case("penryn", CK_Penryn) 1871 .Case("atom", CK_Atom) 1872 .Case("slm", CK_Silvermont) 1873 .Case("corei7", CK_Corei7) 1874 .Case("corei7-avx", CK_Corei7AVX) 1875 .Case("core-avx-i", CK_CoreAVXi) 1876 .Case("core-avx2", CK_CoreAVX2) 1877 .Case("knl", CK_KNL) 1878 .Case("k6", CK_K6) 1879 .Case("k6-2", CK_K6_2) 1880 .Case("k6-3", CK_K6_3) 1881 .Case("athlon", CK_Athlon) 1882 .Case("athlon-tbird", CK_AthlonThunderbird) 1883 .Case("athlon-4", CK_Athlon4) 1884 .Case("athlon-xp", CK_AthlonXP) 1885 .Case("athlon-mp", CK_AthlonMP) 1886 .Case("athlon64", CK_Athlon64) 1887 .Case("athlon64-sse3", CK_Athlon64SSE3) 1888 .Case("athlon-fx", CK_AthlonFX) 1889 .Case("k8", CK_K8) 1890 .Case("k8-sse3", CK_K8SSE3) 1891 .Case("opteron", CK_Opteron) 1892 .Case("opteron-sse3", CK_OpteronSSE3) 1893 .Case("amdfam10", CK_AMDFAM10) 1894 .Case("btver1", CK_BTVER1) 1895 .Case("btver2", CK_BTVER2) 1896 .Case("bdver1", CK_BDVER1) 1897 .Case("bdver2", CK_BDVER2) 1898 .Case("bdver3", CK_BDVER3) 1899 .Case("x86-64", CK_x86_64) 1900 .Case("geode", CK_Geode) 1901 .Default(CK_Generic); 1902 1903 // Perform any per-CPU checks necessary to determine if this CPU is 1904 // acceptable. 1905 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1906 // invalid without explaining *why*. 1907 switch (CPU) { 1908 case CK_Generic: 1909 // No processor selected! 1910 return false; 1911 1912 case CK_i386: 1913 case CK_i486: 1914 case CK_WinChipC6: 1915 case CK_WinChip2: 1916 case CK_C3: 1917 case CK_i586: 1918 case CK_Pentium: 1919 case CK_PentiumMMX: 1920 case CK_i686: 1921 case CK_PentiumPro: 1922 case CK_Pentium2: 1923 case CK_Pentium3: 1924 case CK_Pentium3M: 1925 case CK_PentiumM: 1926 case CK_Yonah: 1927 case CK_C3_2: 1928 case CK_Pentium4: 1929 case CK_Pentium4M: 1930 case CK_Prescott: 1931 case CK_K6: 1932 case CK_K6_2: 1933 case CK_K6_3: 1934 case CK_Athlon: 1935 case CK_AthlonThunderbird: 1936 case CK_Athlon4: 1937 case CK_AthlonXP: 1938 case CK_AthlonMP: 1939 case CK_Geode: 1940 // Only accept certain architectures when compiling in 32-bit mode. 1941 if (getTriple().getArch() != llvm::Triple::x86) 1942 return false; 1943 1944 // Fallthrough 1945 case CK_Nocona: 1946 case CK_Core2: 1947 case CK_Penryn: 1948 case CK_Atom: 1949 case CK_Silvermont: 1950 case CK_Corei7: 1951 case CK_Corei7AVX: 1952 case CK_CoreAVXi: 1953 case CK_CoreAVX2: 1954 case CK_KNL: 1955 case CK_Athlon64: 1956 case CK_Athlon64SSE3: 1957 case CK_AthlonFX: 1958 case CK_K8: 1959 case CK_K8SSE3: 1960 case CK_Opteron: 1961 case CK_OpteronSSE3: 1962 case CK_AMDFAM10: 1963 case CK_BTVER1: 1964 case CK_BTVER2: 1965 case CK_BDVER1: 1966 case CK_BDVER2: 1967 case CK_BDVER3: 1968 case CK_x86_64: 1969 return true; 1970 } 1971 llvm_unreachable("Unhandled CPU kind"); 1972 } 1973 1974 virtual bool setFPMath(StringRef Name); 1975 1976 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1977 // We accept all non-ARM calling conventions 1978 return (CC == CC_X86ThisCall || 1979 CC == CC_X86FastCall || 1980 CC == CC_X86StdCall || 1981 CC == CC_C || 1982 CC == CC_X86Pascal || 1983 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 1984 } 1985 1986 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 1987 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 1988 } 1989 }; 1990 1991 bool X86TargetInfo::setFPMath(StringRef Name) { 1992 if (Name == "387") { 1993 FPMath = FP_387; 1994 return true; 1995 } 1996 if (Name == "sse") { 1997 FPMath = FP_SSE; 1998 return true; 1999 } 2000 return false; 2001 } 2002 2003 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2004 // FIXME: This *really* should not be here. 2005 2006 // X86_64 always has SSE2. 2007 if (getTriple().getArch() == llvm::Triple::x86_64) 2008 setFeatureEnabledImpl(Features, "sse2", true); 2009 2010 switch (CPU) { 2011 case CK_Generic: 2012 case CK_i386: 2013 case CK_i486: 2014 case CK_i586: 2015 case CK_Pentium: 2016 case CK_i686: 2017 case CK_PentiumPro: 2018 break; 2019 case CK_PentiumMMX: 2020 case CK_Pentium2: 2021 setFeatureEnabledImpl(Features, "mmx", true); 2022 break; 2023 case CK_Pentium3: 2024 case CK_Pentium3M: 2025 setFeatureEnabledImpl(Features, "sse", true); 2026 break; 2027 case CK_PentiumM: 2028 case CK_Pentium4: 2029 case CK_Pentium4M: 2030 case CK_x86_64: 2031 setFeatureEnabledImpl(Features, "sse2", true); 2032 break; 2033 case CK_Yonah: 2034 case CK_Prescott: 2035 case CK_Nocona: 2036 setFeatureEnabledImpl(Features, "sse3", true); 2037 setFeatureEnabledImpl(Features, "cx16", true); 2038 break; 2039 case CK_Core2: 2040 setFeatureEnabledImpl(Features, "ssse3", true); 2041 setFeatureEnabledImpl(Features, "cx16", true); 2042 break; 2043 case CK_Penryn: 2044 setFeatureEnabledImpl(Features, "sse4.1", true); 2045 setFeatureEnabledImpl(Features, "cx16", true); 2046 break; 2047 case CK_Atom: 2048 setFeatureEnabledImpl(Features, "ssse3", true); 2049 setFeatureEnabledImpl(Features, "cx16", true); 2050 break; 2051 case CK_Silvermont: 2052 setFeatureEnabledImpl(Features, "sse4.2", true); 2053 setFeatureEnabledImpl(Features, "aes", true); 2054 setFeatureEnabledImpl(Features, "cx16", true); 2055 setFeatureEnabledImpl(Features, "pclmul", true); 2056 break; 2057 case CK_Corei7: 2058 setFeatureEnabledImpl(Features, "sse4.2", true); 2059 setFeatureEnabledImpl(Features, "cx16", true); 2060 break; 2061 case CK_Corei7AVX: 2062 setFeatureEnabledImpl(Features, "avx", true); 2063 setFeatureEnabledImpl(Features, "aes", true); 2064 setFeatureEnabledImpl(Features, "cx16", true); 2065 setFeatureEnabledImpl(Features, "pclmul", true); 2066 break; 2067 case CK_CoreAVXi: 2068 setFeatureEnabledImpl(Features, "avx", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "pclmul", true); 2071 setFeatureEnabledImpl(Features, "rdrnd", true); 2072 setFeatureEnabledImpl(Features, "f16c", true); 2073 break; 2074 case CK_CoreAVX2: 2075 setFeatureEnabledImpl(Features, "avx2", true); 2076 setFeatureEnabledImpl(Features, "aes", true); 2077 setFeatureEnabledImpl(Features, "pclmul", true); 2078 setFeatureEnabledImpl(Features, "lzcnt", true); 2079 setFeatureEnabledImpl(Features, "rdrnd", true); 2080 setFeatureEnabledImpl(Features, "f16c", true); 2081 setFeatureEnabledImpl(Features, "bmi", true); 2082 setFeatureEnabledImpl(Features, "bmi2", true); 2083 setFeatureEnabledImpl(Features, "rtm", true); 2084 setFeatureEnabledImpl(Features, "fma", true); 2085 setFeatureEnabledImpl(Features, "cx16", true); 2086 break; 2087 case CK_KNL: 2088 setFeatureEnabledImpl(Features, "avx512f", true); 2089 setFeatureEnabledImpl(Features, "avx512cd", true); 2090 setFeatureEnabledImpl(Features, "avx512er", true); 2091 setFeatureEnabledImpl(Features, "avx512pf", true); 2092 setFeatureEnabledImpl(Features, "aes", true); 2093 setFeatureEnabledImpl(Features, "pclmul", true); 2094 setFeatureEnabledImpl(Features, "lzcnt", true); 2095 setFeatureEnabledImpl(Features, "rdrnd", true); 2096 setFeatureEnabledImpl(Features, "f16c", true); 2097 setFeatureEnabledImpl(Features, "bmi", true); 2098 setFeatureEnabledImpl(Features, "bmi2", true); 2099 setFeatureEnabledImpl(Features, "rtm", true); 2100 setFeatureEnabledImpl(Features, "fma", true); 2101 break; 2102 case CK_K6: 2103 case CK_WinChipC6: 2104 setFeatureEnabledImpl(Features, "mmx", true); 2105 break; 2106 case CK_K6_2: 2107 case CK_K6_3: 2108 case CK_WinChip2: 2109 case CK_C3: 2110 setFeatureEnabledImpl(Features, "3dnow", true); 2111 break; 2112 case CK_Athlon: 2113 case CK_AthlonThunderbird: 2114 case CK_Geode: 2115 setFeatureEnabledImpl(Features, "3dnowa", true); 2116 break; 2117 case CK_Athlon4: 2118 case CK_AthlonXP: 2119 case CK_AthlonMP: 2120 setFeatureEnabledImpl(Features, "sse", true); 2121 setFeatureEnabledImpl(Features, "3dnowa", true); 2122 break; 2123 case CK_K8: 2124 case CK_Opteron: 2125 case CK_Athlon64: 2126 case CK_AthlonFX: 2127 setFeatureEnabledImpl(Features, "sse2", true); 2128 setFeatureEnabledImpl(Features, "3dnowa", true); 2129 break; 2130 case CK_K8SSE3: 2131 case CK_OpteronSSE3: 2132 case CK_Athlon64SSE3: 2133 setFeatureEnabledImpl(Features, "sse3", true); 2134 setFeatureEnabledImpl(Features, "3dnowa", true); 2135 break; 2136 case CK_AMDFAM10: 2137 setFeatureEnabledImpl(Features, "sse3", true); 2138 setFeatureEnabledImpl(Features, "sse4a", true); 2139 setFeatureEnabledImpl(Features, "3dnowa", true); 2140 setFeatureEnabledImpl(Features, "lzcnt", true); 2141 setFeatureEnabledImpl(Features, "popcnt", true); 2142 break; 2143 case CK_BTVER1: 2144 setFeatureEnabledImpl(Features, "ssse3", true); 2145 setFeatureEnabledImpl(Features, "sse4a", true); 2146 setFeatureEnabledImpl(Features, "cx16", true); 2147 setFeatureEnabledImpl(Features, "lzcnt", true); 2148 setFeatureEnabledImpl(Features, "popcnt", true); 2149 setFeatureEnabledImpl(Features, "prfchw", true); 2150 break; 2151 case CK_BTVER2: 2152 setFeatureEnabledImpl(Features, "avx", true); 2153 setFeatureEnabledImpl(Features, "sse4a", true); 2154 setFeatureEnabledImpl(Features, "lzcnt", true); 2155 setFeatureEnabledImpl(Features, "aes", true); 2156 setFeatureEnabledImpl(Features, "pclmul", true); 2157 setFeatureEnabledImpl(Features, "prfchw", true); 2158 setFeatureEnabledImpl(Features, "bmi", true); 2159 setFeatureEnabledImpl(Features, "f16c", true); 2160 setFeatureEnabledImpl(Features, "cx16", true); 2161 break; 2162 case CK_BDVER1: 2163 setFeatureEnabledImpl(Features, "xop", true); 2164 setFeatureEnabledImpl(Features, "lzcnt", true); 2165 setFeatureEnabledImpl(Features, "aes", true); 2166 setFeatureEnabledImpl(Features, "pclmul", true); 2167 setFeatureEnabledImpl(Features, "prfchw", true); 2168 setFeatureEnabledImpl(Features, "cx16", true); 2169 break; 2170 case CK_BDVER2: 2171 case CK_BDVER3: 2172 setFeatureEnabledImpl(Features, "xop", true); 2173 setFeatureEnabledImpl(Features, "lzcnt", true); 2174 setFeatureEnabledImpl(Features, "aes", true); 2175 setFeatureEnabledImpl(Features, "pclmul", true); 2176 setFeatureEnabledImpl(Features, "prfchw", true); 2177 setFeatureEnabledImpl(Features, "bmi", true); 2178 setFeatureEnabledImpl(Features, "fma", true); 2179 setFeatureEnabledImpl(Features, "f16c", true); 2180 setFeatureEnabledImpl(Features, "tbm", true); 2181 setFeatureEnabledImpl(Features, "cx16", true); 2182 break; 2183 case CK_C3_2: 2184 setFeatureEnabledImpl(Features, "sse", true); 2185 break; 2186 } 2187 } 2188 2189 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2190 X86SSEEnum Level, bool Enabled) { 2191 if (Enabled) { 2192 switch (Level) { 2193 case AVX512F: 2194 Features["avx512f"] = true; 2195 case AVX2: 2196 Features["avx2"] = true; 2197 case AVX: 2198 Features["avx"] = true; 2199 case SSE42: 2200 Features["sse4.2"] = true; 2201 case SSE41: 2202 Features["sse4.1"] = true; 2203 case SSSE3: 2204 Features["ssse3"] = true; 2205 case SSE3: 2206 Features["sse3"] = true; 2207 case SSE2: 2208 Features["sse2"] = true; 2209 case SSE1: 2210 Features["sse"] = true; 2211 case NoSSE: 2212 break; 2213 } 2214 return; 2215 } 2216 2217 switch (Level) { 2218 case NoSSE: 2219 case SSE1: 2220 Features["sse"] = false; 2221 case SSE2: 2222 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2223 Features["sha"] = false; 2224 case SSE3: 2225 Features["sse3"] = false; 2226 setXOPLevel(Features, NoXOP, false); 2227 case SSSE3: 2228 Features["ssse3"] = false; 2229 case SSE41: 2230 Features["sse4.1"] = false; 2231 case SSE42: 2232 Features["sse4.2"] = false; 2233 case AVX: 2234 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2235 setXOPLevel(Features, FMA4, false); 2236 case AVX2: 2237 Features["avx2"] = false; 2238 case AVX512F: 2239 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2240 Features["avx512pf"] = false; 2241 } 2242 } 2243 2244 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2245 MMX3DNowEnum Level, bool Enabled) { 2246 if (Enabled) { 2247 switch (Level) { 2248 case AMD3DNowAthlon: 2249 Features["3dnowa"] = true; 2250 case AMD3DNow: 2251 Features["3dnow"] = true; 2252 case MMX: 2253 Features["mmx"] = true; 2254 case NoMMX3DNow: 2255 break; 2256 } 2257 return; 2258 } 2259 2260 switch (Level) { 2261 case NoMMX3DNow: 2262 case MMX: 2263 Features["mmx"] = false; 2264 case AMD3DNow: 2265 Features["3dnow"] = false; 2266 case AMD3DNowAthlon: 2267 Features["3dnowa"] = false; 2268 } 2269 } 2270 2271 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2272 bool Enabled) { 2273 if (Enabled) { 2274 switch (Level) { 2275 case XOP: 2276 Features["xop"] = true; 2277 case FMA4: 2278 Features["fma4"] = true; 2279 setSSELevel(Features, AVX, true); 2280 case SSE4A: 2281 Features["sse4a"] = true; 2282 setSSELevel(Features, SSE3, true); 2283 case NoXOP: 2284 break; 2285 } 2286 return; 2287 } 2288 2289 switch (Level) { 2290 case NoXOP: 2291 case SSE4A: 2292 Features["sse4a"] = false; 2293 case FMA4: 2294 Features["fma4"] = false; 2295 case XOP: 2296 Features["xop"] = false; 2297 } 2298 } 2299 2300 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2301 StringRef Name, bool Enabled) { 2302 // FIXME: This *really* should not be here. We need some way of translating 2303 // options into llvm subtarget features. 2304 if (Name == "sse4") 2305 Name = "sse4.2"; 2306 2307 Features[Name] = Enabled; 2308 2309 if (Name == "mmx") { 2310 setMMXLevel(Features, MMX, Enabled); 2311 } else if (Name == "sse") { 2312 setSSELevel(Features, SSE1, Enabled); 2313 } else if (Name == "sse2") { 2314 setSSELevel(Features, SSE2, Enabled); 2315 } else if (Name == "sse3") { 2316 setSSELevel(Features, SSE3, Enabled); 2317 } else if (Name == "ssse3") { 2318 setSSELevel(Features, SSSE3, Enabled); 2319 } else if (Name == "sse4.2") { 2320 setSSELevel(Features, SSE42, Enabled); 2321 } else if (Name == "sse4.1") { 2322 setSSELevel(Features, SSE41, Enabled); 2323 } else if (Name == "3dnow") { 2324 setMMXLevel(Features, AMD3DNow, Enabled); 2325 } else if (Name == "3dnowa") { 2326 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2327 } else if (Name == "aes") { 2328 if (Enabled) 2329 setSSELevel(Features, SSE2, Enabled); 2330 } else if (Name == "pclmul") { 2331 if (Enabled) 2332 setSSELevel(Features, SSE2, Enabled); 2333 } else if (Name == "avx") { 2334 setSSELevel(Features, AVX, Enabled); 2335 } else if (Name == "avx2") { 2336 setSSELevel(Features, AVX2, Enabled); 2337 } else if (Name == "avx512f") { 2338 setSSELevel(Features, AVX512F, Enabled); 2339 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2340 if (Enabled) 2341 setSSELevel(Features, AVX512F, Enabled); 2342 } else if (Name == "fma") { 2343 if (Enabled) 2344 setSSELevel(Features, AVX, Enabled); 2345 } else if (Name == "fma4") { 2346 setXOPLevel(Features, FMA4, Enabled); 2347 } else if (Name == "xop") { 2348 setXOPLevel(Features, XOP, Enabled); 2349 } else if (Name == "sse4a") { 2350 setXOPLevel(Features, SSE4A, Enabled); 2351 } else if (Name == "f16c") { 2352 if (Enabled) 2353 setSSELevel(Features, AVX, Enabled); 2354 } else if (Name == "sha") { 2355 if (Enabled) 2356 setSSELevel(Features, SSE2, Enabled); 2357 } 2358 } 2359 2360 /// handleTargetFeatures - Perform initialization based on the user 2361 /// configured set of features. 2362 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2363 DiagnosticsEngine &Diags) { 2364 // Remember the maximum enabled sselevel. 2365 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2366 // Ignore disabled features. 2367 if (Features[i][0] == '-') 2368 continue; 2369 2370 StringRef Feature = StringRef(Features[i]).substr(1); 2371 2372 if (Feature == "aes") { 2373 HasAES = true; 2374 continue; 2375 } 2376 2377 if (Feature == "pclmul") { 2378 HasPCLMUL = true; 2379 continue; 2380 } 2381 2382 if (Feature == "lzcnt") { 2383 HasLZCNT = true; 2384 continue; 2385 } 2386 2387 if (Feature == "rdrnd") { 2388 HasRDRND = true; 2389 continue; 2390 } 2391 2392 if (Feature == "bmi") { 2393 HasBMI = true; 2394 continue; 2395 } 2396 2397 if (Feature == "bmi2") { 2398 HasBMI2 = true; 2399 continue; 2400 } 2401 2402 if (Feature == "popcnt") { 2403 HasPOPCNT = true; 2404 continue; 2405 } 2406 2407 if (Feature == "rtm") { 2408 HasRTM = true; 2409 continue; 2410 } 2411 2412 if (Feature == "prfchw") { 2413 HasPRFCHW = true; 2414 continue; 2415 } 2416 2417 if (Feature == "rdseed") { 2418 HasRDSEED = true; 2419 continue; 2420 } 2421 2422 if (Feature == "tbm") { 2423 HasTBM = true; 2424 continue; 2425 } 2426 2427 if (Feature == "fma") { 2428 HasFMA = true; 2429 continue; 2430 } 2431 2432 if (Feature == "f16c") { 2433 HasF16C = true; 2434 continue; 2435 } 2436 2437 if (Feature == "avx512cd") { 2438 HasAVX512CD = true; 2439 continue; 2440 } 2441 2442 if (Feature == "avx512er") { 2443 HasAVX512ER = true; 2444 continue; 2445 } 2446 2447 if (Feature == "avx512pf") { 2448 HasAVX512PF = true; 2449 continue; 2450 } 2451 2452 if (Feature == "sha") { 2453 HasSHA = true; 2454 continue; 2455 } 2456 2457 if (Feature == "cx16") { 2458 HasCX16 = true; 2459 continue; 2460 } 2461 2462 assert(Features[i][0] == '+' && "Invalid target feature!"); 2463 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2464 .Case("avx512f", AVX512F) 2465 .Case("avx2", AVX2) 2466 .Case("avx", AVX) 2467 .Case("sse4.2", SSE42) 2468 .Case("sse4.1", SSE41) 2469 .Case("ssse3", SSSE3) 2470 .Case("sse3", SSE3) 2471 .Case("sse2", SSE2) 2472 .Case("sse", SSE1) 2473 .Default(NoSSE); 2474 SSELevel = std::max(SSELevel, Level); 2475 2476 MMX3DNowEnum ThreeDNowLevel = 2477 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2478 .Case("3dnowa", AMD3DNowAthlon) 2479 .Case("3dnow", AMD3DNow) 2480 .Case("mmx", MMX) 2481 .Default(NoMMX3DNow); 2482 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2483 2484 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2485 .Case("xop", XOP) 2486 .Case("fma4", FMA4) 2487 .Case("sse4a", SSE4A) 2488 .Default(NoXOP); 2489 XOPLevel = std::max(XOPLevel, XLevel); 2490 } 2491 2492 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2493 // Can't do this earlier because we need to be able to explicitly enable 2494 // popcnt and still disable sse4.2. 2495 if (!HasPOPCNT && SSELevel >= SSE42 && 2496 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2497 HasPOPCNT = true; 2498 Features.push_back("+popcnt"); 2499 } 2500 2501 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2502 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2503 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2504 HasPRFCHW = true; 2505 Features.push_back("+prfchw"); 2506 } 2507 2508 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2509 // matches the selected sse level. 2510 if (FPMath == FP_SSE && SSELevel < SSE1) { 2511 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2512 return false; 2513 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2514 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2515 return false; 2516 } 2517 2518 // Don't tell the backend if we're turning off mmx; it will end up disabling 2519 // SSE, which we don't want. 2520 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2521 // then enable MMX. 2522 std::vector<std::string>::iterator it; 2523 it = std::find(Features.begin(), Features.end(), "-mmx"); 2524 if (it != Features.end()) 2525 Features.erase(it); 2526 else if (SSELevel > NoSSE) 2527 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2528 return true; 2529 } 2530 2531 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2532 /// definitions for this particular subtarget. 2533 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2534 MacroBuilder &Builder) const { 2535 // Target identification. 2536 if (getTriple().getArch() == llvm::Triple::x86_64) { 2537 Builder.defineMacro("__amd64__"); 2538 Builder.defineMacro("__amd64"); 2539 Builder.defineMacro("__x86_64"); 2540 Builder.defineMacro("__x86_64__"); 2541 } else { 2542 DefineStd(Builder, "i386", Opts); 2543 } 2544 2545 // Subtarget options. 2546 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2547 // truly should be based on -mtune options. 2548 switch (CPU) { 2549 case CK_Generic: 2550 break; 2551 case CK_i386: 2552 // The rest are coming from the i386 define above. 2553 Builder.defineMacro("__tune_i386__"); 2554 break; 2555 case CK_i486: 2556 case CK_WinChipC6: 2557 case CK_WinChip2: 2558 case CK_C3: 2559 defineCPUMacros(Builder, "i486"); 2560 break; 2561 case CK_PentiumMMX: 2562 Builder.defineMacro("__pentium_mmx__"); 2563 Builder.defineMacro("__tune_pentium_mmx__"); 2564 // Fallthrough 2565 case CK_i586: 2566 case CK_Pentium: 2567 defineCPUMacros(Builder, "i586"); 2568 defineCPUMacros(Builder, "pentium"); 2569 break; 2570 case CK_Pentium3: 2571 case CK_Pentium3M: 2572 case CK_PentiumM: 2573 Builder.defineMacro("__tune_pentium3__"); 2574 // Fallthrough 2575 case CK_Pentium2: 2576 case CK_C3_2: 2577 Builder.defineMacro("__tune_pentium2__"); 2578 // Fallthrough 2579 case CK_PentiumPro: 2580 Builder.defineMacro("__tune_i686__"); 2581 Builder.defineMacro("__tune_pentiumpro__"); 2582 // Fallthrough 2583 case CK_i686: 2584 Builder.defineMacro("__i686"); 2585 Builder.defineMacro("__i686__"); 2586 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2587 Builder.defineMacro("__pentiumpro"); 2588 Builder.defineMacro("__pentiumpro__"); 2589 break; 2590 case CK_Pentium4: 2591 case CK_Pentium4M: 2592 defineCPUMacros(Builder, "pentium4"); 2593 break; 2594 case CK_Yonah: 2595 case CK_Prescott: 2596 case CK_Nocona: 2597 defineCPUMacros(Builder, "nocona"); 2598 break; 2599 case CK_Core2: 2600 case CK_Penryn: 2601 defineCPUMacros(Builder, "core2"); 2602 break; 2603 case CK_Atom: 2604 defineCPUMacros(Builder, "atom"); 2605 break; 2606 case CK_Silvermont: 2607 defineCPUMacros(Builder, "slm"); 2608 break; 2609 case CK_Corei7: 2610 case CK_Corei7AVX: 2611 case CK_CoreAVXi: 2612 case CK_CoreAVX2: 2613 defineCPUMacros(Builder, "corei7"); 2614 break; 2615 case CK_KNL: 2616 defineCPUMacros(Builder, "knl"); 2617 break; 2618 case CK_K6_2: 2619 Builder.defineMacro("__k6_2__"); 2620 Builder.defineMacro("__tune_k6_2__"); 2621 // Fallthrough 2622 case CK_K6_3: 2623 if (CPU != CK_K6_2) { // In case of fallthrough 2624 // FIXME: GCC may be enabling these in cases where some other k6 2625 // architecture is specified but -m3dnow is explicitly provided. The 2626 // exact semantics need to be determined and emulated here. 2627 Builder.defineMacro("__k6_3__"); 2628 Builder.defineMacro("__tune_k6_3__"); 2629 } 2630 // Fallthrough 2631 case CK_K6: 2632 defineCPUMacros(Builder, "k6"); 2633 break; 2634 case CK_Athlon: 2635 case CK_AthlonThunderbird: 2636 case CK_Athlon4: 2637 case CK_AthlonXP: 2638 case CK_AthlonMP: 2639 defineCPUMacros(Builder, "athlon"); 2640 if (SSELevel != NoSSE) { 2641 Builder.defineMacro("__athlon_sse__"); 2642 Builder.defineMacro("__tune_athlon_sse__"); 2643 } 2644 break; 2645 case CK_K8: 2646 case CK_K8SSE3: 2647 case CK_x86_64: 2648 case CK_Opteron: 2649 case CK_OpteronSSE3: 2650 case CK_Athlon64: 2651 case CK_Athlon64SSE3: 2652 case CK_AthlonFX: 2653 defineCPUMacros(Builder, "k8"); 2654 break; 2655 case CK_AMDFAM10: 2656 defineCPUMacros(Builder, "amdfam10"); 2657 break; 2658 case CK_BTVER1: 2659 defineCPUMacros(Builder, "btver1"); 2660 break; 2661 case CK_BTVER2: 2662 defineCPUMacros(Builder, "btver2"); 2663 break; 2664 case CK_BDVER1: 2665 defineCPUMacros(Builder, "bdver1"); 2666 break; 2667 case CK_BDVER2: 2668 defineCPUMacros(Builder, "bdver2"); 2669 break; 2670 case CK_BDVER3: 2671 defineCPUMacros(Builder, "bdver3"); 2672 break; 2673 case CK_Geode: 2674 defineCPUMacros(Builder, "geode"); 2675 break; 2676 } 2677 2678 // Target properties. 2679 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2680 2681 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2682 // functions in glibc header files that use FP Stack inline asm which the 2683 // backend can't deal with (PR879). 2684 Builder.defineMacro("__NO_MATH_INLINES"); 2685 2686 if (HasAES) 2687 Builder.defineMacro("__AES__"); 2688 2689 if (HasPCLMUL) 2690 Builder.defineMacro("__PCLMUL__"); 2691 2692 if (HasLZCNT) 2693 Builder.defineMacro("__LZCNT__"); 2694 2695 if (HasRDRND) 2696 Builder.defineMacro("__RDRND__"); 2697 2698 if (HasBMI) 2699 Builder.defineMacro("__BMI__"); 2700 2701 if (HasBMI2) 2702 Builder.defineMacro("__BMI2__"); 2703 2704 if (HasPOPCNT) 2705 Builder.defineMacro("__POPCNT__"); 2706 2707 if (HasRTM) 2708 Builder.defineMacro("__RTM__"); 2709 2710 if (HasPRFCHW) 2711 Builder.defineMacro("__PRFCHW__"); 2712 2713 if (HasRDSEED) 2714 Builder.defineMacro("__RDSEED__"); 2715 2716 if (HasTBM) 2717 Builder.defineMacro("__TBM__"); 2718 2719 switch (XOPLevel) { 2720 case XOP: 2721 Builder.defineMacro("__XOP__"); 2722 case FMA4: 2723 Builder.defineMacro("__FMA4__"); 2724 case SSE4A: 2725 Builder.defineMacro("__SSE4A__"); 2726 case NoXOP: 2727 break; 2728 } 2729 2730 if (HasFMA) 2731 Builder.defineMacro("__FMA__"); 2732 2733 if (HasF16C) 2734 Builder.defineMacro("__F16C__"); 2735 2736 if (HasAVX512CD) 2737 Builder.defineMacro("__AVX512CD__"); 2738 if (HasAVX512ER) 2739 Builder.defineMacro("__AVX512ER__"); 2740 if (HasAVX512PF) 2741 Builder.defineMacro("__AVX512PF__"); 2742 2743 if (HasSHA) 2744 Builder.defineMacro("__SHA__"); 2745 2746 if (HasCX16) 2747 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2748 2749 // Each case falls through to the previous one here. 2750 switch (SSELevel) { 2751 case AVX512F: 2752 Builder.defineMacro("__AVX512F__"); 2753 case AVX2: 2754 Builder.defineMacro("__AVX2__"); 2755 case AVX: 2756 Builder.defineMacro("__AVX__"); 2757 case SSE42: 2758 Builder.defineMacro("__SSE4_2__"); 2759 case SSE41: 2760 Builder.defineMacro("__SSE4_1__"); 2761 case SSSE3: 2762 Builder.defineMacro("__SSSE3__"); 2763 case SSE3: 2764 Builder.defineMacro("__SSE3__"); 2765 case SSE2: 2766 Builder.defineMacro("__SSE2__"); 2767 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2768 case SSE1: 2769 Builder.defineMacro("__SSE__"); 2770 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2771 case NoSSE: 2772 break; 2773 } 2774 2775 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2776 switch (SSELevel) { 2777 case AVX512F: 2778 case AVX2: 2779 case AVX: 2780 case SSE42: 2781 case SSE41: 2782 case SSSE3: 2783 case SSE3: 2784 case SSE2: 2785 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2786 break; 2787 case SSE1: 2788 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2789 break; 2790 default: 2791 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2792 } 2793 } 2794 2795 // Each case falls through to the previous one here. 2796 switch (MMX3DNowLevel) { 2797 case AMD3DNowAthlon: 2798 Builder.defineMacro("__3dNOW_A__"); 2799 case AMD3DNow: 2800 Builder.defineMacro("__3dNOW__"); 2801 case MMX: 2802 Builder.defineMacro("__MMX__"); 2803 case NoMMX3DNow: 2804 break; 2805 } 2806 2807 if (CPU >= CK_i486) { 2808 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2809 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2810 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2811 } 2812 if (CPU >= CK_i586) 2813 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2814 } 2815 2816 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2817 return llvm::StringSwitch<bool>(Feature) 2818 .Case("aes", HasAES) 2819 .Case("avx", SSELevel >= AVX) 2820 .Case("avx2", SSELevel >= AVX2) 2821 .Case("avx512f", SSELevel >= AVX512F) 2822 .Case("avx512cd", HasAVX512CD) 2823 .Case("avx512er", HasAVX512ER) 2824 .Case("avx512pf", HasAVX512PF) 2825 .Case("bmi", HasBMI) 2826 .Case("bmi2", HasBMI2) 2827 .Case("cx16", HasCX16) 2828 .Case("f16c", HasF16C) 2829 .Case("fma", HasFMA) 2830 .Case("fma4", XOPLevel >= FMA4) 2831 .Case("tbm", HasTBM) 2832 .Case("lzcnt", HasLZCNT) 2833 .Case("rdrnd", HasRDRND) 2834 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2835 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2836 .Case("mmx", MMX3DNowLevel >= MMX) 2837 .Case("pclmul", HasPCLMUL) 2838 .Case("popcnt", HasPOPCNT) 2839 .Case("rtm", HasRTM) 2840 .Case("prfchw", HasPRFCHW) 2841 .Case("rdseed", HasRDSEED) 2842 .Case("sha", HasSHA) 2843 .Case("sse", SSELevel >= SSE1) 2844 .Case("sse2", SSELevel >= SSE2) 2845 .Case("sse3", SSELevel >= SSE3) 2846 .Case("ssse3", SSELevel >= SSSE3) 2847 .Case("sse4.1", SSELevel >= SSE41) 2848 .Case("sse4.2", SSELevel >= SSE42) 2849 .Case("sse4a", XOPLevel >= SSE4A) 2850 .Case("x86", true) 2851 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2852 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2853 .Case("xop", XOPLevel >= XOP) 2854 .Default(false); 2855 } 2856 2857 bool 2858 X86TargetInfo::validateAsmConstraint(const char *&Name, 2859 TargetInfo::ConstraintInfo &Info) const { 2860 switch (*Name) { 2861 default: return false; 2862 case 'Y': // first letter of a pair: 2863 switch (*(Name+1)) { 2864 default: return false; 2865 case '0': // First SSE register. 2866 case 't': // Any SSE register, when SSE2 is enabled. 2867 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2868 case 'm': // any MMX register, when inter-unit moves enabled. 2869 break; // falls through to setAllowsRegister. 2870 } 2871 case 'a': // eax. 2872 case 'b': // ebx. 2873 case 'c': // ecx. 2874 case 'd': // edx. 2875 case 'S': // esi. 2876 case 'D': // edi. 2877 case 'A': // edx:eax. 2878 case 'f': // any x87 floating point stack register. 2879 case 't': // top of floating point stack. 2880 case 'u': // second from top of floating point stack. 2881 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2882 case 'y': // Any MMX register. 2883 case 'x': // Any SSE register. 2884 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2885 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2886 case 'l': // "Index" registers: any general register that can be used as an 2887 // index in a base+index memory access. 2888 Info.setAllowsRegister(); 2889 return true; 2890 case 'C': // SSE floating point constant. 2891 case 'G': // x87 floating point constant. 2892 case 'e': // 32-bit signed integer constant for use with zero-extending 2893 // x86_64 instructions. 2894 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2895 // x86_64 instructions. 2896 return true; 2897 } 2898 } 2899 2900 2901 std::string 2902 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2903 switch (*Constraint) { 2904 case 'a': return std::string("{ax}"); 2905 case 'b': return std::string("{bx}"); 2906 case 'c': return std::string("{cx}"); 2907 case 'd': return std::string("{dx}"); 2908 case 'S': return std::string("{si}"); 2909 case 'D': return std::string("{di}"); 2910 case 'p': // address 2911 return std::string("im"); 2912 case 't': // top of floating point stack. 2913 return std::string("{st}"); 2914 case 'u': // second from top of floating point stack. 2915 return std::string("{st(1)}"); // second from top of floating point stack. 2916 default: 2917 return std::string(1, *Constraint); 2918 } 2919 } 2920 } // end anonymous namespace 2921 2922 namespace { 2923 // X86-32 generic target 2924 class X86_32TargetInfo : public X86TargetInfo { 2925 public: 2926 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2927 DoubleAlign = LongLongAlign = 32; 2928 LongDoubleWidth = 96; 2929 LongDoubleAlign = 32; 2930 SuitableAlign = 128; 2931 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2932 SizeType = UnsignedInt; 2933 PtrDiffType = SignedInt; 2934 IntPtrType = SignedInt; 2935 RegParmMax = 3; 2936 2937 // Use fpret for all types. 2938 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2939 (1 << TargetInfo::Double) | 2940 (1 << TargetInfo::LongDouble)); 2941 2942 // x86-32 has atomics up to 8 bytes 2943 // FIXME: Check that we actually have cmpxchg8b before setting 2944 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2945 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2946 } 2947 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2948 return TargetInfo::CharPtrBuiltinVaList; 2949 } 2950 2951 int getEHDataRegisterNumber(unsigned RegNo) const { 2952 if (RegNo == 0) return 0; 2953 if (RegNo == 1) return 2; 2954 return -1; 2955 } 2956 virtual bool validateInputSize(StringRef Constraint, 2957 unsigned Size) const { 2958 switch (Constraint[0]) { 2959 default: break; 2960 case 'a': 2961 case 'b': 2962 case 'c': 2963 case 'd': 2964 return Size <= 32; 2965 } 2966 2967 return true; 2968 } 2969 }; 2970 } // end anonymous namespace 2971 2972 namespace { 2973 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2974 public: 2975 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2976 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2977 2978 virtual unsigned getFloatEvalMethod() const { 2979 unsigned Major, Minor, Micro; 2980 getTriple().getOSVersion(Major, Minor, Micro); 2981 // New NetBSD uses the default rounding mode. 2982 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2983 return X86_32TargetInfo::getFloatEvalMethod(); 2984 // NetBSD before 6.99.26 defaults to "double" rounding. 2985 return 1; 2986 } 2987 }; 2988 } // end anonymous namespace 2989 2990 namespace { 2991 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2992 public: 2993 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 2994 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 2995 SizeType = UnsignedLong; 2996 IntPtrType = SignedLong; 2997 PtrDiffType = SignedLong; 2998 } 2999 }; 3000 } // end anonymous namespace 3001 3002 namespace { 3003 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3004 public: 3005 BitrigI386TargetInfo(const llvm::Triple &Triple) 3006 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3007 SizeType = UnsignedLong; 3008 IntPtrType = SignedLong; 3009 PtrDiffType = SignedLong; 3010 } 3011 }; 3012 } // end anonymous namespace 3013 3014 namespace { 3015 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3016 public: 3017 DarwinI386TargetInfo(const llvm::Triple &Triple) 3018 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3019 LongDoubleWidth = 128; 3020 LongDoubleAlign = 128; 3021 SuitableAlign = 128; 3022 MaxVectorAlign = 256; 3023 SizeType = UnsignedLong; 3024 IntPtrType = SignedLong; 3025 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3026 HasAlignMac68kSupport = true; 3027 } 3028 3029 }; 3030 } // end anonymous namespace 3031 3032 namespace { 3033 // x86-32 Windows target 3034 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3035 public: 3036 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3037 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3038 TLSSupported = false; 3039 WCharType = UnsignedShort; 3040 DoubleAlign = LongLongAlign = 64; 3041 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3042 } 3043 virtual void getTargetDefines(const LangOptions &Opts, 3044 MacroBuilder &Builder) const { 3045 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3046 } 3047 }; 3048 } // end anonymous namespace 3049 3050 namespace { 3051 3052 // x86-32 Windows Visual Studio target 3053 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3054 public: 3055 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3056 : WindowsX86_32TargetInfo(Triple) { 3057 LongDoubleWidth = LongDoubleAlign = 64; 3058 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3059 } 3060 virtual void getTargetDefines(const LangOptions &Opts, 3061 MacroBuilder &Builder) const { 3062 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3063 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3064 // The value of the following reflects processor type. 3065 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3066 // We lost the original triple, so we use the default. 3067 Builder.defineMacro("_M_IX86", "600"); 3068 } 3069 }; 3070 } // end anonymous namespace 3071 3072 namespace { 3073 // x86-32 MinGW target 3074 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3075 public: 3076 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3077 : WindowsX86_32TargetInfo(Triple) {} 3078 virtual void getTargetDefines(const LangOptions &Opts, 3079 MacroBuilder &Builder) const { 3080 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3081 DefineStd(Builder, "WIN32", Opts); 3082 DefineStd(Builder, "WINNT", Opts); 3083 Builder.defineMacro("_X86_"); 3084 Builder.defineMacro("__MSVCRT__"); 3085 Builder.defineMacro("__MINGW32__"); 3086 3087 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3088 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3089 if (Opts.MicrosoftExt) 3090 // Provide "as-is" __declspec. 3091 Builder.defineMacro("__declspec", "__declspec"); 3092 else 3093 // Provide alias of __attribute__ like mingw32-gcc. 3094 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3095 } 3096 }; 3097 } // end anonymous namespace 3098 3099 namespace { 3100 // x86-32 Cygwin target 3101 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3102 public: 3103 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3104 : X86_32TargetInfo(Triple) { 3105 TLSSupported = false; 3106 WCharType = UnsignedShort; 3107 DoubleAlign = LongLongAlign = 64; 3108 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3109 } 3110 virtual void getTargetDefines(const LangOptions &Opts, 3111 MacroBuilder &Builder) const { 3112 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3113 Builder.defineMacro("_X86_"); 3114 Builder.defineMacro("__CYGWIN__"); 3115 Builder.defineMacro("__CYGWIN32__"); 3116 DefineStd(Builder, "unix", Opts); 3117 if (Opts.CPlusPlus) 3118 Builder.defineMacro("_GNU_SOURCE"); 3119 } 3120 }; 3121 } // end anonymous namespace 3122 3123 namespace { 3124 // x86-32 Haiku target 3125 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3126 public: 3127 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3128 SizeType = UnsignedLong; 3129 IntPtrType = SignedLong; 3130 PtrDiffType = SignedLong; 3131 ProcessIDType = SignedLong; 3132 this->UserLabelPrefix = ""; 3133 this->TLSSupported = false; 3134 } 3135 virtual void getTargetDefines(const LangOptions &Opts, 3136 MacroBuilder &Builder) const { 3137 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3138 Builder.defineMacro("__INTEL__"); 3139 Builder.defineMacro("__HAIKU__"); 3140 } 3141 }; 3142 } // end anonymous namespace 3143 3144 // RTEMS Target 3145 template<typename Target> 3146 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3147 protected: 3148 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3149 MacroBuilder &Builder) const { 3150 // RTEMS defines; list based off of gcc output 3151 3152 Builder.defineMacro("__rtems__"); 3153 Builder.defineMacro("__ELF__"); 3154 } 3155 3156 public: 3157 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3158 this->UserLabelPrefix = ""; 3159 3160 switch (Triple.getArch()) { 3161 default: 3162 case llvm::Triple::x86: 3163 // this->MCountName = ".mcount"; 3164 break; 3165 case llvm::Triple::mips: 3166 case llvm::Triple::mipsel: 3167 case llvm::Triple::ppc: 3168 case llvm::Triple::ppc64: 3169 case llvm::Triple::ppc64le: 3170 // this->MCountName = "_mcount"; 3171 break; 3172 case llvm::Triple::arm: 3173 // this->MCountName = "__mcount"; 3174 break; 3175 } 3176 } 3177 }; 3178 3179 namespace { 3180 // x86-32 RTEMS target 3181 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3182 public: 3183 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3184 SizeType = UnsignedLong; 3185 IntPtrType = SignedLong; 3186 PtrDiffType = SignedLong; 3187 this->UserLabelPrefix = ""; 3188 } 3189 virtual void getTargetDefines(const LangOptions &Opts, 3190 MacroBuilder &Builder) const { 3191 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3192 Builder.defineMacro("__INTEL__"); 3193 Builder.defineMacro("__rtems__"); 3194 } 3195 }; 3196 } // end anonymous namespace 3197 3198 namespace { 3199 // x86-64 generic target 3200 class X86_64TargetInfo : public X86TargetInfo { 3201 public: 3202 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3203 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3204 LongDoubleWidth = 128; 3205 LongDoubleAlign = 128; 3206 LargeArrayMinWidth = 128; 3207 LargeArrayAlign = 128; 3208 SuitableAlign = 128; 3209 IntMaxType = SignedLong; 3210 UIntMaxType = UnsignedLong; 3211 Int64Type = SignedLong; 3212 RegParmMax = 6; 3213 3214 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3215 3216 // Use fpret only for long double. 3217 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3218 3219 // Use fp2ret for _Complex long double. 3220 ComplexLongDoubleUsesFP2Ret = true; 3221 3222 // x86-64 has atomics up to 16 bytes. 3223 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3224 // on CPUs with cmpxchg16b 3225 MaxAtomicPromoteWidth = 128; 3226 MaxAtomicInlineWidth = 64; 3227 } 3228 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3229 return TargetInfo::X86_64ABIBuiltinVaList; 3230 } 3231 3232 int getEHDataRegisterNumber(unsigned RegNo) const { 3233 if (RegNo == 0) return 0; 3234 if (RegNo == 1) return 1; 3235 return -1; 3236 } 3237 3238 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3239 return (CC == CC_C || 3240 CC == CC_IntelOclBicc || 3241 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3242 } 3243 3244 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3245 return CC_C; 3246 } 3247 3248 }; 3249 } // end anonymous namespace 3250 3251 namespace { 3252 // x86-64 Windows target 3253 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3254 public: 3255 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3256 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3257 TLSSupported = false; 3258 WCharType = UnsignedShort; 3259 LongWidth = LongAlign = 32; 3260 DoubleAlign = LongLongAlign = 64; 3261 IntMaxType = SignedLongLong; 3262 UIntMaxType = UnsignedLongLong; 3263 Int64Type = SignedLongLong; 3264 SizeType = UnsignedLongLong; 3265 PtrDiffType = SignedLongLong; 3266 IntPtrType = SignedLongLong; 3267 this->UserLabelPrefix = ""; 3268 } 3269 virtual void getTargetDefines(const LangOptions &Opts, 3270 MacroBuilder &Builder) const { 3271 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3272 Builder.defineMacro("_WIN64"); 3273 } 3274 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3275 return TargetInfo::CharPtrBuiltinVaList; 3276 } 3277 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3278 return (CC == CC_C || 3279 CC == CC_IntelOclBicc || 3280 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3281 } 3282 }; 3283 } // end anonymous namespace 3284 3285 namespace { 3286 // x86-64 Windows Visual Studio target 3287 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3288 public: 3289 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3290 : WindowsX86_64TargetInfo(Triple) { 3291 LongDoubleWidth = LongDoubleAlign = 64; 3292 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3293 } 3294 virtual void getTargetDefines(const LangOptions &Opts, 3295 MacroBuilder &Builder) const { 3296 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3297 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3298 Builder.defineMacro("_M_X64"); 3299 Builder.defineMacro("_M_AMD64"); 3300 } 3301 }; 3302 } // end anonymous namespace 3303 3304 namespace { 3305 // x86-64 MinGW target 3306 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3307 public: 3308 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3309 : WindowsX86_64TargetInfo(Triple) {} 3310 virtual void getTargetDefines(const LangOptions &Opts, 3311 MacroBuilder &Builder) const { 3312 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3313 DefineStd(Builder, "WIN64", Opts); 3314 Builder.defineMacro("__MSVCRT__"); 3315 Builder.defineMacro("__MINGW32__"); 3316 Builder.defineMacro("__MINGW64__"); 3317 3318 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3319 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3320 if (Opts.MicrosoftExt) 3321 // Provide "as-is" __declspec. 3322 Builder.defineMacro("__declspec", "__declspec"); 3323 else 3324 // Provide alias of __attribute__ like mingw32-gcc. 3325 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3326 } 3327 }; 3328 } // end anonymous namespace 3329 3330 namespace { 3331 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3332 public: 3333 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3334 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3335 Int64Type = SignedLongLong; 3336 MaxVectorAlign = 256; 3337 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3338 } 3339 }; 3340 } // end anonymous namespace 3341 3342 namespace { 3343 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3344 public: 3345 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3346 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3347 IntMaxType = SignedLongLong; 3348 UIntMaxType = UnsignedLongLong; 3349 Int64Type = SignedLongLong; 3350 } 3351 }; 3352 } // end anonymous namespace 3353 3354 namespace { 3355 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3356 public: 3357 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3358 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3359 IntMaxType = SignedLongLong; 3360 UIntMaxType = UnsignedLongLong; 3361 Int64Type = SignedLongLong; 3362 } 3363 }; 3364 } 3365 3366 namespace { 3367 class AArch64TargetInfo : public TargetInfo { 3368 virtual void setDescriptionString() = 0; 3369 static const char * const GCCRegNames[]; 3370 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3371 3372 enum FPUModeEnum { 3373 FPUMode, 3374 NeonMode 3375 }; 3376 3377 unsigned FPU; 3378 unsigned Crypto; 3379 static const Builtin::Info BuiltinInfo[]; 3380 3381 public: 3382 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3383 IntMaxType = SignedLong; 3384 UIntMaxType = UnsignedLong; 3385 Int64Type = SignedLong; 3386 LongWidth = LongAlign = 64; 3387 LongDoubleWidth = LongDoubleAlign = 128; 3388 PointerWidth = PointerAlign = 64; 3389 SuitableAlign = 128; 3390 3391 WCharType = UnsignedInt; 3392 if (getTriple().getOS() == llvm::Triple::NetBSD) 3393 WCharType = SignedInt; 3394 else 3395 WCharType = UnsignedInt; 3396 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3397 3398 // AArch64 backend supports 64-bit operations at the moment. In principle 3399 // 128-bit is possible if register-pairs are used. 3400 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3401 3402 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3403 } 3404 virtual void getTargetDefines(const LangOptions &Opts, 3405 MacroBuilder &Builder) const { 3406 // GCC defines theses currently 3407 Builder.defineMacro("__aarch64__"); 3408 3409 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3410 Builder.defineMacro("__ARM_ACLE", "200"); 3411 Builder.defineMacro("__ARM_ARCH", "8"); 3412 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3413 3414 Builder.defineMacro("__ARM_64BIT_STATE"); 3415 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3416 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3417 3418 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3419 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3420 Builder.defineMacro("__ARM_FEATURE_FMA"); 3421 Builder.defineMacro("__ARM_FEATURE_DIV"); 3422 3423 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3424 3425 // 0xe implies support for half, single and double precision operations. 3426 Builder.defineMacro("__ARM_FP", "0xe"); 3427 3428 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3429 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3430 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3431 3432 if (Opts.FastMath || Opts.FiniteMathOnly) 3433 Builder.defineMacro("__ARM_FP_FAST"); 3434 3435 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3436 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3437 3438 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3439 Opts.ShortWChar ? "2" : "4"); 3440 3441 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3442 Opts.ShortEnums ? "1" : "4"); 3443 3444 if (BigEndian) 3445 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3446 3447 if (FPU == NeonMode) { 3448 Builder.defineMacro("__ARM_NEON"); 3449 // 64-bit NEON supports half, single and double precision operations. 3450 Builder.defineMacro("__ARM_NEON_FP", "7"); 3451 } 3452 3453 if (Crypto) { 3454 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3455 } 3456 } 3457 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3458 unsigned &NumRecords) const { 3459 Records = BuiltinInfo; 3460 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3461 } 3462 virtual bool hasFeature(StringRef Feature) const { 3463 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3464 } 3465 3466 virtual bool setCPU(const std::string &Name) { 3467 return llvm::StringSwitch<bool>(Name) 3468 .Case("generic", true) 3469 .Cases("cortex-a53", "cortex-a57", true) 3470 .Default(false); 3471 } 3472 3473 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3474 DiagnosticsEngine &Diags) { 3475 FPU = FPUMode; 3476 Crypto = 0; 3477 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3478 if (Features[i] == "+neon") 3479 FPU = NeonMode; 3480 if (Features[i] == "+crypto") 3481 Crypto = 1; 3482 } 3483 3484 setDescriptionString(); 3485 3486 return true; 3487 } 3488 3489 virtual void getGCCRegNames(const char *const *&Names, 3490 unsigned &NumNames) const; 3491 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3492 unsigned &NumAliases) const; 3493 3494 virtual bool isCLZForZeroUndef() const { return false; } 3495 3496 virtual bool validateAsmConstraint(const char *&Name, 3497 TargetInfo::ConstraintInfo &Info) const { 3498 switch (*Name) { 3499 default: return false; 3500 case 'w': // An FP/SIMD vector register 3501 Info.setAllowsRegister(); 3502 return true; 3503 case 'I': // Constant that can be used with an ADD instruction 3504 case 'J': // Constant that can be used with a SUB instruction 3505 case 'K': // Constant that can be used with a 32-bit logical instruction 3506 case 'L': // Constant that can be used with a 64-bit logical instruction 3507 case 'M': // Constant that can be used as a 32-bit MOV immediate 3508 case 'N': // Constant that can be used as a 64-bit MOV immediate 3509 case 'Y': // Floating point constant zero 3510 case 'Z': // Integer constant zero 3511 return true; 3512 case 'Q': // A memory reference with base register and no offset 3513 Info.setAllowsMemory(); 3514 return true; 3515 case 'S': // A symbolic address 3516 Info.setAllowsRegister(); 3517 return true; 3518 case 'U': 3519 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3520 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3521 // Usa: An absolute symbolic address 3522 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3523 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3524 } 3525 } 3526 3527 virtual const char *getClobbers() const { 3528 // There are no AArch64 clobbers shared by all asm statements. 3529 return ""; 3530 } 3531 3532 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3533 return TargetInfo::AArch64ABIBuiltinVaList; 3534 } 3535 }; 3536 3537 const char * const AArch64TargetInfo::GCCRegNames[] = { 3538 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3539 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3540 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3541 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3542 3543 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3544 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3545 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3546 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3547 3548 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3549 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3550 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3551 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3552 3553 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3554 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3555 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3556 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3557 3558 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3559 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3560 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3561 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3562 3563 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3564 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3565 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3566 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3567 3568 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3569 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3570 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3571 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3572 }; 3573 3574 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3575 unsigned &NumNames) const { 3576 Names = GCCRegNames; 3577 NumNames = llvm::array_lengthof(GCCRegNames); 3578 } 3579 3580 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3581 { { "x16" }, "ip0"}, 3582 { { "x17" }, "ip1"}, 3583 { { "x29" }, "fp" }, 3584 { { "x30" }, "lr" } 3585 }; 3586 3587 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3588 unsigned &NumAliases) const { 3589 Aliases = GCCRegAliases; 3590 NumAliases = llvm::array_lengthof(GCCRegAliases); 3591 3592 } 3593 3594 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3595 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3596 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3597 ALL_LANGUAGES }, 3598 #define GET_NEON_BUILTINS 3599 #include "clang/Basic/arm_neon.inc" 3600 #undef GET_NEON_BUILTINS 3601 3602 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3603 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3604 ALL_LANGUAGES }, 3605 #include "clang/Basic/BuiltinsAArch64.def" 3606 }; 3607 3608 class AArch64leTargetInfo : public AArch64TargetInfo { 3609 virtual void setDescriptionString() { 3610 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3611 } 3612 3613 public: 3614 AArch64leTargetInfo(const llvm::Triple &Triple) 3615 : AArch64TargetInfo(Triple) { 3616 BigEndian = false; 3617 } 3618 virtual void getTargetDefines(const LangOptions &Opts, 3619 MacroBuilder &Builder) const { 3620 Builder.defineMacro("__AARCH64EL__"); 3621 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3622 } 3623 }; 3624 3625 class AArch64beTargetInfo : public AArch64TargetInfo { 3626 virtual void setDescriptionString() { 3627 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3628 } 3629 3630 public: 3631 AArch64beTargetInfo(const llvm::Triple &Triple) 3632 : AArch64TargetInfo(Triple) { } 3633 virtual void getTargetDefines(const LangOptions &Opts, 3634 MacroBuilder &Builder) const { 3635 Builder.defineMacro("__AARCH64EB__"); 3636 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3637 } 3638 }; 3639 3640 } // end anonymous namespace 3641 3642 namespace { 3643 class ARMTargetInfo : public TargetInfo { 3644 // Possible FPU choices. 3645 enum FPUMode { 3646 VFP2FPU = (1 << 0), 3647 VFP3FPU = (1 << 1), 3648 VFP4FPU = (1 << 2), 3649 NeonFPU = (1 << 3), 3650 FPARMV8 = (1 << 4) 3651 }; 3652 3653 // Possible HWDiv features. 3654 enum HWDivMode { 3655 HWDivThumb = (1 << 0), 3656 HWDivARM = (1 << 1) 3657 }; 3658 3659 static bool FPUModeIsVFP(FPUMode Mode) { 3660 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3661 } 3662 3663 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3664 static const char * const GCCRegNames[]; 3665 3666 std::string ABI, CPU; 3667 3668 enum { 3669 FP_Default, 3670 FP_VFP, 3671 FP_Neon 3672 } FPMath; 3673 3674 unsigned FPU : 5; 3675 3676 unsigned IsAAPCS : 1; 3677 unsigned IsThumb : 1; 3678 unsigned HWDiv : 2; 3679 3680 // Initialized via features. 3681 unsigned SoftFloat : 1; 3682 unsigned SoftFloatABI : 1; 3683 3684 unsigned CRC : 1; 3685 unsigned Crypto : 1; 3686 3687 static const Builtin::Info BuiltinInfo[]; 3688 3689 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3690 // On linux, binaries targeting old cpus call functions in libgcc to 3691 // perform atomic operations. The implementation in libgcc then calls into 3692 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3693 // is that if we assume the kernel is at least as recent as the hardware, 3694 // it is safe to use atomic instructions on armv6 and newer. 3695 if (!T.isOSLinux() && 3696 T.getOS() != llvm::Triple::FreeBSD && 3697 T.getOS() != llvm::Triple::NetBSD && 3698 T.getOS() != llvm::Triple::Bitrig) 3699 return false; 3700 StringRef ArchName = T.getArchName(); 3701 if (T.getArch() == llvm::Triple::arm) { 3702 if (!ArchName.startswith("armv")) 3703 return false; 3704 StringRef VersionStr = ArchName.substr(4); 3705 unsigned Version; 3706 if (VersionStr.getAsInteger(10, Version)) 3707 return false; 3708 return Version >= 6; 3709 } 3710 assert(T.getArch() == llvm::Triple::thumb); 3711 if (!ArchName.startswith("thumbv")) 3712 return false; 3713 StringRef VersionStr = ArchName.substr(6); 3714 unsigned Version; 3715 if (VersionStr.getAsInteger(10, Version)) 3716 return false; 3717 return Version >= 7; 3718 } 3719 3720 void setABIAAPCS() { 3721 IsAAPCS = true; 3722 3723 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3724 const llvm::Triple &T = getTriple(); 3725 3726 // size_t is unsigned long on Darwin and NetBSD. 3727 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3728 SizeType = UnsignedLong; 3729 else 3730 SizeType = UnsignedInt; 3731 3732 if (T.getOS() == llvm::Triple::NetBSD) { 3733 WCharType = SignedInt; 3734 } else { 3735 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3736 WCharType = UnsignedInt; 3737 } 3738 3739 UseBitFieldTypeAlignment = true; 3740 3741 ZeroLengthBitfieldBoundary = 0; 3742 3743 if (IsThumb) { 3744 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3745 // so set preferred for small types to 32. 3746 if (T.isOSBinFormatMachO()) 3747 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3748 "v128:64:128-a:0:32-n32-S64"; 3749 else 3750 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3751 "v128:64:128-a:0:32-n32-S64"; 3752 3753 } else { 3754 if (T.isOSBinFormatMachO()) 3755 DescriptionString = "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3756 else 3757 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3758 } 3759 3760 // FIXME: Enumerated types are variable width in straight AAPCS. 3761 } 3762 3763 void setABIAPCS() { 3764 const llvm::Triple &T = getTriple(); 3765 3766 IsAAPCS = false; 3767 3768 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3769 3770 // size_t is unsigned int on FreeBSD. 3771 if (T.getOS() == llvm::Triple::FreeBSD) 3772 SizeType = UnsignedInt; 3773 else 3774 SizeType = UnsignedLong; 3775 3776 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3777 WCharType = SignedInt; 3778 3779 // Do not respect the alignment of bit-field types when laying out 3780 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3781 UseBitFieldTypeAlignment = false; 3782 3783 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3784 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3785 /// gcc. 3786 ZeroLengthBitfieldBoundary = 32; 3787 3788 if (IsThumb) { 3789 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3790 // so set preferred for small types to 32. 3791 if (T.isOSBinFormatMachO()) 3792 DescriptionString = "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3793 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3794 else 3795 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3796 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3797 } else { 3798 if (T.isOSBinFormatMachO()) 3799 DescriptionString = 3800 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3801 else 3802 DescriptionString = 3803 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3804 } 3805 3806 // FIXME: Override "preferred align" for double and long long. 3807 } 3808 3809 public: 3810 ARMTargetInfo(const llvm::Triple &Triple) 3811 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3812 IsAAPCS(true) { 3813 BigEndian = false; 3814 switch (getTriple().getOS()) { 3815 case llvm::Triple::NetBSD: 3816 PtrDiffType = SignedLong; 3817 break; 3818 default: 3819 PtrDiffType = SignedInt; 3820 break; 3821 } 3822 3823 // {} in inline assembly are neon specifiers, not assembly variant 3824 // specifiers. 3825 NoAsmVariants = true; 3826 3827 // FIXME: Should we just treat this as a feature? 3828 IsThumb = getTriple().getArchName().startswith("thumb"); 3829 3830 setABI("aapcs-linux"); 3831 3832 // ARM targets default to using the ARM C++ ABI. 3833 TheCXXABI.set(TargetCXXABI::GenericARM); 3834 3835 // ARM has atomics up to 8 bytes 3836 MaxAtomicPromoteWidth = 64; 3837 if (shouldUseInlineAtomic(getTriple())) 3838 MaxAtomicInlineWidth = 64; 3839 3840 // Do force alignment of members that follow zero length bitfields. If 3841 // the alignment of the zero-length bitfield is greater than the member 3842 // that follows it, `bar', `bar' will be aligned as the type of the 3843 // zero length bitfield. 3844 UseZeroLengthBitfieldAlignment = true; 3845 } 3846 virtual const char *getABI() const { return ABI.c_str(); } 3847 virtual bool setABI(const std::string &Name) { 3848 ABI = Name; 3849 3850 // The defaults (above) are for AAPCS, check if we need to change them. 3851 // 3852 // FIXME: We need support for -meabi... we could just mangle it into the 3853 // name. 3854 if (Name == "apcs-gnu") { 3855 setABIAPCS(); 3856 return true; 3857 } 3858 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3859 setABIAAPCS(); 3860 return true; 3861 } 3862 return false; 3863 } 3864 3865 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3866 if (IsAAPCS) 3867 Features["aapcs"] = true; 3868 else 3869 Features["apcs"] = true; 3870 3871 StringRef ArchName = getTriple().getArchName(); 3872 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3873 Features["vfp2"] = true; 3874 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3875 CPU == "cortex-a9-mp") { 3876 Features["vfp3"] = true; 3877 Features["neon"] = true; 3878 } 3879 else if (CPU == "cortex-a5") { 3880 Features["vfp4"] = true; 3881 Features["neon"] = true; 3882 } else if (CPU == "swift" || CPU == "cortex-a7" || 3883 CPU == "cortex-a12" || CPU == "cortex-a15" || 3884 CPU == "krait") { 3885 Features["vfp4"] = true; 3886 Features["neon"] = true; 3887 Features["hwdiv"] = true; 3888 Features["hwdiv-arm"] = true; 3889 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3890 Features["fp-armv8"] = true; 3891 Features["neon"] = true; 3892 Features["hwdiv"] = true; 3893 Features["hwdiv-arm"] = true; 3894 Features["crc"] = true; 3895 Features["crypto"] = true; 3896 } else if (CPU == "cortex-r5" || 3897 // Enable the hwdiv extension for all v8a AArch32 cores by 3898 // default. 3899 ArchName == "armv8a" || ArchName == "armv8" || 3900 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3901 Features["hwdiv"] = true; 3902 Features["hwdiv-arm"] = true; 3903 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3904 Features["hwdiv"] = true; 3905 } 3906 } 3907 3908 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3909 DiagnosticsEngine &Diags) { 3910 FPU = 0; 3911 CRC = 0; 3912 Crypto = 0; 3913 SoftFloat = SoftFloatABI = false; 3914 HWDiv = 0; 3915 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3916 if (Features[i] == "+soft-float") 3917 SoftFloat = true; 3918 else if (Features[i] == "+soft-float-abi") 3919 SoftFloatABI = true; 3920 else if (Features[i] == "+vfp2") 3921 FPU |= VFP2FPU; 3922 else if (Features[i] == "+vfp3") 3923 FPU |= VFP3FPU; 3924 else if (Features[i] == "+vfp4") 3925 FPU |= VFP4FPU; 3926 else if (Features[i] == "+fp-armv8") 3927 FPU |= FPARMV8; 3928 else if (Features[i] == "+neon") 3929 FPU |= NeonFPU; 3930 else if (Features[i] == "+hwdiv") 3931 HWDiv |= HWDivThumb; 3932 else if (Features[i] == "+hwdiv-arm") 3933 HWDiv |= HWDivARM; 3934 else if (Features[i] == "+crc") 3935 CRC = 1; 3936 else if (Features[i] == "+crypto") 3937 Crypto = 1; 3938 } 3939 3940 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3941 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3942 return false; 3943 } 3944 3945 if (FPMath == FP_Neon) 3946 Features.push_back("+neonfp"); 3947 else if (FPMath == FP_VFP) 3948 Features.push_back("-neonfp"); 3949 3950 // Remove front-end specific options which the backend handles differently. 3951 std::vector<std::string>::iterator it; 3952 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3953 if (it != Features.end()) 3954 Features.erase(it); 3955 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3956 if (it != Features.end()) 3957 Features.erase(it); 3958 return true; 3959 } 3960 3961 virtual bool hasFeature(StringRef Feature) const { 3962 return llvm::StringSwitch<bool>(Feature) 3963 .Case("arm", true) 3964 .Case("softfloat", SoftFloat) 3965 .Case("thumb", IsThumb) 3966 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3967 .Case("hwdiv", HWDiv & HWDivThumb) 3968 .Case("hwdiv-arm", HWDiv & HWDivARM) 3969 .Default(false); 3970 } 3971 // FIXME: Should we actually have some table instead of these switches? 3972 static const char *getCPUDefineSuffix(StringRef Name) { 3973 return llvm::StringSwitch<const char*>(Name) 3974 .Cases("arm8", "arm810", "4") 3975 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3976 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3977 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3978 .Case("ep9312", "4T") 3979 .Cases("arm10tdmi", "arm1020t", "5T") 3980 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3981 .Case("arm926ej-s", "5TEJ") 3982 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3983 .Cases("xscale", "iwmmxt", "5TE") 3984 .Case("arm1136j-s", "6J") 3985 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3986 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3987 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3988 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 3989 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 3990 .Cases("cortex-r4", "cortex-r5", "7R") 3991 .Case("swift", "7S") 3992 .Cases("cortex-m3", "cortex-m4", "7M") 3993 .Case("cortex-m0", "6M") 3994 .Cases("cortex-a53", "cortex-a57", "8A") 3995 .Default(0); 3996 } 3997 static const char *getCPUProfile(StringRef Name) { 3998 return llvm::StringSwitch<const char*>(Name) 3999 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4000 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4001 .Cases("cortex-a53", "cortex-a57", "A") 4002 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4003 .Cases("cortex-r4", "cortex-r5", "R") 4004 .Default(""); 4005 } 4006 virtual bool setCPU(const std::string &Name) { 4007 if (!getCPUDefineSuffix(Name)) 4008 return false; 4009 4010 CPU = Name; 4011 return true; 4012 } 4013 virtual bool setFPMath(StringRef Name); 4014 virtual void getTargetDefines(const LangOptions &Opts, 4015 MacroBuilder &Builder) const { 4016 // Target identification. 4017 Builder.defineMacro("__arm"); 4018 Builder.defineMacro("__arm__"); 4019 4020 // Target properties. 4021 Builder.defineMacro("__ARMEL__"); 4022 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4023 4024 StringRef CPUArch = getCPUDefineSuffix(CPU); 4025 unsigned int CPUArchVer; 4026 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4027 llvm_unreachable("Invalid char for architecture version number"); 4028 } 4029 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4030 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4031 StringRef CPUProfile = getCPUProfile(CPU); 4032 if (!CPUProfile.empty()) 4033 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4034 4035 // Subtarget options. 4036 4037 // FIXME: It's more complicated than this and we don't really support 4038 // interworking. 4039 if (5 <= CPUArchVer && CPUArchVer <= 8) 4040 Builder.defineMacro("__THUMB_INTERWORK__"); 4041 4042 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4043 // Embedded targets on Darwin follow AAPCS, but not EABI. 4044 if (!getTriple().isOSDarwin()) 4045 Builder.defineMacro("__ARM_EABI__"); 4046 Builder.defineMacro("__ARM_PCS", "1"); 4047 4048 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4049 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4050 } 4051 4052 if (SoftFloat) 4053 Builder.defineMacro("__SOFTFP__"); 4054 4055 if (CPU == "xscale") 4056 Builder.defineMacro("__XSCALE__"); 4057 4058 if (IsThumb) { 4059 Builder.defineMacro("__THUMBEL__"); 4060 Builder.defineMacro("__thumb__"); 4061 // We check both CPUArchVer and ArchName because when only triple is 4062 // specified, the default CPU is arm1136j-s. 4063 StringRef ArchName = getTriple().getArchName(); 4064 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4065 ArchName.endswith("v7") || ArchName.endswith("v8")) 4066 Builder.defineMacro("__thumb2__"); 4067 } 4068 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4069 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4070 4071 // Note, this is always on in gcc, even though it doesn't make sense. 4072 Builder.defineMacro("__APCS_32__"); 4073 4074 if (FPUModeIsVFP((FPUMode) FPU)) { 4075 Builder.defineMacro("__VFP_FP__"); 4076 if (FPU & VFP2FPU) 4077 Builder.defineMacro("__ARM_VFPV2__"); 4078 if (FPU & VFP3FPU) 4079 Builder.defineMacro("__ARM_VFPV3__"); 4080 if (FPU & VFP4FPU) 4081 Builder.defineMacro("__ARM_VFPV4__"); 4082 } 4083 4084 // This only gets set when Neon instructions are actually available, unlike 4085 // the VFP define, hence the soft float and arch check. This is subtly 4086 // different from gcc, we follow the intent which was that it should be set 4087 // when Neon instructions are actually available. 4088 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4089 Builder.defineMacro("__ARM_NEON"); 4090 Builder.defineMacro("__ARM_NEON__"); 4091 } 4092 4093 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4094 Opts.ShortWChar ? "2" : "4"); 4095 4096 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4097 Opts.ShortEnums ? "1" : "4"); 4098 4099 if (CRC) 4100 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4101 4102 if (Crypto) 4103 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4104 4105 if (CPUArchVer >= 6 && CPUArch != "6M") { 4106 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4107 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4108 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4109 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4110 } 4111 } 4112 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4113 unsigned &NumRecords) const { 4114 Records = BuiltinInfo; 4115 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4116 } 4117 virtual bool isCLZForZeroUndef() const { return false; } 4118 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4119 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4120 } 4121 virtual void getGCCRegNames(const char * const *&Names, 4122 unsigned &NumNames) const; 4123 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4124 unsigned &NumAliases) const; 4125 virtual bool validateAsmConstraint(const char *&Name, 4126 TargetInfo::ConstraintInfo &Info) const { 4127 switch (*Name) { 4128 default: break; 4129 case 'l': // r0-r7 4130 case 'h': // r8-r15 4131 case 'w': // VFP Floating point register single precision 4132 case 'P': // VFP Floating point register double precision 4133 Info.setAllowsRegister(); 4134 return true; 4135 case 'Q': // A memory address that is a single base register. 4136 Info.setAllowsMemory(); 4137 return true; 4138 case 'U': // a memory reference... 4139 switch (Name[1]) { 4140 case 'q': // ...ARMV4 ldrsb 4141 case 'v': // ...VFP load/store (reg+constant offset) 4142 case 'y': // ...iWMMXt load/store 4143 case 't': // address valid for load/store opaque types wider 4144 // than 128-bits 4145 case 'n': // valid address for Neon doubleword vector load/store 4146 case 'm': // valid address for Neon element and structure load/store 4147 case 's': // valid address for non-offset loads/stores of quad-word 4148 // values in four ARM registers 4149 Info.setAllowsMemory(); 4150 Name++; 4151 return true; 4152 } 4153 } 4154 return false; 4155 } 4156 virtual std::string convertConstraint(const char *&Constraint) const { 4157 std::string R; 4158 switch (*Constraint) { 4159 case 'U': // Two-character constraint; add "^" hint for later parsing. 4160 R = std::string("^") + std::string(Constraint, 2); 4161 Constraint++; 4162 break; 4163 case 'p': // 'p' should be translated to 'r' by default. 4164 R = std::string("r"); 4165 break; 4166 default: 4167 return std::string(1, *Constraint); 4168 } 4169 return R; 4170 } 4171 virtual bool validateConstraintModifier(StringRef Constraint, 4172 const char Modifier, 4173 unsigned Size) const { 4174 bool isOutput = (Constraint[0] == '='); 4175 bool isInOut = (Constraint[0] == '+'); 4176 4177 // Strip off constraint modifiers. 4178 while (Constraint[0] == '=' || 4179 Constraint[0] == '+' || 4180 Constraint[0] == '&') 4181 Constraint = Constraint.substr(1); 4182 4183 switch (Constraint[0]) { 4184 default: break; 4185 case 'r': { 4186 switch (Modifier) { 4187 default: 4188 return (isInOut || isOutput || Size <= 64); 4189 case 'q': 4190 // A register of size 32 cannot fit a vector type. 4191 return false; 4192 } 4193 } 4194 } 4195 4196 return true; 4197 } 4198 virtual const char *getClobbers() const { 4199 // FIXME: Is this really right? 4200 return ""; 4201 } 4202 4203 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4204 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4205 } 4206 4207 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4208 if (RegNo == 0) return 0; 4209 if (RegNo == 1) return 1; 4210 return -1; 4211 } 4212 }; 4213 4214 bool ARMTargetInfo::setFPMath(StringRef Name) { 4215 if (Name == "neon") { 4216 FPMath = FP_Neon; 4217 return true; 4218 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4219 Name == "vfp4") { 4220 FPMath = FP_VFP; 4221 return true; 4222 } 4223 return false; 4224 } 4225 4226 const char * const ARMTargetInfo::GCCRegNames[] = { 4227 // Integer registers 4228 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4229 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4230 4231 // Float registers 4232 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4233 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4234 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4235 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4236 4237 // Double registers 4238 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4239 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4240 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4241 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4242 4243 // Quad registers 4244 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4245 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4246 }; 4247 4248 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4249 unsigned &NumNames) const { 4250 Names = GCCRegNames; 4251 NumNames = llvm::array_lengthof(GCCRegNames); 4252 } 4253 4254 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4255 { { "a1" }, "r0" }, 4256 { { "a2" }, "r1" }, 4257 { { "a3" }, "r2" }, 4258 { { "a4" }, "r3" }, 4259 { { "v1" }, "r4" }, 4260 { { "v2" }, "r5" }, 4261 { { "v3" }, "r6" }, 4262 { { "v4" }, "r7" }, 4263 { { "v5" }, "r8" }, 4264 { { "v6", "rfp" }, "r9" }, 4265 { { "sl" }, "r10" }, 4266 { { "fp" }, "r11" }, 4267 { { "ip" }, "r12" }, 4268 { { "r13" }, "sp" }, 4269 { { "r14" }, "lr" }, 4270 { { "r15" }, "pc" }, 4271 // The S, D and Q registers overlap, but aren't really aliases; we 4272 // don't want to substitute one of these for a different-sized one. 4273 }; 4274 4275 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4276 unsigned &NumAliases) const { 4277 Aliases = GCCRegAliases; 4278 NumAliases = llvm::array_lengthof(GCCRegAliases); 4279 } 4280 4281 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4282 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4283 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4284 ALL_LANGUAGES }, 4285 #define GET_NEON_BUILTINS 4286 #include "clang/Basic/arm_neon.inc" 4287 #undef GET_NEON_BUILTINS 4288 4289 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4290 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4291 ALL_LANGUAGES }, 4292 #include "clang/Basic/BuiltinsARM.def" 4293 }; 4294 } // end anonymous namespace. 4295 4296 namespace { 4297 class DarwinARMTargetInfo : 4298 public DarwinTargetInfo<ARMTargetInfo> { 4299 protected: 4300 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4301 MacroBuilder &Builder) const { 4302 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4303 } 4304 4305 public: 4306 DarwinARMTargetInfo(const llvm::Triple &Triple) 4307 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4308 HasAlignMac68kSupport = true; 4309 // iOS always has 64-bit atomic instructions. 4310 // FIXME: This should be based off of the target features in ARMTargetInfo. 4311 MaxAtomicInlineWidth = 64; 4312 4313 // Darwin on iOS uses a variant of the ARM C++ ABI. 4314 TheCXXABI.set(TargetCXXABI::iOS); 4315 } 4316 }; 4317 } // end anonymous namespace. 4318 4319 4320 namespace { 4321 // Hexagon abstract base class 4322 class HexagonTargetInfo : public TargetInfo { 4323 static const Builtin::Info BuiltinInfo[]; 4324 static const char * const GCCRegNames[]; 4325 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4326 std::string CPU; 4327 public: 4328 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4329 BigEndian = false; 4330 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4331 4332 // {} in inline assembly are packet specifiers, not assembly variant 4333 // specifiers. 4334 NoAsmVariants = true; 4335 } 4336 4337 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4338 unsigned &NumRecords) const { 4339 Records = BuiltinInfo; 4340 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4341 } 4342 4343 virtual bool validateAsmConstraint(const char *&Name, 4344 TargetInfo::ConstraintInfo &Info) const { 4345 return true; 4346 } 4347 4348 virtual void getTargetDefines(const LangOptions &Opts, 4349 MacroBuilder &Builder) const; 4350 4351 virtual bool hasFeature(StringRef Feature) const { 4352 return Feature == "hexagon"; 4353 } 4354 4355 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4356 return TargetInfo::CharPtrBuiltinVaList; 4357 } 4358 virtual void getGCCRegNames(const char * const *&Names, 4359 unsigned &NumNames) const; 4360 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4361 unsigned &NumAliases) const; 4362 virtual const char *getClobbers() const { 4363 return ""; 4364 } 4365 4366 static const char *getHexagonCPUSuffix(StringRef Name) { 4367 return llvm::StringSwitch<const char*>(Name) 4368 .Case("hexagonv4", "4") 4369 .Case("hexagonv5", "5") 4370 .Default(0); 4371 } 4372 4373 virtual bool setCPU(const std::string &Name) { 4374 if (!getHexagonCPUSuffix(Name)) 4375 return false; 4376 4377 CPU = Name; 4378 return true; 4379 } 4380 }; 4381 4382 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4383 MacroBuilder &Builder) const { 4384 Builder.defineMacro("qdsp6"); 4385 Builder.defineMacro("__qdsp6", "1"); 4386 Builder.defineMacro("__qdsp6__", "1"); 4387 4388 Builder.defineMacro("hexagon"); 4389 Builder.defineMacro("__hexagon", "1"); 4390 Builder.defineMacro("__hexagon__", "1"); 4391 4392 if(CPU == "hexagonv1") { 4393 Builder.defineMacro("__HEXAGON_V1__"); 4394 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4395 if(Opts.HexagonQdsp6Compat) { 4396 Builder.defineMacro("__QDSP6_V1__"); 4397 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4398 } 4399 } 4400 else if(CPU == "hexagonv2") { 4401 Builder.defineMacro("__HEXAGON_V2__"); 4402 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4403 if(Opts.HexagonQdsp6Compat) { 4404 Builder.defineMacro("__QDSP6_V2__"); 4405 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4406 } 4407 } 4408 else if(CPU == "hexagonv3") { 4409 Builder.defineMacro("__HEXAGON_V3__"); 4410 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4411 if(Opts.HexagonQdsp6Compat) { 4412 Builder.defineMacro("__QDSP6_V3__"); 4413 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4414 } 4415 } 4416 else if(CPU == "hexagonv4") { 4417 Builder.defineMacro("__HEXAGON_V4__"); 4418 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4419 if(Opts.HexagonQdsp6Compat) { 4420 Builder.defineMacro("__QDSP6_V4__"); 4421 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4422 } 4423 } 4424 else if(CPU == "hexagonv5") { 4425 Builder.defineMacro("__HEXAGON_V5__"); 4426 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4427 if(Opts.HexagonQdsp6Compat) { 4428 Builder.defineMacro("__QDSP6_V5__"); 4429 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4430 } 4431 } 4432 } 4433 4434 const char * const HexagonTargetInfo::GCCRegNames[] = { 4435 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4436 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4437 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4438 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4439 "p0", "p1", "p2", "p3", 4440 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4441 }; 4442 4443 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4444 unsigned &NumNames) const { 4445 Names = GCCRegNames; 4446 NumNames = llvm::array_lengthof(GCCRegNames); 4447 } 4448 4449 4450 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4451 { { "sp" }, "r29" }, 4452 { { "fp" }, "r30" }, 4453 { { "lr" }, "r31" }, 4454 }; 4455 4456 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4457 unsigned &NumAliases) const { 4458 Aliases = GCCRegAliases; 4459 NumAliases = llvm::array_lengthof(GCCRegAliases); 4460 } 4461 4462 4463 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4464 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4465 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4466 ALL_LANGUAGES }, 4467 #include "clang/Basic/BuiltinsHexagon.def" 4468 }; 4469 } 4470 4471 4472 namespace { 4473 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4474 class SparcTargetInfo : public TargetInfo { 4475 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4476 static const char * const GCCRegNames[]; 4477 bool SoftFloat; 4478 public: 4479 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4480 4481 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4482 DiagnosticsEngine &Diags) { 4483 SoftFloat = false; 4484 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4485 if (Features[i] == "+soft-float") 4486 SoftFloat = true; 4487 return true; 4488 } 4489 virtual void getTargetDefines(const LangOptions &Opts, 4490 MacroBuilder &Builder) const { 4491 DefineStd(Builder, "sparc", Opts); 4492 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4493 4494 if (SoftFloat) 4495 Builder.defineMacro("SOFT_FLOAT", "1"); 4496 } 4497 4498 virtual bool hasFeature(StringRef Feature) const { 4499 return llvm::StringSwitch<bool>(Feature) 4500 .Case("softfloat", SoftFloat) 4501 .Case("sparc", true) 4502 .Default(false); 4503 } 4504 4505 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4506 unsigned &NumRecords) const { 4507 // FIXME: Implement! 4508 } 4509 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4510 return TargetInfo::VoidPtrBuiltinVaList; 4511 } 4512 virtual void getGCCRegNames(const char * const *&Names, 4513 unsigned &NumNames) const; 4514 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4515 unsigned &NumAliases) const; 4516 virtual bool validateAsmConstraint(const char *&Name, 4517 TargetInfo::ConstraintInfo &info) const { 4518 // FIXME: Implement! 4519 return false; 4520 } 4521 virtual const char *getClobbers() const { 4522 // FIXME: Implement! 4523 return ""; 4524 } 4525 }; 4526 4527 const char * const SparcTargetInfo::GCCRegNames[] = { 4528 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4529 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4530 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4531 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4532 }; 4533 4534 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4535 unsigned &NumNames) const { 4536 Names = GCCRegNames; 4537 NumNames = llvm::array_lengthof(GCCRegNames); 4538 } 4539 4540 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4541 { { "g0" }, "r0" }, 4542 { { "g1" }, "r1" }, 4543 { { "g2" }, "r2" }, 4544 { { "g3" }, "r3" }, 4545 { { "g4" }, "r4" }, 4546 { { "g5" }, "r5" }, 4547 { { "g6" }, "r6" }, 4548 { { "g7" }, "r7" }, 4549 { { "o0" }, "r8" }, 4550 { { "o1" }, "r9" }, 4551 { { "o2" }, "r10" }, 4552 { { "o3" }, "r11" }, 4553 { { "o4" }, "r12" }, 4554 { { "o5" }, "r13" }, 4555 { { "o6", "sp" }, "r14" }, 4556 { { "o7" }, "r15" }, 4557 { { "l0" }, "r16" }, 4558 { { "l1" }, "r17" }, 4559 { { "l2" }, "r18" }, 4560 { { "l3" }, "r19" }, 4561 { { "l4" }, "r20" }, 4562 { { "l5" }, "r21" }, 4563 { { "l6" }, "r22" }, 4564 { { "l7" }, "r23" }, 4565 { { "i0" }, "r24" }, 4566 { { "i1" }, "r25" }, 4567 { { "i2" }, "r26" }, 4568 { { "i3" }, "r27" }, 4569 { { "i4" }, "r28" }, 4570 { { "i5" }, "r29" }, 4571 { { "i6", "fp" }, "r30" }, 4572 { { "i7" }, "r31" }, 4573 }; 4574 4575 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4576 unsigned &NumAliases) const { 4577 Aliases = GCCRegAliases; 4578 NumAliases = llvm::array_lengthof(GCCRegAliases); 4579 } 4580 4581 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4582 class SparcV8TargetInfo : public SparcTargetInfo { 4583 public: 4584 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4585 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 4586 } 4587 4588 virtual void getTargetDefines(const LangOptions &Opts, 4589 MacroBuilder &Builder) const { 4590 SparcTargetInfo::getTargetDefines(Opts, Builder); 4591 Builder.defineMacro("__sparcv8"); 4592 } 4593 }; 4594 4595 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4596 class SparcV9TargetInfo : public SparcTargetInfo { 4597 public: 4598 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4599 // FIXME: Support Sparc quad-precision long double? 4600 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 4601 // This is an LP64 platform. 4602 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4603 4604 // OpenBSD uses long long for int64_t and intmax_t. 4605 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4606 IntMaxType = SignedLongLong; 4607 UIntMaxType = UnsignedLongLong; 4608 } else { 4609 IntMaxType = SignedLong; 4610 UIntMaxType = UnsignedLong; 4611 } 4612 Int64Type = IntMaxType; 4613 4614 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 4615 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 4616 LongDoubleWidth = 128; 4617 LongDoubleAlign = 128; 4618 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4619 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4620 } 4621 4622 virtual void getTargetDefines(const LangOptions &Opts, 4623 MacroBuilder &Builder) const { 4624 SparcTargetInfo::getTargetDefines(Opts, Builder); 4625 Builder.defineMacro("__sparcv9"); 4626 Builder.defineMacro("__arch64__"); 4627 // Solaris and its derivative AuroraUX don't need these variants, but the 4628 // BSDs do. 4629 if (getTriple().getOS() != llvm::Triple::Solaris && 4630 getTriple().getOS() != llvm::Triple::AuroraUX) { 4631 Builder.defineMacro("__sparc64__"); 4632 Builder.defineMacro("__sparc_v9__"); 4633 Builder.defineMacro("__sparcv9__"); 4634 } 4635 } 4636 4637 virtual bool setCPU(const std::string &Name) { 4638 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4639 .Case("v9", true) 4640 .Case("ultrasparc", true) 4641 .Case("ultrasparc3", true) 4642 .Case("niagara", true) 4643 .Case("niagara2", true) 4644 .Case("niagara3", true) 4645 .Case("niagara4", true) 4646 .Default(false); 4647 4648 // No need to store the CPU yet. There aren't any CPU-specific 4649 // macros to define. 4650 return CPUKnown; 4651 } 4652 }; 4653 4654 } // end anonymous namespace. 4655 4656 namespace { 4657 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4658 public: 4659 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4660 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4661 SizeType = UnsignedInt; 4662 PtrDiffType = SignedInt; 4663 } 4664 }; 4665 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4666 public: 4667 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4668 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4669 SizeType = UnsignedInt; 4670 PtrDiffType = SignedInt; 4671 } 4672 }; 4673 } // end anonymous namespace. 4674 4675 namespace { 4676 class SystemZTargetInfo : public TargetInfo { 4677 static const char *const GCCRegNames[]; 4678 4679 public: 4680 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4681 TLSSupported = true; 4682 IntWidth = IntAlign = 32; 4683 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4684 PointerWidth = PointerAlign = 64; 4685 LongDoubleWidth = 128; 4686 LongDoubleAlign = 64; 4687 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4688 MinGlobalAlign = 16; 4689 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 4690 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4691 } 4692 virtual void getTargetDefines(const LangOptions &Opts, 4693 MacroBuilder &Builder) const { 4694 Builder.defineMacro("__s390__"); 4695 Builder.defineMacro("__s390x__"); 4696 Builder.defineMacro("__zarch__"); 4697 Builder.defineMacro("__LONG_DOUBLE_128__"); 4698 } 4699 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4700 unsigned &NumRecords) const { 4701 // FIXME: Implement. 4702 Records = 0; 4703 NumRecords = 0; 4704 } 4705 4706 virtual void getGCCRegNames(const char *const *&Names, 4707 unsigned &NumNames) const; 4708 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4709 unsigned &NumAliases) const { 4710 // No aliases. 4711 Aliases = 0; 4712 NumAliases = 0; 4713 } 4714 virtual bool validateAsmConstraint(const char *&Name, 4715 TargetInfo::ConstraintInfo &info) const; 4716 virtual const char *getClobbers() const { 4717 // FIXME: Is this really right? 4718 return ""; 4719 } 4720 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4721 return TargetInfo::SystemZBuiltinVaList; 4722 } 4723 virtual bool setCPU(const std::string &Name) { 4724 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4725 .Case("z10", true) 4726 .Case("z196", true) 4727 .Case("zEC12", true) 4728 .Default(false); 4729 4730 // No need to store the CPU yet. There aren't any CPU-specific 4731 // macros to define. 4732 return CPUKnown; 4733 } 4734 }; 4735 4736 const char *const SystemZTargetInfo::GCCRegNames[] = { 4737 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4738 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4739 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4740 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4741 }; 4742 4743 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4744 unsigned &NumNames) const { 4745 Names = GCCRegNames; 4746 NumNames = llvm::array_lengthof(GCCRegNames); 4747 } 4748 4749 bool SystemZTargetInfo:: 4750 validateAsmConstraint(const char *&Name, 4751 TargetInfo::ConstraintInfo &Info) const { 4752 switch (*Name) { 4753 default: 4754 return false; 4755 4756 case 'a': // Address register 4757 case 'd': // Data register (equivalent to 'r') 4758 case 'f': // Floating-point register 4759 Info.setAllowsRegister(); 4760 return true; 4761 4762 case 'I': // Unsigned 8-bit constant 4763 case 'J': // Unsigned 12-bit constant 4764 case 'K': // Signed 16-bit constant 4765 case 'L': // Signed 20-bit displacement (on all targets we support) 4766 case 'M': // 0x7fffffff 4767 return true; 4768 4769 case 'Q': // Memory with base and unsigned 12-bit displacement 4770 case 'R': // Likewise, plus an index 4771 case 'S': // Memory with base and signed 20-bit displacement 4772 case 'T': // Likewise, plus an index 4773 Info.setAllowsMemory(); 4774 return true; 4775 } 4776 } 4777 } 4778 4779 namespace { 4780 class MSP430TargetInfo : public TargetInfo { 4781 static const char * const GCCRegNames[]; 4782 public: 4783 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4784 BigEndian = false; 4785 TLSSupported = false; 4786 IntWidth = 16; IntAlign = 16; 4787 LongWidth = 32; LongLongWidth = 64; 4788 LongAlign = LongLongAlign = 16; 4789 PointerWidth = 16; PointerAlign = 16; 4790 SuitableAlign = 16; 4791 SizeType = UnsignedInt; 4792 IntMaxType = SignedLongLong; 4793 UIntMaxType = UnsignedLongLong; 4794 IntPtrType = SignedInt; 4795 PtrDiffType = SignedInt; 4796 SigAtomicType = SignedLong; 4797 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 4798 } 4799 virtual void getTargetDefines(const LangOptions &Opts, 4800 MacroBuilder &Builder) const { 4801 Builder.defineMacro("MSP430"); 4802 Builder.defineMacro("__MSP430__"); 4803 // FIXME: defines for different 'flavours' of MCU 4804 } 4805 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4806 unsigned &NumRecords) const { 4807 // FIXME: Implement. 4808 Records = 0; 4809 NumRecords = 0; 4810 } 4811 virtual bool hasFeature(StringRef Feature) const { 4812 return Feature == "msp430"; 4813 } 4814 virtual void getGCCRegNames(const char * const *&Names, 4815 unsigned &NumNames) const; 4816 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4817 unsigned &NumAliases) const { 4818 // No aliases. 4819 Aliases = 0; 4820 NumAliases = 0; 4821 } 4822 virtual bool validateAsmConstraint(const char *&Name, 4823 TargetInfo::ConstraintInfo &info) const { 4824 // No target constraints for now. 4825 return false; 4826 } 4827 virtual const char *getClobbers() const { 4828 // FIXME: Is this really right? 4829 return ""; 4830 } 4831 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4832 // FIXME: implement 4833 return TargetInfo::CharPtrBuiltinVaList; 4834 } 4835 }; 4836 4837 const char * const MSP430TargetInfo::GCCRegNames[] = { 4838 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4839 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4840 }; 4841 4842 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4843 unsigned &NumNames) const { 4844 Names = GCCRegNames; 4845 NumNames = llvm::array_lengthof(GCCRegNames); 4846 } 4847 } 4848 4849 namespace { 4850 4851 // LLVM and Clang cannot be used directly to output native binaries for 4852 // target, but is used to compile C code to llvm bitcode with correct 4853 // type and alignment information. 4854 // 4855 // TCE uses the llvm bitcode as input and uses it for generating customized 4856 // target processor and program binary. TCE co-design environment is 4857 // publicly available in http://tce.cs.tut.fi 4858 4859 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4860 3, // opencl_global 4861 4, // opencl_local 4862 5, // opencl_constant 4863 0, // cuda_device 4864 0, // cuda_constant 4865 0 // cuda_shared 4866 }; 4867 4868 class TCETargetInfo : public TargetInfo{ 4869 public: 4870 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4871 TLSSupported = false; 4872 IntWidth = 32; 4873 LongWidth = LongLongWidth = 32; 4874 PointerWidth = 32; 4875 IntAlign = 32; 4876 LongAlign = LongLongAlign = 32; 4877 PointerAlign = 32; 4878 SuitableAlign = 32; 4879 SizeType = UnsignedInt; 4880 IntMaxType = SignedLong; 4881 UIntMaxType = UnsignedLong; 4882 IntPtrType = SignedInt; 4883 PtrDiffType = SignedInt; 4884 FloatWidth = 32; 4885 FloatAlign = 32; 4886 DoubleWidth = 32; 4887 DoubleAlign = 32; 4888 LongDoubleWidth = 32; 4889 LongDoubleAlign = 32; 4890 FloatFormat = &llvm::APFloat::IEEEsingle; 4891 DoubleFormat = &llvm::APFloat::IEEEsingle; 4892 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4893 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 4894 "-f64:32-v64:32-v128:32-a:0:32-n32"; 4895 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4896 UseAddrSpaceMapMangling = true; 4897 } 4898 4899 virtual void getTargetDefines(const LangOptions &Opts, 4900 MacroBuilder &Builder) const { 4901 DefineStd(Builder, "tce", Opts); 4902 Builder.defineMacro("__TCE__"); 4903 Builder.defineMacro("__TCE_V1__"); 4904 } 4905 virtual bool hasFeature(StringRef Feature) const { 4906 return Feature == "tce"; 4907 } 4908 4909 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4910 unsigned &NumRecords) const {} 4911 virtual const char *getClobbers() const { 4912 return ""; 4913 } 4914 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4915 return TargetInfo::VoidPtrBuiltinVaList; 4916 } 4917 virtual void getGCCRegNames(const char * const *&Names, 4918 unsigned &NumNames) const {} 4919 virtual bool validateAsmConstraint(const char *&Name, 4920 TargetInfo::ConstraintInfo &info) const { 4921 return true; 4922 } 4923 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4924 unsigned &NumAliases) const {} 4925 }; 4926 } 4927 4928 namespace { 4929 class MipsTargetInfoBase : public TargetInfo { 4930 virtual void setDescriptionString() = 0; 4931 4932 static const Builtin::Info BuiltinInfo[]; 4933 std::string CPU; 4934 bool IsMips16; 4935 bool IsMicromips; 4936 bool IsNan2008; 4937 bool IsSingleFloat; 4938 enum MipsFloatABI { 4939 HardFloat, SoftFloat 4940 } FloatABI; 4941 enum DspRevEnum { 4942 NoDSP, DSP1, DSP2 4943 } DspRev; 4944 bool HasMSA; 4945 4946 protected: 4947 bool HasFP64; 4948 std::string ABI; 4949 4950 public: 4951 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4952 const std::string &CPUStr) 4953 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4954 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4955 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4956 4957 virtual const char *getABI() const { return ABI.c_str(); } 4958 virtual bool setABI(const std::string &Name) = 0; 4959 virtual bool setCPU(const std::string &Name) { 4960 CPU = Name; 4961 return true; 4962 } 4963 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4964 // The backend enables certain ABI's by default according to the 4965 // architecture. 4966 // Disable both possible defaults so that we don't end up with multiple 4967 // ABI's selected and trigger an assertion. 4968 Features["o32"] = false; 4969 Features["n64"] = false; 4970 4971 Features[ABI] = true; 4972 Features[CPU] = true; 4973 } 4974 4975 virtual void getTargetDefines(const LangOptions &Opts, 4976 MacroBuilder &Builder) const { 4977 Builder.defineMacro("__mips__"); 4978 Builder.defineMacro("_mips"); 4979 if (Opts.GNUMode) 4980 Builder.defineMacro("mips"); 4981 4982 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4983 4984 switch (FloatABI) { 4985 case HardFloat: 4986 Builder.defineMacro("__mips_hard_float", Twine(1)); 4987 break; 4988 case SoftFloat: 4989 Builder.defineMacro("__mips_soft_float", Twine(1)); 4990 break; 4991 } 4992 4993 if (IsSingleFloat) 4994 Builder.defineMacro("__mips_single_float", Twine(1)); 4995 4996 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4997 Builder.defineMacro("_MIPS_FPSET", 4998 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4999 5000 if (IsMips16) 5001 Builder.defineMacro("__mips16", Twine(1)); 5002 5003 if (IsMicromips) 5004 Builder.defineMacro("__mips_micromips", Twine(1)); 5005 5006 if (IsNan2008) 5007 Builder.defineMacro("__mips_nan2008", Twine(1)); 5008 5009 switch (DspRev) { 5010 default: 5011 break; 5012 case DSP1: 5013 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5014 Builder.defineMacro("__mips_dsp", Twine(1)); 5015 break; 5016 case DSP2: 5017 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5018 Builder.defineMacro("__mips_dspr2", Twine(1)); 5019 Builder.defineMacro("__mips_dsp", Twine(1)); 5020 break; 5021 } 5022 5023 if (HasMSA) 5024 Builder.defineMacro("__mips_msa", Twine(1)); 5025 5026 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5027 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5028 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5029 5030 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5031 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5032 } 5033 5034 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5035 unsigned &NumRecords) const { 5036 Records = BuiltinInfo; 5037 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5038 } 5039 virtual bool hasFeature(StringRef Feature) const { 5040 return llvm::StringSwitch<bool>(Feature) 5041 .Case("mips", true) 5042 .Case("fp64", HasFP64) 5043 .Default(false); 5044 } 5045 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5046 return TargetInfo::VoidPtrBuiltinVaList; 5047 } 5048 virtual void getGCCRegNames(const char * const *&Names, 5049 unsigned &NumNames) const { 5050 static const char *const GCCRegNames[] = { 5051 // CPU register names 5052 // Must match second column of GCCRegAliases 5053 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5054 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5055 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5056 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5057 // Floating point register names 5058 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5059 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5060 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5061 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5062 // Hi/lo and condition register names 5063 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5064 "$fcc5","$fcc6","$fcc7", 5065 // MSA register names 5066 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5067 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5068 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5069 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5070 // MSA control register names 5071 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5072 "$msarequest", "$msamap", "$msaunmap" 5073 }; 5074 Names = GCCRegNames; 5075 NumNames = llvm::array_lengthof(GCCRegNames); 5076 } 5077 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5078 unsigned &NumAliases) const = 0; 5079 virtual bool validateAsmConstraint(const char *&Name, 5080 TargetInfo::ConstraintInfo &Info) const { 5081 switch (*Name) { 5082 default: 5083 return false; 5084 5085 case 'r': // CPU registers. 5086 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5087 case 'y': // Equivalent to "r", backwards compatibility only. 5088 case 'f': // floating-point registers. 5089 case 'c': // $25 for indirect jumps 5090 case 'l': // lo register 5091 case 'x': // hilo register pair 5092 Info.setAllowsRegister(); 5093 return true; 5094 case 'R': // An address that can be used in a non-macro load or store 5095 Info.setAllowsMemory(); 5096 return true; 5097 } 5098 } 5099 5100 virtual const char *getClobbers() const { 5101 // FIXME: Implement! 5102 return ""; 5103 } 5104 5105 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 5106 DiagnosticsEngine &Diags) { 5107 IsMips16 = false; 5108 IsMicromips = false; 5109 IsNan2008 = false; 5110 IsSingleFloat = false; 5111 FloatABI = HardFloat; 5112 DspRev = NoDSP; 5113 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5114 5115 for (std::vector<std::string>::iterator it = Features.begin(), 5116 ie = Features.end(); it != ie; ++it) { 5117 if (*it == "+single-float") 5118 IsSingleFloat = true; 5119 else if (*it == "+soft-float") 5120 FloatABI = SoftFloat; 5121 else if (*it == "+mips16") 5122 IsMips16 = true; 5123 else if (*it == "+micromips") 5124 IsMicromips = true; 5125 else if (*it == "+dsp") 5126 DspRev = std::max(DspRev, DSP1); 5127 else if (*it == "+dspr2") 5128 DspRev = std::max(DspRev, DSP2); 5129 else if (*it == "+msa") 5130 HasMSA = true; 5131 else if (*it == "+fp64") 5132 HasFP64 = true; 5133 else if (*it == "-fp64") 5134 HasFP64 = false; 5135 else if (*it == "+nan2008") 5136 IsNan2008 = true; 5137 } 5138 5139 // Remove front-end specific options. 5140 std::vector<std::string>::iterator it = 5141 std::find(Features.begin(), Features.end(), "+soft-float"); 5142 if (it != Features.end()) 5143 Features.erase(it); 5144 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5145 if (it != Features.end()) 5146 Features.erase(it); 5147 5148 setDescriptionString(); 5149 5150 return true; 5151 } 5152 5153 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5154 if (RegNo == 0) return 4; 5155 if (RegNo == 1) return 5; 5156 return -1; 5157 } 5158 }; 5159 5160 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5161 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5162 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5163 ALL_LANGUAGES }, 5164 #include "clang/Basic/BuiltinsMips.def" 5165 }; 5166 5167 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5168 public: 5169 Mips32TargetInfoBase(const llvm::Triple &Triple) 5170 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5171 SizeType = UnsignedInt; 5172 PtrDiffType = SignedInt; 5173 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5174 } 5175 virtual bool setABI(const std::string &Name) { 5176 if ((Name == "o32") || (Name == "eabi")) { 5177 ABI = Name; 5178 return true; 5179 } else if (Name == "32") { 5180 ABI = "o32"; 5181 return true; 5182 } else 5183 return false; 5184 } 5185 virtual void getTargetDefines(const LangOptions &Opts, 5186 MacroBuilder &Builder) const { 5187 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5188 5189 Builder.defineMacro("__mips", "32"); 5190 5191 if (ABI == "o32") { 5192 Builder.defineMacro("__mips_o32"); 5193 Builder.defineMacro("_ABIO32", "1"); 5194 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5195 } 5196 else if (ABI == "eabi") 5197 Builder.defineMacro("__mips_eabi"); 5198 else 5199 llvm_unreachable("Invalid ABI for Mips32."); 5200 } 5201 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5202 unsigned &NumAliases) const { 5203 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5204 { { "at" }, "$1" }, 5205 { { "v0" }, "$2" }, 5206 { { "v1" }, "$3" }, 5207 { { "a0" }, "$4" }, 5208 { { "a1" }, "$5" }, 5209 { { "a2" }, "$6" }, 5210 { { "a3" }, "$7" }, 5211 { { "t0" }, "$8" }, 5212 { { "t1" }, "$9" }, 5213 { { "t2" }, "$10" }, 5214 { { "t3" }, "$11" }, 5215 { { "t4" }, "$12" }, 5216 { { "t5" }, "$13" }, 5217 { { "t6" }, "$14" }, 5218 { { "t7" }, "$15" }, 5219 { { "s0" }, "$16" }, 5220 { { "s1" }, "$17" }, 5221 { { "s2" }, "$18" }, 5222 { { "s3" }, "$19" }, 5223 { { "s4" }, "$20" }, 5224 { { "s5" }, "$21" }, 5225 { { "s6" }, "$22" }, 5226 { { "s7" }, "$23" }, 5227 { { "t8" }, "$24" }, 5228 { { "t9" }, "$25" }, 5229 { { "k0" }, "$26" }, 5230 { { "k1" }, "$27" }, 5231 { { "gp" }, "$28" }, 5232 { { "sp","$sp" }, "$29" }, 5233 { { "fp","$fp" }, "$30" }, 5234 { { "ra" }, "$31" } 5235 }; 5236 Aliases = GCCRegAliases; 5237 NumAliases = llvm::array_lengthof(GCCRegAliases); 5238 } 5239 }; 5240 5241 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5242 virtual void setDescriptionString() { 5243 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5244 } 5245 5246 public: 5247 Mips32EBTargetInfo(const llvm::Triple &Triple) 5248 : Mips32TargetInfoBase(Triple) { 5249 } 5250 virtual void getTargetDefines(const LangOptions &Opts, 5251 MacroBuilder &Builder) const { 5252 DefineStd(Builder, "MIPSEB", Opts); 5253 Builder.defineMacro("_MIPSEB"); 5254 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5255 } 5256 }; 5257 5258 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5259 virtual void setDescriptionString() { 5260 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5261 } 5262 5263 public: 5264 Mips32ELTargetInfo(const llvm::Triple &Triple) 5265 : Mips32TargetInfoBase(Triple) { 5266 BigEndian = false; 5267 } 5268 virtual void getTargetDefines(const LangOptions &Opts, 5269 MacroBuilder &Builder) const { 5270 DefineStd(Builder, "MIPSEL", Opts); 5271 Builder.defineMacro("_MIPSEL"); 5272 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5273 } 5274 }; 5275 5276 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5277 public: 5278 Mips64TargetInfoBase(const llvm::Triple &Triple) 5279 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5280 LongWidth = LongAlign = 64; 5281 PointerWidth = PointerAlign = 64; 5282 LongDoubleWidth = LongDoubleAlign = 128; 5283 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5284 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5285 LongDoubleWidth = LongDoubleAlign = 64; 5286 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5287 } 5288 SuitableAlign = 128; 5289 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5290 } 5291 virtual bool setABI(const std::string &Name) { 5292 if (Name == "n32") { 5293 LongWidth = LongAlign = 32; 5294 PointerWidth = PointerAlign = 32; 5295 ABI = Name; 5296 return true; 5297 } else if (Name == "n64") { 5298 ABI = Name; 5299 return true; 5300 } else if (Name == "64") { 5301 ABI = "n64"; 5302 return true; 5303 } else 5304 return false; 5305 } 5306 virtual void getTargetDefines(const LangOptions &Opts, 5307 MacroBuilder &Builder) const { 5308 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5309 5310 Builder.defineMacro("__mips", "64"); 5311 Builder.defineMacro("__mips64"); 5312 Builder.defineMacro("__mips64__"); 5313 5314 if (ABI == "n32") { 5315 Builder.defineMacro("__mips_n32"); 5316 Builder.defineMacro("_ABIN32", "2"); 5317 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5318 } 5319 else if (ABI == "n64") { 5320 Builder.defineMacro("__mips_n64"); 5321 Builder.defineMacro("_ABI64", "3"); 5322 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5323 } 5324 else 5325 llvm_unreachable("Invalid ABI for Mips64."); 5326 } 5327 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5328 unsigned &NumAliases) const { 5329 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5330 { { "at" }, "$1" }, 5331 { { "v0" }, "$2" }, 5332 { { "v1" }, "$3" }, 5333 { { "a0" }, "$4" }, 5334 { { "a1" }, "$5" }, 5335 { { "a2" }, "$6" }, 5336 { { "a3" }, "$7" }, 5337 { { "a4" }, "$8" }, 5338 { { "a5" }, "$9" }, 5339 { { "a6" }, "$10" }, 5340 { { "a7" }, "$11" }, 5341 { { "t0" }, "$12" }, 5342 { { "t1" }, "$13" }, 5343 { { "t2" }, "$14" }, 5344 { { "t3" }, "$15" }, 5345 { { "s0" }, "$16" }, 5346 { { "s1" }, "$17" }, 5347 { { "s2" }, "$18" }, 5348 { { "s3" }, "$19" }, 5349 { { "s4" }, "$20" }, 5350 { { "s5" }, "$21" }, 5351 { { "s6" }, "$22" }, 5352 { { "s7" }, "$23" }, 5353 { { "t8" }, "$24" }, 5354 { { "t9" }, "$25" }, 5355 { { "k0" }, "$26" }, 5356 { { "k1" }, "$27" }, 5357 { { "gp" }, "$28" }, 5358 { { "sp","$sp" }, "$29" }, 5359 { { "fp","$fp" }, "$30" }, 5360 { { "ra" }, "$31" } 5361 }; 5362 Aliases = GCCRegAliases; 5363 NumAliases = llvm::array_lengthof(GCCRegAliases); 5364 } 5365 }; 5366 5367 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5368 virtual void setDescriptionString() { 5369 if (ABI == "n32") 5370 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5371 else 5372 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5373 5374 } 5375 5376 public: 5377 Mips64EBTargetInfo(const llvm::Triple &Triple) 5378 : Mips64TargetInfoBase(Triple) {} 5379 virtual void getTargetDefines(const LangOptions &Opts, 5380 MacroBuilder &Builder) const { 5381 DefineStd(Builder, "MIPSEB", Opts); 5382 Builder.defineMacro("_MIPSEB"); 5383 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5384 } 5385 }; 5386 5387 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5388 virtual void setDescriptionString() { 5389 if (ABI == "n32") 5390 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5391 else 5392 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5393 } 5394 public: 5395 Mips64ELTargetInfo(const llvm::Triple &Triple) 5396 : Mips64TargetInfoBase(Triple) { 5397 // Default ABI is n64. 5398 BigEndian = false; 5399 } 5400 virtual void getTargetDefines(const LangOptions &Opts, 5401 MacroBuilder &Builder) const { 5402 DefineStd(Builder, "MIPSEL", Opts); 5403 Builder.defineMacro("_MIPSEL"); 5404 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5405 } 5406 }; 5407 } // end anonymous namespace. 5408 5409 namespace { 5410 class PNaClTargetInfo : public TargetInfo { 5411 public: 5412 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5413 BigEndian = false; 5414 this->UserLabelPrefix = ""; 5415 this->LongAlign = 32; 5416 this->LongWidth = 32; 5417 this->PointerAlign = 32; 5418 this->PointerWidth = 32; 5419 this->IntMaxType = TargetInfo::SignedLongLong; 5420 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5421 this->Int64Type = TargetInfo::SignedLongLong; 5422 this->DoubleAlign = 64; 5423 this->LongDoubleWidth = 64; 5424 this->LongDoubleAlign = 64; 5425 this->SizeType = TargetInfo::UnsignedInt; 5426 this->PtrDiffType = TargetInfo::SignedInt; 5427 this->IntPtrType = TargetInfo::SignedInt; 5428 this->RegParmMax = 0; // Disallow regparm 5429 } 5430 5431 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5432 } 5433 virtual void getArchDefines(const LangOptions &Opts, 5434 MacroBuilder &Builder) const { 5435 Builder.defineMacro("__le32__"); 5436 Builder.defineMacro("__pnacl__"); 5437 } 5438 virtual void getTargetDefines(const LangOptions &Opts, 5439 MacroBuilder &Builder) const { 5440 getArchDefines(Opts, Builder); 5441 } 5442 virtual bool hasFeature(StringRef Feature) const { 5443 return Feature == "pnacl"; 5444 } 5445 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5446 unsigned &NumRecords) const { 5447 } 5448 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5449 return TargetInfo::PNaClABIBuiltinVaList; 5450 } 5451 virtual void getGCCRegNames(const char * const *&Names, 5452 unsigned &NumNames) const; 5453 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5454 unsigned &NumAliases) const; 5455 virtual bool validateAsmConstraint(const char *&Name, 5456 TargetInfo::ConstraintInfo &Info) const { 5457 return false; 5458 } 5459 5460 virtual const char *getClobbers() const { 5461 return ""; 5462 } 5463 }; 5464 5465 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5466 unsigned &NumNames) const { 5467 Names = NULL; 5468 NumNames = 0; 5469 } 5470 5471 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5472 unsigned &NumAliases) const { 5473 Aliases = NULL; 5474 NumAliases = 0; 5475 } 5476 } // end anonymous namespace. 5477 5478 namespace { 5479 static const unsigned SPIRAddrSpaceMap[] = { 5480 1, // opencl_global 5481 3, // opencl_local 5482 2, // opencl_constant 5483 0, // cuda_device 5484 0, // cuda_constant 5485 0 // cuda_shared 5486 }; 5487 class SPIRTargetInfo : public TargetInfo { 5488 public: 5489 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5490 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5491 "SPIR target must use unknown OS"); 5492 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5493 "SPIR target must use unknown environment type"); 5494 BigEndian = false; 5495 TLSSupported = false; 5496 LongWidth = LongAlign = 64; 5497 AddrSpaceMap = &SPIRAddrSpaceMap; 5498 UseAddrSpaceMapMangling = true; 5499 // Define available target features 5500 // These must be defined in sorted order! 5501 NoAsmVariants = true; 5502 } 5503 virtual void getTargetDefines(const LangOptions &Opts, 5504 MacroBuilder &Builder) const { 5505 DefineStd(Builder, "SPIR", Opts); 5506 } 5507 virtual bool hasFeature(StringRef Feature) const { 5508 return Feature == "spir"; 5509 } 5510 5511 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5512 unsigned &NumRecords) const {} 5513 virtual const char *getClobbers() const { 5514 return ""; 5515 } 5516 virtual void getGCCRegNames(const char * const *&Names, 5517 unsigned &NumNames) const {} 5518 virtual bool validateAsmConstraint(const char *&Name, 5519 TargetInfo::ConstraintInfo &info) const { 5520 return true; 5521 } 5522 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5523 unsigned &NumAliases) const {} 5524 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5525 return TargetInfo::VoidPtrBuiltinVaList; 5526 } 5527 }; 5528 5529 5530 class SPIR32TargetInfo : public SPIRTargetInfo { 5531 public: 5532 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5533 PointerWidth = PointerAlign = 32; 5534 SizeType = TargetInfo::UnsignedInt; 5535 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5536 DescriptionString 5537 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 5538 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5539 } 5540 virtual void getTargetDefines(const LangOptions &Opts, 5541 MacroBuilder &Builder) const { 5542 DefineStd(Builder, "SPIR32", Opts); 5543 } 5544 }; 5545 5546 class SPIR64TargetInfo : public SPIRTargetInfo { 5547 public: 5548 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5549 PointerWidth = PointerAlign = 64; 5550 SizeType = TargetInfo::UnsignedLong; 5551 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5552 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 5553 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 5554 } 5555 virtual void getTargetDefines(const LangOptions &Opts, 5556 MacroBuilder &Builder) const { 5557 DefineStd(Builder, "SPIR64", Opts); 5558 } 5559 }; 5560 } 5561 5562 namespace { 5563 class XCoreTargetInfo : public TargetInfo { 5564 static const Builtin::Info BuiltinInfo[]; 5565 public: 5566 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5567 BigEndian = false; 5568 NoAsmVariants = true; 5569 LongLongAlign = 32; 5570 SuitableAlign = 32; 5571 DoubleAlign = LongDoubleAlign = 32; 5572 SizeType = UnsignedInt; 5573 PtrDiffType = SignedInt; 5574 IntPtrType = SignedInt; 5575 WCharType = UnsignedChar; 5576 WIntType = UnsignedInt; 5577 UseZeroLengthBitfieldAlignment = true; 5578 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 5579 "-f64:32-a:0:32-n32"; 5580 } 5581 virtual void getTargetDefines(const LangOptions &Opts, 5582 MacroBuilder &Builder) const { 5583 Builder.defineMacro("__XS1B__"); 5584 } 5585 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5586 unsigned &NumRecords) const { 5587 Records = BuiltinInfo; 5588 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5589 } 5590 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5591 return TargetInfo::VoidPtrBuiltinVaList; 5592 } 5593 virtual const char *getClobbers() const { 5594 return ""; 5595 } 5596 virtual void getGCCRegNames(const char * const *&Names, 5597 unsigned &NumNames) const { 5598 static const char * const GCCRegNames[] = { 5599 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5600 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5601 }; 5602 Names = GCCRegNames; 5603 NumNames = llvm::array_lengthof(GCCRegNames); 5604 } 5605 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5606 unsigned &NumAliases) const { 5607 Aliases = NULL; 5608 NumAliases = 0; 5609 } 5610 virtual bool validateAsmConstraint(const char *&Name, 5611 TargetInfo::ConstraintInfo &Info) const { 5612 return false; 5613 } 5614 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5615 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 5616 return (RegNo < 2)? RegNo : -1; 5617 } 5618 }; 5619 5620 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5621 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5622 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5623 ALL_LANGUAGES }, 5624 #include "clang/Basic/BuiltinsXCore.def" 5625 }; 5626 } // end anonymous namespace. 5627 5628 5629 //===----------------------------------------------------------------------===// 5630 // Driver code 5631 //===----------------------------------------------------------------------===// 5632 5633 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5634 llvm::Triple::OSType os = Triple.getOS(); 5635 5636 switch (Triple.getArch()) { 5637 default: 5638 return NULL; 5639 5640 case llvm::Triple::xcore: 5641 return new XCoreTargetInfo(Triple); 5642 5643 case llvm::Triple::hexagon: 5644 return new HexagonTargetInfo(Triple); 5645 5646 case llvm::Triple::aarch64: 5647 switch (os) { 5648 case llvm::Triple::Linux: 5649 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 5650 case llvm::Triple::NetBSD: 5651 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 5652 default: 5653 return new AArch64leTargetInfo(Triple); 5654 } 5655 5656 case llvm::Triple::aarch64_be: 5657 switch (os) { 5658 case llvm::Triple::Linux: 5659 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 5660 case llvm::Triple::NetBSD: 5661 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 5662 default: 5663 return new AArch64beTargetInfo(Triple); 5664 } 5665 5666 case llvm::Triple::arm: 5667 case llvm::Triple::thumb: 5668 if (Triple.isOSBinFormatMachO()) 5669 return new DarwinARMTargetInfo(Triple); 5670 5671 switch (os) { 5672 case llvm::Triple::Linux: 5673 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5674 case llvm::Triple::FreeBSD: 5675 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5676 case llvm::Triple::NetBSD: 5677 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5678 case llvm::Triple::OpenBSD: 5679 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5680 case llvm::Triple::Bitrig: 5681 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5682 case llvm::Triple::RTEMS: 5683 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5684 case llvm::Triple::NaCl: 5685 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5686 default: 5687 return new ARMTargetInfo(Triple); 5688 } 5689 5690 case llvm::Triple::msp430: 5691 return new MSP430TargetInfo(Triple); 5692 5693 case llvm::Triple::mips: 5694 switch (os) { 5695 case llvm::Triple::Linux: 5696 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5697 case llvm::Triple::RTEMS: 5698 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5699 case llvm::Triple::FreeBSD: 5700 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5701 case llvm::Triple::NetBSD: 5702 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5703 default: 5704 return new Mips32EBTargetInfo(Triple); 5705 } 5706 5707 case llvm::Triple::mipsel: 5708 switch (os) { 5709 case llvm::Triple::Linux: 5710 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5711 case llvm::Triple::RTEMS: 5712 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5713 case llvm::Triple::FreeBSD: 5714 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5715 case llvm::Triple::NetBSD: 5716 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5717 case llvm::Triple::NaCl: 5718 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5719 default: 5720 return new Mips32ELTargetInfo(Triple); 5721 } 5722 5723 case llvm::Triple::mips64: 5724 switch (os) { 5725 case llvm::Triple::Linux: 5726 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5727 case llvm::Triple::RTEMS: 5728 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5729 case llvm::Triple::FreeBSD: 5730 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5731 case llvm::Triple::NetBSD: 5732 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5733 case llvm::Triple::OpenBSD: 5734 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5735 default: 5736 return new Mips64EBTargetInfo(Triple); 5737 } 5738 5739 case llvm::Triple::mips64el: 5740 switch (os) { 5741 case llvm::Triple::Linux: 5742 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5743 case llvm::Triple::RTEMS: 5744 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5745 case llvm::Triple::FreeBSD: 5746 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5747 case llvm::Triple::NetBSD: 5748 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5749 case llvm::Triple::OpenBSD: 5750 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5751 default: 5752 return new Mips64ELTargetInfo(Triple); 5753 } 5754 5755 case llvm::Triple::le32: 5756 switch (os) { 5757 case llvm::Triple::NaCl: 5758 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5759 default: 5760 return NULL; 5761 } 5762 5763 case llvm::Triple::ppc: 5764 if (Triple.isOSDarwin()) 5765 return new DarwinPPC32TargetInfo(Triple); 5766 switch (os) { 5767 case llvm::Triple::Linux: 5768 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5769 case llvm::Triple::FreeBSD: 5770 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5771 case llvm::Triple::NetBSD: 5772 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5773 case llvm::Triple::OpenBSD: 5774 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5775 case llvm::Triple::RTEMS: 5776 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5777 default: 5778 return new PPC32TargetInfo(Triple); 5779 } 5780 5781 case llvm::Triple::ppc64: 5782 if (Triple.isOSDarwin()) 5783 return new DarwinPPC64TargetInfo(Triple); 5784 switch (os) { 5785 case llvm::Triple::Linux: 5786 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5787 case llvm::Triple::Lv2: 5788 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5789 case llvm::Triple::FreeBSD: 5790 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5791 case llvm::Triple::NetBSD: 5792 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5793 default: 5794 return new PPC64TargetInfo(Triple); 5795 } 5796 5797 case llvm::Triple::ppc64le: 5798 switch (os) { 5799 case llvm::Triple::Linux: 5800 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5801 default: 5802 return new PPC64TargetInfo(Triple); 5803 } 5804 5805 case llvm::Triple::nvptx: 5806 return new NVPTX32TargetInfo(Triple); 5807 case llvm::Triple::nvptx64: 5808 return new NVPTX64TargetInfo(Triple); 5809 5810 case llvm::Triple::r600: 5811 return new R600TargetInfo(Triple); 5812 5813 case llvm::Triple::sparc: 5814 switch (os) { 5815 case llvm::Triple::Linux: 5816 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5817 case llvm::Triple::AuroraUX: 5818 return new AuroraUXSparcV8TargetInfo(Triple); 5819 case llvm::Triple::Solaris: 5820 return new SolarisSparcV8TargetInfo(Triple); 5821 case llvm::Triple::NetBSD: 5822 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5823 case llvm::Triple::OpenBSD: 5824 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5825 case llvm::Triple::RTEMS: 5826 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5827 default: 5828 return new SparcV8TargetInfo(Triple); 5829 } 5830 5831 case llvm::Triple::sparcv9: 5832 switch (os) { 5833 case llvm::Triple::Linux: 5834 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5835 case llvm::Triple::AuroraUX: 5836 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5837 case llvm::Triple::Solaris: 5838 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5839 case llvm::Triple::NetBSD: 5840 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5841 case llvm::Triple::OpenBSD: 5842 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5843 case llvm::Triple::FreeBSD: 5844 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5845 default: 5846 return new SparcV9TargetInfo(Triple); 5847 } 5848 5849 case llvm::Triple::systemz: 5850 switch (os) { 5851 case llvm::Triple::Linux: 5852 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5853 default: 5854 return new SystemZTargetInfo(Triple); 5855 } 5856 5857 case llvm::Triple::tce: 5858 return new TCETargetInfo(Triple); 5859 5860 case llvm::Triple::x86: 5861 if (Triple.isOSDarwin()) 5862 return new DarwinI386TargetInfo(Triple); 5863 5864 switch (os) { 5865 case llvm::Triple::AuroraUX: 5866 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5867 case llvm::Triple::Linux: 5868 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5869 case llvm::Triple::DragonFly: 5870 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5871 case llvm::Triple::NetBSD: 5872 return new NetBSDI386TargetInfo(Triple); 5873 case llvm::Triple::OpenBSD: 5874 return new OpenBSDI386TargetInfo(Triple); 5875 case llvm::Triple::Bitrig: 5876 return new BitrigI386TargetInfo(Triple); 5877 case llvm::Triple::FreeBSD: 5878 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5879 case llvm::Triple::KFreeBSD: 5880 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5881 case llvm::Triple::Minix: 5882 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5883 case llvm::Triple::Solaris: 5884 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5885 case llvm::Triple::Cygwin: 5886 return new CygwinX86_32TargetInfo(Triple); 5887 case llvm::Triple::MinGW32: 5888 return new MinGWX86_32TargetInfo(Triple); 5889 case llvm::Triple::Win32: 5890 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5891 case llvm::Triple::Haiku: 5892 return new HaikuX86_32TargetInfo(Triple); 5893 case llvm::Triple::RTEMS: 5894 return new RTEMSX86_32TargetInfo(Triple); 5895 case llvm::Triple::NaCl: 5896 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5897 default: 5898 return new X86_32TargetInfo(Triple); 5899 } 5900 5901 case llvm::Triple::x86_64: 5902 if (Triple.isOSDarwin() || Triple.getObjectFormat() == llvm::Triple::MachO) 5903 return new DarwinX86_64TargetInfo(Triple); 5904 5905 switch (os) { 5906 case llvm::Triple::AuroraUX: 5907 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5908 case llvm::Triple::Linux: 5909 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5910 case llvm::Triple::DragonFly: 5911 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5912 case llvm::Triple::NetBSD: 5913 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5914 case llvm::Triple::OpenBSD: 5915 return new OpenBSDX86_64TargetInfo(Triple); 5916 case llvm::Triple::Bitrig: 5917 return new BitrigX86_64TargetInfo(Triple); 5918 case llvm::Triple::FreeBSD: 5919 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5920 case llvm::Triple::KFreeBSD: 5921 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5922 case llvm::Triple::Solaris: 5923 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5924 case llvm::Triple::MinGW32: 5925 return new MinGWX86_64TargetInfo(Triple); 5926 case llvm::Triple::Win32: // This is what Triple.h supports now. 5927 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5928 case llvm::Triple::NaCl: 5929 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5930 default: 5931 return new X86_64TargetInfo(Triple); 5932 } 5933 5934 case llvm::Triple::spir: { 5935 if (Triple.getOS() != llvm::Triple::UnknownOS || 5936 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5937 return NULL; 5938 return new SPIR32TargetInfo(Triple); 5939 } 5940 case llvm::Triple::spir64: { 5941 if (Triple.getOS() != llvm::Triple::UnknownOS || 5942 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5943 return NULL; 5944 return new SPIR64TargetInfo(Triple); 5945 } 5946 } 5947 } 5948 5949 /// CreateTargetInfo - Return the target info object for the specified target 5950 /// triple. 5951 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5952 TargetOptions *Opts) { 5953 llvm::Triple Triple(Opts->Triple); 5954 5955 // Construct the target 5956 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 5957 if (!Target) { 5958 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5959 return 0; 5960 } 5961 Target->setTargetOpts(Opts); 5962 5963 // Set the target CPU if specified. 5964 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5965 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5966 return 0; 5967 } 5968 5969 // Set the target ABI if specified. 5970 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5971 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5972 return 0; 5973 } 5974 5975 // Set the fp math unit. 5976 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5977 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5978 return 0; 5979 } 5980 5981 // Compute the default target features, we need the target to handle this 5982 // because features may have dependencies on one another. 5983 llvm::StringMap<bool> Features; 5984 Target->getDefaultFeatures(Features); 5985 5986 // Apply the user specified deltas. 5987 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5988 I < N; ++I) { 5989 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5990 // Apply the feature via the target. 5991 bool Enabled = Name[0] == '+'; 5992 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5993 } 5994 5995 // Add the features to the compile options. 5996 // 5997 // FIXME: If we are completely confident that we have the right set, we only 5998 // need to pass the minuses. 5999 Opts->Features.clear(); 6000 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6001 ie = Features.end(); it != ie; ++it) 6002 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6003 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6004 return 0; 6005 6006 return Target.release(); 6007 } 6008