1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/ADT/StringSwitch.h" 26 #include "llvm/ADT/Triple.h" 27 #include "llvm/IR/Type.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 97 98 if (!Opts.ObjCAutoRefCount) { 99 // __weak is always defined, for use in blocks and with objc pointers. 100 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 101 102 // Darwin defines __strong even in C mode (just to nothing). 103 if (Opts.getGC() != LangOptions::NonGC) 104 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 105 else 106 Builder.defineMacro("__strong", ""); 107 108 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 109 // allow this in C, since one might have block pointers in structs that 110 // are used in pure C code and in Objective-C ARC. 111 Builder.defineMacro("__unsafe_unretained", ""); 112 } 113 114 if (Opts.Static) 115 Builder.defineMacro("__STATIC__"); 116 else 117 Builder.defineMacro("__DYNAMIC__"); 118 119 if (Opts.POSIXThreads) 120 Builder.defineMacro("_REENTRANT"); 121 122 // Get the platform type and version number from the triple. 123 unsigned Maj, Min, Rev; 124 if (Triple.isMacOSX()) { 125 Triple.getMacOSXVersion(Maj, Min, Rev); 126 PlatformName = "macosx"; 127 } else { 128 Triple.getOSVersion(Maj, Min, Rev); 129 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 130 } 131 132 // If -target arch-pc-win32-macho option specified, we're 133 // generating code for Win32 ABI. No need to emit 134 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 135 if (PlatformName == "win32") { 136 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 137 return; 138 } 139 140 // Set the appropriate OS version define. 141 if (Triple.isiOS()) { 142 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 143 char Str[6]; 144 Str[0] = '0' + Maj; 145 Str[1] = '0' + (Min / 10); 146 Str[2] = '0' + (Min % 10); 147 Str[3] = '0' + (Rev / 10); 148 Str[4] = '0' + (Rev % 10); 149 Str[5] = '\0'; 150 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 151 Str); 152 } else if (Triple.isMacOSX()) { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 158 char Str[5]; 159 Str[0] = '0' + (Maj / 10); 160 Str[1] = '0' + (Maj % 10); 161 Str[2] = '0' + std::min(Min, 9U); 162 Str[3] = '0' + std::min(Rev, 9U); 163 Str[4] = '\0'; 164 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 165 } 166 167 // Tell users about the kernel if there is one. 168 if (Triple.isOSDarwin()) 169 Builder.defineMacro("__MACH__"); 170 171 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 172 } 173 174 namespace { 175 template<typename Target> 176 class DarwinTargetInfo : public OSTargetInfo<Target> { 177 protected: 178 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 179 MacroBuilder &Builder) const override { 180 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 181 this->PlatformMinVersion); 182 } 183 184 public: 185 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 186 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 187 this->MCountName = "\01mcount"; 188 } 189 190 std::string isValidSectionSpecifier(StringRef SR) const override { 191 // Let MCSectionMachO validate this. 192 StringRef Segment, Section; 193 unsigned TAA, StubSize; 194 bool HasTAA; 195 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 196 TAA, HasTAA, StubSize); 197 } 198 199 const char *getStaticInitSectionSpecifier() const override { 200 // FIXME: We should return 0 when building kexts. 201 return "__TEXT,__StaticInit,regular,pure_instructions"; 202 } 203 204 /// Darwin does not support protected visibility. Darwin's "default" 205 /// is very similar to ELF's "protected"; Darwin requires a "weak" 206 /// attribute on declarations that can be dynamically replaced. 207 bool hasProtectedVisibility() const override { 208 return false; 209 } 210 }; 211 212 213 // DragonFlyBSD Target 214 template<typename Target> 215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 216 protected: 217 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 218 MacroBuilder &Builder) const override { 219 // DragonFly defines; list based off of gcc output 220 Builder.defineMacro("__DragonFly__"); 221 Builder.defineMacro("__DragonFly_cc_version", "100001"); 222 Builder.defineMacro("__ELF__"); 223 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 224 Builder.defineMacro("__tune_i386__"); 225 DefineStd(Builder, "unix", Opts); 226 } 227 public: 228 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 229 : OSTargetInfo<Target>(Triple) { 230 this->UserLabelPrefix = ""; 231 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const override { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 260 // On FreeBSD, wchar_t contains the number of the code point as 261 // used by the character set of the locale. These character sets are 262 // not necessarily a superset of ASCII. 263 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 264 } 265 public: 266 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 267 this->UserLabelPrefix = ""; 268 269 switch (Triple.getArch()) { 270 default: 271 case llvm::Triple::x86: 272 case llvm::Triple::x86_64: 273 this->MCountName = ".mcount"; 274 break; 275 case llvm::Triple::mips: 276 case llvm::Triple::mipsel: 277 case llvm::Triple::ppc: 278 case llvm::Triple::ppc64: 279 case llvm::Triple::ppc64le: 280 this->MCountName = "_mcount"; 281 break; 282 case llvm::Triple::arm: 283 this->MCountName = "__mcount"; 284 break; 285 } 286 } 287 }; 288 289 // GNU/kFreeBSD Target 290 template<typename Target> 291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 292 protected: 293 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 294 MacroBuilder &Builder) const override { 295 // GNU/kFreeBSD defines; list based off of gcc output 296 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__FreeBSD_kernel__"); 299 Builder.defineMacro("__GLIBC__"); 300 Builder.defineMacro("__ELF__"); 301 if (Opts.POSIXThreads) 302 Builder.defineMacro("_REENTRANT"); 303 if (Opts.CPlusPlus) 304 Builder.defineMacro("_GNU_SOURCE"); 305 } 306 public: 307 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 308 this->UserLabelPrefix = ""; 309 } 310 }; 311 312 // Minix Target 313 template<typename Target> 314 class MinixTargetInfo : public OSTargetInfo<Target> { 315 protected: 316 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 317 MacroBuilder &Builder) const override { 318 // Minix defines 319 320 Builder.defineMacro("__minix", "3"); 321 Builder.defineMacro("_EM_WSIZE", "4"); 322 Builder.defineMacro("_EM_PSIZE", "4"); 323 Builder.defineMacro("_EM_SSIZE", "2"); 324 Builder.defineMacro("_EM_LSIZE", "4"); 325 Builder.defineMacro("_EM_FSIZE", "4"); 326 Builder.defineMacro("_EM_DSIZE", "8"); 327 Builder.defineMacro("__ELF__"); 328 DefineStd(Builder, "unix", Opts); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const override { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 359 switch (Triple.getArch()) { 360 default: 361 break; 362 case llvm::Triple::ppc: 363 case llvm::Triple::ppc64: 364 case llvm::Triple::ppc64le: 365 this->MCountName = "_mcount"; 366 break; 367 } 368 } 369 370 const char *getStaticInitSectionSpecifier() const override { 371 return ".text.startup"; 372 } 373 }; 374 375 // NetBSD Target 376 template<typename Target> 377 class NetBSDTargetInfo : public OSTargetInfo<Target> { 378 protected: 379 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 380 MacroBuilder &Builder) const override { 381 // NetBSD defines; list based off of gcc output 382 Builder.defineMacro("__NetBSD__"); 383 Builder.defineMacro("__unix__"); 384 Builder.defineMacro("__ELF__"); 385 if (Opts.POSIXThreads) 386 Builder.defineMacro("_POSIX_THREADS"); 387 } 388 public: 389 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 390 this->UserLabelPrefix = ""; 391 } 392 }; 393 394 // OpenBSD Target 395 template<typename Target> 396 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 397 protected: 398 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 399 MacroBuilder &Builder) const override { 400 // OpenBSD defines; list based off of gcc output 401 402 Builder.defineMacro("__OpenBSD__"); 403 DefineStd(Builder, "unix", Opts); 404 Builder.defineMacro("__ELF__"); 405 if (Opts.POSIXThreads) 406 Builder.defineMacro("_REENTRANT"); 407 } 408 public: 409 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 410 this->UserLabelPrefix = ""; 411 this->TLSSupported = false; 412 413 switch (Triple.getArch()) { 414 default: 415 case llvm::Triple::x86: 416 case llvm::Triple::x86_64: 417 case llvm::Triple::arm: 418 case llvm::Triple::sparc: 419 this->MCountName = "__mcount"; 420 break; 421 case llvm::Triple::mips64: 422 case llvm::Triple::mips64el: 423 case llvm::Triple::ppc: 424 case llvm::Triple::sparcv9: 425 this->MCountName = "_mcount"; 426 break; 427 } 428 } 429 }; 430 431 // Bitrig Target 432 template<typename Target> 433 class BitrigTargetInfo : public OSTargetInfo<Target> { 434 protected: 435 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 436 MacroBuilder &Builder) const override { 437 // Bitrig defines; list based off of gcc output 438 439 Builder.defineMacro("__Bitrig__"); 440 DefineStd(Builder, "unix", Opts); 441 Builder.defineMacro("__ELF__"); 442 if (Opts.POSIXThreads) 443 Builder.defineMacro("_REENTRANT"); 444 } 445 public: 446 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->TLSSupported = false; 449 this->MCountName = "__mcount"; 450 } 451 }; 452 453 // PSP Target 454 template<typename Target> 455 class PSPTargetInfo : public OSTargetInfo<Target> { 456 protected: 457 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 458 MacroBuilder &Builder) const override { 459 // PSP defines; list based on the output of the pspdev gcc toolchain. 460 Builder.defineMacro("PSP"); 461 Builder.defineMacro("_PSP"); 462 Builder.defineMacro("__psp__"); 463 Builder.defineMacro("__ELF__"); 464 } 465 public: 466 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 467 this->UserLabelPrefix = ""; 468 } 469 }; 470 471 // PS3 PPU Target 472 template<typename Target> 473 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 474 protected: 475 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 476 MacroBuilder &Builder) const override { 477 // PS3 PPU defines. 478 Builder.defineMacro("__PPC__"); 479 Builder.defineMacro("__PPU__"); 480 Builder.defineMacro("__CELLOS_LV2__"); 481 Builder.defineMacro("__ELF__"); 482 Builder.defineMacro("__LP32__"); 483 Builder.defineMacro("_ARCH_PPC64"); 484 Builder.defineMacro("__powerpc64__"); 485 } 486 public: 487 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 488 this->UserLabelPrefix = ""; 489 this->LongWidth = this->LongAlign = 32; 490 this->PointerWidth = this->PointerAlign = 32; 491 this->IntMaxType = TargetInfo::SignedLongLong; 492 this->UIntMaxType = TargetInfo::UnsignedLongLong; 493 this->Int64Type = TargetInfo::SignedLongLong; 494 this->SizeType = TargetInfo::UnsignedInt; 495 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 496 } 497 }; 498 499 // AuroraUX target 500 template<typename Target> 501 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 502 protected: 503 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 504 MacroBuilder &Builder) const override { 505 DefineStd(Builder, "sun", Opts); 506 DefineStd(Builder, "unix", Opts); 507 Builder.defineMacro("__ELF__"); 508 Builder.defineMacro("__svr4__"); 509 Builder.defineMacro("__SVR4"); 510 } 511 public: 512 AuroraUXTargetInfo(const llvm::Triple &Triple) 513 : OSTargetInfo<Target>(Triple) { 514 this->UserLabelPrefix = ""; 515 this->WCharType = this->SignedLong; 516 // FIXME: WIntType should be SignedLong 517 } 518 }; 519 520 // Solaris target 521 template<typename Target> 522 class SolarisTargetInfo : public OSTargetInfo<Target> { 523 protected: 524 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 525 MacroBuilder &Builder) const override { 526 DefineStd(Builder, "sun", Opts); 527 DefineStd(Builder, "unix", Opts); 528 Builder.defineMacro("__ELF__"); 529 Builder.defineMacro("__svr4__"); 530 Builder.defineMacro("__SVR4"); 531 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 532 // newer, but to 500 for everything else. feature_test.h has a check to 533 // ensure that you are not using C99 with an old version of X/Open or C89 534 // with a new version. 535 if (Opts.C99 || Opts.C11) 536 Builder.defineMacro("_XOPEN_SOURCE", "600"); 537 else 538 Builder.defineMacro("_XOPEN_SOURCE", "500"); 539 if (Opts.CPlusPlus) 540 Builder.defineMacro("__C99FEATURES__"); 541 Builder.defineMacro("_LARGEFILE_SOURCE"); 542 Builder.defineMacro("_LARGEFILE64_SOURCE"); 543 Builder.defineMacro("__EXTENSIONS__"); 544 Builder.defineMacro("_REENTRANT"); 545 } 546 public: 547 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 548 this->UserLabelPrefix = ""; 549 this->WCharType = this->SignedInt; 550 // FIXME: WIntType should be SignedLong 551 } 552 }; 553 554 // Windows target 555 template<typename Target> 556 class WindowsTargetInfo : public OSTargetInfo<Target> { 557 protected: 558 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 559 MacroBuilder &Builder) const override { 560 Builder.defineMacro("_WIN32"); 561 } 562 void getVisualStudioDefines(const LangOptions &Opts, 563 MacroBuilder &Builder) const { 564 if (Opts.CPlusPlus) { 565 if (Opts.RTTI) 566 Builder.defineMacro("_CPPRTTI"); 567 568 if (Opts.Exceptions) 569 Builder.defineMacro("_CPPUNWIND"); 570 } 571 572 if (!Opts.CharIsSigned) 573 Builder.defineMacro("_CHAR_UNSIGNED"); 574 575 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 576 // but it works for now. 577 if (Opts.POSIXThreads) 578 Builder.defineMacro("_MT"); 579 580 if (Opts.MSCVersion != 0) 581 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 582 583 if (Opts.MicrosoftExt) { 584 Builder.defineMacro("_MSC_EXTENSIONS"); 585 586 if (Opts.CPlusPlus11) { 587 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 588 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 589 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 590 } 591 } 592 593 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 594 } 595 596 public: 597 WindowsTargetInfo(const llvm::Triple &Triple) 598 : OSTargetInfo<Target>(Triple) {} 599 }; 600 601 template <typename Target> 602 class NaClTargetInfo : public OSTargetInfo<Target> { 603 protected: 604 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 605 MacroBuilder &Builder) const override { 606 if (Opts.POSIXThreads) 607 Builder.defineMacro("_REENTRANT"); 608 if (Opts.CPlusPlus) 609 Builder.defineMacro("_GNU_SOURCE"); 610 611 DefineStd(Builder, "unix", Opts); 612 Builder.defineMacro("__ELF__"); 613 Builder.defineMacro("__native_client__"); 614 } 615 616 public: 617 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 618 this->UserLabelPrefix = ""; 619 this->LongAlign = 32; 620 this->LongWidth = 32; 621 this->PointerAlign = 32; 622 this->PointerWidth = 32; 623 this->IntMaxType = TargetInfo::SignedLongLong; 624 this->UIntMaxType = TargetInfo::UnsignedLongLong; 625 this->Int64Type = TargetInfo::SignedLongLong; 626 this->DoubleAlign = 64; 627 this->LongDoubleWidth = 64; 628 this->LongDoubleAlign = 64; 629 this->LongLongWidth = 64; 630 this->LongLongAlign = 64; 631 this->SizeType = TargetInfo::UnsignedInt; 632 this->PtrDiffType = TargetInfo::SignedInt; 633 this->IntPtrType = TargetInfo::SignedInt; 634 // RegParmMax is inherited from the underlying architecture 635 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 636 if (Triple.getArch() == llvm::Triple::arm) { 637 this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128"; 638 } else if (Triple.getArch() == llvm::Triple::x86) { 639 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 640 } else if (Triple.getArch() == llvm::Triple::x86_64) { 641 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 642 } else if (Triple.getArch() == llvm::Triple::mipsel) { 643 // Handled on mips' setDescriptionString. 644 } else { 645 assert(Triple.getArch() == llvm::Triple::le32); 646 this->DescriptionString = "e-p:32:32-i64:64"; 647 } 648 } 649 typename Target::CallingConvCheckResult checkCallingConvention( 650 CallingConv CC) const override { 651 return CC == CC_PnaclCall ? Target::CCCR_OK : 652 Target::checkCallingConvention(CC); 653 } 654 }; 655 } // end anonymous namespace. 656 657 //===----------------------------------------------------------------------===// 658 // Specific target implementations. 659 //===----------------------------------------------------------------------===// 660 661 namespace { 662 // PPC abstract base class 663 class PPCTargetInfo : public TargetInfo { 664 static const Builtin::Info BuiltinInfo[]; 665 static const char * const GCCRegNames[]; 666 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 667 std::string CPU; 668 669 // Target cpu features. 670 bool HasVSX; 671 672 public: 673 PPCTargetInfo(const llvm::Triple &Triple) 674 : TargetInfo(Triple), HasVSX(false) { 675 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 676 LongDoubleWidth = LongDoubleAlign = 128; 677 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 678 } 679 680 /// \brief Flags for architecture specific defines. 681 typedef enum { 682 ArchDefineNone = 0, 683 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 684 ArchDefinePpcgr = 1 << 1, 685 ArchDefinePpcsq = 1 << 2, 686 ArchDefine440 = 1 << 3, 687 ArchDefine603 = 1 << 4, 688 ArchDefine604 = 1 << 5, 689 ArchDefinePwr4 = 1 << 6, 690 ArchDefinePwr5 = 1 << 7, 691 ArchDefinePwr5x = 1 << 8, 692 ArchDefinePwr6 = 1 << 9, 693 ArchDefinePwr6x = 1 << 10, 694 ArchDefinePwr7 = 1 << 11, 695 ArchDefineA2 = 1 << 12, 696 ArchDefineA2q = 1 << 13 697 } ArchDefineTypes; 698 699 // Note: GCC recognizes the following additional cpus: 700 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 701 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 702 // titan, rs64. 703 bool setCPU(const std::string &Name) override { 704 bool CPUKnown = llvm::StringSwitch<bool>(Name) 705 .Case("generic", true) 706 .Case("440", true) 707 .Case("450", true) 708 .Case("601", true) 709 .Case("602", true) 710 .Case("603", true) 711 .Case("603e", true) 712 .Case("603ev", true) 713 .Case("604", true) 714 .Case("604e", true) 715 .Case("620", true) 716 .Case("630", true) 717 .Case("g3", true) 718 .Case("7400", true) 719 .Case("g4", true) 720 .Case("7450", true) 721 .Case("g4+", true) 722 .Case("750", true) 723 .Case("970", true) 724 .Case("g5", true) 725 .Case("a2", true) 726 .Case("a2q", true) 727 .Case("e500mc", true) 728 .Case("e5500", true) 729 .Case("power3", true) 730 .Case("pwr3", true) 731 .Case("power4", true) 732 .Case("pwr4", true) 733 .Case("power5", true) 734 .Case("pwr5", true) 735 .Case("power5x", true) 736 .Case("pwr5x", true) 737 .Case("power6", true) 738 .Case("pwr6", true) 739 .Case("power6x", true) 740 .Case("pwr6x", true) 741 .Case("power7", true) 742 .Case("pwr7", true) 743 .Case("powerpc", true) 744 .Case("ppc", true) 745 .Case("powerpc64", true) 746 .Case("ppc64", true) 747 .Case("powerpc64le", true) 748 .Case("ppc64le", true) 749 .Default(false); 750 751 if (CPUKnown) 752 CPU = Name; 753 754 return CPUKnown; 755 } 756 757 void getTargetBuiltins(const Builtin::Info *&Records, 758 unsigned &NumRecords) const override { 759 Records = BuiltinInfo; 760 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 761 } 762 763 bool isCLZForZeroUndef() const override { return false; } 764 765 void getTargetDefines(const LangOptions &Opts, 766 MacroBuilder &Builder) const override; 767 768 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 769 770 bool handleTargetFeatures(std::vector<std::string> &Features, 771 DiagnosticsEngine &Diags) override; 772 bool hasFeature(StringRef Feature) const override; 773 774 void getGCCRegNames(const char * const *&Names, 775 unsigned &NumNames) const override; 776 void getGCCRegAliases(const GCCRegAlias *&Aliases, 777 unsigned &NumAliases) const override; 778 bool validateAsmConstraint(const char *&Name, 779 TargetInfo::ConstraintInfo &Info) const override { 780 switch (*Name) { 781 default: return false; 782 case 'O': // Zero 783 break; 784 case 'b': // Base register 785 case 'f': // Floating point register 786 Info.setAllowsRegister(); 787 break; 788 // FIXME: The following are added to allow parsing. 789 // I just took a guess at what the actions should be. 790 // Also, is more specific checking needed? I.e. specific registers? 791 case 'd': // Floating point register (containing 64-bit value) 792 case 'v': // Altivec vector register 793 Info.setAllowsRegister(); 794 break; 795 case 'w': 796 switch (Name[1]) { 797 case 'd':// VSX vector register to hold vector double data 798 case 'f':// VSX vector register to hold vector float data 799 case 's':// VSX vector register to hold scalar float data 800 case 'a':// Any VSX register 801 case 'c':// An individual CR bit 802 break; 803 default: 804 return false; 805 } 806 Info.setAllowsRegister(); 807 Name++; // Skip over 'w'. 808 break; 809 case 'h': // `MQ', `CTR', or `LINK' register 810 case 'q': // `MQ' register 811 case 'c': // `CTR' register 812 case 'l': // `LINK' register 813 case 'x': // `CR' register (condition register) number 0 814 case 'y': // `CR' register (condition register) 815 case 'z': // `XER[CA]' carry bit (part of the XER register) 816 Info.setAllowsRegister(); 817 break; 818 case 'I': // Signed 16-bit constant 819 case 'J': // Unsigned 16-bit constant shifted left 16 bits 820 // (use `L' instead for SImode constants) 821 case 'K': // Unsigned 16-bit constant 822 case 'L': // Signed 16-bit constant shifted left 16 bits 823 case 'M': // Constant larger than 31 824 case 'N': // Exact power of 2 825 case 'P': // Constant whose negation is a signed 16-bit constant 826 case 'G': // Floating point constant that can be loaded into a 827 // register with one instruction per word 828 case 'H': // Integer/Floating point constant that can be loaded 829 // into a register using three instructions 830 break; 831 case 'm': // Memory operand. Note that on PowerPC targets, m can 832 // include addresses that update the base register. It 833 // is therefore only safe to use `m' in an asm statement 834 // if that asm statement accesses the operand exactly once. 835 // The asm statement must also use `%U<opno>' as a 836 // placeholder for the "update" flag in the corresponding 837 // load or store instruction. For example: 838 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 839 // is correct but: 840 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 841 // is not. Use es rather than m if you don't want the base 842 // register to be updated. 843 case 'e': 844 if (Name[1] != 's') 845 return false; 846 // es: A "stable" memory operand; that is, one which does not 847 // include any automodification of the base register. Unlike 848 // `m', this constraint can be used in asm statements that 849 // might access the operand several times, or that might not 850 // access it at all. 851 Info.setAllowsMemory(); 852 Name++; // Skip over 'e'. 853 break; 854 case 'Q': // Memory operand that is an offset from a register (it is 855 // usually better to use `m' or `es' in asm statements) 856 case 'Z': // Memory operand that is an indexed or indirect from a 857 // register (it is usually better to use `m' or `es' in 858 // asm statements) 859 Info.setAllowsMemory(); 860 Info.setAllowsRegister(); 861 break; 862 case 'R': // AIX TOC entry 863 case 'a': // Address operand that is an indexed or indirect from a 864 // register (`p' is preferable for asm statements) 865 case 'S': // Constant suitable as a 64-bit mask operand 866 case 'T': // Constant suitable as a 32-bit mask operand 867 case 'U': // System V Release 4 small data area reference 868 case 't': // AND masks that can be performed by two rldic{l, r} 869 // instructions 870 case 'W': // Vector constant that does not require memory 871 case 'j': // Vector constant that is all zeros. 872 break; 873 // End FIXME. 874 } 875 return true; 876 } 877 std::string convertConstraint(const char *&Constraint) const override { 878 std::string R; 879 switch (*Constraint) { 880 case 'e': 881 case 'w': 882 // Two-character constraint; add "^" hint for later parsing. 883 R = std::string("^") + std::string(Constraint, 2); 884 Constraint++; 885 break; 886 default: 887 return TargetInfo::convertConstraint(Constraint); 888 } 889 return R; 890 } 891 const char *getClobbers() const override { 892 return ""; 893 } 894 int getEHDataRegisterNumber(unsigned RegNo) const override { 895 if (RegNo == 0) return 3; 896 if (RegNo == 1) return 4; 897 return -1; 898 } 899 }; 900 901 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 902 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 903 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 904 ALL_LANGUAGES }, 905 #include "clang/Basic/BuiltinsPPC.def" 906 }; 907 908 /// handleTargetFeatures - Perform initialization based on the user 909 /// configured set of features. 910 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 911 DiagnosticsEngine &Diags) { 912 // Remember the maximum enabled sselevel. 913 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 914 // Ignore disabled features. 915 if (Features[i][0] == '-') 916 continue; 917 918 StringRef Feature = StringRef(Features[i]).substr(1); 919 920 if (Feature == "vsx") { 921 HasVSX = true; 922 continue; 923 } 924 925 // TODO: Finish this list and add an assert that we've handled them 926 // all. 927 } 928 929 return true; 930 } 931 932 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 933 /// #defines that are not tied to a specific subtarget. 934 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 935 MacroBuilder &Builder) const { 936 // Target identification. 937 Builder.defineMacro("__ppc__"); 938 Builder.defineMacro("__PPC__"); 939 Builder.defineMacro("_ARCH_PPC"); 940 Builder.defineMacro("__powerpc__"); 941 Builder.defineMacro("__POWERPC__"); 942 if (PointerWidth == 64) { 943 Builder.defineMacro("_ARCH_PPC64"); 944 Builder.defineMacro("__powerpc64__"); 945 Builder.defineMacro("__ppc64__"); 946 Builder.defineMacro("__PPC64__"); 947 } 948 949 // Target properties. 950 if (getTriple().getArch() == llvm::Triple::ppc64le) { 951 Builder.defineMacro("_LITTLE_ENDIAN"); 952 Builder.defineMacro("_CALL_ELF","2"); 953 } else { 954 if (getTriple().getOS() != llvm::Triple::NetBSD && 955 getTriple().getOS() != llvm::Triple::OpenBSD) 956 Builder.defineMacro("_BIG_ENDIAN"); 957 } 958 959 // Subtarget options. 960 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 961 Builder.defineMacro("__REGISTER_PREFIX__", ""); 962 963 // FIXME: Should be controlled by command line option. 964 if (LongDoubleWidth == 128) 965 Builder.defineMacro("__LONG_DOUBLE_128__"); 966 967 if (Opts.AltiVec) { 968 Builder.defineMacro("__VEC__", "10206"); 969 Builder.defineMacro("__ALTIVEC__"); 970 } 971 972 // CPU identification. 973 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 974 .Case("440", ArchDefineName) 975 .Case("450", ArchDefineName | ArchDefine440) 976 .Case("601", ArchDefineName) 977 .Case("602", ArchDefineName | ArchDefinePpcgr) 978 .Case("603", ArchDefineName | ArchDefinePpcgr) 979 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 980 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 981 .Case("604", ArchDefineName | ArchDefinePpcgr) 982 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 983 .Case("620", ArchDefineName | ArchDefinePpcgr) 984 .Case("630", ArchDefineName | ArchDefinePpcgr) 985 .Case("7400", ArchDefineName | ArchDefinePpcgr) 986 .Case("7450", ArchDefineName | ArchDefinePpcgr) 987 .Case("750", ArchDefineName | ArchDefinePpcgr) 988 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 989 | ArchDefinePpcsq) 990 .Case("a2", ArchDefineA2) 991 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 992 .Case("pwr3", ArchDefinePpcgr) 993 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 994 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 995 | ArchDefinePpcsq) 996 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 997 | ArchDefinePpcgr | ArchDefinePpcsq) 998 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 999 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1000 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1001 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1002 | ArchDefinePpcsq) 1003 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1004 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1005 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1006 .Case("power3", ArchDefinePpcgr) 1007 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1008 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1009 | ArchDefinePpcsq) 1010 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1011 | ArchDefinePpcgr | ArchDefinePpcsq) 1012 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1013 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1014 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1015 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1016 | ArchDefinePpcsq) 1017 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1018 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1019 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1020 .Default(ArchDefineNone); 1021 1022 if (defs & ArchDefineName) 1023 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1024 if (defs & ArchDefinePpcgr) 1025 Builder.defineMacro("_ARCH_PPCGR"); 1026 if (defs & ArchDefinePpcsq) 1027 Builder.defineMacro("_ARCH_PPCSQ"); 1028 if (defs & ArchDefine440) 1029 Builder.defineMacro("_ARCH_440"); 1030 if (defs & ArchDefine603) 1031 Builder.defineMacro("_ARCH_603"); 1032 if (defs & ArchDefine604) 1033 Builder.defineMacro("_ARCH_604"); 1034 if (defs & ArchDefinePwr4) 1035 Builder.defineMacro("_ARCH_PWR4"); 1036 if (defs & ArchDefinePwr5) 1037 Builder.defineMacro("_ARCH_PWR5"); 1038 if (defs & ArchDefinePwr5x) 1039 Builder.defineMacro("_ARCH_PWR5X"); 1040 if (defs & ArchDefinePwr6) 1041 Builder.defineMacro("_ARCH_PWR6"); 1042 if (defs & ArchDefinePwr6x) 1043 Builder.defineMacro("_ARCH_PWR6X"); 1044 if (defs & ArchDefinePwr7) 1045 Builder.defineMacro("_ARCH_PWR7"); 1046 if (defs & ArchDefineA2) 1047 Builder.defineMacro("_ARCH_A2"); 1048 if (defs & ArchDefineA2q) { 1049 Builder.defineMacro("_ARCH_A2Q"); 1050 Builder.defineMacro("_ARCH_QP"); 1051 } 1052 1053 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1054 Builder.defineMacro("__bg__"); 1055 Builder.defineMacro("__THW_BLUEGENE__"); 1056 Builder.defineMacro("__bgq__"); 1057 Builder.defineMacro("__TOS_BGQ__"); 1058 } 1059 1060 if (HasVSX) 1061 Builder.defineMacro("__VSX__"); 1062 1063 // FIXME: The following are not yet generated here by Clang, but are 1064 // generated by GCC: 1065 // 1066 // _SOFT_FLOAT_ 1067 // __RECIP_PRECISION__ 1068 // __APPLE_ALTIVEC__ 1069 // __RECIP__ 1070 // __RECIPF__ 1071 // __RSQRTE__ 1072 // __RSQRTEF__ 1073 // _SOFT_DOUBLE_ 1074 // __NO_LWSYNC__ 1075 // __HAVE_BSWAP__ 1076 // __LONGDOUBLE128 1077 // __CMODEL_MEDIUM__ 1078 // __CMODEL_LARGE__ 1079 // _CALL_SYSV 1080 // _CALL_DARWIN 1081 // __NO_FPRS__ 1082 } 1083 1084 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1085 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1086 .Case("7400", true) 1087 .Case("g4", true) 1088 .Case("7450", true) 1089 .Case("g4+", true) 1090 .Case("970", true) 1091 .Case("g5", true) 1092 .Case("pwr6", true) 1093 .Case("pwr7", true) 1094 .Case("ppc64", true) 1095 .Case("ppc64le", true) 1096 .Default(false); 1097 1098 Features["qpx"] = (CPU == "a2q"); 1099 } 1100 1101 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1102 return Feature == "powerpc"; 1103 } 1104 1105 1106 const char * const PPCTargetInfo::GCCRegNames[] = { 1107 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1108 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1109 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1110 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1111 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1112 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1113 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1114 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1115 "mq", "lr", "ctr", "ap", 1116 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1117 "xer", 1118 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1119 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1120 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1121 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1122 "vrsave", "vscr", 1123 "spe_acc", "spefscr", 1124 "sfp" 1125 }; 1126 1127 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1128 unsigned &NumNames) const { 1129 Names = GCCRegNames; 1130 NumNames = llvm::array_lengthof(GCCRegNames); 1131 } 1132 1133 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1134 // While some of these aliases do map to different registers 1135 // they still share the same register name. 1136 { { "0" }, "r0" }, 1137 { { "1"}, "r1" }, 1138 { { "2" }, "r2" }, 1139 { { "3" }, "r3" }, 1140 { { "4" }, "r4" }, 1141 { { "5" }, "r5" }, 1142 { { "6" }, "r6" }, 1143 { { "7" }, "r7" }, 1144 { { "8" }, "r8" }, 1145 { { "9" }, "r9" }, 1146 { { "10" }, "r10" }, 1147 { { "11" }, "r11" }, 1148 { { "12" }, "r12" }, 1149 { { "13" }, "r13" }, 1150 { { "14" }, "r14" }, 1151 { { "15" }, "r15" }, 1152 { { "16" }, "r16" }, 1153 { { "17" }, "r17" }, 1154 { { "18" }, "r18" }, 1155 { { "19" }, "r19" }, 1156 { { "20" }, "r20" }, 1157 { { "21" }, "r21" }, 1158 { { "22" }, "r22" }, 1159 { { "23" }, "r23" }, 1160 { { "24" }, "r24" }, 1161 { { "25" }, "r25" }, 1162 { { "26" }, "r26" }, 1163 { { "27" }, "r27" }, 1164 { { "28" }, "r28" }, 1165 { { "29" }, "r29" }, 1166 { { "30" }, "r30" }, 1167 { { "31" }, "r31" }, 1168 { { "fr0" }, "f0" }, 1169 { { "fr1" }, "f1" }, 1170 { { "fr2" }, "f2" }, 1171 { { "fr3" }, "f3" }, 1172 { { "fr4" }, "f4" }, 1173 { { "fr5" }, "f5" }, 1174 { { "fr6" }, "f6" }, 1175 { { "fr7" }, "f7" }, 1176 { { "fr8" }, "f8" }, 1177 { { "fr9" }, "f9" }, 1178 { { "fr10" }, "f10" }, 1179 { { "fr11" }, "f11" }, 1180 { { "fr12" }, "f12" }, 1181 { { "fr13" }, "f13" }, 1182 { { "fr14" }, "f14" }, 1183 { { "fr15" }, "f15" }, 1184 { { "fr16" }, "f16" }, 1185 { { "fr17" }, "f17" }, 1186 { { "fr18" }, "f18" }, 1187 { { "fr19" }, "f19" }, 1188 { { "fr20" }, "f20" }, 1189 { { "fr21" }, "f21" }, 1190 { { "fr22" }, "f22" }, 1191 { { "fr23" }, "f23" }, 1192 { { "fr24" }, "f24" }, 1193 { { "fr25" }, "f25" }, 1194 { { "fr26" }, "f26" }, 1195 { { "fr27" }, "f27" }, 1196 { { "fr28" }, "f28" }, 1197 { { "fr29" }, "f29" }, 1198 { { "fr30" }, "f30" }, 1199 { { "fr31" }, "f31" }, 1200 { { "cc" }, "cr0" }, 1201 }; 1202 1203 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1204 unsigned &NumAliases) const { 1205 Aliases = GCCRegAliases; 1206 NumAliases = llvm::array_lengthof(GCCRegAliases); 1207 } 1208 } // end anonymous namespace. 1209 1210 namespace { 1211 class PPC32TargetInfo : public PPCTargetInfo { 1212 public: 1213 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1214 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1215 1216 switch (getTriple().getOS()) { 1217 case llvm::Triple::Linux: 1218 case llvm::Triple::FreeBSD: 1219 case llvm::Triple::NetBSD: 1220 SizeType = UnsignedInt; 1221 PtrDiffType = SignedInt; 1222 IntPtrType = SignedInt; 1223 break; 1224 default: 1225 break; 1226 } 1227 1228 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1229 LongDoubleWidth = LongDoubleAlign = 64; 1230 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1231 } 1232 1233 // PPC32 supports atomics up to 4 bytes. 1234 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1235 } 1236 1237 BuiltinVaListKind getBuiltinVaListKind() const override { 1238 // This is the ELF definition, and is overridden by the Darwin sub-target 1239 return TargetInfo::PowerABIBuiltinVaList; 1240 } 1241 }; 1242 } // end anonymous namespace. 1243 1244 // Note: ABI differences may eventually require us to have a separate 1245 // TargetInfo for little endian. 1246 namespace { 1247 class PPC64TargetInfo : public PPCTargetInfo { 1248 public: 1249 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1250 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1251 IntMaxType = SignedLong; 1252 UIntMaxType = UnsignedLong; 1253 Int64Type = SignedLong; 1254 1255 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1256 LongDoubleWidth = LongDoubleAlign = 64; 1257 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1258 DescriptionString = "E-m:e-i64:64-n32:64"; 1259 } else { 1260 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1261 DescriptionString = "e-m:e-i64:64-n32:64"; 1262 } else { 1263 DescriptionString = "E-m:e-i64:64-n32:64"; 1264 } 1265 } 1266 1267 // PPC64 supports atomics up to 8 bytes. 1268 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1269 } 1270 BuiltinVaListKind getBuiltinVaListKind() const override { 1271 return TargetInfo::CharPtrBuiltinVaList; 1272 } 1273 }; 1274 } // end anonymous namespace. 1275 1276 1277 namespace { 1278 class DarwinPPC32TargetInfo : 1279 public DarwinTargetInfo<PPC32TargetInfo> { 1280 public: 1281 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1282 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1283 HasAlignMac68kSupport = true; 1284 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1285 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1286 LongLongAlign = 32; 1287 SuitableAlign = 128; 1288 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1289 } 1290 BuiltinVaListKind getBuiltinVaListKind() const override { 1291 return TargetInfo::CharPtrBuiltinVaList; 1292 } 1293 }; 1294 1295 class DarwinPPC64TargetInfo : 1296 public DarwinTargetInfo<PPC64TargetInfo> { 1297 public: 1298 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1299 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1300 HasAlignMac68kSupport = true; 1301 SuitableAlign = 128; 1302 DescriptionString = "E-m:o-i64:64-n32:64"; 1303 } 1304 }; 1305 } // end anonymous namespace. 1306 1307 namespace { 1308 static const unsigned NVPTXAddrSpaceMap[] = { 1309 1, // opencl_global 1310 3, // opencl_local 1311 4, // opencl_constant 1312 1, // cuda_device 1313 4, // cuda_constant 1314 3, // cuda_shared 1315 }; 1316 class NVPTXTargetInfo : public TargetInfo { 1317 static const char * const GCCRegNames[]; 1318 static const Builtin::Info BuiltinInfo[]; 1319 public: 1320 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1321 BigEndian = false; 1322 TLSSupported = false; 1323 LongWidth = LongAlign = 64; 1324 AddrSpaceMap = &NVPTXAddrSpaceMap; 1325 UseAddrSpaceMapMangling = true; 1326 // Define available target features 1327 // These must be defined in sorted order! 1328 NoAsmVariants = true; 1329 } 1330 void getTargetDefines(const LangOptions &Opts, 1331 MacroBuilder &Builder) const override { 1332 Builder.defineMacro("__PTX__"); 1333 Builder.defineMacro("__NVPTX__"); 1334 } 1335 void getTargetBuiltins(const Builtin::Info *&Records, 1336 unsigned &NumRecords) const override { 1337 Records = BuiltinInfo; 1338 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1339 } 1340 bool hasFeature(StringRef Feature) const override { 1341 return Feature == "ptx" || Feature == "nvptx"; 1342 } 1343 1344 void getGCCRegNames(const char * const *&Names, 1345 unsigned &NumNames) const override; 1346 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1347 unsigned &NumAliases) const override { 1348 // No aliases. 1349 Aliases = 0; 1350 NumAliases = 0; 1351 } 1352 bool validateAsmConstraint(const char *&Name, 1353 TargetInfo::ConstraintInfo &Info) const override { 1354 switch (*Name) { 1355 default: return false; 1356 case 'c': 1357 case 'h': 1358 case 'r': 1359 case 'l': 1360 case 'f': 1361 case 'd': 1362 Info.setAllowsRegister(); 1363 return true; 1364 } 1365 } 1366 const char *getClobbers() const override { 1367 // FIXME: Is this really right? 1368 return ""; 1369 } 1370 BuiltinVaListKind getBuiltinVaListKind() const override { 1371 // FIXME: implement 1372 return TargetInfo::CharPtrBuiltinVaList; 1373 } 1374 bool setCPU(const std::string &Name) override { 1375 bool Valid = llvm::StringSwitch<bool>(Name) 1376 .Case("sm_20", true) 1377 .Case("sm_21", true) 1378 .Case("sm_30", true) 1379 .Case("sm_35", true) 1380 .Default(false); 1381 1382 return Valid; 1383 } 1384 }; 1385 1386 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1387 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1388 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1389 ALL_LANGUAGES }, 1390 #include "clang/Basic/BuiltinsNVPTX.def" 1391 }; 1392 1393 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1394 "r0" 1395 }; 1396 1397 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1398 unsigned &NumNames) const { 1399 Names = GCCRegNames; 1400 NumNames = llvm::array_lengthof(GCCRegNames); 1401 } 1402 1403 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1404 public: 1405 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1406 PointerWidth = PointerAlign = 32; 1407 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1408 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1409 } 1410 }; 1411 1412 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1413 public: 1414 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1415 PointerWidth = PointerAlign = 64; 1416 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1417 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1418 } 1419 }; 1420 } 1421 1422 namespace { 1423 1424 static const unsigned R600AddrSpaceMap[] = { 1425 1, // opencl_global 1426 3, // opencl_local 1427 2, // opencl_constant 1428 1, // cuda_device 1429 2, // cuda_constant 1430 3 // cuda_shared 1431 }; 1432 1433 static const char *DescriptionStringR600 = 1434 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1435 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1436 1437 static const char *DescriptionStringR600DoubleOps = 1438 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1439 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1440 1441 static const char *DescriptionStringSI = 1442 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:64:64" 1443 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1444 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1445 1446 class R600TargetInfo : public TargetInfo { 1447 /// \brief The GPU profiles supported by the R600 target. 1448 enum GPUKind { 1449 GK_NONE, 1450 GK_R600, 1451 GK_R600_DOUBLE_OPS, 1452 GK_R700, 1453 GK_R700_DOUBLE_OPS, 1454 GK_EVERGREEN, 1455 GK_EVERGREEN_DOUBLE_OPS, 1456 GK_NORTHERN_ISLANDS, 1457 GK_CAYMAN, 1458 GK_SOUTHERN_ISLANDS, 1459 GK_SEA_ISLANDS 1460 } GPU; 1461 1462 public: 1463 R600TargetInfo(const llvm::Triple &Triple) 1464 : TargetInfo(Triple), GPU(GK_R600) { 1465 DescriptionString = DescriptionStringR600; 1466 AddrSpaceMap = &R600AddrSpaceMap; 1467 UseAddrSpaceMapMangling = true; 1468 } 1469 1470 const char * getClobbers() const override { 1471 return ""; 1472 } 1473 1474 void getGCCRegNames(const char * const *&Names, 1475 unsigned &numNames) const override { 1476 Names = NULL; 1477 numNames = 0; 1478 } 1479 1480 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1481 unsigned &NumAliases) const override { 1482 Aliases = NULL; 1483 NumAliases = 0; 1484 } 1485 1486 bool validateAsmConstraint(const char *&Name, 1487 TargetInfo::ConstraintInfo &info) const override { 1488 return true; 1489 } 1490 1491 void getTargetBuiltins(const Builtin::Info *&Records, 1492 unsigned &NumRecords) const override { 1493 Records = NULL; 1494 NumRecords = 0; 1495 } 1496 1497 1498 void getTargetDefines(const LangOptions &Opts, 1499 MacroBuilder &Builder) const override { 1500 Builder.defineMacro("__R600__"); 1501 } 1502 1503 BuiltinVaListKind getBuiltinVaListKind() const override { 1504 return TargetInfo::CharPtrBuiltinVaList; 1505 } 1506 1507 bool setCPU(const std::string &Name) override { 1508 GPU = llvm::StringSwitch<GPUKind>(Name) 1509 .Case("r600" , GK_R600) 1510 .Case("rv610", GK_R600) 1511 .Case("rv620", GK_R600) 1512 .Case("rv630", GK_R600) 1513 .Case("rv635", GK_R600) 1514 .Case("rs780", GK_R600) 1515 .Case("rs880", GK_R600) 1516 .Case("rv670", GK_R600_DOUBLE_OPS) 1517 .Case("rv710", GK_R700) 1518 .Case("rv730", GK_R700) 1519 .Case("rv740", GK_R700_DOUBLE_OPS) 1520 .Case("rv770", GK_R700_DOUBLE_OPS) 1521 .Case("palm", GK_EVERGREEN) 1522 .Case("cedar", GK_EVERGREEN) 1523 .Case("sumo", GK_EVERGREEN) 1524 .Case("sumo2", GK_EVERGREEN) 1525 .Case("redwood", GK_EVERGREEN) 1526 .Case("juniper", GK_EVERGREEN) 1527 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1528 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1529 .Case("barts", GK_NORTHERN_ISLANDS) 1530 .Case("turks", GK_NORTHERN_ISLANDS) 1531 .Case("caicos", GK_NORTHERN_ISLANDS) 1532 .Case("cayman", GK_CAYMAN) 1533 .Case("aruba", GK_CAYMAN) 1534 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1535 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1536 .Case("verde", GK_SOUTHERN_ISLANDS) 1537 .Case("oland", GK_SOUTHERN_ISLANDS) 1538 .Case("bonaire", GK_SEA_ISLANDS) 1539 .Case("kabini", GK_SEA_ISLANDS) 1540 .Case("kaveri", GK_SEA_ISLANDS) 1541 .Case("hawaii", GK_SEA_ISLANDS) 1542 .Default(GK_NONE); 1543 1544 if (GPU == GK_NONE) { 1545 return false; 1546 } 1547 1548 // Set the correct data layout 1549 switch (GPU) { 1550 case GK_NONE: 1551 case GK_R600: 1552 case GK_R700: 1553 case GK_EVERGREEN: 1554 case GK_NORTHERN_ISLANDS: 1555 DescriptionString = DescriptionStringR600; 1556 break; 1557 case GK_R600_DOUBLE_OPS: 1558 case GK_R700_DOUBLE_OPS: 1559 case GK_EVERGREEN_DOUBLE_OPS: 1560 case GK_CAYMAN: 1561 DescriptionString = DescriptionStringR600DoubleOps; 1562 break; 1563 case GK_SOUTHERN_ISLANDS: 1564 case GK_SEA_ISLANDS: 1565 DescriptionString = DescriptionStringSI; 1566 break; 1567 } 1568 1569 return true; 1570 } 1571 }; 1572 1573 } // end anonymous namespace 1574 1575 namespace { 1576 // Namespace for x86 abstract base class 1577 const Builtin::Info BuiltinInfo[] = { 1578 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1579 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1580 ALL_LANGUAGES }, 1581 #include "clang/Basic/BuiltinsX86.def" 1582 }; 1583 1584 static const char* const GCCRegNames[] = { 1585 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1586 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1587 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1588 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1589 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1590 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1591 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1592 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1593 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1594 }; 1595 1596 const TargetInfo::AddlRegName AddlRegNames[] = { 1597 { { "al", "ah", "eax", "rax" }, 0 }, 1598 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1599 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1600 { { "dl", "dh", "edx", "rdx" }, 1 }, 1601 { { "esi", "rsi" }, 4 }, 1602 { { "edi", "rdi" }, 5 }, 1603 { { "esp", "rsp" }, 7 }, 1604 { { "ebp", "rbp" }, 6 }, 1605 }; 1606 1607 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1608 // most of the implementation can be shared. 1609 class X86TargetInfo : public TargetInfo { 1610 enum X86SSEEnum { 1611 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1612 } SSELevel; 1613 enum MMX3DNowEnum { 1614 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1615 } MMX3DNowLevel; 1616 enum XOPEnum { 1617 NoXOP, 1618 SSE4A, 1619 FMA4, 1620 XOP 1621 } XOPLevel; 1622 1623 bool HasAES; 1624 bool HasPCLMUL; 1625 bool HasLZCNT; 1626 bool HasRDRND; 1627 bool HasBMI; 1628 bool HasBMI2; 1629 bool HasPOPCNT; 1630 bool HasRTM; 1631 bool HasPRFCHW; 1632 bool HasRDSEED; 1633 bool HasTBM; 1634 bool HasFMA; 1635 bool HasF16C; 1636 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1637 bool HasSHA; 1638 bool HasCX16; 1639 1640 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1641 /// 1642 /// Each enumeration represents a particular CPU supported by Clang. These 1643 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1644 enum CPUKind { 1645 CK_Generic, 1646 1647 /// \name i386 1648 /// i386-generation processors. 1649 //@{ 1650 CK_i386, 1651 //@} 1652 1653 /// \name i486 1654 /// i486-generation processors. 1655 //@{ 1656 CK_i486, 1657 CK_WinChipC6, 1658 CK_WinChip2, 1659 CK_C3, 1660 //@} 1661 1662 /// \name i586 1663 /// i586-generation processors, P5 microarchitecture based. 1664 //@{ 1665 CK_i586, 1666 CK_Pentium, 1667 CK_PentiumMMX, 1668 //@} 1669 1670 /// \name i686 1671 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1672 //@{ 1673 CK_i686, 1674 CK_PentiumPro, 1675 CK_Pentium2, 1676 CK_Pentium3, 1677 CK_Pentium3M, 1678 CK_PentiumM, 1679 CK_C3_2, 1680 1681 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1682 /// Clang however has some logic to suport this. 1683 // FIXME: Warn, deprecate, and potentially remove this. 1684 CK_Yonah, 1685 //@} 1686 1687 /// \name Netburst 1688 /// Netburst microarchitecture based processors. 1689 //@{ 1690 CK_Pentium4, 1691 CK_Pentium4M, 1692 CK_Prescott, 1693 CK_Nocona, 1694 //@} 1695 1696 /// \name Core 1697 /// Core microarchitecture based processors. 1698 //@{ 1699 CK_Core2, 1700 1701 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1702 /// codename which GCC no longer accepts as an option to -march, but Clang 1703 /// has some logic for recognizing it. 1704 // FIXME: Warn, deprecate, and potentially remove this. 1705 CK_Penryn, 1706 //@} 1707 1708 /// \name Atom 1709 /// Atom processors 1710 //@{ 1711 CK_Atom, 1712 CK_Silvermont, 1713 //@} 1714 1715 /// \name Nehalem 1716 /// Nehalem microarchitecture based processors. 1717 //@{ 1718 CK_Corei7, 1719 CK_Corei7AVX, 1720 CK_CoreAVXi, 1721 CK_CoreAVX2, 1722 //@} 1723 1724 /// \name Knights Landing 1725 /// Knights Landing processor. 1726 CK_KNL, 1727 1728 /// \name K6 1729 /// K6 architecture processors. 1730 //@{ 1731 CK_K6, 1732 CK_K6_2, 1733 CK_K6_3, 1734 //@} 1735 1736 /// \name K7 1737 /// K7 architecture processors. 1738 //@{ 1739 CK_Athlon, 1740 CK_AthlonThunderbird, 1741 CK_Athlon4, 1742 CK_AthlonXP, 1743 CK_AthlonMP, 1744 //@} 1745 1746 /// \name K8 1747 /// K8 architecture processors. 1748 //@{ 1749 CK_Athlon64, 1750 CK_Athlon64SSE3, 1751 CK_AthlonFX, 1752 CK_K8, 1753 CK_K8SSE3, 1754 CK_Opteron, 1755 CK_OpteronSSE3, 1756 CK_AMDFAM10, 1757 //@} 1758 1759 /// \name Bobcat 1760 /// Bobcat architecture processors. 1761 //@{ 1762 CK_BTVER1, 1763 CK_BTVER2, 1764 //@} 1765 1766 /// \name Bulldozer 1767 /// Bulldozer architecture processors. 1768 //@{ 1769 CK_BDVER1, 1770 CK_BDVER2, 1771 CK_BDVER3, 1772 //@} 1773 1774 /// This specification is deprecated and will be removed in the future. 1775 /// Users should prefer \see CK_K8. 1776 // FIXME: Warn on this when the CPU is set to it. 1777 CK_x86_64, 1778 //@} 1779 1780 /// \name Geode 1781 /// Geode processors. 1782 //@{ 1783 CK_Geode 1784 //@} 1785 } CPU; 1786 1787 enum FPMathKind { 1788 FP_Default, 1789 FP_SSE, 1790 FP_387 1791 } FPMath; 1792 1793 public: 1794 X86TargetInfo(const llvm::Triple &Triple) 1795 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1796 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1797 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1798 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1799 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1800 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1801 FPMath(FP_Default) { 1802 BigEndian = false; 1803 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1804 } 1805 unsigned getFloatEvalMethod() const override { 1806 // X87 evaluates with 80 bits "long double" precision. 1807 return SSELevel == NoSSE ? 2 : 0; 1808 } 1809 void getTargetBuiltins(const Builtin::Info *&Records, 1810 unsigned &NumRecords) const override { 1811 Records = BuiltinInfo; 1812 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1813 } 1814 void getGCCRegNames(const char * const *&Names, 1815 unsigned &NumNames) const override { 1816 Names = GCCRegNames; 1817 NumNames = llvm::array_lengthof(GCCRegNames); 1818 } 1819 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1820 unsigned &NumAliases) const override { 1821 Aliases = 0; 1822 NumAliases = 0; 1823 } 1824 void getGCCAddlRegNames(const AddlRegName *&Names, 1825 unsigned &NumNames) const override { 1826 Names = AddlRegNames; 1827 NumNames = llvm::array_lengthof(AddlRegNames); 1828 } 1829 bool validateAsmConstraint(const char *&Name, 1830 TargetInfo::ConstraintInfo &info) const override; 1831 std::string convertConstraint(const char *&Constraint) const override; 1832 const char *getClobbers() const override { 1833 return "~{dirflag},~{fpsr},~{flags}"; 1834 } 1835 void getTargetDefines(const LangOptions &Opts, 1836 MacroBuilder &Builder) const override; 1837 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1838 bool Enabled); 1839 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1840 bool Enabled); 1841 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1842 bool Enabled); 1843 void setFeatureEnabled(llvm::StringMap<bool> &Features, 1844 StringRef Name, bool Enabled) const override { 1845 setFeatureEnabledImpl(Features, Name, Enabled); 1846 } 1847 // This exists purely to cut down on the number of virtual calls in 1848 // getDefaultFeatures which calls this repeatedly. 1849 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1850 StringRef Name, bool Enabled); 1851 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 1852 bool hasFeature(StringRef Feature) const override; 1853 bool handleTargetFeatures(std::vector<std::string> &Features, 1854 DiagnosticsEngine &Diags) override; 1855 const char* getABI() const override { 1856 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1857 return "avx"; 1858 else if (getTriple().getArch() == llvm::Triple::x86 && 1859 MMX3DNowLevel == NoMMX3DNow) 1860 return "no-mmx"; 1861 return ""; 1862 } 1863 bool setCPU(const std::string &Name) override { 1864 CPU = llvm::StringSwitch<CPUKind>(Name) 1865 .Case("i386", CK_i386) 1866 .Case("i486", CK_i486) 1867 .Case("winchip-c6", CK_WinChipC6) 1868 .Case("winchip2", CK_WinChip2) 1869 .Case("c3", CK_C3) 1870 .Case("i586", CK_i586) 1871 .Case("pentium", CK_Pentium) 1872 .Case("pentium-mmx", CK_PentiumMMX) 1873 .Case("i686", CK_i686) 1874 .Case("pentiumpro", CK_PentiumPro) 1875 .Case("pentium2", CK_Pentium2) 1876 .Case("pentium3", CK_Pentium3) 1877 .Case("pentium3m", CK_Pentium3M) 1878 .Case("pentium-m", CK_PentiumM) 1879 .Case("c3-2", CK_C3_2) 1880 .Case("yonah", CK_Yonah) 1881 .Case("pentium4", CK_Pentium4) 1882 .Case("pentium4m", CK_Pentium4M) 1883 .Case("prescott", CK_Prescott) 1884 .Case("nocona", CK_Nocona) 1885 .Case("core2", CK_Core2) 1886 .Case("penryn", CK_Penryn) 1887 .Case("atom", CK_Atom) 1888 .Case("slm", CK_Silvermont) 1889 .Case("corei7", CK_Corei7) 1890 .Case("corei7-avx", CK_Corei7AVX) 1891 .Case("core-avx-i", CK_CoreAVXi) 1892 .Case("core-avx2", CK_CoreAVX2) 1893 .Case("knl", CK_KNL) 1894 .Case("k6", CK_K6) 1895 .Case("k6-2", CK_K6_2) 1896 .Case("k6-3", CK_K6_3) 1897 .Case("athlon", CK_Athlon) 1898 .Case("athlon-tbird", CK_AthlonThunderbird) 1899 .Case("athlon-4", CK_Athlon4) 1900 .Case("athlon-xp", CK_AthlonXP) 1901 .Case("athlon-mp", CK_AthlonMP) 1902 .Case("athlon64", CK_Athlon64) 1903 .Case("athlon64-sse3", CK_Athlon64SSE3) 1904 .Case("athlon-fx", CK_AthlonFX) 1905 .Case("k8", CK_K8) 1906 .Case("k8-sse3", CK_K8SSE3) 1907 .Case("opteron", CK_Opteron) 1908 .Case("opteron-sse3", CK_OpteronSSE3) 1909 .Case("amdfam10", CK_AMDFAM10) 1910 .Case("btver1", CK_BTVER1) 1911 .Case("btver2", CK_BTVER2) 1912 .Case("bdver1", CK_BDVER1) 1913 .Case("bdver2", CK_BDVER2) 1914 .Case("bdver3", CK_BDVER3) 1915 .Case("x86-64", CK_x86_64) 1916 .Case("geode", CK_Geode) 1917 .Default(CK_Generic); 1918 1919 // Perform any per-CPU checks necessary to determine if this CPU is 1920 // acceptable. 1921 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1922 // invalid without explaining *why*. 1923 switch (CPU) { 1924 case CK_Generic: 1925 // No processor selected! 1926 return false; 1927 1928 case CK_i386: 1929 case CK_i486: 1930 case CK_WinChipC6: 1931 case CK_WinChip2: 1932 case CK_C3: 1933 case CK_i586: 1934 case CK_Pentium: 1935 case CK_PentiumMMX: 1936 case CK_i686: 1937 case CK_PentiumPro: 1938 case CK_Pentium2: 1939 case CK_Pentium3: 1940 case CK_Pentium3M: 1941 case CK_PentiumM: 1942 case CK_Yonah: 1943 case CK_C3_2: 1944 case CK_Pentium4: 1945 case CK_Pentium4M: 1946 case CK_Prescott: 1947 case CK_K6: 1948 case CK_K6_2: 1949 case CK_K6_3: 1950 case CK_Athlon: 1951 case CK_AthlonThunderbird: 1952 case CK_Athlon4: 1953 case CK_AthlonXP: 1954 case CK_AthlonMP: 1955 case CK_Geode: 1956 // Only accept certain architectures when compiling in 32-bit mode. 1957 if (getTriple().getArch() != llvm::Triple::x86) 1958 return false; 1959 1960 // Fallthrough 1961 case CK_Nocona: 1962 case CK_Core2: 1963 case CK_Penryn: 1964 case CK_Atom: 1965 case CK_Silvermont: 1966 case CK_Corei7: 1967 case CK_Corei7AVX: 1968 case CK_CoreAVXi: 1969 case CK_CoreAVX2: 1970 case CK_KNL: 1971 case CK_Athlon64: 1972 case CK_Athlon64SSE3: 1973 case CK_AthlonFX: 1974 case CK_K8: 1975 case CK_K8SSE3: 1976 case CK_Opteron: 1977 case CK_OpteronSSE3: 1978 case CK_AMDFAM10: 1979 case CK_BTVER1: 1980 case CK_BTVER2: 1981 case CK_BDVER1: 1982 case CK_BDVER2: 1983 case CK_BDVER3: 1984 case CK_x86_64: 1985 return true; 1986 } 1987 llvm_unreachable("Unhandled CPU kind"); 1988 } 1989 1990 bool setFPMath(StringRef Name) override; 1991 1992 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1993 // We accept all non-ARM calling conventions 1994 return (CC == CC_X86ThisCall || 1995 CC == CC_X86FastCall || 1996 CC == CC_X86StdCall || 1997 CC == CC_C || 1998 CC == CC_X86Pascal || 1999 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2000 } 2001 2002 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2003 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2004 } 2005 }; 2006 2007 bool X86TargetInfo::setFPMath(StringRef Name) { 2008 if (Name == "387") { 2009 FPMath = FP_387; 2010 return true; 2011 } 2012 if (Name == "sse") { 2013 FPMath = FP_SSE; 2014 return true; 2015 } 2016 return false; 2017 } 2018 2019 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2020 // FIXME: This *really* should not be here. 2021 2022 // X86_64 always has SSE2. 2023 if (getTriple().getArch() == llvm::Triple::x86_64) 2024 setFeatureEnabledImpl(Features, "sse2", true); 2025 2026 switch (CPU) { 2027 case CK_Generic: 2028 case CK_i386: 2029 case CK_i486: 2030 case CK_i586: 2031 case CK_Pentium: 2032 case CK_i686: 2033 case CK_PentiumPro: 2034 break; 2035 case CK_PentiumMMX: 2036 case CK_Pentium2: 2037 setFeatureEnabledImpl(Features, "mmx", true); 2038 break; 2039 case CK_Pentium3: 2040 case CK_Pentium3M: 2041 setFeatureEnabledImpl(Features, "sse", true); 2042 break; 2043 case CK_PentiumM: 2044 case CK_Pentium4: 2045 case CK_Pentium4M: 2046 case CK_x86_64: 2047 setFeatureEnabledImpl(Features, "sse2", true); 2048 break; 2049 case CK_Yonah: 2050 case CK_Prescott: 2051 case CK_Nocona: 2052 setFeatureEnabledImpl(Features, "sse3", true); 2053 setFeatureEnabledImpl(Features, "cx16", true); 2054 break; 2055 case CK_Core2: 2056 setFeatureEnabledImpl(Features, "ssse3", true); 2057 setFeatureEnabledImpl(Features, "cx16", true); 2058 break; 2059 case CK_Penryn: 2060 setFeatureEnabledImpl(Features, "sse4.1", true); 2061 setFeatureEnabledImpl(Features, "cx16", true); 2062 break; 2063 case CK_Atom: 2064 setFeatureEnabledImpl(Features, "ssse3", true); 2065 setFeatureEnabledImpl(Features, "cx16", true); 2066 break; 2067 case CK_Silvermont: 2068 setFeatureEnabledImpl(Features, "sse4.2", true); 2069 setFeatureEnabledImpl(Features, "aes", true); 2070 setFeatureEnabledImpl(Features, "cx16", true); 2071 setFeatureEnabledImpl(Features, "pclmul", true); 2072 break; 2073 case CK_Corei7: 2074 setFeatureEnabledImpl(Features, "sse4.2", true); 2075 setFeatureEnabledImpl(Features, "cx16", true); 2076 break; 2077 case CK_Corei7AVX: 2078 setFeatureEnabledImpl(Features, "avx", true); 2079 setFeatureEnabledImpl(Features, "aes", true); 2080 setFeatureEnabledImpl(Features, "cx16", true); 2081 setFeatureEnabledImpl(Features, "pclmul", true); 2082 break; 2083 case CK_CoreAVXi: 2084 setFeatureEnabledImpl(Features, "avx", true); 2085 setFeatureEnabledImpl(Features, "aes", true); 2086 setFeatureEnabledImpl(Features, "pclmul", true); 2087 setFeatureEnabledImpl(Features, "rdrnd", true); 2088 setFeatureEnabledImpl(Features, "f16c", true); 2089 break; 2090 case CK_CoreAVX2: 2091 setFeatureEnabledImpl(Features, "avx2", true); 2092 setFeatureEnabledImpl(Features, "aes", true); 2093 setFeatureEnabledImpl(Features, "pclmul", true); 2094 setFeatureEnabledImpl(Features, "lzcnt", true); 2095 setFeatureEnabledImpl(Features, "rdrnd", true); 2096 setFeatureEnabledImpl(Features, "f16c", true); 2097 setFeatureEnabledImpl(Features, "bmi", true); 2098 setFeatureEnabledImpl(Features, "bmi2", true); 2099 setFeatureEnabledImpl(Features, "rtm", true); 2100 setFeatureEnabledImpl(Features, "fma", true); 2101 setFeatureEnabledImpl(Features, "cx16", true); 2102 break; 2103 case CK_KNL: 2104 setFeatureEnabledImpl(Features, "avx512f", true); 2105 setFeatureEnabledImpl(Features, "avx512cd", true); 2106 setFeatureEnabledImpl(Features, "avx512er", true); 2107 setFeatureEnabledImpl(Features, "avx512pf", true); 2108 setFeatureEnabledImpl(Features, "aes", true); 2109 setFeatureEnabledImpl(Features, "pclmul", true); 2110 setFeatureEnabledImpl(Features, "lzcnt", true); 2111 setFeatureEnabledImpl(Features, "rdrnd", true); 2112 setFeatureEnabledImpl(Features, "f16c", true); 2113 setFeatureEnabledImpl(Features, "bmi", true); 2114 setFeatureEnabledImpl(Features, "bmi2", true); 2115 setFeatureEnabledImpl(Features, "rtm", true); 2116 setFeatureEnabledImpl(Features, "fma", true); 2117 break; 2118 case CK_K6: 2119 case CK_WinChipC6: 2120 setFeatureEnabledImpl(Features, "mmx", true); 2121 break; 2122 case CK_K6_2: 2123 case CK_K6_3: 2124 case CK_WinChip2: 2125 case CK_C3: 2126 setFeatureEnabledImpl(Features, "3dnow", true); 2127 break; 2128 case CK_Athlon: 2129 case CK_AthlonThunderbird: 2130 case CK_Geode: 2131 setFeatureEnabledImpl(Features, "3dnowa", true); 2132 break; 2133 case CK_Athlon4: 2134 case CK_AthlonXP: 2135 case CK_AthlonMP: 2136 setFeatureEnabledImpl(Features, "sse", true); 2137 setFeatureEnabledImpl(Features, "3dnowa", true); 2138 break; 2139 case CK_K8: 2140 case CK_Opteron: 2141 case CK_Athlon64: 2142 case CK_AthlonFX: 2143 setFeatureEnabledImpl(Features, "sse2", true); 2144 setFeatureEnabledImpl(Features, "3dnowa", true); 2145 break; 2146 case CK_K8SSE3: 2147 case CK_OpteronSSE3: 2148 case CK_Athlon64SSE3: 2149 setFeatureEnabledImpl(Features, "sse3", true); 2150 setFeatureEnabledImpl(Features, "3dnowa", true); 2151 break; 2152 case CK_AMDFAM10: 2153 setFeatureEnabledImpl(Features, "sse3", true); 2154 setFeatureEnabledImpl(Features, "sse4a", true); 2155 setFeatureEnabledImpl(Features, "3dnowa", true); 2156 setFeatureEnabledImpl(Features, "lzcnt", true); 2157 setFeatureEnabledImpl(Features, "popcnt", true); 2158 break; 2159 case CK_BTVER1: 2160 setFeatureEnabledImpl(Features, "ssse3", true); 2161 setFeatureEnabledImpl(Features, "sse4a", true); 2162 setFeatureEnabledImpl(Features, "cx16", true); 2163 setFeatureEnabledImpl(Features, "lzcnt", true); 2164 setFeatureEnabledImpl(Features, "popcnt", true); 2165 setFeatureEnabledImpl(Features, "prfchw", true); 2166 break; 2167 case CK_BTVER2: 2168 setFeatureEnabledImpl(Features, "avx", true); 2169 setFeatureEnabledImpl(Features, "sse4a", true); 2170 setFeatureEnabledImpl(Features, "lzcnt", true); 2171 setFeatureEnabledImpl(Features, "aes", true); 2172 setFeatureEnabledImpl(Features, "pclmul", true); 2173 setFeatureEnabledImpl(Features, "prfchw", true); 2174 setFeatureEnabledImpl(Features, "bmi", true); 2175 setFeatureEnabledImpl(Features, "f16c", true); 2176 setFeatureEnabledImpl(Features, "cx16", true); 2177 break; 2178 case CK_BDVER1: 2179 setFeatureEnabledImpl(Features, "xop", true); 2180 setFeatureEnabledImpl(Features, "lzcnt", true); 2181 setFeatureEnabledImpl(Features, "aes", true); 2182 setFeatureEnabledImpl(Features, "pclmul", true); 2183 setFeatureEnabledImpl(Features, "prfchw", true); 2184 setFeatureEnabledImpl(Features, "cx16", true); 2185 break; 2186 case CK_BDVER2: 2187 case CK_BDVER3: 2188 setFeatureEnabledImpl(Features, "xop", true); 2189 setFeatureEnabledImpl(Features, "lzcnt", true); 2190 setFeatureEnabledImpl(Features, "aes", true); 2191 setFeatureEnabledImpl(Features, "pclmul", true); 2192 setFeatureEnabledImpl(Features, "prfchw", true); 2193 setFeatureEnabledImpl(Features, "bmi", true); 2194 setFeatureEnabledImpl(Features, "fma", true); 2195 setFeatureEnabledImpl(Features, "f16c", true); 2196 setFeatureEnabledImpl(Features, "tbm", true); 2197 setFeatureEnabledImpl(Features, "cx16", true); 2198 break; 2199 case CK_C3_2: 2200 setFeatureEnabledImpl(Features, "sse", true); 2201 break; 2202 } 2203 } 2204 2205 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2206 X86SSEEnum Level, bool Enabled) { 2207 if (Enabled) { 2208 switch (Level) { 2209 case AVX512F: 2210 Features["avx512f"] = true; 2211 case AVX2: 2212 Features["avx2"] = true; 2213 case AVX: 2214 Features["avx"] = true; 2215 case SSE42: 2216 Features["sse4.2"] = true; 2217 case SSE41: 2218 Features["sse4.1"] = true; 2219 case SSSE3: 2220 Features["ssse3"] = true; 2221 case SSE3: 2222 Features["sse3"] = true; 2223 case SSE2: 2224 Features["sse2"] = true; 2225 case SSE1: 2226 Features["sse"] = true; 2227 case NoSSE: 2228 break; 2229 } 2230 return; 2231 } 2232 2233 switch (Level) { 2234 case NoSSE: 2235 case SSE1: 2236 Features["sse"] = false; 2237 case SSE2: 2238 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2239 Features["sha"] = false; 2240 case SSE3: 2241 Features["sse3"] = false; 2242 setXOPLevel(Features, NoXOP, false); 2243 case SSSE3: 2244 Features["ssse3"] = false; 2245 case SSE41: 2246 Features["sse4.1"] = false; 2247 case SSE42: 2248 Features["sse4.2"] = false; 2249 case AVX: 2250 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2251 setXOPLevel(Features, FMA4, false); 2252 case AVX2: 2253 Features["avx2"] = false; 2254 case AVX512F: 2255 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2256 Features["avx512pf"] = false; 2257 } 2258 } 2259 2260 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2261 MMX3DNowEnum Level, bool Enabled) { 2262 if (Enabled) { 2263 switch (Level) { 2264 case AMD3DNowAthlon: 2265 Features["3dnowa"] = true; 2266 case AMD3DNow: 2267 Features["3dnow"] = true; 2268 case MMX: 2269 Features["mmx"] = true; 2270 case NoMMX3DNow: 2271 break; 2272 } 2273 return; 2274 } 2275 2276 switch (Level) { 2277 case NoMMX3DNow: 2278 case MMX: 2279 Features["mmx"] = false; 2280 case AMD3DNow: 2281 Features["3dnow"] = false; 2282 case AMD3DNowAthlon: 2283 Features["3dnowa"] = false; 2284 } 2285 } 2286 2287 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2288 bool Enabled) { 2289 if (Enabled) { 2290 switch (Level) { 2291 case XOP: 2292 Features["xop"] = true; 2293 case FMA4: 2294 Features["fma4"] = true; 2295 setSSELevel(Features, AVX, true); 2296 case SSE4A: 2297 Features["sse4a"] = true; 2298 setSSELevel(Features, SSE3, true); 2299 case NoXOP: 2300 break; 2301 } 2302 return; 2303 } 2304 2305 switch (Level) { 2306 case NoXOP: 2307 case SSE4A: 2308 Features["sse4a"] = false; 2309 case FMA4: 2310 Features["fma4"] = false; 2311 case XOP: 2312 Features["xop"] = false; 2313 } 2314 } 2315 2316 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2317 StringRef Name, bool Enabled) { 2318 // FIXME: This *really* should not be here. We need some way of translating 2319 // options into llvm subtarget features. 2320 if (Name == "sse4") 2321 Name = "sse4.2"; 2322 2323 Features[Name] = Enabled; 2324 2325 if (Name == "mmx") { 2326 setMMXLevel(Features, MMX, Enabled); 2327 } else if (Name == "sse") { 2328 setSSELevel(Features, SSE1, Enabled); 2329 } else if (Name == "sse2") { 2330 setSSELevel(Features, SSE2, Enabled); 2331 } else if (Name == "sse3") { 2332 setSSELevel(Features, SSE3, Enabled); 2333 } else if (Name == "ssse3") { 2334 setSSELevel(Features, SSSE3, Enabled); 2335 } else if (Name == "sse4.2") { 2336 setSSELevel(Features, SSE42, Enabled); 2337 } else if (Name == "sse4.1") { 2338 setSSELevel(Features, SSE41, Enabled); 2339 } else if (Name == "3dnow") { 2340 setMMXLevel(Features, AMD3DNow, Enabled); 2341 } else if (Name == "3dnowa") { 2342 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2343 } else if (Name == "aes") { 2344 if (Enabled) 2345 setSSELevel(Features, SSE2, Enabled); 2346 } else if (Name == "pclmul") { 2347 if (Enabled) 2348 setSSELevel(Features, SSE2, Enabled); 2349 } else if (Name == "avx") { 2350 setSSELevel(Features, AVX, Enabled); 2351 } else if (Name == "avx2") { 2352 setSSELevel(Features, AVX2, Enabled); 2353 } else if (Name == "avx512f") { 2354 setSSELevel(Features, AVX512F, Enabled); 2355 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2356 if (Enabled) 2357 setSSELevel(Features, AVX512F, Enabled); 2358 } else if (Name == "fma") { 2359 if (Enabled) 2360 setSSELevel(Features, AVX, Enabled); 2361 } else if (Name == "fma4") { 2362 setXOPLevel(Features, FMA4, Enabled); 2363 } else if (Name == "xop") { 2364 setXOPLevel(Features, XOP, Enabled); 2365 } else if (Name == "sse4a") { 2366 setXOPLevel(Features, SSE4A, Enabled); 2367 } else if (Name == "f16c") { 2368 if (Enabled) 2369 setSSELevel(Features, AVX, Enabled); 2370 } else if (Name == "sha") { 2371 if (Enabled) 2372 setSSELevel(Features, SSE2, Enabled); 2373 } 2374 } 2375 2376 /// handleTargetFeatures - Perform initialization based on the user 2377 /// configured set of features. 2378 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2379 DiagnosticsEngine &Diags) { 2380 // Remember the maximum enabled sselevel. 2381 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2382 // Ignore disabled features. 2383 if (Features[i][0] == '-') 2384 continue; 2385 2386 StringRef Feature = StringRef(Features[i]).substr(1); 2387 2388 if (Feature == "aes") { 2389 HasAES = true; 2390 continue; 2391 } 2392 2393 if (Feature == "pclmul") { 2394 HasPCLMUL = true; 2395 continue; 2396 } 2397 2398 if (Feature == "lzcnt") { 2399 HasLZCNT = true; 2400 continue; 2401 } 2402 2403 if (Feature == "rdrnd") { 2404 HasRDRND = true; 2405 continue; 2406 } 2407 2408 if (Feature == "bmi") { 2409 HasBMI = true; 2410 continue; 2411 } 2412 2413 if (Feature == "bmi2") { 2414 HasBMI2 = true; 2415 continue; 2416 } 2417 2418 if (Feature == "popcnt") { 2419 HasPOPCNT = true; 2420 continue; 2421 } 2422 2423 if (Feature == "rtm") { 2424 HasRTM = true; 2425 continue; 2426 } 2427 2428 if (Feature == "prfchw") { 2429 HasPRFCHW = true; 2430 continue; 2431 } 2432 2433 if (Feature == "rdseed") { 2434 HasRDSEED = true; 2435 continue; 2436 } 2437 2438 if (Feature == "tbm") { 2439 HasTBM = true; 2440 continue; 2441 } 2442 2443 if (Feature == "fma") { 2444 HasFMA = true; 2445 continue; 2446 } 2447 2448 if (Feature == "f16c") { 2449 HasF16C = true; 2450 continue; 2451 } 2452 2453 if (Feature == "avx512cd") { 2454 HasAVX512CD = true; 2455 continue; 2456 } 2457 2458 if (Feature == "avx512er") { 2459 HasAVX512ER = true; 2460 continue; 2461 } 2462 2463 if (Feature == "avx512pf") { 2464 HasAVX512PF = true; 2465 continue; 2466 } 2467 2468 if (Feature == "sha") { 2469 HasSHA = true; 2470 continue; 2471 } 2472 2473 if (Feature == "cx16") { 2474 HasCX16 = true; 2475 continue; 2476 } 2477 2478 assert(Features[i][0] == '+' && "Invalid target feature!"); 2479 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2480 .Case("avx512f", AVX512F) 2481 .Case("avx2", AVX2) 2482 .Case("avx", AVX) 2483 .Case("sse4.2", SSE42) 2484 .Case("sse4.1", SSE41) 2485 .Case("ssse3", SSSE3) 2486 .Case("sse3", SSE3) 2487 .Case("sse2", SSE2) 2488 .Case("sse", SSE1) 2489 .Default(NoSSE); 2490 SSELevel = std::max(SSELevel, Level); 2491 2492 MMX3DNowEnum ThreeDNowLevel = 2493 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2494 .Case("3dnowa", AMD3DNowAthlon) 2495 .Case("3dnow", AMD3DNow) 2496 .Case("mmx", MMX) 2497 .Default(NoMMX3DNow); 2498 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2499 2500 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2501 .Case("xop", XOP) 2502 .Case("fma4", FMA4) 2503 .Case("sse4a", SSE4A) 2504 .Default(NoXOP); 2505 XOPLevel = std::max(XOPLevel, XLevel); 2506 } 2507 2508 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2509 // Can't do this earlier because we need to be able to explicitly enable 2510 // popcnt and still disable sse4.2. 2511 if (!HasPOPCNT && SSELevel >= SSE42 && 2512 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2513 HasPOPCNT = true; 2514 Features.push_back("+popcnt"); 2515 } 2516 2517 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2518 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2519 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2520 HasPRFCHW = true; 2521 Features.push_back("+prfchw"); 2522 } 2523 2524 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2525 // matches the selected sse level. 2526 if (FPMath == FP_SSE && SSELevel < SSE1) { 2527 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2528 return false; 2529 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2530 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2531 return false; 2532 } 2533 2534 // Don't tell the backend if we're turning off mmx; it will end up disabling 2535 // SSE, which we don't want. 2536 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2537 // then enable MMX. 2538 std::vector<std::string>::iterator it; 2539 it = std::find(Features.begin(), Features.end(), "-mmx"); 2540 if (it != Features.end()) 2541 Features.erase(it); 2542 else if (SSELevel > NoSSE) 2543 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2544 return true; 2545 } 2546 2547 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2548 /// definitions for this particular subtarget. 2549 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2550 MacroBuilder &Builder) const { 2551 // Target identification. 2552 if (getTriple().getArch() == llvm::Triple::x86_64) { 2553 Builder.defineMacro("__amd64__"); 2554 Builder.defineMacro("__amd64"); 2555 Builder.defineMacro("__x86_64"); 2556 Builder.defineMacro("__x86_64__"); 2557 } else { 2558 DefineStd(Builder, "i386", Opts); 2559 } 2560 2561 // Subtarget options. 2562 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2563 // truly should be based on -mtune options. 2564 switch (CPU) { 2565 case CK_Generic: 2566 break; 2567 case CK_i386: 2568 // The rest are coming from the i386 define above. 2569 Builder.defineMacro("__tune_i386__"); 2570 break; 2571 case CK_i486: 2572 case CK_WinChipC6: 2573 case CK_WinChip2: 2574 case CK_C3: 2575 defineCPUMacros(Builder, "i486"); 2576 break; 2577 case CK_PentiumMMX: 2578 Builder.defineMacro("__pentium_mmx__"); 2579 Builder.defineMacro("__tune_pentium_mmx__"); 2580 // Fallthrough 2581 case CK_i586: 2582 case CK_Pentium: 2583 defineCPUMacros(Builder, "i586"); 2584 defineCPUMacros(Builder, "pentium"); 2585 break; 2586 case CK_Pentium3: 2587 case CK_Pentium3M: 2588 case CK_PentiumM: 2589 Builder.defineMacro("__tune_pentium3__"); 2590 // Fallthrough 2591 case CK_Pentium2: 2592 case CK_C3_2: 2593 Builder.defineMacro("__tune_pentium2__"); 2594 // Fallthrough 2595 case CK_PentiumPro: 2596 Builder.defineMacro("__tune_i686__"); 2597 Builder.defineMacro("__tune_pentiumpro__"); 2598 // Fallthrough 2599 case CK_i686: 2600 Builder.defineMacro("__i686"); 2601 Builder.defineMacro("__i686__"); 2602 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2603 Builder.defineMacro("__pentiumpro"); 2604 Builder.defineMacro("__pentiumpro__"); 2605 break; 2606 case CK_Pentium4: 2607 case CK_Pentium4M: 2608 defineCPUMacros(Builder, "pentium4"); 2609 break; 2610 case CK_Yonah: 2611 case CK_Prescott: 2612 case CK_Nocona: 2613 defineCPUMacros(Builder, "nocona"); 2614 break; 2615 case CK_Core2: 2616 case CK_Penryn: 2617 defineCPUMacros(Builder, "core2"); 2618 break; 2619 case CK_Atom: 2620 defineCPUMacros(Builder, "atom"); 2621 break; 2622 case CK_Silvermont: 2623 defineCPUMacros(Builder, "slm"); 2624 break; 2625 case CK_Corei7: 2626 case CK_Corei7AVX: 2627 case CK_CoreAVXi: 2628 case CK_CoreAVX2: 2629 defineCPUMacros(Builder, "corei7"); 2630 break; 2631 case CK_KNL: 2632 defineCPUMacros(Builder, "knl"); 2633 break; 2634 case CK_K6_2: 2635 Builder.defineMacro("__k6_2__"); 2636 Builder.defineMacro("__tune_k6_2__"); 2637 // Fallthrough 2638 case CK_K6_3: 2639 if (CPU != CK_K6_2) { // In case of fallthrough 2640 // FIXME: GCC may be enabling these in cases where some other k6 2641 // architecture is specified but -m3dnow is explicitly provided. The 2642 // exact semantics need to be determined and emulated here. 2643 Builder.defineMacro("__k6_3__"); 2644 Builder.defineMacro("__tune_k6_3__"); 2645 } 2646 // Fallthrough 2647 case CK_K6: 2648 defineCPUMacros(Builder, "k6"); 2649 break; 2650 case CK_Athlon: 2651 case CK_AthlonThunderbird: 2652 case CK_Athlon4: 2653 case CK_AthlonXP: 2654 case CK_AthlonMP: 2655 defineCPUMacros(Builder, "athlon"); 2656 if (SSELevel != NoSSE) { 2657 Builder.defineMacro("__athlon_sse__"); 2658 Builder.defineMacro("__tune_athlon_sse__"); 2659 } 2660 break; 2661 case CK_K8: 2662 case CK_K8SSE3: 2663 case CK_x86_64: 2664 case CK_Opteron: 2665 case CK_OpteronSSE3: 2666 case CK_Athlon64: 2667 case CK_Athlon64SSE3: 2668 case CK_AthlonFX: 2669 defineCPUMacros(Builder, "k8"); 2670 break; 2671 case CK_AMDFAM10: 2672 defineCPUMacros(Builder, "amdfam10"); 2673 break; 2674 case CK_BTVER1: 2675 defineCPUMacros(Builder, "btver1"); 2676 break; 2677 case CK_BTVER2: 2678 defineCPUMacros(Builder, "btver2"); 2679 break; 2680 case CK_BDVER1: 2681 defineCPUMacros(Builder, "bdver1"); 2682 break; 2683 case CK_BDVER2: 2684 defineCPUMacros(Builder, "bdver2"); 2685 break; 2686 case CK_BDVER3: 2687 defineCPUMacros(Builder, "bdver3"); 2688 break; 2689 case CK_Geode: 2690 defineCPUMacros(Builder, "geode"); 2691 break; 2692 } 2693 2694 // Target properties. 2695 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2696 2697 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2698 // functions in glibc header files that use FP Stack inline asm which the 2699 // backend can't deal with (PR879). 2700 Builder.defineMacro("__NO_MATH_INLINES"); 2701 2702 if (HasAES) 2703 Builder.defineMacro("__AES__"); 2704 2705 if (HasPCLMUL) 2706 Builder.defineMacro("__PCLMUL__"); 2707 2708 if (HasLZCNT) 2709 Builder.defineMacro("__LZCNT__"); 2710 2711 if (HasRDRND) 2712 Builder.defineMacro("__RDRND__"); 2713 2714 if (HasBMI) 2715 Builder.defineMacro("__BMI__"); 2716 2717 if (HasBMI2) 2718 Builder.defineMacro("__BMI2__"); 2719 2720 if (HasPOPCNT) 2721 Builder.defineMacro("__POPCNT__"); 2722 2723 if (HasRTM) 2724 Builder.defineMacro("__RTM__"); 2725 2726 if (HasPRFCHW) 2727 Builder.defineMacro("__PRFCHW__"); 2728 2729 if (HasRDSEED) 2730 Builder.defineMacro("__RDSEED__"); 2731 2732 if (HasTBM) 2733 Builder.defineMacro("__TBM__"); 2734 2735 switch (XOPLevel) { 2736 case XOP: 2737 Builder.defineMacro("__XOP__"); 2738 case FMA4: 2739 Builder.defineMacro("__FMA4__"); 2740 case SSE4A: 2741 Builder.defineMacro("__SSE4A__"); 2742 case NoXOP: 2743 break; 2744 } 2745 2746 if (HasFMA) 2747 Builder.defineMacro("__FMA__"); 2748 2749 if (HasF16C) 2750 Builder.defineMacro("__F16C__"); 2751 2752 if (HasAVX512CD) 2753 Builder.defineMacro("__AVX512CD__"); 2754 if (HasAVX512ER) 2755 Builder.defineMacro("__AVX512ER__"); 2756 if (HasAVX512PF) 2757 Builder.defineMacro("__AVX512PF__"); 2758 2759 if (HasSHA) 2760 Builder.defineMacro("__SHA__"); 2761 2762 if (HasCX16) 2763 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2764 2765 // Each case falls through to the previous one here. 2766 switch (SSELevel) { 2767 case AVX512F: 2768 Builder.defineMacro("__AVX512F__"); 2769 case AVX2: 2770 Builder.defineMacro("__AVX2__"); 2771 case AVX: 2772 Builder.defineMacro("__AVX__"); 2773 case SSE42: 2774 Builder.defineMacro("__SSE4_2__"); 2775 case SSE41: 2776 Builder.defineMacro("__SSE4_1__"); 2777 case SSSE3: 2778 Builder.defineMacro("__SSSE3__"); 2779 case SSE3: 2780 Builder.defineMacro("__SSE3__"); 2781 case SSE2: 2782 Builder.defineMacro("__SSE2__"); 2783 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2784 case SSE1: 2785 Builder.defineMacro("__SSE__"); 2786 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2787 case NoSSE: 2788 break; 2789 } 2790 2791 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2792 switch (SSELevel) { 2793 case AVX512F: 2794 case AVX2: 2795 case AVX: 2796 case SSE42: 2797 case SSE41: 2798 case SSSE3: 2799 case SSE3: 2800 case SSE2: 2801 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2802 break; 2803 case SSE1: 2804 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2805 break; 2806 default: 2807 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2808 } 2809 } 2810 2811 // Each case falls through to the previous one here. 2812 switch (MMX3DNowLevel) { 2813 case AMD3DNowAthlon: 2814 Builder.defineMacro("__3dNOW_A__"); 2815 case AMD3DNow: 2816 Builder.defineMacro("__3dNOW__"); 2817 case MMX: 2818 Builder.defineMacro("__MMX__"); 2819 case NoMMX3DNow: 2820 break; 2821 } 2822 2823 if (CPU >= CK_i486) { 2824 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2825 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2826 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2827 } 2828 if (CPU >= CK_i586) 2829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2830 } 2831 2832 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2833 return llvm::StringSwitch<bool>(Feature) 2834 .Case("aes", HasAES) 2835 .Case("avx", SSELevel >= AVX) 2836 .Case("avx2", SSELevel >= AVX2) 2837 .Case("avx512f", SSELevel >= AVX512F) 2838 .Case("avx512cd", HasAVX512CD) 2839 .Case("avx512er", HasAVX512ER) 2840 .Case("avx512pf", HasAVX512PF) 2841 .Case("bmi", HasBMI) 2842 .Case("bmi2", HasBMI2) 2843 .Case("cx16", HasCX16) 2844 .Case("f16c", HasF16C) 2845 .Case("fma", HasFMA) 2846 .Case("fma4", XOPLevel >= FMA4) 2847 .Case("tbm", HasTBM) 2848 .Case("lzcnt", HasLZCNT) 2849 .Case("rdrnd", HasRDRND) 2850 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2851 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2852 .Case("mmx", MMX3DNowLevel >= MMX) 2853 .Case("pclmul", HasPCLMUL) 2854 .Case("popcnt", HasPOPCNT) 2855 .Case("rtm", HasRTM) 2856 .Case("prfchw", HasPRFCHW) 2857 .Case("rdseed", HasRDSEED) 2858 .Case("sha", HasSHA) 2859 .Case("sse", SSELevel >= SSE1) 2860 .Case("sse2", SSELevel >= SSE2) 2861 .Case("sse3", SSELevel >= SSE3) 2862 .Case("ssse3", SSELevel >= SSSE3) 2863 .Case("sse4.1", SSELevel >= SSE41) 2864 .Case("sse4.2", SSELevel >= SSE42) 2865 .Case("sse4a", XOPLevel >= SSE4A) 2866 .Case("x86", true) 2867 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2868 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2869 .Case("xop", XOPLevel >= XOP) 2870 .Default(false); 2871 } 2872 2873 bool 2874 X86TargetInfo::validateAsmConstraint(const char *&Name, 2875 TargetInfo::ConstraintInfo &Info) const { 2876 switch (*Name) { 2877 default: return false; 2878 case 'Y': // first letter of a pair: 2879 switch (*(Name+1)) { 2880 default: return false; 2881 case '0': // First SSE register. 2882 case 't': // Any SSE register, when SSE2 is enabled. 2883 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2884 case 'm': // any MMX register, when inter-unit moves enabled. 2885 break; // falls through to setAllowsRegister. 2886 } 2887 case 'a': // eax. 2888 case 'b': // ebx. 2889 case 'c': // ecx. 2890 case 'd': // edx. 2891 case 'S': // esi. 2892 case 'D': // edi. 2893 case 'A': // edx:eax. 2894 case 'f': // any x87 floating point stack register. 2895 case 't': // top of floating point stack. 2896 case 'u': // second from top of floating point stack. 2897 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2898 case 'y': // Any MMX register. 2899 case 'x': // Any SSE register. 2900 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2901 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2902 case 'l': // "Index" registers: any general register that can be used as an 2903 // index in a base+index memory access. 2904 Info.setAllowsRegister(); 2905 return true; 2906 case 'C': // SSE floating point constant. 2907 case 'G': // x87 floating point constant. 2908 case 'e': // 32-bit signed integer constant for use with zero-extending 2909 // x86_64 instructions. 2910 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2911 // x86_64 instructions. 2912 return true; 2913 } 2914 } 2915 2916 2917 std::string 2918 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2919 switch (*Constraint) { 2920 case 'a': return std::string("{ax}"); 2921 case 'b': return std::string("{bx}"); 2922 case 'c': return std::string("{cx}"); 2923 case 'd': return std::string("{dx}"); 2924 case 'S': return std::string("{si}"); 2925 case 'D': return std::string("{di}"); 2926 case 'p': // address 2927 return std::string("im"); 2928 case 't': // top of floating point stack. 2929 return std::string("{st}"); 2930 case 'u': // second from top of floating point stack. 2931 return std::string("{st(1)}"); // second from top of floating point stack. 2932 default: 2933 return std::string(1, *Constraint); 2934 } 2935 } 2936 } // end anonymous namespace 2937 2938 namespace { 2939 // X86-32 generic target 2940 class X86_32TargetInfo : public X86TargetInfo { 2941 public: 2942 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2943 DoubleAlign = LongLongAlign = 32; 2944 LongDoubleWidth = 96; 2945 LongDoubleAlign = 32; 2946 SuitableAlign = 128; 2947 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 2948 SizeType = UnsignedInt; 2949 PtrDiffType = SignedInt; 2950 IntPtrType = SignedInt; 2951 RegParmMax = 3; 2952 2953 // Use fpret for all types. 2954 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2955 (1 << TargetInfo::Double) | 2956 (1 << TargetInfo::LongDouble)); 2957 2958 // x86-32 has atomics up to 8 bytes 2959 // FIXME: Check that we actually have cmpxchg8b before setting 2960 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2961 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2962 } 2963 BuiltinVaListKind getBuiltinVaListKind() const override { 2964 return TargetInfo::CharPtrBuiltinVaList; 2965 } 2966 2967 int getEHDataRegisterNumber(unsigned RegNo) const override { 2968 if (RegNo == 0) return 0; 2969 if (RegNo == 1) return 2; 2970 return -1; 2971 } 2972 bool validateInputSize(StringRef Constraint, 2973 unsigned Size) const override { 2974 switch (Constraint[0]) { 2975 default: break; 2976 case 'a': 2977 case 'b': 2978 case 'c': 2979 case 'd': 2980 return Size <= 32; 2981 } 2982 2983 return true; 2984 } 2985 }; 2986 } // end anonymous namespace 2987 2988 namespace { 2989 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2990 public: 2991 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2992 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2993 2994 unsigned getFloatEvalMethod() const override { 2995 unsigned Major, Minor, Micro; 2996 getTriple().getOSVersion(Major, Minor, Micro); 2997 // New NetBSD uses the default rounding mode. 2998 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 2999 return X86_32TargetInfo::getFloatEvalMethod(); 3000 // NetBSD before 6.99.26 defaults to "double" rounding. 3001 return 1; 3002 } 3003 }; 3004 } // end anonymous namespace 3005 3006 namespace { 3007 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3008 public: 3009 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3010 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3011 SizeType = UnsignedLong; 3012 IntPtrType = SignedLong; 3013 PtrDiffType = SignedLong; 3014 } 3015 }; 3016 } // end anonymous namespace 3017 3018 namespace { 3019 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3020 public: 3021 BitrigI386TargetInfo(const llvm::Triple &Triple) 3022 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3023 SizeType = UnsignedLong; 3024 IntPtrType = SignedLong; 3025 PtrDiffType = SignedLong; 3026 } 3027 }; 3028 } // end anonymous namespace 3029 3030 namespace { 3031 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3032 public: 3033 DarwinI386TargetInfo(const llvm::Triple &Triple) 3034 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3035 LongDoubleWidth = 128; 3036 LongDoubleAlign = 128; 3037 SuitableAlign = 128; 3038 MaxVectorAlign = 256; 3039 SizeType = UnsignedLong; 3040 IntPtrType = SignedLong; 3041 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3042 HasAlignMac68kSupport = true; 3043 } 3044 3045 }; 3046 } // end anonymous namespace 3047 3048 namespace { 3049 // x86-32 Windows target 3050 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3051 public: 3052 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3053 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3054 TLSSupported = false; 3055 WCharType = UnsignedShort; 3056 DoubleAlign = LongLongAlign = 64; 3057 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3058 } 3059 void getTargetDefines(const LangOptions &Opts, 3060 MacroBuilder &Builder) const override { 3061 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3062 } 3063 }; 3064 } // end anonymous namespace 3065 3066 namespace { 3067 3068 // x86-32 Windows Visual Studio target 3069 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3070 public: 3071 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3072 : WindowsX86_32TargetInfo(Triple) { 3073 LongDoubleWidth = LongDoubleAlign = 64; 3074 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3075 } 3076 void getTargetDefines(const LangOptions &Opts, 3077 MacroBuilder &Builder) const override { 3078 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3079 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3080 // The value of the following reflects processor type. 3081 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3082 // We lost the original triple, so we use the default. 3083 Builder.defineMacro("_M_IX86", "600"); 3084 } 3085 }; 3086 } // end anonymous namespace 3087 3088 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3089 Builder.defineMacro("__MSVCRT__"); 3090 Builder.defineMacro("__MINGW32__"); 3091 3092 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3093 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3094 // macro anyway for pre-processor compatibility. 3095 if (Opts.MicrosoftExt) 3096 Builder.defineMacro("__declspec", "__declspec"); 3097 else 3098 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3099 3100 if (!Opts.MicrosoftExt) { 3101 // Provide macros for all the calling convention keywords. Provide both 3102 // single and double underscore prefixed variants. These are available on 3103 // x64 as well as x86, even though they have no effect. 3104 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3105 for (const char *CC : CCs) { 3106 std::string GCCSpelling = "__attribute__((__"; 3107 GCCSpelling += CC; 3108 GCCSpelling += "__))"; 3109 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3110 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3111 } 3112 } 3113 } 3114 3115 namespace { 3116 // x86-32 MinGW target 3117 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3118 public: 3119 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3120 : WindowsX86_32TargetInfo(Triple) {} 3121 void getTargetDefines(const LangOptions &Opts, 3122 MacroBuilder &Builder) const override { 3123 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3124 DefineStd(Builder, "WIN32", Opts); 3125 DefineStd(Builder, "WINNT", Opts); 3126 Builder.defineMacro("_X86_"); 3127 addMinGWDefines(Opts, Builder); 3128 } 3129 }; 3130 } // end anonymous namespace 3131 3132 namespace { 3133 // x86-32 Cygwin target 3134 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3135 public: 3136 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3137 : X86_32TargetInfo(Triple) { 3138 TLSSupported = false; 3139 WCharType = UnsignedShort; 3140 DoubleAlign = LongLongAlign = 64; 3141 DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32"; 3142 } 3143 void getTargetDefines(const LangOptions &Opts, 3144 MacroBuilder &Builder) const override { 3145 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3146 Builder.defineMacro("_X86_"); 3147 Builder.defineMacro("__CYGWIN__"); 3148 Builder.defineMacro("__CYGWIN32__"); 3149 DefineStd(Builder, "unix", Opts); 3150 if (Opts.CPlusPlus) 3151 Builder.defineMacro("_GNU_SOURCE"); 3152 } 3153 }; 3154 } // end anonymous namespace 3155 3156 namespace { 3157 // x86-32 Haiku target 3158 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3159 public: 3160 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3161 SizeType = UnsignedLong; 3162 IntPtrType = SignedLong; 3163 PtrDiffType = SignedLong; 3164 ProcessIDType = SignedLong; 3165 this->UserLabelPrefix = ""; 3166 this->TLSSupported = false; 3167 } 3168 void getTargetDefines(const LangOptions &Opts, 3169 MacroBuilder &Builder) const override { 3170 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3171 Builder.defineMacro("__INTEL__"); 3172 Builder.defineMacro("__HAIKU__"); 3173 } 3174 }; 3175 } // end anonymous namespace 3176 3177 // RTEMS Target 3178 template<typename Target> 3179 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3180 protected: 3181 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3182 MacroBuilder &Builder) const override { 3183 // RTEMS defines; list based off of gcc output 3184 3185 Builder.defineMacro("__rtems__"); 3186 Builder.defineMacro("__ELF__"); 3187 } 3188 3189 public: 3190 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3191 this->UserLabelPrefix = ""; 3192 3193 switch (Triple.getArch()) { 3194 default: 3195 case llvm::Triple::x86: 3196 // this->MCountName = ".mcount"; 3197 break; 3198 case llvm::Triple::mips: 3199 case llvm::Triple::mipsel: 3200 case llvm::Triple::ppc: 3201 case llvm::Triple::ppc64: 3202 case llvm::Triple::ppc64le: 3203 // this->MCountName = "_mcount"; 3204 break; 3205 case llvm::Triple::arm: 3206 // this->MCountName = "__mcount"; 3207 break; 3208 } 3209 } 3210 }; 3211 3212 namespace { 3213 // x86-32 RTEMS target 3214 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3215 public: 3216 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3217 SizeType = UnsignedLong; 3218 IntPtrType = SignedLong; 3219 PtrDiffType = SignedLong; 3220 this->UserLabelPrefix = ""; 3221 } 3222 void getTargetDefines(const LangOptions &Opts, 3223 MacroBuilder &Builder) const override { 3224 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3225 Builder.defineMacro("__INTEL__"); 3226 Builder.defineMacro("__rtems__"); 3227 } 3228 }; 3229 } // end anonymous namespace 3230 3231 namespace { 3232 // x86-64 generic target 3233 class X86_64TargetInfo : public X86TargetInfo { 3234 public: 3235 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3236 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3237 LongDoubleWidth = 128; 3238 LongDoubleAlign = 128; 3239 LargeArrayMinWidth = 128; 3240 LargeArrayAlign = 128; 3241 SuitableAlign = 128; 3242 IntMaxType = SignedLong; 3243 UIntMaxType = UnsignedLong; 3244 Int64Type = SignedLong; 3245 RegParmMax = 6; 3246 3247 DescriptionString = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3248 3249 // Use fpret only for long double. 3250 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3251 3252 // Use fp2ret for _Complex long double. 3253 ComplexLongDoubleUsesFP2Ret = true; 3254 3255 // x86-64 has atomics up to 16 bytes. 3256 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3257 // on CPUs with cmpxchg16b 3258 MaxAtomicPromoteWidth = 128; 3259 MaxAtomicInlineWidth = 64; 3260 } 3261 BuiltinVaListKind getBuiltinVaListKind() const override { 3262 return TargetInfo::X86_64ABIBuiltinVaList; 3263 } 3264 3265 int getEHDataRegisterNumber(unsigned RegNo) const override { 3266 if (RegNo == 0) return 0; 3267 if (RegNo == 1) return 1; 3268 return -1; 3269 } 3270 3271 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3272 return (CC == CC_C || 3273 CC == CC_IntelOclBicc || 3274 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3275 } 3276 3277 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3278 return CC_C; 3279 } 3280 3281 }; 3282 } // end anonymous namespace 3283 3284 namespace { 3285 // x86-64 Windows target 3286 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3287 public: 3288 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3289 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3290 TLSSupported = false; 3291 WCharType = UnsignedShort; 3292 LongWidth = LongAlign = 32; 3293 DoubleAlign = LongLongAlign = 64; 3294 IntMaxType = SignedLongLong; 3295 UIntMaxType = UnsignedLongLong; 3296 Int64Type = SignedLongLong; 3297 SizeType = UnsignedLongLong; 3298 PtrDiffType = SignedLongLong; 3299 IntPtrType = SignedLongLong; 3300 this->UserLabelPrefix = ""; 3301 } 3302 void getTargetDefines(const LangOptions &Opts, 3303 MacroBuilder &Builder) const override { 3304 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3305 Builder.defineMacro("_WIN64"); 3306 } 3307 BuiltinVaListKind getBuiltinVaListKind() const override { 3308 return TargetInfo::CharPtrBuiltinVaList; 3309 } 3310 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3311 return (CC == CC_C || 3312 CC == CC_IntelOclBicc || 3313 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3314 } 3315 }; 3316 } // end anonymous namespace 3317 3318 namespace { 3319 // x86-64 Windows Visual Studio target 3320 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3321 public: 3322 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3323 : WindowsX86_64TargetInfo(Triple) { 3324 LongDoubleWidth = LongDoubleAlign = 64; 3325 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3326 } 3327 void getTargetDefines(const LangOptions &Opts, 3328 MacroBuilder &Builder) const override { 3329 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3330 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3331 Builder.defineMacro("_M_X64"); 3332 Builder.defineMacro("_M_AMD64"); 3333 } 3334 }; 3335 } // end anonymous namespace 3336 3337 namespace { 3338 // x86-64 MinGW target 3339 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3340 public: 3341 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3342 : WindowsX86_64TargetInfo(Triple) {} 3343 void getTargetDefines(const LangOptions &Opts, 3344 MacroBuilder &Builder) const override { 3345 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3346 DefineStd(Builder, "WIN64", Opts); 3347 Builder.defineMacro("__MINGW64__"); 3348 addMinGWDefines(Opts, Builder); 3349 } 3350 }; 3351 } // end anonymous namespace 3352 3353 namespace { 3354 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3355 public: 3356 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3357 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3358 Int64Type = SignedLongLong; 3359 MaxVectorAlign = 256; 3360 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3361 llvm::Triple T = llvm::Triple(Triple); 3362 if (T.getOS() == llvm::Triple::IOS) 3363 UseSignedCharForObjCBool = false; 3364 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3365 } 3366 }; 3367 } // end anonymous namespace 3368 3369 namespace { 3370 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3371 public: 3372 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3373 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3374 IntMaxType = SignedLongLong; 3375 UIntMaxType = UnsignedLongLong; 3376 Int64Type = SignedLongLong; 3377 } 3378 }; 3379 } // end anonymous namespace 3380 3381 namespace { 3382 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3383 public: 3384 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3385 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3386 IntMaxType = SignedLongLong; 3387 UIntMaxType = UnsignedLongLong; 3388 Int64Type = SignedLongLong; 3389 } 3390 }; 3391 } 3392 3393 namespace { 3394 class AArch64TargetInfo : public TargetInfo { 3395 virtual void setDescriptionString() = 0; 3396 static const char * const GCCRegNames[]; 3397 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3398 3399 enum FPUModeEnum { 3400 FPUMode, 3401 NeonMode 3402 }; 3403 3404 unsigned FPU; 3405 unsigned Crypto; 3406 static const Builtin::Info BuiltinInfo[]; 3407 3408 public: 3409 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3410 LongWidth = LongAlign = 64; 3411 LongDoubleWidth = LongDoubleAlign = 128; 3412 PointerWidth = PointerAlign = 64; 3413 SuitableAlign = 128; 3414 3415 WCharType = UnsignedInt; 3416 if (getTriple().getOS() == llvm::Triple::NetBSD) { 3417 WCharType = SignedInt; 3418 Int64Type = SignedLongLong; 3419 IntMaxType = SignedLongLong; 3420 UIntMaxType = UnsignedLongLong; 3421 } else { 3422 WCharType = UnsignedInt; 3423 Int64Type = SignedLong; 3424 IntMaxType = SignedLong; 3425 UIntMaxType = UnsignedLong; 3426 } 3427 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3428 3429 // AArch64 backend supports 64-bit operations at the moment. In principle 3430 // 128-bit is possible if register-pairs are used. 3431 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3432 3433 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3434 } 3435 void getTargetDefines(const LangOptions &Opts, 3436 MacroBuilder &Builder) const override { 3437 // GCC defines theses currently 3438 Builder.defineMacro("__aarch64__"); 3439 3440 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3441 Builder.defineMacro("__ARM_ACLE", "200"); 3442 Builder.defineMacro("__ARM_ARCH", "8"); 3443 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3444 3445 Builder.defineMacro("__ARM_64BIT_STATE"); 3446 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3447 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3448 3449 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3450 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3451 Builder.defineMacro("__ARM_FEATURE_FMA"); 3452 Builder.defineMacro("__ARM_FEATURE_DIV"); 3453 3454 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3455 3456 // 0xe implies support for half, single and double precision operations. 3457 Builder.defineMacro("__ARM_FP", "0xe"); 3458 3459 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3460 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3461 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3462 3463 if (Opts.FastMath || Opts.FiniteMathOnly) 3464 Builder.defineMacro("__ARM_FP_FAST"); 3465 3466 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3467 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3468 3469 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3470 Opts.ShortWChar ? "2" : "4"); 3471 3472 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3473 Opts.ShortEnums ? "1" : "4"); 3474 3475 if (FPU == NeonMode) { 3476 Builder.defineMacro("__ARM_NEON"); 3477 // 64-bit NEON supports half, single and double precision operations. 3478 Builder.defineMacro("__ARM_NEON_FP", "7"); 3479 } 3480 3481 if (Crypto) { 3482 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3483 } 3484 } 3485 void getTargetBuiltins(const Builtin::Info *&Records, 3486 unsigned &NumRecords) const override { 3487 Records = BuiltinInfo; 3488 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3489 } 3490 bool hasFeature(StringRef Feature) const override { 3491 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3492 } 3493 3494 bool setCPU(const std::string &Name) override { 3495 return llvm::StringSwitch<bool>(Name) 3496 .Case("generic", true) 3497 .Cases("cortex-a53", "cortex-a57", true) 3498 .Default(false); 3499 } 3500 3501 bool handleTargetFeatures(std::vector<std::string> &Features, 3502 DiagnosticsEngine &Diags) override { 3503 FPU = FPUMode; 3504 Crypto = 0; 3505 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3506 if (Features[i] == "+neon") 3507 FPU = NeonMode; 3508 if (Features[i] == "+crypto") 3509 Crypto = 1; 3510 } 3511 3512 setDescriptionString(); 3513 3514 return true; 3515 } 3516 3517 void getGCCRegNames(const char *const *&Names, 3518 unsigned &NumNames) const override; 3519 void getGCCRegAliases(const GCCRegAlias *&Aliases, 3520 unsigned &NumAliases) const override; 3521 3522 bool isCLZForZeroUndef() const override { return false; } 3523 3524 bool validateAsmConstraint(const char *&Name, 3525 TargetInfo::ConstraintInfo &Info) const override { 3526 switch (*Name) { 3527 default: return false; 3528 case 'w': // An FP/SIMD vector register 3529 Info.setAllowsRegister(); 3530 return true; 3531 case 'I': // Constant that can be used with an ADD instruction 3532 case 'J': // Constant that can be used with a SUB instruction 3533 case 'K': // Constant that can be used with a 32-bit logical instruction 3534 case 'L': // Constant that can be used with a 64-bit logical instruction 3535 case 'M': // Constant that can be used as a 32-bit MOV immediate 3536 case 'N': // Constant that can be used as a 64-bit MOV immediate 3537 case 'Y': // Floating point constant zero 3538 case 'Z': // Integer constant zero 3539 return true; 3540 case 'Q': // A memory reference with base register and no offset 3541 Info.setAllowsMemory(); 3542 return true; 3543 case 'S': // A symbolic address 3544 Info.setAllowsRegister(); 3545 return true; 3546 case 'U': 3547 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3548 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3549 // Usa: An absolute symbolic address 3550 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3551 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3552 } 3553 } 3554 3555 const char *getClobbers() const override { 3556 // There are no AArch64 clobbers shared by all asm statements. 3557 return ""; 3558 } 3559 3560 BuiltinVaListKind getBuiltinVaListKind() const override { 3561 return TargetInfo::AArch64ABIBuiltinVaList; 3562 } 3563 }; 3564 3565 const char * const AArch64TargetInfo::GCCRegNames[] = { 3566 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3567 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3568 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3569 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3570 3571 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3572 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3573 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3574 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3575 3576 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3577 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3578 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3579 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3580 3581 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3582 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3583 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3584 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3585 3586 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3587 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3588 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3589 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3590 3591 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3592 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3593 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3594 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3595 3596 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3597 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3598 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3599 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3600 }; 3601 3602 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3603 unsigned &NumNames) const { 3604 Names = GCCRegNames; 3605 NumNames = llvm::array_lengthof(GCCRegNames); 3606 } 3607 3608 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3609 { { "x16" }, "ip0"}, 3610 { { "x17" }, "ip1"}, 3611 { { "x29" }, "fp" }, 3612 { { "x30" }, "lr" } 3613 }; 3614 3615 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3616 unsigned &NumAliases) const { 3617 Aliases = GCCRegAliases; 3618 NumAliases = llvm::array_lengthof(GCCRegAliases); 3619 3620 } 3621 3622 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3623 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3624 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3625 ALL_LANGUAGES }, 3626 #include "clang/Basic/BuiltinsNEON.def" 3627 3628 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3629 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3630 ALL_LANGUAGES }, 3631 #include "clang/Basic/BuiltinsAArch64.def" 3632 }; 3633 3634 class AArch64leTargetInfo : public AArch64TargetInfo { 3635 void setDescriptionString() override { 3636 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 3637 } 3638 3639 public: 3640 AArch64leTargetInfo(const llvm::Triple &Triple) 3641 : AArch64TargetInfo(Triple) { 3642 BigEndian = false; 3643 } 3644 void getTargetDefines(const LangOptions &Opts, 3645 MacroBuilder &Builder) const override { 3646 Builder.defineMacro("__AARCH64EL__"); 3647 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3648 } 3649 }; 3650 3651 class AArch64beTargetInfo : public AArch64TargetInfo { 3652 void setDescriptionString() override { 3653 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 3654 } 3655 3656 public: 3657 AArch64beTargetInfo(const llvm::Triple &Triple) 3658 : AArch64TargetInfo(Triple) { } 3659 void getTargetDefines(const LangOptions &Opts, 3660 MacroBuilder &Builder) const override { 3661 Builder.defineMacro("__AARCH64EB__"); 3662 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3663 Builder.defineMacro("__ARM_BIG_ENDIAN"); 3664 AArch64TargetInfo::getTargetDefines(Opts, Builder); 3665 } 3666 }; 3667 3668 } // end anonymous namespace 3669 3670 namespace { 3671 class ARMTargetInfo : public TargetInfo { 3672 // Possible FPU choices. 3673 enum FPUMode { 3674 VFP2FPU = (1 << 0), 3675 VFP3FPU = (1 << 1), 3676 VFP4FPU = (1 << 2), 3677 NeonFPU = (1 << 3), 3678 FPARMV8 = (1 << 4) 3679 }; 3680 3681 // Possible HWDiv features. 3682 enum HWDivMode { 3683 HWDivThumb = (1 << 0), 3684 HWDivARM = (1 << 1) 3685 }; 3686 3687 static bool FPUModeIsVFP(FPUMode Mode) { 3688 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3689 } 3690 3691 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3692 static const char * const GCCRegNames[]; 3693 3694 std::string ABI, CPU; 3695 3696 enum { 3697 FP_Default, 3698 FP_VFP, 3699 FP_Neon 3700 } FPMath; 3701 3702 unsigned FPU : 5; 3703 3704 unsigned IsAAPCS : 1; 3705 unsigned IsThumb : 1; 3706 unsigned HWDiv : 2; 3707 3708 // Initialized via features. 3709 unsigned SoftFloat : 1; 3710 unsigned SoftFloatABI : 1; 3711 3712 unsigned CRC : 1; 3713 unsigned Crypto : 1; 3714 3715 static const Builtin::Info BuiltinInfo[]; 3716 3717 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3718 if (T.isOSWindows()) 3719 return true; 3720 3721 // On linux, binaries targeting old cpus call functions in libgcc to 3722 // perform atomic operations. The implementation in libgcc then calls into 3723 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3724 // is that if we assume the kernel is at least as recent as the hardware, 3725 // it is safe to use atomic instructions on armv6 and newer. 3726 if (!T.isOSLinux() && 3727 T.getOS() != llvm::Triple::FreeBSD && 3728 T.getOS() != llvm::Triple::NetBSD && 3729 T.getOS() != llvm::Triple::Bitrig) 3730 return false; 3731 StringRef ArchName = T.getArchName(); 3732 if (T.getArch() == llvm::Triple::arm || 3733 T.getArch() == llvm::Triple::armeb) { 3734 StringRef VersionStr; 3735 if (ArchName.startswith("armv")) 3736 VersionStr = ArchName.substr(4); 3737 else if (ArchName.startswith("armebv")) 3738 VersionStr = ArchName.substr(6); 3739 else 3740 return false; 3741 unsigned Version; 3742 if (VersionStr.getAsInteger(10, Version)) 3743 return false; 3744 return Version >= 6; 3745 } 3746 assert(T.getArch() == llvm::Triple::thumb || 3747 T.getArch() == llvm::Triple::thumbeb); 3748 StringRef VersionStr; 3749 if (ArchName.startswith("thumbv")) 3750 VersionStr = ArchName.substr(6); 3751 else if (ArchName.startswith("thumbebv")) 3752 VersionStr = ArchName.substr(8); 3753 else 3754 return false; 3755 unsigned Version; 3756 if (VersionStr.getAsInteger(10, Version)) 3757 return false; 3758 return Version >= 7; 3759 } 3760 3761 void setABIAAPCS() { 3762 IsAAPCS = true; 3763 3764 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3765 const llvm::Triple &T = getTriple(); 3766 3767 // size_t is unsigned long on Darwin and NetBSD. 3768 if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD) 3769 SizeType = UnsignedLong; 3770 else 3771 SizeType = UnsignedInt; 3772 3773 if (T.getOS() == llvm::Triple::NetBSD) { 3774 WCharType = SignedInt; 3775 } else { 3776 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3777 WCharType = UnsignedInt; 3778 } 3779 3780 UseBitFieldTypeAlignment = true; 3781 3782 ZeroLengthBitfieldBoundary = 0; 3783 3784 if (IsThumb) { 3785 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3786 // so set preferred for small types to 32. 3787 if (T.isOSBinFormatMachO()) { 3788 DescriptionString = BigEndian ? 3789 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3790 "v128:64:128-a:0:32-n32-S64" : 3791 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3792 "v128:64:128-a:0:32-n32-S64"; 3793 } else if (T.isOSWindows()) { 3794 // FIXME: this is invalid for WindowsCE 3795 assert(!BigEndian && "Windows on ARM does not support big endian"); 3796 DescriptionString = "e" 3797 "-m:e" 3798 "-p:32:32" 3799 "-i1:8:32-i8:8:32-i16:16:32-i64:64" 3800 "-v128:64:128" 3801 "-a:0:32" 3802 "-n32" 3803 "-S64"; 3804 } else { 3805 DescriptionString = BigEndian ? 3806 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3807 "v128:64:128-a:0:32-n32-S64" : 3808 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-" 3809 "v128:64:128-a:0:32-n32-S64"; 3810 } 3811 } else { 3812 if (T.isOSBinFormatMachO()) 3813 DescriptionString = BigEndian ? 3814 "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" : 3815 "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64"; 3816 else 3817 DescriptionString = BigEndian ? 3818 "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" : 3819 "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64"; 3820 } 3821 3822 // FIXME: Enumerated types are variable width in straight AAPCS. 3823 } 3824 3825 void setABIAPCS() { 3826 const llvm::Triple &T = getTriple(); 3827 3828 IsAAPCS = false; 3829 3830 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3831 3832 // size_t is unsigned int on FreeBSD. 3833 if (T.getOS() == llvm::Triple::FreeBSD) 3834 SizeType = UnsignedInt; 3835 else 3836 SizeType = UnsignedLong; 3837 3838 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3839 WCharType = SignedInt; 3840 3841 // Do not respect the alignment of bit-field types when laying out 3842 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3843 UseBitFieldTypeAlignment = false; 3844 3845 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3846 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3847 /// gcc. 3848 ZeroLengthBitfieldBoundary = 32; 3849 3850 if (IsThumb) { 3851 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3852 // so set preferred for small types to 32. 3853 if (T.isOSBinFormatMachO()) 3854 DescriptionString = BigEndian ? 3855 "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3856 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3857 "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3858 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3859 else 3860 DescriptionString = BigEndian ? 3861 "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3862 "-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3863 "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64" 3864 "-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3865 } else { 3866 if (T.isOSBinFormatMachO()) 3867 DescriptionString = BigEndian ? 3868 "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3869 "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3870 else 3871 DescriptionString = BigEndian ? 3872 "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" : 3873 "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 3874 } 3875 3876 // FIXME: Override "preferred align" for double and long long. 3877 } 3878 3879 public: 3880 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 3881 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 3882 IsAAPCS(true) { 3883 BigEndian = IsBigEndian; 3884 3885 switch (getTriple().getOS()) { 3886 case llvm::Triple::NetBSD: 3887 PtrDiffType = SignedLong; 3888 break; 3889 default: 3890 PtrDiffType = SignedInt; 3891 break; 3892 } 3893 3894 // {} in inline assembly are neon specifiers, not assembly variant 3895 // specifiers. 3896 NoAsmVariants = true; 3897 3898 // FIXME: Should we just treat this as a feature? 3899 IsThumb = getTriple().getArchName().startswith("thumb"); 3900 3901 setABI("aapcs-linux"); 3902 3903 // ARM targets default to using the ARM C++ ABI. 3904 TheCXXABI.set(TargetCXXABI::GenericARM); 3905 3906 // ARM has atomics up to 8 bytes 3907 MaxAtomicPromoteWidth = 64; 3908 if (shouldUseInlineAtomic(getTriple())) 3909 MaxAtomicInlineWidth = 64; 3910 3911 // Do force alignment of members that follow zero length bitfields. If 3912 // the alignment of the zero-length bitfield is greater than the member 3913 // that follows it, `bar', `bar' will be aligned as the type of the 3914 // zero length bitfield. 3915 UseZeroLengthBitfieldAlignment = true; 3916 } 3917 const char *getABI() const override { return ABI.c_str(); } 3918 bool setABI(const std::string &Name) override { 3919 ABI = Name; 3920 3921 // The defaults (above) are for AAPCS, check if we need to change them. 3922 // 3923 // FIXME: We need support for -meabi... we could just mangle it into the 3924 // name. 3925 if (Name == "apcs-gnu") { 3926 setABIAPCS(); 3927 return true; 3928 } 3929 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 3930 setABIAAPCS(); 3931 return true; 3932 } 3933 return false; 3934 } 3935 3936 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 3937 if (IsAAPCS) 3938 Features["aapcs"] = true; 3939 else 3940 Features["apcs"] = true; 3941 3942 StringRef ArchName = getTriple().getArchName(); 3943 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3944 Features["vfp2"] = true; 3945 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3946 CPU == "cortex-a9-mp") { 3947 Features["vfp3"] = true; 3948 Features["neon"] = true; 3949 } 3950 else if (CPU == "cortex-a5") { 3951 Features["vfp4"] = true; 3952 Features["neon"] = true; 3953 } else if (CPU == "swift" || CPU == "cortex-a7" || 3954 CPU == "cortex-a12" || CPU == "cortex-a15" || 3955 CPU == "krait") { 3956 Features["vfp4"] = true; 3957 Features["neon"] = true; 3958 Features["hwdiv"] = true; 3959 Features["hwdiv-arm"] = true; 3960 } else if (CPU == "cyclone") { 3961 Features["v8fp"] = true; 3962 Features["neon"] = true; 3963 Features["hwdiv"] = true; 3964 Features["hwdiv-arm"] = true; 3965 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3966 Features["fp-armv8"] = true; 3967 Features["neon"] = true; 3968 Features["hwdiv"] = true; 3969 Features["hwdiv-arm"] = true; 3970 Features["crc"] = true; 3971 Features["crypto"] = true; 3972 } else if (CPU == "cortex-r5" || 3973 // Enable the hwdiv extension for all v8a AArch32 cores by 3974 // default. 3975 ArchName == "armv8a" || ArchName == "armv8" || 3976 ArchName == "armebv8a" || ArchName == "armebv8" || 3977 ArchName == "thumbv8a" || ArchName == "thumbv8" || 3978 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 3979 Features["hwdiv"] = true; 3980 Features["hwdiv-arm"] = true; 3981 } else if (CPU == "cortex-m3" || CPU == "cortex-m4") { 3982 Features["hwdiv"] = true; 3983 } 3984 } 3985 3986 bool handleTargetFeatures(std::vector<std::string> &Features, 3987 DiagnosticsEngine &Diags) override { 3988 FPU = 0; 3989 CRC = 0; 3990 Crypto = 0; 3991 SoftFloat = SoftFloatABI = false; 3992 HWDiv = 0; 3993 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3994 if (Features[i] == "+soft-float") 3995 SoftFloat = true; 3996 else if (Features[i] == "+soft-float-abi") 3997 SoftFloatABI = true; 3998 else if (Features[i] == "+vfp2") 3999 FPU |= VFP2FPU; 4000 else if (Features[i] == "+vfp3") 4001 FPU |= VFP3FPU; 4002 else if (Features[i] == "+vfp4") 4003 FPU |= VFP4FPU; 4004 else if (Features[i] == "+fp-armv8") 4005 FPU |= FPARMV8; 4006 else if (Features[i] == "+neon") 4007 FPU |= NeonFPU; 4008 else if (Features[i] == "+hwdiv") 4009 HWDiv |= HWDivThumb; 4010 else if (Features[i] == "+hwdiv-arm") 4011 HWDiv |= HWDivARM; 4012 else if (Features[i] == "+crc") 4013 CRC = 1; 4014 else if (Features[i] == "+crypto") 4015 Crypto = 1; 4016 } 4017 4018 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4019 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4020 return false; 4021 } 4022 4023 if (FPMath == FP_Neon) 4024 Features.push_back("+neonfp"); 4025 else if (FPMath == FP_VFP) 4026 Features.push_back("-neonfp"); 4027 4028 // Remove front-end specific options which the backend handles differently. 4029 std::vector<std::string>::iterator it; 4030 it = std::find(Features.begin(), Features.end(), "+soft-float"); 4031 if (it != Features.end()) 4032 Features.erase(it); 4033 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4034 if (it != Features.end()) 4035 Features.erase(it); 4036 return true; 4037 } 4038 4039 bool hasFeature(StringRef Feature) const override { 4040 return llvm::StringSwitch<bool>(Feature) 4041 .Case("arm", true) 4042 .Case("softfloat", SoftFloat) 4043 .Case("thumb", IsThumb) 4044 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4045 .Case("hwdiv", HWDiv & HWDivThumb) 4046 .Case("hwdiv-arm", HWDiv & HWDivARM) 4047 .Default(false); 4048 } 4049 // FIXME: Should we actually have some table instead of these switches? 4050 static const char *getCPUDefineSuffix(StringRef Name) { 4051 return llvm::StringSwitch<const char*>(Name) 4052 .Cases("arm8", "arm810", "4") 4053 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 4054 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4055 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4056 .Case("ep9312", "4T") 4057 .Cases("arm10tdmi", "arm1020t", "5T") 4058 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4059 .Case("arm926ej-s", "5TEJ") 4060 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4061 .Cases("xscale", "iwmmxt", "5TE") 4062 .Case("arm1136j-s", "6J") 4063 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 4064 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 4065 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4066 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A") 4067 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A") 4068 .Cases("cortex-r4", "cortex-r5", "7R") 4069 .Case("swift", "7S") 4070 .Case("cyclone", "8A") 4071 .Cases("cortex-m3", "cortex-m4", "7M") 4072 .Case("cortex-m0", "6M") 4073 .Cases("cortex-a53", "cortex-a57", "8A") 4074 .Default(0); 4075 } 4076 static const char *getCPUProfile(StringRef Name) { 4077 return llvm::StringSwitch<const char*>(Name) 4078 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4079 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A") 4080 .Cases("cortex-a53", "cortex-a57", "A") 4081 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 4082 .Cases("cortex-r4", "cortex-r5", "R") 4083 .Default(""); 4084 } 4085 bool setCPU(const std::string &Name) override { 4086 if (!getCPUDefineSuffix(Name)) 4087 return false; 4088 4089 CPU = Name; 4090 return true; 4091 } 4092 bool setFPMath(StringRef Name) override; 4093 void getTargetDefines(const LangOptions &Opts, 4094 MacroBuilder &Builder) const override { 4095 // Target identification. 4096 Builder.defineMacro("__arm"); 4097 Builder.defineMacro("__arm__"); 4098 4099 // Target properties. 4100 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4101 4102 StringRef CPUArch = getCPUDefineSuffix(CPU); 4103 unsigned int CPUArchVer; 4104 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 4105 llvm_unreachable("Invalid char for architecture version number"); 4106 } 4107 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4108 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4109 StringRef CPUProfile = getCPUProfile(CPU); 4110 if (!CPUProfile.empty()) 4111 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 4112 4113 // Subtarget options. 4114 4115 // FIXME: It's more complicated than this and we don't really support 4116 // interworking. 4117 // Windows on ARM does not "support" interworking 4118 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4119 Builder.defineMacro("__THUMB_INTERWORK__"); 4120 4121 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4122 // Embedded targets on Darwin follow AAPCS, but not EABI. 4123 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4124 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4125 Builder.defineMacro("__ARM_EABI__"); 4126 Builder.defineMacro("__ARM_PCS", "1"); 4127 4128 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4129 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4130 } 4131 4132 if (SoftFloat) 4133 Builder.defineMacro("__SOFTFP__"); 4134 4135 if (CPU == "xscale") 4136 Builder.defineMacro("__XSCALE__"); 4137 4138 if (IsThumb) { 4139 Builder.defineMacro("__THUMBEL__"); 4140 Builder.defineMacro("__thumb__"); 4141 // We check both CPUArchVer and ArchName because when only triple is 4142 // specified, the default CPU is arm1136j-s. 4143 StringRef ArchName = getTriple().getArchName(); 4144 if (CPUArch == "6T2" || CPUArchVer >= 7 || ArchName.endswith("v6t2") || 4145 ArchName.endswith("v7") || ArchName.endswith("v8")) 4146 Builder.defineMacro("__thumb2__"); 4147 } 4148 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4149 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4150 4151 // Note, this is always on in gcc, even though it doesn't make sense. 4152 Builder.defineMacro("__APCS_32__"); 4153 4154 if (FPUModeIsVFP((FPUMode) FPU)) { 4155 Builder.defineMacro("__VFP_FP__"); 4156 if (FPU & VFP2FPU) 4157 Builder.defineMacro("__ARM_VFPV2__"); 4158 if (FPU & VFP3FPU) 4159 Builder.defineMacro("__ARM_VFPV3__"); 4160 if (FPU & VFP4FPU) 4161 Builder.defineMacro("__ARM_VFPV4__"); 4162 } 4163 4164 // This only gets set when Neon instructions are actually available, unlike 4165 // the VFP define, hence the soft float and arch check. This is subtly 4166 // different from gcc, we follow the intent which was that it should be set 4167 // when Neon instructions are actually available. 4168 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4169 Builder.defineMacro("__ARM_NEON"); 4170 Builder.defineMacro("__ARM_NEON__"); 4171 } 4172 4173 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4174 Opts.ShortWChar ? "2" : "4"); 4175 4176 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4177 Opts.ShortEnums ? "1" : "4"); 4178 4179 if (CRC) 4180 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4181 4182 if (Crypto) 4183 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4184 4185 if (CPUArchVer >= 6 && CPUArch != "6M") { 4186 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4187 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4188 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4189 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4190 } 4191 } 4192 void getTargetBuiltins(const Builtin::Info *&Records, 4193 unsigned &NumRecords) const override { 4194 Records = BuiltinInfo; 4195 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4196 } 4197 bool isCLZForZeroUndef() const override { return false; } 4198 BuiltinVaListKind getBuiltinVaListKind() const override { 4199 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4200 } 4201 void getGCCRegNames(const char * const *&Names, 4202 unsigned &NumNames) const override; 4203 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4204 unsigned &NumAliases) const override; 4205 bool validateAsmConstraint(const char *&Name, 4206 TargetInfo::ConstraintInfo &Info) const override { 4207 switch (*Name) { 4208 default: break; 4209 case 'l': // r0-r7 4210 case 'h': // r8-r15 4211 case 'w': // VFP Floating point register single precision 4212 case 'P': // VFP Floating point register double precision 4213 Info.setAllowsRegister(); 4214 return true; 4215 case 'Q': // A memory address that is a single base register. 4216 Info.setAllowsMemory(); 4217 return true; 4218 case 'U': // a memory reference... 4219 switch (Name[1]) { 4220 case 'q': // ...ARMV4 ldrsb 4221 case 'v': // ...VFP load/store (reg+constant offset) 4222 case 'y': // ...iWMMXt load/store 4223 case 't': // address valid for load/store opaque types wider 4224 // than 128-bits 4225 case 'n': // valid address for Neon doubleword vector load/store 4226 case 'm': // valid address for Neon element and structure load/store 4227 case 's': // valid address for non-offset loads/stores of quad-word 4228 // values in four ARM registers 4229 Info.setAllowsMemory(); 4230 Name++; 4231 return true; 4232 } 4233 } 4234 return false; 4235 } 4236 std::string convertConstraint(const char *&Constraint) const override { 4237 std::string R; 4238 switch (*Constraint) { 4239 case 'U': // Two-character constraint; add "^" hint for later parsing. 4240 R = std::string("^") + std::string(Constraint, 2); 4241 Constraint++; 4242 break; 4243 case 'p': // 'p' should be translated to 'r' by default. 4244 R = std::string("r"); 4245 break; 4246 default: 4247 return std::string(1, *Constraint); 4248 } 4249 return R; 4250 } 4251 bool validateConstraintModifier(StringRef Constraint, const char Modifier, 4252 unsigned Size) const override { 4253 bool isOutput = (Constraint[0] == '='); 4254 bool isInOut = (Constraint[0] == '+'); 4255 4256 // Strip off constraint modifiers. 4257 while (Constraint[0] == '=' || 4258 Constraint[0] == '+' || 4259 Constraint[0] == '&') 4260 Constraint = Constraint.substr(1); 4261 4262 switch (Constraint[0]) { 4263 default: break; 4264 case 'r': { 4265 switch (Modifier) { 4266 default: 4267 return (isInOut || isOutput || Size <= 64); 4268 case 'q': 4269 // A register of size 32 cannot fit a vector type. 4270 return false; 4271 } 4272 } 4273 } 4274 4275 return true; 4276 } 4277 const char *getClobbers() const override { 4278 // FIXME: Is this really right? 4279 return ""; 4280 } 4281 4282 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4283 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4284 } 4285 4286 int getEHDataRegisterNumber(unsigned RegNo) const override { 4287 if (RegNo == 0) return 0; 4288 if (RegNo == 1) return 1; 4289 return -1; 4290 } 4291 }; 4292 4293 bool ARMTargetInfo::setFPMath(StringRef Name) { 4294 if (Name == "neon") { 4295 FPMath = FP_Neon; 4296 return true; 4297 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4298 Name == "vfp4") { 4299 FPMath = FP_VFP; 4300 return true; 4301 } 4302 return false; 4303 } 4304 4305 const char * const ARMTargetInfo::GCCRegNames[] = { 4306 // Integer registers 4307 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4308 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4309 4310 // Float registers 4311 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4312 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4313 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4314 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4315 4316 // Double registers 4317 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4318 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4319 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4320 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4321 4322 // Quad registers 4323 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4324 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4325 }; 4326 4327 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4328 unsigned &NumNames) const { 4329 Names = GCCRegNames; 4330 NumNames = llvm::array_lengthof(GCCRegNames); 4331 } 4332 4333 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4334 { { "a1" }, "r0" }, 4335 { { "a2" }, "r1" }, 4336 { { "a3" }, "r2" }, 4337 { { "a4" }, "r3" }, 4338 { { "v1" }, "r4" }, 4339 { { "v2" }, "r5" }, 4340 { { "v3" }, "r6" }, 4341 { { "v4" }, "r7" }, 4342 { { "v5" }, "r8" }, 4343 { { "v6", "rfp" }, "r9" }, 4344 { { "sl" }, "r10" }, 4345 { { "fp" }, "r11" }, 4346 { { "ip" }, "r12" }, 4347 { { "r13" }, "sp" }, 4348 { { "r14" }, "lr" }, 4349 { { "r15" }, "pc" }, 4350 // The S, D and Q registers overlap, but aren't really aliases; we 4351 // don't want to substitute one of these for a different-sized one. 4352 }; 4353 4354 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4355 unsigned &NumAliases) const { 4356 Aliases = GCCRegAliases; 4357 NumAliases = llvm::array_lengthof(GCCRegAliases); 4358 } 4359 4360 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4361 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4362 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4363 ALL_LANGUAGES }, 4364 #include "clang/Basic/BuiltinsNEON.def" 4365 4366 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4367 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4368 ALL_LANGUAGES }, 4369 #include "clang/Basic/BuiltinsARM.def" 4370 }; 4371 4372 class ARMleTargetInfo : public ARMTargetInfo { 4373 public: 4374 ARMleTargetInfo(const llvm::Triple &Triple) 4375 : ARMTargetInfo(Triple, false) { } 4376 virtual void getTargetDefines(const LangOptions &Opts, 4377 MacroBuilder &Builder) const { 4378 Builder.defineMacro("__ARMEL__"); 4379 ARMTargetInfo::getTargetDefines(Opts, Builder); 4380 } 4381 }; 4382 4383 class ARMbeTargetInfo : public ARMTargetInfo { 4384 public: 4385 ARMbeTargetInfo(const llvm::Triple &Triple) 4386 : ARMTargetInfo(Triple, true) { } 4387 virtual void getTargetDefines(const LangOptions &Opts, 4388 MacroBuilder &Builder) const { 4389 Builder.defineMacro("__ARMEB__"); 4390 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4391 ARMTargetInfo::getTargetDefines(Opts, Builder); 4392 } 4393 }; 4394 } // end anonymous namespace. 4395 4396 namespace { 4397 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4398 const llvm::Triple Triple; 4399 public: 4400 WindowsARMTargetInfo(const llvm::Triple &Triple) 4401 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4402 TLSSupported = false; 4403 WCharType = UnsignedShort; 4404 SizeType = UnsignedInt; 4405 UserLabelPrefix = ""; 4406 } 4407 void getVisualStudioDefines(const LangOptions &Opts, 4408 MacroBuilder &Builder) const { 4409 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4410 4411 // FIXME: this is invalid for WindowsCE 4412 Builder.defineMacro("_M_ARM_NT", "1"); 4413 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4414 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4415 4416 assert((Triple.getArch() == llvm::Triple::arm || 4417 Triple.getArch() == llvm::Triple::thumb) && 4418 "invalid architecture for Windows ARM target info"); 4419 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4420 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4421 4422 // TODO map the complete set of values 4423 // 31: VFPv3 40: VFPv4 4424 Builder.defineMacro("_M_ARM_FP", "31"); 4425 } 4426 }; 4427 4428 // Windows ARM + Itanium C++ ABI Target 4429 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4430 public: 4431 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4432 : WindowsARMTargetInfo(Triple) { 4433 TheCXXABI.set(TargetCXXABI::GenericARM); 4434 } 4435 4436 void getTargetDefines(const LangOptions &Opts, 4437 MacroBuilder &Builder) const override { 4438 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4439 4440 if (Opts.MSVCCompat) 4441 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4442 } 4443 }; 4444 4445 // Windows ARM, MS (C++) ABI 4446 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4447 public: 4448 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4449 : WindowsARMTargetInfo(Triple) { 4450 TheCXXABI.set(TargetCXXABI::Microsoft); 4451 } 4452 4453 void getTargetDefines(const LangOptions &Opts, 4454 MacroBuilder &Builder) const override { 4455 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4456 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4457 } 4458 }; 4459 } 4460 4461 4462 namespace { 4463 class DarwinARMTargetInfo : 4464 public DarwinTargetInfo<ARMleTargetInfo> { 4465 protected: 4466 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4467 MacroBuilder &Builder) const override { 4468 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4469 } 4470 4471 public: 4472 DarwinARMTargetInfo(const llvm::Triple &Triple) 4473 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4474 HasAlignMac68kSupport = true; 4475 // iOS always has 64-bit atomic instructions. 4476 // FIXME: This should be based off of the target features in ARMleTargetInfo. 4477 MaxAtomicInlineWidth = 64; 4478 4479 // Darwin on iOS uses a variant of the ARM C++ ABI. 4480 TheCXXABI.set(TargetCXXABI::iOS); 4481 } 4482 }; 4483 } // end anonymous namespace. 4484 4485 4486 namespace { 4487 class ARM64TargetInfo : public TargetInfo { 4488 virtual void setDescriptionString() = 0; 4489 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4490 static const char *const GCCRegNames[]; 4491 4492 enum FPUModeEnum { 4493 FPUMode, 4494 NeonMode 4495 }; 4496 4497 unsigned FPU; 4498 unsigned Crypto; 4499 4500 static const Builtin::Info BuiltinInfo[]; 4501 4502 std::string ABI; 4503 4504 public: 4505 ARM64TargetInfo(const llvm::Triple &Triple) 4506 : TargetInfo(Triple), ABI("aapcs") { 4507 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4508 IntMaxType = SignedLong; 4509 UIntMaxType = UnsignedLong; 4510 Int64Type = SignedLong; 4511 WCharType = UnsignedInt; 4512 MaxVectorAlign = 128; 4513 RegParmMax = 8; 4514 MaxAtomicInlineWidth = 128; 4515 MaxAtomicPromoteWidth = 128; 4516 4517 LongDoubleWidth = LongDoubleAlign = 128; 4518 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4519 4520 // {} in inline assembly are neon specifiers, not assembly variant 4521 // specifiers. 4522 NoAsmVariants = true; 4523 4524 // ARM64 targets default to using the ARM C++ ABI. 4525 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4526 } 4527 4528 virtual const char *getABI() const { return ABI.c_str(); } 4529 virtual bool setABI(const std::string &Name) { 4530 if (Name != "aapcs" && Name != "darwinpcs") 4531 return false; 4532 4533 ABI = Name; 4534 return true; 4535 } 4536 4537 virtual bool setCPU(const std::string &Name) { 4538 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4539 .Case("generic", true) 4540 .Cases("cortex-a53", "cortex-a57", true) 4541 .Case("cyclone", true) 4542 .Default(false); 4543 return CPUKnown; 4544 } 4545 4546 virtual void getTargetDefines(const LangOptions &Opts, 4547 MacroBuilder &Builder) const { 4548 // Target identification. 4549 Builder.defineMacro("__aarch64__"); 4550 4551 // Target properties. 4552 Builder.defineMacro("_LP64"); 4553 Builder.defineMacro("__LP64__"); 4554 4555 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4556 Builder.defineMacro("__ARM_ACLE", "200"); 4557 Builder.defineMacro("__ARM_ARCH", "8"); 4558 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4559 4560 Builder.defineMacro("__ARM_64BIT_STATE"); 4561 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4562 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4563 4564 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4565 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4566 Builder.defineMacro("__ARM_FEATURE_FMA"); 4567 Builder.defineMacro("__ARM_FEATURE_DIV"); 4568 4569 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4570 4571 // 0xe implies support for half, single and double precision operations. 4572 Builder.defineMacro("__ARM_FP", "0xe"); 4573 4574 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4575 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4576 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4577 4578 if (Opts.FastMath || Opts.FiniteMathOnly) 4579 Builder.defineMacro("__ARM_FP_FAST"); 4580 4581 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 4582 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4583 4584 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4585 4586 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4587 Opts.ShortEnums ? "1" : "4"); 4588 4589 if (FPU == NeonMode) { 4590 Builder.defineMacro("__ARM_NEON"); 4591 // 64-bit NEON supports half, single and double precision operations. 4592 Builder.defineMacro("__ARM_NEON_FP", "7"); 4593 } 4594 4595 if (Crypto) 4596 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4597 } 4598 4599 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4600 unsigned &NumRecords) const { 4601 Records = BuiltinInfo; 4602 NumRecords = clang::ARM64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4603 } 4604 4605 virtual bool hasFeature(StringRef Feature) const { 4606 return Feature == "aarch64" || 4607 Feature == "arm64" || 4608 (Feature == "neon" && FPU == NeonMode); 4609 } 4610 4611 bool handleTargetFeatures(std::vector<std::string> &Features, 4612 DiagnosticsEngine &Diags) override { 4613 FPU = FPUMode; 4614 Crypto = 0; 4615 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4616 if (Features[i] == "+neon") 4617 FPU = NeonMode; 4618 if (Features[i] == "+crypto") 4619 Crypto = 1; 4620 } 4621 4622 setDescriptionString(); 4623 4624 return true; 4625 } 4626 4627 virtual bool isCLZForZeroUndef() const { return false; } 4628 4629 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4630 return TargetInfo::AArch64ABIBuiltinVaList; 4631 } 4632 4633 virtual void getGCCRegNames(const char *const *&Names, 4634 unsigned &NumNames) const; 4635 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4636 unsigned &NumAliases) const; 4637 4638 virtual bool validateAsmConstraint(const char *&Name, 4639 TargetInfo::ConstraintInfo &Info) const { 4640 switch (*Name) { 4641 default: 4642 return false; 4643 case 'w': // Floating point and SIMD registers (V0-V31) 4644 Info.setAllowsRegister(); 4645 return true; 4646 case 'I': // Constant that can be used with an ADD instruction 4647 case 'J': // Constant that can be used with a SUB instruction 4648 case 'K': // Constant that can be used with a 32-bit logical instruction 4649 case 'L': // Constant that can be used with a 64-bit logical instruction 4650 case 'M': // Constant that can be used as a 32-bit MOV immediate 4651 case 'N': // Constant that can be used as a 64-bit MOV immediate 4652 case 'Y': // Floating point constant zero 4653 case 'Z': // Integer constant zero 4654 return true; 4655 case 'Q': // A memory reference with base register and no offset 4656 Info.setAllowsMemory(); 4657 return true; 4658 case 'S': // A symbolic address 4659 Info.setAllowsRegister(); 4660 return true; 4661 case 'U': 4662 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 4663 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 4664 // Usa: An absolute symbolic address 4665 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 4666 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 4667 case 'z': // Zero register, wzr or xzr 4668 Info.setAllowsRegister(); 4669 return true; 4670 case 'x': // Floating point and SIMD registers (V0-V15) 4671 Info.setAllowsRegister(); 4672 return true; 4673 } 4674 return false; 4675 } 4676 4677 virtual const char *getClobbers() const { return ""; } 4678 4679 int getEHDataRegisterNumber(unsigned RegNo) const { 4680 if (RegNo == 0) 4681 return 0; 4682 if (RegNo == 1) 4683 return 1; 4684 return -1; 4685 } 4686 }; 4687 4688 const char *const ARM64TargetInfo::GCCRegNames[] = { 4689 // 32-bit Integer registers 4690 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 4691 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 4692 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 4693 4694 // 64-bit Integer registers 4695 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 4696 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 4697 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 4698 4699 // 32-bit floating point regsisters 4700 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 4701 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 4702 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4703 4704 // 64-bit floating point regsisters 4705 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 4706 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 4707 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4708 4709 // Vector registers 4710 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 4711 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 4712 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 4713 }; 4714 4715 void ARM64TargetInfo::getGCCRegNames(const char *const *&Names, 4716 unsigned &NumNames) const { 4717 Names = GCCRegNames; 4718 NumNames = llvm::array_lengthof(GCCRegNames); 4719 } 4720 4721 const TargetInfo::GCCRegAlias ARM64TargetInfo::GCCRegAliases[] = { 4722 { { "w31" }, "wsp" }, 4723 { { "x29" }, "fp" }, 4724 { { "x30" }, "lr" }, 4725 { { "x31" }, "sp" }, 4726 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 4727 // don't want to substitute one of these for a different-sized one. 4728 }; 4729 4730 void ARM64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4731 unsigned &NumAliases) const { 4732 Aliases = GCCRegAliases; 4733 NumAliases = llvm::array_lengthof(GCCRegAliases); 4734 } 4735 4736 const Builtin::Info ARM64TargetInfo::BuiltinInfo[] = { 4737 #define BUILTIN(ID, TYPE, ATTRS) \ 4738 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4739 #include "clang/Basic/BuiltinsNEON.def" 4740 4741 #define BUILTIN(ID, TYPE, ATTRS) \ 4742 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4743 #include "clang/Basic/BuiltinsARM64.def" 4744 }; 4745 4746 class ARM64leTargetInfo : public ARM64TargetInfo { 4747 void setDescriptionString() override { 4748 if (getTriple().isOSBinFormatMachO()) 4749 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 4750 else 4751 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 4752 } 4753 4754 public: 4755 ARM64leTargetInfo(const llvm::Triple &Triple) 4756 : ARM64TargetInfo(Triple) { 4757 BigEndian = false; 4758 } 4759 void getTargetDefines(const LangOptions &Opts, 4760 MacroBuilder &Builder) const override { 4761 Builder.defineMacro("__AARCH64EL__"); 4762 ARM64TargetInfo::getTargetDefines(Opts, Builder); 4763 } 4764 }; 4765 4766 class ARM64beTargetInfo : public ARM64TargetInfo { 4767 void setDescriptionString() override { 4768 assert(!getTriple().isOSBinFormatMachO()); 4769 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 4770 } 4771 4772 public: 4773 ARM64beTargetInfo(const llvm::Triple &Triple) 4774 : ARM64TargetInfo(Triple) { } 4775 void getTargetDefines(const LangOptions &Opts, 4776 MacroBuilder &Builder) const override { 4777 Builder.defineMacro("__AARCH64EB__"); 4778 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 4779 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4780 ARM64TargetInfo::getTargetDefines(Opts, Builder); 4781 } 4782 }; 4783 } // end anonymous namespace. 4784 4785 namespace { 4786 class DarwinARM64TargetInfo : public DarwinTargetInfo<ARM64leTargetInfo> { 4787 protected: 4788 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4789 MacroBuilder &Builder) const override { 4790 Builder.defineMacro("__AARCH64_SIMD__"); 4791 Builder.defineMacro("__ARM64_ARCH_8__"); 4792 Builder.defineMacro("__ARM_NEON__"); 4793 Builder.defineMacro("__LITTLE_ENDIAN__"); 4794 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4795 Builder.defineMacro("__arm64", "1"); 4796 Builder.defineMacro("__arm64__", "1"); 4797 4798 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4799 } 4800 4801 public: 4802 DarwinARM64TargetInfo(const llvm::Triple &Triple) 4803 : DarwinTargetInfo<ARM64leTargetInfo>(Triple) { 4804 Int64Type = SignedLongLong; 4805 WCharType = SignedInt; 4806 UseSignedCharForObjCBool = false; 4807 4808 LongDoubleWidth = LongDoubleAlign = 64; 4809 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4810 4811 TheCXXABI.set(TargetCXXABI::iOS64); 4812 } 4813 4814 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4815 return TargetInfo::CharPtrBuiltinVaList; 4816 } 4817 }; 4818 } // end anonymous namespace 4819 4820 namespace { 4821 // Hexagon abstract base class 4822 class HexagonTargetInfo : public TargetInfo { 4823 static const Builtin::Info BuiltinInfo[]; 4824 static const char * const GCCRegNames[]; 4825 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4826 std::string CPU; 4827 public: 4828 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4829 BigEndian = false; 4830 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 4831 4832 // {} in inline assembly are packet specifiers, not assembly variant 4833 // specifiers. 4834 NoAsmVariants = true; 4835 } 4836 4837 void getTargetBuiltins(const Builtin::Info *&Records, 4838 unsigned &NumRecords) const override { 4839 Records = BuiltinInfo; 4840 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4841 } 4842 4843 bool validateAsmConstraint(const char *&Name, 4844 TargetInfo::ConstraintInfo &Info) const override { 4845 return true; 4846 } 4847 4848 void getTargetDefines(const LangOptions &Opts, 4849 MacroBuilder &Builder) const override; 4850 4851 bool hasFeature(StringRef Feature) const override { 4852 return Feature == "hexagon"; 4853 } 4854 4855 BuiltinVaListKind getBuiltinVaListKind() const override { 4856 return TargetInfo::CharPtrBuiltinVaList; 4857 } 4858 void getGCCRegNames(const char * const *&Names, 4859 unsigned &NumNames) const override; 4860 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4861 unsigned &NumAliases) const override; 4862 const char *getClobbers() const override { 4863 return ""; 4864 } 4865 4866 static const char *getHexagonCPUSuffix(StringRef Name) { 4867 return llvm::StringSwitch<const char*>(Name) 4868 .Case("hexagonv4", "4") 4869 .Case("hexagonv5", "5") 4870 .Default(0); 4871 } 4872 4873 bool setCPU(const std::string &Name) override { 4874 if (!getHexagonCPUSuffix(Name)) 4875 return false; 4876 4877 CPU = Name; 4878 return true; 4879 } 4880 }; 4881 4882 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4883 MacroBuilder &Builder) const { 4884 Builder.defineMacro("qdsp6"); 4885 Builder.defineMacro("__qdsp6", "1"); 4886 Builder.defineMacro("__qdsp6__", "1"); 4887 4888 Builder.defineMacro("hexagon"); 4889 Builder.defineMacro("__hexagon", "1"); 4890 Builder.defineMacro("__hexagon__", "1"); 4891 4892 if(CPU == "hexagonv1") { 4893 Builder.defineMacro("__HEXAGON_V1__"); 4894 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4895 if(Opts.HexagonQdsp6Compat) { 4896 Builder.defineMacro("__QDSP6_V1__"); 4897 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4898 } 4899 } 4900 else if(CPU == "hexagonv2") { 4901 Builder.defineMacro("__HEXAGON_V2__"); 4902 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4903 if(Opts.HexagonQdsp6Compat) { 4904 Builder.defineMacro("__QDSP6_V2__"); 4905 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4906 } 4907 } 4908 else if(CPU == "hexagonv3") { 4909 Builder.defineMacro("__HEXAGON_V3__"); 4910 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4911 if(Opts.HexagonQdsp6Compat) { 4912 Builder.defineMacro("__QDSP6_V3__"); 4913 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4914 } 4915 } 4916 else if(CPU == "hexagonv4") { 4917 Builder.defineMacro("__HEXAGON_V4__"); 4918 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4919 if(Opts.HexagonQdsp6Compat) { 4920 Builder.defineMacro("__QDSP6_V4__"); 4921 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4922 } 4923 } 4924 else if(CPU == "hexagonv5") { 4925 Builder.defineMacro("__HEXAGON_V5__"); 4926 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4927 if(Opts.HexagonQdsp6Compat) { 4928 Builder.defineMacro("__QDSP6_V5__"); 4929 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4930 } 4931 } 4932 } 4933 4934 const char * const HexagonTargetInfo::GCCRegNames[] = { 4935 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4936 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4937 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4938 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4939 "p0", "p1", "p2", "p3", 4940 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4941 }; 4942 4943 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4944 unsigned &NumNames) const { 4945 Names = GCCRegNames; 4946 NumNames = llvm::array_lengthof(GCCRegNames); 4947 } 4948 4949 4950 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4951 { { "sp" }, "r29" }, 4952 { { "fp" }, "r30" }, 4953 { { "lr" }, "r31" }, 4954 }; 4955 4956 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4957 unsigned &NumAliases) const { 4958 Aliases = GCCRegAliases; 4959 NumAliases = llvm::array_lengthof(GCCRegAliases); 4960 } 4961 4962 4963 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4964 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4965 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4966 ALL_LANGUAGES }, 4967 #include "clang/Basic/BuiltinsHexagon.def" 4968 }; 4969 } 4970 4971 4972 namespace { 4973 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4974 class SparcTargetInfo : public TargetInfo { 4975 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4976 static const char * const GCCRegNames[]; 4977 bool SoftFloat; 4978 public: 4979 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4980 4981 bool handleTargetFeatures(std::vector<std::string> &Features, 4982 DiagnosticsEngine &Diags) override { 4983 SoftFloat = false; 4984 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4985 if (Features[i] == "+soft-float") 4986 SoftFloat = true; 4987 return true; 4988 } 4989 void getTargetDefines(const LangOptions &Opts, 4990 MacroBuilder &Builder) const override { 4991 DefineStd(Builder, "sparc", Opts); 4992 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4993 4994 if (SoftFloat) 4995 Builder.defineMacro("SOFT_FLOAT", "1"); 4996 } 4997 4998 bool hasFeature(StringRef Feature) const override { 4999 return llvm::StringSwitch<bool>(Feature) 5000 .Case("softfloat", SoftFloat) 5001 .Case("sparc", true) 5002 .Default(false); 5003 } 5004 5005 void getTargetBuiltins(const Builtin::Info *&Records, 5006 unsigned &NumRecords) const override { 5007 // FIXME: Implement! 5008 } 5009 BuiltinVaListKind getBuiltinVaListKind() const override { 5010 return TargetInfo::VoidPtrBuiltinVaList; 5011 } 5012 void getGCCRegNames(const char * const *&Names, 5013 unsigned &NumNames) const override; 5014 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5015 unsigned &NumAliases) const override; 5016 bool validateAsmConstraint(const char *&Name, 5017 TargetInfo::ConstraintInfo &info) const override { 5018 // FIXME: Implement! 5019 return false; 5020 } 5021 const char *getClobbers() const override { 5022 // FIXME: Implement! 5023 return ""; 5024 } 5025 }; 5026 5027 const char * const SparcTargetInfo::GCCRegNames[] = { 5028 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5029 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5030 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5031 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5032 }; 5033 5034 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5035 unsigned &NumNames) const { 5036 Names = GCCRegNames; 5037 NumNames = llvm::array_lengthof(GCCRegNames); 5038 } 5039 5040 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5041 { { "g0" }, "r0" }, 5042 { { "g1" }, "r1" }, 5043 { { "g2" }, "r2" }, 5044 { { "g3" }, "r3" }, 5045 { { "g4" }, "r4" }, 5046 { { "g5" }, "r5" }, 5047 { { "g6" }, "r6" }, 5048 { { "g7" }, "r7" }, 5049 { { "o0" }, "r8" }, 5050 { { "o1" }, "r9" }, 5051 { { "o2" }, "r10" }, 5052 { { "o3" }, "r11" }, 5053 { { "o4" }, "r12" }, 5054 { { "o5" }, "r13" }, 5055 { { "o6", "sp" }, "r14" }, 5056 { { "o7" }, "r15" }, 5057 { { "l0" }, "r16" }, 5058 { { "l1" }, "r17" }, 5059 { { "l2" }, "r18" }, 5060 { { "l3" }, "r19" }, 5061 { { "l4" }, "r20" }, 5062 { { "l5" }, "r21" }, 5063 { { "l6" }, "r22" }, 5064 { { "l7" }, "r23" }, 5065 { { "i0" }, "r24" }, 5066 { { "i1" }, "r25" }, 5067 { { "i2" }, "r26" }, 5068 { { "i3" }, "r27" }, 5069 { { "i4" }, "r28" }, 5070 { { "i5" }, "r29" }, 5071 { { "i6", "fp" }, "r30" }, 5072 { { "i7" }, "r31" }, 5073 }; 5074 5075 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5076 unsigned &NumAliases) const { 5077 Aliases = GCCRegAliases; 5078 NumAliases = llvm::array_lengthof(GCCRegAliases); 5079 } 5080 5081 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5082 class SparcV8TargetInfo : public SparcTargetInfo { 5083 public: 5084 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5085 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5086 } 5087 5088 void getTargetDefines(const LangOptions &Opts, 5089 MacroBuilder &Builder) const override { 5090 SparcTargetInfo::getTargetDefines(Opts, Builder); 5091 Builder.defineMacro("__sparcv8"); 5092 } 5093 }; 5094 5095 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5096 class SparcV9TargetInfo : public SparcTargetInfo { 5097 public: 5098 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5099 // FIXME: Support Sparc quad-precision long double? 5100 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5101 // This is an LP64 platform. 5102 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5103 5104 // OpenBSD uses long long for int64_t and intmax_t. 5105 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 5106 IntMaxType = SignedLongLong; 5107 UIntMaxType = UnsignedLongLong; 5108 } else { 5109 IntMaxType = SignedLong; 5110 UIntMaxType = UnsignedLong; 5111 } 5112 Int64Type = IntMaxType; 5113 5114 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5115 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5116 LongDoubleWidth = 128; 5117 LongDoubleAlign = 128; 5118 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5119 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5120 } 5121 5122 void getTargetDefines(const LangOptions &Opts, 5123 MacroBuilder &Builder) const override { 5124 SparcTargetInfo::getTargetDefines(Opts, Builder); 5125 Builder.defineMacro("__sparcv9"); 5126 Builder.defineMacro("__arch64__"); 5127 // Solaris and its derivative AuroraUX don't need these variants, but the 5128 // BSDs do. 5129 if (getTriple().getOS() != llvm::Triple::Solaris && 5130 getTriple().getOS() != llvm::Triple::AuroraUX) { 5131 Builder.defineMacro("__sparc64__"); 5132 Builder.defineMacro("__sparc_v9__"); 5133 Builder.defineMacro("__sparcv9__"); 5134 } 5135 } 5136 5137 bool setCPU(const std::string &Name) override { 5138 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5139 .Case("v9", true) 5140 .Case("ultrasparc", true) 5141 .Case("ultrasparc3", true) 5142 .Case("niagara", true) 5143 .Case("niagara2", true) 5144 .Case("niagara3", true) 5145 .Case("niagara4", true) 5146 .Default(false); 5147 5148 // No need to store the CPU yet. There aren't any CPU-specific 5149 // macros to define. 5150 return CPUKnown; 5151 } 5152 }; 5153 5154 } // end anonymous namespace. 5155 5156 namespace { 5157 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 5158 public: 5159 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 5160 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 5161 SizeType = UnsignedInt; 5162 PtrDiffType = SignedInt; 5163 } 5164 }; 5165 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5166 public: 5167 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5168 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5169 SizeType = UnsignedInt; 5170 PtrDiffType = SignedInt; 5171 } 5172 }; 5173 } // end anonymous namespace. 5174 5175 namespace { 5176 class SystemZTargetInfo : public TargetInfo { 5177 static const char *const GCCRegNames[]; 5178 5179 public: 5180 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5181 TLSSupported = true; 5182 IntWidth = IntAlign = 32; 5183 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5184 PointerWidth = PointerAlign = 64; 5185 LongDoubleWidth = 128; 5186 LongDoubleAlign = 64; 5187 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5188 MinGlobalAlign = 16; 5189 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5190 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5191 } 5192 void getTargetDefines(const LangOptions &Opts, 5193 MacroBuilder &Builder) const override { 5194 Builder.defineMacro("__s390__"); 5195 Builder.defineMacro("__s390x__"); 5196 Builder.defineMacro("__zarch__"); 5197 Builder.defineMacro("__LONG_DOUBLE_128__"); 5198 } 5199 void getTargetBuiltins(const Builtin::Info *&Records, 5200 unsigned &NumRecords) const override { 5201 // FIXME: Implement. 5202 Records = 0; 5203 NumRecords = 0; 5204 } 5205 5206 void getGCCRegNames(const char *const *&Names, 5207 unsigned &NumNames) const override; 5208 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5209 unsigned &NumAliases) const override { 5210 // No aliases. 5211 Aliases = 0; 5212 NumAliases = 0; 5213 } 5214 bool validateAsmConstraint(const char *&Name, 5215 TargetInfo::ConstraintInfo &info) const override; 5216 const char *getClobbers() const override { 5217 // FIXME: Is this really right? 5218 return ""; 5219 } 5220 BuiltinVaListKind getBuiltinVaListKind() const override { 5221 return TargetInfo::SystemZBuiltinVaList; 5222 } 5223 bool setCPU(const std::string &Name) override { 5224 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5225 .Case("z10", true) 5226 .Case("z196", true) 5227 .Case("zEC12", true) 5228 .Default(false); 5229 5230 // No need to store the CPU yet. There aren't any CPU-specific 5231 // macros to define. 5232 return CPUKnown; 5233 } 5234 }; 5235 5236 const char *const SystemZTargetInfo::GCCRegNames[] = { 5237 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5238 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5239 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5240 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5241 }; 5242 5243 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5244 unsigned &NumNames) const { 5245 Names = GCCRegNames; 5246 NumNames = llvm::array_lengthof(GCCRegNames); 5247 } 5248 5249 bool SystemZTargetInfo:: 5250 validateAsmConstraint(const char *&Name, 5251 TargetInfo::ConstraintInfo &Info) const { 5252 switch (*Name) { 5253 default: 5254 return false; 5255 5256 case 'a': // Address register 5257 case 'd': // Data register (equivalent to 'r') 5258 case 'f': // Floating-point register 5259 Info.setAllowsRegister(); 5260 return true; 5261 5262 case 'I': // Unsigned 8-bit constant 5263 case 'J': // Unsigned 12-bit constant 5264 case 'K': // Signed 16-bit constant 5265 case 'L': // Signed 20-bit displacement (on all targets we support) 5266 case 'M': // 0x7fffffff 5267 return true; 5268 5269 case 'Q': // Memory with base and unsigned 12-bit displacement 5270 case 'R': // Likewise, plus an index 5271 case 'S': // Memory with base and signed 20-bit displacement 5272 case 'T': // Likewise, plus an index 5273 Info.setAllowsMemory(); 5274 return true; 5275 } 5276 } 5277 } 5278 5279 namespace { 5280 class MSP430TargetInfo : public TargetInfo { 5281 static const char * const GCCRegNames[]; 5282 public: 5283 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5284 BigEndian = false; 5285 TLSSupported = false; 5286 IntWidth = 16; IntAlign = 16; 5287 LongWidth = 32; LongLongWidth = 64; 5288 LongAlign = LongLongAlign = 16; 5289 PointerWidth = 16; PointerAlign = 16; 5290 SuitableAlign = 16; 5291 SizeType = UnsignedInt; 5292 IntMaxType = SignedLongLong; 5293 UIntMaxType = UnsignedLongLong; 5294 IntPtrType = SignedInt; 5295 PtrDiffType = SignedInt; 5296 SigAtomicType = SignedLong; 5297 DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16"; 5298 } 5299 void getTargetDefines(const LangOptions &Opts, 5300 MacroBuilder &Builder) const override { 5301 Builder.defineMacro("MSP430"); 5302 Builder.defineMacro("__MSP430__"); 5303 // FIXME: defines for different 'flavours' of MCU 5304 } 5305 void getTargetBuiltins(const Builtin::Info *&Records, 5306 unsigned &NumRecords) const override { 5307 // FIXME: Implement. 5308 Records = 0; 5309 NumRecords = 0; 5310 } 5311 bool hasFeature(StringRef Feature) const override { 5312 return Feature == "msp430"; 5313 } 5314 void getGCCRegNames(const char * const *&Names, 5315 unsigned &NumNames) const override; 5316 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5317 unsigned &NumAliases) const override { 5318 // No aliases. 5319 Aliases = 0; 5320 NumAliases = 0; 5321 } 5322 bool validateAsmConstraint(const char *&Name, 5323 TargetInfo::ConstraintInfo &info) const override { 5324 // No target constraints for now. 5325 return false; 5326 } 5327 const char *getClobbers() const override { 5328 // FIXME: Is this really right? 5329 return ""; 5330 } 5331 BuiltinVaListKind getBuiltinVaListKind() const override { 5332 // FIXME: implement 5333 return TargetInfo::CharPtrBuiltinVaList; 5334 } 5335 }; 5336 5337 const char * const MSP430TargetInfo::GCCRegNames[] = { 5338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5340 }; 5341 5342 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5343 unsigned &NumNames) const { 5344 Names = GCCRegNames; 5345 NumNames = llvm::array_lengthof(GCCRegNames); 5346 } 5347 } 5348 5349 namespace { 5350 5351 // LLVM and Clang cannot be used directly to output native binaries for 5352 // target, but is used to compile C code to llvm bitcode with correct 5353 // type and alignment information. 5354 // 5355 // TCE uses the llvm bitcode as input and uses it for generating customized 5356 // target processor and program binary. TCE co-design environment is 5357 // publicly available in http://tce.cs.tut.fi 5358 5359 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5360 3, // opencl_global 5361 4, // opencl_local 5362 5, // opencl_constant 5363 0, // cuda_device 5364 0, // cuda_constant 5365 0 // cuda_shared 5366 }; 5367 5368 class TCETargetInfo : public TargetInfo{ 5369 public: 5370 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5371 TLSSupported = false; 5372 IntWidth = 32; 5373 LongWidth = LongLongWidth = 32; 5374 PointerWidth = 32; 5375 IntAlign = 32; 5376 LongAlign = LongLongAlign = 32; 5377 PointerAlign = 32; 5378 SuitableAlign = 32; 5379 SizeType = UnsignedInt; 5380 IntMaxType = SignedLong; 5381 UIntMaxType = UnsignedLong; 5382 IntPtrType = SignedInt; 5383 PtrDiffType = SignedInt; 5384 FloatWidth = 32; 5385 FloatAlign = 32; 5386 DoubleWidth = 32; 5387 DoubleAlign = 32; 5388 LongDoubleWidth = 32; 5389 LongDoubleAlign = 32; 5390 FloatFormat = &llvm::APFloat::IEEEsingle; 5391 DoubleFormat = &llvm::APFloat::IEEEsingle; 5392 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5393 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5394 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5395 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5396 UseAddrSpaceMapMangling = true; 5397 } 5398 5399 void getTargetDefines(const LangOptions &Opts, 5400 MacroBuilder &Builder) const override { 5401 DefineStd(Builder, "tce", Opts); 5402 Builder.defineMacro("__TCE__"); 5403 Builder.defineMacro("__TCE_V1__"); 5404 } 5405 bool hasFeature(StringRef Feature) const override { 5406 return Feature == "tce"; 5407 } 5408 5409 void getTargetBuiltins(const Builtin::Info *&Records, 5410 unsigned &NumRecords) const override {} 5411 const char *getClobbers() const override { 5412 return ""; 5413 } 5414 BuiltinVaListKind getBuiltinVaListKind() const override { 5415 return TargetInfo::VoidPtrBuiltinVaList; 5416 } 5417 void getGCCRegNames(const char * const *&Names, 5418 unsigned &NumNames) const override {} 5419 bool validateAsmConstraint(const char *&Name, 5420 TargetInfo::ConstraintInfo &info) const override{ 5421 return true; 5422 } 5423 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5424 unsigned &NumAliases) const override {} 5425 }; 5426 } 5427 5428 namespace { 5429 class MipsTargetInfoBase : public TargetInfo { 5430 virtual void setDescriptionString() = 0; 5431 5432 static const Builtin::Info BuiltinInfo[]; 5433 std::string CPU; 5434 bool IsMips16; 5435 bool IsMicromips; 5436 bool IsNan2008; 5437 bool IsSingleFloat; 5438 enum MipsFloatABI { 5439 HardFloat, SoftFloat 5440 } FloatABI; 5441 enum DspRevEnum { 5442 NoDSP, DSP1, DSP2 5443 } DspRev; 5444 bool HasMSA; 5445 5446 protected: 5447 bool HasFP64; 5448 std::string ABI; 5449 5450 public: 5451 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5452 const std::string &CPUStr) 5453 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5454 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5455 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 5456 5457 const char *getABI() const override { return ABI.c_str(); } 5458 bool setABI(const std::string &Name) override = 0; 5459 bool setCPU(const std::string &Name) override { 5460 CPU = Name; 5461 return true; 5462 } 5463 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5464 // The backend enables certain ABI's by default according to the 5465 // architecture. 5466 // Disable both possible defaults so that we don't end up with multiple 5467 // ABI's selected and trigger an assertion. 5468 Features["o32"] = false; 5469 Features["n64"] = false; 5470 5471 Features[ABI] = true; 5472 Features[CPU] = true; 5473 } 5474 5475 void getTargetDefines(const LangOptions &Opts, 5476 MacroBuilder &Builder) const override { 5477 Builder.defineMacro("__mips__"); 5478 Builder.defineMacro("_mips"); 5479 if (Opts.GNUMode) 5480 Builder.defineMacro("mips"); 5481 5482 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5483 5484 switch (FloatABI) { 5485 case HardFloat: 5486 Builder.defineMacro("__mips_hard_float", Twine(1)); 5487 break; 5488 case SoftFloat: 5489 Builder.defineMacro("__mips_soft_float", Twine(1)); 5490 break; 5491 } 5492 5493 if (IsSingleFloat) 5494 Builder.defineMacro("__mips_single_float", Twine(1)); 5495 5496 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5497 Builder.defineMacro("_MIPS_FPSET", 5498 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5499 5500 if (IsMips16) 5501 Builder.defineMacro("__mips16", Twine(1)); 5502 5503 if (IsMicromips) 5504 Builder.defineMacro("__mips_micromips", Twine(1)); 5505 5506 if (IsNan2008) 5507 Builder.defineMacro("__mips_nan2008", Twine(1)); 5508 5509 switch (DspRev) { 5510 default: 5511 break; 5512 case DSP1: 5513 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 5514 Builder.defineMacro("__mips_dsp", Twine(1)); 5515 break; 5516 case DSP2: 5517 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 5518 Builder.defineMacro("__mips_dspr2", Twine(1)); 5519 Builder.defineMacro("__mips_dsp", Twine(1)); 5520 break; 5521 } 5522 5523 if (HasMSA) 5524 Builder.defineMacro("__mips_msa", Twine(1)); 5525 5526 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 5527 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 5528 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 5529 5530 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 5531 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 5532 } 5533 5534 void getTargetBuiltins(const Builtin::Info *&Records, 5535 unsigned &NumRecords) const override { 5536 Records = BuiltinInfo; 5537 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 5538 } 5539 bool hasFeature(StringRef Feature) const override { 5540 return llvm::StringSwitch<bool>(Feature) 5541 .Case("mips", true) 5542 .Case("fp64", HasFP64) 5543 .Default(false); 5544 } 5545 BuiltinVaListKind getBuiltinVaListKind() const override { 5546 return TargetInfo::VoidPtrBuiltinVaList; 5547 } 5548 void getGCCRegNames(const char * const *&Names, 5549 unsigned &NumNames) const override { 5550 static const char *const GCCRegNames[] = { 5551 // CPU register names 5552 // Must match second column of GCCRegAliases 5553 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 5554 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 5555 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 5556 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 5557 // Floating point register names 5558 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 5559 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 5560 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 5561 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 5562 // Hi/lo and condition register names 5563 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 5564 "$fcc5","$fcc6","$fcc7", 5565 // MSA register names 5566 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 5567 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 5568 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 5569 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 5570 // MSA control register names 5571 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 5572 "$msarequest", "$msamap", "$msaunmap" 5573 }; 5574 Names = GCCRegNames; 5575 NumNames = llvm::array_lengthof(GCCRegNames); 5576 } 5577 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5578 unsigned &NumAliases) const override = 0; 5579 bool validateAsmConstraint(const char *&Name, 5580 TargetInfo::ConstraintInfo &Info) const override { 5581 switch (*Name) { 5582 default: 5583 return false; 5584 5585 case 'r': // CPU registers. 5586 case 'd': // Equivalent to "r" unless generating MIPS16 code. 5587 case 'y': // Equivalent to "r", backwards compatibility only. 5588 case 'f': // floating-point registers. 5589 case 'c': // $25 for indirect jumps 5590 case 'l': // lo register 5591 case 'x': // hilo register pair 5592 Info.setAllowsRegister(); 5593 return true; 5594 case 'R': // An address that can be used in a non-macro load or store 5595 Info.setAllowsMemory(); 5596 return true; 5597 } 5598 } 5599 5600 const char *getClobbers() const override { 5601 // FIXME: Implement! 5602 return ""; 5603 } 5604 5605 bool handleTargetFeatures(std::vector<std::string> &Features, 5606 DiagnosticsEngine &Diags) override { 5607 IsMips16 = false; 5608 IsMicromips = false; 5609 IsNan2008 = false; 5610 IsSingleFloat = false; 5611 FloatABI = HardFloat; 5612 DspRev = NoDSP; 5613 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 5614 5615 for (std::vector<std::string>::iterator it = Features.begin(), 5616 ie = Features.end(); it != ie; ++it) { 5617 if (*it == "+single-float") 5618 IsSingleFloat = true; 5619 else if (*it == "+soft-float") 5620 FloatABI = SoftFloat; 5621 else if (*it == "+mips16") 5622 IsMips16 = true; 5623 else if (*it == "+micromips") 5624 IsMicromips = true; 5625 else if (*it == "+dsp") 5626 DspRev = std::max(DspRev, DSP1); 5627 else if (*it == "+dspr2") 5628 DspRev = std::max(DspRev, DSP2); 5629 else if (*it == "+msa") 5630 HasMSA = true; 5631 else if (*it == "+fp64") 5632 HasFP64 = true; 5633 else if (*it == "-fp64") 5634 HasFP64 = false; 5635 else if (*it == "+nan2008") 5636 IsNan2008 = true; 5637 } 5638 5639 // Remove front-end specific options. 5640 std::vector<std::string>::iterator it = 5641 std::find(Features.begin(), Features.end(), "+soft-float"); 5642 if (it != Features.end()) 5643 Features.erase(it); 5644 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5645 if (it != Features.end()) 5646 Features.erase(it); 5647 5648 setDescriptionString(); 5649 5650 return true; 5651 } 5652 5653 int getEHDataRegisterNumber(unsigned RegNo) const override { 5654 if (RegNo == 0) return 4; 5655 if (RegNo == 1) return 5; 5656 return -1; 5657 } 5658 }; 5659 5660 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5661 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5662 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5663 ALL_LANGUAGES }, 5664 #include "clang/Basic/BuiltinsMips.def" 5665 }; 5666 5667 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5668 public: 5669 Mips32TargetInfoBase(const llvm::Triple &Triple) 5670 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 5671 SizeType = UnsignedInt; 5672 PtrDiffType = SignedInt; 5673 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5674 } 5675 bool setABI(const std::string &Name) override { 5676 if ((Name == "o32") || (Name == "eabi")) { 5677 ABI = Name; 5678 return true; 5679 } else if (Name == "32") { 5680 ABI = "o32"; 5681 return true; 5682 } else 5683 return false; 5684 } 5685 void getTargetDefines(const LangOptions &Opts, 5686 MacroBuilder &Builder) const override { 5687 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5688 5689 Builder.defineMacro("__mips", "32"); 5690 5691 if (ABI == "o32") { 5692 Builder.defineMacro("__mips_o32"); 5693 Builder.defineMacro("_ABIO32", "1"); 5694 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5695 } 5696 else if (ABI == "eabi") 5697 Builder.defineMacro("__mips_eabi"); 5698 else 5699 llvm_unreachable("Invalid ABI for Mips32."); 5700 } 5701 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5702 unsigned &NumAliases) const override { 5703 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5704 { { "at" }, "$1" }, 5705 { { "v0" }, "$2" }, 5706 { { "v1" }, "$3" }, 5707 { { "a0" }, "$4" }, 5708 { { "a1" }, "$5" }, 5709 { { "a2" }, "$6" }, 5710 { { "a3" }, "$7" }, 5711 { { "t0" }, "$8" }, 5712 { { "t1" }, "$9" }, 5713 { { "t2" }, "$10" }, 5714 { { "t3" }, "$11" }, 5715 { { "t4" }, "$12" }, 5716 { { "t5" }, "$13" }, 5717 { { "t6" }, "$14" }, 5718 { { "t7" }, "$15" }, 5719 { { "s0" }, "$16" }, 5720 { { "s1" }, "$17" }, 5721 { { "s2" }, "$18" }, 5722 { { "s3" }, "$19" }, 5723 { { "s4" }, "$20" }, 5724 { { "s5" }, "$21" }, 5725 { { "s6" }, "$22" }, 5726 { { "s7" }, "$23" }, 5727 { { "t8" }, "$24" }, 5728 { { "t9" }, "$25" }, 5729 { { "k0" }, "$26" }, 5730 { { "k1" }, "$27" }, 5731 { { "gp" }, "$28" }, 5732 { { "sp","$sp" }, "$29" }, 5733 { { "fp","$fp" }, "$30" }, 5734 { { "ra" }, "$31" } 5735 }; 5736 Aliases = GCCRegAliases; 5737 NumAliases = llvm::array_lengthof(GCCRegAliases); 5738 } 5739 }; 5740 5741 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5742 void setDescriptionString() override { 5743 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5744 } 5745 5746 public: 5747 Mips32EBTargetInfo(const llvm::Triple &Triple) 5748 : Mips32TargetInfoBase(Triple) { 5749 } 5750 void getTargetDefines(const LangOptions &Opts, 5751 MacroBuilder &Builder) const override { 5752 DefineStd(Builder, "MIPSEB", Opts); 5753 Builder.defineMacro("_MIPSEB"); 5754 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5755 } 5756 }; 5757 5758 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5759 void setDescriptionString() override { 5760 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 5761 } 5762 5763 public: 5764 Mips32ELTargetInfo(const llvm::Triple &Triple) 5765 : Mips32TargetInfoBase(Triple) { 5766 BigEndian = false; 5767 } 5768 void getTargetDefines(const LangOptions &Opts, 5769 MacroBuilder &Builder) const override { 5770 DefineStd(Builder, "MIPSEL", Opts); 5771 Builder.defineMacro("_MIPSEL"); 5772 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5773 } 5774 }; 5775 5776 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5777 public: 5778 Mips64TargetInfoBase(const llvm::Triple &Triple) 5779 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 5780 LongWidth = LongAlign = 64; 5781 PointerWidth = PointerAlign = 64; 5782 LongDoubleWidth = LongDoubleAlign = 128; 5783 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5784 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5785 LongDoubleWidth = LongDoubleAlign = 64; 5786 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5787 } 5788 SuitableAlign = 128; 5789 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5790 } 5791 bool setABI(const std::string &Name) override { 5792 if (Name == "n32") { 5793 LongWidth = LongAlign = 32; 5794 PointerWidth = PointerAlign = 32; 5795 ABI = Name; 5796 return true; 5797 } else if (Name == "n64") { 5798 ABI = Name; 5799 return true; 5800 } else if (Name == "64") { 5801 ABI = "n64"; 5802 return true; 5803 } else 5804 return false; 5805 } 5806 void getTargetDefines(const LangOptions &Opts, 5807 MacroBuilder &Builder) const override { 5808 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5809 5810 Builder.defineMacro("__mips", "64"); 5811 Builder.defineMacro("__mips64"); 5812 Builder.defineMacro("__mips64__"); 5813 5814 if (ABI == "n32") { 5815 Builder.defineMacro("__mips_n32"); 5816 Builder.defineMacro("_ABIN32", "2"); 5817 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5818 } 5819 else if (ABI == "n64") { 5820 Builder.defineMacro("__mips_n64"); 5821 Builder.defineMacro("_ABI64", "3"); 5822 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5823 } 5824 else 5825 llvm_unreachable("Invalid ABI for Mips64."); 5826 } 5827 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5828 unsigned &NumAliases) const override { 5829 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5830 { { "at" }, "$1" }, 5831 { { "v0" }, "$2" }, 5832 { { "v1" }, "$3" }, 5833 { { "a0" }, "$4" }, 5834 { { "a1" }, "$5" }, 5835 { { "a2" }, "$6" }, 5836 { { "a3" }, "$7" }, 5837 { { "a4" }, "$8" }, 5838 { { "a5" }, "$9" }, 5839 { { "a6" }, "$10" }, 5840 { { "a7" }, "$11" }, 5841 { { "t0" }, "$12" }, 5842 { { "t1" }, "$13" }, 5843 { { "t2" }, "$14" }, 5844 { { "t3" }, "$15" }, 5845 { { "s0" }, "$16" }, 5846 { { "s1" }, "$17" }, 5847 { { "s2" }, "$18" }, 5848 { { "s3" }, "$19" }, 5849 { { "s4" }, "$20" }, 5850 { { "s5" }, "$21" }, 5851 { { "s6" }, "$22" }, 5852 { { "s7" }, "$23" }, 5853 { { "t8" }, "$24" }, 5854 { { "t9" }, "$25" }, 5855 { { "k0" }, "$26" }, 5856 { { "k1" }, "$27" }, 5857 { { "gp" }, "$28" }, 5858 { { "sp","$sp" }, "$29" }, 5859 { { "fp","$fp" }, "$30" }, 5860 { { "ra" }, "$31" } 5861 }; 5862 Aliases = GCCRegAliases; 5863 NumAliases = llvm::array_lengthof(GCCRegAliases); 5864 } 5865 }; 5866 5867 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5868 void setDescriptionString() override { 5869 if (ABI == "n32") 5870 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5871 else 5872 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5873 5874 } 5875 5876 public: 5877 Mips64EBTargetInfo(const llvm::Triple &Triple) 5878 : Mips64TargetInfoBase(Triple) {} 5879 void getTargetDefines(const LangOptions &Opts, 5880 MacroBuilder &Builder) const override { 5881 DefineStd(Builder, "MIPSEB", Opts); 5882 Builder.defineMacro("_MIPSEB"); 5883 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5884 } 5885 }; 5886 5887 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5888 void setDescriptionString() override { 5889 if (ABI == "n32") 5890 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5891 else 5892 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 5893 } 5894 public: 5895 Mips64ELTargetInfo(const llvm::Triple &Triple) 5896 : Mips64TargetInfoBase(Triple) { 5897 // Default ABI is n64. 5898 BigEndian = false; 5899 } 5900 void getTargetDefines(const LangOptions &Opts, 5901 MacroBuilder &Builder) const override { 5902 DefineStd(Builder, "MIPSEL", Opts); 5903 Builder.defineMacro("_MIPSEL"); 5904 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5905 } 5906 }; 5907 } // end anonymous namespace. 5908 5909 namespace { 5910 class PNaClTargetInfo : public TargetInfo { 5911 public: 5912 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5913 BigEndian = false; 5914 this->UserLabelPrefix = ""; 5915 this->LongAlign = 32; 5916 this->LongWidth = 32; 5917 this->PointerAlign = 32; 5918 this->PointerWidth = 32; 5919 this->IntMaxType = TargetInfo::SignedLongLong; 5920 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5921 this->Int64Type = TargetInfo::SignedLongLong; 5922 this->DoubleAlign = 64; 5923 this->LongDoubleWidth = 64; 5924 this->LongDoubleAlign = 64; 5925 this->SizeType = TargetInfo::UnsignedInt; 5926 this->PtrDiffType = TargetInfo::SignedInt; 5927 this->IntPtrType = TargetInfo::SignedInt; 5928 this->RegParmMax = 0; // Disallow regparm 5929 } 5930 5931 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5932 } 5933 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 5934 Builder.defineMacro("__le32__"); 5935 Builder.defineMacro("__pnacl__"); 5936 } 5937 void getTargetDefines(const LangOptions &Opts, 5938 MacroBuilder &Builder) const override { 5939 getArchDefines(Opts, Builder); 5940 } 5941 bool hasFeature(StringRef Feature) const override { 5942 return Feature == "pnacl"; 5943 } 5944 void getTargetBuiltins(const Builtin::Info *&Records, 5945 unsigned &NumRecords) const override { 5946 } 5947 BuiltinVaListKind getBuiltinVaListKind() const override { 5948 return TargetInfo::PNaClABIBuiltinVaList; 5949 } 5950 void getGCCRegNames(const char * const *&Names, 5951 unsigned &NumNames) const override; 5952 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5953 unsigned &NumAliases) const override; 5954 bool validateAsmConstraint(const char *&Name, 5955 TargetInfo::ConstraintInfo &Info) const override { 5956 return false; 5957 } 5958 5959 const char *getClobbers() const override { 5960 return ""; 5961 } 5962 }; 5963 5964 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5965 unsigned &NumNames) const { 5966 Names = NULL; 5967 NumNames = 0; 5968 } 5969 5970 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5971 unsigned &NumAliases) const { 5972 Aliases = NULL; 5973 NumAliases = 0; 5974 } 5975 } // end anonymous namespace. 5976 5977 namespace { 5978 static const unsigned SPIRAddrSpaceMap[] = { 5979 1, // opencl_global 5980 3, // opencl_local 5981 2, // opencl_constant 5982 0, // cuda_device 5983 0, // cuda_constant 5984 0 // cuda_shared 5985 }; 5986 class SPIRTargetInfo : public TargetInfo { 5987 public: 5988 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5989 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5990 "SPIR target must use unknown OS"); 5991 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5992 "SPIR target must use unknown environment type"); 5993 BigEndian = false; 5994 TLSSupported = false; 5995 LongWidth = LongAlign = 64; 5996 AddrSpaceMap = &SPIRAddrSpaceMap; 5997 UseAddrSpaceMapMangling = true; 5998 // Define available target features 5999 // These must be defined in sorted order! 6000 NoAsmVariants = true; 6001 } 6002 void getTargetDefines(const LangOptions &Opts, 6003 MacroBuilder &Builder) const override { 6004 DefineStd(Builder, "SPIR", Opts); 6005 } 6006 bool hasFeature(StringRef Feature) const override { 6007 return Feature == "spir"; 6008 } 6009 6010 void getTargetBuiltins(const Builtin::Info *&Records, 6011 unsigned &NumRecords) const override {} 6012 const char *getClobbers() const override { 6013 return ""; 6014 } 6015 void getGCCRegNames(const char * const *&Names, 6016 unsigned &NumNames) const override {} 6017 bool validateAsmConstraint(const char *&Name, 6018 TargetInfo::ConstraintInfo &info) const override { 6019 return true; 6020 } 6021 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6022 unsigned &NumAliases) const override {} 6023 BuiltinVaListKind getBuiltinVaListKind() const override { 6024 return TargetInfo::VoidPtrBuiltinVaList; 6025 } 6026 }; 6027 6028 6029 class SPIR32TargetInfo : public SPIRTargetInfo { 6030 public: 6031 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6032 PointerWidth = PointerAlign = 32; 6033 SizeType = TargetInfo::UnsignedInt; 6034 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6035 DescriptionString 6036 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6037 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6038 } 6039 void getTargetDefines(const LangOptions &Opts, 6040 MacroBuilder &Builder) const override { 6041 DefineStd(Builder, "SPIR32", Opts); 6042 } 6043 }; 6044 6045 class SPIR64TargetInfo : public SPIRTargetInfo { 6046 public: 6047 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6048 PointerWidth = PointerAlign = 64; 6049 SizeType = TargetInfo::UnsignedLong; 6050 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6051 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6052 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6053 } 6054 void getTargetDefines(const LangOptions &Opts, 6055 MacroBuilder &Builder) const override { 6056 DefineStd(Builder, "SPIR64", Opts); 6057 } 6058 }; 6059 } 6060 6061 namespace { 6062 class XCoreTargetInfo : public TargetInfo { 6063 static const Builtin::Info BuiltinInfo[]; 6064 public: 6065 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6066 BigEndian = false; 6067 NoAsmVariants = true; 6068 LongLongAlign = 32; 6069 SuitableAlign = 32; 6070 DoubleAlign = LongDoubleAlign = 32; 6071 SizeType = UnsignedInt; 6072 PtrDiffType = SignedInt; 6073 IntPtrType = SignedInt; 6074 WCharType = UnsignedChar; 6075 WIntType = UnsignedInt; 6076 UseZeroLengthBitfieldAlignment = true; 6077 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6078 "-f64:32-a:0:32-n32"; 6079 } 6080 void getTargetDefines(const LangOptions &Opts, 6081 MacroBuilder &Builder) const override { 6082 Builder.defineMacro("__XS1B__"); 6083 } 6084 void getTargetBuiltins(const Builtin::Info *&Records, 6085 unsigned &NumRecords) const override { 6086 Records = BuiltinInfo; 6087 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6088 } 6089 BuiltinVaListKind getBuiltinVaListKind() const override { 6090 return TargetInfo::VoidPtrBuiltinVaList; 6091 } 6092 const char *getClobbers() const override { 6093 return ""; 6094 } 6095 void getGCCRegNames(const char * const *&Names, 6096 unsigned &NumNames) const override { 6097 static const char * const GCCRegNames[] = { 6098 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6099 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6100 }; 6101 Names = GCCRegNames; 6102 NumNames = llvm::array_lengthof(GCCRegNames); 6103 } 6104 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6105 unsigned &NumAliases) const override { 6106 Aliases = NULL; 6107 NumAliases = 0; 6108 } 6109 bool validateAsmConstraint(const char *&Name, 6110 TargetInfo::ConstraintInfo &Info) const override { 6111 return false; 6112 } 6113 int getEHDataRegisterNumber(unsigned RegNo) const override { 6114 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6115 return (RegNo < 2)? RegNo : -1; 6116 } 6117 }; 6118 6119 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6120 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6121 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6122 ALL_LANGUAGES }, 6123 #include "clang/Basic/BuiltinsXCore.def" 6124 }; 6125 } // end anonymous namespace. 6126 6127 6128 //===----------------------------------------------------------------------===// 6129 // Driver code 6130 //===----------------------------------------------------------------------===// 6131 6132 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6133 llvm::Triple::OSType os = Triple.getOS(); 6134 6135 switch (Triple.getArch()) { 6136 default: 6137 return NULL; 6138 6139 case llvm::Triple::arm64: 6140 if (Triple.isOSDarwin()) 6141 return new DarwinARM64TargetInfo(Triple); 6142 6143 switch (os) { 6144 case llvm::Triple::Linux: 6145 return new LinuxTargetInfo<ARM64leTargetInfo>(Triple); 6146 case llvm::Triple::NetBSD: 6147 return new NetBSDTargetInfo<ARM64leTargetInfo>(Triple); 6148 default: 6149 return new ARM64leTargetInfo(Triple); 6150 } 6151 6152 case llvm::Triple::arm64_be: 6153 switch (os) { 6154 case llvm::Triple::Linux: 6155 return new LinuxTargetInfo<ARM64beTargetInfo>(Triple); 6156 case llvm::Triple::NetBSD: 6157 return new NetBSDTargetInfo<ARM64beTargetInfo>(Triple); 6158 default: 6159 return new ARM64beTargetInfo(Triple); 6160 } 6161 6162 case llvm::Triple::xcore: 6163 return new XCoreTargetInfo(Triple); 6164 6165 case llvm::Triple::hexagon: 6166 return new HexagonTargetInfo(Triple); 6167 6168 case llvm::Triple::aarch64: 6169 switch (os) { 6170 case llvm::Triple::Linux: 6171 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6172 case llvm::Triple::NetBSD: 6173 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6174 default: 6175 return new AArch64leTargetInfo(Triple); 6176 } 6177 6178 case llvm::Triple::aarch64_be: 6179 switch (os) { 6180 case llvm::Triple::Linux: 6181 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6182 case llvm::Triple::NetBSD: 6183 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6184 default: 6185 return new AArch64beTargetInfo(Triple); 6186 } 6187 6188 case llvm::Triple::arm: 6189 case llvm::Triple::thumb: 6190 if (Triple.isOSBinFormatMachO()) 6191 return new DarwinARMTargetInfo(Triple); 6192 6193 switch (os) { 6194 case llvm::Triple::Linux: 6195 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6196 case llvm::Triple::FreeBSD: 6197 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6198 case llvm::Triple::NetBSD: 6199 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6200 case llvm::Triple::OpenBSD: 6201 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6202 case llvm::Triple::Bitrig: 6203 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6204 case llvm::Triple::RTEMS: 6205 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6206 case llvm::Triple::NaCl: 6207 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6208 case llvm::Triple::Win32: 6209 switch (Triple.getEnvironment()) { 6210 default: 6211 return new ARMleTargetInfo(Triple); 6212 case llvm::Triple::Itanium: 6213 return new ItaniumWindowsARMleTargetInfo(Triple); 6214 case llvm::Triple::MSVC: 6215 return new MicrosoftARMleTargetInfo(Triple); 6216 } 6217 default: 6218 return new ARMleTargetInfo(Triple); 6219 } 6220 6221 case llvm::Triple::armeb: 6222 case llvm::Triple::thumbeb: 6223 if (Triple.isOSDarwin()) 6224 return new DarwinARMTargetInfo(Triple); 6225 6226 switch (os) { 6227 case llvm::Triple::Linux: 6228 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6229 case llvm::Triple::FreeBSD: 6230 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6231 case llvm::Triple::NetBSD: 6232 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6233 case llvm::Triple::OpenBSD: 6234 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6235 case llvm::Triple::Bitrig: 6236 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6237 case llvm::Triple::RTEMS: 6238 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6239 case llvm::Triple::NaCl: 6240 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6241 default: 6242 return new ARMbeTargetInfo(Triple); 6243 } 6244 6245 case llvm::Triple::msp430: 6246 return new MSP430TargetInfo(Triple); 6247 6248 case llvm::Triple::mips: 6249 switch (os) { 6250 case llvm::Triple::Linux: 6251 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6252 case llvm::Triple::RTEMS: 6253 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6254 case llvm::Triple::FreeBSD: 6255 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6256 case llvm::Triple::NetBSD: 6257 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6258 default: 6259 return new Mips32EBTargetInfo(Triple); 6260 } 6261 6262 case llvm::Triple::mipsel: 6263 switch (os) { 6264 case llvm::Triple::Linux: 6265 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6266 case llvm::Triple::RTEMS: 6267 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6268 case llvm::Triple::FreeBSD: 6269 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6270 case llvm::Triple::NetBSD: 6271 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6272 case llvm::Triple::NaCl: 6273 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6274 default: 6275 return new Mips32ELTargetInfo(Triple); 6276 } 6277 6278 case llvm::Triple::mips64: 6279 switch (os) { 6280 case llvm::Triple::Linux: 6281 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6282 case llvm::Triple::RTEMS: 6283 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6284 case llvm::Triple::FreeBSD: 6285 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6286 case llvm::Triple::NetBSD: 6287 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6288 case llvm::Triple::OpenBSD: 6289 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6290 default: 6291 return new Mips64EBTargetInfo(Triple); 6292 } 6293 6294 case llvm::Triple::mips64el: 6295 switch (os) { 6296 case llvm::Triple::Linux: 6297 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6298 case llvm::Triple::RTEMS: 6299 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6300 case llvm::Triple::FreeBSD: 6301 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6302 case llvm::Triple::NetBSD: 6303 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6304 case llvm::Triple::OpenBSD: 6305 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6306 default: 6307 return new Mips64ELTargetInfo(Triple); 6308 } 6309 6310 case llvm::Triple::le32: 6311 switch (os) { 6312 case llvm::Triple::NaCl: 6313 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6314 default: 6315 return NULL; 6316 } 6317 6318 case llvm::Triple::ppc: 6319 if (Triple.isOSDarwin()) 6320 return new DarwinPPC32TargetInfo(Triple); 6321 switch (os) { 6322 case llvm::Triple::Linux: 6323 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6324 case llvm::Triple::FreeBSD: 6325 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6326 case llvm::Triple::NetBSD: 6327 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6328 case llvm::Triple::OpenBSD: 6329 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6330 case llvm::Triple::RTEMS: 6331 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6332 default: 6333 return new PPC32TargetInfo(Triple); 6334 } 6335 6336 case llvm::Triple::ppc64: 6337 if (Triple.isOSDarwin()) 6338 return new DarwinPPC64TargetInfo(Triple); 6339 switch (os) { 6340 case llvm::Triple::Linux: 6341 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6342 case llvm::Triple::Lv2: 6343 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6344 case llvm::Triple::FreeBSD: 6345 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6346 case llvm::Triple::NetBSD: 6347 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6348 default: 6349 return new PPC64TargetInfo(Triple); 6350 } 6351 6352 case llvm::Triple::ppc64le: 6353 switch (os) { 6354 case llvm::Triple::Linux: 6355 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6356 default: 6357 return new PPC64TargetInfo(Triple); 6358 } 6359 6360 case llvm::Triple::nvptx: 6361 return new NVPTX32TargetInfo(Triple); 6362 case llvm::Triple::nvptx64: 6363 return new NVPTX64TargetInfo(Triple); 6364 6365 case llvm::Triple::r600: 6366 return new R600TargetInfo(Triple); 6367 6368 case llvm::Triple::sparc: 6369 switch (os) { 6370 case llvm::Triple::Linux: 6371 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 6372 case llvm::Triple::AuroraUX: 6373 return new AuroraUXSparcV8TargetInfo(Triple); 6374 case llvm::Triple::Solaris: 6375 return new SolarisSparcV8TargetInfo(Triple); 6376 case llvm::Triple::NetBSD: 6377 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 6378 case llvm::Triple::OpenBSD: 6379 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 6380 case llvm::Triple::RTEMS: 6381 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 6382 default: 6383 return new SparcV8TargetInfo(Triple); 6384 } 6385 6386 case llvm::Triple::sparcv9: 6387 switch (os) { 6388 case llvm::Triple::Linux: 6389 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 6390 case llvm::Triple::AuroraUX: 6391 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 6392 case llvm::Triple::Solaris: 6393 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 6394 case llvm::Triple::NetBSD: 6395 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 6396 case llvm::Triple::OpenBSD: 6397 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 6398 case llvm::Triple::FreeBSD: 6399 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 6400 default: 6401 return new SparcV9TargetInfo(Triple); 6402 } 6403 6404 case llvm::Triple::systemz: 6405 switch (os) { 6406 case llvm::Triple::Linux: 6407 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 6408 default: 6409 return new SystemZTargetInfo(Triple); 6410 } 6411 6412 case llvm::Triple::tce: 6413 return new TCETargetInfo(Triple); 6414 6415 case llvm::Triple::x86: 6416 if (Triple.isOSDarwin()) 6417 return new DarwinI386TargetInfo(Triple); 6418 6419 switch (os) { 6420 case llvm::Triple::AuroraUX: 6421 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 6422 case llvm::Triple::Linux: 6423 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 6424 case llvm::Triple::DragonFly: 6425 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 6426 case llvm::Triple::NetBSD: 6427 return new NetBSDI386TargetInfo(Triple); 6428 case llvm::Triple::OpenBSD: 6429 return new OpenBSDI386TargetInfo(Triple); 6430 case llvm::Triple::Bitrig: 6431 return new BitrigI386TargetInfo(Triple); 6432 case llvm::Triple::FreeBSD: 6433 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6434 case llvm::Triple::KFreeBSD: 6435 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 6436 case llvm::Triple::Minix: 6437 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 6438 case llvm::Triple::Solaris: 6439 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 6440 case llvm::Triple::Win32: { 6441 switch (Triple.getEnvironment()) { 6442 default: 6443 return new X86_32TargetInfo(Triple); 6444 case llvm::Triple::Cygnus: 6445 return new CygwinX86_32TargetInfo(Triple); 6446 case llvm::Triple::GNU: 6447 return new MinGWX86_32TargetInfo(Triple); 6448 case llvm::Triple::MSVC: 6449 return new MicrosoftX86_32TargetInfo(Triple); 6450 } 6451 } 6452 case llvm::Triple::Haiku: 6453 return new HaikuX86_32TargetInfo(Triple); 6454 case llvm::Triple::RTEMS: 6455 return new RTEMSX86_32TargetInfo(Triple); 6456 case llvm::Triple::NaCl: 6457 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 6458 default: 6459 return new X86_32TargetInfo(Triple); 6460 } 6461 6462 case llvm::Triple::x86_64: 6463 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 6464 return new DarwinX86_64TargetInfo(Triple); 6465 6466 switch (os) { 6467 case llvm::Triple::AuroraUX: 6468 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 6469 case llvm::Triple::Linux: 6470 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 6471 case llvm::Triple::DragonFly: 6472 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 6473 case llvm::Triple::NetBSD: 6474 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 6475 case llvm::Triple::OpenBSD: 6476 return new OpenBSDX86_64TargetInfo(Triple); 6477 case llvm::Triple::Bitrig: 6478 return new BitrigX86_64TargetInfo(Triple); 6479 case llvm::Triple::FreeBSD: 6480 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6481 case llvm::Triple::KFreeBSD: 6482 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 6483 case llvm::Triple::Solaris: 6484 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 6485 case llvm::Triple::Win32: { 6486 switch (Triple.getEnvironment()) { 6487 default: 6488 return new X86_64TargetInfo(Triple); 6489 case llvm::Triple::GNU: 6490 return new MinGWX86_64TargetInfo(Triple); 6491 case llvm::Triple::MSVC: 6492 return new MicrosoftX86_64TargetInfo(Triple); 6493 } 6494 } 6495 case llvm::Triple::NaCl: 6496 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 6497 default: 6498 return new X86_64TargetInfo(Triple); 6499 } 6500 6501 case llvm::Triple::spir: { 6502 if (Triple.getOS() != llvm::Triple::UnknownOS || 6503 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6504 return NULL; 6505 return new SPIR32TargetInfo(Triple); 6506 } 6507 case llvm::Triple::spir64: { 6508 if (Triple.getOS() != llvm::Triple::UnknownOS || 6509 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 6510 return NULL; 6511 return new SPIR64TargetInfo(Triple); 6512 } 6513 } 6514 } 6515 6516 /// CreateTargetInfo - Return the target info object for the specified target 6517 /// triple. 6518 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 6519 TargetOptions *Opts) { 6520 llvm::Triple Triple(Opts->Triple); 6521 6522 // Construct the target 6523 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 6524 if (!Target) { 6525 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 6526 return 0; 6527 } 6528 Target->setTargetOpts(Opts); 6529 6530 // Set the target CPU if specified. 6531 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 6532 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 6533 return 0; 6534 } 6535 6536 // Set the target ABI if specified. 6537 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 6538 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 6539 return 0; 6540 } 6541 6542 // Set the fp math unit. 6543 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 6544 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 6545 return 0; 6546 } 6547 6548 // Compute the default target features, we need the target to handle this 6549 // because features may have dependencies on one another. 6550 llvm::StringMap<bool> Features; 6551 Target->getDefaultFeatures(Features); 6552 6553 // Apply the user specified deltas. 6554 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 6555 I < N; ++I) { 6556 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 6557 // Apply the feature via the target. 6558 bool Enabled = Name[0] == '+'; 6559 Target->setFeatureEnabled(Features, Name + 1, Enabled); 6560 } 6561 6562 // Add the features to the compile options. 6563 // 6564 // FIXME: If we are completely confident that we have the right set, we only 6565 // need to pass the minuses. 6566 Opts->Features.clear(); 6567 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 6568 ie = Features.end(); it != ie; ++it) 6569 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 6570 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 6571 return 0; 6572 6573 return Target.release(); 6574 } 6575