1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Support/TargetParser.h" 31 #include <algorithm> 32 #include <memory> 33 34 using namespace clang; 35 36 //===----------------------------------------------------------------------===// 37 // Common code shared among targets. 38 //===----------------------------------------------------------------------===// 39 40 /// DefineStd - Define a macro name and standard variants. For example if 41 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 42 /// when in GNU mode. 43 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 44 const LangOptions &Opts) { 45 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 46 47 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 48 // in the user's namespace. 49 if (Opts.GNUMode) 50 Builder.defineMacro(MacroName); 51 52 // Define __unix. 53 Builder.defineMacro("__" + MacroName); 54 55 // Define __unix__. 56 Builder.defineMacro("__" + MacroName + "__"); 57 } 58 59 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 60 bool Tuning = true) { 61 Builder.defineMacro("__" + CPUName); 62 Builder.defineMacro("__" + CPUName + "__"); 63 if (Tuning) 64 Builder.defineMacro("__tune_" + CPUName + "__"); 65 } 66 67 //===----------------------------------------------------------------------===// 68 // Defines specific to certain operating systems. 69 //===----------------------------------------------------------------------===// 70 71 namespace { 72 template<typename TgtInfo> 73 class OSTargetInfo : public TgtInfo { 74 protected: 75 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 76 MacroBuilder &Builder) const=0; 77 public: 78 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 79 void getTargetDefines(const LangOptions &Opts, 80 MacroBuilder &Builder) const override { 81 TgtInfo::getTargetDefines(Opts, Builder); 82 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 83 } 84 85 }; 86 } // end anonymous namespace 87 88 89 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 90 const llvm::Triple &Triple, 91 StringRef &PlatformName, 92 VersionTuple &PlatformMinVersion) { 93 Builder.defineMacro("__APPLE_CC__", "6000"); 94 Builder.defineMacro("__APPLE__"); 95 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 96 // AddressSanitizer doesn't play well with source fortification, which is on 97 // by default on Darwin. 98 if (Opts.Sanitize.has(SanitizerKind::Address)) 99 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 100 101 if (!Opts.ObjCAutoRefCount) { 102 // __weak is always defined, for use in blocks and with objc pointers. 103 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 104 105 // Darwin defines __strong even in C mode (just to nothing). 106 if (Opts.getGC() != LangOptions::NonGC) 107 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 108 else 109 Builder.defineMacro("__strong", ""); 110 111 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 112 // allow this in C, since one might have block pointers in structs that 113 // are used in pure C code and in Objective-C ARC. 114 Builder.defineMacro("__unsafe_unretained", ""); 115 } 116 117 if (Opts.Static) 118 Builder.defineMacro("__STATIC__"); 119 else 120 Builder.defineMacro("__DYNAMIC__"); 121 122 if (Opts.POSIXThreads) 123 Builder.defineMacro("_REENTRANT"); 124 125 // Get the platform type and version number from the triple. 126 unsigned Maj, Min, Rev; 127 if (Triple.isMacOSX()) { 128 Triple.getMacOSXVersion(Maj, Min, Rev); 129 PlatformName = "macosx"; 130 } else { 131 Triple.getOSVersion(Maj, Min, Rev); 132 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 133 } 134 135 // If -target arch-pc-win32-macho option specified, we're 136 // generating code for Win32 ABI. No need to emit 137 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 138 if (PlatformName == "win32") { 139 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 140 return; 141 } 142 143 // Set the appropriate OS version define. 144 if (Triple.isiOS()) { 145 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 146 char Str[6]; 147 Str[0] = '0' + Maj; 148 Str[1] = '0' + (Min / 10); 149 Str[2] = '0' + (Min % 10); 150 Str[3] = '0' + (Rev / 10); 151 Str[4] = '0' + (Rev % 10); 152 Str[5] = '\0'; 153 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 154 Str); 155 } else if (Triple.isMacOSX()) { 156 // Note that the Driver allows versions which aren't representable in the 157 // define (because we only get a single digit for the minor and micro 158 // revision numbers). So, we limit them to the maximum representable 159 // version. 160 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 161 char Str[7]; 162 if (Maj < 10 || (Maj == 10 && Min < 10)) { 163 Str[0] = '0' + (Maj / 10); 164 Str[1] = '0' + (Maj % 10); 165 Str[2] = '0' + std::min(Min, 9U); 166 Str[3] = '0' + std::min(Rev, 9U); 167 Str[4] = '\0'; 168 } else { 169 // Handle versions > 10.9. 170 Str[0] = '0' + (Maj / 10); 171 Str[1] = '0' + (Maj % 10); 172 Str[2] = '0' + (Min / 10); 173 Str[3] = '0' + (Min % 10); 174 Str[4] = '0' + (Rev / 10); 175 Str[5] = '0' + (Rev % 10); 176 Str[6] = '\0'; 177 } 178 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 179 } 180 181 // Tell users about the kernel if there is one. 182 if (Triple.isOSDarwin()) 183 Builder.defineMacro("__MACH__"); 184 185 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 186 } 187 188 namespace { 189 // CloudABI Target 190 template <typename Target> 191 class CloudABITargetInfo : public OSTargetInfo<Target> { 192 protected: 193 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 194 MacroBuilder &Builder) const override { 195 Builder.defineMacro("__CloudABI__"); 196 Builder.defineMacro("__ELF__"); 197 198 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 199 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 200 Builder.defineMacro("__STDC_UTF_16__"); 201 Builder.defineMacro("__STDC_UTF_32__"); 202 } 203 204 public: 205 CloudABITargetInfo(const llvm::Triple &Triple) 206 : OSTargetInfo<Target>(Triple) { 207 this->UserLabelPrefix = ""; 208 } 209 }; 210 211 template<typename Target> 212 class DarwinTargetInfo : public OSTargetInfo<Target> { 213 protected: 214 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 215 MacroBuilder &Builder) const override { 216 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 217 this->PlatformMinVersion); 218 } 219 220 public: 221 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 222 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 223 this->MCountName = "\01mcount"; 224 } 225 226 std::string isValidSectionSpecifier(StringRef SR) const override { 227 // Let MCSectionMachO validate this. 228 StringRef Segment, Section; 229 unsigned TAA, StubSize; 230 bool HasTAA; 231 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 232 TAA, HasTAA, StubSize); 233 } 234 235 const char *getStaticInitSectionSpecifier() const override { 236 // FIXME: We should return 0 when building kexts. 237 return "__TEXT,__StaticInit,regular,pure_instructions"; 238 } 239 240 /// Darwin does not support protected visibility. Darwin's "default" 241 /// is very similar to ELF's "protected"; Darwin requires a "weak" 242 /// attribute on declarations that can be dynamically replaced. 243 bool hasProtectedVisibility() const override { 244 return false; 245 } 246 }; 247 248 249 // DragonFlyBSD Target 250 template<typename Target> 251 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 252 protected: 253 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 254 MacroBuilder &Builder) const override { 255 // DragonFly defines; list based off of gcc output 256 Builder.defineMacro("__DragonFly__"); 257 Builder.defineMacro("__DragonFly_cc_version", "100001"); 258 Builder.defineMacro("__ELF__"); 259 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 260 Builder.defineMacro("__tune_i386__"); 261 DefineStd(Builder, "unix", Opts); 262 } 263 public: 264 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 265 : OSTargetInfo<Target>(Triple) { 266 this->UserLabelPrefix = ""; 267 268 switch (Triple.getArch()) { 269 default: 270 case llvm::Triple::x86: 271 case llvm::Triple::x86_64: 272 this->MCountName = ".mcount"; 273 break; 274 } 275 } 276 }; 277 278 // FreeBSD Target 279 template<typename Target> 280 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 281 protected: 282 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 283 MacroBuilder &Builder) const override { 284 // FreeBSD defines; list based off of gcc output 285 286 unsigned Release = Triple.getOSMajorVersion(); 287 if (Release == 0U) 288 Release = 8; 289 290 Builder.defineMacro("__FreeBSD__", Twine(Release)); 291 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 292 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 293 DefineStd(Builder, "unix", Opts); 294 Builder.defineMacro("__ELF__"); 295 296 // On FreeBSD, wchar_t contains the number of the code point as 297 // used by the character set of the locale. These character sets are 298 // not necessarily a superset of ASCII. 299 // 300 // FIXME: This is wrong; the macro refers to the numerical values 301 // of wchar_t *literals*, which are not locale-dependent. However, 302 // FreeBSD systems apparently depend on us getting this wrong, and 303 // setting this to 1 is conforming even if all the basic source 304 // character literals have the same encoding as char and wchar_t. 305 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 306 } 307 public: 308 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 309 this->UserLabelPrefix = ""; 310 311 switch (Triple.getArch()) { 312 default: 313 case llvm::Triple::x86: 314 case llvm::Triple::x86_64: 315 this->MCountName = ".mcount"; 316 break; 317 case llvm::Triple::mips: 318 case llvm::Triple::mipsel: 319 case llvm::Triple::ppc: 320 case llvm::Triple::ppc64: 321 case llvm::Triple::ppc64le: 322 this->MCountName = "_mcount"; 323 break; 324 case llvm::Triple::arm: 325 this->MCountName = "__mcount"; 326 break; 327 } 328 } 329 }; 330 331 // GNU/kFreeBSD Target 332 template<typename Target> 333 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 334 protected: 335 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 336 MacroBuilder &Builder) const override { 337 // GNU/kFreeBSD defines; list based off of gcc output 338 339 DefineStd(Builder, "unix", Opts); 340 Builder.defineMacro("__FreeBSD_kernel__"); 341 Builder.defineMacro("__GLIBC__"); 342 Builder.defineMacro("__ELF__"); 343 if (Opts.POSIXThreads) 344 Builder.defineMacro("_REENTRANT"); 345 if (Opts.CPlusPlus) 346 Builder.defineMacro("_GNU_SOURCE"); 347 } 348 public: 349 KFreeBSDTargetInfo(const llvm::Triple &Triple) 350 : OSTargetInfo<Target>(Triple) { 351 this->UserLabelPrefix = ""; 352 } 353 }; 354 355 // Minix Target 356 template<typename Target> 357 class MinixTargetInfo : public OSTargetInfo<Target> { 358 protected: 359 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 360 MacroBuilder &Builder) const override { 361 // Minix defines 362 363 Builder.defineMacro("__minix", "3"); 364 Builder.defineMacro("_EM_WSIZE", "4"); 365 Builder.defineMacro("_EM_PSIZE", "4"); 366 Builder.defineMacro("_EM_SSIZE", "2"); 367 Builder.defineMacro("_EM_LSIZE", "4"); 368 Builder.defineMacro("_EM_FSIZE", "4"); 369 Builder.defineMacro("_EM_DSIZE", "8"); 370 Builder.defineMacro("__ELF__"); 371 DefineStd(Builder, "unix", Opts); 372 } 373 public: 374 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 375 this->UserLabelPrefix = ""; 376 } 377 }; 378 379 // Linux target 380 template<typename Target> 381 class LinuxTargetInfo : public OSTargetInfo<Target> { 382 protected: 383 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 384 MacroBuilder &Builder) const override { 385 // Linux defines; list based off of gcc output 386 DefineStd(Builder, "unix", Opts); 387 DefineStd(Builder, "linux", Opts); 388 Builder.defineMacro("__gnu_linux__"); 389 Builder.defineMacro("__ELF__"); 390 if (Triple.getEnvironment() == llvm::Triple::Android) { 391 Builder.defineMacro("__ANDROID__", "1"); 392 unsigned Maj, Min, Rev; 393 Triple.getEnvironmentVersion(Maj, Min, Rev); 394 this->PlatformName = "android"; 395 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 396 } 397 if (Opts.POSIXThreads) 398 Builder.defineMacro("_REENTRANT"); 399 if (Opts.CPlusPlus) 400 Builder.defineMacro("_GNU_SOURCE"); 401 } 402 public: 403 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 404 this->UserLabelPrefix = ""; 405 this->WIntType = TargetInfo::UnsignedInt; 406 407 switch (Triple.getArch()) { 408 default: 409 break; 410 case llvm::Triple::ppc: 411 case llvm::Triple::ppc64: 412 case llvm::Triple::ppc64le: 413 this->MCountName = "_mcount"; 414 break; 415 } 416 } 417 418 const char *getStaticInitSectionSpecifier() const override { 419 return ".text.startup"; 420 } 421 }; 422 423 // NetBSD Target 424 template<typename Target> 425 class NetBSDTargetInfo : public OSTargetInfo<Target> { 426 protected: 427 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 428 MacroBuilder &Builder) const override { 429 // NetBSD defines; list based off of gcc output 430 Builder.defineMacro("__NetBSD__"); 431 Builder.defineMacro("__unix__"); 432 Builder.defineMacro("__ELF__"); 433 if (Opts.POSIXThreads) 434 Builder.defineMacro("_POSIX_THREADS"); 435 436 switch (Triple.getArch()) { 437 default: 438 break; 439 case llvm::Triple::arm: 440 case llvm::Triple::armeb: 441 case llvm::Triple::thumb: 442 case llvm::Triple::thumbeb: 443 Builder.defineMacro("__ARM_DWARF_EH__"); 444 break; 445 } 446 } 447 public: 448 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 449 this->UserLabelPrefix = ""; 450 this->MCountName = "_mcount"; 451 } 452 }; 453 454 // OpenBSD Target 455 template<typename Target> 456 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 457 protected: 458 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 459 MacroBuilder &Builder) const override { 460 // OpenBSD defines; list based off of gcc output 461 462 Builder.defineMacro("__OpenBSD__"); 463 DefineStd(Builder, "unix", Opts); 464 Builder.defineMacro("__ELF__"); 465 if (Opts.POSIXThreads) 466 Builder.defineMacro("_REENTRANT"); 467 } 468 public: 469 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->TLSSupported = false; 472 473 switch (Triple.getArch()) { 474 default: 475 case llvm::Triple::x86: 476 case llvm::Triple::x86_64: 477 case llvm::Triple::arm: 478 case llvm::Triple::sparc: 479 this->MCountName = "__mcount"; 480 break; 481 case llvm::Triple::mips64: 482 case llvm::Triple::mips64el: 483 case llvm::Triple::ppc: 484 case llvm::Triple::sparcv9: 485 this->MCountName = "_mcount"; 486 break; 487 } 488 } 489 }; 490 491 // Bitrig Target 492 template<typename Target> 493 class BitrigTargetInfo : public OSTargetInfo<Target> { 494 protected: 495 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 496 MacroBuilder &Builder) const override { 497 // Bitrig defines; list based off of gcc output 498 499 Builder.defineMacro("__Bitrig__"); 500 DefineStd(Builder, "unix", Opts); 501 Builder.defineMacro("__ELF__"); 502 if (Opts.POSIXThreads) 503 Builder.defineMacro("_REENTRANT"); 504 505 switch (Triple.getArch()) { 506 default: 507 break; 508 case llvm::Triple::arm: 509 case llvm::Triple::armeb: 510 case llvm::Triple::thumb: 511 case llvm::Triple::thumbeb: 512 Builder.defineMacro("__ARM_DWARF_EH__"); 513 break; 514 } 515 } 516 public: 517 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 518 this->UserLabelPrefix = ""; 519 this->MCountName = "__mcount"; 520 } 521 }; 522 523 // PSP Target 524 template<typename Target> 525 class PSPTargetInfo : public OSTargetInfo<Target> { 526 protected: 527 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 528 MacroBuilder &Builder) const override { 529 // PSP defines; list based on the output of the pspdev gcc toolchain. 530 Builder.defineMacro("PSP"); 531 Builder.defineMacro("_PSP"); 532 Builder.defineMacro("__psp__"); 533 Builder.defineMacro("__ELF__"); 534 } 535 public: 536 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 537 this->UserLabelPrefix = ""; 538 } 539 }; 540 541 // PS3 PPU Target 542 template<typename Target> 543 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 544 protected: 545 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 546 MacroBuilder &Builder) const override { 547 // PS3 PPU defines. 548 Builder.defineMacro("__PPC__"); 549 Builder.defineMacro("__PPU__"); 550 Builder.defineMacro("__CELLOS_LV2__"); 551 Builder.defineMacro("__ELF__"); 552 Builder.defineMacro("__LP32__"); 553 Builder.defineMacro("_ARCH_PPC64"); 554 Builder.defineMacro("__powerpc64__"); 555 } 556 public: 557 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 this->LongWidth = this->LongAlign = 32; 560 this->PointerWidth = this->PointerAlign = 32; 561 this->IntMaxType = TargetInfo::SignedLongLong; 562 this->Int64Type = TargetInfo::SignedLongLong; 563 this->SizeType = TargetInfo::UnsignedInt; 564 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 565 } 566 }; 567 568 template <typename Target> 569 class PS4OSTargetInfo : public OSTargetInfo<Target> { 570 protected: 571 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 572 MacroBuilder &Builder) const override { 573 Builder.defineMacro("__FreeBSD__", "9"); 574 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 575 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 576 DefineStd(Builder, "unix", Opts); 577 Builder.defineMacro("__ELF__"); 578 Builder.defineMacro("__PS4__"); 579 } 580 public: 581 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 582 this->WCharType = this->UnsignedShort; 583 584 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 585 this->MaxTLSAlign = 256; 586 this->UserLabelPrefix = ""; 587 588 switch (Triple.getArch()) { 589 default: 590 case llvm::Triple::x86_64: 591 this->MCountName = ".mcount"; 592 break; 593 } 594 } 595 }; 596 597 // Solaris target 598 template<typename Target> 599 class SolarisTargetInfo : public OSTargetInfo<Target> { 600 protected: 601 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 602 MacroBuilder &Builder) const override { 603 DefineStd(Builder, "sun", Opts); 604 DefineStd(Builder, "unix", Opts); 605 Builder.defineMacro("__ELF__"); 606 Builder.defineMacro("__svr4__"); 607 Builder.defineMacro("__SVR4"); 608 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 609 // newer, but to 500 for everything else. feature_test.h has a check to 610 // ensure that you are not using C99 with an old version of X/Open or C89 611 // with a new version. 612 if (Opts.C99) 613 Builder.defineMacro("_XOPEN_SOURCE", "600"); 614 else 615 Builder.defineMacro("_XOPEN_SOURCE", "500"); 616 if (Opts.CPlusPlus) 617 Builder.defineMacro("__C99FEATURES__"); 618 Builder.defineMacro("_LARGEFILE_SOURCE"); 619 Builder.defineMacro("_LARGEFILE64_SOURCE"); 620 Builder.defineMacro("__EXTENSIONS__"); 621 Builder.defineMacro("_REENTRANT"); 622 } 623 public: 624 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 625 this->UserLabelPrefix = ""; 626 this->WCharType = this->SignedInt; 627 // FIXME: WIntType should be SignedLong 628 } 629 }; 630 631 // Windows target 632 template<typename Target> 633 class WindowsTargetInfo : public OSTargetInfo<Target> { 634 protected: 635 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 636 MacroBuilder &Builder) const override { 637 Builder.defineMacro("_WIN32"); 638 } 639 void getVisualStudioDefines(const LangOptions &Opts, 640 MacroBuilder &Builder) const { 641 if (Opts.CPlusPlus) { 642 if (Opts.RTTIData) 643 Builder.defineMacro("_CPPRTTI"); 644 645 if (Opts.CXXExceptions) 646 Builder.defineMacro("_CPPUNWIND"); 647 } 648 649 if (Opts.Bool) 650 Builder.defineMacro("__BOOL_DEFINED"); 651 652 if (!Opts.CharIsSigned) 653 Builder.defineMacro("_CHAR_UNSIGNED"); 654 655 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 656 // but it works for now. 657 if (Opts.POSIXThreads) 658 Builder.defineMacro("_MT"); 659 660 if (Opts.MSCompatibilityVersion) { 661 Builder.defineMacro("_MSC_VER", 662 Twine(Opts.MSCompatibilityVersion / 100000)); 663 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 664 // FIXME We cannot encode the revision information into 32-bits 665 Builder.defineMacro("_MSC_BUILD", Twine(1)); 666 667 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 668 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 669 } 670 671 if (Opts.MicrosoftExt) { 672 Builder.defineMacro("_MSC_EXTENSIONS"); 673 674 if (Opts.CPlusPlus11) { 675 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 676 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 677 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 678 } 679 } 680 681 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 682 } 683 684 public: 685 WindowsTargetInfo(const llvm::Triple &Triple) 686 : OSTargetInfo<Target>(Triple) {} 687 }; 688 689 template <typename Target> 690 class NaClTargetInfo : public OSTargetInfo<Target> { 691 protected: 692 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 693 MacroBuilder &Builder) const override { 694 if (Opts.POSIXThreads) 695 Builder.defineMacro("_REENTRANT"); 696 if (Opts.CPlusPlus) 697 Builder.defineMacro("_GNU_SOURCE"); 698 699 DefineStd(Builder, "unix", Opts); 700 Builder.defineMacro("__ELF__"); 701 Builder.defineMacro("__native_client__"); 702 } 703 704 public: 705 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 706 this->UserLabelPrefix = ""; 707 this->LongAlign = 32; 708 this->LongWidth = 32; 709 this->PointerAlign = 32; 710 this->PointerWidth = 32; 711 this->IntMaxType = TargetInfo::SignedLongLong; 712 this->Int64Type = TargetInfo::SignedLongLong; 713 this->DoubleAlign = 64; 714 this->LongDoubleWidth = 64; 715 this->LongDoubleAlign = 64; 716 this->LongLongWidth = 64; 717 this->LongLongAlign = 64; 718 this->SizeType = TargetInfo::UnsignedInt; 719 this->PtrDiffType = TargetInfo::SignedInt; 720 this->IntPtrType = TargetInfo::SignedInt; 721 // RegParmMax is inherited from the underlying architecture 722 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 723 if (Triple.getArch() == llvm::Triple::arm) { 724 // Handled in ARM's setABI(). 725 } else if (Triple.getArch() == llvm::Triple::x86) { 726 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 727 } else if (Triple.getArch() == llvm::Triple::x86_64) { 728 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 729 } else if (Triple.getArch() == llvm::Triple::mipsel) { 730 // Handled on mips' setDataLayoutString. 731 } else { 732 assert(Triple.getArch() == llvm::Triple::le32); 733 this->DataLayoutString = "e-p:32:32-i64:64"; 734 } 735 } 736 }; 737 738 namespace { 739 // WebAssembly target 740 template <typename Target> 741 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 742 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 743 MacroBuilder &Builder) const final { 744 // A common platform macro. 745 if (Opts.POSIXThreads) 746 Builder.defineMacro("_REENTRANT"); 747 // Follow g++ convention and predefine _GNU_SOURCE for C++. 748 if (Opts.CPlusPlus) 749 Builder.defineMacro("_GNU_SOURCE"); 750 } 751 752 // As an optimization, group static init code together in a section. 753 const char *getStaticInitSectionSpecifier() const final { 754 return ".text.__startup"; 755 } 756 757 public: 758 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 759 : OSTargetInfo<Target>(Triple) { 760 this->MCountName = "__mcount"; 761 this->UserLabelPrefix = ""; 762 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 763 } 764 }; 765 } // end anonymous namespace 766 767 //===----------------------------------------------------------------------===// 768 // Specific target implementations. 769 //===----------------------------------------------------------------------===// 770 771 // PPC abstract base class 772 class PPCTargetInfo : public TargetInfo { 773 static const Builtin::Info BuiltinInfo[]; 774 static const char * const GCCRegNames[]; 775 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 776 std::string CPU; 777 778 // Target cpu features. 779 bool HasVSX; 780 bool HasP8Vector; 781 bool HasP8Crypto; 782 bool HasDirectMove; 783 bool HasQPX; 784 bool HasHTM; 785 bool HasBPERMD; 786 bool HasExtDiv; 787 788 protected: 789 std::string ABI; 790 791 public: 792 PPCTargetInfo(const llvm::Triple &Triple) 793 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 794 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 795 HasBPERMD(false), HasExtDiv(false) { 796 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 797 SimdDefaultAlign = 128; 798 LongDoubleWidth = LongDoubleAlign = 128; 799 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 800 } 801 802 /// \brief Flags for architecture specific defines. 803 typedef enum { 804 ArchDefineNone = 0, 805 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 806 ArchDefinePpcgr = 1 << 1, 807 ArchDefinePpcsq = 1 << 2, 808 ArchDefine440 = 1 << 3, 809 ArchDefine603 = 1 << 4, 810 ArchDefine604 = 1 << 5, 811 ArchDefinePwr4 = 1 << 6, 812 ArchDefinePwr5 = 1 << 7, 813 ArchDefinePwr5x = 1 << 8, 814 ArchDefinePwr6 = 1 << 9, 815 ArchDefinePwr6x = 1 << 10, 816 ArchDefinePwr7 = 1 << 11, 817 ArchDefinePwr8 = 1 << 12, 818 ArchDefineA2 = 1 << 13, 819 ArchDefineA2q = 1 << 14 820 } ArchDefineTypes; 821 822 // Note: GCC recognizes the following additional cpus: 823 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 824 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 825 // titan, rs64. 826 bool setCPU(const std::string &Name) override { 827 bool CPUKnown = llvm::StringSwitch<bool>(Name) 828 .Case("generic", true) 829 .Case("440", true) 830 .Case("450", true) 831 .Case("601", true) 832 .Case("602", true) 833 .Case("603", true) 834 .Case("603e", true) 835 .Case("603ev", true) 836 .Case("604", true) 837 .Case("604e", true) 838 .Case("620", true) 839 .Case("630", true) 840 .Case("g3", true) 841 .Case("7400", true) 842 .Case("g4", true) 843 .Case("7450", true) 844 .Case("g4+", true) 845 .Case("750", true) 846 .Case("970", true) 847 .Case("g5", true) 848 .Case("a2", true) 849 .Case("a2q", true) 850 .Case("e500mc", true) 851 .Case("e5500", true) 852 .Case("power3", true) 853 .Case("pwr3", true) 854 .Case("power4", true) 855 .Case("pwr4", true) 856 .Case("power5", true) 857 .Case("pwr5", true) 858 .Case("power5x", true) 859 .Case("pwr5x", true) 860 .Case("power6", true) 861 .Case("pwr6", true) 862 .Case("power6x", true) 863 .Case("pwr6x", true) 864 .Case("power7", true) 865 .Case("pwr7", true) 866 .Case("power8", true) 867 .Case("pwr8", true) 868 .Case("powerpc", true) 869 .Case("ppc", true) 870 .Case("powerpc64", true) 871 .Case("ppc64", true) 872 .Case("powerpc64le", true) 873 .Case("ppc64le", true) 874 .Default(false); 875 876 if (CPUKnown) 877 CPU = Name; 878 879 return CPUKnown; 880 } 881 882 883 StringRef getABI() const override { return ABI; } 884 885 void getTargetBuiltins(const Builtin::Info *&Records, 886 unsigned &NumRecords) const override { 887 Records = BuiltinInfo; 888 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 889 } 890 891 bool isCLZForZeroUndef() const override { return false; } 892 893 void getTargetDefines(const LangOptions &Opts, 894 MacroBuilder &Builder) const override; 895 896 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 897 StringRef CPU, 898 std::vector<std::string> &FeaturesVec) const override; 899 900 bool handleTargetFeatures(std::vector<std::string> &Features, 901 DiagnosticsEngine &Diags) override; 902 bool hasFeature(StringRef Feature) const override; 903 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 904 bool Enabled) const override; 905 906 void getGCCRegNames(const char * const *&Names, 907 unsigned &NumNames) const override; 908 void getGCCRegAliases(const GCCRegAlias *&Aliases, 909 unsigned &NumAliases) const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 if (getTriple().getArch() == llvm::Triple::ppc64le || 1230 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1233 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1234 if (PointerWidth == 64) 1235 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1236 } 1237 1238 // FIXME: The following are not yet generated here by Clang, but are 1239 // generated by GCC: 1240 // 1241 // _SOFT_FLOAT_ 1242 // __RECIP_PRECISION__ 1243 // __APPLE_ALTIVEC__ 1244 // __RECIP__ 1245 // __RECIPF__ 1246 // __RSQRTE__ 1247 // __RSQRTEF__ 1248 // _SOFT_DOUBLE_ 1249 // __NO_LWSYNC__ 1250 // __HAVE_BSWAP__ 1251 // __LONGDOUBLE128 1252 // __CMODEL_MEDIUM__ 1253 // __CMODEL_LARGE__ 1254 // _CALL_SYSV 1255 // _CALL_DARWIN 1256 // __NO_FPRS__ 1257 } 1258 1259 // Handle explicit options being passed to the compiler here: if we've 1260 // explicitly turned off vsx and turned on power8-vector or direct-move then 1261 // go ahead and error since the customer has expressed a somewhat incompatible 1262 // set of options. 1263 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1264 std::vector<std::string> &FeaturesVec) { 1265 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1267 FeaturesVec.end()) { 1268 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1269 FeaturesVec.end()) { 1270 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1271 << "-mno-vsx"; 1272 return false; 1273 } 1274 1275 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1276 FeaturesVec.end()) { 1277 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1278 << "-mno-vsx"; 1279 return false; 1280 } 1281 } 1282 1283 return true; 1284 } 1285 1286 bool PPCTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 1287 DiagnosticsEngine &Diags, StringRef CPU, 1288 std::vector<std::string> &FeaturesVec) const { 1289 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1290 .Case("7400", true) 1291 .Case("g4", true) 1292 .Case("7450", true) 1293 .Case("g4+", true) 1294 .Case("970", true) 1295 .Case("g5", true) 1296 .Case("pwr6", true) 1297 .Case("pwr7", true) 1298 .Case("pwr8", true) 1299 .Case("ppc64", true) 1300 .Case("ppc64le", true) 1301 .Default(false); 1302 1303 Features["qpx"] = (CPU == "a2q"); 1304 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1305 .Case("ppc64le", true) 1306 .Case("pwr8", true) 1307 .Default(false); 1308 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1309 .Case("ppc64le", true) 1310 .Case("pwr8", true) 1311 .Default(false); 1312 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1313 .Case("ppc64le", true) 1314 .Case("pwr8", true) 1315 .Case("pwr7", true) 1316 .Default(false); 1317 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1318 .Case("ppc64le", true) 1319 .Case("pwr8", true) 1320 .Case("pwr7", true) 1321 .Default(false); 1322 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1323 .Case("ppc64le", true) 1324 .Case("pwr8", true) 1325 .Default(false); 1326 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1327 .Case("ppc64le", true) 1328 .Case("pwr8", true) 1329 .Case("pwr7", true) 1330 .Default(false); 1331 1332 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1333 return false; 1334 1335 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1336 } 1337 1338 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1339 return llvm::StringSwitch<bool>(Feature) 1340 .Case("powerpc", true) 1341 .Case("vsx", HasVSX) 1342 .Case("power8-vector", HasP8Vector) 1343 .Case("crypto", HasP8Crypto) 1344 .Case("direct-move", HasDirectMove) 1345 .Case("qpx", HasQPX) 1346 .Case("htm", HasHTM) 1347 .Case("bpermd", HasBPERMD) 1348 .Case("extdiv", HasExtDiv) 1349 .Default(false); 1350 } 1351 1352 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1353 StringRef Name, bool Enabled) const { 1354 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1355 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1356 // incompatible options. 1357 if (Enabled) { 1358 if (Name == "vsx") { 1359 Features[Name] = true; 1360 } else if (Name == "direct-move") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else if (Name == "power8-vector") { 1363 Features[Name] = Features["vsx"] = true; 1364 } else { 1365 Features[Name] = true; 1366 } 1367 } else { 1368 if (Name == "vsx") { 1369 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1370 false; 1371 } else { 1372 Features[Name] = false; 1373 } 1374 } 1375 } 1376 1377 const char * const PPCTargetInfo::GCCRegNames[] = { 1378 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1379 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1380 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1381 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1382 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1383 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1384 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1385 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1386 "mq", "lr", "ctr", "ap", 1387 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1388 "xer", 1389 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1390 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1391 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1392 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1393 "vrsave", "vscr", 1394 "spe_acc", "spefscr", 1395 "sfp" 1396 }; 1397 1398 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1399 unsigned &NumNames) const { 1400 Names = GCCRegNames; 1401 NumNames = llvm::array_lengthof(GCCRegNames); 1402 } 1403 1404 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1405 // While some of these aliases do map to different registers 1406 // they still share the same register name. 1407 { { "0" }, "r0" }, 1408 { { "1"}, "r1" }, 1409 { { "2" }, "r2" }, 1410 { { "3" }, "r3" }, 1411 { { "4" }, "r4" }, 1412 { { "5" }, "r5" }, 1413 { { "6" }, "r6" }, 1414 { { "7" }, "r7" }, 1415 { { "8" }, "r8" }, 1416 { { "9" }, "r9" }, 1417 { { "10" }, "r10" }, 1418 { { "11" }, "r11" }, 1419 { { "12" }, "r12" }, 1420 { { "13" }, "r13" }, 1421 { { "14" }, "r14" }, 1422 { { "15" }, "r15" }, 1423 { { "16" }, "r16" }, 1424 { { "17" }, "r17" }, 1425 { { "18" }, "r18" }, 1426 { { "19" }, "r19" }, 1427 { { "20" }, "r20" }, 1428 { { "21" }, "r21" }, 1429 { { "22" }, "r22" }, 1430 { { "23" }, "r23" }, 1431 { { "24" }, "r24" }, 1432 { { "25" }, "r25" }, 1433 { { "26" }, "r26" }, 1434 { { "27" }, "r27" }, 1435 { { "28" }, "r28" }, 1436 { { "29" }, "r29" }, 1437 { { "30" }, "r30" }, 1438 { { "31" }, "r31" }, 1439 { { "fr0" }, "f0" }, 1440 { { "fr1" }, "f1" }, 1441 { { "fr2" }, "f2" }, 1442 { { "fr3" }, "f3" }, 1443 { { "fr4" }, "f4" }, 1444 { { "fr5" }, "f5" }, 1445 { { "fr6" }, "f6" }, 1446 { { "fr7" }, "f7" }, 1447 { { "fr8" }, "f8" }, 1448 { { "fr9" }, "f9" }, 1449 { { "fr10" }, "f10" }, 1450 { { "fr11" }, "f11" }, 1451 { { "fr12" }, "f12" }, 1452 { { "fr13" }, "f13" }, 1453 { { "fr14" }, "f14" }, 1454 { { "fr15" }, "f15" }, 1455 { { "fr16" }, "f16" }, 1456 { { "fr17" }, "f17" }, 1457 { { "fr18" }, "f18" }, 1458 { { "fr19" }, "f19" }, 1459 { { "fr20" }, "f20" }, 1460 { { "fr21" }, "f21" }, 1461 { { "fr22" }, "f22" }, 1462 { { "fr23" }, "f23" }, 1463 { { "fr24" }, "f24" }, 1464 { { "fr25" }, "f25" }, 1465 { { "fr26" }, "f26" }, 1466 { { "fr27" }, "f27" }, 1467 { { "fr28" }, "f28" }, 1468 { { "fr29" }, "f29" }, 1469 { { "fr30" }, "f30" }, 1470 { { "fr31" }, "f31" }, 1471 { { "cc" }, "cr0" }, 1472 }; 1473 1474 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1475 unsigned &NumAliases) const { 1476 Aliases = GCCRegAliases; 1477 NumAliases = llvm::array_lengthof(GCCRegAliases); 1478 } 1479 1480 class PPC32TargetInfo : public PPCTargetInfo { 1481 public: 1482 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1483 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1484 1485 switch (getTriple().getOS()) { 1486 case llvm::Triple::Linux: 1487 case llvm::Triple::FreeBSD: 1488 case llvm::Triple::NetBSD: 1489 SizeType = UnsignedInt; 1490 PtrDiffType = SignedInt; 1491 IntPtrType = SignedInt; 1492 break; 1493 default: 1494 break; 1495 } 1496 1497 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1498 LongDoubleWidth = LongDoubleAlign = 64; 1499 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1500 } 1501 1502 // PPC32 supports atomics up to 4 bytes. 1503 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1504 } 1505 1506 BuiltinVaListKind getBuiltinVaListKind() const override { 1507 // This is the ELF definition, and is overridden by the Darwin sub-target 1508 return TargetInfo::PowerABIBuiltinVaList; 1509 } 1510 }; 1511 1512 // Note: ABI differences may eventually require us to have a separate 1513 // TargetInfo for little endian. 1514 class PPC64TargetInfo : public PPCTargetInfo { 1515 public: 1516 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1517 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1518 IntMaxType = SignedLong; 1519 Int64Type = SignedLong; 1520 1521 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1522 DataLayoutString = "e-m:e-i64:64-n32:64"; 1523 ABI = "elfv2"; 1524 } else { 1525 DataLayoutString = "E-m:e-i64:64-n32:64"; 1526 ABI = "elfv1"; 1527 } 1528 1529 switch (getTriple().getOS()) { 1530 case llvm::Triple::FreeBSD: 1531 LongDoubleWidth = LongDoubleAlign = 64; 1532 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1533 break; 1534 case llvm::Triple::NetBSD: 1535 IntMaxType = SignedLongLong; 1536 Int64Type = SignedLongLong; 1537 break; 1538 default: 1539 break; 1540 } 1541 1542 // PPC64 supports atomics up to 8 bytes. 1543 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1544 } 1545 BuiltinVaListKind getBuiltinVaListKind() const override { 1546 return TargetInfo::CharPtrBuiltinVaList; 1547 } 1548 // PPC64 Linux-specific ABI options. 1549 bool setABI(const std::string &Name) override { 1550 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1551 ABI = Name; 1552 return true; 1553 } 1554 return false; 1555 } 1556 }; 1557 1558 class DarwinPPC32TargetInfo : 1559 public DarwinTargetInfo<PPC32TargetInfo> { 1560 public: 1561 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1562 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1563 HasAlignMac68kSupport = true; 1564 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1565 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1566 LongLongAlign = 32; 1567 SuitableAlign = 128; 1568 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1569 } 1570 BuiltinVaListKind getBuiltinVaListKind() const override { 1571 return TargetInfo::CharPtrBuiltinVaList; 1572 } 1573 }; 1574 1575 class DarwinPPC64TargetInfo : 1576 public DarwinTargetInfo<PPC64TargetInfo> { 1577 public: 1578 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1579 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1580 HasAlignMac68kSupport = true; 1581 SuitableAlign = 128; 1582 DataLayoutString = "E-m:o-i64:64-n32:64"; 1583 } 1584 }; 1585 1586 static const unsigned NVPTXAddrSpaceMap[] = { 1587 1, // opencl_global 1588 3, // opencl_local 1589 4, // opencl_constant 1590 // FIXME: generic has to be added to the target 1591 0, // opencl_generic 1592 1, // cuda_device 1593 4, // cuda_constant 1594 3, // cuda_shared 1595 }; 1596 1597 class NVPTXTargetInfo : public TargetInfo { 1598 static const char *const GCCRegNames[]; 1599 static const Builtin::Info BuiltinInfo[]; 1600 1601 // The GPU profiles supported by the NVPTX backend 1602 enum GPUKind { 1603 GK_NONE, 1604 GK_SM20, 1605 GK_SM21, 1606 GK_SM30, 1607 GK_SM35, 1608 GK_SM37, 1609 } GPU; 1610 1611 public: 1612 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1613 BigEndian = false; 1614 TLSSupported = false; 1615 LongWidth = LongAlign = 64; 1616 AddrSpaceMap = &NVPTXAddrSpaceMap; 1617 UseAddrSpaceMapMangling = true; 1618 // Define available target features 1619 // These must be defined in sorted order! 1620 NoAsmVariants = true; 1621 // Set the default GPU to sm20 1622 GPU = GK_SM20; 1623 } 1624 void getTargetDefines(const LangOptions &Opts, 1625 MacroBuilder &Builder) const override { 1626 Builder.defineMacro("__PTX__"); 1627 Builder.defineMacro("__NVPTX__"); 1628 if (Opts.CUDAIsDevice) { 1629 // Set __CUDA_ARCH__ for the GPU specified. 1630 std::string CUDAArchCode; 1631 switch (GPU) { 1632 case GK_SM20: 1633 CUDAArchCode = "200"; 1634 break; 1635 case GK_SM21: 1636 CUDAArchCode = "210"; 1637 break; 1638 case GK_SM30: 1639 CUDAArchCode = "300"; 1640 break; 1641 case GK_SM35: 1642 CUDAArchCode = "350"; 1643 break; 1644 case GK_SM37: 1645 CUDAArchCode = "370"; 1646 break; 1647 default: 1648 llvm_unreachable("Unhandled target CPU"); 1649 } 1650 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1651 } 1652 } 1653 void getTargetBuiltins(const Builtin::Info *&Records, 1654 unsigned &NumRecords) const override { 1655 Records = BuiltinInfo; 1656 NumRecords = clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin; 1657 } 1658 bool hasFeature(StringRef Feature) const override { 1659 return Feature == "ptx" || Feature == "nvptx"; 1660 } 1661 1662 void getGCCRegNames(const char *const *&Names, 1663 unsigned &NumNames) const override; 1664 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1665 unsigned &NumAliases) const override { 1666 // No aliases. 1667 Aliases = nullptr; 1668 NumAliases = 0; 1669 } 1670 bool validateAsmConstraint(const char *&Name, 1671 TargetInfo::ConstraintInfo &Info) const override { 1672 switch (*Name) { 1673 default: 1674 return false; 1675 case 'c': 1676 case 'h': 1677 case 'r': 1678 case 'l': 1679 case 'f': 1680 case 'd': 1681 Info.setAllowsRegister(); 1682 return true; 1683 } 1684 } 1685 const char *getClobbers() const override { 1686 // FIXME: Is this really right? 1687 return ""; 1688 } 1689 BuiltinVaListKind getBuiltinVaListKind() const override { 1690 // FIXME: implement 1691 return TargetInfo::CharPtrBuiltinVaList; 1692 } 1693 bool setCPU(const std::string &Name) override { 1694 GPU = llvm::StringSwitch<GPUKind>(Name) 1695 .Case("sm_20", GK_SM20) 1696 .Case("sm_21", GK_SM21) 1697 .Case("sm_30", GK_SM30) 1698 .Case("sm_35", GK_SM35) 1699 .Case("sm_37", GK_SM37) 1700 .Default(GK_NONE); 1701 1702 return GPU != GK_NONE; 1703 } 1704 }; 1705 1706 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1707 #define BUILTIN(ID, TYPE, ATTRS) \ 1708 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1709 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1710 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1711 #include "clang/Basic/BuiltinsNVPTX.def" 1712 }; 1713 1714 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1715 1716 void NVPTXTargetInfo::getGCCRegNames(const char *const *&Names, 1717 unsigned &NumNames) const { 1718 Names = GCCRegNames; 1719 NumNames = llvm::array_lengthof(GCCRegNames); 1720 } 1721 1722 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 32; 1726 SizeType = TargetInfo::UnsignedInt; 1727 PtrDiffType = TargetInfo::SignedInt; 1728 IntPtrType = TargetInfo::SignedInt; 1729 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1730 } 1731 }; 1732 1733 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1734 public: 1735 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1736 PointerWidth = PointerAlign = 64; 1737 SizeType = TargetInfo::UnsignedLong; 1738 PtrDiffType = TargetInfo::SignedLong; 1739 IntPtrType = TargetInfo::SignedLong; 1740 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1741 } 1742 }; 1743 1744 static const unsigned AMDGPUAddrSpaceMap[] = { 1745 1, // opencl_global 1746 3, // opencl_local 1747 2, // opencl_constant 1748 4, // opencl_generic 1749 1, // cuda_device 1750 2, // cuda_constant 1751 3 // cuda_shared 1752 }; 1753 1754 // If you edit the description strings, make sure you update 1755 // getPointerWidthV(). 1756 1757 static const char *DataLayoutStringR600 = 1758 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1759 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1760 1761 static const char *DataLayoutStringR600DoubleOps = 1762 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1763 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1764 1765 static const char *DataLayoutStringSI = 1766 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1767 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1768 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1769 1770 class AMDGPUTargetInfo : public TargetInfo { 1771 static const Builtin::Info BuiltinInfo[]; 1772 static const char * const GCCRegNames[]; 1773 1774 /// \brief The GPU profiles supported by the AMDGPU target. 1775 enum GPUKind { 1776 GK_NONE, 1777 GK_R600, 1778 GK_R600_DOUBLE_OPS, 1779 GK_R700, 1780 GK_R700_DOUBLE_OPS, 1781 GK_EVERGREEN, 1782 GK_EVERGREEN_DOUBLE_OPS, 1783 GK_NORTHERN_ISLANDS, 1784 GK_CAYMAN, 1785 GK_SOUTHERN_ISLANDS, 1786 GK_SEA_ISLANDS, 1787 GK_VOLCANIC_ISLANDS 1788 } GPU; 1789 1790 bool hasFP64:1; 1791 bool hasFMAF:1; 1792 bool hasLDEXPF:1; 1793 1794 public: 1795 AMDGPUTargetInfo(const llvm::Triple &Triple) 1796 : TargetInfo(Triple) { 1797 1798 if (Triple.getArch() == llvm::Triple::amdgcn) { 1799 DataLayoutString = DataLayoutStringSI; 1800 GPU = GK_SOUTHERN_ISLANDS; 1801 hasFP64 = true; 1802 hasFMAF = true; 1803 hasLDEXPF = true; 1804 } else { 1805 DataLayoutString = DataLayoutStringR600; 1806 GPU = GK_R600; 1807 hasFP64 = false; 1808 hasFMAF = false; 1809 hasLDEXPF = false; 1810 } 1811 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1812 UseAddrSpaceMapMangling = true; 1813 } 1814 1815 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1816 if (GPU <= GK_CAYMAN) 1817 return 32; 1818 1819 switch(AddrSpace) { 1820 default: 1821 return 64; 1822 case 0: 1823 case 3: 1824 case 5: 1825 return 32; 1826 } 1827 } 1828 1829 const char * getClobbers() const override { 1830 return ""; 1831 } 1832 1833 void getGCCRegNames(const char * const *&Names, 1834 unsigned &NumNames) const override; 1835 1836 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1837 unsigned &NumAliases) const override { 1838 Aliases = nullptr; 1839 NumAliases = 0; 1840 } 1841 1842 bool validateAsmConstraint(const char *&Name, 1843 TargetInfo::ConstraintInfo &info) const override { 1844 return true; 1845 } 1846 1847 void getTargetBuiltins(const Builtin::Info *&Records, 1848 unsigned &NumRecords) const override { 1849 Records = BuiltinInfo; 1850 NumRecords = clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin; 1851 } 1852 1853 void getTargetDefines(const LangOptions &Opts, 1854 MacroBuilder &Builder) const override { 1855 Builder.defineMacro("__R600__"); 1856 if (hasFMAF) 1857 Builder.defineMacro("__HAS_FMAF__"); 1858 if (hasLDEXPF) 1859 Builder.defineMacro("__HAS_LDEXPF__"); 1860 if (hasFP64 && Opts.OpenCL) 1861 Builder.defineMacro("cl_khr_fp64"); 1862 if (Opts.OpenCL) { 1863 if (GPU >= GK_NORTHERN_ISLANDS) { 1864 Builder.defineMacro("cl_khr_byte_addressable_store"); 1865 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1866 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1867 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1868 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1869 } 1870 } 1871 } 1872 1873 BuiltinVaListKind getBuiltinVaListKind() const override { 1874 return TargetInfo::CharPtrBuiltinVaList; 1875 } 1876 1877 bool setCPU(const std::string &Name) override { 1878 GPU = llvm::StringSwitch<GPUKind>(Name) 1879 .Case("r600" , GK_R600) 1880 .Case("rv610", GK_R600) 1881 .Case("rv620", GK_R600) 1882 .Case("rv630", GK_R600) 1883 .Case("rv635", GK_R600) 1884 .Case("rs780", GK_R600) 1885 .Case("rs880", GK_R600) 1886 .Case("rv670", GK_R600_DOUBLE_OPS) 1887 .Case("rv710", GK_R700) 1888 .Case("rv730", GK_R700) 1889 .Case("rv740", GK_R700_DOUBLE_OPS) 1890 .Case("rv770", GK_R700_DOUBLE_OPS) 1891 .Case("palm", GK_EVERGREEN) 1892 .Case("cedar", GK_EVERGREEN) 1893 .Case("sumo", GK_EVERGREEN) 1894 .Case("sumo2", GK_EVERGREEN) 1895 .Case("redwood", GK_EVERGREEN) 1896 .Case("juniper", GK_EVERGREEN) 1897 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1898 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1899 .Case("barts", GK_NORTHERN_ISLANDS) 1900 .Case("turks", GK_NORTHERN_ISLANDS) 1901 .Case("caicos", GK_NORTHERN_ISLANDS) 1902 .Case("cayman", GK_CAYMAN) 1903 .Case("aruba", GK_CAYMAN) 1904 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1905 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1906 .Case("verde", GK_SOUTHERN_ISLANDS) 1907 .Case("oland", GK_SOUTHERN_ISLANDS) 1908 .Case("hainan", GK_SOUTHERN_ISLANDS) 1909 .Case("bonaire", GK_SEA_ISLANDS) 1910 .Case("kabini", GK_SEA_ISLANDS) 1911 .Case("kaveri", GK_SEA_ISLANDS) 1912 .Case("hawaii", GK_SEA_ISLANDS) 1913 .Case("mullins", GK_SEA_ISLANDS) 1914 .Case("tonga", GK_VOLCANIC_ISLANDS) 1915 .Case("iceland", GK_VOLCANIC_ISLANDS) 1916 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1917 .Default(GK_NONE); 1918 1919 if (GPU == GK_NONE) { 1920 return false; 1921 } 1922 1923 // Set the correct data layout 1924 switch (GPU) { 1925 case GK_NONE: 1926 case GK_R600: 1927 case GK_R700: 1928 case GK_EVERGREEN: 1929 case GK_NORTHERN_ISLANDS: 1930 DataLayoutString = DataLayoutStringR600; 1931 hasFP64 = false; 1932 hasFMAF = false; 1933 hasLDEXPF = false; 1934 break; 1935 case GK_R600_DOUBLE_OPS: 1936 case GK_R700_DOUBLE_OPS: 1937 case GK_EVERGREEN_DOUBLE_OPS: 1938 case GK_CAYMAN: 1939 DataLayoutString = DataLayoutStringR600DoubleOps; 1940 hasFP64 = true; 1941 hasFMAF = true; 1942 hasLDEXPF = false; 1943 break; 1944 case GK_SOUTHERN_ISLANDS: 1945 case GK_SEA_ISLANDS: 1946 case GK_VOLCANIC_ISLANDS: 1947 DataLayoutString = DataLayoutStringSI; 1948 hasFP64 = true; 1949 hasFMAF = true; 1950 hasLDEXPF = true; 1951 break; 1952 } 1953 1954 return true; 1955 } 1956 }; 1957 1958 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1959 #define BUILTIN(ID, TYPE, ATTRS) \ 1960 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1961 #include "clang/Basic/BuiltinsAMDGPU.def" 1962 }; 1963 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1964 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1965 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1966 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1967 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1968 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1969 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1970 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1971 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1972 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1973 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1974 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1975 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1976 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1977 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1978 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1979 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1980 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1981 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1982 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1983 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1984 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1985 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1986 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1987 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1988 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1989 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1990 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1991 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1992 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1993 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1994 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1995 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1996 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1997 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1998 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1999 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2000 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2001 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2002 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2003 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2004 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2005 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2006 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2007 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2008 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2009 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2010 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2011 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2012 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 2013 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 2014 }; 2015 2016 void AMDGPUTargetInfo::getGCCRegNames(const char * const *&Names, 2017 unsigned &NumNames) const { 2018 Names = GCCRegNames; 2019 NumNames = llvm::array_lengthof(GCCRegNames); 2020 } 2021 2022 // Namespace for x86 abstract base class 2023 const Builtin::Info BuiltinInfo[] = { 2024 #define BUILTIN(ID, TYPE, ATTRS) \ 2025 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2026 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2027 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2028 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2029 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2030 #include "clang/Basic/BuiltinsX86.def" 2031 }; 2032 2033 static const char* const GCCRegNames[] = { 2034 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2035 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2036 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2037 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2038 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2039 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2040 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2041 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2042 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2043 }; 2044 2045 const TargetInfo::AddlRegName AddlRegNames[] = { 2046 { { "al", "ah", "eax", "rax" }, 0 }, 2047 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2048 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2049 { { "dl", "dh", "edx", "rdx" }, 1 }, 2050 { { "esi", "rsi" }, 4 }, 2051 { { "edi", "rdi" }, 5 }, 2052 { { "esp", "rsp" }, 7 }, 2053 { { "ebp", "rbp" }, 6 }, 2054 { { "r8d", "r8w", "r8b" }, 38 }, 2055 { { "r9d", "r9w", "r9b" }, 39 }, 2056 { { "r10d", "r10w", "r10b" }, 40 }, 2057 { { "r11d", "r11w", "r11b" }, 41 }, 2058 { { "r12d", "r12w", "r12b" }, 42 }, 2059 { { "r13d", "r13w", "r13b" }, 43 }, 2060 { { "r14d", "r14w", "r14b" }, 44 }, 2061 { { "r15d", "r15w", "r15b" }, 45 }, 2062 }; 2063 2064 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2065 // most of the implementation can be shared. 2066 class X86TargetInfo : public TargetInfo { 2067 enum X86SSEEnum { 2068 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2069 } SSELevel; 2070 enum MMX3DNowEnum { 2071 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2072 } MMX3DNowLevel; 2073 enum XOPEnum { 2074 NoXOP, 2075 SSE4A, 2076 FMA4, 2077 XOP 2078 } XOPLevel; 2079 2080 bool HasAES; 2081 bool HasPCLMUL; 2082 bool HasLZCNT; 2083 bool HasRDRND; 2084 bool HasFSGSBASE; 2085 bool HasBMI; 2086 bool HasBMI2; 2087 bool HasPOPCNT; 2088 bool HasRTM; 2089 bool HasPRFCHW; 2090 bool HasRDSEED; 2091 bool HasADX; 2092 bool HasTBM; 2093 bool HasFMA; 2094 bool HasF16C; 2095 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 2096 HasAVX512VL; 2097 bool HasSHA; 2098 bool HasCX16; 2099 2100 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2101 /// 2102 /// Each enumeration represents a particular CPU supported by Clang. These 2103 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2104 enum CPUKind { 2105 CK_Generic, 2106 2107 /// \name i386 2108 /// i386-generation processors. 2109 //@{ 2110 CK_i386, 2111 //@} 2112 2113 /// \name i486 2114 /// i486-generation processors. 2115 //@{ 2116 CK_i486, 2117 CK_WinChipC6, 2118 CK_WinChip2, 2119 CK_C3, 2120 //@} 2121 2122 /// \name i586 2123 /// i586-generation processors, P5 microarchitecture based. 2124 //@{ 2125 CK_i586, 2126 CK_Pentium, 2127 CK_PentiumMMX, 2128 //@} 2129 2130 /// \name i686 2131 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2132 //@{ 2133 CK_i686, 2134 CK_PentiumPro, 2135 CK_Pentium2, 2136 CK_Pentium3, 2137 CK_Pentium3M, 2138 CK_PentiumM, 2139 CK_C3_2, 2140 2141 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2142 /// Clang however has some logic to suport this. 2143 // FIXME: Warn, deprecate, and potentially remove this. 2144 CK_Yonah, 2145 //@} 2146 2147 /// \name Netburst 2148 /// Netburst microarchitecture based processors. 2149 //@{ 2150 CK_Pentium4, 2151 CK_Pentium4M, 2152 CK_Prescott, 2153 CK_Nocona, 2154 //@} 2155 2156 /// \name Core 2157 /// Core microarchitecture based processors. 2158 //@{ 2159 CK_Core2, 2160 2161 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2162 /// codename which GCC no longer accepts as an option to -march, but Clang 2163 /// has some logic for recognizing it. 2164 // FIXME: Warn, deprecate, and potentially remove this. 2165 CK_Penryn, 2166 //@} 2167 2168 /// \name Atom 2169 /// Atom processors 2170 //@{ 2171 CK_Bonnell, 2172 CK_Silvermont, 2173 //@} 2174 2175 /// \name Nehalem 2176 /// Nehalem microarchitecture based processors. 2177 CK_Nehalem, 2178 2179 /// \name Westmere 2180 /// Westmere microarchitecture based processors. 2181 CK_Westmere, 2182 2183 /// \name Sandy Bridge 2184 /// Sandy Bridge microarchitecture based processors. 2185 CK_SandyBridge, 2186 2187 /// \name Ivy Bridge 2188 /// Ivy Bridge microarchitecture based processors. 2189 CK_IvyBridge, 2190 2191 /// \name Haswell 2192 /// Haswell microarchitecture based processors. 2193 CK_Haswell, 2194 2195 /// \name Broadwell 2196 /// Broadwell microarchitecture based processors. 2197 CK_Broadwell, 2198 2199 /// \name Skylake 2200 /// Skylake microarchitecture based processors. 2201 CK_Skylake, 2202 2203 /// \name Knights Landing 2204 /// Knights Landing processor. 2205 CK_KNL, 2206 2207 /// \name K6 2208 /// K6 architecture processors. 2209 //@{ 2210 CK_K6, 2211 CK_K6_2, 2212 CK_K6_3, 2213 //@} 2214 2215 /// \name K7 2216 /// K7 architecture processors. 2217 //@{ 2218 CK_Athlon, 2219 CK_AthlonThunderbird, 2220 CK_Athlon4, 2221 CK_AthlonXP, 2222 CK_AthlonMP, 2223 //@} 2224 2225 /// \name K8 2226 /// K8 architecture processors. 2227 //@{ 2228 CK_Athlon64, 2229 CK_Athlon64SSE3, 2230 CK_AthlonFX, 2231 CK_K8, 2232 CK_K8SSE3, 2233 CK_Opteron, 2234 CK_OpteronSSE3, 2235 CK_AMDFAM10, 2236 //@} 2237 2238 /// \name Bobcat 2239 /// Bobcat architecture processors. 2240 //@{ 2241 CK_BTVER1, 2242 CK_BTVER2, 2243 //@} 2244 2245 /// \name Bulldozer 2246 /// Bulldozer architecture processors. 2247 //@{ 2248 CK_BDVER1, 2249 CK_BDVER2, 2250 CK_BDVER3, 2251 CK_BDVER4, 2252 //@} 2253 2254 /// This specification is deprecated and will be removed in the future. 2255 /// Users should prefer \see CK_K8. 2256 // FIXME: Warn on this when the CPU is set to it. 2257 //@{ 2258 CK_x86_64, 2259 //@} 2260 2261 /// \name Geode 2262 /// Geode processors. 2263 //@{ 2264 CK_Geode 2265 //@} 2266 } CPU; 2267 2268 CPUKind getCPUKind(StringRef CPU) const { 2269 return llvm::StringSwitch<CPUKind>(CPU) 2270 .Case("i386", CK_i386) 2271 .Case("i486", CK_i486) 2272 .Case("winchip-c6", CK_WinChipC6) 2273 .Case("winchip2", CK_WinChip2) 2274 .Case("c3", CK_C3) 2275 .Case("i586", CK_i586) 2276 .Case("pentium", CK_Pentium) 2277 .Case("pentium-mmx", CK_PentiumMMX) 2278 .Case("i686", CK_i686) 2279 .Case("pentiumpro", CK_PentiumPro) 2280 .Case("pentium2", CK_Pentium2) 2281 .Case("pentium3", CK_Pentium3) 2282 .Case("pentium3m", CK_Pentium3M) 2283 .Case("pentium-m", CK_PentiumM) 2284 .Case("c3-2", CK_C3_2) 2285 .Case("yonah", CK_Yonah) 2286 .Case("pentium4", CK_Pentium4) 2287 .Case("pentium4m", CK_Pentium4M) 2288 .Case("prescott", CK_Prescott) 2289 .Case("nocona", CK_Nocona) 2290 .Case("core2", CK_Core2) 2291 .Case("penryn", CK_Penryn) 2292 .Case("bonnell", CK_Bonnell) 2293 .Case("atom", CK_Bonnell) // Legacy name. 2294 .Case("silvermont", CK_Silvermont) 2295 .Case("slm", CK_Silvermont) // Legacy name. 2296 .Case("nehalem", CK_Nehalem) 2297 .Case("corei7", CK_Nehalem) // Legacy name. 2298 .Case("westmere", CK_Westmere) 2299 .Case("sandybridge", CK_SandyBridge) 2300 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2301 .Case("ivybridge", CK_IvyBridge) 2302 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2303 .Case("haswell", CK_Haswell) 2304 .Case("core-avx2", CK_Haswell) // Legacy name. 2305 .Case("broadwell", CK_Broadwell) 2306 .Case("skylake", CK_Skylake) 2307 .Case("skx", CK_Skylake) // Legacy name. 2308 .Case("knl", CK_KNL) 2309 .Case("k6", CK_K6) 2310 .Case("k6-2", CK_K6_2) 2311 .Case("k6-3", CK_K6_3) 2312 .Case("athlon", CK_Athlon) 2313 .Case("athlon-tbird", CK_AthlonThunderbird) 2314 .Case("athlon-4", CK_Athlon4) 2315 .Case("athlon-xp", CK_AthlonXP) 2316 .Case("athlon-mp", CK_AthlonMP) 2317 .Case("athlon64", CK_Athlon64) 2318 .Case("athlon64-sse3", CK_Athlon64SSE3) 2319 .Case("athlon-fx", CK_AthlonFX) 2320 .Case("k8", CK_K8) 2321 .Case("k8-sse3", CK_K8SSE3) 2322 .Case("opteron", CK_Opteron) 2323 .Case("opteron-sse3", CK_OpteronSSE3) 2324 .Case("barcelona", CK_AMDFAM10) 2325 .Case("amdfam10", CK_AMDFAM10) 2326 .Case("btver1", CK_BTVER1) 2327 .Case("btver2", CK_BTVER2) 2328 .Case("bdver1", CK_BDVER1) 2329 .Case("bdver2", CK_BDVER2) 2330 .Case("bdver3", CK_BDVER3) 2331 .Case("bdver4", CK_BDVER4) 2332 .Case("x86-64", CK_x86_64) 2333 .Case("geode", CK_Geode) 2334 .Default(CK_Generic); 2335 } 2336 2337 enum FPMathKind { 2338 FP_Default, 2339 FP_SSE, 2340 FP_387 2341 } FPMath; 2342 2343 public: 2344 X86TargetInfo(const llvm::Triple &Triple) 2345 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2346 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2347 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2348 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2349 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2350 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2351 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2352 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2353 BigEndian = false; 2354 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2355 } 2356 unsigned getFloatEvalMethod() const override { 2357 // X87 evaluates with 80 bits "long double" precision. 2358 return SSELevel == NoSSE ? 2 : 0; 2359 } 2360 void getTargetBuiltins(const Builtin::Info *&Records, 2361 unsigned &NumRecords) const override { 2362 Records = BuiltinInfo; 2363 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2364 } 2365 void getGCCRegNames(const char * const *&Names, 2366 unsigned &NumNames) const override { 2367 Names = GCCRegNames; 2368 NumNames = llvm::array_lengthof(GCCRegNames); 2369 } 2370 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2371 unsigned &NumAliases) const override { 2372 Aliases = nullptr; 2373 NumAliases = 0; 2374 } 2375 void getGCCAddlRegNames(const AddlRegName *&Names, 2376 unsigned &NumNames) const override { 2377 Names = AddlRegNames; 2378 NumNames = llvm::array_lengthof(AddlRegNames); 2379 } 2380 bool validateCpuSupports(StringRef Name) const override; 2381 bool validateAsmConstraint(const char *&Name, 2382 TargetInfo::ConstraintInfo &info) const override; 2383 2384 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2385 2386 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2387 2388 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2389 2390 std::string convertConstraint(const char *&Constraint) const override; 2391 const char *getClobbers() const override { 2392 return "~{dirflag},~{fpsr},~{flags}"; 2393 } 2394 void getTargetDefines(const LangOptions &Opts, 2395 MacroBuilder &Builder) const override; 2396 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2397 bool Enabled); 2398 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2399 bool Enabled); 2400 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2401 bool Enabled); 2402 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2403 StringRef Name, bool Enabled) const override { 2404 setFeatureEnabledImpl(Features, Name, Enabled); 2405 } 2406 // This exists purely to cut down on the number of virtual calls in 2407 // initFeatureMap which calls this repeatedly. 2408 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2409 StringRef Name, bool Enabled); 2410 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2411 StringRef CPU, 2412 std::vector<std::string> &FeaturesVec) const override; 2413 bool hasFeature(StringRef Feature) const override; 2414 bool handleTargetFeatures(std::vector<std::string> &Features, 2415 DiagnosticsEngine &Diags) override; 2416 StringRef getABI() const override { 2417 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2418 return "avx512"; 2419 else if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2420 return "avx"; 2421 else if (getTriple().getArch() == llvm::Triple::x86 && 2422 MMX3DNowLevel == NoMMX3DNow) 2423 return "no-mmx"; 2424 return ""; 2425 } 2426 bool setCPU(const std::string &Name) override { 2427 CPU = getCPUKind(Name); 2428 2429 // Perform any per-CPU checks necessary to determine if this CPU is 2430 // acceptable. 2431 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2432 // invalid without explaining *why*. 2433 switch (CPU) { 2434 case CK_Generic: 2435 // No processor selected! 2436 return false; 2437 2438 case CK_i386: 2439 case CK_i486: 2440 case CK_WinChipC6: 2441 case CK_WinChip2: 2442 case CK_C3: 2443 case CK_i586: 2444 case CK_Pentium: 2445 case CK_PentiumMMX: 2446 case CK_i686: 2447 case CK_PentiumPro: 2448 case CK_Pentium2: 2449 case CK_Pentium3: 2450 case CK_Pentium3M: 2451 case CK_PentiumM: 2452 case CK_Yonah: 2453 case CK_C3_2: 2454 case CK_Pentium4: 2455 case CK_Pentium4M: 2456 case CK_Prescott: 2457 case CK_K6: 2458 case CK_K6_2: 2459 case CK_K6_3: 2460 case CK_Athlon: 2461 case CK_AthlonThunderbird: 2462 case CK_Athlon4: 2463 case CK_AthlonXP: 2464 case CK_AthlonMP: 2465 case CK_Geode: 2466 // Only accept certain architectures when compiling in 32-bit mode. 2467 if (getTriple().getArch() != llvm::Triple::x86) 2468 return false; 2469 2470 // Fallthrough 2471 case CK_Nocona: 2472 case CK_Core2: 2473 case CK_Penryn: 2474 case CK_Bonnell: 2475 case CK_Silvermont: 2476 case CK_Nehalem: 2477 case CK_Westmere: 2478 case CK_SandyBridge: 2479 case CK_IvyBridge: 2480 case CK_Haswell: 2481 case CK_Broadwell: 2482 case CK_Skylake: 2483 case CK_KNL: 2484 case CK_Athlon64: 2485 case CK_Athlon64SSE3: 2486 case CK_AthlonFX: 2487 case CK_K8: 2488 case CK_K8SSE3: 2489 case CK_Opteron: 2490 case CK_OpteronSSE3: 2491 case CK_AMDFAM10: 2492 case CK_BTVER1: 2493 case CK_BTVER2: 2494 case CK_BDVER1: 2495 case CK_BDVER2: 2496 case CK_BDVER3: 2497 case CK_BDVER4: 2498 case CK_x86_64: 2499 return true; 2500 } 2501 llvm_unreachable("Unhandled CPU kind"); 2502 } 2503 2504 bool setFPMath(StringRef Name) override; 2505 2506 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2507 // We accept all non-ARM calling conventions 2508 return (CC == CC_X86ThisCall || 2509 CC == CC_X86FastCall || 2510 CC == CC_X86StdCall || 2511 CC == CC_X86VectorCall || 2512 CC == CC_C || 2513 CC == CC_X86Pascal || 2514 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2515 } 2516 2517 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2518 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2519 } 2520 2521 bool hasSjLjLowering() const override { 2522 return true; 2523 } 2524 }; 2525 2526 bool X86TargetInfo::setFPMath(StringRef Name) { 2527 if (Name == "387") { 2528 FPMath = FP_387; 2529 return true; 2530 } 2531 if (Name == "sse") { 2532 FPMath = FP_SSE; 2533 return true; 2534 } 2535 return false; 2536 } 2537 2538 bool X86TargetInfo::initFeatureMap( 2539 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2540 std::vector<std::string> &FeaturesVec) const { 2541 // FIXME: This *really* should not be here. 2542 // X86_64 always has SSE2. 2543 if (getTriple().getArch() == llvm::Triple::x86_64) 2544 setFeatureEnabledImpl(Features, "sse2", true); 2545 2546 switch (getCPUKind(CPU)) { 2547 case CK_Generic: 2548 case CK_i386: 2549 case CK_i486: 2550 case CK_i586: 2551 case CK_Pentium: 2552 case CK_i686: 2553 case CK_PentiumPro: 2554 break; 2555 case CK_PentiumMMX: 2556 case CK_Pentium2: 2557 case CK_K6: 2558 case CK_WinChipC6: 2559 setFeatureEnabledImpl(Features, "mmx", true); 2560 break; 2561 case CK_Pentium3: 2562 case CK_Pentium3M: 2563 case CK_C3_2: 2564 setFeatureEnabledImpl(Features, "sse", true); 2565 break; 2566 case CK_PentiumM: 2567 case CK_Pentium4: 2568 case CK_Pentium4M: 2569 case CK_x86_64: 2570 setFeatureEnabledImpl(Features, "sse2", true); 2571 break; 2572 case CK_Yonah: 2573 case CK_Prescott: 2574 case CK_Nocona: 2575 setFeatureEnabledImpl(Features, "sse3", true); 2576 setFeatureEnabledImpl(Features, "cx16", true); 2577 break; 2578 case CK_Core2: 2579 case CK_Bonnell: 2580 setFeatureEnabledImpl(Features, "ssse3", true); 2581 setFeatureEnabledImpl(Features, "cx16", true); 2582 break; 2583 case CK_Penryn: 2584 setFeatureEnabledImpl(Features, "sse4.1", true); 2585 setFeatureEnabledImpl(Features, "cx16", true); 2586 break; 2587 case CK_Skylake: 2588 setFeatureEnabledImpl(Features, "avx512f", true); 2589 setFeatureEnabledImpl(Features, "avx512cd", true); 2590 setFeatureEnabledImpl(Features, "avx512dq", true); 2591 setFeatureEnabledImpl(Features, "avx512bw", true); 2592 setFeatureEnabledImpl(Features, "avx512vl", true); 2593 // FALLTHROUGH 2594 case CK_Broadwell: 2595 setFeatureEnabledImpl(Features, "rdseed", true); 2596 setFeatureEnabledImpl(Features, "adx", true); 2597 // FALLTHROUGH 2598 case CK_Haswell: 2599 setFeatureEnabledImpl(Features, "avx2", true); 2600 setFeatureEnabledImpl(Features, "lzcnt", true); 2601 setFeatureEnabledImpl(Features, "bmi", true); 2602 setFeatureEnabledImpl(Features, "bmi2", true); 2603 setFeatureEnabledImpl(Features, "rtm", true); 2604 setFeatureEnabledImpl(Features, "fma", true); 2605 // FALLTHROUGH 2606 case CK_IvyBridge: 2607 setFeatureEnabledImpl(Features, "rdrnd", true); 2608 setFeatureEnabledImpl(Features, "f16c", true); 2609 setFeatureEnabledImpl(Features, "fsgsbase", true); 2610 // FALLTHROUGH 2611 case CK_SandyBridge: 2612 setFeatureEnabledImpl(Features, "avx", true); 2613 // FALLTHROUGH 2614 case CK_Westmere: 2615 case CK_Silvermont: 2616 setFeatureEnabledImpl(Features, "aes", true); 2617 setFeatureEnabledImpl(Features, "pclmul", true); 2618 // FALLTHROUGH 2619 case CK_Nehalem: 2620 setFeatureEnabledImpl(Features, "sse4.2", true); 2621 setFeatureEnabledImpl(Features, "cx16", true); 2622 break; 2623 case CK_KNL: 2624 setFeatureEnabledImpl(Features, "avx512f", true); 2625 setFeatureEnabledImpl(Features, "avx512cd", true); 2626 setFeatureEnabledImpl(Features, "avx512er", true); 2627 setFeatureEnabledImpl(Features, "avx512pf", true); 2628 setFeatureEnabledImpl(Features, "rdseed", true); 2629 setFeatureEnabledImpl(Features, "adx", true); 2630 setFeatureEnabledImpl(Features, "lzcnt", true); 2631 setFeatureEnabledImpl(Features, "bmi", true); 2632 setFeatureEnabledImpl(Features, "bmi2", true); 2633 setFeatureEnabledImpl(Features, "rtm", true); 2634 setFeatureEnabledImpl(Features, "fma", true); 2635 setFeatureEnabledImpl(Features, "rdrnd", true); 2636 setFeatureEnabledImpl(Features, "f16c", true); 2637 setFeatureEnabledImpl(Features, "fsgsbase", true); 2638 setFeatureEnabledImpl(Features, "aes", true); 2639 setFeatureEnabledImpl(Features, "pclmul", true); 2640 setFeatureEnabledImpl(Features, "cx16", true); 2641 break; 2642 case CK_K6_2: 2643 case CK_K6_3: 2644 case CK_WinChip2: 2645 case CK_C3: 2646 setFeatureEnabledImpl(Features, "3dnow", true); 2647 break; 2648 case CK_Athlon: 2649 case CK_AthlonThunderbird: 2650 case CK_Geode: 2651 setFeatureEnabledImpl(Features, "3dnowa", true); 2652 break; 2653 case CK_Athlon4: 2654 case CK_AthlonXP: 2655 case CK_AthlonMP: 2656 setFeatureEnabledImpl(Features, "sse", true); 2657 setFeatureEnabledImpl(Features, "3dnowa", true); 2658 break; 2659 case CK_K8: 2660 case CK_Opteron: 2661 case CK_Athlon64: 2662 case CK_AthlonFX: 2663 setFeatureEnabledImpl(Features, "sse2", true); 2664 setFeatureEnabledImpl(Features, "3dnowa", true); 2665 break; 2666 case CK_AMDFAM10: 2667 setFeatureEnabledImpl(Features, "sse4a", true); 2668 setFeatureEnabledImpl(Features, "lzcnt", true); 2669 setFeatureEnabledImpl(Features, "popcnt", true); 2670 // FALLTHROUGH 2671 case CK_K8SSE3: 2672 case CK_OpteronSSE3: 2673 case CK_Athlon64SSE3: 2674 setFeatureEnabledImpl(Features, "sse3", true); 2675 setFeatureEnabledImpl(Features, "3dnowa", true); 2676 break; 2677 case CK_BTVER2: 2678 setFeatureEnabledImpl(Features, "avx", true); 2679 setFeatureEnabledImpl(Features, "aes", true); 2680 setFeatureEnabledImpl(Features, "pclmul", true); 2681 setFeatureEnabledImpl(Features, "bmi", true); 2682 setFeatureEnabledImpl(Features, "f16c", true); 2683 // FALLTHROUGH 2684 case CK_BTVER1: 2685 setFeatureEnabledImpl(Features, "ssse3", true); 2686 setFeatureEnabledImpl(Features, "sse4a", true); 2687 setFeatureEnabledImpl(Features, "lzcnt", true); 2688 setFeatureEnabledImpl(Features, "popcnt", true); 2689 setFeatureEnabledImpl(Features, "prfchw", true); 2690 setFeatureEnabledImpl(Features, "cx16", true); 2691 break; 2692 case CK_BDVER4: 2693 setFeatureEnabledImpl(Features, "avx2", true); 2694 setFeatureEnabledImpl(Features, "bmi2", true); 2695 // FALLTHROUGH 2696 case CK_BDVER3: 2697 setFeatureEnabledImpl(Features, "fsgsbase", true); 2698 // FALLTHROUGH 2699 case CK_BDVER2: 2700 setFeatureEnabledImpl(Features, "bmi", true); 2701 setFeatureEnabledImpl(Features, "fma", true); 2702 setFeatureEnabledImpl(Features, "f16c", true); 2703 setFeatureEnabledImpl(Features, "tbm", true); 2704 // FALLTHROUGH 2705 case CK_BDVER1: 2706 // xop implies avx, sse4a and fma4. 2707 setFeatureEnabledImpl(Features, "xop", true); 2708 setFeatureEnabledImpl(Features, "lzcnt", true); 2709 setFeatureEnabledImpl(Features, "aes", true); 2710 setFeatureEnabledImpl(Features, "pclmul", true); 2711 setFeatureEnabledImpl(Features, "prfchw", true); 2712 setFeatureEnabledImpl(Features, "cx16", true); 2713 break; 2714 } 2715 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 2716 } 2717 2718 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2719 X86SSEEnum Level, bool Enabled) { 2720 if (Enabled) { 2721 switch (Level) { 2722 case AVX512F: 2723 Features["avx512f"] = true; 2724 case AVX2: 2725 Features["avx2"] = true; 2726 case AVX: 2727 Features["avx"] = true; 2728 case SSE42: 2729 Features["sse4.2"] = true; 2730 case SSE41: 2731 Features["sse4.1"] = true; 2732 case SSSE3: 2733 Features["ssse3"] = true; 2734 case SSE3: 2735 Features["sse3"] = true; 2736 case SSE2: 2737 Features["sse2"] = true; 2738 case SSE1: 2739 Features["sse"] = true; 2740 case NoSSE: 2741 break; 2742 } 2743 return; 2744 } 2745 2746 switch (Level) { 2747 case NoSSE: 2748 case SSE1: 2749 Features["sse"] = false; 2750 case SSE2: 2751 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2752 Features["sha"] = false; 2753 case SSE3: 2754 Features["sse3"] = false; 2755 setXOPLevel(Features, NoXOP, false); 2756 case SSSE3: 2757 Features["ssse3"] = false; 2758 case SSE41: 2759 Features["sse4.1"] = false; 2760 case SSE42: 2761 Features["sse4.2"] = false; 2762 case AVX: 2763 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2764 setXOPLevel(Features, FMA4, false); 2765 case AVX2: 2766 Features["avx2"] = false; 2767 case AVX512F: 2768 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2769 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2770 Features["avx512vl"] = false; 2771 } 2772 } 2773 2774 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2775 MMX3DNowEnum Level, bool Enabled) { 2776 if (Enabled) { 2777 switch (Level) { 2778 case AMD3DNowAthlon: 2779 Features["3dnowa"] = true; 2780 case AMD3DNow: 2781 Features["3dnow"] = true; 2782 case MMX: 2783 Features["mmx"] = true; 2784 case NoMMX3DNow: 2785 break; 2786 } 2787 return; 2788 } 2789 2790 switch (Level) { 2791 case NoMMX3DNow: 2792 case MMX: 2793 Features["mmx"] = false; 2794 case AMD3DNow: 2795 Features["3dnow"] = false; 2796 case AMD3DNowAthlon: 2797 Features["3dnowa"] = false; 2798 } 2799 } 2800 2801 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2802 bool Enabled) { 2803 if (Enabled) { 2804 switch (Level) { 2805 case XOP: 2806 Features["xop"] = true; 2807 case FMA4: 2808 Features["fma4"] = true; 2809 setSSELevel(Features, AVX, true); 2810 case SSE4A: 2811 Features["sse4a"] = true; 2812 setSSELevel(Features, SSE3, true); 2813 case NoXOP: 2814 break; 2815 } 2816 return; 2817 } 2818 2819 switch (Level) { 2820 case NoXOP: 2821 case SSE4A: 2822 Features["sse4a"] = false; 2823 case FMA4: 2824 Features["fma4"] = false; 2825 case XOP: 2826 Features["xop"] = false; 2827 } 2828 } 2829 2830 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2831 StringRef Name, bool Enabled) { 2832 // This is a bit of a hack to deal with the sse4 target feature when used 2833 // as part of the target attribute. We handle sse4 correctly everywhere 2834 // else. See below for more information on how we handle the sse4 options. 2835 if (Name != "sse4") 2836 Features[Name] = Enabled; 2837 2838 if (Name == "mmx") { 2839 setMMXLevel(Features, MMX, Enabled); 2840 } else if (Name == "sse") { 2841 setSSELevel(Features, SSE1, Enabled); 2842 } else if (Name == "sse2") { 2843 setSSELevel(Features, SSE2, Enabled); 2844 } else if (Name == "sse3") { 2845 setSSELevel(Features, SSE3, Enabled); 2846 } else if (Name == "ssse3") { 2847 setSSELevel(Features, SSSE3, Enabled); 2848 } else if (Name == "sse4.2") { 2849 setSSELevel(Features, SSE42, Enabled); 2850 } else if (Name == "sse4.1") { 2851 setSSELevel(Features, SSE41, Enabled); 2852 } else if (Name == "3dnow") { 2853 setMMXLevel(Features, AMD3DNow, Enabled); 2854 } else if (Name == "3dnowa") { 2855 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2856 } else if (Name == "aes") { 2857 if (Enabled) 2858 setSSELevel(Features, SSE2, Enabled); 2859 } else if (Name == "pclmul") { 2860 if (Enabled) 2861 setSSELevel(Features, SSE2, Enabled); 2862 } else if (Name == "avx") { 2863 setSSELevel(Features, AVX, Enabled); 2864 } else if (Name == "avx2") { 2865 setSSELevel(Features, AVX2, Enabled); 2866 } else if (Name == "avx512f") { 2867 setSSELevel(Features, AVX512F, Enabled); 2868 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2869 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2870 if (Enabled) 2871 setSSELevel(Features, AVX512F, Enabled); 2872 } else if (Name == "fma") { 2873 if (Enabled) 2874 setSSELevel(Features, AVX, Enabled); 2875 } else if (Name == "fma4") { 2876 setXOPLevel(Features, FMA4, Enabled); 2877 } else if (Name == "xop") { 2878 setXOPLevel(Features, XOP, Enabled); 2879 } else if (Name == "sse4a") { 2880 setXOPLevel(Features, SSE4A, Enabled); 2881 } else if (Name == "f16c") { 2882 if (Enabled) 2883 setSSELevel(Features, AVX, Enabled); 2884 } else if (Name == "sha") { 2885 if (Enabled) 2886 setSSELevel(Features, SSE2, Enabled); 2887 } else if (Name == "sse4") { 2888 // We can get here via the __target__ attribute since that's not controlled 2889 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2890 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2891 // disabled. 2892 if (Enabled) 2893 setSSELevel(Features, SSE42, Enabled); 2894 else 2895 setSSELevel(Features, SSE41, Enabled); 2896 } 2897 } 2898 2899 /// handleTargetFeatures - Perform initialization based on the user 2900 /// configured set of features. 2901 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2902 DiagnosticsEngine &Diags) { 2903 for (const auto &Feature : Features) { 2904 if (Feature[0] != '+') 2905 continue; 2906 2907 if (Feature == "+aes") { 2908 HasAES = true; 2909 } else if (Feature == "+pclmul") { 2910 HasPCLMUL = true; 2911 } else if (Feature == "+lzcnt") { 2912 HasLZCNT = true; 2913 } else if (Feature == "+rdrnd") { 2914 HasRDRND = true; 2915 } else if (Feature == "+fsgsbase") { 2916 HasFSGSBASE = true; 2917 } else if (Feature == "+bmi") { 2918 HasBMI = true; 2919 } else if (Feature == "+bmi2") { 2920 HasBMI2 = true; 2921 } else if (Feature == "+popcnt") { 2922 HasPOPCNT = true; 2923 } else if (Feature == "+rtm") { 2924 HasRTM = true; 2925 } else if (Feature == "+prfchw") { 2926 HasPRFCHW = true; 2927 } else if (Feature == "+rdseed") { 2928 HasRDSEED = true; 2929 } else if (Feature == "+adx") { 2930 HasADX = true; 2931 } else if (Feature == "+tbm") { 2932 HasTBM = true; 2933 } else if (Feature == "+fma") { 2934 HasFMA = true; 2935 } else if (Feature == "+f16c") { 2936 HasF16C = true; 2937 } else if (Feature == "+avx512cd") { 2938 HasAVX512CD = true; 2939 } else if (Feature == "+avx512er") { 2940 HasAVX512ER = true; 2941 } else if (Feature == "+avx512pf") { 2942 HasAVX512PF = true; 2943 } else if (Feature == "+avx512dq") { 2944 HasAVX512DQ = true; 2945 } else if (Feature == "+avx512bw") { 2946 HasAVX512BW = true; 2947 } else if (Feature == "+avx512vl") { 2948 HasAVX512VL = true; 2949 } else if (Feature == "+sha") { 2950 HasSHA = true; 2951 } else if (Feature == "+cx16") { 2952 HasCX16 = true; 2953 } 2954 2955 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2956 .Case("+avx512f", AVX512F) 2957 .Case("+avx2", AVX2) 2958 .Case("+avx", AVX) 2959 .Case("+sse4.2", SSE42) 2960 .Case("+sse4.1", SSE41) 2961 .Case("+ssse3", SSSE3) 2962 .Case("+sse3", SSE3) 2963 .Case("+sse2", SSE2) 2964 .Case("+sse", SSE1) 2965 .Default(NoSSE); 2966 SSELevel = std::max(SSELevel, Level); 2967 2968 MMX3DNowEnum ThreeDNowLevel = 2969 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2970 .Case("+3dnowa", AMD3DNowAthlon) 2971 .Case("+3dnow", AMD3DNow) 2972 .Case("+mmx", MMX) 2973 .Default(NoMMX3DNow); 2974 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2975 2976 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2977 .Case("+xop", XOP) 2978 .Case("+fma4", FMA4) 2979 .Case("+sse4a", SSE4A) 2980 .Default(NoXOP); 2981 XOPLevel = std::max(XOPLevel, XLevel); 2982 } 2983 2984 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2985 // Can't do this earlier because we need to be able to explicitly enable 2986 // popcnt and still disable sse4.2. 2987 if (!HasPOPCNT && SSELevel >= SSE42 && 2988 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2989 HasPOPCNT = true; 2990 Features.push_back("+popcnt"); 2991 } 2992 2993 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2994 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2995 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2996 HasPRFCHW = true; 2997 Features.push_back("+prfchw"); 2998 } 2999 3000 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3001 // matches the selected sse level. 3002 if (FPMath == FP_SSE && SSELevel < SSE1) { 3003 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 3004 return false; 3005 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 3006 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 3007 return false; 3008 } 3009 3010 // Don't tell the backend if we're turning off mmx; it will end up disabling 3011 // SSE, which we don't want. 3012 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3013 // then enable MMX. 3014 std::vector<std::string>::iterator it; 3015 it = std::find(Features.begin(), Features.end(), "-mmx"); 3016 if (it != Features.end()) 3017 Features.erase(it); 3018 else if (SSELevel > NoSSE) 3019 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 3020 3021 SimdDefaultAlign = 3022 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3023 return true; 3024 } 3025 3026 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3027 /// definitions for this particular subtarget. 3028 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3029 MacroBuilder &Builder) const { 3030 // Target identification. 3031 if (getTriple().getArch() == llvm::Triple::x86_64) { 3032 Builder.defineMacro("__amd64__"); 3033 Builder.defineMacro("__amd64"); 3034 Builder.defineMacro("__x86_64"); 3035 Builder.defineMacro("__x86_64__"); 3036 if (getTriple().getArchName() == "x86_64h") { 3037 Builder.defineMacro("__x86_64h"); 3038 Builder.defineMacro("__x86_64h__"); 3039 } 3040 } else { 3041 DefineStd(Builder, "i386", Opts); 3042 } 3043 3044 // Subtarget options. 3045 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3046 // truly should be based on -mtune options. 3047 switch (CPU) { 3048 case CK_Generic: 3049 break; 3050 case CK_i386: 3051 // The rest are coming from the i386 define above. 3052 Builder.defineMacro("__tune_i386__"); 3053 break; 3054 case CK_i486: 3055 case CK_WinChipC6: 3056 case CK_WinChip2: 3057 case CK_C3: 3058 defineCPUMacros(Builder, "i486"); 3059 break; 3060 case CK_PentiumMMX: 3061 Builder.defineMacro("__pentium_mmx__"); 3062 Builder.defineMacro("__tune_pentium_mmx__"); 3063 // Fallthrough 3064 case CK_i586: 3065 case CK_Pentium: 3066 defineCPUMacros(Builder, "i586"); 3067 defineCPUMacros(Builder, "pentium"); 3068 break; 3069 case CK_Pentium3: 3070 case CK_Pentium3M: 3071 case CK_PentiumM: 3072 Builder.defineMacro("__tune_pentium3__"); 3073 // Fallthrough 3074 case CK_Pentium2: 3075 case CK_C3_2: 3076 Builder.defineMacro("__tune_pentium2__"); 3077 // Fallthrough 3078 case CK_PentiumPro: 3079 Builder.defineMacro("__tune_i686__"); 3080 Builder.defineMacro("__tune_pentiumpro__"); 3081 // Fallthrough 3082 case CK_i686: 3083 Builder.defineMacro("__i686"); 3084 Builder.defineMacro("__i686__"); 3085 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3086 Builder.defineMacro("__pentiumpro"); 3087 Builder.defineMacro("__pentiumpro__"); 3088 break; 3089 case CK_Pentium4: 3090 case CK_Pentium4M: 3091 defineCPUMacros(Builder, "pentium4"); 3092 break; 3093 case CK_Yonah: 3094 case CK_Prescott: 3095 case CK_Nocona: 3096 defineCPUMacros(Builder, "nocona"); 3097 break; 3098 case CK_Core2: 3099 case CK_Penryn: 3100 defineCPUMacros(Builder, "core2"); 3101 break; 3102 case CK_Bonnell: 3103 defineCPUMacros(Builder, "atom"); 3104 break; 3105 case CK_Silvermont: 3106 defineCPUMacros(Builder, "slm"); 3107 break; 3108 case CK_Nehalem: 3109 case CK_Westmere: 3110 case CK_SandyBridge: 3111 case CK_IvyBridge: 3112 case CK_Haswell: 3113 case CK_Broadwell: 3114 // FIXME: Historically, we defined this legacy name, it would be nice to 3115 // remove it at some point. We've never exposed fine-grained names for 3116 // recent primary x86 CPUs, and we should keep it that way. 3117 defineCPUMacros(Builder, "corei7"); 3118 break; 3119 case CK_Skylake: 3120 // FIXME: Historically, we defined this legacy name, it would be nice to 3121 // remove it at some point. This is the only fine-grained CPU macro in the 3122 // main intel CPU line, and it would be better to not have these and force 3123 // people to use ISA macros. 3124 defineCPUMacros(Builder, "skx"); 3125 break; 3126 case CK_KNL: 3127 defineCPUMacros(Builder, "knl"); 3128 break; 3129 case CK_K6_2: 3130 Builder.defineMacro("__k6_2__"); 3131 Builder.defineMacro("__tune_k6_2__"); 3132 // Fallthrough 3133 case CK_K6_3: 3134 if (CPU != CK_K6_2) { // In case of fallthrough 3135 // FIXME: GCC may be enabling these in cases where some other k6 3136 // architecture is specified but -m3dnow is explicitly provided. The 3137 // exact semantics need to be determined and emulated here. 3138 Builder.defineMacro("__k6_3__"); 3139 Builder.defineMacro("__tune_k6_3__"); 3140 } 3141 // Fallthrough 3142 case CK_K6: 3143 defineCPUMacros(Builder, "k6"); 3144 break; 3145 case CK_Athlon: 3146 case CK_AthlonThunderbird: 3147 case CK_Athlon4: 3148 case CK_AthlonXP: 3149 case CK_AthlonMP: 3150 defineCPUMacros(Builder, "athlon"); 3151 if (SSELevel != NoSSE) { 3152 Builder.defineMacro("__athlon_sse__"); 3153 Builder.defineMacro("__tune_athlon_sse__"); 3154 } 3155 break; 3156 case CK_K8: 3157 case CK_K8SSE3: 3158 case CK_x86_64: 3159 case CK_Opteron: 3160 case CK_OpteronSSE3: 3161 case CK_Athlon64: 3162 case CK_Athlon64SSE3: 3163 case CK_AthlonFX: 3164 defineCPUMacros(Builder, "k8"); 3165 break; 3166 case CK_AMDFAM10: 3167 defineCPUMacros(Builder, "amdfam10"); 3168 break; 3169 case CK_BTVER1: 3170 defineCPUMacros(Builder, "btver1"); 3171 break; 3172 case CK_BTVER2: 3173 defineCPUMacros(Builder, "btver2"); 3174 break; 3175 case CK_BDVER1: 3176 defineCPUMacros(Builder, "bdver1"); 3177 break; 3178 case CK_BDVER2: 3179 defineCPUMacros(Builder, "bdver2"); 3180 break; 3181 case CK_BDVER3: 3182 defineCPUMacros(Builder, "bdver3"); 3183 break; 3184 case CK_BDVER4: 3185 defineCPUMacros(Builder, "bdver4"); 3186 break; 3187 case CK_Geode: 3188 defineCPUMacros(Builder, "geode"); 3189 break; 3190 } 3191 3192 // Target properties. 3193 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3194 3195 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3196 // functions in glibc header files that use FP Stack inline asm which the 3197 // backend can't deal with (PR879). 3198 Builder.defineMacro("__NO_MATH_INLINES"); 3199 3200 if (HasAES) 3201 Builder.defineMacro("__AES__"); 3202 3203 if (HasPCLMUL) 3204 Builder.defineMacro("__PCLMUL__"); 3205 3206 if (HasLZCNT) 3207 Builder.defineMacro("__LZCNT__"); 3208 3209 if (HasRDRND) 3210 Builder.defineMacro("__RDRND__"); 3211 3212 if (HasFSGSBASE) 3213 Builder.defineMacro("__FSGSBASE__"); 3214 3215 if (HasBMI) 3216 Builder.defineMacro("__BMI__"); 3217 3218 if (HasBMI2) 3219 Builder.defineMacro("__BMI2__"); 3220 3221 if (HasPOPCNT) 3222 Builder.defineMacro("__POPCNT__"); 3223 3224 if (HasRTM) 3225 Builder.defineMacro("__RTM__"); 3226 3227 if (HasPRFCHW) 3228 Builder.defineMacro("__PRFCHW__"); 3229 3230 if (HasRDSEED) 3231 Builder.defineMacro("__RDSEED__"); 3232 3233 if (HasADX) 3234 Builder.defineMacro("__ADX__"); 3235 3236 if (HasTBM) 3237 Builder.defineMacro("__TBM__"); 3238 3239 switch (XOPLevel) { 3240 case XOP: 3241 Builder.defineMacro("__XOP__"); 3242 case FMA4: 3243 Builder.defineMacro("__FMA4__"); 3244 case SSE4A: 3245 Builder.defineMacro("__SSE4A__"); 3246 case NoXOP: 3247 break; 3248 } 3249 3250 if (HasFMA) 3251 Builder.defineMacro("__FMA__"); 3252 3253 if (HasF16C) 3254 Builder.defineMacro("__F16C__"); 3255 3256 if (HasAVX512CD) 3257 Builder.defineMacro("__AVX512CD__"); 3258 if (HasAVX512ER) 3259 Builder.defineMacro("__AVX512ER__"); 3260 if (HasAVX512PF) 3261 Builder.defineMacro("__AVX512PF__"); 3262 if (HasAVX512DQ) 3263 Builder.defineMacro("__AVX512DQ__"); 3264 if (HasAVX512BW) 3265 Builder.defineMacro("__AVX512BW__"); 3266 if (HasAVX512VL) 3267 Builder.defineMacro("__AVX512VL__"); 3268 3269 if (HasSHA) 3270 Builder.defineMacro("__SHA__"); 3271 3272 if (HasCX16) 3273 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3274 3275 // Each case falls through to the previous one here. 3276 switch (SSELevel) { 3277 case AVX512F: 3278 Builder.defineMacro("__AVX512F__"); 3279 case AVX2: 3280 Builder.defineMacro("__AVX2__"); 3281 case AVX: 3282 Builder.defineMacro("__AVX__"); 3283 case SSE42: 3284 Builder.defineMacro("__SSE4_2__"); 3285 case SSE41: 3286 Builder.defineMacro("__SSE4_1__"); 3287 case SSSE3: 3288 Builder.defineMacro("__SSSE3__"); 3289 case SSE3: 3290 Builder.defineMacro("__SSE3__"); 3291 case SSE2: 3292 Builder.defineMacro("__SSE2__"); 3293 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3294 case SSE1: 3295 Builder.defineMacro("__SSE__"); 3296 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3297 case NoSSE: 3298 break; 3299 } 3300 3301 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3302 switch (SSELevel) { 3303 case AVX512F: 3304 case AVX2: 3305 case AVX: 3306 case SSE42: 3307 case SSE41: 3308 case SSSE3: 3309 case SSE3: 3310 case SSE2: 3311 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3312 break; 3313 case SSE1: 3314 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3315 break; 3316 default: 3317 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3318 } 3319 } 3320 3321 // Each case falls through to the previous one here. 3322 switch (MMX3DNowLevel) { 3323 case AMD3DNowAthlon: 3324 Builder.defineMacro("__3dNOW_A__"); 3325 case AMD3DNow: 3326 Builder.defineMacro("__3dNOW__"); 3327 case MMX: 3328 Builder.defineMacro("__MMX__"); 3329 case NoMMX3DNow: 3330 break; 3331 } 3332 3333 if (CPU >= CK_i486) { 3334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3335 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3336 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3337 } 3338 if (CPU >= CK_i586) 3339 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3340 } 3341 3342 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3343 return llvm::StringSwitch<bool>(Feature) 3344 .Case("aes", HasAES) 3345 .Case("avx", SSELevel >= AVX) 3346 .Case("avx2", SSELevel >= AVX2) 3347 .Case("avx512f", SSELevel >= AVX512F) 3348 .Case("avx512cd", HasAVX512CD) 3349 .Case("avx512er", HasAVX512ER) 3350 .Case("avx512pf", HasAVX512PF) 3351 .Case("avx512dq", HasAVX512DQ) 3352 .Case("avx512bw", HasAVX512BW) 3353 .Case("avx512vl", HasAVX512VL) 3354 .Case("bmi", HasBMI) 3355 .Case("bmi2", HasBMI2) 3356 .Case("cx16", HasCX16) 3357 .Case("f16c", HasF16C) 3358 .Case("fma", HasFMA) 3359 .Case("fma4", XOPLevel >= FMA4) 3360 .Case("fsgsbase", HasFSGSBASE) 3361 .Case("lzcnt", HasLZCNT) 3362 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3363 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3364 .Case("mmx", MMX3DNowLevel >= MMX) 3365 .Case("pclmul", HasPCLMUL) 3366 .Case("popcnt", HasPOPCNT) 3367 .Case("prfchw", HasPRFCHW) 3368 .Case("rdrnd", HasRDRND) 3369 .Case("rdseed", HasRDSEED) 3370 .Case("rtm", HasRTM) 3371 .Case("sha", HasSHA) 3372 .Case("sse", SSELevel >= SSE1) 3373 .Case("sse2", SSELevel >= SSE2) 3374 .Case("sse3", SSELevel >= SSE3) 3375 .Case("ssse3", SSELevel >= SSSE3) 3376 .Case("sse4.1", SSELevel >= SSE41) 3377 .Case("sse4.2", SSELevel >= SSE42) 3378 .Case("sse4a", XOPLevel >= SSE4A) 3379 .Case("tbm", HasTBM) 3380 .Case("x86", true) 3381 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3382 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3383 .Case("xop", XOPLevel >= XOP) 3384 .Default(false); 3385 } 3386 3387 // We can't use a generic validation scheme for the features accepted here 3388 // versus subtarget features accepted in the target attribute because the 3389 // bitfield structure that's initialized in the runtime only supports the 3390 // below currently rather than the full range of subtarget features. (See 3391 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3392 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3393 return llvm::StringSwitch<bool>(FeatureStr) 3394 .Case("cmov", true) 3395 .Case("mmx", true) 3396 .Case("popcnt", true) 3397 .Case("sse", true) 3398 .Case("sse2", true) 3399 .Case("sse3", true) 3400 .Case("sse4.1", true) 3401 .Case("sse4.2", true) 3402 .Case("avx", true) 3403 .Case("avx2", true) 3404 .Case("sse4a", true) 3405 .Case("fma4", true) 3406 .Case("xop", true) 3407 .Case("fma", true) 3408 .Case("avx512f", true) 3409 .Case("bmi", true) 3410 .Case("bmi2", true) 3411 .Default(false); 3412 } 3413 3414 bool 3415 X86TargetInfo::validateAsmConstraint(const char *&Name, 3416 TargetInfo::ConstraintInfo &Info) const { 3417 switch (*Name) { 3418 default: return false; 3419 // Constant constraints. 3420 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3421 // instructions. 3422 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3423 // x86_64 instructions. 3424 case 's': 3425 Info.setRequiresImmediate(); 3426 return true; 3427 case 'I': 3428 Info.setRequiresImmediate(0, 31); 3429 return true; 3430 case 'J': 3431 Info.setRequiresImmediate(0, 63); 3432 return true; 3433 case 'K': 3434 Info.setRequiresImmediate(-128, 127); 3435 return true; 3436 case 'L': 3437 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3438 return true; 3439 case 'M': 3440 Info.setRequiresImmediate(0, 3); 3441 return true; 3442 case 'N': 3443 Info.setRequiresImmediate(0, 255); 3444 return true; 3445 case 'O': 3446 Info.setRequiresImmediate(0, 127); 3447 return true; 3448 // Register constraints. 3449 case 'Y': // 'Y' is the first character for several 2-character constraints. 3450 // Shift the pointer to the second character of the constraint. 3451 Name++; 3452 switch (*Name) { 3453 default: 3454 return false; 3455 case '0': // First SSE register. 3456 case 't': // Any SSE register, when SSE2 is enabled. 3457 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3458 case 'm': // Any MMX register, when inter-unit moves enabled. 3459 Info.setAllowsRegister(); 3460 return true; 3461 } 3462 case 'f': // Any x87 floating point stack register. 3463 // Constraint 'f' cannot be used for output operands. 3464 if (Info.ConstraintStr[0] == '=') 3465 return false; 3466 Info.setAllowsRegister(); 3467 return true; 3468 case 'a': // eax. 3469 case 'b': // ebx. 3470 case 'c': // ecx. 3471 case 'd': // edx. 3472 case 'S': // esi. 3473 case 'D': // edi. 3474 case 'A': // edx:eax. 3475 case 't': // Top of floating point stack. 3476 case 'u': // Second from top of floating point stack. 3477 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3478 case 'y': // Any MMX register. 3479 case 'x': // Any SSE register. 3480 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3481 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3482 case 'l': // "Index" registers: any general register that can be used as an 3483 // index in a base+index memory access. 3484 Info.setAllowsRegister(); 3485 return true; 3486 // Floating point constant constraints. 3487 case 'C': // SSE floating point constant. 3488 case 'G': // x87 floating point constant. 3489 return true; 3490 } 3491 } 3492 3493 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3494 unsigned Size) const { 3495 // Strip off constraint modifiers. 3496 while (Constraint[0] == '=' || 3497 Constraint[0] == '+' || 3498 Constraint[0] == '&') 3499 Constraint = Constraint.substr(1); 3500 3501 return validateOperandSize(Constraint, Size); 3502 } 3503 3504 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3505 unsigned Size) const { 3506 return validateOperandSize(Constraint, Size); 3507 } 3508 3509 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3510 unsigned Size) const { 3511 switch (Constraint[0]) { 3512 default: break; 3513 case 'y': 3514 return Size <= 64; 3515 case 'f': 3516 case 't': 3517 case 'u': 3518 return Size <= 128; 3519 case 'x': 3520 if (SSELevel >= AVX512F) 3521 // 512-bit zmm registers can be used if target supports AVX512F. 3522 return Size <= 512U; 3523 else if (SSELevel >= AVX) 3524 // 256-bit ymm registers can be used if target supports AVX. 3525 return Size <= 256U; 3526 return Size <= 128U; 3527 case 'Y': 3528 // 'Y' is the first character for several 2-character constraints. 3529 switch (Constraint[1]) { 3530 default: break; 3531 case 'm': 3532 // 'Ym' is synonymous with 'y'. 3533 return Size <= 64; 3534 case 'i': 3535 case 't': 3536 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3537 if (SSELevel >= AVX512F) 3538 return Size <= 512U; 3539 else if (SSELevel >= AVX) 3540 return Size <= 256U; 3541 return SSELevel >= SSE2 && Size <= 128U; 3542 } 3543 3544 } 3545 3546 return true; 3547 } 3548 3549 std::string 3550 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3551 switch (*Constraint) { 3552 case 'a': return std::string("{ax}"); 3553 case 'b': return std::string("{bx}"); 3554 case 'c': return std::string("{cx}"); 3555 case 'd': return std::string("{dx}"); 3556 case 'S': return std::string("{si}"); 3557 case 'D': return std::string("{di}"); 3558 case 'p': // address 3559 return std::string("im"); 3560 case 't': // top of floating point stack. 3561 return std::string("{st}"); 3562 case 'u': // second from top of floating point stack. 3563 return std::string("{st(1)}"); // second from top of floating point stack. 3564 default: 3565 return std::string(1, *Constraint); 3566 } 3567 } 3568 3569 // X86-32 generic target 3570 class X86_32TargetInfo : public X86TargetInfo { 3571 public: 3572 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3573 DoubleAlign = LongLongAlign = 32; 3574 LongDoubleWidth = 96; 3575 LongDoubleAlign = 32; 3576 SuitableAlign = 128; 3577 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3578 SizeType = UnsignedInt; 3579 PtrDiffType = SignedInt; 3580 IntPtrType = SignedInt; 3581 RegParmMax = 3; 3582 3583 // Use fpret for all types. 3584 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3585 (1 << TargetInfo::Double) | 3586 (1 << TargetInfo::LongDouble)); 3587 3588 // x86-32 has atomics up to 8 bytes 3589 // FIXME: Check that we actually have cmpxchg8b before setting 3590 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3591 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3592 } 3593 BuiltinVaListKind getBuiltinVaListKind() const override { 3594 return TargetInfo::CharPtrBuiltinVaList; 3595 } 3596 3597 int getEHDataRegisterNumber(unsigned RegNo) const override { 3598 if (RegNo == 0) return 0; 3599 if (RegNo == 1) return 2; 3600 return -1; 3601 } 3602 bool validateOperandSize(StringRef Constraint, 3603 unsigned Size) const override { 3604 switch (Constraint[0]) { 3605 default: break; 3606 case 'R': 3607 case 'q': 3608 case 'Q': 3609 case 'a': 3610 case 'b': 3611 case 'c': 3612 case 'd': 3613 case 'S': 3614 case 'D': 3615 return Size <= 32; 3616 case 'A': 3617 return Size <= 64; 3618 } 3619 3620 return X86TargetInfo::validateOperandSize(Constraint, Size); 3621 } 3622 }; 3623 3624 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3625 public: 3626 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3627 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3628 3629 unsigned getFloatEvalMethod() const override { 3630 unsigned Major, Minor, Micro; 3631 getTriple().getOSVersion(Major, Minor, Micro); 3632 // New NetBSD uses the default rounding mode. 3633 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3634 return X86_32TargetInfo::getFloatEvalMethod(); 3635 // NetBSD before 6.99.26 defaults to "double" rounding. 3636 return 1; 3637 } 3638 }; 3639 3640 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3641 public: 3642 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3643 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3644 SizeType = UnsignedLong; 3645 IntPtrType = SignedLong; 3646 PtrDiffType = SignedLong; 3647 } 3648 }; 3649 3650 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3651 public: 3652 BitrigI386TargetInfo(const llvm::Triple &Triple) 3653 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3654 SizeType = UnsignedLong; 3655 IntPtrType = SignedLong; 3656 PtrDiffType = SignedLong; 3657 } 3658 }; 3659 3660 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3661 public: 3662 DarwinI386TargetInfo(const llvm::Triple &Triple) 3663 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3664 LongDoubleWidth = 128; 3665 LongDoubleAlign = 128; 3666 SuitableAlign = 128; 3667 SizeType = UnsignedLong; 3668 IntPtrType = SignedLong; 3669 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3670 HasAlignMac68kSupport = true; 3671 } 3672 3673 bool handleTargetFeatures(std::vector<std::string> &Features, 3674 DiagnosticsEngine &Diags) override { 3675 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3676 Diags)) 3677 return false; 3678 // We now know the features we have: we can decide how to align vectors. 3679 MaxVectorAlign = 3680 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3681 return true; 3682 } 3683 }; 3684 3685 // x86-32 Windows target 3686 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3687 public: 3688 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3689 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3690 WCharType = UnsignedShort; 3691 DoubleAlign = LongLongAlign = 64; 3692 bool IsWinCOFF = 3693 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3694 DataLayoutString = IsWinCOFF 3695 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3696 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3697 } 3698 void getTargetDefines(const LangOptions &Opts, 3699 MacroBuilder &Builder) const override { 3700 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3701 } 3702 }; 3703 3704 // x86-32 Windows Visual Studio target 3705 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3706 public: 3707 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3708 : WindowsX86_32TargetInfo(Triple) { 3709 LongDoubleWidth = LongDoubleAlign = 64; 3710 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3711 } 3712 void getTargetDefines(const LangOptions &Opts, 3713 MacroBuilder &Builder) const override { 3714 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3715 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3716 // The value of the following reflects processor type. 3717 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3718 // We lost the original triple, so we use the default. 3719 Builder.defineMacro("_M_IX86", "600"); 3720 } 3721 }; 3722 } // end anonymous namespace 3723 3724 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3725 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang supports 3726 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3727 // macro anyway for pre-processor compatibility. 3728 if (Opts.MicrosoftExt) 3729 Builder.defineMacro("__declspec", "__declspec"); 3730 else 3731 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3732 3733 if (!Opts.MicrosoftExt) { 3734 // Provide macros for all the calling convention keywords. Provide both 3735 // single and double underscore prefixed variants. These are available on 3736 // x64 as well as x86, even though they have no effect. 3737 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3738 for (const char *CC : CCs) { 3739 std::string GCCSpelling = "__attribute__((__"; 3740 GCCSpelling += CC; 3741 GCCSpelling += "__))"; 3742 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3743 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3744 } 3745 } 3746 } 3747 3748 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3749 Builder.defineMacro("__MSVCRT__"); 3750 Builder.defineMacro("__MINGW32__"); 3751 addCygMingDefines(Opts, Builder); 3752 } 3753 3754 namespace { 3755 // x86-32 MinGW target 3756 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3757 public: 3758 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3759 : WindowsX86_32TargetInfo(Triple) {} 3760 void getTargetDefines(const LangOptions &Opts, 3761 MacroBuilder &Builder) const override { 3762 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3763 DefineStd(Builder, "WIN32", Opts); 3764 DefineStd(Builder, "WINNT", Opts); 3765 Builder.defineMacro("_X86_"); 3766 addMinGWDefines(Opts, Builder); 3767 } 3768 }; 3769 3770 // x86-32 Cygwin target 3771 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3772 public: 3773 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3774 : X86_32TargetInfo(Triple) { 3775 TLSSupported = false; 3776 WCharType = UnsignedShort; 3777 DoubleAlign = LongLongAlign = 64; 3778 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3779 } 3780 void getTargetDefines(const LangOptions &Opts, 3781 MacroBuilder &Builder) const override { 3782 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3783 Builder.defineMacro("_X86_"); 3784 Builder.defineMacro("__CYGWIN__"); 3785 Builder.defineMacro("__CYGWIN32__"); 3786 addCygMingDefines(Opts, Builder); 3787 DefineStd(Builder, "unix", Opts); 3788 if (Opts.CPlusPlus) 3789 Builder.defineMacro("_GNU_SOURCE"); 3790 } 3791 }; 3792 3793 // x86-32 Haiku target 3794 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3795 public: 3796 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3797 SizeType = UnsignedLong; 3798 IntPtrType = SignedLong; 3799 PtrDiffType = SignedLong; 3800 ProcessIDType = SignedLong; 3801 this->UserLabelPrefix = ""; 3802 this->TLSSupported = false; 3803 } 3804 void getTargetDefines(const LangOptions &Opts, 3805 MacroBuilder &Builder) const override { 3806 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3807 Builder.defineMacro("__INTEL__"); 3808 Builder.defineMacro("__HAIKU__"); 3809 } 3810 }; 3811 3812 // RTEMS Target 3813 template<typename Target> 3814 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3815 protected: 3816 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3817 MacroBuilder &Builder) const override { 3818 // RTEMS defines; list based off of gcc output 3819 3820 Builder.defineMacro("__rtems__"); 3821 Builder.defineMacro("__ELF__"); 3822 } 3823 3824 public: 3825 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3826 this->UserLabelPrefix = ""; 3827 3828 switch (Triple.getArch()) { 3829 default: 3830 case llvm::Triple::x86: 3831 // this->MCountName = ".mcount"; 3832 break; 3833 case llvm::Triple::mips: 3834 case llvm::Triple::mipsel: 3835 case llvm::Triple::ppc: 3836 case llvm::Triple::ppc64: 3837 case llvm::Triple::ppc64le: 3838 // this->MCountName = "_mcount"; 3839 break; 3840 case llvm::Triple::arm: 3841 // this->MCountName = "__mcount"; 3842 break; 3843 } 3844 } 3845 }; 3846 3847 // x86-32 RTEMS target 3848 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3849 public: 3850 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3851 SizeType = UnsignedLong; 3852 IntPtrType = SignedLong; 3853 PtrDiffType = SignedLong; 3854 this->UserLabelPrefix = ""; 3855 } 3856 void getTargetDefines(const LangOptions &Opts, 3857 MacroBuilder &Builder) const override { 3858 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3859 Builder.defineMacro("__INTEL__"); 3860 Builder.defineMacro("__rtems__"); 3861 } 3862 }; 3863 3864 // x86-64 generic target 3865 class X86_64TargetInfo : public X86TargetInfo { 3866 public: 3867 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3868 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3869 bool IsWinCOFF = 3870 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3871 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3872 LongDoubleWidth = 128; 3873 LongDoubleAlign = 128; 3874 LargeArrayMinWidth = 128; 3875 LargeArrayAlign = 128; 3876 SuitableAlign = 128; 3877 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3878 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3879 IntPtrType = IsX32 ? SignedInt : SignedLong; 3880 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3881 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3882 RegParmMax = 6; 3883 3884 // Pointers are 32-bit in x32. 3885 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3886 : IsWinCOFF 3887 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3888 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3889 3890 // Use fpret only for long double. 3891 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3892 3893 // Use fp2ret for _Complex long double. 3894 ComplexLongDoubleUsesFP2Ret = true; 3895 3896 // Make __builtin_ms_va_list available. 3897 HasBuiltinMSVaList = true; 3898 3899 // x86-64 has atomics up to 16 bytes. 3900 MaxAtomicPromoteWidth = 128; 3901 MaxAtomicInlineWidth = 128; 3902 } 3903 BuiltinVaListKind getBuiltinVaListKind() const override { 3904 return TargetInfo::X86_64ABIBuiltinVaList; 3905 } 3906 3907 int getEHDataRegisterNumber(unsigned RegNo) const override { 3908 if (RegNo == 0) return 0; 3909 if (RegNo == 1) return 1; 3910 return -1; 3911 } 3912 3913 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3914 return (CC == CC_C || 3915 CC == CC_X86VectorCall || 3916 CC == CC_IntelOclBicc || 3917 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3918 } 3919 3920 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3921 return CC_C; 3922 } 3923 3924 // for x32 we need it here explicitly 3925 bool hasInt128Type() const override { return true; } 3926 }; 3927 3928 // x86-64 Windows target 3929 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3930 public: 3931 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3932 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3933 WCharType = UnsignedShort; 3934 LongWidth = LongAlign = 32; 3935 DoubleAlign = LongLongAlign = 64; 3936 IntMaxType = SignedLongLong; 3937 Int64Type = SignedLongLong; 3938 SizeType = UnsignedLongLong; 3939 PtrDiffType = SignedLongLong; 3940 IntPtrType = SignedLongLong; 3941 this->UserLabelPrefix = ""; 3942 } 3943 3944 void getTargetDefines(const LangOptions &Opts, 3945 MacroBuilder &Builder) const override { 3946 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3947 Builder.defineMacro("_WIN64"); 3948 } 3949 3950 BuiltinVaListKind getBuiltinVaListKind() const override { 3951 return TargetInfo::CharPtrBuiltinVaList; 3952 } 3953 3954 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3955 switch (CC) { 3956 case CC_X86StdCall: 3957 case CC_X86ThisCall: 3958 case CC_X86FastCall: 3959 return CCCR_Ignore; 3960 case CC_C: 3961 case CC_X86VectorCall: 3962 case CC_IntelOclBicc: 3963 case CC_X86_64SysV: 3964 return CCCR_OK; 3965 default: 3966 return CCCR_Warning; 3967 } 3968 } 3969 }; 3970 3971 // x86-64 Windows Visual Studio target 3972 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3973 public: 3974 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3975 : WindowsX86_64TargetInfo(Triple) { 3976 LongDoubleWidth = LongDoubleAlign = 64; 3977 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3978 } 3979 void getTargetDefines(const LangOptions &Opts, 3980 MacroBuilder &Builder) const override { 3981 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3982 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3983 Builder.defineMacro("_M_X64", "100"); 3984 Builder.defineMacro("_M_AMD64", "100"); 3985 } 3986 }; 3987 3988 // x86-64 MinGW target 3989 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3990 public: 3991 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3992 : WindowsX86_64TargetInfo(Triple) {} 3993 void getTargetDefines(const LangOptions &Opts, 3994 MacroBuilder &Builder) const override { 3995 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3996 DefineStd(Builder, "WIN64", Opts); 3997 Builder.defineMacro("__MINGW64__"); 3998 addMinGWDefines(Opts, Builder); 3999 4000 // GCC defines this macro when it is using __gxx_personality_seh0. 4001 if (!Opts.SjLjExceptions) 4002 Builder.defineMacro("__SEH__"); 4003 } 4004 }; 4005 4006 // x86-64 Cygwin target 4007 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4008 public: 4009 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4010 : X86_64TargetInfo(Triple) { 4011 TLSSupported = false; 4012 WCharType = UnsignedShort; 4013 } 4014 void getTargetDefines(const LangOptions &Opts, 4015 MacroBuilder &Builder) const override { 4016 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4017 Builder.defineMacro("__x86_64__"); 4018 Builder.defineMacro("__CYGWIN__"); 4019 Builder.defineMacro("__CYGWIN64__"); 4020 addCygMingDefines(Opts, Builder); 4021 DefineStd(Builder, "unix", Opts); 4022 if (Opts.CPlusPlus) 4023 Builder.defineMacro("_GNU_SOURCE"); 4024 4025 // GCC defines this macro when it is using __gxx_personality_seh0. 4026 if (!Opts.SjLjExceptions) 4027 Builder.defineMacro("__SEH__"); 4028 } 4029 }; 4030 4031 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4032 public: 4033 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4034 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4035 Int64Type = SignedLongLong; 4036 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4037 llvm::Triple T = llvm::Triple(Triple); 4038 if (T.isiOS()) 4039 UseSignedCharForObjCBool = false; 4040 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4041 } 4042 4043 bool handleTargetFeatures(std::vector<std::string> &Features, 4044 DiagnosticsEngine &Diags) override { 4045 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4046 Diags)) 4047 return false; 4048 // We now know the features we have: we can decide how to align vectors. 4049 MaxVectorAlign = 4050 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4051 return true; 4052 } 4053 }; 4054 4055 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4056 public: 4057 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4058 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4059 IntMaxType = SignedLongLong; 4060 Int64Type = SignedLongLong; 4061 } 4062 }; 4063 4064 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4065 public: 4066 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4067 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4068 IntMaxType = SignedLongLong; 4069 Int64Type = SignedLongLong; 4070 } 4071 }; 4072 4073 class ARMTargetInfo : public TargetInfo { 4074 // Possible FPU choices. 4075 enum FPUMode { 4076 VFP2FPU = (1 << 0), 4077 VFP3FPU = (1 << 1), 4078 VFP4FPU = (1 << 2), 4079 NeonFPU = (1 << 3), 4080 FPARMV8 = (1 << 4) 4081 }; 4082 4083 // Possible HWDiv features. 4084 enum HWDivMode { 4085 HWDivThumb = (1 << 0), 4086 HWDivARM = (1 << 1) 4087 }; 4088 4089 static bool FPUModeIsVFP(FPUMode Mode) { 4090 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4091 } 4092 4093 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4094 static const char * const GCCRegNames[]; 4095 4096 std::string ABI, CPU; 4097 4098 StringRef DefaultCPU; 4099 StringRef CPUProfile; 4100 StringRef CPUAttr; 4101 4102 enum { 4103 FP_Default, 4104 FP_VFP, 4105 FP_Neon 4106 } FPMath; 4107 4108 unsigned ArchISA; 4109 unsigned ArchKind; 4110 unsigned ArchProfile; 4111 unsigned ArchVersion; 4112 4113 unsigned FPU : 5; 4114 4115 unsigned IsAAPCS : 1; 4116 unsigned HWDiv : 2; 4117 4118 // Initialized via features. 4119 unsigned SoftFloat : 1; 4120 unsigned SoftFloatABI : 1; 4121 4122 unsigned CRC : 1; 4123 unsigned Crypto : 1; 4124 unsigned Unaligned : 1; 4125 4126 enum { 4127 LDREX_B = (1 << 0), /// byte (8-bit) 4128 LDREX_H = (1 << 1), /// half (16-bit) 4129 LDREX_W = (1 << 2), /// word (32-bit) 4130 LDREX_D = (1 << 3), /// double (64-bit) 4131 }; 4132 4133 uint32_t LDREX; 4134 4135 // ACLE 6.5.1 Hardware floating point 4136 enum { 4137 HW_FP_HP = (1 << 1), /// half (16-bit) 4138 HW_FP_SP = (1 << 2), /// single (32-bit) 4139 HW_FP_DP = (1 << 3), /// double (64-bit) 4140 }; 4141 uint32_t HW_FP; 4142 4143 static const Builtin::Info BuiltinInfo[]; 4144 4145 void setABIAAPCS() { 4146 IsAAPCS = true; 4147 4148 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4149 const llvm::Triple &T = getTriple(); 4150 4151 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4152 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4153 T.getOS() == llvm::Triple::Bitrig) 4154 SizeType = UnsignedLong; 4155 else 4156 SizeType = UnsignedInt; 4157 4158 switch (T.getOS()) { 4159 case llvm::Triple::NetBSD: 4160 WCharType = SignedInt; 4161 break; 4162 case llvm::Triple::Win32: 4163 WCharType = UnsignedShort; 4164 break; 4165 case llvm::Triple::Linux: 4166 default: 4167 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4168 WCharType = UnsignedInt; 4169 break; 4170 } 4171 4172 UseBitFieldTypeAlignment = true; 4173 4174 ZeroLengthBitfieldBoundary = 0; 4175 4176 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4177 // so set preferred for small types to 32. 4178 if (T.isOSBinFormatMachO()) { 4179 DataLayoutString = 4180 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4181 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4182 } else if (T.isOSWindows()) { 4183 assert(!BigEndian && "Windows on ARM does not support big endian"); 4184 DataLayoutString = "e" 4185 "-m:w" 4186 "-p:32:32" 4187 "-i64:64" 4188 "-v128:64:128" 4189 "-a:0:32" 4190 "-n32" 4191 "-S64"; 4192 } else if (T.isOSNaCl()) { 4193 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4194 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4195 } else { 4196 DataLayoutString = 4197 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4198 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4199 } 4200 4201 // FIXME: Enumerated types are variable width in straight AAPCS. 4202 } 4203 4204 void setABIAPCS() { 4205 const llvm::Triple &T = getTriple(); 4206 4207 IsAAPCS = false; 4208 4209 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4210 4211 // size_t is unsigned int on FreeBSD. 4212 if (T.getOS() == llvm::Triple::FreeBSD) 4213 SizeType = UnsignedInt; 4214 else 4215 SizeType = UnsignedLong; 4216 4217 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4218 WCharType = SignedInt; 4219 4220 // Do not respect the alignment of bit-field types when laying out 4221 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4222 UseBitFieldTypeAlignment = false; 4223 4224 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4225 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4226 /// gcc. 4227 ZeroLengthBitfieldBoundary = 32; 4228 4229 if (T.isOSBinFormatMachO()) 4230 DataLayoutString = 4231 BigEndian 4232 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4233 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4234 else 4235 DataLayoutString = 4236 BigEndian 4237 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4238 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4239 4240 // FIXME: Override "preferred align" for double and long long. 4241 } 4242 4243 void setArchInfo() { 4244 StringRef ArchName = getTriple().getArchName(); 4245 4246 ArchISA = llvm::ARM::parseArchISA(ArchName); 4247 DefaultCPU = getDefaultCPU(ArchName); 4248 4249 unsigned ArchKind = llvm::ARM::parseArch(ArchName); 4250 if (ArchKind == llvm::ARM::AK_INVALID) 4251 // set arch of the CPU, either provided explicitly or hardcoded default 4252 ArchKind = llvm::ARM::parseCPUArch(CPU); 4253 setArchInfo(ArchKind); 4254 } 4255 4256 void setArchInfo(unsigned Kind) { 4257 StringRef SubArch; 4258 4259 // cache TargetParser info 4260 ArchKind = Kind; 4261 SubArch = llvm::ARM::getSubArch(ArchKind); 4262 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4263 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4264 4265 // cache CPU related strings 4266 CPUAttr = getCPUAttr(); 4267 CPUProfile = getCPUProfile(); 4268 } 4269 4270 void setAtomic() { 4271 // when triple does not specify a sub arch, 4272 // then we are not using inline atomics 4273 bool ShouldUseInlineAtomic = DefaultCPU.empty() ? 4274 false : 4275 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4276 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4277 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4278 if (ArchProfile == llvm::ARM::PK_M) { 4279 MaxAtomicPromoteWidth = 32; 4280 if (ShouldUseInlineAtomic) 4281 MaxAtomicInlineWidth = 32; 4282 } 4283 else { 4284 MaxAtomicPromoteWidth = 64; 4285 if (ShouldUseInlineAtomic) 4286 MaxAtomicInlineWidth = 64; 4287 } 4288 } 4289 4290 bool isThumb() const { 4291 return (ArchISA == llvm::ARM::IK_THUMB); 4292 } 4293 4294 bool supportsThumb() const { 4295 return CPUAttr.count('T') || ArchVersion >= 6; 4296 } 4297 4298 bool supportsThumb2() const { 4299 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4300 } 4301 4302 StringRef getDefaultCPU(StringRef ArchName) const { 4303 return llvm::ARM::getDefaultCPU(ArchName); 4304 } 4305 4306 StringRef getCPUAttr() const { 4307 // For most sub-arches, the build attribute CPU name is enough. 4308 // For Cortex variants, it's slightly different. 4309 switch(ArchKind) { 4310 default: 4311 return llvm::ARM::getCPUAttr(ArchKind); 4312 case llvm::ARM::AK_ARMV6M: 4313 case llvm::ARM::AK_ARMV6SM: 4314 case llvm::ARM::AK_ARMV6HL: 4315 return "6M"; 4316 case llvm::ARM::AK_ARMV7S: 4317 return "7S"; 4318 case llvm::ARM::AK_ARMV7: 4319 case llvm::ARM::AK_ARMV7A: 4320 case llvm::ARM::AK_ARMV7L: 4321 case llvm::ARM::AK_ARMV7HL: 4322 return "7A"; 4323 case llvm::ARM::AK_ARMV7R: 4324 return "7R"; 4325 case llvm::ARM::AK_ARMV7M: 4326 return "7M"; 4327 case llvm::ARM::AK_ARMV7EM: 4328 return "7EM"; 4329 case llvm::ARM::AK_ARMV8A: 4330 return "8A"; 4331 case llvm::ARM::AK_ARMV8_1A: 4332 return "8_1A"; 4333 } 4334 } 4335 4336 StringRef getCPUProfile() const { 4337 switch(ArchProfile) { 4338 case llvm::ARM::PK_A: 4339 return "A"; 4340 case llvm::ARM::PK_R: 4341 return "R"; 4342 case llvm::ARM::PK_M: 4343 return "M"; 4344 default: 4345 return ""; 4346 } 4347 } 4348 4349 public: 4350 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4351 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4352 IsAAPCS(true), LDREX(0), HW_FP(0) { 4353 BigEndian = IsBigEndian; 4354 4355 switch (getTriple().getOS()) { 4356 case llvm::Triple::NetBSD: 4357 PtrDiffType = SignedLong; 4358 break; 4359 default: 4360 PtrDiffType = SignedInt; 4361 break; 4362 } 4363 4364 // cache arch related info 4365 setArchInfo(); 4366 4367 // {} in inline assembly are neon specifiers, not assembly variant 4368 // specifiers. 4369 NoAsmVariants = true; 4370 4371 // FIXME: This duplicates code from the driver that sets the -target-abi 4372 // option - this code is used if -target-abi isn't passed and should 4373 // be unified in some way. 4374 if (Triple.isOSBinFormatMachO()) { 4375 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4376 // the frontend matches that. 4377 if (Triple.getEnvironment() == llvm::Triple::EABI || 4378 Triple.getOS() == llvm::Triple::UnknownOS || 4379 StringRef(CPU).startswith("cortex-m")) { 4380 setABI("aapcs"); 4381 } else { 4382 setABI("apcs-gnu"); 4383 } 4384 } else if (Triple.isOSWindows()) { 4385 // FIXME: this is invalid for WindowsCE 4386 setABI("aapcs"); 4387 } else { 4388 // Select the default based on the platform. 4389 switch (Triple.getEnvironment()) { 4390 case llvm::Triple::Android: 4391 case llvm::Triple::GNUEABI: 4392 case llvm::Triple::GNUEABIHF: 4393 setABI("aapcs-linux"); 4394 break; 4395 case llvm::Triple::EABIHF: 4396 case llvm::Triple::EABI: 4397 setABI("aapcs"); 4398 break; 4399 case llvm::Triple::GNU: 4400 setABI("apcs-gnu"); 4401 break; 4402 default: 4403 if (Triple.getOS() == llvm::Triple::NetBSD) 4404 setABI("apcs-gnu"); 4405 else 4406 setABI("aapcs"); 4407 break; 4408 } 4409 } 4410 4411 // ARM targets default to using the ARM C++ ABI. 4412 TheCXXABI.set(TargetCXXABI::GenericARM); 4413 4414 // ARM has atomics up to 8 bytes 4415 setAtomic(); 4416 4417 // Do force alignment of members that follow zero length bitfields. If 4418 // the alignment of the zero-length bitfield is greater than the member 4419 // that follows it, `bar', `bar' will be aligned as the type of the 4420 // zero length bitfield. 4421 UseZeroLengthBitfieldAlignment = true; 4422 } 4423 4424 StringRef getABI() const override { return ABI; } 4425 4426 bool setABI(const std::string &Name) override { 4427 ABI = Name; 4428 4429 // The defaults (above) are for AAPCS, check if we need to change them. 4430 // 4431 // FIXME: We need support for -meabi... we could just mangle it into the 4432 // name. 4433 if (Name == "apcs-gnu") { 4434 setABIAPCS(); 4435 return true; 4436 } 4437 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4438 setABIAAPCS(); 4439 return true; 4440 } 4441 return false; 4442 } 4443 4444 // FIXME: This should be based on Arch attributes, not CPU names. 4445 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4446 StringRef CPU, 4447 std::vector<std::string> &FeaturesVec) const override { 4448 4449 std::vector<const char*> TargetFeatures; 4450 4451 // get default FPU features 4452 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4453 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4454 4455 // get default Extension features 4456 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4457 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4458 4459 for (const char *Feature : TargetFeatures) 4460 if (Feature[0] == '+') 4461 Features[Feature+1] = true; 4462 4463 if (ArchVersion < 6 || 4464 (ArchVersion == 6 && ArchProfile == llvm::ARM::PK_M)) 4465 Features["strict-align"] = true; 4466 4467 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4468 } 4469 4470 bool handleTargetFeatures(std::vector<std::string> &Features, 4471 DiagnosticsEngine &Diags) override { 4472 FPU = 0; 4473 CRC = 0; 4474 Crypto = 0; 4475 Unaligned = 1; 4476 SoftFloat = SoftFloatABI = false; 4477 HWDiv = 0; 4478 4479 // This does not diagnose illegal cases like having both 4480 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4481 uint32_t HW_FP_remove = 0; 4482 for (const auto &Feature : Features) { 4483 if (Feature == "+soft-float") { 4484 SoftFloat = true; 4485 } else if (Feature == "+soft-float-abi") { 4486 SoftFloatABI = true; 4487 } else if (Feature == "+vfp2") { 4488 FPU |= VFP2FPU; 4489 HW_FP |= HW_FP_SP | HW_FP_DP; 4490 } else if (Feature == "+vfp3") { 4491 FPU |= VFP3FPU; 4492 HW_FP |= HW_FP_SP | HW_FP_DP; 4493 } else if (Feature == "+vfp4") { 4494 FPU |= VFP4FPU; 4495 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4496 } else if (Feature == "+fp-armv8") { 4497 FPU |= FPARMV8; 4498 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4499 } else if (Feature == "+neon") { 4500 FPU |= NeonFPU; 4501 HW_FP |= HW_FP_SP | HW_FP_DP; 4502 } else if (Feature == "+hwdiv") { 4503 HWDiv |= HWDivThumb; 4504 } else if (Feature == "+hwdiv-arm") { 4505 HWDiv |= HWDivARM; 4506 } else if (Feature == "+crc") { 4507 CRC = 1; 4508 } else if (Feature == "+crypto") { 4509 Crypto = 1; 4510 } else if (Feature == "+fp-only-sp") { 4511 HW_FP_remove |= HW_FP_DP | HW_FP_HP; 4512 } else if (Feature == "+strict-align") { 4513 Unaligned = 0; 4514 } else if (Feature == "+fp16") { 4515 HW_FP |= HW_FP_HP; 4516 } 4517 } 4518 HW_FP &= ~HW_FP_remove; 4519 4520 switch (ArchVersion) { 4521 case 6: 4522 if (ArchProfile == llvm::ARM::PK_M) 4523 LDREX = 0; 4524 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4525 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4526 else 4527 LDREX = LDREX_W; 4528 break; 4529 case 7: 4530 if (ArchProfile == llvm::ARM::PK_M) 4531 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4532 else 4533 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4534 break; 4535 case 8: 4536 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4537 } 4538 4539 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4540 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4541 return false; 4542 } 4543 4544 if (FPMath == FP_Neon) 4545 Features.push_back("+neonfp"); 4546 else if (FPMath == FP_VFP) 4547 Features.push_back("-neonfp"); 4548 4549 // Remove front-end specific options which the backend handles differently. 4550 auto Feature = 4551 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4552 if (Feature != Features.end()) 4553 Features.erase(Feature); 4554 4555 return true; 4556 } 4557 4558 bool hasFeature(StringRef Feature) const override { 4559 return llvm::StringSwitch<bool>(Feature) 4560 .Case("arm", true) 4561 .Case("aarch32", true) 4562 .Case("softfloat", SoftFloat) 4563 .Case("thumb", isThumb()) 4564 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4565 .Case("hwdiv", HWDiv & HWDivThumb) 4566 .Case("hwdiv-arm", HWDiv & HWDivARM) 4567 .Default(false); 4568 } 4569 4570 bool setCPU(const std::string &Name) override { 4571 if (Name != "generic") 4572 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4573 4574 if (ArchKind == llvm::ARM::AK_INVALID) 4575 return false; 4576 setAtomic(); 4577 CPU = Name; 4578 return true; 4579 } 4580 4581 bool setFPMath(StringRef Name) override; 4582 4583 void getTargetDefines(const LangOptions &Opts, 4584 MacroBuilder &Builder) const override { 4585 // Target identification. 4586 Builder.defineMacro("__arm"); 4587 Builder.defineMacro("__arm__"); 4588 4589 // Target properties. 4590 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4591 if (!CPUAttr.empty()) 4592 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4593 4594 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4595 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4596 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4597 4598 if (ArchVersion >= 8) { 4599 // ACLE 6.5.7 Crypto Extension 4600 if (Crypto) 4601 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4602 // ACLE 6.5.8 CRC32 Extension 4603 if (CRC) 4604 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4605 // ACLE 6.5.10 Numeric Maximum and Minimum 4606 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4607 // ACLE 6.5.9 Directed Rounding 4608 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4609 } 4610 4611 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4612 // is not defined for the M-profile. 4613 // NOTE that the deffault profile is assumed to be 'A' 4614 if (CPUProfile.empty() || CPUProfile != "M") 4615 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4616 4617 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4618 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4619 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4620 if (supportsThumb2()) 4621 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4622 else if (supportsThumb()) 4623 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4624 4625 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4626 // instruction set such as ARM or Thumb. 4627 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4628 4629 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4630 4631 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4632 if (!CPUProfile.empty()) 4633 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4634 4635 // ACLE 6.4.3 Unaligned access supported in hardware 4636 if (Unaligned) 4637 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4638 4639 // ACLE 6.4.4 LDREX/STREX 4640 if (LDREX) 4641 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4642 4643 // ACLE 6.4.5 CLZ 4644 if (ArchVersion == 5 || 4645 (ArchVersion == 6 && CPUProfile != "M") || 4646 ArchVersion > 6) 4647 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4648 4649 // ACLE 6.5.1 Hardware Floating Point 4650 if (HW_FP) 4651 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4652 4653 // ACLE predefines. 4654 Builder.defineMacro("__ARM_ACLE", "200"); 4655 4656 // FP16 support (we currently only support IEEE format). 4657 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4658 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4659 4660 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4661 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4662 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4663 4664 // Subtarget options. 4665 4666 // FIXME: It's more complicated than this and we don't really support 4667 // interworking. 4668 // Windows on ARM does not "support" interworking 4669 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4670 Builder.defineMacro("__THUMB_INTERWORK__"); 4671 4672 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4673 // Embedded targets on Darwin follow AAPCS, but not EABI. 4674 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4675 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4676 Builder.defineMacro("__ARM_EABI__"); 4677 Builder.defineMacro("__ARM_PCS", "1"); 4678 4679 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4680 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4681 } 4682 4683 if (SoftFloat) 4684 Builder.defineMacro("__SOFTFP__"); 4685 4686 if (CPU == "xscale") 4687 Builder.defineMacro("__XSCALE__"); 4688 4689 if (isThumb()) { 4690 Builder.defineMacro("__THUMBEL__"); 4691 Builder.defineMacro("__thumb__"); 4692 if (supportsThumb2()) 4693 Builder.defineMacro("__thumb2__"); 4694 } 4695 4696 // ACLE 6.4.9 32-bit SIMD instructions 4697 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4698 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4699 4700 // ACLE 6.4.10 Hardware Integer Divide 4701 if (((HWDiv & HWDivThumb) && isThumb()) || ((HWDiv & HWDivARM) && !isThumb())) { 4702 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4703 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4704 } 4705 4706 // Note, this is always on in gcc, even though it doesn't make sense. 4707 Builder.defineMacro("__APCS_32__"); 4708 4709 if (FPUModeIsVFP((FPUMode) FPU)) { 4710 Builder.defineMacro("__VFP_FP__"); 4711 if (FPU & VFP2FPU) 4712 Builder.defineMacro("__ARM_VFPV2__"); 4713 if (FPU & VFP3FPU) 4714 Builder.defineMacro("__ARM_VFPV3__"); 4715 if (FPU & VFP4FPU) 4716 Builder.defineMacro("__ARM_VFPV4__"); 4717 } 4718 4719 // This only gets set when Neon instructions are actually available, unlike 4720 // the VFP define, hence the soft float and arch check. This is subtly 4721 // different from gcc, we follow the intent which was that it should be set 4722 // when Neon instructions are actually available. 4723 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4724 Builder.defineMacro("__ARM_NEON", "1"); 4725 Builder.defineMacro("__ARM_NEON__"); 4726 // current AArch32 NEON implementations do not support double-precision 4727 // floating-point even when it is present in VFP. 4728 Builder.defineMacro("__ARM_NEON_FP", "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4729 } 4730 4731 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4732 Opts.ShortWChar ? "2" : "4"); 4733 4734 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4735 Opts.ShortEnums ? "1" : "4"); 4736 4737 if (ArchVersion >= 6 && CPUAttr != "6M") { 4738 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4739 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4740 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4741 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4742 } 4743 4744 // ACLE 6.4.7 DSP instructions 4745 bool hasDSP = false; 4746 bool is5EOrAbove = (ArchVersion >= 6 || 4747 (ArchVersion == 5 && CPUAttr.count('E'))); 4748 // FIXME: We are not getting all 32-bit ARM architectures 4749 bool is32Bit = (!isThumb() || supportsThumb2()); 4750 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUAttr == "7EM")) { 4751 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4752 hasDSP = true; 4753 } 4754 4755 // ACLE 6.4.8 Saturation instructions 4756 bool hasSAT = false; 4757 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4758 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4759 hasSAT = true; 4760 } 4761 4762 // ACLE 6.4.6 Q (saturation) flag 4763 if (hasDSP || hasSAT) 4764 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4765 } 4766 4767 void getTargetBuiltins(const Builtin::Info *&Records, 4768 unsigned &NumRecords) const override { 4769 Records = BuiltinInfo; 4770 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4771 } 4772 bool isCLZForZeroUndef() const override { return false; } 4773 BuiltinVaListKind getBuiltinVaListKind() const override { 4774 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4775 } 4776 void getGCCRegNames(const char * const *&Names, 4777 unsigned &NumNames) const override; 4778 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4779 unsigned &NumAliases) const override; 4780 bool validateAsmConstraint(const char *&Name, 4781 TargetInfo::ConstraintInfo &Info) const override { 4782 switch (*Name) { 4783 default: break; 4784 case 'l': // r0-r7 4785 case 'h': // r8-r15 4786 case 'w': // VFP Floating point register single precision 4787 case 'P': // VFP Floating point register double precision 4788 Info.setAllowsRegister(); 4789 return true; 4790 case 'I': 4791 case 'J': 4792 case 'K': 4793 case 'L': 4794 case 'M': 4795 // FIXME 4796 return true; 4797 case 'Q': // A memory address that is a single base register. 4798 Info.setAllowsMemory(); 4799 return true; 4800 case 'U': // a memory reference... 4801 switch (Name[1]) { 4802 case 'q': // ...ARMV4 ldrsb 4803 case 'v': // ...VFP load/store (reg+constant offset) 4804 case 'y': // ...iWMMXt load/store 4805 case 't': // address valid for load/store opaque types wider 4806 // than 128-bits 4807 case 'n': // valid address for Neon doubleword vector load/store 4808 case 'm': // valid address for Neon element and structure load/store 4809 case 's': // valid address for non-offset loads/stores of quad-word 4810 // values in four ARM registers 4811 Info.setAllowsMemory(); 4812 Name++; 4813 return true; 4814 } 4815 } 4816 return false; 4817 } 4818 std::string convertConstraint(const char *&Constraint) const override { 4819 std::string R; 4820 switch (*Constraint) { 4821 case 'U': // Two-character constraint; add "^" hint for later parsing. 4822 R = std::string("^") + std::string(Constraint, 2); 4823 Constraint++; 4824 break; 4825 case 'p': // 'p' should be translated to 'r' by default. 4826 R = std::string("r"); 4827 break; 4828 default: 4829 return std::string(1, *Constraint); 4830 } 4831 return R; 4832 } 4833 bool 4834 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4835 std::string &SuggestedModifier) const override { 4836 bool isOutput = (Constraint[0] == '='); 4837 bool isInOut = (Constraint[0] == '+'); 4838 4839 // Strip off constraint modifiers. 4840 while (Constraint[0] == '=' || 4841 Constraint[0] == '+' || 4842 Constraint[0] == '&') 4843 Constraint = Constraint.substr(1); 4844 4845 switch (Constraint[0]) { 4846 default: break; 4847 case 'r': { 4848 switch (Modifier) { 4849 default: 4850 return (isInOut || isOutput || Size <= 64); 4851 case 'q': 4852 // A register of size 32 cannot fit a vector type. 4853 return false; 4854 } 4855 } 4856 } 4857 4858 return true; 4859 } 4860 const char *getClobbers() const override { 4861 // FIXME: Is this really right? 4862 return ""; 4863 } 4864 4865 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4866 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4867 } 4868 4869 int getEHDataRegisterNumber(unsigned RegNo) const override { 4870 if (RegNo == 0) return 0; 4871 if (RegNo == 1) return 1; 4872 return -1; 4873 } 4874 4875 bool hasSjLjLowering() const override { 4876 return true; 4877 } 4878 }; 4879 4880 bool ARMTargetInfo::setFPMath(StringRef Name) { 4881 if (Name == "neon") { 4882 FPMath = FP_Neon; 4883 return true; 4884 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4885 Name == "vfp4") { 4886 FPMath = FP_VFP; 4887 return true; 4888 } 4889 return false; 4890 } 4891 4892 const char * const ARMTargetInfo::GCCRegNames[] = { 4893 // Integer registers 4894 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4895 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4896 4897 // Float registers 4898 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4899 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4900 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4901 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4902 4903 // Double registers 4904 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4905 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4906 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4907 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4908 4909 // Quad registers 4910 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4911 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4912 }; 4913 4914 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4915 unsigned &NumNames) const { 4916 Names = GCCRegNames; 4917 NumNames = llvm::array_lengthof(GCCRegNames); 4918 } 4919 4920 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4921 { { "a1" }, "r0" }, 4922 { { "a2" }, "r1" }, 4923 { { "a3" }, "r2" }, 4924 { { "a4" }, "r3" }, 4925 { { "v1" }, "r4" }, 4926 { { "v2" }, "r5" }, 4927 { { "v3" }, "r6" }, 4928 { { "v4" }, "r7" }, 4929 { { "v5" }, "r8" }, 4930 { { "v6", "rfp" }, "r9" }, 4931 { { "sl" }, "r10" }, 4932 { { "fp" }, "r11" }, 4933 { { "ip" }, "r12" }, 4934 { { "r13" }, "sp" }, 4935 { { "r14" }, "lr" }, 4936 { { "r15" }, "pc" }, 4937 // The S, D and Q registers overlap, but aren't really aliases; we 4938 // don't want to substitute one of these for a different-sized one. 4939 }; 4940 4941 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4942 unsigned &NumAliases) const { 4943 Aliases = GCCRegAliases; 4944 NumAliases = llvm::array_lengthof(GCCRegAliases); 4945 } 4946 4947 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4948 #define BUILTIN(ID, TYPE, ATTRS) \ 4949 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4950 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4951 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4952 #include "clang/Basic/BuiltinsNEON.def" 4953 4954 #define BUILTIN(ID, TYPE, ATTRS) \ 4955 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 4956 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 4957 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 4958 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 4959 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 4960 #include "clang/Basic/BuiltinsARM.def" 4961 }; 4962 4963 class ARMleTargetInfo : public ARMTargetInfo { 4964 public: 4965 ARMleTargetInfo(const llvm::Triple &Triple) 4966 : ARMTargetInfo(Triple, false) { } 4967 void getTargetDefines(const LangOptions &Opts, 4968 MacroBuilder &Builder) const override { 4969 Builder.defineMacro("__ARMEL__"); 4970 ARMTargetInfo::getTargetDefines(Opts, Builder); 4971 } 4972 }; 4973 4974 class ARMbeTargetInfo : public ARMTargetInfo { 4975 public: 4976 ARMbeTargetInfo(const llvm::Triple &Triple) 4977 : ARMTargetInfo(Triple, true) { } 4978 void getTargetDefines(const LangOptions &Opts, 4979 MacroBuilder &Builder) const override { 4980 Builder.defineMacro("__ARMEB__"); 4981 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4982 ARMTargetInfo::getTargetDefines(Opts, Builder); 4983 } 4984 }; 4985 4986 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4987 const llvm::Triple Triple; 4988 public: 4989 WindowsARMTargetInfo(const llvm::Triple &Triple) 4990 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4991 TLSSupported = false; 4992 WCharType = UnsignedShort; 4993 SizeType = UnsignedInt; 4994 UserLabelPrefix = ""; 4995 } 4996 void getVisualStudioDefines(const LangOptions &Opts, 4997 MacroBuilder &Builder) const { 4998 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4999 5000 // FIXME: this is invalid for WindowsCE 5001 Builder.defineMacro("_M_ARM_NT", "1"); 5002 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5003 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5004 5005 assert((Triple.getArch() == llvm::Triple::arm || 5006 Triple.getArch() == llvm::Triple::thumb) && 5007 "invalid architecture for Windows ARM target info"); 5008 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5009 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5010 5011 // TODO map the complete set of values 5012 // 31: VFPv3 40: VFPv4 5013 Builder.defineMacro("_M_ARM_FP", "31"); 5014 } 5015 BuiltinVaListKind getBuiltinVaListKind() const override { 5016 return TargetInfo::CharPtrBuiltinVaList; 5017 } 5018 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5019 switch (CC) { 5020 case CC_X86StdCall: 5021 case CC_X86ThisCall: 5022 case CC_X86FastCall: 5023 case CC_X86VectorCall: 5024 return CCCR_Ignore; 5025 case CC_C: 5026 return CCCR_OK; 5027 default: 5028 return CCCR_Warning; 5029 } 5030 } 5031 }; 5032 5033 // Windows ARM + Itanium C++ ABI Target 5034 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5035 public: 5036 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5037 : WindowsARMTargetInfo(Triple) { 5038 TheCXXABI.set(TargetCXXABI::GenericARM); 5039 } 5040 5041 void getTargetDefines(const LangOptions &Opts, 5042 MacroBuilder &Builder) const override { 5043 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5044 5045 if (Opts.MSVCCompat) 5046 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5047 } 5048 }; 5049 5050 // Windows ARM, MS (C++) ABI 5051 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5052 public: 5053 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5054 : WindowsARMTargetInfo(Triple) { 5055 TheCXXABI.set(TargetCXXABI::Microsoft); 5056 } 5057 5058 void getTargetDefines(const LangOptions &Opts, 5059 MacroBuilder &Builder) const override { 5060 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5061 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5062 } 5063 }; 5064 5065 // ARM MinGW target 5066 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5067 public: 5068 MinGWARMTargetInfo(const llvm::Triple &Triple) 5069 : WindowsARMTargetInfo(Triple) { 5070 TheCXXABI.set(TargetCXXABI::GenericARM); 5071 } 5072 5073 void getTargetDefines(const LangOptions &Opts, 5074 MacroBuilder &Builder) const override { 5075 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5076 DefineStd(Builder, "WIN32", Opts); 5077 DefineStd(Builder, "WINNT", Opts); 5078 Builder.defineMacro("_ARM_"); 5079 addMinGWDefines(Opts, Builder); 5080 } 5081 }; 5082 5083 // ARM Cygwin target 5084 class CygwinARMTargetInfo : public ARMleTargetInfo { 5085 public: 5086 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5087 TLSSupported = false; 5088 WCharType = UnsignedShort; 5089 DoubleAlign = LongLongAlign = 64; 5090 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5091 } 5092 void getTargetDefines(const LangOptions &Opts, 5093 MacroBuilder &Builder) const override { 5094 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5095 Builder.defineMacro("_ARM_"); 5096 Builder.defineMacro("__CYGWIN__"); 5097 Builder.defineMacro("__CYGWIN32__"); 5098 DefineStd(Builder, "unix", Opts); 5099 if (Opts.CPlusPlus) 5100 Builder.defineMacro("_GNU_SOURCE"); 5101 } 5102 }; 5103 5104 class DarwinARMTargetInfo : 5105 public DarwinTargetInfo<ARMleTargetInfo> { 5106 protected: 5107 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5108 MacroBuilder &Builder) const override { 5109 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5110 } 5111 5112 public: 5113 DarwinARMTargetInfo(const llvm::Triple &Triple) 5114 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5115 HasAlignMac68kSupport = true; 5116 // iOS always has 64-bit atomic instructions. 5117 // FIXME: This should be based off of the target features in 5118 // ARMleTargetInfo. 5119 MaxAtomicInlineWidth = 64; 5120 5121 // Darwin on iOS uses a variant of the ARM C++ ABI. 5122 TheCXXABI.set(TargetCXXABI::iOS); 5123 } 5124 }; 5125 5126 class AArch64TargetInfo : public TargetInfo { 5127 virtual void setDataLayoutString() = 0; 5128 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5129 static const char *const GCCRegNames[]; 5130 5131 enum FPUModeEnum { 5132 FPUMode, 5133 NeonMode 5134 }; 5135 5136 unsigned FPU; 5137 unsigned CRC; 5138 unsigned Crypto; 5139 unsigned Unaligned; 5140 5141 static const Builtin::Info BuiltinInfo[]; 5142 5143 std::string ABI; 5144 5145 public: 5146 AArch64TargetInfo(const llvm::Triple &Triple) 5147 : TargetInfo(Triple), ABI("aapcs") { 5148 5149 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5150 WCharType = SignedInt; 5151 5152 // NetBSD apparently prefers consistency across ARM targets to consistency 5153 // across 64-bit targets. 5154 Int64Type = SignedLongLong; 5155 IntMaxType = SignedLongLong; 5156 } else { 5157 WCharType = UnsignedInt; 5158 Int64Type = SignedLong; 5159 IntMaxType = SignedLong; 5160 } 5161 5162 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5163 MaxVectorAlign = 128; 5164 MaxAtomicInlineWidth = 128; 5165 MaxAtomicPromoteWidth = 128; 5166 5167 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5168 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5169 5170 // {} in inline assembly are neon specifiers, not assembly variant 5171 // specifiers. 5172 NoAsmVariants = true; 5173 5174 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5175 // contributes to the alignment of the containing aggregate in the same way 5176 // a plain (non bit-field) member of that type would, without exception for 5177 // zero-sized or anonymous bit-fields." 5178 UseBitFieldTypeAlignment = true; 5179 UseZeroLengthBitfieldAlignment = true; 5180 5181 // AArch64 targets default to using the ARM C++ ABI. 5182 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5183 } 5184 5185 StringRef getABI() const override { return ABI; } 5186 bool setABI(const std::string &Name) override { 5187 if (Name != "aapcs" && Name != "darwinpcs") 5188 return false; 5189 5190 ABI = Name; 5191 return true; 5192 } 5193 5194 bool setCPU(const std::string &Name) override { 5195 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5196 .Case("generic", true) 5197 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5198 .Case("cyclone", true) 5199 .Default(false); 5200 return CPUKnown; 5201 } 5202 5203 void getTargetDefines(const LangOptions &Opts, 5204 MacroBuilder &Builder) const override { 5205 // Target identification. 5206 Builder.defineMacro("__aarch64__"); 5207 5208 // Target properties. 5209 Builder.defineMacro("_LP64"); 5210 Builder.defineMacro("__LP64__"); 5211 5212 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5213 Builder.defineMacro("__ARM_ACLE", "200"); 5214 Builder.defineMacro("__ARM_ARCH", "8"); 5215 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5216 5217 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5218 Builder.defineMacro("__ARM_PCS_AAPCS64"); 5219 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5220 5221 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5222 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5223 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5224 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5225 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5226 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5227 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5228 5229 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5230 5231 // 0xe implies support for half, single and double precision operations. 5232 Builder.defineMacro("__ARM_FP", "0xE"); 5233 5234 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5235 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5236 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5237 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5238 5239 if (Opts.FastMath || Opts.FiniteMathOnly) 5240 Builder.defineMacro("__ARM_FP_FAST"); 5241 5242 if (Opts.C99 && !Opts.Freestanding) 5243 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 5244 5245 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5246 5247 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5248 Opts.ShortEnums ? "1" : "4"); 5249 5250 if (FPU == NeonMode) { 5251 Builder.defineMacro("__ARM_NEON", "1"); 5252 // 64-bit NEON supports half, single and double precision operations. 5253 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5254 } 5255 5256 if (CRC) 5257 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5258 5259 if (Crypto) 5260 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5261 5262 if (Unaligned) 5263 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5264 5265 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5266 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5267 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5268 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5269 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5270 } 5271 5272 void getTargetBuiltins(const Builtin::Info *&Records, 5273 unsigned &NumRecords) const override { 5274 Records = BuiltinInfo; 5275 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 5276 } 5277 5278 bool hasFeature(StringRef Feature) const override { 5279 return Feature == "aarch64" || 5280 Feature == "arm64" || 5281 Feature == "arm" || 5282 (Feature == "neon" && FPU == NeonMode); 5283 } 5284 5285 bool handleTargetFeatures(std::vector<std::string> &Features, 5286 DiagnosticsEngine &Diags) override { 5287 FPU = FPUMode; 5288 CRC = 0; 5289 Crypto = 0; 5290 Unaligned = 1; 5291 5292 for (const auto &Feature : Features) { 5293 if (Feature == "+neon") 5294 FPU = NeonMode; 5295 if (Feature == "+crc") 5296 CRC = 1; 5297 if (Feature == "+crypto") 5298 Crypto = 1; 5299 if (Feature == "+strict-align") 5300 Unaligned = 0; 5301 } 5302 5303 setDataLayoutString(); 5304 5305 return true; 5306 } 5307 5308 bool isCLZForZeroUndef() const override { return false; } 5309 5310 BuiltinVaListKind getBuiltinVaListKind() const override { 5311 return TargetInfo::AArch64ABIBuiltinVaList; 5312 } 5313 5314 void getGCCRegNames(const char *const *&Names, 5315 unsigned &NumNames) const override; 5316 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5317 unsigned &NumAliases) const override; 5318 5319 bool validateAsmConstraint(const char *&Name, 5320 TargetInfo::ConstraintInfo &Info) const override { 5321 switch (*Name) { 5322 default: 5323 return false; 5324 case 'w': // Floating point and SIMD registers (V0-V31) 5325 Info.setAllowsRegister(); 5326 return true; 5327 case 'I': // Constant that can be used with an ADD instruction 5328 case 'J': // Constant that can be used with a SUB instruction 5329 case 'K': // Constant that can be used with a 32-bit logical instruction 5330 case 'L': // Constant that can be used with a 64-bit logical instruction 5331 case 'M': // Constant that can be used as a 32-bit MOV immediate 5332 case 'N': // Constant that can be used as a 64-bit MOV immediate 5333 case 'Y': // Floating point constant zero 5334 case 'Z': // Integer constant zero 5335 return true; 5336 case 'Q': // A memory reference with base register and no offset 5337 Info.setAllowsMemory(); 5338 return true; 5339 case 'S': // A symbolic address 5340 Info.setAllowsRegister(); 5341 return true; 5342 case 'U': 5343 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5344 // Utf: A memory address suitable for ldp/stp in TF mode. 5345 // Usa: An absolute symbolic address. 5346 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5347 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5348 case 'z': // Zero register, wzr or xzr 5349 Info.setAllowsRegister(); 5350 return true; 5351 case 'x': // Floating point and SIMD registers (V0-V15) 5352 Info.setAllowsRegister(); 5353 return true; 5354 } 5355 return false; 5356 } 5357 5358 bool 5359 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5360 std::string &SuggestedModifier) const override { 5361 // Strip off constraint modifiers. 5362 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5363 Constraint = Constraint.substr(1); 5364 5365 switch (Constraint[0]) { 5366 default: 5367 return true; 5368 case 'z': 5369 case 'r': { 5370 switch (Modifier) { 5371 case 'x': 5372 case 'w': 5373 // For now assume that the person knows what they're 5374 // doing with the modifier. 5375 return true; 5376 default: 5377 // By default an 'r' constraint will be in the 'x' 5378 // registers. 5379 if (Size == 64) 5380 return true; 5381 5382 SuggestedModifier = "w"; 5383 return false; 5384 } 5385 } 5386 } 5387 } 5388 5389 const char *getClobbers() const override { return ""; } 5390 5391 int getEHDataRegisterNumber(unsigned RegNo) const override { 5392 if (RegNo == 0) 5393 return 0; 5394 if (RegNo == 1) 5395 return 1; 5396 return -1; 5397 } 5398 }; 5399 5400 const char *const AArch64TargetInfo::GCCRegNames[] = { 5401 // 32-bit Integer registers 5402 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5403 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5404 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5405 5406 // 64-bit Integer registers 5407 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5408 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5409 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5410 5411 // 32-bit floating point regsisters 5412 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5413 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5414 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5415 5416 // 64-bit floating point regsisters 5417 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5418 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5419 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5420 5421 // Vector registers 5422 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5423 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5424 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5425 }; 5426 5427 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5428 unsigned &NumNames) const { 5429 Names = GCCRegNames; 5430 NumNames = llvm::array_lengthof(GCCRegNames); 5431 } 5432 5433 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5434 { { "w31" }, "wsp" }, 5435 { { "x29" }, "fp" }, 5436 { { "x30" }, "lr" }, 5437 { { "x31" }, "sp" }, 5438 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5439 // don't want to substitute one of these for a different-sized one. 5440 }; 5441 5442 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5443 unsigned &NumAliases) const { 5444 Aliases = GCCRegAliases; 5445 NumAliases = llvm::array_lengthof(GCCRegAliases); 5446 } 5447 5448 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5449 #define BUILTIN(ID, TYPE, ATTRS) \ 5450 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5451 #include "clang/Basic/BuiltinsNEON.def" 5452 5453 #define BUILTIN(ID, TYPE, ATTRS) \ 5454 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5455 #include "clang/Basic/BuiltinsAArch64.def" 5456 }; 5457 5458 class AArch64leTargetInfo : public AArch64TargetInfo { 5459 void setDataLayoutString() override { 5460 if (getTriple().isOSBinFormatMachO()) 5461 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5462 else 5463 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5464 } 5465 5466 public: 5467 AArch64leTargetInfo(const llvm::Triple &Triple) 5468 : AArch64TargetInfo(Triple) { 5469 BigEndian = false; 5470 } 5471 void getTargetDefines(const LangOptions &Opts, 5472 MacroBuilder &Builder) const override { 5473 Builder.defineMacro("__AARCH64EL__"); 5474 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5475 } 5476 }; 5477 5478 class AArch64beTargetInfo : public AArch64TargetInfo { 5479 void setDataLayoutString() override { 5480 assert(!getTriple().isOSBinFormatMachO()); 5481 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5482 } 5483 5484 public: 5485 AArch64beTargetInfo(const llvm::Triple &Triple) 5486 : AArch64TargetInfo(Triple) { } 5487 void getTargetDefines(const LangOptions &Opts, 5488 MacroBuilder &Builder) const override { 5489 Builder.defineMacro("__AARCH64EB__"); 5490 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5491 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5492 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5493 } 5494 }; 5495 5496 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5497 protected: 5498 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5499 MacroBuilder &Builder) const override { 5500 Builder.defineMacro("__AARCH64_SIMD__"); 5501 Builder.defineMacro("__ARM64_ARCH_8__"); 5502 Builder.defineMacro("__ARM_NEON__"); 5503 Builder.defineMacro("__LITTLE_ENDIAN__"); 5504 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5505 Builder.defineMacro("__arm64", "1"); 5506 Builder.defineMacro("__arm64__", "1"); 5507 5508 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5509 } 5510 5511 public: 5512 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5513 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5514 Int64Type = SignedLongLong; 5515 WCharType = SignedInt; 5516 UseSignedCharForObjCBool = false; 5517 5518 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5519 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5520 5521 TheCXXABI.set(TargetCXXABI::iOS64); 5522 } 5523 5524 BuiltinVaListKind getBuiltinVaListKind() const override { 5525 return TargetInfo::CharPtrBuiltinVaList; 5526 } 5527 }; 5528 5529 // Hexagon abstract base class 5530 class HexagonTargetInfo : public TargetInfo { 5531 static const Builtin::Info BuiltinInfo[]; 5532 static const char * const GCCRegNames[]; 5533 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5534 std::string CPU; 5535 public: 5536 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5537 BigEndian = false; 5538 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5539 5540 // {} in inline assembly are packet specifiers, not assembly variant 5541 // specifiers. 5542 NoAsmVariants = true; 5543 } 5544 5545 void getTargetBuiltins(const Builtin::Info *&Records, 5546 unsigned &NumRecords) const override { 5547 Records = BuiltinInfo; 5548 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5549 } 5550 5551 bool validateAsmConstraint(const char *&Name, 5552 TargetInfo::ConstraintInfo &Info) const override { 5553 return true; 5554 } 5555 5556 void getTargetDefines(const LangOptions &Opts, 5557 MacroBuilder &Builder) const override; 5558 5559 bool hasFeature(StringRef Feature) const override { 5560 return Feature == "hexagon"; 5561 } 5562 5563 BuiltinVaListKind getBuiltinVaListKind() const override { 5564 return TargetInfo::CharPtrBuiltinVaList; 5565 } 5566 void getGCCRegNames(const char * const *&Names, 5567 unsigned &NumNames) const override; 5568 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5569 unsigned &NumAliases) const override; 5570 const char *getClobbers() const override { 5571 return ""; 5572 } 5573 5574 static const char *getHexagonCPUSuffix(StringRef Name) { 5575 return llvm::StringSwitch<const char*>(Name) 5576 .Case("hexagonv4", "4") 5577 .Case("hexagonv5", "5") 5578 .Default(nullptr); 5579 } 5580 5581 bool setCPU(const std::string &Name) override { 5582 if (!getHexagonCPUSuffix(Name)) 5583 return false; 5584 5585 CPU = Name; 5586 return true; 5587 } 5588 }; 5589 5590 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5591 MacroBuilder &Builder) const { 5592 Builder.defineMacro("qdsp6"); 5593 Builder.defineMacro("__qdsp6", "1"); 5594 Builder.defineMacro("__qdsp6__", "1"); 5595 5596 Builder.defineMacro("hexagon"); 5597 Builder.defineMacro("__hexagon", "1"); 5598 Builder.defineMacro("__hexagon__", "1"); 5599 5600 if(CPU == "hexagonv1") { 5601 Builder.defineMacro("__HEXAGON_V1__"); 5602 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5603 if(Opts.HexagonQdsp6Compat) { 5604 Builder.defineMacro("__QDSP6_V1__"); 5605 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5606 } 5607 } 5608 else if(CPU == "hexagonv2") { 5609 Builder.defineMacro("__HEXAGON_V2__"); 5610 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5611 if(Opts.HexagonQdsp6Compat) { 5612 Builder.defineMacro("__QDSP6_V2__"); 5613 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5614 } 5615 } 5616 else if(CPU == "hexagonv3") { 5617 Builder.defineMacro("__HEXAGON_V3__"); 5618 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5619 if(Opts.HexagonQdsp6Compat) { 5620 Builder.defineMacro("__QDSP6_V3__"); 5621 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5622 } 5623 } 5624 else if(CPU == "hexagonv4") { 5625 Builder.defineMacro("__HEXAGON_V4__"); 5626 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5627 if(Opts.HexagonQdsp6Compat) { 5628 Builder.defineMacro("__QDSP6_V4__"); 5629 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5630 } 5631 } 5632 else if(CPU == "hexagonv5") { 5633 Builder.defineMacro("__HEXAGON_V5__"); 5634 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5635 if(Opts.HexagonQdsp6Compat) { 5636 Builder.defineMacro("__QDSP6_V5__"); 5637 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5638 } 5639 } 5640 } 5641 5642 const char * const HexagonTargetInfo::GCCRegNames[] = { 5643 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5644 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5645 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5646 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5647 "p0", "p1", "p2", "p3", 5648 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5649 }; 5650 5651 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5652 unsigned &NumNames) const { 5653 Names = GCCRegNames; 5654 NumNames = llvm::array_lengthof(GCCRegNames); 5655 } 5656 5657 5658 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5659 { { "sp" }, "r29" }, 5660 { { "fp" }, "r30" }, 5661 { { "lr" }, "r31" }, 5662 }; 5663 5664 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5665 unsigned &NumAliases) const { 5666 Aliases = GCCRegAliases; 5667 NumAliases = llvm::array_lengthof(GCCRegAliases); 5668 } 5669 5670 5671 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5672 #define BUILTIN(ID, TYPE, ATTRS) \ 5673 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5674 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5675 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5676 #include "clang/Basic/BuiltinsHexagon.def" 5677 }; 5678 5679 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5680 class SparcTargetInfo : public TargetInfo { 5681 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5682 static const char * const GCCRegNames[]; 5683 bool SoftFloat; 5684 public: 5685 SparcTargetInfo(const llvm::Triple &Triple) 5686 : TargetInfo(Triple), SoftFloat(false) {} 5687 5688 bool handleTargetFeatures(std::vector<std::string> &Features, 5689 DiagnosticsEngine &Diags) override { 5690 // The backend doesn't actually handle soft float yet, but in case someone 5691 // is using the support for the front end continue to support it. 5692 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5693 if (Feature != Features.end()) { 5694 SoftFloat = true; 5695 Features.erase(Feature); 5696 } 5697 return true; 5698 } 5699 void getTargetDefines(const LangOptions &Opts, 5700 MacroBuilder &Builder) const override { 5701 DefineStd(Builder, "sparc", Opts); 5702 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5703 5704 if (SoftFloat) 5705 Builder.defineMacro("SOFT_FLOAT", "1"); 5706 } 5707 5708 bool hasFeature(StringRef Feature) const override { 5709 return llvm::StringSwitch<bool>(Feature) 5710 .Case("softfloat", SoftFloat) 5711 .Case("sparc", true) 5712 .Default(false); 5713 } 5714 5715 void getTargetBuiltins(const Builtin::Info *&Records, 5716 unsigned &NumRecords) const override { 5717 // FIXME: Implement! 5718 } 5719 BuiltinVaListKind getBuiltinVaListKind() const override { 5720 return TargetInfo::VoidPtrBuiltinVaList; 5721 } 5722 void getGCCRegNames(const char * const *&Names, 5723 unsigned &NumNames) const override; 5724 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5725 unsigned &NumAliases) const override; 5726 bool validateAsmConstraint(const char *&Name, 5727 TargetInfo::ConstraintInfo &info) const override { 5728 // FIXME: Implement! 5729 switch (*Name) { 5730 case 'I': // Signed 13-bit constant 5731 case 'J': // Zero 5732 case 'K': // 32-bit constant with the low 12 bits clear 5733 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5734 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5735 case 'N': // Same as 'K' but zext (required for SIMode) 5736 case 'O': // The constant 4096 5737 return true; 5738 } 5739 return false; 5740 } 5741 const char *getClobbers() const override { 5742 // FIXME: Implement! 5743 return ""; 5744 } 5745 }; 5746 5747 const char * const SparcTargetInfo::GCCRegNames[] = { 5748 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5749 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5750 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5751 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5752 }; 5753 5754 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5755 unsigned &NumNames) const { 5756 Names = GCCRegNames; 5757 NumNames = llvm::array_lengthof(GCCRegNames); 5758 } 5759 5760 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5761 { { "g0" }, "r0" }, 5762 { { "g1" }, "r1" }, 5763 { { "g2" }, "r2" }, 5764 { { "g3" }, "r3" }, 5765 { { "g4" }, "r4" }, 5766 { { "g5" }, "r5" }, 5767 { { "g6" }, "r6" }, 5768 { { "g7" }, "r7" }, 5769 { { "o0" }, "r8" }, 5770 { { "o1" }, "r9" }, 5771 { { "o2" }, "r10" }, 5772 { { "o3" }, "r11" }, 5773 { { "o4" }, "r12" }, 5774 { { "o5" }, "r13" }, 5775 { { "o6", "sp" }, "r14" }, 5776 { { "o7" }, "r15" }, 5777 { { "l0" }, "r16" }, 5778 { { "l1" }, "r17" }, 5779 { { "l2" }, "r18" }, 5780 { { "l3" }, "r19" }, 5781 { { "l4" }, "r20" }, 5782 { { "l5" }, "r21" }, 5783 { { "l6" }, "r22" }, 5784 { { "l7" }, "r23" }, 5785 { { "i0" }, "r24" }, 5786 { { "i1" }, "r25" }, 5787 { { "i2" }, "r26" }, 5788 { { "i3" }, "r27" }, 5789 { { "i4" }, "r28" }, 5790 { { "i5" }, "r29" }, 5791 { { "i6", "fp" }, "r30" }, 5792 { { "i7" }, "r31" }, 5793 }; 5794 5795 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5796 unsigned &NumAliases) const { 5797 Aliases = GCCRegAliases; 5798 NumAliases = llvm::array_lengthof(GCCRegAliases); 5799 } 5800 5801 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5802 class SparcV8TargetInfo : public SparcTargetInfo { 5803 public: 5804 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5805 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5806 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5807 switch (getTriple().getOS()) { 5808 default: 5809 SizeType = UnsignedInt; 5810 IntPtrType = SignedInt; 5811 PtrDiffType = SignedInt; 5812 break; 5813 case llvm::Triple::NetBSD: 5814 case llvm::Triple::OpenBSD: 5815 SizeType = UnsignedLong; 5816 IntPtrType = SignedLong; 5817 PtrDiffType = SignedLong; 5818 break; 5819 } 5820 } 5821 5822 void getTargetDefines(const LangOptions &Opts, 5823 MacroBuilder &Builder) const override { 5824 SparcTargetInfo::getTargetDefines(Opts, Builder); 5825 Builder.defineMacro("__sparcv8"); 5826 } 5827 }; 5828 5829 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5830 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5831 public: 5832 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5833 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5834 BigEndian = false; 5835 } 5836 }; 5837 5838 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5839 class SparcV9TargetInfo : public SparcTargetInfo { 5840 public: 5841 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5842 // FIXME: Support Sparc quad-precision long double? 5843 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5844 // This is an LP64 platform. 5845 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5846 5847 // OpenBSD uses long long for int64_t and intmax_t. 5848 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5849 IntMaxType = SignedLongLong; 5850 else 5851 IntMaxType = SignedLong; 5852 Int64Type = IntMaxType; 5853 5854 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5855 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5856 LongDoubleWidth = 128; 5857 LongDoubleAlign = 128; 5858 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5859 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5860 } 5861 5862 void getTargetDefines(const LangOptions &Opts, 5863 MacroBuilder &Builder) const override { 5864 SparcTargetInfo::getTargetDefines(Opts, Builder); 5865 Builder.defineMacro("__sparcv9"); 5866 Builder.defineMacro("__arch64__"); 5867 // Solaris doesn't need these variants, but the BSDs do. 5868 if (getTriple().getOS() != llvm::Triple::Solaris) { 5869 Builder.defineMacro("__sparc64__"); 5870 Builder.defineMacro("__sparc_v9__"); 5871 Builder.defineMacro("__sparcv9__"); 5872 } 5873 } 5874 5875 bool setCPU(const std::string &Name) override { 5876 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5877 .Case("v9", true) 5878 .Case("ultrasparc", true) 5879 .Case("ultrasparc3", true) 5880 .Case("niagara", true) 5881 .Case("niagara2", true) 5882 .Case("niagara3", true) 5883 .Case("niagara4", true) 5884 .Default(false); 5885 5886 // No need to store the CPU yet. There aren't any CPU-specific 5887 // macros to define. 5888 return CPUKnown; 5889 } 5890 }; 5891 5892 class SystemZTargetInfo : public TargetInfo { 5893 static const Builtin::Info BuiltinInfo[]; 5894 static const char *const GCCRegNames[]; 5895 std::string CPU; 5896 bool HasTransactionalExecution; 5897 bool HasVector; 5898 5899 public: 5900 SystemZTargetInfo(const llvm::Triple &Triple) 5901 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5902 IntMaxType = SignedLong; 5903 Int64Type = SignedLong; 5904 TLSSupported = true; 5905 IntWidth = IntAlign = 32; 5906 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5907 PointerWidth = PointerAlign = 64; 5908 LongDoubleWidth = 128; 5909 LongDoubleAlign = 64; 5910 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5911 DefaultAlignForAttributeAligned = 64; 5912 MinGlobalAlign = 16; 5913 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5914 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5915 } 5916 void getTargetDefines(const LangOptions &Opts, 5917 MacroBuilder &Builder) const override { 5918 Builder.defineMacro("__s390__"); 5919 Builder.defineMacro("__s390x__"); 5920 Builder.defineMacro("__zarch__"); 5921 Builder.defineMacro("__LONG_DOUBLE_128__"); 5922 if (HasTransactionalExecution) 5923 Builder.defineMacro("__HTM__"); 5924 if (Opts.ZVector) 5925 Builder.defineMacro("__VEC__", "10301"); 5926 } 5927 void getTargetBuiltins(const Builtin::Info *&Records, 5928 unsigned &NumRecords) const override { 5929 Records = BuiltinInfo; 5930 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5931 } 5932 5933 void getGCCRegNames(const char *const *&Names, 5934 unsigned &NumNames) const override; 5935 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5936 unsigned &NumAliases) const override { 5937 // No aliases. 5938 Aliases = nullptr; 5939 NumAliases = 0; 5940 } 5941 bool validateAsmConstraint(const char *&Name, 5942 TargetInfo::ConstraintInfo &info) const override; 5943 const char *getClobbers() const override { 5944 // FIXME: Is this really right? 5945 return ""; 5946 } 5947 BuiltinVaListKind getBuiltinVaListKind() const override { 5948 return TargetInfo::SystemZBuiltinVaList; 5949 } 5950 bool setCPU(const std::string &Name) override { 5951 CPU = Name; 5952 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5953 .Case("z10", true) 5954 .Case("z196", true) 5955 .Case("zEC12", true) 5956 .Case("z13", true) 5957 .Default(false); 5958 5959 return CPUKnown; 5960 } 5961 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5962 StringRef CPU, 5963 std::vector<std::string> &FeaturesVec) const override { 5964 if (CPU == "zEC12") 5965 Features["transactional-execution"] = true; 5966 if (CPU == "z13") { 5967 Features["transactional-execution"] = true; 5968 Features["vector"] = true; 5969 } 5970 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5971 } 5972 5973 bool handleTargetFeatures(std::vector<std::string> &Features, 5974 DiagnosticsEngine &Diags) override { 5975 HasTransactionalExecution = false; 5976 for (const auto &Feature : Features) { 5977 if (Feature == "+transactional-execution") 5978 HasTransactionalExecution = true; 5979 else if (Feature == "+vector") 5980 HasVector = true; 5981 } 5982 // If we use the vector ABI, vector types are 64-bit aligned. 5983 if (HasVector) { 5984 MaxVectorAlign = 64; 5985 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5986 "-v128:64-a:8:16-n32:64"; 5987 } 5988 return true; 5989 } 5990 5991 bool hasFeature(StringRef Feature) const override { 5992 return llvm::StringSwitch<bool>(Feature) 5993 .Case("systemz", true) 5994 .Case("htm", HasTransactionalExecution) 5995 .Case("vx", HasVector) 5996 .Default(false); 5997 } 5998 5999 StringRef getABI() const override { 6000 if (HasVector) 6001 return "vector"; 6002 return ""; 6003 } 6004 6005 bool useFloat128ManglingForLongDouble() const override { 6006 return true; 6007 } 6008 }; 6009 6010 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6011 #define BUILTIN(ID, TYPE, ATTRS) \ 6012 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6013 #include "clang/Basic/BuiltinsSystemZ.def" 6014 }; 6015 6016 const char *const SystemZTargetInfo::GCCRegNames[] = { 6017 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6018 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6019 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6020 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6021 }; 6022 6023 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 6024 unsigned &NumNames) const { 6025 Names = GCCRegNames; 6026 NumNames = llvm::array_lengthof(GCCRegNames); 6027 } 6028 6029 bool SystemZTargetInfo:: 6030 validateAsmConstraint(const char *&Name, 6031 TargetInfo::ConstraintInfo &Info) const { 6032 switch (*Name) { 6033 default: 6034 return false; 6035 6036 case 'a': // Address register 6037 case 'd': // Data register (equivalent to 'r') 6038 case 'f': // Floating-point register 6039 Info.setAllowsRegister(); 6040 return true; 6041 6042 case 'I': // Unsigned 8-bit constant 6043 case 'J': // Unsigned 12-bit constant 6044 case 'K': // Signed 16-bit constant 6045 case 'L': // Signed 20-bit displacement (on all targets we support) 6046 case 'M': // 0x7fffffff 6047 return true; 6048 6049 case 'Q': // Memory with base and unsigned 12-bit displacement 6050 case 'R': // Likewise, plus an index 6051 case 'S': // Memory with base and signed 20-bit displacement 6052 case 'T': // Likewise, plus an index 6053 Info.setAllowsMemory(); 6054 return true; 6055 } 6056 } 6057 6058 class MSP430TargetInfo : public TargetInfo { 6059 static const char *const GCCRegNames[]; 6060 6061 public: 6062 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6063 BigEndian = false; 6064 TLSSupported = false; 6065 IntWidth = 16; 6066 IntAlign = 16; 6067 LongWidth = 32; 6068 LongLongWidth = 64; 6069 LongAlign = LongLongAlign = 16; 6070 PointerWidth = 16; 6071 PointerAlign = 16; 6072 SuitableAlign = 16; 6073 SizeType = UnsignedInt; 6074 IntMaxType = SignedLongLong; 6075 IntPtrType = SignedInt; 6076 PtrDiffType = SignedInt; 6077 SigAtomicType = SignedLong; 6078 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6079 } 6080 void getTargetDefines(const LangOptions &Opts, 6081 MacroBuilder &Builder) const override { 6082 Builder.defineMacro("MSP430"); 6083 Builder.defineMacro("__MSP430__"); 6084 // FIXME: defines for different 'flavours' of MCU 6085 } 6086 void getTargetBuiltins(const Builtin::Info *&Records, 6087 unsigned &NumRecords) const override { 6088 // FIXME: Implement. 6089 Records = nullptr; 6090 NumRecords = 0; 6091 } 6092 bool hasFeature(StringRef Feature) const override { 6093 return Feature == "msp430"; 6094 } 6095 void getGCCRegNames(const char *const *&Names, 6096 unsigned &NumNames) const override; 6097 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6098 unsigned &NumAliases) const override { 6099 // No aliases. 6100 Aliases = nullptr; 6101 NumAliases = 0; 6102 } 6103 bool validateAsmConstraint(const char *&Name, 6104 TargetInfo::ConstraintInfo &info) const override { 6105 // FIXME: implement 6106 switch (*Name) { 6107 case 'K': // the constant 1 6108 case 'L': // constant -1^20 .. 1^19 6109 case 'M': // constant 1-4: 6110 return true; 6111 } 6112 // No target constraints for now. 6113 return false; 6114 } 6115 const char *getClobbers() const override { 6116 // FIXME: Is this really right? 6117 return ""; 6118 } 6119 BuiltinVaListKind getBuiltinVaListKind() const override { 6120 // FIXME: implement 6121 return TargetInfo::CharPtrBuiltinVaList; 6122 } 6123 }; 6124 6125 const char *const MSP430TargetInfo::GCCRegNames[] = { 6126 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6127 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6128 6129 void MSP430TargetInfo::getGCCRegNames(const char *const *&Names, 6130 unsigned &NumNames) const { 6131 Names = GCCRegNames; 6132 NumNames = llvm::array_lengthof(GCCRegNames); 6133 } 6134 6135 // LLVM and Clang cannot be used directly to output native binaries for 6136 // target, but is used to compile C code to llvm bitcode with correct 6137 // type and alignment information. 6138 // 6139 // TCE uses the llvm bitcode as input and uses it for generating customized 6140 // target processor and program binary. TCE co-design environment is 6141 // publicly available in http://tce.cs.tut.fi 6142 6143 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6144 3, // opencl_global 6145 4, // opencl_local 6146 5, // opencl_constant 6147 // FIXME: generic has to be added to the target 6148 0, // opencl_generic 6149 0, // cuda_device 6150 0, // cuda_constant 6151 0 // cuda_shared 6152 }; 6153 6154 class TCETargetInfo : public TargetInfo { 6155 public: 6156 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6157 TLSSupported = false; 6158 IntWidth = 32; 6159 LongWidth = LongLongWidth = 32; 6160 PointerWidth = 32; 6161 IntAlign = 32; 6162 LongAlign = LongLongAlign = 32; 6163 PointerAlign = 32; 6164 SuitableAlign = 32; 6165 SizeType = UnsignedInt; 6166 IntMaxType = SignedLong; 6167 IntPtrType = SignedInt; 6168 PtrDiffType = SignedInt; 6169 FloatWidth = 32; 6170 FloatAlign = 32; 6171 DoubleWidth = 32; 6172 DoubleAlign = 32; 6173 LongDoubleWidth = 32; 6174 LongDoubleAlign = 32; 6175 FloatFormat = &llvm::APFloat::IEEEsingle; 6176 DoubleFormat = &llvm::APFloat::IEEEsingle; 6177 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6178 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6179 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6180 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6181 UseAddrSpaceMapMangling = true; 6182 } 6183 6184 void getTargetDefines(const LangOptions &Opts, 6185 MacroBuilder &Builder) const override { 6186 DefineStd(Builder, "tce", Opts); 6187 Builder.defineMacro("__TCE__"); 6188 Builder.defineMacro("__TCE_V1__"); 6189 } 6190 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6191 6192 void getTargetBuiltins(const Builtin::Info *&Records, 6193 unsigned &NumRecords) const override {} 6194 const char *getClobbers() const override { return ""; } 6195 BuiltinVaListKind getBuiltinVaListKind() const override { 6196 return TargetInfo::VoidPtrBuiltinVaList; 6197 } 6198 void getGCCRegNames(const char *const *&Names, 6199 unsigned &NumNames) const override {} 6200 bool validateAsmConstraint(const char *&Name, 6201 TargetInfo::ConstraintInfo &info) const override { 6202 return true; 6203 } 6204 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6205 unsigned &NumAliases) const override {} 6206 }; 6207 6208 class BPFTargetInfo : public TargetInfo { 6209 public: 6210 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6211 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6212 SizeType = UnsignedLong; 6213 PtrDiffType = SignedLong; 6214 IntPtrType = SignedLong; 6215 IntMaxType = SignedLong; 6216 Int64Type = SignedLong; 6217 RegParmMax = 5; 6218 if (Triple.getArch() == llvm::Triple::bpfeb) { 6219 BigEndian = true; 6220 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6221 } else { 6222 BigEndian = false; 6223 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6224 } 6225 MaxAtomicPromoteWidth = 64; 6226 MaxAtomicInlineWidth = 64; 6227 TLSSupported = false; 6228 } 6229 void getTargetDefines(const LangOptions &Opts, 6230 MacroBuilder &Builder) const override { 6231 DefineStd(Builder, "bpf", Opts); 6232 Builder.defineMacro("__BPF__"); 6233 } 6234 bool hasFeature(StringRef Feature) const override { 6235 return Feature == "bpf"; 6236 } 6237 6238 void getTargetBuiltins(const Builtin::Info *&Records, 6239 unsigned &NumRecords) const override {} 6240 const char *getClobbers() const override { 6241 return ""; 6242 } 6243 BuiltinVaListKind getBuiltinVaListKind() const override { 6244 return TargetInfo::VoidPtrBuiltinVaList; 6245 } 6246 void getGCCRegNames(const char * const *&Names, 6247 unsigned &NumNames) const override { 6248 Names = nullptr; 6249 NumNames = 0; 6250 } 6251 bool validateAsmConstraint(const char *&Name, 6252 TargetInfo::ConstraintInfo &info) const override { 6253 return true; 6254 } 6255 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6256 unsigned &NumAliases) const override { 6257 Aliases = nullptr; 6258 NumAliases = 0; 6259 } 6260 }; 6261 6262 class MipsTargetInfoBase : public TargetInfo { 6263 virtual void setDataLayoutString() = 0; 6264 6265 static const Builtin::Info BuiltinInfo[]; 6266 std::string CPU; 6267 bool IsMips16; 6268 bool IsMicromips; 6269 bool IsNan2008; 6270 bool IsSingleFloat; 6271 enum MipsFloatABI { 6272 HardFloat, SoftFloat 6273 } FloatABI; 6274 enum DspRevEnum { 6275 NoDSP, DSP1, DSP2 6276 } DspRev; 6277 bool HasMSA; 6278 6279 protected: 6280 bool HasFP64; 6281 std::string ABI; 6282 6283 public: 6284 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6285 const std::string &CPUStr) 6286 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6287 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6288 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6289 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6290 } 6291 6292 bool isNaN2008Default() const { 6293 return CPU == "mips32r6" || CPU == "mips64r6"; 6294 } 6295 6296 bool isFP64Default() const { 6297 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6298 } 6299 6300 bool isNan2008() const override { 6301 return IsNan2008; 6302 } 6303 6304 StringRef getABI() const override { return ABI; } 6305 bool setCPU(const std::string &Name) override { 6306 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6307 getTriple().getArch() == llvm::Triple::mipsel; 6308 CPU = Name; 6309 return llvm::StringSwitch<bool>(Name) 6310 .Case("mips1", IsMips32) 6311 .Case("mips2", IsMips32) 6312 .Case("mips3", true) 6313 .Case("mips4", true) 6314 .Case("mips5", true) 6315 .Case("mips32", IsMips32) 6316 .Case("mips32r2", IsMips32) 6317 .Case("mips32r3", IsMips32) 6318 .Case("mips32r5", IsMips32) 6319 .Case("mips32r6", IsMips32) 6320 .Case("mips64", true) 6321 .Case("mips64r2", true) 6322 .Case("mips64r3", true) 6323 .Case("mips64r5", true) 6324 .Case("mips64r6", true) 6325 .Case("octeon", true) 6326 .Default(false); 6327 } 6328 const std::string& getCPU() const { return CPU; } 6329 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6330 StringRef CPU, 6331 std::vector<std::string> &FeaturesVec) const override { 6332 if (CPU == "octeon") 6333 Features["mips64r2"] = Features["cnmips"] = true; 6334 else 6335 Features[CPU] = true; 6336 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6337 } 6338 6339 void getTargetDefines(const LangOptions &Opts, 6340 MacroBuilder &Builder) const override { 6341 Builder.defineMacro("__mips__"); 6342 Builder.defineMacro("_mips"); 6343 if (Opts.GNUMode) 6344 Builder.defineMacro("mips"); 6345 6346 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6347 6348 switch (FloatABI) { 6349 case HardFloat: 6350 Builder.defineMacro("__mips_hard_float", Twine(1)); 6351 break; 6352 case SoftFloat: 6353 Builder.defineMacro("__mips_soft_float", Twine(1)); 6354 break; 6355 } 6356 6357 if (IsSingleFloat) 6358 Builder.defineMacro("__mips_single_float", Twine(1)); 6359 6360 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6361 Builder.defineMacro("_MIPS_FPSET", 6362 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6363 6364 if (IsMips16) 6365 Builder.defineMacro("__mips16", Twine(1)); 6366 6367 if (IsMicromips) 6368 Builder.defineMacro("__mips_micromips", Twine(1)); 6369 6370 if (IsNan2008) 6371 Builder.defineMacro("__mips_nan2008", Twine(1)); 6372 6373 switch (DspRev) { 6374 default: 6375 break; 6376 case DSP1: 6377 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6378 Builder.defineMacro("__mips_dsp", Twine(1)); 6379 break; 6380 case DSP2: 6381 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6382 Builder.defineMacro("__mips_dspr2", Twine(1)); 6383 Builder.defineMacro("__mips_dsp", Twine(1)); 6384 break; 6385 } 6386 6387 if (HasMSA) 6388 Builder.defineMacro("__mips_msa", Twine(1)); 6389 6390 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6391 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6392 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6393 6394 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6395 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6396 } 6397 6398 void getTargetBuiltins(const Builtin::Info *&Records, 6399 unsigned &NumRecords) const override { 6400 Records = BuiltinInfo; 6401 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6402 } 6403 bool hasFeature(StringRef Feature) const override { 6404 return llvm::StringSwitch<bool>(Feature) 6405 .Case("mips", true) 6406 .Case("fp64", HasFP64) 6407 .Default(false); 6408 } 6409 BuiltinVaListKind getBuiltinVaListKind() const override { 6410 return TargetInfo::VoidPtrBuiltinVaList; 6411 } 6412 void getGCCRegNames(const char * const *&Names, 6413 unsigned &NumNames) const override { 6414 static const char *const GCCRegNames[] = { 6415 // CPU register names 6416 // Must match second column of GCCRegAliases 6417 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6418 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6419 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6420 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6421 // Floating point register names 6422 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6423 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6424 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6425 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6426 // Hi/lo and condition register names 6427 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6428 "$fcc5","$fcc6","$fcc7", 6429 // MSA register names 6430 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6431 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6432 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6433 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6434 // MSA control register names 6435 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6436 "$msarequest", "$msamap", "$msaunmap" 6437 }; 6438 Names = GCCRegNames; 6439 NumNames = llvm::array_lengthof(GCCRegNames); 6440 } 6441 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6442 unsigned &NumAliases) const override = 0; 6443 bool validateAsmConstraint(const char *&Name, 6444 TargetInfo::ConstraintInfo &Info) const override { 6445 switch (*Name) { 6446 default: 6447 return false; 6448 case 'r': // CPU registers. 6449 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6450 case 'y': // Equivalent to "r", backward compatibility only. 6451 case 'f': // floating-point registers. 6452 case 'c': // $25 for indirect jumps 6453 case 'l': // lo register 6454 case 'x': // hilo register pair 6455 Info.setAllowsRegister(); 6456 return true; 6457 case 'I': // Signed 16-bit constant 6458 case 'J': // Integer 0 6459 case 'K': // Unsigned 16-bit constant 6460 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6461 case 'M': // Constants not loadable via lui, addiu, or ori 6462 case 'N': // Constant -1 to -65535 6463 case 'O': // A signed 15-bit constant 6464 case 'P': // A constant between 1 go 65535 6465 return true; 6466 case 'R': // An address that can be used in a non-macro load or store 6467 Info.setAllowsMemory(); 6468 return true; 6469 case 'Z': 6470 if (Name[1] == 'C') { // An address usable by ll, and sc. 6471 Info.setAllowsMemory(); 6472 Name++; // Skip over 'Z'. 6473 return true; 6474 } 6475 return false; 6476 } 6477 } 6478 6479 std::string convertConstraint(const char *&Constraint) const override { 6480 std::string R; 6481 switch (*Constraint) { 6482 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6483 if (Constraint[1] == 'C') { 6484 R = std::string("^") + std::string(Constraint, 2); 6485 Constraint++; 6486 return R; 6487 } 6488 break; 6489 } 6490 return TargetInfo::convertConstraint(Constraint); 6491 } 6492 6493 const char *getClobbers() const override { 6494 // In GCC, $1 is not widely used in generated code (it's used only in a few 6495 // specific situations), so there is no real need for users to add it to 6496 // the clobbers list if they want to use it in their inline assembly code. 6497 // 6498 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6499 // code generation, so using it in inline assembly without adding it to the 6500 // clobbers list can cause conflicts between the inline assembly code and 6501 // the surrounding generated code. 6502 // 6503 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6504 // operands, which will conflict with the ".set at" assembler option (which 6505 // we use only for inline assembly, in order to maintain compatibility with 6506 // GCC) and will also conflict with the user's usage of $1. 6507 // 6508 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6509 // register for generated code is to automatically clobber $1 for all inline 6510 // assembly code. 6511 // 6512 // FIXME: We should automatically clobber $1 only for inline assembly code 6513 // which actually uses it. This would allow LLVM to use $1 for inline 6514 // assembly operands if the user's assembly code doesn't use it. 6515 return "~{$1}"; 6516 } 6517 6518 bool handleTargetFeatures(std::vector<std::string> &Features, 6519 DiagnosticsEngine &Diags) override { 6520 IsMips16 = false; 6521 IsMicromips = false; 6522 IsNan2008 = isNaN2008Default(); 6523 IsSingleFloat = false; 6524 FloatABI = HardFloat; 6525 DspRev = NoDSP; 6526 HasFP64 = isFP64Default(); 6527 6528 for (const auto &Feature : Features) { 6529 if (Feature == "+single-float") 6530 IsSingleFloat = true; 6531 else if (Feature == "+soft-float") 6532 FloatABI = SoftFloat; 6533 else if (Feature == "+mips16") 6534 IsMips16 = true; 6535 else if (Feature == "+micromips") 6536 IsMicromips = true; 6537 else if (Feature == "+dsp") 6538 DspRev = std::max(DspRev, DSP1); 6539 else if (Feature == "+dspr2") 6540 DspRev = std::max(DspRev, DSP2); 6541 else if (Feature == "+msa") 6542 HasMSA = true; 6543 else if (Feature == "+fp64") 6544 HasFP64 = true; 6545 else if (Feature == "-fp64") 6546 HasFP64 = false; 6547 else if (Feature == "+nan2008") 6548 IsNan2008 = true; 6549 else if (Feature == "-nan2008") 6550 IsNan2008 = false; 6551 } 6552 6553 setDataLayoutString(); 6554 6555 return true; 6556 } 6557 6558 int getEHDataRegisterNumber(unsigned RegNo) const override { 6559 if (RegNo == 0) return 4; 6560 if (RegNo == 1) return 5; 6561 return -1; 6562 } 6563 6564 bool isCLZForZeroUndef() const override { return false; } 6565 }; 6566 6567 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6568 #define BUILTIN(ID, TYPE, ATTRS) \ 6569 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6570 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6571 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6572 #include "clang/Basic/BuiltinsMips.def" 6573 }; 6574 6575 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6576 public: 6577 Mips32TargetInfoBase(const llvm::Triple &Triple) 6578 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6579 SizeType = UnsignedInt; 6580 PtrDiffType = SignedInt; 6581 Int64Type = SignedLongLong; 6582 IntMaxType = Int64Type; 6583 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6584 } 6585 bool setABI(const std::string &Name) override { 6586 if (Name == "o32" || Name == "eabi") { 6587 ABI = Name; 6588 return true; 6589 } 6590 return false; 6591 } 6592 void getTargetDefines(const LangOptions &Opts, 6593 MacroBuilder &Builder) const override { 6594 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6595 6596 Builder.defineMacro("__mips", "32"); 6597 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6598 6599 const std::string& CPUStr = getCPU(); 6600 if (CPUStr == "mips32") 6601 Builder.defineMacro("__mips_isa_rev", "1"); 6602 else if (CPUStr == "mips32r2") 6603 Builder.defineMacro("__mips_isa_rev", "2"); 6604 else if (CPUStr == "mips32r3") 6605 Builder.defineMacro("__mips_isa_rev", "3"); 6606 else if (CPUStr == "mips32r5") 6607 Builder.defineMacro("__mips_isa_rev", "5"); 6608 else if (CPUStr == "mips32r6") 6609 Builder.defineMacro("__mips_isa_rev", "6"); 6610 6611 if (ABI == "o32") { 6612 Builder.defineMacro("__mips_o32"); 6613 Builder.defineMacro("_ABIO32", "1"); 6614 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6615 } 6616 else if (ABI == "eabi") 6617 Builder.defineMacro("__mips_eabi"); 6618 else 6619 llvm_unreachable("Invalid ABI for Mips32."); 6620 } 6621 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6622 unsigned &NumAliases) const override { 6623 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6624 { { "at" }, "$1" }, 6625 { { "v0" }, "$2" }, 6626 { { "v1" }, "$3" }, 6627 { { "a0" }, "$4" }, 6628 { { "a1" }, "$5" }, 6629 { { "a2" }, "$6" }, 6630 { { "a3" }, "$7" }, 6631 { { "t0" }, "$8" }, 6632 { { "t1" }, "$9" }, 6633 { { "t2" }, "$10" }, 6634 { { "t3" }, "$11" }, 6635 { { "t4" }, "$12" }, 6636 { { "t5" }, "$13" }, 6637 { { "t6" }, "$14" }, 6638 { { "t7" }, "$15" }, 6639 { { "s0" }, "$16" }, 6640 { { "s1" }, "$17" }, 6641 { { "s2" }, "$18" }, 6642 { { "s3" }, "$19" }, 6643 { { "s4" }, "$20" }, 6644 { { "s5" }, "$21" }, 6645 { { "s6" }, "$22" }, 6646 { { "s7" }, "$23" }, 6647 { { "t8" }, "$24" }, 6648 { { "t9" }, "$25" }, 6649 { { "k0" }, "$26" }, 6650 { { "k1" }, "$27" }, 6651 { { "gp" }, "$28" }, 6652 { { "sp","$sp" }, "$29" }, 6653 { { "fp","$fp" }, "$30" }, 6654 { { "ra" }, "$31" } 6655 }; 6656 Aliases = GCCRegAliases; 6657 NumAliases = llvm::array_lengthof(GCCRegAliases); 6658 } 6659 }; 6660 6661 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6662 void setDataLayoutString() override { 6663 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6664 } 6665 6666 public: 6667 Mips32EBTargetInfo(const llvm::Triple &Triple) 6668 : Mips32TargetInfoBase(Triple) { 6669 } 6670 void getTargetDefines(const LangOptions &Opts, 6671 MacroBuilder &Builder) const override { 6672 DefineStd(Builder, "MIPSEB", Opts); 6673 Builder.defineMacro("_MIPSEB"); 6674 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6675 } 6676 }; 6677 6678 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6679 void setDataLayoutString() override { 6680 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6681 } 6682 6683 public: 6684 Mips32ELTargetInfo(const llvm::Triple &Triple) 6685 : Mips32TargetInfoBase(Triple) { 6686 BigEndian = false; 6687 } 6688 void getTargetDefines(const LangOptions &Opts, 6689 MacroBuilder &Builder) const override { 6690 DefineStd(Builder, "MIPSEL", Opts); 6691 Builder.defineMacro("_MIPSEL"); 6692 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6693 } 6694 }; 6695 6696 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6697 public: 6698 Mips64TargetInfoBase(const llvm::Triple &Triple) 6699 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6700 LongDoubleWidth = LongDoubleAlign = 128; 6701 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6702 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6703 LongDoubleWidth = LongDoubleAlign = 64; 6704 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6705 } 6706 setN64ABITypes(); 6707 SuitableAlign = 128; 6708 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6709 } 6710 6711 void setN64ABITypes() { 6712 LongWidth = LongAlign = 64; 6713 PointerWidth = PointerAlign = 64; 6714 SizeType = UnsignedLong; 6715 PtrDiffType = SignedLong; 6716 Int64Type = SignedLong; 6717 IntMaxType = Int64Type; 6718 } 6719 6720 void setN32ABITypes() { 6721 LongWidth = LongAlign = 32; 6722 PointerWidth = PointerAlign = 32; 6723 SizeType = UnsignedInt; 6724 PtrDiffType = SignedInt; 6725 Int64Type = SignedLongLong; 6726 IntMaxType = Int64Type; 6727 } 6728 6729 bool setABI(const std::string &Name) override { 6730 if (Name == "n32") { 6731 setN32ABITypes(); 6732 ABI = Name; 6733 return true; 6734 } 6735 if (Name == "n64") { 6736 setN64ABITypes(); 6737 ABI = Name; 6738 return true; 6739 } 6740 return false; 6741 } 6742 6743 void getTargetDefines(const LangOptions &Opts, 6744 MacroBuilder &Builder) const override { 6745 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6746 6747 Builder.defineMacro("__mips", "64"); 6748 Builder.defineMacro("__mips64"); 6749 Builder.defineMacro("__mips64__"); 6750 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6751 6752 const std::string& CPUStr = getCPU(); 6753 if (CPUStr == "mips64") 6754 Builder.defineMacro("__mips_isa_rev", "1"); 6755 else if (CPUStr == "mips64r2") 6756 Builder.defineMacro("__mips_isa_rev", "2"); 6757 else if (CPUStr == "mips64r3") 6758 Builder.defineMacro("__mips_isa_rev", "3"); 6759 else if (CPUStr == "mips64r5") 6760 Builder.defineMacro("__mips_isa_rev", "5"); 6761 else if (CPUStr == "mips64r6") 6762 Builder.defineMacro("__mips_isa_rev", "6"); 6763 6764 if (ABI == "n32") { 6765 Builder.defineMacro("__mips_n32"); 6766 Builder.defineMacro("_ABIN32", "2"); 6767 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6768 } 6769 else if (ABI == "n64") { 6770 Builder.defineMacro("__mips_n64"); 6771 Builder.defineMacro("_ABI64", "3"); 6772 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6773 } 6774 else 6775 llvm_unreachable("Invalid ABI for Mips64."); 6776 } 6777 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6778 unsigned &NumAliases) const override { 6779 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6780 { { "at" }, "$1" }, 6781 { { "v0" }, "$2" }, 6782 { { "v1" }, "$3" }, 6783 { { "a0" }, "$4" }, 6784 { { "a1" }, "$5" }, 6785 { { "a2" }, "$6" }, 6786 { { "a3" }, "$7" }, 6787 { { "a4" }, "$8" }, 6788 { { "a5" }, "$9" }, 6789 { { "a6" }, "$10" }, 6790 { { "a7" }, "$11" }, 6791 { { "t0" }, "$12" }, 6792 { { "t1" }, "$13" }, 6793 { { "t2" }, "$14" }, 6794 { { "t3" }, "$15" }, 6795 { { "s0" }, "$16" }, 6796 { { "s1" }, "$17" }, 6797 { { "s2" }, "$18" }, 6798 { { "s3" }, "$19" }, 6799 { { "s4" }, "$20" }, 6800 { { "s5" }, "$21" }, 6801 { { "s6" }, "$22" }, 6802 { { "s7" }, "$23" }, 6803 { { "t8" }, "$24" }, 6804 { { "t9" }, "$25" }, 6805 { { "k0" }, "$26" }, 6806 { { "k1" }, "$27" }, 6807 { { "gp" }, "$28" }, 6808 { { "sp","$sp" }, "$29" }, 6809 { { "fp","$fp" }, "$30" }, 6810 { { "ra" }, "$31" } 6811 }; 6812 Aliases = GCCRegAliases; 6813 NumAliases = llvm::array_lengthof(GCCRegAliases); 6814 } 6815 6816 bool hasInt128Type() const override { return true; } 6817 }; 6818 6819 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6820 void setDataLayoutString() override { 6821 if (ABI == "n32") 6822 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6823 else 6824 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6825 6826 } 6827 6828 public: 6829 Mips64EBTargetInfo(const llvm::Triple &Triple) 6830 : Mips64TargetInfoBase(Triple) {} 6831 void getTargetDefines(const LangOptions &Opts, 6832 MacroBuilder &Builder) const override { 6833 DefineStd(Builder, "MIPSEB", Opts); 6834 Builder.defineMacro("_MIPSEB"); 6835 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6836 } 6837 }; 6838 6839 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6840 void setDataLayoutString() override { 6841 if (ABI == "n32") 6842 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6843 else 6844 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6845 } 6846 public: 6847 Mips64ELTargetInfo(const llvm::Triple &Triple) 6848 : Mips64TargetInfoBase(Triple) { 6849 // Default ABI is n64. 6850 BigEndian = false; 6851 } 6852 void getTargetDefines(const LangOptions &Opts, 6853 MacroBuilder &Builder) const override { 6854 DefineStd(Builder, "MIPSEL", Opts); 6855 Builder.defineMacro("_MIPSEL"); 6856 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6857 } 6858 }; 6859 6860 class PNaClTargetInfo : public TargetInfo { 6861 public: 6862 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6863 BigEndian = false; 6864 this->UserLabelPrefix = ""; 6865 this->LongAlign = 32; 6866 this->LongWidth = 32; 6867 this->PointerAlign = 32; 6868 this->PointerWidth = 32; 6869 this->IntMaxType = TargetInfo::SignedLongLong; 6870 this->Int64Type = TargetInfo::SignedLongLong; 6871 this->DoubleAlign = 64; 6872 this->LongDoubleWidth = 64; 6873 this->LongDoubleAlign = 64; 6874 this->SizeType = TargetInfo::UnsignedInt; 6875 this->PtrDiffType = TargetInfo::SignedInt; 6876 this->IntPtrType = TargetInfo::SignedInt; 6877 this->RegParmMax = 0; // Disallow regparm 6878 } 6879 6880 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6881 Builder.defineMacro("__le32__"); 6882 Builder.defineMacro("__pnacl__"); 6883 } 6884 void getTargetDefines(const LangOptions &Opts, 6885 MacroBuilder &Builder) const override { 6886 getArchDefines(Opts, Builder); 6887 } 6888 bool hasFeature(StringRef Feature) const override { 6889 return Feature == "pnacl"; 6890 } 6891 void getTargetBuiltins(const Builtin::Info *&Records, 6892 unsigned &NumRecords) const override { 6893 } 6894 BuiltinVaListKind getBuiltinVaListKind() const override { 6895 return TargetInfo::PNaClABIBuiltinVaList; 6896 } 6897 void getGCCRegNames(const char * const *&Names, 6898 unsigned &NumNames) const override; 6899 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6900 unsigned &NumAliases) const override; 6901 bool validateAsmConstraint(const char *&Name, 6902 TargetInfo::ConstraintInfo &Info) const override { 6903 return false; 6904 } 6905 6906 const char *getClobbers() const override { 6907 return ""; 6908 } 6909 }; 6910 6911 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6912 unsigned &NumNames) const { 6913 Names = nullptr; 6914 NumNames = 0; 6915 } 6916 6917 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6918 unsigned &NumAliases) const { 6919 Aliases = nullptr; 6920 NumAliases = 0; 6921 } 6922 6923 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6924 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6925 public: 6926 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6927 Mips32ELTargetInfo(Triple) { 6928 } 6929 6930 BuiltinVaListKind getBuiltinVaListKind() const override { 6931 return TargetInfo::PNaClABIBuiltinVaList; 6932 } 6933 }; 6934 6935 class Le64TargetInfo : public TargetInfo { 6936 static const Builtin::Info BuiltinInfo[]; 6937 6938 public: 6939 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6940 BigEndian = false; 6941 NoAsmVariants = true; 6942 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6943 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6944 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6945 } 6946 6947 void getTargetDefines(const LangOptions &Opts, 6948 MacroBuilder &Builder) const override { 6949 DefineStd(Builder, "unix", Opts); 6950 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6951 Builder.defineMacro("__ELF__"); 6952 } 6953 void getTargetBuiltins(const Builtin::Info *&Records, 6954 unsigned &NumRecords) const override { 6955 Records = BuiltinInfo; 6956 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6957 } 6958 BuiltinVaListKind getBuiltinVaListKind() const override { 6959 return TargetInfo::PNaClABIBuiltinVaList; 6960 } 6961 const char *getClobbers() const override { return ""; } 6962 void getGCCRegNames(const char *const *&Names, 6963 unsigned &NumNames) const override { 6964 Names = nullptr; 6965 NumNames = 0; 6966 } 6967 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6968 unsigned &NumAliases) const override { 6969 Aliases = nullptr; 6970 NumAliases = 0; 6971 } 6972 bool validateAsmConstraint(const char *&Name, 6973 TargetInfo::ConstraintInfo &Info) const override { 6974 return false; 6975 } 6976 6977 bool hasProtectedVisibility() const override { return false; } 6978 }; 6979 6980 class WebAssemblyTargetInfo : public TargetInfo { 6981 static const Builtin::Info BuiltinInfo[]; 6982 6983 enum SIMDEnum { 6984 NoSIMD, 6985 SIMD128, 6986 } SIMDLevel; 6987 6988 public: 6989 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 6990 : TargetInfo(T), SIMDLevel(NoSIMD) { 6991 BigEndian = false; 6992 NoAsmVariants = true; 6993 SuitableAlign = 128; 6994 LargeArrayMinWidth = 128; 6995 LargeArrayAlign = 128; 6996 SimdDefaultAlign = 128; 6997 SigAtomicType = SignedLong; 6998 } 6999 7000 protected: 7001 void getTargetDefines(const LangOptions &Opts, 7002 MacroBuilder &Builder) const override { 7003 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7004 if (SIMDLevel >= SIMD128) 7005 Builder.defineMacro("__wasm_simd128__"); 7006 } 7007 7008 private: 7009 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7010 StringRef CPU, 7011 std::vector<std::string> &FeaturesVec) const override { 7012 if (CPU == "bleeding-edge") 7013 Features["simd128"] = true; 7014 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7015 } 7016 bool hasFeature(StringRef Feature) const final { 7017 return llvm::StringSwitch<bool>(Feature) 7018 .Case("simd128", SIMDLevel >= SIMD128) 7019 .Default(false); 7020 } 7021 bool handleTargetFeatures(std::vector<std::string> &Features, 7022 DiagnosticsEngine &Diags) final { 7023 for (const auto &Feature : Features) { 7024 if (Feature == "+simd128") { 7025 SIMDLevel = std::max(SIMDLevel, SIMD128); 7026 continue; 7027 } 7028 if (Feature == "-simd128") { 7029 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7030 continue; 7031 } 7032 7033 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7034 << "-target-feature"; 7035 return false; 7036 } 7037 return true; 7038 } 7039 bool setCPU(const std::string &Name) final { 7040 return llvm::StringSwitch<bool>(Name) 7041 .Case("mvp", true) 7042 .Case("bleeding-edge", true) 7043 .Case("generic", true) 7044 .Default(false); 7045 } 7046 void getTargetBuiltins(const Builtin::Info *&Records, 7047 unsigned &NumRecords) const final { 7048 Records = BuiltinInfo; 7049 NumRecords = clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin; 7050 } 7051 BuiltinVaListKind getBuiltinVaListKind() const final { 7052 // TODO: Implement va_list properly. 7053 return VoidPtrBuiltinVaList; 7054 } 7055 void getGCCRegNames(const char *const *&Names, 7056 unsigned &NumNames) const final { 7057 Names = nullptr; 7058 NumNames = 0; 7059 } 7060 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7061 unsigned &NumAliases) const final { 7062 Aliases = nullptr; 7063 NumAliases = 0; 7064 } 7065 bool 7066 validateAsmConstraint(const char *&Name, 7067 TargetInfo::ConstraintInfo &Info) const final { 7068 return false; 7069 } 7070 const char *getClobbers() const final { return ""; } 7071 bool isCLZForZeroUndef() const final { return false; } 7072 bool hasInt128Type() const final { return true; } 7073 IntType getIntTypeByWidth(unsigned BitWidth, 7074 bool IsSigned) const final { 7075 // WebAssembly prefers long long for explicitly 64-bit integers. 7076 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7077 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7078 } 7079 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7080 bool IsSigned) const final { 7081 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7082 return BitWidth == 64 7083 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7084 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7085 } 7086 }; 7087 7088 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7089 #define BUILTIN(ID, TYPE, ATTRS) \ 7090 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7091 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7092 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7093 #include "clang/Basic/BuiltinsWebAssembly.def" 7094 }; 7095 7096 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7097 public: 7098 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7099 : WebAssemblyTargetInfo(T) { 7100 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7101 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7102 } 7103 7104 protected: 7105 void getTargetDefines(const LangOptions &Opts, 7106 MacroBuilder &Builder) const override { 7107 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7108 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7109 } 7110 }; 7111 7112 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7113 public: 7114 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7115 : WebAssemblyTargetInfo(T) { 7116 LongAlign = LongWidth = 64; 7117 PointerAlign = PointerWidth = 64; 7118 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7119 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7120 } 7121 7122 protected: 7123 void getTargetDefines(const LangOptions &Opts, 7124 MacroBuilder &Builder) const override { 7125 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7126 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7127 } 7128 }; 7129 7130 } // end anonymous namespace. 7131 7132 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7133 #define BUILTIN(ID, TYPE, ATTRS) \ 7134 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7135 #include "clang/Basic/BuiltinsLe64.def" 7136 }; 7137 7138 namespace { 7139 static const unsigned SPIRAddrSpaceMap[] = { 7140 1, // opencl_global 7141 3, // opencl_local 7142 2, // opencl_constant 7143 4, // opencl_generic 7144 0, // cuda_device 7145 0, // cuda_constant 7146 0 // cuda_shared 7147 }; 7148 class SPIRTargetInfo : public TargetInfo { 7149 public: 7150 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7151 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7152 "SPIR target must use unknown OS"); 7153 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7154 "SPIR target must use unknown environment type"); 7155 BigEndian = false; 7156 TLSSupported = false; 7157 LongWidth = LongAlign = 64; 7158 AddrSpaceMap = &SPIRAddrSpaceMap; 7159 UseAddrSpaceMapMangling = true; 7160 // Define available target features 7161 // These must be defined in sorted order! 7162 NoAsmVariants = true; 7163 } 7164 void getTargetDefines(const LangOptions &Opts, 7165 MacroBuilder &Builder) const override { 7166 DefineStd(Builder, "SPIR", Opts); 7167 } 7168 bool hasFeature(StringRef Feature) const override { 7169 return Feature == "spir"; 7170 } 7171 7172 void getTargetBuiltins(const Builtin::Info *&Records, 7173 unsigned &NumRecords) const override {} 7174 const char *getClobbers() const override { return ""; } 7175 void getGCCRegNames(const char *const *&Names, 7176 unsigned &NumNames) const override {} 7177 bool validateAsmConstraint(const char *&Name, 7178 TargetInfo::ConstraintInfo &info) const override { 7179 return true; 7180 } 7181 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7182 unsigned &NumAliases) const override {} 7183 BuiltinVaListKind getBuiltinVaListKind() const override { 7184 return TargetInfo::VoidPtrBuiltinVaList; 7185 } 7186 7187 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7188 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7189 : CCCR_Warning; 7190 } 7191 7192 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7193 return CC_SpirFunction; 7194 } 7195 }; 7196 7197 class SPIR32TargetInfo : public SPIRTargetInfo { 7198 public: 7199 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7200 PointerWidth = PointerAlign = 32; 7201 SizeType = TargetInfo::UnsignedInt; 7202 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7203 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7204 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7205 } 7206 void getTargetDefines(const LangOptions &Opts, 7207 MacroBuilder &Builder) const override { 7208 DefineStd(Builder, "SPIR32", Opts); 7209 } 7210 }; 7211 7212 class SPIR64TargetInfo : public SPIRTargetInfo { 7213 public: 7214 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7215 PointerWidth = PointerAlign = 64; 7216 SizeType = TargetInfo::UnsignedLong; 7217 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7218 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7219 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7220 } 7221 void getTargetDefines(const LangOptions &Opts, 7222 MacroBuilder &Builder) const override { 7223 DefineStd(Builder, "SPIR64", Opts); 7224 } 7225 }; 7226 7227 class XCoreTargetInfo : public TargetInfo { 7228 static const Builtin::Info BuiltinInfo[]; 7229 public: 7230 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7231 BigEndian = false; 7232 NoAsmVariants = true; 7233 LongLongAlign = 32; 7234 SuitableAlign = 32; 7235 DoubleAlign = LongDoubleAlign = 32; 7236 SizeType = UnsignedInt; 7237 PtrDiffType = SignedInt; 7238 IntPtrType = SignedInt; 7239 WCharType = UnsignedChar; 7240 WIntType = UnsignedInt; 7241 UseZeroLengthBitfieldAlignment = true; 7242 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7243 "-f64:32-a:0:32-n32"; 7244 } 7245 void getTargetDefines(const LangOptions &Opts, 7246 MacroBuilder &Builder) const override { 7247 Builder.defineMacro("__XS1B__"); 7248 } 7249 void getTargetBuiltins(const Builtin::Info *&Records, 7250 unsigned &NumRecords) const override { 7251 Records = BuiltinInfo; 7252 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 7253 } 7254 BuiltinVaListKind getBuiltinVaListKind() const override { 7255 return TargetInfo::VoidPtrBuiltinVaList; 7256 } 7257 const char *getClobbers() const override { 7258 return ""; 7259 } 7260 void getGCCRegNames(const char * const *&Names, 7261 unsigned &NumNames) const override { 7262 static const char * const GCCRegNames[] = { 7263 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7264 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7265 }; 7266 Names = GCCRegNames; 7267 NumNames = llvm::array_lengthof(GCCRegNames); 7268 } 7269 void getGCCRegAliases(const GCCRegAlias *&Aliases, 7270 unsigned &NumAliases) const override { 7271 Aliases = nullptr; 7272 NumAliases = 0; 7273 } 7274 bool validateAsmConstraint(const char *&Name, 7275 TargetInfo::ConstraintInfo &Info) const override { 7276 return false; 7277 } 7278 int getEHDataRegisterNumber(unsigned RegNo) const override { 7279 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7280 return (RegNo < 2)? RegNo : -1; 7281 } 7282 }; 7283 7284 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7285 #define BUILTIN(ID, TYPE, ATTRS) \ 7286 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7287 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7288 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7289 #include "clang/Basic/BuiltinsXCore.def" 7290 }; 7291 } // end anonymous namespace. 7292 7293 namespace { 7294 // x86_32 Android target 7295 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7296 public: 7297 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7298 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7299 SuitableAlign = 32; 7300 LongDoubleWidth = 64; 7301 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7302 } 7303 }; 7304 } // end anonymous namespace 7305 7306 namespace { 7307 // x86_64 Android target 7308 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7309 public: 7310 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7311 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7312 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7313 } 7314 7315 bool useFloat128ManglingForLongDouble() const override { 7316 return true; 7317 } 7318 }; 7319 } // end anonymous namespace 7320 7321 7322 //===----------------------------------------------------------------------===// 7323 // Driver code 7324 //===----------------------------------------------------------------------===// 7325 7326 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7327 llvm::Triple::OSType os = Triple.getOS(); 7328 7329 switch (Triple.getArch()) { 7330 default: 7331 return nullptr; 7332 7333 case llvm::Triple::xcore: 7334 return new XCoreTargetInfo(Triple); 7335 7336 case llvm::Triple::hexagon: 7337 return new HexagonTargetInfo(Triple); 7338 7339 case llvm::Triple::aarch64: 7340 if (Triple.isOSDarwin()) 7341 return new DarwinAArch64TargetInfo(Triple); 7342 7343 switch (os) { 7344 case llvm::Triple::FreeBSD: 7345 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7346 case llvm::Triple::Linux: 7347 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7348 case llvm::Triple::NetBSD: 7349 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7350 default: 7351 return new AArch64leTargetInfo(Triple); 7352 } 7353 7354 case llvm::Triple::aarch64_be: 7355 switch (os) { 7356 case llvm::Triple::FreeBSD: 7357 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7358 case llvm::Triple::Linux: 7359 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7360 case llvm::Triple::NetBSD: 7361 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7362 default: 7363 return new AArch64beTargetInfo(Triple); 7364 } 7365 7366 case llvm::Triple::arm: 7367 case llvm::Triple::thumb: 7368 if (Triple.isOSBinFormatMachO()) 7369 return new DarwinARMTargetInfo(Triple); 7370 7371 switch (os) { 7372 case llvm::Triple::Linux: 7373 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7374 case llvm::Triple::FreeBSD: 7375 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7376 case llvm::Triple::NetBSD: 7377 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7378 case llvm::Triple::OpenBSD: 7379 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7380 case llvm::Triple::Bitrig: 7381 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7382 case llvm::Triple::RTEMS: 7383 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7384 case llvm::Triple::NaCl: 7385 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7386 case llvm::Triple::Win32: 7387 switch (Triple.getEnvironment()) { 7388 case llvm::Triple::Cygnus: 7389 return new CygwinARMTargetInfo(Triple); 7390 case llvm::Triple::GNU: 7391 return new MinGWARMTargetInfo(Triple); 7392 case llvm::Triple::Itanium: 7393 return new ItaniumWindowsARMleTargetInfo(Triple); 7394 case llvm::Triple::MSVC: 7395 default: // Assume MSVC for unknown environments 7396 return new MicrosoftARMleTargetInfo(Triple); 7397 } 7398 default: 7399 return new ARMleTargetInfo(Triple); 7400 } 7401 7402 case llvm::Triple::armeb: 7403 case llvm::Triple::thumbeb: 7404 if (Triple.isOSDarwin()) 7405 return new DarwinARMTargetInfo(Triple); 7406 7407 switch (os) { 7408 case llvm::Triple::Linux: 7409 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7410 case llvm::Triple::FreeBSD: 7411 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7412 case llvm::Triple::NetBSD: 7413 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7414 case llvm::Triple::OpenBSD: 7415 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7416 case llvm::Triple::Bitrig: 7417 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7418 case llvm::Triple::RTEMS: 7419 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7420 case llvm::Triple::NaCl: 7421 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7422 default: 7423 return new ARMbeTargetInfo(Triple); 7424 } 7425 7426 case llvm::Triple::bpfeb: 7427 case llvm::Triple::bpfel: 7428 return new BPFTargetInfo(Triple); 7429 7430 case llvm::Triple::msp430: 7431 return new MSP430TargetInfo(Triple); 7432 7433 case llvm::Triple::mips: 7434 switch (os) { 7435 case llvm::Triple::Linux: 7436 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7437 case llvm::Triple::RTEMS: 7438 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7439 case llvm::Triple::FreeBSD: 7440 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7441 case llvm::Triple::NetBSD: 7442 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7443 default: 7444 return new Mips32EBTargetInfo(Triple); 7445 } 7446 7447 case llvm::Triple::mipsel: 7448 switch (os) { 7449 case llvm::Triple::Linux: 7450 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7451 case llvm::Triple::RTEMS: 7452 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7453 case llvm::Triple::FreeBSD: 7454 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7455 case llvm::Triple::NetBSD: 7456 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7457 case llvm::Triple::NaCl: 7458 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7459 default: 7460 return new Mips32ELTargetInfo(Triple); 7461 } 7462 7463 case llvm::Triple::mips64: 7464 switch (os) { 7465 case llvm::Triple::Linux: 7466 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7467 case llvm::Triple::RTEMS: 7468 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7469 case llvm::Triple::FreeBSD: 7470 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7471 case llvm::Triple::NetBSD: 7472 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7473 case llvm::Triple::OpenBSD: 7474 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7475 default: 7476 return new Mips64EBTargetInfo(Triple); 7477 } 7478 7479 case llvm::Triple::mips64el: 7480 switch (os) { 7481 case llvm::Triple::Linux: 7482 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7483 case llvm::Triple::RTEMS: 7484 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7485 case llvm::Triple::FreeBSD: 7486 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7487 case llvm::Triple::NetBSD: 7488 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7489 case llvm::Triple::OpenBSD: 7490 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7491 default: 7492 return new Mips64ELTargetInfo(Triple); 7493 } 7494 7495 case llvm::Triple::le32: 7496 switch (os) { 7497 case llvm::Triple::NaCl: 7498 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7499 default: 7500 return nullptr; 7501 } 7502 7503 case llvm::Triple::le64: 7504 return new Le64TargetInfo(Triple); 7505 7506 case llvm::Triple::ppc: 7507 if (Triple.isOSDarwin()) 7508 return new DarwinPPC32TargetInfo(Triple); 7509 switch (os) { 7510 case llvm::Triple::Linux: 7511 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7512 case llvm::Triple::FreeBSD: 7513 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7514 case llvm::Triple::NetBSD: 7515 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7516 case llvm::Triple::OpenBSD: 7517 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7518 case llvm::Triple::RTEMS: 7519 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7520 default: 7521 return new PPC32TargetInfo(Triple); 7522 } 7523 7524 case llvm::Triple::ppc64: 7525 if (Triple.isOSDarwin()) 7526 return new DarwinPPC64TargetInfo(Triple); 7527 switch (os) { 7528 case llvm::Triple::Linux: 7529 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7530 case llvm::Triple::Lv2: 7531 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7532 case llvm::Triple::FreeBSD: 7533 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7534 case llvm::Triple::NetBSD: 7535 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7536 default: 7537 return new PPC64TargetInfo(Triple); 7538 } 7539 7540 case llvm::Triple::ppc64le: 7541 switch (os) { 7542 case llvm::Triple::Linux: 7543 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7544 case llvm::Triple::NetBSD: 7545 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7546 default: 7547 return new PPC64TargetInfo(Triple); 7548 } 7549 7550 case llvm::Triple::nvptx: 7551 return new NVPTX32TargetInfo(Triple); 7552 case llvm::Triple::nvptx64: 7553 return new NVPTX64TargetInfo(Triple); 7554 7555 case llvm::Triple::amdgcn: 7556 case llvm::Triple::r600: 7557 return new AMDGPUTargetInfo(Triple); 7558 7559 case llvm::Triple::sparc: 7560 switch (os) { 7561 case llvm::Triple::Linux: 7562 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7563 case llvm::Triple::Solaris: 7564 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7565 case llvm::Triple::NetBSD: 7566 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7567 case llvm::Triple::OpenBSD: 7568 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7569 case llvm::Triple::RTEMS: 7570 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7571 default: 7572 return new SparcV8TargetInfo(Triple); 7573 } 7574 7575 // The 'sparcel' architecture copies all the above cases except for Solaris. 7576 case llvm::Triple::sparcel: 7577 switch (os) { 7578 case llvm::Triple::Linux: 7579 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7580 case llvm::Triple::NetBSD: 7581 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7582 case llvm::Triple::OpenBSD: 7583 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7584 case llvm::Triple::RTEMS: 7585 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7586 default: 7587 return new SparcV8elTargetInfo(Triple); 7588 } 7589 7590 case llvm::Triple::sparcv9: 7591 switch (os) { 7592 case llvm::Triple::Linux: 7593 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7594 case llvm::Triple::Solaris: 7595 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7596 case llvm::Triple::NetBSD: 7597 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7598 case llvm::Triple::OpenBSD: 7599 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7600 case llvm::Triple::FreeBSD: 7601 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7602 default: 7603 return new SparcV9TargetInfo(Triple); 7604 } 7605 7606 case llvm::Triple::systemz: 7607 switch (os) { 7608 case llvm::Triple::Linux: 7609 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7610 default: 7611 return new SystemZTargetInfo(Triple); 7612 } 7613 7614 case llvm::Triple::tce: 7615 return new TCETargetInfo(Triple); 7616 7617 case llvm::Triple::x86: 7618 if (Triple.isOSDarwin()) 7619 return new DarwinI386TargetInfo(Triple); 7620 7621 switch (os) { 7622 case llvm::Triple::CloudABI: 7623 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7624 case llvm::Triple::Linux: { 7625 switch (Triple.getEnvironment()) { 7626 default: 7627 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7628 case llvm::Triple::Android: 7629 return new AndroidX86_32TargetInfo(Triple); 7630 } 7631 } 7632 case llvm::Triple::DragonFly: 7633 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7634 case llvm::Triple::NetBSD: 7635 return new NetBSDI386TargetInfo(Triple); 7636 case llvm::Triple::OpenBSD: 7637 return new OpenBSDI386TargetInfo(Triple); 7638 case llvm::Triple::Bitrig: 7639 return new BitrigI386TargetInfo(Triple); 7640 case llvm::Triple::FreeBSD: 7641 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7642 case llvm::Triple::KFreeBSD: 7643 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7644 case llvm::Triple::Minix: 7645 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7646 case llvm::Triple::Solaris: 7647 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7648 case llvm::Triple::Win32: { 7649 switch (Triple.getEnvironment()) { 7650 case llvm::Triple::Cygnus: 7651 return new CygwinX86_32TargetInfo(Triple); 7652 case llvm::Triple::GNU: 7653 return new MinGWX86_32TargetInfo(Triple); 7654 case llvm::Triple::Itanium: 7655 case llvm::Triple::MSVC: 7656 default: // Assume MSVC for unknown environments 7657 return new MicrosoftX86_32TargetInfo(Triple); 7658 } 7659 } 7660 case llvm::Triple::Haiku: 7661 return new HaikuX86_32TargetInfo(Triple); 7662 case llvm::Triple::RTEMS: 7663 return new RTEMSX86_32TargetInfo(Triple); 7664 case llvm::Triple::NaCl: 7665 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7666 default: 7667 return new X86_32TargetInfo(Triple); 7668 } 7669 7670 case llvm::Triple::x86_64: 7671 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7672 return new DarwinX86_64TargetInfo(Triple); 7673 7674 switch (os) { 7675 case llvm::Triple::CloudABI: 7676 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7677 case llvm::Triple::Linux: { 7678 switch (Triple.getEnvironment()) { 7679 default: 7680 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7681 case llvm::Triple::Android: 7682 return new AndroidX86_64TargetInfo(Triple); 7683 } 7684 } 7685 case llvm::Triple::DragonFly: 7686 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7687 case llvm::Triple::NetBSD: 7688 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7689 case llvm::Triple::OpenBSD: 7690 return new OpenBSDX86_64TargetInfo(Triple); 7691 case llvm::Triple::Bitrig: 7692 return new BitrigX86_64TargetInfo(Triple); 7693 case llvm::Triple::FreeBSD: 7694 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7695 case llvm::Triple::KFreeBSD: 7696 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7697 case llvm::Triple::Solaris: 7698 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7699 case llvm::Triple::Win32: { 7700 switch (Triple.getEnvironment()) { 7701 case llvm::Triple::Cygnus: 7702 return new CygwinX86_64TargetInfo(Triple); 7703 case llvm::Triple::GNU: 7704 return new MinGWX86_64TargetInfo(Triple); 7705 case llvm::Triple::MSVC: 7706 default: // Assume MSVC for unknown environments 7707 return new MicrosoftX86_64TargetInfo(Triple); 7708 } 7709 } 7710 case llvm::Triple::NaCl: 7711 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7712 case llvm::Triple::PS4: 7713 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7714 default: 7715 return new X86_64TargetInfo(Triple); 7716 } 7717 7718 case llvm::Triple::spir: { 7719 if (Triple.getOS() != llvm::Triple::UnknownOS || 7720 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7721 return nullptr; 7722 return new SPIR32TargetInfo(Triple); 7723 } 7724 case llvm::Triple::spir64: { 7725 if (Triple.getOS() != llvm::Triple::UnknownOS || 7726 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7727 return nullptr; 7728 return new SPIR64TargetInfo(Triple); 7729 } 7730 case llvm::Triple::wasm32: 7731 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7732 return nullptr; 7733 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7734 case llvm::Triple::wasm64: 7735 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7736 return nullptr; 7737 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7738 } 7739 } 7740 7741 /// CreateTargetInfo - Return the target info object for the specified target 7742 /// options. 7743 TargetInfo * 7744 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7745 const std::shared_ptr<TargetOptions> &Opts) { 7746 llvm::Triple Triple(Opts->Triple); 7747 7748 // Construct the target 7749 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7750 if (!Target) { 7751 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7752 return nullptr; 7753 } 7754 Target->TargetOpts = Opts; 7755 7756 // Set the target CPU if specified. 7757 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7758 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7759 return nullptr; 7760 } 7761 7762 // Set the target ABI if specified. 7763 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7764 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7765 return nullptr; 7766 } 7767 7768 // Set the fp math unit. 7769 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7770 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7771 return nullptr; 7772 } 7773 7774 // Compute the default target features, we need the target to handle this 7775 // because features may have dependencies on one another. 7776 llvm::StringMap<bool> Features; 7777 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7778 Opts->FeaturesAsWritten)) 7779 return nullptr; 7780 7781 // Add the features to the compile options. 7782 Opts->Features.clear(); 7783 for (const auto &F : Features) 7784 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7785 7786 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7787 return nullptr; 7788 7789 return Target.release(); 7790 } 7791