1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasAltivec; 892 bool HasVSX; 893 bool HasP8Vector; 894 bool HasP8Crypto; 895 bool HasDirectMove; 896 bool HasQPX; 897 bool HasHTM; 898 bool HasBPERMD; 899 bool HasExtDiv; 900 bool HasP9Vector; 901 902 protected: 903 std::string ABI; 904 905 public: 906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 910 SuitableAlign = 128; 911 SimdDefaultAlign = 128; 912 LongDoubleWidth = LongDoubleAlign = 128; 913 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 914 } 915 916 /// \brief Flags for architecture specific defines. 917 typedef enum { 918 ArchDefineNone = 0, 919 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 920 ArchDefinePpcgr = 1 << 1, 921 ArchDefinePpcsq = 1 << 2, 922 ArchDefine440 = 1 << 3, 923 ArchDefine603 = 1 << 4, 924 ArchDefine604 = 1 << 5, 925 ArchDefinePwr4 = 1 << 6, 926 ArchDefinePwr5 = 1 << 7, 927 ArchDefinePwr5x = 1 << 8, 928 ArchDefinePwr6 = 1 << 9, 929 ArchDefinePwr6x = 1 << 10, 930 ArchDefinePwr7 = 1 << 11, 931 ArchDefinePwr8 = 1 << 12, 932 ArchDefinePwr9 = 1 << 13, 933 ArchDefineA2 = 1 << 14, 934 ArchDefineA2q = 1 << 15 935 } ArchDefineTypes; 936 937 // Set the language option for altivec based on our value. 938 void adjust(LangOptions &Opts) override { 939 if (HasAltivec) 940 Opts.AltiVec = 1; 941 TargetInfo::adjust(Opts); 942 } 943 944 // Note: GCC recognizes the following additional cpus: 945 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 946 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 947 // titan, rs64. 948 bool setCPU(const std::string &Name) override { 949 bool CPUKnown = llvm::StringSwitch<bool>(Name) 950 .Case("generic", true) 951 .Case("440", true) 952 .Case("450", true) 953 .Case("601", true) 954 .Case("602", true) 955 .Case("603", true) 956 .Case("603e", true) 957 .Case("603ev", true) 958 .Case("604", true) 959 .Case("604e", true) 960 .Case("620", true) 961 .Case("630", true) 962 .Case("g3", true) 963 .Case("7400", true) 964 .Case("g4", true) 965 .Case("7450", true) 966 .Case("g4+", true) 967 .Case("750", true) 968 .Case("970", true) 969 .Case("g5", true) 970 .Case("a2", true) 971 .Case("a2q", true) 972 .Case("e500mc", true) 973 .Case("e5500", true) 974 .Case("power3", true) 975 .Case("pwr3", true) 976 .Case("power4", true) 977 .Case("pwr4", true) 978 .Case("power5", true) 979 .Case("pwr5", true) 980 .Case("power5x", true) 981 .Case("pwr5x", true) 982 .Case("power6", true) 983 .Case("pwr6", true) 984 .Case("power6x", true) 985 .Case("pwr6x", true) 986 .Case("power7", true) 987 .Case("pwr7", true) 988 .Case("power8", true) 989 .Case("pwr8", true) 990 .Case("power9", true) 991 .Case("pwr9", true) 992 .Case("powerpc", true) 993 .Case("ppc", true) 994 .Case("powerpc64", true) 995 .Case("ppc64", true) 996 .Case("powerpc64le", true) 997 .Case("ppc64le", true) 998 .Default(false); 999 1000 if (CPUKnown) 1001 CPU = Name; 1002 1003 return CPUKnown; 1004 } 1005 1006 1007 StringRef getABI() const override { return ABI; } 1008 1009 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1010 return llvm::makeArrayRef(BuiltinInfo, 1011 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1012 } 1013 1014 bool isCLZForZeroUndef() const override { return false; } 1015 1016 void getTargetDefines(const LangOptions &Opts, 1017 MacroBuilder &Builder) const override; 1018 1019 bool 1020 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1021 StringRef CPU, 1022 const std::vector<std::string> &FeaturesVec) const override; 1023 1024 bool handleTargetFeatures(std::vector<std::string> &Features, 1025 DiagnosticsEngine &Diags) override; 1026 bool hasFeature(StringRef Feature) const override; 1027 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1028 bool Enabled) const override; 1029 1030 ArrayRef<const char *> getGCCRegNames() const override; 1031 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1032 bool validateAsmConstraint(const char *&Name, 1033 TargetInfo::ConstraintInfo &Info) const override { 1034 switch (*Name) { 1035 default: return false; 1036 case 'O': // Zero 1037 break; 1038 case 'b': // Base register 1039 case 'f': // Floating point register 1040 Info.setAllowsRegister(); 1041 break; 1042 // FIXME: The following are added to allow parsing. 1043 // I just took a guess at what the actions should be. 1044 // Also, is more specific checking needed? I.e. specific registers? 1045 case 'd': // Floating point register (containing 64-bit value) 1046 case 'v': // Altivec vector register 1047 Info.setAllowsRegister(); 1048 break; 1049 case 'w': 1050 switch (Name[1]) { 1051 case 'd':// VSX vector register to hold vector double data 1052 case 'f':// VSX vector register to hold vector float data 1053 case 's':// VSX vector register to hold scalar float data 1054 case 'a':// Any VSX register 1055 case 'c':// An individual CR bit 1056 break; 1057 default: 1058 return false; 1059 } 1060 Info.setAllowsRegister(); 1061 Name++; // Skip over 'w'. 1062 break; 1063 case 'h': // `MQ', `CTR', or `LINK' register 1064 case 'q': // `MQ' register 1065 case 'c': // `CTR' register 1066 case 'l': // `LINK' register 1067 case 'x': // `CR' register (condition register) number 0 1068 case 'y': // `CR' register (condition register) 1069 case 'z': // `XER[CA]' carry bit (part of the XER register) 1070 Info.setAllowsRegister(); 1071 break; 1072 case 'I': // Signed 16-bit constant 1073 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1074 // (use `L' instead for SImode constants) 1075 case 'K': // Unsigned 16-bit constant 1076 case 'L': // Signed 16-bit constant shifted left 16 bits 1077 case 'M': // Constant larger than 31 1078 case 'N': // Exact power of 2 1079 case 'P': // Constant whose negation is a signed 16-bit constant 1080 case 'G': // Floating point constant that can be loaded into a 1081 // register with one instruction per word 1082 case 'H': // Integer/Floating point constant that can be loaded 1083 // into a register using three instructions 1084 break; 1085 case 'm': // Memory operand. Note that on PowerPC targets, m can 1086 // include addresses that update the base register. It 1087 // is therefore only safe to use `m' in an asm statement 1088 // if that asm statement accesses the operand exactly once. 1089 // The asm statement must also use `%U<opno>' as a 1090 // placeholder for the "update" flag in the corresponding 1091 // load or store instruction. For example: 1092 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1093 // is correct but: 1094 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1095 // is not. Use es rather than m if you don't want the base 1096 // register to be updated. 1097 case 'e': 1098 if (Name[1] != 's') 1099 return false; 1100 // es: A "stable" memory operand; that is, one which does not 1101 // include any automodification of the base register. Unlike 1102 // `m', this constraint can be used in asm statements that 1103 // might access the operand several times, or that might not 1104 // access it at all. 1105 Info.setAllowsMemory(); 1106 Name++; // Skip over 'e'. 1107 break; 1108 case 'Q': // Memory operand that is an offset from a register (it is 1109 // usually better to use `m' or `es' in asm statements) 1110 case 'Z': // Memory operand that is an indexed or indirect from a 1111 // register (it is usually better to use `m' or `es' in 1112 // asm statements) 1113 Info.setAllowsMemory(); 1114 Info.setAllowsRegister(); 1115 break; 1116 case 'R': // AIX TOC entry 1117 case 'a': // Address operand that is an indexed or indirect from a 1118 // register (`p' is preferable for asm statements) 1119 case 'S': // Constant suitable as a 64-bit mask operand 1120 case 'T': // Constant suitable as a 32-bit mask operand 1121 case 'U': // System V Release 4 small data area reference 1122 case 't': // AND masks that can be performed by two rldic{l, r} 1123 // instructions 1124 case 'W': // Vector constant that does not require memory 1125 case 'j': // Vector constant that is all zeros. 1126 break; 1127 // End FIXME. 1128 } 1129 return true; 1130 } 1131 std::string convertConstraint(const char *&Constraint) const override { 1132 std::string R; 1133 switch (*Constraint) { 1134 case 'e': 1135 case 'w': 1136 // Two-character constraint; add "^" hint for later parsing. 1137 R = std::string("^") + std::string(Constraint, 2); 1138 Constraint++; 1139 break; 1140 default: 1141 return TargetInfo::convertConstraint(Constraint); 1142 } 1143 return R; 1144 } 1145 const char *getClobbers() const override { 1146 return ""; 1147 } 1148 int getEHDataRegisterNumber(unsigned RegNo) const override { 1149 if (RegNo == 0) return 3; 1150 if (RegNo == 1) return 4; 1151 return -1; 1152 } 1153 1154 bool hasSjLjLowering() const override { 1155 return true; 1156 } 1157 1158 bool useFloat128ManglingForLongDouble() const override { 1159 return LongDoubleWidth == 128 && 1160 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1161 getTriple().isOSBinFormatELF(); 1162 } 1163 }; 1164 1165 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1166 #define BUILTIN(ID, TYPE, ATTRS) \ 1167 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1168 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1169 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1170 #include "clang/Basic/BuiltinsPPC.def" 1171 }; 1172 1173 /// handleTargetFeatures - Perform initialization based on the user 1174 /// configured set of features. 1175 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1176 DiagnosticsEngine &Diags) { 1177 for (const auto &Feature : Features) { 1178 if (Feature == "+altivec") { 1179 HasAltivec = true; 1180 } else if (Feature == "+vsx") { 1181 HasVSX = true; 1182 } else if (Feature == "+bpermd") { 1183 HasBPERMD = true; 1184 } else if (Feature == "+extdiv") { 1185 HasExtDiv = true; 1186 } else if (Feature == "+power8-vector") { 1187 HasP8Vector = true; 1188 } else if (Feature == "+crypto") { 1189 HasP8Crypto = true; 1190 } else if (Feature == "+direct-move") { 1191 HasDirectMove = true; 1192 } else if (Feature == "+qpx") { 1193 HasQPX = true; 1194 } else if (Feature == "+htm") { 1195 HasHTM = true; 1196 } else if (Feature == "+float128") { 1197 HasFloat128 = true; 1198 } else if (Feature == "+power9-vector") { 1199 HasP9Vector = true; 1200 } 1201 // TODO: Finish this list and add an assert that we've handled them 1202 // all. 1203 } 1204 1205 return true; 1206 } 1207 1208 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1209 /// #defines that are not tied to a specific subtarget. 1210 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1211 MacroBuilder &Builder) const { 1212 // Target identification. 1213 Builder.defineMacro("__ppc__"); 1214 Builder.defineMacro("__PPC__"); 1215 Builder.defineMacro("_ARCH_PPC"); 1216 Builder.defineMacro("__powerpc__"); 1217 Builder.defineMacro("__POWERPC__"); 1218 if (PointerWidth == 64) { 1219 Builder.defineMacro("_ARCH_PPC64"); 1220 Builder.defineMacro("__powerpc64__"); 1221 Builder.defineMacro("__ppc64__"); 1222 Builder.defineMacro("__PPC64__"); 1223 } 1224 1225 // Target properties. 1226 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1227 Builder.defineMacro("_LITTLE_ENDIAN"); 1228 } else { 1229 if (getTriple().getOS() != llvm::Triple::NetBSD && 1230 getTriple().getOS() != llvm::Triple::OpenBSD) 1231 Builder.defineMacro("_BIG_ENDIAN"); 1232 } 1233 1234 // ABI options. 1235 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1236 Builder.defineMacro("_CALL_ELF", "1"); 1237 if (ABI == "elfv2") 1238 Builder.defineMacro("_CALL_ELF", "2"); 1239 1240 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1241 // our suppport post-dates this and it should work on all 64-bit ppc linux 1242 // platforms. It is guaranteed to work on all elfv2 platforms. 1243 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1244 Builder.defineMacro("_CALL_LINUX", "1"); 1245 1246 // Subtarget options. 1247 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1248 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1249 1250 // FIXME: Should be controlled by command line option. 1251 if (LongDoubleWidth == 128) { 1252 Builder.defineMacro("__LONG_DOUBLE_128__"); 1253 Builder.defineMacro("__LONGDOUBLE128"); 1254 } 1255 1256 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1257 if (ABI == "elfv2" || 1258 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1259 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1260 1261 // CPU identification. 1262 ArchDefineTypes defs = 1263 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1264 .Case("440", ArchDefineName) 1265 .Case("450", ArchDefineName | ArchDefine440) 1266 .Case("601", ArchDefineName) 1267 .Case("602", ArchDefineName | ArchDefinePpcgr) 1268 .Case("603", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1270 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("604", ArchDefineName | ArchDefinePpcgr) 1272 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1273 .Case("620", ArchDefineName | ArchDefinePpcgr) 1274 .Case("630", ArchDefineName | ArchDefinePpcgr) 1275 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1277 .Case("750", ArchDefineName | ArchDefinePpcgr) 1278 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1279 ArchDefinePpcsq) 1280 .Case("a2", ArchDefineA2) 1281 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1282 .Case("pwr3", ArchDefinePpcgr) 1283 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1284 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1285 ArchDefinePpcsq) 1286 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1287 ArchDefinePpcgr | ArchDefinePpcsq) 1288 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1289 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1290 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1291 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1292 ArchDefinePpcsq) 1293 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1294 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1295 ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1297 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1298 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1299 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1300 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1301 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1302 ArchDefinePpcsq) 1303 .Case("power3", ArchDefinePpcgr) 1304 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1305 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1306 ArchDefinePpcsq) 1307 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1308 ArchDefinePpcgr | ArchDefinePpcsq) 1309 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1310 ArchDefinePwr4 | ArchDefinePpcgr | 1311 ArchDefinePpcsq) 1312 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1313 ArchDefinePwr5 | ArchDefinePwr4 | 1314 ArchDefinePpcgr | ArchDefinePpcsq) 1315 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1316 ArchDefinePwr5x | ArchDefinePwr5 | 1317 ArchDefinePwr4 | ArchDefinePpcgr | 1318 ArchDefinePpcsq) 1319 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1320 ArchDefinePwr6 | ArchDefinePwr5x | 1321 ArchDefinePwr5 | ArchDefinePwr4 | 1322 ArchDefinePpcgr | ArchDefinePpcsq) 1323 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1324 ArchDefinePwr6x | ArchDefinePwr6 | 1325 ArchDefinePwr5x | ArchDefinePwr5 | 1326 ArchDefinePwr4 | ArchDefinePpcgr | 1327 ArchDefinePpcsq) 1328 // powerpc64le automatically defaults to at least power8. 1329 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1330 ArchDefinePwr6 | ArchDefinePwr5x | 1331 ArchDefinePwr5 | ArchDefinePwr4 | 1332 ArchDefinePpcgr | ArchDefinePpcsq) 1333 .Default(ArchDefineNone); 1334 1335 if (defs & ArchDefineName) 1336 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1337 if (defs & ArchDefinePpcgr) 1338 Builder.defineMacro("_ARCH_PPCGR"); 1339 if (defs & ArchDefinePpcsq) 1340 Builder.defineMacro("_ARCH_PPCSQ"); 1341 if (defs & ArchDefine440) 1342 Builder.defineMacro("_ARCH_440"); 1343 if (defs & ArchDefine603) 1344 Builder.defineMacro("_ARCH_603"); 1345 if (defs & ArchDefine604) 1346 Builder.defineMacro("_ARCH_604"); 1347 if (defs & ArchDefinePwr4) 1348 Builder.defineMacro("_ARCH_PWR4"); 1349 if (defs & ArchDefinePwr5) 1350 Builder.defineMacro("_ARCH_PWR5"); 1351 if (defs & ArchDefinePwr5x) 1352 Builder.defineMacro("_ARCH_PWR5X"); 1353 if (defs & ArchDefinePwr6) 1354 Builder.defineMacro("_ARCH_PWR6"); 1355 if (defs & ArchDefinePwr6x) 1356 Builder.defineMacro("_ARCH_PWR6X"); 1357 if (defs & ArchDefinePwr7) 1358 Builder.defineMacro("_ARCH_PWR7"); 1359 if (defs & ArchDefinePwr8) 1360 Builder.defineMacro("_ARCH_PWR8"); 1361 if (defs & ArchDefinePwr9) 1362 Builder.defineMacro("_ARCH_PWR9"); 1363 if (defs & ArchDefineA2) 1364 Builder.defineMacro("_ARCH_A2"); 1365 if (defs & ArchDefineA2q) { 1366 Builder.defineMacro("_ARCH_A2Q"); 1367 Builder.defineMacro("_ARCH_QP"); 1368 } 1369 1370 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1371 Builder.defineMacro("__bg__"); 1372 Builder.defineMacro("__THW_BLUEGENE__"); 1373 Builder.defineMacro("__bgq__"); 1374 Builder.defineMacro("__TOS_BGQ__"); 1375 } 1376 1377 if (HasAltivec) { 1378 Builder.defineMacro("__VEC__", "10206"); 1379 Builder.defineMacro("__ALTIVEC__"); 1380 } 1381 if (HasVSX) 1382 Builder.defineMacro("__VSX__"); 1383 if (HasP8Vector) 1384 Builder.defineMacro("__POWER8_VECTOR__"); 1385 if (HasP8Crypto) 1386 Builder.defineMacro("__CRYPTO__"); 1387 if (HasHTM) 1388 Builder.defineMacro("__HTM__"); 1389 if (HasFloat128) 1390 Builder.defineMacro("__FLOAT128__"); 1391 if (HasP9Vector) 1392 Builder.defineMacro("__POWER9_VECTOR__"); 1393 1394 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1397 if (PointerWidth == 64) 1398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1399 1400 // We have support for the bswap intrinsics so we can define this. 1401 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1402 1403 // FIXME: The following are not yet generated here by Clang, but are 1404 // generated by GCC: 1405 // 1406 // _SOFT_FLOAT_ 1407 // __RECIP_PRECISION__ 1408 // __APPLE_ALTIVEC__ 1409 // __RECIP__ 1410 // __RECIPF__ 1411 // __RSQRTE__ 1412 // __RSQRTEF__ 1413 // _SOFT_DOUBLE_ 1414 // __NO_LWSYNC__ 1415 // __CMODEL_MEDIUM__ 1416 // __CMODEL_LARGE__ 1417 // _CALL_SYSV 1418 // _CALL_DARWIN 1419 // __NO_FPRS__ 1420 } 1421 1422 // Handle explicit options being passed to the compiler here: if we've 1423 // explicitly turned off vsx and turned on any of: 1424 // - power8-vector 1425 // - direct-move 1426 // - float128 1427 // - power9-vector 1428 // then go ahead and error since the customer has expressed an incompatible 1429 // set of options. 1430 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1431 const std::vector<std::string> &FeaturesVec) { 1432 1433 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1434 FeaturesVec.end()) { 1435 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1436 FeaturesVec.end()) { 1437 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1438 << "-mno-vsx"; 1439 return false; 1440 } 1441 1442 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1443 FeaturesVec.end()) { 1444 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1445 << "-mno-vsx"; 1446 return false; 1447 } 1448 1449 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1450 FeaturesVec.end()) { 1451 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1452 << "-mno-vsx"; 1453 return false; 1454 } 1455 1456 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1457 FeaturesVec.end()) { 1458 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1459 << "-mno-vsx"; 1460 return false; 1461 } 1462 } 1463 1464 return true; 1465 } 1466 1467 bool PPCTargetInfo::initFeatureMap( 1468 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1469 const std::vector<std::string> &FeaturesVec) const { 1470 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1471 .Case("7400", true) 1472 .Case("g4", true) 1473 .Case("7450", true) 1474 .Case("g4+", true) 1475 .Case("970", true) 1476 .Case("g5", true) 1477 .Case("pwr6", true) 1478 .Case("pwr7", true) 1479 .Case("pwr8", true) 1480 .Case("pwr9", true) 1481 .Case("ppc64", true) 1482 .Case("ppc64le", true) 1483 .Default(false); 1484 1485 Features["qpx"] = (CPU == "a2q"); 1486 Features["power9-vector"] = (CPU == "pwr9"); 1487 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1488 .Case("ppc64le", true) 1489 .Case("pwr9", true) 1490 .Case("pwr8", true) 1491 .Default(false); 1492 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1493 .Case("ppc64le", true) 1494 .Case("pwr9", true) 1495 .Case("pwr8", true) 1496 .Default(false); 1497 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1498 .Case("ppc64le", true) 1499 .Case("pwr9", true) 1500 .Case("pwr8", true) 1501 .Case("pwr7", true) 1502 .Default(false); 1503 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1504 .Case("ppc64le", true) 1505 .Case("pwr9", true) 1506 .Case("pwr8", true) 1507 .Case("pwr7", true) 1508 .Default(false); 1509 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1510 .Case("ppc64le", true) 1511 .Case("pwr9", true) 1512 .Case("pwr8", true) 1513 .Default(false); 1514 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1515 .Case("ppc64le", true) 1516 .Case("pwr9", true) 1517 .Case("pwr8", true) 1518 .Case("pwr7", true) 1519 .Default(false); 1520 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1521 .Case("ppc64le", true) 1522 .Case("pwr9", true) 1523 .Case("pwr8", true) 1524 .Default(false); 1525 1526 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1527 return false; 1528 1529 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1530 } 1531 1532 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1533 return llvm::StringSwitch<bool>(Feature) 1534 .Case("powerpc", true) 1535 .Case("altivec", HasAltivec) 1536 .Case("vsx", HasVSX) 1537 .Case("power8-vector", HasP8Vector) 1538 .Case("crypto", HasP8Crypto) 1539 .Case("direct-move", HasDirectMove) 1540 .Case("qpx", HasQPX) 1541 .Case("htm", HasHTM) 1542 .Case("bpermd", HasBPERMD) 1543 .Case("extdiv", HasExtDiv) 1544 .Case("float128", HasFloat128) 1545 .Case("power9-vector", HasP9Vector) 1546 .Default(false); 1547 } 1548 1549 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1550 StringRef Name, bool Enabled) const { 1551 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1552 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1553 // incompatible options. 1554 if (Enabled) { 1555 if (Name == "direct-move" || 1556 Name == "power8-vector" || 1557 Name == "float128" || 1558 Name == "power9-vector") { 1559 // power9-vector is really a superset of power8-vector so encode that. 1560 Features[Name] = Features["vsx"] = true; 1561 if (Name == "power9-vector") 1562 Features["power8-vector"] = true; 1563 } else { 1564 Features[Name] = true; 1565 } 1566 } else { 1567 if (Name == "vsx") { 1568 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1569 Features["float128"] = Features["power9-vector"] = false; 1570 } else { 1571 Features[Name] = false; 1572 } 1573 } 1574 } 1575 1576 const char * const PPCTargetInfo::GCCRegNames[] = { 1577 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1578 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1579 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1580 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1581 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1582 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1583 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1584 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1585 "mq", "lr", "ctr", "ap", 1586 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1587 "xer", 1588 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1589 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1590 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1591 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1592 "vrsave", "vscr", 1593 "spe_acc", "spefscr", 1594 "sfp" 1595 }; 1596 1597 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1598 return llvm::makeArrayRef(GCCRegNames); 1599 } 1600 1601 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1602 // While some of these aliases do map to different registers 1603 // they still share the same register name. 1604 { { "0" }, "r0" }, 1605 { { "1"}, "r1" }, 1606 { { "2" }, "r2" }, 1607 { { "3" }, "r3" }, 1608 { { "4" }, "r4" }, 1609 { { "5" }, "r5" }, 1610 { { "6" }, "r6" }, 1611 { { "7" }, "r7" }, 1612 { { "8" }, "r8" }, 1613 { { "9" }, "r9" }, 1614 { { "10" }, "r10" }, 1615 { { "11" }, "r11" }, 1616 { { "12" }, "r12" }, 1617 { { "13" }, "r13" }, 1618 { { "14" }, "r14" }, 1619 { { "15" }, "r15" }, 1620 { { "16" }, "r16" }, 1621 { { "17" }, "r17" }, 1622 { { "18" }, "r18" }, 1623 { { "19" }, "r19" }, 1624 { { "20" }, "r20" }, 1625 { { "21" }, "r21" }, 1626 { { "22" }, "r22" }, 1627 { { "23" }, "r23" }, 1628 { { "24" }, "r24" }, 1629 { { "25" }, "r25" }, 1630 { { "26" }, "r26" }, 1631 { { "27" }, "r27" }, 1632 { { "28" }, "r28" }, 1633 { { "29" }, "r29" }, 1634 { { "30" }, "r30" }, 1635 { { "31" }, "r31" }, 1636 { { "fr0" }, "f0" }, 1637 { { "fr1" }, "f1" }, 1638 { { "fr2" }, "f2" }, 1639 { { "fr3" }, "f3" }, 1640 { { "fr4" }, "f4" }, 1641 { { "fr5" }, "f5" }, 1642 { { "fr6" }, "f6" }, 1643 { { "fr7" }, "f7" }, 1644 { { "fr8" }, "f8" }, 1645 { { "fr9" }, "f9" }, 1646 { { "fr10" }, "f10" }, 1647 { { "fr11" }, "f11" }, 1648 { { "fr12" }, "f12" }, 1649 { { "fr13" }, "f13" }, 1650 { { "fr14" }, "f14" }, 1651 { { "fr15" }, "f15" }, 1652 { { "fr16" }, "f16" }, 1653 { { "fr17" }, "f17" }, 1654 { { "fr18" }, "f18" }, 1655 { { "fr19" }, "f19" }, 1656 { { "fr20" }, "f20" }, 1657 { { "fr21" }, "f21" }, 1658 { { "fr22" }, "f22" }, 1659 { { "fr23" }, "f23" }, 1660 { { "fr24" }, "f24" }, 1661 { { "fr25" }, "f25" }, 1662 { { "fr26" }, "f26" }, 1663 { { "fr27" }, "f27" }, 1664 { { "fr28" }, "f28" }, 1665 { { "fr29" }, "f29" }, 1666 { { "fr30" }, "f30" }, 1667 { { "fr31" }, "f31" }, 1668 { { "cc" }, "cr0" }, 1669 }; 1670 1671 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1672 return llvm::makeArrayRef(GCCRegAliases); 1673 } 1674 1675 class PPC32TargetInfo : public PPCTargetInfo { 1676 public: 1677 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1678 : PPCTargetInfo(Triple, Opts) { 1679 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1680 1681 switch (getTriple().getOS()) { 1682 case llvm::Triple::Linux: 1683 case llvm::Triple::FreeBSD: 1684 case llvm::Triple::NetBSD: 1685 SizeType = UnsignedInt; 1686 PtrDiffType = SignedInt; 1687 IntPtrType = SignedInt; 1688 break; 1689 default: 1690 break; 1691 } 1692 1693 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1694 LongDoubleWidth = LongDoubleAlign = 64; 1695 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1696 } 1697 1698 // PPC32 supports atomics up to 4 bytes. 1699 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1700 } 1701 1702 BuiltinVaListKind getBuiltinVaListKind() const override { 1703 // This is the ELF definition, and is overridden by the Darwin sub-target 1704 return TargetInfo::PowerABIBuiltinVaList; 1705 } 1706 }; 1707 1708 // Note: ABI differences may eventually require us to have a separate 1709 // TargetInfo for little endian. 1710 class PPC64TargetInfo : public PPCTargetInfo { 1711 public: 1712 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1713 : PPCTargetInfo(Triple, Opts) { 1714 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1715 IntMaxType = SignedLong; 1716 Int64Type = SignedLong; 1717 1718 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1719 resetDataLayout("e-m:e-i64:64-n32:64"); 1720 ABI = "elfv2"; 1721 } else { 1722 resetDataLayout("E-m:e-i64:64-n32:64"); 1723 ABI = "elfv1"; 1724 } 1725 1726 switch (getTriple().getOS()) { 1727 case llvm::Triple::FreeBSD: 1728 LongDoubleWidth = LongDoubleAlign = 64; 1729 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1730 break; 1731 case llvm::Triple::NetBSD: 1732 IntMaxType = SignedLongLong; 1733 Int64Type = SignedLongLong; 1734 break; 1735 default: 1736 break; 1737 } 1738 1739 // PPC64 supports atomics up to 8 bytes. 1740 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1741 } 1742 BuiltinVaListKind getBuiltinVaListKind() const override { 1743 return TargetInfo::CharPtrBuiltinVaList; 1744 } 1745 // PPC64 Linux-specific ABI options. 1746 bool setABI(const std::string &Name) override { 1747 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1748 ABI = Name; 1749 return true; 1750 } 1751 return false; 1752 } 1753 }; 1754 1755 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1756 public: 1757 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1758 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1759 HasAlignMac68kSupport = true; 1760 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1761 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1762 LongLongAlign = 32; 1763 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1764 } 1765 BuiltinVaListKind getBuiltinVaListKind() const override { 1766 return TargetInfo::CharPtrBuiltinVaList; 1767 } 1768 }; 1769 1770 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1771 public: 1772 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1773 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1774 HasAlignMac68kSupport = true; 1775 resetDataLayout("E-m:o-i64:64-n32:64"); 1776 } 1777 }; 1778 1779 static const unsigned NVPTXAddrSpaceMap[] = { 1780 1, // opencl_global 1781 3, // opencl_local 1782 4, // opencl_constant 1783 // FIXME: generic has to be added to the target 1784 0, // opencl_generic 1785 1, // cuda_device 1786 4, // cuda_constant 1787 3, // cuda_shared 1788 }; 1789 1790 class NVPTXTargetInfo : public TargetInfo { 1791 static const char *const GCCRegNames[]; 1792 static const Builtin::Info BuiltinInfo[]; 1793 CudaArch GPU; 1794 std::unique_ptr<TargetInfo> HostTarget; 1795 1796 public: 1797 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1798 unsigned TargetPointerWidth) 1799 : TargetInfo(Triple) { 1800 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1801 "NVPTX only supports 32- and 64-bit modes."); 1802 1803 TLSSupported = false; 1804 AddrSpaceMap = &NVPTXAddrSpaceMap; 1805 UseAddrSpaceMapMangling = true; 1806 1807 // Define available target features 1808 // These must be defined in sorted order! 1809 NoAsmVariants = true; 1810 GPU = CudaArch::SM_20; 1811 1812 if (TargetPointerWidth == 32) 1813 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1814 else 1815 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1816 1817 // If possible, get a TargetInfo for our host triple, so we can match its 1818 // types. 1819 llvm::Triple HostTriple(Opts.HostTriple); 1820 if (!HostTriple.isNVPTX()) 1821 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1822 1823 // If no host target, make some guesses about the data layout and return. 1824 if (!HostTarget) { 1825 LongWidth = LongAlign = TargetPointerWidth; 1826 PointerWidth = PointerAlign = TargetPointerWidth; 1827 switch (TargetPointerWidth) { 1828 case 32: 1829 SizeType = TargetInfo::UnsignedInt; 1830 PtrDiffType = TargetInfo::SignedInt; 1831 IntPtrType = TargetInfo::SignedInt; 1832 break; 1833 case 64: 1834 SizeType = TargetInfo::UnsignedLong; 1835 PtrDiffType = TargetInfo::SignedLong; 1836 IntPtrType = TargetInfo::SignedLong; 1837 break; 1838 default: 1839 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1840 } 1841 return; 1842 } 1843 1844 // Copy properties from host target. 1845 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1846 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1847 BoolWidth = HostTarget->getBoolWidth(); 1848 BoolAlign = HostTarget->getBoolAlign(); 1849 IntWidth = HostTarget->getIntWidth(); 1850 IntAlign = HostTarget->getIntAlign(); 1851 HalfWidth = HostTarget->getHalfWidth(); 1852 HalfAlign = HostTarget->getHalfAlign(); 1853 FloatWidth = HostTarget->getFloatWidth(); 1854 FloatAlign = HostTarget->getFloatAlign(); 1855 DoubleWidth = HostTarget->getDoubleWidth(); 1856 DoubleAlign = HostTarget->getDoubleAlign(); 1857 LongWidth = HostTarget->getLongWidth(); 1858 LongAlign = HostTarget->getLongAlign(); 1859 LongLongWidth = HostTarget->getLongLongWidth(); 1860 LongLongAlign = HostTarget->getLongLongAlign(); 1861 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1862 NewAlign = HostTarget->getNewAlign(); 1863 DefaultAlignForAttributeAligned = 1864 HostTarget->getDefaultAlignForAttributeAligned(); 1865 SizeType = HostTarget->getSizeType(); 1866 IntMaxType = HostTarget->getIntMaxType(); 1867 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1868 IntPtrType = HostTarget->getIntPtrType(); 1869 WCharType = HostTarget->getWCharType(); 1870 WIntType = HostTarget->getWIntType(); 1871 Char16Type = HostTarget->getChar16Type(); 1872 Char32Type = HostTarget->getChar32Type(); 1873 Int64Type = HostTarget->getInt64Type(); 1874 SigAtomicType = HostTarget->getSigAtomicType(); 1875 ProcessIDType = HostTarget->getProcessIDType(); 1876 1877 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1878 UseZeroLengthBitfieldAlignment = 1879 HostTarget->useZeroLengthBitfieldAlignment(); 1880 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1881 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1882 1883 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1884 // we need those macros to be identical on host and device, because (among 1885 // other things) they affect which standard library classes are defined, and 1886 // we need all classes to be defined on both the host and device. 1887 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1888 1889 // Properties intentionally not copied from host: 1890 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1891 // host/device boundary. 1892 // - SuitableAlign: Not visible across the host/device boundary, and may 1893 // correctly be different on host/device, e.g. if host has wider vector 1894 // types than device. 1895 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1896 // as its double type, but that's not necessarily true on the host. 1897 // TODO: nvcc emits a warning when using long double on device; we should 1898 // do the same. 1899 } 1900 void getTargetDefines(const LangOptions &Opts, 1901 MacroBuilder &Builder) const override { 1902 Builder.defineMacro("__PTX__"); 1903 Builder.defineMacro("__NVPTX__"); 1904 if (Opts.CUDAIsDevice) { 1905 // Set __CUDA_ARCH__ for the GPU specified. 1906 std::string CUDAArchCode = [this] { 1907 switch (GPU) { 1908 case CudaArch::UNKNOWN: 1909 assert(false && "No GPU arch when compiling CUDA device code."); 1910 return ""; 1911 case CudaArch::SM_20: 1912 return "200"; 1913 case CudaArch::SM_21: 1914 return "210"; 1915 case CudaArch::SM_30: 1916 return "300"; 1917 case CudaArch::SM_32: 1918 return "320"; 1919 case CudaArch::SM_35: 1920 return "350"; 1921 case CudaArch::SM_37: 1922 return "370"; 1923 case CudaArch::SM_50: 1924 return "500"; 1925 case CudaArch::SM_52: 1926 return "520"; 1927 case CudaArch::SM_53: 1928 return "530"; 1929 case CudaArch::SM_60: 1930 return "600"; 1931 case CudaArch::SM_61: 1932 return "610"; 1933 case CudaArch::SM_62: 1934 return "620"; 1935 } 1936 llvm_unreachable("unhandled CudaArch"); 1937 }(); 1938 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1939 } 1940 } 1941 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1942 return llvm::makeArrayRef(BuiltinInfo, 1943 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1944 } 1945 bool 1946 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1947 StringRef CPU, 1948 const std::vector<std::string> &FeaturesVec) const override { 1949 Features["satom"] = GPU >= CudaArch::SM_60; 1950 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1951 } 1952 1953 bool hasFeature(StringRef Feature) const override { 1954 return llvm::StringSwitch<bool>(Feature) 1955 .Cases("ptx", "nvptx", true) 1956 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1957 .Default(false); 1958 } 1959 1960 ArrayRef<const char *> getGCCRegNames() const override; 1961 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1962 // No aliases. 1963 return None; 1964 } 1965 bool validateAsmConstraint(const char *&Name, 1966 TargetInfo::ConstraintInfo &Info) const override { 1967 switch (*Name) { 1968 default: 1969 return false; 1970 case 'c': 1971 case 'h': 1972 case 'r': 1973 case 'l': 1974 case 'f': 1975 case 'd': 1976 Info.setAllowsRegister(); 1977 return true; 1978 } 1979 } 1980 const char *getClobbers() const override { 1981 // FIXME: Is this really right? 1982 return ""; 1983 } 1984 BuiltinVaListKind getBuiltinVaListKind() const override { 1985 // FIXME: implement 1986 return TargetInfo::CharPtrBuiltinVaList; 1987 } 1988 bool setCPU(const std::string &Name) override { 1989 GPU = StringToCudaArch(Name); 1990 return GPU != CudaArch::UNKNOWN; 1991 } 1992 void setSupportedOpenCLOpts() override { 1993 auto &Opts = getSupportedOpenCLOpts(); 1994 Opts.support("cl_clang_storage_class_specifiers"); 1995 Opts.support("cl_khr_gl_sharing"); 1996 Opts.support("cl_khr_icd"); 1997 1998 Opts.support("cl_khr_fp64"); 1999 Opts.support("cl_khr_byte_addressable_store"); 2000 Opts.support("cl_khr_global_int32_base_atomics"); 2001 Opts.support("cl_khr_global_int32_extended_atomics"); 2002 Opts.support("cl_khr_local_int32_base_atomics"); 2003 Opts.support("cl_khr_local_int32_extended_atomics"); 2004 } 2005 2006 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2007 // CUDA compilations support all of the host's calling conventions. 2008 // 2009 // TODO: We should warn if you apply a non-default CC to anything other than 2010 // a host function. 2011 if (HostTarget) 2012 return HostTarget->checkCallingConvention(CC); 2013 return CCCR_Warning; 2014 } 2015 }; 2016 2017 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2018 #define BUILTIN(ID, TYPE, ATTRS) \ 2019 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2020 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2021 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2022 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2024 #include "clang/Basic/BuiltinsNVPTX.def" 2025 }; 2026 2027 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2028 2029 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2030 return llvm::makeArrayRef(GCCRegNames); 2031 } 2032 2033 static const LangAS::Map AMDGPUPrivateIsZeroMap = { 2034 1, // opencl_global 2035 3, // opencl_local 2036 2, // opencl_constant 2037 4, // opencl_generic 2038 1, // cuda_device 2039 2, // cuda_constant 2040 3 // cuda_shared 2041 }; 2042 static const LangAS::Map AMDGPUGenericIsZeroMap = { 2043 1, // opencl_global 2044 3, // opencl_local 2045 4, // opencl_constant 2046 0, // opencl_generic 2047 1, // cuda_device 2048 4, // cuda_constant 2049 3 // cuda_shared 2050 }; 2051 2052 // If you edit the description strings, make sure you update 2053 // getPointerWidthV(). 2054 2055 static const char *const DataLayoutStringR600 = 2056 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2057 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2058 2059 static const char *const DataLayoutStringSIPrivateIsZero = 2060 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2061 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2062 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2063 2064 static const char *const DataLayoutStringSIGenericIsZero = 2065 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2066 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2067 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2068 2069 class AMDGPUTargetInfo final : public TargetInfo { 2070 static const Builtin::Info BuiltinInfo[]; 2071 static const char * const GCCRegNames[]; 2072 2073 struct AddrSpace { 2074 unsigned Generic, Global, Local, Constant, Private; 2075 AddrSpace(bool IsGenericZero_ = false){ 2076 if (IsGenericZero_) { 2077 Generic = 0; 2078 Global = 1; 2079 Local = 3; 2080 Constant = 4; 2081 Private = 5; 2082 } else { 2083 Generic = 4; 2084 Global = 1; 2085 Local = 3; 2086 Constant = 2; 2087 Private = 0; 2088 } 2089 } 2090 }; 2091 2092 /// \brief The GPU profiles supported by the AMDGPU target. 2093 enum GPUKind { 2094 GK_NONE, 2095 GK_R600, 2096 GK_R600_DOUBLE_OPS, 2097 GK_R700, 2098 GK_R700_DOUBLE_OPS, 2099 GK_EVERGREEN, 2100 GK_EVERGREEN_DOUBLE_OPS, 2101 GK_NORTHERN_ISLANDS, 2102 GK_CAYMAN, 2103 GK_GFX6, 2104 GK_GFX7, 2105 GK_GFX8, 2106 GK_GFX9 2107 } GPU; 2108 2109 bool hasFP64:1; 2110 bool hasFMAF:1; 2111 bool hasLDEXPF:1; 2112 bool hasFullSpeedFP32Denorms:1; 2113 const AddrSpace AS; 2114 2115 static bool isAMDGCN(const llvm::Triple &TT) { 2116 return TT.getArch() == llvm::Triple::amdgcn; 2117 } 2118 2119 static bool isGenericZero(const llvm::Triple &TT) { 2120 return TT.getEnvironmentName() == "amdgiz" || 2121 TT.getEnvironmentName() == "amdgizcl"; 2122 } 2123 public: 2124 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2125 : TargetInfo(Triple) , 2126 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2127 hasFP64(false), 2128 hasFMAF(false), 2129 hasLDEXPF(false), 2130 hasFullSpeedFP32Denorms(false), 2131 AS(isGenericZero(Triple)){ 2132 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2133 hasFP64 = true; 2134 hasFMAF = true; 2135 hasLDEXPF = true; 2136 } 2137 auto IsGenericZero = isGenericZero(Triple); 2138 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2139 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2140 DataLayoutStringSIPrivateIsZero) 2141 : DataLayoutStringR600); 2142 2143 AddrSpaceMap = IsGenericZero ? &AMDGPUGenericIsZeroMap : 2144 &AMDGPUPrivateIsZeroMap; 2145 UseAddrSpaceMapMangling = true; 2146 } 2147 2148 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2149 if (GPU <= GK_CAYMAN) 2150 return 32; 2151 2152 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2153 return 32; 2154 } 2155 return 64; 2156 } 2157 2158 uint64_t getMaxPointerWidth() const override { 2159 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2160 } 2161 2162 const char * getClobbers() const override { 2163 return ""; 2164 } 2165 2166 ArrayRef<const char *> getGCCRegNames() const override; 2167 2168 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2169 return None; 2170 } 2171 2172 bool validateAsmConstraint(const char *&Name, 2173 TargetInfo::ConstraintInfo &Info) const override { 2174 switch (*Name) { 2175 default: break; 2176 case 'v': // vgpr 2177 case 's': // sgpr 2178 Info.setAllowsRegister(); 2179 return true; 2180 } 2181 return false; 2182 } 2183 2184 bool initFeatureMap(llvm::StringMap<bool> &Features, 2185 DiagnosticsEngine &Diags, StringRef CPU, 2186 const std::vector<std::string> &FeatureVec) const override; 2187 2188 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2189 TargetOptions &TargetOpts) const override { 2190 bool hasFP32Denormals = false; 2191 bool hasFP64Denormals = false; 2192 for (auto &I : TargetOpts.FeaturesAsWritten) { 2193 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2194 hasFP32Denormals = true; 2195 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2196 hasFP64Denormals = true; 2197 } 2198 if (!hasFP32Denormals) 2199 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2200 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2201 // Always do not flush fp64 or fp16 denorms. 2202 if (!hasFP64Denormals && hasFP64) 2203 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2204 } 2205 2206 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2207 return llvm::makeArrayRef(BuiltinInfo, 2208 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2209 } 2210 2211 void getTargetDefines(const LangOptions &Opts, 2212 MacroBuilder &Builder) const override { 2213 if (getTriple().getArch() == llvm::Triple::amdgcn) 2214 Builder.defineMacro("__AMDGCN__"); 2215 else 2216 Builder.defineMacro("__R600__"); 2217 2218 if (hasFMAF) 2219 Builder.defineMacro("__HAS_FMAF__"); 2220 if (hasLDEXPF) 2221 Builder.defineMacro("__HAS_LDEXPF__"); 2222 if (hasFP64) 2223 Builder.defineMacro("__HAS_FP64__"); 2224 } 2225 2226 BuiltinVaListKind getBuiltinVaListKind() const override { 2227 return TargetInfo::CharPtrBuiltinVaList; 2228 } 2229 2230 static GPUKind parseR600Name(StringRef Name) { 2231 return llvm::StringSwitch<GPUKind>(Name) 2232 .Case("r600" , GK_R600) 2233 .Case("rv610", GK_R600) 2234 .Case("rv620", GK_R600) 2235 .Case("rv630", GK_R600) 2236 .Case("rv635", GK_R600) 2237 .Case("rs780", GK_R600) 2238 .Case("rs880", GK_R600) 2239 .Case("rv670", GK_R600_DOUBLE_OPS) 2240 .Case("rv710", GK_R700) 2241 .Case("rv730", GK_R700) 2242 .Case("rv740", GK_R700_DOUBLE_OPS) 2243 .Case("rv770", GK_R700_DOUBLE_OPS) 2244 .Case("palm", GK_EVERGREEN) 2245 .Case("cedar", GK_EVERGREEN) 2246 .Case("sumo", GK_EVERGREEN) 2247 .Case("sumo2", GK_EVERGREEN) 2248 .Case("redwood", GK_EVERGREEN) 2249 .Case("juniper", GK_EVERGREEN) 2250 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2251 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2252 .Case("barts", GK_NORTHERN_ISLANDS) 2253 .Case("turks", GK_NORTHERN_ISLANDS) 2254 .Case("caicos", GK_NORTHERN_ISLANDS) 2255 .Case("cayman", GK_CAYMAN) 2256 .Case("aruba", GK_CAYMAN) 2257 .Default(GK_NONE); 2258 } 2259 2260 static GPUKind parseAMDGCNName(StringRef Name) { 2261 return llvm::StringSwitch<GPUKind>(Name) 2262 .Case("tahiti", GK_GFX6) 2263 .Case("pitcairn", GK_GFX6) 2264 .Case("verde", GK_GFX6) 2265 .Case("oland", GK_GFX6) 2266 .Case("hainan", GK_GFX6) 2267 .Case("bonaire", GK_GFX7) 2268 .Case("kabini", GK_GFX7) 2269 .Case("kaveri", GK_GFX7) 2270 .Case("hawaii", GK_GFX7) 2271 .Case("mullins", GK_GFX7) 2272 .Case("gfx700", GK_GFX7) 2273 .Case("gfx701", GK_GFX7) 2274 .Case("gfx702", GK_GFX7) 2275 .Case("tonga", GK_GFX8) 2276 .Case("iceland", GK_GFX8) 2277 .Case("carrizo", GK_GFX8) 2278 .Case("fiji", GK_GFX8) 2279 .Case("stoney", GK_GFX8) 2280 .Case("polaris10", GK_GFX8) 2281 .Case("polaris11", GK_GFX8) 2282 .Case("gfx800", GK_GFX8) 2283 .Case("gfx801", GK_GFX8) 2284 .Case("gfx802", GK_GFX8) 2285 .Case("gfx803", GK_GFX8) 2286 .Case("gfx804", GK_GFX8) 2287 .Case("gfx810", GK_GFX8) 2288 .Case("gfx900", GK_GFX9) 2289 .Case("gfx901", GK_GFX9) 2290 .Default(GK_NONE); 2291 } 2292 2293 bool setCPU(const std::string &Name) override { 2294 if (getTriple().getArch() == llvm::Triple::amdgcn) 2295 GPU = parseAMDGCNName(Name); 2296 else 2297 GPU = parseR600Name(Name); 2298 2299 return GPU != GK_NONE; 2300 } 2301 2302 void setSupportedOpenCLOpts() override { 2303 auto &Opts = getSupportedOpenCLOpts(); 2304 Opts.support("cl_clang_storage_class_specifiers"); 2305 Opts.support("cl_khr_icd"); 2306 2307 if (hasFP64) 2308 Opts.support("cl_khr_fp64"); 2309 if (GPU >= GK_EVERGREEN) { 2310 Opts.support("cl_khr_byte_addressable_store"); 2311 Opts.support("cl_khr_global_int32_base_atomics"); 2312 Opts.support("cl_khr_global_int32_extended_atomics"); 2313 Opts.support("cl_khr_local_int32_base_atomics"); 2314 Opts.support("cl_khr_local_int32_extended_atomics"); 2315 } 2316 if (GPU >= GK_GFX6) { 2317 Opts.support("cl_khr_fp16"); 2318 Opts.support("cl_khr_int64_base_atomics"); 2319 Opts.support("cl_khr_int64_extended_atomics"); 2320 Opts.support("cl_khr_mipmap_image"); 2321 Opts.support("cl_khr_subgroups"); 2322 Opts.support("cl_khr_3d_image_writes"); 2323 Opts.support("cl_amd_media_ops"); 2324 Opts.support("cl_amd_media_ops2"); 2325 } 2326 } 2327 2328 LangAS::ID getOpenCLImageAddrSpace() const override { 2329 return LangAS::opencl_constant; 2330 } 2331 2332 /// \returns Target specific vtbl ptr address space. 2333 unsigned getVtblPtrAddressSpace() const override { 2334 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2335 // would be nice if we could use it here instead of using bare numbers (same 2336 // applies to getDWARFAddressSpace). 2337 return 2; // constant. 2338 } 2339 2340 /// \returns If a target requires an address within a target specific address 2341 /// space \p AddressSpace to be converted in order to be used, then return the 2342 /// corresponding target specific DWARF address space. 2343 /// 2344 /// \returns Otherwise return None and no conversion will be emitted in the 2345 /// DWARF. 2346 Optional<unsigned> getDWARFAddressSpace( 2347 unsigned AddressSpace) const override { 2348 const unsigned DWARF_Private = 1; 2349 const unsigned DWARF_Local = 2; 2350 if (AddressSpace == AS.Private) { 2351 return DWARF_Private; 2352 } else if (AddressSpace == AS.Local) { 2353 return DWARF_Local; 2354 } else { 2355 return None; 2356 } 2357 } 2358 2359 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2360 switch (CC) { 2361 default: 2362 return CCCR_Warning; 2363 case CC_C: 2364 case CC_OpenCLKernel: 2365 return CCCR_OK; 2366 } 2367 } 2368 2369 // In amdgcn target the null pointer in global, constant, and generic 2370 // address space has value 0 but in private and local address space has 2371 // value ~0. 2372 uint64_t getNullPointerValue(unsigned AS) const override { 2373 return AS == LangAS::opencl_local ? ~0 : 0; 2374 } 2375 }; 2376 2377 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2378 #define BUILTIN(ID, TYPE, ATTRS) \ 2379 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2380 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2381 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2382 #include "clang/Basic/BuiltinsAMDGPU.def" 2383 }; 2384 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2385 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2386 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2387 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2388 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2389 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2390 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2391 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2392 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2393 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2394 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2395 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2396 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2397 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2398 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2399 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2400 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2401 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2402 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2403 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2404 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2405 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2406 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2407 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2408 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2409 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2410 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2411 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2412 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2413 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2414 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2415 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2416 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2417 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2418 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2419 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2420 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2421 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2422 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2423 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2424 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2425 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2426 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2427 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2428 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2429 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2430 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2431 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2432 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2433 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2434 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2435 }; 2436 2437 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2438 return llvm::makeArrayRef(GCCRegNames); 2439 } 2440 2441 bool AMDGPUTargetInfo::initFeatureMap( 2442 llvm::StringMap<bool> &Features, 2443 DiagnosticsEngine &Diags, StringRef CPU, 2444 const std::vector<std::string> &FeatureVec) const { 2445 2446 // XXX - What does the member GPU mean if device name string passed here? 2447 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2448 if (CPU.empty()) 2449 CPU = "tahiti"; 2450 2451 switch (parseAMDGCNName(CPU)) { 2452 case GK_GFX6: 2453 case GK_GFX7: 2454 break; 2455 2456 case GK_GFX9: 2457 Features["gfx9-insts"] = true; 2458 LLVM_FALLTHROUGH; 2459 case GK_GFX8: 2460 Features["s-memrealtime"] = true; 2461 Features["16-bit-insts"] = true; 2462 Features["dpp"] = true; 2463 break; 2464 2465 case GK_NONE: 2466 return false; 2467 default: 2468 llvm_unreachable("unhandled subtarget"); 2469 } 2470 } else { 2471 if (CPU.empty()) 2472 CPU = "r600"; 2473 2474 switch (parseR600Name(CPU)) { 2475 case GK_R600: 2476 case GK_R700: 2477 case GK_EVERGREEN: 2478 case GK_NORTHERN_ISLANDS: 2479 break; 2480 case GK_R600_DOUBLE_OPS: 2481 case GK_R700_DOUBLE_OPS: 2482 case GK_EVERGREEN_DOUBLE_OPS: 2483 case GK_CAYMAN: 2484 Features["fp64"] = true; 2485 break; 2486 case GK_NONE: 2487 return false; 2488 default: 2489 llvm_unreachable("unhandled subtarget"); 2490 } 2491 } 2492 2493 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2494 } 2495 2496 const Builtin::Info BuiltinInfoX86[] = { 2497 #define BUILTIN(ID, TYPE, ATTRS) \ 2498 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2499 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2500 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2501 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2502 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2503 #include "clang/Basic/BuiltinsX86.def" 2504 2505 #define BUILTIN(ID, TYPE, ATTRS) \ 2506 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2507 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2508 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2509 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2510 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2511 #include "clang/Basic/BuiltinsX86_64.def" 2512 }; 2513 2514 2515 static const char* const GCCRegNames[] = { 2516 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2517 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2518 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2519 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2520 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2521 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2522 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2523 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2524 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2525 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2526 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2527 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2528 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2529 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2530 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2531 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2532 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2533 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2534 }; 2535 2536 const TargetInfo::AddlRegName AddlRegNames[] = { 2537 { { "al", "ah", "eax", "rax" }, 0 }, 2538 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2539 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2540 { { "dl", "dh", "edx", "rdx" }, 1 }, 2541 { { "esi", "rsi" }, 4 }, 2542 { { "edi", "rdi" }, 5 }, 2543 { { "esp", "rsp" }, 7 }, 2544 { { "ebp", "rbp" }, 6 }, 2545 { { "r8d", "r8w", "r8b" }, 38 }, 2546 { { "r9d", "r9w", "r9b" }, 39 }, 2547 { { "r10d", "r10w", "r10b" }, 40 }, 2548 { { "r11d", "r11w", "r11b" }, 41 }, 2549 { { "r12d", "r12w", "r12b" }, 42 }, 2550 { { "r13d", "r13w", "r13b" }, 43 }, 2551 { { "r14d", "r14w", "r14b" }, 44 }, 2552 { { "r15d", "r15w", "r15b" }, 45 }, 2553 }; 2554 2555 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2556 // most of the implementation can be shared. 2557 class X86TargetInfo : public TargetInfo { 2558 enum X86SSEEnum { 2559 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2560 } SSELevel = NoSSE; 2561 enum MMX3DNowEnum { 2562 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2563 } MMX3DNowLevel = NoMMX3DNow; 2564 enum XOPEnum { 2565 NoXOP, 2566 SSE4A, 2567 FMA4, 2568 XOP 2569 } XOPLevel = NoXOP; 2570 2571 bool HasAES = false; 2572 bool HasPCLMUL = false; 2573 bool HasLZCNT = false; 2574 bool HasRDRND = false; 2575 bool HasFSGSBASE = false; 2576 bool HasBMI = false; 2577 bool HasBMI2 = false; 2578 bool HasPOPCNT = false; 2579 bool HasRTM = false; 2580 bool HasPRFCHW = false; 2581 bool HasRDSEED = false; 2582 bool HasADX = false; 2583 bool HasTBM = false; 2584 bool HasFMA = false; 2585 bool HasF16C = false; 2586 bool HasAVX512CD = false; 2587 bool HasAVX512ER = false; 2588 bool HasAVX512PF = false; 2589 bool HasAVX512DQ = false; 2590 bool HasAVX512BW = false; 2591 bool HasAVX512VL = false; 2592 bool HasAVX512VBMI = false; 2593 bool HasAVX512IFMA = false; 2594 bool HasSHA = false; 2595 bool HasMPX = false; 2596 bool HasSGX = false; 2597 bool HasCX16 = false; 2598 bool HasFXSR = false; 2599 bool HasXSAVE = false; 2600 bool HasXSAVEOPT = false; 2601 bool HasXSAVEC = false; 2602 bool HasXSAVES = false; 2603 bool HasMWAITX = false; 2604 bool HasCLZERO = false; 2605 bool HasPKU = false; 2606 bool HasCLFLUSHOPT = false; 2607 bool HasCLWB = false; 2608 bool HasMOVBE = false; 2609 bool HasPREFETCHWT1 = false; 2610 2611 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2612 /// 2613 /// Each enumeration represents a particular CPU supported by Clang. These 2614 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2615 enum CPUKind { 2616 CK_Generic, 2617 2618 /// \name i386 2619 /// i386-generation processors. 2620 //@{ 2621 CK_i386, 2622 //@} 2623 2624 /// \name i486 2625 /// i486-generation processors. 2626 //@{ 2627 CK_i486, 2628 CK_WinChipC6, 2629 CK_WinChip2, 2630 CK_C3, 2631 //@} 2632 2633 /// \name i586 2634 /// i586-generation processors, P5 microarchitecture based. 2635 //@{ 2636 CK_i586, 2637 CK_Pentium, 2638 CK_PentiumMMX, 2639 //@} 2640 2641 /// \name i686 2642 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2643 //@{ 2644 CK_i686, 2645 CK_PentiumPro, 2646 CK_Pentium2, 2647 CK_Pentium3, 2648 CK_Pentium3M, 2649 CK_PentiumM, 2650 CK_C3_2, 2651 2652 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2653 /// Clang however has some logic to suport this. 2654 // FIXME: Warn, deprecate, and potentially remove this. 2655 CK_Yonah, 2656 //@} 2657 2658 /// \name Netburst 2659 /// Netburst microarchitecture based processors. 2660 //@{ 2661 CK_Pentium4, 2662 CK_Pentium4M, 2663 CK_Prescott, 2664 CK_Nocona, 2665 //@} 2666 2667 /// \name Core 2668 /// Core microarchitecture based processors. 2669 //@{ 2670 CK_Core2, 2671 2672 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2673 /// codename which GCC no longer accepts as an option to -march, but Clang 2674 /// has some logic for recognizing it. 2675 // FIXME: Warn, deprecate, and potentially remove this. 2676 CK_Penryn, 2677 //@} 2678 2679 /// \name Atom 2680 /// Atom processors 2681 //@{ 2682 CK_Bonnell, 2683 CK_Silvermont, 2684 //@} 2685 2686 /// \name Nehalem 2687 /// Nehalem microarchitecture based processors. 2688 CK_Nehalem, 2689 2690 /// \name Westmere 2691 /// Westmere microarchitecture based processors. 2692 CK_Westmere, 2693 2694 /// \name Sandy Bridge 2695 /// Sandy Bridge microarchitecture based processors. 2696 CK_SandyBridge, 2697 2698 /// \name Ivy Bridge 2699 /// Ivy Bridge microarchitecture based processors. 2700 CK_IvyBridge, 2701 2702 /// \name Haswell 2703 /// Haswell microarchitecture based processors. 2704 CK_Haswell, 2705 2706 /// \name Broadwell 2707 /// Broadwell microarchitecture based processors. 2708 CK_Broadwell, 2709 2710 /// \name Skylake Client 2711 /// Skylake client microarchitecture based processors. 2712 CK_SkylakeClient, 2713 2714 /// \name Skylake Server 2715 /// Skylake server microarchitecture based processors. 2716 CK_SkylakeServer, 2717 2718 /// \name Cannonlake Client 2719 /// Cannonlake client microarchitecture based processors. 2720 CK_Cannonlake, 2721 2722 /// \name Knights Landing 2723 /// Knights Landing processor. 2724 CK_KNL, 2725 2726 /// \name Lakemont 2727 /// Lakemont microarchitecture based processors. 2728 CK_Lakemont, 2729 2730 /// \name K6 2731 /// K6 architecture processors. 2732 //@{ 2733 CK_K6, 2734 CK_K6_2, 2735 CK_K6_3, 2736 //@} 2737 2738 /// \name K7 2739 /// K7 architecture processors. 2740 //@{ 2741 CK_Athlon, 2742 CK_AthlonThunderbird, 2743 CK_Athlon4, 2744 CK_AthlonXP, 2745 CK_AthlonMP, 2746 //@} 2747 2748 /// \name K8 2749 /// K8 architecture processors. 2750 //@{ 2751 CK_Athlon64, 2752 CK_Athlon64SSE3, 2753 CK_AthlonFX, 2754 CK_K8, 2755 CK_K8SSE3, 2756 CK_Opteron, 2757 CK_OpteronSSE3, 2758 CK_AMDFAM10, 2759 //@} 2760 2761 /// \name Bobcat 2762 /// Bobcat architecture processors. 2763 //@{ 2764 CK_BTVER1, 2765 CK_BTVER2, 2766 //@} 2767 2768 /// \name Bulldozer 2769 /// Bulldozer architecture processors. 2770 //@{ 2771 CK_BDVER1, 2772 CK_BDVER2, 2773 CK_BDVER3, 2774 CK_BDVER4, 2775 //@} 2776 2777 /// \name zen 2778 /// Zen architecture processors. 2779 //@{ 2780 CK_ZNVER1, 2781 //@} 2782 2783 /// This specification is deprecated and will be removed in the future. 2784 /// Users should prefer \see CK_K8. 2785 // FIXME: Warn on this when the CPU is set to it. 2786 //@{ 2787 CK_x86_64, 2788 //@} 2789 2790 /// \name Geode 2791 /// Geode processors. 2792 //@{ 2793 CK_Geode 2794 //@} 2795 } CPU = CK_Generic; 2796 2797 CPUKind getCPUKind(StringRef CPU) const { 2798 return llvm::StringSwitch<CPUKind>(CPU) 2799 .Case("i386", CK_i386) 2800 .Case("i486", CK_i486) 2801 .Case("winchip-c6", CK_WinChipC6) 2802 .Case("winchip2", CK_WinChip2) 2803 .Case("c3", CK_C3) 2804 .Case("i586", CK_i586) 2805 .Case("pentium", CK_Pentium) 2806 .Case("pentium-mmx", CK_PentiumMMX) 2807 .Case("i686", CK_i686) 2808 .Case("pentiumpro", CK_PentiumPro) 2809 .Case("pentium2", CK_Pentium2) 2810 .Case("pentium3", CK_Pentium3) 2811 .Case("pentium3m", CK_Pentium3M) 2812 .Case("pentium-m", CK_PentiumM) 2813 .Case("c3-2", CK_C3_2) 2814 .Case("yonah", CK_Yonah) 2815 .Case("pentium4", CK_Pentium4) 2816 .Case("pentium4m", CK_Pentium4M) 2817 .Case("prescott", CK_Prescott) 2818 .Case("nocona", CK_Nocona) 2819 .Case("core2", CK_Core2) 2820 .Case("penryn", CK_Penryn) 2821 .Case("bonnell", CK_Bonnell) 2822 .Case("atom", CK_Bonnell) // Legacy name. 2823 .Case("silvermont", CK_Silvermont) 2824 .Case("slm", CK_Silvermont) // Legacy name. 2825 .Case("nehalem", CK_Nehalem) 2826 .Case("corei7", CK_Nehalem) // Legacy name. 2827 .Case("westmere", CK_Westmere) 2828 .Case("sandybridge", CK_SandyBridge) 2829 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2830 .Case("ivybridge", CK_IvyBridge) 2831 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2832 .Case("haswell", CK_Haswell) 2833 .Case("core-avx2", CK_Haswell) // Legacy name. 2834 .Case("broadwell", CK_Broadwell) 2835 .Case("skylake", CK_SkylakeClient) 2836 .Case("skylake-avx512", CK_SkylakeServer) 2837 .Case("skx", CK_SkylakeServer) // Legacy name. 2838 .Case("cannonlake", CK_Cannonlake) 2839 .Case("knl", CK_KNL) 2840 .Case("lakemont", CK_Lakemont) 2841 .Case("k6", CK_K6) 2842 .Case("k6-2", CK_K6_2) 2843 .Case("k6-3", CK_K6_3) 2844 .Case("athlon", CK_Athlon) 2845 .Case("athlon-tbird", CK_AthlonThunderbird) 2846 .Case("athlon-4", CK_Athlon4) 2847 .Case("athlon-xp", CK_AthlonXP) 2848 .Case("athlon-mp", CK_AthlonMP) 2849 .Case("athlon64", CK_Athlon64) 2850 .Case("athlon64-sse3", CK_Athlon64SSE3) 2851 .Case("athlon-fx", CK_AthlonFX) 2852 .Case("k8", CK_K8) 2853 .Case("k8-sse3", CK_K8SSE3) 2854 .Case("opteron", CK_Opteron) 2855 .Case("opteron-sse3", CK_OpteronSSE3) 2856 .Case("barcelona", CK_AMDFAM10) 2857 .Case("amdfam10", CK_AMDFAM10) 2858 .Case("btver1", CK_BTVER1) 2859 .Case("btver2", CK_BTVER2) 2860 .Case("bdver1", CK_BDVER1) 2861 .Case("bdver2", CK_BDVER2) 2862 .Case("bdver3", CK_BDVER3) 2863 .Case("bdver4", CK_BDVER4) 2864 .Case("znver1", CK_ZNVER1) 2865 .Case("x86-64", CK_x86_64) 2866 .Case("geode", CK_Geode) 2867 .Default(CK_Generic); 2868 } 2869 2870 enum FPMathKind { 2871 FP_Default, 2872 FP_SSE, 2873 FP_387 2874 } FPMath = FP_Default; 2875 2876 public: 2877 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2878 : TargetInfo(Triple) { 2879 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2880 } 2881 unsigned getFloatEvalMethod() const override { 2882 // X87 evaluates with 80 bits "long double" precision. 2883 return SSELevel == NoSSE ? 2 : 0; 2884 } 2885 ArrayRef<const char *> getGCCRegNames() const override { 2886 return llvm::makeArrayRef(GCCRegNames); 2887 } 2888 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2889 return None; 2890 } 2891 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2892 return llvm::makeArrayRef(AddlRegNames); 2893 } 2894 bool validateCpuSupports(StringRef Name) const override; 2895 bool validateAsmConstraint(const char *&Name, 2896 TargetInfo::ConstraintInfo &info) const override; 2897 2898 bool validateGlobalRegisterVariable(StringRef RegName, 2899 unsigned RegSize, 2900 bool &HasSizeMismatch) const override { 2901 // esp and ebp are the only 32-bit registers the x86 backend can currently 2902 // handle. 2903 if (RegName.equals("esp") || RegName.equals("ebp")) { 2904 // Check that the register size is 32-bit. 2905 HasSizeMismatch = RegSize != 32; 2906 return true; 2907 } 2908 2909 return false; 2910 } 2911 2912 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2913 2914 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2915 2916 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2917 2918 std::string convertConstraint(const char *&Constraint) const override; 2919 const char *getClobbers() const override { 2920 return "~{dirflag},~{fpsr},~{flags}"; 2921 } 2922 2923 StringRef getConstraintRegister(const StringRef &Constraint, 2924 const StringRef &Expression) const override { 2925 StringRef::iterator I, E; 2926 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2927 if (isalpha(*I)) 2928 break; 2929 } 2930 if (I == E) 2931 return ""; 2932 switch (*I) { 2933 // For the register constraints, return the matching register name 2934 case 'a': 2935 return "ax"; 2936 case 'b': 2937 return "bx"; 2938 case 'c': 2939 return "cx"; 2940 case 'd': 2941 return "dx"; 2942 case 'S': 2943 return "si"; 2944 case 'D': 2945 return "di"; 2946 // In case the constraint is 'r' we need to return Expression 2947 case 'r': 2948 return Expression; 2949 default: 2950 // Default value if there is no constraint for the register 2951 return ""; 2952 } 2953 return ""; 2954 } 2955 2956 void getTargetDefines(const LangOptions &Opts, 2957 MacroBuilder &Builder) const override; 2958 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2959 bool Enabled); 2960 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2961 bool Enabled); 2962 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2963 bool Enabled); 2964 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2965 StringRef Name, bool Enabled) const override { 2966 setFeatureEnabledImpl(Features, Name, Enabled); 2967 } 2968 // This exists purely to cut down on the number of virtual calls in 2969 // initFeatureMap which calls this repeatedly. 2970 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2971 StringRef Name, bool Enabled); 2972 bool 2973 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2974 StringRef CPU, 2975 const std::vector<std::string> &FeaturesVec) const override; 2976 bool hasFeature(StringRef Feature) const override; 2977 bool handleTargetFeatures(std::vector<std::string> &Features, 2978 DiagnosticsEngine &Diags) override; 2979 StringRef getABI() const override { 2980 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2981 return "avx512"; 2982 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2983 return "avx"; 2984 if (getTriple().getArch() == llvm::Triple::x86 && 2985 MMX3DNowLevel == NoMMX3DNow) 2986 return "no-mmx"; 2987 return ""; 2988 } 2989 bool setCPU(const std::string &Name) override { 2990 CPU = getCPUKind(Name); 2991 2992 // Perform any per-CPU checks necessary to determine if this CPU is 2993 // acceptable. 2994 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2995 // invalid without explaining *why*. 2996 switch (CPU) { 2997 case CK_Generic: 2998 // No processor selected! 2999 return false; 3000 3001 case CK_i386: 3002 case CK_i486: 3003 case CK_WinChipC6: 3004 case CK_WinChip2: 3005 case CK_C3: 3006 case CK_i586: 3007 case CK_Pentium: 3008 case CK_PentiumMMX: 3009 case CK_i686: 3010 case CK_PentiumPro: 3011 case CK_Pentium2: 3012 case CK_Pentium3: 3013 case CK_Pentium3M: 3014 case CK_PentiumM: 3015 case CK_Yonah: 3016 case CK_C3_2: 3017 case CK_Pentium4: 3018 case CK_Pentium4M: 3019 case CK_Lakemont: 3020 case CK_Prescott: 3021 case CK_K6: 3022 case CK_K6_2: 3023 case CK_K6_3: 3024 case CK_Athlon: 3025 case CK_AthlonThunderbird: 3026 case CK_Athlon4: 3027 case CK_AthlonXP: 3028 case CK_AthlonMP: 3029 case CK_Geode: 3030 // Only accept certain architectures when compiling in 32-bit mode. 3031 if (getTriple().getArch() != llvm::Triple::x86) 3032 return false; 3033 3034 // Fallthrough 3035 case CK_Nocona: 3036 case CK_Core2: 3037 case CK_Penryn: 3038 case CK_Bonnell: 3039 case CK_Silvermont: 3040 case CK_Nehalem: 3041 case CK_Westmere: 3042 case CK_SandyBridge: 3043 case CK_IvyBridge: 3044 case CK_Haswell: 3045 case CK_Broadwell: 3046 case CK_SkylakeClient: 3047 case CK_SkylakeServer: 3048 case CK_Cannonlake: 3049 case CK_KNL: 3050 case CK_Athlon64: 3051 case CK_Athlon64SSE3: 3052 case CK_AthlonFX: 3053 case CK_K8: 3054 case CK_K8SSE3: 3055 case CK_Opteron: 3056 case CK_OpteronSSE3: 3057 case CK_AMDFAM10: 3058 case CK_BTVER1: 3059 case CK_BTVER2: 3060 case CK_BDVER1: 3061 case CK_BDVER2: 3062 case CK_BDVER3: 3063 case CK_BDVER4: 3064 case CK_ZNVER1: 3065 case CK_x86_64: 3066 return true; 3067 } 3068 llvm_unreachable("Unhandled CPU kind"); 3069 } 3070 3071 bool setFPMath(StringRef Name) override; 3072 3073 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3074 // Most of the non-ARM calling conventions are i386 conventions. 3075 switch (CC) { 3076 case CC_X86ThisCall: 3077 case CC_X86FastCall: 3078 case CC_X86StdCall: 3079 case CC_X86VectorCall: 3080 case CC_X86RegCall: 3081 case CC_C: 3082 case CC_Swift: 3083 case CC_X86Pascal: 3084 case CC_IntelOclBicc: 3085 return CCCR_OK; 3086 default: 3087 return CCCR_Warning; 3088 } 3089 } 3090 3091 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3092 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3093 } 3094 3095 bool hasSjLjLowering() const override { 3096 return true; 3097 } 3098 3099 void setSupportedOpenCLOpts() override { 3100 getSupportedOpenCLOpts().supportAll(); 3101 } 3102 }; 3103 3104 bool X86TargetInfo::setFPMath(StringRef Name) { 3105 if (Name == "387") { 3106 FPMath = FP_387; 3107 return true; 3108 } 3109 if (Name == "sse") { 3110 FPMath = FP_SSE; 3111 return true; 3112 } 3113 return false; 3114 } 3115 3116 bool X86TargetInfo::initFeatureMap( 3117 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3118 const std::vector<std::string> &FeaturesVec) const { 3119 // FIXME: This *really* should not be here. 3120 // X86_64 always has SSE2. 3121 if (getTriple().getArch() == llvm::Triple::x86_64) 3122 setFeatureEnabledImpl(Features, "sse2", true); 3123 3124 const CPUKind Kind = getCPUKind(CPU); 3125 3126 // Enable X87 for all X86 processors but Lakemont. 3127 if (Kind != CK_Lakemont) 3128 setFeatureEnabledImpl(Features, "x87", true); 3129 3130 switch (Kind) { 3131 case CK_Generic: 3132 case CK_i386: 3133 case CK_i486: 3134 case CK_i586: 3135 case CK_Pentium: 3136 case CK_i686: 3137 case CK_PentiumPro: 3138 case CK_Lakemont: 3139 break; 3140 case CK_PentiumMMX: 3141 case CK_Pentium2: 3142 case CK_K6: 3143 case CK_WinChipC6: 3144 setFeatureEnabledImpl(Features, "mmx", true); 3145 break; 3146 case CK_Pentium3: 3147 case CK_Pentium3M: 3148 case CK_C3_2: 3149 setFeatureEnabledImpl(Features, "sse", true); 3150 setFeatureEnabledImpl(Features, "fxsr", true); 3151 break; 3152 case CK_PentiumM: 3153 case CK_Pentium4: 3154 case CK_Pentium4M: 3155 case CK_x86_64: 3156 setFeatureEnabledImpl(Features, "sse2", true); 3157 setFeatureEnabledImpl(Features, "fxsr", true); 3158 break; 3159 case CK_Yonah: 3160 case CK_Prescott: 3161 case CK_Nocona: 3162 setFeatureEnabledImpl(Features, "sse3", true); 3163 setFeatureEnabledImpl(Features, "fxsr", true); 3164 setFeatureEnabledImpl(Features, "cx16", true); 3165 break; 3166 case CK_Core2: 3167 case CK_Bonnell: 3168 setFeatureEnabledImpl(Features, "ssse3", true); 3169 setFeatureEnabledImpl(Features, "fxsr", true); 3170 setFeatureEnabledImpl(Features, "cx16", true); 3171 break; 3172 case CK_Penryn: 3173 setFeatureEnabledImpl(Features, "sse4.1", true); 3174 setFeatureEnabledImpl(Features, "fxsr", true); 3175 setFeatureEnabledImpl(Features, "cx16", true); 3176 break; 3177 case CK_Cannonlake: 3178 setFeatureEnabledImpl(Features, "avx512ifma", true); 3179 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3180 setFeatureEnabledImpl(Features, "sha", true); 3181 LLVM_FALLTHROUGH; 3182 case CK_SkylakeServer: 3183 setFeatureEnabledImpl(Features, "avx512f", true); 3184 setFeatureEnabledImpl(Features, "avx512cd", true); 3185 setFeatureEnabledImpl(Features, "avx512dq", true); 3186 setFeatureEnabledImpl(Features, "avx512bw", true); 3187 setFeatureEnabledImpl(Features, "avx512vl", true); 3188 setFeatureEnabledImpl(Features, "pku", true); 3189 setFeatureEnabledImpl(Features, "clwb", true); 3190 LLVM_FALLTHROUGH; 3191 case CK_SkylakeClient: 3192 setFeatureEnabledImpl(Features, "xsavec", true); 3193 setFeatureEnabledImpl(Features, "xsaves", true); 3194 setFeatureEnabledImpl(Features, "mpx", true); 3195 setFeatureEnabledImpl(Features, "sgx", true); 3196 setFeatureEnabledImpl(Features, "clflushopt", true); 3197 setFeatureEnabledImpl(Features, "rtm", true); 3198 LLVM_FALLTHROUGH; 3199 case CK_Broadwell: 3200 setFeatureEnabledImpl(Features, "rdseed", true); 3201 setFeatureEnabledImpl(Features, "adx", true); 3202 LLVM_FALLTHROUGH; 3203 case CK_Haswell: 3204 setFeatureEnabledImpl(Features, "avx2", true); 3205 setFeatureEnabledImpl(Features, "lzcnt", true); 3206 setFeatureEnabledImpl(Features, "bmi", true); 3207 setFeatureEnabledImpl(Features, "bmi2", true); 3208 setFeatureEnabledImpl(Features, "fma", true); 3209 setFeatureEnabledImpl(Features, "movbe", true); 3210 LLVM_FALLTHROUGH; 3211 case CK_IvyBridge: 3212 setFeatureEnabledImpl(Features, "rdrnd", true); 3213 setFeatureEnabledImpl(Features, "f16c", true); 3214 setFeatureEnabledImpl(Features, "fsgsbase", true); 3215 LLVM_FALLTHROUGH; 3216 case CK_SandyBridge: 3217 setFeatureEnabledImpl(Features, "avx", true); 3218 setFeatureEnabledImpl(Features, "xsave", true); 3219 setFeatureEnabledImpl(Features, "xsaveopt", true); 3220 LLVM_FALLTHROUGH; 3221 case CK_Westmere: 3222 case CK_Silvermont: 3223 setFeatureEnabledImpl(Features, "aes", true); 3224 setFeatureEnabledImpl(Features, "pclmul", true); 3225 LLVM_FALLTHROUGH; 3226 case CK_Nehalem: 3227 setFeatureEnabledImpl(Features, "sse4.2", true); 3228 setFeatureEnabledImpl(Features, "fxsr", true); 3229 setFeatureEnabledImpl(Features, "cx16", true); 3230 break; 3231 case CK_KNL: 3232 setFeatureEnabledImpl(Features, "avx512f", true); 3233 setFeatureEnabledImpl(Features, "avx512cd", true); 3234 setFeatureEnabledImpl(Features, "avx512er", true); 3235 setFeatureEnabledImpl(Features, "avx512pf", true); 3236 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3237 setFeatureEnabledImpl(Features, "fxsr", true); 3238 setFeatureEnabledImpl(Features, "rdseed", true); 3239 setFeatureEnabledImpl(Features, "adx", true); 3240 setFeatureEnabledImpl(Features, "lzcnt", true); 3241 setFeatureEnabledImpl(Features, "bmi", true); 3242 setFeatureEnabledImpl(Features, "bmi2", true); 3243 setFeatureEnabledImpl(Features, "rtm", true); 3244 setFeatureEnabledImpl(Features, "fma", true); 3245 setFeatureEnabledImpl(Features, "rdrnd", true); 3246 setFeatureEnabledImpl(Features, "f16c", true); 3247 setFeatureEnabledImpl(Features, "fsgsbase", true); 3248 setFeatureEnabledImpl(Features, "aes", true); 3249 setFeatureEnabledImpl(Features, "pclmul", true); 3250 setFeatureEnabledImpl(Features, "cx16", true); 3251 setFeatureEnabledImpl(Features, "xsaveopt", true); 3252 setFeatureEnabledImpl(Features, "xsave", true); 3253 setFeatureEnabledImpl(Features, "movbe", true); 3254 break; 3255 case CK_K6_2: 3256 case CK_K6_3: 3257 case CK_WinChip2: 3258 case CK_C3: 3259 setFeatureEnabledImpl(Features, "3dnow", true); 3260 break; 3261 case CK_Athlon: 3262 case CK_AthlonThunderbird: 3263 case CK_Geode: 3264 setFeatureEnabledImpl(Features, "3dnowa", true); 3265 break; 3266 case CK_Athlon4: 3267 case CK_AthlonXP: 3268 case CK_AthlonMP: 3269 setFeatureEnabledImpl(Features, "sse", true); 3270 setFeatureEnabledImpl(Features, "3dnowa", true); 3271 setFeatureEnabledImpl(Features, "fxsr", true); 3272 break; 3273 case CK_K8: 3274 case CK_Opteron: 3275 case CK_Athlon64: 3276 case CK_AthlonFX: 3277 setFeatureEnabledImpl(Features, "sse2", true); 3278 setFeatureEnabledImpl(Features, "3dnowa", true); 3279 setFeatureEnabledImpl(Features, "fxsr", true); 3280 break; 3281 case CK_AMDFAM10: 3282 setFeatureEnabledImpl(Features, "sse4a", true); 3283 setFeatureEnabledImpl(Features, "lzcnt", true); 3284 setFeatureEnabledImpl(Features, "popcnt", true); 3285 LLVM_FALLTHROUGH; 3286 case CK_K8SSE3: 3287 case CK_OpteronSSE3: 3288 case CK_Athlon64SSE3: 3289 setFeatureEnabledImpl(Features, "sse3", true); 3290 setFeatureEnabledImpl(Features, "3dnowa", true); 3291 setFeatureEnabledImpl(Features, "fxsr", true); 3292 break; 3293 case CK_BTVER2: 3294 setFeatureEnabledImpl(Features, "avx", true); 3295 setFeatureEnabledImpl(Features, "aes", true); 3296 setFeatureEnabledImpl(Features, "pclmul", true); 3297 setFeatureEnabledImpl(Features, "bmi", true); 3298 setFeatureEnabledImpl(Features, "f16c", true); 3299 setFeatureEnabledImpl(Features, "xsaveopt", true); 3300 LLVM_FALLTHROUGH; 3301 case CK_BTVER1: 3302 setFeatureEnabledImpl(Features, "ssse3", true); 3303 setFeatureEnabledImpl(Features, "sse4a", true); 3304 setFeatureEnabledImpl(Features, "lzcnt", true); 3305 setFeatureEnabledImpl(Features, "popcnt", true); 3306 setFeatureEnabledImpl(Features, "prfchw", true); 3307 setFeatureEnabledImpl(Features, "cx16", true); 3308 setFeatureEnabledImpl(Features, "fxsr", true); 3309 break; 3310 case CK_ZNVER1: 3311 setFeatureEnabledImpl(Features, "adx", true); 3312 setFeatureEnabledImpl(Features, "aes", true); 3313 setFeatureEnabledImpl(Features, "avx2", true); 3314 setFeatureEnabledImpl(Features, "bmi", true); 3315 setFeatureEnabledImpl(Features, "bmi2", true); 3316 setFeatureEnabledImpl(Features, "clflushopt", true); 3317 setFeatureEnabledImpl(Features, "clzero", true); 3318 setFeatureEnabledImpl(Features, "cx16", true); 3319 setFeatureEnabledImpl(Features, "f16c", true); 3320 setFeatureEnabledImpl(Features, "fma", true); 3321 setFeatureEnabledImpl(Features, "fsgsbase", true); 3322 setFeatureEnabledImpl(Features, "fxsr", true); 3323 setFeatureEnabledImpl(Features, "lzcnt", true); 3324 setFeatureEnabledImpl(Features, "mwaitx", true); 3325 setFeatureEnabledImpl(Features, "movbe", true); 3326 setFeatureEnabledImpl(Features, "pclmul", true); 3327 setFeatureEnabledImpl(Features, "popcnt", true); 3328 setFeatureEnabledImpl(Features, "prfchw", true); 3329 setFeatureEnabledImpl(Features, "rdrnd", true); 3330 setFeatureEnabledImpl(Features, "rdseed", true); 3331 setFeatureEnabledImpl(Features, "sha", true); 3332 setFeatureEnabledImpl(Features, "sse4a", true); 3333 setFeatureEnabledImpl(Features, "xsave", true); 3334 setFeatureEnabledImpl(Features, "xsavec", true); 3335 setFeatureEnabledImpl(Features, "xsaveopt", true); 3336 setFeatureEnabledImpl(Features, "xsaves", true); 3337 break; 3338 case CK_BDVER4: 3339 setFeatureEnabledImpl(Features, "avx2", true); 3340 setFeatureEnabledImpl(Features, "bmi2", true); 3341 setFeatureEnabledImpl(Features, "mwaitx", true); 3342 LLVM_FALLTHROUGH; 3343 case CK_BDVER3: 3344 setFeatureEnabledImpl(Features, "fsgsbase", true); 3345 setFeatureEnabledImpl(Features, "xsaveopt", true); 3346 LLVM_FALLTHROUGH; 3347 case CK_BDVER2: 3348 setFeatureEnabledImpl(Features, "bmi", true); 3349 setFeatureEnabledImpl(Features, "fma", true); 3350 setFeatureEnabledImpl(Features, "f16c", true); 3351 setFeatureEnabledImpl(Features, "tbm", true); 3352 LLVM_FALLTHROUGH; 3353 case CK_BDVER1: 3354 // xop implies avx, sse4a and fma4. 3355 setFeatureEnabledImpl(Features, "xop", true); 3356 setFeatureEnabledImpl(Features, "lzcnt", true); 3357 setFeatureEnabledImpl(Features, "aes", true); 3358 setFeatureEnabledImpl(Features, "pclmul", true); 3359 setFeatureEnabledImpl(Features, "prfchw", true); 3360 setFeatureEnabledImpl(Features, "cx16", true); 3361 setFeatureEnabledImpl(Features, "fxsr", true); 3362 setFeatureEnabledImpl(Features, "xsave", true); 3363 break; 3364 } 3365 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3366 return false; 3367 3368 // Can't do this earlier because we need to be able to explicitly enable 3369 // or disable these features and the things that they depend upon. 3370 3371 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3372 auto I = Features.find("sse4.2"); 3373 if (I != Features.end() && I->getValue() && 3374 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3375 FeaturesVec.end()) 3376 Features["popcnt"] = true; 3377 3378 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3379 I = Features.find("3dnow"); 3380 if (I != Features.end() && I->getValue() && 3381 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3382 FeaturesVec.end()) 3383 Features["prfchw"] = true; 3384 3385 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3386 // then enable MMX. 3387 I = Features.find("sse"); 3388 if (I != Features.end() && I->getValue() && 3389 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3390 FeaturesVec.end()) 3391 Features["mmx"] = true; 3392 3393 return true; 3394 } 3395 3396 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3397 X86SSEEnum Level, bool Enabled) { 3398 if (Enabled) { 3399 switch (Level) { 3400 case AVX512F: 3401 Features["avx512f"] = true; 3402 case AVX2: 3403 Features["avx2"] = true; 3404 case AVX: 3405 Features["avx"] = true; 3406 Features["xsave"] = true; 3407 case SSE42: 3408 Features["sse4.2"] = true; 3409 case SSE41: 3410 Features["sse4.1"] = true; 3411 case SSSE3: 3412 Features["ssse3"] = true; 3413 case SSE3: 3414 Features["sse3"] = true; 3415 case SSE2: 3416 Features["sse2"] = true; 3417 case SSE1: 3418 Features["sse"] = true; 3419 case NoSSE: 3420 break; 3421 } 3422 return; 3423 } 3424 3425 switch (Level) { 3426 case NoSSE: 3427 case SSE1: 3428 Features["sse"] = false; 3429 case SSE2: 3430 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3431 Features["sha"] = false; 3432 case SSE3: 3433 Features["sse3"] = false; 3434 setXOPLevel(Features, NoXOP, false); 3435 case SSSE3: 3436 Features["ssse3"] = false; 3437 case SSE41: 3438 Features["sse4.1"] = false; 3439 case SSE42: 3440 Features["sse4.2"] = false; 3441 case AVX: 3442 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3443 Features["xsaveopt"] = false; 3444 setXOPLevel(Features, FMA4, false); 3445 case AVX2: 3446 Features["avx2"] = false; 3447 case AVX512F: 3448 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3449 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3450 Features["avx512vl"] = Features["avx512vbmi"] = 3451 Features["avx512ifma"] = false; 3452 } 3453 } 3454 3455 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3456 MMX3DNowEnum Level, bool Enabled) { 3457 if (Enabled) { 3458 switch (Level) { 3459 case AMD3DNowAthlon: 3460 Features["3dnowa"] = true; 3461 case AMD3DNow: 3462 Features["3dnow"] = true; 3463 case MMX: 3464 Features["mmx"] = true; 3465 case NoMMX3DNow: 3466 break; 3467 } 3468 return; 3469 } 3470 3471 switch (Level) { 3472 case NoMMX3DNow: 3473 case MMX: 3474 Features["mmx"] = false; 3475 case AMD3DNow: 3476 Features["3dnow"] = false; 3477 case AMD3DNowAthlon: 3478 Features["3dnowa"] = false; 3479 } 3480 } 3481 3482 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3483 bool Enabled) { 3484 if (Enabled) { 3485 switch (Level) { 3486 case XOP: 3487 Features["xop"] = true; 3488 case FMA4: 3489 Features["fma4"] = true; 3490 setSSELevel(Features, AVX, true); 3491 case SSE4A: 3492 Features["sse4a"] = true; 3493 setSSELevel(Features, SSE3, true); 3494 case NoXOP: 3495 break; 3496 } 3497 return; 3498 } 3499 3500 switch (Level) { 3501 case NoXOP: 3502 case SSE4A: 3503 Features["sse4a"] = false; 3504 case FMA4: 3505 Features["fma4"] = false; 3506 case XOP: 3507 Features["xop"] = false; 3508 } 3509 } 3510 3511 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3512 StringRef Name, bool Enabled) { 3513 // This is a bit of a hack to deal with the sse4 target feature when used 3514 // as part of the target attribute. We handle sse4 correctly everywhere 3515 // else. See below for more information on how we handle the sse4 options. 3516 if (Name != "sse4") 3517 Features[Name] = Enabled; 3518 3519 if (Name == "mmx") { 3520 setMMXLevel(Features, MMX, Enabled); 3521 } else if (Name == "sse") { 3522 setSSELevel(Features, SSE1, Enabled); 3523 } else if (Name == "sse2") { 3524 setSSELevel(Features, SSE2, Enabled); 3525 } else if (Name == "sse3") { 3526 setSSELevel(Features, SSE3, Enabled); 3527 } else if (Name == "ssse3") { 3528 setSSELevel(Features, SSSE3, Enabled); 3529 } else if (Name == "sse4.2") { 3530 setSSELevel(Features, SSE42, Enabled); 3531 } else if (Name == "sse4.1") { 3532 setSSELevel(Features, SSE41, Enabled); 3533 } else if (Name == "3dnow") { 3534 setMMXLevel(Features, AMD3DNow, Enabled); 3535 } else if (Name == "3dnowa") { 3536 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3537 } else if (Name == "aes") { 3538 if (Enabled) 3539 setSSELevel(Features, SSE2, Enabled); 3540 } else if (Name == "pclmul") { 3541 if (Enabled) 3542 setSSELevel(Features, SSE2, Enabled); 3543 } else if (Name == "avx") { 3544 setSSELevel(Features, AVX, Enabled); 3545 } else if (Name == "avx2") { 3546 setSSELevel(Features, AVX2, Enabled); 3547 } else if (Name == "avx512f") { 3548 setSSELevel(Features, AVX512F, Enabled); 3549 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3550 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3551 Name == "avx512vbmi" || Name == "avx512ifma") { 3552 if (Enabled) 3553 setSSELevel(Features, AVX512F, Enabled); 3554 // Enable BWI instruction if VBMI is being enabled. 3555 if (Name == "avx512vbmi" && Enabled) 3556 Features["avx512bw"] = true; 3557 // Also disable VBMI if BWI is being disabled. 3558 if (Name == "avx512bw" && !Enabled) 3559 Features["avx512vbmi"] = false; 3560 } else if (Name == "fma") { 3561 if (Enabled) 3562 setSSELevel(Features, AVX, Enabled); 3563 } else if (Name == "fma4") { 3564 setXOPLevel(Features, FMA4, Enabled); 3565 } else if (Name == "xop") { 3566 setXOPLevel(Features, XOP, Enabled); 3567 } else if (Name == "sse4a") { 3568 setXOPLevel(Features, SSE4A, Enabled); 3569 } else if (Name == "f16c") { 3570 if (Enabled) 3571 setSSELevel(Features, AVX, Enabled); 3572 } else if (Name == "sha") { 3573 if (Enabled) 3574 setSSELevel(Features, SSE2, Enabled); 3575 } else if (Name == "sse4") { 3576 // We can get here via the __target__ attribute since that's not controlled 3577 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3578 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3579 // disabled. 3580 if (Enabled) 3581 setSSELevel(Features, SSE42, Enabled); 3582 else 3583 setSSELevel(Features, SSE41, Enabled); 3584 } else if (Name == "xsave") { 3585 if (!Enabled) 3586 Features["xsaveopt"] = false; 3587 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3588 if (Enabled) 3589 Features["xsave"] = true; 3590 } 3591 } 3592 3593 /// handleTargetFeatures - Perform initialization based on the user 3594 /// configured set of features. 3595 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3596 DiagnosticsEngine &Diags) { 3597 for (const auto &Feature : Features) { 3598 if (Feature[0] != '+') 3599 continue; 3600 3601 if (Feature == "+aes") { 3602 HasAES = true; 3603 } else if (Feature == "+pclmul") { 3604 HasPCLMUL = true; 3605 } else if (Feature == "+lzcnt") { 3606 HasLZCNT = true; 3607 } else if (Feature == "+rdrnd") { 3608 HasRDRND = true; 3609 } else if (Feature == "+fsgsbase") { 3610 HasFSGSBASE = true; 3611 } else if (Feature == "+bmi") { 3612 HasBMI = true; 3613 } else if (Feature == "+bmi2") { 3614 HasBMI2 = true; 3615 } else if (Feature == "+popcnt") { 3616 HasPOPCNT = true; 3617 } else if (Feature == "+rtm") { 3618 HasRTM = true; 3619 } else if (Feature == "+prfchw") { 3620 HasPRFCHW = true; 3621 } else if (Feature == "+rdseed") { 3622 HasRDSEED = true; 3623 } else if (Feature == "+adx") { 3624 HasADX = true; 3625 } else if (Feature == "+tbm") { 3626 HasTBM = true; 3627 } else if (Feature == "+fma") { 3628 HasFMA = true; 3629 } else if (Feature == "+f16c") { 3630 HasF16C = true; 3631 } else if (Feature == "+avx512cd") { 3632 HasAVX512CD = true; 3633 } else if (Feature == "+avx512er") { 3634 HasAVX512ER = true; 3635 } else if (Feature == "+avx512pf") { 3636 HasAVX512PF = true; 3637 } else if (Feature == "+avx512dq") { 3638 HasAVX512DQ = true; 3639 } else if (Feature == "+avx512bw") { 3640 HasAVX512BW = true; 3641 } else if (Feature == "+avx512vl") { 3642 HasAVX512VL = true; 3643 } else if (Feature == "+avx512vbmi") { 3644 HasAVX512VBMI = true; 3645 } else if (Feature == "+avx512ifma") { 3646 HasAVX512IFMA = true; 3647 } else if (Feature == "+sha") { 3648 HasSHA = true; 3649 } else if (Feature == "+mpx") { 3650 HasMPX = true; 3651 } else if (Feature == "+movbe") { 3652 HasMOVBE = true; 3653 } else if (Feature == "+sgx") { 3654 HasSGX = true; 3655 } else if (Feature == "+cx16") { 3656 HasCX16 = true; 3657 } else if (Feature == "+fxsr") { 3658 HasFXSR = true; 3659 } else if (Feature == "+xsave") { 3660 HasXSAVE = true; 3661 } else if (Feature == "+xsaveopt") { 3662 HasXSAVEOPT = true; 3663 } else if (Feature == "+xsavec") { 3664 HasXSAVEC = true; 3665 } else if (Feature == "+xsaves") { 3666 HasXSAVES = true; 3667 } else if (Feature == "+mwaitx") { 3668 HasMWAITX = true; 3669 } else if (Feature == "+pku") { 3670 HasPKU = true; 3671 } else if (Feature == "+clflushopt") { 3672 HasCLFLUSHOPT = true; 3673 } else if (Feature == "+clwb") { 3674 HasCLWB = true; 3675 } else if (Feature == "+prefetchwt1") { 3676 HasPREFETCHWT1 = true; 3677 } else if (Feature == "+clzero") { 3678 HasCLZERO = true; 3679 } 3680 3681 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3682 .Case("+avx512f", AVX512F) 3683 .Case("+avx2", AVX2) 3684 .Case("+avx", AVX) 3685 .Case("+sse4.2", SSE42) 3686 .Case("+sse4.1", SSE41) 3687 .Case("+ssse3", SSSE3) 3688 .Case("+sse3", SSE3) 3689 .Case("+sse2", SSE2) 3690 .Case("+sse", SSE1) 3691 .Default(NoSSE); 3692 SSELevel = std::max(SSELevel, Level); 3693 3694 MMX3DNowEnum ThreeDNowLevel = 3695 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3696 .Case("+3dnowa", AMD3DNowAthlon) 3697 .Case("+3dnow", AMD3DNow) 3698 .Case("+mmx", MMX) 3699 .Default(NoMMX3DNow); 3700 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3701 3702 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3703 .Case("+xop", XOP) 3704 .Case("+fma4", FMA4) 3705 .Case("+sse4a", SSE4A) 3706 .Default(NoXOP); 3707 XOPLevel = std::max(XOPLevel, XLevel); 3708 } 3709 3710 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3711 // matches the selected sse level. 3712 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3713 (FPMath == FP_387 && SSELevel >= SSE1)) { 3714 Diags.Report(diag::err_target_unsupported_fpmath) << 3715 (FPMath == FP_SSE ? "sse" : "387"); 3716 return false; 3717 } 3718 3719 SimdDefaultAlign = 3720 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3721 return true; 3722 } 3723 3724 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3725 /// definitions for this particular subtarget. 3726 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3727 MacroBuilder &Builder) const { 3728 // Target identification. 3729 if (getTriple().getArch() == llvm::Triple::x86_64) { 3730 Builder.defineMacro("__amd64__"); 3731 Builder.defineMacro("__amd64"); 3732 Builder.defineMacro("__x86_64"); 3733 Builder.defineMacro("__x86_64__"); 3734 if (getTriple().getArchName() == "x86_64h") { 3735 Builder.defineMacro("__x86_64h"); 3736 Builder.defineMacro("__x86_64h__"); 3737 } 3738 } else { 3739 DefineStd(Builder, "i386", Opts); 3740 } 3741 3742 // Subtarget options. 3743 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3744 // truly should be based on -mtune options. 3745 switch (CPU) { 3746 case CK_Generic: 3747 break; 3748 case CK_i386: 3749 // The rest are coming from the i386 define above. 3750 Builder.defineMacro("__tune_i386__"); 3751 break; 3752 case CK_i486: 3753 case CK_WinChipC6: 3754 case CK_WinChip2: 3755 case CK_C3: 3756 defineCPUMacros(Builder, "i486"); 3757 break; 3758 case CK_PentiumMMX: 3759 Builder.defineMacro("__pentium_mmx__"); 3760 Builder.defineMacro("__tune_pentium_mmx__"); 3761 // Fallthrough 3762 case CK_i586: 3763 case CK_Pentium: 3764 defineCPUMacros(Builder, "i586"); 3765 defineCPUMacros(Builder, "pentium"); 3766 break; 3767 case CK_Pentium3: 3768 case CK_Pentium3M: 3769 case CK_PentiumM: 3770 Builder.defineMacro("__tune_pentium3__"); 3771 // Fallthrough 3772 case CK_Pentium2: 3773 case CK_C3_2: 3774 Builder.defineMacro("__tune_pentium2__"); 3775 // Fallthrough 3776 case CK_PentiumPro: 3777 Builder.defineMacro("__tune_i686__"); 3778 Builder.defineMacro("__tune_pentiumpro__"); 3779 // Fallthrough 3780 case CK_i686: 3781 Builder.defineMacro("__i686"); 3782 Builder.defineMacro("__i686__"); 3783 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3784 Builder.defineMacro("__pentiumpro"); 3785 Builder.defineMacro("__pentiumpro__"); 3786 break; 3787 case CK_Pentium4: 3788 case CK_Pentium4M: 3789 defineCPUMacros(Builder, "pentium4"); 3790 break; 3791 case CK_Yonah: 3792 case CK_Prescott: 3793 case CK_Nocona: 3794 defineCPUMacros(Builder, "nocona"); 3795 break; 3796 case CK_Core2: 3797 case CK_Penryn: 3798 defineCPUMacros(Builder, "core2"); 3799 break; 3800 case CK_Bonnell: 3801 defineCPUMacros(Builder, "atom"); 3802 break; 3803 case CK_Silvermont: 3804 defineCPUMacros(Builder, "slm"); 3805 break; 3806 case CK_Nehalem: 3807 case CK_Westmere: 3808 case CK_SandyBridge: 3809 case CK_IvyBridge: 3810 case CK_Haswell: 3811 case CK_Broadwell: 3812 case CK_SkylakeClient: 3813 // FIXME: Historically, we defined this legacy name, it would be nice to 3814 // remove it at some point. We've never exposed fine-grained names for 3815 // recent primary x86 CPUs, and we should keep it that way. 3816 defineCPUMacros(Builder, "corei7"); 3817 break; 3818 case CK_SkylakeServer: 3819 defineCPUMacros(Builder, "skx"); 3820 break; 3821 case CK_Cannonlake: 3822 break; 3823 case CK_KNL: 3824 defineCPUMacros(Builder, "knl"); 3825 break; 3826 case CK_Lakemont: 3827 Builder.defineMacro("__tune_lakemont__"); 3828 break; 3829 case CK_K6_2: 3830 Builder.defineMacro("__k6_2__"); 3831 Builder.defineMacro("__tune_k6_2__"); 3832 // Fallthrough 3833 case CK_K6_3: 3834 if (CPU != CK_K6_2) { // In case of fallthrough 3835 // FIXME: GCC may be enabling these in cases where some other k6 3836 // architecture is specified but -m3dnow is explicitly provided. The 3837 // exact semantics need to be determined and emulated here. 3838 Builder.defineMacro("__k6_3__"); 3839 Builder.defineMacro("__tune_k6_3__"); 3840 } 3841 // Fallthrough 3842 case CK_K6: 3843 defineCPUMacros(Builder, "k6"); 3844 break; 3845 case CK_Athlon: 3846 case CK_AthlonThunderbird: 3847 case CK_Athlon4: 3848 case CK_AthlonXP: 3849 case CK_AthlonMP: 3850 defineCPUMacros(Builder, "athlon"); 3851 if (SSELevel != NoSSE) { 3852 Builder.defineMacro("__athlon_sse__"); 3853 Builder.defineMacro("__tune_athlon_sse__"); 3854 } 3855 break; 3856 case CK_K8: 3857 case CK_K8SSE3: 3858 case CK_x86_64: 3859 case CK_Opteron: 3860 case CK_OpteronSSE3: 3861 case CK_Athlon64: 3862 case CK_Athlon64SSE3: 3863 case CK_AthlonFX: 3864 defineCPUMacros(Builder, "k8"); 3865 break; 3866 case CK_AMDFAM10: 3867 defineCPUMacros(Builder, "amdfam10"); 3868 break; 3869 case CK_BTVER1: 3870 defineCPUMacros(Builder, "btver1"); 3871 break; 3872 case CK_BTVER2: 3873 defineCPUMacros(Builder, "btver2"); 3874 break; 3875 case CK_BDVER1: 3876 defineCPUMacros(Builder, "bdver1"); 3877 break; 3878 case CK_BDVER2: 3879 defineCPUMacros(Builder, "bdver2"); 3880 break; 3881 case CK_BDVER3: 3882 defineCPUMacros(Builder, "bdver3"); 3883 break; 3884 case CK_BDVER4: 3885 defineCPUMacros(Builder, "bdver4"); 3886 break; 3887 case CK_ZNVER1: 3888 defineCPUMacros(Builder, "znver1"); 3889 break; 3890 case CK_Geode: 3891 defineCPUMacros(Builder, "geode"); 3892 break; 3893 } 3894 3895 // Target properties. 3896 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3897 3898 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3899 // functions in glibc header files that use FP Stack inline asm which the 3900 // backend can't deal with (PR879). 3901 Builder.defineMacro("__NO_MATH_INLINES"); 3902 3903 if (HasAES) 3904 Builder.defineMacro("__AES__"); 3905 3906 if (HasPCLMUL) 3907 Builder.defineMacro("__PCLMUL__"); 3908 3909 if (HasLZCNT) 3910 Builder.defineMacro("__LZCNT__"); 3911 3912 if (HasRDRND) 3913 Builder.defineMacro("__RDRND__"); 3914 3915 if (HasFSGSBASE) 3916 Builder.defineMacro("__FSGSBASE__"); 3917 3918 if (HasBMI) 3919 Builder.defineMacro("__BMI__"); 3920 3921 if (HasBMI2) 3922 Builder.defineMacro("__BMI2__"); 3923 3924 if (HasPOPCNT) 3925 Builder.defineMacro("__POPCNT__"); 3926 3927 if (HasRTM) 3928 Builder.defineMacro("__RTM__"); 3929 3930 if (HasPRFCHW) 3931 Builder.defineMacro("__PRFCHW__"); 3932 3933 if (HasRDSEED) 3934 Builder.defineMacro("__RDSEED__"); 3935 3936 if (HasADX) 3937 Builder.defineMacro("__ADX__"); 3938 3939 if (HasTBM) 3940 Builder.defineMacro("__TBM__"); 3941 3942 if (HasMWAITX) 3943 Builder.defineMacro("__MWAITX__"); 3944 3945 switch (XOPLevel) { 3946 case XOP: 3947 Builder.defineMacro("__XOP__"); 3948 case FMA4: 3949 Builder.defineMacro("__FMA4__"); 3950 case SSE4A: 3951 Builder.defineMacro("__SSE4A__"); 3952 case NoXOP: 3953 break; 3954 } 3955 3956 if (HasFMA) 3957 Builder.defineMacro("__FMA__"); 3958 3959 if (HasF16C) 3960 Builder.defineMacro("__F16C__"); 3961 3962 if (HasAVX512CD) 3963 Builder.defineMacro("__AVX512CD__"); 3964 if (HasAVX512ER) 3965 Builder.defineMacro("__AVX512ER__"); 3966 if (HasAVX512PF) 3967 Builder.defineMacro("__AVX512PF__"); 3968 if (HasAVX512DQ) 3969 Builder.defineMacro("__AVX512DQ__"); 3970 if (HasAVX512BW) 3971 Builder.defineMacro("__AVX512BW__"); 3972 if (HasAVX512VL) 3973 Builder.defineMacro("__AVX512VL__"); 3974 if (HasAVX512VBMI) 3975 Builder.defineMacro("__AVX512VBMI__"); 3976 if (HasAVX512IFMA) 3977 Builder.defineMacro("__AVX512IFMA__"); 3978 3979 if (HasSHA) 3980 Builder.defineMacro("__SHA__"); 3981 3982 if (HasFXSR) 3983 Builder.defineMacro("__FXSR__"); 3984 if (HasXSAVE) 3985 Builder.defineMacro("__XSAVE__"); 3986 if (HasXSAVEOPT) 3987 Builder.defineMacro("__XSAVEOPT__"); 3988 if (HasXSAVEC) 3989 Builder.defineMacro("__XSAVEC__"); 3990 if (HasXSAVES) 3991 Builder.defineMacro("__XSAVES__"); 3992 if (HasPKU) 3993 Builder.defineMacro("__PKU__"); 3994 if (HasCX16) 3995 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3996 if (HasCLFLUSHOPT) 3997 Builder.defineMacro("__CLFLUSHOPT__"); 3998 if (HasCLWB) 3999 Builder.defineMacro("__CLWB__"); 4000 if (HasMPX) 4001 Builder.defineMacro("__MPX__"); 4002 if (HasSGX) 4003 Builder.defineMacro("__SGX__"); 4004 if (HasPREFETCHWT1) 4005 Builder.defineMacro("__PREFETCHWT1__"); 4006 if (HasCLZERO) 4007 Builder.defineMacro("__CLZERO__"); 4008 4009 // Each case falls through to the previous one here. 4010 switch (SSELevel) { 4011 case AVX512F: 4012 Builder.defineMacro("__AVX512F__"); 4013 case AVX2: 4014 Builder.defineMacro("__AVX2__"); 4015 case AVX: 4016 Builder.defineMacro("__AVX__"); 4017 case SSE42: 4018 Builder.defineMacro("__SSE4_2__"); 4019 case SSE41: 4020 Builder.defineMacro("__SSE4_1__"); 4021 case SSSE3: 4022 Builder.defineMacro("__SSSE3__"); 4023 case SSE3: 4024 Builder.defineMacro("__SSE3__"); 4025 case SSE2: 4026 Builder.defineMacro("__SSE2__"); 4027 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4028 case SSE1: 4029 Builder.defineMacro("__SSE__"); 4030 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4031 case NoSSE: 4032 break; 4033 } 4034 4035 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4036 switch (SSELevel) { 4037 case AVX512F: 4038 case AVX2: 4039 case AVX: 4040 case SSE42: 4041 case SSE41: 4042 case SSSE3: 4043 case SSE3: 4044 case SSE2: 4045 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4046 break; 4047 case SSE1: 4048 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4049 break; 4050 default: 4051 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4052 } 4053 } 4054 4055 // Each case falls through to the previous one here. 4056 switch (MMX3DNowLevel) { 4057 case AMD3DNowAthlon: 4058 Builder.defineMacro("__3dNOW_A__"); 4059 case AMD3DNow: 4060 Builder.defineMacro("__3dNOW__"); 4061 case MMX: 4062 Builder.defineMacro("__MMX__"); 4063 case NoMMX3DNow: 4064 break; 4065 } 4066 4067 if (CPU >= CK_i486) { 4068 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4069 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4070 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4071 } 4072 if (CPU >= CK_i586) 4073 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4074 } 4075 4076 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4077 return llvm::StringSwitch<bool>(Feature) 4078 .Case("aes", HasAES) 4079 .Case("avx", SSELevel >= AVX) 4080 .Case("avx2", SSELevel >= AVX2) 4081 .Case("avx512f", SSELevel >= AVX512F) 4082 .Case("avx512cd", HasAVX512CD) 4083 .Case("avx512er", HasAVX512ER) 4084 .Case("avx512pf", HasAVX512PF) 4085 .Case("avx512dq", HasAVX512DQ) 4086 .Case("avx512bw", HasAVX512BW) 4087 .Case("avx512vl", HasAVX512VL) 4088 .Case("avx512vbmi", HasAVX512VBMI) 4089 .Case("avx512ifma", HasAVX512IFMA) 4090 .Case("bmi", HasBMI) 4091 .Case("bmi2", HasBMI2) 4092 .Case("clflushopt", HasCLFLUSHOPT) 4093 .Case("clwb", HasCLWB) 4094 .Case("clzero", HasCLZERO) 4095 .Case("cx16", HasCX16) 4096 .Case("f16c", HasF16C) 4097 .Case("fma", HasFMA) 4098 .Case("fma4", XOPLevel >= FMA4) 4099 .Case("fsgsbase", HasFSGSBASE) 4100 .Case("fxsr", HasFXSR) 4101 .Case("lzcnt", HasLZCNT) 4102 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4103 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4104 .Case("mmx", MMX3DNowLevel >= MMX) 4105 .Case("movbe", HasMOVBE) 4106 .Case("mpx", HasMPX) 4107 .Case("pclmul", HasPCLMUL) 4108 .Case("pku", HasPKU) 4109 .Case("popcnt", HasPOPCNT) 4110 .Case("prefetchwt1", HasPREFETCHWT1) 4111 .Case("prfchw", HasPRFCHW) 4112 .Case("rdrnd", HasRDRND) 4113 .Case("rdseed", HasRDSEED) 4114 .Case("rtm", HasRTM) 4115 .Case("sgx", HasSGX) 4116 .Case("sha", HasSHA) 4117 .Case("sse", SSELevel >= SSE1) 4118 .Case("sse2", SSELevel >= SSE2) 4119 .Case("sse3", SSELevel >= SSE3) 4120 .Case("ssse3", SSELevel >= SSSE3) 4121 .Case("sse4.1", SSELevel >= SSE41) 4122 .Case("sse4.2", SSELevel >= SSE42) 4123 .Case("sse4a", XOPLevel >= SSE4A) 4124 .Case("tbm", HasTBM) 4125 .Case("x86", true) 4126 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4127 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4128 .Case("xop", XOPLevel >= XOP) 4129 .Case("xsave", HasXSAVE) 4130 .Case("xsavec", HasXSAVEC) 4131 .Case("xsaves", HasXSAVES) 4132 .Case("xsaveopt", HasXSAVEOPT) 4133 .Default(false); 4134 } 4135 4136 // We can't use a generic validation scheme for the features accepted here 4137 // versus subtarget features accepted in the target attribute because the 4138 // bitfield structure that's initialized in the runtime only supports the 4139 // below currently rather than the full range of subtarget features. (See 4140 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4141 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4142 return llvm::StringSwitch<bool>(FeatureStr) 4143 .Case("cmov", true) 4144 .Case("mmx", true) 4145 .Case("popcnt", true) 4146 .Case("sse", true) 4147 .Case("sse2", true) 4148 .Case("sse3", true) 4149 .Case("ssse3", true) 4150 .Case("sse4.1", true) 4151 .Case("sse4.2", true) 4152 .Case("avx", true) 4153 .Case("avx2", true) 4154 .Case("sse4a", true) 4155 .Case("fma4", true) 4156 .Case("xop", true) 4157 .Case("fma", true) 4158 .Case("avx512f", true) 4159 .Case("bmi", true) 4160 .Case("bmi2", true) 4161 .Case("aes", true) 4162 .Case("pclmul", true) 4163 .Case("avx512vl", true) 4164 .Case("avx512bw", true) 4165 .Case("avx512dq", true) 4166 .Case("avx512cd", true) 4167 .Case("avx512er", true) 4168 .Case("avx512pf", true) 4169 .Case("avx512vbmi", true) 4170 .Case("avx512ifma", true) 4171 .Default(false); 4172 } 4173 4174 bool 4175 X86TargetInfo::validateAsmConstraint(const char *&Name, 4176 TargetInfo::ConstraintInfo &Info) const { 4177 switch (*Name) { 4178 default: return false; 4179 // Constant constraints. 4180 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4181 // instructions. 4182 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4183 // x86_64 instructions. 4184 case 's': 4185 Info.setRequiresImmediate(); 4186 return true; 4187 case 'I': 4188 Info.setRequiresImmediate(0, 31); 4189 return true; 4190 case 'J': 4191 Info.setRequiresImmediate(0, 63); 4192 return true; 4193 case 'K': 4194 Info.setRequiresImmediate(-128, 127); 4195 return true; 4196 case 'L': 4197 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4198 return true; 4199 case 'M': 4200 Info.setRequiresImmediate(0, 3); 4201 return true; 4202 case 'N': 4203 Info.setRequiresImmediate(0, 255); 4204 return true; 4205 case 'O': 4206 Info.setRequiresImmediate(0, 127); 4207 return true; 4208 // Register constraints. 4209 case 'Y': // 'Y' is the first character for several 2-character constraints. 4210 // Shift the pointer to the second character of the constraint. 4211 Name++; 4212 switch (*Name) { 4213 default: 4214 return false; 4215 case '0': // First SSE register. 4216 case 't': // Any SSE register, when SSE2 is enabled. 4217 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4218 case 'm': // Any MMX register, when inter-unit moves enabled. 4219 case 'k': // AVX512 arch mask registers: k1-k7. 4220 Info.setAllowsRegister(); 4221 return true; 4222 } 4223 case 'f': // Any x87 floating point stack register. 4224 // Constraint 'f' cannot be used for output operands. 4225 if (Info.ConstraintStr[0] == '=') 4226 return false; 4227 Info.setAllowsRegister(); 4228 return true; 4229 case 'a': // eax. 4230 case 'b': // ebx. 4231 case 'c': // ecx. 4232 case 'd': // edx. 4233 case 'S': // esi. 4234 case 'D': // edi. 4235 case 'A': // edx:eax. 4236 case 't': // Top of floating point stack. 4237 case 'u': // Second from top of floating point stack. 4238 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4239 case 'y': // Any MMX register. 4240 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4241 case 'x': // Any SSE register. 4242 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4243 // for intermideate k reg operations). 4244 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4245 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4246 case 'l': // "Index" registers: any general register that can be used as an 4247 // index in a base+index memory access. 4248 Info.setAllowsRegister(); 4249 return true; 4250 // Floating point constant constraints. 4251 case 'C': // SSE floating point constant. 4252 case 'G': // x87 floating point constant. 4253 return true; 4254 } 4255 } 4256 4257 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4258 unsigned Size) const { 4259 // Strip off constraint modifiers. 4260 while (Constraint[0] == '=' || 4261 Constraint[0] == '+' || 4262 Constraint[0] == '&') 4263 Constraint = Constraint.substr(1); 4264 4265 return validateOperandSize(Constraint, Size); 4266 } 4267 4268 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4269 unsigned Size) const { 4270 return validateOperandSize(Constraint, Size); 4271 } 4272 4273 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4274 unsigned Size) const { 4275 switch (Constraint[0]) { 4276 default: break; 4277 case 'k': 4278 // Registers k0-k7 (AVX512) size limit is 64 bit. 4279 case 'y': 4280 return Size <= 64; 4281 case 'f': 4282 case 't': 4283 case 'u': 4284 return Size <= 128; 4285 case 'v': 4286 case 'x': 4287 if (SSELevel >= AVX512F) 4288 // 512-bit zmm registers can be used if target supports AVX512F. 4289 return Size <= 512U; 4290 else if (SSELevel >= AVX) 4291 // 256-bit ymm registers can be used if target supports AVX. 4292 return Size <= 256U; 4293 return Size <= 128U; 4294 case 'Y': 4295 // 'Y' is the first character for several 2-character constraints. 4296 switch (Constraint[1]) { 4297 default: break; 4298 case 'm': 4299 // 'Ym' is synonymous with 'y'. 4300 case 'k': 4301 return Size <= 64; 4302 case 'i': 4303 case 't': 4304 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4305 if (SSELevel >= AVX512F) 4306 return Size <= 512U; 4307 else if (SSELevel >= AVX) 4308 return Size <= 256U; 4309 return SSELevel >= SSE2 && Size <= 128U; 4310 } 4311 4312 } 4313 4314 return true; 4315 } 4316 4317 std::string 4318 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4319 switch (*Constraint) { 4320 case 'a': return std::string("{ax}"); 4321 case 'b': return std::string("{bx}"); 4322 case 'c': return std::string("{cx}"); 4323 case 'd': return std::string("{dx}"); 4324 case 'S': return std::string("{si}"); 4325 case 'D': return std::string("{di}"); 4326 case 'p': // address 4327 return std::string("im"); 4328 case 't': // top of floating point stack. 4329 return std::string("{st}"); 4330 case 'u': // second from top of floating point stack. 4331 return std::string("{st(1)}"); // second from top of floating point stack. 4332 case 'Y': 4333 switch (Constraint[1]) { 4334 default: 4335 // Break from inner switch and fall through (copy single char), 4336 // continue parsing after copying the current constraint into 4337 // the return string. 4338 break; 4339 case 'k': 4340 // "^" hints llvm that this is a 2 letter constraint. 4341 // "Constraint++" is used to promote the string iterator 4342 // to the next constraint. 4343 return std::string("^") + std::string(Constraint++, 2); 4344 } 4345 LLVM_FALLTHROUGH; 4346 default: 4347 return std::string(1, *Constraint); 4348 } 4349 } 4350 4351 // X86-32 generic target 4352 class X86_32TargetInfo : public X86TargetInfo { 4353 public: 4354 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4355 : X86TargetInfo(Triple, Opts) { 4356 DoubleAlign = LongLongAlign = 32; 4357 LongDoubleWidth = 96; 4358 LongDoubleAlign = 32; 4359 SuitableAlign = 128; 4360 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4361 SizeType = UnsignedInt; 4362 PtrDiffType = SignedInt; 4363 IntPtrType = SignedInt; 4364 RegParmMax = 3; 4365 4366 // Use fpret for all types. 4367 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4368 (1 << TargetInfo::Double) | 4369 (1 << TargetInfo::LongDouble)); 4370 4371 // x86-32 has atomics up to 8 bytes 4372 // FIXME: Check that we actually have cmpxchg8b before setting 4373 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4374 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4375 } 4376 BuiltinVaListKind getBuiltinVaListKind() const override { 4377 return TargetInfo::CharPtrBuiltinVaList; 4378 } 4379 4380 int getEHDataRegisterNumber(unsigned RegNo) const override { 4381 if (RegNo == 0) return 0; 4382 if (RegNo == 1) return 2; 4383 return -1; 4384 } 4385 bool validateOperandSize(StringRef Constraint, 4386 unsigned Size) const override { 4387 switch (Constraint[0]) { 4388 default: break; 4389 case 'R': 4390 case 'q': 4391 case 'Q': 4392 case 'a': 4393 case 'b': 4394 case 'c': 4395 case 'd': 4396 case 'S': 4397 case 'D': 4398 return Size <= 32; 4399 case 'A': 4400 return Size <= 64; 4401 } 4402 4403 return X86TargetInfo::validateOperandSize(Constraint, Size); 4404 } 4405 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4406 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4407 Builtin::FirstTSBuiltin + 1); 4408 } 4409 }; 4410 4411 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4412 public: 4413 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4414 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4415 4416 unsigned getFloatEvalMethod() const override { 4417 unsigned Major, Minor, Micro; 4418 getTriple().getOSVersion(Major, Minor, Micro); 4419 // New NetBSD uses the default rounding mode. 4420 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4421 return X86_32TargetInfo::getFloatEvalMethod(); 4422 // NetBSD before 6.99.26 defaults to "double" rounding. 4423 return 1; 4424 } 4425 }; 4426 4427 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4428 public: 4429 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4430 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4431 SizeType = UnsignedLong; 4432 IntPtrType = SignedLong; 4433 PtrDiffType = SignedLong; 4434 } 4435 }; 4436 4437 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4438 public: 4439 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4440 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4441 SizeType = UnsignedLong; 4442 IntPtrType = SignedLong; 4443 PtrDiffType = SignedLong; 4444 } 4445 }; 4446 4447 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4448 public: 4449 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4450 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4451 LongDoubleWidth = 128; 4452 LongDoubleAlign = 128; 4453 SuitableAlign = 128; 4454 MaxVectorAlign = 256; 4455 // The watchOS simulator uses the builtin bool type for Objective-C. 4456 llvm::Triple T = llvm::Triple(Triple); 4457 if (T.isWatchOS()) 4458 UseSignedCharForObjCBool = false; 4459 SizeType = UnsignedLong; 4460 IntPtrType = SignedLong; 4461 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4462 HasAlignMac68kSupport = true; 4463 } 4464 4465 bool handleTargetFeatures(std::vector<std::string> &Features, 4466 DiagnosticsEngine &Diags) override { 4467 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4468 Diags)) 4469 return false; 4470 // We now know the features we have: we can decide how to align vectors. 4471 MaxVectorAlign = 4472 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4473 return true; 4474 } 4475 }; 4476 4477 // x86-32 Windows target 4478 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4479 public: 4480 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4481 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4482 WCharType = UnsignedShort; 4483 DoubleAlign = LongLongAlign = 64; 4484 bool IsWinCOFF = 4485 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4486 resetDataLayout(IsWinCOFF 4487 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4488 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4489 } 4490 void getTargetDefines(const LangOptions &Opts, 4491 MacroBuilder &Builder) const override { 4492 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4493 } 4494 }; 4495 4496 // x86-32 Windows Visual Studio target 4497 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4498 public: 4499 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4500 const TargetOptions &Opts) 4501 : WindowsX86_32TargetInfo(Triple, Opts) { 4502 LongDoubleWidth = LongDoubleAlign = 64; 4503 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4504 } 4505 void getTargetDefines(const LangOptions &Opts, 4506 MacroBuilder &Builder) const override { 4507 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4508 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4509 // The value of the following reflects processor type. 4510 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4511 // We lost the original triple, so we use the default. 4512 Builder.defineMacro("_M_IX86", "600"); 4513 } 4514 }; 4515 4516 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4517 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4518 // supports __declspec natively under -fms-extensions, but we define a no-op 4519 // __declspec macro anyway for pre-processor compatibility. 4520 if (Opts.MicrosoftExt) 4521 Builder.defineMacro("__declspec", "__declspec"); 4522 else 4523 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4524 4525 if (!Opts.MicrosoftExt) { 4526 // Provide macros for all the calling convention keywords. Provide both 4527 // single and double underscore prefixed variants. These are available on 4528 // x64 as well as x86, even though they have no effect. 4529 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4530 for (const char *CC : CCs) { 4531 std::string GCCSpelling = "__attribute__((__"; 4532 GCCSpelling += CC; 4533 GCCSpelling += "__))"; 4534 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4535 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4536 } 4537 } 4538 } 4539 4540 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4541 Builder.defineMacro("__MSVCRT__"); 4542 Builder.defineMacro("__MINGW32__"); 4543 addCygMingDefines(Opts, Builder); 4544 } 4545 4546 // x86-32 MinGW target 4547 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4548 public: 4549 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4550 : WindowsX86_32TargetInfo(Triple, Opts) {} 4551 void getTargetDefines(const LangOptions &Opts, 4552 MacroBuilder &Builder) const override { 4553 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4554 DefineStd(Builder, "WIN32", Opts); 4555 DefineStd(Builder, "WINNT", Opts); 4556 Builder.defineMacro("_X86_"); 4557 addMinGWDefines(Opts, Builder); 4558 } 4559 }; 4560 4561 // x86-32 Cygwin target 4562 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4563 public: 4564 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4565 : X86_32TargetInfo(Triple, Opts) { 4566 WCharType = UnsignedShort; 4567 DoubleAlign = LongLongAlign = 64; 4568 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4569 } 4570 void getTargetDefines(const LangOptions &Opts, 4571 MacroBuilder &Builder) const override { 4572 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4573 Builder.defineMacro("_X86_"); 4574 Builder.defineMacro("__CYGWIN__"); 4575 Builder.defineMacro("__CYGWIN32__"); 4576 addCygMingDefines(Opts, Builder); 4577 DefineStd(Builder, "unix", Opts); 4578 if (Opts.CPlusPlus) 4579 Builder.defineMacro("_GNU_SOURCE"); 4580 } 4581 }; 4582 4583 // x86-32 Haiku target 4584 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4585 public: 4586 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4587 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4588 } 4589 void getTargetDefines(const LangOptions &Opts, 4590 MacroBuilder &Builder) const override { 4591 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4592 Builder.defineMacro("__INTEL__"); 4593 } 4594 }; 4595 4596 // X86-32 MCU target 4597 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4598 public: 4599 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4600 : X86_32TargetInfo(Triple, Opts) { 4601 LongDoubleWidth = 64; 4602 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4603 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4604 WIntType = UnsignedInt; 4605 } 4606 4607 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4608 // On MCU we support only C calling convention. 4609 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4610 } 4611 4612 void getTargetDefines(const LangOptions &Opts, 4613 MacroBuilder &Builder) const override { 4614 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4615 Builder.defineMacro("__iamcu"); 4616 Builder.defineMacro("__iamcu__"); 4617 } 4618 4619 bool allowsLargerPreferedTypeAlignment() const override { 4620 return false; 4621 } 4622 }; 4623 4624 // RTEMS Target 4625 template<typename Target> 4626 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4627 protected: 4628 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4629 MacroBuilder &Builder) const override { 4630 // RTEMS defines; list based off of gcc output 4631 4632 Builder.defineMacro("__rtems__"); 4633 Builder.defineMacro("__ELF__"); 4634 } 4635 4636 public: 4637 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4638 : OSTargetInfo<Target>(Triple, Opts) { 4639 switch (Triple.getArch()) { 4640 default: 4641 case llvm::Triple::x86: 4642 // this->MCountName = ".mcount"; 4643 break; 4644 case llvm::Triple::mips: 4645 case llvm::Triple::mipsel: 4646 case llvm::Triple::ppc: 4647 case llvm::Triple::ppc64: 4648 case llvm::Triple::ppc64le: 4649 // this->MCountName = "_mcount"; 4650 break; 4651 case llvm::Triple::arm: 4652 // this->MCountName = "__mcount"; 4653 break; 4654 } 4655 } 4656 }; 4657 4658 // x86-32 RTEMS target 4659 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4660 public: 4661 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4662 : X86_32TargetInfo(Triple, Opts) { 4663 SizeType = UnsignedLong; 4664 IntPtrType = SignedLong; 4665 PtrDiffType = SignedLong; 4666 } 4667 void getTargetDefines(const LangOptions &Opts, 4668 MacroBuilder &Builder) const override { 4669 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4670 Builder.defineMacro("__INTEL__"); 4671 Builder.defineMacro("__rtems__"); 4672 } 4673 }; 4674 4675 // x86-64 generic target 4676 class X86_64TargetInfo : public X86TargetInfo { 4677 public: 4678 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4679 : X86TargetInfo(Triple, Opts) { 4680 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4681 bool IsWinCOFF = 4682 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4683 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4684 LongDoubleWidth = 128; 4685 LongDoubleAlign = 128; 4686 LargeArrayMinWidth = 128; 4687 LargeArrayAlign = 128; 4688 SuitableAlign = 128; 4689 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4690 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4691 IntPtrType = IsX32 ? SignedInt : SignedLong; 4692 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4693 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4694 RegParmMax = 6; 4695 4696 // Pointers are 32-bit in x32. 4697 resetDataLayout(IsX32 4698 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4699 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4700 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4701 4702 // Use fpret only for long double. 4703 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4704 4705 // Use fp2ret for _Complex long double. 4706 ComplexLongDoubleUsesFP2Ret = true; 4707 4708 // Make __builtin_ms_va_list available. 4709 HasBuiltinMSVaList = true; 4710 4711 // x86-64 has atomics up to 16 bytes. 4712 MaxAtomicPromoteWidth = 128; 4713 MaxAtomicInlineWidth = 128; 4714 } 4715 BuiltinVaListKind getBuiltinVaListKind() const override { 4716 return TargetInfo::X86_64ABIBuiltinVaList; 4717 } 4718 4719 int getEHDataRegisterNumber(unsigned RegNo) const override { 4720 if (RegNo == 0) return 0; 4721 if (RegNo == 1) return 1; 4722 return -1; 4723 } 4724 4725 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4726 switch (CC) { 4727 case CC_C: 4728 case CC_Swift: 4729 case CC_X86VectorCall: 4730 case CC_IntelOclBicc: 4731 case CC_X86_64Win64: 4732 case CC_PreserveMost: 4733 case CC_PreserveAll: 4734 case CC_X86RegCall: 4735 return CCCR_OK; 4736 default: 4737 return CCCR_Warning; 4738 } 4739 } 4740 4741 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4742 return CC_C; 4743 } 4744 4745 // for x32 we need it here explicitly 4746 bool hasInt128Type() const override { return true; } 4747 unsigned getUnwindWordWidth() const override { return 64; } 4748 unsigned getRegisterWidth() const override { return 64; } 4749 4750 bool validateGlobalRegisterVariable(StringRef RegName, 4751 unsigned RegSize, 4752 bool &HasSizeMismatch) const override { 4753 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4754 // handle. 4755 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4756 // Check that the register size is 64-bit. 4757 HasSizeMismatch = RegSize != 64; 4758 return true; 4759 } 4760 4761 // Check if the register is a 32-bit register the backend can handle. 4762 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4763 HasSizeMismatch); 4764 } 4765 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4766 return llvm::makeArrayRef(BuiltinInfoX86, 4767 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4768 } 4769 }; 4770 4771 // x86-64 Windows target 4772 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4773 public: 4774 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4775 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4776 WCharType = UnsignedShort; 4777 LongWidth = LongAlign = 32; 4778 DoubleAlign = LongLongAlign = 64; 4779 IntMaxType = SignedLongLong; 4780 Int64Type = SignedLongLong; 4781 SizeType = UnsignedLongLong; 4782 PtrDiffType = SignedLongLong; 4783 IntPtrType = SignedLongLong; 4784 } 4785 4786 void getTargetDefines(const LangOptions &Opts, 4787 MacroBuilder &Builder) const override { 4788 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4789 Builder.defineMacro("_WIN64"); 4790 } 4791 4792 BuiltinVaListKind getBuiltinVaListKind() const override { 4793 return TargetInfo::CharPtrBuiltinVaList; 4794 } 4795 4796 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4797 switch (CC) { 4798 case CC_X86StdCall: 4799 case CC_X86ThisCall: 4800 case CC_X86FastCall: 4801 return CCCR_Ignore; 4802 case CC_C: 4803 case CC_X86VectorCall: 4804 case CC_IntelOclBicc: 4805 case CC_X86_64SysV: 4806 case CC_Swift: 4807 case CC_X86RegCall: 4808 return CCCR_OK; 4809 default: 4810 return CCCR_Warning; 4811 } 4812 } 4813 }; 4814 4815 // x86-64 Windows Visual Studio target 4816 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4817 public: 4818 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4819 const TargetOptions &Opts) 4820 : WindowsX86_64TargetInfo(Triple, Opts) { 4821 LongDoubleWidth = LongDoubleAlign = 64; 4822 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4823 } 4824 void getTargetDefines(const LangOptions &Opts, 4825 MacroBuilder &Builder) const override { 4826 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4827 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4828 Builder.defineMacro("_M_X64", "100"); 4829 Builder.defineMacro("_M_AMD64", "100"); 4830 } 4831 }; 4832 4833 // x86-64 MinGW target 4834 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4835 public: 4836 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4837 : WindowsX86_64TargetInfo(Triple, Opts) { 4838 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4839 // with x86 FP ops. Weird. 4840 LongDoubleWidth = LongDoubleAlign = 128; 4841 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4842 } 4843 4844 void getTargetDefines(const LangOptions &Opts, 4845 MacroBuilder &Builder) const override { 4846 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4847 DefineStd(Builder, "WIN64", Opts); 4848 Builder.defineMacro("__MINGW64__"); 4849 addMinGWDefines(Opts, Builder); 4850 4851 // GCC defines this macro when it is using __gxx_personality_seh0. 4852 if (!Opts.SjLjExceptions) 4853 Builder.defineMacro("__SEH__"); 4854 } 4855 }; 4856 4857 // x86-64 Cygwin target 4858 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4859 public: 4860 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4861 : X86_64TargetInfo(Triple, Opts) { 4862 TLSSupported = false; 4863 WCharType = UnsignedShort; 4864 } 4865 void getTargetDefines(const LangOptions &Opts, 4866 MacroBuilder &Builder) const override { 4867 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4868 Builder.defineMacro("__x86_64__"); 4869 Builder.defineMacro("__CYGWIN__"); 4870 Builder.defineMacro("__CYGWIN64__"); 4871 addCygMingDefines(Opts, Builder); 4872 DefineStd(Builder, "unix", Opts); 4873 if (Opts.CPlusPlus) 4874 Builder.defineMacro("_GNU_SOURCE"); 4875 4876 // GCC defines this macro when it is using __gxx_personality_seh0. 4877 if (!Opts.SjLjExceptions) 4878 Builder.defineMacro("__SEH__"); 4879 } 4880 }; 4881 4882 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4883 public: 4884 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4885 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4886 Int64Type = SignedLongLong; 4887 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4888 llvm::Triple T = llvm::Triple(Triple); 4889 if (T.isiOS()) 4890 UseSignedCharForObjCBool = false; 4891 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4892 } 4893 4894 bool handleTargetFeatures(std::vector<std::string> &Features, 4895 DiagnosticsEngine &Diags) override { 4896 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4897 Diags)) 4898 return false; 4899 // We now know the features we have: we can decide how to align vectors. 4900 MaxVectorAlign = 4901 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4902 return true; 4903 } 4904 }; 4905 4906 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4907 public: 4908 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4909 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4910 IntMaxType = SignedLongLong; 4911 Int64Type = SignedLongLong; 4912 } 4913 }; 4914 4915 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4916 public: 4917 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4918 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4919 IntMaxType = SignedLongLong; 4920 Int64Type = SignedLongLong; 4921 } 4922 }; 4923 4924 class ARMTargetInfo : public TargetInfo { 4925 // Possible FPU choices. 4926 enum FPUMode { 4927 VFP2FPU = (1 << 0), 4928 VFP3FPU = (1 << 1), 4929 VFP4FPU = (1 << 2), 4930 NeonFPU = (1 << 3), 4931 FPARMV8 = (1 << 4) 4932 }; 4933 4934 // Possible HWDiv features. 4935 enum HWDivMode { 4936 HWDivThumb = (1 << 0), 4937 HWDivARM = (1 << 1) 4938 }; 4939 4940 static bool FPUModeIsVFP(FPUMode Mode) { 4941 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4942 } 4943 4944 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4945 static const char * const GCCRegNames[]; 4946 4947 std::string ABI, CPU; 4948 4949 StringRef CPUProfile; 4950 StringRef CPUAttr; 4951 4952 enum { 4953 FP_Default, 4954 FP_VFP, 4955 FP_Neon 4956 } FPMath; 4957 4958 unsigned ArchISA; 4959 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4960 unsigned ArchProfile; 4961 unsigned ArchVersion; 4962 4963 unsigned FPU : 5; 4964 4965 unsigned IsAAPCS : 1; 4966 unsigned HWDiv : 2; 4967 4968 // Initialized via features. 4969 unsigned SoftFloat : 1; 4970 unsigned SoftFloatABI : 1; 4971 4972 unsigned CRC : 1; 4973 unsigned Crypto : 1; 4974 unsigned DSP : 1; 4975 unsigned Unaligned : 1; 4976 4977 enum { 4978 LDREX_B = (1 << 0), /// byte (8-bit) 4979 LDREX_H = (1 << 1), /// half (16-bit) 4980 LDREX_W = (1 << 2), /// word (32-bit) 4981 LDREX_D = (1 << 3), /// double (64-bit) 4982 }; 4983 4984 uint32_t LDREX; 4985 4986 // ACLE 6.5.1 Hardware floating point 4987 enum { 4988 HW_FP_HP = (1 << 1), /// half (16-bit) 4989 HW_FP_SP = (1 << 2), /// single (32-bit) 4990 HW_FP_DP = (1 << 3), /// double (64-bit) 4991 }; 4992 uint32_t HW_FP; 4993 4994 static const Builtin::Info BuiltinInfo[]; 4995 4996 void setABIAAPCS() { 4997 IsAAPCS = true; 4998 4999 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5000 const llvm::Triple &T = getTriple(); 5001 5002 // size_t is unsigned long on MachO-derived environments, NetBSD, 5003 // OpenBSD and Bitrig. 5004 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5005 T.getOS() == llvm::Triple::OpenBSD || 5006 T.getOS() == llvm::Triple::Bitrig) 5007 SizeType = UnsignedLong; 5008 else 5009 SizeType = UnsignedInt; 5010 5011 switch (T.getOS()) { 5012 case llvm::Triple::NetBSD: 5013 case llvm::Triple::OpenBSD: 5014 WCharType = SignedInt; 5015 break; 5016 case llvm::Triple::Win32: 5017 WCharType = UnsignedShort; 5018 break; 5019 case llvm::Triple::Linux: 5020 default: 5021 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5022 WCharType = UnsignedInt; 5023 break; 5024 } 5025 5026 UseBitFieldTypeAlignment = true; 5027 5028 ZeroLengthBitfieldBoundary = 0; 5029 5030 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5031 // so set preferred for small types to 32. 5032 if (T.isOSBinFormatMachO()) { 5033 resetDataLayout(BigEndian 5034 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5035 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5036 } else if (T.isOSWindows()) { 5037 assert(!BigEndian && "Windows on ARM does not support big endian"); 5038 resetDataLayout("e" 5039 "-m:w" 5040 "-p:32:32" 5041 "-i64:64" 5042 "-v128:64:128" 5043 "-a:0:32" 5044 "-n32" 5045 "-S64"); 5046 } else if (T.isOSNaCl()) { 5047 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5048 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5049 } else { 5050 resetDataLayout(BigEndian 5051 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5052 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5053 } 5054 5055 // FIXME: Enumerated types are variable width in straight AAPCS. 5056 } 5057 5058 void setABIAPCS(bool IsAAPCS16) { 5059 const llvm::Triple &T = getTriple(); 5060 5061 IsAAPCS = false; 5062 5063 if (IsAAPCS16) 5064 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5065 else 5066 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5067 5068 // size_t is unsigned int on FreeBSD. 5069 if (T.getOS() == llvm::Triple::FreeBSD) 5070 SizeType = UnsignedInt; 5071 else 5072 SizeType = UnsignedLong; 5073 5074 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5075 WCharType = SignedInt; 5076 5077 // Do not respect the alignment of bit-field types when laying out 5078 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5079 UseBitFieldTypeAlignment = false; 5080 5081 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5082 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5083 /// gcc. 5084 ZeroLengthBitfieldBoundary = 32; 5085 5086 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5087 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5088 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5089 } else if (T.isOSBinFormatMachO()) 5090 resetDataLayout( 5091 BigEndian 5092 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5093 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5094 else 5095 resetDataLayout( 5096 BigEndian 5097 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5098 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5099 5100 // FIXME: Override "preferred align" for double and long long. 5101 } 5102 5103 void setArchInfo() { 5104 StringRef ArchName = getTriple().getArchName(); 5105 5106 ArchISA = llvm::ARM::parseArchISA(ArchName); 5107 CPU = llvm::ARM::getDefaultCPU(ArchName); 5108 unsigned AK = llvm::ARM::parseArch(ArchName); 5109 if (AK != llvm::ARM::AK_INVALID) 5110 ArchKind = AK; 5111 setArchInfo(ArchKind); 5112 } 5113 5114 void setArchInfo(unsigned Kind) { 5115 StringRef SubArch; 5116 5117 // cache TargetParser info 5118 ArchKind = Kind; 5119 SubArch = llvm::ARM::getSubArch(ArchKind); 5120 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5121 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5122 5123 // cache CPU related strings 5124 CPUAttr = getCPUAttr(); 5125 CPUProfile = getCPUProfile(); 5126 } 5127 5128 void setAtomic() { 5129 // when triple does not specify a sub arch, 5130 // then we are not using inline atomics 5131 bool ShouldUseInlineAtomic = 5132 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5133 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5134 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5135 if (ArchProfile == llvm::ARM::PK_M) { 5136 MaxAtomicPromoteWidth = 32; 5137 if (ShouldUseInlineAtomic) 5138 MaxAtomicInlineWidth = 32; 5139 } 5140 else { 5141 MaxAtomicPromoteWidth = 64; 5142 if (ShouldUseInlineAtomic) 5143 MaxAtomicInlineWidth = 64; 5144 } 5145 } 5146 5147 bool isThumb() const { 5148 return (ArchISA == llvm::ARM::IK_THUMB); 5149 } 5150 5151 bool supportsThumb() const { 5152 return CPUAttr.count('T') || ArchVersion >= 6; 5153 } 5154 5155 bool supportsThumb2() const { 5156 return CPUAttr.equals("6T2") || 5157 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5158 } 5159 5160 StringRef getCPUAttr() const { 5161 // For most sub-arches, the build attribute CPU name is enough. 5162 // For Cortex variants, it's slightly different. 5163 switch(ArchKind) { 5164 default: 5165 return llvm::ARM::getCPUAttr(ArchKind); 5166 case llvm::ARM::AK_ARMV6M: 5167 return "6M"; 5168 case llvm::ARM::AK_ARMV7S: 5169 return "7S"; 5170 case llvm::ARM::AK_ARMV7A: 5171 return "7A"; 5172 case llvm::ARM::AK_ARMV7R: 5173 return "7R"; 5174 case llvm::ARM::AK_ARMV7M: 5175 return "7M"; 5176 case llvm::ARM::AK_ARMV7EM: 5177 return "7EM"; 5178 case llvm::ARM::AK_ARMV7VE: 5179 return "7VE"; 5180 case llvm::ARM::AK_ARMV8A: 5181 return "8A"; 5182 case llvm::ARM::AK_ARMV8_1A: 5183 return "8_1A"; 5184 case llvm::ARM::AK_ARMV8_2A: 5185 return "8_2A"; 5186 case llvm::ARM::AK_ARMV8MBaseline: 5187 return "8M_BASE"; 5188 case llvm::ARM::AK_ARMV8MMainline: 5189 return "8M_MAIN"; 5190 case llvm::ARM::AK_ARMV8R: 5191 return "8R"; 5192 } 5193 } 5194 5195 StringRef getCPUProfile() const { 5196 switch(ArchProfile) { 5197 case llvm::ARM::PK_A: 5198 return "A"; 5199 case llvm::ARM::PK_R: 5200 return "R"; 5201 case llvm::ARM::PK_M: 5202 return "M"; 5203 default: 5204 return ""; 5205 } 5206 } 5207 5208 public: 5209 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5210 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5211 HW_FP(0) { 5212 5213 switch (getTriple().getOS()) { 5214 case llvm::Triple::NetBSD: 5215 case llvm::Triple::OpenBSD: 5216 PtrDiffType = SignedLong; 5217 break; 5218 default: 5219 PtrDiffType = SignedInt; 5220 break; 5221 } 5222 5223 // Cache arch related info. 5224 setArchInfo(); 5225 5226 // {} in inline assembly are neon specifiers, not assembly variant 5227 // specifiers. 5228 NoAsmVariants = true; 5229 5230 // FIXME: This duplicates code from the driver that sets the -target-abi 5231 // option - this code is used if -target-abi isn't passed and should 5232 // be unified in some way. 5233 if (Triple.isOSBinFormatMachO()) { 5234 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5235 // the frontend matches that. 5236 if (Triple.getEnvironment() == llvm::Triple::EABI || 5237 Triple.getOS() == llvm::Triple::UnknownOS || 5238 ArchProfile == llvm::ARM::PK_M) { 5239 setABI("aapcs"); 5240 } else if (Triple.isWatchABI()) { 5241 setABI("aapcs16"); 5242 } else { 5243 setABI("apcs-gnu"); 5244 } 5245 } else if (Triple.isOSWindows()) { 5246 // FIXME: this is invalid for WindowsCE 5247 setABI("aapcs"); 5248 } else { 5249 // Select the default based on the platform. 5250 switch (Triple.getEnvironment()) { 5251 case llvm::Triple::Android: 5252 case llvm::Triple::GNUEABI: 5253 case llvm::Triple::GNUEABIHF: 5254 case llvm::Triple::MuslEABI: 5255 case llvm::Triple::MuslEABIHF: 5256 setABI("aapcs-linux"); 5257 break; 5258 case llvm::Triple::EABIHF: 5259 case llvm::Triple::EABI: 5260 setABI("aapcs"); 5261 break; 5262 case llvm::Triple::GNU: 5263 setABI("apcs-gnu"); 5264 break; 5265 default: 5266 if (Triple.getOS() == llvm::Triple::NetBSD) 5267 setABI("apcs-gnu"); 5268 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5269 setABI("aapcs-linux"); 5270 else 5271 setABI("aapcs"); 5272 break; 5273 } 5274 } 5275 5276 // ARM targets default to using the ARM C++ ABI. 5277 TheCXXABI.set(TargetCXXABI::GenericARM); 5278 5279 // ARM has atomics up to 8 bytes 5280 setAtomic(); 5281 5282 // Do force alignment of members that follow zero length bitfields. If 5283 // the alignment of the zero-length bitfield is greater than the member 5284 // that follows it, `bar', `bar' will be aligned as the type of the 5285 // zero length bitfield. 5286 UseZeroLengthBitfieldAlignment = true; 5287 5288 if (Triple.getOS() == llvm::Triple::Linux || 5289 Triple.getOS() == llvm::Triple::UnknownOS) 5290 this->MCountName = 5291 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5292 } 5293 5294 StringRef getABI() const override { return ABI; } 5295 5296 bool setABI(const std::string &Name) override { 5297 ABI = Name; 5298 5299 // The defaults (above) are for AAPCS, check if we need to change them. 5300 // 5301 // FIXME: We need support for -meabi... we could just mangle it into the 5302 // name. 5303 if (Name == "apcs-gnu" || Name == "aapcs16") { 5304 setABIAPCS(Name == "aapcs16"); 5305 return true; 5306 } 5307 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5308 setABIAAPCS(); 5309 return true; 5310 } 5311 return false; 5312 } 5313 5314 // FIXME: This should be based on Arch attributes, not CPU names. 5315 bool 5316 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5317 StringRef CPU, 5318 const std::vector<std::string> &FeaturesVec) const override { 5319 5320 std::vector<StringRef> TargetFeatures; 5321 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5322 5323 // get default FPU features 5324 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5325 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5326 5327 // get default Extension features 5328 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5329 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5330 5331 for (auto Feature : TargetFeatures) 5332 if (Feature[0] == '+') 5333 Features[Feature.drop_front(1)] = true; 5334 5335 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5336 } 5337 5338 bool handleTargetFeatures(std::vector<std::string> &Features, 5339 DiagnosticsEngine &Diags) override { 5340 FPU = 0; 5341 CRC = 0; 5342 Crypto = 0; 5343 DSP = 0; 5344 Unaligned = 1; 5345 SoftFloat = SoftFloatABI = false; 5346 HWDiv = 0; 5347 5348 // This does not diagnose illegal cases like having both 5349 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5350 uint32_t HW_FP_remove = 0; 5351 for (const auto &Feature : Features) { 5352 if (Feature == "+soft-float") { 5353 SoftFloat = true; 5354 } else if (Feature == "+soft-float-abi") { 5355 SoftFloatABI = true; 5356 } else if (Feature == "+vfp2") { 5357 FPU |= VFP2FPU; 5358 HW_FP |= HW_FP_SP | HW_FP_DP; 5359 } else if (Feature == "+vfp3") { 5360 FPU |= VFP3FPU; 5361 HW_FP |= HW_FP_SP | HW_FP_DP; 5362 } else if (Feature == "+vfp4") { 5363 FPU |= VFP4FPU; 5364 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5365 } else if (Feature == "+fp-armv8") { 5366 FPU |= FPARMV8; 5367 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5368 } else if (Feature == "+neon") { 5369 FPU |= NeonFPU; 5370 HW_FP |= HW_FP_SP | HW_FP_DP; 5371 } else if (Feature == "+hwdiv") { 5372 HWDiv |= HWDivThumb; 5373 } else if (Feature == "+hwdiv-arm") { 5374 HWDiv |= HWDivARM; 5375 } else if (Feature == "+crc") { 5376 CRC = 1; 5377 } else if (Feature == "+crypto") { 5378 Crypto = 1; 5379 } else if (Feature == "+dsp") { 5380 DSP = 1; 5381 } else if (Feature == "+fp-only-sp") { 5382 HW_FP_remove |= HW_FP_DP; 5383 } else if (Feature == "+strict-align") { 5384 Unaligned = 0; 5385 } else if (Feature == "+fp16") { 5386 HW_FP |= HW_FP_HP; 5387 } 5388 } 5389 HW_FP &= ~HW_FP_remove; 5390 5391 switch (ArchVersion) { 5392 case 6: 5393 if (ArchProfile == llvm::ARM::PK_M) 5394 LDREX = 0; 5395 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5396 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5397 else 5398 LDREX = LDREX_W; 5399 break; 5400 case 7: 5401 if (ArchProfile == llvm::ARM::PK_M) 5402 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5403 else 5404 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5405 break; 5406 case 8: 5407 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5408 } 5409 5410 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5411 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5412 return false; 5413 } 5414 5415 if (FPMath == FP_Neon) 5416 Features.push_back("+neonfp"); 5417 else if (FPMath == FP_VFP) 5418 Features.push_back("-neonfp"); 5419 5420 // Remove front-end specific options which the backend handles differently. 5421 auto Feature = 5422 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5423 if (Feature != Features.end()) 5424 Features.erase(Feature); 5425 5426 return true; 5427 } 5428 5429 bool hasFeature(StringRef Feature) const override { 5430 return llvm::StringSwitch<bool>(Feature) 5431 .Case("arm", true) 5432 .Case("aarch32", true) 5433 .Case("softfloat", SoftFloat) 5434 .Case("thumb", isThumb()) 5435 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5436 .Case("hwdiv", HWDiv & HWDivThumb) 5437 .Case("hwdiv-arm", HWDiv & HWDivARM) 5438 .Default(false); 5439 } 5440 5441 bool setCPU(const std::string &Name) override { 5442 if (Name != "generic") 5443 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5444 5445 if (ArchKind == llvm::ARM::AK_INVALID) 5446 return false; 5447 setAtomic(); 5448 CPU = Name; 5449 return true; 5450 } 5451 5452 bool setFPMath(StringRef Name) override; 5453 5454 void getTargetDefines(const LangOptions &Opts, 5455 MacroBuilder &Builder) const override { 5456 // Target identification. 5457 Builder.defineMacro("__arm"); 5458 Builder.defineMacro("__arm__"); 5459 // For bare-metal none-eabi. 5460 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5461 getTriple().getEnvironment() == llvm::Triple::EABI) 5462 Builder.defineMacro("__ELF__"); 5463 5464 // Target properties. 5465 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5466 5467 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5468 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5469 if (getTriple().isWatchABI()) 5470 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5471 5472 if (!CPUAttr.empty()) 5473 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5474 5475 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5476 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5477 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5478 5479 if (ArchVersion >= 8) { 5480 // ACLE 6.5.7 Crypto Extension 5481 if (Crypto) 5482 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5483 // ACLE 6.5.8 CRC32 Extension 5484 if (CRC) 5485 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5486 // ACLE 6.5.10 Numeric Maximum and Minimum 5487 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5488 // ACLE 6.5.9 Directed Rounding 5489 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5490 } 5491 5492 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5493 // is not defined for the M-profile. 5494 // NOTE that the default profile is assumed to be 'A' 5495 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5496 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5497 5498 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5499 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5500 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5501 // v7 and v8 architectures excluding v8-M Baseline. 5502 if (supportsThumb2()) 5503 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5504 else if (supportsThumb()) 5505 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5506 5507 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5508 // instruction set such as ARM or Thumb. 5509 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5510 5511 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5512 5513 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5514 if (!CPUProfile.empty()) 5515 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5516 5517 // ACLE 6.4.3 Unaligned access supported in hardware 5518 if (Unaligned) 5519 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5520 5521 // ACLE 6.4.4 LDREX/STREX 5522 if (LDREX) 5523 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5524 5525 // ACLE 6.4.5 CLZ 5526 if (ArchVersion == 5 || 5527 (ArchVersion == 6 && CPUProfile != "M") || 5528 ArchVersion > 6) 5529 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5530 5531 // ACLE 6.5.1 Hardware Floating Point 5532 if (HW_FP) 5533 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5534 5535 // ACLE predefines. 5536 Builder.defineMacro("__ARM_ACLE", "200"); 5537 5538 // FP16 support (we currently only support IEEE format). 5539 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5540 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5541 5542 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5543 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5544 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5545 5546 // Subtarget options. 5547 5548 // FIXME: It's more complicated than this and we don't really support 5549 // interworking. 5550 // Windows on ARM does not "support" interworking 5551 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5552 Builder.defineMacro("__THUMB_INTERWORK__"); 5553 5554 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5555 // Embedded targets on Darwin follow AAPCS, but not EABI. 5556 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5557 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5558 Builder.defineMacro("__ARM_EABI__"); 5559 Builder.defineMacro("__ARM_PCS", "1"); 5560 } 5561 5562 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5563 ABI == "aapcs16") 5564 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5565 5566 if (SoftFloat) 5567 Builder.defineMacro("__SOFTFP__"); 5568 5569 if (ArchKind == llvm::ARM::AK_XSCALE) 5570 Builder.defineMacro("__XSCALE__"); 5571 5572 if (isThumb()) { 5573 Builder.defineMacro("__THUMBEL__"); 5574 Builder.defineMacro("__thumb__"); 5575 if (supportsThumb2()) 5576 Builder.defineMacro("__thumb2__"); 5577 } 5578 5579 // ACLE 6.4.9 32-bit SIMD instructions 5580 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5581 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5582 5583 // ACLE 6.4.10 Hardware Integer Divide 5584 if (((HWDiv & HWDivThumb) && isThumb()) || 5585 ((HWDiv & HWDivARM) && !isThumb())) { 5586 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5587 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5588 } 5589 5590 // Note, this is always on in gcc, even though it doesn't make sense. 5591 Builder.defineMacro("__APCS_32__"); 5592 5593 if (FPUModeIsVFP((FPUMode) FPU)) { 5594 Builder.defineMacro("__VFP_FP__"); 5595 if (FPU & VFP2FPU) 5596 Builder.defineMacro("__ARM_VFPV2__"); 5597 if (FPU & VFP3FPU) 5598 Builder.defineMacro("__ARM_VFPV3__"); 5599 if (FPU & VFP4FPU) 5600 Builder.defineMacro("__ARM_VFPV4__"); 5601 if (FPU & FPARMV8) 5602 Builder.defineMacro("__ARM_FPV5__"); 5603 } 5604 5605 // This only gets set when Neon instructions are actually available, unlike 5606 // the VFP define, hence the soft float and arch check. This is subtly 5607 // different from gcc, we follow the intent which was that it should be set 5608 // when Neon instructions are actually available. 5609 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5610 Builder.defineMacro("__ARM_NEON", "1"); 5611 Builder.defineMacro("__ARM_NEON__"); 5612 // current AArch32 NEON implementations do not support double-precision 5613 // floating-point even when it is present in VFP. 5614 Builder.defineMacro("__ARM_NEON_FP", 5615 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5616 } 5617 5618 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5619 Opts.ShortWChar ? "2" : "4"); 5620 5621 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5622 Opts.ShortEnums ? "1" : "4"); 5623 5624 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5625 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5626 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5627 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5628 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5629 } 5630 5631 // ACLE 6.4.7 DSP instructions 5632 if (DSP) { 5633 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5634 } 5635 5636 // ACLE 6.4.8 Saturation instructions 5637 bool SAT = false; 5638 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5639 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5640 SAT = true; 5641 } 5642 5643 // ACLE 6.4.6 Q (saturation) flag 5644 if (DSP || SAT) 5645 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5646 5647 if (Opts.UnsafeFPMath) 5648 Builder.defineMacro("__ARM_FP_FAST", "1"); 5649 5650 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5651 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5652 } 5653 5654 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5655 return llvm::makeArrayRef(BuiltinInfo, 5656 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5657 } 5658 bool isCLZForZeroUndef() const override { return false; } 5659 BuiltinVaListKind getBuiltinVaListKind() const override { 5660 return IsAAPCS 5661 ? AAPCSABIBuiltinVaList 5662 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5663 : TargetInfo::VoidPtrBuiltinVaList); 5664 } 5665 ArrayRef<const char *> getGCCRegNames() const override; 5666 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5667 bool validateAsmConstraint(const char *&Name, 5668 TargetInfo::ConstraintInfo &Info) const override { 5669 switch (*Name) { 5670 default: break; 5671 case 'l': // r0-r7 5672 case 'h': // r8-r15 5673 case 't': // VFP Floating point register single precision 5674 case 'w': // VFP Floating point register double precision 5675 Info.setAllowsRegister(); 5676 return true; 5677 case 'I': 5678 case 'J': 5679 case 'K': 5680 case 'L': 5681 case 'M': 5682 // FIXME 5683 return true; 5684 case 'Q': // A memory address that is a single base register. 5685 Info.setAllowsMemory(); 5686 return true; 5687 case 'U': // a memory reference... 5688 switch (Name[1]) { 5689 case 'q': // ...ARMV4 ldrsb 5690 case 'v': // ...VFP load/store (reg+constant offset) 5691 case 'y': // ...iWMMXt load/store 5692 case 't': // address valid for load/store opaque types wider 5693 // than 128-bits 5694 case 'n': // valid address for Neon doubleword vector load/store 5695 case 'm': // valid address for Neon element and structure load/store 5696 case 's': // valid address for non-offset loads/stores of quad-word 5697 // values in four ARM registers 5698 Info.setAllowsMemory(); 5699 Name++; 5700 return true; 5701 } 5702 } 5703 return false; 5704 } 5705 std::string convertConstraint(const char *&Constraint) const override { 5706 std::string R; 5707 switch (*Constraint) { 5708 case 'U': // Two-character constraint; add "^" hint for later parsing. 5709 R = std::string("^") + std::string(Constraint, 2); 5710 Constraint++; 5711 break; 5712 case 'p': // 'p' should be translated to 'r' by default. 5713 R = std::string("r"); 5714 break; 5715 default: 5716 return std::string(1, *Constraint); 5717 } 5718 return R; 5719 } 5720 bool 5721 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5722 std::string &SuggestedModifier) const override { 5723 bool isOutput = (Constraint[0] == '='); 5724 bool isInOut = (Constraint[0] == '+'); 5725 5726 // Strip off constraint modifiers. 5727 while (Constraint[0] == '=' || 5728 Constraint[0] == '+' || 5729 Constraint[0] == '&') 5730 Constraint = Constraint.substr(1); 5731 5732 switch (Constraint[0]) { 5733 default: break; 5734 case 'r': { 5735 switch (Modifier) { 5736 default: 5737 return (isInOut || isOutput || Size <= 64); 5738 case 'q': 5739 // A register of size 32 cannot fit a vector type. 5740 return false; 5741 } 5742 } 5743 } 5744 5745 return true; 5746 } 5747 const char *getClobbers() const override { 5748 // FIXME: Is this really right? 5749 return ""; 5750 } 5751 5752 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5753 switch (CC) { 5754 case CC_AAPCS: 5755 case CC_AAPCS_VFP: 5756 case CC_Swift: 5757 return CCCR_OK; 5758 default: 5759 return CCCR_Warning; 5760 } 5761 } 5762 5763 int getEHDataRegisterNumber(unsigned RegNo) const override { 5764 if (RegNo == 0) return 0; 5765 if (RegNo == 1) return 1; 5766 return -1; 5767 } 5768 5769 bool hasSjLjLowering() const override { 5770 return true; 5771 } 5772 }; 5773 5774 bool ARMTargetInfo::setFPMath(StringRef Name) { 5775 if (Name == "neon") { 5776 FPMath = FP_Neon; 5777 return true; 5778 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5779 Name == "vfp4") { 5780 FPMath = FP_VFP; 5781 return true; 5782 } 5783 return false; 5784 } 5785 5786 const char * const ARMTargetInfo::GCCRegNames[] = { 5787 // Integer registers 5788 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5789 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5790 5791 // Float registers 5792 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5793 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5794 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5795 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5796 5797 // Double registers 5798 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5799 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5800 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5801 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5802 5803 // Quad registers 5804 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5805 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5806 }; 5807 5808 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5809 return llvm::makeArrayRef(GCCRegNames); 5810 } 5811 5812 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5813 { { "a1" }, "r0" }, 5814 { { "a2" }, "r1" }, 5815 { { "a3" }, "r2" }, 5816 { { "a4" }, "r3" }, 5817 { { "v1" }, "r4" }, 5818 { { "v2" }, "r5" }, 5819 { { "v3" }, "r6" }, 5820 { { "v4" }, "r7" }, 5821 { { "v5" }, "r8" }, 5822 { { "v6", "rfp" }, "r9" }, 5823 { { "sl" }, "r10" }, 5824 { { "fp" }, "r11" }, 5825 { { "ip" }, "r12" }, 5826 { { "r13" }, "sp" }, 5827 { { "r14" }, "lr" }, 5828 { { "r15" }, "pc" }, 5829 // The S, D and Q registers overlap, but aren't really aliases; we 5830 // don't want to substitute one of these for a different-sized one. 5831 }; 5832 5833 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5834 return llvm::makeArrayRef(GCCRegAliases); 5835 } 5836 5837 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5838 #define BUILTIN(ID, TYPE, ATTRS) \ 5839 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5840 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5841 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5842 #include "clang/Basic/BuiltinsNEON.def" 5843 5844 #define BUILTIN(ID, TYPE, ATTRS) \ 5845 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5846 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5847 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5848 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5849 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5850 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5851 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5852 #include "clang/Basic/BuiltinsARM.def" 5853 }; 5854 5855 class ARMleTargetInfo : public ARMTargetInfo { 5856 public: 5857 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5858 : ARMTargetInfo(Triple, Opts) {} 5859 void getTargetDefines(const LangOptions &Opts, 5860 MacroBuilder &Builder) const override { 5861 Builder.defineMacro("__ARMEL__"); 5862 ARMTargetInfo::getTargetDefines(Opts, Builder); 5863 } 5864 }; 5865 5866 class ARMbeTargetInfo : public ARMTargetInfo { 5867 public: 5868 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5869 : ARMTargetInfo(Triple, Opts) {} 5870 void getTargetDefines(const LangOptions &Opts, 5871 MacroBuilder &Builder) const override { 5872 Builder.defineMacro("__ARMEB__"); 5873 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5874 ARMTargetInfo::getTargetDefines(Opts, Builder); 5875 } 5876 }; 5877 5878 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5879 const llvm::Triple Triple; 5880 public: 5881 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5882 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5883 WCharType = UnsignedShort; 5884 SizeType = UnsignedInt; 5885 } 5886 void getVisualStudioDefines(const LangOptions &Opts, 5887 MacroBuilder &Builder) const { 5888 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5889 5890 // FIXME: this is invalid for WindowsCE 5891 Builder.defineMacro("_M_ARM_NT", "1"); 5892 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5893 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5894 5895 assert((Triple.getArch() == llvm::Triple::arm || 5896 Triple.getArch() == llvm::Triple::thumb) && 5897 "invalid architecture for Windows ARM target info"); 5898 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5899 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5900 5901 // TODO map the complete set of values 5902 // 31: VFPv3 40: VFPv4 5903 Builder.defineMacro("_M_ARM_FP", "31"); 5904 } 5905 BuiltinVaListKind getBuiltinVaListKind() const override { 5906 return TargetInfo::CharPtrBuiltinVaList; 5907 } 5908 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5909 switch (CC) { 5910 case CC_X86StdCall: 5911 case CC_X86ThisCall: 5912 case CC_X86FastCall: 5913 case CC_X86VectorCall: 5914 return CCCR_Ignore; 5915 case CC_C: 5916 return CCCR_OK; 5917 default: 5918 return CCCR_Warning; 5919 } 5920 } 5921 }; 5922 5923 // Windows ARM + Itanium C++ ABI Target 5924 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5925 public: 5926 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5927 const TargetOptions &Opts) 5928 : WindowsARMTargetInfo(Triple, Opts) { 5929 TheCXXABI.set(TargetCXXABI::GenericARM); 5930 } 5931 5932 void getTargetDefines(const LangOptions &Opts, 5933 MacroBuilder &Builder) const override { 5934 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5935 5936 if (Opts.MSVCCompat) 5937 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5938 } 5939 }; 5940 5941 // Windows ARM, MS (C++) ABI 5942 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5943 public: 5944 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5945 const TargetOptions &Opts) 5946 : WindowsARMTargetInfo(Triple, Opts) { 5947 TheCXXABI.set(TargetCXXABI::Microsoft); 5948 } 5949 5950 void getTargetDefines(const LangOptions &Opts, 5951 MacroBuilder &Builder) const override { 5952 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5953 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5954 } 5955 }; 5956 5957 // ARM MinGW target 5958 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5959 public: 5960 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5961 : WindowsARMTargetInfo(Triple, Opts) { 5962 TheCXXABI.set(TargetCXXABI::GenericARM); 5963 } 5964 5965 void getTargetDefines(const LangOptions &Opts, 5966 MacroBuilder &Builder) const override { 5967 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5968 DefineStd(Builder, "WIN32", Opts); 5969 DefineStd(Builder, "WINNT", Opts); 5970 Builder.defineMacro("_ARM_"); 5971 addMinGWDefines(Opts, Builder); 5972 } 5973 }; 5974 5975 // ARM Cygwin target 5976 class CygwinARMTargetInfo : public ARMleTargetInfo { 5977 public: 5978 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5979 : ARMleTargetInfo(Triple, Opts) { 5980 TLSSupported = false; 5981 WCharType = UnsignedShort; 5982 DoubleAlign = LongLongAlign = 64; 5983 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5984 } 5985 void getTargetDefines(const LangOptions &Opts, 5986 MacroBuilder &Builder) const override { 5987 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5988 Builder.defineMacro("_ARM_"); 5989 Builder.defineMacro("__CYGWIN__"); 5990 Builder.defineMacro("__CYGWIN32__"); 5991 DefineStd(Builder, "unix", Opts); 5992 if (Opts.CPlusPlus) 5993 Builder.defineMacro("_GNU_SOURCE"); 5994 } 5995 }; 5996 5997 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5998 protected: 5999 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6000 MacroBuilder &Builder) const override { 6001 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6002 } 6003 6004 public: 6005 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6006 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6007 HasAlignMac68kSupport = true; 6008 // iOS always has 64-bit atomic instructions. 6009 // FIXME: This should be based off of the target features in 6010 // ARMleTargetInfo. 6011 MaxAtomicInlineWidth = 64; 6012 6013 if (Triple.isWatchABI()) { 6014 // Darwin on iOS uses a variant of the ARM C++ ABI. 6015 TheCXXABI.set(TargetCXXABI::WatchOS); 6016 6017 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6018 // size_t is long, it's a bit weird for it to be int. 6019 PtrDiffType = SignedLong; 6020 6021 // BOOL should be a real boolean on the new ABI 6022 UseSignedCharForObjCBool = false; 6023 } else 6024 TheCXXABI.set(TargetCXXABI::iOS); 6025 } 6026 }; 6027 6028 class AArch64TargetInfo : public TargetInfo { 6029 virtual void setDataLayout() = 0; 6030 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6031 static const char *const GCCRegNames[]; 6032 6033 enum FPUModeEnum { 6034 FPUMode, 6035 NeonMode 6036 }; 6037 6038 unsigned FPU; 6039 unsigned CRC; 6040 unsigned Crypto; 6041 unsigned Unaligned; 6042 unsigned V8_1A; 6043 6044 static const Builtin::Info BuiltinInfo[]; 6045 6046 std::string ABI; 6047 6048 public: 6049 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6050 : TargetInfo(Triple), ABI("aapcs") { 6051 if (getTriple().getOS() == llvm::Triple::NetBSD || 6052 getTriple().getOS() == llvm::Triple::OpenBSD) { 6053 WCharType = SignedInt; 6054 6055 // NetBSD apparently prefers consistency across ARM targets to consistency 6056 // across 64-bit targets. 6057 Int64Type = SignedLongLong; 6058 IntMaxType = SignedLongLong; 6059 } else { 6060 WCharType = UnsignedInt; 6061 Int64Type = SignedLong; 6062 IntMaxType = SignedLong; 6063 } 6064 6065 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6066 MaxVectorAlign = 128; 6067 MaxAtomicInlineWidth = 128; 6068 MaxAtomicPromoteWidth = 128; 6069 6070 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6071 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6072 6073 // {} in inline assembly are neon specifiers, not assembly variant 6074 // specifiers. 6075 NoAsmVariants = true; 6076 6077 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6078 // contributes to the alignment of the containing aggregate in the same way 6079 // a plain (non bit-field) member of that type would, without exception for 6080 // zero-sized or anonymous bit-fields." 6081 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6082 UseZeroLengthBitfieldAlignment = true; 6083 6084 // AArch64 targets default to using the ARM C++ ABI. 6085 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6086 6087 if (Triple.getOS() == llvm::Triple::Linux) 6088 this->MCountName = "\01_mcount"; 6089 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6090 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6091 } 6092 6093 StringRef getABI() const override { return ABI; } 6094 bool setABI(const std::string &Name) override { 6095 if (Name != "aapcs" && Name != "darwinpcs") 6096 return false; 6097 6098 ABI = Name; 6099 return true; 6100 } 6101 6102 bool setCPU(const std::string &Name) override { 6103 return Name == "generic" || 6104 llvm::AArch64::parseCPUArch(Name) != 6105 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6106 } 6107 6108 void getTargetDefines(const LangOptions &Opts, 6109 MacroBuilder &Builder) const override { 6110 // Target identification. 6111 Builder.defineMacro("__aarch64__"); 6112 6113 // Target properties. 6114 Builder.defineMacro("_LP64"); 6115 Builder.defineMacro("__LP64__"); 6116 6117 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6118 Builder.defineMacro("__ARM_ACLE", "200"); 6119 Builder.defineMacro("__ARM_ARCH", "8"); 6120 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6121 6122 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6123 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6124 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6125 6126 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6127 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6128 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6129 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6130 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6131 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6132 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6133 6134 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6135 6136 // 0xe implies support for half, single and double precision operations. 6137 Builder.defineMacro("__ARM_FP", "0xE"); 6138 6139 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6140 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6141 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6142 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6143 6144 if (Opts.UnsafeFPMath) 6145 Builder.defineMacro("__ARM_FP_FAST", "1"); 6146 6147 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6148 6149 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6150 Opts.ShortEnums ? "1" : "4"); 6151 6152 if (FPU == NeonMode) { 6153 Builder.defineMacro("__ARM_NEON", "1"); 6154 // 64-bit NEON supports half, single and double precision operations. 6155 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6156 } 6157 6158 if (CRC) 6159 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6160 6161 if (Crypto) 6162 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6163 6164 if (Unaligned) 6165 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6166 6167 if (V8_1A) 6168 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6169 6170 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6171 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6172 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6173 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6174 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6175 } 6176 6177 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6178 return llvm::makeArrayRef(BuiltinInfo, 6179 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6180 } 6181 6182 bool hasFeature(StringRef Feature) const override { 6183 return Feature == "aarch64" || 6184 Feature == "arm64" || 6185 Feature == "arm" || 6186 (Feature == "neon" && FPU == NeonMode); 6187 } 6188 6189 bool handleTargetFeatures(std::vector<std::string> &Features, 6190 DiagnosticsEngine &Diags) override { 6191 FPU = FPUMode; 6192 CRC = 0; 6193 Crypto = 0; 6194 Unaligned = 1; 6195 V8_1A = 0; 6196 6197 for (const auto &Feature : Features) { 6198 if (Feature == "+neon") 6199 FPU = NeonMode; 6200 if (Feature == "+crc") 6201 CRC = 1; 6202 if (Feature == "+crypto") 6203 Crypto = 1; 6204 if (Feature == "+strict-align") 6205 Unaligned = 0; 6206 if (Feature == "+v8.1a") 6207 V8_1A = 1; 6208 } 6209 6210 setDataLayout(); 6211 6212 return true; 6213 } 6214 6215 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6216 switch (CC) { 6217 case CC_C: 6218 case CC_Swift: 6219 case CC_PreserveMost: 6220 case CC_PreserveAll: 6221 return CCCR_OK; 6222 default: 6223 return CCCR_Warning; 6224 } 6225 } 6226 6227 bool isCLZForZeroUndef() const override { return false; } 6228 6229 BuiltinVaListKind getBuiltinVaListKind() const override { 6230 return TargetInfo::AArch64ABIBuiltinVaList; 6231 } 6232 6233 ArrayRef<const char *> getGCCRegNames() const override; 6234 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6235 6236 bool validateAsmConstraint(const char *&Name, 6237 TargetInfo::ConstraintInfo &Info) const override { 6238 switch (*Name) { 6239 default: 6240 return false; 6241 case 'w': // Floating point and SIMD registers (V0-V31) 6242 Info.setAllowsRegister(); 6243 return true; 6244 case 'I': // Constant that can be used with an ADD instruction 6245 case 'J': // Constant that can be used with a SUB instruction 6246 case 'K': // Constant that can be used with a 32-bit logical instruction 6247 case 'L': // Constant that can be used with a 64-bit logical instruction 6248 case 'M': // Constant that can be used as a 32-bit MOV immediate 6249 case 'N': // Constant that can be used as a 64-bit MOV immediate 6250 case 'Y': // Floating point constant zero 6251 case 'Z': // Integer constant zero 6252 return true; 6253 case 'Q': // A memory reference with base register and no offset 6254 Info.setAllowsMemory(); 6255 return true; 6256 case 'S': // A symbolic address 6257 Info.setAllowsRegister(); 6258 return true; 6259 case 'U': 6260 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6261 // Utf: A memory address suitable for ldp/stp in TF mode. 6262 // Usa: An absolute symbolic address. 6263 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6264 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6265 case 'z': // Zero register, wzr or xzr 6266 Info.setAllowsRegister(); 6267 return true; 6268 case 'x': // Floating point and SIMD registers (V0-V15) 6269 Info.setAllowsRegister(); 6270 return true; 6271 } 6272 return false; 6273 } 6274 6275 bool 6276 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6277 std::string &SuggestedModifier) const override { 6278 // Strip off constraint modifiers. 6279 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6280 Constraint = Constraint.substr(1); 6281 6282 switch (Constraint[0]) { 6283 default: 6284 return true; 6285 case 'z': 6286 case 'r': { 6287 switch (Modifier) { 6288 case 'x': 6289 case 'w': 6290 // For now assume that the person knows what they're 6291 // doing with the modifier. 6292 return true; 6293 default: 6294 // By default an 'r' constraint will be in the 'x' 6295 // registers. 6296 if (Size == 64) 6297 return true; 6298 6299 SuggestedModifier = "w"; 6300 return false; 6301 } 6302 } 6303 } 6304 } 6305 6306 const char *getClobbers() const override { return ""; } 6307 6308 int getEHDataRegisterNumber(unsigned RegNo) const override { 6309 if (RegNo == 0) 6310 return 0; 6311 if (RegNo == 1) 6312 return 1; 6313 return -1; 6314 } 6315 }; 6316 6317 const char *const AArch64TargetInfo::GCCRegNames[] = { 6318 // 32-bit Integer registers 6319 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6320 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6321 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6322 6323 // 64-bit Integer registers 6324 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6325 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6326 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6327 6328 // 32-bit floating point regsisters 6329 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6330 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6331 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6332 6333 // 64-bit floating point regsisters 6334 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6335 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6336 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6337 6338 // Vector registers 6339 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6340 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6341 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6342 }; 6343 6344 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6345 return llvm::makeArrayRef(GCCRegNames); 6346 } 6347 6348 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6349 { { "w31" }, "wsp" }, 6350 { { "x29" }, "fp" }, 6351 { { "x30" }, "lr" }, 6352 { { "x31" }, "sp" }, 6353 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6354 // don't want to substitute one of these for a different-sized one. 6355 }; 6356 6357 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6358 return llvm::makeArrayRef(GCCRegAliases); 6359 } 6360 6361 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6362 #define BUILTIN(ID, TYPE, ATTRS) \ 6363 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6364 #include "clang/Basic/BuiltinsNEON.def" 6365 6366 #define BUILTIN(ID, TYPE, ATTRS) \ 6367 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6368 #include "clang/Basic/BuiltinsAArch64.def" 6369 }; 6370 6371 class AArch64leTargetInfo : public AArch64TargetInfo { 6372 void setDataLayout() override { 6373 if (getTriple().isOSBinFormatMachO()) 6374 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6375 else 6376 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6377 } 6378 6379 public: 6380 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6381 : AArch64TargetInfo(Triple, Opts) { 6382 } 6383 void getTargetDefines(const LangOptions &Opts, 6384 MacroBuilder &Builder) const override { 6385 Builder.defineMacro("__AARCH64EL__"); 6386 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6387 } 6388 }; 6389 6390 class AArch64beTargetInfo : public AArch64TargetInfo { 6391 void setDataLayout() override { 6392 assert(!getTriple().isOSBinFormatMachO()); 6393 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6394 } 6395 6396 public: 6397 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6398 : AArch64TargetInfo(Triple, Opts) {} 6399 void getTargetDefines(const LangOptions &Opts, 6400 MacroBuilder &Builder) const override { 6401 Builder.defineMacro("__AARCH64EB__"); 6402 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6403 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6404 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6405 } 6406 }; 6407 6408 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6409 protected: 6410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6411 MacroBuilder &Builder) const override { 6412 Builder.defineMacro("__AARCH64_SIMD__"); 6413 Builder.defineMacro("__ARM64_ARCH_8__"); 6414 Builder.defineMacro("__ARM_NEON__"); 6415 Builder.defineMacro("__LITTLE_ENDIAN__"); 6416 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6417 Builder.defineMacro("__arm64", "1"); 6418 Builder.defineMacro("__arm64__", "1"); 6419 6420 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6421 } 6422 6423 public: 6424 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6425 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6426 Int64Type = SignedLongLong; 6427 WCharType = SignedInt; 6428 UseSignedCharForObjCBool = false; 6429 6430 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6431 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6432 6433 TheCXXABI.set(TargetCXXABI::iOS64); 6434 } 6435 6436 BuiltinVaListKind getBuiltinVaListKind() const override { 6437 return TargetInfo::CharPtrBuiltinVaList; 6438 } 6439 }; 6440 6441 // Hexagon abstract base class 6442 class HexagonTargetInfo : public TargetInfo { 6443 static const Builtin::Info BuiltinInfo[]; 6444 static const char * const GCCRegNames[]; 6445 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6446 std::string CPU; 6447 bool HasHVX, HasHVXDouble; 6448 bool UseLongCalls; 6449 6450 public: 6451 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6452 : TargetInfo(Triple) { 6453 // Specify the vector alignment explicitly. For v512x1, the calculated 6454 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6455 // the required minimum of 64 bytes. 6456 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6457 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6458 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6459 SizeType = UnsignedInt; 6460 PtrDiffType = SignedInt; 6461 IntPtrType = SignedInt; 6462 6463 // {} in inline assembly are packet specifiers, not assembly variant 6464 // specifiers. 6465 NoAsmVariants = true; 6466 6467 LargeArrayMinWidth = 64; 6468 LargeArrayAlign = 64; 6469 UseBitFieldTypeAlignment = true; 6470 ZeroLengthBitfieldBoundary = 32; 6471 HasHVX = HasHVXDouble = false; 6472 UseLongCalls = false; 6473 } 6474 6475 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6476 return llvm::makeArrayRef(BuiltinInfo, 6477 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6478 } 6479 6480 bool validateAsmConstraint(const char *&Name, 6481 TargetInfo::ConstraintInfo &Info) const override { 6482 switch (*Name) { 6483 case 'v': 6484 case 'q': 6485 if (HasHVX) { 6486 Info.setAllowsRegister(); 6487 return true; 6488 } 6489 break; 6490 case 's': 6491 // Relocatable constant. 6492 return true; 6493 } 6494 return false; 6495 } 6496 6497 void getTargetDefines(const LangOptions &Opts, 6498 MacroBuilder &Builder) const override; 6499 6500 bool isCLZForZeroUndef() const override { return false; } 6501 6502 bool hasFeature(StringRef Feature) const override { 6503 return llvm::StringSwitch<bool>(Feature) 6504 .Case("hexagon", true) 6505 .Case("hvx", HasHVX) 6506 .Case("hvx-double", HasHVXDouble) 6507 .Case("long-calls", UseLongCalls) 6508 .Default(false); 6509 } 6510 6511 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6512 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6513 const override; 6514 6515 bool handleTargetFeatures(std::vector<std::string> &Features, 6516 DiagnosticsEngine &Diags) override; 6517 6518 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6519 bool Enabled) const override; 6520 6521 BuiltinVaListKind getBuiltinVaListKind() const override { 6522 return TargetInfo::CharPtrBuiltinVaList; 6523 } 6524 ArrayRef<const char *> getGCCRegNames() const override; 6525 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6526 const char *getClobbers() const override { 6527 return ""; 6528 } 6529 6530 static const char *getHexagonCPUSuffix(StringRef Name) { 6531 return llvm::StringSwitch<const char*>(Name) 6532 .Case("hexagonv4", "4") 6533 .Case("hexagonv5", "5") 6534 .Case("hexagonv55", "55") 6535 .Case("hexagonv60", "60") 6536 .Case("hexagonv62", "62") 6537 .Default(nullptr); 6538 } 6539 6540 bool setCPU(const std::string &Name) override { 6541 if (!getHexagonCPUSuffix(Name)) 6542 return false; 6543 CPU = Name; 6544 return true; 6545 } 6546 6547 int getEHDataRegisterNumber(unsigned RegNo) const override { 6548 return RegNo < 2 ? RegNo : -1; 6549 } 6550 }; 6551 6552 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6553 MacroBuilder &Builder) const { 6554 Builder.defineMacro("__qdsp6__", "1"); 6555 Builder.defineMacro("__hexagon__", "1"); 6556 6557 if (CPU == "hexagonv4") { 6558 Builder.defineMacro("__HEXAGON_V4__"); 6559 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6560 if (Opts.HexagonQdsp6Compat) { 6561 Builder.defineMacro("__QDSP6_V4__"); 6562 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6563 } 6564 } else if (CPU == "hexagonv5") { 6565 Builder.defineMacro("__HEXAGON_V5__"); 6566 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6567 if(Opts.HexagonQdsp6Compat) { 6568 Builder.defineMacro("__QDSP6_V5__"); 6569 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6570 } 6571 } else if (CPU == "hexagonv55") { 6572 Builder.defineMacro("__HEXAGON_V55__"); 6573 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6574 Builder.defineMacro("__QDSP6_V55__"); 6575 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6576 } else if (CPU == "hexagonv60") { 6577 Builder.defineMacro("__HEXAGON_V60__"); 6578 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6579 Builder.defineMacro("__QDSP6_V60__"); 6580 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6581 } else if (CPU == "hexagonv62") { 6582 Builder.defineMacro("__HEXAGON_V62__"); 6583 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6584 } 6585 6586 if (hasFeature("hvx")) { 6587 Builder.defineMacro("__HVX__"); 6588 if (hasFeature("hvx-double")) 6589 Builder.defineMacro("__HVXDBL__"); 6590 } 6591 } 6592 6593 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6594 DiagnosticsEngine &Diags, StringRef CPU, 6595 const std::vector<std::string> &FeaturesVec) const { 6596 // Default for v60: -hvx, -hvx-double. 6597 Features["hvx"] = false; 6598 Features["hvx-double"] = false; 6599 Features["long-calls"] = false; 6600 6601 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6602 } 6603 6604 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6605 DiagnosticsEngine &Diags) { 6606 for (auto &F : Features) { 6607 if (F == "+hvx") 6608 HasHVX = true; 6609 else if (F == "-hvx") 6610 HasHVX = HasHVXDouble = false; 6611 else if (F == "+hvx-double") 6612 HasHVX = HasHVXDouble = true; 6613 else if (F == "-hvx-double") 6614 HasHVXDouble = false; 6615 6616 if (F == "+long-calls") 6617 UseLongCalls = true; 6618 else if (F == "-long-calls") 6619 UseLongCalls = false; 6620 } 6621 return true; 6622 } 6623 6624 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6625 StringRef Name, bool Enabled) const { 6626 if (Enabled) { 6627 if (Name == "hvx-double") 6628 Features["hvx"] = true; 6629 } else { 6630 if (Name == "hvx") 6631 Features["hvx-double"] = false; 6632 } 6633 Features[Name] = Enabled; 6634 } 6635 6636 const char *const HexagonTargetInfo::GCCRegNames[] = { 6637 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6638 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6639 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6640 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6641 "p0", "p1", "p2", "p3", 6642 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6643 }; 6644 6645 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6646 return llvm::makeArrayRef(GCCRegNames); 6647 } 6648 6649 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6650 { { "sp" }, "r29" }, 6651 { { "fp" }, "r30" }, 6652 { { "lr" }, "r31" }, 6653 }; 6654 6655 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6656 return llvm::makeArrayRef(GCCRegAliases); 6657 } 6658 6659 6660 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6661 #define BUILTIN(ID, TYPE, ATTRS) \ 6662 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6663 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6664 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6665 #include "clang/Basic/BuiltinsHexagon.def" 6666 }; 6667 6668 class LanaiTargetInfo : public TargetInfo { 6669 // Class for Lanai (32-bit). 6670 // The CPU profiles supported by the Lanai backend 6671 enum CPUKind { 6672 CK_NONE, 6673 CK_V11, 6674 } CPU; 6675 6676 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6677 static const char *const GCCRegNames[]; 6678 6679 public: 6680 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6681 : TargetInfo(Triple) { 6682 // Description string has to be kept in sync with backend. 6683 resetDataLayout("E" // Big endian 6684 "-m:e" // ELF name manging 6685 "-p:32:32" // 32 bit pointers, 32 bit aligned 6686 "-i64:64" // 64 bit integers, 64 bit aligned 6687 "-a:0:32" // 32 bit alignment of objects of aggregate type 6688 "-n32" // 32 bit native integer width 6689 "-S64" // 64 bit natural stack alignment 6690 ); 6691 6692 // Setting RegParmMax equal to what mregparm was set to in the old 6693 // toolchain 6694 RegParmMax = 4; 6695 6696 // Set the default CPU to V11 6697 CPU = CK_V11; 6698 6699 // Temporary approach to make everything at least word-aligned and allow for 6700 // safely casting between pointers with different alignment requirements. 6701 // TODO: Remove this when there are no more cast align warnings on the 6702 // firmware. 6703 MinGlobalAlign = 32; 6704 } 6705 6706 void getTargetDefines(const LangOptions &Opts, 6707 MacroBuilder &Builder) const override { 6708 // Define __lanai__ when building for target lanai. 6709 Builder.defineMacro("__lanai__"); 6710 6711 // Set define for the CPU specified. 6712 switch (CPU) { 6713 case CK_V11: 6714 Builder.defineMacro("__LANAI_V11__"); 6715 break; 6716 case CK_NONE: 6717 llvm_unreachable("Unhandled target CPU"); 6718 } 6719 } 6720 6721 bool setCPU(const std::string &Name) override { 6722 CPU = llvm::StringSwitch<CPUKind>(Name) 6723 .Case("v11", CK_V11) 6724 .Default(CK_NONE); 6725 6726 return CPU != CK_NONE; 6727 } 6728 6729 bool hasFeature(StringRef Feature) const override { 6730 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6731 } 6732 6733 ArrayRef<const char *> getGCCRegNames() const override; 6734 6735 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6736 6737 BuiltinVaListKind getBuiltinVaListKind() const override { 6738 return TargetInfo::VoidPtrBuiltinVaList; 6739 } 6740 6741 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6742 6743 bool validateAsmConstraint(const char *&Name, 6744 TargetInfo::ConstraintInfo &info) const override { 6745 return false; 6746 } 6747 6748 const char *getClobbers() const override { return ""; } 6749 }; 6750 6751 const char *const LanaiTargetInfo::GCCRegNames[] = { 6752 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6753 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6754 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6755 6756 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6757 return llvm::makeArrayRef(GCCRegNames); 6758 } 6759 6760 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6761 {{"pc"}, "r2"}, 6762 {{"sp"}, "r4"}, 6763 {{"fp"}, "r5"}, 6764 {{"rv"}, "r8"}, 6765 {{"rr1"}, "r10"}, 6766 {{"rr2"}, "r11"}, 6767 {{"rca"}, "r15"}, 6768 }; 6769 6770 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6771 return llvm::makeArrayRef(GCCRegAliases); 6772 } 6773 6774 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6775 class SparcTargetInfo : public TargetInfo { 6776 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6777 static const char * const GCCRegNames[]; 6778 bool SoftFloat; 6779 public: 6780 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6781 : TargetInfo(Triple), SoftFloat(false) {} 6782 6783 int getEHDataRegisterNumber(unsigned RegNo) const override { 6784 if (RegNo == 0) return 24; 6785 if (RegNo == 1) return 25; 6786 return -1; 6787 } 6788 6789 bool handleTargetFeatures(std::vector<std::string> &Features, 6790 DiagnosticsEngine &Diags) override { 6791 // Check if software floating point is enabled 6792 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6793 if (Feature != Features.end()) { 6794 SoftFloat = true; 6795 } 6796 return true; 6797 } 6798 void getTargetDefines(const LangOptions &Opts, 6799 MacroBuilder &Builder) const override { 6800 DefineStd(Builder, "sparc", Opts); 6801 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6802 6803 if (SoftFloat) 6804 Builder.defineMacro("SOFT_FLOAT", "1"); 6805 } 6806 6807 bool hasFeature(StringRef Feature) const override { 6808 return llvm::StringSwitch<bool>(Feature) 6809 .Case("softfloat", SoftFloat) 6810 .Case("sparc", true) 6811 .Default(false); 6812 } 6813 6814 bool hasSjLjLowering() const override { 6815 return true; 6816 } 6817 6818 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6819 // FIXME: Implement! 6820 return None; 6821 } 6822 BuiltinVaListKind getBuiltinVaListKind() const override { 6823 return TargetInfo::VoidPtrBuiltinVaList; 6824 } 6825 ArrayRef<const char *> getGCCRegNames() const override; 6826 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6827 bool validateAsmConstraint(const char *&Name, 6828 TargetInfo::ConstraintInfo &info) const override { 6829 // FIXME: Implement! 6830 switch (*Name) { 6831 case 'I': // Signed 13-bit constant 6832 case 'J': // Zero 6833 case 'K': // 32-bit constant with the low 12 bits clear 6834 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6835 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6836 case 'N': // Same as 'K' but zext (required for SIMode) 6837 case 'O': // The constant 4096 6838 return true; 6839 } 6840 return false; 6841 } 6842 const char *getClobbers() const override { 6843 // FIXME: Implement! 6844 return ""; 6845 } 6846 6847 // No Sparc V7 for now, the backend doesn't support it anyway. 6848 enum CPUKind { 6849 CK_GENERIC, 6850 CK_V8, 6851 CK_SUPERSPARC, 6852 CK_SPARCLITE, 6853 CK_F934, 6854 CK_HYPERSPARC, 6855 CK_SPARCLITE86X, 6856 CK_SPARCLET, 6857 CK_TSC701, 6858 CK_V9, 6859 CK_ULTRASPARC, 6860 CK_ULTRASPARC3, 6861 CK_NIAGARA, 6862 CK_NIAGARA2, 6863 CK_NIAGARA3, 6864 CK_NIAGARA4, 6865 CK_MYRIAD2100, 6866 CK_MYRIAD2150, 6867 CK_MYRIAD2450, 6868 CK_LEON2, 6869 CK_LEON2_AT697E, 6870 CK_LEON2_AT697F, 6871 CK_LEON3, 6872 CK_LEON3_UT699, 6873 CK_LEON3_GR712RC, 6874 CK_LEON4, 6875 CK_LEON4_GR740 6876 } CPU = CK_GENERIC; 6877 6878 enum CPUGeneration { 6879 CG_V8, 6880 CG_V9, 6881 }; 6882 6883 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6884 switch (Kind) { 6885 case CK_GENERIC: 6886 case CK_V8: 6887 case CK_SUPERSPARC: 6888 case CK_SPARCLITE: 6889 case CK_F934: 6890 case CK_HYPERSPARC: 6891 case CK_SPARCLITE86X: 6892 case CK_SPARCLET: 6893 case CK_TSC701: 6894 case CK_MYRIAD2100: 6895 case CK_MYRIAD2150: 6896 case CK_MYRIAD2450: 6897 case CK_LEON2: 6898 case CK_LEON2_AT697E: 6899 case CK_LEON2_AT697F: 6900 case CK_LEON3: 6901 case CK_LEON3_UT699: 6902 case CK_LEON3_GR712RC: 6903 case CK_LEON4: 6904 case CK_LEON4_GR740: 6905 return CG_V8; 6906 case CK_V9: 6907 case CK_ULTRASPARC: 6908 case CK_ULTRASPARC3: 6909 case CK_NIAGARA: 6910 case CK_NIAGARA2: 6911 case CK_NIAGARA3: 6912 case CK_NIAGARA4: 6913 return CG_V9; 6914 } 6915 llvm_unreachable("Unexpected CPU kind"); 6916 } 6917 6918 CPUKind getCPUKind(StringRef Name) const { 6919 return llvm::StringSwitch<CPUKind>(Name) 6920 .Case("v8", CK_V8) 6921 .Case("supersparc", CK_SUPERSPARC) 6922 .Case("sparclite", CK_SPARCLITE) 6923 .Case("f934", CK_F934) 6924 .Case("hypersparc", CK_HYPERSPARC) 6925 .Case("sparclite86x", CK_SPARCLITE86X) 6926 .Case("sparclet", CK_SPARCLET) 6927 .Case("tsc701", CK_TSC701) 6928 .Case("v9", CK_V9) 6929 .Case("ultrasparc", CK_ULTRASPARC) 6930 .Case("ultrasparc3", CK_ULTRASPARC3) 6931 .Case("niagara", CK_NIAGARA) 6932 .Case("niagara2", CK_NIAGARA2) 6933 .Case("niagara3", CK_NIAGARA3) 6934 .Case("niagara4", CK_NIAGARA4) 6935 .Case("ma2100", CK_MYRIAD2100) 6936 .Case("ma2150", CK_MYRIAD2150) 6937 .Case("ma2450", CK_MYRIAD2450) 6938 // FIXME: the myriad2[.n] spellings are obsolete, 6939 // but a grace period is needed to allow updating dependent builds. 6940 .Case("myriad2", CK_MYRIAD2100) 6941 .Case("myriad2.1", CK_MYRIAD2100) 6942 .Case("myriad2.2", CK_MYRIAD2150) 6943 .Case("leon2", CK_LEON2) 6944 .Case("at697e", CK_LEON2_AT697E) 6945 .Case("at697f", CK_LEON2_AT697F) 6946 .Case("leon3", CK_LEON3) 6947 .Case("ut699", CK_LEON3_UT699) 6948 .Case("gr712rc", CK_LEON3_GR712RC) 6949 .Case("leon4", CK_LEON4) 6950 .Case("gr740", CK_LEON4_GR740) 6951 .Default(CK_GENERIC); 6952 } 6953 6954 bool setCPU(const std::string &Name) override { 6955 CPU = getCPUKind(Name); 6956 return CPU != CK_GENERIC; 6957 } 6958 }; 6959 6960 const char * const SparcTargetInfo::GCCRegNames[] = { 6961 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6962 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6963 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6964 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6965 }; 6966 6967 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6968 return llvm::makeArrayRef(GCCRegNames); 6969 } 6970 6971 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6972 { { "g0" }, "r0" }, 6973 { { "g1" }, "r1" }, 6974 { { "g2" }, "r2" }, 6975 { { "g3" }, "r3" }, 6976 { { "g4" }, "r4" }, 6977 { { "g5" }, "r5" }, 6978 { { "g6" }, "r6" }, 6979 { { "g7" }, "r7" }, 6980 { { "o0" }, "r8" }, 6981 { { "o1" }, "r9" }, 6982 { { "o2" }, "r10" }, 6983 { { "o3" }, "r11" }, 6984 { { "o4" }, "r12" }, 6985 { { "o5" }, "r13" }, 6986 { { "o6", "sp" }, "r14" }, 6987 { { "o7" }, "r15" }, 6988 { { "l0" }, "r16" }, 6989 { { "l1" }, "r17" }, 6990 { { "l2" }, "r18" }, 6991 { { "l3" }, "r19" }, 6992 { { "l4" }, "r20" }, 6993 { { "l5" }, "r21" }, 6994 { { "l6" }, "r22" }, 6995 { { "l7" }, "r23" }, 6996 { { "i0" }, "r24" }, 6997 { { "i1" }, "r25" }, 6998 { { "i2" }, "r26" }, 6999 { { "i3" }, "r27" }, 7000 { { "i4" }, "r28" }, 7001 { { "i5" }, "r29" }, 7002 { { "i6", "fp" }, "r30" }, 7003 { { "i7" }, "r31" }, 7004 }; 7005 7006 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7007 return llvm::makeArrayRef(GCCRegAliases); 7008 } 7009 7010 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7011 class SparcV8TargetInfo : public SparcTargetInfo { 7012 public: 7013 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7014 : SparcTargetInfo(Triple, Opts) { 7015 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7016 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7017 switch (getTriple().getOS()) { 7018 default: 7019 SizeType = UnsignedInt; 7020 IntPtrType = SignedInt; 7021 PtrDiffType = SignedInt; 7022 break; 7023 case llvm::Triple::NetBSD: 7024 case llvm::Triple::OpenBSD: 7025 SizeType = UnsignedLong; 7026 IntPtrType = SignedLong; 7027 PtrDiffType = SignedLong; 7028 break; 7029 } 7030 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7031 // on up to 64 bits. 7032 MaxAtomicPromoteWidth = 64; 7033 MaxAtomicInlineWidth = 32; 7034 } 7035 7036 void getTargetDefines(const LangOptions &Opts, 7037 MacroBuilder &Builder) const override { 7038 SparcTargetInfo::getTargetDefines(Opts, Builder); 7039 switch (getCPUGeneration(CPU)) { 7040 case CG_V8: 7041 Builder.defineMacro("__sparcv8"); 7042 if (getTriple().getOS() != llvm::Triple::Solaris) 7043 Builder.defineMacro("__sparcv8__"); 7044 break; 7045 case CG_V9: 7046 Builder.defineMacro("__sparcv9"); 7047 if (getTriple().getOS() != llvm::Triple::Solaris) { 7048 Builder.defineMacro("__sparcv9__"); 7049 Builder.defineMacro("__sparc_v9__"); 7050 } 7051 break; 7052 } 7053 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7054 std::string MyriadArchValue, Myriad2Value; 7055 Builder.defineMacro("__sparc_v8__"); 7056 Builder.defineMacro("__leon__"); 7057 switch (CPU) { 7058 case CK_MYRIAD2150: 7059 MyriadArchValue = "__ma2150"; 7060 Myriad2Value = "2"; 7061 break; 7062 case CK_MYRIAD2450: 7063 MyriadArchValue = "__ma2450"; 7064 Myriad2Value = "2"; 7065 break; 7066 default: 7067 MyriadArchValue = "__ma2100"; 7068 Myriad2Value = "1"; 7069 break; 7070 } 7071 Builder.defineMacro(MyriadArchValue, "1"); 7072 Builder.defineMacro(MyriadArchValue+"__", "1"); 7073 Builder.defineMacro("__myriad2__", Myriad2Value); 7074 Builder.defineMacro("__myriad2", Myriad2Value); 7075 } 7076 } 7077 7078 bool hasSjLjLowering() const override { 7079 return true; 7080 } 7081 }; 7082 7083 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7084 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7085 public: 7086 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7087 : SparcV8TargetInfo(Triple, Opts) { 7088 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7089 } 7090 }; 7091 7092 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7093 class SparcV9TargetInfo : public SparcTargetInfo { 7094 public: 7095 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7096 : SparcTargetInfo(Triple, Opts) { 7097 // FIXME: Support Sparc quad-precision long double? 7098 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7099 // This is an LP64 platform. 7100 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7101 7102 // OpenBSD uses long long for int64_t and intmax_t. 7103 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7104 IntMaxType = SignedLongLong; 7105 else 7106 IntMaxType = SignedLong; 7107 Int64Type = IntMaxType; 7108 7109 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7110 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7111 LongDoubleWidth = 128; 7112 LongDoubleAlign = 128; 7113 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7114 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7115 } 7116 7117 void getTargetDefines(const LangOptions &Opts, 7118 MacroBuilder &Builder) const override { 7119 SparcTargetInfo::getTargetDefines(Opts, Builder); 7120 Builder.defineMacro("__sparcv9"); 7121 Builder.defineMacro("__arch64__"); 7122 // Solaris doesn't need these variants, but the BSDs do. 7123 if (getTriple().getOS() != llvm::Triple::Solaris) { 7124 Builder.defineMacro("__sparc64__"); 7125 Builder.defineMacro("__sparc_v9__"); 7126 Builder.defineMacro("__sparcv9__"); 7127 } 7128 } 7129 7130 bool setCPU(const std::string &Name) override { 7131 if (!SparcTargetInfo::setCPU(Name)) 7132 return false; 7133 return getCPUGeneration(CPU) == CG_V9; 7134 } 7135 }; 7136 7137 class SystemZTargetInfo : public TargetInfo { 7138 static const Builtin::Info BuiltinInfo[]; 7139 static const char *const GCCRegNames[]; 7140 std::string CPU; 7141 bool HasTransactionalExecution; 7142 bool HasVector; 7143 7144 public: 7145 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7146 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7147 HasVector(false) { 7148 IntMaxType = SignedLong; 7149 Int64Type = SignedLong; 7150 TLSSupported = true; 7151 IntWidth = IntAlign = 32; 7152 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7153 PointerWidth = PointerAlign = 64; 7154 LongDoubleWidth = 128; 7155 LongDoubleAlign = 64; 7156 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7157 DefaultAlignForAttributeAligned = 64; 7158 MinGlobalAlign = 16; 7159 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7160 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7161 } 7162 void getTargetDefines(const LangOptions &Opts, 7163 MacroBuilder &Builder) const override { 7164 Builder.defineMacro("__s390__"); 7165 Builder.defineMacro("__s390x__"); 7166 Builder.defineMacro("__zarch__"); 7167 Builder.defineMacro("__LONG_DOUBLE_128__"); 7168 7169 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7170 .Cases("arch8", "z10", "8") 7171 .Cases("arch9", "z196", "9") 7172 .Cases("arch10", "zEC12", "10") 7173 .Cases("arch11", "z13", "11") 7174 .Default(""); 7175 if (!ISARev.empty()) 7176 Builder.defineMacro("__ARCH__", ISARev); 7177 7178 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7179 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7180 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7181 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7182 7183 if (HasTransactionalExecution) 7184 Builder.defineMacro("__HTM__"); 7185 if (HasVector) 7186 Builder.defineMacro("__VX__"); 7187 if (Opts.ZVector) 7188 Builder.defineMacro("__VEC__", "10301"); 7189 } 7190 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7191 return llvm::makeArrayRef(BuiltinInfo, 7192 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7193 } 7194 7195 ArrayRef<const char *> getGCCRegNames() const override; 7196 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7197 // No aliases. 7198 return None; 7199 } 7200 bool validateAsmConstraint(const char *&Name, 7201 TargetInfo::ConstraintInfo &info) const override; 7202 const char *getClobbers() const override { 7203 // FIXME: Is this really right? 7204 return ""; 7205 } 7206 BuiltinVaListKind getBuiltinVaListKind() const override { 7207 return TargetInfo::SystemZBuiltinVaList; 7208 } 7209 bool setCPU(const std::string &Name) override { 7210 CPU = Name; 7211 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7212 .Case("z10", true) 7213 .Case("arch8", true) 7214 .Case("z196", true) 7215 .Case("arch9", true) 7216 .Case("zEC12", true) 7217 .Case("arch10", true) 7218 .Case("z13", true) 7219 .Case("arch11", true) 7220 .Default(false); 7221 7222 return CPUKnown; 7223 } 7224 bool 7225 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7226 StringRef CPU, 7227 const std::vector<std::string> &FeaturesVec) const override { 7228 if (CPU == "zEC12" || CPU == "arch10") 7229 Features["transactional-execution"] = true; 7230 if (CPU == "z13" || CPU == "arch11") { 7231 Features["transactional-execution"] = true; 7232 Features["vector"] = true; 7233 } 7234 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7235 } 7236 7237 bool handleTargetFeatures(std::vector<std::string> &Features, 7238 DiagnosticsEngine &Diags) override { 7239 HasTransactionalExecution = false; 7240 for (const auto &Feature : Features) { 7241 if (Feature == "+transactional-execution") 7242 HasTransactionalExecution = true; 7243 else if (Feature == "+vector") 7244 HasVector = true; 7245 } 7246 // If we use the vector ABI, vector types are 64-bit aligned. 7247 if (HasVector) { 7248 MaxVectorAlign = 64; 7249 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7250 "-v128:64-a:8:16-n32:64"); 7251 } 7252 return true; 7253 } 7254 7255 bool hasFeature(StringRef Feature) const override { 7256 return llvm::StringSwitch<bool>(Feature) 7257 .Case("systemz", true) 7258 .Case("htm", HasTransactionalExecution) 7259 .Case("vx", HasVector) 7260 .Default(false); 7261 } 7262 7263 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7264 switch (CC) { 7265 case CC_C: 7266 case CC_Swift: 7267 return CCCR_OK; 7268 default: 7269 return CCCR_Warning; 7270 } 7271 } 7272 7273 StringRef getABI() const override { 7274 if (HasVector) 7275 return "vector"; 7276 return ""; 7277 } 7278 7279 bool useFloat128ManglingForLongDouble() const override { 7280 return true; 7281 } 7282 }; 7283 7284 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7285 #define BUILTIN(ID, TYPE, ATTRS) \ 7286 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7287 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7288 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7289 #include "clang/Basic/BuiltinsSystemZ.def" 7290 }; 7291 7292 const char *const SystemZTargetInfo::GCCRegNames[] = { 7293 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7294 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7295 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7296 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7297 }; 7298 7299 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7300 return llvm::makeArrayRef(GCCRegNames); 7301 } 7302 7303 bool SystemZTargetInfo:: 7304 validateAsmConstraint(const char *&Name, 7305 TargetInfo::ConstraintInfo &Info) const { 7306 switch (*Name) { 7307 default: 7308 return false; 7309 7310 case 'a': // Address register 7311 case 'd': // Data register (equivalent to 'r') 7312 case 'f': // Floating-point register 7313 Info.setAllowsRegister(); 7314 return true; 7315 7316 case 'I': // Unsigned 8-bit constant 7317 case 'J': // Unsigned 12-bit constant 7318 case 'K': // Signed 16-bit constant 7319 case 'L': // Signed 20-bit displacement (on all targets we support) 7320 case 'M': // 0x7fffffff 7321 return true; 7322 7323 case 'Q': // Memory with base and unsigned 12-bit displacement 7324 case 'R': // Likewise, plus an index 7325 case 'S': // Memory with base and signed 20-bit displacement 7326 case 'T': // Likewise, plus an index 7327 Info.setAllowsMemory(); 7328 return true; 7329 } 7330 } 7331 7332 class MSP430TargetInfo : public TargetInfo { 7333 static const char *const GCCRegNames[]; 7334 7335 public: 7336 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7337 : TargetInfo(Triple) { 7338 TLSSupported = false; 7339 IntWidth = 16; 7340 IntAlign = 16; 7341 LongWidth = 32; 7342 LongLongWidth = 64; 7343 LongAlign = LongLongAlign = 16; 7344 PointerWidth = 16; 7345 PointerAlign = 16; 7346 SuitableAlign = 16; 7347 SizeType = UnsignedInt; 7348 IntMaxType = SignedLongLong; 7349 IntPtrType = SignedInt; 7350 PtrDiffType = SignedInt; 7351 SigAtomicType = SignedLong; 7352 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7353 } 7354 void getTargetDefines(const LangOptions &Opts, 7355 MacroBuilder &Builder) const override { 7356 Builder.defineMacro("MSP430"); 7357 Builder.defineMacro("__MSP430__"); 7358 // FIXME: defines for different 'flavours' of MCU 7359 } 7360 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7361 // FIXME: Implement. 7362 return None; 7363 } 7364 bool hasFeature(StringRef Feature) const override { 7365 return Feature == "msp430"; 7366 } 7367 ArrayRef<const char *> getGCCRegNames() const override; 7368 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7369 // No aliases. 7370 return None; 7371 } 7372 bool validateAsmConstraint(const char *&Name, 7373 TargetInfo::ConstraintInfo &info) const override { 7374 // FIXME: implement 7375 switch (*Name) { 7376 case 'K': // the constant 1 7377 case 'L': // constant -1^20 .. 1^19 7378 case 'M': // constant 1-4: 7379 return true; 7380 } 7381 // No target constraints for now. 7382 return false; 7383 } 7384 const char *getClobbers() const override { 7385 // FIXME: Is this really right? 7386 return ""; 7387 } 7388 BuiltinVaListKind getBuiltinVaListKind() const override { 7389 // FIXME: implement 7390 return TargetInfo::CharPtrBuiltinVaList; 7391 } 7392 }; 7393 7394 const char *const MSP430TargetInfo::GCCRegNames[] = { 7395 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7396 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7397 7398 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7399 return llvm::makeArrayRef(GCCRegNames); 7400 } 7401 7402 // LLVM and Clang cannot be used directly to output native binaries for 7403 // target, but is used to compile C code to llvm bitcode with correct 7404 // type and alignment information. 7405 // 7406 // TCE uses the llvm bitcode as input and uses it for generating customized 7407 // target processor and program binary. TCE co-design environment is 7408 // publicly available in http://tce.cs.tut.fi 7409 7410 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7411 3, // opencl_global 7412 4, // opencl_local 7413 5, // opencl_constant 7414 // FIXME: generic has to be added to the target 7415 0, // opencl_generic 7416 0, // cuda_device 7417 0, // cuda_constant 7418 0 // cuda_shared 7419 }; 7420 7421 class TCETargetInfo : public TargetInfo { 7422 public: 7423 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7424 : TargetInfo(Triple) { 7425 TLSSupported = false; 7426 IntWidth = 32; 7427 LongWidth = LongLongWidth = 32; 7428 PointerWidth = 32; 7429 IntAlign = 32; 7430 LongAlign = LongLongAlign = 32; 7431 PointerAlign = 32; 7432 SuitableAlign = 32; 7433 SizeType = UnsignedInt; 7434 IntMaxType = SignedLong; 7435 IntPtrType = SignedInt; 7436 PtrDiffType = SignedInt; 7437 FloatWidth = 32; 7438 FloatAlign = 32; 7439 DoubleWidth = 32; 7440 DoubleAlign = 32; 7441 LongDoubleWidth = 32; 7442 LongDoubleAlign = 32; 7443 FloatFormat = &llvm::APFloat::IEEEsingle(); 7444 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7445 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7446 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7447 "i16:16:32-i32:32:32-i64:32:32-" 7448 "f32:32:32-f64:32:32-v64:32:32-" 7449 "v128:32:32-v256:32:32-v512:32:32-" 7450 "v1024:32:32-a0:0:32-n32"); 7451 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7452 UseAddrSpaceMapMangling = true; 7453 } 7454 7455 void getTargetDefines(const LangOptions &Opts, 7456 MacroBuilder &Builder) const override { 7457 DefineStd(Builder, "tce", Opts); 7458 Builder.defineMacro("__TCE__"); 7459 Builder.defineMacro("__TCE_V1__"); 7460 } 7461 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7462 7463 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7464 const char *getClobbers() const override { return ""; } 7465 BuiltinVaListKind getBuiltinVaListKind() const override { 7466 return TargetInfo::VoidPtrBuiltinVaList; 7467 } 7468 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7469 bool validateAsmConstraint(const char *&Name, 7470 TargetInfo::ConstraintInfo &info) const override { 7471 return true; 7472 } 7473 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7474 return None; 7475 } 7476 }; 7477 7478 class TCELETargetInfo : public TCETargetInfo { 7479 public: 7480 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7481 : TCETargetInfo(Triple, Opts) { 7482 BigEndian = false; 7483 7484 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7485 "i16:16:32-i32:32:32-i64:32:32-" 7486 "f32:32:32-f64:32:32-v64:32:32-" 7487 "v128:32:32-v256:32:32-v512:32:32-" 7488 "v1024:32:32-a0:0:32-n32"); 7489 7490 } 7491 7492 virtual void getTargetDefines(const LangOptions &Opts, 7493 MacroBuilder &Builder) const { 7494 DefineStd(Builder, "tcele", Opts); 7495 Builder.defineMacro("__TCE__"); 7496 Builder.defineMacro("__TCE_V1__"); 7497 Builder.defineMacro("__TCELE__"); 7498 Builder.defineMacro("__TCELE_V1__"); 7499 } 7500 7501 }; 7502 7503 class BPFTargetInfo : public TargetInfo { 7504 public: 7505 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7506 : TargetInfo(Triple) { 7507 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7508 SizeType = UnsignedLong; 7509 PtrDiffType = SignedLong; 7510 IntPtrType = SignedLong; 7511 IntMaxType = SignedLong; 7512 Int64Type = SignedLong; 7513 RegParmMax = 5; 7514 if (Triple.getArch() == llvm::Triple::bpfeb) { 7515 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7516 } else { 7517 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7518 } 7519 MaxAtomicPromoteWidth = 64; 7520 MaxAtomicInlineWidth = 64; 7521 TLSSupported = false; 7522 } 7523 void getTargetDefines(const LangOptions &Opts, 7524 MacroBuilder &Builder) const override { 7525 DefineStd(Builder, "bpf", Opts); 7526 Builder.defineMacro("__BPF__"); 7527 } 7528 bool hasFeature(StringRef Feature) const override { 7529 return Feature == "bpf"; 7530 } 7531 7532 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7533 const char *getClobbers() const override { 7534 return ""; 7535 } 7536 BuiltinVaListKind getBuiltinVaListKind() const override { 7537 return TargetInfo::VoidPtrBuiltinVaList; 7538 } 7539 ArrayRef<const char *> getGCCRegNames() const override { 7540 return None; 7541 } 7542 bool validateAsmConstraint(const char *&Name, 7543 TargetInfo::ConstraintInfo &info) const override { 7544 return true; 7545 } 7546 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7547 return None; 7548 } 7549 }; 7550 7551 class MipsTargetInfo : public TargetInfo { 7552 void setDataLayout() { 7553 StringRef Layout; 7554 7555 if (ABI == "o32") 7556 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7557 else if (ABI == "n32") 7558 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7559 else if (ABI == "n64") 7560 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7561 else 7562 llvm_unreachable("Invalid ABI"); 7563 7564 if (BigEndian) 7565 resetDataLayout(("E-" + Layout).str()); 7566 else 7567 resetDataLayout(("e-" + Layout).str()); 7568 } 7569 7570 7571 static const Builtin::Info BuiltinInfo[]; 7572 std::string CPU; 7573 bool IsMips16; 7574 bool IsMicromips; 7575 bool IsNan2008; 7576 bool IsSingleFloat; 7577 bool IsNoABICalls; 7578 bool CanUseBSDABICalls; 7579 enum MipsFloatABI { 7580 HardFloat, SoftFloat 7581 } FloatABI; 7582 enum DspRevEnum { 7583 NoDSP, DSP1, DSP2 7584 } DspRev; 7585 bool HasMSA; 7586 7587 protected: 7588 bool HasFP64; 7589 std::string ABI; 7590 7591 public: 7592 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7593 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7594 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7595 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7596 HasMSA(false), HasFP64(false) { 7597 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7598 7599 setABI((getTriple().getArch() == llvm::Triple::mips || 7600 getTriple().getArch() == llvm::Triple::mipsel) 7601 ? "o32" 7602 : "n64"); 7603 7604 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7605 7606 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7607 Triple.getOS() == llvm::Triple::OpenBSD; 7608 } 7609 7610 bool isNaN2008Default() const { 7611 return CPU == "mips32r6" || CPU == "mips64r6"; 7612 } 7613 7614 bool isFP64Default() const { 7615 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7616 } 7617 7618 bool isNan2008() const override { 7619 return IsNan2008; 7620 } 7621 7622 bool processorSupportsGPR64() const { 7623 return llvm::StringSwitch<bool>(CPU) 7624 .Case("mips3", true) 7625 .Case("mips4", true) 7626 .Case("mips5", true) 7627 .Case("mips64", true) 7628 .Case("mips64r2", true) 7629 .Case("mips64r3", true) 7630 .Case("mips64r5", true) 7631 .Case("mips64r6", true) 7632 .Case("octeon", true) 7633 .Default(false); 7634 return false; 7635 } 7636 7637 StringRef getABI() const override { return ABI; } 7638 bool setABI(const std::string &Name) override { 7639 if (Name == "o32") { 7640 setO32ABITypes(); 7641 ABI = Name; 7642 return true; 7643 } 7644 7645 if (Name == "n32") { 7646 setN32ABITypes(); 7647 ABI = Name; 7648 return true; 7649 } 7650 if (Name == "n64") { 7651 setN64ABITypes(); 7652 ABI = Name; 7653 return true; 7654 } 7655 return false; 7656 } 7657 7658 void setO32ABITypes() { 7659 Int64Type = SignedLongLong; 7660 IntMaxType = Int64Type; 7661 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7662 LongDoubleWidth = LongDoubleAlign = 64; 7663 LongWidth = LongAlign = 32; 7664 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7665 PointerWidth = PointerAlign = 32; 7666 PtrDiffType = SignedInt; 7667 SizeType = UnsignedInt; 7668 SuitableAlign = 64; 7669 } 7670 7671 void setN32N64ABITypes() { 7672 LongDoubleWidth = LongDoubleAlign = 128; 7673 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7674 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7675 LongDoubleWidth = LongDoubleAlign = 64; 7676 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7677 } 7678 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7679 SuitableAlign = 128; 7680 } 7681 7682 void setN64ABITypes() { 7683 setN32N64ABITypes(); 7684 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7685 Int64Type = SignedLongLong; 7686 } else { 7687 Int64Type = SignedLong; 7688 } 7689 IntMaxType = Int64Type; 7690 LongWidth = LongAlign = 64; 7691 PointerWidth = PointerAlign = 64; 7692 PtrDiffType = SignedLong; 7693 SizeType = UnsignedLong; 7694 } 7695 7696 void setN32ABITypes() { 7697 setN32N64ABITypes(); 7698 Int64Type = SignedLongLong; 7699 IntMaxType = Int64Type; 7700 LongWidth = LongAlign = 32; 7701 PointerWidth = PointerAlign = 32; 7702 PtrDiffType = SignedInt; 7703 SizeType = UnsignedInt; 7704 } 7705 7706 bool setCPU(const std::string &Name) override { 7707 CPU = Name; 7708 return llvm::StringSwitch<bool>(Name) 7709 .Case("mips1", true) 7710 .Case("mips2", true) 7711 .Case("mips3", true) 7712 .Case("mips4", true) 7713 .Case("mips5", true) 7714 .Case("mips32", true) 7715 .Case("mips32r2", true) 7716 .Case("mips32r3", true) 7717 .Case("mips32r5", true) 7718 .Case("mips32r6", true) 7719 .Case("mips64", true) 7720 .Case("mips64r2", true) 7721 .Case("mips64r3", true) 7722 .Case("mips64r5", true) 7723 .Case("mips64r6", true) 7724 .Case("octeon", true) 7725 .Case("p5600", true) 7726 .Default(false); 7727 } 7728 const std::string& getCPU() const { return CPU; } 7729 bool 7730 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7731 StringRef CPU, 7732 const std::vector<std::string> &FeaturesVec) const override { 7733 if (CPU.empty()) 7734 CPU = getCPU(); 7735 if (CPU == "octeon") 7736 Features["mips64r2"] = Features["cnmips"] = true; 7737 else 7738 Features[CPU] = true; 7739 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7740 } 7741 7742 void getTargetDefines(const LangOptions &Opts, 7743 MacroBuilder &Builder) const override { 7744 if (BigEndian) { 7745 DefineStd(Builder, "MIPSEB", Opts); 7746 Builder.defineMacro("_MIPSEB"); 7747 } else { 7748 DefineStd(Builder, "MIPSEL", Opts); 7749 Builder.defineMacro("_MIPSEL"); 7750 } 7751 7752 Builder.defineMacro("__mips__"); 7753 Builder.defineMacro("_mips"); 7754 if (Opts.GNUMode) 7755 Builder.defineMacro("mips"); 7756 7757 if (ABI == "o32") { 7758 Builder.defineMacro("__mips", "32"); 7759 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7760 } else { 7761 Builder.defineMacro("__mips", "64"); 7762 Builder.defineMacro("__mips64"); 7763 Builder.defineMacro("__mips64__"); 7764 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7765 } 7766 7767 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7768 .Cases("mips32", "mips64", "1") 7769 .Cases("mips32r2", "mips64r2", "2") 7770 .Cases("mips32r3", "mips64r3", "3") 7771 .Cases("mips32r5", "mips64r5", "5") 7772 .Cases("mips32r6", "mips64r6", "6") 7773 .Default(""); 7774 if (!ISARev.empty()) 7775 Builder.defineMacro("__mips_isa_rev", ISARev); 7776 7777 if (ABI == "o32") { 7778 Builder.defineMacro("__mips_o32"); 7779 Builder.defineMacro("_ABIO32", "1"); 7780 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7781 } else if (ABI == "n32") { 7782 Builder.defineMacro("__mips_n32"); 7783 Builder.defineMacro("_ABIN32", "2"); 7784 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7785 } else if (ABI == "n64") { 7786 Builder.defineMacro("__mips_n64"); 7787 Builder.defineMacro("_ABI64", "3"); 7788 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7789 } else 7790 llvm_unreachable("Invalid ABI."); 7791 7792 if (!IsNoABICalls) { 7793 Builder.defineMacro("__mips_abicalls"); 7794 if (CanUseBSDABICalls) 7795 Builder.defineMacro("__ABICALLS__"); 7796 } 7797 7798 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7799 7800 switch (FloatABI) { 7801 case HardFloat: 7802 Builder.defineMacro("__mips_hard_float", Twine(1)); 7803 break; 7804 case SoftFloat: 7805 Builder.defineMacro("__mips_soft_float", Twine(1)); 7806 break; 7807 } 7808 7809 if (IsSingleFloat) 7810 Builder.defineMacro("__mips_single_float", Twine(1)); 7811 7812 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7813 Builder.defineMacro("_MIPS_FPSET", 7814 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7815 7816 if (IsMips16) 7817 Builder.defineMacro("__mips16", Twine(1)); 7818 7819 if (IsMicromips) 7820 Builder.defineMacro("__mips_micromips", Twine(1)); 7821 7822 if (IsNan2008) 7823 Builder.defineMacro("__mips_nan2008", Twine(1)); 7824 7825 switch (DspRev) { 7826 default: 7827 break; 7828 case DSP1: 7829 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7830 Builder.defineMacro("__mips_dsp", Twine(1)); 7831 break; 7832 case DSP2: 7833 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7834 Builder.defineMacro("__mips_dspr2", Twine(1)); 7835 Builder.defineMacro("__mips_dsp", Twine(1)); 7836 break; 7837 } 7838 7839 if (HasMSA) 7840 Builder.defineMacro("__mips_msa", Twine(1)); 7841 7842 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7843 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7844 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7845 7846 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7847 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7848 7849 // These shouldn't be defined for MIPS-I but there's no need to check 7850 // for that since MIPS-I isn't supported. 7851 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7852 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7854 7855 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7856 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7857 // the instructions exist but using them violates the ABI since they 7858 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7859 if (ABI == "n32" || ABI == "n64") 7860 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7861 } 7862 7863 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7864 return llvm::makeArrayRef(BuiltinInfo, 7865 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7866 } 7867 bool hasFeature(StringRef Feature) const override { 7868 return llvm::StringSwitch<bool>(Feature) 7869 .Case("mips", true) 7870 .Case("fp64", HasFP64) 7871 .Default(false); 7872 } 7873 BuiltinVaListKind getBuiltinVaListKind() const override { 7874 return TargetInfo::VoidPtrBuiltinVaList; 7875 } 7876 ArrayRef<const char *> getGCCRegNames() const override { 7877 static const char *const GCCRegNames[] = { 7878 // CPU register names 7879 // Must match second column of GCCRegAliases 7880 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7881 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7882 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7883 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7884 // Floating point register names 7885 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7886 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7887 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7888 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7889 // Hi/lo and condition register names 7890 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7891 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7892 "$ac3hi","$ac3lo", 7893 // MSA register names 7894 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7895 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7896 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7897 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7898 // MSA control register names 7899 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7900 "$msarequest", "$msamap", "$msaunmap" 7901 }; 7902 return llvm::makeArrayRef(GCCRegNames); 7903 } 7904 bool validateAsmConstraint(const char *&Name, 7905 TargetInfo::ConstraintInfo &Info) const override { 7906 switch (*Name) { 7907 default: 7908 return false; 7909 case 'r': // CPU registers. 7910 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7911 case 'y': // Equivalent to "r", backward compatibility only. 7912 case 'f': // floating-point registers. 7913 case 'c': // $25 for indirect jumps 7914 case 'l': // lo register 7915 case 'x': // hilo register pair 7916 Info.setAllowsRegister(); 7917 return true; 7918 case 'I': // Signed 16-bit constant 7919 case 'J': // Integer 0 7920 case 'K': // Unsigned 16-bit constant 7921 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7922 case 'M': // Constants not loadable via lui, addiu, or ori 7923 case 'N': // Constant -1 to -65535 7924 case 'O': // A signed 15-bit constant 7925 case 'P': // A constant between 1 go 65535 7926 return true; 7927 case 'R': // An address that can be used in a non-macro load or store 7928 Info.setAllowsMemory(); 7929 return true; 7930 case 'Z': 7931 if (Name[1] == 'C') { // An address usable by ll, and sc. 7932 Info.setAllowsMemory(); 7933 Name++; // Skip over 'Z'. 7934 return true; 7935 } 7936 return false; 7937 } 7938 } 7939 7940 std::string convertConstraint(const char *&Constraint) const override { 7941 std::string R; 7942 switch (*Constraint) { 7943 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7944 if (Constraint[1] == 'C') { 7945 R = std::string("^") + std::string(Constraint, 2); 7946 Constraint++; 7947 return R; 7948 } 7949 break; 7950 } 7951 return TargetInfo::convertConstraint(Constraint); 7952 } 7953 7954 const char *getClobbers() const override { 7955 // In GCC, $1 is not widely used in generated code (it's used only in a few 7956 // specific situations), so there is no real need for users to add it to 7957 // the clobbers list if they want to use it in their inline assembly code. 7958 // 7959 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7960 // code generation, so using it in inline assembly without adding it to the 7961 // clobbers list can cause conflicts between the inline assembly code and 7962 // the surrounding generated code. 7963 // 7964 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7965 // operands, which will conflict with the ".set at" assembler option (which 7966 // we use only for inline assembly, in order to maintain compatibility with 7967 // GCC) and will also conflict with the user's usage of $1. 7968 // 7969 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7970 // register for generated code is to automatically clobber $1 for all inline 7971 // assembly code. 7972 // 7973 // FIXME: We should automatically clobber $1 only for inline assembly code 7974 // which actually uses it. This would allow LLVM to use $1 for inline 7975 // assembly operands if the user's assembly code doesn't use it. 7976 return "~{$1}"; 7977 } 7978 7979 bool handleTargetFeatures(std::vector<std::string> &Features, 7980 DiagnosticsEngine &Diags) override { 7981 IsMips16 = false; 7982 IsMicromips = false; 7983 IsNan2008 = isNaN2008Default(); 7984 IsSingleFloat = false; 7985 FloatABI = HardFloat; 7986 DspRev = NoDSP; 7987 HasFP64 = isFP64Default(); 7988 7989 for (const auto &Feature : Features) { 7990 if (Feature == "+single-float") 7991 IsSingleFloat = true; 7992 else if (Feature == "+soft-float") 7993 FloatABI = SoftFloat; 7994 else if (Feature == "+mips16") 7995 IsMips16 = true; 7996 else if (Feature == "+micromips") 7997 IsMicromips = true; 7998 else if (Feature == "+dsp") 7999 DspRev = std::max(DspRev, DSP1); 8000 else if (Feature == "+dspr2") 8001 DspRev = std::max(DspRev, DSP2); 8002 else if (Feature == "+msa") 8003 HasMSA = true; 8004 else if (Feature == "+fp64") 8005 HasFP64 = true; 8006 else if (Feature == "-fp64") 8007 HasFP64 = false; 8008 else if (Feature == "+nan2008") 8009 IsNan2008 = true; 8010 else if (Feature == "-nan2008") 8011 IsNan2008 = false; 8012 else if (Feature == "+noabicalls") 8013 IsNoABICalls = true; 8014 } 8015 8016 setDataLayout(); 8017 8018 return true; 8019 } 8020 8021 int getEHDataRegisterNumber(unsigned RegNo) const override { 8022 if (RegNo == 0) return 4; 8023 if (RegNo == 1) return 5; 8024 return -1; 8025 } 8026 8027 bool isCLZForZeroUndef() const override { return false; } 8028 8029 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8030 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8031 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8032 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8033 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8034 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8035 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8036 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8037 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8038 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8039 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8040 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8041 {{"ra"}, "$31"}}; 8042 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8043 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8044 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8045 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8046 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8047 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8048 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8049 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8050 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8051 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8052 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8053 {{"ra"}, "$31"}}; 8054 if (ABI == "o32") 8055 return llvm::makeArrayRef(O32RegAliases); 8056 return llvm::makeArrayRef(NewABIRegAliases); 8057 } 8058 8059 bool hasInt128Type() const override { 8060 return ABI == "n32" || ABI == "n64"; 8061 } 8062 8063 bool validateTarget(DiagnosticsEngine &Diags) const override { 8064 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8065 // this yet. It's better to fail here than on the backend assertion. 8066 if (processorSupportsGPR64() && ABI == "o32") { 8067 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8068 return false; 8069 } 8070 8071 // 64-bit ABI's require 64-bit CPU's. 8072 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8073 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8074 return false; 8075 } 8076 8077 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8078 // can't handle this yet. It's better to fail here than on the 8079 // backend assertion. 8080 if ((getTriple().getArch() == llvm::Triple::mips64 || 8081 getTriple().getArch() == llvm::Triple::mips64el) && 8082 ABI == "o32") { 8083 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8084 << ABI << getTriple().str(); 8085 return false; 8086 } 8087 8088 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8089 // can't handle this yet. It's better to fail here than on the 8090 // backend assertion. 8091 if ((getTriple().getArch() == llvm::Triple::mips || 8092 getTriple().getArch() == llvm::Triple::mipsel) && 8093 (ABI == "n32" || ABI == "n64")) { 8094 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8095 << ABI << getTriple().str(); 8096 return false; 8097 } 8098 8099 return true; 8100 } 8101 }; 8102 8103 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8104 #define BUILTIN(ID, TYPE, ATTRS) \ 8105 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8106 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8107 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8108 #include "clang/Basic/BuiltinsMips.def" 8109 }; 8110 8111 class PNaClTargetInfo : public TargetInfo { 8112 public: 8113 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8114 : TargetInfo(Triple) { 8115 this->LongAlign = 32; 8116 this->LongWidth = 32; 8117 this->PointerAlign = 32; 8118 this->PointerWidth = 32; 8119 this->IntMaxType = TargetInfo::SignedLongLong; 8120 this->Int64Type = TargetInfo::SignedLongLong; 8121 this->DoubleAlign = 64; 8122 this->LongDoubleWidth = 64; 8123 this->LongDoubleAlign = 64; 8124 this->SizeType = TargetInfo::UnsignedInt; 8125 this->PtrDiffType = TargetInfo::SignedInt; 8126 this->IntPtrType = TargetInfo::SignedInt; 8127 this->RegParmMax = 0; // Disallow regparm 8128 } 8129 8130 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8131 Builder.defineMacro("__le32__"); 8132 Builder.defineMacro("__pnacl__"); 8133 } 8134 void getTargetDefines(const LangOptions &Opts, 8135 MacroBuilder &Builder) const override { 8136 getArchDefines(Opts, Builder); 8137 } 8138 bool hasFeature(StringRef Feature) const override { 8139 return Feature == "pnacl"; 8140 } 8141 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8142 BuiltinVaListKind getBuiltinVaListKind() const override { 8143 return TargetInfo::PNaClABIBuiltinVaList; 8144 } 8145 ArrayRef<const char *> getGCCRegNames() const override; 8146 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8147 bool validateAsmConstraint(const char *&Name, 8148 TargetInfo::ConstraintInfo &Info) const override { 8149 return false; 8150 } 8151 8152 const char *getClobbers() const override { 8153 return ""; 8154 } 8155 }; 8156 8157 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8158 return None; 8159 } 8160 8161 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8162 return None; 8163 } 8164 8165 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8166 class NaClMips32TargetInfo : public MipsTargetInfo { 8167 public: 8168 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8169 : MipsTargetInfo(Triple, Opts) {} 8170 8171 BuiltinVaListKind getBuiltinVaListKind() const override { 8172 return TargetInfo::PNaClABIBuiltinVaList; 8173 } 8174 }; 8175 8176 class Le64TargetInfo : public TargetInfo { 8177 static const Builtin::Info BuiltinInfo[]; 8178 8179 public: 8180 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8181 : TargetInfo(Triple) { 8182 NoAsmVariants = true; 8183 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8184 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8185 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8186 } 8187 8188 void getTargetDefines(const LangOptions &Opts, 8189 MacroBuilder &Builder) const override { 8190 DefineStd(Builder, "unix", Opts); 8191 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8192 Builder.defineMacro("__ELF__"); 8193 } 8194 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8195 return llvm::makeArrayRef(BuiltinInfo, 8196 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8197 } 8198 BuiltinVaListKind getBuiltinVaListKind() const override { 8199 return TargetInfo::PNaClABIBuiltinVaList; 8200 } 8201 const char *getClobbers() const override { return ""; } 8202 ArrayRef<const char *> getGCCRegNames() const override { 8203 return None; 8204 } 8205 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8206 return None; 8207 } 8208 bool validateAsmConstraint(const char *&Name, 8209 TargetInfo::ConstraintInfo &Info) const override { 8210 return false; 8211 } 8212 8213 bool hasProtectedVisibility() const override { return false; } 8214 }; 8215 8216 class WebAssemblyTargetInfo : public TargetInfo { 8217 static const Builtin::Info BuiltinInfo[]; 8218 8219 enum SIMDEnum { 8220 NoSIMD, 8221 SIMD128, 8222 } SIMDLevel; 8223 8224 public: 8225 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8226 : TargetInfo(T), SIMDLevel(NoSIMD) { 8227 NoAsmVariants = true; 8228 SuitableAlign = 128; 8229 LargeArrayMinWidth = 128; 8230 LargeArrayAlign = 128; 8231 SimdDefaultAlign = 128; 8232 SigAtomicType = SignedLong; 8233 LongDoubleWidth = LongDoubleAlign = 128; 8234 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8235 SizeType = UnsignedInt; 8236 PtrDiffType = SignedInt; 8237 IntPtrType = SignedInt; 8238 } 8239 8240 protected: 8241 void getTargetDefines(const LangOptions &Opts, 8242 MacroBuilder &Builder) const override { 8243 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8244 if (SIMDLevel >= SIMD128) 8245 Builder.defineMacro("__wasm_simd128__"); 8246 } 8247 8248 private: 8249 bool 8250 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8251 StringRef CPU, 8252 const std::vector<std::string> &FeaturesVec) const override { 8253 if (CPU == "bleeding-edge") 8254 Features["simd128"] = true; 8255 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8256 } 8257 bool hasFeature(StringRef Feature) const final { 8258 return llvm::StringSwitch<bool>(Feature) 8259 .Case("simd128", SIMDLevel >= SIMD128) 8260 .Default(false); 8261 } 8262 bool handleTargetFeatures(std::vector<std::string> &Features, 8263 DiagnosticsEngine &Diags) final { 8264 for (const auto &Feature : Features) { 8265 if (Feature == "+simd128") { 8266 SIMDLevel = std::max(SIMDLevel, SIMD128); 8267 continue; 8268 } 8269 if (Feature == "-simd128") { 8270 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8271 continue; 8272 } 8273 8274 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8275 << "-target-feature"; 8276 return false; 8277 } 8278 return true; 8279 } 8280 bool setCPU(const std::string &Name) final { 8281 return llvm::StringSwitch<bool>(Name) 8282 .Case("mvp", true) 8283 .Case("bleeding-edge", true) 8284 .Case("generic", true) 8285 .Default(false); 8286 } 8287 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8288 return llvm::makeArrayRef(BuiltinInfo, 8289 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8290 } 8291 BuiltinVaListKind getBuiltinVaListKind() const final { 8292 return VoidPtrBuiltinVaList; 8293 } 8294 ArrayRef<const char *> getGCCRegNames() const final { 8295 return None; 8296 } 8297 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8298 return None; 8299 } 8300 bool 8301 validateAsmConstraint(const char *&Name, 8302 TargetInfo::ConstraintInfo &Info) const final { 8303 return false; 8304 } 8305 const char *getClobbers() const final { return ""; } 8306 bool isCLZForZeroUndef() const final { return false; } 8307 bool hasInt128Type() const final { return true; } 8308 IntType getIntTypeByWidth(unsigned BitWidth, 8309 bool IsSigned) const final { 8310 // WebAssembly prefers long long for explicitly 64-bit integers. 8311 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8312 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8313 } 8314 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8315 bool IsSigned) const final { 8316 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8317 return BitWidth == 64 8318 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8319 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8320 } 8321 }; 8322 8323 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8324 #define BUILTIN(ID, TYPE, ATTRS) \ 8325 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8326 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8327 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8328 #include "clang/Basic/BuiltinsWebAssembly.def" 8329 }; 8330 8331 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8332 public: 8333 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8334 const TargetOptions &Opts) 8335 : WebAssemblyTargetInfo(T, Opts) { 8336 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8337 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8338 } 8339 8340 protected: 8341 void getTargetDefines(const LangOptions &Opts, 8342 MacroBuilder &Builder) const override { 8343 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8344 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8345 } 8346 }; 8347 8348 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8349 public: 8350 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8351 const TargetOptions &Opts) 8352 : WebAssemblyTargetInfo(T, Opts) { 8353 LongAlign = LongWidth = 64; 8354 PointerAlign = PointerWidth = 64; 8355 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8356 SizeType = UnsignedLong; 8357 PtrDiffType = SignedLong; 8358 IntPtrType = SignedLong; 8359 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8360 } 8361 8362 protected: 8363 void getTargetDefines(const LangOptions &Opts, 8364 MacroBuilder &Builder) const override { 8365 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8366 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8367 } 8368 }; 8369 8370 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8371 #define BUILTIN(ID, TYPE, ATTRS) \ 8372 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8373 #include "clang/Basic/BuiltinsLe64.def" 8374 }; 8375 8376 static const unsigned SPIRAddrSpaceMap[] = { 8377 1, // opencl_global 8378 3, // opencl_local 8379 2, // opencl_constant 8380 4, // opencl_generic 8381 0, // cuda_device 8382 0, // cuda_constant 8383 0 // cuda_shared 8384 }; 8385 class SPIRTargetInfo : public TargetInfo { 8386 public: 8387 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8388 : TargetInfo(Triple) { 8389 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8390 "SPIR target must use unknown OS"); 8391 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8392 "SPIR target must use unknown environment type"); 8393 TLSSupported = false; 8394 LongWidth = LongAlign = 64; 8395 AddrSpaceMap = &SPIRAddrSpaceMap; 8396 UseAddrSpaceMapMangling = true; 8397 // Define available target features 8398 // These must be defined in sorted order! 8399 NoAsmVariants = true; 8400 } 8401 void getTargetDefines(const LangOptions &Opts, 8402 MacroBuilder &Builder) const override { 8403 DefineStd(Builder, "SPIR", Opts); 8404 } 8405 bool hasFeature(StringRef Feature) const override { 8406 return Feature == "spir"; 8407 } 8408 8409 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8410 const char *getClobbers() const override { return ""; } 8411 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8412 bool validateAsmConstraint(const char *&Name, 8413 TargetInfo::ConstraintInfo &info) const override { 8414 return true; 8415 } 8416 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8417 return None; 8418 } 8419 BuiltinVaListKind getBuiltinVaListKind() const override { 8420 return TargetInfo::VoidPtrBuiltinVaList; 8421 } 8422 8423 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8424 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8425 : CCCR_Warning; 8426 } 8427 8428 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8429 return CC_SpirFunction; 8430 } 8431 8432 void setSupportedOpenCLOpts() override { 8433 // Assume all OpenCL extensions and optional core features are supported 8434 // for SPIR since it is a generic target. 8435 getSupportedOpenCLOpts().supportAll(); 8436 } 8437 }; 8438 8439 class SPIR32TargetInfo : public SPIRTargetInfo { 8440 public: 8441 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8442 : SPIRTargetInfo(Triple, Opts) { 8443 PointerWidth = PointerAlign = 32; 8444 SizeType = TargetInfo::UnsignedInt; 8445 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8446 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8447 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8448 } 8449 void getTargetDefines(const LangOptions &Opts, 8450 MacroBuilder &Builder) const override { 8451 DefineStd(Builder, "SPIR32", Opts); 8452 } 8453 }; 8454 8455 class SPIR64TargetInfo : public SPIRTargetInfo { 8456 public: 8457 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8458 : SPIRTargetInfo(Triple, Opts) { 8459 PointerWidth = PointerAlign = 64; 8460 SizeType = TargetInfo::UnsignedLong; 8461 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8462 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8463 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8464 } 8465 void getTargetDefines(const LangOptions &Opts, 8466 MacroBuilder &Builder) const override { 8467 DefineStd(Builder, "SPIR64", Opts); 8468 } 8469 }; 8470 8471 class XCoreTargetInfo : public TargetInfo { 8472 static const Builtin::Info BuiltinInfo[]; 8473 public: 8474 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8475 : TargetInfo(Triple) { 8476 NoAsmVariants = true; 8477 LongLongAlign = 32; 8478 SuitableAlign = 32; 8479 DoubleAlign = LongDoubleAlign = 32; 8480 SizeType = UnsignedInt; 8481 PtrDiffType = SignedInt; 8482 IntPtrType = SignedInt; 8483 WCharType = UnsignedChar; 8484 WIntType = UnsignedInt; 8485 UseZeroLengthBitfieldAlignment = true; 8486 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8487 "-f64:32-a:0:32-n32"); 8488 } 8489 void getTargetDefines(const LangOptions &Opts, 8490 MacroBuilder &Builder) const override { 8491 Builder.defineMacro("__XS1B__"); 8492 } 8493 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8494 return llvm::makeArrayRef(BuiltinInfo, 8495 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8496 } 8497 BuiltinVaListKind getBuiltinVaListKind() const override { 8498 return TargetInfo::VoidPtrBuiltinVaList; 8499 } 8500 const char *getClobbers() const override { 8501 return ""; 8502 } 8503 ArrayRef<const char *> getGCCRegNames() const override { 8504 static const char * const GCCRegNames[] = { 8505 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8506 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8507 }; 8508 return llvm::makeArrayRef(GCCRegNames); 8509 } 8510 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8511 return None; 8512 } 8513 bool validateAsmConstraint(const char *&Name, 8514 TargetInfo::ConstraintInfo &Info) const override { 8515 return false; 8516 } 8517 int getEHDataRegisterNumber(unsigned RegNo) const override { 8518 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8519 return (RegNo < 2)? RegNo : -1; 8520 } 8521 bool allowsLargerPreferedTypeAlignment() const override { 8522 return false; 8523 } 8524 }; 8525 8526 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8527 #define BUILTIN(ID, TYPE, ATTRS) \ 8528 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8529 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8530 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8531 #include "clang/Basic/BuiltinsXCore.def" 8532 }; 8533 8534 // x86_32 Android target 8535 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8536 public: 8537 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8538 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8539 SuitableAlign = 32; 8540 LongDoubleWidth = 64; 8541 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8542 } 8543 }; 8544 8545 // x86_64 Android target 8546 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8547 public: 8548 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8549 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8550 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8551 } 8552 8553 bool useFloat128ManglingForLongDouble() const override { 8554 return true; 8555 } 8556 }; 8557 8558 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8559 class RenderScript32TargetInfo : public ARMleTargetInfo { 8560 public: 8561 RenderScript32TargetInfo(const llvm::Triple &Triple, 8562 const TargetOptions &Opts) 8563 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8564 Triple.getOSName(), 8565 Triple.getEnvironmentName()), 8566 Opts) { 8567 IsRenderScriptTarget = true; 8568 LongWidth = LongAlign = 64; 8569 } 8570 void getTargetDefines(const LangOptions &Opts, 8571 MacroBuilder &Builder) const override { 8572 Builder.defineMacro("__RENDERSCRIPT__"); 8573 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8574 } 8575 }; 8576 8577 // 64-bit RenderScript is aarch64 8578 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8579 public: 8580 RenderScript64TargetInfo(const llvm::Triple &Triple, 8581 const TargetOptions &Opts) 8582 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8583 Triple.getOSName(), 8584 Triple.getEnvironmentName()), 8585 Opts) { 8586 IsRenderScriptTarget = true; 8587 } 8588 8589 void getTargetDefines(const LangOptions &Opts, 8590 MacroBuilder &Builder) const override { 8591 Builder.defineMacro("__RENDERSCRIPT__"); 8592 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8593 } 8594 }; 8595 8596 /// Information about a specific microcontroller. 8597 struct MCUInfo { 8598 const char *Name; 8599 const char *DefineName; 8600 }; 8601 8602 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8603 static ArrayRef<MCUInfo> AVRMcus = { 8604 { "at90s1200", "__AVR_AT90S1200__" }, 8605 { "attiny11", "__AVR_ATtiny11__" }, 8606 { "attiny12", "__AVR_ATtiny12__" }, 8607 { "attiny15", "__AVR_ATtiny15__" }, 8608 { "attiny28", "__AVR_ATtiny28__" }, 8609 { "at90s2313", "__AVR_AT90S2313__" }, 8610 { "at90s2323", "__AVR_AT90S2323__" }, 8611 { "at90s2333", "__AVR_AT90S2333__" }, 8612 { "at90s2343", "__AVR_AT90S2343__" }, 8613 { "attiny22", "__AVR_ATtiny22__" }, 8614 { "attiny26", "__AVR_ATtiny26__" }, 8615 { "at86rf401", "__AVR_AT86RF401__" }, 8616 { "at90s4414", "__AVR_AT90S4414__" }, 8617 { "at90s4433", "__AVR_AT90S4433__" }, 8618 { "at90s4434", "__AVR_AT90S4434__" }, 8619 { "at90s8515", "__AVR_AT90S8515__" }, 8620 { "at90c8534", "__AVR_AT90c8534__" }, 8621 { "at90s8535", "__AVR_AT90S8535__" }, 8622 { "ata5272", "__AVR_ATA5272__" }, 8623 { "attiny13", "__AVR_ATtiny13__" }, 8624 { "attiny13a", "__AVR_ATtiny13A__" }, 8625 { "attiny2313", "__AVR_ATtiny2313__" }, 8626 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8627 { "attiny24", "__AVR_ATtiny24__" }, 8628 { "attiny24a", "__AVR_ATtiny24A__" }, 8629 { "attiny4313", "__AVR_ATtiny4313__" }, 8630 { "attiny44", "__AVR_ATtiny44__" }, 8631 { "attiny44a", "__AVR_ATtiny44A__" }, 8632 { "attiny84", "__AVR_ATtiny84__" }, 8633 { "attiny84a", "__AVR_ATtiny84A__" }, 8634 { "attiny25", "__AVR_ATtiny25__" }, 8635 { "attiny45", "__AVR_ATtiny45__" }, 8636 { "attiny85", "__AVR_ATtiny85__" }, 8637 { "attiny261", "__AVR_ATtiny261__" }, 8638 { "attiny261a", "__AVR_ATtiny261A__" }, 8639 { "attiny461", "__AVR_ATtiny461__" }, 8640 { "attiny461a", "__AVR_ATtiny461A__" }, 8641 { "attiny861", "__AVR_ATtiny861__" }, 8642 { "attiny861a", "__AVR_ATtiny861A__" }, 8643 { "attiny87", "__AVR_ATtiny87__" }, 8644 { "attiny43u", "__AVR_ATtiny43U__" }, 8645 { "attiny48", "__AVR_ATtiny48__" }, 8646 { "attiny88", "__AVR_ATtiny88__" }, 8647 { "attiny828", "__AVR_ATtiny828__" }, 8648 { "at43usb355", "__AVR_AT43USB355__" }, 8649 { "at76c711", "__AVR_AT76C711__" }, 8650 { "atmega103", "__AVR_ATmega103__" }, 8651 { "at43usb320", "__AVR_AT43USB320__" }, 8652 { "attiny167", "__AVR_ATtiny167__" }, 8653 { "at90usb82", "__AVR_AT90USB82__" }, 8654 { "at90usb162", "__AVR_AT90USB162__" }, 8655 { "ata5505", "__AVR_ATA5505__" }, 8656 { "atmega8u2", "__AVR_ATmega8U2__" }, 8657 { "atmega16u2", "__AVR_ATmega16U2__" }, 8658 { "atmega32u2", "__AVR_ATmega32U2__" }, 8659 { "attiny1634", "__AVR_ATtiny1634__" }, 8660 { "atmega8", "__AVR_ATmega8__" }, 8661 { "ata6289", "__AVR_ATA6289__" }, 8662 { "atmega8a", "__AVR_ATmega8A__" }, 8663 { "ata6285", "__AVR_ATA6285__" }, 8664 { "ata6286", "__AVR_ATA6286__" }, 8665 { "atmega48", "__AVR_ATmega48__" }, 8666 { "atmega48a", "__AVR_ATmega48A__" }, 8667 { "atmega48pa", "__AVR_ATmega48PA__" }, 8668 { "atmega48p", "__AVR_ATmega48P__" }, 8669 { "atmega88", "__AVR_ATmega88__" }, 8670 { "atmega88a", "__AVR_ATmega88A__" }, 8671 { "atmega88p", "__AVR_ATmega88P__" }, 8672 { "atmega88pa", "__AVR_ATmega88PA__" }, 8673 { "atmega8515", "__AVR_ATmega8515__" }, 8674 { "atmega8535", "__AVR_ATmega8535__" }, 8675 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8676 { "at90pwm1", "__AVR_AT90PWM1__" }, 8677 { "at90pwm2", "__AVR_AT90PWM2__" }, 8678 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8679 { "at90pwm3", "__AVR_AT90PWM3__" }, 8680 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8681 { "at90pwm81", "__AVR_AT90PWM81__" }, 8682 { "ata5790", "__AVR_ATA5790__" }, 8683 { "ata5795", "__AVR_ATA5795__" }, 8684 { "atmega16", "__AVR_ATmega16__" }, 8685 { "atmega16a", "__AVR_ATmega16A__" }, 8686 { "atmega161", "__AVR_ATmega161__" }, 8687 { "atmega162", "__AVR_ATmega162__" }, 8688 { "atmega163", "__AVR_ATmega163__" }, 8689 { "atmega164a", "__AVR_ATmega164A__" }, 8690 { "atmega164p", "__AVR_ATmega164P__" }, 8691 { "atmega164pa", "__AVR_ATmega164PA__" }, 8692 { "atmega165", "__AVR_ATmega165__" }, 8693 { "atmega165a", "__AVR_ATmega165A__" }, 8694 { "atmega165p", "__AVR_ATmega165P__" }, 8695 { "atmega165pa", "__AVR_ATmega165PA__" }, 8696 { "atmega168", "__AVR_ATmega168__" }, 8697 { "atmega168a", "__AVR_ATmega168A__" }, 8698 { "atmega168p", "__AVR_ATmega168P__" }, 8699 { "atmega168pa", "__AVR_ATmega168PA__" }, 8700 { "atmega169", "__AVR_ATmega169__" }, 8701 { "atmega169a", "__AVR_ATmega169A__" }, 8702 { "atmega169p", "__AVR_ATmega169P__" }, 8703 { "atmega169pa", "__AVR_ATmega169PA__" }, 8704 { "atmega32", "__AVR_ATmega32__" }, 8705 { "atmega32a", "__AVR_ATmega32A__" }, 8706 { "atmega323", "__AVR_ATmega323__" }, 8707 { "atmega324a", "__AVR_ATmega324A__" }, 8708 { "atmega324p", "__AVR_ATmega324P__" }, 8709 { "atmega324pa", "__AVR_ATmega324PA__" }, 8710 { "atmega325", "__AVR_ATmega325__" }, 8711 { "atmega325a", "__AVR_ATmega325A__" }, 8712 { "atmega325p", "__AVR_ATmega325P__" }, 8713 { "atmega325pa", "__AVR_ATmega325PA__" }, 8714 { "atmega3250", "__AVR_ATmega3250__" }, 8715 { "atmega3250a", "__AVR_ATmega3250A__" }, 8716 { "atmega3250p", "__AVR_ATmega3250P__" }, 8717 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8718 { "atmega328", "__AVR_ATmega328__" }, 8719 { "atmega328p", "__AVR_ATmega328P__" }, 8720 { "atmega329", "__AVR_ATmega329__" }, 8721 { "atmega329a", "__AVR_ATmega329A__" }, 8722 { "atmega329p", "__AVR_ATmega329P__" }, 8723 { "atmega329pa", "__AVR_ATmega329PA__" }, 8724 { "atmega3290", "__AVR_ATmega3290__" }, 8725 { "atmega3290a", "__AVR_ATmega3290A__" }, 8726 { "atmega3290p", "__AVR_ATmega3290P__" }, 8727 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8728 { "atmega406", "__AVR_ATmega406__" }, 8729 { "atmega64", "__AVR_ATmega64__" }, 8730 { "atmega64a", "__AVR_ATmega64A__" }, 8731 { "atmega640", "__AVR_ATmega640__" }, 8732 { "atmega644", "__AVR_ATmega644__" }, 8733 { "atmega644a", "__AVR_ATmega644A__" }, 8734 { "atmega644p", "__AVR_ATmega644P__" }, 8735 { "atmega644pa", "__AVR_ATmega644PA__" }, 8736 { "atmega645", "__AVR_ATmega645__" }, 8737 { "atmega645a", "__AVR_ATmega645A__" }, 8738 { "atmega645p", "__AVR_ATmega645P__" }, 8739 { "atmega649", "__AVR_ATmega649__" }, 8740 { "atmega649a", "__AVR_ATmega649A__" }, 8741 { "atmega649p", "__AVR_ATmega649P__" }, 8742 { "atmega6450", "__AVR_ATmega6450__" }, 8743 { "atmega6450a", "__AVR_ATmega6450A__" }, 8744 { "atmega6450p", "__AVR_ATmega6450P__" }, 8745 { "atmega6490", "__AVR_ATmega6490__" }, 8746 { "atmega6490a", "__AVR_ATmega6490A__" }, 8747 { "atmega6490p", "__AVR_ATmega6490P__" }, 8748 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8749 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8750 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8751 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8752 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8753 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8754 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8755 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8756 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8757 { "at90can32", "__AVR_AT90CAN32__" }, 8758 { "at90can64", "__AVR_AT90CAN64__" }, 8759 { "at90pwm161", "__AVR_AT90PWM161__" }, 8760 { "at90pwm216", "__AVR_AT90PWM216__" }, 8761 { "at90pwm316", "__AVR_AT90PWM316__" }, 8762 { "atmega32c1", "__AVR_ATmega32C1__" }, 8763 { "atmega64c1", "__AVR_ATmega64C1__" }, 8764 { "atmega16m1", "__AVR_ATmega16M1__" }, 8765 { "atmega32m1", "__AVR_ATmega32M1__" }, 8766 { "atmega64m1", "__AVR_ATmega64M1__" }, 8767 { "atmega16u4", "__AVR_ATmega16U4__" }, 8768 { "atmega32u4", "__AVR_ATmega32U4__" }, 8769 { "atmega32u6", "__AVR_ATmega32U6__" }, 8770 { "at90usb646", "__AVR_AT90USB646__" }, 8771 { "at90usb647", "__AVR_AT90USB647__" }, 8772 { "at90scr100", "__AVR_AT90SCR100__" }, 8773 { "at94k", "__AVR_AT94K__" }, 8774 { "m3000", "__AVR_AT000__" }, 8775 { "atmega128", "__AVR_ATmega128__" }, 8776 { "atmega128a", "__AVR_ATmega128A__" }, 8777 { "atmega1280", "__AVR_ATmega1280__" }, 8778 { "atmega1281", "__AVR_ATmega1281__" }, 8779 { "atmega1284", "__AVR_ATmega1284__" }, 8780 { "atmega1284p", "__AVR_ATmega1284P__" }, 8781 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8782 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8783 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8784 { "at90can128", "__AVR_AT90CAN128__" }, 8785 { "at90usb1286", "__AVR_AT90USB1286__" }, 8786 { "at90usb1287", "__AVR_AT90USB1287__" }, 8787 { "atmega2560", "__AVR_ATmega2560__" }, 8788 { "atmega2561", "__AVR_ATmega2561__" }, 8789 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8790 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8791 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8792 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8793 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8794 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8795 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8796 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8797 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8798 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8799 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8800 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8801 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8802 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8803 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8804 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8805 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8806 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8807 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8808 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8809 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8810 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8811 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8812 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8813 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8814 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8815 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8816 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8817 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8818 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8819 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8820 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8821 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8822 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8823 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8824 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8825 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8826 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8827 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8828 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8829 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8830 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8831 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8832 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8833 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8834 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8835 { "attiny4", "__AVR_ATtiny4__" }, 8836 { "attiny5", "__AVR_ATtiny5__" }, 8837 { "attiny9", "__AVR_ATtiny9__" }, 8838 { "attiny10", "__AVR_ATtiny10__" }, 8839 { "attiny20", "__AVR_ATtiny20__" }, 8840 { "attiny40", "__AVR_ATtiny40__" }, 8841 { "attiny102", "__AVR_ATtiny102__" }, 8842 { "attiny104", "__AVR_ATtiny104__" }, 8843 }; 8844 8845 // AVR Target 8846 class AVRTargetInfo : public TargetInfo { 8847 public: 8848 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8849 : TargetInfo(Triple) { 8850 TLSSupported = false; 8851 PointerWidth = 16; 8852 PointerAlign = 8; 8853 IntWidth = 16; 8854 IntAlign = 8; 8855 LongWidth = 32; 8856 LongAlign = 8; 8857 LongLongWidth = 64; 8858 LongLongAlign = 8; 8859 SuitableAlign = 8; 8860 DefaultAlignForAttributeAligned = 8; 8861 HalfWidth = 16; 8862 HalfAlign = 8; 8863 FloatWidth = 32; 8864 FloatAlign = 8; 8865 DoubleWidth = 32; 8866 DoubleAlign = 8; 8867 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8868 LongDoubleWidth = 32; 8869 LongDoubleAlign = 8; 8870 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8871 SizeType = UnsignedInt; 8872 PtrDiffType = SignedInt; 8873 IntPtrType = SignedInt; 8874 Char16Type = UnsignedInt; 8875 WCharType = SignedInt; 8876 WIntType = SignedInt; 8877 Char32Type = UnsignedLong; 8878 SigAtomicType = SignedChar; 8879 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8880 "-f32:32:32-f64:64:64-n8"); 8881 } 8882 8883 void getTargetDefines(const LangOptions &Opts, 8884 MacroBuilder &Builder) const override { 8885 Builder.defineMacro("AVR"); 8886 Builder.defineMacro("__AVR"); 8887 Builder.defineMacro("__AVR__"); 8888 8889 if (!this->CPU.empty()) { 8890 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8891 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8892 8893 if (It != AVRMcus.end()) 8894 Builder.defineMacro(It->DefineName); 8895 } 8896 } 8897 8898 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8899 return None; 8900 } 8901 8902 BuiltinVaListKind getBuiltinVaListKind() const override { 8903 return TargetInfo::VoidPtrBuiltinVaList; 8904 } 8905 8906 const char *getClobbers() const override { 8907 return ""; 8908 } 8909 8910 ArrayRef<const char *> getGCCRegNames() const override { 8911 static const char * const GCCRegNames[] = { 8912 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8913 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8914 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8915 "r24", "r25", "X", "Y", "Z", "SP" 8916 }; 8917 return llvm::makeArrayRef(GCCRegNames); 8918 } 8919 8920 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8921 return None; 8922 } 8923 8924 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8925 static const TargetInfo::AddlRegName AddlRegNames[] = { 8926 { { "r26", "r27"}, 26 }, 8927 { { "r28", "r29"}, 27 }, 8928 { { "r30", "r31"}, 28 }, 8929 { { "SPL", "SPH"}, 29 }, 8930 }; 8931 return llvm::makeArrayRef(AddlRegNames); 8932 } 8933 8934 bool validateAsmConstraint(const char *&Name, 8935 TargetInfo::ConstraintInfo &Info) const override { 8936 // There aren't any multi-character AVR specific constraints. 8937 if (StringRef(Name).size() > 1) return false; 8938 8939 switch (*Name) { 8940 default: return false; 8941 case 'a': // Simple upper registers 8942 case 'b': // Base pointer registers pairs 8943 case 'd': // Upper register 8944 case 'l': // Lower registers 8945 case 'e': // Pointer register pairs 8946 case 'q': // Stack pointer register 8947 case 'r': // Any register 8948 case 'w': // Special upper register pairs 8949 case 't': // Temporary register 8950 case 'x': case 'X': // Pointer register pair X 8951 case 'y': case 'Y': // Pointer register pair Y 8952 case 'z': case 'Z': // Pointer register pair Z 8953 Info.setAllowsRegister(); 8954 return true; 8955 case 'I': // 6-bit positive integer constant 8956 Info.setRequiresImmediate(0, 63); 8957 return true; 8958 case 'J': // 6-bit negative integer constant 8959 Info.setRequiresImmediate(-63, 0); 8960 return true; 8961 case 'K': // Integer constant (Range: 2) 8962 Info.setRequiresImmediate(2); 8963 return true; 8964 case 'L': // Integer constant (Range: 0) 8965 Info.setRequiresImmediate(0); 8966 return true; 8967 case 'M': // 8-bit integer constant 8968 Info.setRequiresImmediate(0, 0xff); 8969 return true; 8970 case 'N': // Integer constant (Range: -1) 8971 Info.setRequiresImmediate(-1); 8972 return true; 8973 case 'O': // Integer constant (Range: 8, 16, 24) 8974 Info.setRequiresImmediate({8, 16, 24}); 8975 return true; 8976 case 'P': // Integer constant (Range: 1) 8977 Info.setRequiresImmediate(1); 8978 return true; 8979 case 'R': // Integer constant (Range: -6 to 5) 8980 Info.setRequiresImmediate(-6, 5); 8981 return true; 8982 case 'G': // Floating point constant 8983 case 'Q': // A memory address based on Y or Z pointer with displacement. 8984 return true; 8985 } 8986 8987 return false; 8988 } 8989 8990 IntType getIntTypeByWidth(unsigned BitWidth, 8991 bool IsSigned) const final { 8992 // AVR prefers int for 16-bit integers. 8993 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 8994 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8995 } 8996 8997 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8998 bool IsSigned) const final { 8999 // AVR uses int for int_least16_t and int_fast16_t. 9000 return BitWidth == 16 9001 ? (IsSigned ? SignedInt : UnsignedInt) 9002 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9003 } 9004 9005 bool setCPU(const std::string &Name) override { 9006 bool IsFamily = llvm::StringSwitch<bool>(Name) 9007 .Case("avr1", true) 9008 .Case("avr2", true) 9009 .Case("avr25", true) 9010 .Case("avr3", true) 9011 .Case("avr31", true) 9012 .Case("avr35", true) 9013 .Case("avr4", true) 9014 .Case("avr5", true) 9015 .Case("avr51", true) 9016 .Case("avr6", true) 9017 .Case("avrxmega1", true) 9018 .Case("avrxmega2", true) 9019 .Case("avrxmega3", true) 9020 .Case("avrxmega4", true) 9021 .Case("avrxmega5", true) 9022 .Case("avrxmega6", true) 9023 .Case("avrxmega7", true) 9024 .Case("avrtiny", true) 9025 .Default(false); 9026 9027 if (IsFamily) this->CPU = Name; 9028 9029 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9030 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9031 9032 if (IsMCU) this->CPU = Name; 9033 9034 return IsFamily || IsMCU; 9035 } 9036 9037 protected: 9038 std::string CPU; 9039 }; 9040 9041 } // end anonymous namespace 9042 9043 //===----------------------------------------------------------------------===// 9044 // Driver code 9045 //===----------------------------------------------------------------------===// 9046 9047 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9048 const TargetOptions &Opts) { 9049 llvm::Triple::OSType os = Triple.getOS(); 9050 9051 switch (Triple.getArch()) { 9052 default: 9053 return nullptr; 9054 9055 case llvm::Triple::xcore: 9056 return new XCoreTargetInfo(Triple, Opts); 9057 9058 case llvm::Triple::hexagon: 9059 return new HexagonTargetInfo(Triple, Opts); 9060 9061 case llvm::Triple::lanai: 9062 return new LanaiTargetInfo(Triple, Opts); 9063 9064 case llvm::Triple::aarch64: 9065 if (Triple.isOSDarwin()) 9066 return new DarwinAArch64TargetInfo(Triple, Opts); 9067 9068 switch (os) { 9069 case llvm::Triple::CloudABI: 9070 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9071 case llvm::Triple::FreeBSD: 9072 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9073 case llvm::Triple::Fuchsia: 9074 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9075 case llvm::Triple::Linux: 9076 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9077 case llvm::Triple::NetBSD: 9078 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9079 case llvm::Triple::OpenBSD: 9080 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9081 default: 9082 return new AArch64leTargetInfo(Triple, Opts); 9083 } 9084 9085 case llvm::Triple::aarch64_be: 9086 switch (os) { 9087 case llvm::Triple::FreeBSD: 9088 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9089 case llvm::Triple::Fuchsia: 9090 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9091 case llvm::Triple::Linux: 9092 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9093 case llvm::Triple::NetBSD: 9094 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9095 default: 9096 return new AArch64beTargetInfo(Triple, Opts); 9097 } 9098 9099 case llvm::Triple::arm: 9100 case llvm::Triple::thumb: 9101 if (Triple.isOSBinFormatMachO()) 9102 return new DarwinARMTargetInfo(Triple, Opts); 9103 9104 switch (os) { 9105 case llvm::Triple::CloudABI: 9106 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9107 case llvm::Triple::Linux: 9108 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9109 case llvm::Triple::FreeBSD: 9110 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9111 case llvm::Triple::NetBSD: 9112 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9113 case llvm::Triple::OpenBSD: 9114 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9115 case llvm::Triple::Bitrig: 9116 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9117 case llvm::Triple::RTEMS: 9118 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9119 case llvm::Triple::NaCl: 9120 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9121 case llvm::Triple::Win32: 9122 switch (Triple.getEnvironment()) { 9123 case llvm::Triple::Cygnus: 9124 return new CygwinARMTargetInfo(Triple, Opts); 9125 case llvm::Triple::GNU: 9126 return new MinGWARMTargetInfo(Triple, Opts); 9127 case llvm::Triple::Itanium: 9128 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9129 case llvm::Triple::MSVC: 9130 default: // Assume MSVC for unknown environments 9131 return new MicrosoftARMleTargetInfo(Triple, Opts); 9132 } 9133 default: 9134 return new ARMleTargetInfo(Triple, Opts); 9135 } 9136 9137 case llvm::Triple::armeb: 9138 case llvm::Triple::thumbeb: 9139 if (Triple.isOSDarwin()) 9140 return new DarwinARMTargetInfo(Triple, Opts); 9141 9142 switch (os) { 9143 case llvm::Triple::Linux: 9144 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9145 case llvm::Triple::FreeBSD: 9146 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9147 case llvm::Triple::NetBSD: 9148 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9149 case llvm::Triple::OpenBSD: 9150 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9151 case llvm::Triple::Bitrig: 9152 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9153 case llvm::Triple::RTEMS: 9154 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9155 case llvm::Triple::NaCl: 9156 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9157 default: 9158 return new ARMbeTargetInfo(Triple, Opts); 9159 } 9160 9161 case llvm::Triple::avr: 9162 return new AVRTargetInfo(Triple, Opts); 9163 case llvm::Triple::bpfeb: 9164 case llvm::Triple::bpfel: 9165 return new BPFTargetInfo(Triple, Opts); 9166 9167 case llvm::Triple::msp430: 9168 return new MSP430TargetInfo(Triple, Opts); 9169 9170 case llvm::Triple::mips: 9171 switch (os) { 9172 case llvm::Triple::Linux: 9173 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9174 case llvm::Triple::RTEMS: 9175 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9176 case llvm::Triple::FreeBSD: 9177 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9178 case llvm::Triple::NetBSD: 9179 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9180 default: 9181 return new MipsTargetInfo(Triple, Opts); 9182 } 9183 9184 case llvm::Triple::mipsel: 9185 switch (os) { 9186 case llvm::Triple::Linux: 9187 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9188 case llvm::Triple::RTEMS: 9189 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9190 case llvm::Triple::FreeBSD: 9191 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9192 case llvm::Triple::NetBSD: 9193 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9194 case llvm::Triple::NaCl: 9195 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9196 default: 9197 return new MipsTargetInfo(Triple, Opts); 9198 } 9199 9200 case llvm::Triple::mips64: 9201 switch (os) { 9202 case llvm::Triple::Linux: 9203 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9204 case llvm::Triple::RTEMS: 9205 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9206 case llvm::Triple::FreeBSD: 9207 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9208 case llvm::Triple::NetBSD: 9209 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9210 case llvm::Triple::OpenBSD: 9211 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9212 default: 9213 return new MipsTargetInfo(Triple, Opts); 9214 } 9215 9216 case llvm::Triple::mips64el: 9217 switch (os) { 9218 case llvm::Triple::Linux: 9219 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9220 case llvm::Triple::RTEMS: 9221 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9222 case llvm::Triple::FreeBSD: 9223 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9224 case llvm::Triple::NetBSD: 9225 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9226 case llvm::Triple::OpenBSD: 9227 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9228 default: 9229 return new MipsTargetInfo(Triple, Opts); 9230 } 9231 9232 case llvm::Triple::le32: 9233 switch (os) { 9234 case llvm::Triple::NaCl: 9235 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9236 default: 9237 return nullptr; 9238 } 9239 9240 case llvm::Triple::le64: 9241 return new Le64TargetInfo(Triple, Opts); 9242 9243 case llvm::Triple::ppc: 9244 if (Triple.isOSDarwin()) 9245 return new DarwinPPC32TargetInfo(Triple, Opts); 9246 switch (os) { 9247 case llvm::Triple::Linux: 9248 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9249 case llvm::Triple::FreeBSD: 9250 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9251 case llvm::Triple::NetBSD: 9252 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9253 case llvm::Triple::OpenBSD: 9254 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9255 case llvm::Triple::RTEMS: 9256 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9257 default: 9258 return new PPC32TargetInfo(Triple, Opts); 9259 } 9260 9261 case llvm::Triple::ppc64: 9262 if (Triple.isOSDarwin()) 9263 return new DarwinPPC64TargetInfo(Triple, Opts); 9264 switch (os) { 9265 case llvm::Triple::Linux: 9266 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9267 case llvm::Triple::Lv2: 9268 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9269 case llvm::Triple::FreeBSD: 9270 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9271 case llvm::Triple::NetBSD: 9272 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9273 default: 9274 return new PPC64TargetInfo(Triple, Opts); 9275 } 9276 9277 case llvm::Triple::ppc64le: 9278 switch (os) { 9279 case llvm::Triple::Linux: 9280 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9281 case llvm::Triple::NetBSD: 9282 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9283 default: 9284 return new PPC64TargetInfo(Triple, Opts); 9285 } 9286 9287 case llvm::Triple::nvptx: 9288 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9289 case llvm::Triple::nvptx64: 9290 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9291 9292 case llvm::Triple::amdgcn: 9293 case llvm::Triple::r600: 9294 return new AMDGPUTargetInfo(Triple, Opts); 9295 9296 case llvm::Triple::sparc: 9297 switch (os) { 9298 case llvm::Triple::Linux: 9299 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9300 case llvm::Triple::Solaris: 9301 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9302 case llvm::Triple::NetBSD: 9303 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9304 case llvm::Triple::OpenBSD: 9305 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9306 case llvm::Triple::RTEMS: 9307 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9308 default: 9309 return new SparcV8TargetInfo(Triple, Opts); 9310 } 9311 9312 // The 'sparcel' architecture copies all the above cases except for Solaris. 9313 case llvm::Triple::sparcel: 9314 switch (os) { 9315 case llvm::Triple::Linux: 9316 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9317 case llvm::Triple::NetBSD: 9318 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9319 case llvm::Triple::OpenBSD: 9320 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9321 case llvm::Triple::RTEMS: 9322 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9323 default: 9324 return new SparcV8elTargetInfo(Triple, Opts); 9325 } 9326 9327 case llvm::Triple::sparcv9: 9328 switch (os) { 9329 case llvm::Triple::Linux: 9330 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9331 case llvm::Triple::Solaris: 9332 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9333 case llvm::Triple::NetBSD: 9334 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9335 case llvm::Triple::OpenBSD: 9336 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9337 case llvm::Triple::FreeBSD: 9338 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9339 default: 9340 return new SparcV9TargetInfo(Triple, Opts); 9341 } 9342 9343 case llvm::Triple::systemz: 9344 switch (os) { 9345 case llvm::Triple::Linux: 9346 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9347 default: 9348 return new SystemZTargetInfo(Triple, Opts); 9349 } 9350 9351 case llvm::Triple::tce: 9352 return new TCETargetInfo(Triple, Opts); 9353 9354 case llvm::Triple::tcele: 9355 return new TCELETargetInfo(Triple, Opts); 9356 9357 case llvm::Triple::x86: 9358 if (Triple.isOSDarwin()) 9359 return new DarwinI386TargetInfo(Triple, Opts); 9360 9361 switch (os) { 9362 case llvm::Triple::CloudABI: 9363 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9364 case llvm::Triple::Linux: { 9365 switch (Triple.getEnvironment()) { 9366 default: 9367 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9368 case llvm::Triple::Android: 9369 return new AndroidX86_32TargetInfo(Triple, Opts); 9370 } 9371 } 9372 case llvm::Triple::DragonFly: 9373 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9374 case llvm::Triple::NetBSD: 9375 return new NetBSDI386TargetInfo(Triple, Opts); 9376 case llvm::Triple::OpenBSD: 9377 return new OpenBSDI386TargetInfo(Triple, Opts); 9378 case llvm::Triple::Bitrig: 9379 return new BitrigI386TargetInfo(Triple, Opts); 9380 case llvm::Triple::FreeBSD: 9381 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9382 case llvm::Triple::KFreeBSD: 9383 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9384 case llvm::Triple::Minix: 9385 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9386 case llvm::Triple::Solaris: 9387 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9388 case llvm::Triple::Win32: { 9389 switch (Triple.getEnvironment()) { 9390 case llvm::Triple::Cygnus: 9391 return new CygwinX86_32TargetInfo(Triple, Opts); 9392 case llvm::Triple::GNU: 9393 return new MinGWX86_32TargetInfo(Triple, Opts); 9394 case llvm::Triple::Itanium: 9395 case llvm::Triple::MSVC: 9396 default: // Assume MSVC for unknown environments 9397 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9398 } 9399 } 9400 case llvm::Triple::Haiku: 9401 return new HaikuX86_32TargetInfo(Triple, Opts); 9402 case llvm::Triple::RTEMS: 9403 return new RTEMSX86_32TargetInfo(Triple, Opts); 9404 case llvm::Triple::NaCl: 9405 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9406 case llvm::Triple::ELFIAMCU: 9407 return new MCUX86_32TargetInfo(Triple, Opts); 9408 default: 9409 return new X86_32TargetInfo(Triple, Opts); 9410 } 9411 9412 case llvm::Triple::x86_64: 9413 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9414 return new DarwinX86_64TargetInfo(Triple, Opts); 9415 9416 switch (os) { 9417 case llvm::Triple::CloudABI: 9418 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9419 case llvm::Triple::Linux: { 9420 switch (Triple.getEnvironment()) { 9421 default: 9422 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9423 case llvm::Triple::Android: 9424 return new AndroidX86_64TargetInfo(Triple, Opts); 9425 } 9426 } 9427 case llvm::Triple::DragonFly: 9428 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9429 case llvm::Triple::NetBSD: 9430 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9431 case llvm::Triple::OpenBSD: 9432 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9433 case llvm::Triple::Bitrig: 9434 return new BitrigX86_64TargetInfo(Triple, Opts); 9435 case llvm::Triple::FreeBSD: 9436 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9437 case llvm::Triple::Fuchsia: 9438 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9439 case llvm::Triple::KFreeBSD: 9440 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9441 case llvm::Triple::Solaris: 9442 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9443 case llvm::Triple::Win32: { 9444 switch (Triple.getEnvironment()) { 9445 case llvm::Triple::Cygnus: 9446 return new CygwinX86_64TargetInfo(Triple, Opts); 9447 case llvm::Triple::GNU: 9448 return new MinGWX86_64TargetInfo(Triple, Opts); 9449 case llvm::Triple::MSVC: 9450 default: // Assume MSVC for unknown environments 9451 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9452 } 9453 } 9454 case llvm::Triple::Haiku: 9455 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9456 case llvm::Triple::NaCl: 9457 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9458 case llvm::Triple::PS4: 9459 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9460 default: 9461 return new X86_64TargetInfo(Triple, Opts); 9462 } 9463 9464 case llvm::Triple::spir: { 9465 if (Triple.getOS() != llvm::Triple::UnknownOS || 9466 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9467 return nullptr; 9468 return new SPIR32TargetInfo(Triple, Opts); 9469 } 9470 case llvm::Triple::spir64: { 9471 if (Triple.getOS() != llvm::Triple::UnknownOS || 9472 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9473 return nullptr; 9474 return new SPIR64TargetInfo(Triple, Opts); 9475 } 9476 case llvm::Triple::wasm32: 9477 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9478 Triple.getVendor() != llvm::Triple::UnknownVendor || 9479 Triple.getOS() != llvm::Triple::UnknownOS || 9480 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9481 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9482 return nullptr; 9483 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9484 case llvm::Triple::wasm64: 9485 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9486 Triple.getVendor() != llvm::Triple::UnknownVendor || 9487 Triple.getOS() != llvm::Triple::UnknownOS || 9488 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9489 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9490 return nullptr; 9491 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9492 9493 case llvm::Triple::renderscript32: 9494 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9495 case llvm::Triple::renderscript64: 9496 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9497 } 9498 } 9499 9500 /// CreateTargetInfo - Return the target info object for the specified target 9501 /// options. 9502 TargetInfo * 9503 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9504 const std::shared_ptr<TargetOptions> &Opts) { 9505 llvm::Triple Triple(Opts->Triple); 9506 9507 // Construct the target 9508 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9509 if (!Target) { 9510 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9511 return nullptr; 9512 } 9513 Target->TargetOpts = Opts; 9514 9515 // Set the target CPU if specified. 9516 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9517 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9518 return nullptr; 9519 } 9520 9521 // Set the target ABI if specified. 9522 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9523 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9524 return nullptr; 9525 } 9526 9527 // Set the fp math unit. 9528 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9529 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9530 return nullptr; 9531 } 9532 9533 // Compute the default target features, we need the target to handle this 9534 // because features may have dependencies on one another. 9535 llvm::StringMap<bool> Features; 9536 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9537 Opts->FeaturesAsWritten)) 9538 return nullptr; 9539 9540 // Add the features to the compile options. 9541 Opts->Features.clear(); 9542 for (const auto &F : Features) 9543 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9544 9545 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9546 return nullptr; 9547 9548 Target->setSupportedOpenCLOpts(); 9549 Target->setOpenCLExtensionOpts(); 9550 9551 if (!Target->validateTarget(Diags)) 9552 return nullptr; 9553 9554 return Target.release(); 9555 } 9556