1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringExtras.h"
25 #include "llvm/ADT/StringRef.h"
26 #include "llvm/ADT/StringSwitch.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/MC/MCSectionMachO.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include <algorithm>
32 #include <memory>
33 using namespace clang;
34 
35 //===----------------------------------------------------------------------===//
36 //  Common code shared among targets.
37 //===----------------------------------------------------------------------===//
38 
39 /// DefineStd - Define a macro name and standard variants.  For example if
40 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
41 /// when in GNU mode.
42 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
43                       const LangOptions &Opts) {
44   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
45 
46   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
47   // in the user's namespace.
48   if (Opts.GNUMode)
49     Builder.defineMacro(MacroName);
50 
51   // Define __unix.
52   Builder.defineMacro("__" + MacroName);
53 
54   // Define __unix__.
55   Builder.defineMacro("__" + MacroName + "__");
56 }
57 
58 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
59                             bool Tuning = true) {
60   Builder.defineMacro("__" + CPUName);
61   Builder.defineMacro("__" + CPUName + "__");
62   if (Tuning)
63     Builder.defineMacro("__tune_" + CPUName + "__");
64 }
65 
66 //===----------------------------------------------------------------------===//
67 // Defines specific to certain operating systems.
68 //===----------------------------------------------------------------------===//
69 
70 namespace {
71 template<typename TgtInfo>
72 class OSTargetInfo : public TgtInfo {
73 protected:
74   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
75                             MacroBuilder &Builder) const=0;
76 public:
77   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
78   void getTargetDefines(const LangOptions &Opts,
79                         MacroBuilder &Builder) const override {
80     TgtInfo::getTargetDefines(Opts, Builder);
81     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
82   }
83 
84 };
85 } // end anonymous namespace
86 
87 
88 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
89                              const llvm::Triple &Triple,
90                              StringRef &PlatformName,
91                              VersionTuple &PlatformMinVersion) {
92   Builder.defineMacro("__APPLE_CC__", "6000");
93   Builder.defineMacro("__APPLE__");
94   Builder.defineMacro("OBJC_NEW_PROPERTIES");
95   // AddressSanitizer doesn't play well with source fortification, which is on
96   // by default on Darwin.
97   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
98 
99   if (!Opts.ObjCAutoRefCount) {
100     // __weak is always defined, for use in blocks and with objc pointers.
101     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
102 
103     // Darwin defines __strong even in C mode (just to nothing).
104     if (Opts.getGC() != LangOptions::NonGC)
105       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
106     else
107       Builder.defineMacro("__strong", "");
108 
109     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
110     // allow this in C, since one might have block pointers in structs that
111     // are used in pure C code and in Objective-C ARC.
112     Builder.defineMacro("__unsafe_unretained", "");
113   }
114 
115   if (Opts.Static)
116     Builder.defineMacro("__STATIC__");
117   else
118     Builder.defineMacro("__DYNAMIC__");
119 
120   if (Opts.POSIXThreads)
121     Builder.defineMacro("_REENTRANT");
122 
123   // Get the platform type and version number from the triple.
124   unsigned Maj, Min, Rev;
125   if (Triple.isMacOSX()) {
126     Triple.getMacOSXVersion(Maj, Min, Rev);
127     PlatformName = "macosx";
128   } else {
129     Triple.getOSVersion(Maj, Min, Rev);
130     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
131   }
132 
133   // If -target arch-pc-win32-macho option specified, we're
134   // generating code for Win32 ABI. No need to emit
135   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
136   if (PlatformName == "win32") {
137     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
138     return;
139   }
140 
141   // Set the appropriate OS version define.
142   if (Triple.isiOS()) {
143     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
144     char Str[6];
145     Str[0] = '0' + Maj;
146     Str[1] = '0' + (Min / 10);
147     Str[2] = '0' + (Min % 10);
148     Str[3] = '0' + (Rev / 10);
149     Str[4] = '0' + (Rev % 10);
150     Str[5] = '\0';
151     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
152                         Str);
153   } else if (Triple.isMacOSX()) {
154     // Note that the Driver allows versions which aren't representable in the
155     // define (because we only get a single digit for the minor and micro
156     // revision numbers). So, we limit them to the maximum representable
157     // version.
158     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
159     char Str[7];
160     if (Maj < 10 || (Maj == 10 && Min < 10)) {
161       Str[0] = '0' + (Maj / 10);
162       Str[1] = '0' + (Maj % 10);
163       Str[2] = '0' + std::min(Min, 9U);
164       Str[3] = '0' + std::min(Rev, 9U);
165       Str[4] = '\0';
166     } else {
167       // Handle versions > 10.9.
168       Str[0] = '0' + (Maj / 10);
169       Str[1] = '0' + (Maj % 10);
170       Str[2] = '0' + (Min / 10);
171       Str[3] = '0' + (Min % 10);
172       Str[4] = '0' + (Rev / 10);
173       Str[5] = '0' + (Rev % 10);
174       Str[6] = '\0';
175     }
176     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
177   }
178 
179   // Tell users about the kernel if there is one.
180   if (Triple.isOSDarwin())
181     Builder.defineMacro("__MACH__");
182 
183   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
184 }
185 
186 namespace {
187 template<typename Target>
188 class DarwinTargetInfo : public OSTargetInfo<Target> {
189 protected:
190   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
191                     MacroBuilder &Builder) const override {
192     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
193                      this->PlatformMinVersion);
194   }
195 
196 public:
197   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
198     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
199     this->MCountName = "\01mcount";
200   }
201 
202   std::string isValidSectionSpecifier(StringRef SR) const override {
203     // Let MCSectionMachO validate this.
204     StringRef Segment, Section;
205     unsigned TAA, StubSize;
206     bool HasTAA;
207     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
208                                                        TAA, HasTAA, StubSize);
209   }
210 
211   const char *getStaticInitSectionSpecifier() const override {
212     // FIXME: We should return 0 when building kexts.
213     return "__TEXT,__StaticInit,regular,pure_instructions";
214   }
215 
216   /// Darwin does not support protected visibility.  Darwin's "default"
217   /// is very similar to ELF's "protected";  Darwin requires a "weak"
218   /// attribute on declarations that can be dynamically replaced.
219   bool hasProtectedVisibility() const override {
220     return false;
221   }
222 };
223 
224 
225 // DragonFlyBSD Target
226 template<typename Target>
227 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
228 protected:
229   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
230                     MacroBuilder &Builder) const override {
231     // DragonFly defines; list based off of gcc output
232     Builder.defineMacro("__DragonFly__");
233     Builder.defineMacro("__DragonFly_cc_version", "100001");
234     Builder.defineMacro("__ELF__");
235     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
236     Builder.defineMacro("__tune_i386__");
237     DefineStd(Builder, "unix", Opts);
238   }
239 public:
240   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
241       : OSTargetInfo<Target>(Triple) {
242     this->UserLabelPrefix = "";
243 
244     switch (Triple.getArch()) {
245     default:
246     case llvm::Triple::x86:
247     case llvm::Triple::x86_64:
248       this->MCountName = ".mcount";
249       break;
250     }
251   }
252 };
253 
254 // FreeBSD Target
255 template<typename Target>
256 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
257 protected:
258   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
259                     MacroBuilder &Builder) const override {
260     // FreeBSD defines; list based off of gcc output
261 
262     unsigned Release = Triple.getOSMajorVersion();
263     if (Release == 0U)
264       Release = 8;
265 
266     Builder.defineMacro("__FreeBSD__", Twine(Release));
267     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
268     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
269     DefineStd(Builder, "unix", Opts);
270     Builder.defineMacro("__ELF__");
271 
272     // On FreeBSD, wchar_t contains the number of the code point as
273     // used by the character set of the locale. These character sets are
274     // not necessarily a superset of ASCII.
275     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
276   }
277 public:
278   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
279     this->UserLabelPrefix = "";
280 
281     switch (Triple.getArch()) {
282     default:
283     case llvm::Triple::x86:
284     case llvm::Triple::x86_64:
285       this->MCountName = ".mcount";
286       break;
287     case llvm::Triple::mips:
288     case llvm::Triple::mipsel:
289     case llvm::Triple::ppc:
290     case llvm::Triple::ppc64:
291     case llvm::Triple::ppc64le:
292       this->MCountName = "_mcount";
293       break;
294     case llvm::Triple::arm:
295       this->MCountName = "__mcount";
296       break;
297     }
298   }
299 };
300 
301 // GNU/kFreeBSD Target
302 template<typename Target>
303 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
304 protected:
305   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
306                     MacroBuilder &Builder) const override {
307     // GNU/kFreeBSD defines; list based off of gcc output
308 
309     DefineStd(Builder, "unix", Opts);
310     Builder.defineMacro("__FreeBSD_kernel__");
311     Builder.defineMacro("__GLIBC__");
312     Builder.defineMacro("__ELF__");
313     if (Opts.POSIXThreads)
314       Builder.defineMacro("_REENTRANT");
315     if (Opts.CPlusPlus)
316       Builder.defineMacro("_GNU_SOURCE");
317   }
318 public:
319   KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
320     this->UserLabelPrefix = "";
321   }
322 };
323 
324 // Minix Target
325 template<typename Target>
326 class MinixTargetInfo : public OSTargetInfo<Target> {
327 protected:
328   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
329                     MacroBuilder &Builder) const override {
330     // Minix defines
331 
332     Builder.defineMacro("__minix", "3");
333     Builder.defineMacro("_EM_WSIZE", "4");
334     Builder.defineMacro("_EM_PSIZE", "4");
335     Builder.defineMacro("_EM_SSIZE", "2");
336     Builder.defineMacro("_EM_LSIZE", "4");
337     Builder.defineMacro("_EM_FSIZE", "4");
338     Builder.defineMacro("_EM_DSIZE", "8");
339     Builder.defineMacro("__ELF__");
340     DefineStd(Builder, "unix", Opts);
341   }
342 public:
343   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
344     this->UserLabelPrefix = "";
345   }
346 };
347 
348 // Linux target
349 template<typename Target>
350 class LinuxTargetInfo : public OSTargetInfo<Target> {
351 protected:
352   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
353                     MacroBuilder &Builder) const override {
354     // Linux defines; list based off of gcc output
355     DefineStd(Builder, "unix", Opts);
356     DefineStd(Builder, "linux", Opts);
357     Builder.defineMacro("__gnu_linux__");
358     Builder.defineMacro("__ELF__");
359     if (Triple.getEnvironment() == llvm::Triple::Android)
360       Builder.defineMacro("__ANDROID__", "1");
361     if (Opts.POSIXThreads)
362       Builder.defineMacro("_REENTRANT");
363     if (Opts.CPlusPlus)
364       Builder.defineMacro("_GNU_SOURCE");
365   }
366 public:
367   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
368     this->UserLabelPrefix = "";
369     this->WIntType = TargetInfo::UnsignedInt;
370 
371     switch (Triple.getArch()) {
372     default:
373       break;
374     case llvm::Triple::ppc:
375     case llvm::Triple::ppc64:
376     case llvm::Triple::ppc64le:
377       this->MCountName = "_mcount";
378       break;
379     }
380   }
381 
382   const char *getStaticInitSectionSpecifier() const override {
383     return ".text.startup";
384   }
385 };
386 
387 // NetBSD Target
388 template<typename Target>
389 class NetBSDTargetInfo : public OSTargetInfo<Target> {
390 protected:
391   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
392                     MacroBuilder &Builder) const override {
393     // NetBSD defines; list based off of gcc output
394     Builder.defineMacro("__NetBSD__");
395     Builder.defineMacro("__unix__");
396     Builder.defineMacro("__ELF__");
397     if (Opts.POSIXThreads)
398       Builder.defineMacro("_POSIX_THREADS");
399 
400     switch (Triple.getArch()) {
401     default:
402       break;
403     case llvm::Triple::arm:
404     case llvm::Triple::armeb:
405     case llvm::Triple::thumb:
406     case llvm::Triple::thumbeb:
407       Builder.defineMacro("__ARM_DWARF_EH__");
408       break;
409     }
410   }
411 public:
412   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
413     this->UserLabelPrefix = "";
414   }
415 };
416 
417 // OpenBSD Target
418 template<typename Target>
419 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
420 protected:
421   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
422                     MacroBuilder &Builder) const override {
423     // OpenBSD defines; list based off of gcc output
424 
425     Builder.defineMacro("__OpenBSD__");
426     DefineStd(Builder, "unix", Opts);
427     Builder.defineMacro("__ELF__");
428     if (Opts.POSIXThreads)
429       Builder.defineMacro("_REENTRANT");
430   }
431 public:
432   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
433     this->UserLabelPrefix = "";
434     this->TLSSupported = false;
435 
436       switch (Triple.getArch()) {
437         default:
438         case llvm::Triple::x86:
439         case llvm::Triple::x86_64:
440         case llvm::Triple::arm:
441         case llvm::Triple::sparc:
442           this->MCountName = "__mcount";
443           break;
444         case llvm::Triple::mips64:
445         case llvm::Triple::mips64el:
446         case llvm::Triple::ppc:
447         case llvm::Triple::sparcv9:
448           this->MCountName = "_mcount";
449           break;
450       }
451   }
452 };
453 
454 // Bitrig Target
455 template<typename Target>
456 class BitrigTargetInfo : public OSTargetInfo<Target> {
457 protected:
458   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
459                     MacroBuilder &Builder) const override {
460     // Bitrig defines; list based off of gcc output
461 
462     Builder.defineMacro("__Bitrig__");
463     DefineStd(Builder, "unix", Opts);
464     Builder.defineMacro("__ELF__");
465     if (Opts.POSIXThreads)
466       Builder.defineMacro("_REENTRANT");
467   }
468 public:
469   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
470     this->UserLabelPrefix = "";
471     this->MCountName = "__mcount";
472   }
473 };
474 
475 // PSP Target
476 template<typename Target>
477 class PSPTargetInfo : public OSTargetInfo<Target> {
478 protected:
479   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
480                     MacroBuilder &Builder) const override {
481     // PSP defines; list based on the output of the pspdev gcc toolchain.
482     Builder.defineMacro("PSP");
483     Builder.defineMacro("_PSP");
484     Builder.defineMacro("__psp__");
485     Builder.defineMacro("__ELF__");
486   }
487 public:
488   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
489     this->UserLabelPrefix = "";
490   }
491 };
492 
493 // PS3 PPU Target
494 template<typename Target>
495 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
496 protected:
497   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
498                     MacroBuilder &Builder) const override {
499     // PS3 PPU defines.
500     Builder.defineMacro("__PPC__");
501     Builder.defineMacro("__PPU__");
502     Builder.defineMacro("__CELLOS_LV2__");
503     Builder.defineMacro("__ELF__");
504     Builder.defineMacro("__LP32__");
505     Builder.defineMacro("_ARCH_PPC64");
506     Builder.defineMacro("__powerpc64__");
507   }
508 public:
509   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
510     this->UserLabelPrefix = "";
511     this->LongWidth = this->LongAlign = 32;
512     this->PointerWidth = this->PointerAlign = 32;
513     this->IntMaxType = TargetInfo::SignedLongLong;
514     this->Int64Type = TargetInfo::SignedLongLong;
515     this->SizeType = TargetInfo::UnsignedInt;
516     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
517   }
518 };
519 
520 // Solaris target
521 template<typename Target>
522 class SolarisTargetInfo : public OSTargetInfo<Target> {
523 protected:
524   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
525                     MacroBuilder &Builder) const override {
526     DefineStd(Builder, "sun", Opts);
527     DefineStd(Builder, "unix", Opts);
528     Builder.defineMacro("__ELF__");
529     Builder.defineMacro("__svr4__");
530     Builder.defineMacro("__SVR4");
531     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
532     // newer, but to 500 for everything else.  feature_test.h has a check to
533     // ensure that you are not using C99 with an old version of X/Open or C89
534     // with a new version.
535     if (Opts.C99 || Opts.C11)
536       Builder.defineMacro("_XOPEN_SOURCE", "600");
537     else
538       Builder.defineMacro("_XOPEN_SOURCE", "500");
539     if (Opts.CPlusPlus)
540       Builder.defineMacro("__C99FEATURES__");
541     Builder.defineMacro("_LARGEFILE_SOURCE");
542     Builder.defineMacro("_LARGEFILE64_SOURCE");
543     Builder.defineMacro("__EXTENSIONS__");
544     Builder.defineMacro("_REENTRANT");
545   }
546 public:
547   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
548     this->UserLabelPrefix = "";
549     this->WCharType = this->SignedInt;
550     // FIXME: WIntType should be SignedLong
551   }
552 };
553 
554 // Windows target
555 template<typename Target>
556 class WindowsTargetInfo : public OSTargetInfo<Target> {
557 protected:
558   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
559                     MacroBuilder &Builder) const override {
560     Builder.defineMacro("_WIN32");
561   }
562   void getVisualStudioDefines(const LangOptions &Opts,
563                               MacroBuilder &Builder) const {
564     if (Opts.CPlusPlus) {
565       if (Opts.RTTIData)
566         Builder.defineMacro("_CPPRTTI");
567 
568       if (Opts.Exceptions)
569         Builder.defineMacro("_CPPUNWIND");
570     }
571 
572     if (!Opts.CharIsSigned)
573       Builder.defineMacro("_CHAR_UNSIGNED");
574 
575     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
576     //        but it works for now.
577     if (Opts.POSIXThreads)
578       Builder.defineMacro("_MT");
579 
580     if (Opts.MSCompatibilityVersion) {
581       Builder.defineMacro("_MSC_VER",
582                           Twine(Opts.MSCompatibilityVersion / 100000));
583       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
584       // FIXME We cannot encode the revision information into 32-bits
585       Builder.defineMacro("_MSC_BUILD", Twine(1));
586     }
587 
588     if (Opts.MicrosoftExt) {
589       Builder.defineMacro("_MSC_EXTENSIONS");
590 
591       if (Opts.CPlusPlus11) {
592         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
593         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
594         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
595       }
596     }
597 
598     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
599   }
600 
601 public:
602   WindowsTargetInfo(const llvm::Triple &Triple)
603       : OSTargetInfo<Target>(Triple) {}
604 };
605 
606 template <typename Target>
607 class NaClTargetInfo : public OSTargetInfo<Target> {
608 protected:
609   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
610                     MacroBuilder &Builder) const override {
611     if (Opts.POSIXThreads)
612       Builder.defineMacro("_REENTRANT");
613     if (Opts.CPlusPlus)
614       Builder.defineMacro("_GNU_SOURCE");
615 
616     DefineStd(Builder, "unix", Opts);
617     Builder.defineMacro("__ELF__");
618     Builder.defineMacro("__native_client__");
619   }
620 
621 public:
622   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
623     this->UserLabelPrefix = "";
624     this->LongAlign = 32;
625     this->LongWidth = 32;
626     this->PointerAlign = 32;
627     this->PointerWidth = 32;
628     this->IntMaxType = TargetInfo::SignedLongLong;
629     this->Int64Type = TargetInfo::SignedLongLong;
630     this->DoubleAlign = 64;
631     this->LongDoubleWidth = 64;
632     this->LongDoubleAlign = 64;
633     this->LongLongWidth = 64;
634     this->LongLongAlign = 64;
635     this->SizeType = TargetInfo::UnsignedInt;
636     this->PtrDiffType = TargetInfo::SignedInt;
637     this->IntPtrType = TargetInfo::SignedInt;
638     // RegParmMax is inherited from the underlying architecture
639     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
640     if (Triple.getArch() == llvm::Triple::arm) {
641       this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128";
642     } else if (Triple.getArch() == llvm::Triple::x86) {
643       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
644     } else if (Triple.getArch() == llvm::Triple::x86_64) {
645       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
646     } else if (Triple.getArch() == llvm::Triple::mipsel) {
647       // Handled on mips' setDescriptionString.
648     } else {
649       assert(Triple.getArch() == llvm::Triple::le32);
650       this->DescriptionString = "e-p:32:32-i64:64";
651     }
652   }
653   typename Target::CallingConvCheckResult checkCallingConvention(
654       CallingConv CC) const override {
655     return CC == CC_PnaclCall ? Target::CCCR_OK :
656         Target::checkCallingConvention(CC);
657   }
658 };
659 } // end anonymous namespace.
660 
661 //===----------------------------------------------------------------------===//
662 // Specific target implementations.
663 //===----------------------------------------------------------------------===//
664 
665 namespace {
666 // PPC abstract base class
667 class PPCTargetInfo : public TargetInfo {
668   static const Builtin::Info BuiltinInfo[];
669   static const char * const GCCRegNames[];
670   static const TargetInfo::GCCRegAlias GCCRegAliases[];
671   std::string CPU;
672 
673   // Target cpu features.
674   bool HasVSX;
675 
676 protected:
677   std::string ABI;
678 
679 public:
680   PPCTargetInfo(const llvm::Triple &Triple)
681       : TargetInfo(Triple), HasVSX(false) {
682     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
683     LongDoubleWidth = LongDoubleAlign = 128;
684     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
685   }
686 
687   /// \brief Flags for architecture specific defines.
688   typedef enum {
689     ArchDefineNone  = 0,
690     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
691     ArchDefinePpcgr = 1 << 1,
692     ArchDefinePpcsq = 1 << 2,
693     ArchDefine440   = 1 << 3,
694     ArchDefine603   = 1 << 4,
695     ArchDefine604   = 1 << 5,
696     ArchDefinePwr4  = 1 << 6,
697     ArchDefinePwr5  = 1 << 7,
698     ArchDefinePwr5x = 1 << 8,
699     ArchDefinePwr6  = 1 << 9,
700     ArchDefinePwr6x = 1 << 10,
701     ArchDefinePwr7  = 1 << 11,
702     ArchDefinePwr8  = 1 << 12,
703     ArchDefineA2    = 1 << 13,
704     ArchDefineA2q   = 1 << 14
705   } ArchDefineTypes;
706 
707   // Note: GCC recognizes the following additional cpus:
708   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
709   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
710   //  titan, rs64.
711   bool setCPU(const std::string &Name) override {
712     bool CPUKnown = llvm::StringSwitch<bool>(Name)
713       .Case("generic", true)
714       .Case("440", true)
715       .Case("450", true)
716       .Case("601", true)
717       .Case("602", true)
718       .Case("603", true)
719       .Case("603e", true)
720       .Case("603ev", true)
721       .Case("604", true)
722       .Case("604e", true)
723       .Case("620", true)
724       .Case("630", true)
725       .Case("g3", true)
726       .Case("7400", true)
727       .Case("g4", true)
728       .Case("7450", true)
729       .Case("g4+", true)
730       .Case("750", true)
731       .Case("970", true)
732       .Case("g5", true)
733       .Case("a2", true)
734       .Case("a2q", true)
735       .Case("e500mc", true)
736       .Case("e5500", true)
737       .Case("power3", true)
738       .Case("pwr3", true)
739       .Case("power4", true)
740       .Case("pwr4", true)
741       .Case("power5", true)
742       .Case("pwr5", true)
743       .Case("power5x", true)
744       .Case("pwr5x", true)
745       .Case("power6", true)
746       .Case("pwr6", true)
747       .Case("power6x", true)
748       .Case("pwr6x", true)
749       .Case("power7", true)
750       .Case("pwr7", true)
751       .Case("power8", true)
752       .Case("pwr8", true)
753       .Case("powerpc", true)
754       .Case("ppc", true)
755       .Case("powerpc64", true)
756       .Case("ppc64", true)
757       .Case("powerpc64le", true)
758       .Case("ppc64le", true)
759       .Default(false);
760 
761     if (CPUKnown)
762       CPU = Name;
763 
764     return CPUKnown;
765   }
766 
767 
768   StringRef getABI() const override { return ABI; }
769 
770   void getTargetBuiltins(const Builtin::Info *&Records,
771                          unsigned &NumRecords) const override {
772     Records = BuiltinInfo;
773     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
774   }
775 
776   bool isCLZForZeroUndef() const override { return false; }
777 
778   void getTargetDefines(const LangOptions &Opts,
779                         MacroBuilder &Builder) const override;
780 
781   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
782 
783   bool handleTargetFeatures(std::vector<std::string> &Features,
784                             DiagnosticsEngine &Diags) override;
785   bool hasFeature(StringRef Feature) const override;
786 
787   void getGCCRegNames(const char * const *&Names,
788                       unsigned &NumNames) const override;
789   void getGCCRegAliases(const GCCRegAlias *&Aliases,
790                         unsigned &NumAliases) const override;
791   bool validateAsmConstraint(const char *&Name,
792                              TargetInfo::ConstraintInfo &Info) const override {
793     switch (*Name) {
794     default: return false;
795     case 'O': // Zero
796       break;
797     case 'b': // Base register
798     case 'f': // Floating point register
799       Info.setAllowsRegister();
800       break;
801     // FIXME: The following are added to allow parsing.
802     // I just took a guess at what the actions should be.
803     // Also, is more specific checking needed?  I.e. specific registers?
804     case 'd': // Floating point register (containing 64-bit value)
805     case 'v': // Altivec vector register
806       Info.setAllowsRegister();
807       break;
808     case 'w':
809       switch (Name[1]) {
810         case 'd':// VSX vector register to hold vector double data
811         case 'f':// VSX vector register to hold vector float data
812         case 's':// VSX vector register to hold scalar float data
813         case 'a':// Any VSX register
814         case 'c':// An individual CR bit
815           break;
816         default:
817           return false;
818       }
819       Info.setAllowsRegister();
820       Name++; // Skip over 'w'.
821       break;
822     case 'h': // `MQ', `CTR', or `LINK' register
823     case 'q': // `MQ' register
824     case 'c': // `CTR' register
825     case 'l': // `LINK' register
826     case 'x': // `CR' register (condition register) number 0
827     case 'y': // `CR' register (condition register)
828     case 'z': // `XER[CA]' carry bit (part of the XER register)
829       Info.setAllowsRegister();
830       break;
831     case 'I': // Signed 16-bit constant
832     case 'J': // Unsigned 16-bit constant shifted left 16 bits
833               //  (use `L' instead for SImode constants)
834     case 'K': // Unsigned 16-bit constant
835     case 'L': // Signed 16-bit constant shifted left 16 bits
836     case 'M': // Constant larger than 31
837     case 'N': // Exact power of 2
838     case 'P': // Constant whose negation is a signed 16-bit constant
839     case 'G': // Floating point constant that can be loaded into a
840               // register with one instruction per word
841     case 'H': // Integer/Floating point constant that can be loaded
842               // into a register using three instructions
843       break;
844     case 'm': // Memory operand. Note that on PowerPC targets, m can
845               // include addresses that update the base register. It
846               // is therefore only safe to use `m' in an asm statement
847               // if that asm statement accesses the operand exactly once.
848               // The asm statement must also use `%U<opno>' as a
849               // placeholder for the "update" flag in the corresponding
850               // load or store instruction. For example:
851               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
852               // is correct but:
853               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
854               // is not. Use es rather than m if you don't want the base
855               // register to be updated.
856     case 'e':
857       if (Name[1] != 's')
858           return false;
859               // es: A "stable" memory operand; that is, one which does not
860               // include any automodification of the base register. Unlike
861               // `m', this constraint can be used in asm statements that
862               // might access the operand several times, or that might not
863               // access it at all.
864       Info.setAllowsMemory();
865       Name++; // Skip over 'e'.
866       break;
867     case 'Q': // Memory operand that is an offset from a register (it is
868               // usually better to use `m' or `es' in asm statements)
869     case 'Z': // Memory operand that is an indexed or indirect from a
870               // register (it is usually better to use `m' or `es' in
871               // asm statements)
872       Info.setAllowsMemory();
873       Info.setAllowsRegister();
874       break;
875     case 'R': // AIX TOC entry
876     case 'a': // Address operand that is an indexed or indirect from a
877               // register (`p' is preferable for asm statements)
878     case 'S': // Constant suitable as a 64-bit mask operand
879     case 'T': // Constant suitable as a 32-bit mask operand
880     case 'U': // System V Release 4 small data area reference
881     case 't': // AND masks that can be performed by two rldic{l, r}
882               // instructions
883     case 'W': // Vector constant that does not require memory
884     case 'j': // Vector constant that is all zeros.
885       break;
886     // End FIXME.
887     }
888     return true;
889   }
890   std::string convertConstraint(const char *&Constraint) const override {
891     std::string R;
892     switch (*Constraint) {
893     case 'e':
894     case 'w':
895       // Two-character constraint; add "^" hint for later parsing.
896       R = std::string("^") + std::string(Constraint, 2);
897       Constraint++;
898       break;
899     default:
900       return TargetInfo::convertConstraint(Constraint);
901     }
902     return R;
903   }
904   const char *getClobbers() const override {
905     return "";
906   }
907   int getEHDataRegisterNumber(unsigned RegNo) const override {
908     if (RegNo == 0) return 3;
909     if (RegNo == 1) return 4;
910     return -1;
911   }
912 };
913 
914 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
915 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
916 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
917                                               ALL_LANGUAGES },
918 #include "clang/Basic/BuiltinsPPC.def"
919 };
920 
921   /// handleTargetFeatures - Perform initialization based on the user
922 /// configured set of features.
923 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
924                                          DiagnosticsEngine &Diags) {
925   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
926     // Ignore disabled features.
927     if (Features[i][0] == '-')
928       continue;
929 
930     StringRef Feature = StringRef(Features[i]).substr(1);
931 
932     if (Feature == "vsx") {
933       HasVSX = true;
934       continue;
935     }
936 
937     // TODO: Finish this list and add an assert that we've handled them
938     // all.
939   }
940 
941   return true;
942 }
943 
944 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
945 /// #defines that are not tied to a specific subtarget.
946 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
947                                      MacroBuilder &Builder) const {
948   // Target identification.
949   Builder.defineMacro("__ppc__");
950   Builder.defineMacro("__PPC__");
951   Builder.defineMacro("_ARCH_PPC");
952   Builder.defineMacro("__powerpc__");
953   Builder.defineMacro("__POWERPC__");
954   if (PointerWidth == 64) {
955     Builder.defineMacro("_ARCH_PPC64");
956     Builder.defineMacro("__powerpc64__");
957     Builder.defineMacro("__ppc64__");
958     Builder.defineMacro("__PPC64__");
959   }
960 
961   // Target properties.
962   if (getTriple().getArch() == llvm::Triple::ppc64le) {
963     Builder.defineMacro("_LITTLE_ENDIAN");
964   } else {
965     if (getTriple().getOS() != llvm::Triple::NetBSD &&
966         getTriple().getOS() != llvm::Triple::OpenBSD)
967       Builder.defineMacro("_BIG_ENDIAN");
968   }
969 
970   // ABI options.
971   if (ABI == "elfv1")
972     Builder.defineMacro("_CALL_ELF", "1");
973   if (ABI == "elfv2")
974     Builder.defineMacro("_CALL_ELF", "2");
975 
976   // Subtarget options.
977   Builder.defineMacro("__NATURAL_ALIGNMENT__");
978   Builder.defineMacro("__REGISTER_PREFIX__", "");
979 
980   // FIXME: Should be controlled by command line option.
981   if (LongDoubleWidth == 128)
982     Builder.defineMacro("__LONG_DOUBLE_128__");
983 
984   if (Opts.AltiVec) {
985     Builder.defineMacro("__VEC__", "10206");
986     Builder.defineMacro("__ALTIVEC__");
987   }
988 
989   // CPU identification.
990   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
991     .Case("440",   ArchDefineName)
992     .Case("450",   ArchDefineName | ArchDefine440)
993     .Case("601",   ArchDefineName)
994     .Case("602",   ArchDefineName | ArchDefinePpcgr)
995     .Case("603",   ArchDefineName | ArchDefinePpcgr)
996     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
997     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
998     .Case("604",   ArchDefineName | ArchDefinePpcgr)
999     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
1000     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1001     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1002     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1003     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1004     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1005     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1006                      | ArchDefinePpcsq)
1007     .Case("a2",    ArchDefineA2)
1008     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1009     .Case("pwr3",  ArchDefinePpcgr)
1010     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1011     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1012                      | ArchDefinePpcsq)
1013     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1014                      | ArchDefinePpcgr | ArchDefinePpcsq)
1015     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1016                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1017     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1018                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1019                      | ArchDefinePpcsq)
1020     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1021                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1022                      | ArchDefinePpcgr | ArchDefinePpcsq)
1023     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1024                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1025                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1026     .Case("power3",  ArchDefinePpcgr)
1027     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1028     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1029                        | ArchDefinePpcsq)
1030     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1031                        | ArchDefinePpcgr | ArchDefinePpcsq)
1032     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1033                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1034     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1035                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1036                        | ArchDefinePpcsq)
1037     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1038                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1039                        | ArchDefinePpcgr | ArchDefinePpcsq)
1040     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1041                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1042                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1043     .Default(ArchDefineNone);
1044 
1045   if (defs & ArchDefineName)
1046     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1047   if (defs & ArchDefinePpcgr)
1048     Builder.defineMacro("_ARCH_PPCGR");
1049   if (defs & ArchDefinePpcsq)
1050     Builder.defineMacro("_ARCH_PPCSQ");
1051   if (defs & ArchDefine440)
1052     Builder.defineMacro("_ARCH_440");
1053   if (defs & ArchDefine603)
1054     Builder.defineMacro("_ARCH_603");
1055   if (defs & ArchDefine604)
1056     Builder.defineMacro("_ARCH_604");
1057   if (defs & ArchDefinePwr4)
1058     Builder.defineMacro("_ARCH_PWR4");
1059   if (defs & ArchDefinePwr5)
1060     Builder.defineMacro("_ARCH_PWR5");
1061   if (defs & ArchDefinePwr5x)
1062     Builder.defineMacro("_ARCH_PWR5X");
1063   if (defs & ArchDefinePwr6)
1064     Builder.defineMacro("_ARCH_PWR6");
1065   if (defs & ArchDefinePwr6x)
1066     Builder.defineMacro("_ARCH_PWR6X");
1067   if (defs & ArchDefinePwr7)
1068     Builder.defineMacro("_ARCH_PWR7");
1069   if (defs & ArchDefinePwr8)
1070     Builder.defineMacro("_ARCH_PWR8");
1071   if (defs & ArchDefineA2)
1072     Builder.defineMacro("_ARCH_A2");
1073   if (defs & ArchDefineA2q) {
1074     Builder.defineMacro("_ARCH_A2Q");
1075     Builder.defineMacro("_ARCH_QP");
1076   }
1077 
1078   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1079     Builder.defineMacro("__bg__");
1080     Builder.defineMacro("__THW_BLUEGENE__");
1081     Builder.defineMacro("__bgq__");
1082     Builder.defineMacro("__TOS_BGQ__");
1083   }
1084 
1085   if (HasVSX)
1086     Builder.defineMacro("__VSX__");
1087 
1088   // FIXME: The following are not yet generated here by Clang, but are
1089   //        generated by GCC:
1090   //
1091   //   _SOFT_FLOAT_
1092   //   __RECIP_PRECISION__
1093   //   __APPLE_ALTIVEC__
1094   //   __RECIP__
1095   //   __RECIPF__
1096   //   __RSQRTE__
1097   //   __RSQRTEF__
1098   //   _SOFT_DOUBLE_
1099   //   __NO_LWSYNC__
1100   //   __HAVE_BSWAP__
1101   //   __LONGDOUBLE128
1102   //   __CMODEL_MEDIUM__
1103   //   __CMODEL_LARGE__
1104   //   _CALL_SYSV
1105   //   _CALL_DARWIN
1106   //   __NO_FPRS__
1107 }
1108 
1109 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1110   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1111     .Case("7400", true)
1112     .Case("g4", true)
1113     .Case("7450", true)
1114     .Case("g4+", true)
1115     .Case("970", true)
1116     .Case("g5", true)
1117     .Case("pwr6", true)
1118     .Case("pwr7", true)
1119     .Case("pwr8", true)
1120     .Case("ppc64", true)
1121     .Case("ppc64le", true)
1122     .Default(false);
1123 
1124   Features["qpx"] = (CPU == "a2q");
1125 
1126   if (!ABI.empty())
1127     Features[ABI] = true;
1128 }
1129 
1130 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1131   return Feature == "powerpc";
1132 }
1133 
1134 
1135 const char * const PPCTargetInfo::GCCRegNames[] = {
1136   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1137   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1138   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1139   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1140   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1141   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1142   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1143   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1144   "mq", "lr", "ctr", "ap",
1145   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1146   "xer",
1147   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1148   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1149   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1150   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1151   "vrsave", "vscr",
1152   "spe_acc", "spefscr",
1153   "sfp"
1154 };
1155 
1156 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1157                                    unsigned &NumNames) const {
1158   Names = GCCRegNames;
1159   NumNames = llvm::array_lengthof(GCCRegNames);
1160 }
1161 
1162 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1163   // While some of these aliases do map to different registers
1164   // they still share the same register name.
1165   { { "0" }, "r0" },
1166   { { "1"}, "r1" },
1167   { { "2" }, "r2" },
1168   { { "3" }, "r3" },
1169   { { "4" }, "r4" },
1170   { { "5" }, "r5" },
1171   { { "6" }, "r6" },
1172   { { "7" }, "r7" },
1173   { { "8" }, "r8" },
1174   { { "9" }, "r9" },
1175   { { "10" }, "r10" },
1176   { { "11" }, "r11" },
1177   { { "12" }, "r12" },
1178   { { "13" }, "r13" },
1179   { { "14" }, "r14" },
1180   { { "15" }, "r15" },
1181   { { "16" }, "r16" },
1182   { { "17" }, "r17" },
1183   { { "18" }, "r18" },
1184   { { "19" }, "r19" },
1185   { { "20" }, "r20" },
1186   { { "21" }, "r21" },
1187   { { "22" }, "r22" },
1188   { { "23" }, "r23" },
1189   { { "24" }, "r24" },
1190   { { "25" }, "r25" },
1191   { { "26" }, "r26" },
1192   { { "27" }, "r27" },
1193   { { "28" }, "r28" },
1194   { { "29" }, "r29" },
1195   { { "30" }, "r30" },
1196   { { "31" }, "r31" },
1197   { { "fr0" }, "f0" },
1198   { { "fr1" }, "f1" },
1199   { { "fr2" }, "f2" },
1200   { { "fr3" }, "f3" },
1201   { { "fr4" }, "f4" },
1202   { { "fr5" }, "f5" },
1203   { { "fr6" }, "f6" },
1204   { { "fr7" }, "f7" },
1205   { { "fr8" }, "f8" },
1206   { { "fr9" }, "f9" },
1207   { { "fr10" }, "f10" },
1208   { { "fr11" }, "f11" },
1209   { { "fr12" }, "f12" },
1210   { { "fr13" }, "f13" },
1211   { { "fr14" }, "f14" },
1212   { { "fr15" }, "f15" },
1213   { { "fr16" }, "f16" },
1214   { { "fr17" }, "f17" },
1215   { { "fr18" }, "f18" },
1216   { { "fr19" }, "f19" },
1217   { { "fr20" }, "f20" },
1218   { { "fr21" }, "f21" },
1219   { { "fr22" }, "f22" },
1220   { { "fr23" }, "f23" },
1221   { { "fr24" }, "f24" },
1222   { { "fr25" }, "f25" },
1223   { { "fr26" }, "f26" },
1224   { { "fr27" }, "f27" },
1225   { { "fr28" }, "f28" },
1226   { { "fr29" }, "f29" },
1227   { { "fr30" }, "f30" },
1228   { { "fr31" }, "f31" },
1229   { { "cc" }, "cr0" },
1230 };
1231 
1232 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1233                                      unsigned &NumAliases) const {
1234   Aliases = GCCRegAliases;
1235   NumAliases = llvm::array_lengthof(GCCRegAliases);
1236 }
1237 } // end anonymous namespace.
1238 
1239 namespace {
1240 class PPC32TargetInfo : public PPCTargetInfo {
1241 public:
1242   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1243     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1244 
1245     switch (getTriple().getOS()) {
1246     case llvm::Triple::Linux:
1247     case llvm::Triple::FreeBSD:
1248     case llvm::Triple::NetBSD:
1249       SizeType = UnsignedInt;
1250       PtrDiffType = SignedInt;
1251       IntPtrType = SignedInt;
1252       break;
1253     default:
1254       break;
1255     }
1256 
1257     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1258       LongDoubleWidth = LongDoubleAlign = 64;
1259       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1260     }
1261 
1262     // PPC32 supports atomics up to 4 bytes.
1263     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1264   }
1265 
1266   BuiltinVaListKind getBuiltinVaListKind() const override {
1267     // This is the ELF definition, and is overridden by the Darwin sub-target
1268     return TargetInfo::PowerABIBuiltinVaList;
1269   }
1270 };
1271 } // end anonymous namespace.
1272 
1273 // Note: ABI differences may eventually require us to have a separate
1274 // TargetInfo for little endian.
1275 namespace {
1276 class PPC64TargetInfo : public PPCTargetInfo {
1277 public:
1278   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1279     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1280     IntMaxType = SignedLong;
1281     Int64Type = SignedLong;
1282 
1283     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1284       LongDoubleWidth = LongDoubleAlign = 64;
1285       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1286       DescriptionString = "E-m:e-i64:64-n32:64";
1287     } else {
1288       if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1289         DescriptionString = "e-m:e-i64:64-n32:64";
1290         ABI = "elfv2";
1291       } else {
1292         DescriptionString = "E-m:e-i64:64-n32:64";
1293         ABI = "elfv1";
1294       }
1295     }
1296 
1297     // PPC64 supports atomics up to 8 bytes.
1298     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1299   }
1300   BuiltinVaListKind getBuiltinVaListKind() const override {
1301     return TargetInfo::CharPtrBuiltinVaList;
1302   }
1303   // PPC64 Linux-specifc ABI options.
1304   bool setABI(const std::string &Name) override {
1305     if (Name == "elfv1" || Name == "elfv2") {
1306       ABI = Name;
1307       return true;
1308     }
1309     return false;
1310   }
1311 };
1312 } // end anonymous namespace.
1313 
1314 
1315 namespace {
1316 class DarwinPPC32TargetInfo :
1317   public DarwinTargetInfo<PPC32TargetInfo> {
1318 public:
1319   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1320       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1321     HasAlignMac68kSupport = true;
1322     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1323     PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1324     LongLongAlign = 32;
1325     SuitableAlign = 128;
1326     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1327   }
1328   BuiltinVaListKind getBuiltinVaListKind() const override {
1329     return TargetInfo::CharPtrBuiltinVaList;
1330   }
1331 };
1332 
1333 class DarwinPPC64TargetInfo :
1334   public DarwinTargetInfo<PPC64TargetInfo> {
1335 public:
1336   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1337       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1338     HasAlignMac68kSupport = true;
1339     SuitableAlign = 128;
1340     DescriptionString = "E-m:o-i64:64-n32:64";
1341   }
1342 };
1343 } // end anonymous namespace.
1344 
1345 namespace {
1346   static const unsigned NVPTXAddrSpaceMap[] = {
1347     1,    // opencl_global
1348     3,    // opencl_local
1349     4,    // opencl_constant
1350     1,    // cuda_device
1351     4,    // cuda_constant
1352     3,    // cuda_shared
1353   };
1354   class NVPTXTargetInfo : public TargetInfo {
1355     static const char * const GCCRegNames[];
1356     static const Builtin::Info BuiltinInfo[];
1357   public:
1358     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1359       BigEndian = false;
1360       TLSSupported = false;
1361       LongWidth = LongAlign = 64;
1362       AddrSpaceMap = &NVPTXAddrSpaceMap;
1363       UseAddrSpaceMapMangling = true;
1364       // Define available target features
1365       // These must be defined in sorted order!
1366       NoAsmVariants = true;
1367     }
1368     void getTargetDefines(const LangOptions &Opts,
1369                           MacroBuilder &Builder) const override {
1370       Builder.defineMacro("__PTX__");
1371       Builder.defineMacro("__NVPTX__");
1372     }
1373     void getTargetBuiltins(const Builtin::Info *&Records,
1374                            unsigned &NumRecords) const override {
1375       Records = BuiltinInfo;
1376       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1377     }
1378     bool hasFeature(StringRef Feature) const override {
1379       return Feature == "ptx" || Feature == "nvptx";
1380     }
1381 
1382     void getGCCRegNames(const char * const *&Names,
1383                         unsigned &NumNames) const override;
1384     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1385                                   unsigned &NumAliases) const override {
1386       // No aliases.
1387       Aliases = nullptr;
1388       NumAliases = 0;
1389     }
1390     bool validateAsmConstraint(const char *&Name,
1391                                TargetInfo::ConstraintInfo &Info) const override {
1392       switch (*Name) {
1393       default: return false;
1394       case 'c':
1395       case 'h':
1396       case 'r':
1397       case 'l':
1398       case 'f':
1399       case 'd':
1400         Info.setAllowsRegister();
1401         return true;
1402       }
1403     }
1404     const char *getClobbers() const override {
1405       // FIXME: Is this really right?
1406       return "";
1407     }
1408     BuiltinVaListKind getBuiltinVaListKind() const override {
1409       // FIXME: implement
1410       return TargetInfo::CharPtrBuiltinVaList;
1411     }
1412     bool setCPU(const std::string &Name) override {
1413       bool Valid = llvm::StringSwitch<bool>(Name)
1414         .Case("sm_20", true)
1415         .Case("sm_21", true)
1416         .Case("sm_30", true)
1417         .Case("sm_35", true)
1418         .Default(false);
1419 
1420       return Valid;
1421     }
1422   };
1423 
1424   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1425 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1426 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1427                                               ALL_LANGUAGES },
1428 #include "clang/Basic/BuiltinsNVPTX.def"
1429   };
1430 
1431   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1432     "r0"
1433   };
1434 
1435   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1436                                      unsigned &NumNames) const {
1437     Names = GCCRegNames;
1438     NumNames = llvm::array_lengthof(GCCRegNames);
1439   }
1440 
1441   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1442   public:
1443     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1444       PointerWidth = PointerAlign = 32;
1445       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1446       IntPtrType = TargetInfo::SignedInt;
1447       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1448   }
1449   };
1450 
1451   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1452   public:
1453     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1454       PointerWidth = PointerAlign = 64;
1455       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1456       IntPtrType = TargetInfo::SignedLongLong;
1457       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1458   }
1459   };
1460 }
1461 
1462 namespace {
1463 
1464 static const unsigned R600AddrSpaceMap[] = {
1465   1,    // opencl_global
1466   3,    // opencl_local
1467   2,    // opencl_constant
1468   1,    // cuda_device
1469   2,    // cuda_constant
1470   3     // cuda_shared
1471 };
1472 
1473 // If you edit the description strings, make sure you update
1474 // getPointerWidthV().
1475 
1476 static const char *DescriptionStringR600 =
1477   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1478   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1479 
1480 static const char *DescriptionStringR600DoubleOps =
1481   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1482   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1483 
1484 static const char *DescriptionStringSI =
1485   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1486   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1487   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1488 
1489 class R600TargetInfo : public TargetInfo {
1490   static const Builtin::Info BuiltinInfo[];
1491 
1492   /// \brief The GPU profiles supported by the R600 target.
1493   enum GPUKind {
1494     GK_NONE,
1495     GK_R600,
1496     GK_R600_DOUBLE_OPS,
1497     GK_R700,
1498     GK_R700_DOUBLE_OPS,
1499     GK_EVERGREEN,
1500     GK_EVERGREEN_DOUBLE_OPS,
1501     GK_NORTHERN_ISLANDS,
1502     GK_CAYMAN,
1503     GK_SOUTHERN_ISLANDS,
1504     GK_SEA_ISLANDS
1505   } GPU;
1506 
1507 public:
1508   R600TargetInfo(const llvm::Triple &Triple)
1509       : TargetInfo(Triple), GPU(GK_R600) {
1510     DescriptionString = DescriptionStringR600;
1511     AddrSpaceMap = &R600AddrSpaceMap;
1512     UseAddrSpaceMapMangling = true;
1513   }
1514 
1515   uint64_t getPointerWidthV(unsigned AddrSpace) const override {
1516     if (GPU <= GK_CAYMAN)
1517       return 32;
1518 
1519     switch(AddrSpace) {
1520       default:
1521         return 64;
1522       case 0:
1523       case 3:
1524       case 5:
1525         return 32;
1526     }
1527   }
1528 
1529   const char * getClobbers() const override {
1530     return "";
1531   }
1532 
1533   void getGCCRegNames(const char * const *&Names,
1534                       unsigned &numNames) const override {
1535     Names = nullptr;
1536     numNames = 0;
1537   }
1538 
1539   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1540                         unsigned &NumAliases) const override {
1541     Aliases = nullptr;
1542     NumAliases = 0;
1543   }
1544 
1545   bool validateAsmConstraint(const char *&Name,
1546                              TargetInfo::ConstraintInfo &info) const override {
1547     return true;
1548   }
1549 
1550   void getTargetBuiltins(const Builtin::Info *&Records,
1551                          unsigned &NumRecords) const override {
1552     Records = BuiltinInfo;
1553     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1554   }
1555 
1556   void getTargetDefines(const LangOptions &Opts,
1557                         MacroBuilder &Builder) const override {
1558     Builder.defineMacro("__R600__");
1559   }
1560 
1561   BuiltinVaListKind getBuiltinVaListKind() const override {
1562     return TargetInfo::CharPtrBuiltinVaList;
1563   }
1564 
1565   bool setCPU(const std::string &Name) override {
1566     GPU = llvm::StringSwitch<GPUKind>(Name)
1567       .Case("r600" ,    GK_R600)
1568       .Case("rv610",    GK_R600)
1569       .Case("rv620",    GK_R600)
1570       .Case("rv630",    GK_R600)
1571       .Case("rv635",    GK_R600)
1572       .Case("rs780",    GK_R600)
1573       .Case("rs880",    GK_R600)
1574       .Case("rv670",    GK_R600_DOUBLE_OPS)
1575       .Case("rv710",    GK_R700)
1576       .Case("rv730",    GK_R700)
1577       .Case("rv740",    GK_R700_DOUBLE_OPS)
1578       .Case("rv770",    GK_R700_DOUBLE_OPS)
1579       .Case("palm",     GK_EVERGREEN)
1580       .Case("cedar",    GK_EVERGREEN)
1581       .Case("sumo",     GK_EVERGREEN)
1582       .Case("sumo2",    GK_EVERGREEN)
1583       .Case("redwood",  GK_EVERGREEN)
1584       .Case("juniper",  GK_EVERGREEN)
1585       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1586       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1587       .Case("barts",    GK_NORTHERN_ISLANDS)
1588       .Case("turks",    GK_NORTHERN_ISLANDS)
1589       .Case("caicos",   GK_NORTHERN_ISLANDS)
1590       .Case("cayman",   GK_CAYMAN)
1591       .Case("aruba",    GK_CAYMAN)
1592       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1593       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1594       .Case("verde",    GK_SOUTHERN_ISLANDS)
1595       .Case("oland",    GK_SOUTHERN_ISLANDS)
1596       .Case("hainan",   GK_SOUTHERN_ISLANDS)
1597       .Case("bonaire",  GK_SEA_ISLANDS)
1598       .Case("kabini",   GK_SEA_ISLANDS)
1599       .Case("kaveri",   GK_SEA_ISLANDS)
1600       .Case("hawaii",   GK_SEA_ISLANDS)
1601       .Case("mullins",  GK_SEA_ISLANDS)
1602       .Default(GK_NONE);
1603 
1604     if (GPU == GK_NONE) {
1605       return false;
1606     }
1607 
1608     // Set the correct data layout
1609     switch (GPU) {
1610     case GK_NONE:
1611     case GK_R600:
1612     case GK_R700:
1613     case GK_EVERGREEN:
1614     case GK_NORTHERN_ISLANDS:
1615       DescriptionString = DescriptionStringR600;
1616       break;
1617     case GK_R600_DOUBLE_OPS:
1618     case GK_R700_DOUBLE_OPS:
1619     case GK_EVERGREEN_DOUBLE_OPS:
1620     case GK_CAYMAN:
1621       DescriptionString = DescriptionStringR600DoubleOps;
1622       break;
1623     case GK_SOUTHERN_ISLANDS:
1624     case GK_SEA_ISLANDS:
1625       DescriptionString = DescriptionStringSI;
1626       break;
1627     }
1628 
1629     return true;
1630   }
1631 };
1632 
1633 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1634 #define BUILTIN(ID, TYPE, ATTRS)                \
1635   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1636 #include "clang/Basic/BuiltinsR600.def"
1637 };
1638 
1639 } // end anonymous namespace
1640 
1641 namespace {
1642 // Namespace for x86 abstract base class
1643 const Builtin::Info BuiltinInfo[] = {
1644 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1645 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1646                                               ALL_LANGUAGES },
1647 #include "clang/Basic/BuiltinsX86.def"
1648 };
1649 
1650 static const char* const GCCRegNames[] = {
1651   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1652   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1653   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1654   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1655   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1656   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1657   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1658   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1659   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1660 };
1661 
1662 const TargetInfo::AddlRegName AddlRegNames[] = {
1663   { { "al", "ah", "eax", "rax" }, 0 },
1664   { { "bl", "bh", "ebx", "rbx" }, 3 },
1665   { { "cl", "ch", "ecx", "rcx" }, 2 },
1666   { { "dl", "dh", "edx", "rdx" }, 1 },
1667   { { "esi", "rsi" }, 4 },
1668   { { "edi", "rdi" }, 5 },
1669   { { "esp", "rsp" }, 7 },
1670   { { "ebp", "rbp" }, 6 },
1671 };
1672 
1673 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1674 // most of the implementation can be shared.
1675 class X86TargetInfo : public TargetInfo {
1676   enum X86SSEEnum {
1677     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1678   } SSELevel;
1679   enum MMX3DNowEnum {
1680     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1681   } MMX3DNowLevel;
1682   enum XOPEnum {
1683     NoXOP,
1684     SSE4A,
1685     FMA4,
1686     XOP
1687   } XOPLevel;
1688 
1689   bool HasAES;
1690   bool HasPCLMUL;
1691   bool HasLZCNT;
1692   bool HasRDRND;
1693   bool HasBMI;
1694   bool HasBMI2;
1695   bool HasPOPCNT;
1696   bool HasRTM;
1697   bool HasPRFCHW;
1698   bool HasRDSEED;
1699   bool HasADX;
1700   bool HasTBM;
1701   bool HasFMA;
1702   bool HasF16C;
1703   bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, HasAVX512VL;
1704   bool HasSHA;
1705   bool HasCX16;
1706 
1707   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1708   ///
1709   /// Each enumeration represents a particular CPU supported by Clang. These
1710   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1711   enum CPUKind {
1712     CK_Generic,
1713 
1714     /// \name i386
1715     /// i386-generation processors.
1716     //@{
1717     CK_i386,
1718     //@}
1719 
1720     /// \name i486
1721     /// i486-generation processors.
1722     //@{
1723     CK_i486,
1724     CK_WinChipC6,
1725     CK_WinChip2,
1726     CK_C3,
1727     //@}
1728 
1729     /// \name i586
1730     /// i586-generation processors, P5 microarchitecture based.
1731     //@{
1732     CK_i586,
1733     CK_Pentium,
1734     CK_PentiumMMX,
1735     //@}
1736 
1737     /// \name i686
1738     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1739     //@{
1740     CK_i686,
1741     CK_PentiumPro,
1742     CK_Pentium2,
1743     CK_Pentium3,
1744     CK_Pentium3M,
1745     CK_PentiumM,
1746     CK_C3_2,
1747 
1748     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1749     /// Clang however has some logic to suport this.
1750     // FIXME: Warn, deprecate, and potentially remove this.
1751     CK_Yonah,
1752     //@}
1753 
1754     /// \name Netburst
1755     /// Netburst microarchitecture based processors.
1756     //@{
1757     CK_Pentium4,
1758     CK_Pentium4M,
1759     CK_Prescott,
1760     CK_Nocona,
1761     //@}
1762 
1763     /// \name Core
1764     /// Core microarchitecture based processors.
1765     //@{
1766     CK_Core2,
1767 
1768     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1769     /// codename which GCC no longer accepts as an option to -march, but Clang
1770     /// has some logic for recognizing it.
1771     // FIXME: Warn, deprecate, and potentially remove this.
1772     CK_Penryn,
1773     //@}
1774 
1775     /// \name Atom
1776     /// Atom processors
1777     //@{
1778     CK_Atom,
1779     CK_Silvermont,
1780     //@}
1781 
1782     /// \name Nehalem
1783     /// Nehalem microarchitecture based processors.
1784     //@{
1785     CK_Corei7,
1786     CK_Corei7AVX,
1787     CK_CoreAVXi,
1788     CK_CoreAVX2,
1789     CK_Broadwell,
1790     //@}
1791 
1792     /// \name Knights Landing
1793     /// Knights Landing processor.
1794     CK_KNL,
1795 
1796     /// \name Skylake Server
1797     /// Skylake server processor.
1798     CK_SKX,
1799 
1800     /// \name K6
1801     /// K6 architecture processors.
1802     //@{
1803     CK_K6,
1804     CK_K6_2,
1805     CK_K6_3,
1806     //@}
1807 
1808     /// \name K7
1809     /// K7 architecture processors.
1810     //@{
1811     CK_Athlon,
1812     CK_AthlonThunderbird,
1813     CK_Athlon4,
1814     CK_AthlonXP,
1815     CK_AthlonMP,
1816     //@}
1817 
1818     /// \name K8
1819     /// K8 architecture processors.
1820     //@{
1821     CK_Athlon64,
1822     CK_Athlon64SSE3,
1823     CK_AthlonFX,
1824     CK_K8,
1825     CK_K8SSE3,
1826     CK_Opteron,
1827     CK_OpteronSSE3,
1828     CK_AMDFAM10,
1829     //@}
1830 
1831     /// \name Bobcat
1832     /// Bobcat architecture processors.
1833     //@{
1834     CK_BTVER1,
1835     CK_BTVER2,
1836     //@}
1837 
1838     /// \name Bulldozer
1839     /// Bulldozer architecture processors.
1840     //@{
1841     CK_BDVER1,
1842     CK_BDVER2,
1843     CK_BDVER3,
1844     CK_BDVER4,
1845     //@}
1846 
1847     /// This specification is deprecated and will be removed in the future.
1848     /// Users should prefer \see CK_K8.
1849     // FIXME: Warn on this when the CPU is set to it.
1850     CK_x86_64,
1851     //@}
1852 
1853     /// \name Geode
1854     /// Geode processors.
1855     //@{
1856     CK_Geode
1857     //@}
1858   } CPU;
1859 
1860   enum FPMathKind {
1861     FP_Default,
1862     FP_SSE,
1863     FP_387
1864   } FPMath;
1865 
1866 public:
1867   X86TargetInfo(const llvm::Triple &Triple)
1868       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1869         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1870         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1871         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasADX(false),
1872         HasTBM(false), HasFMA(false), HasF16C(false), HasAVX512CD(false),
1873         HasAVX512ER(false), HasAVX512PF(false), HasAVX512DQ(false),
1874         HasAVX512BW(false), HasAVX512VL(false), HasSHA(false), HasCX16(false),
1875         CPU(CK_Generic), FPMath(FP_Default) {
1876     BigEndian = false;
1877     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1878   }
1879   unsigned getFloatEvalMethod() const override {
1880     // X87 evaluates with 80 bits "long double" precision.
1881     return SSELevel == NoSSE ? 2 : 0;
1882   }
1883   void getTargetBuiltins(const Builtin::Info *&Records,
1884                                  unsigned &NumRecords) const override {
1885     Records = BuiltinInfo;
1886     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1887   }
1888   void getGCCRegNames(const char * const *&Names,
1889                       unsigned &NumNames) const override {
1890     Names = GCCRegNames;
1891     NumNames = llvm::array_lengthof(GCCRegNames);
1892   }
1893   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1894                         unsigned &NumAliases) const override {
1895     Aliases = nullptr;
1896     NumAliases = 0;
1897   }
1898   void getGCCAddlRegNames(const AddlRegName *&Names,
1899                           unsigned &NumNames) const override {
1900     Names = AddlRegNames;
1901     NumNames = llvm::array_lengthof(AddlRegNames);
1902   }
1903   bool validateAsmConstraint(const char *&Name,
1904                                      TargetInfo::ConstraintInfo &info) const override;
1905 
1906   bool validateOutputSize(StringRef Constraint, unsigned Size) const override;
1907 
1908   bool validateInputSize(StringRef Constraint, unsigned Size) const override;
1909 
1910   virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const;
1911 
1912   std::string convertConstraint(const char *&Constraint) const override;
1913   const char *getClobbers() const override {
1914     return "~{dirflag},~{fpsr},~{flags}";
1915   }
1916   void getTargetDefines(const LangOptions &Opts,
1917                         MacroBuilder &Builder) const override;
1918   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1919                           bool Enabled);
1920   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1921                           bool Enabled);
1922   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1923                           bool Enabled);
1924   void setFeatureEnabled(llvm::StringMap<bool> &Features,
1925                          StringRef Name, bool Enabled) const override {
1926     setFeatureEnabledImpl(Features, Name, Enabled);
1927   }
1928   // This exists purely to cut down on the number of virtual calls in
1929   // getDefaultFeatures which calls this repeatedly.
1930   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1931                                     StringRef Name, bool Enabled);
1932   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
1933   bool hasFeature(StringRef Feature) const override;
1934   bool handleTargetFeatures(std::vector<std::string> &Features,
1935                             DiagnosticsEngine &Diags) override;
1936   StringRef getABI() const override {
1937     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1938       return "avx";
1939     else if (getTriple().getArch() == llvm::Triple::x86 &&
1940              MMX3DNowLevel == NoMMX3DNow)
1941       return "no-mmx";
1942     return "";
1943   }
1944   bool setCPU(const std::string &Name) override {
1945     CPU = llvm::StringSwitch<CPUKind>(Name)
1946       .Case("i386", CK_i386)
1947       .Case("i486", CK_i486)
1948       .Case("winchip-c6", CK_WinChipC6)
1949       .Case("winchip2", CK_WinChip2)
1950       .Case("c3", CK_C3)
1951       .Case("i586", CK_i586)
1952       .Case("pentium", CK_Pentium)
1953       .Case("pentium-mmx", CK_PentiumMMX)
1954       .Case("i686", CK_i686)
1955       .Case("pentiumpro", CK_PentiumPro)
1956       .Case("pentium2", CK_Pentium2)
1957       .Case("pentium3", CK_Pentium3)
1958       .Case("pentium3m", CK_Pentium3M)
1959       .Case("pentium-m", CK_PentiumM)
1960       .Case("c3-2", CK_C3_2)
1961       .Case("yonah", CK_Yonah)
1962       .Case("pentium4", CK_Pentium4)
1963       .Case("pentium4m", CK_Pentium4M)
1964       .Case("prescott", CK_Prescott)
1965       .Case("nocona", CK_Nocona)
1966       .Case("core2", CK_Core2)
1967       .Case("penryn", CK_Penryn)
1968       .Case("atom", CK_Atom)
1969       .Case("slm", CK_Silvermont)
1970       .Case("corei7", CK_Corei7)
1971       .Case("corei7-avx", CK_Corei7AVX)
1972       .Case("core-avx-i", CK_CoreAVXi)
1973       .Case("core-avx2", CK_CoreAVX2)
1974       .Case("broadwell", CK_Broadwell)
1975       .Case("knl", CK_KNL)
1976       .Case("skx", CK_SKX)
1977       .Case("k6", CK_K6)
1978       .Case("k6-2", CK_K6_2)
1979       .Case("k6-3", CK_K6_3)
1980       .Case("athlon", CK_Athlon)
1981       .Case("athlon-tbird", CK_AthlonThunderbird)
1982       .Case("athlon-4", CK_Athlon4)
1983       .Case("athlon-xp", CK_AthlonXP)
1984       .Case("athlon-mp", CK_AthlonMP)
1985       .Case("athlon64", CK_Athlon64)
1986       .Case("athlon64-sse3", CK_Athlon64SSE3)
1987       .Case("athlon-fx", CK_AthlonFX)
1988       .Case("k8", CK_K8)
1989       .Case("k8-sse3", CK_K8SSE3)
1990       .Case("opteron", CK_Opteron)
1991       .Case("opteron-sse3", CK_OpteronSSE3)
1992       .Case("amdfam10", CK_AMDFAM10)
1993       .Case("btver1", CK_BTVER1)
1994       .Case("btver2", CK_BTVER2)
1995       .Case("bdver1", CK_BDVER1)
1996       .Case("bdver2", CK_BDVER2)
1997       .Case("bdver3", CK_BDVER3)
1998       .Case("bdver4", CK_BDVER4)
1999       .Case("x86-64", CK_x86_64)
2000       .Case("geode", CK_Geode)
2001       .Default(CK_Generic);
2002 
2003     // Perform any per-CPU checks necessary to determine if this CPU is
2004     // acceptable.
2005     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
2006     // invalid without explaining *why*.
2007     switch (CPU) {
2008     case CK_Generic:
2009       // No processor selected!
2010       return false;
2011 
2012     case CK_i386:
2013     case CK_i486:
2014     case CK_WinChipC6:
2015     case CK_WinChip2:
2016     case CK_C3:
2017     case CK_i586:
2018     case CK_Pentium:
2019     case CK_PentiumMMX:
2020     case CK_i686:
2021     case CK_PentiumPro:
2022     case CK_Pentium2:
2023     case CK_Pentium3:
2024     case CK_Pentium3M:
2025     case CK_PentiumM:
2026     case CK_Yonah:
2027     case CK_C3_2:
2028     case CK_Pentium4:
2029     case CK_Pentium4M:
2030     case CK_Prescott:
2031     case CK_K6:
2032     case CK_K6_2:
2033     case CK_K6_3:
2034     case CK_Athlon:
2035     case CK_AthlonThunderbird:
2036     case CK_Athlon4:
2037     case CK_AthlonXP:
2038     case CK_AthlonMP:
2039     case CK_Geode:
2040       // Only accept certain architectures when compiling in 32-bit mode.
2041       if (getTriple().getArch() != llvm::Triple::x86)
2042         return false;
2043 
2044       // Fallthrough
2045     case CK_Nocona:
2046     case CK_Core2:
2047     case CK_Penryn:
2048     case CK_Atom:
2049     case CK_Silvermont:
2050     case CK_Corei7:
2051     case CK_Corei7AVX:
2052     case CK_CoreAVXi:
2053     case CK_CoreAVX2:
2054     case CK_Broadwell:
2055     case CK_KNL:
2056     case CK_SKX:
2057     case CK_Athlon64:
2058     case CK_Athlon64SSE3:
2059     case CK_AthlonFX:
2060     case CK_K8:
2061     case CK_K8SSE3:
2062     case CK_Opteron:
2063     case CK_OpteronSSE3:
2064     case CK_AMDFAM10:
2065     case CK_BTVER1:
2066     case CK_BTVER2:
2067     case CK_BDVER1:
2068     case CK_BDVER2:
2069     case CK_BDVER3:
2070     case CK_BDVER4:
2071     case CK_x86_64:
2072       return true;
2073     }
2074     llvm_unreachable("Unhandled CPU kind");
2075   }
2076 
2077   bool setFPMath(StringRef Name) override;
2078 
2079   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2080     // We accept all non-ARM calling conventions
2081     return (CC == CC_X86ThisCall ||
2082             CC == CC_X86FastCall ||
2083             CC == CC_X86StdCall ||
2084             CC == CC_C ||
2085             CC == CC_X86Pascal ||
2086             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2087   }
2088 
2089   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2090     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2091   }
2092 };
2093 
2094 bool X86TargetInfo::setFPMath(StringRef Name) {
2095   if (Name == "387") {
2096     FPMath = FP_387;
2097     return true;
2098   }
2099   if (Name == "sse") {
2100     FPMath = FP_SSE;
2101     return true;
2102   }
2103   return false;
2104 }
2105 
2106 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2107   // FIXME: This *really* should not be here.
2108 
2109   // X86_64 always has SSE2.
2110   if (getTriple().getArch() == llvm::Triple::x86_64)
2111     setFeatureEnabledImpl(Features, "sse2", true);
2112 
2113   switch (CPU) {
2114   case CK_Generic:
2115   case CK_i386:
2116   case CK_i486:
2117   case CK_i586:
2118   case CK_Pentium:
2119   case CK_i686:
2120   case CK_PentiumPro:
2121     break;
2122   case CK_PentiumMMX:
2123   case CK_Pentium2:
2124     setFeatureEnabledImpl(Features, "mmx", true);
2125     break;
2126   case CK_Pentium3:
2127   case CK_Pentium3M:
2128     setFeatureEnabledImpl(Features, "sse", true);
2129     break;
2130   case CK_PentiumM:
2131   case CK_Pentium4:
2132   case CK_Pentium4M:
2133   case CK_x86_64:
2134     setFeatureEnabledImpl(Features, "sse2", true);
2135     break;
2136   case CK_Yonah:
2137   case CK_Prescott:
2138   case CK_Nocona:
2139     setFeatureEnabledImpl(Features, "sse3", true);
2140     setFeatureEnabledImpl(Features, "cx16", true);
2141     break;
2142   case CK_Core2:
2143     setFeatureEnabledImpl(Features, "ssse3", true);
2144     setFeatureEnabledImpl(Features, "cx16", true);
2145     break;
2146   case CK_Penryn:
2147     setFeatureEnabledImpl(Features, "sse4.1", true);
2148     setFeatureEnabledImpl(Features, "cx16", true);
2149     break;
2150   case CK_Atom:
2151     setFeatureEnabledImpl(Features, "ssse3", true);
2152     setFeatureEnabledImpl(Features, "cx16", true);
2153     break;
2154   case CK_Silvermont:
2155     setFeatureEnabledImpl(Features, "sse4.2", true);
2156     setFeatureEnabledImpl(Features, "aes", true);
2157     setFeatureEnabledImpl(Features, "cx16", true);
2158     setFeatureEnabledImpl(Features, "pclmul", true);
2159     break;
2160   case CK_Corei7:
2161     setFeatureEnabledImpl(Features, "sse4.2", true);
2162     setFeatureEnabledImpl(Features, "cx16", true);
2163     break;
2164   case CK_Corei7AVX:
2165     setFeatureEnabledImpl(Features, "avx", true);
2166     setFeatureEnabledImpl(Features, "aes", true);
2167     setFeatureEnabledImpl(Features, "cx16", true);
2168     setFeatureEnabledImpl(Features, "pclmul", true);
2169     break;
2170   case CK_CoreAVXi:
2171     setFeatureEnabledImpl(Features, "avx", true);
2172     setFeatureEnabledImpl(Features, "aes", true);
2173     setFeatureEnabledImpl(Features, "pclmul", true);
2174     setFeatureEnabledImpl(Features, "rdrnd", true);
2175     setFeatureEnabledImpl(Features, "f16c", true);
2176     break;
2177   case CK_CoreAVX2:
2178     setFeatureEnabledImpl(Features, "avx2", true);
2179     setFeatureEnabledImpl(Features, "aes", true);
2180     setFeatureEnabledImpl(Features, "pclmul", true);
2181     setFeatureEnabledImpl(Features, "lzcnt", true);
2182     setFeatureEnabledImpl(Features, "rdrnd", true);
2183     setFeatureEnabledImpl(Features, "f16c", true);
2184     setFeatureEnabledImpl(Features, "bmi", true);
2185     setFeatureEnabledImpl(Features, "bmi2", true);
2186     setFeatureEnabledImpl(Features, "rtm", true);
2187     setFeatureEnabledImpl(Features, "fma", true);
2188     setFeatureEnabledImpl(Features, "cx16", true);
2189     break;
2190   case CK_Broadwell:
2191     setFeatureEnabledImpl(Features, "avx2", true);
2192     setFeatureEnabledImpl(Features, "aes", true);
2193     setFeatureEnabledImpl(Features, "pclmul", true);
2194     setFeatureEnabledImpl(Features, "lzcnt", true);
2195     setFeatureEnabledImpl(Features, "rdrnd", true);
2196     setFeatureEnabledImpl(Features, "f16c", true);
2197     setFeatureEnabledImpl(Features, "bmi", true);
2198     setFeatureEnabledImpl(Features, "bmi2", true);
2199     setFeatureEnabledImpl(Features, "rtm", true);
2200     setFeatureEnabledImpl(Features, "fma", true);
2201     setFeatureEnabledImpl(Features, "cx16", true);
2202     setFeatureEnabledImpl(Features, "rdseed", true);
2203     setFeatureEnabledImpl(Features, "adx", true);
2204     break;
2205   case CK_KNL:
2206     setFeatureEnabledImpl(Features, "avx512f", true);
2207     setFeatureEnabledImpl(Features, "avx512cd", true);
2208     setFeatureEnabledImpl(Features, "avx512er", true);
2209     setFeatureEnabledImpl(Features, "avx512pf", true);
2210     setFeatureEnabledImpl(Features, "aes", true);
2211     setFeatureEnabledImpl(Features, "pclmul", true);
2212     setFeatureEnabledImpl(Features, "lzcnt", true);
2213     setFeatureEnabledImpl(Features, "rdrnd", true);
2214     setFeatureEnabledImpl(Features, "f16c", true);
2215     setFeatureEnabledImpl(Features, "bmi", true);
2216     setFeatureEnabledImpl(Features, "bmi2", true);
2217     setFeatureEnabledImpl(Features, "rtm", true);
2218     setFeatureEnabledImpl(Features, "fma", true);
2219     setFeatureEnabledImpl(Features, "rdseed", true);
2220     setFeatureEnabledImpl(Features, "adx", true);
2221     break;
2222   case CK_SKX:
2223     setFeatureEnabledImpl(Features, "avx512f", true);
2224     setFeatureEnabledImpl(Features, "avx512cd", true);
2225     setFeatureEnabledImpl(Features, "avx512dq", true);
2226     setFeatureEnabledImpl(Features, "avx512bw", true);
2227     setFeatureEnabledImpl(Features, "avx512vl", true);
2228     setFeatureEnabledImpl(Features, "aes", true);
2229     setFeatureEnabledImpl(Features, "pclmul", true);
2230     setFeatureEnabledImpl(Features, "lzcnt", true);
2231     setFeatureEnabledImpl(Features, "rdrnd", true);
2232     setFeatureEnabledImpl(Features, "f16c", true);
2233     setFeatureEnabledImpl(Features, "bmi", true);
2234     setFeatureEnabledImpl(Features, "bmi2", true);
2235     setFeatureEnabledImpl(Features, "rtm", true);
2236     setFeatureEnabledImpl(Features, "fma", true);
2237     setFeatureEnabledImpl(Features, "rdseed", true);
2238     setFeatureEnabledImpl(Features, "adx", true);
2239     break;
2240   case CK_K6:
2241   case CK_WinChipC6:
2242     setFeatureEnabledImpl(Features, "mmx", true);
2243     break;
2244   case CK_K6_2:
2245   case CK_K6_3:
2246   case CK_WinChip2:
2247   case CK_C3:
2248     setFeatureEnabledImpl(Features, "3dnow", true);
2249     break;
2250   case CK_Athlon:
2251   case CK_AthlonThunderbird:
2252   case CK_Geode:
2253     setFeatureEnabledImpl(Features, "3dnowa", true);
2254     break;
2255   case CK_Athlon4:
2256   case CK_AthlonXP:
2257   case CK_AthlonMP:
2258     setFeatureEnabledImpl(Features, "sse", true);
2259     setFeatureEnabledImpl(Features, "3dnowa", true);
2260     break;
2261   case CK_K8:
2262   case CK_Opteron:
2263   case CK_Athlon64:
2264   case CK_AthlonFX:
2265     setFeatureEnabledImpl(Features, "sse2", true);
2266     setFeatureEnabledImpl(Features, "3dnowa", true);
2267     break;
2268   case CK_K8SSE3:
2269   case CK_OpteronSSE3:
2270   case CK_Athlon64SSE3:
2271     setFeatureEnabledImpl(Features, "sse3", true);
2272     setFeatureEnabledImpl(Features, "3dnowa", true);
2273     break;
2274   case CK_AMDFAM10:
2275     setFeatureEnabledImpl(Features, "sse3", true);
2276     setFeatureEnabledImpl(Features, "sse4a", true);
2277     setFeatureEnabledImpl(Features, "3dnowa", true);
2278     setFeatureEnabledImpl(Features, "lzcnt", true);
2279     setFeatureEnabledImpl(Features, "popcnt", true);
2280     break;
2281   case CK_BTVER1:
2282     setFeatureEnabledImpl(Features, "ssse3", true);
2283     setFeatureEnabledImpl(Features, "sse4a", true);
2284     setFeatureEnabledImpl(Features, "cx16", true);
2285     setFeatureEnabledImpl(Features, "lzcnt", true);
2286     setFeatureEnabledImpl(Features, "popcnt", true);
2287     setFeatureEnabledImpl(Features, "prfchw", true);
2288     break;
2289   case CK_BTVER2:
2290     setFeatureEnabledImpl(Features, "avx", true);
2291     setFeatureEnabledImpl(Features, "sse4a", true);
2292     setFeatureEnabledImpl(Features, "lzcnt", true);
2293     setFeatureEnabledImpl(Features, "aes", true);
2294     setFeatureEnabledImpl(Features, "pclmul", true);
2295     setFeatureEnabledImpl(Features, "prfchw", true);
2296     setFeatureEnabledImpl(Features, "bmi", true);
2297     setFeatureEnabledImpl(Features, "f16c", true);
2298     setFeatureEnabledImpl(Features, "cx16", true);
2299     break;
2300   case CK_BDVER1:
2301     setFeatureEnabledImpl(Features, "xop", true);
2302     setFeatureEnabledImpl(Features, "lzcnt", true);
2303     setFeatureEnabledImpl(Features, "aes", true);
2304     setFeatureEnabledImpl(Features, "pclmul", true);
2305     setFeatureEnabledImpl(Features, "prfchw", true);
2306     setFeatureEnabledImpl(Features, "cx16", true);
2307     break;
2308   case CK_BDVER4:
2309     setFeatureEnabledImpl(Features, "avx2", true);
2310     setFeatureEnabledImpl(Features, "bmi2", true);
2311     // FALLTHROUGH
2312   case CK_BDVER2:
2313   case CK_BDVER3:
2314     setFeatureEnabledImpl(Features, "xop", true);
2315     setFeatureEnabledImpl(Features, "lzcnt", true);
2316     setFeatureEnabledImpl(Features, "aes", true);
2317     setFeatureEnabledImpl(Features, "pclmul", true);
2318     setFeatureEnabledImpl(Features, "prfchw", true);
2319     setFeatureEnabledImpl(Features, "bmi", true);
2320     setFeatureEnabledImpl(Features, "fma", true);
2321     setFeatureEnabledImpl(Features, "f16c", true);
2322     setFeatureEnabledImpl(Features, "tbm", true);
2323     setFeatureEnabledImpl(Features, "cx16", true);
2324     break;
2325   case CK_C3_2:
2326     setFeatureEnabledImpl(Features, "sse", true);
2327     break;
2328   }
2329 }
2330 
2331 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2332                                 X86SSEEnum Level, bool Enabled) {
2333   if (Enabled) {
2334     switch (Level) {
2335     case AVX512F:
2336       Features["avx512f"] = true;
2337     case AVX2:
2338       Features["avx2"] = true;
2339     case AVX:
2340       Features["avx"] = true;
2341     case SSE42:
2342       Features["sse4.2"] = true;
2343     case SSE41:
2344       Features["sse4.1"] = true;
2345     case SSSE3:
2346       Features["ssse3"] = true;
2347     case SSE3:
2348       Features["sse3"] = true;
2349     case SSE2:
2350       Features["sse2"] = true;
2351     case SSE1:
2352       Features["sse"] = true;
2353     case NoSSE:
2354       break;
2355     }
2356     return;
2357   }
2358 
2359   switch (Level) {
2360   case NoSSE:
2361   case SSE1:
2362     Features["sse"] = false;
2363   case SSE2:
2364     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2365       Features["sha"] = false;
2366   case SSE3:
2367     Features["sse3"] = false;
2368     setXOPLevel(Features, NoXOP, false);
2369   case SSSE3:
2370     Features["ssse3"] = false;
2371   case SSE41:
2372     Features["sse4.1"] = false;
2373   case SSE42:
2374     Features["sse4.2"] = false;
2375   case AVX:
2376     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2377     setXOPLevel(Features, FMA4, false);
2378   case AVX2:
2379     Features["avx2"] = false;
2380   case AVX512F:
2381     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = Features["avx512pf"] =
2382     Features["avx512dq"] = Features["avx512bw"] = Features["avx512vl"] = false;
2383   }
2384 }
2385 
2386 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2387                                 MMX3DNowEnum Level, bool Enabled) {
2388   if (Enabled) {
2389     switch (Level) {
2390     case AMD3DNowAthlon:
2391       Features["3dnowa"] = true;
2392     case AMD3DNow:
2393       Features["3dnow"] = true;
2394     case MMX:
2395       Features["mmx"] = true;
2396     case NoMMX3DNow:
2397       break;
2398     }
2399     return;
2400   }
2401 
2402   switch (Level) {
2403   case NoMMX3DNow:
2404   case MMX:
2405     Features["mmx"] = false;
2406   case AMD3DNow:
2407     Features["3dnow"] = false;
2408   case AMD3DNowAthlon:
2409     Features["3dnowa"] = false;
2410   }
2411 }
2412 
2413 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2414                                 bool Enabled) {
2415   if (Enabled) {
2416     switch (Level) {
2417     case XOP:
2418       Features["xop"] = true;
2419     case FMA4:
2420       Features["fma4"] = true;
2421       setSSELevel(Features, AVX, true);
2422     case SSE4A:
2423       Features["sse4a"] = true;
2424       setSSELevel(Features, SSE3, true);
2425     case NoXOP:
2426       break;
2427     }
2428     return;
2429   }
2430 
2431   switch (Level) {
2432   case NoXOP:
2433   case SSE4A:
2434     Features["sse4a"] = false;
2435   case FMA4:
2436     Features["fma4"] = false;
2437   case XOP:
2438     Features["xop"] = false;
2439   }
2440 }
2441 
2442 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2443                                           StringRef Name, bool Enabled) {
2444   // FIXME: This *really* should not be here.  We need some way of translating
2445   // options into llvm subtarget features.
2446   if (Name == "sse4")
2447     Name = "sse4.2";
2448 
2449   Features[Name] = Enabled;
2450 
2451   if (Name == "mmx") {
2452     setMMXLevel(Features, MMX, Enabled);
2453   } else if (Name == "sse") {
2454     setSSELevel(Features, SSE1, Enabled);
2455   } else if (Name == "sse2") {
2456     setSSELevel(Features, SSE2, Enabled);
2457   } else if (Name == "sse3") {
2458     setSSELevel(Features, SSE3, Enabled);
2459   } else if (Name == "ssse3") {
2460     setSSELevel(Features, SSSE3, Enabled);
2461   } else if (Name == "sse4.2") {
2462     setSSELevel(Features, SSE42, Enabled);
2463   } else if (Name == "sse4.1") {
2464     setSSELevel(Features, SSE41, Enabled);
2465   } else if (Name == "3dnow") {
2466     setMMXLevel(Features, AMD3DNow, Enabled);
2467   } else if (Name == "3dnowa") {
2468     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2469   } else if (Name == "aes") {
2470     if (Enabled)
2471       setSSELevel(Features, SSE2, Enabled);
2472   } else if (Name == "pclmul") {
2473     if (Enabled)
2474       setSSELevel(Features, SSE2, Enabled);
2475   } else if (Name == "avx") {
2476     setSSELevel(Features, AVX, Enabled);
2477   } else if (Name == "avx2") {
2478     setSSELevel(Features, AVX2, Enabled);
2479   } else if (Name == "avx512f") {
2480     setSSELevel(Features, AVX512F, Enabled);
2481   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf"
2482           || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") {
2483     if (Enabled)
2484       setSSELevel(Features, AVX512F, Enabled);
2485   } else if (Name == "fma") {
2486     if (Enabled)
2487       setSSELevel(Features, AVX, Enabled);
2488   } else if (Name == "fma4") {
2489     setXOPLevel(Features, FMA4, Enabled);
2490   } else if (Name == "xop") {
2491     setXOPLevel(Features, XOP, Enabled);
2492   } else if (Name == "sse4a") {
2493     setXOPLevel(Features, SSE4A, Enabled);
2494   } else if (Name == "f16c") {
2495     if (Enabled)
2496       setSSELevel(Features, AVX, Enabled);
2497   } else if (Name == "sha") {
2498     if (Enabled)
2499       setSSELevel(Features, SSE2, Enabled);
2500   }
2501 }
2502 
2503 /// handleTargetFeatures - Perform initialization based on the user
2504 /// configured set of features.
2505 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2506                                          DiagnosticsEngine &Diags) {
2507   // Remember the maximum enabled sselevel.
2508   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2509     // Ignore disabled features.
2510     if (Features[i][0] == '-')
2511       continue;
2512 
2513     StringRef Feature = StringRef(Features[i]).substr(1);
2514 
2515     if (Feature == "aes") {
2516       HasAES = true;
2517       continue;
2518     }
2519 
2520     if (Feature == "pclmul") {
2521       HasPCLMUL = true;
2522       continue;
2523     }
2524 
2525     if (Feature == "lzcnt") {
2526       HasLZCNT = true;
2527       continue;
2528     }
2529 
2530     if (Feature == "rdrnd") {
2531       HasRDRND = true;
2532       continue;
2533     }
2534 
2535     if (Feature == "bmi") {
2536       HasBMI = true;
2537       continue;
2538     }
2539 
2540     if (Feature == "bmi2") {
2541       HasBMI2 = true;
2542       continue;
2543     }
2544 
2545     if (Feature == "popcnt") {
2546       HasPOPCNT = true;
2547       continue;
2548     }
2549 
2550     if (Feature == "rtm") {
2551       HasRTM = true;
2552       continue;
2553     }
2554 
2555     if (Feature == "prfchw") {
2556       HasPRFCHW = true;
2557       continue;
2558     }
2559 
2560     if (Feature == "rdseed") {
2561       HasRDSEED = true;
2562       continue;
2563     }
2564 
2565     if (Feature == "adx") {
2566       HasADX = true;
2567       continue;
2568     }
2569 
2570     if (Feature == "tbm") {
2571       HasTBM = true;
2572       continue;
2573     }
2574 
2575     if (Feature == "fma") {
2576       HasFMA = true;
2577       continue;
2578     }
2579 
2580     if (Feature == "f16c") {
2581       HasF16C = true;
2582       continue;
2583     }
2584 
2585     if (Feature == "avx512cd") {
2586       HasAVX512CD = true;
2587       continue;
2588     }
2589 
2590     if (Feature == "avx512er") {
2591       HasAVX512ER = true;
2592       continue;
2593     }
2594 
2595     if (Feature == "avx512pf") {
2596       HasAVX512PF = true;
2597       continue;
2598     }
2599 
2600     if (Feature == "avx512dq") {
2601       HasAVX512DQ = true;
2602       continue;
2603     }
2604 
2605     if (Feature == "avx512bw") {
2606       HasAVX512BW = true;
2607       continue;
2608     }
2609 
2610     if (Feature == "avx512vl") {
2611       HasAVX512VL = true;
2612       continue;
2613     }
2614 
2615     if (Feature == "sha") {
2616       HasSHA = true;
2617       continue;
2618     }
2619 
2620     if (Feature == "cx16") {
2621       HasCX16 = true;
2622       continue;
2623     }
2624 
2625     assert(Features[i][0] == '+' && "Invalid target feature!");
2626     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2627       .Case("avx512f", AVX512F)
2628       .Case("avx2", AVX2)
2629       .Case("avx", AVX)
2630       .Case("sse4.2", SSE42)
2631       .Case("sse4.1", SSE41)
2632       .Case("ssse3", SSSE3)
2633       .Case("sse3", SSE3)
2634       .Case("sse2", SSE2)
2635       .Case("sse", SSE1)
2636       .Default(NoSSE);
2637     SSELevel = std::max(SSELevel, Level);
2638 
2639     MMX3DNowEnum ThreeDNowLevel =
2640       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2641         .Case("3dnowa", AMD3DNowAthlon)
2642         .Case("3dnow", AMD3DNow)
2643         .Case("mmx", MMX)
2644         .Default(NoMMX3DNow);
2645     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2646 
2647     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2648         .Case("xop", XOP)
2649         .Case("fma4", FMA4)
2650         .Case("sse4a", SSE4A)
2651         .Default(NoXOP);
2652     XOPLevel = std::max(XOPLevel, XLevel);
2653   }
2654 
2655   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2656   // Can't do this earlier because we need to be able to explicitly enable
2657   // popcnt and still disable sse4.2.
2658   if (!HasPOPCNT && SSELevel >= SSE42 &&
2659       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2660     HasPOPCNT = true;
2661     Features.push_back("+popcnt");
2662   }
2663 
2664   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2665   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2666       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2667     HasPRFCHW = true;
2668     Features.push_back("+prfchw");
2669   }
2670 
2671   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2672   // matches the selected sse level.
2673   if (FPMath == FP_SSE && SSELevel < SSE1) {
2674     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2675     return false;
2676   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2677     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2678     return false;
2679   }
2680 
2681   // Don't tell the backend if we're turning off mmx; it will end up disabling
2682   // SSE, which we don't want.
2683   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2684   // then enable MMX.
2685   std::vector<std::string>::iterator it;
2686   it = std::find(Features.begin(), Features.end(), "-mmx");
2687   if (it != Features.end())
2688     Features.erase(it);
2689   else if (SSELevel > NoSSE)
2690     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2691   return true;
2692 }
2693 
2694 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2695 /// definitions for this particular subtarget.
2696 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2697                                      MacroBuilder &Builder) const {
2698   // Target identification.
2699   if (getTriple().getArch() == llvm::Triple::x86_64) {
2700     Builder.defineMacro("__amd64__");
2701     Builder.defineMacro("__amd64");
2702     Builder.defineMacro("__x86_64");
2703     Builder.defineMacro("__x86_64__");
2704     if (getTriple().getArchName() == "x86_64h") {
2705       Builder.defineMacro("__x86_64h");
2706       Builder.defineMacro("__x86_64h__");
2707     }
2708   } else {
2709     DefineStd(Builder, "i386", Opts);
2710   }
2711 
2712   // Subtarget options.
2713   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2714   // truly should be based on -mtune options.
2715   switch (CPU) {
2716   case CK_Generic:
2717     break;
2718   case CK_i386:
2719     // The rest are coming from the i386 define above.
2720     Builder.defineMacro("__tune_i386__");
2721     break;
2722   case CK_i486:
2723   case CK_WinChipC6:
2724   case CK_WinChip2:
2725   case CK_C3:
2726     defineCPUMacros(Builder, "i486");
2727     break;
2728   case CK_PentiumMMX:
2729     Builder.defineMacro("__pentium_mmx__");
2730     Builder.defineMacro("__tune_pentium_mmx__");
2731     // Fallthrough
2732   case CK_i586:
2733   case CK_Pentium:
2734     defineCPUMacros(Builder, "i586");
2735     defineCPUMacros(Builder, "pentium");
2736     break;
2737   case CK_Pentium3:
2738   case CK_Pentium3M:
2739   case CK_PentiumM:
2740     Builder.defineMacro("__tune_pentium3__");
2741     // Fallthrough
2742   case CK_Pentium2:
2743   case CK_C3_2:
2744     Builder.defineMacro("__tune_pentium2__");
2745     // Fallthrough
2746   case CK_PentiumPro:
2747     Builder.defineMacro("__tune_i686__");
2748     Builder.defineMacro("__tune_pentiumpro__");
2749     // Fallthrough
2750   case CK_i686:
2751     Builder.defineMacro("__i686");
2752     Builder.defineMacro("__i686__");
2753     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2754     Builder.defineMacro("__pentiumpro");
2755     Builder.defineMacro("__pentiumpro__");
2756     break;
2757   case CK_Pentium4:
2758   case CK_Pentium4M:
2759     defineCPUMacros(Builder, "pentium4");
2760     break;
2761   case CK_Yonah:
2762   case CK_Prescott:
2763   case CK_Nocona:
2764     defineCPUMacros(Builder, "nocona");
2765     break;
2766   case CK_Core2:
2767   case CK_Penryn:
2768     defineCPUMacros(Builder, "core2");
2769     break;
2770   case CK_Atom:
2771     defineCPUMacros(Builder, "atom");
2772     break;
2773   case CK_Silvermont:
2774     defineCPUMacros(Builder, "slm");
2775     break;
2776   case CK_Corei7:
2777   case CK_Corei7AVX:
2778   case CK_CoreAVXi:
2779   case CK_CoreAVX2:
2780   case CK_Broadwell:
2781     defineCPUMacros(Builder, "corei7");
2782     break;
2783   case CK_KNL:
2784     defineCPUMacros(Builder, "knl");
2785     break;
2786   case CK_SKX:
2787     defineCPUMacros(Builder, "skx");
2788     break;
2789   case CK_K6_2:
2790     Builder.defineMacro("__k6_2__");
2791     Builder.defineMacro("__tune_k6_2__");
2792     // Fallthrough
2793   case CK_K6_3:
2794     if (CPU != CK_K6_2) {  // In case of fallthrough
2795       // FIXME: GCC may be enabling these in cases where some other k6
2796       // architecture is specified but -m3dnow is explicitly provided. The
2797       // exact semantics need to be determined and emulated here.
2798       Builder.defineMacro("__k6_3__");
2799       Builder.defineMacro("__tune_k6_3__");
2800     }
2801     // Fallthrough
2802   case CK_K6:
2803     defineCPUMacros(Builder, "k6");
2804     break;
2805   case CK_Athlon:
2806   case CK_AthlonThunderbird:
2807   case CK_Athlon4:
2808   case CK_AthlonXP:
2809   case CK_AthlonMP:
2810     defineCPUMacros(Builder, "athlon");
2811     if (SSELevel != NoSSE) {
2812       Builder.defineMacro("__athlon_sse__");
2813       Builder.defineMacro("__tune_athlon_sse__");
2814     }
2815     break;
2816   case CK_K8:
2817   case CK_K8SSE3:
2818   case CK_x86_64:
2819   case CK_Opteron:
2820   case CK_OpteronSSE3:
2821   case CK_Athlon64:
2822   case CK_Athlon64SSE3:
2823   case CK_AthlonFX:
2824     defineCPUMacros(Builder, "k8");
2825     break;
2826   case CK_AMDFAM10:
2827     defineCPUMacros(Builder, "amdfam10");
2828     break;
2829   case CK_BTVER1:
2830     defineCPUMacros(Builder, "btver1");
2831     break;
2832   case CK_BTVER2:
2833     defineCPUMacros(Builder, "btver2");
2834     break;
2835   case CK_BDVER1:
2836     defineCPUMacros(Builder, "bdver1");
2837     break;
2838   case CK_BDVER2:
2839     defineCPUMacros(Builder, "bdver2");
2840     break;
2841   case CK_BDVER3:
2842     defineCPUMacros(Builder, "bdver3");
2843     break;
2844   case CK_BDVER4:
2845     defineCPUMacros(Builder, "bdver4");
2846     break;
2847   case CK_Geode:
2848     defineCPUMacros(Builder, "geode");
2849     break;
2850   }
2851 
2852   // Target properties.
2853   Builder.defineMacro("__REGISTER_PREFIX__", "");
2854 
2855   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2856   // functions in glibc header files that use FP Stack inline asm which the
2857   // backend can't deal with (PR879).
2858   Builder.defineMacro("__NO_MATH_INLINES");
2859 
2860   if (HasAES)
2861     Builder.defineMacro("__AES__");
2862 
2863   if (HasPCLMUL)
2864     Builder.defineMacro("__PCLMUL__");
2865 
2866   if (HasLZCNT)
2867     Builder.defineMacro("__LZCNT__");
2868 
2869   if (HasRDRND)
2870     Builder.defineMacro("__RDRND__");
2871 
2872   if (HasBMI)
2873     Builder.defineMacro("__BMI__");
2874 
2875   if (HasBMI2)
2876     Builder.defineMacro("__BMI2__");
2877 
2878   if (HasPOPCNT)
2879     Builder.defineMacro("__POPCNT__");
2880 
2881   if (HasRTM)
2882     Builder.defineMacro("__RTM__");
2883 
2884   if (HasPRFCHW)
2885     Builder.defineMacro("__PRFCHW__");
2886 
2887   if (HasRDSEED)
2888     Builder.defineMacro("__RDSEED__");
2889 
2890   if (HasADX)
2891     Builder.defineMacro("__ADX__");
2892 
2893   if (HasTBM)
2894     Builder.defineMacro("__TBM__");
2895 
2896   switch (XOPLevel) {
2897   case XOP:
2898     Builder.defineMacro("__XOP__");
2899   case FMA4:
2900     Builder.defineMacro("__FMA4__");
2901   case SSE4A:
2902     Builder.defineMacro("__SSE4A__");
2903   case NoXOP:
2904     break;
2905   }
2906 
2907   if (HasFMA)
2908     Builder.defineMacro("__FMA__");
2909 
2910   if (HasF16C)
2911     Builder.defineMacro("__F16C__");
2912 
2913   if (HasAVX512CD)
2914     Builder.defineMacro("__AVX512CD__");
2915   if (HasAVX512ER)
2916     Builder.defineMacro("__AVX512ER__");
2917   if (HasAVX512PF)
2918     Builder.defineMacro("__AVX512PF__");
2919   if (HasAVX512DQ)
2920     Builder.defineMacro("__AVX512DQ__");
2921   if (HasAVX512BW)
2922     Builder.defineMacro("__AVX512BW__");
2923   if (HasAVX512VL)
2924     Builder.defineMacro("__AVX512VL__");
2925 
2926   if (HasSHA)
2927     Builder.defineMacro("__SHA__");
2928 
2929   if (HasCX16)
2930     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2931 
2932   // Each case falls through to the previous one here.
2933   switch (SSELevel) {
2934   case AVX512F:
2935     Builder.defineMacro("__AVX512F__");
2936   case AVX2:
2937     Builder.defineMacro("__AVX2__");
2938   case AVX:
2939     Builder.defineMacro("__AVX__");
2940   case SSE42:
2941     Builder.defineMacro("__SSE4_2__");
2942   case SSE41:
2943     Builder.defineMacro("__SSE4_1__");
2944   case SSSE3:
2945     Builder.defineMacro("__SSSE3__");
2946   case SSE3:
2947     Builder.defineMacro("__SSE3__");
2948   case SSE2:
2949     Builder.defineMacro("__SSE2__");
2950     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2951   case SSE1:
2952     Builder.defineMacro("__SSE__");
2953     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2954   case NoSSE:
2955     break;
2956   }
2957 
2958   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2959     switch (SSELevel) {
2960     case AVX512F:
2961     case AVX2:
2962     case AVX:
2963     case SSE42:
2964     case SSE41:
2965     case SSSE3:
2966     case SSE3:
2967     case SSE2:
2968       Builder.defineMacro("_M_IX86_FP", Twine(2));
2969       break;
2970     case SSE1:
2971       Builder.defineMacro("_M_IX86_FP", Twine(1));
2972       break;
2973     default:
2974       Builder.defineMacro("_M_IX86_FP", Twine(0));
2975     }
2976   }
2977 
2978   // Each case falls through to the previous one here.
2979   switch (MMX3DNowLevel) {
2980   case AMD3DNowAthlon:
2981     Builder.defineMacro("__3dNOW_A__");
2982   case AMD3DNow:
2983     Builder.defineMacro("__3dNOW__");
2984   case MMX:
2985     Builder.defineMacro("__MMX__");
2986   case NoMMX3DNow:
2987     break;
2988   }
2989 
2990   if (CPU >= CK_i486) {
2991     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2992     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2993     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2994   }
2995   if (CPU >= CK_i586)
2996     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2997 }
2998 
2999 bool X86TargetInfo::hasFeature(StringRef Feature) const {
3000   return llvm::StringSwitch<bool>(Feature)
3001       .Case("aes", HasAES)
3002       .Case("avx", SSELevel >= AVX)
3003       .Case("avx2", SSELevel >= AVX2)
3004       .Case("avx512f", SSELevel >= AVX512F)
3005       .Case("avx512cd", HasAVX512CD)
3006       .Case("avx512er", HasAVX512ER)
3007       .Case("avx512pf", HasAVX512PF)
3008       .Case("avx512dq", HasAVX512DQ)
3009       .Case("avx512bw", HasAVX512BW)
3010       .Case("avx512vl", HasAVX512VL)
3011       .Case("bmi", HasBMI)
3012       .Case("bmi2", HasBMI2)
3013       .Case("cx16", HasCX16)
3014       .Case("f16c", HasF16C)
3015       .Case("fma", HasFMA)
3016       .Case("fma4", XOPLevel >= FMA4)
3017       .Case("tbm", HasTBM)
3018       .Case("lzcnt", HasLZCNT)
3019       .Case("rdrnd", HasRDRND)
3020       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
3021       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
3022       .Case("mmx", MMX3DNowLevel >= MMX)
3023       .Case("pclmul", HasPCLMUL)
3024       .Case("popcnt", HasPOPCNT)
3025       .Case("rtm", HasRTM)
3026       .Case("prfchw", HasPRFCHW)
3027       .Case("rdseed", HasRDSEED)
3028       .Case("sha", HasSHA)
3029       .Case("sse", SSELevel >= SSE1)
3030       .Case("sse2", SSELevel >= SSE2)
3031       .Case("sse3", SSELevel >= SSE3)
3032       .Case("ssse3", SSELevel >= SSSE3)
3033       .Case("sse4.1", SSELevel >= SSE41)
3034       .Case("sse4.2", SSELevel >= SSE42)
3035       .Case("sse4a", XOPLevel >= SSE4A)
3036       .Case("x86", true)
3037       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
3038       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
3039       .Case("xop", XOPLevel >= XOP)
3040       .Default(false);
3041 }
3042 
3043 bool
3044 X86TargetInfo::validateAsmConstraint(const char *&Name,
3045                                      TargetInfo::ConstraintInfo &Info) const {
3046   switch (*Name) {
3047   default: return false;
3048   case 'Y': // first letter of a pair:
3049     switch (*(Name+1)) {
3050     default: return false;
3051     case '0':  // First SSE register.
3052     case 't':  // Any SSE register, when SSE2 is enabled.
3053     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
3054     case 'm':  // any MMX register, when inter-unit moves enabled.
3055       break;   // falls through to setAllowsRegister.
3056   }
3057   case 'f': // any x87 floating point stack register.
3058     // Constraint 'f' cannot be used for output operands.
3059     if (Info.ConstraintStr[0] == '=')
3060       return false;
3061 
3062     Info.setAllowsRegister();
3063     return true;
3064   case 'a': // eax.
3065   case 'b': // ebx.
3066   case 'c': // ecx.
3067   case 'd': // edx.
3068   case 'S': // esi.
3069   case 'D': // edi.
3070   case 'A': // edx:eax.
3071   case 't': // top of floating point stack.
3072   case 'u': // second from top of floating point stack.
3073   case 'q': // Any register accessible as [r]l: a, b, c, and d.
3074   case 'y': // Any MMX register.
3075   case 'x': // Any SSE register.
3076   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
3077   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
3078   case 'l': // "Index" registers: any general register that can be used as an
3079             // index in a base+index memory access.
3080     Info.setAllowsRegister();
3081     return true;
3082   case 'C': // SSE floating point constant.
3083   case 'G': // x87 floating point constant.
3084   case 'e': // 32-bit signed integer constant for use with zero-extending
3085             // x86_64 instructions.
3086   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
3087             // x86_64 instructions.
3088     return true;
3089   }
3090 }
3091 
3092 bool X86TargetInfo::validateOutputSize(StringRef Constraint,
3093                                        unsigned Size) const {
3094   // Strip off constraint modifiers.
3095   while (Constraint[0] == '=' ||
3096          Constraint[0] == '+' ||
3097          Constraint[0] == '&')
3098     Constraint = Constraint.substr(1);
3099 
3100   return validateOperandSize(Constraint, Size);
3101 }
3102 
3103 bool X86TargetInfo::validateInputSize(StringRef Constraint,
3104                                       unsigned Size) const {
3105   return validateOperandSize(Constraint, Size);
3106 }
3107 
3108 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
3109                                         unsigned Size) const {
3110   switch (Constraint[0]) {
3111   default: break;
3112   case 'y':
3113     return Size <= 64;
3114   case 'f':
3115   case 't':
3116   case 'u':
3117     return Size <= 128;
3118   case 'x':
3119     // 256-bit ymm registers can be used if target supports AVX.
3120     return Size <= (SSELevel >= AVX ? 256U : 128U);
3121   }
3122 
3123   return true;
3124 }
3125 
3126 std::string
3127 X86TargetInfo::convertConstraint(const char *&Constraint) const {
3128   switch (*Constraint) {
3129   case 'a': return std::string("{ax}");
3130   case 'b': return std::string("{bx}");
3131   case 'c': return std::string("{cx}");
3132   case 'd': return std::string("{dx}");
3133   case 'S': return std::string("{si}");
3134   case 'D': return std::string("{di}");
3135   case 'p': // address
3136     return std::string("im");
3137   case 't': // top of floating point stack.
3138     return std::string("{st}");
3139   case 'u': // second from top of floating point stack.
3140     return std::string("{st(1)}"); // second from top of floating point stack.
3141   default:
3142     return std::string(1, *Constraint);
3143   }
3144 }
3145 } // end anonymous namespace
3146 
3147 namespace {
3148 // X86-32 generic target
3149 class X86_32TargetInfo : public X86TargetInfo {
3150 public:
3151   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3152     DoubleAlign = LongLongAlign = 32;
3153     LongDoubleWidth = 96;
3154     LongDoubleAlign = 32;
3155     SuitableAlign = 128;
3156     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
3157     SizeType = UnsignedInt;
3158     PtrDiffType = SignedInt;
3159     IntPtrType = SignedInt;
3160     RegParmMax = 3;
3161 
3162     // Use fpret for all types.
3163     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3164                              (1 << TargetInfo::Double) |
3165                              (1 << TargetInfo::LongDouble));
3166 
3167     // x86-32 has atomics up to 8 bytes
3168     // FIXME: Check that we actually have cmpxchg8b before setting
3169     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3170     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3171   }
3172   BuiltinVaListKind getBuiltinVaListKind() const override {
3173     return TargetInfo::CharPtrBuiltinVaList;
3174   }
3175 
3176   int getEHDataRegisterNumber(unsigned RegNo) const override {
3177     if (RegNo == 0) return 0;
3178     if (RegNo == 1) return 2;
3179     return -1;
3180   }
3181   bool validateOperandSize(StringRef Constraint,
3182                            unsigned Size) const override {
3183     switch (Constraint[0]) {
3184     default: break;
3185     case 'R':
3186     case 'q':
3187     case 'Q':
3188     case 'a':
3189     case 'b':
3190     case 'c':
3191     case 'd':
3192     case 'S':
3193     case 'D':
3194       return Size <= 32;
3195     case 'A':
3196       return Size <= 64;
3197     }
3198 
3199     return X86TargetInfo::validateOperandSize(Constraint, Size);
3200   }
3201 };
3202 } // end anonymous namespace
3203 
3204 namespace {
3205 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3206 public:
3207   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3208       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3209 
3210   unsigned getFloatEvalMethod() const override {
3211     unsigned Major, Minor, Micro;
3212     getTriple().getOSVersion(Major, Minor, Micro);
3213     // New NetBSD uses the default rounding mode.
3214     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3215       return X86_32TargetInfo::getFloatEvalMethod();
3216     // NetBSD before 6.99.26 defaults to "double" rounding.
3217     return 1;
3218   }
3219 };
3220 } // end anonymous namespace
3221 
3222 namespace {
3223 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3224 public:
3225   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3226       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3227     SizeType = UnsignedLong;
3228     IntPtrType = SignedLong;
3229     PtrDiffType = SignedLong;
3230   }
3231 };
3232 } // end anonymous namespace
3233 
3234 namespace {
3235 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3236 public:
3237   BitrigI386TargetInfo(const llvm::Triple &Triple)
3238       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3239     SizeType = UnsignedLong;
3240     IntPtrType = SignedLong;
3241     PtrDiffType = SignedLong;
3242   }
3243 };
3244 } // end anonymous namespace
3245 
3246 namespace {
3247 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3248 public:
3249   DarwinI386TargetInfo(const llvm::Triple &Triple)
3250       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3251     LongDoubleWidth = 128;
3252     LongDoubleAlign = 128;
3253     SuitableAlign = 128;
3254     MaxVectorAlign = 256;
3255     SizeType = UnsignedLong;
3256     IntPtrType = SignedLong;
3257     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3258     HasAlignMac68kSupport = true;
3259   }
3260 
3261 };
3262 } // end anonymous namespace
3263 
3264 namespace {
3265 // x86-32 Windows target
3266 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3267 public:
3268   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3269       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3270     WCharType = UnsignedShort;
3271     DoubleAlign = LongLongAlign = 64;
3272     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3273   }
3274   void getTargetDefines(const LangOptions &Opts,
3275                         MacroBuilder &Builder) const override {
3276     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3277   }
3278 };
3279 
3280 // x86-32 Windows Visual Studio target
3281 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3282 public:
3283   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3284       : WindowsX86_32TargetInfo(Triple) {
3285     LongDoubleWidth = LongDoubleAlign = 64;
3286     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3287   }
3288   void getTargetDefines(const LangOptions &Opts,
3289                         MacroBuilder &Builder) const override {
3290     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3291     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3292     // The value of the following reflects processor type.
3293     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3294     // We lost the original triple, so we use the default.
3295     Builder.defineMacro("_M_IX86", "600");
3296   }
3297 };
3298 } // end anonymous namespace
3299 
3300 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3301   Builder.defineMacro("__MSVCRT__");
3302   Builder.defineMacro("__MINGW32__");
3303 
3304   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3305   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3306   // macro anyway for pre-processor compatibility.
3307   if (Opts.MicrosoftExt)
3308     Builder.defineMacro("__declspec", "__declspec");
3309   else
3310     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3311 
3312   if (!Opts.MicrosoftExt) {
3313     // Provide macros for all the calling convention keywords.  Provide both
3314     // single and double underscore prefixed variants.  These are available on
3315     // x64 as well as x86, even though they have no effect.
3316     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3317     for (const char *CC : CCs) {
3318       std::string GCCSpelling = "__attribute__((__";
3319       GCCSpelling += CC;
3320       GCCSpelling += "__))";
3321       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3322       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3323     }
3324   }
3325 }
3326 
3327 namespace {
3328 // x86-32 MinGW target
3329 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3330 public:
3331   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3332       : WindowsX86_32TargetInfo(Triple) {}
3333   void getTargetDefines(const LangOptions &Opts,
3334                         MacroBuilder &Builder) const override {
3335     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3336     DefineStd(Builder, "WIN32", Opts);
3337     DefineStd(Builder, "WINNT", Opts);
3338     Builder.defineMacro("_X86_");
3339     addMinGWDefines(Opts, Builder);
3340   }
3341 };
3342 } // end anonymous namespace
3343 
3344 namespace {
3345 // x86-32 Cygwin target
3346 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3347 public:
3348   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3349       : X86_32TargetInfo(Triple) {
3350     TLSSupported = false;
3351     WCharType = UnsignedShort;
3352     DoubleAlign = LongLongAlign = 64;
3353     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3354   }
3355   void getTargetDefines(const LangOptions &Opts,
3356                         MacroBuilder &Builder) const override {
3357     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3358     Builder.defineMacro("_X86_");
3359     Builder.defineMacro("__CYGWIN__");
3360     Builder.defineMacro("__CYGWIN32__");
3361     DefineStd(Builder, "unix", Opts);
3362     if (Opts.CPlusPlus)
3363       Builder.defineMacro("_GNU_SOURCE");
3364   }
3365 };
3366 } // end anonymous namespace
3367 
3368 namespace {
3369 // x86-32 Haiku target
3370 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3371 public:
3372   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3373     SizeType = UnsignedLong;
3374     IntPtrType = SignedLong;
3375     PtrDiffType = SignedLong;
3376     ProcessIDType = SignedLong;
3377     this->UserLabelPrefix = "";
3378     this->TLSSupported = false;
3379   }
3380   void getTargetDefines(const LangOptions &Opts,
3381                         MacroBuilder &Builder) const override {
3382     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3383     Builder.defineMacro("__INTEL__");
3384     Builder.defineMacro("__HAIKU__");
3385   }
3386 };
3387 } // end anonymous namespace
3388 
3389 // RTEMS Target
3390 template<typename Target>
3391 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3392 protected:
3393   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3394                     MacroBuilder &Builder) const override {
3395     // RTEMS defines; list based off of gcc output
3396 
3397     Builder.defineMacro("__rtems__");
3398     Builder.defineMacro("__ELF__");
3399   }
3400 
3401 public:
3402   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3403     this->UserLabelPrefix = "";
3404 
3405     switch (Triple.getArch()) {
3406     default:
3407     case llvm::Triple::x86:
3408       // this->MCountName = ".mcount";
3409       break;
3410     case llvm::Triple::mips:
3411     case llvm::Triple::mipsel:
3412     case llvm::Triple::ppc:
3413     case llvm::Triple::ppc64:
3414     case llvm::Triple::ppc64le:
3415       // this->MCountName = "_mcount";
3416       break;
3417     case llvm::Triple::arm:
3418       // this->MCountName = "__mcount";
3419       break;
3420     }
3421   }
3422 };
3423 
3424 namespace {
3425 // x86-32 RTEMS target
3426 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3427 public:
3428   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3429     SizeType = UnsignedLong;
3430     IntPtrType = SignedLong;
3431     PtrDiffType = SignedLong;
3432     this->UserLabelPrefix = "";
3433   }
3434   void getTargetDefines(const LangOptions &Opts,
3435                         MacroBuilder &Builder) const override {
3436     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3437     Builder.defineMacro("__INTEL__");
3438     Builder.defineMacro("__rtems__");
3439   }
3440 };
3441 } // end anonymous namespace
3442 
3443 namespace {
3444 // x86-64 generic target
3445 class X86_64TargetInfo : public X86TargetInfo {
3446 public:
3447   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3448     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3449     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3450     LongDoubleWidth = 128;
3451     LongDoubleAlign = 128;
3452     LargeArrayMinWidth = 128;
3453     LargeArrayAlign = 128;
3454     SuitableAlign = 128;
3455     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3456     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3457     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3458     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3459     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3460     RegParmMax = 6;
3461 
3462     DescriptionString = (IsX32)
3463                             ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
3464                             : "e-m:e-"            "i64:64-f80:128-n8:16:32:64-S128";
3465 
3466     // Use fpret only for long double.
3467     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3468 
3469     // Use fp2ret for _Complex long double.
3470     ComplexLongDoubleUsesFP2Ret = true;
3471 
3472     // x86-64 has atomics up to 16 bytes.
3473     MaxAtomicPromoteWidth = 128;
3474     MaxAtomicInlineWidth = 128;
3475   }
3476   BuiltinVaListKind getBuiltinVaListKind() const override {
3477     return TargetInfo::X86_64ABIBuiltinVaList;
3478   }
3479 
3480   int getEHDataRegisterNumber(unsigned RegNo) const override {
3481     if (RegNo == 0) return 0;
3482     if (RegNo == 1) return 1;
3483     return -1;
3484   }
3485 
3486   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3487     return (CC == CC_C ||
3488             CC == CC_IntelOclBicc ||
3489             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3490   }
3491 
3492   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3493     return CC_C;
3494   }
3495 
3496   // for x32 we need it here explicitly
3497   bool hasInt128Type() const override { return true; }
3498 };
3499 } // end anonymous namespace
3500 
3501 namespace {
3502 // x86-64 Windows target
3503 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3504 public:
3505   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3506       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3507     WCharType = UnsignedShort;
3508     LongWidth = LongAlign = 32;
3509     DoubleAlign = LongLongAlign = 64;
3510     IntMaxType = SignedLongLong;
3511     Int64Type = SignedLongLong;
3512     SizeType = UnsignedLongLong;
3513     PtrDiffType = SignedLongLong;
3514     IntPtrType = SignedLongLong;
3515     this->UserLabelPrefix = "";
3516   }
3517   void getTargetDefines(const LangOptions &Opts,
3518                                 MacroBuilder &Builder) const override {
3519     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3520     Builder.defineMacro("_WIN64");
3521   }
3522   BuiltinVaListKind getBuiltinVaListKind() const override {
3523     return TargetInfo::CharPtrBuiltinVaList;
3524   }
3525   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3526     return (CC == CC_C ||
3527             CC == CC_IntelOclBicc ||
3528             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3529   }
3530 };
3531 } // end anonymous namespace
3532 
3533 namespace {
3534 // x86-64 Windows Visual Studio target
3535 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3536 public:
3537   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3538       : WindowsX86_64TargetInfo(Triple) {
3539     LongDoubleWidth = LongDoubleAlign = 64;
3540     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3541   }
3542   void getTargetDefines(const LangOptions &Opts,
3543                         MacroBuilder &Builder) const override {
3544     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3545     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3546     Builder.defineMacro("_M_X64");
3547     Builder.defineMacro("_M_AMD64");
3548   }
3549 };
3550 } // end anonymous namespace
3551 
3552 namespace {
3553 // x86-64 MinGW target
3554 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3555 public:
3556   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3557       : WindowsX86_64TargetInfo(Triple) {}
3558   void getTargetDefines(const LangOptions &Opts,
3559                         MacroBuilder &Builder) const override {
3560     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3561     DefineStd(Builder, "WIN64", Opts);
3562     Builder.defineMacro("__MINGW64__");
3563     addMinGWDefines(Opts, Builder);
3564   }
3565 };
3566 } // end anonymous namespace
3567 
3568 namespace {
3569 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3570 public:
3571   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3572       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3573     Int64Type = SignedLongLong;
3574     MaxVectorAlign = 256;
3575     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3576     llvm::Triple T = llvm::Triple(Triple);
3577     if (T.getOS() == llvm::Triple::IOS)
3578       UseSignedCharForObjCBool = false;
3579     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3580   }
3581 };
3582 } // end anonymous namespace
3583 
3584 namespace {
3585 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3586 public:
3587   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3588       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3589     IntMaxType = SignedLongLong;
3590     Int64Type = SignedLongLong;
3591   }
3592 };
3593 } // end anonymous namespace
3594 
3595 namespace {
3596 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3597 public:
3598   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3599       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3600     IntMaxType = SignedLongLong;
3601     Int64Type = SignedLongLong;
3602   }
3603 };
3604 }
3605 
3606 
3607 namespace {
3608 class ARMTargetInfo : public TargetInfo {
3609   // Possible FPU choices.
3610   enum FPUMode {
3611     VFP2FPU = (1 << 0),
3612     VFP3FPU = (1 << 1),
3613     VFP4FPU = (1 << 2),
3614     NeonFPU = (1 << 3),
3615     FPARMV8 = (1 << 4)
3616   };
3617 
3618   // Possible HWDiv features.
3619   enum HWDivMode {
3620     HWDivThumb = (1 << 0),
3621     HWDivARM = (1 << 1)
3622   };
3623 
3624   static bool FPUModeIsVFP(FPUMode Mode) {
3625     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3626   }
3627 
3628   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3629   static const char * const GCCRegNames[];
3630 
3631   std::string ABI, CPU;
3632 
3633   enum {
3634     FP_Default,
3635     FP_VFP,
3636     FP_Neon
3637   } FPMath;
3638 
3639   unsigned FPU : 5;
3640 
3641   unsigned IsAAPCS : 1;
3642   unsigned IsThumb : 1;
3643   unsigned HWDiv : 2;
3644 
3645   // Initialized via features.
3646   unsigned SoftFloat : 1;
3647   unsigned SoftFloatABI : 1;
3648 
3649   unsigned CRC : 1;
3650   unsigned Crypto : 1;
3651 
3652   // ACLE 6.5.1 Hardware floating point
3653   enum {
3654     HW_FP_HP = (1 << 1), /// half (16-bit)
3655     HW_FP_SP = (1 << 2), /// single (32-bit)
3656     HW_FP_DP = (1 << 3), /// double (64-bit)
3657   };
3658   uint32_t HW_FP;
3659 
3660   static const Builtin::Info BuiltinInfo[];
3661 
3662   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3663     StringRef ArchName = T.getArchName();
3664     if (T.getArch() == llvm::Triple::arm ||
3665         T.getArch() == llvm::Triple::armeb) {
3666       StringRef VersionStr;
3667       if (ArchName.startswith("armv"))
3668         VersionStr = ArchName.substr(4, 1);
3669       else if (ArchName.startswith("armebv"))
3670         VersionStr = ArchName.substr(6, 1);
3671       else
3672         return false;
3673       unsigned Version;
3674       if (VersionStr.getAsInteger(10, Version))
3675         return false;
3676       return Version >= 6;
3677     }
3678     assert(T.getArch() == llvm::Triple::thumb ||
3679            T.getArch() == llvm::Triple::thumbeb);
3680     StringRef VersionStr;
3681     if (ArchName.startswith("thumbv"))
3682       VersionStr = ArchName.substr(6, 1);
3683     else if (ArchName.startswith("thumbebv"))
3684       VersionStr = ArchName.substr(8, 1);
3685     else
3686       return false;
3687     unsigned Version;
3688     if (VersionStr.getAsInteger(10, Version))
3689       return false;
3690     return Version >= 7;
3691   }
3692 
3693   void setABIAAPCS() {
3694     IsAAPCS = true;
3695 
3696     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3697     const llvm::Triple &T = getTriple();
3698 
3699     // size_t is unsigned long on MachO-derived environments and NetBSD.
3700     if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD)
3701       SizeType = UnsignedLong;
3702     else
3703       SizeType = UnsignedInt;
3704 
3705     switch (T.getOS()) {
3706     case llvm::Triple::NetBSD:
3707       WCharType = SignedInt;
3708       break;
3709     case llvm::Triple::Win32:
3710       WCharType = UnsignedShort;
3711       break;
3712     case llvm::Triple::Linux:
3713     default:
3714       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3715       WCharType = UnsignedInt;
3716       break;
3717     }
3718 
3719     UseBitFieldTypeAlignment = true;
3720 
3721     ZeroLengthBitfieldBoundary = 0;
3722 
3723     if (IsThumb) {
3724       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3725       // so set preferred for small types to 32.
3726       if (T.isOSBinFormatMachO()) {
3727         DescriptionString = BigEndian ?
3728                               "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3729                               "v128:64:128-a:0:32-n32-S64" :
3730                               "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3731                               "v128:64:128-a:0:32-n32-S64";
3732       } else if (T.isOSWindows()) {
3733         // FIXME: this is invalid for WindowsCE
3734         assert(!BigEndian && "Windows on ARM does not support big endian");
3735         DescriptionString = "e"
3736                             "-m:e"
3737                             "-p:32:32"
3738                             "-i1:8:32-i8:8:32-i16:16:32-i64:64"
3739                             "-v128:64:128"
3740                             "-a:0:32"
3741                             "-n32"
3742                             "-S64";
3743       } else {
3744         DescriptionString = BigEndian ?
3745                               "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3746                               "v128:64:128-a:0:32-n32-S64" :
3747                               "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3748                               "v128:64:128-a:0:32-n32-S64";
3749       }
3750     } else {
3751       if (T.isOSBinFormatMachO())
3752         DescriptionString = BigEndian ?
3753                               "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" :
3754                               "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64";
3755       else
3756         DescriptionString = BigEndian ?
3757                               "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" :
3758                               "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64";
3759     }
3760 
3761     // FIXME: Enumerated types are variable width in straight AAPCS.
3762   }
3763 
3764   void setABIAPCS() {
3765     const llvm::Triple &T = getTriple();
3766 
3767     IsAAPCS = false;
3768 
3769     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3770 
3771     // size_t is unsigned int on FreeBSD.
3772     if (T.getOS() == llvm::Triple::FreeBSD)
3773       SizeType = UnsignedInt;
3774     else
3775       SizeType = UnsignedLong;
3776 
3777     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3778     WCharType = SignedInt;
3779 
3780     // Do not respect the alignment of bit-field types when laying out
3781     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3782     UseBitFieldTypeAlignment = false;
3783 
3784     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3785     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3786     /// gcc.
3787     ZeroLengthBitfieldBoundary = 32;
3788 
3789     if (IsThumb) {
3790       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3791       // so set preferred for small types to 32.
3792       if (T.isOSBinFormatMachO())
3793         DescriptionString = BigEndian ?
3794             "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3795             "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3796             "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3797             "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3798       else
3799         DescriptionString = BigEndian ?
3800             "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3801             "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3802             "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3803             "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3804     } else {
3805       if (T.isOSBinFormatMachO())
3806         DescriptionString = BigEndian ?
3807             "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3808             "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3809       else
3810         DescriptionString = BigEndian ?
3811             "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3812             "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3813     }
3814 
3815     // FIXME: Override "preferred align" for double and long long.
3816   }
3817 
3818 public:
3819   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3820       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3821         IsAAPCS(true), HW_FP(0) {
3822     BigEndian = IsBigEndian;
3823 
3824     switch (getTriple().getOS()) {
3825     case llvm::Triple::NetBSD:
3826       PtrDiffType = SignedLong;
3827       break;
3828     default:
3829       PtrDiffType = SignedInt;
3830       break;
3831     }
3832 
3833     // {} in inline assembly are neon specifiers, not assembly variant
3834     // specifiers.
3835     NoAsmVariants = true;
3836 
3837     // FIXME: Should we just treat this as a feature?
3838     IsThumb = getTriple().getArchName().startswith("thumb");
3839 
3840     setABI("aapcs-linux");
3841 
3842     // ARM targets default to using the ARM C++ ABI.
3843     TheCXXABI.set(TargetCXXABI::GenericARM);
3844 
3845     // ARM has atomics up to 8 bytes
3846     MaxAtomicPromoteWidth = 64;
3847     if (shouldUseInlineAtomic(getTriple()))
3848       MaxAtomicInlineWidth = 64;
3849 
3850     // Do force alignment of members that follow zero length bitfields.  If
3851     // the alignment of the zero-length bitfield is greater than the member
3852     // that follows it, `bar', `bar' will be aligned as the  type of the
3853     // zero length bitfield.
3854     UseZeroLengthBitfieldAlignment = true;
3855   }
3856   StringRef getABI() const override { return ABI; }
3857   bool setABI(const std::string &Name) override {
3858     ABI = Name;
3859 
3860     // The defaults (above) are for AAPCS, check if we need to change them.
3861     //
3862     // FIXME: We need support for -meabi... we could just mangle it into the
3863     // name.
3864     if (Name == "apcs-gnu") {
3865       setABIAPCS();
3866       return true;
3867     }
3868     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3869       setABIAAPCS();
3870       return true;
3871     }
3872     return false;
3873   }
3874 
3875   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3876     if (IsAAPCS)
3877       Features["aapcs"] = true;
3878     else
3879       Features["apcs"] = true;
3880 
3881     StringRef ArchName = getTriple().getArchName();
3882     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3883       Features["vfp2"] = true;
3884     else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3885              CPU == "cortex-a9-mp") {
3886       Features["vfp3"] = true;
3887       Features["neon"] = true;
3888     }
3889     else if (CPU == "cortex-a5") {
3890       Features["vfp4"] = true;
3891       Features["neon"] = true;
3892     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3893                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3894                CPU == "krait") {
3895       Features["vfp4"] = true;
3896       Features["neon"] = true;
3897       Features["hwdiv"] = true;
3898       Features["hwdiv-arm"] = true;
3899     } else if (CPU == "cyclone") {
3900       Features["v8fp"] = true;
3901       Features["neon"] = true;
3902       Features["hwdiv"] = true;
3903       Features["hwdiv-arm"] = true;
3904     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3905       Features["fp-armv8"] = true;
3906       Features["neon"] = true;
3907       Features["hwdiv"] = true;
3908       Features["hwdiv-arm"] = true;
3909       Features["crc"] = true;
3910       Features["crypto"] = true;
3911     } else if (CPU == "cortex-r5" ||
3912                // Enable the hwdiv extension for all v8a AArch32 cores by
3913                // default.
3914                ArchName == "armv8a" || ArchName == "armv8" ||
3915                ArchName == "armebv8a" || ArchName == "armebv8" ||
3916                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3917                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3918       Features["hwdiv"] = true;
3919       Features["hwdiv-arm"] = true;
3920     } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7") {
3921       Features["hwdiv"] = true;
3922     }
3923   }
3924 
3925   bool handleTargetFeatures(std::vector<std::string> &Features,
3926                             DiagnosticsEngine &Diags) override {
3927     FPU = 0;
3928     CRC = 0;
3929     Crypto = 0;
3930     SoftFloat = SoftFloatABI = false;
3931     HWDiv = 0;
3932 
3933     for (const auto &Feature : Features) {
3934       if (Feature == "+soft-float") {
3935         SoftFloat = true;
3936       } else if (Feature == "+soft-float-abi") {
3937         SoftFloatABI = true;
3938       } else if (Feature == "+vfp2") {
3939         FPU |= VFP2FPU;
3940         HW_FP = HW_FP_SP | HW_FP_DP;
3941       } else if (Feature == "+vfp3") {
3942         FPU |= VFP3FPU;
3943         HW_FP = HW_FP_SP | HW_FP_DP;
3944       } else if (Feature == "+vfp4") {
3945         FPU |= VFP4FPU;
3946         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3947       } else if (Feature == "+fp-armv8") {
3948         FPU |= FPARMV8;
3949         HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP;
3950       } else if (Feature == "+neon") {
3951         FPU |= NeonFPU;
3952         HW_FP = HW_FP_SP | HW_FP_DP;
3953       } else if (Feature == "+hwdiv") {
3954         HWDiv |= HWDivThumb;
3955       } else if (Feature == "+hwdiv-arm") {
3956         HWDiv |= HWDivARM;
3957       } else if (Feature == "+crc") {
3958         CRC = 1;
3959       } else if (Feature == "+crypto") {
3960         Crypto = 1;
3961       } else if (Feature == "+fp-only-sp") {
3962         HW_FP &= ~HW_FP_DP;
3963       }
3964     }
3965 
3966     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3967       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3968       return false;
3969     }
3970 
3971     if (FPMath == FP_Neon)
3972       Features.push_back("+neonfp");
3973     else if (FPMath == FP_VFP)
3974       Features.push_back("-neonfp");
3975 
3976     // Remove front-end specific options which the backend handles differently.
3977     const StringRef FrontEndFeatures[] = { "+soft-float", "+soft-float-abi" };
3978     for (const auto &FEFeature : FrontEndFeatures) {
3979       auto Feature = std::find(Features.begin(), Features.end(), FEFeature);
3980       if (Feature != Features.end())
3981         Features.erase(Feature);
3982     }
3983 
3984     return true;
3985   }
3986 
3987   bool hasFeature(StringRef Feature) const override {
3988     return llvm::StringSwitch<bool>(Feature)
3989         .Case("arm", true)
3990         .Case("softfloat", SoftFloat)
3991         .Case("thumb", IsThumb)
3992         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3993         .Case("hwdiv", HWDiv & HWDivThumb)
3994         .Case("hwdiv-arm", HWDiv & HWDivARM)
3995         .Default(false);
3996   }
3997   // FIXME: Should we actually have some table instead of these switches?
3998   static const char *getCPUDefineSuffix(StringRef Name) {
3999     return llvm::StringSwitch<const char*>(Name)
4000       .Cases("arm8", "arm810", "4")
4001       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
4002       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
4003       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
4004       .Case("ep9312", "4T")
4005       .Cases("arm10tdmi", "arm1020t", "5T")
4006       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
4007       .Case("arm926ej-s", "5TEJ")
4008       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
4009       .Cases("xscale", "iwmmxt", "5TE")
4010       .Case("arm1136j-s", "6J")
4011       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
4012       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
4013       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
4014       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
4015       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A")
4016       .Cases("cortex-r4", "cortex-r5", "7R")
4017       .Case("swift", "7S")
4018       .Case("cyclone", "8A")
4019       .Case("cortex-m3", "7M")
4020       .Cases("cortex-m4", "cortex-m7", "7EM")
4021       .Case("cortex-m0", "6M")
4022       .Cases("cortex-a53", "cortex-a57", "8A")
4023       .Default(nullptr);
4024   }
4025   static const char *getCPUProfile(StringRef Name) {
4026     return llvm::StringSwitch<const char*>(Name)
4027       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
4028       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A")
4029       .Cases("cortex-a53", "cortex-a57", "A")
4030       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m7", "M")
4031       .Cases("cortex-r4", "cortex-r5", "R")
4032       .Default("");
4033   }
4034   bool setCPU(const std::string &Name) override {
4035     if (!getCPUDefineSuffix(Name))
4036       return false;
4037 
4038     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
4039     StringRef Profile = getCPUProfile(Name);
4040     if (Profile == "M" && MaxAtomicInlineWidth) {
4041       MaxAtomicPromoteWidth = 32;
4042       MaxAtomicInlineWidth = 32;
4043     }
4044 
4045     CPU = Name;
4046     return true;
4047   }
4048   bool setFPMath(StringRef Name) override;
4049   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
4050                      unsigned CPUArchVer) const {
4051     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
4052            (CPUArch.find('M') != StringRef::npos);
4053   }
4054   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
4055                       unsigned CPUArchVer) const {
4056     // We check both CPUArchVer and ArchName because when only triple is
4057     // specified, the default CPU is arm1136j-s.
4058     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
4059            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
4060   }
4061   void getTargetDefines(const LangOptions &Opts,
4062                         MacroBuilder &Builder) const override {
4063     // Target identification.
4064     Builder.defineMacro("__arm");
4065     Builder.defineMacro("__arm__");
4066 
4067     // Target properties.
4068     Builder.defineMacro("__REGISTER_PREFIX__", "");
4069 
4070     StringRef CPUArch = getCPUDefineSuffix(CPU);
4071     unsigned int CPUArchVer;
4072     if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer))
4073       llvm_unreachable("Invalid char for architecture version number");
4074     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
4075 
4076     // ACLE 6.4.1 ARM/Thumb instruction set architecture
4077     StringRef CPUProfile = getCPUProfile(CPU);
4078     StringRef ArchName = getTriple().getArchName();
4079 
4080     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
4081     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
4082     if (CPUArch[0] >= '8') {
4083       Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4084       Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4085     }
4086 
4087     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
4088     // is not defined for the M-profile.
4089     // NOTE that the deffault profile is assumed to be 'A'
4090     if (CPUProfile.empty() || CPUProfile != "M")
4091       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
4092 
4093     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
4094     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
4095     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
4096     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4097       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
4098     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
4099       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
4100 
4101     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
4102     // instruction set such as ARM or Thumb.
4103     Builder.defineMacro("__ARM_32BIT_STATE", "1");
4104 
4105     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
4106 
4107     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
4108     if (!CPUProfile.empty())
4109       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
4110 
4111     // ACLE 6.5.1 Hardware Floating Point
4112     if (HW_FP)
4113       Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP));
4114 
4115     // ACLE predefines.
4116     Builder.defineMacro("__ARM_ACLE", "200");
4117 
4118     // Subtarget options.
4119 
4120     // FIXME: It's more complicated than this and we don't really support
4121     // interworking.
4122     // Windows on ARM does not "support" interworking
4123     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
4124       Builder.defineMacro("__THUMB_INTERWORK__");
4125 
4126     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
4127       // Embedded targets on Darwin follow AAPCS, but not EABI.
4128       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
4129       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
4130         Builder.defineMacro("__ARM_EABI__");
4131       Builder.defineMacro("__ARM_PCS", "1");
4132 
4133       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
4134         Builder.defineMacro("__ARM_PCS_VFP", "1");
4135     }
4136 
4137     if (SoftFloat)
4138       Builder.defineMacro("__SOFTFP__");
4139 
4140     if (CPU == "xscale")
4141       Builder.defineMacro("__XSCALE__");
4142 
4143     if (IsThumb) {
4144       Builder.defineMacro("__THUMBEL__");
4145       Builder.defineMacro("__thumb__");
4146       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
4147         Builder.defineMacro("__thumb2__");
4148     }
4149     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
4150       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
4151 
4152     // Note, this is always on in gcc, even though it doesn't make sense.
4153     Builder.defineMacro("__APCS_32__");
4154 
4155     if (FPUModeIsVFP((FPUMode) FPU)) {
4156       Builder.defineMacro("__VFP_FP__");
4157       if (FPU & VFP2FPU)
4158         Builder.defineMacro("__ARM_VFPV2__");
4159       if (FPU & VFP3FPU)
4160         Builder.defineMacro("__ARM_VFPV3__");
4161       if (FPU & VFP4FPU)
4162         Builder.defineMacro("__ARM_VFPV4__");
4163     }
4164 
4165     // This only gets set when Neon instructions are actually available, unlike
4166     // the VFP define, hence the soft float and arch check. This is subtly
4167     // different from gcc, we follow the intent which was that it should be set
4168     // when Neon instructions are actually available.
4169     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
4170       Builder.defineMacro("__ARM_NEON");
4171       Builder.defineMacro("__ARM_NEON__");
4172     }
4173 
4174     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
4175                         Opts.ShortWChar ? "2" : "4");
4176 
4177     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4178                         Opts.ShortEnums ? "1" : "4");
4179 
4180     if (CRC)
4181       Builder.defineMacro("__ARM_FEATURE_CRC32");
4182 
4183     if (Crypto)
4184       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4185 
4186     if (CPUArchVer >= 6 && CPUArch != "6M") {
4187       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
4188       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
4189       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
4190       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
4191     }
4192   }
4193   void getTargetBuiltins(const Builtin::Info *&Records,
4194                          unsigned &NumRecords) const override {
4195     Records = BuiltinInfo;
4196     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4197   }
4198   bool isCLZForZeroUndef() const override { return false; }
4199   BuiltinVaListKind getBuiltinVaListKind() const override {
4200     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4201   }
4202   void getGCCRegNames(const char * const *&Names,
4203                       unsigned &NumNames) const override;
4204   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4205                         unsigned &NumAliases) const override;
4206   bool validateAsmConstraint(const char *&Name,
4207                              TargetInfo::ConstraintInfo &Info) const override {
4208     switch (*Name) {
4209     default: break;
4210     case 'l': // r0-r7
4211     case 'h': // r8-r15
4212     case 'w': // VFP Floating point register single precision
4213     case 'P': // VFP Floating point register double precision
4214       Info.setAllowsRegister();
4215       return true;
4216     case 'Q': // A memory address that is a single base register.
4217       Info.setAllowsMemory();
4218       return true;
4219     case 'U': // a memory reference...
4220       switch (Name[1]) {
4221       case 'q': // ...ARMV4 ldrsb
4222       case 'v': // ...VFP load/store (reg+constant offset)
4223       case 'y': // ...iWMMXt load/store
4224       case 't': // address valid for load/store opaque types wider
4225                 // than 128-bits
4226       case 'n': // valid address for Neon doubleword vector load/store
4227       case 'm': // valid address for Neon element and structure load/store
4228       case 's': // valid address for non-offset loads/stores of quad-word
4229                 // values in four ARM registers
4230         Info.setAllowsMemory();
4231         Name++;
4232         return true;
4233       }
4234     }
4235     return false;
4236   }
4237   std::string convertConstraint(const char *&Constraint) const override {
4238     std::string R;
4239     switch (*Constraint) {
4240     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4241       R = std::string("^") + std::string(Constraint, 2);
4242       Constraint++;
4243       break;
4244     case 'p': // 'p' should be translated to 'r' by default.
4245       R = std::string("r");
4246       break;
4247     default:
4248       return std::string(1, *Constraint);
4249     }
4250     return R;
4251   }
4252   bool
4253   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4254                              std::string &SuggestedModifier) const override {
4255     bool isOutput = (Constraint[0] == '=');
4256     bool isInOut = (Constraint[0] == '+');
4257 
4258     // Strip off constraint modifiers.
4259     while (Constraint[0] == '=' ||
4260            Constraint[0] == '+' ||
4261            Constraint[0] == '&')
4262       Constraint = Constraint.substr(1);
4263 
4264     switch (Constraint[0]) {
4265     default: break;
4266     case 'r': {
4267       switch (Modifier) {
4268       default:
4269         return (isInOut || isOutput || Size <= 64);
4270       case 'q':
4271         // A register of size 32 cannot fit a vector type.
4272         return false;
4273       }
4274     }
4275     }
4276 
4277     return true;
4278   }
4279   const char *getClobbers() const override {
4280     // FIXME: Is this really right?
4281     return "";
4282   }
4283 
4284   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4285     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4286   }
4287 
4288   int getEHDataRegisterNumber(unsigned RegNo) const override {
4289     if (RegNo == 0) return 0;
4290     if (RegNo == 1) return 1;
4291     return -1;
4292   }
4293 };
4294 
4295 bool ARMTargetInfo::setFPMath(StringRef Name) {
4296   if (Name == "neon") {
4297     FPMath = FP_Neon;
4298     return true;
4299   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4300              Name == "vfp4") {
4301     FPMath = FP_VFP;
4302     return true;
4303   }
4304   return false;
4305 }
4306 
4307 const char * const ARMTargetInfo::GCCRegNames[] = {
4308   // Integer registers
4309   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4310   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4311 
4312   // Float registers
4313   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4314   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4315   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4316   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4317 
4318   // Double registers
4319   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4320   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4321   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4322   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4323 
4324   // Quad registers
4325   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4326   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4327 };
4328 
4329 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4330                                    unsigned &NumNames) const {
4331   Names = GCCRegNames;
4332   NumNames = llvm::array_lengthof(GCCRegNames);
4333 }
4334 
4335 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4336   { { "a1" }, "r0" },
4337   { { "a2" }, "r1" },
4338   { { "a3" }, "r2" },
4339   { { "a4" }, "r3" },
4340   { { "v1" }, "r4" },
4341   { { "v2" }, "r5" },
4342   { { "v3" }, "r6" },
4343   { { "v4" }, "r7" },
4344   { { "v5" }, "r8" },
4345   { { "v6", "rfp" }, "r9" },
4346   { { "sl" }, "r10" },
4347   { { "fp" }, "r11" },
4348   { { "ip" }, "r12" },
4349   { { "r13" }, "sp" },
4350   { { "r14" }, "lr" },
4351   { { "r15" }, "pc" },
4352   // The S, D and Q registers overlap, but aren't really aliases; we
4353   // don't want to substitute one of these for a different-sized one.
4354 };
4355 
4356 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4357                                        unsigned &NumAliases) const {
4358   Aliases = GCCRegAliases;
4359   NumAliases = llvm::array_lengthof(GCCRegAliases);
4360 }
4361 
4362 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4363 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4364 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4365                                               ALL_LANGUAGES },
4366 #include "clang/Basic/BuiltinsNEON.def"
4367 
4368 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4369 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4370 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4371                                               ALL_LANGUAGES },
4372 #include "clang/Basic/BuiltinsARM.def"
4373 };
4374 
4375 class ARMleTargetInfo : public ARMTargetInfo {
4376 public:
4377   ARMleTargetInfo(const llvm::Triple &Triple)
4378     : ARMTargetInfo(Triple, false) { }
4379   virtual void getTargetDefines(const LangOptions &Opts,
4380                                 MacroBuilder &Builder) const {
4381     Builder.defineMacro("__ARMEL__");
4382     ARMTargetInfo::getTargetDefines(Opts, Builder);
4383   }
4384 };
4385 
4386 class ARMbeTargetInfo : public ARMTargetInfo {
4387 public:
4388   ARMbeTargetInfo(const llvm::Triple &Triple)
4389     : ARMTargetInfo(Triple, true) { }
4390   virtual void getTargetDefines(const LangOptions &Opts,
4391                                 MacroBuilder &Builder) const {
4392     Builder.defineMacro("__ARMEB__");
4393     Builder.defineMacro("__ARM_BIG_ENDIAN");
4394     ARMTargetInfo::getTargetDefines(Opts, Builder);
4395   }
4396 };
4397 } // end anonymous namespace.
4398 
4399 namespace {
4400 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4401   const llvm::Triple Triple;
4402 public:
4403   WindowsARMTargetInfo(const llvm::Triple &Triple)
4404     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4405     TLSSupported = false;
4406     WCharType = UnsignedShort;
4407     SizeType = UnsignedInt;
4408     UserLabelPrefix = "";
4409   }
4410   void getVisualStudioDefines(const LangOptions &Opts,
4411                               MacroBuilder &Builder) const {
4412     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4413 
4414     // FIXME: this is invalid for WindowsCE
4415     Builder.defineMacro("_M_ARM_NT", "1");
4416     Builder.defineMacro("_M_ARMT", "_M_ARM");
4417     Builder.defineMacro("_M_THUMB", "_M_ARM");
4418 
4419     assert((Triple.getArch() == llvm::Triple::arm ||
4420             Triple.getArch() == llvm::Triple::thumb) &&
4421            "invalid architecture for Windows ARM target info");
4422     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4423     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4424 
4425     // TODO map the complete set of values
4426     // 31: VFPv3 40: VFPv4
4427     Builder.defineMacro("_M_ARM_FP", "31");
4428   }
4429   BuiltinVaListKind getBuiltinVaListKind() const override {
4430     return TargetInfo::CharPtrBuiltinVaList;
4431   }
4432 };
4433 
4434 // Windows ARM + Itanium C++ ABI Target
4435 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4436 public:
4437   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4438     : WindowsARMTargetInfo(Triple) {
4439     TheCXXABI.set(TargetCXXABI::GenericARM);
4440   }
4441 
4442   void getTargetDefines(const LangOptions &Opts,
4443                         MacroBuilder &Builder) const override {
4444     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4445 
4446     if (Opts.MSVCCompat)
4447       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4448   }
4449 };
4450 
4451 // Windows ARM, MS (C++) ABI
4452 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4453 public:
4454   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4455     : WindowsARMTargetInfo(Triple) {
4456     TheCXXABI.set(TargetCXXABI::Microsoft);
4457   }
4458 
4459   void getTargetDefines(const LangOptions &Opts,
4460                         MacroBuilder &Builder) const override {
4461     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4462     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4463   }
4464 };
4465 }
4466 
4467 
4468 namespace {
4469 class DarwinARMTargetInfo :
4470   public DarwinTargetInfo<ARMleTargetInfo> {
4471 protected:
4472   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4473                     MacroBuilder &Builder) const override {
4474     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4475   }
4476 
4477 public:
4478   DarwinARMTargetInfo(const llvm::Triple &Triple)
4479       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4480     HasAlignMac68kSupport = true;
4481     // iOS always has 64-bit atomic instructions.
4482     // FIXME: This should be based off of the target features in ARMleTargetInfo.
4483     MaxAtomicInlineWidth = 64;
4484 
4485     // Darwin on iOS uses a variant of the ARM C++ ABI.
4486     TheCXXABI.set(TargetCXXABI::iOS);
4487   }
4488 };
4489 } // end anonymous namespace.
4490 
4491 
4492 namespace {
4493 class AArch64TargetInfo : public TargetInfo {
4494   virtual void setDescriptionString() = 0;
4495   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4496   static const char *const GCCRegNames[];
4497 
4498   enum FPUModeEnum {
4499     FPUMode,
4500     NeonMode
4501   };
4502 
4503   unsigned FPU;
4504   unsigned CRC;
4505   unsigned Crypto;
4506 
4507   static const Builtin::Info BuiltinInfo[];
4508 
4509   std::string ABI;
4510 
4511 public:
4512   AArch64TargetInfo(const llvm::Triple &Triple)
4513       : TargetInfo(Triple), ABI("aapcs") {
4514 
4515     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4516       WCharType = SignedInt;
4517 
4518       // NetBSD apparently prefers consistency across ARM targets to consistency
4519       // across 64-bit targets.
4520       Int64Type = SignedLongLong;
4521       IntMaxType = SignedLongLong;
4522     } else {
4523       WCharType = UnsignedInt;
4524       Int64Type = SignedLong;
4525       IntMaxType = SignedLong;
4526     }
4527 
4528     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4529     MaxVectorAlign = 128;
4530     RegParmMax = 8;
4531     MaxAtomicInlineWidth = 128;
4532     MaxAtomicPromoteWidth = 128;
4533 
4534     LongDoubleWidth = LongDoubleAlign = 128;
4535     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4536 
4537     // {} in inline assembly are neon specifiers, not assembly variant
4538     // specifiers.
4539     NoAsmVariants = true;
4540 
4541     // AArch64 targets default to using the ARM C++ ABI.
4542     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4543   }
4544 
4545   StringRef getABI() const override { return ABI; }
4546   virtual bool setABI(const std::string &Name) override {
4547     if (Name != "aapcs" && Name != "darwinpcs")
4548       return false;
4549 
4550     ABI = Name;
4551     return true;
4552   }
4553 
4554   virtual bool setCPU(const std::string &Name) override {
4555     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4556                         .Case("generic", true)
4557                         .Cases("cortex-a53", "cortex-a57", true)
4558                         .Case("cyclone", true)
4559                         .Default(false);
4560     return CPUKnown;
4561   }
4562 
4563   virtual void getTargetDefines(const LangOptions &Opts,
4564                                 MacroBuilder &Builder) const  override {
4565     // Target identification.
4566     Builder.defineMacro("__aarch64__");
4567 
4568     // Target properties.
4569     Builder.defineMacro("_LP64");
4570     Builder.defineMacro("__LP64__");
4571 
4572     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4573     Builder.defineMacro("__ARM_ACLE", "200");
4574     Builder.defineMacro("__ARM_ARCH", "8");
4575     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4576 
4577     Builder.defineMacro("__ARM_64BIT_STATE");
4578     Builder.defineMacro("__ARM_PCS_AAPCS64");
4579     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4580 
4581     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4582     Builder.defineMacro("__ARM_FEATURE_CLZ");
4583     Builder.defineMacro("__ARM_FEATURE_FMA");
4584     Builder.defineMacro("__ARM_FEATURE_DIV");
4585     Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE
4586     Builder.defineMacro("__ARM_FEATURE_DIV");  // For backwards compatibility
4587     Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN");
4588     Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING");
4589 
4590     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4591 
4592     // 0xe implies support for half, single and double precision operations.
4593     Builder.defineMacro("__ARM_FP", "0xe");
4594 
4595     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4596     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4597     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4598 
4599     if (Opts.FastMath || Opts.FiniteMathOnly)
4600       Builder.defineMacro("__ARM_FP_FAST");
4601 
4602     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
4603       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4604 
4605     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4606 
4607     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4608                         Opts.ShortEnums ? "1" : "4");
4609 
4610     if (FPU == NeonMode) {
4611       Builder.defineMacro("__ARM_NEON");
4612       // 64-bit NEON supports half, single and double precision operations.
4613       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4614     }
4615 
4616     if (CRC)
4617       Builder.defineMacro("__ARM_FEATURE_CRC32");
4618 
4619     if (Crypto)
4620       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4621   }
4622 
4623   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4624                                  unsigned &NumRecords) const override {
4625     Records = BuiltinInfo;
4626     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4627   }
4628 
4629   virtual bool hasFeature(StringRef Feature) const override {
4630     return Feature == "aarch64" ||
4631       Feature == "arm64" ||
4632       (Feature == "neon" && FPU == NeonMode);
4633   }
4634 
4635   bool handleTargetFeatures(std::vector<std::string> &Features,
4636                             DiagnosticsEngine &Diags) override {
4637     FPU = FPUMode;
4638     CRC = 0;
4639     Crypto = 0;
4640     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4641       if (Features[i] == "+neon")
4642         FPU = NeonMode;
4643       if (Features[i] == "+crc")
4644         CRC = 1;
4645       if (Features[i] == "+crypto")
4646         Crypto = 1;
4647     }
4648 
4649     setDescriptionString();
4650 
4651     return true;
4652   }
4653 
4654   virtual bool isCLZForZeroUndef() const override { return false; }
4655 
4656   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4657     return TargetInfo::AArch64ABIBuiltinVaList;
4658   }
4659 
4660   virtual void getGCCRegNames(const char *const *&Names,
4661                               unsigned &NumNames) const override;
4662   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4663                                 unsigned &NumAliases) const override;
4664 
4665   virtual bool validateAsmConstraint(const char *&Name,
4666                                      TargetInfo::ConstraintInfo &Info) const override {
4667     switch (*Name) {
4668     default:
4669       return false;
4670     case 'w': // Floating point and SIMD registers (V0-V31)
4671       Info.setAllowsRegister();
4672       return true;
4673     case 'I': // Constant that can be used with an ADD instruction
4674     case 'J': // Constant that can be used with a SUB instruction
4675     case 'K': // Constant that can be used with a 32-bit logical instruction
4676     case 'L': // Constant that can be used with a 64-bit logical instruction
4677     case 'M': // Constant that can be used as a 32-bit MOV immediate
4678     case 'N': // Constant that can be used as a 64-bit MOV immediate
4679     case 'Y': // Floating point constant zero
4680     case 'Z': // Integer constant zero
4681       return true;
4682     case 'Q': // A memory reference with base register and no offset
4683       Info.setAllowsMemory();
4684       return true;
4685     case 'S': // A symbolic address
4686       Info.setAllowsRegister();
4687       return true;
4688     case 'U':
4689       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
4690       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4691       // Usa: An absolute symbolic address
4692       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4693       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
4694     case 'z': // Zero register, wzr or xzr
4695       Info.setAllowsRegister();
4696       return true;
4697     case 'x': // Floating point and SIMD registers (V0-V15)
4698       Info.setAllowsRegister();
4699       return true;
4700     }
4701     return false;
4702   }
4703 
4704   bool
4705   validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size,
4706                              std::string &SuggestedModifier) const override {
4707     // Strip off constraint modifiers.
4708     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4709       Constraint = Constraint.substr(1);
4710 
4711     switch (Constraint[0]) {
4712     default:
4713       return true;
4714     case 'z':
4715     case 'r': {
4716       switch (Modifier) {
4717       case 'x':
4718       case 'w':
4719         // For now assume that the person knows what they're
4720         // doing with the modifier.
4721         return true;
4722       default:
4723         // By default an 'r' constraint will be in the 'x'
4724         // registers.
4725         if (Size == 64)
4726           return true;
4727 
4728         SuggestedModifier = "w";
4729         return false;
4730       }
4731     }
4732     }
4733   }
4734 
4735   virtual const char *getClobbers() const override { return ""; }
4736 
4737   int getEHDataRegisterNumber(unsigned RegNo) const override {
4738     if (RegNo == 0)
4739       return 0;
4740     if (RegNo == 1)
4741       return 1;
4742     return -1;
4743   }
4744 };
4745 
4746 const char *const AArch64TargetInfo::GCCRegNames[] = {
4747   // 32-bit Integer registers
4748   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4749   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4750   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4751 
4752   // 64-bit Integer registers
4753   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4754   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4755   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4756 
4757   // 32-bit floating point regsisters
4758   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4759   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4760   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4761 
4762   // 64-bit floating point regsisters
4763   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4764   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4765   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4766 
4767   // Vector registers
4768   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4769   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4770   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4771 };
4772 
4773 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4774                                      unsigned &NumNames) const {
4775   Names = GCCRegNames;
4776   NumNames = llvm::array_lengthof(GCCRegNames);
4777 }
4778 
4779 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4780   { { "w31" }, "wsp" },
4781   { { "x29" }, "fp" },
4782   { { "x30" }, "lr" },
4783   { { "x31" }, "sp" },
4784   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4785   // don't want to substitute one of these for a different-sized one.
4786 };
4787 
4788 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4789                                        unsigned &NumAliases) const {
4790   Aliases = GCCRegAliases;
4791   NumAliases = llvm::array_lengthof(GCCRegAliases);
4792 }
4793 
4794 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4795 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4796   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4797 #include "clang/Basic/BuiltinsNEON.def"
4798 
4799 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4800   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4801 #include "clang/Basic/BuiltinsAArch64.def"
4802 };
4803 
4804 class AArch64leTargetInfo : public AArch64TargetInfo {
4805   void setDescriptionString() override {
4806     if (getTriple().isOSBinFormatMachO())
4807       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4808     else
4809       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4810   }
4811 
4812 public:
4813   AArch64leTargetInfo(const llvm::Triple &Triple)
4814     : AArch64TargetInfo(Triple) {
4815     BigEndian = false;
4816     }
4817   void getTargetDefines(const LangOptions &Opts,
4818                         MacroBuilder &Builder) const override {
4819     Builder.defineMacro("__AARCH64EL__");
4820     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4821   }
4822 };
4823 
4824 class AArch64beTargetInfo : public AArch64TargetInfo {
4825   void setDescriptionString() override {
4826     assert(!getTriple().isOSBinFormatMachO());
4827     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4828   }
4829 
4830 public:
4831   AArch64beTargetInfo(const llvm::Triple &Triple)
4832     : AArch64TargetInfo(Triple) { }
4833   void getTargetDefines(const LangOptions &Opts,
4834                         MacroBuilder &Builder) const override {
4835     Builder.defineMacro("__AARCH64EB__");
4836     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4837     Builder.defineMacro("__ARM_BIG_ENDIAN");
4838     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4839   }
4840 };
4841 } // end anonymous namespace.
4842 
4843 namespace {
4844 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4845 protected:
4846   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4847                     MacroBuilder &Builder) const override {
4848     Builder.defineMacro("__AARCH64_SIMD__");
4849     Builder.defineMacro("__ARM64_ARCH_8__");
4850     Builder.defineMacro("__ARM_NEON__");
4851     Builder.defineMacro("__LITTLE_ENDIAN__");
4852     Builder.defineMacro("__REGISTER_PREFIX__", "");
4853     Builder.defineMacro("__arm64", "1");
4854     Builder.defineMacro("__arm64__", "1");
4855 
4856     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4857   }
4858 
4859 public:
4860   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4861       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4862     Int64Type = SignedLongLong;
4863     WCharType = SignedInt;
4864     UseSignedCharForObjCBool = false;
4865 
4866     LongDoubleWidth = LongDoubleAlign = 64;
4867     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4868 
4869     TheCXXABI.set(TargetCXXABI::iOS64);
4870   }
4871 
4872   virtual BuiltinVaListKind getBuiltinVaListKind() const override {
4873     return TargetInfo::CharPtrBuiltinVaList;
4874   }
4875 };
4876 } // end anonymous namespace
4877 
4878 namespace {
4879 // Hexagon abstract base class
4880 class HexagonTargetInfo : public TargetInfo {
4881   static const Builtin::Info BuiltinInfo[];
4882   static const char * const GCCRegNames[];
4883   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4884   std::string CPU;
4885 public:
4886   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4887     BigEndian = false;
4888     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4889 
4890     // {} in inline assembly are packet specifiers, not assembly variant
4891     // specifiers.
4892     NoAsmVariants = true;
4893   }
4894 
4895   void getTargetBuiltins(const Builtin::Info *&Records,
4896                          unsigned &NumRecords) const override {
4897     Records = BuiltinInfo;
4898     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4899   }
4900 
4901   bool validateAsmConstraint(const char *&Name,
4902                              TargetInfo::ConstraintInfo &Info) const override {
4903     return true;
4904   }
4905 
4906   void getTargetDefines(const LangOptions &Opts,
4907                         MacroBuilder &Builder) const override;
4908 
4909   bool hasFeature(StringRef Feature) const override {
4910     return Feature == "hexagon";
4911   }
4912 
4913   BuiltinVaListKind getBuiltinVaListKind() const override {
4914     return TargetInfo::CharPtrBuiltinVaList;
4915   }
4916   void getGCCRegNames(const char * const *&Names,
4917                       unsigned &NumNames) const override;
4918   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4919                         unsigned &NumAliases) const override;
4920   const char *getClobbers() const override {
4921     return "";
4922   }
4923 
4924   static const char *getHexagonCPUSuffix(StringRef Name) {
4925     return llvm::StringSwitch<const char*>(Name)
4926       .Case("hexagonv4", "4")
4927       .Case("hexagonv5", "5")
4928       .Default(nullptr);
4929   }
4930 
4931   bool setCPU(const std::string &Name) override {
4932     if (!getHexagonCPUSuffix(Name))
4933       return false;
4934 
4935     CPU = Name;
4936     return true;
4937   }
4938 };
4939 
4940 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4941                                 MacroBuilder &Builder) const {
4942   Builder.defineMacro("qdsp6");
4943   Builder.defineMacro("__qdsp6", "1");
4944   Builder.defineMacro("__qdsp6__", "1");
4945 
4946   Builder.defineMacro("hexagon");
4947   Builder.defineMacro("__hexagon", "1");
4948   Builder.defineMacro("__hexagon__", "1");
4949 
4950   if(CPU == "hexagonv1") {
4951     Builder.defineMacro("__HEXAGON_V1__");
4952     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4953     if(Opts.HexagonQdsp6Compat) {
4954       Builder.defineMacro("__QDSP6_V1__");
4955       Builder.defineMacro("__QDSP6_ARCH__", "1");
4956     }
4957   }
4958   else if(CPU == "hexagonv2") {
4959     Builder.defineMacro("__HEXAGON_V2__");
4960     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4961     if(Opts.HexagonQdsp6Compat) {
4962       Builder.defineMacro("__QDSP6_V2__");
4963       Builder.defineMacro("__QDSP6_ARCH__", "2");
4964     }
4965   }
4966   else if(CPU == "hexagonv3") {
4967     Builder.defineMacro("__HEXAGON_V3__");
4968     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4969     if(Opts.HexagonQdsp6Compat) {
4970       Builder.defineMacro("__QDSP6_V3__");
4971       Builder.defineMacro("__QDSP6_ARCH__", "3");
4972     }
4973   }
4974   else if(CPU == "hexagonv4") {
4975     Builder.defineMacro("__HEXAGON_V4__");
4976     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4977     if(Opts.HexagonQdsp6Compat) {
4978       Builder.defineMacro("__QDSP6_V4__");
4979       Builder.defineMacro("__QDSP6_ARCH__", "4");
4980     }
4981   }
4982   else if(CPU == "hexagonv5") {
4983     Builder.defineMacro("__HEXAGON_V5__");
4984     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4985     if(Opts.HexagonQdsp6Compat) {
4986       Builder.defineMacro("__QDSP6_V5__");
4987       Builder.defineMacro("__QDSP6_ARCH__", "5");
4988     }
4989   }
4990 }
4991 
4992 const char * const HexagonTargetInfo::GCCRegNames[] = {
4993   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4994   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4995   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4996   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4997   "p0", "p1", "p2", "p3",
4998   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4999 };
5000 
5001 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
5002                                    unsigned &NumNames) const {
5003   Names = GCCRegNames;
5004   NumNames = llvm::array_lengthof(GCCRegNames);
5005 }
5006 
5007 
5008 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
5009   { { "sp" }, "r29" },
5010   { { "fp" }, "r30" },
5011   { { "lr" }, "r31" },
5012  };
5013 
5014 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5015                                      unsigned &NumAliases) const {
5016   Aliases = GCCRegAliases;
5017   NumAliases = llvm::array_lengthof(GCCRegAliases);
5018 }
5019 
5020 
5021 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
5022 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5023 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5024                                               ALL_LANGUAGES },
5025 #include "clang/Basic/BuiltinsHexagon.def"
5026 };
5027 }
5028 
5029 
5030 namespace {
5031 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
5032 class SparcTargetInfo : public TargetInfo {
5033   static const TargetInfo::GCCRegAlias GCCRegAliases[];
5034   static const char * const GCCRegNames[];
5035   bool SoftFloat;
5036 public:
5037   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
5038 
5039   bool handleTargetFeatures(std::vector<std::string> &Features,
5040                             DiagnosticsEngine &Diags) override {
5041     SoftFloat = false;
5042     for (unsigned i = 0, e = Features.size(); i != e; ++i)
5043       if (Features[i] == "+soft-float")
5044         SoftFloat = true;
5045     return true;
5046   }
5047   void getTargetDefines(const LangOptions &Opts,
5048                         MacroBuilder &Builder) const override {
5049     DefineStd(Builder, "sparc", Opts);
5050     Builder.defineMacro("__REGISTER_PREFIX__", "");
5051 
5052     if (SoftFloat)
5053       Builder.defineMacro("SOFT_FLOAT", "1");
5054   }
5055 
5056   bool hasFeature(StringRef Feature) const override {
5057     return llvm::StringSwitch<bool>(Feature)
5058              .Case("softfloat", SoftFloat)
5059              .Case("sparc", true)
5060              .Default(false);
5061   }
5062 
5063   void getTargetBuiltins(const Builtin::Info *&Records,
5064                          unsigned &NumRecords) const override {
5065     // FIXME: Implement!
5066   }
5067   BuiltinVaListKind getBuiltinVaListKind() const override {
5068     return TargetInfo::VoidPtrBuiltinVaList;
5069   }
5070   void getGCCRegNames(const char * const *&Names,
5071                       unsigned &NumNames) const override;
5072   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5073                         unsigned &NumAliases) const override;
5074   bool validateAsmConstraint(const char *&Name,
5075                              TargetInfo::ConstraintInfo &info) const override {
5076     // FIXME: Implement!
5077     return false;
5078   }
5079   const char *getClobbers() const override {
5080     // FIXME: Implement!
5081     return "";
5082   }
5083 };
5084 
5085 const char * const SparcTargetInfo::GCCRegNames[] = {
5086   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5087   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
5088   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
5089   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
5090 };
5091 
5092 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
5093                                      unsigned &NumNames) const {
5094   Names = GCCRegNames;
5095   NumNames = llvm::array_lengthof(GCCRegNames);
5096 }
5097 
5098 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
5099   { { "g0" }, "r0" },
5100   { { "g1" }, "r1" },
5101   { { "g2" }, "r2" },
5102   { { "g3" }, "r3" },
5103   { { "g4" }, "r4" },
5104   { { "g5" }, "r5" },
5105   { { "g6" }, "r6" },
5106   { { "g7" }, "r7" },
5107   { { "o0" }, "r8" },
5108   { { "o1" }, "r9" },
5109   { { "o2" }, "r10" },
5110   { { "o3" }, "r11" },
5111   { { "o4" }, "r12" },
5112   { { "o5" }, "r13" },
5113   { { "o6", "sp" }, "r14" },
5114   { { "o7" }, "r15" },
5115   { { "l0" }, "r16" },
5116   { { "l1" }, "r17" },
5117   { { "l2" }, "r18" },
5118   { { "l3" }, "r19" },
5119   { { "l4" }, "r20" },
5120   { { "l5" }, "r21" },
5121   { { "l6" }, "r22" },
5122   { { "l7" }, "r23" },
5123   { { "i0" }, "r24" },
5124   { { "i1" }, "r25" },
5125   { { "i2" }, "r26" },
5126   { { "i3" }, "r27" },
5127   { { "i4" }, "r28" },
5128   { { "i5" }, "r29" },
5129   { { "i6", "fp" }, "r30" },
5130   { { "i7" }, "r31" },
5131 };
5132 
5133 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5134                                        unsigned &NumAliases) const {
5135   Aliases = GCCRegAliases;
5136   NumAliases = llvm::array_lengthof(GCCRegAliases);
5137 }
5138 
5139 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
5140 class SparcV8TargetInfo : public SparcTargetInfo {
5141 public:
5142   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5143     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
5144   }
5145 
5146   void getTargetDefines(const LangOptions &Opts,
5147                         MacroBuilder &Builder) const override {
5148     SparcTargetInfo::getTargetDefines(Opts, Builder);
5149     Builder.defineMacro("__sparcv8");
5150   }
5151 };
5152 
5153 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
5154 class SparcV9TargetInfo : public SparcTargetInfo {
5155 public:
5156   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
5157     // FIXME: Support Sparc quad-precision long double?
5158     DescriptionString = "E-m:e-i64:64-n32:64-S128";
5159     // This is an LP64 platform.
5160     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
5161 
5162     // OpenBSD uses long long for int64_t and intmax_t.
5163     if (getTriple().getOS() == llvm::Triple::OpenBSD)
5164       IntMaxType = SignedLongLong;
5165     else
5166       IntMaxType = SignedLong;
5167     Int64Type = IntMaxType;
5168 
5169     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
5170     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
5171     LongDoubleWidth = 128;
5172     LongDoubleAlign = 128;
5173     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5174     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5175   }
5176 
5177   void getTargetDefines(const LangOptions &Opts,
5178                         MacroBuilder &Builder) const override {
5179     SparcTargetInfo::getTargetDefines(Opts, Builder);
5180     Builder.defineMacro("__sparcv9");
5181     Builder.defineMacro("__arch64__");
5182     // Solaris doesn't need these variants, but the BSDs do.
5183     if (getTriple().getOS() != llvm::Triple::Solaris) {
5184       Builder.defineMacro("__sparc64__");
5185       Builder.defineMacro("__sparc_v9__");
5186       Builder.defineMacro("__sparcv9__");
5187     }
5188   }
5189 
5190   bool setCPU(const std::string &Name) override {
5191     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5192       .Case("v9", true)
5193       .Case("ultrasparc", true)
5194       .Case("ultrasparc3", true)
5195       .Case("niagara", true)
5196       .Case("niagara2", true)
5197       .Case("niagara3", true)
5198       .Case("niagara4", true)
5199       .Default(false);
5200 
5201     // No need to store the CPU yet.  There aren't any CPU-specific
5202     // macros to define.
5203     return CPUKnown;
5204   }
5205 };
5206 
5207 } // end anonymous namespace.
5208 
5209 namespace {
5210 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5211 public:
5212   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5213       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5214     SizeType = UnsignedInt;
5215     PtrDiffType = SignedInt;
5216   }
5217 };
5218 } // end anonymous namespace.
5219 
5220 namespace {
5221 class SystemZTargetInfo : public TargetInfo {
5222   static const char *const GCCRegNames[];
5223 
5224 public:
5225   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5226     TLSSupported = true;
5227     IntWidth = IntAlign = 32;
5228     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5229     PointerWidth = PointerAlign = 64;
5230     LongDoubleWidth = 128;
5231     LongDoubleAlign = 64;
5232     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5233     MinGlobalAlign = 16;
5234     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5235     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5236   }
5237   void getTargetDefines(const LangOptions &Opts,
5238                         MacroBuilder &Builder) const override {
5239     Builder.defineMacro("__s390__");
5240     Builder.defineMacro("__s390x__");
5241     Builder.defineMacro("__zarch__");
5242     Builder.defineMacro("__LONG_DOUBLE_128__");
5243   }
5244   void getTargetBuiltins(const Builtin::Info *&Records,
5245                          unsigned &NumRecords) const override {
5246     // FIXME: Implement.
5247     Records = nullptr;
5248     NumRecords = 0;
5249   }
5250 
5251   void getGCCRegNames(const char *const *&Names,
5252                       unsigned &NumNames) const override;
5253   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5254                         unsigned &NumAliases) const override {
5255     // No aliases.
5256     Aliases = nullptr;
5257     NumAliases = 0;
5258   }
5259   bool validateAsmConstraint(const char *&Name,
5260                              TargetInfo::ConstraintInfo &info) const override;
5261   const char *getClobbers() const override {
5262     // FIXME: Is this really right?
5263     return "";
5264   }
5265   BuiltinVaListKind getBuiltinVaListKind() const override {
5266     return TargetInfo::SystemZBuiltinVaList;
5267   }
5268   bool setCPU(const std::string &Name) override {
5269     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5270       .Case("z10", true)
5271       .Case("z196", true)
5272       .Case("zEC12", true)
5273       .Default(false);
5274 
5275     // No need to store the CPU yet.  There aren't any CPU-specific
5276     // macros to define.
5277     return CPUKnown;
5278   }
5279 };
5280 
5281 const char *const SystemZTargetInfo::GCCRegNames[] = {
5282   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5283   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5284   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5285   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5286 };
5287 
5288 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5289                                        unsigned &NumNames) const {
5290   Names = GCCRegNames;
5291   NumNames = llvm::array_lengthof(GCCRegNames);
5292 }
5293 
5294 bool SystemZTargetInfo::
5295 validateAsmConstraint(const char *&Name,
5296                       TargetInfo::ConstraintInfo &Info) const {
5297   switch (*Name) {
5298   default:
5299     return false;
5300 
5301   case 'a': // Address register
5302   case 'd': // Data register (equivalent to 'r')
5303   case 'f': // Floating-point register
5304     Info.setAllowsRegister();
5305     return true;
5306 
5307   case 'I': // Unsigned 8-bit constant
5308   case 'J': // Unsigned 12-bit constant
5309   case 'K': // Signed 16-bit constant
5310   case 'L': // Signed 20-bit displacement (on all targets we support)
5311   case 'M': // 0x7fffffff
5312     return true;
5313 
5314   case 'Q': // Memory with base and unsigned 12-bit displacement
5315   case 'R': // Likewise, plus an index
5316   case 'S': // Memory with base and signed 20-bit displacement
5317   case 'T': // Likewise, plus an index
5318     Info.setAllowsMemory();
5319     return true;
5320   }
5321 }
5322 }
5323 
5324 namespace {
5325   class MSP430TargetInfo : public TargetInfo {
5326     static const char * const GCCRegNames[];
5327   public:
5328     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5329       BigEndian = false;
5330       TLSSupported = false;
5331       IntWidth = 16; IntAlign = 16;
5332       LongWidth = 32; LongLongWidth = 64;
5333       LongAlign = LongLongAlign = 16;
5334       PointerWidth = 16; PointerAlign = 16;
5335       SuitableAlign = 16;
5336       SizeType = UnsignedInt;
5337       IntMaxType = SignedLongLong;
5338       IntPtrType = SignedInt;
5339       PtrDiffType = SignedInt;
5340       SigAtomicType = SignedLong;
5341       DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16";
5342     }
5343     void getTargetDefines(const LangOptions &Opts,
5344                           MacroBuilder &Builder) const override {
5345       Builder.defineMacro("MSP430");
5346       Builder.defineMacro("__MSP430__");
5347       // FIXME: defines for different 'flavours' of MCU
5348     }
5349     void getTargetBuiltins(const Builtin::Info *&Records,
5350                            unsigned &NumRecords) const override {
5351       // FIXME: Implement.
5352       Records = nullptr;
5353       NumRecords = 0;
5354     }
5355     bool hasFeature(StringRef Feature) const override {
5356       return Feature == "msp430";
5357     }
5358     void getGCCRegNames(const char * const *&Names,
5359                         unsigned &NumNames) const override;
5360     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5361                           unsigned &NumAliases) const override {
5362       // No aliases.
5363       Aliases = nullptr;
5364       NumAliases = 0;
5365     }
5366     bool validateAsmConstraint(const char *&Name,
5367                                TargetInfo::ConstraintInfo &info) const override {
5368       // No target constraints for now.
5369       return false;
5370     }
5371     const char *getClobbers() const override {
5372       // FIXME: Is this really right?
5373       return "";
5374     }
5375     BuiltinVaListKind getBuiltinVaListKind() const override {
5376       // FIXME: implement
5377       return TargetInfo::CharPtrBuiltinVaList;
5378    }
5379   };
5380 
5381   const char * const MSP430TargetInfo::GCCRegNames[] = {
5382     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5383     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5384   };
5385 
5386   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5387                                         unsigned &NumNames) const {
5388     Names = GCCRegNames;
5389     NumNames = llvm::array_lengthof(GCCRegNames);
5390   }
5391 }
5392 
5393 namespace {
5394 
5395   // LLVM and Clang cannot be used directly to output native binaries for
5396   // target, but is used to compile C code to llvm bitcode with correct
5397   // type and alignment information.
5398   //
5399   // TCE uses the llvm bitcode as input and uses it for generating customized
5400   // target processor and program binary. TCE co-design environment is
5401   // publicly available in http://tce.cs.tut.fi
5402 
5403   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5404       3, // opencl_global
5405       4, // opencl_local
5406       5, // opencl_constant
5407       0, // cuda_device
5408       0, // cuda_constant
5409       0  // cuda_shared
5410   };
5411 
5412   class TCETargetInfo : public TargetInfo{
5413   public:
5414     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5415       TLSSupported = false;
5416       IntWidth = 32;
5417       LongWidth = LongLongWidth = 32;
5418       PointerWidth = 32;
5419       IntAlign = 32;
5420       LongAlign = LongLongAlign = 32;
5421       PointerAlign = 32;
5422       SuitableAlign = 32;
5423       SizeType = UnsignedInt;
5424       IntMaxType = SignedLong;
5425       IntPtrType = SignedInt;
5426       PtrDiffType = SignedInt;
5427       FloatWidth = 32;
5428       FloatAlign = 32;
5429       DoubleWidth = 32;
5430       DoubleAlign = 32;
5431       LongDoubleWidth = 32;
5432       LongDoubleAlign = 32;
5433       FloatFormat = &llvm::APFloat::IEEEsingle;
5434       DoubleFormat = &llvm::APFloat::IEEEsingle;
5435       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5436       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5437                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5438       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5439       UseAddrSpaceMapMangling = true;
5440     }
5441 
5442     void getTargetDefines(const LangOptions &Opts,
5443                           MacroBuilder &Builder) const override {
5444       DefineStd(Builder, "tce", Opts);
5445       Builder.defineMacro("__TCE__");
5446       Builder.defineMacro("__TCE_V1__");
5447     }
5448     bool hasFeature(StringRef Feature) const override {
5449       return Feature == "tce";
5450     }
5451 
5452     void getTargetBuiltins(const Builtin::Info *&Records,
5453                            unsigned &NumRecords) const override {}
5454     const char *getClobbers() const override {
5455       return "";
5456     }
5457     BuiltinVaListKind getBuiltinVaListKind() const override {
5458       return TargetInfo::VoidPtrBuiltinVaList;
5459     }
5460     void getGCCRegNames(const char * const *&Names,
5461                         unsigned &NumNames) const override {}
5462     bool validateAsmConstraint(const char *&Name,
5463                                TargetInfo::ConstraintInfo &info) const override{
5464       return true;
5465     }
5466     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5467                           unsigned &NumAliases) const override {}
5468   };
5469 }
5470 
5471 namespace {
5472 class MipsTargetInfoBase : public TargetInfo {
5473   virtual void setDescriptionString() = 0;
5474 
5475   static const Builtin::Info BuiltinInfo[];
5476   std::string CPU;
5477   bool IsMips16;
5478   bool IsMicromips;
5479   bool IsNan2008;
5480   bool IsSingleFloat;
5481   enum MipsFloatABI {
5482     HardFloat, SoftFloat
5483   } FloatABI;
5484   enum DspRevEnum {
5485     NoDSP, DSP1, DSP2
5486   } DspRev;
5487   bool HasMSA;
5488 
5489 protected:
5490   bool HasFP64;
5491   std::string ABI;
5492 
5493 public:
5494   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5495                      const std::string &CPUStr)
5496       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5497         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5498         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5499 
5500   bool isNaN2008Default() const {
5501     return CPU == "mips32r6" || CPU == "mips64r6";
5502   }
5503 
5504   bool isFP64Default() const {
5505     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5506   }
5507 
5508   StringRef getABI() const override { return ABI; }
5509   bool setCPU(const std::string &Name) override {
5510     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5511                     getTriple().getArch() == llvm::Triple::mipsel;
5512     CPU = Name;
5513     return llvm::StringSwitch<bool>(Name)
5514         .Case("mips1", IsMips32)
5515         .Case("mips2", IsMips32)
5516         .Case("mips3", true)
5517         .Case("mips4", true)
5518         .Case("mips5", true)
5519         .Case("mips32", IsMips32)
5520         .Case("mips32r2", IsMips32)
5521         .Case("mips32r6", IsMips32)
5522         .Case("mips64", true)
5523         .Case("mips64r2", true)
5524         .Case("mips64r6", true)
5525         .Case("octeon", true)
5526         .Default(false);
5527   }
5528   const std::string& getCPU() const { return CPU; }
5529   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5530     // The backend enables certain ABI's by default according to the
5531     // architecture.
5532     // Disable both possible defaults so that we don't end up with multiple
5533     // ABI's selected and trigger an assertion.
5534     Features["o32"] = false;
5535     Features["n64"] = false;
5536 
5537     Features[ABI] = true;
5538     if (CPU == "octeon")
5539       Features["mips64r2"] = Features["cnmips"] = true;
5540     else
5541       Features[CPU] = true;
5542   }
5543 
5544   void getTargetDefines(const LangOptions &Opts,
5545                         MacroBuilder &Builder) const override {
5546     Builder.defineMacro("__mips__");
5547     Builder.defineMacro("_mips");
5548     if (Opts.GNUMode)
5549       Builder.defineMacro("mips");
5550 
5551     Builder.defineMacro("__REGISTER_PREFIX__", "");
5552 
5553     switch (FloatABI) {
5554     case HardFloat:
5555       Builder.defineMacro("__mips_hard_float", Twine(1));
5556       break;
5557     case SoftFloat:
5558       Builder.defineMacro("__mips_soft_float", Twine(1));
5559       break;
5560     }
5561 
5562     if (IsSingleFloat)
5563       Builder.defineMacro("__mips_single_float", Twine(1));
5564 
5565     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5566     Builder.defineMacro("_MIPS_FPSET",
5567                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5568 
5569     if (IsMips16)
5570       Builder.defineMacro("__mips16", Twine(1));
5571 
5572     if (IsMicromips)
5573       Builder.defineMacro("__mips_micromips", Twine(1));
5574 
5575     if (IsNan2008)
5576       Builder.defineMacro("__mips_nan2008", Twine(1));
5577 
5578     switch (DspRev) {
5579     default:
5580       break;
5581     case DSP1:
5582       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5583       Builder.defineMacro("__mips_dsp", Twine(1));
5584       break;
5585     case DSP2:
5586       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5587       Builder.defineMacro("__mips_dspr2", Twine(1));
5588       Builder.defineMacro("__mips_dsp", Twine(1));
5589       break;
5590     }
5591 
5592     if (HasMSA)
5593       Builder.defineMacro("__mips_msa", Twine(1));
5594 
5595     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5596     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5597     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5598 
5599     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5600     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5601   }
5602 
5603   void getTargetBuiltins(const Builtin::Info *&Records,
5604                          unsigned &NumRecords) const override {
5605     Records = BuiltinInfo;
5606     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5607   }
5608   bool hasFeature(StringRef Feature) const override {
5609     return llvm::StringSwitch<bool>(Feature)
5610       .Case("mips", true)
5611       .Case("fp64", HasFP64)
5612       .Default(false);
5613   }
5614   BuiltinVaListKind getBuiltinVaListKind() const override {
5615     return TargetInfo::VoidPtrBuiltinVaList;
5616   }
5617   void getGCCRegNames(const char * const *&Names,
5618                       unsigned &NumNames) const override {
5619     static const char *const GCCRegNames[] = {
5620       // CPU register names
5621       // Must match second column of GCCRegAliases
5622       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5623       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5624       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5625       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5626       // Floating point register names
5627       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5628       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5629       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5630       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5631       // Hi/lo and condition register names
5632       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5633       "$fcc5","$fcc6","$fcc7",
5634       // MSA register names
5635       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5636       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5637       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5638       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5639       // MSA control register names
5640       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5641       "$msarequest", "$msamap", "$msaunmap"
5642     };
5643     Names = GCCRegNames;
5644     NumNames = llvm::array_lengthof(GCCRegNames);
5645   }
5646   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5647                         unsigned &NumAliases) const override = 0;
5648   bool validateAsmConstraint(const char *&Name,
5649                              TargetInfo::ConstraintInfo &Info) const override {
5650     switch (*Name) {
5651     default:
5652       return false;
5653 
5654     case 'r': // CPU registers.
5655     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5656     case 'y': // Equivalent to "r", backward compatibility only.
5657     case 'f': // floating-point registers.
5658     case 'c': // $25 for indirect jumps
5659     case 'l': // lo register
5660     case 'x': // hilo register pair
5661       Info.setAllowsRegister();
5662       return true;
5663     case 'R': // An address that can be used in a non-macro load or store
5664       Info.setAllowsMemory();
5665       return true;
5666     }
5667   }
5668 
5669   const char *getClobbers() const override {
5670     // FIXME: Implement!
5671     return "";
5672   }
5673 
5674   bool handleTargetFeatures(std::vector<std::string> &Features,
5675                             DiagnosticsEngine &Diags) override {
5676     IsMips16 = false;
5677     IsMicromips = false;
5678     IsNan2008 = isNaN2008Default();
5679     IsSingleFloat = false;
5680     FloatABI = HardFloat;
5681     DspRev = NoDSP;
5682     HasFP64 = isFP64Default();
5683 
5684     for (std::vector<std::string>::iterator it = Features.begin(),
5685          ie = Features.end(); it != ie; ++it) {
5686       if (*it == "+single-float")
5687         IsSingleFloat = true;
5688       else if (*it == "+soft-float")
5689         FloatABI = SoftFloat;
5690       else if (*it == "+mips16")
5691         IsMips16 = true;
5692       else if (*it == "+micromips")
5693         IsMicromips = true;
5694       else if (*it == "+dsp")
5695         DspRev = std::max(DspRev, DSP1);
5696       else if (*it == "+dspr2")
5697         DspRev = std::max(DspRev, DSP2);
5698       else if (*it == "+msa")
5699         HasMSA = true;
5700       else if (*it == "+fp64")
5701         HasFP64 = true;
5702       else if (*it == "-fp64")
5703         HasFP64 = false;
5704       else if (*it == "+nan2008")
5705         IsNan2008 = true;
5706       else if (*it == "-nan2008")
5707         IsNan2008 = false;
5708     }
5709 
5710     // Remove front-end specific options.
5711     std::vector<std::string>::iterator it =
5712       std::find(Features.begin(), Features.end(), "+soft-float");
5713     if (it != Features.end())
5714       Features.erase(it);
5715 
5716     setDescriptionString();
5717 
5718     return true;
5719   }
5720 
5721   int getEHDataRegisterNumber(unsigned RegNo) const override {
5722     if (RegNo == 0) return 4;
5723     if (RegNo == 1) return 5;
5724     return -1;
5725   }
5726 
5727   bool isCLZForZeroUndef() const override { return false; }
5728 };
5729 
5730 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5731 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5732 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5733                                               ALL_LANGUAGES },
5734 #include "clang/Basic/BuiltinsMips.def"
5735 };
5736 
5737 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5738 public:
5739   Mips32TargetInfoBase(const llvm::Triple &Triple)
5740       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5741     SizeType = UnsignedInt;
5742     PtrDiffType = SignedInt;
5743     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5744   }
5745   bool setABI(const std::string &Name) override {
5746     if (Name == "o32" || Name == "eabi") {
5747       ABI = Name;
5748       return true;
5749     }
5750     return false;
5751   }
5752   void getTargetDefines(const LangOptions &Opts,
5753                         MacroBuilder &Builder) const override {
5754     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5755 
5756     Builder.defineMacro("__mips", "32");
5757     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5758 
5759     const std::string& CPUStr = getCPU();
5760     if (CPUStr == "mips32")
5761       Builder.defineMacro("__mips_isa_rev", "1");
5762     else if (CPUStr == "mips32r2")
5763       Builder.defineMacro("__mips_isa_rev", "2");
5764 
5765     if (ABI == "o32") {
5766       Builder.defineMacro("__mips_o32");
5767       Builder.defineMacro("_ABIO32", "1");
5768       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5769     }
5770     else if (ABI == "eabi")
5771       Builder.defineMacro("__mips_eabi");
5772     else
5773       llvm_unreachable("Invalid ABI for Mips32.");
5774   }
5775   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5776                         unsigned &NumAliases) const override {
5777     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5778       { { "at" },  "$1" },
5779       { { "v0" },  "$2" },
5780       { { "v1" },  "$3" },
5781       { { "a0" },  "$4" },
5782       { { "a1" },  "$5" },
5783       { { "a2" },  "$6" },
5784       { { "a3" },  "$7" },
5785       { { "t0" },  "$8" },
5786       { { "t1" },  "$9" },
5787       { { "t2" }, "$10" },
5788       { { "t3" }, "$11" },
5789       { { "t4" }, "$12" },
5790       { { "t5" }, "$13" },
5791       { { "t6" }, "$14" },
5792       { { "t7" }, "$15" },
5793       { { "s0" }, "$16" },
5794       { { "s1" }, "$17" },
5795       { { "s2" }, "$18" },
5796       { { "s3" }, "$19" },
5797       { { "s4" }, "$20" },
5798       { { "s5" }, "$21" },
5799       { { "s6" }, "$22" },
5800       { { "s7" }, "$23" },
5801       { { "t8" }, "$24" },
5802       { { "t9" }, "$25" },
5803       { { "k0" }, "$26" },
5804       { { "k1" }, "$27" },
5805       { { "gp" }, "$28" },
5806       { { "sp","$sp" }, "$29" },
5807       { { "fp","$fp" }, "$30" },
5808       { { "ra" }, "$31" }
5809     };
5810     Aliases = GCCRegAliases;
5811     NumAliases = llvm::array_lengthof(GCCRegAliases);
5812   }
5813 };
5814 
5815 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5816   void setDescriptionString() override {
5817     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5818   }
5819 
5820 public:
5821   Mips32EBTargetInfo(const llvm::Triple &Triple)
5822       : Mips32TargetInfoBase(Triple) {
5823   }
5824   void getTargetDefines(const LangOptions &Opts,
5825                         MacroBuilder &Builder) const override {
5826     DefineStd(Builder, "MIPSEB", Opts);
5827     Builder.defineMacro("_MIPSEB");
5828     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5829   }
5830 };
5831 
5832 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5833   void setDescriptionString() override {
5834     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5835   }
5836 
5837 public:
5838   Mips32ELTargetInfo(const llvm::Triple &Triple)
5839       : Mips32TargetInfoBase(Triple) {
5840     BigEndian = false;
5841   }
5842   void getTargetDefines(const LangOptions &Opts,
5843                         MacroBuilder &Builder) const override {
5844     DefineStd(Builder, "MIPSEL", Opts);
5845     Builder.defineMacro("_MIPSEL");
5846     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5847   }
5848 };
5849 
5850 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5851 public:
5852   Mips64TargetInfoBase(const llvm::Triple &Triple)
5853       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5854     LongDoubleWidth = LongDoubleAlign = 128;
5855     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5856     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5857       LongDoubleWidth = LongDoubleAlign = 64;
5858       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5859     }
5860     setN64ABITypes();
5861     SuitableAlign = 128;
5862     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5863   }
5864 
5865   void setN64ABITypes() {
5866     LongWidth = LongAlign = 64;
5867     PointerWidth = PointerAlign = 64;
5868     SizeType = UnsignedLong;
5869     PtrDiffType = SignedLong;
5870   }
5871 
5872   void setN32ABITypes() {
5873     LongWidth = LongAlign = 32;
5874     PointerWidth = PointerAlign = 32;
5875     SizeType = UnsignedInt;
5876     PtrDiffType = SignedInt;
5877   }
5878 
5879   bool setABI(const std::string &Name) override {
5880     if (Name == "n32") {
5881       setN32ABITypes();
5882       ABI = Name;
5883       return true;
5884     }
5885     if (Name == "n64") {
5886       setN64ABITypes();
5887       ABI = Name;
5888       return true;
5889     }
5890     return false;
5891   }
5892 
5893   void getTargetDefines(const LangOptions &Opts,
5894                         MacroBuilder &Builder) const override {
5895     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5896 
5897     Builder.defineMacro("__mips", "64");
5898     Builder.defineMacro("__mips64");
5899     Builder.defineMacro("__mips64__");
5900     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5901 
5902     const std::string& CPUStr = getCPU();
5903     if (CPUStr == "mips64")
5904       Builder.defineMacro("__mips_isa_rev", "1");
5905     else if (CPUStr == "mips64r2")
5906       Builder.defineMacro("__mips_isa_rev", "2");
5907 
5908     if (ABI == "n32") {
5909       Builder.defineMacro("__mips_n32");
5910       Builder.defineMacro("_ABIN32", "2");
5911       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5912     }
5913     else if (ABI == "n64") {
5914       Builder.defineMacro("__mips_n64");
5915       Builder.defineMacro("_ABI64", "3");
5916       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5917     }
5918     else
5919       llvm_unreachable("Invalid ABI for Mips64.");
5920   }
5921   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5922                         unsigned &NumAliases) const override {
5923     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5924       { { "at" },  "$1" },
5925       { { "v0" },  "$2" },
5926       { { "v1" },  "$3" },
5927       { { "a0" },  "$4" },
5928       { { "a1" },  "$5" },
5929       { { "a2" },  "$6" },
5930       { { "a3" },  "$7" },
5931       { { "a4" },  "$8" },
5932       { { "a5" },  "$9" },
5933       { { "a6" }, "$10" },
5934       { { "a7" }, "$11" },
5935       { { "t0" }, "$12" },
5936       { { "t1" }, "$13" },
5937       { { "t2" }, "$14" },
5938       { { "t3" }, "$15" },
5939       { { "s0" }, "$16" },
5940       { { "s1" }, "$17" },
5941       { { "s2" }, "$18" },
5942       { { "s3" }, "$19" },
5943       { { "s4" }, "$20" },
5944       { { "s5" }, "$21" },
5945       { { "s6" }, "$22" },
5946       { { "s7" }, "$23" },
5947       { { "t8" }, "$24" },
5948       { { "t9" }, "$25" },
5949       { { "k0" }, "$26" },
5950       { { "k1" }, "$27" },
5951       { { "gp" }, "$28" },
5952       { { "sp","$sp" }, "$29" },
5953       { { "fp","$fp" }, "$30" },
5954       { { "ra" }, "$31" }
5955     };
5956     Aliases = GCCRegAliases;
5957     NumAliases = llvm::array_lengthof(GCCRegAliases);
5958   }
5959 
5960   bool hasInt128Type() const override { return true; }
5961 };
5962 
5963 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5964   void setDescriptionString() override {
5965     if (ABI == "n32")
5966       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5967     else
5968       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5969 
5970   }
5971 
5972 public:
5973   Mips64EBTargetInfo(const llvm::Triple &Triple)
5974       : Mips64TargetInfoBase(Triple) {}
5975   void getTargetDefines(const LangOptions &Opts,
5976                         MacroBuilder &Builder) const override {
5977     DefineStd(Builder, "MIPSEB", Opts);
5978     Builder.defineMacro("_MIPSEB");
5979     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5980   }
5981 };
5982 
5983 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5984   void setDescriptionString() override {
5985     if (ABI == "n32")
5986       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5987     else
5988       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5989   }
5990 public:
5991   Mips64ELTargetInfo(const llvm::Triple &Triple)
5992       : Mips64TargetInfoBase(Triple) {
5993     // Default ABI is n64.
5994     BigEndian = false;
5995   }
5996   void getTargetDefines(const LangOptions &Opts,
5997                         MacroBuilder &Builder) const override {
5998     DefineStd(Builder, "MIPSEL", Opts);
5999     Builder.defineMacro("_MIPSEL");
6000     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
6001   }
6002 };
6003 } // end anonymous namespace.
6004 
6005 namespace {
6006 class PNaClTargetInfo : public TargetInfo {
6007 public:
6008   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6009     BigEndian = false;
6010     this->UserLabelPrefix = "";
6011     this->LongAlign = 32;
6012     this->LongWidth = 32;
6013     this->PointerAlign = 32;
6014     this->PointerWidth = 32;
6015     this->IntMaxType = TargetInfo::SignedLongLong;
6016     this->Int64Type = TargetInfo::SignedLongLong;
6017     this->DoubleAlign = 64;
6018     this->LongDoubleWidth = 64;
6019     this->LongDoubleAlign = 64;
6020     this->SizeType = TargetInfo::UnsignedInt;
6021     this->PtrDiffType = TargetInfo::SignedInt;
6022     this->IntPtrType = TargetInfo::SignedInt;
6023     this->RegParmMax = 0; // Disallow regparm
6024   }
6025 
6026   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
6027   }
6028   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
6029     Builder.defineMacro("__le32__");
6030     Builder.defineMacro("__pnacl__");
6031   }
6032   void getTargetDefines(const LangOptions &Opts,
6033                         MacroBuilder &Builder) const override {
6034     getArchDefines(Opts, Builder);
6035   }
6036   bool hasFeature(StringRef Feature) const override {
6037     return Feature == "pnacl";
6038   }
6039   void getTargetBuiltins(const Builtin::Info *&Records,
6040                          unsigned &NumRecords) const override {
6041   }
6042   BuiltinVaListKind getBuiltinVaListKind() const override {
6043     return TargetInfo::PNaClABIBuiltinVaList;
6044   }
6045   void getGCCRegNames(const char * const *&Names,
6046                       unsigned &NumNames) const override;
6047   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6048                         unsigned &NumAliases) const override;
6049   bool validateAsmConstraint(const char *&Name,
6050                              TargetInfo::ConstraintInfo &Info) const override {
6051     return false;
6052   }
6053 
6054   const char *getClobbers() const override {
6055     return "";
6056   }
6057 };
6058 
6059 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
6060                                      unsigned &NumNames) const {
6061   Names = nullptr;
6062   NumNames = 0;
6063 }
6064 
6065 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
6066                                        unsigned &NumAliases) const {
6067   Aliases = nullptr;
6068   NumAliases = 0;
6069 }
6070 } // end anonymous namespace.
6071 
6072 namespace {
6073 class Le64TargetInfo : public TargetInfo {
6074   static const Builtin::Info BuiltinInfo[];
6075 
6076 public:
6077   Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6078     BigEndian = false;
6079     NoAsmVariants = true;
6080     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
6081     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
6082     DescriptionString =
6083         "e-S128-p:64:64-v16:16-v32:32-v64:64-v96:32-v128:32-m:e-n8:16:32:64";
6084   }
6085 
6086   void getTargetDefines(const LangOptions &Opts,
6087                         MacroBuilder &Builder) const override {
6088     DefineStd(Builder, "unix", Opts);
6089     defineCPUMacros(Builder, "le64", /*Tuning=*/false);
6090     Builder.defineMacro("__ELF__");
6091   }
6092   void getTargetBuiltins(const Builtin::Info *&Records,
6093                          unsigned &NumRecords) const override {
6094     Records = BuiltinInfo;
6095     NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin;
6096   }
6097   BuiltinVaListKind getBuiltinVaListKind() const override {
6098     return TargetInfo::PNaClABIBuiltinVaList;
6099   }
6100   const char *getClobbers() const override { return ""; }
6101   void getGCCRegNames(const char *const *&Names,
6102                       unsigned &NumNames) const override {
6103     Names = nullptr;
6104     NumNames = 0;
6105   }
6106   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6107                         unsigned &NumAliases) const override {
6108     Aliases = nullptr;
6109     NumAliases = 0;
6110   }
6111   bool validateAsmConstraint(const char *&Name,
6112                              TargetInfo::ConstraintInfo &Info) const override {
6113     return false;
6114   }
6115 
6116   bool hasProtectedVisibility() const override { return false; }
6117 };
6118 } // end anonymous namespace.
6119 
6120 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = {
6121 #define BUILTIN(ID, TYPE, ATTRS)                                               \
6122   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6123 #include "clang/Basic/BuiltinsLe64.def"
6124 };
6125 
6126 namespace {
6127   static const unsigned SPIRAddrSpaceMap[] = {
6128     1,    // opencl_global
6129     3,    // opencl_local
6130     2,    // opencl_constant
6131     0,    // cuda_device
6132     0,    // cuda_constant
6133     0     // cuda_shared
6134   };
6135   class SPIRTargetInfo : public TargetInfo {
6136   public:
6137     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6138       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
6139         "SPIR target must use unknown OS");
6140       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
6141         "SPIR target must use unknown environment type");
6142       BigEndian = false;
6143       TLSSupported = false;
6144       LongWidth = LongAlign = 64;
6145       AddrSpaceMap = &SPIRAddrSpaceMap;
6146       UseAddrSpaceMapMangling = true;
6147       // Define available target features
6148       // These must be defined in sorted order!
6149       NoAsmVariants = true;
6150     }
6151     void getTargetDefines(const LangOptions &Opts,
6152                           MacroBuilder &Builder) const override {
6153       DefineStd(Builder, "SPIR", Opts);
6154     }
6155     bool hasFeature(StringRef Feature) const override {
6156       return Feature == "spir";
6157     }
6158 
6159     void getTargetBuiltins(const Builtin::Info *&Records,
6160                            unsigned &NumRecords) const override {}
6161     const char *getClobbers() const override {
6162       return "";
6163     }
6164     void getGCCRegNames(const char * const *&Names,
6165                         unsigned &NumNames) const override {}
6166     bool validateAsmConstraint(const char *&Name,
6167                                TargetInfo::ConstraintInfo &info) const override {
6168       return true;
6169     }
6170     void getGCCRegAliases(const GCCRegAlias *&Aliases,
6171                           unsigned &NumAliases) const override {}
6172     BuiltinVaListKind getBuiltinVaListKind() const override {
6173       return TargetInfo::VoidPtrBuiltinVaList;
6174     }
6175   };
6176 
6177 
6178   class SPIR32TargetInfo : public SPIRTargetInfo {
6179   public:
6180     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6181       PointerWidth = PointerAlign = 32;
6182       SizeType     = TargetInfo::UnsignedInt;
6183       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
6184       DescriptionString
6185         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
6186           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6187     }
6188     void getTargetDefines(const LangOptions &Opts,
6189                           MacroBuilder &Builder) const override {
6190       DefineStd(Builder, "SPIR32", Opts);
6191     }
6192   };
6193 
6194   class SPIR64TargetInfo : public SPIRTargetInfo {
6195   public:
6196     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
6197       PointerWidth = PointerAlign = 64;
6198       SizeType     = TargetInfo::UnsignedLong;
6199       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
6200       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
6201                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
6202     }
6203     void getTargetDefines(const LangOptions &Opts,
6204                           MacroBuilder &Builder) const override {
6205       DefineStd(Builder, "SPIR64", Opts);
6206     }
6207   };
6208 }
6209 
6210 namespace {
6211 class XCoreTargetInfo : public TargetInfo {
6212   static const Builtin::Info BuiltinInfo[];
6213 public:
6214   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
6215     BigEndian = false;
6216     NoAsmVariants = true;
6217     LongLongAlign = 32;
6218     SuitableAlign = 32;
6219     DoubleAlign = LongDoubleAlign = 32;
6220     SizeType = UnsignedInt;
6221     PtrDiffType = SignedInt;
6222     IntPtrType = SignedInt;
6223     WCharType = UnsignedChar;
6224     WIntType = UnsignedInt;
6225     UseZeroLengthBitfieldAlignment = true;
6226     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
6227                         "-f64:32-a:0:32-n32";
6228   }
6229   void getTargetDefines(const LangOptions &Opts,
6230                         MacroBuilder &Builder) const override {
6231     Builder.defineMacro("__XS1B__");
6232   }
6233   void getTargetBuiltins(const Builtin::Info *&Records,
6234                          unsigned &NumRecords) const override {
6235     Records = BuiltinInfo;
6236     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
6237   }
6238   BuiltinVaListKind getBuiltinVaListKind() const override {
6239     return TargetInfo::VoidPtrBuiltinVaList;
6240   }
6241   const char *getClobbers() const override {
6242     return "";
6243   }
6244   void getGCCRegNames(const char * const *&Names,
6245                       unsigned &NumNames) const override {
6246     static const char * const GCCRegNames[] = {
6247       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6248       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6249     };
6250     Names = GCCRegNames;
6251     NumNames = llvm::array_lengthof(GCCRegNames);
6252   }
6253   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6254                         unsigned &NumAliases) const override {
6255     Aliases = nullptr;
6256     NumAliases = 0;
6257   }
6258   bool validateAsmConstraint(const char *&Name,
6259                              TargetInfo::ConstraintInfo &Info) const override {
6260     return false;
6261   }
6262   int getEHDataRegisterNumber(unsigned RegNo) const override {
6263     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6264     return (RegNo < 2)? RegNo : -1;
6265   }
6266 };
6267 
6268 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6269 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6270 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6271                                               ALL_LANGUAGES },
6272 #include "clang/Basic/BuiltinsXCore.def"
6273 };
6274 } // end anonymous namespace.
6275 
6276 
6277 //===----------------------------------------------------------------------===//
6278 // Driver code
6279 //===----------------------------------------------------------------------===//
6280 
6281 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6282   llvm::Triple::OSType os = Triple.getOS();
6283 
6284   switch (Triple.getArch()) {
6285   default:
6286     return nullptr;
6287 
6288   case llvm::Triple::xcore:
6289     return new XCoreTargetInfo(Triple);
6290 
6291   case llvm::Triple::hexagon:
6292     return new HexagonTargetInfo(Triple);
6293 
6294   case llvm::Triple::aarch64:
6295     if (Triple.isOSDarwin())
6296       return new DarwinAArch64TargetInfo(Triple);
6297 
6298     switch (os) {
6299     case llvm::Triple::Linux:
6300       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6301     case llvm::Triple::NetBSD:
6302       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6303     default:
6304       return new AArch64leTargetInfo(Triple);
6305     }
6306 
6307   case llvm::Triple::aarch64_be:
6308     switch (os) {
6309     case llvm::Triple::Linux:
6310       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6311     case llvm::Triple::NetBSD:
6312       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6313     default:
6314       return new AArch64beTargetInfo(Triple);
6315     }
6316 
6317   case llvm::Triple::arm:
6318   case llvm::Triple::thumb:
6319     if (Triple.isOSBinFormatMachO())
6320       return new DarwinARMTargetInfo(Triple);
6321 
6322     switch (os) {
6323     case llvm::Triple::Linux:
6324       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6325     case llvm::Triple::FreeBSD:
6326       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6327     case llvm::Triple::NetBSD:
6328       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6329     case llvm::Triple::OpenBSD:
6330       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6331     case llvm::Triple::Bitrig:
6332       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6333     case llvm::Triple::RTEMS:
6334       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6335     case llvm::Triple::NaCl:
6336       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6337     case llvm::Triple::Win32:
6338       switch (Triple.getEnvironment()) {
6339       default:
6340         return new ARMleTargetInfo(Triple);
6341       case llvm::Triple::Itanium:
6342         return new ItaniumWindowsARMleTargetInfo(Triple);
6343       case llvm::Triple::MSVC:
6344         return new MicrosoftARMleTargetInfo(Triple);
6345       }
6346     default:
6347       return new ARMleTargetInfo(Triple);
6348     }
6349 
6350   case llvm::Triple::armeb:
6351   case llvm::Triple::thumbeb:
6352     if (Triple.isOSDarwin())
6353       return new DarwinARMTargetInfo(Triple);
6354 
6355     switch (os) {
6356     case llvm::Triple::Linux:
6357       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6358     case llvm::Triple::FreeBSD:
6359       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6360     case llvm::Triple::NetBSD:
6361       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6362     case llvm::Triple::OpenBSD:
6363       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6364     case llvm::Triple::Bitrig:
6365       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6366     case llvm::Triple::RTEMS:
6367       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6368     case llvm::Triple::NaCl:
6369       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6370     default:
6371       return new ARMbeTargetInfo(Triple);
6372     }
6373 
6374   case llvm::Triple::msp430:
6375     return new MSP430TargetInfo(Triple);
6376 
6377   case llvm::Triple::mips:
6378     switch (os) {
6379     case llvm::Triple::Linux:
6380       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6381     case llvm::Triple::RTEMS:
6382       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6383     case llvm::Triple::FreeBSD:
6384       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6385     case llvm::Triple::NetBSD:
6386       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6387     default:
6388       return new Mips32EBTargetInfo(Triple);
6389     }
6390 
6391   case llvm::Triple::mipsel:
6392     switch (os) {
6393     case llvm::Triple::Linux:
6394       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6395     case llvm::Triple::RTEMS:
6396       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6397     case llvm::Triple::FreeBSD:
6398       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6399     case llvm::Triple::NetBSD:
6400       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6401     case llvm::Triple::NaCl:
6402       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6403     default:
6404       return new Mips32ELTargetInfo(Triple);
6405     }
6406 
6407   case llvm::Triple::mips64:
6408     switch (os) {
6409     case llvm::Triple::Linux:
6410       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6411     case llvm::Triple::RTEMS:
6412       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6413     case llvm::Triple::FreeBSD:
6414       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6415     case llvm::Triple::NetBSD:
6416       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6417     case llvm::Triple::OpenBSD:
6418       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6419     default:
6420       return new Mips64EBTargetInfo(Triple);
6421     }
6422 
6423   case llvm::Triple::mips64el:
6424     switch (os) {
6425     case llvm::Triple::Linux:
6426       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6427     case llvm::Triple::RTEMS:
6428       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6429     case llvm::Triple::FreeBSD:
6430       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6431     case llvm::Triple::NetBSD:
6432       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6433     case llvm::Triple::OpenBSD:
6434       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6435     default:
6436       return new Mips64ELTargetInfo(Triple);
6437     }
6438 
6439   case llvm::Triple::le32:
6440     switch (os) {
6441       case llvm::Triple::NaCl:
6442         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6443       default:
6444         return nullptr;
6445     }
6446 
6447   case llvm::Triple::le64:
6448     return new Le64TargetInfo(Triple);
6449 
6450   case llvm::Triple::ppc:
6451     if (Triple.isOSDarwin())
6452       return new DarwinPPC32TargetInfo(Triple);
6453     switch (os) {
6454     case llvm::Triple::Linux:
6455       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6456     case llvm::Triple::FreeBSD:
6457       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6458     case llvm::Triple::NetBSD:
6459       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6460     case llvm::Triple::OpenBSD:
6461       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6462     case llvm::Triple::RTEMS:
6463       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6464     default:
6465       return new PPC32TargetInfo(Triple);
6466     }
6467 
6468   case llvm::Triple::ppc64:
6469     if (Triple.isOSDarwin())
6470       return new DarwinPPC64TargetInfo(Triple);
6471     switch (os) {
6472     case llvm::Triple::Linux:
6473       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6474     case llvm::Triple::Lv2:
6475       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6476     case llvm::Triple::FreeBSD:
6477       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6478     case llvm::Triple::NetBSD:
6479       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6480     default:
6481       return new PPC64TargetInfo(Triple);
6482     }
6483 
6484   case llvm::Triple::ppc64le:
6485     switch (os) {
6486     case llvm::Triple::Linux:
6487       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6488     default:
6489       return new PPC64TargetInfo(Triple);
6490     }
6491 
6492   case llvm::Triple::nvptx:
6493     return new NVPTX32TargetInfo(Triple);
6494   case llvm::Triple::nvptx64:
6495     return new NVPTX64TargetInfo(Triple);
6496 
6497   case llvm::Triple::r600:
6498     return new R600TargetInfo(Triple);
6499 
6500   case llvm::Triple::sparc:
6501     switch (os) {
6502     case llvm::Triple::Linux:
6503       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6504     case llvm::Triple::Solaris:
6505       return new SolarisSparcV8TargetInfo(Triple);
6506     case llvm::Triple::NetBSD:
6507       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6508     case llvm::Triple::OpenBSD:
6509       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6510     case llvm::Triple::RTEMS:
6511       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6512     default:
6513       return new SparcV8TargetInfo(Triple);
6514     }
6515 
6516   case llvm::Triple::sparcv9:
6517     switch (os) {
6518     case llvm::Triple::Linux:
6519       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6520     case llvm::Triple::Solaris:
6521       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6522     case llvm::Triple::NetBSD:
6523       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6524     case llvm::Triple::OpenBSD:
6525       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6526     case llvm::Triple::FreeBSD:
6527       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6528     default:
6529       return new SparcV9TargetInfo(Triple);
6530     }
6531 
6532   case llvm::Triple::systemz:
6533     switch (os) {
6534     case llvm::Triple::Linux:
6535       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6536     default:
6537       return new SystemZTargetInfo(Triple);
6538     }
6539 
6540   case llvm::Triple::tce:
6541     return new TCETargetInfo(Triple);
6542 
6543   case llvm::Triple::x86:
6544     if (Triple.isOSDarwin())
6545       return new DarwinI386TargetInfo(Triple);
6546 
6547     switch (os) {
6548     case llvm::Triple::Linux:
6549       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6550     case llvm::Triple::DragonFly:
6551       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6552     case llvm::Triple::NetBSD:
6553       return new NetBSDI386TargetInfo(Triple);
6554     case llvm::Triple::OpenBSD:
6555       return new OpenBSDI386TargetInfo(Triple);
6556     case llvm::Triple::Bitrig:
6557       return new BitrigI386TargetInfo(Triple);
6558     case llvm::Triple::FreeBSD:
6559       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6560     case llvm::Triple::KFreeBSD:
6561       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6562     case llvm::Triple::Minix:
6563       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6564     case llvm::Triple::Solaris:
6565       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6566     case llvm::Triple::Win32: {
6567       switch (Triple.getEnvironment()) {
6568       default:
6569         return new X86_32TargetInfo(Triple);
6570       case llvm::Triple::Cygnus:
6571         return new CygwinX86_32TargetInfo(Triple);
6572       case llvm::Triple::GNU:
6573         return new MinGWX86_32TargetInfo(Triple);
6574       case llvm::Triple::Itanium:
6575       case llvm::Triple::MSVC:
6576         return new MicrosoftX86_32TargetInfo(Triple);
6577       }
6578     }
6579     case llvm::Triple::Haiku:
6580       return new HaikuX86_32TargetInfo(Triple);
6581     case llvm::Triple::RTEMS:
6582       return new RTEMSX86_32TargetInfo(Triple);
6583     case llvm::Triple::NaCl:
6584       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6585     default:
6586       return new X86_32TargetInfo(Triple);
6587     }
6588 
6589   case llvm::Triple::x86_64:
6590     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6591       return new DarwinX86_64TargetInfo(Triple);
6592 
6593     switch (os) {
6594     case llvm::Triple::Linux:
6595       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6596     case llvm::Triple::DragonFly:
6597       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6598     case llvm::Triple::NetBSD:
6599       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6600     case llvm::Triple::OpenBSD:
6601       return new OpenBSDX86_64TargetInfo(Triple);
6602     case llvm::Triple::Bitrig:
6603       return new BitrigX86_64TargetInfo(Triple);
6604     case llvm::Triple::FreeBSD:
6605       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6606     case llvm::Triple::KFreeBSD:
6607       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6608     case llvm::Triple::Solaris:
6609       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6610     case llvm::Triple::Win32: {
6611       switch (Triple.getEnvironment()) {
6612       default:
6613         return new X86_64TargetInfo(Triple);
6614       case llvm::Triple::GNU:
6615         return new MinGWX86_64TargetInfo(Triple);
6616       case llvm::Triple::MSVC:
6617         return new MicrosoftX86_64TargetInfo(Triple);
6618       }
6619     }
6620     case llvm::Triple::NaCl:
6621       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6622     default:
6623       return new X86_64TargetInfo(Triple);
6624     }
6625 
6626     case llvm::Triple::spir: {
6627       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6628           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6629         return nullptr;
6630       return new SPIR32TargetInfo(Triple);
6631     }
6632     case llvm::Triple::spir64: {
6633       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6634           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6635         return nullptr;
6636       return new SPIR64TargetInfo(Triple);
6637     }
6638   }
6639 }
6640 
6641 /// CreateTargetInfo - Return the target info object for the specified target
6642 /// triple.
6643 TargetInfo *
6644 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6645                              const std::shared_ptr<TargetOptions> &Opts) {
6646   llvm::Triple Triple(Opts->Triple);
6647 
6648   // Construct the target
6649   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6650   if (!Target) {
6651     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6652     return nullptr;
6653   }
6654   Target->TargetOpts = Opts;
6655 
6656   // Set the target CPU if specified.
6657   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6658     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6659     return nullptr;
6660   }
6661 
6662   // Set the target ABI if specified.
6663   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6664     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6665     return nullptr;
6666   }
6667 
6668   // Set the fp math unit.
6669   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6670     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6671     return nullptr;
6672   }
6673 
6674   // Compute the default target features, we need the target to handle this
6675   // because features may have dependencies on one another.
6676   llvm::StringMap<bool> Features;
6677   Target->getDefaultFeatures(Features);
6678 
6679   // Apply the user specified deltas.
6680   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6681        I < N; ++I) {
6682     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6683     // Apply the feature via the target.
6684     bool Enabled = Name[0] == '+';
6685     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6686   }
6687 
6688   // Add the features to the compile options.
6689   //
6690   // FIXME: If we are completely confident that we have the right set, we only
6691   // need to pass the minuses.
6692   Opts->Features.clear();
6693   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6694          ie = Features.end(); it != ie; ++it)
6695     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6696   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6697     return nullptr;
6698 
6699   return Target.release();
6700 }
6701