1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 if (Maj) 469 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 470 } 471 if (Opts.POSIXThreads) 472 Builder.defineMacro("_REENTRANT"); 473 if (Opts.CPlusPlus) 474 Builder.defineMacro("_GNU_SOURCE"); 475 if (this->HasFloat128) 476 Builder.defineMacro("__FLOAT128__"); 477 } 478 public: 479 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 480 : OSTargetInfo<Target>(Triple, Opts) { 481 this->WIntType = TargetInfo::UnsignedInt; 482 483 switch (Triple.getArch()) { 484 default: 485 break; 486 case llvm::Triple::ppc: 487 case llvm::Triple::ppc64: 488 case llvm::Triple::ppc64le: 489 this->MCountName = "_mcount"; 490 break; 491 case llvm::Triple::x86: 492 case llvm::Triple::x86_64: 493 case llvm::Triple::systemz: 494 this->HasFloat128 = true; 495 break; 496 } 497 } 498 499 const char *getStaticInitSectionSpecifier() const override { 500 return ".text.startup"; 501 } 502 }; 503 504 // NetBSD Target 505 template<typename Target> 506 class NetBSDTargetInfo : public OSTargetInfo<Target> { 507 protected: 508 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 509 MacroBuilder &Builder) const override { 510 // NetBSD defines; list based off of gcc output 511 Builder.defineMacro("__NetBSD__"); 512 Builder.defineMacro("__unix__"); 513 Builder.defineMacro("__ELF__"); 514 if (Opts.POSIXThreads) 515 Builder.defineMacro("_REENTRANT"); 516 517 switch (Triple.getArch()) { 518 default: 519 break; 520 case llvm::Triple::arm: 521 case llvm::Triple::armeb: 522 case llvm::Triple::thumb: 523 case llvm::Triple::thumbeb: 524 Builder.defineMacro("__ARM_DWARF_EH__"); 525 break; 526 } 527 } 528 public: 529 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 530 : OSTargetInfo<Target>(Triple, Opts) { 531 this->MCountName = "_mcount"; 532 } 533 }; 534 535 // OpenBSD Target 536 template<typename Target> 537 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 538 protected: 539 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 540 MacroBuilder &Builder) const override { 541 // OpenBSD defines; list based off of gcc output 542 543 Builder.defineMacro("__OpenBSD__"); 544 DefineStd(Builder, "unix", Opts); 545 Builder.defineMacro("__ELF__"); 546 if (Opts.POSIXThreads) 547 Builder.defineMacro("_REENTRANT"); 548 if (this->HasFloat128) 549 Builder.defineMacro("__FLOAT128__"); 550 } 551 public: 552 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 553 : OSTargetInfo<Target>(Triple, Opts) { 554 this->TLSSupported = false; 555 556 switch (Triple.getArch()) { 557 case llvm::Triple::x86: 558 case llvm::Triple::x86_64: 559 this->HasFloat128 = true; 560 // FALLTHROUGH 561 default: 562 this->MCountName = "__mcount"; 563 break; 564 case llvm::Triple::mips64: 565 case llvm::Triple::mips64el: 566 case llvm::Triple::ppc: 567 case llvm::Triple::sparcv9: 568 this->MCountName = "_mcount"; 569 break; 570 } 571 } 572 }; 573 574 // Bitrig Target 575 template<typename Target> 576 class BitrigTargetInfo : public OSTargetInfo<Target> { 577 protected: 578 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 579 MacroBuilder &Builder) const override { 580 // Bitrig defines; list based off of gcc output 581 582 Builder.defineMacro("__Bitrig__"); 583 DefineStd(Builder, "unix", Opts); 584 Builder.defineMacro("__ELF__"); 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_REENTRANT"); 587 588 switch (Triple.getArch()) { 589 default: 590 break; 591 case llvm::Triple::arm: 592 case llvm::Triple::armeb: 593 case llvm::Triple::thumb: 594 case llvm::Triple::thumbeb: 595 Builder.defineMacro("__ARM_DWARF_EH__"); 596 break; 597 } 598 } 599 public: 600 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 601 : OSTargetInfo<Target>(Triple, Opts) { 602 this->MCountName = "__mcount"; 603 } 604 }; 605 606 // PSP Target 607 template<typename Target> 608 class PSPTargetInfo : public OSTargetInfo<Target> { 609 protected: 610 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 611 MacroBuilder &Builder) const override { 612 // PSP defines; list based on the output of the pspdev gcc toolchain. 613 Builder.defineMacro("PSP"); 614 Builder.defineMacro("_PSP"); 615 Builder.defineMacro("__psp__"); 616 Builder.defineMacro("__ELF__"); 617 } 618 public: 619 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 620 }; 621 622 // PS3 PPU Target 623 template<typename Target> 624 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 // PS3 PPU defines. 629 Builder.defineMacro("__PPC__"); 630 Builder.defineMacro("__PPU__"); 631 Builder.defineMacro("__CELLOS_LV2__"); 632 Builder.defineMacro("__ELF__"); 633 Builder.defineMacro("__LP32__"); 634 Builder.defineMacro("_ARCH_PPC64"); 635 Builder.defineMacro("__powerpc64__"); 636 } 637 public: 638 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 639 : OSTargetInfo<Target>(Triple, Opts) { 640 this->LongWidth = this->LongAlign = 32; 641 this->PointerWidth = this->PointerAlign = 32; 642 this->IntMaxType = TargetInfo::SignedLongLong; 643 this->Int64Type = TargetInfo::SignedLongLong; 644 this->SizeType = TargetInfo::UnsignedInt; 645 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 646 } 647 }; 648 649 template <typename Target> 650 class PS4OSTargetInfo : public OSTargetInfo<Target> { 651 protected: 652 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 653 MacroBuilder &Builder) const override { 654 Builder.defineMacro("__FreeBSD__", "9"); 655 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 656 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 657 DefineStd(Builder, "unix", Opts); 658 Builder.defineMacro("__ELF__"); 659 Builder.defineMacro("__ORBIS__"); 660 } 661 public: 662 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 663 : OSTargetInfo<Target>(Triple, Opts) { 664 this->WCharType = this->UnsignedShort; 665 666 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 667 this->MaxTLSAlign = 256; 668 669 // On PS4, do not honor explicit bit field alignment, 670 // as in "__attribute__((aligned(2))) int b : 1;". 671 this->UseExplicitBitFieldAlignment = false; 672 673 switch (Triple.getArch()) { 674 default: 675 case llvm::Triple::x86_64: 676 this->MCountName = ".mcount"; 677 break; 678 } 679 } 680 }; 681 682 // Solaris target 683 template<typename Target> 684 class SolarisTargetInfo : public OSTargetInfo<Target> { 685 protected: 686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 687 MacroBuilder &Builder) const override { 688 DefineStd(Builder, "sun", Opts); 689 DefineStd(Builder, "unix", Opts); 690 Builder.defineMacro("__ELF__"); 691 Builder.defineMacro("__svr4__"); 692 Builder.defineMacro("__SVR4"); 693 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 694 // newer, but to 500 for everything else. feature_test.h has a check to 695 // ensure that you are not using C99 with an old version of X/Open or C89 696 // with a new version. 697 if (Opts.C99) 698 Builder.defineMacro("_XOPEN_SOURCE", "600"); 699 else 700 Builder.defineMacro("_XOPEN_SOURCE", "500"); 701 if (Opts.CPlusPlus) 702 Builder.defineMacro("__C99FEATURES__"); 703 Builder.defineMacro("_LARGEFILE_SOURCE"); 704 Builder.defineMacro("_LARGEFILE64_SOURCE"); 705 Builder.defineMacro("__EXTENSIONS__"); 706 Builder.defineMacro("_REENTRANT"); 707 } 708 public: 709 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 710 : OSTargetInfo<Target>(Triple, Opts) { 711 this->WCharType = this->SignedInt; 712 // FIXME: WIntType should be SignedLong 713 } 714 }; 715 716 // Windows target 717 template<typename Target> 718 class WindowsTargetInfo : public OSTargetInfo<Target> { 719 protected: 720 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 721 MacroBuilder &Builder) const override { 722 Builder.defineMacro("_WIN32"); 723 } 724 void getVisualStudioDefines(const LangOptions &Opts, 725 MacroBuilder &Builder) const { 726 if (Opts.CPlusPlus) { 727 if (Opts.RTTIData) 728 Builder.defineMacro("_CPPRTTI"); 729 730 if (Opts.CXXExceptions) 731 Builder.defineMacro("_CPPUNWIND"); 732 } 733 734 if (Opts.Bool) 735 Builder.defineMacro("__BOOL_DEFINED"); 736 737 if (!Opts.CharIsSigned) 738 Builder.defineMacro("_CHAR_UNSIGNED"); 739 740 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 741 // but it works for now. 742 if (Opts.POSIXThreads) 743 Builder.defineMacro("_MT"); 744 745 if (Opts.MSCompatibilityVersion) { 746 Builder.defineMacro("_MSC_VER", 747 Twine(Opts.MSCompatibilityVersion / 100000)); 748 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 749 // FIXME We cannot encode the revision information into 32-bits 750 Builder.defineMacro("_MSC_BUILD", Twine(1)); 751 752 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 753 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 754 755 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 756 if (Opts.CPlusPlus1z) 757 Builder.defineMacro("_MSVC_LANG", "201403L"); 758 else if (Opts.CPlusPlus14) 759 Builder.defineMacro("_MSVC_LANG", "201402L"); 760 } 761 } 762 763 if (Opts.MicrosoftExt) { 764 Builder.defineMacro("_MSC_EXTENSIONS"); 765 766 if (Opts.CPlusPlus11) { 767 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 768 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 769 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 770 } 771 } 772 773 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 774 } 775 776 public: 777 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 778 : OSTargetInfo<Target>(Triple, Opts) {} 779 }; 780 781 template <typename Target> 782 class NaClTargetInfo : public OSTargetInfo<Target> { 783 protected: 784 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 785 MacroBuilder &Builder) const override { 786 if (Opts.POSIXThreads) 787 Builder.defineMacro("_REENTRANT"); 788 if (Opts.CPlusPlus) 789 Builder.defineMacro("_GNU_SOURCE"); 790 791 DefineStd(Builder, "unix", Opts); 792 Builder.defineMacro("__ELF__"); 793 Builder.defineMacro("__native_client__"); 794 } 795 796 public: 797 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 798 : OSTargetInfo<Target>(Triple, Opts) { 799 this->LongAlign = 32; 800 this->LongWidth = 32; 801 this->PointerAlign = 32; 802 this->PointerWidth = 32; 803 this->IntMaxType = TargetInfo::SignedLongLong; 804 this->Int64Type = TargetInfo::SignedLongLong; 805 this->DoubleAlign = 64; 806 this->LongDoubleWidth = 64; 807 this->LongDoubleAlign = 64; 808 this->LongLongWidth = 64; 809 this->LongLongAlign = 64; 810 this->SizeType = TargetInfo::UnsignedInt; 811 this->PtrDiffType = TargetInfo::SignedInt; 812 this->IntPtrType = TargetInfo::SignedInt; 813 // RegParmMax is inherited from the underlying architecture. 814 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 815 if (Triple.getArch() == llvm::Triple::arm) { 816 // Handled in ARM's setABI(). 817 } else if (Triple.getArch() == llvm::Triple::x86) { 818 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 819 } else if (Triple.getArch() == llvm::Triple::x86_64) { 820 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 821 } else if (Triple.getArch() == llvm::Triple::mipsel) { 822 // Handled on mips' setDataLayout. 823 } else { 824 assert(Triple.getArch() == llvm::Triple::le32); 825 this->resetDataLayout("e-p:32:32-i64:64"); 826 } 827 } 828 }; 829 830 // Fuchsia Target 831 template<typename Target> 832 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 833 protected: 834 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 835 MacroBuilder &Builder) const override { 836 Builder.defineMacro("__Fuchsia__"); 837 Builder.defineMacro("__ELF__"); 838 if (Opts.POSIXThreads) 839 Builder.defineMacro("_REENTRANT"); 840 // Required by the libc++ locale support. 841 if (Opts.CPlusPlus) 842 Builder.defineMacro("_GNU_SOURCE"); 843 } 844 public: 845 FuchsiaTargetInfo(const llvm::Triple &Triple, 846 const TargetOptions &Opts) 847 : OSTargetInfo<Target>(Triple, Opts) { 848 this->MCountName = "__mcount"; 849 } 850 }; 851 852 // WebAssembly target 853 template <typename Target> 854 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 855 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 856 MacroBuilder &Builder) const final { 857 // A common platform macro. 858 if (Opts.POSIXThreads) 859 Builder.defineMacro("_REENTRANT"); 860 // Follow g++ convention and predefine _GNU_SOURCE for C++. 861 if (Opts.CPlusPlus) 862 Builder.defineMacro("_GNU_SOURCE"); 863 } 864 865 // As an optimization, group static init code together in a section. 866 const char *getStaticInitSectionSpecifier() const final { 867 return ".text.__startup"; 868 } 869 870 public: 871 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 872 const TargetOptions &Opts) 873 : OSTargetInfo<Target>(Triple, Opts) { 874 this->MCountName = "__mcount"; 875 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 876 } 877 }; 878 879 //===----------------------------------------------------------------------===// 880 // Specific target implementations. 881 //===----------------------------------------------------------------------===// 882 883 // PPC abstract base class 884 class PPCTargetInfo : public TargetInfo { 885 static const Builtin::Info BuiltinInfo[]; 886 static const char * const GCCRegNames[]; 887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 888 std::string CPU; 889 890 // Target cpu features. 891 bool HasAltivec; 892 bool HasVSX; 893 bool HasP8Vector; 894 bool HasP8Crypto; 895 bool HasDirectMove; 896 bool HasQPX; 897 bool HasHTM; 898 bool HasBPERMD; 899 bool HasExtDiv; 900 bool HasP9Vector; 901 902 protected: 903 std::string ABI; 904 905 public: 906 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 907 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 908 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 909 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 910 SimdDefaultAlign = 128; 911 LongDoubleWidth = LongDoubleAlign = 128; 912 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 913 } 914 915 /// \brief Flags for architecture specific defines. 916 typedef enum { 917 ArchDefineNone = 0, 918 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 919 ArchDefinePpcgr = 1 << 1, 920 ArchDefinePpcsq = 1 << 2, 921 ArchDefine440 = 1 << 3, 922 ArchDefine603 = 1 << 4, 923 ArchDefine604 = 1 << 5, 924 ArchDefinePwr4 = 1 << 6, 925 ArchDefinePwr5 = 1 << 7, 926 ArchDefinePwr5x = 1 << 8, 927 ArchDefinePwr6 = 1 << 9, 928 ArchDefinePwr6x = 1 << 10, 929 ArchDefinePwr7 = 1 << 11, 930 ArchDefinePwr8 = 1 << 12, 931 ArchDefinePwr9 = 1 << 13, 932 ArchDefineA2 = 1 << 14, 933 ArchDefineA2q = 1 << 15 934 } ArchDefineTypes; 935 936 // Set the language option for altivec based on our value. 937 void adjust(LangOptions &Opts) override { 938 if (HasAltivec) 939 Opts.AltiVec = 1; 940 TargetInfo::adjust(Opts); 941 } 942 943 // Note: GCC recognizes the following additional cpus: 944 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 945 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 946 // titan, rs64. 947 bool setCPU(const std::string &Name) override { 948 bool CPUKnown = llvm::StringSwitch<bool>(Name) 949 .Case("generic", true) 950 .Case("440", true) 951 .Case("450", true) 952 .Case("601", true) 953 .Case("602", true) 954 .Case("603", true) 955 .Case("603e", true) 956 .Case("603ev", true) 957 .Case("604", true) 958 .Case("604e", true) 959 .Case("620", true) 960 .Case("630", true) 961 .Case("g3", true) 962 .Case("7400", true) 963 .Case("g4", true) 964 .Case("7450", true) 965 .Case("g4+", true) 966 .Case("750", true) 967 .Case("970", true) 968 .Case("g5", true) 969 .Case("a2", true) 970 .Case("a2q", true) 971 .Case("e500mc", true) 972 .Case("e5500", true) 973 .Case("power3", true) 974 .Case("pwr3", true) 975 .Case("power4", true) 976 .Case("pwr4", true) 977 .Case("power5", true) 978 .Case("pwr5", true) 979 .Case("power5x", true) 980 .Case("pwr5x", true) 981 .Case("power6", true) 982 .Case("pwr6", true) 983 .Case("power6x", true) 984 .Case("pwr6x", true) 985 .Case("power7", true) 986 .Case("pwr7", true) 987 .Case("power8", true) 988 .Case("pwr8", true) 989 .Case("power9", true) 990 .Case("pwr9", true) 991 .Case("powerpc", true) 992 .Case("ppc", true) 993 .Case("powerpc64", true) 994 .Case("ppc64", true) 995 .Case("powerpc64le", true) 996 .Case("ppc64le", true) 997 .Default(false); 998 999 if (CPUKnown) 1000 CPU = Name; 1001 1002 return CPUKnown; 1003 } 1004 1005 1006 StringRef getABI() const override { return ABI; } 1007 1008 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1009 return llvm::makeArrayRef(BuiltinInfo, 1010 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1011 } 1012 1013 bool isCLZForZeroUndef() const override { return false; } 1014 1015 void getTargetDefines(const LangOptions &Opts, 1016 MacroBuilder &Builder) const override; 1017 1018 bool 1019 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1020 StringRef CPU, 1021 const std::vector<std::string> &FeaturesVec) const override; 1022 1023 bool handleTargetFeatures(std::vector<std::string> &Features, 1024 DiagnosticsEngine &Diags) override; 1025 bool hasFeature(StringRef Feature) const override; 1026 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1027 bool Enabled) const override; 1028 1029 ArrayRef<const char *> getGCCRegNames() const override; 1030 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1031 bool validateAsmConstraint(const char *&Name, 1032 TargetInfo::ConstraintInfo &Info) const override { 1033 switch (*Name) { 1034 default: return false; 1035 case 'O': // Zero 1036 break; 1037 case 'b': // Base register 1038 case 'f': // Floating point register 1039 Info.setAllowsRegister(); 1040 break; 1041 // FIXME: The following are added to allow parsing. 1042 // I just took a guess at what the actions should be. 1043 // Also, is more specific checking needed? I.e. specific registers? 1044 case 'd': // Floating point register (containing 64-bit value) 1045 case 'v': // Altivec vector register 1046 Info.setAllowsRegister(); 1047 break; 1048 case 'w': 1049 switch (Name[1]) { 1050 case 'd':// VSX vector register to hold vector double data 1051 case 'f':// VSX vector register to hold vector float data 1052 case 's':// VSX vector register to hold scalar float data 1053 case 'a':// Any VSX register 1054 case 'c':// An individual CR bit 1055 break; 1056 default: 1057 return false; 1058 } 1059 Info.setAllowsRegister(); 1060 Name++; // Skip over 'w'. 1061 break; 1062 case 'h': // `MQ', `CTR', or `LINK' register 1063 case 'q': // `MQ' register 1064 case 'c': // `CTR' register 1065 case 'l': // `LINK' register 1066 case 'x': // `CR' register (condition register) number 0 1067 case 'y': // `CR' register (condition register) 1068 case 'z': // `XER[CA]' carry bit (part of the XER register) 1069 Info.setAllowsRegister(); 1070 break; 1071 case 'I': // Signed 16-bit constant 1072 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1073 // (use `L' instead for SImode constants) 1074 case 'K': // Unsigned 16-bit constant 1075 case 'L': // Signed 16-bit constant shifted left 16 bits 1076 case 'M': // Constant larger than 31 1077 case 'N': // Exact power of 2 1078 case 'P': // Constant whose negation is a signed 16-bit constant 1079 case 'G': // Floating point constant that can be loaded into a 1080 // register with one instruction per word 1081 case 'H': // Integer/Floating point constant that can be loaded 1082 // into a register using three instructions 1083 break; 1084 case 'm': // Memory operand. Note that on PowerPC targets, m can 1085 // include addresses that update the base register. It 1086 // is therefore only safe to use `m' in an asm statement 1087 // if that asm statement accesses the operand exactly once. 1088 // The asm statement must also use `%U<opno>' as a 1089 // placeholder for the "update" flag in the corresponding 1090 // load or store instruction. For example: 1091 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1092 // is correct but: 1093 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1094 // is not. Use es rather than m if you don't want the base 1095 // register to be updated. 1096 case 'e': 1097 if (Name[1] != 's') 1098 return false; 1099 // es: A "stable" memory operand; that is, one which does not 1100 // include any automodification of the base register. Unlike 1101 // `m', this constraint can be used in asm statements that 1102 // might access the operand several times, or that might not 1103 // access it at all. 1104 Info.setAllowsMemory(); 1105 Name++; // Skip over 'e'. 1106 break; 1107 case 'Q': // Memory operand that is an offset from a register (it is 1108 // usually better to use `m' or `es' in asm statements) 1109 case 'Z': // Memory operand that is an indexed or indirect from a 1110 // register (it is usually better to use `m' or `es' in 1111 // asm statements) 1112 Info.setAllowsMemory(); 1113 Info.setAllowsRegister(); 1114 break; 1115 case 'R': // AIX TOC entry 1116 case 'a': // Address operand that is an indexed or indirect from a 1117 // register (`p' is preferable for asm statements) 1118 case 'S': // Constant suitable as a 64-bit mask operand 1119 case 'T': // Constant suitable as a 32-bit mask operand 1120 case 'U': // System V Release 4 small data area reference 1121 case 't': // AND masks that can be performed by two rldic{l, r} 1122 // instructions 1123 case 'W': // Vector constant that does not require memory 1124 case 'j': // Vector constant that is all zeros. 1125 break; 1126 // End FIXME. 1127 } 1128 return true; 1129 } 1130 std::string convertConstraint(const char *&Constraint) const override { 1131 std::string R; 1132 switch (*Constraint) { 1133 case 'e': 1134 case 'w': 1135 // Two-character constraint; add "^" hint for later parsing. 1136 R = std::string("^") + std::string(Constraint, 2); 1137 Constraint++; 1138 break; 1139 default: 1140 return TargetInfo::convertConstraint(Constraint); 1141 } 1142 return R; 1143 } 1144 const char *getClobbers() const override { 1145 return ""; 1146 } 1147 int getEHDataRegisterNumber(unsigned RegNo) const override { 1148 if (RegNo == 0) return 3; 1149 if (RegNo == 1) return 4; 1150 return -1; 1151 } 1152 1153 bool hasSjLjLowering() const override { 1154 return true; 1155 } 1156 1157 bool useFloat128ManglingForLongDouble() const override { 1158 return LongDoubleWidth == 128 && 1159 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1160 getTriple().isOSBinFormatELF(); 1161 } 1162 }; 1163 1164 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1165 #define BUILTIN(ID, TYPE, ATTRS) \ 1166 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1167 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1168 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1169 #include "clang/Basic/BuiltinsPPC.def" 1170 }; 1171 1172 /// handleTargetFeatures - Perform initialization based on the user 1173 /// configured set of features. 1174 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1175 DiagnosticsEngine &Diags) { 1176 for (const auto &Feature : Features) { 1177 if (Feature == "+altivec") { 1178 HasAltivec = true; 1179 } else if (Feature == "+vsx") { 1180 HasVSX = true; 1181 } else if (Feature == "+bpermd") { 1182 HasBPERMD = true; 1183 } else if (Feature == "+extdiv") { 1184 HasExtDiv = true; 1185 } else if (Feature == "+power8-vector") { 1186 HasP8Vector = true; 1187 } else if (Feature == "+crypto") { 1188 HasP8Crypto = true; 1189 } else if (Feature == "+direct-move") { 1190 HasDirectMove = true; 1191 } else if (Feature == "+qpx") { 1192 HasQPX = true; 1193 } else if (Feature == "+htm") { 1194 HasHTM = true; 1195 } else if (Feature == "+float128") { 1196 HasFloat128 = true; 1197 } else if (Feature == "+power9-vector") { 1198 HasP9Vector = true; 1199 } 1200 // TODO: Finish this list and add an assert that we've handled them 1201 // all. 1202 } 1203 1204 return true; 1205 } 1206 1207 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1208 /// #defines that are not tied to a specific subtarget. 1209 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1210 MacroBuilder &Builder) const { 1211 // Target identification. 1212 Builder.defineMacro("__ppc__"); 1213 Builder.defineMacro("__PPC__"); 1214 Builder.defineMacro("_ARCH_PPC"); 1215 Builder.defineMacro("__powerpc__"); 1216 Builder.defineMacro("__POWERPC__"); 1217 if (PointerWidth == 64) { 1218 Builder.defineMacro("_ARCH_PPC64"); 1219 Builder.defineMacro("__powerpc64__"); 1220 Builder.defineMacro("__ppc64__"); 1221 Builder.defineMacro("__PPC64__"); 1222 } 1223 1224 // Target properties. 1225 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1226 Builder.defineMacro("_LITTLE_ENDIAN"); 1227 } else { 1228 if (getTriple().getOS() != llvm::Triple::NetBSD && 1229 getTriple().getOS() != llvm::Triple::OpenBSD) 1230 Builder.defineMacro("_BIG_ENDIAN"); 1231 } 1232 1233 // ABI options. 1234 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1235 Builder.defineMacro("_CALL_ELF", "1"); 1236 if (ABI == "elfv2") 1237 Builder.defineMacro("_CALL_ELF", "2"); 1238 1239 // Subtarget options. 1240 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1241 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1242 1243 // FIXME: Should be controlled by command line option. 1244 if (LongDoubleWidth == 128) 1245 Builder.defineMacro("__LONG_DOUBLE_128__"); 1246 1247 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1248 if (ABI == "elfv2" || 1249 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1250 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1251 1252 // CPU identification. 1253 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1254 .Case("440", ArchDefineName) 1255 .Case("450", ArchDefineName | ArchDefine440) 1256 .Case("601", ArchDefineName) 1257 .Case("602", ArchDefineName | ArchDefinePpcgr) 1258 .Case("603", ArchDefineName | ArchDefinePpcgr) 1259 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1260 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1261 .Case("604", ArchDefineName | ArchDefinePpcgr) 1262 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1263 .Case("620", ArchDefineName | ArchDefinePpcgr) 1264 .Case("630", ArchDefineName | ArchDefinePpcgr) 1265 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1266 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1267 .Case("750", ArchDefineName | ArchDefinePpcgr) 1268 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1269 | ArchDefinePpcsq) 1270 .Case("a2", ArchDefineA2) 1271 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1272 .Case("pwr3", ArchDefinePpcgr) 1273 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1274 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1275 | ArchDefinePpcsq) 1276 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1277 | ArchDefinePpcgr | ArchDefinePpcsq) 1278 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1279 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1280 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1281 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1282 | ArchDefinePpcsq) 1283 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1284 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1285 | ArchDefinePpcgr | ArchDefinePpcsq) 1286 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1287 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1288 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1290 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1291 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1292 | ArchDefinePpcsq) 1293 .Case("power3", ArchDefinePpcgr) 1294 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1295 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1296 | ArchDefinePpcsq) 1297 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1298 | ArchDefinePpcgr | ArchDefinePpcsq) 1299 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1300 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1301 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1302 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1303 | ArchDefinePpcsq) 1304 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1305 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1306 | ArchDefinePpcgr | ArchDefinePpcsq) 1307 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1308 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1309 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1311 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1312 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1313 | ArchDefinePpcsq) 1314 .Default(ArchDefineNone); 1315 1316 if (defs & ArchDefineName) 1317 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1318 if (defs & ArchDefinePpcgr) 1319 Builder.defineMacro("_ARCH_PPCGR"); 1320 if (defs & ArchDefinePpcsq) 1321 Builder.defineMacro("_ARCH_PPCSQ"); 1322 if (defs & ArchDefine440) 1323 Builder.defineMacro("_ARCH_440"); 1324 if (defs & ArchDefine603) 1325 Builder.defineMacro("_ARCH_603"); 1326 if (defs & ArchDefine604) 1327 Builder.defineMacro("_ARCH_604"); 1328 if (defs & ArchDefinePwr4) 1329 Builder.defineMacro("_ARCH_PWR4"); 1330 if (defs & ArchDefinePwr5) 1331 Builder.defineMacro("_ARCH_PWR5"); 1332 if (defs & ArchDefinePwr5x) 1333 Builder.defineMacro("_ARCH_PWR5X"); 1334 if (defs & ArchDefinePwr6) 1335 Builder.defineMacro("_ARCH_PWR6"); 1336 if (defs & ArchDefinePwr6x) 1337 Builder.defineMacro("_ARCH_PWR6X"); 1338 if (defs & ArchDefinePwr7) 1339 Builder.defineMacro("_ARCH_PWR7"); 1340 if (defs & ArchDefinePwr8) 1341 Builder.defineMacro("_ARCH_PWR8"); 1342 if (defs & ArchDefinePwr9) 1343 Builder.defineMacro("_ARCH_PWR9"); 1344 if (defs & ArchDefineA2) 1345 Builder.defineMacro("_ARCH_A2"); 1346 if (defs & ArchDefineA2q) { 1347 Builder.defineMacro("_ARCH_A2Q"); 1348 Builder.defineMacro("_ARCH_QP"); 1349 } 1350 1351 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1352 Builder.defineMacro("__bg__"); 1353 Builder.defineMacro("__THW_BLUEGENE__"); 1354 Builder.defineMacro("__bgq__"); 1355 Builder.defineMacro("__TOS_BGQ__"); 1356 } 1357 1358 if (HasAltivec) { 1359 Builder.defineMacro("__VEC__", "10206"); 1360 Builder.defineMacro("__ALTIVEC__"); 1361 } 1362 if (HasVSX) 1363 Builder.defineMacro("__VSX__"); 1364 if (HasP8Vector) 1365 Builder.defineMacro("__POWER8_VECTOR__"); 1366 if (HasP8Crypto) 1367 Builder.defineMacro("__CRYPTO__"); 1368 if (HasHTM) 1369 Builder.defineMacro("__HTM__"); 1370 if (HasFloat128) 1371 Builder.defineMacro("__FLOAT128__"); 1372 if (HasP9Vector) 1373 Builder.defineMacro("__POWER9_VECTOR__"); 1374 1375 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1376 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1377 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1378 if (PointerWidth == 64) 1379 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1380 1381 // FIXME: The following are not yet generated here by Clang, but are 1382 // generated by GCC: 1383 // 1384 // _SOFT_FLOAT_ 1385 // __RECIP_PRECISION__ 1386 // __APPLE_ALTIVEC__ 1387 // __RECIP__ 1388 // __RECIPF__ 1389 // __RSQRTE__ 1390 // __RSQRTEF__ 1391 // _SOFT_DOUBLE_ 1392 // __NO_LWSYNC__ 1393 // __HAVE_BSWAP__ 1394 // __LONGDOUBLE128 1395 // __CMODEL_MEDIUM__ 1396 // __CMODEL_LARGE__ 1397 // _CALL_SYSV 1398 // _CALL_DARWIN 1399 // __NO_FPRS__ 1400 } 1401 1402 // Handle explicit options being passed to the compiler here: if we've 1403 // explicitly turned off vsx and turned on any of: 1404 // - power8-vector 1405 // - direct-move 1406 // - float128 1407 // - power9-vector 1408 // then go ahead and error since the customer has expressed an incompatible 1409 // set of options. 1410 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1411 const std::vector<std::string> &FeaturesVec) { 1412 1413 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1414 FeaturesVec.end()) { 1415 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1416 FeaturesVec.end()) { 1417 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1418 << "-mno-vsx"; 1419 return false; 1420 } 1421 1422 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1423 FeaturesVec.end()) { 1424 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1425 << "-mno-vsx"; 1426 return false; 1427 } 1428 1429 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1430 FeaturesVec.end()) { 1431 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1432 << "-mno-vsx"; 1433 return false; 1434 } 1435 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 } 1443 1444 return true; 1445 } 1446 1447 bool PPCTargetInfo::initFeatureMap( 1448 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1449 const std::vector<std::string> &FeaturesVec) const { 1450 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1451 .Case("7400", true) 1452 .Case("g4", true) 1453 .Case("7450", true) 1454 .Case("g4+", true) 1455 .Case("970", true) 1456 .Case("g5", true) 1457 .Case("pwr6", true) 1458 .Case("pwr7", true) 1459 .Case("pwr8", true) 1460 .Case("pwr9", true) 1461 .Case("ppc64", true) 1462 .Case("ppc64le", true) 1463 .Default(false); 1464 1465 Features["qpx"] = (CPU == "a2q"); 1466 Features["power9-vector"] = (CPU == "pwr9"); 1467 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1468 .Case("ppc64le", true) 1469 .Case("pwr9", true) 1470 .Case("pwr8", true) 1471 .Default(false); 1472 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1473 .Case("ppc64le", true) 1474 .Case("pwr9", true) 1475 .Case("pwr8", true) 1476 .Default(false); 1477 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1478 .Case("ppc64le", true) 1479 .Case("pwr9", true) 1480 .Case("pwr8", true) 1481 .Case("pwr7", true) 1482 .Default(false); 1483 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1484 .Case("ppc64le", true) 1485 .Case("pwr9", true) 1486 .Case("pwr8", true) 1487 .Case("pwr7", true) 1488 .Default(false); 1489 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1490 .Case("ppc64le", true) 1491 .Case("pwr9", true) 1492 .Case("pwr8", true) 1493 .Default(false); 1494 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1495 .Case("ppc64le", true) 1496 .Case("pwr9", true) 1497 .Case("pwr8", true) 1498 .Case("pwr7", true) 1499 .Default(false); 1500 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1501 .Case("ppc64le", true) 1502 .Case("pwr9", true) 1503 .Case("pwr8", true) 1504 .Default(false); 1505 1506 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1507 return false; 1508 1509 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1510 } 1511 1512 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1513 return llvm::StringSwitch<bool>(Feature) 1514 .Case("powerpc", true) 1515 .Case("altivec", HasAltivec) 1516 .Case("vsx", HasVSX) 1517 .Case("power8-vector", HasP8Vector) 1518 .Case("crypto", HasP8Crypto) 1519 .Case("direct-move", HasDirectMove) 1520 .Case("qpx", HasQPX) 1521 .Case("htm", HasHTM) 1522 .Case("bpermd", HasBPERMD) 1523 .Case("extdiv", HasExtDiv) 1524 .Case("float128", HasFloat128) 1525 .Case("power9-vector", HasP9Vector) 1526 .Default(false); 1527 } 1528 1529 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1530 StringRef Name, bool Enabled) const { 1531 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1532 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1533 // incompatible options. 1534 if (Enabled) { 1535 if (Name == "direct-move" || 1536 Name == "power8-vector" || 1537 Name == "float128" || 1538 Name == "power9-vector") { 1539 // power9-vector is really a superset of power8-vector so encode that. 1540 Features[Name] = Features["vsx"] = true; 1541 if (Name == "power9-vector") 1542 Features["power8-vector"] = true; 1543 } else { 1544 Features[Name] = true; 1545 } 1546 } else { 1547 if (Name == "vsx") { 1548 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1549 Features["float128"] = Features["power9-vector"] = false; 1550 } else { 1551 Features[Name] = false; 1552 } 1553 } 1554 } 1555 1556 const char * const PPCTargetInfo::GCCRegNames[] = { 1557 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1558 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1559 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1560 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1561 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1562 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1563 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1564 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1565 "mq", "lr", "ctr", "ap", 1566 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1567 "xer", 1568 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1569 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1570 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1571 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1572 "vrsave", "vscr", 1573 "spe_acc", "spefscr", 1574 "sfp" 1575 }; 1576 1577 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1578 return llvm::makeArrayRef(GCCRegNames); 1579 } 1580 1581 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1582 // While some of these aliases do map to different registers 1583 // they still share the same register name. 1584 { { "0" }, "r0" }, 1585 { { "1"}, "r1" }, 1586 { { "2" }, "r2" }, 1587 { { "3" }, "r3" }, 1588 { { "4" }, "r4" }, 1589 { { "5" }, "r5" }, 1590 { { "6" }, "r6" }, 1591 { { "7" }, "r7" }, 1592 { { "8" }, "r8" }, 1593 { { "9" }, "r9" }, 1594 { { "10" }, "r10" }, 1595 { { "11" }, "r11" }, 1596 { { "12" }, "r12" }, 1597 { { "13" }, "r13" }, 1598 { { "14" }, "r14" }, 1599 { { "15" }, "r15" }, 1600 { { "16" }, "r16" }, 1601 { { "17" }, "r17" }, 1602 { { "18" }, "r18" }, 1603 { { "19" }, "r19" }, 1604 { { "20" }, "r20" }, 1605 { { "21" }, "r21" }, 1606 { { "22" }, "r22" }, 1607 { { "23" }, "r23" }, 1608 { { "24" }, "r24" }, 1609 { { "25" }, "r25" }, 1610 { { "26" }, "r26" }, 1611 { { "27" }, "r27" }, 1612 { { "28" }, "r28" }, 1613 { { "29" }, "r29" }, 1614 { { "30" }, "r30" }, 1615 { { "31" }, "r31" }, 1616 { { "fr0" }, "f0" }, 1617 { { "fr1" }, "f1" }, 1618 { { "fr2" }, "f2" }, 1619 { { "fr3" }, "f3" }, 1620 { { "fr4" }, "f4" }, 1621 { { "fr5" }, "f5" }, 1622 { { "fr6" }, "f6" }, 1623 { { "fr7" }, "f7" }, 1624 { { "fr8" }, "f8" }, 1625 { { "fr9" }, "f9" }, 1626 { { "fr10" }, "f10" }, 1627 { { "fr11" }, "f11" }, 1628 { { "fr12" }, "f12" }, 1629 { { "fr13" }, "f13" }, 1630 { { "fr14" }, "f14" }, 1631 { { "fr15" }, "f15" }, 1632 { { "fr16" }, "f16" }, 1633 { { "fr17" }, "f17" }, 1634 { { "fr18" }, "f18" }, 1635 { { "fr19" }, "f19" }, 1636 { { "fr20" }, "f20" }, 1637 { { "fr21" }, "f21" }, 1638 { { "fr22" }, "f22" }, 1639 { { "fr23" }, "f23" }, 1640 { { "fr24" }, "f24" }, 1641 { { "fr25" }, "f25" }, 1642 { { "fr26" }, "f26" }, 1643 { { "fr27" }, "f27" }, 1644 { { "fr28" }, "f28" }, 1645 { { "fr29" }, "f29" }, 1646 { { "fr30" }, "f30" }, 1647 { { "fr31" }, "f31" }, 1648 { { "cc" }, "cr0" }, 1649 }; 1650 1651 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1652 return llvm::makeArrayRef(GCCRegAliases); 1653 } 1654 1655 class PPC32TargetInfo : public PPCTargetInfo { 1656 public: 1657 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1658 : PPCTargetInfo(Triple, Opts) { 1659 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1660 1661 switch (getTriple().getOS()) { 1662 case llvm::Triple::Linux: 1663 case llvm::Triple::FreeBSD: 1664 case llvm::Triple::NetBSD: 1665 SizeType = UnsignedInt; 1666 PtrDiffType = SignedInt; 1667 IntPtrType = SignedInt; 1668 break; 1669 default: 1670 break; 1671 } 1672 1673 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1674 LongDoubleWidth = LongDoubleAlign = 64; 1675 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1676 } 1677 1678 // PPC32 supports atomics up to 4 bytes. 1679 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1680 } 1681 1682 BuiltinVaListKind getBuiltinVaListKind() const override { 1683 // This is the ELF definition, and is overridden by the Darwin sub-target 1684 return TargetInfo::PowerABIBuiltinVaList; 1685 } 1686 }; 1687 1688 // Note: ABI differences may eventually require us to have a separate 1689 // TargetInfo for little endian. 1690 class PPC64TargetInfo : public PPCTargetInfo { 1691 public: 1692 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1693 : PPCTargetInfo(Triple, Opts) { 1694 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1695 IntMaxType = SignedLong; 1696 Int64Type = SignedLong; 1697 1698 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1699 resetDataLayout("e-m:e-i64:64-n32:64"); 1700 ABI = "elfv2"; 1701 } else { 1702 resetDataLayout("E-m:e-i64:64-n32:64"); 1703 ABI = "elfv1"; 1704 } 1705 1706 switch (getTriple().getOS()) { 1707 case llvm::Triple::FreeBSD: 1708 LongDoubleWidth = LongDoubleAlign = 64; 1709 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1710 break; 1711 case llvm::Triple::NetBSD: 1712 IntMaxType = SignedLongLong; 1713 Int64Type = SignedLongLong; 1714 break; 1715 default: 1716 break; 1717 } 1718 1719 // PPC64 supports atomics up to 8 bytes. 1720 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1721 } 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 return TargetInfo::CharPtrBuiltinVaList; 1724 } 1725 // PPC64 Linux-specific ABI options. 1726 bool setABI(const std::string &Name) override { 1727 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1728 ABI = Name; 1729 return true; 1730 } 1731 return false; 1732 } 1733 }; 1734 1735 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1736 public: 1737 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1738 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1739 HasAlignMac68kSupport = true; 1740 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1741 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1742 LongLongAlign = 32; 1743 SuitableAlign = 128; 1744 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1745 } 1746 BuiltinVaListKind getBuiltinVaListKind() const override { 1747 return TargetInfo::CharPtrBuiltinVaList; 1748 } 1749 }; 1750 1751 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1752 public: 1753 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1754 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1755 HasAlignMac68kSupport = true; 1756 SuitableAlign = 128; 1757 resetDataLayout("E-m:o-i64:64-n32:64"); 1758 } 1759 }; 1760 1761 static const unsigned NVPTXAddrSpaceMap[] = { 1762 1, // opencl_global 1763 3, // opencl_local 1764 4, // opencl_constant 1765 // FIXME: generic has to be added to the target 1766 0, // opencl_generic 1767 1, // cuda_device 1768 4, // cuda_constant 1769 3, // cuda_shared 1770 }; 1771 1772 class NVPTXTargetInfo : public TargetInfo { 1773 static const char *const GCCRegNames[]; 1774 static const Builtin::Info BuiltinInfo[]; 1775 CudaArch GPU; 1776 std::unique_ptr<TargetInfo> HostTarget; 1777 1778 public: 1779 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1780 unsigned TargetPointerWidth) 1781 : TargetInfo(Triple) { 1782 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1783 "NVPTX only supports 32- and 64-bit modes."); 1784 1785 TLSSupported = false; 1786 AddrSpaceMap = &NVPTXAddrSpaceMap; 1787 UseAddrSpaceMapMangling = true; 1788 1789 // Define available target features 1790 // These must be defined in sorted order! 1791 NoAsmVariants = true; 1792 GPU = CudaArch::SM_20; 1793 1794 if (TargetPointerWidth == 32) 1795 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1796 else 1797 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1798 1799 // If possible, get a TargetInfo for our host triple, so we can match its 1800 // types. 1801 llvm::Triple HostTriple(Opts.HostTriple); 1802 if (!HostTriple.isNVPTX()) 1803 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1804 1805 // If no host target, make some guesses about the data layout and return. 1806 if (!HostTarget) { 1807 LongWidth = LongAlign = TargetPointerWidth; 1808 PointerWidth = PointerAlign = TargetPointerWidth; 1809 switch (TargetPointerWidth) { 1810 case 32: 1811 SizeType = TargetInfo::UnsignedInt; 1812 PtrDiffType = TargetInfo::SignedInt; 1813 IntPtrType = TargetInfo::SignedInt; 1814 break; 1815 case 64: 1816 SizeType = TargetInfo::UnsignedLong; 1817 PtrDiffType = TargetInfo::SignedLong; 1818 IntPtrType = TargetInfo::SignedLong; 1819 break; 1820 default: 1821 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1822 } 1823 return; 1824 } 1825 1826 // Copy properties from host target. 1827 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1828 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1829 BoolWidth = HostTarget->getBoolWidth(); 1830 BoolAlign = HostTarget->getBoolAlign(); 1831 IntWidth = HostTarget->getIntWidth(); 1832 IntAlign = HostTarget->getIntAlign(); 1833 HalfWidth = HostTarget->getHalfWidth(); 1834 HalfAlign = HostTarget->getHalfAlign(); 1835 FloatWidth = HostTarget->getFloatWidth(); 1836 FloatAlign = HostTarget->getFloatAlign(); 1837 DoubleWidth = HostTarget->getDoubleWidth(); 1838 DoubleAlign = HostTarget->getDoubleAlign(); 1839 LongWidth = HostTarget->getLongWidth(); 1840 LongAlign = HostTarget->getLongAlign(); 1841 LongLongWidth = HostTarget->getLongLongWidth(); 1842 LongLongAlign = HostTarget->getLongLongAlign(); 1843 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1844 NewAlign = HostTarget->getNewAlign(); 1845 DefaultAlignForAttributeAligned = 1846 HostTarget->getDefaultAlignForAttributeAligned(); 1847 SizeType = HostTarget->getSizeType(); 1848 IntMaxType = HostTarget->getIntMaxType(); 1849 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1850 IntPtrType = HostTarget->getIntPtrType(); 1851 WCharType = HostTarget->getWCharType(); 1852 WIntType = HostTarget->getWIntType(); 1853 Char16Type = HostTarget->getChar16Type(); 1854 Char32Type = HostTarget->getChar32Type(); 1855 Int64Type = HostTarget->getInt64Type(); 1856 SigAtomicType = HostTarget->getSigAtomicType(); 1857 ProcessIDType = HostTarget->getProcessIDType(); 1858 1859 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1860 UseZeroLengthBitfieldAlignment = 1861 HostTarget->useZeroLengthBitfieldAlignment(); 1862 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1863 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1864 1865 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1866 // we need those macros to be identical on host and device, because (among 1867 // other things) they affect which standard library classes are defined, and 1868 // we need all classes to be defined on both the host and device. 1869 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1870 1871 // Properties intentionally not copied from host: 1872 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1873 // host/device boundary. 1874 // - SuitableAlign: Not visible across the host/device boundary, and may 1875 // correctly be different on host/device, e.g. if host has wider vector 1876 // types than device. 1877 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1878 // as its double type, but that's not necessarily true on the host. 1879 // TODO: nvcc emits a warning when using long double on device; we should 1880 // do the same. 1881 } 1882 void getTargetDefines(const LangOptions &Opts, 1883 MacroBuilder &Builder) const override { 1884 Builder.defineMacro("__PTX__"); 1885 Builder.defineMacro("__NVPTX__"); 1886 if (Opts.CUDAIsDevice) { 1887 // Set __CUDA_ARCH__ for the GPU specified. 1888 std::string CUDAArchCode = [this] { 1889 switch (GPU) { 1890 case CudaArch::UNKNOWN: 1891 assert(false && "No GPU arch when compiling CUDA device code."); 1892 return ""; 1893 case CudaArch::SM_20: 1894 return "200"; 1895 case CudaArch::SM_21: 1896 return "210"; 1897 case CudaArch::SM_30: 1898 return "300"; 1899 case CudaArch::SM_32: 1900 return "320"; 1901 case CudaArch::SM_35: 1902 return "350"; 1903 case CudaArch::SM_37: 1904 return "370"; 1905 case CudaArch::SM_50: 1906 return "500"; 1907 case CudaArch::SM_52: 1908 return "520"; 1909 case CudaArch::SM_53: 1910 return "530"; 1911 case CudaArch::SM_60: 1912 return "600"; 1913 case CudaArch::SM_61: 1914 return "610"; 1915 case CudaArch::SM_62: 1916 return "620"; 1917 } 1918 llvm_unreachable("unhandled CudaArch"); 1919 }(); 1920 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1921 } 1922 } 1923 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1924 return llvm::makeArrayRef(BuiltinInfo, 1925 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1926 } 1927 bool 1928 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1929 StringRef CPU, 1930 const std::vector<std::string> &FeaturesVec) const override { 1931 Features["satom"] = GPU >= CudaArch::SM_60; 1932 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1933 } 1934 1935 bool hasFeature(StringRef Feature) const override { 1936 return llvm::StringSwitch<bool>(Feature) 1937 .Cases("ptx", "nvptx", true) 1938 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1939 .Default(false); 1940 } 1941 1942 ArrayRef<const char *> getGCCRegNames() const override; 1943 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1944 // No aliases. 1945 return None; 1946 } 1947 bool validateAsmConstraint(const char *&Name, 1948 TargetInfo::ConstraintInfo &Info) const override { 1949 switch (*Name) { 1950 default: 1951 return false; 1952 case 'c': 1953 case 'h': 1954 case 'r': 1955 case 'l': 1956 case 'f': 1957 case 'd': 1958 Info.setAllowsRegister(); 1959 return true; 1960 } 1961 } 1962 const char *getClobbers() const override { 1963 // FIXME: Is this really right? 1964 return ""; 1965 } 1966 BuiltinVaListKind getBuiltinVaListKind() const override { 1967 // FIXME: implement 1968 return TargetInfo::CharPtrBuiltinVaList; 1969 } 1970 bool setCPU(const std::string &Name) override { 1971 GPU = StringToCudaArch(Name); 1972 return GPU != CudaArch::UNKNOWN; 1973 } 1974 void setSupportedOpenCLOpts() override { 1975 auto &Opts = getSupportedOpenCLOpts(); 1976 Opts.support("cl_clang_storage_class_specifiers"); 1977 Opts.support("cl_khr_gl_sharing"); 1978 Opts.support("cl_khr_icd"); 1979 1980 Opts.support("cl_khr_fp64"); 1981 Opts.support("cl_khr_byte_addressable_store"); 1982 Opts.support("cl_khr_global_int32_base_atomics"); 1983 Opts.support("cl_khr_global_int32_extended_atomics"); 1984 Opts.support("cl_khr_local_int32_base_atomics"); 1985 Opts.support("cl_khr_local_int32_extended_atomics"); 1986 } 1987 1988 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 1989 // CUDA compilations support all of the host's calling conventions. 1990 // 1991 // TODO: We should warn if you apply a non-default CC to anything other than 1992 // a host function. 1993 if (HostTarget) 1994 return HostTarget->checkCallingConvention(CC); 1995 return CCCR_Warning; 1996 } 1997 }; 1998 1999 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2000 #define BUILTIN(ID, TYPE, ATTRS) \ 2001 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2002 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2003 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2004 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2005 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2006 #include "clang/Basic/BuiltinsNVPTX.def" 2007 }; 2008 2009 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2010 2011 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2012 return llvm::makeArrayRef(GCCRegNames); 2013 } 2014 2015 static const unsigned AMDGPUAddrSpaceMap[] = { 2016 1, // opencl_global 2017 3, // opencl_local 2018 2, // opencl_constant 2019 4, // opencl_generic 2020 1, // cuda_device 2021 2, // cuda_constant 2022 3 // cuda_shared 2023 }; 2024 2025 // If you edit the description strings, make sure you update 2026 // getPointerWidthV(). 2027 2028 static const char *const DataLayoutStringR600 = 2029 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2030 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2031 2032 static const char *const DataLayoutStringSI = 2033 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2034 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2035 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2036 2037 class AMDGPUTargetInfo final : public TargetInfo { 2038 static const Builtin::Info BuiltinInfo[]; 2039 static const char * const GCCRegNames[]; 2040 2041 /// \brief The GPU profiles supported by the AMDGPU target. 2042 enum GPUKind { 2043 GK_NONE, 2044 GK_R600, 2045 GK_R600_DOUBLE_OPS, 2046 GK_R700, 2047 GK_R700_DOUBLE_OPS, 2048 GK_EVERGREEN, 2049 GK_EVERGREEN_DOUBLE_OPS, 2050 GK_NORTHERN_ISLANDS, 2051 GK_CAYMAN, 2052 GK_GFX6, 2053 GK_GFX7, 2054 GK_GFX8, 2055 GK_GFX9 2056 } GPU; 2057 2058 bool hasFP64:1; 2059 bool hasFMAF:1; 2060 bool hasLDEXPF:1; 2061 bool hasFullSpeedFP32Denorms:1; 2062 2063 static bool isAMDGCN(const llvm::Triple &TT) { 2064 return TT.getArch() == llvm::Triple::amdgcn; 2065 } 2066 2067 public: 2068 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2069 : TargetInfo(Triple) , 2070 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2071 hasFP64(false), 2072 hasFMAF(false), 2073 hasLDEXPF(false), 2074 hasFullSpeedFP32Denorms(false){ 2075 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2076 hasFP64 = true; 2077 hasFMAF = true; 2078 hasLDEXPF = true; 2079 } 2080 2081 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2082 DataLayoutStringSI : DataLayoutStringR600); 2083 2084 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2085 UseAddrSpaceMapMangling = true; 2086 } 2087 2088 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2089 if (GPU <= GK_CAYMAN) 2090 return 32; 2091 2092 switch(AddrSpace) { 2093 default: 2094 return 64; 2095 case 0: 2096 case 3: 2097 case 5: 2098 return 32; 2099 } 2100 } 2101 2102 uint64_t getMaxPointerWidth() const override { 2103 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2104 } 2105 2106 const char * getClobbers() const override { 2107 return ""; 2108 } 2109 2110 ArrayRef<const char *> getGCCRegNames() const override; 2111 2112 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2113 return None; 2114 } 2115 2116 bool validateAsmConstraint(const char *&Name, 2117 TargetInfo::ConstraintInfo &Info) const override { 2118 switch (*Name) { 2119 default: break; 2120 case 'v': // vgpr 2121 case 's': // sgpr 2122 Info.setAllowsRegister(); 2123 return true; 2124 } 2125 return false; 2126 } 2127 2128 bool initFeatureMap(llvm::StringMap<bool> &Features, 2129 DiagnosticsEngine &Diags, StringRef CPU, 2130 const std::vector<std::string> &FeatureVec) const override; 2131 2132 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2133 TargetOptions &TargetOpts) const override { 2134 bool hasFP32Denormals = false; 2135 bool hasFP64Denormals = false; 2136 for (auto &I : TargetOpts.FeaturesAsWritten) { 2137 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2138 hasFP32Denormals = true; 2139 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2140 hasFP64Denormals = true; 2141 } 2142 if (!hasFP32Denormals) 2143 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2144 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2145 // Always do not flush fp64 or fp16 denorms. 2146 if (!hasFP64Denormals && hasFP64) 2147 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2148 } 2149 2150 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2151 return llvm::makeArrayRef(BuiltinInfo, 2152 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2153 } 2154 2155 void getTargetDefines(const LangOptions &Opts, 2156 MacroBuilder &Builder) const override { 2157 if (getTriple().getArch() == llvm::Triple::amdgcn) 2158 Builder.defineMacro("__AMDGCN__"); 2159 else 2160 Builder.defineMacro("__R600__"); 2161 2162 if (hasFMAF) 2163 Builder.defineMacro("__HAS_FMAF__"); 2164 if (hasLDEXPF) 2165 Builder.defineMacro("__HAS_LDEXPF__"); 2166 if (hasFP64) 2167 Builder.defineMacro("__HAS_FP64__"); 2168 } 2169 2170 BuiltinVaListKind getBuiltinVaListKind() const override { 2171 return TargetInfo::CharPtrBuiltinVaList; 2172 } 2173 2174 static GPUKind parseR600Name(StringRef Name) { 2175 return llvm::StringSwitch<GPUKind>(Name) 2176 .Case("r600" , GK_R600) 2177 .Case("rv610", GK_R600) 2178 .Case("rv620", GK_R600) 2179 .Case("rv630", GK_R600) 2180 .Case("rv635", GK_R600) 2181 .Case("rs780", GK_R600) 2182 .Case("rs880", GK_R600) 2183 .Case("rv670", GK_R600_DOUBLE_OPS) 2184 .Case("rv710", GK_R700) 2185 .Case("rv730", GK_R700) 2186 .Case("rv740", GK_R700_DOUBLE_OPS) 2187 .Case("rv770", GK_R700_DOUBLE_OPS) 2188 .Case("palm", GK_EVERGREEN) 2189 .Case("cedar", GK_EVERGREEN) 2190 .Case("sumo", GK_EVERGREEN) 2191 .Case("sumo2", GK_EVERGREEN) 2192 .Case("redwood", GK_EVERGREEN) 2193 .Case("juniper", GK_EVERGREEN) 2194 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2195 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2196 .Case("barts", GK_NORTHERN_ISLANDS) 2197 .Case("turks", GK_NORTHERN_ISLANDS) 2198 .Case("caicos", GK_NORTHERN_ISLANDS) 2199 .Case("cayman", GK_CAYMAN) 2200 .Case("aruba", GK_CAYMAN) 2201 .Default(GK_NONE); 2202 } 2203 2204 static GPUKind parseAMDGCNName(StringRef Name) { 2205 return llvm::StringSwitch<GPUKind>(Name) 2206 .Case("tahiti", GK_GFX6) 2207 .Case("pitcairn", GK_GFX6) 2208 .Case("verde", GK_GFX6) 2209 .Case("oland", GK_GFX6) 2210 .Case("hainan", GK_GFX6) 2211 .Case("bonaire", GK_GFX7) 2212 .Case("kabini", GK_GFX7) 2213 .Case("kaveri", GK_GFX7) 2214 .Case("hawaii", GK_GFX7) 2215 .Case("mullins", GK_GFX7) 2216 .Case("gfx700", GK_GFX7) 2217 .Case("gfx701", GK_GFX7) 2218 .Case("gfx702", GK_GFX7) 2219 .Case("tonga", GK_GFX8) 2220 .Case("iceland", GK_GFX8) 2221 .Case("carrizo", GK_GFX8) 2222 .Case("fiji", GK_GFX8) 2223 .Case("stoney", GK_GFX8) 2224 .Case("polaris10", GK_GFX8) 2225 .Case("polaris11", GK_GFX8) 2226 .Case("gfx800", GK_GFX8) 2227 .Case("gfx801", GK_GFX8) 2228 .Case("gfx802", GK_GFX8) 2229 .Case("gfx803", GK_GFX8) 2230 .Case("gfx804", GK_GFX8) 2231 .Case("gfx810", GK_GFX8) 2232 .Case("gfx900", GK_GFX9) 2233 .Case("gfx901", GK_GFX9) 2234 .Default(GK_NONE); 2235 } 2236 2237 bool setCPU(const std::string &Name) override { 2238 if (getTriple().getArch() == llvm::Triple::amdgcn) 2239 GPU = parseAMDGCNName(Name); 2240 else 2241 GPU = parseR600Name(Name); 2242 2243 return GPU != GK_NONE; 2244 } 2245 2246 void setSupportedOpenCLOpts() override { 2247 auto &Opts = getSupportedOpenCLOpts(); 2248 Opts.support("cl_clang_storage_class_specifiers"); 2249 Opts.support("cl_khr_icd"); 2250 2251 if (hasFP64) 2252 Opts.support("cl_khr_fp64"); 2253 if (GPU >= GK_EVERGREEN) { 2254 Opts.support("cl_khr_byte_addressable_store"); 2255 Opts.support("cl_khr_global_int32_base_atomics"); 2256 Opts.support("cl_khr_global_int32_extended_atomics"); 2257 Opts.support("cl_khr_local_int32_base_atomics"); 2258 Opts.support("cl_khr_local_int32_extended_atomics"); 2259 } 2260 if (GPU >= GK_GFX6) { 2261 Opts.support("cl_khr_fp16"); 2262 Opts.support("cl_khr_int64_base_atomics"); 2263 Opts.support("cl_khr_int64_extended_atomics"); 2264 Opts.support("cl_khr_mipmap_image"); 2265 Opts.support("cl_khr_subgroups"); 2266 Opts.support("cl_khr_3d_image_writes"); 2267 Opts.support("cl_amd_media_ops"); 2268 Opts.support("cl_amd_media_ops2"); 2269 } 2270 } 2271 2272 LangAS::ID getOpenCLImageAddrSpace() const override { 2273 return LangAS::opencl_constant; 2274 } 2275 2276 /// \returns Target specific vtbl ptr address space. 2277 unsigned getVtblPtrAddressSpace() const override { 2278 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2279 // would be nice if we could use it here instead of using bare numbers (same 2280 // applies to getDWARFAddressSpace). 2281 return 2; // constant. 2282 } 2283 2284 /// \returns If a target requires an address within a target specific address 2285 /// space \p AddressSpace to be converted in order to be used, then return the 2286 /// corresponding target specific DWARF address space. 2287 /// 2288 /// \returns Otherwise return None and no conversion will be emitted in the 2289 /// DWARF. 2290 Optional<unsigned> getDWARFAddressSpace( 2291 unsigned AddressSpace) const override { 2292 switch (AddressSpace) { 2293 case 0: // LLVM Private. 2294 return 1; // DWARF Private. 2295 case 3: // LLVM Local. 2296 return 2; // DWARF Local. 2297 default: 2298 return None; 2299 } 2300 } 2301 2302 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2303 switch (CC) { 2304 default: 2305 return CCCR_Warning; 2306 case CC_C: 2307 case CC_OpenCLKernel: 2308 return CCCR_OK; 2309 } 2310 } 2311 2312 // In amdgcn target the null pointer in global, constant, and generic 2313 // address space has value 0 but in private and local address space has 2314 // value ~0. 2315 uint64_t getNullPointerValue(unsigned AS) const override { 2316 return AS == LangAS::opencl_local ? ~0 : 0; 2317 } 2318 }; 2319 2320 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2321 #define BUILTIN(ID, TYPE, ATTRS) \ 2322 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2323 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2324 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2325 #include "clang/Basic/BuiltinsAMDGPU.def" 2326 }; 2327 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2328 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2329 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2330 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2331 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2332 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2333 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2334 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2335 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2336 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2337 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2338 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2339 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2340 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2341 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2342 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2343 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2344 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2345 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2346 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2347 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2348 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2349 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2350 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2351 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2352 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2353 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2354 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2355 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2356 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2357 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2358 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2359 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2360 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2361 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2362 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2363 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2364 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2365 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2366 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2367 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2368 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2369 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2370 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2371 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2372 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2373 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2374 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2375 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2376 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2377 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2378 }; 2379 2380 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2381 return llvm::makeArrayRef(GCCRegNames); 2382 } 2383 2384 bool AMDGPUTargetInfo::initFeatureMap( 2385 llvm::StringMap<bool> &Features, 2386 DiagnosticsEngine &Diags, StringRef CPU, 2387 const std::vector<std::string> &FeatureVec) const { 2388 2389 // XXX - What does the member GPU mean if device name string passed here? 2390 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2391 if (CPU.empty()) 2392 CPU = "tahiti"; 2393 2394 switch (parseAMDGCNName(CPU)) { 2395 case GK_GFX6: 2396 case GK_GFX7: 2397 break; 2398 2399 case GK_GFX9: 2400 Features["gfx9-insts"] = true; 2401 LLVM_FALLTHROUGH; 2402 case GK_GFX8: 2403 Features["s-memrealtime"] = true; 2404 Features["16-bit-insts"] = true; 2405 Features["dpp"] = true; 2406 break; 2407 2408 case GK_NONE: 2409 return false; 2410 default: 2411 llvm_unreachable("unhandled subtarget"); 2412 } 2413 } else { 2414 if (CPU.empty()) 2415 CPU = "r600"; 2416 2417 switch (parseR600Name(CPU)) { 2418 case GK_R600: 2419 case GK_R700: 2420 case GK_EVERGREEN: 2421 case GK_NORTHERN_ISLANDS: 2422 break; 2423 case GK_R600_DOUBLE_OPS: 2424 case GK_R700_DOUBLE_OPS: 2425 case GK_EVERGREEN_DOUBLE_OPS: 2426 case GK_CAYMAN: 2427 Features["fp64"] = true; 2428 break; 2429 case GK_NONE: 2430 return false; 2431 default: 2432 llvm_unreachable("unhandled subtarget"); 2433 } 2434 } 2435 2436 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2437 } 2438 2439 const Builtin::Info BuiltinInfoX86[] = { 2440 #define BUILTIN(ID, TYPE, ATTRS) \ 2441 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2442 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2443 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2444 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2445 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2446 #include "clang/Basic/BuiltinsX86.def" 2447 2448 #define BUILTIN(ID, TYPE, ATTRS) \ 2449 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2450 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2451 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2452 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2453 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2454 #include "clang/Basic/BuiltinsX86_64.def" 2455 }; 2456 2457 2458 static const char* const GCCRegNames[] = { 2459 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2460 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2461 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2462 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2463 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2464 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2465 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2466 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2467 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2468 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2469 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2470 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2471 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2472 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2473 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2474 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2475 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2476 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2477 }; 2478 2479 const TargetInfo::AddlRegName AddlRegNames[] = { 2480 { { "al", "ah", "eax", "rax" }, 0 }, 2481 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2482 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2483 { { "dl", "dh", "edx", "rdx" }, 1 }, 2484 { { "esi", "rsi" }, 4 }, 2485 { { "edi", "rdi" }, 5 }, 2486 { { "esp", "rsp" }, 7 }, 2487 { { "ebp", "rbp" }, 6 }, 2488 { { "r8d", "r8w", "r8b" }, 38 }, 2489 { { "r9d", "r9w", "r9b" }, 39 }, 2490 { { "r10d", "r10w", "r10b" }, 40 }, 2491 { { "r11d", "r11w", "r11b" }, 41 }, 2492 { { "r12d", "r12w", "r12b" }, 42 }, 2493 { { "r13d", "r13w", "r13b" }, 43 }, 2494 { { "r14d", "r14w", "r14b" }, 44 }, 2495 { { "r15d", "r15w", "r15b" }, 45 }, 2496 }; 2497 2498 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2499 // most of the implementation can be shared. 2500 class X86TargetInfo : public TargetInfo { 2501 enum X86SSEEnum { 2502 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2503 } SSELevel = NoSSE; 2504 enum MMX3DNowEnum { 2505 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2506 } MMX3DNowLevel = NoMMX3DNow; 2507 enum XOPEnum { 2508 NoXOP, 2509 SSE4A, 2510 FMA4, 2511 XOP 2512 } XOPLevel = NoXOP; 2513 2514 bool HasAES = false; 2515 bool HasPCLMUL = false; 2516 bool HasLZCNT = false; 2517 bool HasRDRND = false; 2518 bool HasFSGSBASE = false; 2519 bool HasBMI = false; 2520 bool HasBMI2 = false; 2521 bool HasPOPCNT = false; 2522 bool HasRTM = false; 2523 bool HasPRFCHW = false; 2524 bool HasRDSEED = false; 2525 bool HasADX = false; 2526 bool HasTBM = false; 2527 bool HasFMA = false; 2528 bool HasF16C = false; 2529 bool HasAVX512CD = false; 2530 bool HasAVX512ER = false; 2531 bool HasAVX512PF = false; 2532 bool HasAVX512DQ = false; 2533 bool HasAVX512BW = false; 2534 bool HasAVX512VL = false; 2535 bool HasAVX512VBMI = false; 2536 bool HasAVX512IFMA = false; 2537 bool HasSHA = false; 2538 bool HasMPX = false; 2539 bool HasSGX = false; 2540 bool HasCX16 = false; 2541 bool HasFXSR = false; 2542 bool HasXSAVE = false; 2543 bool HasXSAVEOPT = false; 2544 bool HasXSAVEC = false; 2545 bool HasXSAVES = false; 2546 bool HasMWAITX = false; 2547 bool HasCLZERO = false; 2548 bool HasPKU = false; 2549 bool HasCLFLUSHOPT = false; 2550 bool HasCLWB = false; 2551 bool HasMOVBE = false; 2552 bool HasPREFETCHWT1 = false; 2553 2554 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2555 /// 2556 /// Each enumeration represents a particular CPU supported by Clang. These 2557 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2558 enum CPUKind { 2559 CK_Generic, 2560 2561 /// \name i386 2562 /// i386-generation processors. 2563 //@{ 2564 CK_i386, 2565 //@} 2566 2567 /// \name i486 2568 /// i486-generation processors. 2569 //@{ 2570 CK_i486, 2571 CK_WinChipC6, 2572 CK_WinChip2, 2573 CK_C3, 2574 //@} 2575 2576 /// \name i586 2577 /// i586-generation processors, P5 microarchitecture based. 2578 //@{ 2579 CK_i586, 2580 CK_Pentium, 2581 CK_PentiumMMX, 2582 //@} 2583 2584 /// \name i686 2585 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2586 //@{ 2587 CK_i686, 2588 CK_PentiumPro, 2589 CK_Pentium2, 2590 CK_Pentium3, 2591 CK_Pentium3M, 2592 CK_PentiumM, 2593 CK_C3_2, 2594 2595 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2596 /// Clang however has some logic to suport this. 2597 // FIXME: Warn, deprecate, and potentially remove this. 2598 CK_Yonah, 2599 //@} 2600 2601 /// \name Netburst 2602 /// Netburst microarchitecture based processors. 2603 //@{ 2604 CK_Pentium4, 2605 CK_Pentium4M, 2606 CK_Prescott, 2607 CK_Nocona, 2608 //@} 2609 2610 /// \name Core 2611 /// Core microarchitecture based processors. 2612 //@{ 2613 CK_Core2, 2614 2615 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2616 /// codename which GCC no longer accepts as an option to -march, but Clang 2617 /// has some logic for recognizing it. 2618 // FIXME: Warn, deprecate, and potentially remove this. 2619 CK_Penryn, 2620 //@} 2621 2622 /// \name Atom 2623 /// Atom processors 2624 //@{ 2625 CK_Bonnell, 2626 CK_Silvermont, 2627 //@} 2628 2629 /// \name Nehalem 2630 /// Nehalem microarchitecture based processors. 2631 CK_Nehalem, 2632 2633 /// \name Westmere 2634 /// Westmere microarchitecture based processors. 2635 CK_Westmere, 2636 2637 /// \name Sandy Bridge 2638 /// Sandy Bridge microarchitecture based processors. 2639 CK_SandyBridge, 2640 2641 /// \name Ivy Bridge 2642 /// Ivy Bridge microarchitecture based processors. 2643 CK_IvyBridge, 2644 2645 /// \name Haswell 2646 /// Haswell microarchitecture based processors. 2647 CK_Haswell, 2648 2649 /// \name Broadwell 2650 /// Broadwell microarchitecture based processors. 2651 CK_Broadwell, 2652 2653 /// \name Skylake Client 2654 /// Skylake client microarchitecture based processors. 2655 CK_SkylakeClient, 2656 2657 /// \name Skylake Server 2658 /// Skylake server microarchitecture based processors. 2659 CK_SkylakeServer, 2660 2661 /// \name Cannonlake Client 2662 /// Cannonlake client microarchitecture based processors. 2663 CK_Cannonlake, 2664 2665 /// \name Knights Landing 2666 /// Knights Landing processor. 2667 CK_KNL, 2668 2669 /// \name Lakemont 2670 /// Lakemont microarchitecture based processors. 2671 CK_Lakemont, 2672 2673 /// \name K6 2674 /// K6 architecture processors. 2675 //@{ 2676 CK_K6, 2677 CK_K6_2, 2678 CK_K6_3, 2679 //@} 2680 2681 /// \name K7 2682 /// K7 architecture processors. 2683 //@{ 2684 CK_Athlon, 2685 CK_AthlonThunderbird, 2686 CK_Athlon4, 2687 CK_AthlonXP, 2688 CK_AthlonMP, 2689 //@} 2690 2691 /// \name K8 2692 /// K8 architecture processors. 2693 //@{ 2694 CK_Athlon64, 2695 CK_Athlon64SSE3, 2696 CK_AthlonFX, 2697 CK_K8, 2698 CK_K8SSE3, 2699 CK_Opteron, 2700 CK_OpteronSSE3, 2701 CK_AMDFAM10, 2702 //@} 2703 2704 /// \name Bobcat 2705 /// Bobcat architecture processors. 2706 //@{ 2707 CK_BTVER1, 2708 CK_BTVER2, 2709 //@} 2710 2711 /// \name Bulldozer 2712 /// Bulldozer architecture processors. 2713 //@{ 2714 CK_BDVER1, 2715 CK_BDVER2, 2716 CK_BDVER3, 2717 CK_BDVER4, 2718 //@} 2719 2720 /// \name zen 2721 /// Zen architecture processors. 2722 //@{ 2723 CK_ZNVER1, 2724 //@} 2725 2726 /// This specification is deprecated and will be removed in the future. 2727 /// Users should prefer \see CK_K8. 2728 // FIXME: Warn on this when the CPU is set to it. 2729 //@{ 2730 CK_x86_64, 2731 //@} 2732 2733 /// \name Geode 2734 /// Geode processors. 2735 //@{ 2736 CK_Geode 2737 //@} 2738 } CPU = CK_Generic; 2739 2740 CPUKind getCPUKind(StringRef CPU) const { 2741 return llvm::StringSwitch<CPUKind>(CPU) 2742 .Case("i386", CK_i386) 2743 .Case("i486", CK_i486) 2744 .Case("winchip-c6", CK_WinChipC6) 2745 .Case("winchip2", CK_WinChip2) 2746 .Case("c3", CK_C3) 2747 .Case("i586", CK_i586) 2748 .Case("pentium", CK_Pentium) 2749 .Case("pentium-mmx", CK_PentiumMMX) 2750 .Case("i686", CK_i686) 2751 .Case("pentiumpro", CK_PentiumPro) 2752 .Case("pentium2", CK_Pentium2) 2753 .Case("pentium3", CK_Pentium3) 2754 .Case("pentium3m", CK_Pentium3M) 2755 .Case("pentium-m", CK_PentiumM) 2756 .Case("c3-2", CK_C3_2) 2757 .Case("yonah", CK_Yonah) 2758 .Case("pentium4", CK_Pentium4) 2759 .Case("pentium4m", CK_Pentium4M) 2760 .Case("prescott", CK_Prescott) 2761 .Case("nocona", CK_Nocona) 2762 .Case("core2", CK_Core2) 2763 .Case("penryn", CK_Penryn) 2764 .Case("bonnell", CK_Bonnell) 2765 .Case("atom", CK_Bonnell) // Legacy name. 2766 .Case("silvermont", CK_Silvermont) 2767 .Case("slm", CK_Silvermont) // Legacy name. 2768 .Case("nehalem", CK_Nehalem) 2769 .Case("corei7", CK_Nehalem) // Legacy name. 2770 .Case("westmere", CK_Westmere) 2771 .Case("sandybridge", CK_SandyBridge) 2772 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2773 .Case("ivybridge", CK_IvyBridge) 2774 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2775 .Case("haswell", CK_Haswell) 2776 .Case("core-avx2", CK_Haswell) // Legacy name. 2777 .Case("broadwell", CK_Broadwell) 2778 .Case("skylake", CK_SkylakeClient) 2779 .Case("skylake-avx512", CK_SkylakeServer) 2780 .Case("skx", CK_SkylakeServer) // Legacy name. 2781 .Case("cannonlake", CK_Cannonlake) 2782 .Case("knl", CK_KNL) 2783 .Case("lakemont", CK_Lakemont) 2784 .Case("k6", CK_K6) 2785 .Case("k6-2", CK_K6_2) 2786 .Case("k6-3", CK_K6_3) 2787 .Case("athlon", CK_Athlon) 2788 .Case("athlon-tbird", CK_AthlonThunderbird) 2789 .Case("athlon-4", CK_Athlon4) 2790 .Case("athlon-xp", CK_AthlonXP) 2791 .Case("athlon-mp", CK_AthlonMP) 2792 .Case("athlon64", CK_Athlon64) 2793 .Case("athlon64-sse3", CK_Athlon64SSE3) 2794 .Case("athlon-fx", CK_AthlonFX) 2795 .Case("k8", CK_K8) 2796 .Case("k8-sse3", CK_K8SSE3) 2797 .Case("opteron", CK_Opteron) 2798 .Case("opteron-sse3", CK_OpteronSSE3) 2799 .Case("barcelona", CK_AMDFAM10) 2800 .Case("amdfam10", CK_AMDFAM10) 2801 .Case("btver1", CK_BTVER1) 2802 .Case("btver2", CK_BTVER2) 2803 .Case("bdver1", CK_BDVER1) 2804 .Case("bdver2", CK_BDVER2) 2805 .Case("bdver3", CK_BDVER3) 2806 .Case("bdver4", CK_BDVER4) 2807 .Case("znver1", CK_ZNVER1) 2808 .Case("x86-64", CK_x86_64) 2809 .Case("geode", CK_Geode) 2810 .Default(CK_Generic); 2811 } 2812 2813 enum FPMathKind { 2814 FP_Default, 2815 FP_SSE, 2816 FP_387 2817 } FPMath = FP_Default; 2818 2819 public: 2820 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2821 : TargetInfo(Triple) { 2822 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2823 } 2824 unsigned getFloatEvalMethod() const override { 2825 // X87 evaluates with 80 bits "long double" precision. 2826 return SSELevel == NoSSE ? 2 : 0; 2827 } 2828 ArrayRef<const char *> getGCCRegNames() const override { 2829 return llvm::makeArrayRef(GCCRegNames); 2830 } 2831 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2832 return None; 2833 } 2834 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2835 return llvm::makeArrayRef(AddlRegNames); 2836 } 2837 bool validateCpuSupports(StringRef Name) const override; 2838 bool validateAsmConstraint(const char *&Name, 2839 TargetInfo::ConstraintInfo &info) const override; 2840 2841 bool validateGlobalRegisterVariable(StringRef RegName, 2842 unsigned RegSize, 2843 bool &HasSizeMismatch) const override { 2844 // esp and ebp are the only 32-bit registers the x86 backend can currently 2845 // handle. 2846 if (RegName.equals("esp") || RegName.equals("ebp")) { 2847 // Check that the register size is 32-bit. 2848 HasSizeMismatch = RegSize != 32; 2849 return true; 2850 } 2851 2852 return false; 2853 } 2854 2855 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2856 2857 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2858 2859 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2860 2861 std::string convertConstraint(const char *&Constraint) const override; 2862 const char *getClobbers() const override { 2863 return "~{dirflag},~{fpsr},~{flags}"; 2864 } 2865 2866 StringRef getConstraintRegister(const StringRef &Constraint, 2867 const StringRef &Expression) const override { 2868 StringRef::iterator I, E; 2869 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2870 if (isalpha(*I)) 2871 break; 2872 } 2873 if (I == E) 2874 return ""; 2875 switch (*I) { 2876 // For the register constraints, return the matching register name 2877 case 'a': 2878 return "ax"; 2879 case 'b': 2880 return "bx"; 2881 case 'c': 2882 return "cx"; 2883 case 'd': 2884 return "dx"; 2885 case 'S': 2886 return "si"; 2887 case 'D': 2888 return "di"; 2889 // In case the constraint is 'r' we need to return Expression 2890 case 'r': 2891 return Expression; 2892 default: 2893 // Default value if there is no constraint for the register 2894 return ""; 2895 } 2896 return ""; 2897 } 2898 2899 void getTargetDefines(const LangOptions &Opts, 2900 MacroBuilder &Builder) const override; 2901 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2902 bool Enabled); 2903 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2904 bool Enabled); 2905 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2906 bool Enabled); 2907 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2908 StringRef Name, bool Enabled) const override { 2909 setFeatureEnabledImpl(Features, Name, Enabled); 2910 } 2911 // This exists purely to cut down on the number of virtual calls in 2912 // initFeatureMap which calls this repeatedly. 2913 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2914 StringRef Name, bool Enabled); 2915 bool 2916 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2917 StringRef CPU, 2918 const std::vector<std::string> &FeaturesVec) const override; 2919 bool hasFeature(StringRef Feature) const override; 2920 bool handleTargetFeatures(std::vector<std::string> &Features, 2921 DiagnosticsEngine &Diags) override; 2922 StringRef getABI() const override { 2923 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2924 return "avx512"; 2925 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2926 return "avx"; 2927 if (getTriple().getArch() == llvm::Triple::x86 && 2928 MMX3DNowLevel == NoMMX3DNow) 2929 return "no-mmx"; 2930 return ""; 2931 } 2932 bool setCPU(const std::string &Name) override { 2933 CPU = getCPUKind(Name); 2934 2935 // Perform any per-CPU checks necessary to determine if this CPU is 2936 // acceptable. 2937 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2938 // invalid without explaining *why*. 2939 switch (CPU) { 2940 case CK_Generic: 2941 // No processor selected! 2942 return false; 2943 2944 case CK_i386: 2945 case CK_i486: 2946 case CK_WinChipC6: 2947 case CK_WinChip2: 2948 case CK_C3: 2949 case CK_i586: 2950 case CK_Pentium: 2951 case CK_PentiumMMX: 2952 case CK_i686: 2953 case CK_PentiumPro: 2954 case CK_Pentium2: 2955 case CK_Pentium3: 2956 case CK_Pentium3M: 2957 case CK_PentiumM: 2958 case CK_Yonah: 2959 case CK_C3_2: 2960 case CK_Pentium4: 2961 case CK_Pentium4M: 2962 case CK_Lakemont: 2963 case CK_Prescott: 2964 case CK_K6: 2965 case CK_K6_2: 2966 case CK_K6_3: 2967 case CK_Athlon: 2968 case CK_AthlonThunderbird: 2969 case CK_Athlon4: 2970 case CK_AthlonXP: 2971 case CK_AthlonMP: 2972 case CK_Geode: 2973 // Only accept certain architectures when compiling in 32-bit mode. 2974 if (getTriple().getArch() != llvm::Triple::x86) 2975 return false; 2976 2977 // Fallthrough 2978 case CK_Nocona: 2979 case CK_Core2: 2980 case CK_Penryn: 2981 case CK_Bonnell: 2982 case CK_Silvermont: 2983 case CK_Nehalem: 2984 case CK_Westmere: 2985 case CK_SandyBridge: 2986 case CK_IvyBridge: 2987 case CK_Haswell: 2988 case CK_Broadwell: 2989 case CK_SkylakeClient: 2990 case CK_SkylakeServer: 2991 case CK_Cannonlake: 2992 case CK_KNL: 2993 case CK_Athlon64: 2994 case CK_Athlon64SSE3: 2995 case CK_AthlonFX: 2996 case CK_K8: 2997 case CK_K8SSE3: 2998 case CK_Opteron: 2999 case CK_OpteronSSE3: 3000 case CK_AMDFAM10: 3001 case CK_BTVER1: 3002 case CK_BTVER2: 3003 case CK_BDVER1: 3004 case CK_BDVER2: 3005 case CK_BDVER3: 3006 case CK_BDVER4: 3007 case CK_ZNVER1: 3008 case CK_x86_64: 3009 return true; 3010 } 3011 llvm_unreachable("Unhandled CPU kind"); 3012 } 3013 3014 bool setFPMath(StringRef Name) override; 3015 3016 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3017 // Most of the non-ARM calling conventions are i386 conventions. 3018 switch (CC) { 3019 case CC_X86ThisCall: 3020 case CC_X86FastCall: 3021 case CC_X86StdCall: 3022 case CC_X86VectorCall: 3023 case CC_X86RegCall: 3024 case CC_C: 3025 case CC_Swift: 3026 case CC_X86Pascal: 3027 case CC_IntelOclBicc: 3028 return CCCR_OK; 3029 default: 3030 return CCCR_Warning; 3031 } 3032 } 3033 3034 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3035 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3036 } 3037 3038 bool hasSjLjLowering() const override { 3039 return true; 3040 } 3041 3042 void setSupportedOpenCLOpts() override { 3043 getSupportedOpenCLOpts().supportAll(); 3044 } 3045 }; 3046 3047 bool X86TargetInfo::setFPMath(StringRef Name) { 3048 if (Name == "387") { 3049 FPMath = FP_387; 3050 return true; 3051 } 3052 if (Name == "sse") { 3053 FPMath = FP_SSE; 3054 return true; 3055 } 3056 return false; 3057 } 3058 3059 bool X86TargetInfo::initFeatureMap( 3060 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3061 const std::vector<std::string> &FeaturesVec) const { 3062 // FIXME: This *really* should not be here. 3063 // X86_64 always has SSE2. 3064 if (getTriple().getArch() == llvm::Triple::x86_64) 3065 setFeatureEnabledImpl(Features, "sse2", true); 3066 3067 const CPUKind Kind = getCPUKind(CPU); 3068 3069 // Enable X87 for all X86 processors but Lakemont. 3070 if (Kind != CK_Lakemont) 3071 setFeatureEnabledImpl(Features, "x87", true); 3072 3073 switch (Kind) { 3074 case CK_Generic: 3075 case CK_i386: 3076 case CK_i486: 3077 case CK_i586: 3078 case CK_Pentium: 3079 case CK_i686: 3080 case CK_PentiumPro: 3081 case CK_Lakemont: 3082 break; 3083 case CK_PentiumMMX: 3084 case CK_Pentium2: 3085 case CK_K6: 3086 case CK_WinChipC6: 3087 setFeatureEnabledImpl(Features, "mmx", true); 3088 break; 3089 case CK_Pentium3: 3090 case CK_Pentium3M: 3091 case CK_C3_2: 3092 setFeatureEnabledImpl(Features, "sse", true); 3093 setFeatureEnabledImpl(Features, "fxsr", true); 3094 break; 3095 case CK_PentiumM: 3096 case CK_Pentium4: 3097 case CK_Pentium4M: 3098 case CK_x86_64: 3099 setFeatureEnabledImpl(Features, "sse2", true); 3100 setFeatureEnabledImpl(Features, "fxsr", true); 3101 break; 3102 case CK_Yonah: 3103 case CK_Prescott: 3104 case CK_Nocona: 3105 setFeatureEnabledImpl(Features, "sse3", true); 3106 setFeatureEnabledImpl(Features, "fxsr", true); 3107 setFeatureEnabledImpl(Features, "cx16", true); 3108 break; 3109 case CK_Core2: 3110 case CK_Bonnell: 3111 setFeatureEnabledImpl(Features, "ssse3", true); 3112 setFeatureEnabledImpl(Features, "fxsr", true); 3113 setFeatureEnabledImpl(Features, "cx16", true); 3114 break; 3115 case CK_Penryn: 3116 setFeatureEnabledImpl(Features, "sse4.1", true); 3117 setFeatureEnabledImpl(Features, "fxsr", true); 3118 setFeatureEnabledImpl(Features, "cx16", true); 3119 break; 3120 case CK_Cannonlake: 3121 setFeatureEnabledImpl(Features, "avx512ifma", true); 3122 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3123 setFeatureEnabledImpl(Features, "sha", true); 3124 LLVM_FALLTHROUGH; 3125 case CK_SkylakeServer: 3126 setFeatureEnabledImpl(Features, "avx512f", true); 3127 setFeatureEnabledImpl(Features, "avx512cd", true); 3128 setFeatureEnabledImpl(Features, "avx512dq", true); 3129 setFeatureEnabledImpl(Features, "avx512bw", true); 3130 setFeatureEnabledImpl(Features, "avx512vl", true); 3131 setFeatureEnabledImpl(Features, "pku", true); 3132 setFeatureEnabledImpl(Features, "clwb", true); 3133 LLVM_FALLTHROUGH; 3134 case CK_SkylakeClient: 3135 setFeatureEnabledImpl(Features, "xsavec", true); 3136 setFeatureEnabledImpl(Features, "xsaves", true); 3137 setFeatureEnabledImpl(Features, "mpx", true); 3138 setFeatureEnabledImpl(Features, "sgx", true); 3139 setFeatureEnabledImpl(Features, "clflushopt", true); 3140 LLVM_FALLTHROUGH; 3141 case CK_Broadwell: 3142 setFeatureEnabledImpl(Features, "rdseed", true); 3143 setFeatureEnabledImpl(Features, "adx", true); 3144 LLVM_FALLTHROUGH; 3145 case CK_Haswell: 3146 setFeatureEnabledImpl(Features, "avx2", true); 3147 setFeatureEnabledImpl(Features, "lzcnt", true); 3148 setFeatureEnabledImpl(Features, "bmi", true); 3149 setFeatureEnabledImpl(Features, "bmi2", true); 3150 setFeatureEnabledImpl(Features, "rtm", true); 3151 setFeatureEnabledImpl(Features, "fma", true); 3152 setFeatureEnabledImpl(Features, "movbe", true); 3153 LLVM_FALLTHROUGH; 3154 case CK_IvyBridge: 3155 setFeatureEnabledImpl(Features, "rdrnd", true); 3156 setFeatureEnabledImpl(Features, "f16c", true); 3157 setFeatureEnabledImpl(Features, "fsgsbase", true); 3158 LLVM_FALLTHROUGH; 3159 case CK_SandyBridge: 3160 setFeatureEnabledImpl(Features, "avx", true); 3161 setFeatureEnabledImpl(Features, "xsave", true); 3162 setFeatureEnabledImpl(Features, "xsaveopt", true); 3163 LLVM_FALLTHROUGH; 3164 case CK_Westmere: 3165 case CK_Silvermont: 3166 setFeatureEnabledImpl(Features, "aes", true); 3167 setFeatureEnabledImpl(Features, "pclmul", true); 3168 LLVM_FALLTHROUGH; 3169 case CK_Nehalem: 3170 setFeatureEnabledImpl(Features, "sse4.2", true); 3171 setFeatureEnabledImpl(Features, "fxsr", true); 3172 setFeatureEnabledImpl(Features, "cx16", true); 3173 break; 3174 case CK_KNL: 3175 setFeatureEnabledImpl(Features, "avx512f", true); 3176 setFeatureEnabledImpl(Features, "avx512cd", true); 3177 setFeatureEnabledImpl(Features, "avx512er", true); 3178 setFeatureEnabledImpl(Features, "avx512pf", true); 3179 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3180 setFeatureEnabledImpl(Features, "fxsr", true); 3181 setFeatureEnabledImpl(Features, "rdseed", true); 3182 setFeatureEnabledImpl(Features, "adx", true); 3183 setFeatureEnabledImpl(Features, "lzcnt", true); 3184 setFeatureEnabledImpl(Features, "bmi", true); 3185 setFeatureEnabledImpl(Features, "bmi2", true); 3186 setFeatureEnabledImpl(Features, "rtm", true); 3187 setFeatureEnabledImpl(Features, "fma", true); 3188 setFeatureEnabledImpl(Features, "rdrnd", true); 3189 setFeatureEnabledImpl(Features, "f16c", true); 3190 setFeatureEnabledImpl(Features, "fsgsbase", true); 3191 setFeatureEnabledImpl(Features, "aes", true); 3192 setFeatureEnabledImpl(Features, "pclmul", true); 3193 setFeatureEnabledImpl(Features, "cx16", true); 3194 setFeatureEnabledImpl(Features, "xsaveopt", true); 3195 setFeatureEnabledImpl(Features, "xsave", true); 3196 setFeatureEnabledImpl(Features, "movbe", true); 3197 break; 3198 case CK_K6_2: 3199 case CK_K6_3: 3200 case CK_WinChip2: 3201 case CK_C3: 3202 setFeatureEnabledImpl(Features, "3dnow", true); 3203 break; 3204 case CK_Athlon: 3205 case CK_AthlonThunderbird: 3206 case CK_Geode: 3207 setFeatureEnabledImpl(Features, "3dnowa", true); 3208 break; 3209 case CK_Athlon4: 3210 case CK_AthlonXP: 3211 case CK_AthlonMP: 3212 setFeatureEnabledImpl(Features, "sse", true); 3213 setFeatureEnabledImpl(Features, "3dnowa", true); 3214 setFeatureEnabledImpl(Features, "fxsr", true); 3215 break; 3216 case CK_K8: 3217 case CK_Opteron: 3218 case CK_Athlon64: 3219 case CK_AthlonFX: 3220 setFeatureEnabledImpl(Features, "sse2", true); 3221 setFeatureEnabledImpl(Features, "3dnowa", true); 3222 setFeatureEnabledImpl(Features, "fxsr", true); 3223 break; 3224 case CK_AMDFAM10: 3225 setFeatureEnabledImpl(Features, "sse4a", true); 3226 setFeatureEnabledImpl(Features, "lzcnt", true); 3227 setFeatureEnabledImpl(Features, "popcnt", true); 3228 LLVM_FALLTHROUGH; 3229 case CK_K8SSE3: 3230 case CK_OpteronSSE3: 3231 case CK_Athlon64SSE3: 3232 setFeatureEnabledImpl(Features, "sse3", true); 3233 setFeatureEnabledImpl(Features, "3dnowa", true); 3234 setFeatureEnabledImpl(Features, "fxsr", true); 3235 break; 3236 case CK_BTVER2: 3237 setFeatureEnabledImpl(Features, "avx", true); 3238 setFeatureEnabledImpl(Features, "aes", true); 3239 setFeatureEnabledImpl(Features, "pclmul", true); 3240 setFeatureEnabledImpl(Features, "bmi", true); 3241 setFeatureEnabledImpl(Features, "f16c", true); 3242 setFeatureEnabledImpl(Features, "xsaveopt", true); 3243 LLVM_FALLTHROUGH; 3244 case CK_BTVER1: 3245 setFeatureEnabledImpl(Features, "ssse3", true); 3246 setFeatureEnabledImpl(Features, "sse4a", true); 3247 setFeatureEnabledImpl(Features, "lzcnt", true); 3248 setFeatureEnabledImpl(Features, "popcnt", true); 3249 setFeatureEnabledImpl(Features, "prfchw", true); 3250 setFeatureEnabledImpl(Features, "cx16", true); 3251 setFeatureEnabledImpl(Features, "fxsr", true); 3252 break; 3253 case CK_ZNVER1: 3254 setFeatureEnabledImpl(Features, "adx", true); 3255 setFeatureEnabledImpl(Features, "aes", true); 3256 setFeatureEnabledImpl(Features, "avx2", true); 3257 setFeatureEnabledImpl(Features, "bmi", true); 3258 setFeatureEnabledImpl(Features, "bmi2", true); 3259 setFeatureEnabledImpl(Features, "clflushopt", true); 3260 setFeatureEnabledImpl(Features, "clzero", true); 3261 setFeatureEnabledImpl(Features, "cx16", true); 3262 setFeatureEnabledImpl(Features, "f16c", true); 3263 setFeatureEnabledImpl(Features, "fma", true); 3264 setFeatureEnabledImpl(Features, "fsgsbase", true); 3265 setFeatureEnabledImpl(Features, "fxsr", true); 3266 setFeatureEnabledImpl(Features, "lzcnt", true); 3267 setFeatureEnabledImpl(Features, "mwaitx", true); 3268 setFeatureEnabledImpl(Features, "movbe", true); 3269 setFeatureEnabledImpl(Features, "pclmul", true); 3270 setFeatureEnabledImpl(Features, "popcnt", true); 3271 setFeatureEnabledImpl(Features, "prfchw", true); 3272 setFeatureEnabledImpl(Features, "rdrnd", true); 3273 setFeatureEnabledImpl(Features, "rdseed", true); 3274 setFeatureEnabledImpl(Features, "sha", true); 3275 setFeatureEnabledImpl(Features, "sse4a", true); 3276 setFeatureEnabledImpl(Features, "xsave", true); 3277 setFeatureEnabledImpl(Features, "xsavec", true); 3278 setFeatureEnabledImpl(Features, "xsaveopt", true); 3279 setFeatureEnabledImpl(Features, "xsaves", true); 3280 break; 3281 case CK_BDVER4: 3282 setFeatureEnabledImpl(Features, "avx2", true); 3283 setFeatureEnabledImpl(Features, "bmi2", true); 3284 setFeatureEnabledImpl(Features, "mwaitx", true); 3285 LLVM_FALLTHROUGH; 3286 case CK_BDVER3: 3287 setFeatureEnabledImpl(Features, "fsgsbase", true); 3288 setFeatureEnabledImpl(Features, "xsaveopt", true); 3289 LLVM_FALLTHROUGH; 3290 case CK_BDVER2: 3291 setFeatureEnabledImpl(Features, "bmi", true); 3292 setFeatureEnabledImpl(Features, "fma", true); 3293 setFeatureEnabledImpl(Features, "f16c", true); 3294 setFeatureEnabledImpl(Features, "tbm", true); 3295 LLVM_FALLTHROUGH; 3296 case CK_BDVER1: 3297 // xop implies avx, sse4a and fma4. 3298 setFeatureEnabledImpl(Features, "xop", true); 3299 setFeatureEnabledImpl(Features, "lzcnt", true); 3300 setFeatureEnabledImpl(Features, "aes", true); 3301 setFeatureEnabledImpl(Features, "pclmul", true); 3302 setFeatureEnabledImpl(Features, "prfchw", true); 3303 setFeatureEnabledImpl(Features, "cx16", true); 3304 setFeatureEnabledImpl(Features, "fxsr", true); 3305 setFeatureEnabledImpl(Features, "xsave", true); 3306 break; 3307 } 3308 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3309 return false; 3310 3311 // Can't do this earlier because we need to be able to explicitly enable 3312 // or disable these features and the things that they depend upon. 3313 3314 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3315 auto I = Features.find("sse4.2"); 3316 if (I != Features.end() && I->getValue() && 3317 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3318 FeaturesVec.end()) 3319 Features["popcnt"] = true; 3320 3321 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3322 I = Features.find("3dnow"); 3323 if (I != Features.end() && I->getValue() && 3324 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3325 FeaturesVec.end()) 3326 Features["prfchw"] = true; 3327 3328 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3329 // then enable MMX. 3330 I = Features.find("sse"); 3331 if (I != Features.end() && I->getValue() && 3332 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3333 FeaturesVec.end()) 3334 Features["mmx"] = true; 3335 3336 return true; 3337 } 3338 3339 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3340 X86SSEEnum Level, bool Enabled) { 3341 if (Enabled) { 3342 switch (Level) { 3343 case AVX512F: 3344 Features["avx512f"] = true; 3345 case AVX2: 3346 Features["avx2"] = true; 3347 case AVX: 3348 Features["avx"] = true; 3349 Features["xsave"] = true; 3350 case SSE42: 3351 Features["sse4.2"] = true; 3352 case SSE41: 3353 Features["sse4.1"] = true; 3354 case SSSE3: 3355 Features["ssse3"] = true; 3356 case SSE3: 3357 Features["sse3"] = true; 3358 case SSE2: 3359 Features["sse2"] = true; 3360 case SSE1: 3361 Features["sse"] = true; 3362 case NoSSE: 3363 break; 3364 } 3365 return; 3366 } 3367 3368 switch (Level) { 3369 case NoSSE: 3370 case SSE1: 3371 Features["sse"] = false; 3372 case SSE2: 3373 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3374 Features["sha"] = false; 3375 case SSE3: 3376 Features["sse3"] = false; 3377 setXOPLevel(Features, NoXOP, false); 3378 case SSSE3: 3379 Features["ssse3"] = false; 3380 case SSE41: 3381 Features["sse4.1"] = false; 3382 case SSE42: 3383 Features["sse4.2"] = false; 3384 case AVX: 3385 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3386 Features["xsaveopt"] = false; 3387 setXOPLevel(Features, FMA4, false); 3388 case AVX2: 3389 Features["avx2"] = false; 3390 case AVX512F: 3391 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3392 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3393 Features["avx512vl"] = Features["avx512vbmi"] = 3394 Features["avx512ifma"] = false; 3395 } 3396 } 3397 3398 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3399 MMX3DNowEnum Level, bool Enabled) { 3400 if (Enabled) { 3401 switch (Level) { 3402 case AMD3DNowAthlon: 3403 Features["3dnowa"] = true; 3404 case AMD3DNow: 3405 Features["3dnow"] = true; 3406 case MMX: 3407 Features["mmx"] = true; 3408 case NoMMX3DNow: 3409 break; 3410 } 3411 return; 3412 } 3413 3414 switch (Level) { 3415 case NoMMX3DNow: 3416 case MMX: 3417 Features["mmx"] = false; 3418 case AMD3DNow: 3419 Features["3dnow"] = false; 3420 case AMD3DNowAthlon: 3421 Features["3dnowa"] = false; 3422 } 3423 } 3424 3425 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3426 bool Enabled) { 3427 if (Enabled) { 3428 switch (Level) { 3429 case XOP: 3430 Features["xop"] = true; 3431 case FMA4: 3432 Features["fma4"] = true; 3433 setSSELevel(Features, AVX, true); 3434 case SSE4A: 3435 Features["sse4a"] = true; 3436 setSSELevel(Features, SSE3, true); 3437 case NoXOP: 3438 break; 3439 } 3440 return; 3441 } 3442 3443 switch (Level) { 3444 case NoXOP: 3445 case SSE4A: 3446 Features["sse4a"] = false; 3447 case FMA4: 3448 Features["fma4"] = false; 3449 case XOP: 3450 Features["xop"] = false; 3451 } 3452 } 3453 3454 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3455 StringRef Name, bool Enabled) { 3456 // This is a bit of a hack to deal with the sse4 target feature when used 3457 // as part of the target attribute. We handle sse4 correctly everywhere 3458 // else. See below for more information on how we handle the sse4 options. 3459 if (Name != "sse4") 3460 Features[Name] = Enabled; 3461 3462 if (Name == "mmx") { 3463 setMMXLevel(Features, MMX, Enabled); 3464 } else if (Name == "sse") { 3465 setSSELevel(Features, SSE1, Enabled); 3466 } else if (Name == "sse2") { 3467 setSSELevel(Features, SSE2, Enabled); 3468 } else if (Name == "sse3") { 3469 setSSELevel(Features, SSE3, Enabled); 3470 } else if (Name == "ssse3") { 3471 setSSELevel(Features, SSSE3, Enabled); 3472 } else if (Name == "sse4.2") { 3473 setSSELevel(Features, SSE42, Enabled); 3474 } else if (Name == "sse4.1") { 3475 setSSELevel(Features, SSE41, Enabled); 3476 } else if (Name == "3dnow") { 3477 setMMXLevel(Features, AMD3DNow, Enabled); 3478 } else if (Name == "3dnowa") { 3479 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3480 } else if (Name == "aes") { 3481 if (Enabled) 3482 setSSELevel(Features, SSE2, Enabled); 3483 } else if (Name == "pclmul") { 3484 if (Enabled) 3485 setSSELevel(Features, SSE2, Enabled); 3486 } else if (Name == "avx") { 3487 setSSELevel(Features, AVX, Enabled); 3488 } else if (Name == "avx2") { 3489 setSSELevel(Features, AVX2, Enabled); 3490 } else if (Name == "avx512f") { 3491 setSSELevel(Features, AVX512F, Enabled); 3492 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3493 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3494 Name == "avx512vbmi" || Name == "avx512ifma") { 3495 if (Enabled) 3496 setSSELevel(Features, AVX512F, Enabled); 3497 // Enable BWI instruction if VBMI is being enabled. 3498 if (Name == "avx512vbmi" && Enabled) 3499 Features["avx512bw"] = true; 3500 // Also disable VBMI if BWI is being disabled. 3501 if (Name == "avx512bw" && !Enabled) 3502 Features["avx512vbmi"] = false; 3503 } else if (Name == "fma") { 3504 if (Enabled) 3505 setSSELevel(Features, AVX, Enabled); 3506 } else if (Name == "fma4") { 3507 setXOPLevel(Features, FMA4, Enabled); 3508 } else if (Name == "xop") { 3509 setXOPLevel(Features, XOP, Enabled); 3510 } else if (Name == "sse4a") { 3511 setXOPLevel(Features, SSE4A, Enabled); 3512 } else if (Name == "f16c") { 3513 if (Enabled) 3514 setSSELevel(Features, AVX, Enabled); 3515 } else if (Name == "sha") { 3516 if (Enabled) 3517 setSSELevel(Features, SSE2, Enabled); 3518 } else if (Name == "sse4") { 3519 // We can get here via the __target__ attribute since that's not controlled 3520 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3521 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3522 // disabled. 3523 if (Enabled) 3524 setSSELevel(Features, SSE42, Enabled); 3525 else 3526 setSSELevel(Features, SSE41, Enabled); 3527 } else if (Name == "xsave") { 3528 if (!Enabled) 3529 Features["xsaveopt"] = false; 3530 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3531 if (Enabled) 3532 Features["xsave"] = true; 3533 } 3534 } 3535 3536 /// handleTargetFeatures - Perform initialization based on the user 3537 /// configured set of features. 3538 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3539 DiagnosticsEngine &Diags) { 3540 for (const auto &Feature : Features) { 3541 if (Feature[0] != '+') 3542 continue; 3543 3544 if (Feature == "+aes") { 3545 HasAES = true; 3546 } else if (Feature == "+pclmul") { 3547 HasPCLMUL = true; 3548 } else if (Feature == "+lzcnt") { 3549 HasLZCNT = true; 3550 } else if (Feature == "+rdrnd") { 3551 HasRDRND = true; 3552 } else if (Feature == "+fsgsbase") { 3553 HasFSGSBASE = true; 3554 } else if (Feature == "+bmi") { 3555 HasBMI = true; 3556 } else if (Feature == "+bmi2") { 3557 HasBMI2 = true; 3558 } else if (Feature == "+popcnt") { 3559 HasPOPCNT = true; 3560 } else if (Feature == "+rtm") { 3561 HasRTM = true; 3562 } else if (Feature == "+prfchw") { 3563 HasPRFCHW = true; 3564 } else if (Feature == "+rdseed") { 3565 HasRDSEED = true; 3566 } else if (Feature == "+adx") { 3567 HasADX = true; 3568 } else if (Feature == "+tbm") { 3569 HasTBM = true; 3570 } else if (Feature == "+fma") { 3571 HasFMA = true; 3572 } else if (Feature == "+f16c") { 3573 HasF16C = true; 3574 } else if (Feature == "+avx512cd") { 3575 HasAVX512CD = true; 3576 } else if (Feature == "+avx512er") { 3577 HasAVX512ER = true; 3578 } else if (Feature == "+avx512pf") { 3579 HasAVX512PF = true; 3580 } else if (Feature == "+avx512dq") { 3581 HasAVX512DQ = true; 3582 } else if (Feature == "+avx512bw") { 3583 HasAVX512BW = true; 3584 } else if (Feature == "+avx512vl") { 3585 HasAVX512VL = true; 3586 } else if (Feature == "+avx512vbmi") { 3587 HasAVX512VBMI = true; 3588 } else if (Feature == "+avx512ifma") { 3589 HasAVX512IFMA = true; 3590 } else if (Feature == "+sha") { 3591 HasSHA = true; 3592 } else if (Feature == "+mpx") { 3593 HasMPX = true; 3594 } else if (Feature == "+movbe") { 3595 HasMOVBE = true; 3596 } else if (Feature == "+sgx") { 3597 HasSGX = true; 3598 } else if (Feature == "+cx16") { 3599 HasCX16 = true; 3600 } else if (Feature == "+fxsr") { 3601 HasFXSR = true; 3602 } else if (Feature == "+xsave") { 3603 HasXSAVE = true; 3604 } else if (Feature == "+xsaveopt") { 3605 HasXSAVEOPT = true; 3606 } else if (Feature == "+xsavec") { 3607 HasXSAVEC = true; 3608 } else if (Feature == "+xsaves") { 3609 HasXSAVES = true; 3610 } else if (Feature == "+mwaitx") { 3611 HasMWAITX = true; 3612 } else if (Feature == "+pku") { 3613 HasPKU = true; 3614 } else if (Feature == "+clflushopt") { 3615 HasCLFLUSHOPT = true; 3616 } else if (Feature == "+clwb") { 3617 HasCLWB = true; 3618 } else if (Feature == "+prefetchwt1") { 3619 HasPREFETCHWT1 = true; 3620 } else if (Feature == "+clzero") { 3621 HasCLZERO = true; 3622 } 3623 3624 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3625 .Case("+avx512f", AVX512F) 3626 .Case("+avx2", AVX2) 3627 .Case("+avx", AVX) 3628 .Case("+sse4.2", SSE42) 3629 .Case("+sse4.1", SSE41) 3630 .Case("+ssse3", SSSE3) 3631 .Case("+sse3", SSE3) 3632 .Case("+sse2", SSE2) 3633 .Case("+sse", SSE1) 3634 .Default(NoSSE); 3635 SSELevel = std::max(SSELevel, Level); 3636 3637 MMX3DNowEnum ThreeDNowLevel = 3638 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3639 .Case("+3dnowa", AMD3DNowAthlon) 3640 .Case("+3dnow", AMD3DNow) 3641 .Case("+mmx", MMX) 3642 .Default(NoMMX3DNow); 3643 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3644 3645 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3646 .Case("+xop", XOP) 3647 .Case("+fma4", FMA4) 3648 .Case("+sse4a", SSE4A) 3649 .Default(NoXOP); 3650 XOPLevel = std::max(XOPLevel, XLevel); 3651 } 3652 3653 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3654 // matches the selected sse level. 3655 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3656 (FPMath == FP_387 && SSELevel >= SSE1)) { 3657 Diags.Report(diag::err_target_unsupported_fpmath) << 3658 (FPMath == FP_SSE ? "sse" : "387"); 3659 return false; 3660 } 3661 3662 SimdDefaultAlign = 3663 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3664 return true; 3665 } 3666 3667 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3668 /// definitions for this particular subtarget. 3669 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3670 MacroBuilder &Builder) const { 3671 // Target identification. 3672 if (getTriple().getArch() == llvm::Triple::x86_64) { 3673 Builder.defineMacro("__amd64__"); 3674 Builder.defineMacro("__amd64"); 3675 Builder.defineMacro("__x86_64"); 3676 Builder.defineMacro("__x86_64__"); 3677 if (getTriple().getArchName() == "x86_64h") { 3678 Builder.defineMacro("__x86_64h"); 3679 Builder.defineMacro("__x86_64h__"); 3680 } 3681 } else { 3682 DefineStd(Builder, "i386", Opts); 3683 } 3684 3685 // Subtarget options. 3686 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3687 // truly should be based on -mtune options. 3688 switch (CPU) { 3689 case CK_Generic: 3690 break; 3691 case CK_i386: 3692 // The rest are coming from the i386 define above. 3693 Builder.defineMacro("__tune_i386__"); 3694 break; 3695 case CK_i486: 3696 case CK_WinChipC6: 3697 case CK_WinChip2: 3698 case CK_C3: 3699 defineCPUMacros(Builder, "i486"); 3700 break; 3701 case CK_PentiumMMX: 3702 Builder.defineMacro("__pentium_mmx__"); 3703 Builder.defineMacro("__tune_pentium_mmx__"); 3704 // Fallthrough 3705 case CK_i586: 3706 case CK_Pentium: 3707 defineCPUMacros(Builder, "i586"); 3708 defineCPUMacros(Builder, "pentium"); 3709 break; 3710 case CK_Pentium3: 3711 case CK_Pentium3M: 3712 case CK_PentiumM: 3713 Builder.defineMacro("__tune_pentium3__"); 3714 // Fallthrough 3715 case CK_Pentium2: 3716 case CK_C3_2: 3717 Builder.defineMacro("__tune_pentium2__"); 3718 // Fallthrough 3719 case CK_PentiumPro: 3720 Builder.defineMacro("__tune_i686__"); 3721 Builder.defineMacro("__tune_pentiumpro__"); 3722 // Fallthrough 3723 case CK_i686: 3724 Builder.defineMacro("__i686"); 3725 Builder.defineMacro("__i686__"); 3726 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3727 Builder.defineMacro("__pentiumpro"); 3728 Builder.defineMacro("__pentiumpro__"); 3729 break; 3730 case CK_Pentium4: 3731 case CK_Pentium4M: 3732 defineCPUMacros(Builder, "pentium4"); 3733 break; 3734 case CK_Yonah: 3735 case CK_Prescott: 3736 case CK_Nocona: 3737 defineCPUMacros(Builder, "nocona"); 3738 break; 3739 case CK_Core2: 3740 case CK_Penryn: 3741 defineCPUMacros(Builder, "core2"); 3742 break; 3743 case CK_Bonnell: 3744 defineCPUMacros(Builder, "atom"); 3745 break; 3746 case CK_Silvermont: 3747 defineCPUMacros(Builder, "slm"); 3748 break; 3749 case CK_Nehalem: 3750 case CK_Westmere: 3751 case CK_SandyBridge: 3752 case CK_IvyBridge: 3753 case CK_Haswell: 3754 case CK_Broadwell: 3755 case CK_SkylakeClient: 3756 // FIXME: Historically, we defined this legacy name, it would be nice to 3757 // remove it at some point. We've never exposed fine-grained names for 3758 // recent primary x86 CPUs, and we should keep it that way. 3759 defineCPUMacros(Builder, "corei7"); 3760 break; 3761 case CK_SkylakeServer: 3762 defineCPUMacros(Builder, "skx"); 3763 break; 3764 case CK_Cannonlake: 3765 break; 3766 case CK_KNL: 3767 defineCPUMacros(Builder, "knl"); 3768 break; 3769 case CK_Lakemont: 3770 Builder.defineMacro("__tune_lakemont__"); 3771 break; 3772 case CK_K6_2: 3773 Builder.defineMacro("__k6_2__"); 3774 Builder.defineMacro("__tune_k6_2__"); 3775 // Fallthrough 3776 case CK_K6_3: 3777 if (CPU != CK_K6_2) { // In case of fallthrough 3778 // FIXME: GCC may be enabling these in cases where some other k6 3779 // architecture is specified but -m3dnow is explicitly provided. The 3780 // exact semantics need to be determined and emulated here. 3781 Builder.defineMacro("__k6_3__"); 3782 Builder.defineMacro("__tune_k6_3__"); 3783 } 3784 // Fallthrough 3785 case CK_K6: 3786 defineCPUMacros(Builder, "k6"); 3787 break; 3788 case CK_Athlon: 3789 case CK_AthlonThunderbird: 3790 case CK_Athlon4: 3791 case CK_AthlonXP: 3792 case CK_AthlonMP: 3793 defineCPUMacros(Builder, "athlon"); 3794 if (SSELevel != NoSSE) { 3795 Builder.defineMacro("__athlon_sse__"); 3796 Builder.defineMacro("__tune_athlon_sse__"); 3797 } 3798 break; 3799 case CK_K8: 3800 case CK_K8SSE3: 3801 case CK_x86_64: 3802 case CK_Opteron: 3803 case CK_OpteronSSE3: 3804 case CK_Athlon64: 3805 case CK_Athlon64SSE3: 3806 case CK_AthlonFX: 3807 defineCPUMacros(Builder, "k8"); 3808 break; 3809 case CK_AMDFAM10: 3810 defineCPUMacros(Builder, "amdfam10"); 3811 break; 3812 case CK_BTVER1: 3813 defineCPUMacros(Builder, "btver1"); 3814 break; 3815 case CK_BTVER2: 3816 defineCPUMacros(Builder, "btver2"); 3817 break; 3818 case CK_BDVER1: 3819 defineCPUMacros(Builder, "bdver1"); 3820 break; 3821 case CK_BDVER2: 3822 defineCPUMacros(Builder, "bdver2"); 3823 break; 3824 case CK_BDVER3: 3825 defineCPUMacros(Builder, "bdver3"); 3826 break; 3827 case CK_BDVER4: 3828 defineCPUMacros(Builder, "bdver4"); 3829 break; 3830 case CK_ZNVER1: 3831 defineCPUMacros(Builder, "znver1"); 3832 break; 3833 case CK_Geode: 3834 defineCPUMacros(Builder, "geode"); 3835 break; 3836 } 3837 3838 // Target properties. 3839 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3840 3841 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3842 // functions in glibc header files that use FP Stack inline asm which the 3843 // backend can't deal with (PR879). 3844 Builder.defineMacro("__NO_MATH_INLINES"); 3845 3846 if (HasAES) 3847 Builder.defineMacro("__AES__"); 3848 3849 if (HasPCLMUL) 3850 Builder.defineMacro("__PCLMUL__"); 3851 3852 if (HasLZCNT) 3853 Builder.defineMacro("__LZCNT__"); 3854 3855 if (HasRDRND) 3856 Builder.defineMacro("__RDRND__"); 3857 3858 if (HasFSGSBASE) 3859 Builder.defineMacro("__FSGSBASE__"); 3860 3861 if (HasBMI) 3862 Builder.defineMacro("__BMI__"); 3863 3864 if (HasBMI2) 3865 Builder.defineMacro("__BMI2__"); 3866 3867 if (HasPOPCNT) 3868 Builder.defineMacro("__POPCNT__"); 3869 3870 if (HasRTM) 3871 Builder.defineMacro("__RTM__"); 3872 3873 if (HasPRFCHW) 3874 Builder.defineMacro("__PRFCHW__"); 3875 3876 if (HasRDSEED) 3877 Builder.defineMacro("__RDSEED__"); 3878 3879 if (HasADX) 3880 Builder.defineMacro("__ADX__"); 3881 3882 if (HasTBM) 3883 Builder.defineMacro("__TBM__"); 3884 3885 if (HasMWAITX) 3886 Builder.defineMacro("__MWAITX__"); 3887 3888 switch (XOPLevel) { 3889 case XOP: 3890 Builder.defineMacro("__XOP__"); 3891 case FMA4: 3892 Builder.defineMacro("__FMA4__"); 3893 case SSE4A: 3894 Builder.defineMacro("__SSE4A__"); 3895 case NoXOP: 3896 break; 3897 } 3898 3899 if (HasFMA) 3900 Builder.defineMacro("__FMA__"); 3901 3902 if (HasF16C) 3903 Builder.defineMacro("__F16C__"); 3904 3905 if (HasAVX512CD) 3906 Builder.defineMacro("__AVX512CD__"); 3907 if (HasAVX512ER) 3908 Builder.defineMacro("__AVX512ER__"); 3909 if (HasAVX512PF) 3910 Builder.defineMacro("__AVX512PF__"); 3911 if (HasAVX512DQ) 3912 Builder.defineMacro("__AVX512DQ__"); 3913 if (HasAVX512BW) 3914 Builder.defineMacro("__AVX512BW__"); 3915 if (HasAVX512VL) 3916 Builder.defineMacro("__AVX512VL__"); 3917 if (HasAVX512VBMI) 3918 Builder.defineMacro("__AVX512VBMI__"); 3919 if (HasAVX512IFMA) 3920 Builder.defineMacro("__AVX512IFMA__"); 3921 3922 if (HasSHA) 3923 Builder.defineMacro("__SHA__"); 3924 3925 if (HasFXSR) 3926 Builder.defineMacro("__FXSR__"); 3927 if (HasXSAVE) 3928 Builder.defineMacro("__XSAVE__"); 3929 if (HasXSAVEOPT) 3930 Builder.defineMacro("__XSAVEOPT__"); 3931 if (HasXSAVEC) 3932 Builder.defineMacro("__XSAVEC__"); 3933 if (HasXSAVES) 3934 Builder.defineMacro("__XSAVES__"); 3935 if (HasPKU) 3936 Builder.defineMacro("__PKU__"); 3937 if (HasCX16) 3938 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3939 if (HasCLFLUSHOPT) 3940 Builder.defineMacro("__CLFLUSHOPT__"); 3941 if (HasCLWB) 3942 Builder.defineMacro("__CLWB__"); 3943 if (HasMPX) 3944 Builder.defineMacro("__MPX__"); 3945 if (HasSGX) 3946 Builder.defineMacro("__SGX__"); 3947 if (HasPREFETCHWT1) 3948 Builder.defineMacro("__PREFETCHWT1__"); 3949 if (HasCLZERO) 3950 Builder.defineMacro("__CLZERO__"); 3951 3952 // Each case falls through to the previous one here. 3953 switch (SSELevel) { 3954 case AVX512F: 3955 Builder.defineMacro("__AVX512F__"); 3956 case AVX2: 3957 Builder.defineMacro("__AVX2__"); 3958 case AVX: 3959 Builder.defineMacro("__AVX__"); 3960 case SSE42: 3961 Builder.defineMacro("__SSE4_2__"); 3962 case SSE41: 3963 Builder.defineMacro("__SSE4_1__"); 3964 case SSSE3: 3965 Builder.defineMacro("__SSSE3__"); 3966 case SSE3: 3967 Builder.defineMacro("__SSE3__"); 3968 case SSE2: 3969 Builder.defineMacro("__SSE2__"); 3970 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3971 case SSE1: 3972 Builder.defineMacro("__SSE__"); 3973 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3974 case NoSSE: 3975 break; 3976 } 3977 3978 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3979 switch (SSELevel) { 3980 case AVX512F: 3981 case AVX2: 3982 case AVX: 3983 case SSE42: 3984 case SSE41: 3985 case SSSE3: 3986 case SSE3: 3987 case SSE2: 3988 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3989 break; 3990 case SSE1: 3991 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3992 break; 3993 default: 3994 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3995 } 3996 } 3997 3998 // Each case falls through to the previous one here. 3999 switch (MMX3DNowLevel) { 4000 case AMD3DNowAthlon: 4001 Builder.defineMacro("__3dNOW_A__"); 4002 case AMD3DNow: 4003 Builder.defineMacro("__3dNOW__"); 4004 case MMX: 4005 Builder.defineMacro("__MMX__"); 4006 case NoMMX3DNow: 4007 break; 4008 } 4009 4010 if (CPU >= CK_i486) { 4011 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4012 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4013 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4014 } 4015 if (CPU >= CK_i586) 4016 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4017 } 4018 4019 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4020 return llvm::StringSwitch<bool>(Feature) 4021 .Case("aes", HasAES) 4022 .Case("avx", SSELevel >= AVX) 4023 .Case("avx2", SSELevel >= AVX2) 4024 .Case("avx512f", SSELevel >= AVX512F) 4025 .Case("avx512cd", HasAVX512CD) 4026 .Case("avx512er", HasAVX512ER) 4027 .Case("avx512pf", HasAVX512PF) 4028 .Case("avx512dq", HasAVX512DQ) 4029 .Case("avx512bw", HasAVX512BW) 4030 .Case("avx512vl", HasAVX512VL) 4031 .Case("avx512vbmi", HasAVX512VBMI) 4032 .Case("avx512ifma", HasAVX512IFMA) 4033 .Case("bmi", HasBMI) 4034 .Case("bmi2", HasBMI2) 4035 .Case("clflushopt", HasCLFLUSHOPT) 4036 .Case("clwb", HasCLWB) 4037 .Case("clzero", HasCLZERO) 4038 .Case("cx16", HasCX16) 4039 .Case("f16c", HasF16C) 4040 .Case("fma", HasFMA) 4041 .Case("fma4", XOPLevel >= FMA4) 4042 .Case("fsgsbase", HasFSGSBASE) 4043 .Case("fxsr", HasFXSR) 4044 .Case("lzcnt", HasLZCNT) 4045 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4046 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4047 .Case("mmx", MMX3DNowLevel >= MMX) 4048 .Case("movbe", HasMOVBE) 4049 .Case("mpx", HasMPX) 4050 .Case("pclmul", HasPCLMUL) 4051 .Case("pku", HasPKU) 4052 .Case("popcnt", HasPOPCNT) 4053 .Case("prefetchwt1", HasPREFETCHWT1) 4054 .Case("prfchw", HasPRFCHW) 4055 .Case("rdrnd", HasRDRND) 4056 .Case("rdseed", HasRDSEED) 4057 .Case("rtm", HasRTM) 4058 .Case("sgx", HasSGX) 4059 .Case("sha", HasSHA) 4060 .Case("sse", SSELevel >= SSE1) 4061 .Case("sse2", SSELevel >= SSE2) 4062 .Case("sse3", SSELevel >= SSE3) 4063 .Case("ssse3", SSELevel >= SSSE3) 4064 .Case("sse4.1", SSELevel >= SSE41) 4065 .Case("sse4.2", SSELevel >= SSE42) 4066 .Case("sse4a", XOPLevel >= SSE4A) 4067 .Case("tbm", HasTBM) 4068 .Case("x86", true) 4069 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4070 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4071 .Case("xop", XOPLevel >= XOP) 4072 .Case("xsave", HasXSAVE) 4073 .Case("xsavec", HasXSAVEC) 4074 .Case("xsaves", HasXSAVES) 4075 .Case("xsaveopt", HasXSAVEOPT) 4076 .Default(false); 4077 } 4078 4079 // We can't use a generic validation scheme for the features accepted here 4080 // versus subtarget features accepted in the target attribute because the 4081 // bitfield structure that's initialized in the runtime only supports the 4082 // below currently rather than the full range of subtarget features. (See 4083 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4084 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4085 return llvm::StringSwitch<bool>(FeatureStr) 4086 .Case("cmov", true) 4087 .Case("mmx", true) 4088 .Case("popcnt", true) 4089 .Case("sse", true) 4090 .Case("sse2", true) 4091 .Case("sse3", true) 4092 .Case("ssse3", true) 4093 .Case("sse4.1", true) 4094 .Case("sse4.2", true) 4095 .Case("avx", true) 4096 .Case("avx2", true) 4097 .Case("sse4a", true) 4098 .Case("fma4", true) 4099 .Case("xop", true) 4100 .Case("fma", true) 4101 .Case("avx512f", true) 4102 .Case("bmi", true) 4103 .Case("bmi2", true) 4104 .Case("aes", true) 4105 .Case("pclmul", true) 4106 .Case("avx512vl", true) 4107 .Case("avx512bw", true) 4108 .Case("avx512dq", true) 4109 .Case("avx512cd", true) 4110 .Case("avx512er", true) 4111 .Case("avx512pf", true) 4112 .Case("avx512vbmi", true) 4113 .Case("avx512ifma", true) 4114 .Default(false); 4115 } 4116 4117 bool 4118 X86TargetInfo::validateAsmConstraint(const char *&Name, 4119 TargetInfo::ConstraintInfo &Info) const { 4120 switch (*Name) { 4121 default: return false; 4122 // Constant constraints. 4123 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4124 // instructions. 4125 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4126 // x86_64 instructions. 4127 case 's': 4128 Info.setRequiresImmediate(); 4129 return true; 4130 case 'I': 4131 Info.setRequiresImmediate(0, 31); 4132 return true; 4133 case 'J': 4134 Info.setRequiresImmediate(0, 63); 4135 return true; 4136 case 'K': 4137 Info.setRequiresImmediate(-128, 127); 4138 return true; 4139 case 'L': 4140 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4141 return true; 4142 case 'M': 4143 Info.setRequiresImmediate(0, 3); 4144 return true; 4145 case 'N': 4146 Info.setRequiresImmediate(0, 255); 4147 return true; 4148 case 'O': 4149 Info.setRequiresImmediate(0, 127); 4150 return true; 4151 // Register constraints. 4152 case 'Y': // 'Y' is the first character for several 2-character constraints. 4153 // Shift the pointer to the second character of the constraint. 4154 Name++; 4155 switch (*Name) { 4156 default: 4157 return false; 4158 case '0': // First SSE register. 4159 case 't': // Any SSE register, when SSE2 is enabled. 4160 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4161 case 'm': // Any MMX register, when inter-unit moves enabled. 4162 case 'k': // AVX512 arch mask registers: k1-k7. 4163 Info.setAllowsRegister(); 4164 return true; 4165 } 4166 case 'f': // Any x87 floating point stack register. 4167 // Constraint 'f' cannot be used for output operands. 4168 if (Info.ConstraintStr[0] == '=') 4169 return false; 4170 Info.setAllowsRegister(); 4171 return true; 4172 case 'a': // eax. 4173 case 'b': // ebx. 4174 case 'c': // ecx. 4175 case 'd': // edx. 4176 case 'S': // esi. 4177 case 'D': // edi. 4178 case 'A': // edx:eax. 4179 case 't': // Top of floating point stack. 4180 case 'u': // Second from top of floating point stack. 4181 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4182 case 'y': // Any MMX register. 4183 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4184 case 'x': // Any SSE register. 4185 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4186 // for intermideate k reg operations). 4187 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4188 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4189 case 'l': // "Index" registers: any general register that can be used as an 4190 // index in a base+index memory access. 4191 Info.setAllowsRegister(); 4192 return true; 4193 // Floating point constant constraints. 4194 case 'C': // SSE floating point constant. 4195 case 'G': // x87 floating point constant. 4196 return true; 4197 } 4198 } 4199 4200 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4201 unsigned Size) const { 4202 // Strip off constraint modifiers. 4203 while (Constraint[0] == '=' || 4204 Constraint[0] == '+' || 4205 Constraint[0] == '&') 4206 Constraint = Constraint.substr(1); 4207 4208 return validateOperandSize(Constraint, Size); 4209 } 4210 4211 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4212 unsigned Size) const { 4213 return validateOperandSize(Constraint, Size); 4214 } 4215 4216 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4217 unsigned Size) const { 4218 switch (Constraint[0]) { 4219 default: break; 4220 case 'k': 4221 // Registers k0-k7 (AVX512) size limit is 64 bit. 4222 case 'y': 4223 return Size <= 64; 4224 case 'f': 4225 case 't': 4226 case 'u': 4227 return Size <= 128; 4228 case 'v': 4229 case 'x': 4230 if (SSELevel >= AVX512F) 4231 // 512-bit zmm registers can be used if target supports AVX512F. 4232 return Size <= 512U; 4233 else if (SSELevel >= AVX) 4234 // 256-bit ymm registers can be used if target supports AVX. 4235 return Size <= 256U; 4236 return Size <= 128U; 4237 case 'Y': 4238 // 'Y' is the first character for several 2-character constraints. 4239 switch (Constraint[1]) { 4240 default: break; 4241 case 'm': 4242 // 'Ym' is synonymous with 'y'. 4243 case 'k': 4244 return Size <= 64; 4245 case 'i': 4246 case 't': 4247 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4248 if (SSELevel >= AVX512F) 4249 return Size <= 512U; 4250 else if (SSELevel >= AVX) 4251 return Size <= 256U; 4252 return SSELevel >= SSE2 && Size <= 128U; 4253 } 4254 4255 } 4256 4257 return true; 4258 } 4259 4260 std::string 4261 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4262 switch (*Constraint) { 4263 case 'a': return std::string("{ax}"); 4264 case 'b': return std::string("{bx}"); 4265 case 'c': return std::string("{cx}"); 4266 case 'd': return std::string("{dx}"); 4267 case 'S': return std::string("{si}"); 4268 case 'D': return std::string("{di}"); 4269 case 'p': // address 4270 return std::string("im"); 4271 case 't': // top of floating point stack. 4272 return std::string("{st}"); 4273 case 'u': // second from top of floating point stack. 4274 return std::string("{st(1)}"); // second from top of floating point stack. 4275 case 'Y': 4276 switch (Constraint[1]) { 4277 default: 4278 // Break from inner switch and fall through (copy single char), 4279 // continue parsing after copying the current constraint into 4280 // the return string. 4281 break; 4282 case 'k': 4283 // "^" hints llvm that this is a 2 letter constraint. 4284 // "Constraint++" is used to promote the string iterator 4285 // to the next constraint. 4286 return std::string("^") + std::string(Constraint++, 2); 4287 } 4288 LLVM_FALLTHROUGH; 4289 default: 4290 return std::string(1, *Constraint); 4291 } 4292 } 4293 4294 // X86-32 generic target 4295 class X86_32TargetInfo : public X86TargetInfo { 4296 public: 4297 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4298 : X86TargetInfo(Triple, Opts) { 4299 DoubleAlign = LongLongAlign = 32; 4300 LongDoubleWidth = 96; 4301 LongDoubleAlign = 32; 4302 SuitableAlign = 128; 4303 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4304 SizeType = UnsignedInt; 4305 PtrDiffType = SignedInt; 4306 IntPtrType = SignedInt; 4307 RegParmMax = 3; 4308 4309 // Use fpret for all types. 4310 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4311 (1 << TargetInfo::Double) | 4312 (1 << TargetInfo::LongDouble)); 4313 4314 // x86-32 has atomics up to 8 bytes 4315 // FIXME: Check that we actually have cmpxchg8b before setting 4316 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4317 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4318 } 4319 BuiltinVaListKind getBuiltinVaListKind() const override { 4320 return TargetInfo::CharPtrBuiltinVaList; 4321 } 4322 4323 int getEHDataRegisterNumber(unsigned RegNo) const override { 4324 if (RegNo == 0) return 0; 4325 if (RegNo == 1) return 2; 4326 return -1; 4327 } 4328 bool validateOperandSize(StringRef Constraint, 4329 unsigned Size) const override { 4330 switch (Constraint[0]) { 4331 default: break; 4332 case 'R': 4333 case 'q': 4334 case 'Q': 4335 case 'a': 4336 case 'b': 4337 case 'c': 4338 case 'd': 4339 case 'S': 4340 case 'D': 4341 return Size <= 32; 4342 case 'A': 4343 return Size <= 64; 4344 } 4345 4346 return X86TargetInfo::validateOperandSize(Constraint, Size); 4347 } 4348 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4349 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4350 Builtin::FirstTSBuiltin + 1); 4351 } 4352 }; 4353 4354 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4355 public: 4356 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4357 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4358 4359 unsigned getFloatEvalMethod() const override { 4360 unsigned Major, Minor, Micro; 4361 getTriple().getOSVersion(Major, Minor, Micro); 4362 // New NetBSD uses the default rounding mode. 4363 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4364 return X86_32TargetInfo::getFloatEvalMethod(); 4365 // NetBSD before 6.99.26 defaults to "double" rounding. 4366 return 1; 4367 } 4368 }; 4369 4370 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4371 public: 4372 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4373 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4374 SizeType = UnsignedLong; 4375 IntPtrType = SignedLong; 4376 PtrDiffType = SignedLong; 4377 } 4378 }; 4379 4380 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4381 public: 4382 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4383 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4384 SizeType = UnsignedLong; 4385 IntPtrType = SignedLong; 4386 PtrDiffType = SignedLong; 4387 } 4388 }; 4389 4390 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4391 public: 4392 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4393 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4394 LongDoubleWidth = 128; 4395 LongDoubleAlign = 128; 4396 SuitableAlign = 128; 4397 MaxVectorAlign = 256; 4398 // The watchOS simulator uses the builtin bool type for Objective-C. 4399 llvm::Triple T = llvm::Triple(Triple); 4400 if (T.isWatchOS()) 4401 UseSignedCharForObjCBool = false; 4402 SizeType = UnsignedLong; 4403 IntPtrType = SignedLong; 4404 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4405 HasAlignMac68kSupport = true; 4406 } 4407 4408 bool handleTargetFeatures(std::vector<std::string> &Features, 4409 DiagnosticsEngine &Diags) override { 4410 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4411 Diags)) 4412 return false; 4413 // We now know the features we have: we can decide how to align vectors. 4414 MaxVectorAlign = 4415 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4416 return true; 4417 } 4418 }; 4419 4420 // x86-32 Windows target 4421 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4422 public: 4423 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4424 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4425 WCharType = UnsignedShort; 4426 DoubleAlign = LongLongAlign = 64; 4427 bool IsWinCOFF = 4428 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4429 resetDataLayout(IsWinCOFF 4430 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4431 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4432 } 4433 void getTargetDefines(const LangOptions &Opts, 4434 MacroBuilder &Builder) const override { 4435 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4436 } 4437 }; 4438 4439 // x86-32 Windows Visual Studio target 4440 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4441 public: 4442 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4443 const TargetOptions &Opts) 4444 : WindowsX86_32TargetInfo(Triple, Opts) { 4445 LongDoubleWidth = LongDoubleAlign = 64; 4446 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4447 } 4448 void getTargetDefines(const LangOptions &Opts, 4449 MacroBuilder &Builder) const override { 4450 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4451 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4452 // The value of the following reflects processor type. 4453 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4454 // We lost the original triple, so we use the default. 4455 Builder.defineMacro("_M_IX86", "600"); 4456 } 4457 }; 4458 4459 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4460 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4461 // supports __declspec natively under -fms-extensions, but we define a no-op 4462 // __declspec macro anyway for pre-processor compatibility. 4463 if (Opts.MicrosoftExt) 4464 Builder.defineMacro("__declspec", "__declspec"); 4465 else 4466 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4467 4468 if (!Opts.MicrosoftExt) { 4469 // Provide macros for all the calling convention keywords. Provide both 4470 // single and double underscore prefixed variants. These are available on 4471 // x64 as well as x86, even though they have no effect. 4472 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4473 for (const char *CC : CCs) { 4474 std::string GCCSpelling = "__attribute__((__"; 4475 GCCSpelling += CC; 4476 GCCSpelling += "__))"; 4477 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4478 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4479 } 4480 } 4481 } 4482 4483 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4484 Builder.defineMacro("__MSVCRT__"); 4485 Builder.defineMacro("__MINGW32__"); 4486 addCygMingDefines(Opts, Builder); 4487 } 4488 4489 // x86-32 MinGW target 4490 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4491 public: 4492 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4493 : WindowsX86_32TargetInfo(Triple, Opts) {} 4494 void getTargetDefines(const LangOptions &Opts, 4495 MacroBuilder &Builder) const override { 4496 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4497 DefineStd(Builder, "WIN32", Opts); 4498 DefineStd(Builder, "WINNT", Opts); 4499 Builder.defineMacro("_X86_"); 4500 addMinGWDefines(Opts, Builder); 4501 } 4502 }; 4503 4504 // x86-32 Cygwin target 4505 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4506 public: 4507 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4508 : X86_32TargetInfo(Triple, Opts) { 4509 WCharType = UnsignedShort; 4510 DoubleAlign = LongLongAlign = 64; 4511 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4512 } 4513 void getTargetDefines(const LangOptions &Opts, 4514 MacroBuilder &Builder) const override { 4515 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4516 Builder.defineMacro("_X86_"); 4517 Builder.defineMacro("__CYGWIN__"); 4518 Builder.defineMacro("__CYGWIN32__"); 4519 addCygMingDefines(Opts, Builder); 4520 DefineStd(Builder, "unix", Opts); 4521 if (Opts.CPlusPlus) 4522 Builder.defineMacro("_GNU_SOURCE"); 4523 } 4524 }; 4525 4526 // x86-32 Haiku target 4527 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4528 public: 4529 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4530 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4531 } 4532 void getTargetDefines(const LangOptions &Opts, 4533 MacroBuilder &Builder) const override { 4534 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4535 Builder.defineMacro("__INTEL__"); 4536 } 4537 }; 4538 4539 // X86-32 MCU target 4540 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4541 public: 4542 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4543 : X86_32TargetInfo(Triple, Opts) { 4544 LongDoubleWidth = 64; 4545 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4546 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4547 WIntType = UnsignedInt; 4548 } 4549 4550 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4551 // On MCU we support only C calling convention. 4552 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4553 } 4554 4555 void getTargetDefines(const LangOptions &Opts, 4556 MacroBuilder &Builder) const override { 4557 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4558 Builder.defineMacro("__iamcu"); 4559 Builder.defineMacro("__iamcu__"); 4560 } 4561 4562 bool allowsLargerPreferedTypeAlignment() const override { 4563 return false; 4564 } 4565 }; 4566 4567 // RTEMS Target 4568 template<typename Target> 4569 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4570 protected: 4571 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4572 MacroBuilder &Builder) const override { 4573 // RTEMS defines; list based off of gcc output 4574 4575 Builder.defineMacro("__rtems__"); 4576 Builder.defineMacro("__ELF__"); 4577 } 4578 4579 public: 4580 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4581 : OSTargetInfo<Target>(Triple, Opts) { 4582 switch (Triple.getArch()) { 4583 default: 4584 case llvm::Triple::x86: 4585 // this->MCountName = ".mcount"; 4586 break; 4587 case llvm::Triple::mips: 4588 case llvm::Triple::mipsel: 4589 case llvm::Triple::ppc: 4590 case llvm::Triple::ppc64: 4591 case llvm::Triple::ppc64le: 4592 // this->MCountName = "_mcount"; 4593 break; 4594 case llvm::Triple::arm: 4595 // this->MCountName = "__mcount"; 4596 break; 4597 } 4598 } 4599 }; 4600 4601 // x86-32 RTEMS target 4602 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4603 public: 4604 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4605 : X86_32TargetInfo(Triple, Opts) { 4606 SizeType = UnsignedLong; 4607 IntPtrType = SignedLong; 4608 PtrDiffType = SignedLong; 4609 } 4610 void getTargetDefines(const LangOptions &Opts, 4611 MacroBuilder &Builder) const override { 4612 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4613 Builder.defineMacro("__INTEL__"); 4614 Builder.defineMacro("__rtems__"); 4615 } 4616 }; 4617 4618 // x86-64 generic target 4619 class X86_64TargetInfo : public X86TargetInfo { 4620 public: 4621 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4622 : X86TargetInfo(Triple, Opts) { 4623 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4624 bool IsWinCOFF = 4625 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4626 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4627 LongDoubleWidth = 128; 4628 LongDoubleAlign = 128; 4629 LargeArrayMinWidth = 128; 4630 LargeArrayAlign = 128; 4631 SuitableAlign = 128; 4632 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4633 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4634 IntPtrType = IsX32 ? SignedInt : SignedLong; 4635 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4636 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4637 RegParmMax = 6; 4638 4639 // Pointers are 32-bit in x32. 4640 resetDataLayout(IsX32 4641 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4642 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4643 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4644 4645 // Use fpret only for long double. 4646 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4647 4648 // Use fp2ret for _Complex long double. 4649 ComplexLongDoubleUsesFP2Ret = true; 4650 4651 // Make __builtin_ms_va_list available. 4652 HasBuiltinMSVaList = true; 4653 4654 // x86-64 has atomics up to 16 bytes. 4655 MaxAtomicPromoteWidth = 128; 4656 MaxAtomicInlineWidth = 128; 4657 } 4658 BuiltinVaListKind getBuiltinVaListKind() const override { 4659 return TargetInfo::X86_64ABIBuiltinVaList; 4660 } 4661 4662 int getEHDataRegisterNumber(unsigned RegNo) const override { 4663 if (RegNo == 0) return 0; 4664 if (RegNo == 1) return 1; 4665 return -1; 4666 } 4667 4668 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4669 switch (CC) { 4670 case CC_C: 4671 case CC_Swift: 4672 case CC_X86VectorCall: 4673 case CC_IntelOclBicc: 4674 case CC_X86_64Win64: 4675 case CC_PreserveMost: 4676 case CC_PreserveAll: 4677 case CC_X86RegCall: 4678 return CCCR_OK; 4679 default: 4680 return CCCR_Warning; 4681 } 4682 } 4683 4684 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4685 return CC_C; 4686 } 4687 4688 // for x32 we need it here explicitly 4689 bool hasInt128Type() const override { return true; } 4690 unsigned getUnwindWordWidth() const override { return 64; } 4691 unsigned getRegisterWidth() const override { return 64; } 4692 4693 bool validateGlobalRegisterVariable(StringRef RegName, 4694 unsigned RegSize, 4695 bool &HasSizeMismatch) const override { 4696 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4697 // handle. 4698 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4699 // Check that the register size is 64-bit. 4700 HasSizeMismatch = RegSize != 64; 4701 return true; 4702 } 4703 4704 // Check if the register is a 32-bit register the backend can handle. 4705 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4706 HasSizeMismatch); 4707 } 4708 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4709 return llvm::makeArrayRef(BuiltinInfoX86, 4710 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4711 } 4712 }; 4713 4714 // x86-64 Windows target 4715 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4716 public: 4717 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4718 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4719 WCharType = UnsignedShort; 4720 LongWidth = LongAlign = 32; 4721 DoubleAlign = LongLongAlign = 64; 4722 IntMaxType = SignedLongLong; 4723 Int64Type = SignedLongLong; 4724 SizeType = UnsignedLongLong; 4725 PtrDiffType = SignedLongLong; 4726 IntPtrType = SignedLongLong; 4727 } 4728 4729 void getTargetDefines(const LangOptions &Opts, 4730 MacroBuilder &Builder) const override { 4731 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4732 Builder.defineMacro("_WIN64"); 4733 } 4734 4735 BuiltinVaListKind getBuiltinVaListKind() const override { 4736 return TargetInfo::CharPtrBuiltinVaList; 4737 } 4738 4739 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4740 switch (CC) { 4741 case CC_X86StdCall: 4742 case CC_X86ThisCall: 4743 case CC_X86FastCall: 4744 return CCCR_Ignore; 4745 case CC_C: 4746 case CC_X86VectorCall: 4747 case CC_IntelOclBicc: 4748 case CC_X86_64SysV: 4749 case CC_Swift: 4750 case CC_X86RegCall: 4751 return CCCR_OK; 4752 default: 4753 return CCCR_Warning; 4754 } 4755 } 4756 }; 4757 4758 // x86-64 Windows Visual Studio target 4759 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4760 public: 4761 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4762 const TargetOptions &Opts) 4763 : WindowsX86_64TargetInfo(Triple, Opts) { 4764 LongDoubleWidth = LongDoubleAlign = 64; 4765 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4766 } 4767 void getTargetDefines(const LangOptions &Opts, 4768 MacroBuilder &Builder) const override { 4769 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4770 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4771 Builder.defineMacro("_M_X64", "100"); 4772 Builder.defineMacro("_M_AMD64", "100"); 4773 } 4774 }; 4775 4776 // x86-64 MinGW target 4777 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4778 public: 4779 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4780 : WindowsX86_64TargetInfo(Triple, Opts) { 4781 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4782 // with x86 FP ops. Weird. 4783 LongDoubleWidth = LongDoubleAlign = 128; 4784 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4785 } 4786 4787 void getTargetDefines(const LangOptions &Opts, 4788 MacroBuilder &Builder) const override { 4789 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4790 DefineStd(Builder, "WIN64", Opts); 4791 Builder.defineMacro("__MINGW64__"); 4792 addMinGWDefines(Opts, Builder); 4793 4794 // GCC defines this macro when it is using __gxx_personality_seh0. 4795 if (!Opts.SjLjExceptions) 4796 Builder.defineMacro("__SEH__"); 4797 } 4798 }; 4799 4800 // x86-64 Cygwin target 4801 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4802 public: 4803 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4804 : X86_64TargetInfo(Triple, Opts) { 4805 TLSSupported = false; 4806 WCharType = UnsignedShort; 4807 } 4808 void getTargetDefines(const LangOptions &Opts, 4809 MacroBuilder &Builder) const override { 4810 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4811 Builder.defineMacro("__x86_64__"); 4812 Builder.defineMacro("__CYGWIN__"); 4813 Builder.defineMacro("__CYGWIN64__"); 4814 addCygMingDefines(Opts, Builder); 4815 DefineStd(Builder, "unix", Opts); 4816 if (Opts.CPlusPlus) 4817 Builder.defineMacro("_GNU_SOURCE"); 4818 4819 // GCC defines this macro when it is using __gxx_personality_seh0. 4820 if (!Opts.SjLjExceptions) 4821 Builder.defineMacro("__SEH__"); 4822 } 4823 }; 4824 4825 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4826 public: 4827 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4828 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4829 Int64Type = SignedLongLong; 4830 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4831 llvm::Triple T = llvm::Triple(Triple); 4832 if (T.isiOS()) 4833 UseSignedCharForObjCBool = false; 4834 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4835 } 4836 4837 bool handleTargetFeatures(std::vector<std::string> &Features, 4838 DiagnosticsEngine &Diags) override { 4839 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4840 Diags)) 4841 return false; 4842 // We now know the features we have: we can decide how to align vectors. 4843 MaxVectorAlign = 4844 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4845 return true; 4846 } 4847 }; 4848 4849 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4850 public: 4851 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4852 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4853 IntMaxType = SignedLongLong; 4854 Int64Type = SignedLongLong; 4855 } 4856 }; 4857 4858 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4859 public: 4860 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4861 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4862 IntMaxType = SignedLongLong; 4863 Int64Type = SignedLongLong; 4864 } 4865 }; 4866 4867 class ARMTargetInfo : public TargetInfo { 4868 // Possible FPU choices. 4869 enum FPUMode { 4870 VFP2FPU = (1 << 0), 4871 VFP3FPU = (1 << 1), 4872 VFP4FPU = (1 << 2), 4873 NeonFPU = (1 << 3), 4874 FPARMV8 = (1 << 4) 4875 }; 4876 4877 // Possible HWDiv features. 4878 enum HWDivMode { 4879 HWDivThumb = (1 << 0), 4880 HWDivARM = (1 << 1) 4881 }; 4882 4883 static bool FPUModeIsVFP(FPUMode Mode) { 4884 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4885 } 4886 4887 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4888 static const char * const GCCRegNames[]; 4889 4890 std::string ABI, CPU; 4891 4892 StringRef CPUProfile; 4893 StringRef CPUAttr; 4894 4895 enum { 4896 FP_Default, 4897 FP_VFP, 4898 FP_Neon 4899 } FPMath; 4900 4901 unsigned ArchISA; 4902 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4903 unsigned ArchProfile; 4904 unsigned ArchVersion; 4905 4906 unsigned FPU : 5; 4907 4908 unsigned IsAAPCS : 1; 4909 unsigned HWDiv : 2; 4910 4911 // Initialized via features. 4912 unsigned SoftFloat : 1; 4913 unsigned SoftFloatABI : 1; 4914 4915 unsigned CRC : 1; 4916 unsigned Crypto : 1; 4917 unsigned DSP : 1; 4918 unsigned Unaligned : 1; 4919 4920 enum { 4921 LDREX_B = (1 << 0), /// byte (8-bit) 4922 LDREX_H = (1 << 1), /// half (16-bit) 4923 LDREX_W = (1 << 2), /// word (32-bit) 4924 LDREX_D = (1 << 3), /// double (64-bit) 4925 }; 4926 4927 uint32_t LDREX; 4928 4929 // ACLE 6.5.1 Hardware floating point 4930 enum { 4931 HW_FP_HP = (1 << 1), /// half (16-bit) 4932 HW_FP_SP = (1 << 2), /// single (32-bit) 4933 HW_FP_DP = (1 << 3), /// double (64-bit) 4934 }; 4935 uint32_t HW_FP; 4936 4937 static const Builtin::Info BuiltinInfo[]; 4938 4939 void setABIAAPCS() { 4940 IsAAPCS = true; 4941 4942 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4943 const llvm::Triple &T = getTriple(); 4944 4945 // size_t is unsigned long on MachO-derived environments, NetBSD, 4946 // OpenBSD and Bitrig. 4947 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4948 T.getOS() == llvm::Triple::OpenBSD || 4949 T.getOS() == llvm::Triple::Bitrig) 4950 SizeType = UnsignedLong; 4951 else 4952 SizeType = UnsignedInt; 4953 4954 switch (T.getOS()) { 4955 case llvm::Triple::NetBSD: 4956 case llvm::Triple::OpenBSD: 4957 WCharType = SignedInt; 4958 break; 4959 case llvm::Triple::Win32: 4960 WCharType = UnsignedShort; 4961 break; 4962 case llvm::Triple::Linux: 4963 default: 4964 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4965 WCharType = UnsignedInt; 4966 break; 4967 } 4968 4969 UseBitFieldTypeAlignment = true; 4970 4971 ZeroLengthBitfieldBoundary = 0; 4972 4973 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4974 // so set preferred for small types to 32. 4975 if (T.isOSBinFormatMachO()) { 4976 resetDataLayout(BigEndian 4977 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4978 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4979 } else if (T.isOSWindows()) { 4980 assert(!BigEndian && "Windows on ARM does not support big endian"); 4981 resetDataLayout("e" 4982 "-m:w" 4983 "-p:32:32" 4984 "-i64:64" 4985 "-v128:64:128" 4986 "-a:0:32" 4987 "-n32" 4988 "-S64"); 4989 } else if (T.isOSNaCl()) { 4990 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4991 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4992 } else { 4993 resetDataLayout(BigEndian 4994 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4995 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4996 } 4997 4998 // FIXME: Enumerated types are variable width in straight AAPCS. 4999 } 5000 5001 void setABIAPCS(bool IsAAPCS16) { 5002 const llvm::Triple &T = getTriple(); 5003 5004 IsAAPCS = false; 5005 5006 if (IsAAPCS16) 5007 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5008 else 5009 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5010 5011 // size_t is unsigned int on FreeBSD. 5012 if (T.getOS() == llvm::Triple::FreeBSD) 5013 SizeType = UnsignedInt; 5014 else 5015 SizeType = UnsignedLong; 5016 5017 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5018 WCharType = SignedInt; 5019 5020 // Do not respect the alignment of bit-field types when laying out 5021 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5022 UseBitFieldTypeAlignment = false; 5023 5024 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5025 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5026 /// gcc. 5027 ZeroLengthBitfieldBoundary = 32; 5028 5029 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5030 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5031 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5032 } else if (T.isOSBinFormatMachO()) 5033 resetDataLayout( 5034 BigEndian 5035 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5036 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5037 else 5038 resetDataLayout( 5039 BigEndian 5040 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5041 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5042 5043 // FIXME: Override "preferred align" for double and long long. 5044 } 5045 5046 void setArchInfo() { 5047 StringRef ArchName = getTriple().getArchName(); 5048 5049 ArchISA = llvm::ARM::parseArchISA(ArchName); 5050 CPU = llvm::ARM::getDefaultCPU(ArchName); 5051 unsigned AK = llvm::ARM::parseArch(ArchName); 5052 if (AK != llvm::ARM::AK_INVALID) 5053 ArchKind = AK; 5054 setArchInfo(ArchKind); 5055 } 5056 5057 void setArchInfo(unsigned Kind) { 5058 StringRef SubArch; 5059 5060 // cache TargetParser info 5061 ArchKind = Kind; 5062 SubArch = llvm::ARM::getSubArch(ArchKind); 5063 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5064 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5065 5066 // cache CPU related strings 5067 CPUAttr = getCPUAttr(); 5068 CPUProfile = getCPUProfile(); 5069 } 5070 5071 void setAtomic() { 5072 // when triple does not specify a sub arch, 5073 // then we are not using inline atomics 5074 bool ShouldUseInlineAtomic = 5075 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5076 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5077 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5078 if (ArchProfile == llvm::ARM::PK_M) { 5079 MaxAtomicPromoteWidth = 32; 5080 if (ShouldUseInlineAtomic) 5081 MaxAtomicInlineWidth = 32; 5082 } 5083 else { 5084 MaxAtomicPromoteWidth = 64; 5085 if (ShouldUseInlineAtomic) 5086 MaxAtomicInlineWidth = 64; 5087 } 5088 } 5089 5090 bool isThumb() const { 5091 return (ArchISA == llvm::ARM::IK_THUMB); 5092 } 5093 5094 bool supportsThumb() const { 5095 return CPUAttr.count('T') || ArchVersion >= 6; 5096 } 5097 5098 bool supportsThumb2() const { 5099 return CPUAttr.equals("6T2") || 5100 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5101 } 5102 5103 StringRef getCPUAttr() const { 5104 // For most sub-arches, the build attribute CPU name is enough. 5105 // For Cortex variants, it's slightly different. 5106 switch(ArchKind) { 5107 default: 5108 return llvm::ARM::getCPUAttr(ArchKind); 5109 case llvm::ARM::AK_ARMV6M: 5110 return "6M"; 5111 case llvm::ARM::AK_ARMV7S: 5112 return "7S"; 5113 case llvm::ARM::AK_ARMV7A: 5114 return "7A"; 5115 case llvm::ARM::AK_ARMV7R: 5116 return "7R"; 5117 case llvm::ARM::AK_ARMV7M: 5118 return "7M"; 5119 case llvm::ARM::AK_ARMV7EM: 5120 return "7EM"; 5121 case llvm::ARM::AK_ARMV7VE: 5122 return "7VE"; 5123 case llvm::ARM::AK_ARMV8A: 5124 return "8A"; 5125 case llvm::ARM::AK_ARMV8_1A: 5126 return "8_1A"; 5127 case llvm::ARM::AK_ARMV8_2A: 5128 return "8_2A"; 5129 case llvm::ARM::AK_ARMV8MBaseline: 5130 return "8M_BASE"; 5131 case llvm::ARM::AK_ARMV8MMainline: 5132 return "8M_MAIN"; 5133 case llvm::ARM::AK_ARMV8R: 5134 return "8R"; 5135 } 5136 } 5137 5138 StringRef getCPUProfile() const { 5139 switch(ArchProfile) { 5140 case llvm::ARM::PK_A: 5141 return "A"; 5142 case llvm::ARM::PK_R: 5143 return "R"; 5144 case llvm::ARM::PK_M: 5145 return "M"; 5146 default: 5147 return ""; 5148 } 5149 } 5150 5151 public: 5152 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5153 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5154 HW_FP(0) { 5155 5156 switch (getTriple().getOS()) { 5157 case llvm::Triple::NetBSD: 5158 case llvm::Triple::OpenBSD: 5159 PtrDiffType = SignedLong; 5160 break; 5161 default: 5162 PtrDiffType = SignedInt; 5163 break; 5164 } 5165 5166 // Cache arch related info. 5167 setArchInfo(); 5168 5169 // {} in inline assembly are neon specifiers, not assembly variant 5170 // specifiers. 5171 NoAsmVariants = true; 5172 5173 // FIXME: This duplicates code from the driver that sets the -target-abi 5174 // option - this code is used if -target-abi isn't passed and should 5175 // be unified in some way. 5176 if (Triple.isOSBinFormatMachO()) { 5177 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5178 // the frontend matches that. 5179 if (Triple.getEnvironment() == llvm::Triple::EABI || 5180 Triple.getOS() == llvm::Triple::UnknownOS || 5181 ArchProfile == llvm::ARM::PK_M) { 5182 setABI("aapcs"); 5183 } else if (Triple.isWatchABI()) { 5184 setABI("aapcs16"); 5185 } else { 5186 setABI("apcs-gnu"); 5187 } 5188 } else if (Triple.isOSWindows()) { 5189 // FIXME: this is invalid for WindowsCE 5190 setABI("aapcs"); 5191 } else { 5192 // Select the default based on the platform. 5193 switch (Triple.getEnvironment()) { 5194 case llvm::Triple::Android: 5195 case llvm::Triple::GNUEABI: 5196 case llvm::Triple::GNUEABIHF: 5197 case llvm::Triple::MuslEABI: 5198 case llvm::Triple::MuslEABIHF: 5199 setABI("aapcs-linux"); 5200 break; 5201 case llvm::Triple::EABIHF: 5202 case llvm::Triple::EABI: 5203 setABI("aapcs"); 5204 break; 5205 case llvm::Triple::GNU: 5206 setABI("apcs-gnu"); 5207 break; 5208 default: 5209 if (Triple.getOS() == llvm::Triple::NetBSD) 5210 setABI("apcs-gnu"); 5211 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5212 setABI("aapcs-linux"); 5213 else 5214 setABI("aapcs"); 5215 break; 5216 } 5217 } 5218 5219 // ARM targets default to using the ARM C++ ABI. 5220 TheCXXABI.set(TargetCXXABI::GenericARM); 5221 5222 // ARM has atomics up to 8 bytes 5223 setAtomic(); 5224 5225 // Do force alignment of members that follow zero length bitfields. If 5226 // the alignment of the zero-length bitfield is greater than the member 5227 // that follows it, `bar', `bar' will be aligned as the type of the 5228 // zero length bitfield. 5229 UseZeroLengthBitfieldAlignment = true; 5230 5231 if (Triple.getOS() == llvm::Triple::Linux || 5232 Triple.getOS() == llvm::Triple::UnknownOS) 5233 this->MCountName = 5234 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5235 } 5236 5237 StringRef getABI() const override { return ABI; } 5238 5239 bool setABI(const std::string &Name) override { 5240 ABI = Name; 5241 5242 // The defaults (above) are for AAPCS, check if we need to change them. 5243 // 5244 // FIXME: We need support for -meabi... we could just mangle it into the 5245 // name. 5246 if (Name == "apcs-gnu" || Name == "aapcs16") { 5247 setABIAPCS(Name == "aapcs16"); 5248 return true; 5249 } 5250 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5251 setABIAAPCS(); 5252 return true; 5253 } 5254 return false; 5255 } 5256 5257 // FIXME: This should be based on Arch attributes, not CPU names. 5258 bool 5259 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5260 StringRef CPU, 5261 const std::vector<std::string> &FeaturesVec) const override { 5262 5263 std::vector<StringRef> TargetFeatures; 5264 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5265 5266 // get default FPU features 5267 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5268 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5269 5270 // get default Extension features 5271 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5272 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5273 5274 for (auto Feature : TargetFeatures) 5275 if (Feature[0] == '+') 5276 Features[Feature.drop_front(1)] = true; 5277 5278 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5279 } 5280 5281 bool handleTargetFeatures(std::vector<std::string> &Features, 5282 DiagnosticsEngine &Diags) override { 5283 FPU = 0; 5284 CRC = 0; 5285 Crypto = 0; 5286 DSP = 0; 5287 Unaligned = 1; 5288 SoftFloat = SoftFloatABI = false; 5289 HWDiv = 0; 5290 5291 // This does not diagnose illegal cases like having both 5292 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5293 uint32_t HW_FP_remove = 0; 5294 for (const auto &Feature : Features) { 5295 if (Feature == "+soft-float") { 5296 SoftFloat = true; 5297 } else if (Feature == "+soft-float-abi") { 5298 SoftFloatABI = true; 5299 } else if (Feature == "+vfp2") { 5300 FPU |= VFP2FPU; 5301 HW_FP |= HW_FP_SP | HW_FP_DP; 5302 } else if (Feature == "+vfp3") { 5303 FPU |= VFP3FPU; 5304 HW_FP |= HW_FP_SP | HW_FP_DP; 5305 } else if (Feature == "+vfp4") { 5306 FPU |= VFP4FPU; 5307 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5308 } else if (Feature == "+fp-armv8") { 5309 FPU |= FPARMV8; 5310 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5311 } else if (Feature == "+neon") { 5312 FPU |= NeonFPU; 5313 HW_FP |= HW_FP_SP | HW_FP_DP; 5314 } else if (Feature == "+hwdiv") { 5315 HWDiv |= HWDivThumb; 5316 } else if (Feature == "+hwdiv-arm") { 5317 HWDiv |= HWDivARM; 5318 } else if (Feature == "+crc") { 5319 CRC = 1; 5320 } else if (Feature == "+crypto") { 5321 Crypto = 1; 5322 } else if (Feature == "+dsp") { 5323 DSP = 1; 5324 } else if (Feature == "+fp-only-sp") { 5325 HW_FP_remove |= HW_FP_DP; 5326 } else if (Feature == "+strict-align") { 5327 Unaligned = 0; 5328 } else if (Feature == "+fp16") { 5329 HW_FP |= HW_FP_HP; 5330 } 5331 } 5332 HW_FP &= ~HW_FP_remove; 5333 5334 switch (ArchVersion) { 5335 case 6: 5336 if (ArchProfile == llvm::ARM::PK_M) 5337 LDREX = 0; 5338 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5339 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5340 else 5341 LDREX = LDREX_W; 5342 break; 5343 case 7: 5344 if (ArchProfile == llvm::ARM::PK_M) 5345 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5346 else 5347 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5348 break; 5349 case 8: 5350 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5351 } 5352 5353 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5354 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5355 return false; 5356 } 5357 5358 if (FPMath == FP_Neon) 5359 Features.push_back("+neonfp"); 5360 else if (FPMath == FP_VFP) 5361 Features.push_back("-neonfp"); 5362 5363 // Remove front-end specific options which the backend handles differently. 5364 auto Feature = 5365 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5366 if (Feature != Features.end()) 5367 Features.erase(Feature); 5368 5369 return true; 5370 } 5371 5372 bool hasFeature(StringRef Feature) const override { 5373 return llvm::StringSwitch<bool>(Feature) 5374 .Case("arm", true) 5375 .Case("aarch32", true) 5376 .Case("softfloat", SoftFloat) 5377 .Case("thumb", isThumb()) 5378 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5379 .Case("hwdiv", HWDiv & HWDivThumb) 5380 .Case("hwdiv-arm", HWDiv & HWDivARM) 5381 .Default(false); 5382 } 5383 5384 bool setCPU(const std::string &Name) override { 5385 if (Name != "generic") 5386 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5387 5388 if (ArchKind == llvm::ARM::AK_INVALID) 5389 return false; 5390 setAtomic(); 5391 CPU = Name; 5392 return true; 5393 } 5394 5395 bool setFPMath(StringRef Name) override; 5396 5397 void getTargetDefines(const LangOptions &Opts, 5398 MacroBuilder &Builder) const override { 5399 // Target identification. 5400 Builder.defineMacro("__arm"); 5401 Builder.defineMacro("__arm__"); 5402 // For bare-metal none-eabi. 5403 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5404 getTriple().getEnvironment() == llvm::Triple::EABI) 5405 Builder.defineMacro("__ELF__"); 5406 5407 // Target properties. 5408 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5409 5410 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5411 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5412 if (getTriple().isWatchABI()) 5413 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5414 5415 if (!CPUAttr.empty()) 5416 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5417 5418 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5419 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5420 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5421 5422 if (ArchVersion >= 8) { 5423 // ACLE 6.5.7 Crypto Extension 5424 if (Crypto) 5425 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5426 // ACLE 6.5.8 CRC32 Extension 5427 if (CRC) 5428 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5429 // ACLE 6.5.10 Numeric Maximum and Minimum 5430 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5431 // ACLE 6.5.9 Directed Rounding 5432 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5433 } 5434 5435 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5436 // is not defined for the M-profile. 5437 // NOTE that the default profile is assumed to be 'A' 5438 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5439 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5440 5441 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5442 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5443 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5444 // v7 and v8 architectures excluding v8-M Baseline. 5445 if (supportsThumb2()) 5446 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5447 else if (supportsThumb()) 5448 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5449 5450 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5451 // instruction set such as ARM or Thumb. 5452 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5453 5454 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5455 5456 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5457 if (!CPUProfile.empty()) 5458 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5459 5460 // ACLE 6.4.3 Unaligned access supported in hardware 5461 if (Unaligned) 5462 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5463 5464 // ACLE 6.4.4 LDREX/STREX 5465 if (LDREX) 5466 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5467 5468 // ACLE 6.4.5 CLZ 5469 if (ArchVersion == 5 || 5470 (ArchVersion == 6 && CPUProfile != "M") || 5471 ArchVersion > 6) 5472 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5473 5474 // ACLE 6.5.1 Hardware Floating Point 5475 if (HW_FP) 5476 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5477 5478 // ACLE predefines. 5479 Builder.defineMacro("__ARM_ACLE", "200"); 5480 5481 // FP16 support (we currently only support IEEE format). 5482 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5483 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5484 5485 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5486 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5487 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5488 5489 // Subtarget options. 5490 5491 // FIXME: It's more complicated than this and we don't really support 5492 // interworking. 5493 // Windows on ARM does not "support" interworking 5494 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5495 Builder.defineMacro("__THUMB_INTERWORK__"); 5496 5497 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5498 // Embedded targets on Darwin follow AAPCS, but not EABI. 5499 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5500 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5501 Builder.defineMacro("__ARM_EABI__"); 5502 Builder.defineMacro("__ARM_PCS", "1"); 5503 } 5504 5505 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5506 ABI == "aapcs16") 5507 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5508 5509 if (SoftFloat) 5510 Builder.defineMacro("__SOFTFP__"); 5511 5512 if (ArchKind == llvm::ARM::AK_XSCALE) 5513 Builder.defineMacro("__XSCALE__"); 5514 5515 if (isThumb()) { 5516 Builder.defineMacro("__THUMBEL__"); 5517 Builder.defineMacro("__thumb__"); 5518 if (supportsThumb2()) 5519 Builder.defineMacro("__thumb2__"); 5520 } 5521 5522 // ACLE 6.4.9 32-bit SIMD instructions 5523 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5524 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5525 5526 // ACLE 6.4.10 Hardware Integer Divide 5527 if (((HWDiv & HWDivThumb) && isThumb()) || 5528 ((HWDiv & HWDivARM) && !isThumb())) { 5529 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5530 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5531 } 5532 5533 // Note, this is always on in gcc, even though it doesn't make sense. 5534 Builder.defineMacro("__APCS_32__"); 5535 5536 if (FPUModeIsVFP((FPUMode) FPU)) { 5537 Builder.defineMacro("__VFP_FP__"); 5538 if (FPU & VFP2FPU) 5539 Builder.defineMacro("__ARM_VFPV2__"); 5540 if (FPU & VFP3FPU) 5541 Builder.defineMacro("__ARM_VFPV3__"); 5542 if (FPU & VFP4FPU) 5543 Builder.defineMacro("__ARM_VFPV4__"); 5544 if (FPU & FPARMV8) 5545 Builder.defineMacro("__ARM_FPV5__"); 5546 } 5547 5548 // This only gets set when Neon instructions are actually available, unlike 5549 // the VFP define, hence the soft float and arch check. This is subtly 5550 // different from gcc, we follow the intent which was that it should be set 5551 // when Neon instructions are actually available. 5552 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5553 Builder.defineMacro("__ARM_NEON", "1"); 5554 Builder.defineMacro("__ARM_NEON__"); 5555 // current AArch32 NEON implementations do not support double-precision 5556 // floating-point even when it is present in VFP. 5557 Builder.defineMacro("__ARM_NEON_FP", 5558 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5559 } 5560 5561 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5562 Opts.ShortWChar ? "2" : "4"); 5563 5564 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5565 Opts.ShortEnums ? "1" : "4"); 5566 5567 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5568 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5569 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5570 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5571 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5572 } 5573 5574 // ACLE 6.4.7 DSP instructions 5575 if (DSP) { 5576 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5577 } 5578 5579 // ACLE 6.4.8 Saturation instructions 5580 bool SAT = false; 5581 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5582 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5583 SAT = true; 5584 } 5585 5586 // ACLE 6.4.6 Q (saturation) flag 5587 if (DSP || SAT) 5588 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5589 5590 if (Opts.UnsafeFPMath) 5591 Builder.defineMacro("__ARM_FP_FAST", "1"); 5592 5593 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5594 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5595 } 5596 5597 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5598 return llvm::makeArrayRef(BuiltinInfo, 5599 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5600 } 5601 bool isCLZForZeroUndef() const override { return false; } 5602 BuiltinVaListKind getBuiltinVaListKind() const override { 5603 return IsAAPCS 5604 ? AAPCSABIBuiltinVaList 5605 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5606 : TargetInfo::VoidPtrBuiltinVaList); 5607 } 5608 ArrayRef<const char *> getGCCRegNames() const override; 5609 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5610 bool validateAsmConstraint(const char *&Name, 5611 TargetInfo::ConstraintInfo &Info) const override { 5612 switch (*Name) { 5613 default: break; 5614 case 'l': // r0-r7 5615 case 'h': // r8-r15 5616 case 't': // VFP Floating point register single precision 5617 case 'w': // VFP Floating point register double precision 5618 Info.setAllowsRegister(); 5619 return true; 5620 case 'I': 5621 case 'J': 5622 case 'K': 5623 case 'L': 5624 case 'M': 5625 // FIXME 5626 return true; 5627 case 'Q': // A memory address that is a single base register. 5628 Info.setAllowsMemory(); 5629 return true; 5630 case 'U': // a memory reference... 5631 switch (Name[1]) { 5632 case 'q': // ...ARMV4 ldrsb 5633 case 'v': // ...VFP load/store (reg+constant offset) 5634 case 'y': // ...iWMMXt load/store 5635 case 't': // address valid for load/store opaque types wider 5636 // than 128-bits 5637 case 'n': // valid address for Neon doubleword vector load/store 5638 case 'm': // valid address for Neon element and structure load/store 5639 case 's': // valid address for non-offset loads/stores of quad-word 5640 // values in four ARM registers 5641 Info.setAllowsMemory(); 5642 Name++; 5643 return true; 5644 } 5645 } 5646 return false; 5647 } 5648 std::string convertConstraint(const char *&Constraint) const override { 5649 std::string R; 5650 switch (*Constraint) { 5651 case 'U': // Two-character constraint; add "^" hint for later parsing. 5652 R = std::string("^") + std::string(Constraint, 2); 5653 Constraint++; 5654 break; 5655 case 'p': // 'p' should be translated to 'r' by default. 5656 R = std::string("r"); 5657 break; 5658 default: 5659 return std::string(1, *Constraint); 5660 } 5661 return R; 5662 } 5663 bool 5664 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5665 std::string &SuggestedModifier) const override { 5666 bool isOutput = (Constraint[0] == '='); 5667 bool isInOut = (Constraint[0] == '+'); 5668 5669 // Strip off constraint modifiers. 5670 while (Constraint[0] == '=' || 5671 Constraint[0] == '+' || 5672 Constraint[0] == '&') 5673 Constraint = Constraint.substr(1); 5674 5675 switch (Constraint[0]) { 5676 default: break; 5677 case 'r': { 5678 switch (Modifier) { 5679 default: 5680 return (isInOut || isOutput || Size <= 64); 5681 case 'q': 5682 // A register of size 32 cannot fit a vector type. 5683 return false; 5684 } 5685 } 5686 } 5687 5688 return true; 5689 } 5690 const char *getClobbers() const override { 5691 // FIXME: Is this really right? 5692 return ""; 5693 } 5694 5695 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5696 switch (CC) { 5697 case CC_AAPCS: 5698 case CC_AAPCS_VFP: 5699 case CC_Swift: 5700 return CCCR_OK; 5701 default: 5702 return CCCR_Warning; 5703 } 5704 } 5705 5706 int getEHDataRegisterNumber(unsigned RegNo) const override { 5707 if (RegNo == 0) return 0; 5708 if (RegNo == 1) return 1; 5709 return -1; 5710 } 5711 5712 bool hasSjLjLowering() const override { 5713 return true; 5714 } 5715 }; 5716 5717 bool ARMTargetInfo::setFPMath(StringRef Name) { 5718 if (Name == "neon") { 5719 FPMath = FP_Neon; 5720 return true; 5721 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5722 Name == "vfp4") { 5723 FPMath = FP_VFP; 5724 return true; 5725 } 5726 return false; 5727 } 5728 5729 const char * const ARMTargetInfo::GCCRegNames[] = { 5730 // Integer registers 5731 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5732 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5733 5734 // Float registers 5735 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5736 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5737 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5738 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5739 5740 // Double registers 5741 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5742 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5743 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5744 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5745 5746 // Quad registers 5747 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5748 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5749 }; 5750 5751 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5752 return llvm::makeArrayRef(GCCRegNames); 5753 } 5754 5755 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5756 { { "a1" }, "r0" }, 5757 { { "a2" }, "r1" }, 5758 { { "a3" }, "r2" }, 5759 { { "a4" }, "r3" }, 5760 { { "v1" }, "r4" }, 5761 { { "v2" }, "r5" }, 5762 { { "v3" }, "r6" }, 5763 { { "v4" }, "r7" }, 5764 { { "v5" }, "r8" }, 5765 { { "v6", "rfp" }, "r9" }, 5766 { { "sl" }, "r10" }, 5767 { { "fp" }, "r11" }, 5768 { { "ip" }, "r12" }, 5769 { { "r13" }, "sp" }, 5770 { { "r14" }, "lr" }, 5771 { { "r15" }, "pc" }, 5772 // The S, D and Q registers overlap, but aren't really aliases; we 5773 // don't want to substitute one of these for a different-sized one. 5774 }; 5775 5776 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5777 return llvm::makeArrayRef(GCCRegAliases); 5778 } 5779 5780 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5781 #define BUILTIN(ID, TYPE, ATTRS) \ 5782 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5783 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5784 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5785 #include "clang/Basic/BuiltinsNEON.def" 5786 5787 #define BUILTIN(ID, TYPE, ATTRS) \ 5788 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5789 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5790 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5791 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5792 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5793 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5794 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5795 #include "clang/Basic/BuiltinsARM.def" 5796 }; 5797 5798 class ARMleTargetInfo : public ARMTargetInfo { 5799 public: 5800 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5801 : ARMTargetInfo(Triple, Opts) {} 5802 void getTargetDefines(const LangOptions &Opts, 5803 MacroBuilder &Builder) const override { 5804 Builder.defineMacro("__ARMEL__"); 5805 ARMTargetInfo::getTargetDefines(Opts, Builder); 5806 } 5807 }; 5808 5809 class ARMbeTargetInfo : public ARMTargetInfo { 5810 public: 5811 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5812 : ARMTargetInfo(Triple, Opts) {} 5813 void getTargetDefines(const LangOptions &Opts, 5814 MacroBuilder &Builder) const override { 5815 Builder.defineMacro("__ARMEB__"); 5816 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5817 ARMTargetInfo::getTargetDefines(Opts, Builder); 5818 } 5819 }; 5820 5821 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5822 const llvm::Triple Triple; 5823 public: 5824 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5825 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5826 WCharType = UnsignedShort; 5827 SizeType = UnsignedInt; 5828 } 5829 void getVisualStudioDefines(const LangOptions &Opts, 5830 MacroBuilder &Builder) const { 5831 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5832 5833 // FIXME: this is invalid for WindowsCE 5834 Builder.defineMacro("_M_ARM_NT", "1"); 5835 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5836 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5837 5838 assert((Triple.getArch() == llvm::Triple::arm || 5839 Triple.getArch() == llvm::Triple::thumb) && 5840 "invalid architecture for Windows ARM target info"); 5841 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5842 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5843 5844 // TODO map the complete set of values 5845 // 31: VFPv3 40: VFPv4 5846 Builder.defineMacro("_M_ARM_FP", "31"); 5847 } 5848 BuiltinVaListKind getBuiltinVaListKind() const override { 5849 return TargetInfo::CharPtrBuiltinVaList; 5850 } 5851 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5852 switch (CC) { 5853 case CC_X86StdCall: 5854 case CC_X86ThisCall: 5855 case CC_X86FastCall: 5856 case CC_X86VectorCall: 5857 return CCCR_Ignore; 5858 case CC_C: 5859 return CCCR_OK; 5860 default: 5861 return CCCR_Warning; 5862 } 5863 } 5864 }; 5865 5866 // Windows ARM + Itanium C++ ABI Target 5867 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5868 public: 5869 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5870 const TargetOptions &Opts) 5871 : WindowsARMTargetInfo(Triple, Opts) { 5872 TheCXXABI.set(TargetCXXABI::GenericARM); 5873 } 5874 5875 void getTargetDefines(const LangOptions &Opts, 5876 MacroBuilder &Builder) const override { 5877 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5878 5879 if (Opts.MSVCCompat) 5880 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5881 } 5882 }; 5883 5884 // Windows ARM, MS (C++) ABI 5885 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5886 public: 5887 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5888 const TargetOptions &Opts) 5889 : WindowsARMTargetInfo(Triple, Opts) { 5890 TheCXXABI.set(TargetCXXABI::Microsoft); 5891 } 5892 5893 void getTargetDefines(const LangOptions &Opts, 5894 MacroBuilder &Builder) const override { 5895 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5896 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5897 } 5898 }; 5899 5900 // ARM MinGW target 5901 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5902 public: 5903 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5904 : WindowsARMTargetInfo(Triple, Opts) { 5905 TheCXXABI.set(TargetCXXABI::GenericARM); 5906 } 5907 5908 void getTargetDefines(const LangOptions &Opts, 5909 MacroBuilder &Builder) const override { 5910 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5911 DefineStd(Builder, "WIN32", Opts); 5912 DefineStd(Builder, "WINNT", Opts); 5913 Builder.defineMacro("_ARM_"); 5914 addMinGWDefines(Opts, Builder); 5915 } 5916 }; 5917 5918 // ARM Cygwin target 5919 class CygwinARMTargetInfo : public ARMleTargetInfo { 5920 public: 5921 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5922 : ARMleTargetInfo(Triple, Opts) { 5923 TLSSupported = false; 5924 WCharType = UnsignedShort; 5925 DoubleAlign = LongLongAlign = 64; 5926 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5927 } 5928 void getTargetDefines(const LangOptions &Opts, 5929 MacroBuilder &Builder) const override { 5930 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5931 Builder.defineMacro("_ARM_"); 5932 Builder.defineMacro("__CYGWIN__"); 5933 Builder.defineMacro("__CYGWIN32__"); 5934 DefineStd(Builder, "unix", Opts); 5935 if (Opts.CPlusPlus) 5936 Builder.defineMacro("_GNU_SOURCE"); 5937 } 5938 }; 5939 5940 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5941 protected: 5942 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5943 MacroBuilder &Builder) const override { 5944 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5945 } 5946 5947 public: 5948 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5949 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5950 HasAlignMac68kSupport = true; 5951 // iOS always has 64-bit atomic instructions. 5952 // FIXME: This should be based off of the target features in 5953 // ARMleTargetInfo. 5954 MaxAtomicInlineWidth = 64; 5955 5956 if (Triple.isWatchABI()) { 5957 // Darwin on iOS uses a variant of the ARM C++ ABI. 5958 TheCXXABI.set(TargetCXXABI::WatchOS); 5959 5960 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5961 // size_t is long, it's a bit weird for it to be int. 5962 PtrDiffType = SignedLong; 5963 5964 // BOOL should be a real boolean on the new ABI 5965 UseSignedCharForObjCBool = false; 5966 } else 5967 TheCXXABI.set(TargetCXXABI::iOS); 5968 } 5969 }; 5970 5971 class AArch64TargetInfo : public TargetInfo { 5972 virtual void setDataLayout() = 0; 5973 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5974 static const char *const GCCRegNames[]; 5975 5976 enum FPUModeEnum { 5977 FPUMode, 5978 NeonMode 5979 }; 5980 5981 unsigned FPU; 5982 unsigned CRC; 5983 unsigned Crypto; 5984 unsigned Unaligned; 5985 unsigned V8_1A; 5986 5987 static const Builtin::Info BuiltinInfo[]; 5988 5989 std::string ABI; 5990 5991 public: 5992 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5993 : TargetInfo(Triple), ABI("aapcs") { 5994 if (getTriple().getOS() == llvm::Triple::NetBSD || 5995 getTriple().getOS() == llvm::Triple::OpenBSD) { 5996 WCharType = SignedInt; 5997 5998 // NetBSD apparently prefers consistency across ARM targets to consistency 5999 // across 64-bit targets. 6000 Int64Type = SignedLongLong; 6001 IntMaxType = SignedLongLong; 6002 } else { 6003 WCharType = UnsignedInt; 6004 Int64Type = SignedLong; 6005 IntMaxType = SignedLong; 6006 } 6007 6008 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6009 MaxVectorAlign = 128; 6010 MaxAtomicInlineWidth = 128; 6011 MaxAtomicPromoteWidth = 128; 6012 6013 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6014 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6015 6016 // {} in inline assembly are neon specifiers, not assembly variant 6017 // specifiers. 6018 NoAsmVariants = true; 6019 6020 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6021 // contributes to the alignment of the containing aggregate in the same way 6022 // a plain (non bit-field) member of that type would, without exception for 6023 // zero-sized or anonymous bit-fields." 6024 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6025 UseZeroLengthBitfieldAlignment = true; 6026 6027 // AArch64 targets default to using the ARM C++ ABI. 6028 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6029 6030 if (Triple.getOS() == llvm::Triple::Linux) 6031 this->MCountName = "\01_mcount"; 6032 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6033 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6034 } 6035 6036 StringRef getABI() const override { return ABI; } 6037 bool setABI(const std::string &Name) override { 6038 if (Name != "aapcs" && Name != "darwinpcs") 6039 return false; 6040 6041 ABI = Name; 6042 return true; 6043 } 6044 6045 bool setCPU(const std::string &Name) override { 6046 return Name == "generic" || 6047 llvm::AArch64::parseCPUArch(Name) != 6048 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6049 } 6050 6051 void getTargetDefines(const LangOptions &Opts, 6052 MacroBuilder &Builder) const override { 6053 // Target identification. 6054 Builder.defineMacro("__aarch64__"); 6055 6056 // Target properties. 6057 Builder.defineMacro("_LP64"); 6058 Builder.defineMacro("__LP64__"); 6059 6060 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6061 Builder.defineMacro("__ARM_ACLE", "200"); 6062 Builder.defineMacro("__ARM_ARCH", "8"); 6063 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6064 6065 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6066 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6067 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6068 6069 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6070 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6071 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6072 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6073 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6074 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6075 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6076 6077 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6078 6079 // 0xe implies support for half, single and double precision operations. 6080 Builder.defineMacro("__ARM_FP", "0xE"); 6081 6082 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6083 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6084 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6085 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6086 6087 if (Opts.UnsafeFPMath) 6088 Builder.defineMacro("__ARM_FP_FAST", "1"); 6089 6090 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6091 6092 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6093 Opts.ShortEnums ? "1" : "4"); 6094 6095 if (FPU == NeonMode) { 6096 Builder.defineMacro("__ARM_NEON", "1"); 6097 // 64-bit NEON supports half, single and double precision operations. 6098 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6099 } 6100 6101 if (CRC) 6102 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6103 6104 if (Crypto) 6105 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6106 6107 if (Unaligned) 6108 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6109 6110 if (V8_1A) 6111 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6112 6113 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6114 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6115 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6116 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6117 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6118 } 6119 6120 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6121 return llvm::makeArrayRef(BuiltinInfo, 6122 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6123 } 6124 6125 bool hasFeature(StringRef Feature) const override { 6126 return Feature == "aarch64" || 6127 Feature == "arm64" || 6128 Feature == "arm" || 6129 (Feature == "neon" && FPU == NeonMode); 6130 } 6131 6132 bool handleTargetFeatures(std::vector<std::string> &Features, 6133 DiagnosticsEngine &Diags) override { 6134 FPU = FPUMode; 6135 CRC = 0; 6136 Crypto = 0; 6137 Unaligned = 1; 6138 V8_1A = 0; 6139 6140 for (const auto &Feature : Features) { 6141 if (Feature == "+neon") 6142 FPU = NeonMode; 6143 if (Feature == "+crc") 6144 CRC = 1; 6145 if (Feature == "+crypto") 6146 Crypto = 1; 6147 if (Feature == "+strict-align") 6148 Unaligned = 0; 6149 if (Feature == "+v8.1a") 6150 V8_1A = 1; 6151 } 6152 6153 setDataLayout(); 6154 6155 return true; 6156 } 6157 6158 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6159 switch (CC) { 6160 case CC_C: 6161 case CC_Swift: 6162 case CC_PreserveMost: 6163 case CC_PreserveAll: 6164 return CCCR_OK; 6165 default: 6166 return CCCR_Warning; 6167 } 6168 } 6169 6170 bool isCLZForZeroUndef() const override { return false; } 6171 6172 BuiltinVaListKind getBuiltinVaListKind() const override { 6173 return TargetInfo::AArch64ABIBuiltinVaList; 6174 } 6175 6176 ArrayRef<const char *> getGCCRegNames() const override; 6177 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6178 6179 bool validateAsmConstraint(const char *&Name, 6180 TargetInfo::ConstraintInfo &Info) const override { 6181 switch (*Name) { 6182 default: 6183 return false; 6184 case 'w': // Floating point and SIMD registers (V0-V31) 6185 Info.setAllowsRegister(); 6186 return true; 6187 case 'I': // Constant that can be used with an ADD instruction 6188 case 'J': // Constant that can be used with a SUB instruction 6189 case 'K': // Constant that can be used with a 32-bit logical instruction 6190 case 'L': // Constant that can be used with a 64-bit logical instruction 6191 case 'M': // Constant that can be used as a 32-bit MOV immediate 6192 case 'N': // Constant that can be used as a 64-bit MOV immediate 6193 case 'Y': // Floating point constant zero 6194 case 'Z': // Integer constant zero 6195 return true; 6196 case 'Q': // A memory reference with base register and no offset 6197 Info.setAllowsMemory(); 6198 return true; 6199 case 'S': // A symbolic address 6200 Info.setAllowsRegister(); 6201 return true; 6202 case 'U': 6203 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6204 // Utf: A memory address suitable for ldp/stp in TF mode. 6205 // Usa: An absolute symbolic address. 6206 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6207 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6208 case 'z': // Zero register, wzr or xzr 6209 Info.setAllowsRegister(); 6210 return true; 6211 case 'x': // Floating point and SIMD registers (V0-V15) 6212 Info.setAllowsRegister(); 6213 return true; 6214 } 6215 return false; 6216 } 6217 6218 bool 6219 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6220 std::string &SuggestedModifier) const override { 6221 // Strip off constraint modifiers. 6222 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6223 Constraint = Constraint.substr(1); 6224 6225 switch (Constraint[0]) { 6226 default: 6227 return true; 6228 case 'z': 6229 case 'r': { 6230 switch (Modifier) { 6231 case 'x': 6232 case 'w': 6233 // For now assume that the person knows what they're 6234 // doing with the modifier. 6235 return true; 6236 default: 6237 // By default an 'r' constraint will be in the 'x' 6238 // registers. 6239 if (Size == 64) 6240 return true; 6241 6242 SuggestedModifier = "w"; 6243 return false; 6244 } 6245 } 6246 } 6247 } 6248 6249 const char *getClobbers() const override { return ""; } 6250 6251 int getEHDataRegisterNumber(unsigned RegNo) const override { 6252 if (RegNo == 0) 6253 return 0; 6254 if (RegNo == 1) 6255 return 1; 6256 return -1; 6257 } 6258 }; 6259 6260 const char *const AArch64TargetInfo::GCCRegNames[] = { 6261 // 32-bit Integer registers 6262 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6263 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6264 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6265 6266 // 64-bit Integer registers 6267 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6268 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6269 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6270 6271 // 32-bit floating point regsisters 6272 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6273 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6274 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6275 6276 // 64-bit floating point regsisters 6277 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6278 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6279 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6280 6281 // Vector registers 6282 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6283 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6284 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6285 }; 6286 6287 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6288 return llvm::makeArrayRef(GCCRegNames); 6289 } 6290 6291 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6292 { { "w31" }, "wsp" }, 6293 { { "x29" }, "fp" }, 6294 { { "x30" }, "lr" }, 6295 { { "x31" }, "sp" }, 6296 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6297 // don't want to substitute one of these for a different-sized one. 6298 }; 6299 6300 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6301 return llvm::makeArrayRef(GCCRegAliases); 6302 } 6303 6304 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6305 #define BUILTIN(ID, TYPE, ATTRS) \ 6306 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6307 #include "clang/Basic/BuiltinsNEON.def" 6308 6309 #define BUILTIN(ID, TYPE, ATTRS) \ 6310 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6311 #include "clang/Basic/BuiltinsAArch64.def" 6312 }; 6313 6314 class AArch64leTargetInfo : public AArch64TargetInfo { 6315 void setDataLayout() override { 6316 if (getTriple().isOSBinFormatMachO()) 6317 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6318 else 6319 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6320 } 6321 6322 public: 6323 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6324 : AArch64TargetInfo(Triple, Opts) { 6325 } 6326 void getTargetDefines(const LangOptions &Opts, 6327 MacroBuilder &Builder) const override { 6328 Builder.defineMacro("__AARCH64EL__"); 6329 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6330 } 6331 }; 6332 6333 class AArch64beTargetInfo : public AArch64TargetInfo { 6334 void setDataLayout() override { 6335 assert(!getTriple().isOSBinFormatMachO()); 6336 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6337 } 6338 6339 public: 6340 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6341 : AArch64TargetInfo(Triple, Opts) {} 6342 void getTargetDefines(const LangOptions &Opts, 6343 MacroBuilder &Builder) const override { 6344 Builder.defineMacro("__AARCH64EB__"); 6345 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6346 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6347 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6348 } 6349 }; 6350 6351 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6352 protected: 6353 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6354 MacroBuilder &Builder) const override { 6355 Builder.defineMacro("__AARCH64_SIMD__"); 6356 Builder.defineMacro("__ARM64_ARCH_8__"); 6357 Builder.defineMacro("__ARM_NEON__"); 6358 Builder.defineMacro("__LITTLE_ENDIAN__"); 6359 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6360 Builder.defineMacro("__arm64", "1"); 6361 Builder.defineMacro("__arm64__", "1"); 6362 6363 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6364 } 6365 6366 public: 6367 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6368 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6369 Int64Type = SignedLongLong; 6370 WCharType = SignedInt; 6371 UseSignedCharForObjCBool = false; 6372 6373 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6374 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6375 6376 TheCXXABI.set(TargetCXXABI::iOS64); 6377 } 6378 6379 BuiltinVaListKind getBuiltinVaListKind() const override { 6380 return TargetInfo::CharPtrBuiltinVaList; 6381 } 6382 }; 6383 6384 // Hexagon abstract base class 6385 class HexagonTargetInfo : public TargetInfo { 6386 static const Builtin::Info BuiltinInfo[]; 6387 static const char * const GCCRegNames[]; 6388 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6389 std::string CPU; 6390 bool HasHVX, HasHVXDouble; 6391 bool UseLongCalls; 6392 6393 public: 6394 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6395 : TargetInfo(Triple) { 6396 // Specify the vector alignment explicitly. For v512x1, the calculated 6397 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6398 // the required minimum of 64 bytes. 6399 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6400 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6401 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6402 SizeType = UnsignedInt; 6403 PtrDiffType = SignedInt; 6404 IntPtrType = SignedInt; 6405 6406 // {} in inline assembly are packet specifiers, not assembly variant 6407 // specifiers. 6408 NoAsmVariants = true; 6409 6410 LargeArrayMinWidth = 64; 6411 LargeArrayAlign = 64; 6412 UseBitFieldTypeAlignment = true; 6413 ZeroLengthBitfieldBoundary = 32; 6414 HasHVX = HasHVXDouble = false; 6415 UseLongCalls = false; 6416 } 6417 6418 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6419 return llvm::makeArrayRef(BuiltinInfo, 6420 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6421 } 6422 6423 bool validateAsmConstraint(const char *&Name, 6424 TargetInfo::ConstraintInfo &Info) const override { 6425 switch (*Name) { 6426 case 'v': 6427 case 'q': 6428 if (HasHVX) { 6429 Info.setAllowsRegister(); 6430 return true; 6431 } 6432 break; 6433 case 's': 6434 // Relocatable constant. 6435 return true; 6436 } 6437 return false; 6438 } 6439 6440 void getTargetDefines(const LangOptions &Opts, 6441 MacroBuilder &Builder) const override; 6442 6443 bool isCLZForZeroUndef() const override { return false; } 6444 6445 bool hasFeature(StringRef Feature) const override { 6446 return llvm::StringSwitch<bool>(Feature) 6447 .Case("hexagon", true) 6448 .Case("hvx", HasHVX) 6449 .Case("hvx-double", HasHVXDouble) 6450 .Case("long-calls", UseLongCalls) 6451 .Default(false); 6452 } 6453 6454 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6455 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6456 const override; 6457 6458 bool handleTargetFeatures(std::vector<std::string> &Features, 6459 DiagnosticsEngine &Diags) override; 6460 6461 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6462 bool Enabled) const override; 6463 6464 BuiltinVaListKind getBuiltinVaListKind() const override { 6465 return TargetInfo::CharPtrBuiltinVaList; 6466 } 6467 ArrayRef<const char *> getGCCRegNames() const override; 6468 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6469 const char *getClobbers() const override { 6470 return ""; 6471 } 6472 6473 static const char *getHexagonCPUSuffix(StringRef Name) { 6474 return llvm::StringSwitch<const char*>(Name) 6475 .Case("hexagonv4", "4") 6476 .Case("hexagonv5", "5") 6477 .Case("hexagonv55", "55") 6478 .Case("hexagonv60", "60") 6479 .Case("hexagonv62", "62") 6480 .Default(nullptr); 6481 } 6482 6483 bool setCPU(const std::string &Name) override { 6484 if (!getHexagonCPUSuffix(Name)) 6485 return false; 6486 CPU = Name; 6487 return true; 6488 } 6489 6490 int getEHDataRegisterNumber(unsigned RegNo) const override { 6491 return RegNo < 2 ? RegNo : -1; 6492 } 6493 }; 6494 6495 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6496 MacroBuilder &Builder) const { 6497 Builder.defineMacro("__qdsp6__", "1"); 6498 Builder.defineMacro("__hexagon__", "1"); 6499 6500 if (CPU == "hexagonv4") { 6501 Builder.defineMacro("__HEXAGON_V4__"); 6502 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6503 if (Opts.HexagonQdsp6Compat) { 6504 Builder.defineMacro("__QDSP6_V4__"); 6505 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6506 } 6507 } else if (CPU == "hexagonv5") { 6508 Builder.defineMacro("__HEXAGON_V5__"); 6509 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6510 if(Opts.HexagonQdsp6Compat) { 6511 Builder.defineMacro("__QDSP6_V5__"); 6512 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6513 } 6514 } else if (CPU == "hexagonv55") { 6515 Builder.defineMacro("__HEXAGON_V55__"); 6516 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6517 Builder.defineMacro("__QDSP6_V55__"); 6518 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6519 } else if (CPU == "hexagonv60") { 6520 Builder.defineMacro("__HEXAGON_V60__"); 6521 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6522 Builder.defineMacro("__QDSP6_V60__"); 6523 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6524 } else if (CPU == "hexagonv62") { 6525 Builder.defineMacro("__HEXAGON_V62__"); 6526 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6527 } 6528 6529 if (hasFeature("hvx")) { 6530 Builder.defineMacro("__HVX__"); 6531 if (hasFeature("hvx-double")) 6532 Builder.defineMacro("__HVXDBL__"); 6533 } 6534 } 6535 6536 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6537 DiagnosticsEngine &Diags, StringRef CPU, 6538 const std::vector<std::string> &FeaturesVec) const { 6539 // Default for v60: -hvx, -hvx-double. 6540 Features["hvx"] = false; 6541 Features["hvx-double"] = false; 6542 Features["long-calls"] = false; 6543 6544 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6545 } 6546 6547 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6548 DiagnosticsEngine &Diags) { 6549 for (auto &F : Features) { 6550 if (F == "+hvx") 6551 HasHVX = true; 6552 else if (F == "-hvx") 6553 HasHVX = HasHVXDouble = false; 6554 else if (F == "+hvx-double") 6555 HasHVX = HasHVXDouble = true; 6556 else if (F == "-hvx-double") 6557 HasHVXDouble = false; 6558 6559 if (F == "+long-calls") 6560 UseLongCalls = true; 6561 else if (F == "-long-calls") 6562 UseLongCalls = false; 6563 } 6564 return true; 6565 } 6566 6567 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6568 StringRef Name, bool Enabled) const { 6569 if (Enabled) { 6570 if (Name == "hvx-double") 6571 Features["hvx"] = true; 6572 } else { 6573 if (Name == "hvx") 6574 Features["hvx-double"] = false; 6575 } 6576 Features[Name] = Enabled; 6577 } 6578 6579 const char *const HexagonTargetInfo::GCCRegNames[] = { 6580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6584 "p0", "p1", "p2", "p3", 6585 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6586 }; 6587 6588 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6589 return llvm::makeArrayRef(GCCRegNames); 6590 } 6591 6592 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6593 { { "sp" }, "r29" }, 6594 { { "fp" }, "r30" }, 6595 { { "lr" }, "r31" }, 6596 }; 6597 6598 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6599 return llvm::makeArrayRef(GCCRegAliases); 6600 } 6601 6602 6603 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6604 #define BUILTIN(ID, TYPE, ATTRS) \ 6605 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6606 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6607 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6608 #include "clang/Basic/BuiltinsHexagon.def" 6609 }; 6610 6611 class LanaiTargetInfo : public TargetInfo { 6612 // Class for Lanai (32-bit). 6613 // The CPU profiles supported by the Lanai backend 6614 enum CPUKind { 6615 CK_NONE, 6616 CK_V11, 6617 } CPU; 6618 6619 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6620 static const char *const GCCRegNames[]; 6621 6622 public: 6623 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6624 : TargetInfo(Triple) { 6625 // Description string has to be kept in sync with backend. 6626 resetDataLayout("E" // Big endian 6627 "-m:e" // ELF name manging 6628 "-p:32:32" // 32 bit pointers, 32 bit aligned 6629 "-i64:64" // 64 bit integers, 64 bit aligned 6630 "-a:0:32" // 32 bit alignment of objects of aggregate type 6631 "-n32" // 32 bit native integer width 6632 "-S64" // 64 bit natural stack alignment 6633 ); 6634 6635 // Setting RegParmMax equal to what mregparm was set to in the old 6636 // toolchain 6637 RegParmMax = 4; 6638 6639 // Set the default CPU to V11 6640 CPU = CK_V11; 6641 6642 // Temporary approach to make everything at least word-aligned and allow for 6643 // safely casting between pointers with different alignment requirements. 6644 // TODO: Remove this when there are no more cast align warnings on the 6645 // firmware. 6646 MinGlobalAlign = 32; 6647 } 6648 6649 void getTargetDefines(const LangOptions &Opts, 6650 MacroBuilder &Builder) const override { 6651 // Define __lanai__ when building for target lanai. 6652 Builder.defineMacro("__lanai__"); 6653 6654 // Set define for the CPU specified. 6655 switch (CPU) { 6656 case CK_V11: 6657 Builder.defineMacro("__LANAI_V11__"); 6658 break; 6659 case CK_NONE: 6660 llvm_unreachable("Unhandled target CPU"); 6661 } 6662 } 6663 6664 bool setCPU(const std::string &Name) override { 6665 CPU = llvm::StringSwitch<CPUKind>(Name) 6666 .Case("v11", CK_V11) 6667 .Default(CK_NONE); 6668 6669 return CPU != CK_NONE; 6670 } 6671 6672 bool hasFeature(StringRef Feature) const override { 6673 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6674 } 6675 6676 ArrayRef<const char *> getGCCRegNames() const override; 6677 6678 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6679 6680 BuiltinVaListKind getBuiltinVaListKind() const override { 6681 return TargetInfo::VoidPtrBuiltinVaList; 6682 } 6683 6684 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6685 6686 bool validateAsmConstraint(const char *&Name, 6687 TargetInfo::ConstraintInfo &info) const override { 6688 return false; 6689 } 6690 6691 const char *getClobbers() const override { return ""; } 6692 }; 6693 6694 const char *const LanaiTargetInfo::GCCRegNames[] = { 6695 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6696 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6697 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6698 6699 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6700 return llvm::makeArrayRef(GCCRegNames); 6701 } 6702 6703 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6704 {{"pc"}, "r2"}, 6705 {{"sp"}, "r4"}, 6706 {{"fp"}, "r5"}, 6707 {{"rv"}, "r8"}, 6708 {{"rr1"}, "r10"}, 6709 {{"rr2"}, "r11"}, 6710 {{"rca"}, "r15"}, 6711 }; 6712 6713 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6714 return llvm::makeArrayRef(GCCRegAliases); 6715 } 6716 6717 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6718 class SparcTargetInfo : public TargetInfo { 6719 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6720 static const char * const GCCRegNames[]; 6721 bool SoftFloat; 6722 public: 6723 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6724 : TargetInfo(Triple), SoftFloat(false) {} 6725 6726 int getEHDataRegisterNumber(unsigned RegNo) const override { 6727 if (RegNo == 0) return 24; 6728 if (RegNo == 1) return 25; 6729 return -1; 6730 } 6731 6732 bool handleTargetFeatures(std::vector<std::string> &Features, 6733 DiagnosticsEngine &Diags) override { 6734 // Check if software floating point is enabled 6735 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6736 if (Feature != Features.end()) { 6737 SoftFloat = true; 6738 } 6739 return true; 6740 } 6741 void getTargetDefines(const LangOptions &Opts, 6742 MacroBuilder &Builder) const override { 6743 DefineStd(Builder, "sparc", Opts); 6744 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6745 6746 if (SoftFloat) 6747 Builder.defineMacro("SOFT_FLOAT", "1"); 6748 } 6749 6750 bool hasFeature(StringRef Feature) const override { 6751 return llvm::StringSwitch<bool>(Feature) 6752 .Case("softfloat", SoftFloat) 6753 .Case("sparc", true) 6754 .Default(false); 6755 } 6756 6757 bool hasSjLjLowering() const override { 6758 return true; 6759 } 6760 6761 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6762 // FIXME: Implement! 6763 return None; 6764 } 6765 BuiltinVaListKind getBuiltinVaListKind() const override { 6766 return TargetInfo::VoidPtrBuiltinVaList; 6767 } 6768 ArrayRef<const char *> getGCCRegNames() const override; 6769 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6770 bool validateAsmConstraint(const char *&Name, 6771 TargetInfo::ConstraintInfo &info) const override { 6772 // FIXME: Implement! 6773 switch (*Name) { 6774 case 'I': // Signed 13-bit constant 6775 case 'J': // Zero 6776 case 'K': // 32-bit constant with the low 12 bits clear 6777 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6778 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6779 case 'N': // Same as 'K' but zext (required for SIMode) 6780 case 'O': // The constant 4096 6781 return true; 6782 } 6783 return false; 6784 } 6785 const char *getClobbers() const override { 6786 // FIXME: Implement! 6787 return ""; 6788 } 6789 6790 // No Sparc V7 for now, the backend doesn't support it anyway. 6791 enum CPUKind { 6792 CK_GENERIC, 6793 CK_V8, 6794 CK_SUPERSPARC, 6795 CK_SPARCLITE, 6796 CK_F934, 6797 CK_HYPERSPARC, 6798 CK_SPARCLITE86X, 6799 CK_SPARCLET, 6800 CK_TSC701, 6801 CK_V9, 6802 CK_ULTRASPARC, 6803 CK_ULTRASPARC3, 6804 CK_NIAGARA, 6805 CK_NIAGARA2, 6806 CK_NIAGARA3, 6807 CK_NIAGARA4, 6808 CK_MYRIAD2100, 6809 CK_MYRIAD2150, 6810 CK_MYRIAD2450, 6811 CK_LEON2, 6812 CK_LEON2_AT697E, 6813 CK_LEON2_AT697F, 6814 CK_LEON3, 6815 CK_LEON3_UT699, 6816 CK_LEON3_GR712RC, 6817 CK_LEON4, 6818 CK_LEON4_GR740 6819 } CPU = CK_GENERIC; 6820 6821 enum CPUGeneration { 6822 CG_V8, 6823 CG_V9, 6824 }; 6825 6826 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6827 switch (Kind) { 6828 case CK_GENERIC: 6829 case CK_V8: 6830 case CK_SUPERSPARC: 6831 case CK_SPARCLITE: 6832 case CK_F934: 6833 case CK_HYPERSPARC: 6834 case CK_SPARCLITE86X: 6835 case CK_SPARCLET: 6836 case CK_TSC701: 6837 case CK_MYRIAD2100: 6838 case CK_MYRIAD2150: 6839 case CK_MYRIAD2450: 6840 case CK_LEON2: 6841 case CK_LEON2_AT697E: 6842 case CK_LEON2_AT697F: 6843 case CK_LEON3: 6844 case CK_LEON3_UT699: 6845 case CK_LEON3_GR712RC: 6846 case CK_LEON4: 6847 case CK_LEON4_GR740: 6848 return CG_V8; 6849 case CK_V9: 6850 case CK_ULTRASPARC: 6851 case CK_ULTRASPARC3: 6852 case CK_NIAGARA: 6853 case CK_NIAGARA2: 6854 case CK_NIAGARA3: 6855 case CK_NIAGARA4: 6856 return CG_V9; 6857 } 6858 llvm_unreachable("Unexpected CPU kind"); 6859 } 6860 6861 CPUKind getCPUKind(StringRef Name) const { 6862 return llvm::StringSwitch<CPUKind>(Name) 6863 .Case("v8", CK_V8) 6864 .Case("supersparc", CK_SUPERSPARC) 6865 .Case("sparclite", CK_SPARCLITE) 6866 .Case("f934", CK_F934) 6867 .Case("hypersparc", CK_HYPERSPARC) 6868 .Case("sparclite86x", CK_SPARCLITE86X) 6869 .Case("sparclet", CK_SPARCLET) 6870 .Case("tsc701", CK_TSC701) 6871 .Case("v9", CK_V9) 6872 .Case("ultrasparc", CK_ULTRASPARC) 6873 .Case("ultrasparc3", CK_ULTRASPARC3) 6874 .Case("niagara", CK_NIAGARA) 6875 .Case("niagara2", CK_NIAGARA2) 6876 .Case("niagara3", CK_NIAGARA3) 6877 .Case("niagara4", CK_NIAGARA4) 6878 .Case("ma2100", CK_MYRIAD2100) 6879 .Case("ma2150", CK_MYRIAD2150) 6880 .Case("ma2450", CK_MYRIAD2450) 6881 // FIXME: the myriad2[.n] spellings are obsolete, 6882 // but a grace period is needed to allow updating dependent builds. 6883 .Case("myriad2", CK_MYRIAD2100) 6884 .Case("myriad2.1", CK_MYRIAD2100) 6885 .Case("myriad2.2", CK_MYRIAD2150) 6886 .Case("leon2", CK_LEON2) 6887 .Case("at697e", CK_LEON2_AT697E) 6888 .Case("at697f", CK_LEON2_AT697F) 6889 .Case("leon3", CK_LEON3) 6890 .Case("ut699", CK_LEON3_UT699) 6891 .Case("gr712rc", CK_LEON3_GR712RC) 6892 .Case("leon4", CK_LEON4) 6893 .Case("gr740", CK_LEON4_GR740) 6894 .Default(CK_GENERIC); 6895 } 6896 6897 bool setCPU(const std::string &Name) override { 6898 CPU = getCPUKind(Name); 6899 return CPU != CK_GENERIC; 6900 } 6901 }; 6902 6903 const char * const SparcTargetInfo::GCCRegNames[] = { 6904 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6905 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6906 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6907 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6908 }; 6909 6910 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6911 return llvm::makeArrayRef(GCCRegNames); 6912 } 6913 6914 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6915 { { "g0" }, "r0" }, 6916 { { "g1" }, "r1" }, 6917 { { "g2" }, "r2" }, 6918 { { "g3" }, "r3" }, 6919 { { "g4" }, "r4" }, 6920 { { "g5" }, "r5" }, 6921 { { "g6" }, "r6" }, 6922 { { "g7" }, "r7" }, 6923 { { "o0" }, "r8" }, 6924 { { "o1" }, "r9" }, 6925 { { "o2" }, "r10" }, 6926 { { "o3" }, "r11" }, 6927 { { "o4" }, "r12" }, 6928 { { "o5" }, "r13" }, 6929 { { "o6", "sp" }, "r14" }, 6930 { { "o7" }, "r15" }, 6931 { { "l0" }, "r16" }, 6932 { { "l1" }, "r17" }, 6933 { { "l2" }, "r18" }, 6934 { { "l3" }, "r19" }, 6935 { { "l4" }, "r20" }, 6936 { { "l5" }, "r21" }, 6937 { { "l6" }, "r22" }, 6938 { { "l7" }, "r23" }, 6939 { { "i0" }, "r24" }, 6940 { { "i1" }, "r25" }, 6941 { { "i2" }, "r26" }, 6942 { { "i3" }, "r27" }, 6943 { { "i4" }, "r28" }, 6944 { { "i5" }, "r29" }, 6945 { { "i6", "fp" }, "r30" }, 6946 { { "i7" }, "r31" }, 6947 }; 6948 6949 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6950 return llvm::makeArrayRef(GCCRegAliases); 6951 } 6952 6953 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6954 class SparcV8TargetInfo : public SparcTargetInfo { 6955 public: 6956 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6957 : SparcTargetInfo(Triple, Opts) { 6958 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6959 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6960 switch (getTriple().getOS()) { 6961 default: 6962 SizeType = UnsignedInt; 6963 IntPtrType = SignedInt; 6964 PtrDiffType = SignedInt; 6965 break; 6966 case llvm::Triple::NetBSD: 6967 case llvm::Triple::OpenBSD: 6968 SizeType = UnsignedLong; 6969 IntPtrType = SignedLong; 6970 PtrDiffType = SignedLong; 6971 break; 6972 } 6973 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 6974 // on up to 64 bits. 6975 MaxAtomicPromoteWidth = 64; 6976 MaxAtomicInlineWidth = 32; 6977 } 6978 6979 void getTargetDefines(const LangOptions &Opts, 6980 MacroBuilder &Builder) const override { 6981 SparcTargetInfo::getTargetDefines(Opts, Builder); 6982 switch (getCPUGeneration(CPU)) { 6983 case CG_V8: 6984 Builder.defineMacro("__sparcv8"); 6985 if (getTriple().getOS() != llvm::Triple::Solaris) 6986 Builder.defineMacro("__sparcv8__"); 6987 break; 6988 case CG_V9: 6989 Builder.defineMacro("__sparcv9"); 6990 if (getTriple().getOS() != llvm::Triple::Solaris) { 6991 Builder.defineMacro("__sparcv9__"); 6992 Builder.defineMacro("__sparc_v9__"); 6993 } 6994 break; 6995 } 6996 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6997 std::string MyriadArchValue, Myriad2Value; 6998 Builder.defineMacro("__sparc_v8__"); 6999 Builder.defineMacro("__leon__"); 7000 switch (CPU) { 7001 case CK_MYRIAD2150: 7002 MyriadArchValue = "__ma2150"; 7003 Myriad2Value = "2"; 7004 break; 7005 case CK_MYRIAD2450: 7006 MyriadArchValue = "__ma2450"; 7007 Myriad2Value = "2"; 7008 break; 7009 default: 7010 MyriadArchValue = "__ma2100"; 7011 Myriad2Value = "1"; 7012 break; 7013 } 7014 Builder.defineMacro(MyriadArchValue, "1"); 7015 Builder.defineMacro(MyriadArchValue+"__", "1"); 7016 Builder.defineMacro("__myriad2__", Myriad2Value); 7017 Builder.defineMacro("__myriad2", Myriad2Value); 7018 } 7019 } 7020 7021 bool hasSjLjLowering() const override { 7022 return true; 7023 } 7024 }; 7025 7026 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7027 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7028 public: 7029 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7030 : SparcV8TargetInfo(Triple, Opts) { 7031 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7032 } 7033 }; 7034 7035 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7036 class SparcV9TargetInfo : public SparcTargetInfo { 7037 public: 7038 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7039 : SparcTargetInfo(Triple, Opts) { 7040 // FIXME: Support Sparc quad-precision long double? 7041 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7042 // This is an LP64 platform. 7043 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7044 7045 // OpenBSD uses long long for int64_t and intmax_t. 7046 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7047 IntMaxType = SignedLongLong; 7048 else 7049 IntMaxType = SignedLong; 7050 Int64Type = IntMaxType; 7051 7052 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7053 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7054 LongDoubleWidth = 128; 7055 LongDoubleAlign = 128; 7056 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7057 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7058 } 7059 7060 void getTargetDefines(const LangOptions &Opts, 7061 MacroBuilder &Builder) const override { 7062 SparcTargetInfo::getTargetDefines(Opts, Builder); 7063 Builder.defineMacro("__sparcv9"); 7064 Builder.defineMacro("__arch64__"); 7065 // Solaris doesn't need these variants, but the BSDs do. 7066 if (getTriple().getOS() != llvm::Triple::Solaris) { 7067 Builder.defineMacro("__sparc64__"); 7068 Builder.defineMacro("__sparc_v9__"); 7069 Builder.defineMacro("__sparcv9__"); 7070 } 7071 } 7072 7073 bool setCPU(const std::string &Name) override { 7074 if (!SparcTargetInfo::setCPU(Name)) 7075 return false; 7076 return getCPUGeneration(CPU) == CG_V9; 7077 } 7078 }; 7079 7080 class SystemZTargetInfo : public TargetInfo { 7081 static const Builtin::Info BuiltinInfo[]; 7082 static const char *const GCCRegNames[]; 7083 std::string CPU; 7084 bool HasTransactionalExecution; 7085 bool HasVector; 7086 7087 public: 7088 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7089 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7090 HasVector(false) { 7091 IntMaxType = SignedLong; 7092 Int64Type = SignedLong; 7093 TLSSupported = true; 7094 IntWidth = IntAlign = 32; 7095 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7096 PointerWidth = PointerAlign = 64; 7097 LongDoubleWidth = 128; 7098 LongDoubleAlign = 64; 7099 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7100 DefaultAlignForAttributeAligned = 64; 7101 MinGlobalAlign = 16; 7102 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7103 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7104 } 7105 void getTargetDefines(const LangOptions &Opts, 7106 MacroBuilder &Builder) const override { 7107 Builder.defineMacro("__s390__"); 7108 Builder.defineMacro("__s390x__"); 7109 Builder.defineMacro("__zarch__"); 7110 Builder.defineMacro("__LONG_DOUBLE_128__"); 7111 7112 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7113 .Cases("arch8", "z10", "8") 7114 .Cases("arch9", "z196", "9") 7115 .Cases("arch10", "zEC12", "10") 7116 .Cases("arch11", "z13", "11") 7117 .Default(""); 7118 if (!ISARev.empty()) 7119 Builder.defineMacro("__ARCH__", ISARev); 7120 7121 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7122 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7123 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7124 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7125 7126 if (HasTransactionalExecution) 7127 Builder.defineMacro("__HTM__"); 7128 if (HasVector) 7129 Builder.defineMacro("__VX__"); 7130 if (Opts.ZVector) 7131 Builder.defineMacro("__VEC__", "10301"); 7132 } 7133 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7134 return llvm::makeArrayRef(BuiltinInfo, 7135 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7136 } 7137 7138 ArrayRef<const char *> getGCCRegNames() const override; 7139 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7140 // No aliases. 7141 return None; 7142 } 7143 bool validateAsmConstraint(const char *&Name, 7144 TargetInfo::ConstraintInfo &info) const override; 7145 const char *getClobbers() const override { 7146 // FIXME: Is this really right? 7147 return ""; 7148 } 7149 BuiltinVaListKind getBuiltinVaListKind() const override { 7150 return TargetInfo::SystemZBuiltinVaList; 7151 } 7152 bool setCPU(const std::string &Name) override { 7153 CPU = Name; 7154 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7155 .Case("z10", true) 7156 .Case("arch8", true) 7157 .Case("z196", true) 7158 .Case("arch9", true) 7159 .Case("zEC12", true) 7160 .Case("arch10", true) 7161 .Case("z13", true) 7162 .Case("arch11", true) 7163 .Default(false); 7164 7165 return CPUKnown; 7166 } 7167 bool 7168 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7169 StringRef CPU, 7170 const std::vector<std::string> &FeaturesVec) const override { 7171 if (CPU == "zEC12" || CPU == "arch10") 7172 Features["transactional-execution"] = true; 7173 if (CPU == "z13" || CPU == "arch11") { 7174 Features["transactional-execution"] = true; 7175 Features["vector"] = true; 7176 } 7177 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7178 } 7179 7180 bool handleTargetFeatures(std::vector<std::string> &Features, 7181 DiagnosticsEngine &Diags) override { 7182 HasTransactionalExecution = false; 7183 for (const auto &Feature : Features) { 7184 if (Feature == "+transactional-execution") 7185 HasTransactionalExecution = true; 7186 else if (Feature == "+vector") 7187 HasVector = true; 7188 } 7189 // If we use the vector ABI, vector types are 64-bit aligned. 7190 if (HasVector) { 7191 MaxVectorAlign = 64; 7192 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7193 "-v128:64-a:8:16-n32:64"); 7194 } 7195 return true; 7196 } 7197 7198 bool hasFeature(StringRef Feature) const override { 7199 return llvm::StringSwitch<bool>(Feature) 7200 .Case("systemz", true) 7201 .Case("htm", HasTransactionalExecution) 7202 .Case("vx", HasVector) 7203 .Default(false); 7204 } 7205 7206 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7207 switch (CC) { 7208 case CC_C: 7209 case CC_Swift: 7210 return CCCR_OK; 7211 default: 7212 return CCCR_Warning; 7213 } 7214 } 7215 7216 StringRef getABI() const override { 7217 if (HasVector) 7218 return "vector"; 7219 return ""; 7220 } 7221 7222 bool useFloat128ManglingForLongDouble() const override { 7223 return true; 7224 } 7225 }; 7226 7227 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7228 #define BUILTIN(ID, TYPE, ATTRS) \ 7229 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7230 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7231 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7232 #include "clang/Basic/BuiltinsSystemZ.def" 7233 }; 7234 7235 const char *const SystemZTargetInfo::GCCRegNames[] = { 7236 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7237 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7238 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7239 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7240 }; 7241 7242 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7243 return llvm::makeArrayRef(GCCRegNames); 7244 } 7245 7246 bool SystemZTargetInfo:: 7247 validateAsmConstraint(const char *&Name, 7248 TargetInfo::ConstraintInfo &Info) const { 7249 switch (*Name) { 7250 default: 7251 return false; 7252 7253 case 'a': // Address register 7254 case 'd': // Data register (equivalent to 'r') 7255 case 'f': // Floating-point register 7256 Info.setAllowsRegister(); 7257 return true; 7258 7259 case 'I': // Unsigned 8-bit constant 7260 case 'J': // Unsigned 12-bit constant 7261 case 'K': // Signed 16-bit constant 7262 case 'L': // Signed 20-bit displacement (on all targets we support) 7263 case 'M': // 0x7fffffff 7264 return true; 7265 7266 case 'Q': // Memory with base and unsigned 12-bit displacement 7267 case 'R': // Likewise, plus an index 7268 case 'S': // Memory with base and signed 20-bit displacement 7269 case 'T': // Likewise, plus an index 7270 Info.setAllowsMemory(); 7271 return true; 7272 } 7273 } 7274 7275 class MSP430TargetInfo : public TargetInfo { 7276 static const char *const GCCRegNames[]; 7277 7278 public: 7279 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7280 : TargetInfo(Triple) { 7281 TLSSupported = false; 7282 IntWidth = 16; 7283 IntAlign = 16; 7284 LongWidth = 32; 7285 LongLongWidth = 64; 7286 LongAlign = LongLongAlign = 16; 7287 PointerWidth = 16; 7288 PointerAlign = 16; 7289 SuitableAlign = 16; 7290 SizeType = UnsignedInt; 7291 IntMaxType = SignedLongLong; 7292 IntPtrType = SignedInt; 7293 PtrDiffType = SignedInt; 7294 SigAtomicType = SignedLong; 7295 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7296 } 7297 void getTargetDefines(const LangOptions &Opts, 7298 MacroBuilder &Builder) const override { 7299 Builder.defineMacro("MSP430"); 7300 Builder.defineMacro("__MSP430__"); 7301 // FIXME: defines for different 'flavours' of MCU 7302 } 7303 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7304 // FIXME: Implement. 7305 return None; 7306 } 7307 bool hasFeature(StringRef Feature) const override { 7308 return Feature == "msp430"; 7309 } 7310 ArrayRef<const char *> getGCCRegNames() const override; 7311 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7312 // No aliases. 7313 return None; 7314 } 7315 bool validateAsmConstraint(const char *&Name, 7316 TargetInfo::ConstraintInfo &info) const override { 7317 // FIXME: implement 7318 switch (*Name) { 7319 case 'K': // the constant 1 7320 case 'L': // constant -1^20 .. 1^19 7321 case 'M': // constant 1-4: 7322 return true; 7323 } 7324 // No target constraints for now. 7325 return false; 7326 } 7327 const char *getClobbers() const override { 7328 // FIXME: Is this really right? 7329 return ""; 7330 } 7331 BuiltinVaListKind getBuiltinVaListKind() const override { 7332 // FIXME: implement 7333 return TargetInfo::CharPtrBuiltinVaList; 7334 } 7335 }; 7336 7337 const char *const MSP430TargetInfo::GCCRegNames[] = { 7338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7340 7341 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7342 return llvm::makeArrayRef(GCCRegNames); 7343 } 7344 7345 // LLVM and Clang cannot be used directly to output native binaries for 7346 // target, but is used to compile C code to llvm bitcode with correct 7347 // type and alignment information. 7348 // 7349 // TCE uses the llvm bitcode as input and uses it for generating customized 7350 // target processor and program binary. TCE co-design environment is 7351 // publicly available in http://tce.cs.tut.fi 7352 7353 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7354 3, // opencl_global 7355 4, // opencl_local 7356 5, // opencl_constant 7357 // FIXME: generic has to be added to the target 7358 0, // opencl_generic 7359 0, // cuda_device 7360 0, // cuda_constant 7361 0 // cuda_shared 7362 }; 7363 7364 class TCETargetInfo : public TargetInfo { 7365 public: 7366 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7367 : TargetInfo(Triple) { 7368 TLSSupported = false; 7369 IntWidth = 32; 7370 LongWidth = LongLongWidth = 32; 7371 PointerWidth = 32; 7372 IntAlign = 32; 7373 LongAlign = LongLongAlign = 32; 7374 PointerAlign = 32; 7375 SuitableAlign = 32; 7376 SizeType = UnsignedInt; 7377 IntMaxType = SignedLong; 7378 IntPtrType = SignedInt; 7379 PtrDiffType = SignedInt; 7380 FloatWidth = 32; 7381 FloatAlign = 32; 7382 DoubleWidth = 32; 7383 DoubleAlign = 32; 7384 LongDoubleWidth = 32; 7385 LongDoubleAlign = 32; 7386 FloatFormat = &llvm::APFloat::IEEEsingle(); 7387 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7388 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7389 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7390 "i16:16:32-i32:32:32-i64:32:32-" 7391 "f32:32:32-f64:32:32-v64:32:32-" 7392 "v128:32:32-v256:32:32-v512:32:32-" 7393 "v1024:32:32-a0:0:32-n32"); 7394 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7395 UseAddrSpaceMapMangling = true; 7396 } 7397 7398 void getTargetDefines(const LangOptions &Opts, 7399 MacroBuilder &Builder) const override { 7400 DefineStd(Builder, "tce", Opts); 7401 Builder.defineMacro("__TCE__"); 7402 Builder.defineMacro("__TCE_V1__"); 7403 } 7404 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7405 7406 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7407 const char *getClobbers() const override { return ""; } 7408 BuiltinVaListKind getBuiltinVaListKind() const override { 7409 return TargetInfo::VoidPtrBuiltinVaList; 7410 } 7411 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7412 bool validateAsmConstraint(const char *&Name, 7413 TargetInfo::ConstraintInfo &info) const override { 7414 return true; 7415 } 7416 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7417 return None; 7418 } 7419 }; 7420 7421 class TCELETargetInfo : public TCETargetInfo { 7422 public: 7423 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7424 : TCETargetInfo(Triple, Opts) { 7425 BigEndian = false; 7426 7427 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7428 "i16:16:32-i32:32:32-i64:32:32-" 7429 "f32:32:32-f64:32:32-v64:32:32-" 7430 "v128:32:32-v256:32:32-v512:32:32-" 7431 "v1024:32:32-a0:0:32-n32"); 7432 7433 } 7434 7435 virtual void getTargetDefines(const LangOptions &Opts, 7436 MacroBuilder &Builder) const { 7437 DefineStd(Builder, "tcele", Opts); 7438 Builder.defineMacro("__TCE__"); 7439 Builder.defineMacro("__TCE_V1__"); 7440 Builder.defineMacro("__TCELE__"); 7441 Builder.defineMacro("__TCELE_V1__"); 7442 } 7443 7444 }; 7445 7446 class BPFTargetInfo : public TargetInfo { 7447 public: 7448 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7449 : TargetInfo(Triple) { 7450 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7451 SizeType = UnsignedLong; 7452 PtrDiffType = SignedLong; 7453 IntPtrType = SignedLong; 7454 IntMaxType = SignedLong; 7455 Int64Type = SignedLong; 7456 RegParmMax = 5; 7457 if (Triple.getArch() == llvm::Triple::bpfeb) { 7458 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7459 } else { 7460 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7461 } 7462 MaxAtomicPromoteWidth = 64; 7463 MaxAtomicInlineWidth = 64; 7464 TLSSupported = false; 7465 } 7466 void getTargetDefines(const LangOptions &Opts, 7467 MacroBuilder &Builder) const override { 7468 DefineStd(Builder, "bpf", Opts); 7469 Builder.defineMacro("__BPF__"); 7470 } 7471 bool hasFeature(StringRef Feature) const override { 7472 return Feature == "bpf"; 7473 } 7474 7475 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7476 const char *getClobbers() const override { 7477 return ""; 7478 } 7479 BuiltinVaListKind getBuiltinVaListKind() const override { 7480 return TargetInfo::VoidPtrBuiltinVaList; 7481 } 7482 ArrayRef<const char *> getGCCRegNames() const override { 7483 return None; 7484 } 7485 bool validateAsmConstraint(const char *&Name, 7486 TargetInfo::ConstraintInfo &info) const override { 7487 return true; 7488 } 7489 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7490 return None; 7491 } 7492 }; 7493 7494 class MipsTargetInfo : public TargetInfo { 7495 void setDataLayout() { 7496 StringRef Layout; 7497 7498 if (ABI == "o32") 7499 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7500 else if (ABI == "n32") 7501 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7502 else if (ABI == "n64") 7503 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7504 else 7505 llvm_unreachable("Invalid ABI"); 7506 7507 if (BigEndian) 7508 resetDataLayout(("E-" + Layout).str()); 7509 else 7510 resetDataLayout(("e-" + Layout).str()); 7511 } 7512 7513 7514 static const Builtin::Info BuiltinInfo[]; 7515 std::string CPU; 7516 bool IsMips16; 7517 bool IsMicromips; 7518 bool IsNan2008; 7519 bool IsSingleFloat; 7520 bool IsNoABICalls; 7521 bool CanUseBSDABICalls; 7522 enum MipsFloatABI { 7523 HardFloat, SoftFloat 7524 } FloatABI; 7525 enum DspRevEnum { 7526 NoDSP, DSP1, DSP2 7527 } DspRev; 7528 bool HasMSA; 7529 7530 protected: 7531 bool HasFP64; 7532 std::string ABI; 7533 7534 public: 7535 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7536 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7537 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7538 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7539 HasMSA(false), HasFP64(false) { 7540 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7541 7542 setABI((getTriple().getArch() == llvm::Triple::mips || 7543 getTriple().getArch() == llvm::Triple::mipsel) 7544 ? "o32" 7545 : "n64"); 7546 7547 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7548 7549 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7550 Triple.getOS() == llvm::Triple::OpenBSD; 7551 } 7552 7553 bool isNaN2008Default() const { 7554 return CPU == "mips32r6" || CPU == "mips64r6"; 7555 } 7556 7557 bool isFP64Default() const { 7558 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7559 } 7560 7561 bool isNan2008() const override { 7562 return IsNan2008; 7563 } 7564 7565 bool processorSupportsGPR64() const { 7566 return llvm::StringSwitch<bool>(CPU) 7567 .Case("mips3", true) 7568 .Case("mips4", true) 7569 .Case("mips5", true) 7570 .Case("mips64", true) 7571 .Case("mips64r2", true) 7572 .Case("mips64r3", true) 7573 .Case("mips64r5", true) 7574 .Case("mips64r6", true) 7575 .Case("octeon", true) 7576 .Default(false); 7577 return false; 7578 } 7579 7580 StringRef getABI() const override { return ABI; } 7581 bool setABI(const std::string &Name) override { 7582 if (Name == "o32") { 7583 setO32ABITypes(); 7584 ABI = Name; 7585 return true; 7586 } 7587 7588 if (Name == "n32") { 7589 setN32ABITypes(); 7590 ABI = Name; 7591 return true; 7592 } 7593 if (Name == "n64") { 7594 setN64ABITypes(); 7595 ABI = Name; 7596 return true; 7597 } 7598 return false; 7599 } 7600 7601 void setO32ABITypes() { 7602 Int64Type = SignedLongLong; 7603 IntMaxType = Int64Type; 7604 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7605 LongDoubleWidth = LongDoubleAlign = 64; 7606 LongWidth = LongAlign = 32; 7607 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7608 PointerWidth = PointerAlign = 32; 7609 PtrDiffType = SignedInt; 7610 SizeType = UnsignedInt; 7611 SuitableAlign = 64; 7612 } 7613 7614 void setN32N64ABITypes() { 7615 LongDoubleWidth = LongDoubleAlign = 128; 7616 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7617 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7618 LongDoubleWidth = LongDoubleAlign = 64; 7619 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7620 } 7621 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7622 SuitableAlign = 128; 7623 } 7624 7625 void setN64ABITypes() { 7626 setN32N64ABITypes(); 7627 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7628 Int64Type = SignedLongLong; 7629 } else { 7630 Int64Type = SignedLong; 7631 } 7632 IntMaxType = Int64Type; 7633 LongWidth = LongAlign = 64; 7634 PointerWidth = PointerAlign = 64; 7635 PtrDiffType = SignedLong; 7636 SizeType = UnsignedLong; 7637 } 7638 7639 void setN32ABITypes() { 7640 setN32N64ABITypes(); 7641 Int64Type = SignedLongLong; 7642 IntMaxType = Int64Type; 7643 LongWidth = LongAlign = 32; 7644 PointerWidth = PointerAlign = 32; 7645 PtrDiffType = SignedInt; 7646 SizeType = UnsignedInt; 7647 } 7648 7649 bool setCPU(const std::string &Name) override { 7650 CPU = Name; 7651 return llvm::StringSwitch<bool>(Name) 7652 .Case("mips1", true) 7653 .Case("mips2", true) 7654 .Case("mips3", true) 7655 .Case("mips4", true) 7656 .Case("mips5", true) 7657 .Case("mips32", true) 7658 .Case("mips32r2", true) 7659 .Case("mips32r3", true) 7660 .Case("mips32r5", true) 7661 .Case("mips32r6", true) 7662 .Case("mips64", true) 7663 .Case("mips64r2", true) 7664 .Case("mips64r3", true) 7665 .Case("mips64r5", true) 7666 .Case("mips64r6", true) 7667 .Case("octeon", true) 7668 .Case("p5600", true) 7669 .Default(false); 7670 } 7671 const std::string& getCPU() const { return CPU; } 7672 bool 7673 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7674 StringRef CPU, 7675 const std::vector<std::string> &FeaturesVec) const override { 7676 if (CPU.empty()) 7677 CPU = getCPU(); 7678 if (CPU == "octeon") 7679 Features["mips64r2"] = Features["cnmips"] = true; 7680 else 7681 Features[CPU] = true; 7682 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7683 } 7684 7685 void getTargetDefines(const LangOptions &Opts, 7686 MacroBuilder &Builder) const override { 7687 if (BigEndian) { 7688 DefineStd(Builder, "MIPSEB", Opts); 7689 Builder.defineMacro("_MIPSEB"); 7690 } else { 7691 DefineStd(Builder, "MIPSEL", Opts); 7692 Builder.defineMacro("_MIPSEL"); 7693 } 7694 7695 Builder.defineMacro("__mips__"); 7696 Builder.defineMacro("_mips"); 7697 if (Opts.GNUMode) 7698 Builder.defineMacro("mips"); 7699 7700 if (ABI == "o32") { 7701 Builder.defineMacro("__mips", "32"); 7702 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7703 } else { 7704 Builder.defineMacro("__mips", "64"); 7705 Builder.defineMacro("__mips64"); 7706 Builder.defineMacro("__mips64__"); 7707 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7708 } 7709 7710 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7711 .Cases("mips32", "mips64", "1") 7712 .Cases("mips32r2", "mips64r2", "2") 7713 .Cases("mips32r3", "mips64r3", "3") 7714 .Cases("mips32r5", "mips64r5", "5") 7715 .Cases("mips32r6", "mips64r6", "6") 7716 .Default(""); 7717 if (!ISARev.empty()) 7718 Builder.defineMacro("__mips_isa_rev", ISARev); 7719 7720 if (ABI == "o32") { 7721 Builder.defineMacro("__mips_o32"); 7722 Builder.defineMacro("_ABIO32", "1"); 7723 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7724 } else if (ABI == "n32") { 7725 Builder.defineMacro("__mips_n32"); 7726 Builder.defineMacro("_ABIN32", "2"); 7727 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7728 } else if (ABI == "n64") { 7729 Builder.defineMacro("__mips_n64"); 7730 Builder.defineMacro("_ABI64", "3"); 7731 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7732 } else 7733 llvm_unreachable("Invalid ABI."); 7734 7735 if (!IsNoABICalls) { 7736 Builder.defineMacro("__mips_abicalls"); 7737 if (CanUseBSDABICalls) 7738 Builder.defineMacro("__ABICALLS__"); 7739 } 7740 7741 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7742 7743 switch (FloatABI) { 7744 case HardFloat: 7745 Builder.defineMacro("__mips_hard_float", Twine(1)); 7746 break; 7747 case SoftFloat: 7748 Builder.defineMacro("__mips_soft_float", Twine(1)); 7749 break; 7750 } 7751 7752 if (IsSingleFloat) 7753 Builder.defineMacro("__mips_single_float", Twine(1)); 7754 7755 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7756 Builder.defineMacro("_MIPS_FPSET", 7757 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7758 7759 if (IsMips16) 7760 Builder.defineMacro("__mips16", Twine(1)); 7761 7762 if (IsMicromips) 7763 Builder.defineMacro("__mips_micromips", Twine(1)); 7764 7765 if (IsNan2008) 7766 Builder.defineMacro("__mips_nan2008", Twine(1)); 7767 7768 switch (DspRev) { 7769 default: 7770 break; 7771 case DSP1: 7772 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7773 Builder.defineMacro("__mips_dsp", Twine(1)); 7774 break; 7775 case DSP2: 7776 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7777 Builder.defineMacro("__mips_dspr2", Twine(1)); 7778 Builder.defineMacro("__mips_dsp", Twine(1)); 7779 break; 7780 } 7781 7782 if (HasMSA) 7783 Builder.defineMacro("__mips_msa", Twine(1)); 7784 7785 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7786 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7787 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7788 7789 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7790 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7791 7792 // These shouldn't be defined for MIPS-I but there's no need to check 7793 // for that since MIPS-I isn't supported. 7794 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7795 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7796 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7797 7798 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7799 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7800 // the instructions exist but using them violates the ABI since they 7801 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7802 if (ABI == "n32" || ABI == "n64") 7803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7804 } 7805 7806 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7807 return llvm::makeArrayRef(BuiltinInfo, 7808 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7809 } 7810 bool hasFeature(StringRef Feature) const override { 7811 return llvm::StringSwitch<bool>(Feature) 7812 .Case("mips", true) 7813 .Case("fp64", HasFP64) 7814 .Default(false); 7815 } 7816 BuiltinVaListKind getBuiltinVaListKind() const override { 7817 return TargetInfo::VoidPtrBuiltinVaList; 7818 } 7819 ArrayRef<const char *> getGCCRegNames() const override { 7820 static const char *const GCCRegNames[] = { 7821 // CPU register names 7822 // Must match second column of GCCRegAliases 7823 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7824 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7825 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7826 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7827 // Floating point register names 7828 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7829 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7830 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7831 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7832 // Hi/lo and condition register names 7833 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7834 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7835 "$ac3hi","$ac3lo", 7836 // MSA register names 7837 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7838 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7839 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7840 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7841 // MSA control register names 7842 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7843 "$msarequest", "$msamap", "$msaunmap" 7844 }; 7845 return llvm::makeArrayRef(GCCRegNames); 7846 } 7847 bool validateAsmConstraint(const char *&Name, 7848 TargetInfo::ConstraintInfo &Info) const override { 7849 switch (*Name) { 7850 default: 7851 return false; 7852 case 'r': // CPU registers. 7853 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7854 case 'y': // Equivalent to "r", backward compatibility only. 7855 case 'f': // floating-point registers. 7856 case 'c': // $25 for indirect jumps 7857 case 'l': // lo register 7858 case 'x': // hilo register pair 7859 Info.setAllowsRegister(); 7860 return true; 7861 case 'I': // Signed 16-bit constant 7862 case 'J': // Integer 0 7863 case 'K': // Unsigned 16-bit constant 7864 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7865 case 'M': // Constants not loadable via lui, addiu, or ori 7866 case 'N': // Constant -1 to -65535 7867 case 'O': // A signed 15-bit constant 7868 case 'P': // A constant between 1 go 65535 7869 return true; 7870 case 'R': // An address that can be used in a non-macro load or store 7871 Info.setAllowsMemory(); 7872 return true; 7873 case 'Z': 7874 if (Name[1] == 'C') { // An address usable by ll, and sc. 7875 Info.setAllowsMemory(); 7876 Name++; // Skip over 'Z'. 7877 return true; 7878 } 7879 return false; 7880 } 7881 } 7882 7883 std::string convertConstraint(const char *&Constraint) const override { 7884 std::string R; 7885 switch (*Constraint) { 7886 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7887 if (Constraint[1] == 'C') { 7888 R = std::string("^") + std::string(Constraint, 2); 7889 Constraint++; 7890 return R; 7891 } 7892 break; 7893 } 7894 return TargetInfo::convertConstraint(Constraint); 7895 } 7896 7897 const char *getClobbers() const override { 7898 // In GCC, $1 is not widely used in generated code (it's used only in a few 7899 // specific situations), so there is no real need for users to add it to 7900 // the clobbers list if they want to use it in their inline assembly code. 7901 // 7902 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7903 // code generation, so using it in inline assembly without adding it to the 7904 // clobbers list can cause conflicts between the inline assembly code and 7905 // the surrounding generated code. 7906 // 7907 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7908 // operands, which will conflict with the ".set at" assembler option (which 7909 // we use only for inline assembly, in order to maintain compatibility with 7910 // GCC) and will also conflict with the user's usage of $1. 7911 // 7912 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7913 // register for generated code is to automatically clobber $1 for all inline 7914 // assembly code. 7915 // 7916 // FIXME: We should automatically clobber $1 only for inline assembly code 7917 // which actually uses it. This would allow LLVM to use $1 for inline 7918 // assembly operands if the user's assembly code doesn't use it. 7919 return "~{$1}"; 7920 } 7921 7922 bool handleTargetFeatures(std::vector<std::string> &Features, 7923 DiagnosticsEngine &Diags) override { 7924 IsMips16 = false; 7925 IsMicromips = false; 7926 IsNan2008 = isNaN2008Default(); 7927 IsSingleFloat = false; 7928 FloatABI = HardFloat; 7929 DspRev = NoDSP; 7930 HasFP64 = isFP64Default(); 7931 7932 for (const auto &Feature : Features) { 7933 if (Feature == "+single-float") 7934 IsSingleFloat = true; 7935 else if (Feature == "+soft-float") 7936 FloatABI = SoftFloat; 7937 else if (Feature == "+mips16") 7938 IsMips16 = true; 7939 else if (Feature == "+micromips") 7940 IsMicromips = true; 7941 else if (Feature == "+dsp") 7942 DspRev = std::max(DspRev, DSP1); 7943 else if (Feature == "+dspr2") 7944 DspRev = std::max(DspRev, DSP2); 7945 else if (Feature == "+msa") 7946 HasMSA = true; 7947 else if (Feature == "+fp64") 7948 HasFP64 = true; 7949 else if (Feature == "-fp64") 7950 HasFP64 = false; 7951 else if (Feature == "+nan2008") 7952 IsNan2008 = true; 7953 else if (Feature == "-nan2008") 7954 IsNan2008 = false; 7955 else if (Feature == "+noabicalls") 7956 IsNoABICalls = true; 7957 } 7958 7959 setDataLayout(); 7960 7961 return true; 7962 } 7963 7964 int getEHDataRegisterNumber(unsigned RegNo) const override { 7965 if (RegNo == 0) return 4; 7966 if (RegNo == 1) return 5; 7967 return -1; 7968 } 7969 7970 bool isCLZForZeroUndef() const override { return false; } 7971 7972 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7973 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7974 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7975 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7976 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7977 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7978 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7979 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7980 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7981 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7982 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7983 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7984 {{"ra"}, "$31"}}; 7985 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7986 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7987 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7988 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7989 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7990 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7991 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7992 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7993 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7994 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7995 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7996 {{"ra"}, "$31"}}; 7997 if (ABI == "o32") 7998 return llvm::makeArrayRef(O32RegAliases); 7999 return llvm::makeArrayRef(NewABIRegAliases); 8000 } 8001 8002 bool hasInt128Type() const override { 8003 return ABI == "n32" || ABI == "n64"; 8004 } 8005 8006 bool validateTarget(DiagnosticsEngine &Diags) const override { 8007 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8008 // this yet. It's better to fail here than on the backend assertion. 8009 if (processorSupportsGPR64() && ABI == "o32") { 8010 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8011 return false; 8012 } 8013 8014 // 64-bit ABI's require 64-bit CPU's. 8015 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8016 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8017 return false; 8018 } 8019 8020 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8021 // can't handle this yet. It's better to fail here than on the 8022 // backend assertion. 8023 if ((getTriple().getArch() == llvm::Triple::mips64 || 8024 getTriple().getArch() == llvm::Triple::mips64el) && 8025 ABI == "o32") { 8026 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8027 << ABI << getTriple().str(); 8028 return false; 8029 } 8030 8031 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8032 // can't handle this yet. It's better to fail here than on the 8033 // backend assertion. 8034 if ((getTriple().getArch() == llvm::Triple::mips || 8035 getTriple().getArch() == llvm::Triple::mipsel) && 8036 (ABI == "n32" || ABI == "n64")) { 8037 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8038 << ABI << getTriple().str(); 8039 return false; 8040 } 8041 8042 return true; 8043 } 8044 }; 8045 8046 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8047 #define BUILTIN(ID, TYPE, ATTRS) \ 8048 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8049 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8050 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8051 #include "clang/Basic/BuiltinsMips.def" 8052 }; 8053 8054 class PNaClTargetInfo : public TargetInfo { 8055 public: 8056 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8057 : TargetInfo(Triple) { 8058 this->LongAlign = 32; 8059 this->LongWidth = 32; 8060 this->PointerAlign = 32; 8061 this->PointerWidth = 32; 8062 this->IntMaxType = TargetInfo::SignedLongLong; 8063 this->Int64Type = TargetInfo::SignedLongLong; 8064 this->DoubleAlign = 64; 8065 this->LongDoubleWidth = 64; 8066 this->LongDoubleAlign = 64; 8067 this->SizeType = TargetInfo::UnsignedInt; 8068 this->PtrDiffType = TargetInfo::SignedInt; 8069 this->IntPtrType = TargetInfo::SignedInt; 8070 this->RegParmMax = 0; // Disallow regparm 8071 } 8072 8073 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8074 Builder.defineMacro("__le32__"); 8075 Builder.defineMacro("__pnacl__"); 8076 } 8077 void getTargetDefines(const LangOptions &Opts, 8078 MacroBuilder &Builder) const override { 8079 getArchDefines(Opts, Builder); 8080 } 8081 bool hasFeature(StringRef Feature) const override { 8082 return Feature == "pnacl"; 8083 } 8084 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8085 BuiltinVaListKind getBuiltinVaListKind() const override { 8086 return TargetInfo::PNaClABIBuiltinVaList; 8087 } 8088 ArrayRef<const char *> getGCCRegNames() const override; 8089 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8090 bool validateAsmConstraint(const char *&Name, 8091 TargetInfo::ConstraintInfo &Info) const override { 8092 return false; 8093 } 8094 8095 const char *getClobbers() const override { 8096 return ""; 8097 } 8098 }; 8099 8100 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8101 return None; 8102 } 8103 8104 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8105 return None; 8106 } 8107 8108 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8109 class NaClMips32TargetInfo : public MipsTargetInfo { 8110 public: 8111 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8112 : MipsTargetInfo(Triple, Opts) {} 8113 8114 BuiltinVaListKind getBuiltinVaListKind() const override { 8115 return TargetInfo::PNaClABIBuiltinVaList; 8116 } 8117 }; 8118 8119 class Le64TargetInfo : public TargetInfo { 8120 static const Builtin::Info BuiltinInfo[]; 8121 8122 public: 8123 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8124 : TargetInfo(Triple) { 8125 NoAsmVariants = true; 8126 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8127 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8128 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8129 } 8130 8131 void getTargetDefines(const LangOptions &Opts, 8132 MacroBuilder &Builder) const override { 8133 DefineStd(Builder, "unix", Opts); 8134 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8135 Builder.defineMacro("__ELF__"); 8136 } 8137 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8138 return llvm::makeArrayRef(BuiltinInfo, 8139 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8140 } 8141 BuiltinVaListKind getBuiltinVaListKind() const override { 8142 return TargetInfo::PNaClABIBuiltinVaList; 8143 } 8144 const char *getClobbers() const override { return ""; } 8145 ArrayRef<const char *> getGCCRegNames() const override { 8146 return None; 8147 } 8148 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8149 return None; 8150 } 8151 bool validateAsmConstraint(const char *&Name, 8152 TargetInfo::ConstraintInfo &Info) const override { 8153 return false; 8154 } 8155 8156 bool hasProtectedVisibility() const override { return false; } 8157 }; 8158 8159 class WebAssemblyTargetInfo : public TargetInfo { 8160 static const Builtin::Info BuiltinInfo[]; 8161 8162 enum SIMDEnum { 8163 NoSIMD, 8164 SIMD128, 8165 } SIMDLevel; 8166 8167 public: 8168 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8169 : TargetInfo(T), SIMDLevel(NoSIMD) { 8170 NoAsmVariants = true; 8171 SuitableAlign = 128; 8172 LargeArrayMinWidth = 128; 8173 LargeArrayAlign = 128; 8174 SimdDefaultAlign = 128; 8175 SigAtomicType = SignedLong; 8176 LongDoubleWidth = LongDoubleAlign = 128; 8177 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8178 SizeType = UnsignedInt; 8179 PtrDiffType = SignedInt; 8180 IntPtrType = SignedInt; 8181 } 8182 8183 protected: 8184 void getTargetDefines(const LangOptions &Opts, 8185 MacroBuilder &Builder) const override { 8186 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8187 if (SIMDLevel >= SIMD128) 8188 Builder.defineMacro("__wasm_simd128__"); 8189 } 8190 8191 private: 8192 bool 8193 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8194 StringRef CPU, 8195 const std::vector<std::string> &FeaturesVec) const override { 8196 if (CPU == "bleeding-edge") 8197 Features["simd128"] = true; 8198 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8199 } 8200 bool hasFeature(StringRef Feature) const final { 8201 return llvm::StringSwitch<bool>(Feature) 8202 .Case("simd128", SIMDLevel >= SIMD128) 8203 .Default(false); 8204 } 8205 bool handleTargetFeatures(std::vector<std::string> &Features, 8206 DiagnosticsEngine &Diags) final { 8207 for (const auto &Feature : Features) { 8208 if (Feature == "+simd128") { 8209 SIMDLevel = std::max(SIMDLevel, SIMD128); 8210 continue; 8211 } 8212 if (Feature == "-simd128") { 8213 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8214 continue; 8215 } 8216 8217 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8218 << "-target-feature"; 8219 return false; 8220 } 8221 return true; 8222 } 8223 bool setCPU(const std::string &Name) final { 8224 return llvm::StringSwitch<bool>(Name) 8225 .Case("mvp", true) 8226 .Case("bleeding-edge", true) 8227 .Case("generic", true) 8228 .Default(false); 8229 } 8230 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8231 return llvm::makeArrayRef(BuiltinInfo, 8232 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8233 } 8234 BuiltinVaListKind getBuiltinVaListKind() const final { 8235 return VoidPtrBuiltinVaList; 8236 } 8237 ArrayRef<const char *> getGCCRegNames() const final { 8238 return None; 8239 } 8240 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8241 return None; 8242 } 8243 bool 8244 validateAsmConstraint(const char *&Name, 8245 TargetInfo::ConstraintInfo &Info) const final { 8246 return false; 8247 } 8248 const char *getClobbers() const final { return ""; } 8249 bool isCLZForZeroUndef() const final { return false; } 8250 bool hasInt128Type() const final { return true; } 8251 IntType getIntTypeByWidth(unsigned BitWidth, 8252 bool IsSigned) const final { 8253 // WebAssembly prefers long long for explicitly 64-bit integers. 8254 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8255 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8256 } 8257 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8258 bool IsSigned) const final { 8259 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8260 return BitWidth == 64 8261 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8262 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8263 } 8264 }; 8265 8266 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8267 #define BUILTIN(ID, TYPE, ATTRS) \ 8268 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8269 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8270 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8271 #include "clang/Basic/BuiltinsWebAssembly.def" 8272 }; 8273 8274 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8275 public: 8276 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8277 const TargetOptions &Opts) 8278 : WebAssemblyTargetInfo(T, Opts) { 8279 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8280 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8281 } 8282 8283 protected: 8284 void getTargetDefines(const LangOptions &Opts, 8285 MacroBuilder &Builder) const override { 8286 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8287 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8288 } 8289 }; 8290 8291 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8292 public: 8293 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8294 const TargetOptions &Opts) 8295 : WebAssemblyTargetInfo(T, Opts) { 8296 LongAlign = LongWidth = 64; 8297 PointerAlign = PointerWidth = 64; 8298 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8299 SizeType = UnsignedLong; 8300 PtrDiffType = SignedLong; 8301 IntPtrType = SignedLong; 8302 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8303 } 8304 8305 protected: 8306 void getTargetDefines(const LangOptions &Opts, 8307 MacroBuilder &Builder) const override { 8308 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8309 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8310 } 8311 }; 8312 8313 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8314 #define BUILTIN(ID, TYPE, ATTRS) \ 8315 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8316 #include "clang/Basic/BuiltinsLe64.def" 8317 }; 8318 8319 static const unsigned SPIRAddrSpaceMap[] = { 8320 1, // opencl_global 8321 3, // opencl_local 8322 2, // opencl_constant 8323 4, // opencl_generic 8324 0, // cuda_device 8325 0, // cuda_constant 8326 0 // cuda_shared 8327 }; 8328 class SPIRTargetInfo : public TargetInfo { 8329 public: 8330 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8331 : TargetInfo(Triple) { 8332 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8333 "SPIR target must use unknown OS"); 8334 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8335 "SPIR target must use unknown environment type"); 8336 TLSSupported = false; 8337 LongWidth = LongAlign = 64; 8338 AddrSpaceMap = &SPIRAddrSpaceMap; 8339 UseAddrSpaceMapMangling = true; 8340 // Define available target features 8341 // These must be defined in sorted order! 8342 NoAsmVariants = true; 8343 } 8344 void getTargetDefines(const LangOptions &Opts, 8345 MacroBuilder &Builder) const override { 8346 DefineStd(Builder, "SPIR", Opts); 8347 } 8348 bool hasFeature(StringRef Feature) const override { 8349 return Feature == "spir"; 8350 } 8351 8352 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8353 const char *getClobbers() const override { return ""; } 8354 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8355 bool validateAsmConstraint(const char *&Name, 8356 TargetInfo::ConstraintInfo &info) const override { 8357 return true; 8358 } 8359 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8360 return None; 8361 } 8362 BuiltinVaListKind getBuiltinVaListKind() const override { 8363 return TargetInfo::VoidPtrBuiltinVaList; 8364 } 8365 8366 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8367 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8368 : CCCR_Warning; 8369 } 8370 8371 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8372 return CC_SpirFunction; 8373 } 8374 8375 void setSupportedOpenCLOpts() override { 8376 // Assume all OpenCL extensions and optional core features are supported 8377 // for SPIR since it is a generic target. 8378 getSupportedOpenCLOpts().supportAll(); 8379 } 8380 }; 8381 8382 class SPIR32TargetInfo : public SPIRTargetInfo { 8383 public: 8384 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8385 : SPIRTargetInfo(Triple, Opts) { 8386 PointerWidth = PointerAlign = 32; 8387 SizeType = TargetInfo::UnsignedInt; 8388 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8389 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8390 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8391 } 8392 void getTargetDefines(const LangOptions &Opts, 8393 MacroBuilder &Builder) const override { 8394 DefineStd(Builder, "SPIR32", Opts); 8395 } 8396 }; 8397 8398 class SPIR64TargetInfo : public SPIRTargetInfo { 8399 public: 8400 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8401 : SPIRTargetInfo(Triple, Opts) { 8402 PointerWidth = PointerAlign = 64; 8403 SizeType = TargetInfo::UnsignedLong; 8404 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8405 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8406 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8407 } 8408 void getTargetDefines(const LangOptions &Opts, 8409 MacroBuilder &Builder) const override { 8410 DefineStd(Builder, "SPIR64", Opts); 8411 } 8412 }; 8413 8414 class XCoreTargetInfo : public TargetInfo { 8415 static const Builtin::Info BuiltinInfo[]; 8416 public: 8417 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8418 : TargetInfo(Triple) { 8419 NoAsmVariants = true; 8420 LongLongAlign = 32; 8421 SuitableAlign = 32; 8422 DoubleAlign = LongDoubleAlign = 32; 8423 SizeType = UnsignedInt; 8424 PtrDiffType = SignedInt; 8425 IntPtrType = SignedInt; 8426 WCharType = UnsignedChar; 8427 WIntType = UnsignedInt; 8428 UseZeroLengthBitfieldAlignment = true; 8429 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8430 "-f64:32-a:0:32-n32"); 8431 } 8432 void getTargetDefines(const LangOptions &Opts, 8433 MacroBuilder &Builder) const override { 8434 Builder.defineMacro("__XS1B__"); 8435 } 8436 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8437 return llvm::makeArrayRef(BuiltinInfo, 8438 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8439 } 8440 BuiltinVaListKind getBuiltinVaListKind() const override { 8441 return TargetInfo::VoidPtrBuiltinVaList; 8442 } 8443 const char *getClobbers() const override { 8444 return ""; 8445 } 8446 ArrayRef<const char *> getGCCRegNames() const override { 8447 static const char * const GCCRegNames[] = { 8448 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8449 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8450 }; 8451 return llvm::makeArrayRef(GCCRegNames); 8452 } 8453 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8454 return None; 8455 } 8456 bool validateAsmConstraint(const char *&Name, 8457 TargetInfo::ConstraintInfo &Info) const override { 8458 return false; 8459 } 8460 int getEHDataRegisterNumber(unsigned RegNo) const override { 8461 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8462 return (RegNo < 2)? RegNo : -1; 8463 } 8464 bool allowsLargerPreferedTypeAlignment() const override { 8465 return false; 8466 } 8467 }; 8468 8469 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8470 #define BUILTIN(ID, TYPE, ATTRS) \ 8471 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8472 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8473 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8474 #include "clang/Basic/BuiltinsXCore.def" 8475 }; 8476 8477 // x86_32 Android target 8478 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8479 public: 8480 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8481 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8482 SuitableAlign = 32; 8483 LongDoubleWidth = 64; 8484 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8485 } 8486 }; 8487 8488 // x86_64 Android target 8489 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8490 public: 8491 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8492 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8493 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8494 } 8495 8496 bool useFloat128ManglingForLongDouble() const override { 8497 return true; 8498 } 8499 }; 8500 8501 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8502 class RenderScript32TargetInfo : public ARMleTargetInfo { 8503 public: 8504 RenderScript32TargetInfo(const llvm::Triple &Triple, 8505 const TargetOptions &Opts) 8506 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8507 Triple.getOSName(), 8508 Triple.getEnvironmentName()), 8509 Opts) { 8510 IsRenderScriptTarget = true; 8511 LongWidth = LongAlign = 64; 8512 } 8513 void getTargetDefines(const LangOptions &Opts, 8514 MacroBuilder &Builder) const override { 8515 Builder.defineMacro("__RENDERSCRIPT__"); 8516 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8517 } 8518 }; 8519 8520 // 64-bit RenderScript is aarch64 8521 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8522 public: 8523 RenderScript64TargetInfo(const llvm::Triple &Triple, 8524 const TargetOptions &Opts) 8525 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8526 Triple.getOSName(), 8527 Triple.getEnvironmentName()), 8528 Opts) { 8529 IsRenderScriptTarget = true; 8530 } 8531 8532 void getTargetDefines(const LangOptions &Opts, 8533 MacroBuilder &Builder) const override { 8534 Builder.defineMacro("__RENDERSCRIPT__"); 8535 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8536 } 8537 }; 8538 8539 /// Information about a specific microcontroller. 8540 struct MCUInfo { 8541 const char *Name; 8542 const char *DefineName; 8543 }; 8544 8545 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8546 static ArrayRef<MCUInfo> AVRMcus = { 8547 { "at90s1200", "__AVR_AT90S1200__" }, 8548 { "attiny11", "__AVR_ATtiny11__" }, 8549 { "attiny12", "__AVR_ATtiny12__" }, 8550 { "attiny15", "__AVR_ATtiny15__" }, 8551 { "attiny28", "__AVR_ATtiny28__" }, 8552 { "at90s2313", "__AVR_AT90S2313__" }, 8553 { "at90s2323", "__AVR_AT90S2323__" }, 8554 { "at90s2333", "__AVR_AT90S2333__" }, 8555 { "at90s2343", "__AVR_AT90S2343__" }, 8556 { "attiny22", "__AVR_ATtiny22__" }, 8557 { "attiny26", "__AVR_ATtiny26__" }, 8558 { "at86rf401", "__AVR_AT86RF401__" }, 8559 { "at90s4414", "__AVR_AT90S4414__" }, 8560 { "at90s4433", "__AVR_AT90S4433__" }, 8561 { "at90s4434", "__AVR_AT90S4434__" }, 8562 { "at90s8515", "__AVR_AT90S8515__" }, 8563 { "at90c8534", "__AVR_AT90c8534__" }, 8564 { "at90s8535", "__AVR_AT90S8535__" }, 8565 { "ata5272", "__AVR_ATA5272__" }, 8566 { "attiny13", "__AVR_ATtiny13__" }, 8567 { "attiny13a", "__AVR_ATtiny13A__" }, 8568 { "attiny2313", "__AVR_ATtiny2313__" }, 8569 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8570 { "attiny24", "__AVR_ATtiny24__" }, 8571 { "attiny24a", "__AVR_ATtiny24A__" }, 8572 { "attiny4313", "__AVR_ATtiny4313__" }, 8573 { "attiny44", "__AVR_ATtiny44__" }, 8574 { "attiny44a", "__AVR_ATtiny44A__" }, 8575 { "attiny84", "__AVR_ATtiny84__" }, 8576 { "attiny84a", "__AVR_ATtiny84A__" }, 8577 { "attiny25", "__AVR_ATtiny25__" }, 8578 { "attiny45", "__AVR_ATtiny45__" }, 8579 { "attiny85", "__AVR_ATtiny85__" }, 8580 { "attiny261", "__AVR_ATtiny261__" }, 8581 { "attiny261a", "__AVR_ATtiny261A__" }, 8582 { "attiny461", "__AVR_ATtiny461__" }, 8583 { "attiny461a", "__AVR_ATtiny461A__" }, 8584 { "attiny861", "__AVR_ATtiny861__" }, 8585 { "attiny861a", "__AVR_ATtiny861A__" }, 8586 { "attiny87", "__AVR_ATtiny87__" }, 8587 { "attiny43u", "__AVR_ATtiny43U__" }, 8588 { "attiny48", "__AVR_ATtiny48__" }, 8589 { "attiny88", "__AVR_ATtiny88__" }, 8590 { "attiny828", "__AVR_ATtiny828__" }, 8591 { "at43usb355", "__AVR_AT43USB355__" }, 8592 { "at76c711", "__AVR_AT76C711__" }, 8593 { "atmega103", "__AVR_ATmega103__" }, 8594 { "at43usb320", "__AVR_AT43USB320__" }, 8595 { "attiny167", "__AVR_ATtiny167__" }, 8596 { "at90usb82", "__AVR_AT90USB82__" }, 8597 { "at90usb162", "__AVR_AT90USB162__" }, 8598 { "ata5505", "__AVR_ATA5505__" }, 8599 { "atmega8u2", "__AVR_ATmega8U2__" }, 8600 { "atmega16u2", "__AVR_ATmega16U2__" }, 8601 { "atmega32u2", "__AVR_ATmega32U2__" }, 8602 { "attiny1634", "__AVR_ATtiny1634__" }, 8603 { "atmega8", "__AVR_ATmega8__" }, 8604 { "ata6289", "__AVR_ATA6289__" }, 8605 { "atmega8a", "__AVR_ATmega8A__" }, 8606 { "ata6285", "__AVR_ATA6285__" }, 8607 { "ata6286", "__AVR_ATA6286__" }, 8608 { "atmega48", "__AVR_ATmega48__" }, 8609 { "atmega48a", "__AVR_ATmega48A__" }, 8610 { "atmega48pa", "__AVR_ATmega48PA__" }, 8611 { "atmega48p", "__AVR_ATmega48P__" }, 8612 { "atmega88", "__AVR_ATmega88__" }, 8613 { "atmega88a", "__AVR_ATmega88A__" }, 8614 { "atmega88p", "__AVR_ATmega88P__" }, 8615 { "atmega88pa", "__AVR_ATmega88PA__" }, 8616 { "atmega8515", "__AVR_ATmega8515__" }, 8617 { "atmega8535", "__AVR_ATmega8535__" }, 8618 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8619 { "at90pwm1", "__AVR_AT90PWM1__" }, 8620 { "at90pwm2", "__AVR_AT90PWM2__" }, 8621 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8622 { "at90pwm3", "__AVR_AT90PWM3__" }, 8623 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8624 { "at90pwm81", "__AVR_AT90PWM81__" }, 8625 { "ata5790", "__AVR_ATA5790__" }, 8626 { "ata5795", "__AVR_ATA5795__" }, 8627 { "atmega16", "__AVR_ATmega16__" }, 8628 { "atmega16a", "__AVR_ATmega16A__" }, 8629 { "atmega161", "__AVR_ATmega161__" }, 8630 { "atmega162", "__AVR_ATmega162__" }, 8631 { "atmega163", "__AVR_ATmega163__" }, 8632 { "atmega164a", "__AVR_ATmega164A__" }, 8633 { "atmega164p", "__AVR_ATmega164P__" }, 8634 { "atmega164pa", "__AVR_ATmega164PA__" }, 8635 { "atmega165", "__AVR_ATmega165__" }, 8636 { "atmega165a", "__AVR_ATmega165A__" }, 8637 { "atmega165p", "__AVR_ATmega165P__" }, 8638 { "atmega165pa", "__AVR_ATmega165PA__" }, 8639 { "atmega168", "__AVR_ATmega168__" }, 8640 { "atmega168a", "__AVR_ATmega168A__" }, 8641 { "atmega168p", "__AVR_ATmega168P__" }, 8642 { "atmega168pa", "__AVR_ATmega168PA__" }, 8643 { "atmega169", "__AVR_ATmega169__" }, 8644 { "atmega169a", "__AVR_ATmega169A__" }, 8645 { "atmega169p", "__AVR_ATmega169P__" }, 8646 { "atmega169pa", "__AVR_ATmega169PA__" }, 8647 { "atmega32", "__AVR_ATmega32__" }, 8648 { "atmega32a", "__AVR_ATmega32A__" }, 8649 { "atmega323", "__AVR_ATmega323__" }, 8650 { "atmega324a", "__AVR_ATmega324A__" }, 8651 { "atmega324p", "__AVR_ATmega324P__" }, 8652 { "atmega324pa", "__AVR_ATmega324PA__" }, 8653 { "atmega325", "__AVR_ATmega325__" }, 8654 { "atmega325a", "__AVR_ATmega325A__" }, 8655 { "atmega325p", "__AVR_ATmega325P__" }, 8656 { "atmega325pa", "__AVR_ATmega325PA__" }, 8657 { "atmega3250", "__AVR_ATmega3250__" }, 8658 { "atmega3250a", "__AVR_ATmega3250A__" }, 8659 { "atmega3250p", "__AVR_ATmega3250P__" }, 8660 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8661 { "atmega328", "__AVR_ATmega328__" }, 8662 { "atmega328p", "__AVR_ATmega328P__" }, 8663 { "atmega329", "__AVR_ATmega329__" }, 8664 { "atmega329a", "__AVR_ATmega329A__" }, 8665 { "atmega329p", "__AVR_ATmega329P__" }, 8666 { "atmega329pa", "__AVR_ATmega329PA__" }, 8667 { "atmega3290", "__AVR_ATmega3290__" }, 8668 { "atmega3290a", "__AVR_ATmega3290A__" }, 8669 { "atmega3290p", "__AVR_ATmega3290P__" }, 8670 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8671 { "atmega406", "__AVR_ATmega406__" }, 8672 { "atmega64", "__AVR_ATmega64__" }, 8673 { "atmega64a", "__AVR_ATmega64A__" }, 8674 { "atmega640", "__AVR_ATmega640__" }, 8675 { "atmega644", "__AVR_ATmega644__" }, 8676 { "atmega644a", "__AVR_ATmega644A__" }, 8677 { "atmega644p", "__AVR_ATmega644P__" }, 8678 { "atmega644pa", "__AVR_ATmega644PA__" }, 8679 { "atmega645", "__AVR_ATmega645__" }, 8680 { "atmega645a", "__AVR_ATmega645A__" }, 8681 { "atmega645p", "__AVR_ATmega645P__" }, 8682 { "atmega649", "__AVR_ATmega649__" }, 8683 { "atmega649a", "__AVR_ATmega649A__" }, 8684 { "atmega649p", "__AVR_ATmega649P__" }, 8685 { "atmega6450", "__AVR_ATmega6450__" }, 8686 { "atmega6450a", "__AVR_ATmega6450A__" }, 8687 { "atmega6450p", "__AVR_ATmega6450P__" }, 8688 { "atmega6490", "__AVR_ATmega6490__" }, 8689 { "atmega6490a", "__AVR_ATmega6490A__" }, 8690 { "atmega6490p", "__AVR_ATmega6490P__" }, 8691 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8692 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8693 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8694 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8695 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8696 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8697 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8698 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8699 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8700 { "at90can32", "__AVR_AT90CAN32__" }, 8701 { "at90can64", "__AVR_AT90CAN64__" }, 8702 { "at90pwm161", "__AVR_AT90PWM161__" }, 8703 { "at90pwm216", "__AVR_AT90PWM216__" }, 8704 { "at90pwm316", "__AVR_AT90PWM316__" }, 8705 { "atmega32c1", "__AVR_ATmega32C1__" }, 8706 { "atmega64c1", "__AVR_ATmega64C1__" }, 8707 { "atmega16m1", "__AVR_ATmega16M1__" }, 8708 { "atmega32m1", "__AVR_ATmega32M1__" }, 8709 { "atmega64m1", "__AVR_ATmega64M1__" }, 8710 { "atmega16u4", "__AVR_ATmega16U4__" }, 8711 { "atmega32u4", "__AVR_ATmega32U4__" }, 8712 { "atmega32u6", "__AVR_ATmega32U6__" }, 8713 { "at90usb646", "__AVR_AT90USB646__" }, 8714 { "at90usb647", "__AVR_AT90USB647__" }, 8715 { "at90scr100", "__AVR_AT90SCR100__" }, 8716 { "at94k", "__AVR_AT94K__" }, 8717 { "m3000", "__AVR_AT000__" }, 8718 { "atmega128", "__AVR_ATmega128__" }, 8719 { "atmega128a", "__AVR_ATmega128A__" }, 8720 { "atmega1280", "__AVR_ATmega1280__" }, 8721 { "atmega1281", "__AVR_ATmega1281__" }, 8722 { "atmega1284", "__AVR_ATmega1284__" }, 8723 { "atmega1284p", "__AVR_ATmega1284P__" }, 8724 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8725 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8726 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8727 { "at90can128", "__AVR_AT90CAN128__" }, 8728 { "at90usb1286", "__AVR_AT90USB1286__" }, 8729 { "at90usb1287", "__AVR_AT90USB1287__" }, 8730 { "atmega2560", "__AVR_ATmega2560__" }, 8731 { "atmega2561", "__AVR_ATmega2561__" }, 8732 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8733 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8734 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8735 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8736 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8737 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8738 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8739 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8740 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8741 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8742 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8743 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8744 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8745 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8746 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8747 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8748 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8749 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8750 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8751 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8752 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8753 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8754 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8755 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8756 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8757 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8758 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8759 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8760 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8761 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8762 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8763 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8764 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8765 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8766 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8767 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8768 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8769 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8770 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8771 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8772 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8773 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8774 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8775 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8776 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8777 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8778 { "attiny4", "__AVR_ATtiny4__" }, 8779 { "attiny5", "__AVR_ATtiny5__" }, 8780 { "attiny9", "__AVR_ATtiny9__" }, 8781 { "attiny10", "__AVR_ATtiny10__" }, 8782 { "attiny20", "__AVR_ATtiny20__" }, 8783 { "attiny40", "__AVR_ATtiny40__" }, 8784 { "attiny102", "__AVR_ATtiny102__" }, 8785 { "attiny104", "__AVR_ATtiny104__" }, 8786 }; 8787 8788 // AVR Target 8789 class AVRTargetInfo : public TargetInfo { 8790 public: 8791 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8792 : TargetInfo(Triple) { 8793 TLSSupported = false; 8794 PointerWidth = 16; 8795 PointerAlign = 8; 8796 IntWidth = 16; 8797 IntAlign = 8; 8798 LongWidth = 32; 8799 LongAlign = 8; 8800 LongLongWidth = 64; 8801 LongLongAlign = 8; 8802 SuitableAlign = 8; 8803 DefaultAlignForAttributeAligned = 8; 8804 HalfWidth = 16; 8805 HalfAlign = 8; 8806 FloatWidth = 32; 8807 FloatAlign = 8; 8808 DoubleWidth = 32; 8809 DoubleAlign = 8; 8810 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8811 LongDoubleWidth = 32; 8812 LongDoubleAlign = 8; 8813 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8814 SizeType = UnsignedInt; 8815 PtrDiffType = SignedInt; 8816 IntPtrType = SignedInt; 8817 Char16Type = UnsignedInt; 8818 WCharType = SignedInt; 8819 WIntType = SignedInt; 8820 Char32Type = UnsignedLong; 8821 SigAtomicType = SignedChar; 8822 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8823 "-f32:32:32-f64:64:64-n8"); 8824 } 8825 8826 void getTargetDefines(const LangOptions &Opts, 8827 MacroBuilder &Builder) const override { 8828 Builder.defineMacro("AVR"); 8829 Builder.defineMacro("__AVR"); 8830 Builder.defineMacro("__AVR__"); 8831 8832 if (!this->CPU.empty()) { 8833 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8834 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 8835 8836 if (It != AVRMcus.end()) 8837 Builder.defineMacro(It->DefineName); 8838 } 8839 } 8840 8841 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8842 return None; 8843 } 8844 8845 BuiltinVaListKind getBuiltinVaListKind() const override { 8846 return TargetInfo::VoidPtrBuiltinVaList; 8847 } 8848 8849 const char *getClobbers() const override { 8850 return ""; 8851 } 8852 8853 ArrayRef<const char *> getGCCRegNames() const override { 8854 static const char * const GCCRegNames[] = { 8855 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8856 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 8857 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 8858 "r24", "r25", "X", "Y", "Z", "SP" 8859 }; 8860 return llvm::makeArrayRef(GCCRegNames); 8861 } 8862 8863 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8864 return None; 8865 } 8866 8867 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 8868 static const TargetInfo::AddlRegName AddlRegNames[] = { 8869 { { "r26", "r27"}, 26 }, 8870 { { "r28", "r29"}, 27 }, 8871 { { "r30", "r31"}, 28 }, 8872 { { "SPL", "SPH"}, 29 }, 8873 }; 8874 return llvm::makeArrayRef(AddlRegNames); 8875 } 8876 8877 bool validateAsmConstraint(const char *&Name, 8878 TargetInfo::ConstraintInfo &Info) const override { 8879 // There aren't any multi-character AVR specific constraints. 8880 if (StringRef(Name).size() > 1) return false; 8881 8882 switch (*Name) { 8883 default: return false; 8884 case 'a': // Simple upper registers 8885 case 'b': // Base pointer registers pairs 8886 case 'd': // Upper register 8887 case 'l': // Lower registers 8888 case 'e': // Pointer register pairs 8889 case 'q': // Stack pointer register 8890 case 'r': // Any register 8891 case 'w': // Special upper register pairs 8892 case 't': // Temporary register 8893 case 'x': case 'X': // Pointer register pair X 8894 case 'y': case 'Y': // Pointer register pair Y 8895 case 'z': case 'Z': // Pointer register pair Z 8896 Info.setAllowsRegister(); 8897 return true; 8898 case 'I': // 6-bit positive integer constant 8899 Info.setRequiresImmediate(0, 63); 8900 return true; 8901 case 'J': // 6-bit negative integer constant 8902 Info.setRequiresImmediate(-63, 0); 8903 return true; 8904 case 'K': // Integer constant (Range: 2) 8905 Info.setRequiresImmediate(2); 8906 return true; 8907 case 'L': // Integer constant (Range: 0) 8908 Info.setRequiresImmediate(0); 8909 return true; 8910 case 'M': // 8-bit integer constant 8911 Info.setRequiresImmediate(0, 0xff); 8912 return true; 8913 case 'N': // Integer constant (Range: -1) 8914 Info.setRequiresImmediate(-1); 8915 return true; 8916 case 'O': // Integer constant (Range: 8, 16, 24) 8917 Info.setRequiresImmediate({8, 16, 24}); 8918 return true; 8919 case 'P': // Integer constant (Range: 1) 8920 Info.setRequiresImmediate(1); 8921 return true; 8922 case 'R': // Integer constant (Range: -6 to 5) 8923 Info.setRequiresImmediate(-6, 5); 8924 return true; 8925 case 'G': // Floating point constant 8926 case 'Q': // A memory address based on Y or Z pointer with displacement. 8927 return true; 8928 } 8929 8930 return false; 8931 } 8932 8933 IntType getIntTypeByWidth(unsigned BitWidth, 8934 bool IsSigned) const final { 8935 // AVR prefers int for 16-bit integers. 8936 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 8937 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8938 } 8939 8940 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8941 bool IsSigned) const final { 8942 // AVR uses int for int_least16_t and int_fast16_t. 8943 return BitWidth == 16 8944 ? (IsSigned ? SignedInt : UnsignedInt) 8945 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8946 } 8947 8948 bool setCPU(const std::string &Name) override { 8949 bool IsFamily = llvm::StringSwitch<bool>(Name) 8950 .Case("avr1", true) 8951 .Case("avr2", true) 8952 .Case("avr25", true) 8953 .Case("avr3", true) 8954 .Case("avr31", true) 8955 .Case("avr35", true) 8956 .Case("avr4", true) 8957 .Case("avr5", true) 8958 .Case("avr51", true) 8959 .Case("avr6", true) 8960 .Case("avrxmega1", true) 8961 .Case("avrxmega2", true) 8962 .Case("avrxmega3", true) 8963 .Case("avrxmega4", true) 8964 .Case("avrxmega5", true) 8965 .Case("avrxmega6", true) 8966 .Case("avrxmega7", true) 8967 .Case("avrtiny", true) 8968 .Default(false); 8969 8970 if (IsFamily) this->CPU = Name; 8971 8972 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 8973 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 8974 8975 if (IsMCU) this->CPU = Name; 8976 8977 return IsFamily || IsMCU; 8978 } 8979 8980 protected: 8981 std::string CPU; 8982 }; 8983 8984 } // end anonymous namespace 8985 8986 //===----------------------------------------------------------------------===// 8987 // Driver code 8988 //===----------------------------------------------------------------------===// 8989 8990 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8991 const TargetOptions &Opts) { 8992 llvm::Triple::OSType os = Triple.getOS(); 8993 8994 switch (Triple.getArch()) { 8995 default: 8996 return nullptr; 8997 8998 case llvm::Triple::xcore: 8999 return new XCoreTargetInfo(Triple, Opts); 9000 9001 case llvm::Triple::hexagon: 9002 return new HexagonTargetInfo(Triple, Opts); 9003 9004 case llvm::Triple::lanai: 9005 return new LanaiTargetInfo(Triple, Opts); 9006 9007 case llvm::Triple::aarch64: 9008 if (Triple.isOSDarwin()) 9009 return new DarwinAArch64TargetInfo(Triple, Opts); 9010 9011 switch (os) { 9012 case llvm::Triple::CloudABI: 9013 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9014 case llvm::Triple::FreeBSD: 9015 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9016 case llvm::Triple::Fuchsia: 9017 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9018 case llvm::Triple::Linux: 9019 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9020 case llvm::Triple::NetBSD: 9021 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9022 case llvm::Triple::OpenBSD: 9023 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9024 default: 9025 return new AArch64leTargetInfo(Triple, Opts); 9026 } 9027 9028 case llvm::Triple::aarch64_be: 9029 switch (os) { 9030 case llvm::Triple::FreeBSD: 9031 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9032 case llvm::Triple::Fuchsia: 9033 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9034 case llvm::Triple::Linux: 9035 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9036 case llvm::Triple::NetBSD: 9037 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9038 default: 9039 return new AArch64beTargetInfo(Triple, Opts); 9040 } 9041 9042 case llvm::Triple::arm: 9043 case llvm::Triple::thumb: 9044 if (Triple.isOSBinFormatMachO()) 9045 return new DarwinARMTargetInfo(Triple, Opts); 9046 9047 switch (os) { 9048 case llvm::Triple::CloudABI: 9049 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9050 case llvm::Triple::Linux: 9051 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9052 case llvm::Triple::FreeBSD: 9053 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9054 case llvm::Triple::NetBSD: 9055 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9056 case llvm::Triple::OpenBSD: 9057 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9058 case llvm::Triple::Bitrig: 9059 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9060 case llvm::Triple::RTEMS: 9061 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9062 case llvm::Triple::NaCl: 9063 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9064 case llvm::Triple::Win32: 9065 switch (Triple.getEnvironment()) { 9066 case llvm::Triple::Cygnus: 9067 return new CygwinARMTargetInfo(Triple, Opts); 9068 case llvm::Triple::GNU: 9069 return new MinGWARMTargetInfo(Triple, Opts); 9070 case llvm::Triple::Itanium: 9071 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9072 case llvm::Triple::MSVC: 9073 default: // Assume MSVC for unknown environments 9074 return new MicrosoftARMleTargetInfo(Triple, Opts); 9075 } 9076 default: 9077 return new ARMleTargetInfo(Triple, Opts); 9078 } 9079 9080 case llvm::Triple::armeb: 9081 case llvm::Triple::thumbeb: 9082 if (Triple.isOSDarwin()) 9083 return new DarwinARMTargetInfo(Triple, Opts); 9084 9085 switch (os) { 9086 case llvm::Triple::Linux: 9087 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9088 case llvm::Triple::FreeBSD: 9089 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9090 case llvm::Triple::NetBSD: 9091 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9092 case llvm::Triple::OpenBSD: 9093 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9094 case llvm::Triple::Bitrig: 9095 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9096 case llvm::Triple::RTEMS: 9097 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9098 case llvm::Triple::NaCl: 9099 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9100 default: 9101 return new ARMbeTargetInfo(Triple, Opts); 9102 } 9103 9104 case llvm::Triple::avr: 9105 return new AVRTargetInfo(Triple, Opts); 9106 case llvm::Triple::bpfeb: 9107 case llvm::Triple::bpfel: 9108 return new BPFTargetInfo(Triple, Opts); 9109 9110 case llvm::Triple::msp430: 9111 return new MSP430TargetInfo(Triple, Opts); 9112 9113 case llvm::Triple::mips: 9114 switch (os) { 9115 case llvm::Triple::Linux: 9116 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9117 case llvm::Triple::RTEMS: 9118 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9119 case llvm::Triple::FreeBSD: 9120 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9121 case llvm::Triple::NetBSD: 9122 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9123 default: 9124 return new MipsTargetInfo(Triple, Opts); 9125 } 9126 9127 case llvm::Triple::mipsel: 9128 switch (os) { 9129 case llvm::Triple::Linux: 9130 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9131 case llvm::Triple::RTEMS: 9132 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9133 case llvm::Triple::FreeBSD: 9134 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9135 case llvm::Triple::NetBSD: 9136 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9137 case llvm::Triple::NaCl: 9138 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9139 default: 9140 return new MipsTargetInfo(Triple, Opts); 9141 } 9142 9143 case llvm::Triple::mips64: 9144 switch (os) { 9145 case llvm::Triple::Linux: 9146 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9147 case llvm::Triple::RTEMS: 9148 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9149 case llvm::Triple::FreeBSD: 9150 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9151 case llvm::Triple::NetBSD: 9152 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9153 case llvm::Triple::OpenBSD: 9154 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9155 default: 9156 return new MipsTargetInfo(Triple, Opts); 9157 } 9158 9159 case llvm::Triple::mips64el: 9160 switch (os) { 9161 case llvm::Triple::Linux: 9162 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9163 case llvm::Triple::RTEMS: 9164 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9165 case llvm::Triple::FreeBSD: 9166 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9167 case llvm::Triple::NetBSD: 9168 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9169 case llvm::Triple::OpenBSD: 9170 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9171 default: 9172 return new MipsTargetInfo(Triple, Opts); 9173 } 9174 9175 case llvm::Triple::le32: 9176 switch (os) { 9177 case llvm::Triple::NaCl: 9178 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9179 default: 9180 return nullptr; 9181 } 9182 9183 case llvm::Triple::le64: 9184 return new Le64TargetInfo(Triple, Opts); 9185 9186 case llvm::Triple::ppc: 9187 if (Triple.isOSDarwin()) 9188 return new DarwinPPC32TargetInfo(Triple, Opts); 9189 switch (os) { 9190 case llvm::Triple::Linux: 9191 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9192 case llvm::Triple::FreeBSD: 9193 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9194 case llvm::Triple::NetBSD: 9195 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9196 case llvm::Triple::OpenBSD: 9197 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9198 case llvm::Triple::RTEMS: 9199 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9200 default: 9201 return new PPC32TargetInfo(Triple, Opts); 9202 } 9203 9204 case llvm::Triple::ppc64: 9205 if (Triple.isOSDarwin()) 9206 return new DarwinPPC64TargetInfo(Triple, Opts); 9207 switch (os) { 9208 case llvm::Triple::Linux: 9209 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9210 case llvm::Triple::Lv2: 9211 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9212 case llvm::Triple::FreeBSD: 9213 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9214 case llvm::Triple::NetBSD: 9215 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9216 default: 9217 return new PPC64TargetInfo(Triple, Opts); 9218 } 9219 9220 case llvm::Triple::ppc64le: 9221 switch (os) { 9222 case llvm::Triple::Linux: 9223 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9224 case llvm::Triple::NetBSD: 9225 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9226 default: 9227 return new PPC64TargetInfo(Triple, Opts); 9228 } 9229 9230 case llvm::Triple::nvptx: 9231 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9232 case llvm::Triple::nvptx64: 9233 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9234 9235 case llvm::Triple::amdgcn: 9236 case llvm::Triple::r600: 9237 return new AMDGPUTargetInfo(Triple, Opts); 9238 9239 case llvm::Triple::sparc: 9240 switch (os) { 9241 case llvm::Triple::Linux: 9242 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9243 case llvm::Triple::Solaris: 9244 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9245 case llvm::Triple::NetBSD: 9246 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9247 case llvm::Triple::OpenBSD: 9248 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9249 case llvm::Triple::RTEMS: 9250 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9251 default: 9252 return new SparcV8TargetInfo(Triple, Opts); 9253 } 9254 9255 // The 'sparcel' architecture copies all the above cases except for Solaris. 9256 case llvm::Triple::sparcel: 9257 switch (os) { 9258 case llvm::Triple::Linux: 9259 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9260 case llvm::Triple::NetBSD: 9261 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9262 case llvm::Triple::OpenBSD: 9263 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9264 case llvm::Triple::RTEMS: 9265 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9266 default: 9267 return new SparcV8elTargetInfo(Triple, Opts); 9268 } 9269 9270 case llvm::Triple::sparcv9: 9271 switch (os) { 9272 case llvm::Triple::Linux: 9273 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9274 case llvm::Triple::Solaris: 9275 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9276 case llvm::Triple::NetBSD: 9277 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9278 case llvm::Triple::OpenBSD: 9279 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9280 case llvm::Triple::FreeBSD: 9281 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9282 default: 9283 return new SparcV9TargetInfo(Triple, Opts); 9284 } 9285 9286 case llvm::Triple::systemz: 9287 switch (os) { 9288 case llvm::Triple::Linux: 9289 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9290 default: 9291 return new SystemZTargetInfo(Triple, Opts); 9292 } 9293 9294 case llvm::Triple::tce: 9295 return new TCETargetInfo(Triple, Opts); 9296 9297 case llvm::Triple::tcele: 9298 return new TCELETargetInfo(Triple, Opts); 9299 9300 case llvm::Triple::x86: 9301 if (Triple.isOSDarwin()) 9302 return new DarwinI386TargetInfo(Triple, Opts); 9303 9304 switch (os) { 9305 case llvm::Triple::CloudABI: 9306 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9307 case llvm::Triple::Linux: { 9308 switch (Triple.getEnvironment()) { 9309 default: 9310 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9311 case llvm::Triple::Android: 9312 return new AndroidX86_32TargetInfo(Triple, Opts); 9313 } 9314 } 9315 case llvm::Triple::DragonFly: 9316 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9317 case llvm::Triple::NetBSD: 9318 return new NetBSDI386TargetInfo(Triple, Opts); 9319 case llvm::Triple::OpenBSD: 9320 return new OpenBSDI386TargetInfo(Triple, Opts); 9321 case llvm::Triple::Bitrig: 9322 return new BitrigI386TargetInfo(Triple, Opts); 9323 case llvm::Triple::FreeBSD: 9324 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9325 case llvm::Triple::KFreeBSD: 9326 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9327 case llvm::Triple::Minix: 9328 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9329 case llvm::Triple::Solaris: 9330 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9331 case llvm::Triple::Win32: { 9332 switch (Triple.getEnvironment()) { 9333 case llvm::Triple::Cygnus: 9334 return new CygwinX86_32TargetInfo(Triple, Opts); 9335 case llvm::Triple::GNU: 9336 return new MinGWX86_32TargetInfo(Triple, Opts); 9337 case llvm::Triple::Itanium: 9338 case llvm::Triple::MSVC: 9339 default: // Assume MSVC for unknown environments 9340 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9341 } 9342 } 9343 case llvm::Triple::Haiku: 9344 return new HaikuX86_32TargetInfo(Triple, Opts); 9345 case llvm::Triple::RTEMS: 9346 return new RTEMSX86_32TargetInfo(Triple, Opts); 9347 case llvm::Triple::NaCl: 9348 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9349 case llvm::Triple::ELFIAMCU: 9350 return new MCUX86_32TargetInfo(Triple, Opts); 9351 default: 9352 return new X86_32TargetInfo(Triple, Opts); 9353 } 9354 9355 case llvm::Triple::x86_64: 9356 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9357 return new DarwinX86_64TargetInfo(Triple, Opts); 9358 9359 switch (os) { 9360 case llvm::Triple::CloudABI: 9361 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9362 case llvm::Triple::Linux: { 9363 switch (Triple.getEnvironment()) { 9364 default: 9365 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9366 case llvm::Triple::Android: 9367 return new AndroidX86_64TargetInfo(Triple, Opts); 9368 } 9369 } 9370 case llvm::Triple::DragonFly: 9371 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9372 case llvm::Triple::NetBSD: 9373 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9374 case llvm::Triple::OpenBSD: 9375 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9376 case llvm::Triple::Bitrig: 9377 return new BitrigX86_64TargetInfo(Triple, Opts); 9378 case llvm::Triple::FreeBSD: 9379 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9380 case llvm::Triple::Fuchsia: 9381 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9382 case llvm::Triple::KFreeBSD: 9383 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9384 case llvm::Triple::Solaris: 9385 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9386 case llvm::Triple::Win32: { 9387 switch (Triple.getEnvironment()) { 9388 case llvm::Triple::Cygnus: 9389 return new CygwinX86_64TargetInfo(Triple, Opts); 9390 case llvm::Triple::GNU: 9391 return new MinGWX86_64TargetInfo(Triple, Opts); 9392 case llvm::Triple::MSVC: 9393 default: // Assume MSVC for unknown environments 9394 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9395 } 9396 } 9397 case llvm::Triple::Haiku: 9398 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9399 case llvm::Triple::NaCl: 9400 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9401 case llvm::Triple::PS4: 9402 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9403 default: 9404 return new X86_64TargetInfo(Triple, Opts); 9405 } 9406 9407 case llvm::Triple::spir: { 9408 if (Triple.getOS() != llvm::Triple::UnknownOS || 9409 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9410 return nullptr; 9411 return new SPIR32TargetInfo(Triple, Opts); 9412 } 9413 case llvm::Triple::spir64: { 9414 if (Triple.getOS() != llvm::Triple::UnknownOS || 9415 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9416 return nullptr; 9417 return new SPIR64TargetInfo(Triple, Opts); 9418 } 9419 case llvm::Triple::wasm32: 9420 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9421 Triple.getVendor() != llvm::Triple::UnknownVendor || 9422 Triple.getOS() != llvm::Triple::UnknownOS || 9423 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9424 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9425 return nullptr; 9426 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9427 case llvm::Triple::wasm64: 9428 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9429 Triple.getVendor() != llvm::Triple::UnknownVendor || 9430 Triple.getOS() != llvm::Triple::UnknownOS || 9431 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9432 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9433 return nullptr; 9434 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9435 9436 case llvm::Triple::renderscript32: 9437 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9438 case llvm::Triple::renderscript64: 9439 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9440 } 9441 } 9442 9443 /// CreateTargetInfo - Return the target info object for the specified target 9444 /// options. 9445 TargetInfo * 9446 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9447 const std::shared_ptr<TargetOptions> &Opts) { 9448 llvm::Triple Triple(Opts->Triple); 9449 9450 // Construct the target 9451 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9452 if (!Target) { 9453 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9454 return nullptr; 9455 } 9456 Target->TargetOpts = Opts; 9457 9458 // Set the target CPU if specified. 9459 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9460 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9461 return nullptr; 9462 } 9463 9464 // Set the target ABI if specified. 9465 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9466 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9467 return nullptr; 9468 } 9469 9470 // Set the fp math unit. 9471 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9472 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9473 return nullptr; 9474 } 9475 9476 // Compute the default target features, we need the target to handle this 9477 // because features may have dependencies on one another. 9478 llvm::StringMap<bool> Features; 9479 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9480 Opts->FeaturesAsWritten)) 9481 return nullptr; 9482 9483 // Add the features to the compile options. 9484 Opts->Features.clear(); 9485 for (const auto &F : Features) 9486 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9487 9488 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9489 return nullptr; 9490 9491 Target->setSupportedOpenCLOpts(); 9492 Target->setOpenCLExtensionOpts(); 9493 9494 if (!Target->validateTarget(Diags)) 9495 return nullptr; 9496 9497 return Target.release(); 9498 } 9499