1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 227 this->MCountName = "\01mcount"; 228 } 229 230 std::string isValidSectionSpecifier(StringRef SR) const override { 231 // Let MCSectionMachO validate this. 232 StringRef Segment, Section; 233 unsigned TAA, StubSize; 234 bool HasTAA; 235 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 236 TAA, HasTAA, StubSize); 237 } 238 239 const char *getStaticInitSectionSpecifier() const override { 240 // FIXME: We should return 0 when building kexts. 241 return "__TEXT,__StaticInit,regular,pure_instructions"; 242 } 243 244 /// Darwin does not support protected visibility. Darwin's "default" 245 /// is very similar to ELF's "protected"; Darwin requires a "weak" 246 /// attribute on declarations that can be dynamically replaced. 247 bool hasProtectedVisibility() const override { 248 return false; 249 } 250 }; 251 252 253 // DragonFlyBSD Target 254 template<typename Target> 255 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 256 protected: 257 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 258 MacroBuilder &Builder) const override { 259 // DragonFly defines; list based off of gcc output 260 Builder.defineMacro("__DragonFly__"); 261 Builder.defineMacro("__DragonFly_cc_version", "100001"); 262 Builder.defineMacro("__ELF__"); 263 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 264 Builder.defineMacro("__tune_i386__"); 265 DefineStd(Builder, "unix", Opts); 266 } 267 public: 268 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 269 : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 } 279 } 280 }; 281 282 // FreeBSD Target 283 template<typename Target> 284 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 285 protected: 286 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 287 MacroBuilder &Builder) const override { 288 // FreeBSD defines; list based off of gcc output 289 290 unsigned Release = Triple.getOSMajorVersion(); 291 if (Release == 0U) 292 Release = 8; 293 294 Builder.defineMacro("__FreeBSD__", Twine(Release)); 295 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 296 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 297 DefineStd(Builder, "unix", Opts); 298 Builder.defineMacro("__ELF__"); 299 300 // On FreeBSD, wchar_t contains the number of the code point as 301 // used by the character set of the locale. These character sets are 302 // not necessarily a superset of ASCII. 303 // 304 // FIXME: This is wrong; the macro refers to the numerical values 305 // of wchar_t *literals*, which are not locale-dependent. However, 306 // FreeBSD systems apparently depend on us getting this wrong, and 307 // setting this to 1 is conforming even if all the basic source 308 // character literals have the same encoding as char and wchar_t. 309 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 310 } 311 public: 312 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 313 this->UserLabelPrefix = ""; 314 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 case llvm::Triple::mips: 322 case llvm::Triple::mipsel: 323 case llvm::Triple::ppc: 324 case llvm::Triple::ppc64: 325 case llvm::Triple::ppc64le: 326 this->MCountName = "_mcount"; 327 break; 328 case llvm::Triple::arm: 329 this->MCountName = "__mcount"; 330 break; 331 } 332 } 333 }; 334 335 // GNU/kFreeBSD Target 336 template<typename Target> 337 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 338 protected: 339 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 340 MacroBuilder &Builder) const override { 341 // GNU/kFreeBSD defines; list based off of gcc output 342 343 DefineStd(Builder, "unix", Opts); 344 Builder.defineMacro("__FreeBSD_kernel__"); 345 Builder.defineMacro("__GLIBC__"); 346 Builder.defineMacro("__ELF__"); 347 if (Opts.POSIXThreads) 348 Builder.defineMacro("_REENTRANT"); 349 if (Opts.CPlusPlus) 350 Builder.defineMacro("_GNU_SOURCE"); 351 } 352 public: 353 KFreeBSDTargetInfo(const llvm::Triple &Triple) 354 : OSTargetInfo<Target>(Triple) { 355 this->UserLabelPrefix = ""; 356 } 357 }; 358 359 // Minix Target 360 template<typename Target> 361 class MinixTargetInfo : public OSTargetInfo<Target> { 362 protected: 363 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 364 MacroBuilder &Builder) const override { 365 // Minix defines 366 367 Builder.defineMacro("__minix", "3"); 368 Builder.defineMacro("_EM_WSIZE", "4"); 369 Builder.defineMacro("_EM_PSIZE", "4"); 370 Builder.defineMacro("_EM_SSIZE", "2"); 371 Builder.defineMacro("_EM_LSIZE", "4"); 372 Builder.defineMacro("_EM_FSIZE", "4"); 373 Builder.defineMacro("_EM_DSIZE", "8"); 374 Builder.defineMacro("__ELF__"); 375 DefineStd(Builder, "unix", Opts); 376 } 377 public: 378 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 379 this->UserLabelPrefix = ""; 380 } 381 }; 382 383 // Linux target 384 template<typename Target> 385 class LinuxTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // Linux defines; list based off of gcc output 390 DefineStd(Builder, "unix", Opts); 391 DefineStd(Builder, "linux", Opts); 392 Builder.defineMacro("__gnu_linux__"); 393 Builder.defineMacro("__ELF__"); 394 if (Triple.isAndroid()) { 395 Builder.defineMacro("__ANDROID__", "1"); 396 unsigned Maj, Min, Rev; 397 Triple.getEnvironmentVersion(Maj, Min, Rev); 398 this->PlatformName = "android"; 399 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 400 } 401 if (Opts.POSIXThreads) 402 Builder.defineMacro("_REENTRANT"); 403 if (Opts.CPlusPlus) 404 Builder.defineMacro("_GNU_SOURCE"); 405 } 406 public: 407 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 408 this->UserLabelPrefix = ""; 409 this->WIntType = TargetInfo::UnsignedInt; 410 411 switch (Triple.getArch()) { 412 default: 413 break; 414 case llvm::Triple::ppc: 415 case llvm::Triple::ppc64: 416 case llvm::Triple::ppc64le: 417 this->MCountName = "_mcount"; 418 break; 419 } 420 } 421 422 const char *getStaticInitSectionSpecifier() const override { 423 return ".text.startup"; 424 } 425 }; 426 427 // NetBSD Target 428 template<typename Target> 429 class NetBSDTargetInfo : public OSTargetInfo<Target> { 430 protected: 431 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 432 MacroBuilder &Builder) const override { 433 // NetBSD defines; list based off of gcc output 434 Builder.defineMacro("__NetBSD__"); 435 Builder.defineMacro("__unix__"); 436 Builder.defineMacro("__ELF__"); 437 if (Opts.POSIXThreads) 438 Builder.defineMacro("_POSIX_THREADS"); 439 440 switch (Triple.getArch()) { 441 default: 442 break; 443 case llvm::Triple::arm: 444 case llvm::Triple::armeb: 445 case llvm::Triple::thumb: 446 case llvm::Triple::thumbeb: 447 Builder.defineMacro("__ARM_DWARF_EH__"); 448 break; 449 } 450 } 451 public: 452 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 453 this->UserLabelPrefix = ""; 454 this->MCountName = "_mcount"; 455 } 456 }; 457 458 // OpenBSD Target 459 template<typename Target> 460 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 461 protected: 462 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 463 MacroBuilder &Builder) const override { 464 // OpenBSD defines; list based off of gcc output 465 466 Builder.defineMacro("__OpenBSD__"); 467 DefineStd(Builder, "unix", Opts); 468 Builder.defineMacro("__ELF__"); 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 } 472 public: 473 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 474 this->UserLabelPrefix = ""; 475 this->TLSSupported = false; 476 477 switch (Triple.getArch()) { 478 default: 479 case llvm::Triple::x86: 480 case llvm::Triple::x86_64: 481 case llvm::Triple::arm: 482 case llvm::Triple::sparc: 483 this->MCountName = "__mcount"; 484 break; 485 case llvm::Triple::mips64: 486 case llvm::Triple::mips64el: 487 case llvm::Triple::ppc: 488 case llvm::Triple::sparcv9: 489 this->MCountName = "_mcount"; 490 break; 491 } 492 } 493 }; 494 495 // Bitrig Target 496 template<typename Target> 497 class BitrigTargetInfo : public OSTargetInfo<Target> { 498 protected: 499 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 500 MacroBuilder &Builder) const override { 501 // Bitrig defines; list based off of gcc output 502 503 Builder.defineMacro("__Bitrig__"); 504 DefineStd(Builder, "unix", Opts); 505 Builder.defineMacro("__ELF__"); 506 if (Opts.POSIXThreads) 507 Builder.defineMacro("_REENTRANT"); 508 509 switch (Triple.getArch()) { 510 default: 511 break; 512 case llvm::Triple::arm: 513 case llvm::Triple::armeb: 514 case llvm::Triple::thumb: 515 case llvm::Triple::thumbeb: 516 Builder.defineMacro("__ARM_DWARF_EH__"); 517 break; 518 } 519 } 520 public: 521 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 522 this->UserLabelPrefix = ""; 523 this->MCountName = "__mcount"; 524 } 525 }; 526 527 // PSP Target 528 template<typename Target> 529 class PSPTargetInfo : public OSTargetInfo<Target> { 530 protected: 531 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 532 MacroBuilder &Builder) const override { 533 // PSP defines; list based on the output of the pspdev gcc toolchain. 534 Builder.defineMacro("PSP"); 535 Builder.defineMacro("_PSP"); 536 Builder.defineMacro("__psp__"); 537 Builder.defineMacro("__ELF__"); 538 } 539 public: 540 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 541 this->UserLabelPrefix = ""; 542 } 543 }; 544 545 // PS3 PPU Target 546 template<typename Target> 547 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 548 protected: 549 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 550 MacroBuilder &Builder) const override { 551 // PS3 PPU defines. 552 Builder.defineMacro("__PPC__"); 553 Builder.defineMacro("__PPU__"); 554 Builder.defineMacro("__CELLOS_LV2__"); 555 Builder.defineMacro("__ELF__"); 556 Builder.defineMacro("__LP32__"); 557 Builder.defineMacro("_ARCH_PPC64"); 558 Builder.defineMacro("__powerpc64__"); 559 } 560 public: 561 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 562 this->UserLabelPrefix = ""; 563 this->LongWidth = this->LongAlign = 32; 564 this->PointerWidth = this->PointerAlign = 32; 565 this->IntMaxType = TargetInfo::SignedLongLong; 566 this->Int64Type = TargetInfo::SignedLongLong; 567 this->SizeType = TargetInfo::UnsignedInt; 568 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 569 } 570 }; 571 572 template <typename Target> 573 class PS4OSTargetInfo : public OSTargetInfo<Target> { 574 protected: 575 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 576 MacroBuilder &Builder) const override { 577 Builder.defineMacro("__FreeBSD__", "9"); 578 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 579 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 580 DefineStd(Builder, "unix", Opts); 581 Builder.defineMacro("__ELF__"); 582 Builder.defineMacro("__PS4__"); 583 } 584 public: 585 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 586 this->WCharType = this->UnsignedShort; 587 588 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 589 this->MaxTLSAlign = 256; 590 this->UserLabelPrefix = ""; 591 592 switch (Triple.getArch()) { 593 default: 594 case llvm::Triple::x86_64: 595 this->MCountName = ".mcount"; 596 break; 597 } 598 } 599 }; 600 601 // Solaris target 602 template<typename Target> 603 class SolarisTargetInfo : public OSTargetInfo<Target> { 604 protected: 605 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 606 MacroBuilder &Builder) const override { 607 DefineStd(Builder, "sun", Opts); 608 DefineStd(Builder, "unix", Opts); 609 Builder.defineMacro("__ELF__"); 610 Builder.defineMacro("__svr4__"); 611 Builder.defineMacro("__SVR4"); 612 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 613 // newer, but to 500 for everything else. feature_test.h has a check to 614 // ensure that you are not using C99 with an old version of X/Open or C89 615 // with a new version. 616 if (Opts.C99) 617 Builder.defineMacro("_XOPEN_SOURCE", "600"); 618 else 619 Builder.defineMacro("_XOPEN_SOURCE", "500"); 620 if (Opts.CPlusPlus) 621 Builder.defineMacro("__C99FEATURES__"); 622 Builder.defineMacro("_LARGEFILE_SOURCE"); 623 Builder.defineMacro("_LARGEFILE64_SOURCE"); 624 Builder.defineMacro("__EXTENSIONS__"); 625 Builder.defineMacro("_REENTRANT"); 626 } 627 public: 628 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 629 this->UserLabelPrefix = ""; 630 this->WCharType = this->SignedInt; 631 // FIXME: WIntType should be SignedLong 632 } 633 }; 634 635 // Windows target 636 template<typename Target> 637 class WindowsTargetInfo : public OSTargetInfo<Target> { 638 protected: 639 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 640 MacroBuilder &Builder) const override { 641 Builder.defineMacro("_WIN32"); 642 } 643 void getVisualStudioDefines(const LangOptions &Opts, 644 MacroBuilder &Builder) const { 645 if (Opts.CPlusPlus) { 646 if (Opts.RTTIData) 647 Builder.defineMacro("_CPPRTTI"); 648 649 if (Opts.CXXExceptions) 650 Builder.defineMacro("_CPPUNWIND"); 651 } 652 653 if (Opts.Bool) 654 Builder.defineMacro("__BOOL_DEFINED"); 655 656 if (!Opts.CharIsSigned) 657 Builder.defineMacro("_CHAR_UNSIGNED"); 658 659 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 660 // but it works for now. 661 if (Opts.POSIXThreads) 662 Builder.defineMacro("_MT"); 663 664 if (Opts.MSCompatibilityVersion) { 665 Builder.defineMacro("_MSC_VER", 666 Twine(Opts.MSCompatibilityVersion / 100000)); 667 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 668 // FIXME We cannot encode the revision information into 32-bits 669 Builder.defineMacro("_MSC_BUILD", Twine(1)); 670 671 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 672 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 673 } 674 675 if (Opts.MicrosoftExt) { 676 Builder.defineMacro("_MSC_EXTENSIONS"); 677 678 if (Opts.CPlusPlus11) { 679 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 680 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 681 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 682 } 683 } 684 685 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 686 } 687 688 public: 689 WindowsTargetInfo(const llvm::Triple &Triple) 690 : OSTargetInfo<Target>(Triple) {} 691 }; 692 693 template <typename Target> 694 class NaClTargetInfo : public OSTargetInfo<Target> { 695 protected: 696 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 697 MacroBuilder &Builder) const override { 698 if (Opts.POSIXThreads) 699 Builder.defineMacro("_REENTRANT"); 700 if (Opts.CPlusPlus) 701 Builder.defineMacro("_GNU_SOURCE"); 702 703 DefineStd(Builder, "unix", Opts); 704 Builder.defineMacro("__ELF__"); 705 Builder.defineMacro("__native_client__"); 706 } 707 708 public: 709 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 710 this->UserLabelPrefix = ""; 711 this->LongAlign = 32; 712 this->LongWidth = 32; 713 this->PointerAlign = 32; 714 this->PointerWidth = 32; 715 this->IntMaxType = TargetInfo::SignedLongLong; 716 this->Int64Type = TargetInfo::SignedLongLong; 717 this->DoubleAlign = 64; 718 this->LongDoubleWidth = 64; 719 this->LongDoubleAlign = 64; 720 this->LongLongWidth = 64; 721 this->LongLongAlign = 64; 722 this->SizeType = TargetInfo::UnsignedInt; 723 this->PtrDiffType = TargetInfo::SignedInt; 724 this->IntPtrType = TargetInfo::SignedInt; 725 // RegParmMax is inherited from the underlying architecture 726 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 727 if (Triple.getArch() == llvm::Triple::arm) { 728 // Handled in ARM's setABI(). 729 } else if (Triple.getArch() == llvm::Triple::x86) { 730 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 731 } else if (Triple.getArch() == llvm::Triple::x86_64) { 732 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 733 } else if (Triple.getArch() == llvm::Triple::mipsel) { 734 // Handled on mips' setDataLayoutString. 735 } else { 736 assert(Triple.getArch() == llvm::Triple::le32); 737 this->DataLayoutString = "e-p:32:32-i64:64"; 738 } 739 } 740 }; 741 742 // WebAssembly target 743 template <typename Target> 744 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 745 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 746 MacroBuilder &Builder) const final { 747 // A common platform macro. 748 if (Opts.POSIXThreads) 749 Builder.defineMacro("_REENTRANT"); 750 // Follow g++ convention and predefine _GNU_SOURCE for C++. 751 if (Opts.CPlusPlus) 752 Builder.defineMacro("_GNU_SOURCE"); 753 } 754 755 // As an optimization, group static init code together in a section. 756 const char *getStaticInitSectionSpecifier() const final { 757 return ".text.__startup"; 758 } 759 760 public: 761 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 762 : OSTargetInfo<Target>(Triple) { 763 this->MCountName = "__mcount"; 764 this->UserLabelPrefix = ""; 765 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 766 } 767 }; 768 769 //===----------------------------------------------------------------------===// 770 // Specific target implementations. 771 //===----------------------------------------------------------------------===// 772 773 // PPC abstract base class 774 class PPCTargetInfo : public TargetInfo { 775 static const Builtin::Info BuiltinInfo[]; 776 static const char * const GCCRegNames[]; 777 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 778 std::string CPU; 779 780 // Target cpu features. 781 bool HasVSX; 782 bool HasP8Vector; 783 bool HasP8Crypto; 784 bool HasDirectMove; 785 bool HasQPX; 786 bool HasHTM; 787 bool HasBPERMD; 788 bool HasExtDiv; 789 790 protected: 791 std::string ABI; 792 793 public: 794 PPCTargetInfo(const llvm::Triple &Triple) 795 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 796 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 797 HasBPERMD(false), HasExtDiv(false) { 798 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 799 SimdDefaultAlign = 128; 800 LongDoubleWidth = LongDoubleAlign = 128; 801 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 802 } 803 804 /// \brief Flags for architecture specific defines. 805 typedef enum { 806 ArchDefineNone = 0, 807 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 808 ArchDefinePpcgr = 1 << 1, 809 ArchDefinePpcsq = 1 << 2, 810 ArchDefine440 = 1 << 3, 811 ArchDefine603 = 1 << 4, 812 ArchDefine604 = 1 << 5, 813 ArchDefinePwr4 = 1 << 6, 814 ArchDefinePwr5 = 1 << 7, 815 ArchDefinePwr5x = 1 << 8, 816 ArchDefinePwr6 = 1 << 9, 817 ArchDefinePwr6x = 1 << 10, 818 ArchDefinePwr7 = 1 << 11, 819 ArchDefinePwr8 = 1 << 12, 820 ArchDefineA2 = 1 << 13, 821 ArchDefineA2q = 1 << 14 822 } ArchDefineTypes; 823 824 // Note: GCC recognizes the following additional cpus: 825 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 826 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 827 // titan, rs64. 828 bool setCPU(const std::string &Name) override { 829 bool CPUKnown = llvm::StringSwitch<bool>(Name) 830 .Case("generic", true) 831 .Case("440", true) 832 .Case("450", true) 833 .Case("601", true) 834 .Case("602", true) 835 .Case("603", true) 836 .Case("603e", true) 837 .Case("603ev", true) 838 .Case("604", true) 839 .Case("604e", true) 840 .Case("620", true) 841 .Case("630", true) 842 .Case("g3", true) 843 .Case("7400", true) 844 .Case("g4", true) 845 .Case("7450", true) 846 .Case("g4+", true) 847 .Case("750", true) 848 .Case("970", true) 849 .Case("g5", true) 850 .Case("a2", true) 851 .Case("a2q", true) 852 .Case("e500mc", true) 853 .Case("e5500", true) 854 .Case("power3", true) 855 .Case("pwr3", true) 856 .Case("power4", true) 857 .Case("pwr4", true) 858 .Case("power5", true) 859 .Case("pwr5", true) 860 .Case("power5x", true) 861 .Case("pwr5x", true) 862 .Case("power6", true) 863 .Case("pwr6", true) 864 .Case("power6x", true) 865 .Case("pwr6x", true) 866 .Case("power7", true) 867 .Case("pwr7", true) 868 .Case("power8", true) 869 .Case("pwr8", true) 870 .Case("powerpc", true) 871 .Case("ppc", true) 872 .Case("powerpc64", true) 873 .Case("ppc64", true) 874 .Case("powerpc64le", true) 875 .Case("ppc64le", true) 876 .Default(false); 877 878 if (CPUKnown) 879 CPU = Name; 880 881 return CPUKnown; 882 } 883 884 885 StringRef getABI() const override { return ABI; } 886 887 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 888 return llvm::makeArrayRef(BuiltinInfo, 889 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 890 } 891 892 bool isCLZForZeroUndef() const override { return false; } 893 894 void getTargetDefines(const LangOptions &Opts, 895 MacroBuilder &Builder) const override; 896 897 bool 898 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 899 StringRef CPU, 900 const std::vector<std::string> &FeaturesVec) const override; 901 902 bool handleTargetFeatures(std::vector<std::string> &Features, 903 DiagnosticsEngine &Diags) override; 904 bool hasFeature(StringRef Feature) const override; 905 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 906 bool Enabled) const override; 907 908 ArrayRef<const char *> getGCCRegNames() const override; 909 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 910 bool validateAsmConstraint(const char *&Name, 911 TargetInfo::ConstraintInfo &Info) const override { 912 switch (*Name) { 913 default: return false; 914 case 'O': // Zero 915 break; 916 case 'b': // Base register 917 case 'f': // Floating point register 918 Info.setAllowsRegister(); 919 break; 920 // FIXME: The following are added to allow parsing. 921 // I just took a guess at what the actions should be. 922 // Also, is more specific checking needed? I.e. specific registers? 923 case 'd': // Floating point register (containing 64-bit value) 924 case 'v': // Altivec vector register 925 Info.setAllowsRegister(); 926 break; 927 case 'w': 928 switch (Name[1]) { 929 case 'd':// VSX vector register to hold vector double data 930 case 'f':// VSX vector register to hold vector float data 931 case 's':// VSX vector register to hold scalar float data 932 case 'a':// Any VSX register 933 case 'c':// An individual CR bit 934 break; 935 default: 936 return false; 937 } 938 Info.setAllowsRegister(); 939 Name++; // Skip over 'w'. 940 break; 941 case 'h': // `MQ', `CTR', or `LINK' register 942 case 'q': // `MQ' register 943 case 'c': // `CTR' register 944 case 'l': // `LINK' register 945 case 'x': // `CR' register (condition register) number 0 946 case 'y': // `CR' register (condition register) 947 case 'z': // `XER[CA]' carry bit (part of the XER register) 948 Info.setAllowsRegister(); 949 break; 950 case 'I': // Signed 16-bit constant 951 case 'J': // Unsigned 16-bit constant shifted left 16 bits 952 // (use `L' instead for SImode constants) 953 case 'K': // Unsigned 16-bit constant 954 case 'L': // Signed 16-bit constant shifted left 16 bits 955 case 'M': // Constant larger than 31 956 case 'N': // Exact power of 2 957 case 'P': // Constant whose negation is a signed 16-bit constant 958 case 'G': // Floating point constant that can be loaded into a 959 // register with one instruction per word 960 case 'H': // Integer/Floating point constant that can be loaded 961 // into a register using three instructions 962 break; 963 case 'm': // Memory operand. Note that on PowerPC targets, m can 964 // include addresses that update the base register. It 965 // is therefore only safe to use `m' in an asm statement 966 // if that asm statement accesses the operand exactly once. 967 // The asm statement must also use `%U<opno>' as a 968 // placeholder for the "update" flag in the corresponding 969 // load or store instruction. For example: 970 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 971 // is correct but: 972 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 973 // is not. Use es rather than m if you don't want the base 974 // register to be updated. 975 case 'e': 976 if (Name[1] != 's') 977 return false; 978 // es: A "stable" memory operand; that is, one which does not 979 // include any automodification of the base register. Unlike 980 // `m', this constraint can be used in asm statements that 981 // might access the operand several times, or that might not 982 // access it at all. 983 Info.setAllowsMemory(); 984 Name++; // Skip over 'e'. 985 break; 986 case 'Q': // Memory operand that is an offset from a register (it is 987 // usually better to use `m' or `es' in asm statements) 988 case 'Z': // Memory operand that is an indexed or indirect from a 989 // register (it is usually better to use `m' or `es' in 990 // asm statements) 991 Info.setAllowsMemory(); 992 Info.setAllowsRegister(); 993 break; 994 case 'R': // AIX TOC entry 995 case 'a': // Address operand that is an indexed or indirect from a 996 // register (`p' is preferable for asm statements) 997 case 'S': // Constant suitable as a 64-bit mask operand 998 case 'T': // Constant suitable as a 32-bit mask operand 999 case 'U': // System V Release 4 small data area reference 1000 case 't': // AND masks that can be performed by two rldic{l, r} 1001 // instructions 1002 case 'W': // Vector constant that does not require memory 1003 case 'j': // Vector constant that is all zeros. 1004 break; 1005 // End FIXME. 1006 } 1007 return true; 1008 } 1009 std::string convertConstraint(const char *&Constraint) const override { 1010 std::string R; 1011 switch (*Constraint) { 1012 case 'e': 1013 case 'w': 1014 // Two-character constraint; add "^" hint for later parsing. 1015 R = std::string("^") + std::string(Constraint, 2); 1016 Constraint++; 1017 break; 1018 default: 1019 return TargetInfo::convertConstraint(Constraint); 1020 } 1021 return R; 1022 } 1023 const char *getClobbers() const override { 1024 return ""; 1025 } 1026 int getEHDataRegisterNumber(unsigned RegNo) const override { 1027 if (RegNo == 0) return 3; 1028 if (RegNo == 1) return 4; 1029 return -1; 1030 } 1031 1032 bool hasSjLjLowering() const override { 1033 return true; 1034 } 1035 1036 bool useFloat128ManglingForLongDouble() const override { 1037 return LongDoubleWidth == 128 && 1038 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1039 getTriple().isOSBinFormatELF(); 1040 } 1041 }; 1042 1043 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1044 #define BUILTIN(ID, TYPE, ATTRS) \ 1045 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1046 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1047 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1048 #include "clang/Basic/BuiltinsPPC.def" 1049 }; 1050 1051 /// handleTargetFeatures - Perform initialization based on the user 1052 /// configured set of features. 1053 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1054 DiagnosticsEngine &Diags) { 1055 for (const auto &Feature : Features) { 1056 if (Feature == "+vsx") { 1057 HasVSX = true; 1058 } else if (Feature == "+bpermd") { 1059 HasBPERMD = true; 1060 } else if (Feature == "+extdiv") { 1061 HasExtDiv = true; 1062 } else if (Feature == "+power8-vector") { 1063 HasP8Vector = true; 1064 } else if (Feature == "+crypto") { 1065 HasP8Crypto = true; 1066 } else if (Feature == "+direct-move") { 1067 HasDirectMove = true; 1068 } else if (Feature == "+qpx") { 1069 HasQPX = true; 1070 } else if (Feature == "+htm") { 1071 HasHTM = true; 1072 } 1073 // TODO: Finish this list and add an assert that we've handled them 1074 // all. 1075 } 1076 1077 return true; 1078 } 1079 1080 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1081 /// #defines that are not tied to a specific subtarget. 1082 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 // Target identification. 1085 Builder.defineMacro("__ppc__"); 1086 Builder.defineMacro("__PPC__"); 1087 Builder.defineMacro("_ARCH_PPC"); 1088 Builder.defineMacro("__powerpc__"); 1089 Builder.defineMacro("__POWERPC__"); 1090 if (PointerWidth == 64) { 1091 Builder.defineMacro("_ARCH_PPC64"); 1092 Builder.defineMacro("__powerpc64__"); 1093 Builder.defineMacro("__ppc64__"); 1094 Builder.defineMacro("__PPC64__"); 1095 } 1096 1097 // Target properties. 1098 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1099 Builder.defineMacro("_LITTLE_ENDIAN"); 1100 } else { 1101 if (getTriple().getOS() != llvm::Triple::NetBSD && 1102 getTriple().getOS() != llvm::Triple::OpenBSD) 1103 Builder.defineMacro("_BIG_ENDIAN"); 1104 } 1105 1106 // ABI options. 1107 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1108 Builder.defineMacro("_CALL_ELF", "1"); 1109 if (ABI == "elfv2") 1110 Builder.defineMacro("_CALL_ELF", "2"); 1111 1112 // Subtarget options. 1113 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1114 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1115 1116 // FIXME: Should be controlled by command line option. 1117 if (LongDoubleWidth == 128) 1118 Builder.defineMacro("__LONG_DOUBLE_128__"); 1119 1120 if (Opts.AltiVec) { 1121 Builder.defineMacro("__VEC__", "10206"); 1122 Builder.defineMacro("__ALTIVEC__"); 1123 } 1124 1125 // CPU identification. 1126 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1127 .Case("440", ArchDefineName) 1128 .Case("450", ArchDefineName | ArchDefine440) 1129 .Case("601", ArchDefineName) 1130 .Case("602", ArchDefineName | ArchDefinePpcgr) 1131 .Case("603", ArchDefineName | ArchDefinePpcgr) 1132 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1133 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1134 .Case("604", ArchDefineName | ArchDefinePpcgr) 1135 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1136 .Case("620", ArchDefineName | ArchDefinePpcgr) 1137 .Case("630", ArchDefineName | ArchDefinePpcgr) 1138 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1139 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1140 .Case("750", ArchDefineName | ArchDefinePpcgr) 1141 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1142 | ArchDefinePpcsq) 1143 .Case("a2", ArchDefineA2) 1144 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1145 .Case("pwr3", ArchDefinePpcgr) 1146 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Case("power3", ArchDefinePpcgr) 1163 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1164 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1165 | ArchDefinePpcsq) 1166 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1167 | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1169 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1170 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1171 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1172 | ArchDefinePpcsq) 1173 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1174 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1175 | ArchDefinePpcgr | ArchDefinePpcsq) 1176 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1177 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1178 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1179 .Default(ArchDefineNone); 1180 1181 if (defs & ArchDefineName) 1182 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1183 if (defs & ArchDefinePpcgr) 1184 Builder.defineMacro("_ARCH_PPCGR"); 1185 if (defs & ArchDefinePpcsq) 1186 Builder.defineMacro("_ARCH_PPCSQ"); 1187 if (defs & ArchDefine440) 1188 Builder.defineMacro("_ARCH_440"); 1189 if (defs & ArchDefine603) 1190 Builder.defineMacro("_ARCH_603"); 1191 if (defs & ArchDefine604) 1192 Builder.defineMacro("_ARCH_604"); 1193 if (defs & ArchDefinePwr4) 1194 Builder.defineMacro("_ARCH_PWR4"); 1195 if (defs & ArchDefinePwr5) 1196 Builder.defineMacro("_ARCH_PWR5"); 1197 if (defs & ArchDefinePwr5x) 1198 Builder.defineMacro("_ARCH_PWR5X"); 1199 if (defs & ArchDefinePwr6) 1200 Builder.defineMacro("_ARCH_PWR6"); 1201 if (defs & ArchDefinePwr6x) 1202 Builder.defineMacro("_ARCH_PWR6X"); 1203 if (defs & ArchDefinePwr7) 1204 Builder.defineMacro("_ARCH_PWR7"); 1205 if (defs & ArchDefinePwr8) 1206 Builder.defineMacro("_ARCH_PWR8"); 1207 if (defs & ArchDefineA2) 1208 Builder.defineMacro("_ARCH_A2"); 1209 if (defs & ArchDefineA2q) { 1210 Builder.defineMacro("_ARCH_A2Q"); 1211 Builder.defineMacro("_ARCH_QP"); 1212 } 1213 1214 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1215 Builder.defineMacro("__bg__"); 1216 Builder.defineMacro("__THW_BLUEGENE__"); 1217 Builder.defineMacro("__bgq__"); 1218 Builder.defineMacro("__TOS_BGQ__"); 1219 } 1220 1221 if (HasVSX) 1222 Builder.defineMacro("__VSX__"); 1223 if (HasP8Vector) 1224 Builder.defineMacro("__POWER8_VECTOR__"); 1225 if (HasP8Crypto) 1226 Builder.defineMacro("__CRYPTO__"); 1227 if (HasHTM) 1228 Builder.defineMacro("__HTM__"); 1229 1230 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1231 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1232 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1233 if (PointerWidth == 64) 1234 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1235 1236 // FIXME: The following are not yet generated here by Clang, but are 1237 // generated by GCC: 1238 // 1239 // _SOFT_FLOAT_ 1240 // __RECIP_PRECISION__ 1241 // __APPLE_ALTIVEC__ 1242 // __RECIP__ 1243 // __RECIPF__ 1244 // __RSQRTE__ 1245 // __RSQRTEF__ 1246 // _SOFT_DOUBLE_ 1247 // __NO_LWSYNC__ 1248 // __HAVE_BSWAP__ 1249 // __LONGDOUBLE128 1250 // __CMODEL_MEDIUM__ 1251 // __CMODEL_LARGE__ 1252 // _CALL_SYSV 1253 // _CALL_DARWIN 1254 // __NO_FPRS__ 1255 } 1256 1257 // Handle explicit options being passed to the compiler here: if we've 1258 // explicitly turned off vsx and turned on power8-vector or direct-move then 1259 // go ahead and error since the customer has expressed a somewhat incompatible 1260 // set of options. 1261 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1262 const std::vector<std::string> &FeaturesVec) { 1263 1264 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1265 FeaturesVec.end()) { 1266 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1267 FeaturesVec.end()) { 1268 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1269 << "-mno-vsx"; 1270 return false; 1271 } 1272 1273 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1274 FeaturesVec.end()) { 1275 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1276 << "-mno-vsx"; 1277 return false; 1278 } 1279 } 1280 1281 return true; 1282 } 1283 1284 bool PPCTargetInfo::initFeatureMap( 1285 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1286 const std::vector<std::string> &FeaturesVec) const { 1287 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1288 .Case("7400", true) 1289 .Case("g4", true) 1290 .Case("7450", true) 1291 .Case("g4+", true) 1292 .Case("970", true) 1293 .Case("g5", true) 1294 .Case("pwr6", true) 1295 .Case("pwr7", true) 1296 .Case("pwr8", true) 1297 .Case("ppc64", true) 1298 .Case("ppc64le", true) 1299 .Default(false); 1300 1301 Features["qpx"] = (CPU == "a2q"); 1302 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1303 .Case("ppc64le", true) 1304 .Case("pwr8", true) 1305 .Default(false); 1306 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1307 .Case("ppc64le", true) 1308 .Case("pwr8", true) 1309 .Default(false); 1310 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1311 .Case("ppc64le", true) 1312 .Case("pwr8", true) 1313 .Case("pwr7", true) 1314 .Default(false); 1315 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1316 .Case("ppc64le", true) 1317 .Case("pwr8", true) 1318 .Case("pwr7", true) 1319 .Default(false); 1320 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1321 .Case("ppc64le", true) 1322 .Case("pwr8", true) 1323 .Default(false); 1324 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1325 .Case("ppc64le", true) 1326 .Case("pwr8", true) 1327 .Case("pwr7", true) 1328 .Default(false); 1329 1330 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1331 return false; 1332 1333 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1334 } 1335 1336 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1337 return llvm::StringSwitch<bool>(Feature) 1338 .Case("powerpc", true) 1339 .Case("vsx", HasVSX) 1340 .Case("power8-vector", HasP8Vector) 1341 .Case("crypto", HasP8Crypto) 1342 .Case("direct-move", HasDirectMove) 1343 .Case("qpx", HasQPX) 1344 .Case("htm", HasHTM) 1345 .Case("bpermd", HasBPERMD) 1346 .Case("extdiv", HasExtDiv) 1347 .Default(false); 1348 } 1349 1350 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1351 StringRef Name, bool Enabled) const { 1352 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1353 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1354 // incompatible options. 1355 if (Enabled) { 1356 if (Name == "vsx") { 1357 Features[Name] = true; 1358 } else if (Name == "direct-move") { 1359 Features[Name] = Features["vsx"] = true; 1360 } else if (Name == "power8-vector") { 1361 Features[Name] = Features["vsx"] = true; 1362 } else { 1363 Features[Name] = true; 1364 } 1365 } else { 1366 if (Name == "vsx") { 1367 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1368 false; 1369 } else { 1370 Features[Name] = false; 1371 } 1372 } 1373 } 1374 1375 const char * const PPCTargetInfo::GCCRegNames[] = { 1376 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1377 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1378 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1379 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1380 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1381 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1382 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1383 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1384 "mq", "lr", "ctr", "ap", 1385 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1386 "xer", 1387 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1388 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1389 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1390 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1391 "vrsave", "vscr", 1392 "spe_acc", "spefscr", 1393 "sfp" 1394 }; 1395 1396 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1397 return llvm::makeArrayRef(GCCRegNames); 1398 } 1399 1400 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1401 // While some of these aliases do map to different registers 1402 // they still share the same register name. 1403 { { "0" }, "r0" }, 1404 { { "1"}, "r1" }, 1405 { { "2" }, "r2" }, 1406 { { "3" }, "r3" }, 1407 { { "4" }, "r4" }, 1408 { { "5" }, "r5" }, 1409 { { "6" }, "r6" }, 1410 { { "7" }, "r7" }, 1411 { { "8" }, "r8" }, 1412 { { "9" }, "r9" }, 1413 { { "10" }, "r10" }, 1414 { { "11" }, "r11" }, 1415 { { "12" }, "r12" }, 1416 { { "13" }, "r13" }, 1417 { { "14" }, "r14" }, 1418 { { "15" }, "r15" }, 1419 { { "16" }, "r16" }, 1420 { { "17" }, "r17" }, 1421 { { "18" }, "r18" }, 1422 { { "19" }, "r19" }, 1423 { { "20" }, "r20" }, 1424 { { "21" }, "r21" }, 1425 { { "22" }, "r22" }, 1426 { { "23" }, "r23" }, 1427 { { "24" }, "r24" }, 1428 { { "25" }, "r25" }, 1429 { { "26" }, "r26" }, 1430 { { "27" }, "r27" }, 1431 { { "28" }, "r28" }, 1432 { { "29" }, "r29" }, 1433 { { "30" }, "r30" }, 1434 { { "31" }, "r31" }, 1435 { { "fr0" }, "f0" }, 1436 { { "fr1" }, "f1" }, 1437 { { "fr2" }, "f2" }, 1438 { { "fr3" }, "f3" }, 1439 { { "fr4" }, "f4" }, 1440 { { "fr5" }, "f5" }, 1441 { { "fr6" }, "f6" }, 1442 { { "fr7" }, "f7" }, 1443 { { "fr8" }, "f8" }, 1444 { { "fr9" }, "f9" }, 1445 { { "fr10" }, "f10" }, 1446 { { "fr11" }, "f11" }, 1447 { { "fr12" }, "f12" }, 1448 { { "fr13" }, "f13" }, 1449 { { "fr14" }, "f14" }, 1450 { { "fr15" }, "f15" }, 1451 { { "fr16" }, "f16" }, 1452 { { "fr17" }, "f17" }, 1453 { { "fr18" }, "f18" }, 1454 { { "fr19" }, "f19" }, 1455 { { "fr20" }, "f20" }, 1456 { { "fr21" }, "f21" }, 1457 { { "fr22" }, "f22" }, 1458 { { "fr23" }, "f23" }, 1459 { { "fr24" }, "f24" }, 1460 { { "fr25" }, "f25" }, 1461 { { "fr26" }, "f26" }, 1462 { { "fr27" }, "f27" }, 1463 { { "fr28" }, "f28" }, 1464 { { "fr29" }, "f29" }, 1465 { { "fr30" }, "f30" }, 1466 { { "fr31" }, "f31" }, 1467 { { "cc" }, "cr0" }, 1468 }; 1469 1470 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1471 return llvm::makeArrayRef(GCCRegAliases); 1472 } 1473 1474 class PPC32TargetInfo : public PPCTargetInfo { 1475 public: 1476 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1477 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1478 1479 switch (getTriple().getOS()) { 1480 case llvm::Triple::Linux: 1481 case llvm::Triple::FreeBSD: 1482 case llvm::Triple::NetBSD: 1483 SizeType = UnsignedInt; 1484 PtrDiffType = SignedInt; 1485 IntPtrType = SignedInt; 1486 break; 1487 default: 1488 break; 1489 } 1490 1491 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1492 LongDoubleWidth = LongDoubleAlign = 64; 1493 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1494 } 1495 1496 // PPC32 supports atomics up to 4 bytes. 1497 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1498 } 1499 1500 BuiltinVaListKind getBuiltinVaListKind() const override { 1501 // This is the ELF definition, and is overridden by the Darwin sub-target 1502 return TargetInfo::PowerABIBuiltinVaList; 1503 } 1504 }; 1505 1506 // Note: ABI differences may eventually require us to have a separate 1507 // TargetInfo for little endian. 1508 class PPC64TargetInfo : public PPCTargetInfo { 1509 public: 1510 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1511 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1512 IntMaxType = SignedLong; 1513 Int64Type = SignedLong; 1514 1515 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1516 DataLayoutString = "e-m:e-i64:64-n32:64"; 1517 ABI = "elfv2"; 1518 } else { 1519 DataLayoutString = "E-m:e-i64:64-n32:64"; 1520 ABI = "elfv1"; 1521 } 1522 1523 switch (getTriple().getOS()) { 1524 case llvm::Triple::FreeBSD: 1525 LongDoubleWidth = LongDoubleAlign = 64; 1526 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1527 break; 1528 case llvm::Triple::NetBSD: 1529 IntMaxType = SignedLongLong; 1530 Int64Type = SignedLongLong; 1531 break; 1532 default: 1533 break; 1534 } 1535 1536 // PPC64 supports atomics up to 8 bytes. 1537 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1538 } 1539 BuiltinVaListKind getBuiltinVaListKind() const override { 1540 return TargetInfo::CharPtrBuiltinVaList; 1541 } 1542 // PPC64 Linux-specific ABI options. 1543 bool setABI(const std::string &Name) override { 1544 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1545 ABI = Name; 1546 return true; 1547 } 1548 return false; 1549 } 1550 }; 1551 1552 class DarwinPPC32TargetInfo : 1553 public DarwinTargetInfo<PPC32TargetInfo> { 1554 public: 1555 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1556 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1557 HasAlignMac68kSupport = true; 1558 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1559 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1560 LongLongAlign = 32; 1561 SuitableAlign = 128; 1562 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1563 } 1564 BuiltinVaListKind getBuiltinVaListKind() const override { 1565 return TargetInfo::CharPtrBuiltinVaList; 1566 } 1567 }; 1568 1569 class DarwinPPC64TargetInfo : 1570 public DarwinTargetInfo<PPC64TargetInfo> { 1571 public: 1572 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1573 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1574 HasAlignMac68kSupport = true; 1575 SuitableAlign = 128; 1576 DataLayoutString = "E-m:o-i64:64-n32:64"; 1577 } 1578 }; 1579 1580 static const unsigned NVPTXAddrSpaceMap[] = { 1581 1, // opencl_global 1582 3, // opencl_local 1583 4, // opencl_constant 1584 // FIXME: generic has to be added to the target 1585 0, // opencl_generic 1586 1, // cuda_device 1587 4, // cuda_constant 1588 3, // cuda_shared 1589 }; 1590 1591 class NVPTXTargetInfo : public TargetInfo { 1592 static const char *const GCCRegNames[]; 1593 static const Builtin::Info BuiltinInfo[]; 1594 1595 // The GPU profiles supported by the NVPTX backend 1596 enum GPUKind { 1597 GK_NONE, 1598 GK_SM20, 1599 GK_SM21, 1600 GK_SM30, 1601 GK_SM35, 1602 GK_SM37, 1603 } GPU; 1604 1605 public: 1606 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1607 BigEndian = false; 1608 TLSSupported = false; 1609 LongWidth = LongAlign = 64; 1610 AddrSpaceMap = &NVPTXAddrSpaceMap; 1611 UseAddrSpaceMapMangling = true; 1612 // Define available target features 1613 // These must be defined in sorted order! 1614 NoAsmVariants = true; 1615 // Set the default GPU to sm20 1616 GPU = GK_SM20; 1617 } 1618 void getTargetDefines(const LangOptions &Opts, 1619 MacroBuilder &Builder) const override { 1620 Builder.defineMacro("__PTX__"); 1621 Builder.defineMacro("__NVPTX__"); 1622 if (Opts.CUDAIsDevice) { 1623 // Set __CUDA_ARCH__ for the GPU specified. 1624 std::string CUDAArchCode; 1625 switch (GPU) { 1626 case GK_SM20: 1627 CUDAArchCode = "200"; 1628 break; 1629 case GK_SM21: 1630 CUDAArchCode = "210"; 1631 break; 1632 case GK_SM30: 1633 CUDAArchCode = "300"; 1634 break; 1635 case GK_SM35: 1636 CUDAArchCode = "350"; 1637 break; 1638 case GK_SM37: 1639 CUDAArchCode = "370"; 1640 break; 1641 default: 1642 llvm_unreachable("Unhandled target CPU"); 1643 } 1644 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1645 } 1646 } 1647 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1648 return llvm::makeArrayRef(BuiltinInfo, 1649 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1650 } 1651 bool hasFeature(StringRef Feature) const override { 1652 return Feature == "ptx" || Feature == "nvptx"; 1653 } 1654 1655 ArrayRef<const char *> getGCCRegNames() const override; 1656 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1657 // No aliases. 1658 return None; 1659 } 1660 bool validateAsmConstraint(const char *&Name, 1661 TargetInfo::ConstraintInfo &Info) const override { 1662 switch (*Name) { 1663 default: 1664 return false; 1665 case 'c': 1666 case 'h': 1667 case 'r': 1668 case 'l': 1669 case 'f': 1670 case 'd': 1671 Info.setAllowsRegister(); 1672 return true; 1673 } 1674 } 1675 const char *getClobbers() const override { 1676 // FIXME: Is this really right? 1677 return ""; 1678 } 1679 BuiltinVaListKind getBuiltinVaListKind() const override { 1680 // FIXME: implement 1681 return TargetInfo::CharPtrBuiltinVaList; 1682 } 1683 bool setCPU(const std::string &Name) override { 1684 GPU = llvm::StringSwitch<GPUKind>(Name) 1685 .Case("sm_20", GK_SM20) 1686 .Case("sm_21", GK_SM21) 1687 .Case("sm_30", GK_SM30) 1688 .Case("sm_35", GK_SM35) 1689 .Case("sm_37", GK_SM37) 1690 .Default(GK_NONE); 1691 1692 return GPU != GK_NONE; 1693 } 1694 }; 1695 1696 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1697 #define BUILTIN(ID, TYPE, ATTRS) \ 1698 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1699 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1700 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1701 #include "clang/Basic/BuiltinsNVPTX.def" 1702 }; 1703 1704 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1705 1706 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1707 return llvm::makeArrayRef(GCCRegNames); 1708 } 1709 1710 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1711 public: 1712 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1713 LongWidth = LongAlign = 32; 1714 PointerWidth = PointerAlign = 32; 1715 SizeType = TargetInfo::UnsignedInt; 1716 PtrDiffType = TargetInfo::SignedInt; 1717 IntPtrType = TargetInfo::SignedInt; 1718 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1719 } 1720 }; 1721 1722 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1723 public: 1724 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1725 PointerWidth = PointerAlign = 64; 1726 SizeType = TargetInfo::UnsignedLong; 1727 PtrDiffType = TargetInfo::SignedLong; 1728 IntPtrType = TargetInfo::SignedLong; 1729 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1730 } 1731 }; 1732 1733 static const unsigned AMDGPUAddrSpaceMap[] = { 1734 1, // opencl_global 1735 3, // opencl_local 1736 2, // opencl_constant 1737 4, // opencl_generic 1738 1, // cuda_device 1739 2, // cuda_constant 1740 3 // cuda_shared 1741 }; 1742 1743 // If you edit the description strings, make sure you update 1744 // getPointerWidthV(). 1745 1746 static const char *const DataLayoutStringR600 = 1747 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1748 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1749 1750 static const char *const DataLayoutStringR600DoubleOps = 1751 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1752 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1753 1754 static const char *const DataLayoutStringSI = 1755 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1756 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1757 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1758 1759 class AMDGPUTargetInfo : public TargetInfo { 1760 static const Builtin::Info BuiltinInfo[]; 1761 static const char * const GCCRegNames[]; 1762 1763 /// \brief The GPU profiles supported by the AMDGPU target. 1764 enum GPUKind { 1765 GK_NONE, 1766 GK_R600, 1767 GK_R600_DOUBLE_OPS, 1768 GK_R700, 1769 GK_R700_DOUBLE_OPS, 1770 GK_EVERGREEN, 1771 GK_EVERGREEN_DOUBLE_OPS, 1772 GK_NORTHERN_ISLANDS, 1773 GK_CAYMAN, 1774 GK_SOUTHERN_ISLANDS, 1775 GK_SEA_ISLANDS, 1776 GK_VOLCANIC_ISLANDS 1777 } GPU; 1778 1779 bool hasFP64:1; 1780 bool hasFMAF:1; 1781 bool hasLDEXPF:1; 1782 1783 public: 1784 AMDGPUTargetInfo(const llvm::Triple &Triple) 1785 : TargetInfo(Triple) { 1786 1787 if (Triple.getArch() == llvm::Triple::amdgcn) { 1788 DataLayoutString = DataLayoutStringSI; 1789 GPU = GK_SOUTHERN_ISLANDS; 1790 hasFP64 = true; 1791 hasFMAF = true; 1792 hasLDEXPF = true; 1793 } else { 1794 DataLayoutString = DataLayoutStringR600; 1795 GPU = GK_R600; 1796 hasFP64 = false; 1797 hasFMAF = false; 1798 hasLDEXPF = false; 1799 } 1800 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1801 UseAddrSpaceMapMangling = true; 1802 } 1803 1804 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1805 if (GPU <= GK_CAYMAN) 1806 return 32; 1807 1808 switch(AddrSpace) { 1809 default: 1810 return 64; 1811 case 0: 1812 case 3: 1813 case 5: 1814 return 32; 1815 } 1816 } 1817 1818 const char * getClobbers() const override { 1819 return ""; 1820 } 1821 1822 ArrayRef<const char *> getGCCRegNames() const override; 1823 1824 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1825 return None; 1826 } 1827 1828 bool validateAsmConstraint(const char *&Name, 1829 TargetInfo::ConstraintInfo &info) const override { 1830 return true; 1831 } 1832 1833 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1834 return llvm::makeArrayRef(BuiltinInfo, 1835 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1836 } 1837 1838 void getTargetDefines(const LangOptions &Opts, 1839 MacroBuilder &Builder) const override { 1840 Builder.defineMacro("__R600__"); 1841 if (hasFMAF) 1842 Builder.defineMacro("__HAS_FMAF__"); 1843 if (hasLDEXPF) 1844 Builder.defineMacro("__HAS_LDEXPF__"); 1845 if (hasFP64 && Opts.OpenCL) 1846 Builder.defineMacro("cl_khr_fp64"); 1847 if (Opts.OpenCL) { 1848 if (GPU >= GK_NORTHERN_ISLANDS) { 1849 Builder.defineMacro("cl_khr_byte_addressable_store"); 1850 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1851 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1852 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1853 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1854 } 1855 } 1856 } 1857 1858 BuiltinVaListKind getBuiltinVaListKind() const override { 1859 return TargetInfo::CharPtrBuiltinVaList; 1860 } 1861 1862 bool setCPU(const std::string &Name) override { 1863 GPU = llvm::StringSwitch<GPUKind>(Name) 1864 .Case("r600" , GK_R600) 1865 .Case("rv610", GK_R600) 1866 .Case("rv620", GK_R600) 1867 .Case("rv630", GK_R600) 1868 .Case("rv635", GK_R600) 1869 .Case("rs780", GK_R600) 1870 .Case("rs880", GK_R600) 1871 .Case("rv670", GK_R600_DOUBLE_OPS) 1872 .Case("rv710", GK_R700) 1873 .Case("rv730", GK_R700) 1874 .Case("rv740", GK_R700_DOUBLE_OPS) 1875 .Case("rv770", GK_R700_DOUBLE_OPS) 1876 .Case("palm", GK_EVERGREEN) 1877 .Case("cedar", GK_EVERGREEN) 1878 .Case("sumo", GK_EVERGREEN) 1879 .Case("sumo2", GK_EVERGREEN) 1880 .Case("redwood", GK_EVERGREEN) 1881 .Case("juniper", GK_EVERGREEN) 1882 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1883 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1884 .Case("barts", GK_NORTHERN_ISLANDS) 1885 .Case("turks", GK_NORTHERN_ISLANDS) 1886 .Case("caicos", GK_NORTHERN_ISLANDS) 1887 .Case("cayman", GK_CAYMAN) 1888 .Case("aruba", GK_CAYMAN) 1889 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1890 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1891 .Case("verde", GK_SOUTHERN_ISLANDS) 1892 .Case("oland", GK_SOUTHERN_ISLANDS) 1893 .Case("hainan", GK_SOUTHERN_ISLANDS) 1894 .Case("bonaire", GK_SEA_ISLANDS) 1895 .Case("kabini", GK_SEA_ISLANDS) 1896 .Case("kaveri", GK_SEA_ISLANDS) 1897 .Case("hawaii", GK_SEA_ISLANDS) 1898 .Case("mullins", GK_SEA_ISLANDS) 1899 .Case("tonga", GK_VOLCANIC_ISLANDS) 1900 .Case("iceland", GK_VOLCANIC_ISLANDS) 1901 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1902 .Default(GK_NONE); 1903 1904 if (GPU == GK_NONE) { 1905 return false; 1906 } 1907 1908 // Set the correct data layout 1909 switch (GPU) { 1910 case GK_NONE: 1911 case GK_R600: 1912 case GK_R700: 1913 case GK_EVERGREEN: 1914 case GK_NORTHERN_ISLANDS: 1915 DataLayoutString = DataLayoutStringR600; 1916 hasFP64 = false; 1917 hasFMAF = false; 1918 hasLDEXPF = false; 1919 break; 1920 case GK_R600_DOUBLE_OPS: 1921 case GK_R700_DOUBLE_OPS: 1922 case GK_EVERGREEN_DOUBLE_OPS: 1923 case GK_CAYMAN: 1924 DataLayoutString = DataLayoutStringR600DoubleOps; 1925 hasFP64 = true; 1926 hasFMAF = true; 1927 hasLDEXPF = false; 1928 break; 1929 case GK_SOUTHERN_ISLANDS: 1930 case GK_SEA_ISLANDS: 1931 case GK_VOLCANIC_ISLANDS: 1932 DataLayoutString = DataLayoutStringSI; 1933 hasFP64 = true; 1934 hasFMAF = true; 1935 hasLDEXPF = true; 1936 break; 1937 } 1938 1939 return true; 1940 } 1941 }; 1942 1943 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1944 #define BUILTIN(ID, TYPE, ATTRS) \ 1945 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1946 #include "clang/Basic/BuiltinsAMDGPU.def" 1947 }; 1948 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1949 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1950 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1951 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1952 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1953 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1954 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1955 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1956 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1957 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1958 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1959 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1960 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1961 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1962 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1963 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1964 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1965 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1966 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1967 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1968 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1969 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1970 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1971 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1972 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1973 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1974 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1975 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1976 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1977 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1978 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1979 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1980 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1981 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1982 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1983 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1984 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1985 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1986 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1987 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1988 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1989 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1990 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1991 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1992 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1993 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1994 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1995 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1996 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1997 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1998 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1999 }; 2000 2001 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2002 return llvm::makeArrayRef(GCCRegNames); 2003 } 2004 2005 // Namespace for x86 abstract base class 2006 const Builtin::Info BuiltinInfo[] = { 2007 #define BUILTIN(ID, TYPE, ATTRS) \ 2008 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2009 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2010 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2011 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2012 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2013 #include "clang/Basic/BuiltinsX86.def" 2014 }; 2015 2016 static const char* const GCCRegNames[] = { 2017 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2018 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2019 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2020 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2021 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2022 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2023 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2024 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2025 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2026 }; 2027 2028 const TargetInfo::AddlRegName AddlRegNames[] = { 2029 { { "al", "ah", "eax", "rax" }, 0 }, 2030 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2031 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2032 { { "dl", "dh", "edx", "rdx" }, 1 }, 2033 { { "esi", "rsi" }, 4 }, 2034 { { "edi", "rdi" }, 5 }, 2035 { { "esp", "rsp" }, 7 }, 2036 { { "ebp", "rbp" }, 6 }, 2037 { { "r8d", "r8w", "r8b" }, 38 }, 2038 { { "r9d", "r9w", "r9b" }, 39 }, 2039 { { "r10d", "r10w", "r10b" }, 40 }, 2040 { { "r11d", "r11w", "r11b" }, 41 }, 2041 { { "r12d", "r12w", "r12b" }, 42 }, 2042 { { "r13d", "r13w", "r13b" }, 43 }, 2043 { { "r14d", "r14w", "r14b" }, 44 }, 2044 { { "r15d", "r15w", "r15b" }, 45 }, 2045 }; 2046 2047 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2048 // most of the implementation can be shared. 2049 class X86TargetInfo : public TargetInfo { 2050 enum X86SSEEnum { 2051 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2052 } SSELevel = NoSSE; 2053 enum MMX3DNowEnum { 2054 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2055 } MMX3DNowLevel = NoMMX3DNow; 2056 enum XOPEnum { 2057 NoXOP, 2058 SSE4A, 2059 FMA4, 2060 XOP 2061 } XOPLevel = NoXOP; 2062 2063 bool HasAES = false; 2064 bool HasPCLMUL = false; 2065 bool HasLZCNT = false; 2066 bool HasRDRND = false; 2067 bool HasFSGSBASE = false; 2068 bool HasBMI = false; 2069 bool HasBMI2 = false; 2070 bool HasPOPCNT = false; 2071 bool HasRTM = false; 2072 bool HasPRFCHW = false; 2073 bool HasRDSEED = false; 2074 bool HasADX = false; 2075 bool HasTBM = false; 2076 bool HasFMA = false; 2077 bool HasF16C = false; 2078 bool HasAVX512CD = false; 2079 bool HasAVX512ER = false; 2080 bool HasAVX512PF = false; 2081 bool HasAVX512DQ = false; 2082 bool HasAVX512BW = false; 2083 bool HasAVX512VL = false; 2084 bool HasSHA = false; 2085 bool HasCX16 = false; 2086 bool HasFXSR = false; 2087 bool HasXSAVE = false; 2088 bool HasXSAVEOPT = false; 2089 bool HasXSAVEC = false; 2090 bool HasXSAVES = false; 2091 2092 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2093 /// 2094 /// Each enumeration represents a particular CPU supported by Clang. These 2095 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2096 enum CPUKind { 2097 CK_Generic, 2098 2099 /// \name i386 2100 /// i386-generation processors. 2101 //@{ 2102 CK_i386, 2103 //@} 2104 2105 /// \name i486 2106 /// i486-generation processors. 2107 //@{ 2108 CK_i486, 2109 CK_WinChipC6, 2110 CK_WinChip2, 2111 CK_C3, 2112 //@} 2113 2114 /// \name i586 2115 /// i586-generation processors, P5 microarchitecture based. 2116 //@{ 2117 CK_i586, 2118 CK_Pentium, 2119 CK_PentiumMMX, 2120 //@} 2121 2122 /// \name i686 2123 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2124 //@{ 2125 CK_i686, 2126 CK_PentiumPro, 2127 CK_Pentium2, 2128 CK_Pentium3, 2129 CK_Pentium3M, 2130 CK_PentiumM, 2131 CK_C3_2, 2132 2133 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2134 /// Clang however has some logic to suport this. 2135 // FIXME: Warn, deprecate, and potentially remove this. 2136 CK_Yonah, 2137 //@} 2138 2139 /// \name Netburst 2140 /// Netburst microarchitecture based processors. 2141 //@{ 2142 CK_Pentium4, 2143 CK_Pentium4M, 2144 CK_Prescott, 2145 CK_Nocona, 2146 //@} 2147 2148 /// \name Core 2149 /// Core microarchitecture based processors. 2150 //@{ 2151 CK_Core2, 2152 2153 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2154 /// codename which GCC no longer accepts as an option to -march, but Clang 2155 /// has some logic for recognizing it. 2156 // FIXME: Warn, deprecate, and potentially remove this. 2157 CK_Penryn, 2158 //@} 2159 2160 /// \name Atom 2161 /// Atom processors 2162 //@{ 2163 CK_Bonnell, 2164 CK_Silvermont, 2165 //@} 2166 2167 /// \name Nehalem 2168 /// Nehalem microarchitecture based processors. 2169 CK_Nehalem, 2170 2171 /// \name Westmere 2172 /// Westmere microarchitecture based processors. 2173 CK_Westmere, 2174 2175 /// \name Sandy Bridge 2176 /// Sandy Bridge microarchitecture based processors. 2177 CK_SandyBridge, 2178 2179 /// \name Ivy Bridge 2180 /// Ivy Bridge microarchitecture based processors. 2181 CK_IvyBridge, 2182 2183 /// \name Haswell 2184 /// Haswell microarchitecture based processors. 2185 CK_Haswell, 2186 2187 /// \name Broadwell 2188 /// Broadwell microarchitecture based processors. 2189 CK_Broadwell, 2190 2191 /// \name Skylake 2192 /// Skylake microarchitecture based processors. 2193 CK_Skylake, 2194 2195 /// \name Knights Landing 2196 /// Knights Landing processor. 2197 CK_KNL, 2198 2199 /// \name K6 2200 /// K6 architecture processors. 2201 //@{ 2202 CK_K6, 2203 CK_K6_2, 2204 CK_K6_3, 2205 //@} 2206 2207 /// \name K7 2208 /// K7 architecture processors. 2209 //@{ 2210 CK_Athlon, 2211 CK_AthlonThunderbird, 2212 CK_Athlon4, 2213 CK_AthlonXP, 2214 CK_AthlonMP, 2215 //@} 2216 2217 /// \name K8 2218 /// K8 architecture processors. 2219 //@{ 2220 CK_Athlon64, 2221 CK_Athlon64SSE3, 2222 CK_AthlonFX, 2223 CK_K8, 2224 CK_K8SSE3, 2225 CK_Opteron, 2226 CK_OpteronSSE3, 2227 CK_AMDFAM10, 2228 //@} 2229 2230 /// \name Bobcat 2231 /// Bobcat architecture processors. 2232 //@{ 2233 CK_BTVER1, 2234 CK_BTVER2, 2235 //@} 2236 2237 /// \name Bulldozer 2238 /// Bulldozer architecture processors. 2239 //@{ 2240 CK_BDVER1, 2241 CK_BDVER2, 2242 CK_BDVER3, 2243 CK_BDVER4, 2244 //@} 2245 2246 /// This specification is deprecated and will be removed in the future. 2247 /// Users should prefer \see CK_K8. 2248 // FIXME: Warn on this when the CPU is set to it. 2249 //@{ 2250 CK_x86_64, 2251 //@} 2252 2253 /// \name Geode 2254 /// Geode processors. 2255 //@{ 2256 CK_Geode 2257 //@} 2258 } CPU = CK_Generic; 2259 2260 CPUKind getCPUKind(StringRef CPU) const { 2261 return llvm::StringSwitch<CPUKind>(CPU) 2262 .Case("i386", CK_i386) 2263 .Case("i486", CK_i486) 2264 .Case("winchip-c6", CK_WinChipC6) 2265 .Case("winchip2", CK_WinChip2) 2266 .Case("c3", CK_C3) 2267 .Case("i586", CK_i586) 2268 .Case("pentium", CK_Pentium) 2269 .Case("pentium-mmx", CK_PentiumMMX) 2270 .Case("i686", CK_i686) 2271 .Case("pentiumpro", CK_PentiumPro) 2272 .Case("pentium2", CK_Pentium2) 2273 .Case("pentium3", CK_Pentium3) 2274 .Case("pentium3m", CK_Pentium3M) 2275 .Case("pentium-m", CK_PentiumM) 2276 .Case("c3-2", CK_C3_2) 2277 .Case("yonah", CK_Yonah) 2278 .Case("pentium4", CK_Pentium4) 2279 .Case("pentium4m", CK_Pentium4M) 2280 .Case("prescott", CK_Prescott) 2281 .Case("nocona", CK_Nocona) 2282 .Case("core2", CK_Core2) 2283 .Case("penryn", CK_Penryn) 2284 .Case("bonnell", CK_Bonnell) 2285 .Case("atom", CK_Bonnell) // Legacy name. 2286 .Case("silvermont", CK_Silvermont) 2287 .Case("slm", CK_Silvermont) // Legacy name. 2288 .Case("nehalem", CK_Nehalem) 2289 .Case("corei7", CK_Nehalem) // Legacy name. 2290 .Case("westmere", CK_Westmere) 2291 .Case("sandybridge", CK_SandyBridge) 2292 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2293 .Case("ivybridge", CK_IvyBridge) 2294 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2295 .Case("haswell", CK_Haswell) 2296 .Case("core-avx2", CK_Haswell) // Legacy name. 2297 .Case("broadwell", CK_Broadwell) 2298 .Case("skylake", CK_Skylake) 2299 .Case("skx", CK_Skylake) // Legacy name. 2300 .Case("knl", CK_KNL) 2301 .Case("k6", CK_K6) 2302 .Case("k6-2", CK_K6_2) 2303 .Case("k6-3", CK_K6_3) 2304 .Case("athlon", CK_Athlon) 2305 .Case("athlon-tbird", CK_AthlonThunderbird) 2306 .Case("athlon-4", CK_Athlon4) 2307 .Case("athlon-xp", CK_AthlonXP) 2308 .Case("athlon-mp", CK_AthlonMP) 2309 .Case("athlon64", CK_Athlon64) 2310 .Case("athlon64-sse3", CK_Athlon64SSE3) 2311 .Case("athlon-fx", CK_AthlonFX) 2312 .Case("k8", CK_K8) 2313 .Case("k8-sse3", CK_K8SSE3) 2314 .Case("opteron", CK_Opteron) 2315 .Case("opteron-sse3", CK_OpteronSSE3) 2316 .Case("barcelona", CK_AMDFAM10) 2317 .Case("amdfam10", CK_AMDFAM10) 2318 .Case("btver1", CK_BTVER1) 2319 .Case("btver2", CK_BTVER2) 2320 .Case("bdver1", CK_BDVER1) 2321 .Case("bdver2", CK_BDVER2) 2322 .Case("bdver3", CK_BDVER3) 2323 .Case("bdver4", CK_BDVER4) 2324 .Case("x86-64", CK_x86_64) 2325 .Case("geode", CK_Geode) 2326 .Default(CK_Generic); 2327 } 2328 2329 enum FPMathKind { 2330 FP_Default, 2331 FP_SSE, 2332 FP_387 2333 } FPMath = FP_Default; 2334 2335 public: 2336 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2337 BigEndian = false; 2338 LongDoubleFormat = Triple.isOSIAMCU() ? &llvm::APFloat::IEEEdouble 2339 : &llvm::APFloat::x87DoubleExtended; 2340 } 2341 unsigned getFloatEvalMethod() const override { 2342 // X87 evaluates with 80 bits "long double" precision. 2343 return SSELevel == NoSSE ? 2 : 0; 2344 } 2345 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2346 return llvm::makeArrayRef(BuiltinInfo, 2347 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2348 } 2349 ArrayRef<const char *> getGCCRegNames() const override { 2350 return llvm::makeArrayRef(GCCRegNames); 2351 } 2352 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2353 return None; 2354 } 2355 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2356 return llvm::makeArrayRef(AddlRegNames); 2357 } 2358 bool validateCpuSupports(StringRef Name) const override; 2359 bool validateAsmConstraint(const char *&Name, 2360 TargetInfo::ConstraintInfo &info) const override; 2361 2362 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2363 2364 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2365 2366 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2367 2368 std::string convertConstraint(const char *&Constraint) const override; 2369 const char *getClobbers() const override { 2370 return "~{dirflag},~{fpsr},~{flags}"; 2371 } 2372 void getTargetDefines(const LangOptions &Opts, 2373 MacroBuilder &Builder) const override; 2374 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2375 bool Enabled); 2376 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2377 bool Enabled); 2378 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2379 bool Enabled); 2380 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2381 StringRef Name, bool Enabled) const override { 2382 setFeatureEnabledImpl(Features, Name, Enabled); 2383 } 2384 // This exists purely to cut down on the number of virtual calls in 2385 // initFeatureMap which calls this repeatedly. 2386 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2387 StringRef Name, bool Enabled); 2388 bool 2389 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2390 StringRef CPU, 2391 const std::vector<std::string> &FeaturesVec) const override; 2392 bool hasFeature(StringRef Feature) const override; 2393 bool handleTargetFeatures(std::vector<std::string> &Features, 2394 DiagnosticsEngine &Diags) override; 2395 StringRef getABI() const override { 2396 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2397 return "avx512"; 2398 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2399 return "avx"; 2400 if (getTriple().getArch() == llvm::Triple::x86 && 2401 MMX3DNowLevel == NoMMX3DNow) 2402 return "no-mmx"; 2403 return ""; 2404 } 2405 bool setCPU(const std::string &Name) override { 2406 CPU = getCPUKind(Name); 2407 2408 // Perform any per-CPU checks necessary to determine if this CPU is 2409 // acceptable. 2410 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2411 // invalid without explaining *why*. 2412 switch (CPU) { 2413 case CK_Generic: 2414 // No processor selected! 2415 return false; 2416 2417 case CK_i386: 2418 case CK_i486: 2419 case CK_WinChipC6: 2420 case CK_WinChip2: 2421 case CK_C3: 2422 case CK_i586: 2423 case CK_Pentium: 2424 case CK_PentiumMMX: 2425 case CK_i686: 2426 case CK_PentiumPro: 2427 case CK_Pentium2: 2428 case CK_Pentium3: 2429 case CK_Pentium3M: 2430 case CK_PentiumM: 2431 case CK_Yonah: 2432 case CK_C3_2: 2433 case CK_Pentium4: 2434 case CK_Pentium4M: 2435 case CK_Prescott: 2436 case CK_K6: 2437 case CK_K6_2: 2438 case CK_K6_3: 2439 case CK_Athlon: 2440 case CK_AthlonThunderbird: 2441 case CK_Athlon4: 2442 case CK_AthlonXP: 2443 case CK_AthlonMP: 2444 case CK_Geode: 2445 // Only accept certain architectures when compiling in 32-bit mode. 2446 if (getTriple().getArch() != llvm::Triple::x86) 2447 return false; 2448 2449 // Fallthrough 2450 case CK_Nocona: 2451 case CK_Core2: 2452 case CK_Penryn: 2453 case CK_Bonnell: 2454 case CK_Silvermont: 2455 case CK_Nehalem: 2456 case CK_Westmere: 2457 case CK_SandyBridge: 2458 case CK_IvyBridge: 2459 case CK_Haswell: 2460 case CK_Broadwell: 2461 case CK_Skylake: 2462 case CK_KNL: 2463 case CK_Athlon64: 2464 case CK_Athlon64SSE3: 2465 case CK_AthlonFX: 2466 case CK_K8: 2467 case CK_K8SSE3: 2468 case CK_Opteron: 2469 case CK_OpteronSSE3: 2470 case CK_AMDFAM10: 2471 case CK_BTVER1: 2472 case CK_BTVER2: 2473 case CK_BDVER1: 2474 case CK_BDVER2: 2475 case CK_BDVER3: 2476 case CK_BDVER4: 2477 case CK_x86_64: 2478 return true; 2479 } 2480 llvm_unreachable("Unhandled CPU kind"); 2481 } 2482 2483 bool setFPMath(StringRef Name) override; 2484 2485 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2486 // We accept all non-ARM calling conventions 2487 return (CC == CC_X86ThisCall || 2488 CC == CC_X86FastCall || 2489 CC == CC_X86StdCall || 2490 CC == CC_X86VectorCall || 2491 CC == CC_C || 2492 CC == CC_X86Pascal || 2493 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2494 } 2495 2496 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2497 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2498 } 2499 2500 bool hasSjLjLowering() const override { 2501 return true; 2502 } 2503 }; 2504 2505 bool X86TargetInfo::setFPMath(StringRef Name) { 2506 if (Name == "387") { 2507 FPMath = FP_387; 2508 return true; 2509 } 2510 if (Name == "sse") { 2511 FPMath = FP_SSE; 2512 return true; 2513 } 2514 return false; 2515 } 2516 2517 bool X86TargetInfo::initFeatureMap( 2518 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2519 const std::vector<std::string> &FeaturesVec) const { 2520 // FIXME: This *really* should not be here. 2521 // X86_64 always has SSE2. 2522 if (getTriple().getArch() == llvm::Triple::x86_64) 2523 setFeatureEnabledImpl(Features, "sse2", true); 2524 2525 switch (getCPUKind(CPU)) { 2526 case CK_Generic: 2527 case CK_i386: 2528 case CK_i486: 2529 case CK_i586: 2530 case CK_Pentium: 2531 case CK_i686: 2532 case CK_PentiumPro: 2533 break; 2534 case CK_PentiumMMX: 2535 case CK_Pentium2: 2536 case CK_K6: 2537 case CK_WinChipC6: 2538 setFeatureEnabledImpl(Features, "mmx", true); 2539 break; 2540 case CK_Pentium3: 2541 case CK_Pentium3M: 2542 case CK_C3_2: 2543 setFeatureEnabledImpl(Features, "sse", true); 2544 setFeatureEnabledImpl(Features, "fxsr", true); 2545 break; 2546 case CK_PentiumM: 2547 case CK_Pentium4: 2548 case CK_Pentium4M: 2549 case CK_x86_64: 2550 setFeatureEnabledImpl(Features, "sse2", true); 2551 setFeatureEnabledImpl(Features, "fxsr", true); 2552 break; 2553 case CK_Yonah: 2554 case CK_Prescott: 2555 case CK_Nocona: 2556 setFeatureEnabledImpl(Features, "sse3", true); 2557 setFeatureEnabledImpl(Features, "fxsr", true); 2558 setFeatureEnabledImpl(Features, "cx16", true); 2559 break; 2560 case CK_Core2: 2561 case CK_Bonnell: 2562 setFeatureEnabledImpl(Features, "ssse3", true); 2563 setFeatureEnabledImpl(Features, "fxsr", true); 2564 setFeatureEnabledImpl(Features, "cx16", true); 2565 break; 2566 case CK_Penryn: 2567 setFeatureEnabledImpl(Features, "sse4.1", true); 2568 setFeatureEnabledImpl(Features, "fxsr", true); 2569 setFeatureEnabledImpl(Features, "cx16", true); 2570 break; 2571 case CK_Skylake: 2572 setFeatureEnabledImpl(Features, "avx512f", true); 2573 setFeatureEnabledImpl(Features, "avx512cd", true); 2574 setFeatureEnabledImpl(Features, "avx512dq", true); 2575 setFeatureEnabledImpl(Features, "avx512bw", true); 2576 setFeatureEnabledImpl(Features, "avx512vl", true); 2577 setFeatureEnabledImpl(Features, "xsavec", true); 2578 setFeatureEnabledImpl(Features, "xsaves", true); 2579 // FALLTHROUGH 2580 case CK_Broadwell: 2581 setFeatureEnabledImpl(Features, "rdseed", true); 2582 setFeatureEnabledImpl(Features, "adx", true); 2583 // FALLTHROUGH 2584 case CK_Haswell: 2585 setFeatureEnabledImpl(Features, "avx2", true); 2586 setFeatureEnabledImpl(Features, "lzcnt", true); 2587 setFeatureEnabledImpl(Features, "bmi", true); 2588 setFeatureEnabledImpl(Features, "bmi2", true); 2589 setFeatureEnabledImpl(Features, "rtm", true); 2590 setFeatureEnabledImpl(Features, "fma", true); 2591 // FALLTHROUGH 2592 case CK_IvyBridge: 2593 setFeatureEnabledImpl(Features, "rdrnd", true); 2594 setFeatureEnabledImpl(Features, "f16c", true); 2595 setFeatureEnabledImpl(Features, "fsgsbase", true); 2596 // FALLTHROUGH 2597 case CK_SandyBridge: 2598 setFeatureEnabledImpl(Features, "avx", true); 2599 setFeatureEnabledImpl(Features, "xsave", true); 2600 setFeatureEnabledImpl(Features, "xsaveopt", true); 2601 // FALLTHROUGH 2602 case CK_Westmere: 2603 case CK_Silvermont: 2604 setFeatureEnabledImpl(Features, "aes", true); 2605 setFeatureEnabledImpl(Features, "pclmul", true); 2606 // FALLTHROUGH 2607 case CK_Nehalem: 2608 setFeatureEnabledImpl(Features, "sse4.2", true); 2609 setFeatureEnabledImpl(Features, "fxsr", true); 2610 setFeatureEnabledImpl(Features, "cx16", true); 2611 break; 2612 case CK_KNL: 2613 setFeatureEnabledImpl(Features, "avx512f", true); 2614 setFeatureEnabledImpl(Features, "avx512cd", true); 2615 setFeatureEnabledImpl(Features, "avx512er", true); 2616 setFeatureEnabledImpl(Features, "avx512pf", true); 2617 setFeatureEnabledImpl(Features, "fxsr", true); 2618 setFeatureEnabledImpl(Features, "rdseed", true); 2619 setFeatureEnabledImpl(Features, "adx", true); 2620 setFeatureEnabledImpl(Features, "lzcnt", true); 2621 setFeatureEnabledImpl(Features, "bmi", true); 2622 setFeatureEnabledImpl(Features, "bmi2", true); 2623 setFeatureEnabledImpl(Features, "rtm", true); 2624 setFeatureEnabledImpl(Features, "fma", true); 2625 setFeatureEnabledImpl(Features, "rdrnd", true); 2626 setFeatureEnabledImpl(Features, "f16c", true); 2627 setFeatureEnabledImpl(Features, "fsgsbase", true); 2628 setFeatureEnabledImpl(Features, "aes", true); 2629 setFeatureEnabledImpl(Features, "pclmul", true); 2630 setFeatureEnabledImpl(Features, "cx16", true); 2631 setFeatureEnabledImpl(Features, "xsaveopt", true); 2632 setFeatureEnabledImpl(Features, "xsave", true); 2633 break; 2634 case CK_K6_2: 2635 case CK_K6_3: 2636 case CK_WinChip2: 2637 case CK_C3: 2638 setFeatureEnabledImpl(Features, "3dnow", true); 2639 break; 2640 case CK_Athlon: 2641 case CK_AthlonThunderbird: 2642 case CK_Geode: 2643 setFeatureEnabledImpl(Features, "3dnowa", true); 2644 break; 2645 case CK_Athlon4: 2646 case CK_AthlonXP: 2647 case CK_AthlonMP: 2648 setFeatureEnabledImpl(Features, "sse", true); 2649 setFeatureEnabledImpl(Features, "3dnowa", true); 2650 setFeatureEnabledImpl(Features, "fxsr", true); 2651 break; 2652 case CK_K8: 2653 case CK_Opteron: 2654 case CK_Athlon64: 2655 case CK_AthlonFX: 2656 setFeatureEnabledImpl(Features, "sse2", true); 2657 setFeatureEnabledImpl(Features, "3dnowa", true); 2658 setFeatureEnabledImpl(Features, "fxsr", true); 2659 break; 2660 case CK_AMDFAM10: 2661 setFeatureEnabledImpl(Features, "sse4a", true); 2662 setFeatureEnabledImpl(Features, "lzcnt", true); 2663 setFeatureEnabledImpl(Features, "popcnt", true); 2664 // FALLTHROUGH 2665 case CK_K8SSE3: 2666 case CK_OpteronSSE3: 2667 case CK_Athlon64SSE3: 2668 setFeatureEnabledImpl(Features, "sse3", true); 2669 setFeatureEnabledImpl(Features, "3dnowa", true); 2670 setFeatureEnabledImpl(Features, "fxsr", true); 2671 break; 2672 case CK_BTVER2: 2673 setFeatureEnabledImpl(Features, "avx", true); 2674 setFeatureEnabledImpl(Features, "aes", true); 2675 setFeatureEnabledImpl(Features, "pclmul", true); 2676 setFeatureEnabledImpl(Features, "bmi", true); 2677 setFeatureEnabledImpl(Features, "f16c", true); 2678 setFeatureEnabledImpl(Features, "xsaveopt", true); 2679 // FALLTHROUGH 2680 case CK_BTVER1: 2681 setFeatureEnabledImpl(Features, "ssse3", true); 2682 setFeatureEnabledImpl(Features, "sse4a", true); 2683 setFeatureEnabledImpl(Features, "lzcnt", true); 2684 setFeatureEnabledImpl(Features, "popcnt", true); 2685 setFeatureEnabledImpl(Features, "prfchw", true); 2686 setFeatureEnabledImpl(Features, "cx16", true); 2687 setFeatureEnabledImpl(Features, "fxsr", true); 2688 setFeatureEnabledImpl(Features, "xsave", true); 2689 break; 2690 case CK_BDVER4: 2691 setFeatureEnabledImpl(Features, "avx2", true); 2692 setFeatureEnabledImpl(Features, "bmi2", true); 2693 // FALLTHROUGH 2694 case CK_BDVER3: 2695 setFeatureEnabledImpl(Features, "fsgsbase", true); 2696 setFeatureEnabledImpl(Features, "xsaveopt", true); 2697 // FALLTHROUGH 2698 case CK_BDVER2: 2699 setFeatureEnabledImpl(Features, "bmi", true); 2700 setFeatureEnabledImpl(Features, "fma", true); 2701 setFeatureEnabledImpl(Features, "f16c", true); 2702 setFeatureEnabledImpl(Features, "tbm", true); 2703 // FALLTHROUGH 2704 case CK_BDVER1: 2705 // xop implies avx, sse4a and fma4. 2706 setFeatureEnabledImpl(Features, "xop", true); 2707 setFeatureEnabledImpl(Features, "lzcnt", true); 2708 setFeatureEnabledImpl(Features, "aes", true); 2709 setFeatureEnabledImpl(Features, "pclmul", true); 2710 setFeatureEnabledImpl(Features, "prfchw", true); 2711 setFeatureEnabledImpl(Features, "cx16", true); 2712 setFeatureEnabledImpl(Features, "fxsr", true); 2713 setFeatureEnabledImpl(Features, "xsave", true); 2714 break; 2715 } 2716 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2717 return false; 2718 2719 // Can't do this earlier because we need to be able to explicitly enable 2720 // or disable these features and the things that they depend upon. 2721 2722 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2723 auto I = Features.find("sse4.2"); 2724 if (I != Features.end() && I->getValue() && 2725 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2726 FeaturesVec.end()) 2727 Features["popcnt"] = true; 2728 2729 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2730 I = Features.find("3dnow"); 2731 if (I != Features.end() && I->getValue() && 2732 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2733 FeaturesVec.end()) 2734 Features["prfchw"] = true; 2735 2736 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2737 // then enable MMX. 2738 I = Features.find("sse"); 2739 if (I != Features.end() && I->getValue() && 2740 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2741 FeaturesVec.end()) 2742 Features["mmx"] = true; 2743 2744 return true; 2745 } 2746 2747 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2748 X86SSEEnum Level, bool Enabled) { 2749 if (Enabled) { 2750 switch (Level) { 2751 case AVX512F: 2752 Features["avx512f"] = true; 2753 case AVX2: 2754 Features["avx2"] = true; 2755 case AVX: 2756 Features["avx"] = true; 2757 Features["xsave"] = true; 2758 case SSE42: 2759 Features["sse4.2"] = true; 2760 case SSE41: 2761 Features["sse4.1"] = true; 2762 case SSSE3: 2763 Features["ssse3"] = true; 2764 case SSE3: 2765 Features["sse3"] = true; 2766 case SSE2: 2767 Features["sse2"] = true; 2768 case SSE1: 2769 Features["sse"] = true; 2770 case NoSSE: 2771 break; 2772 } 2773 return; 2774 } 2775 2776 switch (Level) { 2777 case NoSSE: 2778 case SSE1: 2779 Features["sse"] = false; 2780 case SSE2: 2781 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2782 Features["sha"] = false; 2783 case SSE3: 2784 Features["sse3"] = false; 2785 setXOPLevel(Features, NoXOP, false); 2786 case SSSE3: 2787 Features["ssse3"] = false; 2788 case SSE41: 2789 Features["sse4.1"] = false; 2790 case SSE42: 2791 Features["sse4.2"] = false; 2792 case AVX: 2793 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2794 Features["xsaveopt"] = false; 2795 setXOPLevel(Features, FMA4, false); 2796 case AVX2: 2797 Features["avx2"] = false; 2798 case AVX512F: 2799 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2800 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2801 Features["avx512vl"] = false; 2802 } 2803 } 2804 2805 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2806 MMX3DNowEnum Level, bool Enabled) { 2807 if (Enabled) { 2808 switch (Level) { 2809 case AMD3DNowAthlon: 2810 Features["3dnowa"] = true; 2811 case AMD3DNow: 2812 Features["3dnow"] = true; 2813 case MMX: 2814 Features["mmx"] = true; 2815 case NoMMX3DNow: 2816 break; 2817 } 2818 return; 2819 } 2820 2821 switch (Level) { 2822 case NoMMX3DNow: 2823 case MMX: 2824 Features["mmx"] = false; 2825 case AMD3DNow: 2826 Features["3dnow"] = false; 2827 case AMD3DNowAthlon: 2828 Features["3dnowa"] = false; 2829 } 2830 } 2831 2832 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2833 bool Enabled) { 2834 if (Enabled) { 2835 switch (Level) { 2836 case XOP: 2837 Features["xop"] = true; 2838 case FMA4: 2839 Features["fma4"] = true; 2840 setSSELevel(Features, AVX, true); 2841 case SSE4A: 2842 Features["sse4a"] = true; 2843 setSSELevel(Features, SSE3, true); 2844 case NoXOP: 2845 break; 2846 } 2847 return; 2848 } 2849 2850 switch (Level) { 2851 case NoXOP: 2852 case SSE4A: 2853 Features["sse4a"] = false; 2854 case FMA4: 2855 Features["fma4"] = false; 2856 case XOP: 2857 Features["xop"] = false; 2858 } 2859 } 2860 2861 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2862 StringRef Name, bool Enabled) { 2863 // This is a bit of a hack to deal with the sse4 target feature when used 2864 // as part of the target attribute. We handle sse4 correctly everywhere 2865 // else. See below for more information on how we handle the sse4 options. 2866 if (Name != "sse4") 2867 Features[Name] = Enabled; 2868 2869 if (Name == "mmx") { 2870 setMMXLevel(Features, MMX, Enabled); 2871 } else if (Name == "sse") { 2872 setSSELevel(Features, SSE1, Enabled); 2873 } else if (Name == "sse2") { 2874 setSSELevel(Features, SSE2, Enabled); 2875 } else if (Name == "sse3") { 2876 setSSELevel(Features, SSE3, Enabled); 2877 } else if (Name == "ssse3") { 2878 setSSELevel(Features, SSSE3, Enabled); 2879 } else if (Name == "sse4.2") { 2880 setSSELevel(Features, SSE42, Enabled); 2881 } else if (Name == "sse4.1") { 2882 setSSELevel(Features, SSE41, Enabled); 2883 } else if (Name == "3dnow") { 2884 setMMXLevel(Features, AMD3DNow, Enabled); 2885 } else if (Name == "3dnowa") { 2886 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2887 } else if (Name == "aes") { 2888 if (Enabled) 2889 setSSELevel(Features, SSE2, Enabled); 2890 } else if (Name == "pclmul") { 2891 if (Enabled) 2892 setSSELevel(Features, SSE2, Enabled); 2893 } else if (Name == "avx") { 2894 setSSELevel(Features, AVX, Enabled); 2895 } else if (Name == "avx2") { 2896 setSSELevel(Features, AVX2, Enabled); 2897 } else if (Name == "avx512f") { 2898 setSSELevel(Features, AVX512F, Enabled); 2899 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2900 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2901 if (Enabled) 2902 setSSELevel(Features, AVX512F, Enabled); 2903 } else if (Name == "fma") { 2904 if (Enabled) 2905 setSSELevel(Features, AVX, Enabled); 2906 } else if (Name == "fma4") { 2907 setXOPLevel(Features, FMA4, Enabled); 2908 } else if (Name == "xop") { 2909 setXOPLevel(Features, XOP, Enabled); 2910 } else if (Name == "sse4a") { 2911 setXOPLevel(Features, SSE4A, Enabled); 2912 } else if (Name == "f16c") { 2913 if (Enabled) 2914 setSSELevel(Features, AVX, Enabled); 2915 } else if (Name == "sha") { 2916 if (Enabled) 2917 setSSELevel(Features, SSE2, Enabled); 2918 } else if (Name == "sse4") { 2919 // We can get here via the __target__ attribute since that's not controlled 2920 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 2921 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 2922 // disabled. 2923 if (Enabled) 2924 setSSELevel(Features, SSE42, Enabled); 2925 else 2926 setSSELevel(Features, SSE41, Enabled); 2927 } else if (Name == "xsave") { 2928 if (Enabled) 2929 setSSELevel(Features, AVX, Enabled); 2930 else 2931 Features["xsaveopt"] = false; 2932 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 2933 if (Enabled) { 2934 Features["xsave"] = true; 2935 setSSELevel(Features, AVX, Enabled); 2936 } 2937 } 2938 } 2939 2940 /// handleTargetFeatures - Perform initialization based on the user 2941 /// configured set of features. 2942 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2943 DiagnosticsEngine &Diags) { 2944 for (const auto &Feature : Features) { 2945 if (Feature[0] != '+') 2946 continue; 2947 2948 if (Feature == "+aes") { 2949 HasAES = true; 2950 } else if (Feature == "+pclmul") { 2951 HasPCLMUL = true; 2952 } else if (Feature == "+lzcnt") { 2953 HasLZCNT = true; 2954 } else if (Feature == "+rdrnd") { 2955 HasRDRND = true; 2956 } else if (Feature == "+fsgsbase") { 2957 HasFSGSBASE = true; 2958 } else if (Feature == "+bmi") { 2959 HasBMI = true; 2960 } else if (Feature == "+bmi2") { 2961 HasBMI2 = true; 2962 } else if (Feature == "+popcnt") { 2963 HasPOPCNT = true; 2964 } else if (Feature == "+rtm") { 2965 HasRTM = true; 2966 } else if (Feature == "+prfchw") { 2967 HasPRFCHW = true; 2968 } else if (Feature == "+rdseed") { 2969 HasRDSEED = true; 2970 } else if (Feature == "+adx") { 2971 HasADX = true; 2972 } else if (Feature == "+tbm") { 2973 HasTBM = true; 2974 } else if (Feature == "+fma") { 2975 HasFMA = true; 2976 } else if (Feature == "+f16c") { 2977 HasF16C = true; 2978 } else if (Feature == "+avx512cd") { 2979 HasAVX512CD = true; 2980 } else if (Feature == "+avx512er") { 2981 HasAVX512ER = true; 2982 } else if (Feature == "+avx512pf") { 2983 HasAVX512PF = true; 2984 } else if (Feature == "+avx512dq") { 2985 HasAVX512DQ = true; 2986 } else if (Feature == "+avx512bw") { 2987 HasAVX512BW = true; 2988 } else if (Feature == "+avx512vl") { 2989 HasAVX512VL = true; 2990 } else if (Feature == "+sha") { 2991 HasSHA = true; 2992 } else if (Feature == "+cx16") { 2993 HasCX16 = true; 2994 } else if (Feature == "+fxsr") { 2995 HasFXSR = true; 2996 } else if (Feature == "+xsave") { 2997 HasXSAVE = true; 2998 } else if (Feature == "+xsaveopt") { 2999 HasXSAVEOPT = true; 3000 } else if (Feature == "+xsavec") { 3001 HasXSAVEC = true; 3002 } else if (Feature == "+xsaves") { 3003 HasXSAVES = true; 3004 } 3005 3006 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3007 .Case("+avx512f", AVX512F) 3008 .Case("+avx2", AVX2) 3009 .Case("+avx", AVX) 3010 .Case("+sse4.2", SSE42) 3011 .Case("+sse4.1", SSE41) 3012 .Case("+ssse3", SSSE3) 3013 .Case("+sse3", SSE3) 3014 .Case("+sse2", SSE2) 3015 .Case("+sse", SSE1) 3016 .Default(NoSSE); 3017 SSELevel = std::max(SSELevel, Level); 3018 3019 MMX3DNowEnum ThreeDNowLevel = 3020 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3021 .Case("+3dnowa", AMD3DNowAthlon) 3022 .Case("+3dnow", AMD3DNow) 3023 .Case("+mmx", MMX) 3024 .Default(NoMMX3DNow); 3025 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3026 3027 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3028 .Case("+xop", XOP) 3029 .Case("+fma4", FMA4) 3030 .Case("+sse4a", SSE4A) 3031 .Default(NoXOP); 3032 XOPLevel = std::max(XOPLevel, XLevel); 3033 } 3034 3035 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3036 // matches the selected sse level. 3037 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3038 (FPMath == FP_387 && SSELevel >= SSE1)) { 3039 Diags.Report(diag::err_target_unsupported_fpmath) << 3040 (FPMath == FP_SSE ? "sse" : "387"); 3041 return false; 3042 } 3043 3044 SimdDefaultAlign = 3045 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3046 return true; 3047 } 3048 3049 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3050 /// definitions for this particular subtarget. 3051 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3052 MacroBuilder &Builder) const { 3053 // Target identification. 3054 if (getTriple().getArch() == llvm::Triple::x86_64) { 3055 Builder.defineMacro("__amd64__"); 3056 Builder.defineMacro("__amd64"); 3057 Builder.defineMacro("__x86_64"); 3058 Builder.defineMacro("__x86_64__"); 3059 if (getTriple().getArchName() == "x86_64h") { 3060 Builder.defineMacro("__x86_64h"); 3061 Builder.defineMacro("__x86_64h__"); 3062 } 3063 } else { 3064 DefineStd(Builder, "i386", Opts); 3065 } 3066 3067 // Subtarget options. 3068 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3069 // truly should be based on -mtune options. 3070 switch (CPU) { 3071 case CK_Generic: 3072 break; 3073 case CK_i386: 3074 // The rest are coming from the i386 define above. 3075 Builder.defineMacro("__tune_i386__"); 3076 break; 3077 case CK_i486: 3078 case CK_WinChipC6: 3079 case CK_WinChip2: 3080 case CK_C3: 3081 defineCPUMacros(Builder, "i486"); 3082 break; 3083 case CK_PentiumMMX: 3084 Builder.defineMacro("__pentium_mmx__"); 3085 Builder.defineMacro("__tune_pentium_mmx__"); 3086 // Fallthrough 3087 case CK_i586: 3088 case CK_Pentium: 3089 defineCPUMacros(Builder, "i586"); 3090 defineCPUMacros(Builder, "pentium"); 3091 break; 3092 case CK_Pentium3: 3093 case CK_Pentium3M: 3094 case CK_PentiumM: 3095 Builder.defineMacro("__tune_pentium3__"); 3096 // Fallthrough 3097 case CK_Pentium2: 3098 case CK_C3_2: 3099 Builder.defineMacro("__tune_pentium2__"); 3100 // Fallthrough 3101 case CK_PentiumPro: 3102 Builder.defineMacro("__tune_i686__"); 3103 Builder.defineMacro("__tune_pentiumpro__"); 3104 // Fallthrough 3105 case CK_i686: 3106 Builder.defineMacro("__i686"); 3107 Builder.defineMacro("__i686__"); 3108 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3109 Builder.defineMacro("__pentiumpro"); 3110 Builder.defineMacro("__pentiumpro__"); 3111 break; 3112 case CK_Pentium4: 3113 case CK_Pentium4M: 3114 defineCPUMacros(Builder, "pentium4"); 3115 break; 3116 case CK_Yonah: 3117 case CK_Prescott: 3118 case CK_Nocona: 3119 defineCPUMacros(Builder, "nocona"); 3120 break; 3121 case CK_Core2: 3122 case CK_Penryn: 3123 defineCPUMacros(Builder, "core2"); 3124 break; 3125 case CK_Bonnell: 3126 defineCPUMacros(Builder, "atom"); 3127 break; 3128 case CK_Silvermont: 3129 defineCPUMacros(Builder, "slm"); 3130 break; 3131 case CK_Nehalem: 3132 case CK_Westmere: 3133 case CK_SandyBridge: 3134 case CK_IvyBridge: 3135 case CK_Haswell: 3136 case CK_Broadwell: 3137 // FIXME: Historically, we defined this legacy name, it would be nice to 3138 // remove it at some point. We've never exposed fine-grained names for 3139 // recent primary x86 CPUs, and we should keep it that way. 3140 defineCPUMacros(Builder, "corei7"); 3141 break; 3142 case CK_Skylake: 3143 // FIXME: Historically, we defined this legacy name, it would be nice to 3144 // remove it at some point. This is the only fine-grained CPU macro in the 3145 // main intel CPU line, and it would be better to not have these and force 3146 // people to use ISA macros. 3147 defineCPUMacros(Builder, "skx"); 3148 break; 3149 case CK_KNL: 3150 defineCPUMacros(Builder, "knl"); 3151 break; 3152 case CK_K6_2: 3153 Builder.defineMacro("__k6_2__"); 3154 Builder.defineMacro("__tune_k6_2__"); 3155 // Fallthrough 3156 case CK_K6_3: 3157 if (CPU != CK_K6_2) { // In case of fallthrough 3158 // FIXME: GCC may be enabling these in cases where some other k6 3159 // architecture is specified but -m3dnow is explicitly provided. The 3160 // exact semantics need to be determined and emulated here. 3161 Builder.defineMacro("__k6_3__"); 3162 Builder.defineMacro("__tune_k6_3__"); 3163 } 3164 // Fallthrough 3165 case CK_K6: 3166 defineCPUMacros(Builder, "k6"); 3167 break; 3168 case CK_Athlon: 3169 case CK_AthlonThunderbird: 3170 case CK_Athlon4: 3171 case CK_AthlonXP: 3172 case CK_AthlonMP: 3173 defineCPUMacros(Builder, "athlon"); 3174 if (SSELevel != NoSSE) { 3175 Builder.defineMacro("__athlon_sse__"); 3176 Builder.defineMacro("__tune_athlon_sse__"); 3177 } 3178 break; 3179 case CK_K8: 3180 case CK_K8SSE3: 3181 case CK_x86_64: 3182 case CK_Opteron: 3183 case CK_OpteronSSE3: 3184 case CK_Athlon64: 3185 case CK_Athlon64SSE3: 3186 case CK_AthlonFX: 3187 defineCPUMacros(Builder, "k8"); 3188 break; 3189 case CK_AMDFAM10: 3190 defineCPUMacros(Builder, "amdfam10"); 3191 break; 3192 case CK_BTVER1: 3193 defineCPUMacros(Builder, "btver1"); 3194 break; 3195 case CK_BTVER2: 3196 defineCPUMacros(Builder, "btver2"); 3197 break; 3198 case CK_BDVER1: 3199 defineCPUMacros(Builder, "bdver1"); 3200 break; 3201 case CK_BDVER2: 3202 defineCPUMacros(Builder, "bdver2"); 3203 break; 3204 case CK_BDVER3: 3205 defineCPUMacros(Builder, "bdver3"); 3206 break; 3207 case CK_BDVER4: 3208 defineCPUMacros(Builder, "bdver4"); 3209 break; 3210 case CK_Geode: 3211 defineCPUMacros(Builder, "geode"); 3212 break; 3213 } 3214 3215 // Target properties. 3216 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3217 3218 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3219 // functions in glibc header files that use FP Stack inline asm which the 3220 // backend can't deal with (PR879). 3221 Builder.defineMacro("__NO_MATH_INLINES"); 3222 3223 if (HasAES) 3224 Builder.defineMacro("__AES__"); 3225 3226 if (HasPCLMUL) 3227 Builder.defineMacro("__PCLMUL__"); 3228 3229 if (HasLZCNT) 3230 Builder.defineMacro("__LZCNT__"); 3231 3232 if (HasRDRND) 3233 Builder.defineMacro("__RDRND__"); 3234 3235 if (HasFSGSBASE) 3236 Builder.defineMacro("__FSGSBASE__"); 3237 3238 if (HasBMI) 3239 Builder.defineMacro("__BMI__"); 3240 3241 if (HasBMI2) 3242 Builder.defineMacro("__BMI2__"); 3243 3244 if (HasPOPCNT) 3245 Builder.defineMacro("__POPCNT__"); 3246 3247 if (HasRTM) 3248 Builder.defineMacro("__RTM__"); 3249 3250 if (HasPRFCHW) 3251 Builder.defineMacro("__PRFCHW__"); 3252 3253 if (HasRDSEED) 3254 Builder.defineMacro("__RDSEED__"); 3255 3256 if (HasADX) 3257 Builder.defineMacro("__ADX__"); 3258 3259 if (HasTBM) 3260 Builder.defineMacro("__TBM__"); 3261 3262 switch (XOPLevel) { 3263 case XOP: 3264 Builder.defineMacro("__XOP__"); 3265 case FMA4: 3266 Builder.defineMacro("__FMA4__"); 3267 case SSE4A: 3268 Builder.defineMacro("__SSE4A__"); 3269 case NoXOP: 3270 break; 3271 } 3272 3273 if (HasFMA) 3274 Builder.defineMacro("__FMA__"); 3275 3276 if (HasF16C) 3277 Builder.defineMacro("__F16C__"); 3278 3279 if (HasAVX512CD) 3280 Builder.defineMacro("__AVX512CD__"); 3281 if (HasAVX512ER) 3282 Builder.defineMacro("__AVX512ER__"); 3283 if (HasAVX512PF) 3284 Builder.defineMacro("__AVX512PF__"); 3285 if (HasAVX512DQ) 3286 Builder.defineMacro("__AVX512DQ__"); 3287 if (HasAVX512BW) 3288 Builder.defineMacro("__AVX512BW__"); 3289 if (HasAVX512VL) 3290 Builder.defineMacro("__AVX512VL__"); 3291 3292 if (HasSHA) 3293 Builder.defineMacro("__SHA__"); 3294 3295 if (HasFXSR) 3296 Builder.defineMacro("__FXSR__"); 3297 if (HasXSAVE) 3298 Builder.defineMacro("__XSAVE__"); 3299 if (HasXSAVEOPT) 3300 Builder.defineMacro("__XSAVEOPT__"); 3301 if (HasXSAVEC) 3302 Builder.defineMacro("__XSAVEC__"); 3303 if (HasXSAVES) 3304 Builder.defineMacro("__XSAVES__"); 3305 3306 if (HasCX16) 3307 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3308 3309 // Each case falls through to the previous one here. 3310 switch (SSELevel) { 3311 case AVX512F: 3312 Builder.defineMacro("__AVX512F__"); 3313 case AVX2: 3314 Builder.defineMacro("__AVX2__"); 3315 case AVX: 3316 Builder.defineMacro("__AVX__"); 3317 case SSE42: 3318 Builder.defineMacro("__SSE4_2__"); 3319 case SSE41: 3320 Builder.defineMacro("__SSE4_1__"); 3321 case SSSE3: 3322 Builder.defineMacro("__SSSE3__"); 3323 case SSE3: 3324 Builder.defineMacro("__SSE3__"); 3325 case SSE2: 3326 Builder.defineMacro("__SSE2__"); 3327 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3328 case SSE1: 3329 Builder.defineMacro("__SSE__"); 3330 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3331 case NoSSE: 3332 break; 3333 } 3334 3335 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3336 switch (SSELevel) { 3337 case AVX512F: 3338 case AVX2: 3339 case AVX: 3340 case SSE42: 3341 case SSE41: 3342 case SSSE3: 3343 case SSE3: 3344 case SSE2: 3345 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3346 break; 3347 case SSE1: 3348 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3349 break; 3350 default: 3351 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3352 } 3353 } 3354 3355 // Each case falls through to the previous one here. 3356 switch (MMX3DNowLevel) { 3357 case AMD3DNowAthlon: 3358 Builder.defineMacro("__3dNOW_A__"); 3359 case AMD3DNow: 3360 Builder.defineMacro("__3dNOW__"); 3361 case MMX: 3362 Builder.defineMacro("__MMX__"); 3363 case NoMMX3DNow: 3364 break; 3365 } 3366 3367 if (CPU >= CK_i486) { 3368 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3369 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3370 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3371 } 3372 if (CPU >= CK_i586) 3373 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3374 3375 if (getTriple().isOSIAMCU()) { 3376 Builder.defineMacro("__iamcu"); 3377 Builder.defineMacro("__iamcu__"); 3378 } 3379 } 3380 3381 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3382 return llvm::StringSwitch<bool>(Feature) 3383 .Case("aes", HasAES) 3384 .Case("avx", SSELevel >= AVX) 3385 .Case("avx2", SSELevel >= AVX2) 3386 .Case("avx512f", SSELevel >= AVX512F) 3387 .Case("avx512cd", HasAVX512CD) 3388 .Case("avx512er", HasAVX512ER) 3389 .Case("avx512pf", HasAVX512PF) 3390 .Case("avx512dq", HasAVX512DQ) 3391 .Case("avx512bw", HasAVX512BW) 3392 .Case("avx512vl", HasAVX512VL) 3393 .Case("bmi", HasBMI) 3394 .Case("bmi2", HasBMI2) 3395 .Case("cx16", HasCX16) 3396 .Case("f16c", HasF16C) 3397 .Case("fma", HasFMA) 3398 .Case("fma4", XOPLevel >= FMA4) 3399 .Case("fsgsbase", HasFSGSBASE) 3400 .Case("fxsr", HasFXSR) 3401 .Case("lzcnt", HasLZCNT) 3402 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3403 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3404 .Case("mmx", MMX3DNowLevel >= MMX) 3405 .Case("pclmul", HasPCLMUL) 3406 .Case("popcnt", HasPOPCNT) 3407 .Case("prfchw", HasPRFCHW) 3408 .Case("rdrnd", HasRDRND) 3409 .Case("rdseed", HasRDSEED) 3410 .Case("rtm", HasRTM) 3411 .Case("sha", HasSHA) 3412 .Case("sse", SSELevel >= SSE1) 3413 .Case("sse2", SSELevel >= SSE2) 3414 .Case("sse3", SSELevel >= SSE3) 3415 .Case("ssse3", SSELevel >= SSSE3) 3416 .Case("sse4.1", SSELevel >= SSE41) 3417 .Case("sse4.2", SSELevel >= SSE42) 3418 .Case("sse4a", XOPLevel >= SSE4A) 3419 .Case("tbm", HasTBM) 3420 .Case("x86", true) 3421 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3422 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3423 .Case("xop", XOPLevel >= XOP) 3424 .Case("xsave", HasXSAVE) 3425 .Case("xsavec", HasXSAVEC) 3426 .Case("xsaves", HasXSAVES) 3427 .Case("xsaveopt", HasXSAVEOPT) 3428 .Default(false); 3429 } 3430 3431 // We can't use a generic validation scheme for the features accepted here 3432 // versus subtarget features accepted in the target attribute because the 3433 // bitfield structure that's initialized in the runtime only supports the 3434 // below currently rather than the full range of subtarget features. (See 3435 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3436 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3437 return llvm::StringSwitch<bool>(FeatureStr) 3438 .Case("cmov", true) 3439 .Case("mmx", true) 3440 .Case("popcnt", true) 3441 .Case("sse", true) 3442 .Case("sse2", true) 3443 .Case("sse3", true) 3444 .Case("sse4.1", true) 3445 .Case("sse4.2", true) 3446 .Case("avx", true) 3447 .Case("avx2", true) 3448 .Case("sse4a", true) 3449 .Case("fma4", true) 3450 .Case("xop", true) 3451 .Case("fma", true) 3452 .Case("avx512f", true) 3453 .Case("bmi", true) 3454 .Case("bmi2", true) 3455 .Default(false); 3456 } 3457 3458 bool 3459 X86TargetInfo::validateAsmConstraint(const char *&Name, 3460 TargetInfo::ConstraintInfo &Info) const { 3461 switch (*Name) { 3462 default: return false; 3463 // Constant constraints. 3464 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3465 // instructions. 3466 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3467 // x86_64 instructions. 3468 case 's': 3469 Info.setRequiresImmediate(); 3470 return true; 3471 case 'I': 3472 Info.setRequiresImmediate(0, 31); 3473 return true; 3474 case 'J': 3475 Info.setRequiresImmediate(0, 63); 3476 return true; 3477 case 'K': 3478 Info.setRequiresImmediate(-128, 127); 3479 return true; 3480 case 'L': 3481 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3482 return true; 3483 case 'M': 3484 Info.setRequiresImmediate(0, 3); 3485 return true; 3486 case 'N': 3487 Info.setRequiresImmediate(0, 255); 3488 return true; 3489 case 'O': 3490 Info.setRequiresImmediate(0, 127); 3491 return true; 3492 // Register constraints. 3493 case 'Y': // 'Y' is the first character for several 2-character constraints. 3494 // Shift the pointer to the second character of the constraint. 3495 Name++; 3496 switch (*Name) { 3497 default: 3498 return false; 3499 case '0': // First SSE register. 3500 case 't': // Any SSE register, when SSE2 is enabled. 3501 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3502 case 'm': // Any MMX register, when inter-unit moves enabled. 3503 Info.setAllowsRegister(); 3504 return true; 3505 } 3506 case 'f': // Any x87 floating point stack register. 3507 // Constraint 'f' cannot be used for output operands. 3508 if (Info.ConstraintStr[0] == '=') 3509 return false; 3510 Info.setAllowsRegister(); 3511 return true; 3512 case 'a': // eax. 3513 case 'b': // ebx. 3514 case 'c': // ecx. 3515 case 'd': // edx. 3516 case 'S': // esi. 3517 case 'D': // edi. 3518 case 'A': // edx:eax. 3519 case 't': // Top of floating point stack. 3520 case 'u': // Second from top of floating point stack. 3521 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3522 case 'y': // Any MMX register. 3523 case 'x': // Any SSE register. 3524 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3525 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3526 case 'l': // "Index" registers: any general register that can be used as an 3527 // index in a base+index memory access. 3528 Info.setAllowsRegister(); 3529 return true; 3530 // Floating point constant constraints. 3531 case 'C': // SSE floating point constant. 3532 case 'G': // x87 floating point constant. 3533 return true; 3534 } 3535 } 3536 3537 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3538 unsigned Size) const { 3539 // Strip off constraint modifiers. 3540 while (Constraint[0] == '=' || 3541 Constraint[0] == '+' || 3542 Constraint[0] == '&') 3543 Constraint = Constraint.substr(1); 3544 3545 return validateOperandSize(Constraint, Size); 3546 } 3547 3548 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3549 unsigned Size) const { 3550 return validateOperandSize(Constraint, Size); 3551 } 3552 3553 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3554 unsigned Size) const { 3555 switch (Constraint[0]) { 3556 default: break; 3557 case 'y': 3558 return Size <= 64; 3559 case 'f': 3560 case 't': 3561 case 'u': 3562 return Size <= 128; 3563 case 'x': 3564 if (SSELevel >= AVX512F) 3565 // 512-bit zmm registers can be used if target supports AVX512F. 3566 return Size <= 512U; 3567 else if (SSELevel >= AVX) 3568 // 256-bit ymm registers can be used if target supports AVX. 3569 return Size <= 256U; 3570 return Size <= 128U; 3571 case 'Y': 3572 // 'Y' is the first character for several 2-character constraints. 3573 switch (Constraint[1]) { 3574 default: break; 3575 case 'm': 3576 // 'Ym' is synonymous with 'y'. 3577 return Size <= 64; 3578 case 'i': 3579 case 't': 3580 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3581 if (SSELevel >= AVX512F) 3582 return Size <= 512U; 3583 else if (SSELevel >= AVX) 3584 return Size <= 256U; 3585 return SSELevel >= SSE2 && Size <= 128U; 3586 } 3587 3588 } 3589 3590 return true; 3591 } 3592 3593 std::string 3594 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3595 switch (*Constraint) { 3596 case 'a': return std::string("{ax}"); 3597 case 'b': return std::string("{bx}"); 3598 case 'c': return std::string("{cx}"); 3599 case 'd': return std::string("{dx}"); 3600 case 'S': return std::string("{si}"); 3601 case 'D': return std::string("{di}"); 3602 case 'p': // address 3603 return std::string("im"); 3604 case 't': // top of floating point stack. 3605 return std::string("{st}"); 3606 case 'u': // second from top of floating point stack. 3607 return std::string("{st(1)}"); // second from top of floating point stack. 3608 default: 3609 return std::string(1, *Constraint); 3610 } 3611 } 3612 3613 // X86-32 generic target 3614 class X86_32TargetInfo : public X86TargetInfo { 3615 public: 3616 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3617 DoubleAlign = LongLongAlign = 32; 3618 LongDoubleWidth = 96; 3619 LongDoubleAlign = 32; 3620 SuitableAlign = 128; 3621 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3622 SizeType = UnsignedInt; 3623 PtrDiffType = SignedInt; 3624 IntPtrType = SignedInt; 3625 RegParmMax = 3; 3626 3627 // Use fpret for all types. 3628 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3629 (1 << TargetInfo::Double) | 3630 (1 << TargetInfo::LongDouble)); 3631 3632 // x86-32 has atomics up to 8 bytes 3633 // FIXME: Check that we actually have cmpxchg8b before setting 3634 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3635 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3636 } 3637 BuiltinVaListKind getBuiltinVaListKind() const override { 3638 return TargetInfo::CharPtrBuiltinVaList; 3639 } 3640 3641 int getEHDataRegisterNumber(unsigned RegNo) const override { 3642 if (RegNo == 0) return 0; 3643 if (RegNo == 1) return 2; 3644 return -1; 3645 } 3646 bool validateOperandSize(StringRef Constraint, 3647 unsigned Size) const override { 3648 switch (Constraint[0]) { 3649 default: break; 3650 case 'R': 3651 case 'q': 3652 case 'Q': 3653 case 'a': 3654 case 'b': 3655 case 'c': 3656 case 'd': 3657 case 'S': 3658 case 'D': 3659 return Size <= 32; 3660 case 'A': 3661 return Size <= 64; 3662 } 3663 3664 return X86TargetInfo::validateOperandSize(Constraint, Size); 3665 } 3666 }; 3667 3668 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3669 public: 3670 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3671 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3672 3673 unsigned getFloatEvalMethod() const override { 3674 unsigned Major, Minor, Micro; 3675 getTriple().getOSVersion(Major, Minor, Micro); 3676 // New NetBSD uses the default rounding mode. 3677 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3678 return X86_32TargetInfo::getFloatEvalMethod(); 3679 // NetBSD before 6.99.26 defaults to "double" rounding. 3680 return 1; 3681 } 3682 }; 3683 3684 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3685 public: 3686 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3687 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3688 SizeType = UnsignedLong; 3689 IntPtrType = SignedLong; 3690 PtrDiffType = SignedLong; 3691 } 3692 }; 3693 3694 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3695 public: 3696 BitrigI386TargetInfo(const llvm::Triple &Triple) 3697 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3698 SizeType = UnsignedLong; 3699 IntPtrType = SignedLong; 3700 PtrDiffType = SignedLong; 3701 } 3702 }; 3703 3704 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3705 public: 3706 DarwinI386TargetInfo(const llvm::Triple &Triple) 3707 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3708 LongDoubleWidth = 128; 3709 LongDoubleAlign = 128; 3710 SuitableAlign = 128; 3711 MaxVectorAlign = 256; 3712 // The watchOS simulator uses the builtin bool type for Objective-C. 3713 llvm::Triple T = llvm::Triple(Triple); 3714 if (T.isWatchOS()) 3715 UseSignedCharForObjCBool = false; 3716 SizeType = UnsignedLong; 3717 IntPtrType = SignedLong; 3718 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3719 HasAlignMac68kSupport = true; 3720 } 3721 3722 bool handleTargetFeatures(std::vector<std::string> &Features, 3723 DiagnosticsEngine &Diags) override { 3724 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3725 Diags)) 3726 return false; 3727 // We now know the features we have: we can decide how to align vectors. 3728 MaxVectorAlign = 3729 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3730 return true; 3731 } 3732 }; 3733 3734 // x86-32 Windows target 3735 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3736 public: 3737 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3738 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3739 WCharType = UnsignedShort; 3740 DoubleAlign = LongLongAlign = 64; 3741 bool IsWinCOFF = 3742 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3743 DataLayoutString = IsWinCOFF 3744 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3745 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3746 } 3747 void getTargetDefines(const LangOptions &Opts, 3748 MacroBuilder &Builder) const override { 3749 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3750 } 3751 }; 3752 3753 // x86-32 Windows Visual Studio target 3754 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3755 public: 3756 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3757 : WindowsX86_32TargetInfo(Triple) { 3758 LongDoubleWidth = LongDoubleAlign = 64; 3759 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3760 } 3761 void getTargetDefines(const LangOptions &Opts, 3762 MacroBuilder &Builder) const override { 3763 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3764 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3765 // The value of the following reflects processor type. 3766 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3767 // We lost the original triple, so we use the default. 3768 Builder.defineMacro("_M_IX86", "600"); 3769 } 3770 }; 3771 3772 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3773 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3774 // supports __declspec natively under -fms-extensions, but we define a no-op 3775 // __declspec macro anyway for pre-processor compatibility. 3776 if (Opts.MicrosoftExt) 3777 Builder.defineMacro("__declspec", "__declspec"); 3778 else 3779 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3780 3781 if (!Opts.MicrosoftExt) { 3782 // Provide macros for all the calling convention keywords. Provide both 3783 // single and double underscore prefixed variants. These are available on 3784 // x64 as well as x86, even though they have no effect. 3785 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3786 for (const char *CC : CCs) { 3787 std::string GCCSpelling = "__attribute__((__"; 3788 GCCSpelling += CC; 3789 GCCSpelling += "__))"; 3790 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3791 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3792 } 3793 } 3794 } 3795 3796 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3797 Builder.defineMacro("__MSVCRT__"); 3798 Builder.defineMacro("__MINGW32__"); 3799 addCygMingDefines(Opts, Builder); 3800 } 3801 3802 // x86-32 MinGW target 3803 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3804 public: 3805 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3806 : WindowsX86_32TargetInfo(Triple) {} 3807 void getTargetDefines(const LangOptions &Opts, 3808 MacroBuilder &Builder) const override { 3809 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3810 DefineStd(Builder, "WIN32", Opts); 3811 DefineStd(Builder, "WINNT", Opts); 3812 Builder.defineMacro("_X86_"); 3813 addMinGWDefines(Opts, Builder); 3814 } 3815 }; 3816 3817 // x86-32 Cygwin target 3818 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3819 public: 3820 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3821 : X86_32TargetInfo(Triple) { 3822 TLSSupported = false; 3823 WCharType = UnsignedShort; 3824 DoubleAlign = LongLongAlign = 64; 3825 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3826 } 3827 void getTargetDefines(const LangOptions &Opts, 3828 MacroBuilder &Builder) const override { 3829 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3830 Builder.defineMacro("_X86_"); 3831 Builder.defineMacro("__CYGWIN__"); 3832 Builder.defineMacro("__CYGWIN32__"); 3833 addCygMingDefines(Opts, Builder); 3834 DefineStd(Builder, "unix", Opts); 3835 if (Opts.CPlusPlus) 3836 Builder.defineMacro("_GNU_SOURCE"); 3837 } 3838 }; 3839 3840 // x86-32 Haiku target 3841 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3842 public: 3843 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3844 SizeType = UnsignedLong; 3845 IntPtrType = SignedLong; 3846 PtrDiffType = SignedLong; 3847 ProcessIDType = SignedLong; 3848 this->UserLabelPrefix = ""; 3849 this->TLSSupported = false; 3850 } 3851 void getTargetDefines(const LangOptions &Opts, 3852 MacroBuilder &Builder) const override { 3853 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3854 Builder.defineMacro("__INTEL__"); 3855 Builder.defineMacro("__HAIKU__"); 3856 } 3857 }; 3858 3859 // RTEMS Target 3860 template<typename Target> 3861 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3862 protected: 3863 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3864 MacroBuilder &Builder) const override { 3865 // RTEMS defines; list based off of gcc output 3866 3867 Builder.defineMacro("__rtems__"); 3868 Builder.defineMacro("__ELF__"); 3869 } 3870 3871 public: 3872 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3873 this->UserLabelPrefix = ""; 3874 3875 switch (Triple.getArch()) { 3876 default: 3877 case llvm::Triple::x86: 3878 // this->MCountName = ".mcount"; 3879 break; 3880 case llvm::Triple::mips: 3881 case llvm::Triple::mipsel: 3882 case llvm::Triple::ppc: 3883 case llvm::Triple::ppc64: 3884 case llvm::Triple::ppc64le: 3885 // this->MCountName = "_mcount"; 3886 break; 3887 case llvm::Triple::arm: 3888 // this->MCountName = "__mcount"; 3889 break; 3890 } 3891 } 3892 }; 3893 3894 // x86-32 RTEMS target 3895 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3896 public: 3897 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3898 SizeType = UnsignedLong; 3899 IntPtrType = SignedLong; 3900 PtrDiffType = SignedLong; 3901 this->UserLabelPrefix = ""; 3902 } 3903 void getTargetDefines(const LangOptions &Opts, 3904 MacroBuilder &Builder) const override { 3905 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3906 Builder.defineMacro("__INTEL__"); 3907 Builder.defineMacro("__rtems__"); 3908 } 3909 }; 3910 3911 // x86-64 generic target 3912 class X86_64TargetInfo : public X86TargetInfo { 3913 public: 3914 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3915 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3916 bool IsWinCOFF = 3917 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3918 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3919 LongDoubleWidth = 128; 3920 LongDoubleAlign = 128; 3921 LargeArrayMinWidth = 128; 3922 LargeArrayAlign = 128; 3923 SuitableAlign = 128; 3924 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3925 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3926 IntPtrType = IsX32 ? SignedInt : SignedLong; 3927 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3928 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3929 RegParmMax = 6; 3930 3931 // Pointers are 32-bit in x32. 3932 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3933 : IsWinCOFF 3934 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3935 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3936 3937 // Use fpret only for long double. 3938 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3939 3940 // Use fp2ret for _Complex long double. 3941 ComplexLongDoubleUsesFP2Ret = true; 3942 3943 // Make __builtin_ms_va_list available. 3944 HasBuiltinMSVaList = true; 3945 3946 // x86-64 has atomics up to 16 bytes. 3947 MaxAtomicPromoteWidth = 128; 3948 MaxAtomicInlineWidth = 128; 3949 } 3950 BuiltinVaListKind getBuiltinVaListKind() const override { 3951 return TargetInfo::X86_64ABIBuiltinVaList; 3952 } 3953 3954 int getEHDataRegisterNumber(unsigned RegNo) const override { 3955 if (RegNo == 0) return 0; 3956 if (RegNo == 1) return 1; 3957 return -1; 3958 } 3959 3960 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3961 return (CC == CC_C || 3962 CC == CC_X86VectorCall || 3963 CC == CC_IntelOclBicc || 3964 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3965 } 3966 3967 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3968 return CC_C; 3969 } 3970 3971 // for x32 we need it here explicitly 3972 bool hasInt128Type() const override { return true; } 3973 }; 3974 3975 // x86-64 Windows target 3976 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3977 public: 3978 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3979 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3980 WCharType = UnsignedShort; 3981 LongWidth = LongAlign = 32; 3982 DoubleAlign = LongLongAlign = 64; 3983 IntMaxType = SignedLongLong; 3984 Int64Type = SignedLongLong; 3985 SizeType = UnsignedLongLong; 3986 PtrDiffType = SignedLongLong; 3987 IntPtrType = SignedLongLong; 3988 this->UserLabelPrefix = ""; 3989 } 3990 3991 void getTargetDefines(const LangOptions &Opts, 3992 MacroBuilder &Builder) const override { 3993 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3994 Builder.defineMacro("_WIN64"); 3995 } 3996 3997 BuiltinVaListKind getBuiltinVaListKind() const override { 3998 return TargetInfo::CharPtrBuiltinVaList; 3999 } 4000 4001 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4002 switch (CC) { 4003 case CC_X86StdCall: 4004 case CC_X86ThisCall: 4005 case CC_X86FastCall: 4006 return CCCR_Ignore; 4007 case CC_C: 4008 case CC_X86VectorCall: 4009 case CC_IntelOclBicc: 4010 case CC_X86_64SysV: 4011 return CCCR_OK; 4012 default: 4013 return CCCR_Warning; 4014 } 4015 } 4016 }; 4017 4018 // x86-64 Windows Visual Studio target 4019 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4020 public: 4021 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4022 : WindowsX86_64TargetInfo(Triple) { 4023 LongDoubleWidth = LongDoubleAlign = 64; 4024 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4025 } 4026 void getTargetDefines(const LangOptions &Opts, 4027 MacroBuilder &Builder) const override { 4028 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4029 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4030 Builder.defineMacro("_M_X64", "100"); 4031 Builder.defineMacro("_M_AMD64", "100"); 4032 } 4033 }; 4034 4035 // x86-64 MinGW target 4036 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4037 public: 4038 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4039 : WindowsX86_64TargetInfo(Triple) { 4040 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4041 // with x86 FP ops. Weird. 4042 LongDoubleWidth = LongDoubleAlign = 128; 4043 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4044 } 4045 4046 void getTargetDefines(const LangOptions &Opts, 4047 MacroBuilder &Builder) const override { 4048 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4049 DefineStd(Builder, "WIN64", Opts); 4050 Builder.defineMacro("__MINGW64__"); 4051 addMinGWDefines(Opts, Builder); 4052 4053 // GCC defines this macro when it is using __gxx_personality_seh0. 4054 if (!Opts.SjLjExceptions) 4055 Builder.defineMacro("__SEH__"); 4056 } 4057 }; 4058 4059 // x86-64 Cygwin target 4060 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4061 public: 4062 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4063 : X86_64TargetInfo(Triple) { 4064 TLSSupported = false; 4065 WCharType = UnsignedShort; 4066 } 4067 void getTargetDefines(const LangOptions &Opts, 4068 MacroBuilder &Builder) const override { 4069 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4070 Builder.defineMacro("__x86_64__"); 4071 Builder.defineMacro("__CYGWIN__"); 4072 Builder.defineMacro("__CYGWIN64__"); 4073 addCygMingDefines(Opts, Builder); 4074 DefineStd(Builder, "unix", Opts); 4075 if (Opts.CPlusPlus) 4076 Builder.defineMacro("_GNU_SOURCE"); 4077 4078 // GCC defines this macro when it is using __gxx_personality_seh0. 4079 if (!Opts.SjLjExceptions) 4080 Builder.defineMacro("__SEH__"); 4081 } 4082 }; 4083 4084 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4085 public: 4086 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4087 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4088 Int64Type = SignedLongLong; 4089 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4090 llvm::Triple T = llvm::Triple(Triple); 4091 if (T.isiOS()) 4092 UseSignedCharForObjCBool = false; 4093 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4094 } 4095 4096 bool handleTargetFeatures(std::vector<std::string> &Features, 4097 DiagnosticsEngine &Diags) override { 4098 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4099 Diags)) 4100 return false; 4101 // We now know the features we have: we can decide how to align vectors. 4102 MaxVectorAlign = 4103 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4104 return true; 4105 } 4106 }; 4107 4108 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4109 public: 4110 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4111 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4112 IntMaxType = SignedLongLong; 4113 Int64Type = SignedLongLong; 4114 } 4115 }; 4116 4117 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4118 public: 4119 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4120 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4121 IntMaxType = SignedLongLong; 4122 Int64Type = SignedLongLong; 4123 } 4124 }; 4125 4126 class ARMTargetInfo : public TargetInfo { 4127 // Possible FPU choices. 4128 enum FPUMode { 4129 VFP2FPU = (1 << 0), 4130 VFP3FPU = (1 << 1), 4131 VFP4FPU = (1 << 2), 4132 NeonFPU = (1 << 3), 4133 FPARMV8 = (1 << 4) 4134 }; 4135 4136 // Possible HWDiv features. 4137 enum HWDivMode { 4138 HWDivThumb = (1 << 0), 4139 HWDivARM = (1 << 1) 4140 }; 4141 4142 static bool FPUModeIsVFP(FPUMode Mode) { 4143 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4144 } 4145 4146 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4147 static const char * const GCCRegNames[]; 4148 4149 std::string ABI, CPU; 4150 4151 StringRef CPUProfile; 4152 StringRef CPUAttr; 4153 4154 enum { 4155 FP_Default, 4156 FP_VFP, 4157 FP_Neon 4158 } FPMath; 4159 4160 unsigned ArchISA; 4161 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4162 unsigned ArchProfile; 4163 unsigned ArchVersion; 4164 4165 unsigned FPU : 5; 4166 4167 unsigned IsAAPCS : 1; 4168 unsigned HWDiv : 2; 4169 4170 // Initialized via features. 4171 unsigned SoftFloat : 1; 4172 unsigned SoftFloatABI : 1; 4173 4174 unsigned CRC : 1; 4175 unsigned Crypto : 1; 4176 unsigned DSP : 1; 4177 unsigned Unaligned : 1; 4178 4179 enum { 4180 LDREX_B = (1 << 0), /// byte (8-bit) 4181 LDREX_H = (1 << 1), /// half (16-bit) 4182 LDREX_W = (1 << 2), /// word (32-bit) 4183 LDREX_D = (1 << 3), /// double (64-bit) 4184 }; 4185 4186 uint32_t LDREX; 4187 4188 // ACLE 6.5.1 Hardware floating point 4189 enum { 4190 HW_FP_HP = (1 << 1), /// half (16-bit) 4191 HW_FP_SP = (1 << 2), /// single (32-bit) 4192 HW_FP_DP = (1 << 3), /// double (64-bit) 4193 }; 4194 uint32_t HW_FP; 4195 4196 static const Builtin::Info BuiltinInfo[]; 4197 4198 void setABIAAPCS() { 4199 IsAAPCS = true; 4200 4201 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4202 const llvm::Triple &T = getTriple(); 4203 4204 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4205 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4206 T.getOS() == llvm::Triple::Bitrig) 4207 SizeType = UnsignedLong; 4208 else 4209 SizeType = UnsignedInt; 4210 4211 switch (T.getOS()) { 4212 case llvm::Triple::NetBSD: 4213 WCharType = SignedInt; 4214 break; 4215 case llvm::Triple::Win32: 4216 WCharType = UnsignedShort; 4217 break; 4218 case llvm::Triple::Linux: 4219 default: 4220 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4221 WCharType = UnsignedInt; 4222 break; 4223 } 4224 4225 UseBitFieldTypeAlignment = true; 4226 4227 ZeroLengthBitfieldBoundary = 0; 4228 4229 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4230 // so set preferred for small types to 32. 4231 if (T.isOSBinFormatMachO()) { 4232 DataLayoutString = 4233 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4234 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4235 } else if (T.isOSWindows()) { 4236 assert(!BigEndian && "Windows on ARM does not support big endian"); 4237 DataLayoutString = "e" 4238 "-m:w" 4239 "-p:32:32" 4240 "-i64:64" 4241 "-v128:64:128" 4242 "-a:0:32" 4243 "-n32" 4244 "-S64"; 4245 } else if (T.isOSNaCl()) { 4246 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4247 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4248 } else { 4249 DataLayoutString = 4250 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4251 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4252 } 4253 4254 // FIXME: Enumerated types are variable width in straight AAPCS. 4255 } 4256 4257 void setABIAPCS(bool IsAAPCS16) { 4258 const llvm::Triple &T = getTriple(); 4259 4260 IsAAPCS = false; 4261 4262 if (IsAAPCS16) 4263 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4264 else 4265 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4266 4267 // size_t is unsigned int on FreeBSD. 4268 if (T.getOS() == llvm::Triple::FreeBSD) 4269 SizeType = UnsignedInt; 4270 else 4271 SizeType = UnsignedLong; 4272 4273 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4274 WCharType = SignedInt; 4275 4276 // Do not respect the alignment of bit-field types when laying out 4277 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4278 UseBitFieldTypeAlignment = false; 4279 4280 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4281 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4282 /// gcc. 4283 ZeroLengthBitfieldBoundary = 32; 4284 4285 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4286 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4287 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4288 } else if (T.isOSBinFormatMachO()) 4289 DataLayoutString = 4290 BigEndian 4291 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4292 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4293 else 4294 DataLayoutString = 4295 BigEndian 4296 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4297 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4298 4299 // FIXME: Override "preferred align" for double and long long. 4300 } 4301 4302 void setArchInfo() { 4303 StringRef ArchName = getTriple().getArchName(); 4304 4305 ArchISA = llvm::ARM::parseArchISA(ArchName); 4306 CPU = llvm::ARM::getDefaultCPU(ArchName); 4307 unsigned AK = llvm::ARM::parseArch(ArchName); 4308 if (AK != llvm::ARM::AK_INVALID) 4309 ArchKind = AK; 4310 setArchInfo(ArchKind); 4311 } 4312 4313 void setArchInfo(unsigned Kind) { 4314 StringRef SubArch; 4315 4316 // cache TargetParser info 4317 ArchKind = Kind; 4318 SubArch = llvm::ARM::getSubArch(ArchKind); 4319 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4320 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4321 4322 // cache CPU related strings 4323 CPUAttr = getCPUAttr(); 4324 CPUProfile = getCPUProfile(); 4325 } 4326 4327 void setAtomic() { 4328 // when triple does not specify a sub arch, 4329 // then we are not using inline atomics 4330 bool ShouldUseInlineAtomic = 4331 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4332 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4333 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4334 if (ArchProfile == llvm::ARM::PK_M) { 4335 MaxAtomicPromoteWidth = 32; 4336 if (ShouldUseInlineAtomic) 4337 MaxAtomicInlineWidth = 32; 4338 } 4339 else { 4340 MaxAtomicPromoteWidth = 64; 4341 if (ShouldUseInlineAtomic) 4342 MaxAtomicInlineWidth = 64; 4343 } 4344 } 4345 4346 bool isThumb() const { 4347 return (ArchISA == llvm::ARM::IK_THUMB); 4348 } 4349 4350 bool supportsThumb() const { 4351 return CPUAttr.count('T') || ArchVersion >= 6; 4352 } 4353 4354 bool supportsThumb2() const { 4355 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4356 } 4357 4358 StringRef getCPUAttr() const { 4359 // For most sub-arches, the build attribute CPU name is enough. 4360 // For Cortex variants, it's slightly different. 4361 switch(ArchKind) { 4362 default: 4363 return llvm::ARM::getCPUAttr(ArchKind); 4364 case llvm::ARM::AK_ARMV6M: 4365 case llvm::ARM::AK_ARMV6SM: 4366 case llvm::ARM::AK_ARMV6HL: 4367 return "6M"; 4368 case llvm::ARM::AK_ARMV7S: 4369 return "7S"; 4370 case llvm::ARM::AK_ARMV7: 4371 case llvm::ARM::AK_ARMV7A: 4372 case llvm::ARM::AK_ARMV7L: 4373 case llvm::ARM::AK_ARMV7HL: 4374 return "7A"; 4375 case llvm::ARM::AK_ARMV7R: 4376 return "7R"; 4377 case llvm::ARM::AK_ARMV7M: 4378 return "7M"; 4379 case llvm::ARM::AK_ARMV7EM: 4380 return "7EM"; 4381 case llvm::ARM::AK_ARMV8A: 4382 return "8A"; 4383 case llvm::ARM::AK_ARMV8_1A: 4384 return "8_1A"; 4385 } 4386 } 4387 4388 StringRef getCPUProfile() const { 4389 switch(ArchProfile) { 4390 case llvm::ARM::PK_A: 4391 return "A"; 4392 case llvm::ARM::PK_R: 4393 return "R"; 4394 case llvm::ARM::PK_M: 4395 return "M"; 4396 default: 4397 return ""; 4398 } 4399 } 4400 4401 public: 4402 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4403 : TargetInfo(Triple), FPMath(FP_Default), 4404 IsAAPCS(true), LDREX(0), HW_FP(0) { 4405 BigEndian = IsBigEndian; 4406 4407 switch (getTriple().getOS()) { 4408 case llvm::Triple::NetBSD: 4409 PtrDiffType = SignedLong; 4410 break; 4411 default: 4412 PtrDiffType = SignedInt; 4413 break; 4414 } 4415 4416 // Cache arch related info. 4417 setArchInfo(); 4418 4419 // {} in inline assembly are neon specifiers, not assembly variant 4420 // specifiers. 4421 NoAsmVariants = true; 4422 4423 // FIXME: This duplicates code from the driver that sets the -target-abi 4424 // option - this code is used if -target-abi isn't passed and should 4425 // be unified in some way. 4426 if (Triple.isOSBinFormatMachO()) { 4427 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4428 // the frontend matches that. 4429 if (Triple.getEnvironment() == llvm::Triple::EABI || 4430 Triple.getOS() == llvm::Triple::UnknownOS || 4431 StringRef(CPU).startswith("cortex-m")) { 4432 setABI("aapcs"); 4433 } else if (Triple.isWatchOS()) { 4434 setABI("aapcs16"); 4435 } else { 4436 setABI("apcs-gnu"); 4437 } 4438 } else if (Triple.isOSWindows()) { 4439 // FIXME: this is invalid for WindowsCE 4440 setABI("aapcs"); 4441 } else { 4442 // Select the default based on the platform. 4443 switch (Triple.getEnvironment()) { 4444 case llvm::Triple::Android: 4445 case llvm::Triple::GNUEABI: 4446 case llvm::Triple::GNUEABIHF: 4447 setABI("aapcs-linux"); 4448 break; 4449 case llvm::Triple::EABIHF: 4450 case llvm::Triple::EABI: 4451 setABI("aapcs"); 4452 break; 4453 case llvm::Triple::GNU: 4454 setABI("apcs-gnu"); 4455 break; 4456 default: 4457 if (Triple.getOS() == llvm::Triple::NetBSD) 4458 setABI("apcs-gnu"); 4459 else 4460 setABI("aapcs"); 4461 break; 4462 } 4463 } 4464 4465 // ARM targets default to using the ARM C++ ABI. 4466 TheCXXABI.set(TargetCXXABI::GenericARM); 4467 4468 // ARM has atomics up to 8 bytes 4469 setAtomic(); 4470 4471 // Do force alignment of members that follow zero length bitfields. If 4472 // the alignment of the zero-length bitfield is greater than the member 4473 // that follows it, `bar', `bar' will be aligned as the type of the 4474 // zero length bitfield. 4475 UseZeroLengthBitfieldAlignment = true; 4476 } 4477 4478 StringRef getABI() const override { return ABI; } 4479 4480 bool setABI(const std::string &Name) override { 4481 ABI = Name; 4482 4483 // The defaults (above) are for AAPCS, check if we need to change them. 4484 // 4485 // FIXME: We need support for -meabi... we could just mangle it into the 4486 // name. 4487 if (Name == "apcs-gnu" || Name == "aapcs16") { 4488 setABIAPCS(Name == "aapcs16"); 4489 return true; 4490 } 4491 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4492 setABIAAPCS(); 4493 return true; 4494 } 4495 return false; 4496 } 4497 4498 // FIXME: This should be based on Arch attributes, not CPU names. 4499 bool 4500 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4501 StringRef CPU, 4502 const std::vector<std::string> &FeaturesVec) const override { 4503 4504 std::vector<const char*> TargetFeatures; 4505 4506 // get default FPU features 4507 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU); 4508 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4509 4510 // get default Extension features 4511 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU); 4512 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4513 4514 for (const char *Feature : TargetFeatures) 4515 if (Feature[0] == '+') 4516 Features[Feature+1] = true; 4517 4518 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4519 } 4520 4521 bool handleTargetFeatures(std::vector<std::string> &Features, 4522 DiagnosticsEngine &Diags) override { 4523 FPU = 0; 4524 CRC = 0; 4525 Crypto = 0; 4526 DSP = 0; 4527 Unaligned = 1; 4528 SoftFloat = SoftFloatABI = false; 4529 HWDiv = 0; 4530 4531 // This does not diagnose illegal cases like having both 4532 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4533 uint32_t HW_FP_remove = 0; 4534 for (const auto &Feature : Features) { 4535 if (Feature == "+soft-float") { 4536 SoftFloat = true; 4537 } else if (Feature == "+soft-float-abi") { 4538 SoftFloatABI = true; 4539 } else if (Feature == "+vfp2") { 4540 FPU |= VFP2FPU; 4541 HW_FP |= HW_FP_SP | HW_FP_DP; 4542 } else if (Feature == "+vfp3") { 4543 FPU |= VFP3FPU; 4544 HW_FP |= HW_FP_SP | HW_FP_DP; 4545 } else if (Feature == "+vfp4") { 4546 FPU |= VFP4FPU; 4547 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4548 } else if (Feature == "+fp-armv8") { 4549 FPU |= FPARMV8; 4550 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4551 } else if (Feature == "+neon") { 4552 FPU |= NeonFPU; 4553 HW_FP |= HW_FP_SP | HW_FP_DP; 4554 } else if (Feature == "+hwdiv") { 4555 HWDiv |= HWDivThumb; 4556 } else if (Feature == "+hwdiv-arm") { 4557 HWDiv |= HWDivARM; 4558 } else if (Feature == "+crc") { 4559 CRC = 1; 4560 } else if (Feature == "+crypto") { 4561 Crypto = 1; 4562 } else if (Feature == "+dsp") { 4563 DSP = 1; 4564 } else if (Feature == "+fp-only-sp") { 4565 HW_FP_remove |= HW_FP_DP; 4566 } else if (Feature == "+strict-align") { 4567 Unaligned = 0; 4568 } else if (Feature == "+fp16") { 4569 HW_FP |= HW_FP_HP; 4570 } 4571 } 4572 HW_FP &= ~HW_FP_remove; 4573 4574 switch (ArchVersion) { 4575 case 6: 4576 if (ArchProfile == llvm::ARM::PK_M) 4577 LDREX = 0; 4578 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4579 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4580 else 4581 LDREX = LDREX_W; 4582 break; 4583 case 7: 4584 if (ArchProfile == llvm::ARM::PK_M) 4585 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4586 else 4587 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4588 break; 4589 case 8: 4590 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4591 } 4592 4593 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4594 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4595 return false; 4596 } 4597 4598 if (FPMath == FP_Neon) 4599 Features.push_back("+neonfp"); 4600 else if (FPMath == FP_VFP) 4601 Features.push_back("-neonfp"); 4602 4603 // Remove front-end specific options which the backend handles differently. 4604 auto Feature = 4605 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4606 if (Feature != Features.end()) 4607 Features.erase(Feature); 4608 4609 return true; 4610 } 4611 4612 bool hasFeature(StringRef Feature) const override { 4613 return llvm::StringSwitch<bool>(Feature) 4614 .Case("arm", true) 4615 .Case("aarch32", true) 4616 .Case("softfloat", SoftFloat) 4617 .Case("thumb", isThumb()) 4618 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4619 .Case("hwdiv", HWDiv & HWDivThumb) 4620 .Case("hwdiv-arm", HWDiv & HWDivARM) 4621 .Default(false); 4622 } 4623 4624 bool setCPU(const std::string &Name) override { 4625 if (Name != "generic") 4626 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4627 4628 if (ArchKind == llvm::ARM::AK_INVALID) 4629 return false; 4630 setAtomic(); 4631 CPU = Name; 4632 return true; 4633 } 4634 4635 bool setFPMath(StringRef Name) override; 4636 4637 void getTargetDefines(const LangOptions &Opts, 4638 MacroBuilder &Builder) const override { 4639 // Target identification. 4640 Builder.defineMacro("__arm"); 4641 Builder.defineMacro("__arm__"); 4642 4643 // Target properties. 4644 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4645 4646 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4647 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4648 if (getTriple().isWatchOS()) 4649 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4650 4651 if (!CPUAttr.empty()) 4652 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4653 4654 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4655 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4656 Builder.defineMacro("__ARM_ARCH", llvm::utostr(ArchVersion)); 4657 4658 if (ArchVersion >= 8) { 4659 // ACLE 6.5.7 Crypto Extension 4660 if (Crypto) 4661 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4662 // ACLE 6.5.8 CRC32 Extension 4663 if (CRC) 4664 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4665 // ACLE 6.5.10 Numeric Maximum and Minimum 4666 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4667 // ACLE 6.5.9 Directed Rounding 4668 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4669 } 4670 4671 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4672 // is not defined for the M-profile. 4673 // NOTE that the deffault profile is assumed to be 'A' 4674 if (CPUProfile.empty() || CPUProfile != "M") 4675 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4676 4677 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4678 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4679 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4680 if (supportsThumb2()) 4681 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4682 else if (supportsThumb()) 4683 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4684 4685 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4686 // instruction set such as ARM or Thumb. 4687 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4688 4689 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4690 4691 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4692 if (!CPUProfile.empty()) 4693 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4694 4695 // ACLE 6.4.3 Unaligned access supported in hardware 4696 if (Unaligned) 4697 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4698 4699 // ACLE 6.4.4 LDREX/STREX 4700 if (LDREX) 4701 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4702 4703 // ACLE 6.4.5 CLZ 4704 if (ArchVersion == 5 || 4705 (ArchVersion == 6 && CPUProfile != "M") || 4706 ArchVersion > 6) 4707 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4708 4709 // ACLE 6.5.1 Hardware Floating Point 4710 if (HW_FP) 4711 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4712 4713 // ACLE predefines. 4714 Builder.defineMacro("__ARM_ACLE", "200"); 4715 4716 // FP16 support (we currently only support IEEE format). 4717 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4718 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4719 4720 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4721 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4722 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4723 4724 // Subtarget options. 4725 4726 // FIXME: It's more complicated than this and we don't really support 4727 // interworking. 4728 // Windows on ARM does not "support" interworking 4729 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4730 Builder.defineMacro("__THUMB_INTERWORK__"); 4731 4732 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4733 // Embedded targets on Darwin follow AAPCS, but not EABI. 4734 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4735 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4736 Builder.defineMacro("__ARM_EABI__"); 4737 Builder.defineMacro("__ARM_PCS", "1"); 4738 4739 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4740 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4741 } 4742 4743 if (SoftFloat) 4744 Builder.defineMacro("__SOFTFP__"); 4745 4746 if (CPU == "xscale") 4747 Builder.defineMacro("__XSCALE__"); 4748 4749 if (isThumb()) { 4750 Builder.defineMacro("__THUMBEL__"); 4751 Builder.defineMacro("__thumb__"); 4752 if (supportsThumb2()) 4753 Builder.defineMacro("__thumb2__"); 4754 } 4755 4756 // ACLE 6.4.9 32-bit SIMD instructions 4757 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4758 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4759 4760 // ACLE 6.4.10 Hardware Integer Divide 4761 if (((HWDiv & HWDivThumb) && isThumb()) || 4762 ((HWDiv & HWDivARM) && !isThumb())) { 4763 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4764 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4765 } 4766 4767 // Note, this is always on in gcc, even though it doesn't make sense. 4768 Builder.defineMacro("__APCS_32__"); 4769 4770 if (FPUModeIsVFP((FPUMode) FPU)) { 4771 Builder.defineMacro("__VFP_FP__"); 4772 if (FPU & VFP2FPU) 4773 Builder.defineMacro("__ARM_VFPV2__"); 4774 if (FPU & VFP3FPU) 4775 Builder.defineMacro("__ARM_VFPV3__"); 4776 if (FPU & VFP4FPU) 4777 Builder.defineMacro("__ARM_VFPV4__"); 4778 } 4779 4780 // This only gets set when Neon instructions are actually available, unlike 4781 // the VFP define, hence the soft float and arch check. This is subtly 4782 // different from gcc, we follow the intent which was that it should be set 4783 // when Neon instructions are actually available. 4784 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4785 Builder.defineMacro("__ARM_NEON", "1"); 4786 Builder.defineMacro("__ARM_NEON__"); 4787 // current AArch32 NEON implementations do not support double-precision 4788 // floating-point even when it is present in VFP. 4789 Builder.defineMacro("__ARM_NEON_FP", 4790 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4791 } 4792 4793 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4794 Opts.ShortWChar ? "2" : "4"); 4795 4796 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4797 Opts.ShortEnums ? "1" : "4"); 4798 4799 if (ArchVersion >= 6 && CPUAttr != "6M") { 4800 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4801 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4802 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4803 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4804 } 4805 4806 // ACLE 6.4.7 DSP instructions 4807 if (DSP) { 4808 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4809 } 4810 4811 // ACLE 6.4.8 Saturation instructions 4812 bool SAT = false; 4813 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4814 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4815 SAT = true; 4816 } 4817 4818 // ACLE 6.4.6 Q (saturation) flag 4819 if (DSP || SAT) 4820 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4821 4822 if (Opts.UnsafeFPMath) 4823 Builder.defineMacro("__ARM_FP_FAST", "1"); 4824 } 4825 4826 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4827 return llvm::makeArrayRef(BuiltinInfo, 4828 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4829 } 4830 bool isCLZForZeroUndef() const override { return false; } 4831 BuiltinVaListKind getBuiltinVaListKind() const override { 4832 return IsAAPCS 4833 ? AAPCSABIBuiltinVaList 4834 : (getTriple().isWatchOS() ? TargetInfo::CharPtrBuiltinVaList 4835 : TargetInfo::VoidPtrBuiltinVaList); 4836 } 4837 ArrayRef<const char *> getGCCRegNames() const override; 4838 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 4839 bool validateAsmConstraint(const char *&Name, 4840 TargetInfo::ConstraintInfo &Info) const override { 4841 switch (*Name) { 4842 default: break; 4843 case 'l': // r0-r7 4844 case 'h': // r8-r15 4845 case 'w': // VFP Floating point register single precision 4846 case 'P': // VFP Floating point register double precision 4847 Info.setAllowsRegister(); 4848 return true; 4849 case 'I': 4850 case 'J': 4851 case 'K': 4852 case 'L': 4853 case 'M': 4854 // FIXME 4855 return true; 4856 case 'Q': // A memory address that is a single base register. 4857 Info.setAllowsMemory(); 4858 return true; 4859 case 'U': // a memory reference... 4860 switch (Name[1]) { 4861 case 'q': // ...ARMV4 ldrsb 4862 case 'v': // ...VFP load/store (reg+constant offset) 4863 case 'y': // ...iWMMXt load/store 4864 case 't': // address valid for load/store opaque types wider 4865 // than 128-bits 4866 case 'n': // valid address for Neon doubleword vector load/store 4867 case 'm': // valid address for Neon element and structure load/store 4868 case 's': // valid address for non-offset loads/stores of quad-word 4869 // values in four ARM registers 4870 Info.setAllowsMemory(); 4871 Name++; 4872 return true; 4873 } 4874 } 4875 return false; 4876 } 4877 std::string convertConstraint(const char *&Constraint) const override { 4878 std::string R; 4879 switch (*Constraint) { 4880 case 'U': // Two-character constraint; add "^" hint for later parsing. 4881 R = std::string("^") + std::string(Constraint, 2); 4882 Constraint++; 4883 break; 4884 case 'p': // 'p' should be translated to 'r' by default. 4885 R = std::string("r"); 4886 break; 4887 default: 4888 return std::string(1, *Constraint); 4889 } 4890 return R; 4891 } 4892 bool 4893 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4894 std::string &SuggestedModifier) const override { 4895 bool isOutput = (Constraint[0] == '='); 4896 bool isInOut = (Constraint[0] == '+'); 4897 4898 // Strip off constraint modifiers. 4899 while (Constraint[0] == '=' || 4900 Constraint[0] == '+' || 4901 Constraint[0] == '&') 4902 Constraint = Constraint.substr(1); 4903 4904 switch (Constraint[0]) { 4905 default: break; 4906 case 'r': { 4907 switch (Modifier) { 4908 default: 4909 return (isInOut || isOutput || Size <= 64); 4910 case 'q': 4911 // A register of size 32 cannot fit a vector type. 4912 return false; 4913 } 4914 } 4915 } 4916 4917 return true; 4918 } 4919 const char *getClobbers() const override { 4920 // FIXME: Is this really right? 4921 return ""; 4922 } 4923 4924 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4925 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4926 } 4927 4928 int getEHDataRegisterNumber(unsigned RegNo) const override { 4929 if (RegNo == 0) return 0; 4930 if (RegNo == 1) return 1; 4931 return -1; 4932 } 4933 4934 bool hasSjLjLowering() const override { 4935 return true; 4936 } 4937 }; 4938 4939 bool ARMTargetInfo::setFPMath(StringRef Name) { 4940 if (Name == "neon") { 4941 FPMath = FP_Neon; 4942 return true; 4943 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4944 Name == "vfp4") { 4945 FPMath = FP_VFP; 4946 return true; 4947 } 4948 return false; 4949 } 4950 4951 const char * const ARMTargetInfo::GCCRegNames[] = { 4952 // Integer registers 4953 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4954 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4955 4956 // Float registers 4957 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4958 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4959 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4960 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4961 4962 // Double registers 4963 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4964 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4965 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4966 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4967 4968 // Quad registers 4969 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4970 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4971 }; 4972 4973 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 4974 return llvm::makeArrayRef(GCCRegNames); 4975 } 4976 4977 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4978 { { "a1" }, "r0" }, 4979 { { "a2" }, "r1" }, 4980 { { "a3" }, "r2" }, 4981 { { "a4" }, "r3" }, 4982 { { "v1" }, "r4" }, 4983 { { "v2" }, "r5" }, 4984 { { "v3" }, "r6" }, 4985 { { "v4" }, "r7" }, 4986 { { "v5" }, "r8" }, 4987 { { "v6", "rfp" }, "r9" }, 4988 { { "sl" }, "r10" }, 4989 { { "fp" }, "r11" }, 4990 { { "ip" }, "r12" }, 4991 { { "r13" }, "sp" }, 4992 { { "r14" }, "lr" }, 4993 { { "r15" }, "pc" }, 4994 // The S, D and Q registers overlap, but aren't really aliases; we 4995 // don't want to substitute one of these for a different-sized one. 4996 }; 4997 4998 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 4999 return llvm::makeArrayRef(GCCRegAliases); 5000 } 5001 5002 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5003 #define BUILTIN(ID, TYPE, ATTRS) \ 5004 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5005 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5006 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5007 #include "clang/Basic/BuiltinsNEON.def" 5008 5009 #define BUILTIN(ID, TYPE, ATTRS) \ 5010 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5011 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5012 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5013 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5014 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5015 #include "clang/Basic/BuiltinsARM.def" 5016 }; 5017 5018 class ARMleTargetInfo : public ARMTargetInfo { 5019 public: 5020 ARMleTargetInfo(const llvm::Triple &Triple) 5021 : ARMTargetInfo(Triple, false) { } 5022 void getTargetDefines(const LangOptions &Opts, 5023 MacroBuilder &Builder) const override { 5024 Builder.defineMacro("__ARMEL__"); 5025 ARMTargetInfo::getTargetDefines(Opts, Builder); 5026 } 5027 }; 5028 5029 class ARMbeTargetInfo : public ARMTargetInfo { 5030 public: 5031 ARMbeTargetInfo(const llvm::Triple &Triple) 5032 : ARMTargetInfo(Triple, true) { } 5033 void getTargetDefines(const LangOptions &Opts, 5034 MacroBuilder &Builder) const override { 5035 Builder.defineMacro("__ARMEB__"); 5036 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5037 ARMTargetInfo::getTargetDefines(Opts, Builder); 5038 } 5039 }; 5040 5041 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5042 const llvm::Triple Triple; 5043 public: 5044 WindowsARMTargetInfo(const llvm::Triple &Triple) 5045 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5046 TLSSupported = false; 5047 WCharType = UnsignedShort; 5048 SizeType = UnsignedInt; 5049 UserLabelPrefix = ""; 5050 } 5051 void getVisualStudioDefines(const LangOptions &Opts, 5052 MacroBuilder &Builder) const { 5053 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5054 5055 // FIXME: this is invalid for WindowsCE 5056 Builder.defineMacro("_M_ARM_NT", "1"); 5057 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5058 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5059 5060 assert((Triple.getArch() == llvm::Triple::arm || 5061 Triple.getArch() == llvm::Triple::thumb) && 5062 "invalid architecture for Windows ARM target info"); 5063 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5064 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5065 5066 // TODO map the complete set of values 5067 // 31: VFPv3 40: VFPv4 5068 Builder.defineMacro("_M_ARM_FP", "31"); 5069 } 5070 BuiltinVaListKind getBuiltinVaListKind() const override { 5071 return TargetInfo::CharPtrBuiltinVaList; 5072 } 5073 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5074 switch (CC) { 5075 case CC_X86StdCall: 5076 case CC_X86ThisCall: 5077 case CC_X86FastCall: 5078 case CC_X86VectorCall: 5079 return CCCR_Ignore; 5080 case CC_C: 5081 return CCCR_OK; 5082 default: 5083 return CCCR_Warning; 5084 } 5085 } 5086 }; 5087 5088 // Windows ARM + Itanium C++ ABI Target 5089 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5090 public: 5091 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5092 : WindowsARMTargetInfo(Triple) { 5093 TheCXXABI.set(TargetCXXABI::GenericARM); 5094 } 5095 5096 void getTargetDefines(const LangOptions &Opts, 5097 MacroBuilder &Builder) const override { 5098 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5099 5100 if (Opts.MSVCCompat) 5101 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5102 } 5103 }; 5104 5105 // Windows ARM, MS (C++) ABI 5106 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5107 public: 5108 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5109 : WindowsARMTargetInfo(Triple) { 5110 TheCXXABI.set(TargetCXXABI::Microsoft); 5111 } 5112 5113 void getTargetDefines(const LangOptions &Opts, 5114 MacroBuilder &Builder) const override { 5115 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5116 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5117 } 5118 }; 5119 5120 // ARM MinGW target 5121 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5122 public: 5123 MinGWARMTargetInfo(const llvm::Triple &Triple) 5124 : WindowsARMTargetInfo(Triple) { 5125 TheCXXABI.set(TargetCXXABI::GenericARM); 5126 } 5127 5128 void getTargetDefines(const LangOptions &Opts, 5129 MacroBuilder &Builder) const override { 5130 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5131 DefineStd(Builder, "WIN32", Opts); 5132 DefineStd(Builder, "WINNT", Opts); 5133 Builder.defineMacro("_ARM_"); 5134 addMinGWDefines(Opts, Builder); 5135 } 5136 }; 5137 5138 // ARM Cygwin target 5139 class CygwinARMTargetInfo : public ARMleTargetInfo { 5140 public: 5141 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5142 TLSSupported = false; 5143 WCharType = UnsignedShort; 5144 DoubleAlign = LongLongAlign = 64; 5145 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5146 } 5147 void getTargetDefines(const LangOptions &Opts, 5148 MacroBuilder &Builder) const override { 5149 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5150 Builder.defineMacro("_ARM_"); 5151 Builder.defineMacro("__CYGWIN__"); 5152 Builder.defineMacro("__CYGWIN32__"); 5153 DefineStd(Builder, "unix", Opts); 5154 if (Opts.CPlusPlus) 5155 Builder.defineMacro("_GNU_SOURCE"); 5156 } 5157 }; 5158 5159 class DarwinARMTargetInfo : 5160 public DarwinTargetInfo<ARMleTargetInfo> { 5161 protected: 5162 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5163 MacroBuilder &Builder) const override { 5164 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5165 } 5166 5167 public: 5168 DarwinARMTargetInfo(const llvm::Triple &Triple) 5169 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5170 HasAlignMac68kSupport = true; 5171 // iOS always has 64-bit atomic instructions. 5172 // FIXME: This should be based off of the target features in 5173 // ARMleTargetInfo. 5174 MaxAtomicInlineWidth = 64; 5175 5176 if (Triple.isWatchOS()) { 5177 // Darwin on iOS uses a variant of the ARM C++ ABI. 5178 TheCXXABI.set(TargetCXXABI::WatchOS); 5179 5180 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5181 // size_t is long, it's a bit weird for it to be int. 5182 PtrDiffType = SignedLong; 5183 5184 // BOOL should be a real boolean on the new ABI 5185 UseSignedCharForObjCBool = false; 5186 } else 5187 TheCXXABI.set(TargetCXXABI::iOS); 5188 } 5189 }; 5190 5191 class AArch64TargetInfo : public TargetInfo { 5192 virtual void setDataLayoutString() = 0; 5193 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5194 static const char *const GCCRegNames[]; 5195 5196 enum FPUModeEnum { 5197 FPUMode, 5198 NeonMode 5199 }; 5200 5201 unsigned FPU; 5202 unsigned CRC; 5203 unsigned Crypto; 5204 unsigned Unaligned; 5205 5206 static const Builtin::Info BuiltinInfo[]; 5207 5208 std::string ABI; 5209 5210 public: 5211 AArch64TargetInfo(const llvm::Triple &Triple) 5212 : TargetInfo(Triple), ABI("aapcs") { 5213 5214 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5215 WCharType = SignedInt; 5216 5217 // NetBSD apparently prefers consistency across ARM targets to consistency 5218 // across 64-bit targets. 5219 Int64Type = SignedLongLong; 5220 IntMaxType = SignedLongLong; 5221 } else { 5222 WCharType = UnsignedInt; 5223 Int64Type = SignedLong; 5224 IntMaxType = SignedLong; 5225 } 5226 5227 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5228 MaxVectorAlign = 128; 5229 MaxAtomicInlineWidth = 128; 5230 MaxAtomicPromoteWidth = 128; 5231 5232 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5233 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5234 5235 // {} in inline assembly are neon specifiers, not assembly variant 5236 // specifiers. 5237 NoAsmVariants = true; 5238 5239 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5240 // contributes to the alignment of the containing aggregate in the same way 5241 // a plain (non bit-field) member of that type would, without exception for 5242 // zero-sized or anonymous bit-fields." 5243 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5244 UseZeroLengthBitfieldAlignment = true; 5245 5246 // AArch64 targets default to using the ARM C++ ABI. 5247 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5248 } 5249 5250 StringRef getABI() const override { return ABI; } 5251 bool setABI(const std::string &Name) override { 5252 if (Name != "aapcs" && Name != "darwinpcs") 5253 return false; 5254 5255 ABI = Name; 5256 return true; 5257 } 5258 5259 bool setCPU(const std::string &Name) override { 5260 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5261 .Case("generic", true) 5262 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 5263 .Case("cyclone", true) 5264 .Default(false); 5265 return CPUKnown; 5266 } 5267 5268 void getTargetDefines(const LangOptions &Opts, 5269 MacroBuilder &Builder) const override { 5270 // Target identification. 5271 Builder.defineMacro("__aarch64__"); 5272 5273 // Target properties. 5274 Builder.defineMacro("_LP64"); 5275 Builder.defineMacro("__LP64__"); 5276 5277 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5278 Builder.defineMacro("__ARM_ACLE", "200"); 5279 Builder.defineMacro("__ARM_ARCH", "8"); 5280 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5281 5282 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5283 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5284 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5285 5286 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5287 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5288 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5289 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5290 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5291 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5292 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5293 5294 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5295 5296 // 0xe implies support for half, single and double precision operations. 5297 Builder.defineMacro("__ARM_FP", "0xE"); 5298 5299 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5300 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5301 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5302 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5303 5304 if (Opts.UnsafeFPMath) 5305 Builder.defineMacro("__ARM_FP_FAST", "1"); 5306 5307 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5308 5309 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5310 Opts.ShortEnums ? "1" : "4"); 5311 5312 if (FPU == NeonMode) { 5313 Builder.defineMacro("__ARM_NEON", "1"); 5314 // 64-bit NEON supports half, single and double precision operations. 5315 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5316 } 5317 5318 if (CRC) 5319 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5320 5321 if (Crypto) 5322 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5323 5324 if (Unaligned) 5325 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5326 5327 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5328 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5329 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5330 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5332 } 5333 5334 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5335 return llvm::makeArrayRef(BuiltinInfo, 5336 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5337 } 5338 5339 bool hasFeature(StringRef Feature) const override { 5340 return Feature == "aarch64" || 5341 Feature == "arm64" || 5342 Feature == "arm" || 5343 (Feature == "neon" && FPU == NeonMode); 5344 } 5345 5346 bool handleTargetFeatures(std::vector<std::string> &Features, 5347 DiagnosticsEngine &Diags) override { 5348 FPU = FPUMode; 5349 CRC = 0; 5350 Crypto = 0; 5351 Unaligned = 1; 5352 5353 for (const auto &Feature : Features) { 5354 if (Feature == "+neon") 5355 FPU = NeonMode; 5356 if (Feature == "+crc") 5357 CRC = 1; 5358 if (Feature == "+crypto") 5359 Crypto = 1; 5360 if (Feature == "+strict-align") 5361 Unaligned = 0; 5362 } 5363 5364 setDataLayoutString(); 5365 5366 return true; 5367 } 5368 5369 bool isCLZForZeroUndef() const override { return false; } 5370 5371 BuiltinVaListKind getBuiltinVaListKind() const override { 5372 return TargetInfo::AArch64ABIBuiltinVaList; 5373 } 5374 5375 ArrayRef<const char *> getGCCRegNames() const override; 5376 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5377 5378 bool validateAsmConstraint(const char *&Name, 5379 TargetInfo::ConstraintInfo &Info) const override { 5380 switch (*Name) { 5381 default: 5382 return false; 5383 case 'w': // Floating point and SIMD registers (V0-V31) 5384 Info.setAllowsRegister(); 5385 return true; 5386 case 'I': // Constant that can be used with an ADD instruction 5387 case 'J': // Constant that can be used with a SUB instruction 5388 case 'K': // Constant that can be used with a 32-bit logical instruction 5389 case 'L': // Constant that can be used with a 64-bit logical instruction 5390 case 'M': // Constant that can be used as a 32-bit MOV immediate 5391 case 'N': // Constant that can be used as a 64-bit MOV immediate 5392 case 'Y': // Floating point constant zero 5393 case 'Z': // Integer constant zero 5394 return true; 5395 case 'Q': // A memory reference with base register and no offset 5396 Info.setAllowsMemory(); 5397 return true; 5398 case 'S': // A symbolic address 5399 Info.setAllowsRegister(); 5400 return true; 5401 case 'U': 5402 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5403 // Utf: A memory address suitable for ldp/stp in TF mode. 5404 // Usa: An absolute symbolic address. 5405 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5406 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5407 case 'z': // Zero register, wzr or xzr 5408 Info.setAllowsRegister(); 5409 return true; 5410 case 'x': // Floating point and SIMD registers (V0-V15) 5411 Info.setAllowsRegister(); 5412 return true; 5413 } 5414 return false; 5415 } 5416 5417 bool 5418 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5419 std::string &SuggestedModifier) const override { 5420 // Strip off constraint modifiers. 5421 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5422 Constraint = Constraint.substr(1); 5423 5424 switch (Constraint[0]) { 5425 default: 5426 return true; 5427 case 'z': 5428 case 'r': { 5429 switch (Modifier) { 5430 case 'x': 5431 case 'w': 5432 // For now assume that the person knows what they're 5433 // doing with the modifier. 5434 return true; 5435 default: 5436 // By default an 'r' constraint will be in the 'x' 5437 // registers. 5438 if (Size == 64) 5439 return true; 5440 5441 SuggestedModifier = "w"; 5442 return false; 5443 } 5444 } 5445 } 5446 } 5447 5448 const char *getClobbers() const override { return ""; } 5449 5450 int getEHDataRegisterNumber(unsigned RegNo) const override { 5451 if (RegNo == 0) 5452 return 0; 5453 if (RegNo == 1) 5454 return 1; 5455 return -1; 5456 } 5457 }; 5458 5459 const char *const AArch64TargetInfo::GCCRegNames[] = { 5460 // 32-bit Integer registers 5461 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5462 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5463 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5464 5465 // 64-bit Integer registers 5466 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5467 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5468 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5469 5470 // 32-bit floating point regsisters 5471 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5472 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5473 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5474 5475 // 64-bit floating point regsisters 5476 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5477 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5478 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5479 5480 // Vector registers 5481 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5482 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5483 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5484 }; 5485 5486 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5487 return llvm::makeArrayRef(GCCRegNames); 5488 } 5489 5490 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5491 { { "w31" }, "wsp" }, 5492 { { "x29" }, "fp" }, 5493 { { "x30" }, "lr" }, 5494 { { "x31" }, "sp" }, 5495 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5496 // don't want to substitute one of these for a different-sized one. 5497 }; 5498 5499 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5500 return llvm::makeArrayRef(GCCRegAliases); 5501 } 5502 5503 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5504 #define BUILTIN(ID, TYPE, ATTRS) \ 5505 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5506 #include "clang/Basic/BuiltinsNEON.def" 5507 5508 #define BUILTIN(ID, TYPE, ATTRS) \ 5509 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5510 #include "clang/Basic/BuiltinsAArch64.def" 5511 }; 5512 5513 class AArch64leTargetInfo : public AArch64TargetInfo { 5514 void setDataLayoutString() override { 5515 if (getTriple().isOSBinFormatMachO()) 5516 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5517 else 5518 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5519 } 5520 5521 public: 5522 AArch64leTargetInfo(const llvm::Triple &Triple) 5523 : AArch64TargetInfo(Triple) { 5524 BigEndian = false; 5525 } 5526 void getTargetDefines(const LangOptions &Opts, 5527 MacroBuilder &Builder) const override { 5528 Builder.defineMacro("__AARCH64EL__"); 5529 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5530 } 5531 }; 5532 5533 class AArch64beTargetInfo : public AArch64TargetInfo { 5534 void setDataLayoutString() override { 5535 assert(!getTriple().isOSBinFormatMachO()); 5536 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5537 } 5538 5539 public: 5540 AArch64beTargetInfo(const llvm::Triple &Triple) 5541 : AArch64TargetInfo(Triple) { } 5542 void getTargetDefines(const LangOptions &Opts, 5543 MacroBuilder &Builder) const override { 5544 Builder.defineMacro("__AARCH64EB__"); 5545 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5546 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5547 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5548 } 5549 }; 5550 5551 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5552 protected: 5553 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5554 MacroBuilder &Builder) const override { 5555 Builder.defineMacro("__AARCH64_SIMD__"); 5556 Builder.defineMacro("__ARM64_ARCH_8__"); 5557 Builder.defineMacro("__ARM_NEON__"); 5558 Builder.defineMacro("__LITTLE_ENDIAN__"); 5559 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5560 Builder.defineMacro("__arm64", "1"); 5561 Builder.defineMacro("__arm64__", "1"); 5562 5563 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5564 } 5565 5566 public: 5567 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5568 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5569 Int64Type = SignedLongLong; 5570 WCharType = SignedInt; 5571 UseSignedCharForObjCBool = false; 5572 5573 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5574 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5575 5576 TheCXXABI.set(TargetCXXABI::iOS64); 5577 } 5578 5579 BuiltinVaListKind getBuiltinVaListKind() const override { 5580 return TargetInfo::CharPtrBuiltinVaList; 5581 } 5582 }; 5583 5584 // Hexagon abstract base class 5585 class HexagonTargetInfo : public TargetInfo { 5586 static const Builtin::Info BuiltinInfo[]; 5587 static const char * const GCCRegNames[]; 5588 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5589 std::string CPU; 5590 public: 5591 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5592 BigEndian = false; 5593 DataLayoutString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5594 5595 // {} in inline assembly are packet specifiers, not assembly variant 5596 // specifiers. 5597 NoAsmVariants = true; 5598 } 5599 5600 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5601 return llvm::makeArrayRef(BuiltinInfo, 5602 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5603 } 5604 5605 bool validateAsmConstraint(const char *&Name, 5606 TargetInfo::ConstraintInfo &Info) const override { 5607 return true; 5608 } 5609 5610 void getTargetDefines(const LangOptions &Opts, 5611 MacroBuilder &Builder) const override; 5612 5613 bool hasFeature(StringRef Feature) const override { 5614 return Feature == "hexagon"; 5615 } 5616 5617 BuiltinVaListKind getBuiltinVaListKind() const override { 5618 return TargetInfo::CharPtrBuiltinVaList; 5619 } 5620 ArrayRef<const char *> getGCCRegNames() const override; 5621 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5622 const char *getClobbers() const override { 5623 return ""; 5624 } 5625 5626 static const char *getHexagonCPUSuffix(StringRef Name) { 5627 return llvm::StringSwitch<const char*>(Name) 5628 .Case("hexagonv4", "4") 5629 .Case("hexagonv5", "5") 5630 .Default(nullptr); 5631 } 5632 5633 bool setCPU(const std::string &Name) override { 5634 if (!getHexagonCPUSuffix(Name)) 5635 return false; 5636 5637 CPU = Name; 5638 return true; 5639 } 5640 }; 5641 5642 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5643 MacroBuilder &Builder) const { 5644 Builder.defineMacro("qdsp6"); 5645 Builder.defineMacro("__qdsp6", "1"); 5646 Builder.defineMacro("__qdsp6__", "1"); 5647 5648 Builder.defineMacro("hexagon"); 5649 Builder.defineMacro("__hexagon", "1"); 5650 Builder.defineMacro("__hexagon__", "1"); 5651 5652 if(CPU == "hexagonv1") { 5653 Builder.defineMacro("__HEXAGON_V1__"); 5654 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5655 if(Opts.HexagonQdsp6Compat) { 5656 Builder.defineMacro("__QDSP6_V1__"); 5657 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5658 } 5659 } 5660 else if(CPU == "hexagonv2") { 5661 Builder.defineMacro("__HEXAGON_V2__"); 5662 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5663 if(Opts.HexagonQdsp6Compat) { 5664 Builder.defineMacro("__QDSP6_V2__"); 5665 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5666 } 5667 } 5668 else if(CPU == "hexagonv3") { 5669 Builder.defineMacro("__HEXAGON_V3__"); 5670 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5671 if(Opts.HexagonQdsp6Compat) { 5672 Builder.defineMacro("__QDSP6_V3__"); 5673 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5674 } 5675 } 5676 else if(CPU == "hexagonv4") { 5677 Builder.defineMacro("__HEXAGON_V4__"); 5678 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5679 if(Opts.HexagonQdsp6Compat) { 5680 Builder.defineMacro("__QDSP6_V4__"); 5681 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5682 } 5683 } 5684 else if(CPU == "hexagonv5") { 5685 Builder.defineMacro("__HEXAGON_V5__"); 5686 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5687 if(Opts.HexagonQdsp6Compat) { 5688 Builder.defineMacro("__QDSP6_V5__"); 5689 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5690 } 5691 } 5692 } 5693 5694 const char * const HexagonTargetInfo::GCCRegNames[] = { 5695 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5696 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5697 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5698 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5699 "p0", "p1", "p2", "p3", 5700 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5701 }; 5702 5703 ArrayRef<const char *> HexagonTargetInfo::getGCCRegNames() const { 5704 return llvm::makeArrayRef(GCCRegNames); 5705 } 5706 5707 5708 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5709 { { "sp" }, "r29" }, 5710 { { "fp" }, "r30" }, 5711 { { "lr" }, "r31" }, 5712 }; 5713 5714 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5715 return llvm::makeArrayRef(GCCRegAliases); 5716 } 5717 5718 5719 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5720 #define BUILTIN(ID, TYPE, ATTRS) \ 5721 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5722 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5723 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5724 #include "clang/Basic/BuiltinsHexagon.def" 5725 }; 5726 5727 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5728 class SparcTargetInfo : public TargetInfo { 5729 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5730 static const char * const GCCRegNames[]; 5731 bool SoftFloat; 5732 public: 5733 SparcTargetInfo(const llvm::Triple &Triple) 5734 : TargetInfo(Triple), SoftFloat(false) {} 5735 5736 bool handleTargetFeatures(std::vector<std::string> &Features, 5737 DiagnosticsEngine &Diags) override { 5738 // The backend doesn't actually handle soft float yet, but in case someone 5739 // is using the support for the front end continue to support it. 5740 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5741 if (Feature != Features.end()) { 5742 SoftFloat = true; 5743 Features.erase(Feature); 5744 } 5745 return true; 5746 } 5747 void getTargetDefines(const LangOptions &Opts, 5748 MacroBuilder &Builder) const override { 5749 DefineStd(Builder, "sparc", Opts); 5750 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5751 5752 if (SoftFloat) 5753 Builder.defineMacro("SOFT_FLOAT", "1"); 5754 } 5755 5756 bool hasFeature(StringRef Feature) const override { 5757 return llvm::StringSwitch<bool>(Feature) 5758 .Case("softfloat", SoftFloat) 5759 .Case("sparc", true) 5760 .Default(false); 5761 } 5762 5763 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5764 // FIXME: Implement! 5765 return None; 5766 } 5767 BuiltinVaListKind getBuiltinVaListKind() const override { 5768 return TargetInfo::VoidPtrBuiltinVaList; 5769 } 5770 ArrayRef<const char *> getGCCRegNames() const override; 5771 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5772 bool validateAsmConstraint(const char *&Name, 5773 TargetInfo::ConstraintInfo &info) const override { 5774 // FIXME: Implement! 5775 switch (*Name) { 5776 case 'I': // Signed 13-bit constant 5777 case 'J': // Zero 5778 case 'K': // 32-bit constant with the low 12 bits clear 5779 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5780 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5781 case 'N': // Same as 'K' but zext (required for SIMode) 5782 case 'O': // The constant 4096 5783 return true; 5784 } 5785 return false; 5786 } 5787 const char *getClobbers() const override { 5788 // FIXME: Implement! 5789 return ""; 5790 } 5791 }; 5792 5793 const char * const SparcTargetInfo::GCCRegNames[] = { 5794 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5795 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5796 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5797 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5798 }; 5799 5800 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 5801 return llvm::makeArrayRef(GCCRegNames); 5802 } 5803 5804 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5805 { { "g0" }, "r0" }, 5806 { { "g1" }, "r1" }, 5807 { { "g2" }, "r2" }, 5808 { { "g3" }, "r3" }, 5809 { { "g4" }, "r4" }, 5810 { { "g5" }, "r5" }, 5811 { { "g6" }, "r6" }, 5812 { { "g7" }, "r7" }, 5813 { { "o0" }, "r8" }, 5814 { { "o1" }, "r9" }, 5815 { { "o2" }, "r10" }, 5816 { { "o3" }, "r11" }, 5817 { { "o4" }, "r12" }, 5818 { { "o5" }, "r13" }, 5819 { { "o6", "sp" }, "r14" }, 5820 { { "o7" }, "r15" }, 5821 { { "l0" }, "r16" }, 5822 { { "l1" }, "r17" }, 5823 { { "l2" }, "r18" }, 5824 { { "l3" }, "r19" }, 5825 { { "l4" }, "r20" }, 5826 { { "l5" }, "r21" }, 5827 { { "l6" }, "r22" }, 5828 { { "l7" }, "r23" }, 5829 { { "i0" }, "r24" }, 5830 { { "i1" }, "r25" }, 5831 { { "i2" }, "r26" }, 5832 { { "i3" }, "r27" }, 5833 { { "i4" }, "r28" }, 5834 { { "i5" }, "r29" }, 5835 { { "i6", "fp" }, "r30" }, 5836 { { "i7" }, "r31" }, 5837 }; 5838 5839 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 5840 return llvm::makeArrayRef(GCCRegAliases); 5841 } 5842 5843 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5844 class SparcV8TargetInfo : public SparcTargetInfo { 5845 public: 5846 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5847 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5848 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 5849 switch (getTriple().getOS()) { 5850 default: 5851 SizeType = UnsignedInt; 5852 IntPtrType = SignedInt; 5853 PtrDiffType = SignedInt; 5854 break; 5855 case llvm::Triple::NetBSD: 5856 case llvm::Triple::OpenBSD: 5857 SizeType = UnsignedLong; 5858 IntPtrType = SignedLong; 5859 PtrDiffType = SignedLong; 5860 break; 5861 } 5862 } 5863 5864 void getTargetDefines(const LangOptions &Opts, 5865 MacroBuilder &Builder) const override { 5866 SparcTargetInfo::getTargetDefines(Opts, Builder); 5867 Builder.defineMacro("__sparcv8"); 5868 } 5869 }; 5870 5871 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5872 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5873 public: 5874 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5875 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5876 BigEndian = false; 5877 } 5878 }; 5879 5880 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5881 class SparcV9TargetInfo : public SparcTargetInfo { 5882 public: 5883 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5884 // FIXME: Support Sparc quad-precision long double? 5885 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 5886 // This is an LP64 platform. 5887 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5888 5889 // OpenBSD uses long long for int64_t and intmax_t. 5890 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5891 IntMaxType = SignedLongLong; 5892 else 5893 IntMaxType = SignedLong; 5894 Int64Type = IntMaxType; 5895 5896 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5897 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5898 LongDoubleWidth = 128; 5899 LongDoubleAlign = 128; 5900 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5901 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5902 } 5903 5904 void getTargetDefines(const LangOptions &Opts, 5905 MacroBuilder &Builder) const override { 5906 SparcTargetInfo::getTargetDefines(Opts, Builder); 5907 Builder.defineMacro("__sparcv9"); 5908 Builder.defineMacro("__arch64__"); 5909 // Solaris doesn't need these variants, but the BSDs do. 5910 if (getTriple().getOS() != llvm::Triple::Solaris) { 5911 Builder.defineMacro("__sparc64__"); 5912 Builder.defineMacro("__sparc_v9__"); 5913 Builder.defineMacro("__sparcv9__"); 5914 } 5915 } 5916 5917 bool setCPU(const std::string &Name) override { 5918 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5919 .Case("v9", true) 5920 .Case("ultrasparc", true) 5921 .Case("ultrasparc3", true) 5922 .Case("niagara", true) 5923 .Case("niagara2", true) 5924 .Case("niagara3", true) 5925 .Case("niagara4", true) 5926 .Default(false); 5927 5928 // No need to store the CPU yet. There aren't any CPU-specific 5929 // macros to define. 5930 return CPUKnown; 5931 } 5932 }; 5933 5934 class SystemZTargetInfo : public TargetInfo { 5935 static const Builtin::Info BuiltinInfo[]; 5936 static const char *const GCCRegNames[]; 5937 std::string CPU; 5938 bool HasTransactionalExecution; 5939 bool HasVector; 5940 5941 public: 5942 SystemZTargetInfo(const llvm::Triple &Triple) 5943 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 5944 HasVector(false) { 5945 IntMaxType = SignedLong; 5946 Int64Type = SignedLong; 5947 TLSSupported = true; 5948 IntWidth = IntAlign = 32; 5949 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5950 PointerWidth = PointerAlign = 64; 5951 LongDoubleWidth = 128; 5952 LongDoubleAlign = 64; 5953 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5954 DefaultAlignForAttributeAligned = 64; 5955 MinGlobalAlign = 16; 5956 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5957 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5958 } 5959 void getTargetDefines(const LangOptions &Opts, 5960 MacroBuilder &Builder) const override { 5961 Builder.defineMacro("__s390__"); 5962 Builder.defineMacro("__s390x__"); 5963 Builder.defineMacro("__zarch__"); 5964 Builder.defineMacro("__LONG_DOUBLE_128__"); 5965 if (HasTransactionalExecution) 5966 Builder.defineMacro("__HTM__"); 5967 if (Opts.ZVector) 5968 Builder.defineMacro("__VEC__", "10301"); 5969 } 5970 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5971 return llvm::makeArrayRef(BuiltinInfo, 5972 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 5973 } 5974 5975 ArrayRef<const char *> getGCCRegNames() const override; 5976 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 5977 // No aliases. 5978 return None; 5979 } 5980 bool validateAsmConstraint(const char *&Name, 5981 TargetInfo::ConstraintInfo &info) const override; 5982 const char *getClobbers() const override { 5983 // FIXME: Is this really right? 5984 return ""; 5985 } 5986 BuiltinVaListKind getBuiltinVaListKind() const override { 5987 return TargetInfo::SystemZBuiltinVaList; 5988 } 5989 bool setCPU(const std::string &Name) override { 5990 CPU = Name; 5991 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5992 .Case("z10", true) 5993 .Case("z196", true) 5994 .Case("zEC12", true) 5995 .Case("z13", true) 5996 .Default(false); 5997 5998 return CPUKnown; 5999 } 6000 bool 6001 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6002 StringRef CPU, 6003 const std::vector<std::string> &FeaturesVec) const override { 6004 if (CPU == "zEC12") 6005 Features["transactional-execution"] = true; 6006 if (CPU == "z13") { 6007 Features["transactional-execution"] = true; 6008 Features["vector"] = true; 6009 } 6010 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6011 } 6012 6013 bool handleTargetFeatures(std::vector<std::string> &Features, 6014 DiagnosticsEngine &Diags) override { 6015 HasTransactionalExecution = false; 6016 for (const auto &Feature : Features) { 6017 if (Feature == "+transactional-execution") 6018 HasTransactionalExecution = true; 6019 else if (Feature == "+vector") 6020 HasVector = true; 6021 } 6022 // If we use the vector ABI, vector types are 64-bit aligned. 6023 if (HasVector) { 6024 MaxVectorAlign = 64; 6025 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6026 "-v128:64-a:8:16-n32:64"; 6027 } 6028 return true; 6029 } 6030 6031 bool hasFeature(StringRef Feature) const override { 6032 return llvm::StringSwitch<bool>(Feature) 6033 .Case("systemz", true) 6034 .Case("htm", HasTransactionalExecution) 6035 .Case("vx", HasVector) 6036 .Default(false); 6037 } 6038 6039 StringRef getABI() const override { 6040 if (HasVector) 6041 return "vector"; 6042 return ""; 6043 } 6044 6045 bool useFloat128ManglingForLongDouble() const override { 6046 return true; 6047 } 6048 }; 6049 6050 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6051 #define BUILTIN(ID, TYPE, ATTRS) \ 6052 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6053 #include "clang/Basic/BuiltinsSystemZ.def" 6054 }; 6055 6056 const char *const SystemZTargetInfo::GCCRegNames[] = { 6057 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6058 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6059 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6060 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6061 }; 6062 6063 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6064 return llvm::makeArrayRef(GCCRegNames); 6065 } 6066 6067 bool SystemZTargetInfo:: 6068 validateAsmConstraint(const char *&Name, 6069 TargetInfo::ConstraintInfo &Info) const { 6070 switch (*Name) { 6071 default: 6072 return false; 6073 6074 case 'a': // Address register 6075 case 'd': // Data register (equivalent to 'r') 6076 case 'f': // Floating-point register 6077 Info.setAllowsRegister(); 6078 return true; 6079 6080 case 'I': // Unsigned 8-bit constant 6081 case 'J': // Unsigned 12-bit constant 6082 case 'K': // Signed 16-bit constant 6083 case 'L': // Signed 20-bit displacement (on all targets we support) 6084 case 'M': // 0x7fffffff 6085 return true; 6086 6087 case 'Q': // Memory with base and unsigned 12-bit displacement 6088 case 'R': // Likewise, plus an index 6089 case 'S': // Memory with base and signed 20-bit displacement 6090 case 'T': // Likewise, plus an index 6091 Info.setAllowsMemory(); 6092 return true; 6093 } 6094 } 6095 6096 class MSP430TargetInfo : public TargetInfo { 6097 static const char *const GCCRegNames[]; 6098 6099 public: 6100 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6101 BigEndian = false; 6102 TLSSupported = false; 6103 IntWidth = 16; 6104 IntAlign = 16; 6105 LongWidth = 32; 6106 LongLongWidth = 64; 6107 LongAlign = LongLongAlign = 16; 6108 PointerWidth = 16; 6109 PointerAlign = 16; 6110 SuitableAlign = 16; 6111 SizeType = UnsignedInt; 6112 IntMaxType = SignedLongLong; 6113 IntPtrType = SignedInt; 6114 PtrDiffType = SignedInt; 6115 SigAtomicType = SignedLong; 6116 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6117 } 6118 void getTargetDefines(const LangOptions &Opts, 6119 MacroBuilder &Builder) const override { 6120 Builder.defineMacro("MSP430"); 6121 Builder.defineMacro("__MSP430__"); 6122 // FIXME: defines for different 'flavours' of MCU 6123 } 6124 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6125 // FIXME: Implement. 6126 return None; 6127 } 6128 bool hasFeature(StringRef Feature) const override { 6129 return Feature == "msp430"; 6130 } 6131 ArrayRef<const char *> getGCCRegNames() const override; 6132 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6133 // No aliases. 6134 return None; 6135 } 6136 bool validateAsmConstraint(const char *&Name, 6137 TargetInfo::ConstraintInfo &info) const override { 6138 // FIXME: implement 6139 switch (*Name) { 6140 case 'K': // the constant 1 6141 case 'L': // constant -1^20 .. 1^19 6142 case 'M': // constant 1-4: 6143 return true; 6144 } 6145 // No target constraints for now. 6146 return false; 6147 } 6148 const char *getClobbers() const override { 6149 // FIXME: Is this really right? 6150 return ""; 6151 } 6152 BuiltinVaListKind getBuiltinVaListKind() const override { 6153 // FIXME: implement 6154 return TargetInfo::CharPtrBuiltinVaList; 6155 } 6156 }; 6157 6158 const char *const MSP430TargetInfo::GCCRegNames[] = { 6159 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6160 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6161 6162 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6163 return llvm::makeArrayRef(GCCRegNames); 6164 } 6165 6166 // LLVM and Clang cannot be used directly to output native binaries for 6167 // target, but is used to compile C code to llvm bitcode with correct 6168 // type and alignment information. 6169 // 6170 // TCE uses the llvm bitcode as input and uses it for generating customized 6171 // target processor and program binary. TCE co-design environment is 6172 // publicly available in http://tce.cs.tut.fi 6173 6174 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6175 3, // opencl_global 6176 4, // opencl_local 6177 5, // opencl_constant 6178 // FIXME: generic has to be added to the target 6179 0, // opencl_generic 6180 0, // cuda_device 6181 0, // cuda_constant 6182 0 // cuda_shared 6183 }; 6184 6185 class TCETargetInfo : public TargetInfo { 6186 public: 6187 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6188 TLSSupported = false; 6189 IntWidth = 32; 6190 LongWidth = LongLongWidth = 32; 6191 PointerWidth = 32; 6192 IntAlign = 32; 6193 LongAlign = LongLongAlign = 32; 6194 PointerAlign = 32; 6195 SuitableAlign = 32; 6196 SizeType = UnsignedInt; 6197 IntMaxType = SignedLong; 6198 IntPtrType = SignedInt; 6199 PtrDiffType = SignedInt; 6200 FloatWidth = 32; 6201 FloatAlign = 32; 6202 DoubleWidth = 32; 6203 DoubleAlign = 32; 6204 LongDoubleWidth = 32; 6205 LongDoubleAlign = 32; 6206 FloatFormat = &llvm::APFloat::IEEEsingle; 6207 DoubleFormat = &llvm::APFloat::IEEEsingle; 6208 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6209 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6210 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6211 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6212 UseAddrSpaceMapMangling = true; 6213 } 6214 6215 void getTargetDefines(const LangOptions &Opts, 6216 MacroBuilder &Builder) const override { 6217 DefineStd(Builder, "tce", Opts); 6218 Builder.defineMacro("__TCE__"); 6219 Builder.defineMacro("__TCE_V1__"); 6220 } 6221 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6222 6223 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6224 const char *getClobbers() const override { return ""; } 6225 BuiltinVaListKind getBuiltinVaListKind() const override { 6226 return TargetInfo::VoidPtrBuiltinVaList; 6227 } 6228 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6229 bool validateAsmConstraint(const char *&Name, 6230 TargetInfo::ConstraintInfo &info) const override { 6231 return true; 6232 } 6233 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6234 return None; 6235 } 6236 }; 6237 6238 class BPFTargetInfo : public TargetInfo { 6239 public: 6240 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6241 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6242 SizeType = UnsignedLong; 6243 PtrDiffType = SignedLong; 6244 IntPtrType = SignedLong; 6245 IntMaxType = SignedLong; 6246 Int64Type = SignedLong; 6247 RegParmMax = 5; 6248 if (Triple.getArch() == llvm::Triple::bpfeb) { 6249 BigEndian = true; 6250 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6251 } else { 6252 BigEndian = false; 6253 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6254 } 6255 MaxAtomicPromoteWidth = 64; 6256 MaxAtomicInlineWidth = 64; 6257 TLSSupported = false; 6258 } 6259 void getTargetDefines(const LangOptions &Opts, 6260 MacroBuilder &Builder) const override { 6261 DefineStd(Builder, "bpf", Opts); 6262 Builder.defineMacro("__BPF__"); 6263 } 6264 bool hasFeature(StringRef Feature) const override { 6265 return Feature == "bpf"; 6266 } 6267 6268 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6269 const char *getClobbers() const override { 6270 return ""; 6271 } 6272 BuiltinVaListKind getBuiltinVaListKind() const override { 6273 return TargetInfo::VoidPtrBuiltinVaList; 6274 } 6275 ArrayRef<const char *> getGCCRegNames() const override { 6276 return None; 6277 } 6278 bool validateAsmConstraint(const char *&Name, 6279 TargetInfo::ConstraintInfo &info) const override { 6280 return true; 6281 } 6282 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6283 return None; 6284 } 6285 }; 6286 6287 class MipsTargetInfoBase : public TargetInfo { 6288 virtual void setDataLayoutString() = 0; 6289 6290 static const Builtin::Info BuiltinInfo[]; 6291 std::string CPU; 6292 bool IsMips16; 6293 bool IsMicromips; 6294 bool IsNan2008; 6295 bool IsSingleFloat; 6296 enum MipsFloatABI { 6297 HardFloat, SoftFloat 6298 } FloatABI; 6299 enum DspRevEnum { 6300 NoDSP, DSP1, DSP2 6301 } DspRev; 6302 bool HasMSA; 6303 6304 protected: 6305 bool HasFP64; 6306 std::string ABI; 6307 6308 public: 6309 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6310 const std::string &CPUStr) 6311 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6312 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6313 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6314 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6315 } 6316 6317 bool isNaN2008Default() const { 6318 return CPU == "mips32r6" || CPU == "mips64r6"; 6319 } 6320 6321 bool isFP64Default() const { 6322 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6323 } 6324 6325 bool isNan2008() const override { 6326 return IsNan2008; 6327 } 6328 6329 StringRef getABI() const override { return ABI; } 6330 bool setCPU(const std::string &Name) override { 6331 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6332 getTriple().getArch() == llvm::Triple::mipsel; 6333 CPU = Name; 6334 return llvm::StringSwitch<bool>(Name) 6335 .Case("mips1", IsMips32) 6336 .Case("mips2", IsMips32) 6337 .Case("mips3", true) 6338 .Case("mips4", true) 6339 .Case("mips5", true) 6340 .Case("mips32", IsMips32) 6341 .Case("mips32r2", IsMips32) 6342 .Case("mips32r3", IsMips32) 6343 .Case("mips32r5", IsMips32) 6344 .Case("mips32r6", IsMips32) 6345 .Case("mips64", true) 6346 .Case("mips64r2", true) 6347 .Case("mips64r3", true) 6348 .Case("mips64r5", true) 6349 .Case("mips64r6", true) 6350 .Case("octeon", true) 6351 .Case("p5600", true) 6352 .Default(false); 6353 } 6354 const std::string& getCPU() const { return CPU; } 6355 bool 6356 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6357 StringRef CPU, 6358 const std::vector<std::string> &FeaturesVec) const override { 6359 if (CPU == "octeon") 6360 Features["mips64r2"] = Features["cnmips"] = true; 6361 else 6362 Features[CPU] = true; 6363 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6364 } 6365 6366 void getTargetDefines(const LangOptions &Opts, 6367 MacroBuilder &Builder) const override { 6368 Builder.defineMacro("__mips__"); 6369 Builder.defineMacro("_mips"); 6370 if (Opts.GNUMode) 6371 Builder.defineMacro("mips"); 6372 6373 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6374 6375 switch (FloatABI) { 6376 case HardFloat: 6377 Builder.defineMacro("__mips_hard_float", Twine(1)); 6378 break; 6379 case SoftFloat: 6380 Builder.defineMacro("__mips_soft_float", Twine(1)); 6381 break; 6382 } 6383 6384 if (IsSingleFloat) 6385 Builder.defineMacro("__mips_single_float", Twine(1)); 6386 6387 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6388 Builder.defineMacro("_MIPS_FPSET", 6389 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6390 6391 if (IsMips16) 6392 Builder.defineMacro("__mips16", Twine(1)); 6393 6394 if (IsMicromips) 6395 Builder.defineMacro("__mips_micromips", Twine(1)); 6396 6397 if (IsNan2008) 6398 Builder.defineMacro("__mips_nan2008", Twine(1)); 6399 6400 switch (DspRev) { 6401 default: 6402 break; 6403 case DSP1: 6404 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6405 Builder.defineMacro("__mips_dsp", Twine(1)); 6406 break; 6407 case DSP2: 6408 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6409 Builder.defineMacro("__mips_dspr2", Twine(1)); 6410 Builder.defineMacro("__mips_dsp", Twine(1)); 6411 break; 6412 } 6413 6414 if (HasMSA) 6415 Builder.defineMacro("__mips_msa", Twine(1)); 6416 6417 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6418 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6419 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6420 6421 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6422 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6423 } 6424 6425 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6426 return llvm::makeArrayRef(BuiltinInfo, 6427 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6428 } 6429 bool hasFeature(StringRef Feature) const override { 6430 return llvm::StringSwitch<bool>(Feature) 6431 .Case("mips", true) 6432 .Case("fp64", HasFP64) 6433 .Default(false); 6434 } 6435 BuiltinVaListKind getBuiltinVaListKind() const override { 6436 return TargetInfo::VoidPtrBuiltinVaList; 6437 } 6438 ArrayRef<const char *> getGCCRegNames() const override { 6439 static const char *const GCCRegNames[] = { 6440 // CPU register names 6441 // Must match second column of GCCRegAliases 6442 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6443 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6444 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6445 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6446 // Floating point register names 6447 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6448 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6449 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6450 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6451 // Hi/lo and condition register names 6452 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6453 "$fcc5","$fcc6","$fcc7", 6454 // MSA register names 6455 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6456 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6457 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6458 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6459 // MSA control register names 6460 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6461 "$msarequest", "$msamap", "$msaunmap" 6462 }; 6463 return llvm::makeArrayRef(GCCRegNames); 6464 } 6465 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6466 bool validateAsmConstraint(const char *&Name, 6467 TargetInfo::ConstraintInfo &Info) const override { 6468 switch (*Name) { 6469 default: 6470 return false; 6471 case 'r': // CPU registers. 6472 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6473 case 'y': // Equivalent to "r", backward compatibility only. 6474 case 'f': // floating-point registers. 6475 case 'c': // $25 for indirect jumps 6476 case 'l': // lo register 6477 case 'x': // hilo register pair 6478 Info.setAllowsRegister(); 6479 return true; 6480 case 'I': // Signed 16-bit constant 6481 case 'J': // Integer 0 6482 case 'K': // Unsigned 16-bit constant 6483 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6484 case 'M': // Constants not loadable via lui, addiu, or ori 6485 case 'N': // Constant -1 to -65535 6486 case 'O': // A signed 15-bit constant 6487 case 'P': // A constant between 1 go 65535 6488 return true; 6489 case 'R': // An address that can be used in a non-macro load or store 6490 Info.setAllowsMemory(); 6491 return true; 6492 case 'Z': 6493 if (Name[1] == 'C') { // An address usable by ll, and sc. 6494 Info.setAllowsMemory(); 6495 Name++; // Skip over 'Z'. 6496 return true; 6497 } 6498 return false; 6499 } 6500 } 6501 6502 std::string convertConstraint(const char *&Constraint) const override { 6503 std::string R; 6504 switch (*Constraint) { 6505 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6506 if (Constraint[1] == 'C') { 6507 R = std::string("^") + std::string(Constraint, 2); 6508 Constraint++; 6509 return R; 6510 } 6511 break; 6512 } 6513 return TargetInfo::convertConstraint(Constraint); 6514 } 6515 6516 const char *getClobbers() const override { 6517 // In GCC, $1 is not widely used in generated code (it's used only in a few 6518 // specific situations), so there is no real need for users to add it to 6519 // the clobbers list if they want to use it in their inline assembly code. 6520 // 6521 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6522 // code generation, so using it in inline assembly without adding it to the 6523 // clobbers list can cause conflicts between the inline assembly code and 6524 // the surrounding generated code. 6525 // 6526 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6527 // operands, which will conflict with the ".set at" assembler option (which 6528 // we use only for inline assembly, in order to maintain compatibility with 6529 // GCC) and will also conflict with the user's usage of $1. 6530 // 6531 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6532 // register for generated code is to automatically clobber $1 for all inline 6533 // assembly code. 6534 // 6535 // FIXME: We should automatically clobber $1 only for inline assembly code 6536 // which actually uses it. This would allow LLVM to use $1 for inline 6537 // assembly operands if the user's assembly code doesn't use it. 6538 return "~{$1}"; 6539 } 6540 6541 bool handleTargetFeatures(std::vector<std::string> &Features, 6542 DiagnosticsEngine &Diags) override { 6543 IsMips16 = false; 6544 IsMicromips = false; 6545 IsNan2008 = isNaN2008Default(); 6546 IsSingleFloat = false; 6547 FloatABI = HardFloat; 6548 DspRev = NoDSP; 6549 HasFP64 = isFP64Default(); 6550 6551 for (const auto &Feature : Features) { 6552 if (Feature == "+single-float") 6553 IsSingleFloat = true; 6554 else if (Feature == "+soft-float") 6555 FloatABI = SoftFloat; 6556 else if (Feature == "+mips16") 6557 IsMips16 = true; 6558 else if (Feature == "+micromips") 6559 IsMicromips = true; 6560 else if (Feature == "+dsp") 6561 DspRev = std::max(DspRev, DSP1); 6562 else if (Feature == "+dspr2") 6563 DspRev = std::max(DspRev, DSP2); 6564 else if (Feature == "+msa") 6565 HasMSA = true; 6566 else if (Feature == "+fp64") 6567 HasFP64 = true; 6568 else if (Feature == "-fp64") 6569 HasFP64 = false; 6570 else if (Feature == "+nan2008") 6571 IsNan2008 = true; 6572 else if (Feature == "-nan2008") 6573 IsNan2008 = false; 6574 } 6575 6576 setDataLayoutString(); 6577 6578 return true; 6579 } 6580 6581 int getEHDataRegisterNumber(unsigned RegNo) const override { 6582 if (RegNo == 0) return 4; 6583 if (RegNo == 1) return 5; 6584 return -1; 6585 } 6586 6587 bool isCLZForZeroUndef() const override { return false; } 6588 }; 6589 6590 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6591 #define BUILTIN(ID, TYPE, ATTRS) \ 6592 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6593 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6594 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6595 #include "clang/Basic/BuiltinsMips.def" 6596 }; 6597 6598 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6599 public: 6600 Mips32TargetInfoBase(const llvm::Triple &Triple) 6601 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6602 SizeType = UnsignedInt; 6603 PtrDiffType = SignedInt; 6604 Int64Type = SignedLongLong; 6605 IntMaxType = Int64Type; 6606 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6607 } 6608 bool setABI(const std::string &Name) override { 6609 if (Name == "o32" || Name == "eabi") { 6610 ABI = Name; 6611 return true; 6612 } 6613 return false; 6614 } 6615 void getTargetDefines(const LangOptions &Opts, 6616 MacroBuilder &Builder) const override { 6617 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6618 6619 Builder.defineMacro("__mips", "32"); 6620 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6621 6622 const std::string& CPUStr = getCPU(); 6623 if (CPUStr == "mips32") 6624 Builder.defineMacro("__mips_isa_rev", "1"); 6625 else if (CPUStr == "mips32r2") 6626 Builder.defineMacro("__mips_isa_rev", "2"); 6627 else if (CPUStr == "mips32r3") 6628 Builder.defineMacro("__mips_isa_rev", "3"); 6629 else if (CPUStr == "mips32r5") 6630 Builder.defineMacro("__mips_isa_rev", "5"); 6631 else if (CPUStr == "mips32r6") 6632 Builder.defineMacro("__mips_isa_rev", "6"); 6633 6634 if (ABI == "o32") { 6635 Builder.defineMacro("__mips_o32"); 6636 Builder.defineMacro("_ABIO32", "1"); 6637 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6638 } 6639 else if (ABI == "eabi") 6640 Builder.defineMacro("__mips_eabi"); 6641 else 6642 llvm_unreachable("Invalid ABI for Mips32."); 6643 } 6644 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6645 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6646 { { "at" }, "$1" }, 6647 { { "v0" }, "$2" }, 6648 { { "v1" }, "$3" }, 6649 { { "a0" }, "$4" }, 6650 { { "a1" }, "$5" }, 6651 { { "a2" }, "$6" }, 6652 { { "a3" }, "$7" }, 6653 { { "t0" }, "$8" }, 6654 { { "t1" }, "$9" }, 6655 { { "t2" }, "$10" }, 6656 { { "t3" }, "$11" }, 6657 { { "t4" }, "$12" }, 6658 { { "t5" }, "$13" }, 6659 { { "t6" }, "$14" }, 6660 { { "t7" }, "$15" }, 6661 { { "s0" }, "$16" }, 6662 { { "s1" }, "$17" }, 6663 { { "s2" }, "$18" }, 6664 { { "s3" }, "$19" }, 6665 { { "s4" }, "$20" }, 6666 { { "s5" }, "$21" }, 6667 { { "s6" }, "$22" }, 6668 { { "s7" }, "$23" }, 6669 { { "t8" }, "$24" }, 6670 { { "t9" }, "$25" }, 6671 { { "k0" }, "$26" }, 6672 { { "k1" }, "$27" }, 6673 { { "gp" }, "$28" }, 6674 { { "sp","$sp" }, "$29" }, 6675 { { "fp","$fp" }, "$30" }, 6676 { { "ra" }, "$31" } 6677 }; 6678 return llvm::makeArrayRef(GCCRegAliases); 6679 } 6680 }; 6681 6682 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6683 void setDataLayoutString() override { 6684 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6685 } 6686 6687 public: 6688 Mips32EBTargetInfo(const llvm::Triple &Triple) 6689 : Mips32TargetInfoBase(Triple) { 6690 } 6691 void getTargetDefines(const LangOptions &Opts, 6692 MacroBuilder &Builder) const override { 6693 DefineStd(Builder, "MIPSEB", Opts); 6694 Builder.defineMacro("_MIPSEB"); 6695 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6696 } 6697 }; 6698 6699 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6700 void setDataLayoutString() override { 6701 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6702 } 6703 6704 public: 6705 Mips32ELTargetInfo(const llvm::Triple &Triple) 6706 : Mips32TargetInfoBase(Triple) { 6707 BigEndian = false; 6708 } 6709 void getTargetDefines(const LangOptions &Opts, 6710 MacroBuilder &Builder) const override { 6711 DefineStd(Builder, "MIPSEL", Opts); 6712 Builder.defineMacro("_MIPSEL"); 6713 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6714 } 6715 }; 6716 6717 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6718 public: 6719 Mips64TargetInfoBase(const llvm::Triple &Triple) 6720 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6721 LongDoubleWidth = LongDoubleAlign = 128; 6722 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6723 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6724 LongDoubleWidth = LongDoubleAlign = 64; 6725 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6726 } 6727 setN64ABITypes(); 6728 SuitableAlign = 128; 6729 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6730 } 6731 6732 void setN64ABITypes() { 6733 LongWidth = LongAlign = 64; 6734 PointerWidth = PointerAlign = 64; 6735 SizeType = UnsignedLong; 6736 PtrDiffType = SignedLong; 6737 Int64Type = SignedLong; 6738 IntMaxType = Int64Type; 6739 } 6740 6741 void setN32ABITypes() { 6742 LongWidth = LongAlign = 32; 6743 PointerWidth = PointerAlign = 32; 6744 SizeType = UnsignedInt; 6745 PtrDiffType = SignedInt; 6746 Int64Type = SignedLongLong; 6747 IntMaxType = Int64Type; 6748 } 6749 6750 bool setABI(const std::string &Name) override { 6751 if (Name == "n32") { 6752 setN32ABITypes(); 6753 ABI = Name; 6754 return true; 6755 } 6756 if (Name == "n64") { 6757 setN64ABITypes(); 6758 ABI = Name; 6759 return true; 6760 } 6761 return false; 6762 } 6763 6764 void getTargetDefines(const LangOptions &Opts, 6765 MacroBuilder &Builder) const override { 6766 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6767 6768 Builder.defineMacro("__mips", "64"); 6769 Builder.defineMacro("__mips64"); 6770 Builder.defineMacro("__mips64__"); 6771 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6772 6773 const std::string& CPUStr = getCPU(); 6774 if (CPUStr == "mips64") 6775 Builder.defineMacro("__mips_isa_rev", "1"); 6776 else if (CPUStr == "mips64r2") 6777 Builder.defineMacro("__mips_isa_rev", "2"); 6778 else if (CPUStr == "mips64r3") 6779 Builder.defineMacro("__mips_isa_rev", "3"); 6780 else if (CPUStr == "mips64r5") 6781 Builder.defineMacro("__mips_isa_rev", "5"); 6782 else if (CPUStr == "mips64r6") 6783 Builder.defineMacro("__mips_isa_rev", "6"); 6784 6785 if (ABI == "n32") { 6786 Builder.defineMacro("__mips_n32"); 6787 Builder.defineMacro("_ABIN32", "2"); 6788 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6789 } 6790 else if (ABI == "n64") { 6791 Builder.defineMacro("__mips_n64"); 6792 Builder.defineMacro("_ABI64", "3"); 6793 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6794 } 6795 else 6796 llvm_unreachable("Invalid ABI for Mips64."); 6797 } 6798 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6799 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6800 { { "at" }, "$1" }, 6801 { { "v0" }, "$2" }, 6802 { { "v1" }, "$3" }, 6803 { { "a0" }, "$4" }, 6804 { { "a1" }, "$5" }, 6805 { { "a2" }, "$6" }, 6806 { { "a3" }, "$7" }, 6807 { { "a4" }, "$8" }, 6808 { { "a5" }, "$9" }, 6809 { { "a6" }, "$10" }, 6810 { { "a7" }, "$11" }, 6811 { { "t0" }, "$12" }, 6812 { { "t1" }, "$13" }, 6813 { { "t2" }, "$14" }, 6814 { { "t3" }, "$15" }, 6815 { { "s0" }, "$16" }, 6816 { { "s1" }, "$17" }, 6817 { { "s2" }, "$18" }, 6818 { { "s3" }, "$19" }, 6819 { { "s4" }, "$20" }, 6820 { { "s5" }, "$21" }, 6821 { { "s6" }, "$22" }, 6822 { { "s7" }, "$23" }, 6823 { { "t8" }, "$24" }, 6824 { { "t9" }, "$25" }, 6825 { { "k0" }, "$26" }, 6826 { { "k1" }, "$27" }, 6827 { { "gp" }, "$28" }, 6828 { { "sp","$sp" }, "$29" }, 6829 { { "fp","$fp" }, "$30" }, 6830 { { "ra" }, "$31" } 6831 }; 6832 return llvm::makeArrayRef(GCCRegAliases); 6833 } 6834 6835 bool hasInt128Type() const override { return true; } 6836 }; 6837 6838 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6839 void setDataLayoutString() override { 6840 if (ABI == "n32") 6841 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6842 else 6843 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6844 6845 } 6846 6847 public: 6848 Mips64EBTargetInfo(const llvm::Triple &Triple) 6849 : Mips64TargetInfoBase(Triple) {} 6850 void getTargetDefines(const LangOptions &Opts, 6851 MacroBuilder &Builder) const override { 6852 DefineStd(Builder, "MIPSEB", Opts); 6853 Builder.defineMacro("_MIPSEB"); 6854 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6855 } 6856 }; 6857 6858 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6859 void setDataLayoutString() override { 6860 if (ABI == "n32") 6861 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6862 else 6863 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6864 } 6865 public: 6866 Mips64ELTargetInfo(const llvm::Triple &Triple) 6867 : Mips64TargetInfoBase(Triple) { 6868 // Default ABI is n64. 6869 BigEndian = false; 6870 } 6871 void getTargetDefines(const LangOptions &Opts, 6872 MacroBuilder &Builder) const override { 6873 DefineStd(Builder, "MIPSEL", Opts); 6874 Builder.defineMacro("_MIPSEL"); 6875 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6876 } 6877 }; 6878 6879 class PNaClTargetInfo : public TargetInfo { 6880 public: 6881 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6882 BigEndian = false; 6883 this->UserLabelPrefix = ""; 6884 this->LongAlign = 32; 6885 this->LongWidth = 32; 6886 this->PointerAlign = 32; 6887 this->PointerWidth = 32; 6888 this->IntMaxType = TargetInfo::SignedLongLong; 6889 this->Int64Type = TargetInfo::SignedLongLong; 6890 this->DoubleAlign = 64; 6891 this->LongDoubleWidth = 64; 6892 this->LongDoubleAlign = 64; 6893 this->SizeType = TargetInfo::UnsignedInt; 6894 this->PtrDiffType = TargetInfo::SignedInt; 6895 this->IntPtrType = TargetInfo::SignedInt; 6896 this->RegParmMax = 0; // Disallow regparm 6897 } 6898 6899 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6900 Builder.defineMacro("__le32__"); 6901 Builder.defineMacro("__pnacl__"); 6902 } 6903 void getTargetDefines(const LangOptions &Opts, 6904 MacroBuilder &Builder) const override { 6905 getArchDefines(Opts, Builder); 6906 } 6907 bool hasFeature(StringRef Feature) const override { 6908 return Feature == "pnacl"; 6909 } 6910 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6911 BuiltinVaListKind getBuiltinVaListKind() const override { 6912 return TargetInfo::PNaClABIBuiltinVaList; 6913 } 6914 ArrayRef<const char *> getGCCRegNames() const override; 6915 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6916 bool validateAsmConstraint(const char *&Name, 6917 TargetInfo::ConstraintInfo &Info) const override { 6918 return false; 6919 } 6920 6921 const char *getClobbers() const override { 6922 return ""; 6923 } 6924 }; 6925 6926 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 6927 return None; 6928 } 6929 6930 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 6931 return None; 6932 } 6933 6934 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 6935 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 6936 public: 6937 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 6938 Mips32ELTargetInfo(Triple) { 6939 } 6940 6941 BuiltinVaListKind getBuiltinVaListKind() const override { 6942 return TargetInfo::PNaClABIBuiltinVaList; 6943 } 6944 }; 6945 6946 class Le64TargetInfo : public TargetInfo { 6947 static const Builtin::Info BuiltinInfo[]; 6948 6949 public: 6950 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6951 BigEndian = false; 6952 NoAsmVariants = true; 6953 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6954 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6955 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6956 } 6957 6958 void getTargetDefines(const LangOptions &Opts, 6959 MacroBuilder &Builder) const override { 6960 DefineStd(Builder, "unix", Opts); 6961 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6962 Builder.defineMacro("__ELF__"); 6963 } 6964 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6965 return llvm::makeArrayRef(BuiltinInfo, 6966 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6967 } 6968 BuiltinVaListKind getBuiltinVaListKind() const override { 6969 return TargetInfo::PNaClABIBuiltinVaList; 6970 } 6971 const char *getClobbers() const override { return ""; } 6972 ArrayRef<const char *> getGCCRegNames() const override { 6973 return None; 6974 } 6975 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6976 return None; 6977 } 6978 bool validateAsmConstraint(const char *&Name, 6979 TargetInfo::ConstraintInfo &Info) const override { 6980 return false; 6981 } 6982 6983 bool hasProtectedVisibility() const override { return false; } 6984 }; 6985 6986 class WebAssemblyTargetInfo : public TargetInfo { 6987 static const Builtin::Info BuiltinInfo[]; 6988 6989 enum SIMDEnum { 6990 NoSIMD, 6991 SIMD128, 6992 } SIMDLevel; 6993 6994 public: 6995 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 6996 : TargetInfo(T), SIMDLevel(NoSIMD) { 6997 BigEndian = false; 6998 NoAsmVariants = true; 6999 SuitableAlign = 128; 7000 LargeArrayMinWidth = 128; 7001 LargeArrayAlign = 128; 7002 SimdDefaultAlign = 128; 7003 SigAtomicType = SignedLong; 7004 } 7005 7006 protected: 7007 void getTargetDefines(const LangOptions &Opts, 7008 MacroBuilder &Builder) const override { 7009 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7010 if (SIMDLevel >= SIMD128) 7011 Builder.defineMacro("__wasm_simd128__"); 7012 } 7013 7014 private: 7015 bool 7016 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7017 StringRef CPU, 7018 const std::vector<std::string> &FeaturesVec) const override { 7019 if (CPU == "bleeding-edge") 7020 Features["simd128"] = true; 7021 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7022 } 7023 bool hasFeature(StringRef Feature) const final { 7024 return llvm::StringSwitch<bool>(Feature) 7025 .Case("simd128", SIMDLevel >= SIMD128) 7026 .Default(false); 7027 } 7028 bool handleTargetFeatures(std::vector<std::string> &Features, 7029 DiagnosticsEngine &Diags) final { 7030 for (const auto &Feature : Features) { 7031 if (Feature == "+simd128") { 7032 SIMDLevel = std::max(SIMDLevel, SIMD128); 7033 continue; 7034 } 7035 if (Feature == "-simd128") { 7036 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7037 continue; 7038 } 7039 7040 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7041 << "-target-feature"; 7042 return false; 7043 } 7044 return true; 7045 } 7046 bool setCPU(const std::string &Name) final { 7047 return llvm::StringSwitch<bool>(Name) 7048 .Case("mvp", true) 7049 .Case("bleeding-edge", true) 7050 .Case("generic", true) 7051 .Default(false); 7052 } 7053 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7054 return llvm::makeArrayRef(BuiltinInfo, 7055 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7056 } 7057 BuiltinVaListKind getBuiltinVaListKind() const final { 7058 // TODO: Implement va_list properly. 7059 return VoidPtrBuiltinVaList; 7060 } 7061 ArrayRef<const char *> getGCCRegNames() const final { 7062 return None; 7063 } 7064 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7065 return None; 7066 } 7067 bool 7068 validateAsmConstraint(const char *&Name, 7069 TargetInfo::ConstraintInfo &Info) const final { 7070 return false; 7071 } 7072 const char *getClobbers() const final { return ""; } 7073 bool isCLZForZeroUndef() const final { return false; } 7074 bool hasInt128Type() const final { return true; } 7075 IntType getIntTypeByWidth(unsigned BitWidth, 7076 bool IsSigned) const final { 7077 // WebAssembly prefers long long for explicitly 64-bit integers. 7078 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7079 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7080 } 7081 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7082 bool IsSigned) const final { 7083 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7084 return BitWidth == 64 7085 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7086 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7087 } 7088 }; 7089 7090 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7091 #define BUILTIN(ID, TYPE, ATTRS) \ 7092 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7093 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7094 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7095 #include "clang/Basic/BuiltinsWebAssembly.def" 7096 }; 7097 7098 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7099 public: 7100 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7101 : WebAssemblyTargetInfo(T) { 7102 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7103 DataLayoutString = "e-p:32:32-i64:64-n32:64-S128"; 7104 } 7105 7106 protected: 7107 void getTargetDefines(const LangOptions &Opts, 7108 MacroBuilder &Builder) const override { 7109 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7110 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7111 } 7112 }; 7113 7114 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7115 public: 7116 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7117 : WebAssemblyTargetInfo(T) { 7118 LongAlign = LongWidth = 64; 7119 PointerAlign = PointerWidth = 64; 7120 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7121 DataLayoutString = "e-p:64:64-i64:64-n32:64-S128"; 7122 } 7123 7124 protected: 7125 void getTargetDefines(const LangOptions &Opts, 7126 MacroBuilder &Builder) const override { 7127 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7128 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7129 } 7130 }; 7131 7132 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7133 #define BUILTIN(ID, TYPE, ATTRS) \ 7134 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7135 #include "clang/Basic/BuiltinsLe64.def" 7136 }; 7137 7138 static const unsigned SPIRAddrSpaceMap[] = { 7139 1, // opencl_global 7140 3, // opencl_local 7141 2, // opencl_constant 7142 4, // opencl_generic 7143 0, // cuda_device 7144 0, // cuda_constant 7145 0 // cuda_shared 7146 }; 7147 class SPIRTargetInfo : public TargetInfo { 7148 public: 7149 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7150 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7151 "SPIR target must use unknown OS"); 7152 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7153 "SPIR target must use unknown environment type"); 7154 BigEndian = false; 7155 TLSSupported = false; 7156 LongWidth = LongAlign = 64; 7157 AddrSpaceMap = &SPIRAddrSpaceMap; 7158 UseAddrSpaceMapMangling = true; 7159 // Define available target features 7160 // These must be defined in sorted order! 7161 NoAsmVariants = true; 7162 } 7163 void getTargetDefines(const LangOptions &Opts, 7164 MacroBuilder &Builder) const override { 7165 DefineStd(Builder, "SPIR", Opts); 7166 } 7167 bool hasFeature(StringRef Feature) const override { 7168 return Feature == "spir"; 7169 } 7170 7171 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7172 const char *getClobbers() const override { return ""; } 7173 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7174 bool validateAsmConstraint(const char *&Name, 7175 TargetInfo::ConstraintInfo &info) const override { 7176 return true; 7177 } 7178 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7179 return None; 7180 } 7181 BuiltinVaListKind getBuiltinVaListKind() const override { 7182 return TargetInfo::VoidPtrBuiltinVaList; 7183 } 7184 7185 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7186 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7187 : CCCR_Warning; 7188 } 7189 7190 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7191 return CC_SpirFunction; 7192 } 7193 }; 7194 7195 class SPIR32TargetInfo : public SPIRTargetInfo { 7196 public: 7197 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7198 PointerWidth = PointerAlign = 32; 7199 SizeType = TargetInfo::UnsignedInt; 7200 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7201 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7202 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7203 } 7204 void getTargetDefines(const LangOptions &Opts, 7205 MacroBuilder &Builder) const override { 7206 DefineStd(Builder, "SPIR32", Opts); 7207 } 7208 }; 7209 7210 class SPIR64TargetInfo : public SPIRTargetInfo { 7211 public: 7212 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7213 PointerWidth = PointerAlign = 64; 7214 SizeType = TargetInfo::UnsignedLong; 7215 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7216 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7217 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7218 } 7219 void getTargetDefines(const LangOptions &Opts, 7220 MacroBuilder &Builder) const override { 7221 DefineStd(Builder, "SPIR64", Opts); 7222 } 7223 }; 7224 7225 class XCoreTargetInfo : public TargetInfo { 7226 static const Builtin::Info BuiltinInfo[]; 7227 public: 7228 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7229 BigEndian = false; 7230 NoAsmVariants = true; 7231 LongLongAlign = 32; 7232 SuitableAlign = 32; 7233 DoubleAlign = LongDoubleAlign = 32; 7234 SizeType = UnsignedInt; 7235 PtrDiffType = SignedInt; 7236 IntPtrType = SignedInt; 7237 WCharType = UnsignedChar; 7238 WIntType = UnsignedInt; 7239 UseZeroLengthBitfieldAlignment = true; 7240 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7241 "-f64:32-a:0:32-n32"; 7242 } 7243 void getTargetDefines(const LangOptions &Opts, 7244 MacroBuilder &Builder) const override { 7245 Builder.defineMacro("__XS1B__"); 7246 } 7247 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7248 return llvm::makeArrayRef(BuiltinInfo, 7249 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7250 } 7251 BuiltinVaListKind getBuiltinVaListKind() const override { 7252 return TargetInfo::VoidPtrBuiltinVaList; 7253 } 7254 const char *getClobbers() const override { 7255 return ""; 7256 } 7257 ArrayRef<const char *> getGCCRegNames() const override { 7258 static const char * const GCCRegNames[] = { 7259 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7260 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7261 }; 7262 return llvm::makeArrayRef(GCCRegNames); 7263 } 7264 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7265 return None; 7266 } 7267 bool validateAsmConstraint(const char *&Name, 7268 TargetInfo::ConstraintInfo &Info) const override { 7269 return false; 7270 } 7271 int getEHDataRegisterNumber(unsigned RegNo) const override { 7272 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7273 return (RegNo < 2)? RegNo : -1; 7274 } 7275 }; 7276 7277 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7278 #define BUILTIN(ID, TYPE, ATTRS) \ 7279 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7280 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7281 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7282 #include "clang/Basic/BuiltinsXCore.def" 7283 }; 7284 7285 // x86_32 Android target 7286 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7287 public: 7288 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7289 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7290 SuitableAlign = 32; 7291 LongDoubleWidth = 64; 7292 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7293 } 7294 }; 7295 7296 // x86_64 Android target 7297 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7298 public: 7299 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7300 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7301 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7302 } 7303 7304 bool useFloat128ManglingForLongDouble() const override { 7305 return true; 7306 } 7307 }; 7308 } // end anonymous namespace 7309 7310 //===----------------------------------------------------------------------===// 7311 // Driver code 7312 //===----------------------------------------------------------------------===// 7313 7314 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7315 llvm::Triple::OSType os = Triple.getOS(); 7316 7317 switch (Triple.getArch()) { 7318 default: 7319 return nullptr; 7320 7321 case llvm::Triple::xcore: 7322 return new XCoreTargetInfo(Triple); 7323 7324 case llvm::Triple::hexagon: 7325 return new HexagonTargetInfo(Triple); 7326 7327 case llvm::Triple::aarch64: 7328 if (Triple.isOSDarwin()) 7329 return new DarwinAArch64TargetInfo(Triple); 7330 7331 switch (os) { 7332 case llvm::Triple::CloudABI: 7333 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7334 case llvm::Triple::FreeBSD: 7335 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7336 case llvm::Triple::Linux: 7337 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7338 case llvm::Triple::NetBSD: 7339 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7340 default: 7341 return new AArch64leTargetInfo(Triple); 7342 } 7343 7344 case llvm::Triple::aarch64_be: 7345 switch (os) { 7346 case llvm::Triple::FreeBSD: 7347 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7348 case llvm::Triple::Linux: 7349 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7350 case llvm::Triple::NetBSD: 7351 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7352 default: 7353 return new AArch64beTargetInfo(Triple); 7354 } 7355 7356 case llvm::Triple::arm: 7357 case llvm::Triple::thumb: 7358 if (Triple.isOSBinFormatMachO()) 7359 return new DarwinARMTargetInfo(Triple); 7360 7361 switch (os) { 7362 case llvm::Triple::Linux: 7363 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7364 case llvm::Triple::FreeBSD: 7365 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7366 case llvm::Triple::NetBSD: 7367 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7368 case llvm::Triple::OpenBSD: 7369 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7370 case llvm::Triple::Bitrig: 7371 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7372 case llvm::Triple::RTEMS: 7373 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7374 case llvm::Triple::NaCl: 7375 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7376 case llvm::Triple::Win32: 7377 switch (Triple.getEnvironment()) { 7378 case llvm::Triple::Cygnus: 7379 return new CygwinARMTargetInfo(Triple); 7380 case llvm::Triple::GNU: 7381 return new MinGWARMTargetInfo(Triple); 7382 case llvm::Triple::Itanium: 7383 return new ItaniumWindowsARMleTargetInfo(Triple); 7384 case llvm::Triple::MSVC: 7385 default: // Assume MSVC for unknown environments 7386 return new MicrosoftARMleTargetInfo(Triple); 7387 } 7388 default: 7389 return new ARMleTargetInfo(Triple); 7390 } 7391 7392 case llvm::Triple::armeb: 7393 case llvm::Triple::thumbeb: 7394 if (Triple.isOSDarwin()) 7395 return new DarwinARMTargetInfo(Triple); 7396 7397 switch (os) { 7398 case llvm::Triple::Linux: 7399 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7400 case llvm::Triple::FreeBSD: 7401 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7402 case llvm::Triple::NetBSD: 7403 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7404 case llvm::Triple::OpenBSD: 7405 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7406 case llvm::Triple::Bitrig: 7407 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7408 case llvm::Triple::RTEMS: 7409 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7410 case llvm::Triple::NaCl: 7411 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7412 default: 7413 return new ARMbeTargetInfo(Triple); 7414 } 7415 7416 case llvm::Triple::bpfeb: 7417 case llvm::Triple::bpfel: 7418 return new BPFTargetInfo(Triple); 7419 7420 case llvm::Triple::msp430: 7421 return new MSP430TargetInfo(Triple); 7422 7423 case llvm::Triple::mips: 7424 switch (os) { 7425 case llvm::Triple::Linux: 7426 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7427 case llvm::Triple::RTEMS: 7428 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7429 case llvm::Triple::FreeBSD: 7430 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7431 case llvm::Triple::NetBSD: 7432 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7433 default: 7434 return new Mips32EBTargetInfo(Triple); 7435 } 7436 7437 case llvm::Triple::mipsel: 7438 switch (os) { 7439 case llvm::Triple::Linux: 7440 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7441 case llvm::Triple::RTEMS: 7442 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7443 case llvm::Triple::FreeBSD: 7444 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7445 case llvm::Triple::NetBSD: 7446 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7447 case llvm::Triple::NaCl: 7448 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7449 default: 7450 return new Mips32ELTargetInfo(Triple); 7451 } 7452 7453 case llvm::Triple::mips64: 7454 switch (os) { 7455 case llvm::Triple::Linux: 7456 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7457 case llvm::Triple::RTEMS: 7458 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7459 case llvm::Triple::FreeBSD: 7460 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7461 case llvm::Triple::NetBSD: 7462 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7463 case llvm::Triple::OpenBSD: 7464 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7465 default: 7466 return new Mips64EBTargetInfo(Triple); 7467 } 7468 7469 case llvm::Triple::mips64el: 7470 switch (os) { 7471 case llvm::Triple::Linux: 7472 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7473 case llvm::Triple::RTEMS: 7474 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7475 case llvm::Triple::FreeBSD: 7476 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7477 case llvm::Triple::NetBSD: 7478 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7479 case llvm::Triple::OpenBSD: 7480 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7481 default: 7482 return new Mips64ELTargetInfo(Triple); 7483 } 7484 7485 case llvm::Triple::le32: 7486 switch (os) { 7487 case llvm::Triple::NaCl: 7488 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7489 default: 7490 return nullptr; 7491 } 7492 7493 case llvm::Triple::le64: 7494 return new Le64TargetInfo(Triple); 7495 7496 case llvm::Triple::ppc: 7497 if (Triple.isOSDarwin()) 7498 return new DarwinPPC32TargetInfo(Triple); 7499 switch (os) { 7500 case llvm::Triple::Linux: 7501 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7502 case llvm::Triple::FreeBSD: 7503 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7504 case llvm::Triple::NetBSD: 7505 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7506 case llvm::Triple::OpenBSD: 7507 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7508 case llvm::Triple::RTEMS: 7509 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7510 default: 7511 return new PPC32TargetInfo(Triple); 7512 } 7513 7514 case llvm::Triple::ppc64: 7515 if (Triple.isOSDarwin()) 7516 return new DarwinPPC64TargetInfo(Triple); 7517 switch (os) { 7518 case llvm::Triple::Linux: 7519 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7520 case llvm::Triple::Lv2: 7521 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7522 case llvm::Triple::FreeBSD: 7523 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7524 case llvm::Triple::NetBSD: 7525 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7526 default: 7527 return new PPC64TargetInfo(Triple); 7528 } 7529 7530 case llvm::Triple::ppc64le: 7531 switch (os) { 7532 case llvm::Triple::Linux: 7533 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7534 case llvm::Triple::NetBSD: 7535 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7536 default: 7537 return new PPC64TargetInfo(Triple); 7538 } 7539 7540 case llvm::Triple::nvptx: 7541 return new NVPTX32TargetInfo(Triple); 7542 case llvm::Triple::nvptx64: 7543 return new NVPTX64TargetInfo(Triple); 7544 7545 case llvm::Triple::amdgcn: 7546 case llvm::Triple::r600: 7547 return new AMDGPUTargetInfo(Triple); 7548 7549 case llvm::Triple::sparc: 7550 switch (os) { 7551 case llvm::Triple::Linux: 7552 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7553 case llvm::Triple::Solaris: 7554 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7555 case llvm::Triple::NetBSD: 7556 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7557 case llvm::Triple::OpenBSD: 7558 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7559 case llvm::Triple::RTEMS: 7560 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7561 default: 7562 return new SparcV8TargetInfo(Triple); 7563 } 7564 7565 // The 'sparcel' architecture copies all the above cases except for Solaris. 7566 case llvm::Triple::sparcel: 7567 switch (os) { 7568 case llvm::Triple::Linux: 7569 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7570 case llvm::Triple::NetBSD: 7571 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7572 case llvm::Triple::OpenBSD: 7573 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7574 case llvm::Triple::RTEMS: 7575 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7576 default: 7577 return new SparcV8elTargetInfo(Triple); 7578 } 7579 7580 case llvm::Triple::sparcv9: 7581 switch (os) { 7582 case llvm::Triple::Linux: 7583 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7584 case llvm::Triple::Solaris: 7585 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7586 case llvm::Triple::NetBSD: 7587 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7588 case llvm::Triple::OpenBSD: 7589 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7590 case llvm::Triple::FreeBSD: 7591 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7592 default: 7593 return new SparcV9TargetInfo(Triple); 7594 } 7595 7596 case llvm::Triple::systemz: 7597 switch (os) { 7598 case llvm::Triple::Linux: 7599 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7600 default: 7601 return new SystemZTargetInfo(Triple); 7602 } 7603 7604 case llvm::Triple::tce: 7605 return new TCETargetInfo(Triple); 7606 7607 case llvm::Triple::x86: 7608 if (Triple.isOSDarwin()) 7609 return new DarwinI386TargetInfo(Triple); 7610 7611 switch (os) { 7612 case llvm::Triple::CloudABI: 7613 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7614 case llvm::Triple::Linux: { 7615 switch (Triple.getEnvironment()) { 7616 default: 7617 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7618 case llvm::Triple::Android: 7619 return new AndroidX86_32TargetInfo(Triple); 7620 } 7621 } 7622 case llvm::Triple::DragonFly: 7623 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7624 case llvm::Triple::NetBSD: 7625 return new NetBSDI386TargetInfo(Triple); 7626 case llvm::Triple::OpenBSD: 7627 return new OpenBSDI386TargetInfo(Triple); 7628 case llvm::Triple::Bitrig: 7629 return new BitrigI386TargetInfo(Triple); 7630 case llvm::Triple::FreeBSD: 7631 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7632 case llvm::Triple::KFreeBSD: 7633 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7634 case llvm::Triple::Minix: 7635 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7636 case llvm::Triple::Solaris: 7637 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7638 case llvm::Triple::Win32: { 7639 switch (Triple.getEnvironment()) { 7640 case llvm::Triple::Cygnus: 7641 return new CygwinX86_32TargetInfo(Triple); 7642 case llvm::Triple::GNU: 7643 return new MinGWX86_32TargetInfo(Triple); 7644 case llvm::Triple::Itanium: 7645 case llvm::Triple::MSVC: 7646 default: // Assume MSVC for unknown environments 7647 return new MicrosoftX86_32TargetInfo(Triple); 7648 } 7649 } 7650 case llvm::Triple::Haiku: 7651 return new HaikuX86_32TargetInfo(Triple); 7652 case llvm::Triple::RTEMS: 7653 return new RTEMSX86_32TargetInfo(Triple); 7654 case llvm::Triple::NaCl: 7655 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7656 default: 7657 return new X86_32TargetInfo(Triple); 7658 } 7659 7660 case llvm::Triple::x86_64: 7661 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7662 return new DarwinX86_64TargetInfo(Triple); 7663 7664 switch (os) { 7665 case llvm::Triple::CloudABI: 7666 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7667 case llvm::Triple::Linux: { 7668 switch (Triple.getEnvironment()) { 7669 default: 7670 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7671 case llvm::Triple::Android: 7672 return new AndroidX86_64TargetInfo(Triple); 7673 } 7674 } 7675 case llvm::Triple::DragonFly: 7676 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7677 case llvm::Triple::NetBSD: 7678 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7679 case llvm::Triple::OpenBSD: 7680 return new OpenBSDX86_64TargetInfo(Triple); 7681 case llvm::Triple::Bitrig: 7682 return new BitrigX86_64TargetInfo(Triple); 7683 case llvm::Triple::FreeBSD: 7684 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7685 case llvm::Triple::KFreeBSD: 7686 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7687 case llvm::Triple::Solaris: 7688 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7689 case llvm::Triple::Win32: { 7690 switch (Triple.getEnvironment()) { 7691 case llvm::Triple::Cygnus: 7692 return new CygwinX86_64TargetInfo(Triple); 7693 case llvm::Triple::GNU: 7694 return new MinGWX86_64TargetInfo(Triple); 7695 case llvm::Triple::MSVC: 7696 default: // Assume MSVC for unknown environments 7697 return new MicrosoftX86_64TargetInfo(Triple); 7698 } 7699 } 7700 case llvm::Triple::NaCl: 7701 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7702 case llvm::Triple::PS4: 7703 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7704 default: 7705 return new X86_64TargetInfo(Triple); 7706 } 7707 7708 case llvm::Triple::spir: { 7709 if (Triple.getOS() != llvm::Triple::UnknownOS || 7710 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7711 return nullptr; 7712 return new SPIR32TargetInfo(Triple); 7713 } 7714 case llvm::Triple::spir64: { 7715 if (Triple.getOS() != llvm::Triple::UnknownOS || 7716 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7717 return nullptr; 7718 return new SPIR64TargetInfo(Triple); 7719 } 7720 case llvm::Triple::wasm32: 7721 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 7722 return nullptr; 7723 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 7724 case llvm::Triple::wasm64: 7725 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 7726 return nullptr; 7727 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 7728 } 7729 } 7730 7731 /// CreateTargetInfo - Return the target info object for the specified target 7732 /// options. 7733 TargetInfo * 7734 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7735 const std::shared_ptr<TargetOptions> &Opts) { 7736 llvm::Triple Triple(Opts->Triple); 7737 7738 // Construct the target 7739 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7740 if (!Target) { 7741 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7742 return nullptr; 7743 } 7744 Target->TargetOpts = Opts; 7745 7746 // Set the target CPU if specified. 7747 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7748 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7749 return nullptr; 7750 } 7751 7752 // Set the target ABI if specified. 7753 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7754 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7755 return nullptr; 7756 } 7757 7758 // Set the fp math unit. 7759 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7760 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7761 return nullptr; 7762 } 7763 7764 // Compute the default target features, we need the target to handle this 7765 // because features may have dependencies on one another. 7766 llvm::StringMap<bool> Features; 7767 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 7768 Opts->FeaturesAsWritten)) 7769 return nullptr; 7770 7771 // Add the features to the compile options. 7772 Opts->Features.clear(); 7773 for (const auto &F : Features) 7774 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 7775 7776 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7777 return nullptr; 7778 7779 return Target.release(); 7780 } 7781