1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("__STDC_NO_THREADS__"); 121 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 122 // AddressSanitizer doesn't play well with source fortification, which is on 123 // by default on Darwin. 124 if (Opts.Sanitize.has(SanitizerKind::Address)) 125 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 126 127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 128 if (!Opts.ObjC1) { 129 // __weak is always defined, for use in blocks and with objc pointers. 130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 131 Builder.defineMacro("__strong", ""); 132 Builder.defineMacro("__unsafe_unretained", ""); 133 } 134 135 if (Opts.Static) 136 Builder.defineMacro("__STATIC__"); 137 else 138 Builder.defineMacro("__DYNAMIC__"); 139 140 if (Opts.POSIXThreads) 141 Builder.defineMacro("_REENTRANT"); 142 143 // Get the platform type and version number from the triple. 144 unsigned Maj, Min, Rev; 145 if (Triple.isMacOSX()) { 146 Triple.getMacOSXVersion(Maj, Min, Rev); 147 PlatformName = "macos"; 148 } else { 149 Triple.getOSVersion(Maj, Min, Rev); 150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 151 } 152 153 // If -target arch-pc-win32-macho option specified, we're 154 // generating code for Win32 ABI. No need to emit 155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 156 if (PlatformName == "win32") { 157 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 158 return; 159 } 160 161 // Set the appropriate OS version define. 162 if (Triple.isiOS()) { 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[7]; 165 if (Maj < 10) { 166 Str[0] = '0' + Maj; 167 Str[1] = '0' + (Min / 10); 168 Str[2] = '0' + (Min % 10); 169 Str[3] = '0' + (Rev / 10); 170 Str[4] = '0' + (Rev % 10); 171 Str[5] = '\0'; 172 } else { 173 // Handle versions >= 10. 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + (Min / 10); 177 Str[3] = '0' + (Min % 10); 178 Str[4] = '0' + (Rev / 10); 179 Str[5] = '0' + (Rev % 10); 180 Str[6] = '\0'; 181 } 182 if (Triple.isTvOS()) 183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 184 else 185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 186 Str); 187 188 } else if (Triple.isWatchOS()) { 189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[6]; 191 Str[0] = '0' + Maj; 192 Str[1] = '0' + (Min / 10); 193 Str[2] = '0' + (Min % 10); 194 Str[3] = '0' + (Rev / 10); 195 Str[4] = '0' + (Rev % 10); 196 Str[5] = '\0'; 197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 198 } else if (Triple.isMacOSX()) { 199 // Note that the Driver allows versions which aren't representable in the 200 // define (because we only get a single digit for the minor and micro 201 // revision numbers). So, we limit them to the maximum representable 202 // version. 203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 204 char Str[7]; 205 if (Maj < 10 || (Maj == 10 && Min < 10)) { 206 Str[0] = '0' + (Maj / 10); 207 Str[1] = '0' + (Maj % 10); 208 Str[2] = '0' + std::min(Min, 9U); 209 Str[3] = '0' + std::min(Rev, 9U); 210 Str[4] = '\0'; 211 } else { 212 // Handle versions > 10.9. 213 Str[0] = '0' + (Maj / 10); 214 Str[1] = '0' + (Maj % 10); 215 Str[2] = '0' + (Min / 10); 216 Str[3] = '0' + (Min % 10); 217 Str[4] = '0' + (Rev / 10); 218 Str[5] = '0' + (Rev % 10); 219 Str[6] = '\0'; 220 } 221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 222 } 223 224 // Tell users about the kernel if there is one. 225 if (Triple.isOSDarwin()) 226 Builder.defineMacro("__MACH__"); 227 228 // The Watch ABI uses Dwarf EH. 229 if(Triple.isWatchABI()) 230 Builder.defineMacro("__ARM_DWARF_EH__"); 231 232 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 233 } 234 235 template<typename Target> 236 class DarwinTargetInfo : public OSTargetInfo<Target> { 237 protected: 238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 239 MacroBuilder &Builder) const override { 240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 241 this->PlatformMinVersion); 242 } 243 244 public: 245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 246 : OSTargetInfo<Target>(Triple, Opts) { 247 // By default, no TLS, and we whitelist permitted architecture/OS 248 // combinations. 249 this->TLSSupported = false; 250 251 if (Triple.isMacOSX()) 252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 253 else if (Triple.isiOS()) { 254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 255 if (Triple.getArch() == llvm::Triple::x86_64 || 256 Triple.getArch() == llvm::Triple::aarch64) 257 this->TLSSupported = !Triple.isOSVersionLT(8); 258 else if (Triple.getArch() == llvm::Triple::x86 || 259 Triple.getArch() == llvm::Triple::arm || 260 Triple.getArch() == llvm::Triple::thumb) 261 this->TLSSupported = !Triple.isOSVersionLT(9); 262 } else if (Triple.isWatchOS()) 263 this->TLSSupported = !Triple.isOSVersionLT(2); 264 265 this->MCountName = "\01mcount"; 266 } 267 268 std::string isValidSectionSpecifier(StringRef SR) const override { 269 // Let MCSectionMachO validate this. 270 StringRef Segment, Section; 271 unsigned TAA, StubSize; 272 bool HasTAA; 273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 274 TAA, HasTAA, StubSize); 275 } 276 277 const char *getStaticInitSectionSpecifier() const override { 278 // FIXME: We should return 0 when building kexts. 279 return "__TEXT,__StaticInit,regular,pure_instructions"; 280 } 281 282 /// Darwin does not support protected visibility. Darwin's "default" 283 /// is very similar to ELF's "protected"; Darwin requires a "weak" 284 /// attribute on declarations that can be dynamically replaced. 285 bool hasProtectedVisibility() const override { 286 return false; 287 } 288 289 unsigned getExnObjectAlignment() const override { 290 // The alignment of an exception object is 8-bytes for darwin since 291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 292 // and therefore doesn't guarantee 16-byte alignment. 293 return 64; 294 } 295 }; 296 297 298 // DragonFlyBSD Target 299 template<typename Target> 300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 301 protected: 302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 303 MacroBuilder &Builder) const override { 304 // DragonFly defines; list based off of gcc output 305 Builder.defineMacro("__DragonFly__"); 306 Builder.defineMacro("__DragonFly_cc_version", "100001"); 307 Builder.defineMacro("__ELF__"); 308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 309 Builder.defineMacro("__tune_i386__"); 310 DefineStd(Builder, "unix", Opts); 311 } 312 public: 313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 314 : OSTargetInfo<Target>(Triple, Opts) { 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 } 322 } 323 }; 324 325 #ifndef FREEBSD_CC_VERSION 326 #define FREEBSD_CC_VERSION 0U 327 #endif 328 329 // FreeBSD Target 330 template<typename Target> 331 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // FreeBSD defines; list based off of gcc output 336 337 unsigned Release = Triple.getOSMajorVersion(); 338 if (Release == 0U) 339 Release = 8U; 340 unsigned CCVersion = FREEBSD_CC_VERSION; 341 if (CCVersion == 0U) 342 CCVersion = Release * 100000U + 1U; 343 344 Builder.defineMacro("__FreeBSD__", Twine(Release)); 345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 347 DefineStd(Builder, "unix", Opts); 348 Builder.defineMacro("__ELF__"); 349 350 // On FreeBSD, wchar_t contains the number of the code point as 351 // used by the character set of the locale. These character sets are 352 // not necessarily a superset of ASCII. 353 // 354 // FIXME: This is wrong; the macro refers to the numerical values 355 // of wchar_t *literals*, which are not locale-dependent. However, 356 // FreeBSD systems apparently depend on us getting this wrong, and 357 // setting this to 1 is conforming even if all the basic source 358 // character literals have the same encoding as char and wchar_t. 359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 360 } 361 public: 362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : OSTargetInfo<Target>(Triple, Opts) { 364 switch (Triple.getArch()) { 365 default: 366 case llvm::Triple::x86: 367 case llvm::Triple::x86_64: 368 this->MCountName = ".mcount"; 369 break; 370 case llvm::Triple::mips: 371 case llvm::Triple::mipsel: 372 case llvm::Triple::ppc: 373 case llvm::Triple::ppc64: 374 case llvm::Triple::ppc64le: 375 this->MCountName = "_mcount"; 376 break; 377 case llvm::Triple::arm: 378 this->MCountName = "__mcount"; 379 break; 380 } 381 } 382 }; 383 384 // GNU/kFreeBSD Target 385 template<typename Target> 386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // GNU/kFreeBSD defines; list based off of gcc output 391 392 DefineStd(Builder, "unix", Opts); 393 Builder.defineMacro("__FreeBSD_kernel__"); 394 Builder.defineMacro("__GLIBC__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 403 : OSTargetInfo<Target>(Triple, Opts) {} 404 }; 405 406 // Haiku Target 407 template<typename Target> 408 class HaikuTargetInfo : public OSTargetInfo<Target> { 409 protected: 410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 411 MacroBuilder &Builder) const override { 412 // Haiku defines; list based off of gcc output 413 Builder.defineMacro("__HAIKU__"); 414 Builder.defineMacro("__ELF__"); 415 DefineStd(Builder, "unix", Opts); 416 } 417 public: 418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 419 : OSTargetInfo<Target>(Triple, Opts) { 420 this->SizeType = TargetInfo::UnsignedLong; 421 this->IntPtrType = TargetInfo::SignedLong; 422 this->PtrDiffType = TargetInfo::SignedLong; 423 this->ProcessIDType = TargetInfo::SignedLong; 424 this->TLSSupported = false; 425 426 } 427 }; 428 429 // Minix Target 430 template<typename Target> 431 class MinixTargetInfo : public OSTargetInfo<Target> { 432 protected: 433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 434 MacroBuilder &Builder) const override { 435 // Minix defines 436 437 Builder.defineMacro("__minix", "3"); 438 Builder.defineMacro("_EM_WSIZE", "4"); 439 Builder.defineMacro("_EM_PSIZE", "4"); 440 Builder.defineMacro("_EM_SSIZE", "2"); 441 Builder.defineMacro("_EM_LSIZE", "4"); 442 Builder.defineMacro("_EM_FSIZE", "4"); 443 Builder.defineMacro("_EM_DSIZE", "8"); 444 Builder.defineMacro("__ELF__"); 445 DefineStd(Builder, "unix", Opts); 446 } 447 public: 448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 449 : OSTargetInfo<Target>(Triple, Opts) {} 450 }; 451 452 // Linux target 453 template<typename Target> 454 class LinuxTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // Linux defines; list based off of gcc output 459 DefineStd(Builder, "unix", Opts); 460 DefineStd(Builder, "linux", Opts); 461 Builder.defineMacro("__gnu_linux__"); 462 Builder.defineMacro("__ELF__"); 463 if (Triple.isAndroid()) { 464 Builder.defineMacro("__ANDROID__", "1"); 465 unsigned Maj, Min, Rev; 466 Triple.getEnvironmentVersion(Maj, Min, Rev); 467 this->PlatformName = "android"; 468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 469 if (Maj) 470 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 471 } 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 if (Opts.CPlusPlus) 475 Builder.defineMacro("_GNU_SOURCE"); 476 if (this->HasFloat128) 477 Builder.defineMacro("__FLOAT128__"); 478 } 479 public: 480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 481 : OSTargetInfo<Target>(Triple, Opts) { 482 this->WIntType = TargetInfo::UnsignedInt; 483 484 switch (Triple.getArch()) { 485 default: 486 break; 487 case llvm::Triple::ppc: 488 case llvm::Triple::ppc64: 489 case llvm::Triple::ppc64le: 490 this->MCountName = "_mcount"; 491 break; 492 case llvm::Triple::x86: 493 case llvm::Triple::x86_64: 494 case llvm::Triple::systemz: 495 this->HasFloat128 = true; 496 break; 497 } 498 } 499 500 const char *getStaticInitSectionSpecifier() const override { 501 return ".text.startup"; 502 } 503 }; 504 505 // NetBSD Target 506 template<typename Target> 507 class NetBSDTargetInfo : public OSTargetInfo<Target> { 508 protected: 509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 510 MacroBuilder &Builder) const override { 511 // NetBSD defines; list based off of gcc output 512 Builder.defineMacro("__NetBSD__"); 513 Builder.defineMacro("__unix__"); 514 Builder.defineMacro("__ELF__"); 515 if (Opts.POSIXThreads) 516 Builder.defineMacro("_REENTRANT"); 517 518 switch (Triple.getArch()) { 519 default: 520 break; 521 case llvm::Triple::arm: 522 case llvm::Triple::armeb: 523 case llvm::Triple::thumb: 524 case llvm::Triple::thumbeb: 525 Builder.defineMacro("__ARM_DWARF_EH__"); 526 break; 527 } 528 } 529 public: 530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 531 : OSTargetInfo<Target>(Triple, Opts) { 532 this->MCountName = "_mcount"; 533 } 534 }; 535 536 // OpenBSD Target 537 template<typename Target> 538 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 539 protected: 540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 541 MacroBuilder &Builder) const override { 542 // OpenBSD defines; list based off of gcc output 543 544 Builder.defineMacro("__OpenBSD__"); 545 DefineStd(Builder, "unix", Opts); 546 Builder.defineMacro("__ELF__"); 547 if (Opts.POSIXThreads) 548 Builder.defineMacro("_REENTRANT"); 549 if (this->HasFloat128) 550 Builder.defineMacro("__FLOAT128__"); 551 } 552 public: 553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 554 : OSTargetInfo<Target>(Triple, Opts) { 555 this->TLSSupported = false; 556 557 switch (Triple.getArch()) { 558 case llvm::Triple::x86: 559 case llvm::Triple::x86_64: 560 this->HasFloat128 = true; 561 // FALLTHROUGH 562 default: 563 this->MCountName = "__mcount"; 564 break; 565 case llvm::Triple::mips64: 566 case llvm::Triple::mips64el: 567 case llvm::Triple::ppc: 568 case llvm::Triple::sparcv9: 569 this->MCountName = "_mcount"; 570 break; 571 } 572 } 573 }; 574 575 // Bitrig Target 576 template<typename Target> 577 class BitrigTargetInfo : public OSTargetInfo<Target> { 578 protected: 579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const override { 581 // Bitrig defines; list based off of gcc output 582 583 Builder.defineMacro("__Bitrig__"); 584 DefineStd(Builder, "unix", Opts); 585 Builder.defineMacro("__ELF__"); 586 if (Opts.POSIXThreads) 587 Builder.defineMacro("_REENTRANT"); 588 589 switch (Triple.getArch()) { 590 default: 591 break; 592 case llvm::Triple::arm: 593 case llvm::Triple::armeb: 594 case llvm::Triple::thumb: 595 case llvm::Triple::thumbeb: 596 Builder.defineMacro("__ARM_DWARF_EH__"); 597 break; 598 } 599 } 600 public: 601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->MCountName = "__mcount"; 604 } 605 }; 606 607 // PSP Target 608 template<typename Target> 609 class PSPTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 // PSP defines; list based on the output of the pspdev gcc toolchain. 614 Builder.defineMacro("PSP"); 615 Builder.defineMacro("_PSP"); 616 Builder.defineMacro("__psp__"); 617 Builder.defineMacro("__ELF__"); 618 } 619 public: 620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 621 }; 622 623 // PS3 PPU Target 624 template<typename Target> 625 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 626 protected: 627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 628 MacroBuilder &Builder) const override { 629 // PS3 PPU defines. 630 Builder.defineMacro("__PPC__"); 631 Builder.defineMacro("__PPU__"); 632 Builder.defineMacro("__CELLOS_LV2__"); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__LP32__"); 635 Builder.defineMacro("_ARCH_PPC64"); 636 Builder.defineMacro("__powerpc64__"); 637 } 638 public: 639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 640 : OSTargetInfo<Target>(Triple, Opts) { 641 this->LongWidth = this->LongAlign = 32; 642 this->PointerWidth = this->PointerAlign = 32; 643 this->IntMaxType = TargetInfo::SignedLongLong; 644 this->Int64Type = TargetInfo::SignedLongLong; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 647 } 648 }; 649 650 template <typename Target> 651 class PS4OSTargetInfo : public OSTargetInfo<Target> { 652 protected: 653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 654 MacroBuilder &Builder) const override { 655 Builder.defineMacro("__FreeBSD__", "9"); 656 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 658 DefineStd(Builder, "unix", Opts); 659 Builder.defineMacro("__ELF__"); 660 Builder.defineMacro("__ORBIS__"); 661 } 662 public: 663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 664 : OSTargetInfo<Target>(Triple, Opts) { 665 this->WCharType = this->UnsignedShort; 666 667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 668 this->MaxTLSAlign = 256; 669 670 // On PS4, do not honor explicit bit field alignment, 671 // as in "__attribute__((aligned(2))) int b : 1;". 672 this->UseExplicitBitFieldAlignment = false; 673 674 switch (Triple.getArch()) { 675 default: 676 case llvm::Triple::x86_64: 677 this->MCountName = ".mcount"; 678 break; 679 } 680 } 681 }; 682 683 // Solaris target 684 template<typename Target> 685 class SolarisTargetInfo : public OSTargetInfo<Target> { 686 protected: 687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 688 MacroBuilder &Builder) const override { 689 DefineStd(Builder, "sun", Opts); 690 DefineStd(Builder, "unix", Opts); 691 Builder.defineMacro("__ELF__"); 692 Builder.defineMacro("__svr4__"); 693 Builder.defineMacro("__SVR4"); 694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 695 // newer, but to 500 for everything else. feature_test.h has a check to 696 // ensure that you are not using C99 with an old version of X/Open or C89 697 // with a new version. 698 if (Opts.C99) 699 Builder.defineMacro("_XOPEN_SOURCE", "600"); 700 else 701 Builder.defineMacro("_XOPEN_SOURCE", "500"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("__C99FEATURES__"); 704 Builder.defineMacro("_LARGEFILE_SOURCE"); 705 Builder.defineMacro("_LARGEFILE64_SOURCE"); 706 Builder.defineMacro("__EXTENSIONS__"); 707 Builder.defineMacro("_REENTRANT"); 708 } 709 public: 710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 711 : OSTargetInfo<Target>(Triple, Opts) { 712 this->WCharType = this->SignedInt; 713 // FIXME: WIntType should be SignedLong 714 } 715 }; 716 717 // Windows target 718 template<typename Target> 719 class WindowsTargetInfo : public OSTargetInfo<Target> { 720 protected: 721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 722 MacroBuilder &Builder) const override { 723 Builder.defineMacro("_WIN32"); 724 } 725 void getVisualStudioDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const { 727 if (Opts.CPlusPlus) { 728 if (Opts.RTTIData) 729 Builder.defineMacro("_CPPRTTI"); 730 731 if (Opts.CXXExceptions) 732 Builder.defineMacro("_CPPUNWIND"); 733 } 734 735 if (Opts.Bool) 736 Builder.defineMacro("__BOOL_DEFINED"); 737 738 if (!Opts.CharIsSigned) 739 Builder.defineMacro("_CHAR_UNSIGNED"); 740 741 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 742 // but it works for now. 743 if (Opts.POSIXThreads) 744 Builder.defineMacro("_MT"); 745 746 if (Opts.MSCompatibilityVersion) { 747 Builder.defineMacro("_MSC_VER", 748 Twine(Opts.MSCompatibilityVersion / 100000)); 749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 750 // FIXME We cannot encode the revision information into 32-bits 751 Builder.defineMacro("_MSC_BUILD", Twine(1)); 752 753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 755 756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 757 if (Opts.CPlusPlus1z) 758 Builder.defineMacro("_MSVC_LANG", "201403L"); 759 else if (Opts.CPlusPlus14) 760 Builder.defineMacro("_MSVC_LANG", "201402L"); 761 } 762 } 763 764 if (Opts.MicrosoftExt) { 765 Builder.defineMacro("_MSC_EXTENSIONS"); 766 767 if (Opts.CPlusPlus11) { 768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 771 } 772 } 773 774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 775 } 776 777 public: 778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 779 : OSTargetInfo<Target>(Triple, Opts) {} 780 }; 781 782 template <typename Target> 783 class NaClTargetInfo : public OSTargetInfo<Target> { 784 protected: 785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 786 MacroBuilder &Builder) const override { 787 if (Opts.POSIXThreads) 788 Builder.defineMacro("_REENTRANT"); 789 if (Opts.CPlusPlus) 790 Builder.defineMacro("_GNU_SOURCE"); 791 792 DefineStd(Builder, "unix", Opts); 793 Builder.defineMacro("__ELF__"); 794 Builder.defineMacro("__native_client__"); 795 } 796 797 public: 798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 799 : OSTargetInfo<Target>(Triple, Opts) { 800 this->LongAlign = 32; 801 this->LongWidth = 32; 802 this->PointerAlign = 32; 803 this->PointerWidth = 32; 804 this->IntMaxType = TargetInfo::SignedLongLong; 805 this->Int64Type = TargetInfo::SignedLongLong; 806 this->DoubleAlign = 64; 807 this->LongDoubleWidth = 64; 808 this->LongDoubleAlign = 64; 809 this->LongLongWidth = 64; 810 this->LongLongAlign = 64; 811 this->SizeType = TargetInfo::UnsignedInt; 812 this->PtrDiffType = TargetInfo::SignedInt; 813 this->IntPtrType = TargetInfo::SignedInt; 814 // RegParmMax is inherited from the underlying architecture. 815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 816 if (Triple.getArch() == llvm::Triple::arm) { 817 // Handled in ARM's setABI(). 818 } else if (Triple.getArch() == llvm::Triple::x86) { 819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 820 } else if (Triple.getArch() == llvm::Triple::x86_64) { 821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 822 } else if (Triple.getArch() == llvm::Triple::mipsel) { 823 // Handled on mips' setDataLayout. 824 } else { 825 assert(Triple.getArch() == llvm::Triple::le32); 826 this->resetDataLayout("e-p:32:32-i64:64"); 827 } 828 } 829 }; 830 831 // Fuchsia Target 832 template<typename Target> 833 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 834 protected: 835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 836 MacroBuilder &Builder) const override { 837 Builder.defineMacro("__Fuchsia__"); 838 Builder.defineMacro("__ELF__"); 839 if (Opts.POSIXThreads) 840 Builder.defineMacro("_REENTRANT"); 841 // Required by the libc++ locale support. 842 if (Opts.CPlusPlus) 843 Builder.defineMacro("_GNU_SOURCE"); 844 } 845 public: 846 FuchsiaTargetInfo(const llvm::Triple &Triple, 847 const TargetOptions &Opts) 848 : OSTargetInfo<Target>(Triple, Opts) { 849 this->MCountName = "__mcount"; 850 } 851 }; 852 853 // WebAssembly target 854 template <typename Target> 855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 857 MacroBuilder &Builder) const final { 858 // A common platform macro. 859 if (Opts.POSIXThreads) 860 Builder.defineMacro("_REENTRANT"); 861 // Follow g++ convention and predefine _GNU_SOURCE for C++. 862 if (Opts.CPlusPlus) 863 Builder.defineMacro("_GNU_SOURCE"); 864 } 865 866 // As an optimization, group static init code together in a section. 867 const char *getStaticInitSectionSpecifier() const final { 868 return ".text.__startup"; 869 } 870 871 public: 872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 873 const TargetOptions &Opts) 874 : OSTargetInfo<Target>(Triple, Opts) { 875 this->MCountName = "__mcount"; 876 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 877 } 878 }; 879 880 //===----------------------------------------------------------------------===// 881 // Specific target implementations. 882 //===----------------------------------------------------------------------===// 883 884 // PPC abstract base class 885 class PPCTargetInfo : public TargetInfo { 886 static const Builtin::Info BuiltinInfo[]; 887 static const char * const GCCRegNames[]; 888 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 889 std::string CPU; 890 891 // Target cpu features. 892 bool HasAltivec; 893 bool HasVSX; 894 bool HasP8Vector; 895 bool HasP8Crypto; 896 bool HasDirectMove; 897 bool HasQPX; 898 bool HasHTM; 899 bool HasBPERMD; 900 bool HasExtDiv; 901 bool HasP9Vector; 902 903 protected: 904 std::string ABI; 905 906 public: 907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 911 SuitableAlign = 128; 912 SimdDefaultAlign = 128; 913 LongDoubleWidth = LongDoubleAlign = 128; 914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 915 } 916 917 /// \brief Flags for architecture specific defines. 918 typedef enum { 919 ArchDefineNone = 0, 920 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 921 ArchDefinePpcgr = 1 << 1, 922 ArchDefinePpcsq = 1 << 2, 923 ArchDefine440 = 1 << 3, 924 ArchDefine603 = 1 << 4, 925 ArchDefine604 = 1 << 5, 926 ArchDefinePwr4 = 1 << 6, 927 ArchDefinePwr5 = 1 << 7, 928 ArchDefinePwr5x = 1 << 8, 929 ArchDefinePwr6 = 1 << 9, 930 ArchDefinePwr6x = 1 << 10, 931 ArchDefinePwr7 = 1 << 11, 932 ArchDefinePwr8 = 1 << 12, 933 ArchDefinePwr9 = 1 << 13, 934 ArchDefineA2 = 1 << 14, 935 ArchDefineA2q = 1 << 15 936 } ArchDefineTypes; 937 938 // Set the language option for altivec based on our value. 939 void adjust(LangOptions &Opts) override { 940 if (HasAltivec) 941 Opts.AltiVec = 1; 942 TargetInfo::adjust(Opts); 943 } 944 945 // Note: GCC recognizes the following additional cpus: 946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 948 // titan, rs64. 949 bool setCPU(const std::string &Name) override { 950 bool CPUKnown = llvm::StringSwitch<bool>(Name) 951 .Case("generic", true) 952 .Case("440", true) 953 .Case("450", true) 954 .Case("601", true) 955 .Case("602", true) 956 .Case("603", true) 957 .Case("603e", true) 958 .Case("603ev", true) 959 .Case("604", true) 960 .Case("604e", true) 961 .Case("620", true) 962 .Case("630", true) 963 .Case("g3", true) 964 .Case("7400", true) 965 .Case("g4", true) 966 .Case("7450", true) 967 .Case("g4+", true) 968 .Case("750", true) 969 .Case("970", true) 970 .Case("g5", true) 971 .Case("a2", true) 972 .Case("a2q", true) 973 .Case("e500mc", true) 974 .Case("e5500", true) 975 .Case("power3", true) 976 .Case("pwr3", true) 977 .Case("power4", true) 978 .Case("pwr4", true) 979 .Case("power5", true) 980 .Case("pwr5", true) 981 .Case("power5x", true) 982 .Case("pwr5x", true) 983 .Case("power6", true) 984 .Case("pwr6", true) 985 .Case("power6x", true) 986 .Case("pwr6x", true) 987 .Case("power7", true) 988 .Case("pwr7", true) 989 .Case("power8", true) 990 .Case("pwr8", true) 991 .Case("power9", true) 992 .Case("pwr9", true) 993 .Case("powerpc", true) 994 .Case("ppc", true) 995 .Case("powerpc64", true) 996 .Case("ppc64", true) 997 .Case("powerpc64le", true) 998 .Case("ppc64le", true) 999 .Default(false); 1000 1001 if (CPUKnown) 1002 CPU = Name; 1003 1004 return CPUKnown; 1005 } 1006 1007 1008 StringRef getABI() const override { return ABI; } 1009 1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1011 return llvm::makeArrayRef(BuiltinInfo, 1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1013 } 1014 1015 bool isCLZForZeroUndef() const override { return false; } 1016 1017 void getTargetDefines(const LangOptions &Opts, 1018 MacroBuilder &Builder) const override; 1019 1020 bool 1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1022 StringRef CPU, 1023 const std::vector<std::string> &FeaturesVec) const override; 1024 1025 bool handleTargetFeatures(std::vector<std::string> &Features, 1026 DiagnosticsEngine &Diags) override; 1027 bool hasFeature(StringRef Feature) const override; 1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1029 bool Enabled) const override; 1030 1031 ArrayRef<const char *> getGCCRegNames() const override; 1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1033 bool validateAsmConstraint(const char *&Name, 1034 TargetInfo::ConstraintInfo &Info) const override { 1035 switch (*Name) { 1036 default: return false; 1037 case 'O': // Zero 1038 break; 1039 case 'b': // Base register 1040 case 'f': // Floating point register 1041 Info.setAllowsRegister(); 1042 break; 1043 // FIXME: The following are added to allow parsing. 1044 // I just took a guess at what the actions should be. 1045 // Also, is more specific checking needed? I.e. specific registers? 1046 case 'd': // Floating point register (containing 64-bit value) 1047 case 'v': // Altivec vector register 1048 Info.setAllowsRegister(); 1049 break; 1050 case 'w': 1051 switch (Name[1]) { 1052 case 'd':// VSX vector register to hold vector double data 1053 case 'f':// VSX vector register to hold vector float data 1054 case 's':// VSX vector register to hold scalar float data 1055 case 'a':// Any VSX register 1056 case 'c':// An individual CR bit 1057 break; 1058 default: 1059 return false; 1060 } 1061 Info.setAllowsRegister(); 1062 Name++; // Skip over 'w'. 1063 break; 1064 case 'h': // `MQ', `CTR', or `LINK' register 1065 case 'q': // `MQ' register 1066 case 'c': // `CTR' register 1067 case 'l': // `LINK' register 1068 case 'x': // `CR' register (condition register) number 0 1069 case 'y': // `CR' register (condition register) 1070 case 'z': // `XER[CA]' carry bit (part of the XER register) 1071 Info.setAllowsRegister(); 1072 break; 1073 case 'I': // Signed 16-bit constant 1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1075 // (use `L' instead for SImode constants) 1076 case 'K': // Unsigned 16-bit constant 1077 case 'L': // Signed 16-bit constant shifted left 16 bits 1078 case 'M': // Constant larger than 31 1079 case 'N': // Exact power of 2 1080 case 'P': // Constant whose negation is a signed 16-bit constant 1081 case 'G': // Floating point constant that can be loaded into a 1082 // register with one instruction per word 1083 case 'H': // Integer/Floating point constant that can be loaded 1084 // into a register using three instructions 1085 break; 1086 case 'm': // Memory operand. Note that on PowerPC targets, m can 1087 // include addresses that update the base register. It 1088 // is therefore only safe to use `m' in an asm statement 1089 // if that asm statement accesses the operand exactly once. 1090 // The asm statement must also use `%U<opno>' as a 1091 // placeholder for the "update" flag in the corresponding 1092 // load or store instruction. For example: 1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1094 // is correct but: 1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1096 // is not. Use es rather than m if you don't want the base 1097 // register to be updated. 1098 case 'e': 1099 if (Name[1] != 's') 1100 return false; 1101 // es: A "stable" memory operand; that is, one which does not 1102 // include any automodification of the base register. Unlike 1103 // `m', this constraint can be used in asm statements that 1104 // might access the operand several times, or that might not 1105 // access it at all. 1106 Info.setAllowsMemory(); 1107 Name++; // Skip over 'e'. 1108 break; 1109 case 'Q': // Memory operand that is an offset from a register (it is 1110 // usually better to use `m' or `es' in asm statements) 1111 case 'Z': // Memory operand that is an indexed or indirect from a 1112 // register (it is usually better to use `m' or `es' in 1113 // asm statements) 1114 Info.setAllowsMemory(); 1115 Info.setAllowsRegister(); 1116 break; 1117 case 'R': // AIX TOC entry 1118 case 'a': // Address operand that is an indexed or indirect from a 1119 // register (`p' is preferable for asm statements) 1120 case 'S': // Constant suitable as a 64-bit mask operand 1121 case 'T': // Constant suitable as a 32-bit mask operand 1122 case 'U': // System V Release 4 small data area reference 1123 case 't': // AND masks that can be performed by two rldic{l, r} 1124 // instructions 1125 case 'W': // Vector constant that does not require memory 1126 case 'j': // Vector constant that is all zeros. 1127 break; 1128 // End FIXME. 1129 } 1130 return true; 1131 } 1132 std::string convertConstraint(const char *&Constraint) const override { 1133 std::string R; 1134 switch (*Constraint) { 1135 case 'e': 1136 case 'w': 1137 // Two-character constraint; add "^" hint for later parsing. 1138 R = std::string("^") + std::string(Constraint, 2); 1139 Constraint++; 1140 break; 1141 default: 1142 return TargetInfo::convertConstraint(Constraint); 1143 } 1144 return R; 1145 } 1146 const char *getClobbers() const override { 1147 return ""; 1148 } 1149 int getEHDataRegisterNumber(unsigned RegNo) const override { 1150 if (RegNo == 0) return 3; 1151 if (RegNo == 1) return 4; 1152 return -1; 1153 } 1154 1155 bool hasSjLjLowering() const override { 1156 return true; 1157 } 1158 1159 bool useFloat128ManglingForLongDouble() const override { 1160 return LongDoubleWidth == 128 && 1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1162 getTriple().isOSBinFormatELF(); 1163 } 1164 }; 1165 1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1167 #define BUILTIN(ID, TYPE, ATTRS) \ 1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1171 #include "clang/Basic/BuiltinsPPC.def" 1172 }; 1173 1174 /// handleTargetFeatures - Perform initialization based on the user 1175 /// configured set of features. 1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1177 DiagnosticsEngine &Diags) { 1178 for (const auto &Feature : Features) { 1179 if (Feature == "+altivec") { 1180 HasAltivec = true; 1181 } else if (Feature == "+vsx") { 1182 HasVSX = true; 1183 } else if (Feature == "+bpermd") { 1184 HasBPERMD = true; 1185 } else if (Feature == "+extdiv") { 1186 HasExtDiv = true; 1187 } else if (Feature == "+power8-vector") { 1188 HasP8Vector = true; 1189 } else if (Feature == "+crypto") { 1190 HasP8Crypto = true; 1191 } else if (Feature == "+direct-move") { 1192 HasDirectMove = true; 1193 } else if (Feature == "+qpx") { 1194 HasQPX = true; 1195 } else if (Feature == "+htm") { 1196 HasHTM = true; 1197 } else if (Feature == "+float128") { 1198 HasFloat128 = true; 1199 } else if (Feature == "+power9-vector") { 1200 HasP9Vector = true; 1201 } 1202 // TODO: Finish this list and add an assert that we've handled them 1203 // all. 1204 } 1205 1206 return true; 1207 } 1208 1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1210 /// #defines that are not tied to a specific subtarget. 1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1212 MacroBuilder &Builder) const { 1213 // Target identification. 1214 Builder.defineMacro("__ppc__"); 1215 Builder.defineMacro("__PPC__"); 1216 Builder.defineMacro("_ARCH_PPC"); 1217 Builder.defineMacro("__powerpc__"); 1218 Builder.defineMacro("__POWERPC__"); 1219 if (PointerWidth == 64) { 1220 Builder.defineMacro("_ARCH_PPC64"); 1221 Builder.defineMacro("__powerpc64__"); 1222 Builder.defineMacro("__ppc64__"); 1223 Builder.defineMacro("__PPC64__"); 1224 } 1225 1226 // Target properties. 1227 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1228 Builder.defineMacro("_LITTLE_ENDIAN"); 1229 } else { 1230 if (getTriple().getOS() != llvm::Triple::NetBSD && 1231 getTriple().getOS() != llvm::Triple::OpenBSD) 1232 Builder.defineMacro("_BIG_ENDIAN"); 1233 } 1234 1235 // ABI options. 1236 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1237 Builder.defineMacro("_CALL_ELF", "1"); 1238 if (ABI == "elfv2") 1239 Builder.defineMacro("_CALL_ELF", "2"); 1240 1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1242 // our suppport post-dates this and it should work on all 64-bit ppc linux 1243 // platforms. It is guaranteed to work on all elfv2 platforms. 1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1245 Builder.defineMacro("_CALL_LINUX", "1"); 1246 1247 // Subtarget options. 1248 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1250 1251 // FIXME: Should be controlled by command line option. 1252 if (LongDoubleWidth == 128) { 1253 Builder.defineMacro("__LONG_DOUBLE_128__"); 1254 Builder.defineMacro("__LONGDOUBLE128"); 1255 } 1256 1257 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1258 if (ABI == "elfv2" || 1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1261 1262 // CPU identification. 1263 ArchDefineTypes defs = 1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1265 .Case("440", ArchDefineName) 1266 .Case("450", ArchDefineName | ArchDefine440) 1267 .Case("601", ArchDefineName) 1268 .Case("602", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603", ArchDefineName | ArchDefinePpcgr) 1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1272 .Case("604", ArchDefineName | ArchDefinePpcgr) 1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1274 .Case("620", ArchDefineName | ArchDefinePpcgr) 1275 .Case("630", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1277 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1278 .Case("750", ArchDefineName | ArchDefinePpcgr) 1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1280 ArchDefinePpcsq) 1281 .Case("a2", ArchDefineA2) 1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1283 .Case("pwr3", ArchDefinePpcgr) 1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1286 ArchDefinePpcsq) 1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1288 ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1293 ArchDefinePpcsq) 1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1296 ArchDefinePpcgr | ArchDefinePpcsq) 1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("power3", ArchDefinePpcgr) 1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1307 ArchDefinePpcsq) 1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1309 ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1311 ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1314 ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1317 ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | 1319 ArchDefinePpcsq) 1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1321 ArchDefinePwr6 | ArchDefinePwr5x | 1322 ArchDefinePwr5 | ArchDefinePwr4 | 1323 ArchDefinePpcgr | ArchDefinePpcsq) 1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1325 ArchDefinePwr6x | ArchDefinePwr6 | 1326 ArchDefinePwr5x | ArchDefinePwr5 | 1327 ArchDefinePwr4 | ArchDefinePpcgr | 1328 ArchDefinePpcsq) 1329 // powerpc64le automatically defaults to at least power8. 1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1331 ArchDefinePwr6 | ArchDefinePwr5x | 1332 ArchDefinePwr5 | ArchDefinePwr4 | 1333 ArchDefinePpcgr | ArchDefinePpcsq) 1334 .Default(ArchDefineNone); 1335 1336 if (defs & ArchDefineName) 1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1338 if (defs & ArchDefinePpcgr) 1339 Builder.defineMacro("_ARCH_PPCGR"); 1340 if (defs & ArchDefinePpcsq) 1341 Builder.defineMacro("_ARCH_PPCSQ"); 1342 if (defs & ArchDefine440) 1343 Builder.defineMacro("_ARCH_440"); 1344 if (defs & ArchDefine603) 1345 Builder.defineMacro("_ARCH_603"); 1346 if (defs & ArchDefine604) 1347 Builder.defineMacro("_ARCH_604"); 1348 if (defs & ArchDefinePwr4) 1349 Builder.defineMacro("_ARCH_PWR4"); 1350 if (defs & ArchDefinePwr5) 1351 Builder.defineMacro("_ARCH_PWR5"); 1352 if (defs & ArchDefinePwr5x) 1353 Builder.defineMacro("_ARCH_PWR5X"); 1354 if (defs & ArchDefinePwr6) 1355 Builder.defineMacro("_ARCH_PWR6"); 1356 if (defs & ArchDefinePwr6x) 1357 Builder.defineMacro("_ARCH_PWR6X"); 1358 if (defs & ArchDefinePwr7) 1359 Builder.defineMacro("_ARCH_PWR7"); 1360 if (defs & ArchDefinePwr8) 1361 Builder.defineMacro("_ARCH_PWR8"); 1362 if (defs & ArchDefinePwr9) 1363 Builder.defineMacro("_ARCH_PWR9"); 1364 if (defs & ArchDefineA2) 1365 Builder.defineMacro("_ARCH_A2"); 1366 if (defs & ArchDefineA2q) { 1367 Builder.defineMacro("_ARCH_A2Q"); 1368 Builder.defineMacro("_ARCH_QP"); 1369 } 1370 1371 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1372 Builder.defineMacro("__bg__"); 1373 Builder.defineMacro("__THW_BLUEGENE__"); 1374 Builder.defineMacro("__bgq__"); 1375 Builder.defineMacro("__TOS_BGQ__"); 1376 } 1377 1378 if (HasAltivec) { 1379 Builder.defineMacro("__VEC__", "10206"); 1380 Builder.defineMacro("__ALTIVEC__"); 1381 } 1382 if (HasVSX) 1383 Builder.defineMacro("__VSX__"); 1384 if (HasP8Vector) 1385 Builder.defineMacro("__POWER8_VECTOR__"); 1386 if (HasP8Crypto) 1387 Builder.defineMacro("__CRYPTO__"); 1388 if (HasHTM) 1389 Builder.defineMacro("__HTM__"); 1390 if (HasFloat128) 1391 Builder.defineMacro("__FLOAT128__"); 1392 if (HasP9Vector) 1393 Builder.defineMacro("__POWER9_VECTOR__"); 1394 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1398 if (PointerWidth == 64) 1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1400 1401 // We have support for the bswap intrinsics so we can define this. 1402 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1403 1404 // FIXME: The following are not yet generated here by Clang, but are 1405 // generated by GCC: 1406 // 1407 // _SOFT_FLOAT_ 1408 // __RECIP_PRECISION__ 1409 // __APPLE_ALTIVEC__ 1410 // __RECIP__ 1411 // __RECIPF__ 1412 // __RSQRTE__ 1413 // __RSQRTEF__ 1414 // _SOFT_DOUBLE_ 1415 // __NO_LWSYNC__ 1416 // __CMODEL_MEDIUM__ 1417 // __CMODEL_LARGE__ 1418 // _CALL_SYSV 1419 // _CALL_DARWIN 1420 // __NO_FPRS__ 1421 } 1422 1423 // Handle explicit options being passed to the compiler here: if we've 1424 // explicitly turned off vsx and turned on any of: 1425 // - power8-vector 1426 // - direct-move 1427 // - float128 1428 // - power9-vector 1429 // then go ahead and error since the customer has expressed an incompatible 1430 // set of options. 1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1432 const std::vector<std::string> &FeaturesVec) { 1433 1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1435 FeaturesVec.end()) { 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1444 FeaturesVec.end()) { 1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1446 << "-mno-vsx"; 1447 return false; 1448 } 1449 1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1451 FeaturesVec.end()) { 1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1453 << "-mno-vsx"; 1454 return false; 1455 } 1456 1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1458 FeaturesVec.end()) { 1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1460 << "-mno-vsx"; 1461 return false; 1462 } 1463 } 1464 1465 return true; 1466 } 1467 1468 bool PPCTargetInfo::initFeatureMap( 1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1470 const std::vector<std::string> &FeaturesVec) const { 1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("7400", true) 1473 .Case("g4", true) 1474 .Case("7450", true) 1475 .Case("g4+", true) 1476 .Case("970", true) 1477 .Case("g5", true) 1478 .Case("pwr6", true) 1479 .Case("pwr7", true) 1480 .Case("pwr8", true) 1481 .Case("pwr9", true) 1482 .Case("ppc64", true) 1483 .Case("ppc64le", true) 1484 .Default(false); 1485 1486 Features["qpx"] = (CPU == "a2q"); 1487 Features["power9-vector"] = (CPU == "pwr9"); 1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("ppc64le", true) 1490 .Case("pwr9", true) 1491 .Case("pwr8", true) 1492 .Default(false); 1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1494 .Case("ppc64le", true) 1495 .Case("pwr9", true) 1496 .Case("pwr8", true) 1497 .Default(false); 1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1499 .Case("ppc64le", true) 1500 .Case("pwr9", true) 1501 .Case("pwr8", true) 1502 .Case("pwr7", true) 1503 .Default(false); 1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1505 .Case("ppc64le", true) 1506 .Case("pwr9", true) 1507 .Case("pwr8", true) 1508 .Case("pwr7", true) 1509 .Default(false); 1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Default(false); 1526 1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1528 return false; 1529 1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1531 } 1532 1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1534 return llvm::StringSwitch<bool>(Feature) 1535 .Case("powerpc", true) 1536 .Case("altivec", HasAltivec) 1537 .Case("vsx", HasVSX) 1538 .Case("power8-vector", HasP8Vector) 1539 .Case("crypto", HasP8Crypto) 1540 .Case("direct-move", HasDirectMove) 1541 .Case("qpx", HasQPX) 1542 .Case("htm", HasHTM) 1543 .Case("bpermd", HasBPERMD) 1544 .Case("extdiv", HasExtDiv) 1545 .Case("float128", HasFloat128) 1546 .Case("power9-vector", HasP9Vector) 1547 .Default(false); 1548 } 1549 1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1551 StringRef Name, bool Enabled) const { 1552 if (Enabled) { 1553 // If we're enabling any of the vsx based features then enable vsx and 1554 // altivec. We'll diagnose any problems later. 1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1556 .Case("vsx", true) 1557 .Case("direct-move", true) 1558 .Case("power8-vector", true) 1559 .Case("power9-vector", true) 1560 .Case("float128", true) 1561 .Default(false); 1562 if (FeatureHasVSX) 1563 Features["vsx"] = Features["altivec"] = true; 1564 if (Name == "power9-vector") 1565 Features["power8-vector"] = true; 1566 Features[Name] = true; 1567 } else { 1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1569 // features. 1570 if ((Name == "altivec") || (Name == "vsx")) 1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1572 Features["float128"] = Features["power9-vector"] = false; 1573 if (Name == "power8-vector") 1574 Features["power9-vector"] = false; 1575 Features[Name] = false; 1576 } 1577 } 1578 1579 const char * const PPCTargetInfo::GCCRegNames[] = { 1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1588 "mq", "lr", "ctr", "ap", 1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1590 "xer", 1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1595 "vrsave", "vscr", 1596 "spe_acc", "spefscr", 1597 "sfp" 1598 }; 1599 1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1601 return llvm::makeArrayRef(GCCRegNames); 1602 } 1603 1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1605 // While some of these aliases do map to different registers 1606 // they still share the same register name. 1607 { { "0" }, "r0" }, 1608 { { "1"}, "r1" }, 1609 { { "2" }, "r2" }, 1610 { { "3" }, "r3" }, 1611 { { "4" }, "r4" }, 1612 { { "5" }, "r5" }, 1613 { { "6" }, "r6" }, 1614 { { "7" }, "r7" }, 1615 { { "8" }, "r8" }, 1616 { { "9" }, "r9" }, 1617 { { "10" }, "r10" }, 1618 { { "11" }, "r11" }, 1619 { { "12" }, "r12" }, 1620 { { "13" }, "r13" }, 1621 { { "14" }, "r14" }, 1622 { { "15" }, "r15" }, 1623 { { "16" }, "r16" }, 1624 { { "17" }, "r17" }, 1625 { { "18" }, "r18" }, 1626 { { "19" }, "r19" }, 1627 { { "20" }, "r20" }, 1628 { { "21" }, "r21" }, 1629 { { "22" }, "r22" }, 1630 { { "23" }, "r23" }, 1631 { { "24" }, "r24" }, 1632 { { "25" }, "r25" }, 1633 { { "26" }, "r26" }, 1634 { { "27" }, "r27" }, 1635 { { "28" }, "r28" }, 1636 { { "29" }, "r29" }, 1637 { { "30" }, "r30" }, 1638 { { "31" }, "r31" }, 1639 { { "fr0" }, "f0" }, 1640 { { "fr1" }, "f1" }, 1641 { { "fr2" }, "f2" }, 1642 { { "fr3" }, "f3" }, 1643 { { "fr4" }, "f4" }, 1644 { { "fr5" }, "f5" }, 1645 { { "fr6" }, "f6" }, 1646 { { "fr7" }, "f7" }, 1647 { { "fr8" }, "f8" }, 1648 { { "fr9" }, "f9" }, 1649 { { "fr10" }, "f10" }, 1650 { { "fr11" }, "f11" }, 1651 { { "fr12" }, "f12" }, 1652 { { "fr13" }, "f13" }, 1653 { { "fr14" }, "f14" }, 1654 { { "fr15" }, "f15" }, 1655 { { "fr16" }, "f16" }, 1656 { { "fr17" }, "f17" }, 1657 { { "fr18" }, "f18" }, 1658 { { "fr19" }, "f19" }, 1659 { { "fr20" }, "f20" }, 1660 { { "fr21" }, "f21" }, 1661 { { "fr22" }, "f22" }, 1662 { { "fr23" }, "f23" }, 1663 { { "fr24" }, "f24" }, 1664 { { "fr25" }, "f25" }, 1665 { { "fr26" }, "f26" }, 1666 { { "fr27" }, "f27" }, 1667 { { "fr28" }, "f28" }, 1668 { { "fr29" }, "f29" }, 1669 { { "fr30" }, "f30" }, 1670 { { "fr31" }, "f31" }, 1671 { { "cc" }, "cr0" }, 1672 }; 1673 1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1675 return llvm::makeArrayRef(GCCRegAliases); 1676 } 1677 1678 class PPC32TargetInfo : public PPCTargetInfo { 1679 public: 1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1681 : PPCTargetInfo(Triple, Opts) { 1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::Linux: 1686 case llvm::Triple::FreeBSD: 1687 case llvm::Triple::NetBSD: 1688 SizeType = UnsignedInt; 1689 PtrDiffType = SignedInt; 1690 IntPtrType = SignedInt; 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1697 LongDoubleWidth = LongDoubleAlign = 64; 1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1699 } 1700 1701 // PPC32 supports atomics up to 4 bytes. 1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1703 } 1704 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 // This is the ELF definition, and is overridden by the Darwin sub-target 1707 return TargetInfo::PowerABIBuiltinVaList; 1708 } 1709 }; 1710 1711 // Note: ABI differences may eventually require us to have a separate 1712 // TargetInfo for little endian. 1713 class PPC64TargetInfo : public PPCTargetInfo { 1714 public: 1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : PPCTargetInfo(Triple, Opts) { 1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1718 IntMaxType = SignedLong; 1719 Int64Type = SignedLong; 1720 1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1722 resetDataLayout("e-m:e-i64:64-n32:64"); 1723 ABI = "elfv2"; 1724 } else { 1725 resetDataLayout("E-m:e-i64:64-n32:64"); 1726 ABI = "elfv1"; 1727 } 1728 1729 switch (getTriple().getOS()) { 1730 case llvm::Triple::FreeBSD: 1731 LongDoubleWidth = LongDoubleAlign = 64; 1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1733 break; 1734 case llvm::Triple::NetBSD: 1735 IntMaxType = SignedLongLong; 1736 Int64Type = SignedLongLong; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 // PPC64 supports atomics up to 8 bytes. 1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1744 } 1745 BuiltinVaListKind getBuiltinVaListKind() const override { 1746 return TargetInfo::CharPtrBuiltinVaList; 1747 } 1748 // PPC64 Linux-specific ABI options. 1749 bool setABI(const std::string &Name) override { 1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1751 ABI = Name; 1752 return true; 1753 } 1754 return false; 1755 } 1756 }; 1757 1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1759 public: 1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1762 HasAlignMac68kSupport = true; 1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1765 LongLongAlign = 32; 1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1767 } 1768 BuiltinVaListKind getBuiltinVaListKind() const override { 1769 return TargetInfo::CharPtrBuiltinVaList; 1770 } 1771 }; 1772 1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1774 public: 1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 resetDataLayout("E-m:o-i64:64-n32:64"); 1779 } 1780 }; 1781 1782 static const unsigned NVPTXAddrSpaceMap[] = { 1783 0, // Default 1784 1, // opencl_global 1785 3, // opencl_local 1786 4, // opencl_constant 1787 // FIXME: generic has to be added to the target 1788 0, // opencl_generic 1789 1, // cuda_device 1790 4, // cuda_constant 1791 3, // cuda_shared 1792 }; 1793 1794 class NVPTXTargetInfo : public TargetInfo { 1795 static const char *const GCCRegNames[]; 1796 static const Builtin::Info BuiltinInfo[]; 1797 CudaArch GPU; 1798 std::unique_ptr<TargetInfo> HostTarget; 1799 1800 public: 1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1802 unsigned TargetPointerWidth) 1803 : TargetInfo(Triple) { 1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1805 "NVPTX only supports 32- and 64-bit modes."); 1806 1807 TLSSupported = false; 1808 AddrSpaceMap = &NVPTXAddrSpaceMap; 1809 UseAddrSpaceMapMangling = true; 1810 1811 // Define available target features 1812 // These must be defined in sorted order! 1813 NoAsmVariants = true; 1814 GPU = CudaArch::SM_20; 1815 1816 if (TargetPointerWidth == 32) 1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1818 else 1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1820 1821 // If possible, get a TargetInfo for our host triple, so we can match its 1822 // types. 1823 llvm::Triple HostTriple(Opts.HostTriple); 1824 if (!HostTriple.isNVPTX()) 1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1826 1827 // If no host target, make some guesses about the data layout and return. 1828 if (!HostTarget) { 1829 LongWidth = LongAlign = TargetPointerWidth; 1830 PointerWidth = PointerAlign = TargetPointerWidth; 1831 switch (TargetPointerWidth) { 1832 case 32: 1833 SizeType = TargetInfo::UnsignedInt; 1834 PtrDiffType = TargetInfo::SignedInt; 1835 IntPtrType = TargetInfo::SignedInt; 1836 break; 1837 case 64: 1838 SizeType = TargetInfo::UnsignedLong; 1839 PtrDiffType = TargetInfo::SignedLong; 1840 IntPtrType = TargetInfo::SignedLong; 1841 break; 1842 default: 1843 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1844 } 1845 return; 1846 } 1847 1848 // Copy properties from host target. 1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1851 BoolWidth = HostTarget->getBoolWidth(); 1852 BoolAlign = HostTarget->getBoolAlign(); 1853 IntWidth = HostTarget->getIntWidth(); 1854 IntAlign = HostTarget->getIntAlign(); 1855 HalfWidth = HostTarget->getHalfWidth(); 1856 HalfAlign = HostTarget->getHalfAlign(); 1857 FloatWidth = HostTarget->getFloatWidth(); 1858 FloatAlign = HostTarget->getFloatAlign(); 1859 DoubleWidth = HostTarget->getDoubleWidth(); 1860 DoubleAlign = HostTarget->getDoubleAlign(); 1861 LongWidth = HostTarget->getLongWidth(); 1862 LongAlign = HostTarget->getLongAlign(); 1863 LongLongWidth = HostTarget->getLongLongWidth(); 1864 LongLongAlign = HostTarget->getLongLongAlign(); 1865 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1866 NewAlign = HostTarget->getNewAlign(); 1867 DefaultAlignForAttributeAligned = 1868 HostTarget->getDefaultAlignForAttributeAligned(); 1869 SizeType = HostTarget->getSizeType(); 1870 IntMaxType = HostTarget->getIntMaxType(); 1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1872 IntPtrType = HostTarget->getIntPtrType(); 1873 WCharType = HostTarget->getWCharType(); 1874 WIntType = HostTarget->getWIntType(); 1875 Char16Type = HostTarget->getChar16Type(); 1876 Char32Type = HostTarget->getChar32Type(); 1877 Int64Type = HostTarget->getInt64Type(); 1878 SigAtomicType = HostTarget->getSigAtomicType(); 1879 ProcessIDType = HostTarget->getProcessIDType(); 1880 1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1882 UseZeroLengthBitfieldAlignment = 1883 HostTarget->useZeroLengthBitfieldAlignment(); 1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1886 1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1888 // we need those macros to be identical on host and device, because (among 1889 // other things) they affect which standard library classes are defined, and 1890 // we need all classes to be defined on both the host and device. 1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1892 1893 // Properties intentionally not copied from host: 1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1895 // host/device boundary. 1896 // - SuitableAlign: Not visible across the host/device boundary, and may 1897 // correctly be different on host/device, e.g. if host has wider vector 1898 // types than device. 1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1900 // as its double type, but that's not necessarily true on the host. 1901 // TODO: nvcc emits a warning when using long double on device; we should 1902 // do the same. 1903 } 1904 void getTargetDefines(const LangOptions &Opts, 1905 MacroBuilder &Builder) const override { 1906 Builder.defineMacro("__PTX__"); 1907 Builder.defineMacro("__NVPTX__"); 1908 if (Opts.CUDAIsDevice) { 1909 // Set __CUDA_ARCH__ for the GPU specified. 1910 std::string CUDAArchCode = [this] { 1911 switch (GPU) { 1912 case CudaArch::UNKNOWN: 1913 assert(false && "No GPU arch when compiling CUDA device code."); 1914 return ""; 1915 case CudaArch::SM_20: 1916 return "200"; 1917 case CudaArch::SM_21: 1918 return "210"; 1919 case CudaArch::SM_30: 1920 return "300"; 1921 case CudaArch::SM_32: 1922 return "320"; 1923 case CudaArch::SM_35: 1924 return "350"; 1925 case CudaArch::SM_37: 1926 return "370"; 1927 case CudaArch::SM_50: 1928 return "500"; 1929 case CudaArch::SM_52: 1930 return "520"; 1931 case CudaArch::SM_53: 1932 return "530"; 1933 case CudaArch::SM_60: 1934 return "600"; 1935 case CudaArch::SM_61: 1936 return "610"; 1937 case CudaArch::SM_62: 1938 return "620"; 1939 } 1940 llvm_unreachable("unhandled CudaArch"); 1941 }(); 1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1943 } 1944 } 1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1946 return llvm::makeArrayRef(BuiltinInfo, 1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1948 } 1949 bool 1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1951 StringRef CPU, 1952 const std::vector<std::string> &FeaturesVec) const override { 1953 Features["satom"] = GPU >= CudaArch::SM_60; 1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1955 } 1956 1957 bool hasFeature(StringRef Feature) const override { 1958 return llvm::StringSwitch<bool>(Feature) 1959 .Cases("ptx", "nvptx", true) 1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1961 .Default(false); 1962 } 1963 1964 ArrayRef<const char *> getGCCRegNames() const override; 1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1966 // No aliases. 1967 return None; 1968 } 1969 bool validateAsmConstraint(const char *&Name, 1970 TargetInfo::ConstraintInfo &Info) const override { 1971 switch (*Name) { 1972 default: 1973 return false; 1974 case 'c': 1975 case 'h': 1976 case 'r': 1977 case 'l': 1978 case 'f': 1979 case 'd': 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 } 1984 const char *getClobbers() const override { 1985 // FIXME: Is this really right? 1986 return ""; 1987 } 1988 BuiltinVaListKind getBuiltinVaListKind() const override { 1989 // FIXME: implement 1990 return TargetInfo::CharPtrBuiltinVaList; 1991 } 1992 bool setCPU(const std::string &Name) override { 1993 GPU = StringToCudaArch(Name); 1994 return GPU != CudaArch::UNKNOWN; 1995 } 1996 void setSupportedOpenCLOpts() override { 1997 auto &Opts = getSupportedOpenCLOpts(); 1998 Opts.support("cl_clang_storage_class_specifiers"); 1999 Opts.support("cl_khr_gl_sharing"); 2000 Opts.support("cl_khr_icd"); 2001 2002 Opts.support("cl_khr_fp64"); 2003 Opts.support("cl_khr_byte_addressable_store"); 2004 Opts.support("cl_khr_global_int32_base_atomics"); 2005 Opts.support("cl_khr_global_int32_extended_atomics"); 2006 Opts.support("cl_khr_local_int32_base_atomics"); 2007 Opts.support("cl_khr_local_int32_extended_atomics"); 2008 } 2009 2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2011 // CUDA compilations support all of the host's calling conventions. 2012 // 2013 // TODO: We should warn if you apply a non-default CC to anything other than 2014 // a host function. 2015 if (HostTarget) 2016 return HostTarget->checkCallingConvention(CC); 2017 return CCCR_Warning; 2018 } 2019 }; 2020 2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2022 #define BUILTIN(ID, TYPE, ATTRS) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2028 #include "clang/Basic/BuiltinsNVPTX.def" 2029 }; 2030 2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2032 2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2038 4, // Default 2039 1, // opencl_global 2040 3, // opencl_local 2041 2, // opencl_constant 2042 4, // opencl_generic 2043 1, // cuda_device 2044 2, // cuda_constant 2045 3 // cuda_shared 2046 }; 2047 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2048 0, // Default 2049 1, // opencl_global 2050 3, // opencl_local 2051 2, // opencl_constant 2052 0, // opencl_generic 2053 1, // cuda_device 2054 2, // cuda_constant 2055 3 // cuda_shared 2056 }; 2057 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2058 0, // Default 2059 1, // opencl_global 2060 3, // opencl_local 2061 2, // opencl_constant 2062 4, // opencl_generic 2063 1, // cuda_device 2064 2, // cuda_constant 2065 3 // cuda_shared 2066 }; 2067 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2068 5, // Default 2069 1, // opencl_global 2070 3, // opencl_local 2071 2, // opencl_constant 2072 0, // opencl_generic 2073 1, // cuda_device 2074 2, // cuda_constant 2075 3 // cuda_shared 2076 }; 2077 2078 // If you edit the description strings, make sure you update 2079 // getPointerWidthV(). 2080 2081 static const char *const DataLayoutStringR600 = 2082 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2083 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2084 2085 static const char *const DataLayoutStringSIPrivateIsZero = 2086 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2087 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2088 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2089 2090 static const char *const DataLayoutStringSIGenericIsZero = 2091 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2092 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2093 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2094 2095 class AMDGPUTargetInfo final : public TargetInfo { 2096 static const Builtin::Info BuiltinInfo[]; 2097 static const char * const GCCRegNames[]; 2098 2099 struct AddrSpace { 2100 unsigned Generic, Global, Local, Constant, Private; 2101 AddrSpace(bool IsGenericZero_ = false){ 2102 if (IsGenericZero_) { 2103 Generic = 0; 2104 Global = 1; 2105 Local = 3; 2106 Constant = 2; 2107 Private = 5; 2108 } else { 2109 Generic = 4; 2110 Global = 1; 2111 Local = 3; 2112 Constant = 2; 2113 Private = 0; 2114 } 2115 } 2116 }; 2117 2118 /// \brief The GPU profiles supported by the AMDGPU target. 2119 enum GPUKind { 2120 GK_NONE, 2121 GK_R600, 2122 GK_R600_DOUBLE_OPS, 2123 GK_R700, 2124 GK_R700_DOUBLE_OPS, 2125 GK_EVERGREEN, 2126 GK_EVERGREEN_DOUBLE_OPS, 2127 GK_NORTHERN_ISLANDS, 2128 GK_CAYMAN, 2129 GK_GFX6, 2130 GK_GFX7, 2131 GK_GFX8, 2132 GK_GFX9 2133 } GPU; 2134 2135 bool hasFP64:1; 2136 bool hasFMAF:1; 2137 bool hasLDEXPF:1; 2138 const AddrSpace AS; 2139 2140 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2141 return parseAMDGCNName(GPUName) >= GK_GFX9; 2142 } 2143 2144 static bool isAMDGCN(const llvm::Triple &TT) { 2145 return TT.getArch() == llvm::Triple::amdgcn; 2146 } 2147 2148 static bool isGenericZero(const llvm::Triple &TT) { 2149 return TT.getEnvironmentName() == "amdgiz" || 2150 TT.getEnvironmentName() == "amdgizcl"; 2151 } 2152 public: 2153 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2154 : TargetInfo(Triple) , 2155 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2156 hasFP64(false), 2157 hasFMAF(false), 2158 hasLDEXPF(false), 2159 AS(isGenericZero(Triple)){ 2160 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2161 hasFP64 = true; 2162 hasFMAF = true; 2163 hasLDEXPF = true; 2164 } 2165 auto IsGenericZero = isGenericZero(Triple); 2166 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2167 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2168 DataLayoutStringSIPrivateIsZero) 2169 : DataLayoutStringR600); 2170 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2171 2172 UseAddrSpaceMapMangling = true; 2173 } 2174 2175 void adjust(LangOptions &Opts) override { 2176 TargetInfo::adjust(Opts); 2177 if (isGenericZero(getTriple())) { 2178 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2179 : &AMDGPUNonOpenCLGenericIsZeroMap; 2180 } else { 2181 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2182 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2183 } 2184 } 2185 2186 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2187 if (GPU <= GK_CAYMAN) 2188 return 32; 2189 2190 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2191 return 32; 2192 } 2193 return 64; 2194 } 2195 2196 uint64_t getMaxPointerWidth() const override { 2197 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2198 } 2199 2200 const char * getClobbers() const override { 2201 return ""; 2202 } 2203 2204 ArrayRef<const char *> getGCCRegNames() const override; 2205 2206 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2207 return None; 2208 } 2209 2210 bool validateAsmConstraint(const char *&Name, 2211 TargetInfo::ConstraintInfo &Info) const override { 2212 switch (*Name) { 2213 default: break; 2214 case 'v': // vgpr 2215 case 's': // sgpr 2216 Info.setAllowsRegister(); 2217 return true; 2218 } 2219 return false; 2220 } 2221 2222 bool initFeatureMap(llvm::StringMap<bool> &Features, 2223 DiagnosticsEngine &Diags, StringRef CPU, 2224 const std::vector<std::string> &FeatureVec) const override; 2225 2226 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2227 TargetOptions &TargetOpts) const override { 2228 bool hasFP32Denormals = false; 2229 bool hasFP64Denormals = false; 2230 for (auto &I : TargetOpts.FeaturesAsWritten) { 2231 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2232 hasFP32Denormals = true; 2233 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2234 hasFP64Denormals = true; 2235 } 2236 if (!hasFP32Denormals) 2237 TargetOpts.Features.push_back( 2238 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2239 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2240 // Always do not flush fp64 or fp16 denorms. 2241 if (!hasFP64Denormals && hasFP64) 2242 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2243 } 2244 2245 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2246 return llvm::makeArrayRef(BuiltinInfo, 2247 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2248 } 2249 2250 void getTargetDefines(const LangOptions &Opts, 2251 MacroBuilder &Builder) const override { 2252 if (getTriple().getArch() == llvm::Triple::amdgcn) 2253 Builder.defineMacro("__AMDGCN__"); 2254 else 2255 Builder.defineMacro("__R600__"); 2256 2257 if (hasFMAF) 2258 Builder.defineMacro("__HAS_FMAF__"); 2259 if (hasLDEXPF) 2260 Builder.defineMacro("__HAS_LDEXPF__"); 2261 if (hasFP64) 2262 Builder.defineMacro("__HAS_FP64__"); 2263 } 2264 2265 BuiltinVaListKind getBuiltinVaListKind() const override { 2266 return TargetInfo::CharPtrBuiltinVaList; 2267 } 2268 2269 static GPUKind parseR600Name(StringRef Name) { 2270 return llvm::StringSwitch<GPUKind>(Name) 2271 .Case("r600" , GK_R600) 2272 .Case("rv610", GK_R600) 2273 .Case("rv620", GK_R600) 2274 .Case("rv630", GK_R600) 2275 .Case("rv635", GK_R600) 2276 .Case("rs780", GK_R600) 2277 .Case("rs880", GK_R600) 2278 .Case("rv670", GK_R600_DOUBLE_OPS) 2279 .Case("rv710", GK_R700) 2280 .Case("rv730", GK_R700) 2281 .Case("rv740", GK_R700_DOUBLE_OPS) 2282 .Case("rv770", GK_R700_DOUBLE_OPS) 2283 .Case("palm", GK_EVERGREEN) 2284 .Case("cedar", GK_EVERGREEN) 2285 .Case("sumo", GK_EVERGREEN) 2286 .Case("sumo2", GK_EVERGREEN) 2287 .Case("redwood", GK_EVERGREEN) 2288 .Case("juniper", GK_EVERGREEN) 2289 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2290 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2291 .Case("barts", GK_NORTHERN_ISLANDS) 2292 .Case("turks", GK_NORTHERN_ISLANDS) 2293 .Case("caicos", GK_NORTHERN_ISLANDS) 2294 .Case("cayman", GK_CAYMAN) 2295 .Case("aruba", GK_CAYMAN) 2296 .Default(GK_NONE); 2297 } 2298 2299 static GPUKind parseAMDGCNName(StringRef Name) { 2300 return llvm::StringSwitch<GPUKind>(Name) 2301 .Case("tahiti", GK_GFX6) 2302 .Case("pitcairn", GK_GFX6) 2303 .Case("verde", GK_GFX6) 2304 .Case("oland", GK_GFX6) 2305 .Case("hainan", GK_GFX6) 2306 .Case("bonaire", GK_GFX7) 2307 .Case("kabini", GK_GFX7) 2308 .Case("kaveri", GK_GFX7) 2309 .Case("hawaii", GK_GFX7) 2310 .Case("mullins", GK_GFX7) 2311 .Case("gfx700", GK_GFX7) 2312 .Case("gfx701", GK_GFX7) 2313 .Case("gfx702", GK_GFX7) 2314 .Case("tonga", GK_GFX8) 2315 .Case("iceland", GK_GFX8) 2316 .Case("carrizo", GK_GFX8) 2317 .Case("fiji", GK_GFX8) 2318 .Case("stoney", GK_GFX8) 2319 .Case("polaris10", GK_GFX8) 2320 .Case("polaris11", GK_GFX8) 2321 .Case("gfx800", GK_GFX8) 2322 .Case("gfx801", GK_GFX8) 2323 .Case("gfx802", GK_GFX8) 2324 .Case("gfx803", GK_GFX8) 2325 .Case("gfx804", GK_GFX8) 2326 .Case("gfx810", GK_GFX8) 2327 .Case("gfx900", GK_GFX9) 2328 .Case("gfx901", GK_GFX9) 2329 .Default(GK_NONE); 2330 } 2331 2332 bool setCPU(const std::string &Name) override { 2333 if (getTriple().getArch() == llvm::Triple::amdgcn) 2334 GPU = parseAMDGCNName(Name); 2335 else 2336 GPU = parseR600Name(Name); 2337 2338 return GPU != GK_NONE; 2339 } 2340 2341 void setSupportedOpenCLOpts() override { 2342 auto &Opts = getSupportedOpenCLOpts(); 2343 Opts.support("cl_clang_storage_class_specifiers"); 2344 Opts.support("cl_khr_icd"); 2345 2346 if (hasFP64) 2347 Opts.support("cl_khr_fp64"); 2348 if (GPU >= GK_EVERGREEN) { 2349 Opts.support("cl_khr_byte_addressable_store"); 2350 Opts.support("cl_khr_global_int32_base_atomics"); 2351 Opts.support("cl_khr_global_int32_extended_atomics"); 2352 Opts.support("cl_khr_local_int32_base_atomics"); 2353 Opts.support("cl_khr_local_int32_extended_atomics"); 2354 } 2355 if (GPU >= GK_GFX6) { 2356 Opts.support("cl_khr_fp16"); 2357 Opts.support("cl_khr_int64_base_atomics"); 2358 Opts.support("cl_khr_int64_extended_atomics"); 2359 Opts.support("cl_khr_mipmap_image"); 2360 Opts.support("cl_khr_subgroups"); 2361 Opts.support("cl_khr_3d_image_writes"); 2362 Opts.support("cl_amd_media_ops"); 2363 Opts.support("cl_amd_media_ops2"); 2364 } 2365 } 2366 2367 LangAS::ID getOpenCLImageAddrSpace() const override { 2368 return LangAS::opencl_constant; 2369 } 2370 2371 /// \returns Target specific vtbl ptr address space. 2372 unsigned getVtblPtrAddressSpace() const override { 2373 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2374 // would be nice if we could use it here instead of using bare numbers (same 2375 // applies to getDWARFAddressSpace). 2376 return 2; // constant. 2377 } 2378 2379 /// \returns If a target requires an address within a target specific address 2380 /// space \p AddressSpace to be converted in order to be used, then return the 2381 /// corresponding target specific DWARF address space. 2382 /// 2383 /// \returns Otherwise return None and no conversion will be emitted in the 2384 /// DWARF. 2385 Optional<unsigned> getDWARFAddressSpace( 2386 unsigned AddressSpace) const override { 2387 const unsigned DWARF_Private = 1; 2388 const unsigned DWARF_Local = 2; 2389 if (AddressSpace == AS.Private) { 2390 return DWARF_Private; 2391 } else if (AddressSpace == AS.Local) { 2392 return DWARF_Local; 2393 } else { 2394 return None; 2395 } 2396 } 2397 2398 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2399 switch (CC) { 2400 default: 2401 return CCCR_Warning; 2402 case CC_C: 2403 case CC_OpenCLKernel: 2404 return CCCR_OK; 2405 } 2406 } 2407 2408 // In amdgcn target the null pointer in global, constant, and generic 2409 // address space has value 0 but in private and local address space has 2410 // value ~0. 2411 uint64_t getNullPointerValue(unsigned AS) const override { 2412 return AS == LangAS::opencl_local ? ~0 : 0; 2413 } 2414 }; 2415 2416 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2417 #define BUILTIN(ID, TYPE, ATTRS) \ 2418 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2419 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2420 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2421 #include "clang/Basic/BuiltinsAMDGPU.def" 2422 }; 2423 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2424 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2425 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2426 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2427 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2428 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2429 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2430 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2431 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2432 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2433 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2434 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2435 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2436 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2437 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2438 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2439 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2440 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2441 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2442 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2443 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2444 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2445 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2446 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2447 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2448 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2449 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2450 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2451 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2452 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2453 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2454 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2455 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2460 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2461 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2462 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2463 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2464 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2465 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2466 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2467 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2468 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2469 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2470 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2471 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2472 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2473 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2474 }; 2475 2476 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2477 return llvm::makeArrayRef(GCCRegNames); 2478 } 2479 2480 bool AMDGPUTargetInfo::initFeatureMap( 2481 llvm::StringMap<bool> &Features, 2482 DiagnosticsEngine &Diags, StringRef CPU, 2483 const std::vector<std::string> &FeatureVec) const { 2484 2485 // XXX - What does the member GPU mean if device name string passed here? 2486 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2487 if (CPU.empty()) 2488 CPU = "tahiti"; 2489 2490 switch (parseAMDGCNName(CPU)) { 2491 case GK_GFX6: 2492 case GK_GFX7: 2493 break; 2494 2495 case GK_GFX9: 2496 Features["gfx9-insts"] = true; 2497 LLVM_FALLTHROUGH; 2498 case GK_GFX8: 2499 Features["s-memrealtime"] = true; 2500 Features["16-bit-insts"] = true; 2501 Features["dpp"] = true; 2502 break; 2503 2504 case GK_NONE: 2505 return false; 2506 default: 2507 llvm_unreachable("unhandled subtarget"); 2508 } 2509 } else { 2510 if (CPU.empty()) 2511 CPU = "r600"; 2512 2513 switch (parseR600Name(CPU)) { 2514 case GK_R600: 2515 case GK_R700: 2516 case GK_EVERGREEN: 2517 case GK_NORTHERN_ISLANDS: 2518 break; 2519 case GK_R600_DOUBLE_OPS: 2520 case GK_R700_DOUBLE_OPS: 2521 case GK_EVERGREEN_DOUBLE_OPS: 2522 case GK_CAYMAN: 2523 Features["fp64"] = true; 2524 break; 2525 case GK_NONE: 2526 return false; 2527 default: 2528 llvm_unreachable("unhandled subtarget"); 2529 } 2530 } 2531 2532 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2533 } 2534 2535 const Builtin::Info BuiltinInfoX86[] = { 2536 #define BUILTIN(ID, TYPE, ATTRS) \ 2537 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2538 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2539 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2540 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2541 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2542 #include "clang/Basic/BuiltinsX86.def" 2543 2544 #define BUILTIN(ID, TYPE, ATTRS) \ 2545 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2546 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2548 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2549 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2550 #include "clang/Basic/BuiltinsX86_64.def" 2551 }; 2552 2553 2554 static const char* const GCCRegNames[] = { 2555 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2556 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2557 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2558 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2559 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2560 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2561 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2562 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2563 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2564 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2565 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2566 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2567 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2568 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2569 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2570 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2571 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2572 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2573 }; 2574 2575 const TargetInfo::AddlRegName AddlRegNames[] = { 2576 { { "al", "ah", "eax", "rax" }, 0 }, 2577 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2578 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2579 { { "dl", "dh", "edx", "rdx" }, 1 }, 2580 { { "esi", "rsi" }, 4 }, 2581 { { "edi", "rdi" }, 5 }, 2582 { { "esp", "rsp" }, 7 }, 2583 { { "ebp", "rbp" }, 6 }, 2584 { { "r8d", "r8w", "r8b" }, 38 }, 2585 { { "r9d", "r9w", "r9b" }, 39 }, 2586 { { "r10d", "r10w", "r10b" }, 40 }, 2587 { { "r11d", "r11w", "r11b" }, 41 }, 2588 { { "r12d", "r12w", "r12b" }, 42 }, 2589 { { "r13d", "r13w", "r13b" }, 43 }, 2590 { { "r14d", "r14w", "r14b" }, 44 }, 2591 { { "r15d", "r15w", "r15b" }, 45 }, 2592 }; 2593 2594 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2595 // most of the implementation can be shared. 2596 class X86TargetInfo : public TargetInfo { 2597 enum X86SSEEnum { 2598 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2599 } SSELevel = NoSSE; 2600 enum MMX3DNowEnum { 2601 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2602 } MMX3DNowLevel = NoMMX3DNow; 2603 enum XOPEnum { 2604 NoXOP, 2605 SSE4A, 2606 FMA4, 2607 XOP 2608 } XOPLevel = NoXOP; 2609 2610 bool HasAES = false; 2611 bool HasPCLMUL = false; 2612 bool HasLZCNT = false; 2613 bool HasRDRND = false; 2614 bool HasFSGSBASE = false; 2615 bool HasBMI = false; 2616 bool HasBMI2 = false; 2617 bool HasPOPCNT = false; 2618 bool HasRTM = false; 2619 bool HasPRFCHW = false; 2620 bool HasRDSEED = false; 2621 bool HasADX = false; 2622 bool HasTBM = false; 2623 bool HasLWP = false; 2624 bool HasFMA = false; 2625 bool HasF16C = false; 2626 bool HasAVX512CD = false; 2627 bool HasAVX512VPOPCNTDQ = false; 2628 bool HasAVX512ER = false; 2629 bool HasAVX512PF = false; 2630 bool HasAVX512DQ = false; 2631 bool HasAVX512BW = false; 2632 bool HasAVX512VL = false; 2633 bool HasAVX512VBMI = false; 2634 bool HasAVX512IFMA = false; 2635 bool HasSHA = false; 2636 bool HasMPX = false; 2637 bool HasSGX = false; 2638 bool HasCX16 = false; 2639 bool HasFXSR = false; 2640 bool HasXSAVE = false; 2641 bool HasXSAVEOPT = false; 2642 bool HasXSAVEC = false; 2643 bool HasXSAVES = false; 2644 bool HasMWAITX = false; 2645 bool HasCLZERO = false; 2646 bool HasPKU = false; 2647 bool HasCLFLUSHOPT = false; 2648 bool HasCLWB = false; 2649 bool HasMOVBE = false; 2650 bool HasPREFETCHWT1 = false; 2651 2652 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2653 /// 2654 /// Each enumeration represents a particular CPU supported by Clang. These 2655 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2656 enum CPUKind { 2657 CK_Generic, 2658 2659 /// \name i386 2660 /// i386-generation processors. 2661 //@{ 2662 CK_i386, 2663 //@} 2664 2665 /// \name i486 2666 /// i486-generation processors. 2667 //@{ 2668 CK_i486, 2669 CK_WinChipC6, 2670 CK_WinChip2, 2671 CK_C3, 2672 //@} 2673 2674 /// \name i586 2675 /// i586-generation processors, P5 microarchitecture based. 2676 //@{ 2677 CK_i586, 2678 CK_Pentium, 2679 CK_PentiumMMX, 2680 //@} 2681 2682 /// \name i686 2683 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2684 //@{ 2685 CK_i686, 2686 CK_PentiumPro, 2687 CK_Pentium2, 2688 CK_Pentium3, 2689 CK_Pentium3M, 2690 CK_PentiumM, 2691 CK_C3_2, 2692 2693 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2694 /// Clang however has some logic to suport this. 2695 // FIXME: Warn, deprecate, and potentially remove this. 2696 CK_Yonah, 2697 //@} 2698 2699 /// \name Netburst 2700 /// Netburst microarchitecture based processors. 2701 //@{ 2702 CK_Pentium4, 2703 CK_Pentium4M, 2704 CK_Prescott, 2705 CK_Nocona, 2706 //@} 2707 2708 /// \name Core 2709 /// Core microarchitecture based processors. 2710 //@{ 2711 CK_Core2, 2712 2713 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2714 /// codename which GCC no longer accepts as an option to -march, but Clang 2715 /// has some logic for recognizing it. 2716 // FIXME: Warn, deprecate, and potentially remove this. 2717 CK_Penryn, 2718 //@} 2719 2720 /// \name Atom 2721 /// Atom processors 2722 //@{ 2723 CK_Bonnell, 2724 CK_Silvermont, 2725 //@} 2726 2727 /// \name Nehalem 2728 /// Nehalem microarchitecture based processors. 2729 CK_Nehalem, 2730 2731 /// \name Westmere 2732 /// Westmere microarchitecture based processors. 2733 CK_Westmere, 2734 2735 /// \name Sandy Bridge 2736 /// Sandy Bridge microarchitecture based processors. 2737 CK_SandyBridge, 2738 2739 /// \name Ivy Bridge 2740 /// Ivy Bridge microarchitecture based processors. 2741 CK_IvyBridge, 2742 2743 /// \name Haswell 2744 /// Haswell microarchitecture based processors. 2745 CK_Haswell, 2746 2747 /// \name Broadwell 2748 /// Broadwell microarchitecture based processors. 2749 CK_Broadwell, 2750 2751 /// \name Skylake Client 2752 /// Skylake client microarchitecture based processors. 2753 CK_SkylakeClient, 2754 2755 /// \name Skylake Server 2756 /// Skylake server microarchitecture based processors. 2757 CK_SkylakeServer, 2758 2759 /// \name Cannonlake Client 2760 /// Cannonlake client microarchitecture based processors. 2761 CK_Cannonlake, 2762 2763 /// \name Knights Landing 2764 /// Knights Landing processor. 2765 CK_KNL, 2766 2767 /// \name Lakemont 2768 /// Lakemont microarchitecture based processors. 2769 CK_Lakemont, 2770 2771 /// \name K6 2772 /// K6 architecture processors. 2773 //@{ 2774 CK_K6, 2775 CK_K6_2, 2776 CK_K6_3, 2777 //@} 2778 2779 /// \name K7 2780 /// K7 architecture processors. 2781 //@{ 2782 CK_Athlon, 2783 CK_AthlonThunderbird, 2784 CK_Athlon4, 2785 CK_AthlonXP, 2786 CK_AthlonMP, 2787 //@} 2788 2789 /// \name K8 2790 /// K8 architecture processors. 2791 //@{ 2792 CK_Athlon64, 2793 CK_Athlon64SSE3, 2794 CK_AthlonFX, 2795 CK_K8, 2796 CK_K8SSE3, 2797 CK_Opteron, 2798 CK_OpteronSSE3, 2799 CK_AMDFAM10, 2800 //@} 2801 2802 /// \name Bobcat 2803 /// Bobcat architecture processors. 2804 //@{ 2805 CK_BTVER1, 2806 CK_BTVER2, 2807 //@} 2808 2809 /// \name Bulldozer 2810 /// Bulldozer architecture processors. 2811 //@{ 2812 CK_BDVER1, 2813 CK_BDVER2, 2814 CK_BDVER3, 2815 CK_BDVER4, 2816 //@} 2817 2818 /// \name zen 2819 /// Zen architecture processors. 2820 //@{ 2821 CK_ZNVER1, 2822 //@} 2823 2824 /// This specification is deprecated and will be removed in the future. 2825 /// Users should prefer \see CK_K8. 2826 // FIXME: Warn on this when the CPU is set to it. 2827 //@{ 2828 CK_x86_64, 2829 //@} 2830 2831 /// \name Geode 2832 /// Geode processors. 2833 //@{ 2834 CK_Geode 2835 //@} 2836 } CPU = CK_Generic; 2837 2838 CPUKind getCPUKind(StringRef CPU) const { 2839 return llvm::StringSwitch<CPUKind>(CPU) 2840 .Case("i386", CK_i386) 2841 .Case("i486", CK_i486) 2842 .Case("winchip-c6", CK_WinChipC6) 2843 .Case("winchip2", CK_WinChip2) 2844 .Case("c3", CK_C3) 2845 .Case("i586", CK_i586) 2846 .Case("pentium", CK_Pentium) 2847 .Case("pentium-mmx", CK_PentiumMMX) 2848 .Case("i686", CK_i686) 2849 .Case("pentiumpro", CK_PentiumPro) 2850 .Case("pentium2", CK_Pentium2) 2851 .Case("pentium3", CK_Pentium3) 2852 .Case("pentium3m", CK_Pentium3M) 2853 .Case("pentium-m", CK_PentiumM) 2854 .Case("c3-2", CK_C3_2) 2855 .Case("yonah", CK_Yonah) 2856 .Case("pentium4", CK_Pentium4) 2857 .Case("pentium4m", CK_Pentium4M) 2858 .Case("prescott", CK_Prescott) 2859 .Case("nocona", CK_Nocona) 2860 .Case("core2", CK_Core2) 2861 .Case("penryn", CK_Penryn) 2862 .Case("bonnell", CK_Bonnell) 2863 .Case("atom", CK_Bonnell) // Legacy name. 2864 .Case("silvermont", CK_Silvermont) 2865 .Case("slm", CK_Silvermont) // Legacy name. 2866 .Case("nehalem", CK_Nehalem) 2867 .Case("corei7", CK_Nehalem) // Legacy name. 2868 .Case("westmere", CK_Westmere) 2869 .Case("sandybridge", CK_SandyBridge) 2870 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2871 .Case("ivybridge", CK_IvyBridge) 2872 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2873 .Case("haswell", CK_Haswell) 2874 .Case("core-avx2", CK_Haswell) // Legacy name. 2875 .Case("broadwell", CK_Broadwell) 2876 .Case("skylake", CK_SkylakeClient) 2877 .Case("skylake-avx512", CK_SkylakeServer) 2878 .Case("skx", CK_SkylakeServer) // Legacy name. 2879 .Case("cannonlake", CK_Cannonlake) 2880 .Case("knl", CK_KNL) 2881 .Case("lakemont", CK_Lakemont) 2882 .Case("k6", CK_K6) 2883 .Case("k6-2", CK_K6_2) 2884 .Case("k6-3", CK_K6_3) 2885 .Case("athlon", CK_Athlon) 2886 .Case("athlon-tbird", CK_AthlonThunderbird) 2887 .Case("athlon-4", CK_Athlon4) 2888 .Case("athlon-xp", CK_AthlonXP) 2889 .Case("athlon-mp", CK_AthlonMP) 2890 .Case("athlon64", CK_Athlon64) 2891 .Case("athlon64-sse3", CK_Athlon64SSE3) 2892 .Case("athlon-fx", CK_AthlonFX) 2893 .Case("k8", CK_K8) 2894 .Case("k8-sse3", CK_K8SSE3) 2895 .Case("opteron", CK_Opteron) 2896 .Case("opteron-sse3", CK_OpteronSSE3) 2897 .Case("barcelona", CK_AMDFAM10) 2898 .Case("amdfam10", CK_AMDFAM10) 2899 .Case("btver1", CK_BTVER1) 2900 .Case("btver2", CK_BTVER2) 2901 .Case("bdver1", CK_BDVER1) 2902 .Case("bdver2", CK_BDVER2) 2903 .Case("bdver3", CK_BDVER3) 2904 .Case("bdver4", CK_BDVER4) 2905 .Case("znver1", CK_ZNVER1) 2906 .Case("x86-64", CK_x86_64) 2907 .Case("geode", CK_Geode) 2908 .Default(CK_Generic); 2909 } 2910 2911 enum FPMathKind { 2912 FP_Default, 2913 FP_SSE, 2914 FP_387 2915 } FPMath = FP_Default; 2916 2917 public: 2918 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2919 : TargetInfo(Triple) { 2920 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2921 } 2922 unsigned getFloatEvalMethod() const override { 2923 // X87 evaluates with 80 bits "long double" precision. 2924 return SSELevel == NoSSE ? 2 : 0; 2925 } 2926 ArrayRef<const char *> getGCCRegNames() const override { 2927 return llvm::makeArrayRef(GCCRegNames); 2928 } 2929 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2930 return None; 2931 } 2932 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2933 return llvm::makeArrayRef(AddlRegNames); 2934 } 2935 bool validateCpuSupports(StringRef Name) const override; 2936 bool validateAsmConstraint(const char *&Name, 2937 TargetInfo::ConstraintInfo &info) const override; 2938 2939 bool validateGlobalRegisterVariable(StringRef RegName, 2940 unsigned RegSize, 2941 bool &HasSizeMismatch) const override { 2942 // esp and ebp are the only 32-bit registers the x86 backend can currently 2943 // handle. 2944 if (RegName.equals("esp") || RegName.equals("ebp")) { 2945 // Check that the register size is 32-bit. 2946 HasSizeMismatch = RegSize != 32; 2947 return true; 2948 } 2949 2950 return false; 2951 } 2952 2953 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2954 2955 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2956 2957 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2958 2959 std::string convertConstraint(const char *&Constraint) const override; 2960 const char *getClobbers() const override { 2961 return "~{dirflag},~{fpsr},~{flags}"; 2962 } 2963 2964 StringRef getConstraintRegister(const StringRef &Constraint, 2965 const StringRef &Expression) const override { 2966 StringRef::iterator I, E; 2967 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2968 if (isalpha(*I)) 2969 break; 2970 } 2971 if (I == E) 2972 return ""; 2973 switch (*I) { 2974 // For the register constraints, return the matching register name 2975 case 'a': 2976 return "ax"; 2977 case 'b': 2978 return "bx"; 2979 case 'c': 2980 return "cx"; 2981 case 'd': 2982 return "dx"; 2983 case 'S': 2984 return "si"; 2985 case 'D': 2986 return "di"; 2987 // In case the constraint is 'r' we need to return Expression 2988 case 'r': 2989 return Expression; 2990 default: 2991 // Default value if there is no constraint for the register 2992 return ""; 2993 } 2994 return ""; 2995 } 2996 2997 void getTargetDefines(const LangOptions &Opts, 2998 MacroBuilder &Builder) const override; 2999 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3000 bool Enabled); 3001 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3002 bool Enabled); 3003 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3004 bool Enabled); 3005 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3006 StringRef Name, bool Enabled) const override { 3007 setFeatureEnabledImpl(Features, Name, Enabled); 3008 } 3009 // This exists purely to cut down on the number of virtual calls in 3010 // initFeatureMap which calls this repeatedly. 3011 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3012 StringRef Name, bool Enabled); 3013 bool 3014 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3015 StringRef CPU, 3016 const std::vector<std::string> &FeaturesVec) const override; 3017 bool hasFeature(StringRef Feature) const override; 3018 bool handleTargetFeatures(std::vector<std::string> &Features, 3019 DiagnosticsEngine &Diags) override; 3020 StringRef getABI() const override { 3021 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3022 return "avx512"; 3023 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3024 return "avx"; 3025 if (getTriple().getArch() == llvm::Triple::x86 && 3026 MMX3DNowLevel == NoMMX3DNow) 3027 return "no-mmx"; 3028 return ""; 3029 } 3030 bool setCPU(const std::string &Name) override { 3031 CPU = getCPUKind(Name); 3032 3033 // Perform any per-CPU checks necessary to determine if this CPU is 3034 // acceptable. 3035 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3036 // invalid without explaining *why*. 3037 switch (CPU) { 3038 case CK_Generic: 3039 // No processor selected! 3040 return false; 3041 3042 case CK_i386: 3043 case CK_i486: 3044 case CK_WinChipC6: 3045 case CK_WinChip2: 3046 case CK_C3: 3047 case CK_i586: 3048 case CK_Pentium: 3049 case CK_PentiumMMX: 3050 case CK_i686: 3051 case CK_PentiumPro: 3052 case CK_Pentium2: 3053 case CK_Pentium3: 3054 case CK_Pentium3M: 3055 case CK_PentiumM: 3056 case CK_Yonah: 3057 case CK_C3_2: 3058 case CK_Pentium4: 3059 case CK_Pentium4M: 3060 case CK_Lakemont: 3061 case CK_Prescott: 3062 case CK_K6: 3063 case CK_K6_2: 3064 case CK_K6_3: 3065 case CK_Athlon: 3066 case CK_AthlonThunderbird: 3067 case CK_Athlon4: 3068 case CK_AthlonXP: 3069 case CK_AthlonMP: 3070 case CK_Geode: 3071 // Only accept certain architectures when compiling in 32-bit mode. 3072 if (getTriple().getArch() != llvm::Triple::x86) 3073 return false; 3074 3075 // Fallthrough 3076 case CK_Nocona: 3077 case CK_Core2: 3078 case CK_Penryn: 3079 case CK_Bonnell: 3080 case CK_Silvermont: 3081 case CK_Nehalem: 3082 case CK_Westmere: 3083 case CK_SandyBridge: 3084 case CK_IvyBridge: 3085 case CK_Haswell: 3086 case CK_Broadwell: 3087 case CK_SkylakeClient: 3088 case CK_SkylakeServer: 3089 case CK_Cannonlake: 3090 case CK_KNL: 3091 case CK_Athlon64: 3092 case CK_Athlon64SSE3: 3093 case CK_AthlonFX: 3094 case CK_K8: 3095 case CK_K8SSE3: 3096 case CK_Opteron: 3097 case CK_OpteronSSE3: 3098 case CK_AMDFAM10: 3099 case CK_BTVER1: 3100 case CK_BTVER2: 3101 case CK_BDVER1: 3102 case CK_BDVER2: 3103 case CK_BDVER3: 3104 case CK_BDVER4: 3105 case CK_ZNVER1: 3106 case CK_x86_64: 3107 return true; 3108 } 3109 llvm_unreachable("Unhandled CPU kind"); 3110 } 3111 3112 bool setFPMath(StringRef Name) override; 3113 3114 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3115 // Most of the non-ARM calling conventions are i386 conventions. 3116 switch (CC) { 3117 case CC_X86ThisCall: 3118 case CC_X86FastCall: 3119 case CC_X86StdCall: 3120 case CC_X86VectorCall: 3121 case CC_X86RegCall: 3122 case CC_C: 3123 case CC_Swift: 3124 case CC_X86Pascal: 3125 case CC_IntelOclBicc: 3126 case CC_OpenCLKernel: 3127 return CCCR_OK; 3128 default: 3129 return CCCR_Warning; 3130 } 3131 } 3132 3133 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3134 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3135 } 3136 3137 bool hasSjLjLowering() const override { 3138 return true; 3139 } 3140 3141 void setSupportedOpenCLOpts() override { 3142 getSupportedOpenCLOpts().supportAll(); 3143 } 3144 }; 3145 3146 bool X86TargetInfo::setFPMath(StringRef Name) { 3147 if (Name == "387") { 3148 FPMath = FP_387; 3149 return true; 3150 } 3151 if (Name == "sse") { 3152 FPMath = FP_SSE; 3153 return true; 3154 } 3155 return false; 3156 } 3157 3158 bool X86TargetInfo::initFeatureMap( 3159 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3160 const std::vector<std::string> &FeaturesVec) const { 3161 // FIXME: This *really* should not be here. 3162 // X86_64 always has SSE2. 3163 if (getTriple().getArch() == llvm::Triple::x86_64) 3164 setFeatureEnabledImpl(Features, "sse2", true); 3165 3166 const CPUKind Kind = getCPUKind(CPU); 3167 3168 // Enable X87 for all X86 processors but Lakemont. 3169 if (Kind != CK_Lakemont) 3170 setFeatureEnabledImpl(Features, "x87", true); 3171 3172 switch (Kind) { 3173 case CK_Generic: 3174 case CK_i386: 3175 case CK_i486: 3176 case CK_i586: 3177 case CK_Pentium: 3178 case CK_i686: 3179 case CK_PentiumPro: 3180 case CK_Lakemont: 3181 break; 3182 case CK_PentiumMMX: 3183 case CK_Pentium2: 3184 case CK_K6: 3185 case CK_WinChipC6: 3186 setFeatureEnabledImpl(Features, "mmx", true); 3187 break; 3188 case CK_Pentium3: 3189 case CK_Pentium3M: 3190 case CK_C3_2: 3191 setFeatureEnabledImpl(Features, "sse", true); 3192 setFeatureEnabledImpl(Features, "fxsr", true); 3193 break; 3194 case CK_PentiumM: 3195 case CK_Pentium4: 3196 case CK_Pentium4M: 3197 case CK_x86_64: 3198 setFeatureEnabledImpl(Features, "sse2", true); 3199 setFeatureEnabledImpl(Features, "fxsr", true); 3200 break; 3201 case CK_Yonah: 3202 case CK_Prescott: 3203 case CK_Nocona: 3204 setFeatureEnabledImpl(Features, "sse3", true); 3205 setFeatureEnabledImpl(Features, "fxsr", true); 3206 setFeatureEnabledImpl(Features, "cx16", true); 3207 break; 3208 case CK_Core2: 3209 case CK_Bonnell: 3210 setFeatureEnabledImpl(Features, "ssse3", true); 3211 setFeatureEnabledImpl(Features, "fxsr", true); 3212 setFeatureEnabledImpl(Features, "cx16", true); 3213 break; 3214 case CK_Penryn: 3215 setFeatureEnabledImpl(Features, "sse4.1", true); 3216 setFeatureEnabledImpl(Features, "fxsr", true); 3217 setFeatureEnabledImpl(Features, "cx16", true); 3218 break; 3219 case CK_Cannonlake: 3220 setFeatureEnabledImpl(Features, "avx512ifma", true); 3221 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3222 setFeatureEnabledImpl(Features, "sha", true); 3223 LLVM_FALLTHROUGH; 3224 case CK_SkylakeServer: 3225 setFeatureEnabledImpl(Features, "avx512f", true); 3226 setFeatureEnabledImpl(Features, "avx512cd", true); 3227 setFeatureEnabledImpl(Features, "avx512dq", true); 3228 setFeatureEnabledImpl(Features, "avx512bw", true); 3229 setFeatureEnabledImpl(Features, "avx512vl", true); 3230 setFeatureEnabledImpl(Features, "pku", true); 3231 setFeatureEnabledImpl(Features, "clwb", true); 3232 LLVM_FALLTHROUGH; 3233 case CK_SkylakeClient: 3234 setFeatureEnabledImpl(Features, "xsavec", true); 3235 setFeatureEnabledImpl(Features, "xsaves", true); 3236 setFeatureEnabledImpl(Features, "mpx", true); 3237 setFeatureEnabledImpl(Features, "sgx", true); 3238 setFeatureEnabledImpl(Features, "clflushopt", true); 3239 setFeatureEnabledImpl(Features, "rtm", true); 3240 LLVM_FALLTHROUGH; 3241 case CK_Broadwell: 3242 setFeatureEnabledImpl(Features, "rdseed", true); 3243 setFeatureEnabledImpl(Features, "adx", true); 3244 LLVM_FALLTHROUGH; 3245 case CK_Haswell: 3246 setFeatureEnabledImpl(Features, "avx2", true); 3247 setFeatureEnabledImpl(Features, "lzcnt", true); 3248 setFeatureEnabledImpl(Features, "bmi", true); 3249 setFeatureEnabledImpl(Features, "bmi2", true); 3250 setFeatureEnabledImpl(Features, "fma", true); 3251 setFeatureEnabledImpl(Features, "movbe", true); 3252 LLVM_FALLTHROUGH; 3253 case CK_IvyBridge: 3254 setFeatureEnabledImpl(Features, "rdrnd", true); 3255 setFeatureEnabledImpl(Features, "f16c", true); 3256 setFeatureEnabledImpl(Features, "fsgsbase", true); 3257 LLVM_FALLTHROUGH; 3258 case CK_SandyBridge: 3259 setFeatureEnabledImpl(Features, "avx", true); 3260 setFeatureEnabledImpl(Features, "xsave", true); 3261 setFeatureEnabledImpl(Features, "xsaveopt", true); 3262 LLVM_FALLTHROUGH; 3263 case CK_Westmere: 3264 case CK_Silvermont: 3265 setFeatureEnabledImpl(Features, "aes", true); 3266 setFeatureEnabledImpl(Features, "pclmul", true); 3267 LLVM_FALLTHROUGH; 3268 case CK_Nehalem: 3269 setFeatureEnabledImpl(Features, "sse4.2", true); 3270 setFeatureEnabledImpl(Features, "fxsr", true); 3271 setFeatureEnabledImpl(Features, "cx16", true); 3272 break; 3273 case CK_KNL: 3274 setFeatureEnabledImpl(Features, "avx512f", true); 3275 setFeatureEnabledImpl(Features, "avx512cd", true); 3276 setFeatureEnabledImpl(Features, "avx512er", true); 3277 setFeatureEnabledImpl(Features, "avx512pf", true); 3278 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3279 setFeatureEnabledImpl(Features, "fxsr", true); 3280 setFeatureEnabledImpl(Features, "rdseed", true); 3281 setFeatureEnabledImpl(Features, "adx", true); 3282 setFeatureEnabledImpl(Features, "lzcnt", true); 3283 setFeatureEnabledImpl(Features, "bmi", true); 3284 setFeatureEnabledImpl(Features, "bmi2", true); 3285 setFeatureEnabledImpl(Features, "rtm", true); 3286 setFeatureEnabledImpl(Features, "fma", true); 3287 setFeatureEnabledImpl(Features, "rdrnd", true); 3288 setFeatureEnabledImpl(Features, "f16c", true); 3289 setFeatureEnabledImpl(Features, "fsgsbase", true); 3290 setFeatureEnabledImpl(Features, "aes", true); 3291 setFeatureEnabledImpl(Features, "pclmul", true); 3292 setFeatureEnabledImpl(Features, "cx16", true); 3293 setFeatureEnabledImpl(Features, "xsaveopt", true); 3294 setFeatureEnabledImpl(Features, "xsave", true); 3295 setFeatureEnabledImpl(Features, "movbe", true); 3296 break; 3297 case CK_K6_2: 3298 case CK_K6_3: 3299 case CK_WinChip2: 3300 case CK_C3: 3301 setFeatureEnabledImpl(Features, "3dnow", true); 3302 break; 3303 case CK_Athlon: 3304 case CK_AthlonThunderbird: 3305 case CK_Geode: 3306 setFeatureEnabledImpl(Features, "3dnowa", true); 3307 break; 3308 case CK_Athlon4: 3309 case CK_AthlonXP: 3310 case CK_AthlonMP: 3311 setFeatureEnabledImpl(Features, "sse", true); 3312 setFeatureEnabledImpl(Features, "3dnowa", true); 3313 setFeatureEnabledImpl(Features, "fxsr", true); 3314 break; 3315 case CK_K8: 3316 case CK_Opteron: 3317 case CK_Athlon64: 3318 case CK_AthlonFX: 3319 setFeatureEnabledImpl(Features, "sse2", true); 3320 setFeatureEnabledImpl(Features, "3dnowa", true); 3321 setFeatureEnabledImpl(Features, "fxsr", true); 3322 break; 3323 case CK_AMDFAM10: 3324 setFeatureEnabledImpl(Features, "sse4a", true); 3325 setFeatureEnabledImpl(Features, "lzcnt", true); 3326 setFeatureEnabledImpl(Features, "popcnt", true); 3327 LLVM_FALLTHROUGH; 3328 case CK_K8SSE3: 3329 case CK_OpteronSSE3: 3330 case CK_Athlon64SSE3: 3331 setFeatureEnabledImpl(Features, "sse3", true); 3332 setFeatureEnabledImpl(Features, "3dnowa", true); 3333 setFeatureEnabledImpl(Features, "fxsr", true); 3334 break; 3335 case CK_BTVER2: 3336 setFeatureEnabledImpl(Features, "avx", true); 3337 setFeatureEnabledImpl(Features, "aes", true); 3338 setFeatureEnabledImpl(Features, "pclmul", true); 3339 setFeatureEnabledImpl(Features, "bmi", true); 3340 setFeatureEnabledImpl(Features, "f16c", true); 3341 setFeatureEnabledImpl(Features, "xsaveopt", true); 3342 LLVM_FALLTHROUGH; 3343 case CK_BTVER1: 3344 setFeatureEnabledImpl(Features, "ssse3", true); 3345 setFeatureEnabledImpl(Features, "sse4a", true); 3346 setFeatureEnabledImpl(Features, "lzcnt", true); 3347 setFeatureEnabledImpl(Features, "popcnt", true); 3348 setFeatureEnabledImpl(Features, "prfchw", true); 3349 setFeatureEnabledImpl(Features, "cx16", true); 3350 setFeatureEnabledImpl(Features, "fxsr", true); 3351 break; 3352 case CK_ZNVER1: 3353 setFeatureEnabledImpl(Features, "adx", true); 3354 setFeatureEnabledImpl(Features, "aes", true); 3355 setFeatureEnabledImpl(Features, "avx2", true); 3356 setFeatureEnabledImpl(Features, "bmi", true); 3357 setFeatureEnabledImpl(Features, "bmi2", true); 3358 setFeatureEnabledImpl(Features, "clflushopt", true); 3359 setFeatureEnabledImpl(Features, "clzero", true); 3360 setFeatureEnabledImpl(Features, "cx16", true); 3361 setFeatureEnabledImpl(Features, "f16c", true); 3362 setFeatureEnabledImpl(Features, "fma", true); 3363 setFeatureEnabledImpl(Features, "fsgsbase", true); 3364 setFeatureEnabledImpl(Features, "fxsr", true); 3365 setFeatureEnabledImpl(Features, "lzcnt", true); 3366 setFeatureEnabledImpl(Features, "mwaitx", true); 3367 setFeatureEnabledImpl(Features, "movbe", true); 3368 setFeatureEnabledImpl(Features, "pclmul", true); 3369 setFeatureEnabledImpl(Features, "popcnt", true); 3370 setFeatureEnabledImpl(Features, "prfchw", true); 3371 setFeatureEnabledImpl(Features, "rdrnd", true); 3372 setFeatureEnabledImpl(Features, "rdseed", true); 3373 setFeatureEnabledImpl(Features, "sha", true); 3374 setFeatureEnabledImpl(Features, "sse4a", true); 3375 setFeatureEnabledImpl(Features, "xsave", true); 3376 setFeatureEnabledImpl(Features, "xsavec", true); 3377 setFeatureEnabledImpl(Features, "xsaveopt", true); 3378 setFeatureEnabledImpl(Features, "xsaves", true); 3379 break; 3380 case CK_BDVER4: 3381 setFeatureEnabledImpl(Features, "avx2", true); 3382 setFeatureEnabledImpl(Features, "bmi2", true); 3383 setFeatureEnabledImpl(Features, "mwaitx", true); 3384 LLVM_FALLTHROUGH; 3385 case CK_BDVER3: 3386 setFeatureEnabledImpl(Features, "fsgsbase", true); 3387 setFeatureEnabledImpl(Features, "xsaveopt", true); 3388 LLVM_FALLTHROUGH; 3389 case CK_BDVER2: 3390 setFeatureEnabledImpl(Features, "bmi", true); 3391 setFeatureEnabledImpl(Features, "fma", true); 3392 setFeatureEnabledImpl(Features, "f16c", true); 3393 setFeatureEnabledImpl(Features, "tbm", true); 3394 LLVM_FALLTHROUGH; 3395 case CK_BDVER1: 3396 // xop implies avx, sse4a and fma4. 3397 setFeatureEnabledImpl(Features, "xop", true); 3398 setFeatureEnabledImpl(Features, "lwp", true); 3399 setFeatureEnabledImpl(Features, "lzcnt", true); 3400 setFeatureEnabledImpl(Features, "aes", true); 3401 setFeatureEnabledImpl(Features, "pclmul", true); 3402 setFeatureEnabledImpl(Features, "prfchw", true); 3403 setFeatureEnabledImpl(Features, "cx16", true); 3404 setFeatureEnabledImpl(Features, "fxsr", true); 3405 setFeatureEnabledImpl(Features, "xsave", true); 3406 break; 3407 } 3408 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3409 return false; 3410 3411 // Can't do this earlier because we need to be able to explicitly enable 3412 // or disable these features and the things that they depend upon. 3413 3414 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3415 auto I = Features.find("sse4.2"); 3416 if (I != Features.end() && I->getValue() && 3417 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3418 FeaturesVec.end()) 3419 Features["popcnt"] = true; 3420 3421 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3422 I = Features.find("3dnow"); 3423 if (I != Features.end() && I->getValue() && 3424 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3425 FeaturesVec.end()) 3426 Features["prfchw"] = true; 3427 3428 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3429 // then enable MMX. 3430 I = Features.find("sse"); 3431 if (I != Features.end() && I->getValue() && 3432 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3433 FeaturesVec.end()) 3434 Features["mmx"] = true; 3435 3436 return true; 3437 } 3438 3439 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3440 X86SSEEnum Level, bool Enabled) { 3441 if (Enabled) { 3442 switch (Level) { 3443 case AVX512F: 3444 Features["avx512f"] = true; 3445 LLVM_FALLTHROUGH; 3446 case AVX2: 3447 Features["avx2"] = true; 3448 LLVM_FALLTHROUGH; 3449 case AVX: 3450 Features["avx"] = true; 3451 Features["xsave"] = true; 3452 LLVM_FALLTHROUGH; 3453 case SSE42: 3454 Features["sse4.2"] = true; 3455 LLVM_FALLTHROUGH; 3456 case SSE41: 3457 Features["sse4.1"] = true; 3458 LLVM_FALLTHROUGH; 3459 case SSSE3: 3460 Features["ssse3"] = true; 3461 LLVM_FALLTHROUGH; 3462 case SSE3: 3463 Features["sse3"] = true; 3464 LLVM_FALLTHROUGH; 3465 case SSE2: 3466 Features["sse2"] = true; 3467 LLVM_FALLTHROUGH; 3468 case SSE1: 3469 Features["sse"] = true; 3470 LLVM_FALLTHROUGH; 3471 case NoSSE: 3472 break; 3473 } 3474 return; 3475 } 3476 3477 switch (Level) { 3478 case NoSSE: 3479 case SSE1: 3480 Features["sse"] = false; 3481 LLVM_FALLTHROUGH; 3482 case SSE2: 3483 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3484 Features["sha"] = false; 3485 LLVM_FALLTHROUGH; 3486 case SSE3: 3487 Features["sse3"] = false; 3488 setXOPLevel(Features, NoXOP, false); 3489 LLVM_FALLTHROUGH; 3490 case SSSE3: 3491 Features["ssse3"] = false; 3492 LLVM_FALLTHROUGH; 3493 case SSE41: 3494 Features["sse4.1"] = false; 3495 LLVM_FALLTHROUGH; 3496 case SSE42: 3497 Features["sse4.2"] = false; 3498 LLVM_FALLTHROUGH; 3499 case AVX: 3500 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3501 Features["xsaveopt"] = false; 3502 setXOPLevel(Features, FMA4, false); 3503 LLVM_FALLTHROUGH; 3504 case AVX2: 3505 Features["avx2"] = false; 3506 LLVM_FALLTHROUGH; 3507 case AVX512F: 3508 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3509 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3510 Features["avx512vl"] = Features["avx512vbmi"] = 3511 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3512 } 3513 } 3514 3515 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3516 MMX3DNowEnum Level, bool Enabled) { 3517 if (Enabled) { 3518 switch (Level) { 3519 case AMD3DNowAthlon: 3520 Features["3dnowa"] = true; 3521 LLVM_FALLTHROUGH; 3522 case AMD3DNow: 3523 Features["3dnow"] = true; 3524 LLVM_FALLTHROUGH; 3525 case MMX: 3526 Features["mmx"] = true; 3527 LLVM_FALLTHROUGH; 3528 case NoMMX3DNow: 3529 break; 3530 } 3531 return; 3532 } 3533 3534 switch (Level) { 3535 case NoMMX3DNow: 3536 case MMX: 3537 Features["mmx"] = false; 3538 LLVM_FALLTHROUGH; 3539 case AMD3DNow: 3540 Features["3dnow"] = false; 3541 LLVM_FALLTHROUGH; 3542 case AMD3DNowAthlon: 3543 Features["3dnowa"] = false; 3544 } 3545 } 3546 3547 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3548 bool Enabled) { 3549 if (Enabled) { 3550 switch (Level) { 3551 case XOP: 3552 Features["xop"] = true; 3553 LLVM_FALLTHROUGH; 3554 case FMA4: 3555 Features["fma4"] = true; 3556 setSSELevel(Features, AVX, true); 3557 LLVM_FALLTHROUGH; 3558 case SSE4A: 3559 Features["sse4a"] = true; 3560 setSSELevel(Features, SSE3, true); 3561 LLVM_FALLTHROUGH; 3562 case NoXOP: 3563 break; 3564 } 3565 return; 3566 } 3567 3568 switch (Level) { 3569 case NoXOP: 3570 case SSE4A: 3571 Features["sse4a"] = false; 3572 LLVM_FALLTHROUGH; 3573 case FMA4: 3574 Features["fma4"] = false; 3575 LLVM_FALLTHROUGH; 3576 case XOP: 3577 Features["xop"] = false; 3578 } 3579 } 3580 3581 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3582 StringRef Name, bool Enabled) { 3583 // This is a bit of a hack to deal with the sse4 target feature when used 3584 // as part of the target attribute. We handle sse4 correctly everywhere 3585 // else. See below for more information on how we handle the sse4 options. 3586 if (Name != "sse4") 3587 Features[Name] = Enabled; 3588 3589 if (Name == "mmx") { 3590 setMMXLevel(Features, MMX, Enabled); 3591 } else if (Name == "sse") { 3592 setSSELevel(Features, SSE1, Enabled); 3593 } else if (Name == "sse2") { 3594 setSSELevel(Features, SSE2, Enabled); 3595 } else if (Name == "sse3") { 3596 setSSELevel(Features, SSE3, Enabled); 3597 } else if (Name == "ssse3") { 3598 setSSELevel(Features, SSSE3, Enabled); 3599 } else if (Name == "sse4.2") { 3600 setSSELevel(Features, SSE42, Enabled); 3601 } else if (Name == "sse4.1") { 3602 setSSELevel(Features, SSE41, Enabled); 3603 } else if (Name == "3dnow") { 3604 setMMXLevel(Features, AMD3DNow, Enabled); 3605 } else if (Name == "3dnowa") { 3606 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3607 } else if (Name == "aes") { 3608 if (Enabled) 3609 setSSELevel(Features, SSE2, Enabled); 3610 } else if (Name == "pclmul") { 3611 if (Enabled) 3612 setSSELevel(Features, SSE2, Enabled); 3613 } else if (Name == "avx") { 3614 setSSELevel(Features, AVX, Enabled); 3615 } else if (Name == "avx2") { 3616 setSSELevel(Features, AVX2, Enabled); 3617 } else if (Name == "avx512f") { 3618 setSSELevel(Features, AVX512F, Enabled); 3619 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3620 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3621 Name == "avx512vbmi" || Name == "avx512ifma" || 3622 Name == "avx512vpopcntdq") { 3623 if (Enabled) 3624 setSSELevel(Features, AVX512F, Enabled); 3625 // Enable BWI instruction if VBMI is being enabled. 3626 if (Name == "avx512vbmi" && Enabled) 3627 Features["avx512bw"] = true; 3628 // Also disable VBMI if BWI is being disabled. 3629 if (Name == "avx512bw" && !Enabled) 3630 Features["avx512vbmi"] = false; 3631 } else if (Name == "fma") { 3632 if (Enabled) 3633 setSSELevel(Features, AVX, Enabled); 3634 } else if (Name == "fma4") { 3635 setXOPLevel(Features, FMA4, Enabled); 3636 } else if (Name == "xop") { 3637 setXOPLevel(Features, XOP, Enabled); 3638 } else if (Name == "sse4a") { 3639 setXOPLevel(Features, SSE4A, Enabled); 3640 } else if (Name == "f16c") { 3641 if (Enabled) 3642 setSSELevel(Features, AVX, Enabled); 3643 } else if (Name == "sha") { 3644 if (Enabled) 3645 setSSELevel(Features, SSE2, Enabled); 3646 } else if (Name == "sse4") { 3647 // We can get here via the __target__ attribute since that's not controlled 3648 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3649 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3650 // disabled. 3651 if (Enabled) 3652 setSSELevel(Features, SSE42, Enabled); 3653 else 3654 setSSELevel(Features, SSE41, Enabled); 3655 } else if (Name == "xsave") { 3656 if (!Enabled) 3657 Features["xsaveopt"] = false; 3658 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3659 if (Enabled) 3660 Features["xsave"] = true; 3661 } 3662 } 3663 3664 /// handleTargetFeatures - Perform initialization based on the user 3665 /// configured set of features. 3666 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3667 DiagnosticsEngine &Diags) { 3668 for (const auto &Feature : Features) { 3669 if (Feature[0] != '+') 3670 continue; 3671 3672 if (Feature == "+aes") { 3673 HasAES = true; 3674 } else if (Feature == "+pclmul") { 3675 HasPCLMUL = true; 3676 } else if (Feature == "+lzcnt") { 3677 HasLZCNT = true; 3678 } else if (Feature == "+rdrnd") { 3679 HasRDRND = true; 3680 } else if (Feature == "+fsgsbase") { 3681 HasFSGSBASE = true; 3682 } else if (Feature == "+bmi") { 3683 HasBMI = true; 3684 } else if (Feature == "+bmi2") { 3685 HasBMI2 = true; 3686 } else if (Feature == "+popcnt") { 3687 HasPOPCNT = true; 3688 } else if (Feature == "+rtm") { 3689 HasRTM = true; 3690 } else if (Feature == "+prfchw") { 3691 HasPRFCHW = true; 3692 } else if (Feature == "+rdseed") { 3693 HasRDSEED = true; 3694 } else if (Feature == "+adx") { 3695 HasADX = true; 3696 } else if (Feature == "+tbm") { 3697 HasTBM = true; 3698 } else if (Feature == "+lwp") { 3699 HasLWP = true; 3700 } else if (Feature == "+fma") { 3701 HasFMA = true; 3702 } else if (Feature == "+f16c") { 3703 HasF16C = true; 3704 } else if (Feature == "+avx512cd") { 3705 HasAVX512CD = true; 3706 } else if (Feature == "+avx512vpopcntdq") { 3707 HasAVX512VPOPCNTDQ = true; 3708 } else if (Feature == "+avx512er") { 3709 HasAVX512ER = true; 3710 } else if (Feature == "+avx512pf") { 3711 HasAVX512PF = true; 3712 } else if (Feature == "+avx512dq") { 3713 HasAVX512DQ = true; 3714 } else if (Feature == "+avx512bw") { 3715 HasAVX512BW = true; 3716 } else if (Feature == "+avx512vl") { 3717 HasAVX512VL = true; 3718 } else if (Feature == "+avx512vbmi") { 3719 HasAVX512VBMI = true; 3720 } else if (Feature == "+avx512ifma") { 3721 HasAVX512IFMA = true; 3722 } else if (Feature == "+sha") { 3723 HasSHA = true; 3724 } else if (Feature == "+mpx") { 3725 HasMPX = true; 3726 } else if (Feature == "+movbe") { 3727 HasMOVBE = true; 3728 } else if (Feature == "+sgx") { 3729 HasSGX = true; 3730 } else if (Feature == "+cx16") { 3731 HasCX16 = true; 3732 } else if (Feature == "+fxsr") { 3733 HasFXSR = true; 3734 } else if (Feature == "+xsave") { 3735 HasXSAVE = true; 3736 } else if (Feature == "+xsaveopt") { 3737 HasXSAVEOPT = true; 3738 } else if (Feature == "+xsavec") { 3739 HasXSAVEC = true; 3740 } else if (Feature == "+xsaves") { 3741 HasXSAVES = true; 3742 } else if (Feature == "+mwaitx") { 3743 HasMWAITX = true; 3744 } else if (Feature == "+pku") { 3745 HasPKU = true; 3746 } else if (Feature == "+clflushopt") { 3747 HasCLFLUSHOPT = true; 3748 } else if (Feature == "+clwb") { 3749 HasCLWB = true; 3750 } else if (Feature == "+prefetchwt1") { 3751 HasPREFETCHWT1 = true; 3752 } else if (Feature == "+clzero") { 3753 HasCLZERO = true; 3754 } 3755 3756 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3757 .Case("+avx512f", AVX512F) 3758 .Case("+avx2", AVX2) 3759 .Case("+avx", AVX) 3760 .Case("+sse4.2", SSE42) 3761 .Case("+sse4.1", SSE41) 3762 .Case("+ssse3", SSSE3) 3763 .Case("+sse3", SSE3) 3764 .Case("+sse2", SSE2) 3765 .Case("+sse", SSE1) 3766 .Default(NoSSE); 3767 SSELevel = std::max(SSELevel, Level); 3768 3769 MMX3DNowEnum ThreeDNowLevel = 3770 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3771 .Case("+3dnowa", AMD3DNowAthlon) 3772 .Case("+3dnow", AMD3DNow) 3773 .Case("+mmx", MMX) 3774 .Default(NoMMX3DNow); 3775 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3776 3777 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3778 .Case("+xop", XOP) 3779 .Case("+fma4", FMA4) 3780 .Case("+sse4a", SSE4A) 3781 .Default(NoXOP); 3782 XOPLevel = std::max(XOPLevel, XLevel); 3783 } 3784 3785 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3786 // matches the selected sse level. 3787 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3788 (FPMath == FP_387 && SSELevel >= SSE1)) { 3789 Diags.Report(diag::err_target_unsupported_fpmath) << 3790 (FPMath == FP_SSE ? "sse" : "387"); 3791 return false; 3792 } 3793 3794 SimdDefaultAlign = 3795 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3796 return true; 3797 } 3798 3799 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3800 /// definitions for this particular subtarget. 3801 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3802 MacroBuilder &Builder) const { 3803 // Target identification. 3804 if (getTriple().getArch() == llvm::Triple::x86_64) { 3805 Builder.defineMacro("__amd64__"); 3806 Builder.defineMacro("__amd64"); 3807 Builder.defineMacro("__x86_64"); 3808 Builder.defineMacro("__x86_64__"); 3809 if (getTriple().getArchName() == "x86_64h") { 3810 Builder.defineMacro("__x86_64h"); 3811 Builder.defineMacro("__x86_64h__"); 3812 } 3813 } else { 3814 DefineStd(Builder, "i386", Opts); 3815 } 3816 3817 // Subtarget options. 3818 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3819 // truly should be based on -mtune options. 3820 switch (CPU) { 3821 case CK_Generic: 3822 break; 3823 case CK_i386: 3824 // The rest are coming from the i386 define above. 3825 Builder.defineMacro("__tune_i386__"); 3826 break; 3827 case CK_i486: 3828 case CK_WinChipC6: 3829 case CK_WinChip2: 3830 case CK_C3: 3831 defineCPUMacros(Builder, "i486"); 3832 break; 3833 case CK_PentiumMMX: 3834 Builder.defineMacro("__pentium_mmx__"); 3835 Builder.defineMacro("__tune_pentium_mmx__"); 3836 // Fallthrough 3837 case CK_i586: 3838 case CK_Pentium: 3839 defineCPUMacros(Builder, "i586"); 3840 defineCPUMacros(Builder, "pentium"); 3841 break; 3842 case CK_Pentium3: 3843 case CK_Pentium3M: 3844 case CK_PentiumM: 3845 Builder.defineMacro("__tune_pentium3__"); 3846 // Fallthrough 3847 case CK_Pentium2: 3848 case CK_C3_2: 3849 Builder.defineMacro("__tune_pentium2__"); 3850 // Fallthrough 3851 case CK_PentiumPro: 3852 Builder.defineMacro("__tune_i686__"); 3853 Builder.defineMacro("__tune_pentiumpro__"); 3854 // Fallthrough 3855 case CK_i686: 3856 Builder.defineMacro("__i686"); 3857 Builder.defineMacro("__i686__"); 3858 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3859 Builder.defineMacro("__pentiumpro"); 3860 Builder.defineMacro("__pentiumpro__"); 3861 break; 3862 case CK_Pentium4: 3863 case CK_Pentium4M: 3864 defineCPUMacros(Builder, "pentium4"); 3865 break; 3866 case CK_Yonah: 3867 case CK_Prescott: 3868 case CK_Nocona: 3869 defineCPUMacros(Builder, "nocona"); 3870 break; 3871 case CK_Core2: 3872 case CK_Penryn: 3873 defineCPUMacros(Builder, "core2"); 3874 break; 3875 case CK_Bonnell: 3876 defineCPUMacros(Builder, "atom"); 3877 break; 3878 case CK_Silvermont: 3879 defineCPUMacros(Builder, "slm"); 3880 break; 3881 case CK_Nehalem: 3882 case CK_Westmere: 3883 case CK_SandyBridge: 3884 case CK_IvyBridge: 3885 case CK_Haswell: 3886 case CK_Broadwell: 3887 case CK_SkylakeClient: 3888 // FIXME: Historically, we defined this legacy name, it would be nice to 3889 // remove it at some point. We've never exposed fine-grained names for 3890 // recent primary x86 CPUs, and we should keep it that way. 3891 defineCPUMacros(Builder, "corei7"); 3892 break; 3893 case CK_SkylakeServer: 3894 defineCPUMacros(Builder, "skx"); 3895 break; 3896 case CK_Cannonlake: 3897 break; 3898 case CK_KNL: 3899 defineCPUMacros(Builder, "knl"); 3900 break; 3901 case CK_Lakemont: 3902 Builder.defineMacro("__tune_lakemont__"); 3903 break; 3904 case CK_K6_2: 3905 Builder.defineMacro("__k6_2__"); 3906 Builder.defineMacro("__tune_k6_2__"); 3907 // Fallthrough 3908 case CK_K6_3: 3909 if (CPU != CK_K6_2) { // In case of fallthrough 3910 // FIXME: GCC may be enabling these in cases where some other k6 3911 // architecture is specified but -m3dnow is explicitly provided. The 3912 // exact semantics need to be determined and emulated here. 3913 Builder.defineMacro("__k6_3__"); 3914 Builder.defineMacro("__tune_k6_3__"); 3915 } 3916 // Fallthrough 3917 case CK_K6: 3918 defineCPUMacros(Builder, "k6"); 3919 break; 3920 case CK_Athlon: 3921 case CK_AthlonThunderbird: 3922 case CK_Athlon4: 3923 case CK_AthlonXP: 3924 case CK_AthlonMP: 3925 defineCPUMacros(Builder, "athlon"); 3926 if (SSELevel != NoSSE) { 3927 Builder.defineMacro("__athlon_sse__"); 3928 Builder.defineMacro("__tune_athlon_sse__"); 3929 } 3930 break; 3931 case CK_K8: 3932 case CK_K8SSE3: 3933 case CK_x86_64: 3934 case CK_Opteron: 3935 case CK_OpteronSSE3: 3936 case CK_Athlon64: 3937 case CK_Athlon64SSE3: 3938 case CK_AthlonFX: 3939 defineCPUMacros(Builder, "k8"); 3940 break; 3941 case CK_AMDFAM10: 3942 defineCPUMacros(Builder, "amdfam10"); 3943 break; 3944 case CK_BTVER1: 3945 defineCPUMacros(Builder, "btver1"); 3946 break; 3947 case CK_BTVER2: 3948 defineCPUMacros(Builder, "btver2"); 3949 break; 3950 case CK_BDVER1: 3951 defineCPUMacros(Builder, "bdver1"); 3952 break; 3953 case CK_BDVER2: 3954 defineCPUMacros(Builder, "bdver2"); 3955 break; 3956 case CK_BDVER3: 3957 defineCPUMacros(Builder, "bdver3"); 3958 break; 3959 case CK_BDVER4: 3960 defineCPUMacros(Builder, "bdver4"); 3961 break; 3962 case CK_ZNVER1: 3963 defineCPUMacros(Builder, "znver1"); 3964 break; 3965 case CK_Geode: 3966 defineCPUMacros(Builder, "geode"); 3967 break; 3968 } 3969 3970 // Target properties. 3971 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3972 3973 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3974 // functions in glibc header files that use FP Stack inline asm which the 3975 // backend can't deal with (PR879). 3976 Builder.defineMacro("__NO_MATH_INLINES"); 3977 3978 if (HasAES) 3979 Builder.defineMacro("__AES__"); 3980 3981 if (HasPCLMUL) 3982 Builder.defineMacro("__PCLMUL__"); 3983 3984 if (HasLZCNT) 3985 Builder.defineMacro("__LZCNT__"); 3986 3987 if (HasRDRND) 3988 Builder.defineMacro("__RDRND__"); 3989 3990 if (HasFSGSBASE) 3991 Builder.defineMacro("__FSGSBASE__"); 3992 3993 if (HasBMI) 3994 Builder.defineMacro("__BMI__"); 3995 3996 if (HasBMI2) 3997 Builder.defineMacro("__BMI2__"); 3998 3999 if (HasPOPCNT) 4000 Builder.defineMacro("__POPCNT__"); 4001 4002 if (HasRTM) 4003 Builder.defineMacro("__RTM__"); 4004 4005 if (HasPRFCHW) 4006 Builder.defineMacro("__PRFCHW__"); 4007 4008 if (HasRDSEED) 4009 Builder.defineMacro("__RDSEED__"); 4010 4011 if (HasADX) 4012 Builder.defineMacro("__ADX__"); 4013 4014 if (HasTBM) 4015 Builder.defineMacro("__TBM__"); 4016 4017 if (HasLWP) 4018 Builder.defineMacro("__LWP__"); 4019 4020 if (HasMWAITX) 4021 Builder.defineMacro("__MWAITX__"); 4022 4023 switch (XOPLevel) { 4024 case XOP: 4025 Builder.defineMacro("__XOP__"); 4026 LLVM_FALLTHROUGH; 4027 case FMA4: 4028 Builder.defineMacro("__FMA4__"); 4029 LLVM_FALLTHROUGH; 4030 case SSE4A: 4031 Builder.defineMacro("__SSE4A__"); 4032 LLVM_FALLTHROUGH; 4033 case NoXOP: 4034 break; 4035 } 4036 4037 if (HasFMA) 4038 Builder.defineMacro("__FMA__"); 4039 4040 if (HasF16C) 4041 Builder.defineMacro("__F16C__"); 4042 4043 if (HasAVX512CD) 4044 Builder.defineMacro("__AVX512CD__"); 4045 if (HasAVX512VPOPCNTDQ) 4046 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4047 if (HasAVX512ER) 4048 Builder.defineMacro("__AVX512ER__"); 4049 if (HasAVX512PF) 4050 Builder.defineMacro("__AVX512PF__"); 4051 if (HasAVX512DQ) 4052 Builder.defineMacro("__AVX512DQ__"); 4053 if (HasAVX512BW) 4054 Builder.defineMacro("__AVX512BW__"); 4055 if (HasAVX512VL) 4056 Builder.defineMacro("__AVX512VL__"); 4057 if (HasAVX512VBMI) 4058 Builder.defineMacro("__AVX512VBMI__"); 4059 if (HasAVX512IFMA) 4060 Builder.defineMacro("__AVX512IFMA__"); 4061 4062 if (HasSHA) 4063 Builder.defineMacro("__SHA__"); 4064 4065 if (HasFXSR) 4066 Builder.defineMacro("__FXSR__"); 4067 if (HasXSAVE) 4068 Builder.defineMacro("__XSAVE__"); 4069 if (HasXSAVEOPT) 4070 Builder.defineMacro("__XSAVEOPT__"); 4071 if (HasXSAVEC) 4072 Builder.defineMacro("__XSAVEC__"); 4073 if (HasXSAVES) 4074 Builder.defineMacro("__XSAVES__"); 4075 if (HasPKU) 4076 Builder.defineMacro("__PKU__"); 4077 if (HasCX16) 4078 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4079 if (HasCLFLUSHOPT) 4080 Builder.defineMacro("__CLFLUSHOPT__"); 4081 if (HasCLWB) 4082 Builder.defineMacro("__CLWB__"); 4083 if (HasMPX) 4084 Builder.defineMacro("__MPX__"); 4085 if (HasSGX) 4086 Builder.defineMacro("__SGX__"); 4087 if (HasPREFETCHWT1) 4088 Builder.defineMacro("__PREFETCHWT1__"); 4089 if (HasCLZERO) 4090 Builder.defineMacro("__CLZERO__"); 4091 4092 // Each case falls through to the previous one here. 4093 switch (SSELevel) { 4094 case AVX512F: 4095 Builder.defineMacro("__AVX512F__"); 4096 LLVM_FALLTHROUGH; 4097 case AVX2: 4098 Builder.defineMacro("__AVX2__"); 4099 LLVM_FALLTHROUGH; 4100 case AVX: 4101 Builder.defineMacro("__AVX__"); 4102 LLVM_FALLTHROUGH; 4103 case SSE42: 4104 Builder.defineMacro("__SSE4_2__"); 4105 LLVM_FALLTHROUGH; 4106 case SSE41: 4107 Builder.defineMacro("__SSE4_1__"); 4108 LLVM_FALLTHROUGH; 4109 case SSSE3: 4110 Builder.defineMacro("__SSSE3__"); 4111 LLVM_FALLTHROUGH; 4112 case SSE3: 4113 Builder.defineMacro("__SSE3__"); 4114 LLVM_FALLTHROUGH; 4115 case SSE2: 4116 Builder.defineMacro("__SSE2__"); 4117 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4118 LLVM_FALLTHROUGH; 4119 case SSE1: 4120 Builder.defineMacro("__SSE__"); 4121 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4122 LLVM_FALLTHROUGH; 4123 case NoSSE: 4124 break; 4125 } 4126 4127 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4128 switch (SSELevel) { 4129 case AVX512F: 4130 case AVX2: 4131 case AVX: 4132 case SSE42: 4133 case SSE41: 4134 case SSSE3: 4135 case SSE3: 4136 case SSE2: 4137 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4138 break; 4139 case SSE1: 4140 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4141 break; 4142 default: 4143 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4144 } 4145 } 4146 4147 // Each case falls through to the previous one here. 4148 switch (MMX3DNowLevel) { 4149 case AMD3DNowAthlon: 4150 Builder.defineMacro("__3dNOW_A__"); 4151 LLVM_FALLTHROUGH; 4152 case AMD3DNow: 4153 Builder.defineMacro("__3dNOW__"); 4154 LLVM_FALLTHROUGH; 4155 case MMX: 4156 Builder.defineMacro("__MMX__"); 4157 LLVM_FALLTHROUGH; 4158 case NoMMX3DNow: 4159 break; 4160 } 4161 4162 if (CPU >= CK_i486) { 4163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4165 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4166 } 4167 if (CPU >= CK_i586) 4168 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4169 4170 if (HasFloat128) 4171 Builder.defineMacro("__SIZEOF_FLOAT128__", "16"); 4172 } 4173 4174 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4175 return llvm::StringSwitch<bool>(Feature) 4176 .Case("aes", HasAES) 4177 .Case("avx", SSELevel >= AVX) 4178 .Case("avx2", SSELevel >= AVX2) 4179 .Case("avx512f", SSELevel >= AVX512F) 4180 .Case("avx512cd", HasAVX512CD) 4181 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4182 .Case("avx512er", HasAVX512ER) 4183 .Case("avx512pf", HasAVX512PF) 4184 .Case("avx512dq", HasAVX512DQ) 4185 .Case("avx512bw", HasAVX512BW) 4186 .Case("avx512vl", HasAVX512VL) 4187 .Case("avx512vbmi", HasAVX512VBMI) 4188 .Case("avx512ifma", HasAVX512IFMA) 4189 .Case("bmi", HasBMI) 4190 .Case("bmi2", HasBMI2) 4191 .Case("clflushopt", HasCLFLUSHOPT) 4192 .Case("clwb", HasCLWB) 4193 .Case("clzero", HasCLZERO) 4194 .Case("cx16", HasCX16) 4195 .Case("f16c", HasF16C) 4196 .Case("fma", HasFMA) 4197 .Case("fma4", XOPLevel >= FMA4) 4198 .Case("fsgsbase", HasFSGSBASE) 4199 .Case("fxsr", HasFXSR) 4200 .Case("lzcnt", HasLZCNT) 4201 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4202 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4203 .Case("mmx", MMX3DNowLevel >= MMX) 4204 .Case("movbe", HasMOVBE) 4205 .Case("mpx", HasMPX) 4206 .Case("pclmul", HasPCLMUL) 4207 .Case("pku", HasPKU) 4208 .Case("popcnt", HasPOPCNT) 4209 .Case("prefetchwt1", HasPREFETCHWT1) 4210 .Case("prfchw", HasPRFCHW) 4211 .Case("rdrnd", HasRDRND) 4212 .Case("rdseed", HasRDSEED) 4213 .Case("rtm", HasRTM) 4214 .Case("sgx", HasSGX) 4215 .Case("sha", HasSHA) 4216 .Case("sse", SSELevel >= SSE1) 4217 .Case("sse2", SSELevel >= SSE2) 4218 .Case("sse3", SSELevel >= SSE3) 4219 .Case("ssse3", SSELevel >= SSSE3) 4220 .Case("sse4.1", SSELevel >= SSE41) 4221 .Case("sse4.2", SSELevel >= SSE42) 4222 .Case("sse4a", XOPLevel >= SSE4A) 4223 .Case("tbm", HasTBM) 4224 .Case("lwp", HasLWP) 4225 .Case("x86", true) 4226 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4227 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4228 .Case("xop", XOPLevel >= XOP) 4229 .Case("xsave", HasXSAVE) 4230 .Case("xsavec", HasXSAVEC) 4231 .Case("xsaves", HasXSAVES) 4232 .Case("xsaveopt", HasXSAVEOPT) 4233 .Default(false); 4234 } 4235 4236 // We can't use a generic validation scheme for the features accepted here 4237 // versus subtarget features accepted in the target attribute because the 4238 // bitfield structure that's initialized in the runtime only supports the 4239 // below currently rather than the full range of subtarget features. (See 4240 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4241 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4242 return llvm::StringSwitch<bool>(FeatureStr) 4243 .Case("cmov", true) 4244 .Case("mmx", true) 4245 .Case("popcnt", true) 4246 .Case("sse", true) 4247 .Case("sse2", true) 4248 .Case("sse3", true) 4249 .Case("ssse3", true) 4250 .Case("sse4.1", true) 4251 .Case("sse4.2", true) 4252 .Case("avx", true) 4253 .Case("avx2", true) 4254 .Case("sse4a", true) 4255 .Case("fma4", true) 4256 .Case("xop", true) 4257 .Case("fma", true) 4258 .Case("avx512f", true) 4259 .Case("bmi", true) 4260 .Case("bmi2", true) 4261 .Case("aes", true) 4262 .Case("pclmul", true) 4263 .Case("avx512vl", true) 4264 .Case("avx512bw", true) 4265 .Case("avx512dq", true) 4266 .Case("avx512cd", true) 4267 .Case("avx512vpopcntdq", true) 4268 .Case("avx512er", true) 4269 .Case("avx512pf", true) 4270 .Case("avx512vbmi", true) 4271 .Case("avx512ifma", true) 4272 .Default(false); 4273 } 4274 4275 bool 4276 X86TargetInfo::validateAsmConstraint(const char *&Name, 4277 TargetInfo::ConstraintInfo &Info) const { 4278 switch (*Name) { 4279 default: return false; 4280 // Constant constraints. 4281 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4282 // instructions. 4283 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4284 // x86_64 instructions. 4285 case 's': 4286 Info.setRequiresImmediate(); 4287 return true; 4288 case 'I': 4289 Info.setRequiresImmediate(0, 31); 4290 return true; 4291 case 'J': 4292 Info.setRequiresImmediate(0, 63); 4293 return true; 4294 case 'K': 4295 Info.setRequiresImmediate(-128, 127); 4296 return true; 4297 case 'L': 4298 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4299 return true; 4300 case 'M': 4301 Info.setRequiresImmediate(0, 3); 4302 return true; 4303 case 'N': 4304 Info.setRequiresImmediate(0, 255); 4305 return true; 4306 case 'O': 4307 Info.setRequiresImmediate(0, 127); 4308 return true; 4309 // Register constraints. 4310 case 'Y': // 'Y' is the first character for several 2-character constraints. 4311 // Shift the pointer to the second character of the constraint. 4312 Name++; 4313 switch (*Name) { 4314 default: 4315 return false; 4316 case '0': // First SSE register. 4317 case 't': // Any SSE register, when SSE2 is enabled. 4318 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4319 case 'm': // Any MMX register, when inter-unit moves enabled. 4320 case 'k': // AVX512 arch mask registers: k1-k7. 4321 Info.setAllowsRegister(); 4322 return true; 4323 } 4324 case 'f': // Any x87 floating point stack register. 4325 // Constraint 'f' cannot be used for output operands. 4326 if (Info.ConstraintStr[0] == '=') 4327 return false; 4328 Info.setAllowsRegister(); 4329 return true; 4330 case 'a': // eax. 4331 case 'b': // ebx. 4332 case 'c': // ecx. 4333 case 'd': // edx. 4334 case 'S': // esi. 4335 case 'D': // edi. 4336 case 'A': // edx:eax. 4337 case 't': // Top of floating point stack. 4338 case 'u': // Second from top of floating point stack. 4339 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4340 case 'y': // Any MMX register. 4341 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4342 case 'x': // Any SSE register. 4343 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4344 // for intermideate k reg operations). 4345 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4346 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4347 case 'l': // "Index" registers: any general register that can be used as an 4348 // index in a base+index memory access. 4349 Info.setAllowsRegister(); 4350 return true; 4351 // Floating point constant constraints. 4352 case 'C': // SSE floating point constant. 4353 case 'G': // x87 floating point constant. 4354 return true; 4355 } 4356 } 4357 4358 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4359 unsigned Size) const { 4360 // Strip off constraint modifiers. 4361 while (Constraint[0] == '=' || 4362 Constraint[0] == '+' || 4363 Constraint[0] == '&') 4364 Constraint = Constraint.substr(1); 4365 4366 return validateOperandSize(Constraint, Size); 4367 } 4368 4369 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4370 unsigned Size) const { 4371 return validateOperandSize(Constraint, Size); 4372 } 4373 4374 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4375 unsigned Size) const { 4376 switch (Constraint[0]) { 4377 default: break; 4378 case 'k': 4379 // Registers k0-k7 (AVX512) size limit is 64 bit. 4380 case 'y': 4381 return Size <= 64; 4382 case 'f': 4383 case 't': 4384 case 'u': 4385 return Size <= 128; 4386 case 'v': 4387 case 'x': 4388 if (SSELevel >= AVX512F) 4389 // 512-bit zmm registers can be used if target supports AVX512F. 4390 return Size <= 512U; 4391 else if (SSELevel >= AVX) 4392 // 256-bit ymm registers can be used if target supports AVX. 4393 return Size <= 256U; 4394 return Size <= 128U; 4395 case 'Y': 4396 // 'Y' is the first character for several 2-character constraints. 4397 switch (Constraint[1]) { 4398 default: break; 4399 case 'm': 4400 // 'Ym' is synonymous with 'y'. 4401 case 'k': 4402 return Size <= 64; 4403 case 'i': 4404 case 't': 4405 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4406 if (SSELevel >= AVX512F) 4407 return Size <= 512U; 4408 else if (SSELevel >= AVX) 4409 return Size <= 256U; 4410 return SSELevel >= SSE2 && Size <= 128U; 4411 } 4412 4413 } 4414 4415 return true; 4416 } 4417 4418 std::string 4419 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4420 switch (*Constraint) { 4421 case 'a': return std::string("{ax}"); 4422 case 'b': return std::string("{bx}"); 4423 case 'c': return std::string("{cx}"); 4424 case 'd': return std::string("{dx}"); 4425 case 'S': return std::string("{si}"); 4426 case 'D': return std::string("{di}"); 4427 case 'p': // address 4428 return std::string("im"); 4429 case 't': // top of floating point stack. 4430 return std::string("{st}"); 4431 case 'u': // second from top of floating point stack. 4432 return std::string("{st(1)}"); // second from top of floating point stack. 4433 case 'Y': 4434 switch (Constraint[1]) { 4435 default: 4436 // Break from inner switch and fall through (copy single char), 4437 // continue parsing after copying the current constraint into 4438 // the return string. 4439 break; 4440 case 'k': 4441 // "^" hints llvm that this is a 2 letter constraint. 4442 // "Constraint++" is used to promote the string iterator 4443 // to the next constraint. 4444 return std::string("^") + std::string(Constraint++, 2); 4445 } 4446 LLVM_FALLTHROUGH; 4447 default: 4448 return std::string(1, *Constraint); 4449 } 4450 } 4451 4452 // X86-32 generic target 4453 class X86_32TargetInfo : public X86TargetInfo { 4454 public: 4455 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4456 : X86TargetInfo(Triple, Opts) { 4457 DoubleAlign = LongLongAlign = 32; 4458 LongDoubleWidth = 96; 4459 LongDoubleAlign = 32; 4460 SuitableAlign = 128; 4461 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4462 SizeType = UnsignedInt; 4463 PtrDiffType = SignedInt; 4464 IntPtrType = SignedInt; 4465 RegParmMax = 3; 4466 4467 // Use fpret for all types. 4468 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4469 (1 << TargetInfo::Double) | 4470 (1 << TargetInfo::LongDouble)); 4471 4472 // x86-32 has atomics up to 8 bytes 4473 // FIXME: Check that we actually have cmpxchg8b before setting 4474 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4475 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4476 } 4477 BuiltinVaListKind getBuiltinVaListKind() const override { 4478 return TargetInfo::CharPtrBuiltinVaList; 4479 } 4480 4481 int getEHDataRegisterNumber(unsigned RegNo) const override { 4482 if (RegNo == 0) return 0; 4483 if (RegNo == 1) return 2; 4484 return -1; 4485 } 4486 bool validateOperandSize(StringRef Constraint, 4487 unsigned Size) const override { 4488 switch (Constraint[0]) { 4489 default: break; 4490 case 'R': 4491 case 'q': 4492 case 'Q': 4493 case 'a': 4494 case 'b': 4495 case 'c': 4496 case 'd': 4497 case 'S': 4498 case 'D': 4499 return Size <= 32; 4500 case 'A': 4501 return Size <= 64; 4502 } 4503 4504 return X86TargetInfo::validateOperandSize(Constraint, Size); 4505 } 4506 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4507 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4508 Builtin::FirstTSBuiltin + 1); 4509 } 4510 }; 4511 4512 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4513 public: 4514 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4515 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4516 4517 unsigned getFloatEvalMethod() const override { 4518 unsigned Major, Minor, Micro; 4519 getTriple().getOSVersion(Major, Minor, Micro); 4520 // New NetBSD uses the default rounding mode. 4521 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4522 return X86_32TargetInfo::getFloatEvalMethod(); 4523 // NetBSD before 6.99.26 defaults to "double" rounding. 4524 return 1; 4525 } 4526 }; 4527 4528 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4529 public: 4530 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4531 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4532 SizeType = UnsignedLong; 4533 IntPtrType = SignedLong; 4534 PtrDiffType = SignedLong; 4535 } 4536 }; 4537 4538 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4539 public: 4540 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4541 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4542 SizeType = UnsignedLong; 4543 IntPtrType = SignedLong; 4544 PtrDiffType = SignedLong; 4545 } 4546 }; 4547 4548 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4549 public: 4550 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4551 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4552 LongDoubleWidth = 128; 4553 LongDoubleAlign = 128; 4554 SuitableAlign = 128; 4555 MaxVectorAlign = 256; 4556 // The watchOS simulator uses the builtin bool type for Objective-C. 4557 llvm::Triple T = llvm::Triple(Triple); 4558 if (T.isWatchOS()) 4559 UseSignedCharForObjCBool = false; 4560 SizeType = UnsignedLong; 4561 IntPtrType = SignedLong; 4562 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4563 HasAlignMac68kSupport = true; 4564 } 4565 4566 bool handleTargetFeatures(std::vector<std::string> &Features, 4567 DiagnosticsEngine &Diags) override { 4568 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4569 Diags)) 4570 return false; 4571 // We now know the features we have: we can decide how to align vectors. 4572 MaxVectorAlign = 4573 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4574 return true; 4575 } 4576 }; 4577 4578 // x86-32 Windows target 4579 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4580 public: 4581 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4582 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4583 WCharType = UnsignedShort; 4584 DoubleAlign = LongLongAlign = 64; 4585 bool IsWinCOFF = 4586 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4587 resetDataLayout(IsWinCOFF 4588 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4589 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4590 } 4591 void getTargetDefines(const LangOptions &Opts, 4592 MacroBuilder &Builder) const override { 4593 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4594 } 4595 }; 4596 4597 // x86-32 Windows Visual Studio target 4598 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4599 public: 4600 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4601 const TargetOptions &Opts) 4602 : WindowsX86_32TargetInfo(Triple, Opts) { 4603 LongDoubleWidth = LongDoubleAlign = 64; 4604 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4605 } 4606 void getTargetDefines(const LangOptions &Opts, 4607 MacroBuilder &Builder) const override { 4608 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4609 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4610 // The value of the following reflects processor type. 4611 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4612 // We lost the original triple, so we use the default. 4613 Builder.defineMacro("_M_IX86", "600"); 4614 } 4615 }; 4616 4617 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4618 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4619 // supports __declspec natively under -fms-extensions, but we define a no-op 4620 // __declspec macro anyway for pre-processor compatibility. 4621 if (Opts.MicrosoftExt) 4622 Builder.defineMacro("__declspec", "__declspec"); 4623 else 4624 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4625 4626 if (!Opts.MicrosoftExt) { 4627 // Provide macros for all the calling convention keywords. Provide both 4628 // single and double underscore prefixed variants. These are available on 4629 // x64 as well as x86, even though they have no effect. 4630 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4631 for (const char *CC : CCs) { 4632 std::string GCCSpelling = "__attribute__((__"; 4633 GCCSpelling += CC; 4634 GCCSpelling += "__))"; 4635 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4636 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4637 } 4638 } 4639 } 4640 4641 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4642 Builder.defineMacro("__MSVCRT__"); 4643 Builder.defineMacro("__MINGW32__"); 4644 addCygMingDefines(Opts, Builder); 4645 } 4646 4647 // x86-32 MinGW target 4648 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4649 public: 4650 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4651 : WindowsX86_32TargetInfo(Triple, Opts) { 4652 HasFloat128 = true; 4653 } 4654 void getTargetDefines(const LangOptions &Opts, 4655 MacroBuilder &Builder) const override { 4656 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4657 DefineStd(Builder, "WIN32", Opts); 4658 DefineStd(Builder, "WINNT", Opts); 4659 Builder.defineMacro("_X86_"); 4660 addMinGWDefines(Opts, Builder); 4661 } 4662 }; 4663 4664 // x86-32 Cygwin target 4665 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4666 public: 4667 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4668 : X86_32TargetInfo(Triple, Opts) { 4669 WCharType = UnsignedShort; 4670 DoubleAlign = LongLongAlign = 64; 4671 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4672 } 4673 void getTargetDefines(const LangOptions &Opts, 4674 MacroBuilder &Builder) const override { 4675 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4676 Builder.defineMacro("_X86_"); 4677 Builder.defineMacro("__CYGWIN__"); 4678 Builder.defineMacro("__CYGWIN32__"); 4679 addCygMingDefines(Opts, Builder); 4680 DefineStd(Builder, "unix", Opts); 4681 if (Opts.CPlusPlus) 4682 Builder.defineMacro("_GNU_SOURCE"); 4683 } 4684 }; 4685 4686 // x86-32 Haiku target 4687 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4688 public: 4689 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4690 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4691 } 4692 void getTargetDefines(const LangOptions &Opts, 4693 MacroBuilder &Builder) const override { 4694 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4695 Builder.defineMacro("__INTEL__"); 4696 } 4697 }; 4698 4699 // X86-32 MCU target 4700 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4701 public: 4702 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4703 : X86_32TargetInfo(Triple, Opts) { 4704 LongDoubleWidth = 64; 4705 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4706 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4707 WIntType = UnsignedInt; 4708 } 4709 4710 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4711 // On MCU we support only C calling convention. 4712 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4713 } 4714 4715 void getTargetDefines(const LangOptions &Opts, 4716 MacroBuilder &Builder) const override { 4717 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4718 Builder.defineMacro("__iamcu"); 4719 Builder.defineMacro("__iamcu__"); 4720 } 4721 4722 bool allowsLargerPreferedTypeAlignment() const override { 4723 return false; 4724 } 4725 }; 4726 4727 // RTEMS Target 4728 template<typename Target> 4729 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4730 protected: 4731 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4732 MacroBuilder &Builder) const override { 4733 // RTEMS defines; list based off of gcc output 4734 4735 Builder.defineMacro("__rtems__"); 4736 Builder.defineMacro("__ELF__"); 4737 } 4738 4739 public: 4740 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4741 : OSTargetInfo<Target>(Triple, Opts) { 4742 switch (Triple.getArch()) { 4743 default: 4744 case llvm::Triple::x86: 4745 // this->MCountName = ".mcount"; 4746 break; 4747 case llvm::Triple::mips: 4748 case llvm::Triple::mipsel: 4749 case llvm::Triple::ppc: 4750 case llvm::Triple::ppc64: 4751 case llvm::Triple::ppc64le: 4752 // this->MCountName = "_mcount"; 4753 break; 4754 case llvm::Triple::arm: 4755 // this->MCountName = "__mcount"; 4756 break; 4757 } 4758 } 4759 }; 4760 4761 // x86-32 RTEMS target 4762 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4763 public: 4764 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4765 : X86_32TargetInfo(Triple, Opts) { 4766 SizeType = UnsignedLong; 4767 IntPtrType = SignedLong; 4768 PtrDiffType = SignedLong; 4769 } 4770 void getTargetDefines(const LangOptions &Opts, 4771 MacroBuilder &Builder) const override { 4772 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4773 Builder.defineMacro("__INTEL__"); 4774 Builder.defineMacro("__rtems__"); 4775 } 4776 }; 4777 4778 // x86-64 generic target 4779 class X86_64TargetInfo : public X86TargetInfo { 4780 public: 4781 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4782 : X86TargetInfo(Triple, Opts) { 4783 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4784 bool IsWinCOFF = 4785 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4786 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4787 LongDoubleWidth = 128; 4788 LongDoubleAlign = 128; 4789 LargeArrayMinWidth = 128; 4790 LargeArrayAlign = 128; 4791 SuitableAlign = 128; 4792 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4793 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4794 IntPtrType = IsX32 ? SignedInt : SignedLong; 4795 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4796 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4797 RegParmMax = 6; 4798 4799 // Pointers are 32-bit in x32. 4800 resetDataLayout(IsX32 4801 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4802 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4803 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4804 4805 // Use fpret only for long double. 4806 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4807 4808 // Use fp2ret for _Complex long double. 4809 ComplexLongDoubleUsesFP2Ret = true; 4810 4811 // Make __builtin_ms_va_list available. 4812 HasBuiltinMSVaList = true; 4813 4814 // x86-64 has atomics up to 16 bytes. 4815 MaxAtomicPromoteWidth = 128; 4816 MaxAtomicInlineWidth = 128; 4817 } 4818 BuiltinVaListKind getBuiltinVaListKind() const override { 4819 return TargetInfo::X86_64ABIBuiltinVaList; 4820 } 4821 4822 int getEHDataRegisterNumber(unsigned RegNo) const override { 4823 if (RegNo == 0) return 0; 4824 if (RegNo == 1) return 1; 4825 return -1; 4826 } 4827 4828 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4829 switch (CC) { 4830 case CC_C: 4831 case CC_Swift: 4832 case CC_X86VectorCall: 4833 case CC_IntelOclBicc: 4834 case CC_X86_64Win64: 4835 case CC_PreserveMost: 4836 case CC_PreserveAll: 4837 case CC_X86RegCall: 4838 case CC_OpenCLKernel: 4839 return CCCR_OK; 4840 default: 4841 return CCCR_Warning; 4842 } 4843 } 4844 4845 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4846 return CC_C; 4847 } 4848 4849 // for x32 we need it here explicitly 4850 bool hasInt128Type() const override { return true; } 4851 unsigned getUnwindWordWidth() const override { return 64; } 4852 unsigned getRegisterWidth() const override { return 64; } 4853 4854 bool validateGlobalRegisterVariable(StringRef RegName, 4855 unsigned RegSize, 4856 bool &HasSizeMismatch) const override { 4857 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4858 // handle. 4859 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4860 // Check that the register size is 64-bit. 4861 HasSizeMismatch = RegSize != 64; 4862 return true; 4863 } 4864 4865 // Check if the register is a 32-bit register the backend can handle. 4866 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4867 HasSizeMismatch); 4868 } 4869 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4870 return llvm::makeArrayRef(BuiltinInfoX86, 4871 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4872 } 4873 }; 4874 4875 // x86-64 Windows target 4876 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4877 public: 4878 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4879 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4880 WCharType = UnsignedShort; 4881 LongWidth = LongAlign = 32; 4882 DoubleAlign = LongLongAlign = 64; 4883 IntMaxType = SignedLongLong; 4884 Int64Type = SignedLongLong; 4885 SizeType = UnsignedLongLong; 4886 PtrDiffType = SignedLongLong; 4887 IntPtrType = SignedLongLong; 4888 } 4889 4890 void getTargetDefines(const LangOptions &Opts, 4891 MacroBuilder &Builder) const override { 4892 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4893 Builder.defineMacro("_WIN64"); 4894 } 4895 4896 BuiltinVaListKind getBuiltinVaListKind() const override { 4897 return TargetInfo::CharPtrBuiltinVaList; 4898 } 4899 4900 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4901 switch (CC) { 4902 case CC_X86StdCall: 4903 case CC_X86ThisCall: 4904 case CC_X86FastCall: 4905 return CCCR_Ignore; 4906 case CC_C: 4907 case CC_X86VectorCall: 4908 case CC_IntelOclBicc: 4909 case CC_X86_64SysV: 4910 case CC_Swift: 4911 case CC_X86RegCall: 4912 case CC_OpenCLKernel: 4913 return CCCR_OK; 4914 default: 4915 return CCCR_Warning; 4916 } 4917 } 4918 }; 4919 4920 // x86-64 Windows Visual Studio target 4921 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4922 public: 4923 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4924 const TargetOptions &Opts) 4925 : WindowsX86_64TargetInfo(Triple, Opts) { 4926 LongDoubleWidth = LongDoubleAlign = 64; 4927 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4928 } 4929 void getTargetDefines(const LangOptions &Opts, 4930 MacroBuilder &Builder) const override { 4931 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4932 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4933 Builder.defineMacro("_M_X64", "100"); 4934 Builder.defineMacro("_M_AMD64", "100"); 4935 } 4936 }; 4937 4938 // x86-64 MinGW target 4939 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4940 public: 4941 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4942 : WindowsX86_64TargetInfo(Triple, Opts) { 4943 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4944 // with x86 FP ops. Weird. 4945 LongDoubleWidth = LongDoubleAlign = 128; 4946 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4947 HasFloat128 = true; 4948 } 4949 4950 void getTargetDefines(const LangOptions &Opts, 4951 MacroBuilder &Builder) const override { 4952 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4953 DefineStd(Builder, "WIN64", Opts); 4954 Builder.defineMacro("__MINGW64__"); 4955 addMinGWDefines(Opts, Builder); 4956 4957 // GCC defines this macro when it is using __gxx_personality_seh0. 4958 if (!Opts.SjLjExceptions) 4959 Builder.defineMacro("__SEH__"); 4960 } 4961 }; 4962 4963 // x86-64 Cygwin target 4964 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4965 public: 4966 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4967 : X86_64TargetInfo(Triple, Opts) { 4968 TLSSupported = false; 4969 WCharType = UnsignedShort; 4970 } 4971 void getTargetDefines(const LangOptions &Opts, 4972 MacroBuilder &Builder) const override { 4973 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4974 Builder.defineMacro("__x86_64__"); 4975 Builder.defineMacro("__CYGWIN__"); 4976 Builder.defineMacro("__CYGWIN64__"); 4977 addCygMingDefines(Opts, Builder); 4978 DefineStd(Builder, "unix", Opts); 4979 if (Opts.CPlusPlus) 4980 Builder.defineMacro("_GNU_SOURCE"); 4981 4982 // GCC defines this macro when it is using __gxx_personality_seh0. 4983 if (!Opts.SjLjExceptions) 4984 Builder.defineMacro("__SEH__"); 4985 } 4986 }; 4987 4988 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4989 public: 4990 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4991 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4992 Int64Type = SignedLongLong; 4993 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4994 llvm::Triple T = llvm::Triple(Triple); 4995 if (T.isiOS()) 4996 UseSignedCharForObjCBool = false; 4997 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4998 } 4999 5000 bool handleTargetFeatures(std::vector<std::string> &Features, 5001 DiagnosticsEngine &Diags) override { 5002 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 5003 Diags)) 5004 return false; 5005 // We now know the features we have: we can decide how to align vectors. 5006 MaxVectorAlign = 5007 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 5008 return true; 5009 } 5010 }; 5011 5012 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5013 public: 5014 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5015 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5016 IntMaxType = SignedLongLong; 5017 Int64Type = SignedLongLong; 5018 } 5019 }; 5020 5021 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5022 public: 5023 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5024 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5025 IntMaxType = SignedLongLong; 5026 Int64Type = SignedLongLong; 5027 } 5028 }; 5029 5030 class ARMTargetInfo : public TargetInfo { 5031 // Possible FPU choices. 5032 enum FPUMode { 5033 VFP2FPU = (1 << 0), 5034 VFP3FPU = (1 << 1), 5035 VFP4FPU = (1 << 2), 5036 NeonFPU = (1 << 3), 5037 FPARMV8 = (1 << 4) 5038 }; 5039 5040 // Possible HWDiv features. 5041 enum HWDivMode { 5042 HWDivThumb = (1 << 0), 5043 HWDivARM = (1 << 1) 5044 }; 5045 5046 static bool FPUModeIsVFP(FPUMode Mode) { 5047 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5048 } 5049 5050 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5051 static const char * const GCCRegNames[]; 5052 5053 std::string ABI, CPU; 5054 5055 StringRef CPUProfile; 5056 StringRef CPUAttr; 5057 5058 enum { 5059 FP_Default, 5060 FP_VFP, 5061 FP_Neon 5062 } FPMath; 5063 5064 unsigned ArchISA; 5065 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5066 unsigned ArchProfile; 5067 unsigned ArchVersion; 5068 5069 unsigned FPU : 5; 5070 5071 unsigned IsAAPCS : 1; 5072 unsigned HWDiv : 2; 5073 5074 // Initialized via features. 5075 unsigned SoftFloat : 1; 5076 unsigned SoftFloatABI : 1; 5077 5078 unsigned CRC : 1; 5079 unsigned Crypto : 1; 5080 unsigned DSP : 1; 5081 unsigned Unaligned : 1; 5082 5083 enum { 5084 LDREX_B = (1 << 0), /// byte (8-bit) 5085 LDREX_H = (1 << 1), /// half (16-bit) 5086 LDREX_W = (1 << 2), /// word (32-bit) 5087 LDREX_D = (1 << 3), /// double (64-bit) 5088 }; 5089 5090 uint32_t LDREX; 5091 5092 // ACLE 6.5.1 Hardware floating point 5093 enum { 5094 HW_FP_HP = (1 << 1), /// half (16-bit) 5095 HW_FP_SP = (1 << 2), /// single (32-bit) 5096 HW_FP_DP = (1 << 3), /// double (64-bit) 5097 }; 5098 uint32_t HW_FP; 5099 5100 static const Builtin::Info BuiltinInfo[]; 5101 5102 void setABIAAPCS() { 5103 IsAAPCS = true; 5104 5105 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5106 const llvm::Triple &T = getTriple(); 5107 5108 // size_t is unsigned long on MachO-derived environments, NetBSD, 5109 // OpenBSD and Bitrig. 5110 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5111 T.getOS() == llvm::Triple::OpenBSD || 5112 T.getOS() == llvm::Triple::Bitrig) 5113 SizeType = UnsignedLong; 5114 else 5115 SizeType = UnsignedInt; 5116 5117 switch (T.getOS()) { 5118 case llvm::Triple::NetBSD: 5119 case llvm::Triple::OpenBSD: 5120 WCharType = SignedInt; 5121 break; 5122 case llvm::Triple::Win32: 5123 WCharType = UnsignedShort; 5124 break; 5125 case llvm::Triple::Linux: 5126 default: 5127 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5128 WCharType = UnsignedInt; 5129 break; 5130 } 5131 5132 UseBitFieldTypeAlignment = true; 5133 5134 ZeroLengthBitfieldBoundary = 0; 5135 5136 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5137 // so set preferred for small types to 32. 5138 if (T.isOSBinFormatMachO()) { 5139 resetDataLayout(BigEndian 5140 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5141 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5142 } else if (T.isOSWindows()) { 5143 assert(!BigEndian && "Windows on ARM does not support big endian"); 5144 resetDataLayout("e" 5145 "-m:w" 5146 "-p:32:32" 5147 "-i64:64" 5148 "-v128:64:128" 5149 "-a:0:32" 5150 "-n32" 5151 "-S64"); 5152 } else if (T.isOSNaCl()) { 5153 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5154 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5155 } else { 5156 resetDataLayout(BigEndian 5157 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5158 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5159 } 5160 5161 // FIXME: Enumerated types are variable width in straight AAPCS. 5162 } 5163 5164 void setABIAPCS(bool IsAAPCS16) { 5165 const llvm::Triple &T = getTriple(); 5166 5167 IsAAPCS = false; 5168 5169 if (IsAAPCS16) 5170 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5171 else 5172 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5173 5174 // size_t is unsigned int on FreeBSD. 5175 if (T.getOS() == llvm::Triple::FreeBSD) 5176 SizeType = UnsignedInt; 5177 else 5178 SizeType = UnsignedLong; 5179 5180 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5181 WCharType = SignedInt; 5182 5183 // Do not respect the alignment of bit-field types when laying out 5184 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5185 UseBitFieldTypeAlignment = false; 5186 5187 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5188 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5189 /// gcc. 5190 ZeroLengthBitfieldBoundary = 32; 5191 5192 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5193 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5194 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5195 } else if (T.isOSBinFormatMachO()) 5196 resetDataLayout( 5197 BigEndian 5198 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5199 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5200 else 5201 resetDataLayout( 5202 BigEndian 5203 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5204 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5205 5206 // FIXME: Override "preferred align" for double and long long. 5207 } 5208 5209 void setArchInfo() { 5210 StringRef ArchName = getTriple().getArchName(); 5211 5212 ArchISA = llvm::ARM::parseArchISA(ArchName); 5213 CPU = llvm::ARM::getDefaultCPU(ArchName); 5214 unsigned AK = llvm::ARM::parseArch(ArchName); 5215 if (AK != llvm::ARM::AK_INVALID) 5216 ArchKind = AK; 5217 setArchInfo(ArchKind); 5218 } 5219 5220 void setArchInfo(unsigned Kind) { 5221 StringRef SubArch; 5222 5223 // cache TargetParser info 5224 ArchKind = Kind; 5225 SubArch = llvm::ARM::getSubArch(ArchKind); 5226 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5227 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5228 5229 // cache CPU related strings 5230 CPUAttr = getCPUAttr(); 5231 CPUProfile = getCPUProfile(); 5232 } 5233 5234 void setAtomic() { 5235 // when triple does not specify a sub arch, 5236 // then we are not using inline atomics 5237 bool ShouldUseInlineAtomic = 5238 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5239 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5240 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5241 if (ArchProfile == llvm::ARM::PK_M) { 5242 MaxAtomicPromoteWidth = 32; 5243 if (ShouldUseInlineAtomic) 5244 MaxAtomicInlineWidth = 32; 5245 } 5246 else { 5247 MaxAtomicPromoteWidth = 64; 5248 if (ShouldUseInlineAtomic) 5249 MaxAtomicInlineWidth = 64; 5250 } 5251 } 5252 5253 bool isThumb() const { 5254 return (ArchISA == llvm::ARM::IK_THUMB); 5255 } 5256 5257 bool supportsThumb() const { 5258 return CPUAttr.count('T') || ArchVersion >= 6; 5259 } 5260 5261 bool supportsThumb2() const { 5262 return CPUAttr.equals("6T2") || 5263 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5264 } 5265 5266 StringRef getCPUAttr() const { 5267 // For most sub-arches, the build attribute CPU name is enough. 5268 // For Cortex variants, it's slightly different. 5269 switch(ArchKind) { 5270 default: 5271 return llvm::ARM::getCPUAttr(ArchKind); 5272 case llvm::ARM::AK_ARMV6M: 5273 return "6M"; 5274 case llvm::ARM::AK_ARMV7S: 5275 return "7S"; 5276 case llvm::ARM::AK_ARMV7A: 5277 return "7A"; 5278 case llvm::ARM::AK_ARMV7R: 5279 return "7R"; 5280 case llvm::ARM::AK_ARMV7M: 5281 return "7M"; 5282 case llvm::ARM::AK_ARMV7EM: 5283 return "7EM"; 5284 case llvm::ARM::AK_ARMV7VE: 5285 return "7VE"; 5286 case llvm::ARM::AK_ARMV8A: 5287 return "8A"; 5288 case llvm::ARM::AK_ARMV8_1A: 5289 return "8_1A"; 5290 case llvm::ARM::AK_ARMV8_2A: 5291 return "8_2A"; 5292 case llvm::ARM::AK_ARMV8MBaseline: 5293 return "8M_BASE"; 5294 case llvm::ARM::AK_ARMV8MMainline: 5295 return "8M_MAIN"; 5296 case llvm::ARM::AK_ARMV8R: 5297 return "8R"; 5298 } 5299 } 5300 5301 StringRef getCPUProfile() const { 5302 switch(ArchProfile) { 5303 case llvm::ARM::PK_A: 5304 return "A"; 5305 case llvm::ARM::PK_R: 5306 return "R"; 5307 case llvm::ARM::PK_M: 5308 return "M"; 5309 default: 5310 return ""; 5311 } 5312 } 5313 5314 public: 5315 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5316 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5317 HW_FP(0) { 5318 5319 switch (getTriple().getOS()) { 5320 case llvm::Triple::NetBSD: 5321 case llvm::Triple::OpenBSD: 5322 PtrDiffType = SignedLong; 5323 break; 5324 default: 5325 PtrDiffType = SignedInt; 5326 break; 5327 } 5328 5329 // Cache arch related info. 5330 setArchInfo(); 5331 5332 // {} in inline assembly are neon specifiers, not assembly variant 5333 // specifiers. 5334 NoAsmVariants = true; 5335 5336 // FIXME: This duplicates code from the driver that sets the -target-abi 5337 // option - this code is used if -target-abi isn't passed and should 5338 // be unified in some way. 5339 if (Triple.isOSBinFormatMachO()) { 5340 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5341 // the frontend matches that. 5342 if (Triple.getEnvironment() == llvm::Triple::EABI || 5343 Triple.getOS() == llvm::Triple::UnknownOS || 5344 ArchProfile == llvm::ARM::PK_M) { 5345 setABI("aapcs"); 5346 } else if (Triple.isWatchABI()) { 5347 setABI("aapcs16"); 5348 } else { 5349 setABI("apcs-gnu"); 5350 } 5351 } else if (Triple.isOSWindows()) { 5352 // FIXME: this is invalid for WindowsCE 5353 setABI("aapcs"); 5354 } else { 5355 // Select the default based on the platform. 5356 switch (Triple.getEnvironment()) { 5357 case llvm::Triple::Android: 5358 case llvm::Triple::GNUEABI: 5359 case llvm::Triple::GNUEABIHF: 5360 case llvm::Triple::MuslEABI: 5361 case llvm::Triple::MuslEABIHF: 5362 setABI("aapcs-linux"); 5363 break; 5364 case llvm::Triple::EABIHF: 5365 case llvm::Triple::EABI: 5366 setABI("aapcs"); 5367 break; 5368 case llvm::Triple::GNU: 5369 setABI("apcs-gnu"); 5370 break; 5371 default: 5372 if (Triple.getOS() == llvm::Triple::NetBSD) 5373 setABI("apcs-gnu"); 5374 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5375 setABI("aapcs-linux"); 5376 else 5377 setABI("aapcs"); 5378 break; 5379 } 5380 } 5381 5382 // ARM targets default to using the ARM C++ ABI. 5383 TheCXXABI.set(TargetCXXABI::GenericARM); 5384 5385 // ARM has atomics up to 8 bytes 5386 setAtomic(); 5387 5388 // Maximum alignment for ARM NEON data types should be 64-bits (AAPCS) 5389 if (IsAAPCS && (Triple.getEnvironment() != llvm::Triple::Android)) 5390 MaxVectorAlign = 64; 5391 5392 // Do force alignment of members that follow zero length bitfields. If 5393 // the alignment of the zero-length bitfield is greater than the member 5394 // that follows it, `bar', `bar' will be aligned as the type of the 5395 // zero length bitfield. 5396 UseZeroLengthBitfieldAlignment = true; 5397 5398 if (Triple.getOS() == llvm::Triple::Linux || 5399 Triple.getOS() == llvm::Triple::UnknownOS) 5400 this->MCountName = 5401 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5402 } 5403 5404 StringRef getABI() const override { return ABI; } 5405 5406 bool setABI(const std::string &Name) override { 5407 ABI = Name; 5408 5409 // The defaults (above) are for AAPCS, check if we need to change them. 5410 // 5411 // FIXME: We need support for -meabi... we could just mangle it into the 5412 // name. 5413 if (Name == "apcs-gnu" || Name == "aapcs16") { 5414 setABIAPCS(Name == "aapcs16"); 5415 return true; 5416 } 5417 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5418 setABIAAPCS(); 5419 return true; 5420 } 5421 return false; 5422 } 5423 5424 // FIXME: This should be based on Arch attributes, not CPU names. 5425 bool 5426 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5427 StringRef CPU, 5428 const std::vector<std::string> &FeaturesVec) const override { 5429 5430 std::vector<StringRef> TargetFeatures; 5431 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5432 5433 // get default FPU features 5434 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5435 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5436 5437 // get default Extension features 5438 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5439 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5440 5441 for (auto Feature : TargetFeatures) 5442 if (Feature[0] == '+') 5443 Features[Feature.drop_front(1)] = true; 5444 5445 // Enable or disable thumb-mode explicitly per function to enable mixed 5446 // ARM and Thumb code generation. 5447 if (isThumb()) 5448 Features["thumb-mode"] = true; 5449 else 5450 Features["thumb-mode"] = false; 5451 5452 // Convert user-provided arm and thumb GNU target attributes to 5453 // [-|+]thumb-mode target features respectively. 5454 std::vector<std::string> UpdatedFeaturesVec(FeaturesVec); 5455 for (auto &Feature : UpdatedFeaturesVec) { 5456 if (Feature.compare("+arm") == 0) 5457 Feature = "-thumb-mode"; 5458 else if (Feature.compare("+thumb") == 0) 5459 Feature = "+thumb-mode"; 5460 } 5461 5462 return TargetInfo::initFeatureMap(Features, Diags, CPU, UpdatedFeaturesVec); 5463 } 5464 5465 bool handleTargetFeatures(std::vector<std::string> &Features, 5466 DiagnosticsEngine &Diags) override { 5467 FPU = 0; 5468 CRC = 0; 5469 Crypto = 0; 5470 DSP = 0; 5471 Unaligned = 1; 5472 SoftFloat = SoftFloatABI = false; 5473 HWDiv = 0; 5474 5475 // This does not diagnose illegal cases like having both 5476 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5477 uint32_t HW_FP_remove = 0; 5478 for (const auto &Feature : Features) { 5479 if (Feature == "+soft-float") { 5480 SoftFloat = true; 5481 } else if (Feature == "+soft-float-abi") { 5482 SoftFloatABI = true; 5483 } else if (Feature == "+vfp2") { 5484 FPU |= VFP2FPU; 5485 HW_FP |= HW_FP_SP | HW_FP_DP; 5486 } else if (Feature == "+vfp3") { 5487 FPU |= VFP3FPU; 5488 HW_FP |= HW_FP_SP | HW_FP_DP; 5489 } else if (Feature == "+vfp4") { 5490 FPU |= VFP4FPU; 5491 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5492 } else if (Feature == "+fp-armv8") { 5493 FPU |= FPARMV8; 5494 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5495 } else if (Feature == "+neon") { 5496 FPU |= NeonFPU; 5497 HW_FP |= HW_FP_SP | HW_FP_DP; 5498 } else if (Feature == "+hwdiv") { 5499 HWDiv |= HWDivThumb; 5500 } else if (Feature == "+hwdiv-arm") { 5501 HWDiv |= HWDivARM; 5502 } else if (Feature == "+crc") { 5503 CRC = 1; 5504 } else if (Feature == "+crypto") { 5505 Crypto = 1; 5506 } else if (Feature == "+dsp") { 5507 DSP = 1; 5508 } else if (Feature == "+fp-only-sp") { 5509 HW_FP_remove |= HW_FP_DP; 5510 } else if (Feature == "+strict-align") { 5511 Unaligned = 0; 5512 } else if (Feature == "+fp16") { 5513 HW_FP |= HW_FP_HP; 5514 } 5515 } 5516 HW_FP &= ~HW_FP_remove; 5517 5518 switch (ArchVersion) { 5519 case 6: 5520 if (ArchProfile == llvm::ARM::PK_M) 5521 LDREX = 0; 5522 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5523 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5524 else 5525 LDREX = LDREX_W; 5526 break; 5527 case 7: 5528 if (ArchProfile == llvm::ARM::PK_M) 5529 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5530 else 5531 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5532 break; 5533 case 8: 5534 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5535 } 5536 5537 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5538 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5539 return false; 5540 } 5541 5542 if (FPMath == FP_Neon) 5543 Features.push_back("+neonfp"); 5544 else if (FPMath == FP_VFP) 5545 Features.push_back("-neonfp"); 5546 5547 // Remove front-end specific options which the backend handles differently. 5548 auto Feature = 5549 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5550 if (Feature != Features.end()) 5551 Features.erase(Feature); 5552 5553 return true; 5554 } 5555 5556 bool hasFeature(StringRef Feature) const override { 5557 return llvm::StringSwitch<bool>(Feature) 5558 .Case("arm", true) 5559 .Case("aarch32", true) 5560 .Case("softfloat", SoftFloat) 5561 .Case("thumb", isThumb()) 5562 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5563 .Case("vfp", FPU && !SoftFloat) 5564 .Case("hwdiv", HWDiv & HWDivThumb) 5565 .Case("hwdiv-arm", HWDiv & HWDivARM) 5566 .Default(false); 5567 } 5568 5569 bool setCPU(const std::string &Name) override { 5570 if (Name != "generic") 5571 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5572 5573 if (ArchKind == llvm::ARM::AK_INVALID) 5574 return false; 5575 setAtomic(); 5576 CPU = Name; 5577 return true; 5578 } 5579 5580 bool setFPMath(StringRef Name) override; 5581 5582 void getTargetDefines(const LangOptions &Opts, 5583 MacroBuilder &Builder) const override { 5584 // Target identification. 5585 Builder.defineMacro("__arm"); 5586 Builder.defineMacro("__arm__"); 5587 // For bare-metal none-eabi. 5588 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5589 (getTriple().getEnvironment() == llvm::Triple::EABI || 5590 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5591 Builder.defineMacro("__ELF__"); 5592 5593 5594 // Target properties. 5595 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5596 5597 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5598 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5599 if (getTriple().isWatchABI()) 5600 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5601 5602 if (!CPUAttr.empty()) 5603 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5604 5605 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5606 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5607 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5608 5609 if (ArchVersion >= 8) { 5610 // ACLE 6.5.7 Crypto Extension 5611 if (Crypto) 5612 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5613 // ACLE 6.5.8 CRC32 Extension 5614 if (CRC) 5615 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5616 // ACLE 6.5.10 Numeric Maximum and Minimum 5617 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5618 // ACLE 6.5.9 Directed Rounding 5619 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5620 } 5621 5622 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5623 // is not defined for the M-profile. 5624 // NOTE that the default profile is assumed to be 'A' 5625 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5626 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5627 5628 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5629 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5630 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5631 // v7 and v8 architectures excluding v8-M Baseline. 5632 if (supportsThumb2()) 5633 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5634 else if (supportsThumb()) 5635 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5636 5637 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5638 // instruction set such as ARM or Thumb. 5639 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5640 5641 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5642 5643 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5644 if (!CPUProfile.empty()) 5645 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5646 5647 // ACLE 6.4.3 Unaligned access supported in hardware 5648 if (Unaligned) 5649 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5650 5651 // ACLE 6.4.4 LDREX/STREX 5652 if (LDREX) 5653 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5654 5655 // ACLE 6.4.5 CLZ 5656 if (ArchVersion == 5 || 5657 (ArchVersion == 6 && CPUProfile != "M") || 5658 ArchVersion > 6) 5659 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5660 5661 // ACLE 6.5.1 Hardware Floating Point 5662 if (HW_FP) 5663 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5664 5665 // ACLE predefines. 5666 Builder.defineMacro("__ARM_ACLE", "200"); 5667 5668 // FP16 support (we currently only support IEEE format). 5669 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5670 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5671 5672 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5673 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5674 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5675 5676 // Subtarget options. 5677 5678 // FIXME: It's more complicated than this and we don't really support 5679 // interworking. 5680 // Windows on ARM does not "support" interworking 5681 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5682 Builder.defineMacro("__THUMB_INTERWORK__"); 5683 5684 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5685 // Embedded targets on Darwin follow AAPCS, but not EABI. 5686 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5687 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5688 Builder.defineMacro("__ARM_EABI__"); 5689 Builder.defineMacro("__ARM_PCS", "1"); 5690 } 5691 5692 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5693 ABI == "aapcs16") 5694 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5695 5696 if (SoftFloat) 5697 Builder.defineMacro("__SOFTFP__"); 5698 5699 if (ArchKind == llvm::ARM::AK_XSCALE) 5700 Builder.defineMacro("__XSCALE__"); 5701 5702 if (isThumb()) { 5703 Builder.defineMacro("__THUMBEL__"); 5704 Builder.defineMacro("__thumb__"); 5705 if (supportsThumb2()) 5706 Builder.defineMacro("__thumb2__"); 5707 } 5708 5709 // ACLE 6.4.9 32-bit SIMD instructions 5710 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5711 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5712 5713 // ACLE 6.4.10 Hardware Integer Divide 5714 if (((HWDiv & HWDivThumb) && isThumb()) || 5715 ((HWDiv & HWDivARM) && !isThumb())) { 5716 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5717 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5718 } 5719 5720 // Note, this is always on in gcc, even though it doesn't make sense. 5721 Builder.defineMacro("__APCS_32__"); 5722 5723 if (FPUModeIsVFP((FPUMode) FPU)) { 5724 Builder.defineMacro("__VFP_FP__"); 5725 if (FPU & VFP2FPU) 5726 Builder.defineMacro("__ARM_VFPV2__"); 5727 if (FPU & VFP3FPU) 5728 Builder.defineMacro("__ARM_VFPV3__"); 5729 if (FPU & VFP4FPU) 5730 Builder.defineMacro("__ARM_VFPV4__"); 5731 if (FPU & FPARMV8) 5732 Builder.defineMacro("__ARM_FPV5__"); 5733 } 5734 5735 // This only gets set when Neon instructions are actually available, unlike 5736 // the VFP define, hence the soft float and arch check. This is subtly 5737 // different from gcc, we follow the intent which was that it should be set 5738 // when Neon instructions are actually available. 5739 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5740 Builder.defineMacro("__ARM_NEON", "1"); 5741 Builder.defineMacro("__ARM_NEON__"); 5742 // current AArch32 NEON implementations do not support double-precision 5743 // floating-point even when it is present in VFP. 5744 Builder.defineMacro("__ARM_NEON_FP", 5745 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5746 } 5747 5748 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5749 Opts.ShortWChar ? "2" : "4"); 5750 5751 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5752 Opts.ShortEnums ? "1" : "4"); 5753 5754 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5755 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5756 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5757 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5758 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5759 } 5760 5761 // ACLE 6.4.7 DSP instructions 5762 if (DSP) { 5763 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5764 } 5765 5766 // ACLE 6.4.8 Saturation instructions 5767 bool SAT = false; 5768 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5769 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5770 SAT = true; 5771 } 5772 5773 // ACLE 6.4.6 Q (saturation) flag 5774 if (DSP || SAT) 5775 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5776 5777 if (Opts.UnsafeFPMath) 5778 Builder.defineMacro("__ARM_FP_FAST", "1"); 5779 5780 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5781 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5782 } 5783 5784 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5785 return llvm::makeArrayRef(BuiltinInfo, 5786 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5787 } 5788 bool isCLZForZeroUndef() const override { return false; } 5789 BuiltinVaListKind getBuiltinVaListKind() const override { 5790 return IsAAPCS 5791 ? AAPCSABIBuiltinVaList 5792 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5793 : TargetInfo::VoidPtrBuiltinVaList); 5794 } 5795 ArrayRef<const char *> getGCCRegNames() const override; 5796 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5797 bool validateAsmConstraint(const char *&Name, 5798 TargetInfo::ConstraintInfo &Info) const override { 5799 switch (*Name) { 5800 default: break; 5801 case 'l': // r0-r7 5802 case 'h': // r8-r15 5803 case 't': // VFP Floating point register single precision 5804 case 'w': // VFP Floating point register double precision 5805 Info.setAllowsRegister(); 5806 return true; 5807 case 'I': 5808 case 'J': 5809 case 'K': 5810 case 'L': 5811 case 'M': 5812 // FIXME 5813 return true; 5814 case 'Q': // A memory address that is a single base register. 5815 Info.setAllowsMemory(); 5816 return true; 5817 case 'U': // a memory reference... 5818 switch (Name[1]) { 5819 case 'q': // ...ARMV4 ldrsb 5820 case 'v': // ...VFP load/store (reg+constant offset) 5821 case 'y': // ...iWMMXt load/store 5822 case 't': // address valid for load/store opaque types wider 5823 // than 128-bits 5824 case 'n': // valid address for Neon doubleword vector load/store 5825 case 'm': // valid address for Neon element and structure load/store 5826 case 's': // valid address for non-offset loads/stores of quad-word 5827 // values in four ARM registers 5828 Info.setAllowsMemory(); 5829 Name++; 5830 return true; 5831 } 5832 } 5833 return false; 5834 } 5835 std::string convertConstraint(const char *&Constraint) const override { 5836 std::string R; 5837 switch (*Constraint) { 5838 case 'U': // Two-character constraint; add "^" hint for later parsing. 5839 R = std::string("^") + std::string(Constraint, 2); 5840 Constraint++; 5841 break; 5842 case 'p': // 'p' should be translated to 'r' by default. 5843 R = std::string("r"); 5844 break; 5845 default: 5846 return std::string(1, *Constraint); 5847 } 5848 return R; 5849 } 5850 bool 5851 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5852 std::string &SuggestedModifier) const override { 5853 bool isOutput = (Constraint[0] == '='); 5854 bool isInOut = (Constraint[0] == '+'); 5855 5856 // Strip off constraint modifiers. 5857 while (Constraint[0] == '=' || 5858 Constraint[0] == '+' || 5859 Constraint[0] == '&') 5860 Constraint = Constraint.substr(1); 5861 5862 switch (Constraint[0]) { 5863 default: break; 5864 case 'r': { 5865 switch (Modifier) { 5866 default: 5867 return (isInOut || isOutput || Size <= 64); 5868 case 'q': 5869 // A register of size 32 cannot fit a vector type. 5870 return false; 5871 } 5872 } 5873 } 5874 5875 return true; 5876 } 5877 const char *getClobbers() const override { 5878 // FIXME: Is this really right? 5879 return ""; 5880 } 5881 5882 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5883 switch (CC) { 5884 case CC_AAPCS: 5885 case CC_AAPCS_VFP: 5886 case CC_Swift: 5887 case CC_OpenCLKernel: 5888 return CCCR_OK; 5889 default: 5890 return CCCR_Warning; 5891 } 5892 } 5893 5894 int getEHDataRegisterNumber(unsigned RegNo) const override { 5895 if (RegNo == 0) return 0; 5896 if (RegNo == 1) return 1; 5897 return -1; 5898 } 5899 5900 bool hasSjLjLowering() const override { 5901 return true; 5902 } 5903 }; 5904 5905 bool ARMTargetInfo::setFPMath(StringRef Name) { 5906 if (Name == "neon") { 5907 FPMath = FP_Neon; 5908 return true; 5909 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5910 Name == "vfp4") { 5911 FPMath = FP_VFP; 5912 return true; 5913 } 5914 return false; 5915 } 5916 5917 const char * const ARMTargetInfo::GCCRegNames[] = { 5918 // Integer registers 5919 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5920 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5921 5922 // Float registers 5923 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5924 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5925 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5926 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5927 5928 // Double registers 5929 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5930 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5931 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5932 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5933 5934 // Quad registers 5935 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5936 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5937 }; 5938 5939 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5940 return llvm::makeArrayRef(GCCRegNames); 5941 } 5942 5943 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5944 { { "a1" }, "r0" }, 5945 { { "a2" }, "r1" }, 5946 { { "a3" }, "r2" }, 5947 { { "a4" }, "r3" }, 5948 { { "v1" }, "r4" }, 5949 { { "v2" }, "r5" }, 5950 { { "v3" }, "r6" }, 5951 { { "v4" }, "r7" }, 5952 { { "v5" }, "r8" }, 5953 { { "v6", "rfp" }, "r9" }, 5954 { { "sl" }, "r10" }, 5955 { { "fp" }, "r11" }, 5956 { { "ip" }, "r12" }, 5957 { { "r13" }, "sp" }, 5958 { { "r14" }, "lr" }, 5959 { { "r15" }, "pc" }, 5960 // The S, D and Q registers overlap, but aren't really aliases; we 5961 // don't want to substitute one of these for a different-sized one. 5962 }; 5963 5964 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5965 return llvm::makeArrayRef(GCCRegAliases); 5966 } 5967 5968 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5969 #define BUILTIN(ID, TYPE, ATTRS) \ 5970 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5971 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5972 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5973 #include "clang/Basic/BuiltinsNEON.def" 5974 5975 #define BUILTIN(ID, TYPE, ATTRS) \ 5976 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5977 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5978 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5979 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5980 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5981 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5982 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5983 #include "clang/Basic/BuiltinsARM.def" 5984 }; 5985 5986 class ARMleTargetInfo : public ARMTargetInfo { 5987 public: 5988 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5989 : ARMTargetInfo(Triple, Opts) {} 5990 void getTargetDefines(const LangOptions &Opts, 5991 MacroBuilder &Builder) const override { 5992 Builder.defineMacro("__ARMEL__"); 5993 ARMTargetInfo::getTargetDefines(Opts, Builder); 5994 } 5995 }; 5996 5997 class ARMbeTargetInfo : public ARMTargetInfo { 5998 public: 5999 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6000 : ARMTargetInfo(Triple, Opts) {} 6001 void getTargetDefines(const LangOptions &Opts, 6002 MacroBuilder &Builder) const override { 6003 Builder.defineMacro("__ARMEB__"); 6004 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6005 ARMTargetInfo::getTargetDefines(Opts, Builder); 6006 } 6007 }; 6008 6009 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 6010 const llvm::Triple Triple; 6011 public: 6012 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6013 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 6014 WCharType = UnsignedShort; 6015 SizeType = UnsignedInt; 6016 } 6017 void getVisualStudioDefines(const LangOptions &Opts, 6018 MacroBuilder &Builder) const { 6019 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 6020 6021 // FIXME: this is invalid for WindowsCE 6022 Builder.defineMacro("_M_ARM_NT", "1"); 6023 Builder.defineMacro("_M_ARMT", "_M_ARM"); 6024 Builder.defineMacro("_M_THUMB", "_M_ARM"); 6025 6026 assert((Triple.getArch() == llvm::Triple::arm || 6027 Triple.getArch() == llvm::Triple::thumb) && 6028 "invalid architecture for Windows ARM target info"); 6029 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 6030 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6031 6032 // TODO map the complete set of values 6033 // 31: VFPv3 40: VFPv4 6034 Builder.defineMacro("_M_ARM_FP", "31"); 6035 } 6036 BuiltinVaListKind getBuiltinVaListKind() const override { 6037 return TargetInfo::CharPtrBuiltinVaList; 6038 } 6039 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6040 switch (CC) { 6041 case CC_X86StdCall: 6042 case CC_X86ThisCall: 6043 case CC_X86FastCall: 6044 case CC_X86VectorCall: 6045 return CCCR_Ignore; 6046 case CC_C: 6047 case CC_OpenCLKernel: 6048 return CCCR_OK; 6049 default: 6050 return CCCR_Warning; 6051 } 6052 } 6053 }; 6054 6055 // Windows ARM + Itanium C++ ABI Target 6056 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6057 public: 6058 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6059 const TargetOptions &Opts) 6060 : WindowsARMTargetInfo(Triple, Opts) { 6061 TheCXXABI.set(TargetCXXABI::GenericARM); 6062 } 6063 6064 void getTargetDefines(const LangOptions &Opts, 6065 MacroBuilder &Builder) const override { 6066 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6067 6068 if (Opts.MSVCCompat) 6069 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6070 } 6071 }; 6072 6073 // Windows ARM, MS (C++) ABI 6074 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6075 public: 6076 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6077 const TargetOptions &Opts) 6078 : WindowsARMTargetInfo(Triple, Opts) { 6079 TheCXXABI.set(TargetCXXABI::Microsoft); 6080 } 6081 6082 void getTargetDefines(const LangOptions &Opts, 6083 MacroBuilder &Builder) const override { 6084 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6085 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6086 } 6087 }; 6088 6089 // ARM MinGW target 6090 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6091 public: 6092 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6093 : WindowsARMTargetInfo(Triple, Opts) { 6094 TheCXXABI.set(TargetCXXABI::GenericARM); 6095 } 6096 6097 void getTargetDefines(const LangOptions &Opts, 6098 MacroBuilder &Builder) const override { 6099 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6100 DefineStd(Builder, "WIN32", Opts); 6101 DefineStd(Builder, "WINNT", Opts); 6102 Builder.defineMacro("_ARM_"); 6103 addMinGWDefines(Opts, Builder); 6104 } 6105 }; 6106 6107 // ARM Cygwin target 6108 class CygwinARMTargetInfo : public ARMleTargetInfo { 6109 public: 6110 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6111 : ARMleTargetInfo(Triple, Opts) { 6112 TLSSupported = false; 6113 WCharType = UnsignedShort; 6114 DoubleAlign = LongLongAlign = 64; 6115 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6116 } 6117 void getTargetDefines(const LangOptions &Opts, 6118 MacroBuilder &Builder) const override { 6119 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6120 Builder.defineMacro("_ARM_"); 6121 Builder.defineMacro("__CYGWIN__"); 6122 Builder.defineMacro("__CYGWIN32__"); 6123 DefineStd(Builder, "unix", Opts); 6124 if (Opts.CPlusPlus) 6125 Builder.defineMacro("_GNU_SOURCE"); 6126 } 6127 }; 6128 6129 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6130 protected: 6131 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6132 MacroBuilder &Builder) const override { 6133 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6134 } 6135 6136 public: 6137 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6138 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6139 HasAlignMac68kSupport = true; 6140 // iOS always has 64-bit atomic instructions. 6141 // FIXME: This should be based off of the target features in 6142 // ARMleTargetInfo. 6143 MaxAtomicInlineWidth = 64; 6144 6145 if (Triple.isWatchABI()) { 6146 // Darwin on iOS uses a variant of the ARM C++ ABI. 6147 TheCXXABI.set(TargetCXXABI::WatchOS); 6148 6149 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6150 // size_t is long, it's a bit weird for it to be int. 6151 PtrDiffType = SignedLong; 6152 6153 // BOOL should be a real boolean on the new ABI 6154 UseSignedCharForObjCBool = false; 6155 } else 6156 TheCXXABI.set(TargetCXXABI::iOS); 6157 } 6158 }; 6159 6160 class AArch64TargetInfo : public TargetInfo { 6161 virtual void setDataLayout() = 0; 6162 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6163 static const char *const GCCRegNames[]; 6164 6165 enum FPUModeEnum { 6166 FPUMode, 6167 NeonMode 6168 }; 6169 6170 unsigned FPU; 6171 unsigned CRC; 6172 unsigned Crypto; 6173 unsigned Unaligned; 6174 unsigned V8_1A; 6175 unsigned V8_2A; 6176 unsigned HasFullFP16; 6177 6178 static const Builtin::Info BuiltinInfo[]; 6179 6180 std::string ABI; 6181 6182 public: 6183 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6184 : TargetInfo(Triple), ABI("aapcs") { 6185 if (getTriple().getOS() == llvm::Triple::NetBSD || 6186 getTriple().getOS() == llvm::Triple::OpenBSD) { 6187 WCharType = SignedInt; 6188 6189 // NetBSD apparently prefers consistency across ARM targets to consistency 6190 // across 64-bit targets. 6191 Int64Type = SignedLongLong; 6192 IntMaxType = SignedLongLong; 6193 } else { 6194 WCharType = UnsignedInt; 6195 Int64Type = SignedLong; 6196 IntMaxType = SignedLong; 6197 } 6198 6199 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6200 MaxVectorAlign = 128; 6201 MaxAtomicInlineWidth = 128; 6202 MaxAtomicPromoteWidth = 128; 6203 6204 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6205 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6206 6207 // {} in inline assembly are neon specifiers, not assembly variant 6208 // specifiers. 6209 NoAsmVariants = true; 6210 6211 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6212 // contributes to the alignment of the containing aggregate in the same way 6213 // a plain (non bit-field) member of that type would, without exception for 6214 // zero-sized or anonymous bit-fields." 6215 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6216 UseZeroLengthBitfieldAlignment = true; 6217 6218 // AArch64 targets default to using the ARM C++ ABI. 6219 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6220 6221 if (Triple.getOS() == llvm::Triple::Linux) 6222 this->MCountName = "\01_mcount"; 6223 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6224 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6225 } 6226 6227 StringRef getABI() const override { return ABI; } 6228 bool setABI(const std::string &Name) override { 6229 if (Name != "aapcs" && Name != "darwinpcs") 6230 return false; 6231 6232 ABI = Name; 6233 return true; 6234 } 6235 6236 bool setCPU(const std::string &Name) override { 6237 return Name == "generic" || 6238 llvm::AArch64::parseCPUArch(Name) != 6239 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6240 } 6241 6242 void getTargetDefines(const LangOptions &Opts, 6243 MacroBuilder &Builder) const override { 6244 // Target identification. 6245 Builder.defineMacro("__aarch64__"); 6246 // For bare-metal none-eabi. 6247 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6248 (getTriple().getEnvironment() == llvm::Triple::EABI || 6249 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6250 Builder.defineMacro("__ELF__"); 6251 6252 // Target properties. 6253 Builder.defineMacro("_LP64"); 6254 Builder.defineMacro("__LP64__"); 6255 6256 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6257 Builder.defineMacro("__ARM_ACLE", "200"); 6258 Builder.defineMacro("__ARM_ARCH", "8"); 6259 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6260 6261 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6262 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6263 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6264 6265 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6266 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6267 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6268 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6269 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6270 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6271 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6272 6273 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6274 6275 // 0xe implies support for half, single and double precision operations. 6276 Builder.defineMacro("__ARM_FP", "0xE"); 6277 6278 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6279 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6280 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6281 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6282 6283 if (Opts.UnsafeFPMath) 6284 Builder.defineMacro("__ARM_FP_FAST", "1"); 6285 6286 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6287 6288 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6289 Opts.ShortEnums ? "1" : "4"); 6290 6291 if (FPU == NeonMode) { 6292 Builder.defineMacro("__ARM_NEON", "1"); 6293 // 64-bit NEON supports half, single and double precision operations. 6294 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6295 } 6296 6297 if (CRC) 6298 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6299 6300 if (Crypto) 6301 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6302 6303 if (Unaligned) 6304 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6305 6306 if (V8_1A) 6307 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6308 if (V8_2A && FPU == NeonMode && HasFullFP16) 6309 Builder.defineMacro("__ARM_FEATURE_FP16_VECTOR_ARITHMETIC", "1"); 6310 6311 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6312 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6313 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6314 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6315 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6316 } 6317 6318 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6319 return llvm::makeArrayRef(BuiltinInfo, 6320 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6321 } 6322 6323 bool hasFeature(StringRef Feature) const override { 6324 return Feature == "aarch64" || 6325 Feature == "arm64" || 6326 Feature == "arm" || 6327 (Feature == "neon" && FPU == NeonMode); 6328 } 6329 6330 bool handleTargetFeatures(std::vector<std::string> &Features, 6331 DiagnosticsEngine &Diags) override { 6332 FPU = FPUMode; 6333 CRC = 0; 6334 Crypto = 0; 6335 Unaligned = 1; 6336 V8_1A = 0; 6337 V8_2A = 0; 6338 HasFullFP16 = 0; 6339 6340 for (const auto &Feature : Features) { 6341 if (Feature == "+neon") 6342 FPU = NeonMode; 6343 if (Feature == "+crc") 6344 CRC = 1; 6345 if (Feature == "+crypto") 6346 Crypto = 1; 6347 if (Feature == "+strict-align") 6348 Unaligned = 0; 6349 if (Feature == "+v8.1a") 6350 V8_1A = 1; 6351 if (Feature == "+v8.2a") 6352 V8_2A = 1; 6353 if (Feature == "+fullfp16") 6354 HasFullFP16 = 1; 6355 } 6356 6357 setDataLayout(); 6358 6359 return true; 6360 } 6361 6362 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6363 switch (CC) { 6364 case CC_C: 6365 case CC_Swift: 6366 case CC_PreserveMost: 6367 case CC_PreserveAll: 6368 case CC_OpenCLKernel: 6369 return CCCR_OK; 6370 default: 6371 return CCCR_Warning; 6372 } 6373 } 6374 6375 bool isCLZForZeroUndef() const override { return false; } 6376 6377 BuiltinVaListKind getBuiltinVaListKind() const override { 6378 return TargetInfo::AArch64ABIBuiltinVaList; 6379 } 6380 6381 ArrayRef<const char *> getGCCRegNames() const override; 6382 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6383 6384 bool validateAsmConstraint(const char *&Name, 6385 TargetInfo::ConstraintInfo &Info) const override { 6386 switch (*Name) { 6387 default: 6388 return false; 6389 case 'w': // Floating point and SIMD registers (V0-V31) 6390 Info.setAllowsRegister(); 6391 return true; 6392 case 'I': // Constant that can be used with an ADD instruction 6393 case 'J': // Constant that can be used with a SUB instruction 6394 case 'K': // Constant that can be used with a 32-bit logical instruction 6395 case 'L': // Constant that can be used with a 64-bit logical instruction 6396 case 'M': // Constant that can be used as a 32-bit MOV immediate 6397 case 'N': // Constant that can be used as a 64-bit MOV immediate 6398 case 'Y': // Floating point constant zero 6399 case 'Z': // Integer constant zero 6400 return true; 6401 case 'Q': // A memory reference with base register and no offset 6402 Info.setAllowsMemory(); 6403 return true; 6404 case 'S': // A symbolic address 6405 Info.setAllowsRegister(); 6406 return true; 6407 case 'U': 6408 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6409 // Utf: A memory address suitable for ldp/stp in TF mode. 6410 // Usa: An absolute symbolic address. 6411 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6412 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6413 case 'z': // Zero register, wzr or xzr 6414 Info.setAllowsRegister(); 6415 return true; 6416 case 'x': // Floating point and SIMD registers (V0-V15) 6417 Info.setAllowsRegister(); 6418 return true; 6419 } 6420 return false; 6421 } 6422 6423 bool 6424 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6425 std::string &SuggestedModifier) const override { 6426 // Strip off constraint modifiers. 6427 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6428 Constraint = Constraint.substr(1); 6429 6430 switch (Constraint[0]) { 6431 default: 6432 return true; 6433 case 'z': 6434 case 'r': { 6435 switch (Modifier) { 6436 case 'x': 6437 case 'w': 6438 // For now assume that the person knows what they're 6439 // doing with the modifier. 6440 return true; 6441 default: 6442 // By default an 'r' constraint will be in the 'x' 6443 // registers. 6444 if (Size == 64) 6445 return true; 6446 6447 SuggestedModifier = "w"; 6448 return false; 6449 } 6450 } 6451 } 6452 } 6453 6454 const char *getClobbers() const override { return ""; } 6455 6456 int getEHDataRegisterNumber(unsigned RegNo) const override { 6457 if (RegNo == 0) 6458 return 0; 6459 if (RegNo == 1) 6460 return 1; 6461 return -1; 6462 } 6463 }; 6464 6465 const char *const AArch64TargetInfo::GCCRegNames[] = { 6466 // 32-bit Integer registers 6467 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6468 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6469 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6470 6471 // 64-bit Integer registers 6472 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6473 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6474 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6475 6476 // 32-bit floating point regsisters 6477 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6478 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6479 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6480 6481 // 64-bit floating point regsisters 6482 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6483 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6484 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6485 6486 // Vector registers 6487 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6488 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6489 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6490 }; 6491 6492 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6493 return llvm::makeArrayRef(GCCRegNames); 6494 } 6495 6496 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6497 { { "w31" }, "wsp" }, 6498 { { "x29" }, "fp" }, 6499 { { "x30" }, "lr" }, 6500 { { "x31" }, "sp" }, 6501 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6502 // don't want to substitute one of these for a different-sized one. 6503 }; 6504 6505 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6506 return llvm::makeArrayRef(GCCRegAliases); 6507 } 6508 6509 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6510 #define BUILTIN(ID, TYPE, ATTRS) \ 6511 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6512 #include "clang/Basic/BuiltinsNEON.def" 6513 6514 #define BUILTIN(ID, TYPE, ATTRS) \ 6515 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6516 #include "clang/Basic/BuiltinsAArch64.def" 6517 }; 6518 6519 class AArch64leTargetInfo : public AArch64TargetInfo { 6520 void setDataLayout() override { 6521 if (getTriple().isOSBinFormatMachO()) 6522 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6523 else 6524 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6525 } 6526 6527 public: 6528 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6529 : AArch64TargetInfo(Triple, Opts) { 6530 } 6531 void getTargetDefines(const LangOptions &Opts, 6532 MacroBuilder &Builder) const override { 6533 Builder.defineMacro("__AARCH64EL__"); 6534 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6535 } 6536 }; 6537 6538 class AArch64beTargetInfo : public AArch64TargetInfo { 6539 void setDataLayout() override { 6540 assert(!getTriple().isOSBinFormatMachO()); 6541 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6542 } 6543 6544 public: 6545 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6546 : AArch64TargetInfo(Triple, Opts) {} 6547 void getTargetDefines(const LangOptions &Opts, 6548 MacroBuilder &Builder) const override { 6549 Builder.defineMacro("__AARCH64EB__"); 6550 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6551 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6552 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6553 } 6554 }; 6555 6556 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6557 protected: 6558 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6559 MacroBuilder &Builder) const override { 6560 Builder.defineMacro("__AARCH64_SIMD__"); 6561 Builder.defineMacro("__ARM64_ARCH_8__"); 6562 Builder.defineMacro("__ARM_NEON__"); 6563 Builder.defineMacro("__LITTLE_ENDIAN__"); 6564 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6565 Builder.defineMacro("__arm64", "1"); 6566 Builder.defineMacro("__arm64__", "1"); 6567 6568 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6569 } 6570 6571 public: 6572 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6573 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6574 Int64Type = SignedLongLong; 6575 WCharType = SignedInt; 6576 UseSignedCharForObjCBool = false; 6577 6578 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6579 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6580 6581 TheCXXABI.set(TargetCXXABI::iOS64); 6582 } 6583 6584 BuiltinVaListKind getBuiltinVaListKind() const override { 6585 return TargetInfo::CharPtrBuiltinVaList; 6586 } 6587 }; 6588 6589 // Hexagon abstract base class 6590 class HexagonTargetInfo : public TargetInfo { 6591 static const Builtin::Info BuiltinInfo[]; 6592 static const char * const GCCRegNames[]; 6593 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6594 std::string CPU; 6595 bool HasHVX, HasHVXDouble; 6596 bool UseLongCalls; 6597 6598 public: 6599 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6600 : TargetInfo(Triple) { 6601 // Specify the vector alignment explicitly. For v512x1, the calculated 6602 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6603 // the required minimum of 64 bytes. 6604 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6605 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6606 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6607 SizeType = UnsignedInt; 6608 PtrDiffType = SignedInt; 6609 IntPtrType = SignedInt; 6610 6611 // {} in inline assembly are packet specifiers, not assembly variant 6612 // specifiers. 6613 NoAsmVariants = true; 6614 6615 LargeArrayMinWidth = 64; 6616 LargeArrayAlign = 64; 6617 UseBitFieldTypeAlignment = true; 6618 ZeroLengthBitfieldBoundary = 32; 6619 HasHVX = HasHVXDouble = false; 6620 UseLongCalls = false; 6621 } 6622 6623 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6624 return llvm::makeArrayRef(BuiltinInfo, 6625 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6626 } 6627 6628 bool validateAsmConstraint(const char *&Name, 6629 TargetInfo::ConstraintInfo &Info) const override { 6630 switch (*Name) { 6631 case 'v': 6632 case 'q': 6633 if (HasHVX) { 6634 Info.setAllowsRegister(); 6635 return true; 6636 } 6637 break; 6638 case 's': 6639 // Relocatable constant. 6640 return true; 6641 } 6642 return false; 6643 } 6644 6645 void getTargetDefines(const LangOptions &Opts, 6646 MacroBuilder &Builder) const override; 6647 6648 bool isCLZForZeroUndef() const override { return false; } 6649 6650 bool hasFeature(StringRef Feature) const override { 6651 return llvm::StringSwitch<bool>(Feature) 6652 .Case("hexagon", true) 6653 .Case("hvx", HasHVX) 6654 .Case("hvx-double", HasHVXDouble) 6655 .Case("long-calls", UseLongCalls) 6656 .Default(false); 6657 } 6658 6659 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6660 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6661 const override; 6662 6663 bool handleTargetFeatures(std::vector<std::string> &Features, 6664 DiagnosticsEngine &Diags) override; 6665 6666 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6667 bool Enabled) const override; 6668 6669 BuiltinVaListKind getBuiltinVaListKind() const override { 6670 return TargetInfo::CharPtrBuiltinVaList; 6671 } 6672 ArrayRef<const char *> getGCCRegNames() const override; 6673 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6674 const char *getClobbers() const override { 6675 return ""; 6676 } 6677 6678 static const char *getHexagonCPUSuffix(StringRef Name) { 6679 return llvm::StringSwitch<const char*>(Name) 6680 .Case("hexagonv4", "4") 6681 .Case("hexagonv5", "5") 6682 .Case("hexagonv55", "55") 6683 .Case("hexagonv60", "60") 6684 .Case("hexagonv62", "62") 6685 .Default(nullptr); 6686 } 6687 6688 bool setCPU(const std::string &Name) override { 6689 if (!getHexagonCPUSuffix(Name)) 6690 return false; 6691 CPU = Name; 6692 return true; 6693 } 6694 6695 int getEHDataRegisterNumber(unsigned RegNo) const override { 6696 return RegNo < 2 ? RegNo : -1; 6697 } 6698 }; 6699 6700 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6701 MacroBuilder &Builder) const { 6702 Builder.defineMacro("__qdsp6__", "1"); 6703 Builder.defineMacro("__hexagon__", "1"); 6704 6705 if (CPU == "hexagonv4") { 6706 Builder.defineMacro("__HEXAGON_V4__"); 6707 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6708 if (Opts.HexagonQdsp6Compat) { 6709 Builder.defineMacro("__QDSP6_V4__"); 6710 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6711 } 6712 } else if (CPU == "hexagonv5") { 6713 Builder.defineMacro("__HEXAGON_V5__"); 6714 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6715 if(Opts.HexagonQdsp6Compat) { 6716 Builder.defineMacro("__QDSP6_V5__"); 6717 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6718 } 6719 } else if (CPU == "hexagonv55") { 6720 Builder.defineMacro("__HEXAGON_V55__"); 6721 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6722 Builder.defineMacro("__QDSP6_V55__"); 6723 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6724 } else if (CPU == "hexagonv60") { 6725 Builder.defineMacro("__HEXAGON_V60__"); 6726 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6727 Builder.defineMacro("__QDSP6_V60__"); 6728 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6729 } else if (CPU == "hexagonv62") { 6730 Builder.defineMacro("__HEXAGON_V62__"); 6731 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6732 } 6733 6734 if (hasFeature("hvx")) { 6735 Builder.defineMacro("__HVX__"); 6736 if (hasFeature("hvx-double")) 6737 Builder.defineMacro("__HVXDBL__"); 6738 } 6739 } 6740 6741 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6742 DiagnosticsEngine &Diags, StringRef CPU, 6743 const std::vector<std::string> &FeaturesVec) const { 6744 // Default for v60: -hvx, -hvx-double. 6745 Features["hvx"] = false; 6746 Features["hvx-double"] = false; 6747 Features["long-calls"] = false; 6748 6749 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6750 } 6751 6752 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6753 DiagnosticsEngine &Diags) { 6754 for (auto &F : Features) { 6755 if (F == "+hvx") 6756 HasHVX = true; 6757 else if (F == "-hvx") 6758 HasHVX = HasHVXDouble = false; 6759 else if (F == "+hvx-double") 6760 HasHVX = HasHVXDouble = true; 6761 else if (F == "-hvx-double") 6762 HasHVXDouble = false; 6763 6764 if (F == "+long-calls") 6765 UseLongCalls = true; 6766 else if (F == "-long-calls") 6767 UseLongCalls = false; 6768 } 6769 return true; 6770 } 6771 6772 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6773 StringRef Name, bool Enabled) const { 6774 if (Enabled) { 6775 if (Name == "hvx-double") 6776 Features["hvx"] = true; 6777 } else { 6778 if (Name == "hvx") 6779 Features["hvx-double"] = false; 6780 } 6781 Features[Name] = Enabled; 6782 } 6783 6784 const char *const HexagonTargetInfo::GCCRegNames[] = { 6785 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6786 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6787 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6788 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6789 "p0", "p1", "p2", "p3", 6790 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6791 }; 6792 6793 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6794 return llvm::makeArrayRef(GCCRegNames); 6795 } 6796 6797 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6798 { { "sp" }, "r29" }, 6799 { { "fp" }, "r30" }, 6800 { { "lr" }, "r31" }, 6801 }; 6802 6803 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6804 return llvm::makeArrayRef(GCCRegAliases); 6805 } 6806 6807 6808 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6809 #define BUILTIN(ID, TYPE, ATTRS) \ 6810 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6811 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6812 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6813 #include "clang/Basic/BuiltinsHexagon.def" 6814 }; 6815 6816 class LanaiTargetInfo : public TargetInfo { 6817 // Class for Lanai (32-bit). 6818 // The CPU profiles supported by the Lanai backend 6819 enum CPUKind { 6820 CK_NONE, 6821 CK_V11, 6822 } CPU; 6823 6824 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6825 static const char *const GCCRegNames[]; 6826 6827 public: 6828 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6829 : TargetInfo(Triple) { 6830 // Description string has to be kept in sync with backend. 6831 resetDataLayout("E" // Big endian 6832 "-m:e" // ELF name manging 6833 "-p:32:32" // 32 bit pointers, 32 bit aligned 6834 "-i64:64" // 64 bit integers, 64 bit aligned 6835 "-a:0:32" // 32 bit alignment of objects of aggregate type 6836 "-n32" // 32 bit native integer width 6837 "-S64" // 64 bit natural stack alignment 6838 ); 6839 6840 // Setting RegParmMax equal to what mregparm was set to in the old 6841 // toolchain 6842 RegParmMax = 4; 6843 6844 // Set the default CPU to V11 6845 CPU = CK_V11; 6846 6847 // Temporary approach to make everything at least word-aligned and allow for 6848 // safely casting between pointers with different alignment requirements. 6849 // TODO: Remove this when there are no more cast align warnings on the 6850 // firmware. 6851 MinGlobalAlign = 32; 6852 } 6853 6854 void getTargetDefines(const LangOptions &Opts, 6855 MacroBuilder &Builder) const override { 6856 // Define __lanai__ when building for target lanai. 6857 Builder.defineMacro("__lanai__"); 6858 6859 // Set define for the CPU specified. 6860 switch (CPU) { 6861 case CK_V11: 6862 Builder.defineMacro("__LANAI_V11__"); 6863 break; 6864 case CK_NONE: 6865 llvm_unreachable("Unhandled target CPU"); 6866 } 6867 } 6868 6869 bool setCPU(const std::string &Name) override { 6870 CPU = llvm::StringSwitch<CPUKind>(Name) 6871 .Case("v11", CK_V11) 6872 .Default(CK_NONE); 6873 6874 return CPU != CK_NONE; 6875 } 6876 6877 bool hasFeature(StringRef Feature) const override { 6878 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6879 } 6880 6881 ArrayRef<const char *> getGCCRegNames() const override; 6882 6883 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6884 6885 BuiltinVaListKind getBuiltinVaListKind() const override { 6886 return TargetInfo::VoidPtrBuiltinVaList; 6887 } 6888 6889 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6890 6891 bool validateAsmConstraint(const char *&Name, 6892 TargetInfo::ConstraintInfo &info) const override { 6893 return false; 6894 } 6895 6896 const char *getClobbers() const override { return ""; } 6897 }; 6898 6899 const char *const LanaiTargetInfo::GCCRegNames[] = { 6900 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6901 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6902 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6903 6904 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6905 return llvm::makeArrayRef(GCCRegNames); 6906 } 6907 6908 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6909 {{"pc"}, "r2"}, 6910 {{"sp"}, "r4"}, 6911 {{"fp"}, "r5"}, 6912 {{"rv"}, "r8"}, 6913 {{"rr1"}, "r10"}, 6914 {{"rr2"}, "r11"}, 6915 {{"rca"}, "r15"}, 6916 }; 6917 6918 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6919 return llvm::makeArrayRef(GCCRegAliases); 6920 } 6921 6922 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6923 class SparcTargetInfo : public TargetInfo { 6924 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6925 static const char * const GCCRegNames[]; 6926 bool SoftFloat; 6927 public: 6928 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6929 : TargetInfo(Triple), SoftFloat(false) {} 6930 6931 int getEHDataRegisterNumber(unsigned RegNo) const override { 6932 if (RegNo == 0) return 24; 6933 if (RegNo == 1) return 25; 6934 return -1; 6935 } 6936 6937 bool handleTargetFeatures(std::vector<std::string> &Features, 6938 DiagnosticsEngine &Diags) override { 6939 // Check if software floating point is enabled 6940 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6941 if (Feature != Features.end()) { 6942 SoftFloat = true; 6943 } 6944 return true; 6945 } 6946 void getTargetDefines(const LangOptions &Opts, 6947 MacroBuilder &Builder) const override { 6948 DefineStd(Builder, "sparc", Opts); 6949 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6950 6951 if (SoftFloat) 6952 Builder.defineMacro("SOFT_FLOAT", "1"); 6953 } 6954 6955 bool hasFeature(StringRef Feature) const override { 6956 return llvm::StringSwitch<bool>(Feature) 6957 .Case("softfloat", SoftFloat) 6958 .Case("sparc", true) 6959 .Default(false); 6960 } 6961 6962 bool hasSjLjLowering() const override { 6963 return true; 6964 } 6965 6966 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6967 // FIXME: Implement! 6968 return None; 6969 } 6970 BuiltinVaListKind getBuiltinVaListKind() const override { 6971 return TargetInfo::VoidPtrBuiltinVaList; 6972 } 6973 ArrayRef<const char *> getGCCRegNames() const override; 6974 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6975 bool validateAsmConstraint(const char *&Name, 6976 TargetInfo::ConstraintInfo &info) const override { 6977 // FIXME: Implement! 6978 switch (*Name) { 6979 case 'I': // Signed 13-bit constant 6980 case 'J': // Zero 6981 case 'K': // 32-bit constant with the low 12 bits clear 6982 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6983 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6984 case 'N': // Same as 'K' but zext (required for SIMode) 6985 case 'O': // The constant 4096 6986 return true; 6987 6988 case 'f': 6989 case 'e': 6990 info.setAllowsRegister(); 6991 return true; 6992 } 6993 return false; 6994 } 6995 const char *getClobbers() const override { 6996 // FIXME: Implement! 6997 return ""; 6998 } 6999 7000 // No Sparc V7 for now, the backend doesn't support it anyway. 7001 enum CPUKind { 7002 CK_GENERIC, 7003 CK_V8, 7004 CK_SUPERSPARC, 7005 CK_SPARCLITE, 7006 CK_F934, 7007 CK_HYPERSPARC, 7008 CK_SPARCLITE86X, 7009 CK_SPARCLET, 7010 CK_TSC701, 7011 CK_V9, 7012 CK_ULTRASPARC, 7013 CK_ULTRASPARC3, 7014 CK_NIAGARA, 7015 CK_NIAGARA2, 7016 CK_NIAGARA3, 7017 CK_NIAGARA4, 7018 CK_MYRIAD2100, 7019 CK_MYRIAD2150, 7020 CK_MYRIAD2450, 7021 CK_LEON2, 7022 CK_LEON2_AT697E, 7023 CK_LEON2_AT697F, 7024 CK_LEON3, 7025 CK_LEON3_UT699, 7026 CK_LEON3_GR712RC, 7027 CK_LEON4, 7028 CK_LEON4_GR740 7029 } CPU = CK_GENERIC; 7030 7031 enum CPUGeneration { 7032 CG_V8, 7033 CG_V9, 7034 }; 7035 7036 CPUGeneration getCPUGeneration(CPUKind Kind) const { 7037 switch (Kind) { 7038 case CK_GENERIC: 7039 case CK_V8: 7040 case CK_SUPERSPARC: 7041 case CK_SPARCLITE: 7042 case CK_F934: 7043 case CK_HYPERSPARC: 7044 case CK_SPARCLITE86X: 7045 case CK_SPARCLET: 7046 case CK_TSC701: 7047 case CK_MYRIAD2100: 7048 case CK_MYRIAD2150: 7049 case CK_MYRIAD2450: 7050 case CK_LEON2: 7051 case CK_LEON2_AT697E: 7052 case CK_LEON2_AT697F: 7053 case CK_LEON3: 7054 case CK_LEON3_UT699: 7055 case CK_LEON3_GR712RC: 7056 case CK_LEON4: 7057 case CK_LEON4_GR740: 7058 return CG_V8; 7059 case CK_V9: 7060 case CK_ULTRASPARC: 7061 case CK_ULTRASPARC3: 7062 case CK_NIAGARA: 7063 case CK_NIAGARA2: 7064 case CK_NIAGARA3: 7065 case CK_NIAGARA4: 7066 return CG_V9; 7067 } 7068 llvm_unreachable("Unexpected CPU kind"); 7069 } 7070 7071 CPUKind getCPUKind(StringRef Name) const { 7072 return llvm::StringSwitch<CPUKind>(Name) 7073 .Case("v8", CK_V8) 7074 .Case("supersparc", CK_SUPERSPARC) 7075 .Case("sparclite", CK_SPARCLITE) 7076 .Case("f934", CK_F934) 7077 .Case("hypersparc", CK_HYPERSPARC) 7078 .Case("sparclite86x", CK_SPARCLITE86X) 7079 .Case("sparclet", CK_SPARCLET) 7080 .Case("tsc701", CK_TSC701) 7081 .Case("v9", CK_V9) 7082 .Case("ultrasparc", CK_ULTRASPARC) 7083 .Case("ultrasparc3", CK_ULTRASPARC3) 7084 .Case("niagara", CK_NIAGARA) 7085 .Case("niagara2", CK_NIAGARA2) 7086 .Case("niagara3", CK_NIAGARA3) 7087 .Case("niagara4", CK_NIAGARA4) 7088 .Case("ma2100", CK_MYRIAD2100) 7089 .Case("ma2150", CK_MYRIAD2150) 7090 .Case("ma2450", CK_MYRIAD2450) 7091 // FIXME: the myriad2[.n] spellings are obsolete, 7092 // but a grace period is needed to allow updating dependent builds. 7093 .Case("myriad2", CK_MYRIAD2100) 7094 .Case("myriad2.1", CK_MYRIAD2100) 7095 .Case("myriad2.2", CK_MYRIAD2150) 7096 .Case("leon2", CK_LEON2) 7097 .Case("at697e", CK_LEON2_AT697E) 7098 .Case("at697f", CK_LEON2_AT697F) 7099 .Case("leon3", CK_LEON3) 7100 .Case("ut699", CK_LEON3_UT699) 7101 .Case("gr712rc", CK_LEON3_GR712RC) 7102 .Case("leon4", CK_LEON4) 7103 .Case("gr740", CK_LEON4_GR740) 7104 .Default(CK_GENERIC); 7105 } 7106 7107 bool setCPU(const std::string &Name) override { 7108 CPU = getCPUKind(Name); 7109 return CPU != CK_GENERIC; 7110 } 7111 }; 7112 7113 const char * const SparcTargetInfo::GCCRegNames[] = { 7114 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7115 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7116 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7117 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7118 }; 7119 7120 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7121 return llvm::makeArrayRef(GCCRegNames); 7122 } 7123 7124 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7125 { { "g0" }, "r0" }, 7126 { { "g1" }, "r1" }, 7127 { { "g2" }, "r2" }, 7128 { { "g3" }, "r3" }, 7129 { { "g4" }, "r4" }, 7130 { { "g5" }, "r5" }, 7131 { { "g6" }, "r6" }, 7132 { { "g7" }, "r7" }, 7133 { { "o0" }, "r8" }, 7134 { { "o1" }, "r9" }, 7135 { { "o2" }, "r10" }, 7136 { { "o3" }, "r11" }, 7137 { { "o4" }, "r12" }, 7138 { { "o5" }, "r13" }, 7139 { { "o6", "sp" }, "r14" }, 7140 { { "o7" }, "r15" }, 7141 { { "l0" }, "r16" }, 7142 { { "l1" }, "r17" }, 7143 { { "l2" }, "r18" }, 7144 { { "l3" }, "r19" }, 7145 { { "l4" }, "r20" }, 7146 { { "l5" }, "r21" }, 7147 { { "l6" }, "r22" }, 7148 { { "l7" }, "r23" }, 7149 { { "i0" }, "r24" }, 7150 { { "i1" }, "r25" }, 7151 { { "i2" }, "r26" }, 7152 { { "i3" }, "r27" }, 7153 { { "i4" }, "r28" }, 7154 { { "i5" }, "r29" }, 7155 { { "i6", "fp" }, "r30" }, 7156 { { "i7" }, "r31" }, 7157 }; 7158 7159 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7160 return llvm::makeArrayRef(GCCRegAliases); 7161 } 7162 7163 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7164 class SparcV8TargetInfo : public SparcTargetInfo { 7165 public: 7166 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7167 : SparcTargetInfo(Triple, Opts) { 7168 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7169 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7170 switch (getTriple().getOS()) { 7171 default: 7172 SizeType = UnsignedInt; 7173 IntPtrType = SignedInt; 7174 PtrDiffType = SignedInt; 7175 break; 7176 case llvm::Triple::NetBSD: 7177 case llvm::Triple::OpenBSD: 7178 SizeType = UnsignedLong; 7179 IntPtrType = SignedLong; 7180 PtrDiffType = SignedLong; 7181 break; 7182 } 7183 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7184 // on up to 64 bits. 7185 MaxAtomicPromoteWidth = 64; 7186 MaxAtomicInlineWidth = 32; 7187 } 7188 7189 void getTargetDefines(const LangOptions &Opts, 7190 MacroBuilder &Builder) const override { 7191 SparcTargetInfo::getTargetDefines(Opts, Builder); 7192 switch (getCPUGeneration(CPU)) { 7193 case CG_V8: 7194 Builder.defineMacro("__sparcv8"); 7195 if (getTriple().getOS() != llvm::Triple::Solaris) 7196 Builder.defineMacro("__sparcv8__"); 7197 break; 7198 case CG_V9: 7199 Builder.defineMacro("__sparcv9"); 7200 if (getTriple().getOS() != llvm::Triple::Solaris) { 7201 Builder.defineMacro("__sparcv9__"); 7202 Builder.defineMacro("__sparc_v9__"); 7203 } 7204 break; 7205 } 7206 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7207 std::string MyriadArchValue, Myriad2Value; 7208 Builder.defineMacro("__sparc_v8__"); 7209 Builder.defineMacro("__leon__"); 7210 switch (CPU) { 7211 case CK_MYRIAD2150: 7212 MyriadArchValue = "__ma2150"; 7213 Myriad2Value = "2"; 7214 break; 7215 case CK_MYRIAD2450: 7216 MyriadArchValue = "__ma2450"; 7217 Myriad2Value = "2"; 7218 break; 7219 default: 7220 MyriadArchValue = "__ma2100"; 7221 Myriad2Value = "1"; 7222 break; 7223 } 7224 Builder.defineMacro(MyriadArchValue, "1"); 7225 Builder.defineMacro(MyriadArchValue+"__", "1"); 7226 Builder.defineMacro("__myriad2__", Myriad2Value); 7227 Builder.defineMacro("__myriad2", Myriad2Value); 7228 } 7229 } 7230 7231 bool hasSjLjLowering() const override { 7232 return true; 7233 } 7234 }; 7235 7236 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7237 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7238 public: 7239 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7240 : SparcV8TargetInfo(Triple, Opts) { 7241 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7242 } 7243 }; 7244 7245 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7246 class SparcV9TargetInfo : public SparcTargetInfo { 7247 public: 7248 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7249 : SparcTargetInfo(Triple, Opts) { 7250 // FIXME: Support Sparc quad-precision long double? 7251 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7252 // This is an LP64 platform. 7253 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7254 7255 // OpenBSD uses long long for int64_t and intmax_t. 7256 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7257 IntMaxType = SignedLongLong; 7258 else 7259 IntMaxType = SignedLong; 7260 Int64Type = IntMaxType; 7261 7262 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7263 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7264 LongDoubleWidth = 128; 7265 LongDoubleAlign = 128; 7266 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7267 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7268 } 7269 7270 void getTargetDefines(const LangOptions &Opts, 7271 MacroBuilder &Builder) const override { 7272 SparcTargetInfo::getTargetDefines(Opts, Builder); 7273 Builder.defineMacro("__sparcv9"); 7274 Builder.defineMacro("__arch64__"); 7275 // Solaris doesn't need these variants, but the BSDs do. 7276 if (getTriple().getOS() != llvm::Triple::Solaris) { 7277 Builder.defineMacro("__sparc64__"); 7278 Builder.defineMacro("__sparc_v9__"); 7279 Builder.defineMacro("__sparcv9__"); 7280 } 7281 } 7282 7283 bool setCPU(const std::string &Name) override { 7284 if (!SparcTargetInfo::setCPU(Name)) 7285 return false; 7286 return getCPUGeneration(CPU) == CG_V9; 7287 } 7288 }; 7289 7290 class SystemZTargetInfo : public TargetInfo { 7291 static const Builtin::Info BuiltinInfo[]; 7292 static const char *const GCCRegNames[]; 7293 std::string CPU; 7294 bool HasTransactionalExecution; 7295 bool HasVector; 7296 7297 public: 7298 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7299 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7300 HasVector(false) { 7301 IntMaxType = SignedLong; 7302 Int64Type = SignedLong; 7303 TLSSupported = true; 7304 IntWidth = IntAlign = 32; 7305 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7306 PointerWidth = PointerAlign = 64; 7307 LongDoubleWidth = 128; 7308 LongDoubleAlign = 64; 7309 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7310 DefaultAlignForAttributeAligned = 64; 7311 MinGlobalAlign = 16; 7312 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7313 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7314 } 7315 void getTargetDefines(const LangOptions &Opts, 7316 MacroBuilder &Builder) const override { 7317 Builder.defineMacro("__s390__"); 7318 Builder.defineMacro("__s390x__"); 7319 Builder.defineMacro("__zarch__"); 7320 Builder.defineMacro("__LONG_DOUBLE_128__"); 7321 7322 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7323 .Cases("arch8", "z10", "8") 7324 .Cases("arch9", "z196", "9") 7325 .Cases("arch10", "zEC12", "10") 7326 .Cases("arch11", "z13", "11") 7327 .Default(""); 7328 if (!ISARev.empty()) 7329 Builder.defineMacro("__ARCH__", ISARev); 7330 7331 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7332 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7333 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7334 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7335 7336 if (HasTransactionalExecution) 7337 Builder.defineMacro("__HTM__"); 7338 if (HasVector) 7339 Builder.defineMacro("__VX__"); 7340 if (Opts.ZVector) 7341 Builder.defineMacro("__VEC__", "10301"); 7342 } 7343 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7344 return llvm::makeArrayRef(BuiltinInfo, 7345 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7346 } 7347 7348 ArrayRef<const char *> getGCCRegNames() const override; 7349 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7350 // No aliases. 7351 return None; 7352 } 7353 bool validateAsmConstraint(const char *&Name, 7354 TargetInfo::ConstraintInfo &info) const override; 7355 const char *getClobbers() const override { 7356 // FIXME: Is this really right? 7357 return ""; 7358 } 7359 BuiltinVaListKind getBuiltinVaListKind() const override { 7360 return TargetInfo::SystemZBuiltinVaList; 7361 } 7362 bool setCPU(const std::string &Name) override { 7363 CPU = Name; 7364 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7365 .Case("z10", true) 7366 .Case("arch8", true) 7367 .Case("z196", true) 7368 .Case("arch9", true) 7369 .Case("zEC12", true) 7370 .Case("arch10", true) 7371 .Case("z13", true) 7372 .Case("arch11", true) 7373 .Default(false); 7374 7375 return CPUKnown; 7376 } 7377 bool 7378 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7379 StringRef CPU, 7380 const std::vector<std::string> &FeaturesVec) const override { 7381 if (CPU == "zEC12" || CPU == "arch10") 7382 Features["transactional-execution"] = true; 7383 if (CPU == "z13" || CPU == "arch11") { 7384 Features["transactional-execution"] = true; 7385 Features["vector"] = true; 7386 } 7387 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7388 } 7389 7390 bool handleTargetFeatures(std::vector<std::string> &Features, 7391 DiagnosticsEngine &Diags) override { 7392 HasTransactionalExecution = false; 7393 for (const auto &Feature : Features) { 7394 if (Feature == "+transactional-execution") 7395 HasTransactionalExecution = true; 7396 else if (Feature == "+vector") 7397 HasVector = true; 7398 } 7399 // If we use the vector ABI, vector types are 64-bit aligned. 7400 if (HasVector) { 7401 MaxVectorAlign = 64; 7402 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7403 "-v128:64-a:8:16-n32:64"); 7404 } 7405 return true; 7406 } 7407 7408 bool hasFeature(StringRef Feature) const override { 7409 return llvm::StringSwitch<bool>(Feature) 7410 .Case("systemz", true) 7411 .Case("htm", HasTransactionalExecution) 7412 .Case("vx", HasVector) 7413 .Default(false); 7414 } 7415 7416 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7417 switch (CC) { 7418 case CC_C: 7419 case CC_Swift: 7420 case CC_OpenCLKernel: 7421 return CCCR_OK; 7422 default: 7423 return CCCR_Warning; 7424 } 7425 } 7426 7427 StringRef getABI() const override { 7428 if (HasVector) 7429 return "vector"; 7430 return ""; 7431 } 7432 7433 bool useFloat128ManglingForLongDouble() const override { 7434 return true; 7435 } 7436 }; 7437 7438 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7439 #define BUILTIN(ID, TYPE, ATTRS) \ 7440 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7441 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7442 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7443 #include "clang/Basic/BuiltinsSystemZ.def" 7444 }; 7445 7446 const char *const SystemZTargetInfo::GCCRegNames[] = { 7447 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7448 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7449 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7450 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7451 }; 7452 7453 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7454 return llvm::makeArrayRef(GCCRegNames); 7455 } 7456 7457 bool SystemZTargetInfo:: 7458 validateAsmConstraint(const char *&Name, 7459 TargetInfo::ConstraintInfo &Info) const { 7460 switch (*Name) { 7461 default: 7462 return false; 7463 7464 case 'a': // Address register 7465 case 'd': // Data register (equivalent to 'r') 7466 case 'f': // Floating-point register 7467 Info.setAllowsRegister(); 7468 return true; 7469 7470 case 'I': // Unsigned 8-bit constant 7471 case 'J': // Unsigned 12-bit constant 7472 case 'K': // Signed 16-bit constant 7473 case 'L': // Signed 20-bit displacement (on all targets we support) 7474 case 'M': // 0x7fffffff 7475 return true; 7476 7477 case 'Q': // Memory with base and unsigned 12-bit displacement 7478 case 'R': // Likewise, plus an index 7479 case 'S': // Memory with base and signed 20-bit displacement 7480 case 'T': // Likewise, plus an index 7481 Info.setAllowsMemory(); 7482 return true; 7483 } 7484 } 7485 7486 class MSP430TargetInfo : public TargetInfo { 7487 static const char *const GCCRegNames[]; 7488 7489 public: 7490 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7491 : TargetInfo(Triple) { 7492 TLSSupported = false; 7493 IntWidth = 16; 7494 IntAlign = 16; 7495 LongWidth = 32; 7496 LongLongWidth = 64; 7497 LongAlign = LongLongAlign = 16; 7498 PointerWidth = 16; 7499 PointerAlign = 16; 7500 SuitableAlign = 16; 7501 SizeType = UnsignedInt; 7502 IntMaxType = SignedLongLong; 7503 IntPtrType = SignedInt; 7504 PtrDiffType = SignedInt; 7505 SigAtomicType = SignedLong; 7506 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7507 } 7508 void getTargetDefines(const LangOptions &Opts, 7509 MacroBuilder &Builder) const override { 7510 Builder.defineMacro("MSP430"); 7511 Builder.defineMacro("__MSP430__"); 7512 // FIXME: defines for different 'flavours' of MCU 7513 } 7514 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7515 // FIXME: Implement. 7516 return None; 7517 } 7518 bool hasFeature(StringRef Feature) const override { 7519 return Feature == "msp430"; 7520 } 7521 ArrayRef<const char *> getGCCRegNames() const override; 7522 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7523 // No aliases. 7524 return None; 7525 } 7526 bool validateAsmConstraint(const char *&Name, 7527 TargetInfo::ConstraintInfo &info) const override { 7528 // FIXME: implement 7529 switch (*Name) { 7530 case 'K': // the constant 1 7531 case 'L': // constant -1^20 .. 1^19 7532 case 'M': // constant 1-4: 7533 return true; 7534 } 7535 // No target constraints for now. 7536 return false; 7537 } 7538 const char *getClobbers() const override { 7539 // FIXME: Is this really right? 7540 return ""; 7541 } 7542 BuiltinVaListKind getBuiltinVaListKind() const override { 7543 // FIXME: implement 7544 return TargetInfo::CharPtrBuiltinVaList; 7545 } 7546 }; 7547 7548 const char *const MSP430TargetInfo::GCCRegNames[] = { 7549 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7550 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7551 7552 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7553 return llvm::makeArrayRef(GCCRegNames); 7554 } 7555 7556 // LLVM and Clang cannot be used directly to output native binaries for 7557 // target, but is used to compile C code to llvm bitcode with correct 7558 // type and alignment information. 7559 // 7560 // TCE uses the llvm bitcode as input and uses it for generating customized 7561 // target processor and program binary. TCE co-design environment is 7562 // publicly available in http://tce.cs.tut.fi 7563 7564 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7565 0, // Default 7566 3, // opencl_global 7567 4, // opencl_local 7568 5, // opencl_constant 7569 // FIXME: generic has to be added to the target 7570 0, // opencl_generic 7571 0, // cuda_device 7572 0, // cuda_constant 7573 0 // cuda_shared 7574 }; 7575 7576 class TCETargetInfo : public TargetInfo { 7577 public: 7578 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7579 : TargetInfo(Triple) { 7580 TLSSupported = false; 7581 IntWidth = 32; 7582 LongWidth = LongLongWidth = 32; 7583 PointerWidth = 32; 7584 IntAlign = 32; 7585 LongAlign = LongLongAlign = 32; 7586 PointerAlign = 32; 7587 SuitableAlign = 32; 7588 SizeType = UnsignedInt; 7589 IntMaxType = SignedLong; 7590 IntPtrType = SignedInt; 7591 PtrDiffType = SignedInt; 7592 FloatWidth = 32; 7593 FloatAlign = 32; 7594 DoubleWidth = 32; 7595 DoubleAlign = 32; 7596 LongDoubleWidth = 32; 7597 LongDoubleAlign = 32; 7598 FloatFormat = &llvm::APFloat::IEEEsingle(); 7599 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7600 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7601 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7602 "i16:16:32-i32:32:32-i64:32:32-" 7603 "f32:32:32-f64:32:32-v64:32:32-" 7604 "v128:32:32-v256:32:32-v512:32:32-" 7605 "v1024:32:32-a0:0:32-n32"); 7606 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7607 UseAddrSpaceMapMangling = true; 7608 } 7609 7610 void getTargetDefines(const LangOptions &Opts, 7611 MacroBuilder &Builder) const override { 7612 DefineStd(Builder, "tce", Opts); 7613 Builder.defineMacro("__TCE__"); 7614 Builder.defineMacro("__TCE_V1__"); 7615 } 7616 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7617 7618 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7619 const char *getClobbers() const override { return ""; } 7620 BuiltinVaListKind getBuiltinVaListKind() const override { 7621 return TargetInfo::VoidPtrBuiltinVaList; 7622 } 7623 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7624 bool validateAsmConstraint(const char *&Name, 7625 TargetInfo::ConstraintInfo &info) const override { 7626 return true; 7627 } 7628 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7629 return None; 7630 } 7631 }; 7632 7633 class TCELETargetInfo : public TCETargetInfo { 7634 public: 7635 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7636 : TCETargetInfo(Triple, Opts) { 7637 BigEndian = false; 7638 7639 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7640 "i16:16:32-i32:32:32-i64:32:32-" 7641 "f32:32:32-f64:32:32-v64:32:32-" 7642 "v128:32:32-v256:32:32-v512:32:32-" 7643 "v1024:32:32-a0:0:32-n32"); 7644 7645 } 7646 7647 virtual void getTargetDefines(const LangOptions &Opts, 7648 MacroBuilder &Builder) const { 7649 DefineStd(Builder, "tcele", Opts); 7650 Builder.defineMacro("__TCE__"); 7651 Builder.defineMacro("__TCE_V1__"); 7652 Builder.defineMacro("__TCELE__"); 7653 Builder.defineMacro("__TCELE_V1__"); 7654 } 7655 7656 }; 7657 7658 class BPFTargetInfo : public TargetInfo { 7659 public: 7660 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7661 : TargetInfo(Triple) { 7662 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7663 SizeType = UnsignedLong; 7664 PtrDiffType = SignedLong; 7665 IntPtrType = SignedLong; 7666 IntMaxType = SignedLong; 7667 Int64Type = SignedLong; 7668 RegParmMax = 5; 7669 if (Triple.getArch() == llvm::Triple::bpfeb) { 7670 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7671 } else { 7672 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7673 } 7674 MaxAtomicPromoteWidth = 64; 7675 MaxAtomicInlineWidth = 64; 7676 TLSSupported = false; 7677 } 7678 void getTargetDefines(const LangOptions &Opts, 7679 MacroBuilder &Builder) const override { 7680 DefineStd(Builder, "bpf", Opts); 7681 Builder.defineMacro("__BPF__"); 7682 } 7683 bool hasFeature(StringRef Feature) const override { 7684 return Feature == "bpf"; 7685 } 7686 7687 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7688 const char *getClobbers() const override { 7689 return ""; 7690 } 7691 BuiltinVaListKind getBuiltinVaListKind() const override { 7692 return TargetInfo::VoidPtrBuiltinVaList; 7693 } 7694 ArrayRef<const char *> getGCCRegNames() const override { 7695 return None; 7696 } 7697 bool validateAsmConstraint(const char *&Name, 7698 TargetInfo::ConstraintInfo &info) const override { 7699 return true; 7700 } 7701 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7702 return None; 7703 } 7704 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7705 switch (CC) { 7706 default: 7707 return CCCR_Warning; 7708 case CC_C: 7709 case CC_OpenCLKernel: 7710 return CCCR_OK; 7711 } 7712 } 7713 }; 7714 7715 class MipsTargetInfo : public TargetInfo { 7716 void setDataLayout() { 7717 StringRef Layout; 7718 7719 if (ABI == "o32") 7720 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7721 else if (ABI == "n32") 7722 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7723 else if (ABI == "n64") 7724 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7725 else 7726 llvm_unreachable("Invalid ABI"); 7727 7728 if (BigEndian) 7729 resetDataLayout(("E-" + Layout).str()); 7730 else 7731 resetDataLayout(("e-" + Layout).str()); 7732 } 7733 7734 7735 static const Builtin::Info BuiltinInfo[]; 7736 std::string CPU; 7737 bool IsMips16; 7738 bool IsMicromips; 7739 bool IsNan2008; 7740 bool IsSingleFloat; 7741 bool IsNoABICalls; 7742 bool CanUseBSDABICalls; 7743 enum MipsFloatABI { 7744 HardFloat, SoftFloat 7745 } FloatABI; 7746 enum DspRevEnum { 7747 NoDSP, DSP1, DSP2 7748 } DspRev; 7749 bool HasMSA; 7750 bool DisableMadd4; 7751 7752 protected: 7753 bool HasFP64; 7754 std::string ABI; 7755 7756 public: 7757 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7758 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7759 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7760 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7761 HasMSA(false), DisableMadd4(false), HasFP64(false) { 7762 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7763 7764 setABI((getTriple().getArch() == llvm::Triple::mips || 7765 getTriple().getArch() == llvm::Triple::mipsel) 7766 ? "o32" 7767 : "n64"); 7768 7769 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7770 7771 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7772 Triple.getOS() == llvm::Triple::OpenBSD; 7773 } 7774 7775 bool isNaN2008Default() const { 7776 return CPU == "mips32r6" || CPU == "mips64r6"; 7777 } 7778 7779 bool isFP64Default() const { 7780 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7781 } 7782 7783 bool isNan2008() const override { 7784 return IsNan2008; 7785 } 7786 7787 bool processorSupportsGPR64() const { 7788 return llvm::StringSwitch<bool>(CPU) 7789 .Case("mips3", true) 7790 .Case("mips4", true) 7791 .Case("mips5", true) 7792 .Case("mips64", true) 7793 .Case("mips64r2", true) 7794 .Case("mips64r3", true) 7795 .Case("mips64r5", true) 7796 .Case("mips64r6", true) 7797 .Case("octeon", true) 7798 .Default(false); 7799 return false; 7800 } 7801 7802 StringRef getABI() const override { return ABI; } 7803 bool setABI(const std::string &Name) override { 7804 if (Name == "o32") { 7805 setO32ABITypes(); 7806 ABI = Name; 7807 return true; 7808 } 7809 7810 if (Name == "n32") { 7811 setN32ABITypes(); 7812 ABI = Name; 7813 return true; 7814 } 7815 if (Name == "n64") { 7816 setN64ABITypes(); 7817 ABI = Name; 7818 return true; 7819 } 7820 return false; 7821 } 7822 7823 void setO32ABITypes() { 7824 Int64Type = SignedLongLong; 7825 IntMaxType = Int64Type; 7826 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7827 LongDoubleWidth = LongDoubleAlign = 64; 7828 LongWidth = LongAlign = 32; 7829 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7830 PointerWidth = PointerAlign = 32; 7831 PtrDiffType = SignedInt; 7832 SizeType = UnsignedInt; 7833 SuitableAlign = 64; 7834 } 7835 7836 void setN32N64ABITypes() { 7837 LongDoubleWidth = LongDoubleAlign = 128; 7838 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7839 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7840 LongDoubleWidth = LongDoubleAlign = 64; 7841 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7842 } 7843 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7844 SuitableAlign = 128; 7845 } 7846 7847 void setN64ABITypes() { 7848 setN32N64ABITypes(); 7849 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7850 Int64Type = SignedLongLong; 7851 } else { 7852 Int64Type = SignedLong; 7853 } 7854 IntMaxType = Int64Type; 7855 LongWidth = LongAlign = 64; 7856 PointerWidth = PointerAlign = 64; 7857 PtrDiffType = SignedLong; 7858 SizeType = UnsignedLong; 7859 } 7860 7861 void setN32ABITypes() { 7862 setN32N64ABITypes(); 7863 Int64Type = SignedLongLong; 7864 IntMaxType = Int64Type; 7865 LongWidth = LongAlign = 32; 7866 PointerWidth = PointerAlign = 32; 7867 PtrDiffType = SignedInt; 7868 SizeType = UnsignedInt; 7869 } 7870 7871 bool setCPU(const std::string &Name) override { 7872 CPU = Name; 7873 return llvm::StringSwitch<bool>(Name) 7874 .Case("mips1", true) 7875 .Case("mips2", true) 7876 .Case("mips3", true) 7877 .Case("mips4", true) 7878 .Case("mips5", true) 7879 .Case("mips32", true) 7880 .Case("mips32r2", true) 7881 .Case("mips32r3", true) 7882 .Case("mips32r5", true) 7883 .Case("mips32r6", true) 7884 .Case("mips64", true) 7885 .Case("mips64r2", true) 7886 .Case("mips64r3", true) 7887 .Case("mips64r5", true) 7888 .Case("mips64r6", true) 7889 .Case("octeon", true) 7890 .Case("p5600", true) 7891 .Default(false); 7892 } 7893 const std::string& getCPU() const { return CPU; } 7894 bool 7895 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7896 StringRef CPU, 7897 const std::vector<std::string> &FeaturesVec) const override { 7898 if (CPU.empty()) 7899 CPU = getCPU(); 7900 if (CPU == "octeon") 7901 Features["mips64r2"] = Features["cnmips"] = true; 7902 else 7903 Features[CPU] = true; 7904 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7905 } 7906 7907 void getTargetDefines(const LangOptions &Opts, 7908 MacroBuilder &Builder) const override { 7909 if (BigEndian) { 7910 DefineStd(Builder, "MIPSEB", Opts); 7911 Builder.defineMacro("_MIPSEB"); 7912 } else { 7913 DefineStd(Builder, "MIPSEL", Opts); 7914 Builder.defineMacro("_MIPSEL"); 7915 } 7916 7917 Builder.defineMacro("__mips__"); 7918 Builder.defineMacro("_mips"); 7919 if (Opts.GNUMode) 7920 Builder.defineMacro("mips"); 7921 7922 if (ABI == "o32") { 7923 Builder.defineMacro("__mips", "32"); 7924 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7925 } else { 7926 Builder.defineMacro("__mips", "64"); 7927 Builder.defineMacro("__mips64"); 7928 Builder.defineMacro("__mips64__"); 7929 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7930 } 7931 7932 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7933 .Cases("mips32", "mips64", "1") 7934 .Cases("mips32r2", "mips64r2", "2") 7935 .Cases("mips32r3", "mips64r3", "3") 7936 .Cases("mips32r5", "mips64r5", "5") 7937 .Cases("mips32r6", "mips64r6", "6") 7938 .Default(""); 7939 if (!ISARev.empty()) 7940 Builder.defineMacro("__mips_isa_rev", ISARev); 7941 7942 if (ABI == "o32") { 7943 Builder.defineMacro("__mips_o32"); 7944 Builder.defineMacro("_ABIO32", "1"); 7945 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7946 } else if (ABI == "n32") { 7947 Builder.defineMacro("__mips_n32"); 7948 Builder.defineMacro("_ABIN32", "2"); 7949 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7950 } else if (ABI == "n64") { 7951 Builder.defineMacro("__mips_n64"); 7952 Builder.defineMacro("_ABI64", "3"); 7953 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7954 } else 7955 llvm_unreachable("Invalid ABI."); 7956 7957 if (!IsNoABICalls) { 7958 Builder.defineMacro("__mips_abicalls"); 7959 if (CanUseBSDABICalls) 7960 Builder.defineMacro("__ABICALLS__"); 7961 } 7962 7963 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7964 7965 switch (FloatABI) { 7966 case HardFloat: 7967 Builder.defineMacro("__mips_hard_float", Twine(1)); 7968 break; 7969 case SoftFloat: 7970 Builder.defineMacro("__mips_soft_float", Twine(1)); 7971 break; 7972 } 7973 7974 if (IsSingleFloat) 7975 Builder.defineMacro("__mips_single_float", Twine(1)); 7976 7977 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7978 Builder.defineMacro("_MIPS_FPSET", 7979 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7980 7981 if (IsMips16) 7982 Builder.defineMacro("__mips16", Twine(1)); 7983 7984 if (IsMicromips) 7985 Builder.defineMacro("__mips_micromips", Twine(1)); 7986 7987 if (IsNan2008) 7988 Builder.defineMacro("__mips_nan2008", Twine(1)); 7989 7990 switch (DspRev) { 7991 default: 7992 break; 7993 case DSP1: 7994 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7995 Builder.defineMacro("__mips_dsp", Twine(1)); 7996 break; 7997 case DSP2: 7998 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7999 Builder.defineMacro("__mips_dspr2", Twine(1)); 8000 Builder.defineMacro("__mips_dsp", Twine(1)); 8001 break; 8002 } 8003 8004 if (HasMSA) 8005 Builder.defineMacro("__mips_msa", Twine(1)); 8006 8007 if (DisableMadd4) 8008 Builder.defineMacro("__mips_no_madd4", Twine(1)); 8009 8010 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 8011 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 8012 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 8013 8014 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 8015 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 8016 8017 // These shouldn't be defined for MIPS-I but there's no need to check 8018 // for that since MIPS-I isn't supported. 8019 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 8020 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 8021 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 8022 8023 // 32-bit MIPS processors don't have the necessary lld/scd instructions 8024 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 8025 // the instructions exist but using them violates the ABI since they 8026 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 8027 if (ABI == "n32" || ABI == "n64") 8028 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 8029 } 8030 8031 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8032 return llvm::makeArrayRef(BuiltinInfo, 8033 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 8034 } 8035 bool hasFeature(StringRef Feature) const override { 8036 return llvm::StringSwitch<bool>(Feature) 8037 .Case("mips", true) 8038 .Case("fp64", HasFP64) 8039 .Default(false); 8040 } 8041 BuiltinVaListKind getBuiltinVaListKind() const override { 8042 return TargetInfo::VoidPtrBuiltinVaList; 8043 } 8044 ArrayRef<const char *> getGCCRegNames() const override { 8045 static const char *const GCCRegNames[] = { 8046 // CPU register names 8047 // Must match second column of GCCRegAliases 8048 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 8049 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 8050 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 8051 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 8052 // Floating point register names 8053 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 8054 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 8055 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 8056 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8057 // Hi/lo and condition register names 8058 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8059 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8060 "$ac3hi","$ac3lo", 8061 // MSA register names 8062 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8063 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8064 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8065 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8066 // MSA control register names 8067 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8068 "$msarequest", "$msamap", "$msaunmap" 8069 }; 8070 return llvm::makeArrayRef(GCCRegNames); 8071 } 8072 bool validateAsmConstraint(const char *&Name, 8073 TargetInfo::ConstraintInfo &Info) const override { 8074 switch (*Name) { 8075 default: 8076 return false; 8077 case 'r': // CPU registers. 8078 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8079 case 'y': // Equivalent to "r", backward compatibility only. 8080 case 'f': // floating-point registers. 8081 case 'c': // $25 for indirect jumps 8082 case 'l': // lo register 8083 case 'x': // hilo register pair 8084 Info.setAllowsRegister(); 8085 return true; 8086 case 'I': // Signed 16-bit constant 8087 case 'J': // Integer 0 8088 case 'K': // Unsigned 16-bit constant 8089 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8090 case 'M': // Constants not loadable via lui, addiu, or ori 8091 case 'N': // Constant -1 to -65535 8092 case 'O': // A signed 15-bit constant 8093 case 'P': // A constant between 1 go 65535 8094 return true; 8095 case 'R': // An address that can be used in a non-macro load or store 8096 Info.setAllowsMemory(); 8097 return true; 8098 case 'Z': 8099 if (Name[1] == 'C') { // An address usable by ll, and sc. 8100 Info.setAllowsMemory(); 8101 Name++; // Skip over 'Z'. 8102 return true; 8103 } 8104 return false; 8105 } 8106 } 8107 8108 std::string convertConstraint(const char *&Constraint) const override { 8109 std::string R; 8110 switch (*Constraint) { 8111 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8112 if (Constraint[1] == 'C') { 8113 R = std::string("^") + std::string(Constraint, 2); 8114 Constraint++; 8115 return R; 8116 } 8117 break; 8118 } 8119 return TargetInfo::convertConstraint(Constraint); 8120 } 8121 8122 const char *getClobbers() const override { 8123 // In GCC, $1 is not widely used in generated code (it's used only in a few 8124 // specific situations), so there is no real need for users to add it to 8125 // the clobbers list if they want to use it in their inline assembly code. 8126 // 8127 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8128 // code generation, so using it in inline assembly without adding it to the 8129 // clobbers list can cause conflicts between the inline assembly code and 8130 // the surrounding generated code. 8131 // 8132 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8133 // operands, which will conflict with the ".set at" assembler option (which 8134 // we use only for inline assembly, in order to maintain compatibility with 8135 // GCC) and will also conflict with the user's usage of $1. 8136 // 8137 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8138 // register for generated code is to automatically clobber $1 for all inline 8139 // assembly code. 8140 // 8141 // FIXME: We should automatically clobber $1 only for inline assembly code 8142 // which actually uses it. This would allow LLVM to use $1 for inline 8143 // assembly operands if the user's assembly code doesn't use it. 8144 return "~{$1}"; 8145 } 8146 8147 bool handleTargetFeatures(std::vector<std::string> &Features, 8148 DiagnosticsEngine &Diags) override { 8149 IsMips16 = false; 8150 IsMicromips = false; 8151 IsNan2008 = isNaN2008Default(); 8152 IsSingleFloat = false; 8153 FloatABI = HardFloat; 8154 DspRev = NoDSP; 8155 HasFP64 = isFP64Default(); 8156 8157 for (const auto &Feature : Features) { 8158 if (Feature == "+single-float") 8159 IsSingleFloat = true; 8160 else if (Feature == "+soft-float") 8161 FloatABI = SoftFloat; 8162 else if (Feature == "+mips16") 8163 IsMips16 = true; 8164 else if (Feature == "+micromips") 8165 IsMicromips = true; 8166 else if (Feature == "+dsp") 8167 DspRev = std::max(DspRev, DSP1); 8168 else if (Feature == "+dspr2") 8169 DspRev = std::max(DspRev, DSP2); 8170 else if (Feature == "+msa") 8171 HasMSA = true; 8172 else if (Feature == "+nomadd4") 8173 DisableMadd4 = true; 8174 else if (Feature == "+fp64") 8175 HasFP64 = true; 8176 else if (Feature == "-fp64") 8177 HasFP64 = false; 8178 else if (Feature == "+nan2008") 8179 IsNan2008 = true; 8180 else if (Feature == "-nan2008") 8181 IsNan2008 = false; 8182 else if (Feature == "+noabicalls") 8183 IsNoABICalls = true; 8184 } 8185 8186 setDataLayout(); 8187 8188 return true; 8189 } 8190 8191 int getEHDataRegisterNumber(unsigned RegNo) const override { 8192 if (RegNo == 0) return 4; 8193 if (RegNo == 1) return 5; 8194 return -1; 8195 } 8196 8197 bool isCLZForZeroUndef() const override { return false; } 8198 8199 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8200 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8201 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8202 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8203 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8204 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8205 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8206 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8207 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8208 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8209 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8210 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8211 {{"ra"}, "$31"}}; 8212 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8213 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8214 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8215 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8216 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8217 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8218 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8219 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8220 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8221 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8222 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8223 {{"ra"}, "$31"}}; 8224 if (ABI == "o32") 8225 return llvm::makeArrayRef(O32RegAliases); 8226 return llvm::makeArrayRef(NewABIRegAliases); 8227 } 8228 8229 bool hasInt128Type() const override { 8230 return ABI == "n32" || ABI == "n64"; 8231 } 8232 8233 bool validateTarget(DiagnosticsEngine &Diags) const override { 8234 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8235 // this yet. It's better to fail here than on the backend assertion. 8236 if (processorSupportsGPR64() && ABI == "o32") { 8237 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8238 return false; 8239 } 8240 8241 // 64-bit ABI's require 64-bit CPU's. 8242 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8243 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8244 return false; 8245 } 8246 8247 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8248 // can't handle this yet. It's better to fail here than on the 8249 // backend assertion. 8250 if ((getTriple().getArch() == llvm::Triple::mips64 || 8251 getTriple().getArch() == llvm::Triple::mips64el) && 8252 ABI == "o32") { 8253 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8254 << ABI << getTriple().str(); 8255 return false; 8256 } 8257 8258 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8259 // can't handle this yet. It's better to fail here than on the 8260 // backend assertion. 8261 if ((getTriple().getArch() == llvm::Triple::mips || 8262 getTriple().getArch() == llvm::Triple::mipsel) && 8263 (ABI == "n32" || ABI == "n64")) { 8264 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8265 << ABI << getTriple().str(); 8266 return false; 8267 } 8268 8269 return true; 8270 } 8271 }; 8272 8273 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8274 #define BUILTIN(ID, TYPE, ATTRS) \ 8275 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8276 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8277 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8278 #include "clang/Basic/BuiltinsMips.def" 8279 }; 8280 8281 class PNaClTargetInfo : public TargetInfo { 8282 public: 8283 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8284 : TargetInfo(Triple) { 8285 this->LongAlign = 32; 8286 this->LongWidth = 32; 8287 this->PointerAlign = 32; 8288 this->PointerWidth = 32; 8289 this->IntMaxType = TargetInfo::SignedLongLong; 8290 this->Int64Type = TargetInfo::SignedLongLong; 8291 this->DoubleAlign = 64; 8292 this->LongDoubleWidth = 64; 8293 this->LongDoubleAlign = 64; 8294 this->SizeType = TargetInfo::UnsignedInt; 8295 this->PtrDiffType = TargetInfo::SignedInt; 8296 this->IntPtrType = TargetInfo::SignedInt; 8297 this->RegParmMax = 0; // Disallow regparm 8298 } 8299 8300 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8301 Builder.defineMacro("__le32__"); 8302 Builder.defineMacro("__pnacl__"); 8303 } 8304 void getTargetDefines(const LangOptions &Opts, 8305 MacroBuilder &Builder) const override { 8306 getArchDefines(Opts, Builder); 8307 } 8308 bool hasFeature(StringRef Feature) const override { 8309 return Feature == "pnacl"; 8310 } 8311 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8312 BuiltinVaListKind getBuiltinVaListKind() const override { 8313 return TargetInfo::PNaClABIBuiltinVaList; 8314 } 8315 ArrayRef<const char *> getGCCRegNames() const override; 8316 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8317 bool validateAsmConstraint(const char *&Name, 8318 TargetInfo::ConstraintInfo &Info) const override { 8319 return false; 8320 } 8321 8322 const char *getClobbers() const override { 8323 return ""; 8324 } 8325 }; 8326 8327 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8328 return None; 8329 } 8330 8331 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8332 return None; 8333 } 8334 8335 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8336 class NaClMips32TargetInfo : public MipsTargetInfo { 8337 public: 8338 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8339 : MipsTargetInfo(Triple, Opts) {} 8340 8341 BuiltinVaListKind getBuiltinVaListKind() const override { 8342 return TargetInfo::PNaClABIBuiltinVaList; 8343 } 8344 }; 8345 8346 class Le64TargetInfo : public TargetInfo { 8347 static const Builtin::Info BuiltinInfo[]; 8348 8349 public: 8350 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8351 : TargetInfo(Triple) { 8352 NoAsmVariants = true; 8353 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8354 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8355 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8356 } 8357 8358 void getTargetDefines(const LangOptions &Opts, 8359 MacroBuilder &Builder) const override { 8360 DefineStd(Builder, "unix", Opts); 8361 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8362 Builder.defineMacro("__ELF__"); 8363 } 8364 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8365 return llvm::makeArrayRef(BuiltinInfo, 8366 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8367 } 8368 BuiltinVaListKind getBuiltinVaListKind() const override { 8369 return TargetInfo::PNaClABIBuiltinVaList; 8370 } 8371 const char *getClobbers() const override { return ""; } 8372 ArrayRef<const char *> getGCCRegNames() const override { 8373 return None; 8374 } 8375 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8376 return None; 8377 } 8378 bool validateAsmConstraint(const char *&Name, 8379 TargetInfo::ConstraintInfo &Info) const override { 8380 return false; 8381 } 8382 8383 bool hasProtectedVisibility() const override { return false; } 8384 }; 8385 8386 class WebAssemblyTargetInfo : public TargetInfo { 8387 static const Builtin::Info BuiltinInfo[]; 8388 8389 enum SIMDEnum { 8390 NoSIMD, 8391 SIMD128, 8392 } SIMDLevel; 8393 8394 public: 8395 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8396 : TargetInfo(T), SIMDLevel(NoSIMD) { 8397 NoAsmVariants = true; 8398 SuitableAlign = 128; 8399 LargeArrayMinWidth = 128; 8400 LargeArrayAlign = 128; 8401 SimdDefaultAlign = 128; 8402 SigAtomicType = SignedLong; 8403 LongDoubleWidth = LongDoubleAlign = 128; 8404 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8405 SizeType = UnsignedInt; 8406 PtrDiffType = SignedInt; 8407 IntPtrType = SignedInt; 8408 } 8409 8410 protected: 8411 void getTargetDefines(const LangOptions &Opts, 8412 MacroBuilder &Builder) const override { 8413 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8414 if (SIMDLevel >= SIMD128) 8415 Builder.defineMacro("__wasm_simd128__"); 8416 } 8417 8418 private: 8419 bool 8420 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8421 StringRef CPU, 8422 const std::vector<std::string> &FeaturesVec) const override { 8423 if (CPU == "bleeding-edge") 8424 Features["simd128"] = true; 8425 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8426 } 8427 bool hasFeature(StringRef Feature) const final { 8428 return llvm::StringSwitch<bool>(Feature) 8429 .Case("simd128", SIMDLevel >= SIMD128) 8430 .Default(false); 8431 } 8432 bool handleTargetFeatures(std::vector<std::string> &Features, 8433 DiagnosticsEngine &Diags) final { 8434 for (const auto &Feature : Features) { 8435 if (Feature == "+simd128") { 8436 SIMDLevel = std::max(SIMDLevel, SIMD128); 8437 continue; 8438 } 8439 if (Feature == "-simd128") { 8440 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8441 continue; 8442 } 8443 8444 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8445 << "-target-feature"; 8446 return false; 8447 } 8448 return true; 8449 } 8450 bool setCPU(const std::string &Name) final { 8451 return llvm::StringSwitch<bool>(Name) 8452 .Case("mvp", true) 8453 .Case("bleeding-edge", true) 8454 .Case("generic", true) 8455 .Default(false); 8456 } 8457 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8458 return llvm::makeArrayRef(BuiltinInfo, 8459 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8460 } 8461 BuiltinVaListKind getBuiltinVaListKind() const final { 8462 return VoidPtrBuiltinVaList; 8463 } 8464 ArrayRef<const char *> getGCCRegNames() const final { 8465 return None; 8466 } 8467 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8468 return None; 8469 } 8470 bool 8471 validateAsmConstraint(const char *&Name, 8472 TargetInfo::ConstraintInfo &Info) const final { 8473 return false; 8474 } 8475 const char *getClobbers() const final { return ""; } 8476 bool isCLZForZeroUndef() const final { return false; } 8477 bool hasInt128Type() const final { return true; } 8478 IntType getIntTypeByWidth(unsigned BitWidth, 8479 bool IsSigned) const final { 8480 // WebAssembly prefers long long for explicitly 64-bit integers. 8481 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8482 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8483 } 8484 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8485 bool IsSigned) const final { 8486 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8487 return BitWidth == 64 8488 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8489 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8490 } 8491 }; 8492 8493 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8494 #define BUILTIN(ID, TYPE, ATTRS) \ 8495 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8496 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8497 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8498 #include "clang/Basic/BuiltinsWebAssembly.def" 8499 }; 8500 8501 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8502 public: 8503 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8504 const TargetOptions &Opts) 8505 : WebAssemblyTargetInfo(T, Opts) { 8506 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8507 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8508 } 8509 8510 protected: 8511 void getTargetDefines(const LangOptions &Opts, 8512 MacroBuilder &Builder) const override { 8513 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8514 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8515 } 8516 }; 8517 8518 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8519 public: 8520 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8521 const TargetOptions &Opts) 8522 : WebAssemblyTargetInfo(T, Opts) { 8523 LongAlign = LongWidth = 64; 8524 PointerAlign = PointerWidth = 64; 8525 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8526 SizeType = UnsignedLong; 8527 PtrDiffType = SignedLong; 8528 IntPtrType = SignedLong; 8529 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8530 } 8531 8532 protected: 8533 void getTargetDefines(const LangOptions &Opts, 8534 MacroBuilder &Builder) const override { 8535 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8536 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8537 } 8538 }; 8539 8540 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8541 #define BUILTIN(ID, TYPE, ATTRS) \ 8542 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8543 #include "clang/Basic/BuiltinsLe64.def" 8544 }; 8545 8546 static const unsigned SPIRAddrSpaceMap[] = { 8547 0, // Default 8548 1, // opencl_global 8549 3, // opencl_local 8550 2, // opencl_constant 8551 4, // opencl_generic 8552 0, // cuda_device 8553 0, // cuda_constant 8554 0 // cuda_shared 8555 }; 8556 class SPIRTargetInfo : public TargetInfo { 8557 public: 8558 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8559 : TargetInfo(Triple) { 8560 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8561 "SPIR target must use unknown OS"); 8562 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8563 "SPIR target must use unknown environment type"); 8564 TLSSupported = false; 8565 LongWidth = LongAlign = 64; 8566 AddrSpaceMap = &SPIRAddrSpaceMap; 8567 UseAddrSpaceMapMangling = true; 8568 // Define available target features 8569 // These must be defined in sorted order! 8570 NoAsmVariants = true; 8571 } 8572 void getTargetDefines(const LangOptions &Opts, 8573 MacroBuilder &Builder) const override { 8574 DefineStd(Builder, "SPIR", Opts); 8575 } 8576 bool hasFeature(StringRef Feature) const override { 8577 return Feature == "spir"; 8578 } 8579 8580 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8581 const char *getClobbers() const override { return ""; } 8582 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8583 bool validateAsmConstraint(const char *&Name, 8584 TargetInfo::ConstraintInfo &info) const override { 8585 return true; 8586 } 8587 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8588 return None; 8589 } 8590 BuiltinVaListKind getBuiltinVaListKind() const override { 8591 return TargetInfo::VoidPtrBuiltinVaList; 8592 } 8593 8594 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8595 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8596 : CCCR_Warning; 8597 } 8598 8599 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8600 return CC_SpirFunction; 8601 } 8602 8603 void setSupportedOpenCLOpts() override { 8604 // Assume all OpenCL extensions and optional core features are supported 8605 // for SPIR since it is a generic target. 8606 getSupportedOpenCLOpts().supportAll(); 8607 } 8608 }; 8609 8610 class SPIR32TargetInfo : public SPIRTargetInfo { 8611 public: 8612 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8613 : SPIRTargetInfo(Triple, Opts) { 8614 PointerWidth = PointerAlign = 32; 8615 SizeType = TargetInfo::UnsignedInt; 8616 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8617 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8618 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8619 } 8620 void getTargetDefines(const LangOptions &Opts, 8621 MacroBuilder &Builder) const override { 8622 DefineStd(Builder, "SPIR32", Opts); 8623 } 8624 }; 8625 8626 class SPIR64TargetInfo : public SPIRTargetInfo { 8627 public: 8628 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8629 : SPIRTargetInfo(Triple, Opts) { 8630 PointerWidth = PointerAlign = 64; 8631 SizeType = TargetInfo::UnsignedLong; 8632 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8633 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8634 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8635 } 8636 void getTargetDefines(const LangOptions &Opts, 8637 MacroBuilder &Builder) const override { 8638 DefineStd(Builder, "SPIR64", Opts); 8639 } 8640 }; 8641 8642 class XCoreTargetInfo : public TargetInfo { 8643 static const Builtin::Info BuiltinInfo[]; 8644 public: 8645 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8646 : TargetInfo(Triple) { 8647 NoAsmVariants = true; 8648 LongLongAlign = 32; 8649 SuitableAlign = 32; 8650 DoubleAlign = LongDoubleAlign = 32; 8651 SizeType = UnsignedInt; 8652 PtrDiffType = SignedInt; 8653 IntPtrType = SignedInt; 8654 WCharType = UnsignedChar; 8655 WIntType = UnsignedInt; 8656 UseZeroLengthBitfieldAlignment = true; 8657 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8658 "-f64:32-a:0:32-n32"); 8659 } 8660 void getTargetDefines(const LangOptions &Opts, 8661 MacroBuilder &Builder) const override { 8662 Builder.defineMacro("__XS1B__"); 8663 } 8664 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8665 return llvm::makeArrayRef(BuiltinInfo, 8666 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8667 } 8668 BuiltinVaListKind getBuiltinVaListKind() const override { 8669 return TargetInfo::VoidPtrBuiltinVaList; 8670 } 8671 const char *getClobbers() const override { 8672 return ""; 8673 } 8674 ArrayRef<const char *> getGCCRegNames() const override { 8675 static const char * const GCCRegNames[] = { 8676 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8677 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8678 }; 8679 return llvm::makeArrayRef(GCCRegNames); 8680 } 8681 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8682 return None; 8683 } 8684 bool validateAsmConstraint(const char *&Name, 8685 TargetInfo::ConstraintInfo &Info) const override { 8686 return false; 8687 } 8688 int getEHDataRegisterNumber(unsigned RegNo) const override { 8689 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8690 return (RegNo < 2)? RegNo : -1; 8691 } 8692 bool allowsLargerPreferedTypeAlignment() const override { 8693 return false; 8694 } 8695 }; 8696 8697 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8698 #define BUILTIN(ID, TYPE, ATTRS) \ 8699 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8700 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8701 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8702 #include "clang/Basic/BuiltinsXCore.def" 8703 }; 8704 8705 // x86_32 Android target 8706 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8707 public: 8708 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8709 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8710 SuitableAlign = 32; 8711 LongDoubleWidth = 64; 8712 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8713 } 8714 }; 8715 8716 // x86_64 Android target 8717 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8718 public: 8719 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8720 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8721 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8722 } 8723 8724 bool useFloat128ManglingForLongDouble() const override { 8725 return true; 8726 } 8727 }; 8728 8729 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8730 class RenderScript32TargetInfo : public ARMleTargetInfo { 8731 public: 8732 RenderScript32TargetInfo(const llvm::Triple &Triple, 8733 const TargetOptions &Opts) 8734 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8735 Triple.getOSName(), 8736 Triple.getEnvironmentName()), 8737 Opts) { 8738 IsRenderScriptTarget = true; 8739 LongWidth = LongAlign = 64; 8740 } 8741 void getTargetDefines(const LangOptions &Opts, 8742 MacroBuilder &Builder) const override { 8743 Builder.defineMacro("__RENDERSCRIPT__"); 8744 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8745 } 8746 }; 8747 8748 // 64-bit RenderScript is aarch64 8749 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8750 public: 8751 RenderScript64TargetInfo(const llvm::Triple &Triple, 8752 const TargetOptions &Opts) 8753 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8754 Triple.getOSName(), 8755 Triple.getEnvironmentName()), 8756 Opts) { 8757 IsRenderScriptTarget = true; 8758 } 8759 8760 void getTargetDefines(const LangOptions &Opts, 8761 MacroBuilder &Builder) const override { 8762 Builder.defineMacro("__RENDERSCRIPT__"); 8763 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8764 } 8765 }; 8766 8767 /// Information about a specific microcontroller. 8768 struct MCUInfo { 8769 const char *Name; 8770 const char *DefineName; 8771 }; 8772 8773 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8774 static ArrayRef<MCUInfo> AVRMcus = { 8775 { "at90s1200", "__AVR_AT90S1200__" }, 8776 { "attiny11", "__AVR_ATtiny11__" }, 8777 { "attiny12", "__AVR_ATtiny12__" }, 8778 { "attiny15", "__AVR_ATtiny15__" }, 8779 { "attiny28", "__AVR_ATtiny28__" }, 8780 { "at90s2313", "__AVR_AT90S2313__" }, 8781 { "at90s2323", "__AVR_AT90S2323__" }, 8782 { "at90s2333", "__AVR_AT90S2333__" }, 8783 { "at90s2343", "__AVR_AT90S2343__" }, 8784 { "attiny22", "__AVR_ATtiny22__" }, 8785 { "attiny26", "__AVR_ATtiny26__" }, 8786 { "at86rf401", "__AVR_AT86RF401__" }, 8787 { "at90s4414", "__AVR_AT90S4414__" }, 8788 { "at90s4433", "__AVR_AT90S4433__" }, 8789 { "at90s4434", "__AVR_AT90S4434__" }, 8790 { "at90s8515", "__AVR_AT90S8515__" }, 8791 { "at90c8534", "__AVR_AT90c8534__" }, 8792 { "at90s8535", "__AVR_AT90S8535__" }, 8793 { "ata5272", "__AVR_ATA5272__" }, 8794 { "attiny13", "__AVR_ATtiny13__" }, 8795 { "attiny13a", "__AVR_ATtiny13A__" }, 8796 { "attiny2313", "__AVR_ATtiny2313__" }, 8797 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8798 { "attiny24", "__AVR_ATtiny24__" }, 8799 { "attiny24a", "__AVR_ATtiny24A__" }, 8800 { "attiny4313", "__AVR_ATtiny4313__" }, 8801 { "attiny44", "__AVR_ATtiny44__" }, 8802 { "attiny44a", "__AVR_ATtiny44A__" }, 8803 { "attiny84", "__AVR_ATtiny84__" }, 8804 { "attiny84a", "__AVR_ATtiny84A__" }, 8805 { "attiny25", "__AVR_ATtiny25__" }, 8806 { "attiny45", "__AVR_ATtiny45__" }, 8807 { "attiny85", "__AVR_ATtiny85__" }, 8808 { "attiny261", "__AVR_ATtiny261__" }, 8809 { "attiny261a", "__AVR_ATtiny261A__" }, 8810 { "attiny461", "__AVR_ATtiny461__" }, 8811 { "attiny461a", "__AVR_ATtiny461A__" }, 8812 { "attiny861", "__AVR_ATtiny861__" }, 8813 { "attiny861a", "__AVR_ATtiny861A__" }, 8814 { "attiny87", "__AVR_ATtiny87__" }, 8815 { "attiny43u", "__AVR_ATtiny43U__" }, 8816 { "attiny48", "__AVR_ATtiny48__" }, 8817 { "attiny88", "__AVR_ATtiny88__" }, 8818 { "attiny828", "__AVR_ATtiny828__" }, 8819 { "at43usb355", "__AVR_AT43USB355__" }, 8820 { "at76c711", "__AVR_AT76C711__" }, 8821 { "atmega103", "__AVR_ATmega103__" }, 8822 { "at43usb320", "__AVR_AT43USB320__" }, 8823 { "attiny167", "__AVR_ATtiny167__" }, 8824 { "at90usb82", "__AVR_AT90USB82__" }, 8825 { "at90usb162", "__AVR_AT90USB162__" }, 8826 { "ata5505", "__AVR_ATA5505__" }, 8827 { "atmega8u2", "__AVR_ATmega8U2__" }, 8828 { "atmega16u2", "__AVR_ATmega16U2__" }, 8829 { "atmega32u2", "__AVR_ATmega32U2__" }, 8830 { "attiny1634", "__AVR_ATtiny1634__" }, 8831 { "atmega8", "__AVR_ATmega8__" }, 8832 { "ata6289", "__AVR_ATA6289__" }, 8833 { "atmega8a", "__AVR_ATmega8A__" }, 8834 { "ata6285", "__AVR_ATA6285__" }, 8835 { "ata6286", "__AVR_ATA6286__" }, 8836 { "atmega48", "__AVR_ATmega48__" }, 8837 { "atmega48a", "__AVR_ATmega48A__" }, 8838 { "atmega48pa", "__AVR_ATmega48PA__" }, 8839 { "atmega48p", "__AVR_ATmega48P__" }, 8840 { "atmega88", "__AVR_ATmega88__" }, 8841 { "atmega88a", "__AVR_ATmega88A__" }, 8842 { "atmega88p", "__AVR_ATmega88P__" }, 8843 { "atmega88pa", "__AVR_ATmega88PA__" }, 8844 { "atmega8515", "__AVR_ATmega8515__" }, 8845 { "atmega8535", "__AVR_ATmega8535__" }, 8846 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8847 { "at90pwm1", "__AVR_AT90PWM1__" }, 8848 { "at90pwm2", "__AVR_AT90PWM2__" }, 8849 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8850 { "at90pwm3", "__AVR_AT90PWM3__" }, 8851 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8852 { "at90pwm81", "__AVR_AT90PWM81__" }, 8853 { "ata5790", "__AVR_ATA5790__" }, 8854 { "ata5795", "__AVR_ATA5795__" }, 8855 { "atmega16", "__AVR_ATmega16__" }, 8856 { "atmega16a", "__AVR_ATmega16A__" }, 8857 { "atmega161", "__AVR_ATmega161__" }, 8858 { "atmega162", "__AVR_ATmega162__" }, 8859 { "atmega163", "__AVR_ATmega163__" }, 8860 { "atmega164a", "__AVR_ATmega164A__" }, 8861 { "atmega164p", "__AVR_ATmega164P__" }, 8862 { "atmega164pa", "__AVR_ATmega164PA__" }, 8863 { "atmega165", "__AVR_ATmega165__" }, 8864 { "atmega165a", "__AVR_ATmega165A__" }, 8865 { "atmega165p", "__AVR_ATmega165P__" }, 8866 { "atmega165pa", "__AVR_ATmega165PA__" }, 8867 { "atmega168", "__AVR_ATmega168__" }, 8868 { "atmega168a", "__AVR_ATmega168A__" }, 8869 { "atmega168p", "__AVR_ATmega168P__" }, 8870 { "atmega168pa", "__AVR_ATmega168PA__" }, 8871 { "atmega169", "__AVR_ATmega169__" }, 8872 { "atmega169a", "__AVR_ATmega169A__" }, 8873 { "atmega169p", "__AVR_ATmega169P__" }, 8874 { "atmega169pa", "__AVR_ATmega169PA__" }, 8875 { "atmega32", "__AVR_ATmega32__" }, 8876 { "atmega32a", "__AVR_ATmega32A__" }, 8877 { "atmega323", "__AVR_ATmega323__" }, 8878 { "atmega324a", "__AVR_ATmega324A__" }, 8879 { "atmega324p", "__AVR_ATmega324P__" }, 8880 { "atmega324pa", "__AVR_ATmega324PA__" }, 8881 { "atmega325", "__AVR_ATmega325__" }, 8882 { "atmega325a", "__AVR_ATmega325A__" }, 8883 { "atmega325p", "__AVR_ATmega325P__" }, 8884 { "atmega325pa", "__AVR_ATmega325PA__" }, 8885 { "atmega3250", "__AVR_ATmega3250__" }, 8886 { "atmega3250a", "__AVR_ATmega3250A__" }, 8887 { "atmega3250p", "__AVR_ATmega3250P__" }, 8888 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8889 { "atmega328", "__AVR_ATmega328__" }, 8890 { "atmega328p", "__AVR_ATmega328P__" }, 8891 { "atmega329", "__AVR_ATmega329__" }, 8892 { "atmega329a", "__AVR_ATmega329A__" }, 8893 { "atmega329p", "__AVR_ATmega329P__" }, 8894 { "atmega329pa", "__AVR_ATmega329PA__" }, 8895 { "atmega3290", "__AVR_ATmega3290__" }, 8896 { "atmega3290a", "__AVR_ATmega3290A__" }, 8897 { "atmega3290p", "__AVR_ATmega3290P__" }, 8898 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8899 { "atmega406", "__AVR_ATmega406__" }, 8900 { "atmega64", "__AVR_ATmega64__" }, 8901 { "atmega64a", "__AVR_ATmega64A__" }, 8902 { "atmega640", "__AVR_ATmega640__" }, 8903 { "atmega644", "__AVR_ATmega644__" }, 8904 { "atmega644a", "__AVR_ATmega644A__" }, 8905 { "atmega644p", "__AVR_ATmega644P__" }, 8906 { "atmega644pa", "__AVR_ATmega644PA__" }, 8907 { "atmega645", "__AVR_ATmega645__" }, 8908 { "atmega645a", "__AVR_ATmega645A__" }, 8909 { "atmega645p", "__AVR_ATmega645P__" }, 8910 { "atmega649", "__AVR_ATmega649__" }, 8911 { "atmega649a", "__AVR_ATmega649A__" }, 8912 { "atmega649p", "__AVR_ATmega649P__" }, 8913 { "atmega6450", "__AVR_ATmega6450__" }, 8914 { "atmega6450a", "__AVR_ATmega6450A__" }, 8915 { "atmega6450p", "__AVR_ATmega6450P__" }, 8916 { "atmega6490", "__AVR_ATmega6490__" }, 8917 { "atmega6490a", "__AVR_ATmega6490A__" }, 8918 { "atmega6490p", "__AVR_ATmega6490P__" }, 8919 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8920 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8921 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8922 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8923 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8924 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8925 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8926 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8927 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8928 { "at90can32", "__AVR_AT90CAN32__" }, 8929 { "at90can64", "__AVR_AT90CAN64__" }, 8930 { "at90pwm161", "__AVR_AT90PWM161__" }, 8931 { "at90pwm216", "__AVR_AT90PWM216__" }, 8932 { "at90pwm316", "__AVR_AT90PWM316__" }, 8933 { "atmega32c1", "__AVR_ATmega32C1__" }, 8934 { "atmega64c1", "__AVR_ATmega64C1__" }, 8935 { "atmega16m1", "__AVR_ATmega16M1__" }, 8936 { "atmega32m1", "__AVR_ATmega32M1__" }, 8937 { "atmega64m1", "__AVR_ATmega64M1__" }, 8938 { "atmega16u4", "__AVR_ATmega16U4__" }, 8939 { "atmega32u4", "__AVR_ATmega32U4__" }, 8940 { "atmega32u6", "__AVR_ATmega32U6__" }, 8941 { "at90usb646", "__AVR_AT90USB646__" }, 8942 { "at90usb647", "__AVR_AT90USB647__" }, 8943 { "at90scr100", "__AVR_AT90SCR100__" }, 8944 { "at94k", "__AVR_AT94K__" }, 8945 { "m3000", "__AVR_AT000__" }, 8946 { "atmega128", "__AVR_ATmega128__" }, 8947 { "atmega128a", "__AVR_ATmega128A__" }, 8948 { "atmega1280", "__AVR_ATmega1280__" }, 8949 { "atmega1281", "__AVR_ATmega1281__" }, 8950 { "atmega1284", "__AVR_ATmega1284__" }, 8951 { "atmega1284p", "__AVR_ATmega1284P__" }, 8952 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8953 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8954 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8955 { "at90can128", "__AVR_AT90CAN128__" }, 8956 { "at90usb1286", "__AVR_AT90USB1286__" }, 8957 { "at90usb1287", "__AVR_AT90USB1287__" }, 8958 { "atmega2560", "__AVR_ATmega2560__" }, 8959 { "atmega2561", "__AVR_ATmega2561__" }, 8960 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8961 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8962 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8963 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8964 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8965 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8966 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8967 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8968 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8969 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8970 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8971 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8972 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8973 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8974 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8975 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8976 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8977 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8978 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8979 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8980 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8981 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8982 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8983 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8984 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8985 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8986 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8987 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8988 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8989 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8990 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8991 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8992 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8993 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8994 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8995 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8996 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8997 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8998 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8999 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 9000 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 9001 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 9002 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 9003 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 9004 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 9005 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 9006 { "attiny4", "__AVR_ATtiny4__" }, 9007 { "attiny5", "__AVR_ATtiny5__" }, 9008 { "attiny9", "__AVR_ATtiny9__" }, 9009 { "attiny10", "__AVR_ATtiny10__" }, 9010 { "attiny20", "__AVR_ATtiny20__" }, 9011 { "attiny40", "__AVR_ATtiny40__" }, 9012 { "attiny102", "__AVR_ATtiny102__" }, 9013 { "attiny104", "__AVR_ATtiny104__" }, 9014 }; 9015 9016 // AVR Target 9017 class AVRTargetInfo : public TargetInfo { 9018 public: 9019 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 9020 : TargetInfo(Triple) { 9021 TLSSupported = false; 9022 PointerWidth = 16; 9023 PointerAlign = 8; 9024 IntWidth = 16; 9025 IntAlign = 8; 9026 LongWidth = 32; 9027 LongAlign = 8; 9028 LongLongWidth = 64; 9029 LongLongAlign = 8; 9030 SuitableAlign = 8; 9031 DefaultAlignForAttributeAligned = 8; 9032 HalfWidth = 16; 9033 HalfAlign = 8; 9034 FloatWidth = 32; 9035 FloatAlign = 8; 9036 DoubleWidth = 32; 9037 DoubleAlign = 8; 9038 DoubleFormat = &llvm::APFloat::IEEEsingle(); 9039 LongDoubleWidth = 32; 9040 LongDoubleAlign = 8; 9041 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 9042 SizeType = UnsignedInt; 9043 PtrDiffType = SignedInt; 9044 IntPtrType = SignedInt; 9045 Char16Type = UnsignedInt; 9046 WCharType = SignedInt; 9047 WIntType = SignedInt; 9048 Char32Type = UnsignedLong; 9049 SigAtomicType = SignedChar; 9050 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 9051 "-f32:32:32-f64:64:64-n8"); 9052 } 9053 9054 void getTargetDefines(const LangOptions &Opts, 9055 MacroBuilder &Builder) const override { 9056 Builder.defineMacro("AVR"); 9057 Builder.defineMacro("__AVR"); 9058 Builder.defineMacro("__AVR__"); 9059 9060 if (!this->CPU.empty()) { 9061 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9062 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9063 9064 if (It != AVRMcus.end()) 9065 Builder.defineMacro(It->DefineName); 9066 } 9067 } 9068 9069 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9070 return None; 9071 } 9072 9073 BuiltinVaListKind getBuiltinVaListKind() const override { 9074 return TargetInfo::VoidPtrBuiltinVaList; 9075 } 9076 9077 const char *getClobbers() const override { 9078 return ""; 9079 } 9080 9081 ArrayRef<const char *> getGCCRegNames() const override { 9082 static const char * const GCCRegNames[] = { 9083 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9084 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9085 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9086 "r24", "r25", "X", "Y", "Z", "SP" 9087 }; 9088 return llvm::makeArrayRef(GCCRegNames); 9089 } 9090 9091 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9092 return None; 9093 } 9094 9095 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9096 static const TargetInfo::AddlRegName AddlRegNames[] = { 9097 { { "r26", "r27"}, 26 }, 9098 { { "r28", "r29"}, 27 }, 9099 { { "r30", "r31"}, 28 }, 9100 { { "SPL", "SPH"}, 29 }, 9101 }; 9102 return llvm::makeArrayRef(AddlRegNames); 9103 } 9104 9105 bool validateAsmConstraint(const char *&Name, 9106 TargetInfo::ConstraintInfo &Info) const override { 9107 // There aren't any multi-character AVR specific constraints. 9108 if (StringRef(Name).size() > 1) return false; 9109 9110 switch (*Name) { 9111 default: return false; 9112 case 'a': // Simple upper registers 9113 case 'b': // Base pointer registers pairs 9114 case 'd': // Upper register 9115 case 'l': // Lower registers 9116 case 'e': // Pointer register pairs 9117 case 'q': // Stack pointer register 9118 case 'r': // Any register 9119 case 'w': // Special upper register pairs 9120 case 't': // Temporary register 9121 case 'x': case 'X': // Pointer register pair X 9122 case 'y': case 'Y': // Pointer register pair Y 9123 case 'z': case 'Z': // Pointer register pair Z 9124 Info.setAllowsRegister(); 9125 return true; 9126 case 'I': // 6-bit positive integer constant 9127 Info.setRequiresImmediate(0, 63); 9128 return true; 9129 case 'J': // 6-bit negative integer constant 9130 Info.setRequiresImmediate(-63, 0); 9131 return true; 9132 case 'K': // Integer constant (Range: 2) 9133 Info.setRequiresImmediate(2); 9134 return true; 9135 case 'L': // Integer constant (Range: 0) 9136 Info.setRequiresImmediate(0); 9137 return true; 9138 case 'M': // 8-bit integer constant 9139 Info.setRequiresImmediate(0, 0xff); 9140 return true; 9141 case 'N': // Integer constant (Range: -1) 9142 Info.setRequiresImmediate(-1); 9143 return true; 9144 case 'O': // Integer constant (Range: 8, 16, 24) 9145 Info.setRequiresImmediate({8, 16, 24}); 9146 return true; 9147 case 'P': // Integer constant (Range: 1) 9148 Info.setRequiresImmediate(1); 9149 return true; 9150 case 'R': // Integer constant (Range: -6 to 5) 9151 Info.setRequiresImmediate(-6, 5); 9152 return true; 9153 case 'G': // Floating point constant 9154 case 'Q': // A memory address based on Y or Z pointer with displacement. 9155 return true; 9156 } 9157 9158 return false; 9159 } 9160 9161 IntType getIntTypeByWidth(unsigned BitWidth, 9162 bool IsSigned) const final { 9163 // AVR prefers int for 16-bit integers. 9164 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9165 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9166 } 9167 9168 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9169 bool IsSigned) const final { 9170 // AVR uses int for int_least16_t and int_fast16_t. 9171 return BitWidth == 16 9172 ? (IsSigned ? SignedInt : UnsignedInt) 9173 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9174 } 9175 9176 bool setCPU(const std::string &Name) override { 9177 bool IsFamily = llvm::StringSwitch<bool>(Name) 9178 .Case("avr1", true) 9179 .Case("avr2", true) 9180 .Case("avr25", true) 9181 .Case("avr3", true) 9182 .Case("avr31", true) 9183 .Case("avr35", true) 9184 .Case("avr4", true) 9185 .Case("avr5", true) 9186 .Case("avr51", true) 9187 .Case("avr6", true) 9188 .Case("avrxmega1", true) 9189 .Case("avrxmega2", true) 9190 .Case("avrxmega3", true) 9191 .Case("avrxmega4", true) 9192 .Case("avrxmega5", true) 9193 .Case("avrxmega6", true) 9194 .Case("avrxmega7", true) 9195 .Case("avrtiny", true) 9196 .Default(false); 9197 9198 if (IsFamily) this->CPU = Name; 9199 9200 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9201 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9202 9203 if (IsMCU) this->CPU = Name; 9204 9205 return IsFamily || IsMCU; 9206 } 9207 9208 protected: 9209 std::string CPU; 9210 }; 9211 9212 } // end anonymous namespace 9213 9214 //===----------------------------------------------------------------------===// 9215 // Driver code 9216 //===----------------------------------------------------------------------===// 9217 9218 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9219 const TargetOptions &Opts) { 9220 llvm::Triple::OSType os = Triple.getOS(); 9221 9222 switch (Triple.getArch()) { 9223 default: 9224 return nullptr; 9225 9226 case llvm::Triple::xcore: 9227 return new XCoreTargetInfo(Triple, Opts); 9228 9229 case llvm::Triple::hexagon: 9230 return new HexagonTargetInfo(Triple, Opts); 9231 9232 case llvm::Triple::lanai: 9233 return new LanaiTargetInfo(Triple, Opts); 9234 9235 case llvm::Triple::aarch64: 9236 if (Triple.isOSDarwin()) 9237 return new DarwinAArch64TargetInfo(Triple, Opts); 9238 9239 switch (os) { 9240 case llvm::Triple::CloudABI: 9241 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9242 case llvm::Triple::FreeBSD: 9243 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9244 case llvm::Triple::Fuchsia: 9245 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9246 case llvm::Triple::Linux: 9247 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9248 case llvm::Triple::NetBSD: 9249 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9250 case llvm::Triple::OpenBSD: 9251 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9252 default: 9253 return new AArch64leTargetInfo(Triple, Opts); 9254 } 9255 9256 case llvm::Triple::aarch64_be: 9257 switch (os) { 9258 case llvm::Triple::FreeBSD: 9259 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9260 case llvm::Triple::Fuchsia: 9261 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9262 case llvm::Triple::Linux: 9263 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9264 case llvm::Triple::NetBSD: 9265 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9266 default: 9267 return new AArch64beTargetInfo(Triple, Opts); 9268 } 9269 9270 case llvm::Triple::arm: 9271 case llvm::Triple::thumb: 9272 if (Triple.isOSBinFormatMachO()) 9273 return new DarwinARMTargetInfo(Triple, Opts); 9274 9275 switch (os) { 9276 case llvm::Triple::CloudABI: 9277 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9278 case llvm::Triple::Linux: 9279 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9280 case llvm::Triple::FreeBSD: 9281 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9282 case llvm::Triple::NetBSD: 9283 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9284 case llvm::Triple::OpenBSD: 9285 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9286 case llvm::Triple::Bitrig: 9287 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9288 case llvm::Triple::RTEMS: 9289 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9290 case llvm::Triple::NaCl: 9291 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9292 case llvm::Triple::Win32: 9293 switch (Triple.getEnvironment()) { 9294 case llvm::Triple::Cygnus: 9295 return new CygwinARMTargetInfo(Triple, Opts); 9296 case llvm::Triple::GNU: 9297 return new MinGWARMTargetInfo(Triple, Opts); 9298 case llvm::Triple::Itanium: 9299 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9300 case llvm::Triple::MSVC: 9301 default: // Assume MSVC for unknown environments 9302 return new MicrosoftARMleTargetInfo(Triple, Opts); 9303 } 9304 default: 9305 return new ARMleTargetInfo(Triple, Opts); 9306 } 9307 9308 case llvm::Triple::armeb: 9309 case llvm::Triple::thumbeb: 9310 if (Triple.isOSDarwin()) 9311 return new DarwinARMTargetInfo(Triple, Opts); 9312 9313 switch (os) { 9314 case llvm::Triple::Linux: 9315 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9316 case llvm::Triple::FreeBSD: 9317 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9318 case llvm::Triple::NetBSD: 9319 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9320 case llvm::Triple::OpenBSD: 9321 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9322 case llvm::Triple::Bitrig: 9323 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9324 case llvm::Triple::RTEMS: 9325 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9326 case llvm::Triple::NaCl: 9327 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9328 default: 9329 return new ARMbeTargetInfo(Triple, Opts); 9330 } 9331 9332 case llvm::Triple::avr: 9333 return new AVRTargetInfo(Triple, Opts); 9334 case llvm::Triple::bpfeb: 9335 case llvm::Triple::bpfel: 9336 return new BPFTargetInfo(Triple, Opts); 9337 9338 case llvm::Triple::msp430: 9339 return new MSP430TargetInfo(Triple, Opts); 9340 9341 case llvm::Triple::mips: 9342 switch (os) { 9343 case llvm::Triple::Linux: 9344 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9345 case llvm::Triple::RTEMS: 9346 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9347 case llvm::Triple::FreeBSD: 9348 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9349 case llvm::Triple::NetBSD: 9350 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9351 default: 9352 return new MipsTargetInfo(Triple, Opts); 9353 } 9354 9355 case llvm::Triple::mipsel: 9356 switch (os) { 9357 case llvm::Triple::Linux: 9358 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9359 case llvm::Triple::RTEMS: 9360 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9361 case llvm::Triple::FreeBSD: 9362 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9363 case llvm::Triple::NetBSD: 9364 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9365 case llvm::Triple::NaCl: 9366 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9367 default: 9368 return new MipsTargetInfo(Triple, Opts); 9369 } 9370 9371 case llvm::Triple::mips64: 9372 switch (os) { 9373 case llvm::Triple::Linux: 9374 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9375 case llvm::Triple::RTEMS: 9376 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9377 case llvm::Triple::FreeBSD: 9378 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9379 case llvm::Triple::NetBSD: 9380 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9381 case llvm::Triple::OpenBSD: 9382 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9383 default: 9384 return new MipsTargetInfo(Triple, Opts); 9385 } 9386 9387 case llvm::Triple::mips64el: 9388 switch (os) { 9389 case llvm::Triple::Linux: 9390 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9391 case llvm::Triple::RTEMS: 9392 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9393 case llvm::Triple::FreeBSD: 9394 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9395 case llvm::Triple::NetBSD: 9396 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9397 case llvm::Triple::OpenBSD: 9398 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9399 default: 9400 return new MipsTargetInfo(Triple, Opts); 9401 } 9402 9403 case llvm::Triple::le32: 9404 switch (os) { 9405 case llvm::Triple::NaCl: 9406 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9407 default: 9408 return nullptr; 9409 } 9410 9411 case llvm::Triple::le64: 9412 return new Le64TargetInfo(Triple, Opts); 9413 9414 case llvm::Triple::ppc: 9415 if (Triple.isOSDarwin()) 9416 return new DarwinPPC32TargetInfo(Triple, Opts); 9417 switch (os) { 9418 case llvm::Triple::Linux: 9419 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9420 case llvm::Triple::FreeBSD: 9421 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9422 case llvm::Triple::NetBSD: 9423 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9424 case llvm::Triple::OpenBSD: 9425 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9426 case llvm::Triple::RTEMS: 9427 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9428 default: 9429 return new PPC32TargetInfo(Triple, Opts); 9430 } 9431 9432 case llvm::Triple::ppc64: 9433 if (Triple.isOSDarwin()) 9434 return new DarwinPPC64TargetInfo(Triple, Opts); 9435 switch (os) { 9436 case llvm::Triple::Linux: 9437 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9438 case llvm::Triple::Lv2: 9439 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9440 case llvm::Triple::FreeBSD: 9441 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9442 case llvm::Triple::NetBSD: 9443 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9444 default: 9445 return new PPC64TargetInfo(Triple, Opts); 9446 } 9447 9448 case llvm::Triple::ppc64le: 9449 switch (os) { 9450 case llvm::Triple::Linux: 9451 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9452 case llvm::Triple::NetBSD: 9453 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9454 default: 9455 return new PPC64TargetInfo(Triple, Opts); 9456 } 9457 9458 case llvm::Triple::nvptx: 9459 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9460 case llvm::Triple::nvptx64: 9461 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9462 9463 case llvm::Triple::amdgcn: 9464 case llvm::Triple::r600: 9465 return new AMDGPUTargetInfo(Triple, Opts); 9466 9467 case llvm::Triple::sparc: 9468 switch (os) { 9469 case llvm::Triple::Linux: 9470 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9471 case llvm::Triple::Solaris: 9472 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9473 case llvm::Triple::NetBSD: 9474 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9475 case llvm::Triple::OpenBSD: 9476 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9477 case llvm::Triple::RTEMS: 9478 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9479 default: 9480 return new SparcV8TargetInfo(Triple, Opts); 9481 } 9482 9483 // The 'sparcel' architecture copies all the above cases except for Solaris. 9484 case llvm::Triple::sparcel: 9485 switch (os) { 9486 case llvm::Triple::Linux: 9487 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9488 case llvm::Triple::NetBSD: 9489 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9490 case llvm::Triple::OpenBSD: 9491 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9492 case llvm::Triple::RTEMS: 9493 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9494 default: 9495 return new SparcV8elTargetInfo(Triple, Opts); 9496 } 9497 9498 case llvm::Triple::sparcv9: 9499 switch (os) { 9500 case llvm::Triple::Linux: 9501 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9502 case llvm::Triple::Solaris: 9503 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9504 case llvm::Triple::NetBSD: 9505 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9506 case llvm::Triple::OpenBSD: 9507 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9508 case llvm::Triple::FreeBSD: 9509 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9510 default: 9511 return new SparcV9TargetInfo(Triple, Opts); 9512 } 9513 9514 case llvm::Triple::systemz: 9515 switch (os) { 9516 case llvm::Triple::Linux: 9517 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9518 default: 9519 return new SystemZTargetInfo(Triple, Opts); 9520 } 9521 9522 case llvm::Triple::tce: 9523 return new TCETargetInfo(Triple, Opts); 9524 9525 case llvm::Triple::tcele: 9526 return new TCELETargetInfo(Triple, Opts); 9527 9528 case llvm::Triple::x86: 9529 if (Triple.isOSDarwin()) 9530 return new DarwinI386TargetInfo(Triple, Opts); 9531 9532 switch (os) { 9533 case llvm::Triple::CloudABI: 9534 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9535 case llvm::Triple::Linux: { 9536 switch (Triple.getEnvironment()) { 9537 default: 9538 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9539 case llvm::Triple::Android: 9540 return new AndroidX86_32TargetInfo(Triple, Opts); 9541 } 9542 } 9543 case llvm::Triple::DragonFly: 9544 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9545 case llvm::Triple::NetBSD: 9546 return new NetBSDI386TargetInfo(Triple, Opts); 9547 case llvm::Triple::OpenBSD: 9548 return new OpenBSDI386TargetInfo(Triple, Opts); 9549 case llvm::Triple::Bitrig: 9550 return new BitrigI386TargetInfo(Triple, Opts); 9551 case llvm::Triple::FreeBSD: 9552 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9553 case llvm::Triple::KFreeBSD: 9554 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9555 case llvm::Triple::Minix: 9556 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9557 case llvm::Triple::Solaris: 9558 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9559 case llvm::Triple::Win32: { 9560 switch (Triple.getEnvironment()) { 9561 case llvm::Triple::Cygnus: 9562 return new CygwinX86_32TargetInfo(Triple, Opts); 9563 case llvm::Triple::GNU: 9564 return new MinGWX86_32TargetInfo(Triple, Opts); 9565 case llvm::Triple::Itanium: 9566 case llvm::Triple::MSVC: 9567 default: // Assume MSVC for unknown environments 9568 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9569 } 9570 } 9571 case llvm::Triple::Haiku: 9572 return new HaikuX86_32TargetInfo(Triple, Opts); 9573 case llvm::Triple::RTEMS: 9574 return new RTEMSX86_32TargetInfo(Triple, Opts); 9575 case llvm::Triple::NaCl: 9576 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9577 case llvm::Triple::ELFIAMCU: 9578 return new MCUX86_32TargetInfo(Triple, Opts); 9579 default: 9580 return new X86_32TargetInfo(Triple, Opts); 9581 } 9582 9583 case llvm::Triple::x86_64: 9584 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9585 return new DarwinX86_64TargetInfo(Triple, Opts); 9586 9587 switch (os) { 9588 case llvm::Triple::CloudABI: 9589 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9590 case llvm::Triple::Linux: { 9591 switch (Triple.getEnvironment()) { 9592 default: 9593 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9594 case llvm::Triple::Android: 9595 return new AndroidX86_64TargetInfo(Triple, Opts); 9596 } 9597 } 9598 case llvm::Triple::DragonFly: 9599 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9600 case llvm::Triple::NetBSD: 9601 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9602 case llvm::Triple::OpenBSD: 9603 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9604 case llvm::Triple::Bitrig: 9605 return new BitrigX86_64TargetInfo(Triple, Opts); 9606 case llvm::Triple::FreeBSD: 9607 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9608 case llvm::Triple::Fuchsia: 9609 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9610 case llvm::Triple::KFreeBSD: 9611 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9612 case llvm::Triple::Solaris: 9613 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9614 case llvm::Triple::Win32: { 9615 switch (Triple.getEnvironment()) { 9616 case llvm::Triple::Cygnus: 9617 return new CygwinX86_64TargetInfo(Triple, Opts); 9618 case llvm::Triple::GNU: 9619 return new MinGWX86_64TargetInfo(Triple, Opts); 9620 case llvm::Triple::MSVC: 9621 default: // Assume MSVC for unknown environments 9622 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9623 } 9624 } 9625 case llvm::Triple::Haiku: 9626 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9627 case llvm::Triple::NaCl: 9628 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9629 case llvm::Triple::PS4: 9630 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9631 default: 9632 return new X86_64TargetInfo(Triple, Opts); 9633 } 9634 9635 case llvm::Triple::spir: { 9636 if (Triple.getOS() != llvm::Triple::UnknownOS || 9637 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9638 return nullptr; 9639 return new SPIR32TargetInfo(Triple, Opts); 9640 } 9641 case llvm::Triple::spir64: { 9642 if (Triple.getOS() != llvm::Triple::UnknownOS || 9643 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9644 return nullptr; 9645 return new SPIR64TargetInfo(Triple, Opts); 9646 } 9647 case llvm::Triple::wasm32: 9648 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9649 Triple.getVendor() != llvm::Triple::UnknownVendor || 9650 Triple.getOS() != llvm::Triple::UnknownOS || 9651 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9652 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9653 return nullptr; 9654 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9655 case llvm::Triple::wasm64: 9656 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9657 Triple.getVendor() != llvm::Triple::UnknownVendor || 9658 Triple.getOS() != llvm::Triple::UnknownOS || 9659 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9660 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9661 return nullptr; 9662 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9663 9664 case llvm::Triple::renderscript32: 9665 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9666 case llvm::Triple::renderscript64: 9667 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9668 } 9669 } 9670 9671 /// CreateTargetInfo - Return the target info object for the specified target 9672 /// options. 9673 TargetInfo * 9674 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9675 const std::shared_ptr<TargetOptions> &Opts) { 9676 llvm::Triple Triple(Opts->Triple); 9677 9678 // Construct the target 9679 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9680 if (!Target) { 9681 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9682 return nullptr; 9683 } 9684 Target->TargetOpts = Opts; 9685 9686 // Set the target CPU if specified. 9687 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9688 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9689 return nullptr; 9690 } 9691 9692 // Set the target ABI if specified. 9693 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9694 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9695 return nullptr; 9696 } 9697 9698 // Set the fp math unit. 9699 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9700 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9701 return nullptr; 9702 } 9703 9704 // Compute the default target features, we need the target to handle this 9705 // because features may have dependencies on one another. 9706 llvm::StringMap<bool> Features; 9707 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9708 Opts->FeaturesAsWritten)) 9709 return nullptr; 9710 9711 // Add the features to the compile options. 9712 Opts->Features.clear(); 9713 for (const auto &F : Features) 9714 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9715 9716 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9717 return nullptr; 9718 9719 Target->setSupportedOpenCLOpts(); 9720 Target->setOpenCLExtensionOpts(); 9721 9722 if (!Target->validateTarget(Diags)) 9723 return nullptr; 9724 9725 return Target.release(); 9726 } 9727