1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include "llvm/Type.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const std::string& triple) : TgtInfo(triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "5621"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.AddressSanitizer) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.getOS() == llvm::Triple::IOS) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", Str); 152 } else { 153 // Note that the Driver allows versions which aren't representable in the 154 // define (because we only get a single digit for the minor and micro 155 // revision numbers). So, we limit them to the maximum representable 156 // version. 157 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[5]; 160 Str[0] = '0' + (Maj / 10); 161 Str[1] = '0' + (Maj % 10); 162 Str[2] = '0' + std::min(Min, 9U); 163 Str[3] = '0' + std::min(Rev, 9U); 164 Str[4] = '\0'; 165 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 166 } 167 168 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 169 } 170 171 namespace { 172 template<typename Target> 173 class DarwinTargetInfo : public OSTargetInfo<Target> { 174 protected: 175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 176 MacroBuilder &Builder) const { 177 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 178 this->PlatformMinVersion); 179 } 180 181 public: 182 DarwinTargetInfo(const std::string& triple) : 183 OSTargetInfo<Target>(triple) { 184 llvm::Triple T = llvm::Triple(triple); 185 this->TLSSupported = T.isMacOSX() && !T.isMacOSXVersionLT(10,7); 186 this->MCountName = "\01mcount"; 187 } 188 189 virtual std::string isValidSectionSpecifier(StringRef SR) const { 190 // Let MCSectionMachO validate this. 191 StringRef Segment, Section; 192 unsigned TAA, StubSize; 193 bool HasTAA; 194 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 195 TAA, HasTAA, StubSize); 196 } 197 198 virtual const char *getStaticInitSectionSpecifier() const { 199 // FIXME: We should return 0 when building kexts. 200 return "__TEXT,__StaticInit,regular,pure_instructions"; 201 } 202 203 /// Darwin does not support protected visibility. Darwin's "default" 204 /// is very similar to ELF's "protected"; Darwin requires a "weak" 205 /// attribute on declarations that can be dynamically replaced. 206 virtual bool hasProtectedVisibility() const { 207 return false; 208 } 209 }; 210 211 212 // DragonFlyBSD Target 213 template<typename Target> 214 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 215 protected: 216 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 217 MacroBuilder &Builder) const { 218 // DragonFly defines; list based off of gcc output 219 Builder.defineMacro("__DragonFly__"); 220 Builder.defineMacro("__DragonFly_cc_version", "100001"); 221 Builder.defineMacro("__ELF__"); 222 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 223 Builder.defineMacro("__tune_i386__"); 224 DefineStd(Builder, "unix", Opts); 225 } 226 public: 227 DragonFlyBSDTargetInfo(const std::string &triple) 228 : OSTargetInfo<Target>(triple) { 229 this->UserLabelPrefix = ""; 230 231 llvm::Triple Triple(triple); 232 switch (Triple.getArch()) { 233 default: 234 case llvm::Triple::x86: 235 case llvm::Triple::x86_64: 236 this->MCountName = ".mcount"; 237 break; 238 } 239 } 240 }; 241 242 // FreeBSD Target 243 template<typename Target> 244 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 245 protected: 246 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 247 MacroBuilder &Builder) const { 248 // FreeBSD defines; list based off of gcc output 249 250 unsigned Release = Triple.getOSMajorVersion(); 251 if (Release == 0U) 252 Release = 8; 253 254 Builder.defineMacro("__FreeBSD__", Twine(Release)); 255 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 256 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 257 DefineStd(Builder, "unix", Opts); 258 Builder.defineMacro("__ELF__"); 259 } 260 public: 261 FreeBSDTargetInfo(const std::string &triple) 262 : OSTargetInfo<Target>(triple) { 263 this->UserLabelPrefix = ""; 264 265 llvm::Triple Triple(triple); 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 case llvm::Triple::mips: 273 case llvm::Triple::mipsel: 274 case llvm::Triple::ppc: 275 case llvm::Triple::ppc64: 276 this->MCountName = "_mcount"; 277 break; 278 case llvm::Triple::arm: 279 this->MCountName = "__mcount"; 280 break; 281 } 282 283 } 284 }; 285 286 // Minix Target 287 template<typename Target> 288 class MinixTargetInfo : public OSTargetInfo<Target> { 289 protected: 290 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 291 MacroBuilder &Builder) const { 292 // Minix defines 293 294 Builder.defineMacro("__minix", "3"); 295 Builder.defineMacro("_EM_WSIZE", "4"); 296 Builder.defineMacro("_EM_PSIZE", "4"); 297 Builder.defineMacro("_EM_SSIZE", "2"); 298 Builder.defineMacro("_EM_LSIZE", "4"); 299 Builder.defineMacro("_EM_FSIZE", "4"); 300 Builder.defineMacro("_EM_DSIZE", "8"); 301 Builder.defineMacro("__ELF__"); 302 DefineStd(Builder, "unix", Opts); 303 } 304 public: 305 MinixTargetInfo(const std::string &triple) 306 : OSTargetInfo<Target>(triple) { 307 this->UserLabelPrefix = ""; 308 } 309 }; 310 311 // Linux target 312 template<typename Target> 313 class LinuxTargetInfo : public OSTargetInfo<Target> { 314 protected: 315 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 316 MacroBuilder &Builder) const { 317 // Linux defines; list based off of gcc output 318 DefineStd(Builder, "unix", Opts); 319 DefineStd(Builder, "linux", Opts); 320 Builder.defineMacro("__gnu_linux__"); 321 Builder.defineMacro("__ELF__"); 322 if (Triple.getEnvironment() == llvm::Triple::Android) 323 Builder.defineMacro("__ANDROID__", "1"); 324 if (Opts.POSIXThreads) 325 Builder.defineMacro("_REENTRANT"); 326 if (Opts.CPlusPlus) 327 Builder.defineMacro("_GNU_SOURCE"); 328 } 329 public: 330 LinuxTargetInfo(const std::string& triple) 331 : OSTargetInfo<Target>(triple) { 332 this->UserLabelPrefix = ""; 333 this->WIntType = TargetInfo::UnsignedInt; 334 } 335 336 virtual const char *getStaticInitSectionSpecifier() const { 337 return ".text.startup"; 338 } 339 }; 340 341 // NetBSD Target 342 template<typename Target> 343 class NetBSDTargetInfo : public OSTargetInfo<Target> { 344 protected: 345 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 346 MacroBuilder &Builder) const { 347 // NetBSD defines; list based off of gcc output 348 Builder.defineMacro("__NetBSD__"); 349 Builder.defineMacro("__unix__"); 350 Builder.defineMacro("__ELF__"); 351 if (Opts.POSIXThreads) 352 Builder.defineMacro("_POSIX_THREADS"); 353 } 354 public: 355 NetBSDTargetInfo(const std::string &triple) 356 : OSTargetInfo<Target>(triple) { 357 this->UserLabelPrefix = ""; 358 } 359 }; 360 361 // OpenBSD Target 362 template<typename Target> 363 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 364 protected: 365 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 366 MacroBuilder &Builder) const { 367 // OpenBSD defines; list based off of gcc output 368 369 Builder.defineMacro("__OpenBSD__"); 370 DefineStd(Builder, "unix", Opts); 371 Builder.defineMacro("__ELF__"); 372 if (Opts.POSIXThreads) 373 Builder.defineMacro("_REENTRANT"); 374 } 375 public: 376 OpenBSDTargetInfo(const std::string &triple) 377 : OSTargetInfo<Target>(triple) { 378 this->UserLabelPrefix = ""; 379 this->TLSSupported = false; 380 381 llvm::Triple Triple(triple); 382 switch (Triple.getArch()) { 383 default: 384 case llvm::Triple::x86: 385 case llvm::Triple::x86_64: 386 case llvm::Triple::arm: 387 case llvm::Triple::sparc: 388 this->MCountName = "__mcount"; 389 break; 390 case llvm::Triple::mips64: 391 case llvm::Triple::mips64el: 392 case llvm::Triple::ppc: 393 case llvm::Triple::sparcv9: 394 this->MCountName = "_mcount"; 395 break; 396 } 397 } 398 }; 399 400 // Bitrig Target 401 template<typename Target> 402 class BitrigTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const { 406 // Bitrig defines; list based off of gcc output 407 408 Builder.defineMacro("__Bitrig__"); 409 DefineStd(Builder, "unix", Opts); 410 Builder.defineMacro("__ELF__"); 411 if (Opts.POSIXThreads) 412 Builder.defineMacro("_REENTRANT"); 413 } 414 public: 415 BitrigTargetInfo(const std::string &triple) 416 : OSTargetInfo<Target>(triple) { 417 this->UserLabelPrefix = ""; 418 this->TLSSupported = false; 419 this->MCountName = "__mcount"; 420 } 421 }; 422 423 // PSP Target 424 template<typename Target> 425 class PSPTargetInfo : public OSTargetInfo<Target> { 426 protected: 427 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 428 MacroBuilder &Builder) const { 429 // PSP defines; list based on the output of the pspdev gcc toolchain. 430 Builder.defineMacro("PSP"); 431 Builder.defineMacro("_PSP"); 432 Builder.defineMacro("__psp__"); 433 Builder.defineMacro("__ELF__"); 434 } 435 public: 436 PSPTargetInfo(const std::string& triple) 437 : OSTargetInfo<Target>(triple) { 438 this->UserLabelPrefix = ""; 439 } 440 }; 441 442 // PS3 PPU Target 443 template<typename Target> 444 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 445 protected: 446 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 447 MacroBuilder &Builder) const { 448 // PS3 PPU defines. 449 Builder.defineMacro("__PPC__"); 450 Builder.defineMacro("__PPU__"); 451 Builder.defineMacro("__CELLOS_LV2__"); 452 Builder.defineMacro("__ELF__"); 453 Builder.defineMacro("__LP32__"); 454 Builder.defineMacro("_ARCH_PPC64"); 455 Builder.defineMacro("__powerpc64__"); 456 } 457 public: 458 PS3PPUTargetInfo(const std::string& triple) 459 : OSTargetInfo<Target>(triple) { 460 this->UserLabelPrefix = ""; 461 this->LongWidth = this->LongAlign = 32; 462 this->PointerWidth = this->PointerAlign = 32; 463 this->IntMaxType = TargetInfo::SignedLongLong; 464 this->UIntMaxType = TargetInfo::UnsignedLongLong; 465 this->Int64Type = TargetInfo::SignedLongLong; 466 this->SizeType = TargetInfo::UnsignedInt; 467 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 468 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 469 } 470 }; 471 472 // FIXME: Need a real SPU target. 473 // PS3 SPU Target 474 template<typename Target> 475 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 476 protected: 477 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 478 MacroBuilder &Builder) const { 479 // PS3 PPU defines. 480 Builder.defineMacro("__SPU__"); 481 Builder.defineMacro("__ELF__"); 482 } 483 public: 484 PS3SPUTargetInfo(const std::string& triple) 485 : OSTargetInfo<Target>(triple) { 486 this->UserLabelPrefix = ""; 487 } 488 }; 489 490 // AuroraUX target 491 template<typename Target> 492 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 493 protected: 494 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 495 MacroBuilder &Builder) const { 496 DefineStd(Builder, "sun", Opts); 497 DefineStd(Builder, "unix", Opts); 498 Builder.defineMacro("__ELF__"); 499 Builder.defineMacro("__svr4__"); 500 Builder.defineMacro("__SVR4"); 501 } 502 public: 503 AuroraUXTargetInfo(const std::string& triple) 504 : OSTargetInfo<Target>(triple) { 505 this->UserLabelPrefix = ""; 506 this->WCharType = this->SignedLong; 507 // FIXME: WIntType should be SignedLong 508 } 509 }; 510 511 // Solaris target 512 template<typename Target> 513 class SolarisTargetInfo : public OSTargetInfo<Target> { 514 protected: 515 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 516 MacroBuilder &Builder) const { 517 DefineStd(Builder, "sun", Opts); 518 DefineStd(Builder, "unix", Opts); 519 Builder.defineMacro("__ELF__"); 520 Builder.defineMacro("__svr4__"); 521 Builder.defineMacro("__SVR4"); 522 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 523 // newer, but to 500 for everything else. feature_test.h has a check to 524 // ensure that you are not using C99 with an old version of X/Open or C89 525 // with a new version. 526 if (Opts.C99 || Opts.C11) 527 Builder.defineMacro("_XOPEN_SOURCE", "600"); 528 else 529 Builder.defineMacro("_XOPEN_SOURCE", "500"); 530 if (Opts.CPlusPlus) 531 Builder.defineMacro("__C99FEATURES__"); 532 Builder.defineMacro("_LARGEFILE_SOURCE"); 533 Builder.defineMacro("_LARGEFILE64_SOURCE"); 534 Builder.defineMacro("__EXTENSIONS__"); 535 Builder.defineMacro("_REENTRANT"); 536 } 537 public: 538 SolarisTargetInfo(const std::string& triple) 539 : OSTargetInfo<Target>(triple) { 540 this->UserLabelPrefix = ""; 541 this->WCharType = this->SignedInt; 542 // FIXME: WIntType should be SignedLong 543 } 544 }; 545 546 // Windows target 547 template<typename Target> 548 class WindowsTargetInfo : public OSTargetInfo<Target> { 549 protected: 550 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 551 MacroBuilder &Builder) const { 552 Builder.defineMacro("_WIN32"); 553 } 554 void getVisualStudioDefines(const LangOptions &Opts, 555 MacroBuilder &Builder) const { 556 if (Opts.CPlusPlus) { 557 if (Opts.RTTI) 558 Builder.defineMacro("_CPPRTTI"); 559 560 if (Opts.Exceptions) 561 Builder.defineMacro("_CPPUNWIND"); 562 } 563 564 if (!Opts.CharIsSigned) 565 Builder.defineMacro("_CHAR_UNSIGNED"); 566 567 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 568 // but it works for now. 569 if (Opts.POSIXThreads) 570 Builder.defineMacro("_MT"); 571 572 if (Opts.MSCVersion != 0) 573 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 574 575 if (Opts.MicrosoftExt) { 576 Builder.defineMacro("_MSC_EXTENSIONS"); 577 578 if (Opts.CPlusPlus0x) { 579 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 580 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 581 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 582 } 583 } 584 585 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 586 } 587 588 public: 589 WindowsTargetInfo(const std::string &triple) 590 : OSTargetInfo<Target>(triple) {} 591 }; 592 593 } // end anonymous namespace. 594 595 //===----------------------------------------------------------------------===// 596 // Specific target implementations. 597 //===----------------------------------------------------------------------===// 598 599 namespace { 600 // PPC abstract base class 601 class PPCTargetInfo : public TargetInfo { 602 static const Builtin::Info BuiltinInfo[]; 603 static const char * const GCCRegNames[]; 604 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 605 std::string CPU; 606 public: 607 PPCTargetInfo(const std::string& triple) : TargetInfo(triple) { 608 LongDoubleWidth = LongDoubleAlign = 128; 609 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 610 } 611 612 /// \brief Flags for architecture specific defines. 613 typedef enum { 614 ArchDefineNone = 0, 615 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 616 ArchDefinePpcgr = 1 << 1, 617 ArchDefinePpcsq = 1 << 2, 618 ArchDefine440 = 1 << 3, 619 ArchDefine603 = 1 << 4, 620 ArchDefine604 = 1 << 5, 621 ArchDefinePwr4 = 1 << 6, 622 ArchDefinePwr6 = 1 << 7 623 } ArchDefineTypes; 624 625 virtual bool setCPU(const std::string &Name) { 626 bool CPUKnown = llvm::StringSwitch<bool>(Name) 627 .Case("generic", true) 628 .Case("440", true) 629 .Case("450", true) 630 .Case("601", true) 631 .Case("602", true) 632 .Case("603", true) 633 .Case("603e", true) 634 .Case("603ev", true) 635 .Case("604", true) 636 .Case("604e", true) 637 .Case("620", true) 638 .Case("g3", true) 639 .Case("7400", true) 640 .Case("g4", true) 641 .Case("7450", true) 642 .Case("g4+", true) 643 .Case("750", true) 644 .Case("970", true) 645 .Case("g5", true) 646 .Case("a2", true) 647 .Case("e500mc", true) 648 .Case("e5500", true) 649 .Case("pwr6", true) 650 .Case("pwr7", true) 651 .Case("ppc", true) 652 .Case("ppc64", true) 653 .Default(false); 654 655 if (CPUKnown) 656 CPU = Name; 657 658 return CPUKnown; 659 } 660 661 virtual void getTargetBuiltins(const Builtin::Info *&Records, 662 unsigned &NumRecords) const { 663 Records = BuiltinInfo; 664 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 665 } 666 667 virtual bool isCLZForZeroUndef() const { return false; } 668 669 virtual void getTargetDefines(const LangOptions &Opts, 670 MacroBuilder &Builder) const; 671 672 virtual bool hasFeature(StringRef Feature) const; 673 674 virtual void getGCCRegNames(const char * const *&Names, 675 unsigned &NumNames) const; 676 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 677 unsigned &NumAliases) const; 678 virtual bool validateAsmConstraint(const char *&Name, 679 TargetInfo::ConstraintInfo &Info) const { 680 switch (*Name) { 681 default: return false; 682 case 'O': // Zero 683 break; 684 case 'b': // Base register 685 case 'f': // Floating point register 686 Info.setAllowsRegister(); 687 break; 688 // FIXME: The following are added to allow parsing. 689 // I just took a guess at what the actions should be. 690 // Also, is more specific checking needed? I.e. specific registers? 691 case 'd': // Floating point register (containing 64-bit value) 692 case 'v': // Altivec vector register 693 Info.setAllowsRegister(); 694 break; 695 case 'w': 696 switch (Name[1]) { 697 case 'd':// VSX vector register to hold vector double data 698 case 'f':// VSX vector register to hold vector float data 699 case 's':// VSX vector register to hold scalar float data 700 case 'a':// Any VSX register 701 break; 702 default: 703 return false; 704 } 705 Info.setAllowsRegister(); 706 Name++; // Skip over 'w'. 707 break; 708 case 'h': // `MQ', `CTR', or `LINK' register 709 case 'q': // `MQ' register 710 case 'c': // `CTR' register 711 case 'l': // `LINK' register 712 case 'x': // `CR' register (condition register) number 0 713 case 'y': // `CR' register (condition register) 714 case 'z': // `XER[CA]' carry bit (part of the XER register) 715 Info.setAllowsRegister(); 716 break; 717 case 'I': // Signed 16-bit constant 718 case 'J': // Unsigned 16-bit constant shifted left 16 bits 719 // (use `L' instead for SImode constants) 720 case 'K': // Unsigned 16-bit constant 721 case 'L': // Signed 16-bit constant shifted left 16 bits 722 case 'M': // Constant larger than 31 723 case 'N': // Exact power of 2 724 case 'P': // Constant whose negation is a signed 16-bit constant 725 case 'G': // Floating point constant that can be loaded into a 726 // register with one instruction per word 727 case 'H': // Integer/Floating point constant that can be loaded 728 // into a register using three instructions 729 break; 730 case 'm': // Memory operand. Note that on PowerPC targets, m can 731 // include addresses that update the base register. It 732 // is therefore only safe to use `m' in an asm statement 733 // if that asm statement accesses the operand exactly once. 734 // The asm statement must also use `%U<opno>' as a 735 // placeholder for the "update" flag in the corresponding 736 // load or store instruction. For example: 737 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 738 // is correct but: 739 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 740 // is not. Use es rather than m if you don't want the base 741 // register to be updated. 742 case 'e': 743 if (Name[1] != 's') 744 return false; 745 // es: A "stable" memory operand; that is, one which does not 746 // include any automodification of the base register. Unlike 747 // `m', this constraint can be used in asm statements that 748 // might access the operand several times, or that might not 749 // access it at all. 750 Info.setAllowsMemory(); 751 Name++; // Skip over 'e'. 752 break; 753 case 'Q': // Memory operand that is an offset from a register (it is 754 // usually better to use `m' or `es' in asm statements) 755 case 'Z': // Memory operand that is an indexed or indirect from a 756 // register (it is usually better to use `m' or `es' in 757 // asm statements) 758 Info.setAllowsMemory(); 759 Info.setAllowsRegister(); 760 break; 761 case 'R': // AIX TOC entry 762 case 'a': // Address operand that is an indexed or indirect from a 763 // register (`p' is preferable for asm statements) 764 case 'S': // Constant suitable as a 64-bit mask operand 765 case 'T': // Constant suitable as a 32-bit mask operand 766 case 'U': // System V Release 4 small data area reference 767 case 't': // AND masks that can be performed by two rldic{l, r} 768 // instructions 769 case 'W': // Vector constant that does not require memory 770 case 'j': // Vector constant that is all zeros. 771 break; 772 // End FIXME. 773 } 774 return true; 775 } 776 virtual const char *getClobbers() const { 777 return ""; 778 } 779 }; 780 781 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 782 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 783 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 784 ALL_LANGUAGES }, 785 #include "clang/Basic/BuiltinsPPC.def" 786 }; 787 788 789 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 790 /// #defines that are not tied to a specific subtarget. 791 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 792 MacroBuilder &Builder) const { 793 // Target identification. 794 Builder.defineMacro("__ppc__"); 795 Builder.defineMacro("_ARCH_PPC"); 796 Builder.defineMacro("__powerpc__"); 797 Builder.defineMacro("__POWERPC__"); 798 if (PointerWidth == 64) { 799 Builder.defineMacro("_ARCH_PPC64"); 800 Builder.defineMacro("__powerpc64__"); 801 Builder.defineMacro("__ppc64__"); 802 } else { 803 Builder.defineMacro("__ppc__"); 804 } 805 806 // Target properties. 807 if (getTriple().getOS() != llvm::Triple::NetBSD && 808 getTriple().getOS() != llvm::Triple::OpenBSD) 809 Builder.defineMacro("_BIG_ENDIAN"); 810 Builder.defineMacro("__BIG_ENDIAN__"); 811 812 // Subtarget options. 813 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 814 Builder.defineMacro("__REGISTER_PREFIX__", ""); 815 816 // FIXME: Should be controlled by command line option. 817 Builder.defineMacro("__LONG_DOUBLE_128__"); 818 819 if (Opts.AltiVec) { 820 Builder.defineMacro("__VEC__", "10206"); 821 Builder.defineMacro("__ALTIVEC__"); 822 } 823 824 // CPU identification. 825 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 826 .Case("440", ArchDefineName) 827 .Case("450", ArchDefineName | ArchDefine440) 828 .Case("601", ArchDefineName) 829 .Case("602", ArchDefineName | ArchDefinePpcgr) 830 .Case("603", ArchDefineName | ArchDefinePpcgr) 831 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 832 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 833 .Case("604", ArchDefineName | ArchDefinePpcgr) 834 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 835 .Case("620", ArchDefineName | ArchDefinePpcgr) 836 .Case("7400", ArchDefineName | ArchDefinePpcgr) 837 .Case("7450", ArchDefineName | ArchDefinePpcgr) 838 .Case("750", ArchDefineName | ArchDefinePpcgr) 839 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 840 | ArchDefinePpcsq) 841 .Case("pwr6", ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 842 .Case("pwr7", ArchDefineName | ArchDefinePwr6 | ArchDefinePpcgr 843 | ArchDefinePpcsq) 844 .Default(ArchDefineNone); 845 846 if (defs & ArchDefineName) 847 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 848 if (defs & ArchDefinePpcgr) 849 Builder.defineMacro("_ARCH_PPCGR"); 850 if (defs & ArchDefinePpcsq) 851 Builder.defineMacro("_ARCH_PPCSQ"); 852 if (defs & ArchDefine440) 853 Builder.defineMacro("_ARCH_440"); 854 if (defs & ArchDefine603) 855 Builder.defineMacro("_ARCH_603"); 856 if (defs & ArchDefine604) 857 Builder.defineMacro("_ARCH_604"); 858 if (defs & (ArchDefinePwr4 | ArchDefinePwr6)) 859 Builder.defineMacro("_ARCH_PWR4"); 860 if (defs & ArchDefinePwr6) { 861 Builder.defineMacro("_ARCH_PWR5"); 862 Builder.defineMacro("_ARCH_PWR6"); 863 } 864 } 865 866 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 867 return Feature == "powerpc"; 868 } 869 870 871 const char * const PPCTargetInfo::GCCRegNames[] = { 872 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 873 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 874 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 875 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 876 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 877 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 878 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 879 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 880 "mq", "lr", "ctr", "ap", 881 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 882 "xer", 883 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 884 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 885 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 886 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 887 "vrsave", "vscr", 888 "spe_acc", "spefscr", 889 "sfp" 890 }; 891 892 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 893 unsigned &NumNames) const { 894 Names = GCCRegNames; 895 NumNames = llvm::array_lengthof(GCCRegNames); 896 } 897 898 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 899 // While some of these aliases do map to different registers 900 // they still share the same register name. 901 { { "0" }, "r0" }, 902 { { "1"}, "r1" }, 903 { { "2" }, "r2" }, 904 { { "3" }, "r3" }, 905 { { "4" }, "r4" }, 906 { { "5" }, "r5" }, 907 { { "6" }, "r6" }, 908 { { "7" }, "r7" }, 909 { { "8" }, "r8" }, 910 { { "9" }, "r9" }, 911 { { "10" }, "r10" }, 912 { { "11" }, "r11" }, 913 { { "12" }, "r12" }, 914 { { "13" }, "r13" }, 915 { { "14" }, "r14" }, 916 { { "15" }, "r15" }, 917 { { "16" }, "r16" }, 918 { { "17" }, "r17" }, 919 { { "18" }, "r18" }, 920 { { "19" }, "r19" }, 921 { { "20" }, "r20" }, 922 { { "21" }, "r21" }, 923 { { "22" }, "r22" }, 924 { { "23" }, "r23" }, 925 { { "24" }, "r24" }, 926 { { "25" }, "r25" }, 927 { { "26" }, "r26" }, 928 { { "27" }, "r27" }, 929 { { "28" }, "r28" }, 930 { { "29" }, "r29" }, 931 { { "30" }, "r30" }, 932 { { "31" }, "r31" }, 933 { { "fr0" }, "f0" }, 934 { { "fr1" }, "f1" }, 935 { { "fr2" }, "f2" }, 936 { { "fr3" }, "f3" }, 937 { { "fr4" }, "f4" }, 938 { { "fr5" }, "f5" }, 939 { { "fr6" }, "f6" }, 940 { { "fr7" }, "f7" }, 941 { { "fr8" }, "f8" }, 942 { { "fr9" }, "f9" }, 943 { { "fr10" }, "f10" }, 944 { { "fr11" }, "f11" }, 945 { { "fr12" }, "f12" }, 946 { { "fr13" }, "f13" }, 947 { { "fr14" }, "f14" }, 948 { { "fr15" }, "f15" }, 949 { { "fr16" }, "f16" }, 950 { { "fr17" }, "f17" }, 951 { { "fr18" }, "f18" }, 952 { { "fr19" }, "f19" }, 953 { { "fr20" }, "f20" }, 954 { { "fr21" }, "f21" }, 955 { { "fr22" }, "f22" }, 956 { { "fr23" }, "f23" }, 957 { { "fr24" }, "f24" }, 958 { { "fr25" }, "f25" }, 959 { { "fr26" }, "f26" }, 960 { { "fr27" }, "f27" }, 961 { { "fr28" }, "f28" }, 962 { { "fr29" }, "f29" }, 963 { { "fr30" }, "f30" }, 964 { { "fr31" }, "f31" }, 965 { { "cc" }, "cr0" }, 966 }; 967 968 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 969 unsigned &NumAliases) const { 970 Aliases = GCCRegAliases; 971 NumAliases = llvm::array_lengthof(GCCRegAliases); 972 } 973 } // end anonymous namespace. 974 975 namespace { 976 class PPC32TargetInfo : public PPCTargetInfo { 977 public: 978 PPC32TargetInfo(const std::string &triple) : PPCTargetInfo(triple) { 979 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 980 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 981 982 switch (getTriple().getOS()) { 983 case llvm::Triple::Linux: 984 case llvm::Triple::FreeBSD: 985 case llvm::Triple::NetBSD: 986 SizeType = UnsignedInt; 987 PtrDiffType = SignedInt; 988 IntPtrType = SignedInt; 989 break; 990 default: 991 break; 992 } 993 994 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 995 LongDoubleWidth = LongDoubleAlign = 64; 996 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 997 } 998 } 999 1000 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1001 // This is the ELF definition, and is overridden by the Darwin sub-target 1002 return TargetInfo::PowerABIBuiltinVaList; 1003 } 1004 }; 1005 } // end anonymous namespace. 1006 1007 namespace { 1008 class PPC64TargetInfo : public PPCTargetInfo { 1009 public: 1010 PPC64TargetInfo(const std::string& triple) : PPCTargetInfo(triple) { 1011 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1012 IntMaxType = SignedLong; 1013 UIntMaxType = UnsignedLong; 1014 Int64Type = SignedLong; 1015 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1016 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1017 1018 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1019 LongDoubleWidth = LongDoubleAlign = 64; 1020 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1021 } 1022 } 1023 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1024 return TargetInfo::CharPtrBuiltinVaList; 1025 } 1026 }; 1027 } // end anonymous namespace. 1028 1029 1030 namespace { 1031 class DarwinPPC32TargetInfo : 1032 public DarwinTargetInfo<PPC32TargetInfo> { 1033 public: 1034 DarwinPPC32TargetInfo(const std::string& triple) 1035 : DarwinTargetInfo<PPC32TargetInfo>(triple) { 1036 HasAlignMac68kSupport = true; 1037 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1038 LongLongAlign = 32; 1039 SuitableAlign = 128; 1040 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1041 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1042 } 1043 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1044 return TargetInfo::CharPtrBuiltinVaList; 1045 } 1046 }; 1047 1048 class DarwinPPC64TargetInfo : 1049 public DarwinTargetInfo<PPC64TargetInfo> { 1050 public: 1051 DarwinPPC64TargetInfo(const std::string& triple) 1052 : DarwinTargetInfo<PPC64TargetInfo>(triple) { 1053 HasAlignMac68kSupport = true; 1054 SuitableAlign = 128; 1055 } 1056 }; 1057 } // end anonymous namespace. 1058 1059 namespace { 1060 static const unsigned NVPTXAddrSpaceMap[] = { 1061 1, // opencl_global 1062 3, // opencl_local 1063 4, // opencl_constant 1064 1, // cuda_device 1065 4, // cuda_constant 1066 3, // cuda_shared 1067 }; 1068 class NVPTXTargetInfo : public TargetInfo { 1069 static const char * const GCCRegNames[]; 1070 static const Builtin::Info BuiltinInfo[]; 1071 std::vector<llvm::StringRef> AvailableFeatures; 1072 public: 1073 NVPTXTargetInfo(const std::string& triple) : TargetInfo(triple) { 1074 BigEndian = false; 1075 TLSSupported = false; 1076 LongWidth = LongAlign = 64; 1077 AddrSpaceMap = &NVPTXAddrSpaceMap; 1078 // Define available target features 1079 // These must be defined in sorted order! 1080 NoAsmVariants = true; 1081 } 1082 virtual void getTargetDefines(const LangOptions &Opts, 1083 MacroBuilder &Builder) const { 1084 Builder.defineMacro("__PTX__"); 1085 Builder.defineMacro("__NVPTX__"); 1086 } 1087 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1088 unsigned &NumRecords) const { 1089 Records = BuiltinInfo; 1090 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1091 } 1092 virtual bool hasFeature(StringRef Feature) const { 1093 return Feature == "ptx" || Feature == "nvptx"; 1094 } 1095 1096 virtual void getGCCRegNames(const char * const *&Names, 1097 unsigned &NumNames) const; 1098 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1099 unsigned &NumAliases) const { 1100 // No aliases. 1101 Aliases = 0; 1102 NumAliases = 0; 1103 } 1104 virtual bool validateAsmConstraint(const char *&Name, 1105 TargetInfo::ConstraintInfo &info) const { 1106 // FIXME: implement 1107 return true; 1108 } 1109 virtual const char *getClobbers() const { 1110 // FIXME: Is this really right? 1111 return ""; 1112 } 1113 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1114 // FIXME: implement 1115 return TargetInfo::CharPtrBuiltinVaList; 1116 } 1117 virtual bool setCPU(const std::string &Name) { 1118 return Name == "sm_10" || Name == "sm_13" || Name == "sm_20"; 1119 } 1120 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1121 StringRef Name, 1122 bool Enabled) const; 1123 }; 1124 1125 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1126 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1127 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1128 ALL_LANGUAGES }, 1129 #include "clang/Basic/BuiltinsNVPTX.def" 1130 }; 1131 1132 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1133 "r0" 1134 }; 1135 1136 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1137 unsigned &NumNames) const { 1138 Names = GCCRegNames; 1139 NumNames = llvm::array_lengthof(GCCRegNames); 1140 } 1141 1142 bool NVPTXTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1143 StringRef Name, 1144 bool Enabled) const { 1145 if(std::binary_search(AvailableFeatures.begin(), AvailableFeatures.end(), 1146 Name)) { 1147 Features[Name] = Enabled; 1148 return true; 1149 } else { 1150 return false; 1151 } 1152 } 1153 1154 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1155 public: 1156 NVPTX32TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1157 PointerWidth = PointerAlign = 32; 1158 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1159 DescriptionString 1160 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1161 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1162 "n16:32:64"; 1163 } 1164 }; 1165 1166 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1167 public: 1168 NVPTX64TargetInfo(const std::string& triple) : NVPTXTargetInfo(triple) { 1169 PointerWidth = PointerAlign = 64; 1170 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1171 DescriptionString 1172 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1173 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1174 "n16:32:64"; 1175 } 1176 }; 1177 } 1178 1179 namespace { 1180 // MBlaze abstract base class 1181 class MBlazeTargetInfo : public TargetInfo { 1182 static const char * const GCCRegNames[]; 1183 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 1184 1185 public: 1186 MBlazeTargetInfo(const std::string& triple) : TargetInfo(triple) { 1187 DescriptionString = "E-p:32:32:32-i8:8:8-i16:16:16"; 1188 } 1189 1190 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1191 unsigned &NumRecords) const { 1192 // FIXME: Implement. 1193 Records = 0; 1194 NumRecords = 0; 1195 } 1196 1197 virtual void getTargetDefines(const LangOptions &Opts, 1198 MacroBuilder &Builder) const; 1199 1200 virtual bool hasFeature(StringRef Feature) const { 1201 return Feature == "mblaze"; 1202 } 1203 1204 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1205 return TargetInfo::CharPtrBuiltinVaList; 1206 } 1207 virtual const char *getTargetPrefix() const { 1208 return "mblaze"; 1209 } 1210 virtual void getGCCRegNames(const char * const *&Names, 1211 unsigned &NumNames) const; 1212 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1213 unsigned &NumAliases) const; 1214 virtual bool validateAsmConstraint(const char *&Name, 1215 TargetInfo::ConstraintInfo &Info) const { 1216 switch (*Name) { 1217 default: return false; 1218 case 'O': // Zero 1219 return true; 1220 case 'b': // Base register 1221 case 'f': // Floating point register 1222 Info.setAllowsRegister(); 1223 return true; 1224 } 1225 } 1226 virtual const char *getClobbers() const { 1227 return ""; 1228 } 1229 }; 1230 1231 /// MBlazeTargetInfo::getTargetDefines - Return a set of the MBlaze-specific 1232 /// #defines that are not tied to a specific subtarget. 1233 void MBlazeTargetInfo::getTargetDefines(const LangOptions &Opts, 1234 MacroBuilder &Builder) const { 1235 // Target identification. 1236 Builder.defineMacro("__microblaze__"); 1237 Builder.defineMacro("_ARCH_MICROBLAZE"); 1238 Builder.defineMacro("__MICROBLAZE__"); 1239 1240 // Target properties. 1241 Builder.defineMacro("_BIG_ENDIAN"); 1242 Builder.defineMacro("__BIG_ENDIAN__"); 1243 1244 // Subtarget options. 1245 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1246 } 1247 1248 1249 const char * const MBlazeTargetInfo::GCCRegNames[] = { 1250 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1251 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1252 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1253 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1254 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 1255 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 1256 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 1257 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 1258 "hi", "lo", "accum","rmsr", "$fcc1","$fcc2","$fcc3","$fcc4", 1259 "$fcc5","$fcc6","$fcc7","$ap", "$rap", "$frp" 1260 }; 1261 1262 void MBlazeTargetInfo::getGCCRegNames(const char * const *&Names, 1263 unsigned &NumNames) const { 1264 Names = GCCRegNames; 1265 NumNames = llvm::array_lengthof(GCCRegNames); 1266 } 1267 1268 const TargetInfo::GCCRegAlias MBlazeTargetInfo::GCCRegAliases[] = { 1269 { {"f0"}, "r0" }, 1270 { {"f1"}, "r1" }, 1271 { {"f2"}, "r2" }, 1272 { {"f3"}, "r3" }, 1273 { {"f4"}, "r4" }, 1274 { {"f5"}, "r5" }, 1275 { {"f6"}, "r6" }, 1276 { {"f7"}, "r7" }, 1277 { {"f8"}, "r8" }, 1278 { {"f9"}, "r9" }, 1279 { {"f10"}, "r10" }, 1280 { {"f11"}, "r11" }, 1281 { {"f12"}, "r12" }, 1282 { {"f13"}, "r13" }, 1283 { {"f14"}, "r14" }, 1284 { {"f15"}, "r15" }, 1285 { {"f16"}, "r16" }, 1286 { {"f17"}, "r17" }, 1287 { {"f18"}, "r18" }, 1288 { {"f19"}, "r19" }, 1289 { {"f20"}, "r20" }, 1290 { {"f21"}, "r21" }, 1291 { {"f22"}, "r22" }, 1292 { {"f23"}, "r23" }, 1293 { {"f24"}, "r24" }, 1294 { {"f25"}, "r25" }, 1295 { {"f26"}, "r26" }, 1296 { {"f27"}, "r27" }, 1297 { {"f28"}, "r28" }, 1298 { {"f29"}, "r29" }, 1299 { {"f30"}, "r30" }, 1300 { {"f31"}, "r31" }, 1301 }; 1302 1303 void MBlazeTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1304 unsigned &NumAliases) const { 1305 Aliases = GCCRegAliases; 1306 NumAliases = llvm::array_lengthof(GCCRegAliases); 1307 } 1308 } // end anonymous namespace. 1309 1310 namespace { 1311 // Namespace for x86 abstract base class 1312 const Builtin::Info BuiltinInfo[] = { 1313 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1314 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1315 ALL_LANGUAGES }, 1316 #include "clang/Basic/BuiltinsX86.def" 1317 }; 1318 1319 static const char* const GCCRegNames[] = { 1320 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1321 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1322 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1323 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1324 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1325 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1326 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1327 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1328 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1329 }; 1330 1331 const TargetInfo::AddlRegName AddlRegNames[] = { 1332 { { "al", "ah", "eax", "rax" }, 0 }, 1333 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1334 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1335 { { "dl", "dh", "edx", "rdx" }, 1 }, 1336 { { "esi", "rsi" }, 4 }, 1337 { { "edi", "rdi" }, 5 }, 1338 { { "esp", "rsp" }, 7 }, 1339 { { "ebp", "rbp" }, 6 }, 1340 }; 1341 1342 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1343 // most of the implementation can be shared. 1344 class X86TargetInfo : public TargetInfo { 1345 enum X86SSEEnum { 1346 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2 1347 } SSELevel; 1348 enum MMX3DNowEnum { 1349 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1350 } MMX3DNowLevel; 1351 1352 bool HasAES; 1353 bool HasPCLMUL; 1354 bool HasLZCNT; 1355 bool HasRDRND; 1356 bool HasBMI; 1357 bool HasBMI2; 1358 bool HasPOPCNT; 1359 bool HasSSE4a; 1360 bool HasFMA4; 1361 bool HasFMA; 1362 bool HasXOP; 1363 1364 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1365 /// 1366 /// Each enumeration represents a particular CPU supported by Clang. These 1367 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1368 enum CPUKind { 1369 CK_Generic, 1370 1371 /// \name i386 1372 /// i386-generation processors. 1373 //@{ 1374 CK_i386, 1375 //@} 1376 1377 /// \name i486 1378 /// i486-generation processors. 1379 //@{ 1380 CK_i486, 1381 CK_WinChipC6, 1382 CK_WinChip2, 1383 CK_C3, 1384 //@} 1385 1386 /// \name i586 1387 /// i586-generation processors, P5 microarchitecture based. 1388 //@{ 1389 CK_i586, 1390 CK_Pentium, 1391 CK_PentiumMMX, 1392 //@} 1393 1394 /// \name i686 1395 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1396 //@{ 1397 CK_i686, 1398 CK_PentiumPro, 1399 CK_Pentium2, 1400 CK_Pentium3, 1401 CK_Pentium3M, 1402 CK_PentiumM, 1403 CK_C3_2, 1404 1405 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1406 /// Clang however has some logic to suport this. 1407 // FIXME: Warn, deprecate, and potentially remove this. 1408 CK_Yonah, 1409 //@} 1410 1411 /// \name Netburst 1412 /// Netburst microarchitecture based processors. 1413 //@{ 1414 CK_Pentium4, 1415 CK_Pentium4M, 1416 CK_Prescott, 1417 CK_Nocona, 1418 //@} 1419 1420 /// \name Core 1421 /// Core microarchitecture based processors. 1422 //@{ 1423 CK_Core2, 1424 1425 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1426 /// codename which GCC no longer accepts as an option to -march, but Clang 1427 /// has some logic for recognizing it. 1428 // FIXME: Warn, deprecate, and potentially remove this. 1429 CK_Penryn, 1430 //@} 1431 1432 /// \name Atom 1433 /// Atom processors 1434 //@{ 1435 CK_Atom, 1436 //@} 1437 1438 /// \name Nehalem 1439 /// Nehalem microarchitecture based processors. 1440 //@{ 1441 CK_Corei7, 1442 CK_Corei7AVX, 1443 CK_CoreAVXi, 1444 CK_CoreAVX2, 1445 //@} 1446 1447 /// \name K6 1448 /// K6 architecture processors. 1449 //@{ 1450 CK_K6, 1451 CK_K6_2, 1452 CK_K6_3, 1453 //@} 1454 1455 /// \name K7 1456 /// K7 architecture processors. 1457 //@{ 1458 CK_Athlon, 1459 CK_AthlonThunderbird, 1460 CK_Athlon4, 1461 CK_AthlonXP, 1462 CK_AthlonMP, 1463 //@} 1464 1465 /// \name K8 1466 /// K8 architecture processors. 1467 //@{ 1468 CK_Athlon64, 1469 CK_Athlon64SSE3, 1470 CK_AthlonFX, 1471 CK_K8, 1472 CK_K8SSE3, 1473 CK_Opteron, 1474 CK_OpteronSSE3, 1475 CK_AMDFAM10, 1476 //@} 1477 1478 /// \name Bobcat 1479 /// Bobcat architecture processors. 1480 //@{ 1481 CK_BTVER1, 1482 //@} 1483 1484 /// \name Bulldozer 1485 /// Bulldozer architecture processors. 1486 //@{ 1487 CK_BDVER1, 1488 CK_BDVER2, 1489 //@} 1490 1491 /// This specification is deprecated and will be removed in the future. 1492 /// Users should prefer \see CK_K8. 1493 // FIXME: Warn on this when the CPU is set to it. 1494 CK_x86_64, 1495 //@} 1496 1497 /// \name Geode 1498 /// Geode processors. 1499 //@{ 1500 CK_Geode 1501 //@} 1502 } CPU; 1503 1504 public: 1505 X86TargetInfo(const std::string& triple) 1506 : TargetInfo(triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1507 HasAES(false), HasPCLMUL(false), HasLZCNT(false), HasRDRND(false), 1508 HasBMI(false), HasBMI2(false), HasPOPCNT(false), HasSSE4a(false), 1509 HasFMA4(false), HasFMA(false), HasXOP(false), CPU(CK_Generic) { 1510 BigEndian = false; 1511 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1512 } 1513 virtual unsigned getFloatEvalMethod() const { 1514 // X87 evaluates with 80 bits "long double" precision. 1515 return SSELevel == NoSSE ? 2 : 0; 1516 } 1517 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1518 unsigned &NumRecords) const { 1519 Records = BuiltinInfo; 1520 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1521 } 1522 virtual void getGCCRegNames(const char * const *&Names, 1523 unsigned &NumNames) const { 1524 Names = GCCRegNames; 1525 NumNames = llvm::array_lengthof(GCCRegNames); 1526 } 1527 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1528 unsigned &NumAliases) const { 1529 Aliases = 0; 1530 NumAliases = 0; 1531 } 1532 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1533 unsigned &NumNames) const { 1534 Names = AddlRegNames; 1535 NumNames = llvm::array_lengthof(AddlRegNames); 1536 } 1537 virtual bool validateAsmConstraint(const char *&Name, 1538 TargetInfo::ConstraintInfo &info) const; 1539 virtual std::string convertConstraint(const char *&Constraint) const; 1540 virtual const char *getClobbers() const { 1541 return "~{dirflag},~{fpsr},~{flags}"; 1542 } 1543 virtual void getTargetDefines(const LangOptions &Opts, 1544 MacroBuilder &Builder) const; 1545 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 1546 StringRef Name, 1547 bool Enabled) const; 1548 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1549 virtual bool hasFeature(StringRef Feature) const; 1550 virtual void HandleTargetFeatures(std::vector<std::string> &Features); 1551 virtual const char* getABI() const { 1552 if (PointerWidth == 64 && SSELevel >= AVX) 1553 return "avx"; 1554 else if (PointerWidth == 32 && MMX3DNowLevel == NoMMX3DNow) 1555 return "no-mmx"; 1556 return ""; 1557 } 1558 virtual bool setCPU(const std::string &Name) { 1559 CPU = llvm::StringSwitch<CPUKind>(Name) 1560 .Case("i386", CK_i386) 1561 .Case("i486", CK_i486) 1562 .Case("winchip-c6", CK_WinChipC6) 1563 .Case("winchip2", CK_WinChip2) 1564 .Case("c3", CK_C3) 1565 .Case("i586", CK_i586) 1566 .Case("pentium", CK_Pentium) 1567 .Case("pentium-mmx", CK_PentiumMMX) 1568 .Case("i686", CK_i686) 1569 .Case("pentiumpro", CK_PentiumPro) 1570 .Case("pentium2", CK_Pentium2) 1571 .Case("pentium3", CK_Pentium3) 1572 .Case("pentium3m", CK_Pentium3M) 1573 .Case("pentium-m", CK_PentiumM) 1574 .Case("c3-2", CK_C3_2) 1575 .Case("yonah", CK_Yonah) 1576 .Case("pentium4", CK_Pentium4) 1577 .Case("pentium4m", CK_Pentium4M) 1578 .Case("prescott", CK_Prescott) 1579 .Case("nocona", CK_Nocona) 1580 .Case("core2", CK_Core2) 1581 .Case("penryn", CK_Penryn) 1582 .Case("atom", CK_Atom) 1583 .Case("corei7", CK_Corei7) 1584 .Case("corei7-avx", CK_Corei7AVX) 1585 .Case("core-avx-i", CK_CoreAVXi) 1586 .Case("core-avx2", CK_CoreAVX2) 1587 .Case("k6", CK_K6) 1588 .Case("k6-2", CK_K6_2) 1589 .Case("k6-3", CK_K6_3) 1590 .Case("athlon", CK_Athlon) 1591 .Case("athlon-tbird", CK_AthlonThunderbird) 1592 .Case("athlon-4", CK_Athlon4) 1593 .Case("athlon-xp", CK_AthlonXP) 1594 .Case("athlon-mp", CK_AthlonMP) 1595 .Case("athlon64", CK_Athlon64) 1596 .Case("athlon64-sse3", CK_Athlon64SSE3) 1597 .Case("athlon-fx", CK_AthlonFX) 1598 .Case("k8", CK_K8) 1599 .Case("k8-sse3", CK_K8SSE3) 1600 .Case("opteron", CK_Opteron) 1601 .Case("opteron-sse3", CK_OpteronSSE3) 1602 .Case("amdfam10", CK_AMDFAM10) 1603 .Case("btver1", CK_BTVER1) 1604 .Case("bdver1", CK_BDVER1) 1605 .Case("bdver2", CK_BDVER2) 1606 .Case("x86-64", CK_x86_64) 1607 .Case("geode", CK_Geode) 1608 .Default(CK_Generic); 1609 1610 // Perform any per-CPU checks necessary to determine if this CPU is 1611 // acceptable. 1612 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1613 // invalid without explaining *why*. 1614 switch (CPU) { 1615 case CK_Generic: 1616 // No processor selected! 1617 return false; 1618 1619 case CK_i386: 1620 case CK_i486: 1621 case CK_WinChipC6: 1622 case CK_WinChip2: 1623 case CK_C3: 1624 case CK_i586: 1625 case CK_Pentium: 1626 case CK_PentiumMMX: 1627 case CK_i686: 1628 case CK_PentiumPro: 1629 case CK_Pentium2: 1630 case CK_Pentium3: 1631 case CK_Pentium3M: 1632 case CK_PentiumM: 1633 case CK_Yonah: 1634 case CK_C3_2: 1635 case CK_Pentium4: 1636 case CK_Pentium4M: 1637 case CK_Prescott: 1638 case CK_K6: 1639 case CK_K6_2: 1640 case CK_K6_3: 1641 case CK_Athlon: 1642 case CK_AthlonThunderbird: 1643 case CK_Athlon4: 1644 case CK_AthlonXP: 1645 case CK_AthlonMP: 1646 case CK_Geode: 1647 // Only accept certain architectures when compiling in 32-bit mode. 1648 if (PointerWidth != 32) 1649 return false; 1650 1651 // Fallthrough 1652 case CK_Nocona: 1653 case CK_Core2: 1654 case CK_Penryn: 1655 case CK_Atom: 1656 case CK_Corei7: 1657 case CK_Corei7AVX: 1658 case CK_CoreAVXi: 1659 case CK_CoreAVX2: 1660 case CK_Athlon64: 1661 case CK_Athlon64SSE3: 1662 case CK_AthlonFX: 1663 case CK_K8: 1664 case CK_K8SSE3: 1665 case CK_Opteron: 1666 case CK_OpteronSSE3: 1667 case CK_AMDFAM10: 1668 case CK_BTVER1: 1669 case CK_BDVER1: 1670 case CK_BDVER2: 1671 case CK_x86_64: 1672 return true; 1673 } 1674 llvm_unreachable("Unhandled CPU kind"); 1675 } 1676 1677 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1678 // We accept all non-ARM calling conventions 1679 return (CC == CC_X86ThisCall || 1680 CC == CC_X86FastCall || 1681 CC == CC_X86StdCall || 1682 CC == CC_C || 1683 CC == CC_X86Pascal) ? CCCR_OK : CCCR_Warning; 1684 } 1685 1686 virtual CallingConv getDefaultCallingConv() const { 1687 return CC_C; 1688 } 1689 }; 1690 1691 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1692 // FIXME: This should not be here. 1693 Features["3dnow"] = false; 1694 Features["3dnowa"] = false; 1695 Features["mmx"] = false; 1696 Features["sse"] = false; 1697 Features["sse2"] = false; 1698 Features["sse3"] = false; 1699 Features["ssse3"] = false; 1700 Features["sse41"] = false; 1701 Features["sse42"] = false; 1702 Features["sse4a"] = false; 1703 Features["aes"] = false; 1704 Features["pclmul"] = false; 1705 Features["avx"] = false; 1706 Features["avx2"] = false; 1707 Features["lzcnt"] = false; 1708 Features["rdrand"] = false; 1709 Features["bmi"] = false; 1710 Features["bmi2"] = false; 1711 Features["popcnt"] = false; 1712 Features["fma4"] = false; 1713 Features["fma"] = false; 1714 Features["xop"] = false; 1715 1716 // FIXME: This *really* should not be here. 1717 1718 // X86_64 always has SSE2. 1719 if (PointerWidth == 64) 1720 Features["sse2"] = Features["sse"] = Features["mmx"] = true; 1721 1722 switch (CPU) { 1723 case CK_Generic: 1724 case CK_i386: 1725 case CK_i486: 1726 case CK_i586: 1727 case CK_Pentium: 1728 case CK_i686: 1729 case CK_PentiumPro: 1730 break; 1731 case CK_PentiumMMX: 1732 case CK_Pentium2: 1733 setFeatureEnabled(Features, "mmx", true); 1734 break; 1735 case CK_Pentium3: 1736 case CK_Pentium3M: 1737 setFeatureEnabled(Features, "mmx", true); 1738 setFeatureEnabled(Features, "sse", true); 1739 break; 1740 case CK_PentiumM: 1741 case CK_Pentium4: 1742 case CK_Pentium4M: 1743 case CK_x86_64: 1744 setFeatureEnabled(Features, "mmx", true); 1745 setFeatureEnabled(Features, "sse2", true); 1746 break; 1747 case CK_Yonah: 1748 case CK_Prescott: 1749 case CK_Nocona: 1750 setFeatureEnabled(Features, "mmx", true); 1751 setFeatureEnabled(Features, "sse3", true); 1752 break; 1753 case CK_Core2: 1754 setFeatureEnabled(Features, "mmx", true); 1755 setFeatureEnabled(Features, "ssse3", true); 1756 break; 1757 case CK_Penryn: 1758 setFeatureEnabled(Features, "mmx", true); 1759 setFeatureEnabled(Features, "sse4.1", true); 1760 break; 1761 case CK_Atom: 1762 setFeatureEnabled(Features, "mmx", true); 1763 setFeatureEnabled(Features, "ssse3", true); 1764 break; 1765 case CK_Corei7: 1766 setFeatureEnabled(Features, "mmx", true); 1767 setFeatureEnabled(Features, "sse4", true); 1768 break; 1769 case CK_Corei7AVX: 1770 setFeatureEnabled(Features, "mmx", true); 1771 setFeatureEnabled(Features, "avx", true); 1772 setFeatureEnabled(Features, "aes", true); 1773 setFeatureEnabled(Features, "pclmul", true); 1774 break; 1775 case CK_CoreAVXi: 1776 setFeatureEnabled(Features, "mmx", true); 1777 setFeatureEnabled(Features, "avx", true); 1778 setFeatureEnabled(Features, "aes", true); 1779 setFeatureEnabled(Features, "pclmul", true); 1780 setFeatureEnabled(Features, "rdrnd", true); 1781 break; 1782 case CK_CoreAVX2: 1783 setFeatureEnabled(Features, "mmx", true); 1784 setFeatureEnabled(Features, "avx2", true); 1785 setFeatureEnabled(Features, "aes", true); 1786 setFeatureEnabled(Features, "pclmul", true); 1787 setFeatureEnabled(Features, "lzcnt", true); 1788 setFeatureEnabled(Features, "rdrnd", true); 1789 setFeatureEnabled(Features, "bmi", true); 1790 setFeatureEnabled(Features, "bmi2", true); 1791 setFeatureEnabled(Features, "fma", true); 1792 break; 1793 case CK_K6: 1794 case CK_WinChipC6: 1795 setFeatureEnabled(Features, "mmx", true); 1796 break; 1797 case CK_K6_2: 1798 case CK_K6_3: 1799 case CK_WinChip2: 1800 case CK_C3: 1801 setFeatureEnabled(Features, "3dnow", true); 1802 break; 1803 case CK_Athlon: 1804 case CK_AthlonThunderbird: 1805 case CK_Geode: 1806 setFeatureEnabled(Features, "3dnowa", true); 1807 break; 1808 case CK_Athlon4: 1809 case CK_AthlonXP: 1810 case CK_AthlonMP: 1811 setFeatureEnabled(Features, "sse", true); 1812 setFeatureEnabled(Features, "3dnowa", true); 1813 break; 1814 case CK_K8: 1815 case CK_Opteron: 1816 case CK_Athlon64: 1817 case CK_AthlonFX: 1818 setFeatureEnabled(Features, "sse2", true); 1819 setFeatureEnabled(Features, "3dnowa", true); 1820 break; 1821 case CK_K8SSE3: 1822 case CK_OpteronSSE3: 1823 case CK_Athlon64SSE3: 1824 setFeatureEnabled(Features, "sse3", true); 1825 setFeatureEnabled(Features, "3dnowa", true); 1826 break; 1827 case CK_AMDFAM10: 1828 setFeatureEnabled(Features, "sse3", true); 1829 setFeatureEnabled(Features, "sse4a", true); 1830 setFeatureEnabled(Features, "3dnowa", true); 1831 break; 1832 case CK_BTVER1: 1833 setFeatureEnabled(Features, "ssse3", true); 1834 setFeatureEnabled(Features, "sse4a", true); 1835 break; 1836 case CK_BDVER1: 1837 case CK_BDVER2: 1838 setFeatureEnabled(Features, "avx", true); 1839 setFeatureEnabled(Features, "xop", true); 1840 setFeatureEnabled(Features, "aes", true); 1841 setFeatureEnabled(Features, "pclmul", true); 1842 break; 1843 case CK_C3_2: 1844 setFeatureEnabled(Features, "mmx", true); 1845 setFeatureEnabled(Features, "sse", true); 1846 break; 1847 } 1848 } 1849 1850 bool X86TargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1851 StringRef Name, 1852 bool Enabled) const { 1853 // FIXME: This *really* should not be here. We need some way of translating 1854 // options into llvm subtarget features. 1855 if (!Features.count(Name) && 1856 (Name != "sse4" && Name != "sse4.2" && Name != "sse4.1" && 1857 Name != "rdrnd")) 1858 return false; 1859 1860 // FIXME: this should probably use a switch with fall through. 1861 1862 if (Enabled) { 1863 if (Name == "mmx") 1864 Features["mmx"] = true; 1865 else if (Name == "sse") 1866 Features["mmx"] = Features["sse"] = true; 1867 else if (Name == "sse2") 1868 Features["mmx"] = Features["sse"] = Features["sse2"] = true; 1869 else if (Name == "sse3") 1870 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1871 true; 1872 else if (Name == "ssse3") 1873 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1874 Features["ssse3"] = true; 1875 else if (Name == "sse4" || Name == "sse4.2") 1876 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1877 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1878 Features["popcnt"] = true; 1879 else if (Name == "sse4.1") 1880 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1881 Features["ssse3"] = Features["sse41"] = true; 1882 else if (Name == "3dnow") 1883 Features["mmx"] = Features["3dnow"] = true; 1884 else if (Name == "3dnowa") 1885 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = true; 1886 else if (Name == "aes") 1887 Features["sse"] = Features["sse2"] = Features["aes"] = true; 1888 else if (Name == "pclmul") 1889 Features["sse"] = Features["sse2"] = Features["pclmul"] = true; 1890 else if (Name == "avx") 1891 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1892 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1893 Features["popcnt"] = Features["avx"] = true; 1894 else if (Name == "avx2") 1895 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1896 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1897 Features["popcnt"] = Features["avx"] = Features["avx2"] = true; 1898 else if (Name == "fma") 1899 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1900 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1901 Features["popcnt"] = Features["avx"] = Features["fma"] = true; 1902 else if (Name == "fma4") 1903 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1904 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1905 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1906 Features["fma4"] = true; 1907 else if (Name == "xop") 1908 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1909 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1910 Features["popcnt"] = Features["avx"] = Features["sse4a"] = 1911 Features["fma4"] = Features["xop"] = true; 1912 else if (Name == "sse4a") 1913 Features["mmx"] = Features["sse"] = Features["sse2"] = Features["sse3"] = 1914 Features["sse4a"] = true; 1915 else if (Name == "lzcnt") 1916 Features["lzcnt"] = true; 1917 else if (Name == "rdrnd") 1918 Features["rdrand"] = true; 1919 else if (Name == "bmi") 1920 Features["bmi"] = true; 1921 else if (Name == "bmi2") 1922 Features["bmi2"] = true; 1923 else if (Name == "popcnt") 1924 Features["popcnt"] = true; 1925 } else { 1926 if (Name == "mmx") 1927 Features["mmx"] = Features["3dnow"] = Features["3dnowa"] = false; 1928 else if (Name == "sse") 1929 Features["sse"] = Features["sse2"] = Features["sse3"] = 1930 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1931 Features["sse4a"] = Features["avx"] = Features["avx2"] = 1932 Features["fma"] = Features["fma4"] = Features["aes"] = 1933 Features["pclmul"] = Features["xop"] = false; 1934 else if (Name == "sse2") 1935 Features["sse2"] = Features["sse3"] = Features["ssse3"] = 1936 Features["sse41"] = Features["sse42"] = Features["sse4a"] = 1937 Features["avx"] = Features["avx2"] = Features["fma"] = 1938 Features["fma4"] = Features["aes"] = Features["pclmul"] = 1939 Features["xop"] = false; 1940 else if (Name == "sse3") 1941 Features["sse3"] = Features["ssse3"] = Features["sse41"] = 1942 Features["sse42"] = Features["sse4a"] = Features["avx"] = 1943 Features["avx2"] = Features["fma"] = Features["fma4"] = 1944 Features["xop"] = false; 1945 else if (Name == "ssse3") 1946 Features["ssse3"] = Features["sse41"] = Features["sse42"] = 1947 Features["avx"] = Features["avx2"] = Features["fma"] = false; 1948 else if (Name == "sse4" || Name == "sse4.1") 1949 Features["sse41"] = Features["sse42"] = Features["avx"] = 1950 Features["avx2"] = Features["fma"] = false; 1951 else if (Name == "sse4.2") 1952 Features["sse42"] = Features["avx"] = Features["avx2"] = 1953 Features["fma"] = false; 1954 else if (Name == "3dnow") 1955 Features["3dnow"] = Features["3dnowa"] = false; 1956 else if (Name == "3dnowa") 1957 Features["3dnowa"] = false; 1958 else if (Name == "aes") 1959 Features["aes"] = false; 1960 else if (Name == "pclmul") 1961 Features["pclmul"] = false; 1962 else if (Name == "avx") 1963 Features["avx"] = Features["avx2"] = Features["fma"] = 1964 Features["fma4"] = Features["xop"] = false; 1965 else if (Name == "avx2") 1966 Features["avx2"] = false; 1967 else if (Name == "fma") 1968 Features["fma"] = false; 1969 else if (Name == "sse4a") 1970 Features["sse4a"] = Features["fma4"] = Features["xop"] = false; 1971 else if (Name == "lzcnt") 1972 Features["lzcnt"] = false; 1973 else if (Name == "rdrnd") 1974 Features["rdrand"] = false; 1975 else if (Name == "bmi") 1976 Features["bmi"] = false; 1977 else if (Name == "bmi2") 1978 Features["bmi2"] = false; 1979 else if (Name == "popcnt") 1980 Features["popcnt"] = false; 1981 else if (Name == "fma4") 1982 Features["fma4"] = Features["xop"] = false; 1983 else if (Name == "xop") 1984 Features["xop"] = false; 1985 } 1986 1987 return true; 1988 } 1989 1990 /// HandleTargetOptions - Perform initialization based on the user 1991 /// configured set of features. 1992 void X86TargetInfo::HandleTargetFeatures(std::vector<std::string> &Features) { 1993 // Remember the maximum enabled sselevel. 1994 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1995 // Ignore disabled features. 1996 if (Features[i][0] == '-') 1997 continue; 1998 1999 StringRef Feature = StringRef(Features[i]).substr(1); 2000 2001 if (Feature == "aes") { 2002 HasAES = true; 2003 continue; 2004 } 2005 2006 if (Feature == "pclmul") { 2007 HasPCLMUL = true; 2008 continue; 2009 } 2010 2011 if (Feature == "lzcnt") { 2012 HasLZCNT = true; 2013 continue; 2014 } 2015 2016 if (Feature == "rdrand") { 2017 HasRDRND = true; 2018 continue; 2019 } 2020 2021 if (Feature == "bmi") { 2022 HasBMI = true; 2023 continue; 2024 } 2025 2026 if (Feature == "bmi2") { 2027 HasBMI2 = true; 2028 continue; 2029 } 2030 2031 if (Feature == "popcnt") { 2032 HasPOPCNT = true; 2033 continue; 2034 } 2035 2036 if (Feature == "sse4a") { 2037 HasSSE4a = true; 2038 continue; 2039 } 2040 2041 if (Feature == "fma4") { 2042 HasFMA4 = true; 2043 continue; 2044 } 2045 2046 if (Feature == "fma") { 2047 HasFMA = true; 2048 continue; 2049 } 2050 2051 if (Feature == "xop") { 2052 HasXOP = true; 2053 continue; 2054 } 2055 2056 assert(Features[i][0] == '+' && "Invalid target feature!"); 2057 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2058 .Case("avx2", AVX2) 2059 .Case("avx", AVX) 2060 .Case("sse42", SSE42) 2061 .Case("sse41", SSE41) 2062 .Case("ssse3", SSSE3) 2063 .Case("sse3", SSE3) 2064 .Case("sse2", SSE2) 2065 .Case("sse", SSE1) 2066 .Default(NoSSE); 2067 SSELevel = std::max(SSELevel, Level); 2068 2069 MMX3DNowEnum ThreeDNowLevel = 2070 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2071 .Case("3dnowa", AMD3DNowAthlon) 2072 .Case("3dnow", AMD3DNow) 2073 .Case("mmx", MMX) 2074 .Default(NoMMX3DNow); 2075 2076 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2077 } 2078 2079 // Don't tell the backend if we're turning off mmx; it will end up disabling 2080 // SSE, which we don't want. 2081 std::vector<std::string>::iterator it; 2082 it = std::find(Features.begin(), Features.end(), "-mmx"); 2083 if (it != Features.end()) 2084 Features.erase(it); 2085 } 2086 2087 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2088 /// definitions for this particular subtarget. 2089 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2090 MacroBuilder &Builder) const { 2091 // Target identification. 2092 if (PointerWidth == 64) { 2093 Builder.defineMacro("__amd64__"); 2094 Builder.defineMacro("__amd64"); 2095 Builder.defineMacro("__x86_64"); 2096 Builder.defineMacro("__x86_64__"); 2097 } else { 2098 DefineStd(Builder, "i386", Opts); 2099 } 2100 2101 // Subtarget options. 2102 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2103 // truly should be based on -mtune options. 2104 switch (CPU) { 2105 case CK_Generic: 2106 break; 2107 case CK_i386: 2108 // The rest are coming from the i386 define above. 2109 Builder.defineMacro("__tune_i386__"); 2110 break; 2111 case CK_i486: 2112 case CK_WinChipC6: 2113 case CK_WinChip2: 2114 case CK_C3: 2115 defineCPUMacros(Builder, "i486"); 2116 break; 2117 case CK_PentiumMMX: 2118 Builder.defineMacro("__pentium_mmx__"); 2119 Builder.defineMacro("__tune_pentium_mmx__"); 2120 // Fallthrough 2121 case CK_i586: 2122 case CK_Pentium: 2123 defineCPUMacros(Builder, "i586"); 2124 defineCPUMacros(Builder, "pentium"); 2125 break; 2126 case CK_Pentium3: 2127 case CK_Pentium3M: 2128 case CK_PentiumM: 2129 Builder.defineMacro("__tune_pentium3__"); 2130 // Fallthrough 2131 case CK_Pentium2: 2132 case CK_C3_2: 2133 Builder.defineMacro("__tune_pentium2__"); 2134 // Fallthrough 2135 case CK_PentiumPro: 2136 Builder.defineMacro("__tune_i686__"); 2137 Builder.defineMacro("__tune_pentiumpro__"); 2138 // Fallthrough 2139 case CK_i686: 2140 Builder.defineMacro("__i686"); 2141 Builder.defineMacro("__i686__"); 2142 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2143 Builder.defineMacro("__pentiumpro"); 2144 Builder.defineMacro("__pentiumpro__"); 2145 break; 2146 case CK_Pentium4: 2147 case CK_Pentium4M: 2148 defineCPUMacros(Builder, "pentium4"); 2149 break; 2150 case CK_Yonah: 2151 case CK_Prescott: 2152 case CK_Nocona: 2153 defineCPUMacros(Builder, "nocona"); 2154 break; 2155 case CK_Core2: 2156 case CK_Penryn: 2157 defineCPUMacros(Builder, "core2"); 2158 break; 2159 case CK_Atom: 2160 defineCPUMacros(Builder, "atom"); 2161 break; 2162 case CK_Corei7: 2163 case CK_Corei7AVX: 2164 case CK_CoreAVXi: 2165 case CK_CoreAVX2: 2166 defineCPUMacros(Builder, "corei7"); 2167 break; 2168 case CK_K6_2: 2169 Builder.defineMacro("__k6_2__"); 2170 Builder.defineMacro("__tune_k6_2__"); 2171 // Fallthrough 2172 case CK_K6_3: 2173 if (CPU != CK_K6_2) { // In case of fallthrough 2174 // FIXME: GCC may be enabling these in cases where some other k6 2175 // architecture is specified but -m3dnow is explicitly provided. The 2176 // exact semantics need to be determined and emulated here. 2177 Builder.defineMacro("__k6_3__"); 2178 Builder.defineMacro("__tune_k6_3__"); 2179 } 2180 // Fallthrough 2181 case CK_K6: 2182 defineCPUMacros(Builder, "k6"); 2183 break; 2184 case CK_Athlon: 2185 case CK_AthlonThunderbird: 2186 case CK_Athlon4: 2187 case CK_AthlonXP: 2188 case CK_AthlonMP: 2189 defineCPUMacros(Builder, "athlon"); 2190 if (SSELevel != NoSSE) { 2191 Builder.defineMacro("__athlon_sse__"); 2192 Builder.defineMacro("__tune_athlon_sse__"); 2193 } 2194 break; 2195 case CK_K8: 2196 case CK_K8SSE3: 2197 case CK_x86_64: 2198 case CK_Opteron: 2199 case CK_OpteronSSE3: 2200 case CK_Athlon64: 2201 case CK_Athlon64SSE3: 2202 case CK_AthlonFX: 2203 defineCPUMacros(Builder, "k8"); 2204 break; 2205 case CK_AMDFAM10: 2206 defineCPUMacros(Builder, "amdfam10"); 2207 break; 2208 case CK_BTVER1: 2209 defineCPUMacros(Builder, "btver1"); 2210 break; 2211 case CK_BDVER1: 2212 defineCPUMacros(Builder, "bdver1"); 2213 break; 2214 case CK_BDVER2: 2215 defineCPUMacros(Builder, "bdver2"); 2216 break; 2217 case CK_Geode: 2218 defineCPUMacros(Builder, "geode"); 2219 break; 2220 } 2221 2222 // Target properties. 2223 Builder.defineMacro("__LITTLE_ENDIAN__"); 2224 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2225 2226 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2227 // functions in glibc header files that use FP Stack inline asm which the 2228 // backend can't deal with (PR879). 2229 Builder.defineMacro("__NO_MATH_INLINES"); 2230 2231 if (HasAES) 2232 Builder.defineMacro("__AES__"); 2233 2234 if (HasPCLMUL) 2235 Builder.defineMacro("__PCLMUL__"); 2236 2237 if (HasLZCNT) 2238 Builder.defineMacro("__LZCNT__"); 2239 2240 if (HasRDRND) 2241 Builder.defineMacro("__RDRND__"); 2242 2243 if (HasBMI) 2244 Builder.defineMacro("__BMI__"); 2245 2246 if (HasBMI2) 2247 Builder.defineMacro("__BMI2__"); 2248 2249 if (HasPOPCNT) 2250 Builder.defineMacro("__POPCNT__"); 2251 2252 if (HasSSE4a) 2253 Builder.defineMacro("__SSE4A__"); 2254 2255 if (HasFMA4) 2256 Builder.defineMacro("__FMA4__"); 2257 2258 if (HasFMA) 2259 Builder.defineMacro("__FMA__"); 2260 2261 if (HasXOP) 2262 Builder.defineMacro("__XOP__"); 2263 2264 // Each case falls through to the previous one here. 2265 switch (SSELevel) { 2266 case AVX2: 2267 Builder.defineMacro("__AVX2__"); 2268 case AVX: 2269 Builder.defineMacro("__AVX__"); 2270 case SSE42: 2271 Builder.defineMacro("__SSE4_2__"); 2272 case SSE41: 2273 Builder.defineMacro("__SSE4_1__"); 2274 case SSSE3: 2275 Builder.defineMacro("__SSSE3__"); 2276 case SSE3: 2277 Builder.defineMacro("__SSE3__"); 2278 case SSE2: 2279 Builder.defineMacro("__SSE2__"); 2280 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2281 case SSE1: 2282 Builder.defineMacro("__SSE__"); 2283 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2284 case NoSSE: 2285 break; 2286 } 2287 2288 if (Opts.MicrosoftExt && PointerWidth == 32) { 2289 switch (SSELevel) { 2290 case AVX2: 2291 case AVX: 2292 case SSE42: 2293 case SSE41: 2294 case SSSE3: 2295 case SSE3: 2296 case SSE2: 2297 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2298 break; 2299 case SSE1: 2300 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2301 break; 2302 default: 2303 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2304 } 2305 } 2306 2307 // Each case falls through to the previous one here. 2308 switch (MMX3DNowLevel) { 2309 case AMD3DNowAthlon: 2310 Builder.defineMacro("__3dNOW_A__"); 2311 case AMD3DNow: 2312 Builder.defineMacro("__3dNOW__"); 2313 case MMX: 2314 Builder.defineMacro("__MMX__"); 2315 case NoMMX3DNow: 2316 break; 2317 } 2318 } 2319 2320 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2321 return llvm::StringSwitch<bool>(Feature) 2322 .Case("aes", HasAES) 2323 .Case("avx", SSELevel >= AVX) 2324 .Case("avx2", SSELevel >= AVX2) 2325 .Case("bmi", HasBMI) 2326 .Case("bmi2", HasBMI2) 2327 .Case("fma", HasFMA) 2328 .Case("fma4", HasFMA4) 2329 .Case("lzcnt", HasLZCNT) 2330 .Case("rdrnd", HasRDRND) 2331 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2332 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2333 .Case("mmx", MMX3DNowLevel >= MMX) 2334 .Case("pclmul", HasPCLMUL) 2335 .Case("popcnt", HasPOPCNT) 2336 .Case("sse", SSELevel >= SSE1) 2337 .Case("sse2", SSELevel >= SSE2) 2338 .Case("sse3", SSELevel >= SSE3) 2339 .Case("ssse3", SSELevel >= SSSE3) 2340 .Case("sse41", SSELevel >= SSE41) 2341 .Case("sse42", SSELevel >= SSE42) 2342 .Case("sse4a", HasSSE4a) 2343 .Case("x86", true) 2344 .Case("x86_32", PointerWidth == 32) 2345 .Case("x86_64", PointerWidth == 64) 2346 .Case("xop", HasXOP) 2347 .Default(false); 2348 } 2349 2350 bool 2351 X86TargetInfo::validateAsmConstraint(const char *&Name, 2352 TargetInfo::ConstraintInfo &Info) const { 2353 switch (*Name) { 2354 default: return false; 2355 case 'Y': // first letter of a pair: 2356 switch (*(Name+1)) { 2357 default: return false; 2358 case '0': // First SSE register. 2359 case 't': // Any SSE register, when SSE2 is enabled. 2360 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2361 case 'm': // any MMX register, when inter-unit moves enabled. 2362 break; // falls through to setAllowsRegister. 2363 } 2364 case 'a': // eax. 2365 case 'b': // ebx. 2366 case 'c': // ecx. 2367 case 'd': // edx. 2368 case 'S': // esi. 2369 case 'D': // edi. 2370 case 'A': // edx:eax. 2371 case 'f': // any x87 floating point stack register. 2372 case 't': // top of floating point stack. 2373 case 'u': // second from top of floating point stack. 2374 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2375 case 'y': // Any MMX register. 2376 case 'x': // Any SSE register. 2377 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2378 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2379 case 'l': // "Index" registers: any general register that can be used as an 2380 // index in a base+index memory access. 2381 Info.setAllowsRegister(); 2382 return true; 2383 case 'C': // SSE floating point constant. 2384 case 'G': // x87 floating point constant. 2385 case 'e': // 32-bit signed integer constant for use with zero-extending 2386 // x86_64 instructions. 2387 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2388 // x86_64 instructions. 2389 return true; 2390 } 2391 } 2392 2393 2394 std::string 2395 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2396 switch (*Constraint) { 2397 case 'a': return std::string("{ax}"); 2398 case 'b': return std::string("{bx}"); 2399 case 'c': return std::string("{cx}"); 2400 case 'd': return std::string("{dx}"); 2401 case 'S': return std::string("{si}"); 2402 case 'D': return std::string("{di}"); 2403 case 'p': // address 2404 return std::string("im"); 2405 case 't': // top of floating point stack. 2406 return std::string("{st}"); 2407 case 'u': // second from top of floating point stack. 2408 return std::string("{st(1)}"); // second from top of floating point stack. 2409 default: 2410 return std::string(1, *Constraint); 2411 } 2412 } 2413 } // end anonymous namespace 2414 2415 namespace { 2416 // X86-32 generic target 2417 class X86_32TargetInfo : public X86TargetInfo { 2418 public: 2419 X86_32TargetInfo(const std::string& triple) : X86TargetInfo(triple) { 2420 DoubleAlign = LongLongAlign = 32; 2421 LongDoubleWidth = 96; 2422 LongDoubleAlign = 32; 2423 SuitableAlign = 128; 2424 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2425 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2426 "a0:0:64-f80:32:32-n8:16:32-S128"; 2427 SizeType = UnsignedInt; 2428 PtrDiffType = SignedInt; 2429 IntPtrType = SignedInt; 2430 RegParmMax = 3; 2431 2432 // Use fpret for all types. 2433 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2434 (1 << TargetInfo::Double) | 2435 (1 << TargetInfo::LongDouble)); 2436 2437 // x86-32 has atomics up to 8 bytes 2438 // FIXME: Check that we actually have cmpxchg8b before setting 2439 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2440 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2441 } 2442 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2443 return TargetInfo::CharPtrBuiltinVaList; 2444 } 2445 2446 int getEHDataRegisterNumber(unsigned RegNo) const { 2447 if (RegNo == 0) return 0; 2448 if (RegNo == 1) return 2; 2449 return -1; 2450 } 2451 }; 2452 } // end anonymous namespace 2453 2454 namespace { 2455 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2456 public: 2457 NetBSDI386TargetInfo(const std::string &triple) : 2458 NetBSDTargetInfo<X86_32TargetInfo>(triple) { 2459 } 2460 2461 virtual unsigned getFloatEvalMethod() const { 2462 // NetBSD defaults to "double" rounding 2463 return 1; 2464 } 2465 }; 2466 } // end anonymous namespace 2467 2468 namespace { 2469 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 2470 public: 2471 OpenBSDI386TargetInfo(const std::string& triple) : 2472 OpenBSDTargetInfo<X86_32TargetInfo>(triple) { 2473 SizeType = UnsignedLong; 2474 IntPtrType = SignedLong; 2475 PtrDiffType = SignedLong; 2476 } 2477 }; 2478 } // end anonymous namespace 2479 2480 namespace { 2481 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 2482 public: 2483 BitrigI386TargetInfo(const std::string& triple) : 2484 BitrigTargetInfo<X86_32TargetInfo>(triple) { 2485 SizeType = UnsignedLong; 2486 IntPtrType = SignedLong; 2487 PtrDiffType = SignedLong; 2488 } 2489 }; 2490 } // end anonymous namespace 2491 2492 namespace { 2493 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 2494 public: 2495 DarwinI386TargetInfo(const std::string& triple) : 2496 DarwinTargetInfo<X86_32TargetInfo>(triple) { 2497 LongDoubleWidth = 128; 2498 LongDoubleAlign = 128; 2499 SuitableAlign = 128; 2500 MaxVectorAlign = 256; 2501 SizeType = UnsignedLong; 2502 IntPtrType = SignedLong; 2503 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2504 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2505 "a0:0:64-f80:128:128-n8:16:32-S128"; 2506 HasAlignMac68kSupport = true; 2507 } 2508 2509 }; 2510 } // end anonymous namespace 2511 2512 namespace { 2513 // x86-32 Windows target 2514 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 2515 public: 2516 WindowsX86_32TargetInfo(const std::string& triple) 2517 : WindowsTargetInfo<X86_32TargetInfo>(triple) { 2518 TLSSupported = false; 2519 WCharType = UnsignedShort; 2520 DoubleAlign = LongLongAlign = 64; 2521 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2522 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 2523 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 2524 } 2525 virtual void getTargetDefines(const LangOptions &Opts, 2526 MacroBuilder &Builder) const { 2527 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 2528 } 2529 }; 2530 } // end anonymous namespace 2531 2532 namespace { 2533 2534 // x86-32 Windows Visual Studio target 2535 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 2536 public: 2537 VisualStudioWindowsX86_32TargetInfo(const std::string& triple) 2538 : WindowsX86_32TargetInfo(triple) { 2539 LongDoubleWidth = LongDoubleAlign = 64; 2540 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2541 } 2542 virtual void getTargetDefines(const LangOptions &Opts, 2543 MacroBuilder &Builder) const { 2544 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2545 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 2546 // The value of the following reflects processor type. 2547 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 2548 // We lost the original triple, so we use the default. 2549 Builder.defineMacro("_M_IX86", "600"); 2550 } 2551 }; 2552 } // end anonymous namespace 2553 2554 namespace { 2555 // x86-32 MinGW target 2556 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 2557 public: 2558 MinGWX86_32TargetInfo(const std::string& triple) 2559 : WindowsX86_32TargetInfo(triple) { 2560 } 2561 virtual void getTargetDefines(const LangOptions &Opts, 2562 MacroBuilder &Builder) const { 2563 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 2564 DefineStd(Builder, "WIN32", Opts); 2565 DefineStd(Builder, "WINNT", Opts); 2566 Builder.defineMacro("_X86_"); 2567 Builder.defineMacro("__MSVCRT__"); 2568 Builder.defineMacro("__MINGW32__"); 2569 2570 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2571 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2572 if (Opts.MicrosoftExt) 2573 // Provide "as-is" __declspec. 2574 Builder.defineMacro("__declspec", "__declspec"); 2575 else 2576 // Provide alias of __attribute__ like mingw32-gcc. 2577 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2578 } 2579 }; 2580 } // end anonymous namespace 2581 2582 namespace { 2583 // x86-32 Cygwin target 2584 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 2585 public: 2586 CygwinX86_32TargetInfo(const std::string& triple) 2587 : X86_32TargetInfo(triple) { 2588 TLSSupported = false; 2589 WCharType = UnsignedShort; 2590 DoubleAlign = LongLongAlign = 64; 2591 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2592 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2593 "a0:0:64-f80:32:32-n8:16:32-S32"; 2594 } 2595 virtual void getTargetDefines(const LangOptions &Opts, 2596 MacroBuilder &Builder) const { 2597 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2598 Builder.defineMacro("__CYGWIN__"); 2599 Builder.defineMacro("__CYGWIN32__"); 2600 DefineStd(Builder, "unix", Opts); 2601 if (Opts.CPlusPlus) 2602 Builder.defineMacro("_GNU_SOURCE"); 2603 } 2604 }; 2605 } // end anonymous namespace 2606 2607 namespace { 2608 // x86-32 Haiku target 2609 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 2610 public: 2611 HaikuX86_32TargetInfo(const std::string& triple) 2612 : X86_32TargetInfo(triple) { 2613 SizeType = UnsignedLong; 2614 IntPtrType = SignedLong; 2615 PtrDiffType = SignedLong; 2616 this->UserLabelPrefix = ""; 2617 } 2618 virtual void getTargetDefines(const LangOptions &Opts, 2619 MacroBuilder &Builder) const { 2620 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2621 Builder.defineMacro("__INTEL__"); 2622 Builder.defineMacro("__HAIKU__"); 2623 } 2624 }; 2625 } // end anonymous namespace 2626 2627 // RTEMS Target 2628 template<typename Target> 2629 class RTEMSTargetInfo : public OSTargetInfo<Target> { 2630 protected: 2631 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 2632 MacroBuilder &Builder) const { 2633 // RTEMS defines; list based off of gcc output 2634 2635 Builder.defineMacro("__rtems__"); 2636 Builder.defineMacro("__ELF__"); 2637 } 2638 public: 2639 RTEMSTargetInfo(const std::string &triple) 2640 : OSTargetInfo<Target>(triple) { 2641 this->UserLabelPrefix = ""; 2642 2643 llvm::Triple Triple(triple); 2644 switch (Triple.getArch()) { 2645 default: 2646 case llvm::Triple::x86: 2647 // this->MCountName = ".mcount"; 2648 break; 2649 case llvm::Triple::mips: 2650 case llvm::Triple::mipsel: 2651 case llvm::Triple::ppc: 2652 case llvm::Triple::ppc64: 2653 // this->MCountName = "_mcount"; 2654 break; 2655 case llvm::Triple::arm: 2656 // this->MCountName = "__mcount"; 2657 break; 2658 } 2659 2660 } 2661 }; 2662 2663 namespace { 2664 // x86-32 RTEMS target 2665 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 2666 public: 2667 RTEMSX86_32TargetInfo(const std::string& triple) 2668 : X86_32TargetInfo(triple) { 2669 SizeType = UnsignedLong; 2670 IntPtrType = SignedLong; 2671 PtrDiffType = SignedLong; 2672 this->UserLabelPrefix = ""; 2673 } 2674 virtual void getTargetDefines(const LangOptions &Opts, 2675 MacroBuilder &Builder) const { 2676 X86_32TargetInfo::getTargetDefines(Opts, Builder); 2677 Builder.defineMacro("__INTEL__"); 2678 Builder.defineMacro("__rtems__"); 2679 } 2680 }; 2681 } // end anonymous namespace 2682 2683 namespace { 2684 // x86-64 generic target 2685 class X86_64TargetInfo : public X86TargetInfo { 2686 public: 2687 X86_64TargetInfo(const std::string &triple) : X86TargetInfo(triple) { 2688 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 2689 LongDoubleWidth = 128; 2690 LongDoubleAlign = 128; 2691 LargeArrayMinWidth = 128; 2692 LargeArrayAlign = 128; 2693 SuitableAlign = 128; 2694 IntMaxType = SignedLong; 2695 UIntMaxType = UnsignedLong; 2696 Int64Type = SignedLong; 2697 RegParmMax = 6; 2698 2699 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2700 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 2701 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 2702 2703 // Use fpret only for long double. 2704 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 2705 2706 // Use fp2ret for _Complex long double. 2707 ComplexLongDoubleUsesFP2Ret = true; 2708 2709 // x86-64 has atomics up to 16 bytes. 2710 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 2711 // on CPUs with cmpxchg16b 2712 MaxAtomicPromoteWidth = 128; 2713 MaxAtomicInlineWidth = 64; 2714 } 2715 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2716 return TargetInfo::X86_64ABIBuiltinVaList; 2717 } 2718 2719 int getEHDataRegisterNumber(unsigned RegNo) const { 2720 if (RegNo == 0) return 0; 2721 if (RegNo == 1) return 1; 2722 return -1; 2723 } 2724 2725 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 2726 return TargetInfo::checkCallingConvention(CC); 2727 } 2728 2729 virtual CallingConv getDefaultCallingConv() const { 2730 return CC_Default; 2731 } 2732 2733 }; 2734 } // end anonymous namespace 2735 2736 namespace { 2737 // x86-64 Windows target 2738 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 2739 public: 2740 WindowsX86_64TargetInfo(const std::string& triple) 2741 : WindowsTargetInfo<X86_64TargetInfo>(triple) { 2742 TLSSupported = false; 2743 WCharType = UnsignedShort; 2744 LongWidth = LongAlign = 32; 2745 DoubleAlign = LongLongAlign = 64; 2746 IntMaxType = SignedLongLong; 2747 UIntMaxType = UnsignedLongLong; 2748 Int64Type = SignedLongLong; 2749 SizeType = UnsignedLongLong; 2750 PtrDiffType = SignedLongLong; 2751 IntPtrType = SignedLongLong; 2752 this->UserLabelPrefix = ""; 2753 } 2754 virtual void getTargetDefines(const LangOptions &Opts, 2755 MacroBuilder &Builder) const { 2756 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 2757 Builder.defineMacro("_WIN64"); 2758 } 2759 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2760 return TargetInfo::CharPtrBuiltinVaList; 2761 } 2762 }; 2763 } // end anonymous namespace 2764 2765 namespace { 2766 // x86-64 Windows Visual Studio target 2767 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 2768 public: 2769 VisualStudioWindowsX86_64TargetInfo(const std::string& triple) 2770 : WindowsX86_64TargetInfo(triple) { 2771 LongDoubleWidth = LongDoubleAlign = 64; 2772 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 2773 } 2774 virtual void getTargetDefines(const LangOptions &Opts, 2775 MacroBuilder &Builder) const { 2776 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2777 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 2778 Builder.defineMacro("_M_X64"); 2779 Builder.defineMacro("_M_AMD64"); 2780 } 2781 }; 2782 } // end anonymous namespace 2783 2784 namespace { 2785 // x86-64 MinGW target 2786 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 2787 public: 2788 MinGWX86_64TargetInfo(const std::string& triple) 2789 : WindowsX86_64TargetInfo(triple) { 2790 } 2791 virtual void getTargetDefines(const LangOptions &Opts, 2792 MacroBuilder &Builder) const { 2793 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 2794 DefineStd(Builder, "WIN64", Opts); 2795 Builder.defineMacro("__MSVCRT__"); 2796 Builder.defineMacro("__MINGW32__"); 2797 Builder.defineMacro("__MINGW64__"); 2798 2799 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 2800 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 2801 if (Opts.MicrosoftExt) 2802 // Provide "as-is" __declspec. 2803 Builder.defineMacro("__declspec", "__declspec"); 2804 else 2805 // Provide alias of __attribute__ like mingw32-gcc. 2806 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 2807 } 2808 }; 2809 } // end anonymous namespace 2810 2811 namespace { 2812 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 2813 public: 2814 DarwinX86_64TargetInfo(const std::string& triple) 2815 : DarwinTargetInfo<X86_64TargetInfo>(triple) { 2816 Int64Type = SignedLongLong; 2817 MaxVectorAlign = 256; 2818 } 2819 }; 2820 } // end anonymous namespace 2821 2822 namespace { 2823 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 2824 public: 2825 OpenBSDX86_64TargetInfo(const std::string& triple) 2826 : OpenBSDTargetInfo<X86_64TargetInfo>(triple) { 2827 IntMaxType = SignedLongLong; 2828 UIntMaxType = UnsignedLongLong; 2829 Int64Type = SignedLongLong; 2830 } 2831 }; 2832 } // end anonymous namespace 2833 2834 namespace { 2835 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 2836 public: 2837 BitrigX86_64TargetInfo(const std::string& triple) 2838 : BitrigTargetInfo<X86_64TargetInfo>(triple) { 2839 IntMaxType = SignedLongLong; 2840 UIntMaxType = UnsignedLongLong; 2841 Int64Type = SignedLongLong; 2842 } 2843 }; 2844 } // end anonymous namespace 2845 2846 namespace { 2847 class ARMTargetInfo : public TargetInfo { 2848 // Possible FPU choices. 2849 enum FPUMode { 2850 VFP2FPU = (1 << 0), 2851 VFP3FPU = (1 << 1), 2852 VFP4FPU = (1 << 2), 2853 NeonFPU = (1 << 3) 2854 }; 2855 2856 static bool FPUModeIsVFP(FPUMode Mode) { 2857 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU); 2858 } 2859 2860 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 2861 static const char * const GCCRegNames[]; 2862 2863 std::string ABI, CPU; 2864 2865 unsigned FPU : 4; 2866 2867 unsigned IsThumb : 1; 2868 2869 // Initialized via features. 2870 unsigned SoftFloat : 1; 2871 unsigned SoftFloatABI : 1; 2872 2873 static const Builtin::Info BuiltinInfo[]; 2874 2875 public: 2876 ARMTargetInfo(const std::string &TripleStr) 2877 : TargetInfo(TripleStr), ABI("aapcs-linux"), CPU("arm1136j-s") 2878 { 2879 BigEndian = false; 2880 SizeType = UnsignedInt; 2881 PtrDiffType = SignedInt; 2882 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 2883 WCharType = UnsignedInt; 2884 2885 // {} in inline assembly are neon specifiers, not assembly variant 2886 // specifiers. 2887 NoAsmVariants = true; 2888 2889 // FIXME: Should we just treat this as a feature? 2890 IsThumb = getTriple().getArchName().startswith("thumb"); 2891 if (IsThumb) { 2892 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2893 // so set preferred for small types to 32. 2894 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2895 "i64:64:64-f32:32:32-f64:64:64-" 2896 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 2897 } else { 2898 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2899 "i64:64:64-f32:32:32-f64:64:64-" 2900 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 2901 } 2902 2903 // ARM targets default to using the ARM C++ ABI. 2904 CXXABI = CXXABI_ARM; 2905 2906 // ARM has atomics up to 8 bytes 2907 // FIXME: Set MaxAtomicInlineWidth if we have the feature v6e 2908 MaxAtomicPromoteWidth = 64; 2909 2910 // Do force alignment of members that follow zero length bitfields. If 2911 // the alignment of the zero-length bitfield is greater than the member 2912 // that follows it, `bar', `bar' will be aligned as the type of the 2913 // zero length bitfield. 2914 UseZeroLengthBitfieldAlignment = true; 2915 } 2916 virtual const char *getABI() const { return ABI.c_str(); } 2917 virtual bool setABI(const std::string &Name) { 2918 ABI = Name; 2919 2920 // The defaults (above) are for AAPCS, check if we need to change them. 2921 // 2922 // FIXME: We need support for -meabi... we could just mangle it into the 2923 // name. 2924 if (Name == "apcs-gnu") { 2925 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 2926 SizeType = UnsignedLong; 2927 2928 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 2929 WCharType = SignedInt; 2930 2931 // Do not respect the alignment of bit-field types when laying out 2932 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 2933 UseBitFieldTypeAlignment = false; 2934 2935 /// gcc forces the alignment to 4 bytes, regardless of the type of the 2936 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 2937 /// gcc. 2938 ZeroLengthBitfieldBoundary = 32; 2939 2940 if (IsThumb) { 2941 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 2942 // so set preferred for small types to 32. 2943 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 2944 "i64:32:64-f32:32:32-f64:32:64-" 2945 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2946 } else { 2947 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2948 "i64:32:64-f32:32:32-f64:32:64-" 2949 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 2950 } 2951 2952 // FIXME: Override "preferred align" for double and long long. 2953 } else if (Name == "aapcs") { 2954 // FIXME: Enumerated types are variable width in straight AAPCS. 2955 } else if (Name == "aapcs-linux") { 2956 ; 2957 } else 2958 return false; 2959 2960 return true; 2961 } 2962 2963 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2964 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 2965 Features["vfp2"] = true; 2966 else if (CPU == "cortex-a8" || CPU == "cortex-a15" || 2967 CPU == "cortex-a9" || CPU == "cortex-a9-mp") 2968 Features["neon"] = true; 2969 else if (CPU == "swift") { 2970 Features["vfp4"] = true; 2971 Features["neon"] = true; 2972 } 2973 } 2974 2975 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 2976 StringRef Name, 2977 bool Enabled) const { 2978 if (Name == "soft-float" || Name == "soft-float-abi" || 2979 Name == "vfp2" || Name == "vfp3" || Name == "vfp4" || Name == "neon" || 2980 Name == "d16" || Name == "neonfp") { 2981 Features[Name] = Enabled; 2982 } else 2983 return false; 2984 2985 return true; 2986 } 2987 2988 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 2989 FPU = 0; 2990 SoftFloat = SoftFloatABI = false; 2991 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 2992 if (Features[i] == "+soft-float") 2993 SoftFloat = true; 2994 else if (Features[i] == "+soft-float-abi") 2995 SoftFloatABI = true; 2996 else if (Features[i] == "+vfp2") 2997 FPU |= VFP2FPU; 2998 else if (Features[i] == "+vfp3") 2999 FPU |= VFP3FPU; 3000 else if (Features[i] == "+vfp4") 3001 FPU |= VFP4FPU; 3002 else if (Features[i] == "+neon") 3003 FPU |= NeonFPU; 3004 } 3005 3006 // Remove front-end specific options which the backend handles differently. 3007 std::vector<std::string>::iterator it; 3008 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3009 if (it != Features.end()) 3010 Features.erase(it); 3011 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3012 if (it != Features.end()) 3013 Features.erase(it); 3014 } 3015 3016 virtual bool hasFeature(StringRef Feature) const { 3017 return llvm::StringSwitch<bool>(Feature) 3018 .Case("arm", true) 3019 .Case("softfloat", SoftFloat) 3020 .Case("thumb", IsThumb) 3021 .Case("neon", FPU == NeonFPU && !SoftFloat && 3022 StringRef(getCPUDefineSuffix(CPU)).startswith("7")) 3023 .Default(false); 3024 } 3025 // FIXME: Should we actually have some table instead of these switches? 3026 static const char *getCPUDefineSuffix(StringRef Name) { 3027 return llvm::StringSwitch<const char*>(Name) 3028 .Cases("arm8", "arm810", "4") 3029 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3030 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3031 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3032 .Case("ep9312", "4T") 3033 .Cases("arm10tdmi", "arm1020t", "5T") 3034 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3035 .Case("arm926ej-s", "5TEJ") 3036 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3037 .Cases("xscale", "iwmmxt", "5TE") 3038 .Case("arm1136j-s", "6J") 3039 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3040 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3041 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3042 .Cases("cortex-a8", "cortex-a9", "cortex-a15", "7A") 3043 .Case("cortex-a9-mp", "7F") 3044 .Case("swift", "7S") 3045 .Cases("cortex-m3", "cortex-m4", "7M") 3046 .Case("cortex-m0", "6M") 3047 .Default(0); 3048 } 3049 static const char *getCPUProfile(StringRef Name) { 3050 return llvm::StringSwitch<const char*>(Name) 3051 .Cases("cortex-a8", "cortex-a9", "A") 3052 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3053 .Default(""); 3054 } 3055 virtual bool setCPU(const std::string &Name) { 3056 if (!getCPUDefineSuffix(Name)) 3057 return false; 3058 3059 CPU = Name; 3060 return true; 3061 } 3062 virtual void getTargetDefines(const LangOptions &Opts, 3063 MacroBuilder &Builder) const { 3064 // Target identification. 3065 Builder.defineMacro("__arm"); 3066 Builder.defineMacro("__arm__"); 3067 3068 // Target properties. 3069 Builder.defineMacro("__ARMEL__"); 3070 Builder.defineMacro("__LITTLE_ENDIAN__"); 3071 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3072 3073 StringRef CPUArch = getCPUDefineSuffix(CPU); 3074 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3075 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3076 StringRef CPUProfile = getCPUProfile(CPU); 3077 if (!CPUProfile.empty()) 3078 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3079 3080 // Subtarget options. 3081 3082 // FIXME: It's more complicated than this and we don't really support 3083 // interworking. 3084 if ('5' <= CPUArch[0] && CPUArch[0] <= '7') 3085 Builder.defineMacro("__THUMB_INTERWORK__"); 3086 3087 if (ABI == "aapcs" || ABI == "aapcs-linux") { 3088 Builder.defineMacro("__ARM_EABI__"); 3089 Builder.defineMacro("__ARM_PCS", "1"); 3090 3091 if (!SoftFloat && !SoftFloatABI) 3092 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3093 } 3094 3095 if (SoftFloat) 3096 Builder.defineMacro("__SOFTFP__"); 3097 3098 if (CPU == "xscale") 3099 Builder.defineMacro("__XSCALE__"); 3100 3101 bool IsARMv7 = CPUArch.startswith("7"); 3102 if (IsThumb) { 3103 Builder.defineMacro("__THUMBEL__"); 3104 Builder.defineMacro("__thumb__"); 3105 if (CPUArch == "6T2" || IsARMv7) 3106 Builder.defineMacro("__thumb2__"); 3107 } 3108 3109 // Note, this is always on in gcc, even though it doesn't make sense. 3110 Builder.defineMacro("__APCS_32__"); 3111 3112 if (FPUModeIsVFP((FPUMode) FPU)) { 3113 Builder.defineMacro("__VFP_FP__"); 3114 if (FPU & VFP2FPU) 3115 Builder.defineMacro("__ARM_VFPV2__"); 3116 if (FPU & VFP3FPU) 3117 Builder.defineMacro("__ARM_VFPV3__"); 3118 if (FPU & VFP4FPU) 3119 Builder.defineMacro("__ARM_VFPV4__"); 3120 } 3121 3122 // This only gets set when Neon instructions are actually available, unlike 3123 // the VFP define, hence the soft float and arch check. This is subtly 3124 // different from gcc, we follow the intent which was that it should be set 3125 // when Neon instructions are actually available. 3126 if ((FPU & NeonFPU) && !SoftFloat && IsARMv7) 3127 Builder.defineMacro("__ARM_NEON__"); 3128 } 3129 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3130 unsigned &NumRecords) const { 3131 Records = BuiltinInfo; 3132 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 3133 } 3134 virtual bool isCLZForZeroUndef() const { return false; } 3135 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3136 return TargetInfo::VoidPtrBuiltinVaList; 3137 } 3138 virtual void getGCCRegNames(const char * const *&Names, 3139 unsigned &NumNames) const; 3140 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3141 unsigned &NumAliases) const; 3142 virtual bool validateAsmConstraint(const char *&Name, 3143 TargetInfo::ConstraintInfo &Info) const { 3144 switch (*Name) { 3145 default: break; 3146 case 'l': // r0-r7 3147 case 'h': // r8-r15 3148 case 'w': // VFP Floating point register single precision 3149 case 'P': // VFP Floating point register double precision 3150 Info.setAllowsRegister(); 3151 return true; 3152 case 'Q': // A memory address that is a single base register. 3153 Info.setAllowsMemory(); 3154 return true; 3155 case 'U': // a memory reference... 3156 switch (Name[1]) { 3157 case 'q': // ...ARMV4 ldrsb 3158 case 'v': // ...VFP load/store (reg+constant offset) 3159 case 'y': // ...iWMMXt load/store 3160 case 't': // address valid for load/store opaque types wider 3161 // than 128-bits 3162 case 'n': // valid address for Neon doubleword vector load/store 3163 case 'm': // valid address for Neon element and structure load/store 3164 case 's': // valid address for non-offset loads/stores of quad-word 3165 // values in four ARM registers 3166 Info.setAllowsMemory(); 3167 Name++; 3168 return true; 3169 } 3170 } 3171 return false; 3172 } 3173 virtual std::string convertConstraint(const char *&Constraint) const { 3174 std::string R; 3175 switch (*Constraint) { 3176 case 'U': // Two-character constraint; add "^" hint for later parsing. 3177 R = std::string("^") + std::string(Constraint, 2); 3178 Constraint++; 3179 break; 3180 case 'p': // 'p' should be translated to 'r' by default. 3181 R = std::string("r"); 3182 break; 3183 default: 3184 return std::string(1, *Constraint); 3185 } 3186 return R; 3187 } 3188 virtual const char *getClobbers() const { 3189 // FIXME: Is this really right? 3190 return ""; 3191 } 3192 3193 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3194 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 3195 } 3196 }; 3197 3198 const char * const ARMTargetInfo::GCCRegNames[] = { 3199 // Integer registers 3200 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3201 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 3202 3203 // Float registers 3204 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3205 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3206 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3207 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3208 3209 // Double registers 3210 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3211 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3212 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3213 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3214 3215 // Quad registers 3216 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3217 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 3218 }; 3219 3220 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 3221 unsigned &NumNames) const { 3222 Names = GCCRegNames; 3223 NumNames = llvm::array_lengthof(GCCRegNames); 3224 } 3225 3226 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 3227 { { "a1" }, "r0" }, 3228 { { "a2" }, "r1" }, 3229 { { "a3" }, "r2" }, 3230 { { "a4" }, "r3" }, 3231 { { "v1" }, "r4" }, 3232 { { "v2" }, "r5" }, 3233 { { "v3" }, "r6" }, 3234 { { "v4" }, "r7" }, 3235 { { "v5" }, "r8" }, 3236 { { "v6", "rfp" }, "r9" }, 3237 { { "sl" }, "r10" }, 3238 { { "fp" }, "r11" }, 3239 { { "ip" }, "r12" }, 3240 { { "r13" }, "sp" }, 3241 { { "r14" }, "lr" }, 3242 { { "r15" }, "pc" }, 3243 // The S, D and Q registers overlap, but aren't really aliases; we 3244 // don't want to substitute one of these for a different-sized one. 3245 }; 3246 3247 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3248 unsigned &NumAliases) const { 3249 Aliases = GCCRegAliases; 3250 NumAliases = llvm::array_lengthof(GCCRegAliases); 3251 } 3252 3253 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 3254 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3255 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3256 ALL_LANGUAGES }, 3257 #include "clang/Basic/BuiltinsARM.def" 3258 }; 3259 } // end anonymous namespace. 3260 3261 namespace { 3262 class DarwinARMTargetInfo : 3263 public DarwinTargetInfo<ARMTargetInfo> { 3264 protected: 3265 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3266 MacroBuilder &Builder) const { 3267 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 3268 } 3269 3270 public: 3271 DarwinARMTargetInfo(const std::string& triple) 3272 : DarwinTargetInfo<ARMTargetInfo>(triple) { 3273 HasAlignMac68kSupport = true; 3274 // iOS always has 64-bit atomic instructions. 3275 // FIXME: This should be based off of the target features in ARMTargetInfo. 3276 MaxAtomicInlineWidth = 64; 3277 } 3278 }; 3279 } // end anonymous namespace. 3280 3281 3282 namespace { 3283 // Hexagon abstract base class 3284 class HexagonTargetInfo : public TargetInfo { 3285 static const Builtin::Info BuiltinInfo[]; 3286 static const char * const GCCRegNames[]; 3287 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3288 std::string CPU; 3289 public: 3290 HexagonTargetInfo(const std::string& triple) : TargetInfo(triple) { 3291 BigEndian = false; 3292 DescriptionString = ("e-p:32:32:32-" 3293 "i64:64:64-i32:32:32-i16:16:16-i1:32:32" 3294 "f64:64:64-f32:32:32-a0:0-n32"); 3295 3296 // {} in inline assembly are packet specifiers, not assembly variant 3297 // specifiers. 3298 NoAsmVariants = true; 3299 } 3300 3301 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3302 unsigned &NumRecords) const { 3303 Records = BuiltinInfo; 3304 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 3305 } 3306 3307 virtual bool validateAsmConstraint(const char *&Name, 3308 TargetInfo::ConstraintInfo &Info) const { 3309 return true; 3310 } 3311 3312 virtual void getTargetDefines(const LangOptions &Opts, 3313 MacroBuilder &Builder) const; 3314 3315 virtual bool hasFeature(StringRef Feature) const { 3316 return Feature == "hexagon"; 3317 } 3318 3319 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3320 return TargetInfo::CharPtrBuiltinVaList; 3321 } 3322 virtual void getGCCRegNames(const char * const *&Names, 3323 unsigned &NumNames) const; 3324 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3325 unsigned &NumAliases) const; 3326 virtual const char *getClobbers() const { 3327 return ""; 3328 } 3329 3330 static const char *getHexagonCPUSuffix(StringRef Name) { 3331 return llvm::StringSwitch<const char*>(Name) 3332 .Case("hexagonv2", "2") 3333 .Case("hexagonv3", "3") 3334 .Case("hexagonv4", "4") 3335 .Case("hexagonv5", "5") 3336 .Default(0); 3337 } 3338 3339 virtual bool setCPU(const std::string &Name) { 3340 if (!getHexagonCPUSuffix(Name)) 3341 return false; 3342 3343 CPU = Name; 3344 return true; 3345 } 3346 }; 3347 3348 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 3349 MacroBuilder &Builder) const { 3350 Builder.defineMacro("qdsp6"); 3351 Builder.defineMacro("__qdsp6", "1"); 3352 Builder.defineMacro("__qdsp6__", "1"); 3353 3354 Builder.defineMacro("hexagon"); 3355 Builder.defineMacro("__hexagon", "1"); 3356 Builder.defineMacro("__hexagon__", "1"); 3357 3358 if(CPU == "hexagonv1") { 3359 Builder.defineMacro("__HEXAGON_V1__"); 3360 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 3361 if(Opts.HexagonQdsp6Compat) { 3362 Builder.defineMacro("__QDSP6_V1__"); 3363 Builder.defineMacro("__QDSP6_ARCH__", "1"); 3364 } 3365 } 3366 else if(CPU == "hexagonv2") { 3367 Builder.defineMacro("__HEXAGON_V2__"); 3368 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 3369 if(Opts.HexagonQdsp6Compat) { 3370 Builder.defineMacro("__QDSP6_V2__"); 3371 Builder.defineMacro("__QDSP6_ARCH__", "2"); 3372 } 3373 } 3374 else if(CPU == "hexagonv3") { 3375 Builder.defineMacro("__HEXAGON_V3__"); 3376 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 3377 if(Opts.HexagonQdsp6Compat) { 3378 Builder.defineMacro("__QDSP6_V3__"); 3379 Builder.defineMacro("__QDSP6_ARCH__", "3"); 3380 } 3381 } 3382 else if(CPU == "hexagonv4") { 3383 Builder.defineMacro("__HEXAGON_V4__"); 3384 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 3385 if(Opts.HexagonQdsp6Compat) { 3386 Builder.defineMacro("__QDSP6_V4__"); 3387 Builder.defineMacro("__QDSP6_ARCH__", "4"); 3388 } 3389 } 3390 else if(CPU == "hexagonv5") { 3391 Builder.defineMacro("__HEXAGON_V5__"); 3392 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 3393 if(Opts.HexagonQdsp6Compat) { 3394 Builder.defineMacro("__QDSP6_V5__"); 3395 Builder.defineMacro("__QDSP6_ARCH__", "5"); 3396 } 3397 } 3398 } 3399 3400 const char * const HexagonTargetInfo::GCCRegNames[] = { 3401 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3402 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3403 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3404 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 3405 "p0", "p1", "p2", "p3", 3406 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 3407 }; 3408 3409 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 3410 unsigned &NumNames) const { 3411 Names = GCCRegNames; 3412 NumNames = llvm::array_lengthof(GCCRegNames); 3413 } 3414 3415 3416 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 3417 { { "sp" }, "r29" }, 3418 { { "fp" }, "r30" }, 3419 { { "lr" }, "r31" }, 3420 }; 3421 3422 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3423 unsigned &NumAliases) const { 3424 Aliases = GCCRegAliases; 3425 NumAliases = llvm::array_lengthof(GCCRegAliases); 3426 } 3427 3428 3429 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 3430 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3431 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3432 ALL_LANGUAGES }, 3433 #include "clang/Basic/BuiltinsHexagon.def" 3434 }; 3435 } 3436 3437 3438 namespace { 3439 class SparcV8TargetInfo : public TargetInfo { 3440 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3441 static const char * const GCCRegNames[]; 3442 bool SoftFloat; 3443 public: 3444 SparcV8TargetInfo(const std::string& triple) : TargetInfo(triple) { 3445 // FIXME: Support Sparc quad-precision long double? 3446 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3447 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3448 } 3449 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3450 StringRef Name, 3451 bool Enabled) const { 3452 if (Name == "soft-float") 3453 Features[Name] = Enabled; 3454 else 3455 return false; 3456 3457 return true; 3458 } 3459 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3460 SoftFloat = false; 3461 for (unsigned i = 0, e = Features.size(); i != e; ++i) 3462 if (Features[i] == "+soft-float") 3463 SoftFloat = true; 3464 } 3465 virtual void getTargetDefines(const LangOptions &Opts, 3466 MacroBuilder &Builder) const { 3467 DefineStd(Builder, "sparc", Opts); 3468 Builder.defineMacro("__sparcv8"); 3469 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3470 3471 if (SoftFloat) 3472 Builder.defineMacro("SOFT_FLOAT", "1"); 3473 } 3474 3475 virtual bool hasFeature(StringRef Feature) const { 3476 return llvm::StringSwitch<bool>(Feature) 3477 .Case("softfloat", SoftFloat) 3478 .Case("sparc", true) 3479 .Default(false); 3480 } 3481 3482 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3483 unsigned &NumRecords) const { 3484 // FIXME: Implement! 3485 } 3486 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3487 return TargetInfo::VoidPtrBuiltinVaList; 3488 } 3489 virtual void getGCCRegNames(const char * const *&Names, 3490 unsigned &NumNames) const; 3491 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3492 unsigned &NumAliases) const; 3493 virtual bool validateAsmConstraint(const char *&Name, 3494 TargetInfo::ConstraintInfo &info) const { 3495 // FIXME: Implement! 3496 return false; 3497 } 3498 virtual const char *getClobbers() const { 3499 // FIXME: Implement! 3500 return ""; 3501 } 3502 }; 3503 3504 const char * const SparcV8TargetInfo::GCCRegNames[] = { 3505 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3506 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 3507 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 3508 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 3509 }; 3510 3511 void SparcV8TargetInfo::getGCCRegNames(const char * const *&Names, 3512 unsigned &NumNames) const { 3513 Names = GCCRegNames; 3514 NumNames = llvm::array_lengthof(GCCRegNames); 3515 } 3516 3517 const TargetInfo::GCCRegAlias SparcV8TargetInfo::GCCRegAliases[] = { 3518 { { "g0" }, "r0" }, 3519 { { "g1" }, "r1" }, 3520 { { "g2" }, "r2" }, 3521 { { "g3" }, "r3" }, 3522 { { "g4" }, "r4" }, 3523 { { "g5" }, "r5" }, 3524 { { "g6" }, "r6" }, 3525 { { "g7" }, "r7" }, 3526 { { "o0" }, "r8" }, 3527 { { "o1" }, "r9" }, 3528 { { "o2" }, "r10" }, 3529 { { "o3" }, "r11" }, 3530 { { "o4" }, "r12" }, 3531 { { "o5" }, "r13" }, 3532 { { "o6", "sp" }, "r14" }, 3533 { { "o7" }, "r15" }, 3534 { { "l0" }, "r16" }, 3535 { { "l1" }, "r17" }, 3536 { { "l2" }, "r18" }, 3537 { { "l3" }, "r19" }, 3538 { { "l4" }, "r20" }, 3539 { { "l5" }, "r21" }, 3540 { { "l6" }, "r22" }, 3541 { { "l7" }, "r23" }, 3542 { { "i0" }, "r24" }, 3543 { { "i1" }, "r25" }, 3544 { { "i2" }, "r26" }, 3545 { { "i3" }, "r27" }, 3546 { { "i4" }, "r28" }, 3547 { { "i5" }, "r29" }, 3548 { { "i6", "fp" }, "r30" }, 3549 { { "i7" }, "r31" }, 3550 }; 3551 3552 void SparcV8TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3553 unsigned &NumAliases) const { 3554 Aliases = GCCRegAliases; 3555 NumAliases = llvm::array_lengthof(GCCRegAliases); 3556 } 3557 } // end anonymous namespace. 3558 3559 namespace { 3560 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 3561 public: 3562 AuroraUXSparcV8TargetInfo(const std::string& triple) : 3563 AuroraUXTargetInfo<SparcV8TargetInfo>(triple) { 3564 SizeType = UnsignedInt; 3565 PtrDiffType = SignedInt; 3566 } 3567 }; 3568 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 3569 public: 3570 SolarisSparcV8TargetInfo(const std::string& triple) : 3571 SolarisTargetInfo<SparcV8TargetInfo>(triple) { 3572 SizeType = UnsignedInt; 3573 PtrDiffType = SignedInt; 3574 } 3575 }; 3576 } // end anonymous namespace. 3577 3578 namespace { 3579 class MSP430TargetInfo : public TargetInfo { 3580 static const char * const GCCRegNames[]; 3581 public: 3582 MSP430TargetInfo(const std::string& triple) : TargetInfo(triple) { 3583 BigEndian = false; 3584 TLSSupported = false; 3585 IntWidth = 16; IntAlign = 16; 3586 LongWidth = 32; LongLongWidth = 64; 3587 LongAlign = LongLongAlign = 16; 3588 PointerWidth = 16; PointerAlign = 16; 3589 SuitableAlign = 16; 3590 SizeType = UnsignedInt; 3591 IntMaxType = SignedLong; 3592 UIntMaxType = UnsignedLong; 3593 IntPtrType = SignedShort; 3594 PtrDiffType = SignedInt; 3595 SigAtomicType = SignedLong; 3596 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 3597 } 3598 virtual void getTargetDefines(const LangOptions &Opts, 3599 MacroBuilder &Builder) const { 3600 Builder.defineMacro("MSP430"); 3601 Builder.defineMacro("__MSP430__"); 3602 // FIXME: defines for different 'flavours' of MCU 3603 } 3604 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3605 unsigned &NumRecords) const { 3606 // FIXME: Implement. 3607 Records = 0; 3608 NumRecords = 0; 3609 } 3610 virtual bool hasFeature(StringRef Feature) const { 3611 return Feature == "msp430"; 3612 } 3613 virtual void getGCCRegNames(const char * const *&Names, 3614 unsigned &NumNames) const; 3615 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3616 unsigned &NumAliases) const { 3617 // No aliases. 3618 Aliases = 0; 3619 NumAliases = 0; 3620 } 3621 virtual bool validateAsmConstraint(const char *&Name, 3622 TargetInfo::ConstraintInfo &info) const { 3623 // No target constraints for now. 3624 return false; 3625 } 3626 virtual const char *getClobbers() const { 3627 // FIXME: Is this really right? 3628 return ""; 3629 } 3630 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3631 // FIXME: implement 3632 return TargetInfo::CharPtrBuiltinVaList; 3633 } 3634 }; 3635 3636 const char * const MSP430TargetInfo::GCCRegNames[] = { 3637 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 3638 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 3639 }; 3640 3641 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 3642 unsigned &NumNames) const { 3643 Names = GCCRegNames; 3644 NumNames = llvm::array_lengthof(GCCRegNames); 3645 } 3646 } 3647 3648 namespace { 3649 3650 // LLVM and Clang cannot be used directly to output native binaries for 3651 // target, but is used to compile C code to llvm bitcode with correct 3652 // type and alignment information. 3653 // 3654 // TCE uses the llvm bitcode as input and uses it for generating customized 3655 // target processor and program binary. TCE co-design environment is 3656 // publicly available in http://tce.cs.tut.fi 3657 3658 static const unsigned TCEOpenCLAddrSpaceMap[] = { 3659 3, // opencl_global 3660 4, // opencl_local 3661 5, // opencl_constant 3662 0, // cuda_device 3663 0, // cuda_constant 3664 0 // cuda_shared 3665 }; 3666 3667 class TCETargetInfo : public TargetInfo{ 3668 public: 3669 TCETargetInfo(const std::string& triple) : TargetInfo(triple) { 3670 TLSSupported = false; 3671 IntWidth = 32; 3672 LongWidth = LongLongWidth = 32; 3673 PointerWidth = 32; 3674 IntAlign = 32; 3675 LongAlign = LongLongAlign = 32; 3676 PointerAlign = 32; 3677 SuitableAlign = 32; 3678 SizeType = UnsignedInt; 3679 IntMaxType = SignedLong; 3680 UIntMaxType = UnsignedLong; 3681 IntPtrType = SignedInt; 3682 PtrDiffType = SignedInt; 3683 FloatWidth = 32; 3684 FloatAlign = 32; 3685 DoubleWidth = 32; 3686 DoubleAlign = 32; 3687 LongDoubleWidth = 32; 3688 LongDoubleAlign = 32; 3689 FloatFormat = &llvm::APFloat::IEEEsingle; 3690 DoubleFormat = &llvm::APFloat::IEEEsingle; 3691 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 3692 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 3693 "i16:16:32-i32:32:32-i64:32:32-" 3694 "f32:32:32-f64:32:32-v64:32:32-" 3695 "v128:32:32-a0:0:32-n32"; 3696 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 3697 } 3698 3699 virtual void getTargetDefines(const LangOptions &Opts, 3700 MacroBuilder &Builder) const { 3701 DefineStd(Builder, "tce", Opts); 3702 Builder.defineMacro("__TCE__"); 3703 Builder.defineMacro("__TCE_V1__"); 3704 } 3705 virtual bool hasFeature(StringRef Feature) const { 3706 return Feature == "tce"; 3707 } 3708 3709 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3710 unsigned &NumRecords) const {} 3711 virtual const char *getClobbers() const { 3712 return ""; 3713 } 3714 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3715 return TargetInfo::VoidPtrBuiltinVaList; 3716 } 3717 virtual void getGCCRegNames(const char * const *&Names, 3718 unsigned &NumNames) const {} 3719 virtual bool validateAsmConstraint(const char *&Name, 3720 TargetInfo::ConstraintInfo &info) const { 3721 return true; 3722 } 3723 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3724 unsigned &NumAliases) const {} 3725 }; 3726 } 3727 3728 namespace { 3729 class MipsTargetInfoBase : public TargetInfo { 3730 static const Builtin::Info BuiltinInfo[]; 3731 std::string CPU; 3732 bool IsMips16; 3733 enum MipsFloatABI { 3734 HardFloat, SingleFloat, SoftFloat 3735 } FloatABI; 3736 enum DspRevEnum { 3737 NoDSP, DSP1, DSP2 3738 } DspRev; 3739 3740 protected: 3741 std::string ABI; 3742 3743 public: 3744 MipsTargetInfoBase(const std::string& triple, 3745 const std::string& ABIStr, 3746 const std::string& CPUStr) 3747 : TargetInfo(triple), 3748 CPU(CPUStr), 3749 IsMips16(false), 3750 FloatABI(HardFloat), 3751 DspRev(NoDSP), 3752 ABI(ABIStr) 3753 {} 3754 3755 virtual const char *getABI() const { return ABI.c_str(); } 3756 virtual bool setABI(const std::string &Name) = 0; 3757 virtual bool setCPU(const std::string &Name) { 3758 CPU = Name; 3759 return true; 3760 } 3761 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3762 Features[ABI] = true; 3763 Features[CPU] = true; 3764 } 3765 3766 virtual void getTargetDefines(const LangOptions &Opts, 3767 MacroBuilder &Builder) const { 3768 DefineStd(Builder, "mips", Opts); 3769 Builder.defineMacro("_mips"); 3770 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3771 3772 switch (FloatABI) { 3773 case HardFloat: 3774 Builder.defineMacro("__mips_hard_float", Twine(1)); 3775 break; 3776 case SingleFloat: 3777 Builder.defineMacro("__mips_hard_float", Twine(1)); 3778 Builder.defineMacro("__mips_single_float", Twine(1)); 3779 break; 3780 case SoftFloat: 3781 Builder.defineMacro("__mips_soft_float", Twine(1)); 3782 break; 3783 } 3784 3785 if (IsMips16) 3786 Builder.defineMacro("__mips16", Twine(1)); 3787 3788 switch (DspRev) { 3789 default: 3790 break; 3791 case DSP1: 3792 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 3793 Builder.defineMacro("__mips_dsp", Twine(1)); 3794 break; 3795 case DSP2: 3796 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 3797 Builder.defineMacro("__mips_dspr2", Twine(1)); 3798 Builder.defineMacro("__mips_dsp", Twine(1)); 3799 break; 3800 } 3801 3802 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 3803 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 3804 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 3805 3806 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 3807 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 3808 } 3809 3810 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3811 unsigned &NumRecords) const { 3812 Records = BuiltinInfo; 3813 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 3814 } 3815 virtual bool hasFeature(StringRef Feature) const { 3816 return Feature == "mips"; 3817 } 3818 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3819 return TargetInfo::VoidPtrBuiltinVaList; 3820 } 3821 virtual void getGCCRegNames(const char * const *&Names, 3822 unsigned &NumNames) const { 3823 static const char * const GCCRegNames[] = { 3824 // CPU register names 3825 // Must match second column of GCCRegAliases 3826 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 3827 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 3828 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 3829 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 3830 // Floating point register names 3831 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 3832 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 3833 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 3834 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 3835 // Hi/lo and condition register names 3836 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 3837 "$fcc5","$fcc6","$fcc7" 3838 }; 3839 Names = GCCRegNames; 3840 NumNames = llvm::array_lengthof(GCCRegNames); 3841 } 3842 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3843 unsigned &NumAliases) const = 0; 3844 virtual bool validateAsmConstraint(const char *&Name, 3845 TargetInfo::ConstraintInfo &Info) const { 3846 switch (*Name) { 3847 default: 3848 return false; 3849 3850 case 'r': // CPU registers. 3851 case 'd': // Equivalent to "r" unless generating MIPS16 code. 3852 case 'y': // Equivalent to "r", backwards compatibility only. 3853 case 'f': // floating-point registers. 3854 case 'c': // $25 for indirect jumps 3855 case 'l': // lo register 3856 case 'x': // hilo register pair 3857 Info.setAllowsRegister(); 3858 return true; 3859 } 3860 } 3861 3862 virtual const char *getClobbers() const { 3863 // FIXME: Implement! 3864 return ""; 3865 } 3866 3867 virtual bool setFeatureEnabled(llvm::StringMap<bool> &Features, 3868 StringRef Name, 3869 bool Enabled) const { 3870 if (Name == "soft-float" || Name == "single-float" || 3871 Name == "o32" || Name == "n32" || Name == "n64" || Name == "eabi" || 3872 Name == "mips32" || Name == "mips32r2" || 3873 Name == "mips64" || Name == "mips64r2" || 3874 Name == "mips16" || Name == "dsp" || Name == "dspr2") { 3875 Features[Name] = Enabled; 3876 return true; 3877 } 3878 return false; 3879 } 3880 3881 virtual void HandleTargetFeatures(std::vector<std::string> &Features) { 3882 IsMips16 = false; 3883 FloatABI = HardFloat; 3884 DspRev = NoDSP; 3885 3886 for (std::vector<std::string>::iterator it = Features.begin(), 3887 ie = Features.end(); it != ie; ++it) { 3888 if (*it == "+single-float") 3889 FloatABI = SingleFloat; 3890 else if (*it == "+soft-float") 3891 FloatABI = SoftFloat; 3892 else if (*it == "+mips16") 3893 IsMips16 = true; 3894 else if (*it == "+dsp") 3895 DspRev = std::max(DspRev, DSP1); 3896 else if (*it == "+dspr2") 3897 DspRev = std::max(DspRev, DSP2); 3898 } 3899 3900 // Remove front-end specific option. 3901 std::vector<std::string>::iterator it = 3902 std::find(Features.begin(), Features.end(), "+soft-float"); 3903 if (it != Features.end()) 3904 Features.erase(it); 3905 } 3906 }; 3907 3908 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 3909 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3910 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3911 ALL_LANGUAGES }, 3912 #include "clang/Basic/BuiltinsMips.def" 3913 }; 3914 3915 class Mips32TargetInfoBase : public MipsTargetInfoBase { 3916 public: 3917 Mips32TargetInfoBase(const std::string& triple) : 3918 MipsTargetInfoBase(triple, "o32", "mips32") { 3919 SizeType = UnsignedInt; 3920 PtrDiffType = SignedInt; 3921 } 3922 virtual bool setABI(const std::string &Name) { 3923 if ((Name == "o32") || (Name == "eabi")) { 3924 ABI = Name; 3925 return true; 3926 } else 3927 return false; 3928 } 3929 virtual void getTargetDefines(const LangOptions &Opts, 3930 MacroBuilder &Builder) const { 3931 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 3932 3933 if (ABI == "o32") { 3934 Builder.defineMacro("__mips_o32"); 3935 Builder.defineMacro("_ABIO32", "1"); 3936 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 3937 } 3938 else if (ABI == "eabi") 3939 Builder.defineMacro("__mips_eabi"); 3940 else 3941 llvm_unreachable("Invalid ABI for Mips32."); 3942 } 3943 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3944 unsigned &NumAliases) const { 3945 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 3946 { { "at" }, "$1" }, 3947 { { "v0" }, "$2" }, 3948 { { "v1" }, "$3" }, 3949 { { "a0" }, "$4" }, 3950 { { "a1" }, "$5" }, 3951 { { "a2" }, "$6" }, 3952 { { "a3" }, "$7" }, 3953 { { "t0" }, "$8" }, 3954 { { "t1" }, "$9" }, 3955 { { "t2" }, "$10" }, 3956 { { "t3" }, "$11" }, 3957 { { "t4" }, "$12" }, 3958 { { "t5" }, "$13" }, 3959 { { "t6" }, "$14" }, 3960 { { "t7" }, "$15" }, 3961 { { "s0" }, "$16" }, 3962 { { "s1" }, "$17" }, 3963 { { "s2" }, "$18" }, 3964 { { "s3" }, "$19" }, 3965 { { "s4" }, "$20" }, 3966 { { "s5" }, "$21" }, 3967 { { "s6" }, "$22" }, 3968 { { "s7" }, "$23" }, 3969 { { "t8" }, "$24" }, 3970 { { "t9" }, "$25" }, 3971 { { "k0" }, "$26" }, 3972 { { "k1" }, "$27" }, 3973 { { "gp" }, "$28" }, 3974 { { "sp","$sp" }, "$29" }, 3975 { { "fp","$fp" }, "$30" }, 3976 { { "ra" }, "$31" } 3977 }; 3978 Aliases = GCCRegAliases; 3979 NumAliases = llvm::array_lengthof(GCCRegAliases); 3980 } 3981 }; 3982 3983 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 3984 public: 3985 Mips32EBTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 3986 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 3987 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 3988 } 3989 virtual void getTargetDefines(const LangOptions &Opts, 3990 MacroBuilder &Builder) const { 3991 DefineStd(Builder, "MIPSEB", Opts); 3992 Builder.defineMacro("_MIPSEB"); 3993 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 3994 } 3995 }; 3996 3997 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 3998 public: 3999 Mips32ELTargetInfo(const std::string& triple) : Mips32TargetInfoBase(triple) { 4000 BigEndian = false; 4001 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4002 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32"; 4003 } 4004 virtual void getTargetDefines(const LangOptions &Opts, 4005 MacroBuilder &Builder) const { 4006 DefineStd(Builder, "MIPSEL", Opts); 4007 Builder.defineMacro("_MIPSEL"); 4008 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 4009 } 4010 }; 4011 4012 class Mips64TargetInfoBase : public MipsTargetInfoBase { 4013 virtual void SetDescriptionString(const std::string &Name) = 0; 4014 public: 4015 Mips64TargetInfoBase(const std::string& triple) : 4016 MipsTargetInfoBase(triple, "n64", "mips64") { 4017 LongWidth = LongAlign = 64; 4018 PointerWidth = PointerAlign = 64; 4019 LongDoubleWidth = LongDoubleAlign = 128; 4020 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4021 SuitableAlign = 128; 4022 } 4023 virtual bool setABI(const std::string &Name) { 4024 SetDescriptionString(Name); 4025 4026 if (Name != "n32" && Name != "n64") 4027 return false; 4028 4029 ABI = Name; 4030 4031 if (Name == "n32") { 4032 LongWidth = LongAlign = 32; 4033 PointerWidth = PointerAlign = 32; 4034 } 4035 4036 return true; 4037 } 4038 virtual void getTargetDefines(const LangOptions &Opts, 4039 MacroBuilder &Builder) const { 4040 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 4041 4042 Builder.defineMacro("__mips64"); 4043 Builder.defineMacro("__mips64__"); 4044 4045 if (ABI == "n32") { 4046 Builder.defineMacro("__mips_n32"); 4047 Builder.defineMacro("_ABIN32", "2"); 4048 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 4049 } 4050 else if (ABI == "n64") { 4051 Builder.defineMacro("__mips_n64"); 4052 Builder.defineMacro("_ABI64", "3"); 4053 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 4054 } 4055 else 4056 llvm_unreachable("Invalid ABI for Mips64."); 4057 } 4058 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4059 unsigned &NumAliases) const { 4060 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 4061 { { "at" }, "$1" }, 4062 { { "v0" }, "$2" }, 4063 { { "v1" }, "$3" }, 4064 { { "a0" }, "$4" }, 4065 { { "a1" }, "$5" }, 4066 { { "a2" }, "$6" }, 4067 { { "a3" }, "$7" }, 4068 { { "a4" }, "$8" }, 4069 { { "a5" }, "$9" }, 4070 { { "a6" }, "$10" }, 4071 { { "a7" }, "$11" }, 4072 { { "t0" }, "$12" }, 4073 { { "t1" }, "$13" }, 4074 { { "t2" }, "$14" }, 4075 { { "t3" }, "$15" }, 4076 { { "s0" }, "$16" }, 4077 { { "s1" }, "$17" }, 4078 { { "s2" }, "$18" }, 4079 { { "s3" }, "$19" }, 4080 { { "s4" }, "$20" }, 4081 { { "s5" }, "$21" }, 4082 { { "s6" }, "$22" }, 4083 { { "s7" }, "$23" }, 4084 { { "t8" }, "$24" }, 4085 { { "t9" }, "$25" }, 4086 { { "k0" }, "$26" }, 4087 { { "k1" }, "$27" }, 4088 { { "gp" }, "$28" }, 4089 { { "sp","$sp" }, "$29" }, 4090 { { "fp","$fp" }, "$30" }, 4091 { { "ra" }, "$31" } 4092 }; 4093 Aliases = GCCRegAliases; 4094 NumAliases = llvm::array_lengthof(GCCRegAliases); 4095 } 4096 }; 4097 4098 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 4099 virtual void SetDescriptionString(const std::string &Name) { 4100 // Change DescriptionString only if ABI is n32. 4101 if (Name == "n32") 4102 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4103 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4104 "v64:64:64-n32"; 4105 } 4106 public: 4107 Mips64EBTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4108 // Default ABI is n64. 4109 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4110 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4111 "v64:64:64-n32"; 4112 } 4113 virtual void getTargetDefines(const LangOptions &Opts, 4114 MacroBuilder &Builder) const { 4115 DefineStd(Builder, "MIPSEB", Opts); 4116 Builder.defineMacro("_MIPSEB"); 4117 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4118 } 4119 }; 4120 4121 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 4122 virtual void SetDescriptionString(const std::string &Name) { 4123 // Change DescriptionString only if ABI is n32. 4124 if (Name == "n32") 4125 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4126 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 4127 "-v64:64:64-n32"; 4128 } 4129 public: 4130 Mips64ELTargetInfo(const std::string& triple) : Mips64TargetInfoBase(triple) { 4131 // Default ABI is n64. 4132 BigEndian = false; 4133 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 4134 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 4135 "v64:64:64-n32"; 4136 } 4137 virtual void getTargetDefines(const LangOptions &Opts, 4138 MacroBuilder &Builder) const { 4139 DefineStd(Builder, "MIPSEL", Opts); 4140 Builder.defineMacro("_MIPSEL"); 4141 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 4142 } 4143 }; 4144 } // end anonymous namespace. 4145 4146 namespace { 4147 class PNaClTargetInfo : public TargetInfo { 4148 public: 4149 PNaClTargetInfo(const std::string& triple) : TargetInfo(triple) { 4150 BigEndian = false; 4151 this->UserLabelPrefix = ""; 4152 this->LongAlign = 32; 4153 this->LongWidth = 32; 4154 this->PointerAlign = 32; 4155 this->PointerWidth = 32; 4156 this->IntMaxType = TargetInfo::SignedLongLong; 4157 this->UIntMaxType = TargetInfo::UnsignedLongLong; 4158 this->Int64Type = TargetInfo::SignedLongLong; 4159 this->DoubleAlign = 64; 4160 this->LongDoubleWidth = 64; 4161 this->LongDoubleAlign = 64; 4162 this->SizeType = TargetInfo::UnsignedInt; 4163 this->PtrDiffType = TargetInfo::SignedInt; 4164 this->IntPtrType = TargetInfo::SignedInt; 4165 this->RegParmMax = 2; 4166 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 4167 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 4168 } 4169 4170 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4171 } 4172 virtual void getArchDefines(const LangOptions &Opts, 4173 MacroBuilder &Builder) const { 4174 Builder.defineMacro("__le32__"); 4175 Builder.defineMacro("__pnacl__"); 4176 } 4177 virtual void getTargetDefines(const LangOptions &Opts, 4178 MacroBuilder &Builder) const { 4179 DefineStd(Builder, "unix", Opts); 4180 Builder.defineMacro("__ELF__"); 4181 if (Opts.POSIXThreads) 4182 Builder.defineMacro("_REENTRANT"); 4183 if (Opts.CPlusPlus) 4184 Builder.defineMacro("_GNU_SOURCE"); 4185 4186 Builder.defineMacro("__LITTLE_ENDIAN__"); 4187 Builder.defineMacro("__native_client__"); 4188 getArchDefines(Opts, Builder); 4189 } 4190 virtual bool hasFeature(StringRef Feature) const { 4191 return Feature == "pnacl"; 4192 } 4193 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4194 unsigned &NumRecords) const { 4195 } 4196 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4197 return TargetInfo::PNaClABIBuiltinVaList; 4198 } 4199 virtual void getGCCRegNames(const char * const *&Names, 4200 unsigned &NumNames) const; 4201 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4202 unsigned &NumAliases) const; 4203 virtual bool validateAsmConstraint(const char *&Name, 4204 TargetInfo::ConstraintInfo &Info) const { 4205 return false; 4206 } 4207 4208 virtual const char *getClobbers() const { 4209 return ""; 4210 } 4211 }; 4212 4213 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 4214 unsigned &NumNames) const { 4215 Names = NULL; 4216 NumNames = 0; 4217 } 4218 4219 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4220 unsigned &NumAliases) const { 4221 Aliases = NULL; 4222 NumAliases = 0; 4223 } 4224 } // end anonymous namespace. 4225 4226 4227 //===----------------------------------------------------------------------===// 4228 // Driver code 4229 //===----------------------------------------------------------------------===// 4230 4231 static TargetInfo *AllocateTarget(const std::string &T) { 4232 llvm::Triple Triple(T); 4233 llvm::Triple::OSType os = Triple.getOS(); 4234 4235 switch (Triple.getArch()) { 4236 default: 4237 return NULL; 4238 4239 case llvm::Triple::hexagon: 4240 return new HexagonTargetInfo(T); 4241 4242 case llvm::Triple::arm: 4243 case llvm::Triple::thumb: 4244 if (Triple.isOSDarwin()) 4245 return new DarwinARMTargetInfo(T); 4246 4247 switch (os) { 4248 case llvm::Triple::Linux: 4249 return new LinuxTargetInfo<ARMTargetInfo>(T); 4250 case llvm::Triple::FreeBSD: 4251 return new FreeBSDTargetInfo<ARMTargetInfo>(T); 4252 case llvm::Triple::NetBSD: 4253 return new NetBSDTargetInfo<ARMTargetInfo>(T); 4254 case llvm::Triple::OpenBSD: 4255 return new OpenBSDTargetInfo<ARMTargetInfo>(T); 4256 case llvm::Triple::Bitrig: 4257 return new BitrigTargetInfo<ARMTargetInfo>(T); 4258 case llvm::Triple::RTEMS: 4259 return new RTEMSTargetInfo<ARMTargetInfo>(T); 4260 default: 4261 return new ARMTargetInfo(T); 4262 } 4263 4264 case llvm::Triple::msp430: 4265 return new MSP430TargetInfo(T); 4266 4267 case llvm::Triple::mips: 4268 switch (os) { 4269 case llvm::Triple::Linux: 4270 return new LinuxTargetInfo<Mips32EBTargetInfo>(T); 4271 case llvm::Triple::RTEMS: 4272 return new RTEMSTargetInfo<Mips32EBTargetInfo>(T); 4273 case llvm::Triple::FreeBSD: 4274 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(T); 4275 case llvm::Triple::NetBSD: 4276 return new NetBSDTargetInfo<Mips32EBTargetInfo>(T); 4277 default: 4278 return new Mips32EBTargetInfo(T); 4279 } 4280 4281 case llvm::Triple::mipsel: 4282 switch (os) { 4283 case llvm::Triple::Linux: 4284 return new LinuxTargetInfo<Mips32ELTargetInfo>(T); 4285 case llvm::Triple::RTEMS: 4286 return new RTEMSTargetInfo<Mips32ELTargetInfo>(T); 4287 case llvm::Triple::FreeBSD: 4288 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(T); 4289 case llvm::Triple::NetBSD: 4290 return new NetBSDTargetInfo<Mips32ELTargetInfo>(T); 4291 default: 4292 return new Mips32ELTargetInfo(T); 4293 } 4294 4295 case llvm::Triple::mips64: 4296 switch (os) { 4297 case llvm::Triple::Linux: 4298 return new LinuxTargetInfo<Mips64EBTargetInfo>(T); 4299 case llvm::Triple::RTEMS: 4300 return new RTEMSTargetInfo<Mips64EBTargetInfo>(T); 4301 case llvm::Triple::FreeBSD: 4302 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(T); 4303 case llvm::Triple::NetBSD: 4304 return new NetBSDTargetInfo<Mips64EBTargetInfo>(T); 4305 case llvm::Triple::OpenBSD: 4306 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(T); 4307 default: 4308 return new Mips64EBTargetInfo(T); 4309 } 4310 4311 case llvm::Triple::mips64el: 4312 switch (os) { 4313 case llvm::Triple::Linux: 4314 return new LinuxTargetInfo<Mips64ELTargetInfo>(T); 4315 case llvm::Triple::RTEMS: 4316 return new RTEMSTargetInfo<Mips64ELTargetInfo>(T); 4317 case llvm::Triple::FreeBSD: 4318 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(T); 4319 case llvm::Triple::NetBSD: 4320 return new NetBSDTargetInfo<Mips64ELTargetInfo>(T); 4321 case llvm::Triple::OpenBSD: 4322 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(T); 4323 default: 4324 return new Mips64ELTargetInfo(T); 4325 } 4326 4327 case llvm::Triple::le32: 4328 switch (os) { 4329 case llvm::Triple::NativeClient: 4330 return new PNaClTargetInfo(T); 4331 default: 4332 return NULL; 4333 } 4334 4335 case llvm::Triple::ppc: 4336 if (Triple.isOSDarwin()) 4337 return new DarwinPPC32TargetInfo(T); 4338 switch (os) { 4339 case llvm::Triple::Linux: 4340 return new LinuxTargetInfo<PPC32TargetInfo>(T); 4341 case llvm::Triple::FreeBSD: 4342 return new FreeBSDTargetInfo<PPC32TargetInfo>(T); 4343 case llvm::Triple::NetBSD: 4344 return new NetBSDTargetInfo<PPC32TargetInfo>(T); 4345 case llvm::Triple::OpenBSD: 4346 return new OpenBSDTargetInfo<PPC32TargetInfo>(T); 4347 case llvm::Triple::RTEMS: 4348 return new RTEMSTargetInfo<PPC32TargetInfo>(T); 4349 default: 4350 return new PPC32TargetInfo(T); 4351 } 4352 4353 case llvm::Triple::ppc64: 4354 if (Triple.isOSDarwin()) 4355 return new DarwinPPC64TargetInfo(T); 4356 switch (os) { 4357 case llvm::Triple::Linux: 4358 return new LinuxTargetInfo<PPC64TargetInfo>(T); 4359 case llvm::Triple::Lv2: 4360 return new PS3PPUTargetInfo<PPC64TargetInfo>(T); 4361 case llvm::Triple::FreeBSD: 4362 return new FreeBSDTargetInfo<PPC64TargetInfo>(T); 4363 case llvm::Triple::NetBSD: 4364 return new NetBSDTargetInfo<PPC64TargetInfo>(T); 4365 default: 4366 return new PPC64TargetInfo(T); 4367 } 4368 4369 case llvm::Triple::nvptx: 4370 return new NVPTX32TargetInfo(T); 4371 case llvm::Triple::nvptx64: 4372 return new NVPTX64TargetInfo(T); 4373 4374 case llvm::Triple::mblaze: 4375 return new MBlazeTargetInfo(T); 4376 4377 case llvm::Triple::sparc: 4378 switch (os) { 4379 case llvm::Triple::Linux: 4380 return new LinuxTargetInfo<SparcV8TargetInfo>(T); 4381 case llvm::Triple::AuroraUX: 4382 return new AuroraUXSparcV8TargetInfo(T); 4383 case llvm::Triple::Solaris: 4384 return new SolarisSparcV8TargetInfo(T); 4385 case llvm::Triple::NetBSD: 4386 return new NetBSDTargetInfo<SparcV8TargetInfo>(T); 4387 case llvm::Triple::OpenBSD: 4388 return new OpenBSDTargetInfo<SparcV8TargetInfo>(T); 4389 case llvm::Triple::RTEMS: 4390 return new RTEMSTargetInfo<SparcV8TargetInfo>(T); 4391 default: 4392 return new SparcV8TargetInfo(T); 4393 } 4394 4395 // FIXME: Need a real SPU target. 4396 case llvm::Triple::cellspu: 4397 return new PS3SPUTargetInfo<PPC64TargetInfo>(T); 4398 4399 case llvm::Triple::tce: 4400 return new TCETargetInfo(T); 4401 4402 case llvm::Triple::x86: 4403 if (Triple.isOSDarwin()) 4404 return new DarwinI386TargetInfo(T); 4405 4406 switch (os) { 4407 case llvm::Triple::AuroraUX: 4408 return new AuroraUXTargetInfo<X86_32TargetInfo>(T); 4409 case llvm::Triple::Linux: 4410 return new LinuxTargetInfo<X86_32TargetInfo>(T); 4411 case llvm::Triple::DragonFly: 4412 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(T); 4413 case llvm::Triple::NetBSD: 4414 return new NetBSDI386TargetInfo(T); 4415 case llvm::Triple::OpenBSD: 4416 return new OpenBSDI386TargetInfo(T); 4417 case llvm::Triple::Bitrig: 4418 return new BitrigI386TargetInfo(T); 4419 case llvm::Triple::FreeBSD: 4420 return new FreeBSDTargetInfo<X86_32TargetInfo>(T); 4421 case llvm::Triple::Minix: 4422 return new MinixTargetInfo<X86_32TargetInfo>(T); 4423 case llvm::Triple::Solaris: 4424 return new SolarisTargetInfo<X86_32TargetInfo>(T); 4425 case llvm::Triple::Cygwin: 4426 return new CygwinX86_32TargetInfo(T); 4427 case llvm::Triple::MinGW32: 4428 return new MinGWX86_32TargetInfo(T); 4429 case llvm::Triple::Win32: 4430 return new VisualStudioWindowsX86_32TargetInfo(T); 4431 case llvm::Triple::Haiku: 4432 return new HaikuX86_32TargetInfo(T); 4433 case llvm::Triple::RTEMS: 4434 return new RTEMSX86_32TargetInfo(T); 4435 default: 4436 return new X86_32TargetInfo(T); 4437 } 4438 4439 case llvm::Triple::x86_64: 4440 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 4441 return new DarwinX86_64TargetInfo(T); 4442 4443 switch (os) { 4444 case llvm::Triple::AuroraUX: 4445 return new AuroraUXTargetInfo<X86_64TargetInfo>(T); 4446 case llvm::Triple::Linux: 4447 return new LinuxTargetInfo<X86_64TargetInfo>(T); 4448 case llvm::Triple::DragonFly: 4449 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(T); 4450 case llvm::Triple::NetBSD: 4451 return new NetBSDTargetInfo<X86_64TargetInfo>(T); 4452 case llvm::Triple::OpenBSD: 4453 return new OpenBSDX86_64TargetInfo(T); 4454 case llvm::Triple::Bitrig: 4455 return new BitrigX86_64TargetInfo(T); 4456 case llvm::Triple::FreeBSD: 4457 return new FreeBSDTargetInfo<X86_64TargetInfo>(T); 4458 case llvm::Triple::Solaris: 4459 return new SolarisTargetInfo<X86_64TargetInfo>(T); 4460 case llvm::Triple::MinGW32: 4461 return new MinGWX86_64TargetInfo(T); 4462 case llvm::Triple::Win32: // This is what Triple.h supports now. 4463 return new VisualStudioWindowsX86_64TargetInfo(T); 4464 default: 4465 return new X86_64TargetInfo(T); 4466 } 4467 } 4468 } 4469 4470 /// CreateTargetInfo - Return the target info object for the specified target 4471 /// triple. 4472 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 4473 TargetOptions &Opts) { 4474 llvm::Triple Triple(Opts.Triple); 4475 4476 // Construct the target 4477 OwningPtr<TargetInfo> Target(AllocateTarget(Triple.str())); 4478 if (!Target) { 4479 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 4480 return 0; 4481 } 4482 4483 // Set the target CPU if specified. 4484 if (!Opts.CPU.empty() && !Target->setCPU(Opts.CPU)) { 4485 Diags.Report(diag::err_target_unknown_cpu) << Opts.CPU; 4486 return 0; 4487 } 4488 4489 // Set the target ABI if specified. 4490 if (!Opts.ABI.empty() && !Target->setABI(Opts.ABI)) { 4491 Diags.Report(diag::err_target_unknown_abi) << Opts.ABI; 4492 return 0; 4493 } 4494 4495 // Set the target C++ ABI. 4496 if (!Opts.CXXABI.empty() && !Target->setCXXABI(Opts.CXXABI)) { 4497 Diags.Report(diag::err_target_unknown_cxxabi) << Opts.CXXABI; 4498 return 0; 4499 } 4500 4501 // Compute the default target features, we need the target to handle this 4502 // because features may have dependencies on one another. 4503 llvm::StringMap<bool> Features; 4504 Target->getDefaultFeatures(Features); 4505 4506 // Apply the user specified deltas. 4507 // First the enables. 4508 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4509 ie = Opts.Features.end(); it != ie; ++it) { 4510 const char *Name = it->c_str(); 4511 4512 if (Name[0] != '+') 4513 continue; 4514 4515 // Apply the feature via the target. 4516 if (!Target->setFeatureEnabled(Features, Name + 1, true)) { 4517 Diags.Report(diag::err_target_invalid_feature) << Name; 4518 return 0; 4519 } 4520 } 4521 4522 // Then the disables. 4523 for (std::vector<std::string>::const_iterator it = Opts.Features.begin(), 4524 ie = Opts.Features.end(); it != ie; ++it) { 4525 const char *Name = it->c_str(); 4526 4527 if (Name[0] == '+') 4528 continue; 4529 4530 // Apply the feature via the target. 4531 if (Name[0] != '-' || 4532 !Target->setFeatureEnabled(Features, Name + 1, false)) { 4533 Diags.Report(diag::err_target_invalid_feature) << Name; 4534 return 0; 4535 } 4536 } 4537 4538 // Add the features to the compile options. 4539 // 4540 // FIXME: If we are completely confident that we have the right set, we only 4541 // need to pass the minuses. 4542 Opts.Features.clear(); 4543 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 4544 ie = Features.end(); it != ie; ++it) 4545 Opts.Features.push_back((it->second ? "+" : "-") + it->first().str()); 4546 Target->HandleTargetFeatures(Opts.Features); 4547 4548 return Target.take(); 4549 } 4550