1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 121 // AddressSanitizer doesn't play well with source fortification, which is on 122 // by default on Darwin. 123 if (Opts.Sanitize.has(SanitizerKind::Address)) 124 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 125 126 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 127 if (!Opts.ObjC1) { 128 // __weak is always defined, for use in blocks and with objc pointers. 129 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 130 Builder.defineMacro("__strong", ""); 131 Builder.defineMacro("__unsafe_unretained", ""); 132 } 133 134 if (Opts.Static) 135 Builder.defineMacro("__STATIC__"); 136 else 137 Builder.defineMacro("__DYNAMIC__"); 138 139 if (Opts.POSIXThreads) 140 Builder.defineMacro("_REENTRANT"); 141 142 // Get the platform type and version number from the triple. 143 unsigned Maj, Min, Rev; 144 if (Triple.isMacOSX()) { 145 Triple.getMacOSXVersion(Maj, Min, Rev); 146 PlatformName = "macos"; 147 } else { 148 Triple.getOSVersion(Maj, Min, Rev); 149 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 150 } 151 152 // If -target arch-pc-win32-macho option specified, we're 153 // generating code for Win32 ABI. No need to emit 154 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 155 if (PlatformName == "win32") { 156 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 157 return; 158 } 159 160 // Set the appropriate OS version define. 161 if (Triple.isiOS()) { 162 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 163 char Str[7]; 164 if (Maj < 10) { 165 Str[0] = '0' + Maj; 166 Str[1] = '0' + (Min / 10); 167 Str[2] = '0' + (Min % 10); 168 Str[3] = '0' + (Rev / 10); 169 Str[4] = '0' + (Rev % 10); 170 Str[5] = '\0'; 171 } else { 172 // Handle versions >= 10. 173 Str[0] = '0' + (Maj / 10); 174 Str[1] = '0' + (Maj % 10); 175 Str[2] = '0' + (Min / 10); 176 Str[3] = '0' + (Min % 10); 177 Str[4] = '0' + (Rev / 10); 178 Str[5] = '0' + (Rev % 10); 179 Str[6] = '\0'; 180 } 181 if (Triple.isTvOS()) 182 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 183 else 184 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 185 Str); 186 187 } else if (Triple.isWatchOS()) { 188 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 189 char Str[6]; 190 Str[0] = '0' + Maj; 191 Str[1] = '0' + (Min / 10); 192 Str[2] = '0' + (Min % 10); 193 Str[3] = '0' + (Rev / 10); 194 Str[4] = '0' + (Rev % 10); 195 Str[5] = '\0'; 196 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 197 } else if (Triple.isMacOSX()) { 198 // Note that the Driver allows versions which aren't representable in the 199 // define (because we only get a single digit for the minor and micro 200 // revision numbers). So, we limit them to the maximum representable 201 // version. 202 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 203 char Str[7]; 204 if (Maj < 10 || (Maj == 10 && Min < 10)) { 205 Str[0] = '0' + (Maj / 10); 206 Str[1] = '0' + (Maj % 10); 207 Str[2] = '0' + std::min(Min, 9U); 208 Str[3] = '0' + std::min(Rev, 9U); 209 Str[4] = '\0'; 210 } else { 211 // Handle versions > 10.9. 212 Str[0] = '0' + (Maj / 10); 213 Str[1] = '0' + (Maj % 10); 214 Str[2] = '0' + (Min / 10); 215 Str[3] = '0' + (Min % 10); 216 Str[4] = '0' + (Rev / 10); 217 Str[5] = '0' + (Rev % 10); 218 Str[6] = '\0'; 219 } 220 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 221 } 222 223 // Tell users about the kernel if there is one. 224 if (Triple.isOSDarwin()) 225 Builder.defineMacro("__MACH__"); 226 227 // The Watch ABI uses Dwarf EH. 228 if(Triple.isWatchABI()) 229 Builder.defineMacro("__ARM_DWARF_EH__"); 230 231 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 232 } 233 234 template<typename Target> 235 class DarwinTargetInfo : public OSTargetInfo<Target> { 236 protected: 237 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 238 MacroBuilder &Builder) const override { 239 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 240 this->PlatformMinVersion); 241 } 242 243 public: 244 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 245 : OSTargetInfo<Target>(Triple, Opts) { 246 // By default, no TLS, and we whitelist permitted architecture/OS 247 // combinations. 248 this->TLSSupported = false; 249 250 if (Triple.isMacOSX()) 251 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 252 else if (Triple.isiOS()) { 253 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 254 if (Triple.getArch() == llvm::Triple::x86_64 || 255 Triple.getArch() == llvm::Triple::aarch64) 256 this->TLSSupported = !Triple.isOSVersionLT(8); 257 else if (Triple.getArch() == llvm::Triple::x86 || 258 Triple.getArch() == llvm::Triple::arm || 259 Triple.getArch() == llvm::Triple::thumb) 260 this->TLSSupported = !Triple.isOSVersionLT(9); 261 } else if (Triple.isWatchOS()) 262 this->TLSSupported = !Triple.isOSVersionLT(2); 263 264 this->MCountName = "\01mcount"; 265 } 266 267 std::string isValidSectionSpecifier(StringRef SR) const override { 268 // Let MCSectionMachO validate this. 269 StringRef Segment, Section; 270 unsigned TAA, StubSize; 271 bool HasTAA; 272 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 273 TAA, HasTAA, StubSize); 274 } 275 276 const char *getStaticInitSectionSpecifier() const override { 277 // FIXME: We should return 0 when building kexts. 278 return "__TEXT,__StaticInit,regular,pure_instructions"; 279 } 280 281 /// Darwin does not support protected visibility. Darwin's "default" 282 /// is very similar to ELF's "protected"; Darwin requires a "weak" 283 /// attribute on declarations that can be dynamically replaced. 284 bool hasProtectedVisibility() const override { 285 return false; 286 } 287 288 unsigned getExnObjectAlignment() const override { 289 // The alignment of an exception object is 8-bytes for darwin since 290 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 291 // and therefore doesn't guarantee 16-byte alignment. 292 return 64; 293 } 294 }; 295 296 297 // DragonFlyBSD Target 298 template<typename Target> 299 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 300 protected: 301 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 302 MacroBuilder &Builder) const override { 303 // DragonFly defines; list based off of gcc output 304 Builder.defineMacro("__DragonFly__"); 305 Builder.defineMacro("__DragonFly_cc_version", "100001"); 306 Builder.defineMacro("__ELF__"); 307 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 308 Builder.defineMacro("__tune_i386__"); 309 DefineStd(Builder, "unix", Opts); 310 } 311 public: 312 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 313 : OSTargetInfo<Target>(Triple, Opts) { 314 switch (Triple.getArch()) { 315 default: 316 case llvm::Triple::x86: 317 case llvm::Triple::x86_64: 318 this->MCountName = ".mcount"; 319 break; 320 } 321 } 322 }; 323 324 #ifndef FREEBSD_CC_VERSION 325 #define FREEBSD_CC_VERSION 0U 326 #endif 327 328 // FreeBSD Target 329 template<typename Target> 330 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 331 protected: 332 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 333 MacroBuilder &Builder) const override { 334 // FreeBSD defines; list based off of gcc output 335 336 unsigned Release = Triple.getOSMajorVersion(); 337 if (Release == 0U) 338 Release = 8U; 339 unsigned CCVersion = FREEBSD_CC_VERSION; 340 if (CCVersion == 0U) 341 CCVersion = Release * 100000U + 1U; 342 343 Builder.defineMacro("__FreeBSD__", Twine(Release)); 344 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 345 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 346 DefineStd(Builder, "unix", Opts); 347 Builder.defineMacro("__ELF__"); 348 349 // On FreeBSD, wchar_t contains the number of the code point as 350 // used by the character set of the locale. These character sets are 351 // not necessarily a superset of ASCII. 352 // 353 // FIXME: This is wrong; the macro refers to the numerical values 354 // of wchar_t *literals*, which are not locale-dependent. However, 355 // FreeBSD systems apparently depend on us getting this wrong, and 356 // setting this to 1 is conforming even if all the basic source 357 // character literals have the same encoding as char and wchar_t. 358 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 359 } 360 public: 361 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 362 : OSTargetInfo<Target>(Triple, Opts) { 363 switch (Triple.getArch()) { 364 default: 365 case llvm::Triple::x86: 366 case llvm::Triple::x86_64: 367 this->MCountName = ".mcount"; 368 break; 369 case llvm::Triple::mips: 370 case llvm::Triple::mipsel: 371 case llvm::Triple::ppc: 372 case llvm::Triple::ppc64: 373 case llvm::Triple::ppc64le: 374 this->MCountName = "_mcount"; 375 break; 376 case llvm::Triple::arm: 377 this->MCountName = "__mcount"; 378 break; 379 } 380 } 381 }; 382 383 // GNU/kFreeBSD Target 384 template<typename Target> 385 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 386 protected: 387 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 388 MacroBuilder &Builder) const override { 389 // GNU/kFreeBSD defines; list based off of gcc output 390 391 DefineStd(Builder, "unix", Opts); 392 Builder.defineMacro("__FreeBSD_kernel__"); 393 Builder.defineMacro("__GLIBC__"); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 402 : OSTargetInfo<Target>(Triple, Opts) {} 403 }; 404 405 // Haiku Target 406 template<typename Target> 407 class HaikuTargetInfo : public OSTargetInfo<Target> { 408 protected: 409 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 410 MacroBuilder &Builder) const override { 411 // Haiku defines; list based off of gcc output 412 Builder.defineMacro("__HAIKU__"); 413 Builder.defineMacro("__ELF__"); 414 DefineStd(Builder, "unix", Opts); 415 } 416 public: 417 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 418 : OSTargetInfo<Target>(Triple, Opts) { 419 this->SizeType = TargetInfo::UnsignedLong; 420 this->IntPtrType = TargetInfo::SignedLong; 421 this->PtrDiffType = TargetInfo::SignedLong; 422 this->ProcessIDType = TargetInfo::SignedLong; 423 this->TLSSupported = false; 424 425 } 426 }; 427 428 // Minix Target 429 template<typename Target> 430 class MinixTargetInfo : public OSTargetInfo<Target> { 431 protected: 432 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 433 MacroBuilder &Builder) const override { 434 // Minix defines 435 436 Builder.defineMacro("__minix", "3"); 437 Builder.defineMacro("_EM_WSIZE", "4"); 438 Builder.defineMacro("_EM_PSIZE", "4"); 439 Builder.defineMacro("_EM_SSIZE", "2"); 440 Builder.defineMacro("_EM_LSIZE", "4"); 441 Builder.defineMacro("_EM_FSIZE", "4"); 442 Builder.defineMacro("_EM_DSIZE", "8"); 443 Builder.defineMacro("__ELF__"); 444 DefineStd(Builder, "unix", Opts); 445 } 446 public: 447 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 448 : OSTargetInfo<Target>(Triple, Opts) {} 449 }; 450 451 // Linux target 452 template<typename Target> 453 class LinuxTargetInfo : public OSTargetInfo<Target> { 454 protected: 455 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 456 MacroBuilder &Builder) const override { 457 // Linux defines; list based off of gcc output 458 DefineStd(Builder, "unix", Opts); 459 DefineStd(Builder, "linux", Opts); 460 Builder.defineMacro("__gnu_linux__"); 461 Builder.defineMacro("__ELF__"); 462 if (Triple.isAndroid()) { 463 Builder.defineMacro("__ANDROID__", "1"); 464 unsigned Maj, Min, Rev; 465 Triple.getEnvironmentVersion(Maj, Min, Rev); 466 this->PlatformName = "android"; 467 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 468 } 469 if (Opts.POSIXThreads) 470 Builder.defineMacro("_REENTRANT"); 471 if (Opts.CPlusPlus) 472 Builder.defineMacro("_GNU_SOURCE"); 473 if (this->HasFloat128) 474 Builder.defineMacro("__FLOAT128__"); 475 } 476 public: 477 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 478 : OSTargetInfo<Target>(Triple, Opts) { 479 this->WIntType = TargetInfo::UnsignedInt; 480 481 switch (Triple.getArch()) { 482 default: 483 break; 484 case llvm::Triple::ppc: 485 case llvm::Triple::ppc64: 486 case llvm::Triple::ppc64le: 487 this->MCountName = "_mcount"; 488 break; 489 case llvm::Triple::x86: 490 case llvm::Triple::x86_64: 491 case llvm::Triple::systemz: 492 this->HasFloat128 = true; 493 break; 494 } 495 } 496 497 const char *getStaticInitSectionSpecifier() const override { 498 return ".text.startup"; 499 } 500 }; 501 502 // NetBSD Target 503 template<typename Target> 504 class NetBSDTargetInfo : public OSTargetInfo<Target> { 505 protected: 506 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 507 MacroBuilder &Builder) const override { 508 // NetBSD defines; list based off of gcc output 509 Builder.defineMacro("__NetBSD__"); 510 Builder.defineMacro("__unix__"); 511 Builder.defineMacro("__ELF__"); 512 if (Opts.POSIXThreads) 513 Builder.defineMacro("_POSIX_THREADS"); 514 515 switch (Triple.getArch()) { 516 default: 517 break; 518 case llvm::Triple::arm: 519 case llvm::Triple::armeb: 520 case llvm::Triple::thumb: 521 case llvm::Triple::thumbeb: 522 Builder.defineMacro("__ARM_DWARF_EH__"); 523 break; 524 } 525 } 526 public: 527 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 528 : OSTargetInfo<Target>(Triple, Opts) { 529 this->MCountName = "_mcount"; 530 } 531 }; 532 533 // OpenBSD Target 534 template<typename Target> 535 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 536 protected: 537 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 538 MacroBuilder &Builder) const override { 539 // OpenBSD defines; list based off of gcc output 540 541 Builder.defineMacro("__OpenBSD__"); 542 DefineStd(Builder, "unix", Opts); 543 Builder.defineMacro("__ELF__"); 544 if (Opts.POSIXThreads) 545 Builder.defineMacro("_REENTRANT"); 546 } 547 public: 548 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 549 : OSTargetInfo<Target>(Triple, Opts) { 550 this->TLSSupported = false; 551 552 switch (Triple.getArch()) { 553 default: 554 case llvm::Triple::x86: 555 case llvm::Triple::x86_64: 556 case llvm::Triple::arm: 557 case llvm::Triple::sparc: 558 this->MCountName = "__mcount"; 559 break; 560 case llvm::Triple::mips64: 561 case llvm::Triple::mips64el: 562 case llvm::Triple::ppc: 563 case llvm::Triple::sparcv9: 564 this->MCountName = "_mcount"; 565 break; 566 } 567 } 568 }; 569 570 // Bitrig Target 571 template<typename Target> 572 class BitrigTargetInfo : public OSTargetInfo<Target> { 573 protected: 574 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 575 MacroBuilder &Builder) const override { 576 // Bitrig defines; list based off of gcc output 577 578 Builder.defineMacro("__Bitrig__"); 579 DefineStd(Builder, "unix", Opts); 580 Builder.defineMacro("__ELF__"); 581 if (Opts.POSIXThreads) 582 Builder.defineMacro("_REENTRANT"); 583 584 switch (Triple.getArch()) { 585 default: 586 break; 587 case llvm::Triple::arm: 588 case llvm::Triple::armeb: 589 case llvm::Triple::thumb: 590 case llvm::Triple::thumbeb: 591 Builder.defineMacro("__ARM_DWARF_EH__"); 592 break; 593 } 594 } 595 public: 596 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 597 : OSTargetInfo<Target>(Triple, Opts) { 598 this->MCountName = "__mcount"; 599 } 600 }; 601 602 // PSP Target 603 template<typename Target> 604 class PSPTargetInfo : public OSTargetInfo<Target> { 605 protected: 606 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 607 MacroBuilder &Builder) const override { 608 // PSP defines; list based on the output of the pspdev gcc toolchain. 609 Builder.defineMacro("PSP"); 610 Builder.defineMacro("_PSP"); 611 Builder.defineMacro("__psp__"); 612 Builder.defineMacro("__ELF__"); 613 } 614 public: 615 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 616 }; 617 618 // PS3 PPU Target 619 template<typename Target> 620 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 621 protected: 622 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 623 MacroBuilder &Builder) const override { 624 // PS3 PPU defines. 625 Builder.defineMacro("__PPC__"); 626 Builder.defineMacro("__PPU__"); 627 Builder.defineMacro("__CELLOS_LV2__"); 628 Builder.defineMacro("__ELF__"); 629 Builder.defineMacro("__LP32__"); 630 Builder.defineMacro("_ARCH_PPC64"); 631 Builder.defineMacro("__powerpc64__"); 632 } 633 public: 634 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 635 : OSTargetInfo<Target>(Triple, Opts) { 636 this->LongWidth = this->LongAlign = 32; 637 this->PointerWidth = this->PointerAlign = 32; 638 this->IntMaxType = TargetInfo::SignedLongLong; 639 this->Int64Type = TargetInfo::SignedLongLong; 640 this->SizeType = TargetInfo::UnsignedInt; 641 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 642 } 643 }; 644 645 template <typename Target> 646 class PS4OSTargetInfo : public OSTargetInfo<Target> { 647 protected: 648 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 649 MacroBuilder &Builder) const override { 650 Builder.defineMacro("__FreeBSD__", "9"); 651 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 652 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 653 DefineStd(Builder, "unix", Opts); 654 Builder.defineMacro("__ELF__"); 655 Builder.defineMacro("__ORBIS__"); 656 } 657 public: 658 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 659 : OSTargetInfo<Target>(Triple, Opts) { 660 this->WCharType = this->UnsignedShort; 661 662 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 663 this->MaxTLSAlign = 256; 664 665 // On PS4, do not honor explicit bit field alignment, 666 // as in "__attribute__((aligned(2))) int b : 1;". 667 this->UseExplicitBitFieldAlignment = false; 668 669 switch (Triple.getArch()) { 670 default: 671 case llvm::Triple::x86_64: 672 this->MCountName = ".mcount"; 673 break; 674 } 675 } 676 }; 677 678 // Solaris target 679 template<typename Target> 680 class SolarisTargetInfo : public OSTargetInfo<Target> { 681 protected: 682 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 683 MacroBuilder &Builder) const override { 684 DefineStd(Builder, "sun", Opts); 685 DefineStd(Builder, "unix", Opts); 686 Builder.defineMacro("__ELF__"); 687 Builder.defineMacro("__svr4__"); 688 Builder.defineMacro("__SVR4"); 689 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 690 // newer, but to 500 for everything else. feature_test.h has a check to 691 // ensure that you are not using C99 with an old version of X/Open or C89 692 // with a new version. 693 if (Opts.C99) 694 Builder.defineMacro("_XOPEN_SOURCE", "600"); 695 else 696 Builder.defineMacro("_XOPEN_SOURCE", "500"); 697 if (Opts.CPlusPlus) 698 Builder.defineMacro("__C99FEATURES__"); 699 Builder.defineMacro("_LARGEFILE_SOURCE"); 700 Builder.defineMacro("_LARGEFILE64_SOURCE"); 701 Builder.defineMacro("__EXTENSIONS__"); 702 Builder.defineMacro("_REENTRANT"); 703 } 704 public: 705 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 706 : OSTargetInfo<Target>(Triple, Opts) { 707 this->WCharType = this->SignedInt; 708 // FIXME: WIntType should be SignedLong 709 } 710 }; 711 712 // Windows target 713 template<typename Target> 714 class WindowsTargetInfo : public OSTargetInfo<Target> { 715 protected: 716 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 717 MacroBuilder &Builder) const override { 718 Builder.defineMacro("_WIN32"); 719 } 720 void getVisualStudioDefines(const LangOptions &Opts, 721 MacroBuilder &Builder) const { 722 if (Opts.CPlusPlus) { 723 if (Opts.RTTIData) 724 Builder.defineMacro("_CPPRTTI"); 725 726 if (Opts.CXXExceptions) 727 Builder.defineMacro("_CPPUNWIND"); 728 } 729 730 if (Opts.Bool) 731 Builder.defineMacro("__BOOL_DEFINED"); 732 733 if (!Opts.CharIsSigned) 734 Builder.defineMacro("_CHAR_UNSIGNED"); 735 736 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 737 // but it works for now. 738 if (Opts.POSIXThreads) 739 Builder.defineMacro("_MT"); 740 741 if (Opts.MSCompatibilityVersion) { 742 Builder.defineMacro("_MSC_VER", 743 Twine(Opts.MSCompatibilityVersion / 100000)); 744 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 745 // FIXME We cannot encode the revision information into 32-bits 746 Builder.defineMacro("_MSC_BUILD", Twine(1)); 747 748 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 749 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 750 751 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 752 if (Opts.CPlusPlus1z) 753 Builder.defineMacro("_MSVC_LANG", "201403L"); 754 else if (Opts.CPlusPlus14) 755 Builder.defineMacro("_MSVC_LANG", "201402L"); 756 } 757 } 758 759 if (Opts.MicrosoftExt) { 760 Builder.defineMacro("_MSC_EXTENSIONS"); 761 762 if (Opts.CPlusPlus11) { 763 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 764 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 765 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 766 } 767 } 768 769 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 770 } 771 772 public: 773 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 774 : OSTargetInfo<Target>(Triple, Opts) {} 775 }; 776 777 template <typename Target> 778 class NaClTargetInfo : public OSTargetInfo<Target> { 779 protected: 780 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 781 MacroBuilder &Builder) const override { 782 if (Opts.POSIXThreads) 783 Builder.defineMacro("_REENTRANT"); 784 if (Opts.CPlusPlus) 785 Builder.defineMacro("_GNU_SOURCE"); 786 787 DefineStd(Builder, "unix", Opts); 788 Builder.defineMacro("__ELF__"); 789 Builder.defineMacro("__native_client__"); 790 } 791 792 public: 793 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 794 : OSTargetInfo<Target>(Triple, Opts) { 795 this->LongAlign = 32; 796 this->LongWidth = 32; 797 this->PointerAlign = 32; 798 this->PointerWidth = 32; 799 this->IntMaxType = TargetInfo::SignedLongLong; 800 this->Int64Type = TargetInfo::SignedLongLong; 801 this->DoubleAlign = 64; 802 this->LongDoubleWidth = 64; 803 this->LongDoubleAlign = 64; 804 this->LongLongWidth = 64; 805 this->LongLongAlign = 64; 806 this->SizeType = TargetInfo::UnsignedInt; 807 this->PtrDiffType = TargetInfo::SignedInt; 808 this->IntPtrType = TargetInfo::SignedInt; 809 // RegParmMax is inherited from the underlying architecture. 810 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 811 if (Triple.getArch() == llvm::Triple::arm) { 812 // Handled in ARM's setABI(). 813 } else if (Triple.getArch() == llvm::Triple::x86) { 814 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 815 } else if (Triple.getArch() == llvm::Triple::x86_64) { 816 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 817 } else if (Triple.getArch() == llvm::Triple::mipsel) { 818 // Handled on mips' setDataLayout. 819 } else { 820 assert(Triple.getArch() == llvm::Triple::le32); 821 this->resetDataLayout("e-p:32:32-i64:64"); 822 } 823 } 824 }; 825 826 // Fuchsia Target 827 template<typename Target> 828 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 829 protected: 830 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 831 MacroBuilder &Builder) const override { 832 Builder.defineMacro("__Fuchsia__"); 833 Builder.defineMacro("__ELF__"); 834 if (Opts.POSIXThreads) 835 Builder.defineMacro("_REENTRANT"); 836 // Required by the libc++ locale support. 837 if (Opts.CPlusPlus) 838 Builder.defineMacro("_GNU_SOURCE"); 839 } 840 public: 841 FuchsiaTargetInfo(const llvm::Triple &Triple, 842 const TargetOptions &Opts) 843 : OSTargetInfo<Target>(Triple, Opts) { 844 this->MCountName = "__mcount"; 845 } 846 }; 847 848 // WebAssembly target 849 template <typename Target> 850 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 851 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 852 MacroBuilder &Builder) const final { 853 // A common platform macro. 854 if (Opts.POSIXThreads) 855 Builder.defineMacro("_REENTRANT"); 856 // Follow g++ convention and predefine _GNU_SOURCE for C++. 857 if (Opts.CPlusPlus) 858 Builder.defineMacro("_GNU_SOURCE"); 859 } 860 861 // As an optimization, group static init code together in a section. 862 const char *getStaticInitSectionSpecifier() const final { 863 return ".text.__startup"; 864 } 865 866 public: 867 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 868 const TargetOptions &Opts) 869 : OSTargetInfo<Target>(Triple, Opts) { 870 this->MCountName = "__mcount"; 871 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 872 } 873 }; 874 875 //===----------------------------------------------------------------------===// 876 // Specific target implementations. 877 //===----------------------------------------------------------------------===// 878 879 // PPC abstract base class 880 class PPCTargetInfo : public TargetInfo { 881 static const Builtin::Info BuiltinInfo[]; 882 static const char * const GCCRegNames[]; 883 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 884 std::string CPU; 885 886 // Target cpu features. 887 bool HasVSX; 888 bool HasP8Vector; 889 bool HasP8Crypto; 890 bool HasDirectMove; 891 bool HasQPX; 892 bool HasHTM; 893 bool HasBPERMD; 894 bool HasExtDiv; 895 bool HasP9Vector; 896 897 protected: 898 std::string ABI; 899 900 public: 901 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 902 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 903 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 904 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 905 SimdDefaultAlign = 128; 906 LongDoubleWidth = LongDoubleAlign = 128; 907 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 908 } 909 910 /// \brief Flags for architecture specific defines. 911 typedef enum { 912 ArchDefineNone = 0, 913 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 914 ArchDefinePpcgr = 1 << 1, 915 ArchDefinePpcsq = 1 << 2, 916 ArchDefine440 = 1 << 3, 917 ArchDefine603 = 1 << 4, 918 ArchDefine604 = 1 << 5, 919 ArchDefinePwr4 = 1 << 6, 920 ArchDefinePwr5 = 1 << 7, 921 ArchDefinePwr5x = 1 << 8, 922 ArchDefinePwr6 = 1 << 9, 923 ArchDefinePwr6x = 1 << 10, 924 ArchDefinePwr7 = 1 << 11, 925 ArchDefinePwr8 = 1 << 12, 926 ArchDefinePwr9 = 1 << 13, 927 ArchDefineA2 = 1 << 14, 928 ArchDefineA2q = 1 << 15 929 } ArchDefineTypes; 930 931 // Note: GCC recognizes the following additional cpus: 932 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 933 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 934 // titan, rs64. 935 bool setCPU(const std::string &Name) override { 936 bool CPUKnown = llvm::StringSwitch<bool>(Name) 937 .Case("generic", true) 938 .Case("440", true) 939 .Case("450", true) 940 .Case("601", true) 941 .Case("602", true) 942 .Case("603", true) 943 .Case("603e", true) 944 .Case("603ev", true) 945 .Case("604", true) 946 .Case("604e", true) 947 .Case("620", true) 948 .Case("630", true) 949 .Case("g3", true) 950 .Case("7400", true) 951 .Case("g4", true) 952 .Case("7450", true) 953 .Case("g4+", true) 954 .Case("750", true) 955 .Case("970", true) 956 .Case("g5", true) 957 .Case("a2", true) 958 .Case("a2q", true) 959 .Case("e500mc", true) 960 .Case("e5500", true) 961 .Case("power3", true) 962 .Case("pwr3", true) 963 .Case("power4", true) 964 .Case("pwr4", true) 965 .Case("power5", true) 966 .Case("pwr5", true) 967 .Case("power5x", true) 968 .Case("pwr5x", true) 969 .Case("power6", true) 970 .Case("pwr6", true) 971 .Case("power6x", true) 972 .Case("pwr6x", true) 973 .Case("power7", true) 974 .Case("pwr7", true) 975 .Case("power8", true) 976 .Case("pwr8", true) 977 .Case("power9", true) 978 .Case("pwr9", true) 979 .Case("powerpc", true) 980 .Case("ppc", true) 981 .Case("powerpc64", true) 982 .Case("ppc64", true) 983 .Case("powerpc64le", true) 984 .Case("ppc64le", true) 985 .Default(false); 986 987 if (CPUKnown) 988 CPU = Name; 989 990 return CPUKnown; 991 } 992 993 994 StringRef getABI() const override { return ABI; } 995 996 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 997 return llvm::makeArrayRef(BuiltinInfo, 998 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 999 } 1000 1001 bool isCLZForZeroUndef() const override { return false; } 1002 1003 void getTargetDefines(const LangOptions &Opts, 1004 MacroBuilder &Builder) const override; 1005 1006 bool 1007 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1008 StringRef CPU, 1009 const std::vector<std::string> &FeaturesVec) const override; 1010 1011 bool handleTargetFeatures(std::vector<std::string> &Features, 1012 DiagnosticsEngine &Diags) override; 1013 bool hasFeature(StringRef Feature) const override; 1014 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1015 bool Enabled) const override; 1016 1017 ArrayRef<const char *> getGCCRegNames() const override; 1018 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1019 bool validateAsmConstraint(const char *&Name, 1020 TargetInfo::ConstraintInfo &Info) const override { 1021 switch (*Name) { 1022 default: return false; 1023 case 'O': // Zero 1024 break; 1025 case 'b': // Base register 1026 case 'f': // Floating point register 1027 Info.setAllowsRegister(); 1028 break; 1029 // FIXME: The following are added to allow parsing. 1030 // I just took a guess at what the actions should be. 1031 // Also, is more specific checking needed? I.e. specific registers? 1032 case 'd': // Floating point register (containing 64-bit value) 1033 case 'v': // Altivec vector register 1034 Info.setAllowsRegister(); 1035 break; 1036 case 'w': 1037 switch (Name[1]) { 1038 case 'd':// VSX vector register to hold vector double data 1039 case 'f':// VSX vector register to hold vector float data 1040 case 's':// VSX vector register to hold scalar float data 1041 case 'a':// Any VSX register 1042 case 'c':// An individual CR bit 1043 break; 1044 default: 1045 return false; 1046 } 1047 Info.setAllowsRegister(); 1048 Name++; // Skip over 'w'. 1049 break; 1050 case 'h': // `MQ', `CTR', or `LINK' register 1051 case 'q': // `MQ' register 1052 case 'c': // `CTR' register 1053 case 'l': // `LINK' register 1054 case 'x': // `CR' register (condition register) number 0 1055 case 'y': // `CR' register (condition register) 1056 case 'z': // `XER[CA]' carry bit (part of the XER register) 1057 Info.setAllowsRegister(); 1058 break; 1059 case 'I': // Signed 16-bit constant 1060 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1061 // (use `L' instead for SImode constants) 1062 case 'K': // Unsigned 16-bit constant 1063 case 'L': // Signed 16-bit constant shifted left 16 bits 1064 case 'M': // Constant larger than 31 1065 case 'N': // Exact power of 2 1066 case 'P': // Constant whose negation is a signed 16-bit constant 1067 case 'G': // Floating point constant that can be loaded into a 1068 // register with one instruction per word 1069 case 'H': // Integer/Floating point constant that can be loaded 1070 // into a register using three instructions 1071 break; 1072 case 'm': // Memory operand. Note that on PowerPC targets, m can 1073 // include addresses that update the base register. It 1074 // is therefore only safe to use `m' in an asm statement 1075 // if that asm statement accesses the operand exactly once. 1076 // The asm statement must also use `%U<opno>' as a 1077 // placeholder for the "update" flag in the corresponding 1078 // load or store instruction. For example: 1079 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1080 // is correct but: 1081 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1082 // is not. Use es rather than m if you don't want the base 1083 // register to be updated. 1084 case 'e': 1085 if (Name[1] != 's') 1086 return false; 1087 // es: A "stable" memory operand; that is, one which does not 1088 // include any automodification of the base register. Unlike 1089 // `m', this constraint can be used in asm statements that 1090 // might access the operand several times, or that might not 1091 // access it at all. 1092 Info.setAllowsMemory(); 1093 Name++; // Skip over 'e'. 1094 break; 1095 case 'Q': // Memory operand that is an offset from a register (it is 1096 // usually better to use `m' or `es' in asm statements) 1097 case 'Z': // Memory operand that is an indexed or indirect from a 1098 // register (it is usually better to use `m' or `es' in 1099 // asm statements) 1100 Info.setAllowsMemory(); 1101 Info.setAllowsRegister(); 1102 break; 1103 case 'R': // AIX TOC entry 1104 case 'a': // Address operand that is an indexed or indirect from a 1105 // register (`p' is preferable for asm statements) 1106 case 'S': // Constant suitable as a 64-bit mask operand 1107 case 'T': // Constant suitable as a 32-bit mask operand 1108 case 'U': // System V Release 4 small data area reference 1109 case 't': // AND masks that can be performed by two rldic{l, r} 1110 // instructions 1111 case 'W': // Vector constant that does not require memory 1112 case 'j': // Vector constant that is all zeros. 1113 break; 1114 // End FIXME. 1115 } 1116 return true; 1117 } 1118 std::string convertConstraint(const char *&Constraint) const override { 1119 std::string R; 1120 switch (*Constraint) { 1121 case 'e': 1122 case 'w': 1123 // Two-character constraint; add "^" hint for later parsing. 1124 R = std::string("^") + std::string(Constraint, 2); 1125 Constraint++; 1126 break; 1127 default: 1128 return TargetInfo::convertConstraint(Constraint); 1129 } 1130 return R; 1131 } 1132 const char *getClobbers() const override { 1133 return ""; 1134 } 1135 int getEHDataRegisterNumber(unsigned RegNo) const override { 1136 if (RegNo == 0) return 3; 1137 if (RegNo == 1) return 4; 1138 return -1; 1139 } 1140 1141 bool hasSjLjLowering() const override { 1142 return true; 1143 } 1144 1145 bool useFloat128ManglingForLongDouble() const override { 1146 return LongDoubleWidth == 128 && 1147 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1148 getTriple().isOSBinFormatELF(); 1149 } 1150 }; 1151 1152 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1153 #define BUILTIN(ID, TYPE, ATTRS) \ 1154 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1155 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1156 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1157 #include "clang/Basic/BuiltinsPPC.def" 1158 }; 1159 1160 /// handleTargetFeatures - Perform initialization based on the user 1161 /// configured set of features. 1162 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1163 DiagnosticsEngine &Diags) { 1164 for (const auto &Feature : Features) { 1165 if (Feature == "+vsx") { 1166 HasVSX = true; 1167 } else if (Feature == "+bpermd") { 1168 HasBPERMD = true; 1169 } else if (Feature == "+extdiv") { 1170 HasExtDiv = true; 1171 } else if (Feature == "+power8-vector") { 1172 HasP8Vector = true; 1173 } else if (Feature == "+crypto") { 1174 HasP8Crypto = true; 1175 } else if (Feature == "+direct-move") { 1176 HasDirectMove = true; 1177 } else if (Feature == "+qpx") { 1178 HasQPX = true; 1179 } else if (Feature == "+htm") { 1180 HasHTM = true; 1181 } else if (Feature == "+float128") { 1182 HasFloat128 = true; 1183 } else if (Feature == "+power9-vector") { 1184 HasP9Vector = true; 1185 } 1186 // TODO: Finish this list and add an assert that we've handled them 1187 // all. 1188 } 1189 1190 return true; 1191 } 1192 1193 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1194 /// #defines that are not tied to a specific subtarget. 1195 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1196 MacroBuilder &Builder) const { 1197 // Target identification. 1198 Builder.defineMacro("__ppc__"); 1199 Builder.defineMacro("__PPC__"); 1200 Builder.defineMacro("_ARCH_PPC"); 1201 Builder.defineMacro("__powerpc__"); 1202 Builder.defineMacro("__POWERPC__"); 1203 if (PointerWidth == 64) { 1204 Builder.defineMacro("_ARCH_PPC64"); 1205 Builder.defineMacro("__powerpc64__"); 1206 Builder.defineMacro("__ppc64__"); 1207 Builder.defineMacro("__PPC64__"); 1208 } 1209 1210 // Target properties. 1211 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1212 Builder.defineMacro("_LITTLE_ENDIAN"); 1213 } else { 1214 if (getTriple().getOS() != llvm::Triple::NetBSD && 1215 getTriple().getOS() != llvm::Triple::OpenBSD) 1216 Builder.defineMacro("_BIG_ENDIAN"); 1217 } 1218 1219 // ABI options. 1220 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1221 Builder.defineMacro("_CALL_ELF", "1"); 1222 if (ABI == "elfv2") 1223 Builder.defineMacro("_CALL_ELF", "2"); 1224 1225 // Subtarget options. 1226 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1227 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1228 1229 // FIXME: Should be controlled by command line option. 1230 if (LongDoubleWidth == 128) 1231 Builder.defineMacro("__LONG_DOUBLE_128__"); 1232 1233 if (Opts.AltiVec) { 1234 Builder.defineMacro("__VEC__", "10206"); 1235 Builder.defineMacro("__ALTIVEC__"); 1236 } 1237 1238 // CPU identification. 1239 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1240 .Case("440", ArchDefineName) 1241 .Case("450", ArchDefineName | ArchDefine440) 1242 .Case("601", ArchDefineName) 1243 .Case("602", ArchDefineName | ArchDefinePpcgr) 1244 .Case("603", ArchDefineName | ArchDefinePpcgr) 1245 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1246 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1247 .Case("604", ArchDefineName | ArchDefinePpcgr) 1248 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1249 .Case("620", ArchDefineName | ArchDefinePpcgr) 1250 .Case("630", ArchDefineName | ArchDefinePpcgr) 1251 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1252 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1253 .Case("750", ArchDefineName | ArchDefinePpcgr) 1254 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1255 | ArchDefinePpcsq) 1256 .Case("a2", ArchDefineA2) 1257 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1258 .Case("pwr3", ArchDefinePpcgr) 1259 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1260 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1261 | ArchDefinePpcsq) 1262 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1263 | ArchDefinePpcgr | ArchDefinePpcsq) 1264 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1265 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1266 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1267 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1268 | ArchDefinePpcsq) 1269 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1270 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1271 | ArchDefinePpcgr | ArchDefinePpcsq) 1272 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1273 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1274 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1275 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 1276 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1277 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1278 | ArchDefinePpcsq) 1279 .Case("power3", ArchDefinePpcgr) 1280 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1281 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1282 | ArchDefinePpcsq) 1283 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1284 | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1286 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1287 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1288 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1289 | ArchDefinePpcsq) 1290 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1291 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1292 | ArchDefinePpcgr | ArchDefinePpcsq) 1293 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1294 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1295 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1296 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 1297 | ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1298 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1299 | ArchDefinePpcsq) 1300 .Default(ArchDefineNone); 1301 1302 if (defs & ArchDefineName) 1303 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1304 if (defs & ArchDefinePpcgr) 1305 Builder.defineMacro("_ARCH_PPCGR"); 1306 if (defs & ArchDefinePpcsq) 1307 Builder.defineMacro("_ARCH_PPCSQ"); 1308 if (defs & ArchDefine440) 1309 Builder.defineMacro("_ARCH_440"); 1310 if (defs & ArchDefine603) 1311 Builder.defineMacro("_ARCH_603"); 1312 if (defs & ArchDefine604) 1313 Builder.defineMacro("_ARCH_604"); 1314 if (defs & ArchDefinePwr4) 1315 Builder.defineMacro("_ARCH_PWR4"); 1316 if (defs & ArchDefinePwr5) 1317 Builder.defineMacro("_ARCH_PWR5"); 1318 if (defs & ArchDefinePwr5x) 1319 Builder.defineMacro("_ARCH_PWR5X"); 1320 if (defs & ArchDefinePwr6) 1321 Builder.defineMacro("_ARCH_PWR6"); 1322 if (defs & ArchDefinePwr6x) 1323 Builder.defineMacro("_ARCH_PWR6X"); 1324 if (defs & ArchDefinePwr7) 1325 Builder.defineMacro("_ARCH_PWR7"); 1326 if (defs & ArchDefinePwr8) 1327 Builder.defineMacro("_ARCH_PWR8"); 1328 if (defs & ArchDefinePwr9) 1329 Builder.defineMacro("_ARCH_PWR9"); 1330 if (defs & ArchDefineA2) 1331 Builder.defineMacro("_ARCH_A2"); 1332 if (defs & ArchDefineA2q) { 1333 Builder.defineMacro("_ARCH_A2Q"); 1334 Builder.defineMacro("_ARCH_QP"); 1335 } 1336 1337 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1338 Builder.defineMacro("__bg__"); 1339 Builder.defineMacro("__THW_BLUEGENE__"); 1340 Builder.defineMacro("__bgq__"); 1341 Builder.defineMacro("__TOS_BGQ__"); 1342 } 1343 1344 if (HasVSX) 1345 Builder.defineMacro("__VSX__"); 1346 if (HasP8Vector) 1347 Builder.defineMacro("__POWER8_VECTOR__"); 1348 if (HasP8Crypto) 1349 Builder.defineMacro("__CRYPTO__"); 1350 if (HasHTM) 1351 Builder.defineMacro("__HTM__"); 1352 if (HasFloat128) 1353 Builder.defineMacro("__FLOAT128__"); 1354 if (HasP9Vector) 1355 Builder.defineMacro("__POWER9_VECTOR__"); 1356 1357 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1358 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1359 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1360 if (PointerWidth == 64) 1361 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1362 1363 // FIXME: The following are not yet generated here by Clang, but are 1364 // generated by GCC: 1365 // 1366 // _SOFT_FLOAT_ 1367 // __RECIP_PRECISION__ 1368 // __APPLE_ALTIVEC__ 1369 // __RECIP__ 1370 // __RECIPF__ 1371 // __RSQRTE__ 1372 // __RSQRTEF__ 1373 // _SOFT_DOUBLE_ 1374 // __NO_LWSYNC__ 1375 // __HAVE_BSWAP__ 1376 // __LONGDOUBLE128 1377 // __CMODEL_MEDIUM__ 1378 // __CMODEL_LARGE__ 1379 // _CALL_SYSV 1380 // _CALL_DARWIN 1381 // __NO_FPRS__ 1382 } 1383 1384 // Handle explicit options being passed to the compiler here: if we've 1385 // explicitly turned off vsx and turned on any of: 1386 // - power8-vector 1387 // - direct-move 1388 // - float128 1389 // - power9-vector 1390 // then go ahead and error since the customer has expressed an incompatible 1391 // set of options. 1392 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1393 const std::vector<std::string> &FeaturesVec) { 1394 1395 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1396 FeaturesVec.end()) { 1397 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1398 FeaturesVec.end()) { 1399 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1400 << "-mno-vsx"; 1401 return false; 1402 } 1403 1404 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1405 FeaturesVec.end()) { 1406 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1407 << "-mno-vsx"; 1408 return false; 1409 } 1410 1411 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1412 FeaturesVec.end()) { 1413 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1414 << "-mno-vsx"; 1415 return false; 1416 } 1417 1418 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1419 FeaturesVec.end()) { 1420 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1421 << "-mno-vsx"; 1422 return false; 1423 } 1424 } 1425 1426 return true; 1427 } 1428 1429 bool PPCTargetInfo::initFeatureMap( 1430 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1431 const std::vector<std::string> &FeaturesVec) const { 1432 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1433 .Case("7400", true) 1434 .Case("g4", true) 1435 .Case("7450", true) 1436 .Case("g4+", true) 1437 .Case("970", true) 1438 .Case("g5", true) 1439 .Case("pwr6", true) 1440 .Case("pwr7", true) 1441 .Case("pwr8", true) 1442 .Case("pwr9", true) 1443 .Case("ppc64", true) 1444 .Case("ppc64le", true) 1445 .Default(false); 1446 1447 Features["qpx"] = (CPU == "a2q"); 1448 Features["power9-vector"] = (CPU == "pwr9"); 1449 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1450 .Case("ppc64le", true) 1451 .Case("pwr9", true) 1452 .Case("pwr8", true) 1453 .Default(false); 1454 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1455 .Case("ppc64le", true) 1456 .Case("pwr9", true) 1457 .Case("pwr8", true) 1458 .Default(false); 1459 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1460 .Case("ppc64le", true) 1461 .Case("pwr9", true) 1462 .Case("pwr8", true) 1463 .Case("pwr7", true) 1464 .Default(false); 1465 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1466 .Case("ppc64le", true) 1467 .Case("pwr9", true) 1468 .Case("pwr8", true) 1469 .Case("pwr7", true) 1470 .Default(false); 1471 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("ppc64le", true) 1473 .Case("pwr9", true) 1474 .Case("pwr8", true) 1475 .Default(false); 1476 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1477 .Case("ppc64le", true) 1478 .Case("pwr9", true) 1479 .Case("pwr8", true) 1480 .Case("pwr7", true) 1481 .Default(false); 1482 1483 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1484 return false; 1485 1486 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1487 } 1488 1489 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1490 return llvm::StringSwitch<bool>(Feature) 1491 .Case("powerpc", true) 1492 .Case("vsx", HasVSX) 1493 .Case("power8-vector", HasP8Vector) 1494 .Case("crypto", HasP8Crypto) 1495 .Case("direct-move", HasDirectMove) 1496 .Case("qpx", HasQPX) 1497 .Case("htm", HasHTM) 1498 .Case("bpermd", HasBPERMD) 1499 .Case("extdiv", HasExtDiv) 1500 .Case("float128", HasFloat128) 1501 .Case("power9-vector", HasP9Vector) 1502 .Default(false); 1503 } 1504 1505 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1506 StringRef Name, bool Enabled) const { 1507 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1508 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1509 // incompatible options. 1510 if (Enabled) { 1511 if (Name == "direct-move" || 1512 Name == "power8-vector" || 1513 Name == "float128" || 1514 Name == "power9-vector") { 1515 // power9-vector is really a superset of power8-vector so encode that. 1516 Features[Name] = Features["vsx"] = true; 1517 if (Name == "power9-vector") 1518 Features["power8-vector"] = true; 1519 } else { 1520 Features[Name] = true; 1521 } 1522 } else { 1523 if (Name == "vsx") { 1524 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1525 Features["float128"] = Features["power9-vector"] = false; 1526 } else { 1527 Features[Name] = false; 1528 } 1529 } 1530 } 1531 1532 const char * const PPCTargetInfo::GCCRegNames[] = { 1533 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1534 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1535 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1536 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1537 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1538 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1539 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1540 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1541 "mq", "lr", "ctr", "ap", 1542 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1543 "xer", 1544 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1545 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1546 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1547 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1548 "vrsave", "vscr", 1549 "spe_acc", "spefscr", 1550 "sfp" 1551 }; 1552 1553 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1554 return llvm::makeArrayRef(GCCRegNames); 1555 } 1556 1557 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1558 // While some of these aliases do map to different registers 1559 // they still share the same register name. 1560 { { "0" }, "r0" }, 1561 { { "1"}, "r1" }, 1562 { { "2" }, "r2" }, 1563 { { "3" }, "r3" }, 1564 { { "4" }, "r4" }, 1565 { { "5" }, "r5" }, 1566 { { "6" }, "r6" }, 1567 { { "7" }, "r7" }, 1568 { { "8" }, "r8" }, 1569 { { "9" }, "r9" }, 1570 { { "10" }, "r10" }, 1571 { { "11" }, "r11" }, 1572 { { "12" }, "r12" }, 1573 { { "13" }, "r13" }, 1574 { { "14" }, "r14" }, 1575 { { "15" }, "r15" }, 1576 { { "16" }, "r16" }, 1577 { { "17" }, "r17" }, 1578 { { "18" }, "r18" }, 1579 { { "19" }, "r19" }, 1580 { { "20" }, "r20" }, 1581 { { "21" }, "r21" }, 1582 { { "22" }, "r22" }, 1583 { { "23" }, "r23" }, 1584 { { "24" }, "r24" }, 1585 { { "25" }, "r25" }, 1586 { { "26" }, "r26" }, 1587 { { "27" }, "r27" }, 1588 { { "28" }, "r28" }, 1589 { { "29" }, "r29" }, 1590 { { "30" }, "r30" }, 1591 { { "31" }, "r31" }, 1592 { { "fr0" }, "f0" }, 1593 { { "fr1" }, "f1" }, 1594 { { "fr2" }, "f2" }, 1595 { { "fr3" }, "f3" }, 1596 { { "fr4" }, "f4" }, 1597 { { "fr5" }, "f5" }, 1598 { { "fr6" }, "f6" }, 1599 { { "fr7" }, "f7" }, 1600 { { "fr8" }, "f8" }, 1601 { { "fr9" }, "f9" }, 1602 { { "fr10" }, "f10" }, 1603 { { "fr11" }, "f11" }, 1604 { { "fr12" }, "f12" }, 1605 { { "fr13" }, "f13" }, 1606 { { "fr14" }, "f14" }, 1607 { { "fr15" }, "f15" }, 1608 { { "fr16" }, "f16" }, 1609 { { "fr17" }, "f17" }, 1610 { { "fr18" }, "f18" }, 1611 { { "fr19" }, "f19" }, 1612 { { "fr20" }, "f20" }, 1613 { { "fr21" }, "f21" }, 1614 { { "fr22" }, "f22" }, 1615 { { "fr23" }, "f23" }, 1616 { { "fr24" }, "f24" }, 1617 { { "fr25" }, "f25" }, 1618 { { "fr26" }, "f26" }, 1619 { { "fr27" }, "f27" }, 1620 { { "fr28" }, "f28" }, 1621 { { "fr29" }, "f29" }, 1622 { { "fr30" }, "f30" }, 1623 { { "fr31" }, "f31" }, 1624 { { "cc" }, "cr0" }, 1625 }; 1626 1627 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1628 return llvm::makeArrayRef(GCCRegAliases); 1629 } 1630 1631 class PPC32TargetInfo : public PPCTargetInfo { 1632 public: 1633 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1634 : PPCTargetInfo(Triple, Opts) { 1635 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1636 1637 switch (getTriple().getOS()) { 1638 case llvm::Triple::Linux: 1639 case llvm::Triple::FreeBSD: 1640 case llvm::Triple::NetBSD: 1641 SizeType = UnsignedInt; 1642 PtrDiffType = SignedInt; 1643 IntPtrType = SignedInt; 1644 break; 1645 default: 1646 break; 1647 } 1648 1649 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1650 LongDoubleWidth = LongDoubleAlign = 64; 1651 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1652 } 1653 1654 // PPC32 supports atomics up to 4 bytes. 1655 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1656 } 1657 1658 BuiltinVaListKind getBuiltinVaListKind() const override { 1659 // This is the ELF definition, and is overridden by the Darwin sub-target 1660 return TargetInfo::PowerABIBuiltinVaList; 1661 } 1662 }; 1663 1664 // Note: ABI differences may eventually require us to have a separate 1665 // TargetInfo for little endian. 1666 class PPC64TargetInfo : public PPCTargetInfo { 1667 public: 1668 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1669 : PPCTargetInfo(Triple, Opts) { 1670 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1671 IntMaxType = SignedLong; 1672 Int64Type = SignedLong; 1673 1674 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1675 resetDataLayout("e-m:e-i64:64-n32:64"); 1676 ABI = "elfv2"; 1677 } else { 1678 resetDataLayout("E-m:e-i64:64-n32:64"); 1679 ABI = "elfv1"; 1680 } 1681 1682 switch (getTriple().getOS()) { 1683 case llvm::Triple::FreeBSD: 1684 LongDoubleWidth = LongDoubleAlign = 64; 1685 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1686 break; 1687 case llvm::Triple::NetBSD: 1688 IntMaxType = SignedLongLong; 1689 Int64Type = SignedLongLong; 1690 break; 1691 default: 1692 break; 1693 } 1694 1695 // PPC64 supports atomics up to 8 bytes. 1696 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1697 } 1698 BuiltinVaListKind getBuiltinVaListKind() const override { 1699 return TargetInfo::CharPtrBuiltinVaList; 1700 } 1701 // PPC64 Linux-specific ABI options. 1702 bool setABI(const std::string &Name) override { 1703 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1704 ABI = Name; 1705 return true; 1706 } 1707 return false; 1708 } 1709 }; 1710 1711 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1712 public: 1713 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1714 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1715 HasAlignMac68kSupport = true; 1716 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1717 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1718 LongLongAlign = 32; 1719 SuitableAlign = 128; 1720 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1721 } 1722 BuiltinVaListKind getBuiltinVaListKind() const override { 1723 return TargetInfo::CharPtrBuiltinVaList; 1724 } 1725 }; 1726 1727 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1728 public: 1729 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1730 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1731 HasAlignMac68kSupport = true; 1732 SuitableAlign = 128; 1733 resetDataLayout("E-m:o-i64:64-n32:64"); 1734 } 1735 }; 1736 1737 static const unsigned NVPTXAddrSpaceMap[] = { 1738 1, // opencl_global 1739 3, // opencl_local 1740 4, // opencl_constant 1741 // FIXME: generic has to be added to the target 1742 0, // opencl_generic 1743 1, // cuda_device 1744 4, // cuda_constant 1745 3, // cuda_shared 1746 }; 1747 1748 class NVPTXTargetInfo : public TargetInfo { 1749 static const char *const GCCRegNames[]; 1750 static const Builtin::Info BuiltinInfo[]; 1751 CudaArch GPU; 1752 1753 public: 1754 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1755 : TargetInfo(Triple) { 1756 TLSSupported = false; 1757 LongWidth = LongAlign = 64; 1758 AddrSpaceMap = &NVPTXAddrSpaceMap; 1759 UseAddrSpaceMapMangling = true; 1760 // Define available target features 1761 // These must be defined in sorted order! 1762 NoAsmVariants = true; 1763 GPU = CudaArch::SM_20; 1764 1765 // If possible, get a TargetInfo for our host triple, so we can match its 1766 // types. 1767 llvm::Triple HostTriple(Opts.HostTriple); 1768 if (HostTriple.isNVPTX()) 1769 return; 1770 std::unique_ptr<TargetInfo> HostTarget( 1771 AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1772 if (!HostTarget) { 1773 return; 1774 } 1775 1776 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1777 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1778 BoolWidth = HostTarget->getBoolWidth(); 1779 BoolAlign = HostTarget->getBoolAlign(); 1780 IntWidth = HostTarget->getIntWidth(); 1781 IntAlign = HostTarget->getIntAlign(); 1782 HalfWidth = HostTarget->getHalfWidth(); 1783 HalfAlign = HostTarget->getHalfAlign(); 1784 FloatWidth = HostTarget->getFloatWidth(); 1785 FloatAlign = HostTarget->getFloatAlign(); 1786 DoubleWidth = HostTarget->getDoubleWidth(); 1787 DoubleAlign = HostTarget->getDoubleAlign(); 1788 LongWidth = HostTarget->getLongWidth(); 1789 LongAlign = HostTarget->getLongAlign(); 1790 LongLongWidth = HostTarget->getLongLongWidth(); 1791 LongLongAlign = HostTarget->getLongLongAlign(); 1792 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1793 NewAlign = HostTarget->getNewAlign(); 1794 DefaultAlignForAttributeAligned = 1795 HostTarget->getDefaultAlignForAttributeAligned(); 1796 SizeType = HostTarget->getSizeType(); 1797 IntMaxType = HostTarget->getIntMaxType(); 1798 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1799 IntPtrType = HostTarget->getIntPtrType(); 1800 WCharType = HostTarget->getWCharType(); 1801 WIntType = HostTarget->getWIntType(); 1802 Char16Type = HostTarget->getChar16Type(); 1803 Char32Type = HostTarget->getChar32Type(); 1804 Int64Type = HostTarget->getInt64Type(); 1805 SigAtomicType = HostTarget->getSigAtomicType(); 1806 ProcessIDType = HostTarget->getProcessIDType(); 1807 1808 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1809 UseZeroLengthBitfieldAlignment = 1810 HostTarget->useZeroLengthBitfieldAlignment(); 1811 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1812 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1813 1814 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1815 // we need those macros to be identical on host and device, because (among 1816 // other things) they affect which standard library classes are defined, and 1817 // we need all classes to be defined on both the host and device. 1818 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1819 1820 // Properties intentionally not copied from host: 1821 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1822 // host/device boundary. 1823 // - SuitableAlign: Not visible across the host/device boundary, and may 1824 // correctly be different on host/device, e.g. if host has wider vector 1825 // types than device. 1826 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1827 // as its double type, but that's not necessarily true on the host. 1828 // TODO: nvcc emits a warning when using long double on device; we should 1829 // do the same. 1830 } 1831 void getTargetDefines(const LangOptions &Opts, 1832 MacroBuilder &Builder) const override { 1833 Builder.defineMacro("__PTX__"); 1834 Builder.defineMacro("__NVPTX__"); 1835 if (Opts.CUDAIsDevice) { 1836 // Set __CUDA_ARCH__ for the GPU specified. 1837 std::string CUDAArchCode = [this] { 1838 switch (GPU) { 1839 case CudaArch::UNKNOWN: 1840 assert(false && "No GPU arch when compiling CUDA device code."); 1841 return ""; 1842 case CudaArch::SM_20: 1843 return "200"; 1844 case CudaArch::SM_21: 1845 return "210"; 1846 case CudaArch::SM_30: 1847 return "300"; 1848 case CudaArch::SM_32: 1849 return "320"; 1850 case CudaArch::SM_35: 1851 return "350"; 1852 case CudaArch::SM_37: 1853 return "370"; 1854 case CudaArch::SM_50: 1855 return "500"; 1856 case CudaArch::SM_52: 1857 return "520"; 1858 case CudaArch::SM_53: 1859 return "530"; 1860 case CudaArch::SM_60: 1861 return "600"; 1862 case CudaArch::SM_61: 1863 return "610"; 1864 case CudaArch::SM_62: 1865 return "620"; 1866 } 1867 llvm_unreachable("unhandled CudaArch"); 1868 }(); 1869 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1870 } 1871 } 1872 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1873 return llvm::makeArrayRef(BuiltinInfo, 1874 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1875 } 1876 bool 1877 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1878 StringRef CPU, 1879 const std::vector<std::string> &FeaturesVec) const override { 1880 Features["satom"] = GPU >= CudaArch::SM_60; 1881 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1882 } 1883 1884 bool hasFeature(StringRef Feature) const override { 1885 return llvm::StringSwitch<bool>(Feature) 1886 .Cases("ptx", "nvptx", true) 1887 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1888 .Default(false); 1889 } 1890 1891 ArrayRef<const char *> getGCCRegNames() const override; 1892 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1893 // No aliases. 1894 return None; 1895 } 1896 bool validateAsmConstraint(const char *&Name, 1897 TargetInfo::ConstraintInfo &Info) const override { 1898 switch (*Name) { 1899 default: 1900 return false; 1901 case 'c': 1902 case 'h': 1903 case 'r': 1904 case 'l': 1905 case 'f': 1906 case 'd': 1907 Info.setAllowsRegister(); 1908 return true; 1909 } 1910 } 1911 const char *getClobbers() const override { 1912 // FIXME: Is this really right? 1913 return ""; 1914 } 1915 BuiltinVaListKind getBuiltinVaListKind() const override { 1916 // FIXME: implement 1917 return TargetInfo::CharPtrBuiltinVaList; 1918 } 1919 bool setCPU(const std::string &Name) override { 1920 GPU = StringToCudaArch(Name); 1921 return GPU != CudaArch::UNKNOWN; 1922 } 1923 void setSupportedOpenCLOpts() override { 1924 auto &Opts = getSupportedOpenCLOpts(); 1925 Opts.cl_clang_storage_class_specifiers = 1; 1926 Opts.cl_khr_gl_sharing = 1; 1927 Opts.cl_khr_icd = 1; 1928 1929 Opts.cl_khr_fp64 = 1; 1930 Opts.cl_khr_byte_addressable_store = 1; 1931 Opts.cl_khr_global_int32_base_atomics = 1; 1932 Opts.cl_khr_global_int32_extended_atomics = 1; 1933 Opts.cl_khr_local_int32_base_atomics = 1; 1934 Opts.cl_khr_local_int32_extended_atomics = 1; 1935 } 1936 }; 1937 1938 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1939 #define BUILTIN(ID, TYPE, ATTRS) \ 1940 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1941 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1942 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1943 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 1944 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 1945 #include "clang/Basic/BuiltinsNVPTX.def" 1946 }; 1947 1948 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1949 1950 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1951 return llvm::makeArrayRef(GCCRegNames); 1952 } 1953 1954 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1955 public: 1956 NVPTX32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1957 : NVPTXTargetInfo(Triple, Opts) { 1958 LongWidth = LongAlign = 32; 1959 PointerWidth = PointerAlign = 32; 1960 SizeType = TargetInfo::UnsignedInt; 1961 PtrDiffType = TargetInfo::SignedInt; 1962 IntPtrType = TargetInfo::SignedInt; 1963 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1964 } 1965 }; 1966 1967 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1968 public: 1969 NVPTX64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1970 : NVPTXTargetInfo(Triple, Opts) { 1971 PointerWidth = PointerAlign = 64; 1972 SizeType = TargetInfo::UnsignedLong; 1973 PtrDiffType = TargetInfo::SignedLong; 1974 IntPtrType = TargetInfo::SignedLong; 1975 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1976 } 1977 }; 1978 1979 static const unsigned AMDGPUAddrSpaceMap[] = { 1980 1, // opencl_global 1981 3, // opencl_local 1982 2, // opencl_constant 1983 4, // opencl_generic 1984 1, // cuda_device 1985 2, // cuda_constant 1986 3 // cuda_shared 1987 }; 1988 1989 // If you edit the description strings, make sure you update 1990 // getPointerWidthV(). 1991 1992 static const char *const DataLayoutStringR600 = 1993 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1994 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1995 1996 static const char *const DataLayoutStringSI = 1997 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 1998 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1999 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2000 2001 class AMDGPUTargetInfo final : public TargetInfo { 2002 static const Builtin::Info BuiltinInfo[]; 2003 static const char * const GCCRegNames[]; 2004 2005 /// \brief The GPU profiles supported by the AMDGPU target. 2006 enum GPUKind { 2007 GK_NONE, 2008 GK_R600, 2009 GK_R600_DOUBLE_OPS, 2010 GK_R700, 2011 GK_R700_DOUBLE_OPS, 2012 GK_EVERGREEN, 2013 GK_EVERGREEN_DOUBLE_OPS, 2014 GK_NORTHERN_ISLANDS, 2015 GK_CAYMAN, 2016 GK_GFX6, 2017 GK_GFX7, 2018 GK_GFX8 2019 } GPU; 2020 2021 bool hasFP64:1; 2022 bool hasFMAF:1; 2023 bool hasLDEXPF:1; 2024 bool hasFullSpeedFP32Denorms:1; 2025 2026 static bool isAMDGCN(const llvm::Triple &TT) { 2027 return TT.getArch() == llvm::Triple::amdgcn; 2028 } 2029 2030 public: 2031 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2032 : TargetInfo(Triple) , 2033 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2034 hasFP64(false), 2035 hasFMAF(false), 2036 hasLDEXPF(false), 2037 hasFullSpeedFP32Denorms(false){ 2038 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2039 hasFP64 = true; 2040 hasFMAF = true; 2041 hasLDEXPF = true; 2042 } 2043 2044 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2045 DataLayoutStringSI : DataLayoutStringR600); 2046 2047 AddrSpaceMap = &AMDGPUAddrSpaceMap; 2048 UseAddrSpaceMapMangling = true; 2049 } 2050 2051 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2052 if (GPU <= GK_CAYMAN) 2053 return 32; 2054 2055 switch(AddrSpace) { 2056 default: 2057 return 64; 2058 case 0: 2059 case 3: 2060 case 5: 2061 return 32; 2062 } 2063 } 2064 2065 uint64_t getMaxPointerWidth() const override { 2066 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2067 } 2068 2069 const char * getClobbers() const override { 2070 return ""; 2071 } 2072 2073 ArrayRef<const char *> getGCCRegNames() const override; 2074 2075 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2076 return None; 2077 } 2078 2079 bool validateAsmConstraint(const char *&Name, 2080 TargetInfo::ConstraintInfo &Info) const override { 2081 switch (*Name) { 2082 default: break; 2083 case 'v': // vgpr 2084 case 's': // sgpr 2085 Info.setAllowsRegister(); 2086 return true; 2087 } 2088 return false; 2089 } 2090 2091 bool initFeatureMap(llvm::StringMap<bool> &Features, 2092 DiagnosticsEngine &Diags, StringRef CPU, 2093 const std::vector<std::string> &FeatureVec) const override; 2094 2095 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2096 TargetOptions &TargetOpts) const override { 2097 bool hasFP32Denormals = false; 2098 bool hasFP64Denormals = false; 2099 for (auto &I : TargetOpts.FeaturesAsWritten) { 2100 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2101 hasFP32Denormals = true; 2102 if (I == "+fp64-denormals" || I == "-fp64-denormals") 2103 hasFP64Denormals = true; 2104 } 2105 if (!hasFP32Denormals) 2106 TargetOpts.Features.push_back((Twine(hasFullSpeedFP32Denorms && 2107 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2108 // Always do not flush fp64 denorms. 2109 if (!hasFP64Denormals && hasFP64) 2110 TargetOpts.Features.push_back("+fp64-denormals"); 2111 } 2112 2113 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2114 return llvm::makeArrayRef(BuiltinInfo, 2115 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2116 } 2117 2118 void getTargetDefines(const LangOptions &Opts, 2119 MacroBuilder &Builder) const override { 2120 if (getTriple().getArch() == llvm::Triple::amdgcn) 2121 Builder.defineMacro("__AMDGCN__"); 2122 else 2123 Builder.defineMacro("__R600__"); 2124 2125 if (hasFMAF) 2126 Builder.defineMacro("__HAS_FMAF__"); 2127 if (hasLDEXPF) 2128 Builder.defineMacro("__HAS_LDEXPF__"); 2129 if (hasFP64) 2130 Builder.defineMacro("__HAS_FP64__"); 2131 } 2132 2133 BuiltinVaListKind getBuiltinVaListKind() const override { 2134 return TargetInfo::CharPtrBuiltinVaList; 2135 } 2136 2137 static GPUKind parseR600Name(StringRef Name) { 2138 return llvm::StringSwitch<GPUKind>(Name) 2139 .Case("r600" , GK_R600) 2140 .Case("rv610", GK_R600) 2141 .Case("rv620", GK_R600) 2142 .Case("rv630", GK_R600) 2143 .Case("rv635", GK_R600) 2144 .Case("rs780", GK_R600) 2145 .Case("rs880", GK_R600) 2146 .Case("rv670", GK_R600_DOUBLE_OPS) 2147 .Case("rv710", GK_R700) 2148 .Case("rv730", GK_R700) 2149 .Case("rv740", GK_R700_DOUBLE_OPS) 2150 .Case("rv770", GK_R700_DOUBLE_OPS) 2151 .Case("palm", GK_EVERGREEN) 2152 .Case("cedar", GK_EVERGREEN) 2153 .Case("sumo", GK_EVERGREEN) 2154 .Case("sumo2", GK_EVERGREEN) 2155 .Case("redwood", GK_EVERGREEN) 2156 .Case("juniper", GK_EVERGREEN) 2157 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2158 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2159 .Case("barts", GK_NORTHERN_ISLANDS) 2160 .Case("turks", GK_NORTHERN_ISLANDS) 2161 .Case("caicos", GK_NORTHERN_ISLANDS) 2162 .Case("cayman", GK_CAYMAN) 2163 .Case("aruba", GK_CAYMAN) 2164 .Default(GK_NONE); 2165 } 2166 2167 static GPUKind parseAMDGCNName(StringRef Name) { 2168 return llvm::StringSwitch<GPUKind>(Name) 2169 .Case("tahiti", GK_GFX6) 2170 .Case("pitcairn", GK_GFX6) 2171 .Case("verde", GK_GFX6) 2172 .Case("oland", GK_GFX6) 2173 .Case("hainan", GK_GFX6) 2174 .Case("bonaire", GK_GFX7) 2175 .Case("kabini", GK_GFX7) 2176 .Case("kaveri", GK_GFX7) 2177 .Case("hawaii", GK_GFX7) 2178 .Case("mullins", GK_GFX7) 2179 .Case("gfx700", GK_GFX7) 2180 .Case("gfx701", GK_GFX7) 2181 .Case("gfx702", GK_GFX7) 2182 .Case("tonga", GK_GFX8) 2183 .Case("iceland", GK_GFX8) 2184 .Case("carrizo", GK_GFX8) 2185 .Case("fiji", GK_GFX8) 2186 .Case("stoney", GK_GFX8) 2187 .Case("polaris10", GK_GFX8) 2188 .Case("polaris11", GK_GFX8) 2189 .Case("gfx800", GK_GFX8) 2190 .Case("gfx801", GK_GFX8) 2191 .Case("gfx802", GK_GFX8) 2192 .Case("gfx803", GK_GFX8) 2193 .Case("gfx804", GK_GFX8) 2194 .Case("gfx810", GK_GFX8) 2195 .Default(GK_NONE); 2196 } 2197 2198 bool setCPU(const std::string &Name) override { 2199 if (getTriple().getArch() == llvm::Triple::amdgcn) 2200 GPU = parseAMDGCNName(Name); 2201 else 2202 GPU = parseR600Name(Name); 2203 2204 return GPU != GK_NONE; 2205 } 2206 2207 void setSupportedOpenCLOpts() override { 2208 auto &Opts = getSupportedOpenCLOpts(); 2209 Opts.cl_clang_storage_class_specifiers = 1; 2210 Opts.cl_khr_icd = 1; 2211 2212 if (hasFP64) 2213 Opts.cl_khr_fp64 = 1; 2214 if (GPU >= GK_EVERGREEN) { 2215 Opts.cl_khr_byte_addressable_store = 1; 2216 Opts.cl_khr_global_int32_base_atomics = 1; 2217 Opts.cl_khr_global_int32_extended_atomics = 1; 2218 Opts.cl_khr_local_int32_base_atomics = 1; 2219 Opts.cl_khr_local_int32_extended_atomics = 1; 2220 } 2221 if (GPU >= GK_GFX6) { 2222 Opts.cl_khr_fp16 = 1; 2223 Opts.cl_khr_int64_base_atomics = 1; 2224 Opts.cl_khr_int64_extended_atomics = 1; 2225 Opts.cl_khr_mipmap_image = 1; 2226 Opts.cl_khr_subgroups = 1; 2227 Opts.cl_khr_3d_image_writes = 1; 2228 Opts.cl_amd_media_ops = 1; 2229 Opts.cl_amd_media_ops2 = 1; 2230 } 2231 } 2232 2233 LangAS::ID getOpenCLImageAddrSpace() const override { 2234 return LangAS::opencl_constant; 2235 } 2236 2237 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2238 switch (CC) { 2239 default: 2240 return CCCR_Warning; 2241 case CC_C: 2242 case CC_OpenCLKernel: 2243 return CCCR_OK; 2244 } 2245 } 2246 }; 2247 2248 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2249 #define BUILTIN(ID, TYPE, ATTRS) \ 2250 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2251 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2252 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2253 #include "clang/Basic/BuiltinsAMDGPU.def" 2254 }; 2255 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2256 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2257 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2258 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2259 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2260 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2261 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2262 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2263 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2264 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2265 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2266 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2267 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2268 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2269 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2270 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2271 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2272 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2273 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2274 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2275 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2276 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2277 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2278 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2279 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2280 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2281 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2282 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2283 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2284 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2285 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2286 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2287 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2288 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2289 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2290 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2291 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2292 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2293 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2294 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2295 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2296 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2297 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2298 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2299 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2300 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2301 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2302 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2303 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2304 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2305 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2306 }; 2307 2308 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2309 return llvm::makeArrayRef(GCCRegNames); 2310 } 2311 2312 bool AMDGPUTargetInfo::initFeatureMap( 2313 llvm::StringMap<bool> &Features, 2314 DiagnosticsEngine &Diags, StringRef CPU, 2315 const std::vector<std::string> &FeatureVec) const { 2316 2317 // XXX - What does the member GPU mean if device name string passed here? 2318 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2319 if (CPU.empty()) 2320 CPU = "tahiti"; 2321 2322 switch (parseAMDGCNName(CPU)) { 2323 case GK_GFX6: 2324 case GK_GFX7: 2325 break; 2326 2327 case GK_GFX8: 2328 Features["s-memrealtime"] = true; 2329 Features["16-bit-insts"] = true; 2330 break; 2331 2332 case GK_NONE: 2333 return false; 2334 default: 2335 llvm_unreachable("unhandled subtarget"); 2336 } 2337 } else { 2338 if (CPU.empty()) 2339 CPU = "r600"; 2340 2341 switch (parseR600Name(CPU)) { 2342 case GK_R600: 2343 case GK_R700: 2344 case GK_EVERGREEN: 2345 case GK_NORTHERN_ISLANDS: 2346 break; 2347 case GK_R600_DOUBLE_OPS: 2348 case GK_R700_DOUBLE_OPS: 2349 case GK_EVERGREEN_DOUBLE_OPS: 2350 case GK_CAYMAN: 2351 Features["fp64"] = true; 2352 break; 2353 case GK_NONE: 2354 return false; 2355 default: 2356 llvm_unreachable("unhandled subtarget"); 2357 } 2358 } 2359 2360 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2361 } 2362 2363 const Builtin::Info BuiltinInfoX86[] = { 2364 #define BUILTIN(ID, TYPE, ATTRS) \ 2365 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2366 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2367 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2368 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2369 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2370 #include "clang/Basic/BuiltinsX86.def" 2371 2372 #define BUILTIN(ID, TYPE, ATTRS) \ 2373 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2374 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2375 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2376 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2377 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2378 #include "clang/Basic/BuiltinsX86_64.def" 2379 }; 2380 2381 2382 static const char* const GCCRegNames[] = { 2383 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2384 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2385 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2386 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2387 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2388 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2389 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2390 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2391 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2392 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2393 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2394 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2395 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2396 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2397 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2398 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2399 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2400 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2401 }; 2402 2403 const TargetInfo::AddlRegName AddlRegNames[] = { 2404 { { "al", "ah", "eax", "rax" }, 0 }, 2405 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2406 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2407 { { "dl", "dh", "edx", "rdx" }, 1 }, 2408 { { "esi", "rsi" }, 4 }, 2409 { { "edi", "rdi" }, 5 }, 2410 { { "esp", "rsp" }, 7 }, 2411 { { "ebp", "rbp" }, 6 }, 2412 { { "r8d", "r8w", "r8b" }, 38 }, 2413 { { "r9d", "r9w", "r9b" }, 39 }, 2414 { { "r10d", "r10w", "r10b" }, 40 }, 2415 { { "r11d", "r11w", "r11b" }, 41 }, 2416 { { "r12d", "r12w", "r12b" }, 42 }, 2417 { { "r13d", "r13w", "r13b" }, 43 }, 2418 { { "r14d", "r14w", "r14b" }, 44 }, 2419 { { "r15d", "r15w", "r15b" }, 45 }, 2420 }; 2421 2422 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2423 // most of the implementation can be shared. 2424 class X86TargetInfo : public TargetInfo { 2425 enum X86SSEEnum { 2426 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2427 } SSELevel = NoSSE; 2428 enum MMX3DNowEnum { 2429 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2430 } MMX3DNowLevel = NoMMX3DNow; 2431 enum XOPEnum { 2432 NoXOP, 2433 SSE4A, 2434 FMA4, 2435 XOP 2436 } XOPLevel = NoXOP; 2437 2438 bool HasAES = false; 2439 bool HasPCLMUL = false; 2440 bool HasLZCNT = false; 2441 bool HasRDRND = false; 2442 bool HasFSGSBASE = false; 2443 bool HasBMI = false; 2444 bool HasBMI2 = false; 2445 bool HasPOPCNT = false; 2446 bool HasRTM = false; 2447 bool HasPRFCHW = false; 2448 bool HasRDSEED = false; 2449 bool HasADX = false; 2450 bool HasTBM = false; 2451 bool HasFMA = false; 2452 bool HasF16C = false; 2453 bool HasAVX512CD = false; 2454 bool HasAVX512ER = false; 2455 bool HasAVX512PF = false; 2456 bool HasAVX512DQ = false; 2457 bool HasAVX512BW = false; 2458 bool HasAVX512VL = false; 2459 bool HasAVX512VBMI = false; 2460 bool HasAVX512IFMA = false; 2461 bool HasSHA = false; 2462 bool HasMPX = false; 2463 bool HasSGX = false; 2464 bool HasCX16 = false; 2465 bool HasFXSR = false; 2466 bool HasXSAVE = false; 2467 bool HasXSAVEOPT = false; 2468 bool HasXSAVEC = false; 2469 bool HasXSAVES = false; 2470 bool HasMWAITX = false; 2471 bool HasPKU = false; 2472 bool HasCLFLUSHOPT = false; 2473 bool HasPCOMMIT = false; 2474 bool HasCLWB = false; 2475 bool HasUMIP = false; 2476 bool HasMOVBE = false; 2477 bool HasPREFETCHWT1 = false; 2478 2479 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2480 /// 2481 /// Each enumeration represents a particular CPU supported by Clang. These 2482 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2483 enum CPUKind { 2484 CK_Generic, 2485 2486 /// \name i386 2487 /// i386-generation processors. 2488 //@{ 2489 CK_i386, 2490 //@} 2491 2492 /// \name i486 2493 /// i486-generation processors. 2494 //@{ 2495 CK_i486, 2496 CK_WinChipC6, 2497 CK_WinChip2, 2498 CK_C3, 2499 //@} 2500 2501 /// \name i586 2502 /// i586-generation processors, P5 microarchitecture based. 2503 //@{ 2504 CK_i586, 2505 CK_Pentium, 2506 CK_PentiumMMX, 2507 //@} 2508 2509 /// \name i686 2510 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2511 //@{ 2512 CK_i686, 2513 CK_PentiumPro, 2514 CK_Pentium2, 2515 CK_Pentium3, 2516 CK_Pentium3M, 2517 CK_PentiumM, 2518 CK_C3_2, 2519 2520 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2521 /// Clang however has some logic to suport this. 2522 // FIXME: Warn, deprecate, and potentially remove this. 2523 CK_Yonah, 2524 //@} 2525 2526 /// \name Netburst 2527 /// Netburst microarchitecture based processors. 2528 //@{ 2529 CK_Pentium4, 2530 CK_Pentium4M, 2531 CK_Prescott, 2532 CK_Nocona, 2533 //@} 2534 2535 /// \name Core 2536 /// Core microarchitecture based processors. 2537 //@{ 2538 CK_Core2, 2539 2540 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2541 /// codename which GCC no longer accepts as an option to -march, but Clang 2542 /// has some logic for recognizing it. 2543 // FIXME: Warn, deprecate, and potentially remove this. 2544 CK_Penryn, 2545 //@} 2546 2547 /// \name Atom 2548 /// Atom processors 2549 //@{ 2550 CK_Bonnell, 2551 CK_Silvermont, 2552 //@} 2553 2554 /// \name Nehalem 2555 /// Nehalem microarchitecture based processors. 2556 CK_Nehalem, 2557 2558 /// \name Westmere 2559 /// Westmere microarchitecture based processors. 2560 CK_Westmere, 2561 2562 /// \name Sandy Bridge 2563 /// Sandy Bridge microarchitecture based processors. 2564 CK_SandyBridge, 2565 2566 /// \name Ivy Bridge 2567 /// Ivy Bridge microarchitecture based processors. 2568 CK_IvyBridge, 2569 2570 /// \name Haswell 2571 /// Haswell microarchitecture based processors. 2572 CK_Haswell, 2573 2574 /// \name Broadwell 2575 /// Broadwell microarchitecture based processors. 2576 CK_Broadwell, 2577 2578 /// \name Skylake Client 2579 /// Skylake client microarchitecture based processors. 2580 CK_SkylakeClient, 2581 2582 /// \name Skylake Server 2583 /// Skylake server microarchitecture based processors. 2584 CK_SkylakeServer, 2585 2586 /// \name Cannonlake Client 2587 /// Cannonlake client microarchitecture based processors. 2588 CK_Cannonlake, 2589 2590 /// \name Knights Landing 2591 /// Knights Landing processor. 2592 CK_KNL, 2593 2594 /// \name Lakemont 2595 /// Lakemont microarchitecture based processors. 2596 CK_Lakemont, 2597 2598 /// \name K6 2599 /// K6 architecture processors. 2600 //@{ 2601 CK_K6, 2602 CK_K6_2, 2603 CK_K6_3, 2604 //@} 2605 2606 /// \name K7 2607 /// K7 architecture processors. 2608 //@{ 2609 CK_Athlon, 2610 CK_AthlonThunderbird, 2611 CK_Athlon4, 2612 CK_AthlonXP, 2613 CK_AthlonMP, 2614 //@} 2615 2616 /// \name K8 2617 /// K8 architecture processors. 2618 //@{ 2619 CK_Athlon64, 2620 CK_Athlon64SSE3, 2621 CK_AthlonFX, 2622 CK_K8, 2623 CK_K8SSE3, 2624 CK_Opteron, 2625 CK_OpteronSSE3, 2626 CK_AMDFAM10, 2627 //@} 2628 2629 /// \name Bobcat 2630 /// Bobcat architecture processors. 2631 //@{ 2632 CK_BTVER1, 2633 CK_BTVER2, 2634 //@} 2635 2636 /// \name Bulldozer 2637 /// Bulldozer architecture processors. 2638 //@{ 2639 CK_BDVER1, 2640 CK_BDVER2, 2641 CK_BDVER3, 2642 CK_BDVER4, 2643 //@} 2644 2645 /// This specification is deprecated and will be removed in the future. 2646 /// Users should prefer \see CK_K8. 2647 // FIXME: Warn on this when the CPU is set to it. 2648 //@{ 2649 CK_x86_64, 2650 //@} 2651 2652 /// \name Geode 2653 /// Geode processors. 2654 //@{ 2655 CK_Geode 2656 //@} 2657 } CPU = CK_Generic; 2658 2659 CPUKind getCPUKind(StringRef CPU) const { 2660 return llvm::StringSwitch<CPUKind>(CPU) 2661 .Case("i386", CK_i386) 2662 .Case("i486", CK_i486) 2663 .Case("winchip-c6", CK_WinChipC6) 2664 .Case("winchip2", CK_WinChip2) 2665 .Case("c3", CK_C3) 2666 .Case("i586", CK_i586) 2667 .Case("pentium", CK_Pentium) 2668 .Case("pentium-mmx", CK_PentiumMMX) 2669 .Case("i686", CK_i686) 2670 .Case("pentiumpro", CK_PentiumPro) 2671 .Case("pentium2", CK_Pentium2) 2672 .Case("pentium3", CK_Pentium3) 2673 .Case("pentium3m", CK_Pentium3M) 2674 .Case("pentium-m", CK_PentiumM) 2675 .Case("c3-2", CK_C3_2) 2676 .Case("yonah", CK_Yonah) 2677 .Case("pentium4", CK_Pentium4) 2678 .Case("pentium4m", CK_Pentium4M) 2679 .Case("prescott", CK_Prescott) 2680 .Case("nocona", CK_Nocona) 2681 .Case("core2", CK_Core2) 2682 .Case("penryn", CK_Penryn) 2683 .Case("bonnell", CK_Bonnell) 2684 .Case("atom", CK_Bonnell) // Legacy name. 2685 .Case("silvermont", CK_Silvermont) 2686 .Case("slm", CK_Silvermont) // Legacy name. 2687 .Case("nehalem", CK_Nehalem) 2688 .Case("corei7", CK_Nehalem) // Legacy name. 2689 .Case("westmere", CK_Westmere) 2690 .Case("sandybridge", CK_SandyBridge) 2691 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2692 .Case("ivybridge", CK_IvyBridge) 2693 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2694 .Case("haswell", CK_Haswell) 2695 .Case("core-avx2", CK_Haswell) // Legacy name. 2696 .Case("broadwell", CK_Broadwell) 2697 .Case("skylake", CK_SkylakeClient) 2698 .Case("skylake-avx512", CK_SkylakeServer) 2699 .Case("skx", CK_SkylakeServer) // Legacy name. 2700 .Case("cannonlake", CK_Cannonlake) 2701 .Case("knl", CK_KNL) 2702 .Case("lakemont", CK_Lakemont) 2703 .Case("k6", CK_K6) 2704 .Case("k6-2", CK_K6_2) 2705 .Case("k6-3", CK_K6_3) 2706 .Case("athlon", CK_Athlon) 2707 .Case("athlon-tbird", CK_AthlonThunderbird) 2708 .Case("athlon-4", CK_Athlon4) 2709 .Case("athlon-xp", CK_AthlonXP) 2710 .Case("athlon-mp", CK_AthlonMP) 2711 .Case("athlon64", CK_Athlon64) 2712 .Case("athlon64-sse3", CK_Athlon64SSE3) 2713 .Case("athlon-fx", CK_AthlonFX) 2714 .Case("k8", CK_K8) 2715 .Case("k8-sse3", CK_K8SSE3) 2716 .Case("opteron", CK_Opteron) 2717 .Case("opteron-sse3", CK_OpteronSSE3) 2718 .Case("barcelona", CK_AMDFAM10) 2719 .Case("amdfam10", CK_AMDFAM10) 2720 .Case("btver1", CK_BTVER1) 2721 .Case("btver2", CK_BTVER2) 2722 .Case("bdver1", CK_BDVER1) 2723 .Case("bdver2", CK_BDVER2) 2724 .Case("bdver3", CK_BDVER3) 2725 .Case("bdver4", CK_BDVER4) 2726 .Case("x86-64", CK_x86_64) 2727 .Case("geode", CK_Geode) 2728 .Default(CK_Generic); 2729 } 2730 2731 enum FPMathKind { 2732 FP_Default, 2733 FP_SSE, 2734 FP_387 2735 } FPMath = FP_Default; 2736 2737 public: 2738 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2739 : TargetInfo(Triple) { 2740 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2741 } 2742 unsigned getFloatEvalMethod() const override { 2743 // X87 evaluates with 80 bits "long double" precision. 2744 return SSELevel == NoSSE ? 2 : 0; 2745 } 2746 ArrayRef<const char *> getGCCRegNames() const override { 2747 return llvm::makeArrayRef(GCCRegNames); 2748 } 2749 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2750 return None; 2751 } 2752 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2753 return llvm::makeArrayRef(AddlRegNames); 2754 } 2755 bool validateCpuSupports(StringRef Name) const override; 2756 bool validateAsmConstraint(const char *&Name, 2757 TargetInfo::ConstraintInfo &info) const override; 2758 2759 bool validateGlobalRegisterVariable(StringRef RegName, 2760 unsigned RegSize, 2761 bool &HasSizeMismatch) const override { 2762 // esp and ebp are the only 32-bit registers the x86 backend can currently 2763 // handle. 2764 if (RegName.equals("esp") || RegName.equals("ebp")) { 2765 // Check that the register size is 32-bit. 2766 HasSizeMismatch = RegSize != 32; 2767 return true; 2768 } 2769 2770 return false; 2771 } 2772 2773 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2774 2775 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2776 2777 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2778 2779 std::string convertConstraint(const char *&Constraint) const override; 2780 const char *getClobbers() const override { 2781 return "~{dirflag},~{fpsr},~{flags}"; 2782 } 2783 void getTargetDefines(const LangOptions &Opts, 2784 MacroBuilder &Builder) const override; 2785 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2786 bool Enabled); 2787 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2788 bool Enabled); 2789 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2790 bool Enabled); 2791 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2792 StringRef Name, bool Enabled) const override { 2793 setFeatureEnabledImpl(Features, Name, Enabled); 2794 } 2795 // This exists purely to cut down on the number of virtual calls in 2796 // initFeatureMap which calls this repeatedly. 2797 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2798 StringRef Name, bool Enabled); 2799 bool 2800 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2801 StringRef CPU, 2802 const std::vector<std::string> &FeaturesVec) const override; 2803 bool hasFeature(StringRef Feature) const override; 2804 bool handleTargetFeatures(std::vector<std::string> &Features, 2805 DiagnosticsEngine &Diags) override; 2806 StringRef getABI() const override { 2807 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2808 return "avx512"; 2809 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2810 return "avx"; 2811 if (getTriple().getArch() == llvm::Triple::x86 && 2812 MMX3DNowLevel == NoMMX3DNow) 2813 return "no-mmx"; 2814 return ""; 2815 } 2816 bool setCPU(const std::string &Name) override { 2817 CPU = getCPUKind(Name); 2818 2819 // Perform any per-CPU checks necessary to determine if this CPU is 2820 // acceptable. 2821 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2822 // invalid without explaining *why*. 2823 switch (CPU) { 2824 case CK_Generic: 2825 // No processor selected! 2826 return false; 2827 2828 case CK_i386: 2829 case CK_i486: 2830 case CK_WinChipC6: 2831 case CK_WinChip2: 2832 case CK_C3: 2833 case CK_i586: 2834 case CK_Pentium: 2835 case CK_PentiumMMX: 2836 case CK_i686: 2837 case CK_PentiumPro: 2838 case CK_Pentium2: 2839 case CK_Pentium3: 2840 case CK_Pentium3M: 2841 case CK_PentiumM: 2842 case CK_Yonah: 2843 case CK_C3_2: 2844 case CK_Pentium4: 2845 case CK_Pentium4M: 2846 case CK_Lakemont: 2847 case CK_Prescott: 2848 case CK_K6: 2849 case CK_K6_2: 2850 case CK_K6_3: 2851 case CK_Athlon: 2852 case CK_AthlonThunderbird: 2853 case CK_Athlon4: 2854 case CK_AthlonXP: 2855 case CK_AthlonMP: 2856 case CK_Geode: 2857 // Only accept certain architectures when compiling in 32-bit mode. 2858 if (getTriple().getArch() != llvm::Triple::x86) 2859 return false; 2860 2861 // Fallthrough 2862 case CK_Nocona: 2863 case CK_Core2: 2864 case CK_Penryn: 2865 case CK_Bonnell: 2866 case CK_Silvermont: 2867 case CK_Nehalem: 2868 case CK_Westmere: 2869 case CK_SandyBridge: 2870 case CK_IvyBridge: 2871 case CK_Haswell: 2872 case CK_Broadwell: 2873 case CK_SkylakeClient: 2874 case CK_SkylakeServer: 2875 case CK_Cannonlake: 2876 case CK_KNL: 2877 case CK_Athlon64: 2878 case CK_Athlon64SSE3: 2879 case CK_AthlonFX: 2880 case CK_K8: 2881 case CK_K8SSE3: 2882 case CK_Opteron: 2883 case CK_OpteronSSE3: 2884 case CK_AMDFAM10: 2885 case CK_BTVER1: 2886 case CK_BTVER2: 2887 case CK_BDVER1: 2888 case CK_BDVER2: 2889 case CK_BDVER3: 2890 case CK_BDVER4: 2891 case CK_x86_64: 2892 return true; 2893 } 2894 llvm_unreachable("Unhandled CPU kind"); 2895 } 2896 2897 bool setFPMath(StringRef Name) override; 2898 2899 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2900 // Most of the non-ARM calling conventions are i386 conventions. 2901 switch (CC) { 2902 case CC_X86ThisCall: 2903 case CC_X86FastCall: 2904 case CC_X86StdCall: 2905 case CC_X86VectorCall: 2906 case CC_C: 2907 case CC_Swift: 2908 case CC_X86Pascal: 2909 case CC_IntelOclBicc: 2910 return CCCR_OK; 2911 default: 2912 return CCCR_Warning; 2913 } 2914 } 2915 2916 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2917 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2918 } 2919 2920 bool hasSjLjLowering() const override { 2921 return true; 2922 } 2923 2924 void setSupportedOpenCLOpts() override { 2925 getSupportedOpenCLOpts().setAll(); 2926 } 2927 }; 2928 2929 bool X86TargetInfo::setFPMath(StringRef Name) { 2930 if (Name == "387") { 2931 FPMath = FP_387; 2932 return true; 2933 } 2934 if (Name == "sse") { 2935 FPMath = FP_SSE; 2936 return true; 2937 } 2938 return false; 2939 } 2940 2941 bool X86TargetInfo::initFeatureMap( 2942 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2943 const std::vector<std::string> &FeaturesVec) const { 2944 // FIXME: This *really* should not be here. 2945 // X86_64 always has SSE2. 2946 if (getTriple().getArch() == llvm::Triple::x86_64) 2947 setFeatureEnabledImpl(Features, "sse2", true); 2948 2949 const CPUKind Kind = getCPUKind(CPU); 2950 2951 // Enable X87 for all X86 processors but Lakemont. 2952 if (Kind != CK_Lakemont) 2953 setFeatureEnabledImpl(Features, "x87", true); 2954 2955 switch (Kind) { 2956 case CK_Generic: 2957 case CK_i386: 2958 case CK_i486: 2959 case CK_i586: 2960 case CK_Pentium: 2961 case CK_i686: 2962 case CK_PentiumPro: 2963 case CK_Lakemont: 2964 break; 2965 case CK_PentiumMMX: 2966 case CK_Pentium2: 2967 case CK_K6: 2968 case CK_WinChipC6: 2969 setFeatureEnabledImpl(Features, "mmx", true); 2970 break; 2971 case CK_Pentium3: 2972 case CK_Pentium3M: 2973 case CK_C3_2: 2974 setFeatureEnabledImpl(Features, "sse", true); 2975 setFeatureEnabledImpl(Features, "fxsr", true); 2976 break; 2977 case CK_PentiumM: 2978 case CK_Pentium4: 2979 case CK_Pentium4M: 2980 case CK_x86_64: 2981 setFeatureEnabledImpl(Features, "sse2", true); 2982 setFeatureEnabledImpl(Features, "fxsr", true); 2983 break; 2984 case CK_Yonah: 2985 case CK_Prescott: 2986 case CK_Nocona: 2987 setFeatureEnabledImpl(Features, "sse3", true); 2988 setFeatureEnabledImpl(Features, "fxsr", true); 2989 setFeatureEnabledImpl(Features, "cx16", true); 2990 break; 2991 case CK_Core2: 2992 case CK_Bonnell: 2993 setFeatureEnabledImpl(Features, "ssse3", true); 2994 setFeatureEnabledImpl(Features, "fxsr", true); 2995 setFeatureEnabledImpl(Features, "cx16", true); 2996 break; 2997 case CK_Penryn: 2998 setFeatureEnabledImpl(Features, "sse4.1", true); 2999 setFeatureEnabledImpl(Features, "fxsr", true); 3000 setFeatureEnabledImpl(Features, "cx16", true); 3001 break; 3002 case CK_Cannonlake: 3003 setFeatureEnabledImpl(Features, "avx512ifma", true); 3004 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3005 setFeatureEnabledImpl(Features, "sha", true); 3006 setFeatureEnabledImpl(Features, "umip", true); 3007 // FALLTHROUGH 3008 case CK_SkylakeServer: 3009 setFeatureEnabledImpl(Features, "avx512f", true); 3010 setFeatureEnabledImpl(Features, "avx512cd", true); 3011 setFeatureEnabledImpl(Features, "avx512dq", true); 3012 setFeatureEnabledImpl(Features, "avx512bw", true); 3013 setFeatureEnabledImpl(Features, "avx512vl", true); 3014 setFeatureEnabledImpl(Features, "pku", true); 3015 setFeatureEnabledImpl(Features, "pcommit", true); 3016 setFeatureEnabledImpl(Features, "clwb", true); 3017 // FALLTHROUGH 3018 case CK_SkylakeClient: 3019 setFeatureEnabledImpl(Features, "xsavec", true); 3020 setFeatureEnabledImpl(Features, "xsaves", true); 3021 setFeatureEnabledImpl(Features, "mpx", true); 3022 setFeatureEnabledImpl(Features, "sgx", true); 3023 setFeatureEnabledImpl(Features, "clflushopt", true); 3024 // FALLTHROUGH 3025 case CK_Broadwell: 3026 setFeatureEnabledImpl(Features, "rdseed", true); 3027 setFeatureEnabledImpl(Features, "adx", true); 3028 // FALLTHROUGH 3029 case CK_Haswell: 3030 setFeatureEnabledImpl(Features, "avx2", true); 3031 setFeatureEnabledImpl(Features, "lzcnt", true); 3032 setFeatureEnabledImpl(Features, "bmi", true); 3033 setFeatureEnabledImpl(Features, "bmi2", true); 3034 setFeatureEnabledImpl(Features, "rtm", true); 3035 setFeatureEnabledImpl(Features, "fma", true); 3036 setFeatureEnabledImpl(Features, "movbe", true); 3037 // FALLTHROUGH 3038 case CK_IvyBridge: 3039 setFeatureEnabledImpl(Features, "rdrnd", true); 3040 setFeatureEnabledImpl(Features, "f16c", true); 3041 setFeatureEnabledImpl(Features, "fsgsbase", true); 3042 // FALLTHROUGH 3043 case CK_SandyBridge: 3044 setFeatureEnabledImpl(Features, "avx", true); 3045 setFeatureEnabledImpl(Features, "xsave", true); 3046 setFeatureEnabledImpl(Features, "xsaveopt", true); 3047 // FALLTHROUGH 3048 case CK_Westmere: 3049 case CK_Silvermont: 3050 setFeatureEnabledImpl(Features, "aes", true); 3051 setFeatureEnabledImpl(Features, "pclmul", true); 3052 // FALLTHROUGH 3053 case CK_Nehalem: 3054 setFeatureEnabledImpl(Features, "sse4.2", true); 3055 setFeatureEnabledImpl(Features, "fxsr", true); 3056 setFeatureEnabledImpl(Features, "cx16", true); 3057 break; 3058 case CK_KNL: 3059 setFeatureEnabledImpl(Features, "avx512f", true); 3060 setFeatureEnabledImpl(Features, "avx512cd", true); 3061 setFeatureEnabledImpl(Features, "avx512er", true); 3062 setFeatureEnabledImpl(Features, "avx512pf", true); 3063 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3064 setFeatureEnabledImpl(Features, "fxsr", true); 3065 setFeatureEnabledImpl(Features, "rdseed", true); 3066 setFeatureEnabledImpl(Features, "adx", true); 3067 setFeatureEnabledImpl(Features, "lzcnt", true); 3068 setFeatureEnabledImpl(Features, "bmi", true); 3069 setFeatureEnabledImpl(Features, "bmi2", true); 3070 setFeatureEnabledImpl(Features, "rtm", true); 3071 setFeatureEnabledImpl(Features, "fma", true); 3072 setFeatureEnabledImpl(Features, "rdrnd", true); 3073 setFeatureEnabledImpl(Features, "f16c", true); 3074 setFeatureEnabledImpl(Features, "fsgsbase", true); 3075 setFeatureEnabledImpl(Features, "aes", true); 3076 setFeatureEnabledImpl(Features, "pclmul", true); 3077 setFeatureEnabledImpl(Features, "cx16", true); 3078 setFeatureEnabledImpl(Features, "xsaveopt", true); 3079 setFeatureEnabledImpl(Features, "xsave", true); 3080 setFeatureEnabledImpl(Features, "movbe", true); 3081 break; 3082 case CK_K6_2: 3083 case CK_K6_3: 3084 case CK_WinChip2: 3085 case CK_C3: 3086 setFeatureEnabledImpl(Features, "3dnow", true); 3087 break; 3088 case CK_Athlon: 3089 case CK_AthlonThunderbird: 3090 case CK_Geode: 3091 setFeatureEnabledImpl(Features, "3dnowa", true); 3092 break; 3093 case CK_Athlon4: 3094 case CK_AthlonXP: 3095 case CK_AthlonMP: 3096 setFeatureEnabledImpl(Features, "sse", true); 3097 setFeatureEnabledImpl(Features, "3dnowa", true); 3098 setFeatureEnabledImpl(Features, "fxsr", true); 3099 break; 3100 case CK_K8: 3101 case CK_Opteron: 3102 case CK_Athlon64: 3103 case CK_AthlonFX: 3104 setFeatureEnabledImpl(Features, "sse2", true); 3105 setFeatureEnabledImpl(Features, "3dnowa", true); 3106 setFeatureEnabledImpl(Features, "fxsr", true); 3107 break; 3108 case CK_AMDFAM10: 3109 setFeatureEnabledImpl(Features, "sse4a", true); 3110 setFeatureEnabledImpl(Features, "lzcnt", true); 3111 setFeatureEnabledImpl(Features, "popcnt", true); 3112 // FALLTHROUGH 3113 case CK_K8SSE3: 3114 case CK_OpteronSSE3: 3115 case CK_Athlon64SSE3: 3116 setFeatureEnabledImpl(Features, "sse3", true); 3117 setFeatureEnabledImpl(Features, "3dnowa", true); 3118 setFeatureEnabledImpl(Features, "fxsr", true); 3119 break; 3120 case CK_BTVER2: 3121 setFeatureEnabledImpl(Features, "avx", true); 3122 setFeatureEnabledImpl(Features, "aes", true); 3123 setFeatureEnabledImpl(Features, "pclmul", true); 3124 setFeatureEnabledImpl(Features, "bmi", true); 3125 setFeatureEnabledImpl(Features, "f16c", true); 3126 setFeatureEnabledImpl(Features, "xsaveopt", true); 3127 // FALLTHROUGH 3128 case CK_BTVER1: 3129 setFeatureEnabledImpl(Features, "ssse3", true); 3130 setFeatureEnabledImpl(Features, "sse4a", true); 3131 setFeatureEnabledImpl(Features, "lzcnt", true); 3132 setFeatureEnabledImpl(Features, "popcnt", true); 3133 setFeatureEnabledImpl(Features, "prfchw", true); 3134 setFeatureEnabledImpl(Features, "cx16", true); 3135 setFeatureEnabledImpl(Features, "fxsr", true); 3136 break; 3137 case CK_BDVER4: 3138 setFeatureEnabledImpl(Features, "avx2", true); 3139 setFeatureEnabledImpl(Features, "bmi2", true); 3140 setFeatureEnabledImpl(Features, "mwaitx", true); 3141 // FALLTHROUGH 3142 case CK_BDVER3: 3143 setFeatureEnabledImpl(Features, "fsgsbase", true); 3144 setFeatureEnabledImpl(Features, "xsaveopt", true); 3145 // FALLTHROUGH 3146 case CK_BDVER2: 3147 setFeatureEnabledImpl(Features, "bmi", true); 3148 setFeatureEnabledImpl(Features, "fma", true); 3149 setFeatureEnabledImpl(Features, "f16c", true); 3150 setFeatureEnabledImpl(Features, "tbm", true); 3151 // FALLTHROUGH 3152 case CK_BDVER1: 3153 // xop implies avx, sse4a and fma4. 3154 setFeatureEnabledImpl(Features, "xop", true); 3155 setFeatureEnabledImpl(Features, "lzcnt", true); 3156 setFeatureEnabledImpl(Features, "aes", true); 3157 setFeatureEnabledImpl(Features, "pclmul", true); 3158 setFeatureEnabledImpl(Features, "prfchw", true); 3159 setFeatureEnabledImpl(Features, "cx16", true); 3160 setFeatureEnabledImpl(Features, "fxsr", true); 3161 setFeatureEnabledImpl(Features, "xsave", true); 3162 break; 3163 } 3164 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3165 return false; 3166 3167 // Can't do this earlier because we need to be able to explicitly enable 3168 // or disable these features and the things that they depend upon. 3169 3170 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3171 auto I = Features.find("sse4.2"); 3172 if (I != Features.end() && I->getValue() && 3173 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3174 FeaturesVec.end()) 3175 Features["popcnt"] = true; 3176 3177 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3178 I = Features.find("3dnow"); 3179 if (I != Features.end() && I->getValue() && 3180 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3181 FeaturesVec.end()) 3182 Features["prfchw"] = true; 3183 3184 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3185 // then enable MMX. 3186 I = Features.find("sse"); 3187 if (I != Features.end() && I->getValue() && 3188 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3189 FeaturesVec.end()) 3190 Features["mmx"] = true; 3191 3192 return true; 3193 } 3194 3195 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3196 X86SSEEnum Level, bool Enabled) { 3197 if (Enabled) { 3198 switch (Level) { 3199 case AVX512F: 3200 Features["avx512f"] = true; 3201 case AVX2: 3202 Features["avx2"] = true; 3203 case AVX: 3204 Features["avx"] = true; 3205 Features["xsave"] = true; 3206 case SSE42: 3207 Features["sse4.2"] = true; 3208 case SSE41: 3209 Features["sse4.1"] = true; 3210 case SSSE3: 3211 Features["ssse3"] = true; 3212 case SSE3: 3213 Features["sse3"] = true; 3214 case SSE2: 3215 Features["sse2"] = true; 3216 case SSE1: 3217 Features["sse"] = true; 3218 case NoSSE: 3219 break; 3220 } 3221 return; 3222 } 3223 3224 switch (Level) { 3225 case NoSSE: 3226 case SSE1: 3227 Features["sse"] = false; 3228 case SSE2: 3229 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3230 Features["sha"] = false; 3231 case SSE3: 3232 Features["sse3"] = false; 3233 setXOPLevel(Features, NoXOP, false); 3234 case SSSE3: 3235 Features["ssse3"] = false; 3236 case SSE41: 3237 Features["sse4.1"] = false; 3238 case SSE42: 3239 Features["sse4.2"] = false; 3240 case AVX: 3241 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3242 Features["xsaveopt"] = false; 3243 setXOPLevel(Features, FMA4, false); 3244 case AVX2: 3245 Features["avx2"] = false; 3246 case AVX512F: 3247 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3248 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3249 Features["avx512vl"] = Features["avx512vbmi"] = 3250 Features["avx512ifma"] = false; 3251 } 3252 } 3253 3254 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3255 MMX3DNowEnum Level, bool Enabled) { 3256 if (Enabled) { 3257 switch (Level) { 3258 case AMD3DNowAthlon: 3259 Features["3dnowa"] = true; 3260 case AMD3DNow: 3261 Features["3dnow"] = true; 3262 case MMX: 3263 Features["mmx"] = true; 3264 case NoMMX3DNow: 3265 break; 3266 } 3267 return; 3268 } 3269 3270 switch (Level) { 3271 case NoMMX3DNow: 3272 case MMX: 3273 Features["mmx"] = false; 3274 case AMD3DNow: 3275 Features["3dnow"] = false; 3276 case AMD3DNowAthlon: 3277 Features["3dnowa"] = false; 3278 } 3279 } 3280 3281 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3282 bool Enabled) { 3283 if (Enabled) { 3284 switch (Level) { 3285 case XOP: 3286 Features["xop"] = true; 3287 case FMA4: 3288 Features["fma4"] = true; 3289 setSSELevel(Features, AVX, true); 3290 case SSE4A: 3291 Features["sse4a"] = true; 3292 setSSELevel(Features, SSE3, true); 3293 case NoXOP: 3294 break; 3295 } 3296 return; 3297 } 3298 3299 switch (Level) { 3300 case NoXOP: 3301 case SSE4A: 3302 Features["sse4a"] = false; 3303 case FMA4: 3304 Features["fma4"] = false; 3305 case XOP: 3306 Features["xop"] = false; 3307 } 3308 } 3309 3310 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3311 StringRef Name, bool Enabled) { 3312 // This is a bit of a hack to deal with the sse4 target feature when used 3313 // as part of the target attribute. We handle sse4 correctly everywhere 3314 // else. See below for more information on how we handle the sse4 options. 3315 if (Name != "sse4") 3316 Features[Name] = Enabled; 3317 3318 if (Name == "mmx") { 3319 setMMXLevel(Features, MMX, Enabled); 3320 } else if (Name == "sse") { 3321 setSSELevel(Features, SSE1, Enabled); 3322 } else if (Name == "sse2") { 3323 setSSELevel(Features, SSE2, Enabled); 3324 } else if (Name == "sse3") { 3325 setSSELevel(Features, SSE3, Enabled); 3326 } else if (Name == "ssse3") { 3327 setSSELevel(Features, SSSE3, Enabled); 3328 } else if (Name == "sse4.2") { 3329 setSSELevel(Features, SSE42, Enabled); 3330 } else if (Name == "sse4.1") { 3331 setSSELevel(Features, SSE41, Enabled); 3332 } else if (Name == "3dnow") { 3333 setMMXLevel(Features, AMD3DNow, Enabled); 3334 } else if (Name == "3dnowa") { 3335 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3336 } else if (Name == "aes") { 3337 if (Enabled) 3338 setSSELevel(Features, SSE2, Enabled); 3339 } else if (Name == "pclmul") { 3340 if (Enabled) 3341 setSSELevel(Features, SSE2, Enabled); 3342 } else if (Name == "avx") { 3343 setSSELevel(Features, AVX, Enabled); 3344 } else if (Name == "avx2") { 3345 setSSELevel(Features, AVX2, Enabled); 3346 } else if (Name == "avx512f") { 3347 setSSELevel(Features, AVX512F, Enabled); 3348 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3349 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3350 Name == "avx512vbmi" || Name == "avx512ifma") { 3351 if (Enabled) 3352 setSSELevel(Features, AVX512F, Enabled); 3353 } else if (Name == "fma") { 3354 if (Enabled) 3355 setSSELevel(Features, AVX, Enabled); 3356 } else if (Name == "fma4") { 3357 setXOPLevel(Features, FMA4, Enabled); 3358 } else if (Name == "xop") { 3359 setXOPLevel(Features, XOP, Enabled); 3360 } else if (Name == "sse4a") { 3361 setXOPLevel(Features, SSE4A, Enabled); 3362 } else if (Name == "f16c") { 3363 if (Enabled) 3364 setSSELevel(Features, AVX, Enabled); 3365 } else if (Name == "sha") { 3366 if (Enabled) 3367 setSSELevel(Features, SSE2, Enabled); 3368 } else if (Name == "sse4") { 3369 // We can get here via the __target__ attribute since that's not controlled 3370 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3371 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3372 // disabled. 3373 if (Enabled) 3374 setSSELevel(Features, SSE42, Enabled); 3375 else 3376 setSSELevel(Features, SSE41, Enabled); 3377 } else if (Name == "xsave") { 3378 if (!Enabled) 3379 Features["xsaveopt"] = false; 3380 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3381 if (Enabled) 3382 Features["xsave"] = true; 3383 } 3384 } 3385 3386 /// handleTargetFeatures - Perform initialization based on the user 3387 /// configured set of features. 3388 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3389 DiagnosticsEngine &Diags) { 3390 for (const auto &Feature : Features) { 3391 if (Feature[0] != '+') 3392 continue; 3393 3394 if (Feature == "+aes") { 3395 HasAES = true; 3396 } else if (Feature == "+pclmul") { 3397 HasPCLMUL = true; 3398 } else if (Feature == "+lzcnt") { 3399 HasLZCNT = true; 3400 } else if (Feature == "+rdrnd") { 3401 HasRDRND = true; 3402 } else if (Feature == "+fsgsbase") { 3403 HasFSGSBASE = true; 3404 } else if (Feature == "+bmi") { 3405 HasBMI = true; 3406 } else if (Feature == "+bmi2") { 3407 HasBMI2 = true; 3408 } else if (Feature == "+popcnt") { 3409 HasPOPCNT = true; 3410 } else if (Feature == "+rtm") { 3411 HasRTM = true; 3412 } else if (Feature == "+prfchw") { 3413 HasPRFCHW = true; 3414 } else if (Feature == "+rdseed") { 3415 HasRDSEED = true; 3416 } else if (Feature == "+adx") { 3417 HasADX = true; 3418 } else if (Feature == "+tbm") { 3419 HasTBM = true; 3420 } else if (Feature == "+fma") { 3421 HasFMA = true; 3422 } else if (Feature == "+f16c") { 3423 HasF16C = true; 3424 } else if (Feature == "+avx512cd") { 3425 HasAVX512CD = true; 3426 } else if (Feature == "+avx512er") { 3427 HasAVX512ER = true; 3428 } else if (Feature == "+avx512pf") { 3429 HasAVX512PF = true; 3430 } else if (Feature == "+avx512dq") { 3431 HasAVX512DQ = true; 3432 } else if (Feature == "+avx512bw") { 3433 HasAVX512BW = true; 3434 } else if (Feature == "+avx512vl") { 3435 HasAVX512VL = true; 3436 } else if (Feature == "+avx512vbmi") { 3437 HasAVX512VBMI = true; 3438 } else if (Feature == "+avx512ifma") { 3439 HasAVX512IFMA = true; 3440 } else if (Feature == "+sha") { 3441 HasSHA = true; 3442 } else if (Feature == "+mpx") { 3443 HasMPX = true; 3444 } else if (Feature == "+movbe") { 3445 HasMOVBE = true; 3446 } else if (Feature == "+sgx") { 3447 HasSGX = true; 3448 } else if (Feature == "+cx16") { 3449 HasCX16 = true; 3450 } else if (Feature == "+fxsr") { 3451 HasFXSR = true; 3452 } else if (Feature == "+xsave") { 3453 HasXSAVE = true; 3454 } else if (Feature == "+xsaveopt") { 3455 HasXSAVEOPT = true; 3456 } else if (Feature == "+xsavec") { 3457 HasXSAVEC = true; 3458 } else if (Feature == "+xsaves") { 3459 HasXSAVES = true; 3460 } else if (Feature == "+mwaitx") { 3461 HasMWAITX = true; 3462 } else if (Feature == "+pku") { 3463 HasPKU = true; 3464 } else if (Feature == "+clflushopt") { 3465 HasCLFLUSHOPT = true; 3466 } else if (Feature == "+pcommit") { 3467 HasPCOMMIT = true; 3468 } else if (Feature == "+clwb") { 3469 HasCLWB = true; 3470 } else if (Feature == "+umip") { 3471 HasUMIP = true; 3472 } else if (Feature == "+prefetchwt1") { 3473 HasPREFETCHWT1 = true; 3474 } 3475 3476 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3477 .Case("+avx512f", AVX512F) 3478 .Case("+avx2", AVX2) 3479 .Case("+avx", AVX) 3480 .Case("+sse4.2", SSE42) 3481 .Case("+sse4.1", SSE41) 3482 .Case("+ssse3", SSSE3) 3483 .Case("+sse3", SSE3) 3484 .Case("+sse2", SSE2) 3485 .Case("+sse", SSE1) 3486 .Default(NoSSE); 3487 SSELevel = std::max(SSELevel, Level); 3488 3489 MMX3DNowEnum ThreeDNowLevel = 3490 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3491 .Case("+3dnowa", AMD3DNowAthlon) 3492 .Case("+3dnow", AMD3DNow) 3493 .Case("+mmx", MMX) 3494 .Default(NoMMX3DNow); 3495 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3496 3497 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3498 .Case("+xop", XOP) 3499 .Case("+fma4", FMA4) 3500 .Case("+sse4a", SSE4A) 3501 .Default(NoXOP); 3502 XOPLevel = std::max(XOPLevel, XLevel); 3503 } 3504 3505 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3506 // matches the selected sse level. 3507 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3508 (FPMath == FP_387 && SSELevel >= SSE1)) { 3509 Diags.Report(diag::err_target_unsupported_fpmath) << 3510 (FPMath == FP_SSE ? "sse" : "387"); 3511 return false; 3512 } 3513 3514 SimdDefaultAlign = 3515 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3516 return true; 3517 } 3518 3519 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3520 /// definitions for this particular subtarget. 3521 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3522 MacroBuilder &Builder) const { 3523 // Target identification. 3524 if (getTriple().getArch() == llvm::Triple::x86_64) { 3525 Builder.defineMacro("__amd64__"); 3526 Builder.defineMacro("__amd64"); 3527 Builder.defineMacro("__x86_64"); 3528 Builder.defineMacro("__x86_64__"); 3529 if (getTriple().getArchName() == "x86_64h") { 3530 Builder.defineMacro("__x86_64h"); 3531 Builder.defineMacro("__x86_64h__"); 3532 } 3533 } else { 3534 DefineStd(Builder, "i386", Opts); 3535 } 3536 3537 // Subtarget options. 3538 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3539 // truly should be based on -mtune options. 3540 switch (CPU) { 3541 case CK_Generic: 3542 break; 3543 case CK_i386: 3544 // The rest are coming from the i386 define above. 3545 Builder.defineMacro("__tune_i386__"); 3546 break; 3547 case CK_i486: 3548 case CK_WinChipC6: 3549 case CK_WinChip2: 3550 case CK_C3: 3551 defineCPUMacros(Builder, "i486"); 3552 break; 3553 case CK_PentiumMMX: 3554 Builder.defineMacro("__pentium_mmx__"); 3555 Builder.defineMacro("__tune_pentium_mmx__"); 3556 // Fallthrough 3557 case CK_i586: 3558 case CK_Pentium: 3559 defineCPUMacros(Builder, "i586"); 3560 defineCPUMacros(Builder, "pentium"); 3561 break; 3562 case CK_Pentium3: 3563 case CK_Pentium3M: 3564 case CK_PentiumM: 3565 Builder.defineMacro("__tune_pentium3__"); 3566 // Fallthrough 3567 case CK_Pentium2: 3568 case CK_C3_2: 3569 Builder.defineMacro("__tune_pentium2__"); 3570 // Fallthrough 3571 case CK_PentiumPro: 3572 Builder.defineMacro("__tune_i686__"); 3573 Builder.defineMacro("__tune_pentiumpro__"); 3574 // Fallthrough 3575 case CK_i686: 3576 Builder.defineMacro("__i686"); 3577 Builder.defineMacro("__i686__"); 3578 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3579 Builder.defineMacro("__pentiumpro"); 3580 Builder.defineMacro("__pentiumpro__"); 3581 break; 3582 case CK_Pentium4: 3583 case CK_Pentium4M: 3584 defineCPUMacros(Builder, "pentium4"); 3585 break; 3586 case CK_Yonah: 3587 case CK_Prescott: 3588 case CK_Nocona: 3589 defineCPUMacros(Builder, "nocona"); 3590 break; 3591 case CK_Core2: 3592 case CK_Penryn: 3593 defineCPUMacros(Builder, "core2"); 3594 break; 3595 case CK_Bonnell: 3596 defineCPUMacros(Builder, "atom"); 3597 break; 3598 case CK_Silvermont: 3599 defineCPUMacros(Builder, "slm"); 3600 break; 3601 case CK_Nehalem: 3602 case CK_Westmere: 3603 case CK_SandyBridge: 3604 case CK_IvyBridge: 3605 case CK_Haswell: 3606 case CK_Broadwell: 3607 case CK_SkylakeClient: 3608 // FIXME: Historically, we defined this legacy name, it would be nice to 3609 // remove it at some point. We've never exposed fine-grained names for 3610 // recent primary x86 CPUs, and we should keep it that way. 3611 defineCPUMacros(Builder, "corei7"); 3612 break; 3613 case CK_SkylakeServer: 3614 defineCPUMacros(Builder, "skx"); 3615 break; 3616 case CK_Cannonlake: 3617 break; 3618 case CK_KNL: 3619 defineCPUMacros(Builder, "knl"); 3620 break; 3621 case CK_Lakemont: 3622 Builder.defineMacro("__tune_lakemont__"); 3623 break; 3624 case CK_K6_2: 3625 Builder.defineMacro("__k6_2__"); 3626 Builder.defineMacro("__tune_k6_2__"); 3627 // Fallthrough 3628 case CK_K6_3: 3629 if (CPU != CK_K6_2) { // In case of fallthrough 3630 // FIXME: GCC may be enabling these in cases where some other k6 3631 // architecture is specified but -m3dnow is explicitly provided. The 3632 // exact semantics need to be determined and emulated here. 3633 Builder.defineMacro("__k6_3__"); 3634 Builder.defineMacro("__tune_k6_3__"); 3635 } 3636 // Fallthrough 3637 case CK_K6: 3638 defineCPUMacros(Builder, "k6"); 3639 break; 3640 case CK_Athlon: 3641 case CK_AthlonThunderbird: 3642 case CK_Athlon4: 3643 case CK_AthlonXP: 3644 case CK_AthlonMP: 3645 defineCPUMacros(Builder, "athlon"); 3646 if (SSELevel != NoSSE) { 3647 Builder.defineMacro("__athlon_sse__"); 3648 Builder.defineMacro("__tune_athlon_sse__"); 3649 } 3650 break; 3651 case CK_K8: 3652 case CK_K8SSE3: 3653 case CK_x86_64: 3654 case CK_Opteron: 3655 case CK_OpteronSSE3: 3656 case CK_Athlon64: 3657 case CK_Athlon64SSE3: 3658 case CK_AthlonFX: 3659 defineCPUMacros(Builder, "k8"); 3660 break; 3661 case CK_AMDFAM10: 3662 defineCPUMacros(Builder, "amdfam10"); 3663 break; 3664 case CK_BTVER1: 3665 defineCPUMacros(Builder, "btver1"); 3666 break; 3667 case CK_BTVER2: 3668 defineCPUMacros(Builder, "btver2"); 3669 break; 3670 case CK_BDVER1: 3671 defineCPUMacros(Builder, "bdver1"); 3672 break; 3673 case CK_BDVER2: 3674 defineCPUMacros(Builder, "bdver2"); 3675 break; 3676 case CK_BDVER3: 3677 defineCPUMacros(Builder, "bdver3"); 3678 break; 3679 case CK_BDVER4: 3680 defineCPUMacros(Builder, "bdver4"); 3681 break; 3682 case CK_Geode: 3683 defineCPUMacros(Builder, "geode"); 3684 break; 3685 } 3686 3687 // Target properties. 3688 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3689 3690 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3691 // functions in glibc header files that use FP Stack inline asm which the 3692 // backend can't deal with (PR879). 3693 Builder.defineMacro("__NO_MATH_INLINES"); 3694 3695 if (HasAES) 3696 Builder.defineMacro("__AES__"); 3697 3698 if (HasPCLMUL) 3699 Builder.defineMacro("__PCLMUL__"); 3700 3701 if (HasLZCNT) 3702 Builder.defineMacro("__LZCNT__"); 3703 3704 if (HasRDRND) 3705 Builder.defineMacro("__RDRND__"); 3706 3707 if (HasFSGSBASE) 3708 Builder.defineMacro("__FSGSBASE__"); 3709 3710 if (HasBMI) 3711 Builder.defineMacro("__BMI__"); 3712 3713 if (HasBMI2) 3714 Builder.defineMacro("__BMI2__"); 3715 3716 if (HasPOPCNT) 3717 Builder.defineMacro("__POPCNT__"); 3718 3719 if (HasRTM) 3720 Builder.defineMacro("__RTM__"); 3721 3722 if (HasPRFCHW) 3723 Builder.defineMacro("__PRFCHW__"); 3724 3725 if (HasRDSEED) 3726 Builder.defineMacro("__RDSEED__"); 3727 3728 if (HasADX) 3729 Builder.defineMacro("__ADX__"); 3730 3731 if (HasTBM) 3732 Builder.defineMacro("__TBM__"); 3733 3734 if (HasMWAITX) 3735 Builder.defineMacro("__MWAITX__"); 3736 3737 switch (XOPLevel) { 3738 case XOP: 3739 Builder.defineMacro("__XOP__"); 3740 case FMA4: 3741 Builder.defineMacro("__FMA4__"); 3742 case SSE4A: 3743 Builder.defineMacro("__SSE4A__"); 3744 case NoXOP: 3745 break; 3746 } 3747 3748 if (HasFMA) 3749 Builder.defineMacro("__FMA__"); 3750 3751 if (HasF16C) 3752 Builder.defineMacro("__F16C__"); 3753 3754 if (HasAVX512CD) 3755 Builder.defineMacro("__AVX512CD__"); 3756 if (HasAVX512ER) 3757 Builder.defineMacro("__AVX512ER__"); 3758 if (HasAVX512PF) 3759 Builder.defineMacro("__AVX512PF__"); 3760 if (HasAVX512DQ) 3761 Builder.defineMacro("__AVX512DQ__"); 3762 if (HasAVX512BW) 3763 Builder.defineMacro("__AVX512BW__"); 3764 if (HasAVX512VL) 3765 Builder.defineMacro("__AVX512VL__"); 3766 if (HasAVX512VBMI) 3767 Builder.defineMacro("__AVX512VBMI__"); 3768 if (HasAVX512IFMA) 3769 Builder.defineMacro("__AVX512IFMA__"); 3770 3771 if (HasSHA) 3772 Builder.defineMacro("__SHA__"); 3773 3774 if (HasFXSR) 3775 Builder.defineMacro("__FXSR__"); 3776 if (HasXSAVE) 3777 Builder.defineMacro("__XSAVE__"); 3778 if (HasXSAVEOPT) 3779 Builder.defineMacro("__XSAVEOPT__"); 3780 if (HasXSAVEC) 3781 Builder.defineMacro("__XSAVEC__"); 3782 if (HasXSAVES) 3783 Builder.defineMacro("__XSAVES__"); 3784 if (HasPKU) 3785 Builder.defineMacro("__PKU__"); 3786 if (HasCX16) 3787 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3788 3789 // Each case falls through to the previous one here. 3790 switch (SSELevel) { 3791 case AVX512F: 3792 Builder.defineMacro("__AVX512F__"); 3793 case AVX2: 3794 Builder.defineMacro("__AVX2__"); 3795 case AVX: 3796 Builder.defineMacro("__AVX__"); 3797 case SSE42: 3798 Builder.defineMacro("__SSE4_2__"); 3799 case SSE41: 3800 Builder.defineMacro("__SSE4_1__"); 3801 case SSSE3: 3802 Builder.defineMacro("__SSSE3__"); 3803 case SSE3: 3804 Builder.defineMacro("__SSE3__"); 3805 case SSE2: 3806 Builder.defineMacro("__SSE2__"); 3807 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3808 case SSE1: 3809 Builder.defineMacro("__SSE__"); 3810 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3811 case NoSSE: 3812 break; 3813 } 3814 3815 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3816 switch (SSELevel) { 3817 case AVX512F: 3818 case AVX2: 3819 case AVX: 3820 case SSE42: 3821 case SSE41: 3822 case SSSE3: 3823 case SSE3: 3824 case SSE2: 3825 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3826 break; 3827 case SSE1: 3828 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3829 break; 3830 default: 3831 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3832 } 3833 } 3834 3835 // Each case falls through to the previous one here. 3836 switch (MMX3DNowLevel) { 3837 case AMD3DNowAthlon: 3838 Builder.defineMacro("__3dNOW_A__"); 3839 case AMD3DNow: 3840 Builder.defineMacro("__3dNOW__"); 3841 case MMX: 3842 Builder.defineMacro("__MMX__"); 3843 case NoMMX3DNow: 3844 break; 3845 } 3846 3847 if (CPU >= CK_i486) { 3848 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3849 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3850 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3851 } 3852 if (CPU >= CK_i586) 3853 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3854 } 3855 3856 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3857 return llvm::StringSwitch<bool>(Feature) 3858 .Case("aes", HasAES) 3859 .Case("avx", SSELevel >= AVX) 3860 .Case("avx2", SSELevel >= AVX2) 3861 .Case("avx512f", SSELevel >= AVX512F) 3862 .Case("avx512cd", HasAVX512CD) 3863 .Case("avx512er", HasAVX512ER) 3864 .Case("avx512pf", HasAVX512PF) 3865 .Case("avx512dq", HasAVX512DQ) 3866 .Case("avx512bw", HasAVX512BW) 3867 .Case("avx512vl", HasAVX512VL) 3868 .Case("avx512vbmi", HasAVX512VBMI) 3869 .Case("avx512ifma", HasAVX512IFMA) 3870 .Case("bmi", HasBMI) 3871 .Case("bmi2", HasBMI2) 3872 .Case("clflushopt", HasCLFLUSHOPT) 3873 .Case("clwb", HasCLWB) 3874 .Case("cx16", HasCX16) 3875 .Case("f16c", HasF16C) 3876 .Case("fma", HasFMA) 3877 .Case("fma4", XOPLevel >= FMA4) 3878 .Case("fsgsbase", HasFSGSBASE) 3879 .Case("fxsr", HasFXSR) 3880 .Case("lzcnt", HasLZCNT) 3881 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3882 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3883 .Case("mmx", MMX3DNowLevel >= MMX) 3884 .Case("movbe", HasMOVBE) 3885 .Case("mpx", HasMPX) 3886 .Case("pclmul", HasPCLMUL) 3887 .Case("pcommit", HasPCOMMIT) 3888 .Case("pku", HasPKU) 3889 .Case("popcnt", HasPOPCNT) 3890 .Case("prefetchwt1", HasPREFETCHWT1) 3891 .Case("prfchw", HasPRFCHW) 3892 .Case("rdrnd", HasRDRND) 3893 .Case("rdseed", HasRDSEED) 3894 .Case("rtm", HasRTM) 3895 .Case("sgx", HasSGX) 3896 .Case("sha", HasSHA) 3897 .Case("sse", SSELevel >= SSE1) 3898 .Case("sse2", SSELevel >= SSE2) 3899 .Case("sse3", SSELevel >= SSE3) 3900 .Case("ssse3", SSELevel >= SSSE3) 3901 .Case("sse4.1", SSELevel >= SSE41) 3902 .Case("sse4.2", SSELevel >= SSE42) 3903 .Case("sse4a", XOPLevel >= SSE4A) 3904 .Case("tbm", HasTBM) 3905 .Case("umip", HasUMIP) 3906 .Case("x86", true) 3907 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3908 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3909 .Case("xop", XOPLevel >= XOP) 3910 .Case("xsave", HasXSAVE) 3911 .Case("xsavec", HasXSAVEC) 3912 .Case("xsaves", HasXSAVES) 3913 .Case("xsaveopt", HasXSAVEOPT) 3914 .Default(false); 3915 } 3916 3917 // We can't use a generic validation scheme for the features accepted here 3918 // versus subtarget features accepted in the target attribute because the 3919 // bitfield structure that's initialized in the runtime only supports the 3920 // below currently rather than the full range of subtarget features. (See 3921 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3922 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3923 return llvm::StringSwitch<bool>(FeatureStr) 3924 .Case("cmov", true) 3925 .Case("mmx", true) 3926 .Case("popcnt", true) 3927 .Case("sse", true) 3928 .Case("sse2", true) 3929 .Case("sse3", true) 3930 .Case("ssse3", true) 3931 .Case("sse4.1", true) 3932 .Case("sse4.2", true) 3933 .Case("avx", true) 3934 .Case("avx2", true) 3935 .Case("sse4a", true) 3936 .Case("fma4", true) 3937 .Case("xop", true) 3938 .Case("fma", true) 3939 .Case("avx512f", true) 3940 .Case("bmi", true) 3941 .Case("bmi2", true) 3942 .Case("aes", true) 3943 .Case("pclmul", true) 3944 .Case("avx512vl", true) 3945 .Case("avx512bw", true) 3946 .Case("avx512dq", true) 3947 .Case("avx512cd", true) 3948 .Case("avx512er", true) 3949 .Case("avx512pf", true) 3950 .Case("avx512vbmi", true) 3951 .Case("avx512ifma", true) 3952 .Default(false); 3953 } 3954 3955 bool 3956 X86TargetInfo::validateAsmConstraint(const char *&Name, 3957 TargetInfo::ConstraintInfo &Info) const { 3958 switch (*Name) { 3959 default: return false; 3960 // Constant constraints. 3961 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3962 // instructions. 3963 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3964 // x86_64 instructions. 3965 case 's': 3966 Info.setRequiresImmediate(); 3967 return true; 3968 case 'I': 3969 Info.setRequiresImmediate(0, 31); 3970 return true; 3971 case 'J': 3972 Info.setRequiresImmediate(0, 63); 3973 return true; 3974 case 'K': 3975 Info.setRequiresImmediate(-128, 127); 3976 return true; 3977 case 'L': 3978 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3979 return true; 3980 case 'M': 3981 Info.setRequiresImmediate(0, 3); 3982 return true; 3983 case 'N': 3984 Info.setRequiresImmediate(0, 255); 3985 return true; 3986 case 'O': 3987 Info.setRequiresImmediate(0, 127); 3988 return true; 3989 // Register constraints. 3990 case 'Y': // 'Y' is the first character for several 2-character constraints. 3991 // Shift the pointer to the second character of the constraint. 3992 Name++; 3993 switch (*Name) { 3994 default: 3995 return false; 3996 case '0': // First SSE register. 3997 case 't': // Any SSE register, when SSE2 is enabled. 3998 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3999 case 'm': // Any MMX register, when inter-unit moves enabled. 4000 case 'k': // AVX512 arch mask registers: k1-k7. 4001 Info.setAllowsRegister(); 4002 return true; 4003 } 4004 case 'f': // Any x87 floating point stack register. 4005 // Constraint 'f' cannot be used for output operands. 4006 if (Info.ConstraintStr[0] == '=') 4007 return false; 4008 Info.setAllowsRegister(); 4009 return true; 4010 case 'a': // eax. 4011 case 'b': // ebx. 4012 case 'c': // ecx. 4013 case 'd': // edx. 4014 case 'S': // esi. 4015 case 'D': // edi. 4016 case 'A': // edx:eax. 4017 case 't': // Top of floating point stack. 4018 case 'u': // Second from top of floating point stack. 4019 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4020 case 'y': // Any MMX register. 4021 case 'x': // Any SSE register. 4022 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4023 // for intermideate k reg operations). 4024 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4025 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4026 case 'l': // "Index" registers: any general register that can be used as an 4027 // index in a base+index memory access. 4028 Info.setAllowsRegister(); 4029 return true; 4030 // Floating point constant constraints. 4031 case 'C': // SSE floating point constant. 4032 case 'G': // x87 floating point constant. 4033 return true; 4034 } 4035 } 4036 4037 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4038 unsigned Size) const { 4039 // Strip off constraint modifiers. 4040 while (Constraint[0] == '=' || 4041 Constraint[0] == '+' || 4042 Constraint[0] == '&') 4043 Constraint = Constraint.substr(1); 4044 4045 return validateOperandSize(Constraint, Size); 4046 } 4047 4048 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4049 unsigned Size) const { 4050 return validateOperandSize(Constraint, Size); 4051 } 4052 4053 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4054 unsigned Size) const { 4055 switch (Constraint[0]) { 4056 default: break; 4057 case 'k': 4058 // Registers k0-k7 (AVX512) size limit is 64 bit. 4059 case 'y': 4060 return Size <= 64; 4061 case 'f': 4062 case 't': 4063 case 'u': 4064 return Size <= 128; 4065 case 'x': 4066 if (SSELevel >= AVX512F) 4067 // 512-bit zmm registers can be used if target supports AVX512F. 4068 return Size <= 512U; 4069 else if (SSELevel >= AVX) 4070 // 256-bit ymm registers can be used if target supports AVX. 4071 return Size <= 256U; 4072 return Size <= 128U; 4073 case 'Y': 4074 // 'Y' is the first character for several 2-character constraints. 4075 switch (Constraint[1]) { 4076 default: break; 4077 case 'm': 4078 // 'Ym' is synonymous with 'y'. 4079 case 'k': 4080 return Size <= 64; 4081 case 'i': 4082 case 't': 4083 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4084 if (SSELevel >= AVX512F) 4085 return Size <= 512U; 4086 else if (SSELevel >= AVX) 4087 return Size <= 256U; 4088 return SSELevel >= SSE2 && Size <= 128U; 4089 } 4090 4091 } 4092 4093 return true; 4094 } 4095 4096 std::string 4097 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4098 switch (*Constraint) { 4099 case 'a': return std::string("{ax}"); 4100 case 'b': return std::string("{bx}"); 4101 case 'c': return std::string("{cx}"); 4102 case 'd': return std::string("{dx}"); 4103 case 'S': return std::string("{si}"); 4104 case 'D': return std::string("{di}"); 4105 case 'p': // address 4106 return std::string("im"); 4107 case 't': // top of floating point stack. 4108 return std::string("{st}"); 4109 case 'u': // second from top of floating point stack. 4110 return std::string("{st(1)}"); // second from top of floating point stack. 4111 case 'Y': 4112 switch (Constraint[1]) { 4113 default: 4114 // Break from inner switch and fall through (copy single char), 4115 // continue parsing after copying the current constraint into 4116 // the return string. 4117 break; 4118 case 'k': 4119 // "^" hints llvm that this is a 2 letter constraint. 4120 // "Constraint++" is used to promote the string iterator 4121 // to the next constraint. 4122 return std::string("^") + std::string(Constraint++, 2); 4123 } 4124 LLVM_FALLTHROUGH; 4125 default: 4126 return std::string(1, *Constraint); 4127 } 4128 } 4129 4130 // X86-32 generic target 4131 class X86_32TargetInfo : public X86TargetInfo { 4132 public: 4133 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4134 : X86TargetInfo(Triple, Opts) { 4135 DoubleAlign = LongLongAlign = 32; 4136 LongDoubleWidth = 96; 4137 LongDoubleAlign = 32; 4138 SuitableAlign = 128; 4139 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4140 SizeType = UnsignedInt; 4141 PtrDiffType = SignedInt; 4142 IntPtrType = SignedInt; 4143 RegParmMax = 3; 4144 4145 // Use fpret for all types. 4146 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4147 (1 << TargetInfo::Double) | 4148 (1 << TargetInfo::LongDouble)); 4149 4150 // x86-32 has atomics up to 8 bytes 4151 // FIXME: Check that we actually have cmpxchg8b before setting 4152 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4153 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4154 } 4155 BuiltinVaListKind getBuiltinVaListKind() const override { 4156 return TargetInfo::CharPtrBuiltinVaList; 4157 } 4158 4159 int getEHDataRegisterNumber(unsigned RegNo) const override { 4160 if (RegNo == 0) return 0; 4161 if (RegNo == 1) return 2; 4162 return -1; 4163 } 4164 bool validateOperandSize(StringRef Constraint, 4165 unsigned Size) const override { 4166 switch (Constraint[0]) { 4167 default: break; 4168 case 'R': 4169 case 'q': 4170 case 'Q': 4171 case 'a': 4172 case 'b': 4173 case 'c': 4174 case 'd': 4175 case 'S': 4176 case 'D': 4177 return Size <= 32; 4178 case 'A': 4179 return Size <= 64; 4180 } 4181 4182 return X86TargetInfo::validateOperandSize(Constraint, Size); 4183 } 4184 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4185 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4186 Builtin::FirstTSBuiltin + 1); 4187 } 4188 }; 4189 4190 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4191 public: 4192 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4193 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4194 4195 unsigned getFloatEvalMethod() const override { 4196 unsigned Major, Minor, Micro; 4197 getTriple().getOSVersion(Major, Minor, Micro); 4198 // New NetBSD uses the default rounding mode. 4199 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4200 return X86_32TargetInfo::getFloatEvalMethod(); 4201 // NetBSD before 6.99.26 defaults to "double" rounding. 4202 return 1; 4203 } 4204 }; 4205 4206 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4207 public: 4208 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4209 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4210 SizeType = UnsignedLong; 4211 IntPtrType = SignedLong; 4212 PtrDiffType = SignedLong; 4213 } 4214 }; 4215 4216 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4217 public: 4218 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4219 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4220 SizeType = UnsignedLong; 4221 IntPtrType = SignedLong; 4222 PtrDiffType = SignedLong; 4223 } 4224 }; 4225 4226 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4227 public: 4228 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4229 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4230 LongDoubleWidth = 128; 4231 LongDoubleAlign = 128; 4232 SuitableAlign = 128; 4233 MaxVectorAlign = 256; 4234 // The watchOS simulator uses the builtin bool type for Objective-C. 4235 llvm::Triple T = llvm::Triple(Triple); 4236 if (T.isWatchOS()) 4237 UseSignedCharForObjCBool = false; 4238 SizeType = UnsignedLong; 4239 IntPtrType = SignedLong; 4240 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4241 HasAlignMac68kSupport = true; 4242 } 4243 4244 bool handleTargetFeatures(std::vector<std::string> &Features, 4245 DiagnosticsEngine &Diags) override { 4246 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4247 Diags)) 4248 return false; 4249 // We now know the features we have: we can decide how to align vectors. 4250 MaxVectorAlign = 4251 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4252 return true; 4253 } 4254 }; 4255 4256 // x86-32 Windows target 4257 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4258 public: 4259 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4260 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4261 WCharType = UnsignedShort; 4262 DoubleAlign = LongLongAlign = 64; 4263 bool IsWinCOFF = 4264 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4265 resetDataLayout(IsWinCOFF 4266 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4267 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4268 } 4269 void getTargetDefines(const LangOptions &Opts, 4270 MacroBuilder &Builder) const override { 4271 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4272 } 4273 }; 4274 4275 // x86-32 Windows Visual Studio target 4276 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4277 public: 4278 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4279 const TargetOptions &Opts) 4280 : WindowsX86_32TargetInfo(Triple, Opts) { 4281 LongDoubleWidth = LongDoubleAlign = 64; 4282 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4283 } 4284 void getTargetDefines(const LangOptions &Opts, 4285 MacroBuilder &Builder) const override { 4286 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4287 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4288 // The value of the following reflects processor type. 4289 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4290 // We lost the original triple, so we use the default. 4291 Builder.defineMacro("_M_IX86", "600"); 4292 } 4293 }; 4294 4295 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4296 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4297 // supports __declspec natively under -fms-extensions, but we define a no-op 4298 // __declspec macro anyway for pre-processor compatibility. 4299 if (Opts.MicrosoftExt) 4300 Builder.defineMacro("__declspec", "__declspec"); 4301 else 4302 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4303 4304 if (!Opts.MicrosoftExt) { 4305 // Provide macros for all the calling convention keywords. Provide both 4306 // single and double underscore prefixed variants. These are available on 4307 // x64 as well as x86, even though they have no effect. 4308 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4309 for (const char *CC : CCs) { 4310 std::string GCCSpelling = "__attribute__((__"; 4311 GCCSpelling += CC; 4312 GCCSpelling += "__))"; 4313 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4314 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4315 } 4316 } 4317 } 4318 4319 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4320 Builder.defineMacro("__MSVCRT__"); 4321 Builder.defineMacro("__MINGW32__"); 4322 addCygMingDefines(Opts, Builder); 4323 } 4324 4325 // x86-32 MinGW target 4326 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4327 public: 4328 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4329 : WindowsX86_32TargetInfo(Triple, Opts) {} 4330 void getTargetDefines(const LangOptions &Opts, 4331 MacroBuilder &Builder) const override { 4332 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4333 DefineStd(Builder, "WIN32", Opts); 4334 DefineStd(Builder, "WINNT", Opts); 4335 Builder.defineMacro("_X86_"); 4336 addMinGWDefines(Opts, Builder); 4337 } 4338 }; 4339 4340 // x86-32 Cygwin target 4341 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4342 public: 4343 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4344 : X86_32TargetInfo(Triple, Opts) { 4345 WCharType = UnsignedShort; 4346 DoubleAlign = LongLongAlign = 64; 4347 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4348 } 4349 void getTargetDefines(const LangOptions &Opts, 4350 MacroBuilder &Builder) const override { 4351 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4352 Builder.defineMacro("_X86_"); 4353 Builder.defineMacro("__CYGWIN__"); 4354 Builder.defineMacro("__CYGWIN32__"); 4355 addCygMingDefines(Opts, Builder); 4356 DefineStd(Builder, "unix", Opts); 4357 if (Opts.CPlusPlus) 4358 Builder.defineMacro("_GNU_SOURCE"); 4359 } 4360 }; 4361 4362 // x86-32 Haiku target 4363 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4364 public: 4365 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4366 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4367 } 4368 void getTargetDefines(const LangOptions &Opts, 4369 MacroBuilder &Builder) const override { 4370 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4371 Builder.defineMacro("__INTEL__"); 4372 } 4373 }; 4374 4375 // X86-32 MCU target 4376 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4377 public: 4378 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4379 : X86_32TargetInfo(Triple, Opts) { 4380 LongDoubleWidth = 64; 4381 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4382 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4383 WIntType = UnsignedInt; 4384 } 4385 4386 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4387 // On MCU we support only C calling convention. 4388 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4389 } 4390 4391 void getTargetDefines(const LangOptions &Opts, 4392 MacroBuilder &Builder) const override { 4393 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4394 Builder.defineMacro("__iamcu"); 4395 Builder.defineMacro("__iamcu__"); 4396 } 4397 4398 bool allowsLargerPreferedTypeAlignment() const override { 4399 return false; 4400 } 4401 }; 4402 4403 // RTEMS Target 4404 template<typename Target> 4405 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4406 protected: 4407 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4408 MacroBuilder &Builder) const override { 4409 // RTEMS defines; list based off of gcc output 4410 4411 Builder.defineMacro("__rtems__"); 4412 Builder.defineMacro("__ELF__"); 4413 } 4414 4415 public: 4416 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4417 : OSTargetInfo<Target>(Triple, Opts) { 4418 switch (Triple.getArch()) { 4419 default: 4420 case llvm::Triple::x86: 4421 // this->MCountName = ".mcount"; 4422 break; 4423 case llvm::Triple::mips: 4424 case llvm::Triple::mipsel: 4425 case llvm::Triple::ppc: 4426 case llvm::Triple::ppc64: 4427 case llvm::Triple::ppc64le: 4428 // this->MCountName = "_mcount"; 4429 break; 4430 case llvm::Triple::arm: 4431 // this->MCountName = "__mcount"; 4432 break; 4433 } 4434 } 4435 }; 4436 4437 // x86-32 RTEMS target 4438 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4439 public: 4440 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4441 : X86_32TargetInfo(Triple, Opts) { 4442 SizeType = UnsignedLong; 4443 IntPtrType = SignedLong; 4444 PtrDiffType = SignedLong; 4445 } 4446 void getTargetDefines(const LangOptions &Opts, 4447 MacroBuilder &Builder) const override { 4448 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4449 Builder.defineMacro("__INTEL__"); 4450 Builder.defineMacro("__rtems__"); 4451 } 4452 }; 4453 4454 // x86-64 generic target 4455 class X86_64TargetInfo : public X86TargetInfo { 4456 public: 4457 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4458 : X86TargetInfo(Triple, Opts) { 4459 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4460 bool IsWinCOFF = 4461 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4462 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4463 LongDoubleWidth = 128; 4464 LongDoubleAlign = 128; 4465 LargeArrayMinWidth = 128; 4466 LargeArrayAlign = 128; 4467 SuitableAlign = 128; 4468 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4469 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4470 IntPtrType = IsX32 ? SignedInt : SignedLong; 4471 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4472 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4473 RegParmMax = 6; 4474 4475 // Pointers are 32-bit in x32. 4476 resetDataLayout(IsX32 4477 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4478 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4479 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4480 4481 // Use fpret only for long double. 4482 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4483 4484 // Use fp2ret for _Complex long double. 4485 ComplexLongDoubleUsesFP2Ret = true; 4486 4487 // Make __builtin_ms_va_list available. 4488 HasBuiltinMSVaList = true; 4489 4490 // x86-64 has atomics up to 16 bytes. 4491 MaxAtomicPromoteWidth = 128; 4492 MaxAtomicInlineWidth = 128; 4493 } 4494 BuiltinVaListKind getBuiltinVaListKind() const override { 4495 return TargetInfo::X86_64ABIBuiltinVaList; 4496 } 4497 4498 int getEHDataRegisterNumber(unsigned RegNo) const override { 4499 if (RegNo == 0) return 0; 4500 if (RegNo == 1) return 1; 4501 return -1; 4502 } 4503 4504 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4505 switch (CC) { 4506 case CC_C: 4507 case CC_Swift: 4508 case CC_X86VectorCall: 4509 case CC_IntelOclBicc: 4510 case CC_X86_64Win64: 4511 case CC_PreserveMost: 4512 case CC_PreserveAll: 4513 return CCCR_OK; 4514 default: 4515 return CCCR_Warning; 4516 } 4517 } 4518 4519 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4520 return CC_C; 4521 } 4522 4523 // for x32 we need it here explicitly 4524 bool hasInt128Type() const override { return true; } 4525 unsigned getUnwindWordWidth() const override { return 64; } 4526 unsigned getRegisterWidth() const override { return 64; } 4527 4528 bool validateGlobalRegisterVariable(StringRef RegName, 4529 unsigned RegSize, 4530 bool &HasSizeMismatch) const override { 4531 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4532 // handle. 4533 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4534 // Check that the register size is 64-bit. 4535 HasSizeMismatch = RegSize != 64; 4536 return true; 4537 } 4538 4539 // Check if the register is a 32-bit register the backend can handle. 4540 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4541 HasSizeMismatch); 4542 } 4543 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4544 return llvm::makeArrayRef(BuiltinInfoX86, 4545 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4546 } 4547 }; 4548 4549 // x86-64 Windows target 4550 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4551 public: 4552 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4553 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4554 WCharType = UnsignedShort; 4555 LongWidth = LongAlign = 32; 4556 DoubleAlign = LongLongAlign = 64; 4557 IntMaxType = SignedLongLong; 4558 Int64Type = SignedLongLong; 4559 SizeType = UnsignedLongLong; 4560 PtrDiffType = SignedLongLong; 4561 IntPtrType = SignedLongLong; 4562 } 4563 4564 void getTargetDefines(const LangOptions &Opts, 4565 MacroBuilder &Builder) const override { 4566 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4567 Builder.defineMacro("_WIN64"); 4568 } 4569 4570 BuiltinVaListKind getBuiltinVaListKind() const override { 4571 return TargetInfo::CharPtrBuiltinVaList; 4572 } 4573 4574 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4575 switch (CC) { 4576 case CC_X86StdCall: 4577 case CC_X86ThisCall: 4578 case CC_X86FastCall: 4579 return CCCR_Ignore; 4580 case CC_C: 4581 case CC_X86VectorCall: 4582 case CC_IntelOclBicc: 4583 case CC_X86_64SysV: 4584 case CC_Swift: 4585 return CCCR_OK; 4586 default: 4587 return CCCR_Warning; 4588 } 4589 } 4590 }; 4591 4592 // x86-64 Windows Visual Studio target 4593 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4594 public: 4595 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4596 const TargetOptions &Opts) 4597 : WindowsX86_64TargetInfo(Triple, Opts) { 4598 LongDoubleWidth = LongDoubleAlign = 64; 4599 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4600 } 4601 void getTargetDefines(const LangOptions &Opts, 4602 MacroBuilder &Builder) const override { 4603 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4604 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4605 Builder.defineMacro("_M_X64", "100"); 4606 Builder.defineMacro("_M_AMD64", "100"); 4607 } 4608 }; 4609 4610 // x86-64 MinGW target 4611 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4612 public: 4613 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4614 : WindowsX86_64TargetInfo(Triple, Opts) { 4615 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4616 // with x86 FP ops. Weird. 4617 LongDoubleWidth = LongDoubleAlign = 128; 4618 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4619 } 4620 4621 void getTargetDefines(const LangOptions &Opts, 4622 MacroBuilder &Builder) const override { 4623 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4624 DefineStd(Builder, "WIN64", Opts); 4625 Builder.defineMacro("__MINGW64__"); 4626 addMinGWDefines(Opts, Builder); 4627 4628 // GCC defines this macro when it is using __gxx_personality_seh0. 4629 if (!Opts.SjLjExceptions) 4630 Builder.defineMacro("__SEH__"); 4631 } 4632 }; 4633 4634 // x86-64 Cygwin target 4635 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4636 public: 4637 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4638 : X86_64TargetInfo(Triple, Opts) { 4639 TLSSupported = false; 4640 WCharType = UnsignedShort; 4641 } 4642 void getTargetDefines(const LangOptions &Opts, 4643 MacroBuilder &Builder) const override { 4644 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4645 Builder.defineMacro("__x86_64__"); 4646 Builder.defineMacro("__CYGWIN__"); 4647 Builder.defineMacro("__CYGWIN64__"); 4648 addCygMingDefines(Opts, Builder); 4649 DefineStd(Builder, "unix", Opts); 4650 if (Opts.CPlusPlus) 4651 Builder.defineMacro("_GNU_SOURCE"); 4652 4653 // GCC defines this macro when it is using __gxx_personality_seh0. 4654 if (!Opts.SjLjExceptions) 4655 Builder.defineMacro("__SEH__"); 4656 } 4657 }; 4658 4659 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4660 public: 4661 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4662 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4663 Int64Type = SignedLongLong; 4664 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4665 llvm::Triple T = llvm::Triple(Triple); 4666 if (T.isiOS()) 4667 UseSignedCharForObjCBool = false; 4668 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4669 } 4670 4671 bool handleTargetFeatures(std::vector<std::string> &Features, 4672 DiagnosticsEngine &Diags) override { 4673 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4674 Diags)) 4675 return false; 4676 // We now know the features we have: we can decide how to align vectors. 4677 MaxVectorAlign = 4678 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4679 return true; 4680 } 4681 }; 4682 4683 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4684 public: 4685 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4686 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4687 IntMaxType = SignedLongLong; 4688 Int64Type = SignedLongLong; 4689 } 4690 }; 4691 4692 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4693 public: 4694 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4695 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4696 IntMaxType = SignedLongLong; 4697 Int64Type = SignedLongLong; 4698 } 4699 }; 4700 4701 class ARMTargetInfo : public TargetInfo { 4702 // Possible FPU choices. 4703 enum FPUMode { 4704 VFP2FPU = (1 << 0), 4705 VFP3FPU = (1 << 1), 4706 VFP4FPU = (1 << 2), 4707 NeonFPU = (1 << 3), 4708 FPARMV8 = (1 << 4) 4709 }; 4710 4711 // Possible HWDiv features. 4712 enum HWDivMode { 4713 HWDivThumb = (1 << 0), 4714 HWDivARM = (1 << 1) 4715 }; 4716 4717 static bool FPUModeIsVFP(FPUMode Mode) { 4718 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4719 } 4720 4721 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4722 static const char * const GCCRegNames[]; 4723 4724 std::string ABI, CPU; 4725 4726 StringRef CPUProfile; 4727 StringRef CPUAttr; 4728 4729 enum { 4730 FP_Default, 4731 FP_VFP, 4732 FP_Neon 4733 } FPMath; 4734 4735 unsigned ArchISA; 4736 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4737 unsigned ArchProfile; 4738 unsigned ArchVersion; 4739 4740 unsigned FPU : 5; 4741 4742 unsigned IsAAPCS : 1; 4743 unsigned HWDiv : 2; 4744 4745 // Initialized via features. 4746 unsigned SoftFloat : 1; 4747 unsigned SoftFloatABI : 1; 4748 4749 unsigned CRC : 1; 4750 unsigned Crypto : 1; 4751 unsigned DSP : 1; 4752 unsigned Unaligned : 1; 4753 4754 enum { 4755 LDREX_B = (1 << 0), /// byte (8-bit) 4756 LDREX_H = (1 << 1), /// half (16-bit) 4757 LDREX_W = (1 << 2), /// word (32-bit) 4758 LDREX_D = (1 << 3), /// double (64-bit) 4759 }; 4760 4761 uint32_t LDREX; 4762 4763 // ACLE 6.5.1 Hardware floating point 4764 enum { 4765 HW_FP_HP = (1 << 1), /// half (16-bit) 4766 HW_FP_SP = (1 << 2), /// single (32-bit) 4767 HW_FP_DP = (1 << 3), /// double (64-bit) 4768 }; 4769 uint32_t HW_FP; 4770 4771 static const Builtin::Info BuiltinInfo[]; 4772 4773 void setABIAAPCS() { 4774 IsAAPCS = true; 4775 4776 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4777 const llvm::Triple &T = getTriple(); 4778 4779 // size_t is unsigned long on MachO-derived environments, NetBSD, 4780 // OpenBSD and Bitrig. 4781 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4782 T.getOS() == llvm::Triple::OpenBSD || 4783 T.getOS() == llvm::Triple::Bitrig) 4784 SizeType = UnsignedLong; 4785 else 4786 SizeType = UnsignedInt; 4787 4788 switch (T.getOS()) { 4789 case llvm::Triple::NetBSD: 4790 case llvm::Triple::OpenBSD: 4791 WCharType = SignedInt; 4792 break; 4793 case llvm::Triple::Win32: 4794 WCharType = UnsignedShort; 4795 break; 4796 case llvm::Triple::Linux: 4797 default: 4798 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4799 WCharType = UnsignedInt; 4800 break; 4801 } 4802 4803 UseBitFieldTypeAlignment = true; 4804 4805 ZeroLengthBitfieldBoundary = 0; 4806 4807 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4808 // so set preferred for small types to 32. 4809 if (T.isOSBinFormatMachO()) { 4810 resetDataLayout(BigEndian 4811 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4812 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4813 } else if (T.isOSWindows()) { 4814 assert(!BigEndian && "Windows on ARM does not support big endian"); 4815 resetDataLayout("e" 4816 "-m:w" 4817 "-p:32:32" 4818 "-i64:64" 4819 "-v128:64:128" 4820 "-a:0:32" 4821 "-n32" 4822 "-S64"); 4823 } else if (T.isOSNaCl()) { 4824 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4825 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 4826 } else { 4827 resetDataLayout(BigEndian 4828 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4829 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 4830 } 4831 4832 // FIXME: Enumerated types are variable width in straight AAPCS. 4833 } 4834 4835 void setABIAPCS(bool IsAAPCS16) { 4836 const llvm::Triple &T = getTriple(); 4837 4838 IsAAPCS = false; 4839 4840 if (IsAAPCS16) 4841 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4842 else 4843 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4844 4845 // size_t is unsigned int on FreeBSD. 4846 if (T.getOS() == llvm::Triple::FreeBSD) 4847 SizeType = UnsignedInt; 4848 else 4849 SizeType = UnsignedLong; 4850 4851 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4852 WCharType = SignedInt; 4853 4854 // Do not respect the alignment of bit-field types when laying out 4855 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4856 UseBitFieldTypeAlignment = false; 4857 4858 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4859 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4860 /// gcc. 4861 ZeroLengthBitfieldBoundary = 32; 4862 4863 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4864 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4865 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 4866 } else if (T.isOSBinFormatMachO()) 4867 resetDataLayout( 4868 BigEndian 4869 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4870 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4871 else 4872 resetDataLayout( 4873 BigEndian 4874 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4875 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 4876 4877 // FIXME: Override "preferred align" for double and long long. 4878 } 4879 4880 void setArchInfo() { 4881 StringRef ArchName = getTriple().getArchName(); 4882 4883 ArchISA = llvm::ARM::parseArchISA(ArchName); 4884 CPU = llvm::ARM::getDefaultCPU(ArchName); 4885 unsigned AK = llvm::ARM::parseArch(ArchName); 4886 if (AK != llvm::ARM::AK_INVALID) 4887 ArchKind = AK; 4888 setArchInfo(ArchKind); 4889 } 4890 4891 void setArchInfo(unsigned Kind) { 4892 StringRef SubArch; 4893 4894 // cache TargetParser info 4895 ArchKind = Kind; 4896 SubArch = llvm::ARM::getSubArch(ArchKind); 4897 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4898 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4899 4900 // cache CPU related strings 4901 CPUAttr = getCPUAttr(); 4902 CPUProfile = getCPUProfile(); 4903 } 4904 4905 void setAtomic() { 4906 // when triple does not specify a sub arch, 4907 // then we are not using inline atomics 4908 bool ShouldUseInlineAtomic = 4909 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4910 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4911 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4912 if (ArchProfile == llvm::ARM::PK_M) { 4913 MaxAtomicPromoteWidth = 32; 4914 if (ShouldUseInlineAtomic) 4915 MaxAtomicInlineWidth = 32; 4916 } 4917 else { 4918 MaxAtomicPromoteWidth = 64; 4919 if (ShouldUseInlineAtomic) 4920 MaxAtomicInlineWidth = 64; 4921 } 4922 } 4923 4924 bool isThumb() const { 4925 return (ArchISA == llvm::ARM::IK_THUMB); 4926 } 4927 4928 bool supportsThumb() const { 4929 return CPUAttr.count('T') || ArchVersion >= 6; 4930 } 4931 4932 bool supportsThumb2() const { 4933 return CPUAttr.equals("6T2") || 4934 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 4935 } 4936 4937 StringRef getCPUAttr() const { 4938 // For most sub-arches, the build attribute CPU name is enough. 4939 // For Cortex variants, it's slightly different. 4940 switch(ArchKind) { 4941 default: 4942 return llvm::ARM::getCPUAttr(ArchKind); 4943 case llvm::ARM::AK_ARMV6M: 4944 return "6M"; 4945 case llvm::ARM::AK_ARMV7S: 4946 return "7S"; 4947 case llvm::ARM::AK_ARMV7A: 4948 return "7A"; 4949 case llvm::ARM::AK_ARMV7R: 4950 return "7R"; 4951 case llvm::ARM::AK_ARMV7M: 4952 return "7M"; 4953 case llvm::ARM::AK_ARMV7EM: 4954 return "7EM"; 4955 case llvm::ARM::AK_ARMV8A: 4956 return "8A"; 4957 case llvm::ARM::AK_ARMV8_1A: 4958 return "8_1A"; 4959 case llvm::ARM::AK_ARMV8_2A: 4960 return "8_2A"; 4961 case llvm::ARM::AK_ARMV8MBaseline: 4962 return "8M_BASE"; 4963 case llvm::ARM::AK_ARMV8MMainline: 4964 return "8M_MAIN"; 4965 case llvm::ARM::AK_ARMV8R: 4966 return "8R"; 4967 } 4968 } 4969 4970 StringRef getCPUProfile() const { 4971 switch(ArchProfile) { 4972 case llvm::ARM::PK_A: 4973 return "A"; 4974 case llvm::ARM::PK_R: 4975 return "R"; 4976 case llvm::ARM::PK_M: 4977 return "M"; 4978 default: 4979 return ""; 4980 } 4981 } 4982 4983 public: 4984 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4985 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 4986 HW_FP(0) { 4987 4988 switch (getTriple().getOS()) { 4989 case llvm::Triple::NetBSD: 4990 case llvm::Triple::OpenBSD: 4991 PtrDiffType = SignedLong; 4992 break; 4993 default: 4994 PtrDiffType = SignedInt; 4995 break; 4996 } 4997 4998 // Cache arch related info. 4999 setArchInfo(); 5000 5001 // {} in inline assembly are neon specifiers, not assembly variant 5002 // specifiers. 5003 NoAsmVariants = true; 5004 5005 // FIXME: This duplicates code from the driver that sets the -target-abi 5006 // option - this code is used if -target-abi isn't passed and should 5007 // be unified in some way. 5008 if (Triple.isOSBinFormatMachO()) { 5009 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5010 // the frontend matches that. 5011 if (Triple.getEnvironment() == llvm::Triple::EABI || 5012 Triple.getOS() == llvm::Triple::UnknownOS || 5013 ArchProfile == llvm::ARM::PK_M) { 5014 setABI("aapcs"); 5015 } else if (Triple.isWatchABI()) { 5016 setABI("aapcs16"); 5017 } else { 5018 setABI("apcs-gnu"); 5019 } 5020 } else if (Triple.isOSWindows()) { 5021 // FIXME: this is invalid for WindowsCE 5022 setABI("aapcs"); 5023 } else { 5024 // Select the default based on the platform. 5025 switch (Triple.getEnvironment()) { 5026 case llvm::Triple::Android: 5027 case llvm::Triple::GNUEABI: 5028 case llvm::Triple::GNUEABIHF: 5029 case llvm::Triple::MuslEABI: 5030 case llvm::Triple::MuslEABIHF: 5031 setABI("aapcs-linux"); 5032 break; 5033 case llvm::Triple::EABIHF: 5034 case llvm::Triple::EABI: 5035 setABI("aapcs"); 5036 break; 5037 case llvm::Triple::GNU: 5038 setABI("apcs-gnu"); 5039 break; 5040 default: 5041 if (Triple.getOS() == llvm::Triple::NetBSD) 5042 setABI("apcs-gnu"); 5043 else 5044 setABI("aapcs"); 5045 break; 5046 } 5047 } 5048 5049 // ARM targets default to using the ARM C++ ABI. 5050 TheCXXABI.set(TargetCXXABI::GenericARM); 5051 5052 // ARM has atomics up to 8 bytes 5053 setAtomic(); 5054 5055 // Do force alignment of members that follow zero length bitfields. If 5056 // the alignment of the zero-length bitfield is greater than the member 5057 // that follows it, `bar', `bar' will be aligned as the type of the 5058 // zero length bitfield. 5059 UseZeroLengthBitfieldAlignment = true; 5060 5061 if (Triple.getOS() == llvm::Triple::Linux || 5062 Triple.getOS() == llvm::Triple::UnknownOS) 5063 this->MCountName = 5064 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5065 } 5066 5067 StringRef getABI() const override { return ABI; } 5068 5069 bool setABI(const std::string &Name) override { 5070 ABI = Name; 5071 5072 // The defaults (above) are for AAPCS, check if we need to change them. 5073 // 5074 // FIXME: We need support for -meabi... we could just mangle it into the 5075 // name. 5076 if (Name == "apcs-gnu" || Name == "aapcs16") { 5077 setABIAPCS(Name == "aapcs16"); 5078 return true; 5079 } 5080 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5081 setABIAAPCS(); 5082 return true; 5083 } 5084 return false; 5085 } 5086 5087 // FIXME: This should be based on Arch attributes, not CPU names. 5088 bool 5089 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5090 StringRef CPU, 5091 const std::vector<std::string> &FeaturesVec) const override { 5092 5093 std::vector<StringRef> TargetFeatures; 5094 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5095 5096 // get default FPU features 5097 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5098 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5099 5100 // get default Extension features 5101 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5102 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5103 5104 for (auto Feature : TargetFeatures) 5105 if (Feature[0] == '+') 5106 Features[Feature.drop_front(1)] = true; 5107 5108 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5109 } 5110 5111 bool handleTargetFeatures(std::vector<std::string> &Features, 5112 DiagnosticsEngine &Diags) override { 5113 FPU = 0; 5114 CRC = 0; 5115 Crypto = 0; 5116 DSP = 0; 5117 Unaligned = 1; 5118 SoftFloat = SoftFloatABI = false; 5119 HWDiv = 0; 5120 5121 // This does not diagnose illegal cases like having both 5122 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5123 uint32_t HW_FP_remove = 0; 5124 for (const auto &Feature : Features) { 5125 if (Feature == "+soft-float") { 5126 SoftFloat = true; 5127 } else if (Feature == "+soft-float-abi") { 5128 SoftFloatABI = true; 5129 } else if (Feature == "+vfp2") { 5130 FPU |= VFP2FPU; 5131 HW_FP |= HW_FP_SP | HW_FP_DP; 5132 } else if (Feature == "+vfp3") { 5133 FPU |= VFP3FPU; 5134 HW_FP |= HW_FP_SP | HW_FP_DP; 5135 } else if (Feature == "+vfp4") { 5136 FPU |= VFP4FPU; 5137 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5138 } else if (Feature == "+fp-armv8") { 5139 FPU |= FPARMV8; 5140 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5141 } else if (Feature == "+neon") { 5142 FPU |= NeonFPU; 5143 HW_FP |= HW_FP_SP | HW_FP_DP; 5144 } else if (Feature == "+hwdiv") { 5145 HWDiv |= HWDivThumb; 5146 } else if (Feature == "+hwdiv-arm") { 5147 HWDiv |= HWDivARM; 5148 } else if (Feature == "+crc") { 5149 CRC = 1; 5150 } else if (Feature == "+crypto") { 5151 Crypto = 1; 5152 } else if (Feature == "+dsp") { 5153 DSP = 1; 5154 } else if (Feature == "+fp-only-sp") { 5155 HW_FP_remove |= HW_FP_DP; 5156 } else if (Feature == "+strict-align") { 5157 Unaligned = 0; 5158 } else if (Feature == "+fp16") { 5159 HW_FP |= HW_FP_HP; 5160 } 5161 } 5162 HW_FP &= ~HW_FP_remove; 5163 5164 switch (ArchVersion) { 5165 case 6: 5166 if (ArchProfile == llvm::ARM::PK_M) 5167 LDREX = 0; 5168 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5169 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5170 else 5171 LDREX = LDREX_W; 5172 break; 5173 case 7: 5174 if (ArchProfile == llvm::ARM::PK_M) 5175 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5176 else 5177 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5178 break; 5179 case 8: 5180 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5181 } 5182 5183 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5184 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5185 return false; 5186 } 5187 5188 if (FPMath == FP_Neon) 5189 Features.push_back("+neonfp"); 5190 else if (FPMath == FP_VFP) 5191 Features.push_back("-neonfp"); 5192 5193 // Remove front-end specific options which the backend handles differently. 5194 auto Feature = 5195 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5196 if (Feature != Features.end()) 5197 Features.erase(Feature); 5198 5199 return true; 5200 } 5201 5202 bool hasFeature(StringRef Feature) const override { 5203 return llvm::StringSwitch<bool>(Feature) 5204 .Case("arm", true) 5205 .Case("aarch32", true) 5206 .Case("softfloat", SoftFloat) 5207 .Case("thumb", isThumb()) 5208 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5209 .Case("hwdiv", HWDiv & HWDivThumb) 5210 .Case("hwdiv-arm", HWDiv & HWDivARM) 5211 .Default(false); 5212 } 5213 5214 bool setCPU(const std::string &Name) override { 5215 if (Name != "generic") 5216 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5217 5218 if (ArchKind == llvm::ARM::AK_INVALID) 5219 return false; 5220 setAtomic(); 5221 CPU = Name; 5222 return true; 5223 } 5224 5225 bool setFPMath(StringRef Name) override; 5226 5227 void getTargetDefines(const LangOptions &Opts, 5228 MacroBuilder &Builder) const override { 5229 // Target identification. 5230 Builder.defineMacro("__arm"); 5231 Builder.defineMacro("__arm__"); 5232 // For bare-metal none-eabi. 5233 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5234 getTriple().getEnvironment() == llvm::Triple::EABI) 5235 Builder.defineMacro("__ELF__"); 5236 5237 // Target properties. 5238 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5239 5240 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5241 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5242 if (getTriple().isWatchABI()) 5243 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5244 5245 if (!CPUAttr.empty()) 5246 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5247 5248 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5249 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5250 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5251 5252 if (ArchVersion >= 8) { 5253 // ACLE 6.5.7 Crypto Extension 5254 if (Crypto) 5255 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5256 // ACLE 6.5.8 CRC32 Extension 5257 if (CRC) 5258 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5259 // ACLE 6.5.10 Numeric Maximum and Minimum 5260 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5261 // ACLE 6.5.9 Directed Rounding 5262 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5263 } 5264 5265 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5266 // is not defined for the M-profile. 5267 // NOTE that the default profile is assumed to be 'A' 5268 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5269 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5270 5271 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5272 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5273 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5274 // v7 and v8 architectures excluding v8-M Baseline. 5275 if (supportsThumb2()) 5276 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5277 else if (supportsThumb()) 5278 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5279 5280 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5281 // instruction set such as ARM or Thumb. 5282 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5283 5284 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5285 5286 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5287 if (!CPUProfile.empty()) 5288 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5289 5290 // ACLE 6.4.3 Unaligned access supported in hardware 5291 if (Unaligned) 5292 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5293 5294 // ACLE 6.4.4 LDREX/STREX 5295 if (LDREX) 5296 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5297 5298 // ACLE 6.4.5 CLZ 5299 if (ArchVersion == 5 || 5300 (ArchVersion == 6 && CPUProfile != "M") || 5301 ArchVersion > 6) 5302 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5303 5304 // ACLE 6.5.1 Hardware Floating Point 5305 if (HW_FP) 5306 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5307 5308 // ACLE predefines. 5309 Builder.defineMacro("__ARM_ACLE", "200"); 5310 5311 // FP16 support (we currently only support IEEE format). 5312 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5313 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5314 5315 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5316 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5317 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5318 5319 // Subtarget options. 5320 5321 // FIXME: It's more complicated than this and we don't really support 5322 // interworking. 5323 // Windows on ARM does not "support" interworking 5324 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5325 Builder.defineMacro("__THUMB_INTERWORK__"); 5326 5327 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5328 // Embedded targets on Darwin follow AAPCS, but not EABI. 5329 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5330 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5331 Builder.defineMacro("__ARM_EABI__"); 5332 Builder.defineMacro("__ARM_PCS", "1"); 5333 } 5334 5335 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5336 ABI == "aapcs16") 5337 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5338 5339 if (SoftFloat) 5340 Builder.defineMacro("__SOFTFP__"); 5341 5342 if (ArchKind == llvm::ARM::AK_XSCALE) 5343 Builder.defineMacro("__XSCALE__"); 5344 5345 if (isThumb()) { 5346 Builder.defineMacro("__THUMBEL__"); 5347 Builder.defineMacro("__thumb__"); 5348 if (supportsThumb2()) 5349 Builder.defineMacro("__thumb2__"); 5350 } 5351 5352 // ACLE 6.4.9 32-bit SIMD instructions 5353 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5354 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5355 5356 // ACLE 6.4.10 Hardware Integer Divide 5357 if (((HWDiv & HWDivThumb) && isThumb()) || 5358 ((HWDiv & HWDivARM) && !isThumb())) { 5359 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5360 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5361 } 5362 5363 // Note, this is always on in gcc, even though it doesn't make sense. 5364 Builder.defineMacro("__APCS_32__"); 5365 5366 if (FPUModeIsVFP((FPUMode) FPU)) { 5367 Builder.defineMacro("__VFP_FP__"); 5368 if (FPU & VFP2FPU) 5369 Builder.defineMacro("__ARM_VFPV2__"); 5370 if (FPU & VFP3FPU) 5371 Builder.defineMacro("__ARM_VFPV3__"); 5372 if (FPU & VFP4FPU) 5373 Builder.defineMacro("__ARM_VFPV4__"); 5374 } 5375 5376 // This only gets set when Neon instructions are actually available, unlike 5377 // the VFP define, hence the soft float and arch check. This is subtly 5378 // different from gcc, we follow the intent which was that it should be set 5379 // when Neon instructions are actually available. 5380 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5381 Builder.defineMacro("__ARM_NEON", "1"); 5382 Builder.defineMacro("__ARM_NEON__"); 5383 // current AArch32 NEON implementations do not support double-precision 5384 // floating-point even when it is present in VFP. 5385 Builder.defineMacro("__ARM_NEON_FP", 5386 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5387 } 5388 5389 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5390 Opts.ShortWChar ? "2" : "4"); 5391 5392 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5393 Opts.ShortEnums ? "1" : "4"); 5394 5395 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5398 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5400 } 5401 5402 // ACLE 6.4.7 DSP instructions 5403 if (DSP) { 5404 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5405 } 5406 5407 // ACLE 6.4.8 Saturation instructions 5408 bool SAT = false; 5409 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5410 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5411 SAT = true; 5412 } 5413 5414 // ACLE 6.4.6 Q (saturation) flag 5415 if (DSP || SAT) 5416 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5417 5418 if (Opts.UnsafeFPMath) 5419 Builder.defineMacro("__ARM_FP_FAST", "1"); 5420 5421 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5422 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5423 } 5424 5425 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5426 return llvm::makeArrayRef(BuiltinInfo, 5427 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5428 } 5429 bool isCLZForZeroUndef() const override { return false; } 5430 BuiltinVaListKind getBuiltinVaListKind() const override { 5431 return IsAAPCS 5432 ? AAPCSABIBuiltinVaList 5433 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5434 : TargetInfo::VoidPtrBuiltinVaList); 5435 } 5436 ArrayRef<const char *> getGCCRegNames() const override; 5437 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5438 bool validateAsmConstraint(const char *&Name, 5439 TargetInfo::ConstraintInfo &Info) const override { 5440 switch (*Name) { 5441 default: break; 5442 case 'l': // r0-r7 5443 case 'h': // r8-r15 5444 case 't': // VFP Floating point register single precision 5445 case 'w': // VFP Floating point register double precision 5446 Info.setAllowsRegister(); 5447 return true; 5448 case 'I': 5449 case 'J': 5450 case 'K': 5451 case 'L': 5452 case 'M': 5453 // FIXME 5454 return true; 5455 case 'Q': // A memory address that is a single base register. 5456 Info.setAllowsMemory(); 5457 return true; 5458 case 'U': // a memory reference... 5459 switch (Name[1]) { 5460 case 'q': // ...ARMV4 ldrsb 5461 case 'v': // ...VFP load/store (reg+constant offset) 5462 case 'y': // ...iWMMXt load/store 5463 case 't': // address valid for load/store opaque types wider 5464 // than 128-bits 5465 case 'n': // valid address for Neon doubleword vector load/store 5466 case 'm': // valid address for Neon element and structure load/store 5467 case 's': // valid address for non-offset loads/stores of quad-word 5468 // values in four ARM registers 5469 Info.setAllowsMemory(); 5470 Name++; 5471 return true; 5472 } 5473 } 5474 return false; 5475 } 5476 std::string convertConstraint(const char *&Constraint) const override { 5477 std::string R; 5478 switch (*Constraint) { 5479 case 'U': // Two-character constraint; add "^" hint for later parsing. 5480 R = std::string("^") + std::string(Constraint, 2); 5481 Constraint++; 5482 break; 5483 case 'p': // 'p' should be translated to 'r' by default. 5484 R = std::string("r"); 5485 break; 5486 default: 5487 return std::string(1, *Constraint); 5488 } 5489 return R; 5490 } 5491 bool 5492 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5493 std::string &SuggestedModifier) const override { 5494 bool isOutput = (Constraint[0] == '='); 5495 bool isInOut = (Constraint[0] == '+'); 5496 5497 // Strip off constraint modifiers. 5498 while (Constraint[0] == '=' || 5499 Constraint[0] == '+' || 5500 Constraint[0] == '&') 5501 Constraint = Constraint.substr(1); 5502 5503 switch (Constraint[0]) { 5504 default: break; 5505 case 'r': { 5506 switch (Modifier) { 5507 default: 5508 return (isInOut || isOutput || Size <= 64); 5509 case 'q': 5510 // A register of size 32 cannot fit a vector type. 5511 return false; 5512 } 5513 } 5514 } 5515 5516 return true; 5517 } 5518 const char *getClobbers() const override { 5519 // FIXME: Is this really right? 5520 return ""; 5521 } 5522 5523 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5524 switch (CC) { 5525 case CC_AAPCS: 5526 case CC_AAPCS_VFP: 5527 case CC_Swift: 5528 return CCCR_OK; 5529 default: 5530 return CCCR_Warning; 5531 } 5532 } 5533 5534 int getEHDataRegisterNumber(unsigned RegNo) const override { 5535 if (RegNo == 0) return 0; 5536 if (RegNo == 1) return 1; 5537 return -1; 5538 } 5539 5540 bool hasSjLjLowering() const override { 5541 return true; 5542 } 5543 }; 5544 5545 bool ARMTargetInfo::setFPMath(StringRef Name) { 5546 if (Name == "neon") { 5547 FPMath = FP_Neon; 5548 return true; 5549 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5550 Name == "vfp4") { 5551 FPMath = FP_VFP; 5552 return true; 5553 } 5554 return false; 5555 } 5556 5557 const char * const ARMTargetInfo::GCCRegNames[] = { 5558 // Integer registers 5559 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5560 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5561 5562 // Float registers 5563 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5564 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5565 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5566 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5567 5568 // Double registers 5569 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5570 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5571 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5572 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5573 5574 // Quad registers 5575 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5576 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5577 }; 5578 5579 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5580 return llvm::makeArrayRef(GCCRegNames); 5581 } 5582 5583 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5584 { { "a1" }, "r0" }, 5585 { { "a2" }, "r1" }, 5586 { { "a3" }, "r2" }, 5587 { { "a4" }, "r3" }, 5588 { { "v1" }, "r4" }, 5589 { { "v2" }, "r5" }, 5590 { { "v3" }, "r6" }, 5591 { { "v4" }, "r7" }, 5592 { { "v5" }, "r8" }, 5593 { { "v6", "rfp" }, "r9" }, 5594 { { "sl" }, "r10" }, 5595 { { "fp" }, "r11" }, 5596 { { "ip" }, "r12" }, 5597 { { "r13" }, "sp" }, 5598 { { "r14" }, "lr" }, 5599 { { "r15" }, "pc" }, 5600 // The S, D and Q registers overlap, but aren't really aliases; we 5601 // don't want to substitute one of these for a different-sized one. 5602 }; 5603 5604 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5605 return llvm::makeArrayRef(GCCRegAliases); 5606 } 5607 5608 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5609 #define BUILTIN(ID, TYPE, ATTRS) \ 5610 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5611 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5612 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5613 #include "clang/Basic/BuiltinsNEON.def" 5614 5615 #define BUILTIN(ID, TYPE, ATTRS) \ 5616 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5617 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5618 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5619 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5620 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5621 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5622 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5623 #include "clang/Basic/BuiltinsARM.def" 5624 }; 5625 5626 class ARMleTargetInfo : public ARMTargetInfo { 5627 public: 5628 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5629 : ARMTargetInfo(Triple, Opts) {} 5630 void getTargetDefines(const LangOptions &Opts, 5631 MacroBuilder &Builder) const override { 5632 Builder.defineMacro("__ARMEL__"); 5633 ARMTargetInfo::getTargetDefines(Opts, Builder); 5634 } 5635 }; 5636 5637 class ARMbeTargetInfo : public ARMTargetInfo { 5638 public: 5639 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5640 : ARMTargetInfo(Triple, Opts) {} 5641 void getTargetDefines(const LangOptions &Opts, 5642 MacroBuilder &Builder) const override { 5643 Builder.defineMacro("__ARMEB__"); 5644 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5645 ARMTargetInfo::getTargetDefines(Opts, Builder); 5646 } 5647 }; 5648 5649 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5650 const llvm::Triple Triple; 5651 public: 5652 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5653 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5654 WCharType = UnsignedShort; 5655 SizeType = UnsignedInt; 5656 } 5657 void getVisualStudioDefines(const LangOptions &Opts, 5658 MacroBuilder &Builder) const { 5659 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5660 5661 // FIXME: this is invalid for WindowsCE 5662 Builder.defineMacro("_M_ARM_NT", "1"); 5663 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5664 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5665 5666 assert((Triple.getArch() == llvm::Triple::arm || 5667 Triple.getArch() == llvm::Triple::thumb) && 5668 "invalid architecture for Windows ARM target info"); 5669 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5670 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5671 5672 // TODO map the complete set of values 5673 // 31: VFPv3 40: VFPv4 5674 Builder.defineMacro("_M_ARM_FP", "31"); 5675 } 5676 BuiltinVaListKind getBuiltinVaListKind() const override { 5677 return TargetInfo::CharPtrBuiltinVaList; 5678 } 5679 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5680 switch (CC) { 5681 case CC_X86StdCall: 5682 case CC_X86ThisCall: 5683 case CC_X86FastCall: 5684 case CC_X86VectorCall: 5685 return CCCR_Ignore; 5686 case CC_C: 5687 return CCCR_OK; 5688 default: 5689 return CCCR_Warning; 5690 } 5691 } 5692 }; 5693 5694 // Windows ARM + Itanium C++ ABI Target 5695 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5696 public: 5697 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 5698 const TargetOptions &Opts) 5699 : WindowsARMTargetInfo(Triple, Opts) { 5700 TheCXXABI.set(TargetCXXABI::GenericARM); 5701 } 5702 5703 void getTargetDefines(const LangOptions &Opts, 5704 MacroBuilder &Builder) const override { 5705 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5706 5707 if (Opts.MSVCCompat) 5708 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5709 } 5710 }; 5711 5712 // Windows ARM, MS (C++) ABI 5713 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5714 public: 5715 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 5716 const TargetOptions &Opts) 5717 : WindowsARMTargetInfo(Triple, Opts) { 5718 TheCXXABI.set(TargetCXXABI::Microsoft); 5719 } 5720 5721 void getTargetDefines(const LangOptions &Opts, 5722 MacroBuilder &Builder) const override { 5723 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5724 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5725 } 5726 }; 5727 5728 // ARM MinGW target 5729 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5730 public: 5731 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5732 : WindowsARMTargetInfo(Triple, Opts) { 5733 TheCXXABI.set(TargetCXXABI::GenericARM); 5734 } 5735 5736 void getTargetDefines(const LangOptions &Opts, 5737 MacroBuilder &Builder) const override { 5738 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5739 DefineStd(Builder, "WIN32", Opts); 5740 DefineStd(Builder, "WINNT", Opts); 5741 Builder.defineMacro("_ARM_"); 5742 addMinGWDefines(Opts, Builder); 5743 } 5744 }; 5745 5746 // ARM Cygwin target 5747 class CygwinARMTargetInfo : public ARMleTargetInfo { 5748 public: 5749 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5750 : ARMleTargetInfo(Triple, Opts) { 5751 TLSSupported = false; 5752 WCharType = UnsignedShort; 5753 DoubleAlign = LongLongAlign = 64; 5754 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5755 } 5756 void getTargetDefines(const LangOptions &Opts, 5757 MacroBuilder &Builder) const override { 5758 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5759 Builder.defineMacro("_ARM_"); 5760 Builder.defineMacro("__CYGWIN__"); 5761 Builder.defineMacro("__CYGWIN32__"); 5762 DefineStd(Builder, "unix", Opts); 5763 if (Opts.CPlusPlus) 5764 Builder.defineMacro("_GNU_SOURCE"); 5765 } 5766 }; 5767 5768 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 5769 protected: 5770 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5771 MacroBuilder &Builder) const override { 5772 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5773 } 5774 5775 public: 5776 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5777 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 5778 HasAlignMac68kSupport = true; 5779 // iOS always has 64-bit atomic instructions. 5780 // FIXME: This should be based off of the target features in 5781 // ARMleTargetInfo. 5782 MaxAtomicInlineWidth = 64; 5783 5784 if (Triple.isWatchABI()) { 5785 // Darwin on iOS uses a variant of the ARM C++ ABI. 5786 TheCXXABI.set(TargetCXXABI::WatchOS); 5787 5788 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5789 // size_t is long, it's a bit weird for it to be int. 5790 PtrDiffType = SignedLong; 5791 5792 // BOOL should be a real boolean on the new ABI 5793 UseSignedCharForObjCBool = false; 5794 } else 5795 TheCXXABI.set(TargetCXXABI::iOS); 5796 } 5797 }; 5798 5799 class AArch64TargetInfo : public TargetInfo { 5800 virtual void setDataLayout() = 0; 5801 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5802 static const char *const GCCRegNames[]; 5803 5804 enum FPUModeEnum { 5805 FPUMode, 5806 NeonMode 5807 }; 5808 5809 unsigned FPU; 5810 unsigned CRC; 5811 unsigned Crypto; 5812 unsigned Unaligned; 5813 unsigned V8_1A; 5814 5815 static const Builtin::Info BuiltinInfo[]; 5816 5817 std::string ABI; 5818 5819 public: 5820 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5821 : TargetInfo(Triple), ABI("aapcs") { 5822 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5823 WCharType = SignedInt; 5824 5825 // NetBSD apparently prefers consistency across ARM targets to consistency 5826 // across 64-bit targets. 5827 Int64Type = SignedLongLong; 5828 IntMaxType = SignedLongLong; 5829 } else { 5830 WCharType = UnsignedInt; 5831 Int64Type = SignedLong; 5832 IntMaxType = SignedLong; 5833 } 5834 5835 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5836 MaxVectorAlign = 128; 5837 MaxAtomicInlineWidth = 128; 5838 MaxAtomicPromoteWidth = 128; 5839 5840 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5841 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5842 5843 // {} in inline assembly are neon specifiers, not assembly variant 5844 // specifiers. 5845 NoAsmVariants = true; 5846 5847 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5848 // contributes to the alignment of the containing aggregate in the same way 5849 // a plain (non bit-field) member of that type would, without exception for 5850 // zero-sized or anonymous bit-fields." 5851 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5852 UseZeroLengthBitfieldAlignment = true; 5853 5854 // AArch64 targets default to using the ARM C++ ABI. 5855 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5856 5857 if (Triple.getOS() == llvm::Triple::Linux || 5858 Triple.getOS() == llvm::Triple::UnknownOS) 5859 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 5860 } 5861 5862 StringRef getABI() const override { return ABI; } 5863 bool setABI(const std::string &Name) override { 5864 if (Name != "aapcs" && Name != "darwinpcs") 5865 return false; 5866 5867 ABI = Name; 5868 return true; 5869 } 5870 5871 bool setCPU(const std::string &Name) override { 5872 return Name == "generic" || 5873 llvm::AArch64::parseCPUArch(Name) != 5874 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 5875 } 5876 5877 void getTargetDefines(const LangOptions &Opts, 5878 MacroBuilder &Builder) const override { 5879 // Target identification. 5880 Builder.defineMacro("__aarch64__"); 5881 5882 // Target properties. 5883 Builder.defineMacro("_LP64"); 5884 Builder.defineMacro("__LP64__"); 5885 5886 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5887 Builder.defineMacro("__ARM_ACLE", "200"); 5888 Builder.defineMacro("__ARM_ARCH", "8"); 5889 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5890 5891 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5892 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5893 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5894 5895 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5896 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5897 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5898 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5899 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5900 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5901 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5902 5903 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5904 5905 // 0xe implies support for half, single and double precision operations. 5906 Builder.defineMacro("__ARM_FP", "0xE"); 5907 5908 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5909 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5910 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5911 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5912 5913 if (Opts.UnsafeFPMath) 5914 Builder.defineMacro("__ARM_FP_FAST", "1"); 5915 5916 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5917 5918 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5919 Opts.ShortEnums ? "1" : "4"); 5920 5921 if (FPU == NeonMode) { 5922 Builder.defineMacro("__ARM_NEON", "1"); 5923 // 64-bit NEON supports half, single and double precision operations. 5924 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5925 } 5926 5927 if (CRC) 5928 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5929 5930 if (Crypto) 5931 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5932 5933 if (Unaligned) 5934 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5935 5936 if (V8_1A) 5937 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5938 5939 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5940 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5941 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5942 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5943 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5944 } 5945 5946 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5947 return llvm::makeArrayRef(BuiltinInfo, 5948 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5949 } 5950 5951 bool hasFeature(StringRef Feature) const override { 5952 return Feature == "aarch64" || 5953 Feature == "arm64" || 5954 Feature == "arm" || 5955 (Feature == "neon" && FPU == NeonMode); 5956 } 5957 5958 bool handleTargetFeatures(std::vector<std::string> &Features, 5959 DiagnosticsEngine &Diags) override { 5960 FPU = FPUMode; 5961 CRC = 0; 5962 Crypto = 0; 5963 Unaligned = 1; 5964 V8_1A = 0; 5965 5966 for (const auto &Feature : Features) { 5967 if (Feature == "+neon") 5968 FPU = NeonMode; 5969 if (Feature == "+crc") 5970 CRC = 1; 5971 if (Feature == "+crypto") 5972 Crypto = 1; 5973 if (Feature == "+strict-align") 5974 Unaligned = 0; 5975 if (Feature == "+v8.1a") 5976 V8_1A = 1; 5977 } 5978 5979 setDataLayout(); 5980 5981 return true; 5982 } 5983 5984 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5985 switch (CC) { 5986 case CC_C: 5987 case CC_Swift: 5988 case CC_PreserveMost: 5989 case CC_PreserveAll: 5990 return CCCR_OK; 5991 default: 5992 return CCCR_Warning; 5993 } 5994 } 5995 5996 bool isCLZForZeroUndef() const override { return false; } 5997 5998 BuiltinVaListKind getBuiltinVaListKind() const override { 5999 return TargetInfo::AArch64ABIBuiltinVaList; 6000 } 6001 6002 ArrayRef<const char *> getGCCRegNames() const override; 6003 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6004 6005 bool validateAsmConstraint(const char *&Name, 6006 TargetInfo::ConstraintInfo &Info) const override { 6007 switch (*Name) { 6008 default: 6009 return false; 6010 case 'w': // Floating point and SIMD registers (V0-V31) 6011 Info.setAllowsRegister(); 6012 return true; 6013 case 'I': // Constant that can be used with an ADD instruction 6014 case 'J': // Constant that can be used with a SUB instruction 6015 case 'K': // Constant that can be used with a 32-bit logical instruction 6016 case 'L': // Constant that can be used with a 64-bit logical instruction 6017 case 'M': // Constant that can be used as a 32-bit MOV immediate 6018 case 'N': // Constant that can be used as a 64-bit MOV immediate 6019 case 'Y': // Floating point constant zero 6020 case 'Z': // Integer constant zero 6021 return true; 6022 case 'Q': // A memory reference with base register and no offset 6023 Info.setAllowsMemory(); 6024 return true; 6025 case 'S': // A symbolic address 6026 Info.setAllowsRegister(); 6027 return true; 6028 case 'U': 6029 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6030 // Utf: A memory address suitable for ldp/stp in TF mode. 6031 // Usa: An absolute symbolic address. 6032 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6033 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6034 case 'z': // Zero register, wzr or xzr 6035 Info.setAllowsRegister(); 6036 return true; 6037 case 'x': // Floating point and SIMD registers (V0-V15) 6038 Info.setAllowsRegister(); 6039 return true; 6040 } 6041 return false; 6042 } 6043 6044 bool 6045 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6046 std::string &SuggestedModifier) const override { 6047 // Strip off constraint modifiers. 6048 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6049 Constraint = Constraint.substr(1); 6050 6051 switch (Constraint[0]) { 6052 default: 6053 return true; 6054 case 'z': 6055 case 'r': { 6056 switch (Modifier) { 6057 case 'x': 6058 case 'w': 6059 // For now assume that the person knows what they're 6060 // doing with the modifier. 6061 return true; 6062 default: 6063 // By default an 'r' constraint will be in the 'x' 6064 // registers. 6065 if (Size == 64) 6066 return true; 6067 6068 SuggestedModifier = "w"; 6069 return false; 6070 } 6071 } 6072 } 6073 } 6074 6075 const char *getClobbers() const override { return ""; } 6076 6077 int getEHDataRegisterNumber(unsigned RegNo) const override { 6078 if (RegNo == 0) 6079 return 0; 6080 if (RegNo == 1) 6081 return 1; 6082 return -1; 6083 } 6084 }; 6085 6086 const char *const AArch64TargetInfo::GCCRegNames[] = { 6087 // 32-bit Integer registers 6088 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6089 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6090 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6091 6092 // 64-bit Integer registers 6093 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6094 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6095 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6096 6097 // 32-bit floating point regsisters 6098 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6099 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6100 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6101 6102 // 64-bit floating point regsisters 6103 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6104 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6105 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6106 6107 // Vector registers 6108 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6109 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6110 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6111 }; 6112 6113 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6114 return llvm::makeArrayRef(GCCRegNames); 6115 } 6116 6117 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6118 { { "w31" }, "wsp" }, 6119 { { "x29" }, "fp" }, 6120 { { "x30" }, "lr" }, 6121 { { "x31" }, "sp" }, 6122 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6123 // don't want to substitute one of these for a different-sized one. 6124 }; 6125 6126 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6127 return llvm::makeArrayRef(GCCRegAliases); 6128 } 6129 6130 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6131 #define BUILTIN(ID, TYPE, ATTRS) \ 6132 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6133 #include "clang/Basic/BuiltinsNEON.def" 6134 6135 #define BUILTIN(ID, TYPE, ATTRS) \ 6136 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6137 #include "clang/Basic/BuiltinsAArch64.def" 6138 }; 6139 6140 class AArch64leTargetInfo : public AArch64TargetInfo { 6141 void setDataLayout() override { 6142 if (getTriple().isOSBinFormatMachO()) 6143 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6144 else 6145 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6146 } 6147 6148 public: 6149 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6150 : AArch64TargetInfo(Triple, Opts) { 6151 } 6152 void getTargetDefines(const LangOptions &Opts, 6153 MacroBuilder &Builder) const override { 6154 Builder.defineMacro("__AARCH64EL__"); 6155 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6156 } 6157 }; 6158 6159 class AArch64beTargetInfo : public AArch64TargetInfo { 6160 void setDataLayout() override { 6161 assert(!getTriple().isOSBinFormatMachO()); 6162 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6163 } 6164 6165 public: 6166 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6167 : AArch64TargetInfo(Triple, Opts) {} 6168 void getTargetDefines(const LangOptions &Opts, 6169 MacroBuilder &Builder) const override { 6170 Builder.defineMacro("__AARCH64EB__"); 6171 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6172 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6173 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6174 } 6175 }; 6176 6177 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6178 protected: 6179 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6180 MacroBuilder &Builder) const override { 6181 Builder.defineMacro("__AARCH64_SIMD__"); 6182 Builder.defineMacro("__ARM64_ARCH_8__"); 6183 Builder.defineMacro("__ARM_NEON__"); 6184 Builder.defineMacro("__LITTLE_ENDIAN__"); 6185 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6186 Builder.defineMacro("__arm64", "1"); 6187 Builder.defineMacro("__arm64__", "1"); 6188 6189 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6190 } 6191 6192 public: 6193 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6194 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6195 Int64Type = SignedLongLong; 6196 WCharType = SignedInt; 6197 UseSignedCharForObjCBool = false; 6198 6199 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6200 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6201 6202 TheCXXABI.set(TargetCXXABI::iOS64); 6203 } 6204 6205 BuiltinVaListKind getBuiltinVaListKind() const override { 6206 return TargetInfo::CharPtrBuiltinVaList; 6207 } 6208 }; 6209 6210 // Hexagon abstract base class 6211 class HexagonTargetInfo : public TargetInfo { 6212 static const Builtin::Info BuiltinInfo[]; 6213 static const char * const GCCRegNames[]; 6214 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6215 std::string CPU; 6216 bool HasHVX, HasHVXDouble; 6217 bool UseLongCalls; 6218 6219 public: 6220 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6221 : TargetInfo(Triple) { 6222 // Specify the vector alignment explicitly. For v512x1, the calculated 6223 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6224 // the required minimum of 64 bytes. 6225 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6226 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6227 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6228 SizeType = UnsignedInt; 6229 PtrDiffType = SignedInt; 6230 IntPtrType = SignedInt; 6231 6232 // {} in inline assembly are packet specifiers, not assembly variant 6233 // specifiers. 6234 NoAsmVariants = true; 6235 6236 LargeArrayMinWidth = 64; 6237 LargeArrayAlign = 64; 6238 UseBitFieldTypeAlignment = true; 6239 ZeroLengthBitfieldBoundary = 32; 6240 HasHVX = HasHVXDouble = false; 6241 UseLongCalls = false; 6242 } 6243 6244 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6245 return llvm::makeArrayRef(BuiltinInfo, 6246 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6247 } 6248 6249 bool validateAsmConstraint(const char *&Name, 6250 TargetInfo::ConstraintInfo &Info) const override { 6251 switch (*Name) { 6252 case 'v': 6253 case 'q': 6254 if (HasHVX) { 6255 Info.setAllowsRegister(); 6256 return true; 6257 } 6258 break; 6259 case 's': 6260 // Relocatable constant. 6261 return true; 6262 } 6263 return false; 6264 } 6265 6266 void getTargetDefines(const LangOptions &Opts, 6267 MacroBuilder &Builder) const override; 6268 6269 bool isCLZForZeroUndef() const override { return false; } 6270 6271 bool hasFeature(StringRef Feature) const override { 6272 return llvm::StringSwitch<bool>(Feature) 6273 .Case("hexagon", true) 6274 .Case("hvx", HasHVX) 6275 .Case("hvx-double", HasHVXDouble) 6276 .Case("long-calls", UseLongCalls) 6277 .Default(false); 6278 } 6279 6280 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6281 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6282 const override; 6283 6284 bool handleTargetFeatures(std::vector<std::string> &Features, 6285 DiagnosticsEngine &Diags) override; 6286 6287 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6288 bool Enabled) const override; 6289 6290 BuiltinVaListKind getBuiltinVaListKind() const override { 6291 return TargetInfo::CharPtrBuiltinVaList; 6292 } 6293 ArrayRef<const char *> getGCCRegNames() const override; 6294 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6295 const char *getClobbers() const override { 6296 return ""; 6297 } 6298 6299 static const char *getHexagonCPUSuffix(StringRef Name) { 6300 return llvm::StringSwitch<const char*>(Name) 6301 .Case("hexagonv4", "4") 6302 .Case("hexagonv5", "5") 6303 .Case("hexagonv55", "55") 6304 .Case("hexagonv60", "60") 6305 .Default(nullptr); 6306 } 6307 6308 bool setCPU(const std::string &Name) override { 6309 if (!getHexagonCPUSuffix(Name)) 6310 return false; 6311 CPU = Name; 6312 return true; 6313 } 6314 6315 int getEHDataRegisterNumber(unsigned RegNo) const override { 6316 return RegNo < 2 ? RegNo : -1; 6317 } 6318 }; 6319 6320 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6321 MacroBuilder &Builder) const { 6322 Builder.defineMacro("__qdsp6__", "1"); 6323 Builder.defineMacro("__hexagon__", "1"); 6324 6325 if (CPU == "hexagonv4") { 6326 Builder.defineMacro("__HEXAGON_V4__"); 6327 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6328 if (Opts.HexagonQdsp6Compat) { 6329 Builder.defineMacro("__QDSP6_V4__"); 6330 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6331 } 6332 } else if (CPU == "hexagonv5") { 6333 Builder.defineMacro("__HEXAGON_V5__"); 6334 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6335 if(Opts.HexagonQdsp6Compat) { 6336 Builder.defineMacro("__QDSP6_V5__"); 6337 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6338 } 6339 } else if (CPU == "hexagonv55") { 6340 Builder.defineMacro("__HEXAGON_V55__"); 6341 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6342 Builder.defineMacro("__QDSP6_V55__"); 6343 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6344 } else if (CPU == "hexagonv60") { 6345 Builder.defineMacro("__HEXAGON_V60__"); 6346 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6347 Builder.defineMacro("__QDSP6_V60__"); 6348 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6349 } 6350 6351 if (hasFeature("hvx")) { 6352 Builder.defineMacro("__HVX__"); 6353 if (hasFeature("hvx-double")) 6354 Builder.defineMacro("__HVXDBL__"); 6355 } 6356 } 6357 6358 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6359 DiagnosticsEngine &Diags, StringRef CPU, 6360 const std::vector<std::string> &FeaturesVec) const { 6361 // Default for v60: -hvx, -hvx-double. 6362 Features["hvx"] = false; 6363 Features["hvx-double"] = false; 6364 Features["long-calls"] = false; 6365 6366 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6367 } 6368 6369 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6370 DiagnosticsEngine &Diags) { 6371 for (auto &F : Features) { 6372 if (F == "+hvx") 6373 HasHVX = true; 6374 else if (F == "-hvx") 6375 HasHVX = HasHVXDouble = false; 6376 else if (F == "+hvx-double") 6377 HasHVX = HasHVXDouble = true; 6378 else if (F == "-hvx-double") 6379 HasHVXDouble = false; 6380 6381 if (F == "+long-calls") 6382 UseLongCalls = true; 6383 else if (F == "-long-calls") 6384 UseLongCalls = false; 6385 } 6386 return true; 6387 } 6388 6389 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6390 StringRef Name, bool Enabled) const { 6391 if (Enabled) { 6392 if (Name == "hvx-double") 6393 Features["hvx"] = true; 6394 } else { 6395 if (Name == "hvx") 6396 Features["hvx-double"] = false; 6397 } 6398 Features[Name] = Enabled; 6399 } 6400 6401 const char *const HexagonTargetInfo::GCCRegNames[] = { 6402 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6403 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6404 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6405 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6406 "p0", "p1", "p2", "p3", 6407 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6408 }; 6409 6410 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6411 return llvm::makeArrayRef(GCCRegNames); 6412 } 6413 6414 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6415 { { "sp" }, "r29" }, 6416 { { "fp" }, "r30" }, 6417 { { "lr" }, "r31" }, 6418 }; 6419 6420 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6421 return llvm::makeArrayRef(GCCRegAliases); 6422 } 6423 6424 6425 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6426 #define BUILTIN(ID, TYPE, ATTRS) \ 6427 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6428 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6429 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6430 #include "clang/Basic/BuiltinsHexagon.def" 6431 }; 6432 6433 class LanaiTargetInfo : public TargetInfo { 6434 // Class for Lanai (32-bit). 6435 // The CPU profiles supported by the Lanai backend 6436 enum CPUKind { 6437 CK_NONE, 6438 CK_V11, 6439 } CPU; 6440 6441 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6442 static const char *const GCCRegNames[]; 6443 6444 public: 6445 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6446 : TargetInfo(Triple) { 6447 // Description string has to be kept in sync with backend. 6448 resetDataLayout("E" // Big endian 6449 "-m:e" // ELF name manging 6450 "-p:32:32" // 32 bit pointers, 32 bit aligned 6451 "-i64:64" // 64 bit integers, 64 bit aligned 6452 "-a:0:32" // 32 bit alignment of objects of aggregate type 6453 "-n32" // 32 bit native integer width 6454 "-S64" // 64 bit natural stack alignment 6455 ); 6456 6457 // Setting RegParmMax equal to what mregparm was set to in the old 6458 // toolchain 6459 RegParmMax = 4; 6460 6461 // Set the default CPU to V11 6462 CPU = CK_V11; 6463 6464 // Temporary approach to make everything at least word-aligned and allow for 6465 // safely casting between pointers with different alignment requirements. 6466 // TODO: Remove this when there are no more cast align warnings on the 6467 // firmware. 6468 MinGlobalAlign = 32; 6469 } 6470 6471 void getTargetDefines(const LangOptions &Opts, 6472 MacroBuilder &Builder) const override { 6473 // Define __lanai__ when building for target lanai. 6474 Builder.defineMacro("__lanai__"); 6475 6476 // Set define for the CPU specified. 6477 switch (CPU) { 6478 case CK_V11: 6479 Builder.defineMacro("__LANAI_V11__"); 6480 break; 6481 case CK_NONE: 6482 llvm_unreachable("Unhandled target CPU"); 6483 } 6484 } 6485 6486 bool setCPU(const std::string &Name) override { 6487 CPU = llvm::StringSwitch<CPUKind>(Name) 6488 .Case("v11", CK_V11) 6489 .Default(CK_NONE); 6490 6491 return CPU != CK_NONE; 6492 } 6493 6494 bool hasFeature(StringRef Feature) const override { 6495 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6496 } 6497 6498 ArrayRef<const char *> getGCCRegNames() const override; 6499 6500 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6501 6502 BuiltinVaListKind getBuiltinVaListKind() const override { 6503 return TargetInfo::VoidPtrBuiltinVaList; 6504 } 6505 6506 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6507 6508 bool validateAsmConstraint(const char *&Name, 6509 TargetInfo::ConstraintInfo &info) const override { 6510 return false; 6511 } 6512 6513 const char *getClobbers() const override { return ""; } 6514 }; 6515 6516 const char *const LanaiTargetInfo::GCCRegNames[] = { 6517 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6518 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6519 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6520 6521 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6522 return llvm::makeArrayRef(GCCRegNames); 6523 } 6524 6525 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6526 {{"pc"}, "r2"}, 6527 {{"sp"}, "r4"}, 6528 {{"fp"}, "r5"}, 6529 {{"rv"}, "r8"}, 6530 {{"rr1"}, "r10"}, 6531 {{"rr2"}, "r11"}, 6532 {{"rca"}, "r15"}, 6533 }; 6534 6535 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6536 return llvm::makeArrayRef(GCCRegAliases); 6537 } 6538 6539 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6540 class SparcTargetInfo : public TargetInfo { 6541 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6542 static const char * const GCCRegNames[]; 6543 bool SoftFloat; 6544 public: 6545 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6546 : TargetInfo(Triple), SoftFloat(false) {} 6547 6548 int getEHDataRegisterNumber(unsigned RegNo) const override { 6549 if (RegNo == 0) return 24; 6550 if (RegNo == 1) return 25; 6551 return -1; 6552 } 6553 6554 bool handleTargetFeatures(std::vector<std::string> &Features, 6555 DiagnosticsEngine &Diags) override { 6556 // Check if software floating point is enabled 6557 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6558 if (Feature != Features.end()) { 6559 SoftFloat = true; 6560 } 6561 return true; 6562 } 6563 void getTargetDefines(const LangOptions &Opts, 6564 MacroBuilder &Builder) const override { 6565 DefineStd(Builder, "sparc", Opts); 6566 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6567 6568 if (SoftFloat) 6569 Builder.defineMacro("SOFT_FLOAT", "1"); 6570 } 6571 6572 bool hasFeature(StringRef Feature) const override { 6573 return llvm::StringSwitch<bool>(Feature) 6574 .Case("softfloat", SoftFloat) 6575 .Case("sparc", true) 6576 .Default(false); 6577 } 6578 6579 bool hasSjLjLowering() const override { 6580 return true; 6581 } 6582 6583 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6584 // FIXME: Implement! 6585 return None; 6586 } 6587 BuiltinVaListKind getBuiltinVaListKind() const override { 6588 return TargetInfo::VoidPtrBuiltinVaList; 6589 } 6590 ArrayRef<const char *> getGCCRegNames() const override; 6591 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6592 bool validateAsmConstraint(const char *&Name, 6593 TargetInfo::ConstraintInfo &info) const override { 6594 // FIXME: Implement! 6595 switch (*Name) { 6596 case 'I': // Signed 13-bit constant 6597 case 'J': // Zero 6598 case 'K': // 32-bit constant with the low 12 bits clear 6599 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6600 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6601 case 'N': // Same as 'K' but zext (required for SIMode) 6602 case 'O': // The constant 4096 6603 return true; 6604 } 6605 return false; 6606 } 6607 const char *getClobbers() const override { 6608 // FIXME: Implement! 6609 return ""; 6610 } 6611 6612 // No Sparc V7 for now, the backend doesn't support it anyway. 6613 enum CPUKind { 6614 CK_GENERIC, 6615 CK_V8, 6616 CK_SUPERSPARC, 6617 CK_SPARCLITE, 6618 CK_F934, 6619 CK_HYPERSPARC, 6620 CK_SPARCLITE86X, 6621 CK_SPARCLET, 6622 CK_TSC701, 6623 CK_V9, 6624 CK_ULTRASPARC, 6625 CK_ULTRASPARC3, 6626 CK_NIAGARA, 6627 CK_NIAGARA2, 6628 CK_NIAGARA3, 6629 CK_NIAGARA4, 6630 CK_MYRIAD2100, 6631 CK_MYRIAD2150, 6632 CK_MYRIAD2450, 6633 CK_LEON2, 6634 CK_LEON2_AT697E, 6635 CK_LEON2_AT697F, 6636 CK_LEON3, 6637 CK_LEON3_UT699, 6638 CK_LEON3_GR712RC, 6639 CK_LEON4, 6640 CK_LEON4_GR740 6641 } CPU = CK_GENERIC; 6642 6643 enum CPUGeneration { 6644 CG_V8, 6645 CG_V9, 6646 }; 6647 6648 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6649 switch (Kind) { 6650 case CK_GENERIC: 6651 case CK_V8: 6652 case CK_SUPERSPARC: 6653 case CK_SPARCLITE: 6654 case CK_F934: 6655 case CK_HYPERSPARC: 6656 case CK_SPARCLITE86X: 6657 case CK_SPARCLET: 6658 case CK_TSC701: 6659 case CK_MYRIAD2100: 6660 case CK_MYRIAD2150: 6661 case CK_MYRIAD2450: 6662 case CK_LEON2: 6663 case CK_LEON2_AT697E: 6664 case CK_LEON2_AT697F: 6665 case CK_LEON3: 6666 case CK_LEON3_UT699: 6667 case CK_LEON3_GR712RC: 6668 case CK_LEON4: 6669 case CK_LEON4_GR740: 6670 return CG_V8; 6671 case CK_V9: 6672 case CK_ULTRASPARC: 6673 case CK_ULTRASPARC3: 6674 case CK_NIAGARA: 6675 case CK_NIAGARA2: 6676 case CK_NIAGARA3: 6677 case CK_NIAGARA4: 6678 return CG_V9; 6679 } 6680 llvm_unreachable("Unexpected CPU kind"); 6681 } 6682 6683 CPUKind getCPUKind(StringRef Name) const { 6684 return llvm::StringSwitch<CPUKind>(Name) 6685 .Case("v8", CK_V8) 6686 .Case("supersparc", CK_SUPERSPARC) 6687 .Case("sparclite", CK_SPARCLITE) 6688 .Case("f934", CK_F934) 6689 .Case("hypersparc", CK_HYPERSPARC) 6690 .Case("sparclite86x", CK_SPARCLITE86X) 6691 .Case("sparclet", CK_SPARCLET) 6692 .Case("tsc701", CK_TSC701) 6693 .Case("v9", CK_V9) 6694 .Case("ultrasparc", CK_ULTRASPARC) 6695 .Case("ultrasparc3", CK_ULTRASPARC3) 6696 .Case("niagara", CK_NIAGARA) 6697 .Case("niagara2", CK_NIAGARA2) 6698 .Case("niagara3", CK_NIAGARA3) 6699 .Case("niagara4", CK_NIAGARA4) 6700 .Case("ma2100", CK_MYRIAD2100) 6701 .Case("ma2150", CK_MYRIAD2150) 6702 .Case("ma2450", CK_MYRIAD2450) 6703 // FIXME: the myriad2[.n] spellings are obsolete, 6704 // but a grace period is needed to allow updating dependent builds. 6705 .Case("myriad2", CK_MYRIAD2100) 6706 .Case("myriad2.1", CK_MYRIAD2100) 6707 .Case("myriad2.2", CK_MYRIAD2150) 6708 .Case("leon2", CK_LEON2) 6709 .Case("at697e", CK_LEON2_AT697E) 6710 .Case("at697f", CK_LEON2_AT697F) 6711 .Case("leon3", CK_LEON3) 6712 .Case("ut699", CK_LEON3_UT699) 6713 .Case("gr712rc", CK_LEON3_GR712RC) 6714 .Case("leon4", CK_LEON4) 6715 .Case("gr740", CK_LEON4_GR740) 6716 .Default(CK_GENERIC); 6717 } 6718 6719 bool setCPU(const std::string &Name) override { 6720 CPU = getCPUKind(Name); 6721 return CPU != CK_GENERIC; 6722 } 6723 }; 6724 6725 const char * const SparcTargetInfo::GCCRegNames[] = { 6726 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6727 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6728 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6729 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6730 }; 6731 6732 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6733 return llvm::makeArrayRef(GCCRegNames); 6734 } 6735 6736 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6737 { { "g0" }, "r0" }, 6738 { { "g1" }, "r1" }, 6739 { { "g2" }, "r2" }, 6740 { { "g3" }, "r3" }, 6741 { { "g4" }, "r4" }, 6742 { { "g5" }, "r5" }, 6743 { { "g6" }, "r6" }, 6744 { { "g7" }, "r7" }, 6745 { { "o0" }, "r8" }, 6746 { { "o1" }, "r9" }, 6747 { { "o2" }, "r10" }, 6748 { { "o3" }, "r11" }, 6749 { { "o4" }, "r12" }, 6750 { { "o5" }, "r13" }, 6751 { { "o6", "sp" }, "r14" }, 6752 { { "o7" }, "r15" }, 6753 { { "l0" }, "r16" }, 6754 { { "l1" }, "r17" }, 6755 { { "l2" }, "r18" }, 6756 { { "l3" }, "r19" }, 6757 { { "l4" }, "r20" }, 6758 { { "l5" }, "r21" }, 6759 { { "l6" }, "r22" }, 6760 { { "l7" }, "r23" }, 6761 { { "i0" }, "r24" }, 6762 { { "i1" }, "r25" }, 6763 { { "i2" }, "r26" }, 6764 { { "i3" }, "r27" }, 6765 { { "i4" }, "r28" }, 6766 { { "i5" }, "r29" }, 6767 { { "i6", "fp" }, "r30" }, 6768 { { "i7" }, "r31" }, 6769 }; 6770 6771 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6772 return llvm::makeArrayRef(GCCRegAliases); 6773 } 6774 6775 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6776 class SparcV8TargetInfo : public SparcTargetInfo { 6777 public: 6778 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6779 : SparcTargetInfo(Triple, Opts) { 6780 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6781 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6782 switch (getTriple().getOS()) { 6783 default: 6784 SizeType = UnsignedInt; 6785 IntPtrType = SignedInt; 6786 PtrDiffType = SignedInt; 6787 break; 6788 case llvm::Triple::NetBSD: 6789 case llvm::Triple::OpenBSD: 6790 SizeType = UnsignedLong; 6791 IntPtrType = SignedLong; 6792 PtrDiffType = SignedLong; 6793 break; 6794 } 6795 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6796 } 6797 6798 void getTargetDefines(const LangOptions &Opts, 6799 MacroBuilder &Builder) const override { 6800 SparcTargetInfo::getTargetDefines(Opts, Builder); 6801 switch (getCPUGeneration(CPU)) { 6802 case CG_V8: 6803 Builder.defineMacro("__sparcv8"); 6804 if (getTriple().getOS() != llvm::Triple::Solaris) 6805 Builder.defineMacro("__sparcv8__"); 6806 break; 6807 case CG_V9: 6808 Builder.defineMacro("__sparcv9"); 6809 if (getTriple().getOS() != llvm::Triple::Solaris) { 6810 Builder.defineMacro("__sparcv9__"); 6811 Builder.defineMacro("__sparc_v9__"); 6812 } 6813 break; 6814 } 6815 if (getTriple().getVendor() == llvm::Triple::Myriad) { 6816 std::string MyriadArchValue, Myriad2Value; 6817 Builder.defineMacro("__sparc_v8__"); 6818 Builder.defineMacro("__leon__"); 6819 switch (CPU) { 6820 case CK_MYRIAD2150: 6821 MyriadArchValue = "__ma2150"; 6822 Myriad2Value = "2"; 6823 break; 6824 case CK_MYRIAD2450: 6825 MyriadArchValue = "__ma2450"; 6826 Myriad2Value = "2"; 6827 break; 6828 default: 6829 MyriadArchValue = "__ma2100"; 6830 Myriad2Value = "1"; 6831 break; 6832 } 6833 Builder.defineMacro(MyriadArchValue, "1"); 6834 Builder.defineMacro(MyriadArchValue+"__", "1"); 6835 Builder.defineMacro("__myriad2__", Myriad2Value); 6836 Builder.defineMacro("__myriad2", Myriad2Value); 6837 } 6838 } 6839 6840 bool hasSjLjLowering() const override { 6841 return true; 6842 } 6843 }; 6844 6845 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6846 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6847 public: 6848 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6849 : SparcV8TargetInfo(Triple, Opts) { 6850 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 6851 } 6852 }; 6853 6854 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6855 class SparcV9TargetInfo : public SparcTargetInfo { 6856 public: 6857 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6858 : SparcTargetInfo(Triple, Opts) { 6859 // FIXME: Support Sparc quad-precision long double? 6860 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 6861 // This is an LP64 platform. 6862 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6863 6864 // OpenBSD uses long long for int64_t and intmax_t. 6865 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6866 IntMaxType = SignedLongLong; 6867 else 6868 IntMaxType = SignedLong; 6869 Int64Type = IntMaxType; 6870 6871 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6872 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6873 LongDoubleWidth = 128; 6874 LongDoubleAlign = 128; 6875 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6876 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6877 } 6878 6879 void getTargetDefines(const LangOptions &Opts, 6880 MacroBuilder &Builder) const override { 6881 SparcTargetInfo::getTargetDefines(Opts, Builder); 6882 Builder.defineMacro("__sparcv9"); 6883 Builder.defineMacro("__arch64__"); 6884 // Solaris doesn't need these variants, but the BSDs do. 6885 if (getTriple().getOS() != llvm::Triple::Solaris) { 6886 Builder.defineMacro("__sparc64__"); 6887 Builder.defineMacro("__sparc_v9__"); 6888 Builder.defineMacro("__sparcv9__"); 6889 } 6890 } 6891 6892 bool setCPU(const std::string &Name) override { 6893 if (!SparcTargetInfo::setCPU(Name)) 6894 return false; 6895 return getCPUGeneration(CPU) == CG_V9; 6896 } 6897 }; 6898 6899 class SystemZTargetInfo : public TargetInfo { 6900 static const Builtin::Info BuiltinInfo[]; 6901 static const char *const GCCRegNames[]; 6902 std::string CPU; 6903 bool HasTransactionalExecution; 6904 bool HasVector; 6905 6906 public: 6907 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6908 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6909 HasVector(false) { 6910 IntMaxType = SignedLong; 6911 Int64Type = SignedLong; 6912 TLSSupported = true; 6913 IntWidth = IntAlign = 32; 6914 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6915 PointerWidth = PointerAlign = 64; 6916 LongDoubleWidth = 128; 6917 LongDoubleAlign = 64; 6918 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6919 DefaultAlignForAttributeAligned = 64; 6920 MinGlobalAlign = 16; 6921 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 6922 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6923 } 6924 void getTargetDefines(const LangOptions &Opts, 6925 MacroBuilder &Builder) const override { 6926 Builder.defineMacro("__s390__"); 6927 Builder.defineMacro("__s390x__"); 6928 Builder.defineMacro("__zarch__"); 6929 Builder.defineMacro("__LONG_DOUBLE_128__"); 6930 6931 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6932 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6933 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6934 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6935 6936 if (HasTransactionalExecution) 6937 Builder.defineMacro("__HTM__"); 6938 if (Opts.ZVector) 6939 Builder.defineMacro("__VEC__", "10301"); 6940 } 6941 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6942 return llvm::makeArrayRef(BuiltinInfo, 6943 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6944 } 6945 6946 ArrayRef<const char *> getGCCRegNames() const override; 6947 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6948 // No aliases. 6949 return None; 6950 } 6951 bool validateAsmConstraint(const char *&Name, 6952 TargetInfo::ConstraintInfo &info) const override; 6953 const char *getClobbers() const override { 6954 // FIXME: Is this really right? 6955 return ""; 6956 } 6957 BuiltinVaListKind getBuiltinVaListKind() const override { 6958 return TargetInfo::SystemZBuiltinVaList; 6959 } 6960 bool setCPU(const std::string &Name) override { 6961 CPU = Name; 6962 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6963 .Case("z10", true) 6964 .Case("arch8", true) 6965 .Case("z196", true) 6966 .Case("arch9", true) 6967 .Case("zEC12", true) 6968 .Case("arch10", true) 6969 .Case("z13", true) 6970 .Case("arch11", true) 6971 .Default(false); 6972 6973 return CPUKnown; 6974 } 6975 bool 6976 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6977 StringRef CPU, 6978 const std::vector<std::string> &FeaturesVec) const override { 6979 if (CPU == "zEC12" || CPU == "arch10") 6980 Features["transactional-execution"] = true; 6981 if (CPU == "z13" || CPU == "arch11") { 6982 Features["transactional-execution"] = true; 6983 Features["vector"] = true; 6984 } 6985 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6986 } 6987 6988 bool handleTargetFeatures(std::vector<std::string> &Features, 6989 DiagnosticsEngine &Diags) override { 6990 HasTransactionalExecution = false; 6991 for (const auto &Feature : Features) { 6992 if (Feature == "+transactional-execution") 6993 HasTransactionalExecution = true; 6994 else if (Feature == "+vector") 6995 HasVector = true; 6996 } 6997 // If we use the vector ABI, vector types are 64-bit aligned. 6998 if (HasVector) { 6999 MaxVectorAlign = 64; 7000 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7001 "-v128:64-a:8:16-n32:64"); 7002 } 7003 return true; 7004 } 7005 7006 bool hasFeature(StringRef Feature) const override { 7007 return llvm::StringSwitch<bool>(Feature) 7008 .Case("systemz", true) 7009 .Case("htm", HasTransactionalExecution) 7010 .Case("vx", HasVector) 7011 .Default(false); 7012 } 7013 7014 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7015 switch (CC) { 7016 case CC_C: 7017 case CC_Swift: 7018 return CCCR_OK; 7019 default: 7020 return CCCR_Warning; 7021 } 7022 } 7023 7024 StringRef getABI() const override { 7025 if (HasVector) 7026 return "vector"; 7027 return ""; 7028 } 7029 7030 bool useFloat128ManglingForLongDouble() const override { 7031 return true; 7032 } 7033 }; 7034 7035 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7036 #define BUILTIN(ID, TYPE, ATTRS) \ 7037 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7038 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7039 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7040 #include "clang/Basic/BuiltinsSystemZ.def" 7041 }; 7042 7043 const char *const SystemZTargetInfo::GCCRegNames[] = { 7044 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7045 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7046 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7047 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7048 }; 7049 7050 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7051 return llvm::makeArrayRef(GCCRegNames); 7052 } 7053 7054 bool SystemZTargetInfo:: 7055 validateAsmConstraint(const char *&Name, 7056 TargetInfo::ConstraintInfo &Info) const { 7057 switch (*Name) { 7058 default: 7059 return false; 7060 7061 case 'a': // Address register 7062 case 'd': // Data register (equivalent to 'r') 7063 case 'f': // Floating-point register 7064 Info.setAllowsRegister(); 7065 return true; 7066 7067 case 'I': // Unsigned 8-bit constant 7068 case 'J': // Unsigned 12-bit constant 7069 case 'K': // Signed 16-bit constant 7070 case 'L': // Signed 20-bit displacement (on all targets we support) 7071 case 'M': // 0x7fffffff 7072 return true; 7073 7074 case 'Q': // Memory with base and unsigned 12-bit displacement 7075 case 'R': // Likewise, plus an index 7076 case 'S': // Memory with base and signed 20-bit displacement 7077 case 'T': // Likewise, plus an index 7078 Info.setAllowsMemory(); 7079 return true; 7080 } 7081 } 7082 7083 class MSP430TargetInfo : public TargetInfo { 7084 static const char *const GCCRegNames[]; 7085 7086 public: 7087 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7088 : TargetInfo(Triple) { 7089 TLSSupported = false; 7090 IntWidth = 16; 7091 IntAlign = 16; 7092 LongWidth = 32; 7093 LongLongWidth = 64; 7094 LongAlign = LongLongAlign = 16; 7095 PointerWidth = 16; 7096 PointerAlign = 16; 7097 SuitableAlign = 16; 7098 SizeType = UnsignedInt; 7099 IntMaxType = SignedLongLong; 7100 IntPtrType = SignedInt; 7101 PtrDiffType = SignedInt; 7102 SigAtomicType = SignedLong; 7103 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7104 } 7105 void getTargetDefines(const LangOptions &Opts, 7106 MacroBuilder &Builder) const override { 7107 Builder.defineMacro("MSP430"); 7108 Builder.defineMacro("__MSP430__"); 7109 // FIXME: defines for different 'flavours' of MCU 7110 } 7111 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7112 // FIXME: Implement. 7113 return None; 7114 } 7115 bool hasFeature(StringRef Feature) const override { 7116 return Feature == "msp430"; 7117 } 7118 ArrayRef<const char *> getGCCRegNames() const override; 7119 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7120 // No aliases. 7121 return None; 7122 } 7123 bool validateAsmConstraint(const char *&Name, 7124 TargetInfo::ConstraintInfo &info) const override { 7125 // FIXME: implement 7126 switch (*Name) { 7127 case 'K': // the constant 1 7128 case 'L': // constant -1^20 .. 1^19 7129 case 'M': // constant 1-4: 7130 return true; 7131 } 7132 // No target constraints for now. 7133 return false; 7134 } 7135 const char *getClobbers() const override { 7136 // FIXME: Is this really right? 7137 return ""; 7138 } 7139 BuiltinVaListKind getBuiltinVaListKind() const override { 7140 // FIXME: implement 7141 return TargetInfo::CharPtrBuiltinVaList; 7142 } 7143 }; 7144 7145 const char *const MSP430TargetInfo::GCCRegNames[] = { 7146 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7147 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7148 7149 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7150 return llvm::makeArrayRef(GCCRegNames); 7151 } 7152 7153 // LLVM and Clang cannot be used directly to output native binaries for 7154 // target, but is used to compile C code to llvm bitcode with correct 7155 // type and alignment information. 7156 // 7157 // TCE uses the llvm bitcode as input and uses it for generating customized 7158 // target processor and program binary. TCE co-design environment is 7159 // publicly available in http://tce.cs.tut.fi 7160 7161 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7162 3, // opencl_global 7163 4, // opencl_local 7164 5, // opencl_constant 7165 // FIXME: generic has to be added to the target 7166 0, // opencl_generic 7167 0, // cuda_device 7168 0, // cuda_constant 7169 0 // cuda_shared 7170 }; 7171 7172 class TCETargetInfo : public TargetInfo { 7173 public: 7174 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7175 : TargetInfo(Triple) { 7176 TLSSupported = false; 7177 IntWidth = 32; 7178 LongWidth = LongLongWidth = 32; 7179 PointerWidth = 32; 7180 IntAlign = 32; 7181 LongAlign = LongLongAlign = 32; 7182 PointerAlign = 32; 7183 SuitableAlign = 32; 7184 SizeType = UnsignedInt; 7185 IntMaxType = SignedLong; 7186 IntPtrType = SignedInt; 7187 PtrDiffType = SignedInt; 7188 FloatWidth = 32; 7189 FloatAlign = 32; 7190 DoubleWidth = 32; 7191 DoubleAlign = 32; 7192 LongDoubleWidth = 32; 7193 LongDoubleAlign = 32; 7194 FloatFormat = &llvm::APFloat::IEEEsingle; 7195 DoubleFormat = &llvm::APFloat::IEEEsingle; 7196 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 7197 resetDataLayout("E-p:32:32-i8:8:32-i16:16:32-i64:32" 7198 "-f64:32-v64:32-v128:32-a:0:32-n32"); 7199 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7200 UseAddrSpaceMapMangling = true; 7201 } 7202 7203 void getTargetDefines(const LangOptions &Opts, 7204 MacroBuilder &Builder) const override { 7205 DefineStd(Builder, "tce", Opts); 7206 Builder.defineMacro("__TCE__"); 7207 Builder.defineMacro("__TCE_V1__"); 7208 } 7209 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7210 7211 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7212 const char *getClobbers() const override { return ""; } 7213 BuiltinVaListKind getBuiltinVaListKind() const override { 7214 return TargetInfo::VoidPtrBuiltinVaList; 7215 } 7216 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7217 bool validateAsmConstraint(const char *&Name, 7218 TargetInfo::ConstraintInfo &info) const override { 7219 return true; 7220 } 7221 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7222 return None; 7223 } 7224 }; 7225 7226 class BPFTargetInfo : public TargetInfo { 7227 public: 7228 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7229 : TargetInfo(Triple) { 7230 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7231 SizeType = UnsignedLong; 7232 PtrDiffType = SignedLong; 7233 IntPtrType = SignedLong; 7234 IntMaxType = SignedLong; 7235 Int64Type = SignedLong; 7236 RegParmMax = 5; 7237 if (Triple.getArch() == llvm::Triple::bpfeb) { 7238 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7239 } else { 7240 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7241 } 7242 MaxAtomicPromoteWidth = 64; 7243 MaxAtomicInlineWidth = 64; 7244 TLSSupported = false; 7245 } 7246 void getTargetDefines(const LangOptions &Opts, 7247 MacroBuilder &Builder) const override { 7248 DefineStd(Builder, "bpf", Opts); 7249 Builder.defineMacro("__BPF__"); 7250 } 7251 bool hasFeature(StringRef Feature) const override { 7252 return Feature == "bpf"; 7253 } 7254 7255 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7256 const char *getClobbers() const override { 7257 return ""; 7258 } 7259 BuiltinVaListKind getBuiltinVaListKind() const override { 7260 return TargetInfo::VoidPtrBuiltinVaList; 7261 } 7262 ArrayRef<const char *> getGCCRegNames() const override { 7263 return None; 7264 } 7265 bool validateAsmConstraint(const char *&Name, 7266 TargetInfo::ConstraintInfo &info) const override { 7267 return true; 7268 } 7269 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7270 return None; 7271 } 7272 }; 7273 7274 class MipsTargetInfo : public TargetInfo { 7275 void setDataLayout() { 7276 StringRef Layout; 7277 7278 if (ABI == "o32") 7279 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7280 else if (ABI == "n32") 7281 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7282 else if (ABI == "n64") 7283 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7284 else 7285 llvm_unreachable("Invalid ABI"); 7286 7287 if (BigEndian) 7288 resetDataLayout(("E-" + Layout).str()); 7289 else 7290 resetDataLayout(("e-" + Layout).str()); 7291 } 7292 7293 7294 static const Builtin::Info BuiltinInfo[]; 7295 std::string CPU; 7296 bool IsMips16; 7297 bool IsMicromips; 7298 bool IsNan2008; 7299 bool IsSingleFloat; 7300 enum MipsFloatABI { 7301 HardFloat, SoftFloat 7302 } FloatABI; 7303 enum DspRevEnum { 7304 NoDSP, DSP1, DSP2 7305 } DspRev; 7306 bool HasMSA; 7307 7308 protected: 7309 bool HasFP64; 7310 std::string ABI; 7311 7312 public: 7313 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7314 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7315 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 7316 DspRev(NoDSP), HasMSA(false), HasFP64(false) { 7317 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7318 7319 setABI((getTriple().getArch() == llvm::Triple::mips || 7320 getTriple().getArch() == llvm::Triple::mipsel) 7321 ? "o32" 7322 : "n64"); 7323 7324 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7325 } 7326 7327 bool isNaN2008Default() const { 7328 return CPU == "mips32r6" || CPU == "mips64r6"; 7329 } 7330 7331 bool isFP64Default() const { 7332 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7333 } 7334 7335 bool isNan2008() const override { 7336 return IsNan2008; 7337 } 7338 7339 bool processorSupportsGPR64() const { 7340 return llvm::StringSwitch<bool>(CPU) 7341 .Case("mips3", true) 7342 .Case("mips4", true) 7343 .Case("mips5", true) 7344 .Case("mips64", true) 7345 .Case("mips64r2", true) 7346 .Case("mips64r3", true) 7347 .Case("mips64r5", true) 7348 .Case("mips64r6", true) 7349 .Case("octeon", true) 7350 .Default(false); 7351 return false; 7352 } 7353 7354 StringRef getABI() const override { return ABI; } 7355 bool setABI(const std::string &Name) override { 7356 if (Name == "o32") { 7357 setO32ABITypes(); 7358 ABI = Name; 7359 return true; 7360 } 7361 7362 if (Name == "n32") { 7363 setN32ABITypes(); 7364 ABI = Name; 7365 return true; 7366 } 7367 if (Name == "n64") { 7368 setN64ABITypes(); 7369 ABI = Name; 7370 return true; 7371 } 7372 return false; 7373 } 7374 7375 void setO32ABITypes() { 7376 Int64Type = SignedLongLong; 7377 IntMaxType = Int64Type; 7378 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7379 LongDoubleWidth = LongDoubleAlign = 64; 7380 LongWidth = LongAlign = 32; 7381 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7382 PointerWidth = PointerAlign = 32; 7383 PtrDiffType = SignedInt; 7384 SizeType = UnsignedInt; 7385 SuitableAlign = 64; 7386 } 7387 7388 void setN32N64ABITypes() { 7389 LongDoubleWidth = LongDoubleAlign = 128; 7390 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7391 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7392 LongDoubleWidth = LongDoubleAlign = 64; 7393 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7394 } 7395 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7396 SuitableAlign = 128; 7397 } 7398 7399 void setN64ABITypes() { 7400 setN32N64ABITypes(); 7401 Int64Type = SignedLong; 7402 IntMaxType = Int64Type; 7403 LongWidth = LongAlign = 64; 7404 PointerWidth = PointerAlign = 64; 7405 PtrDiffType = SignedLong; 7406 SizeType = UnsignedLong; 7407 } 7408 7409 void setN32ABITypes() { 7410 setN32N64ABITypes(); 7411 Int64Type = SignedLongLong; 7412 IntMaxType = Int64Type; 7413 LongWidth = LongAlign = 32; 7414 PointerWidth = PointerAlign = 32; 7415 PtrDiffType = SignedInt; 7416 SizeType = UnsignedInt; 7417 } 7418 7419 bool setCPU(const std::string &Name) override { 7420 CPU = Name; 7421 return llvm::StringSwitch<bool>(Name) 7422 .Case("mips1", true) 7423 .Case("mips2", true) 7424 .Case("mips3", true) 7425 .Case("mips4", true) 7426 .Case("mips5", true) 7427 .Case("mips32", true) 7428 .Case("mips32r2", true) 7429 .Case("mips32r3", true) 7430 .Case("mips32r5", true) 7431 .Case("mips32r6", true) 7432 .Case("mips64", true) 7433 .Case("mips64r2", true) 7434 .Case("mips64r3", true) 7435 .Case("mips64r5", true) 7436 .Case("mips64r6", true) 7437 .Case("octeon", true) 7438 .Case("p5600", true) 7439 .Default(false); 7440 } 7441 const std::string& getCPU() const { return CPU; } 7442 bool 7443 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7444 StringRef CPU, 7445 const std::vector<std::string> &FeaturesVec) const override { 7446 if (CPU.empty()) 7447 CPU = getCPU(); 7448 if (CPU == "octeon") 7449 Features["mips64r2"] = Features["cnmips"] = true; 7450 else 7451 Features[CPU] = true; 7452 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7453 } 7454 7455 void getTargetDefines(const LangOptions &Opts, 7456 MacroBuilder &Builder) const override { 7457 if (BigEndian) { 7458 DefineStd(Builder, "MIPSEB", Opts); 7459 Builder.defineMacro("_MIPSEB"); 7460 } else { 7461 DefineStd(Builder, "MIPSEL", Opts); 7462 Builder.defineMacro("_MIPSEL"); 7463 } 7464 7465 Builder.defineMacro("__mips__"); 7466 Builder.defineMacro("_mips"); 7467 if (Opts.GNUMode) 7468 Builder.defineMacro("mips"); 7469 7470 if (ABI == "o32") { 7471 Builder.defineMacro("__mips", "32"); 7472 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7473 } else { 7474 Builder.defineMacro("__mips", "64"); 7475 Builder.defineMacro("__mips64"); 7476 Builder.defineMacro("__mips64__"); 7477 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7478 } 7479 7480 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7481 .Cases("mips32", "mips64", "1") 7482 .Cases("mips32r2", "mips64r2", "2") 7483 .Cases("mips32r3", "mips64r3", "3") 7484 .Cases("mips32r5", "mips64r5", "5") 7485 .Cases("mips32r6", "mips64r6", "6") 7486 .Default(""); 7487 if (!ISARev.empty()) 7488 Builder.defineMacro("__mips_isa_rev", ISARev); 7489 7490 if (ABI == "o32") { 7491 Builder.defineMacro("__mips_o32"); 7492 Builder.defineMacro("_ABIO32", "1"); 7493 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7494 } else if (ABI == "n32") { 7495 Builder.defineMacro("__mips_n32"); 7496 Builder.defineMacro("_ABIN32", "2"); 7497 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7498 } else if (ABI == "n64") { 7499 Builder.defineMacro("__mips_n64"); 7500 Builder.defineMacro("_ABI64", "3"); 7501 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7502 } else 7503 llvm_unreachable("Invalid ABI."); 7504 7505 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7506 7507 switch (FloatABI) { 7508 case HardFloat: 7509 Builder.defineMacro("__mips_hard_float", Twine(1)); 7510 break; 7511 case SoftFloat: 7512 Builder.defineMacro("__mips_soft_float", Twine(1)); 7513 break; 7514 } 7515 7516 if (IsSingleFloat) 7517 Builder.defineMacro("__mips_single_float", Twine(1)); 7518 7519 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7520 Builder.defineMacro("_MIPS_FPSET", 7521 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7522 7523 if (IsMips16) 7524 Builder.defineMacro("__mips16", Twine(1)); 7525 7526 if (IsMicromips) 7527 Builder.defineMacro("__mips_micromips", Twine(1)); 7528 7529 if (IsNan2008) 7530 Builder.defineMacro("__mips_nan2008", Twine(1)); 7531 7532 switch (DspRev) { 7533 default: 7534 break; 7535 case DSP1: 7536 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7537 Builder.defineMacro("__mips_dsp", Twine(1)); 7538 break; 7539 case DSP2: 7540 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7541 Builder.defineMacro("__mips_dspr2", Twine(1)); 7542 Builder.defineMacro("__mips_dsp", Twine(1)); 7543 break; 7544 } 7545 7546 if (HasMSA) 7547 Builder.defineMacro("__mips_msa", Twine(1)); 7548 7549 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7550 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7551 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7552 7553 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7554 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7555 7556 // These shouldn't be defined for MIPS-I but there's no need to check 7557 // for that since MIPS-I isn't supported. 7558 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7559 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7560 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7561 7562 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7563 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7564 // the instructions exist but using them violates the ABI since they 7565 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7566 if (ABI == "n32" || ABI == "n64") 7567 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7568 } 7569 7570 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7571 return llvm::makeArrayRef(BuiltinInfo, 7572 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7573 } 7574 bool hasFeature(StringRef Feature) const override { 7575 return llvm::StringSwitch<bool>(Feature) 7576 .Case("mips", true) 7577 .Case("fp64", HasFP64) 7578 .Default(false); 7579 } 7580 BuiltinVaListKind getBuiltinVaListKind() const override { 7581 return TargetInfo::VoidPtrBuiltinVaList; 7582 } 7583 ArrayRef<const char *> getGCCRegNames() const override { 7584 static const char *const GCCRegNames[] = { 7585 // CPU register names 7586 // Must match second column of GCCRegAliases 7587 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7588 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7589 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7590 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7591 // Floating point register names 7592 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7593 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7594 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7595 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 7596 // Hi/lo and condition register names 7597 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 7598 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 7599 "$ac3hi","$ac3lo", 7600 // MSA register names 7601 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 7602 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 7603 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 7604 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 7605 // MSA control register names 7606 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 7607 "$msarequest", "$msamap", "$msaunmap" 7608 }; 7609 return llvm::makeArrayRef(GCCRegNames); 7610 } 7611 bool validateAsmConstraint(const char *&Name, 7612 TargetInfo::ConstraintInfo &Info) const override { 7613 switch (*Name) { 7614 default: 7615 return false; 7616 case 'r': // CPU registers. 7617 case 'd': // Equivalent to "r" unless generating MIPS16 code. 7618 case 'y': // Equivalent to "r", backward compatibility only. 7619 case 'f': // floating-point registers. 7620 case 'c': // $25 for indirect jumps 7621 case 'l': // lo register 7622 case 'x': // hilo register pair 7623 Info.setAllowsRegister(); 7624 return true; 7625 case 'I': // Signed 16-bit constant 7626 case 'J': // Integer 0 7627 case 'K': // Unsigned 16-bit constant 7628 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 7629 case 'M': // Constants not loadable via lui, addiu, or ori 7630 case 'N': // Constant -1 to -65535 7631 case 'O': // A signed 15-bit constant 7632 case 'P': // A constant between 1 go 65535 7633 return true; 7634 case 'R': // An address that can be used in a non-macro load or store 7635 Info.setAllowsMemory(); 7636 return true; 7637 case 'Z': 7638 if (Name[1] == 'C') { // An address usable by ll, and sc. 7639 Info.setAllowsMemory(); 7640 Name++; // Skip over 'Z'. 7641 return true; 7642 } 7643 return false; 7644 } 7645 } 7646 7647 std::string convertConstraint(const char *&Constraint) const override { 7648 std::string R; 7649 switch (*Constraint) { 7650 case 'Z': // Two-character constraint; add "^" hint for later parsing. 7651 if (Constraint[1] == 'C') { 7652 R = std::string("^") + std::string(Constraint, 2); 7653 Constraint++; 7654 return R; 7655 } 7656 break; 7657 } 7658 return TargetInfo::convertConstraint(Constraint); 7659 } 7660 7661 const char *getClobbers() const override { 7662 // In GCC, $1 is not widely used in generated code (it's used only in a few 7663 // specific situations), so there is no real need for users to add it to 7664 // the clobbers list if they want to use it in their inline assembly code. 7665 // 7666 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 7667 // code generation, so using it in inline assembly without adding it to the 7668 // clobbers list can cause conflicts between the inline assembly code and 7669 // the surrounding generated code. 7670 // 7671 // Another problem is that LLVM is allowed to choose $1 for inline assembly 7672 // operands, which will conflict with the ".set at" assembler option (which 7673 // we use only for inline assembly, in order to maintain compatibility with 7674 // GCC) and will also conflict with the user's usage of $1. 7675 // 7676 // The easiest way to avoid these conflicts and keep $1 as an allocatable 7677 // register for generated code is to automatically clobber $1 for all inline 7678 // assembly code. 7679 // 7680 // FIXME: We should automatically clobber $1 only for inline assembly code 7681 // which actually uses it. This would allow LLVM to use $1 for inline 7682 // assembly operands if the user's assembly code doesn't use it. 7683 return "~{$1}"; 7684 } 7685 7686 bool handleTargetFeatures(std::vector<std::string> &Features, 7687 DiagnosticsEngine &Diags) override { 7688 IsMips16 = false; 7689 IsMicromips = false; 7690 IsNan2008 = isNaN2008Default(); 7691 IsSingleFloat = false; 7692 FloatABI = HardFloat; 7693 DspRev = NoDSP; 7694 HasFP64 = isFP64Default(); 7695 7696 for (const auto &Feature : Features) { 7697 if (Feature == "+single-float") 7698 IsSingleFloat = true; 7699 else if (Feature == "+soft-float") 7700 FloatABI = SoftFloat; 7701 else if (Feature == "+mips16") 7702 IsMips16 = true; 7703 else if (Feature == "+micromips") 7704 IsMicromips = true; 7705 else if (Feature == "+dsp") 7706 DspRev = std::max(DspRev, DSP1); 7707 else if (Feature == "+dspr2") 7708 DspRev = std::max(DspRev, DSP2); 7709 else if (Feature == "+msa") 7710 HasMSA = true; 7711 else if (Feature == "+fp64") 7712 HasFP64 = true; 7713 else if (Feature == "-fp64") 7714 HasFP64 = false; 7715 else if (Feature == "+nan2008") 7716 IsNan2008 = true; 7717 else if (Feature == "-nan2008") 7718 IsNan2008 = false; 7719 } 7720 7721 setDataLayout(); 7722 7723 return true; 7724 } 7725 7726 int getEHDataRegisterNumber(unsigned RegNo) const override { 7727 if (RegNo == 0) return 4; 7728 if (RegNo == 1) return 5; 7729 return -1; 7730 } 7731 7732 bool isCLZForZeroUndef() const override { return false; } 7733 7734 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7735 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 7736 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7737 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7738 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 7739 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 7740 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 7741 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7742 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7743 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7744 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7745 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7746 {{"ra"}, "$31"}}; 7747 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 7748 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 7749 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 7750 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 7751 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 7752 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 7753 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 7754 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 7755 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 7756 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 7757 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 7758 {{"ra"}, "$31"}}; 7759 if (ABI == "o32") 7760 return llvm::makeArrayRef(O32RegAliases); 7761 return llvm::makeArrayRef(NewABIRegAliases); 7762 } 7763 7764 bool hasInt128Type() const override { 7765 return ABI == "n32" || ABI == "n64"; 7766 } 7767 7768 bool validateTarget(DiagnosticsEngine &Diags) const override { 7769 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 7770 // this yet. It's better to fail here than on the backend assertion. 7771 if (processorSupportsGPR64() && ABI == "o32") { 7772 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7773 return false; 7774 } 7775 7776 // 64-bit ABI's require 64-bit CPU's. 7777 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 7778 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 7779 return false; 7780 } 7781 7782 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 7783 // can't handle this yet. It's better to fail here than on the 7784 // backend assertion. 7785 if ((getTriple().getArch() == llvm::Triple::mips64 || 7786 getTriple().getArch() == llvm::Triple::mips64el) && 7787 ABI == "o32") { 7788 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7789 << ABI << getTriple().str(); 7790 return false; 7791 } 7792 7793 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 7794 // can't handle this yet. It's better to fail here than on the 7795 // backend assertion. 7796 if ((getTriple().getArch() == llvm::Triple::mips || 7797 getTriple().getArch() == llvm::Triple::mipsel) && 7798 (ABI == "n32" || ABI == "n64")) { 7799 Diags.Report(diag::err_target_unsupported_abi_for_triple) 7800 << ABI << getTriple().str(); 7801 return false; 7802 } 7803 7804 return true; 7805 } 7806 }; 7807 7808 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 7809 #define BUILTIN(ID, TYPE, ATTRS) \ 7810 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7811 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7812 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7813 #include "clang/Basic/BuiltinsMips.def" 7814 }; 7815 7816 class PNaClTargetInfo : public TargetInfo { 7817 public: 7818 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7819 : TargetInfo(Triple) { 7820 this->LongAlign = 32; 7821 this->LongWidth = 32; 7822 this->PointerAlign = 32; 7823 this->PointerWidth = 32; 7824 this->IntMaxType = TargetInfo::SignedLongLong; 7825 this->Int64Type = TargetInfo::SignedLongLong; 7826 this->DoubleAlign = 64; 7827 this->LongDoubleWidth = 64; 7828 this->LongDoubleAlign = 64; 7829 this->SizeType = TargetInfo::UnsignedInt; 7830 this->PtrDiffType = TargetInfo::SignedInt; 7831 this->IntPtrType = TargetInfo::SignedInt; 7832 this->RegParmMax = 0; // Disallow regparm 7833 } 7834 7835 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7836 Builder.defineMacro("__le32__"); 7837 Builder.defineMacro("__pnacl__"); 7838 } 7839 void getTargetDefines(const LangOptions &Opts, 7840 MacroBuilder &Builder) const override { 7841 getArchDefines(Opts, Builder); 7842 } 7843 bool hasFeature(StringRef Feature) const override { 7844 return Feature == "pnacl"; 7845 } 7846 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7847 BuiltinVaListKind getBuiltinVaListKind() const override { 7848 return TargetInfo::PNaClABIBuiltinVaList; 7849 } 7850 ArrayRef<const char *> getGCCRegNames() const override; 7851 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7852 bool validateAsmConstraint(const char *&Name, 7853 TargetInfo::ConstraintInfo &Info) const override { 7854 return false; 7855 } 7856 7857 const char *getClobbers() const override { 7858 return ""; 7859 } 7860 }; 7861 7862 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7863 return None; 7864 } 7865 7866 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7867 return None; 7868 } 7869 7870 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7871 class NaClMips32TargetInfo : public MipsTargetInfo { 7872 public: 7873 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7874 : MipsTargetInfo(Triple, Opts) {} 7875 7876 BuiltinVaListKind getBuiltinVaListKind() const override { 7877 return TargetInfo::PNaClABIBuiltinVaList; 7878 } 7879 }; 7880 7881 class Le64TargetInfo : public TargetInfo { 7882 static const Builtin::Info BuiltinInfo[]; 7883 7884 public: 7885 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7886 : TargetInfo(Triple) { 7887 NoAsmVariants = true; 7888 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7889 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7890 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 7891 } 7892 7893 void getTargetDefines(const LangOptions &Opts, 7894 MacroBuilder &Builder) const override { 7895 DefineStd(Builder, "unix", Opts); 7896 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7897 Builder.defineMacro("__ELF__"); 7898 } 7899 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7900 return llvm::makeArrayRef(BuiltinInfo, 7901 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7902 } 7903 BuiltinVaListKind getBuiltinVaListKind() const override { 7904 return TargetInfo::PNaClABIBuiltinVaList; 7905 } 7906 const char *getClobbers() const override { return ""; } 7907 ArrayRef<const char *> getGCCRegNames() const override { 7908 return None; 7909 } 7910 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7911 return None; 7912 } 7913 bool validateAsmConstraint(const char *&Name, 7914 TargetInfo::ConstraintInfo &Info) const override { 7915 return false; 7916 } 7917 7918 bool hasProtectedVisibility() const override { return false; } 7919 }; 7920 7921 class WebAssemblyTargetInfo : public TargetInfo { 7922 static const Builtin::Info BuiltinInfo[]; 7923 7924 enum SIMDEnum { 7925 NoSIMD, 7926 SIMD128, 7927 } SIMDLevel; 7928 7929 public: 7930 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 7931 : TargetInfo(T), SIMDLevel(NoSIMD) { 7932 NoAsmVariants = true; 7933 SuitableAlign = 128; 7934 LargeArrayMinWidth = 128; 7935 LargeArrayAlign = 128; 7936 SimdDefaultAlign = 128; 7937 SigAtomicType = SignedLong; 7938 LongDoubleWidth = LongDoubleAlign = 128; 7939 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7940 SizeType = UnsignedInt; 7941 PtrDiffType = SignedInt; 7942 IntPtrType = SignedInt; 7943 } 7944 7945 protected: 7946 void getTargetDefines(const LangOptions &Opts, 7947 MacroBuilder &Builder) const override { 7948 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7949 if (SIMDLevel >= SIMD128) 7950 Builder.defineMacro("__wasm_simd128__"); 7951 } 7952 7953 private: 7954 bool 7955 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7956 StringRef CPU, 7957 const std::vector<std::string> &FeaturesVec) const override { 7958 if (CPU == "bleeding-edge") 7959 Features["simd128"] = true; 7960 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7961 } 7962 bool hasFeature(StringRef Feature) const final { 7963 return llvm::StringSwitch<bool>(Feature) 7964 .Case("simd128", SIMDLevel >= SIMD128) 7965 .Default(false); 7966 } 7967 bool handleTargetFeatures(std::vector<std::string> &Features, 7968 DiagnosticsEngine &Diags) final { 7969 for (const auto &Feature : Features) { 7970 if (Feature == "+simd128") { 7971 SIMDLevel = std::max(SIMDLevel, SIMD128); 7972 continue; 7973 } 7974 if (Feature == "-simd128") { 7975 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7976 continue; 7977 } 7978 7979 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7980 << "-target-feature"; 7981 return false; 7982 } 7983 return true; 7984 } 7985 bool setCPU(const std::string &Name) final { 7986 return llvm::StringSwitch<bool>(Name) 7987 .Case("mvp", true) 7988 .Case("bleeding-edge", true) 7989 .Case("generic", true) 7990 .Default(false); 7991 } 7992 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7993 return llvm::makeArrayRef(BuiltinInfo, 7994 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7995 } 7996 BuiltinVaListKind getBuiltinVaListKind() const final { 7997 return VoidPtrBuiltinVaList; 7998 } 7999 ArrayRef<const char *> getGCCRegNames() const final { 8000 return None; 8001 } 8002 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8003 return None; 8004 } 8005 bool 8006 validateAsmConstraint(const char *&Name, 8007 TargetInfo::ConstraintInfo &Info) const final { 8008 return false; 8009 } 8010 const char *getClobbers() const final { return ""; } 8011 bool isCLZForZeroUndef() const final { return false; } 8012 bool hasInt128Type() const final { return true; } 8013 IntType getIntTypeByWidth(unsigned BitWidth, 8014 bool IsSigned) const final { 8015 // WebAssembly prefers long long for explicitly 64-bit integers. 8016 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8017 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8018 } 8019 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8020 bool IsSigned) const final { 8021 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8022 return BitWidth == 64 8023 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8024 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8025 } 8026 }; 8027 8028 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8029 #define BUILTIN(ID, TYPE, ATTRS) \ 8030 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8031 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8032 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8033 #include "clang/Basic/BuiltinsWebAssembly.def" 8034 }; 8035 8036 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8037 public: 8038 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8039 const TargetOptions &Opts) 8040 : WebAssemblyTargetInfo(T, Opts) { 8041 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8042 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8043 } 8044 8045 protected: 8046 void getTargetDefines(const LangOptions &Opts, 8047 MacroBuilder &Builder) const override { 8048 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8049 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8050 } 8051 }; 8052 8053 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8054 public: 8055 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8056 const TargetOptions &Opts) 8057 : WebAssemblyTargetInfo(T, Opts) { 8058 LongAlign = LongWidth = 64; 8059 PointerAlign = PointerWidth = 64; 8060 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8061 SizeType = UnsignedLong; 8062 PtrDiffType = SignedLong; 8063 IntPtrType = SignedLong; 8064 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8065 } 8066 8067 protected: 8068 void getTargetDefines(const LangOptions &Opts, 8069 MacroBuilder &Builder) const override { 8070 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8071 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8072 } 8073 }; 8074 8075 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8076 #define BUILTIN(ID, TYPE, ATTRS) \ 8077 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8078 #include "clang/Basic/BuiltinsLe64.def" 8079 }; 8080 8081 static const unsigned SPIRAddrSpaceMap[] = { 8082 1, // opencl_global 8083 3, // opencl_local 8084 2, // opencl_constant 8085 4, // opencl_generic 8086 0, // cuda_device 8087 0, // cuda_constant 8088 0 // cuda_shared 8089 }; 8090 class SPIRTargetInfo : public TargetInfo { 8091 public: 8092 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8093 : TargetInfo(Triple) { 8094 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8095 "SPIR target must use unknown OS"); 8096 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8097 "SPIR target must use unknown environment type"); 8098 TLSSupported = false; 8099 LongWidth = LongAlign = 64; 8100 AddrSpaceMap = &SPIRAddrSpaceMap; 8101 UseAddrSpaceMapMangling = true; 8102 // Define available target features 8103 // These must be defined in sorted order! 8104 NoAsmVariants = true; 8105 } 8106 void getTargetDefines(const LangOptions &Opts, 8107 MacroBuilder &Builder) const override { 8108 DefineStd(Builder, "SPIR", Opts); 8109 } 8110 bool hasFeature(StringRef Feature) const override { 8111 return Feature == "spir"; 8112 } 8113 8114 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8115 const char *getClobbers() const override { return ""; } 8116 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8117 bool validateAsmConstraint(const char *&Name, 8118 TargetInfo::ConstraintInfo &info) const override { 8119 return true; 8120 } 8121 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8122 return None; 8123 } 8124 BuiltinVaListKind getBuiltinVaListKind() const override { 8125 return TargetInfo::VoidPtrBuiltinVaList; 8126 } 8127 8128 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8129 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8130 : CCCR_Warning; 8131 } 8132 8133 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8134 return CC_SpirFunction; 8135 } 8136 8137 void setSupportedOpenCLOpts() override { 8138 // Assume all OpenCL extensions and optional core features are supported 8139 // for SPIR since it is a generic target. 8140 getSupportedOpenCLOpts().setAll(); 8141 } 8142 }; 8143 8144 class SPIR32TargetInfo : public SPIRTargetInfo { 8145 public: 8146 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8147 : SPIRTargetInfo(Triple, Opts) { 8148 PointerWidth = PointerAlign = 32; 8149 SizeType = TargetInfo::UnsignedInt; 8150 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8151 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8152 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8153 } 8154 void getTargetDefines(const LangOptions &Opts, 8155 MacroBuilder &Builder) const override { 8156 DefineStd(Builder, "SPIR32", Opts); 8157 } 8158 }; 8159 8160 class SPIR64TargetInfo : public SPIRTargetInfo { 8161 public: 8162 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8163 : SPIRTargetInfo(Triple, Opts) { 8164 PointerWidth = PointerAlign = 64; 8165 SizeType = TargetInfo::UnsignedLong; 8166 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8167 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8168 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8169 } 8170 void getTargetDefines(const LangOptions &Opts, 8171 MacroBuilder &Builder) const override { 8172 DefineStd(Builder, "SPIR64", Opts); 8173 } 8174 }; 8175 8176 class XCoreTargetInfo : public TargetInfo { 8177 static const Builtin::Info BuiltinInfo[]; 8178 public: 8179 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8180 : TargetInfo(Triple) { 8181 NoAsmVariants = true; 8182 LongLongAlign = 32; 8183 SuitableAlign = 32; 8184 DoubleAlign = LongDoubleAlign = 32; 8185 SizeType = UnsignedInt; 8186 PtrDiffType = SignedInt; 8187 IntPtrType = SignedInt; 8188 WCharType = UnsignedChar; 8189 WIntType = UnsignedInt; 8190 UseZeroLengthBitfieldAlignment = true; 8191 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8192 "-f64:32-a:0:32-n32"); 8193 } 8194 void getTargetDefines(const LangOptions &Opts, 8195 MacroBuilder &Builder) const override { 8196 Builder.defineMacro("__XS1B__"); 8197 } 8198 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8199 return llvm::makeArrayRef(BuiltinInfo, 8200 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8201 } 8202 BuiltinVaListKind getBuiltinVaListKind() const override { 8203 return TargetInfo::VoidPtrBuiltinVaList; 8204 } 8205 const char *getClobbers() const override { 8206 return ""; 8207 } 8208 ArrayRef<const char *> getGCCRegNames() const override { 8209 static const char * const GCCRegNames[] = { 8210 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8211 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8212 }; 8213 return llvm::makeArrayRef(GCCRegNames); 8214 } 8215 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8216 return None; 8217 } 8218 bool validateAsmConstraint(const char *&Name, 8219 TargetInfo::ConstraintInfo &Info) const override { 8220 return false; 8221 } 8222 int getEHDataRegisterNumber(unsigned RegNo) const override { 8223 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8224 return (RegNo < 2)? RegNo : -1; 8225 } 8226 bool allowsLargerPreferedTypeAlignment() const override { 8227 return false; 8228 } 8229 }; 8230 8231 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8232 #define BUILTIN(ID, TYPE, ATTRS) \ 8233 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8234 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8235 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8236 #include "clang/Basic/BuiltinsXCore.def" 8237 }; 8238 8239 // x86_32 Android target 8240 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8241 public: 8242 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8243 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8244 SuitableAlign = 32; 8245 LongDoubleWidth = 64; 8246 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 8247 } 8248 }; 8249 8250 // x86_64 Android target 8251 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8252 public: 8253 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8254 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8255 LongDoubleFormat = &llvm::APFloat::IEEEquad; 8256 } 8257 8258 bool useFloat128ManglingForLongDouble() const override { 8259 return true; 8260 } 8261 }; 8262 8263 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8264 class RenderScript32TargetInfo : public ARMleTargetInfo { 8265 public: 8266 RenderScript32TargetInfo(const llvm::Triple &Triple, 8267 const TargetOptions &Opts) 8268 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8269 Triple.getOSName(), 8270 Triple.getEnvironmentName()), 8271 Opts) { 8272 IsRenderScriptTarget = true; 8273 LongWidth = LongAlign = 64; 8274 } 8275 void getTargetDefines(const LangOptions &Opts, 8276 MacroBuilder &Builder) const override { 8277 Builder.defineMacro("__RENDERSCRIPT__"); 8278 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8279 } 8280 }; 8281 8282 // 64-bit RenderScript is aarch64 8283 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8284 public: 8285 RenderScript64TargetInfo(const llvm::Triple &Triple, 8286 const TargetOptions &Opts) 8287 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8288 Triple.getOSName(), 8289 Triple.getEnvironmentName()), 8290 Opts) { 8291 IsRenderScriptTarget = true; 8292 } 8293 8294 void getTargetDefines(const LangOptions &Opts, 8295 MacroBuilder &Builder) const override { 8296 Builder.defineMacro("__RENDERSCRIPT__"); 8297 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8298 } 8299 }; 8300 8301 } // end anonymous namespace 8302 8303 //===----------------------------------------------------------------------===// 8304 // Driver code 8305 //===----------------------------------------------------------------------===// 8306 8307 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 8308 const TargetOptions &Opts) { 8309 llvm::Triple::OSType os = Triple.getOS(); 8310 8311 switch (Triple.getArch()) { 8312 default: 8313 return nullptr; 8314 8315 case llvm::Triple::xcore: 8316 return new XCoreTargetInfo(Triple, Opts); 8317 8318 case llvm::Triple::hexagon: 8319 return new HexagonTargetInfo(Triple, Opts); 8320 8321 case llvm::Triple::lanai: 8322 return new LanaiTargetInfo(Triple, Opts); 8323 8324 case llvm::Triple::aarch64: 8325 if (Triple.isOSDarwin()) 8326 return new DarwinAArch64TargetInfo(Triple, Opts); 8327 8328 switch (os) { 8329 case llvm::Triple::CloudABI: 8330 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 8331 case llvm::Triple::FreeBSD: 8332 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8333 case llvm::Triple::Fuchsia: 8334 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8335 case llvm::Triple::Linux: 8336 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8337 case llvm::Triple::NetBSD: 8338 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 8339 default: 8340 return new AArch64leTargetInfo(Triple, Opts); 8341 } 8342 8343 case llvm::Triple::aarch64_be: 8344 switch (os) { 8345 case llvm::Triple::FreeBSD: 8346 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8347 case llvm::Triple::Fuchsia: 8348 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8349 case llvm::Triple::Linux: 8350 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8351 case llvm::Triple::NetBSD: 8352 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 8353 default: 8354 return new AArch64beTargetInfo(Triple, Opts); 8355 } 8356 8357 case llvm::Triple::arm: 8358 case llvm::Triple::thumb: 8359 if (Triple.isOSBinFormatMachO()) 8360 return new DarwinARMTargetInfo(Triple, Opts); 8361 8362 switch (os) { 8363 case llvm::Triple::CloudABI: 8364 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 8365 case llvm::Triple::Linux: 8366 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 8367 case llvm::Triple::FreeBSD: 8368 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8369 case llvm::Triple::Fuchsia: 8370 return new FuchsiaTargetInfo<ARMleTargetInfo>(Triple, Opts); 8371 case llvm::Triple::NetBSD: 8372 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8373 case llvm::Triple::OpenBSD: 8374 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 8375 case llvm::Triple::Bitrig: 8376 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 8377 case llvm::Triple::RTEMS: 8378 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 8379 case llvm::Triple::NaCl: 8380 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 8381 case llvm::Triple::Win32: 8382 switch (Triple.getEnvironment()) { 8383 case llvm::Triple::Cygnus: 8384 return new CygwinARMTargetInfo(Triple, Opts); 8385 case llvm::Triple::GNU: 8386 return new MinGWARMTargetInfo(Triple, Opts); 8387 case llvm::Triple::Itanium: 8388 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 8389 case llvm::Triple::MSVC: 8390 default: // Assume MSVC for unknown environments 8391 return new MicrosoftARMleTargetInfo(Triple, Opts); 8392 } 8393 default: 8394 return new ARMleTargetInfo(Triple, Opts); 8395 } 8396 8397 case llvm::Triple::armeb: 8398 case llvm::Triple::thumbeb: 8399 if (Triple.isOSDarwin()) 8400 return new DarwinARMTargetInfo(Triple, Opts); 8401 8402 switch (os) { 8403 case llvm::Triple::Linux: 8404 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8405 case llvm::Triple::FreeBSD: 8406 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8407 case llvm::Triple::Fuchsia: 8408 return new FuchsiaTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8409 case llvm::Triple::NetBSD: 8410 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8411 case llvm::Triple::OpenBSD: 8412 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8413 case llvm::Triple::Bitrig: 8414 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8415 case llvm::Triple::RTEMS: 8416 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8417 case llvm::Triple::NaCl: 8418 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 8419 default: 8420 return new ARMbeTargetInfo(Triple, Opts); 8421 } 8422 8423 case llvm::Triple::bpfeb: 8424 case llvm::Triple::bpfel: 8425 return new BPFTargetInfo(Triple, Opts); 8426 8427 case llvm::Triple::msp430: 8428 return new MSP430TargetInfo(Triple, Opts); 8429 8430 case llvm::Triple::mips: 8431 switch (os) { 8432 case llvm::Triple::Linux: 8433 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8434 case llvm::Triple::RTEMS: 8435 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8436 case llvm::Triple::FreeBSD: 8437 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8438 case llvm::Triple::NetBSD: 8439 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8440 default: 8441 return new MipsTargetInfo(Triple, Opts); 8442 } 8443 8444 case llvm::Triple::mipsel: 8445 switch (os) { 8446 case llvm::Triple::Linux: 8447 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8448 case llvm::Triple::RTEMS: 8449 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8450 case llvm::Triple::FreeBSD: 8451 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8452 case llvm::Triple::NetBSD: 8453 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8454 case llvm::Triple::NaCl: 8455 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 8456 default: 8457 return new MipsTargetInfo(Triple, Opts); 8458 } 8459 8460 case llvm::Triple::mips64: 8461 switch (os) { 8462 case llvm::Triple::Linux: 8463 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8464 case llvm::Triple::RTEMS: 8465 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8466 case llvm::Triple::FreeBSD: 8467 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8468 case llvm::Triple::NetBSD: 8469 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8470 case llvm::Triple::OpenBSD: 8471 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8472 default: 8473 return new MipsTargetInfo(Triple, Opts); 8474 } 8475 8476 case llvm::Triple::mips64el: 8477 switch (os) { 8478 case llvm::Triple::Linux: 8479 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 8480 case llvm::Triple::RTEMS: 8481 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 8482 case llvm::Triple::FreeBSD: 8483 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8484 case llvm::Triple::NetBSD: 8485 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8486 case llvm::Triple::OpenBSD: 8487 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 8488 default: 8489 return new MipsTargetInfo(Triple, Opts); 8490 } 8491 8492 case llvm::Triple::le32: 8493 switch (os) { 8494 case llvm::Triple::NaCl: 8495 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 8496 default: 8497 return nullptr; 8498 } 8499 8500 case llvm::Triple::le64: 8501 return new Le64TargetInfo(Triple, Opts); 8502 8503 case llvm::Triple::ppc: 8504 if (Triple.isOSDarwin()) 8505 return new DarwinPPC32TargetInfo(Triple, Opts); 8506 switch (os) { 8507 case llvm::Triple::Linux: 8508 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 8509 case llvm::Triple::FreeBSD: 8510 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8511 case llvm::Triple::NetBSD: 8512 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8513 case llvm::Triple::OpenBSD: 8514 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 8515 case llvm::Triple::RTEMS: 8516 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 8517 default: 8518 return new PPC32TargetInfo(Triple, Opts); 8519 } 8520 8521 case llvm::Triple::ppc64: 8522 if (Triple.isOSDarwin()) 8523 return new DarwinPPC64TargetInfo(Triple, Opts); 8524 switch (os) { 8525 case llvm::Triple::Linux: 8526 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8527 case llvm::Triple::Lv2: 8528 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 8529 case llvm::Triple::FreeBSD: 8530 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8531 case llvm::Triple::NetBSD: 8532 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8533 default: 8534 return new PPC64TargetInfo(Triple, Opts); 8535 } 8536 8537 case llvm::Triple::ppc64le: 8538 switch (os) { 8539 case llvm::Triple::Linux: 8540 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 8541 case llvm::Triple::NetBSD: 8542 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 8543 default: 8544 return new PPC64TargetInfo(Triple, Opts); 8545 } 8546 8547 case llvm::Triple::nvptx: 8548 return new NVPTX32TargetInfo(Triple, Opts); 8549 case llvm::Triple::nvptx64: 8550 return new NVPTX64TargetInfo(Triple, Opts); 8551 8552 case llvm::Triple::amdgcn: 8553 case llvm::Triple::r600: 8554 return new AMDGPUTargetInfo(Triple, Opts); 8555 8556 case llvm::Triple::sparc: 8557 switch (os) { 8558 case llvm::Triple::Linux: 8559 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8560 case llvm::Triple::Solaris: 8561 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8562 case llvm::Triple::NetBSD: 8563 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8564 case llvm::Triple::OpenBSD: 8565 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8566 case llvm::Triple::RTEMS: 8567 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 8568 default: 8569 return new SparcV8TargetInfo(Triple, Opts); 8570 } 8571 8572 // The 'sparcel' architecture copies all the above cases except for Solaris. 8573 case llvm::Triple::sparcel: 8574 switch (os) { 8575 case llvm::Triple::Linux: 8576 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8577 case llvm::Triple::NetBSD: 8578 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8579 case llvm::Triple::OpenBSD: 8580 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8581 case llvm::Triple::RTEMS: 8582 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 8583 default: 8584 return new SparcV8elTargetInfo(Triple, Opts); 8585 } 8586 8587 case llvm::Triple::sparcv9: 8588 switch (os) { 8589 case llvm::Triple::Linux: 8590 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8591 case llvm::Triple::Solaris: 8592 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8593 case llvm::Triple::NetBSD: 8594 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8595 case llvm::Triple::OpenBSD: 8596 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8597 case llvm::Triple::FreeBSD: 8598 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 8599 default: 8600 return new SparcV9TargetInfo(Triple, Opts); 8601 } 8602 8603 case llvm::Triple::systemz: 8604 switch (os) { 8605 case llvm::Triple::Linux: 8606 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 8607 default: 8608 return new SystemZTargetInfo(Triple, Opts); 8609 } 8610 8611 case llvm::Triple::tce: 8612 return new TCETargetInfo(Triple, Opts); 8613 8614 case llvm::Triple::x86: 8615 if (Triple.isOSDarwin()) 8616 return new DarwinI386TargetInfo(Triple, Opts); 8617 8618 switch (os) { 8619 case llvm::Triple::CloudABI: 8620 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 8621 case llvm::Triple::Linux: { 8622 switch (Triple.getEnvironment()) { 8623 default: 8624 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 8625 case llvm::Triple::Android: 8626 return new AndroidX86_32TargetInfo(Triple, Opts); 8627 } 8628 } 8629 case llvm::Triple::DragonFly: 8630 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8631 case llvm::Triple::NetBSD: 8632 return new NetBSDI386TargetInfo(Triple, Opts); 8633 case llvm::Triple::OpenBSD: 8634 return new OpenBSDI386TargetInfo(Triple, Opts); 8635 case llvm::Triple::Bitrig: 8636 return new BitrigI386TargetInfo(Triple, Opts); 8637 case llvm::Triple::FreeBSD: 8638 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8639 case llvm::Triple::Fuchsia: 8640 return new FuchsiaTargetInfo<X86_32TargetInfo>(Triple, Opts); 8641 case llvm::Triple::KFreeBSD: 8642 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 8643 case llvm::Triple::Minix: 8644 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 8645 case llvm::Triple::Solaris: 8646 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 8647 case llvm::Triple::Win32: { 8648 switch (Triple.getEnvironment()) { 8649 case llvm::Triple::Cygnus: 8650 return new CygwinX86_32TargetInfo(Triple, Opts); 8651 case llvm::Triple::GNU: 8652 return new MinGWX86_32TargetInfo(Triple, Opts); 8653 case llvm::Triple::Itanium: 8654 case llvm::Triple::MSVC: 8655 default: // Assume MSVC for unknown environments 8656 return new MicrosoftX86_32TargetInfo(Triple, Opts); 8657 } 8658 } 8659 case llvm::Triple::Haiku: 8660 return new HaikuX86_32TargetInfo(Triple, Opts); 8661 case llvm::Triple::RTEMS: 8662 return new RTEMSX86_32TargetInfo(Triple, Opts); 8663 case llvm::Triple::NaCl: 8664 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 8665 case llvm::Triple::ELFIAMCU: 8666 return new MCUX86_32TargetInfo(Triple, Opts); 8667 default: 8668 return new X86_32TargetInfo(Triple, Opts); 8669 } 8670 8671 case llvm::Triple::x86_64: 8672 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 8673 return new DarwinX86_64TargetInfo(Triple, Opts); 8674 8675 switch (os) { 8676 case llvm::Triple::CloudABI: 8677 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 8678 case llvm::Triple::Linux: { 8679 switch (Triple.getEnvironment()) { 8680 default: 8681 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 8682 case llvm::Triple::Android: 8683 return new AndroidX86_64TargetInfo(Triple, Opts); 8684 } 8685 } 8686 case llvm::Triple::DragonFly: 8687 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8688 case llvm::Triple::NetBSD: 8689 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8690 case llvm::Triple::OpenBSD: 8691 return new OpenBSDX86_64TargetInfo(Triple, Opts); 8692 case llvm::Triple::Bitrig: 8693 return new BitrigX86_64TargetInfo(Triple, Opts); 8694 case llvm::Triple::FreeBSD: 8695 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8696 case llvm::Triple::Fuchsia: 8697 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 8698 case llvm::Triple::KFreeBSD: 8699 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 8700 case llvm::Triple::Solaris: 8701 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 8702 case llvm::Triple::Win32: { 8703 switch (Triple.getEnvironment()) { 8704 case llvm::Triple::Cygnus: 8705 return new CygwinX86_64TargetInfo(Triple, Opts); 8706 case llvm::Triple::GNU: 8707 return new MinGWX86_64TargetInfo(Triple, Opts); 8708 case llvm::Triple::MSVC: 8709 default: // Assume MSVC for unknown environments 8710 return new MicrosoftX86_64TargetInfo(Triple, Opts); 8711 } 8712 } 8713 case llvm::Triple::Haiku: 8714 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 8715 case llvm::Triple::NaCl: 8716 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 8717 case llvm::Triple::PS4: 8718 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 8719 default: 8720 return new X86_64TargetInfo(Triple, Opts); 8721 } 8722 8723 case llvm::Triple::spir: { 8724 if (Triple.getOS() != llvm::Triple::UnknownOS || 8725 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8726 return nullptr; 8727 return new SPIR32TargetInfo(Triple, Opts); 8728 } 8729 case llvm::Triple::spir64: { 8730 if (Triple.getOS() != llvm::Triple::UnknownOS || 8731 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8732 return nullptr; 8733 return new SPIR64TargetInfo(Triple, Opts); 8734 } 8735 case llvm::Triple::wasm32: 8736 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8737 return nullptr; 8738 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 8739 case llvm::Triple::wasm64: 8740 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8741 return nullptr; 8742 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 8743 8744 case llvm::Triple::renderscript32: 8745 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 8746 case llvm::Triple::renderscript64: 8747 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 8748 } 8749 } 8750 8751 /// CreateTargetInfo - Return the target info object for the specified target 8752 /// options. 8753 TargetInfo * 8754 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8755 const std::shared_ptr<TargetOptions> &Opts) { 8756 llvm::Triple Triple(Opts->Triple); 8757 8758 // Construct the target 8759 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 8760 if (!Target) { 8761 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8762 return nullptr; 8763 } 8764 Target->TargetOpts = Opts; 8765 8766 // Set the target CPU if specified. 8767 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8768 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8769 return nullptr; 8770 } 8771 8772 // Set the target ABI if specified. 8773 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8774 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8775 return nullptr; 8776 } 8777 8778 // Set the fp math unit. 8779 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8780 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8781 return nullptr; 8782 } 8783 8784 // Compute the default target features, we need the target to handle this 8785 // because features may have dependencies on one another. 8786 llvm::StringMap<bool> Features; 8787 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8788 Opts->FeaturesAsWritten)) 8789 return nullptr; 8790 8791 // Add the features to the compile options. 8792 Opts->Features.clear(); 8793 for (const auto &F : Features) 8794 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8795 8796 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8797 return nullptr; 8798 8799 Target->setSupportedOpenCLOpts(); 8800 8801 if (!Target->validateTarget(Diags)) 8802 return nullptr; 8803 8804 return Target.release(); 8805 } 8806