1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/MC/MCSectionMachO.h" 29 #include "llvm/Support/ErrorHandling.h" 30 #include <algorithm> 31 #include <memory> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const override { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 94 // AddressSanitizer doesn't play well with source fortification, which is on 95 // by default on Darwin. 96 if (Opts.Sanitize.has(SanitizerKind::Address)) 97 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // Set the appropriate OS version define. 142 if (Triple.isiOS()) { 143 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 144 char Str[6]; 145 Str[0] = '0' + Maj; 146 Str[1] = '0' + (Min / 10); 147 Str[2] = '0' + (Min % 10); 148 Str[3] = '0' + (Rev / 10); 149 Str[4] = '0' + (Rev % 10); 150 Str[5] = '\0'; 151 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 152 Str); 153 } else if (Triple.isMacOSX()) { 154 // Note that the Driver allows versions which aren't representable in the 155 // define (because we only get a single digit for the minor and micro 156 // revision numbers). So, we limit them to the maximum representable 157 // version. 158 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[7]; 160 if (Maj < 10 || (Maj == 10 && Min < 10)) { 161 Str[0] = '0' + (Maj / 10); 162 Str[1] = '0' + (Maj % 10); 163 Str[2] = '0' + std::min(Min, 9U); 164 Str[3] = '0' + std::min(Rev, 9U); 165 Str[4] = '\0'; 166 } else { 167 // Handle versions > 10.9. 168 Str[0] = '0' + (Maj / 10); 169 Str[1] = '0' + (Maj % 10); 170 Str[2] = '0' + (Min / 10); 171 Str[3] = '0' + (Min % 10); 172 Str[4] = '0' + (Rev / 10); 173 Str[5] = '0' + (Rev % 10); 174 Str[6] = '\0'; 175 } 176 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 177 } 178 179 // Tell users about the kernel if there is one. 180 if (Triple.isOSDarwin()) 181 Builder.defineMacro("__MACH__"); 182 183 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 184 } 185 186 namespace { 187 // CloudABI Target 188 template <typename Target> 189 class CloudABITargetInfo : public OSTargetInfo<Target> { 190 protected: 191 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 192 MacroBuilder &Builder) const override { 193 Builder.defineMacro("__CloudABI__"); 194 Builder.defineMacro("__ELF__"); 195 196 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 197 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 198 Builder.defineMacro("__STDC_UTF_16__"); 199 Builder.defineMacro("__STDC_UTF_32__"); 200 } 201 202 public: 203 CloudABITargetInfo(const llvm::Triple &Triple) 204 : OSTargetInfo<Target>(Triple) { 205 this->UserLabelPrefix = ""; 206 } 207 }; 208 209 template<typename Target> 210 class DarwinTargetInfo : public OSTargetInfo<Target> { 211 protected: 212 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 213 MacroBuilder &Builder) const override { 214 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 215 this->PlatformMinVersion); 216 } 217 218 public: 219 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 220 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 221 this->MCountName = "\01mcount"; 222 } 223 224 std::string isValidSectionSpecifier(StringRef SR) const override { 225 // Let MCSectionMachO validate this. 226 StringRef Segment, Section; 227 unsigned TAA, StubSize; 228 bool HasTAA; 229 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 230 TAA, HasTAA, StubSize); 231 } 232 233 const char *getStaticInitSectionSpecifier() const override { 234 // FIXME: We should return 0 when building kexts. 235 return "__TEXT,__StaticInit,regular,pure_instructions"; 236 } 237 238 /// Darwin does not support protected visibility. Darwin's "default" 239 /// is very similar to ELF's "protected"; Darwin requires a "weak" 240 /// attribute on declarations that can be dynamically replaced. 241 bool hasProtectedVisibility() const override { 242 return false; 243 } 244 }; 245 246 247 // DragonFlyBSD Target 248 template<typename Target> 249 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 250 protected: 251 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 252 MacroBuilder &Builder) const override { 253 // DragonFly defines; list based off of gcc output 254 Builder.defineMacro("__DragonFly__"); 255 Builder.defineMacro("__DragonFly_cc_version", "100001"); 256 Builder.defineMacro("__ELF__"); 257 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 258 Builder.defineMacro("__tune_i386__"); 259 DefineStd(Builder, "unix", Opts); 260 } 261 public: 262 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 263 : OSTargetInfo<Target>(Triple) { 264 this->UserLabelPrefix = ""; 265 266 switch (Triple.getArch()) { 267 default: 268 case llvm::Triple::x86: 269 case llvm::Triple::x86_64: 270 this->MCountName = ".mcount"; 271 break; 272 } 273 } 274 }; 275 276 // FreeBSD Target 277 template<typename Target> 278 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 279 protected: 280 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 281 MacroBuilder &Builder) const override { 282 // FreeBSD defines; list based off of gcc output 283 284 unsigned Release = Triple.getOSMajorVersion(); 285 if (Release == 0U) 286 Release = 8; 287 288 Builder.defineMacro("__FreeBSD__", Twine(Release)); 289 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 290 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 291 DefineStd(Builder, "unix", Opts); 292 Builder.defineMacro("__ELF__"); 293 294 // On FreeBSD, wchar_t contains the number of the code point as 295 // used by the character set of the locale. These character sets are 296 // not necessarily a superset of ASCII. 297 // 298 // FIXME: This is wrong; the macro refers to the numerical values 299 // of wchar_t *literals*, which are not locale-dependent. However, 300 // FreeBSD systems apparently depend on us getting this wrong, and 301 // setting this to 1 is conforming even if all the basic source 302 // character literals have the same encoding as char and wchar_t. 303 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 304 } 305 public: 306 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 307 this->UserLabelPrefix = ""; 308 309 switch (Triple.getArch()) { 310 default: 311 case llvm::Triple::x86: 312 case llvm::Triple::x86_64: 313 this->MCountName = ".mcount"; 314 break; 315 case llvm::Triple::mips: 316 case llvm::Triple::mipsel: 317 case llvm::Triple::ppc: 318 case llvm::Triple::ppc64: 319 case llvm::Triple::ppc64le: 320 this->MCountName = "_mcount"; 321 break; 322 case llvm::Triple::arm: 323 this->MCountName = "__mcount"; 324 break; 325 } 326 } 327 }; 328 329 // GNU/kFreeBSD Target 330 template<typename Target> 331 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // GNU/kFreeBSD defines; list based off of gcc output 336 337 DefineStd(Builder, "unix", Opts); 338 Builder.defineMacro("__FreeBSD_kernel__"); 339 Builder.defineMacro("__GLIBC__"); 340 Builder.defineMacro("__ELF__"); 341 if (Opts.POSIXThreads) 342 Builder.defineMacro("_REENTRANT"); 343 if (Opts.CPlusPlus) 344 Builder.defineMacro("_GNU_SOURCE"); 345 } 346 public: 347 KFreeBSDTargetInfo(const llvm::Triple &Triple) 348 : OSTargetInfo<Target>(Triple) { 349 this->UserLabelPrefix = ""; 350 } 351 }; 352 353 // Minix Target 354 template<typename Target> 355 class MinixTargetInfo : public OSTargetInfo<Target> { 356 protected: 357 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 358 MacroBuilder &Builder) const override { 359 // Minix defines 360 361 Builder.defineMacro("__minix", "3"); 362 Builder.defineMacro("_EM_WSIZE", "4"); 363 Builder.defineMacro("_EM_PSIZE", "4"); 364 Builder.defineMacro("_EM_SSIZE", "2"); 365 Builder.defineMacro("_EM_LSIZE", "4"); 366 Builder.defineMacro("_EM_FSIZE", "4"); 367 Builder.defineMacro("_EM_DSIZE", "8"); 368 Builder.defineMacro("__ELF__"); 369 DefineStd(Builder, "unix", Opts); 370 } 371 public: 372 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 373 this->UserLabelPrefix = ""; 374 } 375 }; 376 377 // Linux target 378 template<typename Target> 379 class LinuxTargetInfo : public OSTargetInfo<Target> { 380 protected: 381 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 382 MacroBuilder &Builder) const override { 383 // Linux defines; list based off of gcc output 384 DefineStd(Builder, "unix", Opts); 385 DefineStd(Builder, "linux", Opts); 386 Builder.defineMacro("__gnu_linux__"); 387 Builder.defineMacro("__ELF__"); 388 if (Triple.getEnvironment() == llvm::Triple::Android) { 389 Builder.defineMacro("__ANDROID__", "1"); 390 unsigned Maj, Min, Rev; 391 Triple.getOSVersion(Maj, Min, Rev); 392 this->PlatformName = "android"; 393 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 394 } 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 if (Opts.CPlusPlus) 398 Builder.defineMacro("_GNU_SOURCE"); 399 } 400 public: 401 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 402 this->UserLabelPrefix = ""; 403 this->WIntType = TargetInfo::UnsignedInt; 404 405 switch (Triple.getArch()) { 406 default: 407 break; 408 case llvm::Triple::ppc: 409 case llvm::Triple::ppc64: 410 case llvm::Triple::ppc64le: 411 this->MCountName = "_mcount"; 412 break; 413 } 414 } 415 416 const char *getStaticInitSectionSpecifier() const override { 417 return ".text.startup"; 418 } 419 }; 420 421 // NetBSD Target 422 template<typename Target> 423 class NetBSDTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const override { 427 // NetBSD defines; list based off of gcc output 428 Builder.defineMacro("__NetBSD__"); 429 Builder.defineMacro("__unix__"); 430 Builder.defineMacro("__ELF__"); 431 if (Opts.POSIXThreads) 432 Builder.defineMacro("_POSIX_THREADS"); 433 434 switch (Triple.getArch()) { 435 default: 436 break; 437 case llvm::Triple::arm: 438 case llvm::Triple::armeb: 439 case llvm::Triple::thumb: 440 case llvm::Triple::thumbeb: 441 Builder.defineMacro("__ARM_DWARF_EH__"); 442 break; 443 } 444 } 445 public: 446 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 447 this->UserLabelPrefix = ""; 448 this->MCountName = "_mcount"; 449 } 450 }; 451 452 // OpenBSD Target 453 template<typename Target> 454 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // OpenBSD defines; list based off of gcc output 459 460 Builder.defineMacro("__OpenBSD__"); 461 DefineStd(Builder, "unix", Opts); 462 Builder.defineMacro("__ELF__"); 463 if (Opts.POSIXThreads) 464 Builder.defineMacro("_REENTRANT"); 465 } 466 public: 467 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 468 this->UserLabelPrefix = ""; 469 this->TLSSupported = false; 470 471 switch (Triple.getArch()) { 472 default: 473 case llvm::Triple::x86: 474 case llvm::Triple::x86_64: 475 case llvm::Triple::arm: 476 case llvm::Triple::sparc: 477 this->MCountName = "__mcount"; 478 break; 479 case llvm::Triple::mips64: 480 case llvm::Triple::mips64el: 481 case llvm::Triple::ppc: 482 case llvm::Triple::sparcv9: 483 this->MCountName = "_mcount"; 484 break; 485 } 486 } 487 }; 488 489 // Bitrig Target 490 template<typename Target> 491 class BitrigTargetInfo : public OSTargetInfo<Target> { 492 protected: 493 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 494 MacroBuilder &Builder) const override { 495 // Bitrig defines; list based off of gcc output 496 497 Builder.defineMacro("__Bitrig__"); 498 DefineStd(Builder, "unix", Opts); 499 Builder.defineMacro("__ELF__"); 500 if (Opts.POSIXThreads) 501 Builder.defineMacro("_REENTRANT"); 502 503 switch (Triple.getArch()) { 504 default: 505 break; 506 case llvm::Triple::arm: 507 case llvm::Triple::armeb: 508 case llvm::Triple::thumb: 509 case llvm::Triple::thumbeb: 510 Builder.defineMacro("__ARM_DWARF_EH__"); 511 break; 512 } 513 } 514 public: 515 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 516 this->UserLabelPrefix = ""; 517 this->MCountName = "__mcount"; 518 } 519 }; 520 521 // PSP Target 522 template<typename Target> 523 class PSPTargetInfo : public OSTargetInfo<Target> { 524 protected: 525 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 526 MacroBuilder &Builder) const override { 527 // PSP defines; list based on the output of the pspdev gcc toolchain. 528 Builder.defineMacro("PSP"); 529 Builder.defineMacro("_PSP"); 530 Builder.defineMacro("__psp__"); 531 Builder.defineMacro("__ELF__"); 532 } 533 public: 534 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 535 this->UserLabelPrefix = ""; 536 } 537 }; 538 539 // PS3 PPU Target 540 template<typename Target> 541 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 542 protected: 543 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 544 MacroBuilder &Builder) const override { 545 // PS3 PPU defines. 546 Builder.defineMacro("__PPC__"); 547 Builder.defineMacro("__PPU__"); 548 Builder.defineMacro("__CELLOS_LV2__"); 549 Builder.defineMacro("__ELF__"); 550 Builder.defineMacro("__LP32__"); 551 Builder.defineMacro("_ARCH_PPC64"); 552 Builder.defineMacro("__powerpc64__"); 553 } 554 public: 555 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 556 this->UserLabelPrefix = ""; 557 this->LongWidth = this->LongAlign = 32; 558 this->PointerWidth = this->PointerAlign = 32; 559 this->IntMaxType = TargetInfo::SignedLongLong; 560 this->Int64Type = TargetInfo::SignedLongLong; 561 this->SizeType = TargetInfo::UnsignedInt; 562 this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64"; 563 } 564 }; 565 566 template <typename Target> 567 class PS4OSTargetInfo : public OSTargetInfo<Target> { 568 protected: 569 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 570 MacroBuilder &Builder) const override { 571 Builder.defineMacro("__FreeBSD__", "9"); 572 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 573 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 574 DefineStd(Builder, "unix", Opts); 575 Builder.defineMacro("__ELF__"); 576 Builder.defineMacro("__PS4__"); 577 } 578 public: 579 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 580 this->WCharType = this->UnsignedShort; 581 582 this->UserLabelPrefix = ""; 583 584 switch (Triple.getArch()) { 585 default: 586 case llvm::Triple::x86_64: 587 this->MCountName = ".mcount"; 588 break; 589 } 590 } 591 }; 592 593 // Solaris target 594 template<typename Target> 595 class SolarisTargetInfo : public OSTargetInfo<Target> { 596 protected: 597 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 598 MacroBuilder &Builder) const override { 599 DefineStd(Builder, "sun", Opts); 600 DefineStd(Builder, "unix", Opts); 601 Builder.defineMacro("__ELF__"); 602 Builder.defineMacro("__svr4__"); 603 Builder.defineMacro("__SVR4"); 604 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 605 // newer, but to 500 for everything else. feature_test.h has a check to 606 // ensure that you are not using C99 with an old version of X/Open or C89 607 // with a new version. 608 if (Opts.C99) 609 Builder.defineMacro("_XOPEN_SOURCE", "600"); 610 else 611 Builder.defineMacro("_XOPEN_SOURCE", "500"); 612 if (Opts.CPlusPlus) 613 Builder.defineMacro("__C99FEATURES__"); 614 Builder.defineMacro("_LARGEFILE_SOURCE"); 615 Builder.defineMacro("_LARGEFILE64_SOURCE"); 616 Builder.defineMacro("__EXTENSIONS__"); 617 Builder.defineMacro("_REENTRANT"); 618 } 619 public: 620 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 621 this->UserLabelPrefix = ""; 622 this->WCharType = this->SignedInt; 623 // FIXME: WIntType should be SignedLong 624 } 625 }; 626 627 // Windows target 628 template<typename Target> 629 class WindowsTargetInfo : public OSTargetInfo<Target> { 630 protected: 631 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 632 MacroBuilder &Builder) const override { 633 Builder.defineMacro("_WIN32"); 634 } 635 void getVisualStudioDefines(const LangOptions &Opts, 636 MacroBuilder &Builder) const { 637 if (Opts.CPlusPlus) { 638 if (Opts.RTTIData) 639 Builder.defineMacro("_CPPRTTI"); 640 641 if (Opts.CXXExceptions) 642 Builder.defineMacro("_CPPUNWIND"); 643 } 644 645 if (!Opts.CharIsSigned) 646 Builder.defineMacro("_CHAR_UNSIGNED"); 647 648 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 649 // but it works for now. 650 if (Opts.POSIXThreads) 651 Builder.defineMacro("_MT"); 652 653 if (Opts.MSCompatibilityVersion) { 654 Builder.defineMacro("_MSC_VER", 655 Twine(Opts.MSCompatibilityVersion / 100000)); 656 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 657 // FIXME We cannot encode the revision information into 32-bits 658 Builder.defineMacro("_MSC_BUILD", Twine(1)); 659 660 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 661 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 662 } 663 664 if (Opts.MicrosoftExt) { 665 Builder.defineMacro("_MSC_EXTENSIONS"); 666 667 if (Opts.CPlusPlus11) { 668 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 669 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 670 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 671 } 672 } 673 674 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 675 } 676 677 public: 678 WindowsTargetInfo(const llvm::Triple &Triple) 679 : OSTargetInfo<Target>(Triple) {} 680 }; 681 682 template <typename Target> 683 class NaClTargetInfo : public OSTargetInfo<Target> { 684 protected: 685 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 686 MacroBuilder &Builder) const override { 687 if (Opts.POSIXThreads) 688 Builder.defineMacro("_REENTRANT"); 689 if (Opts.CPlusPlus) 690 Builder.defineMacro("_GNU_SOURCE"); 691 692 DefineStd(Builder, "unix", Opts); 693 Builder.defineMacro("__ELF__"); 694 Builder.defineMacro("__native_client__"); 695 } 696 697 public: 698 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 699 this->UserLabelPrefix = ""; 700 this->LongAlign = 32; 701 this->LongWidth = 32; 702 this->PointerAlign = 32; 703 this->PointerWidth = 32; 704 this->IntMaxType = TargetInfo::SignedLongLong; 705 this->Int64Type = TargetInfo::SignedLongLong; 706 this->DoubleAlign = 64; 707 this->LongDoubleWidth = 64; 708 this->LongDoubleAlign = 64; 709 this->LongLongWidth = 64; 710 this->LongLongAlign = 64; 711 this->SizeType = TargetInfo::UnsignedInt; 712 this->PtrDiffType = TargetInfo::SignedInt; 713 this->IntPtrType = TargetInfo::SignedInt; 714 // RegParmMax is inherited from the underlying architecture 715 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 716 if (Triple.getArch() == llvm::Triple::arm) { 717 // Handled in ARM's setABI(). 718 } else if (Triple.getArch() == llvm::Triple::x86) { 719 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 720 } else if (Triple.getArch() == llvm::Triple::x86_64) { 721 this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 722 } else if (Triple.getArch() == llvm::Triple::mipsel) { 723 // Handled on mips' setDescriptionString. 724 } else { 725 assert(Triple.getArch() == llvm::Triple::le32); 726 this->DescriptionString = "e-p:32:32-i64:64"; 727 } 728 } 729 }; 730 731 //===----------------------------------------------------------------------===// 732 // Specific target implementations. 733 //===----------------------------------------------------------------------===// 734 735 // PPC abstract base class 736 class PPCTargetInfo : public TargetInfo { 737 static const Builtin::Info BuiltinInfo[]; 738 static const char * const GCCRegNames[]; 739 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 740 std::string CPU; 741 742 // Target cpu features. 743 bool HasVSX; 744 bool HasP8Vector; 745 bool HasP8Crypto; 746 bool HasDirectMove; 747 bool HasQPX; 748 bool HasHTM; 749 bool HasBPERMD; 750 bool HasExtDiv; 751 752 protected: 753 std::string ABI; 754 755 public: 756 PPCTargetInfo(const llvm::Triple &Triple) 757 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 758 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 759 HasBPERMD(false), HasExtDiv(false) { 760 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 761 LongDoubleWidth = LongDoubleAlign = 128; 762 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 763 } 764 765 /// \brief Flags for architecture specific defines. 766 typedef enum { 767 ArchDefineNone = 0, 768 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 769 ArchDefinePpcgr = 1 << 1, 770 ArchDefinePpcsq = 1 << 2, 771 ArchDefine440 = 1 << 3, 772 ArchDefine603 = 1 << 4, 773 ArchDefine604 = 1 << 5, 774 ArchDefinePwr4 = 1 << 6, 775 ArchDefinePwr5 = 1 << 7, 776 ArchDefinePwr5x = 1 << 8, 777 ArchDefinePwr6 = 1 << 9, 778 ArchDefinePwr6x = 1 << 10, 779 ArchDefinePwr7 = 1 << 11, 780 ArchDefinePwr8 = 1 << 12, 781 ArchDefineA2 = 1 << 13, 782 ArchDefineA2q = 1 << 14 783 } ArchDefineTypes; 784 785 // Note: GCC recognizes the following additional cpus: 786 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 787 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 788 // titan, rs64. 789 bool setCPU(const std::string &Name) override { 790 bool CPUKnown = llvm::StringSwitch<bool>(Name) 791 .Case("generic", true) 792 .Case("440", true) 793 .Case("450", true) 794 .Case("601", true) 795 .Case("602", true) 796 .Case("603", true) 797 .Case("603e", true) 798 .Case("603ev", true) 799 .Case("604", true) 800 .Case("604e", true) 801 .Case("620", true) 802 .Case("630", true) 803 .Case("g3", true) 804 .Case("7400", true) 805 .Case("g4", true) 806 .Case("7450", true) 807 .Case("g4+", true) 808 .Case("750", true) 809 .Case("970", true) 810 .Case("g5", true) 811 .Case("a2", true) 812 .Case("a2q", true) 813 .Case("e500mc", true) 814 .Case("e5500", true) 815 .Case("power3", true) 816 .Case("pwr3", true) 817 .Case("power4", true) 818 .Case("pwr4", true) 819 .Case("power5", true) 820 .Case("pwr5", true) 821 .Case("power5x", true) 822 .Case("pwr5x", true) 823 .Case("power6", true) 824 .Case("pwr6", true) 825 .Case("power6x", true) 826 .Case("pwr6x", true) 827 .Case("power7", true) 828 .Case("pwr7", true) 829 .Case("power8", true) 830 .Case("pwr8", true) 831 .Case("powerpc", true) 832 .Case("ppc", true) 833 .Case("powerpc64", true) 834 .Case("ppc64", true) 835 .Case("powerpc64le", true) 836 .Case("ppc64le", true) 837 .Default(false); 838 839 if (CPUKnown) 840 CPU = Name; 841 842 return CPUKnown; 843 } 844 845 846 StringRef getABI() const override { return ABI; } 847 848 void getTargetBuiltins(const Builtin::Info *&Records, 849 unsigned &NumRecords) const override { 850 Records = BuiltinInfo; 851 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 852 } 853 854 bool isCLZForZeroUndef() const override { return false; } 855 856 void getTargetDefines(const LangOptions &Opts, 857 MacroBuilder &Builder) const override; 858 859 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 860 861 bool handleTargetFeatures(std::vector<std::string> &Features, 862 DiagnosticsEngine &Diags) override; 863 bool hasFeature(StringRef Feature) const override; 864 865 void getGCCRegNames(const char * const *&Names, 866 unsigned &NumNames) const override; 867 void getGCCRegAliases(const GCCRegAlias *&Aliases, 868 unsigned &NumAliases) const override; 869 bool validateAsmConstraint(const char *&Name, 870 TargetInfo::ConstraintInfo &Info) const override { 871 switch (*Name) { 872 default: return false; 873 case 'O': // Zero 874 break; 875 case 'b': // Base register 876 case 'f': // Floating point register 877 Info.setAllowsRegister(); 878 break; 879 // FIXME: The following are added to allow parsing. 880 // I just took a guess at what the actions should be. 881 // Also, is more specific checking needed? I.e. specific registers? 882 case 'd': // Floating point register (containing 64-bit value) 883 case 'v': // Altivec vector register 884 Info.setAllowsRegister(); 885 break; 886 case 'w': 887 switch (Name[1]) { 888 case 'd':// VSX vector register to hold vector double data 889 case 'f':// VSX vector register to hold vector float data 890 case 's':// VSX vector register to hold scalar float data 891 case 'a':// Any VSX register 892 case 'c':// An individual CR bit 893 break; 894 default: 895 return false; 896 } 897 Info.setAllowsRegister(); 898 Name++; // Skip over 'w'. 899 break; 900 case 'h': // `MQ', `CTR', or `LINK' register 901 case 'q': // `MQ' register 902 case 'c': // `CTR' register 903 case 'l': // `LINK' register 904 case 'x': // `CR' register (condition register) number 0 905 case 'y': // `CR' register (condition register) 906 case 'z': // `XER[CA]' carry bit (part of the XER register) 907 Info.setAllowsRegister(); 908 break; 909 case 'I': // Signed 16-bit constant 910 case 'J': // Unsigned 16-bit constant shifted left 16 bits 911 // (use `L' instead for SImode constants) 912 case 'K': // Unsigned 16-bit constant 913 case 'L': // Signed 16-bit constant shifted left 16 bits 914 case 'M': // Constant larger than 31 915 case 'N': // Exact power of 2 916 case 'P': // Constant whose negation is a signed 16-bit constant 917 case 'G': // Floating point constant that can be loaded into a 918 // register with one instruction per word 919 case 'H': // Integer/Floating point constant that can be loaded 920 // into a register using three instructions 921 break; 922 case 'm': // Memory operand. Note that on PowerPC targets, m can 923 // include addresses that update the base register. It 924 // is therefore only safe to use `m' in an asm statement 925 // if that asm statement accesses the operand exactly once. 926 // The asm statement must also use `%U<opno>' as a 927 // placeholder for the "update" flag in the corresponding 928 // load or store instruction. For example: 929 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 930 // is correct but: 931 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 932 // is not. Use es rather than m if you don't want the base 933 // register to be updated. 934 case 'e': 935 if (Name[1] != 's') 936 return false; 937 // es: A "stable" memory operand; that is, one which does not 938 // include any automodification of the base register. Unlike 939 // `m', this constraint can be used in asm statements that 940 // might access the operand several times, or that might not 941 // access it at all. 942 Info.setAllowsMemory(); 943 Name++; // Skip over 'e'. 944 break; 945 case 'Q': // Memory operand that is an offset from a register (it is 946 // usually better to use `m' or `es' in asm statements) 947 case 'Z': // Memory operand that is an indexed or indirect from a 948 // register (it is usually better to use `m' or `es' in 949 // asm statements) 950 Info.setAllowsMemory(); 951 Info.setAllowsRegister(); 952 break; 953 case 'R': // AIX TOC entry 954 case 'a': // Address operand that is an indexed or indirect from a 955 // register (`p' is preferable for asm statements) 956 case 'S': // Constant suitable as a 64-bit mask operand 957 case 'T': // Constant suitable as a 32-bit mask operand 958 case 'U': // System V Release 4 small data area reference 959 case 't': // AND masks that can be performed by two rldic{l, r} 960 // instructions 961 case 'W': // Vector constant that does not require memory 962 case 'j': // Vector constant that is all zeros. 963 break; 964 // End FIXME. 965 } 966 return true; 967 } 968 std::string convertConstraint(const char *&Constraint) const override { 969 std::string R; 970 switch (*Constraint) { 971 case 'e': 972 case 'w': 973 // Two-character constraint; add "^" hint for later parsing. 974 R = std::string("^") + std::string(Constraint, 2); 975 Constraint++; 976 break; 977 default: 978 return TargetInfo::convertConstraint(Constraint); 979 } 980 return R; 981 } 982 const char *getClobbers() const override { 983 return ""; 984 } 985 int getEHDataRegisterNumber(unsigned RegNo) const override { 986 if (RegNo == 0) return 3; 987 if (RegNo == 1) return 4; 988 return -1; 989 } 990 991 bool hasSjLjLowering() const override { 992 return true; 993 } 994 }; 995 996 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 997 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 998 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 999 ALL_LANGUAGES }, 1000 #include "clang/Basic/BuiltinsPPC.def" 1001 }; 1002 1003 /// handleTargetFeatures - Perform initialization based on the user 1004 /// configured set of features. 1005 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1006 DiagnosticsEngine &Diags) { 1007 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 1008 // Ignore disabled features. 1009 if (Features[i][0] == '-') 1010 continue; 1011 1012 StringRef Feature = StringRef(Features[i]).substr(1); 1013 1014 if (Feature == "vsx") { 1015 HasVSX = true; 1016 continue; 1017 } 1018 1019 if (Feature == "bpermd") { 1020 HasBPERMD = true; 1021 continue; 1022 } 1023 1024 if (Feature == "extdiv") { 1025 HasExtDiv = true; 1026 continue; 1027 } 1028 1029 if (Feature == "power8-vector") { 1030 HasP8Vector = true; 1031 HasVSX = true; 1032 continue; 1033 } 1034 1035 if (Feature == "crypto") { 1036 HasP8Crypto = true; 1037 continue; 1038 } 1039 1040 if (Feature == "direct-move") { 1041 HasDirectMove = true; 1042 HasVSX = true; 1043 continue; 1044 } 1045 1046 if (Feature == "qpx") { 1047 HasQPX = true; 1048 continue; 1049 } 1050 1051 if (Feature == "htm") { 1052 HasHTM = true; 1053 continue; 1054 } 1055 1056 // TODO: Finish this list and add an assert that we've handled them 1057 // all. 1058 } 1059 1060 return true; 1061 } 1062 1063 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1064 /// #defines that are not tied to a specific subtarget. 1065 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1066 MacroBuilder &Builder) const { 1067 // Target identification. 1068 Builder.defineMacro("__ppc__"); 1069 Builder.defineMacro("__PPC__"); 1070 Builder.defineMacro("_ARCH_PPC"); 1071 Builder.defineMacro("__powerpc__"); 1072 Builder.defineMacro("__POWERPC__"); 1073 if (PointerWidth == 64) { 1074 Builder.defineMacro("_ARCH_PPC64"); 1075 Builder.defineMacro("__powerpc64__"); 1076 Builder.defineMacro("__ppc64__"); 1077 Builder.defineMacro("__PPC64__"); 1078 } 1079 1080 // Target properties. 1081 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1082 Builder.defineMacro("_LITTLE_ENDIAN"); 1083 } else { 1084 if (getTriple().getOS() != llvm::Triple::NetBSD && 1085 getTriple().getOS() != llvm::Triple::OpenBSD) 1086 Builder.defineMacro("_BIG_ENDIAN"); 1087 } 1088 1089 // ABI options. 1090 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1091 Builder.defineMacro("_CALL_ELF", "1"); 1092 if (ABI == "elfv2") 1093 Builder.defineMacro("_CALL_ELF", "2"); 1094 1095 // Subtarget options. 1096 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1097 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1098 1099 // FIXME: Should be controlled by command line option. 1100 if (LongDoubleWidth == 128) 1101 Builder.defineMacro("__LONG_DOUBLE_128__"); 1102 1103 if (Opts.AltiVec) { 1104 Builder.defineMacro("__VEC__", "10206"); 1105 Builder.defineMacro("__ALTIVEC__"); 1106 } 1107 1108 // CPU identification. 1109 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1110 .Case("440", ArchDefineName) 1111 .Case("450", ArchDefineName | ArchDefine440) 1112 .Case("601", ArchDefineName) 1113 .Case("602", ArchDefineName | ArchDefinePpcgr) 1114 .Case("603", ArchDefineName | ArchDefinePpcgr) 1115 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1116 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1117 .Case("604", ArchDefineName | ArchDefinePpcgr) 1118 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1119 .Case("620", ArchDefineName | ArchDefinePpcgr) 1120 .Case("630", ArchDefineName | ArchDefinePpcgr) 1121 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1122 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1123 .Case("750", ArchDefineName | ArchDefinePpcgr) 1124 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1125 | ArchDefinePpcsq) 1126 .Case("a2", ArchDefineA2) 1127 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1128 .Case("pwr3", ArchDefinePpcgr) 1129 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1130 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1131 | ArchDefinePpcsq) 1132 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1133 | ArchDefinePpcgr | ArchDefinePpcsq) 1134 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1135 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1136 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1137 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1138 | ArchDefinePpcsq) 1139 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1140 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1141 | ArchDefinePpcgr | ArchDefinePpcsq) 1142 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1143 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1144 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1145 .Case("power3", ArchDefinePpcgr) 1146 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1147 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1148 | ArchDefinePpcsq) 1149 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1150 | ArchDefinePpcgr | ArchDefinePpcsq) 1151 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1152 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1153 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1154 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1155 | ArchDefinePpcsq) 1156 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1157 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1158 | ArchDefinePpcgr | ArchDefinePpcsq) 1159 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1160 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1161 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1162 .Default(ArchDefineNone); 1163 1164 if (defs & ArchDefineName) 1165 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1166 if (defs & ArchDefinePpcgr) 1167 Builder.defineMacro("_ARCH_PPCGR"); 1168 if (defs & ArchDefinePpcsq) 1169 Builder.defineMacro("_ARCH_PPCSQ"); 1170 if (defs & ArchDefine440) 1171 Builder.defineMacro("_ARCH_440"); 1172 if (defs & ArchDefine603) 1173 Builder.defineMacro("_ARCH_603"); 1174 if (defs & ArchDefine604) 1175 Builder.defineMacro("_ARCH_604"); 1176 if (defs & ArchDefinePwr4) 1177 Builder.defineMacro("_ARCH_PWR4"); 1178 if (defs & ArchDefinePwr5) 1179 Builder.defineMacro("_ARCH_PWR5"); 1180 if (defs & ArchDefinePwr5x) 1181 Builder.defineMacro("_ARCH_PWR5X"); 1182 if (defs & ArchDefinePwr6) 1183 Builder.defineMacro("_ARCH_PWR6"); 1184 if (defs & ArchDefinePwr6x) 1185 Builder.defineMacro("_ARCH_PWR6X"); 1186 if (defs & ArchDefinePwr7) 1187 Builder.defineMacro("_ARCH_PWR7"); 1188 if (defs & ArchDefinePwr8) 1189 Builder.defineMacro("_ARCH_PWR8"); 1190 if (defs & ArchDefineA2) 1191 Builder.defineMacro("_ARCH_A2"); 1192 if (defs & ArchDefineA2q) { 1193 Builder.defineMacro("_ARCH_A2Q"); 1194 Builder.defineMacro("_ARCH_QP"); 1195 } 1196 1197 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1198 Builder.defineMacro("__bg__"); 1199 Builder.defineMacro("__THW_BLUEGENE__"); 1200 Builder.defineMacro("__bgq__"); 1201 Builder.defineMacro("__TOS_BGQ__"); 1202 } 1203 1204 if (HasVSX) 1205 Builder.defineMacro("__VSX__"); 1206 if (HasP8Vector) 1207 Builder.defineMacro("__POWER8_VECTOR__"); 1208 if (HasP8Crypto) 1209 Builder.defineMacro("__CRYPTO__"); 1210 if (HasHTM) 1211 Builder.defineMacro("__HTM__"); 1212 if (getTriple().getArch() == llvm::Triple::ppc64le || 1213 (defs & ArchDefinePwr8) || (CPU == "pwr8")) { 1214 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1215 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1216 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1217 if (PointerWidth == 64) 1218 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1219 } 1220 1221 // FIXME: The following are not yet generated here by Clang, but are 1222 // generated by GCC: 1223 // 1224 // _SOFT_FLOAT_ 1225 // __RECIP_PRECISION__ 1226 // __APPLE_ALTIVEC__ 1227 // __RECIP__ 1228 // __RECIPF__ 1229 // __RSQRTE__ 1230 // __RSQRTEF__ 1231 // _SOFT_DOUBLE_ 1232 // __NO_LWSYNC__ 1233 // __HAVE_BSWAP__ 1234 // __LONGDOUBLE128 1235 // __CMODEL_MEDIUM__ 1236 // __CMODEL_LARGE__ 1237 // _CALL_SYSV 1238 // _CALL_DARWIN 1239 // __NO_FPRS__ 1240 } 1241 1242 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1243 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1244 .Case("7400", true) 1245 .Case("g4", true) 1246 .Case("7450", true) 1247 .Case("g4+", true) 1248 .Case("970", true) 1249 .Case("g5", true) 1250 .Case("pwr6", true) 1251 .Case("pwr7", true) 1252 .Case("pwr8", true) 1253 .Case("ppc64", true) 1254 .Case("ppc64le", true) 1255 .Default(false); 1256 1257 Features["qpx"] = (CPU == "a2q"); 1258 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1259 .Case("ppc64le", true) 1260 .Case("pwr8", true) 1261 .Default(false); 1262 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1263 .Case("ppc64le", true) 1264 .Case("pwr8", true) 1265 .Default(false); 1266 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1267 .Case("ppc64le", true) 1268 .Case("pwr8", true) 1269 .Case("pwr7", true) 1270 .Default(false); 1271 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1272 .Case("ppc64le", true) 1273 .Case("pwr8", true) 1274 .Case("pwr7", true) 1275 .Default(false); 1276 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1277 .Case("ppc64le", true) 1278 .Case("pwr8", true) 1279 .Default(false); 1280 } 1281 1282 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1283 return llvm::StringSwitch<bool>(Feature) 1284 .Case("powerpc", true) 1285 .Case("vsx", HasVSX) 1286 .Case("power8-vector", HasP8Vector) 1287 .Case("crypto", HasP8Crypto) 1288 .Case("direct-move", HasDirectMove) 1289 .Case("qpx", HasQPX) 1290 .Case("htm", HasHTM) 1291 .Case("bpermd", HasBPERMD) 1292 .Case("extdiv", HasExtDiv) 1293 .Default(false); 1294 } 1295 1296 const char * const PPCTargetInfo::GCCRegNames[] = { 1297 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1298 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1299 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1300 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1301 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1302 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1303 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1304 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1305 "mq", "lr", "ctr", "ap", 1306 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1307 "xer", 1308 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1309 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1310 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1311 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1312 "vrsave", "vscr", 1313 "spe_acc", "spefscr", 1314 "sfp" 1315 }; 1316 1317 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1318 unsigned &NumNames) const { 1319 Names = GCCRegNames; 1320 NumNames = llvm::array_lengthof(GCCRegNames); 1321 } 1322 1323 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1324 // While some of these aliases do map to different registers 1325 // they still share the same register name. 1326 { { "0" }, "r0" }, 1327 { { "1"}, "r1" }, 1328 { { "2" }, "r2" }, 1329 { { "3" }, "r3" }, 1330 { { "4" }, "r4" }, 1331 { { "5" }, "r5" }, 1332 { { "6" }, "r6" }, 1333 { { "7" }, "r7" }, 1334 { { "8" }, "r8" }, 1335 { { "9" }, "r9" }, 1336 { { "10" }, "r10" }, 1337 { { "11" }, "r11" }, 1338 { { "12" }, "r12" }, 1339 { { "13" }, "r13" }, 1340 { { "14" }, "r14" }, 1341 { { "15" }, "r15" }, 1342 { { "16" }, "r16" }, 1343 { { "17" }, "r17" }, 1344 { { "18" }, "r18" }, 1345 { { "19" }, "r19" }, 1346 { { "20" }, "r20" }, 1347 { { "21" }, "r21" }, 1348 { { "22" }, "r22" }, 1349 { { "23" }, "r23" }, 1350 { { "24" }, "r24" }, 1351 { { "25" }, "r25" }, 1352 { { "26" }, "r26" }, 1353 { { "27" }, "r27" }, 1354 { { "28" }, "r28" }, 1355 { { "29" }, "r29" }, 1356 { { "30" }, "r30" }, 1357 { { "31" }, "r31" }, 1358 { { "fr0" }, "f0" }, 1359 { { "fr1" }, "f1" }, 1360 { { "fr2" }, "f2" }, 1361 { { "fr3" }, "f3" }, 1362 { { "fr4" }, "f4" }, 1363 { { "fr5" }, "f5" }, 1364 { { "fr6" }, "f6" }, 1365 { { "fr7" }, "f7" }, 1366 { { "fr8" }, "f8" }, 1367 { { "fr9" }, "f9" }, 1368 { { "fr10" }, "f10" }, 1369 { { "fr11" }, "f11" }, 1370 { { "fr12" }, "f12" }, 1371 { { "fr13" }, "f13" }, 1372 { { "fr14" }, "f14" }, 1373 { { "fr15" }, "f15" }, 1374 { { "fr16" }, "f16" }, 1375 { { "fr17" }, "f17" }, 1376 { { "fr18" }, "f18" }, 1377 { { "fr19" }, "f19" }, 1378 { { "fr20" }, "f20" }, 1379 { { "fr21" }, "f21" }, 1380 { { "fr22" }, "f22" }, 1381 { { "fr23" }, "f23" }, 1382 { { "fr24" }, "f24" }, 1383 { { "fr25" }, "f25" }, 1384 { { "fr26" }, "f26" }, 1385 { { "fr27" }, "f27" }, 1386 { { "fr28" }, "f28" }, 1387 { { "fr29" }, "f29" }, 1388 { { "fr30" }, "f30" }, 1389 { { "fr31" }, "f31" }, 1390 { { "cc" }, "cr0" }, 1391 }; 1392 1393 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1394 unsigned &NumAliases) const { 1395 Aliases = GCCRegAliases; 1396 NumAliases = llvm::array_lengthof(GCCRegAliases); 1397 } 1398 1399 class PPC32TargetInfo : public PPCTargetInfo { 1400 public: 1401 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1402 DescriptionString = "E-m:e-p:32:32-i64:64-n32"; 1403 1404 switch (getTriple().getOS()) { 1405 case llvm::Triple::Linux: 1406 case llvm::Triple::FreeBSD: 1407 case llvm::Triple::NetBSD: 1408 SizeType = UnsignedInt; 1409 PtrDiffType = SignedInt; 1410 IntPtrType = SignedInt; 1411 break; 1412 default: 1413 break; 1414 } 1415 1416 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1417 LongDoubleWidth = LongDoubleAlign = 64; 1418 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1419 } 1420 1421 // PPC32 supports atomics up to 4 bytes. 1422 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1423 } 1424 1425 BuiltinVaListKind getBuiltinVaListKind() const override { 1426 // This is the ELF definition, and is overridden by the Darwin sub-target 1427 return TargetInfo::PowerABIBuiltinVaList; 1428 } 1429 }; 1430 1431 // Note: ABI differences may eventually require us to have a separate 1432 // TargetInfo for little endian. 1433 class PPC64TargetInfo : public PPCTargetInfo { 1434 public: 1435 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1436 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1437 IntMaxType = SignedLong; 1438 Int64Type = SignedLong; 1439 1440 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1441 DescriptionString = "e-m:e-i64:64-n32:64"; 1442 ABI = "elfv2"; 1443 } else { 1444 DescriptionString = "E-m:e-i64:64-n32:64"; 1445 ABI = "elfv1"; 1446 } 1447 1448 switch (getTriple().getOS()) { 1449 case llvm::Triple::FreeBSD: 1450 LongDoubleWidth = LongDoubleAlign = 64; 1451 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1452 break; 1453 case llvm::Triple::NetBSD: 1454 IntMaxType = SignedLongLong; 1455 Int64Type = SignedLongLong; 1456 break; 1457 default: 1458 break; 1459 } 1460 1461 // PPC64 supports atomics up to 8 bytes. 1462 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1463 } 1464 BuiltinVaListKind getBuiltinVaListKind() const override { 1465 return TargetInfo::CharPtrBuiltinVaList; 1466 } 1467 // PPC64 Linux-specifc ABI options. 1468 bool setABI(const std::string &Name) override { 1469 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1470 ABI = Name; 1471 return true; 1472 } 1473 return false; 1474 } 1475 }; 1476 1477 class DarwinPPC32TargetInfo : 1478 public DarwinTargetInfo<PPC32TargetInfo> { 1479 public: 1480 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1481 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1482 HasAlignMac68kSupport = true; 1483 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1484 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1485 LongLongAlign = 32; 1486 SuitableAlign = 128; 1487 DescriptionString = "E-m:o-p:32:32-f64:32:64-n32"; 1488 } 1489 BuiltinVaListKind getBuiltinVaListKind() const override { 1490 return TargetInfo::CharPtrBuiltinVaList; 1491 } 1492 }; 1493 1494 class DarwinPPC64TargetInfo : 1495 public DarwinTargetInfo<PPC64TargetInfo> { 1496 public: 1497 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1498 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1499 HasAlignMac68kSupport = true; 1500 SuitableAlign = 128; 1501 DescriptionString = "E-m:o-i64:64-n32:64"; 1502 } 1503 }; 1504 1505 static const unsigned NVPTXAddrSpaceMap[] = { 1506 1, // opencl_global 1507 3, // opencl_local 1508 4, // opencl_constant 1509 // FIXME: generic has to be added to the target 1510 0, // opencl_generic 1511 1, // cuda_device 1512 4, // cuda_constant 1513 3, // cuda_shared 1514 }; 1515 class NVPTXTargetInfo : public TargetInfo { 1516 static const char * const GCCRegNames[]; 1517 static const Builtin::Info BuiltinInfo[]; 1518 1519 // The GPU profiles supported by the NVPTX backend 1520 enum GPUKind { 1521 GK_NONE, 1522 GK_SM20, 1523 GK_SM21, 1524 GK_SM30, 1525 GK_SM35, 1526 GK_SM37, 1527 } GPU; 1528 1529 public: 1530 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1531 BigEndian = false; 1532 TLSSupported = false; 1533 LongWidth = LongAlign = 64; 1534 AddrSpaceMap = &NVPTXAddrSpaceMap; 1535 UseAddrSpaceMapMangling = true; 1536 // Define available target features 1537 // These must be defined in sorted order! 1538 NoAsmVariants = true; 1539 // Set the default GPU to sm20 1540 GPU = GK_SM20; 1541 } 1542 void getTargetDefines(const LangOptions &Opts, 1543 MacroBuilder &Builder) const override { 1544 Builder.defineMacro("__PTX__"); 1545 Builder.defineMacro("__NVPTX__"); 1546 if (Opts.CUDAIsDevice) { 1547 // Set __CUDA_ARCH__ for the GPU specified. 1548 std::string CUDAArchCode; 1549 switch (GPU) { 1550 case GK_SM20: 1551 CUDAArchCode = "200"; 1552 break; 1553 case GK_SM21: 1554 CUDAArchCode = "210"; 1555 break; 1556 case GK_SM30: 1557 CUDAArchCode = "300"; 1558 break; 1559 case GK_SM35: 1560 CUDAArchCode = "350"; 1561 break; 1562 case GK_SM37: 1563 CUDAArchCode = "370"; 1564 break; 1565 default: 1566 llvm_unreachable("Unhandled target CPU"); 1567 } 1568 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1569 } 1570 } 1571 void getTargetBuiltins(const Builtin::Info *&Records, 1572 unsigned &NumRecords) const override { 1573 Records = BuiltinInfo; 1574 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1575 } 1576 bool hasFeature(StringRef Feature) const override { 1577 return Feature == "ptx" || Feature == "nvptx"; 1578 } 1579 1580 void getGCCRegNames(const char * const *&Names, 1581 unsigned &NumNames) const override; 1582 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1583 unsigned &NumAliases) const override { 1584 // No aliases. 1585 Aliases = nullptr; 1586 NumAliases = 0; 1587 } 1588 bool 1589 validateAsmConstraint(const char *&Name, 1590 TargetInfo::ConstraintInfo &Info) const override { 1591 switch (*Name) { 1592 default: return false; 1593 case 'c': 1594 case 'h': 1595 case 'r': 1596 case 'l': 1597 case 'f': 1598 case 'd': 1599 Info.setAllowsRegister(); 1600 return true; 1601 } 1602 } 1603 const char *getClobbers() const override { 1604 // FIXME: Is this really right? 1605 return ""; 1606 } 1607 BuiltinVaListKind getBuiltinVaListKind() const override { 1608 // FIXME: implement 1609 return TargetInfo::CharPtrBuiltinVaList; 1610 } 1611 bool setCPU(const std::string &Name) override { 1612 GPU = llvm::StringSwitch<GPUKind>(Name) 1613 .Case("sm_20", GK_SM20) 1614 .Case("sm_21", GK_SM21) 1615 .Case("sm_30", GK_SM30) 1616 .Case("sm_35", GK_SM35) 1617 .Case("sm_37", GK_SM37) 1618 .Default(GK_NONE); 1619 1620 return GPU != GK_NONE; 1621 } 1622 }; 1623 1624 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1625 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1626 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1627 ALL_LANGUAGES }, 1628 #include "clang/Basic/BuiltinsNVPTX.def" 1629 }; 1630 1631 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1632 "r0" 1633 }; 1634 1635 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1636 unsigned &NumNames) const { 1637 Names = GCCRegNames; 1638 NumNames = llvm::array_lengthof(GCCRegNames); 1639 } 1640 1641 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1642 public: 1643 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1644 PointerWidth = PointerAlign = 32; 1645 SizeType = TargetInfo::UnsignedInt; 1646 PtrDiffType = TargetInfo::SignedInt; 1647 IntPtrType = TargetInfo::SignedInt; 1648 DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1649 } 1650 }; 1651 1652 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1653 public: 1654 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1655 PointerWidth = PointerAlign = 64; 1656 SizeType = TargetInfo::UnsignedLong; 1657 PtrDiffType = TargetInfo::SignedLong; 1658 IntPtrType = TargetInfo::SignedLong; 1659 DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1660 } 1661 }; 1662 1663 static const unsigned R600AddrSpaceMap[] = { 1664 1, // opencl_global 1665 3, // opencl_local 1666 2, // opencl_constant 1667 4, // opencl_generic 1668 1, // cuda_device 1669 2, // cuda_constant 1670 3 // cuda_shared 1671 }; 1672 1673 // If you edit the description strings, make sure you update 1674 // getPointerWidthV(). 1675 1676 static const char *DescriptionStringR600 = 1677 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1678 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1679 1680 static const char *DescriptionStringR600DoubleOps = 1681 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1682 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1683 1684 static const char *DescriptionStringSI = 1685 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1686 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1687 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1688 1689 class R600TargetInfo : public TargetInfo { 1690 static const Builtin::Info BuiltinInfo[]; 1691 static const char * const GCCRegNames[]; 1692 1693 /// \brief The GPU profiles supported by the R600 target. 1694 enum GPUKind { 1695 GK_NONE, 1696 GK_R600, 1697 GK_R600_DOUBLE_OPS, 1698 GK_R700, 1699 GK_R700_DOUBLE_OPS, 1700 GK_EVERGREEN, 1701 GK_EVERGREEN_DOUBLE_OPS, 1702 GK_NORTHERN_ISLANDS, 1703 GK_CAYMAN, 1704 GK_SOUTHERN_ISLANDS, 1705 GK_SEA_ISLANDS 1706 } GPU; 1707 1708 bool hasFP64:1; 1709 bool hasFMAF:1; 1710 bool hasLDEXPF:1; 1711 1712 public: 1713 R600TargetInfo(const llvm::Triple &Triple) 1714 : TargetInfo(Triple) { 1715 1716 if (Triple.getArch() == llvm::Triple::amdgcn) { 1717 DescriptionString = DescriptionStringSI; 1718 GPU = GK_SOUTHERN_ISLANDS; 1719 hasFP64 = true; 1720 hasFMAF = true; 1721 hasLDEXPF = true; 1722 } else { 1723 DescriptionString = DescriptionStringR600; 1724 GPU = GK_R600; 1725 hasFP64 = false; 1726 hasFMAF = false; 1727 hasLDEXPF = false; 1728 } 1729 AddrSpaceMap = &R600AddrSpaceMap; 1730 UseAddrSpaceMapMangling = true; 1731 } 1732 1733 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1734 if (GPU <= GK_CAYMAN) 1735 return 32; 1736 1737 switch(AddrSpace) { 1738 default: 1739 return 64; 1740 case 0: 1741 case 3: 1742 case 5: 1743 return 32; 1744 } 1745 } 1746 1747 const char * getClobbers() const override { 1748 return ""; 1749 } 1750 1751 void getGCCRegNames(const char * const *&Names, 1752 unsigned &NumNames) const override; 1753 1754 void getGCCRegAliases(const GCCRegAlias *&Aliases, 1755 unsigned &NumAliases) const override { 1756 Aliases = nullptr; 1757 NumAliases = 0; 1758 } 1759 1760 bool validateAsmConstraint(const char *&Name, 1761 TargetInfo::ConstraintInfo &info) const override { 1762 return true; 1763 } 1764 1765 void getTargetBuiltins(const Builtin::Info *&Records, 1766 unsigned &NumRecords) const override { 1767 Records = BuiltinInfo; 1768 NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin; 1769 } 1770 1771 void getTargetDefines(const LangOptions &Opts, 1772 MacroBuilder &Builder) const override { 1773 Builder.defineMacro("__R600__"); 1774 if (hasFMAF) 1775 Builder.defineMacro("__HAS_FMAF__"); 1776 if (hasLDEXPF) 1777 Builder.defineMacro("__HAS_LDEXPF__"); 1778 if (hasFP64 && Opts.OpenCL) { 1779 Builder.defineMacro("cl_khr_fp64"); 1780 } 1781 } 1782 1783 BuiltinVaListKind getBuiltinVaListKind() const override { 1784 return TargetInfo::CharPtrBuiltinVaList; 1785 } 1786 1787 bool setCPU(const std::string &Name) override { 1788 GPU = llvm::StringSwitch<GPUKind>(Name) 1789 .Case("r600" , GK_R600) 1790 .Case("rv610", GK_R600) 1791 .Case("rv620", GK_R600) 1792 .Case("rv630", GK_R600) 1793 .Case("rv635", GK_R600) 1794 .Case("rs780", GK_R600) 1795 .Case("rs880", GK_R600) 1796 .Case("rv670", GK_R600_DOUBLE_OPS) 1797 .Case("rv710", GK_R700) 1798 .Case("rv730", GK_R700) 1799 .Case("rv740", GK_R700_DOUBLE_OPS) 1800 .Case("rv770", GK_R700_DOUBLE_OPS) 1801 .Case("palm", GK_EVERGREEN) 1802 .Case("cedar", GK_EVERGREEN) 1803 .Case("sumo", GK_EVERGREEN) 1804 .Case("sumo2", GK_EVERGREEN) 1805 .Case("redwood", GK_EVERGREEN) 1806 .Case("juniper", GK_EVERGREEN) 1807 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1808 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1809 .Case("barts", GK_NORTHERN_ISLANDS) 1810 .Case("turks", GK_NORTHERN_ISLANDS) 1811 .Case("caicos", GK_NORTHERN_ISLANDS) 1812 .Case("cayman", GK_CAYMAN) 1813 .Case("aruba", GK_CAYMAN) 1814 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1815 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1816 .Case("verde", GK_SOUTHERN_ISLANDS) 1817 .Case("oland", GK_SOUTHERN_ISLANDS) 1818 .Case("hainan", GK_SOUTHERN_ISLANDS) 1819 .Case("bonaire", GK_SEA_ISLANDS) 1820 .Case("kabini", GK_SEA_ISLANDS) 1821 .Case("kaveri", GK_SEA_ISLANDS) 1822 .Case("hawaii", GK_SEA_ISLANDS) 1823 .Case("mullins", GK_SEA_ISLANDS) 1824 .Default(GK_NONE); 1825 1826 if (GPU == GK_NONE) { 1827 return false; 1828 } 1829 1830 // Set the correct data layout 1831 switch (GPU) { 1832 case GK_NONE: 1833 case GK_R600: 1834 case GK_R700: 1835 case GK_EVERGREEN: 1836 case GK_NORTHERN_ISLANDS: 1837 DescriptionString = DescriptionStringR600; 1838 hasFP64 = false; 1839 hasFMAF = false; 1840 hasLDEXPF = false; 1841 break; 1842 case GK_R600_DOUBLE_OPS: 1843 case GK_R700_DOUBLE_OPS: 1844 case GK_EVERGREEN_DOUBLE_OPS: 1845 case GK_CAYMAN: 1846 DescriptionString = DescriptionStringR600DoubleOps; 1847 hasFP64 = true; 1848 hasFMAF = true; 1849 hasLDEXPF = false; 1850 break; 1851 case GK_SOUTHERN_ISLANDS: 1852 case GK_SEA_ISLANDS: 1853 DescriptionString = DescriptionStringSI; 1854 hasFP64 = true; 1855 hasFMAF = true; 1856 hasLDEXPF = true; 1857 break; 1858 } 1859 1860 return true; 1861 } 1862 }; 1863 1864 const Builtin::Info R600TargetInfo::BuiltinInfo[] = { 1865 #define BUILTIN(ID, TYPE, ATTRS) \ 1866 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1867 #include "clang/Basic/BuiltinsR600.def" 1868 }; 1869 const char * const R600TargetInfo::GCCRegNames[] = { 1870 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1871 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1872 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1873 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1874 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1875 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1876 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1877 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1878 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1879 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1880 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1881 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1882 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1883 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1884 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1885 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1886 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1887 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1888 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 1889 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 1890 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 1891 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 1892 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 1893 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 1894 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 1895 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 1896 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 1897 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 1898 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 1899 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 1900 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 1901 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 1902 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 1903 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 1904 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 1905 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 1906 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 1907 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 1908 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 1909 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 1910 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 1911 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 1912 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 1913 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 1914 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 1915 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 1916 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 1917 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 1918 "exec", "vcc", "scc", "m0", "flat_scr", "exec_lo", "exec_hi", 1919 "vcc_lo", "vcc_hi", "flat_scr_lo", "flat_scr_hi" 1920 }; 1921 1922 void R600TargetInfo::getGCCRegNames(const char * const *&Names, 1923 unsigned &NumNames) const { 1924 Names = GCCRegNames; 1925 NumNames = llvm::array_lengthof(GCCRegNames); 1926 } 1927 1928 // Namespace for x86 abstract base class 1929 const Builtin::Info BuiltinInfo[] = { 1930 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1931 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1932 ALL_LANGUAGES }, 1933 #include "clang/Basic/BuiltinsX86.def" 1934 }; 1935 1936 static const char* const GCCRegNames[] = { 1937 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1938 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1939 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1940 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1941 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1942 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1943 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1944 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1945 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1946 }; 1947 1948 const TargetInfo::AddlRegName AddlRegNames[] = { 1949 { { "al", "ah", "eax", "rax" }, 0 }, 1950 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1951 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1952 { { "dl", "dh", "edx", "rdx" }, 1 }, 1953 { { "esi", "rsi" }, 4 }, 1954 { { "edi", "rdi" }, 5 }, 1955 { { "esp", "rsp" }, 7 }, 1956 { { "ebp", "rbp" }, 6 }, 1957 }; 1958 1959 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1960 // most of the implementation can be shared. 1961 class X86TargetInfo : public TargetInfo { 1962 enum X86SSEEnum { 1963 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1964 } SSELevel; 1965 enum MMX3DNowEnum { 1966 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1967 } MMX3DNowLevel; 1968 enum XOPEnum { 1969 NoXOP, 1970 SSE4A, 1971 FMA4, 1972 XOP 1973 } XOPLevel; 1974 1975 bool HasAES; 1976 bool HasPCLMUL; 1977 bool HasLZCNT; 1978 bool HasRDRND; 1979 bool HasFSGSBASE; 1980 bool HasBMI; 1981 bool HasBMI2; 1982 bool HasPOPCNT; 1983 bool HasRTM; 1984 bool HasPRFCHW; 1985 bool HasRDSEED; 1986 bool HasADX; 1987 bool HasTBM; 1988 bool HasFMA; 1989 bool HasF16C; 1990 bool HasAVX512CD, HasAVX512ER, HasAVX512PF, HasAVX512DQ, HasAVX512BW, 1991 HasAVX512VL; 1992 bool HasSHA; 1993 bool HasCX16; 1994 1995 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1996 /// 1997 /// Each enumeration represents a particular CPU supported by Clang. These 1998 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1999 enum CPUKind { 2000 CK_Generic, 2001 2002 /// \name i386 2003 /// i386-generation processors. 2004 //@{ 2005 CK_i386, 2006 //@} 2007 2008 /// \name i486 2009 /// i486-generation processors. 2010 //@{ 2011 CK_i486, 2012 CK_WinChipC6, 2013 CK_WinChip2, 2014 CK_C3, 2015 //@} 2016 2017 /// \name i586 2018 /// i586-generation processors, P5 microarchitecture based. 2019 //@{ 2020 CK_i586, 2021 CK_Pentium, 2022 CK_PentiumMMX, 2023 //@} 2024 2025 /// \name i686 2026 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2027 //@{ 2028 CK_i686, 2029 CK_PentiumPro, 2030 CK_Pentium2, 2031 CK_Pentium3, 2032 CK_Pentium3M, 2033 CK_PentiumM, 2034 CK_C3_2, 2035 2036 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2037 /// Clang however has some logic to suport this. 2038 // FIXME: Warn, deprecate, and potentially remove this. 2039 CK_Yonah, 2040 //@} 2041 2042 /// \name Netburst 2043 /// Netburst microarchitecture based processors. 2044 //@{ 2045 CK_Pentium4, 2046 CK_Pentium4M, 2047 CK_Prescott, 2048 CK_Nocona, 2049 //@} 2050 2051 /// \name Core 2052 /// Core microarchitecture based processors. 2053 //@{ 2054 CK_Core2, 2055 2056 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2057 /// codename which GCC no longer accepts as an option to -march, but Clang 2058 /// has some logic for recognizing it. 2059 // FIXME: Warn, deprecate, and potentially remove this. 2060 CK_Penryn, 2061 //@} 2062 2063 /// \name Atom 2064 /// Atom processors 2065 //@{ 2066 CK_Bonnell, 2067 CK_Silvermont, 2068 //@} 2069 2070 /// \name Nehalem 2071 /// Nehalem microarchitecture based processors. 2072 CK_Nehalem, 2073 2074 /// \name Westmere 2075 /// Westmere microarchitecture based processors. 2076 CK_Westmere, 2077 2078 /// \name Sandy Bridge 2079 /// Sandy Bridge microarchitecture based processors. 2080 CK_SandyBridge, 2081 2082 /// \name Ivy Bridge 2083 /// Ivy Bridge microarchitecture based processors. 2084 CK_IvyBridge, 2085 2086 /// \name Haswell 2087 /// Haswell microarchitecture based processors. 2088 CK_Haswell, 2089 2090 /// \name Broadwell 2091 /// Broadwell microarchitecture based processors. 2092 CK_Broadwell, 2093 2094 /// \name Skylake 2095 /// Skylake microarchitecture based processors. 2096 CK_Skylake, 2097 2098 /// \name Knights Landing 2099 /// Knights Landing processor. 2100 CK_KNL, 2101 2102 /// \name K6 2103 /// K6 architecture processors. 2104 //@{ 2105 CK_K6, 2106 CK_K6_2, 2107 CK_K6_3, 2108 //@} 2109 2110 /// \name K7 2111 /// K7 architecture processors. 2112 //@{ 2113 CK_Athlon, 2114 CK_AthlonThunderbird, 2115 CK_Athlon4, 2116 CK_AthlonXP, 2117 CK_AthlonMP, 2118 //@} 2119 2120 /// \name K8 2121 /// K8 architecture processors. 2122 //@{ 2123 CK_Athlon64, 2124 CK_Athlon64SSE3, 2125 CK_AthlonFX, 2126 CK_K8, 2127 CK_K8SSE3, 2128 CK_Opteron, 2129 CK_OpteronSSE3, 2130 CK_AMDFAM10, 2131 //@} 2132 2133 /// \name Bobcat 2134 /// Bobcat architecture processors. 2135 //@{ 2136 CK_BTVER1, 2137 CK_BTVER2, 2138 //@} 2139 2140 /// \name Bulldozer 2141 /// Bulldozer architecture processors. 2142 //@{ 2143 CK_BDVER1, 2144 CK_BDVER2, 2145 CK_BDVER3, 2146 CK_BDVER4, 2147 //@} 2148 2149 /// This specification is deprecated and will be removed in the future. 2150 /// Users should prefer \see CK_K8. 2151 // FIXME: Warn on this when the CPU is set to it. 2152 //@{ 2153 CK_x86_64, 2154 //@} 2155 2156 /// \name Geode 2157 /// Geode processors. 2158 //@{ 2159 CK_Geode 2160 //@} 2161 } CPU; 2162 2163 enum FPMathKind { 2164 FP_Default, 2165 FP_SSE, 2166 FP_387 2167 } FPMath; 2168 2169 public: 2170 X86TargetInfo(const llvm::Triple &Triple) 2171 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 2172 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 2173 HasRDRND(false), HasFSGSBASE(false), HasBMI(false), HasBMI2(false), 2174 HasPOPCNT(false), HasRTM(false), HasPRFCHW(false), HasRDSEED(false), 2175 HasADX(false), HasTBM(false), HasFMA(false), HasF16C(false), 2176 HasAVX512CD(false), HasAVX512ER(false), HasAVX512PF(false), 2177 HasAVX512DQ(false), HasAVX512BW(false), HasAVX512VL(false), 2178 HasSHA(false), HasCX16(false), CPU(CK_Generic), FPMath(FP_Default) { 2179 BigEndian = false; 2180 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2181 } 2182 unsigned getFloatEvalMethod() const override { 2183 // X87 evaluates with 80 bits "long double" precision. 2184 return SSELevel == NoSSE ? 2 : 0; 2185 } 2186 void getTargetBuiltins(const Builtin::Info *&Records, 2187 unsigned &NumRecords) const override { 2188 Records = BuiltinInfo; 2189 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 2190 } 2191 void getGCCRegNames(const char * const *&Names, 2192 unsigned &NumNames) const override { 2193 Names = GCCRegNames; 2194 NumNames = llvm::array_lengthof(GCCRegNames); 2195 } 2196 void getGCCRegAliases(const GCCRegAlias *&Aliases, 2197 unsigned &NumAliases) const override { 2198 Aliases = nullptr; 2199 NumAliases = 0; 2200 } 2201 void getGCCAddlRegNames(const AddlRegName *&Names, 2202 unsigned &NumNames) const override { 2203 Names = AddlRegNames; 2204 NumNames = llvm::array_lengthof(AddlRegNames); 2205 } 2206 bool validateAsmConstraint(const char *&Name, 2207 TargetInfo::ConstraintInfo &info) const override; 2208 2209 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2210 2211 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2212 2213 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2214 2215 std::string convertConstraint(const char *&Constraint) const override; 2216 const char *getClobbers() const override { 2217 return "~{dirflag},~{fpsr},~{flags}"; 2218 } 2219 void getTargetDefines(const LangOptions &Opts, 2220 MacroBuilder &Builder) const override; 2221 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2222 bool Enabled); 2223 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2224 bool Enabled); 2225 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2226 bool Enabled); 2227 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2228 StringRef Name, bool Enabled) const override { 2229 setFeatureEnabledImpl(Features, Name, Enabled); 2230 } 2231 // This exists purely to cut down on the number of virtual calls in 2232 // getDefaultFeatures which calls this repeatedly. 2233 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2234 StringRef Name, bool Enabled); 2235 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override; 2236 bool hasFeature(StringRef Feature) const override; 2237 bool handleTargetFeatures(std::vector<std::string> &Features, 2238 DiagnosticsEngine &Diags) override; 2239 StringRef getABI() const override { 2240 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2241 return "avx"; 2242 else if (getTriple().getArch() == llvm::Triple::x86 && 2243 MMX3DNowLevel == NoMMX3DNow) 2244 return "no-mmx"; 2245 return ""; 2246 } 2247 bool setCPU(const std::string &Name) override { 2248 CPU = llvm::StringSwitch<CPUKind>(Name) 2249 .Case("i386", CK_i386) 2250 .Case("i486", CK_i486) 2251 .Case("winchip-c6", CK_WinChipC6) 2252 .Case("winchip2", CK_WinChip2) 2253 .Case("c3", CK_C3) 2254 .Case("i586", CK_i586) 2255 .Case("pentium", CK_Pentium) 2256 .Case("pentium-mmx", CK_PentiumMMX) 2257 .Case("i686", CK_i686) 2258 .Case("pentiumpro", CK_PentiumPro) 2259 .Case("pentium2", CK_Pentium2) 2260 .Case("pentium3", CK_Pentium3) 2261 .Case("pentium3m", CK_Pentium3M) 2262 .Case("pentium-m", CK_PentiumM) 2263 .Case("c3-2", CK_C3_2) 2264 .Case("yonah", CK_Yonah) 2265 .Case("pentium4", CK_Pentium4) 2266 .Case("pentium4m", CK_Pentium4M) 2267 .Case("prescott", CK_Prescott) 2268 .Case("nocona", CK_Nocona) 2269 .Case("core2", CK_Core2) 2270 .Case("penryn", CK_Penryn) 2271 .Case("bonnell", CK_Bonnell) 2272 .Case("atom", CK_Bonnell) // Legacy name. 2273 .Case("silvermont", CK_Silvermont) 2274 .Case("slm", CK_Silvermont) // Legacy name. 2275 .Case("nehalem", CK_Nehalem) 2276 .Case("corei7", CK_Nehalem) // Legacy name. 2277 .Case("westmere", CK_Westmere) 2278 .Case("sandybridge", CK_SandyBridge) 2279 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2280 .Case("ivybridge", CK_IvyBridge) 2281 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2282 .Case("haswell", CK_Haswell) 2283 .Case("core-avx2", CK_Haswell) // Legacy name. 2284 .Case("broadwell", CK_Broadwell) 2285 .Case("skylake", CK_Skylake) 2286 .Case("skx", CK_Skylake) // Legacy name. 2287 .Case("knl", CK_KNL) 2288 .Case("k6", CK_K6) 2289 .Case("k6-2", CK_K6_2) 2290 .Case("k6-3", CK_K6_3) 2291 .Case("athlon", CK_Athlon) 2292 .Case("athlon-tbird", CK_AthlonThunderbird) 2293 .Case("athlon-4", CK_Athlon4) 2294 .Case("athlon-xp", CK_AthlonXP) 2295 .Case("athlon-mp", CK_AthlonMP) 2296 .Case("athlon64", CK_Athlon64) 2297 .Case("athlon64-sse3", CK_Athlon64SSE3) 2298 .Case("athlon-fx", CK_AthlonFX) 2299 .Case("k8", CK_K8) 2300 .Case("k8-sse3", CK_K8SSE3) 2301 .Case("opteron", CK_Opteron) 2302 .Case("opteron-sse3", CK_OpteronSSE3) 2303 .Case("barcelona", CK_AMDFAM10) 2304 .Case("amdfam10", CK_AMDFAM10) 2305 .Case("btver1", CK_BTVER1) 2306 .Case("btver2", CK_BTVER2) 2307 .Case("bdver1", CK_BDVER1) 2308 .Case("bdver2", CK_BDVER2) 2309 .Case("bdver3", CK_BDVER3) 2310 .Case("bdver4", CK_BDVER4) 2311 .Case("x86-64", CK_x86_64) 2312 .Case("geode", CK_Geode) 2313 .Default(CK_Generic); 2314 2315 // Perform any per-CPU checks necessary to determine if this CPU is 2316 // acceptable. 2317 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2318 // invalid without explaining *why*. 2319 switch (CPU) { 2320 case CK_Generic: 2321 // No processor selected! 2322 return false; 2323 2324 case CK_i386: 2325 case CK_i486: 2326 case CK_WinChipC6: 2327 case CK_WinChip2: 2328 case CK_C3: 2329 case CK_i586: 2330 case CK_Pentium: 2331 case CK_PentiumMMX: 2332 case CK_i686: 2333 case CK_PentiumPro: 2334 case CK_Pentium2: 2335 case CK_Pentium3: 2336 case CK_Pentium3M: 2337 case CK_PentiumM: 2338 case CK_Yonah: 2339 case CK_C3_2: 2340 case CK_Pentium4: 2341 case CK_Pentium4M: 2342 case CK_Prescott: 2343 case CK_K6: 2344 case CK_K6_2: 2345 case CK_K6_3: 2346 case CK_Athlon: 2347 case CK_AthlonThunderbird: 2348 case CK_Athlon4: 2349 case CK_AthlonXP: 2350 case CK_AthlonMP: 2351 case CK_Geode: 2352 // Only accept certain architectures when compiling in 32-bit mode. 2353 if (getTriple().getArch() != llvm::Triple::x86) 2354 return false; 2355 2356 // Fallthrough 2357 case CK_Nocona: 2358 case CK_Core2: 2359 case CK_Penryn: 2360 case CK_Bonnell: 2361 case CK_Silvermont: 2362 case CK_Nehalem: 2363 case CK_Westmere: 2364 case CK_SandyBridge: 2365 case CK_IvyBridge: 2366 case CK_Haswell: 2367 case CK_Broadwell: 2368 case CK_Skylake: 2369 case CK_KNL: 2370 case CK_Athlon64: 2371 case CK_Athlon64SSE3: 2372 case CK_AthlonFX: 2373 case CK_K8: 2374 case CK_K8SSE3: 2375 case CK_Opteron: 2376 case CK_OpteronSSE3: 2377 case CK_AMDFAM10: 2378 case CK_BTVER1: 2379 case CK_BTVER2: 2380 case CK_BDVER1: 2381 case CK_BDVER2: 2382 case CK_BDVER3: 2383 case CK_BDVER4: 2384 case CK_x86_64: 2385 return true; 2386 } 2387 llvm_unreachable("Unhandled CPU kind"); 2388 } 2389 2390 bool setFPMath(StringRef Name) override; 2391 2392 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2393 // We accept all non-ARM calling conventions 2394 return (CC == CC_X86ThisCall || 2395 CC == CC_X86FastCall || 2396 CC == CC_X86StdCall || 2397 CC == CC_X86VectorCall || 2398 CC == CC_C || 2399 CC == CC_X86Pascal || 2400 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2401 } 2402 2403 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2404 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2405 } 2406 2407 bool hasSjLjLowering() const override { 2408 return true; 2409 } 2410 }; 2411 2412 bool X86TargetInfo::setFPMath(StringRef Name) { 2413 if (Name == "387") { 2414 FPMath = FP_387; 2415 return true; 2416 } 2417 if (Name == "sse") { 2418 FPMath = FP_SSE; 2419 return true; 2420 } 2421 return false; 2422 } 2423 2424 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2425 // FIXME: This *really* should not be here. 2426 2427 // X86_64 always has SSE2. 2428 if (getTriple().getArch() == llvm::Triple::x86_64) 2429 setFeatureEnabledImpl(Features, "sse2", true); 2430 2431 switch (CPU) { 2432 case CK_Generic: 2433 case CK_i386: 2434 case CK_i486: 2435 case CK_i586: 2436 case CK_Pentium: 2437 case CK_i686: 2438 case CK_PentiumPro: 2439 break; 2440 case CK_PentiumMMX: 2441 case CK_Pentium2: 2442 case CK_K6: 2443 case CK_WinChipC6: 2444 setFeatureEnabledImpl(Features, "mmx", true); 2445 break; 2446 case CK_Pentium3: 2447 case CK_Pentium3M: 2448 case CK_C3_2: 2449 setFeatureEnabledImpl(Features, "sse", true); 2450 break; 2451 case CK_PentiumM: 2452 case CK_Pentium4: 2453 case CK_Pentium4M: 2454 case CK_x86_64: 2455 setFeatureEnabledImpl(Features, "sse2", true); 2456 break; 2457 case CK_Yonah: 2458 case CK_Prescott: 2459 case CK_Nocona: 2460 setFeatureEnabledImpl(Features, "sse3", true); 2461 setFeatureEnabledImpl(Features, "cx16", true); 2462 break; 2463 case CK_Core2: 2464 case CK_Bonnell: 2465 setFeatureEnabledImpl(Features, "ssse3", true); 2466 setFeatureEnabledImpl(Features, "cx16", true); 2467 break; 2468 case CK_Penryn: 2469 setFeatureEnabledImpl(Features, "sse4.1", true); 2470 setFeatureEnabledImpl(Features, "cx16", true); 2471 break; 2472 case CK_Skylake: 2473 setFeatureEnabledImpl(Features, "avx512f", true); 2474 setFeatureEnabledImpl(Features, "avx512cd", true); 2475 setFeatureEnabledImpl(Features, "avx512dq", true); 2476 setFeatureEnabledImpl(Features, "avx512bw", true); 2477 setFeatureEnabledImpl(Features, "avx512vl", true); 2478 // FALLTHROUGH 2479 case CK_Broadwell: 2480 setFeatureEnabledImpl(Features, "rdseed", true); 2481 setFeatureEnabledImpl(Features, "adx", true); 2482 // FALLTHROUGH 2483 case CK_Haswell: 2484 setFeatureEnabledImpl(Features, "avx2", true); 2485 setFeatureEnabledImpl(Features, "lzcnt", true); 2486 setFeatureEnabledImpl(Features, "bmi", true); 2487 setFeatureEnabledImpl(Features, "bmi2", true); 2488 setFeatureEnabledImpl(Features, "rtm", true); 2489 setFeatureEnabledImpl(Features, "fma", true); 2490 // FALLTHROUGH 2491 case CK_IvyBridge: 2492 setFeatureEnabledImpl(Features, "rdrnd", true); 2493 setFeatureEnabledImpl(Features, "f16c", true); 2494 setFeatureEnabledImpl(Features, "fsgsbase", true); 2495 // FALLTHROUGH 2496 case CK_SandyBridge: 2497 setFeatureEnabledImpl(Features, "avx", true); 2498 // FALLTHROUGH 2499 case CK_Westmere: 2500 case CK_Silvermont: 2501 setFeatureEnabledImpl(Features, "aes", true); 2502 setFeatureEnabledImpl(Features, "pclmul", true); 2503 // FALLTHROUGH 2504 case CK_Nehalem: 2505 setFeatureEnabledImpl(Features, "sse4.2", true); 2506 setFeatureEnabledImpl(Features, "cx16", true); 2507 break; 2508 case CK_KNL: 2509 setFeatureEnabledImpl(Features, "avx512f", true); 2510 setFeatureEnabledImpl(Features, "avx512cd", true); 2511 setFeatureEnabledImpl(Features, "avx512er", true); 2512 setFeatureEnabledImpl(Features, "avx512pf", true); 2513 setFeatureEnabledImpl(Features, "rdseed", true); 2514 setFeatureEnabledImpl(Features, "adx", true); 2515 setFeatureEnabledImpl(Features, "lzcnt", true); 2516 setFeatureEnabledImpl(Features, "bmi", true); 2517 setFeatureEnabledImpl(Features, "bmi2", true); 2518 setFeatureEnabledImpl(Features, "rtm", true); 2519 setFeatureEnabledImpl(Features, "fma", true); 2520 setFeatureEnabledImpl(Features, "rdrnd", true); 2521 setFeatureEnabledImpl(Features, "f16c", true); 2522 setFeatureEnabledImpl(Features, "fsgsbase", true); 2523 setFeatureEnabledImpl(Features, "aes", true); 2524 setFeatureEnabledImpl(Features, "pclmul", true); 2525 setFeatureEnabledImpl(Features, "cx16", true); 2526 break; 2527 case CK_K6_2: 2528 case CK_K6_3: 2529 case CK_WinChip2: 2530 case CK_C3: 2531 setFeatureEnabledImpl(Features, "3dnow", true); 2532 break; 2533 case CK_Athlon: 2534 case CK_AthlonThunderbird: 2535 case CK_Geode: 2536 setFeatureEnabledImpl(Features, "3dnowa", true); 2537 break; 2538 case CK_Athlon4: 2539 case CK_AthlonXP: 2540 case CK_AthlonMP: 2541 setFeatureEnabledImpl(Features, "sse", true); 2542 setFeatureEnabledImpl(Features, "3dnowa", true); 2543 break; 2544 case CK_K8: 2545 case CK_Opteron: 2546 case CK_Athlon64: 2547 case CK_AthlonFX: 2548 setFeatureEnabledImpl(Features, "sse2", true); 2549 setFeatureEnabledImpl(Features, "3dnowa", true); 2550 break; 2551 case CK_AMDFAM10: 2552 setFeatureEnabledImpl(Features, "sse4a", true); 2553 setFeatureEnabledImpl(Features, "lzcnt", true); 2554 setFeatureEnabledImpl(Features, "popcnt", true); 2555 // FALLTHROUGH 2556 case CK_K8SSE3: 2557 case CK_OpteronSSE3: 2558 case CK_Athlon64SSE3: 2559 setFeatureEnabledImpl(Features, "sse3", true); 2560 setFeatureEnabledImpl(Features, "3dnowa", true); 2561 break; 2562 case CK_BTVER2: 2563 setFeatureEnabledImpl(Features, "avx", true); 2564 setFeatureEnabledImpl(Features, "aes", true); 2565 setFeatureEnabledImpl(Features, "pclmul", true); 2566 setFeatureEnabledImpl(Features, "bmi", true); 2567 setFeatureEnabledImpl(Features, "f16c", true); 2568 // FALLTHROUGH 2569 case CK_BTVER1: 2570 setFeatureEnabledImpl(Features, "ssse3", true); 2571 setFeatureEnabledImpl(Features, "sse4a", true); 2572 setFeatureEnabledImpl(Features, "lzcnt", true); 2573 setFeatureEnabledImpl(Features, "popcnt", true); 2574 setFeatureEnabledImpl(Features, "prfchw", true); 2575 setFeatureEnabledImpl(Features, "cx16", true); 2576 break; 2577 case CK_BDVER4: 2578 setFeatureEnabledImpl(Features, "avx2", true); 2579 setFeatureEnabledImpl(Features, "bmi2", true); 2580 // FALLTHROUGH 2581 case CK_BDVER3: 2582 setFeatureEnabledImpl(Features, "fsgsbase", true); 2583 // FALLTHROUGH 2584 case CK_BDVER2: 2585 setFeatureEnabledImpl(Features, "bmi", true); 2586 setFeatureEnabledImpl(Features, "fma", true); 2587 setFeatureEnabledImpl(Features, "f16c", true); 2588 setFeatureEnabledImpl(Features, "tbm", true); 2589 // FALLTHROUGH 2590 case CK_BDVER1: 2591 // xop implies avx, sse4a and fma4. 2592 setFeatureEnabledImpl(Features, "xop", true); 2593 setFeatureEnabledImpl(Features, "lzcnt", true); 2594 setFeatureEnabledImpl(Features, "aes", true); 2595 setFeatureEnabledImpl(Features, "pclmul", true); 2596 setFeatureEnabledImpl(Features, "prfchw", true); 2597 setFeatureEnabledImpl(Features, "cx16", true); 2598 break; 2599 } 2600 } 2601 2602 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2603 X86SSEEnum Level, bool Enabled) { 2604 if (Enabled) { 2605 switch (Level) { 2606 case AVX512F: 2607 Features["avx512f"] = true; 2608 case AVX2: 2609 Features["avx2"] = true; 2610 case AVX: 2611 Features["avx"] = true; 2612 case SSE42: 2613 Features["sse4.2"] = true; 2614 case SSE41: 2615 Features["sse4.1"] = true; 2616 case SSSE3: 2617 Features["ssse3"] = true; 2618 case SSE3: 2619 Features["sse3"] = true; 2620 case SSE2: 2621 Features["sse2"] = true; 2622 case SSE1: 2623 Features["sse"] = true; 2624 case NoSSE: 2625 break; 2626 } 2627 return; 2628 } 2629 2630 switch (Level) { 2631 case NoSSE: 2632 case SSE1: 2633 Features["sse"] = false; 2634 case SSE2: 2635 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2636 Features["sha"] = false; 2637 case SSE3: 2638 Features["sse3"] = false; 2639 setXOPLevel(Features, NoXOP, false); 2640 case SSSE3: 2641 Features["ssse3"] = false; 2642 case SSE41: 2643 Features["sse4.1"] = false; 2644 case SSE42: 2645 Features["sse4.2"] = false; 2646 case AVX: 2647 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2648 setXOPLevel(Features, FMA4, false); 2649 case AVX2: 2650 Features["avx2"] = false; 2651 case AVX512F: 2652 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2653 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2654 Features["avx512vl"] = false; 2655 } 2656 } 2657 2658 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2659 MMX3DNowEnum Level, bool Enabled) { 2660 if (Enabled) { 2661 switch (Level) { 2662 case AMD3DNowAthlon: 2663 Features["3dnowa"] = true; 2664 case AMD3DNow: 2665 Features["3dnow"] = true; 2666 case MMX: 2667 Features["mmx"] = true; 2668 case NoMMX3DNow: 2669 break; 2670 } 2671 return; 2672 } 2673 2674 switch (Level) { 2675 case NoMMX3DNow: 2676 case MMX: 2677 Features["mmx"] = false; 2678 case AMD3DNow: 2679 Features["3dnow"] = false; 2680 case AMD3DNowAthlon: 2681 Features["3dnowa"] = false; 2682 } 2683 } 2684 2685 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2686 bool Enabled) { 2687 if (Enabled) { 2688 switch (Level) { 2689 case XOP: 2690 Features["xop"] = true; 2691 case FMA4: 2692 Features["fma4"] = true; 2693 setSSELevel(Features, AVX, true); 2694 case SSE4A: 2695 Features["sse4a"] = true; 2696 setSSELevel(Features, SSE3, true); 2697 case NoXOP: 2698 break; 2699 } 2700 return; 2701 } 2702 2703 switch (Level) { 2704 case NoXOP: 2705 case SSE4A: 2706 Features["sse4a"] = false; 2707 case FMA4: 2708 Features["fma4"] = false; 2709 case XOP: 2710 Features["xop"] = false; 2711 } 2712 } 2713 2714 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2715 StringRef Name, bool Enabled) { 2716 Features[Name] = Enabled; 2717 2718 if (Name == "mmx") { 2719 setMMXLevel(Features, MMX, Enabled); 2720 } else if (Name == "sse") { 2721 setSSELevel(Features, SSE1, Enabled); 2722 } else if (Name == "sse2") { 2723 setSSELevel(Features, SSE2, Enabled); 2724 } else if (Name == "sse3") { 2725 setSSELevel(Features, SSE3, Enabled); 2726 } else if (Name == "ssse3") { 2727 setSSELevel(Features, SSSE3, Enabled); 2728 } else if (Name == "sse4.2") { 2729 setSSELevel(Features, SSE42, Enabled); 2730 } else if (Name == "sse4.1") { 2731 setSSELevel(Features, SSE41, Enabled); 2732 } else if (Name == "3dnow") { 2733 setMMXLevel(Features, AMD3DNow, Enabled); 2734 } else if (Name == "3dnowa") { 2735 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2736 } else if (Name == "aes") { 2737 if (Enabled) 2738 setSSELevel(Features, SSE2, Enabled); 2739 } else if (Name == "pclmul") { 2740 if (Enabled) 2741 setSSELevel(Features, SSE2, Enabled); 2742 } else if (Name == "avx") { 2743 setSSELevel(Features, AVX, Enabled); 2744 } else if (Name == "avx2") { 2745 setSSELevel(Features, AVX2, Enabled); 2746 } else if (Name == "avx512f") { 2747 setSSELevel(Features, AVX512F, Enabled); 2748 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2749 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2750 if (Enabled) 2751 setSSELevel(Features, AVX512F, Enabled); 2752 } else if (Name == "fma") { 2753 if (Enabled) 2754 setSSELevel(Features, AVX, Enabled); 2755 } else if (Name == "fma4") { 2756 setXOPLevel(Features, FMA4, Enabled); 2757 } else if (Name == "xop") { 2758 setXOPLevel(Features, XOP, Enabled); 2759 } else if (Name == "sse4a") { 2760 setXOPLevel(Features, SSE4A, Enabled); 2761 } else if (Name == "f16c") { 2762 if (Enabled) 2763 setSSELevel(Features, AVX, Enabled); 2764 } else if (Name == "sha") { 2765 if (Enabled) 2766 setSSELevel(Features, SSE2, Enabled); 2767 } 2768 } 2769 2770 /// handleTargetFeatures - Perform initialization based on the user 2771 /// configured set of features. 2772 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2773 DiagnosticsEngine &Diags) { 2774 // Remember the maximum enabled sselevel. 2775 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2776 // Ignore disabled features. 2777 if (Features[i][0] == '-') 2778 continue; 2779 2780 StringRef Feature = StringRef(Features[i]).substr(1); 2781 2782 if (Feature == "aes") { 2783 HasAES = true; 2784 continue; 2785 } 2786 2787 if (Feature == "pclmul") { 2788 HasPCLMUL = true; 2789 continue; 2790 } 2791 2792 if (Feature == "lzcnt") { 2793 HasLZCNT = true; 2794 continue; 2795 } 2796 2797 if (Feature == "rdrnd") { 2798 HasRDRND = true; 2799 continue; 2800 } 2801 2802 if (Feature == "fsgsbase") { 2803 HasFSGSBASE = true; 2804 continue; 2805 } 2806 2807 if (Feature == "bmi") { 2808 HasBMI = true; 2809 continue; 2810 } 2811 2812 if (Feature == "bmi2") { 2813 HasBMI2 = true; 2814 continue; 2815 } 2816 2817 if (Feature == "popcnt") { 2818 HasPOPCNT = true; 2819 continue; 2820 } 2821 2822 if (Feature == "rtm") { 2823 HasRTM = true; 2824 continue; 2825 } 2826 2827 if (Feature == "prfchw") { 2828 HasPRFCHW = true; 2829 continue; 2830 } 2831 2832 if (Feature == "rdseed") { 2833 HasRDSEED = true; 2834 continue; 2835 } 2836 2837 if (Feature == "adx") { 2838 HasADX = true; 2839 continue; 2840 } 2841 2842 if (Feature == "tbm") { 2843 HasTBM = true; 2844 continue; 2845 } 2846 2847 if (Feature == "fma") { 2848 HasFMA = true; 2849 continue; 2850 } 2851 2852 if (Feature == "f16c") { 2853 HasF16C = true; 2854 continue; 2855 } 2856 2857 if (Feature == "avx512cd") { 2858 HasAVX512CD = true; 2859 continue; 2860 } 2861 2862 if (Feature == "avx512er") { 2863 HasAVX512ER = true; 2864 continue; 2865 } 2866 2867 if (Feature == "avx512pf") { 2868 HasAVX512PF = true; 2869 continue; 2870 } 2871 2872 if (Feature == "avx512dq") { 2873 HasAVX512DQ = true; 2874 continue; 2875 } 2876 2877 if (Feature == "avx512bw") { 2878 HasAVX512BW = true; 2879 continue; 2880 } 2881 2882 if (Feature == "avx512vl") { 2883 HasAVX512VL = true; 2884 continue; 2885 } 2886 2887 if (Feature == "sha") { 2888 HasSHA = true; 2889 continue; 2890 } 2891 2892 if (Feature == "cx16") { 2893 HasCX16 = true; 2894 continue; 2895 } 2896 2897 assert(Features[i][0] == '+' && "Invalid target feature!"); 2898 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2899 .Case("avx512f", AVX512F) 2900 .Case("avx2", AVX2) 2901 .Case("avx", AVX) 2902 .Case("sse4.2", SSE42) 2903 .Case("sse4.1", SSE41) 2904 .Case("ssse3", SSSE3) 2905 .Case("sse3", SSE3) 2906 .Case("sse2", SSE2) 2907 .Case("sse", SSE1) 2908 .Default(NoSSE); 2909 SSELevel = std::max(SSELevel, Level); 2910 2911 MMX3DNowEnum ThreeDNowLevel = 2912 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2913 .Case("3dnowa", AMD3DNowAthlon) 2914 .Case("3dnow", AMD3DNow) 2915 .Case("mmx", MMX) 2916 .Default(NoMMX3DNow); 2917 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2918 2919 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2920 .Case("xop", XOP) 2921 .Case("fma4", FMA4) 2922 .Case("sse4a", SSE4A) 2923 .Default(NoXOP); 2924 XOPLevel = std::max(XOPLevel, XLevel); 2925 } 2926 2927 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2928 // Can't do this earlier because we need to be able to explicitly enable 2929 // popcnt and still disable sse4.2. 2930 if (!HasPOPCNT && SSELevel >= SSE42 && 2931 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2932 HasPOPCNT = true; 2933 Features.push_back("+popcnt"); 2934 } 2935 2936 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2937 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2938 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2939 HasPRFCHW = true; 2940 Features.push_back("+prfchw"); 2941 } 2942 2943 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2944 // matches the selected sse level. 2945 if (FPMath == FP_SSE && SSELevel < SSE1) { 2946 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2947 return false; 2948 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2949 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2950 return false; 2951 } 2952 2953 // Don't tell the backend if we're turning off mmx; it will end up disabling 2954 // SSE, which we don't want. 2955 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2956 // then enable MMX. 2957 std::vector<std::string>::iterator it; 2958 it = std::find(Features.begin(), Features.end(), "-mmx"); 2959 if (it != Features.end()) 2960 Features.erase(it); 2961 else if (SSELevel > NoSSE) 2962 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2963 return true; 2964 } 2965 2966 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2967 /// definitions for this particular subtarget. 2968 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2969 MacroBuilder &Builder) const { 2970 // Target identification. 2971 if (getTriple().getArch() == llvm::Triple::x86_64) { 2972 Builder.defineMacro("__amd64__"); 2973 Builder.defineMacro("__amd64"); 2974 Builder.defineMacro("__x86_64"); 2975 Builder.defineMacro("__x86_64__"); 2976 if (getTriple().getArchName() == "x86_64h") { 2977 Builder.defineMacro("__x86_64h"); 2978 Builder.defineMacro("__x86_64h__"); 2979 } 2980 } else { 2981 DefineStd(Builder, "i386", Opts); 2982 } 2983 2984 // Subtarget options. 2985 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2986 // truly should be based on -mtune options. 2987 switch (CPU) { 2988 case CK_Generic: 2989 break; 2990 case CK_i386: 2991 // The rest are coming from the i386 define above. 2992 Builder.defineMacro("__tune_i386__"); 2993 break; 2994 case CK_i486: 2995 case CK_WinChipC6: 2996 case CK_WinChip2: 2997 case CK_C3: 2998 defineCPUMacros(Builder, "i486"); 2999 break; 3000 case CK_PentiumMMX: 3001 Builder.defineMacro("__pentium_mmx__"); 3002 Builder.defineMacro("__tune_pentium_mmx__"); 3003 // Fallthrough 3004 case CK_i586: 3005 case CK_Pentium: 3006 defineCPUMacros(Builder, "i586"); 3007 defineCPUMacros(Builder, "pentium"); 3008 break; 3009 case CK_Pentium3: 3010 case CK_Pentium3M: 3011 case CK_PentiumM: 3012 Builder.defineMacro("__tune_pentium3__"); 3013 // Fallthrough 3014 case CK_Pentium2: 3015 case CK_C3_2: 3016 Builder.defineMacro("__tune_pentium2__"); 3017 // Fallthrough 3018 case CK_PentiumPro: 3019 Builder.defineMacro("__tune_i686__"); 3020 Builder.defineMacro("__tune_pentiumpro__"); 3021 // Fallthrough 3022 case CK_i686: 3023 Builder.defineMacro("__i686"); 3024 Builder.defineMacro("__i686__"); 3025 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3026 Builder.defineMacro("__pentiumpro"); 3027 Builder.defineMacro("__pentiumpro__"); 3028 break; 3029 case CK_Pentium4: 3030 case CK_Pentium4M: 3031 defineCPUMacros(Builder, "pentium4"); 3032 break; 3033 case CK_Yonah: 3034 case CK_Prescott: 3035 case CK_Nocona: 3036 defineCPUMacros(Builder, "nocona"); 3037 break; 3038 case CK_Core2: 3039 case CK_Penryn: 3040 defineCPUMacros(Builder, "core2"); 3041 break; 3042 case CK_Bonnell: 3043 defineCPUMacros(Builder, "atom"); 3044 break; 3045 case CK_Silvermont: 3046 defineCPUMacros(Builder, "slm"); 3047 break; 3048 case CK_Nehalem: 3049 case CK_Westmere: 3050 case CK_SandyBridge: 3051 case CK_IvyBridge: 3052 case CK_Haswell: 3053 case CK_Broadwell: 3054 // FIXME: Historically, we defined this legacy name, it would be nice to 3055 // remove it at some point. We've never exposed fine-grained names for 3056 // recent primary x86 CPUs, and we should keep it that way. 3057 defineCPUMacros(Builder, "corei7"); 3058 break; 3059 case CK_Skylake: 3060 // FIXME: Historically, we defined this legacy name, it would be nice to 3061 // remove it at some point. This is the only fine-grained CPU macro in the 3062 // main intel CPU line, and it would be better to not have these and force 3063 // people to use ISA macros. 3064 defineCPUMacros(Builder, "skx"); 3065 break; 3066 case CK_KNL: 3067 defineCPUMacros(Builder, "knl"); 3068 break; 3069 case CK_K6_2: 3070 Builder.defineMacro("__k6_2__"); 3071 Builder.defineMacro("__tune_k6_2__"); 3072 // Fallthrough 3073 case CK_K6_3: 3074 if (CPU != CK_K6_2) { // In case of fallthrough 3075 // FIXME: GCC may be enabling these in cases where some other k6 3076 // architecture is specified but -m3dnow is explicitly provided. The 3077 // exact semantics need to be determined and emulated here. 3078 Builder.defineMacro("__k6_3__"); 3079 Builder.defineMacro("__tune_k6_3__"); 3080 } 3081 // Fallthrough 3082 case CK_K6: 3083 defineCPUMacros(Builder, "k6"); 3084 break; 3085 case CK_Athlon: 3086 case CK_AthlonThunderbird: 3087 case CK_Athlon4: 3088 case CK_AthlonXP: 3089 case CK_AthlonMP: 3090 defineCPUMacros(Builder, "athlon"); 3091 if (SSELevel != NoSSE) { 3092 Builder.defineMacro("__athlon_sse__"); 3093 Builder.defineMacro("__tune_athlon_sse__"); 3094 } 3095 break; 3096 case CK_K8: 3097 case CK_K8SSE3: 3098 case CK_x86_64: 3099 case CK_Opteron: 3100 case CK_OpteronSSE3: 3101 case CK_Athlon64: 3102 case CK_Athlon64SSE3: 3103 case CK_AthlonFX: 3104 defineCPUMacros(Builder, "k8"); 3105 break; 3106 case CK_AMDFAM10: 3107 defineCPUMacros(Builder, "amdfam10"); 3108 break; 3109 case CK_BTVER1: 3110 defineCPUMacros(Builder, "btver1"); 3111 break; 3112 case CK_BTVER2: 3113 defineCPUMacros(Builder, "btver2"); 3114 break; 3115 case CK_BDVER1: 3116 defineCPUMacros(Builder, "bdver1"); 3117 break; 3118 case CK_BDVER2: 3119 defineCPUMacros(Builder, "bdver2"); 3120 break; 3121 case CK_BDVER3: 3122 defineCPUMacros(Builder, "bdver3"); 3123 break; 3124 case CK_BDVER4: 3125 defineCPUMacros(Builder, "bdver4"); 3126 break; 3127 case CK_Geode: 3128 defineCPUMacros(Builder, "geode"); 3129 break; 3130 } 3131 3132 // Target properties. 3133 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3134 3135 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3136 // functions in glibc header files that use FP Stack inline asm which the 3137 // backend can't deal with (PR879). 3138 Builder.defineMacro("__NO_MATH_INLINES"); 3139 3140 if (HasAES) 3141 Builder.defineMacro("__AES__"); 3142 3143 if (HasPCLMUL) 3144 Builder.defineMacro("__PCLMUL__"); 3145 3146 if (HasLZCNT) 3147 Builder.defineMacro("__LZCNT__"); 3148 3149 if (HasRDRND) 3150 Builder.defineMacro("__RDRND__"); 3151 3152 if (HasFSGSBASE) 3153 Builder.defineMacro("__FSGSBASE__"); 3154 3155 if (HasBMI) 3156 Builder.defineMacro("__BMI__"); 3157 3158 if (HasBMI2) 3159 Builder.defineMacro("__BMI2__"); 3160 3161 if (HasPOPCNT) 3162 Builder.defineMacro("__POPCNT__"); 3163 3164 if (HasRTM) 3165 Builder.defineMacro("__RTM__"); 3166 3167 if (HasPRFCHW) 3168 Builder.defineMacro("__PRFCHW__"); 3169 3170 if (HasRDSEED) 3171 Builder.defineMacro("__RDSEED__"); 3172 3173 if (HasADX) 3174 Builder.defineMacro("__ADX__"); 3175 3176 if (HasTBM) 3177 Builder.defineMacro("__TBM__"); 3178 3179 switch (XOPLevel) { 3180 case XOP: 3181 Builder.defineMacro("__XOP__"); 3182 case FMA4: 3183 Builder.defineMacro("__FMA4__"); 3184 case SSE4A: 3185 Builder.defineMacro("__SSE4A__"); 3186 case NoXOP: 3187 break; 3188 } 3189 3190 if (HasFMA) 3191 Builder.defineMacro("__FMA__"); 3192 3193 if (HasF16C) 3194 Builder.defineMacro("__F16C__"); 3195 3196 if (HasAVX512CD) 3197 Builder.defineMacro("__AVX512CD__"); 3198 if (HasAVX512ER) 3199 Builder.defineMacro("__AVX512ER__"); 3200 if (HasAVX512PF) 3201 Builder.defineMacro("__AVX512PF__"); 3202 if (HasAVX512DQ) 3203 Builder.defineMacro("__AVX512DQ__"); 3204 if (HasAVX512BW) 3205 Builder.defineMacro("__AVX512BW__"); 3206 if (HasAVX512VL) 3207 Builder.defineMacro("__AVX512VL__"); 3208 3209 if (HasSHA) 3210 Builder.defineMacro("__SHA__"); 3211 3212 if (HasCX16) 3213 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3214 3215 // Each case falls through to the previous one here. 3216 switch (SSELevel) { 3217 case AVX512F: 3218 Builder.defineMacro("__AVX512F__"); 3219 case AVX2: 3220 Builder.defineMacro("__AVX2__"); 3221 case AVX: 3222 Builder.defineMacro("__AVX__"); 3223 case SSE42: 3224 Builder.defineMacro("__SSE4_2__"); 3225 case SSE41: 3226 Builder.defineMacro("__SSE4_1__"); 3227 case SSSE3: 3228 Builder.defineMacro("__SSSE3__"); 3229 case SSE3: 3230 Builder.defineMacro("__SSE3__"); 3231 case SSE2: 3232 Builder.defineMacro("__SSE2__"); 3233 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3234 case SSE1: 3235 Builder.defineMacro("__SSE__"); 3236 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3237 case NoSSE: 3238 break; 3239 } 3240 3241 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3242 switch (SSELevel) { 3243 case AVX512F: 3244 case AVX2: 3245 case AVX: 3246 case SSE42: 3247 case SSE41: 3248 case SSSE3: 3249 case SSE3: 3250 case SSE2: 3251 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3252 break; 3253 case SSE1: 3254 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3255 break; 3256 default: 3257 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3258 } 3259 } 3260 3261 // Each case falls through to the previous one here. 3262 switch (MMX3DNowLevel) { 3263 case AMD3DNowAthlon: 3264 Builder.defineMacro("__3dNOW_A__"); 3265 case AMD3DNow: 3266 Builder.defineMacro("__3dNOW__"); 3267 case MMX: 3268 Builder.defineMacro("__MMX__"); 3269 case NoMMX3DNow: 3270 break; 3271 } 3272 3273 if (CPU >= CK_i486) { 3274 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3275 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3277 } 3278 if (CPU >= CK_i586) 3279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3280 } 3281 3282 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3283 return llvm::StringSwitch<bool>(Feature) 3284 .Case("aes", HasAES) 3285 .Case("avx", SSELevel >= AVX) 3286 .Case("avx2", SSELevel >= AVX2) 3287 .Case("avx512f", SSELevel >= AVX512F) 3288 .Case("avx512cd", HasAVX512CD) 3289 .Case("avx512er", HasAVX512ER) 3290 .Case("avx512pf", HasAVX512PF) 3291 .Case("avx512dq", HasAVX512DQ) 3292 .Case("avx512bw", HasAVX512BW) 3293 .Case("avx512vl", HasAVX512VL) 3294 .Case("bmi", HasBMI) 3295 .Case("bmi2", HasBMI2) 3296 .Case("cx16", HasCX16) 3297 .Case("f16c", HasF16C) 3298 .Case("fma", HasFMA) 3299 .Case("fma4", XOPLevel >= FMA4) 3300 .Case("fsgsbase", HasFSGSBASE) 3301 .Case("lzcnt", HasLZCNT) 3302 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3303 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3304 .Case("mmx", MMX3DNowLevel >= MMX) 3305 .Case("pclmul", HasPCLMUL) 3306 .Case("popcnt", HasPOPCNT) 3307 .Case("prfchw", HasPRFCHW) 3308 .Case("rdrnd", HasRDRND) 3309 .Case("rdseed", HasRDSEED) 3310 .Case("rtm", HasRTM) 3311 .Case("sha", HasSHA) 3312 .Case("sse", SSELevel >= SSE1) 3313 .Case("sse2", SSELevel >= SSE2) 3314 .Case("sse3", SSELevel >= SSE3) 3315 .Case("ssse3", SSELevel >= SSSE3) 3316 .Case("sse4.1", SSELevel >= SSE41) 3317 .Case("sse4.2", SSELevel >= SSE42) 3318 .Case("sse4a", XOPLevel >= SSE4A) 3319 .Case("tbm", HasTBM) 3320 .Case("x86", true) 3321 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3322 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3323 .Case("xop", XOPLevel >= XOP) 3324 .Default(false); 3325 } 3326 3327 bool 3328 X86TargetInfo::validateAsmConstraint(const char *&Name, 3329 TargetInfo::ConstraintInfo &Info) const { 3330 switch (*Name) { 3331 default: return false; 3332 case 'I': 3333 Info.setRequiresImmediate(0, 31); 3334 return true; 3335 case 'J': 3336 Info.setRequiresImmediate(0, 63); 3337 return true; 3338 case 'K': 3339 Info.setRequiresImmediate(-128, 127); 3340 return true; 3341 case 'L': 3342 // FIXME: properly analyze this constraint: 3343 // must be one of 0xff, 0xffff, or 0xffffffff 3344 return true; 3345 case 'M': 3346 Info.setRequiresImmediate(0, 3); 3347 return true; 3348 case 'N': 3349 Info.setRequiresImmediate(0, 255); 3350 return true; 3351 case 'O': 3352 Info.setRequiresImmediate(0, 127); 3353 return true; 3354 case 'Y': // first letter of a pair: 3355 switch (*(Name+1)) { 3356 default: return false; 3357 case '0': // First SSE register. 3358 case 't': // Any SSE register, when SSE2 is enabled. 3359 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3360 case 'm': // any MMX register, when inter-unit moves enabled. 3361 break; // falls through to setAllowsRegister. 3362 } 3363 case 'f': // any x87 floating point stack register. 3364 // Constraint 'f' cannot be used for output operands. 3365 if (Info.ConstraintStr[0] == '=') 3366 return false; 3367 3368 Info.setAllowsRegister(); 3369 return true; 3370 case 'a': // eax. 3371 case 'b': // ebx. 3372 case 'c': // ecx. 3373 case 'd': // edx. 3374 case 'S': // esi. 3375 case 'D': // edi. 3376 case 'A': // edx:eax. 3377 case 't': // top of floating point stack. 3378 case 'u': // second from top of floating point stack. 3379 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3380 case 'y': // Any MMX register. 3381 case 'x': // Any SSE register. 3382 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3383 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3384 case 'l': // "Index" registers: any general register that can be used as an 3385 // index in a base+index memory access. 3386 Info.setAllowsRegister(); 3387 return true; 3388 case 'C': // SSE floating point constant. 3389 case 'G': // x87 floating point constant. 3390 case 'e': // 32-bit signed integer constant for use with zero-extending 3391 // x86_64 instructions. 3392 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3393 // x86_64 instructions. 3394 return true; 3395 } 3396 } 3397 3398 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3399 unsigned Size) const { 3400 // Strip off constraint modifiers. 3401 while (Constraint[0] == '=' || 3402 Constraint[0] == '+' || 3403 Constraint[0] == '&') 3404 Constraint = Constraint.substr(1); 3405 3406 return validateOperandSize(Constraint, Size); 3407 } 3408 3409 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3410 unsigned Size) const { 3411 return validateOperandSize(Constraint, Size); 3412 } 3413 3414 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3415 unsigned Size) const { 3416 switch (Constraint[0]) { 3417 default: break; 3418 case 'y': 3419 return Size <= 64; 3420 case 'f': 3421 case 't': 3422 case 'u': 3423 return Size <= 128; 3424 case 'x': 3425 // 256-bit ymm registers can be used if target supports AVX. 3426 return Size <= (SSELevel >= AVX ? 256U : 128U); 3427 } 3428 3429 return true; 3430 } 3431 3432 std::string 3433 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3434 switch (*Constraint) { 3435 case 'a': return std::string("{ax}"); 3436 case 'b': return std::string("{bx}"); 3437 case 'c': return std::string("{cx}"); 3438 case 'd': return std::string("{dx}"); 3439 case 'S': return std::string("{si}"); 3440 case 'D': return std::string("{di}"); 3441 case 'p': // address 3442 return std::string("im"); 3443 case 't': // top of floating point stack. 3444 return std::string("{st}"); 3445 case 'u': // second from top of floating point stack. 3446 return std::string("{st(1)}"); // second from top of floating point stack. 3447 default: 3448 return std::string(1, *Constraint); 3449 } 3450 } 3451 3452 // X86-32 generic target 3453 class X86_32TargetInfo : public X86TargetInfo { 3454 public: 3455 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3456 DoubleAlign = LongLongAlign = 32; 3457 LongDoubleWidth = 96; 3458 LongDoubleAlign = 32; 3459 SuitableAlign = 128; 3460 DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3461 SizeType = UnsignedInt; 3462 PtrDiffType = SignedInt; 3463 IntPtrType = SignedInt; 3464 RegParmMax = 3; 3465 3466 // Use fpret for all types. 3467 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3468 (1 << TargetInfo::Double) | 3469 (1 << TargetInfo::LongDouble)); 3470 3471 // x86-32 has atomics up to 8 bytes 3472 // FIXME: Check that we actually have cmpxchg8b before setting 3473 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3474 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3475 } 3476 BuiltinVaListKind getBuiltinVaListKind() const override { 3477 return TargetInfo::CharPtrBuiltinVaList; 3478 } 3479 3480 int getEHDataRegisterNumber(unsigned RegNo) const override { 3481 if (RegNo == 0) return 0; 3482 if (RegNo == 1) return 2; 3483 return -1; 3484 } 3485 bool validateOperandSize(StringRef Constraint, 3486 unsigned Size) const override { 3487 switch (Constraint[0]) { 3488 default: break; 3489 case 'R': 3490 case 'q': 3491 case 'Q': 3492 case 'a': 3493 case 'b': 3494 case 'c': 3495 case 'd': 3496 case 'S': 3497 case 'D': 3498 return Size <= 32; 3499 case 'A': 3500 return Size <= 64; 3501 } 3502 3503 return X86TargetInfo::validateOperandSize(Constraint, Size); 3504 } 3505 }; 3506 3507 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3508 public: 3509 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3510 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3511 3512 unsigned getFloatEvalMethod() const override { 3513 unsigned Major, Minor, Micro; 3514 getTriple().getOSVersion(Major, Minor, Micro); 3515 // New NetBSD uses the default rounding mode. 3516 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3517 return X86_32TargetInfo::getFloatEvalMethod(); 3518 // NetBSD before 6.99.26 defaults to "double" rounding. 3519 return 1; 3520 } 3521 }; 3522 3523 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3524 public: 3525 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3526 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3527 SizeType = UnsignedLong; 3528 IntPtrType = SignedLong; 3529 PtrDiffType = SignedLong; 3530 } 3531 }; 3532 3533 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3534 public: 3535 BitrigI386TargetInfo(const llvm::Triple &Triple) 3536 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3537 SizeType = UnsignedLong; 3538 IntPtrType = SignedLong; 3539 PtrDiffType = SignedLong; 3540 } 3541 }; 3542 3543 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3544 public: 3545 DarwinI386TargetInfo(const llvm::Triple &Triple) 3546 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3547 LongDoubleWidth = 128; 3548 LongDoubleAlign = 128; 3549 SuitableAlign = 128; 3550 MaxVectorAlign = 256; 3551 SizeType = UnsignedLong; 3552 IntPtrType = SignedLong; 3553 DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3554 HasAlignMac68kSupport = true; 3555 } 3556 3557 }; 3558 3559 // x86-32 Windows target 3560 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3561 public: 3562 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3563 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3564 WCharType = UnsignedShort; 3565 DoubleAlign = LongLongAlign = 64; 3566 bool IsWinCOFF = 3567 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3568 DescriptionString = IsWinCOFF 3569 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3570 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3571 } 3572 void getTargetDefines(const LangOptions &Opts, 3573 MacroBuilder &Builder) const override { 3574 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3575 } 3576 }; 3577 3578 // x86-32 Windows Visual Studio target 3579 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3580 public: 3581 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3582 : WindowsX86_32TargetInfo(Triple) { 3583 LongDoubleWidth = LongDoubleAlign = 64; 3584 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3585 } 3586 void getTargetDefines(const LangOptions &Opts, 3587 MacroBuilder &Builder) const override { 3588 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3589 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3590 // The value of the following reflects processor type. 3591 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3592 // We lost the original triple, so we use the default. 3593 Builder.defineMacro("_M_IX86", "600"); 3594 } 3595 }; 3596 } // end anonymous namespace 3597 3598 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3599 Builder.defineMacro("__MSVCRT__"); 3600 Builder.defineMacro("__MINGW32__"); 3601 3602 // Mingw defines __declspec(a) to __attribute__((a)). Clang supports 3603 // __declspec natively under -fms-extensions, but we define a no-op __declspec 3604 // macro anyway for pre-processor compatibility. 3605 if (Opts.MicrosoftExt) 3606 Builder.defineMacro("__declspec", "__declspec"); 3607 else 3608 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3609 3610 if (!Opts.MicrosoftExt) { 3611 // Provide macros for all the calling convention keywords. Provide both 3612 // single and double underscore prefixed variants. These are available on 3613 // x64 as well as x86, even though they have no effect. 3614 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3615 for (const char *CC : CCs) { 3616 std::string GCCSpelling = "__attribute__((__"; 3617 GCCSpelling += CC; 3618 GCCSpelling += "__))"; 3619 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3620 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3621 } 3622 } 3623 } 3624 3625 namespace { 3626 // x86-32 MinGW target 3627 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3628 public: 3629 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3630 : WindowsX86_32TargetInfo(Triple) {} 3631 void getTargetDefines(const LangOptions &Opts, 3632 MacroBuilder &Builder) const override { 3633 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3634 DefineStd(Builder, "WIN32", Opts); 3635 DefineStd(Builder, "WINNT", Opts); 3636 Builder.defineMacro("_X86_"); 3637 addMinGWDefines(Opts, Builder); 3638 } 3639 }; 3640 3641 // x86-32 Cygwin target 3642 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3643 public: 3644 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3645 : X86_32TargetInfo(Triple) { 3646 TLSSupported = false; 3647 WCharType = UnsignedShort; 3648 DoubleAlign = LongLongAlign = 64; 3649 DescriptionString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3650 } 3651 void getTargetDefines(const LangOptions &Opts, 3652 MacroBuilder &Builder) const override { 3653 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3654 Builder.defineMacro("_X86_"); 3655 Builder.defineMacro("__CYGWIN__"); 3656 Builder.defineMacro("__CYGWIN32__"); 3657 DefineStd(Builder, "unix", Opts); 3658 if (Opts.CPlusPlus) 3659 Builder.defineMacro("_GNU_SOURCE"); 3660 } 3661 }; 3662 3663 // x86-32 Haiku target 3664 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3665 public: 3666 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3667 SizeType = UnsignedLong; 3668 IntPtrType = SignedLong; 3669 PtrDiffType = SignedLong; 3670 ProcessIDType = SignedLong; 3671 this->UserLabelPrefix = ""; 3672 this->TLSSupported = false; 3673 } 3674 void getTargetDefines(const LangOptions &Opts, 3675 MacroBuilder &Builder) const override { 3676 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3677 Builder.defineMacro("__INTEL__"); 3678 Builder.defineMacro("__HAIKU__"); 3679 } 3680 }; 3681 3682 // RTEMS Target 3683 template<typename Target> 3684 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3685 protected: 3686 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3687 MacroBuilder &Builder) const override { 3688 // RTEMS defines; list based off of gcc output 3689 3690 Builder.defineMacro("__rtems__"); 3691 Builder.defineMacro("__ELF__"); 3692 } 3693 3694 public: 3695 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3696 this->UserLabelPrefix = ""; 3697 3698 switch (Triple.getArch()) { 3699 default: 3700 case llvm::Triple::x86: 3701 // this->MCountName = ".mcount"; 3702 break; 3703 case llvm::Triple::mips: 3704 case llvm::Triple::mipsel: 3705 case llvm::Triple::ppc: 3706 case llvm::Triple::ppc64: 3707 case llvm::Triple::ppc64le: 3708 // this->MCountName = "_mcount"; 3709 break; 3710 case llvm::Triple::arm: 3711 // this->MCountName = "__mcount"; 3712 break; 3713 } 3714 } 3715 }; 3716 3717 // x86-32 RTEMS target 3718 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3719 public: 3720 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3721 SizeType = UnsignedLong; 3722 IntPtrType = SignedLong; 3723 PtrDiffType = SignedLong; 3724 this->UserLabelPrefix = ""; 3725 } 3726 void getTargetDefines(const LangOptions &Opts, 3727 MacroBuilder &Builder) const override { 3728 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3729 Builder.defineMacro("__INTEL__"); 3730 Builder.defineMacro("__rtems__"); 3731 } 3732 }; 3733 3734 // x86-64 generic target 3735 class X86_64TargetInfo : public X86TargetInfo { 3736 public: 3737 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3738 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 3739 bool IsWinCOFF = 3740 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3741 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 3742 LongDoubleWidth = 128; 3743 LongDoubleAlign = 128; 3744 LargeArrayMinWidth = 128; 3745 LargeArrayAlign = 128; 3746 SuitableAlign = 128; 3747 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 3748 PtrDiffType = IsX32 ? SignedInt : SignedLong; 3749 IntPtrType = IsX32 ? SignedInt : SignedLong; 3750 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 3751 Int64Type = IsX32 ? SignedLongLong : SignedLong; 3752 RegParmMax = 6; 3753 3754 // Pointers are 32-bit in x32. 3755 DescriptionString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 3756 : IsWinCOFF 3757 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 3758 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 3759 3760 // Use fpret only for long double. 3761 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3762 3763 // Use fp2ret for _Complex long double. 3764 ComplexLongDoubleUsesFP2Ret = true; 3765 3766 // x86-64 has atomics up to 16 bytes. 3767 MaxAtomicPromoteWidth = 128; 3768 MaxAtomicInlineWidth = 128; 3769 } 3770 BuiltinVaListKind getBuiltinVaListKind() const override { 3771 return TargetInfo::X86_64ABIBuiltinVaList; 3772 } 3773 3774 int getEHDataRegisterNumber(unsigned RegNo) const override { 3775 if (RegNo == 0) return 0; 3776 if (RegNo == 1) return 1; 3777 return -1; 3778 } 3779 3780 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3781 return (CC == CC_C || 3782 CC == CC_X86VectorCall || 3783 CC == CC_IntelOclBicc || 3784 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3785 } 3786 3787 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3788 return CC_C; 3789 } 3790 3791 // for x32 we need it here explicitly 3792 bool hasInt128Type() const override { return true; } 3793 }; 3794 3795 // x86-64 Windows target 3796 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3797 public: 3798 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3799 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3800 WCharType = UnsignedShort; 3801 LongWidth = LongAlign = 32; 3802 DoubleAlign = LongLongAlign = 64; 3803 IntMaxType = SignedLongLong; 3804 Int64Type = SignedLongLong; 3805 SizeType = UnsignedLongLong; 3806 PtrDiffType = SignedLongLong; 3807 IntPtrType = SignedLongLong; 3808 this->UserLabelPrefix = ""; 3809 } 3810 3811 void getTargetDefines(const LangOptions &Opts, 3812 MacroBuilder &Builder) const override { 3813 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3814 Builder.defineMacro("_WIN64"); 3815 } 3816 3817 BuiltinVaListKind getBuiltinVaListKind() const override { 3818 return TargetInfo::CharPtrBuiltinVaList; 3819 } 3820 3821 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3822 switch (CC) { 3823 case CC_X86StdCall: 3824 case CC_X86ThisCall: 3825 case CC_X86FastCall: 3826 return CCCR_Ignore; 3827 case CC_C: 3828 case CC_X86VectorCall: 3829 case CC_IntelOclBicc: 3830 case CC_X86_64SysV: 3831 return CCCR_OK; 3832 default: 3833 return CCCR_Warning; 3834 } 3835 } 3836 }; 3837 3838 // x86-64 Windows Visual Studio target 3839 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 3840 public: 3841 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 3842 : WindowsX86_64TargetInfo(Triple) { 3843 LongDoubleWidth = LongDoubleAlign = 64; 3844 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3845 } 3846 void getTargetDefines(const LangOptions &Opts, 3847 MacroBuilder &Builder) const override { 3848 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3849 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3850 Builder.defineMacro("_M_X64"); 3851 Builder.defineMacro("_M_AMD64"); 3852 } 3853 }; 3854 3855 // x86-64 MinGW target 3856 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3857 public: 3858 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3859 : WindowsX86_64TargetInfo(Triple) {} 3860 void getTargetDefines(const LangOptions &Opts, 3861 MacroBuilder &Builder) const override { 3862 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3863 DefineStd(Builder, "WIN64", Opts); 3864 Builder.defineMacro("__MINGW64__"); 3865 addMinGWDefines(Opts, Builder); 3866 3867 // GCC defines this macro when it is using __gxx_personality_seh0. 3868 if (!Opts.SjLjExceptions) 3869 Builder.defineMacro("__SEH__"); 3870 } 3871 }; 3872 3873 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3874 public: 3875 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3876 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3877 Int64Type = SignedLongLong; 3878 MaxVectorAlign = 256; 3879 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 3880 llvm::Triple T = llvm::Triple(Triple); 3881 if (T.isiOS()) 3882 UseSignedCharForObjCBool = false; 3883 DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 3884 } 3885 }; 3886 3887 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3888 public: 3889 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3890 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3891 IntMaxType = SignedLongLong; 3892 Int64Type = SignedLongLong; 3893 } 3894 }; 3895 3896 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3897 public: 3898 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3899 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3900 IntMaxType = SignedLongLong; 3901 Int64Type = SignedLongLong; 3902 } 3903 }; 3904 3905 class ARMTargetInfo : public TargetInfo { 3906 // Possible FPU choices. 3907 enum FPUMode { 3908 VFP2FPU = (1 << 0), 3909 VFP3FPU = (1 << 1), 3910 VFP4FPU = (1 << 2), 3911 NeonFPU = (1 << 3), 3912 FPARMV8 = (1 << 4) 3913 }; 3914 3915 // Possible HWDiv features. 3916 enum HWDivMode { 3917 HWDivThumb = (1 << 0), 3918 HWDivARM = (1 << 1) 3919 }; 3920 3921 static bool FPUModeIsVFP(FPUMode Mode) { 3922 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3923 } 3924 3925 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3926 static const char * const GCCRegNames[]; 3927 3928 std::string ABI, CPU; 3929 3930 enum { 3931 FP_Default, 3932 FP_VFP, 3933 FP_Neon 3934 } FPMath; 3935 3936 unsigned FPU : 5; 3937 3938 unsigned IsAAPCS : 1; 3939 unsigned IsThumb : 1; 3940 unsigned HWDiv : 2; 3941 3942 // Initialized via features. 3943 unsigned SoftFloat : 1; 3944 unsigned SoftFloatABI : 1; 3945 3946 unsigned CRC : 1; 3947 unsigned Crypto : 1; 3948 3949 // ACLE 6.5.1 Hardware floating point 3950 enum { 3951 HW_FP_HP = (1 << 1), /// half (16-bit) 3952 HW_FP_SP = (1 << 2), /// single (32-bit) 3953 HW_FP_DP = (1 << 3), /// double (64-bit) 3954 }; 3955 uint32_t HW_FP; 3956 3957 static const Builtin::Info BuiltinInfo[]; 3958 3959 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3960 StringRef ArchName = T.getArchName(); 3961 if (T.getArch() == llvm::Triple::arm || 3962 T.getArch() == llvm::Triple::armeb) { 3963 StringRef VersionStr; 3964 if (ArchName.startswith("armv")) 3965 VersionStr = ArchName.substr(4, 1); 3966 else if (ArchName.startswith("armebv")) 3967 VersionStr = ArchName.substr(6, 1); 3968 else 3969 return false; 3970 unsigned Version; 3971 if (VersionStr.getAsInteger(10, Version)) 3972 return false; 3973 return Version >= 6; 3974 } 3975 assert(T.getArch() == llvm::Triple::thumb || 3976 T.getArch() == llvm::Triple::thumbeb); 3977 StringRef VersionStr; 3978 if (ArchName.startswith("thumbv")) 3979 VersionStr = ArchName.substr(6, 1); 3980 else if (ArchName.startswith("thumbebv")) 3981 VersionStr = ArchName.substr(8, 1); 3982 else 3983 return false; 3984 unsigned Version; 3985 if (VersionStr.getAsInteger(10, Version)) 3986 return false; 3987 return Version >= 7; 3988 } 3989 3990 void setABIAAPCS() { 3991 IsAAPCS = true; 3992 3993 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 3994 const llvm::Triple &T = getTriple(); 3995 3996 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 3997 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 3998 T.getOS() == llvm::Triple::Bitrig) 3999 SizeType = UnsignedLong; 4000 else 4001 SizeType = UnsignedInt; 4002 4003 switch (T.getOS()) { 4004 case llvm::Triple::NetBSD: 4005 WCharType = SignedInt; 4006 break; 4007 case llvm::Triple::Win32: 4008 WCharType = UnsignedShort; 4009 break; 4010 case llvm::Triple::Linux: 4011 default: 4012 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4013 WCharType = UnsignedInt; 4014 break; 4015 } 4016 4017 UseBitFieldTypeAlignment = true; 4018 4019 ZeroLengthBitfieldBoundary = 0; 4020 4021 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4022 // so set preferred for small types to 32. 4023 if (T.isOSBinFormatMachO()) { 4024 DescriptionString = 4025 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4026 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4027 } else if (T.isOSWindows()) { 4028 assert(!BigEndian && "Windows on ARM does not support big endian"); 4029 DescriptionString = "e" 4030 "-m:w" 4031 "-p:32:32" 4032 "-i64:64" 4033 "-v128:64:128" 4034 "-a:0:32" 4035 "-n32" 4036 "-S64"; 4037 } else if (T.isOSNaCl()) { 4038 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4039 DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4040 } else { 4041 DescriptionString = 4042 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4043 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4044 } 4045 4046 // FIXME: Enumerated types are variable width in straight AAPCS. 4047 } 4048 4049 void setABIAPCS() { 4050 const llvm::Triple &T = getTriple(); 4051 4052 IsAAPCS = false; 4053 4054 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4055 4056 // size_t is unsigned int on FreeBSD. 4057 if (T.getOS() == llvm::Triple::FreeBSD) 4058 SizeType = UnsignedInt; 4059 else 4060 SizeType = UnsignedLong; 4061 4062 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4063 WCharType = SignedInt; 4064 4065 // Do not respect the alignment of bit-field types when laying out 4066 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4067 UseBitFieldTypeAlignment = false; 4068 4069 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4070 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4071 /// gcc. 4072 ZeroLengthBitfieldBoundary = 32; 4073 4074 if (T.isOSBinFormatMachO()) 4075 DescriptionString = 4076 BigEndian 4077 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4078 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4079 else 4080 DescriptionString = 4081 BigEndian 4082 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4083 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4084 4085 // FIXME: Override "preferred align" for double and long long. 4086 } 4087 4088 public: 4089 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4090 : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default), 4091 IsAAPCS(true), HW_FP(0) { 4092 BigEndian = IsBigEndian; 4093 4094 switch (getTriple().getOS()) { 4095 case llvm::Triple::NetBSD: 4096 PtrDiffType = SignedLong; 4097 break; 4098 default: 4099 PtrDiffType = SignedInt; 4100 break; 4101 } 4102 4103 // {} in inline assembly are neon specifiers, not assembly variant 4104 // specifiers. 4105 NoAsmVariants = true; 4106 4107 // FIXME: Should we just treat this as a feature? 4108 IsThumb = getTriple().getArchName().startswith("thumb"); 4109 4110 // FIXME: This duplicates code from the driver that sets the -target-abi 4111 // option - this code is used if -target-abi isn't passed and should 4112 // be unified in some way. 4113 if (Triple.isOSBinFormatMachO()) { 4114 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4115 // the frontend matches that. 4116 if (Triple.getEnvironment() == llvm::Triple::EABI || 4117 Triple.getOS() == llvm::Triple::UnknownOS || 4118 StringRef(CPU).startswith("cortex-m")) { 4119 setABI("aapcs"); 4120 } else { 4121 setABI("apcs-gnu"); 4122 } 4123 } else if (Triple.isOSWindows()) { 4124 // FIXME: this is invalid for WindowsCE 4125 setABI("aapcs"); 4126 } else { 4127 // Select the default based on the platform. 4128 switch (Triple.getEnvironment()) { 4129 case llvm::Triple::Android: 4130 case llvm::Triple::GNUEABI: 4131 case llvm::Triple::GNUEABIHF: 4132 setABI("aapcs-linux"); 4133 break; 4134 case llvm::Triple::EABIHF: 4135 case llvm::Triple::EABI: 4136 setABI("aapcs"); 4137 break; 4138 case llvm::Triple::GNU: 4139 setABI("apcs-gnu"); 4140 break; 4141 default: 4142 if (Triple.getOS() == llvm::Triple::NetBSD) 4143 setABI("apcs-gnu"); 4144 else 4145 setABI("aapcs"); 4146 break; 4147 } 4148 } 4149 4150 // ARM targets default to using the ARM C++ ABI. 4151 TheCXXABI.set(TargetCXXABI::GenericARM); 4152 4153 // ARM has atomics up to 8 bytes 4154 MaxAtomicPromoteWidth = 64; 4155 if (shouldUseInlineAtomic(getTriple())) 4156 MaxAtomicInlineWidth = 64; 4157 4158 // Do force alignment of members that follow zero length bitfields. If 4159 // the alignment of the zero-length bitfield is greater than the member 4160 // that follows it, `bar', `bar' will be aligned as the type of the 4161 // zero length bitfield. 4162 UseZeroLengthBitfieldAlignment = true; 4163 } 4164 StringRef getABI() const override { return ABI; } 4165 bool setABI(const std::string &Name) override { 4166 ABI = Name; 4167 4168 // The defaults (above) are for AAPCS, check if we need to change them. 4169 // 4170 // FIXME: We need support for -meabi... we could just mangle it into the 4171 // name. 4172 if (Name == "apcs-gnu") { 4173 setABIAPCS(); 4174 return true; 4175 } 4176 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4177 setABIAAPCS(); 4178 return true; 4179 } 4180 return false; 4181 } 4182 4183 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 4184 StringRef ArchName = getTriple().getArchName(); 4185 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 4186 Features["vfp2"] = true; 4187 else if (CPU == "cortex-a8" || CPU == "cortex-a9") { 4188 Features["vfp3"] = true; 4189 Features["neon"] = true; 4190 } 4191 else if (CPU == "cortex-a5") { 4192 Features["vfp4"] = true; 4193 Features["neon"] = true; 4194 } else if (CPU == "swift" || CPU == "cortex-a7" || 4195 CPU == "cortex-a12" || CPU == "cortex-a15" || 4196 CPU == "cortex-a17" || CPU == "krait") { 4197 Features["vfp4"] = true; 4198 Features["neon"] = true; 4199 Features["hwdiv"] = true; 4200 Features["hwdiv-arm"] = true; 4201 } else if (CPU == "cyclone" || CPU == "cortex-a53" || CPU == "cortex-a57" || 4202 CPU == "cortex-a72") { 4203 Features["fp-armv8"] = true; 4204 Features["neon"] = true; 4205 Features["hwdiv"] = true; 4206 Features["hwdiv-arm"] = true; 4207 Features["crc"] = true; 4208 Features["crypto"] = true; 4209 } else if (CPU == "cortex-r5" || CPU == "cortex-r7" || 4210 // Enable the hwdiv extension for all v8a AArch32 cores by 4211 // default. 4212 // FIXME: Use ARMTargetParser. This would require Triple::arm/thumb 4213 // to be recogniseable universally. 4214 ArchName == "armv8.1a" || ArchName == "thumbv8.1a" || //v8.1a 4215 ArchName == "armebv8.1a" || ArchName == "thumbebv8.1a" || 4216 ArchName == "armv8a" || ArchName == "armv8" || //v8a 4217 ArchName == "armebv8a" || ArchName == "armebv8" || 4218 ArchName == "thumbv8a" || ArchName == "thumbv8" || 4219 ArchName == "thumbebv8a" || ArchName == "thumbebv8") { 4220 Features["hwdiv"] = true; 4221 Features["hwdiv-arm"] = true; 4222 } else if (CPU == "cortex-m3" || CPU == "cortex-m4" || CPU == "cortex-m7" || 4223 CPU == "sc300" || CPU == "cortex-r4" || CPU == "cortex-r4f") { 4224 Features["hwdiv"] = true; 4225 } 4226 } 4227 4228 bool handleTargetFeatures(std::vector<std::string> &Features, 4229 DiagnosticsEngine &Diags) override { 4230 FPU = 0; 4231 CRC = 0; 4232 Crypto = 0; 4233 SoftFloat = SoftFloatABI = false; 4234 HWDiv = 0; 4235 4236 for (const auto &Feature : Features) { 4237 if (Feature == "+soft-float") { 4238 SoftFloat = true; 4239 } else if (Feature == "+soft-float-abi") { 4240 SoftFloatABI = true; 4241 } else if (Feature == "+vfp2") { 4242 FPU |= VFP2FPU; 4243 HW_FP = HW_FP_SP | HW_FP_DP; 4244 } else if (Feature == "+vfp3") { 4245 FPU |= VFP3FPU; 4246 HW_FP = HW_FP_SP | HW_FP_DP; 4247 } else if (Feature == "+vfp4") { 4248 FPU |= VFP4FPU; 4249 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4250 } else if (Feature == "+fp-armv8") { 4251 FPU |= FPARMV8; 4252 HW_FP = HW_FP_SP | HW_FP_DP | HW_FP_HP; 4253 } else if (Feature == "+neon") { 4254 FPU |= NeonFPU; 4255 HW_FP = HW_FP_SP | HW_FP_DP; 4256 } else if (Feature == "+hwdiv") { 4257 HWDiv |= HWDivThumb; 4258 } else if (Feature == "+hwdiv-arm") { 4259 HWDiv |= HWDivARM; 4260 } else if (Feature == "+crc") { 4261 CRC = 1; 4262 } else if (Feature == "+crypto") { 4263 Crypto = 1; 4264 } else if (Feature == "+fp-only-sp") { 4265 HW_FP &= ~HW_FP_DP; 4266 } 4267 } 4268 4269 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4270 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4271 return false; 4272 } 4273 4274 if (FPMath == FP_Neon) 4275 Features.push_back("+neonfp"); 4276 else if (FPMath == FP_VFP) 4277 Features.push_back("-neonfp"); 4278 4279 // Remove front-end specific options which the backend handles differently. 4280 auto Feature = 4281 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4282 if (Feature != Features.end()) 4283 Features.erase(Feature); 4284 4285 return true; 4286 } 4287 4288 bool hasFeature(StringRef Feature) const override { 4289 return llvm::StringSwitch<bool>(Feature) 4290 .Case("arm", true) 4291 .Case("softfloat", SoftFloat) 4292 .Case("thumb", IsThumb) 4293 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4294 .Case("hwdiv", HWDiv & HWDivThumb) 4295 .Case("hwdiv-arm", HWDiv & HWDivARM) 4296 .Default(false); 4297 } 4298 // FIXME: Should we actually have some table instead of these switches? 4299 const char *getCPUDefineSuffix(StringRef Name) const { 4300 // FIXME: Use ARMTargetParser 4301 if(Name == "generic") { 4302 auto subarch = getTriple().getSubArch(); 4303 switch (subarch) { 4304 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4305 return "8_1A"; 4306 default: 4307 break; 4308 } 4309 } 4310 4311 return llvm::StringSwitch<const char *>(Name) 4312 .Cases("arm8", "arm810", "4") 4313 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", 4314 "4") 4315 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 4316 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 4317 .Case("ep9312", "4T") 4318 .Cases("arm10tdmi", "arm1020t", "5T") 4319 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 4320 .Case("arm926ej-s", "5TEJ") 4321 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 4322 .Cases("xscale", "iwmmxt", "5TE") 4323 .Case("arm1136j-s", "6J") 4324 .Case("arm1136jf-s", "6") 4325 .Cases("mpcorenovfp", "mpcore", "6K") 4326 .Cases("arm1176jz-s", "arm1176jzf-s", "6K") 4327 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 4328 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 4329 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4330 "7A") 4331 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "7R") 4332 .Case("swift", "7S") 4333 .Case("cyclone", "8A") 4334 .Cases("sc300", "cortex-m3", "7M") 4335 .Cases("cortex-m4", "cortex-m7", "7EM") 4336 .Cases("sc000", "cortex-m0", "cortex-m0plus", "cortex-m1", "6M") 4337 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "8A") 4338 .Default(nullptr); 4339 } 4340 const char *getCPUProfile(StringRef Name) const { 4341 if(Name == "generic") { 4342 auto subarch = getTriple().getSubArch(); 4343 switch (subarch) { 4344 case llvm::Triple::SubArchType::ARMSubArch_v8_1a: 4345 return "A"; 4346 default: 4347 break; 4348 } 4349 } 4350 4351 // FIXME: Use ARMTargetParser 4352 return llvm::StringSwitch<const char *>(Name) 4353 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 4354 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "cortex-a17", "krait", 4355 "A") 4356 .Cases("cortex-a53", "cortex-a57", "cortex-a72", "A") 4357 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "cortex-m0plus", "M") 4358 .Cases("cortex-m1", "cortex-m7", "sc000", "sc300", "M") 4359 .Cases("cortex-r4", "cortex-r4f", "cortex-r5", "cortex-r7", "R") 4360 .Default(""); 4361 } 4362 bool setCPU(const std::string &Name) override { 4363 if (!getCPUDefineSuffix(Name)) 4364 return false; 4365 4366 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4367 StringRef Profile = getCPUProfile(Name); 4368 if (Profile == "M" && MaxAtomicInlineWidth) { 4369 MaxAtomicPromoteWidth = 32; 4370 MaxAtomicInlineWidth = 32; 4371 } 4372 4373 CPU = Name; 4374 return true; 4375 } 4376 bool setFPMath(StringRef Name) override; 4377 bool supportsThumb(StringRef ArchName, StringRef CPUArch, 4378 unsigned CPUArchVer) const { 4379 return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) || 4380 (CPUArch.find('M') != StringRef::npos); 4381 } 4382 bool supportsThumb2(StringRef ArchName, StringRef CPUArch, 4383 unsigned CPUArchVer) const { 4384 // We check both CPUArchVer and ArchName because when only triple is 4385 // specified, the default CPU is arm1136j-s. 4386 return ArchName.endswith("v6t2") || ArchName.endswith("v7") || 4387 ArchName.endswith("v8.1a") || 4388 ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7; 4389 } 4390 void getTargetDefines(const LangOptions &Opts, 4391 MacroBuilder &Builder) const override { 4392 // Target identification. 4393 Builder.defineMacro("__arm"); 4394 Builder.defineMacro("__arm__"); 4395 4396 // Target properties. 4397 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4398 4399 StringRef CPUArch = getCPUDefineSuffix(CPU); 4400 unsigned int CPUArchVer; 4401 if (CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) 4402 llvm_unreachable("Invalid char for architecture version number"); 4403 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 4404 4405 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4406 StringRef CPUProfile = getCPUProfile(CPU); 4407 StringRef ArchName = getTriple().getArchName(); 4408 4409 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4410 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 4411 if (CPUArch[0] >= '8') { 4412 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4413 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4414 } 4415 4416 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4417 // is not defined for the M-profile. 4418 // NOTE that the deffault profile is assumed to be 'A' 4419 if (CPUProfile.empty() || CPUProfile != "M") 4420 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4421 4422 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4423 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4424 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4425 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4426 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4427 else if (supportsThumb(ArchName, CPUArch, CPUArchVer)) 4428 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4429 4430 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4431 // instruction set such as ARM or Thumb. 4432 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4433 4434 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4435 4436 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4437 if (!CPUProfile.empty()) 4438 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4439 4440 // ACLE 6.5.1 Hardware Floating Point 4441 if (HW_FP) 4442 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4443 4444 // ACLE predefines. 4445 Builder.defineMacro("__ARM_ACLE", "200"); 4446 4447 // Subtarget options. 4448 4449 // FIXME: It's more complicated than this and we don't really support 4450 // interworking. 4451 // Windows on ARM does not "support" interworking 4452 if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows()) 4453 Builder.defineMacro("__THUMB_INTERWORK__"); 4454 4455 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4456 // Embedded targets on Darwin follow AAPCS, but not EABI. 4457 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4458 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4459 Builder.defineMacro("__ARM_EABI__"); 4460 Builder.defineMacro("__ARM_PCS", "1"); 4461 4462 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4463 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4464 } 4465 4466 if (SoftFloat) 4467 Builder.defineMacro("__SOFTFP__"); 4468 4469 if (CPU == "xscale") 4470 Builder.defineMacro("__XSCALE__"); 4471 4472 if (IsThumb) { 4473 Builder.defineMacro("__THUMBEL__"); 4474 Builder.defineMacro("__thumb__"); 4475 if (supportsThumb2(ArchName, CPUArch, CPUArchVer)) 4476 Builder.defineMacro("__thumb2__"); 4477 } 4478 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 4479 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4480 4481 // Note, this is always on in gcc, even though it doesn't make sense. 4482 Builder.defineMacro("__APCS_32__"); 4483 4484 if (FPUModeIsVFP((FPUMode) FPU)) { 4485 Builder.defineMacro("__VFP_FP__"); 4486 if (FPU & VFP2FPU) 4487 Builder.defineMacro("__ARM_VFPV2__"); 4488 if (FPU & VFP3FPU) 4489 Builder.defineMacro("__ARM_VFPV3__"); 4490 if (FPU & VFP4FPU) 4491 Builder.defineMacro("__ARM_VFPV4__"); 4492 } 4493 4494 // This only gets set when Neon instructions are actually available, unlike 4495 // the VFP define, hence the soft float and arch check. This is subtly 4496 // different from gcc, we follow the intent which was that it should be set 4497 // when Neon instructions are actually available. 4498 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) { 4499 Builder.defineMacro("__ARM_NEON"); 4500 Builder.defineMacro("__ARM_NEON__"); 4501 } 4502 4503 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4504 Opts.ShortWChar ? "2" : "4"); 4505 4506 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4507 Opts.ShortEnums ? "1" : "4"); 4508 4509 if (CRC) 4510 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4511 4512 if (Crypto) 4513 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4514 4515 if (CPUArchVer >= 6 && CPUArch != "6M") { 4516 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4517 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4518 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4519 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4520 } 4521 4522 bool is5EOrAbove = (CPUArchVer >= 6 || 4523 (CPUArchVer == 5 && 4524 CPUArch.find('E') != StringRef::npos)); 4525 bool is32Bit = (!IsThumb || supportsThumb2(ArchName, CPUArch, CPUArchVer)); 4526 if (is5EOrAbove && is32Bit && (CPUProfile != "M" || CPUArch == "7EM")) 4527 Builder.defineMacro("__ARM_FEATURE_DSP"); 4528 } 4529 void getTargetBuiltins(const Builtin::Info *&Records, 4530 unsigned &NumRecords) const override { 4531 Records = BuiltinInfo; 4532 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4533 } 4534 bool isCLZForZeroUndef() const override { return false; } 4535 BuiltinVaListKind getBuiltinVaListKind() const override { 4536 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4537 } 4538 void getGCCRegNames(const char * const *&Names, 4539 unsigned &NumNames) const override; 4540 void getGCCRegAliases(const GCCRegAlias *&Aliases, 4541 unsigned &NumAliases) const override; 4542 bool validateAsmConstraint(const char *&Name, 4543 TargetInfo::ConstraintInfo &Info) const override { 4544 switch (*Name) { 4545 default: break; 4546 case 'l': // r0-r7 4547 case 'h': // r8-r15 4548 case 'w': // VFP Floating point register single precision 4549 case 'P': // VFP Floating point register double precision 4550 Info.setAllowsRegister(); 4551 return true; 4552 case 'I': 4553 case 'J': 4554 case 'K': 4555 case 'L': 4556 case 'M': 4557 // FIXME 4558 return true; 4559 case 'Q': // A memory address that is a single base register. 4560 Info.setAllowsMemory(); 4561 return true; 4562 case 'U': // a memory reference... 4563 switch (Name[1]) { 4564 case 'q': // ...ARMV4 ldrsb 4565 case 'v': // ...VFP load/store (reg+constant offset) 4566 case 'y': // ...iWMMXt load/store 4567 case 't': // address valid for load/store opaque types wider 4568 // than 128-bits 4569 case 'n': // valid address for Neon doubleword vector load/store 4570 case 'm': // valid address for Neon element and structure load/store 4571 case 's': // valid address for non-offset loads/stores of quad-word 4572 // values in four ARM registers 4573 Info.setAllowsMemory(); 4574 Name++; 4575 return true; 4576 } 4577 } 4578 return false; 4579 } 4580 std::string convertConstraint(const char *&Constraint) const override { 4581 std::string R; 4582 switch (*Constraint) { 4583 case 'U': // Two-character constraint; add "^" hint for later parsing. 4584 R = std::string("^") + std::string(Constraint, 2); 4585 Constraint++; 4586 break; 4587 case 'p': // 'p' should be translated to 'r' by default. 4588 R = std::string("r"); 4589 break; 4590 default: 4591 return std::string(1, *Constraint); 4592 } 4593 return R; 4594 } 4595 bool 4596 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 4597 std::string &SuggestedModifier) const override { 4598 bool isOutput = (Constraint[0] == '='); 4599 bool isInOut = (Constraint[0] == '+'); 4600 4601 // Strip off constraint modifiers. 4602 while (Constraint[0] == '=' || 4603 Constraint[0] == '+' || 4604 Constraint[0] == '&') 4605 Constraint = Constraint.substr(1); 4606 4607 switch (Constraint[0]) { 4608 default: break; 4609 case 'r': { 4610 switch (Modifier) { 4611 default: 4612 return (isInOut || isOutput || Size <= 64); 4613 case 'q': 4614 // A register of size 32 cannot fit a vector type. 4615 return false; 4616 } 4617 } 4618 } 4619 4620 return true; 4621 } 4622 const char *getClobbers() const override { 4623 // FIXME: Is this really right? 4624 return ""; 4625 } 4626 4627 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4628 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4629 } 4630 4631 int getEHDataRegisterNumber(unsigned RegNo) const override { 4632 if (RegNo == 0) return 0; 4633 if (RegNo == 1) return 1; 4634 return -1; 4635 } 4636 }; 4637 4638 bool ARMTargetInfo::setFPMath(StringRef Name) { 4639 if (Name == "neon") { 4640 FPMath = FP_Neon; 4641 return true; 4642 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4643 Name == "vfp4") { 4644 FPMath = FP_VFP; 4645 return true; 4646 } 4647 return false; 4648 } 4649 4650 const char * const ARMTargetInfo::GCCRegNames[] = { 4651 // Integer registers 4652 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4653 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4654 4655 // Float registers 4656 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4657 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4658 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4659 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4660 4661 // Double registers 4662 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4663 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4664 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4665 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4666 4667 // Quad registers 4668 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4669 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4670 }; 4671 4672 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4673 unsigned &NumNames) const { 4674 Names = GCCRegNames; 4675 NumNames = llvm::array_lengthof(GCCRegNames); 4676 } 4677 4678 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4679 { { "a1" }, "r0" }, 4680 { { "a2" }, "r1" }, 4681 { { "a3" }, "r2" }, 4682 { { "a4" }, "r3" }, 4683 { { "v1" }, "r4" }, 4684 { { "v2" }, "r5" }, 4685 { { "v3" }, "r6" }, 4686 { { "v4" }, "r7" }, 4687 { { "v5" }, "r8" }, 4688 { { "v6", "rfp" }, "r9" }, 4689 { { "sl" }, "r10" }, 4690 { { "fp" }, "r11" }, 4691 { { "ip" }, "r12" }, 4692 { { "r13" }, "sp" }, 4693 { { "r14" }, "lr" }, 4694 { { "r15" }, "pc" }, 4695 // The S, D and Q registers overlap, but aren't really aliases; we 4696 // don't want to substitute one of these for a different-sized one. 4697 }; 4698 4699 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4700 unsigned &NumAliases) const { 4701 Aliases = GCCRegAliases; 4702 NumAliases = llvm::array_lengthof(GCCRegAliases); 4703 } 4704 4705 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4706 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4707 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4708 ALL_LANGUAGES }, 4709 #include "clang/Basic/BuiltinsNEON.def" 4710 4711 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4712 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG }, 4713 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4714 ALL_LANGUAGES }, 4715 #include "clang/Basic/BuiltinsARM.def" 4716 }; 4717 4718 class ARMleTargetInfo : public ARMTargetInfo { 4719 public: 4720 ARMleTargetInfo(const llvm::Triple &Triple) 4721 : ARMTargetInfo(Triple, false) { } 4722 void getTargetDefines(const LangOptions &Opts, 4723 MacroBuilder &Builder) const override { 4724 Builder.defineMacro("__ARMEL__"); 4725 ARMTargetInfo::getTargetDefines(Opts, Builder); 4726 } 4727 }; 4728 4729 class ARMbeTargetInfo : public ARMTargetInfo { 4730 public: 4731 ARMbeTargetInfo(const llvm::Triple &Triple) 4732 : ARMTargetInfo(Triple, true) { } 4733 void getTargetDefines(const LangOptions &Opts, 4734 MacroBuilder &Builder) const override { 4735 Builder.defineMacro("__ARMEB__"); 4736 Builder.defineMacro("__ARM_BIG_ENDIAN"); 4737 ARMTargetInfo::getTargetDefines(Opts, Builder); 4738 } 4739 }; 4740 4741 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 4742 const llvm::Triple Triple; 4743 public: 4744 WindowsARMTargetInfo(const llvm::Triple &Triple) 4745 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 4746 TLSSupported = false; 4747 WCharType = UnsignedShort; 4748 SizeType = UnsignedInt; 4749 UserLabelPrefix = ""; 4750 } 4751 void getVisualStudioDefines(const LangOptions &Opts, 4752 MacroBuilder &Builder) const { 4753 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 4754 4755 // FIXME: this is invalid for WindowsCE 4756 Builder.defineMacro("_M_ARM_NT", "1"); 4757 Builder.defineMacro("_M_ARMT", "_M_ARM"); 4758 Builder.defineMacro("_M_THUMB", "_M_ARM"); 4759 4760 assert((Triple.getArch() == llvm::Triple::arm || 4761 Triple.getArch() == llvm::Triple::thumb) && 4762 "invalid architecture for Windows ARM target info"); 4763 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 4764 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 4765 4766 // TODO map the complete set of values 4767 // 31: VFPv3 40: VFPv4 4768 Builder.defineMacro("_M_ARM_FP", "31"); 4769 } 4770 BuiltinVaListKind getBuiltinVaListKind() const override { 4771 return TargetInfo::CharPtrBuiltinVaList; 4772 } 4773 }; 4774 4775 // Windows ARM + Itanium C++ ABI Target 4776 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 4777 public: 4778 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 4779 : WindowsARMTargetInfo(Triple) { 4780 TheCXXABI.set(TargetCXXABI::GenericARM); 4781 } 4782 4783 void getTargetDefines(const LangOptions &Opts, 4784 MacroBuilder &Builder) const override { 4785 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4786 4787 if (Opts.MSVCCompat) 4788 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4789 } 4790 }; 4791 4792 // Windows ARM, MS (C++) ABI 4793 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 4794 public: 4795 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 4796 : WindowsARMTargetInfo(Triple) { 4797 TheCXXABI.set(TargetCXXABI::Microsoft); 4798 } 4799 4800 void getTargetDefines(const LangOptions &Opts, 4801 MacroBuilder &Builder) const override { 4802 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 4803 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 4804 } 4805 }; 4806 4807 class DarwinARMTargetInfo : 4808 public DarwinTargetInfo<ARMleTargetInfo> { 4809 protected: 4810 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4811 MacroBuilder &Builder) const override { 4812 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4813 } 4814 4815 public: 4816 DarwinARMTargetInfo(const llvm::Triple &Triple) 4817 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 4818 HasAlignMac68kSupport = true; 4819 // iOS always has 64-bit atomic instructions. 4820 // FIXME: This should be based off of the target features in 4821 // ARMleTargetInfo. 4822 MaxAtomicInlineWidth = 64; 4823 4824 // Darwin on iOS uses a variant of the ARM C++ ABI. 4825 TheCXXABI.set(TargetCXXABI::iOS); 4826 } 4827 }; 4828 4829 class AArch64TargetInfo : public TargetInfo { 4830 virtual void setDescriptionString() = 0; 4831 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4832 static const char *const GCCRegNames[]; 4833 4834 enum FPUModeEnum { 4835 FPUMode, 4836 NeonMode 4837 }; 4838 4839 unsigned FPU; 4840 unsigned CRC; 4841 unsigned Crypto; 4842 4843 static const Builtin::Info BuiltinInfo[]; 4844 4845 std::string ABI; 4846 4847 public: 4848 AArch64TargetInfo(const llvm::Triple &Triple) 4849 : TargetInfo(Triple), ABI("aapcs") { 4850 4851 if (getTriple().getOS() == llvm::Triple::NetBSD) { 4852 WCharType = SignedInt; 4853 4854 // NetBSD apparently prefers consistency across ARM targets to consistency 4855 // across 64-bit targets. 4856 Int64Type = SignedLongLong; 4857 IntMaxType = SignedLongLong; 4858 } else { 4859 WCharType = UnsignedInt; 4860 Int64Type = SignedLong; 4861 IntMaxType = SignedLong; 4862 } 4863 4864 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4865 MaxVectorAlign = 128; 4866 RegParmMax = 8; 4867 MaxAtomicInlineWidth = 128; 4868 MaxAtomicPromoteWidth = 128; 4869 4870 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 4871 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4872 4873 // {} in inline assembly are neon specifiers, not assembly variant 4874 // specifiers. 4875 NoAsmVariants = true; 4876 4877 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 4878 // contributes to the alignment of the containing aggregate in the same way 4879 // a plain (non bit-field) member of that type would, without exception for 4880 // zero-sized or anonymous bit-fields." 4881 UseBitFieldTypeAlignment = true; 4882 UseZeroLengthBitfieldAlignment = true; 4883 4884 // AArch64 targets default to using the ARM C++ ABI. 4885 TheCXXABI.set(TargetCXXABI::GenericAArch64); 4886 } 4887 4888 StringRef getABI() const override { return ABI; } 4889 bool setABI(const std::string &Name) override { 4890 if (Name != "aapcs" && Name != "darwinpcs") 4891 return false; 4892 4893 ABI = Name; 4894 return true; 4895 } 4896 4897 bool setCPU(const std::string &Name) override { 4898 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4899 .Case("generic", true) 4900 .Cases("cortex-a53", "cortex-a57", "cortex-a72", true) 4901 .Case("cyclone", true) 4902 .Default(false); 4903 return CPUKnown; 4904 } 4905 4906 void getTargetDefines(const LangOptions &Opts, 4907 MacroBuilder &Builder) const override { 4908 // Target identification. 4909 Builder.defineMacro("__aarch64__"); 4910 4911 // Target properties. 4912 Builder.defineMacro("_LP64"); 4913 Builder.defineMacro("__LP64__"); 4914 4915 // ACLE predefines. Many can only have one possible value on v8 AArch64. 4916 Builder.defineMacro("__ARM_ACLE", "200"); 4917 Builder.defineMacro("__ARM_ARCH", "8"); 4918 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 4919 4920 Builder.defineMacro("__ARM_64BIT_STATE"); 4921 Builder.defineMacro("__ARM_PCS_AAPCS64"); 4922 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 4923 4924 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 4925 Builder.defineMacro("__ARM_FEATURE_CLZ"); 4926 Builder.defineMacro("__ARM_FEATURE_FMA"); 4927 Builder.defineMacro("__ARM_FEATURE_DIV"); 4928 Builder.defineMacro("__ARM_FEATURE_IDIV"); // As specified in ACLE 4929 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 4930 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN"); 4931 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING"); 4932 4933 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 4934 4935 // 0xe implies support for half, single and double precision operations. 4936 Builder.defineMacro("__ARM_FP", "0xe"); 4937 4938 // PCS specifies this for SysV variants, which is all we support. Other ABIs 4939 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 4940 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 4941 4942 if (Opts.FastMath || Opts.FiniteMathOnly) 4943 Builder.defineMacro("__ARM_FP_FAST"); 4944 4945 if (Opts.C99 && !Opts.Freestanding) 4946 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 4947 4948 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 4949 4950 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4951 Opts.ShortEnums ? "1" : "4"); 4952 4953 if (FPU == NeonMode) { 4954 Builder.defineMacro("__ARM_NEON"); 4955 // 64-bit NEON supports half, single and double precision operations. 4956 Builder.defineMacro("__ARM_NEON_FP", "0xe"); 4957 } 4958 4959 if (CRC) 4960 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4961 4962 if (Crypto) 4963 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 4964 4965 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 4966 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4967 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4968 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4970 } 4971 4972 void getTargetBuiltins(const Builtin::Info *&Records, 4973 unsigned &NumRecords) const override { 4974 Records = BuiltinInfo; 4975 NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin; 4976 } 4977 4978 bool hasFeature(StringRef Feature) const override { 4979 return Feature == "aarch64" || 4980 Feature == "arm64" || 4981 (Feature == "neon" && FPU == NeonMode); 4982 } 4983 4984 bool handleTargetFeatures(std::vector<std::string> &Features, 4985 DiagnosticsEngine &Diags) override { 4986 FPU = FPUMode; 4987 CRC = 0; 4988 Crypto = 0; 4989 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 4990 if (Features[i] == "+neon") 4991 FPU = NeonMode; 4992 if (Features[i] == "+crc") 4993 CRC = 1; 4994 if (Features[i] == "+crypto") 4995 Crypto = 1; 4996 } 4997 4998 setDescriptionString(); 4999 5000 return true; 5001 } 5002 5003 bool isCLZForZeroUndef() const override { return false; } 5004 5005 BuiltinVaListKind getBuiltinVaListKind() const override { 5006 return TargetInfo::AArch64ABIBuiltinVaList; 5007 } 5008 5009 void getGCCRegNames(const char *const *&Names, 5010 unsigned &NumNames) const override; 5011 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5012 unsigned &NumAliases) const override; 5013 5014 bool validateAsmConstraint(const char *&Name, 5015 TargetInfo::ConstraintInfo &Info) const override { 5016 switch (*Name) { 5017 default: 5018 return false; 5019 case 'w': // Floating point and SIMD registers (V0-V31) 5020 Info.setAllowsRegister(); 5021 return true; 5022 case 'I': // Constant that can be used with an ADD instruction 5023 case 'J': // Constant that can be used with a SUB instruction 5024 case 'K': // Constant that can be used with a 32-bit logical instruction 5025 case 'L': // Constant that can be used with a 64-bit logical instruction 5026 case 'M': // Constant that can be used as a 32-bit MOV immediate 5027 case 'N': // Constant that can be used as a 64-bit MOV immediate 5028 case 'Y': // Floating point constant zero 5029 case 'Z': // Integer constant zero 5030 return true; 5031 case 'Q': // A memory reference with base register and no offset 5032 Info.setAllowsMemory(); 5033 return true; 5034 case 'S': // A symbolic address 5035 Info.setAllowsRegister(); 5036 return true; 5037 case 'U': 5038 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5039 // Utf: A memory address suitable for ldp/stp in TF mode. 5040 // Usa: An absolute symbolic address. 5041 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5042 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5043 case 'z': // Zero register, wzr or xzr 5044 Info.setAllowsRegister(); 5045 return true; 5046 case 'x': // Floating point and SIMD registers (V0-V15) 5047 Info.setAllowsRegister(); 5048 return true; 5049 } 5050 return false; 5051 } 5052 5053 bool 5054 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5055 std::string &SuggestedModifier) const override { 5056 // Strip off constraint modifiers. 5057 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5058 Constraint = Constraint.substr(1); 5059 5060 switch (Constraint[0]) { 5061 default: 5062 return true; 5063 case 'z': 5064 case 'r': { 5065 switch (Modifier) { 5066 case 'x': 5067 case 'w': 5068 // For now assume that the person knows what they're 5069 // doing with the modifier. 5070 return true; 5071 default: 5072 // By default an 'r' constraint will be in the 'x' 5073 // registers. 5074 if (Size == 64) 5075 return true; 5076 5077 SuggestedModifier = "w"; 5078 return false; 5079 } 5080 } 5081 } 5082 } 5083 5084 const char *getClobbers() const override { return ""; } 5085 5086 int getEHDataRegisterNumber(unsigned RegNo) const override { 5087 if (RegNo == 0) 5088 return 0; 5089 if (RegNo == 1) 5090 return 1; 5091 return -1; 5092 } 5093 }; 5094 5095 const char *const AArch64TargetInfo::GCCRegNames[] = { 5096 // 32-bit Integer registers 5097 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5098 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5099 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5100 5101 // 64-bit Integer registers 5102 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5103 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5104 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5105 5106 // 32-bit floating point regsisters 5107 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5108 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5109 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5110 5111 // 64-bit floating point regsisters 5112 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5113 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5114 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5115 5116 // Vector registers 5117 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5118 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5119 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5120 }; 5121 5122 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names, 5123 unsigned &NumNames) const { 5124 Names = GCCRegNames; 5125 NumNames = llvm::array_lengthof(GCCRegNames); 5126 } 5127 5128 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5129 { { "w31" }, "wsp" }, 5130 { { "x29" }, "fp" }, 5131 { { "x30" }, "lr" }, 5132 { { "x31" }, "sp" }, 5133 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5134 // don't want to substitute one of these for a different-sized one. 5135 }; 5136 5137 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5138 unsigned &NumAliases) const { 5139 Aliases = GCCRegAliases; 5140 NumAliases = llvm::array_lengthof(GCCRegAliases); 5141 } 5142 5143 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5144 #define BUILTIN(ID, TYPE, ATTRS) \ 5145 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5146 #include "clang/Basic/BuiltinsNEON.def" 5147 5148 #define BUILTIN(ID, TYPE, ATTRS) \ 5149 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5150 #include "clang/Basic/BuiltinsAArch64.def" 5151 }; 5152 5153 class AArch64leTargetInfo : public AArch64TargetInfo { 5154 void setDescriptionString() override { 5155 if (getTriple().isOSBinFormatMachO()) 5156 DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5157 else 5158 DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5159 } 5160 5161 public: 5162 AArch64leTargetInfo(const llvm::Triple &Triple) 5163 : AArch64TargetInfo(Triple) { 5164 BigEndian = false; 5165 } 5166 void getTargetDefines(const LangOptions &Opts, 5167 MacroBuilder &Builder) const override { 5168 Builder.defineMacro("__AARCH64EL__"); 5169 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5170 } 5171 }; 5172 5173 class AArch64beTargetInfo : public AArch64TargetInfo { 5174 void setDescriptionString() override { 5175 assert(!getTriple().isOSBinFormatMachO()); 5176 DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5177 } 5178 5179 public: 5180 AArch64beTargetInfo(const llvm::Triple &Triple) 5181 : AArch64TargetInfo(Triple) { } 5182 void getTargetDefines(const LangOptions &Opts, 5183 MacroBuilder &Builder) const override { 5184 Builder.defineMacro("__AARCH64EB__"); 5185 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5186 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5187 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5188 } 5189 }; 5190 5191 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5192 protected: 5193 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5194 MacroBuilder &Builder) const override { 5195 Builder.defineMacro("__AARCH64_SIMD__"); 5196 Builder.defineMacro("__ARM64_ARCH_8__"); 5197 Builder.defineMacro("__ARM_NEON__"); 5198 Builder.defineMacro("__LITTLE_ENDIAN__"); 5199 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5200 Builder.defineMacro("__arm64", "1"); 5201 Builder.defineMacro("__arm64__", "1"); 5202 5203 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5204 } 5205 5206 public: 5207 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5208 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5209 Int64Type = SignedLongLong; 5210 WCharType = SignedInt; 5211 UseSignedCharForObjCBool = false; 5212 5213 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5214 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5215 5216 TheCXXABI.set(TargetCXXABI::iOS64); 5217 } 5218 5219 BuiltinVaListKind getBuiltinVaListKind() const override { 5220 return TargetInfo::CharPtrBuiltinVaList; 5221 } 5222 }; 5223 5224 // Hexagon abstract base class 5225 class HexagonTargetInfo : public TargetInfo { 5226 static const Builtin::Info BuiltinInfo[]; 5227 static const char * const GCCRegNames[]; 5228 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5229 std::string CPU; 5230 public: 5231 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5232 BigEndian = false; 5233 DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32"; 5234 5235 // {} in inline assembly are packet specifiers, not assembly variant 5236 // specifiers. 5237 NoAsmVariants = true; 5238 } 5239 5240 void getTargetBuiltins(const Builtin::Info *&Records, 5241 unsigned &NumRecords) const override { 5242 Records = BuiltinInfo; 5243 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 5244 } 5245 5246 bool validateAsmConstraint(const char *&Name, 5247 TargetInfo::ConstraintInfo &Info) const override { 5248 return true; 5249 } 5250 5251 void getTargetDefines(const LangOptions &Opts, 5252 MacroBuilder &Builder) const override; 5253 5254 bool hasFeature(StringRef Feature) const override { 5255 return Feature == "hexagon"; 5256 } 5257 5258 BuiltinVaListKind getBuiltinVaListKind() const override { 5259 return TargetInfo::CharPtrBuiltinVaList; 5260 } 5261 void getGCCRegNames(const char * const *&Names, 5262 unsigned &NumNames) const override; 5263 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5264 unsigned &NumAliases) const override; 5265 const char *getClobbers() const override { 5266 return ""; 5267 } 5268 5269 static const char *getHexagonCPUSuffix(StringRef Name) { 5270 return llvm::StringSwitch<const char*>(Name) 5271 .Case("hexagonv4", "4") 5272 .Case("hexagonv5", "5") 5273 .Default(nullptr); 5274 } 5275 5276 bool setCPU(const std::string &Name) override { 5277 if (!getHexagonCPUSuffix(Name)) 5278 return false; 5279 5280 CPU = Name; 5281 return true; 5282 } 5283 }; 5284 5285 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5286 MacroBuilder &Builder) const { 5287 Builder.defineMacro("qdsp6"); 5288 Builder.defineMacro("__qdsp6", "1"); 5289 Builder.defineMacro("__qdsp6__", "1"); 5290 5291 Builder.defineMacro("hexagon"); 5292 Builder.defineMacro("__hexagon", "1"); 5293 Builder.defineMacro("__hexagon__", "1"); 5294 5295 if(CPU == "hexagonv1") { 5296 Builder.defineMacro("__HEXAGON_V1__"); 5297 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 5298 if(Opts.HexagonQdsp6Compat) { 5299 Builder.defineMacro("__QDSP6_V1__"); 5300 Builder.defineMacro("__QDSP6_ARCH__", "1"); 5301 } 5302 } 5303 else if(CPU == "hexagonv2") { 5304 Builder.defineMacro("__HEXAGON_V2__"); 5305 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 5306 if(Opts.HexagonQdsp6Compat) { 5307 Builder.defineMacro("__QDSP6_V2__"); 5308 Builder.defineMacro("__QDSP6_ARCH__", "2"); 5309 } 5310 } 5311 else if(CPU == "hexagonv3") { 5312 Builder.defineMacro("__HEXAGON_V3__"); 5313 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 5314 if(Opts.HexagonQdsp6Compat) { 5315 Builder.defineMacro("__QDSP6_V3__"); 5316 Builder.defineMacro("__QDSP6_ARCH__", "3"); 5317 } 5318 } 5319 else if(CPU == "hexagonv4") { 5320 Builder.defineMacro("__HEXAGON_V4__"); 5321 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5322 if(Opts.HexagonQdsp6Compat) { 5323 Builder.defineMacro("__QDSP6_V4__"); 5324 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5325 } 5326 } 5327 else if(CPU == "hexagonv5") { 5328 Builder.defineMacro("__HEXAGON_V5__"); 5329 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5330 if(Opts.HexagonQdsp6Compat) { 5331 Builder.defineMacro("__QDSP6_V5__"); 5332 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5333 } 5334 } 5335 } 5336 5337 const char * const HexagonTargetInfo::GCCRegNames[] = { 5338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5340 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5341 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5342 "p0", "p1", "p2", "p3", 5343 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5344 }; 5345 5346 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 5347 unsigned &NumNames) const { 5348 Names = GCCRegNames; 5349 NumNames = llvm::array_lengthof(GCCRegNames); 5350 } 5351 5352 5353 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5354 { { "sp" }, "r29" }, 5355 { { "fp" }, "r30" }, 5356 { { "lr" }, "r31" }, 5357 }; 5358 5359 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5360 unsigned &NumAliases) const { 5361 Aliases = GCCRegAliases; 5362 NumAliases = llvm::array_lengthof(GCCRegAliases); 5363 } 5364 5365 5366 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5367 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5368 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5369 ALL_LANGUAGES }, 5370 #include "clang/Basic/BuiltinsHexagon.def" 5371 }; 5372 5373 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5374 class SparcTargetInfo : public TargetInfo { 5375 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5376 static const char * const GCCRegNames[]; 5377 bool SoftFloat; 5378 public: 5379 SparcTargetInfo(const llvm::Triple &Triple) 5380 : TargetInfo(Triple), SoftFloat(false) {} 5381 5382 bool handleTargetFeatures(std::vector<std::string> &Features, 5383 DiagnosticsEngine &Diags) override { 5384 // The backend doesn't actually handle soft float yet, but in case someone 5385 // is using the support for the front end continue to support it. 5386 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5387 if (Feature != Features.end()) { 5388 SoftFloat = true; 5389 Features.erase(Feature); 5390 } 5391 return true; 5392 } 5393 void getTargetDefines(const LangOptions &Opts, 5394 MacroBuilder &Builder) const override { 5395 DefineStd(Builder, "sparc", Opts); 5396 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5397 5398 if (SoftFloat) 5399 Builder.defineMacro("SOFT_FLOAT", "1"); 5400 } 5401 5402 bool hasFeature(StringRef Feature) const override { 5403 return llvm::StringSwitch<bool>(Feature) 5404 .Case("softfloat", SoftFloat) 5405 .Case("sparc", true) 5406 .Default(false); 5407 } 5408 5409 void getTargetBuiltins(const Builtin::Info *&Records, 5410 unsigned &NumRecords) const override { 5411 // FIXME: Implement! 5412 } 5413 BuiltinVaListKind getBuiltinVaListKind() const override { 5414 return TargetInfo::VoidPtrBuiltinVaList; 5415 } 5416 void getGCCRegNames(const char * const *&Names, 5417 unsigned &NumNames) const override; 5418 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5419 unsigned &NumAliases) const override; 5420 bool validateAsmConstraint(const char *&Name, 5421 TargetInfo::ConstraintInfo &info) const override { 5422 // FIXME: Implement! 5423 switch (*Name) { 5424 case 'I': // Signed 13-bit constant 5425 case 'J': // Zero 5426 case 'K': // 32-bit constant with the low 12 bits clear 5427 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5428 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5429 case 'N': // Same as 'K' but zext (required for SIMode) 5430 case 'O': // The constant 4096 5431 return true; 5432 } 5433 return false; 5434 } 5435 const char *getClobbers() const override { 5436 // FIXME: Implement! 5437 return ""; 5438 } 5439 }; 5440 5441 const char * const SparcTargetInfo::GCCRegNames[] = { 5442 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5443 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5444 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5445 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 5446 }; 5447 5448 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 5449 unsigned &NumNames) const { 5450 Names = GCCRegNames; 5451 NumNames = llvm::array_lengthof(GCCRegNames); 5452 } 5453 5454 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 5455 { { "g0" }, "r0" }, 5456 { { "g1" }, "r1" }, 5457 { { "g2" }, "r2" }, 5458 { { "g3" }, "r3" }, 5459 { { "g4" }, "r4" }, 5460 { { "g5" }, "r5" }, 5461 { { "g6" }, "r6" }, 5462 { { "g7" }, "r7" }, 5463 { { "o0" }, "r8" }, 5464 { { "o1" }, "r9" }, 5465 { { "o2" }, "r10" }, 5466 { { "o3" }, "r11" }, 5467 { { "o4" }, "r12" }, 5468 { { "o5" }, "r13" }, 5469 { { "o6", "sp" }, "r14" }, 5470 { { "o7" }, "r15" }, 5471 { { "l0" }, "r16" }, 5472 { { "l1" }, "r17" }, 5473 { { "l2" }, "r18" }, 5474 { { "l3" }, "r19" }, 5475 { { "l4" }, "r20" }, 5476 { { "l5" }, "r21" }, 5477 { { "l6" }, "r22" }, 5478 { { "l7" }, "r23" }, 5479 { { "i0" }, "r24" }, 5480 { { "i1" }, "r25" }, 5481 { { "i2" }, "r26" }, 5482 { { "i3" }, "r27" }, 5483 { { "i4" }, "r28" }, 5484 { { "i5" }, "r29" }, 5485 { { "i6", "fp" }, "r30" }, 5486 { { "i7" }, "r31" }, 5487 }; 5488 5489 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5490 unsigned &NumAliases) const { 5491 Aliases = GCCRegAliases; 5492 NumAliases = llvm::array_lengthof(GCCRegAliases); 5493 } 5494 5495 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 5496 class SparcV8TargetInfo : public SparcTargetInfo { 5497 public: 5498 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5499 DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5500 } 5501 5502 void getTargetDefines(const LangOptions &Opts, 5503 MacroBuilder &Builder) const override { 5504 SparcTargetInfo::getTargetDefines(Opts, Builder); 5505 Builder.defineMacro("__sparcv8"); 5506 } 5507 }; 5508 5509 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 5510 class SparcV8elTargetInfo : public SparcV8TargetInfo { 5511 public: 5512 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 5513 DescriptionString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 5514 BigEndian = false; 5515 } 5516 }; 5517 5518 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 5519 class SparcV9TargetInfo : public SparcTargetInfo { 5520 public: 5521 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 5522 // FIXME: Support Sparc quad-precision long double? 5523 DescriptionString = "E-m:e-i64:64-n32:64-S128"; 5524 // This is an LP64 platform. 5525 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5526 5527 // OpenBSD uses long long for int64_t and intmax_t. 5528 if (getTriple().getOS() == llvm::Triple::OpenBSD) 5529 IntMaxType = SignedLongLong; 5530 else 5531 IntMaxType = SignedLong; 5532 Int64Type = IntMaxType; 5533 5534 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 5535 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 5536 LongDoubleWidth = 128; 5537 LongDoubleAlign = 128; 5538 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5539 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5540 } 5541 5542 void getTargetDefines(const LangOptions &Opts, 5543 MacroBuilder &Builder) const override { 5544 SparcTargetInfo::getTargetDefines(Opts, Builder); 5545 Builder.defineMacro("__sparcv9"); 5546 Builder.defineMacro("__arch64__"); 5547 // Solaris doesn't need these variants, but the BSDs do. 5548 if (getTriple().getOS() != llvm::Triple::Solaris) { 5549 Builder.defineMacro("__sparc64__"); 5550 Builder.defineMacro("__sparc_v9__"); 5551 Builder.defineMacro("__sparcv9__"); 5552 } 5553 } 5554 5555 bool setCPU(const std::string &Name) override { 5556 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5557 .Case("v9", true) 5558 .Case("ultrasparc", true) 5559 .Case("ultrasparc3", true) 5560 .Case("niagara", true) 5561 .Case("niagara2", true) 5562 .Case("niagara3", true) 5563 .Case("niagara4", true) 5564 .Default(false); 5565 5566 // No need to store the CPU yet. There aren't any CPU-specific 5567 // macros to define. 5568 return CPUKnown; 5569 } 5570 }; 5571 5572 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 5573 public: 5574 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 5575 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 5576 SizeType = UnsignedInt; 5577 PtrDiffType = SignedInt; 5578 } 5579 }; 5580 5581 class SystemZTargetInfo : public TargetInfo { 5582 static const Builtin::Info BuiltinInfo[]; 5583 static const char *const GCCRegNames[]; 5584 std::string CPU; 5585 bool HasTransactionalExecution; 5586 bool HasVector; 5587 5588 public: 5589 SystemZTargetInfo(const llvm::Triple &Triple) 5590 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), HasVector(false) { 5591 IntMaxType = SignedLong; 5592 Int64Type = SignedLong; 5593 TLSSupported = true; 5594 IntWidth = IntAlign = 32; 5595 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 5596 PointerWidth = PointerAlign = 64; 5597 LongDoubleWidth = 128; 5598 LongDoubleAlign = 64; 5599 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5600 DefaultAlignForAttributeAligned = 64; 5601 MinGlobalAlign = 16; 5602 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 5603 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5604 } 5605 void getTargetDefines(const LangOptions &Opts, 5606 MacroBuilder &Builder) const override { 5607 Builder.defineMacro("__s390__"); 5608 Builder.defineMacro("__s390x__"); 5609 Builder.defineMacro("__zarch__"); 5610 Builder.defineMacro("__LONG_DOUBLE_128__"); 5611 if (HasTransactionalExecution) 5612 Builder.defineMacro("__HTM__"); 5613 } 5614 void getTargetBuiltins(const Builtin::Info *&Records, 5615 unsigned &NumRecords) const override { 5616 Records = BuiltinInfo; 5617 NumRecords = clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin; 5618 } 5619 5620 void getGCCRegNames(const char *const *&Names, 5621 unsigned &NumNames) const override; 5622 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5623 unsigned &NumAliases) const override { 5624 // No aliases. 5625 Aliases = nullptr; 5626 NumAliases = 0; 5627 } 5628 bool validateAsmConstraint(const char *&Name, 5629 TargetInfo::ConstraintInfo &info) const override; 5630 const char *getClobbers() const override { 5631 // FIXME: Is this really right? 5632 return ""; 5633 } 5634 BuiltinVaListKind getBuiltinVaListKind() const override { 5635 return TargetInfo::SystemZBuiltinVaList; 5636 } 5637 bool setCPU(const std::string &Name) override { 5638 CPU = Name; 5639 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5640 .Case("z10", true) 5641 .Case("z196", true) 5642 .Case("zEC12", true) 5643 .Case("z13", true) 5644 .Default(false); 5645 5646 return CPUKnown; 5647 } 5648 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5649 if (CPU == "zEC12") 5650 Features["transactional-execution"] = true; 5651 if (CPU == "z13") { 5652 Features["transactional-execution"] = true; 5653 Features["vector"] = true; 5654 } 5655 } 5656 5657 bool handleTargetFeatures(std::vector<std::string> &Features, 5658 DiagnosticsEngine &Diags) override { 5659 HasTransactionalExecution = false; 5660 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 5661 if (Features[i] == "+transactional-execution") 5662 HasTransactionalExecution = true; 5663 if (Features[i] == "+vector") 5664 HasVector = true; 5665 } 5666 // If we use the vector ABI, vector types are 64-bit aligned. 5667 if (HasVector) { 5668 MaxVectorAlign = 64; 5669 DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 5670 "-v128:64-a:8:16-n32:64"; 5671 } 5672 return true; 5673 } 5674 5675 bool hasFeature(StringRef Feature) const override { 5676 return llvm::StringSwitch<bool>(Feature) 5677 .Case("systemz", true) 5678 .Case("htm", HasTransactionalExecution) 5679 .Case("vx", HasVector) 5680 .Default(false); 5681 } 5682 5683 StringRef getABI() const override { 5684 if (HasVector) 5685 return "vector"; 5686 return ""; 5687 } 5688 }; 5689 5690 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 5691 #define BUILTIN(ID, TYPE, ATTRS) \ 5692 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5693 #include "clang/Basic/BuiltinsSystemZ.def" 5694 }; 5695 5696 const char *const SystemZTargetInfo::GCCRegNames[] = { 5697 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5698 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5699 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 5700 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 5701 }; 5702 5703 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 5704 unsigned &NumNames) const { 5705 Names = GCCRegNames; 5706 NumNames = llvm::array_lengthof(GCCRegNames); 5707 } 5708 5709 bool SystemZTargetInfo:: 5710 validateAsmConstraint(const char *&Name, 5711 TargetInfo::ConstraintInfo &Info) const { 5712 switch (*Name) { 5713 default: 5714 return false; 5715 5716 case 'a': // Address register 5717 case 'd': // Data register (equivalent to 'r') 5718 case 'f': // Floating-point register 5719 Info.setAllowsRegister(); 5720 return true; 5721 5722 case 'I': // Unsigned 8-bit constant 5723 case 'J': // Unsigned 12-bit constant 5724 case 'K': // Signed 16-bit constant 5725 case 'L': // Signed 20-bit displacement (on all targets we support) 5726 case 'M': // 0x7fffffff 5727 return true; 5728 5729 case 'Q': // Memory with base and unsigned 12-bit displacement 5730 case 'R': // Likewise, plus an index 5731 case 'S': // Memory with base and signed 20-bit displacement 5732 case 'T': // Likewise, plus an index 5733 Info.setAllowsMemory(); 5734 return true; 5735 } 5736 } 5737 5738 class MSP430TargetInfo : public TargetInfo { 5739 static const char * const GCCRegNames[]; 5740 public: 5741 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5742 BigEndian = false; 5743 TLSSupported = false; 5744 IntWidth = 16; IntAlign = 16; 5745 LongWidth = 32; LongLongWidth = 64; 5746 LongAlign = LongLongAlign = 16; 5747 PointerWidth = 16; PointerAlign = 16; 5748 SuitableAlign = 16; 5749 SizeType = UnsignedInt; 5750 IntMaxType = SignedLongLong; 5751 IntPtrType = SignedInt; 5752 PtrDiffType = SignedInt; 5753 SigAtomicType = SignedLong; 5754 DescriptionString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 5755 } 5756 void getTargetDefines(const LangOptions &Opts, 5757 MacroBuilder &Builder) const override { 5758 Builder.defineMacro("MSP430"); 5759 Builder.defineMacro("__MSP430__"); 5760 // FIXME: defines for different 'flavours' of MCU 5761 } 5762 void getTargetBuiltins(const Builtin::Info *&Records, 5763 unsigned &NumRecords) const override { 5764 // FIXME: Implement. 5765 Records = nullptr; 5766 NumRecords = 0; 5767 } 5768 bool hasFeature(StringRef Feature) const override { 5769 return Feature == "msp430"; 5770 } 5771 void getGCCRegNames(const char * const *&Names, 5772 unsigned &NumNames) const override; 5773 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5774 unsigned &NumAliases) const override { 5775 // No aliases. 5776 Aliases = nullptr; 5777 NumAliases = 0; 5778 } 5779 bool 5780 validateAsmConstraint(const char *&Name, 5781 TargetInfo::ConstraintInfo &info) const override { 5782 // FIXME: implement 5783 switch (*Name) { 5784 case 'K': // the constant 1 5785 case 'L': // constant -1^20 .. 1^19 5786 case 'M': // constant 1-4: 5787 return true; 5788 } 5789 // No target constraints for now. 5790 return false; 5791 } 5792 const char *getClobbers() const override { 5793 // FIXME: Is this really right? 5794 return ""; 5795 } 5796 BuiltinVaListKind getBuiltinVaListKind() const override { 5797 // FIXME: implement 5798 return TargetInfo::CharPtrBuiltinVaList; 5799 } 5800 }; 5801 5802 const char * const MSP430TargetInfo::GCCRegNames[] = { 5803 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5804 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 5805 }; 5806 5807 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 5808 unsigned &NumNames) const { 5809 Names = GCCRegNames; 5810 NumNames = llvm::array_lengthof(GCCRegNames); 5811 } 5812 5813 // LLVM and Clang cannot be used directly to output native binaries for 5814 // target, but is used to compile C code to llvm bitcode with correct 5815 // type and alignment information. 5816 // 5817 // TCE uses the llvm bitcode as input and uses it for generating customized 5818 // target processor and program binary. TCE co-design environment is 5819 // publicly available in http://tce.cs.tut.fi 5820 5821 static const unsigned TCEOpenCLAddrSpaceMap[] = { 5822 3, // opencl_global 5823 4, // opencl_local 5824 5, // opencl_constant 5825 // FIXME: generic has to be added to the target 5826 0, // opencl_generic 5827 0, // cuda_device 5828 0, // cuda_constant 5829 0 // cuda_shared 5830 }; 5831 5832 class TCETargetInfo : public TargetInfo{ 5833 public: 5834 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5835 TLSSupported = false; 5836 IntWidth = 32; 5837 LongWidth = LongLongWidth = 32; 5838 PointerWidth = 32; 5839 IntAlign = 32; 5840 LongAlign = LongLongAlign = 32; 5841 PointerAlign = 32; 5842 SuitableAlign = 32; 5843 SizeType = UnsignedInt; 5844 IntMaxType = SignedLong; 5845 IntPtrType = SignedInt; 5846 PtrDiffType = SignedInt; 5847 FloatWidth = 32; 5848 FloatAlign = 32; 5849 DoubleWidth = 32; 5850 DoubleAlign = 32; 5851 LongDoubleWidth = 32; 5852 LongDoubleAlign = 32; 5853 FloatFormat = &llvm::APFloat::IEEEsingle; 5854 DoubleFormat = &llvm::APFloat::IEEEsingle; 5855 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 5856 DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 5857 "-f64:32-v64:32-v128:32-a:0:32-n32"; 5858 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 5859 UseAddrSpaceMapMangling = true; 5860 } 5861 5862 void getTargetDefines(const LangOptions &Opts, 5863 MacroBuilder &Builder) const override { 5864 DefineStd(Builder, "tce", Opts); 5865 Builder.defineMacro("__TCE__"); 5866 Builder.defineMacro("__TCE_V1__"); 5867 } 5868 bool hasFeature(StringRef Feature) const override { 5869 return Feature == "tce"; 5870 } 5871 5872 void getTargetBuiltins(const Builtin::Info *&Records, 5873 unsigned &NumRecords) const override {} 5874 const char *getClobbers() const override { 5875 return ""; 5876 } 5877 BuiltinVaListKind getBuiltinVaListKind() const override { 5878 return TargetInfo::VoidPtrBuiltinVaList; 5879 } 5880 void getGCCRegNames(const char * const *&Names, 5881 unsigned &NumNames) const override {} 5882 bool validateAsmConstraint(const char *&Name, 5883 TargetInfo::ConstraintInfo &info) const override{ 5884 return true; 5885 } 5886 void getGCCRegAliases(const GCCRegAlias *&Aliases, 5887 unsigned &NumAliases) const override {} 5888 }; 5889 5890 class MipsTargetInfoBase : public TargetInfo { 5891 virtual void setDescriptionString() = 0; 5892 5893 static const Builtin::Info BuiltinInfo[]; 5894 std::string CPU; 5895 bool IsMips16; 5896 bool IsMicromips; 5897 bool IsNan2008; 5898 bool IsSingleFloat; 5899 enum MipsFloatABI { 5900 HardFloat, SoftFloat 5901 } FloatABI; 5902 enum DspRevEnum { 5903 NoDSP, DSP1, DSP2 5904 } DspRev; 5905 bool HasMSA; 5906 5907 protected: 5908 bool HasFP64; 5909 std::string ABI; 5910 5911 public: 5912 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 5913 const std::string &CPUStr) 5914 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 5915 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 5916 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 5917 TheCXXABI.set(TargetCXXABI::GenericMIPS); 5918 } 5919 5920 bool isNaN2008Default() const { 5921 return CPU == "mips32r6" || CPU == "mips64r6"; 5922 } 5923 5924 bool isFP64Default() const { 5925 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 5926 } 5927 5928 bool isNan2008() const override { 5929 return IsNan2008; 5930 } 5931 5932 StringRef getABI() const override { return ABI; } 5933 bool setCPU(const std::string &Name) override { 5934 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 5935 getTriple().getArch() == llvm::Triple::mipsel; 5936 CPU = Name; 5937 return llvm::StringSwitch<bool>(Name) 5938 .Case("mips1", IsMips32) 5939 .Case("mips2", IsMips32) 5940 .Case("mips3", true) 5941 .Case("mips4", true) 5942 .Case("mips5", true) 5943 .Case("mips32", IsMips32) 5944 .Case("mips32r2", IsMips32) 5945 .Case("mips32r3", IsMips32) 5946 .Case("mips32r5", IsMips32) 5947 .Case("mips32r6", IsMips32) 5948 .Case("mips64", true) 5949 .Case("mips64r2", true) 5950 .Case("mips64r3", true) 5951 .Case("mips64r5", true) 5952 .Case("mips64r6", true) 5953 .Case("octeon", true) 5954 .Default(false); 5955 } 5956 const std::string& getCPU() const { return CPU; } 5957 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 5958 if (CPU == "octeon") 5959 Features["mips64r2"] = Features["cnmips"] = true; 5960 else 5961 Features[CPU] = true; 5962 } 5963 5964 void getTargetDefines(const LangOptions &Opts, 5965 MacroBuilder &Builder) const override { 5966 Builder.defineMacro("__mips__"); 5967 Builder.defineMacro("_mips"); 5968 if (Opts.GNUMode) 5969 Builder.defineMacro("mips"); 5970 5971 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5972 5973 switch (FloatABI) { 5974 case HardFloat: 5975 Builder.defineMacro("__mips_hard_float", Twine(1)); 5976 break; 5977 case SoftFloat: 5978 Builder.defineMacro("__mips_soft_float", Twine(1)); 5979 break; 5980 } 5981 5982 if (IsSingleFloat) 5983 Builder.defineMacro("__mips_single_float", Twine(1)); 5984 5985 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 5986 Builder.defineMacro("_MIPS_FPSET", 5987 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 5988 5989 if (IsMips16) 5990 Builder.defineMacro("__mips16", Twine(1)); 5991 5992 if (IsMicromips) 5993 Builder.defineMacro("__mips_micromips", Twine(1)); 5994 5995 if (IsNan2008) 5996 Builder.defineMacro("__mips_nan2008", Twine(1)); 5997 5998 switch (DspRev) { 5999 default: 6000 break; 6001 case DSP1: 6002 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6003 Builder.defineMacro("__mips_dsp", Twine(1)); 6004 break; 6005 case DSP2: 6006 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6007 Builder.defineMacro("__mips_dspr2", Twine(1)); 6008 Builder.defineMacro("__mips_dsp", Twine(1)); 6009 break; 6010 } 6011 6012 if (HasMSA) 6013 Builder.defineMacro("__mips_msa", Twine(1)); 6014 6015 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6016 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6017 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6018 6019 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6020 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6021 } 6022 6023 void getTargetBuiltins(const Builtin::Info *&Records, 6024 unsigned &NumRecords) const override { 6025 Records = BuiltinInfo; 6026 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 6027 } 6028 bool hasFeature(StringRef Feature) const override { 6029 return llvm::StringSwitch<bool>(Feature) 6030 .Case("mips", true) 6031 .Case("fp64", HasFP64) 6032 .Default(false); 6033 } 6034 BuiltinVaListKind getBuiltinVaListKind() const override { 6035 return TargetInfo::VoidPtrBuiltinVaList; 6036 } 6037 void getGCCRegNames(const char * const *&Names, 6038 unsigned &NumNames) const override { 6039 static const char *const GCCRegNames[] = { 6040 // CPU register names 6041 // Must match second column of GCCRegAliases 6042 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6043 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6044 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6045 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6046 // Floating point register names 6047 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6048 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6049 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6050 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6051 // Hi/lo and condition register names 6052 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6053 "$fcc5","$fcc6","$fcc7", 6054 // MSA register names 6055 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6056 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6057 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6058 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6059 // MSA control register names 6060 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6061 "$msarequest", "$msamap", "$msaunmap" 6062 }; 6063 Names = GCCRegNames; 6064 NumNames = llvm::array_lengthof(GCCRegNames); 6065 } 6066 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6067 unsigned &NumAliases) const override = 0; 6068 bool validateAsmConstraint(const char *&Name, 6069 TargetInfo::ConstraintInfo &Info) const override { 6070 switch (*Name) { 6071 default: 6072 return false; 6073 case 'r': // CPU registers. 6074 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6075 case 'y': // Equivalent to "r", backward compatibility only. 6076 case 'f': // floating-point registers. 6077 case 'c': // $25 for indirect jumps 6078 case 'l': // lo register 6079 case 'x': // hilo register pair 6080 Info.setAllowsRegister(); 6081 return true; 6082 case 'I': // Signed 16-bit constant 6083 case 'J': // Integer 0 6084 case 'K': // Unsigned 16-bit constant 6085 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6086 case 'M': // Constants not loadable via lui, addiu, or ori 6087 case 'N': // Constant -1 to -65535 6088 case 'O': // A signed 15-bit constant 6089 case 'P': // A constant between 1 go 65535 6090 return true; 6091 case 'R': // An address that can be used in a non-macro load or store 6092 Info.setAllowsMemory(); 6093 return true; 6094 case 'Z': 6095 if (Name[1] == 'C') { // An address usable by ll, and sc. 6096 Info.setAllowsMemory(); 6097 Name++; // Skip over 'Z'. 6098 return true; 6099 } 6100 return false; 6101 } 6102 } 6103 6104 std::string convertConstraint(const char *&Constraint) const override { 6105 std::string R; 6106 switch (*Constraint) { 6107 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6108 if (Constraint[1] == 'C') { 6109 R = std::string("^") + std::string(Constraint, 2); 6110 Constraint++; 6111 return R; 6112 } 6113 break; 6114 } 6115 return TargetInfo::convertConstraint(Constraint); 6116 } 6117 6118 const char *getClobbers() const override { 6119 // In GCC, $1 is not widely used in generated code (it's used only in a few 6120 // specific situations), so there is no real need for users to add it to 6121 // the clobbers list if they want to use it in their inline assembly code. 6122 // 6123 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6124 // code generation, so using it in inline assembly without adding it to the 6125 // clobbers list can cause conflicts between the inline assembly code and 6126 // the surrounding generated code. 6127 // 6128 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6129 // operands, which will conflict with the ".set at" assembler option (which 6130 // we use only for inline assembly, in order to maintain compatibility with 6131 // GCC) and will also conflict with the user's usage of $1. 6132 // 6133 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6134 // register for generated code is to automatically clobber $1 for all inline 6135 // assembly code. 6136 // 6137 // FIXME: We should automatically clobber $1 only for inline assembly code 6138 // which actually uses it. This would allow LLVM to use $1 for inline 6139 // assembly operands if the user's assembly code doesn't use it. 6140 return "~{$1}"; 6141 } 6142 6143 bool handleTargetFeatures(std::vector<std::string> &Features, 6144 DiagnosticsEngine &Diags) override { 6145 IsMips16 = false; 6146 IsMicromips = false; 6147 IsNan2008 = isNaN2008Default(); 6148 IsSingleFloat = false; 6149 FloatABI = HardFloat; 6150 DspRev = NoDSP; 6151 HasFP64 = isFP64Default(); 6152 6153 for (std::vector<std::string>::iterator it = Features.begin(), 6154 ie = Features.end(); it != ie; ++it) { 6155 if (*it == "+single-float") 6156 IsSingleFloat = true; 6157 else if (*it == "+soft-float") 6158 FloatABI = SoftFloat; 6159 else if (*it == "+mips16") 6160 IsMips16 = true; 6161 else if (*it == "+micromips") 6162 IsMicromips = true; 6163 else if (*it == "+dsp") 6164 DspRev = std::max(DspRev, DSP1); 6165 else if (*it == "+dspr2") 6166 DspRev = std::max(DspRev, DSP2); 6167 else if (*it == "+msa") 6168 HasMSA = true; 6169 else if (*it == "+fp64") 6170 HasFP64 = true; 6171 else if (*it == "-fp64") 6172 HasFP64 = false; 6173 else if (*it == "+nan2008") 6174 IsNan2008 = true; 6175 else if (*it == "-nan2008") 6176 IsNan2008 = false; 6177 } 6178 6179 setDescriptionString(); 6180 6181 return true; 6182 } 6183 6184 int getEHDataRegisterNumber(unsigned RegNo) const override { 6185 if (RegNo == 0) return 4; 6186 if (RegNo == 1) return 5; 6187 return -1; 6188 } 6189 6190 bool isCLZForZeroUndef() const override { return false; } 6191 }; 6192 6193 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6194 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6195 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6196 ALL_LANGUAGES }, 6197 #include "clang/Basic/BuiltinsMips.def" 6198 }; 6199 6200 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6201 public: 6202 Mips32TargetInfoBase(const llvm::Triple &Triple) 6203 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6204 SizeType = UnsignedInt; 6205 PtrDiffType = SignedInt; 6206 Int64Type = SignedLongLong; 6207 IntMaxType = Int64Type; 6208 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6209 } 6210 bool setABI(const std::string &Name) override { 6211 if (Name == "o32" || Name == "eabi") { 6212 ABI = Name; 6213 return true; 6214 } 6215 return false; 6216 } 6217 void getTargetDefines(const LangOptions &Opts, 6218 MacroBuilder &Builder) const override { 6219 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6220 6221 Builder.defineMacro("__mips", "32"); 6222 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6223 6224 const std::string& CPUStr = getCPU(); 6225 if (CPUStr == "mips32") 6226 Builder.defineMacro("__mips_isa_rev", "1"); 6227 else if (CPUStr == "mips32r2") 6228 Builder.defineMacro("__mips_isa_rev", "2"); 6229 else if (CPUStr == "mips32r3") 6230 Builder.defineMacro("__mips_isa_rev", "3"); 6231 else if (CPUStr == "mips32r5") 6232 Builder.defineMacro("__mips_isa_rev", "5"); 6233 else if (CPUStr == "mips32r6") 6234 Builder.defineMacro("__mips_isa_rev", "6"); 6235 6236 if (ABI == "o32") { 6237 Builder.defineMacro("__mips_o32"); 6238 Builder.defineMacro("_ABIO32", "1"); 6239 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6240 } 6241 else if (ABI == "eabi") 6242 Builder.defineMacro("__mips_eabi"); 6243 else 6244 llvm_unreachable("Invalid ABI for Mips32."); 6245 } 6246 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6247 unsigned &NumAliases) const override { 6248 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6249 { { "at" }, "$1" }, 6250 { { "v0" }, "$2" }, 6251 { { "v1" }, "$3" }, 6252 { { "a0" }, "$4" }, 6253 { { "a1" }, "$5" }, 6254 { { "a2" }, "$6" }, 6255 { { "a3" }, "$7" }, 6256 { { "t0" }, "$8" }, 6257 { { "t1" }, "$9" }, 6258 { { "t2" }, "$10" }, 6259 { { "t3" }, "$11" }, 6260 { { "t4" }, "$12" }, 6261 { { "t5" }, "$13" }, 6262 { { "t6" }, "$14" }, 6263 { { "t7" }, "$15" }, 6264 { { "s0" }, "$16" }, 6265 { { "s1" }, "$17" }, 6266 { { "s2" }, "$18" }, 6267 { { "s3" }, "$19" }, 6268 { { "s4" }, "$20" }, 6269 { { "s5" }, "$21" }, 6270 { { "s6" }, "$22" }, 6271 { { "s7" }, "$23" }, 6272 { { "t8" }, "$24" }, 6273 { { "t9" }, "$25" }, 6274 { { "k0" }, "$26" }, 6275 { { "k1" }, "$27" }, 6276 { { "gp" }, "$28" }, 6277 { { "sp","$sp" }, "$29" }, 6278 { { "fp","$fp" }, "$30" }, 6279 { { "ra" }, "$31" } 6280 }; 6281 Aliases = GCCRegAliases; 6282 NumAliases = llvm::array_lengthof(GCCRegAliases); 6283 } 6284 }; 6285 6286 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6287 void setDescriptionString() override { 6288 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6289 } 6290 6291 public: 6292 Mips32EBTargetInfo(const llvm::Triple &Triple) 6293 : Mips32TargetInfoBase(Triple) { 6294 } 6295 void getTargetDefines(const LangOptions &Opts, 6296 MacroBuilder &Builder) const override { 6297 DefineStd(Builder, "MIPSEB", Opts); 6298 Builder.defineMacro("_MIPSEB"); 6299 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6300 } 6301 }; 6302 6303 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 6304 void setDescriptionString() override { 6305 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6306 } 6307 6308 public: 6309 Mips32ELTargetInfo(const llvm::Triple &Triple) 6310 : Mips32TargetInfoBase(Triple) { 6311 BigEndian = false; 6312 } 6313 void getTargetDefines(const LangOptions &Opts, 6314 MacroBuilder &Builder) const override { 6315 DefineStd(Builder, "MIPSEL", Opts); 6316 Builder.defineMacro("_MIPSEL"); 6317 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6318 } 6319 }; 6320 6321 class Mips64TargetInfoBase : public MipsTargetInfoBase { 6322 public: 6323 Mips64TargetInfoBase(const llvm::Triple &Triple) 6324 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 6325 LongDoubleWidth = LongDoubleAlign = 128; 6326 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6327 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 6328 LongDoubleWidth = LongDoubleAlign = 64; 6329 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6330 } 6331 setN64ABITypes(); 6332 SuitableAlign = 128; 6333 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6334 } 6335 6336 void setN64ABITypes() { 6337 LongWidth = LongAlign = 64; 6338 PointerWidth = PointerAlign = 64; 6339 SizeType = UnsignedLong; 6340 PtrDiffType = SignedLong; 6341 Int64Type = SignedLong; 6342 IntMaxType = Int64Type; 6343 } 6344 6345 void setN32ABITypes() { 6346 LongWidth = LongAlign = 32; 6347 PointerWidth = PointerAlign = 32; 6348 SizeType = UnsignedInt; 6349 PtrDiffType = SignedInt; 6350 Int64Type = SignedLongLong; 6351 IntMaxType = Int64Type; 6352 } 6353 6354 bool setABI(const std::string &Name) override { 6355 if (Name == "n32") { 6356 setN32ABITypes(); 6357 ABI = Name; 6358 return true; 6359 } 6360 if (Name == "n64") { 6361 setN64ABITypes(); 6362 ABI = Name; 6363 return true; 6364 } 6365 return false; 6366 } 6367 6368 void getTargetDefines(const LangOptions &Opts, 6369 MacroBuilder &Builder) const override { 6370 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6371 6372 Builder.defineMacro("__mips", "64"); 6373 Builder.defineMacro("__mips64"); 6374 Builder.defineMacro("__mips64__"); 6375 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 6376 6377 const std::string& CPUStr = getCPU(); 6378 if (CPUStr == "mips64") 6379 Builder.defineMacro("__mips_isa_rev", "1"); 6380 else if (CPUStr == "mips64r2") 6381 Builder.defineMacro("__mips_isa_rev", "2"); 6382 else if (CPUStr == "mips64r3") 6383 Builder.defineMacro("__mips_isa_rev", "3"); 6384 else if (CPUStr == "mips64r5") 6385 Builder.defineMacro("__mips_isa_rev", "5"); 6386 else if (CPUStr == "mips64r6") 6387 Builder.defineMacro("__mips_isa_rev", "6"); 6388 6389 if (ABI == "n32") { 6390 Builder.defineMacro("__mips_n32"); 6391 Builder.defineMacro("_ABIN32", "2"); 6392 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 6393 } 6394 else if (ABI == "n64") { 6395 Builder.defineMacro("__mips_n64"); 6396 Builder.defineMacro("_ABI64", "3"); 6397 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 6398 } 6399 else 6400 llvm_unreachable("Invalid ABI for Mips64."); 6401 } 6402 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6403 unsigned &NumAliases) const override { 6404 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6405 { { "at" }, "$1" }, 6406 { { "v0" }, "$2" }, 6407 { { "v1" }, "$3" }, 6408 { { "a0" }, "$4" }, 6409 { { "a1" }, "$5" }, 6410 { { "a2" }, "$6" }, 6411 { { "a3" }, "$7" }, 6412 { { "a4" }, "$8" }, 6413 { { "a5" }, "$9" }, 6414 { { "a6" }, "$10" }, 6415 { { "a7" }, "$11" }, 6416 { { "t0" }, "$12" }, 6417 { { "t1" }, "$13" }, 6418 { { "t2" }, "$14" }, 6419 { { "t3" }, "$15" }, 6420 { { "s0" }, "$16" }, 6421 { { "s1" }, "$17" }, 6422 { { "s2" }, "$18" }, 6423 { { "s3" }, "$19" }, 6424 { { "s4" }, "$20" }, 6425 { { "s5" }, "$21" }, 6426 { { "s6" }, "$22" }, 6427 { { "s7" }, "$23" }, 6428 { { "t8" }, "$24" }, 6429 { { "t9" }, "$25" }, 6430 { { "k0" }, "$26" }, 6431 { { "k1" }, "$27" }, 6432 { { "gp" }, "$28" }, 6433 { { "sp","$sp" }, "$29" }, 6434 { { "fp","$fp" }, "$30" }, 6435 { { "ra" }, "$31" } 6436 }; 6437 Aliases = GCCRegAliases; 6438 NumAliases = llvm::array_lengthof(GCCRegAliases); 6439 } 6440 6441 bool hasInt128Type() const override { return true; } 6442 }; 6443 6444 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 6445 void setDescriptionString() override { 6446 if (ABI == "n32") 6447 DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6448 else 6449 DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6450 6451 } 6452 6453 public: 6454 Mips64EBTargetInfo(const llvm::Triple &Triple) 6455 : Mips64TargetInfoBase(Triple) {} 6456 void getTargetDefines(const LangOptions &Opts, 6457 MacroBuilder &Builder) const override { 6458 DefineStd(Builder, "MIPSEB", Opts); 6459 Builder.defineMacro("_MIPSEB"); 6460 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6461 } 6462 }; 6463 6464 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 6465 void setDescriptionString() override { 6466 if (ABI == "n32") 6467 DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6468 else 6469 DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 6470 } 6471 public: 6472 Mips64ELTargetInfo(const llvm::Triple &Triple) 6473 : Mips64TargetInfoBase(Triple) { 6474 // Default ABI is n64. 6475 BigEndian = false; 6476 } 6477 void getTargetDefines(const LangOptions &Opts, 6478 MacroBuilder &Builder) const override { 6479 DefineStd(Builder, "MIPSEL", Opts); 6480 Builder.defineMacro("_MIPSEL"); 6481 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 6482 } 6483 }; 6484 6485 class PNaClTargetInfo : public TargetInfo { 6486 public: 6487 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6488 BigEndian = false; 6489 this->UserLabelPrefix = ""; 6490 this->LongAlign = 32; 6491 this->LongWidth = 32; 6492 this->PointerAlign = 32; 6493 this->PointerWidth = 32; 6494 this->IntMaxType = TargetInfo::SignedLongLong; 6495 this->Int64Type = TargetInfo::SignedLongLong; 6496 this->DoubleAlign = 64; 6497 this->LongDoubleWidth = 64; 6498 this->LongDoubleAlign = 64; 6499 this->SizeType = TargetInfo::UnsignedInt; 6500 this->PtrDiffType = TargetInfo::SignedInt; 6501 this->IntPtrType = TargetInfo::SignedInt; 6502 this->RegParmMax = 0; // Disallow regparm 6503 } 6504 6505 void getDefaultFeatures(llvm::StringMap<bool> &Features) const override { 6506 } 6507 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 6508 Builder.defineMacro("__le32__"); 6509 Builder.defineMacro("__pnacl__"); 6510 } 6511 void getTargetDefines(const LangOptions &Opts, 6512 MacroBuilder &Builder) const override { 6513 getArchDefines(Opts, Builder); 6514 } 6515 bool hasFeature(StringRef Feature) const override { 6516 return Feature == "pnacl"; 6517 } 6518 void getTargetBuiltins(const Builtin::Info *&Records, 6519 unsigned &NumRecords) const override { 6520 } 6521 BuiltinVaListKind getBuiltinVaListKind() const override { 6522 return TargetInfo::PNaClABIBuiltinVaList; 6523 } 6524 void getGCCRegNames(const char * const *&Names, 6525 unsigned &NumNames) const override; 6526 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6527 unsigned &NumAliases) const override; 6528 bool validateAsmConstraint(const char *&Name, 6529 TargetInfo::ConstraintInfo &Info) const override { 6530 return false; 6531 } 6532 6533 const char *getClobbers() const override { 6534 return ""; 6535 } 6536 }; 6537 6538 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 6539 unsigned &NumNames) const { 6540 Names = nullptr; 6541 NumNames = 0; 6542 } 6543 6544 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 6545 unsigned &NumAliases) const { 6546 Aliases = nullptr; 6547 NumAliases = 0; 6548 } 6549 6550 class Le64TargetInfo : public TargetInfo { 6551 static const Builtin::Info BuiltinInfo[]; 6552 6553 public: 6554 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6555 BigEndian = false; 6556 NoAsmVariants = true; 6557 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6558 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6559 DescriptionString = 6560 "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 6561 } 6562 6563 void getTargetDefines(const LangOptions &Opts, 6564 MacroBuilder &Builder) const override { 6565 DefineStd(Builder, "unix", Opts); 6566 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 6567 Builder.defineMacro("__ELF__"); 6568 } 6569 void getTargetBuiltins(const Builtin::Info *&Records, 6570 unsigned &NumRecords) const override { 6571 Records = BuiltinInfo; 6572 NumRecords = clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin; 6573 } 6574 BuiltinVaListKind getBuiltinVaListKind() const override { 6575 return TargetInfo::PNaClABIBuiltinVaList; 6576 } 6577 const char *getClobbers() const override { return ""; } 6578 void getGCCRegNames(const char *const *&Names, 6579 unsigned &NumNames) const override { 6580 Names = nullptr; 6581 NumNames = 0; 6582 } 6583 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6584 unsigned &NumAliases) const override { 6585 Aliases = nullptr; 6586 NumAliases = 0; 6587 } 6588 bool validateAsmConstraint(const char *&Name, 6589 TargetInfo::ConstraintInfo &Info) const override { 6590 return false; 6591 } 6592 6593 bool hasProtectedVisibility() const override { return false; } 6594 }; 6595 } // end anonymous namespace. 6596 6597 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 6598 #define BUILTIN(ID, TYPE, ATTRS) \ 6599 { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6600 #include "clang/Basic/BuiltinsLe64.def" 6601 }; 6602 6603 namespace { 6604 static const unsigned SPIRAddrSpaceMap[] = { 6605 1, // opencl_global 6606 3, // opencl_local 6607 2, // opencl_constant 6608 4, // opencl_generic 6609 0, // cuda_device 6610 0, // cuda_constant 6611 0 // cuda_shared 6612 }; 6613 class SPIRTargetInfo : public TargetInfo { 6614 public: 6615 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6616 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 6617 "SPIR target must use unknown OS"); 6618 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 6619 "SPIR target must use unknown environment type"); 6620 BigEndian = false; 6621 TLSSupported = false; 6622 LongWidth = LongAlign = 64; 6623 AddrSpaceMap = &SPIRAddrSpaceMap; 6624 UseAddrSpaceMapMangling = true; 6625 // Define available target features 6626 // These must be defined in sorted order! 6627 NoAsmVariants = true; 6628 } 6629 void getTargetDefines(const LangOptions &Opts, 6630 MacroBuilder &Builder) const override { 6631 DefineStd(Builder, "SPIR", Opts); 6632 } 6633 bool hasFeature(StringRef Feature) const override { 6634 return Feature == "spir"; 6635 } 6636 6637 void getTargetBuiltins(const Builtin::Info *&Records, 6638 unsigned &NumRecords) const override {} 6639 const char *getClobbers() const override { 6640 return ""; 6641 } 6642 void getGCCRegNames(const char * const *&Names, 6643 unsigned &NumNames) const override {} 6644 bool 6645 validateAsmConstraint(const char *&Name, 6646 TargetInfo::ConstraintInfo &info) const override { 6647 return true; 6648 } 6649 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6650 unsigned &NumAliases) const override {} 6651 BuiltinVaListKind getBuiltinVaListKind() const override { 6652 return TargetInfo::VoidPtrBuiltinVaList; 6653 } 6654 6655 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6656 return (CC == CC_SpirFunction || 6657 CC == CC_SpirKernel) ? CCCR_OK : CCCR_Warning; 6658 } 6659 6660 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 6661 return CC_SpirFunction; 6662 } 6663 }; 6664 6665 6666 class SPIR32TargetInfo : public SPIRTargetInfo { 6667 public: 6668 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6669 PointerWidth = PointerAlign = 32; 6670 SizeType = TargetInfo::UnsignedInt; 6671 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 6672 DescriptionString 6673 = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 6674 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6675 } 6676 void getTargetDefines(const LangOptions &Opts, 6677 MacroBuilder &Builder) const override { 6678 DefineStd(Builder, "SPIR32", Opts); 6679 } 6680 }; 6681 6682 class SPIR64TargetInfo : public SPIRTargetInfo { 6683 public: 6684 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 6685 PointerWidth = PointerAlign = 64; 6686 SizeType = TargetInfo::UnsignedLong; 6687 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 6688 DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 6689 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 6690 } 6691 void getTargetDefines(const LangOptions &Opts, 6692 MacroBuilder &Builder) const override { 6693 DefineStd(Builder, "SPIR64", Opts); 6694 } 6695 }; 6696 6697 class XCoreTargetInfo : public TargetInfo { 6698 static const Builtin::Info BuiltinInfo[]; 6699 public: 6700 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6701 BigEndian = false; 6702 NoAsmVariants = true; 6703 LongLongAlign = 32; 6704 SuitableAlign = 32; 6705 DoubleAlign = LongDoubleAlign = 32; 6706 SizeType = UnsignedInt; 6707 PtrDiffType = SignedInt; 6708 IntPtrType = SignedInt; 6709 WCharType = UnsignedChar; 6710 WIntType = UnsignedInt; 6711 UseZeroLengthBitfieldAlignment = true; 6712 DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 6713 "-f64:32-a:0:32-n32"; 6714 } 6715 void getTargetDefines(const LangOptions &Opts, 6716 MacroBuilder &Builder) const override { 6717 Builder.defineMacro("__XS1B__"); 6718 } 6719 void getTargetBuiltins(const Builtin::Info *&Records, 6720 unsigned &NumRecords) const override { 6721 Records = BuiltinInfo; 6722 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 6723 } 6724 BuiltinVaListKind getBuiltinVaListKind() const override { 6725 return TargetInfo::VoidPtrBuiltinVaList; 6726 } 6727 const char *getClobbers() const override { 6728 return ""; 6729 } 6730 void getGCCRegNames(const char * const *&Names, 6731 unsigned &NumNames) const override { 6732 static const char * const GCCRegNames[] = { 6733 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6734 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 6735 }; 6736 Names = GCCRegNames; 6737 NumNames = llvm::array_lengthof(GCCRegNames); 6738 } 6739 void getGCCRegAliases(const GCCRegAlias *&Aliases, 6740 unsigned &NumAliases) const override { 6741 Aliases = nullptr; 6742 NumAliases = 0; 6743 } 6744 bool validateAsmConstraint(const char *&Name, 6745 TargetInfo::ConstraintInfo &Info) const override { 6746 return false; 6747 } 6748 int getEHDataRegisterNumber(unsigned RegNo) const override { 6749 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 6750 return (RegNo < 2)? RegNo : -1; 6751 } 6752 }; 6753 6754 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 6755 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 6756 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 6757 ALL_LANGUAGES }, 6758 #include "clang/Basic/BuiltinsXCore.def" 6759 }; 6760 } // end anonymous namespace. 6761 6762 namespace { 6763 // x86_32 Android target 6764 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 6765 public: 6766 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 6767 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 6768 SuitableAlign = 32; 6769 LongDoubleWidth = 64; 6770 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 6771 } 6772 }; 6773 } // end anonymous namespace 6774 6775 namespace { 6776 // x86_64 Android target 6777 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 6778 public: 6779 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 6780 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 6781 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6782 } 6783 }; 6784 } // end anonymous namespace 6785 6786 6787 //===----------------------------------------------------------------------===// 6788 // Driver code 6789 //===----------------------------------------------------------------------===// 6790 6791 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 6792 llvm::Triple::OSType os = Triple.getOS(); 6793 6794 switch (Triple.getArch()) { 6795 default: 6796 return nullptr; 6797 6798 case llvm::Triple::xcore: 6799 return new XCoreTargetInfo(Triple); 6800 6801 case llvm::Triple::hexagon: 6802 return new HexagonTargetInfo(Triple); 6803 6804 case llvm::Triple::aarch64: 6805 if (Triple.isOSDarwin()) 6806 return new DarwinAArch64TargetInfo(Triple); 6807 6808 switch (os) { 6809 case llvm::Triple::FreeBSD: 6810 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 6811 case llvm::Triple::Linux: 6812 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 6813 case llvm::Triple::NetBSD: 6814 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 6815 default: 6816 return new AArch64leTargetInfo(Triple); 6817 } 6818 6819 case llvm::Triple::aarch64_be: 6820 switch (os) { 6821 case llvm::Triple::FreeBSD: 6822 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 6823 case llvm::Triple::Linux: 6824 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 6825 case llvm::Triple::NetBSD: 6826 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 6827 default: 6828 return new AArch64beTargetInfo(Triple); 6829 } 6830 6831 case llvm::Triple::arm: 6832 case llvm::Triple::thumb: 6833 if (Triple.isOSBinFormatMachO()) 6834 return new DarwinARMTargetInfo(Triple); 6835 6836 switch (os) { 6837 case llvm::Triple::Linux: 6838 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 6839 case llvm::Triple::FreeBSD: 6840 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 6841 case llvm::Triple::NetBSD: 6842 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 6843 case llvm::Triple::OpenBSD: 6844 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 6845 case llvm::Triple::Bitrig: 6846 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 6847 case llvm::Triple::RTEMS: 6848 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 6849 case llvm::Triple::NaCl: 6850 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 6851 case llvm::Triple::Win32: 6852 switch (Triple.getEnvironment()) { 6853 default: 6854 return new ARMleTargetInfo(Triple); 6855 case llvm::Triple::Itanium: 6856 return new ItaniumWindowsARMleTargetInfo(Triple); 6857 case llvm::Triple::MSVC: 6858 return new MicrosoftARMleTargetInfo(Triple); 6859 } 6860 default: 6861 return new ARMleTargetInfo(Triple); 6862 } 6863 6864 case llvm::Triple::armeb: 6865 case llvm::Triple::thumbeb: 6866 if (Triple.isOSDarwin()) 6867 return new DarwinARMTargetInfo(Triple); 6868 6869 switch (os) { 6870 case llvm::Triple::Linux: 6871 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 6872 case llvm::Triple::FreeBSD: 6873 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 6874 case llvm::Triple::NetBSD: 6875 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 6876 case llvm::Triple::OpenBSD: 6877 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 6878 case llvm::Triple::Bitrig: 6879 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 6880 case llvm::Triple::RTEMS: 6881 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 6882 case llvm::Triple::NaCl: 6883 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 6884 default: 6885 return new ARMbeTargetInfo(Triple); 6886 } 6887 6888 case llvm::Triple::msp430: 6889 return new MSP430TargetInfo(Triple); 6890 6891 case llvm::Triple::mips: 6892 switch (os) { 6893 case llvm::Triple::Linux: 6894 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 6895 case llvm::Triple::RTEMS: 6896 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 6897 case llvm::Triple::FreeBSD: 6898 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6899 case llvm::Triple::NetBSD: 6900 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 6901 default: 6902 return new Mips32EBTargetInfo(Triple); 6903 } 6904 6905 case llvm::Triple::mipsel: 6906 switch (os) { 6907 case llvm::Triple::Linux: 6908 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 6909 case llvm::Triple::RTEMS: 6910 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 6911 case llvm::Triple::FreeBSD: 6912 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6913 case llvm::Triple::NetBSD: 6914 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 6915 case llvm::Triple::NaCl: 6916 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 6917 default: 6918 return new Mips32ELTargetInfo(Triple); 6919 } 6920 6921 case llvm::Triple::mips64: 6922 switch (os) { 6923 case llvm::Triple::Linux: 6924 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 6925 case llvm::Triple::RTEMS: 6926 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 6927 case llvm::Triple::FreeBSD: 6928 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6929 case llvm::Triple::NetBSD: 6930 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6931 case llvm::Triple::OpenBSD: 6932 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 6933 default: 6934 return new Mips64EBTargetInfo(Triple); 6935 } 6936 6937 case llvm::Triple::mips64el: 6938 switch (os) { 6939 case llvm::Triple::Linux: 6940 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 6941 case llvm::Triple::RTEMS: 6942 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 6943 case llvm::Triple::FreeBSD: 6944 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6945 case llvm::Triple::NetBSD: 6946 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6947 case llvm::Triple::OpenBSD: 6948 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 6949 default: 6950 return new Mips64ELTargetInfo(Triple); 6951 } 6952 6953 case llvm::Triple::le32: 6954 switch (os) { 6955 case llvm::Triple::NaCl: 6956 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 6957 default: 6958 return nullptr; 6959 } 6960 6961 case llvm::Triple::le64: 6962 return new Le64TargetInfo(Triple); 6963 6964 case llvm::Triple::ppc: 6965 if (Triple.isOSDarwin()) 6966 return new DarwinPPC32TargetInfo(Triple); 6967 switch (os) { 6968 case llvm::Triple::Linux: 6969 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 6970 case llvm::Triple::FreeBSD: 6971 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 6972 case llvm::Triple::NetBSD: 6973 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 6974 case llvm::Triple::OpenBSD: 6975 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 6976 case llvm::Triple::RTEMS: 6977 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 6978 default: 6979 return new PPC32TargetInfo(Triple); 6980 } 6981 6982 case llvm::Triple::ppc64: 6983 if (Triple.isOSDarwin()) 6984 return new DarwinPPC64TargetInfo(Triple); 6985 switch (os) { 6986 case llvm::Triple::Linux: 6987 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 6988 case llvm::Triple::Lv2: 6989 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 6990 case llvm::Triple::FreeBSD: 6991 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 6992 case llvm::Triple::NetBSD: 6993 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 6994 default: 6995 return new PPC64TargetInfo(Triple); 6996 } 6997 6998 case llvm::Triple::ppc64le: 6999 switch (os) { 7000 case llvm::Triple::Linux: 7001 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7002 case llvm::Triple::NetBSD: 7003 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7004 default: 7005 return new PPC64TargetInfo(Triple); 7006 } 7007 7008 case llvm::Triple::nvptx: 7009 return new NVPTX32TargetInfo(Triple); 7010 case llvm::Triple::nvptx64: 7011 return new NVPTX64TargetInfo(Triple); 7012 7013 case llvm::Triple::amdgcn: 7014 case llvm::Triple::r600: 7015 return new R600TargetInfo(Triple); 7016 7017 case llvm::Triple::sparc: 7018 switch (os) { 7019 case llvm::Triple::Linux: 7020 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7021 case llvm::Triple::Solaris: 7022 return new SolarisSparcV8TargetInfo(Triple); 7023 case llvm::Triple::NetBSD: 7024 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7025 case llvm::Triple::OpenBSD: 7026 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7027 case llvm::Triple::RTEMS: 7028 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7029 default: 7030 return new SparcV8TargetInfo(Triple); 7031 } 7032 7033 // The 'sparcel' architecture copies all the above cases except for Solaris. 7034 case llvm::Triple::sparcel: 7035 switch (os) { 7036 case llvm::Triple::Linux: 7037 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7038 case llvm::Triple::NetBSD: 7039 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7040 case llvm::Triple::OpenBSD: 7041 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7042 case llvm::Triple::RTEMS: 7043 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7044 default: 7045 return new SparcV8elTargetInfo(Triple); 7046 } 7047 7048 case llvm::Triple::sparcv9: 7049 switch (os) { 7050 case llvm::Triple::Linux: 7051 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7052 case llvm::Triple::Solaris: 7053 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7054 case llvm::Triple::NetBSD: 7055 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7056 case llvm::Triple::OpenBSD: 7057 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7058 case llvm::Triple::FreeBSD: 7059 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7060 default: 7061 return new SparcV9TargetInfo(Triple); 7062 } 7063 7064 case llvm::Triple::systemz: 7065 switch (os) { 7066 case llvm::Triple::Linux: 7067 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7068 default: 7069 return new SystemZTargetInfo(Triple); 7070 } 7071 7072 case llvm::Triple::tce: 7073 return new TCETargetInfo(Triple); 7074 7075 case llvm::Triple::x86: 7076 if (Triple.isOSDarwin()) 7077 return new DarwinI386TargetInfo(Triple); 7078 7079 switch (os) { 7080 case llvm::Triple::Linux: { 7081 switch (Triple.getEnvironment()) { 7082 default: 7083 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7084 case llvm::Triple::Android: 7085 return new AndroidX86_32TargetInfo(Triple); 7086 } 7087 } 7088 case llvm::Triple::DragonFly: 7089 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7090 case llvm::Triple::NetBSD: 7091 return new NetBSDI386TargetInfo(Triple); 7092 case llvm::Triple::OpenBSD: 7093 return new OpenBSDI386TargetInfo(Triple); 7094 case llvm::Triple::Bitrig: 7095 return new BitrigI386TargetInfo(Triple); 7096 case llvm::Triple::FreeBSD: 7097 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7098 case llvm::Triple::KFreeBSD: 7099 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7100 case llvm::Triple::Minix: 7101 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7102 case llvm::Triple::Solaris: 7103 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7104 case llvm::Triple::Win32: { 7105 switch (Triple.getEnvironment()) { 7106 default: 7107 return new X86_32TargetInfo(Triple); 7108 case llvm::Triple::Cygnus: 7109 return new CygwinX86_32TargetInfo(Triple); 7110 case llvm::Triple::GNU: 7111 return new MinGWX86_32TargetInfo(Triple); 7112 case llvm::Triple::Itanium: 7113 case llvm::Triple::MSVC: 7114 return new MicrosoftX86_32TargetInfo(Triple); 7115 } 7116 } 7117 case llvm::Triple::Haiku: 7118 return new HaikuX86_32TargetInfo(Triple); 7119 case llvm::Triple::RTEMS: 7120 return new RTEMSX86_32TargetInfo(Triple); 7121 case llvm::Triple::NaCl: 7122 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7123 default: 7124 return new X86_32TargetInfo(Triple); 7125 } 7126 7127 case llvm::Triple::x86_64: 7128 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7129 return new DarwinX86_64TargetInfo(Triple); 7130 7131 switch (os) { 7132 case llvm::Triple::CloudABI: 7133 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7134 case llvm::Triple::Linux: { 7135 switch (Triple.getEnvironment()) { 7136 default: 7137 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7138 case llvm::Triple::Android: 7139 return new AndroidX86_64TargetInfo(Triple); 7140 } 7141 } 7142 case llvm::Triple::DragonFly: 7143 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7144 case llvm::Triple::NetBSD: 7145 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7146 case llvm::Triple::OpenBSD: 7147 return new OpenBSDX86_64TargetInfo(Triple); 7148 case llvm::Triple::Bitrig: 7149 return new BitrigX86_64TargetInfo(Triple); 7150 case llvm::Triple::FreeBSD: 7151 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7152 case llvm::Triple::KFreeBSD: 7153 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7154 case llvm::Triple::Solaris: 7155 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7156 case llvm::Triple::Win32: { 7157 switch (Triple.getEnvironment()) { 7158 default: 7159 return new X86_64TargetInfo(Triple); 7160 case llvm::Triple::GNU: 7161 return new MinGWX86_64TargetInfo(Triple); 7162 case llvm::Triple::MSVC: 7163 return new MicrosoftX86_64TargetInfo(Triple); 7164 } 7165 } 7166 case llvm::Triple::NaCl: 7167 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 7168 case llvm::Triple::PS4: 7169 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 7170 default: 7171 return new X86_64TargetInfo(Triple); 7172 } 7173 7174 case llvm::Triple::spir: { 7175 if (Triple.getOS() != llvm::Triple::UnknownOS || 7176 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7177 return nullptr; 7178 return new SPIR32TargetInfo(Triple); 7179 } 7180 case llvm::Triple::spir64: { 7181 if (Triple.getOS() != llvm::Triple::UnknownOS || 7182 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 7183 return nullptr; 7184 return new SPIR64TargetInfo(Triple); 7185 } 7186 } 7187 } 7188 7189 /// CreateTargetInfo - Return the target info object for the specified target 7190 /// triple. 7191 TargetInfo * 7192 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 7193 const std::shared_ptr<TargetOptions> &Opts) { 7194 llvm::Triple Triple(Opts->Triple); 7195 7196 // Construct the target 7197 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 7198 if (!Target) { 7199 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 7200 return nullptr; 7201 } 7202 Target->TargetOpts = Opts; 7203 7204 // Set the target CPU if specified. 7205 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 7206 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 7207 return nullptr; 7208 } 7209 7210 // Set the target ABI if specified. 7211 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 7212 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 7213 return nullptr; 7214 } 7215 7216 // Set the fp math unit. 7217 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 7218 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 7219 return nullptr; 7220 } 7221 7222 // Compute the default target features, we need the target to handle this 7223 // because features may have dependencies on one another. 7224 llvm::StringMap<bool> Features; 7225 Target->getDefaultFeatures(Features); 7226 7227 // Apply the user specified deltas. 7228 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 7229 I < N; ++I) { 7230 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 7231 // Apply the feature via the target. 7232 bool Enabled = Name[0] == '+'; 7233 Target->setFeatureEnabled(Features, Name + 1, Enabled); 7234 } 7235 7236 // Add the features to the compile options. 7237 // 7238 // FIXME: If we are completely confident that we have the right set, we only 7239 // need to pass the minuses. 7240 Opts->Features.clear(); 7241 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 7242 ie = Features.end(); it != ie; ++it) 7243 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 7244 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 7245 return nullptr; 7246 7247 return Target.release(); 7248 } 7249