1 //===--- Targets.cpp - Implement -arch option and targets -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements construction of a TargetInfo object from a
11 // target triple.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "clang/Basic/TargetInfo.h"
16 #include "clang/Basic/Builtins.h"
17 #include "clang/Basic/Diagnostic.h"
18 #include "clang/Basic/LangOptions.h"
19 #include "clang/Basic/MacroBuilder.h"
20 #include "clang/Basic/TargetBuiltins.h"
21 #include "clang/Basic/TargetOptions.h"
22 #include "llvm/ADT/APFloat.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/ADT/StringRef.h"
25 #include "llvm/ADT/StringSwitch.h"
26 #include "llvm/ADT/Triple.h"
27 #include "llvm/IR/Type.h"
28 #include "llvm/MC/MCSectionMachO.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include <algorithm>
31 #include <memory>
32 using namespace clang;
33 
34 //===----------------------------------------------------------------------===//
35 //  Common code shared among targets.
36 //===----------------------------------------------------------------------===//
37 
38 /// DefineStd - Define a macro name and standard variants.  For example if
39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix"
40 /// when in GNU mode.
41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName,
42                       const LangOptions &Opts) {
43   assert(MacroName[0] != '_' && "Identifier should be in the user's namespace");
44 
45   // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier
46   // in the user's namespace.
47   if (Opts.GNUMode)
48     Builder.defineMacro(MacroName);
49 
50   // Define __unix.
51   Builder.defineMacro("__" + MacroName);
52 
53   // Define __unix__.
54   Builder.defineMacro("__" + MacroName + "__");
55 }
56 
57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName,
58                             bool Tuning = true) {
59   Builder.defineMacro("__" + CPUName);
60   Builder.defineMacro("__" + CPUName + "__");
61   if (Tuning)
62     Builder.defineMacro("__tune_" + CPUName + "__");
63 }
64 
65 //===----------------------------------------------------------------------===//
66 // Defines specific to certain operating systems.
67 //===----------------------------------------------------------------------===//
68 
69 namespace {
70 template<typename TgtInfo>
71 class OSTargetInfo : public TgtInfo {
72 protected:
73   virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
74                             MacroBuilder &Builder) const=0;
75 public:
76   OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {}
77   void getTargetDefines(const LangOptions &Opts,
78                         MacroBuilder &Builder) const override {
79     TgtInfo::getTargetDefines(Opts, Builder);
80     getOSDefines(Opts, TgtInfo::getTriple(), Builder);
81   }
82 
83 };
84 } // end anonymous namespace
85 
86 
87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts,
88                              const llvm::Triple &Triple,
89                              StringRef &PlatformName,
90                              VersionTuple &PlatformMinVersion) {
91   Builder.defineMacro("__APPLE_CC__", "6000");
92   Builder.defineMacro("__APPLE__");
93   Builder.defineMacro("OBJC_NEW_PROPERTIES");
94   // AddressSanitizer doesn't play well with source fortification, which is on
95   // by default on Darwin.
96   if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0");
97 
98   if (!Opts.ObjCAutoRefCount) {
99     // __weak is always defined, for use in blocks and with objc pointers.
100     Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))");
101 
102     // Darwin defines __strong even in C mode (just to nothing).
103     if (Opts.getGC() != LangOptions::NonGC)
104       Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))");
105     else
106       Builder.defineMacro("__strong", "");
107 
108     // __unsafe_unretained is defined to nothing in non-ARC mode. We even
109     // allow this in C, since one might have block pointers in structs that
110     // are used in pure C code and in Objective-C ARC.
111     Builder.defineMacro("__unsafe_unretained", "");
112   }
113 
114   if (Opts.Static)
115     Builder.defineMacro("__STATIC__");
116   else
117     Builder.defineMacro("__DYNAMIC__");
118 
119   if (Opts.POSIXThreads)
120     Builder.defineMacro("_REENTRANT");
121 
122   // Get the platform type and version number from the triple.
123   unsigned Maj, Min, Rev;
124   if (Triple.isMacOSX()) {
125     Triple.getMacOSXVersion(Maj, Min, Rev);
126     PlatformName = "macosx";
127   } else {
128     Triple.getOSVersion(Maj, Min, Rev);
129     PlatformName = llvm::Triple::getOSTypeName(Triple.getOS());
130   }
131 
132   // If -target arch-pc-win32-macho option specified, we're
133   // generating code for Win32 ABI. No need to emit
134   // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__.
135   if (PlatformName == "win32") {
136     PlatformMinVersion = VersionTuple(Maj, Min, Rev);
137     return;
138   }
139 
140   // Set the appropriate OS version define.
141   if (Triple.isiOS()) {
142     assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!");
143     char Str[6];
144     Str[0] = '0' + Maj;
145     Str[1] = '0' + (Min / 10);
146     Str[2] = '0' + (Min % 10);
147     Str[3] = '0' + (Rev / 10);
148     Str[4] = '0' + (Rev % 10);
149     Str[5] = '\0';
150     Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__",
151                         Str);
152   } else if (Triple.isMacOSX()) {
153     // Note that the Driver allows versions which aren't representable in the
154     // define (because we only get a single digit for the minor and micro
155     // revision numbers). So, we limit them to the maximum representable
156     // version.
157     assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!");
158     char Str[5];
159     Str[0] = '0' + (Maj / 10);
160     Str[1] = '0' + (Maj % 10);
161     Str[2] = '0' + std::min(Min, 9U);
162     Str[3] = '0' + std::min(Rev, 9U);
163     Str[4] = '\0';
164     Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str);
165   }
166 
167   // Tell users about the kernel if there is one.
168   if (Triple.isOSDarwin())
169     Builder.defineMacro("__MACH__");
170 
171   PlatformMinVersion = VersionTuple(Maj, Min, Rev);
172 }
173 
174 namespace {
175 template<typename Target>
176 class DarwinTargetInfo : public OSTargetInfo<Target> {
177 protected:
178   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
179                     MacroBuilder &Builder) const override {
180     getDarwinDefines(Builder, Opts, Triple, this->PlatformName,
181                      this->PlatformMinVersion);
182   }
183 
184 public:
185   DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
186     this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7);
187     this->MCountName = "\01mcount";
188   }
189 
190   std::string isValidSectionSpecifier(StringRef SR) const override {
191     // Let MCSectionMachO validate this.
192     StringRef Segment, Section;
193     unsigned TAA, StubSize;
194     bool HasTAA;
195     return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section,
196                                                        TAA, HasTAA, StubSize);
197   }
198 
199   const char *getStaticInitSectionSpecifier() const override {
200     // FIXME: We should return 0 when building kexts.
201     return "__TEXT,__StaticInit,regular,pure_instructions";
202   }
203 
204   /// Darwin does not support protected visibility.  Darwin's "default"
205   /// is very similar to ELF's "protected";  Darwin requires a "weak"
206   /// attribute on declarations that can be dynamically replaced.
207   bool hasProtectedVisibility() const override {
208     return false;
209   }
210 };
211 
212 
213 // DragonFlyBSD Target
214 template<typename Target>
215 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> {
216 protected:
217   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
218                     MacroBuilder &Builder) const override {
219     // DragonFly defines; list based off of gcc output
220     Builder.defineMacro("__DragonFly__");
221     Builder.defineMacro("__DragonFly_cc_version", "100001");
222     Builder.defineMacro("__ELF__");
223     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
224     Builder.defineMacro("__tune_i386__");
225     DefineStd(Builder, "unix", Opts);
226   }
227 public:
228   DragonFlyBSDTargetInfo(const llvm::Triple &Triple)
229       : OSTargetInfo<Target>(Triple) {
230     this->UserLabelPrefix = "";
231 
232     switch (Triple.getArch()) {
233     default:
234     case llvm::Triple::x86:
235     case llvm::Triple::x86_64:
236       this->MCountName = ".mcount";
237       break;
238     }
239   }
240 };
241 
242 // FreeBSD Target
243 template<typename Target>
244 class FreeBSDTargetInfo : public OSTargetInfo<Target> {
245 protected:
246   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
247                     MacroBuilder &Builder) const override {
248     // FreeBSD defines; list based off of gcc output
249 
250     unsigned Release = Triple.getOSMajorVersion();
251     if (Release == 0U)
252       Release = 8;
253 
254     Builder.defineMacro("__FreeBSD__", Twine(Release));
255     Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U));
256     Builder.defineMacro("__KPRINTF_ATTRIBUTE__");
257     DefineStd(Builder, "unix", Opts);
258     Builder.defineMacro("__ELF__");
259 
260     // On FreeBSD, wchar_t contains the number of the code point as
261     // used by the character set of the locale. These character sets are
262     // not necessarily a superset of ASCII.
263     Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1");
264   }
265 public:
266   FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
267     this->UserLabelPrefix = "";
268 
269     switch (Triple.getArch()) {
270     default:
271     case llvm::Triple::x86:
272     case llvm::Triple::x86_64:
273       this->MCountName = ".mcount";
274       break;
275     case llvm::Triple::mips:
276     case llvm::Triple::mipsel:
277     case llvm::Triple::ppc:
278     case llvm::Triple::ppc64:
279     case llvm::Triple::ppc64le:
280       this->MCountName = "_mcount";
281       break;
282     case llvm::Triple::arm:
283       this->MCountName = "__mcount";
284       break;
285     }
286   }
287 };
288 
289 // GNU/kFreeBSD Target
290 template<typename Target>
291 class KFreeBSDTargetInfo : public OSTargetInfo<Target> {
292 protected:
293   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
294                     MacroBuilder &Builder) const override {
295     // GNU/kFreeBSD defines; list based off of gcc output
296 
297     DefineStd(Builder, "unix", Opts);
298     Builder.defineMacro("__FreeBSD_kernel__");
299     Builder.defineMacro("__GLIBC__");
300     Builder.defineMacro("__ELF__");
301     if (Opts.POSIXThreads)
302       Builder.defineMacro("_REENTRANT");
303     if (Opts.CPlusPlus)
304       Builder.defineMacro("_GNU_SOURCE");
305   }
306 public:
307   KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
308     this->UserLabelPrefix = "";
309   }
310 };
311 
312 // Minix Target
313 template<typename Target>
314 class MinixTargetInfo : public OSTargetInfo<Target> {
315 protected:
316   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
317                     MacroBuilder &Builder) const override {
318     // Minix defines
319 
320     Builder.defineMacro("__minix", "3");
321     Builder.defineMacro("_EM_WSIZE", "4");
322     Builder.defineMacro("_EM_PSIZE", "4");
323     Builder.defineMacro("_EM_SSIZE", "2");
324     Builder.defineMacro("_EM_LSIZE", "4");
325     Builder.defineMacro("_EM_FSIZE", "4");
326     Builder.defineMacro("_EM_DSIZE", "8");
327     Builder.defineMacro("__ELF__");
328     DefineStd(Builder, "unix", Opts);
329   }
330 public:
331   MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
332     this->UserLabelPrefix = "";
333   }
334 };
335 
336 // Linux target
337 template<typename Target>
338 class LinuxTargetInfo : public OSTargetInfo<Target> {
339 protected:
340   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
341                     MacroBuilder &Builder) const override {
342     // Linux defines; list based off of gcc output
343     DefineStd(Builder, "unix", Opts);
344     DefineStd(Builder, "linux", Opts);
345     Builder.defineMacro("__gnu_linux__");
346     Builder.defineMacro("__ELF__");
347     if (Triple.getEnvironment() == llvm::Triple::Android)
348       Builder.defineMacro("__ANDROID__", "1");
349     if (Opts.POSIXThreads)
350       Builder.defineMacro("_REENTRANT");
351     if (Opts.CPlusPlus)
352       Builder.defineMacro("_GNU_SOURCE");
353   }
354 public:
355   LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
356     this->UserLabelPrefix = "";
357     this->WIntType = TargetInfo::UnsignedInt;
358 
359     switch (Triple.getArch()) {
360     default:
361       break;
362     case llvm::Triple::ppc:
363     case llvm::Triple::ppc64:
364     case llvm::Triple::ppc64le:
365       this->MCountName = "_mcount";
366       break;
367     }
368   }
369 
370   const char *getStaticInitSectionSpecifier() const override {
371     return ".text.startup";
372   }
373 };
374 
375 // NetBSD Target
376 template<typename Target>
377 class NetBSDTargetInfo : public OSTargetInfo<Target> {
378 protected:
379   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
380                     MacroBuilder &Builder) const override {
381     // NetBSD defines; list based off of gcc output
382     Builder.defineMacro("__NetBSD__");
383     Builder.defineMacro("__unix__");
384     Builder.defineMacro("__ELF__");
385     if (Opts.POSIXThreads)
386       Builder.defineMacro("_POSIX_THREADS");
387 
388     switch (Triple.getArch()) {
389     default:
390       break;
391     case llvm::Triple::arm:
392     case llvm::Triple::armeb:
393     case llvm::Triple::thumb:
394     case llvm::Triple::thumbeb:
395       Builder.defineMacro("__ARM_DWARF_EH__");
396       break;
397     }
398   }
399 public:
400   NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
401     this->UserLabelPrefix = "";
402   }
403 };
404 
405 // OpenBSD Target
406 template<typename Target>
407 class OpenBSDTargetInfo : public OSTargetInfo<Target> {
408 protected:
409   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
410                     MacroBuilder &Builder) const override {
411     // OpenBSD defines; list based off of gcc output
412 
413     Builder.defineMacro("__OpenBSD__");
414     DefineStd(Builder, "unix", Opts);
415     Builder.defineMacro("__ELF__");
416     if (Opts.POSIXThreads)
417       Builder.defineMacro("_REENTRANT");
418   }
419 public:
420   OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
421     this->UserLabelPrefix = "";
422     this->TLSSupported = false;
423 
424       switch (Triple.getArch()) {
425         default:
426         case llvm::Triple::x86:
427         case llvm::Triple::x86_64:
428         case llvm::Triple::arm:
429         case llvm::Triple::sparc:
430           this->MCountName = "__mcount";
431           break;
432         case llvm::Triple::mips64:
433         case llvm::Triple::mips64el:
434         case llvm::Triple::ppc:
435         case llvm::Triple::sparcv9:
436           this->MCountName = "_mcount";
437           break;
438       }
439   }
440 };
441 
442 // Bitrig Target
443 template<typename Target>
444 class BitrigTargetInfo : public OSTargetInfo<Target> {
445 protected:
446   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
447                     MacroBuilder &Builder) const override {
448     // Bitrig defines; list based off of gcc output
449 
450     Builder.defineMacro("__Bitrig__");
451     DefineStd(Builder, "unix", Opts);
452     Builder.defineMacro("__ELF__");
453     if (Opts.POSIXThreads)
454       Builder.defineMacro("_REENTRANT");
455   }
456 public:
457   BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
458     this->UserLabelPrefix = "";
459     this->MCountName = "__mcount";
460   }
461 };
462 
463 // PSP Target
464 template<typename Target>
465 class PSPTargetInfo : public OSTargetInfo<Target> {
466 protected:
467   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
468                     MacroBuilder &Builder) const override {
469     // PSP defines; list based on the output of the pspdev gcc toolchain.
470     Builder.defineMacro("PSP");
471     Builder.defineMacro("_PSP");
472     Builder.defineMacro("__psp__");
473     Builder.defineMacro("__ELF__");
474   }
475 public:
476   PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
477     this->UserLabelPrefix = "";
478   }
479 };
480 
481 // PS3 PPU Target
482 template<typename Target>
483 class PS3PPUTargetInfo : public OSTargetInfo<Target> {
484 protected:
485   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
486                     MacroBuilder &Builder) const override {
487     // PS3 PPU defines.
488     Builder.defineMacro("__PPC__");
489     Builder.defineMacro("__PPU__");
490     Builder.defineMacro("__CELLOS_LV2__");
491     Builder.defineMacro("__ELF__");
492     Builder.defineMacro("__LP32__");
493     Builder.defineMacro("_ARCH_PPC64");
494     Builder.defineMacro("__powerpc64__");
495   }
496 public:
497   PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
498     this->UserLabelPrefix = "";
499     this->LongWidth = this->LongAlign = 32;
500     this->PointerWidth = this->PointerAlign = 32;
501     this->IntMaxType = TargetInfo::SignedLongLong;
502     this->Int64Type = TargetInfo::SignedLongLong;
503     this->SizeType = TargetInfo::UnsignedInt;
504     this->DescriptionString = "E-m:e-p:32:32-i64:64-n32:64";
505   }
506 };
507 
508 // AuroraUX target
509 template<typename Target>
510 class AuroraUXTargetInfo : public OSTargetInfo<Target> {
511 protected:
512   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
513                     MacroBuilder &Builder) const override {
514     DefineStd(Builder, "sun", Opts);
515     DefineStd(Builder, "unix", Opts);
516     Builder.defineMacro("__ELF__");
517     Builder.defineMacro("__svr4__");
518     Builder.defineMacro("__SVR4");
519   }
520 public:
521   AuroraUXTargetInfo(const llvm::Triple &Triple)
522       : OSTargetInfo<Target>(Triple) {
523     this->UserLabelPrefix = "";
524     this->WCharType = this->SignedLong;
525     // FIXME: WIntType should be SignedLong
526   }
527 };
528 
529 // Solaris target
530 template<typename Target>
531 class SolarisTargetInfo : public OSTargetInfo<Target> {
532 protected:
533   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
534                     MacroBuilder &Builder) const override {
535     DefineStd(Builder, "sun", Opts);
536     DefineStd(Builder, "unix", Opts);
537     Builder.defineMacro("__ELF__");
538     Builder.defineMacro("__svr4__");
539     Builder.defineMacro("__SVR4");
540     // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and
541     // newer, but to 500 for everything else.  feature_test.h has a check to
542     // ensure that you are not using C99 with an old version of X/Open or C89
543     // with a new version.
544     if (Opts.C99 || Opts.C11)
545       Builder.defineMacro("_XOPEN_SOURCE", "600");
546     else
547       Builder.defineMacro("_XOPEN_SOURCE", "500");
548     if (Opts.CPlusPlus)
549       Builder.defineMacro("__C99FEATURES__");
550     Builder.defineMacro("_LARGEFILE_SOURCE");
551     Builder.defineMacro("_LARGEFILE64_SOURCE");
552     Builder.defineMacro("__EXTENSIONS__");
553     Builder.defineMacro("_REENTRANT");
554   }
555 public:
556   SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
557     this->UserLabelPrefix = "";
558     this->WCharType = this->SignedInt;
559     // FIXME: WIntType should be SignedLong
560   }
561 };
562 
563 // Windows target
564 template<typename Target>
565 class WindowsTargetInfo : public OSTargetInfo<Target> {
566 protected:
567   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
568                     MacroBuilder &Builder) const override {
569     Builder.defineMacro("_WIN32");
570   }
571   void getVisualStudioDefines(const LangOptions &Opts,
572                               MacroBuilder &Builder) const {
573     if (Opts.CPlusPlus) {
574       if (Opts.RTTIData)
575         Builder.defineMacro("_CPPRTTI");
576 
577       if (Opts.Exceptions)
578         Builder.defineMacro("_CPPUNWIND");
579     }
580 
581     if (!Opts.CharIsSigned)
582       Builder.defineMacro("_CHAR_UNSIGNED");
583 
584     // FIXME: POSIXThreads isn't exactly the option this should be defined for,
585     //        but it works for now.
586     if (Opts.POSIXThreads)
587       Builder.defineMacro("_MT");
588 
589     if (Opts.MSCompatibilityVersion) {
590       Builder.defineMacro("_MSC_VER",
591                           Twine(Opts.MSCompatibilityVersion / 100000));
592       Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion));
593       // FIXME We cannot encode the revision information into 32-bits
594       Builder.defineMacro("_MSC_BUILD", Twine(1));
595     }
596 
597     if (Opts.MicrosoftExt) {
598       Builder.defineMacro("_MSC_EXTENSIONS");
599 
600       if (Opts.CPlusPlus11) {
601         Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED");
602         Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED");
603         Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED");
604       }
605     }
606 
607     Builder.defineMacro("_INTEGRAL_MAX_BITS", "64");
608   }
609 
610 public:
611   WindowsTargetInfo(const llvm::Triple &Triple)
612       : OSTargetInfo<Target>(Triple) {}
613 };
614 
615 template <typename Target>
616 class NaClTargetInfo : public OSTargetInfo<Target> {
617 protected:
618   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
619                     MacroBuilder &Builder) const override {
620     if (Opts.POSIXThreads)
621       Builder.defineMacro("_REENTRANT");
622     if (Opts.CPlusPlus)
623       Builder.defineMacro("_GNU_SOURCE");
624 
625     DefineStd(Builder, "unix", Opts);
626     Builder.defineMacro("__ELF__");
627     Builder.defineMacro("__native_client__");
628   }
629 
630 public:
631   NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
632     this->UserLabelPrefix = "";
633     this->LongAlign = 32;
634     this->LongWidth = 32;
635     this->PointerAlign = 32;
636     this->PointerWidth = 32;
637     this->IntMaxType = TargetInfo::SignedLongLong;
638     this->Int64Type = TargetInfo::SignedLongLong;
639     this->DoubleAlign = 64;
640     this->LongDoubleWidth = 64;
641     this->LongDoubleAlign = 64;
642     this->LongLongWidth = 64;
643     this->LongLongAlign = 64;
644     this->SizeType = TargetInfo::UnsignedInt;
645     this->PtrDiffType = TargetInfo::SignedInt;
646     this->IntPtrType = TargetInfo::SignedInt;
647     // RegParmMax is inherited from the underlying architecture
648     this->LongDoubleFormat = &llvm::APFloat::IEEEdouble;
649     if (Triple.getArch() == llvm::Triple::arm) {
650       this->DescriptionString = "e-m:e-p:32:32-i64:64-v128:64:128-n32-S128";
651     } else if (Triple.getArch() == llvm::Triple::x86) {
652       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32-S128";
653     } else if (Triple.getArch() == llvm::Triple::x86_64) {
654       this->DescriptionString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128";
655     } else if (Triple.getArch() == llvm::Triple::mipsel) {
656       // Handled on mips' setDescriptionString.
657     } else {
658       assert(Triple.getArch() == llvm::Triple::le32);
659       this->DescriptionString = "e-p:32:32-i64:64";
660     }
661   }
662   typename Target::CallingConvCheckResult checkCallingConvention(
663       CallingConv CC) const override {
664     return CC == CC_PnaclCall ? Target::CCCR_OK :
665         Target::checkCallingConvention(CC);
666   }
667 };
668 } // end anonymous namespace.
669 
670 //===----------------------------------------------------------------------===//
671 // Specific target implementations.
672 //===----------------------------------------------------------------------===//
673 
674 namespace {
675 // PPC abstract base class
676 class PPCTargetInfo : public TargetInfo {
677   static const Builtin::Info BuiltinInfo[];
678   static const char * const GCCRegNames[];
679   static const TargetInfo::GCCRegAlias GCCRegAliases[];
680   std::string CPU;
681 
682   // Target cpu features.
683   bool HasVSX;
684 
685 public:
686   PPCTargetInfo(const llvm::Triple &Triple)
687       : TargetInfo(Triple), HasVSX(false) {
688     BigEndian = (Triple.getArch() != llvm::Triple::ppc64le);
689     LongDoubleWidth = LongDoubleAlign = 128;
690     LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble;
691   }
692 
693   /// \brief Flags for architecture specific defines.
694   typedef enum {
695     ArchDefineNone  = 0,
696     ArchDefineName  = 1 << 0, // <name> is substituted for arch name.
697     ArchDefinePpcgr = 1 << 1,
698     ArchDefinePpcsq = 1 << 2,
699     ArchDefine440   = 1 << 3,
700     ArchDefine603   = 1 << 4,
701     ArchDefine604   = 1 << 5,
702     ArchDefinePwr4  = 1 << 6,
703     ArchDefinePwr5  = 1 << 7,
704     ArchDefinePwr5x = 1 << 8,
705     ArchDefinePwr6  = 1 << 9,
706     ArchDefinePwr6x = 1 << 10,
707     ArchDefinePwr7  = 1 << 11,
708     ArchDefinePwr8  = 1 << 12,
709     ArchDefineA2    = 1 << 13,
710     ArchDefineA2q   = 1 << 14
711   } ArchDefineTypes;
712 
713   // Note: GCC recognizes the following additional cpus:
714   //  401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801,
715   //  821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell,
716   //  titan, rs64.
717   bool setCPU(const std::string &Name) override {
718     bool CPUKnown = llvm::StringSwitch<bool>(Name)
719       .Case("generic", true)
720       .Case("440", true)
721       .Case("450", true)
722       .Case("601", true)
723       .Case("602", true)
724       .Case("603", true)
725       .Case("603e", true)
726       .Case("603ev", true)
727       .Case("604", true)
728       .Case("604e", true)
729       .Case("620", true)
730       .Case("630", true)
731       .Case("g3", true)
732       .Case("7400", true)
733       .Case("g4", true)
734       .Case("7450", true)
735       .Case("g4+", true)
736       .Case("750", true)
737       .Case("970", true)
738       .Case("g5", true)
739       .Case("a2", true)
740       .Case("a2q", true)
741       .Case("e500mc", true)
742       .Case("e5500", true)
743       .Case("power3", true)
744       .Case("pwr3", true)
745       .Case("power4", true)
746       .Case("pwr4", true)
747       .Case("power5", true)
748       .Case("pwr5", true)
749       .Case("power5x", true)
750       .Case("pwr5x", true)
751       .Case("power6", true)
752       .Case("pwr6", true)
753       .Case("power6x", true)
754       .Case("pwr6x", true)
755       .Case("power7", true)
756       .Case("pwr7", true)
757       .Case("power8", true)
758       .Case("pwr8", true)
759       .Case("powerpc", true)
760       .Case("ppc", true)
761       .Case("powerpc64", true)
762       .Case("ppc64", true)
763       .Case("powerpc64le", true)
764       .Case("ppc64le", true)
765       .Default(false);
766 
767     if (CPUKnown)
768       CPU = Name;
769 
770     return CPUKnown;
771   }
772 
773   void getTargetBuiltins(const Builtin::Info *&Records,
774                          unsigned &NumRecords) const override {
775     Records = BuiltinInfo;
776     NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin;
777   }
778 
779   bool isCLZForZeroUndef() const override { return false; }
780 
781   void getTargetDefines(const LangOptions &Opts,
782                         MacroBuilder &Builder) const override;
783 
784   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
785 
786   bool handleTargetFeatures(std::vector<std::string> &Features,
787                             DiagnosticsEngine &Diags) override;
788   bool hasFeature(StringRef Feature) const override;
789 
790   void getGCCRegNames(const char * const *&Names,
791                       unsigned &NumNames) const override;
792   void getGCCRegAliases(const GCCRegAlias *&Aliases,
793                         unsigned &NumAliases) const override;
794   bool validateAsmConstraint(const char *&Name,
795                              TargetInfo::ConstraintInfo &Info) const override {
796     switch (*Name) {
797     default: return false;
798     case 'O': // Zero
799       break;
800     case 'b': // Base register
801     case 'f': // Floating point register
802       Info.setAllowsRegister();
803       break;
804     // FIXME: The following are added to allow parsing.
805     // I just took a guess at what the actions should be.
806     // Also, is more specific checking needed?  I.e. specific registers?
807     case 'd': // Floating point register (containing 64-bit value)
808     case 'v': // Altivec vector register
809       Info.setAllowsRegister();
810       break;
811     case 'w':
812       switch (Name[1]) {
813         case 'd':// VSX vector register to hold vector double data
814         case 'f':// VSX vector register to hold vector float data
815         case 's':// VSX vector register to hold scalar float data
816         case 'a':// Any VSX register
817         case 'c':// An individual CR bit
818           break;
819         default:
820           return false;
821       }
822       Info.setAllowsRegister();
823       Name++; // Skip over 'w'.
824       break;
825     case 'h': // `MQ', `CTR', or `LINK' register
826     case 'q': // `MQ' register
827     case 'c': // `CTR' register
828     case 'l': // `LINK' register
829     case 'x': // `CR' register (condition register) number 0
830     case 'y': // `CR' register (condition register)
831     case 'z': // `XER[CA]' carry bit (part of the XER register)
832       Info.setAllowsRegister();
833       break;
834     case 'I': // Signed 16-bit constant
835     case 'J': // Unsigned 16-bit constant shifted left 16 bits
836               //  (use `L' instead for SImode constants)
837     case 'K': // Unsigned 16-bit constant
838     case 'L': // Signed 16-bit constant shifted left 16 bits
839     case 'M': // Constant larger than 31
840     case 'N': // Exact power of 2
841     case 'P': // Constant whose negation is a signed 16-bit constant
842     case 'G': // Floating point constant that can be loaded into a
843               // register with one instruction per word
844     case 'H': // Integer/Floating point constant that can be loaded
845               // into a register using three instructions
846       break;
847     case 'm': // Memory operand. Note that on PowerPC targets, m can
848               // include addresses that update the base register. It
849               // is therefore only safe to use `m' in an asm statement
850               // if that asm statement accesses the operand exactly once.
851               // The asm statement must also use `%U<opno>' as a
852               // placeholder for the "update" flag in the corresponding
853               // load or store instruction. For example:
854               // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val));
855               // is correct but:
856               // asm ("st %1,%0" : "=m" (mem) : "r" (val));
857               // is not. Use es rather than m if you don't want the base
858               // register to be updated.
859     case 'e':
860       if (Name[1] != 's')
861           return false;
862               // es: A "stable" memory operand; that is, one which does not
863               // include any automodification of the base register. Unlike
864               // `m', this constraint can be used in asm statements that
865               // might access the operand several times, or that might not
866               // access it at all.
867       Info.setAllowsMemory();
868       Name++; // Skip over 'e'.
869       break;
870     case 'Q': // Memory operand that is an offset from a register (it is
871               // usually better to use `m' or `es' in asm statements)
872     case 'Z': // Memory operand that is an indexed or indirect from a
873               // register (it is usually better to use `m' or `es' in
874               // asm statements)
875       Info.setAllowsMemory();
876       Info.setAllowsRegister();
877       break;
878     case 'R': // AIX TOC entry
879     case 'a': // Address operand that is an indexed or indirect from a
880               // register (`p' is preferable for asm statements)
881     case 'S': // Constant suitable as a 64-bit mask operand
882     case 'T': // Constant suitable as a 32-bit mask operand
883     case 'U': // System V Release 4 small data area reference
884     case 't': // AND masks that can be performed by two rldic{l, r}
885               // instructions
886     case 'W': // Vector constant that does not require memory
887     case 'j': // Vector constant that is all zeros.
888       break;
889     // End FIXME.
890     }
891     return true;
892   }
893   std::string convertConstraint(const char *&Constraint) const override {
894     std::string R;
895     switch (*Constraint) {
896     case 'e':
897     case 'w':
898       // Two-character constraint; add "^" hint for later parsing.
899       R = std::string("^") + std::string(Constraint, 2);
900       Constraint++;
901       break;
902     default:
903       return TargetInfo::convertConstraint(Constraint);
904     }
905     return R;
906   }
907   const char *getClobbers() const override {
908     return "";
909   }
910   int getEHDataRegisterNumber(unsigned RegNo) const override {
911     if (RegNo == 0) return 3;
912     if (RegNo == 1) return 4;
913     return -1;
914   }
915 };
916 
917 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = {
918 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
919 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
920                                               ALL_LANGUAGES },
921 #include "clang/Basic/BuiltinsPPC.def"
922 };
923 
924   /// handleTargetFeatures - Perform initialization based on the user
925 /// configured set of features.
926 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
927                                          DiagnosticsEngine &Diags) {
928   // Remember the maximum enabled sselevel.
929   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
930     // Ignore disabled features.
931     if (Features[i][0] == '-')
932       continue;
933 
934     StringRef Feature = StringRef(Features[i]).substr(1);
935 
936     if (Feature == "vsx") {
937       HasVSX = true;
938       continue;
939     }
940 
941     // TODO: Finish this list and add an assert that we've handled them
942     // all.
943   }
944 
945   return true;
946 }
947 
948 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific
949 /// #defines that are not tied to a specific subtarget.
950 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
951                                      MacroBuilder &Builder) const {
952   // Target identification.
953   Builder.defineMacro("__ppc__");
954   Builder.defineMacro("__PPC__");
955   Builder.defineMacro("_ARCH_PPC");
956   Builder.defineMacro("__powerpc__");
957   Builder.defineMacro("__POWERPC__");
958   if (PointerWidth == 64) {
959     Builder.defineMacro("_ARCH_PPC64");
960     Builder.defineMacro("__powerpc64__");
961     Builder.defineMacro("__ppc64__");
962     Builder.defineMacro("__PPC64__");
963   }
964 
965   // Target properties.
966   if (getTriple().getArch() == llvm::Triple::ppc64le) {
967     Builder.defineMacro("_LITTLE_ENDIAN");
968     Builder.defineMacro("_CALL_ELF","2");
969   } else {
970     if (getTriple().getOS() != llvm::Triple::NetBSD &&
971         getTriple().getOS() != llvm::Triple::OpenBSD)
972       Builder.defineMacro("_BIG_ENDIAN");
973   }
974 
975   // Subtarget options.
976   Builder.defineMacro("__NATURAL_ALIGNMENT__");
977   Builder.defineMacro("__REGISTER_PREFIX__", "");
978 
979   // FIXME: Should be controlled by command line option.
980   if (LongDoubleWidth == 128)
981     Builder.defineMacro("__LONG_DOUBLE_128__");
982 
983   if (Opts.AltiVec) {
984     Builder.defineMacro("__VEC__", "10206");
985     Builder.defineMacro("__ALTIVEC__");
986   }
987 
988   // CPU identification.
989   ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU)
990     .Case("440",   ArchDefineName)
991     .Case("450",   ArchDefineName | ArchDefine440)
992     .Case("601",   ArchDefineName)
993     .Case("602",   ArchDefineName | ArchDefinePpcgr)
994     .Case("603",   ArchDefineName | ArchDefinePpcgr)
995     .Case("603e",  ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
996     .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr)
997     .Case("604",   ArchDefineName | ArchDefinePpcgr)
998     .Case("604e",  ArchDefineName | ArchDefine604 | ArchDefinePpcgr)
999     .Case("620",   ArchDefineName | ArchDefinePpcgr)
1000     .Case("630",   ArchDefineName | ArchDefinePpcgr)
1001     .Case("7400",  ArchDefineName | ArchDefinePpcgr)
1002     .Case("7450",  ArchDefineName | ArchDefinePpcgr)
1003     .Case("750",   ArchDefineName | ArchDefinePpcgr)
1004     .Case("970",   ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1005                      | ArchDefinePpcsq)
1006     .Case("a2",    ArchDefineA2)
1007     .Case("a2q",   ArchDefineName | ArchDefineA2 | ArchDefineA2q)
1008     .Case("pwr3",  ArchDefinePpcgr)
1009     .Case("pwr4",  ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq)
1010     .Case("pwr5",  ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr
1011                      | ArchDefinePpcsq)
1012     .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4
1013                      | ArchDefinePpcgr | ArchDefinePpcsq)
1014     .Case("pwr6",  ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5
1015                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1016     .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x
1017                      | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1018                      | ArchDefinePpcsq)
1019     .Case("pwr7",  ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6
1020                      | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1021                      | ArchDefinePpcgr | ArchDefinePpcsq)
1022     .Case("pwr8",  ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x
1023                      | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1024                      | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1025     .Case("power3",  ArchDefinePpcgr)
1026     .Case("power4",  ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1027     .Case("power5",  ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1028                        | ArchDefinePpcsq)
1029     .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1030                        | ArchDefinePpcgr | ArchDefinePpcsq)
1031     .Case("power6",  ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1032                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1033     .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x
1034                        | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr
1035                        | ArchDefinePpcsq)
1036     .Case("power7",  ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6
1037                        | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4
1038                        | ArchDefinePpcgr | ArchDefinePpcsq)
1039     .Case("power8",  ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x
1040                        | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5
1041                        | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
1042     .Default(ArchDefineNone);
1043 
1044   if (defs & ArchDefineName)
1045     Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper()));
1046   if (defs & ArchDefinePpcgr)
1047     Builder.defineMacro("_ARCH_PPCGR");
1048   if (defs & ArchDefinePpcsq)
1049     Builder.defineMacro("_ARCH_PPCSQ");
1050   if (defs & ArchDefine440)
1051     Builder.defineMacro("_ARCH_440");
1052   if (defs & ArchDefine603)
1053     Builder.defineMacro("_ARCH_603");
1054   if (defs & ArchDefine604)
1055     Builder.defineMacro("_ARCH_604");
1056   if (defs & ArchDefinePwr4)
1057     Builder.defineMacro("_ARCH_PWR4");
1058   if (defs & ArchDefinePwr5)
1059     Builder.defineMacro("_ARCH_PWR5");
1060   if (defs & ArchDefinePwr5x)
1061     Builder.defineMacro("_ARCH_PWR5X");
1062   if (defs & ArchDefinePwr6)
1063     Builder.defineMacro("_ARCH_PWR6");
1064   if (defs & ArchDefinePwr6x)
1065     Builder.defineMacro("_ARCH_PWR6X");
1066   if (defs & ArchDefinePwr7)
1067     Builder.defineMacro("_ARCH_PWR7");
1068   if (defs & ArchDefinePwr8)
1069     Builder.defineMacro("_ARCH_PWR8");
1070   if (defs & ArchDefineA2)
1071     Builder.defineMacro("_ARCH_A2");
1072   if (defs & ArchDefineA2q) {
1073     Builder.defineMacro("_ARCH_A2Q");
1074     Builder.defineMacro("_ARCH_QP");
1075   }
1076 
1077   if (getTriple().getVendor() == llvm::Triple::BGQ) {
1078     Builder.defineMacro("__bg__");
1079     Builder.defineMacro("__THW_BLUEGENE__");
1080     Builder.defineMacro("__bgq__");
1081     Builder.defineMacro("__TOS_BGQ__");
1082   }
1083 
1084   if (HasVSX)
1085     Builder.defineMacro("__VSX__");
1086 
1087   // FIXME: The following are not yet generated here by Clang, but are
1088   //        generated by GCC:
1089   //
1090   //   _SOFT_FLOAT_
1091   //   __RECIP_PRECISION__
1092   //   __APPLE_ALTIVEC__
1093   //   __RECIP__
1094   //   __RECIPF__
1095   //   __RSQRTE__
1096   //   __RSQRTEF__
1097   //   _SOFT_DOUBLE_
1098   //   __NO_LWSYNC__
1099   //   __HAVE_BSWAP__
1100   //   __LONGDOUBLE128
1101   //   __CMODEL_MEDIUM__
1102   //   __CMODEL_LARGE__
1103   //   _CALL_SYSV
1104   //   _CALL_DARWIN
1105   //   __NO_FPRS__
1106 }
1107 
1108 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
1109   Features["altivec"] = llvm::StringSwitch<bool>(CPU)
1110     .Case("7400", true)
1111     .Case("g4", true)
1112     .Case("7450", true)
1113     .Case("g4+", true)
1114     .Case("970", true)
1115     .Case("g5", true)
1116     .Case("pwr6", true)
1117     .Case("pwr7", true)
1118     .Case("pwr8", true)
1119     .Case("ppc64", true)
1120     .Case("ppc64le", true)
1121     .Default(false);
1122 
1123   Features["qpx"] = (CPU == "a2q");
1124 }
1125 
1126 bool PPCTargetInfo::hasFeature(StringRef Feature) const {
1127   return Feature == "powerpc";
1128 }
1129 
1130 
1131 const char * const PPCTargetInfo::GCCRegNames[] = {
1132   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
1133   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1134   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
1135   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
1136   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
1137   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
1138   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
1139   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
1140   "mq", "lr", "ctr", "ap",
1141   "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7",
1142   "xer",
1143   "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
1144   "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
1145   "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
1146   "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31",
1147   "vrsave", "vscr",
1148   "spe_acc", "spefscr",
1149   "sfp"
1150 };
1151 
1152 void PPCTargetInfo::getGCCRegNames(const char * const *&Names,
1153                                    unsigned &NumNames) const {
1154   Names = GCCRegNames;
1155   NumNames = llvm::array_lengthof(GCCRegNames);
1156 }
1157 
1158 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = {
1159   // While some of these aliases do map to different registers
1160   // they still share the same register name.
1161   { { "0" }, "r0" },
1162   { { "1"}, "r1" },
1163   { { "2" }, "r2" },
1164   { { "3" }, "r3" },
1165   { { "4" }, "r4" },
1166   { { "5" }, "r5" },
1167   { { "6" }, "r6" },
1168   { { "7" }, "r7" },
1169   { { "8" }, "r8" },
1170   { { "9" }, "r9" },
1171   { { "10" }, "r10" },
1172   { { "11" }, "r11" },
1173   { { "12" }, "r12" },
1174   { { "13" }, "r13" },
1175   { { "14" }, "r14" },
1176   { { "15" }, "r15" },
1177   { { "16" }, "r16" },
1178   { { "17" }, "r17" },
1179   { { "18" }, "r18" },
1180   { { "19" }, "r19" },
1181   { { "20" }, "r20" },
1182   { { "21" }, "r21" },
1183   { { "22" }, "r22" },
1184   { { "23" }, "r23" },
1185   { { "24" }, "r24" },
1186   { { "25" }, "r25" },
1187   { { "26" }, "r26" },
1188   { { "27" }, "r27" },
1189   { { "28" }, "r28" },
1190   { { "29" }, "r29" },
1191   { { "30" }, "r30" },
1192   { { "31" }, "r31" },
1193   { { "fr0" }, "f0" },
1194   { { "fr1" }, "f1" },
1195   { { "fr2" }, "f2" },
1196   { { "fr3" }, "f3" },
1197   { { "fr4" }, "f4" },
1198   { { "fr5" }, "f5" },
1199   { { "fr6" }, "f6" },
1200   { { "fr7" }, "f7" },
1201   { { "fr8" }, "f8" },
1202   { { "fr9" }, "f9" },
1203   { { "fr10" }, "f10" },
1204   { { "fr11" }, "f11" },
1205   { { "fr12" }, "f12" },
1206   { { "fr13" }, "f13" },
1207   { { "fr14" }, "f14" },
1208   { { "fr15" }, "f15" },
1209   { { "fr16" }, "f16" },
1210   { { "fr17" }, "f17" },
1211   { { "fr18" }, "f18" },
1212   { { "fr19" }, "f19" },
1213   { { "fr20" }, "f20" },
1214   { { "fr21" }, "f21" },
1215   { { "fr22" }, "f22" },
1216   { { "fr23" }, "f23" },
1217   { { "fr24" }, "f24" },
1218   { { "fr25" }, "f25" },
1219   { { "fr26" }, "f26" },
1220   { { "fr27" }, "f27" },
1221   { { "fr28" }, "f28" },
1222   { { "fr29" }, "f29" },
1223   { { "fr30" }, "f30" },
1224   { { "fr31" }, "f31" },
1225   { { "cc" }, "cr0" },
1226 };
1227 
1228 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
1229                                      unsigned &NumAliases) const {
1230   Aliases = GCCRegAliases;
1231   NumAliases = llvm::array_lengthof(GCCRegAliases);
1232 }
1233 } // end anonymous namespace.
1234 
1235 namespace {
1236 class PPC32TargetInfo : public PPCTargetInfo {
1237 public:
1238   PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1239     DescriptionString = "E-m:e-p:32:32-i64:64-n32";
1240 
1241     switch (getTriple().getOS()) {
1242     case llvm::Triple::Linux:
1243     case llvm::Triple::FreeBSD:
1244     case llvm::Triple::NetBSD:
1245       SizeType = UnsignedInt;
1246       PtrDiffType = SignedInt;
1247       IntPtrType = SignedInt;
1248       break;
1249     default:
1250       break;
1251     }
1252 
1253     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1254       LongDoubleWidth = LongDoubleAlign = 64;
1255       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1256     }
1257 
1258     // PPC32 supports atomics up to 4 bytes.
1259     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
1260   }
1261 
1262   BuiltinVaListKind getBuiltinVaListKind() const override {
1263     // This is the ELF definition, and is overridden by the Darwin sub-target
1264     return TargetInfo::PowerABIBuiltinVaList;
1265   }
1266 };
1267 } // end anonymous namespace.
1268 
1269 // Note: ABI differences may eventually require us to have a separate
1270 // TargetInfo for little endian.
1271 namespace {
1272 class PPC64TargetInfo : public PPCTargetInfo {
1273 public:
1274   PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) {
1275     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
1276     IntMaxType = SignedLong;
1277     Int64Type = SignedLong;
1278 
1279     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
1280       LongDoubleWidth = LongDoubleAlign = 64;
1281       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
1282       DescriptionString = "E-m:e-i64:64-n32:64";
1283     } else {
1284       if ((Triple.getArch() == llvm::Triple::ppc64le)) {
1285         DescriptionString = "e-m:e-i64:64-n32:64";
1286       } else {
1287         DescriptionString = "E-m:e-i64:64-n32:64";
1288       }
1289 }
1290 
1291     // PPC64 supports atomics up to 8 bytes.
1292     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
1293   }
1294   BuiltinVaListKind getBuiltinVaListKind() const override {
1295     return TargetInfo::CharPtrBuiltinVaList;
1296   }
1297 };
1298 } // end anonymous namespace.
1299 
1300 
1301 namespace {
1302 class DarwinPPC32TargetInfo :
1303   public DarwinTargetInfo<PPC32TargetInfo> {
1304 public:
1305   DarwinPPC32TargetInfo(const llvm::Triple &Triple)
1306       : DarwinTargetInfo<PPC32TargetInfo>(Triple) {
1307     HasAlignMac68kSupport = true;
1308     BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool?
1309     PtrDiffType = SignedInt;    // for http://llvm.org/bugs/show_bug.cgi?id=15726
1310     LongLongAlign = 32;
1311     SuitableAlign = 128;
1312     DescriptionString = "E-m:o-p:32:32-f64:32:64-n32";
1313   }
1314   BuiltinVaListKind getBuiltinVaListKind() const override {
1315     return TargetInfo::CharPtrBuiltinVaList;
1316   }
1317 };
1318 
1319 class DarwinPPC64TargetInfo :
1320   public DarwinTargetInfo<PPC64TargetInfo> {
1321 public:
1322   DarwinPPC64TargetInfo(const llvm::Triple &Triple)
1323       : DarwinTargetInfo<PPC64TargetInfo>(Triple) {
1324     HasAlignMac68kSupport = true;
1325     SuitableAlign = 128;
1326     DescriptionString = "E-m:o-i64:64-n32:64";
1327   }
1328 };
1329 } // end anonymous namespace.
1330 
1331 namespace {
1332   static const unsigned NVPTXAddrSpaceMap[] = {
1333     1,    // opencl_global
1334     3,    // opencl_local
1335     4,    // opencl_constant
1336     1,    // cuda_device
1337     4,    // cuda_constant
1338     3,    // cuda_shared
1339   };
1340   class NVPTXTargetInfo : public TargetInfo {
1341     static const char * const GCCRegNames[];
1342     static const Builtin::Info BuiltinInfo[];
1343   public:
1344     NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
1345       BigEndian = false;
1346       TLSSupported = false;
1347       LongWidth = LongAlign = 64;
1348       AddrSpaceMap = &NVPTXAddrSpaceMap;
1349       UseAddrSpaceMapMangling = true;
1350       // Define available target features
1351       // These must be defined in sorted order!
1352       NoAsmVariants = true;
1353     }
1354     void getTargetDefines(const LangOptions &Opts,
1355                           MacroBuilder &Builder) const override {
1356       Builder.defineMacro("__PTX__");
1357       Builder.defineMacro("__NVPTX__");
1358     }
1359     void getTargetBuiltins(const Builtin::Info *&Records,
1360                            unsigned &NumRecords) const override {
1361       Records = BuiltinInfo;
1362       NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin;
1363     }
1364     bool hasFeature(StringRef Feature) const override {
1365       return Feature == "ptx" || Feature == "nvptx";
1366     }
1367 
1368     void getGCCRegNames(const char * const *&Names,
1369                         unsigned &NumNames) const override;
1370     void getGCCRegAliases(const GCCRegAlias *&Aliases,
1371                                   unsigned &NumAliases) const override {
1372       // No aliases.
1373       Aliases = nullptr;
1374       NumAliases = 0;
1375     }
1376     bool validateAsmConstraint(const char *&Name,
1377                                TargetInfo::ConstraintInfo &Info) const override {
1378       switch (*Name) {
1379       default: return false;
1380       case 'c':
1381       case 'h':
1382       case 'r':
1383       case 'l':
1384       case 'f':
1385       case 'd':
1386         Info.setAllowsRegister();
1387         return true;
1388       }
1389     }
1390     const char *getClobbers() const override {
1391       // FIXME: Is this really right?
1392       return "";
1393     }
1394     BuiltinVaListKind getBuiltinVaListKind() const override {
1395       // FIXME: implement
1396       return TargetInfo::CharPtrBuiltinVaList;
1397     }
1398     bool setCPU(const std::string &Name) override {
1399       bool Valid = llvm::StringSwitch<bool>(Name)
1400         .Case("sm_20", true)
1401         .Case("sm_21", true)
1402         .Case("sm_30", true)
1403         .Case("sm_35", true)
1404         .Default(false);
1405 
1406       return Valid;
1407     }
1408   };
1409 
1410   const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = {
1411 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1412 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1413                                               ALL_LANGUAGES },
1414 #include "clang/Basic/BuiltinsNVPTX.def"
1415   };
1416 
1417   const char * const NVPTXTargetInfo::GCCRegNames[] = {
1418     "r0"
1419   };
1420 
1421   void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names,
1422                                      unsigned &NumNames) const {
1423     Names = GCCRegNames;
1424     NumNames = llvm::array_lengthof(GCCRegNames);
1425   }
1426 
1427   class NVPTX32TargetInfo : public NVPTXTargetInfo {
1428   public:
1429     NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1430       PointerWidth = PointerAlign = 32;
1431       SizeType     = PtrDiffType = TargetInfo::UnsignedInt;
1432       IntPtrType = TargetInfo::SignedInt;
1433       DescriptionString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64";
1434   }
1435   };
1436 
1437   class NVPTX64TargetInfo : public NVPTXTargetInfo {
1438   public:
1439     NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) {
1440       PointerWidth = PointerAlign = 64;
1441       SizeType     = PtrDiffType = TargetInfo::UnsignedLongLong;
1442       IntPtrType = TargetInfo::SignedLongLong;
1443       DescriptionString = "e-i64:64-v16:16-v32:32-n16:32:64";
1444   }
1445   };
1446 }
1447 
1448 namespace {
1449 
1450 static const unsigned R600AddrSpaceMap[] = {
1451   1,    // opencl_global
1452   3,    // opencl_local
1453   2,    // opencl_constant
1454   1,    // cuda_device
1455   2,    // cuda_constant
1456   3     // cuda_shared
1457 };
1458 
1459 static const char *DescriptionStringR600 =
1460   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1461   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1462 
1463 static const char *DescriptionStringR600DoubleOps =
1464   "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1465   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1466 
1467 static const char *DescriptionStringSI =
1468   "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64"
1469   "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
1470   "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
1471 
1472 class R600TargetInfo : public TargetInfo {
1473   static const Builtin::Info BuiltinInfo[];
1474 
1475   /// \brief The GPU profiles supported by the R600 target.
1476   enum GPUKind {
1477     GK_NONE,
1478     GK_R600,
1479     GK_R600_DOUBLE_OPS,
1480     GK_R700,
1481     GK_R700_DOUBLE_OPS,
1482     GK_EVERGREEN,
1483     GK_EVERGREEN_DOUBLE_OPS,
1484     GK_NORTHERN_ISLANDS,
1485     GK_CAYMAN,
1486     GK_SOUTHERN_ISLANDS,
1487     GK_SEA_ISLANDS
1488   } GPU;
1489 
1490 public:
1491   R600TargetInfo(const llvm::Triple &Triple)
1492       : TargetInfo(Triple), GPU(GK_R600) {
1493     DescriptionString = DescriptionStringR600;
1494     AddrSpaceMap = &R600AddrSpaceMap;
1495     UseAddrSpaceMapMangling = true;
1496   }
1497 
1498   const char * getClobbers() const override {
1499     return "";
1500   }
1501 
1502   void getGCCRegNames(const char * const *&Names,
1503                       unsigned &numNames) const override {
1504     Names = nullptr;
1505     numNames = 0;
1506   }
1507 
1508   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1509                         unsigned &NumAliases) const override {
1510     Aliases = nullptr;
1511     NumAliases = 0;
1512   }
1513 
1514   bool validateAsmConstraint(const char *&Name,
1515                              TargetInfo::ConstraintInfo &info) const override {
1516     return true;
1517   }
1518 
1519   void getTargetBuiltins(const Builtin::Info *&Records,
1520                          unsigned &NumRecords) const override {
1521     Records = BuiltinInfo;
1522     NumRecords = clang::R600::LastTSBuiltin - Builtin::FirstTSBuiltin;
1523   }
1524 
1525   void getTargetDefines(const LangOptions &Opts,
1526                         MacroBuilder &Builder) const override {
1527     Builder.defineMacro("__R600__");
1528   }
1529 
1530   BuiltinVaListKind getBuiltinVaListKind() const override {
1531     return TargetInfo::CharPtrBuiltinVaList;
1532   }
1533 
1534   bool setCPU(const std::string &Name) override {
1535     GPU = llvm::StringSwitch<GPUKind>(Name)
1536       .Case("r600" ,    GK_R600)
1537       .Case("rv610",    GK_R600)
1538       .Case("rv620",    GK_R600)
1539       .Case("rv630",    GK_R600)
1540       .Case("rv635",    GK_R600)
1541       .Case("rs780",    GK_R600)
1542       .Case("rs880",    GK_R600)
1543       .Case("rv670",    GK_R600_DOUBLE_OPS)
1544       .Case("rv710",    GK_R700)
1545       .Case("rv730",    GK_R700)
1546       .Case("rv740",    GK_R700_DOUBLE_OPS)
1547       .Case("rv770",    GK_R700_DOUBLE_OPS)
1548       .Case("palm",     GK_EVERGREEN)
1549       .Case("cedar",    GK_EVERGREEN)
1550       .Case("sumo",     GK_EVERGREEN)
1551       .Case("sumo2",    GK_EVERGREEN)
1552       .Case("redwood",  GK_EVERGREEN)
1553       .Case("juniper",  GK_EVERGREEN)
1554       .Case("hemlock",  GK_EVERGREEN_DOUBLE_OPS)
1555       .Case("cypress",  GK_EVERGREEN_DOUBLE_OPS)
1556       .Case("barts",    GK_NORTHERN_ISLANDS)
1557       .Case("turks",    GK_NORTHERN_ISLANDS)
1558       .Case("caicos",   GK_NORTHERN_ISLANDS)
1559       .Case("cayman",   GK_CAYMAN)
1560       .Case("aruba",    GK_CAYMAN)
1561       .Case("tahiti",   GK_SOUTHERN_ISLANDS)
1562       .Case("pitcairn", GK_SOUTHERN_ISLANDS)
1563       .Case("verde",    GK_SOUTHERN_ISLANDS)
1564       .Case("oland",    GK_SOUTHERN_ISLANDS)
1565       .Case("bonaire",  GK_SEA_ISLANDS)
1566       .Case("kabini",   GK_SEA_ISLANDS)
1567       .Case("kaveri",   GK_SEA_ISLANDS)
1568       .Case("hawaii",   GK_SEA_ISLANDS)
1569       .Default(GK_NONE);
1570 
1571     if (GPU == GK_NONE) {
1572       return false;
1573     }
1574 
1575     // Set the correct data layout
1576     switch (GPU) {
1577     case GK_NONE:
1578     case GK_R600:
1579     case GK_R700:
1580     case GK_EVERGREEN:
1581     case GK_NORTHERN_ISLANDS:
1582       DescriptionString = DescriptionStringR600;
1583       break;
1584     case GK_R600_DOUBLE_OPS:
1585     case GK_R700_DOUBLE_OPS:
1586     case GK_EVERGREEN_DOUBLE_OPS:
1587     case GK_CAYMAN:
1588       DescriptionString = DescriptionStringR600DoubleOps;
1589       break;
1590     case GK_SOUTHERN_ISLANDS:
1591     case GK_SEA_ISLANDS:
1592       DescriptionString = DescriptionStringSI;
1593       break;
1594     }
1595 
1596     return true;
1597   }
1598 };
1599 
1600 const Builtin::Info R600TargetInfo::BuiltinInfo[] = {
1601 #define BUILTIN(ID, TYPE, ATTRS)                \
1602   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1603 #include "clang/Basic/BuiltinsR600.def"
1604 };
1605 
1606 } // end anonymous namespace
1607 
1608 namespace {
1609 // Namespace for x86 abstract base class
1610 const Builtin::Info BuiltinInfo[] = {
1611 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
1612 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
1613                                               ALL_LANGUAGES },
1614 #include "clang/Basic/BuiltinsX86.def"
1615 };
1616 
1617 static const char* const GCCRegNames[] = {
1618   "ax", "dx", "cx", "bx", "si", "di", "bp", "sp",
1619   "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)",
1620   "argp", "flags", "fpcr", "fpsr", "dirflag", "frame",
1621   "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7",
1622   "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",
1623   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
1624   "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15",
1625   "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7",
1626   "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15",
1627 };
1628 
1629 const TargetInfo::AddlRegName AddlRegNames[] = {
1630   { { "al", "ah", "eax", "rax" }, 0 },
1631   { { "bl", "bh", "ebx", "rbx" }, 3 },
1632   { { "cl", "ch", "ecx", "rcx" }, 2 },
1633   { { "dl", "dh", "edx", "rdx" }, 1 },
1634   { { "esi", "rsi" }, 4 },
1635   { { "edi", "rdi" }, 5 },
1636   { { "esp", "rsp" }, 7 },
1637   { { "ebp", "rbp" }, 6 },
1638 };
1639 
1640 // X86 target abstract base class; x86-32 and x86-64 are very close, so
1641 // most of the implementation can be shared.
1642 class X86TargetInfo : public TargetInfo {
1643   enum X86SSEEnum {
1644     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
1645   } SSELevel;
1646   enum MMX3DNowEnum {
1647     NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon
1648   } MMX3DNowLevel;
1649   enum XOPEnum {
1650     NoXOP,
1651     SSE4A,
1652     FMA4,
1653     XOP
1654   } XOPLevel;
1655 
1656   bool HasAES;
1657   bool HasPCLMUL;
1658   bool HasLZCNT;
1659   bool HasRDRND;
1660   bool HasBMI;
1661   bool HasBMI2;
1662   bool HasPOPCNT;
1663   bool HasRTM;
1664   bool HasPRFCHW;
1665   bool HasRDSEED;
1666   bool HasTBM;
1667   bool HasFMA;
1668   bool HasF16C;
1669   bool HasAVX512CD, HasAVX512ER, HasAVX512PF;
1670   bool HasSHA;
1671   bool HasCX16;
1672 
1673   /// \brief Enumeration of all of the X86 CPUs supported by Clang.
1674   ///
1675   /// Each enumeration represents a particular CPU supported by Clang. These
1676   /// loosely correspond to the options passed to '-march' or '-mtune' flags.
1677   enum CPUKind {
1678     CK_Generic,
1679 
1680     /// \name i386
1681     /// i386-generation processors.
1682     //@{
1683     CK_i386,
1684     //@}
1685 
1686     /// \name i486
1687     /// i486-generation processors.
1688     //@{
1689     CK_i486,
1690     CK_WinChipC6,
1691     CK_WinChip2,
1692     CK_C3,
1693     //@}
1694 
1695     /// \name i586
1696     /// i586-generation processors, P5 microarchitecture based.
1697     //@{
1698     CK_i586,
1699     CK_Pentium,
1700     CK_PentiumMMX,
1701     //@}
1702 
1703     /// \name i686
1704     /// i686-generation processors, P6 / Pentium M microarchitecture based.
1705     //@{
1706     CK_i686,
1707     CK_PentiumPro,
1708     CK_Pentium2,
1709     CK_Pentium3,
1710     CK_Pentium3M,
1711     CK_PentiumM,
1712     CK_C3_2,
1713 
1714     /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah.
1715     /// Clang however has some logic to suport this.
1716     // FIXME: Warn, deprecate, and potentially remove this.
1717     CK_Yonah,
1718     //@}
1719 
1720     /// \name Netburst
1721     /// Netburst microarchitecture based processors.
1722     //@{
1723     CK_Pentium4,
1724     CK_Pentium4M,
1725     CK_Prescott,
1726     CK_Nocona,
1727     //@}
1728 
1729     /// \name Core
1730     /// Core microarchitecture based processors.
1731     //@{
1732     CK_Core2,
1733 
1734     /// This enumerator, like \see CK_Yonah, is a bit odd. It is another
1735     /// codename which GCC no longer accepts as an option to -march, but Clang
1736     /// has some logic for recognizing it.
1737     // FIXME: Warn, deprecate, and potentially remove this.
1738     CK_Penryn,
1739     //@}
1740 
1741     /// \name Atom
1742     /// Atom processors
1743     //@{
1744     CK_Atom,
1745     CK_Silvermont,
1746     //@}
1747 
1748     /// \name Nehalem
1749     /// Nehalem microarchitecture based processors.
1750     //@{
1751     CK_Corei7,
1752     CK_Corei7AVX,
1753     CK_CoreAVXi,
1754     CK_CoreAVX2,
1755     //@}
1756 
1757     /// \name Knights Landing
1758     /// Knights Landing processor.
1759     CK_KNL,
1760 
1761     /// \name K6
1762     /// K6 architecture processors.
1763     //@{
1764     CK_K6,
1765     CK_K6_2,
1766     CK_K6_3,
1767     //@}
1768 
1769     /// \name K7
1770     /// K7 architecture processors.
1771     //@{
1772     CK_Athlon,
1773     CK_AthlonThunderbird,
1774     CK_Athlon4,
1775     CK_AthlonXP,
1776     CK_AthlonMP,
1777     //@}
1778 
1779     /// \name K8
1780     /// K8 architecture processors.
1781     //@{
1782     CK_Athlon64,
1783     CK_Athlon64SSE3,
1784     CK_AthlonFX,
1785     CK_K8,
1786     CK_K8SSE3,
1787     CK_Opteron,
1788     CK_OpteronSSE3,
1789     CK_AMDFAM10,
1790     //@}
1791 
1792     /// \name Bobcat
1793     /// Bobcat architecture processors.
1794     //@{
1795     CK_BTVER1,
1796     CK_BTVER2,
1797     //@}
1798 
1799     /// \name Bulldozer
1800     /// Bulldozer architecture processors.
1801     //@{
1802     CK_BDVER1,
1803     CK_BDVER2,
1804     CK_BDVER3,
1805     CK_BDVER4,
1806     //@}
1807 
1808     /// This specification is deprecated and will be removed in the future.
1809     /// Users should prefer \see CK_K8.
1810     // FIXME: Warn on this when the CPU is set to it.
1811     CK_x86_64,
1812     //@}
1813 
1814     /// \name Geode
1815     /// Geode processors.
1816     //@{
1817     CK_Geode
1818     //@}
1819   } CPU;
1820 
1821   enum FPMathKind {
1822     FP_Default,
1823     FP_SSE,
1824     FP_387
1825   } FPMath;
1826 
1827 public:
1828   X86TargetInfo(const llvm::Triple &Triple)
1829       : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow),
1830         XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false),
1831         HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false),
1832         HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false),
1833         HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false),
1834         HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic),
1835         FPMath(FP_Default) {
1836     BigEndian = false;
1837     LongDoubleFormat = &llvm::APFloat::x87DoubleExtended;
1838   }
1839   unsigned getFloatEvalMethod() const override {
1840     // X87 evaluates with 80 bits "long double" precision.
1841     return SSELevel == NoSSE ? 2 : 0;
1842   }
1843   void getTargetBuiltins(const Builtin::Info *&Records,
1844                                  unsigned &NumRecords) const override {
1845     Records = BuiltinInfo;
1846     NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin;
1847   }
1848   void getGCCRegNames(const char * const *&Names,
1849                       unsigned &NumNames) const override {
1850     Names = GCCRegNames;
1851     NumNames = llvm::array_lengthof(GCCRegNames);
1852   }
1853   void getGCCRegAliases(const GCCRegAlias *&Aliases,
1854                         unsigned &NumAliases) const override {
1855     Aliases = nullptr;
1856     NumAliases = 0;
1857   }
1858   void getGCCAddlRegNames(const AddlRegName *&Names,
1859                           unsigned &NumNames) const override {
1860     Names = AddlRegNames;
1861     NumNames = llvm::array_lengthof(AddlRegNames);
1862   }
1863   bool validateAsmConstraint(const char *&Name,
1864                                      TargetInfo::ConstraintInfo &info) const override;
1865   std::string convertConstraint(const char *&Constraint) const override;
1866   const char *getClobbers() const override {
1867     return "~{dirflag},~{fpsr},~{flags}";
1868   }
1869   void getTargetDefines(const LangOptions &Opts,
1870                         MacroBuilder &Builder) const override;
1871   static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level,
1872                           bool Enabled);
1873   static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level,
1874                           bool Enabled);
1875   static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
1876                           bool Enabled);
1877   void setFeatureEnabled(llvm::StringMap<bool> &Features,
1878                          StringRef Name, bool Enabled) const override {
1879     setFeatureEnabledImpl(Features, Name, Enabled);
1880   }
1881   // This exists purely to cut down on the number of virtual calls in
1882   // getDefaultFeatures which calls this repeatedly.
1883   static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
1884                                     StringRef Name, bool Enabled);
1885   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override;
1886   bool hasFeature(StringRef Feature) const override;
1887   bool handleTargetFeatures(std::vector<std::string> &Features,
1888                             DiagnosticsEngine &Diags) override;
1889   StringRef getABI() const override {
1890     if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
1891       return "avx";
1892     else if (getTriple().getArch() == llvm::Triple::x86 &&
1893              MMX3DNowLevel == NoMMX3DNow)
1894       return "no-mmx";
1895     return "";
1896   }
1897   bool setCPU(const std::string &Name) override {
1898     CPU = llvm::StringSwitch<CPUKind>(Name)
1899       .Case("i386", CK_i386)
1900       .Case("i486", CK_i486)
1901       .Case("winchip-c6", CK_WinChipC6)
1902       .Case("winchip2", CK_WinChip2)
1903       .Case("c3", CK_C3)
1904       .Case("i586", CK_i586)
1905       .Case("pentium", CK_Pentium)
1906       .Case("pentium-mmx", CK_PentiumMMX)
1907       .Case("i686", CK_i686)
1908       .Case("pentiumpro", CK_PentiumPro)
1909       .Case("pentium2", CK_Pentium2)
1910       .Case("pentium3", CK_Pentium3)
1911       .Case("pentium3m", CK_Pentium3M)
1912       .Case("pentium-m", CK_PentiumM)
1913       .Case("c3-2", CK_C3_2)
1914       .Case("yonah", CK_Yonah)
1915       .Case("pentium4", CK_Pentium4)
1916       .Case("pentium4m", CK_Pentium4M)
1917       .Case("prescott", CK_Prescott)
1918       .Case("nocona", CK_Nocona)
1919       .Case("core2", CK_Core2)
1920       .Case("penryn", CK_Penryn)
1921       .Case("atom", CK_Atom)
1922       .Case("slm", CK_Silvermont)
1923       .Case("corei7", CK_Corei7)
1924       .Case("corei7-avx", CK_Corei7AVX)
1925       .Case("core-avx-i", CK_CoreAVXi)
1926       .Case("core-avx2", CK_CoreAVX2)
1927       .Case("knl", CK_KNL)
1928       .Case("k6", CK_K6)
1929       .Case("k6-2", CK_K6_2)
1930       .Case("k6-3", CK_K6_3)
1931       .Case("athlon", CK_Athlon)
1932       .Case("athlon-tbird", CK_AthlonThunderbird)
1933       .Case("athlon-4", CK_Athlon4)
1934       .Case("athlon-xp", CK_AthlonXP)
1935       .Case("athlon-mp", CK_AthlonMP)
1936       .Case("athlon64", CK_Athlon64)
1937       .Case("athlon64-sse3", CK_Athlon64SSE3)
1938       .Case("athlon-fx", CK_AthlonFX)
1939       .Case("k8", CK_K8)
1940       .Case("k8-sse3", CK_K8SSE3)
1941       .Case("opteron", CK_Opteron)
1942       .Case("opteron-sse3", CK_OpteronSSE3)
1943       .Case("amdfam10", CK_AMDFAM10)
1944       .Case("btver1", CK_BTVER1)
1945       .Case("btver2", CK_BTVER2)
1946       .Case("bdver1", CK_BDVER1)
1947       .Case("bdver2", CK_BDVER2)
1948       .Case("bdver3", CK_BDVER3)
1949       .Case("bdver4", CK_BDVER4)
1950       .Case("x86-64", CK_x86_64)
1951       .Case("geode", CK_Geode)
1952       .Default(CK_Generic);
1953 
1954     // Perform any per-CPU checks necessary to determine if this CPU is
1955     // acceptable.
1956     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
1957     // invalid without explaining *why*.
1958     switch (CPU) {
1959     case CK_Generic:
1960       // No processor selected!
1961       return false;
1962 
1963     case CK_i386:
1964     case CK_i486:
1965     case CK_WinChipC6:
1966     case CK_WinChip2:
1967     case CK_C3:
1968     case CK_i586:
1969     case CK_Pentium:
1970     case CK_PentiumMMX:
1971     case CK_i686:
1972     case CK_PentiumPro:
1973     case CK_Pentium2:
1974     case CK_Pentium3:
1975     case CK_Pentium3M:
1976     case CK_PentiumM:
1977     case CK_Yonah:
1978     case CK_C3_2:
1979     case CK_Pentium4:
1980     case CK_Pentium4M:
1981     case CK_Prescott:
1982     case CK_K6:
1983     case CK_K6_2:
1984     case CK_K6_3:
1985     case CK_Athlon:
1986     case CK_AthlonThunderbird:
1987     case CK_Athlon4:
1988     case CK_AthlonXP:
1989     case CK_AthlonMP:
1990     case CK_Geode:
1991       // Only accept certain architectures when compiling in 32-bit mode.
1992       if (getTriple().getArch() != llvm::Triple::x86)
1993         return false;
1994 
1995       // Fallthrough
1996     case CK_Nocona:
1997     case CK_Core2:
1998     case CK_Penryn:
1999     case CK_Atom:
2000     case CK_Silvermont:
2001     case CK_Corei7:
2002     case CK_Corei7AVX:
2003     case CK_CoreAVXi:
2004     case CK_CoreAVX2:
2005     case CK_KNL:
2006     case CK_Athlon64:
2007     case CK_Athlon64SSE3:
2008     case CK_AthlonFX:
2009     case CK_K8:
2010     case CK_K8SSE3:
2011     case CK_Opteron:
2012     case CK_OpteronSSE3:
2013     case CK_AMDFAM10:
2014     case CK_BTVER1:
2015     case CK_BTVER2:
2016     case CK_BDVER1:
2017     case CK_BDVER2:
2018     case CK_BDVER3:
2019     case CK_BDVER4:
2020     case CK_x86_64:
2021       return true;
2022     }
2023     llvm_unreachable("Unhandled CPU kind");
2024   }
2025 
2026   bool setFPMath(StringRef Name) override;
2027 
2028   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
2029     // We accept all non-ARM calling conventions
2030     return (CC == CC_X86ThisCall ||
2031             CC == CC_X86FastCall ||
2032             CC == CC_X86StdCall ||
2033             CC == CC_C ||
2034             CC == CC_X86Pascal ||
2035             CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning;
2036   }
2037 
2038   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
2039     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
2040   }
2041 };
2042 
2043 bool X86TargetInfo::setFPMath(StringRef Name) {
2044   if (Name == "387") {
2045     FPMath = FP_387;
2046     return true;
2047   }
2048   if (Name == "sse") {
2049     FPMath = FP_SSE;
2050     return true;
2051   }
2052   return false;
2053 }
2054 
2055 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const {
2056   // FIXME: This *really* should not be here.
2057 
2058   // X86_64 always has SSE2.
2059   if (getTriple().getArch() == llvm::Triple::x86_64)
2060     setFeatureEnabledImpl(Features, "sse2", true);
2061 
2062   switch (CPU) {
2063   case CK_Generic:
2064   case CK_i386:
2065   case CK_i486:
2066   case CK_i586:
2067   case CK_Pentium:
2068   case CK_i686:
2069   case CK_PentiumPro:
2070     break;
2071   case CK_PentiumMMX:
2072   case CK_Pentium2:
2073     setFeatureEnabledImpl(Features, "mmx", true);
2074     break;
2075   case CK_Pentium3:
2076   case CK_Pentium3M:
2077     setFeatureEnabledImpl(Features, "sse", true);
2078     break;
2079   case CK_PentiumM:
2080   case CK_Pentium4:
2081   case CK_Pentium4M:
2082   case CK_x86_64:
2083     setFeatureEnabledImpl(Features, "sse2", true);
2084     break;
2085   case CK_Yonah:
2086   case CK_Prescott:
2087   case CK_Nocona:
2088     setFeatureEnabledImpl(Features, "sse3", true);
2089     setFeatureEnabledImpl(Features, "cx16", true);
2090     break;
2091   case CK_Core2:
2092     setFeatureEnabledImpl(Features, "ssse3", true);
2093     setFeatureEnabledImpl(Features, "cx16", true);
2094     break;
2095   case CK_Penryn:
2096     setFeatureEnabledImpl(Features, "sse4.1", true);
2097     setFeatureEnabledImpl(Features, "cx16", true);
2098     break;
2099   case CK_Atom:
2100     setFeatureEnabledImpl(Features, "ssse3", true);
2101     setFeatureEnabledImpl(Features, "cx16", true);
2102     break;
2103   case CK_Silvermont:
2104     setFeatureEnabledImpl(Features, "sse4.2", true);
2105     setFeatureEnabledImpl(Features, "aes", true);
2106     setFeatureEnabledImpl(Features, "cx16", true);
2107     setFeatureEnabledImpl(Features, "pclmul", true);
2108     break;
2109   case CK_Corei7:
2110     setFeatureEnabledImpl(Features, "sse4.2", true);
2111     setFeatureEnabledImpl(Features, "cx16", true);
2112     break;
2113   case CK_Corei7AVX:
2114     setFeatureEnabledImpl(Features, "avx", true);
2115     setFeatureEnabledImpl(Features, "aes", true);
2116     setFeatureEnabledImpl(Features, "cx16", true);
2117     setFeatureEnabledImpl(Features, "pclmul", true);
2118     break;
2119   case CK_CoreAVXi:
2120     setFeatureEnabledImpl(Features, "avx", true);
2121     setFeatureEnabledImpl(Features, "aes", true);
2122     setFeatureEnabledImpl(Features, "pclmul", true);
2123     setFeatureEnabledImpl(Features, "rdrnd", true);
2124     setFeatureEnabledImpl(Features, "f16c", true);
2125     break;
2126   case CK_CoreAVX2:
2127     setFeatureEnabledImpl(Features, "avx2", true);
2128     setFeatureEnabledImpl(Features, "aes", true);
2129     setFeatureEnabledImpl(Features, "pclmul", true);
2130     setFeatureEnabledImpl(Features, "lzcnt", true);
2131     setFeatureEnabledImpl(Features, "rdrnd", true);
2132     setFeatureEnabledImpl(Features, "f16c", true);
2133     setFeatureEnabledImpl(Features, "bmi", true);
2134     setFeatureEnabledImpl(Features, "bmi2", true);
2135     setFeatureEnabledImpl(Features, "rtm", true);
2136     setFeatureEnabledImpl(Features, "fma", true);
2137     setFeatureEnabledImpl(Features, "cx16", true);
2138     break;
2139   case CK_KNL:
2140     setFeatureEnabledImpl(Features, "avx512f", true);
2141     setFeatureEnabledImpl(Features, "avx512cd", true);
2142     setFeatureEnabledImpl(Features, "avx512er", true);
2143     setFeatureEnabledImpl(Features, "avx512pf", true);
2144     setFeatureEnabledImpl(Features, "aes", true);
2145     setFeatureEnabledImpl(Features, "pclmul", true);
2146     setFeatureEnabledImpl(Features, "lzcnt", true);
2147     setFeatureEnabledImpl(Features, "rdrnd", true);
2148     setFeatureEnabledImpl(Features, "f16c", true);
2149     setFeatureEnabledImpl(Features, "bmi", true);
2150     setFeatureEnabledImpl(Features, "bmi2", true);
2151     setFeatureEnabledImpl(Features, "rtm", true);
2152     setFeatureEnabledImpl(Features, "fma", true);
2153     break;
2154   case CK_K6:
2155   case CK_WinChipC6:
2156     setFeatureEnabledImpl(Features, "mmx", true);
2157     break;
2158   case CK_K6_2:
2159   case CK_K6_3:
2160   case CK_WinChip2:
2161   case CK_C3:
2162     setFeatureEnabledImpl(Features, "3dnow", true);
2163     break;
2164   case CK_Athlon:
2165   case CK_AthlonThunderbird:
2166   case CK_Geode:
2167     setFeatureEnabledImpl(Features, "3dnowa", true);
2168     break;
2169   case CK_Athlon4:
2170   case CK_AthlonXP:
2171   case CK_AthlonMP:
2172     setFeatureEnabledImpl(Features, "sse", true);
2173     setFeatureEnabledImpl(Features, "3dnowa", true);
2174     break;
2175   case CK_K8:
2176   case CK_Opteron:
2177   case CK_Athlon64:
2178   case CK_AthlonFX:
2179     setFeatureEnabledImpl(Features, "sse2", true);
2180     setFeatureEnabledImpl(Features, "3dnowa", true);
2181     break;
2182   case CK_K8SSE3:
2183   case CK_OpteronSSE3:
2184   case CK_Athlon64SSE3:
2185     setFeatureEnabledImpl(Features, "sse3", true);
2186     setFeatureEnabledImpl(Features, "3dnowa", true);
2187     break;
2188   case CK_AMDFAM10:
2189     setFeatureEnabledImpl(Features, "sse3", true);
2190     setFeatureEnabledImpl(Features, "sse4a", true);
2191     setFeatureEnabledImpl(Features, "3dnowa", true);
2192     setFeatureEnabledImpl(Features, "lzcnt", true);
2193     setFeatureEnabledImpl(Features, "popcnt", true);
2194     break;
2195   case CK_BTVER1:
2196     setFeatureEnabledImpl(Features, "ssse3", true);
2197     setFeatureEnabledImpl(Features, "sse4a", true);
2198     setFeatureEnabledImpl(Features, "cx16", true);
2199     setFeatureEnabledImpl(Features, "lzcnt", true);
2200     setFeatureEnabledImpl(Features, "popcnt", true);
2201     setFeatureEnabledImpl(Features, "prfchw", true);
2202     break;
2203   case CK_BTVER2:
2204     setFeatureEnabledImpl(Features, "avx", true);
2205     setFeatureEnabledImpl(Features, "sse4a", true);
2206     setFeatureEnabledImpl(Features, "lzcnt", true);
2207     setFeatureEnabledImpl(Features, "aes", true);
2208     setFeatureEnabledImpl(Features, "pclmul", true);
2209     setFeatureEnabledImpl(Features, "prfchw", true);
2210     setFeatureEnabledImpl(Features, "bmi", true);
2211     setFeatureEnabledImpl(Features, "f16c", true);
2212     setFeatureEnabledImpl(Features, "cx16", true);
2213     break;
2214   case CK_BDVER1:
2215     setFeatureEnabledImpl(Features, "xop", true);
2216     setFeatureEnabledImpl(Features, "lzcnt", true);
2217     setFeatureEnabledImpl(Features, "aes", true);
2218     setFeatureEnabledImpl(Features, "pclmul", true);
2219     setFeatureEnabledImpl(Features, "prfchw", true);
2220     setFeatureEnabledImpl(Features, "cx16", true);
2221     break;
2222   case CK_BDVER4:
2223     setFeatureEnabledImpl(Features, "avx2", true);
2224     setFeatureEnabledImpl(Features, "bmi2", true);
2225     // FALLTHROUGH
2226   case CK_BDVER2:
2227   case CK_BDVER3:
2228     setFeatureEnabledImpl(Features, "xop", true);
2229     setFeatureEnabledImpl(Features, "lzcnt", true);
2230     setFeatureEnabledImpl(Features, "aes", true);
2231     setFeatureEnabledImpl(Features, "pclmul", true);
2232     setFeatureEnabledImpl(Features, "prfchw", true);
2233     setFeatureEnabledImpl(Features, "bmi", true);
2234     setFeatureEnabledImpl(Features, "fma", true);
2235     setFeatureEnabledImpl(Features, "f16c", true);
2236     setFeatureEnabledImpl(Features, "tbm", true);
2237     setFeatureEnabledImpl(Features, "cx16", true);
2238     break;
2239   case CK_C3_2:
2240     setFeatureEnabledImpl(Features, "sse", true);
2241     break;
2242   }
2243 }
2244 
2245 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features,
2246                                 X86SSEEnum Level, bool Enabled) {
2247   if (Enabled) {
2248     switch (Level) {
2249     case AVX512F:
2250       Features["avx512f"] = true;
2251     case AVX2:
2252       Features["avx2"] = true;
2253     case AVX:
2254       Features["avx"] = true;
2255     case SSE42:
2256       Features["sse4.2"] = true;
2257     case SSE41:
2258       Features["sse4.1"] = true;
2259     case SSSE3:
2260       Features["ssse3"] = true;
2261     case SSE3:
2262       Features["sse3"] = true;
2263     case SSE2:
2264       Features["sse2"] = true;
2265     case SSE1:
2266       Features["sse"] = true;
2267     case NoSSE:
2268       break;
2269     }
2270     return;
2271   }
2272 
2273   switch (Level) {
2274   case NoSSE:
2275   case SSE1:
2276     Features["sse"] = false;
2277   case SSE2:
2278     Features["sse2"] = Features["pclmul"] = Features["aes"] =
2279       Features["sha"] = false;
2280   case SSE3:
2281     Features["sse3"] = false;
2282     setXOPLevel(Features, NoXOP, false);
2283   case SSSE3:
2284     Features["ssse3"] = false;
2285   case SSE41:
2286     Features["sse4.1"] = false;
2287   case SSE42:
2288     Features["sse4.2"] = false;
2289   case AVX:
2290     Features["fma"] = Features["avx"] = Features["f16c"] = false;
2291     setXOPLevel(Features, FMA4, false);
2292   case AVX2:
2293     Features["avx2"] = false;
2294   case AVX512F:
2295     Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] =
2296       Features["avx512pf"] = false;
2297   }
2298 }
2299 
2300 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features,
2301                                 MMX3DNowEnum Level, bool Enabled) {
2302   if (Enabled) {
2303     switch (Level) {
2304     case AMD3DNowAthlon:
2305       Features["3dnowa"] = true;
2306     case AMD3DNow:
2307       Features["3dnow"] = true;
2308     case MMX:
2309       Features["mmx"] = true;
2310     case NoMMX3DNow:
2311       break;
2312     }
2313     return;
2314   }
2315 
2316   switch (Level) {
2317   case NoMMX3DNow:
2318   case MMX:
2319     Features["mmx"] = false;
2320   case AMD3DNow:
2321     Features["3dnow"] = false;
2322   case AMD3DNowAthlon:
2323     Features["3dnowa"] = false;
2324   }
2325 }
2326 
2327 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level,
2328                                 bool Enabled) {
2329   if (Enabled) {
2330     switch (Level) {
2331     case XOP:
2332       Features["xop"] = true;
2333     case FMA4:
2334       Features["fma4"] = true;
2335       setSSELevel(Features, AVX, true);
2336     case SSE4A:
2337       Features["sse4a"] = true;
2338       setSSELevel(Features, SSE3, true);
2339     case NoXOP:
2340       break;
2341     }
2342     return;
2343   }
2344 
2345   switch (Level) {
2346   case NoXOP:
2347   case SSE4A:
2348     Features["sse4a"] = false;
2349   case FMA4:
2350     Features["fma4"] = false;
2351   case XOP:
2352     Features["xop"] = false;
2353   }
2354 }
2355 
2356 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features,
2357                                           StringRef Name, bool Enabled) {
2358   // FIXME: This *really* should not be here.  We need some way of translating
2359   // options into llvm subtarget features.
2360   if (Name == "sse4")
2361     Name = "sse4.2";
2362 
2363   Features[Name] = Enabled;
2364 
2365   if (Name == "mmx") {
2366     setMMXLevel(Features, MMX, Enabled);
2367   } else if (Name == "sse") {
2368     setSSELevel(Features, SSE1, Enabled);
2369   } else if (Name == "sse2") {
2370     setSSELevel(Features, SSE2, Enabled);
2371   } else if (Name == "sse3") {
2372     setSSELevel(Features, SSE3, Enabled);
2373   } else if (Name == "ssse3") {
2374     setSSELevel(Features, SSSE3, Enabled);
2375   } else if (Name == "sse4.2") {
2376     setSSELevel(Features, SSE42, Enabled);
2377   } else if (Name == "sse4.1") {
2378     setSSELevel(Features, SSE41, Enabled);
2379   } else if (Name == "3dnow") {
2380     setMMXLevel(Features, AMD3DNow, Enabled);
2381   } else if (Name == "3dnowa") {
2382     setMMXLevel(Features, AMD3DNowAthlon, Enabled);
2383   } else if (Name == "aes") {
2384     if (Enabled)
2385       setSSELevel(Features, SSE2, Enabled);
2386   } else if (Name == "pclmul") {
2387     if (Enabled)
2388       setSSELevel(Features, SSE2, Enabled);
2389   } else if (Name == "avx") {
2390     setSSELevel(Features, AVX, Enabled);
2391   } else if (Name == "avx2") {
2392     setSSELevel(Features, AVX2, Enabled);
2393   } else if (Name == "avx512f") {
2394     setSSELevel(Features, AVX512F, Enabled);
2395   } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") {
2396     if (Enabled)
2397       setSSELevel(Features, AVX512F, Enabled);
2398   } else if (Name == "fma") {
2399     if (Enabled)
2400       setSSELevel(Features, AVX, Enabled);
2401   } else if (Name == "fma4") {
2402     setXOPLevel(Features, FMA4, Enabled);
2403   } else if (Name == "xop") {
2404     setXOPLevel(Features, XOP, Enabled);
2405   } else if (Name == "sse4a") {
2406     setXOPLevel(Features, SSE4A, Enabled);
2407   } else if (Name == "f16c") {
2408     if (Enabled)
2409       setSSELevel(Features, AVX, Enabled);
2410   } else if (Name == "sha") {
2411     if (Enabled)
2412       setSSELevel(Features, SSE2, Enabled);
2413   }
2414 }
2415 
2416 /// handleTargetFeatures - Perform initialization based on the user
2417 /// configured set of features.
2418 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
2419                                          DiagnosticsEngine &Diags) {
2420   // Remember the maximum enabled sselevel.
2421   for (unsigned i = 0, e = Features.size(); i !=e; ++i) {
2422     // Ignore disabled features.
2423     if (Features[i][0] == '-')
2424       continue;
2425 
2426     StringRef Feature = StringRef(Features[i]).substr(1);
2427 
2428     if (Feature == "aes") {
2429       HasAES = true;
2430       continue;
2431     }
2432 
2433     if (Feature == "pclmul") {
2434       HasPCLMUL = true;
2435       continue;
2436     }
2437 
2438     if (Feature == "lzcnt") {
2439       HasLZCNT = true;
2440       continue;
2441     }
2442 
2443     if (Feature == "rdrnd") {
2444       HasRDRND = true;
2445       continue;
2446     }
2447 
2448     if (Feature == "bmi") {
2449       HasBMI = true;
2450       continue;
2451     }
2452 
2453     if (Feature == "bmi2") {
2454       HasBMI2 = true;
2455       continue;
2456     }
2457 
2458     if (Feature == "popcnt") {
2459       HasPOPCNT = true;
2460       continue;
2461     }
2462 
2463     if (Feature == "rtm") {
2464       HasRTM = true;
2465       continue;
2466     }
2467 
2468     if (Feature == "prfchw") {
2469       HasPRFCHW = true;
2470       continue;
2471     }
2472 
2473     if (Feature == "rdseed") {
2474       HasRDSEED = true;
2475       continue;
2476     }
2477 
2478     if (Feature == "tbm") {
2479       HasTBM = true;
2480       continue;
2481     }
2482 
2483     if (Feature == "fma") {
2484       HasFMA = true;
2485       continue;
2486     }
2487 
2488     if (Feature == "f16c") {
2489       HasF16C = true;
2490       continue;
2491     }
2492 
2493     if (Feature == "avx512cd") {
2494       HasAVX512CD = true;
2495       continue;
2496     }
2497 
2498     if (Feature == "avx512er") {
2499       HasAVX512ER = true;
2500       continue;
2501     }
2502 
2503     if (Feature == "avx512pf") {
2504       HasAVX512PF = true;
2505       continue;
2506     }
2507 
2508     if (Feature == "sha") {
2509       HasSHA = true;
2510       continue;
2511     }
2512 
2513     if (Feature == "cx16") {
2514       HasCX16 = true;
2515       continue;
2516     }
2517 
2518     assert(Features[i][0] == '+' && "Invalid target feature!");
2519     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
2520       .Case("avx512f", AVX512F)
2521       .Case("avx2", AVX2)
2522       .Case("avx", AVX)
2523       .Case("sse4.2", SSE42)
2524       .Case("sse4.1", SSE41)
2525       .Case("ssse3", SSSE3)
2526       .Case("sse3", SSE3)
2527       .Case("sse2", SSE2)
2528       .Case("sse", SSE1)
2529       .Default(NoSSE);
2530     SSELevel = std::max(SSELevel, Level);
2531 
2532     MMX3DNowEnum ThreeDNowLevel =
2533       llvm::StringSwitch<MMX3DNowEnum>(Feature)
2534         .Case("3dnowa", AMD3DNowAthlon)
2535         .Case("3dnow", AMD3DNow)
2536         .Case("mmx", MMX)
2537         .Default(NoMMX3DNow);
2538     MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel);
2539 
2540     XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature)
2541         .Case("xop", XOP)
2542         .Case("fma4", FMA4)
2543         .Case("sse4a", SSE4A)
2544         .Default(NoXOP);
2545     XOPLevel = std::max(XOPLevel, XLevel);
2546   }
2547 
2548   // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled.
2549   // Can't do this earlier because we need to be able to explicitly enable
2550   // popcnt and still disable sse4.2.
2551   if (!HasPOPCNT && SSELevel >= SSE42 &&
2552       std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){
2553     HasPOPCNT = true;
2554     Features.push_back("+popcnt");
2555   }
2556 
2557   // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled.
2558   if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow &&
2559       std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){
2560     HasPRFCHW = true;
2561     Features.push_back("+prfchw");
2562   }
2563 
2564   // LLVM doesn't have a separate switch for fpmath, so only accept it if it
2565   // matches the selected sse level.
2566   if (FPMath == FP_SSE && SSELevel < SSE1) {
2567     Diags.Report(diag::err_target_unsupported_fpmath) << "sse";
2568     return false;
2569   } else if (FPMath == FP_387 && SSELevel >= SSE1) {
2570     Diags.Report(diag::err_target_unsupported_fpmath) << "387";
2571     return false;
2572   }
2573 
2574   // Don't tell the backend if we're turning off mmx; it will end up disabling
2575   // SSE, which we don't want.
2576   // Additionally, if SSE is enabled and mmx is not explicitly disabled,
2577   // then enable MMX.
2578   std::vector<std::string>::iterator it;
2579   it = std::find(Features.begin(), Features.end(), "-mmx");
2580   if (it != Features.end())
2581     Features.erase(it);
2582   else if (SSELevel > NoSSE)
2583     MMX3DNowLevel = std::max(MMX3DNowLevel, MMX);
2584   return true;
2585 }
2586 
2587 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
2588 /// definitions for this particular subtarget.
2589 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
2590                                      MacroBuilder &Builder) const {
2591   // Target identification.
2592   if (getTriple().getArch() == llvm::Triple::x86_64) {
2593     Builder.defineMacro("__amd64__");
2594     Builder.defineMacro("__amd64");
2595     Builder.defineMacro("__x86_64");
2596     Builder.defineMacro("__x86_64__");
2597   } else {
2598     DefineStd(Builder, "i386", Opts);
2599   }
2600 
2601   // Subtarget options.
2602   // FIXME: We are hard-coding the tune parameters based on the CPU, but they
2603   // truly should be based on -mtune options.
2604   switch (CPU) {
2605   case CK_Generic:
2606     break;
2607   case CK_i386:
2608     // The rest are coming from the i386 define above.
2609     Builder.defineMacro("__tune_i386__");
2610     break;
2611   case CK_i486:
2612   case CK_WinChipC6:
2613   case CK_WinChip2:
2614   case CK_C3:
2615     defineCPUMacros(Builder, "i486");
2616     break;
2617   case CK_PentiumMMX:
2618     Builder.defineMacro("__pentium_mmx__");
2619     Builder.defineMacro("__tune_pentium_mmx__");
2620     // Fallthrough
2621   case CK_i586:
2622   case CK_Pentium:
2623     defineCPUMacros(Builder, "i586");
2624     defineCPUMacros(Builder, "pentium");
2625     break;
2626   case CK_Pentium3:
2627   case CK_Pentium3M:
2628   case CK_PentiumM:
2629     Builder.defineMacro("__tune_pentium3__");
2630     // Fallthrough
2631   case CK_Pentium2:
2632   case CK_C3_2:
2633     Builder.defineMacro("__tune_pentium2__");
2634     // Fallthrough
2635   case CK_PentiumPro:
2636     Builder.defineMacro("__tune_i686__");
2637     Builder.defineMacro("__tune_pentiumpro__");
2638     // Fallthrough
2639   case CK_i686:
2640     Builder.defineMacro("__i686");
2641     Builder.defineMacro("__i686__");
2642     // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686.
2643     Builder.defineMacro("__pentiumpro");
2644     Builder.defineMacro("__pentiumpro__");
2645     break;
2646   case CK_Pentium4:
2647   case CK_Pentium4M:
2648     defineCPUMacros(Builder, "pentium4");
2649     break;
2650   case CK_Yonah:
2651   case CK_Prescott:
2652   case CK_Nocona:
2653     defineCPUMacros(Builder, "nocona");
2654     break;
2655   case CK_Core2:
2656   case CK_Penryn:
2657     defineCPUMacros(Builder, "core2");
2658     break;
2659   case CK_Atom:
2660     defineCPUMacros(Builder, "atom");
2661     break;
2662   case CK_Silvermont:
2663     defineCPUMacros(Builder, "slm");
2664     break;
2665   case CK_Corei7:
2666   case CK_Corei7AVX:
2667   case CK_CoreAVXi:
2668   case CK_CoreAVX2:
2669     defineCPUMacros(Builder, "corei7");
2670     break;
2671   case CK_KNL:
2672     defineCPUMacros(Builder, "knl");
2673     break;
2674   case CK_K6_2:
2675     Builder.defineMacro("__k6_2__");
2676     Builder.defineMacro("__tune_k6_2__");
2677     // Fallthrough
2678   case CK_K6_3:
2679     if (CPU != CK_K6_2) {  // In case of fallthrough
2680       // FIXME: GCC may be enabling these in cases where some other k6
2681       // architecture is specified but -m3dnow is explicitly provided. The
2682       // exact semantics need to be determined and emulated here.
2683       Builder.defineMacro("__k6_3__");
2684       Builder.defineMacro("__tune_k6_3__");
2685     }
2686     // Fallthrough
2687   case CK_K6:
2688     defineCPUMacros(Builder, "k6");
2689     break;
2690   case CK_Athlon:
2691   case CK_AthlonThunderbird:
2692   case CK_Athlon4:
2693   case CK_AthlonXP:
2694   case CK_AthlonMP:
2695     defineCPUMacros(Builder, "athlon");
2696     if (SSELevel != NoSSE) {
2697       Builder.defineMacro("__athlon_sse__");
2698       Builder.defineMacro("__tune_athlon_sse__");
2699     }
2700     break;
2701   case CK_K8:
2702   case CK_K8SSE3:
2703   case CK_x86_64:
2704   case CK_Opteron:
2705   case CK_OpteronSSE3:
2706   case CK_Athlon64:
2707   case CK_Athlon64SSE3:
2708   case CK_AthlonFX:
2709     defineCPUMacros(Builder, "k8");
2710     break;
2711   case CK_AMDFAM10:
2712     defineCPUMacros(Builder, "amdfam10");
2713     break;
2714   case CK_BTVER1:
2715     defineCPUMacros(Builder, "btver1");
2716     break;
2717   case CK_BTVER2:
2718     defineCPUMacros(Builder, "btver2");
2719     break;
2720   case CK_BDVER1:
2721     defineCPUMacros(Builder, "bdver1");
2722     break;
2723   case CK_BDVER2:
2724     defineCPUMacros(Builder, "bdver2");
2725     break;
2726   case CK_BDVER3:
2727     defineCPUMacros(Builder, "bdver3");
2728     break;
2729   case CK_BDVER4:
2730     defineCPUMacros(Builder, "bdver4");
2731     break;
2732   case CK_Geode:
2733     defineCPUMacros(Builder, "geode");
2734     break;
2735   }
2736 
2737   // Target properties.
2738   Builder.defineMacro("__REGISTER_PREFIX__", "");
2739 
2740   // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline
2741   // functions in glibc header files that use FP Stack inline asm which the
2742   // backend can't deal with (PR879).
2743   Builder.defineMacro("__NO_MATH_INLINES");
2744 
2745   if (HasAES)
2746     Builder.defineMacro("__AES__");
2747 
2748   if (HasPCLMUL)
2749     Builder.defineMacro("__PCLMUL__");
2750 
2751   if (HasLZCNT)
2752     Builder.defineMacro("__LZCNT__");
2753 
2754   if (HasRDRND)
2755     Builder.defineMacro("__RDRND__");
2756 
2757   if (HasBMI)
2758     Builder.defineMacro("__BMI__");
2759 
2760   if (HasBMI2)
2761     Builder.defineMacro("__BMI2__");
2762 
2763   if (HasPOPCNT)
2764     Builder.defineMacro("__POPCNT__");
2765 
2766   if (HasRTM)
2767     Builder.defineMacro("__RTM__");
2768 
2769   if (HasPRFCHW)
2770     Builder.defineMacro("__PRFCHW__");
2771 
2772   if (HasRDSEED)
2773     Builder.defineMacro("__RDSEED__");
2774 
2775   if (HasTBM)
2776     Builder.defineMacro("__TBM__");
2777 
2778   switch (XOPLevel) {
2779   case XOP:
2780     Builder.defineMacro("__XOP__");
2781   case FMA4:
2782     Builder.defineMacro("__FMA4__");
2783   case SSE4A:
2784     Builder.defineMacro("__SSE4A__");
2785   case NoXOP:
2786     break;
2787   }
2788 
2789   if (HasFMA)
2790     Builder.defineMacro("__FMA__");
2791 
2792   if (HasF16C)
2793     Builder.defineMacro("__F16C__");
2794 
2795   if (HasAVX512CD)
2796     Builder.defineMacro("__AVX512CD__");
2797   if (HasAVX512ER)
2798     Builder.defineMacro("__AVX512ER__");
2799   if (HasAVX512PF)
2800     Builder.defineMacro("__AVX512PF__");
2801 
2802   if (HasSHA)
2803     Builder.defineMacro("__SHA__");
2804 
2805   if (HasCX16)
2806     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
2807 
2808   // Each case falls through to the previous one here.
2809   switch (SSELevel) {
2810   case AVX512F:
2811     Builder.defineMacro("__AVX512F__");
2812   case AVX2:
2813     Builder.defineMacro("__AVX2__");
2814   case AVX:
2815     Builder.defineMacro("__AVX__");
2816   case SSE42:
2817     Builder.defineMacro("__SSE4_2__");
2818   case SSE41:
2819     Builder.defineMacro("__SSE4_1__");
2820   case SSSE3:
2821     Builder.defineMacro("__SSSE3__");
2822   case SSE3:
2823     Builder.defineMacro("__SSE3__");
2824   case SSE2:
2825     Builder.defineMacro("__SSE2__");
2826     Builder.defineMacro("__SSE2_MATH__");  // -mfp-math=sse always implied.
2827   case SSE1:
2828     Builder.defineMacro("__SSE__");
2829     Builder.defineMacro("__SSE_MATH__");   // -mfp-math=sse always implied.
2830   case NoSSE:
2831     break;
2832   }
2833 
2834   if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) {
2835     switch (SSELevel) {
2836     case AVX512F:
2837     case AVX2:
2838     case AVX:
2839     case SSE42:
2840     case SSE41:
2841     case SSSE3:
2842     case SSE3:
2843     case SSE2:
2844       Builder.defineMacro("_M_IX86_FP", Twine(2));
2845       break;
2846     case SSE1:
2847       Builder.defineMacro("_M_IX86_FP", Twine(1));
2848       break;
2849     default:
2850       Builder.defineMacro("_M_IX86_FP", Twine(0));
2851     }
2852   }
2853 
2854   // Each case falls through to the previous one here.
2855   switch (MMX3DNowLevel) {
2856   case AMD3DNowAthlon:
2857     Builder.defineMacro("__3dNOW_A__");
2858   case AMD3DNow:
2859     Builder.defineMacro("__3dNOW__");
2860   case MMX:
2861     Builder.defineMacro("__MMX__");
2862   case NoMMX3DNow:
2863     break;
2864   }
2865 
2866   if (CPU >= CK_i486) {
2867     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
2868     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
2869     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
2870   }
2871   if (CPU >= CK_i586)
2872     Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
2873 }
2874 
2875 bool X86TargetInfo::hasFeature(StringRef Feature) const {
2876   return llvm::StringSwitch<bool>(Feature)
2877       .Case("aes", HasAES)
2878       .Case("avx", SSELevel >= AVX)
2879       .Case("avx2", SSELevel >= AVX2)
2880       .Case("avx512f", SSELevel >= AVX512F)
2881       .Case("avx512cd", HasAVX512CD)
2882       .Case("avx512er", HasAVX512ER)
2883       .Case("avx512pf", HasAVX512PF)
2884       .Case("bmi", HasBMI)
2885       .Case("bmi2", HasBMI2)
2886       .Case("cx16", HasCX16)
2887       .Case("f16c", HasF16C)
2888       .Case("fma", HasFMA)
2889       .Case("fma4", XOPLevel >= FMA4)
2890       .Case("tbm", HasTBM)
2891       .Case("lzcnt", HasLZCNT)
2892       .Case("rdrnd", HasRDRND)
2893       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
2894       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
2895       .Case("mmx", MMX3DNowLevel >= MMX)
2896       .Case("pclmul", HasPCLMUL)
2897       .Case("popcnt", HasPOPCNT)
2898       .Case("rtm", HasRTM)
2899       .Case("prfchw", HasPRFCHW)
2900       .Case("rdseed", HasRDSEED)
2901       .Case("sha", HasSHA)
2902       .Case("sse", SSELevel >= SSE1)
2903       .Case("sse2", SSELevel >= SSE2)
2904       .Case("sse3", SSELevel >= SSE3)
2905       .Case("ssse3", SSELevel >= SSSE3)
2906       .Case("sse4.1", SSELevel >= SSE41)
2907       .Case("sse4.2", SSELevel >= SSE42)
2908       .Case("sse4a", XOPLevel >= SSE4A)
2909       .Case("x86", true)
2910       .Case("x86_32", getTriple().getArch() == llvm::Triple::x86)
2911       .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64)
2912       .Case("xop", XOPLevel >= XOP)
2913       .Default(false);
2914 }
2915 
2916 bool
2917 X86TargetInfo::validateAsmConstraint(const char *&Name,
2918                                      TargetInfo::ConstraintInfo &Info) const {
2919   switch (*Name) {
2920   default: return false;
2921   case 'Y': // first letter of a pair:
2922     switch (*(Name+1)) {
2923     default: return false;
2924     case '0':  // First SSE register.
2925     case 't':  // Any SSE register, when SSE2 is enabled.
2926     case 'i':  // Any SSE register, when SSE2 and inter-unit moves enabled.
2927     case 'm':  // any MMX register, when inter-unit moves enabled.
2928       break;   // falls through to setAllowsRegister.
2929   }
2930   case 'f': // any x87 floating point stack register.
2931     // Constraint 'f' cannot be used for output operands.
2932     if (Info.ConstraintStr[0] == '=')
2933       return false;
2934 
2935     Info.setAllowsRegister();
2936     return true;
2937   case 'a': // eax.
2938   case 'b': // ebx.
2939   case 'c': // ecx.
2940   case 'd': // edx.
2941   case 'S': // esi.
2942   case 'D': // edi.
2943   case 'A': // edx:eax.
2944   case 't': // top of floating point stack.
2945   case 'u': // second from top of floating point stack.
2946   case 'q': // Any register accessible as [r]l: a, b, c, and d.
2947   case 'y': // Any MMX register.
2948   case 'x': // Any SSE register.
2949   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
2950   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
2951   case 'l': // "Index" registers: any general register that can be used as an
2952             // index in a base+index memory access.
2953     Info.setAllowsRegister();
2954     return true;
2955   case 'C': // SSE floating point constant.
2956   case 'G': // x87 floating point constant.
2957   case 'e': // 32-bit signed integer constant for use with zero-extending
2958             // x86_64 instructions.
2959   case 'Z': // 32-bit unsigned integer constant for use with zero-extending
2960             // x86_64 instructions.
2961     return true;
2962   }
2963 }
2964 
2965 
2966 std::string
2967 X86TargetInfo::convertConstraint(const char *&Constraint) const {
2968   switch (*Constraint) {
2969   case 'a': return std::string("{ax}");
2970   case 'b': return std::string("{bx}");
2971   case 'c': return std::string("{cx}");
2972   case 'd': return std::string("{dx}");
2973   case 'S': return std::string("{si}");
2974   case 'D': return std::string("{di}");
2975   case 'p': // address
2976     return std::string("im");
2977   case 't': // top of floating point stack.
2978     return std::string("{st}");
2979   case 'u': // second from top of floating point stack.
2980     return std::string("{st(1)}"); // second from top of floating point stack.
2981   default:
2982     return std::string(1, *Constraint);
2983   }
2984 }
2985 } // end anonymous namespace
2986 
2987 namespace {
2988 // X86-32 generic target
2989 class X86_32TargetInfo : public X86TargetInfo {
2990 public:
2991   X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
2992     DoubleAlign = LongLongAlign = 32;
2993     LongDoubleWidth = 96;
2994     LongDoubleAlign = 32;
2995     SuitableAlign = 128;
2996     DescriptionString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128";
2997     SizeType = UnsignedInt;
2998     PtrDiffType = SignedInt;
2999     IntPtrType = SignedInt;
3000     RegParmMax = 3;
3001 
3002     // Use fpret for all types.
3003     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
3004                              (1 << TargetInfo::Double) |
3005                              (1 << TargetInfo::LongDouble));
3006 
3007     // x86-32 has atomics up to 8 bytes
3008     // FIXME: Check that we actually have cmpxchg8b before setting
3009     // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
3010     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
3011   }
3012   BuiltinVaListKind getBuiltinVaListKind() const override {
3013     return TargetInfo::CharPtrBuiltinVaList;
3014   }
3015 
3016   int getEHDataRegisterNumber(unsigned RegNo) const override {
3017     if (RegNo == 0) return 0;
3018     if (RegNo == 1) return 2;
3019     return -1;
3020   }
3021   bool validateInputSize(StringRef Constraint,
3022                          unsigned Size) const override {
3023     switch (Constraint[0]) {
3024     default: break;
3025     case 'a':
3026     case 'b':
3027     case 'c':
3028     case 'd':
3029       return Size <= 32;
3030     }
3031 
3032     return true;
3033   }
3034 };
3035 } // end anonymous namespace
3036 
3037 namespace {
3038 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> {
3039 public:
3040   NetBSDI386TargetInfo(const llvm::Triple &Triple)
3041       : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {}
3042 
3043   unsigned getFloatEvalMethod() const override {
3044     unsigned Major, Minor, Micro;
3045     getTriple().getOSVersion(Major, Minor, Micro);
3046     // New NetBSD uses the default rounding mode.
3047     if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0)
3048       return X86_32TargetInfo::getFloatEvalMethod();
3049     // NetBSD before 6.99.26 defaults to "double" rounding.
3050     return 1;
3051   }
3052 };
3053 } // end anonymous namespace
3054 
3055 namespace {
3056 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> {
3057 public:
3058   OpenBSDI386TargetInfo(const llvm::Triple &Triple)
3059       : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) {
3060     SizeType = UnsignedLong;
3061     IntPtrType = SignedLong;
3062     PtrDiffType = SignedLong;
3063   }
3064 };
3065 } // end anonymous namespace
3066 
3067 namespace {
3068 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> {
3069 public:
3070   BitrigI386TargetInfo(const llvm::Triple &Triple)
3071       : BitrigTargetInfo<X86_32TargetInfo>(Triple) {
3072     SizeType = UnsignedLong;
3073     IntPtrType = SignedLong;
3074     PtrDiffType = SignedLong;
3075   }
3076 };
3077 } // end anonymous namespace
3078 
3079 namespace {
3080 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> {
3081 public:
3082   DarwinI386TargetInfo(const llvm::Triple &Triple)
3083       : DarwinTargetInfo<X86_32TargetInfo>(Triple) {
3084     LongDoubleWidth = 128;
3085     LongDoubleAlign = 128;
3086     SuitableAlign = 128;
3087     MaxVectorAlign = 256;
3088     SizeType = UnsignedLong;
3089     IntPtrType = SignedLong;
3090     DescriptionString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128";
3091     HasAlignMac68kSupport = true;
3092   }
3093 
3094 };
3095 } // end anonymous namespace
3096 
3097 namespace {
3098 // x86-32 Windows target
3099 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> {
3100 public:
3101   WindowsX86_32TargetInfo(const llvm::Triple &Triple)
3102       : WindowsTargetInfo<X86_32TargetInfo>(Triple) {
3103     WCharType = UnsignedShort;
3104     DoubleAlign = LongLongAlign = 64;
3105     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3106   }
3107   void getTargetDefines(const LangOptions &Opts,
3108                         MacroBuilder &Builder) const override {
3109     WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder);
3110   }
3111 };
3112 
3113 // x86-32 Windows Visual Studio target
3114 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo {
3115 public:
3116   MicrosoftX86_32TargetInfo(const llvm::Triple &Triple)
3117       : WindowsX86_32TargetInfo(Triple) {
3118     LongDoubleWidth = LongDoubleAlign = 64;
3119     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3120   }
3121   void getTargetDefines(const LangOptions &Opts,
3122                         MacroBuilder &Builder) const override {
3123     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3124     WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder);
3125     // The value of the following reflects processor type.
3126     // 300=386, 400=486, 500=Pentium, 600=Blend (default)
3127     // We lost the original triple, so we use the default.
3128     Builder.defineMacro("_M_IX86", "600");
3129   }
3130 };
3131 } // end anonymous namespace
3132 
3133 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) {
3134   Builder.defineMacro("__MSVCRT__");
3135   Builder.defineMacro("__MINGW32__");
3136 
3137   // Mingw defines __declspec(a) to __attribute__((a)).  Clang supports
3138   // __declspec natively under -fms-extensions, but we define a no-op __declspec
3139   // macro anyway for pre-processor compatibility.
3140   if (Opts.MicrosoftExt)
3141     Builder.defineMacro("__declspec", "__declspec");
3142   else
3143     Builder.defineMacro("__declspec(a)", "__attribute__((a))");
3144 
3145   if (!Opts.MicrosoftExt) {
3146     // Provide macros for all the calling convention keywords.  Provide both
3147     // single and double underscore prefixed variants.  These are available on
3148     // x64 as well as x86, even though they have no effect.
3149     const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"};
3150     for (const char *CC : CCs) {
3151       std::string GCCSpelling = "__attribute__((__";
3152       GCCSpelling += CC;
3153       GCCSpelling += "__))";
3154       Builder.defineMacro(Twine("_") + CC, GCCSpelling);
3155       Builder.defineMacro(Twine("__") + CC, GCCSpelling);
3156     }
3157   }
3158 }
3159 
3160 namespace {
3161 // x86-32 MinGW target
3162 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo {
3163 public:
3164   MinGWX86_32TargetInfo(const llvm::Triple &Triple)
3165       : WindowsX86_32TargetInfo(Triple) {}
3166   void getTargetDefines(const LangOptions &Opts,
3167                         MacroBuilder &Builder) const override {
3168     WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder);
3169     DefineStd(Builder, "WIN32", Opts);
3170     DefineStd(Builder, "WINNT", Opts);
3171     Builder.defineMacro("_X86_");
3172     addMinGWDefines(Opts, Builder);
3173   }
3174 };
3175 } // end anonymous namespace
3176 
3177 namespace {
3178 // x86-32 Cygwin target
3179 class CygwinX86_32TargetInfo : public X86_32TargetInfo {
3180 public:
3181   CygwinX86_32TargetInfo(const llvm::Triple &Triple)
3182       : X86_32TargetInfo(Triple) {
3183     TLSSupported = false;
3184     WCharType = UnsignedShort;
3185     DoubleAlign = LongLongAlign = 64;
3186     DescriptionString = "e-m:w-p:32:32-i64:64-f80:32-n8:16:32-S32";
3187   }
3188   void getTargetDefines(const LangOptions &Opts,
3189                         MacroBuilder &Builder) const override {
3190     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3191     Builder.defineMacro("_X86_");
3192     Builder.defineMacro("__CYGWIN__");
3193     Builder.defineMacro("__CYGWIN32__");
3194     DefineStd(Builder, "unix", Opts);
3195     if (Opts.CPlusPlus)
3196       Builder.defineMacro("_GNU_SOURCE");
3197   }
3198 };
3199 } // end anonymous namespace
3200 
3201 namespace {
3202 // x86-32 Haiku target
3203 class HaikuX86_32TargetInfo : public X86_32TargetInfo {
3204 public:
3205   HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3206     SizeType = UnsignedLong;
3207     IntPtrType = SignedLong;
3208     PtrDiffType = SignedLong;
3209     ProcessIDType = SignedLong;
3210     this->UserLabelPrefix = "";
3211     this->TLSSupported = false;
3212   }
3213   void getTargetDefines(const LangOptions &Opts,
3214                         MacroBuilder &Builder) const override {
3215     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3216     Builder.defineMacro("__INTEL__");
3217     Builder.defineMacro("__HAIKU__");
3218   }
3219 };
3220 } // end anonymous namespace
3221 
3222 // RTEMS Target
3223 template<typename Target>
3224 class RTEMSTargetInfo : public OSTargetInfo<Target> {
3225 protected:
3226   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
3227                     MacroBuilder &Builder) const override {
3228     // RTEMS defines; list based off of gcc output
3229 
3230     Builder.defineMacro("__rtems__");
3231     Builder.defineMacro("__ELF__");
3232   }
3233 
3234 public:
3235   RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {
3236     this->UserLabelPrefix = "";
3237 
3238     switch (Triple.getArch()) {
3239     default:
3240     case llvm::Triple::x86:
3241       // this->MCountName = ".mcount";
3242       break;
3243     case llvm::Triple::mips:
3244     case llvm::Triple::mipsel:
3245     case llvm::Triple::ppc:
3246     case llvm::Triple::ppc64:
3247     case llvm::Triple::ppc64le:
3248       // this->MCountName = "_mcount";
3249       break;
3250     case llvm::Triple::arm:
3251       // this->MCountName = "__mcount";
3252       break;
3253     }
3254   }
3255 };
3256 
3257 namespace {
3258 // x86-32 RTEMS target
3259 class RTEMSX86_32TargetInfo : public X86_32TargetInfo {
3260 public:
3261   RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) {
3262     SizeType = UnsignedLong;
3263     IntPtrType = SignedLong;
3264     PtrDiffType = SignedLong;
3265     this->UserLabelPrefix = "";
3266   }
3267   void getTargetDefines(const LangOptions &Opts,
3268                         MacroBuilder &Builder) const override {
3269     X86_32TargetInfo::getTargetDefines(Opts, Builder);
3270     Builder.defineMacro("__INTEL__");
3271     Builder.defineMacro("__rtems__");
3272   }
3273 };
3274 } // end anonymous namespace
3275 
3276 namespace {
3277 // x86-64 generic target
3278 class X86_64TargetInfo : public X86TargetInfo {
3279 public:
3280   X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
3281     const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32;
3282     LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64;
3283     LongDoubleWidth = 128;
3284     LongDoubleAlign = 128;
3285     LargeArrayMinWidth = 128;
3286     LargeArrayAlign = 128;
3287     SuitableAlign = 128;
3288     SizeType    = IsX32 ? UnsignedInt      : UnsignedLong;
3289     PtrDiffType = IsX32 ? SignedInt        : SignedLong;
3290     IntPtrType  = IsX32 ? SignedInt        : SignedLong;
3291     IntMaxType  = IsX32 ? SignedLongLong   : SignedLong;
3292     Int64Type   = IsX32 ? SignedLongLong   : SignedLong;
3293     RegParmMax = 6;
3294 
3295     DescriptionString = (IsX32)
3296                             ? "e-m:e-" "p:32:32-" "i64:64-f80:128-n8:16:32:64-S128"
3297                             : "e-m:e-"            "i64:64-f80:128-n8:16:32:64-S128";
3298 
3299     // Use fpret only for long double.
3300     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
3301 
3302     // Use fp2ret for _Complex long double.
3303     ComplexLongDoubleUsesFP2Ret = true;
3304 
3305     // x86-64 has atomics up to 16 bytes.
3306     MaxAtomicPromoteWidth = 128;
3307     MaxAtomicInlineWidth = 128;
3308   }
3309   BuiltinVaListKind getBuiltinVaListKind() const override {
3310     return TargetInfo::X86_64ABIBuiltinVaList;
3311   }
3312 
3313   int getEHDataRegisterNumber(unsigned RegNo) const override {
3314     if (RegNo == 0) return 0;
3315     if (RegNo == 1) return 1;
3316     return -1;
3317   }
3318 
3319   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3320     return (CC == CC_C ||
3321             CC == CC_IntelOclBicc ||
3322             CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning;
3323   }
3324 
3325   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
3326     return CC_C;
3327   }
3328 
3329 };
3330 } // end anonymous namespace
3331 
3332 namespace {
3333 // x86-64 Windows target
3334 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> {
3335 public:
3336   WindowsX86_64TargetInfo(const llvm::Triple &Triple)
3337       : WindowsTargetInfo<X86_64TargetInfo>(Triple) {
3338     WCharType = UnsignedShort;
3339     LongWidth = LongAlign = 32;
3340     DoubleAlign = LongLongAlign = 64;
3341     IntMaxType = SignedLongLong;
3342     Int64Type = SignedLongLong;
3343     SizeType = UnsignedLongLong;
3344     PtrDiffType = SignedLongLong;
3345     IntPtrType = SignedLongLong;
3346     this->UserLabelPrefix = "";
3347   }
3348   void getTargetDefines(const LangOptions &Opts,
3349                                 MacroBuilder &Builder) const override {
3350     WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder);
3351     Builder.defineMacro("_WIN64");
3352   }
3353   BuiltinVaListKind getBuiltinVaListKind() const override {
3354     return TargetInfo::CharPtrBuiltinVaList;
3355   }
3356   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
3357     return (CC == CC_C ||
3358             CC == CC_IntelOclBicc ||
3359             CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning;
3360   }
3361 };
3362 } // end anonymous namespace
3363 
3364 namespace {
3365 // x86-64 Windows Visual Studio target
3366 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo {
3367 public:
3368   MicrosoftX86_64TargetInfo(const llvm::Triple &Triple)
3369       : WindowsX86_64TargetInfo(Triple) {
3370     LongDoubleWidth = LongDoubleAlign = 64;
3371     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
3372   }
3373   void getTargetDefines(const LangOptions &Opts,
3374                         MacroBuilder &Builder) const override {
3375     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3376     WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder);
3377     Builder.defineMacro("_M_X64");
3378     Builder.defineMacro("_M_AMD64");
3379   }
3380 };
3381 } // end anonymous namespace
3382 
3383 namespace {
3384 // x86-64 MinGW target
3385 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo {
3386 public:
3387   MinGWX86_64TargetInfo(const llvm::Triple &Triple)
3388       : WindowsX86_64TargetInfo(Triple) {}
3389   void getTargetDefines(const LangOptions &Opts,
3390                         MacroBuilder &Builder) const override {
3391     WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder);
3392     DefineStd(Builder, "WIN64", Opts);
3393     Builder.defineMacro("__MINGW64__");
3394     addMinGWDefines(Opts, Builder);
3395   }
3396 };
3397 } // end anonymous namespace
3398 
3399 namespace {
3400 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> {
3401 public:
3402   DarwinX86_64TargetInfo(const llvm::Triple &Triple)
3403       : DarwinTargetInfo<X86_64TargetInfo>(Triple) {
3404     Int64Type = SignedLongLong;
3405     MaxVectorAlign = 256;
3406     // The 64-bit iOS simulator uses the builtin bool type for Objective-C.
3407     llvm::Triple T = llvm::Triple(Triple);
3408     if (T.getOS() == llvm::Triple::IOS)
3409       UseSignedCharForObjCBool = false;
3410     DescriptionString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128";
3411   }
3412 };
3413 } // end anonymous namespace
3414 
3415 namespace {
3416 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> {
3417 public:
3418   OpenBSDX86_64TargetInfo(const llvm::Triple &Triple)
3419       : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) {
3420     IntMaxType = SignedLongLong;
3421     Int64Type = SignedLongLong;
3422   }
3423 };
3424 } // end anonymous namespace
3425 
3426 namespace {
3427 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> {
3428 public:
3429   BitrigX86_64TargetInfo(const llvm::Triple &Triple)
3430       : BitrigTargetInfo<X86_64TargetInfo>(Triple) {
3431     IntMaxType = SignedLongLong;
3432     Int64Type = SignedLongLong;
3433   }
3434 };
3435 }
3436 
3437 
3438 namespace {
3439 class ARMTargetInfo : public TargetInfo {
3440   // Possible FPU choices.
3441   enum FPUMode {
3442     VFP2FPU = (1 << 0),
3443     VFP3FPU = (1 << 1),
3444     VFP4FPU = (1 << 2),
3445     NeonFPU = (1 << 3),
3446     FPARMV8 = (1 << 4)
3447   };
3448 
3449   // Possible HWDiv features.
3450   enum HWDivMode {
3451     HWDivThumb = (1 << 0),
3452     HWDivARM = (1 << 1)
3453   };
3454 
3455   static bool FPUModeIsVFP(FPUMode Mode) {
3456     return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8);
3457   }
3458 
3459   static const TargetInfo::GCCRegAlias GCCRegAliases[];
3460   static const char * const GCCRegNames[];
3461 
3462   std::string ABI, CPU;
3463 
3464   enum {
3465     FP_Default,
3466     FP_VFP,
3467     FP_Neon
3468   } FPMath;
3469 
3470   unsigned FPU : 5;
3471 
3472   unsigned IsAAPCS : 1;
3473   unsigned IsThumb : 1;
3474   unsigned HWDiv : 2;
3475 
3476   // Initialized via features.
3477   unsigned SoftFloat : 1;
3478   unsigned SoftFloatABI : 1;
3479 
3480   unsigned CRC : 1;
3481   unsigned Crypto : 1;
3482 
3483   static const Builtin::Info BuiltinInfo[];
3484 
3485   static bool shouldUseInlineAtomic(const llvm::Triple &T) {
3486     StringRef ArchName = T.getArchName();
3487     if (T.getArch() == llvm::Triple::arm ||
3488         T.getArch() == llvm::Triple::armeb) {
3489       StringRef VersionStr;
3490       if (ArchName.startswith("armv"))
3491         VersionStr = ArchName.substr(4, 1);
3492       else if (ArchName.startswith("armebv"))
3493         VersionStr = ArchName.substr(6, 1);
3494       else
3495         return false;
3496       unsigned Version;
3497       if (VersionStr.getAsInteger(10, Version))
3498         return false;
3499       return Version >= 6;
3500     }
3501     assert(T.getArch() == llvm::Triple::thumb ||
3502            T.getArch() == llvm::Triple::thumbeb);
3503     StringRef VersionStr;
3504     if (ArchName.startswith("thumbv"))
3505       VersionStr = ArchName.substr(6, 1);
3506     else if (ArchName.startswith("thumbebv"))
3507       VersionStr = ArchName.substr(8, 1);
3508     else
3509       return false;
3510     unsigned Version;
3511     if (VersionStr.getAsInteger(10, Version))
3512       return false;
3513     return Version >= 7;
3514   }
3515 
3516   void setABIAAPCS() {
3517     IsAAPCS = true;
3518 
3519     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64;
3520     const llvm::Triple &T = getTriple();
3521 
3522     // size_t is unsigned long on Darwin and NetBSD.
3523     if (T.isOSDarwin() || T.getOS() == llvm::Triple::NetBSD)
3524       SizeType = UnsignedLong;
3525     else
3526       SizeType = UnsignedInt;
3527 
3528     switch (T.getOS()) {
3529     case llvm::Triple::NetBSD:
3530       WCharType = SignedInt;
3531       break;
3532     case llvm::Triple::Win32:
3533       WCharType = UnsignedShort;
3534       break;
3535     case llvm::Triple::Linux:
3536     default:
3537       // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int.
3538       WCharType = UnsignedInt;
3539       break;
3540     }
3541 
3542     UseBitFieldTypeAlignment = true;
3543 
3544     ZeroLengthBitfieldBoundary = 0;
3545 
3546     if (IsThumb) {
3547       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3548       // so set preferred for small types to 32.
3549       if (T.isOSBinFormatMachO()) {
3550         DescriptionString = BigEndian ?
3551                               "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3552                               "v128:64:128-a:0:32-n32-S64" :
3553                               "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3554                               "v128:64:128-a:0:32-n32-S64";
3555       } else if (T.isOSWindows()) {
3556         // FIXME: this is invalid for WindowsCE
3557         assert(!BigEndian && "Windows on ARM does not support big endian");
3558         DescriptionString = "e"
3559                             "-m:e"
3560                             "-p:32:32"
3561                             "-i1:8:32-i8:8:32-i16:16:32-i64:64"
3562                             "-v128:64:128"
3563                             "-a:0:32"
3564                             "-n32"
3565                             "-S64";
3566       } else {
3567         DescriptionString = BigEndian ?
3568                               "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3569                               "v128:64:128-a:0:32-n32-S64" :
3570                               "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:64-"
3571                               "v128:64:128-a:0:32-n32-S64";
3572       }
3573     } else {
3574       if (T.isOSBinFormatMachO())
3575         DescriptionString = BigEndian ?
3576                               "E-m:o-p:32:32-i64:64-v128:64:128-n32-S64" :
3577                               "e-m:o-p:32:32-i64:64-v128:64:128-n32-S64";
3578       else
3579         DescriptionString = BigEndian ?
3580                               "E-m:e-p:32:32-i64:64-v128:64:128-n32-S64" :
3581                               "e-m:e-p:32:32-i64:64-v128:64:128-n32-S64";
3582     }
3583 
3584     // FIXME: Enumerated types are variable width in straight AAPCS.
3585   }
3586 
3587   void setABIAPCS() {
3588     const llvm::Triple &T = getTriple();
3589 
3590     IsAAPCS = false;
3591 
3592     DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32;
3593 
3594     // size_t is unsigned int on FreeBSD.
3595     if (T.getOS() == llvm::Triple::FreeBSD)
3596       SizeType = UnsignedInt;
3597     else
3598       SizeType = UnsignedLong;
3599 
3600     // Revert to using SignedInt on apcs-gnu to comply with existing behaviour.
3601     WCharType = SignedInt;
3602 
3603     // Do not respect the alignment of bit-field types when laying out
3604     // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc.
3605     UseBitFieldTypeAlignment = false;
3606 
3607     /// gcc forces the alignment to 4 bytes, regardless of the type of the
3608     /// zero length bitfield.  This corresponds to EMPTY_FIELD_BOUNDARY in
3609     /// gcc.
3610     ZeroLengthBitfieldBoundary = 32;
3611 
3612     if (IsThumb) {
3613       // Thumb1 add sp, #imm requires the immediate value be multiple of 4,
3614       // so set preferred for small types to 32.
3615       if (T.isOSBinFormatMachO())
3616         DescriptionString = BigEndian ?
3617             "E-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3618             "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3619             "e-m:o-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3620             "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3621       else
3622         DescriptionString = BigEndian ?
3623             "E-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3624             "-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3625             "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-f64:32:64"
3626             "-v64:32:64-v128:32:128-a:0:32-n32-S32";
3627     } else {
3628       if (T.isOSBinFormatMachO())
3629         DescriptionString = BigEndian ?
3630             "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3631             "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3632       else
3633         DescriptionString = BigEndian ?
3634             "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" :
3635             "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32";
3636     }
3637 
3638     // FIXME: Override "preferred align" for double and long long.
3639   }
3640 
3641 public:
3642   ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian)
3643       : TargetInfo(Triple), CPU("arm1136j-s"), FPMath(FP_Default),
3644         IsAAPCS(true) {
3645     BigEndian = IsBigEndian;
3646 
3647     switch (getTriple().getOS()) {
3648     case llvm::Triple::NetBSD:
3649       PtrDiffType = SignedLong;
3650       break;
3651     default:
3652       PtrDiffType = SignedInt;
3653       break;
3654     }
3655 
3656     // {} in inline assembly are neon specifiers, not assembly variant
3657     // specifiers.
3658     NoAsmVariants = true;
3659 
3660     // FIXME: Should we just treat this as a feature?
3661     IsThumb = getTriple().getArchName().startswith("thumb");
3662 
3663     setABI("aapcs-linux");
3664 
3665     // ARM targets default to using the ARM C++ ABI.
3666     TheCXXABI.set(TargetCXXABI::GenericARM);
3667 
3668     // ARM has atomics up to 8 bytes
3669     MaxAtomicPromoteWidth = 64;
3670     if (shouldUseInlineAtomic(getTriple()))
3671       MaxAtomicInlineWidth = 64;
3672 
3673     // Do force alignment of members that follow zero length bitfields.  If
3674     // the alignment of the zero-length bitfield is greater than the member
3675     // that follows it, `bar', `bar' will be aligned as the  type of the
3676     // zero length bitfield.
3677     UseZeroLengthBitfieldAlignment = true;
3678   }
3679   StringRef getABI() const override { return ABI; }
3680   bool setABI(const std::string &Name) override {
3681     ABI = Name;
3682 
3683     // The defaults (above) are for AAPCS, check if we need to change them.
3684     //
3685     // FIXME: We need support for -meabi... we could just mangle it into the
3686     // name.
3687     if (Name == "apcs-gnu") {
3688       setABIAPCS();
3689       return true;
3690     }
3691     if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") {
3692       setABIAAPCS();
3693       return true;
3694     }
3695     return false;
3696   }
3697 
3698   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
3699     if (IsAAPCS)
3700       Features["aapcs"] = true;
3701     else
3702       Features["apcs"] = true;
3703 
3704     StringRef ArchName = getTriple().getArchName();
3705     if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore")
3706       Features["vfp2"] = true;
3707     else if (CPU == "cortex-a8" || CPU == "cortex-a9" ||
3708              CPU == "cortex-a9-mp") {
3709       Features["vfp3"] = true;
3710       Features["neon"] = true;
3711     }
3712     else if (CPU == "cortex-a5") {
3713       Features["vfp4"] = true;
3714       Features["neon"] = true;
3715     } else if (CPU == "swift" || CPU == "cortex-a7" ||
3716                CPU == "cortex-a12" || CPU == "cortex-a15" ||
3717                CPU == "krait") {
3718       Features["vfp4"] = true;
3719       Features["neon"] = true;
3720       Features["hwdiv"] = true;
3721       Features["hwdiv-arm"] = true;
3722     } else if (CPU == "cyclone") {
3723       Features["v8fp"] = true;
3724       Features["neon"] = true;
3725       Features["hwdiv"] = true;
3726       Features["hwdiv-arm"] = true;
3727     } else if (CPU == "cortex-a53" || CPU == "cortex-a57") {
3728       Features["fp-armv8"] = true;
3729       Features["neon"] = true;
3730       Features["hwdiv"] = true;
3731       Features["hwdiv-arm"] = true;
3732       Features["crc"] = true;
3733       Features["crypto"] = true;
3734     } else if (CPU == "cortex-r5" ||
3735                // Enable the hwdiv extension for all v8a AArch32 cores by
3736                // default.
3737                ArchName == "armv8a" || ArchName == "armv8" ||
3738                ArchName == "armebv8a" || ArchName == "armebv8" ||
3739                ArchName == "thumbv8a" || ArchName == "thumbv8" ||
3740                ArchName == "thumbebv8a" || ArchName == "thumbebv8") {
3741       Features["hwdiv"] = true;
3742       Features["hwdiv-arm"] = true;
3743     } else if (CPU == "cortex-m3" || CPU == "cortex-m4") {
3744       Features["hwdiv"] = true;
3745     }
3746   }
3747 
3748   bool handleTargetFeatures(std::vector<std::string> &Features,
3749                             DiagnosticsEngine &Diags) override {
3750     FPU = 0;
3751     CRC = 0;
3752     Crypto = 0;
3753     SoftFloat = SoftFloatABI = false;
3754     HWDiv = 0;
3755     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
3756       if (Features[i] == "+soft-float")
3757         SoftFloat = true;
3758       else if (Features[i] == "+soft-float-abi")
3759         SoftFloatABI = true;
3760       else if (Features[i] == "+vfp2")
3761         FPU |= VFP2FPU;
3762       else if (Features[i] == "+vfp3")
3763         FPU |= VFP3FPU;
3764       else if (Features[i] == "+vfp4")
3765         FPU |= VFP4FPU;
3766       else if (Features[i] == "+fp-armv8")
3767         FPU |= FPARMV8;
3768       else if (Features[i] == "+neon")
3769         FPU |= NeonFPU;
3770       else if (Features[i] == "+hwdiv")
3771         HWDiv |= HWDivThumb;
3772       else if (Features[i] == "+hwdiv-arm")
3773         HWDiv |= HWDivARM;
3774       else if (Features[i] == "+crc")
3775         CRC = 1;
3776       else if (Features[i] == "+crypto")
3777         Crypto = 1;
3778     }
3779 
3780     if (!(FPU & NeonFPU) && FPMath == FP_Neon) {
3781       Diags.Report(diag::err_target_unsupported_fpmath) << "neon";
3782       return false;
3783     }
3784 
3785     if (FPMath == FP_Neon)
3786       Features.push_back("+neonfp");
3787     else if (FPMath == FP_VFP)
3788       Features.push_back("-neonfp");
3789 
3790     // Remove front-end specific options which the backend handles differently.
3791     std::vector<std::string>::iterator it;
3792     it = std::find(Features.begin(), Features.end(), "+soft-float");
3793     if (it != Features.end())
3794       Features.erase(it);
3795     it = std::find(Features.begin(), Features.end(), "+soft-float-abi");
3796     if (it != Features.end())
3797       Features.erase(it);
3798     return true;
3799   }
3800 
3801   bool hasFeature(StringRef Feature) const override {
3802     return llvm::StringSwitch<bool>(Feature)
3803         .Case("arm", true)
3804         .Case("softfloat", SoftFloat)
3805         .Case("thumb", IsThumb)
3806         .Case("neon", (FPU & NeonFPU) && !SoftFloat)
3807         .Case("hwdiv", HWDiv & HWDivThumb)
3808         .Case("hwdiv-arm", HWDiv & HWDivARM)
3809         .Default(false);
3810   }
3811   // FIXME: Should we actually have some table instead of these switches?
3812   static const char *getCPUDefineSuffix(StringRef Name) {
3813     return llvm::StringSwitch<const char*>(Name)
3814       .Cases("arm8", "arm810", "4")
3815       .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4")
3816       .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T")
3817       .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T")
3818       .Case("ep9312", "4T")
3819       .Cases("arm10tdmi", "arm1020t", "5T")
3820       .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE")
3821       .Case("arm926ej-s", "5TEJ")
3822       .Cases("arm10e", "arm1020e", "arm1022e", "5TE")
3823       .Cases("xscale", "iwmmxt", "5TE")
3824       .Case("arm1136j-s", "6J")
3825       .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK")
3826       .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K")
3827       .Cases("arm1156t2-s", "arm1156t2f-s", "6T2")
3828       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "cortex-a9-mp", "7A")
3829       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "7A")
3830       .Cases("cortex-r4", "cortex-r5", "7R")
3831       .Case("swift", "7S")
3832       .Case("cyclone", "8A")
3833       .Case("cortex-m3", "7M")
3834       .Case("cortex-m4", "7EM")
3835       .Case("cortex-m0", "6M")
3836       .Cases("cortex-a53", "cortex-a57", "8A")
3837       .Default(nullptr);
3838   }
3839   static const char *getCPUProfile(StringRef Name) {
3840     return llvm::StringSwitch<const char*>(Name)
3841       .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A")
3842       .Cases("cortex-a9", "cortex-a12", "cortex-a15", "krait", "A")
3843       .Cases("cortex-a53", "cortex-a57", "A")
3844       .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M")
3845       .Cases("cortex-r4", "cortex-r5", "R")
3846       .Default("");
3847   }
3848   bool setCPU(const std::string &Name) override {
3849     if (!getCPUDefineSuffix(Name))
3850       return false;
3851 
3852     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
3853     StringRef Profile = getCPUProfile(Name);
3854     if (Profile == "M" && MaxAtomicInlineWidth) {
3855       MaxAtomicPromoteWidth = 32;
3856       MaxAtomicInlineWidth = 32;
3857     }
3858 
3859     CPU = Name;
3860     return true;
3861   }
3862   bool setFPMath(StringRef Name) override;
3863   bool supportsThumb(StringRef ArchName, StringRef CPUArch,
3864                      unsigned CPUArchVer) const {
3865     return CPUArchVer >= 7 || (CPUArch.find('T') != StringRef::npos) ||
3866            (CPUArch.find('M') != StringRef::npos);
3867   }
3868   bool supportsThumb2(StringRef ArchName, StringRef CPUArch,
3869                       unsigned CPUArchVer) const {
3870     // We check both CPUArchVer and ArchName because when only triple is
3871     // specified, the default CPU is arm1136j-s.
3872     return ArchName.endswith("v6t2") || ArchName.endswith("v7") ||
3873            ArchName.endswith("v8") || CPUArch == "6T2" || CPUArchVer >= 7;
3874   }
3875   void getTargetDefines(const LangOptions &Opts,
3876                         MacroBuilder &Builder) const override {
3877     // Target identification.
3878     Builder.defineMacro("__arm");
3879     Builder.defineMacro("__arm__");
3880 
3881     // Target properties.
3882     Builder.defineMacro("__REGISTER_PREFIX__", "");
3883 
3884     StringRef CPUArch = getCPUDefineSuffix(CPU);
3885     unsigned int CPUArchVer;
3886     if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) {
3887       llvm_unreachable("Invalid char for architecture version number");
3888     }
3889     Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__");
3890 
3891     // ACLE 6.4.1 ARM/Thumb instruction set architecture
3892     StringRef CPUProfile = getCPUProfile(CPU);
3893     StringRef ArchName = getTriple().getArchName();
3894 
3895     // __ARM_ARCH is defined as an integer value indicating the current ARM ISA
3896     Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1));
3897 
3898     // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA.  It
3899     // is not defined for the M-profile.
3900     // NOTE that the deffault profile is assumed to be 'A'
3901     if (CPUProfile.empty() || CPUProfile != "M")
3902       Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1");
3903 
3904     // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original
3905     // Thumb ISA (including v6-M).  It is set to 2 if the core supports the
3906     // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture.
3907     if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
3908       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2");
3909     else if (supportsThumb(ArchName, CPUArch, CPUArchVer))
3910       Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1");
3911 
3912     // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit
3913     // instruction set such as ARM or Thumb.
3914     Builder.defineMacro("__ARM_32BIT_STATE", "1");
3915 
3916     // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex)
3917 
3918     // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset.
3919     if (!CPUProfile.empty())
3920       Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'");
3921 
3922     // ACLE predefines.
3923     Builder.defineMacro("__ARM_ACLE", "200");
3924 
3925     // Subtarget options.
3926 
3927     // FIXME: It's more complicated than this and we don't really support
3928     // interworking.
3929     // Windows on ARM does not "support" interworking
3930     if (5 <= CPUArchVer && CPUArchVer <= 8 && !getTriple().isOSWindows())
3931       Builder.defineMacro("__THUMB_INTERWORK__");
3932 
3933     if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") {
3934       // Embedded targets on Darwin follow AAPCS, but not EABI.
3935       // Windows on ARM follows AAPCS VFP, but does not conform to EABI.
3936       if (!getTriple().isOSDarwin() && !getTriple().isOSWindows())
3937         Builder.defineMacro("__ARM_EABI__");
3938       Builder.defineMacro("__ARM_PCS", "1");
3939 
3940       if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp")
3941         Builder.defineMacro("__ARM_PCS_VFP", "1");
3942     }
3943 
3944     if (SoftFloat)
3945       Builder.defineMacro("__SOFTFP__");
3946 
3947     if (CPU == "xscale")
3948       Builder.defineMacro("__XSCALE__");
3949 
3950     if (IsThumb) {
3951       Builder.defineMacro("__THUMBEL__");
3952       Builder.defineMacro("__thumb__");
3953       if (supportsThumb2(ArchName, CPUArch, CPUArchVer))
3954         Builder.defineMacro("__thumb2__");
3955     }
3956     if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb))
3957       Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1");
3958 
3959     // Note, this is always on in gcc, even though it doesn't make sense.
3960     Builder.defineMacro("__APCS_32__");
3961 
3962     if (FPUModeIsVFP((FPUMode) FPU)) {
3963       Builder.defineMacro("__VFP_FP__");
3964       if (FPU & VFP2FPU)
3965         Builder.defineMacro("__ARM_VFPV2__");
3966       if (FPU & VFP3FPU)
3967         Builder.defineMacro("__ARM_VFPV3__");
3968       if (FPU & VFP4FPU)
3969         Builder.defineMacro("__ARM_VFPV4__");
3970     }
3971 
3972     // This only gets set when Neon instructions are actually available, unlike
3973     // the VFP define, hence the soft float and arch check. This is subtly
3974     // different from gcc, we follow the intent which was that it should be set
3975     // when Neon instructions are actually available.
3976     if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) {
3977       Builder.defineMacro("__ARM_NEON");
3978       Builder.defineMacro("__ARM_NEON__");
3979     }
3980 
3981     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
3982                         Opts.ShortWChar ? "2" : "4");
3983 
3984     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
3985                         Opts.ShortEnums ? "1" : "4");
3986 
3987     if (CRC)
3988       Builder.defineMacro("__ARM_FEATURE_CRC32");
3989 
3990     if (Crypto)
3991       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
3992 
3993     if (CPUArchVer >= 6 && CPUArch != "6M") {
3994       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
3995       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
3996       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
3997       Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
3998     }
3999   }
4000   void getTargetBuiltins(const Builtin::Info *&Records,
4001                          unsigned &NumRecords) const override {
4002     Records = BuiltinInfo;
4003     NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin;
4004   }
4005   bool isCLZForZeroUndef() const override { return false; }
4006   BuiltinVaListKind getBuiltinVaListKind() const override {
4007     return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList;
4008   }
4009   void getGCCRegNames(const char * const *&Names,
4010                       unsigned &NumNames) const override;
4011   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4012                         unsigned &NumAliases) const override;
4013   bool validateAsmConstraint(const char *&Name,
4014                              TargetInfo::ConstraintInfo &Info) const override {
4015     switch (*Name) {
4016     default: break;
4017     case 'l': // r0-r7
4018     case 'h': // r8-r15
4019     case 'w': // VFP Floating point register single precision
4020     case 'P': // VFP Floating point register double precision
4021       Info.setAllowsRegister();
4022       return true;
4023     case 'Q': // A memory address that is a single base register.
4024       Info.setAllowsMemory();
4025       return true;
4026     case 'U': // a memory reference...
4027       switch (Name[1]) {
4028       case 'q': // ...ARMV4 ldrsb
4029       case 'v': // ...VFP load/store (reg+constant offset)
4030       case 'y': // ...iWMMXt load/store
4031       case 't': // address valid for load/store opaque types wider
4032                 // than 128-bits
4033       case 'n': // valid address for Neon doubleword vector load/store
4034       case 'm': // valid address for Neon element and structure load/store
4035       case 's': // valid address for non-offset loads/stores of quad-word
4036                 // values in four ARM registers
4037         Info.setAllowsMemory();
4038         Name++;
4039         return true;
4040       }
4041     }
4042     return false;
4043   }
4044   std::string convertConstraint(const char *&Constraint) const override {
4045     std::string R;
4046     switch (*Constraint) {
4047     case 'U':   // Two-character constraint; add "^" hint for later parsing.
4048       R = std::string("^") + std::string(Constraint, 2);
4049       Constraint++;
4050       break;
4051     case 'p': // 'p' should be translated to 'r' by default.
4052       R = std::string("r");
4053       break;
4054     default:
4055       return std::string(1, *Constraint);
4056     }
4057     return R;
4058   }
4059   bool validateConstraintModifier(StringRef Constraint, const char Modifier,
4060                                   unsigned Size) const override {
4061     bool isOutput = (Constraint[0] == '=');
4062     bool isInOut = (Constraint[0] == '+');
4063 
4064     // Strip off constraint modifiers.
4065     while (Constraint[0] == '=' ||
4066            Constraint[0] == '+' ||
4067            Constraint[0] == '&')
4068       Constraint = Constraint.substr(1);
4069 
4070     switch (Constraint[0]) {
4071     default: break;
4072     case 'r': {
4073       switch (Modifier) {
4074       default:
4075         return (isInOut || isOutput || Size <= 64);
4076       case 'q':
4077         // A register of size 32 cannot fit a vector type.
4078         return false;
4079       }
4080     }
4081     }
4082 
4083     return true;
4084   }
4085   const char *getClobbers() const override {
4086     // FIXME: Is this really right?
4087     return "";
4088   }
4089 
4090   CallingConvCheckResult checkCallingConvention(CallingConv CC) const override {
4091     return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning;
4092   }
4093 
4094   int getEHDataRegisterNumber(unsigned RegNo) const override {
4095     if (RegNo == 0) return 0;
4096     if (RegNo == 1) return 1;
4097     return -1;
4098   }
4099 };
4100 
4101 bool ARMTargetInfo::setFPMath(StringRef Name) {
4102   if (Name == "neon") {
4103     FPMath = FP_Neon;
4104     return true;
4105   } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" ||
4106              Name == "vfp4") {
4107     FPMath = FP_VFP;
4108     return true;
4109   }
4110   return false;
4111 }
4112 
4113 const char * const ARMTargetInfo::GCCRegNames[] = {
4114   // Integer registers
4115   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4116   "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc",
4117 
4118   // Float registers
4119   "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
4120   "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
4121   "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
4122   "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4123 
4124   // Double registers
4125   "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7",
4126   "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15",
4127   "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23",
4128   "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4129 
4130   // Quad registers
4131   "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7",
4132   "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15"
4133 };
4134 
4135 void ARMTargetInfo::getGCCRegNames(const char * const *&Names,
4136                                    unsigned &NumNames) const {
4137   Names = GCCRegNames;
4138   NumNames = llvm::array_lengthof(GCCRegNames);
4139 }
4140 
4141 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = {
4142   { { "a1" }, "r0" },
4143   { { "a2" }, "r1" },
4144   { { "a3" }, "r2" },
4145   { { "a4" }, "r3" },
4146   { { "v1" }, "r4" },
4147   { { "v2" }, "r5" },
4148   { { "v3" }, "r6" },
4149   { { "v4" }, "r7" },
4150   { { "v5" }, "r8" },
4151   { { "v6", "rfp" }, "r9" },
4152   { { "sl" }, "r10" },
4153   { { "fp" }, "r11" },
4154   { { "ip" }, "r12" },
4155   { { "r13" }, "sp" },
4156   { { "r14" }, "lr" },
4157   { { "r15" }, "pc" },
4158   // The S, D and Q registers overlap, but aren't really aliases; we
4159   // don't want to substitute one of these for a different-sized one.
4160 };
4161 
4162 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4163                                        unsigned &NumAliases) const {
4164   Aliases = GCCRegAliases;
4165   NumAliases = llvm::array_lengthof(GCCRegAliases);
4166 }
4167 
4168 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = {
4169 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4170 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4171                                               ALL_LANGUAGES },
4172 #include "clang/Basic/BuiltinsNEON.def"
4173 
4174 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4175 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) { #ID, TYPE, ATTRS, 0, LANG },
4176 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4177                                               ALL_LANGUAGES },
4178 #include "clang/Basic/BuiltinsARM.def"
4179 };
4180 
4181 class ARMleTargetInfo : public ARMTargetInfo {
4182 public:
4183   ARMleTargetInfo(const llvm::Triple &Triple)
4184     : ARMTargetInfo(Triple, false) { }
4185   virtual void getTargetDefines(const LangOptions &Opts,
4186                                 MacroBuilder &Builder) const {
4187     Builder.defineMacro("__ARMEL__");
4188     ARMTargetInfo::getTargetDefines(Opts, Builder);
4189   }
4190 };
4191 
4192 class ARMbeTargetInfo : public ARMTargetInfo {
4193 public:
4194   ARMbeTargetInfo(const llvm::Triple &Triple)
4195     : ARMTargetInfo(Triple, true) { }
4196   virtual void getTargetDefines(const LangOptions &Opts,
4197                                 MacroBuilder &Builder) const {
4198     Builder.defineMacro("__ARMEB__");
4199     Builder.defineMacro("__ARM_BIG_ENDIAN");
4200     ARMTargetInfo::getTargetDefines(Opts, Builder);
4201   }
4202 };
4203 } // end anonymous namespace.
4204 
4205 namespace {
4206 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> {
4207   const llvm::Triple Triple;
4208 public:
4209   WindowsARMTargetInfo(const llvm::Triple &Triple)
4210     : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) {
4211     TLSSupported = false;
4212     WCharType = UnsignedShort;
4213     SizeType = UnsignedInt;
4214     UserLabelPrefix = "";
4215   }
4216   void getVisualStudioDefines(const LangOptions &Opts,
4217                               MacroBuilder &Builder) const {
4218     WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder);
4219 
4220     // FIXME: this is invalid for WindowsCE
4221     Builder.defineMacro("_M_ARM_NT", "1");
4222     Builder.defineMacro("_M_ARMT", "_M_ARM");
4223     Builder.defineMacro("_M_THUMB", "_M_ARM");
4224 
4225     assert((Triple.getArch() == llvm::Triple::arm ||
4226             Triple.getArch() == llvm::Triple::thumb) &&
4227            "invalid architecture for Windows ARM target info");
4228     unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6;
4229     Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset));
4230 
4231     // TODO map the complete set of values
4232     // 31: VFPv3 40: VFPv4
4233     Builder.defineMacro("_M_ARM_FP", "31");
4234   }
4235   BuiltinVaListKind getBuiltinVaListKind() const override {
4236     return TargetInfo::CharPtrBuiltinVaList;
4237   }
4238 };
4239 
4240 // Windows ARM + Itanium C++ ABI Target
4241 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo {
4242 public:
4243   ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple)
4244     : WindowsARMTargetInfo(Triple) {
4245     TheCXXABI.set(TargetCXXABI::GenericARM);
4246   }
4247 
4248   void getTargetDefines(const LangOptions &Opts,
4249                         MacroBuilder &Builder) const override {
4250     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4251 
4252     if (Opts.MSVCCompat)
4253       WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4254   }
4255 };
4256 
4257 // Windows ARM, MS (C++) ABI
4258 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo {
4259 public:
4260   MicrosoftARMleTargetInfo(const llvm::Triple &Triple)
4261     : WindowsARMTargetInfo(Triple) {
4262     TheCXXABI.set(TargetCXXABI::Microsoft);
4263   }
4264 
4265   void getTargetDefines(const LangOptions &Opts,
4266                         MacroBuilder &Builder) const override {
4267     WindowsARMTargetInfo::getTargetDefines(Opts, Builder);
4268     WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder);
4269   }
4270 };
4271 }
4272 
4273 
4274 namespace {
4275 class DarwinARMTargetInfo :
4276   public DarwinTargetInfo<ARMleTargetInfo> {
4277 protected:
4278   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4279                     MacroBuilder &Builder) const override {
4280     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4281   }
4282 
4283 public:
4284   DarwinARMTargetInfo(const llvm::Triple &Triple)
4285       : DarwinTargetInfo<ARMleTargetInfo>(Triple) {
4286     HasAlignMac68kSupport = true;
4287     // iOS always has 64-bit atomic instructions.
4288     // FIXME: This should be based off of the target features in ARMleTargetInfo.
4289     MaxAtomicInlineWidth = 64;
4290 
4291     // Darwin on iOS uses a variant of the ARM C++ ABI.
4292     TheCXXABI.set(TargetCXXABI::iOS);
4293   }
4294 };
4295 } // end anonymous namespace.
4296 
4297 
4298 namespace {
4299 class AArch64TargetInfo : public TargetInfo {
4300   virtual void setDescriptionString() = 0;
4301   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4302   static const char *const GCCRegNames[];
4303 
4304   enum FPUModeEnum {
4305     FPUMode,
4306     NeonMode
4307   };
4308 
4309   unsigned FPU;
4310   unsigned CRC;
4311   unsigned Crypto;
4312 
4313   static const Builtin::Info BuiltinInfo[];
4314 
4315   std::string ABI;
4316 
4317 public:
4318   AArch64TargetInfo(const llvm::Triple &Triple)
4319       : TargetInfo(Triple), ABI("aapcs") {
4320 
4321     if (getTriple().getOS() == llvm::Triple::NetBSD) {
4322       WCharType = SignedInt;
4323 
4324       // NetBSD apparently prefers consistency across ARM targets to consistency
4325       // across 64-bit targets.
4326       Int64Type = SignedLongLong;
4327       IntMaxType = SignedLongLong;
4328     } else {
4329       WCharType = UnsignedInt;
4330       Int64Type = SignedLong;
4331       IntMaxType = SignedLong;
4332     }
4333 
4334     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4335     MaxVectorAlign = 128;
4336     RegParmMax = 8;
4337     MaxAtomicInlineWidth = 128;
4338     MaxAtomicPromoteWidth = 128;
4339 
4340     LongDoubleWidth = LongDoubleAlign = 128;
4341     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4342 
4343     // {} in inline assembly are neon specifiers, not assembly variant
4344     // specifiers.
4345     NoAsmVariants = true;
4346 
4347     // AArch64 targets default to using the ARM C++ ABI.
4348     TheCXXABI.set(TargetCXXABI::GenericAArch64);
4349   }
4350 
4351   StringRef getABI() const override { return ABI; }
4352   virtual bool setABI(const std::string &Name) {
4353     if (Name != "aapcs" && Name != "darwinpcs")
4354       return false;
4355 
4356     ABI = Name;
4357     return true;
4358   }
4359 
4360   virtual bool setCPU(const std::string &Name) {
4361     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4362                         .Case("generic", true)
4363                         .Cases("cortex-a53", "cortex-a57", true)
4364                         .Case("cyclone", true)
4365                         .Default(false);
4366     return CPUKnown;
4367   }
4368 
4369   virtual void getTargetDefines(const LangOptions &Opts,
4370                                 MacroBuilder &Builder) const {
4371     // Target identification.
4372     Builder.defineMacro("__aarch64__");
4373 
4374     // Target properties.
4375     Builder.defineMacro("_LP64");
4376     Builder.defineMacro("__LP64__");
4377 
4378     // ACLE predefines. Many can only have one possible value on v8 AArch64.
4379     Builder.defineMacro("__ARM_ACLE", "200");
4380     Builder.defineMacro("__ARM_ARCH", "8");
4381     Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'");
4382 
4383     Builder.defineMacro("__ARM_64BIT_STATE");
4384     Builder.defineMacro("__ARM_PCS_AAPCS64");
4385     Builder.defineMacro("__ARM_ARCH_ISA_A64");
4386 
4387     Builder.defineMacro("__ARM_FEATURE_UNALIGNED");
4388     Builder.defineMacro("__ARM_FEATURE_CLZ");
4389     Builder.defineMacro("__ARM_FEATURE_FMA");
4390     Builder.defineMacro("__ARM_FEATURE_DIV");
4391 
4392     Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4");
4393 
4394     // 0xe implies support for half, single and double precision operations.
4395     Builder.defineMacro("__ARM_FP", "0xe");
4396 
4397     // PCS specifies this for SysV variants, which is all we support. Other ABIs
4398     // may choose __ARM_FP16_FORMAT_ALTERNATIVE.
4399     Builder.defineMacro("__ARM_FP16_FORMAT_IEEE");
4400 
4401     if (Opts.FastMath || Opts.FiniteMathOnly)
4402       Builder.defineMacro("__ARM_FP_FAST");
4403 
4404     if ((Opts.C99 || Opts.C11) && !Opts.Freestanding)
4405       Builder.defineMacro("__ARM_FP_FENV_ROUNDING");
4406 
4407     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4");
4408 
4409     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
4410                         Opts.ShortEnums ? "1" : "4");
4411 
4412     if (FPU == NeonMode) {
4413       Builder.defineMacro("__ARM_NEON");
4414       // 64-bit NEON supports half, single and double precision operations.
4415       Builder.defineMacro("__ARM_NEON_FP", "0xe");
4416     }
4417 
4418     if (CRC)
4419       Builder.defineMacro("__ARM_FEATURE_CRC32");
4420 
4421     if (Crypto)
4422       Builder.defineMacro("__ARM_FEATURE_CRYPTO");
4423   }
4424 
4425   virtual void getTargetBuiltins(const Builtin::Info *&Records,
4426                                  unsigned &NumRecords) const {
4427     Records = BuiltinInfo;
4428     NumRecords = clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin;
4429   }
4430 
4431   virtual bool hasFeature(StringRef Feature) const {
4432     return Feature == "aarch64" ||
4433       Feature == "arm64" ||
4434       (Feature == "neon" && FPU == NeonMode);
4435   }
4436 
4437   bool handleTargetFeatures(std::vector<std::string> &Features,
4438                             DiagnosticsEngine &Diags) override {
4439     FPU = FPUMode;
4440     CRC = 0;
4441     Crypto = 0;
4442     for (unsigned i = 0, e = Features.size(); i != e; ++i) {
4443       if (Features[i] == "+neon")
4444         FPU = NeonMode;
4445       if (Features[i] == "+crc")
4446         CRC = 1;
4447       if (Features[i] == "+crypto")
4448         Crypto = 1;
4449     }
4450 
4451     setDescriptionString();
4452 
4453     return true;
4454   }
4455 
4456   virtual bool isCLZForZeroUndef() const { return false; }
4457 
4458   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4459     return TargetInfo::AArch64ABIBuiltinVaList;
4460   }
4461 
4462   virtual void getGCCRegNames(const char *const *&Names,
4463                               unsigned &NumNames) const;
4464   virtual void getGCCRegAliases(const GCCRegAlias *&Aliases,
4465                                 unsigned &NumAliases) const;
4466 
4467   virtual bool validateAsmConstraint(const char *&Name,
4468                                      TargetInfo::ConstraintInfo &Info) const {
4469     switch (*Name) {
4470     default:
4471       return false;
4472     case 'w': // Floating point and SIMD registers (V0-V31)
4473       Info.setAllowsRegister();
4474       return true;
4475     case 'I': // Constant that can be used with an ADD instruction
4476     case 'J': // Constant that can be used with a SUB instruction
4477     case 'K': // Constant that can be used with a 32-bit logical instruction
4478     case 'L': // Constant that can be used with a 64-bit logical instruction
4479     case 'M': // Constant that can be used as a 32-bit MOV immediate
4480     case 'N': // Constant that can be used as a 64-bit MOV immediate
4481     case 'Y': // Floating point constant zero
4482     case 'Z': // Integer constant zero
4483       return true;
4484     case 'Q': // A memory reference with base register and no offset
4485       Info.setAllowsMemory();
4486       return true;
4487     case 'S': // A symbolic address
4488       Info.setAllowsRegister();
4489       return true;
4490     case 'U':
4491       // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
4492       // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
4493       // Usa: An absolute symbolic address
4494       // Ush: The high part (bits 32:12) of a pc-relative symbolic address
4495       llvm_unreachable("FIXME: Unimplemented support for bizarre constraints");
4496     case 'z': // Zero register, wzr or xzr
4497       Info.setAllowsRegister();
4498       return true;
4499     case 'x': // Floating point and SIMD registers (V0-V15)
4500       Info.setAllowsRegister();
4501       return true;
4502     }
4503     return false;
4504   }
4505 
4506   virtual bool validateConstraintModifier(StringRef Constraint,
4507                                           const char Modifier,
4508                                           unsigned Size) const {
4509     // Strip off constraint modifiers.
4510     while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&')
4511       Constraint = Constraint.substr(1);
4512 
4513     switch (Constraint[0]) {
4514     default:
4515       return true;
4516     case 'z':
4517     case 'r': {
4518       switch (Modifier) {
4519       case 'x':
4520       case 'w':
4521         // For now assume that the person knows what they're
4522         // doing with the modifier.
4523         return true;
4524       default:
4525         // By default an 'r' constraint will be in the 'x'
4526         // registers.
4527         return Size == 64;
4528       }
4529     }
4530     }
4531   }
4532 
4533   virtual const char *getClobbers() const { return ""; }
4534 
4535   int getEHDataRegisterNumber(unsigned RegNo) const {
4536     if (RegNo == 0)
4537       return 0;
4538     if (RegNo == 1)
4539       return 1;
4540     return -1;
4541   }
4542 };
4543 
4544 const char *const AArch64TargetInfo::GCCRegNames[] = {
4545   // 32-bit Integer registers
4546   "w0",  "w1",  "w2",  "w3",  "w4",  "w5",  "w6",  "w7",  "w8",  "w9",  "w10",
4547   "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21",
4548   "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp",
4549 
4550   // 64-bit Integer registers
4551   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",  "x8",  "x9",  "x10",
4552   "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21",
4553   "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp",  "lr",  "sp",
4554 
4555   // 32-bit floating point regsisters
4556   "s0",  "s1",  "s2",  "s3",  "s4",  "s5",  "s6",  "s7",  "s8",  "s9",  "s10",
4557   "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21",
4558   "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
4559 
4560   // 64-bit floating point regsisters
4561   "d0",  "d1",  "d2",  "d3",  "d4",  "d5",  "d6",  "d7",  "d8",  "d9",  "d10",
4562   "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21",
4563   "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31",
4564 
4565   // Vector registers
4566   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",  "v7",  "v8",  "v9",  "v10",
4567   "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21",
4568   "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
4569 };
4570 
4571 void AArch64TargetInfo::getGCCRegNames(const char *const *&Names,
4572                                      unsigned &NumNames) const {
4573   Names = GCCRegNames;
4574   NumNames = llvm::array_lengthof(GCCRegNames);
4575 }
4576 
4577 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = {
4578   { { "w31" }, "wsp" },
4579   { { "x29" }, "fp" },
4580   { { "x30" }, "lr" },
4581   { { "x31" }, "sp" },
4582   // The S/D/Q and W/X registers overlap, but aren't really aliases; we
4583   // don't want to substitute one of these for a different-sized one.
4584 };
4585 
4586 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4587                                        unsigned &NumAliases) const {
4588   Aliases = GCCRegAliases;
4589   NumAliases = llvm::array_lengthof(GCCRegAliases);
4590 }
4591 
4592 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = {
4593 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4594   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4595 #include "clang/Basic/BuiltinsNEON.def"
4596 
4597 #define BUILTIN(ID, TYPE, ATTRS)                                               \
4598   { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4599 #include "clang/Basic/BuiltinsAArch64.def"
4600 };
4601 
4602 class AArch64leTargetInfo : public AArch64TargetInfo {
4603   void setDescriptionString() override {
4604     if (getTriple().isOSBinFormatMachO())
4605       DescriptionString = "e-m:o-i64:64-i128:128-n32:64-S128";
4606     else
4607       DescriptionString = "e-m:e-i64:64-i128:128-n32:64-S128";
4608   }
4609 
4610 public:
4611   AArch64leTargetInfo(const llvm::Triple &Triple)
4612     : AArch64TargetInfo(Triple) {
4613     BigEndian = false;
4614     }
4615   void getTargetDefines(const LangOptions &Opts,
4616                         MacroBuilder &Builder) const override {
4617     Builder.defineMacro("__AARCH64EL__");
4618     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4619   }
4620 };
4621 
4622 class AArch64beTargetInfo : public AArch64TargetInfo {
4623   void setDescriptionString() override {
4624     assert(!getTriple().isOSBinFormatMachO());
4625     DescriptionString = "E-m:e-i64:64-i128:128-n32:64-S128";
4626   }
4627 
4628 public:
4629   AArch64beTargetInfo(const llvm::Triple &Triple)
4630     : AArch64TargetInfo(Triple) { }
4631   void getTargetDefines(const LangOptions &Opts,
4632                         MacroBuilder &Builder) const override {
4633     Builder.defineMacro("__AARCH64EB__");
4634     Builder.defineMacro("__AARCH_BIG_ENDIAN");
4635     Builder.defineMacro("__ARM_BIG_ENDIAN");
4636     AArch64TargetInfo::getTargetDefines(Opts, Builder);
4637   }
4638 };
4639 } // end anonymous namespace.
4640 
4641 namespace {
4642 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> {
4643 protected:
4644   void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple,
4645                     MacroBuilder &Builder) const override {
4646     Builder.defineMacro("__AARCH64_SIMD__");
4647     Builder.defineMacro("__ARM64_ARCH_8__");
4648     Builder.defineMacro("__ARM_NEON__");
4649     Builder.defineMacro("__LITTLE_ENDIAN__");
4650     Builder.defineMacro("__REGISTER_PREFIX__", "");
4651     Builder.defineMacro("__arm64", "1");
4652     Builder.defineMacro("__arm64__", "1");
4653 
4654     getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion);
4655   }
4656 
4657 public:
4658   DarwinAArch64TargetInfo(const llvm::Triple &Triple)
4659       : DarwinTargetInfo<AArch64leTargetInfo>(Triple) {
4660     Int64Type = SignedLongLong;
4661     WCharType = SignedInt;
4662     UseSignedCharForObjCBool = false;
4663 
4664     LongDoubleWidth = LongDoubleAlign = 64;
4665     LongDoubleFormat = &llvm::APFloat::IEEEdouble;
4666 
4667     TheCXXABI.set(TargetCXXABI::iOS64);
4668   }
4669 
4670   virtual BuiltinVaListKind getBuiltinVaListKind() const {
4671     return TargetInfo::CharPtrBuiltinVaList;
4672   }
4673 };
4674 } // end anonymous namespace
4675 
4676 namespace {
4677 // Hexagon abstract base class
4678 class HexagonTargetInfo : public TargetInfo {
4679   static const Builtin::Info BuiltinInfo[];
4680   static const char * const GCCRegNames[];
4681   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4682   std::string CPU;
4683 public:
4684   HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
4685     BigEndian = false;
4686     DescriptionString = "e-m:e-p:32:32-i1:32-i64:64-a:0-n32";
4687 
4688     // {} in inline assembly are packet specifiers, not assembly variant
4689     // specifiers.
4690     NoAsmVariants = true;
4691   }
4692 
4693   void getTargetBuiltins(const Builtin::Info *&Records,
4694                          unsigned &NumRecords) const override {
4695     Records = BuiltinInfo;
4696     NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin;
4697   }
4698 
4699   bool validateAsmConstraint(const char *&Name,
4700                              TargetInfo::ConstraintInfo &Info) const override {
4701     return true;
4702   }
4703 
4704   void getTargetDefines(const LangOptions &Opts,
4705                         MacroBuilder &Builder) const override;
4706 
4707   bool hasFeature(StringRef Feature) const override {
4708     return Feature == "hexagon";
4709   }
4710 
4711   BuiltinVaListKind getBuiltinVaListKind() const override {
4712     return TargetInfo::CharPtrBuiltinVaList;
4713   }
4714   void getGCCRegNames(const char * const *&Names,
4715                       unsigned &NumNames) const override;
4716   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4717                         unsigned &NumAliases) const override;
4718   const char *getClobbers() const override {
4719     return "";
4720   }
4721 
4722   static const char *getHexagonCPUSuffix(StringRef Name) {
4723     return llvm::StringSwitch<const char*>(Name)
4724       .Case("hexagonv4", "4")
4725       .Case("hexagonv5", "5")
4726       .Default(nullptr);
4727   }
4728 
4729   bool setCPU(const std::string &Name) override {
4730     if (!getHexagonCPUSuffix(Name))
4731       return false;
4732 
4733     CPU = Name;
4734     return true;
4735   }
4736 };
4737 
4738 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
4739                                 MacroBuilder &Builder) const {
4740   Builder.defineMacro("qdsp6");
4741   Builder.defineMacro("__qdsp6", "1");
4742   Builder.defineMacro("__qdsp6__", "1");
4743 
4744   Builder.defineMacro("hexagon");
4745   Builder.defineMacro("__hexagon", "1");
4746   Builder.defineMacro("__hexagon__", "1");
4747 
4748   if(CPU == "hexagonv1") {
4749     Builder.defineMacro("__HEXAGON_V1__");
4750     Builder.defineMacro("__HEXAGON_ARCH__", "1");
4751     if(Opts.HexagonQdsp6Compat) {
4752       Builder.defineMacro("__QDSP6_V1__");
4753       Builder.defineMacro("__QDSP6_ARCH__", "1");
4754     }
4755   }
4756   else if(CPU == "hexagonv2") {
4757     Builder.defineMacro("__HEXAGON_V2__");
4758     Builder.defineMacro("__HEXAGON_ARCH__", "2");
4759     if(Opts.HexagonQdsp6Compat) {
4760       Builder.defineMacro("__QDSP6_V2__");
4761       Builder.defineMacro("__QDSP6_ARCH__", "2");
4762     }
4763   }
4764   else if(CPU == "hexagonv3") {
4765     Builder.defineMacro("__HEXAGON_V3__");
4766     Builder.defineMacro("__HEXAGON_ARCH__", "3");
4767     if(Opts.HexagonQdsp6Compat) {
4768       Builder.defineMacro("__QDSP6_V3__");
4769       Builder.defineMacro("__QDSP6_ARCH__", "3");
4770     }
4771   }
4772   else if(CPU == "hexagonv4") {
4773     Builder.defineMacro("__HEXAGON_V4__");
4774     Builder.defineMacro("__HEXAGON_ARCH__", "4");
4775     if(Opts.HexagonQdsp6Compat) {
4776       Builder.defineMacro("__QDSP6_V4__");
4777       Builder.defineMacro("__QDSP6_ARCH__", "4");
4778     }
4779   }
4780   else if(CPU == "hexagonv5") {
4781     Builder.defineMacro("__HEXAGON_V5__");
4782     Builder.defineMacro("__HEXAGON_ARCH__", "5");
4783     if(Opts.HexagonQdsp6Compat) {
4784       Builder.defineMacro("__QDSP6_V5__");
4785       Builder.defineMacro("__QDSP6_ARCH__", "5");
4786     }
4787   }
4788 }
4789 
4790 const char * const HexagonTargetInfo::GCCRegNames[] = {
4791   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4792   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4793   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4794   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
4795   "p0", "p1", "p2", "p3",
4796   "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp"
4797 };
4798 
4799 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names,
4800                                    unsigned &NumNames) const {
4801   Names = GCCRegNames;
4802   NumNames = llvm::array_lengthof(GCCRegNames);
4803 }
4804 
4805 
4806 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = {
4807   { { "sp" }, "r29" },
4808   { { "fp" }, "r30" },
4809   { { "lr" }, "r31" },
4810  };
4811 
4812 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4813                                      unsigned &NumAliases) const {
4814   Aliases = GCCRegAliases;
4815   NumAliases = llvm::array_lengthof(GCCRegAliases);
4816 }
4817 
4818 
4819 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = {
4820 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
4821 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
4822                                               ALL_LANGUAGES },
4823 #include "clang/Basic/BuiltinsHexagon.def"
4824 };
4825 }
4826 
4827 
4828 namespace {
4829 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit).
4830 class SparcTargetInfo : public TargetInfo {
4831   static const TargetInfo::GCCRegAlias GCCRegAliases[];
4832   static const char * const GCCRegNames[];
4833   bool SoftFloat;
4834 public:
4835   SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {}
4836 
4837   bool handleTargetFeatures(std::vector<std::string> &Features,
4838                             DiagnosticsEngine &Diags) override {
4839     SoftFloat = false;
4840     for (unsigned i = 0, e = Features.size(); i != e; ++i)
4841       if (Features[i] == "+soft-float")
4842         SoftFloat = true;
4843     return true;
4844   }
4845   void getTargetDefines(const LangOptions &Opts,
4846                         MacroBuilder &Builder) const override {
4847     DefineStd(Builder, "sparc", Opts);
4848     Builder.defineMacro("__REGISTER_PREFIX__", "");
4849 
4850     if (SoftFloat)
4851       Builder.defineMacro("SOFT_FLOAT", "1");
4852   }
4853 
4854   bool hasFeature(StringRef Feature) const override {
4855     return llvm::StringSwitch<bool>(Feature)
4856              .Case("softfloat", SoftFloat)
4857              .Case("sparc", true)
4858              .Default(false);
4859   }
4860 
4861   void getTargetBuiltins(const Builtin::Info *&Records,
4862                          unsigned &NumRecords) const override {
4863     // FIXME: Implement!
4864   }
4865   BuiltinVaListKind getBuiltinVaListKind() const override {
4866     return TargetInfo::VoidPtrBuiltinVaList;
4867   }
4868   void getGCCRegNames(const char * const *&Names,
4869                       unsigned &NumNames) const override;
4870   void getGCCRegAliases(const GCCRegAlias *&Aliases,
4871                         unsigned &NumAliases) const override;
4872   bool validateAsmConstraint(const char *&Name,
4873                              TargetInfo::ConstraintInfo &info) const override {
4874     // FIXME: Implement!
4875     return false;
4876   }
4877   const char *getClobbers() const override {
4878     // FIXME: Implement!
4879     return "";
4880   }
4881 };
4882 
4883 const char * const SparcTargetInfo::GCCRegNames[] = {
4884   "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
4885   "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
4886   "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
4887   "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
4888 };
4889 
4890 void SparcTargetInfo::getGCCRegNames(const char * const *&Names,
4891                                      unsigned &NumNames) const {
4892   Names = GCCRegNames;
4893   NumNames = llvm::array_lengthof(GCCRegNames);
4894 }
4895 
4896 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = {
4897   { { "g0" }, "r0" },
4898   { { "g1" }, "r1" },
4899   { { "g2" }, "r2" },
4900   { { "g3" }, "r3" },
4901   { { "g4" }, "r4" },
4902   { { "g5" }, "r5" },
4903   { { "g6" }, "r6" },
4904   { { "g7" }, "r7" },
4905   { { "o0" }, "r8" },
4906   { { "o1" }, "r9" },
4907   { { "o2" }, "r10" },
4908   { { "o3" }, "r11" },
4909   { { "o4" }, "r12" },
4910   { { "o5" }, "r13" },
4911   { { "o6", "sp" }, "r14" },
4912   { { "o7" }, "r15" },
4913   { { "l0" }, "r16" },
4914   { { "l1" }, "r17" },
4915   { { "l2" }, "r18" },
4916   { { "l3" }, "r19" },
4917   { { "l4" }, "r20" },
4918   { { "l5" }, "r21" },
4919   { { "l6" }, "r22" },
4920   { { "l7" }, "r23" },
4921   { { "i0" }, "r24" },
4922   { { "i1" }, "r25" },
4923   { { "i2" }, "r26" },
4924   { { "i3" }, "r27" },
4925   { { "i4" }, "r28" },
4926   { { "i5" }, "r29" },
4927   { { "i6", "fp" }, "r30" },
4928   { { "i7" }, "r31" },
4929 };
4930 
4931 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
4932                                        unsigned &NumAliases) const {
4933   Aliases = GCCRegAliases;
4934   NumAliases = llvm::array_lengthof(GCCRegAliases);
4935 }
4936 
4937 // SPARC v8 is the 32-bit mode selected by Triple::sparc.
4938 class SparcV8TargetInfo : public SparcTargetInfo {
4939 public:
4940   SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4941     DescriptionString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64";
4942   }
4943 
4944   void getTargetDefines(const LangOptions &Opts,
4945                         MacroBuilder &Builder) const override {
4946     SparcTargetInfo::getTargetDefines(Opts, Builder);
4947     Builder.defineMacro("__sparcv8");
4948   }
4949 };
4950 
4951 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9.
4952 class SparcV9TargetInfo : public SparcTargetInfo {
4953 public:
4954   SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) {
4955     // FIXME: Support Sparc quad-precision long double?
4956     DescriptionString = "E-m:e-i64:64-n32:64-S128";
4957     // This is an LP64 platform.
4958     LongWidth = LongAlign = PointerWidth = PointerAlign = 64;
4959 
4960     // OpenBSD uses long long for int64_t and intmax_t.
4961     if (getTriple().getOS() == llvm::Triple::OpenBSD)
4962       IntMaxType = SignedLongLong;
4963     else
4964       IntMaxType = SignedLong;
4965     Int64Type = IntMaxType;
4966 
4967     // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit
4968     // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned.
4969     LongDoubleWidth = 128;
4970     LongDoubleAlign = 128;
4971     LongDoubleFormat = &llvm::APFloat::IEEEquad;
4972     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
4973   }
4974 
4975   void getTargetDefines(const LangOptions &Opts,
4976                         MacroBuilder &Builder) const override {
4977     SparcTargetInfo::getTargetDefines(Opts, Builder);
4978     Builder.defineMacro("__sparcv9");
4979     Builder.defineMacro("__arch64__");
4980     // Solaris and its derivative AuroraUX don't need these variants, but the
4981     // BSDs do.
4982     if (getTriple().getOS() != llvm::Triple::Solaris &&
4983         getTriple().getOS() != llvm::Triple::AuroraUX) {
4984       Builder.defineMacro("__sparc64__");
4985       Builder.defineMacro("__sparc_v9__");
4986       Builder.defineMacro("__sparcv9__");
4987     }
4988   }
4989 
4990   bool setCPU(const std::string &Name) override {
4991     bool CPUKnown = llvm::StringSwitch<bool>(Name)
4992       .Case("v9", true)
4993       .Case("ultrasparc", true)
4994       .Case("ultrasparc3", true)
4995       .Case("niagara", true)
4996       .Case("niagara2", true)
4997       .Case("niagara3", true)
4998       .Case("niagara4", true)
4999       .Default(false);
5000 
5001     // No need to store the CPU yet.  There aren't any CPU-specific
5002     // macros to define.
5003     return CPUKnown;
5004   }
5005 };
5006 
5007 } // end anonymous namespace.
5008 
5009 namespace {
5010 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> {
5011 public:
5012   AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple)
5013       : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) {
5014     SizeType = UnsignedInt;
5015     PtrDiffType = SignedInt;
5016   }
5017 };
5018 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> {
5019 public:
5020   SolarisSparcV8TargetInfo(const llvm::Triple &Triple)
5021       : SolarisTargetInfo<SparcV8TargetInfo>(Triple) {
5022     SizeType = UnsignedInt;
5023     PtrDiffType = SignedInt;
5024   }
5025 };
5026 } // end anonymous namespace.
5027 
5028 namespace {
5029 class SystemZTargetInfo : public TargetInfo {
5030   static const char *const GCCRegNames[];
5031 
5032 public:
5033   SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5034     TLSSupported = true;
5035     IntWidth = IntAlign = 32;
5036     LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64;
5037     PointerWidth = PointerAlign = 64;
5038     LongDoubleWidth = 128;
5039     LongDoubleAlign = 64;
5040     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5041     MinGlobalAlign = 16;
5042     DescriptionString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64";
5043     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5044   }
5045   void getTargetDefines(const LangOptions &Opts,
5046                         MacroBuilder &Builder) const override {
5047     Builder.defineMacro("__s390__");
5048     Builder.defineMacro("__s390x__");
5049     Builder.defineMacro("__zarch__");
5050     Builder.defineMacro("__LONG_DOUBLE_128__");
5051   }
5052   void getTargetBuiltins(const Builtin::Info *&Records,
5053                          unsigned &NumRecords) const override {
5054     // FIXME: Implement.
5055     Records = nullptr;
5056     NumRecords = 0;
5057   }
5058 
5059   void getGCCRegNames(const char *const *&Names,
5060                       unsigned &NumNames) const override;
5061   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5062                         unsigned &NumAliases) const override {
5063     // No aliases.
5064     Aliases = nullptr;
5065     NumAliases = 0;
5066   }
5067   bool validateAsmConstraint(const char *&Name,
5068                              TargetInfo::ConstraintInfo &info) const override;
5069   const char *getClobbers() const override {
5070     // FIXME: Is this really right?
5071     return "";
5072   }
5073   BuiltinVaListKind getBuiltinVaListKind() const override {
5074     return TargetInfo::SystemZBuiltinVaList;
5075   }
5076   bool setCPU(const std::string &Name) override {
5077     bool CPUKnown = llvm::StringSwitch<bool>(Name)
5078       .Case("z10", true)
5079       .Case("z196", true)
5080       .Case("zEC12", true)
5081       .Default(false);
5082 
5083     // No need to store the CPU yet.  There aren't any CPU-specific
5084     // macros to define.
5085     return CPUKnown;
5086   }
5087 };
5088 
5089 const char *const SystemZTargetInfo::GCCRegNames[] = {
5090   "r0",  "r1",  "r2",  "r3",  "r4",  "r5",  "r6",  "r7",
5091   "r8",  "r9",  "r10", "r11", "r12", "r13", "r14", "r15",
5092   "f0",  "f2",  "f4",  "f6",  "f1",  "f3",  "f5",  "f7",
5093   "f8",  "f10", "f12", "f14", "f9",  "f11", "f13", "f15"
5094 };
5095 
5096 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names,
5097                                        unsigned &NumNames) const {
5098   Names = GCCRegNames;
5099   NumNames = llvm::array_lengthof(GCCRegNames);
5100 }
5101 
5102 bool SystemZTargetInfo::
5103 validateAsmConstraint(const char *&Name,
5104                       TargetInfo::ConstraintInfo &Info) const {
5105   switch (*Name) {
5106   default:
5107     return false;
5108 
5109   case 'a': // Address register
5110   case 'd': // Data register (equivalent to 'r')
5111   case 'f': // Floating-point register
5112     Info.setAllowsRegister();
5113     return true;
5114 
5115   case 'I': // Unsigned 8-bit constant
5116   case 'J': // Unsigned 12-bit constant
5117   case 'K': // Signed 16-bit constant
5118   case 'L': // Signed 20-bit displacement (on all targets we support)
5119   case 'M': // 0x7fffffff
5120     return true;
5121 
5122   case 'Q': // Memory with base and unsigned 12-bit displacement
5123   case 'R': // Likewise, plus an index
5124   case 'S': // Memory with base and signed 20-bit displacement
5125   case 'T': // Likewise, plus an index
5126     Info.setAllowsMemory();
5127     return true;
5128   }
5129 }
5130 }
5131 
5132 namespace {
5133   class MSP430TargetInfo : public TargetInfo {
5134     static const char * const GCCRegNames[];
5135   public:
5136     MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5137       BigEndian = false;
5138       TLSSupported = false;
5139       IntWidth = 16; IntAlign = 16;
5140       LongWidth = 32; LongLongWidth = 64;
5141       LongAlign = LongLongAlign = 16;
5142       PointerWidth = 16; PointerAlign = 16;
5143       SuitableAlign = 16;
5144       SizeType = UnsignedInt;
5145       IntMaxType = SignedLongLong;
5146       IntPtrType = SignedInt;
5147       PtrDiffType = SignedInt;
5148       SigAtomicType = SignedLong;
5149       DescriptionString = "e-m:e-p:16:16-i32:16:32-n8:16";
5150     }
5151     void getTargetDefines(const LangOptions &Opts,
5152                           MacroBuilder &Builder) const override {
5153       Builder.defineMacro("MSP430");
5154       Builder.defineMacro("__MSP430__");
5155       // FIXME: defines for different 'flavours' of MCU
5156     }
5157     void getTargetBuiltins(const Builtin::Info *&Records,
5158                            unsigned &NumRecords) const override {
5159       // FIXME: Implement.
5160       Records = nullptr;
5161       NumRecords = 0;
5162     }
5163     bool hasFeature(StringRef Feature) const override {
5164       return Feature == "msp430";
5165     }
5166     void getGCCRegNames(const char * const *&Names,
5167                         unsigned &NumNames) const override;
5168     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5169                           unsigned &NumAliases) const override {
5170       // No aliases.
5171       Aliases = nullptr;
5172       NumAliases = 0;
5173     }
5174     bool validateAsmConstraint(const char *&Name,
5175                                TargetInfo::ConstraintInfo &info) const override {
5176       // No target constraints for now.
5177       return false;
5178     }
5179     const char *getClobbers() const override {
5180       // FIXME: Is this really right?
5181       return "";
5182     }
5183     BuiltinVaListKind getBuiltinVaListKind() const override {
5184       // FIXME: implement
5185       return TargetInfo::CharPtrBuiltinVaList;
5186    }
5187   };
5188 
5189   const char * const MSP430TargetInfo::GCCRegNames[] = {
5190     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
5191     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5192   };
5193 
5194   void MSP430TargetInfo::getGCCRegNames(const char * const *&Names,
5195                                         unsigned &NumNames) const {
5196     Names = GCCRegNames;
5197     NumNames = llvm::array_lengthof(GCCRegNames);
5198   }
5199 }
5200 
5201 namespace {
5202 
5203   // LLVM and Clang cannot be used directly to output native binaries for
5204   // target, but is used to compile C code to llvm bitcode with correct
5205   // type and alignment information.
5206   //
5207   // TCE uses the llvm bitcode as input and uses it for generating customized
5208   // target processor and program binary. TCE co-design environment is
5209   // publicly available in http://tce.cs.tut.fi
5210 
5211   static const unsigned TCEOpenCLAddrSpaceMap[] = {
5212       3, // opencl_global
5213       4, // opencl_local
5214       5, // opencl_constant
5215       0, // cuda_device
5216       0, // cuda_constant
5217       0  // cuda_shared
5218   };
5219 
5220   class TCETargetInfo : public TargetInfo{
5221   public:
5222     TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5223       TLSSupported = false;
5224       IntWidth = 32;
5225       LongWidth = LongLongWidth = 32;
5226       PointerWidth = 32;
5227       IntAlign = 32;
5228       LongAlign = LongLongAlign = 32;
5229       PointerAlign = 32;
5230       SuitableAlign = 32;
5231       SizeType = UnsignedInt;
5232       IntMaxType = SignedLong;
5233       IntPtrType = SignedInt;
5234       PtrDiffType = SignedInt;
5235       FloatWidth = 32;
5236       FloatAlign = 32;
5237       DoubleWidth = 32;
5238       DoubleAlign = 32;
5239       LongDoubleWidth = 32;
5240       LongDoubleAlign = 32;
5241       FloatFormat = &llvm::APFloat::IEEEsingle;
5242       DoubleFormat = &llvm::APFloat::IEEEsingle;
5243       LongDoubleFormat = &llvm::APFloat::IEEEsingle;
5244       DescriptionString = "E-p:32:32-i8:8:32-i16:16:32-i64:32"
5245                           "-f64:32-v64:32-v128:32-a:0:32-n32";
5246       AddrSpaceMap = &TCEOpenCLAddrSpaceMap;
5247       UseAddrSpaceMapMangling = true;
5248     }
5249 
5250     void getTargetDefines(const LangOptions &Opts,
5251                           MacroBuilder &Builder) const override {
5252       DefineStd(Builder, "tce", Opts);
5253       Builder.defineMacro("__TCE__");
5254       Builder.defineMacro("__TCE_V1__");
5255     }
5256     bool hasFeature(StringRef Feature) const override {
5257       return Feature == "tce";
5258     }
5259 
5260     void getTargetBuiltins(const Builtin::Info *&Records,
5261                            unsigned &NumRecords) const override {}
5262     const char *getClobbers() const override {
5263       return "";
5264     }
5265     BuiltinVaListKind getBuiltinVaListKind() const override {
5266       return TargetInfo::VoidPtrBuiltinVaList;
5267     }
5268     void getGCCRegNames(const char * const *&Names,
5269                         unsigned &NumNames) const override {}
5270     bool validateAsmConstraint(const char *&Name,
5271                                TargetInfo::ConstraintInfo &info) const override{
5272       return true;
5273     }
5274     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5275                           unsigned &NumAliases) const override {}
5276   };
5277 }
5278 
5279 namespace {
5280 class MipsTargetInfoBase : public TargetInfo {
5281   virtual void setDescriptionString() = 0;
5282 
5283   static const Builtin::Info BuiltinInfo[];
5284   std::string CPU;
5285   bool IsMips16;
5286   bool IsMicromips;
5287   bool IsNan2008;
5288   bool IsSingleFloat;
5289   enum MipsFloatABI {
5290     HardFloat, SoftFloat
5291   } FloatABI;
5292   enum DspRevEnum {
5293     NoDSP, DSP1, DSP2
5294   } DspRev;
5295   bool HasMSA;
5296 
5297 protected:
5298   bool HasFP64;
5299   std::string ABI;
5300 
5301 public:
5302   MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr,
5303                      const std::string &CPUStr)
5304       : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false),
5305         IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat),
5306         DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {}
5307 
5308   bool isNaN2008Default() const {
5309     return CPU == "mips32r6" || CPU == "mips64r6";
5310   }
5311 
5312   bool isFP64Default() const {
5313     return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64";
5314   }
5315 
5316   StringRef getABI() const override { return ABI; }
5317   bool setCPU(const std::string &Name) override {
5318     bool IsMips32 = getTriple().getArch() == llvm::Triple::mips ||
5319                     getTriple().getArch() == llvm::Triple::mipsel;
5320     CPU = Name;
5321     return llvm::StringSwitch<bool>(Name)
5322         .Case("mips1", IsMips32)
5323         .Case("mips2", IsMips32)
5324         .Case("mips3", true)
5325         .Case("mips4", true)
5326         .Case("mips5", true)
5327         .Case("mips32", IsMips32)
5328         .Case("mips32r2", IsMips32)
5329         .Case("mips32r6", IsMips32)
5330         .Case("mips64", true)
5331         .Case("mips64r2", true)
5332         .Case("mips64r6", true)
5333         .Case("octeon", true)
5334         .Default(false);
5335   }
5336   const std::string& getCPU() const { return CPU; }
5337   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5338     // The backend enables certain ABI's by default according to the
5339     // architecture.
5340     // Disable both possible defaults so that we don't end up with multiple
5341     // ABI's selected and trigger an assertion.
5342     Features["o32"] = false;
5343     Features["n64"] = false;
5344 
5345     Features[ABI] = true;
5346     if (CPU == "octeon")
5347       Features["mips64r2"] = Features["cnmips"] = true;
5348     else
5349       Features[CPU] = true;
5350   }
5351 
5352   void getTargetDefines(const LangOptions &Opts,
5353                         MacroBuilder &Builder) const override {
5354     Builder.defineMacro("__mips__");
5355     Builder.defineMacro("_mips");
5356     if (Opts.GNUMode)
5357       Builder.defineMacro("mips");
5358 
5359     Builder.defineMacro("__REGISTER_PREFIX__", "");
5360 
5361     switch (FloatABI) {
5362     case HardFloat:
5363       Builder.defineMacro("__mips_hard_float", Twine(1));
5364       break;
5365     case SoftFloat:
5366       Builder.defineMacro("__mips_soft_float", Twine(1));
5367       break;
5368     }
5369 
5370     if (IsSingleFloat)
5371       Builder.defineMacro("__mips_single_float", Twine(1));
5372 
5373     Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32));
5374     Builder.defineMacro("_MIPS_FPSET",
5375                         Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2)));
5376 
5377     if (IsMips16)
5378       Builder.defineMacro("__mips16", Twine(1));
5379 
5380     if (IsMicromips)
5381       Builder.defineMacro("__mips_micromips", Twine(1));
5382 
5383     if (IsNan2008)
5384       Builder.defineMacro("__mips_nan2008", Twine(1));
5385 
5386     switch (DspRev) {
5387     default:
5388       break;
5389     case DSP1:
5390       Builder.defineMacro("__mips_dsp_rev", Twine(1));
5391       Builder.defineMacro("__mips_dsp", Twine(1));
5392       break;
5393     case DSP2:
5394       Builder.defineMacro("__mips_dsp_rev", Twine(2));
5395       Builder.defineMacro("__mips_dspr2", Twine(1));
5396       Builder.defineMacro("__mips_dsp", Twine(1));
5397       break;
5398     }
5399 
5400     if (HasMSA)
5401       Builder.defineMacro("__mips_msa", Twine(1));
5402 
5403     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
5404     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
5405     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
5406 
5407     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
5408     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
5409   }
5410 
5411   void getTargetBuiltins(const Builtin::Info *&Records,
5412                          unsigned &NumRecords) const override {
5413     Records = BuiltinInfo;
5414     NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin;
5415   }
5416   bool hasFeature(StringRef Feature) const override {
5417     return llvm::StringSwitch<bool>(Feature)
5418       .Case("mips", true)
5419       .Case("fp64", HasFP64)
5420       .Default(false);
5421   }
5422   BuiltinVaListKind getBuiltinVaListKind() const override {
5423     return TargetInfo::VoidPtrBuiltinVaList;
5424   }
5425   void getGCCRegNames(const char * const *&Names,
5426                       unsigned &NumNames) const override {
5427     static const char *const GCCRegNames[] = {
5428       // CPU register names
5429       // Must match second column of GCCRegAliases
5430       "$0",   "$1",   "$2",   "$3",   "$4",   "$5",   "$6",   "$7",
5431       "$8",   "$9",   "$10",  "$11",  "$12",  "$13",  "$14",  "$15",
5432       "$16",  "$17",  "$18",  "$19",  "$20",  "$21",  "$22",  "$23",
5433       "$24",  "$25",  "$26",  "$27",  "$28",  "$29",  "$30",  "$31",
5434       // Floating point register names
5435       "$f0",  "$f1",  "$f2",  "$f3",  "$f4",  "$f5",  "$f6",  "$f7",
5436       "$f8",  "$f9",  "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
5437       "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
5438       "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
5439       // Hi/lo and condition register names
5440       "hi",   "lo",   "",     "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
5441       "$fcc5","$fcc6","$fcc7",
5442       // MSA register names
5443       "$w0",  "$w1",  "$w2",  "$w3",  "$w4",  "$w5",  "$w6",  "$w7",
5444       "$w8",  "$w9",  "$w10", "$w11", "$w12", "$w13", "$w14", "$w15",
5445       "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23",
5446       "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31",
5447       // MSA control register names
5448       "$msair",      "$msacsr", "$msaaccess", "$msasave", "$msamodify",
5449       "$msarequest", "$msamap", "$msaunmap"
5450     };
5451     Names = GCCRegNames;
5452     NumNames = llvm::array_lengthof(GCCRegNames);
5453   }
5454   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5455                         unsigned &NumAliases) const override = 0;
5456   bool validateAsmConstraint(const char *&Name,
5457                              TargetInfo::ConstraintInfo &Info) const override {
5458     switch (*Name) {
5459     default:
5460       return false;
5461 
5462     case 'r': // CPU registers.
5463     case 'd': // Equivalent to "r" unless generating MIPS16 code.
5464     case 'y': // Equivalent to "r", backward compatibility only.
5465     case 'f': // floating-point registers.
5466     case 'c': // $25 for indirect jumps
5467     case 'l': // lo register
5468     case 'x': // hilo register pair
5469       Info.setAllowsRegister();
5470       return true;
5471     case 'R': // An address that can be used in a non-macro load or store
5472       Info.setAllowsMemory();
5473       return true;
5474     }
5475   }
5476 
5477   const char *getClobbers() const override {
5478     // FIXME: Implement!
5479     return "";
5480   }
5481 
5482   bool handleTargetFeatures(std::vector<std::string> &Features,
5483                             DiagnosticsEngine &Diags) override {
5484     IsMips16 = false;
5485     IsMicromips = false;
5486     IsNan2008 = isNaN2008Default();
5487     IsSingleFloat = false;
5488     FloatABI = HardFloat;
5489     DspRev = NoDSP;
5490     HasFP64 = isFP64Default();
5491 
5492     for (std::vector<std::string>::iterator it = Features.begin(),
5493          ie = Features.end(); it != ie; ++it) {
5494       if (*it == "+single-float")
5495         IsSingleFloat = true;
5496       else if (*it == "+soft-float")
5497         FloatABI = SoftFloat;
5498       else if (*it == "+mips16")
5499         IsMips16 = true;
5500       else if (*it == "+micromips")
5501         IsMicromips = true;
5502       else if (*it == "+dsp")
5503         DspRev = std::max(DspRev, DSP1);
5504       else if (*it == "+dspr2")
5505         DspRev = std::max(DspRev, DSP2);
5506       else if (*it == "+msa")
5507         HasMSA = true;
5508       else if (*it == "+fp64")
5509         HasFP64 = true;
5510       else if (*it == "-fp64")
5511         HasFP64 = false;
5512       else if (*it == "+nan2008")
5513         IsNan2008 = true;
5514       else if (*it == "-nan2008")
5515         IsNan2008 = false;
5516     }
5517 
5518     // Remove front-end specific options.
5519     std::vector<std::string>::iterator it =
5520       std::find(Features.begin(), Features.end(), "+soft-float");
5521     if (it != Features.end())
5522       Features.erase(it);
5523 
5524     setDescriptionString();
5525 
5526     return true;
5527   }
5528 
5529   int getEHDataRegisterNumber(unsigned RegNo) const override {
5530     if (RegNo == 0) return 4;
5531     if (RegNo == 1) return 5;
5532     return -1;
5533   }
5534 
5535   bool isCLZForZeroUndef() const override { return false; }
5536 };
5537 
5538 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = {
5539 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
5540 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
5541                                               ALL_LANGUAGES },
5542 #include "clang/Basic/BuiltinsMips.def"
5543 };
5544 
5545 class Mips32TargetInfoBase : public MipsTargetInfoBase {
5546 public:
5547   Mips32TargetInfoBase(const llvm::Triple &Triple)
5548       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
5549     SizeType = UnsignedInt;
5550     PtrDiffType = SignedInt;
5551     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
5552   }
5553   bool setABI(const std::string &Name) override {
5554     if (Name == "o32" || Name == "eabi") {
5555       ABI = Name;
5556       return true;
5557     }
5558     return false;
5559   }
5560   void getTargetDefines(const LangOptions &Opts,
5561                         MacroBuilder &Builder) const override {
5562     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5563 
5564     Builder.defineMacro("__mips", "32");
5565     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32");
5566 
5567     const std::string& CPUStr = getCPU();
5568     if (CPUStr == "mips32")
5569       Builder.defineMacro("__mips_isa_rev", "1");
5570     else if (CPUStr == "mips32r2")
5571       Builder.defineMacro("__mips_isa_rev", "2");
5572 
5573     if (ABI == "o32") {
5574       Builder.defineMacro("__mips_o32");
5575       Builder.defineMacro("_ABIO32", "1");
5576       Builder.defineMacro("_MIPS_SIM", "_ABIO32");
5577     }
5578     else if (ABI == "eabi")
5579       Builder.defineMacro("__mips_eabi");
5580     else
5581       llvm_unreachable("Invalid ABI for Mips32.");
5582   }
5583   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5584                         unsigned &NumAliases) const override {
5585     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5586       { { "at" },  "$1" },
5587       { { "v0" },  "$2" },
5588       { { "v1" },  "$3" },
5589       { { "a0" },  "$4" },
5590       { { "a1" },  "$5" },
5591       { { "a2" },  "$6" },
5592       { { "a3" },  "$7" },
5593       { { "t0" },  "$8" },
5594       { { "t1" },  "$9" },
5595       { { "t2" }, "$10" },
5596       { { "t3" }, "$11" },
5597       { { "t4" }, "$12" },
5598       { { "t5" }, "$13" },
5599       { { "t6" }, "$14" },
5600       { { "t7" }, "$15" },
5601       { { "s0" }, "$16" },
5602       { { "s1" }, "$17" },
5603       { { "s2" }, "$18" },
5604       { { "s3" }, "$19" },
5605       { { "s4" }, "$20" },
5606       { { "s5" }, "$21" },
5607       { { "s6" }, "$22" },
5608       { { "s7" }, "$23" },
5609       { { "t8" }, "$24" },
5610       { { "t9" }, "$25" },
5611       { { "k0" }, "$26" },
5612       { { "k1" }, "$27" },
5613       { { "gp" }, "$28" },
5614       { { "sp","$sp" }, "$29" },
5615       { { "fp","$fp" }, "$30" },
5616       { { "ra" }, "$31" }
5617     };
5618     Aliases = GCCRegAliases;
5619     NumAliases = llvm::array_lengthof(GCCRegAliases);
5620   }
5621 };
5622 
5623 class Mips32EBTargetInfo : public Mips32TargetInfoBase {
5624   void setDescriptionString() override {
5625     DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5626   }
5627 
5628 public:
5629   Mips32EBTargetInfo(const llvm::Triple &Triple)
5630       : Mips32TargetInfoBase(Triple) {
5631   }
5632   void getTargetDefines(const LangOptions &Opts,
5633                         MacroBuilder &Builder) const override {
5634     DefineStd(Builder, "MIPSEB", Opts);
5635     Builder.defineMacro("_MIPSEB");
5636     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5637   }
5638 };
5639 
5640 class Mips32ELTargetInfo : public Mips32TargetInfoBase {
5641   void setDescriptionString() override {
5642     DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64";
5643   }
5644 
5645 public:
5646   Mips32ELTargetInfo(const llvm::Triple &Triple)
5647       : Mips32TargetInfoBase(Triple) {
5648     BigEndian = false;
5649   }
5650   void getTargetDefines(const LangOptions &Opts,
5651                         MacroBuilder &Builder) const override {
5652     DefineStd(Builder, "MIPSEL", Opts);
5653     Builder.defineMacro("_MIPSEL");
5654     Mips32TargetInfoBase::getTargetDefines(Opts, Builder);
5655   }
5656 };
5657 
5658 class Mips64TargetInfoBase : public MipsTargetInfoBase {
5659 public:
5660   Mips64TargetInfoBase(const llvm::Triple &Triple)
5661       : MipsTargetInfoBase(Triple, "n64", "mips64r2") {
5662     LongDoubleWidth = LongDoubleAlign = 128;
5663     LongDoubleFormat = &llvm::APFloat::IEEEquad;
5664     if (getTriple().getOS() == llvm::Triple::FreeBSD) {
5665       LongDoubleWidth = LongDoubleAlign = 64;
5666       LongDoubleFormat = &llvm::APFloat::IEEEdouble;
5667     }
5668     setN64ABITypes();
5669     SuitableAlign = 128;
5670     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
5671   }
5672 
5673   void setN64ABITypes() {
5674     LongWidth = LongAlign = 64;
5675     PointerWidth = PointerAlign = 64;
5676     SizeType = UnsignedLong;
5677     PtrDiffType = SignedLong;
5678   }
5679 
5680   void setN32ABITypes() {
5681     LongWidth = LongAlign = 32;
5682     PointerWidth = PointerAlign = 32;
5683     SizeType = UnsignedInt;
5684     PtrDiffType = SignedInt;
5685   }
5686 
5687   bool setABI(const std::string &Name) override {
5688     if (Name == "n32") {
5689       setN32ABITypes();
5690       ABI = Name;
5691       return true;
5692     }
5693     if (Name == "n64") {
5694       setN64ABITypes();
5695       ABI = Name;
5696       return true;
5697     }
5698     return false;
5699   }
5700 
5701   void getTargetDefines(const LangOptions &Opts,
5702                         MacroBuilder &Builder) const override {
5703     MipsTargetInfoBase::getTargetDefines(Opts, Builder);
5704 
5705     Builder.defineMacro("__mips", "64");
5706     Builder.defineMacro("__mips64");
5707     Builder.defineMacro("__mips64__");
5708     Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64");
5709 
5710     const std::string& CPUStr = getCPU();
5711     if (CPUStr == "mips64")
5712       Builder.defineMacro("__mips_isa_rev", "1");
5713     else if (CPUStr == "mips64r2")
5714       Builder.defineMacro("__mips_isa_rev", "2");
5715 
5716     if (ABI == "n32") {
5717       Builder.defineMacro("__mips_n32");
5718       Builder.defineMacro("_ABIN32", "2");
5719       Builder.defineMacro("_MIPS_SIM", "_ABIN32");
5720     }
5721     else if (ABI == "n64") {
5722       Builder.defineMacro("__mips_n64");
5723       Builder.defineMacro("_ABI64", "3");
5724       Builder.defineMacro("_MIPS_SIM", "_ABI64");
5725     }
5726     else
5727       llvm_unreachable("Invalid ABI for Mips64.");
5728   }
5729   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5730                         unsigned &NumAliases) const override {
5731     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
5732       { { "at" },  "$1" },
5733       { { "v0" },  "$2" },
5734       { { "v1" },  "$3" },
5735       { { "a0" },  "$4" },
5736       { { "a1" },  "$5" },
5737       { { "a2" },  "$6" },
5738       { { "a3" },  "$7" },
5739       { { "a4" },  "$8" },
5740       { { "a5" },  "$9" },
5741       { { "a6" }, "$10" },
5742       { { "a7" }, "$11" },
5743       { { "t0" }, "$12" },
5744       { { "t1" }, "$13" },
5745       { { "t2" }, "$14" },
5746       { { "t3" }, "$15" },
5747       { { "s0" }, "$16" },
5748       { { "s1" }, "$17" },
5749       { { "s2" }, "$18" },
5750       { { "s3" }, "$19" },
5751       { { "s4" }, "$20" },
5752       { { "s5" }, "$21" },
5753       { { "s6" }, "$22" },
5754       { { "s7" }, "$23" },
5755       { { "t8" }, "$24" },
5756       { { "t9" }, "$25" },
5757       { { "k0" }, "$26" },
5758       { { "k1" }, "$27" },
5759       { { "gp" }, "$28" },
5760       { { "sp","$sp" }, "$29" },
5761       { { "fp","$fp" }, "$30" },
5762       { { "ra" }, "$31" }
5763     };
5764     Aliases = GCCRegAliases;
5765     NumAliases = llvm::array_lengthof(GCCRegAliases);
5766   }
5767 
5768   bool hasInt128Type() const override { return true; }
5769 };
5770 
5771 class Mips64EBTargetInfo : public Mips64TargetInfoBase {
5772   void setDescriptionString() override {
5773     if (ABI == "n32")
5774       DescriptionString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5775     else
5776       DescriptionString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5777 
5778   }
5779 
5780 public:
5781   Mips64EBTargetInfo(const llvm::Triple &Triple)
5782       : Mips64TargetInfoBase(Triple) {}
5783   void getTargetDefines(const LangOptions &Opts,
5784                         MacroBuilder &Builder) const override {
5785     DefineStd(Builder, "MIPSEB", Opts);
5786     Builder.defineMacro("_MIPSEB");
5787     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5788   }
5789 };
5790 
5791 class Mips64ELTargetInfo : public Mips64TargetInfoBase {
5792   void setDescriptionString() override {
5793     if (ABI == "n32")
5794       DescriptionString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5795     else
5796       DescriptionString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128";
5797   }
5798 public:
5799   Mips64ELTargetInfo(const llvm::Triple &Triple)
5800       : Mips64TargetInfoBase(Triple) {
5801     // Default ABI is n64.
5802     BigEndian = false;
5803   }
5804   void getTargetDefines(const LangOptions &Opts,
5805                         MacroBuilder &Builder) const override {
5806     DefineStd(Builder, "MIPSEL", Opts);
5807     Builder.defineMacro("_MIPSEL");
5808     Mips64TargetInfoBase::getTargetDefines(Opts, Builder);
5809   }
5810 };
5811 } // end anonymous namespace.
5812 
5813 namespace {
5814 class PNaClTargetInfo : public TargetInfo {
5815 public:
5816   PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5817     BigEndian = false;
5818     this->UserLabelPrefix = "";
5819     this->LongAlign = 32;
5820     this->LongWidth = 32;
5821     this->PointerAlign = 32;
5822     this->PointerWidth = 32;
5823     this->IntMaxType = TargetInfo::SignedLongLong;
5824     this->Int64Type = TargetInfo::SignedLongLong;
5825     this->DoubleAlign = 64;
5826     this->LongDoubleWidth = 64;
5827     this->LongDoubleAlign = 64;
5828     this->SizeType = TargetInfo::UnsignedInt;
5829     this->PtrDiffType = TargetInfo::SignedInt;
5830     this->IntPtrType = TargetInfo::SignedInt;
5831     this->RegParmMax = 0; // Disallow regparm
5832   }
5833 
5834   void getDefaultFeatures(llvm::StringMap<bool> &Features) const override {
5835   }
5836   void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const {
5837     Builder.defineMacro("__le32__");
5838     Builder.defineMacro("__pnacl__");
5839   }
5840   void getTargetDefines(const LangOptions &Opts,
5841                         MacroBuilder &Builder) const override {
5842     getArchDefines(Opts, Builder);
5843   }
5844   bool hasFeature(StringRef Feature) const override {
5845     return Feature == "pnacl";
5846   }
5847   void getTargetBuiltins(const Builtin::Info *&Records,
5848                          unsigned &NumRecords) const override {
5849   }
5850   BuiltinVaListKind getBuiltinVaListKind() const override {
5851     return TargetInfo::PNaClABIBuiltinVaList;
5852   }
5853   void getGCCRegNames(const char * const *&Names,
5854                       unsigned &NumNames) const override;
5855   void getGCCRegAliases(const GCCRegAlias *&Aliases,
5856                         unsigned &NumAliases) const override;
5857   bool validateAsmConstraint(const char *&Name,
5858                              TargetInfo::ConstraintInfo &Info) const override {
5859     return false;
5860   }
5861 
5862   const char *getClobbers() const override {
5863     return "";
5864   }
5865 };
5866 
5867 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names,
5868                                      unsigned &NumNames) const {
5869   Names = nullptr;
5870   NumNames = 0;
5871 }
5872 
5873 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases,
5874                                        unsigned &NumAliases) const {
5875   Aliases = nullptr;
5876   NumAliases = 0;
5877 }
5878 } // end anonymous namespace.
5879 
5880 namespace {
5881   static const unsigned SPIRAddrSpaceMap[] = {
5882     1,    // opencl_global
5883     3,    // opencl_local
5884     2,    // opencl_constant
5885     0,    // cuda_device
5886     0,    // cuda_constant
5887     0     // cuda_shared
5888   };
5889   class SPIRTargetInfo : public TargetInfo {
5890   public:
5891     SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5892       assert(getTriple().getOS() == llvm::Triple::UnknownOS &&
5893         "SPIR target must use unknown OS");
5894       assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment &&
5895         "SPIR target must use unknown environment type");
5896       BigEndian = false;
5897       TLSSupported = false;
5898       LongWidth = LongAlign = 64;
5899       AddrSpaceMap = &SPIRAddrSpaceMap;
5900       UseAddrSpaceMapMangling = true;
5901       // Define available target features
5902       // These must be defined in sorted order!
5903       NoAsmVariants = true;
5904     }
5905     void getTargetDefines(const LangOptions &Opts,
5906                           MacroBuilder &Builder) const override {
5907       DefineStd(Builder, "SPIR", Opts);
5908     }
5909     bool hasFeature(StringRef Feature) const override {
5910       return Feature == "spir";
5911     }
5912 
5913     void getTargetBuiltins(const Builtin::Info *&Records,
5914                            unsigned &NumRecords) const override {}
5915     const char *getClobbers() const override {
5916       return "";
5917     }
5918     void getGCCRegNames(const char * const *&Names,
5919                         unsigned &NumNames) const override {}
5920     bool validateAsmConstraint(const char *&Name,
5921                                TargetInfo::ConstraintInfo &info) const override {
5922       return true;
5923     }
5924     void getGCCRegAliases(const GCCRegAlias *&Aliases,
5925                           unsigned &NumAliases) const override {}
5926     BuiltinVaListKind getBuiltinVaListKind() const override {
5927       return TargetInfo::VoidPtrBuiltinVaList;
5928     }
5929   };
5930 
5931 
5932   class SPIR32TargetInfo : public SPIRTargetInfo {
5933   public:
5934     SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5935       PointerWidth = PointerAlign = 32;
5936       SizeType     = TargetInfo::UnsignedInt;
5937       PtrDiffType = IntPtrType = TargetInfo::SignedInt;
5938       DescriptionString
5939         = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-"
5940           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
5941     }
5942     void getTargetDefines(const LangOptions &Opts,
5943                           MacroBuilder &Builder) const override {
5944       DefineStd(Builder, "SPIR32", Opts);
5945     }
5946   };
5947 
5948   class SPIR64TargetInfo : public SPIRTargetInfo {
5949   public:
5950     SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) {
5951       PointerWidth = PointerAlign = 64;
5952       SizeType     = TargetInfo::UnsignedLong;
5953       PtrDiffType = IntPtrType = TargetInfo::SignedLong;
5954       DescriptionString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-"
5955                           "v96:128-v192:256-v256:256-v512:512-v1024:1024";
5956     }
5957     void getTargetDefines(const LangOptions &Opts,
5958                           MacroBuilder &Builder) const override {
5959       DefineStd(Builder, "SPIR64", Opts);
5960     }
5961   };
5962 }
5963 
5964 namespace {
5965 class XCoreTargetInfo : public TargetInfo {
5966   static const Builtin::Info BuiltinInfo[];
5967 public:
5968   XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {
5969     BigEndian = false;
5970     NoAsmVariants = true;
5971     LongLongAlign = 32;
5972     SuitableAlign = 32;
5973     DoubleAlign = LongDoubleAlign = 32;
5974     SizeType = UnsignedInt;
5975     PtrDiffType = SignedInt;
5976     IntPtrType = SignedInt;
5977     WCharType = UnsignedChar;
5978     WIntType = UnsignedInt;
5979     UseZeroLengthBitfieldAlignment = true;
5980     DescriptionString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32"
5981                         "-f64:32-a:0:32-n32";
5982   }
5983   void getTargetDefines(const LangOptions &Opts,
5984                         MacroBuilder &Builder) const override {
5985     Builder.defineMacro("__XS1B__");
5986   }
5987   void getTargetBuiltins(const Builtin::Info *&Records,
5988                          unsigned &NumRecords) const override {
5989     Records = BuiltinInfo;
5990     NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin;
5991   }
5992   BuiltinVaListKind getBuiltinVaListKind() const override {
5993     return TargetInfo::VoidPtrBuiltinVaList;
5994   }
5995   const char *getClobbers() const override {
5996     return "";
5997   }
5998   void getGCCRegNames(const char * const *&Names,
5999                       unsigned &NumNames) const override {
6000     static const char * const GCCRegNames[] = {
6001       "r0",   "r1",   "r2",   "r3",   "r4",   "r5",   "r6",   "r7",
6002       "r8",   "r9",   "r10",  "r11",  "cp",   "dp",   "sp",   "lr"
6003     };
6004     Names = GCCRegNames;
6005     NumNames = llvm::array_lengthof(GCCRegNames);
6006   }
6007   void getGCCRegAliases(const GCCRegAlias *&Aliases,
6008                         unsigned &NumAliases) const override {
6009     Aliases = nullptr;
6010     NumAliases = 0;
6011   }
6012   bool validateAsmConstraint(const char *&Name,
6013                              TargetInfo::ConstraintInfo &Info) const override {
6014     return false;
6015   }
6016   int getEHDataRegisterNumber(unsigned RegNo) const override {
6017     // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
6018     return (RegNo < 2)? RegNo : -1;
6019   }
6020 };
6021 
6022 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = {
6023 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES },
6024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\
6025                                               ALL_LANGUAGES },
6026 #include "clang/Basic/BuiltinsXCore.def"
6027 };
6028 } // end anonymous namespace.
6029 
6030 
6031 //===----------------------------------------------------------------------===//
6032 // Driver code
6033 //===----------------------------------------------------------------------===//
6034 
6035 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) {
6036   llvm::Triple::OSType os = Triple.getOS();
6037 
6038   switch (Triple.getArch()) {
6039   default:
6040     return nullptr;
6041 
6042   case llvm::Triple::xcore:
6043     return new XCoreTargetInfo(Triple);
6044 
6045   case llvm::Triple::hexagon:
6046     return new HexagonTargetInfo(Triple);
6047 
6048   case llvm::Triple::aarch64:
6049     if (Triple.isOSDarwin())
6050       return new DarwinAArch64TargetInfo(Triple);
6051 
6052     switch (os) {
6053     case llvm::Triple::Linux:
6054       return new LinuxTargetInfo<AArch64leTargetInfo>(Triple);
6055     case llvm::Triple::NetBSD:
6056       return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple);
6057     default:
6058       return new AArch64leTargetInfo(Triple);
6059     }
6060 
6061   case llvm::Triple::aarch64_be:
6062     switch (os) {
6063     case llvm::Triple::Linux:
6064       return new LinuxTargetInfo<AArch64beTargetInfo>(Triple);
6065     case llvm::Triple::NetBSD:
6066       return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple);
6067     default:
6068       return new AArch64beTargetInfo(Triple);
6069     }
6070 
6071   case llvm::Triple::arm:
6072   case llvm::Triple::thumb:
6073     if (Triple.isOSBinFormatMachO())
6074       return new DarwinARMTargetInfo(Triple);
6075 
6076     switch (os) {
6077     case llvm::Triple::Linux:
6078       return new LinuxTargetInfo<ARMleTargetInfo>(Triple);
6079     case llvm::Triple::FreeBSD:
6080       return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple);
6081     case llvm::Triple::NetBSD:
6082       return new NetBSDTargetInfo<ARMleTargetInfo>(Triple);
6083     case llvm::Triple::OpenBSD:
6084       return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple);
6085     case llvm::Triple::Bitrig:
6086       return new BitrigTargetInfo<ARMleTargetInfo>(Triple);
6087     case llvm::Triple::RTEMS:
6088       return new RTEMSTargetInfo<ARMleTargetInfo>(Triple);
6089     case llvm::Triple::NaCl:
6090       return new NaClTargetInfo<ARMleTargetInfo>(Triple);
6091     case llvm::Triple::Win32:
6092       switch (Triple.getEnvironment()) {
6093       default:
6094         return new ARMleTargetInfo(Triple);
6095       case llvm::Triple::Itanium:
6096         return new ItaniumWindowsARMleTargetInfo(Triple);
6097       case llvm::Triple::MSVC:
6098         return new MicrosoftARMleTargetInfo(Triple);
6099       }
6100     default:
6101       return new ARMleTargetInfo(Triple);
6102     }
6103 
6104   case llvm::Triple::armeb:
6105   case llvm::Triple::thumbeb:
6106     if (Triple.isOSDarwin())
6107       return new DarwinARMTargetInfo(Triple);
6108 
6109     switch (os) {
6110     case llvm::Triple::Linux:
6111       return new LinuxTargetInfo<ARMbeTargetInfo>(Triple);
6112     case llvm::Triple::FreeBSD:
6113       return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple);
6114     case llvm::Triple::NetBSD:
6115       return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple);
6116     case llvm::Triple::OpenBSD:
6117       return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple);
6118     case llvm::Triple::Bitrig:
6119       return new BitrigTargetInfo<ARMbeTargetInfo>(Triple);
6120     case llvm::Triple::RTEMS:
6121       return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple);
6122     case llvm::Triple::NaCl:
6123       return new NaClTargetInfo<ARMbeTargetInfo>(Triple);
6124     default:
6125       return new ARMbeTargetInfo(Triple);
6126     }
6127 
6128   case llvm::Triple::msp430:
6129     return new MSP430TargetInfo(Triple);
6130 
6131   case llvm::Triple::mips:
6132     switch (os) {
6133     case llvm::Triple::Linux:
6134       return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple);
6135     case llvm::Triple::RTEMS:
6136       return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple);
6137     case llvm::Triple::FreeBSD:
6138       return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6139     case llvm::Triple::NetBSD:
6140       return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple);
6141     default:
6142       return new Mips32EBTargetInfo(Triple);
6143     }
6144 
6145   case llvm::Triple::mipsel:
6146     switch (os) {
6147     case llvm::Triple::Linux:
6148       return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple);
6149     case llvm::Triple::RTEMS:
6150       return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple);
6151     case llvm::Triple::FreeBSD:
6152       return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6153     case llvm::Triple::NetBSD:
6154       return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple);
6155     case llvm::Triple::NaCl:
6156       return new NaClTargetInfo<Mips32ELTargetInfo>(Triple);
6157     default:
6158       return new Mips32ELTargetInfo(Triple);
6159     }
6160 
6161   case llvm::Triple::mips64:
6162     switch (os) {
6163     case llvm::Triple::Linux:
6164       return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple);
6165     case llvm::Triple::RTEMS:
6166       return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple);
6167     case llvm::Triple::FreeBSD:
6168       return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6169     case llvm::Triple::NetBSD:
6170       return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6171     case llvm::Triple::OpenBSD:
6172       return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple);
6173     default:
6174       return new Mips64EBTargetInfo(Triple);
6175     }
6176 
6177   case llvm::Triple::mips64el:
6178     switch (os) {
6179     case llvm::Triple::Linux:
6180       return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple);
6181     case llvm::Triple::RTEMS:
6182       return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple);
6183     case llvm::Triple::FreeBSD:
6184       return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6185     case llvm::Triple::NetBSD:
6186       return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6187     case llvm::Triple::OpenBSD:
6188       return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple);
6189     default:
6190       return new Mips64ELTargetInfo(Triple);
6191     }
6192 
6193   case llvm::Triple::le32:
6194     switch (os) {
6195       case llvm::Triple::NaCl:
6196         return new NaClTargetInfo<PNaClTargetInfo>(Triple);
6197       default:
6198         return nullptr;
6199     }
6200 
6201   case llvm::Triple::ppc:
6202     if (Triple.isOSDarwin())
6203       return new DarwinPPC32TargetInfo(Triple);
6204     switch (os) {
6205     case llvm::Triple::Linux:
6206       return new LinuxTargetInfo<PPC32TargetInfo>(Triple);
6207     case llvm::Triple::FreeBSD:
6208       return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple);
6209     case llvm::Triple::NetBSD:
6210       return new NetBSDTargetInfo<PPC32TargetInfo>(Triple);
6211     case llvm::Triple::OpenBSD:
6212       return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple);
6213     case llvm::Triple::RTEMS:
6214       return new RTEMSTargetInfo<PPC32TargetInfo>(Triple);
6215     default:
6216       return new PPC32TargetInfo(Triple);
6217     }
6218 
6219   case llvm::Triple::ppc64:
6220     if (Triple.isOSDarwin())
6221       return new DarwinPPC64TargetInfo(Triple);
6222     switch (os) {
6223     case llvm::Triple::Linux:
6224       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6225     case llvm::Triple::Lv2:
6226       return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple);
6227     case llvm::Triple::FreeBSD:
6228       return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple);
6229     case llvm::Triple::NetBSD:
6230       return new NetBSDTargetInfo<PPC64TargetInfo>(Triple);
6231     default:
6232       return new PPC64TargetInfo(Triple);
6233     }
6234 
6235   case llvm::Triple::ppc64le:
6236     switch (os) {
6237     case llvm::Triple::Linux:
6238       return new LinuxTargetInfo<PPC64TargetInfo>(Triple);
6239     default:
6240       return new PPC64TargetInfo(Triple);
6241     }
6242 
6243   case llvm::Triple::nvptx:
6244     return new NVPTX32TargetInfo(Triple);
6245   case llvm::Triple::nvptx64:
6246     return new NVPTX64TargetInfo(Triple);
6247 
6248   case llvm::Triple::r600:
6249     return new R600TargetInfo(Triple);
6250 
6251   case llvm::Triple::sparc:
6252     switch (os) {
6253     case llvm::Triple::Linux:
6254       return new LinuxTargetInfo<SparcV8TargetInfo>(Triple);
6255     case llvm::Triple::AuroraUX:
6256       return new AuroraUXSparcV8TargetInfo(Triple);
6257     case llvm::Triple::Solaris:
6258       return new SolarisSparcV8TargetInfo(Triple);
6259     case llvm::Triple::NetBSD:
6260       return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple);
6261     case llvm::Triple::OpenBSD:
6262       return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple);
6263     case llvm::Triple::RTEMS:
6264       return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple);
6265     default:
6266       return new SparcV8TargetInfo(Triple);
6267     }
6268 
6269   case llvm::Triple::sparcv9:
6270     switch (os) {
6271     case llvm::Triple::Linux:
6272       return new LinuxTargetInfo<SparcV9TargetInfo>(Triple);
6273     case llvm::Triple::AuroraUX:
6274       return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple);
6275     case llvm::Triple::Solaris:
6276       return new SolarisTargetInfo<SparcV9TargetInfo>(Triple);
6277     case llvm::Triple::NetBSD:
6278       return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple);
6279     case llvm::Triple::OpenBSD:
6280       return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple);
6281     case llvm::Triple::FreeBSD:
6282       return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple);
6283     default:
6284       return new SparcV9TargetInfo(Triple);
6285     }
6286 
6287   case llvm::Triple::systemz:
6288     switch (os) {
6289     case llvm::Triple::Linux:
6290       return new LinuxTargetInfo<SystemZTargetInfo>(Triple);
6291     default:
6292       return new SystemZTargetInfo(Triple);
6293     }
6294 
6295   case llvm::Triple::tce:
6296     return new TCETargetInfo(Triple);
6297 
6298   case llvm::Triple::x86:
6299     if (Triple.isOSDarwin())
6300       return new DarwinI386TargetInfo(Triple);
6301 
6302     switch (os) {
6303     case llvm::Triple::AuroraUX:
6304       return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple);
6305     case llvm::Triple::Linux:
6306       return new LinuxTargetInfo<X86_32TargetInfo>(Triple);
6307     case llvm::Triple::DragonFly:
6308       return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple);
6309     case llvm::Triple::NetBSD:
6310       return new NetBSDI386TargetInfo(Triple);
6311     case llvm::Triple::OpenBSD:
6312       return new OpenBSDI386TargetInfo(Triple);
6313     case llvm::Triple::Bitrig:
6314       return new BitrigI386TargetInfo(Triple);
6315     case llvm::Triple::FreeBSD:
6316       return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6317     case llvm::Triple::KFreeBSD:
6318       return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple);
6319     case llvm::Triple::Minix:
6320       return new MinixTargetInfo<X86_32TargetInfo>(Triple);
6321     case llvm::Triple::Solaris:
6322       return new SolarisTargetInfo<X86_32TargetInfo>(Triple);
6323     case llvm::Triple::Win32: {
6324       switch (Triple.getEnvironment()) {
6325       default:
6326         return new X86_32TargetInfo(Triple);
6327       case llvm::Triple::Cygnus:
6328         return new CygwinX86_32TargetInfo(Triple);
6329       case llvm::Triple::GNU:
6330         return new MinGWX86_32TargetInfo(Triple);
6331       case llvm::Triple::Itanium:
6332       case llvm::Triple::MSVC:
6333         return new MicrosoftX86_32TargetInfo(Triple);
6334       }
6335     }
6336     case llvm::Triple::Haiku:
6337       return new HaikuX86_32TargetInfo(Triple);
6338     case llvm::Triple::RTEMS:
6339       return new RTEMSX86_32TargetInfo(Triple);
6340     case llvm::Triple::NaCl:
6341       return new NaClTargetInfo<X86_32TargetInfo>(Triple);
6342     default:
6343       return new X86_32TargetInfo(Triple);
6344     }
6345 
6346   case llvm::Triple::x86_64:
6347     if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO())
6348       return new DarwinX86_64TargetInfo(Triple);
6349 
6350     switch (os) {
6351     case llvm::Triple::AuroraUX:
6352       return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple);
6353     case llvm::Triple::Linux:
6354       return new LinuxTargetInfo<X86_64TargetInfo>(Triple);
6355     case llvm::Triple::DragonFly:
6356       return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple);
6357     case llvm::Triple::NetBSD:
6358       return new NetBSDTargetInfo<X86_64TargetInfo>(Triple);
6359     case llvm::Triple::OpenBSD:
6360       return new OpenBSDX86_64TargetInfo(Triple);
6361     case llvm::Triple::Bitrig:
6362       return new BitrigX86_64TargetInfo(Triple);
6363     case llvm::Triple::FreeBSD:
6364       return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6365     case llvm::Triple::KFreeBSD:
6366       return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple);
6367     case llvm::Triple::Solaris:
6368       return new SolarisTargetInfo<X86_64TargetInfo>(Triple);
6369     case llvm::Triple::Win32: {
6370       switch (Triple.getEnvironment()) {
6371       default:
6372         return new X86_64TargetInfo(Triple);
6373       case llvm::Triple::GNU:
6374         return new MinGWX86_64TargetInfo(Triple);
6375       case llvm::Triple::MSVC:
6376         return new MicrosoftX86_64TargetInfo(Triple);
6377       }
6378     }
6379     case llvm::Triple::NaCl:
6380       return new NaClTargetInfo<X86_64TargetInfo>(Triple);
6381     default:
6382       return new X86_64TargetInfo(Triple);
6383     }
6384 
6385     case llvm::Triple::spir: {
6386       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6387           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6388         return nullptr;
6389       return new SPIR32TargetInfo(Triple);
6390     }
6391     case llvm::Triple::spir64: {
6392       if (Triple.getOS() != llvm::Triple::UnknownOS ||
6393           Triple.getEnvironment() != llvm::Triple::UnknownEnvironment)
6394         return nullptr;
6395       return new SPIR64TargetInfo(Triple);
6396     }
6397   }
6398 }
6399 
6400 /// CreateTargetInfo - Return the target info object for the specified target
6401 /// triple.
6402 TargetInfo *
6403 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags,
6404                              const std::shared_ptr<TargetOptions> &Opts) {
6405   llvm::Triple Triple(Opts->Triple);
6406 
6407   // Construct the target
6408   std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple));
6409   if (!Target) {
6410     Diags.Report(diag::err_target_unknown_triple) << Triple.str();
6411     return nullptr;
6412   }
6413   Target->TargetOpts = Opts;
6414 
6415   // Set the target CPU if specified.
6416   if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) {
6417     Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU;
6418     return nullptr;
6419   }
6420 
6421   // Set the target ABI if specified.
6422   if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) {
6423     Diags.Report(diag::err_target_unknown_abi) << Opts->ABI;
6424     return nullptr;
6425   }
6426 
6427   // Set the fp math unit.
6428   if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) {
6429     Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath;
6430     return nullptr;
6431   }
6432 
6433   // Compute the default target features, we need the target to handle this
6434   // because features may have dependencies on one another.
6435   llvm::StringMap<bool> Features;
6436   Target->getDefaultFeatures(Features);
6437 
6438   // Apply the user specified deltas.
6439   for (unsigned I = 0, N = Opts->FeaturesAsWritten.size();
6440        I < N; ++I) {
6441     const char *Name = Opts->FeaturesAsWritten[I].c_str();
6442     // Apply the feature via the target.
6443     bool Enabled = Name[0] == '+';
6444     Target->setFeatureEnabled(Features, Name + 1, Enabled);
6445   }
6446 
6447   // Add the features to the compile options.
6448   //
6449   // FIXME: If we are completely confident that we have the right set, we only
6450   // need to pass the minuses.
6451   Opts->Features.clear();
6452   for (llvm::StringMap<bool>::const_iterator it = Features.begin(),
6453          ie = Features.end(); it != ie; ++it)
6454     Opts->Features.push_back((it->second ? "+" : "-") + it->first().str());
6455   if (!Target->handleTargetFeatures(Opts->Features, Diags))
6456     return nullptr;
6457 
6458   return Target.release();
6459 }
6460