1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/Builtins.h" 16 #include "clang/Basic/Cuda.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetInfo.h" 22 #include "clang/Basic/TargetOptions.h" 23 #include "clang/Basic/Version.h" 24 #include "clang/Frontend/CodeGenOptions.h" 25 #include "llvm/ADT/APFloat.h" 26 #include "llvm/ADT/STLExtras.h" 27 #include "llvm/ADT/StringExtras.h" 28 #include "llvm/ADT/StringRef.h" 29 #include "llvm/ADT/StringSwitch.h" 30 #include "llvm/ADT/Triple.h" 31 #include "llvm/MC/MCSectionMachO.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/TargetParser.h" 34 #include <algorithm> 35 #include <memory> 36 37 using namespace clang; 38 39 //===----------------------------------------------------------------------===// 40 // Common code shared among targets. 41 //===----------------------------------------------------------------------===// 42 43 /// DefineStd - Define a macro name and standard variants. For example if 44 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 45 /// when in GNU mode. 46 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 47 const LangOptions &Opts) { 48 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 49 50 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 51 // in the user's namespace. 52 if (Opts.GNUMode) 53 Builder.defineMacro(MacroName); 54 55 // Define __unix. 56 Builder.defineMacro("__" + MacroName); 57 58 // Define __unix__. 59 Builder.defineMacro("__" + MacroName + "__"); 60 } 61 62 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 63 bool Tuning = true) { 64 Builder.defineMacro("__" + CPUName); 65 Builder.defineMacro("__" + CPUName + "__"); 66 if (Tuning) 67 Builder.defineMacro("__tune_" + CPUName + "__"); 68 } 69 70 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 71 const TargetOptions &Opts); 72 73 //===----------------------------------------------------------------------===// 74 // Defines specific to certain operating systems. 75 //===----------------------------------------------------------------------===// 76 77 namespace { 78 template<typename TgtInfo> 79 class OSTargetInfo : public TgtInfo { 80 protected: 81 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 82 MacroBuilder &Builder) const=0; 83 public: 84 OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 85 : TgtInfo(Triple, Opts) {} 86 void getTargetDefines(const LangOptions &Opts, 87 MacroBuilder &Builder) const override { 88 TgtInfo::getTargetDefines(Opts, Builder); 89 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 90 } 91 92 }; 93 94 // CloudABI Target 95 template <typename Target> 96 class CloudABITargetInfo : public OSTargetInfo<Target> { 97 protected: 98 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 99 MacroBuilder &Builder) const override { 100 Builder.defineMacro("__CloudABI__"); 101 Builder.defineMacro("__ELF__"); 102 103 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 104 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 105 Builder.defineMacro("__STDC_UTF_16__"); 106 Builder.defineMacro("__STDC_UTF_32__"); 107 } 108 109 public: 110 CloudABITargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 111 : OSTargetInfo<Target>(Triple, Opts) {} 112 }; 113 114 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 115 const llvm::Triple &Triple, 116 StringRef &PlatformName, 117 VersionTuple &PlatformMinVersion) { 118 Builder.defineMacro("__APPLE_CC__", "6000"); 119 Builder.defineMacro("__APPLE__"); 120 Builder.defineMacro("__STDC_NO_THREADS__"); 121 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 122 // AddressSanitizer doesn't play well with source fortification, which is on 123 // by default on Darwin. 124 if (Opts.Sanitize.has(SanitizerKind::Address)) 125 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 126 127 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 128 if (!Opts.ObjC1) { 129 // __weak is always defined, for use in blocks and with objc pointers. 130 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 131 Builder.defineMacro("__strong", ""); 132 Builder.defineMacro("__unsafe_unretained", ""); 133 } 134 135 if (Opts.Static) 136 Builder.defineMacro("__STATIC__"); 137 else 138 Builder.defineMacro("__DYNAMIC__"); 139 140 if (Opts.POSIXThreads) 141 Builder.defineMacro("_REENTRANT"); 142 143 // Get the platform type and version number from the triple. 144 unsigned Maj, Min, Rev; 145 if (Triple.isMacOSX()) { 146 Triple.getMacOSXVersion(Maj, Min, Rev); 147 PlatformName = "macos"; 148 } else { 149 Triple.getOSVersion(Maj, Min, Rev); 150 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 151 } 152 153 // If -target arch-pc-win32-macho option specified, we're 154 // generating code for Win32 ABI. No need to emit 155 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 156 if (PlatformName == "win32") { 157 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 158 return; 159 } 160 161 // Set the appropriate OS version define. 162 if (Triple.isiOS()) { 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[7]; 165 if (Maj < 10) { 166 Str[0] = '0' + Maj; 167 Str[1] = '0' + (Min / 10); 168 Str[2] = '0' + (Min % 10); 169 Str[3] = '0' + (Rev / 10); 170 Str[4] = '0' + (Rev % 10); 171 Str[5] = '\0'; 172 } else { 173 // Handle versions >= 10. 174 Str[0] = '0' + (Maj / 10); 175 Str[1] = '0' + (Maj % 10); 176 Str[2] = '0' + (Min / 10); 177 Str[3] = '0' + (Min % 10); 178 Str[4] = '0' + (Rev / 10); 179 Str[5] = '0' + (Rev % 10); 180 Str[6] = '\0'; 181 } 182 if (Triple.isTvOS()) 183 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 184 else 185 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 186 Str); 187 188 } else if (Triple.isWatchOS()) { 189 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 190 char Str[6]; 191 Str[0] = '0' + Maj; 192 Str[1] = '0' + (Min / 10); 193 Str[2] = '0' + (Min % 10); 194 Str[3] = '0' + (Rev / 10); 195 Str[4] = '0' + (Rev % 10); 196 Str[5] = '\0'; 197 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 198 } else if (Triple.isMacOSX()) { 199 // Note that the Driver allows versions which aren't representable in the 200 // define (because we only get a single digit for the minor and micro 201 // revision numbers). So, we limit them to the maximum representable 202 // version. 203 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 204 char Str[7]; 205 if (Maj < 10 || (Maj == 10 && Min < 10)) { 206 Str[0] = '0' + (Maj / 10); 207 Str[1] = '0' + (Maj % 10); 208 Str[2] = '0' + std::min(Min, 9U); 209 Str[3] = '0' + std::min(Rev, 9U); 210 Str[4] = '\0'; 211 } else { 212 // Handle versions > 10.9. 213 Str[0] = '0' + (Maj / 10); 214 Str[1] = '0' + (Maj % 10); 215 Str[2] = '0' + (Min / 10); 216 Str[3] = '0' + (Min % 10); 217 Str[4] = '0' + (Rev / 10); 218 Str[5] = '0' + (Rev % 10); 219 Str[6] = '\0'; 220 } 221 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 222 } 223 224 // Tell users about the kernel if there is one. 225 if (Triple.isOSDarwin()) 226 Builder.defineMacro("__MACH__"); 227 228 // The Watch ABI uses Dwarf EH. 229 if(Triple.isWatchABI()) 230 Builder.defineMacro("__ARM_DWARF_EH__"); 231 232 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 233 } 234 235 template<typename Target> 236 class DarwinTargetInfo : public OSTargetInfo<Target> { 237 protected: 238 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 239 MacroBuilder &Builder) const override { 240 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 241 this->PlatformMinVersion); 242 } 243 244 public: 245 DarwinTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 246 : OSTargetInfo<Target>(Triple, Opts) { 247 // By default, no TLS, and we whitelist permitted architecture/OS 248 // combinations. 249 this->TLSSupported = false; 250 251 if (Triple.isMacOSX()) 252 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 253 else if (Triple.isiOS()) { 254 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 255 if (Triple.getArch() == llvm::Triple::x86_64 || 256 Triple.getArch() == llvm::Triple::aarch64) 257 this->TLSSupported = !Triple.isOSVersionLT(8); 258 else if (Triple.getArch() == llvm::Triple::x86 || 259 Triple.getArch() == llvm::Triple::arm || 260 Triple.getArch() == llvm::Triple::thumb) 261 this->TLSSupported = !Triple.isOSVersionLT(9); 262 } else if (Triple.isWatchOS()) 263 this->TLSSupported = !Triple.isOSVersionLT(2); 264 265 this->MCountName = "\01mcount"; 266 } 267 268 std::string isValidSectionSpecifier(StringRef SR) const override { 269 // Let MCSectionMachO validate this. 270 StringRef Segment, Section; 271 unsigned TAA, StubSize; 272 bool HasTAA; 273 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 274 TAA, HasTAA, StubSize); 275 } 276 277 const char *getStaticInitSectionSpecifier() const override { 278 // FIXME: We should return 0 when building kexts. 279 return "__TEXT,__StaticInit,regular,pure_instructions"; 280 } 281 282 /// Darwin does not support protected visibility. Darwin's "default" 283 /// is very similar to ELF's "protected"; Darwin requires a "weak" 284 /// attribute on declarations that can be dynamically replaced. 285 bool hasProtectedVisibility() const override { 286 return false; 287 } 288 289 unsigned getExnObjectAlignment() const override { 290 // The alignment of an exception object is 8-bytes for darwin since 291 // libc++abi doesn't declare _Unwind_Exception with __attribute__((aligned)) 292 // and therefore doesn't guarantee 16-byte alignment. 293 return 64; 294 } 295 }; 296 297 298 // DragonFlyBSD Target 299 template<typename Target> 300 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 301 protected: 302 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 303 MacroBuilder &Builder) const override { 304 // DragonFly defines; list based off of gcc output 305 Builder.defineMacro("__DragonFly__"); 306 Builder.defineMacro("__DragonFly_cc_version", "100001"); 307 Builder.defineMacro("__ELF__"); 308 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 309 Builder.defineMacro("__tune_i386__"); 310 DefineStd(Builder, "unix", Opts); 311 } 312 public: 313 DragonFlyBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 314 : OSTargetInfo<Target>(Triple, Opts) { 315 switch (Triple.getArch()) { 316 default: 317 case llvm::Triple::x86: 318 case llvm::Triple::x86_64: 319 this->MCountName = ".mcount"; 320 break; 321 } 322 } 323 }; 324 325 #ifndef FREEBSD_CC_VERSION 326 #define FREEBSD_CC_VERSION 0U 327 #endif 328 329 // FreeBSD Target 330 template<typename Target> 331 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 332 protected: 333 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 334 MacroBuilder &Builder) const override { 335 // FreeBSD defines; list based off of gcc output 336 337 unsigned Release = Triple.getOSMajorVersion(); 338 if (Release == 0U) 339 Release = 8U; 340 unsigned CCVersion = FREEBSD_CC_VERSION; 341 if (CCVersion == 0U) 342 CCVersion = Release * 100000U + 1U; 343 344 Builder.defineMacro("__FreeBSD__", Twine(Release)); 345 Builder.defineMacro("__FreeBSD_cc_version", Twine(CCVersion)); 346 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 347 DefineStd(Builder, "unix", Opts); 348 Builder.defineMacro("__ELF__"); 349 350 // On FreeBSD, wchar_t contains the number of the code point as 351 // used by the character set of the locale. These character sets are 352 // not necessarily a superset of ASCII. 353 // 354 // FIXME: This is wrong; the macro refers to the numerical values 355 // of wchar_t *literals*, which are not locale-dependent. However, 356 // FreeBSD systems apparently depend on us getting this wrong, and 357 // setting this to 1 is conforming even if all the basic source 358 // character literals have the same encoding as char and wchar_t. 359 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 360 } 361 public: 362 FreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 363 : OSTargetInfo<Target>(Triple, Opts) { 364 switch (Triple.getArch()) { 365 default: 366 case llvm::Triple::x86: 367 case llvm::Triple::x86_64: 368 this->MCountName = ".mcount"; 369 break; 370 case llvm::Triple::mips: 371 case llvm::Triple::mipsel: 372 case llvm::Triple::ppc: 373 case llvm::Triple::ppc64: 374 case llvm::Triple::ppc64le: 375 this->MCountName = "_mcount"; 376 break; 377 case llvm::Triple::arm: 378 this->MCountName = "__mcount"; 379 break; 380 } 381 } 382 }; 383 384 // GNU/kFreeBSD Target 385 template<typename Target> 386 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const override { 390 // GNU/kFreeBSD defines; list based off of gcc output 391 392 DefineStd(Builder, "unix", Opts); 393 Builder.defineMacro("__FreeBSD_kernel__"); 394 Builder.defineMacro("__GLIBC__"); 395 Builder.defineMacro("__ELF__"); 396 if (Opts.POSIXThreads) 397 Builder.defineMacro("_REENTRANT"); 398 if (Opts.CPlusPlus) 399 Builder.defineMacro("_GNU_SOURCE"); 400 } 401 public: 402 KFreeBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 403 : OSTargetInfo<Target>(Triple, Opts) {} 404 }; 405 406 // Haiku Target 407 template<typename Target> 408 class HaikuTargetInfo : public OSTargetInfo<Target> { 409 protected: 410 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 411 MacroBuilder &Builder) const override { 412 // Haiku defines; list based off of gcc output 413 Builder.defineMacro("__HAIKU__"); 414 Builder.defineMacro("__ELF__"); 415 DefineStd(Builder, "unix", Opts); 416 } 417 public: 418 HaikuTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 419 : OSTargetInfo<Target>(Triple, Opts) { 420 this->SizeType = TargetInfo::UnsignedLong; 421 this->IntPtrType = TargetInfo::SignedLong; 422 this->PtrDiffType = TargetInfo::SignedLong; 423 this->ProcessIDType = TargetInfo::SignedLong; 424 this->TLSSupported = false; 425 426 } 427 }; 428 429 // Minix Target 430 template<typename Target> 431 class MinixTargetInfo : public OSTargetInfo<Target> { 432 protected: 433 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 434 MacroBuilder &Builder) const override { 435 // Minix defines 436 437 Builder.defineMacro("__minix", "3"); 438 Builder.defineMacro("_EM_WSIZE", "4"); 439 Builder.defineMacro("_EM_PSIZE", "4"); 440 Builder.defineMacro("_EM_SSIZE", "2"); 441 Builder.defineMacro("_EM_LSIZE", "4"); 442 Builder.defineMacro("_EM_FSIZE", "4"); 443 Builder.defineMacro("_EM_DSIZE", "8"); 444 Builder.defineMacro("__ELF__"); 445 DefineStd(Builder, "unix", Opts); 446 } 447 public: 448 MinixTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 449 : OSTargetInfo<Target>(Triple, Opts) {} 450 }; 451 452 // Linux target 453 template<typename Target> 454 class LinuxTargetInfo : public OSTargetInfo<Target> { 455 protected: 456 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 457 MacroBuilder &Builder) const override { 458 // Linux defines; list based off of gcc output 459 DefineStd(Builder, "unix", Opts); 460 DefineStd(Builder, "linux", Opts); 461 Builder.defineMacro("__gnu_linux__"); 462 Builder.defineMacro("__ELF__"); 463 if (Triple.isAndroid()) { 464 Builder.defineMacro("__ANDROID__", "1"); 465 unsigned Maj, Min, Rev; 466 Triple.getEnvironmentVersion(Maj, Min, Rev); 467 this->PlatformName = "android"; 468 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 469 if (Maj) 470 Builder.defineMacro("__ANDROID_API__", Twine(Maj)); 471 } 472 if (Opts.POSIXThreads) 473 Builder.defineMacro("_REENTRANT"); 474 if (Opts.CPlusPlus) 475 Builder.defineMacro("_GNU_SOURCE"); 476 if (this->HasFloat128) 477 Builder.defineMacro("__FLOAT128__"); 478 } 479 public: 480 LinuxTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 481 : OSTargetInfo<Target>(Triple, Opts) { 482 this->WIntType = TargetInfo::UnsignedInt; 483 484 switch (Triple.getArch()) { 485 default: 486 break; 487 case llvm::Triple::ppc: 488 case llvm::Triple::ppc64: 489 case llvm::Triple::ppc64le: 490 this->MCountName = "_mcount"; 491 break; 492 case llvm::Triple::x86: 493 case llvm::Triple::x86_64: 494 case llvm::Triple::systemz: 495 this->HasFloat128 = true; 496 break; 497 } 498 } 499 500 const char *getStaticInitSectionSpecifier() const override { 501 return ".text.startup"; 502 } 503 }; 504 505 // NetBSD Target 506 template<typename Target> 507 class NetBSDTargetInfo : public OSTargetInfo<Target> { 508 protected: 509 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 510 MacroBuilder &Builder) const override { 511 // NetBSD defines; list based off of gcc output 512 Builder.defineMacro("__NetBSD__"); 513 Builder.defineMacro("__unix__"); 514 Builder.defineMacro("__ELF__"); 515 if (Opts.POSIXThreads) 516 Builder.defineMacro("_REENTRANT"); 517 518 switch (Triple.getArch()) { 519 default: 520 break; 521 case llvm::Triple::arm: 522 case llvm::Triple::armeb: 523 case llvm::Triple::thumb: 524 case llvm::Triple::thumbeb: 525 Builder.defineMacro("__ARM_DWARF_EH__"); 526 break; 527 } 528 } 529 public: 530 NetBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 531 : OSTargetInfo<Target>(Triple, Opts) { 532 this->MCountName = "_mcount"; 533 } 534 }; 535 536 // OpenBSD Target 537 template<typename Target> 538 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 539 protected: 540 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 541 MacroBuilder &Builder) const override { 542 // OpenBSD defines; list based off of gcc output 543 544 Builder.defineMacro("__OpenBSD__"); 545 DefineStd(Builder, "unix", Opts); 546 Builder.defineMacro("__ELF__"); 547 if (Opts.POSIXThreads) 548 Builder.defineMacro("_REENTRANT"); 549 if (this->HasFloat128) 550 Builder.defineMacro("__FLOAT128__"); 551 } 552 public: 553 OpenBSDTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 554 : OSTargetInfo<Target>(Triple, Opts) { 555 this->TLSSupported = false; 556 557 switch (Triple.getArch()) { 558 case llvm::Triple::x86: 559 case llvm::Triple::x86_64: 560 this->HasFloat128 = true; 561 // FALLTHROUGH 562 default: 563 this->MCountName = "__mcount"; 564 break; 565 case llvm::Triple::mips64: 566 case llvm::Triple::mips64el: 567 case llvm::Triple::ppc: 568 case llvm::Triple::sparcv9: 569 this->MCountName = "_mcount"; 570 break; 571 } 572 } 573 }; 574 575 // Bitrig Target 576 template<typename Target> 577 class BitrigTargetInfo : public OSTargetInfo<Target> { 578 protected: 579 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 580 MacroBuilder &Builder) const override { 581 // Bitrig defines; list based off of gcc output 582 583 Builder.defineMacro("__Bitrig__"); 584 DefineStd(Builder, "unix", Opts); 585 Builder.defineMacro("__ELF__"); 586 if (Opts.POSIXThreads) 587 Builder.defineMacro("_REENTRANT"); 588 589 switch (Triple.getArch()) { 590 default: 591 break; 592 case llvm::Triple::arm: 593 case llvm::Triple::armeb: 594 case llvm::Triple::thumb: 595 case llvm::Triple::thumbeb: 596 Builder.defineMacro("__ARM_DWARF_EH__"); 597 break; 598 } 599 } 600 public: 601 BitrigTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 602 : OSTargetInfo<Target>(Triple, Opts) { 603 this->MCountName = "__mcount"; 604 } 605 }; 606 607 // PSP Target 608 template<typename Target> 609 class PSPTargetInfo : public OSTargetInfo<Target> { 610 protected: 611 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 612 MacroBuilder &Builder) const override { 613 // PSP defines; list based on the output of the pspdev gcc toolchain. 614 Builder.defineMacro("PSP"); 615 Builder.defineMacro("_PSP"); 616 Builder.defineMacro("__psp__"); 617 Builder.defineMacro("__ELF__"); 618 } 619 public: 620 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) {} 621 }; 622 623 // PS3 PPU Target 624 template<typename Target> 625 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 626 protected: 627 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 628 MacroBuilder &Builder) const override { 629 // PS3 PPU defines. 630 Builder.defineMacro("__PPC__"); 631 Builder.defineMacro("__PPU__"); 632 Builder.defineMacro("__CELLOS_LV2__"); 633 Builder.defineMacro("__ELF__"); 634 Builder.defineMacro("__LP32__"); 635 Builder.defineMacro("_ARCH_PPC64"); 636 Builder.defineMacro("__powerpc64__"); 637 } 638 public: 639 PS3PPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 640 : OSTargetInfo<Target>(Triple, Opts) { 641 this->LongWidth = this->LongAlign = 32; 642 this->PointerWidth = this->PointerAlign = 32; 643 this->IntMaxType = TargetInfo::SignedLongLong; 644 this->Int64Type = TargetInfo::SignedLongLong; 645 this->SizeType = TargetInfo::UnsignedInt; 646 this->resetDataLayout("E-m:e-p:32:32-i64:64-n32:64"); 647 } 648 }; 649 650 template <typename Target> 651 class PS4OSTargetInfo : public OSTargetInfo<Target> { 652 protected: 653 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 654 MacroBuilder &Builder) const override { 655 Builder.defineMacro("__FreeBSD__", "9"); 656 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 657 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 658 DefineStd(Builder, "unix", Opts); 659 Builder.defineMacro("__ELF__"); 660 Builder.defineMacro("__ORBIS__"); 661 } 662 public: 663 PS4OSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 664 : OSTargetInfo<Target>(Triple, Opts) { 665 this->WCharType = this->UnsignedShort; 666 667 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 668 this->MaxTLSAlign = 256; 669 670 // On PS4, do not honor explicit bit field alignment, 671 // as in "__attribute__((aligned(2))) int b : 1;". 672 this->UseExplicitBitFieldAlignment = false; 673 674 switch (Triple.getArch()) { 675 default: 676 case llvm::Triple::x86_64: 677 this->MCountName = ".mcount"; 678 break; 679 } 680 } 681 }; 682 683 // Solaris target 684 template<typename Target> 685 class SolarisTargetInfo : public OSTargetInfo<Target> { 686 protected: 687 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 688 MacroBuilder &Builder) const override { 689 DefineStd(Builder, "sun", Opts); 690 DefineStd(Builder, "unix", Opts); 691 Builder.defineMacro("__ELF__"); 692 Builder.defineMacro("__svr4__"); 693 Builder.defineMacro("__SVR4"); 694 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 695 // newer, but to 500 for everything else. feature_test.h has a check to 696 // ensure that you are not using C99 with an old version of X/Open or C89 697 // with a new version. 698 if (Opts.C99) 699 Builder.defineMacro("_XOPEN_SOURCE", "600"); 700 else 701 Builder.defineMacro("_XOPEN_SOURCE", "500"); 702 if (Opts.CPlusPlus) 703 Builder.defineMacro("__C99FEATURES__"); 704 Builder.defineMacro("_LARGEFILE_SOURCE"); 705 Builder.defineMacro("_LARGEFILE64_SOURCE"); 706 Builder.defineMacro("__EXTENSIONS__"); 707 Builder.defineMacro("_REENTRANT"); 708 } 709 public: 710 SolarisTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 711 : OSTargetInfo<Target>(Triple, Opts) { 712 this->WCharType = this->SignedInt; 713 // FIXME: WIntType should be SignedLong 714 } 715 }; 716 717 // Windows target 718 template<typename Target> 719 class WindowsTargetInfo : public OSTargetInfo<Target> { 720 protected: 721 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 722 MacroBuilder &Builder) const override { 723 Builder.defineMacro("_WIN32"); 724 } 725 void getVisualStudioDefines(const LangOptions &Opts, 726 MacroBuilder &Builder) const { 727 if (Opts.CPlusPlus) { 728 if (Opts.RTTIData) 729 Builder.defineMacro("_CPPRTTI"); 730 731 if (Opts.CXXExceptions) 732 Builder.defineMacro("_CPPUNWIND"); 733 } 734 735 if (Opts.Bool) 736 Builder.defineMacro("__BOOL_DEFINED"); 737 738 if (!Opts.CharIsSigned) 739 Builder.defineMacro("_CHAR_UNSIGNED"); 740 741 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 742 // but it works for now. 743 if (Opts.POSIXThreads) 744 Builder.defineMacro("_MT"); 745 746 if (Opts.MSCompatibilityVersion) { 747 Builder.defineMacro("_MSC_VER", 748 Twine(Opts.MSCompatibilityVersion / 100000)); 749 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 750 // FIXME We cannot encode the revision information into 32-bits 751 Builder.defineMacro("_MSC_BUILD", Twine(1)); 752 753 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 754 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 755 756 if (Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) { 757 if (Opts.CPlusPlus1z) 758 Builder.defineMacro("_MSVC_LANG", "201403L"); 759 else if (Opts.CPlusPlus14) 760 Builder.defineMacro("_MSVC_LANG", "201402L"); 761 } 762 } 763 764 if (Opts.MicrosoftExt) { 765 Builder.defineMacro("_MSC_EXTENSIONS"); 766 767 if (Opts.CPlusPlus11) { 768 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 769 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 770 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 771 } 772 } 773 774 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 775 } 776 777 public: 778 WindowsTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 779 : OSTargetInfo<Target>(Triple, Opts) {} 780 }; 781 782 template <typename Target> 783 class NaClTargetInfo : public OSTargetInfo<Target> { 784 protected: 785 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 786 MacroBuilder &Builder) const override { 787 if (Opts.POSIXThreads) 788 Builder.defineMacro("_REENTRANT"); 789 if (Opts.CPlusPlus) 790 Builder.defineMacro("_GNU_SOURCE"); 791 792 DefineStd(Builder, "unix", Opts); 793 Builder.defineMacro("__ELF__"); 794 Builder.defineMacro("__native_client__"); 795 } 796 797 public: 798 NaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 799 : OSTargetInfo<Target>(Triple, Opts) { 800 this->LongAlign = 32; 801 this->LongWidth = 32; 802 this->PointerAlign = 32; 803 this->PointerWidth = 32; 804 this->IntMaxType = TargetInfo::SignedLongLong; 805 this->Int64Type = TargetInfo::SignedLongLong; 806 this->DoubleAlign = 64; 807 this->LongDoubleWidth = 64; 808 this->LongDoubleAlign = 64; 809 this->LongLongWidth = 64; 810 this->LongLongAlign = 64; 811 this->SizeType = TargetInfo::UnsignedInt; 812 this->PtrDiffType = TargetInfo::SignedInt; 813 this->IntPtrType = TargetInfo::SignedInt; 814 // RegParmMax is inherited from the underlying architecture. 815 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 816 if (Triple.getArch() == llvm::Triple::arm) { 817 // Handled in ARM's setABI(). 818 } else if (Triple.getArch() == llvm::Triple::x86) { 819 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32-S128"); 820 } else if (Triple.getArch() == llvm::Triple::x86_64) { 821 this->resetDataLayout("e-m:e-p:32:32-i64:64-n8:16:32:64-S128"); 822 } else if (Triple.getArch() == llvm::Triple::mipsel) { 823 // Handled on mips' setDataLayout. 824 } else { 825 assert(Triple.getArch() == llvm::Triple::le32); 826 this->resetDataLayout("e-p:32:32-i64:64"); 827 } 828 } 829 }; 830 831 // Fuchsia Target 832 template<typename Target> 833 class FuchsiaTargetInfo : public OSTargetInfo<Target> { 834 protected: 835 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 836 MacroBuilder &Builder) const override { 837 Builder.defineMacro("__Fuchsia__"); 838 Builder.defineMacro("__ELF__"); 839 if (Opts.POSIXThreads) 840 Builder.defineMacro("_REENTRANT"); 841 // Required by the libc++ locale support. 842 if (Opts.CPlusPlus) 843 Builder.defineMacro("_GNU_SOURCE"); 844 } 845 public: 846 FuchsiaTargetInfo(const llvm::Triple &Triple, 847 const TargetOptions &Opts) 848 : OSTargetInfo<Target>(Triple, Opts) { 849 this->MCountName = "__mcount"; 850 } 851 }; 852 853 // WebAssembly target 854 template <typename Target> 855 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 856 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 857 MacroBuilder &Builder) const final { 858 // A common platform macro. 859 if (Opts.POSIXThreads) 860 Builder.defineMacro("_REENTRANT"); 861 // Follow g++ convention and predefine _GNU_SOURCE for C++. 862 if (Opts.CPlusPlus) 863 Builder.defineMacro("_GNU_SOURCE"); 864 } 865 866 // As an optimization, group static init code together in a section. 867 const char *getStaticInitSectionSpecifier() const final { 868 return ".text.__startup"; 869 } 870 871 public: 872 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple, 873 const TargetOptions &Opts) 874 : OSTargetInfo<Target>(Triple, Opts) { 875 this->MCountName = "__mcount"; 876 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 877 } 878 }; 879 880 //===----------------------------------------------------------------------===// 881 // Specific target implementations. 882 //===----------------------------------------------------------------------===// 883 884 // PPC abstract base class 885 class PPCTargetInfo : public TargetInfo { 886 static const Builtin::Info BuiltinInfo[]; 887 static const char * const GCCRegNames[]; 888 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 889 std::string CPU; 890 891 // Target cpu features. 892 bool HasAltivec; 893 bool HasVSX; 894 bool HasP8Vector; 895 bool HasP8Crypto; 896 bool HasDirectMove; 897 bool HasQPX; 898 bool HasHTM; 899 bool HasBPERMD; 900 bool HasExtDiv; 901 bool HasP9Vector; 902 903 protected: 904 std::string ABI; 905 906 public: 907 PPCTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 908 : TargetInfo(Triple), HasAltivec(false), HasVSX(false), HasP8Vector(false), 909 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 910 HasBPERMD(false), HasExtDiv(false), HasP9Vector(false) { 911 SuitableAlign = 128; 912 SimdDefaultAlign = 128; 913 LongDoubleWidth = LongDoubleAlign = 128; 914 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble(); 915 } 916 917 /// \brief Flags for architecture specific defines. 918 typedef enum { 919 ArchDefineNone = 0, 920 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 921 ArchDefinePpcgr = 1 << 1, 922 ArchDefinePpcsq = 1 << 2, 923 ArchDefine440 = 1 << 3, 924 ArchDefine603 = 1 << 4, 925 ArchDefine604 = 1 << 5, 926 ArchDefinePwr4 = 1 << 6, 927 ArchDefinePwr5 = 1 << 7, 928 ArchDefinePwr5x = 1 << 8, 929 ArchDefinePwr6 = 1 << 9, 930 ArchDefinePwr6x = 1 << 10, 931 ArchDefinePwr7 = 1 << 11, 932 ArchDefinePwr8 = 1 << 12, 933 ArchDefinePwr9 = 1 << 13, 934 ArchDefineA2 = 1 << 14, 935 ArchDefineA2q = 1 << 15 936 } ArchDefineTypes; 937 938 // Set the language option for altivec based on our value. 939 void adjust(LangOptions &Opts) override { 940 if (HasAltivec) 941 Opts.AltiVec = 1; 942 TargetInfo::adjust(Opts); 943 } 944 945 // Note: GCC recognizes the following additional cpus: 946 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 947 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 948 // titan, rs64. 949 bool setCPU(const std::string &Name) override { 950 bool CPUKnown = llvm::StringSwitch<bool>(Name) 951 .Case("generic", true) 952 .Case("440", true) 953 .Case("450", true) 954 .Case("601", true) 955 .Case("602", true) 956 .Case("603", true) 957 .Case("603e", true) 958 .Case("603ev", true) 959 .Case("604", true) 960 .Case("604e", true) 961 .Case("620", true) 962 .Case("630", true) 963 .Case("g3", true) 964 .Case("7400", true) 965 .Case("g4", true) 966 .Case("7450", true) 967 .Case("g4+", true) 968 .Case("750", true) 969 .Case("970", true) 970 .Case("g5", true) 971 .Case("a2", true) 972 .Case("a2q", true) 973 .Case("e500mc", true) 974 .Case("e5500", true) 975 .Case("power3", true) 976 .Case("pwr3", true) 977 .Case("power4", true) 978 .Case("pwr4", true) 979 .Case("power5", true) 980 .Case("pwr5", true) 981 .Case("power5x", true) 982 .Case("pwr5x", true) 983 .Case("power6", true) 984 .Case("pwr6", true) 985 .Case("power6x", true) 986 .Case("pwr6x", true) 987 .Case("power7", true) 988 .Case("pwr7", true) 989 .Case("power8", true) 990 .Case("pwr8", true) 991 .Case("power9", true) 992 .Case("pwr9", true) 993 .Case("powerpc", true) 994 .Case("ppc", true) 995 .Case("powerpc64", true) 996 .Case("ppc64", true) 997 .Case("powerpc64le", true) 998 .Case("ppc64le", true) 999 .Default(false); 1000 1001 if (CPUKnown) 1002 CPU = Name; 1003 1004 return CPUKnown; 1005 } 1006 1007 1008 StringRef getABI() const override { return ABI; } 1009 1010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1011 return llvm::makeArrayRef(BuiltinInfo, 1012 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 1013 } 1014 1015 bool isCLZForZeroUndef() const override { return false; } 1016 1017 void getTargetDefines(const LangOptions &Opts, 1018 MacroBuilder &Builder) const override; 1019 1020 bool 1021 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1022 StringRef CPU, 1023 const std::vector<std::string> &FeaturesVec) const override; 1024 1025 bool handleTargetFeatures(std::vector<std::string> &Features, 1026 DiagnosticsEngine &Diags) override; 1027 bool hasFeature(StringRef Feature) const override; 1028 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 1029 bool Enabled) const override; 1030 1031 ArrayRef<const char *> getGCCRegNames() const override; 1032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 1033 bool validateAsmConstraint(const char *&Name, 1034 TargetInfo::ConstraintInfo &Info) const override { 1035 switch (*Name) { 1036 default: return false; 1037 case 'O': // Zero 1038 break; 1039 case 'b': // Base register 1040 case 'f': // Floating point register 1041 Info.setAllowsRegister(); 1042 break; 1043 // FIXME: The following are added to allow parsing. 1044 // I just took a guess at what the actions should be. 1045 // Also, is more specific checking needed? I.e. specific registers? 1046 case 'd': // Floating point register (containing 64-bit value) 1047 case 'v': // Altivec vector register 1048 Info.setAllowsRegister(); 1049 break; 1050 case 'w': 1051 switch (Name[1]) { 1052 case 'd':// VSX vector register to hold vector double data 1053 case 'f':// VSX vector register to hold vector float data 1054 case 's':// VSX vector register to hold scalar float data 1055 case 'a':// Any VSX register 1056 case 'c':// An individual CR bit 1057 break; 1058 default: 1059 return false; 1060 } 1061 Info.setAllowsRegister(); 1062 Name++; // Skip over 'w'. 1063 break; 1064 case 'h': // `MQ', `CTR', or `LINK' register 1065 case 'q': // `MQ' register 1066 case 'c': // `CTR' register 1067 case 'l': // `LINK' register 1068 case 'x': // `CR' register (condition register) number 0 1069 case 'y': // `CR' register (condition register) 1070 case 'z': // `XER[CA]' carry bit (part of the XER register) 1071 Info.setAllowsRegister(); 1072 break; 1073 case 'I': // Signed 16-bit constant 1074 case 'J': // Unsigned 16-bit constant shifted left 16 bits 1075 // (use `L' instead for SImode constants) 1076 case 'K': // Unsigned 16-bit constant 1077 case 'L': // Signed 16-bit constant shifted left 16 bits 1078 case 'M': // Constant larger than 31 1079 case 'N': // Exact power of 2 1080 case 'P': // Constant whose negation is a signed 16-bit constant 1081 case 'G': // Floating point constant that can be loaded into a 1082 // register with one instruction per word 1083 case 'H': // Integer/Floating point constant that can be loaded 1084 // into a register using three instructions 1085 break; 1086 case 'm': // Memory operand. Note that on PowerPC targets, m can 1087 // include addresses that update the base register. It 1088 // is therefore only safe to use `m' in an asm statement 1089 // if that asm statement accesses the operand exactly once. 1090 // The asm statement must also use `%U<opno>' as a 1091 // placeholder for the "update" flag in the corresponding 1092 // load or store instruction. For example: 1093 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 1094 // is correct but: 1095 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 1096 // is not. Use es rather than m if you don't want the base 1097 // register to be updated. 1098 case 'e': 1099 if (Name[1] != 's') 1100 return false; 1101 // es: A "stable" memory operand; that is, one which does not 1102 // include any automodification of the base register. Unlike 1103 // `m', this constraint can be used in asm statements that 1104 // might access the operand several times, or that might not 1105 // access it at all. 1106 Info.setAllowsMemory(); 1107 Name++; // Skip over 'e'. 1108 break; 1109 case 'Q': // Memory operand that is an offset from a register (it is 1110 // usually better to use `m' or `es' in asm statements) 1111 case 'Z': // Memory operand that is an indexed or indirect from a 1112 // register (it is usually better to use `m' or `es' in 1113 // asm statements) 1114 Info.setAllowsMemory(); 1115 Info.setAllowsRegister(); 1116 break; 1117 case 'R': // AIX TOC entry 1118 case 'a': // Address operand that is an indexed or indirect from a 1119 // register (`p' is preferable for asm statements) 1120 case 'S': // Constant suitable as a 64-bit mask operand 1121 case 'T': // Constant suitable as a 32-bit mask operand 1122 case 'U': // System V Release 4 small data area reference 1123 case 't': // AND masks that can be performed by two rldic{l, r} 1124 // instructions 1125 case 'W': // Vector constant that does not require memory 1126 case 'j': // Vector constant that is all zeros. 1127 break; 1128 // End FIXME. 1129 } 1130 return true; 1131 } 1132 std::string convertConstraint(const char *&Constraint) const override { 1133 std::string R; 1134 switch (*Constraint) { 1135 case 'e': 1136 case 'w': 1137 // Two-character constraint; add "^" hint for later parsing. 1138 R = std::string("^") + std::string(Constraint, 2); 1139 Constraint++; 1140 break; 1141 default: 1142 return TargetInfo::convertConstraint(Constraint); 1143 } 1144 return R; 1145 } 1146 const char *getClobbers() const override { 1147 return ""; 1148 } 1149 int getEHDataRegisterNumber(unsigned RegNo) const override { 1150 if (RegNo == 0) return 3; 1151 if (RegNo == 1) return 4; 1152 return -1; 1153 } 1154 1155 bool hasSjLjLowering() const override { 1156 return true; 1157 } 1158 1159 bool useFloat128ManglingForLongDouble() const override { 1160 return LongDoubleWidth == 128 && 1161 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble() && 1162 getTriple().isOSBinFormatELF(); 1163 } 1164 }; 1165 1166 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1167 #define BUILTIN(ID, TYPE, ATTRS) \ 1168 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1169 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1170 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1171 #include "clang/Basic/BuiltinsPPC.def" 1172 }; 1173 1174 /// handleTargetFeatures - Perform initialization based on the user 1175 /// configured set of features. 1176 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1177 DiagnosticsEngine &Diags) { 1178 for (const auto &Feature : Features) { 1179 if (Feature == "+altivec") { 1180 HasAltivec = true; 1181 } else if (Feature == "+vsx") { 1182 HasVSX = true; 1183 } else if (Feature == "+bpermd") { 1184 HasBPERMD = true; 1185 } else if (Feature == "+extdiv") { 1186 HasExtDiv = true; 1187 } else if (Feature == "+power8-vector") { 1188 HasP8Vector = true; 1189 } else if (Feature == "+crypto") { 1190 HasP8Crypto = true; 1191 } else if (Feature == "+direct-move") { 1192 HasDirectMove = true; 1193 } else if (Feature == "+qpx") { 1194 HasQPX = true; 1195 } else if (Feature == "+htm") { 1196 HasHTM = true; 1197 } else if (Feature == "+float128") { 1198 HasFloat128 = true; 1199 } else if (Feature == "+power9-vector") { 1200 HasP9Vector = true; 1201 } 1202 // TODO: Finish this list and add an assert that we've handled them 1203 // all. 1204 } 1205 1206 return true; 1207 } 1208 1209 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1210 /// #defines that are not tied to a specific subtarget. 1211 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1212 MacroBuilder &Builder) const { 1213 // Target identification. 1214 Builder.defineMacro("__ppc__"); 1215 Builder.defineMacro("__PPC__"); 1216 Builder.defineMacro("_ARCH_PPC"); 1217 Builder.defineMacro("__powerpc__"); 1218 Builder.defineMacro("__POWERPC__"); 1219 if (PointerWidth == 64) { 1220 Builder.defineMacro("_ARCH_PPC64"); 1221 Builder.defineMacro("__powerpc64__"); 1222 Builder.defineMacro("__ppc64__"); 1223 Builder.defineMacro("__PPC64__"); 1224 } 1225 1226 // Target properties. 1227 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1228 Builder.defineMacro("_LITTLE_ENDIAN"); 1229 } else { 1230 if (getTriple().getOS() != llvm::Triple::NetBSD && 1231 getTriple().getOS() != llvm::Triple::OpenBSD) 1232 Builder.defineMacro("_BIG_ENDIAN"); 1233 } 1234 1235 // ABI options. 1236 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1237 Builder.defineMacro("_CALL_ELF", "1"); 1238 if (ABI == "elfv2") 1239 Builder.defineMacro("_CALL_ELF", "2"); 1240 1241 // This typically is only for a new enough linker (bfd >= 2.16.2 or gold), but 1242 // our suppport post-dates this and it should work on all 64-bit ppc linux 1243 // platforms. It is guaranteed to work on all elfv2 platforms. 1244 if (getTriple().getOS() == llvm::Triple::Linux && PointerWidth == 64) 1245 Builder.defineMacro("_CALL_LINUX", "1"); 1246 1247 // Subtarget options. 1248 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1249 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1250 1251 // FIXME: Should be controlled by command line option. 1252 if (LongDoubleWidth == 128) { 1253 Builder.defineMacro("__LONG_DOUBLE_128__"); 1254 Builder.defineMacro("__LONGDOUBLE128"); 1255 } 1256 1257 // Define this for elfv2 (64-bit only) or 64-bit darwin. 1258 if (ABI == "elfv2" || 1259 (getTriple().getOS() == llvm::Triple::Darwin && PointerWidth == 64)) 1260 Builder.defineMacro("__STRUCT_PARM_ALIGN__", "16"); 1261 1262 // CPU identification. 1263 ArchDefineTypes defs = 1264 (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1265 .Case("440", ArchDefineName) 1266 .Case("450", ArchDefineName | ArchDefine440) 1267 .Case("601", ArchDefineName) 1268 .Case("602", ArchDefineName | ArchDefinePpcgr) 1269 .Case("603", ArchDefineName | ArchDefinePpcgr) 1270 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1271 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1272 .Case("604", ArchDefineName | ArchDefinePpcgr) 1273 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1274 .Case("620", ArchDefineName | ArchDefinePpcgr) 1275 .Case("630", ArchDefineName | ArchDefinePpcgr) 1276 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1277 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1278 .Case("750", ArchDefineName | ArchDefinePpcgr) 1279 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1280 ArchDefinePpcsq) 1281 .Case("a2", ArchDefineA2) 1282 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1283 .Case("pwr3", ArchDefinePpcgr) 1284 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1285 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr | 1286 ArchDefinePpcsq) 1287 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 | 1288 ArchDefinePpcgr | ArchDefinePpcsq) 1289 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 | 1290 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1291 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x | 1292 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1293 ArchDefinePpcsq) 1294 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 | 1295 ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1296 ArchDefinePpcgr | ArchDefinePpcsq) 1297 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x | 1298 ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1299 ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1300 .Case("pwr9", ArchDefineName | ArchDefinePwr8 | ArchDefinePwr7 | 1301 ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1302 ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1303 ArchDefinePpcsq) 1304 .Case("power3", ArchDefinePpcgr) 1305 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1306 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr | 1307 ArchDefinePpcsq) 1308 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 | 1309 ArchDefinePpcgr | ArchDefinePpcsq) 1310 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 | 1311 ArchDefinePwr4 | ArchDefinePpcgr | 1312 ArchDefinePpcsq) 1313 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x | 1314 ArchDefinePwr5 | ArchDefinePwr4 | 1315 ArchDefinePpcgr | ArchDefinePpcsq) 1316 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 | 1317 ArchDefinePwr5x | ArchDefinePwr5 | 1318 ArchDefinePwr4 | ArchDefinePpcgr | 1319 ArchDefinePpcsq) 1320 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1321 ArchDefinePwr6 | ArchDefinePwr5x | 1322 ArchDefinePwr5 | ArchDefinePwr4 | 1323 ArchDefinePpcgr | ArchDefinePpcsq) 1324 .Case("power9", ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 | 1325 ArchDefinePwr6x | ArchDefinePwr6 | 1326 ArchDefinePwr5x | ArchDefinePwr5 | 1327 ArchDefinePwr4 | ArchDefinePpcgr | 1328 ArchDefinePpcsq) 1329 // powerpc64le automatically defaults to at least power8. 1330 .Case("ppc64le", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x | 1331 ArchDefinePwr6 | ArchDefinePwr5x | 1332 ArchDefinePwr5 | ArchDefinePwr4 | 1333 ArchDefinePpcgr | ArchDefinePpcsq) 1334 .Default(ArchDefineNone); 1335 1336 if (defs & ArchDefineName) 1337 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1338 if (defs & ArchDefinePpcgr) 1339 Builder.defineMacro("_ARCH_PPCGR"); 1340 if (defs & ArchDefinePpcsq) 1341 Builder.defineMacro("_ARCH_PPCSQ"); 1342 if (defs & ArchDefine440) 1343 Builder.defineMacro("_ARCH_440"); 1344 if (defs & ArchDefine603) 1345 Builder.defineMacro("_ARCH_603"); 1346 if (defs & ArchDefine604) 1347 Builder.defineMacro("_ARCH_604"); 1348 if (defs & ArchDefinePwr4) 1349 Builder.defineMacro("_ARCH_PWR4"); 1350 if (defs & ArchDefinePwr5) 1351 Builder.defineMacro("_ARCH_PWR5"); 1352 if (defs & ArchDefinePwr5x) 1353 Builder.defineMacro("_ARCH_PWR5X"); 1354 if (defs & ArchDefinePwr6) 1355 Builder.defineMacro("_ARCH_PWR6"); 1356 if (defs & ArchDefinePwr6x) 1357 Builder.defineMacro("_ARCH_PWR6X"); 1358 if (defs & ArchDefinePwr7) 1359 Builder.defineMacro("_ARCH_PWR7"); 1360 if (defs & ArchDefinePwr8) 1361 Builder.defineMacro("_ARCH_PWR8"); 1362 if (defs & ArchDefinePwr9) 1363 Builder.defineMacro("_ARCH_PWR9"); 1364 if (defs & ArchDefineA2) 1365 Builder.defineMacro("_ARCH_A2"); 1366 if (defs & ArchDefineA2q) { 1367 Builder.defineMacro("_ARCH_A2Q"); 1368 Builder.defineMacro("_ARCH_QP"); 1369 } 1370 1371 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1372 Builder.defineMacro("__bg__"); 1373 Builder.defineMacro("__THW_BLUEGENE__"); 1374 Builder.defineMacro("__bgq__"); 1375 Builder.defineMacro("__TOS_BGQ__"); 1376 } 1377 1378 if (HasAltivec) { 1379 Builder.defineMacro("__VEC__", "10206"); 1380 Builder.defineMacro("__ALTIVEC__"); 1381 } 1382 if (HasVSX) 1383 Builder.defineMacro("__VSX__"); 1384 if (HasP8Vector) 1385 Builder.defineMacro("__POWER8_VECTOR__"); 1386 if (HasP8Crypto) 1387 Builder.defineMacro("__CRYPTO__"); 1388 if (HasHTM) 1389 Builder.defineMacro("__HTM__"); 1390 if (HasFloat128) 1391 Builder.defineMacro("__FLOAT128__"); 1392 if (HasP9Vector) 1393 Builder.defineMacro("__POWER9_VECTOR__"); 1394 1395 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1396 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1397 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1398 if (PointerWidth == 64) 1399 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1400 1401 // We have support for the bswap intrinsics so we can define this. 1402 Builder.defineMacro("__HAVE_BSWAP__", "1"); 1403 1404 // FIXME: The following are not yet generated here by Clang, but are 1405 // generated by GCC: 1406 // 1407 // _SOFT_FLOAT_ 1408 // __RECIP_PRECISION__ 1409 // __APPLE_ALTIVEC__ 1410 // __RECIP__ 1411 // __RECIPF__ 1412 // __RSQRTE__ 1413 // __RSQRTEF__ 1414 // _SOFT_DOUBLE_ 1415 // __NO_LWSYNC__ 1416 // __CMODEL_MEDIUM__ 1417 // __CMODEL_LARGE__ 1418 // _CALL_SYSV 1419 // _CALL_DARWIN 1420 // __NO_FPRS__ 1421 } 1422 1423 // Handle explicit options being passed to the compiler here: if we've 1424 // explicitly turned off vsx and turned on any of: 1425 // - power8-vector 1426 // - direct-move 1427 // - float128 1428 // - power9-vector 1429 // then go ahead and error since the customer has expressed an incompatible 1430 // set of options. 1431 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1432 const std::vector<std::string> &FeaturesVec) { 1433 1434 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1435 FeaturesVec.end()) { 1436 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1437 FeaturesVec.end()) { 1438 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1439 << "-mno-vsx"; 1440 return false; 1441 } 1442 1443 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1444 FeaturesVec.end()) { 1445 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1446 << "-mno-vsx"; 1447 return false; 1448 } 1449 1450 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+float128") != 1451 FeaturesVec.end()) { 1452 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mfloat128" 1453 << "-mno-vsx"; 1454 return false; 1455 } 1456 1457 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power9-vector") != 1458 FeaturesVec.end()) { 1459 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower9-vector" 1460 << "-mno-vsx"; 1461 return false; 1462 } 1463 } 1464 1465 return true; 1466 } 1467 1468 bool PPCTargetInfo::initFeatureMap( 1469 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1470 const std::vector<std::string> &FeaturesVec) const { 1471 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1472 .Case("7400", true) 1473 .Case("g4", true) 1474 .Case("7450", true) 1475 .Case("g4+", true) 1476 .Case("970", true) 1477 .Case("g5", true) 1478 .Case("pwr6", true) 1479 .Case("pwr7", true) 1480 .Case("pwr8", true) 1481 .Case("pwr9", true) 1482 .Case("ppc64", true) 1483 .Case("ppc64le", true) 1484 .Default(false); 1485 1486 Features["qpx"] = (CPU == "a2q"); 1487 Features["power9-vector"] = (CPU == "pwr9"); 1488 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1489 .Case("ppc64le", true) 1490 .Case("pwr9", true) 1491 .Case("pwr8", true) 1492 .Default(false); 1493 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1494 .Case("ppc64le", true) 1495 .Case("pwr9", true) 1496 .Case("pwr8", true) 1497 .Default(false); 1498 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1499 .Case("ppc64le", true) 1500 .Case("pwr9", true) 1501 .Case("pwr8", true) 1502 .Case("pwr7", true) 1503 .Default(false); 1504 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1505 .Case("ppc64le", true) 1506 .Case("pwr9", true) 1507 .Case("pwr8", true) 1508 .Case("pwr7", true) 1509 .Default(false); 1510 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1511 .Case("ppc64le", true) 1512 .Case("pwr9", true) 1513 .Case("pwr8", true) 1514 .Default(false); 1515 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1516 .Case("ppc64le", true) 1517 .Case("pwr9", true) 1518 .Case("pwr8", true) 1519 .Case("pwr7", true) 1520 .Default(false); 1521 Features["htm"] = llvm::StringSwitch<bool>(CPU) 1522 .Case("ppc64le", true) 1523 .Case("pwr9", true) 1524 .Case("pwr8", true) 1525 .Default(false); 1526 1527 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1528 return false; 1529 1530 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1531 } 1532 1533 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1534 return llvm::StringSwitch<bool>(Feature) 1535 .Case("powerpc", true) 1536 .Case("altivec", HasAltivec) 1537 .Case("vsx", HasVSX) 1538 .Case("power8-vector", HasP8Vector) 1539 .Case("crypto", HasP8Crypto) 1540 .Case("direct-move", HasDirectMove) 1541 .Case("qpx", HasQPX) 1542 .Case("htm", HasHTM) 1543 .Case("bpermd", HasBPERMD) 1544 .Case("extdiv", HasExtDiv) 1545 .Case("float128", HasFloat128) 1546 .Case("power9-vector", HasP9Vector) 1547 .Default(false); 1548 } 1549 1550 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1551 StringRef Name, bool Enabled) const { 1552 if (Enabled) { 1553 // If we're enabling any of the vsx based features then enable vsx and 1554 // altivec. We'll diagnose any problems later. 1555 bool FeatureHasVSX = llvm::StringSwitch<bool>(Name) 1556 .Case("vsx", true) 1557 .Case("direct-move", true) 1558 .Case("power8-vector", true) 1559 .Case("power9-vector", true) 1560 .Case("float128", true) 1561 .Default(false); 1562 if (FeatureHasVSX) 1563 Features["vsx"] = Features["altivec"] = true; 1564 if (Name == "power9-vector") 1565 Features["power8-vector"] = true; 1566 Features[Name] = true; 1567 } else { 1568 // If we're disabling altivec or vsx go ahead and disable all of the vsx 1569 // features. 1570 if ((Name == "altivec") || (Name == "vsx")) 1571 Features["vsx"] = Features["direct-move"] = Features["power8-vector"] = 1572 Features["float128"] = Features["power9-vector"] = false; 1573 if (Name == "power8-vector") 1574 Features["power9-vector"] = false; 1575 Features[Name] = false; 1576 } 1577 } 1578 1579 const char * const PPCTargetInfo::GCCRegNames[] = { 1580 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1581 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1582 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1583 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1584 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1585 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1586 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1587 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1588 "mq", "lr", "ctr", "ap", 1589 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1590 "xer", 1591 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1592 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1593 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1594 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1595 "vrsave", "vscr", 1596 "spe_acc", "spefscr", 1597 "sfp" 1598 }; 1599 1600 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1601 return llvm::makeArrayRef(GCCRegNames); 1602 } 1603 1604 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1605 // While some of these aliases do map to different registers 1606 // they still share the same register name. 1607 { { "0" }, "r0" }, 1608 { { "1"}, "r1" }, 1609 { { "2" }, "r2" }, 1610 { { "3" }, "r3" }, 1611 { { "4" }, "r4" }, 1612 { { "5" }, "r5" }, 1613 { { "6" }, "r6" }, 1614 { { "7" }, "r7" }, 1615 { { "8" }, "r8" }, 1616 { { "9" }, "r9" }, 1617 { { "10" }, "r10" }, 1618 { { "11" }, "r11" }, 1619 { { "12" }, "r12" }, 1620 { { "13" }, "r13" }, 1621 { { "14" }, "r14" }, 1622 { { "15" }, "r15" }, 1623 { { "16" }, "r16" }, 1624 { { "17" }, "r17" }, 1625 { { "18" }, "r18" }, 1626 { { "19" }, "r19" }, 1627 { { "20" }, "r20" }, 1628 { { "21" }, "r21" }, 1629 { { "22" }, "r22" }, 1630 { { "23" }, "r23" }, 1631 { { "24" }, "r24" }, 1632 { { "25" }, "r25" }, 1633 { { "26" }, "r26" }, 1634 { { "27" }, "r27" }, 1635 { { "28" }, "r28" }, 1636 { { "29" }, "r29" }, 1637 { { "30" }, "r30" }, 1638 { { "31" }, "r31" }, 1639 { { "fr0" }, "f0" }, 1640 { { "fr1" }, "f1" }, 1641 { { "fr2" }, "f2" }, 1642 { { "fr3" }, "f3" }, 1643 { { "fr4" }, "f4" }, 1644 { { "fr5" }, "f5" }, 1645 { { "fr6" }, "f6" }, 1646 { { "fr7" }, "f7" }, 1647 { { "fr8" }, "f8" }, 1648 { { "fr9" }, "f9" }, 1649 { { "fr10" }, "f10" }, 1650 { { "fr11" }, "f11" }, 1651 { { "fr12" }, "f12" }, 1652 { { "fr13" }, "f13" }, 1653 { { "fr14" }, "f14" }, 1654 { { "fr15" }, "f15" }, 1655 { { "fr16" }, "f16" }, 1656 { { "fr17" }, "f17" }, 1657 { { "fr18" }, "f18" }, 1658 { { "fr19" }, "f19" }, 1659 { { "fr20" }, "f20" }, 1660 { { "fr21" }, "f21" }, 1661 { { "fr22" }, "f22" }, 1662 { { "fr23" }, "f23" }, 1663 { { "fr24" }, "f24" }, 1664 { { "fr25" }, "f25" }, 1665 { { "fr26" }, "f26" }, 1666 { { "fr27" }, "f27" }, 1667 { { "fr28" }, "f28" }, 1668 { { "fr29" }, "f29" }, 1669 { { "fr30" }, "f30" }, 1670 { { "fr31" }, "f31" }, 1671 { { "cc" }, "cr0" }, 1672 }; 1673 1674 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1675 return llvm::makeArrayRef(GCCRegAliases); 1676 } 1677 1678 class PPC32TargetInfo : public PPCTargetInfo { 1679 public: 1680 PPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1681 : PPCTargetInfo(Triple, Opts) { 1682 resetDataLayout("E-m:e-p:32:32-i64:64-n32"); 1683 1684 switch (getTriple().getOS()) { 1685 case llvm::Triple::Linux: 1686 case llvm::Triple::FreeBSD: 1687 case llvm::Triple::NetBSD: 1688 SizeType = UnsignedInt; 1689 PtrDiffType = SignedInt; 1690 IntPtrType = SignedInt; 1691 break; 1692 default: 1693 break; 1694 } 1695 1696 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1697 LongDoubleWidth = LongDoubleAlign = 64; 1698 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1699 } 1700 1701 // PPC32 supports atomics up to 4 bytes. 1702 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1703 } 1704 1705 BuiltinVaListKind getBuiltinVaListKind() const override { 1706 // This is the ELF definition, and is overridden by the Darwin sub-target 1707 return TargetInfo::PowerABIBuiltinVaList; 1708 } 1709 }; 1710 1711 // Note: ABI differences may eventually require us to have a separate 1712 // TargetInfo for little endian. 1713 class PPC64TargetInfo : public PPCTargetInfo { 1714 public: 1715 PPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1716 : PPCTargetInfo(Triple, Opts) { 1717 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1718 IntMaxType = SignedLong; 1719 Int64Type = SignedLong; 1720 1721 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1722 resetDataLayout("e-m:e-i64:64-n32:64"); 1723 ABI = "elfv2"; 1724 } else { 1725 resetDataLayout("E-m:e-i64:64-n32:64"); 1726 ABI = "elfv1"; 1727 } 1728 1729 switch (getTriple().getOS()) { 1730 case llvm::Triple::FreeBSD: 1731 LongDoubleWidth = LongDoubleAlign = 64; 1732 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 1733 break; 1734 case llvm::Triple::NetBSD: 1735 IntMaxType = SignedLongLong; 1736 Int64Type = SignedLongLong; 1737 break; 1738 default: 1739 break; 1740 } 1741 1742 // PPC64 supports atomics up to 8 bytes. 1743 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1744 } 1745 BuiltinVaListKind getBuiltinVaListKind() const override { 1746 return TargetInfo::CharPtrBuiltinVaList; 1747 } 1748 // PPC64 Linux-specific ABI options. 1749 bool setABI(const std::string &Name) override { 1750 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1751 ABI = Name; 1752 return true; 1753 } 1754 return false; 1755 } 1756 }; 1757 1758 class DarwinPPC32TargetInfo : public DarwinTargetInfo<PPC32TargetInfo> { 1759 public: 1760 DarwinPPC32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1761 : DarwinTargetInfo<PPC32TargetInfo>(Triple, Opts) { 1762 HasAlignMac68kSupport = true; 1763 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1764 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1765 LongLongAlign = 32; 1766 resetDataLayout("E-m:o-p:32:32-f64:32:64-n32"); 1767 } 1768 BuiltinVaListKind getBuiltinVaListKind() const override { 1769 return TargetInfo::CharPtrBuiltinVaList; 1770 } 1771 }; 1772 1773 class DarwinPPC64TargetInfo : public DarwinTargetInfo<PPC64TargetInfo> { 1774 public: 1775 DarwinPPC64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 1776 : DarwinTargetInfo<PPC64TargetInfo>(Triple, Opts) { 1777 HasAlignMac68kSupport = true; 1778 resetDataLayout("E-m:o-i64:64-n32:64"); 1779 } 1780 }; 1781 1782 static const unsigned NVPTXAddrSpaceMap[] = { 1783 0, // Default 1784 1, // opencl_global 1785 3, // opencl_local 1786 4, // opencl_constant 1787 // FIXME: generic has to be added to the target 1788 0, // opencl_generic 1789 1, // cuda_device 1790 4, // cuda_constant 1791 3, // cuda_shared 1792 }; 1793 1794 class NVPTXTargetInfo : public TargetInfo { 1795 static const char *const GCCRegNames[]; 1796 static const Builtin::Info BuiltinInfo[]; 1797 CudaArch GPU; 1798 std::unique_ptr<TargetInfo> HostTarget; 1799 1800 public: 1801 NVPTXTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts, 1802 unsigned TargetPointerWidth) 1803 : TargetInfo(Triple) { 1804 assert((TargetPointerWidth == 32 || TargetPointerWidth == 64) && 1805 "NVPTX only supports 32- and 64-bit modes."); 1806 1807 TLSSupported = false; 1808 AddrSpaceMap = &NVPTXAddrSpaceMap; 1809 UseAddrSpaceMapMangling = true; 1810 1811 // Define available target features 1812 // These must be defined in sorted order! 1813 NoAsmVariants = true; 1814 GPU = CudaArch::SM_20; 1815 1816 if (TargetPointerWidth == 32) 1817 resetDataLayout("e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"); 1818 else 1819 resetDataLayout("e-i64:64-v16:16-v32:32-n16:32:64"); 1820 1821 // If possible, get a TargetInfo for our host triple, so we can match its 1822 // types. 1823 llvm::Triple HostTriple(Opts.HostTriple); 1824 if (!HostTriple.isNVPTX()) 1825 HostTarget.reset(AllocateTarget(llvm::Triple(Opts.HostTriple), Opts)); 1826 1827 // If no host target, make some guesses about the data layout and return. 1828 if (!HostTarget) { 1829 LongWidth = LongAlign = TargetPointerWidth; 1830 PointerWidth = PointerAlign = TargetPointerWidth; 1831 switch (TargetPointerWidth) { 1832 case 32: 1833 SizeType = TargetInfo::UnsignedInt; 1834 PtrDiffType = TargetInfo::SignedInt; 1835 IntPtrType = TargetInfo::SignedInt; 1836 break; 1837 case 64: 1838 SizeType = TargetInfo::UnsignedLong; 1839 PtrDiffType = TargetInfo::SignedLong; 1840 IntPtrType = TargetInfo::SignedLong; 1841 break; 1842 default: 1843 llvm_unreachable("TargetPointerWidth must be 32 or 64"); 1844 } 1845 return; 1846 } 1847 1848 // Copy properties from host target. 1849 PointerWidth = HostTarget->getPointerWidth(/* AddrSpace = */ 0); 1850 PointerAlign = HostTarget->getPointerAlign(/* AddrSpace = */ 0); 1851 BoolWidth = HostTarget->getBoolWidth(); 1852 BoolAlign = HostTarget->getBoolAlign(); 1853 IntWidth = HostTarget->getIntWidth(); 1854 IntAlign = HostTarget->getIntAlign(); 1855 HalfWidth = HostTarget->getHalfWidth(); 1856 HalfAlign = HostTarget->getHalfAlign(); 1857 FloatWidth = HostTarget->getFloatWidth(); 1858 FloatAlign = HostTarget->getFloatAlign(); 1859 DoubleWidth = HostTarget->getDoubleWidth(); 1860 DoubleAlign = HostTarget->getDoubleAlign(); 1861 LongWidth = HostTarget->getLongWidth(); 1862 LongAlign = HostTarget->getLongAlign(); 1863 LongLongWidth = HostTarget->getLongLongWidth(); 1864 LongLongAlign = HostTarget->getLongLongAlign(); 1865 MinGlobalAlign = HostTarget->getMinGlobalAlign(); 1866 NewAlign = HostTarget->getNewAlign(); 1867 DefaultAlignForAttributeAligned = 1868 HostTarget->getDefaultAlignForAttributeAligned(); 1869 SizeType = HostTarget->getSizeType(); 1870 IntMaxType = HostTarget->getIntMaxType(); 1871 PtrDiffType = HostTarget->getPtrDiffType(/* AddrSpace = */ 0); 1872 IntPtrType = HostTarget->getIntPtrType(); 1873 WCharType = HostTarget->getWCharType(); 1874 WIntType = HostTarget->getWIntType(); 1875 Char16Type = HostTarget->getChar16Type(); 1876 Char32Type = HostTarget->getChar32Type(); 1877 Int64Type = HostTarget->getInt64Type(); 1878 SigAtomicType = HostTarget->getSigAtomicType(); 1879 ProcessIDType = HostTarget->getProcessIDType(); 1880 1881 UseBitFieldTypeAlignment = HostTarget->useBitFieldTypeAlignment(); 1882 UseZeroLengthBitfieldAlignment = 1883 HostTarget->useZeroLengthBitfieldAlignment(); 1884 UseExplicitBitFieldAlignment = HostTarget->useExplicitBitFieldAlignment(); 1885 ZeroLengthBitfieldBoundary = HostTarget->getZeroLengthBitfieldBoundary(); 1886 1887 // This is a bit of a lie, but it controls __GCC_ATOMIC_XXX_LOCK_FREE, and 1888 // we need those macros to be identical on host and device, because (among 1889 // other things) they affect which standard library classes are defined, and 1890 // we need all classes to be defined on both the host and device. 1891 MaxAtomicInlineWidth = HostTarget->getMaxAtomicInlineWidth(); 1892 1893 // Properties intentionally not copied from host: 1894 // - LargeArrayMinWidth, LargeArrayAlign: Not visible across the 1895 // host/device boundary. 1896 // - SuitableAlign: Not visible across the host/device boundary, and may 1897 // correctly be different on host/device, e.g. if host has wider vector 1898 // types than device. 1899 // - LongDoubleWidth, LongDoubleAlign: nvptx's long double type is the same 1900 // as its double type, but that's not necessarily true on the host. 1901 // TODO: nvcc emits a warning when using long double on device; we should 1902 // do the same. 1903 } 1904 void getTargetDefines(const LangOptions &Opts, 1905 MacroBuilder &Builder) const override { 1906 Builder.defineMacro("__PTX__"); 1907 Builder.defineMacro("__NVPTX__"); 1908 if (Opts.CUDAIsDevice) { 1909 // Set __CUDA_ARCH__ for the GPU specified. 1910 std::string CUDAArchCode = [this] { 1911 switch (GPU) { 1912 case CudaArch::UNKNOWN: 1913 assert(false && "No GPU arch when compiling CUDA device code."); 1914 return ""; 1915 case CudaArch::SM_20: 1916 return "200"; 1917 case CudaArch::SM_21: 1918 return "210"; 1919 case CudaArch::SM_30: 1920 return "300"; 1921 case CudaArch::SM_32: 1922 return "320"; 1923 case CudaArch::SM_35: 1924 return "350"; 1925 case CudaArch::SM_37: 1926 return "370"; 1927 case CudaArch::SM_50: 1928 return "500"; 1929 case CudaArch::SM_52: 1930 return "520"; 1931 case CudaArch::SM_53: 1932 return "530"; 1933 case CudaArch::SM_60: 1934 return "600"; 1935 case CudaArch::SM_61: 1936 return "610"; 1937 case CudaArch::SM_62: 1938 return "620"; 1939 } 1940 llvm_unreachable("unhandled CudaArch"); 1941 }(); 1942 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1943 } 1944 } 1945 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1946 return llvm::makeArrayRef(BuiltinInfo, 1947 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1948 } 1949 bool 1950 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 1951 StringRef CPU, 1952 const std::vector<std::string> &FeaturesVec) const override { 1953 Features["satom"] = GPU >= CudaArch::SM_60; 1954 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1955 } 1956 1957 bool hasFeature(StringRef Feature) const override { 1958 return llvm::StringSwitch<bool>(Feature) 1959 .Cases("ptx", "nvptx", true) 1960 .Case("satom", GPU >= CudaArch::SM_60) // Atomics w/ scope. 1961 .Default(false); 1962 } 1963 1964 ArrayRef<const char *> getGCCRegNames() const override; 1965 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1966 // No aliases. 1967 return None; 1968 } 1969 bool validateAsmConstraint(const char *&Name, 1970 TargetInfo::ConstraintInfo &Info) const override { 1971 switch (*Name) { 1972 default: 1973 return false; 1974 case 'c': 1975 case 'h': 1976 case 'r': 1977 case 'l': 1978 case 'f': 1979 case 'd': 1980 Info.setAllowsRegister(); 1981 return true; 1982 } 1983 } 1984 const char *getClobbers() const override { 1985 // FIXME: Is this really right? 1986 return ""; 1987 } 1988 BuiltinVaListKind getBuiltinVaListKind() const override { 1989 // FIXME: implement 1990 return TargetInfo::CharPtrBuiltinVaList; 1991 } 1992 bool setCPU(const std::string &Name) override { 1993 GPU = StringToCudaArch(Name); 1994 return GPU != CudaArch::UNKNOWN; 1995 } 1996 void setSupportedOpenCLOpts() override { 1997 auto &Opts = getSupportedOpenCLOpts(); 1998 Opts.support("cl_clang_storage_class_specifiers"); 1999 Opts.support("cl_khr_gl_sharing"); 2000 Opts.support("cl_khr_icd"); 2001 2002 Opts.support("cl_khr_fp64"); 2003 Opts.support("cl_khr_byte_addressable_store"); 2004 Opts.support("cl_khr_global_int32_base_atomics"); 2005 Opts.support("cl_khr_global_int32_extended_atomics"); 2006 Opts.support("cl_khr_local_int32_base_atomics"); 2007 Opts.support("cl_khr_local_int32_extended_atomics"); 2008 } 2009 2010 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2011 // CUDA compilations support all of the host's calling conventions. 2012 // 2013 // TODO: We should warn if you apply a non-default CC to anything other than 2014 // a host function. 2015 if (HostTarget) 2016 return HostTarget->checkCallingConvention(CC); 2017 return CCCR_Warning; 2018 } 2019 }; 2020 2021 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 2022 #define BUILTIN(ID, TYPE, ATTRS) \ 2023 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2024 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2025 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2026 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2027 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2028 #include "clang/Basic/BuiltinsNVPTX.def" 2029 }; 2030 2031 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 2032 2033 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 static const LangAS::Map AMDGPUNonOpenCLPrivateIsZeroMap = { 2038 4, // Default 2039 1, // opencl_global 2040 3, // opencl_local 2041 2, // opencl_constant 2042 4, // opencl_generic 2043 1, // cuda_device 2044 2, // cuda_constant 2045 3 // cuda_shared 2046 }; 2047 static const LangAS::Map AMDGPUNonOpenCLGenericIsZeroMap = { 2048 0, // Default 2049 1, // opencl_global 2050 3, // opencl_local 2051 2, // opencl_constant 2052 0, // opencl_generic 2053 1, // cuda_device 2054 2, // cuda_constant 2055 3 // cuda_shared 2056 }; 2057 static const LangAS::Map AMDGPUOpenCLPrivateIsZeroMap = { 2058 0, // Default 2059 1, // opencl_global 2060 3, // opencl_local 2061 2, // opencl_constant 2062 4, // opencl_generic 2063 1, // cuda_device 2064 2, // cuda_constant 2065 3 // cuda_shared 2066 }; 2067 static const LangAS::Map AMDGPUOpenCLGenericIsZeroMap = { 2068 5, // Default 2069 1, // opencl_global 2070 3, // opencl_local 2071 2, // opencl_constant 2072 0, // opencl_generic 2073 1, // cuda_device 2074 2, // cuda_constant 2075 3 // cuda_shared 2076 }; 2077 2078 // If you edit the description strings, make sure you update 2079 // getPointerWidthV(). 2080 2081 static const char *const DataLayoutStringR600 = 2082 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2083 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2084 2085 static const char *const DataLayoutStringSIPrivateIsZero = 2086 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32" 2087 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2088 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 2089 2090 static const char *const DataLayoutStringSIGenericIsZero = 2091 "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" 2092 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 2093 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; 2094 2095 class AMDGPUTargetInfo final : public TargetInfo { 2096 static const Builtin::Info BuiltinInfo[]; 2097 static const char * const GCCRegNames[]; 2098 2099 struct AddrSpace { 2100 unsigned Generic, Global, Local, Constant, Private; 2101 AddrSpace(bool IsGenericZero_ = false){ 2102 if (IsGenericZero_) { 2103 Generic = 0; 2104 Global = 1; 2105 Local = 3; 2106 Constant = 2; 2107 Private = 5; 2108 } else { 2109 Generic = 4; 2110 Global = 1; 2111 Local = 3; 2112 Constant = 2; 2113 Private = 0; 2114 } 2115 } 2116 }; 2117 2118 /// \brief The GPU profiles supported by the AMDGPU target. 2119 enum GPUKind { 2120 GK_NONE, 2121 GK_R600, 2122 GK_R600_DOUBLE_OPS, 2123 GK_R700, 2124 GK_R700_DOUBLE_OPS, 2125 GK_EVERGREEN, 2126 GK_EVERGREEN_DOUBLE_OPS, 2127 GK_NORTHERN_ISLANDS, 2128 GK_CAYMAN, 2129 GK_GFX6, 2130 GK_GFX7, 2131 GK_GFX8, 2132 GK_GFX9 2133 } GPU; 2134 2135 bool hasFP64:1; 2136 bool hasFMAF:1; 2137 bool hasLDEXPF:1; 2138 const AddrSpace AS; 2139 2140 static bool hasFullSpeedFMAF32(StringRef GPUName) { 2141 return parseAMDGCNName(GPUName) >= GK_GFX9; 2142 } 2143 2144 static bool isAMDGCN(const llvm::Triple &TT) { 2145 return TT.getArch() == llvm::Triple::amdgcn; 2146 } 2147 2148 static bool isGenericZero(const llvm::Triple &TT) { 2149 return TT.getEnvironmentName() == "amdgiz" || 2150 TT.getEnvironmentName() == "amdgizcl"; 2151 } 2152 public: 2153 AMDGPUTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 2154 : TargetInfo(Triple) , 2155 GPU(isAMDGCN(Triple) ? GK_GFX6 : GK_R600), 2156 hasFP64(false), 2157 hasFMAF(false), 2158 hasLDEXPF(false), 2159 AS(isGenericZero(Triple)){ 2160 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2161 hasFP64 = true; 2162 hasFMAF = true; 2163 hasLDEXPF = true; 2164 } 2165 auto IsGenericZero = isGenericZero(Triple); 2166 resetDataLayout(getTriple().getArch() == llvm::Triple::amdgcn ? 2167 (IsGenericZero ? DataLayoutStringSIGenericIsZero : 2168 DataLayoutStringSIPrivateIsZero) 2169 : DataLayoutStringR600); 2170 assert(DataLayout->getAllocaAddrSpace() == AS.Private); 2171 2172 UseAddrSpaceMapMangling = true; 2173 } 2174 2175 void adjust(LangOptions &Opts) override { 2176 TargetInfo::adjust(Opts); 2177 if (isGenericZero(getTriple())) { 2178 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLGenericIsZeroMap 2179 : &AMDGPUNonOpenCLGenericIsZeroMap; 2180 } else { 2181 AddrSpaceMap = Opts.OpenCL ? &AMDGPUOpenCLPrivateIsZeroMap 2182 : &AMDGPUNonOpenCLPrivateIsZeroMap; 2183 } 2184 } 2185 2186 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 2187 if (GPU <= GK_CAYMAN) 2188 return 32; 2189 2190 if (AddrSpace == AS.Private || AddrSpace == AS.Local) { 2191 return 32; 2192 } 2193 return 64; 2194 } 2195 2196 uint64_t getMaxPointerWidth() const override { 2197 return getTriple().getArch() == llvm::Triple::amdgcn ? 64 : 32; 2198 } 2199 2200 const char * getClobbers() const override { 2201 return ""; 2202 } 2203 2204 ArrayRef<const char *> getGCCRegNames() const override; 2205 2206 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2207 return None; 2208 } 2209 2210 bool validateAsmConstraint(const char *&Name, 2211 TargetInfo::ConstraintInfo &Info) const override { 2212 switch (*Name) { 2213 default: break; 2214 case 'v': // vgpr 2215 case 's': // sgpr 2216 Info.setAllowsRegister(); 2217 return true; 2218 } 2219 return false; 2220 } 2221 2222 bool initFeatureMap(llvm::StringMap<bool> &Features, 2223 DiagnosticsEngine &Diags, StringRef CPU, 2224 const std::vector<std::string> &FeatureVec) const override; 2225 2226 void adjustTargetOptions(const CodeGenOptions &CGOpts, 2227 TargetOptions &TargetOpts) const override { 2228 bool hasFP32Denormals = false; 2229 bool hasFP64Denormals = false; 2230 for (auto &I : TargetOpts.FeaturesAsWritten) { 2231 if (I == "+fp32-denormals" || I == "-fp32-denormals") 2232 hasFP32Denormals = true; 2233 if (I == "+fp64-fp16-denormals" || I == "-fp64-fp16-denormals") 2234 hasFP64Denormals = true; 2235 } 2236 if (!hasFP32Denormals) 2237 TargetOpts.Features.push_back( 2238 (Twine(hasFullSpeedFMAF32(TargetOpts.CPU) && 2239 !CGOpts.FlushDenorm ? '+' : '-') + Twine("fp32-denormals")).str()); 2240 // Always do not flush fp64 or fp16 denorms. 2241 if (!hasFP64Denormals && hasFP64) 2242 TargetOpts.Features.push_back("+fp64-fp16-denormals"); 2243 } 2244 2245 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2246 return llvm::makeArrayRef(BuiltinInfo, 2247 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 2248 } 2249 2250 void getTargetDefines(const LangOptions &Opts, 2251 MacroBuilder &Builder) const override { 2252 if (getTriple().getArch() == llvm::Triple::amdgcn) 2253 Builder.defineMacro("__AMDGCN__"); 2254 else 2255 Builder.defineMacro("__R600__"); 2256 2257 if (hasFMAF) 2258 Builder.defineMacro("__HAS_FMAF__"); 2259 if (hasLDEXPF) 2260 Builder.defineMacro("__HAS_LDEXPF__"); 2261 if (hasFP64) 2262 Builder.defineMacro("__HAS_FP64__"); 2263 } 2264 2265 BuiltinVaListKind getBuiltinVaListKind() const override { 2266 return TargetInfo::CharPtrBuiltinVaList; 2267 } 2268 2269 static GPUKind parseR600Name(StringRef Name) { 2270 return llvm::StringSwitch<GPUKind>(Name) 2271 .Case("r600" , GK_R600) 2272 .Case("rv610", GK_R600) 2273 .Case("rv620", GK_R600) 2274 .Case("rv630", GK_R600) 2275 .Case("rv635", GK_R600) 2276 .Case("rs780", GK_R600) 2277 .Case("rs880", GK_R600) 2278 .Case("rv670", GK_R600_DOUBLE_OPS) 2279 .Case("rv710", GK_R700) 2280 .Case("rv730", GK_R700) 2281 .Case("rv740", GK_R700_DOUBLE_OPS) 2282 .Case("rv770", GK_R700_DOUBLE_OPS) 2283 .Case("palm", GK_EVERGREEN) 2284 .Case("cedar", GK_EVERGREEN) 2285 .Case("sumo", GK_EVERGREEN) 2286 .Case("sumo2", GK_EVERGREEN) 2287 .Case("redwood", GK_EVERGREEN) 2288 .Case("juniper", GK_EVERGREEN) 2289 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 2290 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 2291 .Case("barts", GK_NORTHERN_ISLANDS) 2292 .Case("turks", GK_NORTHERN_ISLANDS) 2293 .Case("caicos", GK_NORTHERN_ISLANDS) 2294 .Case("cayman", GK_CAYMAN) 2295 .Case("aruba", GK_CAYMAN) 2296 .Default(GK_NONE); 2297 } 2298 2299 static GPUKind parseAMDGCNName(StringRef Name) { 2300 return llvm::StringSwitch<GPUKind>(Name) 2301 .Case("tahiti", GK_GFX6) 2302 .Case("pitcairn", GK_GFX6) 2303 .Case("verde", GK_GFX6) 2304 .Case("oland", GK_GFX6) 2305 .Case("hainan", GK_GFX6) 2306 .Case("bonaire", GK_GFX7) 2307 .Case("kabini", GK_GFX7) 2308 .Case("kaveri", GK_GFX7) 2309 .Case("hawaii", GK_GFX7) 2310 .Case("mullins", GK_GFX7) 2311 .Case("gfx700", GK_GFX7) 2312 .Case("gfx701", GK_GFX7) 2313 .Case("gfx702", GK_GFX7) 2314 .Case("tonga", GK_GFX8) 2315 .Case("iceland", GK_GFX8) 2316 .Case("carrizo", GK_GFX8) 2317 .Case("fiji", GK_GFX8) 2318 .Case("stoney", GK_GFX8) 2319 .Case("polaris10", GK_GFX8) 2320 .Case("polaris11", GK_GFX8) 2321 .Case("gfx800", GK_GFX8) 2322 .Case("gfx801", GK_GFX8) 2323 .Case("gfx802", GK_GFX8) 2324 .Case("gfx803", GK_GFX8) 2325 .Case("gfx804", GK_GFX8) 2326 .Case("gfx810", GK_GFX8) 2327 .Case("gfx900", GK_GFX9) 2328 .Case("gfx901", GK_GFX9) 2329 .Default(GK_NONE); 2330 } 2331 2332 bool setCPU(const std::string &Name) override { 2333 if (getTriple().getArch() == llvm::Triple::amdgcn) 2334 GPU = parseAMDGCNName(Name); 2335 else 2336 GPU = parseR600Name(Name); 2337 2338 return GPU != GK_NONE; 2339 } 2340 2341 void setSupportedOpenCLOpts() override { 2342 auto &Opts = getSupportedOpenCLOpts(); 2343 Opts.support("cl_clang_storage_class_specifiers"); 2344 Opts.support("cl_khr_icd"); 2345 2346 if (hasFP64) 2347 Opts.support("cl_khr_fp64"); 2348 if (GPU >= GK_EVERGREEN) { 2349 Opts.support("cl_khr_byte_addressable_store"); 2350 Opts.support("cl_khr_global_int32_base_atomics"); 2351 Opts.support("cl_khr_global_int32_extended_atomics"); 2352 Opts.support("cl_khr_local_int32_base_atomics"); 2353 Opts.support("cl_khr_local_int32_extended_atomics"); 2354 } 2355 if (GPU >= GK_GFX6) { 2356 Opts.support("cl_khr_fp16"); 2357 Opts.support("cl_khr_int64_base_atomics"); 2358 Opts.support("cl_khr_int64_extended_atomics"); 2359 Opts.support("cl_khr_mipmap_image"); 2360 Opts.support("cl_khr_subgroups"); 2361 Opts.support("cl_khr_3d_image_writes"); 2362 Opts.support("cl_amd_media_ops"); 2363 Opts.support("cl_amd_media_ops2"); 2364 } 2365 } 2366 2367 LangAS::ID getOpenCLImageAddrSpace() const override { 2368 return LangAS::opencl_constant; 2369 } 2370 2371 /// \returns Target specific vtbl ptr address space. 2372 unsigned getVtblPtrAddressSpace() const override { 2373 // \todo: We currently have address spaces defined in AMDGPU Backend. It 2374 // would be nice if we could use it here instead of using bare numbers (same 2375 // applies to getDWARFAddressSpace). 2376 return 2; // constant. 2377 } 2378 2379 /// \returns If a target requires an address within a target specific address 2380 /// space \p AddressSpace to be converted in order to be used, then return the 2381 /// corresponding target specific DWARF address space. 2382 /// 2383 /// \returns Otherwise return None and no conversion will be emitted in the 2384 /// DWARF. 2385 Optional<unsigned> getDWARFAddressSpace( 2386 unsigned AddressSpace) const override { 2387 const unsigned DWARF_Private = 1; 2388 const unsigned DWARF_Local = 2; 2389 if (AddressSpace == AS.Private) { 2390 return DWARF_Private; 2391 } else if (AddressSpace == AS.Local) { 2392 return DWARF_Local; 2393 } else { 2394 return None; 2395 } 2396 } 2397 2398 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2399 switch (CC) { 2400 default: 2401 return CCCR_Warning; 2402 case CC_C: 2403 case CC_OpenCLKernel: 2404 return CCCR_OK; 2405 } 2406 } 2407 2408 // In amdgcn target the null pointer in global, constant, and generic 2409 // address space has value 0 but in private and local address space has 2410 // value ~0. 2411 uint64_t getNullPointerValue(unsigned AS) const override { 2412 return AS == LangAS::opencl_local ? ~0 : 0; 2413 } 2414 }; 2415 2416 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 2417 #define BUILTIN(ID, TYPE, ATTRS) \ 2418 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2419 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2420 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2421 #include "clang/Basic/BuiltinsAMDGPU.def" 2422 }; 2423 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 2424 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 2425 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 2426 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 2427 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 2428 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 2429 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 2430 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 2431 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 2432 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 2433 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 2434 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 2435 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 2436 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 2437 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 2438 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 2439 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 2440 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 2441 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 2442 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2443 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2444 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2445 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2446 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2447 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2448 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2449 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2450 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2451 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2452 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2453 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2454 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2455 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2456 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2457 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2458 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2459 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2460 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2461 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2462 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2463 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2464 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2465 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2466 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2467 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2468 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2469 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2470 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2471 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127", 2472 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2473 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2474 }; 2475 2476 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2477 return llvm::makeArrayRef(GCCRegNames); 2478 } 2479 2480 bool AMDGPUTargetInfo::initFeatureMap( 2481 llvm::StringMap<bool> &Features, 2482 DiagnosticsEngine &Diags, StringRef CPU, 2483 const std::vector<std::string> &FeatureVec) const { 2484 2485 // XXX - What does the member GPU mean if device name string passed here? 2486 if (getTriple().getArch() == llvm::Triple::amdgcn) { 2487 if (CPU.empty()) 2488 CPU = "tahiti"; 2489 2490 switch (parseAMDGCNName(CPU)) { 2491 case GK_GFX6: 2492 case GK_GFX7: 2493 break; 2494 2495 case GK_GFX9: 2496 Features["gfx9-insts"] = true; 2497 LLVM_FALLTHROUGH; 2498 case GK_GFX8: 2499 Features["s-memrealtime"] = true; 2500 Features["16-bit-insts"] = true; 2501 Features["dpp"] = true; 2502 break; 2503 2504 case GK_NONE: 2505 return false; 2506 default: 2507 llvm_unreachable("unhandled subtarget"); 2508 } 2509 } else { 2510 if (CPU.empty()) 2511 CPU = "r600"; 2512 2513 switch (parseR600Name(CPU)) { 2514 case GK_R600: 2515 case GK_R700: 2516 case GK_EVERGREEN: 2517 case GK_NORTHERN_ISLANDS: 2518 break; 2519 case GK_R600_DOUBLE_OPS: 2520 case GK_R700_DOUBLE_OPS: 2521 case GK_EVERGREEN_DOUBLE_OPS: 2522 case GK_CAYMAN: 2523 Features["fp64"] = true; 2524 break; 2525 case GK_NONE: 2526 return false; 2527 default: 2528 llvm_unreachable("unhandled subtarget"); 2529 } 2530 } 2531 2532 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeatureVec); 2533 } 2534 2535 const Builtin::Info BuiltinInfoX86[] = { 2536 #define BUILTIN(ID, TYPE, ATTRS) \ 2537 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2538 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2539 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2540 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2541 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2542 #include "clang/Basic/BuiltinsX86.def" 2543 2544 #define BUILTIN(ID, TYPE, ATTRS) \ 2545 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2546 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2547 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2548 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 2549 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 2550 #include "clang/Basic/BuiltinsX86_64.def" 2551 }; 2552 2553 2554 static const char* const GCCRegNames[] = { 2555 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2556 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2557 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2558 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2559 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2560 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2561 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2562 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2563 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2564 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2565 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2566 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2567 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2568 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2569 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2570 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2571 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2572 "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", 2573 }; 2574 2575 const TargetInfo::AddlRegName AddlRegNames[] = { 2576 { { "al", "ah", "eax", "rax" }, 0 }, 2577 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2578 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2579 { { "dl", "dh", "edx", "rdx" }, 1 }, 2580 { { "esi", "rsi" }, 4 }, 2581 { { "edi", "rdi" }, 5 }, 2582 { { "esp", "rsp" }, 7 }, 2583 { { "ebp", "rbp" }, 6 }, 2584 { { "r8d", "r8w", "r8b" }, 38 }, 2585 { { "r9d", "r9w", "r9b" }, 39 }, 2586 { { "r10d", "r10w", "r10b" }, 40 }, 2587 { { "r11d", "r11w", "r11b" }, 41 }, 2588 { { "r12d", "r12w", "r12b" }, 42 }, 2589 { { "r13d", "r13w", "r13b" }, 43 }, 2590 { { "r14d", "r14w", "r14b" }, 44 }, 2591 { { "r15d", "r15w", "r15b" }, 45 }, 2592 }; 2593 2594 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2595 // most of the implementation can be shared. 2596 class X86TargetInfo : public TargetInfo { 2597 enum X86SSEEnum { 2598 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2599 } SSELevel = NoSSE; 2600 enum MMX3DNowEnum { 2601 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2602 } MMX3DNowLevel = NoMMX3DNow; 2603 enum XOPEnum { 2604 NoXOP, 2605 SSE4A, 2606 FMA4, 2607 XOP 2608 } XOPLevel = NoXOP; 2609 2610 bool HasAES = false; 2611 bool HasPCLMUL = false; 2612 bool HasLZCNT = false; 2613 bool HasRDRND = false; 2614 bool HasFSGSBASE = false; 2615 bool HasBMI = false; 2616 bool HasBMI2 = false; 2617 bool HasPOPCNT = false; 2618 bool HasRTM = false; 2619 bool HasPRFCHW = false; 2620 bool HasRDSEED = false; 2621 bool HasADX = false; 2622 bool HasTBM = false; 2623 bool HasLWP = false; 2624 bool HasFMA = false; 2625 bool HasF16C = false; 2626 bool HasAVX512CD = false; 2627 bool HasAVX512VPOPCNTDQ = false; 2628 bool HasAVX512ER = false; 2629 bool HasAVX512PF = false; 2630 bool HasAVX512DQ = false; 2631 bool HasAVX512BW = false; 2632 bool HasAVX512VL = false; 2633 bool HasAVX512VBMI = false; 2634 bool HasAVX512IFMA = false; 2635 bool HasSHA = false; 2636 bool HasMPX = false; 2637 bool HasSGX = false; 2638 bool HasCX16 = false; 2639 bool HasFXSR = false; 2640 bool HasXSAVE = false; 2641 bool HasXSAVEOPT = false; 2642 bool HasXSAVEC = false; 2643 bool HasXSAVES = false; 2644 bool HasMWAITX = false; 2645 bool HasCLZERO = false; 2646 bool HasPKU = false; 2647 bool HasCLFLUSHOPT = false; 2648 bool HasCLWB = false; 2649 bool HasMOVBE = false; 2650 bool HasPREFETCHWT1 = false; 2651 2652 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2653 /// 2654 /// Each enumeration represents a particular CPU supported by Clang. These 2655 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2656 enum CPUKind { 2657 CK_Generic, 2658 2659 /// \name i386 2660 /// i386-generation processors. 2661 //@{ 2662 CK_i386, 2663 //@} 2664 2665 /// \name i486 2666 /// i486-generation processors. 2667 //@{ 2668 CK_i486, 2669 CK_WinChipC6, 2670 CK_WinChip2, 2671 CK_C3, 2672 //@} 2673 2674 /// \name i586 2675 /// i586-generation processors, P5 microarchitecture based. 2676 //@{ 2677 CK_i586, 2678 CK_Pentium, 2679 CK_PentiumMMX, 2680 //@} 2681 2682 /// \name i686 2683 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2684 //@{ 2685 CK_i686, 2686 CK_PentiumPro, 2687 CK_Pentium2, 2688 CK_Pentium3, 2689 CK_Pentium3M, 2690 CK_PentiumM, 2691 CK_C3_2, 2692 2693 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2694 /// Clang however has some logic to suport this. 2695 // FIXME: Warn, deprecate, and potentially remove this. 2696 CK_Yonah, 2697 //@} 2698 2699 /// \name Netburst 2700 /// Netburst microarchitecture based processors. 2701 //@{ 2702 CK_Pentium4, 2703 CK_Pentium4M, 2704 CK_Prescott, 2705 CK_Nocona, 2706 //@} 2707 2708 /// \name Core 2709 /// Core microarchitecture based processors. 2710 //@{ 2711 CK_Core2, 2712 2713 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2714 /// codename which GCC no longer accepts as an option to -march, but Clang 2715 /// has some logic for recognizing it. 2716 // FIXME: Warn, deprecate, and potentially remove this. 2717 CK_Penryn, 2718 //@} 2719 2720 /// \name Atom 2721 /// Atom processors 2722 //@{ 2723 CK_Bonnell, 2724 CK_Silvermont, 2725 //@} 2726 2727 /// \name Nehalem 2728 /// Nehalem microarchitecture based processors. 2729 CK_Nehalem, 2730 2731 /// \name Westmere 2732 /// Westmere microarchitecture based processors. 2733 CK_Westmere, 2734 2735 /// \name Sandy Bridge 2736 /// Sandy Bridge microarchitecture based processors. 2737 CK_SandyBridge, 2738 2739 /// \name Ivy Bridge 2740 /// Ivy Bridge microarchitecture based processors. 2741 CK_IvyBridge, 2742 2743 /// \name Haswell 2744 /// Haswell microarchitecture based processors. 2745 CK_Haswell, 2746 2747 /// \name Broadwell 2748 /// Broadwell microarchitecture based processors. 2749 CK_Broadwell, 2750 2751 /// \name Skylake Client 2752 /// Skylake client microarchitecture based processors. 2753 CK_SkylakeClient, 2754 2755 /// \name Skylake Server 2756 /// Skylake server microarchitecture based processors. 2757 CK_SkylakeServer, 2758 2759 /// \name Cannonlake Client 2760 /// Cannonlake client microarchitecture based processors. 2761 CK_Cannonlake, 2762 2763 /// \name Knights Landing 2764 /// Knights Landing processor. 2765 CK_KNL, 2766 2767 /// \name Lakemont 2768 /// Lakemont microarchitecture based processors. 2769 CK_Lakemont, 2770 2771 /// \name K6 2772 /// K6 architecture processors. 2773 //@{ 2774 CK_K6, 2775 CK_K6_2, 2776 CK_K6_3, 2777 //@} 2778 2779 /// \name K7 2780 /// K7 architecture processors. 2781 //@{ 2782 CK_Athlon, 2783 CK_AthlonThunderbird, 2784 CK_Athlon4, 2785 CK_AthlonXP, 2786 CK_AthlonMP, 2787 //@} 2788 2789 /// \name K8 2790 /// K8 architecture processors. 2791 //@{ 2792 CK_Athlon64, 2793 CK_Athlon64SSE3, 2794 CK_AthlonFX, 2795 CK_K8, 2796 CK_K8SSE3, 2797 CK_Opteron, 2798 CK_OpteronSSE3, 2799 CK_AMDFAM10, 2800 //@} 2801 2802 /// \name Bobcat 2803 /// Bobcat architecture processors. 2804 //@{ 2805 CK_BTVER1, 2806 CK_BTVER2, 2807 //@} 2808 2809 /// \name Bulldozer 2810 /// Bulldozer architecture processors. 2811 //@{ 2812 CK_BDVER1, 2813 CK_BDVER2, 2814 CK_BDVER3, 2815 CK_BDVER4, 2816 //@} 2817 2818 /// \name zen 2819 /// Zen architecture processors. 2820 //@{ 2821 CK_ZNVER1, 2822 //@} 2823 2824 /// This specification is deprecated and will be removed in the future. 2825 /// Users should prefer \see CK_K8. 2826 // FIXME: Warn on this when the CPU is set to it. 2827 //@{ 2828 CK_x86_64, 2829 //@} 2830 2831 /// \name Geode 2832 /// Geode processors. 2833 //@{ 2834 CK_Geode 2835 //@} 2836 } CPU = CK_Generic; 2837 2838 CPUKind getCPUKind(StringRef CPU) const { 2839 return llvm::StringSwitch<CPUKind>(CPU) 2840 .Case("i386", CK_i386) 2841 .Case("i486", CK_i486) 2842 .Case("winchip-c6", CK_WinChipC6) 2843 .Case("winchip2", CK_WinChip2) 2844 .Case("c3", CK_C3) 2845 .Case("i586", CK_i586) 2846 .Case("pentium", CK_Pentium) 2847 .Case("pentium-mmx", CK_PentiumMMX) 2848 .Case("i686", CK_i686) 2849 .Case("pentiumpro", CK_PentiumPro) 2850 .Case("pentium2", CK_Pentium2) 2851 .Case("pentium3", CK_Pentium3) 2852 .Case("pentium3m", CK_Pentium3M) 2853 .Case("pentium-m", CK_PentiumM) 2854 .Case("c3-2", CK_C3_2) 2855 .Case("yonah", CK_Yonah) 2856 .Case("pentium4", CK_Pentium4) 2857 .Case("pentium4m", CK_Pentium4M) 2858 .Case("prescott", CK_Prescott) 2859 .Case("nocona", CK_Nocona) 2860 .Case("core2", CK_Core2) 2861 .Case("penryn", CK_Penryn) 2862 .Case("bonnell", CK_Bonnell) 2863 .Case("atom", CK_Bonnell) // Legacy name. 2864 .Case("silvermont", CK_Silvermont) 2865 .Case("slm", CK_Silvermont) // Legacy name. 2866 .Case("nehalem", CK_Nehalem) 2867 .Case("corei7", CK_Nehalem) // Legacy name. 2868 .Case("westmere", CK_Westmere) 2869 .Case("sandybridge", CK_SandyBridge) 2870 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2871 .Case("ivybridge", CK_IvyBridge) 2872 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2873 .Case("haswell", CK_Haswell) 2874 .Case("core-avx2", CK_Haswell) // Legacy name. 2875 .Case("broadwell", CK_Broadwell) 2876 .Case("skylake", CK_SkylakeClient) 2877 .Case("skylake-avx512", CK_SkylakeServer) 2878 .Case("skx", CK_SkylakeServer) // Legacy name. 2879 .Case("cannonlake", CK_Cannonlake) 2880 .Case("knl", CK_KNL) 2881 .Case("lakemont", CK_Lakemont) 2882 .Case("k6", CK_K6) 2883 .Case("k6-2", CK_K6_2) 2884 .Case("k6-3", CK_K6_3) 2885 .Case("athlon", CK_Athlon) 2886 .Case("athlon-tbird", CK_AthlonThunderbird) 2887 .Case("athlon-4", CK_Athlon4) 2888 .Case("athlon-xp", CK_AthlonXP) 2889 .Case("athlon-mp", CK_AthlonMP) 2890 .Case("athlon64", CK_Athlon64) 2891 .Case("athlon64-sse3", CK_Athlon64SSE3) 2892 .Case("athlon-fx", CK_AthlonFX) 2893 .Case("k8", CK_K8) 2894 .Case("k8-sse3", CK_K8SSE3) 2895 .Case("opteron", CK_Opteron) 2896 .Case("opteron-sse3", CK_OpteronSSE3) 2897 .Case("barcelona", CK_AMDFAM10) 2898 .Case("amdfam10", CK_AMDFAM10) 2899 .Case("btver1", CK_BTVER1) 2900 .Case("btver2", CK_BTVER2) 2901 .Case("bdver1", CK_BDVER1) 2902 .Case("bdver2", CK_BDVER2) 2903 .Case("bdver3", CK_BDVER3) 2904 .Case("bdver4", CK_BDVER4) 2905 .Case("znver1", CK_ZNVER1) 2906 .Case("x86-64", CK_x86_64) 2907 .Case("geode", CK_Geode) 2908 .Default(CK_Generic); 2909 } 2910 2911 enum FPMathKind { 2912 FP_Default, 2913 FP_SSE, 2914 FP_387 2915 } FPMath = FP_Default; 2916 2917 public: 2918 X86TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 2919 : TargetInfo(Triple) { 2920 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 2921 } 2922 unsigned getFloatEvalMethod() const override { 2923 // X87 evaluates with 80 bits "long double" precision. 2924 return SSELevel == NoSSE ? 2 : 0; 2925 } 2926 ArrayRef<const char *> getGCCRegNames() const override { 2927 return llvm::makeArrayRef(GCCRegNames); 2928 } 2929 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2930 return None; 2931 } 2932 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2933 return llvm::makeArrayRef(AddlRegNames); 2934 } 2935 bool validateCpuSupports(StringRef Name) const override; 2936 bool validateAsmConstraint(const char *&Name, 2937 TargetInfo::ConstraintInfo &info) const override; 2938 2939 bool validateGlobalRegisterVariable(StringRef RegName, 2940 unsigned RegSize, 2941 bool &HasSizeMismatch) const override { 2942 // esp and ebp are the only 32-bit registers the x86 backend can currently 2943 // handle. 2944 if (RegName.equals("esp") || RegName.equals("ebp")) { 2945 // Check that the register size is 32-bit. 2946 HasSizeMismatch = RegSize != 32; 2947 return true; 2948 } 2949 2950 return false; 2951 } 2952 2953 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2954 2955 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2956 2957 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2958 2959 std::string convertConstraint(const char *&Constraint) const override; 2960 const char *getClobbers() const override { 2961 return "~{dirflag},~{fpsr},~{flags}"; 2962 } 2963 2964 StringRef getConstraintRegister(const StringRef &Constraint, 2965 const StringRef &Expression) const override { 2966 StringRef::iterator I, E; 2967 for (I = Constraint.begin(), E = Constraint.end(); I != E; ++I) { 2968 if (isalpha(*I)) 2969 break; 2970 } 2971 if (I == E) 2972 return ""; 2973 switch (*I) { 2974 // For the register constraints, return the matching register name 2975 case 'a': 2976 return "ax"; 2977 case 'b': 2978 return "bx"; 2979 case 'c': 2980 return "cx"; 2981 case 'd': 2982 return "dx"; 2983 case 'S': 2984 return "si"; 2985 case 'D': 2986 return "di"; 2987 // In case the constraint is 'r' we need to return Expression 2988 case 'r': 2989 return Expression; 2990 default: 2991 // Default value if there is no constraint for the register 2992 return ""; 2993 } 2994 return ""; 2995 } 2996 2997 void getTargetDefines(const LangOptions &Opts, 2998 MacroBuilder &Builder) const override; 2999 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 3000 bool Enabled); 3001 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 3002 bool Enabled); 3003 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3004 bool Enabled); 3005 void setFeatureEnabled(llvm::StringMap<bool> &Features, 3006 StringRef Name, bool Enabled) const override { 3007 setFeatureEnabledImpl(Features, Name, Enabled); 3008 } 3009 // This exists purely to cut down on the number of virtual calls in 3010 // initFeatureMap which calls this repeatedly. 3011 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3012 StringRef Name, bool Enabled); 3013 bool 3014 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 3015 StringRef CPU, 3016 const std::vector<std::string> &FeaturesVec) const override; 3017 bool hasFeature(StringRef Feature) const override; 3018 bool handleTargetFeatures(std::vector<std::string> &Features, 3019 DiagnosticsEngine &Diags) override; 3020 StringRef getABI() const override { 3021 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 3022 return "avx512"; 3023 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 3024 return "avx"; 3025 if (getTriple().getArch() == llvm::Triple::x86 && 3026 MMX3DNowLevel == NoMMX3DNow) 3027 return "no-mmx"; 3028 return ""; 3029 } 3030 bool setCPU(const std::string &Name) override { 3031 CPU = getCPUKind(Name); 3032 3033 // Perform any per-CPU checks necessary to determine if this CPU is 3034 // acceptable. 3035 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 3036 // invalid without explaining *why*. 3037 switch (CPU) { 3038 case CK_Generic: 3039 // No processor selected! 3040 return false; 3041 3042 case CK_i386: 3043 case CK_i486: 3044 case CK_WinChipC6: 3045 case CK_WinChip2: 3046 case CK_C3: 3047 case CK_i586: 3048 case CK_Pentium: 3049 case CK_PentiumMMX: 3050 case CK_i686: 3051 case CK_PentiumPro: 3052 case CK_Pentium2: 3053 case CK_Pentium3: 3054 case CK_Pentium3M: 3055 case CK_PentiumM: 3056 case CK_Yonah: 3057 case CK_C3_2: 3058 case CK_Pentium4: 3059 case CK_Pentium4M: 3060 case CK_Lakemont: 3061 case CK_Prescott: 3062 case CK_K6: 3063 case CK_K6_2: 3064 case CK_K6_3: 3065 case CK_Athlon: 3066 case CK_AthlonThunderbird: 3067 case CK_Athlon4: 3068 case CK_AthlonXP: 3069 case CK_AthlonMP: 3070 case CK_Geode: 3071 // Only accept certain architectures when compiling in 32-bit mode. 3072 if (getTriple().getArch() != llvm::Triple::x86) 3073 return false; 3074 3075 // Fallthrough 3076 case CK_Nocona: 3077 case CK_Core2: 3078 case CK_Penryn: 3079 case CK_Bonnell: 3080 case CK_Silvermont: 3081 case CK_Nehalem: 3082 case CK_Westmere: 3083 case CK_SandyBridge: 3084 case CK_IvyBridge: 3085 case CK_Haswell: 3086 case CK_Broadwell: 3087 case CK_SkylakeClient: 3088 case CK_SkylakeServer: 3089 case CK_Cannonlake: 3090 case CK_KNL: 3091 case CK_Athlon64: 3092 case CK_Athlon64SSE3: 3093 case CK_AthlonFX: 3094 case CK_K8: 3095 case CK_K8SSE3: 3096 case CK_Opteron: 3097 case CK_OpteronSSE3: 3098 case CK_AMDFAM10: 3099 case CK_BTVER1: 3100 case CK_BTVER2: 3101 case CK_BDVER1: 3102 case CK_BDVER2: 3103 case CK_BDVER3: 3104 case CK_BDVER4: 3105 case CK_ZNVER1: 3106 case CK_x86_64: 3107 return true; 3108 } 3109 llvm_unreachable("Unhandled CPU kind"); 3110 } 3111 3112 bool setFPMath(StringRef Name) override; 3113 3114 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3115 // Most of the non-ARM calling conventions are i386 conventions. 3116 switch (CC) { 3117 case CC_X86ThisCall: 3118 case CC_X86FastCall: 3119 case CC_X86StdCall: 3120 case CC_X86VectorCall: 3121 case CC_X86RegCall: 3122 case CC_C: 3123 case CC_Swift: 3124 case CC_X86Pascal: 3125 case CC_IntelOclBicc: 3126 return CCCR_OK; 3127 default: 3128 return CCCR_Warning; 3129 } 3130 } 3131 3132 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 3133 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 3134 } 3135 3136 bool hasSjLjLowering() const override { 3137 return true; 3138 } 3139 3140 void setSupportedOpenCLOpts() override { 3141 getSupportedOpenCLOpts().supportAll(); 3142 } 3143 }; 3144 3145 bool X86TargetInfo::setFPMath(StringRef Name) { 3146 if (Name == "387") { 3147 FPMath = FP_387; 3148 return true; 3149 } 3150 if (Name == "sse") { 3151 FPMath = FP_SSE; 3152 return true; 3153 } 3154 return false; 3155 } 3156 3157 bool X86TargetInfo::initFeatureMap( 3158 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 3159 const std::vector<std::string> &FeaturesVec) const { 3160 // FIXME: This *really* should not be here. 3161 // X86_64 always has SSE2. 3162 if (getTriple().getArch() == llvm::Triple::x86_64) 3163 setFeatureEnabledImpl(Features, "sse2", true); 3164 3165 const CPUKind Kind = getCPUKind(CPU); 3166 3167 // Enable X87 for all X86 processors but Lakemont. 3168 if (Kind != CK_Lakemont) 3169 setFeatureEnabledImpl(Features, "x87", true); 3170 3171 switch (Kind) { 3172 case CK_Generic: 3173 case CK_i386: 3174 case CK_i486: 3175 case CK_i586: 3176 case CK_Pentium: 3177 case CK_i686: 3178 case CK_PentiumPro: 3179 case CK_Lakemont: 3180 break; 3181 case CK_PentiumMMX: 3182 case CK_Pentium2: 3183 case CK_K6: 3184 case CK_WinChipC6: 3185 setFeatureEnabledImpl(Features, "mmx", true); 3186 break; 3187 case CK_Pentium3: 3188 case CK_Pentium3M: 3189 case CK_C3_2: 3190 setFeatureEnabledImpl(Features, "sse", true); 3191 setFeatureEnabledImpl(Features, "fxsr", true); 3192 break; 3193 case CK_PentiumM: 3194 case CK_Pentium4: 3195 case CK_Pentium4M: 3196 case CK_x86_64: 3197 setFeatureEnabledImpl(Features, "sse2", true); 3198 setFeatureEnabledImpl(Features, "fxsr", true); 3199 break; 3200 case CK_Yonah: 3201 case CK_Prescott: 3202 case CK_Nocona: 3203 setFeatureEnabledImpl(Features, "sse3", true); 3204 setFeatureEnabledImpl(Features, "fxsr", true); 3205 setFeatureEnabledImpl(Features, "cx16", true); 3206 break; 3207 case CK_Core2: 3208 case CK_Bonnell: 3209 setFeatureEnabledImpl(Features, "ssse3", true); 3210 setFeatureEnabledImpl(Features, "fxsr", true); 3211 setFeatureEnabledImpl(Features, "cx16", true); 3212 break; 3213 case CK_Penryn: 3214 setFeatureEnabledImpl(Features, "sse4.1", true); 3215 setFeatureEnabledImpl(Features, "fxsr", true); 3216 setFeatureEnabledImpl(Features, "cx16", true); 3217 break; 3218 case CK_Cannonlake: 3219 setFeatureEnabledImpl(Features, "avx512ifma", true); 3220 setFeatureEnabledImpl(Features, "avx512vbmi", true); 3221 setFeatureEnabledImpl(Features, "sha", true); 3222 LLVM_FALLTHROUGH; 3223 case CK_SkylakeServer: 3224 setFeatureEnabledImpl(Features, "avx512f", true); 3225 setFeatureEnabledImpl(Features, "avx512cd", true); 3226 setFeatureEnabledImpl(Features, "avx512dq", true); 3227 setFeatureEnabledImpl(Features, "avx512bw", true); 3228 setFeatureEnabledImpl(Features, "avx512vl", true); 3229 setFeatureEnabledImpl(Features, "pku", true); 3230 setFeatureEnabledImpl(Features, "clwb", true); 3231 LLVM_FALLTHROUGH; 3232 case CK_SkylakeClient: 3233 setFeatureEnabledImpl(Features, "xsavec", true); 3234 setFeatureEnabledImpl(Features, "xsaves", true); 3235 setFeatureEnabledImpl(Features, "mpx", true); 3236 setFeatureEnabledImpl(Features, "sgx", true); 3237 setFeatureEnabledImpl(Features, "clflushopt", true); 3238 setFeatureEnabledImpl(Features, "rtm", true); 3239 LLVM_FALLTHROUGH; 3240 case CK_Broadwell: 3241 setFeatureEnabledImpl(Features, "rdseed", true); 3242 setFeatureEnabledImpl(Features, "adx", true); 3243 LLVM_FALLTHROUGH; 3244 case CK_Haswell: 3245 setFeatureEnabledImpl(Features, "avx2", true); 3246 setFeatureEnabledImpl(Features, "lzcnt", true); 3247 setFeatureEnabledImpl(Features, "bmi", true); 3248 setFeatureEnabledImpl(Features, "bmi2", true); 3249 setFeatureEnabledImpl(Features, "fma", true); 3250 setFeatureEnabledImpl(Features, "movbe", true); 3251 LLVM_FALLTHROUGH; 3252 case CK_IvyBridge: 3253 setFeatureEnabledImpl(Features, "rdrnd", true); 3254 setFeatureEnabledImpl(Features, "f16c", true); 3255 setFeatureEnabledImpl(Features, "fsgsbase", true); 3256 LLVM_FALLTHROUGH; 3257 case CK_SandyBridge: 3258 setFeatureEnabledImpl(Features, "avx", true); 3259 setFeatureEnabledImpl(Features, "xsave", true); 3260 setFeatureEnabledImpl(Features, "xsaveopt", true); 3261 LLVM_FALLTHROUGH; 3262 case CK_Westmere: 3263 case CK_Silvermont: 3264 setFeatureEnabledImpl(Features, "aes", true); 3265 setFeatureEnabledImpl(Features, "pclmul", true); 3266 LLVM_FALLTHROUGH; 3267 case CK_Nehalem: 3268 setFeatureEnabledImpl(Features, "sse4.2", true); 3269 setFeatureEnabledImpl(Features, "fxsr", true); 3270 setFeatureEnabledImpl(Features, "cx16", true); 3271 break; 3272 case CK_KNL: 3273 setFeatureEnabledImpl(Features, "avx512f", true); 3274 setFeatureEnabledImpl(Features, "avx512cd", true); 3275 setFeatureEnabledImpl(Features, "avx512er", true); 3276 setFeatureEnabledImpl(Features, "avx512pf", true); 3277 setFeatureEnabledImpl(Features, "prefetchwt1", true); 3278 setFeatureEnabledImpl(Features, "fxsr", true); 3279 setFeatureEnabledImpl(Features, "rdseed", true); 3280 setFeatureEnabledImpl(Features, "adx", true); 3281 setFeatureEnabledImpl(Features, "lzcnt", true); 3282 setFeatureEnabledImpl(Features, "bmi", true); 3283 setFeatureEnabledImpl(Features, "bmi2", true); 3284 setFeatureEnabledImpl(Features, "rtm", true); 3285 setFeatureEnabledImpl(Features, "fma", true); 3286 setFeatureEnabledImpl(Features, "rdrnd", true); 3287 setFeatureEnabledImpl(Features, "f16c", true); 3288 setFeatureEnabledImpl(Features, "fsgsbase", true); 3289 setFeatureEnabledImpl(Features, "aes", true); 3290 setFeatureEnabledImpl(Features, "pclmul", true); 3291 setFeatureEnabledImpl(Features, "cx16", true); 3292 setFeatureEnabledImpl(Features, "xsaveopt", true); 3293 setFeatureEnabledImpl(Features, "xsave", true); 3294 setFeatureEnabledImpl(Features, "movbe", true); 3295 break; 3296 case CK_K6_2: 3297 case CK_K6_3: 3298 case CK_WinChip2: 3299 case CK_C3: 3300 setFeatureEnabledImpl(Features, "3dnow", true); 3301 break; 3302 case CK_Athlon: 3303 case CK_AthlonThunderbird: 3304 case CK_Geode: 3305 setFeatureEnabledImpl(Features, "3dnowa", true); 3306 break; 3307 case CK_Athlon4: 3308 case CK_AthlonXP: 3309 case CK_AthlonMP: 3310 setFeatureEnabledImpl(Features, "sse", true); 3311 setFeatureEnabledImpl(Features, "3dnowa", true); 3312 setFeatureEnabledImpl(Features, "fxsr", true); 3313 break; 3314 case CK_K8: 3315 case CK_Opteron: 3316 case CK_Athlon64: 3317 case CK_AthlonFX: 3318 setFeatureEnabledImpl(Features, "sse2", true); 3319 setFeatureEnabledImpl(Features, "3dnowa", true); 3320 setFeatureEnabledImpl(Features, "fxsr", true); 3321 break; 3322 case CK_AMDFAM10: 3323 setFeatureEnabledImpl(Features, "sse4a", true); 3324 setFeatureEnabledImpl(Features, "lzcnt", true); 3325 setFeatureEnabledImpl(Features, "popcnt", true); 3326 LLVM_FALLTHROUGH; 3327 case CK_K8SSE3: 3328 case CK_OpteronSSE3: 3329 case CK_Athlon64SSE3: 3330 setFeatureEnabledImpl(Features, "sse3", true); 3331 setFeatureEnabledImpl(Features, "3dnowa", true); 3332 setFeatureEnabledImpl(Features, "fxsr", true); 3333 break; 3334 case CK_BTVER2: 3335 setFeatureEnabledImpl(Features, "avx", true); 3336 setFeatureEnabledImpl(Features, "aes", true); 3337 setFeatureEnabledImpl(Features, "pclmul", true); 3338 setFeatureEnabledImpl(Features, "bmi", true); 3339 setFeatureEnabledImpl(Features, "f16c", true); 3340 setFeatureEnabledImpl(Features, "xsaveopt", true); 3341 LLVM_FALLTHROUGH; 3342 case CK_BTVER1: 3343 setFeatureEnabledImpl(Features, "ssse3", true); 3344 setFeatureEnabledImpl(Features, "sse4a", true); 3345 setFeatureEnabledImpl(Features, "lzcnt", true); 3346 setFeatureEnabledImpl(Features, "popcnt", true); 3347 setFeatureEnabledImpl(Features, "prfchw", true); 3348 setFeatureEnabledImpl(Features, "cx16", true); 3349 setFeatureEnabledImpl(Features, "fxsr", true); 3350 break; 3351 case CK_ZNVER1: 3352 setFeatureEnabledImpl(Features, "adx", true); 3353 setFeatureEnabledImpl(Features, "aes", true); 3354 setFeatureEnabledImpl(Features, "avx2", true); 3355 setFeatureEnabledImpl(Features, "bmi", true); 3356 setFeatureEnabledImpl(Features, "bmi2", true); 3357 setFeatureEnabledImpl(Features, "clflushopt", true); 3358 setFeatureEnabledImpl(Features, "clzero", true); 3359 setFeatureEnabledImpl(Features, "cx16", true); 3360 setFeatureEnabledImpl(Features, "f16c", true); 3361 setFeatureEnabledImpl(Features, "fma", true); 3362 setFeatureEnabledImpl(Features, "fsgsbase", true); 3363 setFeatureEnabledImpl(Features, "fxsr", true); 3364 setFeatureEnabledImpl(Features, "lzcnt", true); 3365 setFeatureEnabledImpl(Features, "mwaitx", true); 3366 setFeatureEnabledImpl(Features, "movbe", true); 3367 setFeatureEnabledImpl(Features, "pclmul", true); 3368 setFeatureEnabledImpl(Features, "popcnt", true); 3369 setFeatureEnabledImpl(Features, "prfchw", true); 3370 setFeatureEnabledImpl(Features, "rdrnd", true); 3371 setFeatureEnabledImpl(Features, "rdseed", true); 3372 setFeatureEnabledImpl(Features, "sha", true); 3373 setFeatureEnabledImpl(Features, "sse4a", true); 3374 setFeatureEnabledImpl(Features, "xsave", true); 3375 setFeatureEnabledImpl(Features, "xsavec", true); 3376 setFeatureEnabledImpl(Features, "xsaveopt", true); 3377 setFeatureEnabledImpl(Features, "xsaves", true); 3378 break; 3379 case CK_BDVER4: 3380 setFeatureEnabledImpl(Features, "avx2", true); 3381 setFeatureEnabledImpl(Features, "bmi2", true); 3382 setFeatureEnabledImpl(Features, "mwaitx", true); 3383 LLVM_FALLTHROUGH; 3384 case CK_BDVER3: 3385 setFeatureEnabledImpl(Features, "fsgsbase", true); 3386 setFeatureEnabledImpl(Features, "xsaveopt", true); 3387 LLVM_FALLTHROUGH; 3388 case CK_BDVER2: 3389 setFeatureEnabledImpl(Features, "bmi", true); 3390 setFeatureEnabledImpl(Features, "fma", true); 3391 setFeatureEnabledImpl(Features, "f16c", true); 3392 setFeatureEnabledImpl(Features, "tbm", true); 3393 LLVM_FALLTHROUGH; 3394 case CK_BDVER1: 3395 // xop implies avx, sse4a and fma4. 3396 setFeatureEnabledImpl(Features, "xop", true); 3397 setFeatureEnabledImpl(Features, "lwp", true); 3398 setFeatureEnabledImpl(Features, "lzcnt", true); 3399 setFeatureEnabledImpl(Features, "aes", true); 3400 setFeatureEnabledImpl(Features, "pclmul", true); 3401 setFeatureEnabledImpl(Features, "prfchw", true); 3402 setFeatureEnabledImpl(Features, "cx16", true); 3403 setFeatureEnabledImpl(Features, "fxsr", true); 3404 setFeatureEnabledImpl(Features, "xsave", true); 3405 break; 3406 } 3407 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 3408 return false; 3409 3410 // Can't do this earlier because we need to be able to explicitly enable 3411 // or disable these features and the things that they depend upon. 3412 3413 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 3414 auto I = Features.find("sse4.2"); 3415 if (I != Features.end() && I->getValue() && 3416 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 3417 FeaturesVec.end()) 3418 Features["popcnt"] = true; 3419 3420 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 3421 I = Features.find("3dnow"); 3422 if (I != Features.end() && I->getValue() && 3423 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 3424 FeaturesVec.end()) 3425 Features["prfchw"] = true; 3426 3427 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 3428 // then enable MMX. 3429 I = Features.find("sse"); 3430 if (I != Features.end() && I->getValue() && 3431 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 3432 FeaturesVec.end()) 3433 Features["mmx"] = true; 3434 3435 return true; 3436 } 3437 3438 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 3439 X86SSEEnum Level, bool Enabled) { 3440 if (Enabled) { 3441 switch (Level) { 3442 case AVX512F: 3443 Features["avx512f"] = true; 3444 LLVM_FALLTHROUGH; 3445 case AVX2: 3446 Features["avx2"] = true; 3447 LLVM_FALLTHROUGH; 3448 case AVX: 3449 Features["avx"] = true; 3450 Features["xsave"] = true; 3451 LLVM_FALLTHROUGH; 3452 case SSE42: 3453 Features["sse4.2"] = true; 3454 LLVM_FALLTHROUGH; 3455 case SSE41: 3456 Features["sse4.1"] = true; 3457 LLVM_FALLTHROUGH; 3458 case SSSE3: 3459 Features["ssse3"] = true; 3460 LLVM_FALLTHROUGH; 3461 case SSE3: 3462 Features["sse3"] = true; 3463 LLVM_FALLTHROUGH; 3464 case SSE2: 3465 Features["sse2"] = true; 3466 LLVM_FALLTHROUGH; 3467 case SSE1: 3468 Features["sse"] = true; 3469 LLVM_FALLTHROUGH; 3470 case NoSSE: 3471 break; 3472 } 3473 return; 3474 } 3475 3476 switch (Level) { 3477 case NoSSE: 3478 case SSE1: 3479 Features["sse"] = false; 3480 LLVM_FALLTHROUGH; 3481 case SSE2: 3482 Features["sse2"] = Features["pclmul"] = Features["aes"] = 3483 Features["sha"] = false; 3484 LLVM_FALLTHROUGH; 3485 case SSE3: 3486 Features["sse3"] = false; 3487 setXOPLevel(Features, NoXOP, false); 3488 LLVM_FALLTHROUGH; 3489 case SSSE3: 3490 Features["ssse3"] = false; 3491 LLVM_FALLTHROUGH; 3492 case SSE41: 3493 Features["sse4.1"] = false; 3494 LLVM_FALLTHROUGH; 3495 case SSE42: 3496 Features["sse4.2"] = false; 3497 LLVM_FALLTHROUGH; 3498 case AVX: 3499 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 3500 Features["xsaveopt"] = false; 3501 setXOPLevel(Features, FMA4, false); 3502 LLVM_FALLTHROUGH; 3503 case AVX2: 3504 Features["avx2"] = false; 3505 LLVM_FALLTHROUGH; 3506 case AVX512F: 3507 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 3508 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 3509 Features["avx512vl"] = Features["avx512vbmi"] = 3510 Features["avx512ifma"] = Features["avx512vpopcntdq"] = false; 3511 } 3512 } 3513 3514 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 3515 MMX3DNowEnum Level, bool Enabled) { 3516 if (Enabled) { 3517 switch (Level) { 3518 case AMD3DNowAthlon: 3519 Features["3dnowa"] = true; 3520 LLVM_FALLTHROUGH; 3521 case AMD3DNow: 3522 Features["3dnow"] = true; 3523 LLVM_FALLTHROUGH; 3524 case MMX: 3525 Features["mmx"] = true; 3526 LLVM_FALLTHROUGH; 3527 case NoMMX3DNow: 3528 break; 3529 } 3530 return; 3531 } 3532 3533 switch (Level) { 3534 case NoMMX3DNow: 3535 case MMX: 3536 Features["mmx"] = false; 3537 LLVM_FALLTHROUGH; 3538 case AMD3DNow: 3539 Features["3dnow"] = false; 3540 LLVM_FALLTHROUGH; 3541 case AMD3DNowAthlon: 3542 Features["3dnowa"] = false; 3543 } 3544 } 3545 3546 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 3547 bool Enabled) { 3548 if (Enabled) { 3549 switch (Level) { 3550 case XOP: 3551 Features["xop"] = true; 3552 LLVM_FALLTHROUGH; 3553 case FMA4: 3554 Features["fma4"] = true; 3555 setSSELevel(Features, AVX, true); 3556 LLVM_FALLTHROUGH; 3557 case SSE4A: 3558 Features["sse4a"] = true; 3559 setSSELevel(Features, SSE3, true); 3560 LLVM_FALLTHROUGH; 3561 case NoXOP: 3562 break; 3563 } 3564 return; 3565 } 3566 3567 switch (Level) { 3568 case NoXOP: 3569 case SSE4A: 3570 Features["sse4a"] = false; 3571 LLVM_FALLTHROUGH; 3572 case FMA4: 3573 Features["fma4"] = false; 3574 LLVM_FALLTHROUGH; 3575 case XOP: 3576 Features["xop"] = false; 3577 } 3578 } 3579 3580 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 3581 StringRef Name, bool Enabled) { 3582 // This is a bit of a hack to deal with the sse4 target feature when used 3583 // as part of the target attribute. We handle sse4 correctly everywhere 3584 // else. See below for more information on how we handle the sse4 options. 3585 if (Name != "sse4") 3586 Features[Name] = Enabled; 3587 3588 if (Name == "mmx") { 3589 setMMXLevel(Features, MMX, Enabled); 3590 } else if (Name == "sse") { 3591 setSSELevel(Features, SSE1, Enabled); 3592 } else if (Name == "sse2") { 3593 setSSELevel(Features, SSE2, Enabled); 3594 } else if (Name == "sse3") { 3595 setSSELevel(Features, SSE3, Enabled); 3596 } else if (Name == "ssse3") { 3597 setSSELevel(Features, SSSE3, Enabled); 3598 } else if (Name == "sse4.2") { 3599 setSSELevel(Features, SSE42, Enabled); 3600 } else if (Name == "sse4.1") { 3601 setSSELevel(Features, SSE41, Enabled); 3602 } else if (Name == "3dnow") { 3603 setMMXLevel(Features, AMD3DNow, Enabled); 3604 } else if (Name == "3dnowa") { 3605 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 3606 } else if (Name == "aes") { 3607 if (Enabled) 3608 setSSELevel(Features, SSE2, Enabled); 3609 } else if (Name == "pclmul") { 3610 if (Enabled) 3611 setSSELevel(Features, SSE2, Enabled); 3612 } else if (Name == "avx") { 3613 setSSELevel(Features, AVX, Enabled); 3614 } else if (Name == "avx2") { 3615 setSSELevel(Features, AVX2, Enabled); 3616 } else if (Name == "avx512f") { 3617 setSSELevel(Features, AVX512F, Enabled); 3618 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" || 3619 Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl" || 3620 Name == "avx512vbmi" || Name == "avx512ifma" || 3621 Name == "avx512vpopcntdq") { 3622 if (Enabled) 3623 setSSELevel(Features, AVX512F, Enabled); 3624 // Enable BWI instruction if VBMI is being enabled. 3625 if (Name == "avx512vbmi" && Enabled) 3626 Features["avx512bw"] = true; 3627 // Also disable VBMI if BWI is being disabled. 3628 if (Name == "avx512bw" && !Enabled) 3629 Features["avx512vbmi"] = false; 3630 } else if (Name == "fma") { 3631 if (Enabled) 3632 setSSELevel(Features, AVX, Enabled); 3633 } else if (Name == "fma4") { 3634 setXOPLevel(Features, FMA4, Enabled); 3635 } else if (Name == "xop") { 3636 setXOPLevel(Features, XOP, Enabled); 3637 } else if (Name == "sse4a") { 3638 setXOPLevel(Features, SSE4A, Enabled); 3639 } else if (Name == "f16c") { 3640 if (Enabled) 3641 setSSELevel(Features, AVX, Enabled); 3642 } else if (Name == "sha") { 3643 if (Enabled) 3644 setSSELevel(Features, SSE2, Enabled); 3645 } else if (Name == "sse4") { 3646 // We can get here via the __target__ attribute since that's not controlled 3647 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3648 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3649 // disabled. 3650 if (Enabled) 3651 setSSELevel(Features, SSE42, Enabled); 3652 else 3653 setSSELevel(Features, SSE41, Enabled); 3654 } else if (Name == "xsave") { 3655 if (!Enabled) 3656 Features["xsaveopt"] = false; 3657 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3658 if (Enabled) 3659 Features["xsave"] = true; 3660 } 3661 } 3662 3663 /// handleTargetFeatures - Perform initialization based on the user 3664 /// configured set of features. 3665 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3666 DiagnosticsEngine &Diags) { 3667 for (const auto &Feature : Features) { 3668 if (Feature[0] != '+') 3669 continue; 3670 3671 if (Feature == "+aes") { 3672 HasAES = true; 3673 } else if (Feature == "+pclmul") { 3674 HasPCLMUL = true; 3675 } else if (Feature == "+lzcnt") { 3676 HasLZCNT = true; 3677 } else if (Feature == "+rdrnd") { 3678 HasRDRND = true; 3679 } else if (Feature == "+fsgsbase") { 3680 HasFSGSBASE = true; 3681 } else if (Feature == "+bmi") { 3682 HasBMI = true; 3683 } else if (Feature == "+bmi2") { 3684 HasBMI2 = true; 3685 } else if (Feature == "+popcnt") { 3686 HasPOPCNT = true; 3687 } else if (Feature == "+rtm") { 3688 HasRTM = true; 3689 } else if (Feature == "+prfchw") { 3690 HasPRFCHW = true; 3691 } else if (Feature == "+rdseed") { 3692 HasRDSEED = true; 3693 } else if (Feature == "+adx") { 3694 HasADX = true; 3695 } else if (Feature == "+tbm") { 3696 HasTBM = true; 3697 } else if (Feature == "+lwp") { 3698 HasLWP = true; 3699 } else if (Feature == "+fma") { 3700 HasFMA = true; 3701 } else if (Feature == "+f16c") { 3702 HasF16C = true; 3703 } else if (Feature == "+avx512cd") { 3704 HasAVX512CD = true; 3705 } else if (Feature == "+avx512vpopcntdq") { 3706 HasAVX512VPOPCNTDQ = true; 3707 } else if (Feature == "+avx512er") { 3708 HasAVX512ER = true; 3709 } else if (Feature == "+avx512pf") { 3710 HasAVX512PF = true; 3711 } else if (Feature == "+avx512dq") { 3712 HasAVX512DQ = true; 3713 } else if (Feature == "+avx512bw") { 3714 HasAVX512BW = true; 3715 } else if (Feature == "+avx512vl") { 3716 HasAVX512VL = true; 3717 } else if (Feature == "+avx512vbmi") { 3718 HasAVX512VBMI = true; 3719 } else if (Feature == "+avx512ifma") { 3720 HasAVX512IFMA = true; 3721 } else if (Feature == "+sha") { 3722 HasSHA = true; 3723 } else if (Feature == "+mpx") { 3724 HasMPX = true; 3725 } else if (Feature == "+movbe") { 3726 HasMOVBE = true; 3727 } else if (Feature == "+sgx") { 3728 HasSGX = true; 3729 } else if (Feature == "+cx16") { 3730 HasCX16 = true; 3731 } else if (Feature == "+fxsr") { 3732 HasFXSR = true; 3733 } else if (Feature == "+xsave") { 3734 HasXSAVE = true; 3735 } else if (Feature == "+xsaveopt") { 3736 HasXSAVEOPT = true; 3737 } else if (Feature == "+xsavec") { 3738 HasXSAVEC = true; 3739 } else if (Feature == "+xsaves") { 3740 HasXSAVES = true; 3741 } else if (Feature == "+mwaitx") { 3742 HasMWAITX = true; 3743 } else if (Feature == "+pku") { 3744 HasPKU = true; 3745 } else if (Feature == "+clflushopt") { 3746 HasCLFLUSHOPT = true; 3747 } else if (Feature == "+clwb") { 3748 HasCLWB = true; 3749 } else if (Feature == "+prefetchwt1") { 3750 HasPREFETCHWT1 = true; 3751 } else if (Feature == "+clzero") { 3752 HasCLZERO = true; 3753 } 3754 3755 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3756 .Case("+avx512f", AVX512F) 3757 .Case("+avx2", AVX2) 3758 .Case("+avx", AVX) 3759 .Case("+sse4.2", SSE42) 3760 .Case("+sse4.1", SSE41) 3761 .Case("+ssse3", SSSE3) 3762 .Case("+sse3", SSE3) 3763 .Case("+sse2", SSE2) 3764 .Case("+sse", SSE1) 3765 .Default(NoSSE); 3766 SSELevel = std::max(SSELevel, Level); 3767 3768 MMX3DNowEnum ThreeDNowLevel = 3769 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3770 .Case("+3dnowa", AMD3DNowAthlon) 3771 .Case("+3dnow", AMD3DNow) 3772 .Case("+mmx", MMX) 3773 .Default(NoMMX3DNow); 3774 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3775 3776 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3777 .Case("+xop", XOP) 3778 .Case("+fma4", FMA4) 3779 .Case("+sse4a", SSE4A) 3780 .Default(NoXOP); 3781 XOPLevel = std::max(XOPLevel, XLevel); 3782 } 3783 3784 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3785 // matches the selected sse level. 3786 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3787 (FPMath == FP_387 && SSELevel >= SSE1)) { 3788 Diags.Report(diag::err_target_unsupported_fpmath) << 3789 (FPMath == FP_SSE ? "sse" : "387"); 3790 return false; 3791 } 3792 3793 SimdDefaultAlign = 3794 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3795 return true; 3796 } 3797 3798 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3799 /// definitions for this particular subtarget. 3800 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3801 MacroBuilder &Builder) const { 3802 // Target identification. 3803 if (getTriple().getArch() == llvm::Triple::x86_64) { 3804 Builder.defineMacro("__amd64__"); 3805 Builder.defineMacro("__amd64"); 3806 Builder.defineMacro("__x86_64"); 3807 Builder.defineMacro("__x86_64__"); 3808 if (getTriple().getArchName() == "x86_64h") { 3809 Builder.defineMacro("__x86_64h"); 3810 Builder.defineMacro("__x86_64h__"); 3811 } 3812 } else { 3813 DefineStd(Builder, "i386", Opts); 3814 } 3815 3816 // Subtarget options. 3817 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3818 // truly should be based on -mtune options. 3819 switch (CPU) { 3820 case CK_Generic: 3821 break; 3822 case CK_i386: 3823 // The rest are coming from the i386 define above. 3824 Builder.defineMacro("__tune_i386__"); 3825 break; 3826 case CK_i486: 3827 case CK_WinChipC6: 3828 case CK_WinChip2: 3829 case CK_C3: 3830 defineCPUMacros(Builder, "i486"); 3831 break; 3832 case CK_PentiumMMX: 3833 Builder.defineMacro("__pentium_mmx__"); 3834 Builder.defineMacro("__tune_pentium_mmx__"); 3835 // Fallthrough 3836 case CK_i586: 3837 case CK_Pentium: 3838 defineCPUMacros(Builder, "i586"); 3839 defineCPUMacros(Builder, "pentium"); 3840 break; 3841 case CK_Pentium3: 3842 case CK_Pentium3M: 3843 case CK_PentiumM: 3844 Builder.defineMacro("__tune_pentium3__"); 3845 // Fallthrough 3846 case CK_Pentium2: 3847 case CK_C3_2: 3848 Builder.defineMacro("__tune_pentium2__"); 3849 // Fallthrough 3850 case CK_PentiumPro: 3851 Builder.defineMacro("__tune_i686__"); 3852 Builder.defineMacro("__tune_pentiumpro__"); 3853 // Fallthrough 3854 case CK_i686: 3855 Builder.defineMacro("__i686"); 3856 Builder.defineMacro("__i686__"); 3857 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3858 Builder.defineMacro("__pentiumpro"); 3859 Builder.defineMacro("__pentiumpro__"); 3860 break; 3861 case CK_Pentium4: 3862 case CK_Pentium4M: 3863 defineCPUMacros(Builder, "pentium4"); 3864 break; 3865 case CK_Yonah: 3866 case CK_Prescott: 3867 case CK_Nocona: 3868 defineCPUMacros(Builder, "nocona"); 3869 break; 3870 case CK_Core2: 3871 case CK_Penryn: 3872 defineCPUMacros(Builder, "core2"); 3873 break; 3874 case CK_Bonnell: 3875 defineCPUMacros(Builder, "atom"); 3876 break; 3877 case CK_Silvermont: 3878 defineCPUMacros(Builder, "slm"); 3879 break; 3880 case CK_Nehalem: 3881 case CK_Westmere: 3882 case CK_SandyBridge: 3883 case CK_IvyBridge: 3884 case CK_Haswell: 3885 case CK_Broadwell: 3886 case CK_SkylakeClient: 3887 // FIXME: Historically, we defined this legacy name, it would be nice to 3888 // remove it at some point. We've never exposed fine-grained names for 3889 // recent primary x86 CPUs, and we should keep it that way. 3890 defineCPUMacros(Builder, "corei7"); 3891 break; 3892 case CK_SkylakeServer: 3893 defineCPUMacros(Builder, "skx"); 3894 break; 3895 case CK_Cannonlake: 3896 break; 3897 case CK_KNL: 3898 defineCPUMacros(Builder, "knl"); 3899 break; 3900 case CK_Lakemont: 3901 Builder.defineMacro("__tune_lakemont__"); 3902 break; 3903 case CK_K6_2: 3904 Builder.defineMacro("__k6_2__"); 3905 Builder.defineMacro("__tune_k6_2__"); 3906 // Fallthrough 3907 case CK_K6_3: 3908 if (CPU != CK_K6_2) { // In case of fallthrough 3909 // FIXME: GCC may be enabling these in cases where some other k6 3910 // architecture is specified but -m3dnow is explicitly provided. The 3911 // exact semantics need to be determined and emulated here. 3912 Builder.defineMacro("__k6_3__"); 3913 Builder.defineMacro("__tune_k6_3__"); 3914 } 3915 // Fallthrough 3916 case CK_K6: 3917 defineCPUMacros(Builder, "k6"); 3918 break; 3919 case CK_Athlon: 3920 case CK_AthlonThunderbird: 3921 case CK_Athlon4: 3922 case CK_AthlonXP: 3923 case CK_AthlonMP: 3924 defineCPUMacros(Builder, "athlon"); 3925 if (SSELevel != NoSSE) { 3926 Builder.defineMacro("__athlon_sse__"); 3927 Builder.defineMacro("__tune_athlon_sse__"); 3928 } 3929 break; 3930 case CK_K8: 3931 case CK_K8SSE3: 3932 case CK_x86_64: 3933 case CK_Opteron: 3934 case CK_OpteronSSE3: 3935 case CK_Athlon64: 3936 case CK_Athlon64SSE3: 3937 case CK_AthlonFX: 3938 defineCPUMacros(Builder, "k8"); 3939 break; 3940 case CK_AMDFAM10: 3941 defineCPUMacros(Builder, "amdfam10"); 3942 break; 3943 case CK_BTVER1: 3944 defineCPUMacros(Builder, "btver1"); 3945 break; 3946 case CK_BTVER2: 3947 defineCPUMacros(Builder, "btver2"); 3948 break; 3949 case CK_BDVER1: 3950 defineCPUMacros(Builder, "bdver1"); 3951 break; 3952 case CK_BDVER2: 3953 defineCPUMacros(Builder, "bdver2"); 3954 break; 3955 case CK_BDVER3: 3956 defineCPUMacros(Builder, "bdver3"); 3957 break; 3958 case CK_BDVER4: 3959 defineCPUMacros(Builder, "bdver4"); 3960 break; 3961 case CK_ZNVER1: 3962 defineCPUMacros(Builder, "znver1"); 3963 break; 3964 case CK_Geode: 3965 defineCPUMacros(Builder, "geode"); 3966 break; 3967 } 3968 3969 // Target properties. 3970 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3971 3972 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3973 // functions in glibc header files that use FP Stack inline asm which the 3974 // backend can't deal with (PR879). 3975 Builder.defineMacro("__NO_MATH_INLINES"); 3976 3977 if (HasAES) 3978 Builder.defineMacro("__AES__"); 3979 3980 if (HasPCLMUL) 3981 Builder.defineMacro("__PCLMUL__"); 3982 3983 if (HasLZCNT) 3984 Builder.defineMacro("__LZCNT__"); 3985 3986 if (HasRDRND) 3987 Builder.defineMacro("__RDRND__"); 3988 3989 if (HasFSGSBASE) 3990 Builder.defineMacro("__FSGSBASE__"); 3991 3992 if (HasBMI) 3993 Builder.defineMacro("__BMI__"); 3994 3995 if (HasBMI2) 3996 Builder.defineMacro("__BMI2__"); 3997 3998 if (HasPOPCNT) 3999 Builder.defineMacro("__POPCNT__"); 4000 4001 if (HasRTM) 4002 Builder.defineMacro("__RTM__"); 4003 4004 if (HasPRFCHW) 4005 Builder.defineMacro("__PRFCHW__"); 4006 4007 if (HasRDSEED) 4008 Builder.defineMacro("__RDSEED__"); 4009 4010 if (HasADX) 4011 Builder.defineMacro("__ADX__"); 4012 4013 if (HasTBM) 4014 Builder.defineMacro("__TBM__"); 4015 4016 if (HasLWP) 4017 Builder.defineMacro("__LWP__"); 4018 4019 if (HasMWAITX) 4020 Builder.defineMacro("__MWAITX__"); 4021 4022 switch (XOPLevel) { 4023 case XOP: 4024 Builder.defineMacro("__XOP__"); 4025 LLVM_FALLTHROUGH; 4026 case FMA4: 4027 Builder.defineMacro("__FMA4__"); 4028 LLVM_FALLTHROUGH; 4029 case SSE4A: 4030 Builder.defineMacro("__SSE4A__"); 4031 LLVM_FALLTHROUGH; 4032 case NoXOP: 4033 break; 4034 } 4035 4036 if (HasFMA) 4037 Builder.defineMacro("__FMA__"); 4038 4039 if (HasF16C) 4040 Builder.defineMacro("__F16C__"); 4041 4042 if (HasAVX512CD) 4043 Builder.defineMacro("__AVX512CD__"); 4044 if (HasAVX512VPOPCNTDQ) 4045 Builder.defineMacro("__AVX512VPOPCNTDQ__"); 4046 if (HasAVX512ER) 4047 Builder.defineMacro("__AVX512ER__"); 4048 if (HasAVX512PF) 4049 Builder.defineMacro("__AVX512PF__"); 4050 if (HasAVX512DQ) 4051 Builder.defineMacro("__AVX512DQ__"); 4052 if (HasAVX512BW) 4053 Builder.defineMacro("__AVX512BW__"); 4054 if (HasAVX512VL) 4055 Builder.defineMacro("__AVX512VL__"); 4056 if (HasAVX512VBMI) 4057 Builder.defineMacro("__AVX512VBMI__"); 4058 if (HasAVX512IFMA) 4059 Builder.defineMacro("__AVX512IFMA__"); 4060 4061 if (HasSHA) 4062 Builder.defineMacro("__SHA__"); 4063 4064 if (HasFXSR) 4065 Builder.defineMacro("__FXSR__"); 4066 if (HasXSAVE) 4067 Builder.defineMacro("__XSAVE__"); 4068 if (HasXSAVEOPT) 4069 Builder.defineMacro("__XSAVEOPT__"); 4070 if (HasXSAVEC) 4071 Builder.defineMacro("__XSAVEC__"); 4072 if (HasXSAVES) 4073 Builder.defineMacro("__XSAVES__"); 4074 if (HasPKU) 4075 Builder.defineMacro("__PKU__"); 4076 if (HasCX16) 4077 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 4078 if (HasCLFLUSHOPT) 4079 Builder.defineMacro("__CLFLUSHOPT__"); 4080 if (HasCLWB) 4081 Builder.defineMacro("__CLWB__"); 4082 if (HasMPX) 4083 Builder.defineMacro("__MPX__"); 4084 if (HasSGX) 4085 Builder.defineMacro("__SGX__"); 4086 if (HasPREFETCHWT1) 4087 Builder.defineMacro("__PREFETCHWT1__"); 4088 if (HasCLZERO) 4089 Builder.defineMacro("__CLZERO__"); 4090 4091 // Each case falls through to the previous one here. 4092 switch (SSELevel) { 4093 case AVX512F: 4094 Builder.defineMacro("__AVX512F__"); 4095 LLVM_FALLTHROUGH; 4096 case AVX2: 4097 Builder.defineMacro("__AVX2__"); 4098 LLVM_FALLTHROUGH; 4099 case AVX: 4100 Builder.defineMacro("__AVX__"); 4101 LLVM_FALLTHROUGH; 4102 case SSE42: 4103 Builder.defineMacro("__SSE4_2__"); 4104 LLVM_FALLTHROUGH; 4105 case SSE41: 4106 Builder.defineMacro("__SSE4_1__"); 4107 LLVM_FALLTHROUGH; 4108 case SSSE3: 4109 Builder.defineMacro("__SSSE3__"); 4110 LLVM_FALLTHROUGH; 4111 case SSE3: 4112 Builder.defineMacro("__SSE3__"); 4113 LLVM_FALLTHROUGH; 4114 case SSE2: 4115 Builder.defineMacro("__SSE2__"); 4116 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 4117 LLVM_FALLTHROUGH; 4118 case SSE1: 4119 Builder.defineMacro("__SSE__"); 4120 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 4121 LLVM_FALLTHROUGH; 4122 case NoSSE: 4123 break; 4124 } 4125 4126 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 4127 switch (SSELevel) { 4128 case AVX512F: 4129 case AVX2: 4130 case AVX: 4131 case SSE42: 4132 case SSE41: 4133 case SSSE3: 4134 case SSE3: 4135 case SSE2: 4136 Builder.defineMacro("_M_IX86_FP", Twine(2)); 4137 break; 4138 case SSE1: 4139 Builder.defineMacro("_M_IX86_FP", Twine(1)); 4140 break; 4141 default: 4142 Builder.defineMacro("_M_IX86_FP", Twine(0)); 4143 } 4144 } 4145 4146 // Each case falls through to the previous one here. 4147 switch (MMX3DNowLevel) { 4148 case AMD3DNowAthlon: 4149 Builder.defineMacro("__3dNOW_A__"); 4150 LLVM_FALLTHROUGH; 4151 case AMD3DNow: 4152 Builder.defineMacro("__3dNOW__"); 4153 LLVM_FALLTHROUGH; 4154 case MMX: 4155 Builder.defineMacro("__MMX__"); 4156 LLVM_FALLTHROUGH; 4157 case NoMMX3DNow: 4158 break; 4159 } 4160 4161 if (CPU >= CK_i486) { 4162 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4163 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4164 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4165 } 4166 if (CPU >= CK_i586) 4167 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4168 } 4169 4170 bool X86TargetInfo::hasFeature(StringRef Feature) const { 4171 return llvm::StringSwitch<bool>(Feature) 4172 .Case("aes", HasAES) 4173 .Case("avx", SSELevel >= AVX) 4174 .Case("avx2", SSELevel >= AVX2) 4175 .Case("avx512f", SSELevel >= AVX512F) 4176 .Case("avx512cd", HasAVX512CD) 4177 .Case("avx512vpopcntdq", HasAVX512VPOPCNTDQ) 4178 .Case("avx512er", HasAVX512ER) 4179 .Case("avx512pf", HasAVX512PF) 4180 .Case("avx512dq", HasAVX512DQ) 4181 .Case("avx512bw", HasAVX512BW) 4182 .Case("avx512vl", HasAVX512VL) 4183 .Case("avx512vbmi", HasAVX512VBMI) 4184 .Case("avx512ifma", HasAVX512IFMA) 4185 .Case("bmi", HasBMI) 4186 .Case("bmi2", HasBMI2) 4187 .Case("clflushopt", HasCLFLUSHOPT) 4188 .Case("clwb", HasCLWB) 4189 .Case("clzero", HasCLZERO) 4190 .Case("cx16", HasCX16) 4191 .Case("f16c", HasF16C) 4192 .Case("fma", HasFMA) 4193 .Case("fma4", XOPLevel >= FMA4) 4194 .Case("fsgsbase", HasFSGSBASE) 4195 .Case("fxsr", HasFXSR) 4196 .Case("lzcnt", HasLZCNT) 4197 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 4198 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 4199 .Case("mmx", MMX3DNowLevel >= MMX) 4200 .Case("movbe", HasMOVBE) 4201 .Case("mpx", HasMPX) 4202 .Case("pclmul", HasPCLMUL) 4203 .Case("pku", HasPKU) 4204 .Case("popcnt", HasPOPCNT) 4205 .Case("prefetchwt1", HasPREFETCHWT1) 4206 .Case("prfchw", HasPRFCHW) 4207 .Case("rdrnd", HasRDRND) 4208 .Case("rdseed", HasRDSEED) 4209 .Case("rtm", HasRTM) 4210 .Case("sgx", HasSGX) 4211 .Case("sha", HasSHA) 4212 .Case("sse", SSELevel >= SSE1) 4213 .Case("sse2", SSELevel >= SSE2) 4214 .Case("sse3", SSELevel >= SSE3) 4215 .Case("ssse3", SSELevel >= SSSE3) 4216 .Case("sse4.1", SSELevel >= SSE41) 4217 .Case("sse4.2", SSELevel >= SSE42) 4218 .Case("sse4a", XOPLevel >= SSE4A) 4219 .Case("tbm", HasTBM) 4220 .Case("lwp", HasLWP) 4221 .Case("x86", true) 4222 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 4223 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 4224 .Case("xop", XOPLevel >= XOP) 4225 .Case("xsave", HasXSAVE) 4226 .Case("xsavec", HasXSAVEC) 4227 .Case("xsaves", HasXSAVES) 4228 .Case("xsaveopt", HasXSAVEOPT) 4229 .Default(false); 4230 } 4231 4232 // We can't use a generic validation scheme for the features accepted here 4233 // versus subtarget features accepted in the target attribute because the 4234 // bitfield structure that's initialized in the runtime only supports the 4235 // below currently rather than the full range of subtarget features. (See 4236 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 4237 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 4238 return llvm::StringSwitch<bool>(FeatureStr) 4239 .Case("cmov", true) 4240 .Case("mmx", true) 4241 .Case("popcnt", true) 4242 .Case("sse", true) 4243 .Case("sse2", true) 4244 .Case("sse3", true) 4245 .Case("ssse3", true) 4246 .Case("sse4.1", true) 4247 .Case("sse4.2", true) 4248 .Case("avx", true) 4249 .Case("avx2", true) 4250 .Case("sse4a", true) 4251 .Case("fma4", true) 4252 .Case("xop", true) 4253 .Case("fma", true) 4254 .Case("avx512f", true) 4255 .Case("bmi", true) 4256 .Case("bmi2", true) 4257 .Case("aes", true) 4258 .Case("pclmul", true) 4259 .Case("avx512vl", true) 4260 .Case("avx512bw", true) 4261 .Case("avx512dq", true) 4262 .Case("avx512cd", true) 4263 .Case("avx512vpopcntdq", true) 4264 .Case("avx512er", true) 4265 .Case("avx512pf", true) 4266 .Case("avx512vbmi", true) 4267 .Case("avx512ifma", true) 4268 .Default(false); 4269 } 4270 4271 bool 4272 X86TargetInfo::validateAsmConstraint(const char *&Name, 4273 TargetInfo::ConstraintInfo &Info) const { 4274 switch (*Name) { 4275 default: return false; 4276 // Constant constraints. 4277 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 4278 // instructions. 4279 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 4280 // x86_64 instructions. 4281 case 's': 4282 Info.setRequiresImmediate(); 4283 return true; 4284 case 'I': 4285 Info.setRequiresImmediate(0, 31); 4286 return true; 4287 case 'J': 4288 Info.setRequiresImmediate(0, 63); 4289 return true; 4290 case 'K': 4291 Info.setRequiresImmediate(-128, 127); 4292 return true; 4293 case 'L': 4294 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 4295 return true; 4296 case 'M': 4297 Info.setRequiresImmediate(0, 3); 4298 return true; 4299 case 'N': 4300 Info.setRequiresImmediate(0, 255); 4301 return true; 4302 case 'O': 4303 Info.setRequiresImmediate(0, 127); 4304 return true; 4305 // Register constraints. 4306 case 'Y': // 'Y' is the first character for several 2-character constraints. 4307 // Shift the pointer to the second character of the constraint. 4308 Name++; 4309 switch (*Name) { 4310 default: 4311 return false; 4312 case '0': // First SSE register. 4313 case 't': // Any SSE register, when SSE2 is enabled. 4314 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 4315 case 'm': // Any MMX register, when inter-unit moves enabled. 4316 case 'k': // AVX512 arch mask registers: k1-k7. 4317 Info.setAllowsRegister(); 4318 return true; 4319 } 4320 case 'f': // Any x87 floating point stack register. 4321 // Constraint 'f' cannot be used for output operands. 4322 if (Info.ConstraintStr[0] == '=') 4323 return false; 4324 Info.setAllowsRegister(); 4325 return true; 4326 case 'a': // eax. 4327 case 'b': // ebx. 4328 case 'c': // ecx. 4329 case 'd': // edx. 4330 case 'S': // esi. 4331 case 'D': // edi. 4332 case 'A': // edx:eax. 4333 case 't': // Top of floating point stack. 4334 case 'u': // Second from top of floating point stack. 4335 case 'q': // Any register accessible as [r]l: a, b, c, and d. 4336 case 'y': // Any MMX register. 4337 case 'v': // Any {X,Y,Z}MM register (Arch & context dependent) 4338 case 'x': // Any SSE register. 4339 case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0 4340 // for intermideate k reg operations). 4341 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 4342 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 4343 case 'l': // "Index" registers: any general register that can be used as an 4344 // index in a base+index memory access. 4345 Info.setAllowsRegister(); 4346 return true; 4347 // Floating point constant constraints. 4348 case 'C': // SSE floating point constant. 4349 case 'G': // x87 floating point constant. 4350 return true; 4351 } 4352 } 4353 4354 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 4355 unsigned Size) const { 4356 // Strip off constraint modifiers. 4357 while (Constraint[0] == '=' || 4358 Constraint[0] == '+' || 4359 Constraint[0] == '&') 4360 Constraint = Constraint.substr(1); 4361 4362 return validateOperandSize(Constraint, Size); 4363 } 4364 4365 bool X86TargetInfo::validateInputSize(StringRef Constraint, 4366 unsigned Size) const { 4367 return validateOperandSize(Constraint, Size); 4368 } 4369 4370 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 4371 unsigned Size) const { 4372 switch (Constraint[0]) { 4373 default: break; 4374 case 'k': 4375 // Registers k0-k7 (AVX512) size limit is 64 bit. 4376 case 'y': 4377 return Size <= 64; 4378 case 'f': 4379 case 't': 4380 case 'u': 4381 return Size <= 128; 4382 case 'v': 4383 case 'x': 4384 if (SSELevel >= AVX512F) 4385 // 512-bit zmm registers can be used if target supports AVX512F. 4386 return Size <= 512U; 4387 else if (SSELevel >= AVX) 4388 // 256-bit ymm registers can be used if target supports AVX. 4389 return Size <= 256U; 4390 return Size <= 128U; 4391 case 'Y': 4392 // 'Y' is the first character for several 2-character constraints. 4393 switch (Constraint[1]) { 4394 default: break; 4395 case 'm': 4396 // 'Ym' is synonymous with 'y'. 4397 case 'k': 4398 return Size <= 64; 4399 case 'i': 4400 case 't': 4401 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 4402 if (SSELevel >= AVX512F) 4403 return Size <= 512U; 4404 else if (SSELevel >= AVX) 4405 return Size <= 256U; 4406 return SSELevel >= SSE2 && Size <= 128U; 4407 } 4408 4409 } 4410 4411 return true; 4412 } 4413 4414 std::string 4415 X86TargetInfo::convertConstraint(const char *&Constraint) const { 4416 switch (*Constraint) { 4417 case 'a': return std::string("{ax}"); 4418 case 'b': return std::string("{bx}"); 4419 case 'c': return std::string("{cx}"); 4420 case 'd': return std::string("{dx}"); 4421 case 'S': return std::string("{si}"); 4422 case 'D': return std::string("{di}"); 4423 case 'p': // address 4424 return std::string("im"); 4425 case 't': // top of floating point stack. 4426 return std::string("{st}"); 4427 case 'u': // second from top of floating point stack. 4428 return std::string("{st(1)}"); // second from top of floating point stack. 4429 case 'Y': 4430 switch (Constraint[1]) { 4431 default: 4432 // Break from inner switch and fall through (copy single char), 4433 // continue parsing after copying the current constraint into 4434 // the return string. 4435 break; 4436 case 'k': 4437 // "^" hints llvm that this is a 2 letter constraint. 4438 // "Constraint++" is used to promote the string iterator 4439 // to the next constraint. 4440 return std::string("^") + std::string(Constraint++, 2); 4441 } 4442 LLVM_FALLTHROUGH; 4443 default: 4444 return std::string(1, *Constraint); 4445 } 4446 } 4447 4448 // X86-32 generic target 4449 class X86_32TargetInfo : public X86TargetInfo { 4450 public: 4451 X86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4452 : X86TargetInfo(Triple, Opts) { 4453 DoubleAlign = LongLongAlign = 32; 4454 LongDoubleWidth = 96; 4455 LongDoubleAlign = 32; 4456 SuitableAlign = 128; 4457 resetDataLayout("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"); 4458 SizeType = UnsignedInt; 4459 PtrDiffType = SignedInt; 4460 IntPtrType = SignedInt; 4461 RegParmMax = 3; 4462 4463 // Use fpret for all types. 4464 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 4465 (1 << TargetInfo::Double) | 4466 (1 << TargetInfo::LongDouble)); 4467 4468 // x86-32 has atomics up to 8 bytes 4469 // FIXME: Check that we actually have cmpxchg8b before setting 4470 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 4471 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4472 } 4473 BuiltinVaListKind getBuiltinVaListKind() const override { 4474 return TargetInfo::CharPtrBuiltinVaList; 4475 } 4476 4477 int getEHDataRegisterNumber(unsigned RegNo) const override { 4478 if (RegNo == 0) return 0; 4479 if (RegNo == 1) return 2; 4480 return -1; 4481 } 4482 bool validateOperandSize(StringRef Constraint, 4483 unsigned Size) const override { 4484 switch (Constraint[0]) { 4485 default: break; 4486 case 'R': 4487 case 'q': 4488 case 'Q': 4489 case 'a': 4490 case 'b': 4491 case 'c': 4492 case 'd': 4493 case 'S': 4494 case 'D': 4495 return Size <= 32; 4496 case 'A': 4497 return Size <= 64; 4498 } 4499 4500 return X86TargetInfo::validateOperandSize(Constraint, Size); 4501 } 4502 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4503 return llvm::makeArrayRef(BuiltinInfoX86, clang::X86::LastX86CommonBuiltin - 4504 Builtin::FirstTSBuiltin + 1); 4505 } 4506 }; 4507 4508 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 4509 public: 4510 NetBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4511 : NetBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) {} 4512 4513 unsigned getFloatEvalMethod() const override { 4514 unsigned Major, Minor, Micro; 4515 getTriple().getOSVersion(Major, Minor, Micro); 4516 // New NetBSD uses the default rounding mode. 4517 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 4518 return X86_32TargetInfo::getFloatEvalMethod(); 4519 // NetBSD before 6.99.26 defaults to "double" rounding. 4520 return 1; 4521 } 4522 }; 4523 4524 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 4525 public: 4526 OpenBSDI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4527 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4528 SizeType = UnsignedLong; 4529 IntPtrType = SignedLong; 4530 PtrDiffType = SignedLong; 4531 } 4532 }; 4533 4534 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 4535 public: 4536 BitrigI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4537 : BitrigTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4538 SizeType = UnsignedLong; 4539 IntPtrType = SignedLong; 4540 PtrDiffType = SignedLong; 4541 } 4542 }; 4543 4544 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 4545 public: 4546 DarwinI386TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4547 : DarwinTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4548 LongDoubleWidth = 128; 4549 LongDoubleAlign = 128; 4550 SuitableAlign = 128; 4551 MaxVectorAlign = 256; 4552 // The watchOS simulator uses the builtin bool type for Objective-C. 4553 llvm::Triple T = llvm::Triple(Triple); 4554 if (T.isWatchOS()) 4555 UseSignedCharForObjCBool = false; 4556 SizeType = UnsignedLong; 4557 IntPtrType = SignedLong; 4558 resetDataLayout("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"); 4559 HasAlignMac68kSupport = true; 4560 } 4561 4562 bool handleTargetFeatures(std::vector<std::string> &Features, 4563 DiagnosticsEngine &Diags) override { 4564 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 4565 Diags)) 4566 return false; 4567 // We now know the features we have: we can decide how to align vectors. 4568 MaxVectorAlign = 4569 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4570 return true; 4571 } 4572 }; 4573 4574 // x86-32 Windows target 4575 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 4576 public: 4577 WindowsX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4578 : WindowsTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4579 WCharType = UnsignedShort; 4580 DoubleAlign = LongLongAlign = 64; 4581 bool IsWinCOFF = 4582 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4583 resetDataLayout(IsWinCOFF 4584 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 4585 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4586 } 4587 void getTargetDefines(const LangOptions &Opts, 4588 MacroBuilder &Builder) const override { 4589 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4590 } 4591 }; 4592 4593 // x86-32 Windows Visual Studio target 4594 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 4595 public: 4596 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple, 4597 const TargetOptions &Opts) 4598 : WindowsX86_32TargetInfo(Triple, Opts) { 4599 LongDoubleWidth = LongDoubleAlign = 64; 4600 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4601 } 4602 void getTargetDefines(const LangOptions &Opts, 4603 MacroBuilder &Builder) const override { 4604 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4605 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 4606 // The value of the following reflects processor type. 4607 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 4608 // We lost the original triple, so we use the default. 4609 Builder.defineMacro("_M_IX86", "600"); 4610 } 4611 }; 4612 4613 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4614 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 4615 // supports __declspec natively under -fms-extensions, but we define a no-op 4616 // __declspec macro anyway for pre-processor compatibility. 4617 if (Opts.MicrosoftExt) 4618 Builder.defineMacro("__declspec", "__declspec"); 4619 else 4620 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 4621 4622 if (!Opts.MicrosoftExt) { 4623 // Provide macros for all the calling convention keywords. Provide both 4624 // single and double underscore prefixed variants. These are available on 4625 // x64 as well as x86, even though they have no effect. 4626 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 4627 for (const char *CC : CCs) { 4628 std::string GCCSpelling = "__attribute__((__"; 4629 GCCSpelling += CC; 4630 GCCSpelling += "__))"; 4631 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 4632 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 4633 } 4634 } 4635 } 4636 4637 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 4638 Builder.defineMacro("__MSVCRT__"); 4639 Builder.defineMacro("__MINGW32__"); 4640 addCygMingDefines(Opts, Builder); 4641 } 4642 4643 // x86-32 MinGW target 4644 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 4645 public: 4646 MinGWX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4647 : WindowsX86_32TargetInfo(Triple, Opts) {} 4648 void getTargetDefines(const LangOptions &Opts, 4649 MacroBuilder &Builder) const override { 4650 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 4651 DefineStd(Builder, "WIN32", Opts); 4652 DefineStd(Builder, "WINNT", Opts); 4653 Builder.defineMacro("_X86_"); 4654 addMinGWDefines(Opts, Builder); 4655 } 4656 }; 4657 4658 // x86-32 Cygwin target 4659 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 4660 public: 4661 CygwinX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4662 : X86_32TargetInfo(Triple, Opts) { 4663 WCharType = UnsignedShort; 4664 DoubleAlign = LongLongAlign = 64; 4665 resetDataLayout("e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"); 4666 } 4667 void getTargetDefines(const LangOptions &Opts, 4668 MacroBuilder &Builder) const override { 4669 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4670 Builder.defineMacro("_X86_"); 4671 Builder.defineMacro("__CYGWIN__"); 4672 Builder.defineMacro("__CYGWIN32__"); 4673 addCygMingDefines(Opts, Builder); 4674 DefineStd(Builder, "unix", Opts); 4675 if (Opts.CPlusPlus) 4676 Builder.defineMacro("_GNU_SOURCE"); 4677 } 4678 }; 4679 4680 // x86-32 Haiku target 4681 class HaikuX86_32TargetInfo : public HaikuTargetInfo<X86_32TargetInfo> { 4682 public: 4683 HaikuX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4684 : HaikuTargetInfo<X86_32TargetInfo>(Triple, Opts) { 4685 } 4686 void getTargetDefines(const LangOptions &Opts, 4687 MacroBuilder &Builder) const override { 4688 HaikuTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 4689 Builder.defineMacro("__INTEL__"); 4690 } 4691 }; 4692 4693 // X86-32 MCU target 4694 class MCUX86_32TargetInfo : public X86_32TargetInfo { 4695 public: 4696 MCUX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4697 : X86_32TargetInfo(Triple, Opts) { 4698 LongDoubleWidth = 64; 4699 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4700 resetDataLayout("e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"); 4701 WIntType = UnsignedInt; 4702 } 4703 4704 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4705 // On MCU we support only C calling convention. 4706 return CC == CC_C ? CCCR_OK : CCCR_Warning; 4707 } 4708 4709 void getTargetDefines(const LangOptions &Opts, 4710 MacroBuilder &Builder) const override { 4711 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4712 Builder.defineMacro("__iamcu"); 4713 Builder.defineMacro("__iamcu__"); 4714 } 4715 4716 bool allowsLargerPreferedTypeAlignment() const override { 4717 return false; 4718 } 4719 }; 4720 4721 // RTEMS Target 4722 template<typename Target> 4723 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4724 protected: 4725 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4726 MacroBuilder &Builder) const override { 4727 // RTEMS defines; list based off of gcc output 4728 4729 Builder.defineMacro("__rtems__"); 4730 Builder.defineMacro("__ELF__"); 4731 } 4732 4733 public: 4734 RTEMSTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4735 : OSTargetInfo<Target>(Triple, Opts) { 4736 switch (Triple.getArch()) { 4737 default: 4738 case llvm::Triple::x86: 4739 // this->MCountName = ".mcount"; 4740 break; 4741 case llvm::Triple::mips: 4742 case llvm::Triple::mipsel: 4743 case llvm::Triple::ppc: 4744 case llvm::Triple::ppc64: 4745 case llvm::Triple::ppc64le: 4746 // this->MCountName = "_mcount"; 4747 break; 4748 case llvm::Triple::arm: 4749 // this->MCountName = "__mcount"; 4750 break; 4751 } 4752 } 4753 }; 4754 4755 // x86-32 RTEMS target 4756 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4757 public: 4758 RTEMSX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4759 : X86_32TargetInfo(Triple, Opts) { 4760 SizeType = UnsignedLong; 4761 IntPtrType = SignedLong; 4762 PtrDiffType = SignedLong; 4763 } 4764 void getTargetDefines(const LangOptions &Opts, 4765 MacroBuilder &Builder) const override { 4766 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4767 Builder.defineMacro("__INTEL__"); 4768 Builder.defineMacro("__rtems__"); 4769 } 4770 }; 4771 4772 // x86-64 generic target 4773 class X86_64TargetInfo : public X86TargetInfo { 4774 public: 4775 X86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4776 : X86TargetInfo(Triple, Opts) { 4777 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4778 bool IsWinCOFF = 4779 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4780 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4781 LongDoubleWidth = 128; 4782 LongDoubleAlign = 128; 4783 LargeArrayMinWidth = 128; 4784 LargeArrayAlign = 128; 4785 SuitableAlign = 128; 4786 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4787 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4788 IntPtrType = IsX32 ? SignedInt : SignedLong; 4789 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4790 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4791 RegParmMax = 6; 4792 4793 // Pointers are 32-bit in x32. 4794 resetDataLayout(IsX32 4795 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4796 : IsWinCOFF ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4797 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"); 4798 4799 // Use fpret only for long double. 4800 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4801 4802 // Use fp2ret for _Complex long double. 4803 ComplexLongDoubleUsesFP2Ret = true; 4804 4805 // Make __builtin_ms_va_list available. 4806 HasBuiltinMSVaList = true; 4807 4808 // x86-64 has atomics up to 16 bytes. 4809 MaxAtomicPromoteWidth = 128; 4810 MaxAtomicInlineWidth = 128; 4811 } 4812 BuiltinVaListKind getBuiltinVaListKind() const override { 4813 return TargetInfo::X86_64ABIBuiltinVaList; 4814 } 4815 4816 int getEHDataRegisterNumber(unsigned RegNo) const override { 4817 if (RegNo == 0) return 0; 4818 if (RegNo == 1) return 1; 4819 return -1; 4820 } 4821 4822 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4823 switch (CC) { 4824 case CC_C: 4825 case CC_Swift: 4826 case CC_X86VectorCall: 4827 case CC_IntelOclBicc: 4828 case CC_X86_64Win64: 4829 case CC_PreserveMost: 4830 case CC_PreserveAll: 4831 case CC_X86RegCall: 4832 return CCCR_OK; 4833 default: 4834 return CCCR_Warning; 4835 } 4836 } 4837 4838 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4839 return CC_C; 4840 } 4841 4842 // for x32 we need it here explicitly 4843 bool hasInt128Type() const override { return true; } 4844 unsigned getUnwindWordWidth() const override { return 64; } 4845 unsigned getRegisterWidth() const override { return 64; } 4846 4847 bool validateGlobalRegisterVariable(StringRef RegName, 4848 unsigned RegSize, 4849 bool &HasSizeMismatch) const override { 4850 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4851 // handle. 4852 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4853 // Check that the register size is 64-bit. 4854 HasSizeMismatch = RegSize != 64; 4855 return true; 4856 } 4857 4858 // Check if the register is a 32-bit register the backend can handle. 4859 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4860 HasSizeMismatch); 4861 } 4862 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4863 return llvm::makeArrayRef(BuiltinInfoX86, 4864 X86::LastTSBuiltin - Builtin::FirstTSBuiltin); 4865 } 4866 }; 4867 4868 // x86-64 Windows target 4869 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4870 public: 4871 WindowsX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4872 : WindowsTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4873 WCharType = UnsignedShort; 4874 LongWidth = LongAlign = 32; 4875 DoubleAlign = LongLongAlign = 64; 4876 IntMaxType = SignedLongLong; 4877 Int64Type = SignedLongLong; 4878 SizeType = UnsignedLongLong; 4879 PtrDiffType = SignedLongLong; 4880 IntPtrType = SignedLongLong; 4881 } 4882 4883 void getTargetDefines(const LangOptions &Opts, 4884 MacroBuilder &Builder) const override { 4885 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4886 Builder.defineMacro("_WIN64"); 4887 } 4888 4889 BuiltinVaListKind getBuiltinVaListKind() const override { 4890 return TargetInfo::CharPtrBuiltinVaList; 4891 } 4892 4893 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4894 switch (CC) { 4895 case CC_X86StdCall: 4896 case CC_X86ThisCall: 4897 case CC_X86FastCall: 4898 return CCCR_Ignore; 4899 case CC_C: 4900 case CC_X86VectorCall: 4901 case CC_IntelOclBicc: 4902 case CC_X86_64SysV: 4903 case CC_Swift: 4904 case CC_X86RegCall: 4905 return CCCR_OK; 4906 default: 4907 return CCCR_Warning; 4908 } 4909 } 4910 }; 4911 4912 // x86-64 Windows Visual Studio target 4913 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4914 public: 4915 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple, 4916 const TargetOptions &Opts) 4917 : WindowsX86_64TargetInfo(Triple, Opts) { 4918 LongDoubleWidth = LongDoubleAlign = 64; 4919 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 4920 } 4921 void getTargetDefines(const LangOptions &Opts, 4922 MacroBuilder &Builder) const override { 4923 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4924 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4925 Builder.defineMacro("_M_X64", "100"); 4926 Builder.defineMacro("_M_AMD64", "100"); 4927 } 4928 }; 4929 4930 // x86-64 MinGW target 4931 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4932 public: 4933 MinGWX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4934 : WindowsX86_64TargetInfo(Triple, Opts) { 4935 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4936 // with x86 FP ops. Weird. 4937 LongDoubleWidth = LongDoubleAlign = 128; 4938 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended(); 4939 } 4940 4941 void getTargetDefines(const LangOptions &Opts, 4942 MacroBuilder &Builder) const override { 4943 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4944 DefineStd(Builder, "WIN64", Opts); 4945 Builder.defineMacro("__MINGW64__"); 4946 addMinGWDefines(Opts, Builder); 4947 4948 // GCC defines this macro when it is using __gxx_personality_seh0. 4949 if (!Opts.SjLjExceptions) 4950 Builder.defineMacro("__SEH__"); 4951 } 4952 }; 4953 4954 // x86-64 Cygwin target 4955 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4956 public: 4957 CygwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4958 : X86_64TargetInfo(Triple, Opts) { 4959 TLSSupported = false; 4960 WCharType = UnsignedShort; 4961 } 4962 void getTargetDefines(const LangOptions &Opts, 4963 MacroBuilder &Builder) const override { 4964 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4965 Builder.defineMacro("__x86_64__"); 4966 Builder.defineMacro("__CYGWIN__"); 4967 Builder.defineMacro("__CYGWIN64__"); 4968 addCygMingDefines(Opts, Builder); 4969 DefineStd(Builder, "unix", Opts); 4970 if (Opts.CPlusPlus) 4971 Builder.defineMacro("_GNU_SOURCE"); 4972 4973 // GCC defines this macro when it is using __gxx_personality_seh0. 4974 if (!Opts.SjLjExceptions) 4975 Builder.defineMacro("__SEH__"); 4976 } 4977 }; 4978 4979 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4980 public: 4981 DarwinX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 4982 : DarwinTargetInfo<X86_64TargetInfo>(Triple, Opts) { 4983 Int64Type = SignedLongLong; 4984 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4985 llvm::Triple T = llvm::Triple(Triple); 4986 if (T.isiOS()) 4987 UseSignedCharForObjCBool = false; 4988 resetDataLayout("e-m:o-i64:64-f80:128-n8:16:32:64-S128"); 4989 } 4990 4991 bool handleTargetFeatures(std::vector<std::string> &Features, 4992 DiagnosticsEngine &Diags) override { 4993 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4994 Diags)) 4995 return false; 4996 // We now know the features we have: we can decide how to align vectors. 4997 MaxVectorAlign = 4998 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4999 return true; 5000 } 5001 }; 5002 5003 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 5004 public: 5005 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5006 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5007 IntMaxType = SignedLongLong; 5008 Int64Type = SignedLongLong; 5009 } 5010 }; 5011 5012 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 5013 public: 5014 BitrigX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5015 : BitrigTargetInfo<X86_64TargetInfo>(Triple, Opts) { 5016 IntMaxType = SignedLongLong; 5017 Int64Type = SignedLongLong; 5018 } 5019 }; 5020 5021 class ARMTargetInfo : public TargetInfo { 5022 // Possible FPU choices. 5023 enum FPUMode { 5024 VFP2FPU = (1 << 0), 5025 VFP3FPU = (1 << 1), 5026 VFP4FPU = (1 << 2), 5027 NeonFPU = (1 << 3), 5028 FPARMV8 = (1 << 4) 5029 }; 5030 5031 // Possible HWDiv features. 5032 enum HWDivMode { 5033 HWDivThumb = (1 << 0), 5034 HWDivARM = (1 << 1) 5035 }; 5036 5037 static bool FPUModeIsVFP(FPUMode Mode) { 5038 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 5039 } 5040 5041 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5042 static const char * const GCCRegNames[]; 5043 5044 std::string ABI, CPU; 5045 5046 StringRef CPUProfile; 5047 StringRef CPUAttr; 5048 5049 enum { 5050 FP_Default, 5051 FP_VFP, 5052 FP_Neon 5053 } FPMath; 5054 5055 unsigned ArchISA; 5056 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 5057 unsigned ArchProfile; 5058 unsigned ArchVersion; 5059 5060 unsigned FPU : 5; 5061 5062 unsigned IsAAPCS : 1; 5063 unsigned HWDiv : 2; 5064 5065 // Initialized via features. 5066 unsigned SoftFloat : 1; 5067 unsigned SoftFloatABI : 1; 5068 5069 unsigned CRC : 1; 5070 unsigned Crypto : 1; 5071 unsigned DSP : 1; 5072 unsigned Unaligned : 1; 5073 5074 enum { 5075 LDREX_B = (1 << 0), /// byte (8-bit) 5076 LDREX_H = (1 << 1), /// half (16-bit) 5077 LDREX_W = (1 << 2), /// word (32-bit) 5078 LDREX_D = (1 << 3), /// double (64-bit) 5079 }; 5080 5081 uint32_t LDREX; 5082 5083 // ACLE 6.5.1 Hardware floating point 5084 enum { 5085 HW_FP_HP = (1 << 1), /// half (16-bit) 5086 HW_FP_SP = (1 << 2), /// single (32-bit) 5087 HW_FP_DP = (1 << 3), /// double (64-bit) 5088 }; 5089 uint32_t HW_FP; 5090 5091 static const Builtin::Info BuiltinInfo[]; 5092 5093 void setABIAAPCS() { 5094 IsAAPCS = true; 5095 5096 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5097 const llvm::Triple &T = getTriple(); 5098 5099 // size_t is unsigned long on MachO-derived environments, NetBSD, 5100 // OpenBSD and Bitrig. 5101 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 5102 T.getOS() == llvm::Triple::OpenBSD || 5103 T.getOS() == llvm::Triple::Bitrig) 5104 SizeType = UnsignedLong; 5105 else 5106 SizeType = UnsignedInt; 5107 5108 switch (T.getOS()) { 5109 case llvm::Triple::NetBSD: 5110 case llvm::Triple::OpenBSD: 5111 WCharType = SignedInt; 5112 break; 5113 case llvm::Triple::Win32: 5114 WCharType = UnsignedShort; 5115 break; 5116 case llvm::Triple::Linux: 5117 default: 5118 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 5119 WCharType = UnsignedInt; 5120 break; 5121 } 5122 5123 UseBitFieldTypeAlignment = true; 5124 5125 ZeroLengthBitfieldBoundary = 0; 5126 5127 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 5128 // so set preferred for small types to 32. 5129 if (T.isOSBinFormatMachO()) { 5130 resetDataLayout(BigEndian 5131 ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5132 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5133 } else if (T.isOSWindows()) { 5134 assert(!BigEndian && "Windows on ARM does not support big endian"); 5135 resetDataLayout("e" 5136 "-m:w" 5137 "-p:32:32" 5138 "-i64:64" 5139 "-v128:64:128" 5140 "-a:0:32" 5141 "-n32" 5142 "-S64"); 5143 } else if (T.isOSNaCl()) { 5144 assert(!BigEndian && "NaCl on ARM does not support big endian"); 5145 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"); 5146 } else { 5147 resetDataLayout(BigEndian 5148 ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 5149 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 5150 } 5151 5152 // FIXME: Enumerated types are variable width in straight AAPCS. 5153 } 5154 5155 void setABIAPCS(bool IsAAPCS16) { 5156 const llvm::Triple &T = getTriple(); 5157 5158 IsAAPCS = false; 5159 5160 if (IsAAPCS16) 5161 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 5162 else 5163 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 5164 5165 // size_t is unsigned int on FreeBSD. 5166 if (T.getOS() == llvm::Triple::FreeBSD) 5167 SizeType = UnsignedInt; 5168 else 5169 SizeType = UnsignedLong; 5170 5171 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 5172 WCharType = SignedInt; 5173 5174 // Do not respect the alignment of bit-field types when laying out 5175 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 5176 UseBitFieldTypeAlignment = false; 5177 5178 /// gcc forces the alignment to 4 bytes, regardless of the type of the 5179 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 5180 /// gcc. 5181 ZeroLengthBitfieldBoundary = 32; 5182 5183 if (T.isOSBinFormatMachO() && IsAAPCS16) { 5184 assert(!BigEndian && "AAPCS16 does not support big-endian"); 5185 resetDataLayout("e-m:o-p:32:32-i64:64-a:0:32-n32-S128"); 5186 } else if (T.isOSBinFormatMachO()) 5187 resetDataLayout( 5188 BigEndian 5189 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5190 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5191 else 5192 resetDataLayout( 5193 BigEndian 5194 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 5195 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"); 5196 5197 // FIXME: Override "preferred align" for double and long long. 5198 } 5199 5200 void setArchInfo() { 5201 StringRef ArchName = getTriple().getArchName(); 5202 5203 ArchISA = llvm::ARM::parseArchISA(ArchName); 5204 CPU = llvm::ARM::getDefaultCPU(ArchName); 5205 unsigned AK = llvm::ARM::parseArch(ArchName); 5206 if (AK != llvm::ARM::AK_INVALID) 5207 ArchKind = AK; 5208 setArchInfo(ArchKind); 5209 } 5210 5211 void setArchInfo(unsigned Kind) { 5212 StringRef SubArch; 5213 5214 // cache TargetParser info 5215 ArchKind = Kind; 5216 SubArch = llvm::ARM::getSubArch(ArchKind); 5217 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 5218 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 5219 5220 // cache CPU related strings 5221 CPUAttr = getCPUAttr(); 5222 CPUProfile = getCPUProfile(); 5223 } 5224 5225 void setAtomic() { 5226 // when triple does not specify a sub arch, 5227 // then we are not using inline atomics 5228 bool ShouldUseInlineAtomic = 5229 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 5230 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 5231 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 5232 if (ArchProfile == llvm::ARM::PK_M) { 5233 MaxAtomicPromoteWidth = 32; 5234 if (ShouldUseInlineAtomic) 5235 MaxAtomicInlineWidth = 32; 5236 } 5237 else { 5238 MaxAtomicPromoteWidth = 64; 5239 if (ShouldUseInlineAtomic) 5240 MaxAtomicInlineWidth = 64; 5241 } 5242 } 5243 5244 bool isThumb() const { 5245 return (ArchISA == llvm::ARM::IK_THUMB); 5246 } 5247 5248 bool supportsThumb() const { 5249 return CPUAttr.count('T') || ArchVersion >= 6; 5250 } 5251 5252 bool supportsThumb2() const { 5253 return CPUAttr.equals("6T2") || 5254 (ArchVersion >= 7 && !CPUAttr.equals("8M_BASE")); 5255 } 5256 5257 StringRef getCPUAttr() const { 5258 // For most sub-arches, the build attribute CPU name is enough. 5259 // For Cortex variants, it's slightly different. 5260 switch(ArchKind) { 5261 default: 5262 return llvm::ARM::getCPUAttr(ArchKind); 5263 case llvm::ARM::AK_ARMV6M: 5264 return "6M"; 5265 case llvm::ARM::AK_ARMV7S: 5266 return "7S"; 5267 case llvm::ARM::AK_ARMV7A: 5268 return "7A"; 5269 case llvm::ARM::AK_ARMV7R: 5270 return "7R"; 5271 case llvm::ARM::AK_ARMV7M: 5272 return "7M"; 5273 case llvm::ARM::AK_ARMV7EM: 5274 return "7EM"; 5275 case llvm::ARM::AK_ARMV7VE: 5276 return "7VE"; 5277 case llvm::ARM::AK_ARMV8A: 5278 return "8A"; 5279 case llvm::ARM::AK_ARMV8_1A: 5280 return "8_1A"; 5281 case llvm::ARM::AK_ARMV8_2A: 5282 return "8_2A"; 5283 case llvm::ARM::AK_ARMV8MBaseline: 5284 return "8M_BASE"; 5285 case llvm::ARM::AK_ARMV8MMainline: 5286 return "8M_MAIN"; 5287 case llvm::ARM::AK_ARMV8R: 5288 return "8R"; 5289 } 5290 } 5291 5292 StringRef getCPUProfile() const { 5293 switch(ArchProfile) { 5294 case llvm::ARM::PK_A: 5295 return "A"; 5296 case llvm::ARM::PK_R: 5297 return "R"; 5298 case llvm::ARM::PK_M: 5299 return "M"; 5300 default: 5301 return ""; 5302 } 5303 } 5304 5305 public: 5306 ARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5307 : TargetInfo(Triple), FPMath(FP_Default), IsAAPCS(true), LDREX(0), 5308 HW_FP(0) { 5309 5310 switch (getTriple().getOS()) { 5311 case llvm::Triple::NetBSD: 5312 case llvm::Triple::OpenBSD: 5313 PtrDiffType = SignedLong; 5314 break; 5315 default: 5316 PtrDiffType = SignedInt; 5317 break; 5318 } 5319 5320 // Cache arch related info. 5321 setArchInfo(); 5322 5323 // {} in inline assembly are neon specifiers, not assembly variant 5324 // specifiers. 5325 NoAsmVariants = true; 5326 5327 // FIXME: This duplicates code from the driver that sets the -target-abi 5328 // option - this code is used if -target-abi isn't passed and should 5329 // be unified in some way. 5330 if (Triple.isOSBinFormatMachO()) { 5331 // The backend is hardwired to assume AAPCS for M-class processors, ensure 5332 // the frontend matches that. 5333 if (Triple.getEnvironment() == llvm::Triple::EABI || 5334 Triple.getOS() == llvm::Triple::UnknownOS || 5335 ArchProfile == llvm::ARM::PK_M) { 5336 setABI("aapcs"); 5337 } else if (Triple.isWatchABI()) { 5338 setABI("aapcs16"); 5339 } else { 5340 setABI("apcs-gnu"); 5341 } 5342 } else if (Triple.isOSWindows()) { 5343 // FIXME: this is invalid for WindowsCE 5344 setABI("aapcs"); 5345 } else { 5346 // Select the default based on the platform. 5347 switch (Triple.getEnvironment()) { 5348 case llvm::Triple::Android: 5349 case llvm::Triple::GNUEABI: 5350 case llvm::Triple::GNUEABIHF: 5351 case llvm::Triple::MuslEABI: 5352 case llvm::Triple::MuslEABIHF: 5353 setABI("aapcs-linux"); 5354 break; 5355 case llvm::Triple::EABIHF: 5356 case llvm::Triple::EABI: 5357 setABI("aapcs"); 5358 break; 5359 case llvm::Triple::GNU: 5360 setABI("apcs-gnu"); 5361 break; 5362 default: 5363 if (Triple.getOS() == llvm::Triple::NetBSD) 5364 setABI("apcs-gnu"); 5365 else if (Triple.getOS() == llvm::Triple::OpenBSD) 5366 setABI("aapcs-linux"); 5367 else 5368 setABI("aapcs"); 5369 break; 5370 } 5371 } 5372 5373 // ARM targets default to using the ARM C++ ABI. 5374 TheCXXABI.set(TargetCXXABI::GenericARM); 5375 5376 // ARM has atomics up to 8 bytes 5377 setAtomic(); 5378 5379 // Do force alignment of members that follow zero length bitfields. If 5380 // the alignment of the zero-length bitfield is greater than the member 5381 // that follows it, `bar', `bar' will be aligned as the type of the 5382 // zero length bitfield. 5383 UseZeroLengthBitfieldAlignment = true; 5384 5385 if (Triple.getOS() == llvm::Triple::Linux || 5386 Triple.getOS() == llvm::Triple::UnknownOS) 5387 this->MCountName = 5388 Opts.EABIVersion == "gnu" ? "\01__gnu_mcount_nc" : "\01mcount"; 5389 } 5390 5391 StringRef getABI() const override { return ABI; } 5392 5393 bool setABI(const std::string &Name) override { 5394 ABI = Name; 5395 5396 // The defaults (above) are for AAPCS, check if we need to change them. 5397 // 5398 // FIXME: We need support for -meabi... we could just mangle it into the 5399 // name. 5400 if (Name == "apcs-gnu" || Name == "aapcs16") { 5401 setABIAPCS(Name == "aapcs16"); 5402 return true; 5403 } 5404 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 5405 setABIAAPCS(); 5406 return true; 5407 } 5408 return false; 5409 } 5410 5411 // FIXME: This should be based on Arch attributes, not CPU names. 5412 bool 5413 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5414 StringRef CPU, 5415 const std::vector<std::string> &FeaturesVec) const override { 5416 5417 std::vector<StringRef> TargetFeatures; 5418 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 5419 5420 // get default FPU features 5421 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 5422 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 5423 5424 // get default Extension features 5425 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 5426 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 5427 5428 for (auto Feature : TargetFeatures) 5429 if (Feature[0] == '+') 5430 Features[Feature.drop_front(1)] = true; 5431 5432 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5433 } 5434 5435 bool handleTargetFeatures(std::vector<std::string> &Features, 5436 DiagnosticsEngine &Diags) override { 5437 FPU = 0; 5438 CRC = 0; 5439 Crypto = 0; 5440 DSP = 0; 5441 Unaligned = 1; 5442 SoftFloat = SoftFloatABI = false; 5443 HWDiv = 0; 5444 5445 // This does not diagnose illegal cases like having both 5446 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 5447 uint32_t HW_FP_remove = 0; 5448 for (const auto &Feature : Features) { 5449 if (Feature == "+soft-float") { 5450 SoftFloat = true; 5451 } else if (Feature == "+soft-float-abi") { 5452 SoftFloatABI = true; 5453 } else if (Feature == "+vfp2") { 5454 FPU |= VFP2FPU; 5455 HW_FP |= HW_FP_SP | HW_FP_DP; 5456 } else if (Feature == "+vfp3") { 5457 FPU |= VFP3FPU; 5458 HW_FP |= HW_FP_SP | HW_FP_DP; 5459 } else if (Feature == "+vfp4") { 5460 FPU |= VFP4FPU; 5461 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5462 } else if (Feature == "+fp-armv8") { 5463 FPU |= FPARMV8; 5464 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 5465 } else if (Feature == "+neon") { 5466 FPU |= NeonFPU; 5467 HW_FP |= HW_FP_SP | HW_FP_DP; 5468 } else if (Feature == "+hwdiv") { 5469 HWDiv |= HWDivThumb; 5470 } else if (Feature == "+hwdiv-arm") { 5471 HWDiv |= HWDivARM; 5472 } else if (Feature == "+crc") { 5473 CRC = 1; 5474 } else if (Feature == "+crypto") { 5475 Crypto = 1; 5476 } else if (Feature == "+dsp") { 5477 DSP = 1; 5478 } else if (Feature == "+fp-only-sp") { 5479 HW_FP_remove |= HW_FP_DP; 5480 } else if (Feature == "+strict-align") { 5481 Unaligned = 0; 5482 } else if (Feature == "+fp16") { 5483 HW_FP |= HW_FP_HP; 5484 } 5485 } 5486 HW_FP &= ~HW_FP_remove; 5487 5488 switch (ArchVersion) { 5489 case 6: 5490 if (ArchProfile == llvm::ARM::PK_M) 5491 LDREX = 0; 5492 else if (ArchKind == llvm::ARM::AK_ARMV6K) 5493 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5494 else 5495 LDREX = LDREX_W; 5496 break; 5497 case 7: 5498 if (ArchProfile == llvm::ARM::PK_M) 5499 LDREX = LDREX_W | LDREX_H | LDREX_B ; 5500 else 5501 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5502 break; 5503 case 8: 5504 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 5505 } 5506 5507 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 5508 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 5509 return false; 5510 } 5511 5512 if (FPMath == FP_Neon) 5513 Features.push_back("+neonfp"); 5514 else if (FPMath == FP_VFP) 5515 Features.push_back("-neonfp"); 5516 5517 // Remove front-end specific options which the backend handles differently. 5518 auto Feature = 5519 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 5520 if (Feature != Features.end()) 5521 Features.erase(Feature); 5522 5523 return true; 5524 } 5525 5526 bool hasFeature(StringRef Feature) const override { 5527 return llvm::StringSwitch<bool>(Feature) 5528 .Case("arm", true) 5529 .Case("aarch32", true) 5530 .Case("softfloat", SoftFloat) 5531 .Case("thumb", isThumb()) 5532 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 5533 .Case("vfp", FPU && !SoftFloat) 5534 .Case("hwdiv", HWDiv & HWDivThumb) 5535 .Case("hwdiv-arm", HWDiv & HWDivARM) 5536 .Default(false); 5537 } 5538 5539 bool setCPU(const std::string &Name) override { 5540 if (Name != "generic") 5541 setArchInfo(llvm::ARM::parseCPUArch(Name)); 5542 5543 if (ArchKind == llvm::ARM::AK_INVALID) 5544 return false; 5545 setAtomic(); 5546 CPU = Name; 5547 return true; 5548 } 5549 5550 bool setFPMath(StringRef Name) override; 5551 5552 void getTargetDefines(const LangOptions &Opts, 5553 MacroBuilder &Builder) const override { 5554 // Target identification. 5555 Builder.defineMacro("__arm"); 5556 Builder.defineMacro("__arm__"); 5557 // For bare-metal none-eabi. 5558 if (getTriple().getOS() == llvm::Triple::UnknownOS && 5559 (getTriple().getEnvironment() == llvm::Triple::EABI || 5560 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 5561 Builder.defineMacro("__ELF__"); 5562 5563 5564 // Target properties. 5565 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5566 5567 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 5568 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 5569 if (getTriple().isWatchABI()) 5570 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 5571 5572 if (!CPUAttr.empty()) 5573 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 5574 5575 // ACLE 6.4.1 ARM/Thumb instruction set architecture 5576 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 5577 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 5578 5579 if (ArchVersion >= 8) { 5580 // ACLE 6.5.7 Crypto Extension 5581 if (Crypto) 5582 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5583 // ACLE 6.5.8 CRC32 Extension 5584 if (CRC) 5585 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5586 // ACLE 6.5.10 Numeric Maximum and Minimum 5587 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5588 // ACLE 6.5.9 Directed Rounding 5589 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5590 } 5591 5592 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 5593 // is not defined for the M-profile. 5594 // NOTE that the default profile is assumed to be 'A' 5595 if (CPUProfile.empty() || ArchProfile != llvm::ARM::PK_M) 5596 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 5597 5598 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supports the original 5599 // Thumb ISA (including v6-M and v8-M Baseline). It is set to 2 if the 5600 // core supports the Thumb-2 ISA as found in the v6T2 architecture and all 5601 // v7 and v8 architectures excluding v8-M Baseline. 5602 if (supportsThumb2()) 5603 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 5604 else if (supportsThumb()) 5605 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 5606 5607 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 5608 // instruction set such as ARM or Thumb. 5609 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 5610 5611 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 5612 5613 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 5614 if (!CPUProfile.empty()) 5615 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 5616 5617 // ACLE 6.4.3 Unaligned access supported in hardware 5618 if (Unaligned) 5619 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5620 5621 // ACLE 6.4.4 LDREX/STREX 5622 if (LDREX) 5623 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 5624 5625 // ACLE 6.4.5 CLZ 5626 if (ArchVersion == 5 || 5627 (ArchVersion == 6 && CPUProfile != "M") || 5628 ArchVersion > 6) 5629 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5630 5631 // ACLE 6.5.1 Hardware Floating Point 5632 if (HW_FP) 5633 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 5634 5635 // ACLE predefines. 5636 Builder.defineMacro("__ARM_ACLE", "200"); 5637 5638 // FP16 support (we currently only support IEEE format). 5639 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5640 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5641 5642 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 5643 if (ArchVersion >= 7 && (FPU & VFP4FPU)) 5644 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5645 5646 // Subtarget options. 5647 5648 // FIXME: It's more complicated than this and we don't really support 5649 // interworking. 5650 // Windows on ARM does not "support" interworking 5651 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 5652 Builder.defineMacro("__THUMB_INTERWORK__"); 5653 5654 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 5655 // Embedded targets on Darwin follow AAPCS, but not EABI. 5656 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 5657 if (!getTriple().isOSBinFormatMachO() && !getTriple().isOSWindows()) 5658 Builder.defineMacro("__ARM_EABI__"); 5659 Builder.defineMacro("__ARM_PCS", "1"); 5660 } 5661 5662 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp" || 5663 ABI == "aapcs16") 5664 Builder.defineMacro("__ARM_PCS_VFP", "1"); 5665 5666 if (SoftFloat) 5667 Builder.defineMacro("__SOFTFP__"); 5668 5669 if (ArchKind == llvm::ARM::AK_XSCALE) 5670 Builder.defineMacro("__XSCALE__"); 5671 5672 if (isThumb()) { 5673 Builder.defineMacro("__THUMBEL__"); 5674 Builder.defineMacro("__thumb__"); 5675 if (supportsThumb2()) 5676 Builder.defineMacro("__thumb2__"); 5677 } 5678 5679 // ACLE 6.4.9 32-bit SIMD instructions 5680 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 5681 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 5682 5683 // ACLE 6.4.10 Hardware Integer Divide 5684 if (((HWDiv & HWDivThumb) && isThumb()) || 5685 ((HWDiv & HWDivARM) && !isThumb())) { 5686 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 5687 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 5688 } 5689 5690 // Note, this is always on in gcc, even though it doesn't make sense. 5691 Builder.defineMacro("__APCS_32__"); 5692 5693 if (FPUModeIsVFP((FPUMode) FPU)) { 5694 Builder.defineMacro("__VFP_FP__"); 5695 if (FPU & VFP2FPU) 5696 Builder.defineMacro("__ARM_VFPV2__"); 5697 if (FPU & VFP3FPU) 5698 Builder.defineMacro("__ARM_VFPV3__"); 5699 if (FPU & VFP4FPU) 5700 Builder.defineMacro("__ARM_VFPV4__"); 5701 if (FPU & FPARMV8) 5702 Builder.defineMacro("__ARM_FPV5__"); 5703 } 5704 5705 // This only gets set when Neon instructions are actually available, unlike 5706 // the VFP define, hence the soft float and arch check. This is subtly 5707 // different from gcc, we follow the intent which was that it should be set 5708 // when Neon instructions are actually available. 5709 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 5710 Builder.defineMacro("__ARM_NEON", "1"); 5711 Builder.defineMacro("__ARM_NEON__"); 5712 // current AArch32 NEON implementations do not support double-precision 5713 // floating-point even when it is present in VFP. 5714 Builder.defineMacro("__ARM_NEON_FP", 5715 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 5716 } 5717 5718 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 5719 Opts.ShortWChar ? "2" : "4"); 5720 5721 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5722 Opts.ShortEnums ? "1" : "4"); 5723 5724 if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") { 5725 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5726 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5727 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5728 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5729 } 5730 5731 // ACLE 6.4.7 DSP instructions 5732 if (DSP) { 5733 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 5734 } 5735 5736 // ACLE 6.4.8 Saturation instructions 5737 bool SAT = false; 5738 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 5739 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 5740 SAT = true; 5741 } 5742 5743 // ACLE 6.4.6 Q (saturation) flag 5744 if (DSP || SAT) 5745 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 5746 5747 if (Opts.UnsafeFPMath) 5748 Builder.defineMacro("__ARM_FP_FAST", "1"); 5749 5750 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 5751 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5752 } 5753 5754 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5755 return llvm::makeArrayRef(BuiltinInfo, 5756 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 5757 } 5758 bool isCLZForZeroUndef() const override { return false; } 5759 BuiltinVaListKind getBuiltinVaListKind() const override { 5760 return IsAAPCS 5761 ? AAPCSABIBuiltinVaList 5762 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5763 : TargetInfo::VoidPtrBuiltinVaList); 5764 } 5765 ArrayRef<const char *> getGCCRegNames() const override; 5766 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5767 bool validateAsmConstraint(const char *&Name, 5768 TargetInfo::ConstraintInfo &Info) const override { 5769 switch (*Name) { 5770 default: break; 5771 case 'l': // r0-r7 5772 case 'h': // r8-r15 5773 case 't': // VFP Floating point register single precision 5774 case 'w': // VFP Floating point register double precision 5775 Info.setAllowsRegister(); 5776 return true; 5777 case 'I': 5778 case 'J': 5779 case 'K': 5780 case 'L': 5781 case 'M': 5782 // FIXME 5783 return true; 5784 case 'Q': // A memory address that is a single base register. 5785 Info.setAllowsMemory(); 5786 return true; 5787 case 'U': // a memory reference... 5788 switch (Name[1]) { 5789 case 'q': // ...ARMV4 ldrsb 5790 case 'v': // ...VFP load/store (reg+constant offset) 5791 case 'y': // ...iWMMXt load/store 5792 case 't': // address valid for load/store opaque types wider 5793 // than 128-bits 5794 case 'n': // valid address for Neon doubleword vector load/store 5795 case 'm': // valid address for Neon element and structure load/store 5796 case 's': // valid address for non-offset loads/stores of quad-word 5797 // values in four ARM registers 5798 Info.setAllowsMemory(); 5799 Name++; 5800 return true; 5801 } 5802 } 5803 return false; 5804 } 5805 std::string convertConstraint(const char *&Constraint) const override { 5806 std::string R; 5807 switch (*Constraint) { 5808 case 'U': // Two-character constraint; add "^" hint for later parsing. 5809 R = std::string("^") + std::string(Constraint, 2); 5810 Constraint++; 5811 break; 5812 case 'p': // 'p' should be translated to 'r' by default. 5813 R = std::string("r"); 5814 break; 5815 default: 5816 return std::string(1, *Constraint); 5817 } 5818 return R; 5819 } 5820 bool 5821 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5822 std::string &SuggestedModifier) const override { 5823 bool isOutput = (Constraint[0] == '='); 5824 bool isInOut = (Constraint[0] == '+'); 5825 5826 // Strip off constraint modifiers. 5827 while (Constraint[0] == '=' || 5828 Constraint[0] == '+' || 5829 Constraint[0] == '&') 5830 Constraint = Constraint.substr(1); 5831 5832 switch (Constraint[0]) { 5833 default: break; 5834 case 'r': { 5835 switch (Modifier) { 5836 default: 5837 return (isInOut || isOutput || Size <= 64); 5838 case 'q': 5839 // A register of size 32 cannot fit a vector type. 5840 return false; 5841 } 5842 } 5843 } 5844 5845 return true; 5846 } 5847 const char *getClobbers() const override { 5848 // FIXME: Is this really right? 5849 return ""; 5850 } 5851 5852 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5853 switch (CC) { 5854 case CC_AAPCS: 5855 case CC_AAPCS_VFP: 5856 case CC_Swift: 5857 return CCCR_OK; 5858 default: 5859 return CCCR_Warning; 5860 } 5861 } 5862 5863 int getEHDataRegisterNumber(unsigned RegNo) const override { 5864 if (RegNo == 0) return 0; 5865 if (RegNo == 1) return 1; 5866 return -1; 5867 } 5868 5869 bool hasSjLjLowering() const override { 5870 return true; 5871 } 5872 }; 5873 5874 bool ARMTargetInfo::setFPMath(StringRef Name) { 5875 if (Name == "neon") { 5876 FPMath = FP_Neon; 5877 return true; 5878 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5879 Name == "vfp4") { 5880 FPMath = FP_VFP; 5881 return true; 5882 } 5883 return false; 5884 } 5885 5886 const char * const ARMTargetInfo::GCCRegNames[] = { 5887 // Integer registers 5888 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5889 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5890 5891 // Float registers 5892 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5893 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5894 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5895 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5896 5897 // Double registers 5898 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5899 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5900 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5901 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5902 5903 // Quad registers 5904 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5905 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5906 }; 5907 5908 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5909 return llvm::makeArrayRef(GCCRegNames); 5910 } 5911 5912 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5913 { { "a1" }, "r0" }, 5914 { { "a2" }, "r1" }, 5915 { { "a3" }, "r2" }, 5916 { { "a4" }, "r3" }, 5917 { { "v1" }, "r4" }, 5918 { { "v2" }, "r5" }, 5919 { { "v3" }, "r6" }, 5920 { { "v4" }, "r7" }, 5921 { { "v5" }, "r8" }, 5922 { { "v6", "rfp" }, "r9" }, 5923 { { "sl" }, "r10" }, 5924 { { "fp" }, "r11" }, 5925 { { "ip" }, "r12" }, 5926 { { "r13" }, "sp" }, 5927 { { "r14" }, "lr" }, 5928 { { "r15" }, "pc" }, 5929 // The S, D and Q registers overlap, but aren't really aliases; we 5930 // don't want to substitute one of these for a different-sized one. 5931 }; 5932 5933 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5934 return llvm::makeArrayRef(GCCRegAliases); 5935 } 5936 5937 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5938 #define BUILTIN(ID, TYPE, ATTRS) \ 5939 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5940 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5941 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5942 #include "clang/Basic/BuiltinsNEON.def" 5943 5944 #define BUILTIN(ID, TYPE, ATTRS) \ 5945 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5946 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5947 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5948 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5949 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5950 #define TARGET_HEADER_BUILTIN(ID, TYPE, ATTRS, HEADER, LANGS, FEATURE) \ 5951 { #ID, TYPE, ATTRS, HEADER, LANGS, FEATURE }, 5952 #include "clang/Basic/BuiltinsARM.def" 5953 }; 5954 5955 class ARMleTargetInfo : public ARMTargetInfo { 5956 public: 5957 ARMleTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5958 : ARMTargetInfo(Triple, Opts) {} 5959 void getTargetDefines(const LangOptions &Opts, 5960 MacroBuilder &Builder) const override { 5961 Builder.defineMacro("__ARMEL__"); 5962 ARMTargetInfo::getTargetDefines(Opts, Builder); 5963 } 5964 }; 5965 5966 class ARMbeTargetInfo : public ARMTargetInfo { 5967 public: 5968 ARMbeTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5969 : ARMTargetInfo(Triple, Opts) {} 5970 void getTargetDefines(const LangOptions &Opts, 5971 MacroBuilder &Builder) const override { 5972 Builder.defineMacro("__ARMEB__"); 5973 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5974 ARMTargetInfo::getTargetDefines(Opts, Builder); 5975 } 5976 }; 5977 5978 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5979 const llvm::Triple Triple; 5980 public: 5981 WindowsARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 5982 : WindowsTargetInfo<ARMleTargetInfo>(Triple, Opts), Triple(Triple) { 5983 WCharType = UnsignedShort; 5984 SizeType = UnsignedInt; 5985 } 5986 void getVisualStudioDefines(const LangOptions &Opts, 5987 MacroBuilder &Builder) const { 5988 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5989 5990 // FIXME: this is invalid for WindowsCE 5991 Builder.defineMacro("_M_ARM_NT", "1"); 5992 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5993 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5994 5995 assert((Triple.getArch() == llvm::Triple::arm || 5996 Triple.getArch() == llvm::Triple::thumb) && 5997 "invalid architecture for Windows ARM target info"); 5998 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5999 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 6000 6001 // TODO map the complete set of values 6002 // 31: VFPv3 40: VFPv4 6003 Builder.defineMacro("_M_ARM_FP", "31"); 6004 } 6005 BuiltinVaListKind getBuiltinVaListKind() const override { 6006 return TargetInfo::CharPtrBuiltinVaList; 6007 } 6008 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6009 switch (CC) { 6010 case CC_X86StdCall: 6011 case CC_X86ThisCall: 6012 case CC_X86FastCall: 6013 case CC_X86VectorCall: 6014 return CCCR_Ignore; 6015 case CC_C: 6016 return CCCR_OK; 6017 default: 6018 return CCCR_Warning; 6019 } 6020 } 6021 }; 6022 6023 // Windows ARM + Itanium C++ ABI Target 6024 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 6025 public: 6026 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple, 6027 const TargetOptions &Opts) 6028 : WindowsARMTargetInfo(Triple, Opts) { 6029 TheCXXABI.set(TargetCXXABI::GenericARM); 6030 } 6031 6032 void getTargetDefines(const LangOptions &Opts, 6033 MacroBuilder &Builder) const override { 6034 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6035 6036 if (Opts.MSVCCompat) 6037 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6038 } 6039 }; 6040 6041 // Windows ARM, MS (C++) ABI 6042 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 6043 public: 6044 MicrosoftARMleTargetInfo(const llvm::Triple &Triple, 6045 const TargetOptions &Opts) 6046 : WindowsARMTargetInfo(Triple, Opts) { 6047 TheCXXABI.set(TargetCXXABI::Microsoft); 6048 } 6049 6050 void getTargetDefines(const LangOptions &Opts, 6051 MacroBuilder &Builder) const override { 6052 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6053 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 6054 } 6055 }; 6056 6057 // ARM MinGW target 6058 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 6059 public: 6060 MinGWARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6061 : WindowsARMTargetInfo(Triple, Opts) { 6062 TheCXXABI.set(TargetCXXABI::GenericARM); 6063 } 6064 6065 void getTargetDefines(const LangOptions &Opts, 6066 MacroBuilder &Builder) const override { 6067 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 6068 DefineStd(Builder, "WIN32", Opts); 6069 DefineStd(Builder, "WINNT", Opts); 6070 Builder.defineMacro("_ARM_"); 6071 addMinGWDefines(Opts, Builder); 6072 } 6073 }; 6074 6075 // ARM Cygwin target 6076 class CygwinARMTargetInfo : public ARMleTargetInfo { 6077 public: 6078 CygwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6079 : ARMleTargetInfo(Triple, Opts) { 6080 TLSSupported = false; 6081 WCharType = UnsignedShort; 6082 DoubleAlign = LongLongAlign = 64; 6083 resetDataLayout("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"); 6084 } 6085 void getTargetDefines(const LangOptions &Opts, 6086 MacroBuilder &Builder) const override { 6087 ARMleTargetInfo::getTargetDefines(Opts, Builder); 6088 Builder.defineMacro("_ARM_"); 6089 Builder.defineMacro("__CYGWIN__"); 6090 Builder.defineMacro("__CYGWIN32__"); 6091 DefineStd(Builder, "unix", Opts); 6092 if (Opts.CPlusPlus) 6093 Builder.defineMacro("_GNU_SOURCE"); 6094 } 6095 }; 6096 6097 class DarwinARMTargetInfo : public DarwinTargetInfo<ARMleTargetInfo> { 6098 protected: 6099 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6100 MacroBuilder &Builder) const override { 6101 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6102 } 6103 6104 public: 6105 DarwinARMTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6106 : DarwinTargetInfo<ARMleTargetInfo>(Triple, Opts) { 6107 HasAlignMac68kSupport = true; 6108 // iOS always has 64-bit atomic instructions. 6109 // FIXME: This should be based off of the target features in 6110 // ARMleTargetInfo. 6111 MaxAtomicInlineWidth = 64; 6112 6113 if (Triple.isWatchABI()) { 6114 // Darwin on iOS uses a variant of the ARM C++ ABI. 6115 TheCXXABI.set(TargetCXXABI::WatchOS); 6116 6117 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 6118 // size_t is long, it's a bit weird for it to be int. 6119 PtrDiffType = SignedLong; 6120 6121 // BOOL should be a real boolean on the new ABI 6122 UseSignedCharForObjCBool = false; 6123 } else 6124 TheCXXABI.set(TargetCXXABI::iOS); 6125 } 6126 }; 6127 6128 class AArch64TargetInfo : public TargetInfo { 6129 virtual void setDataLayout() = 0; 6130 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6131 static const char *const GCCRegNames[]; 6132 6133 enum FPUModeEnum { 6134 FPUMode, 6135 NeonMode 6136 }; 6137 6138 unsigned FPU; 6139 unsigned CRC; 6140 unsigned Crypto; 6141 unsigned Unaligned; 6142 unsigned V8_1A; 6143 6144 static const Builtin::Info BuiltinInfo[]; 6145 6146 std::string ABI; 6147 6148 public: 6149 AArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6150 : TargetInfo(Triple), ABI("aapcs") { 6151 if (getTriple().getOS() == llvm::Triple::NetBSD || 6152 getTriple().getOS() == llvm::Triple::OpenBSD) { 6153 WCharType = SignedInt; 6154 6155 // NetBSD apparently prefers consistency across ARM targets to consistency 6156 // across 64-bit targets. 6157 Int64Type = SignedLongLong; 6158 IntMaxType = SignedLongLong; 6159 } else { 6160 WCharType = UnsignedInt; 6161 Int64Type = SignedLong; 6162 IntMaxType = SignedLong; 6163 } 6164 6165 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6166 MaxVectorAlign = 128; 6167 MaxAtomicInlineWidth = 128; 6168 MaxAtomicPromoteWidth = 128; 6169 6170 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 6171 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 6172 6173 // {} in inline assembly are neon specifiers, not assembly variant 6174 // specifiers. 6175 NoAsmVariants = true; 6176 6177 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 6178 // contributes to the alignment of the containing aggregate in the same way 6179 // a plain (non bit-field) member of that type would, without exception for 6180 // zero-sized or anonymous bit-fields." 6181 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 6182 UseZeroLengthBitfieldAlignment = true; 6183 6184 // AArch64 targets default to using the ARM C++ ABI. 6185 TheCXXABI.set(TargetCXXABI::GenericAArch64); 6186 6187 if (Triple.getOS() == llvm::Triple::Linux) 6188 this->MCountName = "\01_mcount"; 6189 else if (Triple.getOS() == llvm::Triple::UnknownOS) 6190 this->MCountName = Opts.EABIVersion == "gnu" ? "\01_mcount" : "mcount"; 6191 } 6192 6193 StringRef getABI() const override { return ABI; } 6194 bool setABI(const std::string &Name) override { 6195 if (Name != "aapcs" && Name != "darwinpcs") 6196 return false; 6197 6198 ABI = Name; 6199 return true; 6200 } 6201 6202 bool setCPU(const std::string &Name) override { 6203 return Name == "generic" || 6204 llvm::AArch64::parseCPUArch(Name) != 6205 static_cast<unsigned>(llvm::AArch64::ArchKind::AK_INVALID); 6206 } 6207 6208 void getTargetDefines(const LangOptions &Opts, 6209 MacroBuilder &Builder) const override { 6210 // Target identification. 6211 Builder.defineMacro("__aarch64__"); 6212 // For bare-metal none-eabi. 6213 if (getTriple().getOS() == llvm::Triple::UnknownOS && 6214 (getTriple().getEnvironment() == llvm::Triple::EABI || 6215 getTriple().getEnvironment() == llvm::Triple::EABIHF)) 6216 Builder.defineMacro("__ELF__"); 6217 6218 // Target properties. 6219 Builder.defineMacro("_LP64"); 6220 Builder.defineMacro("__LP64__"); 6221 6222 // ACLE predefines. Many can only have one possible value on v8 AArch64. 6223 Builder.defineMacro("__ARM_ACLE", "200"); 6224 Builder.defineMacro("__ARM_ARCH", "8"); 6225 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 6226 6227 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 6228 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 6229 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 6230 6231 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 6232 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 6233 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 6234 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 6235 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 6236 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 6237 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 6238 6239 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 6240 6241 // 0xe implies support for half, single and double precision operations. 6242 Builder.defineMacro("__ARM_FP", "0xE"); 6243 6244 // PCS specifies this for SysV variants, which is all we support. Other ABIs 6245 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 6246 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 6247 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 6248 6249 if (Opts.UnsafeFPMath) 6250 Builder.defineMacro("__ARM_FP_FAST", "1"); 6251 6252 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 6253 6254 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 6255 Opts.ShortEnums ? "1" : "4"); 6256 6257 if (FPU == NeonMode) { 6258 Builder.defineMacro("__ARM_NEON", "1"); 6259 // 64-bit NEON supports half, single and double precision operations. 6260 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 6261 } 6262 6263 if (CRC) 6264 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 6265 6266 if (Crypto) 6267 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 6268 6269 if (Unaligned) 6270 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 6271 6272 if (V8_1A) 6273 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 6274 6275 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 6276 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6277 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6278 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6279 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6280 } 6281 6282 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6283 return llvm::makeArrayRef(BuiltinInfo, 6284 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 6285 } 6286 6287 bool hasFeature(StringRef Feature) const override { 6288 return Feature == "aarch64" || 6289 Feature == "arm64" || 6290 Feature == "arm" || 6291 (Feature == "neon" && FPU == NeonMode); 6292 } 6293 6294 bool handleTargetFeatures(std::vector<std::string> &Features, 6295 DiagnosticsEngine &Diags) override { 6296 FPU = FPUMode; 6297 CRC = 0; 6298 Crypto = 0; 6299 Unaligned = 1; 6300 V8_1A = 0; 6301 6302 for (const auto &Feature : Features) { 6303 if (Feature == "+neon") 6304 FPU = NeonMode; 6305 if (Feature == "+crc") 6306 CRC = 1; 6307 if (Feature == "+crypto") 6308 Crypto = 1; 6309 if (Feature == "+strict-align") 6310 Unaligned = 0; 6311 if (Feature == "+v8.1a") 6312 V8_1A = 1; 6313 } 6314 6315 setDataLayout(); 6316 6317 return true; 6318 } 6319 6320 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 6321 switch (CC) { 6322 case CC_C: 6323 case CC_Swift: 6324 case CC_PreserveMost: 6325 case CC_PreserveAll: 6326 return CCCR_OK; 6327 default: 6328 return CCCR_Warning; 6329 } 6330 } 6331 6332 bool isCLZForZeroUndef() const override { return false; } 6333 6334 BuiltinVaListKind getBuiltinVaListKind() const override { 6335 return TargetInfo::AArch64ABIBuiltinVaList; 6336 } 6337 6338 ArrayRef<const char *> getGCCRegNames() const override; 6339 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6340 6341 bool validateAsmConstraint(const char *&Name, 6342 TargetInfo::ConstraintInfo &Info) const override { 6343 switch (*Name) { 6344 default: 6345 return false; 6346 case 'w': // Floating point and SIMD registers (V0-V31) 6347 Info.setAllowsRegister(); 6348 return true; 6349 case 'I': // Constant that can be used with an ADD instruction 6350 case 'J': // Constant that can be used with a SUB instruction 6351 case 'K': // Constant that can be used with a 32-bit logical instruction 6352 case 'L': // Constant that can be used with a 64-bit logical instruction 6353 case 'M': // Constant that can be used as a 32-bit MOV immediate 6354 case 'N': // Constant that can be used as a 64-bit MOV immediate 6355 case 'Y': // Floating point constant zero 6356 case 'Z': // Integer constant zero 6357 return true; 6358 case 'Q': // A memory reference with base register and no offset 6359 Info.setAllowsMemory(); 6360 return true; 6361 case 'S': // A symbolic address 6362 Info.setAllowsRegister(); 6363 return true; 6364 case 'U': 6365 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 6366 // Utf: A memory address suitable for ldp/stp in TF mode. 6367 // Usa: An absolute symbolic address. 6368 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 6369 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 6370 case 'z': // Zero register, wzr or xzr 6371 Info.setAllowsRegister(); 6372 return true; 6373 case 'x': // Floating point and SIMD registers (V0-V15) 6374 Info.setAllowsRegister(); 6375 return true; 6376 } 6377 return false; 6378 } 6379 6380 bool 6381 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 6382 std::string &SuggestedModifier) const override { 6383 // Strip off constraint modifiers. 6384 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 6385 Constraint = Constraint.substr(1); 6386 6387 switch (Constraint[0]) { 6388 default: 6389 return true; 6390 case 'z': 6391 case 'r': { 6392 switch (Modifier) { 6393 case 'x': 6394 case 'w': 6395 // For now assume that the person knows what they're 6396 // doing with the modifier. 6397 return true; 6398 default: 6399 // By default an 'r' constraint will be in the 'x' 6400 // registers. 6401 if (Size == 64) 6402 return true; 6403 6404 SuggestedModifier = "w"; 6405 return false; 6406 } 6407 } 6408 } 6409 } 6410 6411 const char *getClobbers() const override { return ""; } 6412 6413 int getEHDataRegisterNumber(unsigned RegNo) const override { 6414 if (RegNo == 0) 6415 return 0; 6416 if (RegNo == 1) 6417 return 1; 6418 return -1; 6419 } 6420 }; 6421 6422 const char *const AArch64TargetInfo::GCCRegNames[] = { 6423 // 32-bit Integer registers 6424 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 6425 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 6426 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 6427 6428 // 64-bit Integer registers 6429 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 6430 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 6431 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 6432 6433 // 32-bit floating point regsisters 6434 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 6435 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 6436 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 6437 6438 // 64-bit floating point regsisters 6439 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 6440 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 6441 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 6442 6443 // Vector registers 6444 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 6445 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 6446 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 6447 }; 6448 6449 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 6450 return llvm::makeArrayRef(GCCRegNames); 6451 } 6452 6453 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 6454 { { "w31" }, "wsp" }, 6455 { { "x29" }, "fp" }, 6456 { { "x30" }, "lr" }, 6457 { { "x31" }, "sp" }, 6458 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 6459 // don't want to substitute one of these for a different-sized one. 6460 }; 6461 6462 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 6463 return llvm::makeArrayRef(GCCRegAliases); 6464 } 6465 6466 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 6467 #define BUILTIN(ID, TYPE, ATTRS) \ 6468 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6469 #include "clang/Basic/BuiltinsNEON.def" 6470 6471 #define BUILTIN(ID, TYPE, ATTRS) \ 6472 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6473 #include "clang/Basic/BuiltinsAArch64.def" 6474 }; 6475 6476 class AArch64leTargetInfo : public AArch64TargetInfo { 6477 void setDataLayout() override { 6478 if (getTriple().isOSBinFormatMachO()) 6479 resetDataLayout("e-m:o-i64:64-i128:128-n32:64-S128"); 6480 else 6481 resetDataLayout("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6482 } 6483 6484 public: 6485 AArch64leTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6486 : AArch64TargetInfo(Triple, Opts) { 6487 } 6488 void getTargetDefines(const LangOptions &Opts, 6489 MacroBuilder &Builder) const override { 6490 Builder.defineMacro("__AARCH64EL__"); 6491 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6492 } 6493 }; 6494 6495 class AArch64beTargetInfo : public AArch64TargetInfo { 6496 void setDataLayout() override { 6497 assert(!getTriple().isOSBinFormatMachO()); 6498 resetDataLayout("E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"); 6499 } 6500 6501 public: 6502 AArch64beTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6503 : AArch64TargetInfo(Triple, Opts) {} 6504 void getTargetDefines(const LangOptions &Opts, 6505 MacroBuilder &Builder) const override { 6506 Builder.defineMacro("__AARCH64EB__"); 6507 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 6508 Builder.defineMacro("__ARM_BIG_ENDIAN"); 6509 AArch64TargetInfo::getTargetDefines(Opts, Builder); 6510 } 6511 }; 6512 6513 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 6514 protected: 6515 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 6516 MacroBuilder &Builder) const override { 6517 Builder.defineMacro("__AARCH64_SIMD__"); 6518 Builder.defineMacro("__ARM64_ARCH_8__"); 6519 Builder.defineMacro("__ARM_NEON__"); 6520 Builder.defineMacro("__LITTLE_ENDIAN__"); 6521 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6522 Builder.defineMacro("__arm64", "1"); 6523 Builder.defineMacro("__arm64__", "1"); 6524 6525 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 6526 } 6527 6528 public: 6529 DarwinAArch64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 6530 : DarwinTargetInfo<AArch64leTargetInfo>(Triple, Opts) { 6531 Int64Type = SignedLongLong; 6532 WCharType = SignedInt; 6533 UseSignedCharForObjCBool = false; 6534 6535 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 6536 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 6537 6538 TheCXXABI.set(TargetCXXABI::iOS64); 6539 } 6540 6541 BuiltinVaListKind getBuiltinVaListKind() const override { 6542 return TargetInfo::CharPtrBuiltinVaList; 6543 } 6544 }; 6545 6546 // Hexagon abstract base class 6547 class HexagonTargetInfo : public TargetInfo { 6548 static const Builtin::Info BuiltinInfo[]; 6549 static const char * const GCCRegNames[]; 6550 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6551 std::string CPU; 6552 bool HasHVX, HasHVXDouble; 6553 bool UseLongCalls; 6554 6555 public: 6556 HexagonTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6557 : TargetInfo(Triple) { 6558 // Specify the vector alignment explicitly. For v512x1, the calculated 6559 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 6560 // the required minimum of 64 bytes. 6561 resetDataLayout("e-m:e-p:32:32:32-a:0-n16:32-" 6562 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 6563 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"); 6564 SizeType = UnsignedInt; 6565 PtrDiffType = SignedInt; 6566 IntPtrType = SignedInt; 6567 6568 // {} in inline assembly are packet specifiers, not assembly variant 6569 // specifiers. 6570 NoAsmVariants = true; 6571 6572 LargeArrayMinWidth = 64; 6573 LargeArrayAlign = 64; 6574 UseBitFieldTypeAlignment = true; 6575 ZeroLengthBitfieldBoundary = 32; 6576 HasHVX = HasHVXDouble = false; 6577 UseLongCalls = false; 6578 } 6579 6580 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6581 return llvm::makeArrayRef(BuiltinInfo, 6582 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 6583 } 6584 6585 bool validateAsmConstraint(const char *&Name, 6586 TargetInfo::ConstraintInfo &Info) const override { 6587 switch (*Name) { 6588 case 'v': 6589 case 'q': 6590 if (HasHVX) { 6591 Info.setAllowsRegister(); 6592 return true; 6593 } 6594 break; 6595 case 's': 6596 // Relocatable constant. 6597 return true; 6598 } 6599 return false; 6600 } 6601 6602 void getTargetDefines(const LangOptions &Opts, 6603 MacroBuilder &Builder) const override; 6604 6605 bool isCLZForZeroUndef() const override { return false; } 6606 6607 bool hasFeature(StringRef Feature) const override { 6608 return llvm::StringSwitch<bool>(Feature) 6609 .Case("hexagon", true) 6610 .Case("hvx", HasHVX) 6611 .Case("hvx-double", HasHVXDouble) 6612 .Case("long-calls", UseLongCalls) 6613 .Default(false); 6614 } 6615 6616 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6617 StringRef CPU, const std::vector<std::string> &FeaturesVec) 6618 const override; 6619 6620 bool handleTargetFeatures(std::vector<std::string> &Features, 6621 DiagnosticsEngine &Diags) override; 6622 6623 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 6624 bool Enabled) const override; 6625 6626 BuiltinVaListKind getBuiltinVaListKind() const override { 6627 return TargetInfo::CharPtrBuiltinVaList; 6628 } 6629 ArrayRef<const char *> getGCCRegNames() const override; 6630 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6631 const char *getClobbers() const override { 6632 return ""; 6633 } 6634 6635 static const char *getHexagonCPUSuffix(StringRef Name) { 6636 return llvm::StringSwitch<const char*>(Name) 6637 .Case("hexagonv4", "4") 6638 .Case("hexagonv5", "5") 6639 .Case("hexagonv55", "55") 6640 .Case("hexagonv60", "60") 6641 .Case("hexagonv62", "62") 6642 .Default(nullptr); 6643 } 6644 6645 bool setCPU(const std::string &Name) override { 6646 if (!getHexagonCPUSuffix(Name)) 6647 return false; 6648 CPU = Name; 6649 return true; 6650 } 6651 6652 int getEHDataRegisterNumber(unsigned RegNo) const override { 6653 return RegNo < 2 ? RegNo : -1; 6654 } 6655 }; 6656 6657 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 6658 MacroBuilder &Builder) const { 6659 Builder.defineMacro("__qdsp6__", "1"); 6660 Builder.defineMacro("__hexagon__", "1"); 6661 6662 if (CPU == "hexagonv4") { 6663 Builder.defineMacro("__HEXAGON_V4__"); 6664 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 6665 if (Opts.HexagonQdsp6Compat) { 6666 Builder.defineMacro("__QDSP6_V4__"); 6667 Builder.defineMacro("__QDSP6_ARCH__", "4"); 6668 } 6669 } else if (CPU == "hexagonv5") { 6670 Builder.defineMacro("__HEXAGON_V5__"); 6671 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 6672 if(Opts.HexagonQdsp6Compat) { 6673 Builder.defineMacro("__QDSP6_V5__"); 6674 Builder.defineMacro("__QDSP6_ARCH__", "5"); 6675 } 6676 } else if (CPU == "hexagonv55") { 6677 Builder.defineMacro("__HEXAGON_V55__"); 6678 Builder.defineMacro("__HEXAGON_ARCH__", "55"); 6679 Builder.defineMacro("__QDSP6_V55__"); 6680 Builder.defineMacro("__QDSP6_ARCH__", "55"); 6681 } else if (CPU == "hexagonv60") { 6682 Builder.defineMacro("__HEXAGON_V60__"); 6683 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 6684 Builder.defineMacro("__QDSP6_V60__"); 6685 Builder.defineMacro("__QDSP6_ARCH__", "60"); 6686 } else if (CPU == "hexagonv62") { 6687 Builder.defineMacro("__HEXAGON_V62__"); 6688 Builder.defineMacro("__HEXAGON_ARCH__", "62"); 6689 } 6690 6691 if (hasFeature("hvx")) { 6692 Builder.defineMacro("__HVX__"); 6693 if (hasFeature("hvx-double")) 6694 Builder.defineMacro("__HVXDBL__"); 6695 } 6696 } 6697 6698 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 6699 DiagnosticsEngine &Diags, StringRef CPU, 6700 const std::vector<std::string> &FeaturesVec) const { 6701 // Default for v60: -hvx, -hvx-double. 6702 Features["hvx"] = false; 6703 Features["hvx-double"] = false; 6704 Features["long-calls"] = false; 6705 6706 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6707 } 6708 6709 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 6710 DiagnosticsEngine &Diags) { 6711 for (auto &F : Features) { 6712 if (F == "+hvx") 6713 HasHVX = true; 6714 else if (F == "-hvx") 6715 HasHVX = HasHVXDouble = false; 6716 else if (F == "+hvx-double") 6717 HasHVX = HasHVXDouble = true; 6718 else if (F == "-hvx-double") 6719 HasHVXDouble = false; 6720 6721 if (F == "+long-calls") 6722 UseLongCalls = true; 6723 else if (F == "-long-calls") 6724 UseLongCalls = false; 6725 } 6726 return true; 6727 } 6728 6729 void HexagonTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 6730 StringRef Name, bool Enabled) const { 6731 if (Enabled) { 6732 if (Name == "hvx-double") 6733 Features["hvx"] = true; 6734 } else { 6735 if (Name == "hvx") 6736 Features["hvx-double"] = false; 6737 } 6738 Features[Name] = Enabled; 6739 } 6740 6741 const char *const HexagonTargetInfo::GCCRegNames[] = { 6742 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6743 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6744 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6745 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 6746 "p0", "p1", "p2", "p3", 6747 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 6748 }; 6749 6750 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 6751 return llvm::makeArrayRef(GCCRegNames); 6752 } 6753 6754 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 6755 { { "sp" }, "r29" }, 6756 { { "fp" }, "r30" }, 6757 { { "lr" }, "r31" }, 6758 }; 6759 6760 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 6761 return llvm::makeArrayRef(GCCRegAliases); 6762 } 6763 6764 6765 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 6766 #define BUILTIN(ID, TYPE, ATTRS) \ 6767 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6768 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6769 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6770 #include "clang/Basic/BuiltinsHexagon.def" 6771 }; 6772 6773 class LanaiTargetInfo : public TargetInfo { 6774 // Class for Lanai (32-bit). 6775 // The CPU profiles supported by the Lanai backend 6776 enum CPUKind { 6777 CK_NONE, 6778 CK_V11, 6779 } CPU; 6780 6781 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6782 static const char *const GCCRegNames[]; 6783 6784 public: 6785 LanaiTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6786 : TargetInfo(Triple) { 6787 // Description string has to be kept in sync with backend. 6788 resetDataLayout("E" // Big endian 6789 "-m:e" // ELF name manging 6790 "-p:32:32" // 32 bit pointers, 32 bit aligned 6791 "-i64:64" // 64 bit integers, 64 bit aligned 6792 "-a:0:32" // 32 bit alignment of objects of aggregate type 6793 "-n32" // 32 bit native integer width 6794 "-S64" // 64 bit natural stack alignment 6795 ); 6796 6797 // Setting RegParmMax equal to what mregparm was set to in the old 6798 // toolchain 6799 RegParmMax = 4; 6800 6801 // Set the default CPU to V11 6802 CPU = CK_V11; 6803 6804 // Temporary approach to make everything at least word-aligned and allow for 6805 // safely casting between pointers with different alignment requirements. 6806 // TODO: Remove this when there are no more cast align warnings on the 6807 // firmware. 6808 MinGlobalAlign = 32; 6809 } 6810 6811 void getTargetDefines(const LangOptions &Opts, 6812 MacroBuilder &Builder) const override { 6813 // Define __lanai__ when building for target lanai. 6814 Builder.defineMacro("__lanai__"); 6815 6816 // Set define for the CPU specified. 6817 switch (CPU) { 6818 case CK_V11: 6819 Builder.defineMacro("__LANAI_V11__"); 6820 break; 6821 case CK_NONE: 6822 llvm_unreachable("Unhandled target CPU"); 6823 } 6824 } 6825 6826 bool setCPU(const std::string &Name) override { 6827 CPU = llvm::StringSwitch<CPUKind>(Name) 6828 .Case("v11", CK_V11) 6829 .Default(CK_NONE); 6830 6831 return CPU != CK_NONE; 6832 } 6833 6834 bool hasFeature(StringRef Feature) const override { 6835 return llvm::StringSwitch<bool>(Feature).Case("lanai", true).Default(false); 6836 } 6837 6838 ArrayRef<const char *> getGCCRegNames() const override; 6839 6840 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6841 6842 BuiltinVaListKind getBuiltinVaListKind() const override { 6843 return TargetInfo::VoidPtrBuiltinVaList; 6844 } 6845 6846 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6847 6848 bool validateAsmConstraint(const char *&Name, 6849 TargetInfo::ConstraintInfo &info) const override { 6850 return false; 6851 } 6852 6853 const char *getClobbers() const override { return ""; } 6854 }; 6855 6856 const char *const LanaiTargetInfo::GCCRegNames[] = { 6857 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", 6858 "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", "r20", "r21", 6859 "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"}; 6860 6861 ArrayRef<const char *> LanaiTargetInfo::getGCCRegNames() const { 6862 return llvm::makeArrayRef(GCCRegNames); 6863 } 6864 6865 const TargetInfo::GCCRegAlias LanaiTargetInfo::GCCRegAliases[] = { 6866 {{"pc"}, "r2"}, 6867 {{"sp"}, "r4"}, 6868 {{"fp"}, "r5"}, 6869 {{"rv"}, "r8"}, 6870 {{"rr1"}, "r10"}, 6871 {{"rr2"}, "r11"}, 6872 {{"rca"}, "r15"}, 6873 }; 6874 6875 ArrayRef<TargetInfo::GCCRegAlias> LanaiTargetInfo::getGCCRegAliases() const { 6876 return llvm::makeArrayRef(GCCRegAliases); 6877 } 6878 6879 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 6880 class SparcTargetInfo : public TargetInfo { 6881 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 6882 static const char * const GCCRegNames[]; 6883 bool SoftFloat; 6884 public: 6885 SparcTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 6886 : TargetInfo(Triple), SoftFloat(false) {} 6887 6888 int getEHDataRegisterNumber(unsigned RegNo) const override { 6889 if (RegNo == 0) return 24; 6890 if (RegNo == 1) return 25; 6891 return -1; 6892 } 6893 6894 bool handleTargetFeatures(std::vector<std::string> &Features, 6895 DiagnosticsEngine &Diags) override { 6896 // Check if software floating point is enabled 6897 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 6898 if (Feature != Features.end()) { 6899 SoftFloat = true; 6900 } 6901 return true; 6902 } 6903 void getTargetDefines(const LangOptions &Opts, 6904 MacroBuilder &Builder) const override { 6905 DefineStd(Builder, "sparc", Opts); 6906 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6907 6908 if (SoftFloat) 6909 Builder.defineMacro("SOFT_FLOAT", "1"); 6910 } 6911 6912 bool hasFeature(StringRef Feature) const override { 6913 return llvm::StringSwitch<bool>(Feature) 6914 .Case("softfloat", SoftFloat) 6915 .Case("sparc", true) 6916 .Default(false); 6917 } 6918 6919 bool hasSjLjLowering() const override { 6920 return true; 6921 } 6922 6923 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6924 // FIXME: Implement! 6925 return None; 6926 } 6927 BuiltinVaListKind getBuiltinVaListKind() const override { 6928 return TargetInfo::VoidPtrBuiltinVaList; 6929 } 6930 ArrayRef<const char *> getGCCRegNames() const override; 6931 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 6932 bool validateAsmConstraint(const char *&Name, 6933 TargetInfo::ConstraintInfo &info) const override { 6934 // FIXME: Implement! 6935 switch (*Name) { 6936 case 'I': // Signed 13-bit constant 6937 case 'J': // Zero 6938 case 'K': // 32-bit constant with the low 12 bits clear 6939 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 6940 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 6941 case 'N': // Same as 'K' but zext (required for SIMode) 6942 case 'O': // The constant 4096 6943 return true; 6944 6945 case 'f': 6946 case 'e': 6947 info.setAllowsRegister(); 6948 return true; 6949 } 6950 return false; 6951 } 6952 const char *getClobbers() const override { 6953 // FIXME: Implement! 6954 return ""; 6955 } 6956 6957 // No Sparc V7 for now, the backend doesn't support it anyway. 6958 enum CPUKind { 6959 CK_GENERIC, 6960 CK_V8, 6961 CK_SUPERSPARC, 6962 CK_SPARCLITE, 6963 CK_F934, 6964 CK_HYPERSPARC, 6965 CK_SPARCLITE86X, 6966 CK_SPARCLET, 6967 CK_TSC701, 6968 CK_V9, 6969 CK_ULTRASPARC, 6970 CK_ULTRASPARC3, 6971 CK_NIAGARA, 6972 CK_NIAGARA2, 6973 CK_NIAGARA3, 6974 CK_NIAGARA4, 6975 CK_MYRIAD2100, 6976 CK_MYRIAD2150, 6977 CK_MYRIAD2450, 6978 CK_LEON2, 6979 CK_LEON2_AT697E, 6980 CK_LEON2_AT697F, 6981 CK_LEON3, 6982 CK_LEON3_UT699, 6983 CK_LEON3_GR712RC, 6984 CK_LEON4, 6985 CK_LEON4_GR740 6986 } CPU = CK_GENERIC; 6987 6988 enum CPUGeneration { 6989 CG_V8, 6990 CG_V9, 6991 }; 6992 6993 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6994 switch (Kind) { 6995 case CK_GENERIC: 6996 case CK_V8: 6997 case CK_SUPERSPARC: 6998 case CK_SPARCLITE: 6999 case CK_F934: 7000 case CK_HYPERSPARC: 7001 case CK_SPARCLITE86X: 7002 case CK_SPARCLET: 7003 case CK_TSC701: 7004 case CK_MYRIAD2100: 7005 case CK_MYRIAD2150: 7006 case CK_MYRIAD2450: 7007 case CK_LEON2: 7008 case CK_LEON2_AT697E: 7009 case CK_LEON2_AT697F: 7010 case CK_LEON3: 7011 case CK_LEON3_UT699: 7012 case CK_LEON3_GR712RC: 7013 case CK_LEON4: 7014 case CK_LEON4_GR740: 7015 return CG_V8; 7016 case CK_V9: 7017 case CK_ULTRASPARC: 7018 case CK_ULTRASPARC3: 7019 case CK_NIAGARA: 7020 case CK_NIAGARA2: 7021 case CK_NIAGARA3: 7022 case CK_NIAGARA4: 7023 return CG_V9; 7024 } 7025 llvm_unreachable("Unexpected CPU kind"); 7026 } 7027 7028 CPUKind getCPUKind(StringRef Name) const { 7029 return llvm::StringSwitch<CPUKind>(Name) 7030 .Case("v8", CK_V8) 7031 .Case("supersparc", CK_SUPERSPARC) 7032 .Case("sparclite", CK_SPARCLITE) 7033 .Case("f934", CK_F934) 7034 .Case("hypersparc", CK_HYPERSPARC) 7035 .Case("sparclite86x", CK_SPARCLITE86X) 7036 .Case("sparclet", CK_SPARCLET) 7037 .Case("tsc701", CK_TSC701) 7038 .Case("v9", CK_V9) 7039 .Case("ultrasparc", CK_ULTRASPARC) 7040 .Case("ultrasparc3", CK_ULTRASPARC3) 7041 .Case("niagara", CK_NIAGARA) 7042 .Case("niagara2", CK_NIAGARA2) 7043 .Case("niagara3", CK_NIAGARA3) 7044 .Case("niagara4", CK_NIAGARA4) 7045 .Case("ma2100", CK_MYRIAD2100) 7046 .Case("ma2150", CK_MYRIAD2150) 7047 .Case("ma2450", CK_MYRIAD2450) 7048 // FIXME: the myriad2[.n] spellings are obsolete, 7049 // but a grace period is needed to allow updating dependent builds. 7050 .Case("myriad2", CK_MYRIAD2100) 7051 .Case("myriad2.1", CK_MYRIAD2100) 7052 .Case("myriad2.2", CK_MYRIAD2150) 7053 .Case("leon2", CK_LEON2) 7054 .Case("at697e", CK_LEON2_AT697E) 7055 .Case("at697f", CK_LEON2_AT697F) 7056 .Case("leon3", CK_LEON3) 7057 .Case("ut699", CK_LEON3_UT699) 7058 .Case("gr712rc", CK_LEON3_GR712RC) 7059 .Case("leon4", CK_LEON4) 7060 .Case("gr740", CK_LEON4_GR740) 7061 .Default(CK_GENERIC); 7062 } 7063 7064 bool setCPU(const std::string &Name) override { 7065 CPU = getCPUKind(Name); 7066 return CPU != CK_GENERIC; 7067 } 7068 }; 7069 7070 const char * const SparcTargetInfo::GCCRegNames[] = { 7071 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7072 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7073 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 7074 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 7075 }; 7076 7077 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 7078 return llvm::makeArrayRef(GCCRegNames); 7079 } 7080 7081 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 7082 { { "g0" }, "r0" }, 7083 { { "g1" }, "r1" }, 7084 { { "g2" }, "r2" }, 7085 { { "g3" }, "r3" }, 7086 { { "g4" }, "r4" }, 7087 { { "g5" }, "r5" }, 7088 { { "g6" }, "r6" }, 7089 { { "g7" }, "r7" }, 7090 { { "o0" }, "r8" }, 7091 { { "o1" }, "r9" }, 7092 { { "o2" }, "r10" }, 7093 { { "o3" }, "r11" }, 7094 { { "o4" }, "r12" }, 7095 { { "o5" }, "r13" }, 7096 { { "o6", "sp" }, "r14" }, 7097 { { "o7" }, "r15" }, 7098 { { "l0" }, "r16" }, 7099 { { "l1" }, "r17" }, 7100 { { "l2" }, "r18" }, 7101 { { "l3" }, "r19" }, 7102 { { "l4" }, "r20" }, 7103 { { "l5" }, "r21" }, 7104 { { "l6" }, "r22" }, 7105 { { "l7" }, "r23" }, 7106 { { "i0" }, "r24" }, 7107 { { "i1" }, "r25" }, 7108 { { "i2" }, "r26" }, 7109 { { "i3" }, "r27" }, 7110 { { "i4" }, "r28" }, 7111 { { "i5" }, "r29" }, 7112 { { "i6", "fp" }, "r30" }, 7113 { { "i7" }, "r31" }, 7114 }; 7115 7116 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 7117 return llvm::makeArrayRef(GCCRegAliases); 7118 } 7119 7120 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 7121 class SparcV8TargetInfo : public SparcTargetInfo { 7122 public: 7123 SparcV8TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7124 : SparcTargetInfo(Triple, Opts) { 7125 resetDataLayout("E-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7126 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 7127 switch (getTriple().getOS()) { 7128 default: 7129 SizeType = UnsignedInt; 7130 IntPtrType = SignedInt; 7131 PtrDiffType = SignedInt; 7132 break; 7133 case llvm::Triple::NetBSD: 7134 case llvm::Triple::OpenBSD: 7135 SizeType = UnsignedLong; 7136 IntPtrType = SignedLong; 7137 PtrDiffType = SignedLong; 7138 break; 7139 } 7140 // Up to 32 bits are lock-free atomic, but we're willing to do atomic ops 7141 // on up to 64 bits. 7142 MaxAtomicPromoteWidth = 64; 7143 MaxAtomicInlineWidth = 32; 7144 } 7145 7146 void getTargetDefines(const LangOptions &Opts, 7147 MacroBuilder &Builder) const override { 7148 SparcTargetInfo::getTargetDefines(Opts, Builder); 7149 switch (getCPUGeneration(CPU)) { 7150 case CG_V8: 7151 Builder.defineMacro("__sparcv8"); 7152 if (getTriple().getOS() != llvm::Triple::Solaris) 7153 Builder.defineMacro("__sparcv8__"); 7154 break; 7155 case CG_V9: 7156 Builder.defineMacro("__sparcv9"); 7157 if (getTriple().getOS() != llvm::Triple::Solaris) { 7158 Builder.defineMacro("__sparcv9__"); 7159 Builder.defineMacro("__sparc_v9__"); 7160 } 7161 break; 7162 } 7163 if (getTriple().getVendor() == llvm::Triple::Myriad) { 7164 std::string MyriadArchValue, Myriad2Value; 7165 Builder.defineMacro("__sparc_v8__"); 7166 Builder.defineMacro("__leon__"); 7167 switch (CPU) { 7168 case CK_MYRIAD2150: 7169 MyriadArchValue = "__ma2150"; 7170 Myriad2Value = "2"; 7171 break; 7172 case CK_MYRIAD2450: 7173 MyriadArchValue = "__ma2450"; 7174 Myriad2Value = "2"; 7175 break; 7176 default: 7177 MyriadArchValue = "__ma2100"; 7178 Myriad2Value = "1"; 7179 break; 7180 } 7181 Builder.defineMacro(MyriadArchValue, "1"); 7182 Builder.defineMacro(MyriadArchValue+"__", "1"); 7183 Builder.defineMacro("__myriad2__", Myriad2Value); 7184 Builder.defineMacro("__myriad2", Myriad2Value); 7185 } 7186 } 7187 7188 bool hasSjLjLowering() const override { 7189 return true; 7190 } 7191 }; 7192 7193 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 7194 class SparcV8elTargetInfo : public SparcV8TargetInfo { 7195 public: 7196 SparcV8elTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7197 : SparcV8TargetInfo(Triple, Opts) { 7198 resetDataLayout("e-m:e-p:32:32-i64:64-f128:64-n32-S64"); 7199 } 7200 }; 7201 7202 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 7203 class SparcV9TargetInfo : public SparcTargetInfo { 7204 public: 7205 SparcV9TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7206 : SparcTargetInfo(Triple, Opts) { 7207 // FIXME: Support Sparc quad-precision long double? 7208 resetDataLayout("E-m:e-i64:64-n32:64-S128"); 7209 // This is an LP64 platform. 7210 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7211 7212 // OpenBSD uses long long for int64_t and intmax_t. 7213 if (getTriple().getOS() == llvm::Triple::OpenBSD) 7214 IntMaxType = SignedLongLong; 7215 else 7216 IntMaxType = SignedLong; 7217 Int64Type = IntMaxType; 7218 7219 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 7220 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 7221 LongDoubleWidth = 128; 7222 LongDoubleAlign = 128; 7223 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7224 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7225 } 7226 7227 void getTargetDefines(const LangOptions &Opts, 7228 MacroBuilder &Builder) const override { 7229 SparcTargetInfo::getTargetDefines(Opts, Builder); 7230 Builder.defineMacro("__sparcv9"); 7231 Builder.defineMacro("__arch64__"); 7232 // Solaris doesn't need these variants, but the BSDs do. 7233 if (getTriple().getOS() != llvm::Triple::Solaris) { 7234 Builder.defineMacro("__sparc64__"); 7235 Builder.defineMacro("__sparc_v9__"); 7236 Builder.defineMacro("__sparcv9__"); 7237 } 7238 } 7239 7240 bool setCPU(const std::string &Name) override { 7241 if (!SparcTargetInfo::setCPU(Name)) 7242 return false; 7243 return getCPUGeneration(CPU) == CG_V9; 7244 } 7245 }; 7246 7247 class SystemZTargetInfo : public TargetInfo { 7248 static const Builtin::Info BuiltinInfo[]; 7249 static const char *const GCCRegNames[]; 7250 std::string CPU; 7251 bool HasTransactionalExecution; 7252 bool HasVector; 7253 7254 public: 7255 SystemZTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7256 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 7257 HasVector(false) { 7258 IntMaxType = SignedLong; 7259 Int64Type = SignedLong; 7260 TLSSupported = true; 7261 IntWidth = IntAlign = 32; 7262 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 7263 PointerWidth = PointerAlign = 64; 7264 LongDoubleWidth = 128; 7265 LongDoubleAlign = 64; 7266 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7267 DefaultAlignForAttributeAligned = 64; 7268 MinGlobalAlign = 16; 7269 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"); 7270 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7271 } 7272 void getTargetDefines(const LangOptions &Opts, 7273 MacroBuilder &Builder) const override { 7274 Builder.defineMacro("__s390__"); 7275 Builder.defineMacro("__s390x__"); 7276 Builder.defineMacro("__zarch__"); 7277 Builder.defineMacro("__LONG_DOUBLE_128__"); 7278 7279 const std::string ISARev = llvm::StringSwitch<std::string>(CPU) 7280 .Cases("arch8", "z10", "8") 7281 .Cases("arch9", "z196", "9") 7282 .Cases("arch10", "zEC12", "10") 7283 .Cases("arch11", "z13", "11") 7284 .Default(""); 7285 if (!ISARev.empty()) 7286 Builder.defineMacro("__ARCH__", ISARev); 7287 7288 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7289 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7290 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7291 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7292 7293 if (HasTransactionalExecution) 7294 Builder.defineMacro("__HTM__"); 7295 if (HasVector) 7296 Builder.defineMacro("__VX__"); 7297 if (Opts.ZVector) 7298 Builder.defineMacro("__VEC__", "10301"); 7299 } 7300 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7301 return llvm::makeArrayRef(BuiltinInfo, 7302 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 7303 } 7304 7305 ArrayRef<const char *> getGCCRegNames() const override; 7306 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7307 // No aliases. 7308 return None; 7309 } 7310 bool validateAsmConstraint(const char *&Name, 7311 TargetInfo::ConstraintInfo &info) const override; 7312 const char *getClobbers() const override { 7313 // FIXME: Is this really right? 7314 return ""; 7315 } 7316 BuiltinVaListKind getBuiltinVaListKind() const override { 7317 return TargetInfo::SystemZBuiltinVaList; 7318 } 7319 bool setCPU(const std::string &Name) override { 7320 CPU = Name; 7321 bool CPUKnown = llvm::StringSwitch<bool>(Name) 7322 .Case("z10", true) 7323 .Case("arch8", true) 7324 .Case("z196", true) 7325 .Case("arch9", true) 7326 .Case("zEC12", true) 7327 .Case("arch10", true) 7328 .Case("z13", true) 7329 .Case("arch11", true) 7330 .Default(false); 7331 7332 return CPUKnown; 7333 } 7334 bool 7335 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7336 StringRef CPU, 7337 const std::vector<std::string> &FeaturesVec) const override { 7338 if (CPU == "zEC12" || CPU == "arch10") 7339 Features["transactional-execution"] = true; 7340 if (CPU == "z13" || CPU == "arch11") { 7341 Features["transactional-execution"] = true; 7342 Features["vector"] = true; 7343 } 7344 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7345 } 7346 7347 bool handleTargetFeatures(std::vector<std::string> &Features, 7348 DiagnosticsEngine &Diags) override { 7349 HasTransactionalExecution = false; 7350 for (const auto &Feature : Features) { 7351 if (Feature == "+transactional-execution") 7352 HasTransactionalExecution = true; 7353 else if (Feature == "+vector") 7354 HasVector = true; 7355 } 7356 // If we use the vector ABI, vector types are 64-bit aligned. 7357 if (HasVector) { 7358 MaxVectorAlign = 64; 7359 resetDataLayout("E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 7360 "-v128:64-a:8:16-n32:64"); 7361 } 7362 return true; 7363 } 7364 7365 bool hasFeature(StringRef Feature) const override { 7366 return llvm::StringSwitch<bool>(Feature) 7367 .Case("systemz", true) 7368 .Case("htm", HasTransactionalExecution) 7369 .Case("vx", HasVector) 7370 .Default(false); 7371 } 7372 7373 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7374 switch (CC) { 7375 case CC_C: 7376 case CC_Swift: 7377 return CCCR_OK; 7378 default: 7379 return CCCR_Warning; 7380 } 7381 } 7382 7383 StringRef getABI() const override { 7384 if (HasVector) 7385 return "vector"; 7386 return ""; 7387 } 7388 7389 bool useFloat128ManglingForLongDouble() const override { 7390 return true; 7391 } 7392 }; 7393 7394 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 7395 #define BUILTIN(ID, TYPE, ATTRS) \ 7396 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7397 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 7398 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 7399 #include "clang/Basic/BuiltinsSystemZ.def" 7400 }; 7401 7402 const char *const SystemZTargetInfo::GCCRegNames[] = { 7403 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7404 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 7405 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 7406 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 7407 }; 7408 7409 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 7410 return llvm::makeArrayRef(GCCRegNames); 7411 } 7412 7413 bool SystemZTargetInfo:: 7414 validateAsmConstraint(const char *&Name, 7415 TargetInfo::ConstraintInfo &Info) const { 7416 switch (*Name) { 7417 default: 7418 return false; 7419 7420 case 'a': // Address register 7421 case 'd': // Data register (equivalent to 'r') 7422 case 'f': // Floating-point register 7423 Info.setAllowsRegister(); 7424 return true; 7425 7426 case 'I': // Unsigned 8-bit constant 7427 case 'J': // Unsigned 12-bit constant 7428 case 'K': // Signed 16-bit constant 7429 case 'L': // Signed 20-bit displacement (on all targets we support) 7430 case 'M': // 0x7fffffff 7431 return true; 7432 7433 case 'Q': // Memory with base and unsigned 12-bit displacement 7434 case 'R': // Likewise, plus an index 7435 case 'S': // Memory with base and signed 20-bit displacement 7436 case 'T': // Likewise, plus an index 7437 Info.setAllowsMemory(); 7438 return true; 7439 } 7440 } 7441 7442 class MSP430TargetInfo : public TargetInfo { 7443 static const char *const GCCRegNames[]; 7444 7445 public: 7446 MSP430TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7447 : TargetInfo(Triple) { 7448 TLSSupported = false; 7449 IntWidth = 16; 7450 IntAlign = 16; 7451 LongWidth = 32; 7452 LongLongWidth = 64; 7453 LongAlign = LongLongAlign = 16; 7454 PointerWidth = 16; 7455 PointerAlign = 16; 7456 SuitableAlign = 16; 7457 SizeType = UnsignedInt; 7458 IntMaxType = SignedLongLong; 7459 IntPtrType = SignedInt; 7460 PtrDiffType = SignedInt; 7461 SigAtomicType = SignedLong; 7462 resetDataLayout("e-m:e-p:16:16-i32:16:32-a:16-n8:16"); 7463 } 7464 void getTargetDefines(const LangOptions &Opts, 7465 MacroBuilder &Builder) const override { 7466 Builder.defineMacro("MSP430"); 7467 Builder.defineMacro("__MSP430__"); 7468 // FIXME: defines for different 'flavours' of MCU 7469 } 7470 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7471 // FIXME: Implement. 7472 return None; 7473 } 7474 bool hasFeature(StringRef Feature) const override { 7475 return Feature == "msp430"; 7476 } 7477 ArrayRef<const char *> getGCCRegNames() const override; 7478 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7479 // No aliases. 7480 return None; 7481 } 7482 bool validateAsmConstraint(const char *&Name, 7483 TargetInfo::ConstraintInfo &info) const override { 7484 // FIXME: implement 7485 switch (*Name) { 7486 case 'K': // the constant 1 7487 case 'L': // constant -1^20 .. 1^19 7488 case 'M': // constant 1-4: 7489 return true; 7490 } 7491 // No target constraints for now. 7492 return false; 7493 } 7494 const char *getClobbers() const override { 7495 // FIXME: Is this really right? 7496 return ""; 7497 } 7498 BuiltinVaListKind getBuiltinVaListKind() const override { 7499 // FIXME: implement 7500 return TargetInfo::CharPtrBuiltinVaList; 7501 } 7502 }; 7503 7504 const char *const MSP430TargetInfo::GCCRegNames[] = { 7505 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7506 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 7507 7508 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 7509 return llvm::makeArrayRef(GCCRegNames); 7510 } 7511 7512 // LLVM and Clang cannot be used directly to output native binaries for 7513 // target, but is used to compile C code to llvm bitcode with correct 7514 // type and alignment information. 7515 // 7516 // TCE uses the llvm bitcode as input and uses it for generating customized 7517 // target processor and program binary. TCE co-design environment is 7518 // publicly available in http://tce.cs.tut.fi 7519 7520 static const unsigned TCEOpenCLAddrSpaceMap[] = { 7521 0, // Default 7522 3, // opencl_global 7523 4, // opencl_local 7524 5, // opencl_constant 7525 // FIXME: generic has to be added to the target 7526 0, // opencl_generic 7527 0, // cuda_device 7528 0, // cuda_constant 7529 0 // cuda_shared 7530 }; 7531 7532 class TCETargetInfo : public TargetInfo { 7533 public: 7534 TCETargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7535 : TargetInfo(Triple) { 7536 TLSSupported = false; 7537 IntWidth = 32; 7538 LongWidth = LongLongWidth = 32; 7539 PointerWidth = 32; 7540 IntAlign = 32; 7541 LongAlign = LongLongAlign = 32; 7542 PointerAlign = 32; 7543 SuitableAlign = 32; 7544 SizeType = UnsignedInt; 7545 IntMaxType = SignedLong; 7546 IntPtrType = SignedInt; 7547 PtrDiffType = SignedInt; 7548 FloatWidth = 32; 7549 FloatAlign = 32; 7550 DoubleWidth = 32; 7551 DoubleAlign = 32; 7552 LongDoubleWidth = 32; 7553 LongDoubleAlign = 32; 7554 FloatFormat = &llvm::APFloat::IEEEsingle(); 7555 DoubleFormat = &llvm::APFloat::IEEEsingle(); 7556 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 7557 resetDataLayout("E-p:32:32:32-i1:8:8-i8:8:32-" 7558 "i16:16:32-i32:32:32-i64:32:32-" 7559 "f32:32:32-f64:32:32-v64:32:32-" 7560 "v128:32:32-v256:32:32-v512:32:32-" 7561 "v1024:32:32-a0:0:32-n32"); 7562 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 7563 UseAddrSpaceMapMangling = true; 7564 } 7565 7566 void getTargetDefines(const LangOptions &Opts, 7567 MacroBuilder &Builder) const override { 7568 DefineStd(Builder, "tce", Opts); 7569 Builder.defineMacro("__TCE__"); 7570 Builder.defineMacro("__TCE_V1__"); 7571 } 7572 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 7573 7574 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7575 const char *getClobbers() const override { return ""; } 7576 BuiltinVaListKind getBuiltinVaListKind() const override { 7577 return TargetInfo::VoidPtrBuiltinVaList; 7578 } 7579 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7580 bool validateAsmConstraint(const char *&Name, 7581 TargetInfo::ConstraintInfo &info) const override { 7582 return true; 7583 } 7584 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7585 return None; 7586 } 7587 }; 7588 7589 class TCELETargetInfo : public TCETargetInfo { 7590 public: 7591 TCELETargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 7592 : TCETargetInfo(Triple, Opts) { 7593 BigEndian = false; 7594 7595 resetDataLayout("e-p:32:32:32-i1:8:8-i8:8:32-" 7596 "i16:16:32-i32:32:32-i64:32:32-" 7597 "f32:32:32-f64:32:32-v64:32:32-" 7598 "v128:32:32-v256:32:32-v512:32:32-" 7599 "v1024:32:32-a0:0:32-n32"); 7600 7601 } 7602 7603 virtual void getTargetDefines(const LangOptions &Opts, 7604 MacroBuilder &Builder) const { 7605 DefineStd(Builder, "tcele", Opts); 7606 Builder.defineMacro("__TCE__"); 7607 Builder.defineMacro("__TCE_V1__"); 7608 Builder.defineMacro("__TCELE__"); 7609 Builder.defineMacro("__TCELE_V1__"); 7610 } 7611 7612 }; 7613 7614 class BPFTargetInfo : public TargetInfo { 7615 public: 7616 BPFTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7617 : TargetInfo(Triple) { 7618 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7619 SizeType = UnsignedLong; 7620 PtrDiffType = SignedLong; 7621 IntPtrType = SignedLong; 7622 IntMaxType = SignedLong; 7623 Int64Type = SignedLong; 7624 RegParmMax = 5; 7625 if (Triple.getArch() == llvm::Triple::bpfeb) { 7626 resetDataLayout("E-m:e-p:64:64-i64:64-n32:64-S128"); 7627 } else { 7628 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 7629 } 7630 MaxAtomicPromoteWidth = 64; 7631 MaxAtomicInlineWidth = 64; 7632 TLSSupported = false; 7633 } 7634 void getTargetDefines(const LangOptions &Opts, 7635 MacroBuilder &Builder) const override { 7636 DefineStd(Builder, "bpf", Opts); 7637 Builder.defineMacro("__BPF__"); 7638 } 7639 bool hasFeature(StringRef Feature) const override { 7640 return Feature == "bpf"; 7641 } 7642 7643 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7644 const char *getClobbers() const override { 7645 return ""; 7646 } 7647 BuiltinVaListKind getBuiltinVaListKind() const override { 7648 return TargetInfo::VoidPtrBuiltinVaList; 7649 } 7650 ArrayRef<const char *> getGCCRegNames() const override { 7651 return None; 7652 } 7653 bool validateAsmConstraint(const char *&Name, 7654 TargetInfo::ConstraintInfo &info) const override { 7655 return true; 7656 } 7657 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7658 return None; 7659 } 7660 }; 7661 7662 class MipsTargetInfo : public TargetInfo { 7663 void setDataLayout() { 7664 StringRef Layout; 7665 7666 if (ABI == "o32") 7667 Layout = "m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7668 else if (ABI == "n32") 7669 Layout = "m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7670 else if (ABI == "n64") 7671 Layout = "m:e-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7672 else 7673 llvm_unreachable("Invalid ABI"); 7674 7675 if (BigEndian) 7676 resetDataLayout(("E-" + Layout).str()); 7677 else 7678 resetDataLayout(("e-" + Layout).str()); 7679 } 7680 7681 7682 static const Builtin::Info BuiltinInfo[]; 7683 std::string CPU; 7684 bool IsMips16; 7685 bool IsMicromips; 7686 bool IsNan2008; 7687 bool IsSingleFloat; 7688 bool IsNoABICalls; 7689 bool CanUseBSDABICalls; 7690 enum MipsFloatABI { 7691 HardFloat, SoftFloat 7692 } FloatABI; 7693 enum DspRevEnum { 7694 NoDSP, DSP1, DSP2 7695 } DspRev; 7696 bool HasMSA; 7697 7698 protected: 7699 bool HasFP64; 7700 std::string ABI; 7701 7702 public: 7703 MipsTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 7704 : TargetInfo(Triple), IsMips16(false), IsMicromips(false), 7705 IsNan2008(false), IsSingleFloat(false), IsNoABICalls(false), 7706 CanUseBSDABICalls(false), FloatABI(HardFloat), DspRev(NoDSP), 7707 HasMSA(false), HasFP64(false) { 7708 TheCXXABI.set(TargetCXXABI::GenericMIPS); 7709 7710 setABI((getTriple().getArch() == llvm::Triple::mips || 7711 getTriple().getArch() == llvm::Triple::mipsel) 7712 ? "o32" 7713 : "n64"); 7714 7715 CPU = ABI == "o32" ? "mips32r2" : "mips64r2"; 7716 7717 CanUseBSDABICalls = Triple.getOS() == llvm::Triple::FreeBSD || 7718 Triple.getOS() == llvm::Triple::OpenBSD; 7719 } 7720 7721 bool isNaN2008Default() const { 7722 return CPU == "mips32r6" || CPU == "mips64r6"; 7723 } 7724 7725 bool isFP64Default() const { 7726 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 7727 } 7728 7729 bool isNan2008() const override { 7730 return IsNan2008; 7731 } 7732 7733 bool processorSupportsGPR64() const { 7734 return llvm::StringSwitch<bool>(CPU) 7735 .Case("mips3", true) 7736 .Case("mips4", true) 7737 .Case("mips5", true) 7738 .Case("mips64", true) 7739 .Case("mips64r2", true) 7740 .Case("mips64r3", true) 7741 .Case("mips64r5", true) 7742 .Case("mips64r6", true) 7743 .Case("octeon", true) 7744 .Default(false); 7745 return false; 7746 } 7747 7748 StringRef getABI() const override { return ABI; } 7749 bool setABI(const std::string &Name) override { 7750 if (Name == "o32") { 7751 setO32ABITypes(); 7752 ABI = Name; 7753 return true; 7754 } 7755 7756 if (Name == "n32") { 7757 setN32ABITypes(); 7758 ABI = Name; 7759 return true; 7760 } 7761 if (Name == "n64") { 7762 setN64ABITypes(); 7763 ABI = Name; 7764 return true; 7765 } 7766 return false; 7767 } 7768 7769 void setO32ABITypes() { 7770 Int64Type = SignedLongLong; 7771 IntMaxType = Int64Type; 7772 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7773 LongDoubleWidth = LongDoubleAlign = 64; 7774 LongWidth = LongAlign = 32; 7775 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7776 PointerWidth = PointerAlign = 32; 7777 PtrDiffType = SignedInt; 7778 SizeType = UnsignedInt; 7779 SuitableAlign = 64; 7780 } 7781 7782 void setN32N64ABITypes() { 7783 LongDoubleWidth = LongDoubleAlign = 128; 7784 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 7785 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7786 LongDoubleWidth = LongDoubleAlign = 64; 7787 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 7788 } 7789 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7790 SuitableAlign = 128; 7791 } 7792 7793 void setN64ABITypes() { 7794 setN32N64ABITypes(); 7795 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 7796 Int64Type = SignedLongLong; 7797 } else { 7798 Int64Type = SignedLong; 7799 } 7800 IntMaxType = Int64Type; 7801 LongWidth = LongAlign = 64; 7802 PointerWidth = PointerAlign = 64; 7803 PtrDiffType = SignedLong; 7804 SizeType = UnsignedLong; 7805 } 7806 7807 void setN32ABITypes() { 7808 setN32N64ABITypes(); 7809 Int64Type = SignedLongLong; 7810 IntMaxType = Int64Type; 7811 LongWidth = LongAlign = 32; 7812 PointerWidth = PointerAlign = 32; 7813 PtrDiffType = SignedInt; 7814 SizeType = UnsignedInt; 7815 } 7816 7817 bool setCPU(const std::string &Name) override { 7818 CPU = Name; 7819 return llvm::StringSwitch<bool>(Name) 7820 .Case("mips1", true) 7821 .Case("mips2", true) 7822 .Case("mips3", true) 7823 .Case("mips4", true) 7824 .Case("mips5", true) 7825 .Case("mips32", true) 7826 .Case("mips32r2", true) 7827 .Case("mips32r3", true) 7828 .Case("mips32r5", true) 7829 .Case("mips32r6", true) 7830 .Case("mips64", true) 7831 .Case("mips64r2", true) 7832 .Case("mips64r3", true) 7833 .Case("mips64r5", true) 7834 .Case("mips64r6", true) 7835 .Case("octeon", true) 7836 .Case("p5600", true) 7837 .Default(false); 7838 } 7839 const std::string& getCPU() const { return CPU; } 7840 bool 7841 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7842 StringRef CPU, 7843 const std::vector<std::string> &FeaturesVec) const override { 7844 if (CPU.empty()) 7845 CPU = getCPU(); 7846 if (CPU == "octeon") 7847 Features["mips64r2"] = Features["cnmips"] = true; 7848 else 7849 Features[CPU] = true; 7850 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7851 } 7852 7853 void getTargetDefines(const LangOptions &Opts, 7854 MacroBuilder &Builder) const override { 7855 if (BigEndian) { 7856 DefineStd(Builder, "MIPSEB", Opts); 7857 Builder.defineMacro("_MIPSEB"); 7858 } else { 7859 DefineStd(Builder, "MIPSEL", Opts); 7860 Builder.defineMacro("_MIPSEL"); 7861 } 7862 7863 Builder.defineMacro("__mips__"); 7864 Builder.defineMacro("_mips"); 7865 if (Opts.GNUMode) 7866 Builder.defineMacro("mips"); 7867 7868 if (ABI == "o32") { 7869 Builder.defineMacro("__mips", "32"); 7870 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 7871 } else { 7872 Builder.defineMacro("__mips", "64"); 7873 Builder.defineMacro("__mips64"); 7874 Builder.defineMacro("__mips64__"); 7875 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7876 } 7877 7878 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) 7879 .Cases("mips32", "mips64", "1") 7880 .Cases("mips32r2", "mips64r2", "2") 7881 .Cases("mips32r3", "mips64r3", "3") 7882 .Cases("mips32r5", "mips64r5", "5") 7883 .Cases("mips32r6", "mips64r6", "6") 7884 .Default(""); 7885 if (!ISARev.empty()) 7886 Builder.defineMacro("__mips_isa_rev", ISARev); 7887 7888 if (ABI == "o32") { 7889 Builder.defineMacro("__mips_o32"); 7890 Builder.defineMacro("_ABIO32", "1"); 7891 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 7892 } else if (ABI == "n32") { 7893 Builder.defineMacro("__mips_n32"); 7894 Builder.defineMacro("_ABIN32", "2"); 7895 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7896 } else if (ABI == "n64") { 7897 Builder.defineMacro("__mips_n64"); 7898 Builder.defineMacro("_ABI64", "3"); 7899 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7900 } else 7901 llvm_unreachable("Invalid ABI."); 7902 7903 if (!IsNoABICalls) { 7904 Builder.defineMacro("__mips_abicalls"); 7905 if (CanUseBSDABICalls) 7906 Builder.defineMacro("__ABICALLS__"); 7907 } 7908 7909 Builder.defineMacro("__REGISTER_PREFIX__", ""); 7910 7911 switch (FloatABI) { 7912 case HardFloat: 7913 Builder.defineMacro("__mips_hard_float", Twine(1)); 7914 break; 7915 case SoftFloat: 7916 Builder.defineMacro("__mips_soft_float", Twine(1)); 7917 break; 7918 } 7919 7920 if (IsSingleFloat) 7921 Builder.defineMacro("__mips_single_float", Twine(1)); 7922 7923 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 7924 Builder.defineMacro("_MIPS_FPSET", 7925 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 7926 7927 if (IsMips16) 7928 Builder.defineMacro("__mips16", Twine(1)); 7929 7930 if (IsMicromips) 7931 Builder.defineMacro("__mips_micromips", Twine(1)); 7932 7933 if (IsNan2008) 7934 Builder.defineMacro("__mips_nan2008", Twine(1)); 7935 7936 switch (DspRev) { 7937 default: 7938 break; 7939 case DSP1: 7940 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 7941 Builder.defineMacro("__mips_dsp", Twine(1)); 7942 break; 7943 case DSP2: 7944 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 7945 Builder.defineMacro("__mips_dspr2", Twine(1)); 7946 Builder.defineMacro("__mips_dsp", Twine(1)); 7947 break; 7948 } 7949 7950 if (HasMSA) 7951 Builder.defineMacro("__mips_msa", Twine(1)); 7952 7953 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 7954 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 7955 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 7956 7957 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 7958 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 7959 7960 // These shouldn't be defined for MIPS-I but there's no need to check 7961 // for that since MIPS-I isn't supported. 7962 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 7963 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 7964 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 7965 7966 // 32-bit MIPS processors don't have the necessary lld/scd instructions 7967 // found in 64-bit processors. In the case of O32 on a 64-bit processor, 7968 // the instructions exist but using them violates the ABI since they 7969 // require 64-bit GPRs and O32 only supports 32-bit GPRs. 7970 if (ABI == "n32" || ABI == "n64") 7971 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7972 } 7973 7974 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7975 return llvm::makeArrayRef(BuiltinInfo, 7976 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 7977 } 7978 bool hasFeature(StringRef Feature) const override { 7979 return llvm::StringSwitch<bool>(Feature) 7980 .Case("mips", true) 7981 .Case("fp64", HasFP64) 7982 .Default(false); 7983 } 7984 BuiltinVaListKind getBuiltinVaListKind() const override { 7985 return TargetInfo::VoidPtrBuiltinVaList; 7986 } 7987 ArrayRef<const char *> getGCCRegNames() const override { 7988 static const char *const GCCRegNames[] = { 7989 // CPU register names 7990 // Must match second column of GCCRegAliases 7991 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 7992 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 7993 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 7994 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 7995 // Floating point register names 7996 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 7997 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 7998 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 7999 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 8000 // Hi/lo and condition register names 8001 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 8002 "$fcc5","$fcc6","$fcc7","$ac1hi","$ac1lo","$ac2hi","$ac2lo", 8003 "$ac3hi","$ac3lo", 8004 // MSA register names 8005 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 8006 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 8007 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 8008 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 8009 // MSA control register names 8010 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 8011 "$msarequest", "$msamap", "$msaunmap" 8012 }; 8013 return llvm::makeArrayRef(GCCRegNames); 8014 } 8015 bool validateAsmConstraint(const char *&Name, 8016 TargetInfo::ConstraintInfo &Info) const override { 8017 switch (*Name) { 8018 default: 8019 return false; 8020 case 'r': // CPU registers. 8021 case 'd': // Equivalent to "r" unless generating MIPS16 code. 8022 case 'y': // Equivalent to "r", backward compatibility only. 8023 case 'f': // floating-point registers. 8024 case 'c': // $25 for indirect jumps 8025 case 'l': // lo register 8026 case 'x': // hilo register pair 8027 Info.setAllowsRegister(); 8028 return true; 8029 case 'I': // Signed 16-bit constant 8030 case 'J': // Integer 0 8031 case 'K': // Unsigned 16-bit constant 8032 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 8033 case 'M': // Constants not loadable via lui, addiu, or ori 8034 case 'N': // Constant -1 to -65535 8035 case 'O': // A signed 15-bit constant 8036 case 'P': // A constant between 1 go 65535 8037 return true; 8038 case 'R': // An address that can be used in a non-macro load or store 8039 Info.setAllowsMemory(); 8040 return true; 8041 case 'Z': 8042 if (Name[1] == 'C') { // An address usable by ll, and sc. 8043 Info.setAllowsMemory(); 8044 Name++; // Skip over 'Z'. 8045 return true; 8046 } 8047 return false; 8048 } 8049 } 8050 8051 std::string convertConstraint(const char *&Constraint) const override { 8052 std::string R; 8053 switch (*Constraint) { 8054 case 'Z': // Two-character constraint; add "^" hint for later parsing. 8055 if (Constraint[1] == 'C') { 8056 R = std::string("^") + std::string(Constraint, 2); 8057 Constraint++; 8058 return R; 8059 } 8060 break; 8061 } 8062 return TargetInfo::convertConstraint(Constraint); 8063 } 8064 8065 const char *getClobbers() const override { 8066 // In GCC, $1 is not widely used in generated code (it's used only in a few 8067 // specific situations), so there is no real need for users to add it to 8068 // the clobbers list if they want to use it in their inline assembly code. 8069 // 8070 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 8071 // code generation, so using it in inline assembly without adding it to the 8072 // clobbers list can cause conflicts between the inline assembly code and 8073 // the surrounding generated code. 8074 // 8075 // Another problem is that LLVM is allowed to choose $1 for inline assembly 8076 // operands, which will conflict with the ".set at" assembler option (which 8077 // we use only for inline assembly, in order to maintain compatibility with 8078 // GCC) and will also conflict with the user's usage of $1. 8079 // 8080 // The easiest way to avoid these conflicts and keep $1 as an allocatable 8081 // register for generated code is to automatically clobber $1 for all inline 8082 // assembly code. 8083 // 8084 // FIXME: We should automatically clobber $1 only for inline assembly code 8085 // which actually uses it. This would allow LLVM to use $1 for inline 8086 // assembly operands if the user's assembly code doesn't use it. 8087 return "~{$1}"; 8088 } 8089 8090 bool handleTargetFeatures(std::vector<std::string> &Features, 8091 DiagnosticsEngine &Diags) override { 8092 IsMips16 = false; 8093 IsMicromips = false; 8094 IsNan2008 = isNaN2008Default(); 8095 IsSingleFloat = false; 8096 FloatABI = HardFloat; 8097 DspRev = NoDSP; 8098 HasFP64 = isFP64Default(); 8099 8100 for (const auto &Feature : Features) { 8101 if (Feature == "+single-float") 8102 IsSingleFloat = true; 8103 else if (Feature == "+soft-float") 8104 FloatABI = SoftFloat; 8105 else if (Feature == "+mips16") 8106 IsMips16 = true; 8107 else if (Feature == "+micromips") 8108 IsMicromips = true; 8109 else if (Feature == "+dsp") 8110 DspRev = std::max(DspRev, DSP1); 8111 else if (Feature == "+dspr2") 8112 DspRev = std::max(DspRev, DSP2); 8113 else if (Feature == "+msa") 8114 HasMSA = true; 8115 else if (Feature == "+fp64") 8116 HasFP64 = true; 8117 else if (Feature == "-fp64") 8118 HasFP64 = false; 8119 else if (Feature == "+nan2008") 8120 IsNan2008 = true; 8121 else if (Feature == "-nan2008") 8122 IsNan2008 = false; 8123 else if (Feature == "+noabicalls") 8124 IsNoABICalls = true; 8125 } 8126 8127 setDataLayout(); 8128 8129 return true; 8130 } 8131 8132 int getEHDataRegisterNumber(unsigned RegNo) const override { 8133 if (RegNo == 0) return 4; 8134 if (RegNo == 1) return 5; 8135 return -1; 8136 } 8137 8138 bool isCLZForZeroUndef() const override { return false; } 8139 8140 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8141 static const TargetInfo::GCCRegAlias O32RegAliases[] = { 8142 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8143 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8144 {{"a3"}, "$7"}, {{"t0"}, "$8"}, {{"t1"}, "$9"}, 8145 {{"t2"}, "$10"}, {{"t3"}, "$11"}, {{"t4"}, "$12"}, 8146 {{"t5"}, "$13"}, {{"t6"}, "$14"}, {{"t7"}, "$15"}, 8147 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8148 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8149 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8150 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8151 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8152 {{"ra"}, "$31"}}; 8153 static const TargetInfo::GCCRegAlias NewABIRegAliases[] = { 8154 {{"at"}, "$1"}, {{"v0"}, "$2"}, {{"v1"}, "$3"}, 8155 {{"a0"}, "$4"}, {{"a1"}, "$5"}, {{"a2"}, "$6"}, 8156 {{"a3"}, "$7"}, {{"a4"}, "$8"}, {{"a5"}, "$9"}, 8157 {{"a6"}, "$10"}, {{"a7"}, "$11"}, {{"t0"}, "$12"}, 8158 {{"t1"}, "$13"}, {{"t2"}, "$14"}, {{"t3"}, "$15"}, 8159 {{"s0"}, "$16"}, {{"s1"}, "$17"}, {{"s2"}, "$18"}, 8160 {{"s3"}, "$19"}, {{"s4"}, "$20"}, {{"s5"}, "$21"}, 8161 {{"s6"}, "$22"}, {{"s7"}, "$23"}, {{"t8"}, "$24"}, 8162 {{"t9"}, "$25"}, {{"k0"}, "$26"}, {{"k1"}, "$27"}, 8163 {{"gp"}, "$28"}, {{"sp", "$sp"}, "$29"}, {{"fp", "$fp"}, "$30"}, 8164 {{"ra"}, "$31"}}; 8165 if (ABI == "o32") 8166 return llvm::makeArrayRef(O32RegAliases); 8167 return llvm::makeArrayRef(NewABIRegAliases); 8168 } 8169 8170 bool hasInt128Type() const override { 8171 return ABI == "n32" || ABI == "n64"; 8172 } 8173 8174 bool validateTarget(DiagnosticsEngine &Diags) const override { 8175 // FIXME: It's valid to use O32 on a 64-bit CPU but the backend can't handle 8176 // this yet. It's better to fail here than on the backend assertion. 8177 if (processorSupportsGPR64() && ABI == "o32") { 8178 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8179 return false; 8180 } 8181 8182 // 64-bit ABI's require 64-bit CPU's. 8183 if (!processorSupportsGPR64() && (ABI == "n32" || ABI == "n64")) { 8184 Diags.Report(diag::err_target_unsupported_abi) << ABI << CPU; 8185 return false; 8186 } 8187 8188 // FIXME: It's valid to use O32 on a mips64/mips64el triple but the backend 8189 // can't handle this yet. It's better to fail here than on the 8190 // backend assertion. 8191 if ((getTriple().getArch() == llvm::Triple::mips64 || 8192 getTriple().getArch() == llvm::Triple::mips64el) && 8193 ABI == "o32") { 8194 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8195 << ABI << getTriple().str(); 8196 return false; 8197 } 8198 8199 // FIXME: It's valid to use N32/N64 on a mips/mipsel triple but the backend 8200 // can't handle this yet. It's better to fail here than on the 8201 // backend assertion. 8202 if ((getTriple().getArch() == llvm::Triple::mips || 8203 getTriple().getArch() == llvm::Triple::mipsel) && 8204 (ABI == "n32" || ABI == "n64")) { 8205 Diags.Report(diag::err_target_unsupported_abi_for_triple) 8206 << ABI << getTriple().str(); 8207 return false; 8208 } 8209 8210 return true; 8211 } 8212 }; 8213 8214 const Builtin::Info MipsTargetInfo::BuiltinInfo[] = { 8215 #define BUILTIN(ID, TYPE, ATTRS) \ 8216 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8217 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8218 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8219 #include "clang/Basic/BuiltinsMips.def" 8220 }; 8221 8222 class PNaClTargetInfo : public TargetInfo { 8223 public: 8224 PNaClTargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8225 : TargetInfo(Triple) { 8226 this->LongAlign = 32; 8227 this->LongWidth = 32; 8228 this->PointerAlign = 32; 8229 this->PointerWidth = 32; 8230 this->IntMaxType = TargetInfo::SignedLongLong; 8231 this->Int64Type = TargetInfo::SignedLongLong; 8232 this->DoubleAlign = 64; 8233 this->LongDoubleWidth = 64; 8234 this->LongDoubleAlign = 64; 8235 this->SizeType = TargetInfo::UnsignedInt; 8236 this->PtrDiffType = TargetInfo::SignedInt; 8237 this->IntPtrType = TargetInfo::SignedInt; 8238 this->RegParmMax = 0; // Disallow regparm 8239 } 8240 8241 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 8242 Builder.defineMacro("__le32__"); 8243 Builder.defineMacro("__pnacl__"); 8244 } 8245 void getTargetDefines(const LangOptions &Opts, 8246 MacroBuilder &Builder) const override { 8247 getArchDefines(Opts, Builder); 8248 } 8249 bool hasFeature(StringRef Feature) const override { 8250 return Feature == "pnacl"; 8251 } 8252 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8253 BuiltinVaListKind getBuiltinVaListKind() const override { 8254 return TargetInfo::PNaClABIBuiltinVaList; 8255 } 8256 ArrayRef<const char *> getGCCRegNames() const override; 8257 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 8258 bool validateAsmConstraint(const char *&Name, 8259 TargetInfo::ConstraintInfo &Info) const override { 8260 return false; 8261 } 8262 8263 const char *getClobbers() const override { 8264 return ""; 8265 } 8266 }; 8267 8268 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 8269 return None; 8270 } 8271 8272 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 8273 return None; 8274 } 8275 8276 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 8277 class NaClMips32TargetInfo : public MipsTargetInfo { 8278 public: 8279 NaClMips32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8280 : MipsTargetInfo(Triple, Opts) {} 8281 8282 BuiltinVaListKind getBuiltinVaListKind() const override { 8283 return TargetInfo::PNaClABIBuiltinVaList; 8284 } 8285 }; 8286 8287 class Le64TargetInfo : public TargetInfo { 8288 static const Builtin::Info BuiltinInfo[]; 8289 8290 public: 8291 Le64TargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8292 : TargetInfo(Triple) { 8293 NoAsmVariants = true; 8294 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 8295 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8296 resetDataLayout("e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"); 8297 } 8298 8299 void getTargetDefines(const LangOptions &Opts, 8300 MacroBuilder &Builder) const override { 8301 DefineStd(Builder, "unix", Opts); 8302 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 8303 Builder.defineMacro("__ELF__"); 8304 } 8305 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8306 return llvm::makeArrayRef(BuiltinInfo, 8307 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 8308 } 8309 BuiltinVaListKind getBuiltinVaListKind() const override { 8310 return TargetInfo::PNaClABIBuiltinVaList; 8311 } 8312 const char *getClobbers() const override { return ""; } 8313 ArrayRef<const char *> getGCCRegNames() const override { 8314 return None; 8315 } 8316 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8317 return None; 8318 } 8319 bool validateAsmConstraint(const char *&Name, 8320 TargetInfo::ConstraintInfo &Info) const override { 8321 return false; 8322 } 8323 8324 bool hasProtectedVisibility() const override { return false; } 8325 }; 8326 8327 class WebAssemblyTargetInfo : public TargetInfo { 8328 static const Builtin::Info BuiltinInfo[]; 8329 8330 enum SIMDEnum { 8331 NoSIMD, 8332 SIMD128, 8333 } SIMDLevel; 8334 8335 public: 8336 explicit WebAssemblyTargetInfo(const llvm::Triple &T, const TargetOptions &) 8337 : TargetInfo(T), SIMDLevel(NoSIMD) { 8338 NoAsmVariants = true; 8339 SuitableAlign = 128; 8340 LargeArrayMinWidth = 128; 8341 LargeArrayAlign = 128; 8342 SimdDefaultAlign = 128; 8343 SigAtomicType = SignedLong; 8344 LongDoubleWidth = LongDoubleAlign = 128; 8345 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8346 SizeType = UnsignedInt; 8347 PtrDiffType = SignedInt; 8348 IntPtrType = SignedInt; 8349 } 8350 8351 protected: 8352 void getTargetDefines(const LangOptions &Opts, 8353 MacroBuilder &Builder) const override { 8354 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 8355 if (SIMDLevel >= SIMD128) 8356 Builder.defineMacro("__wasm_simd128__"); 8357 } 8358 8359 private: 8360 bool 8361 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 8362 StringRef CPU, 8363 const std::vector<std::string> &FeaturesVec) const override { 8364 if (CPU == "bleeding-edge") 8365 Features["simd128"] = true; 8366 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 8367 } 8368 bool hasFeature(StringRef Feature) const final { 8369 return llvm::StringSwitch<bool>(Feature) 8370 .Case("simd128", SIMDLevel >= SIMD128) 8371 .Default(false); 8372 } 8373 bool handleTargetFeatures(std::vector<std::string> &Features, 8374 DiagnosticsEngine &Diags) final { 8375 for (const auto &Feature : Features) { 8376 if (Feature == "+simd128") { 8377 SIMDLevel = std::max(SIMDLevel, SIMD128); 8378 continue; 8379 } 8380 if (Feature == "-simd128") { 8381 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 8382 continue; 8383 } 8384 8385 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 8386 << "-target-feature"; 8387 return false; 8388 } 8389 return true; 8390 } 8391 bool setCPU(const std::string &Name) final { 8392 return llvm::StringSwitch<bool>(Name) 8393 .Case("mvp", true) 8394 .Case("bleeding-edge", true) 8395 .Case("generic", true) 8396 .Default(false); 8397 } 8398 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 8399 return llvm::makeArrayRef(BuiltinInfo, 8400 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 8401 } 8402 BuiltinVaListKind getBuiltinVaListKind() const final { 8403 return VoidPtrBuiltinVaList; 8404 } 8405 ArrayRef<const char *> getGCCRegNames() const final { 8406 return None; 8407 } 8408 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 8409 return None; 8410 } 8411 bool 8412 validateAsmConstraint(const char *&Name, 8413 TargetInfo::ConstraintInfo &Info) const final { 8414 return false; 8415 } 8416 const char *getClobbers() const final { return ""; } 8417 bool isCLZForZeroUndef() const final { return false; } 8418 bool hasInt128Type() const final { return true; } 8419 IntType getIntTypeByWidth(unsigned BitWidth, 8420 bool IsSigned) const final { 8421 // WebAssembly prefers long long for explicitly 64-bit integers. 8422 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8423 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 8424 } 8425 IntType getLeastIntTypeByWidth(unsigned BitWidth, 8426 bool IsSigned) const final { 8427 // WebAssembly uses long long for int_least64_t and int_fast64_t. 8428 return BitWidth == 64 8429 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 8430 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 8431 } 8432 }; 8433 8434 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 8435 #define BUILTIN(ID, TYPE, ATTRS) \ 8436 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8437 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8438 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8439 #include "clang/Basic/BuiltinsWebAssembly.def" 8440 }; 8441 8442 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 8443 public: 8444 explicit WebAssembly32TargetInfo(const llvm::Triple &T, 8445 const TargetOptions &Opts) 8446 : WebAssemblyTargetInfo(T, Opts) { 8447 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 8448 resetDataLayout("e-m:e-p:32:32-i64:64-n32:64-S128"); 8449 } 8450 8451 protected: 8452 void getTargetDefines(const LangOptions &Opts, 8453 MacroBuilder &Builder) const override { 8454 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8455 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 8456 } 8457 }; 8458 8459 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 8460 public: 8461 explicit WebAssembly64TargetInfo(const llvm::Triple &T, 8462 const TargetOptions &Opts) 8463 : WebAssemblyTargetInfo(T, Opts) { 8464 LongAlign = LongWidth = 64; 8465 PointerAlign = PointerWidth = 64; 8466 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 8467 SizeType = UnsignedLong; 8468 PtrDiffType = SignedLong; 8469 IntPtrType = SignedLong; 8470 resetDataLayout("e-m:e-p:64:64-i64:64-n32:64-S128"); 8471 } 8472 8473 protected: 8474 void getTargetDefines(const LangOptions &Opts, 8475 MacroBuilder &Builder) const override { 8476 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 8477 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 8478 } 8479 }; 8480 8481 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 8482 #define BUILTIN(ID, TYPE, ATTRS) \ 8483 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8484 #include "clang/Basic/BuiltinsLe64.def" 8485 }; 8486 8487 static const unsigned SPIRAddrSpaceMap[] = { 8488 0, // Default 8489 1, // opencl_global 8490 3, // opencl_local 8491 2, // opencl_constant 8492 4, // opencl_generic 8493 0, // cuda_device 8494 0, // cuda_constant 8495 0 // cuda_shared 8496 }; 8497 class SPIRTargetInfo : public TargetInfo { 8498 public: 8499 SPIRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8500 : TargetInfo(Triple) { 8501 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 8502 "SPIR target must use unknown OS"); 8503 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 8504 "SPIR target must use unknown environment type"); 8505 TLSSupported = false; 8506 LongWidth = LongAlign = 64; 8507 AddrSpaceMap = &SPIRAddrSpaceMap; 8508 UseAddrSpaceMapMangling = true; 8509 // Define available target features 8510 // These must be defined in sorted order! 8511 NoAsmVariants = true; 8512 } 8513 void getTargetDefines(const LangOptions &Opts, 8514 MacroBuilder &Builder) const override { 8515 DefineStd(Builder, "SPIR", Opts); 8516 } 8517 bool hasFeature(StringRef Feature) const override { 8518 return Feature == "spir"; 8519 } 8520 8521 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 8522 const char *getClobbers() const override { return ""; } 8523 ArrayRef<const char *> getGCCRegNames() const override { return None; } 8524 bool validateAsmConstraint(const char *&Name, 8525 TargetInfo::ConstraintInfo &info) const override { 8526 return true; 8527 } 8528 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8529 return None; 8530 } 8531 BuiltinVaListKind getBuiltinVaListKind() const override { 8532 return TargetInfo::VoidPtrBuiltinVaList; 8533 } 8534 8535 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 8536 return (CC == CC_SpirFunction || CC == CC_OpenCLKernel) ? CCCR_OK 8537 : CCCR_Warning; 8538 } 8539 8540 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 8541 return CC_SpirFunction; 8542 } 8543 8544 void setSupportedOpenCLOpts() override { 8545 // Assume all OpenCL extensions and optional core features are supported 8546 // for SPIR since it is a generic target. 8547 getSupportedOpenCLOpts().supportAll(); 8548 } 8549 }; 8550 8551 class SPIR32TargetInfo : public SPIRTargetInfo { 8552 public: 8553 SPIR32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8554 : SPIRTargetInfo(Triple, Opts) { 8555 PointerWidth = PointerAlign = 32; 8556 SizeType = TargetInfo::UnsignedInt; 8557 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 8558 resetDataLayout("e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 8559 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8560 } 8561 void getTargetDefines(const LangOptions &Opts, 8562 MacroBuilder &Builder) const override { 8563 DefineStd(Builder, "SPIR32", Opts); 8564 } 8565 }; 8566 8567 class SPIR64TargetInfo : public SPIRTargetInfo { 8568 public: 8569 SPIR64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8570 : SPIRTargetInfo(Triple, Opts) { 8571 PointerWidth = PointerAlign = 64; 8572 SizeType = TargetInfo::UnsignedLong; 8573 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 8574 resetDataLayout("e-i64:64-v16:16-v24:32-v32:32-v48:64-" 8575 "v96:128-v192:256-v256:256-v512:512-v1024:1024"); 8576 } 8577 void getTargetDefines(const LangOptions &Opts, 8578 MacroBuilder &Builder) const override { 8579 DefineStd(Builder, "SPIR64", Opts); 8580 } 8581 }; 8582 8583 class XCoreTargetInfo : public TargetInfo { 8584 static const Builtin::Info BuiltinInfo[]; 8585 public: 8586 XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8587 : TargetInfo(Triple) { 8588 NoAsmVariants = true; 8589 LongLongAlign = 32; 8590 SuitableAlign = 32; 8591 DoubleAlign = LongDoubleAlign = 32; 8592 SizeType = UnsignedInt; 8593 PtrDiffType = SignedInt; 8594 IntPtrType = SignedInt; 8595 WCharType = UnsignedChar; 8596 WIntType = UnsignedInt; 8597 UseZeroLengthBitfieldAlignment = true; 8598 resetDataLayout("e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 8599 "-f64:32-a:0:32-n32"); 8600 } 8601 void getTargetDefines(const LangOptions &Opts, 8602 MacroBuilder &Builder) const override { 8603 Builder.defineMacro("__XS1B__"); 8604 } 8605 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 8606 return llvm::makeArrayRef(BuiltinInfo, 8607 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 8608 } 8609 BuiltinVaListKind getBuiltinVaListKind() const override { 8610 return TargetInfo::VoidPtrBuiltinVaList; 8611 } 8612 const char *getClobbers() const override { 8613 return ""; 8614 } 8615 ArrayRef<const char *> getGCCRegNames() const override { 8616 static const char * const GCCRegNames[] = { 8617 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 8618 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 8619 }; 8620 return llvm::makeArrayRef(GCCRegNames); 8621 } 8622 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 8623 return None; 8624 } 8625 bool validateAsmConstraint(const char *&Name, 8626 TargetInfo::ConstraintInfo &Info) const override { 8627 return false; 8628 } 8629 int getEHDataRegisterNumber(unsigned RegNo) const override { 8630 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 8631 return (RegNo < 2)? RegNo : -1; 8632 } 8633 bool allowsLargerPreferedTypeAlignment() const override { 8634 return false; 8635 } 8636 }; 8637 8638 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 8639 #define BUILTIN(ID, TYPE, ATTRS) \ 8640 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 8641 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 8642 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 8643 #include "clang/Basic/BuiltinsXCore.def" 8644 }; 8645 8646 // x86_32 Android target 8647 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 8648 public: 8649 AndroidX86_32TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8650 : LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts) { 8651 SuitableAlign = 32; 8652 LongDoubleWidth = 64; 8653 LongDoubleFormat = &llvm::APFloat::IEEEdouble(); 8654 } 8655 }; 8656 8657 // x86_64 Android target 8658 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 8659 public: 8660 AndroidX86_64TargetInfo(const llvm::Triple &Triple, const TargetOptions &Opts) 8661 : LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts) { 8662 LongDoubleFormat = &llvm::APFloat::IEEEquad(); 8663 } 8664 8665 bool useFloat128ManglingForLongDouble() const override { 8666 return true; 8667 } 8668 }; 8669 8670 // 32-bit RenderScript is armv7 with width and align of 'long' set to 8-bytes 8671 class RenderScript32TargetInfo : public ARMleTargetInfo { 8672 public: 8673 RenderScript32TargetInfo(const llvm::Triple &Triple, 8674 const TargetOptions &Opts) 8675 : ARMleTargetInfo(llvm::Triple("armv7", Triple.getVendorName(), 8676 Triple.getOSName(), 8677 Triple.getEnvironmentName()), 8678 Opts) { 8679 IsRenderScriptTarget = true; 8680 LongWidth = LongAlign = 64; 8681 } 8682 void getTargetDefines(const LangOptions &Opts, 8683 MacroBuilder &Builder) const override { 8684 Builder.defineMacro("__RENDERSCRIPT__"); 8685 ARMleTargetInfo::getTargetDefines(Opts, Builder); 8686 } 8687 }; 8688 8689 // 64-bit RenderScript is aarch64 8690 class RenderScript64TargetInfo : public AArch64leTargetInfo { 8691 public: 8692 RenderScript64TargetInfo(const llvm::Triple &Triple, 8693 const TargetOptions &Opts) 8694 : AArch64leTargetInfo(llvm::Triple("aarch64", Triple.getVendorName(), 8695 Triple.getOSName(), 8696 Triple.getEnvironmentName()), 8697 Opts) { 8698 IsRenderScriptTarget = true; 8699 } 8700 8701 void getTargetDefines(const LangOptions &Opts, 8702 MacroBuilder &Builder) const override { 8703 Builder.defineMacro("__RENDERSCRIPT__"); 8704 AArch64leTargetInfo::getTargetDefines(Opts, Builder); 8705 } 8706 }; 8707 8708 /// Information about a specific microcontroller. 8709 struct MCUInfo { 8710 const char *Name; 8711 const char *DefineName; 8712 }; 8713 8714 // This list should be kept up-to-date with AVRDevices.td in LLVM. 8715 static ArrayRef<MCUInfo> AVRMcus = { 8716 { "at90s1200", "__AVR_AT90S1200__" }, 8717 { "attiny11", "__AVR_ATtiny11__" }, 8718 { "attiny12", "__AVR_ATtiny12__" }, 8719 { "attiny15", "__AVR_ATtiny15__" }, 8720 { "attiny28", "__AVR_ATtiny28__" }, 8721 { "at90s2313", "__AVR_AT90S2313__" }, 8722 { "at90s2323", "__AVR_AT90S2323__" }, 8723 { "at90s2333", "__AVR_AT90S2333__" }, 8724 { "at90s2343", "__AVR_AT90S2343__" }, 8725 { "attiny22", "__AVR_ATtiny22__" }, 8726 { "attiny26", "__AVR_ATtiny26__" }, 8727 { "at86rf401", "__AVR_AT86RF401__" }, 8728 { "at90s4414", "__AVR_AT90S4414__" }, 8729 { "at90s4433", "__AVR_AT90S4433__" }, 8730 { "at90s4434", "__AVR_AT90S4434__" }, 8731 { "at90s8515", "__AVR_AT90S8515__" }, 8732 { "at90c8534", "__AVR_AT90c8534__" }, 8733 { "at90s8535", "__AVR_AT90S8535__" }, 8734 { "ata5272", "__AVR_ATA5272__" }, 8735 { "attiny13", "__AVR_ATtiny13__" }, 8736 { "attiny13a", "__AVR_ATtiny13A__" }, 8737 { "attiny2313", "__AVR_ATtiny2313__" }, 8738 { "attiny2313a", "__AVR_ATtiny2313A__" }, 8739 { "attiny24", "__AVR_ATtiny24__" }, 8740 { "attiny24a", "__AVR_ATtiny24A__" }, 8741 { "attiny4313", "__AVR_ATtiny4313__" }, 8742 { "attiny44", "__AVR_ATtiny44__" }, 8743 { "attiny44a", "__AVR_ATtiny44A__" }, 8744 { "attiny84", "__AVR_ATtiny84__" }, 8745 { "attiny84a", "__AVR_ATtiny84A__" }, 8746 { "attiny25", "__AVR_ATtiny25__" }, 8747 { "attiny45", "__AVR_ATtiny45__" }, 8748 { "attiny85", "__AVR_ATtiny85__" }, 8749 { "attiny261", "__AVR_ATtiny261__" }, 8750 { "attiny261a", "__AVR_ATtiny261A__" }, 8751 { "attiny461", "__AVR_ATtiny461__" }, 8752 { "attiny461a", "__AVR_ATtiny461A__" }, 8753 { "attiny861", "__AVR_ATtiny861__" }, 8754 { "attiny861a", "__AVR_ATtiny861A__" }, 8755 { "attiny87", "__AVR_ATtiny87__" }, 8756 { "attiny43u", "__AVR_ATtiny43U__" }, 8757 { "attiny48", "__AVR_ATtiny48__" }, 8758 { "attiny88", "__AVR_ATtiny88__" }, 8759 { "attiny828", "__AVR_ATtiny828__" }, 8760 { "at43usb355", "__AVR_AT43USB355__" }, 8761 { "at76c711", "__AVR_AT76C711__" }, 8762 { "atmega103", "__AVR_ATmega103__" }, 8763 { "at43usb320", "__AVR_AT43USB320__" }, 8764 { "attiny167", "__AVR_ATtiny167__" }, 8765 { "at90usb82", "__AVR_AT90USB82__" }, 8766 { "at90usb162", "__AVR_AT90USB162__" }, 8767 { "ata5505", "__AVR_ATA5505__" }, 8768 { "atmega8u2", "__AVR_ATmega8U2__" }, 8769 { "atmega16u2", "__AVR_ATmega16U2__" }, 8770 { "atmega32u2", "__AVR_ATmega32U2__" }, 8771 { "attiny1634", "__AVR_ATtiny1634__" }, 8772 { "atmega8", "__AVR_ATmega8__" }, 8773 { "ata6289", "__AVR_ATA6289__" }, 8774 { "atmega8a", "__AVR_ATmega8A__" }, 8775 { "ata6285", "__AVR_ATA6285__" }, 8776 { "ata6286", "__AVR_ATA6286__" }, 8777 { "atmega48", "__AVR_ATmega48__" }, 8778 { "atmega48a", "__AVR_ATmega48A__" }, 8779 { "atmega48pa", "__AVR_ATmega48PA__" }, 8780 { "atmega48p", "__AVR_ATmega48P__" }, 8781 { "atmega88", "__AVR_ATmega88__" }, 8782 { "atmega88a", "__AVR_ATmega88A__" }, 8783 { "atmega88p", "__AVR_ATmega88P__" }, 8784 { "atmega88pa", "__AVR_ATmega88PA__" }, 8785 { "atmega8515", "__AVR_ATmega8515__" }, 8786 { "atmega8535", "__AVR_ATmega8535__" }, 8787 { "atmega8hva", "__AVR_ATmega8HVA__" }, 8788 { "at90pwm1", "__AVR_AT90PWM1__" }, 8789 { "at90pwm2", "__AVR_AT90PWM2__" }, 8790 { "at90pwm2b", "__AVR_AT90PWM2B__" }, 8791 { "at90pwm3", "__AVR_AT90PWM3__" }, 8792 { "at90pwm3b", "__AVR_AT90PWM3B__" }, 8793 { "at90pwm81", "__AVR_AT90PWM81__" }, 8794 { "ata5790", "__AVR_ATA5790__" }, 8795 { "ata5795", "__AVR_ATA5795__" }, 8796 { "atmega16", "__AVR_ATmega16__" }, 8797 { "atmega16a", "__AVR_ATmega16A__" }, 8798 { "atmega161", "__AVR_ATmega161__" }, 8799 { "atmega162", "__AVR_ATmega162__" }, 8800 { "atmega163", "__AVR_ATmega163__" }, 8801 { "atmega164a", "__AVR_ATmega164A__" }, 8802 { "atmega164p", "__AVR_ATmega164P__" }, 8803 { "atmega164pa", "__AVR_ATmega164PA__" }, 8804 { "atmega165", "__AVR_ATmega165__" }, 8805 { "atmega165a", "__AVR_ATmega165A__" }, 8806 { "atmega165p", "__AVR_ATmega165P__" }, 8807 { "atmega165pa", "__AVR_ATmega165PA__" }, 8808 { "atmega168", "__AVR_ATmega168__" }, 8809 { "atmega168a", "__AVR_ATmega168A__" }, 8810 { "atmega168p", "__AVR_ATmega168P__" }, 8811 { "atmega168pa", "__AVR_ATmega168PA__" }, 8812 { "atmega169", "__AVR_ATmega169__" }, 8813 { "atmega169a", "__AVR_ATmega169A__" }, 8814 { "atmega169p", "__AVR_ATmega169P__" }, 8815 { "atmega169pa", "__AVR_ATmega169PA__" }, 8816 { "atmega32", "__AVR_ATmega32__" }, 8817 { "atmega32a", "__AVR_ATmega32A__" }, 8818 { "atmega323", "__AVR_ATmega323__" }, 8819 { "atmega324a", "__AVR_ATmega324A__" }, 8820 { "atmega324p", "__AVR_ATmega324P__" }, 8821 { "atmega324pa", "__AVR_ATmega324PA__" }, 8822 { "atmega325", "__AVR_ATmega325__" }, 8823 { "atmega325a", "__AVR_ATmega325A__" }, 8824 { "atmega325p", "__AVR_ATmega325P__" }, 8825 { "atmega325pa", "__AVR_ATmega325PA__" }, 8826 { "atmega3250", "__AVR_ATmega3250__" }, 8827 { "atmega3250a", "__AVR_ATmega3250A__" }, 8828 { "atmega3250p", "__AVR_ATmega3250P__" }, 8829 { "atmega3250pa", "__AVR_ATmega3250PA__" }, 8830 { "atmega328", "__AVR_ATmega328__" }, 8831 { "atmega328p", "__AVR_ATmega328P__" }, 8832 { "atmega329", "__AVR_ATmega329__" }, 8833 { "atmega329a", "__AVR_ATmega329A__" }, 8834 { "atmega329p", "__AVR_ATmega329P__" }, 8835 { "atmega329pa", "__AVR_ATmega329PA__" }, 8836 { "atmega3290", "__AVR_ATmega3290__" }, 8837 { "atmega3290a", "__AVR_ATmega3290A__" }, 8838 { "atmega3290p", "__AVR_ATmega3290P__" }, 8839 { "atmega3290pa", "__AVR_ATmega3290PA__" }, 8840 { "atmega406", "__AVR_ATmega406__" }, 8841 { "atmega64", "__AVR_ATmega64__" }, 8842 { "atmega64a", "__AVR_ATmega64A__" }, 8843 { "atmega640", "__AVR_ATmega640__" }, 8844 { "atmega644", "__AVR_ATmega644__" }, 8845 { "atmega644a", "__AVR_ATmega644A__" }, 8846 { "atmega644p", "__AVR_ATmega644P__" }, 8847 { "atmega644pa", "__AVR_ATmega644PA__" }, 8848 { "atmega645", "__AVR_ATmega645__" }, 8849 { "atmega645a", "__AVR_ATmega645A__" }, 8850 { "atmega645p", "__AVR_ATmega645P__" }, 8851 { "atmega649", "__AVR_ATmega649__" }, 8852 { "atmega649a", "__AVR_ATmega649A__" }, 8853 { "atmega649p", "__AVR_ATmega649P__" }, 8854 { "atmega6450", "__AVR_ATmega6450__" }, 8855 { "atmega6450a", "__AVR_ATmega6450A__" }, 8856 { "atmega6450p", "__AVR_ATmega6450P__" }, 8857 { "atmega6490", "__AVR_ATmega6490__" }, 8858 { "atmega6490a", "__AVR_ATmega6490A__" }, 8859 { "atmega6490p", "__AVR_ATmega6490P__" }, 8860 { "atmega64rfr2", "__AVR_ATmega64RFR2__" }, 8861 { "atmega644rfr2", "__AVR_ATmega644RFR2__" }, 8862 { "atmega16hva", "__AVR_ATmega16HVA__" }, 8863 { "atmega16hva2", "__AVR_ATmega16HVA2__" }, 8864 { "atmega16hvb", "__AVR_ATmega16HVB__" }, 8865 { "atmega16hvbrevb", "__AVR_ATmega16HVBREVB__" }, 8866 { "atmega32hvb", "__AVR_ATmega32HVB__" }, 8867 { "atmega32hvbrevb", "__AVR_ATmega32HVBREVB__" }, 8868 { "atmega64hve", "__AVR_ATmega64HVE__" }, 8869 { "at90can32", "__AVR_AT90CAN32__" }, 8870 { "at90can64", "__AVR_AT90CAN64__" }, 8871 { "at90pwm161", "__AVR_AT90PWM161__" }, 8872 { "at90pwm216", "__AVR_AT90PWM216__" }, 8873 { "at90pwm316", "__AVR_AT90PWM316__" }, 8874 { "atmega32c1", "__AVR_ATmega32C1__" }, 8875 { "atmega64c1", "__AVR_ATmega64C1__" }, 8876 { "atmega16m1", "__AVR_ATmega16M1__" }, 8877 { "atmega32m1", "__AVR_ATmega32M1__" }, 8878 { "atmega64m1", "__AVR_ATmega64M1__" }, 8879 { "atmega16u4", "__AVR_ATmega16U4__" }, 8880 { "atmega32u4", "__AVR_ATmega32U4__" }, 8881 { "atmega32u6", "__AVR_ATmega32U6__" }, 8882 { "at90usb646", "__AVR_AT90USB646__" }, 8883 { "at90usb647", "__AVR_AT90USB647__" }, 8884 { "at90scr100", "__AVR_AT90SCR100__" }, 8885 { "at94k", "__AVR_AT94K__" }, 8886 { "m3000", "__AVR_AT000__" }, 8887 { "atmega128", "__AVR_ATmega128__" }, 8888 { "atmega128a", "__AVR_ATmega128A__" }, 8889 { "atmega1280", "__AVR_ATmega1280__" }, 8890 { "atmega1281", "__AVR_ATmega1281__" }, 8891 { "atmega1284", "__AVR_ATmega1284__" }, 8892 { "atmega1284p", "__AVR_ATmega1284P__" }, 8893 { "atmega128rfa1", "__AVR_ATmega128RFA1__" }, 8894 { "atmega128rfr2", "__AVR_ATmega128RFR2__" }, 8895 { "atmega1284rfr2", "__AVR_ATmega1284RFR2__" }, 8896 { "at90can128", "__AVR_AT90CAN128__" }, 8897 { "at90usb1286", "__AVR_AT90USB1286__" }, 8898 { "at90usb1287", "__AVR_AT90USB1287__" }, 8899 { "atmega2560", "__AVR_ATmega2560__" }, 8900 { "atmega2561", "__AVR_ATmega2561__" }, 8901 { "atmega256rfr2", "__AVR_ATmega256RFR2__" }, 8902 { "atmega2564rfr2", "__AVR_ATmega2564RFR2__" }, 8903 { "atxmega16a4", "__AVR_ATxmega16A4__" }, 8904 { "atxmega16a4u", "__AVR_ATxmega16a4U__" }, 8905 { "atxmega16c4", "__AVR_ATxmega16C4__" }, 8906 { "atxmega16d4", "__AVR_ATxmega16D4__" }, 8907 { "atxmega32a4", "__AVR_ATxmega32A4__" }, 8908 { "atxmega32a4u", "__AVR_ATxmega32A4U__" }, 8909 { "atxmega32c4", "__AVR_ATxmega32C4__" }, 8910 { "atxmega32d4", "__AVR_ATxmega32D4__" }, 8911 { "atxmega32e5", "__AVR_ATxmega32E5__" }, 8912 { "atxmega16e5", "__AVR_ATxmega16E5__" }, 8913 { "atxmega8e5", "__AVR_ATxmega8E5__" }, 8914 { "atxmega32x1", "__AVR_ATxmega32X1__" }, 8915 { "atxmega64a3", "__AVR_ATxmega64A3__" }, 8916 { "atxmega64a3u", "__AVR_ATxmega64A3U__" }, 8917 { "atxmega64a4u", "__AVR_ATxmega64A4U__" }, 8918 { "atxmega64b1", "__AVR_ATxmega64B1__" }, 8919 { "atxmega64b3", "__AVR_ATxmega64B3__" }, 8920 { "atxmega64c3", "__AVR_ATxmega64C3__" }, 8921 { "atxmega64d3", "__AVR_ATxmega64D3__" }, 8922 { "atxmega64d4", "__AVR_ATxmega64D4__" }, 8923 { "atxmega64a1", "__AVR_ATxmega64A1__" }, 8924 { "atxmega64a1u", "__AVR_ATxmega64A1U__" }, 8925 { "atxmega128a3", "__AVR_ATxmega128A3__" }, 8926 { "atxmega128a3u", "__AVR_ATxmega128A3U__" }, 8927 { "atxmega128b1", "__AVR_ATxmega128B1__" }, 8928 { "atxmega128b3", "__AVR_ATxmega128B3__" }, 8929 { "atxmega128c3", "__AVR_ATxmega128C3__" }, 8930 { "atxmega128d3", "__AVR_ATxmega128D3__" }, 8931 { "atxmega128d4", "__AVR_ATxmega128D4__" }, 8932 { "atxmega192a3", "__AVR_ATxmega192A3__" }, 8933 { "atxmega192a3u", "__AVR_ATxmega192A3U__" }, 8934 { "atxmega192c3", "__AVR_ATxmega192C3__" }, 8935 { "atxmega192d3", "__AVR_ATxmega192D3__" }, 8936 { "atxmega256a3", "__AVR_ATxmega256A3__" }, 8937 { "atxmega256a3u", "__AVR_ATxmega256A3U__" }, 8938 { "atxmega256a3b", "__AVR_ATxmega256A3B__" }, 8939 { "atxmega256a3bu", "__AVR_ATxmega256A3BU__" }, 8940 { "atxmega256c3", "__AVR_ATxmega256C3__" }, 8941 { "atxmega256d3", "__AVR_ATxmega256D3__" }, 8942 { "atxmega384c3", "__AVR_ATxmega384C3__" }, 8943 { "atxmega384d3", "__AVR_ATxmega384D3__" }, 8944 { "atxmega128a1", "__AVR_ATxmega128A1__" }, 8945 { "atxmega128a1u", "__AVR_ATxmega128A1U__" }, 8946 { "atxmega128a4u", "__AVR_ATxmega128a4U__" }, 8947 { "attiny4", "__AVR_ATtiny4__" }, 8948 { "attiny5", "__AVR_ATtiny5__" }, 8949 { "attiny9", "__AVR_ATtiny9__" }, 8950 { "attiny10", "__AVR_ATtiny10__" }, 8951 { "attiny20", "__AVR_ATtiny20__" }, 8952 { "attiny40", "__AVR_ATtiny40__" }, 8953 { "attiny102", "__AVR_ATtiny102__" }, 8954 { "attiny104", "__AVR_ATtiny104__" }, 8955 }; 8956 8957 // AVR Target 8958 class AVRTargetInfo : public TargetInfo { 8959 public: 8960 AVRTargetInfo(const llvm::Triple &Triple, const TargetOptions &) 8961 : TargetInfo(Triple) { 8962 TLSSupported = false; 8963 PointerWidth = 16; 8964 PointerAlign = 8; 8965 IntWidth = 16; 8966 IntAlign = 8; 8967 LongWidth = 32; 8968 LongAlign = 8; 8969 LongLongWidth = 64; 8970 LongLongAlign = 8; 8971 SuitableAlign = 8; 8972 DefaultAlignForAttributeAligned = 8; 8973 HalfWidth = 16; 8974 HalfAlign = 8; 8975 FloatWidth = 32; 8976 FloatAlign = 8; 8977 DoubleWidth = 32; 8978 DoubleAlign = 8; 8979 DoubleFormat = &llvm::APFloat::IEEEsingle(); 8980 LongDoubleWidth = 32; 8981 LongDoubleAlign = 8; 8982 LongDoubleFormat = &llvm::APFloat::IEEEsingle(); 8983 SizeType = UnsignedInt; 8984 PtrDiffType = SignedInt; 8985 IntPtrType = SignedInt; 8986 Char16Type = UnsignedInt; 8987 WCharType = SignedInt; 8988 WIntType = SignedInt; 8989 Char32Type = UnsignedLong; 8990 SigAtomicType = SignedChar; 8991 resetDataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:32:32-i64:64:64" 8992 "-f32:32:32-f64:64:64-n8"); 8993 } 8994 8995 void getTargetDefines(const LangOptions &Opts, 8996 MacroBuilder &Builder) const override { 8997 Builder.defineMacro("AVR"); 8998 Builder.defineMacro("__AVR"); 8999 Builder.defineMacro("__AVR__"); 9000 9001 if (!this->CPU.empty()) { 9002 auto It = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9003 [&](const MCUInfo &Info) { return Info.Name == this->CPU; }); 9004 9005 if (It != AVRMcus.end()) 9006 Builder.defineMacro(It->DefineName); 9007 } 9008 } 9009 9010 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 9011 return None; 9012 } 9013 9014 BuiltinVaListKind getBuiltinVaListKind() const override { 9015 return TargetInfo::VoidPtrBuiltinVaList; 9016 } 9017 9018 const char *getClobbers() const override { 9019 return ""; 9020 } 9021 9022 ArrayRef<const char *> getGCCRegNames() const override { 9023 static const char * const GCCRegNames[] = { 9024 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 9025 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 9026 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 9027 "r24", "r25", "X", "Y", "Z", "SP" 9028 }; 9029 return llvm::makeArrayRef(GCCRegNames); 9030 } 9031 9032 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 9033 return None; 9034 } 9035 9036 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 9037 static const TargetInfo::AddlRegName AddlRegNames[] = { 9038 { { "r26", "r27"}, 26 }, 9039 { { "r28", "r29"}, 27 }, 9040 { { "r30", "r31"}, 28 }, 9041 { { "SPL", "SPH"}, 29 }, 9042 }; 9043 return llvm::makeArrayRef(AddlRegNames); 9044 } 9045 9046 bool validateAsmConstraint(const char *&Name, 9047 TargetInfo::ConstraintInfo &Info) const override { 9048 // There aren't any multi-character AVR specific constraints. 9049 if (StringRef(Name).size() > 1) return false; 9050 9051 switch (*Name) { 9052 default: return false; 9053 case 'a': // Simple upper registers 9054 case 'b': // Base pointer registers pairs 9055 case 'd': // Upper register 9056 case 'l': // Lower registers 9057 case 'e': // Pointer register pairs 9058 case 'q': // Stack pointer register 9059 case 'r': // Any register 9060 case 'w': // Special upper register pairs 9061 case 't': // Temporary register 9062 case 'x': case 'X': // Pointer register pair X 9063 case 'y': case 'Y': // Pointer register pair Y 9064 case 'z': case 'Z': // Pointer register pair Z 9065 Info.setAllowsRegister(); 9066 return true; 9067 case 'I': // 6-bit positive integer constant 9068 Info.setRequiresImmediate(0, 63); 9069 return true; 9070 case 'J': // 6-bit negative integer constant 9071 Info.setRequiresImmediate(-63, 0); 9072 return true; 9073 case 'K': // Integer constant (Range: 2) 9074 Info.setRequiresImmediate(2); 9075 return true; 9076 case 'L': // Integer constant (Range: 0) 9077 Info.setRequiresImmediate(0); 9078 return true; 9079 case 'M': // 8-bit integer constant 9080 Info.setRequiresImmediate(0, 0xff); 9081 return true; 9082 case 'N': // Integer constant (Range: -1) 9083 Info.setRequiresImmediate(-1); 9084 return true; 9085 case 'O': // Integer constant (Range: 8, 16, 24) 9086 Info.setRequiresImmediate({8, 16, 24}); 9087 return true; 9088 case 'P': // Integer constant (Range: 1) 9089 Info.setRequiresImmediate(1); 9090 return true; 9091 case 'R': // Integer constant (Range: -6 to 5) 9092 Info.setRequiresImmediate(-6, 5); 9093 return true; 9094 case 'G': // Floating point constant 9095 case 'Q': // A memory address based on Y or Z pointer with displacement. 9096 return true; 9097 } 9098 9099 return false; 9100 } 9101 9102 IntType getIntTypeByWidth(unsigned BitWidth, 9103 bool IsSigned) const final { 9104 // AVR prefers int for 16-bit integers. 9105 return BitWidth == 16 ? (IsSigned ? SignedInt : UnsignedInt) 9106 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 9107 } 9108 9109 IntType getLeastIntTypeByWidth(unsigned BitWidth, 9110 bool IsSigned) const final { 9111 // AVR uses int for int_least16_t and int_fast16_t. 9112 return BitWidth == 16 9113 ? (IsSigned ? SignedInt : UnsignedInt) 9114 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 9115 } 9116 9117 bool setCPU(const std::string &Name) override { 9118 bool IsFamily = llvm::StringSwitch<bool>(Name) 9119 .Case("avr1", true) 9120 .Case("avr2", true) 9121 .Case("avr25", true) 9122 .Case("avr3", true) 9123 .Case("avr31", true) 9124 .Case("avr35", true) 9125 .Case("avr4", true) 9126 .Case("avr5", true) 9127 .Case("avr51", true) 9128 .Case("avr6", true) 9129 .Case("avrxmega1", true) 9130 .Case("avrxmega2", true) 9131 .Case("avrxmega3", true) 9132 .Case("avrxmega4", true) 9133 .Case("avrxmega5", true) 9134 .Case("avrxmega6", true) 9135 .Case("avrxmega7", true) 9136 .Case("avrtiny", true) 9137 .Default(false); 9138 9139 if (IsFamily) this->CPU = Name; 9140 9141 bool IsMCU = std::find_if(AVRMcus.begin(), AVRMcus.end(), 9142 [&](const MCUInfo &Info) { return Info.Name == Name; }) != AVRMcus.end(); 9143 9144 if (IsMCU) this->CPU = Name; 9145 9146 return IsFamily || IsMCU; 9147 } 9148 9149 protected: 9150 std::string CPU; 9151 }; 9152 9153 } // end anonymous namespace 9154 9155 //===----------------------------------------------------------------------===// 9156 // Driver code 9157 //===----------------------------------------------------------------------===// 9158 9159 static TargetInfo *AllocateTarget(const llvm::Triple &Triple, 9160 const TargetOptions &Opts) { 9161 llvm::Triple::OSType os = Triple.getOS(); 9162 9163 switch (Triple.getArch()) { 9164 default: 9165 return nullptr; 9166 9167 case llvm::Triple::xcore: 9168 return new XCoreTargetInfo(Triple, Opts); 9169 9170 case llvm::Triple::hexagon: 9171 return new HexagonTargetInfo(Triple, Opts); 9172 9173 case llvm::Triple::lanai: 9174 return new LanaiTargetInfo(Triple, Opts); 9175 9176 case llvm::Triple::aarch64: 9177 if (Triple.isOSDarwin()) 9178 return new DarwinAArch64TargetInfo(Triple, Opts); 9179 9180 switch (os) { 9181 case llvm::Triple::CloudABI: 9182 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple, Opts); 9183 case llvm::Triple::FreeBSD: 9184 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9185 case llvm::Triple::Fuchsia: 9186 return new FuchsiaTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9187 case llvm::Triple::Linux: 9188 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9189 case llvm::Triple::NetBSD: 9190 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9191 case llvm::Triple::OpenBSD: 9192 return new OpenBSDTargetInfo<AArch64leTargetInfo>(Triple, Opts); 9193 default: 9194 return new AArch64leTargetInfo(Triple, Opts); 9195 } 9196 9197 case llvm::Triple::aarch64_be: 9198 switch (os) { 9199 case llvm::Triple::FreeBSD: 9200 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9201 case llvm::Triple::Fuchsia: 9202 return new FuchsiaTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9203 case llvm::Triple::Linux: 9204 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9205 case llvm::Triple::NetBSD: 9206 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple, Opts); 9207 default: 9208 return new AArch64beTargetInfo(Triple, Opts); 9209 } 9210 9211 case llvm::Triple::arm: 9212 case llvm::Triple::thumb: 9213 if (Triple.isOSBinFormatMachO()) 9214 return new DarwinARMTargetInfo(Triple, Opts); 9215 9216 switch (os) { 9217 case llvm::Triple::CloudABI: 9218 return new CloudABITargetInfo<ARMleTargetInfo>(Triple, Opts); 9219 case llvm::Triple::Linux: 9220 return new LinuxTargetInfo<ARMleTargetInfo>(Triple, Opts); 9221 case llvm::Triple::FreeBSD: 9222 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9223 case llvm::Triple::NetBSD: 9224 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9225 case llvm::Triple::OpenBSD: 9226 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple, Opts); 9227 case llvm::Triple::Bitrig: 9228 return new BitrigTargetInfo<ARMleTargetInfo>(Triple, Opts); 9229 case llvm::Triple::RTEMS: 9230 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple, Opts); 9231 case llvm::Triple::NaCl: 9232 return new NaClTargetInfo<ARMleTargetInfo>(Triple, Opts); 9233 case llvm::Triple::Win32: 9234 switch (Triple.getEnvironment()) { 9235 case llvm::Triple::Cygnus: 9236 return new CygwinARMTargetInfo(Triple, Opts); 9237 case llvm::Triple::GNU: 9238 return new MinGWARMTargetInfo(Triple, Opts); 9239 case llvm::Triple::Itanium: 9240 return new ItaniumWindowsARMleTargetInfo(Triple, Opts); 9241 case llvm::Triple::MSVC: 9242 default: // Assume MSVC for unknown environments 9243 return new MicrosoftARMleTargetInfo(Triple, Opts); 9244 } 9245 default: 9246 return new ARMleTargetInfo(Triple, Opts); 9247 } 9248 9249 case llvm::Triple::armeb: 9250 case llvm::Triple::thumbeb: 9251 if (Triple.isOSDarwin()) 9252 return new DarwinARMTargetInfo(Triple, Opts); 9253 9254 switch (os) { 9255 case llvm::Triple::Linux: 9256 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9257 case llvm::Triple::FreeBSD: 9258 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9259 case llvm::Triple::NetBSD: 9260 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9261 case llvm::Triple::OpenBSD: 9262 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9263 case llvm::Triple::Bitrig: 9264 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9265 case llvm::Triple::RTEMS: 9266 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9267 case llvm::Triple::NaCl: 9268 return new NaClTargetInfo<ARMbeTargetInfo>(Triple, Opts); 9269 default: 9270 return new ARMbeTargetInfo(Triple, Opts); 9271 } 9272 9273 case llvm::Triple::avr: 9274 return new AVRTargetInfo(Triple, Opts); 9275 case llvm::Triple::bpfeb: 9276 case llvm::Triple::bpfel: 9277 return new BPFTargetInfo(Triple, Opts); 9278 9279 case llvm::Triple::msp430: 9280 return new MSP430TargetInfo(Triple, Opts); 9281 9282 case llvm::Triple::mips: 9283 switch (os) { 9284 case llvm::Triple::Linux: 9285 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9286 case llvm::Triple::RTEMS: 9287 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9288 case llvm::Triple::FreeBSD: 9289 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9290 case llvm::Triple::NetBSD: 9291 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9292 default: 9293 return new MipsTargetInfo(Triple, Opts); 9294 } 9295 9296 case llvm::Triple::mipsel: 9297 switch (os) { 9298 case llvm::Triple::Linux: 9299 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9300 case llvm::Triple::RTEMS: 9301 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9302 case llvm::Triple::FreeBSD: 9303 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9304 case llvm::Triple::NetBSD: 9305 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9306 case llvm::Triple::NaCl: 9307 return new NaClTargetInfo<NaClMips32TargetInfo>(Triple, Opts); 9308 default: 9309 return new MipsTargetInfo(Triple, Opts); 9310 } 9311 9312 case llvm::Triple::mips64: 9313 switch (os) { 9314 case llvm::Triple::Linux: 9315 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9316 case llvm::Triple::RTEMS: 9317 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9318 case llvm::Triple::FreeBSD: 9319 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9320 case llvm::Triple::NetBSD: 9321 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9322 case llvm::Triple::OpenBSD: 9323 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9324 default: 9325 return new MipsTargetInfo(Triple, Opts); 9326 } 9327 9328 case llvm::Triple::mips64el: 9329 switch (os) { 9330 case llvm::Triple::Linux: 9331 return new LinuxTargetInfo<MipsTargetInfo>(Triple, Opts); 9332 case llvm::Triple::RTEMS: 9333 return new RTEMSTargetInfo<MipsTargetInfo>(Triple, Opts); 9334 case llvm::Triple::FreeBSD: 9335 return new FreeBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9336 case llvm::Triple::NetBSD: 9337 return new NetBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9338 case llvm::Triple::OpenBSD: 9339 return new OpenBSDTargetInfo<MipsTargetInfo>(Triple, Opts); 9340 default: 9341 return new MipsTargetInfo(Triple, Opts); 9342 } 9343 9344 case llvm::Triple::le32: 9345 switch (os) { 9346 case llvm::Triple::NaCl: 9347 return new NaClTargetInfo<PNaClTargetInfo>(Triple, Opts); 9348 default: 9349 return nullptr; 9350 } 9351 9352 case llvm::Triple::le64: 9353 return new Le64TargetInfo(Triple, Opts); 9354 9355 case llvm::Triple::ppc: 9356 if (Triple.isOSDarwin()) 9357 return new DarwinPPC32TargetInfo(Triple, Opts); 9358 switch (os) { 9359 case llvm::Triple::Linux: 9360 return new LinuxTargetInfo<PPC32TargetInfo>(Triple, Opts); 9361 case llvm::Triple::FreeBSD: 9362 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9363 case llvm::Triple::NetBSD: 9364 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9365 case llvm::Triple::OpenBSD: 9366 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple, Opts); 9367 case llvm::Triple::RTEMS: 9368 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple, Opts); 9369 default: 9370 return new PPC32TargetInfo(Triple, Opts); 9371 } 9372 9373 case llvm::Triple::ppc64: 9374 if (Triple.isOSDarwin()) 9375 return new DarwinPPC64TargetInfo(Triple, Opts); 9376 switch (os) { 9377 case llvm::Triple::Linux: 9378 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9379 case llvm::Triple::Lv2: 9380 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple, Opts); 9381 case llvm::Triple::FreeBSD: 9382 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9383 case llvm::Triple::NetBSD: 9384 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9385 default: 9386 return new PPC64TargetInfo(Triple, Opts); 9387 } 9388 9389 case llvm::Triple::ppc64le: 9390 switch (os) { 9391 case llvm::Triple::Linux: 9392 return new LinuxTargetInfo<PPC64TargetInfo>(Triple, Opts); 9393 case llvm::Triple::NetBSD: 9394 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple, Opts); 9395 default: 9396 return new PPC64TargetInfo(Triple, Opts); 9397 } 9398 9399 case llvm::Triple::nvptx: 9400 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/32); 9401 case llvm::Triple::nvptx64: 9402 return new NVPTXTargetInfo(Triple, Opts, /*TargetPointerWidth=*/64); 9403 9404 case llvm::Triple::amdgcn: 9405 case llvm::Triple::r600: 9406 return new AMDGPUTargetInfo(Triple, Opts); 9407 9408 case llvm::Triple::sparc: 9409 switch (os) { 9410 case llvm::Triple::Linux: 9411 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9412 case llvm::Triple::Solaris: 9413 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9414 case llvm::Triple::NetBSD: 9415 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9416 case llvm::Triple::OpenBSD: 9417 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9418 case llvm::Triple::RTEMS: 9419 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple, Opts); 9420 default: 9421 return new SparcV8TargetInfo(Triple, Opts); 9422 } 9423 9424 // The 'sparcel' architecture copies all the above cases except for Solaris. 9425 case llvm::Triple::sparcel: 9426 switch (os) { 9427 case llvm::Triple::Linux: 9428 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9429 case llvm::Triple::NetBSD: 9430 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9431 case llvm::Triple::OpenBSD: 9432 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9433 case llvm::Triple::RTEMS: 9434 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple, Opts); 9435 default: 9436 return new SparcV8elTargetInfo(Triple, Opts); 9437 } 9438 9439 case llvm::Triple::sparcv9: 9440 switch (os) { 9441 case llvm::Triple::Linux: 9442 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9443 case llvm::Triple::Solaris: 9444 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9445 case llvm::Triple::NetBSD: 9446 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9447 case llvm::Triple::OpenBSD: 9448 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9449 case llvm::Triple::FreeBSD: 9450 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple, Opts); 9451 default: 9452 return new SparcV9TargetInfo(Triple, Opts); 9453 } 9454 9455 case llvm::Triple::systemz: 9456 switch (os) { 9457 case llvm::Triple::Linux: 9458 return new LinuxTargetInfo<SystemZTargetInfo>(Triple, Opts); 9459 default: 9460 return new SystemZTargetInfo(Triple, Opts); 9461 } 9462 9463 case llvm::Triple::tce: 9464 return new TCETargetInfo(Triple, Opts); 9465 9466 case llvm::Triple::tcele: 9467 return new TCELETargetInfo(Triple, Opts); 9468 9469 case llvm::Triple::x86: 9470 if (Triple.isOSDarwin()) 9471 return new DarwinI386TargetInfo(Triple, Opts); 9472 9473 switch (os) { 9474 case llvm::Triple::CloudABI: 9475 return new CloudABITargetInfo<X86_32TargetInfo>(Triple, Opts); 9476 case llvm::Triple::Linux: { 9477 switch (Triple.getEnvironment()) { 9478 default: 9479 return new LinuxTargetInfo<X86_32TargetInfo>(Triple, Opts); 9480 case llvm::Triple::Android: 9481 return new AndroidX86_32TargetInfo(Triple, Opts); 9482 } 9483 } 9484 case llvm::Triple::DragonFly: 9485 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9486 case llvm::Triple::NetBSD: 9487 return new NetBSDI386TargetInfo(Triple, Opts); 9488 case llvm::Triple::OpenBSD: 9489 return new OpenBSDI386TargetInfo(Triple, Opts); 9490 case llvm::Triple::Bitrig: 9491 return new BitrigI386TargetInfo(Triple, Opts); 9492 case llvm::Triple::FreeBSD: 9493 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9494 case llvm::Triple::KFreeBSD: 9495 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple, Opts); 9496 case llvm::Triple::Minix: 9497 return new MinixTargetInfo<X86_32TargetInfo>(Triple, Opts); 9498 case llvm::Triple::Solaris: 9499 return new SolarisTargetInfo<X86_32TargetInfo>(Triple, Opts); 9500 case llvm::Triple::Win32: { 9501 switch (Triple.getEnvironment()) { 9502 case llvm::Triple::Cygnus: 9503 return new CygwinX86_32TargetInfo(Triple, Opts); 9504 case llvm::Triple::GNU: 9505 return new MinGWX86_32TargetInfo(Triple, Opts); 9506 case llvm::Triple::Itanium: 9507 case llvm::Triple::MSVC: 9508 default: // Assume MSVC for unknown environments 9509 return new MicrosoftX86_32TargetInfo(Triple, Opts); 9510 } 9511 } 9512 case llvm::Triple::Haiku: 9513 return new HaikuX86_32TargetInfo(Triple, Opts); 9514 case llvm::Triple::RTEMS: 9515 return new RTEMSX86_32TargetInfo(Triple, Opts); 9516 case llvm::Triple::NaCl: 9517 return new NaClTargetInfo<X86_32TargetInfo>(Triple, Opts); 9518 case llvm::Triple::ELFIAMCU: 9519 return new MCUX86_32TargetInfo(Triple, Opts); 9520 default: 9521 return new X86_32TargetInfo(Triple, Opts); 9522 } 9523 9524 case llvm::Triple::x86_64: 9525 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 9526 return new DarwinX86_64TargetInfo(Triple, Opts); 9527 9528 switch (os) { 9529 case llvm::Triple::CloudABI: 9530 return new CloudABITargetInfo<X86_64TargetInfo>(Triple, Opts); 9531 case llvm::Triple::Linux: { 9532 switch (Triple.getEnvironment()) { 9533 default: 9534 return new LinuxTargetInfo<X86_64TargetInfo>(Triple, Opts); 9535 case llvm::Triple::Android: 9536 return new AndroidX86_64TargetInfo(Triple, Opts); 9537 } 9538 } 9539 case llvm::Triple::DragonFly: 9540 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9541 case llvm::Triple::NetBSD: 9542 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9543 case llvm::Triple::OpenBSD: 9544 return new OpenBSDX86_64TargetInfo(Triple, Opts); 9545 case llvm::Triple::Bitrig: 9546 return new BitrigX86_64TargetInfo(Triple, Opts); 9547 case llvm::Triple::FreeBSD: 9548 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9549 case llvm::Triple::Fuchsia: 9550 return new FuchsiaTargetInfo<X86_64TargetInfo>(Triple, Opts); 9551 case llvm::Triple::KFreeBSD: 9552 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple, Opts); 9553 case llvm::Triple::Solaris: 9554 return new SolarisTargetInfo<X86_64TargetInfo>(Triple, Opts); 9555 case llvm::Triple::Win32: { 9556 switch (Triple.getEnvironment()) { 9557 case llvm::Triple::Cygnus: 9558 return new CygwinX86_64TargetInfo(Triple, Opts); 9559 case llvm::Triple::GNU: 9560 return new MinGWX86_64TargetInfo(Triple, Opts); 9561 case llvm::Triple::MSVC: 9562 default: // Assume MSVC for unknown environments 9563 return new MicrosoftX86_64TargetInfo(Triple, Opts); 9564 } 9565 } 9566 case llvm::Triple::Haiku: 9567 return new HaikuTargetInfo<X86_64TargetInfo>(Triple, Opts); 9568 case llvm::Triple::NaCl: 9569 return new NaClTargetInfo<X86_64TargetInfo>(Triple, Opts); 9570 case llvm::Triple::PS4: 9571 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple, Opts); 9572 default: 9573 return new X86_64TargetInfo(Triple, Opts); 9574 } 9575 9576 case llvm::Triple::spir: { 9577 if (Triple.getOS() != llvm::Triple::UnknownOS || 9578 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9579 return nullptr; 9580 return new SPIR32TargetInfo(Triple, Opts); 9581 } 9582 case llvm::Triple::spir64: { 9583 if (Triple.getOS() != llvm::Triple::UnknownOS || 9584 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 9585 return nullptr; 9586 return new SPIR64TargetInfo(Triple, Opts); 9587 } 9588 case llvm::Triple::wasm32: 9589 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9590 Triple.getVendor() != llvm::Triple::UnknownVendor || 9591 Triple.getOS() != llvm::Triple::UnknownOS || 9592 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9593 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9594 return nullptr; 9595 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple, Opts); 9596 case llvm::Triple::wasm64: 9597 if (Triple.getSubArch() != llvm::Triple::NoSubArch || 9598 Triple.getVendor() != llvm::Triple::UnknownVendor || 9599 Triple.getOS() != llvm::Triple::UnknownOS || 9600 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment || 9601 !(Triple.isOSBinFormatELF() || Triple.isOSBinFormatWasm())) 9602 return nullptr; 9603 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple, Opts); 9604 9605 case llvm::Triple::renderscript32: 9606 return new LinuxTargetInfo<RenderScript32TargetInfo>(Triple, Opts); 9607 case llvm::Triple::renderscript64: 9608 return new LinuxTargetInfo<RenderScript64TargetInfo>(Triple, Opts); 9609 } 9610 } 9611 9612 /// CreateTargetInfo - Return the target info object for the specified target 9613 /// options. 9614 TargetInfo * 9615 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 9616 const std::shared_ptr<TargetOptions> &Opts) { 9617 llvm::Triple Triple(Opts->Triple); 9618 9619 // Construct the target 9620 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple, *Opts)); 9621 if (!Target) { 9622 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 9623 return nullptr; 9624 } 9625 Target->TargetOpts = Opts; 9626 9627 // Set the target CPU if specified. 9628 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 9629 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 9630 return nullptr; 9631 } 9632 9633 // Set the target ABI if specified. 9634 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 9635 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 9636 return nullptr; 9637 } 9638 9639 // Set the fp math unit. 9640 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 9641 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 9642 return nullptr; 9643 } 9644 9645 // Compute the default target features, we need the target to handle this 9646 // because features may have dependencies on one another. 9647 llvm::StringMap<bool> Features; 9648 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 9649 Opts->FeaturesAsWritten)) 9650 return nullptr; 9651 9652 // Add the features to the compile options. 9653 Opts->Features.clear(); 9654 for (const auto &F : Features) 9655 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 9656 9657 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 9658 return nullptr; 9659 9660 Target->setSupportedOpenCLOpts(); 9661 Target->setOpenCLExtensionOpts(); 9662 9663 if (!Target->validateTarget(Diags)) 9664 return nullptr; 9665 9666 return Target.release(); 9667 } 9668