1 //===--- Targets.cpp - Implement target feature support -------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "clang/Basic/Version.h" 23 #include "llvm/ADT/APFloat.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/StringSwitch.h" 28 #include "llvm/ADT/Triple.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/TargetParser.h" 32 #include <algorithm> 33 #include <memory> 34 35 using namespace clang; 36 37 //===----------------------------------------------------------------------===// 38 // Common code shared among targets. 39 //===----------------------------------------------------------------------===// 40 41 /// DefineStd - Define a macro name and standard variants. For example if 42 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 43 /// when in GNU mode. 44 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 45 const LangOptions &Opts) { 46 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 47 48 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 49 // in the user's namespace. 50 if (Opts.GNUMode) 51 Builder.defineMacro(MacroName); 52 53 // Define __unix. 54 Builder.defineMacro("__" + MacroName); 55 56 // Define __unix__. 57 Builder.defineMacro("__" + MacroName + "__"); 58 } 59 60 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 61 bool Tuning = true) { 62 Builder.defineMacro("__" + CPUName); 63 Builder.defineMacro("__" + CPUName + "__"); 64 if (Tuning) 65 Builder.defineMacro("__tune_" + CPUName + "__"); 66 } 67 68 //===----------------------------------------------------------------------===// 69 // Defines specific to certain operating systems. 70 //===----------------------------------------------------------------------===// 71 72 namespace { 73 template<typename TgtInfo> 74 class OSTargetInfo : public TgtInfo { 75 protected: 76 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 77 MacroBuilder &Builder) const=0; 78 public: 79 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 80 void getTargetDefines(const LangOptions &Opts, 81 MacroBuilder &Builder) const override { 82 TgtInfo::getTargetDefines(Opts, Builder); 83 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 84 } 85 86 }; 87 88 // CloudABI Target 89 template <typename Target> 90 class CloudABITargetInfo : public OSTargetInfo<Target> { 91 protected: 92 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 93 MacroBuilder &Builder) const override { 94 Builder.defineMacro("__CloudABI__"); 95 Builder.defineMacro("__ELF__"); 96 97 // CloudABI uses ISO/IEC 10646:2012 for wchar_t, char16_t and char32_t. 98 Builder.defineMacro("__STDC_ISO_10646__", "201206L"); 99 Builder.defineMacro("__STDC_UTF_16__"); 100 Builder.defineMacro("__STDC_UTF_32__"); 101 } 102 103 public: 104 CloudABITargetInfo(const llvm::Triple &Triple) 105 : OSTargetInfo<Target>(Triple) { 106 this->UserLabelPrefix = ""; 107 } 108 }; 109 110 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 111 const llvm::Triple &Triple, 112 StringRef &PlatformName, 113 VersionTuple &PlatformMinVersion) { 114 Builder.defineMacro("__APPLE_CC__", "6000"); 115 Builder.defineMacro("__APPLE__"); 116 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 117 // AddressSanitizer doesn't play well with source fortification, which is on 118 // by default on Darwin. 119 if (Opts.Sanitize.has(SanitizerKind::Address)) 120 Builder.defineMacro("_FORTIFY_SOURCE", "0"); 121 122 // Darwin defines __weak, __strong, and __unsafe_unretained even in C mode. 123 if (!Opts.ObjC1) { 124 // __weak is always defined, for use in blocks and with objc pointers. 125 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 126 Builder.defineMacro("__strong", ""); 127 Builder.defineMacro("__unsafe_unretained", ""); 128 } 129 130 if (Opts.Static) 131 Builder.defineMacro("__STATIC__"); 132 else 133 Builder.defineMacro("__DYNAMIC__"); 134 135 if (Opts.POSIXThreads) 136 Builder.defineMacro("_REENTRANT"); 137 138 // Get the platform type and version number from the triple. 139 unsigned Maj, Min, Rev; 140 if (Triple.isMacOSX()) { 141 Triple.getMacOSXVersion(Maj, Min, Rev); 142 PlatformName = "macosx"; 143 } else { 144 Triple.getOSVersion(Maj, Min, Rev); 145 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 146 } 147 148 // If -target arch-pc-win32-macho option specified, we're 149 // generating code for Win32 ABI. No need to emit 150 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 151 if (PlatformName == "win32") { 152 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 153 return; 154 } 155 156 // Set the appropriate OS version define. 157 if (Triple.isiOS()) { 158 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 159 char Str[6]; 160 Str[0] = '0' + Maj; 161 Str[1] = '0' + (Min / 10); 162 Str[2] = '0' + (Min % 10); 163 Str[3] = '0' + (Rev / 10); 164 Str[4] = '0' + (Rev % 10); 165 Str[5] = '\0'; 166 if (Triple.isTvOS()) 167 Builder.defineMacro("__ENVIRONMENT_TV_OS_VERSION_MIN_REQUIRED__", Str); 168 else 169 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 170 Str); 171 172 } else if (Triple.isWatchOS()) { 173 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 174 char Str[6]; 175 Str[0] = '0' + Maj; 176 Str[1] = '0' + (Min / 10); 177 Str[2] = '0' + (Min % 10); 178 Str[3] = '0' + (Rev / 10); 179 Str[4] = '0' + (Rev % 10); 180 Str[5] = '\0'; 181 Builder.defineMacro("__ENVIRONMENT_WATCH_OS_VERSION_MIN_REQUIRED__", Str); 182 } else if (Triple.isMacOSX()) { 183 // Note that the Driver allows versions which aren't representable in the 184 // define (because we only get a single digit for the minor and micro 185 // revision numbers). So, we limit them to the maximum representable 186 // version. 187 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 188 char Str[7]; 189 if (Maj < 10 || (Maj == 10 && Min < 10)) { 190 Str[0] = '0' + (Maj / 10); 191 Str[1] = '0' + (Maj % 10); 192 Str[2] = '0' + std::min(Min, 9U); 193 Str[3] = '0' + std::min(Rev, 9U); 194 Str[4] = '\0'; 195 } else { 196 // Handle versions > 10.9. 197 Str[0] = '0' + (Maj / 10); 198 Str[1] = '0' + (Maj % 10); 199 Str[2] = '0' + (Min / 10); 200 Str[3] = '0' + (Min % 10); 201 Str[4] = '0' + (Rev / 10); 202 Str[5] = '0' + (Rev % 10); 203 Str[6] = '\0'; 204 } 205 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 206 } 207 208 // Tell users about the kernel if there is one. 209 if (Triple.isOSDarwin()) 210 Builder.defineMacro("__MACH__"); 211 212 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 213 } 214 215 template<typename Target> 216 class DarwinTargetInfo : public OSTargetInfo<Target> { 217 protected: 218 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 219 MacroBuilder &Builder) const override { 220 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 221 this->PlatformMinVersion); 222 } 223 224 public: 225 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 226 // By default, no TLS, and we whitelist permitted architecture/OS 227 // combinations. 228 this->TLSSupported = false; 229 230 if (Triple.isMacOSX()) 231 this->TLSSupported = !Triple.isMacOSXVersionLT(10, 7); 232 else if (Triple.isiOS()) { 233 // 64-bit iOS supported it from 8 onwards, 32-bit from 9 onwards. 234 if (Triple.getArch() == llvm::Triple::x86_64 || 235 Triple.getArch() == llvm::Triple::aarch64) 236 this->TLSSupported = !Triple.isOSVersionLT(8); 237 else if (Triple.getArch() == llvm::Triple::x86 || 238 Triple.getArch() == llvm::Triple::arm || 239 Triple.getArch() == llvm::Triple::thumb) 240 this->TLSSupported = !Triple.isOSVersionLT(9); 241 } else if (Triple.isWatchOS()) 242 this->TLSSupported = !Triple.isOSVersionLT(2); 243 244 this->MCountName = "\01mcount"; 245 } 246 247 std::string isValidSectionSpecifier(StringRef SR) const override { 248 // Let MCSectionMachO validate this. 249 StringRef Segment, Section; 250 unsigned TAA, StubSize; 251 bool HasTAA; 252 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 253 TAA, HasTAA, StubSize); 254 } 255 256 const char *getStaticInitSectionSpecifier() const override { 257 // FIXME: We should return 0 when building kexts. 258 return "__TEXT,__StaticInit,regular,pure_instructions"; 259 } 260 261 /// Darwin does not support protected visibility. Darwin's "default" 262 /// is very similar to ELF's "protected"; Darwin requires a "weak" 263 /// attribute on declarations that can be dynamically replaced. 264 bool hasProtectedVisibility() const override { 265 return false; 266 } 267 }; 268 269 270 // DragonFlyBSD Target 271 template<typename Target> 272 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 273 protected: 274 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 275 MacroBuilder &Builder) const override { 276 // DragonFly defines; list based off of gcc output 277 Builder.defineMacro("__DragonFly__"); 278 Builder.defineMacro("__DragonFly_cc_version", "100001"); 279 Builder.defineMacro("__ELF__"); 280 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 281 Builder.defineMacro("__tune_i386__"); 282 DefineStd(Builder, "unix", Opts); 283 } 284 public: 285 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 286 : OSTargetInfo<Target>(Triple) { 287 this->UserLabelPrefix = ""; 288 289 switch (Triple.getArch()) { 290 default: 291 case llvm::Triple::x86: 292 case llvm::Triple::x86_64: 293 this->MCountName = ".mcount"; 294 break; 295 } 296 } 297 }; 298 299 // FreeBSD Target 300 template<typename Target> 301 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 302 protected: 303 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 304 MacroBuilder &Builder) const override { 305 // FreeBSD defines; list based off of gcc output 306 307 unsigned Release = Triple.getOSMajorVersion(); 308 if (Release == 0U) 309 Release = 8; 310 311 Builder.defineMacro("__FreeBSD__", Twine(Release)); 312 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 313 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 314 DefineStd(Builder, "unix", Opts); 315 Builder.defineMacro("__ELF__"); 316 317 // On FreeBSD, wchar_t contains the number of the code point as 318 // used by the character set of the locale. These character sets are 319 // not necessarily a superset of ASCII. 320 // 321 // FIXME: This is wrong; the macro refers to the numerical values 322 // of wchar_t *literals*, which are not locale-dependent. However, 323 // FreeBSD systems apparently depend on us getting this wrong, and 324 // setting this to 1 is conforming even if all the basic source 325 // character literals have the same encoding as char and wchar_t. 326 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 327 } 328 public: 329 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 330 this->UserLabelPrefix = ""; 331 332 switch (Triple.getArch()) { 333 default: 334 case llvm::Triple::x86: 335 case llvm::Triple::x86_64: 336 this->MCountName = ".mcount"; 337 break; 338 case llvm::Triple::mips: 339 case llvm::Triple::mipsel: 340 case llvm::Triple::ppc: 341 case llvm::Triple::ppc64: 342 case llvm::Triple::ppc64le: 343 this->MCountName = "_mcount"; 344 break; 345 case llvm::Triple::arm: 346 this->MCountName = "__mcount"; 347 break; 348 } 349 } 350 }; 351 352 // GNU/kFreeBSD Target 353 template<typename Target> 354 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 355 protected: 356 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 357 MacroBuilder &Builder) const override { 358 // GNU/kFreeBSD defines; list based off of gcc output 359 360 DefineStd(Builder, "unix", Opts); 361 Builder.defineMacro("__FreeBSD_kernel__"); 362 Builder.defineMacro("__GLIBC__"); 363 Builder.defineMacro("__ELF__"); 364 if (Opts.POSIXThreads) 365 Builder.defineMacro("_REENTRANT"); 366 if (Opts.CPlusPlus) 367 Builder.defineMacro("_GNU_SOURCE"); 368 } 369 public: 370 KFreeBSDTargetInfo(const llvm::Triple &Triple) 371 : OSTargetInfo<Target>(Triple) { 372 this->UserLabelPrefix = ""; 373 } 374 }; 375 376 // Minix Target 377 template<typename Target> 378 class MinixTargetInfo : public OSTargetInfo<Target> { 379 protected: 380 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 381 MacroBuilder &Builder) const override { 382 // Minix defines 383 384 Builder.defineMacro("__minix", "3"); 385 Builder.defineMacro("_EM_WSIZE", "4"); 386 Builder.defineMacro("_EM_PSIZE", "4"); 387 Builder.defineMacro("_EM_SSIZE", "2"); 388 Builder.defineMacro("_EM_LSIZE", "4"); 389 Builder.defineMacro("_EM_FSIZE", "4"); 390 Builder.defineMacro("_EM_DSIZE", "8"); 391 Builder.defineMacro("__ELF__"); 392 DefineStd(Builder, "unix", Opts); 393 } 394 public: 395 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 396 this->UserLabelPrefix = ""; 397 } 398 }; 399 400 // Linux target 401 template<typename Target> 402 class LinuxTargetInfo : public OSTargetInfo<Target> { 403 protected: 404 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 405 MacroBuilder &Builder) const override { 406 // Linux defines; list based off of gcc output 407 DefineStd(Builder, "unix", Opts); 408 DefineStd(Builder, "linux", Opts); 409 Builder.defineMacro("__gnu_linux__"); 410 Builder.defineMacro("__ELF__"); 411 if (Triple.isAndroid()) { 412 Builder.defineMacro("__ANDROID__", "1"); 413 unsigned Maj, Min, Rev; 414 Triple.getEnvironmentVersion(Maj, Min, Rev); 415 this->PlatformName = "android"; 416 this->PlatformMinVersion = VersionTuple(Maj, Min, Rev); 417 } 418 if (Opts.POSIXThreads) 419 Builder.defineMacro("_REENTRANT"); 420 if (Opts.CPlusPlus) 421 Builder.defineMacro("_GNU_SOURCE"); 422 } 423 public: 424 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 425 this->UserLabelPrefix = ""; 426 this->WIntType = TargetInfo::UnsignedInt; 427 428 switch (Triple.getArch()) { 429 default: 430 break; 431 case llvm::Triple::ppc: 432 case llvm::Triple::ppc64: 433 case llvm::Triple::ppc64le: 434 this->MCountName = "_mcount"; 435 break; 436 } 437 } 438 439 const char *getStaticInitSectionSpecifier() const override { 440 return ".text.startup"; 441 } 442 }; 443 444 // NetBSD Target 445 template<typename Target> 446 class NetBSDTargetInfo : public OSTargetInfo<Target> { 447 protected: 448 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 449 MacroBuilder &Builder) const override { 450 // NetBSD defines; list based off of gcc output 451 Builder.defineMacro("__NetBSD__"); 452 Builder.defineMacro("__unix__"); 453 Builder.defineMacro("__ELF__"); 454 if (Opts.POSIXThreads) 455 Builder.defineMacro("_POSIX_THREADS"); 456 457 switch (Triple.getArch()) { 458 default: 459 break; 460 case llvm::Triple::arm: 461 case llvm::Triple::armeb: 462 case llvm::Triple::thumb: 463 case llvm::Triple::thumbeb: 464 Builder.defineMacro("__ARM_DWARF_EH__"); 465 break; 466 } 467 } 468 public: 469 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 470 this->UserLabelPrefix = ""; 471 this->MCountName = "_mcount"; 472 } 473 }; 474 475 // OpenBSD Target 476 template<typename Target> 477 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 478 protected: 479 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 480 MacroBuilder &Builder) const override { 481 // OpenBSD defines; list based off of gcc output 482 483 Builder.defineMacro("__OpenBSD__"); 484 DefineStd(Builder, "unix", Opts); 485 Builder.defineMacro("__ELF__"); 486 if (Opts.POSIXThreads) 487 Builder.defineMacro("_REENTRANT"); 488 } 489 public: 490 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 491 this->UserLabelPrefix = ""; 492 this->TLSSupported = false; 493 494 switch (Triple.getArch()) { 495 default: 496 case llvm::Triple::x86: 497 case llvm::Triple::x86_64: 498 case llvm::Triple::arm: 499 case llvm::Triple::sparc: 500 this->MCountName = "__mcount"; 501 break; 502 case llvm::Triple::mips64: 503 case llvm::Triple::mips64el: 504 case llvm::Triple::ppc: 505 case llvm::Triple::sparcv9: 506 this->MCountName = "_mcount"; 507 break; 508 } 509 } 510 }; 511 512 // Bitrig Target 513 template<typename Target> 514 class BitrigTargetInfo : public OSTargetInfo<Target> { 515 protected: 516 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 517 MacroBuilder &Builder) const override { 518 // Bitrig defines; list based off of gcc output 519 520 Builder.defineMacro("__Bitrig__"); 521 DefineStd(Builder, "unix", Opts); 522 Builder.defineMacro("__ELF__"); 523 if (Opts.POSIXThreads) 524 Builder.defineMacro("_REENTRANT"); 525 526 switch (Triple.getArch()) { 527 default: 528 break; 529 case llvm::Triple::arm: 530 case llvm::Triple::armeb: 531 case llvm::Triple::thumb: 532 case llvm::Triple::thumbeb: 533 Builder.defineMacro("__ARM_DWARF_EH__"); 534 break; 535 } 536 } 537 public: 538 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 539 this->UserLabelPrefix = ""; 540 this->MCountName = "__mcount"; 541 } 542 }; 543 544 // PSP Target 545 template<typename Target> 546 class PSPTargetInfo : public OSTargetInfo<Target> { 547 protected: 548 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 549 MacroBuilder &Builder) const override { 550 // PSP defines; list based on the output of the pspdev gcc toolchain. 551 Builder.defineMacro("PSP"); 552 Builder.defineMacro("_PSP"); 553 Builder.defineMacro("__psp__"); 554 Builder.defineMacro("__ELF__"); 555 } 556 public: 557 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 558 this->UserLabelPrefix = ""; 559 } 560 }; 561 562 // PS3 PPU Target 563 template<typename Target> 564 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 565 protected: 566 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 567 MacroBuilder &Builder) const override { 568 // PS3 PPU defines. 569 Builder.defineMacro("__PPC__"); 570 Builder.defineMacro("__PPU__"); 571 Builder.defineMacro("__CELLOS_LV2__"); 572 Builder.defineMacro("__ELF__"); 573 Builder.defineMacro("__LP32__"); 574 Builder.defineMacro("_ARCH_PPC64"); 575 Builder.defineMacro("__powerpc64__"); 576 } 577 public: 578 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 579 this->UserLabelPrefix = ""; 580 this->LongWidth = this->LongAlign = 32; 581 this->PointerWidth = this->PointerAlign = 32; 582 this->IntMaxType = TargetInfo::SignedLongLong; 583 this->Int64Type = TargetInfo::SignedLongLong; 584 this->SizeType = TargetInfo::UnsignedInt; 585 this->DataLayoutString = "E-m:e-p:32:32-i64:64-n32:64"; 586 } 587 }; 588 589 template <typename Target> 590 class PS4OSTargetInfo : public OSTargetInfo<Target> { 591 protected: 592 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 593 MacroBuilder &Builder) const override { 594 Builder.defineMacro("__FreeBSD__", "9"); 595 Builder.defineMacro("__FreeBSD_cc_version", "900001"); 596 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 597 DefineStd(Builder, "unix", Opts); 598 Builder.defineMacro("__ELF__"); 599 Builder.defineMacro("__PS4__"); 600 } 601 public: 602 PS4OSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 603 this->WCharType = this->UnsignedShort; 604 605 // On PS4, TLS variable cannot be aligned to more than 32 bytes (256 bits). 606 this->MaxTLSAlign = 256; 607 this->UserLabelPrefix = ""; 608 609 // On PS4, do not honor explicit bit field alignment, 610 // as in "__attribute__((aligned(2))) int b : 1;". 611 this->UseExplicitBitFieldAlignment = false; 612 613 switch (Triple.getArch()) { 614 default: 615 case llvm::Triple::x86_64: 616 this->MCountName = ".mcount"; 617 break; 618 } 619 } 620 }; 621 622 // Solaris target 623 template<typename Target> 624 class SolarisTargetInfo : public OSTargetInfo<Target> { 625 protected: 626 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 627 MacroBuilder &Builder) const override { 628 DefineStd(Builder, "sun", Opts); 629 DefineStd(Builder, "unix", Opts); 630 Builder.defineMacro("__ELF__"); 631 Builder.defineMacro("__svr4__"); 632 Builder.defineMacro("__SVR4"); 633 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 634 // newer, but to 500 for everything else. feature_test.h has a check to 635 // ensure that you are not using C99 with an old version of X/Open or C89 636 // with a new version. 637 if (Opts.C99) 638 Builder.defineMacro("_XOPEN_SOURCE", "600"); 639 else 640 Builder.defineMacro("_XOPEN_SOURCE", "500"); 641 if (Opts.CPlusPlus) 642 Builder.defineMacro("__C99FEATURES__"); 643 Builder.defineMacro("_LARGEFILE_SOURCE"); 644 Builder.defineMacro("_LARGEFILE64_SOURCE"); 645 Builder.defineMacro("__EXTENSIONS__"); 646 Builder.defineMacro("_REENTRANT"); 647 } 648 public: 649 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 650 this->UserLabelPrefix = ""; 651 this->WCharType = this->SignedInt; 652 // FIXME: WIntType should be SignedLong 653 } 654 }; 655 656 // Windows target 657 template<typename Target> 658 class WindowsTargetInfo : public OSTargetInfo<Target> { 659 protected: 660 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 661 MacroBuilder &Builder) const override { 662 Builder.defineMacro("_WIN32"); 663 } 664 void getVisualStudioDefines(const LangOptions &Opts, 665 MacroBuilder &Builder) const { 666 if (Opts.CPlusPlus) { 667 if (Opts.RTTIData) 668 Builder.defineMacro("_CPPRTTI"); 669 670 if (Opts.CXXExceptions) 671 Builder.defineMacro("_CPPUNWIND"); 672 } 673 674 if (Opts.Bool) 675 Builder.defineMacro("__BOOL_DEFINED"); 676 677 if (!Opts.CharIsSigned) 678 Builder.defineMacro("_CHAR_UNSIGNED"); 679 680 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 681 // but it works for now. 682 if (Opts.POSIXThreads) 683 Builder.defineMacro("_MT"); 684 685 if (Opts.MSCompatibilityVersion) { 686 Builder.defineMacro("_MSC_VER", 687 Twine(Opts.MSCompatibilityVersion / 100000)); 688 Builder.defineMacro("_MSC_FULL_VER", Twine(Opts.MSCompatibilityVersion)); 689 // FIXME We cannot encode the revision information into 32-bits 690 Builder.defineMacro("_MSC_BUILD", Twine(1)); 691 692 if (Opts.CPlusPlus11 && Opts.isCompatibleWithMSVC(LangOptions::MSVC2015)) 693 Builder.defineMacro("_HAS_CHAR16_T_LANGUAGE_SUPPORT", Twine(1)); 694 } 695 696 if (Opts.MicrosoftExt) { 697 Builder.defineMacro("_MSC_EXTENSIONS"); 698 699 if (Opts.CPlusPlus11) { 700 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 701 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 702 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 703 } 704 } 705 706 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 707 } 708 709 public: 710 WindowsTargetInfo(const llvm::Triple &Triple) 711 : OSTargetInfo<Target>(Triple) {} 712 }; 713 714 template <typename Target> 715 class NaClTargetInfo : public OSTargetInfo<Target> { 716 protected: 717 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 718 MacroBuilder &Builder) const override { 719 if (Opts.POSIXThreads) 720 Builder.defineMacro("_REENTRANT"); 721 if (Opts.CPlusPlus) 722 Builder.defineMacro("_GNU_SOURCE"); 723 724 DefineStd(Builder, "unix", Opts); 725 Builder.defineMacro("__ELF__"); 726 Builder.defineMacro("__native_client__"); 727 } 728 729 public: 730 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 731 this->UserLabelPrefix = ""; 732 this->LongAlign = 32; 733 this->LongWidth = 32; 734 this->PointerAlign = 32; 735 this->PointerWidth = 32; 736 this->IntMaxType = TargetInfo::SignedLongLong; 737 this->Int64Type = TargetInfo::SignedLongLong; 738 this->DoubleAlign = 64; 739 this->LongDoubleWidth = 64; 740 this->LongDoubleAlign = 64; 741 this->LongLongWidth = 64; 742 this->LongLongAlign = 64; 743 this->SizeType = TargetInfo::UnsignedInt; 744 this->PtrDiffType = TargetInfo::SignedInt; 745 this->IntPtrType = TargetInfo::SignedInt; 746 // RegParmMax is inherited from the underlying architecture 747 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 748 if (Triple.getArch() == llvm::Triple::arm) { 749 // Handled in ARM's setABI(). 750 } else if (Triple.getArch() == llvm::Triple::x86) { 751 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32-S128"; 752 } else if (Triple.getArch() == llvm::Triple::x86_64) { 753 this->DataLayoutString = "e-m:e-p:32:32-i64:64-n8:16:32:64-S128"; 754 } else if (Triple.getArch() == llvm::Triple::mipsel) { 755 // Handled on mips' setDataLayoutString. 756 } else { 757 assert(Triple.getArch() == llvm::Triple::le32); 758 this->DataLayoutString = "e-p:32:32-i64:64"; 759 } 760 } 761 }; 762 763 // WebAssembly target 764 template <typename Target> 765 class WebAssemblyOSTargetInfo : public OSTargetInfo<Target> { 766 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 767 MacroBuilder &Builder) const final { 768 // A common platform macro. 769 if (Opts.POSIXThreads) 770 Builder.defineMacro("_REENTRANT"); 771 // Follow g++ convention and predefine _GNU_SOURCE for C++. 772 if (Opts.CPlusPlus) 773 Builder.defineMacro("_GNU_SOURCE"); 774 } 775 776 // As an optimization, group static init code together in a section. 777 const char *getStaticInitSectionSpecifier() const final { 778 return ".text.__startup"; 779 } 780 781 public: 782 explicit WebAssemblyOSTargetInfo(const llvm::Triple &Triple) 783 : OSTargetInfo<Target>(Triple) { 784 this->MCountName = "__mcount"; 785 this->UserLabelPrefix = ""; 786 this->TheCXXABI.set(TargetCXXABI::WebAssembly); 787 } 788 }; 789 790 //===----------------------------------------------------------------------===// 791 // Specific target implementations. 792 //===----------------------------------------------------------------------===// 793 794 // PPC abstract base class 795 class PPCTargetInfo : public TargetInfo { 796 static const Builtin::Info BuiltinInfo[]; 797 static const char * const GCCRegNames[]; 798 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 799 std::string CPU; 800 801 // Target cpu features. 802 bool HasVSX; 803 bool HasP8Vector; 804 bool HasP8Crypto; 805 bool HasDirectMove; 806 bool HasQPX; 807 bool HasHTM; 808 bool HasBPERMD; 809 bool HasExtDiv; 810 811 protected: 812 std::string ABI; 813 814 public: 815 PPCTargetInfo(const llvm::Triple &Triple) 816 : TargetInfo(Triple), HasVSX(false), HasP8Vector(false), 817 HasP8Crypto(false), HasDirectMove(false), HasQPX(false), HasHTM(false), 818 HasBPERMD(false), HasExtDiv(false) { 819 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 820 SimdDefaultAlign = 128; 821 LongDoubleWidth = LongDoubleAlign = 128; 822 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 823 } 824 825 /// \brief Flags for architecture specific defines. 826 typedef enum { 827 ArchDefineNone = 0, 828 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 829 ArchDefinePpcgr = 1 << 1, 830 ArchDefinePpcsq = 1 << 2, 831 ArchDefine440 = 1 << 3, 832 ArchDefine603 = 1 << 4, 833 ArchDefine604 = 1 << 5, 834 ArchDefinePwr4 = 1 << 6, 835 ArchDefinePwr5 = 1 << 7, 836 ArchDefinePwr5x = 1 << 8, 837 ArchDefinePwr6 = 1 << 9, 838 ArchDefinePwr6x = 1 << 10, 839 ArchDefinePwr7 = 1 << 11, 840 ArchDefinePwr8 = 1 << 12, 841 ArchDefineA2 = 1 << 13, 842 ArchDefineA2q = 1 << 14 843 } ArchDefineTypes; 844 845 // Note: GCC recognizes the following additional cpus: 846 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 847 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 848 // titan, rs64. 849 bool setCPU(const std::string &Name) override { 850 bool CPUKnown = llvm::StringSwitch<bool>(Name) 851 .Case("generic", true) 852 .Case("440", true) 853 .Case("450", true) 854 .Case("601", true) 855 .Case("602", true) 856 .Case("603", true) 857 .Case("603e", true) 858 .Case("603ev", true) 859 .Case("604", true) 860 .Case("604e", true) 861 .Case("620", true) 862 .Case("630", true) 863 .Case("g3", true) 864 .Case("7400", true) 865 .Case("g4", true) 866 .Case("7450", true) 867 .Case("g4+", true) 868 .Case("750", true) 869 .Case("970", true) 870 .Case("g5", true) 871 .Case("a2", true) 872 .Case("a2q", true) 873 .Case("e500mc", true) 874 .Case("e5500", true) 875 .Case("power3", true) 876 .Case("pwr3", true) 877 .Case("power4", true) 878 .Case("pwr4", true) 879 .Case("power5", true) 880 .Case("pwr5", true) 881 .Case("power5x", true) 882 .Case("pwr5x", true) 883 .Case("power6", true) 884 .Case("pwr6", true) 885 .Case("power6x", true) 886 .Case("pwr6x", true) 887 .Case("power7", true) 888 .Case("pwr7", true) 889 .Case("power8", true) 890 .Case("pwr8", true) 891 .Case("powerpc", true) 892 .Case("ppc", true) 893 .Case("powerpc64", true) 894 .Case("ppc64", true) 895 .Case("powerpc64le", true) 896 .Case("ppc64le", true) 897 .Default(false); 898 899 if (CPUKnown) 900 CPU = Name; 901 902 return CPUKnown; 903 } 904 905 906 StringRef getABI() const override { return ABI; } 907 908 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 909 return llvm::makeArrayRef(BuiltinInfo, 910 clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin); 911 } 912 913 bool isCLZForZeroUndef() const override { return false; } 914 915 void getTargetDefines(const LangOptions &Opts, 916 MacroBuilder &Builder) const override; 917 918 bool 919 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 920 StringRef CPU, 921 const std::vector<std::string> &FeaturesVec) const override; 922 923 bool handleTargetFeatures(std::vector<std::string> &Features, 924 DiagnosticsEngine &Diags) override; 925 bool hasFeature(StringRef Feature) const override; 926 void setFeatureEnabled(llvm::StringMap<bool> &Features, StringRef Name, 927 bool Enabled) const override; 928 929 ArrayRef<const char *> getGCCRegNames() const override; 930 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 931 bool validateAsmConstraint(const char *&Name, 932 TargetInfo::ConstraintInfo &Info) const override { 933 switch (*Name) { 934 default: return false; 935 case 'O': // Zero 936 break; 937 case 'b': // Base register 938 case 'f': // Floating point register 939 Info.setAllowsRegister(); 940 break; 941 // FIXME: The following are added to allow parsing. 942 // I just took a guess at what the actions should be. 943 // Also, is more specific checking needed? I.e. specific registers? 944 case 'd': // Floating point register (containing 64-bit value) 945 case 'v': // Altivec vector register 946 Info.setAllowsRegister(); 947 break; 948 case 'w': 949 switch (Name[1]) { 950 case 'd':// VSX vector register to hold vector double data 951 case 'f':// VSX vector register to hold vector float data 952 case 's':// VSX vector register to hold scalar float data 953 case 'a':// Any VSX register 954 case 'c':// An individual CR bit 955 break; 956 default: 957 return false; 958 } 959 Info.setAllowsRegister(); 960 Name++; // Skip over 'w'. 961 break; 962 case 'h': // `MQ', `CTR', or `LINK' register 963 case 'q': // `MQ' register 964 case 'c': // `CTR' register 965 case 'l': // `LINK' register 966 case 'x': // `CR' register (condition register) number 0 967 case 'y': // `CR' register (condition register) 968 case 'z': // `XER[CA]' carry bit (part of the XER register) 969 Info.setAllowsRegister(); 970 break; 971 case 'I': // Signed 16-bit constant 972 case 'J': // Unsigned 16-bit constant shifted left 16 bits 973 // (use `L' instead for SImode constants) 974 case 'K': // Unsigned 16-bit constant 975 case 'L': // Signed 16-bit constant shifted left 16 bits 976 case 'M': // Constant larger than 31 977 case 'N': // Exact power of 2 978 case 'P': // Constant whose negation is a signed 16-bit constant 979 case 'G': // Floating point constant that can be loaded into a 980 // register with one instruction per word 981 case 'H': // Integer/Floating point constant that can be loaded 982 // into a register using three instructions 983 break; 984 case 'm': // Memory operand. Note that on PowerPC targets, m can 985 // include addresses that update the base register. It 986 // is therefore only safe to use `m' in an asm statement 987 // if that asm statement accesses the operand exactly once. 988 // The asm statement must also use `%U<opno>' as a 989 // placeholder for the "update" flag in the corresponding 990 // load or store instruction. For example: 991 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 992 // is correct but: 993 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 994 // is not. Use es rather than m if you don't want the base 995 // register to be updated. 996 case 'e': 997 if (Name[1] != 's') 998 return false; 999 // es: A "stable" memory operand; that is, one which does not 1000 // include any automodification of the base register. Unlike 1001 // `m', this constraint can be used in asm statements that 1002 // might access the operand several times, or that might not 1003 // access it at all. 1004 Info.setAllowsMemory(); 1005 Name++; // Skip over 'e'. 1006 break; 1007 case 'Q': // Memory operand that is an offset from a register (it is 1008 // usually better to use `m' or `es' in asm statements) 1009 case 'Z': // Memory operand that is an indexed or indirect from a 1010 // register (it is usually better to use `m' or `es' in 1011 // asm statements) 1012 Info.setAllowsMemory(); 1013 Info.setAllowsRegister(); 1014 break; 1015 case 'R': // AIX TOC entry 1016 case 'a': // Address operand that is an indexed or indirect from a 1017 // register (`p' is preferable for asm statements) 1018 case 'S': // Constant suitable as a 64-bit mask operand 1019 case 'T': // Constant suitable as a 32-bit mask operand 1020 case 'U': // System V Release 4 small data area reference 1021 case 't': // AND masks that can be performed by two rldic{l, r} 1022 // instructions 1023 case 'W': // Vector constant that does not require memory 1024 case 'j': // Vector constant that is all zeros. 1025 break; 1026 // End FIXME. 1027 } 1028 return true; 1029 } 1030 std::string convertConstraint(const char *&Constraint) const override { 1031 std::string R; 1032 switch (*Constraint) { 1033 case 'e': 1034 case 'w': 1035 // Two-character constraint; add "^" hint for later parsing. 1036 R = std::string("^") + std::string(Constraint, 2); 1037 Constraint++; 1038 break; 1039 default: 1040 return TargetInfo::convertConstraint(Constraint); 1041 } 1042 return R; 1043 } 1044 const char *getClobbers() const override { 1045 return ""; 1046 } 1047 int getEHDataRegisterNumber(unsigned RegNo) const override { 1048 if (RegNo == 0) return 3; 1049 if (RegNo == 1) return 4; 1050 return -1; 1051 } 1052 1053 bool hasSjLjLowering() const override { 1054 return true; 1055 } 1056 1057 bool useFloat128ManglingForLongDouble() const override { 1058 return LongDoubleWidth == 128 && 1059 LongDoubleFormat == &llvm::APFloat::PPCDoubleDouble && 1060 getTriple().isOSBinFormatELF(); 1061 } 1062 }; 1063 1064 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 1065 #define BUILTIN(ID, TYPE, ATTRS) \ 1066 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1067 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1068 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1069 #include "clang/Basic/BuiltinsPPC.def" 1070 }; 1071 1072 /// handleTargetFeatures - Perform initialization based on the user 1073 /// configured set of features. 1074 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 1075 DiagnosticsEngine &Diags) { 1076 for (const auto &Feature : Features) { 1077 if (Feature == "+vsx") { 1078 HasVSX = true; 1079 } else if (Feature == "+bpermd") { 1080 HasBPERMD = true; 1081 } else if (Feature == "+extdiv") { 1082 HasExtDiv = true; 1083 } else if (Feature == "+power8-vector") { 1084 HasP8Vector = true; 1085 } else if (Feature == "+crypto") { 1086 HasP8Crypto = true; 1087 } else if (Feature == "+direct-move") { 1088 HasDirectMove = true; 1089 } else if (Feature == "+qpx") { 1090 HasQPX = true; 1091 } else if (Feature == "+htm") { 1092 HasHTM = true; 1093 } 1094 // TODO: Finish this list and add an assert that we've handled them 1095 // all. 1096 } 1097 1098 return true; 1099 } 1100 1101 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 1102 /// #defines that are not tied to a specific subtarget. 1103 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 1104 MacroBuilder &Builder) const { 1105 // Target identification. 1106 Builder.defineMacro("__ppc__"); 1107 Builder.defineMacro("__PPC__"); 1108 Builder.defineMacro("_ARCH_PPC"); 1109 Builder.defineMacro("__powerpc__"); 1110 Builder.defineMacro("__POWERPC__"); 1111 if (PointerWidth == 64) { 1112 Builder.defineMacro("_ARCH_PPC64"); 1113 Builder.defineMacro("__powerpc64__"); 1114 Builder.defineMacro("__ppc64__"); 1115 Builder.defineMacro("__PPC64__"); 1116 } 1117 1118 // Target properties. 1119 if (getTriple().getArch() == llvm::Triple::ppc64le) { 1120 Builder.defineMacro("_LITTLE_ENDIAN"); 1121 } else { 1122 if (getTriple().getOS() != llvm::Triple::NetBSD && 1123 getTriple().getOS() != llvm::Triple::OpenBSD) 1124 Builder.defineMacro("_BIG_ENDIAN"); 1125 } 1126 1127 // ABI options. 1128 if (ABI == "elfv1" || ABI == "elfv1-qpx") 1129 Builder.defineMacro("_CALL_ELF", "1"); 1130 if (ABI == "elfv2") 1131 Builder.defineMacro("_CALL_ELF", "2"); 1132 1133 // Subtarget options. 1134 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 1135 Builder.defineMacro("__REGISTER_PREFIX__", ""); 1136 1137 // FIXME: Should be controlled by command line option. 1138 if (LongDoubleWidth == 128) 1139 Builder.defineMacro("__LONG_DOUBLE_128__"); 1140 1141 if (Opts.AltiVec) { 1142 Builder.defineMacro("__VEC__", "10206"); 1143 Builder.defineMacro("__ALTIVEC__"); 1144 } 1145 1146 // CPU identification. 1147 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 1148 .Case("440", ArchDefineName) 1149 .Case("450", ArchDefineName | ArchDefine440) 1150 .Case("601", ArchDefineName) 1151 .Case("602", ArchDefineName | ArchDefinePpcgr) 1152 .Case("603", ArchDefineName | ArchDefinePpcgr) 1153 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1154 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 1155 .Case("604", ArchDefineName | ArchDefinePpcgr) 1156 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 1157 .Case("620", ArchDefineName | ArchDefinePpcgr) 1158 .Case("630", ArchDefineName | ArchDefinePpcgr) 1159 .Case("7400", ArchDefineName | ArchDefinePpcgr) 1160 .Case("7450", ArchDefineName | ArchDefinePpcgr) 1161 .Case("750", ArchDefineName | ArchDefinePpcgr) 1162 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1163 | ArchDefinePpcsq) 1164 .Case("a2", ArchDefineA2) 1165 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 1166 .Case("pwr3", ArchDefinePpcgr) 1167 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 1168 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 1169 | ArchDefinePpcsq) 1170 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 1171 | ArchDefinePpcgr | ArchDefinePpcsq) 1172 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 1173 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1174 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 1175 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1176 | ArchDefinePpcsq) 1177 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 1178 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1179 | ArchDefinePpcgr | ArchDefinePpcsq) 1180 .Case("pwr8", ArchDefineName | ArchDefinePwr7 | ArchDefinePwr6x 1181 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1182 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1183 .Case("power3", ArchDefinePpcgr) 1184 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1185 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1186 | ArchDefinePpcsq) 1187 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1188 | ArchDefinePpcgr | ArchDefinePpcsq) 1189 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1190 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1191 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 1192 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 1193 | ArchDefinePpcsq) 1194 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1195 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1196 | ArchDefinePpcgr | ArchDefinePpcsq) 1197 .Case("power8", ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6x 1198 | ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 1199 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 1200 .Default(ArchDefineNone); 1201 1202 if (defs & ArchDefineName) 1203 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1204 if (defs & ArchDefinePpcgr) 1205 Builder.defineMacro("_ARCH_PPCGR"); 1206 if (defs & ArchDefinePpcsq) 1207 Builder.defineMacro("_ARCH_PPCSQ"); 1208 if (defs & ArchDefine440) 1209 Builder.defineMacro("_ARCH_440"); 1210 if (defs & ArchDefine603) 1211 Builder.defineMacro("_ARCH_603"); 1212 if (defs & ArchDefine604) 1213 Builder.defineMacro("_ARCH_604"); 1214 if (defs & ArchDefinePwr4) 1215 Builder.defineMacro("_ARCH_PWR4"); 1216 if (defs & ArchDefinePwr5) 1217 Builder.defineMacro("_ARCH_PWR5"); 1218 if (defs & ArchDefinePwr5x) 1219 Builder.defineMacro("_ARCH_PWR5X"); 1220 if (defs & ArchDefinePwr6) 1221 Builder.defineMacro("_ARCH_PWR6"); 1222 if (defs & ArchDefinePwr6x) 1223 Builder.defineMacro("_ARCH_PWR6X"); 1224 if (defs & ArchDefinePwr7) 1225 Builder.defineMacro("_ARCH_PWR7"); 1226 if (defs & ArchDefinePwr8) 1227 Builder.defineMacro("_ARCH_PWR8"); 1228 if (defs & ArchDefineA2) 1229 Builder.defineMacro("_ARCH_A2"); 1230 if (defs & ArchDefineA2q) { 1231 Builder.defineMacro("_ARCH_A2Q"); 1232 Builder.defineMacro("_ARCH_QP"); 1233 } 1234 1235 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1236 Builder.defineMacro("__bg__"); 1237 Builder.defineMacro("__THW_BLUEGENE__"); 1238 Builder.defineMacro("__bgq__"); 1239 Builder.defineMacro("__TOS_BGQ__"); 1240 } 1241 1242 if (HasVSX) 1243 Builder.defineMacro("__VSX__"); 1244 if (HasP8Vector) 1245 Builder.defineMacro("__POWER8_VECTOR__"); 1246 if (HasP8Crypto) 1247 Builder.defineMacro("__CRYPTO__"); 1248 if (HasHTM) 1249 Builder.defineMacro("__HTM__"); 1250 1251 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 1252 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 1253 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 1254 if (PointerWidth == 64) 1255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 1256 1257 // FIXME: The following are not yet generated here by Clang, but are 1258 // generated by GCC: 1259 // 1260 // _SOFT_FLOAT_ 1261 // __RECIP_PRECISION__ 1262 // __APPLE_ALTIVEC__ 1263 // __RECIP__ 1264 // __RECIPF__ 1265 // __RSQRTE__ 1266 // __RSQRTEF__ 1267 // _SOFT_DOUBLE_ 1268 // __NO_LWSYNC__ 1269 // __HAVE_BSWAP__ 1270 // __LONGDOUBLE128 1271 // __CMODEL_MEDIUM__ 1272 // __CMODEL_LARGE__ 1273 // _CALL_SYSV 1274 // _CALL_DARWIN 1275 // __NO_FPRS__ 1276 } 1277 1278 // Handle explicit options being passed to the compiler here: if we've 1279 // explicitly turned off vsx and turned on power8-vector or direct-move then 1280 // go ahead and error since the customer has expressed a somewhat incompatible 1281 // set of options. 1282 static bool ppcUserFeaturesCheck(DiagnosticsEngine &Diags, 1283 const std::vector<std::string> &FeaturesVec) { 1284 1285 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "-vsx") != 1286 FeaturesVec.end()) { 1287 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+power8-vector") != 1288 FeaturesVec.end()) { 1289 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mpower8-vector" 1290 << "-mno-vsx"; 1291 return false; 1292 } 1293 1294 if (std::find(FeaturesVec.begin(), FeaturesVec.end(), "+direct-move") != 1295 FeaturesVec.end()) { 1296 Diags.Report(diag::err_opt_not_valid_with_opt) << "-mdirect-move" 1297 << "-mno-vsx"; 1298 return false; 1299 } 1300 } 1301 1302 return true; 1303 } 1304 1305 bool PPCTargetInfo::initFeatureMap( 1306 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 1307 const std::vector<std::string> &FeaturesVec) const { 1308 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1309 .Case("7400", true) 1310 .Case("g4", true) 1311 .Case("7450", true) 1312 .Case("g4+", true) 1313 .Case("970", true) 1314 .Case("g5", true) 1315 .Case("pwr6", true) 1316 .Case("pwr7", true) 1317 .Case("pwr8", true) 1318 .Case("ppc64", true) 1319 .Case("ppc64le", true) 1320 .Default(false); 1321 1322 Features["qpx"] = (CPU == "a2q"); 1323 Features["crypto"] = llvm::StringSwitch<bool>(CPU) 1324 .Case("ppc64le", true) 1325 .Case("pwr8", true) 1326 .Default(false); 1327 Features["power8-vector"] = llvm::StringSwitch<bool>(CPU) 1328 .Case("ppc64le", true) 1329 .Case("pwr8", true) 1330 .Default(false); 1331 Features["bpermd"] = llvm::StringSwitch<bool>(CPU) 1332 .Case("ppc64le", true) 1333 .Case("pwr8", true) 1334 .Case("pwr7", true) 1335 .Default(false); 1336 Features["extdiv"] = llvm::StringSwitch<bool>(CPU) 1337 .Case("ppc64le", true) 1338 .Case("pwr8", true) 1339 .Case("pwr7", true) 1340 .Default(false); 1341 Features["direct-move"] = llvm::StringSwitch<bool>(CPU) 1342 .Case("ppc64le", true) 1343 .Case("pwr8", true) 1344 .Default(false); 1345 Features["vsx"] = llvm::StringSwitch<bool>(CPU) 1346 .Case("ppc64le", true) 1347 .Case("pwr8", true) 1348 .Case("pwr7", true) 1349 .Default(false); 1350 1351 if (!ppcUserFeaturesCheck(Diags, FeaturesVec)) 1352 return false; 1353 1354 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 1355 } 1356 1357 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1358 return llvm::StringSwitch<bool>(Feature) 1359 .Case("powerpc", true) 1360 .Case("vsx", HasVSX) 1361 .Case("power8-vector", HasP8Vector) 1362 .Case("crypto", HasP8Crypto) 1363 .Case("direct-move", HasDirectMove) 1364 .Case("qpx", HasQPX) 1365 .Case("htm", HasHTM) 1366 .Case("bpermd", HasBPERMD) 1367 .Case("extdiv", HasExtDiv) 1368 .Default(false); 1369 } 1370 1371 void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features, 1372 StringRef Name, bool Enabled) const { 1373 // If we're enabling direct-move or power8-vector go ahead and enable vsx 1374 // as well. Do the inverse if we're disabling vsx. We'll diagnose any user 1375 // incompatible options. 1376 if (Enabled) { 1377 if (Name == "vsx") { 1378 Features[Name] = true; 1379 } else if (Name == "direct-move") { 1380 Features[Name] = Features["vsx"] = true; 1381 } else if (Name == "power8-vector") { 1382 Features[Name] = Features["vsx"] = true; 1383 } else { 1384 Features[Name] = true; 1385 } 1386 } else { 1387 if (Name == "vsx") { 1388 Features[Name] = Features["direct-move"] = Features["power8-vector"] = 1389 false; 1390 } else { 1391 Features[Name] = false; 1392 } 1393 } 1394 } 1395 1396 const char * const PPCTargetInfo::GCCRegNames[] = { 1397 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1398 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1399 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1400 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1401 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1402 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1403 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1404 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1405 "mq", "lr", "ctr", "ap", 1406 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1407 "xer", 1408 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1409 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1410 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1411 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1412 "vrsave", "vscr", 1413 "spe_acc", "spefscr", 1414 "sfp" 1415 }; 1416 1417 ArrayRef<const char*> PPCTargetInfo::getGCCRegNames() const { 1418 return llvm::makeArrayRef(GCCRegNames); 1419 } 1420 1421 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1422 // While some of these aliases do map to different registers 1423 // they still share the same register name. 1424 { { "0" }, "r0" }, 1425 { { "1"}, "r1" }, 1426 { { "2" }, "r2" }, 1427 { { "3" }, "r3" }, 1428 { { "4" }, "r4" }, 1429 { { "5" }, "r5" }, 1430 { { "6" }, "r6" }, 1431 { { "7" }, "r7" }, 1432 { { "8" }, "r8" }, 1433 { { "9" }, "r9" }, 1434 { { "10" }, "r10" }, 1435 { { "11" }, "r11" }, 1436 { { "12" }, "r12" }, 1437 { { "13" }, "r13" }, 1438 { { "14" }, "r14" }, 1439 { { "15" }, "r15" }, 1440 { { "16" }, "r16" }, 1441 { { "17" }, "r17" }, 1442 { { "18" }, "r18" }, 1443 { { "19" }, "r19" }, 1444 { { "20" }, "r20" }, 1445 { { "21" }, "r21" }, 1446 { { "22" }, "r22" }, 1447 { { "23" }, "r23" }, 1448 { { "24" }, "r24" }, 1449 { { "25" }, "r25" }, 1450 { { "26" }, "r26" }, 1451 { { "27" }, "r27" }, 1452 { { "28" }, "r28" }, 1453 { { "29" }, "r29" }, 1454 { { "30" }, "r30" }, 1455 { { "31" }, "r31" }, 1456 { { "fr0" }, "f0" }, 1457 { { "fr1" }, "f1" }, 1458 { { "fr2" }, "f2" }, 1459 { { "fr3" }, "f3" }, 1460 { { "fr4" }, "f4" }, 1461 { { "fr5" }, "f5" }, 1462 { { "fr6" }, "f6" }, 1463 { { "fr7" }, "f7" }, 1464 { { "fr8" }, "f8" }, 1465 { { "fr9" }, "f9" }, 1466 { { "fr10" }, "f10" }, 1467 { { "fr11" }, "f11" }, 1468 { { "fr12" }, "f12" }, 1469 { { "fr13" }, "f13" }, 1470 { { "fr14" }, "f14" }, 1471 { { "fr15" }, "f15" }, 1472 { { "fr16" }, "f16" }, 1473 { { "fr17" }, "f17" }, 1474 { { "fr18" }, "f18" }, 1475 { { "fr19" }, "f19" }, 1476 { { "fr20" }, "f20" }, 1477 { { "fr21" }, "f21" }, 1478 { { "fr22" }, "f22" }, 1479 { { "fr23" }, "f23" }, 1480 { { "fr24" }, "f24" }, 1481 { { "fr25" }, "f25" }, 1482 { { "fr26" }, "f26" }, 1483 { { "fr27" }, "f27" }, 1484 { { "fr28" }, "f28" }, 1485 { { "fr29" }, "f29" }, 1486 { { "fr30" }, "f30" }, 1487 { { "fr31" }, "f31" }, 1488 { { "cc" }, "cr0" }, 1489 }; 1490 1491 ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const { 1492 return llvm::makeArrayRef(GCCRegAliases); 1493 } 1494 1495 class PPC32TargetInfo : public PPCTargetInfo { 1496 public: 1497 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1498 DataLayoutString = "E-m:e-p:32:32-i64:64-n32"; 1499 1500 switch (getTriple().getOS()) { 1501 case llvm::Triple::Linux: 1502 case llvm::Triple::FreeBSD: 1503 case llvm::Triple::NetBSD: 1504 SizeType = UnsignedInt; 1505 PtrDiffType = SignedInt; 1506 IntPtrType = SignedInt; 1507 break; 1508 default: 1509 break; 1510 } 1511 1512 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1513 LongDoubleWidth = LongDoubleAlign = 64; 1514 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1515 } 1516 1517 // PPC32 supports atomics up to 4 bytes. 1518 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1519 } 1520 1521 BuiltinVaListKind getBuiltinVaListKind() const override { 1522 // This is the ELF definition, and is overridden by the Darwin sub-target 1523 return TargetInfo::PowerABIBuiltinVaList; 1524 } 1525 }; 1526 1527 // Note: ABI differences may eventually require us to have a separate 1528 // TargetInfo for little endian. 1529 class PPC64TargetInfo : public PPCTargetInfo { 1530 public: 1531 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1532 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1533 IntMaxType = SignedLong; 1534 Int64Type = SignedLong; 1535 1536 if ((Triple.getArch() == llvm::Triple::ppc64le)) { 1537 DataLayoutString = "e-m:e-i64:64-n32:64"; 1538 ABI = "elfv2"; 1539 } else { 1540 DataLayoutString = "E-m:e-i64:64-n32:64"; 1541 ABI = "elfv1"; 1542 } 1543 1544 switch (getTriple().getOS()) { 1545 case llvm::Triple::FreeBSD: 1546 LongDoubleWidth = LongDoubleAlign = 64; 1547 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1548 break; 1549 case llvm::Triple::NetBSD: 1550 IntMaxType = SignedLongLong; 1551 Int64Type = SignedLongLong; 1552 break; 1553 default: 1554 break; 1555 } 1556 1557 // PPC64 supports atomics up to 8 bytes. 1558 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1559 } 1560 BuiltinVaListKind getBuiltinVaListKind() const override { 1561 return TargetInfo::CharPtrBuiltinVaList; 1562 } 1563 // PPC64 Linux-specific ABI options. 1564 bool setABI(const std::string &Name) override { 1565 if (Name == "elfv1" || Name == "elfv1-qpx" || Name == "elfv2") { 1566 ABI = Name; 1567 return true; 1568 } 1569 return false; 1570 } 1571 }; 1572 1573 class DarwinPPC32TargetInfo : 1574 public DarwinTargetInfo<PPC32TargetInfo> { 1575 public: 1576 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1577 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1578 HasAlignMac68kSupport = true; 1579 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1580 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1581 LongLongAlign = 32; 1582 SuitableAlign = 128; 1583 DataLayoutString = "E-m:o-p:32:32-f64:32:64-n32"; 1584 } 1585 BuiltinVaListKind getBuiltinVaListKind() const override { 1586 return TargetInfo::CharPtrBuiltinVaList; 1587 } 1588 }; 1589 1590 class DarwinPPC64TargetInfo : 1591 public DarwinTargetInfo<PPC64TargetInfo> { 1592 public: 1593 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1594 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1595 HasAlignMac68kSupport = true; 1596 SuitableAlign = 128; 1597 DataLayoutString = "E-m:o-i64:64-n32:64"; 1598 } 1599 }; 1600 1601 static const unsigned NVPTXAddrSpaceMap[] = { 1602 1, // opencl_global 1603 3, // opencl_local 1604 4, // opencl_constant 1605 // FIXME: generic has to be added to the target 1606 0, // opencl_generic 1607 1, // cuda_device 1608 4, // cuda_constant 1609 3, // cuda_shared 1610 }; 1611 1612 class NVPTXTargetInfo : public TargetInfo { 1613 static const char *const GCCRegNames[]; 1614 static const Builtin::Info BuiltinInfo[]; 1615 1616 // The GPU profiles supported by the NVPTX backend 1617 enum GPUKind { 1618 GK_NONE, 1619 GK_SM20, 1620 GK_SM21, 1621 GK_SM30, 1622 GK_SM35, 1623 GK_SM37, 1624 } GPU; 1625 1626 public: 1627 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1628 BigEndian = false; 1629 TLSSupported = false; 1630 LongWidth = LongAlign = 64; 1631 AddrSpaceMap = &NVPTXAddrSpaceMap; 1632 UseAddrSpaceMapMangling = true; 1633 // Define available target features 1634 // These must be defined in sorted order! 1635 NoAsmVariants = true; 1636 // Set the default GPU to sm20 1637 GPU = GK_SM20; 1638 } 1639 void getTargetDefines(const LangOptions &Opts, 1640 MacroBuilder &Builder) const override { 1641 Builder.defineMacro("__PTX__"); 1642 Builder.defineMacro("__NVPTX__"); 1643 if (Opts.CUDAIsDevice) { 1644 // Set __CUDA_ARCH__ for the GPU specified. 1645 std::string CUDAArchCode; 1646 switch (GPU) { 1647 case GK_SM20: 1648 CUDAArchCode = "200"; 1649 break; 1650 case GK_SM21: 1651 CUDAArchCode = "210"; 1652 break; 1653 case GK_SM30: 1654 CUDAArchCode = "300"; 1655 break; 1656 case GK_SM35: 1657 CUDAArchCode = "350"; 1658 break; 1659 case GK_SM37: 1660 CUDAArchCode = "370"; 1661 break; 1662 default: 1663 llvm_unreachable("Unhandled target CPU"); 1664 } 1665 Builder.defineMacro("__CUDA_ARCH__", CUDAArchCode); 1666 } 1667 } 1668 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1669 return llvm::makeArrayRef(BuiltinInfo, 1670 clang::NVPTX::LastTSBuiltin - Builtin::FirstTSBuiltin); 1671 } 1672 bool hasFeature(StringRef Feature) const override { 1673 return Feature == "ptx" || Feature == "nvptx"; 1674 } 1675 1676 ArrayRef<const char *> getGCCRegNames() const override; 1677 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1678 // No aliases. 1679 return None; 1680 } 1681 bool validateAsmConstraint(const char *&Name, 1682 TargetInfo::ConstraintInfo &Info) const override { 1683 switch (*Name) { 1684 default: 1685 return false; 1686 case 'c': 1687 case 'h': 1688 case 'r': 1689 case 'l': 1690 case 'f': 1691 case 'd': 1692 Info.setAllowsRegister(); 1693 return true; 1694 } 1695 } 1696 const char *getClobbers() const override { 1697 // FIXME: Is this really right? 1698 return ""; 1699 } 1700 BuiltinVaListKind getBuiltinVaListKind() const override { 1701 // FIXME: implement 1702 return TargetInfo::CharPtrBuiltinVaList; 1703 } 1704 bool setCPU(const std::string &Name) override { 1705 GPU = llvm::StringSwitch<GPUKind>(Name) 1706 .Case("sm_20", GK_SM20) 1707 .Case("sm_21", GK_SM21) 1708 .Case("sm_30", GK_SM30) 1709 .Case("sm_35", GK_SM35) 1710 .Case("sm_37", GK_SM37) 1711 .Default(GK_NONE); 1712 1713 return GPU != GK_NONE; 1714 } 1715 }; 1716 1717 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1718 #define BUILTIN(ID, TYPE, ATTRS) \ 1719 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1720 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 1721 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 1722 #include "clang/Basic/BuiltinsNVPTX.def" 1723 }; 1724 1725 const char *const NVPTXTargetInfo::GCCRegNames[] = {"r0"}; 1726 1727 ArrayRef<const char *> NVPTXTargetInfo::getGCCRegNames() const { 1728 return llvm::makeArrayRef(GCCRegNames); 1729 } 1730 1731 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1732 public: 1733 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1734 LongWidth = LongAlign = 32; 1735 PointerWidth = PointerAlign = 32; 1736 SizeType = TargetInfo::UnsignedInt; 1737 PtrDiffType = TargetInfo::SignedInt; 1738 IntPtrType = TargetInfo::SignedInt; 1739 DataLayoutString = "e-p:32:32-i64:64-v16:16-v32:32-n16:32:64"; 1740 } 1741 }; 1742 1743 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1744 public: 1745 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1746 PointerWidth = PointerAlign = 64; 1747 SizeType = TargetInfo::UnsignedLong; 1748 PtrDiffType = TargetInfo::SignedLong; 1749 IntPtrType = TargetInfo::SignedLong; 1750 DataLayoutString = "e-i64:64-v16:16-v32:32-n16:32:64"; 1751 } 1752 }; 1753 1754 static const unsigned AMDGPUAddrSpaceMap[] = { 1755 1, // opencl_global 1756 3, // opencl_local 1757 2, // opencl_constant 1758 4, // opencl_generic 1759 1, // cuda_device 1760 2, // cuda_constant 1761 3 // cuda_shared 1762 }; 1763 1764 // If you edit the description strings, make sure you update 1765 // getPointerWidthV(). 1766 1767 static const char *const DataLayoutStringR600 = 1768 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1769 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1770 1771 static const char *const DataLayoutStringR600DoubleOps = 1772 "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1773 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1774 1775 static const char *const DataLayoutStringSI = 1776 "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64" 1777 "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" 1778 "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"; 1779 1780 class AMDGPUTargetInfo : public TargetInfo { 1781 static const Builtin::Info BuiltinInfo[]; 1782 static const char * const GCCRegNames[]; 1783 1784 /// \brief The GPU profiles supported by the AMDGPU target. 1785 enum GPUKind { 1786 GK_NONE, 1787 GK_R600, 1788 GK_R600_DOUBLE_OPS, 1789 GK_R700, 1790 GK_R700_DOUBLE_OPS, 1791 GK_EVERGREEN, 1792 GK_EVERGREEN_DOUBLE_OPS, 1793 GK_NORTHERN_ISLANDS, 1794 GK_CAYMAN, 1795 GK_SOUTHERN_ISLANDS, 1796 GK_SEA_ISLANDS, 1797 GK_VOLCANIC_ISLANDS 1798 } GPU; 1799 1800 bool hasFP64:1; 1801 bool hasFMAF:1; 1802 bool hasLDEXPF:1; 1803 1804 public: 1805 AMDGPUTargetInfo(const llvm::Triple &Triple) 1806 : TargetInfo(Triple) { 1807 1808 if (Triple.getArch() == llvm::Triple::amdgcn) { 1809 DataLayoutString = DataLayoutStringSI; 1810 GPU = GK_SOUTHERN_ISLANDS; 1811 hasFP64 = true; 1812 hasFMAF = true; 1813 hasLDEXPF = true; 1814 } else { 1815 DataLayoutString = DataLayoutStringR600; 1816 GPU = GK_R600; 1817 hasFP64 = false; 1818 hasFMAF = false; 1819 hasLDEXPF = false; 1820 } 1821 AddrSpaceMap = &AMDGPUAddrSpaceMap; 1822 UseAddrSpaceMapMangling = true; 1823 } 1824 1825 uint64_t getPointerWidthV(unsigned AddrSpace) const override { 1826 if (GPU <= GK_CAYMAN) 1827 return 32; 1828 1829 switch(AddrSpace) { 1830 default: 1831 return 64; 1832 case 0: 1833 case 3: 1834 case 5: 1835 return 32; 1836 } 1837 } 1838 1839 const char * getClobbers() const override { 1840 return ""; 1841 } 1842 1843 ArrayRef<const char *> getGCCRegNames() const override; 1844 1845 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 1846 return None; 1847 } 1848 1849 bool validateAsmConstraint(const char *&Name, 1850 TargetInfo::ConstraintInfo &Info) const override { 1851 switch (*Name) { 1852 default: break; 1853 case 'v': // vgpr 1854 case 's': // sgpr 1855 Info.setAllowsRegister(); 1856 return true; 1857 } 1858 return false; 1859 } 1860 1861 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 1862 return llvm::makeArrayRef(BuiltinInfo, 1863 clang::AMDGPU::LastTSBuiltin - Builtin::FirstTSBuiltin); 1864 } 1865 1866 void getTargetDefines(const LangOptions &Opts, 1867 MacroBuilder &Builder) const override { 1868 if (getTriple().getArch() == llvm::Triple::amdgcn) 1869 Builder.defineMacro("__AMDGCN__"); 1870 else 1871 Builder.defineMacro("__R600__"); 1872 1873 if (hasFMAF) 1874 Builder.defineMacro("__HAS_FMAF__"); 1875 if (hasLDEXPF) 1876 Builder.defineMacro("__HAS_LDEXPF__"); 1877 if (hasFP64 && Opts.OpenCL) 1878 Builder.defineMacro("cl_khr_fp64"); 1879 if (Opts.OpenCL) { 1880 if (GPU >= GK_NORTHERN_ISLANDS) { 1881 Builder.defineMacro("cl_khr_byte_addressable_store"); 1882 Builder.defineMacro("cl_khr_global_int32_base_atomics"); 1883 Builder.defineMacro("cl_khr_global_int32_extended_atomics"); 1884 Builder.defineMacro("cl_khr_local_int32_base_atomics"); 1885 Builder.defineMacro("cl_khr_local_int32_extended_atomics"); 1886 } 1887 } 1888 } 1889 1890 BuiltinVaListKind getBuiltinVaListKind() const override { 1891 return TargetInfo::CharPtrBuiltinVaList; 1892 } 1893 1894 bool setCPU(const std::string &Name) override { 1895 GPU = llvm::StringSwitch<GPUKind>(Name) 1896 .Case("r600" , GK_R600) 1897 .Case("rv610", GK_R600) 1898 .Case("rv620", GK_R600) 1899 .Case("rv630", GK_R600) 1900 .Case("rv635", GK_R600) 1901 .Case("rs780", GK_R600) 1902 .Case("rs880", GK_R600) 1903 .Case("rv670", GK_R600_DOUBLE_OPS) 1904 .Case("rv710", GK_R700) 1905 .Case("rv730", GK_R700) 1906 .Case("rv740", GK_R700_DOUBLE_OPS) 1907 .Case("rv770", GK_R700_DOUBLE_OPS) 1908 .Case("palm", GK_EVERGREEN) 1909 .Case("cedar", GK_EVERGREEN) 1910 .Case("sumo", GK_EVERGREEN) 1911 .Case("sumo2", GK_EVERGREEN) 1912 .Case("redwood", GK_EVERGREEN) 1913 .Case("juniper", GK_EVERGREEN) 1914 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1915 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1916 .Case("barts", GK_NORTHERN_ISLANDS) 1917 .Case("turks", GK_NORTHERN_ISLANDS) 1918 .Case("caicos", GK_NORTHERN_ISLANDS) 1919 .Case("cayman", GK_CAYMAN) 1920 .Case("aruba", GK_CAYMAN) 1921 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1922 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1923 .Case("verde", GK_SOUTHERN_ISLANDS) 1924 .Case("oland", GK_SOUTHERN_ISLANDS) 1925 .Case("hainan", GK_SOUTHERN_ISLANDS) 1926 .Case("bonaire", GK_SEA_ISLANDS) 1927 .Case("kabini", GK_SEA_ISLANDS) 1928 .Case("kaveri", GK_SEA_ISLANDS) 1929 .Case("hawaii", GK_SEA_ISLANDS) 1930 .Case("mullins", GK_SEA_ISLANDS) 1931 .Case("tonga", GK_VOLCANIC_ISLANDS) 1932 .Case("iceland", GK_VOLCANIC_ISLANDS) 1933 .Case("carrizo", GK_VOLCANIC_ISLANDS) 1934 .Default(GK_NONE); 1935 1936 if (GPU == GK_NONE) { 1937 return false; 1938 } 1939 1940 // Set the correct data layout 1941 switch (GPU) { 1942 case GK_NONE: 1943 case GK_R600: 1944 case GK_R700: 1945 case GK_EVERGREEN: 1946 case GK_NORTHERN_ISLANDS: 1947 DataLayoutString = DataLayoutStringR600; 1948 hasFP64 = false; 1949 hasFMAF = false; 1950 hasLDEXPF = false; 1951 break; 1952 case GK_R600_DOUBLE_OPS: 1953 case GK_R700_DOUBLE_OPS: 1954 case GK_EVERGREEN_DOUBLE_OPS: 1955 case GK_CAYMAN: 1956 DataLayoutString = DataLayoutStringR600DoubleOps; 1957 hasFP64 = true; 1958 hasFMAF = true; 1959 hasLDEXPF = false; 1960 break; 1961 case GK_SOUTHERN_ISLANDS: 1962 case GK_SEA_ISLANDS: 1963 case GK_VOLCANIC_ISLANDS: 1964 DataLayoutString = DataLayoutStringSI; 1965 hasFP64 = true; 1966 hasFMAF = true; 1967 hasLDEXPF = true; 1968 break; 1969 } 1970 1971 return true; 1972 } 1973 }; 1974 1975 const Builtin::Info AMDGPUTargetInfo::BuiltinInfo[] = { 1976 #define BUILTIN(ID, TYPE, ATTRS) \ 1977 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 1978 #include "clang/Basic/BuiltinsAMDGPU.def" 1979 }; 1980 const char * const AMDGPUTargetInfo::GCCRegNames[] = { 1981 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1982 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1983 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1984 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1985 "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", 1986 "v40", "v41", "v42", "v43", "v44", "v45", "v46", "v47", 1987 "v48", "v49", "v50", "v51", "v52", "v53", "v54", "v55", 1988 "v56", "v57", "v58", "v59", "v60", "v61", "v62", "v63", 1989 "v64", "v65", "v66", "v67", "v68", "v69", "v70", "v71", 1990 "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", 1991 "v80", "v81", "v82", "v83", "v84", "v85", "v86", "v87", 1992 "v88", "v89", "v90", "v91", "v92", "v93", "v94", "v95", 1993 "v96", "v97", "v98", "v99", "v100", "v101", "v102", "v103", 1994 "v104", "v105", "v106", "v107", "v108", "v109", "v110", "v111", 1995 "v112", "v113", "v114", "v115", "v116", "v117", "v118", "v119", 1996 "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", 1997 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", 1998 "v136", "v137", "v138", "v139", "v140", "v141", "v142", "v143", 1999 "v144", "v145", "v146", "v147", "v148", "v149", "v150", "v151", 2000 "v152", "v153", "v154", "v155", "v156", "v157", "v158", "v159", 2001 "v160", "v161", "v162", "v163", "v164", "v165", "v166", "v167", 2002 "v168", "v169", "v170", "v171", "v172", "v173", "v174", "v175", 2003 "v176", "v177", "v178", "v179", "v180", "v181", "v182", "v183", 2004 "v184", "v185", "v186", "v187", "v188", "v189", "v190", "v191", 2005 "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", 2006 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", 2007 "v208", "v209", "v210", "v211", "v212", "v213", "v214", "v215", 2008 "v216", "v217", "v218", "v219", "v220", "v221", "v222", "v223", 2009 "v224", "v225", "v226", "v227", "v228", "v229", "v230", "v231", 2010 "v232", "v233", "v234", "v235", "v236", "v237", "v238", "v239", 2011 "v240", "v241", "v242", "v243", "v244", "v245", "v246", "v247", 2012 "v248", "v249", "v250", "v251", "v252", "v253", "v254", "v255", 2013 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 2014 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 2015 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 2016 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 2017 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", 2018 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47", 2019 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55", 2020 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63", 2021 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71", 2022 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", 2023 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87", 2024 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95", 2025 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103", 2026 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111", 2027 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119", 2028 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127" 2029 "exec", "vcc", "scc", "m0", "flat_scratch", "exec_lo", "exec_hi", 2030 "vcc_lo", "vcc_hi", "flat_scratch_lo", "flat_scratch_hi" 2031 }; 2032 2033 ArrayRef<const char *> AMDGPUTargetInfo::getGCCRegNames() const { 2034 return llvm::makeArrayRef(GCCRegNames); 2035 } 2036 2037 // Namespace for x86 abstract base class 2038 const Builtin::Info BuiltinInfo[] = { 2039 #define BUILTIN(ID, TYPE, ATTRS) \ 2040 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 2041 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 2042 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 2043 #define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) \ 2044 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, FEATURE }, 2045 #include "clang/Basic/BuiltinsX86.def" 2046 }; 2047 2048 static const char* const GCCRegNames[] = { 2049 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 2050 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 2051 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 2052 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 2053 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 2054 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 2055 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 2056 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 2057 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 2058 "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", 2059 "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", 2060 "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", 2061 "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", 2062 "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", 2063 "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", 2064 "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", 2065 "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", 2066 }; 2067 2068 const TargetInfo::AddlRegName AddlRegNames[] = { 2069 { { "al", "ah", "eax", "rax" }, 0 }, 2070 { { "bl", "bh", "ebx", "rbx" }, 3 }, 2071 { { "cl", "ch", "ecx", "rcx" }, 2 }, 2072 { { "dl", "dh", "edx", "rdx" }, 1 }, 2073 { { "esi", "rsi" }, 4 }, 2074 { { "edi", "rdi" }, 5 }, 2075 { { "esp", "rsp" }, 7 }, 2076 { { "ebp", "rbp" }, 6 }, 2077 { { "r8d", "r8w", "r8b" }, 38 }, 2078 { { "r9d", "r9w", "r9b" }, 39 }, 2079 { { "r10d", "r10w", "r10b" }, 40 }, 2080 { { "r11d", "r11w", "r11b" }, 41 }, 2081 { { "r12d", "r12w", "r12b" }, 42 }, 2082 { { "r13d", "r13w", "r13b" }, 43 }, 2083 { { "r14d", "r14w", "r14b" }, 44 }, 2084 { { "r15d", "r15w", "r15b" }, 45 }, 2085 }; 2086 2087 // X86 target abstract base class; x86-32 and x86-64 are very close, so 2088 // most of the implementation can be shared. 2089 class X86TargetInfo : public TargetInfo { 2090 enum X86SSEEnum { 2091 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 2092 } SSELevel = NoSSE; 2093 enum MMX3DNowEnum { 2094 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 2095 } MMX3DNowLevel = NoMMX3DNow; 2096 enum XOPEnum { 2097 NoXOP, 2098 SSE4A, 2099 FMA4, 2100 XOP 2101 } XOPLevel = NoXOP; 2102 2103 bool HasAES = false; 2104 bool HasPCLMUL = false; 2105 bool HasLZCNT = false; 2106 bool HasRDRND = false; 2107 bool HasFSGSBASE = false; 2108 bool HasBMI = false; 2109 bool HasBMI2 = false; 2110 bool HasPOPCNT = false; 2111 bool HasRTM = false; 2112 bool HasPRFCHW = false; 2113 bool HasRDSEED = false; 2114 bool HasADX = false; 2115 bool HasTBM = false; 2116 bool HasFMA = false; 2117 bool HasF16C = false; 2118 bool HasAVX512CD = false; 2119 bool HasAVX512ER = false; 2120 bool HasAVX512PF = false; 2121 bool HasAVX512DQ = false; 2122 bool HasAVX512BW = false; 2123 bool HasAVX512VL = false; 2124 bool HasAVX512VBMI = false; 2125 bool HasAVX512IFMA = false; 2126 bool HasSHA = false; 2127 bool HasMPX = false; 2128 bool HasSGX = false; 2129 bool HasCX16 = false; 2130 bool HasFXSR = false; 2131 bool HasXSAVE = false; 2132 bool HasXSAVEOPT = false; 2133 bool HasXSAVEC = false; 2134 bool HasXSAVES = false; 2135 bool HasPKU = false; 2136 bool HasCLFLUSHOPT = false; 2137 bool HasPCOMMIT = false; 2138 bool HasCLWB = false; 2139 bool HasUMIP = false; 2140 bool HasMOVBE = false; 2141 bool HasPREFETCHWT1 = false; 2142 2143 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 2144 /// 2145 /// Each enumeration represents a particular CPU supported by Clang. These 2146 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 2147 enum CPUKind { 2148 CK_Generic, 2149 2150 /// \name i386 2151 /// i386-generation processors. 2152 //@{ 2153 CK_i386, 2154 //@} 2155 2156 /// \name i486 2157 /// i486-generation processors. 2158 //@{ 2159 CK_i486, 2160 CK_WinChipC6, 2161 CK_WinChip2, 2162 CK_C3, 2163 //@} 2164 2165 /// \name i586 2166 /// i586-generation processors, P5 microarchitecture based. 2167 //@{ 2168 CK_i586, 2169 CK_Pentium, 2170 CK_PentiumMMX, 2171 //@} 2172 2173 /// \name i686 2174 /// i686-generation processors, P6 / Pentium M microarchitecture based. 2175 //@{ 2176 CK_i686, 2177 CK_PentiumPro, 2178 CK_Pentium2, 2179 CK_Pentium3, 2180 CK_Pentium3M, 2181 CK_PentiumM, 2182 CK_C3_2, 2183 2184 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 2185 /// Clang however has some logic to suport this. 2186 // FIXME: Warn, deprecate, and potentially remove this. 2187 CK_Yonah, 2188 //@} 2189 2190 /// \name Netburst 2191 /// Netburst microarchitecture based processors. 2192 //@{ 2193 CK_Pentium4, 2194 CK_Pentium4M, 2195 CK_Prescott, 2196 CK_Nocona, 2197 //@} 2198 2199 /// \name Core 2200 /// Core microarchitecture based processors. 2201 //@{ 2202 CK_Core2, 2203 2204 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 2205 /// codename which GCC no longer accepts as an option to -march, but Clang 2206 /// has some logic for recognizing it. 2207 // FIXME: Warn, deprecate, and potentially remove this. 2208 CK_Penryn, 2209 //@} 2210 2211 /// \name Atom 2212 /// Atom processors 2213 //@{ 2214 CK_Bonnell, 2215 CK_Silvermont, 2216 //@} 2217 2218 /// \name Nehalem 2219 /// Nehalem microarchitecture based processors. 2220 CK_Nehalem, 2221 2222 /// \name Westmere 2223 /// Westmere microarchitecture based processors. 2224 CK_Westmere, 2225 2226 /// \name Sandy Bridge 2227 /// Sandy Bridge microarchitecture based processors. 2228 CK_SandyBridge, 2229 2230 /// \name Ivy Bridge 2231 /// Ivy Bridge microarchitecture based processors. 2232 CK_IvyBridge, 2233 2234 /// \name Haswell 2235 /// Haswell microarchitecture based processors. 2236 CK_Haswell, 2237 2238 /// \name Broadwell 2239 /// Broadwell microarchitecture based processors. 2240 CK_Broadwell, 2241 2242 /// \name Skylake Client 2243 /// Skylake client microarchitecture based processors. 2244 CK_SkylakeClient, 2245 2246 /// \name Skylake Server 2247 /// Skylake server microarchitecture based processors. 2248 CK_SkylakeServer, 2249 2250 /// \name Cannonlake Client 2251 /// Cannonlake client microarchitecture based processors. 2252 CK_Cannonlake, 2253 2254 /// \name Knights Landing 2255 /// Knights Landing processor. 2256 CK_KNL, 2257 2258 /// \name K6 2259 /// K6 architecture processors. 2260 //@{ 2261 CK_K6, 2262 CK_K6_2, 2263 CK_K6_3, 2264 //@} 2265 2266 /// \name K7 2267 /// K7 architecture processors. 2268 //@{ 2269 CK_Athlon, 2270 CK_AthlonThunderbird, 2271 CK_Athlon4, 2272 CK_AthlonXP, 2273 CK_AthlonMP, 2274 //@} 2275 2276 /// \name K8 2277 /// K8 architecture processors. 2278 //@{ 2279 CK_Athlon64, 2280 CK_Athlon64SSE3, 2281 CK_AthlonFX, 2282 CK_K8, 2283 CK_K8SSE3, 2284 CK_Opteron, 2285 CK_OpteronSSE3, 2286 CK_AMDFAM10, 2287 //@} 2288 2289 /// \name Bobcat 2290 /// Bobcat architecture processors. 2291 //@{ 2292 CK_BTVER1, 2293 CK_BTVER2, 2294 //@} 2295 2296 /// \name Bulldozer 2297 /// Bulldozer architecture processors. 2298 //@{ 2299 CK_BDVER1, 2300 CK_BDVER2, 2301 CK_BDVER3, 2302 CK_BDVER4, 2303 //@} 2304 2305 /// This specification is deprecated and will be removed in the future. 2306 /// Users should prefer \see CK_K8. 2307 // FIXME: Warn on this when the CPU is set to it. 2308 //@{ 2309 CK_x86_64, 2310 //@} 2311 2312 /// \name Geode 2313 /// Geode processors. 2314 //@{ 2315 CK_Geode 2316 //@} 2317 } CPU = CK_Generic; 2318 2319 CPUKind getCPUKind(StringRef CPU) const { 2320 return llvm::StringSwitch<CPUKind>(CPU) 2321 .Case("i386", CK_i386) 2322 .Case("i486", CK_i486) 2323 .Case("winchip-c6", CK_WinChipC6) 2324 .Case("winchip2", CK_WinChip2) 2325 .Case("c3", CK_C3) 2326 .Case("i586", CK_i586) 2327 .Case("pentium", CK_Pentium) 2328 .Case("pentium-mmx", CK_PentiumMMX) 2329 .Case("i686", CK_i686) 2330 .Case("pentiumpro", CK_PentiumPro) 2331 .Case("pentium2", CK_Pentium2) 2332 .Case("pentium3", CK_Pentium3) 2333 .Case("pentium3m", CK_Pentium3M) 2334 .Case("pentium-m", CK_PentiumM) 2335 .Case("c3-2", CK_C3_2) 2336 .Case("yonah", CK_Yonah) 2337 .Case("pentium4", CK_Pentium4) 2338 .Case("pentium4m", CK_Pentium4M) 2339 .Case("prescott", CK_Prescott) 2340 .Case("nocona", CK_Nocona) 2341 .Case("core2", CK_Core2) 2342 .Case("penryn", CK_Penryn) 2343 .Case("bonnell", CK_Bonnell) 2344 .Case("atom", CK_Bonnell) // Legacy name. 2345 .Case("silvermont", CK_Silvermont) 2346 .Case("slm", CK_Silvermont) // Legacy name. 2347 .Case("nehalem", CK_Nehalem) 2348 .Case("corei7", CK_Nehalem) // Legacy name. 2349 .Case("westmere", CK_Westmere) 2350 .Case("sandybridge", CK_SandyBridge) 2351 .Case("corei7-avx", CK_SandyBridge) // Legacy name. 2352 .Case("ivybridge", CK_IvyBridge) 2353 .Case("core-avx-i", CK_IvyBridge) // Legacy name. 2354 .Case("haswell", CK_Haswell) 2355 .Case("core-avx2", CK_Haswell) // Legacy name. 2356 .Case("broadwell", CK_Broadwell) 2357 .Case("skylake", CK_SkylakeClient) 2358 .Case("skylake-avx512", CK_SkylakeServer) 2359 .Case("skx", CK_SkylakeServer) // Legacy name. 2360 .Case("cannonlake", CK_Cannonlake) 2361 .Case("knl", CK_KNL) 2362 .Case("k6", CK_K6) 2363 .Case("k6-2", CK_K6_2) 2364 .Case("k6-3", CK_K6_3) 2365 .Case("athlon", CK_Athlon) 2366 .Case("athlon-tbird", CK_AthlonThunderbird) 2367 .Case("athlon-4", CK_Athlon4) 2368 .Case("athlon-xp", CK_AthlonXP) 2369 .Case("athlon-mp", CK_AthlonMP) 2370 .Case("athlon64", CK_Athlon64) 2371 .Case("athlon64-sse3", CK_Athlon64SSE3) 2372 .Case("athlon-fx", CK_AthlonFX) 2373 .Case("k8", CK_K8) 2374 .Case("k8-sse3", CK_K8SSE3) 2375 .Case("opteron", CK_Opteron) 2376 .Case("opteron-sse3", CK_OpteronSSE3) 2377 .Case("barcelona", CK_AMDFAM10) 2378 .Case("amdfam10", CK_AMDFAM10) 2379 .Case("btver1", CK_BTVER1) 2380 .Case("btver2", CK_BTVER2) 2381 .Case("bdver1", CK_BDVER1) 2382 .Case("bdver2", CK_BDVER2) 2383 .Case("bdver3", CK_BDVER3) 2384 .Case("bdver4", CK_BDVER4) 2385 .Case("x86-64", CK_x86_64) 2386 .Case("geode", CK_Geode) 2387 .Default(CK_Generic); 2388 } 2389 2390 enum FPMathKind { 2391 FP_Default, 2392 FP_SSE, 2393 FP_387 2394 } FPMath = FP_Default; 2395 2396 public: 2397 X86TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 2398 BigEndian = false; 2399 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 2400 } 2401 unsigned getFloatEvalMethod() const override { 2402 // X87 evaluates with 80 bits "long double" precision. 2403 return SSELevel == NoSSE ? 2 : 0; 2404 } 2405 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 2406 return llvm::makeArrayRef(BuiltinInfo, 2407 clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin); 2408 } 2409 ArrayRef<const char *> getGCCRegNames() const override { 2410 return llvm::makeArrayRef(GCCRegNames); 2411 } 2412 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 2413 return None; 2414 } 2415 ArrayRef<TargetInfo::AddlRegName> getGCCAddlRegNames() const override { 2416 return llvm::makeArrayRef(AddlRegNames); 2417 } 2418 bool validateCpuSupports(StringRef Name) const override; 2419 bool validateAsmConstraint(const char *&Name, 2420 TargetInfo::ConstraintInfo &info) const override; 2421 2422 bool validateGlobalRegisterVariable(StringRef RegName, 2423 unsigned RegSize, 2424 bool &HasSizeMismatch) const override { 2425 // esp and ebp are the only 32-bit registers the x86 backend can currently 2426 // handle. 2427 if (RegName.equals("esp") || RegName.equals("ebp")) { 2428 // Check that the register size is 32-bit. 2429 HasSizeMismatch = RegSize != 32; 2430 return true; 2431 } 2432 2433 return false; 2434 } 2435 2436 bool validateOutputSize(StringRef Constraint, unsigned Size) const override; 2437 2438 bool validateInputSize(StringRef Constraint, unsigned Size) const override; 2439 2440 virtual bool validateOperandSize(StringRef Constraint, unsigned Size) const; 2441 2442 std::string convertConstraint(const char *&Constraint) const override; 2443 const char *getClobbers() const override { 2444 return "~{dirflag},~{fpsr},~{flags}"; 2445 } 2446 void getTargetDefines(const LangOptions &Opts, 2447 MacroBuilder &Builder) const override; 2448 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 2449 bool Enabled); 2450 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 2451 bool Enabled); 2452 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2453 bool Enabled); 2454 void setFeatureEnabled(llvm::StringMap<bool> &Features, 2455 StringRef Name, bool Enabled) const override { 2456 setFeatureEnabledImpl(Features, Name, Enabled); 2457 } 2458 // This exists purely to cut down on the number of virtual calls in 2459 // initFeatureMap which calls this repeatedly. 2460 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2461 StringRef Name, bool Enabled); 2462 bool 2463 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 2464 StringRef CPU, 2465 const std::vector<std::string> &FeaturesVec) const override; 2466 bool hasFeature(StringRef Feature) const override; 2467 bool handleTargetFeatures(std::vector<std::string> &Features, 2468 DiagnosticsEngine &Diags) override; 2469 StringRef getABI() const override { 2470 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX512F) 2471 return "avx512"; 2472 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 2473 return "avx"; 2474 if (getTriple().getArch() == llvm::Triple::x86 && 2475 MMX3DNowLevel == NoMMX3DNow) 2476 return "no-mmx"; 2477 return ""; 2478 } 2479 bool setCPU(const std::string &Name) override { 2480 CPU = getCPUKind(Name); 2481 2482 // Perform any per-CPU checks necessary to determine if this CPU is 2483 // acceptable. 2484 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 2485 // invalid without explaining *why*. 2486 switch (CPU) { 2487 case CK_Generic: 2488 // No processor selected! 2489 return false; 2490 2491 case CK_i386: 2492 case CK_i486: 2493 case CK_WinChipC6: 2494 case CK_WinChip2: 2495 case CK_C3: 2496 case CK_i586: 2497 case CK_Pentium: 2498 case CK_PentiumMMX: 2499 case CK_i686: 2500 case CK_PentiumPro: 2501 case CK_Pentium2: 2502 case CK_Pentium3: 2503 case CK_Pentium3M: 2504 case CK_PentiumM: 2505 case CK_Yonah: 2506 case CK_C3_2: 2507 case CK_Pentium4: 2508 case CK_Pentium4M: 2509 case CK_Prescott: 2510 case CK_K6: 2511 case CK_K6_2: 2512 case CK_K6_3: 2513 case CK_Athlon: 2514 case CK_AthlonThunderbird: 2515 case CK_Athlon4: 2516 case CK_AthlonXP: 2517 case CK_AthlonMP: 2518 case CK_Geode: 2519 // Only accept certain architectures when compiling in 32-bit mode. 2520 if (getTriple().getArch() != llvm::Triple::x86) 2521 return false; 2522 2523 // Fallthrough 2524 case CK_Nocona: 2525 case CK_Core2: 2526 case CK_Penryn: 2527 case CK_Bonnell: 2528 case CK_Silvermont: 2529 case CK_Nehalem: 2530 case CK_Westmere: 2531 case CK_SandyBridge: 2532 case CK_IvyBridge: 2533 case CK_Haswell: 2534 case CK_Broadwell: 2535 case CK_SkylakeClient: 2536 case CK_SkylakeServer: 2537 case CK_Cannonlake: 2538 case CK_KNL: 2539 case CK_Athlon64: 2540 case CK_Athlon64SSE3: 2541 case CK_AthlonFX: 2542 case CK_K8: 2543 case CK_K8SSE3: 2544 case CK_Opteron: 2545 case CK_OpteronSSE3: 2546 case CK_AMDFAM10: 2547 case CK_BTVER1: 2548 case CK_BTVER2: 2549 case CK_BDVER1: 2550 case CK_BDVER2: 2551 case CK_BDVER3: 2552 case CK_BDVER4: 2553 case CK_x86_64: 2554 return true; 2555 } 2556 llvm_unreachable("Unhandled CPU kind"); 2557 } 2558 2559 bool setFPMath(StringRef Name) override; 2560 2561 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 2562 // We accept all non-ARM calling conventions 2563 return (CC == CC_X86ThisCall || 2564 CC == CC_X86FastCall || 2565 CC == CC_X86StdCall || 2566 CC == CC_X86VectorCall || 2567 CC == CC_C || 2568 CC == CC_X86Pascal || 2569 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2570 } 2571 2572 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 2573 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2574 } 2575 2576 bool hasSjLjLowering() const override { 2577 return true; 2578 } 2579 }; 2580 2581 bool X86TargetInfo::setFPMath(StringRef Name) { 2582 if (Name == "387") { 2583 FPMath = FP_387; 2584 return true; 2585 } 2586 if (Name == "sse") { 2587 FPMath = FP_SSE; 2588 return true; 2589 } 2590 return false; 2591 } 2592 2593 bool X86TargetInfo::initFeatureMap( 2594 llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, StringRef CPU, 2595 const std::vector<std::string> &FeaturesVec) const { 2596 // FIXME: This *really* should not be here. 2597 // X86_64 always has SSE2. 2598 if (getTriple().getArch() == llvm::Triple::x86_64) 2599 setFeatureEnabledImpl(Features, "sse2", true); 2600 2601 switch (getCPUKind(CPU)) { 2602 case CK_Generic: 2603 case CK_i386: 2604 case CK_i486: 2605 case CK_i586: 2606 case CK_Pentium: 2607 case CK_i686: 2608 case CK_PentiumPro: 2609 break; 2610 case CK_PentiumMMX: 2611 case CK_Pentium2: 2612 case CK_K6: 2613 case CK_WinChipC6: 2614 setFeatureEnabledImpl(Features, "mmx", true); 2615 break; 2616 case CK_Pentium3: 2617 case CK_Pentium3M: 2618 case CK_C3_2: 2619 setFeatureEnabledImpl(Features, "sse", true); 2620 setFeatureEnabledImpl(Features, "fxsr", true); 2621 break; 2622 case CK_PentiumM: 2623 case CK_Pentium4: 2624 case CK_Pentium4M: 2625 case CK_x86_64: 2626 setFeatureEnabledImpl(Features, "sse2", true); 2627 setFeatureEnabledImpl(Features, "fxsr", true); 2628 break; 2629 case CK_Yonah: 2630 case CK_Prescott: 2631 case CK_Nocona: 2632 setFeatureEnabledImpl(Features, "sse3", true); 2633 setFeatureEnabledImpl(Features, "fxsr", true); 2634 setFeatureEnabledImpl(Features, "cx16", true); 2635 break; 2636 case CK_Core2: 2637 case CK_Bonnell: 2638 setFeatureEnabledImpl(Features, "ssse3", true); 2639 setFeatureEnabledImpl(Features, "fxsr", true); 2640 setFeatureEnabledImpl(Features, "cx16", true); 2641 break; 2642 case CK_Penryn: 2643 setFeatureEnabledImpl(Features, "sse4.1", true); 2644 setFeatureEnabledImpl(Features, "fxsr", true); 2645 setFeatureEnabledImpl(Features, "cx16", true); 2646 break; 2647 case CK_Cannonlake: 2648 setFeatureEnabledImpl(Features, "avx512ifma", true); 2649 setFeatureEnabledImpl(Features, "avx512vbmi", true); 2650 setFeatureEnabledImpl(Features, "sha", true); 2651 setFeatureEnabledImpl(Features, "umip", true); 2652 // FALLTHROUGH 2653 case CK_SkylakeServer: 2654 setFeatureEnabledImpl(Features, "avx512f", true); 2655 setFeatureEnabledImpl(Features, "avx512cd", true); 2656 setFeatureEnabledImpl(Features, "avx512dq", true); 2657 setFeatureEnabledImpl(Features, "avx512bw", true); 2658 setFeatureEnabledImpl(Features, "avx512vl", true); 2659 setFeatureEnabledImpl(Features, "pku", true); 2660 setFeatureEnabledImpl(Features, "pcommit", true); 2661 setFeatureEnabledImpl(Features, "clwb", true); 2662 // FALLTHROUGH 2663 case CK_SkylakeClient: 2664 setFeatureEnabledImpl(Features, "xsavec", true); 2665 setFeatureEnabledImpl(Features, "xsaves", true); 2666 setFeatureEnabledImpl(Features, "mpx", true); 2667 setFeatureEnabledImpl(Features, "sgx", true); 2668 setFeatureEnabledImpl(Features, "clflushopt", true); 2669 // FALLTHROUGH 2670 case CK_Broadwell: 2671 setFeatureEnabledImpl(Features, "rdseed", true); 2672 setFeatureEnabledImpl(Features, "adx", true); 2673 // FALLTHROUGH 2674 case CK_Haswell: 2675 setFeatureEnabledImpl(Features, "avx2", true); 2676 setFeatureEnabledImpl(Features, "lzcnt", true); 2677 setFeatureEnabledImpl(Features, "bmi", true); 2678 setFeatureEnabledImpl(Features, "bmi2", true); 2679 setFeatureEnabledImpl(Features, "rtm", true); 2680 setFeatureEnabledImpl(Features, "fma", true); 2681 setFeatureEnabledImpl(Features, "movbe", true); 2682 // FALLTHROUGH 2683 case CK_IvyBridge: 2684 setFeatureEnabledImpl(Features, "rdrnd", true); 2685 setFeatureEnabledImpl(Features, "f16c", true); 2686 setFeatureEnabledImpl(Features, "fsgsbase", true); 2687 // FALLTHROUGH 2688 case CK_SandyBridge: 2689 setFeatureEnabledImpl(Features, "avx", true); 2690 setFeatureEnabledImpl(Features, "xsave", true); 2691 setFeatureEnabledImpl(Features, "xsaveopt", true); 2692 // FALLTHROUGH 2693 case CK_Westmere: 2694 case CK_Silvermont: 2695 setFeatureEnabledImpl(Features, "aes", true); 2696 setFeatureEnabledImpl(Features, "pclmul", true); 2697 // FALLTHROUGH 2698 case CK_Nehalem: 2699 setFeatureEnabledImpl(Features, "sse4.2", true); 2700 setFeatureEnabledImpl(Features, "fxsr", true); 2701 setFeatureEnabledImpl(Features, "cx16", true); 2702 break; 2703 case CK_KNL: 2704 setFeatureEnabledImpl(Features, "avx512f", true); 2705 setFeatureEnabledImpl(Features, "avx512cd", true); 2706 setFeatureEnabledImpl(Features, "avx512er", true); 2707 setFeatureEnabledImpl(Features, "avx512pf", true); 2708 setFeatureEnabledImpl(Features, "prefetchwt1", true); 2709 setFeatureEnabledImpl(Features, "fxsr", true); 2710 setFeatureEnabledImpl(Features, "rdseed", true); 2711 setFeatureEnabledImpl(Features, "adx", true); 2712 setFeatureEnabledImpl(Features, "lzcnt", true); 2713 setFeatureEnabledImpl(Features, "bmi", true); 2714 setFeatureEnabledImpl(Features, "bmi2", true); 2715 setFeatureEnabledImpl(Features, "rtm", true); 2716 setFeatureEnabledImpl(Features, "fma", true); 2717 setFeatureEnabledImpl(Features, "rdrnd", true); 2718 setFeatureEnabledImpl(Features, "f16c", true); 2719 setFeatureEnabledImpl(Features, "fsgsbase", true); 2720 setFeatureEnabledImpl(Features, "aes", true); 2721 setFeatureEnabledImpl(Features, "pclmul", true); 2722 setFeatureEnabledImpl(Features, "cx16", true); 2723 setFeatureEnabledImpl(Features, "xsaveopt", true); 2724 setFeatureEnabledImpl(Features, "xsave", true); 2725 setFeatureEnabledImpl(Features, "movbe", true); 2726 break; 2727 case CK_K6_2: 2728 case CK_K6_3: 2729 case CK_WinChip2: 2730 case CK_C3: 2731 setFeatureEnabledImpl(Features, "3dnow", true); 2732 break; 2733 case CK_Athlon: 2734 case CK_AthlonThunderbird: 2735 case CK_Geode: 2736 setFeatureEnabledImpl(Features, "3dnowa", true); 2737 break; 2738 case CK_Athlon4: 2739 case CK_AthlonXP: 2740 case CK_AthlonMP: 2741 setFeatureEnabledImpl(Features, "sse", true); 2742 setFeatureEnabledImpl(Features, "3dnowa", true); 2743 setFeatureEnabledImpl(Features, "fxsr", true); 2744 break; 2745 case CK_K8: 2746 case CK_Opteron: 2747 case CK_Athlon64: 2748 case CK_AthlonFX: 2749 setFeatureEnabledImpl(Features, "sse2", true); 2750 setFeatureEnabledImpl(Features, "3dnowa", true); 2751 setFeatureEnabledImpl(Features, "fxsr", true); 2752 break; 2753 case CK_AMDFAM10: 2754 setFeatureEnabledImpl(Features, "sse4a", true); 2755 setFeatureEnabledImpl(Features, "lzcnt", true); 2756 setFeatureEnabledImpl(Features, "popcnt", true); 2757 // FALLTHROUGH 2758 case CK_K8SSE3: 2759 case CK_OpteronSSE3: 2760 case CK_Athlon64SSE3: 2761 setFeatureEnabledImpl(Features, "sse3", true); 2762 setFeatureEnabledImpl(Features, "3dnowa", true); 2763 setFeatureEnabledImpl(Features, "fxsr", true); 2764 break; 2765 case CK_BTVER2: 2766 setFeatureEnabledImpl(Features, "avx", true); 2767 setFeatureEnabledImpl(Features, "aes", true); 2768 setFeatureEnabledImpl(Features, "pclmul", true); 2769 setFeatureEnabledImpl(Features, "bmi", true); 2770 setFeatureEnabledImpl(Features, "f16c", true); 2771 setFeatureEnabledImpl(Features, "xsaveopt", true); 2772 // FALLTHROUGH 2773 case CK_BTVER1: 2774 setFeatureEnabledImpl(Features, "ssse3", true); 2775 setFeatureEnabledImpl(Features, "sse4a", true); 2776 setFeatureEnabledImpl(Features, "lzcnt", true); 2777 setFeatureEnabledImpl(Features, "popcnt", true); 2778 setFeatureEnabledImpl(Features, "prfchw", true); 2779 setFeatureEnabledImpl(Features, "cx16", true); 2780 setFeatureEnabledImpl(Features, "fxsr", true); 2781 setFeatureEnabledImpl(Features, "xsave", true); 2782 break; 2783 case CK_BDVER4: 2784 setFeatureEnabledImpl(Features, "avx2", true); 2785 setFeatureEnabledImpl(Features, "bmi2", true); 2786 // FALLTHROUGH 2787 case CK_BDVER3: 2788 setFeatureEnabledImpl(Features, "fsgsbase", true); 2789 setFeatureEnabledImpl(Features, "xsaveopt", true); 2790 // FALLTHROUGH 2791 case CK_BDVER2: 2792 setFeatureEnabledImpl(Features, "bmi", true); 2793 setFeatureEnabledImpl(Features, "fma", true); 2794 setFeatureEnabledImpl(Features, "f16c", true); 2795 setFeatureEnabledImpl(Features, "tbm", true); 2796 // FALLTHROUGH 2797 case CK_BDVER1: 2798 // xop implies avx, sse4a and fma4. 2799 setFeatureEnabledImpl(Features, "xop", true); 2800 setFeatureEnabledImpl(Features, "lzcnt", true); 2801 setFeatureEnabledImpl(Features, "aes", true); 2802 setFeatureEnabledImpl(Features, "pclmul", true); 2803 setFeatureEnabledImpl(Features, "prfchw", true); 2804 setFeatureEnabledImpl(Features, "cx16", true); 2805 setFeatureEnabledImpl(Features, "fxsr", true); 2806 setFeatureEnabledImpl(Features, "xsave", true); 2807 break; 2808 } 2809 if (!TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec)) 2810 return false; 2811 2812 // Can't do this earlier because we need to be able to explicitly enable 2813 // or disable these features and the things that they depend upon. 2814 2815 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2816 auto I = Features.find("sse4.2"); 2817 if (I != Features.end() && I->getValue() && 2818 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-popcnt") == 2819 FeaturesVec.end()) 2820 Features["popcnt"] = true; 2821 2822 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2823 I = Features.find("3dnow"); 2824 if (I != Features.end() && I->getValue() && 2825 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-prfchw") == 2826 FeaturesVec.end()) 2827 Features["prfchw"] = true; 2828 2829 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2830 // then enable MMX. 2831 I = Features.find("sse"); 2832 if (I != Features.end() && I->getValue() && 2833 std::find(FeaturesVec.begin(), FeaturesVec.end(), "-mmx") == 2834 FeaturesVec.end()) 2835 Features["mmx"] = true; 2836 2837 return true; 2838 } 2839 2840 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2841 X86SSEEnum Level, bool Enabled) { 2842 if (Enabled) { 2843 switch (Level) { 2844 case AVX512F: 2845 Features["avx512f"] = true; 2846 case AVX2: 2847 Features["avx2"] = true; 2848 case AVX: 2849 Features["avx"] = true; 2850 Features["xsave"] = true; 2851 case SSE42: 2852 Features["sse4.2"] = true; 2853 case SSE41: 2854 Features["sse4.1"] = true; 2855 case SSSE3: 2856 Features["ssse3"] = true; 2857 case SSE3: 2858 Features["sse3"] = true; 2859 case SSE2: 2860 Features["sse2"] = true; 2861 case SSE1: 2862 Features["sse"] = true; 2863 case NoSSE: 2864 break; 2865 } 2866 return; 2867 } 2868 2869 switch (Level) { 2870 case NoSSE: 2871 case SSE1: 2872 Features["sse"] = false; 2873 case SSE2: 2874 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2875 Features["sha"] = false; 2876 case SSE3: 2877 Features["sse3"] = false; 2878 setXOPLevel(Features, NoXOP, false); 2879 case SSSE3: 2880 Features["ssse3"] = false; 2881 case SSE41: 2882 Features["sse4.1"] = false; 2883 case SSE42: 2884 Features["sse4.2"] = false; 2885 case AVX: 2886 Features["fma"] = Features["avx"] = Features["f16c"] = Features["xsave"] = 2887 Features["xsaveopt"] = false; 2888 setXOPLevel(Features, FMA4, false); 2889 case AVX2: 2890 Features["avx2"] = false; 2891 case AVX512F: 2892 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2893 Features["avx512pf"] = Features["avx512dq"] = Features["avx512bw"] = 2894 Features["avx512vl"] = false; 2895 } 2896 } 2897 2898 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2899 MMX3DNowEnum Level, bool Enabled) { 2900 if (Enabled) { 2901 switch (Level) { 2902 case AMD3DNowAthlon: 2903 Features["3dnowa"] = true; 2904 case AMD3DNow: 2905 Features["3dnow"] = true; 2906 case MMX: 2907 Features["mmx"] = true; 2908 case NoMMX3DNow: 2909 break; 2910 } 2911 return; 2912 } 2913 2914 switch (Level) { 2915 case NoMMX3DNow: 2916 case MMX: 2917 Features["mmx"] = false; 2918 case AMD3DNow: 2919 Features["3dnow"] = false; 2920 case AMD3DNowAthlon: 2921 Features["3dnowa"] = false; 2922 } 2923 } 2924 2925 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2926 bool Enabled) { 2927 if (Enabled) { 2928 switch (Level) { 2929 case XOP: 2930 Features["xop"] = true; 2931 case FMA4: 2932 Features["fma4"] = true; 2933 setSSELevel(Features, AVX, true); 2934 case SSE4A: 2935 Features["sse4a"] = true; 2936 setSSELevel(Features, SSE3, true); 2937 case NoXOP: 2938 break; 2939 } 2940 return; 2941 } 2942 2943 switch (Level) { 2944 case NoXOP: 2945 case SSE4A: 2946 Features["sse4a"] = false; 2947 case FMA4: 2948 Features["fma4"] = false; 2949 case XOP: 2950 Features["xop"] = false; 2951 } 2952 } 2953 2954 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2955 StringRef Name, bool Enabled) { 2956 // This is a bit of a hack to deal with the sse4 target feature when used 2957 // as part of the target attribute. We handle sse4 correctly everywhere 2958 // else. See below for more information on how we handle the sse4 options. 2959 if (Name != "sse4") 2960 Features[Name] = Enabled; 2961 2962 if (Name == "mmx") { 2963 setMMXLevel(Features, MMX, Enabled); 2964 } else if (Name == "sse") { 2965 setSSELevel(Features, SSE1, Enabled); 2966 } else if (Name == "sse2") { 2967 setSSELevel(Features, SSE2, Enabled); 2968 } else if (Name == "sse3") { 2969 setSSELevel(Features, SSE3, Enabled); 2970 } else if (Name == "ssse3") { 2971 setSSELevel(Features, SSSE3, Enabled); 2972 } else if (Name == "sse4.2") { 2973 setSSELevel(Features, SSE42, Enabled); 2974 } else if (Name == "sse4.1") { 2975 setSSELevel(Features, SSE41, Enabled); 2976 } else if (Name == "3dnow") { 2977 setMMXLevel(Features, AMD3DNow, Enabled); 2978 } else if (Name == "3dnowa") { 2979 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2980 } else if (Name == "aes") { 2981 if (Enabled) 2982 setSSELevel(Features, SSE2, Enabled); 2983 } else if (Name == "pclmul") { 2984 if (Enabled) 2985 setSSELevel(Features, SSE2, Enabled); 2986 } else if (Name == "avx") { 2987 setSSELevel(Features, AVX, Enabled); 2988 } else if (Name == "avx2") { 2989 setSSELevel(Features, AVX2, Enabled); 2990 } else if (Name == "avx512f") { 2991 setSSELevel(Features, AVX512F, Enabled); 2992 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf" 2993 || Name == "avx512dq" || Name == "avx512bw" || Name == "avx512vl") { 2994 if (Enabled) 2995 setSSELevel(Features, AVX512F, Enabled); 2996 } else if (Name == "fma") { 2997 if (Enabled) 2998 setSSELevel(Features, AVX, Enabled); 2999 } else if (Name == "fma4") { 3000 setXOPLevel(Features, FMA4, Enabled); 3001 } else if (Name == "xop") { 3002 setXOPLevel(Features, XOP, Enabled); 3003 } else if (Name == "sse4a") { 3004 setXOPLevel(Features, SSE4A, Enabled); 3005 } else if (Name == "f16c") { 3006 if (Enabled) 3007 setSSELevel(Features, AVX, Enabled); 3008 } else if (Name == "sha") { 3009 if (Enabled) 3010 setSSELevel(Features, SSE2, Enabled); 3011 } else if (Name == "sse4") { 3012 // We can get here via the __target__ attribute since that's not controlled 3013 // via the -msse4/-mno-sse4 command line alias. Handle this the same way 3014 // here - turn on the sse4.2 if enabled, turn off the sse4.1 level if 3015 // disabled. 3016 if (Enabled) 3017 setSSELevel(Features, SSE42, Enabled); 3018 else 3019 setSSELevel(Features, SSE41, Enabled); 3020 } else if (Name == "xsave") { 3021 if (Enabled) 3022 setSSELevel(Features, AVX, Enabled); 3023 else 3024 Features["xsaveopt"] = false; 3025 } else if (Name == "xsaveopt" || Name == "xsavec" || Name == "xsaves") { 3026 if (Enabled) { 3027 Features["xsave"] = true; 3028 setSSELevel(Features, AVX, Enabled); 3029 } 3030 } 3031 } 3032 3033 /// handleTargetFeatures - Perform initialization based on the user 3034 /// configured set of features. 3035 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 3036 DiagnosticsEngine &Diags) { 3037 for (const auto &Feature : Features) { 3038 if (Feature[0] != '+') 3039 continue; 3040 3041 if (Feature == "+aes") { 3042 HasAES = true; 3043 } else if (Feature == "+pclmul") { 3044 HasPCLMUL = true; 3045 } else if (Feature == "+lzcnt") { 3046 HasLZCNT = true; 3047 } else if (Feature == "+rdrnd") { 3048 HasRDRND = true; 3049 } else if (Feature == "+fsgsbase") { 3050 HasFSGSBASE = true; 3051 } else if (Feature == "+bmi") { 3052 HasBMI = true; 3053 } else if (Feature == "+bmi2") { 3054 HasBMI2 = true; 3055 } else if (Feature == "+popcnt") { 3056 HasPOPCNT = true; 3057 } else if (Feature == "+rtm") { 3058 HasRTM = true; 3059 } else if (Feature == "+prfchw") { 3060 HasPRFCHW = true; 3061 } else if (Feature == "+rdseed") { 3062 HasRDSEED = true; 3063 } else if (Feature == "+adx") { 3064 HasADX = true; 3065 } else if (Feature == "+tbm") { 3066 HasTBM = true; 3067 } else if (Feature == "+fma") { 3068 HasFMA = true; 3069 } else if (Feature == "+f16c") { 3070 HasF16C = true; 3071 } else if (Feature == "+avx512cd") { 3072 HasAVX512CD = true; 3073 } else if (Feature == "+avx512er") { 3074 HasAVX512ER = true; 3075 } else if (Feature == "+avx512pf") { 3076 HasAVX512PF = true; 3077 } else if (Feature == "+avx512dq") { 3078 HasAVX512DQ = true; 3079 } else if (Feature == "+avx512bw") { 3080 HasAVX512BW = true; 3081 } else if (Feature == "+avx512vl") { 3082 HasAVX512VL = true; 3083 } else if (Feature == "+avx512vbmi") { 3084 HasAVX512VBMI = true; 3085 } else if (Feature == "+avx512ifma") { 3086 HasAVX512IFMA = true; 3087 } else if (Feature == "+sha") { 3088 HasSHA = true; 3089 } else if (Feature == "+mpx") { 3090 HasMPX = true; 3091 } else if (Feature == "+movbe") { 3092 HasMOVBE = true; 3093 } else if (Feature == "+sgx") { 3094 HasSGX = true; 3095 } else if (Feature == "+cx16") { 3096 HasCX16 = true; 3097 } else if (Feature == "+fxsr") { 3098 HasFXSR = true; 3099 } else if (Feature == "+xsave") { 3100 HasXSAVE = true; 3101 } else if (Feature == "+xsaveopt") { 3102 HasXSAVEOPT = true; 3103 } else if (Feature == "+xsavec") { 3104 HasXSAVEC = true; 3105 } else if (Feature == "+xsaves") { 3106 HasXSAVES = true; 3107 } else if (Feature == "+pku") { 3108 HasPKU = true; 3109 } else if (Feature == "+clflushopt") { 3110 HasCLFLUSHOPT = true; 3111 } else if (Feature == "+pcommit") { 3112 HasPCOMMIT = true; 3113 } else if (Feature == "+clwb") { 3114 HasCLWB = true; 3115 } else if (Feature == "+umip") { 3116 HasUMIP = true; 3117 } else if (Feature == "+prefetchwt1") { 3118 HasPREFETCHWT1 = true; 3119 } 3120 3121 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 3122 .Case("+avx512f", AVX512F) 3123 .Case("+avx2", AVX2) 3124 .Case("+avx", AVX) 3125 .Case("+sse4.2", SSE42) 3126 .Case("+sse4.1", SSE41) 3127 .Case("+ssse3", SSSE3) 3128 .Case("+sse3", SSE3) 3129 .Case("+sse2", SSE2) 3130 .Case("+sse", SSE1) 3131 .Default(NoSSE); 3132 SSELevel = std::max(SSELevel, Level); 3133 3134 MMX3DNowEnum ThreeDNowLevel = 3135 llvm::StringSwitch<MMX3DNowEnum>(Feature) 3136 .Case("+3dnowa", AMD3DNowAthlon) 3137 .Case("+3dnow", AMD3DNow) 3138 .Case("+mmx", MMX) 3139 .Default(NoMMX3DNow); 3140 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 3141 3142 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 3143 .Case("+xop", XOP) 3144 .Case("+fma4", FMA4) 3145 .Case("+sse4a", SSE4A) 3146 .Default(NoXOP); 3147 XOPLevel = std::max(XOPLevel, XLevel); 3148 } 3149 3150 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 3151 // matches the selected sse level. 3152 if ((FPMath == FP_SSE && SSELevel < SSE1) || 3153 (FPMath == FP_387 && SSELevel >= SSE1)) { 3154 Diags.Report(diag::err_target_unsupported_fpmath) << 3155 (FPMath == FP_SSE ? "sse" : "387"); 3156 return false; 3157 } 3158 3159 SimdDefaultAlign = 3160 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3161 return true; 3162 } 3163 3164 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 3165 /// definitions for this particular subtarget. 3166 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 3167 MacroBuilder &Builder) const { 3168 // Target identification. 3169 if (getTriple().getArch() == llvm::Triple::x86_64) { 3170 Builder.defineMacro("__amd64__"); 3171 Builder.defineMacro("__amd64"); 3172 Builder.defineMacro("__x86_64"); 3173 Builder.defineMacro("__x86_64__"); 3174 if (getTriple().getArchName() == "x86_64h") { 3175 Builder.defineMacro("__x86_64h"); 3176 Builder.defineMacro("__x86_64h__"); 3177 } 3178 } else { 3179 DefineStd(Builder, "i386", Opts); 3180 } 3181 3182 // Subtarget options. 3183 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 3184 // truly should be based on -mtune options. 3185 switch (CPU) { 3186 case CK_Generic: 3187 break; 3188 case CK_i386: 3189 // The rest are coming from the i386 define above. 3190 Builder.defineMacro("__tune_i386__"); 3191 break; 3192 case CK_i486: 3193 case CK_WinChipC6: 3194 case CK_WinChip2: 3195 case CK_C3: 3196 defineCPUMacros(Builder, "i486"); 3197 break; 3198 case CK_PentiumMMX: 3199 Builder.defineMacro("__pentium_mmx__"); 3200 Builder.defineMacro("__tune_pentium_mmx__"); 3201 // Fallthrough 3202 case CK_i586: 3203 case CK_Pentium: 3204 defineCPUMacros(Builder, "i586"); 3205 defineCPUMacros(Builder, "pentium"); 3206 break; 3207 case CK_Pentium3: 3208 case CK_Pentium3M: 3209 case CK_PentiumM: 3210 Builder.defineMacro("__tune_pentium3__"); 3211 // Fallthrough 3212 case CK_Pentium2: 3213 case CK_C3_2: 3214 Builder.defineMacro("__tune_pentium2__"); 3215 // Fallthrough 3216 case CK_PentiumPro: 3217 Builder.defineMacro("__tune_i686__"); 3218 Builder.defineMacro("__tune_pentiumpro__"); 3219 // Fallthrough 3220 case CK_i686: 3221 Builder.defineMacro("__i686"); 3222 Builder.defineMacro("__i686__"); 3223 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 3224 Builder.defineMacro("__pentiumpro"); 3225 Builder.defineMacro("__pentiumpro__"); 3226 break; 3227 case CK_Pentium4: 3228 case CK_Pentium4M: 3229 defineCPUMacros(Builder, "pentium4"); 3230 break; 3231 case CK_Yonah: 3232 case CK_Prescott: 3233 case CK_Nocona: 3234 defineCPUMacros(Builder, "nocona"); 3235 break; 3236 case CK_Core2: 3237 case CK_Penryn: 3238 defineCPUMacros(Builder, "core2"); 3239 break; 3240 case CK_Bonnell: 3241 defineCPUMacros(Builder, "atom"); 3242 break; 3243 case CK_Silvermont: 3244 defineCPUMacros(Builder, "slm"); 3245 break; 3246 case CK_Nehalem: 3247 case CK_Westmere: 3248 case CK_SandyBridge: 3249 case CK_IvyBridge: 3250 case CK_Haswell: 3251 case CK_Broadwell: 3252 case CK_SkylakeClient: 3253 // FIXME: Historically, we defined this legacy name, it would be nice to 3254 // remove it at some point. We've never exposed fine-grained names for 3255 // recent primary x86 CPUs, and we should keep it that way. 3256 defineCPUMacros(Builder, "corei7"); 3257 break; 3258 case CK_SkylakeServer: 3259 defineCPUMacros(Builder, "skx"); 3260 break; 3261 case CK_Cannonlake: 3262 break; 3263 case CK_KNL: 3264 defineCPUMacros(Builder, "knl"); 3265 break; 3266 case CK_K6_2: 3267 Builder.defineMacro("__k6_2__"); 3268 Builder.defineMacro("__tune_k6_2__"); 3269 // Fallthrough 3270 case CK_K6_3: 3271 if (CPU != CK_K6_2) { // In case of fallthrough 3272 // FIXME: GCC may be enabling these in cases where some other k6 3273 // architecture is specified but -m3dnow is explicitly provided. The 3274 // exact semantics need to be determined and emulated here. 3275 Builder.defineMacro("__k6_3__"); 3276 Builder.defineMacro("__tune_k6_3__"); 3277 } 3278 // Fallthrough 3279 case CK_K6: 3280 defineCPUMacros(Builder, "k6"); 3281 break; 3282 case CK_Athlon: 3283 case CK_AthlonThunderbird: 3284 case CK_Athlon4: 3285 case CK_AthlonXP: 3286 case CK_AthlonMP: 3287 defineCPUMacros(Builder, "athlon"); 3288 if (SSELevel != NoSSE) { 3289 Builder.defineMacro("__athlon_sse__"); 3290 Builder.defineMacro("__tune_athlon_sse__"); 3291 } 3292 break; 3293 case CK_K8: 3294 case CK_K8SSE3: 3295 case CK_x86_64: 3296 case CK_Opteron: 3297 case CK_OpteronSSE3: 3298 case CK_Athlon64: 3299 case CK_Athlon64SSE3: 3300 case CK_AthlonFX: 3301 defineCPUMacros(Builder, "k8"); 3302 break; 3303 case CK_AMDFAM10: 3304 defineCPUMacros(Builder, "amdfam10"); 3305 break; 3306 case CK_BTVER1: 3307 defineCPUMacros(Builder, "btver1"); 3308 break; 3309 case CK_BTVER2: 3310 defineCPUMacros(Builder, "btver2"); 3311 break; 3312 case CK_BDVER1: 3313 defineCPUMacros(Builder, "bdver1"); 3314 break; 3315 case CK_BDVER2: 3316 defineCPUMacros(Builder, "bdver2"); 3317 break; 3318 case CK_BDVER3: 3319 defineCPUMacros(Builder, "bdver3"); 3320 break; 3321 case CK_BDVER4: 3322 defineCPUMacros(Builder, "bdver4"); 3323 break; 3324 case CK_Geode: 3325 defineCPUMacros(Builder, "geode"); 3326 break; 3327 } 3328 3329 // Target properties. 3330 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3331 3332 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 3333 // functions in glibc header files that use FP Stack inline asm which the 3334 // backend can't deal with (PR879). 3335 Builder.defineMacro("__NO_MATH_INLINES"); 3336 3337 if (HasAES) 3338 Builder.defineMacro("__AES__"); 3339 3340 if (HasPCLMUL) 3341 Builder.defineMacro("__PCLMUL__"); 3342 3343 if (HasLZCNT) 3344 Builder.defineMacro("__LZCNT__"); 3345 3346 if (HasRDRND) 3347 Builder.defineMacro("__RDRND__"); 3348 3349 if (HasFSGSBASE) 3350 Builder.defineMacro("__FSGSBASE__"); 3351 3352 if (HasBMI) 3353 Builder.defineMacro("__BMI__"); 3354 3355 if (HasBMI2) 3356 Builder.defineMacro("__BMI2__"); 3357 3358 if (HasPOPCNT) 3359 Builder.defineMacro("__POPCNT__"); 3360 3361 if (HasRTM) 3362 Builder.defineMacro("__RTM__"); 3363 3364 if (HasPRFCHW) 3365 Builder.defineMacro("__PRFCHW__"); 3366 3367 if (HasRDSEED) 3368 Builder.defineMacro("__RDSEED__"); 3369 3370 if (HasADX) 3371 Builder.defineMacro("__ADX__"); 3372 3373 if (HasTBM) 3374 Builder.defineMacro("__TBM__"); 3375 3376 switch (XOPLevel) { 3377 case XOP: 3378 Builder.defineMacro("__XOP__"); 3379 case FMA4: 3380 Builder.defineMacro("__FMA4__"); 3381 case SSE4A: 3382 Builder.defineMacro("__SSE4A__"); 3383 case NoXOP: 3384 break; 3385 } 3386 3387 if (HasFMA) 3388 Builder.defineMacro("__FMA__"); 3389 3390 if (HasF16C) 3391 Builder.defineMacro("__F16C__"); 3392 3393 if (HasAVX512CD) 3394 Builder.defineMacro("__AVX512CD__"); 3395 if (HasAVX512ER) 3396 Builder.defineMacro("__AVX512ER__"); 3397 if (HasAVX512PF) 3398 Builder.defineMacro("__AVX512PF__"); 3399 if (HasAVX512DQ) 3400 Builder.defineMacro("__AVX512DQ__"); 3401 if (HasAVX512BW) 3402 Builder.defineMacro("__AVX512BW__"); 3403 if (HasAVX512VL) 3404 Builder.defineMacro("__AVX512VL__"); 3405 3406 if (HasSHA) 3407 Builder.defineMacro("__SHA__"); 3408 3409 if (HasFXSR) 3410 Builder.defineMacro("__FXSR__"); 3411 if (HasXSAVE) 3412 Builder.defineMacro("__XSAVE__"); 3413 if (HasXSAVEOPT) 3414 Builder.defineMacro("__XSAVEOPT__"); 3415 if (HasXSAVEC) 3416 Builder.defineMacro("__XSAVEC__"); 3417 if (HasXSAVES) 3418 Builder.defineMacro("__XSAVES__"); 3419 if (HasPKU) 3420 Builder.defineMacro("__PKU__"); 3421 if (HasCX16) 3422 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 3423 3424 // Each case falls through to the previous one here. 3425 switch (SSELevel) { 3426 case AVX512F: 3427 Builder.defineMacro("__AVX512F__"); 3428 case AVX2: 3429 Builder.defineMacro("__AVX2__"); 3430 case AVX: 3431 Builder.defineMacro("__AVX__"); 3432 case SSE42: 3433 Builder.defineMacro("__SSE4_2__"); 3434 case SSE41: 3435 Builder.defineMacro("__SSE4_1__"); 3436 case SSSE3: 3437 Builder.defineMacro("__SSSE3__"); 3438 case SSE3: 3439 Builder.defineMacro("__SSE3__"); 3440 case SSE2: 3441 Builder.defineMacro("__SSE2__"); 3442 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 3443 case SSE1: 3444 Builder.defineMacro("__SSE__"); 3445 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 3446 case NoSSE: 3447 break; 3448 } 3449 3450 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 3451 switch (SSELevel) { 3452 case AVX512F: 3453 case AVX2: 3454 case AVX: 3455 case SSE42: 3456 case SSE41: 3457 case SSSE3: 3458 case SSE3: 3459 case SSE2: 3460 Builder.defineMacro("_M_IX86_FP", Twine(2)); 3461 break; 3462 case SSE1: 3463 Builder.defineMacro("_M_IX86_FP", Twine(1)); 3464 break; 3465 default: 3466 Builder.defineMacro("_M_IX86_FP", Twine(0)); 3467 } 3468 } 3469 3470 // Each case falls through to the previous one here. 3471 switch (MMX3DNowLevel) { 3472 case AMD3DNowAthlon: 3473 Builder.defineMacro("__3dNOW_A__"); 3474 case AMD3DNow: 3475 Builder.defineMacro("__3dNOW__"); 3476 case MMX: 3477 Builder.defineMacro("__MMX__"); 3478 case NoMMX3DNow: 3479 break; 3480 } 3481 3482 if (CPU >= CK_i486) { 3483 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 3484 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 3485 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 3486 } 3487 if (CPU >= CK_i586) 3488 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 3489 } 3490 3491 bool X86TargetInfo::hasFeature(StringRef Feature) const { 3492 return llvm::StringSwitch<bool>(Feature) 3493 .Case("aes", HasAES) 3494 .Case("avx", SSELevel >= AVX) 3495 .Case("avx2", SSELevel >= AVX2) 3496 .Case("avx512f", SSELevel >= AVX512F) 3497 .Case("avx512cd", HasAVX512CD) 3498 .Case("avx512er", HasAVX512ER) 3499 .Case("avx512pf", HasAVX512PF) 3500 .Case("avx512dq", HasAVX512DQ) 3501 .Case("avx512bw", HasAVX512BW) 3502 .Case("avx512vl", HasAVX512VL) 3503 .Case("avx512vbmi", HasAVX512VBMI) 3504 .Case("avx512ifma", HasAVX512IFMA) 3505 .Case("bmi", HasBMI) 3506 .Case("bmi2", HasBMI2) 3507 .Case("clflushopt", HasCLFLUSHOPT) 3508 .Case("clwb", HasCLWB) 3509 .Case("cx16", HasCX16) 3510 .Case("f16c", HasF16C) 3511 .Case("fma", HasFMA) 3512 .Case("fma4", XOPLevel >= FMA4) 3513 .Case("fsgsbase", HasFSGSBASE) 3514 .Case("fxsr", HasFXSR) 3515 .Case("lzcnt", HasLZCNT) 3516 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 3517 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 3518 .Case("mmx", MMX3DNowLevel >= MMX) 3519 .Case("movbe", HasMOVBE) 3520 .Case("mpx", HasMPX) 3521 .Case("pclmul", HasPCLMUL) 3522 .Case("pcommit", HasPCOMMIT) 3523 .Case("pku", HasPKU) 3524 .Case("popcnt", HasPOPCNT) 3525 .Case("prefetchwt1", HasPREFETCHWT1) 3526 .Case("prfchw", HasPRFCHW) 3527 .Case("rdrnd", HasRDRND) 3528 .Case("rdseed", HasRDSEED) 3529 .Case("rtm", HasRTM) 3530 .Case("sgx", HasSGX) 3531 .Case("sha", HasSHA) 3532 .Case("sse", SSELevel >= SSE1) 3533 .Case("sse2", SSELevel >= SSE2) 3534 .Case("sse3", SSELevel >= SSE3) 3535 .Case("ssse3", SSELevel >= SSSE3) 3536 .Case("sse4.1", SSELevel >= SSE41) 3537 .Case("sse4.2", SSELevel >= SSE42) 3538 .Case("sse4a", XOPLevel >= SSE4A) 3539 .Case("tbm", HasTBM) 3540 .Case("umip", HasUMIP) 3541 .Case("x86", true) 3542 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 3543 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 3544 .Case("xop", XOPLevel >= XOP) 3545 .Case("xsave", HasXSAVE) 3546 .Case("xsavec", HasXSAVEC) 3547 .Case("xsaves", HasXSAVES) 3548 .Case("xsaveopt", HasXSAVEOPT) 3549 .Default(false); 3550 } 3551 3552 // We can't use a generic validation scheme for the features accepted here 3553 // versus subtarget features accepted in the target attribute because the 3554 // bitfield structure that's initialized in the runtime only supports the 3555 // below currently rather than the full range of subtarget features. (See 3556 // X86TargetInfo::hasFeature for a somewhat comprehensive list). 3557 bool X86TargetInfo::validateCpuSupports(StringRef FeatureStr) const { 3558 return llvm::StringSwitch<bool>(FeatureStr) 3559 .Case("cmov", true) 3560 .Case("mmx", true) 3561 .Case("popcnt", true) 3562 .Case("sse", true) 3563 .Case("sse2", true) 3564 .Case("sse3", true) 3565 .Case("sse4.1", true) 3566 .Case("sse4.2", true) 3567 .Case("avx", true) 3568 .Case("avx2", true) 3569 .Case("sse4a", true) 3570 .Case("fma4", true) 3571 .Case("xop", true) 3572 .Case("fma", true) 3573 .Case("avx512f", true) 3574 .Case("bmi", true) 3575 .Case("bmi2", true) 3576 .Default(false); 3577 } 3578 3579 bool 3580 X86TargetInfo::validateAsmConstraint(const char *&Name, 3581 TargetInfo::ConstraintInfo &Info) const { 3582 switch (*Name) { 3583 default: return false; 3584 // Constant constraints. 3585 case 'e': // 32-bit signed integer constant for use with sign-extending x86_64 3586 // instructions. 3587 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 3588 // x86_64 instructions. 3589 case 's': 3590 Info.setRequiresImmediate(); 3591 return true; 3592 case 'I': 3593 Info.setRequiresImmediate(0, 31); 3594 return true; 3595 case 'J': 3596 Info.setRequiresImmediate(0, 63); 3597 return true; 3598 case 'K': 3599 Info.setRequiresImmediate(-128, 127); 3600 return true; 3601 case 'L': 3602 Info.setRequiresImmediate({ int(0xff), int(0xffff), int(0xffffffff) }); 3603 return true; 3604 case 'M': 3605 Info.setRequiresImmediate(0, 3); 3606 return true; 3607 case 'N': 3608 Info.setRequiresImmediate(0, 255); 3609 return true; 3610 case 'O': 3611 Info.setRequiresImmediate(0, 127); 3612 return true; 3613 // Register constraints. 3614 case 'Y': // 'Y' is the first character for several 2-character constraints. 3615 // Shift the pointer to the second character of the constraint. 3616 Name++; 3617 switch (*Name) { 3618 default: 3619 return false; 3620 case '0': // First SSE register. 3621 case 't': // Any SSE register, when SSE2 is enabled. 3622 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 3623 case 'm': // Any MMX register, when inter-unit moves enabled. 3624 Info.setAllowsRegister(); 3625 return true; 3626 } 3627 case 'f': // Any x87 floating point stack register. 3628 // Constraint 'f' cannot be used for output operands. 3629 if (Info.ConstraintStr[0] == '=') 3630 return false; 3631 Info.setAllowsRegister(); 3632 return true; 3633 case 'a': // eax. 3634 case 'b': // ebx. 3635 case 'c': // ecx. 3636 case 'd': // edx. 3637 case 'S': // esi. 3638 case 'D': // edi. 3639 case 'A': // edx:eax. 3640 case 't': // Top of floating point stack. 3641 case 'u': // Second from top of floating point stack. 3642 case 'q': // Any register accessible as [r]l: a, b, c, and d. 3643 case 'y': // Any MMX register. 3644 case 'x': // Any SSE register. 3645 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 3646 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 3647 case 'l': // "Index" registers: any general register that can be used as an 3648 // index in a base+index memory access. 3649 Info.setAllowsRegister(); 3650 return true; 3651 // Floating point constant constraints. 3652 case 'C': // SSE floating point constant. 3653 case 'G': // x87 floating point constant. 3654 return true; 3655 } 3656 } 3657 3658 bool X86TargetInfo::validateOutputSize(StringRef Constraint, 3659 unsigned Size) const { 3660 // Strip off constraint modifiers. 3661 while (Constraint[0] == '=' || 3662 Constraint[0] == '+' || 3663 Constraint[0] == '&') 3664 Constraint = Constraint.substr(1); 3665 3666 return validateOperandSize(Constraint, Size); 3667 } 3668 3669 bool X86TargetInfo::validateInputSize(StringRef Constraint, 3670 unsigned Size) const { 3671 return validateOperandSize(Constraint, Size); 3672 } 3673 3674 bool X86TargetInfo::validateOperandSize(StringRef Constraint, 3675 unsigned Size) const { 3676 switch (Constraint[0]) { 3677 default: break; 3678 case 'y': 3679 return Size <= 64; 3680 case 'f': 3681 case 't': 3682 case 'u': 3683 return Size <= 128; 3684 case 'x': 3685 if (SSELevel >= AVX512F) 3686 // 512-bit zmm registers can be used if target supports AVX512F. 3687 return Size <= 512U; 3688 else if (SSELevel >= AVX) 3689 // 256-bit ymm registers can be used if target supports AVX. 3690 return Size <= 256U; 3691 return Size <= 128U; 3692 case 'Y': 3693 // 'Y' is the first character for several 2-character constraints. 3694 switch (Constraint[1]) { 3695 default: break; 3696 case 'm': 3697 // 'Ym' is synonymous with 'y'. 3698 return Size <= 64; 3699 case 'i': 3700 case 't': 3701 // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled. 3702 if (SSELevel >= AVX512F) 3703 return Size <= 512U; 3704 else if (SSELevel >= AVX) 3705 return Size <= 256U; 3706 return SSELevel >= SSE2 && Size <= 128U; 3707 } 3708 3709 } 3710 3711 return true; 3712 } 3713 3714 std::string 3715 X86TargetInfo::convertConstraint(const char *&Constraint) const { 3716 switch (*Constraint) { 3717 case 'a': return std::string("{ax}"); 3718 case 'b': return std::string("{bx}"); 3719 case 'c': return std::string("{cx}"); 3720 case 'd': return std::string("{dx}"); 3721 case 'S': return std::string("{si}"); 3722 case 'D': return std::string("{di}"); 3723 case 'p': // address 3724 return std::string("im"); 3725 case 't': // top of floating point stack. 3726 return std::string("{st}"); 3727 case 'u': // second from top of floating point stack. 3728 return std::string("{st(1)}"); // second from top of floating point stack. 3729 default: 3730 return std::string(1, *Constraint); 3731 } 3732 } 3733 3734 // X86-32 generic target 3735 class X86_32TargetInfo : public X86TargetInfo { 3736 public: 3737 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3738 DoubleAlign = LongLongAlign = 32; 3739 LongDoubleWidth = 96; 3740 LongDoubleAlign = 32; 3741 SuitableAlign = 128; 3742 DataLayoutString = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"; 3743 SizeType = UnsignedInt; 3744 PtrDiffType = SignedInt; 3745 IntPtrType = SignedInt; 3746 RegParmMax = 3; 3747 3748 // Use fpret for all types. 3749 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 3750 (1 << TargetInfo::Double) | 3751 (1 << TargetInfo::LongDouble)); 3752 3753 // x86-32 has atomics up to 8 bytes 3754 // FIXME: Check that we actually have cmpxchg8b before setting 3755 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 3756 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3757 } 3758 BuiltinVaListKind getBuiltinVaListKind() const override { 3759 return TargetInfo::CharPtrBuiltinVaList; 3760 } 3761 3762 int getEHDataRegisterNumber(unsigned RegNo) const override { 3763 if (RegNo == 0) return 0; 3764 if (RegNo == 1) return 2; 3765 return -1; 3766 } 3767 bool validateOperandSize(StringRef Constraint, 3768 unsigned Size) const override { 3769 switch (Constraint[0]) { 3770 default: break; 3771 case 'R': 3772 case 'q': 3773 case 'Q': 3774 case 'a': 3775 case 'b': 3776 case 'c': 3777 case 'd': 3778 case 'S': 3779 case 'D': 3780 return Size <= 32; 3781 case 'A': 3782 return Size <= 64; 3783 } 3784 3785 return X86TargetInfo::validateOperandSize(Constraint, Size); 3786 } 3787 }; 3788 3789 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 3790 public: 3791 NetBSDI386TargetInfo(const llvm::Triple &Triple) 3792 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 3793 3794 unsigned getFloatEvalMethod() const override { 3795 unsigned Major, Minor, Micro; 3796 getTriple().getOSVersion(Major, Minor, Micro); 3797 // New NetBSD uses the default rounding mode. 3798 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3799 return X86_32TargetInfo::getFloatEvalMethod(); 3800 // NetBSD before 6.99.26 defaults to "double" rounding. 3801 return 1; 3802 } 3803 }; 3804 3805 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3806 public: 3807 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3808 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3809 SizeType = UnsignedLong; 3810 IntPtrType = SignedLong; 3811 PtrDiffType = SignedLong; 3812 } 3813 }; 3814 3815 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3816 public: 3817 BitrigI386TargetInfo(const llvm::Triple &Triple) 3818 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3819 SizeType = UnsignedLong; 3820 IntPtrType = SignedLong; 3821 PtrDiffType = SignedLong; 3822 } 3823 }; 3824 3825 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3826 public: 3827 DarwinI386TargetInfo(const llvm::Triple &Triple) 3828 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3829 LongDoubleWidth = 128; 3830 LongDoubleAlign = 128; 3831 SuitableAlign = 128; 3832 MaxVectorAlign = 256; 3833 // The watchOS simulator uses the builtin bool type for Objective-C. 3834 llvm::Triple T = llvm::Triple(Triple); 3835 if (T.isWatchOS()) 3836 UseSignedCharForObjCBool = false; 3837 SizeType = UnsignedLong; 3838 IntPtrType = SignedLong; 3839 DataLayoutString = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"; 3840 HasAlignMac68kSupport = true; 3841 } 3842 3843 bool handleTargetFeatures(std::vector<std::string> &Features, 3844 DiagnosticsEngine &Diags) override { 3845 if (!DarwinTargetInfo<X86_32TargetInfo>::handleTargetFeatures(Features, 3846 Diags)) 3847 return false; 3848 // We now know the features we have: we can decide how to align vectors. 3849 MaxVectorAlign = 3850 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 3851 return true; 3852 } 3853 }; 3854 3855 // x86-32 Windows target 3856 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3857 public: 3858 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3859 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3860 WCharType = UnsignedShort; 3861 DoubleAlign = LongLongAlign = 64; 3862 bool IsWinCOFF = 3863 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 3864 DataLayoutString = IsWinCOFF 3865 ? "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32" 3866 : "e-m:e-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3867 } 3868 void getTargetDefines(const LangOptions &Opts, 3869 MacroBuilder &Builder) const override { 3870 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3871 } 3872 }; 3873 3874 // x86-32 Windows Visual Studio target 3875 class MicrosoftX86_32TargetInfo : public WindowsX86_32TargetInfo { 3876 public: 3877 MicrosoftX86_32TargetInfo(const llvm::Triple &Triple) 3878 : WindowsX86_32TargetInfo(Triple) { 3879 LongDoubleWidth = LongDoubleAlign = 64; 3880 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3881 } 3882 void getTargetDefines(const LangOptions &Opts, 3883 MacroBuilder &Builder) const override { 3884 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3885 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3886 // The value of the following reflects processor type. 3887 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3888 // We lost the original triple, so we use the default. 3889 Builder.defineMacro("_M_IX86", "600"); 3890 } 3891 }; 3892 3893 static void addCygMingDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3894 // Mingw and cygwin define __declspec(a) to __attribute__((a)). Clang 3895 // supports __declspec natively under -fms-extensions, but we define a no-op 3896 // __declspec macro anyway for pre-processor compatibility. 3897 if (Opts.MicrosoftExt) 3898 Builder.defineMacro("__declspec", "__declspec"); 3899 else 3900 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3901 3902 if (!Opts.MicrosoftExt) { 3903 // Provide macros for all the calling convention keywords. Provide both 3904 // single and double underscore prefixed variants. These are available on 3905 // x64 as well as x86, even though they have no effect. 3906 const char *CCs[] = {"cdecl", "stdcall", "fastcall", "thiscall", "pascal"}; 3907 for (const char *CC : CCs) { 3908 std::string GCCSpelling = "__attribute__((__"; 3909 GCCSpelling += CC; 3910 GCCSpelling += "__))"; 3911 Builder.defineMacro(Twine("_") + CC, GCCSpelling); 3912 Builder.defineMacro(Twine("__") + CC, GCCSpelling); 3913 } 3914 } 3915 } 3916 3917 static void addMinGWDefines(const LangOptions &Opts, MacroBuilder &Builder) { 3918 Builder.defineMacro("__MSVCRT__"); 3919 Builder.defineMacro("__MINGW32__"); 3920 addCygMingDefines(Opts, Builder); 3921 } 3922 3923 // x86-32 MinGW target 3924 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3925 public: 3926 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3927 : WindowsX86_32TargetInfo(Triple) {} 3928 void getTargetDefines(const LangOptions &Opts, 3929 MacroBuilder &Builder) const override { 3930 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3931 DefineStd(Builder, "WIN32", Opts); 3932 DefineStd(Builder, "WINNT", Opts); 3933 Builder.defineMacro("_X86_"); 3934 addMinGWDefines(Opts, Builder); 3935 } 3936 }; 3937 3938 // x86-32 Cygwin target 3939 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3940 public: 3941 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3942 : X86_32TargetInfo(Triple) { 3943 WCharType = UnsignedShort; 3944 DoubleAlign = LongLongAlign = 64; 3945 DataLayoutString = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"; 3946 } 3947 void getTargetDefines(const LangOptions &Opts, 3948 MacroBuilder &Builder) const override { 3949 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3950 Builder.defineMacro("_X86_"); 3951 Builder.defineMacro("__CYGWIN__"); 3952 Builder.defineMacro("__CYGWIN32__"); 3953 addCygMingDefines(Opts, Builder); 3954 DefineStd(Builder, "unix", Opts); 3955 if (Opts.CPlusPlus) 3956 Builder.defineMacro("_GNU_SOURCE"); 3957 } 3958 }; 3959 3960 // x86-32 Haiku target 3961 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3962 public: 3963 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3964 SizeType = UnsignedLong; 3965 IntPtrType = SignedLong; 3966 PtrDiffType = SignedLong; 3967 ProcessIDType = SignedLong; 3968 this->UserLabelPrefix = ""; 3969 this->TLSSupported = false; 3970 } 3971 void getTargetDefines(const LangOptions &Opts, 3972 MacroBuilder &Builder) const override { 3973 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3974 Builder.defineMacro("__INTEL__"); 3975 Builder.defineMacro("__HAIKU__"); 3976 } 3977 }; 3978 3979 // X86-32 MCU target 3980 class MCUX86_32TargetInfo : public X86_32TargetInfo { 3981 public: 3982 MCUX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3983 LongDoubleWidth = 64; 3984 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3985 DataLayoutString = 3986 "e-m:e-p:32:32-i64:32-f64:32-f128:32-n8:16:32-a:0:32-S32"; 3987 UserLabelPrefix = ""; 3988 WIntType = UnsignedInt; 3989 } 3990 3991 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 3992 // On MCU we support only C calling convention. 3993 return CC == CC_C ? CCCR_OK : CCCR_Warning; 3994 } 3995 3996 void getTargetDefines(const LangOptions &Opts, 3997 MacroBuilder &Builder) const override { 3998 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3999 Builder.defineMacro("__iamcu"); 4000 Builder.defineMacro("__iamcu__"); 4001 } 4002 4003 bool allowsLargerPreferedTypeAlignment() const override { 4004 return false; 4005 } 4006 }; 4007 4008 // RTEMS Target 4009 template<typename Target> 4010 class RTEMSTargetInfo : public OSTargetInfo<Target> { 4011 protected: 4012 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4013 MacroBuilder &Builder) const override { 4014 // RTEMS defines; list based off of gcc output 4015 4016 Builder.defineMacro("__rtems__"); 4017 Builder.defineMacro("__ELF__"); 4018 } 4019 4020 public: 4021 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 4022 this->UserLabelPrefix = ""; 4023 4024 switch (Triple.getArch()) { 4025 default: 4026 case llvm::Triple::x86: 4027 // this->MCountName = ".mcount"; 4028 break; 4029 case llvm::Triple::mips: 4030 case llvm::Triple::mipsel: 4031 case llvm::Triple::ppc: 4032 case llvm::Triple::ppc64: 4033 case llvm::Triple::ppc64le: 4034 // this->MCountName = "_mcount"; 4035 break; 4036 case llvm::Triple::arm: 4037 // this->MCountName = "__mcount"; 4038 break; 4039 } 4040 } 4041 }; 4042 4043 // x86-32 RTEMS target 4044 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 4045 public: 4046 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 4047 SizeType = UnsignedLong; 4048 IntPtrType = SignedLong; 4049 PtrDiffType = SignedLong; 4050 this->UserLabelPrefix = ""; 4051 } 4052 void getTargetDefines(const LangOptions &Opts, 4053 MacroBuilder &Builder) const override { 4054 X86_32TargetInfo::getTargetDefines(Opts, Builder); 4055 Builder.defineMacro("__INTEL__"); 4056 Builder.defineMacro("__rtems__"); 4057 } 4058 }; 4059 4060 // x86-64 generic target 4061 class X86_64TargetInfo : public X86TargetInfo { 4062 public: 4063 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 4064 const bool IsX32 = getTriple().getEnvironment() == llvm::Triple::GNUX32; 4065 bool IsWinCOFF = 4066 getTriple().isOSWindows() && getTriple().isOSBinFormatCOFF(); 4067 LongWidth = LongAlign = PointerWidth = PointerAlign = IsX32 ? 32 : 64; 4068 LongDoubleWidth = 128; 4069 LongDoubleAlign = 128; 4070 LargeArrayMinWidth = 128; 4071 LargeArrayAlign = 128; 4072 SuitableAlign = 128; 4073 SizeType = IsX32 ? UnsignedInt : UnsignedLong; 4074 PtrDiffType = IsX32 ? SignedInt : SignedLong; 4075 IntPtrType = IsX32 ? SignedInt : SignedLong; 4076 IntMaxType = IsX32 ? SignedLongLong : SignedLong; 4077 Int64Type = IsX32 ? SignedLongLong : SignedLong; 4078 RegParmMax = 6; 4079 4080 // Pointers are 32-bit in x32. 4081 DataLayoutString = IsX32 ? "e-m:e-p:32:32-i64:64-f80:128-n8:16:32:64-S128" 4082 : IsWinCOFF 4083 ? "e-m:w-i64:64-f80:128-n8:16:32:64-S128" 4084 : "e-m:e-i64:64-f80:128-n8:16:32:64-S128"; 4085 4086 // Use fpret only for long double. 4087 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 4088 4089 // Use fp2ret for _Complex long double. 4090 ComplexLongDoubleUsesFP2Ret = true; 4091 4092 // Make __builtin_ms_va_list available. 4093 HasBuiltinMSVaList = true; 4094 4095 // x86-64 has atomics up to 16 bytes. 4096 MaxAtomicPromoteWidth = 128; 4097 MaxAtomicInlineWidth = 128; 4098 } 4099 BuiltinVaListKind getBuiltinVaListKind() const override { 4100 return TargetInfo::X86_64ABIBuiltinVaList; 4101 } 4102 4103 int getEHDataRegisterNumber(unsigned RegNo) const override { 4104 if (RegNo == 0) return 0; 4105 if (RegNo == 1) return 1; 4106 return -1; 4107 } 4108 4109 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4110 return (CC == CC_C || 4111 CC == CC_X86VectorCall || 4112 CC == CC_IntelOclBicc || 4113 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 4114 } 4115 4116 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 4117 return CC_C; 4118 } 4119 4120 // for x32 we need it here explicitly 4121 bool hasInt128Type() const override { return true; } 4122 unsigned getUnwindWordWidth() const override { return 64; } 4123 unsigned getRegisterWidth() const override { return 64; } 4124 4125 bool validateGlobalRegisterVariable(StringRef RegName, 4126 unsigned RegSize, 4127 bool &HasSizeMismatch) const override { 4128 // rsp and rbp are the only 64-bit registers the x86 backend can currently 4129 // handle. 4130 if (RegName.equals("rsp") || RegName.equals("rbp")) { 4131 // Check that the register size is 64-bit. 4132 HasSizeMismatch = RegSize != 64; 4133 return true; 4134 } 4135 4136 // Check if the register is a 32-bit register the backend can handle. 4137 return X86TargetInfo::validateGlobalRegisterVariable(RegName, RegSize, 4138 HasSizeMismatch); 4139 } 4140 }; 4141 4142 // x86-64 Windows target 4143 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 4144 public: 4145 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 4146 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 4147 WCharType = UnsignedShort; 4148 LongWidth = LongAlign = 32; 4149 DoubleAlign = LongLongAlign = 64; 4150 IntMaxType = SignedLongLong; 4151 Int64Type = SignedLongLong; 4152 SizeType = UnsignedLongLong; 4153 PtrDiffType = SignedLongLong; 4154 IntPtrType = SignedLongLong; 4155 this->UserLabelPrefix = ""; 4156 } 4157 4158 void getTargetDefines(const LangOptions &Opts, 4159 MacroBuilder &Builder) const override { 4160 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 4161 Builder.defineMacro("_WIN64"); 4162 } 4163 4164 BuiltinVaListKind getBuiltinVaListKind() const override { 4165 return TargetInfo::CharPtrBuiltinVaList; 4166 } 4167 4168 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 4169 switch (CC) { 4170 case CC_X86StdCall: 4171 case CC_X86ThisCall: 4172 case CC_X86FastCall: 4173 return CCCR_Ignore; 4174 case CC_C: 4175 case CC_X86VectorCall: 4176 case CC_IntelOclBicc: 4177 case CC_X86_64SysV: 4178 return CCCR_OK; 4179 default: 4180 return CCCR_Warning; 4181 } 4182 } 4183 }; 4184 4185 // x86-64 Windows Visual Studio target 4186 class MicrosoftX86_64TargetInfo : public WindowsX86_64TargetInfo { 4187 public: 4188 MicrosoftX86_64TargetInfo(const llvm::Triple &Triple) 4189 : WindowsX86_64TargetInfo(Triple) { 4190 LongDoubleWidth = LongDoubleAlign = 64; 4191 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 4192 } 4193 void getTargetDefines(const LangOptions &Opts, 4194 MacroBuilder &Builder) const override { 4195 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4196 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 4197 Builder.defineMacro("_M_X64", "100"); 4198 Builder.defineMacro("_M_AMD64", "100"); 4199 } 4200 }; 4201 4202 // x86-64 MinGW target 4203 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 4204 public: 4205 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 4206 : WindowsX86_64TargetInfo(Triple) { 4207 // Mingw64 rounds long double size and alignment up to 16 bytes, but sticks 4208 // with x86 FP ops. Weird. 4209 LongDoubleWidth = LongDoubleAlign = 128; 4210 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 4211 } 4212 4213 void getTargetDefines(const LangOptions &Opts, 4214 MacroBuilder &Builder) const override { 4215 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 4216 DefineStd(Builder, "WIN64", Opts); 4217 Builder.defineMacro("__MINGW64__"); 4218 addMinGWDefines(Opts, Builder); 4219 4220 // GCC defines this macro when it is using __gxx_personality_seh0. 4221 if (!Opts.SjLjExceptions) 4222 Builder.defineMacro("__SEH__"); 4223 } 4224 }; 4225 4226 // x86-64 Cygwin target 4227 class CygwinX86_64TargetInfo : public X86_64TargetInfo { 4228 public: 4229 CygwinX86_64TargetInfo(const llvm::Triple &Triple) 4230 : X86_64TargetInfo(Triple) { 4231 TLSSupported = false; 4232 WCharType = UnsignedShort; 4233 UserLabelPrefix = ""; 4234 } 4235 void getTargetDefines(const LangOptions &Opts, 4236 MacroBuilder &Builder) const override { 4237 X86_64TargetInfo::getTargetDefines(Opts, Builder); 4238 Builder.defineMacro("__x86_64__"); 4239 Builder.defineMacro("__CYGWIN__"); 4240 Builder.defineMacro("__CYGWIN64__"); 4241 addCygMingDefines(Opts, Builder); 4242 DefineStd(Builder, "unix", Opts); 4243 if (Opts.CPlusPlus) 4244 Builder.defineMacro("_GNU_SOURCE"); 4245 4246 // GCC defines this macro when it is using __gxx_personality_seh0. 4247 if (!Opts.SjLjExceptions) 4248 Builder.defineMacro("__SEH__"); 4249 } 4250 }; 4251 4252 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 4253 public: 4254 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 4255 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 4256 Int64Type = SignedLongLong; 4257 // The 64-bit iOS simulator uses the builtin bool type for Objective-C. 4258 llvm::Triple T = llvm::Triple(Triple); 4259 if (T.isiOS()) 4260 UseSignedCharForObjCBool = false; 4261 DataLayoutString = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"; 4262 } 4263 4264 bool handleTargetFeatures(std::vector<std::string> &Features, 4265 DiagnosticsEngine &Diags) override { 4266 if (!DarwinTargetInfo<X86_64TargetInfo>::handleTargetFeatures(Features, 4267 Diags)) 4268 return false; 4269 // We now know the features we have: we can decide how to align vectors. 4270 MaxVectorAlign = 4271 hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128; 4272 return true; 4273 } 4274 }; 4275 4276 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 4277 public: 4278 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 4279 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 4280 IntMaxType = SignedLongLong; 4281 Int64Type = SignedLongLong; 4282 } 4283 }; 4284 4285 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 4286 public: 4287 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 4288 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 4289 IntMaxType = SignedLongLong; 4290 Int64Type = SignedLongLong; 4291 } 4292 }; 4293 4294 class ARMTargetInfo : public TargetInfo { 4295 // Possible FPU choices. 4296 enum FPUMode { 4297 VFP2FPU = (1 << 0), 4298 VFP3FPU = (1 << 1), 4299 VFP4FPU = (1 << 2), 4300 NeonFPU = (1 << 3), 4301 FPARMV8 = (1 << 4) 4302 }; 4303 4304 // Possible HWDiv features. 4305 enum HWDivMode { 4306 HWDivThumb = (1 << 0), 4307 HWDivARM = (1 << 1) 4308 }; 4309 4310 static bool FPUModeIsVFP(FPUMode Mode) { 4311 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 4312 } 4313 4314 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4315 static const char * const GCCRegNames[]; 4316 4317 std::string ABI, CPU; 4318 4319 StringRef CPUProfile; 4320 StringRef CPUAttr; 4321 4322 enum { 4323 FP_Default, 4324 FP_VFP, 4325 FP_Neon 4326 } FPMath; 4327 4328 unsigned ArchISA; 4329 unsigned ArchKind = llvm::ARM::AK_ARMV4T; 4330 unsigned ArchProfile; 4331 unsigned ArchVersion; 4332 4333 unsigned FPU : 5; 4334 4335 unsigned IsAAPCS : 1; 4336 unsigned HWDiv : 2; 4337 4338 // Initialized via features. 4339 unsigned SoftFloat : 1; 4340 unsigned SoftFloatABI : 1; 4341 4342 unsigned CRC : 1; 4343 unsigned Crypto : 1; 4344 unsigned DSP : 1; 4345 unsigned Unaligned : 1; 4346 4347 enum { 4348 LDREX_B = (1 << 0), /// byte (8-bit) 4349 LDREX_H = (1 << 1), /// half (16-bit) 4350 LDREX_W = (1 << 2), /// word (32-bit) 4351 LDREX_D = (1 << 3), /// double (64-bit) 4352 }; 4353 4354 uint32_t LDREX; 4355 4356 // ACLE 6.5.1 Hardware floating point 4357 enum { 4358 HW_FP_HP = (1 << 1), /// half (16-bit) 4359 HW_FP_SP = (1 << 2), /// single (32-bit) 4360 HW_FP_DP = (1 << 3), /// double (64-bit) 4361 }; 4362 uint32_t HW_FP; 4363 4364 static const Builtin::Info BuiltinInfo[]; 4365 4366 void setABIAAPCS() { 4367 IsAAPCS = true; 4368 4369 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4370 const llvm::Triple &T = getTriple(); 4371 4372 // size_t is unsigned long on MachO-derived environments, NetBSD and Bitrig. 4373 if (T.isOSBinFormatMachO() || T.getOS() == llvm::Triple::NetBSD || 4374 T.getOS() == llvm::Triple::Bitrig) 4375 SizeType = UnsignedLong; 4376 else 4377 SizeType = UnsignedInt; 4378 4379 switch (T.getOS()) { 4380 case llvm::Triple::NetBSD: 4381 WCharType = SignedInt; 4382 break; 4383 case llvm::Triple::Win32: 4384 WCharType = UnsignedShort; 4385 break; 4386 case llvm::Triple::Linux: 4387 default: 4388 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 4389 WCharType = UnsignedInt; 4390 break; 4391 } 4392 4393 UseBitFieldTypeAlignment = true; 4394 4395 ZeroLengthBitfieldBoundary = 0; 4396 4397 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 4398 // so set preferred for small types to 32. 4399 if (T.isOSBinFormatMachO()) { 4400 DataLayoutString = 4401 BigEndian ? "E-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4402 : "e-m:o-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4403 } else if (T.isOSWindows()) { 4404 assert(!BigEndian && "Windows on ARM does not support big endian"); 4405 DataLayoutString = "e" 4406 "-m:w" 4407 "-p:32:32" 4408 "-i64:64" 4409 "-v128:64:128" 4410 "-a:0:32" 4411 "-n32" 4412 "-S64"; 4413 } else if (T.isOSNaCl()) { 4414 assert(!BigEndian && "NaCl on ARM does not support big endian"); 4415 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S128"; 4416 } else { 4417 DataLayoutString = 4418 BigEndian ? "E-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64" 4419 : "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 4420 } 4421 4422 // FIXME: Enumerated types are variable width in straight AAPCS. 4423 } 4424 4425 void setABIAPCS(bool IsAAPCS16) { 4426 const llvm::Triple &T = getTriple(); 4427 4428 IsAAPCS = false; 4429 4430 if (IsAAPCS16) 4431 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 64; 4432 else 4433 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 4434 4435 // size_t is unsigned int on FreeBSD. 4436 if (T.getOS() == llvm::Triple::FreeBSD) 4437 SizeType = UnsignedInt; 4438 else 4439 SizeType = UnsignedLong; 4440 4441 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 4442 WCharType = SignedInt; 4443 4444 // Do not respect the alignment of bit-field types when laying out 4445 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 4446 UseBitFieldTypeAlignment = false; 4447 4448 /// gcc forces the alignment to 4 bytes, regardless of the type of the 4449 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 4450 /// gcc. 4451 ZeroLengthBitfieldBoundary = 32; 4452 4453 if (T.isOSBinFormatMachO() && IsAAPCS16) { 4454 assert(!BigEndian && "AAPCS16 does not support big-endian"); 4455 DataLayoutString = "e-m:o-p:32:32-i64:64-a:0:32-n32-S128"; 4456 } else if (T.isOSBinFormatMachO()) 4457 DataLayoutString = 4458 BigEndian 4459 ? "E-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4460 : "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4461 else 4462 DataLayoutString = 4463 BigEndian 4464 ? "E-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32" 4465 : "e-m:e-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"; 4466 4467 // FIXME: Override "preferred align" for double and long long. 4468 } 4469 4470 void setArchInfo() { 4471 StringRef ArchName = getTriple().getArchName(); 4472 4473 ArchISA = llvm::ARM::parseArchISA(ArchName); 4474 CPU = llvm::ARM::getDefaultCPU(ArchName); 4475 unsigned AK = llvm::ARM::parseArch(ArchName); 4476 if (AK != llvm::ARM::AK_INVALID) 4477 ArchKind = AK; 4478 setArchInfo(ArchKind); 4479 } 4480 4481 void setArchInfo(unsigned Kind) { 4482 StringRef SubArch; 4483 4484 // cache TargetParser info 4485 ArchKind = Kind; 4486 SubArch = llvm::ARM::getSubArch(ArchKind); 4487 ArchProfile = llvm::ARM::parseArchProfile(SubArch); 4488 ArchVersion = llvm::ARM::parseArchVersion(SubArch); 4489 4490 // cache CPU related strings 4491 CPUAttr = getCPUAttr(); 4492 CPUProfile = getCPUProfile(); 4493 } 4494 4495 void setAtomic() { 4496 // when triple does not specify a sub arch, 4497 // then we are not using inline atomics 4498 bool ShouldUseInlineAtomic = 4499 (ArchISA == llvm::ARM::IK_ARM && ArchVersion >= 6) || 4500 (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7); 4501 // Cortex M does not support 8 byte atomics, while general Thumb2 does. 4502 if (ArchProfile == llvm::ARM::PK_M) { 4503 MaxAtomicPromoteWidth = 32; 4504 if (ShouldUseInlineAtomic) 4505 MaxAtomicInlineWidth = 32; 4506 } 4507 else { 4508 MaxAtomicPromoteWidth = 64; 4509 if (ShouldUseInlineAtomic) 4510 MaxAtomicInlineWidth = 64; 4511 } 4512 } 4513 4514 bool isThumb() const { 4515 return (ArchISA == llvm::ARM::IK_THUMB); 4516 } 4517 4518 bool supportsThumb() const { 4519 return CPUAttr.count('T') || ArchVersion >= 6; 4520 } 4521 4522 bool supportsThumb2() const { 4523 return CPUAttr.equals("6T2") || ArchVersion >= 7; 4524 } 4525 4526 StringRef getCPUAttr() const { 4527 // For most sub-arches, the build attribute CPU name is enough. 4528 // For Cortex variants, it's slightly different. 4529 switch(ArchKind) { 4530 default: 4531 return llvm::ARM::getCPUAttr(ArchKind); 4532 case llvm::ARM::AK_ARMV6M: 4533 return "6M"; 4534 case llvm::ARM::AK_ARMV7S: 4535 return "7S"; 4536 case llvm::ARM::AK_ARMV7A: 4537 return "7A"; 4538 case llvm::ARM::AK_ARMV7R: 4539 return "7R"; 4540 case llvm::ARM::AK_ARMV7M: 4541 return "7M"; 4542 case llvm::ARM::AK_ARMV7EM: 4543 return "7EM"; 4544 case llvm::ARM::AK_ARMV8A: 4545 return "8A"; 4546 case llvm::ARM::AK_ARMV8_1A: 4547 return "8_1A"; 4548 case llvm::ARM::AK_ARMV8_2A: 4549 return "8_2A"; 4550 } 4551 } 4552 4553 StringRef getCPUProfile() const { 4554 switch(ArchProfile) { 4555 case llvm::ARM::PK_A: 4556 return "A"; 4557 case llvm::ARM::PK_R: 4558 return "R"; 4559 case llvm::ARM::PK_M: 4560 return "M"; 4561 default: 4562 return ""; 4563 } 4564 } 4565 4566 public: 4567 ARMTargetInfo(const llvm::Triple &Triple, bool IsBigEndian) 4568 : TargetInfo(Triple), FPMath(FP_Default), 4569 IsAAPCS(true), LDREX(0), HW_FP(0) { 4570 BigEndian = IsBigEndian; 4571 4572 switch (getTriple().getOS()) { 4573 case llvm::Triple::NetBSD: 4574 PtrDiffType = SignedLong; 4575 break; 4576 default: 4577 PtrDiffType = SignedInt; 4578 break; 4579 } 4580 4581 // Cache arch related info. 4582 setArchInfo(); 4583 4584 // {} in inline assembly are neon specifiers, not assembly variant 4585 // specifiers. 4586 NoAsmVariants = true; 4587 4588 // FIXME: This duplicates code from the driver that sets the -target-abi 4589 // option - this code is used if -target-abi isn't passed and should 4590 // be unified in some way. 4591 if (Triple.isOSBinFormatMachO()) { 4592 // The backend is hardwired to assume AAPCS for M-class processors, ensure 4593 // the frontend matches that. 4594 if (Triple.getEnvironment() == llvm::Triple::EABI || 4595 Triple.getOS() == llvm::Triple::UnknownOS || 4596 StringRef(CPU).startswith("cortex-m")) { 4597 setABI("aapcs"); 4598 } else if (Triple.isWatchABI()) { 4599 setABI("aapcs16"); 4600 } else { 4601 setABI("apcs-gnu"); 4602 } 4603 } else if (Triple.isOSWindows()) { 4604 // FIXME: this is invalid for WindowsCE 4605 setABI("aapcs"); 4606 } else { 4607 // Select the default based on the platform. 4608 switch (Triple.getEnvironment()) { 4609 case llvm::Triple::Android: 4610 case llvm::Triple::GNUEABI: 4611 case llvm::Triple::GNUEABIHF: 4612 setABI("aapcs-linux"); 4613 break; 4614 case llvm::Triple::EABIHF: 4615 case llvm::Triple::EABI: 4616 setABI("aapcs"); 4617 break; 4618 case llvm::Triple::GNU: 4619 setABI("apcs-gnu"); 4620 break; 4621 default: 4622 if (Triple.getOS() == llvm::Triple::NetBSD) 4623 setABI("apcs-gnu"); 4624 else 4625 setABI("aapcs"); 4626 break; 4627 } 4628 } 4629 4630 // ARM targets default to using the ARM C++ ABI. 4631 TheCXXABI.set(TargetCXXABI::GenericARM); 4632 4633 // ARM has atomics up to 8 bytes 4634 setAtomic(); 4635 4636 // Do force alignment of members that follow zero length bitfields. If 4637 // the alignment of the zero-length bitfield is greater than the member 4638 // that follows it, `bar', `bar' will be aligned as the type of the 4639 // zero length bitfield. 4640 UseZeroLengthBitfieldAlignment = true; 4641 } 4642 4643 StringRef getABI() const override { return ABI; } 4644 4645 bool setABI(const std::string &Name) override { 4646 ABI = Name; 4647 4648 // The defaults (above) are for AAPCS, check if we need to change them. 4649 // 4650 // FIXME: We need support for -meabi... we could just mangle it into the 4651 // name. 4652 if (Name == "apcs-gnu" || Name == "aapcs16") { 4653 setABIAPCS(Name == "aapcs16"); 4654 return true; 4655 } 4656 if (Name == "aapcs" || Name == "aapcs-vfp" || Name == "aapcs-linux") { 4657 setABIAAPCS(); 4658 return true; 4659 } 4660 return false; 4661 } 4662 4663 // FIXME: This should be based on Arch attributes, not CPU names. 4664 bool 4665 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 4666 StringRef CPU, 4667 const std::vector<std::string> &FeaturesVec) const override { 4668 4669 std::vector<const char*> TargetFeatures; 4670 unsigned Arch = llvm::ARM::parseArch(getTriple().getArchName()); 4671 4672 // get default FPU features 4673 unsigned FPUKind = llvm::ARM::getDefaultFPU(CPU, Arch); 4674 llvm::ARM::getFPUFeatures(FPUKind, TargetFeatures); 4675 4676 // get default Extension features 4677 unsigned Extensions = llvm::ARM::getDefaultExtensions(CPU, Arch); 4678 llvm::ARM::getExtensionFeatures(Extensions, TargetFeatures); 4679 4680 for (const char *Feature : TargetFeatures) 4681 if (Feature[0] == '+') 4682 Features[Feature+1] = true; 4683 4684 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 4685 } 4686 4687 bool handleTargetFeatures(std::vector<std::string> &Features, 4688 DiagnosticsEngine &Diags) override { 4689 FPU = 0; 4690 CRC = 0; 4691 Crypto = 0; 4692 DSP = 0; 4693 Unaligned = 1; 4694 SoftFloat = SoftFloatABI = false; 4695 HWDiv = 0; 4696 4697 // This does not diagnose illegal cases like having both 4698 // "+vfpv2" and "+vfpv3" or having "+neon" and "+fp-only-sp". 4699 uint32_t HW_FP_remove = 0; 4700 for (const auto &Feature : Features) { 4701 if (Feature == "+soft-float") { 4702 SoftFloat = true; 4703 } else if (Feature == "+soft-float-abi") { 4704 SoftFloatABI = true; 4705 } else if (Feature == "+vfp2") { 4706 FPU |= VFP2FPU; 4707 HW_FP |= HW_FP_SP | HW_FP_DP; 4708 } else if (Feature == "+vfp3") { 4709 FPU |= VFP3FPU; 4710 HW_FP |= HW_FP_SP | HW_FP_DP; 4711 } else if (Feature == "+vfp4") { 4712 FPU |= VFP4FPU; 4713 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4714 } else if (Feature == "+fp-armv8") { 4715 FPU |= FPARMV8; 4716 HW_FP |= HW_FP_SP | HW_FP_DP | HW_FP_HP; 4717 } else if (Feature == "+neon") { 4718 FPU |= NeonFPU; 4719 HW_FP |= HW_FP_SP | HW_FP_DP; 4720 } else if (Feature == "+hwdiv") { 4721 HWDiv |= HWDivThumb; 4722 } else if (Feature == "+hwdiv-arm") { 4723 HWDiv |= HWDivARM; 4724 } else if (Feature == "+crc") { 4725 CRC = 1; 4726 } else if (Feature == "+crypto") { 4727 Crypto = 1; 4728 } else if (Feature == "+dsp") { 4729 DSP = 1; 4730 } else if (Feature == "+fp-only-sp") { 4731 HW_FP_remove |= HW_FP_DP; 4732 } else if (Feature == "+strict-align") { 4733 Unaligned = 0; 4734 } else if (Feature == "+fp16") { 4735 HW_FP |= HW_FP_HP; 4736 } 4737 } 4738 HW_FP &= ~HW_FP_remove; 4739 4740 switch (ArchVersion) { 4741 case 6: 4742 if (ArchProfile == llvm::ARM::PK_M) 4743 LDREX = 0; 4744 else if (ArchKind == llvm::ARM::AK_ARMV6K) 4745 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4746 else 4747 LDREX = LDREX_W; 4748 break; 4749 case 7: 4750 if (ArchProfile == llvm::ARM::PK_M) 4751 LDREX = LDREX_W | LDREX_H | LDREX_B ; 4752 else 4753 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4754 break; 4755 case 8: 4756 LDREX = LDREX_D | LDREX_W | LDREX_H | LDREX_B ; 4757 } 4758 4759 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 4760 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 4761 return false; 4762 } 4763 4764 if (FPMath == FP_Neon) 4765 Features.push_back("+neonfp"); 4766 else if (FPMath == FP_VFP) 4767 Features.push_back("-neonfp"); 4768 4769 // Remove front-end specific options which the backend handles differently. 4770 auto Feature = 4771 std::find(Features.begin(), Features.end(), "+soft-float-abi"); 4772 if (Feature != Features.end()) 4773 Features.erase(Feature); 4774 4775 return true; 4776 } 4777 4778 bool hasFeature(StringRef Feature) const override { 4779 return llvm::StringSwitch<bool>(Feature) 4780 .Case("arm", true) 4781 .Case("aarch32", true) 4782 .Case("softfloat", SoftFloat) 4783 .Case("thumb", isThumb()) 4784 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 4785 .Case("hwdiv", HWDiv & HWDivThumb) 4786 .Case("hwdiv-arm", HWDiv & HWDivARM) 4787 .Default(false); 4788 } 4789 4790 bool setCPU(const std::string &Name) override { 4791 if (Name != "generic") 4792 setArchInfo(llvm::ARM::parseCPUArch(Name)); 4793 4794 if (ArchKind == llvm::ARM::AK_INVALID) 4795 return false; 4796 setAtomic(); 4797 CPU = Name; 4798 return true; 4799 } 4800 4801 bool setFPMath(StringRef Name) override; 4802 4803 void getTargetDefines(const LangOptions &Opts, 4804 MacroBuilder &Builder) const override { 4805 // Target identification. 4806 Builder.defineMacro("__arm"); 4807 Builder.defineMacro("__arm__"); 4808 4809 // Target properties. 4810 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4811 4812 // Unfortunately, __ARM_ARCH_7K__ is now more of an ABI descriptor. The CPU 4813 // happens to be Cortex-A7 though, so it should still get __ARM_ARCH_7A__. 4814 if (getTriple().isWatchABI()) 4815 Builder.defineMacro("__ARM_ARCH_7K__", "2"); 4816 4817 if (!CPUAttr.empty()) 4818 Builder.defineMacro("__ARM_ARCH_" + CPUAttr + "__"); 4819 4820 // ACLE 6.4.1 ARM/Thumb instruction set architecture 4821 // __ARM_ARCH is defined as an integer value indicating the current ARM ISA 4822 Builder.defineMacro("__ARM_ARCH", Twine(ArchVersion)); 4823 4824 if (ArchVersion >= 8) { 4825 // ACLE 6.5.7 Crypto Extension 4826 if (Crypto) 4827 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 4828 // ACLE 6.5.8 CRC32 Extension 4829 if (CRC) 4830 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 4831 // ACLE 6.5.10 Numeric Maximum and Minimum 4832 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 4833 // ACLE 6.5.9 Directed Rounding 4834 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 4835 } 4836 4837 // __ARM_ARCH_ISA_ARM is defined to 1 if the core supports the ARM ISA. It 4838 // is not defined for the M-profile. 4839 // NOTE that the deffault profile is assumed to be 'A' 4840 if (CPUProfile.empty() || CPUProfile != "M") 4841 Builder.defineMacro("__ARM_ARCH_ISA_ARM", "1"); 4842 4843 // __ARM_ARCH_ISA_THUMB is defined to 1 if the core supporst the original 4844 // Thumb ISA (including v6-M). It is set to 2 if the core supports the 4845 // Thumb-2 ISA as found in the v6T2 architecture and all v7 architecture. 4846 if (supportsThumb2()) 4847 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "2"); 4848 else if (supportsThumb()) 4849 Builder.defineMacro("__ARM_ARCH_ISA_THUMB", "1"); 4850 4851 // __ARM_32BIT_STATE is defined to 1 if code is being generated for a 32-bit 4852 // instruction set such as ARM or Thumb. 4853 Builder.defineMacro("__ARM_32BIT_STATE", "1"); 4854 4855 // ACLE 6.4.2 Architectural Profile (A, R, M or pre-Cortex) 4856 4857 // __ARM_ARCH_PROFILE is defined as 'A', 'R', 'M' or 'S', or unset. 4858 if (!CPUProfile.empty()) 4859 Builder.defineMacro("__ARM_ARCH_PROFILE", "'" + CPUProfile + "'"); 4860 4861 // ACLE 6.4.3 Unaligned access supported in hardware 4862 if (Unaligned) 4863 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 4864 4865 // ACLE 6.4.4 LDREX/STREX 4866 if (LDREX) 4867 Builder.defineMacro("__ARM_FEATURE_LDREX", "0x" + llvm::utohexstr(LDREX)); 4868 4869 // ACLE 6.4.5 CLZ 4870 if (ArchVersion == 5 || 4871 (ArchVersion == 6 && CPUProfile != "M") || 4872 ArchVersion > 6) 4873 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 4874 4875 // ACLE 6.5.1 Hardware Floating Point 4876 if (HW_FP) 4877 Builder.defineMacro("__ARM_FP", "0x" + llvm::utohexstr(HW_FP)); 4878 4879 // ACLE predefines. 4880 Builder.defineMacro("__ARM_ACLE", "200"); 4881 4882 // FP16 support (we currently only support IEEE format). 4883 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 4884 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 4885 4886 // ACLE 6.5.3 Fused multiply-accumulate (FMA) 4887 if (ArchVersion >= 7 && (CPUProfile != "M" || CPUAttr == "7EM")) 4888 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 4889 4890 // Subtarget options. 4891 4892 // FIXME: It's more complicated than this and we don't really support 4893 // interworking. 4894 // Windows on ARM does not "support" interworking 4895 if (5 <= ArchVersion && ArchVersion <= 8 && !getTriple().isOSWindows()) 4896 Builder.defineMacro("__THUMB_INTERWORK__"); 4897 4898 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 4899 // Embedded targets on Darwin follow AAPCS, but not EABI. 4900 // Windows on ARM follows AAPCS VFP, but does not conform to EABI. 4901 if (!getTriple().isOSDarwin() && !getTriple().isOSWindows()) 4902 Builder.defineMacro("__ARM_EABI__"); 4903 Builder.defineMacro("__ARM_PCS", "1"); 4904 4905 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 4906 Builder.defineMacro("__ARM_PCS_VFP", "1"); 4907 } 4908 4909 if (SoftFloat) 4910 Builder.defineMacro("__SOFTFP__"); 4911 4912 if (CPU == "xscale") 4913 Builder.defineMacro("__XSCALE__"); 4914 4915 if (isThumb()) { 4916 Builder.defineMacro("__THUMBEL__"); 4917 Builder.defineMacro("__thumb__"); 4918 if (supportsThumb2()) 4919 Builder.defineMacro("__thumb2__"); 4920 } 4921 4922 // ACLE 6.4.9 32-bit SIMD instructions 4923 if (ArchVersion >= 6 && (CPUProfile != "M" || CPUAttr == "7EM")) 4924 Builder.defineMacro("__ARM_FEATURE_SIMD32", "1"); 4925 4926 // ACLE 6.4.10 Hardware Integer Divide 4927 if (((HWDiv & HWDivThumb) && isThumb()) || 4928 ((HWDiv & HWDivARM) && !isThumb())) { 4929 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); 4930 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 4931 } 4932 4933 // Note, this is always on in gcc, even though it doesn't make sense. 4934 Builder.defineMacro("__APCS_32__"); 4935 4936 if (FPUModeIsVFP((FPUMode) FPU)) { 4937 Builder.defineMacro("__VFP_FP__"); 4938 if (FPU & VFP2FPU) 4939 Builder.defineMacro("__ARM_VFPV2__"); 4940 if (FPU & VFP3FPU) 4941 Builder.defineMacro("__ARM_VFPV3__"); 4942 if (FPU & VFP4FPU) 4943 Builder.defineMacro("__ARM_VFPV4__"); 4944 } 4945 4946 // This only gets set when Neon instructions are actually available, unlike 4947 // the VFP define, hence the soft float and arch check. This is subtly 4948 // different from gcc, we follow the intent which was that it should be set 4949 // when Neon instructions are actually available. 4950 if ((FPU & NeonFPU) && !SoftFloat && ArchVersion >= 7) { 4951 Builder.defineMacro("__ARM_NEON", "1"); 4952 Builder.defineMacro("__ARM_NEON__"); 4953 // current AArch32 NEON implementations do not support double-precision 4954 // floating-point even when it is present in VFP. 4955 Builder.defineMacro("__ARM_NEON_FP", 4956 "0x" + llvm::utohexstr(HW_FP & ~HW_FP_DP)); 4957 } 4958 4959 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 4960 Opts.ShortWChar ? "2" : "4"); 4961 4962 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 4963 Opts.ShortEnums ? "1" : "4"); 4964 4965 if (ArchVersion >= 6 && CPUAttr != "6M") { 4966 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4967 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4968 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4969 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4970 } 4971 4972 // ACLE 6.4.7 DSP instructions 4973 if (DSP) { 4974 Builder.defineMacro("__ARM_FEATURE_DSP", "1"); 4975 } 4976 4977 // ACLE 6.4.8 Saturation instructions 4978 bool SAT = false; 4979 if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) { 4980 Builder.defineMacro("__ARM_FEATURE_SAT", "1"); 4981 SAT = true; 4982 } 4983 4984 // ACLE 6.4.6 Q (saturation) flag 4985 if (DSP || SAT) 4986 Builder.defineMacro("__ARM_FEATURE_QBIT", "1"); 4987 4988 if (Opts.UnsafeFPMath) 4989 Builder.defineMacro("__ARM_FP_FAST", "1"); 4990 4991 if (ArchKind == llvm::ARM::AK_ARMV8_1A) 4992 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 4993 } 4994 4995 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 4996 return llvm::makeArrayRef(BuiltinInfo, 4997 clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin); 4998 } 4999 bool isCLZForZeroUndef() const override { return false; } 5000 BuiltinVaListKind getBuiltinVaListKind() const override { 5001 return IsAAPCS 5002 ? AAPCSABIBuiltinVaList 5003 : (getTriple().isWatchABI() ? TargetInfo::CharPtrBuiltinVaList 5004 : TargetInfo::VoidPtrBuiltinVaList); 5005 } 5006 ArrayRef<const char *> getGCCRegNames() const override; 5007 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5008 bool validateAsmConstraint(const char *&Name, 5009 TargetInfo::ConstraintInfo &Info) const override { 5010 switch (*Name) { 5011 default: break; 5012 case 'l': // r0-r7 5013 case 'h': // r8-r15 5014 case 't': // VFP Floating point register single precision 5015 case 'w': // VFP Floating point register double precision 5016 Info.setAllowsRegister(); 5017 return true; 5018 case 'I': 5019 case 'J': 5020 case 'K': 5021 case 'L': 5022 case 'M': 5023 // FIXME 5024 return true; 5025 case 'Q': // A memory address that is a single base register. 5026 Info.setAllowsMemory(); 5027 return true; 5028 case 'U': // a memory reference... 5029 switch (Name[1]) { 5030 case 'q': // ...ARMV4 ldrsb 5031 case 'v': // ...VFP load/store (reg+constant offset) 5032 case 'y': // ...iWMMXt load/store 5033 case 't': // address valid for load/store opaque types wider 5034 // than 128-bits 5035 case 'n': // valid address for Neon doubleword vector load/store 5036 case 'm': // valid address for Neon element and structure load/store 5037 case 's': // valid address for non-offset loads/stores of quad-word 5038 // values in four ARM registers 5039 Info.setAllowsMemory(); 5040 Name++; 5041 return true; 5042 } 5043 } 5044 return false; 5045 } 5046 std::string convertConstraint(const char *&Constraint) const override { 5047 std::string R; 5048 switch (*Constraint) { 5049 case 'U': // Two-character constraint; add "^" hint for later parsing. 5050 R = std::string("^") + std::string(Constraint, 2); 5051 Constraint++; 5052 break; 5053 case 'p': // 'p' should be translated to 'r' by default. 5054 R = std::string("r"); 5055 break; 5056 default: 5057 return std::string(1, *Constraint); 5058 } 5059 return R; 5060 } 5061 bool 5062 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5063 std::string &SuggestedModifier) const override { 5064 bool isOutput = (Constraint[0] == '='); 5065 bool isInOut = (Constraint[0] == '+'); 5066 5067 // Strip off constraint modifiers. 5068 while (Constraint[0] == '=' || 5069 Constraint[0] == '+' || 5070 Constraint[0] == '&') 5071 Constraint = Constraint.substr(1); 5072 5073 switch (Constraint[0]) { 5074 default: break; 5075 case 'r': { 5076 switch (Modifier) { 5077 default: 5078 return (isInOut || isOutput || Size <= 64); 5079 case 'q': 5080 // A register of size 32 cannot fit a vector type. 5081 return false; 5082 } 5083 } 5084 } 5085 5086 return true; 5087 } 5088 const char *getClobbers() const override { 5089 // FIXME: Is this really right? 5090 return ""; 5091 } 5092 5093 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5094 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 5095 } 5096 5097 int getEHDataRegisterNumber(unsigned RegNo) const override { 5098 if (RegNo == 0) return 0; 5099 if (RegNo == 1) return 1; 5100 return -1; 5101 } 5102 5103 bool hasSjLjLowering() const override { 5104 return true; 5105 } 5106 }; 5107 5108 bool ARMTargetInfo::setFPMath(StringRef Name) { 5109 if (Name == "neon") { 5110 FPMath = FP_Neon; 5111 return true; 5112 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 5113 Name == "vfp4") { 5114 FPMath = FP_VFP; 5115 return true; 5116 } 5117 return false; 5118 } 5119 5120 const char * const ARMTargetInfo::GCCRegNames[] = { 5121 // Integer registers 5122 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5123 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 5124 5125 // Float registers 5126 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 5127 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 5128 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 5129 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5130 5131 // Double registers 5132 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 5133 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 5134 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 5135 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5136 5137 // Quad registers 5138 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 5139 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 5140 }; 5141 5142 ArrayRef<const char *> ARMTargetInfo::getGCCRegNames() const { 5143 return llvm::makeArrayRef(GCCRegNames); 5144 } 5145 5146 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 5147 { { "a1" }, "r0" }, 5148 { { "a2" }, "r1" }, 5149 { { "a3" }, "r2" }, 5150 { { "a4" }, "r3" }, 5151 { { "v1" }, "r4" }, 5152 { { "v2" }, "r5" }, 5153 { { "v3" }, "r6" }, 5154 { { "v4" }, "r7" }, 5155 { { "v5" }, "r8" }, 5156 { { "v6", "rfp" }, "r9" }, 5157 { { "sl" }, "r10" }, 5158 { { "fp" }, "r11" }, 5159 { { "ip" }, "r12" }, 5160 { { "r13" }, "sp" }, 5161 { { "r14" }, "lr" }, 5162 { { "r15" }, "pc" }, 5163 // The S, D and Q registers overlap, but aren't really aliases; we 5164 // don't want to substitute one of these for a different-sized one. 5165 }; 5166 5167 ArrayRef<TargetInfo::GCCRegAlias> ARMTargetInfo::getGCCRegAliases() const { 5168 return llvm::makeArrayRef(GCCRegAliases); 5169 } 5170 5171 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 5172 #define BUILTIN(ID, TYPE, ATTRS) \ 5173 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5174 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5175 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5176 #include "clang/Basic/BuiltinsNEON.def" 5177 5178 #define BUILTIN(ID, TYPE, ATTRS) \ 5179 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5180 #define LANGBUILTIN(ID, TYPE, ATTRS, LANG) \ 5181 { #ID, TYPE, ATTRS, nullptr, LANG, nullptr }, 5182 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5183 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5184 #include "clang/Basic/BuiltinsARM.def" 5185 }; 5186 5187 class ARMleTargetInfo : public ARMTargetInfo { 5188 public: 5189 ARMleTargetInfo(const llvm::Triple &Triple) 5190 : ARMTargetInfo(Triple, false) { } 5191 void getTargetDefines(const LangOptions &Opts, 5192 MacroBuilder &Builder) const override { 5193 Builder.defineMacro("__ARMEL__"); 5194 ARMTargetInfo::getTargetDefines(Opts, Builder); 5195 } 5196 }; 5197 5198 class ARMbeTargetInfo : public ARMTargetInfo { 5199 public: 5200 ARMbeTargetInfo(const llvm::Triple &Triple) 5201 : ARMTargetInfo(Triple, true) { } 5202 void getTargetDefines(const LangOptions &Opts, 5203 MacroBuilder &Builder) const override { 5204 Builder.defineMacro("__ARMEB__"); 5205 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5206 ARMTargetInfo::getTargetDefines(Opts, Builder); 5207 } 5208 }; 5209 5210 class WindowsARMTargetInfo : public WindowsTargetInfo<ARMleTargetInfo> { 5211 const llvm::Triple Triple; 5212 public: 5213 WindowsARMTargetInfo(const llvm::Triple &Triple) 5214 : WindowsTargetInfo<ARMleTargetInfo>(Triple), Triple(Triple) { 5215 WCharType = UnsignedShort; 5216 SizeType = UnsignedInt; 5217 UserLabelPrefix = ""; 5218 } 5219 void getVisualStudioDefines(const LangOptions &Opts, 5220 MacroBuilder &Builder) const { 5221 WindowsTargetInfo<ARMleTargetInfo>::getVisualStudioDefines(Opts, Builder); 5222 5223 // FIXME: this is invalid for WindowsCE 5224 Builder.defineMacro("_M_ARM_NT", "1"); 5225 Builder.defineMacro("_M_ARMT", "_M_ARM"); 5226 Builder.defineMacro("_M_THUMB", "_M_ARM"); 5227 5228 assert((Triple.getArch() == llvm::Triple::arm || 5229 Triple.getArch() == llvm::Triple::thumb) && 5230 "invalid architecture for Windows ARM target info"); 5231 unsigned Offset = Triple.getArch() == llvm::Triple::arm ? 4 : 6; 5232 Builder.defineMacro("_M_ARM", Triple.getArchName().substr(Offset)); 5233 5234 // TODO map the complete set of values 5235 // 31: VFPv3 40: VFPv4 5236 Builder.defineMacro("_M_ARM_FP", "31"); 5237 } 5238 BuiltinVaListKind getBuiltinVaListKind() const override { 5239 return TargetInfo::CharPtrBuiltinVaList; 5240 } 5241 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 5242 switch (CC) { 5243 case CC_X86StdCall: 5244 case CC_X86ThisCall: 5245 case CC_X86FastCall: 5246 case CC_X86VectorCall: 5247 return CCCR_Ignore; 5248 case CC_C: 5249 return CCCR_OK; 5250 default: 5251 return CCCR_Warning; 5252 } 5253 } 5254 }; 5255 5256 // Windows ARM + Itanium C++ ABI Target 5257 class ItaniumWindowsARMleTargetInfo : public WindowsARMTargetInfo { 5258 public: 5259 ItaniumWindowsARMleTargetInfo(const llvm::Triple &Triple) 5260 : WindowsARMTargetInfo(Triple) { 5261 TheCXXABI.set(TargetCXXABI::GenericARM); 5262 } 5263 5264 void getTargetDefines(const LangOptions &Opts, 5265 MacroBuilder &Builder) const override { 5266 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5267 5268 if (Opts.MSVCCompat) 5269 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5270 } 5271 }; 5272 5273 // Windows ARM, MS (C++) ABI 5274 class MicrosoftARMleTargetInfo : public WindowsARMTargetInfo { 5275 public: 5276 MicrosoftARMleTargetInfo(const llvm::Triple &Triple) 5277 : WindowsARMTargetInfo(Triple) { 5278 TheCXXABI.set(TargetCXXABI::Microsoft); 5279 } 5280 5281 void getTargetDefines(const LangOptions &Opts, 5282 MacroBuilder &Builder) const override { 5283 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5284 WindowsARMTargetInfo::getVisualStudioDefines(Opts, Builder); 5285 } 5286 }; 5287 5288 // ARM MinGW target 5289 class MinGWARMTargetInfo : public WindowsARMTargetInfo { 5290 public: 5291 MinGWARMTargetInfo(const llvm::Triple &Triple) 5292 : WindowsARMTargetInfo(Triple) { 5293 TheCXXABI.set(TargetCXXABI::GenericARM); 5294 } 5295 5296 void getTargetDefines(const LangOptions &Opts, 5297 MacroBuilder &Builder) const override { 5298 WindowsARMTargetInfo::getTargetDefines(Opts, Builder); 5299 DefineStd(Builder, "WIN32", Opts); 5300 DefineStd(Builder, "WINNT", Opts); 5301 Builder.defineMacro("_ARM_"); 5302 addMinGWDefines(Opts, Builder); 5303 } 5304 }; 5305 5306 // ARM Cygwin target 5307 class CygwinARMTargetInfo : public ARMleTargetInfo { 5308 public: 5309 CygwinARMTargetInfo(const llvm::Triple &Triple) : ARMleTargetInfo(Triple) { 5310 TLSSupported = false; 5311 WCharType = UnsignedShort; 5312 DoubleAlign = LongLongAlign = 64; 5313 DataLayoutString = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"; 5314 } 5315 void getTargetDefines(const LangOptions &Opts, 5316 MacroBuilder &Builder) const override { 5317 ARMleTargetInfo::getTargetDefines(Opts, Builder); 5318 Builder.defineMacro("_ARM_"); 5319 Builder.defineMacro("__CYGWIN__"); 5320 Builder.defineMacro("__CYGWIN32__"); 5321 DefineStd(Builder, "unix", Opts); 5322 if (Opts.CPlusPlus) 5323 Builder.defineMacro("_GNU_SOURCE"); 5324 } 5325 }; 5326 5327 class DarwinARMTargetInfo : 5328 public DarwinTargetInfo<ARMleTargetInfo> { 5329 protected: 5330 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5331 MacroBuilder &Builder) const override { 5332 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5333 } 5334 5335 public: 5336 DarwinARMTargetInfo(const llvm::Triple &Triple) 5337 : DarwinTargetInfo<ARMleTargetInfo>(Triple) { 5338 HasAlignMac68kSupport = true; 5339 // iOS always has 64-bit atomic instructions. 5340 // FIXME: This should be based off of the target features in 5341 // ARMleTargetInfo. 5342 MaxAtomicInlineWidth = 64; 5343 5344 if (Triple.isWatchABI()) { 5345 // Darwin on iOS uses a variant of the ARM C++ ABI. 5346 TheCXXABI.set(TargetCXXABI::WatchOS); 5347 5348 // The 32-bit ABI is silent on what ptrdiff_t should be, but given that 5349 // size_t is long, it's a bit weird for it to be int. 5350 PtrDiffType = SignedLong; 5351 5352 // BOOL should be a real boolean on the new ABI 5353 UseSignedCharForObjCBool = false; 5354 } else 5355 TheCXXABI.set(TargetCXXABI::iOS); 5356 } 5357 }; 5358 5359 class AArch64TargetInfo : public TargetInfo { 5360 virtual void setDataLayoutString() = 0; 5361 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5362 static const char *const GCCRegNames[]; 5363 5364 enum FPUModeEnum { 5365 FPUMode, 5366 NeonMode 5367 }; 5368 5369 unsigned FPU; 5370 unsigned CRC; 5371 unsigned Crypto; 5372 unsigned Unaligned; 5373 unsigned V8_1A; 5374 5375 static const Builtin::Info BuiltinInfo[]; 5376 5377 std::string ABI; 5378 5379 public: 5380 AArch64TargetInfo(const llvm::Triple &Triple) 5381 : TargetInfo(Triple), ABI("aapcs") { 5382 5383 if (getTriple().getOS() == llvm::Triple::NetBSD) { 5384 WCharType = SignedInt; 5385 5386 // NetBSD apparently prefers consistency across ARM targets to consistency 5387 // across 64-bit targets. 5388 Int64Type = SignedLongLong; 5389 IntMaxType = SignedLongLong; 5390 } else { 5391 WCharType = UnsignedInt; 5392 Int64Type = SignedLong; 5393 IntMaxType = SignedLong; 5394 } 5395 5396 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 5397 MaxVectorAlign = 128; 5398 MaxAtomicInlineWidth = 128; 5399 MaxAtomicPromoteWidth = 128; 5400 5401 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 128; 5402 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5403 5404 // {} in inline assembly are neon specifiers, not assembly variant 5405 // specifiers. 5406 NoAsmVariants = true; 5407 5408 // AAPCS gives rules for bitfields. 7.1.7 says: "The container type 5409 // contributes to the alignment of the containing aggregate in the same way 5410 // a plain (non bit-field) member of that type would, without exception for 5411 // zero-sized or anonymous bit-fields." 5412 assert(UseBitFieldTypeAlignment && "bitfields affect type alignment"); 5413 UseZeroLengthBitfieldAlignment = true; 5414 5415 // AArch64 targets default to using the ARM C++ ABI. 5416 TheCXXABI.set(TargetCXXABI::GenericAArch64); 5417 } 5418 5419 StringRef getABI() const override { return ABI; } 5420 bool setABI(const std::string &Name) override { 5421 if (Name != "aapcs" && Name != "darwinpcs") 5422 return false; 5423 5424 ABI = Name; 5425 return true; 5426 } 5427 5428 bool setCPU(const std::string &Name) override { 5429 bool CPUKnown = llvm::StringSwitch<bool>(Name) 5430 .Case("generic", true) 5431 .Cases("cortex-a53", "cortex-a57", "cortex-a72", 5432 "cortex-a35", "exynos-m1", true) 5433 .Case("cyclone", true) 5434 .Case("kryo", true) 5435 .Default(false); 5436 return CPUKnown; 5437 } 5438 5439 void getTargetDefines(const LangOptions &Opts, 5440 MacroBuilder &Builder) const override { 5441 // Target identification. 5442 Builder.defineMacro("__aarch64__"); 5443 5444 // Target properties. 5445 Builder.defineMacro("_LP64"); 5446 Builder.defineMacro("__LP64__"); 5447 5448 // ACLE predefines. Many can only have one possible value on v8 AArch64. 5449 Builder.defineMacro("__ARM_ACLE", "200"); 5450 Builder.defineMacro("__ARM_ARCH", "8"); 5451 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 5452 5453 Builder.defineMacro("__ARM_64BIT_STATE", "1"); 5454 Builder.defineMacro("__ARM_PCS_AAPCS64", "1"); 5455 Builder.defineMacro("__ARM_ARCH_ISA_A64", "1"); 5456 5457 Builder.defineMacro("__ARM_FEATURE_CLZ", "1"); 5458 Builder.defineMacro("__ARM_FEATURE_FMA", "1"); 5459 Builder.defineMacro("__ARM_FEATURE_LDREX", "0xF"); 5460 Builder.defineMacro("__ARM_FEATURE_IDIV", "1"); // As specified in ACLE 5461 Builder.defineMacro("__ARM_FEATURE_DIV"); // For backwards compatibility 5462 Builder.defineMacro("__ARM_FEATURE_NUMERIC_MAXMIN", "1"); 5463 Builder.defineMacro("__ARM_FEATURE_DIRECTED_ROUNDING", "1"); 5464 5465 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 5466 5467 // 0xe implies support for half, single and double precision operations. 5468 Builder.defineMacro("__ARM_FP", "0xE"); 5469 5470 // PCS specifies this for SysV variants, which is all we support. Other ABIs 5471 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 5472 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE", "1"); 5473 Builder.defineMacro("__ARM_FP16_ARGS", "1"); 5474 5475 if (Opts.UnsafeFPMath) 5476 Builder.defineMacro("__ARM_FP_FAST", "1"); 5477 5478 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", Opts.ShortWChar ? "2" : "4"); 5479 5480 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 5481 Opts.ShortEnums ? "1" : "4"); 5482 5483 if (FPU == NeonMode) { 5484 Builder.defineMacro("__ARM_NEON", "1"); 5485 // 64-bit NEON supports half, single and double precision operations. 5486 Builder.defineMacro("__ARM_NEON_FP", "0xE"); 5487 } 5488 5489 if (CRC) 5490 Builder.defineMacro("__ARM_FEATURE_CRC32", "1"); 5491 5492 if (Crypto) 5493 Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1"); 5494 5495 if (Unaligned) 5496 Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1"); 5497 5498 if (V8_1A) 5499 Builder.defineMacro("__ARM_FEATURE_QRDMX", "1"); 5500 5501 // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work. 5502 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 5503 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 5504 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 5505 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 5506 } 5507 5508 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5509 return llvm::makeArrayRef(BuiltinInfo, 5510 clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin); 5511 } 5512 5513 bool hasFeature(StringRef Feature) const override { 5514 return Feature == "aarch64" || 5515 Feature == "arm64" || 5516 Feature == "arm" || 5517 (Feature == "neon" && FPU == NeonMode); 5518 } 5519 5520 bool handleTargetFeatures(std::vector<std::string> &Features, 5521 DiagnosticsEngine &Diags) override { 5522 FPU = FPUMode; 5523 CRC = 0; 5524 Crypto = 0; 5525 Unaligned = 1; 5526 V8_1A = 0; 5527 5528 for (const auto &Feature : Features) { 5529 if (Feature == "+neon") 5530 FPU = NeonMode; 5531 if (Feature == "+crc") 5532 CRC = 1; 5533 if (Feature == "+crypto") 5534 Crypto = 1; 5535 if (Feature == "+strict-align") 5536 Unaligned = 0; 5537 if (Feature == "+v8.1a") 5538 V8_1A = 1; 5539 } 5540 5541 setDataLayoutString(); 5542 5543 return true; 5544 } 5545 5546 bool isCLZForZeroUndef() const override { return false; } 5547 5548 BuiltinVaListKind getBuiltinVaListKind() const override { 5549 return TargetInfo::AArch64ABIBuiltinVaList; 5550 } 5551 5552 ArrayRef<const char *> getGCCRegNames() const override; 5553 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5554 5555 bool validateAsmConstraint(const char *&Name, 5556 TargetInfo::ConstraintInfo &Info) const override { 5557 switch (*Name) { 5558 default: 5559 return false; 5560 case 'w': // Floating point and SIMD registers (V0-V31) 5561 Info.setAllowsRegister(); 5562 return true; 5563 case 'I': // Constant that can be used with an ADD instruction 5564 case 'J': // Constant that can be used with a SUB instruction 5565 case 'K': // Constant that can be used with a 32-bit logical instruction 5566 case 'L': // Constant that can be used with a 64-bit logical instruction 5567 case 'M': // Constant that can be used as a 32-bit MOV immediate 5568 case 'N': // Constant that can be used as a 64-bit MOV immediate 5569 case 'Y': // Floating point constant zero 5570 case 'Z': // Integer constant zero 5571 return true; 5572 case 'Q': // A memory reference with base register and no offset 5573 Info.setAllowsMemory(); 5574 return true; 5575 case 'S': // A symbolic address 5576 Info.setAllowsRegister(); 5577 return true; 5578 case 'U': 5579 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes. 5580 // Utf: A memory address suitable for ldp/stp in TF mode. 5581 // Usa: An absolute symbolic address. 5582 // Ush: The high part (bits 32:12) of a pc-relative symbolic address. 5583 llvm_unreachable("FIXME: Unimplemented support for U* constraints."); 5584 case 'z': // Zero register, wzr or xzr 5585 Info.setAllowsRegister(); 5586 return true; 5587 case 'x': // Floating point and SIMD registers (V0-V15) 5588 Info.setAllowsRegister(); 5589 return true; 5590 } 5591 return false; 5592 } 5593 5594 bool 5595 validateConstraintModifier(StringRef Constraint, char Modifier, unsigned Size, 5596 std::string &SuggestedModifier) const override { 5597 // Strip off constraint modifiers. 5598 while (Constraint[0] == '=' || Constraint[0] == '+' || Constraint[0] == '&') 5599 Constraint = Constraint.substr(1); 5600 5601 switch (Constraint[0]) { 5602 default: 5603 return true; 5604 case 'z': 5605 case 'r': { 5606 switch (Modifier) { 5607 case 'x': 5608 case 'w': 5609 // For now assume that the person knows what they're 5610 // doing with the modifier. 5611 return true; 5612 default: 5613 // By default an 'r' constraint will be in the 'x' 5614 // registers. 5615 if (Size == 64) 5616 return true; 5617 5618 SuggestedModifier = "w"; 5619 return false; 5620 } 5621 } 5622 } 5623 } 5624 5625 const char *getClobbers() const override { return ""; } 5626 5627 int getEHDataRegisterNumber(unsigned RegNo) const override { 5628 if (RegNo == 0) 5629 return 0; 5630 if (RegNo == 1) 5631 return 1; 5632 return -1; 5633 } 5634 }; 5635 5636 const char *const AArch64TargetInfo::GCCRegNames[] = { 5637 // 32-bit Integer registers 5638 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", "w8", "w9", "w10", 5639 "w11", "w12", "w13", "w14", "w15", "w16", "w17", "w18", "w19", "w20", "w21", 5640 "w22", "w23", "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", 5641 5642 // 64-bit Integer registers 5643 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", "x8", "x9", "x10", 5644 "x11", "x12", "x13", "x14", "x15", "x16", "x17", "x18", "x19", "x20", "x21", 5645 "x22", "x23", "x24", "x25", "x26", "x27", "x28", "fp", "lr", "sp", 5646 5647 // 32-bit floating point regsisters 5648 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", 5649 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", "s21", 5650 "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 5651 5652 // 64-bit floating point regsisters 5653 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "d8", "d9", "d10", 5654 "d11", "d12", "d13", "d14", "d15", "d16", "d17", "d18", "d19", "d20", "d21", 5655 "d22", "d23", "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 5656 5657 // Vector registers 5658 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", 5659 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", "v21", 5660 "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31" 5661 }; 5662 5663 ArrayRef<const char *> AArch64TargetInfo::getGCCRegNames() const { 5664 return llvm::makeArrayRef(GCCRegNames); 5665 } 5666 5667 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 5668 { { "w31" }, "wsp" }, 5669 { { "x29" }, "fp" }, 5670 { { "x30" }, "lr" }, 5671 { { "x31" }, "sp" }, 5672 // The S/D/Q and W/X registers overlap, but aren't really aliases; we 5673 // don't want to substitute one of these for a different-sized one. 5674 }; 5675 5676 ArrayRef<TargetInfo::GCCRegAlias> AArch64TargetInfo::getGCCRegAliases() const { 5677 return llvm::makeArrayRef(GCCRegAliases); 5678 } 5679 5680 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 5681 #define BUILTIN(ID, TYPE, ATTRS) \ 5682 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5683 #include "clang/Basic/BuiltinsNEON.def" 5684 5685 #define BUILTIN(ID, TYPE, ATTRS) \ 5686 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5687 #include "clang/Basic/BuiltinsAArch64.def" 5688 }; 5689 5690 class AArch64leTargetInfo : public AArch64TargetInfo { 5691 void setDataLayoutString() override { 5692 if (getTriple().isOSBinFormatMachO()) 5693 DataLayoutString = "e-m:o-i64:64-i128:128-n32:64-S128"; 5694 else 5695 DataLayoutString = "e-m:e-i64:64-i128:128-n32:64-S128"; 5696 } 5697 5698 public: 5699 AArch64leTargetInfo(const llvm::Triple &Triple) 5700 : AArch64TargetInfo(Triple) { 5701 BigEndian = false; 5702 } 5703 void getTargetDefines(const LangOptions &Opts, 5704 MacroBuilder &Builder) const override { 5705 Builder.defineMacro("__AARCH64EL__"); 5706 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5707 } 5708 }; 5709 5710 class AArch64beTargetInfo : public AArch64TargetInfo { 5711 void setDataLayoutString() override { 5712 assert(!getTriple().isOSBinFormatMachO()); 5713 DataLayoutString = "E-m:e-i64:64-i128:128-n32:64-S128"; 5714 } 5715 5716 public: 5717 AArch64beTargetInfo(const llvm::Triple &Triple) 5718 : AArch64TargetInfo(Triple) { } 5719 void getTargetDefines(const LangOptions &Opts, 5720 MacroBuilder &Builder) const override { 5721 Builder.defineMacro("__AARCH64EB__"); 5722 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 5723 Builder.defineMacro("__ARM_BIG_ENDIAN"); 5724 AArch64TargetInfo::getTargetDefines(Opts, Builder); 5725 } 5726 }; 5727 5728 class DarwinAArch64TargetInfo : public DarwinTargetInfo<AArch64leTargetInfo> { 5729 protected: 5730 void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 5731 MacroBuilder &Builder) const override { 5732 Builder.defineMacro("__AARCH64_SIMD__"); 5733 Builder.defineMacro("__ARM64_ARCH_8__"); 5734 Builder.defineMacro("__ARM_NEON__"); 5735 Builder.defineMacro("__LITTLE_ENDIAN__"); 5736 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5737 Builder.defineMacro("__arm64", "1"); 5738 Builder.defineMacro("__arm64__", "1"); 5739 5740 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 5741 } 5742 5743 public: 5744 DarwinAArch64TargetInfo(const llvm::Triple &Triple) 5745 : DarwinTargetInfo<AArch64leTargetInfo>(Triple) { 5746 Int64Type = SignedLongLong; 5747 WCharType = SignedInt; 5748 UseSignedCharForObjCBool = false; 5749 5750 LongDoubleWidth = LongDoubleAlign = SuitableAlign = 64; 5751 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5752 5753 TheCXXABI.set(TargetCXXABI::iOS64); 5754 } 5755 5756 BuiltinVaListKind getBuiltinVaListKind() const override { 5757 return TargetInfo::CharPtrBuiltinVaList; 5758 } 5759 }; 5760 5761 // Hexagon abstract base class 5762 class HexagonTargetInfo : public TargetInfo { 5763 static const Builtin::Info BuiltinInfo[]; 5764 static const char * const GCCRegNames[]; 5765 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5766 std::string CPU; 5767 bool HasHVX, HasHVXDouble; 5768 5769 public: 5770 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5771 BigEndian = false; 5772 // Specify the vector alignment explicitly. For v512x1, the calculated 5773 // alignment would be 512*alignment(i1), which is 512 bytes, instead of 5774 // the required minimum of 64 bytes. 5775 DataLayoutString = "e-m:e-p:32:32:32-a:0-n16:32-" 5776 "i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-" 5777 "v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"; 5778 SizeType = UnsignedInt; 5779 PtrDiffType = SignedInt; 5780 IntPtrType = SignedInt; 5781 5782 // {} in inline assembly are packet specifiers, not assembly variant 5783 // specifiers. 5784 NoAsmVariants = true; 5785 5786 LargeArrayMinWidth = 64; 5787 LargeArrayAlign = 64; 5788 UseBitFieldTypeAlignment = true; 5789 ZeroLengthBitfieldBoundary = 32; 5790 HasHVX = HasHVXDouble = false; 5791 } 5792 5793 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5794 return llvm::makeArrayRef(BuiltinInfo, 5795 clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin); 5796 } 5797 5798 bool validateAsmConstraint(const char *&Name, 5799 TargetInfo::ConstraintInfo &Info) const override { 5800 return true; 5801 } 5802 5803 void getTargetDefines(const LangOptions &Opts, 5804 MacroBuilder &Builder) const override; 5805 5806 bool isCLZForZeroUndef() const override { return false; } 5807 5808 bool hasFeature(StringRef Feature) const override { 5809 return llvm::StringSwitch<bool>(Feature) 5810 .Case("hexagon", true) 5811 .Case("hvx", HasHVX) 5812 .Case("hvx-double", HasHVXDouble) 5813 .Default(false); 5814 } 5815 5816 bool initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 5817 StringRef CPU, const std::vector<std::string> &FeaturesVec) 5818 const override; 5819 5820 bool handleTargetFeatures(std::vector<std::string> &Features, 5821 DiagnosticsEngine &Diags) override; 5822 5823 BuiltinVaListKind getBuiltinVaListKind() const override { 5824 return TargetInfo::CharPtrBuiltinVaList; 5825 } 5826 ArrayRef<const char *> getGCCRegNames() const override; 5827 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5828 const char *getClobbers() const override { 5829 return ""; 5830 } 5831 5832 static const char *getHexagonCPUSuffix(StringRef Name) { 5833 return llvm::StringSwitch<const char*>(Name) 5834 .Case("hexagonv4", "4") 5835 .Case("hexagonv5", "5") 5836 .Case("hexagonv55", "55") 5837 .Case("hexagonv60", "60") 5838 .Default(nullptr); 5839 } 5840 5841 bool setCPU(const std::string &Name) override { 5842 if (!getHexagonCPUSuffix(Name)) 5843 return false; 5844 CPU = Name; 5845 return true; 5846 } 5847 5848 int getEHDataRegisterNumber(unsigned RegNo) const override { 5849 return RegNo < 2 ? RegNo : -1; 5850 } 5851 }; 5852 5853 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 5854 MacroBuilder &Builder) const { 5855 Builder.defineMacro("__qdsp6__", "1"); 5856 Builder.defineMacro("__hexagon__", "1"); 5857 5858 if (CPU == "hexagonv4") { 5859 Builder.defineMacro("__HEXAGON_V4__"); 5860 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 5861 if (Opts.HexagonQdsp6Compat) { 5862 Builder.defineMacro("__QDSP6_V4__"); 5863 Builder.defineMacro("__QDSP6_ARCH__", "4"); 5864 } 5865 } else if (CPU == "hexagonv5") { 5866 Builder.defineMacro("__HEXAGON_V5__"); 5867 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 5868 if(Opts.HexagonQdsp6Compat) { 5869 Builder.defineMacro("__QDSP6_V5__"); 5870 Builder.defineMacro("__QDSP6_ARCH__", "5"); 5871 } 5872 } else if (CPU == "hexagonv60") { 5873 Builder.defineMacro("__HEXAGON_V60__"); 5874 Builder.defineMacro("__HEXAGON_ARCH__", "60"); 5875 Builder.defineMacro("__QDSP6_V60__"); 5876 Builder.defineMacro("__QDSP6_ARCH__", "60"); 5877 } 5878 } 5879 5880 bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 5881 DiagnosticsEngine &Diags) { 5882 for (auto &F : Features) { 5883 if (F == "+hvx") 5884 HasHVX = true; 5885 else if (F == "-hvx") 5886 HasHVX = HasHVXDouble = false; 5887 else if (F == "+hvx-double") 5888 HasHVX = HasHVXDouble = true; 5889 else if (F == "-hvx-double") 5890 HasHVXDouble = false; 5891 } 5892 return true; 5893 } 5894 5895 bool HexagonTargetInfo::initFeatureMap(llvm::StringMap<bool> &Features, 5896 DiagnosticsEngine &Diags, StringRef CPU, 5897 const std::vector<std::string> &FeaturesVec) const { 5898 // Default for v60: -hvx, -hvx-double. 5899 Features["hvx"] = false; 5900 Features["hvx-double"] = false; 5901 5902 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 5903 } 5904 5905 5906 const char *const HexagonTargetInfo::GCCRegNames[] = { 5907 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5908 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 5909 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 5910 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 5911 "p0", "p1", "p2", "p3", 5912 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 5913 }; 5914 5915 ArrayRef<const char*> HexagonTargetInfo::getGCCRegNames() const { 5916 return llvm::makeArrayRef(GCCRegNames); 5917 } 5918 5919 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 5920 { { "sp" }, "r29" }, 5921 { { "fp" }, "r30" }, 5922 { { "lr" }, "r31" }, 5923 }; 5924 5925 ArrayRef<TargetInfo::GCCRegAlias> HexagonTargetInfo::getGCCRegAliases() const { 5926 return llvm::makeArrayRef(GCCRegAliases); 5927 } 5928 5929 5930 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 5931 #define BUILTIN(ID, TYPE, ATTRS) \ 5932 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 5933 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 5934 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 5935 #include "clang/Basic/BuiltinsHexagon.def" 5936 }; 5937 5938 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 5939 class SparcTargetInfo : public TargetInfo { 5940 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 5941 static const char * const GCCRegNames[]; 5942 bool SoftFloat; 5943 public: 5944 SparcTargetInfo(const llvm::Triple &Triple) 5945 : TargetInfo(Triple), SoftFloat(false) {} 5946 5947 bool handleTargetFeatures(std::vector<std::string> &Features, 5948 DiagnosticsEngine &Diags) override { 5949 // The backend doesn't actually handle soft float yet, but in case someone 5950 // is using the support for the front end continue to support it. 5951 auto Feature = std::find(Features.begin(), Features.end(), "+soft-float"); 5952 if (Feature != Features.end()) { 5953 SoftFloat = true; 5954 Features.erase(Feature); 5955 } 5956 return true; 5957 } 5958 void getTargetDefines(const LangOptions &Opts, 5959 MacroBuilder &Builder) const override { 5960 DefineStd(Builder, "sparc", Opts); 5961 Builder.defineMacro("__REGISTER_PREFIX__", ""); 5962 5963 if (SoftFloat) 5964 Builder.defineMacro("SOFT_FLOAT", "1"); 5965 } 5966 5967 bool hasFeature(StringRef Feature) const override { 5968 return llvm::StringSwitch<bool>(Feature) 5969 .Case("softfloat", SoftFloat) 5970 .Case("sparc", true) 5971 .Default(false); 5972 } 5973 5974 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 5975 // FIXME: Implement! 5976 return None; 5977 } 5978 BuiltinVaListKind getBuiltinVaListKind() const override { 5979 return TargetInfo::VoidPtrBuiltinVaList; 5980 } 5981 ArrayRef<const char *> getGCCRegNames() const override; 5982 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 5983 bool validateAsmConstraint(const char *&Name, 5984 TargetInfo::ConstraintInfo &info) const override { 5985 // FIXME: Implement! 5986 switch (*Name) { 5987 case 'I': // Signed 13-bit constant 5988 case 'J': // Zero 5989 case 'K': // 32-bit constant with the low 12 bits clear 5990 case 'L': // A constant in the range supported by movcc (11-bit signed imm) 5991 case 'M': // A constant in the range supported by movrcc (19-bit signed imm) 5992 case 'N': // Same as 'K' but zext (required for SIMode) 5993 case 'O': // The constant 4096 5994 return true; 5995 } 5996 return false; 5997 } 5998 const char *getClobbers() const override { 5999 // FIXME: Implement! 6000 return ""; 6001 } 6002 6003 // No Sparc V7 for now, the backend doesn't support it anyway. 6004 enum CPUKind { 6005 CK_GENERIC, 6006 CK_V8, 6007 CK_SUPERSPARC, 6008 CK_SPARCLITE, 6009 CK_F934, 6010 CK_HYPERSPARC, 6011 CK_SPARCLITE86X, 6012 CK_SPARCLET, 6013 CK_TSC701, 6014 CK_V9, 6015 CK_ULTRASPARC, 6016 CK_ULTRASPARC3, 6017 CK_NIAGARA, 6018 CK_NIAGARA2, 6019 CK_NIAGARA3, 6020 CK_NIAGARA4 6021 } CPU = CK_GENERIC; 6022 6023 enum CPUGeneration { 6024 CG_V8, 6025 CG_V9, 6026 }; 6027 6028 CPUGeneration getCPUGeneration(CPUKind Kind) const { 6029 switch (Kind) { 6030 case CK_GENERIC: 6031 case CK_V8: 6032 case CK_SUPERSPARC: 6033 case CK_SPARCLITE: 6034 case CK_F934: 6035 case CK_HYPERSPARC: 6036 case CK_SPARCLITE86X: 6037 case CK_SPARCLET: 6038 case CK_TSC701: 6039 return CG_V8; 6040 case CK_V9: 6041 case CK_ULTRASPARC: 6042 case CK_ULTRASPARC3: 6043 case CK_NIAGARA: 6044 case CK_NIAGARA2: 6045 case CK_NIAGARA3: 6046 case CK_NIAGARA4: 6047 return CG_V9; 6048 } 6049 llvm_unreachable("Unexpected CPU kind"); 6050 } 6051 6052 CPUKind getCPUKind(StringRef Name) const { 6053 return llvm::StringSwitch<CPUKind>(Name) 6054 .Case("v8", CK_V8) 6055 .Case("supersparc", CK_SUPERSPARC) 6056 .Case("sparclite", CK_SPARCLITE) 6057 .Case("f934", CK_F934) 6058 .Case("hypersparc", CK_HYPERSPARC) 6059 .Case("sparclite86x", CK_SPARCLITE86X) 6060 .Case("sparclet", CK_SPARCLET) 6061 .Case("tsc701", CK_TSC701) 6062 .Case("v9", CK_V9) 6063 .Case("ultrasparc", CK_ULTRASPARC) 6064 .Case("ultrasparc3", CK_ULTRASPARC3) 6065 .Case("niagara", CK_NIAGARA) 6066 .Case("niagara2", CK_NIAGARA2) 6067 .Case("niagara3", CK_NIAGARA3) 6068 .Case("niagara4", CK_NIAGARA4) 6069 .Default(CK_GENERIC); 6070 } 6071 6072 bool setCPU(const std::string &Name) override { 6073 CPU = getCPUKind(Name); 6074 return CPU != CK_GENERIC; 6075 } 6076 }; 6077 6078 const char * const SparcTargetInfo::GCCRegNames[] = { 6079 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6080 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6081 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 6082 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 6083 }; 6084 6085 ArrayRef<const char *> SparcTargetInfo::getGCCRegNames() const { 6086 return llvm::makeArrayRef(GCCRegNames); 6087 } 6088 6089 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 6090 { { "g0" }, "r0" }, 6091 { { "g1" }, "r1" }, 6092 { { "g2" }, "r2" }, 6093 { { "g3" }, "r3" }, 6094 { { "g4" }, "r4" }, 6095 { { "g5" }, "r5" }, 6096 { { "g6" }, "r6" }, 6097 { { "g7" }, "r7" }, 6098 { { "o0" }, "r8" }, 6099 { { "o1" }, "r9" }, 6100 { { "o2" }, "r10" }, 6101 { { "o3" }, "r11" }, 6102 { { "o4" }, "r12" }, 6103 { { "o5" }, "r13" }, 6104 { { "o6", "sp" }, "r14" }, 6105 { { "o7" }, "r15" }, 6106 { { "l0" }, "r16" }, 6107 { { "l1" }, "r17" }, 6108 { { "l2" }, "r18" }, 6109 { { "l3" }, "r19" }, 6110 { { "l4" }, "r20" }, 6111 { { "l5" }, "r21" }, 6112 { { "l6" }, "r22" }, 6113 { { "l7" }, "r23" }, 6114 { { "i0" }, "r24" }, 6115 { { "i1" }, "r25" }, 6116 { { "i2" }, "r26" }, 6117 { { "i3" }, "r27" }, 6118 { { "i4" }, "r28" }, 6119 { { "i5" }, "r29" }, 6120 { { "i6", "fp" }, "r30" }, 6121 { { "i7" }, "r31" }, 6122 }; 6123 6124 ArrayRef<TargetInfo::GCCRegAlias> SparcTargetInfo::getGCCRegAliases() const { 6125 return llvm::makeArrayRef(GCCRegAliases); 6126 } 6127 6128 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 6129 class SparcV8TargetInfo : public SparcTargetInfo { 6130 public: 6131 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6132 DataLayoutString = "E-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6133 // NetBSD / OpenBSD use long (same as llvm default); everyone else uses int. 6134 switch (getTriple().getOS()) { 6135 default: 6136 SizeType = UnsignedInt; 6137 IntPtrType = SignedInt; 6138 PtrDiffType = SignedInt; 6139 break; 6140 case llvm::Triple::NetBSD: 6141 case llvm::Triple::OpenBSD: 6142 SizeType = UnsignedLong; 6143 IntPtrType = SignedLong; 6144 PtrDiffType = SignedLong; 6145 break; 6146 } 6147 } 6148 6149 void getTargetDefines(const LangOptions &Opts, 6150 MacroBuilder &Builder) const override { 6151 SparcTargetInfo::getTargetDefines(Opts, Builder); 6152 switch (getCPUGeneration(CPU)) { 6153 case CG_V8: 6154 Builder.defineMacro("__sparcv8"); 6155 if (getTriple().getOS() != llvm::Triple::Solaris) 6156 Builder.defineMacro("__sparcv8__"); 6157 break; 6158 case CG_V9: 6159 Builder.defineMacro("__sparcv9"); 6160 if (getTriple().getOS() != llvm::Triple::Solaris) { 6161 Builder.defineMacro("__sparcv9__"); 6162 Builder.defineMacro("__sparc_v9__"); 6163 } 6164 break; 6165 } 6166 } 6167 }; 6168 6169 // SPARCV8el is the 32-bit little-endian mode selected by Triple::sparcel. 6170 class SparcV8elTargetInfo : public SparcV8TargetInfo { 6171 public: 6172 SparcV8elTargetInfo(const llvm::Triple &Triple) : SparcV8TargetInfo(Triple) { 6173 DataLayoutString = "e-m:e-p:32:32-i64:64-f128:64-n32-S64"; 6174 BigEndian = false; 6175 } 6176 }; 6177 6178 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 6179 class SparcV9TargetInfo : public SparcTargetInfo { 6180 public: 6181 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 6182 // FIXME: Support Sparc quad-precision long double? 6183 DataLayoutString = "E-m:e-i64:64-n32:64-S128"; 6184 // This is an LP64 platform. 6185 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6186 6187 // OpenBSD uses long long for int64_t and intmax_t. 6188 if (getTriple().getOS() == llvm::Triple::OpenBSD) 6189 IntMaxType = SignedLongLong; 6190 else 6191 IntMaxType = SignedLong; 6192 Int64Type = IntMaxType; 6193 6194 // The SPARCv8 System V ABI has long double 128-bits in size, but 64-bit 6195 // aligned. The SPARCv9 SCD 2.4.1 says 16-byte aligned. 6196 LongDoubleWidth = 128; 6197 LongDoubleAlign = 128; 6198 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6199 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6200 } 6201 6202 void getTargetDefines(const LangOptions &Opts, 6203 MacroBuilder &Builder) const override { 6204 SparcTargetInfo::getTargetDefines(Opts, Builder); 6205 Builder.defineMacro("__sparcv9"); 6206 Builder.defineMacro("__arch64__"); 6207 // Solaris doesn't need these variants, but the BSDs do. 6208 if (getTriple().getOS() != llvm::Triple::Solaris) { 6209 Builder.defineMacro("__sparc64__"); 6210 Builder.defineMacro("__sparc_v9__"); 6211 Builder.defineMacro("__sparcv9__"); 6212 } 6213 } 6214 6215 bool setCPU(const std::string &Name) override { 6216 if (!SparcTargetInfo::setCPU(Name)) 6217 return false; 6218 return getCPUGeneration(CPU) == CG_V9; 6219 } 6220 }; 6221 6222 class SystemZTargetInfo : public TargetInfo { 6223 static const Builtin::Info BuiltinInfo[]; 6224 static const char *const GCCRegNames[]; 6225 std::string CPU; 6226 bool HasTransactionalExecution; 6227 bool HasVector; 6228 6229 public: 6230 SystemZTargetInfo(const llvm::Triple &Triple) 6231 : TargetInfo(Triple), CPU("z10"), HasTransactionalExecution(false), 6232 HasVector(false) { 6233 IntMaxType = SignedLong; 6234 Int64Type = SignedLong; 6235 TLSSupported = true; 6236 IntWidth = IntAlign = 32; 6237 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 6238 PointerWidth = PointerAlign = 64; 6239 LongDoubleWidth = 128; 6240 LongDoubleAlign = 64; 6241 LongDoubleFormat = &llvm::APFloat::IEEEquad; 6242 DefaultAlignForAttributeAligned = 64; 6243 MinGlobalAlign = 16; 6244 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-a:8:16-n32:64"; 6245 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 6246 } 6247 void getTargetDefines(const LangOptions &Opts, 6248 MacroBuilder &Builder) const override { 6249 Builder.defineMacro("__s390__"); 6250 Builder.defineMacro("__s390x__"); 6251 Builder.defineMacro("__zarch__"); 6252 Builder.defineMacro("__LONG_DOUBLE_128__"); 6253 6254 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6255 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6256 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6257 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 6258 6259 if (HasTransactionalExecution) 6260 Builder.defineMacro("__HTM__"); 6261 if (Opts.ZVector) 6262 Builder.defineMacro("__VEC__", "10301"); 6263 } 6264 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6265 return llvm::makeArrayRef(BuiltinInfo, 6266 clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin); 6267 } 6268 6269 ArrayRef<const char *> getGCCRegNames() const override; 6270 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6271 // No aliases. 6272 return None; 6273 } 6274 bool validateAsmConstraint(const char *&Name, 6275 TargetInfo::ConstraintInfo &info) const override; 6276 const char *getClobbers() const override { 6277 // FIXME: Is this really right? 6278 return ""; 6279 } 6280 BuiltinVaListKind getBuiltinVaListKind() const override { 6281 return TargetInfo::SystemZBuiltinVaList; 6282 } 6283 bool setCPU(const std::string &Name) override { 6284 CPU = Name; 6285 bool CPUKnown = llvm::StringSwitch<bool>(Name) 6286 .Case("z10", true) 6287 .Case("z196", true) 6288 .Case("zEC12", true) 6289 .Case("z13", true) 6290 .Default(false); 6291 6292 return CPUKnown; 6293 } 6294 bool 6295 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6296 StringRef CPU, 6297 const std::vector<std::string> &FeaturesVec) const override { 6298 if (CPU == "zEC12") 6299 Features["transactional-execution"] = true; 6300 if (CPU == "z13") { 6301 Features["transactional-execution"] = true; 6302 Features["vector"] = true; 6303 } 6304 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6305 } 6306 6307 bool handleTargetFeatures(std::vector<std::string> &Features, 6308 DiagnosticsEngine &Diags) override { 6309 HasTransactionalExecution = false; 6310 for (const auto &Feature : Features) { 6311 if (Feature == "+transactional-execution") 6312 HasTransactionalExecution = true; 6313 else if (Feature == "+vector") 6314 HasVector = true; 6315 } 6316 // If we use the vector ABI, vector types are 64-bit aligned. 6317 if (HasVector) { 6318 MaxVectorAlign = 64; 6319 DataLayoutString = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64" 6320 "-v128:64-a:8:16-n32:64"; 6321 } 6322 return true; 6323 } 6324 6325 bool hasFeature(StringRef Feature) const override { 6326 return llvm::StringSwitch<bool>(Feature) 6327 .Case("systemz", true) 6328 .Case("htm", HasTransactionalExecution) 6329 .Case("vx", HasVector) 6330 .Default(false); 6331 } 6332 6333 StringRef getABI() const override { 6334 if (HasVector) 6335 return "vector"; 6336 return ""; 6337 } 6338 6339 bool useFloat128ManglingForLongDouble() const override { 6340 return true; 6341 } 6342 }; 6343 6344 const Builtin::Info SystemZTargetInfo::BuiltinInfo[] = { 6345 #define BUILTIN(ID, TYPE, ATTRS) \ 6346 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6347 #include "clang/Basic/BuiltinsSystemZ.def" 6348 }; 6349 6350 const char *const SystemZTargetInfo::GCCRegNames[] = { 6351 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6352 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 6353 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 6354 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 6355 }; 6356 6357 ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const { 6358 return llvm::makeArrayRef(GCCRegNames); 6359 } 6360 6361 bool SystemZTargetInfo:: 6362 validateAsmConstraint(const char *&Name, 6363 TargetInfo::ConstraintInfo &Info) const { 6364 switch (*Name) { 6365 default: 6366 return false; 6367 6368 case 'a': // Address register 6369 case 'd': // Data register (equivalent to 'r') 6370 case 'f': // Floating-point register 6371 Info.setAllowsRegister(); 6372 return true; 6373 6374 case 'I': // Unsigned 8-bit constant 6375 case 'J': // Unsigned 12-bit constant 6376 case 'K': // Signed 16-bit constant 6377 case 'L': // Signed 20-bit displacement (on all targets we support) 6378 case 'M': // 0x7fffffff 6379 return true; 6380 6381 case 'Q': // Memory with base and unsigned 12-bit displacement 6382 case 'R': // Likewise, plus an index 6383 case 'S': // Memory with base and signed 20-bit displacement 6384 case 'T': // Likewise, plus an index 6385 Info.setAllowsMemory(); 6386 return true; 6387 } 6388 } 6389 6390 class MSP430TargetInfo : public TargetInfo { 6391 static const char *const GCCRegNames[]; 6392 6393 public: 6394 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6395 BigEndian = false; 6396 TLSSupported = false; 6397 IntWidth = 16; 6398 IntAlign = 16; 6399 LongWidth = 32; 6400 LongLongWidth = 64; 6401 LongAlign = LongLongAlign = 16; 6402 PointerWidth = 16; 6403 PointerAlign = 16; 6404 SuitableAlign = 16; 6405 SizeType = UnsignedInt; 6406 IntMaxType = SignedLongLong; 6407 IntPtrType = SignedInt; 6408 PtrDiffType = SignedInt; 6409 SigAtomicType = SignedLong; 6410 DataLayoutString = "e-m:e-p:16:16-i32:16:32-a:16-n8:16"; 6411 } 6412 void getTargetDefines(const LangOptions &Opts, 6413 MacroBuilder &Builder) const override { 6414 Builder.defineMacro("MSP430"); 6415 Builder.defineMacro("__MSP430__"); 6416 // FIXME: defines for different 'flavours' of MCU 6417 } 6418 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6419 // FIXME: Implement. 6420 return None; 6421 } 6422 bool hasFeature(StringRef Feature) const override { 6423 return Feature == "msp430"; 6424 } 6425 ArrayRef<const char *> getGCCRegNames() const override; 6426 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6427 // No aliases. 6428 return None; 6429 } 6430 bool validateAsmConstraint(const char *&Name, 6431 TargetInfo::ConstraintInfo &info) const override { 6432 // FIXME: implement 6433 switch (*Name) { 6434 case 'K': // the constant 1 6435 case 'L': // constant -1^20 .. 1^19 6436 case 'M': // constant 1-4: 6437 return true; 6438 } 6439 // No target constraints for now. 6440 return false; 6441 } 6442 const char *getClobbers() const override { 6443 // FIXME: Is this really right? 6444 return ""; 6445 } 6446 BuiltinVaListKind getBuiltinVaListKind() const override { 6447 // FIXME: implement 6448 return TargetInfo::CharPtrBuiltinVaList; 6449 } 6450 }; 6451 6452 const char *const MSP430TargetInfo::GCCRegNames[] = { 6453 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 6454 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}; 6455 6456 ArrayRef<const char *> MSP430TargetInfo::getGCCRegNames() const { 6457 return llvm::makeArrayRef(GCCRegNames); 6458 } 6459 6460 // LLVM and Clang cannot be used directly to output native binaries for 6461 // target, but is used to compile C code to llvm bitcode with correct 6462 // type and alignment information. 6463 // 6464 // TCE uses the llvm bitcode as input and uses it for generating customized 6465 // target processor and program binary. TCE co-design environment is 6466 // publicly available in http://tce.cs.tut.fi 6467 6468 static const unsigned TCEOpenCLAddrSpaceMap[] = { 6469 3, // opencl_global 6470 4, // opencl_local 6471 5, // opencl_constant 6472 // FIXME: generic has to be added to the target 6473 0, // opencl_generic 6474 0, // cuda_device 6475 0, // cuda_constant 6476 0 // cuda_shared 6477 }; 6478 6479 class TCETargetInfo : public TargetInfo { 6480 public: 6481 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6482 TLSSupported = false; 6483 IntWidth = 32; 6484 LongWidth = LongLongWidth = 32; 6485 PointerWidth = 32; 6486 IntAlign = 32; 6487 LongAlign = LongLongAlign = 32; 6488 PointerAlign = 32; 6489 SuitableAlign = 32; 6490 SizeType = UnsignedInt; 6491 IntMaxType = SignedLong; 6492 IntPtrType = SignedInt; 6493 PtrDiffType = SignedInt; 6494 FloatWidth = 32; 6495 FloatAlign = 32; 6496 DoubleWidth = 32; 6497 DoubleAlign = 32; 6498 LongDoubleWidth = 32; 6499 LongDoubleAlign = 32; 6500 FloatFormat = &llvm::APFloat::IEEEsingle; 6501 DoubleFormat = &llvm::APFloat::IEEEsingle; 6502 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 6503 DataLayoutString = "E-p:32:32-i8:8:32-i16:16:32-i64:32" 6504 "-f64:32-v64:32-v128:32-a:0:32-n32"; 6505 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 6506 UseAddrSpaceMapMangling = true; 6507 } 6508 6509 void getTargetDefines(const LangOptions &Opts, 6510 MacroBuilder &Builder) const override { 6511 DefineStd(Builder, "tce", Opts); 6512 Builder.defineMacro("__TCE__"); 6513 Builder.defineMacro("__TCE_V1__"); 6514 } 6515 bool hasFeature(StringRef Feature) const override { return Feature == "tce"; } 6516 6517 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6518 const char *getClobbers() const override { return ""; } 6519 BuiltinVaListKind getBuiltinVaListKind() const override { 6520 return TargetInfo::VoidPtrBuiltinVaList; 6521 } 6522 ArrayRef<const char *> getGCCRegNames() const override { return None; } 6523 bool validateAsmConstraint(const char *&Name, 6524 TargetInfo::ConstraintInfo &info) const override { 6525 return true; 6526 } 6527 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6528 return None; 6529 } 6530 }; 6531 6532 class BPFTargetInfo : public TargetInfo { 6533 public: 6534 BPFTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 6535 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 6536 SizeType = UnsignedLong; 6537 PtrDiffType = SignedLong; 6538 IntPtrType = SignedLong; 6539 IntMaxType = SignedLong; 6540 Int64Type = SignedLong; 6541 RegParmMax = 5; 6542 if (Triple.getArch() == llvm::Triple::bpfeb) { 6543 BigEndian = true; 6544 DataLayoutString = "E-m:e-p:64:64-i64:64-n32:64-S128"; 6545 } else { 6546 BigEndian = false; 6547 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 6548 } 6549 MaxAtomicPromoteWidth = 64; 6550 MaxAtomicInlineWidth = 64; 6551 TLSSupported = false; 6552 } 6553 void getTargetDefines(const LangOptions &Opts, 6554 MacroBuilder &Builder) const override { 6555 DefineStd(Builder, "bpf", Opts); 6556 Builder.defineMacro("__BPF__"); 6557 } 6558 bool hasFeature(StringRef Feature) const override { 6559 return Feature == "bpf"; 6560 } 6561 6562 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 6563 const char *getClobbers() const override { 6564 return ""; 6565 } 6566 BuiltinVaListKind getBuiltinVaListKind() const override { 6567 return TargetInfo::VoidPtrBuiltinVaList; 6568 } 6569 ArrayRef<const char *> getGCCRegNames() const override { 6570 return None; 6571 } 6572 bool validateAsmConstraint(const char *&Name, 6573 TargetInfo::ConstraintInfo &info) const override { 6574 return true; 6575 } 6576 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6577 return None; 6578 } 6579 }; 6580 6581 class MipsTargetInfoBase : public TargetInfo { 6582 virtual void setDataLayoutString() = 0; 6583 6584 static const Builtin::Info BuiltinInfo[]; 6585 std::string CPU; 6586 bool IsMips16; 6587 bool IsMicromips; 6588 bool IsNan2008; 6589 bool IsSingleFloat; 6590 enum MipsFloatABI { 6591 HardFloat, SoftFloat 6592 } FloatABI; 6593 enum DspRevEnum { 6594 NoDSP, DSP1, DSP2 6595 } DspRev; 6596 bool HasMSA; 6597 6598 protected: 6599 bool HasFP64; 6600 std::string ABI; 6601 6602 public: 6603 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 6604 const std::string &CPUStr) 6605 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 6606 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 6607 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) { 6608 TheCXXABI.set(TargetCXXABI::GenericMIPS); 6609 } 6610 6611 bool isNaN2008Default() const { 6612 return CPU == "mips32r6" || CPU == "mips64r6"; 6613 } 6614 6615 bool isFP64Default() const { 6616 return CPU == "mips32r6" || ABI == "n32" || ABI == "n64" || ABI == "64"; 6617 } 6618 6619 bool isNan2008() const override { 6620 return IsNan2008; 6621 } 6622 6623 StringRef getABI() const override { return ABI; } 6624 bool setCPU(const std::string &Name) override { 6625 bool IsMips32 = getTriple().getArch() == llvm::Triple::mips || 6626 getTriple().getArch() == llvm::Triple::mipsel; 6627 CPU = Name; 6628 return llvm::StringSwitch<bool>(Name) 6629 .Case("mips1", IsMips32) 6630 .Case("mips2", IsMips32) 6631 .Case("mips3", true) 6632 .Case("mips4", true) 6633 .Case("mips5", true) 6634 .Case("mips32", IsMips32) 6635 .Case("mips32r2", IsMips32) 6636 .Case("mips32r3", IsMips32) 6637 .Case("mips32r5", IsMips32) 6638 .Case("mips32r6", IsMips32) 6639 .Case("mips64", true) 6640 .Case("mips64r2", true) 6641 .Case("mips64r3", true) 6642 .Case("mips64r5", true) 6643 .Case("mips64r6", true) 6644 .Case("octeon", true) 6645 .Case("p5600", true) 6646 .Default(false); 6647 } 6648 const std::string& getCPU() const { return CPU; } 6649 bool 6650 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 6651 StringRef CPU, 6652 const std::vector<std::string> &FeaturesVec) const override { 6653 if (CPU == "octeon") 6654 Features["mips64r2"] = Features["cnmips"] = true; 6655 else 6656 Features[CPU] = true; 6657 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 6658 } 6659 6660 void getTargetDefines(const LangOptions &Opts, 6661 MacroBuilder &Builder) const override { 6662 Builder.defineMacro("__mips__"); 6663 Builder.defineMacro("_mips"); 6664 if (Opts.GNUMode) 6665 Builder.defineMacro("mips"); 6666 6667 Builder.defineMacro("__REGISTER_PREFIX__", ""); 6668 6669 switch (FloatABI) { 6670 case HardFloat: 6671 Builder.defineMacro("__mips_hard_float", Twine(1)); 6672 break; 6673 case SoftFloat: 6674 Builder.defineMacro("__mips_soft_float", Twine(1)); 6675 break; 6676 } 6677 6678 if (IsSingleFloat) 6679 Builder.defineMacro("__mips_single_float", Twine(1)); 6680 6681 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 6682 Builder.defineMacro("_MIPS_FPSET", 6683 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 6684 6685 if (IsMips16) 6686 Builder.defineMacro("__mips16", Twine(1)); 6687 6688 if (IsMicromips) 6689 Builder.defineMacro("__mips_micromips", Twine(1)); 6690 6691 if (IsNan2008) 6692 Builder.defineMacro("__mips_nan2008", Twine(1)); 6693 6694 switch (DspRev) { 6695 default: 6696 break; 6697 case DSP1: 6698 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 6699 Builder.defineMacro("__mips_dsp", Twine(1)); 6700 break; 6701 case DSP2: 6702 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 6703 Builder.defineMacro("__mips_dspr2", Twine(1)); 6704 Builder.defineMacro("__mips_dsp", Twine(1)); 6705 break; 6706 } 6707 6708 if (HasMSA) 6709 Builder.defineMacro("__mips_msa", Twine(1)); 6710 6711 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 6712 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 6713 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 6714 6715 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 6716 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 6717 6718 // These shouldn't be defined for MIPS-I but there's no need to check 6719 // for that since MIPS-I isn't supported. 6720 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 6721 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 6722 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 6723 } 6724 6725 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 6726 return llvm::makeArrayRef(BuiltinInfo, 6727 clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin); 6728 } 6729 bool hasFeature(StringRef Feature) const override { 6730 return llvm::StringSwitch<bool>(Feature) 6731 .Case("mips", true) 6732 .Case("fp64", HasFP64) 6733 .Default(false); 6734 } 6735 BuiltinVaListKind getBuiltinVaListKind() const override { 6736 return TargetInfo::VoidPtrBuiltinVaList; 6737 } 6738 ArrayRef<const char *> getGCCRegNames() const override { 6739 static const char *const GCCRegNames[] = { 6740 // CPU register names 6741 // Must match second column of GCCRegAliases 6742 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 6743 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 6744 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 6745 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 6746 // Floating point register names 6747 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 6748 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 6749 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 6750 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 6751 // Hi/lo and condition register names 6752 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 6753 "$fcc5","$fcc6","$fcc7", 6754 // MSA register names 6755 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 6756 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 6757 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 6758 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 6759 // MSA control register names 6760 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 6761 "$msarequest", "$msamap", "$msaunmap" 6762 }; 6763 return llvm::makeArrayRef(GCCRegNames); 6764 } 6765 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override = 0; 6766 bool validateAsmConstraint(const char *&Name, 6767 TargetInfo::ConstraintInfo &Info) const override { 6768 switch (*Name) { 6769 default: 6770 return false; 6771 case 'r': // CPU registers. 6772 case 'd': // Equivalent to "r" unless generating MIPS16 code. 6773 case 'y': // Equivalent to "r", backward compatibility only. 6774 case 'f': // floating-point registers. 6775 case 'c': // $25 for indirect jumps 6776 case 'l': // lo register 6777 case 'x': // hilo register pair 6778 Info.setAllowsRegister(); 6779 return true; 6780 case 'I': // Signed 16-bit constant 6781 case 'J': // Integer 0 6782 case 'K': // Unsigned 16-bit constant 6783 case 'L': // Signed 32-bit constant, lower 16-bit zeros (for lui) 6784 case 'M': // Constants not loadable via lui, addiu, or ori 6785 case 'N': // Constant -1 to -65535 6786 case 'O': // A signed 15-bit constant 6787 case 'P': // A constant between 1 go 65535 6788 return true; 6789 case 'R': // An address that can be used in a non-macro load or store 6790 Info.setAllowsMemory(); 6791 return true; 6792 case 'Z': 6793 if (Name[1] == 'C') { // An address usable by ll, and sc. 6794 Info.setAllowsMemory(); 6795 Name++; // Skip over 'Z'. 6796 return true; 6797 } 6798 return false; 6799 } 6800 } 6801 6802 std::string convertConstraint(const char *&Constraint) const override { 6803 std::string R; 6804 switch (*Constraint) { 6805 case 'Z': // Two-character constraint; add "^" hint for later parsing. 6806 if (Constraint[1] == 'C') { 6807 R = std::string("^") + std::string(Constraint, 2); 6808 Constraint++; 6809 return R; 6810 } 6811 break; 6812 } 6813 return TargetInfo::convertConstraint(Constraint); 6814 } 6815 6816 const char *getClobbers() const override { 6817 // In GCC, $1 is not widely used in generated code (it's used only in a few 6818 // specific situations), so there is no real need for users to add it to 6819 // the clobbers list if they want to use it in their inline assembly code. 6820 // 6821 // In LLVM, $1 is treated as a normal GPR and is always allocatable during 6822 // code generation, so using it in inline assembly without adding it to the 6823 // clobbers list can cause conflicts between the inline assembly code and 6824 // the surrounding generated code. 6825 // 6826 // Another problem is that LLVM is allowed to choose $1 for inline assembly 6827 // operands, which will conflict with the ".set at" assembler option (which 6828 // we use only for inline assembly, in order to maintain compatibility with 6829 // GCC) and will also conflict with the user's usage of $1. 6830 // 6831 // The easiest way to avoid these conflicts and keep $1 as an allocatable 6832 // register for generated code is to automatically clobber $1 for all inline 6833 // assembly code. 6834 // 6835 // FIXME: We should automatically clobber $1 only for inline assembly code 6836 // which actually uses it. This would allow LLVM to use $1 for inline 6837 // assembly operands if the user's assembly code doesn't use it. 6838 return "~{$1}"; 6839 } 6840 6841 bool handleTargetFeatures(std::vector<std::string> &Features, 6842 DiagnosticsEngine &Diags) override { 6843 IsMips16 = false; 6844 IsMicromips = false; 6845 IsNan2008 = isNaN2008Default(); 6846 IsSingleFloat = false; 6847 FloatABI = HardFloat; 6848 DspRev = NoDSP; 6849 HasFP64 = isFP64Default(); 6850 6851 for (const auto &Feature : Features) { 6852 if (Feature == "+single-float") 6853 IsSingleFloat = true; 6854 else if (Feature == "+soft-float") 6855 FloatABI = SoftFloat; 6856 else if (Feature == "+mips16") 6857 IsMips16 = true; 6858 else if (Feature == "+micromips") 6859 IsMicromips = true; 6860 else if (Feature == "+dsp") 6861 DspRev = std::max(DspRev, DSP1); 6862 else if (Feature == "+dspr2") 6863 DspRev = std::max(DspRev, DSP2); 6864 else if (Feature == "+msa") 6865 HasMSA = true; 6866 else if (Feature == "+fp64") 6867 HasFP64 = true; 6868 else if (Feature == "-fp64") 6869 HasFP64 = false; 6870 else if (Feature == "+nan2008") 6871 IsNan2008 = true; 6872 else if (Feature == "-nan2008") 6873 IsNan2008 = false; 6874 } 6875 6876 setDataLayoutString(); 6877 6878 return true; 6879 } 6880 6881 int getEHDataRegisterNumber(unsigned RegNo) const override { 6882 if (RegNo == 0) return 4; 6883 if (RegNo == 1) return 5; 6884 return -1; 6885 } 6886 6887 bool isCLZForZeroUndef() const override { return false; } 6888 }; 6889 6890 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 6891 #define BUILTIN(ID, TYPE, ATTRS) \ 6892 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 6893 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 6894 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 6895 #include "clang/Basic/BuiltinsMips.def" 6896 }; 6897 6898 class Mips32TargetInfoBase : public MipsTargetInfoBase { 6899 public: 6900 Mips32TargetInfoBase(const llvm::Triple &Triple) 6901 : MipsTargetInfoBase(Triple, "o32", "mips32r2") { 6902 SizeType = UnsignedInt; 6903 PtrDiffType = SignedInt; 6904 Int64Type = SignedLongLong; 6905 IntMaxType = Int64Type; 6906 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 6907 } 6908 bool setABI(const std::string &Name) override { 6909 if (Name == "o32" || Name == "eabi") { 6910 ABI = Name; 6911 return true; 6912 } 6913 return false; 6914 } 6915 void getTargetDefines(const LangOptions &Opts, 6916 MacroBuilder &Builder) const override { 6917 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 6918 6919 Builder.defineMacro("__mips", "32"); 6920 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS32"); 6921 6922 const std::string& CPUStr = getCPU(); 6923 if (CPUStr == "mips32") 6924 Builder.defineMacro("__mips_isa_rev", "1"); 6925 else if (CPUStr == "mips32r2") 6926 Builder.defineMacro("__mips_isa_rev", "2"); 6927 else if (CPUStr == "mips32r3") 6928 Builder.defineMacro("__mips_isa_rev", "3"); 6929 else if (CPUStr == "mips32r5") 6930 Builder.defineMacro("__mips_isa_rev", "5"); 6931 else if (CPUStr == "mips32r6") 6932 Builder.defineMacro("__mips_isa_rev", "6"); 6933 6934 if (ABI == "o32") { 6935 Builder.defineMacro("__mips_o32"); 6936 Builder.defineMacro("_ABIO32", "1"); 6937 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 6938 } 6939 else if (ABI == "eabi") 6940 Builder.defineMacro("__mips_eabi"); 6941 else 6942 llvm_unreachable("Invalid ABI for Mips32."); 6943 } 6944 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 6945 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 6946 { { "at" }, "$1" }, 6947 { { "v0" }, "$2" }, 6948 { { "v1" }, "$3" }, 6949 { { "a0" }, "$4" }, 6950 { { "a1" }, "$5" }, 6951 { { "a2" }, "$6" }, 6952 { { "a3" }, "$7" }, 6953 { { "t0" }, "$8" }, 6954 { { "t1" }, "$9" }, 6955 { { "t2" }, "$10" }, 6956 { { "t3" }, "$11" }, 6957 { { "t4" }, "$12" }, 6958 { { "t5" }, "$13" }, 6959 { { "t6" }, "$14" }, 6960 { { "t7" }, "$15" }, 6961 { { "s0" }, "$16" }, 6962 { { "s1" }, "$17" }, 6963 { { "s2" }, "$18" }, 6964 { { "s3" }, "$19" }, 6965 { { "s4" }, "$20" }, 6966 { { "s5" }, "$21" }, 6967 { { "s6" }, "$22" }, 6968 { { "s7" }, "$23" }, 6969 { { "t8" }, "$24" }, 6970 { { "t9" }, "$25" }, 6971 { { "k0" }, "$26" }, 6972 { { "k1" }, "$27" }, 6973 { { "gp" }, "$28" }, 6974 { { "sp","$sp" }, "$29" }, 6975 { { "fp","$fp" }, "$30" }, 6976 { { "ra" }, "$31" } 6977 }; 6978 return llvm::makeArrayRef(GCCRegAliases); 6979 } 6980 }; 6981 6982 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 6983 void setDataLayoutString() override { 6984 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 6985 } 6986 6987 public: 6988 Mips32EBTargetInfo(const llvm::Triple &Triple) 6989 : Mips32TargetInfoBase(Triple) { 6990 } 6991 void getTargetDefines(const LangOptions &Opts, 6992 MacroBuilder &Builder) const override { 6993 DefineStd(Builder, "MIPSEB", Opts); 6994 Builder.defineMacro("_MIPSEB"); 6995 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 6996 } 6997 }; 6998 6999 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 7000 void setDataLayoutString() override { 7001 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32-S64"; 7002 } 7003 7004 public: 7005 Mips32ELTargetInfo(const llvm::Triple &Triple) 7006 : Mips32TargetInfoBase(Triple) { 7007 BigEndian = false; 7008 } 7009 void getTargetDefines(const LangOptions &Opts, 7010 MacroBuilder &Builder) const override { 7011 DefineStd(Builder, "MIPSEL", Opts); 7012 Builder.defineMacro("_MIPSEL"); 7013 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 7014 } 7015 }; 7016 7017 class Mips64TargetInfoBase : public MipsTargetInfoBase { 7018 public: 7019 Mips64TargetInfoBase(const llvm::Triple &Triple) 7020 : MipsTargetInfoBase(Triple, "n64", "mips64r2") { 7021 LongDoubleWidth = LongDoubleAlign = 128; 7022 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7023 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 7024 LongDoubleWidth = LongDoubleAlign = 64; 7025 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7026 } 7027 setN64ABITypes(); 7028 SuitableAlign = 128; 7029 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7030 } 7031 7032 void setN64ABITypes() { 7033 LongWidth = LongAlign = 64; 7034 PointerWidth = PointerAlign = 64; 7035 SizeType = UnsignedLong; 7036 PtrDiffType = SignedLong; 7037 Int64Type = SignedLong; 7038 IntMaxType = Int64Type; 7039 } 7040 7041 void setN32ABITypes() { 7042 LongWidth = LongAlign = 32; 7043 PointerWidth = PointerAlign = 32; 7044 SizeType = UnsignedInt; 7045 PtrDiffType = SignedInt; 7046 Int64Type = SignedLongLong; 7047 IntMaxType = Int64Type; 7048 } 7049 7050 bool setABI(const std::string &Name) override { 7051 if (Name == "n32") { 7052 setN32ABITypes(); 7053 ABI = Name; 7054 return true; 7055 } 7056 if (Name == "n64") { 7057 setN64ABITypes(); 7058 ABI = Name; 7059 return true; 7060 } 7061 return false; 7062 } 7063 7064 void getTargetDefines(const LangOptions &Opts, 7065 MacroBuilder &Builder) const override { 7066 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 7067 7068 Builder.defineMacro("__mips", "64"); 7069 Builder.defineMacro("__mips64"); 7070 Builder.defineMacro("__mips64__"); 7071 Builder.defineMacro("_MIPS_ISA", "_MIPS_ISA_MIPS64"); 7072 7073 const std::string& CPUStr = getCPU(); 7074 if (CPUStr == "mips64") 7075 Builder.defineMacro("__mips_isa_rev", "1"); 7076 else if (CPUStr == "mips64r2") 7077 Builder.defineMacro("__mips_isa_rev", "2"); 7078 else if (CPUStr == "mips64r3") 7079 Builder.defineMacro("__mips_isa_rev", "3"); 7080 else if (CPUStr == "mips64r5") 7081 Builder.defineMacro("__mips_isa_rev", "5"); 7082 else if (CPUStr == "mips64r6") 7083 Builder.defineMacro("__mips_isa_rev", "6"); 7084 7085 if (ABI == "n32") { 7086 Builder.defineMacro("__mips_n32"); 7087 Builder.defineMacro("_ABIN32", "2"); 7088 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 7089 } 7090 else if (ABI == "n64") { 7091 Builder.defineMacro("__mips_n64"); 7092 Builder.defineMacro("_ABI64", "3"); 7093 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 7094 } 7095 else 7096 llvm_unreachable("Invalid ABI for Mips64."); 7097 7098 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 7099 } 7100 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7101 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 7102 { { "at" }, "$1" }, 7103 { { "v0" }, "$2" }, 7104 { { "v1" }, "$3" }, 7105 { { "a0" }, "$4" }, 7106 { { "a1" }, "$5" }, 7107 { { "a2" }, "$6" }, 7108 { { "a3" }, "$7" }, 7109 { { "a4" }, "$8" }, 7110 { { "a5" }, "$9" }, 7111 { { "a6" }, "$10" }, 7112 { { "a7" }, "$11" }, 7113 { { "t0" }, "$12" }, 7114 { { "t1" }, "$13" }, 7115 { { "t2" }, "$14" }, 7116 { { "t3" }, "$15" }, 7117 { { "s0" }, "$16" }, 7118 { { "s1" }, "$17" }, 7119 { { "s2" }, "$18" }, 7120 { { "s3" }, "$19" }, 7121 { { "s4" }, "$20" }, 7122 { { "s5" }, "$21" }, 7123 { { "s6" }, "$22" }, 7124 { { "s7" }, "$23" }, 7125 { { "t8" }, "$24" }, 7126 { { "t9" }, "$25" }, 7127 { { "k0" }, "$26" }, 7128 { { "k1" }, "$27" }, 7129 { { "gp" }, "$28" }, 7130 { { "sp","$sp" }, "$29" }, 7131 { { "fp","$fp" }, "$30" }, 7132 { { "ra" }, "$31" } 7133 }; 7134 return llvm::makeArrayRef(GCCRegAliases); 7135 } 7136 7137 bool hasInt128Type() const override { return true; } 7138 }; 7139 7140 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 7141 void setDataLayoutString() override { 7142 if (ABI == "n32") 7143 DataLayoutString = "E-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7144 else 7145 DataLayoutString = "E-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7146 7147 } 7148 7149 public: 7150 Mips64EBTargetInfo(const llvm::Triple &Triple) 7151 : Mips64TargetInfoBase(Triple) {} 7152 void getTargetDefines(const LangOptions &Opts, 7153 MacroBuilder &Builder) const override { 7154 DefineStd(Builder, "MIPSEB", Opts); 7155 Builder.defineMacro("_MIPSEB"); 7156 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7157 } 7158 }; 7159 7160 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 7161 void setDataLayoutString() override { 7162 if (ABI == "n32") 7163 DataLayoutString = "e-m:m-p:32:32-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7164 else 7165 DataLayoutString = "e-m:m-i8:8:32-i16:16:32-i64:64-n32:64-S128"; 7166 } 7167 public: 7168 Mips64ELTargetInfo(const llvm::Triple &Triple) 7169 : Mips64TargetInfoBase(Triple) { 7170 // Default ABI is n64. 7171 BigEndian = false; 7172 } 7173 void getTargetDefines(const LangOptions &Opts, 7174 MacroBuilder &Builder) const override { 7175 DefineStd(Builder, "MIPSEL", Opts); 7176 Builder.defineMacro("_MIPSEL"); 7177 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 7178 } 7179 }; 7180 7181 class PNaClTargetInfo : public TargetInfo { 7182 public: 7183 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7184 BigEndian = false; 7185 this->UserLabelPrefix = ""; 7186 this->LongAlign = 32; 7187 this->LongWidth = 32; 7188 this->PointerAlign = 32; 7189 this->PointerWidth = 32; 7190 this->IntMaxType = TargetInfo::SignedLongLong; 7191 this->Int64Type = TargetInfo::SignedLongLong; 7192 this->DoubleAlign = 64; 7193 this->LongDoubleWidth = 64; 7194 this->LongDoubleAlign = 64; 7195 this->SizeType = TargetInfo::UnsignedInt; 7196 this->PtrDiffType = TargetInfo::SignedInt; 7197 this->IntPtrType = TargetInfo::SignedInt; 7198 this->RegParmMax = 0; // Disallow regparm 7199 } 7200 7201 void getArchDefines(const LangOptions &Opts, MacroBuilder &Builder) const { 7202 Builder.defineMacro("__le32__"); 7203 Builder.defineMacro("__pnacl__"); 7204 } 7205 void getTargetDefines(const LangOptions &Opts, 7206 MacroBuilder &Builder) const override { 7207 getArchDefines(Opts, Builder); 7208 } 7209 bool hasFeature(StringRef Feature) const override { 7210 return Feature == "pnacl"; 7211 } 7212 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7213 BuiltinVaListKind getBuiltinVaListKind() const override { 7214 return TargetInfo::PNaClABIBuiltinVaList; 7215 } 7216 ArrayRef<const char *> getGCCRegNames() const override; 7217 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override; 7218 bool validateAsmConstraint(const char *&Name, 7219 TargetInfo::ConstraintInfo &Info) const override { 7220 return false; 7221 } 7222 7223 const char *getClobbers() const override { 7224 return ""; 7225 } 7226 }; 7227 7228 ArrayRef<const char *> PNaClTargetInfo::getGCCRegNames() const { 7229 return None; 7230 } 7231 7232 ArrayRef<TargetInfo::GCCRegAlias> PNaClTargetInfo::getGCCRegAliases() const { 7233 return None; 7234 } 7235 7236 // We attempt to use PNaCl (le32) frontend and Mips32EL backend. 7237 class NaClMips32ELTargetInfo : public Mips32ELTargetInfo { 7238 public: 7239 NaClMips32ELTargetInfo(const llvm::Triple &Triple) : 7240 Mips32ELTargetInfo(Triple) { 7241 } 7242 7243 BuiltinVaListKind getBuiltinVaListKind() const override { 7244 return TargetInfo::PNaClABIBuiltinVaList; 7245 } 7246 }; 7247 7248 class Le64TargetInfo : public TargetInfo { 7249 static const Builtin::Info BuiltinInfo[]; 7250 7251 public: 7252 Le64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7253 BigEndian = false; 7254 NoAsmVariants = true; 7255 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 7256 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7257 DataLayoutString = "e-m:e-v128:32-v16:16-v32:32-v96:32-n8:16:32:64-S128"; 7258 } 7259 7260 void getTargetDefines(const LangOptions &Opts, 7261 MacroBuilder &Builder) const override { 7262 DefineStd(Builder, "unix", Opts); 7263 defineCPUMacros(Builder, "le64", /*Tuning=*/false); 7264 Builder.defineMacro("__ELF__"); 7265 } 7266 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7267 return llvm::makeArrayRef(BuiltinInfo, 7268 clang::Le64::LastTSBuiltin - Builtin::FirstTSBuiltin); 7269 } 7270 BuiltinVaListKind getBuiltinVaListKind() const override { 7271 return TargetInfo::PNaClABIBuiltinVaList; 7272 } 7273 const char *getClobbers() const override { return ""; } 7274 ArrayRef<const char *> getGCCRegNames() const override { 7275 return None; 7276 } 7277 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7278 return None; 7279 } 7280 bool validateAsmConstraint(const char *&Name, 7281 TargetInfo::ConstraintInfo &Info) const override { 7282 return false; 7283 } 7284 7285 bool hasProtectedVisibility() const override { return false; } 7286 }; 7287 7288 class WebAssemblyTargetInfo : public TargetInfo { 7289 static const Builtin::Info BuiltinInfo[]; 7290 7291 enum SIMDEnum { 7292 NoSIMD, 7293 SIMD128, 7294 } SIMDLevel; 7295 7296 public: 7297 explicit WebAssemblyTargetInfo(const llvm::Triple &T) 7298 : TargetInfo(T), SIMDLevel(NoSIMD) { 7299 BigEndian = false; 7300 NoAsmVariants = true; 7301 SuitableAlign = 128; 7302 LargeArrayMinWidth = 128; 7303 LargeArrayAlign = 128; 7304 SimdDefaultAlign = 128; 7305 SigAtomicType = SignedLong; 7306 LongDoubleWidth = LongDoubleAlign = 128; 7307 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7308 } 7309 7310 protected: 7311 void getTargetDefines(const LangOptions &Opts, 7312 MacroBuilder &Builder) const override { 7313 defineCPUMacros(Builder, "wasm", /*Tuning=*/false); 7314 if (SIMDLevel >= SIMD128) 7315 Builder.defineMacro("__wasm_simd128__"); 7316 } 7317 7318 private: 7319 bool 7320 initFeatureMap(llvm::StringMap<bool> &Features, DiagnosticsEngine &Diags, 7321 StringRef CPU, 7322 const std::vector<std::string> &FeaturesVec) const override { 7323 if (CPU == "bleeding-edge") 7324 Features["simd128"] = true; 7325 return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); 7326 } 7327 bool hasFeature(StringRef Feature) const final { 7328 return llvm::StringSwitch<bool>(Feature) 7329 .Case("simd128", SIMDLevel >= SIMD128) 7330 .Default(false); 7331 } 7332 bool handleTargetFeatures(std::vector<std::string> &Features, 7333 DiagnosticsEngine &Diags) final { 7334 for (const auto &Feature : Features) { 7335 if (Feature == "+simd128") { 7336 SIMDLevel = std::max(SIMDLevel, SIMD128); 7337 continue; 7338 } 7339 if (Feature == "-simd128") { 7340 SIMDLevel = std::min(SIMDLevel, SIMDEnum(SIMD128 - 1)); 7341 continue; 7342 } 7343 7344 Diags.Report(diag::err_opt_not_valid_with_opt) << Feature 7345 << "-target-feature"; 7346 return false; 7347 } 7348 return true; 7349 } 7350 bool setCPU(const std::string &Name) final { 7351 return llvm::StringSwitch<bool>(Name) 7352 .Case("mvp", true) 7353 .Case("bleeding-edge", true) 7354 .Case("generic", true) 7355 .Default(false); 7356 } 7357 ArrayRef<Builtin::Info> getTargetBuiltins() const final { 7358 return llvm::makeArrayRef(BuiltinInfo, 7359 clang::WebAssembly::LastTSBuiltin - Builtin::FirstTSBuiltin); 7360 } 7361 BuiltinVaListKind getBuiltinVaListKind() const final { 7362 return VoidPtrBuiltinVaList; 7363 } 7364 ArrayRef<const char *> getGCCRegNames() const final { 7365 return None; 7366 } 7367 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const final { 7368 return None; 7369 } 7370 bool 7371 validateAsmConstraint(const char *&Name, 7372 TargetInfo::ConstraintInfo &Info) const final { 7373 return false; 7374 } 7375 const char *getClobbers() const final { return ""; } 7376 bool isCLZForZeroUndef() const final { return false; } 7377 bool hasInt128Type() const final { return true; } 7378 IntType getIntTypeByWidth(unsigned BitWidth, 7379 bool IsSigned) const final { 7380 // WebAssembly prefers long long for explicitly 64-bit integers. 7381 return BitWidth == 64 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7382 : TargetInfo::getIntTypeByWidth(BitWidth, IsSigned); 7383 } 7384 IntType getLeastIntTypeByWidth(unsigned BitWidth, 7385 bool IsSigned) const final { 7386 // WebAssembly uses long long for int_least64_t and int_fast64_t. 7387 return BitWidth == 64 7388 ? (IsSigned ? SignedLongLong : UnsignedLongLong) 7389 : TargetInfo::getLeastIntTypeByWidth(BitWidth, IsSigned); 7390 } 7391 }; 7392 7393 const Builtin::Info WebAssemblyTargetInfo::BuiltinInfo[] = { 7394 #define BUILTIN(ID, TYPE, ATTRS) \ 7395 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7396 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7397 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7398 #include "clang/Basic/BuiltinsWebAssembly.def" 7399 }; 7400 7401 class WebAssembly32TargetInfo : public WebAssemblyTargetInfo { 7402 public: 7403 explicit WebAssembly32TargetInfo(const llvm::Triple &T) 7404 : WebAssemblyTargetInfo(T) { 7405 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 7406 DataLayoutString = "e-m:e-p:32:32-i64:64-n32:64-S128"; 7407 } 7408 7409 protected: 7410 void getTargetDefines(const LangOptions &Opts, 7411 MacroBuilder &Builder) const override { 7412 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7413 defineCPUMacros(Builder, "wasm32", /*Tuning=*/false); 7414 } 7415 }; 7416 7417 class WebAssembly64TargetInfo : public WebAssemblyTargetInfo { 7418 public: 7419 explicit WebAssembly64TargetInfo(const llvm::Triple &T) 7420 : WebAssemblyTargetInfo(T) { 7421 LongAlign = LongWidth = 64; 7422 PointerAlign = PointerWidth = 64; 7423 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 7424 DataLayoutString = "e-m:e-p:64:64-i64:64-n32:64-S128"; 7425 } 7426 7427 protected: 7428 void getTargetDefines(const LangOptions &Opts, 7429 MacroBuilder &Builder) const override { 7430 WebAssemblyTargetInfo::getTargetDefines(Opts, Builder); 7431 defineCPUMacros(Builder, "wasm64", /*Tuning=*/false); 7432 } 7433 }; 7434 7435 const Builtin::Info Le64TargetInfo::BuiltinInfo[] = { 7436 #define BUILTIN(ID, TYPE, ATTRS) \ 7437 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7438 #include "clang/Basic/BuiltinsLe64.def" 7439 }; 7440 7441 static const unsigned SPIRAddrSpaceMap[] = { 7442 1, // opencl_global 7443 3, // opencl_local 7444 2, // opencl_constant 7445 4, // opencl_generic 7446 0, // cuda_device 7447 0, // cuda_constant 7448 0 // cuda_shared 7449 }; 7450 class SPIRTargetInfo : public TargetInfo { 7451 public: 7452 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7453 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 7454 "SPIR target must use unknown OS"); 7455 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 7456 "SPIR target must use unknown environment type"); 7457 BigEndian = false; 7458 TLSSupported = false; 7459 LongWidth = LongAlign = 64; 7460 AddrSpaceMap = &SPIRAddrSpaceMap; 7461 UseAddrSpaceMapMangling = true; 7462 // Define available target features 7463 // These must be defined in sorted order! 7464 NoAsmVariants = true; 7465 } 7466 void getTargetDefines(const LangOptions &Opts, 7467 MacroBuilder &Builder) const override { 7468 DefineStd(Builder, "SPIR", Opts); 7469 } 7470 bool hasFeature(StringRef Feature) const override { 7471 return Feature == "spir"; 7472 } 7473 7474 ArrayRef<Builtin::Info> getTargetBuiltins() const override { return None; } 7475 const char *getClobbers() const override { return ""; } 7476 ArrayRef<const char *> getGCCRegNames() const override { return None; } 7477 bool validateAsmConstraint(const char *&Name, 7478 TargetInfo::ConstraintInfo &info) const override { 7479 return true; 7480 } 7481 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7482 return None; 7483 } 7484 BuiltinVaListKind getBuiltinVaListKind() const override { 7485 return TargetInfo::VoidPtrBuiltinVaList; 7486 } 7487 7488 CallingConvCheckResult checkCallingConvention(CallingConv CC) const override { 7489 return (CC == CC_SpirFunction || CC == CC_SpirKernel) ? CCCR_OK 7490 : CCCR_Warning; 7491 } 7492 7493 CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override { 7494 return CC_SpirFunction; 7495 } 7496 }; 7497 7498 class SPIR32TargetInfo : public SPIRTargetInfo { 7499 public: 7500 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7501 PointerWidth = PointerAlign = 32; 7502 SizeType = TargetInfo::UnsignedInt; 7503 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 7504 DataLayoutString = "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-" 7505 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7506 } 7507 void getTargetDefines(const LangOptions &Opts, 7508 MacroBuilder &Builder) const override { 7509 DefineStd(Builder, "SPIR32", Opts); 7510 } 7511 }; 7512 7513 class SPIR64TargetInfo : public SPIRTargetInfo { 7514 public: 7515 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 7516 PointerWidth = PointerAlign = 64; 7517 SizeType = TargetInfo::UnsignedLong; 7518 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 7519 DataLayoutString = "e-i64:64-v16:16-v24:32-v32:32-v48:64-" 7520 "v96:128-v192:256-v256:256-v512:512-v1024:1024"; 7521 } 7522 void getTargetDefines(const LangOptions &Opts, 7523 MacroBuilder &Builder) const override { 7524 DefineStd(Builder, "SPIR64", Opts); 7525 } 7526 }; 7527 7528 class XCoreTargetInfo : public TargetInfo { 7529 static const Builtin::Info BuiltinInfo[]; 7530 public: 7531 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 7532 BigEndian = false; 7533 NoAsmVariants = true; 7534 LongLongAlign = 32; 7535 SuitableAlign = 32; 7536 DoubleAlign = LongDoubleAlign = 32; 7537 SizeType = UnsignedInt; 7538 PtrDiffType = SignedInt; 7539 IntPtrType = SignedInt; 7540 WCharType = UnsignedChar; 7541 WIntType = UnsignedInt; 7542 UseZeroLengthBitfieldAlignment = true; 7543 DataLayoutString = "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i64:32" 7544 "-f64:32-a:0:32-n32"; 7545 } 7546 void getTargetDefines(const LangOptions &Opts, 7547 MacroBuilder &Builder) const override { 7548 Builder.defineMacro("__XS1B__"); 7549 } 7550 ArrayRef<Builtin::Info> getTargetBuiltins() const override { 7551 return llvm::makeArrayRef(BuiltinInfo, 7552 clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin); 7553 } 7554 BuiltinVaListKind getBuiltinVaListKind() const override { 7555 return TargetInfo::VoidPtrBuiltinVaList; 7556 } 7557 const char *getClobbers() const override { 7558 return ""; 7559 } 7560 ArrayRef<const char *> getGCCRegNames() const override { 7561 static const char * const GCCRegNames[] = { 7562 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 7563 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 7564 }; 7565 return llvm::makeArrayRef(GCCRegNames); 7566 } 7567 ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override { 7568 return None; 7569 } 7570 bool validateAsmConstraint(const char *&Name, 7571 TargetInfo::ConstraintInfo &Info) const override { 7572 return false; 7573 } 7574 int getEHDataRegisterNumber(unsigned RegNo) const override { 7575 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister 7576 return (RegNo < 2)? RegNo : -1; 7577 } 7578 bool allowsLargerPreferedTypeAlignment() const override { 7579 return false; 7580 } 7581 }; 7582 7583 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 7584 #define BUILTIN(ID, TYPE, ATTRS) \ 7585 { #ID, TYPE, ATTRS, nullptr, ALL_LANGUAGES, nullptr }, 7586 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) \ 7587 { #ID, TYPE, ATTRS, HEADER, ALL_LANGUAGES, nullptr }, 7588 #include "clang/Basic/BuiltinsXCore.def" 7589 }; 7590 7591 // x86_32 Android target 7592 class AndroidX86_32TargetInfo : public LinuxTargetInfo<X86_32TargetInfo> { 7593 public: 7594 AndroidX86_32TargetInfo(const llvm::Triple &Triple) 7595 : LinuxTargetInfo<X86_32TargetInfo>(Triple) { 7596 SuitableAlign = 32; 7597 LongDoubleWidth = 64; 7598 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 7599 } 7600 }; 7601 7602 // x86_64 Android target 7603 class AndroidX86_64TargetInfo : public LinuxTargetInfo<X86_64TargetInfo> { 7604 public: 7605 AndroidX86_64TargetInfo(const llvm::Triple &Triple) 7606 : LinuxTargetInfo<X86_64TargetInfo>(Triple) { 7607 LongDoubleFormat = &llvm::APFloat::IEEEquad; 7608 } 7609 7610 bool useFloat128ManglingForLongDouble() const override { 7611 return true; 7612 } 7613 }; 7614 } // end anonymous namespace 7615 7616 //===----------------------------------------------------------------------===// 7617 // Driver code 7618 //===----------------------------------------------------------------------===// 7619 7620 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 7621 llvm::Triple::OSType os = Triple.getOS(); 7622 7623 switch (Triple.getArch()) { 7624 default: 7625 return nullptr; 7626 7627 case llvm::Triple::xcore: 7628 return new XCoreTargetInfo(Triple); 7629 7630 case llvm::Triple::hexagon: 7631 return new HexagonTargetInfo(Triple); 7632 7633 case llvm::Triple::aarch64: 7634 if (Triple.isOSDarwin()) 7635 return new DarwinAArch64TargetInfo(Triple); 7636 7637 switch (os) { 7638 case llvm::Triple::CloudABI: 7639 return new CloudABITargetInfo<AArch64leTargetInfo>(Triple); 7640 case llvm::Triple::FreeBSD: 7641 return new FreeBSDTargetInfo<AArch64leTargetInfo>(Triple); 7642 case llvm::Triple::Linux: 7643 return new LinuxTargetInfo<AArch64leTargetInfo>(Triple); 7644 case llvm::Triple::NetBSD: 7645 return new NetBSDTargetInfo<AArch64leTargetInfo>(Triple); 7646 default: 7647 return new AArch64leTargetInfo(Triple); 7648 } 7649 7650 case llvm::Triple::aarch64_be: 7651 switch (os) { 7652 case llvm::Triple::FreeBSD: 7653 return new FreeBSDTargetInfo<AArch64beTargetInfo>(Triple); 7654 case llvm::Triple::Linux: 7655 return new LinuxTargetInfo<AArch64beTargetInfo>(Triple); 7656 case llvm::Triple::NetBSD: 7657 return new NetBSDTargetInfo<AArch64beTargetInfo>(Triple); 7658 default: 7659 return new AArch64beTargetInfo(Triple); 7660 } 7661 7662 case llvm::Triple::arm: 7663 case llvm::Triple::thumb: 7664 if (Triple.isOSBinFormatMachO()) 7665 return new DarwinARMTargetInfo(Triple); 7666 7667 switch (os) { 7668 case llvm::Triple::Linux: 7669 return new LinuxTargetInfo<ARMleTargetInfo>(Triple); 7670 case llvm::Triple::FreeBSD: 7671 return new FreeBSDTargetInfo<ARMleTargetInfo>(Triple); 7672 case llvm::Triple::NetBSD: 7673 return new NetBSDTargetInfo<ARMleTargetInfo>(Triple); 7674 case llvm::Triple::OpenBSD: 7675 return new OpenBSDTargetInfo<ARMleTargetInfo>(Triple); 7676 case llvm::Triple::Bitrig: 7677 return new BitrigTargetInfo<ARMleTargetInfo>(Triple); 7678 case llvm::Triple::RTEMS: 7679 return new RTEMSTargetInfo<ARMleTargetInfo>(Triple); 7680 case llvm::Triple::NaCl: 7681 return new NaClTargetInfo<ARMleTargetInfo>(Triple); 7682 case llvm::Triple::Win32: 7683 switch (Triple.getEnvironment()) { 7684 case llvm::Triple::Cygnus: 7685 return new CygwinARMTargetInfo(Triple); 7686 case llvm::Triple::GNU: 7687 return new MinGWARMTargetInfo(Triple); 7688 case llvm::Triple::Itanium: 7689 return new ItaniumWindowsARMleTargetInfo(Triple); 7690 case llvm::Triple::MSVC: 7691 default: // Assume MSVC for unknown environments 7692 return new MicrosoftARMleTargetInfo(Triple); 7693 } 7694 default: 7695 return new ARMleTargetInfo(Triple); 7696 } 7697 7698 case llvm::Triple::armeb: 7699 case llvm::Triple::thumbeb: 7700 if (Triple.isOSDarwin()) 7701 return new DarwinARMTargetInfo(Triple); 7702 7703 switch (os) { 7704 case llvm::Triple::Linux: 7705 return new LinuxTargetInfo<ARMbeTargetInfo>(Triple); 7706 case llvm::Triple::FreeBSD: 7707 return new FreeBSDTargetInfo<ARMbeTargetInfo>(Triple); 7708 case llvm::Triple::NetBSD: 7709 return new NetBSDTargetInfo<ARMbeTargetInfo>(Triple); 7710 case llvm::Triple::OpenBSD: 7711 return new OpenBSDTargetInfo<ARMbeTargetInfo>(Triple); 7712 case llvm::Triple::Bitrig: 7713 return new BitrigTargetInfo<ARMbeTargetInfo>(Triple); 7714 case llvm::Triple::RTEMS: 7715 return new RTEMSTargetInfo<ARMbeTargetInfo>(Triple); 7716 case llvm::Triple::NaCl: 7717 return new NaClTargetInfo<ARMbeTargetInfo>(Triple); 7718 default: 7719 return new ARMbeTargetInfo(Triple); 7720 } 7721 7722 case llvm::Triple::bpfeb: 7723 case llvm::Triple::bpfel: 7724 return new BPFTargetInfo(Triple); 7725 7726 case llvm::Triple::msp430: 7727 return new MSP430TargetInfo(Triple); 7728 7729 case llvm::Triple::mips: 7730 switch (os) { 7731 case llvm::Triple::Linux: 7732 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 7733 case llvm::Triple::RTEMS: 7734 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 7735 case llvm::Triple::FreeBSD: 7736 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7737 case llvm::Triple::NetBSD: 7738 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 7739 default: 7740 return new Mips32EBTargetInfo(Triple); 7741 } 7742 7743 case llvm::Triple::mipsel: 7744 switch (os) { 7745 case llvm::Triple::Linux: 7746 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 7747 case llvm::Triple::RTEMS: 7748 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 7749 case llvm::Triple::FreeBSD: 7750 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7751 case llvm::Triple::NetBSD: 7752 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 7753 case llvm::Triple::NaCl: 7754 return new NaClTargetInfo<NaClMips32ELTargetInfo>(Triple); 7755 default: 7756 return new Mips32ELTargetInfo(Triple); 7757 } 7758 7759 case llvm::Triple::mips64: 7760 switch (os) { 7761 case llvm::Triple::Linux: 7762 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 7763 case llvm::Triple::RTEMS: 7764 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 7765 case llvm::Triple::FreeBSD: 7766 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7767 case llvm::Triple::NetBSD: 7768 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7769 case llvm::Triple::OpenBSD: 7770 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 7771 default: 7772 return new Mips64EBTargetInfo(Triple); 7773 } 7774 7775 case llvm::Triple::mips64el: 7776 switch (os) { 7777 case llvm::Triple::Linux: 7778 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 7779 case llvm::Triple::RTEMS: 7780 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 7781 case llvm::Triple::FreeBSD: 7782 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7783 case llvm::Triple::NetBSD: 7784 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7785 case llvm::Triple::OpenBSD: 7786 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 7787 default: 7788 return new Mips64ELTargetInfo(Triple); 7789 } 7790 7791 case llvm::Triple::le32: 7792 switch (os) { 7793 case llvm::Triple::NaCl: 7794 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 7795 default: 7796 return nullptr; 7797 } 7798 7799 case llvm::Triple::le64: 7800 return new Le64TargetInfo(Triple); 7801 7802 case llvm::Triple::ppc: 7803 if (Triple.isOSDarwin()) 7804 return new DarwinPPC32TargetInfo(Triple); 7805 switch (os) { 7806 case llvm::Triple::Linux: 7807 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 7808 case llvm::Triple::FreeBSD: 7809 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 7810 case llvm::Triple::NetBSD: 7811 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 7812 case llvm::Triple::OpenBSD: 7813 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 7814 case llvm::Triple::RTEMS: 7815 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 7816 default: 7817 return new PPC32TargetInfo(Triple); 7818 } 7819 7820 case llvm::Triple::ppc64: 7821 if (Triple.isOSDarwin()) 7822 return new DarwinPPC64TargetInfo(Triple); 7823 switch (os) { 7824 case llvm::Triple::Linux: 7825 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7826 case llvm::Triple::Lv2: 7827 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 7828 case llvm::Triple::FreeBSD: 7829 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 7830 case llvm::Triple::NetBSD: 7831 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7832 default: 7833 return new PPC64TargetInfo(Triple); 7834 } 7835 7836 case llvm::Triple::ppc64le: 7837 switch (os) { 7838 case llvm::Triple::Linux: 7839 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 7840 case llvm::Triple::NetBSD: 7841 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 7842 default: 7843 return new PPC64TargetInfo(Triple); 7844 } 7845 7846 case llvm::Triple::nvptx: 7847 return new NVPTX32TargetInfo(Triple); 7848 case llvm::Triple::nvptx64: 7849 return new NVPTX64TargetInfo(Triple); 7850 7851 case llvm::Triple::amdgcn: 7852 case llvm::Triple::r600: 7853 return new AMDGPUTargetInfo(Triple); 7854 7855 case llvm::Triple::sparc: 7856 switch (os) { 7857 case llvm::Triple::Linux: 7858 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 7859 case llvm::Triple::Solaris: 7860 return new SolarisTargetInfo<SparcV8TargetInfo>(Triple); 7861 case llvm::Triple::NetBSD: 7862 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 7863 case llvm::Triple::OpenBSD: 7864 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 7865 case llvm::Triple::RTEMS: 7866 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 7867 default: 7868 return new SparcV8TargetInfo(Triple); 7869 } 7870 7871 // The 'sparcel' architecture copies all the above cases except for Solaris. 7872 case llvm::Triple::sparcel: 7873 switch (os) { 7874 case llvm::Triple::Linux: 7875 return new LinuxTargetInfo<SparcV8elTargetInfo>(Triple); 7876 case llvm::Triple::NetBSD: 7877 return new NetBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7878 case llvm::Triple::OpenBSD: 7879 return new OpenBSDTargetInfo<SparcV8elTargetInfo>(Triple); 7880 case llvm::Triple::RTEMS: 7881 return new RTEMSTargetInfo<SparcV8elTargetInfo>(Triple); 7882 default: 7883 return new SparcV8elTargetInfo(Triple); 7884 } 7885 7886 case llvm::Triple::sparcv9: 7887 switch (os) { 7888 case llvm::Triple::Linux: 7889 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 7890 case llvm::Triple::Solaris: 7891 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 7892 case llvm::Triple::NetBSD: 7893 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 7894 case llvm::Triple::OpenBSD: 7895 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 7896 case llvm::Triple::FreeBSD: 7897 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 7898 default: 7899 return new SparcV9TargetInfo(Triple); 7900 } 7901 7902 case llvm::Triple::systemz: 7903 switch (os) { 7904 case llvm::Triple::Linux: 7905 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 7906 default: 7907 return new SystemZTargetInfo(Triple); 7908 } 7909 7910 case llvm::Triple::tce: 7911 return new TCETargetInfo(Triple); 7912 7913 case llvm::Triple::x86: 7914 if (Triple.isOSDarwin()) 7915 return new DarwinI386TargetInfo(Triple); 7916 7917 switch (os) { 7918 case llvm::Triple::CloudABI: 7919 return new CloudABITargetInfo<X86_32TargetInfo>(Triple); 7920 case llvm::Triple::Linux: { 7921 switch (Triple.getEnvironment()) { 7922 default: 7923 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 7924 case llvm::Triple::Android: 7925 return new AndroidX86_32TargetInfo(Triple); 7926 } 7927 } 7928 case llvm::Triple::DragonFly: 7929 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 7930 case llvm::Triple::NetBSD: 7931 return new NetBSDI386TargetInfo(Triple); 7932 case llvm::Triple::OpenBSD: 7933 return new OpenBSDI386TargetInfo(Triple); 7934 case llvm::Triple::Bitrig: 7935 return new BitrigI386TargetInfo(Triple); 7936 case llvm::Triple::FreeBSD: 7937 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7938 case llvm::Triple::KFreeBSD: 7939 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 7940 case llvm::Triple::Minix: 7941 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 7942 case llvm::Triple::Solaris: 7943 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 7944 case llvm::Triple::Win32: { 7945 switch (Triple.getEnvironment()) { 7946 case llvm::Triple::Cygnus: 7947 return new CygwinX86_32TargetInfo(Triple); 7948 case llvm::Triple::GNU: 7949 return new MinGWX86_32TargetInfo(Triple); 7950 case llvm::Triple::Itanium: 7951 case llvm::Triple::MSVC: 7952 default: // Assume MSVC for unknown environments 7953 return new MicrosoftX86_32TargetInfo(Triple); 7954 } 7955 } 7956 case llvm::Triple::Haiku: 7957 return new HaikuX86_32TargetInfo(Triple); 7958 case llvm::Triple::RTEMS: 7959 return new RTEMSX86_32TargetInfo(Triple); 7960 case llvm::Triple::NaCl: 7961 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 7962 case llvm::Triple::ELFIAMCU: 7963 return new MCUX86_32TargetInfo(Triple); 7964 default: 7965 return new X86_32TargetInfo(Triple); 7966 } 7967 7968 case llvm::Triple::x86_64: 7969 if (Triple.isOSDarwin() || Triple.isOSBinFormatMachO()) 7970 return new DarwinX86_64TargetInfo(Triple); 7971 7972 switch (os) { 7973 case llvm::Triple::CloudABI: 7974 return new CloudABITargetInfo<X86_64TargetInfo>(Triple); 7975 case llvm::Triple::Linux: { 7976 switch (Triple.getEnvironment()) { 7977 default: 7978 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 7979 case llvm::Triple::Android: 7980 return new AndroidX86_64TargetInfo(Triple); 7981 } 7982 } 7983 case llvm::Triple::DragonFly: 7984 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 7985 case llvm::Triple::NetBSD: 7986 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 7987 case llvm::Triple::OpenBSD: 7988 return new OpenBSDX86_64TargetInfo(Triple); 7989 case llvm::Triple::Bitrig: 7990 return new BitrigX86_64TargetInfo(Triple); 7991 case llvm::Triple::FreeBSD: 7992 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7993 case llvm::Triple::KFreeBSD: 7994 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 7995 case llvm::Triple::Solaris: 7996 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 7997 case llvm::Triple::Win32: { 7998 switch (Triple.getEnvironment()) { 7999 case llvm::Triple::Cygnus: 8000 return new CygwinX86_64TargetInfo(Triple); 8001 case llvm::Triple::GNU: 8002 return new MinGWX86_64TargetInfo(Triple); 8003 case llvm::Triple::MSVC: 8004 default: // Assume MSVC for unknown environments 8005 return new MicrosoftX86_64TargetInfo(Triple); 8006 } 8007 } 8008 case llvm::Triple::NaCl: 8009 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 8010 case llvm::Triple::PS4: 8011 return new PS4OSTargetInfo<X86_64TargetInfo>(Triple); 8012 default: 8013 return new X86_64TargetInfo(Triple); 8014 } 8015 8016 case llvm::Triple::spir: { 8017 if (Triple.getOS() != llvm::Triple::UnknownOS || 8018 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8019 return nullptr; 8020 return new SPIR32TargetInfo(Triple); 8021 } 8022 case llvm::Triple::spir64: { 8023 if (Triple.getOS() != llvm::Triple::UnknownOS || 8024 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 8025 return nullptr; 8026 return new SPIR64TargetInfo(Triple); 8027 } 8028 case llvm::Triple::wasm32: 8029 if (!(Triple == llvm::Triple("wasm32-unknown-unknown"))) 8030 return nullptr; 8031 return new WebAssemblyOSTargetInfo<WebAssembly32TargetInfo>(Triple); 8032 case llvm::Triple::wasm64: 8033 if (!(Triple == llvm::Triple("wasm64-unknown-unknown"))) 8034 return nullptr; 8035 return new WebAssemblyOSTargetInfo<WebAssembly64TargetInfo>(Triple); 8036 } 8037 } 8038 8039 /// CreateTargetInfo - Return the target info object for the specified target 8040 /// options. 8041 TargetInfo * 8042 TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 8043 const std::shared_ptr<TargetOptions> &Opts) { 8044 llvm::Triple Triple(Opts->Triple); 8045 8046 // Construct the target 8047 std::unique_ptr<TargetInfo> Target(AllocateTarget(Triple)); 8048 if (!Target) { 8049 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 8050 return nullptr; 8051 } 8052 Target->TargetOpts = Opts; 8053 8054 // Set the target CPU if specified. 8055 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 8056 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 8057 return nullptr; 8058 } 8059 8060 // Set the target ABI if specified. 8061 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 8062 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 8063 return nullptr; 8064 } 8065 8066 // Set the fp math unit. 8067 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 8068 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 8069 return nullptr; 8070 } 8071 8072 // Compute the default target features, we need the target to handle this 8073 // because features may have dependencies on one another. 8074 llvm::StringMap<bool> Features; 8075 if (!Target->initFeatureMap(Features, Diags, Opts->CPU, 8076 Opts->FeaturesAsWritten)) 8077 return nullptr; 8078 8079 // Add the features to the compile options. 8080 Opts->Features.clear(); 8081 for (const auto &F : Features) 8082 Opts->Features.push_back((F.getValue() ? "+" : "-") + F.getKey().str()); 8083 8084 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 8085 return nullptr; 8086 8087 return Target.release(); 8088 } 8089